2006.190.07:24:50.04:Log Opened: Mark IV Field System Version 9.7.7 2006.190.07:24:50.09:location,TSUKUB32,-140.09,36.10,61.0 2006.190.07:24:50.09:horizon1,0.,5.,360. 2006.190.07:24:50.10:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.190.07:24:50.10:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.190.07:24:50.10:drivev11,330,270,no 2006.190.07:24:50.11:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.190.07:24:50.11:drivev13,15.000,268,10.000,10.000,10.000 2006.190.07:24:50.11:drivev21,330,270,no 2006.190.07:24:50.12:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.190.07:24:50.12:drivev23,15.000,268,10.000,10.000,10.000 2006.190.07:24:50.13:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.190.07:24:50.18:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.190.07:24:50.18:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.190.07:24:50.19:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.190.07:24:50.19:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.190.07:24:50.19:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.190.07:24:50.20:time,-0.364,101.533,rate 2006.190.07:24:50.20:flagr,200 2006.190.07:24:50.21:proc=k06190ts 2006.190.07:24:50.21:" k06190 2006 tsukub32 t ts 2006.190.07:24:50.21:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.190.07:24:50.27:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.190.07:24:50.27:" 108 tsukub32 14 17400 2006.190.07:24:50.27:" drudg version 050216 compiled under fs 9.7.07 2006.190.07:24:50.28:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.190.07:24:50.28:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.190.07:24:50.31:"source=azel,0d,88d 2006.190.07:24:50.35:"!+2m 2006.190.07:24:50.36:scan_name=190-0730,k06190,60 2006.190.07:24:50.36:source=3c371,180650.68,694928.1,2000.0,ccw 2006.190.07:24:50.37#antcn#PM 1 00019 2005 228 00 22 31 00 2006.190.07:24:50.37#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.190.07:24:50.37#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.190.07:24:50.37#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.190.07:24:50.37#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.190.07:24:50.37#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.190.07:24:51.13#flagr#flagr/antenna,new-source 2006.190.07:24:51.14:ready_k5 2006.190.07:24:51.14&ready_k5/obsinfo=st 2006.190.07:24:51.15&ready_k5/autoobs=1 2006.190.07:24:51.15&ready_k5/autoobs=2 2006.190.07:24:51.15&ready_k5/autoobs=3 2006.190.07:24:51.16&ready_k5/autoobs=4 2006.190.07:24:51.16&ready_k5/obsinfo 2006.190.07:24:51.17/obsinfo=st/error_log.tmp was not found (or not removed). 2006.190.07:24:54.39/autoobs//k5ts1/ autoobs started! 2006.190.07:24:57.14#trakl#Source acquired 2006.190.07:24:57.54/autoobs//k5ts2/ autoobs started! 2006.190.07:24:58.14#flagr#flagr/antenna,acquired 2006.190.07:25:00.67/autoobs//k5ts3/ autoobs started! 2006.190.07:25:03.80/autoobs//k5ts4/ autoobs started! 2006.190.07:25:03.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:25:03.83:4f8m12a=1 2006.190.07:25:03.83&4f8m12a/xlog=on 2006.190.07:25:03.83&4f8m12a/echo=on 2006.190.07:25:03.83&4f8m12a/pcalon 2006.190.07:25:03.83&4f8m12a/"tpicd=stop 2006.190.07:25:03.83&4f8m12a/vc4f8 2006.190.07:25:03.83&4f8m12a/ifd4f 2006.190.07:25:03.83&4f8m12a/"form=m,16.000,1:2 2006.190.07:25:03.83&4f8m12a/"tpicd 2006.190.07:25:03.83&4f8m12a/echo=off 2006.190.07:25:03.83&4f8m12a/xlog=off 2006.190.07:25:03.83$4f8m12a/echo=on 2006.190.07:25:03.83$4f8m12a/pcalon 2006.190.07:25:03.83&pcalon/"no phase cal control is implemented here 2006.190.07:25:03.83$pcalon/"no phase cal control is implemented here 2006.190.07:25:03.83$4f8m12a/"tpicd=stop 2006.190.07:25:03.83$4f8m12a/vc4f8 2006.190.07:25:03.83&vc4f8/valo=1,532.99 2006.190.07:25:03.83&vc4f8/va=1,8 2006.190.07:25:03.83&vc4f8/valo=2,572.99 2006.190.07:25:03.83&vc4f8/va=2,7 2006.190.07:25:03.83&vc4f8/valo=3,672.99 2006.190.07:25:03.83&vc4f8/va=3,6 2006.190.07:25:03.83&vc4f8/valo=4,832.99 2006.190.07:25:03.83&vc4f8/va=4,7 2006.190.07:25:03.83&vc4f8/valo=5,652.99 2006.190.07:25:03.83&vc4f8/va=5,7 2006.190.07:25:03.83&vc4f8/valo=6,772.99 2006.190.07:25:03.83&vc4f8/va=6,6 2006.190.07:25:03.83&vc4f8/valo=7,832.99 2006.190.07:25:03.83&vc4f8/va=7,6 2006.190.07:25:03.83&vc4f8/valo=8,852.99 2006.190.07:25:03.83&vc4f8/va=8,6 2006.190.07:25:03.83&vc4f8/vblo=1,632.99 2006.190.07:25:03.83&vc4f8/vb=1,4 2006.190.07:25:03.83&vc4f8/vblo=2,640.99 2006.190.07:25:03.83&vc4f8/vb=2,4 2006.190.07:25:03.83&vc4f8/vblo=3,656.99 2006.190.07:25:03.83&vc4f8/vb=3,4 2006.190.07:25:03.83&vc4f8/vblo=4,712.99 2006.190.07:25:03.83&vc4f8/vb=4,4 2006.190.07:25:03.83&vc4f8/vblo=5,744.99 2006.190.07:25:03.83&vc4f8/vb=5,4 2006.190.07:25:03.83&vc4f8/vblo=6,752.99 2006.190.07:25:03.83&vc4f8/vb=6,4 2006.190.07:25:03.83&vc4f8/vabw=wide 2006.190.07:25:03.83&vc4f8/vbbw=wide 2006.190.07:25:03.83$vc4f8/valo=1,532.99 2006.190.07:25:03.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.07:25:03.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.07:25:03.83#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:03.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:03.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:03.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:03.83#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:25:03.83#ibcon#first serial, iclass 39, count 0 2006.190.07:25:03.83#ibcon#enter sib2, iclass 39, count 0 2006.190.07:25:03.83#ibcon#flushed, iclass 39, count 0 2006.190.07:25:03.83#ibcon#about to write, iclass 39, count 0 2006.190.07:25:03.83#ibcon#wrote, iclass 39, count 0 2006.190.07:25:03.83#ibcon#about to read 3, iclass 39, count 0 2006.190.07:25:03.84#ibcon#read 3, iclass 39, count 0 2006.190.07:25:03.84#ibcon#about to read 4, iclass 39, count 0 2006.190.07:25:03.84#ibcon#read 4, iclass 39, count 0 2006.190.07:25:03.84#ibcon#about to read 5, iclass 39, count 0 2006.190.07:25:03.84#ibcon#read 5, iclass 39, count 0 2006.190.07:25:03.84#ibcon#about to read 6, iclass 39, count 0 2006.190.07:25:03.84#ibcon#read 6, iclass 39, count 0 2006.190.07:25:03.84#ibcon#end of sib2, iclass 39, count 0 2006.190.07:25:03.84#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:25:03.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:25:03.84#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:25:03.84#ibcon#*before write, iclass 39, count 0 2006.190.07:25:03.84#ibcon#enter sib2, iclass 39, count 0 2006.190.07:25:03.84#ibcon#flushed, iclass 39, count 0 2006.190.07:25:03.84#ibcon#about to write, iclass 39, count 0 2006.190.07:25:03.84#ibcon#wrote, iclass 39, count 0 2006.190.07:25:03.84#ibcon#about to read 3, iclass 39, count 0 2006.190.07:25:03.89#ibcon#read 3, iclass 39, count 0 2006.190.07:25:03.89#ibcon#about to read 4, iclass 39, count 0 2006.190.07:25:03.89#ibcon#read 4, iclass 39, count 0 2006.190.07:25:03.89#ibcon#about to read 5, iclass 39, count 0 2006.190.07:25:03.89#ibcon#read 5, iclass 39, count 0 2006.190.07:25:03.89#ibcon#about to read 6, iclass 39, count 0 2006.190.07:25:03.89#ibcon#read 6, iclass 39, count 0 2006.190.07:25:03.89#ibcon#end of sib2, iclass 39, count 0 2006.190.07:25:03.89#ibcon#*after write, iclass 39, count 0 2006.190.07:25:03.89#ibcon#*before return 0, iclass 39, count 0 2006.190.07:25:03.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:03.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:03.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:25:03.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:25:03.89$vc4f8/va=1,8 2006.190.07:25:03.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.07:25:03.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.07:25:03.89#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:03.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:03.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:03.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:03.89#ibcon#enter wrdev, iclass 3, count 2 2006.190.07:25:03.89#ibcon#first serial, iclass 3, count 2 2006.190.07:25:03.89#ibcon#enter sib2, iclass 3, count 2 2006.190.07:25:03.89#ibcon#flushed, iclass 3, count 2 2006.190.07:25:03.89#ibcon#about to write, iclass 3, count 2 2006.190.07:25:03.89#ibcon#wrote, iclass 3, count 2 2006.190.07:25:03.89#ibcon#about to read 3, iclass 3, count 2 2006.190.07:25:03.91#ibcon#read 3, iclass 3, count 2 2006.190.07:25:03.91#ibcon#about to read 4, iclass 3, count 2 2006.190.07:25:03.91#ibcon#read 4, iclass 3, count 2 2006.190.07:25:03.91#ibcon#about to read 5, iclass 3, count 2 2006.190.07:25:03.91#ibcon#read 5, iclass 3, count 2 2006.190.07:25:03.91#ibcon#about to read 6, iclass 3, count 2 2006.190.07:25:03.91#ibcon#read 6, iclass 3, count 2 2006.190.07:25:03.91#ibcon#end of sib2, iclass 3, count 2 2006.190.07:25:03.91#ibcon#*mode == 0, iclass 3, count 2 2006.190.07:25:03.91#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.07:25:03.91#ibcon#[25=AT01-08\r\n] 2006.190.07:25:03.91#ibcon#*before write, iclass 3, count 2 2006.190.07:25:03.91#ibcon#enter sib2, iclass 3, count 2 2006.190.07:25:03.91#ibcon#flushed, iclass 3, count 2 2006.190.07:25:03.91#ibcon#about to write, iclass 3, count 2 2006.190.07:25:03.91#ibcon#wrote, iclass 3, count 2 2006.190.07:25:03.91#ibcon#about to read 3, iclass 3, count 2 2006.190.07:25:03.95#ibcon#read 3, iclass 3, count 2 2006.190.07:25:03.95#ibcon#about to read 4, iclass 3, count 2 2006.190.07:25:03.95#ibcon#read 4, iclass 3, count 2 2006.190.07:25:03.95#ibcon#about to read 5, iclass 3, count 2 2006.190.07:25:03.95#ibcon#read 5, iclass 3, count 2 2006.190.07:25:03.95#ibcon#about to read 6, iclass 3, count 2 2006.190.07:25:03.95#ibcon#read 6, iclass 3, count 2 2006.190.07:25:03.95#ibcon#end of sib2, iclass 3, count 2 2006.190.07:25:03.95#ibcon#*after write, iclass 3, count 2 2006.190.07:25:03.95#ibcon#*before return 0, iclass 3, count 2 2006.190.07:25:03.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:03.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:03.95#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.07:25:03.95#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:03.95#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:04.07#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:04.07#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:04.07#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:25:04.07#ibcon#first serial, iclass 3, count 0 2006.190.07:25:04.07#ibcon#enter sib2, iclass 3, count 0 2006.190.07:25:04.07#ibcon#flushed, iclass 3, count 0 2006.190.07:25:04.07#ibcon#about to write, iclass 3, count 0 2006.190.07:25:04.07#ibcon#wrote, iclass 3, count 0 2006.190.07:25:04.07#ibcon#about to read 3, iclass 3, count 0 2006.190.07:25:04.08#ibcon#read 3, iclass 3, count 0 2006.190.07:25:04.08#ibcon#about to read 4, iclass 3, count 0 2006.190.07:25:04.08#ibcon#read 4, iclass 3, count 0 2006.190.07:25:04.08#ibcon#about to read 5, iclass 3, count 0 2006.190.07:25:04.08#ibcon#read 5, iclass 3, count 0 2006.190.07:25:04.08#ibcon#about to read 6, iclass 3, count 0 2006.190.07:25:04.08#ibcon#read 6, iclass 3, count 0 2006.190.07:25:04.08#ibcon#end of sib2, iclass 3, count 0 2006.190.07:25:04.08#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:25:04.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:25:04.08#ibcon#[25=USB\r\n] 2006.190.07:25:04.08#ibcon#*before write, iclass 3, count 0 2006.190.07:25:04.08#ibcon#enter sib2, iclass 3, count 0 2006.190.07:25:04.08#ibcon#flushed, iclass 3, count 0 2006.190.07:25:04.08#ibcon#about to write, iclass 3, count 0 2006.190.07:25:04.08#ibcon#wrote, iclass 3, count 0 2006.190.07:25:04.08#ibcon#about to read 3, iclass 3, count 0 2006.190.07:25:04.11#ibcon#read 3, iclass 3, count 0 2006.190.07:25:04.11#ibcon#about to read 4, iclass 3, count 0 2006.190.07:25:04.11#ibcon#read 4, iclass 3, count 0 2006.190.07:25:04.11#ibcon#about to read 5, iclass 3, count 0 2006.190.07:25:04.11#ibcon#read 5, iclass 3, count 0 2006.190.07:25:04.11#ibcon#about to read 6, iclass 3, count 0 2006.190.07:25:04.11#ibcon#read 6, iclass 3, count 0 2006.190.07:25:04.11#ibcon#end of sib2, iclass 3, count 0 2006.190.07:25:04.11#ibcon#*after write, iclass 3, count 0 2006.190.07:25:04.11#ibcon#*before return 0, iclass 3, count 0 2006.190.07:25:04.11#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:04.11#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:04.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:25:04.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:25:04.11$vc4f8/valo=2,572.99 2006.190.07:25:04.11#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.07:25:04.11#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.07:25:04.11#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:04.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:04.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:04.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:04.11#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:25:04.11#ibcon#first serial, iclass 5, count 0 2006.190.07:25:04.11#ibcon#enter sib2, iclass 5, count 0 2006.190.07:25:04.11#ibcon#flushed, iclass 5, count 0 2006.190.07:25:04.11#ibcon#about to write, iclass 5, count 0 2006.190.07:25:04.11#ibcon#wrote, iclass 5, count 0 2006.190.07:25:04.11#ibcon#about to read 3, iclass 5, count 0 2006.190.07:25:04.13#ibcon#read 3, iclass 5, count 0 2006.190.07:25:04.13#ibcon#about to read 4, iclass 5, count 0 2006.190.07:25:04.13#ibcon#read 4, iclass 5, count 0 2006.190.07:25:04.13#ibcon#about to read 5, iclass 5, count 0 2006.190.07:25:04.13#ibcon#read 5, iclass 5, count 0 2006.190.07:25:04.13#ibcon#about to read 6, iclass 5, count 0 2006.190.07:25:04.13#ibcon#read 6, iclass 5, count 0 2006.190.07:25:04.13#ibcon#end of sib2, iclass 5, count 0 2006.190.07:25:04.13#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:25:04.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:25:04.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:25:04.13#ibcon#*before write, iclass 5, count 0 2006.190.07:25:04.13#ibcon#enter sib2, iclass 5, count 0 2006.190.07:25:04.13#ibcon#flushed, iclass 5, count 0 2006.190.07:25:04.13#ibcon#about to write, iclass 5, count 0 2006.190.07:25:04.13#ibcon#wrote, iclass 5, count 0 2006.190.07:25:04.13#ibcon#about to read 3, iclass 5, count 0 2006.190.07:25:04.17#ibcon#read 3, iclass 5, count 0 2006.190.07:25:04.17#ibcon#about to read 4, iclass 5, count 0 2006.190.07:25:04.17#ibcon#read 4, iclass 5, count 0 2006.190.07:25:04.17#ibcon#about to read 5, iclass 5, count 0 2006.190.07:25:04.17#ibcon#read 5, iclass 5, count 0 2006.190.07:25:04.17#ibcon#about to read 6, iclass 5, count 0 2006.190.07:25:04.17#ibcon#read 6, iclass 5, count 0 2006.190.07:25:04.17#ibcon#end of sib2, iclass 5, count 0 2006.190.07:25:04.17#ibcon#*after write, iclass 5, count 0 2006.190.07:25:04.17#ibcon#*before return 0, iclass 5, count 0 2006.190.07:25:04.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:04.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:04.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:25:04.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:25:04.17$vc4f8/va=2,7 2006.190.07:25:04.17#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.07:25:04.17#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.07:25:04.17#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:04.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:04.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:04.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:04.23#ibcon#enter wrdev, iclass 7, count 2 2006.190.07:25:04.23#ibcon#first serial, iclass 7, count 2 2006.190.07:25:04.23#ibcon#enter sib2, iclass 7, count 2 2006.190.07:25:04.23#ibcon#flushed, iclass 7, count 2 2006.190.07:25:04.23#ibcon#about to write, iclass 7, count 2 2006.190.07:25:04.23#ibcon#wrote, iclass 7, count 2 2006.190.07:25:04.23#ibcon#about to read 3, iclass 7, count 2 2006.190.07:25:04.26#ibcon#read 3, iclass 7, count 2 2006.190.07:25:04.26#ibcon#about to read 4, iclass 7, count 2 2006.190.07:25:04.26#ibcon#read 4, iclass 7, count 2 2006.190.07:25:04.26#ibcon#about to read 5, iclass 7, count 2 2006.190.07:25:04.26#ibcon#read 5, iclass 7, count 2 2006.190.07:25:04.26#ibcon#about to read 6, iclass 7, count 2 2006.190.07:25:04.26#ibcon#read 6, iclass 7, count 2 2006.190.07:25:04.26#ibcon#end of sib2, iclass 7, count 2 2006.190.07:25:04.26#ibcon#*mode == 0, iclass 7, count 2 2006.190.07:25:04.26#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.07:25:04.26#ibcon#[25=AT02-07\r\n] 2006.190.07:25:04.26#ibcon#*before write, iclass 7, count 2 2006.190.07:25:04.26#ibcon#enter sib2, iclass 7, count 2 2006.190.07:25:04.26#ibcon#flushed, iclass 7, count 2 2006.190.07:25:04.26#ibcon#about to write, iclass 7, count 2 2006.190.07:25:04.26#ibcon#wrote, iclass 7, count 2 2006.190.07:25:04.26#ibcon#about to read 3, iclass 7, count 2 2006.190.07:25:04.29#ibcon#read 3, iclass 7, count 2 2006.190.07:25:04.29#ibcon#about to read 4, iclass 7, count 2 2006.190.07:25:04.29#ibcon#read 4, iclass 7, count 2 2006.190.07:25:04.29#ibcon#about to read 5, iclass 7, count 2 2006.190.07:25:04.29#ibcon#read 5, iclass 7, count 2 2006.190.07:25:04.29#ibcon#about to read 6, iclass 7, count 2 2006.190.07:25:04.29#ibcon#read 6, iclass 7, count 2 2006.190.07:25:04.29#ibcon#end of sib2, iclass 7, count 2 2006.190.07:25:04.29#ibcon#*after write, iclass 7, count 2 2006.190.07:25:04.29#ibcon#*before return 0, iclass 7, count 2 2006.190.07:25:04.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:04.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:04.29#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.07:25:04.29#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:04.29#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:04.41#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:04.41#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:04.41#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:25:04.41#ibcon#first serial, iclass 7, count 0 2006.190.07:25:04.41#ibcon#enter sib2, iclass 7, count 0 2006.190.07:25:04.41#ibcon#flushed, iclass 7, count 0 2006.190.07:25:04.41#ibcon#about to write, iclass 7, count 0 2006.190.07:25:04.41#ibcon#wrote, iclass 7, count 0 2006.190.07:25:04.41#ibcon#about to read 3, iclass 7, count 0 2006.190.07:25:04.43#ibcon#read 3, iclass 7, count 0 2006.190.07:25:04.43#ibcon#about to read 4, iclass 7, count 0 2006.190.07:25:04.43#ibcon#read 4, iclass 7, count 0 2006.190.07:25:04.43#ibcon#about to read 5, iclass 7, count 0 2006.190.07:25:04.43#ibcon#read 5, iclass 7, count 0 2006.190.07:25:04.43#ibcon#about to read 6, iclass 7, count 0 2006.190.07:25:04.43#ibcon#read 6, iclass 7, count 0 2006.190.07:25:04.43#ibcon#end of sib2, iclass 7, count 0 2006.190.07:25:04.43#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:25:04.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:25:04.43#ibcon#[25=USB\r\n] 2006.190.07:25:04.43#ibcon#*before write, iclass 7, count 0 2006.190.07:25:04.43#ibcon#enter sib2, iclass 7, count 0 2006.190.07:25:04.43#ibcon#flushed, iclass 7, count 0 2006.190.07:25:04.43#ibcon#about to write, iclass 7, count 0 2006.190.07:25:04.43#ibcon#wrote, iclass 7, count 0 2006.190.07:25:04.43#ibcon#about to read 3, iclass 7, count 0 2006.190.07:25:04.46#ibcon#read 3, iclass 7, count 0 2006.190.07:25:04.46#ibcon#about to read 4, iclass 7, count 0 2006.190.07:25:04.46#ibcon#read 4, iclass 7, count 0 2006.190.07:25:04.46#ibcon#about to read 5, iclass 7, count 0 2006.190.07:25:04.46#ibcon#read 5, iclass 7, count 0 2006.190.07:25:04.46#ibcon#about to read 6, iclass 7, count 0 2006.190.07:25:04.46#ibcon#read 6, iclass 7, count 0 2006.190.07:25:04.46#ibcon#end of sib2, iclass 7, count 0 2006.190.07:25:04.46#ibcon#*after write, iclass 7, count 0 2006.190.07:25:04.46#ibcon#*before return 0, iclass 7, count 0 2006.190.07:25:04.46#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:04.46#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:04.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:25:04.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:25:04.46$vc4f8/valo=3,672.99 2006.190.07:25:04.46#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.07:25:04.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.07:25:04.46#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:04.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:04.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:04.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:04.46#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:25:04.46#ibcon#first serial, iclass 11, count 0 2006.190.07:25:04.46#ibcon#enter sib2, iclass 11, count 0 2006.190.07:25:04.46#ibcon#flushed, iclass 11, count 0 2006.190.07:25:04.46#ibcon#about to write, iclass 11, count 0 2006.190.07:25:04.46#ibcon#wrote, iclass 11, count 0 2006.190.07:25:04.46#ibcon#about to read 3, iclass 11, count 0 2006.190.07:25:04.48#ibcon#read 3, iclass 11, count 0 2006.190.07:25:04.48#ibcon#about to read 4, iclass 11, count 0 2006.190.07:25:04.48#ibcon#read 4, iclass 11, count 0 2006.190.07:25:04.48#ibcon#about to read 5, iclass 11, count 0 2006.190.07:25:04.48#ibcon#read 5, iclass 11, count 0 2006.190.07:25:04.48#ibcon#about to read 6, iclass 11, count 0 2006.190.07:25:04.48#ibcon#read 6, iclass 11, count 0 2006.190.07:25:04.48#ibcon#end of sib2, iclass 11, count 0 2006.190.07:25:04.48#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:25:04.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:25:04.48#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:25:04.48#ibcon#*before write, iclass 11, count 0 2006.190.07:25:04.48#ibcon#enter sib2, iclass 11, count 0 2006.190.07:25:04.48#ibcon#flushed, iclass 11, count 0 2006.190.07:25:04.48#ibcon#about to write, iclass 11, count 0 2006.190.07:25:04.48#ibcon#wrote, iclass 11, count 0 2006.190.07:25:04.48#ibcon#about to read 3, iclass 11, count 0 2006.190.07:25:04.53#ibcon#read 3, iclass 11, count 0 2006.190.07:25:04.53#ibcon#about to read 4, iclass 11, count 0 2006.190.07:25:04.53#ibcon#read 4, iclass 11, count 0 2006.190.07:25:04.53#ibcon#about to read 5, iclass 11, count 0 2006.190.07:25:04.53#ibcon#read 5, iclass 11, count 0 2006.190.07:25:04.53#ibcon#about to read 6, iclass 11, count 0 2006.190.07:25:04.53#ibcon#read 6, iclass 11, count 0 2006.190.07:25:04.53#ibcon#end of sib2, iclass 11, count 0 2006.190.07:25:04.53#ibcon#*after write, iclass 11, count 0 2006.190.07:25:04.53#ibcon#*before return 0, iclass 11, count 0 2006.190.07:25:04.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:04.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:04.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:25:04.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:25:04.53$vc4f8/va=3,6 2006.190.07:25:04.53#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.07:25:04.53#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.07:25:04.53#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:04.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:04.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:04.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:04.57#ibcon#enter wrdev, iclass 13, count 2 2006.190.07:25:04.57#ibcon#first serial, iclass 13, count 2 2006.190.07:25:04.57#ibcon#enter sib2, iclass 13, count 2 2006.190.07:25:04.57#ibcon#flushed, iclass 13, count 2 2006.190.07:25:04.57#ibcon#about to write, iclass 13, count 2 2006.190.07:25:04.57#ibcon#wrote, iclass 13, count 2 2006.190.07:25:04.57#ibcon#about to read 3, iclass 13, count 2 2006.190.07:25:04.59#ibcon#read 3, iclass 13, count 2 2006.190.07:25:04.59#ibcon#about to read 4, iclass 13, count 2 2006.190.07:25:04.59#ibcon#read 4, iclass 13, count 2 2006.190.07:25:04.59#ibcon#about to read 5, iclass 13, count 2 2006.190.07:25:04.59#ibcon#read 5, iclass 13, count 2 2006.190.07:25:04.59#ibcon#about to read 6, iclass 13, count 2 2006.190.07:25:04.59#ibcon#read 6, iclass 13, count 2 2006.190.07:25:04.59#ibcon#end of sib2, iclass 13, count 2 2006.190.07:25:04.59#ibcon#*mode == 0, iclass 13, count 2 2006.190.07:25:04.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.07:25:04.59#ibcon#[25=AT03-06\r\n] 2006.190.07:25:04.59#ibcon#*before write, iclass 13, count 2 2006.190.07:25:04.59#ibcon#enter sib2, iclass 13, count 2 2006.190.07:25:04.59#ibcon#flushed, iclass 13, count 2 2006.190.07:25:04.59#ibcon#about to write, iclass 13, count 2 2006.190.07:25:04.59#ibcon#wrote, iclass 13, count 2 2006.190.07:25:04.59#ibcon#about to read 3, iclass 13, count 2 2006.190.07:25:04.62#ibcon#read 3, iclass 13, count 2 2006.190.07:25:04.62#ibcon#about to read 4, iclass 13, count 2 2006.190.07:25:04.62#ibcon#read 4, iclass 13, count 2 2006.190.07:25:04.62#ibcon#about to read 5, iclass 13, count 2 2006.190.07:25:04.62#ibcon#read 5, iclass 13, count 2 2006.190.07:25:04.62#ibcon#about to read 6, iclass 13, count 2 2006.190.07:25:04.62#ibcon#read 6, iclass 13, count 2 2006.190.07:25:04.62#ibcon#end of sib2, iclass 13, count 2 2006.190.07:25:04.62#ibcon#*after write, iclass 13, count 2 2006.190.07:25:04.62#ibcon#*before return 0, iclass 13, count 2 2006.190.07:25:04.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:04.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:04.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.07:25:04.62#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:04.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:04.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:04.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:04.74#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:25:04.74#ibcon#first serial, iclass 13, count 0 2006.190.07:25:04.74#ibcon#enter sib2, iclass 13, count 0 2006.190.07:25:04.74#ibcon#flushed, iclass 13, count 0 2006.190.07:25:04.74#ibcon#about to write, iclass 13, count 0 2006.190.07:25:04.74#ibcon#wrote, iclass 13, count 0 2006.190.07:25:04.74#ibcon#about to read 3, iclass 13, count 0 2006.190.07:25:04.76#ibcon#read 3, iclass 13, count 0 2006.190.07:25:04.76#ibcon#about to read 4, iclass 13, count 0 2006.190.07:25:04.76#ibcon#read 4, iclass 13, count 0 2006.190.07:25:04.76#ibcon#about to read 5, iclass 13, count 0 2006.190.07:25:04.76#ibcon#read 5, iclass 13, count 0 2006.190.07:25:04.76#ibcon#about to read 6, iclass 13, count 0 2006.190.07:25:04.76#ibcon#read 6, iclass 13, count 0 2006.190.07:25:04.76#ibcon#end of sib2, iclass 13, count 0 2006.190.07:25:04.76#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:25:04.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:25:04.76#ibcon#[25=USB\r\n] 2006.190.07:25:04.76#ibcon#*before write, iclass 13, count 0 2006.190.07:25:04.76#ibcon#enter sib2, iclass 13, count 0 2006.190.07:25:04.76#ibcon#flushed, iclass 13, count 0 2006.190.07:25:04.76#ibcon#about to write, iclass 13, count 0 2006.190.07:25:04.76#ibcon#wrote, iclass 13, count 0 2006.190.07:25:04.76#ibcon#about to read 3, iclass 13, count 0 2006.190.07:25:04.79#ibcon#read 3, iclass 13, count 0 2006.190.07:25:04.79#ibcon#about to read 4, iclass 13, count 0 2006.190.07:25:04.79#ibcon#read 4, iclass 13, count 0 2006.190.07:25:04.79#ibcon#about to read 5, iclass 13, count 0 2006.190.07:25:04.79#ibcon#read 5, iclass 13, count 0 2006.190.07:25:04.79#ibcon#about to read 6, iclass 13, count 0 2006.190.07:25:04.79#ibcon#read 6, iclass 13, count 0 2006.190.07:25:04.79#ibcon#end of sib2, iclass 13, count 0 2006.190.07:25:04.79#ibcon#*after write, iclass 13, count 0 2006.190.07:25:04.79#ibcon#*before return 0, iclass 13, count 0 2006.190.07:25:04.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:04.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:04.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:25:04.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:25:04.79$vc4f8/valo=4,832.99 2006.190.07:25:04.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:25:04.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:25:04.79#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:04.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:04.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:04.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:04.79#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:25:04.79#ibcon#first serial, iclass 15, count 0 2006.190.07:25:04.79#ibcon#enter sib2, iclass 15, count 0 2006.190.07:25:04.79#ibcon#flushed, iclass 15, count 0 2006.190.07:25:04.79#ibcon#about to write, iclass 15, count 0 2006.190.07:25:04.79#ibcon#wrote, iclass 15, count 0 2006.190.07:25:04.79#ibcon#about to read 3, iclass 15, count 0 2006.190.07:25:04.81#ibcon#read 3, iclass 15, count 0 2006.190.07:25:04.81#ibcon#about to read 4, iclass 15, count 0 2006.190.07:25:04.81#ibcon#read 4, iclass 15, count 0 2006.190.07:25:04.81#ibcon#about to read 5, iclass 15, count 0 2006.190.07:25:04.81#ibcon#read 5, iclass 15, count 0 2006.190.07:25:04.81#ibcon#about to read 6, iclass 15, count 0 2006.190.07:25:04.81#ibcon#read 6, iclass 15, count 0 2006.190.07:25:04.81#ibcon#end of sib2, iclass 15, count 0 2006.190.07:25:04.81#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:25:04.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:25:04.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:25:04.81#ibcon#*before write, iclass 15, count 0 2006.190.07:25:04.81#ibcon#enter sib2, iclass 15, count 0 2006.190.07:25:04.81#ibcon#flushed, iclass 15, count 0 2006.190.07:25:04.81#ibcon#about to write, iclass 15, count 0 2006.190.07:25:04.81#ibcon#wrote, iclass 15, count 0 2006.190.07:25:04.81#ibcon#about to read 3, iclass 15, count 0 2006.190.07:25:04.85#ibcon#read 3, iclass 15, count 0 2006.190.07:25:04.85#ibcon#about to read 4, iclass 15, count 0 2006.190.07:25:04.85#ibcon#read 4, iclass 15, count 0 2006.190.07:25:04.85#ibcon#about to read 5, iclass 15, count 0 2006.190.07:25:04.85#ibcon#read 5, iclass 15, count 0 2006.190.07:25:04.85#ibcon#about to read 6, iclass 15, count 0 2006.190.07:25:04.85#ibcon#read 6, iclass 15, count 0 2006.190.07:25:04.85#ibcon#end of sib2, iclass 15, count 0 2006.190.07:25:04.85#ibcon#*after write, iclass 15, count 0 2006.190.07:25:04.85#ibcon#*before return 0, iclass 15, count 0 2006.190.07:25:04.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:04.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:04.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:25:04.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:25:04.85$vc4f8/va=4,7 2006.190.07:25:04.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.07:25:04.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.07:25:04.85#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:04.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:04.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:04.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:04.91#ibcon#enter wrdev, iclass 17, count 2 2006.190.07:25:04.91#ibcon#first serial, iclass 17, count 2 2006.190.07:25:04.91#ibcon#enter sib2, iclass 17, count 2 2006.190.07:25:04.91#ibcon#flushed, iclass 17, count 2 2006.190.07:25:04.91#ibcon#about to write, iclass 17, count 2 2006.190.07:25:04.91#ibcon#wrote, iclass 17, count 2 2006.190.07:25:04.91#ibcon#about to read 3, iclass 17, count 2 2006.190.07:25:04.93#ibcon#read 3, iclass 17, count 2 2006.190.07:25:04.93#ibcon#about to read 4, iclass 17, count 2 2006.190.07:25:04.93#ibcon#read 4, iclass 17, count 2 2006.190.07:25:04.93#ibcon#about to read 5, iclass 17, count 2 2006.190.07:25:04.93#ibcon#read 5, iclass 17, count 2 2006.190.07:25:04.93#ibcon#about to read 6, iclass 17, count 2 2006.190.07:25:04.93#ibcon#read 6, iclass 17, count 2 2006.190.07:25:04.93#ibcon#end of sib2, iclass 17, count 2 2006.190.07:25:04.93#ibcon#*mode == 0, iclass 17, count 2 2006.190.07:25:04.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.07:25:04.93#ibcon#[25=AT04-07\r\n] 2006.190.07:25:04.93#ibcon#*before write, iclass 17, count 2 2006.190.07:25:04.93#ibcon#enter sib2, iclass 17, count 2 2006.190.07:25:04.93#ibcon#flushed, iclass 17, count 2 2006.190.07:25:04.93#ibcon#about to write, iclass 17, count 2 2006.190.07:25:04.93#ibcon#wrote, iclass 17, count 2 2006.190.07:25:04.93#ibcon#about to read 3, iclass 17, count 2 2006.190.07:25:04.96#ibcon#read 3, iclass 17, count 2 2006.190.07:25:04.96#ibcon#about to read 4, iclass 17, count 2 2006.190.07:25:04.96#ibcon#read 4, iclass 17, count 2 2006.190.07:25:04.96#ibcon#about to read 5, iclass 17, count 2 2006.190.07:25:04.96#ibcon#read 5, iclass 17, count 2 2006.190.07:25:04.96#ibcon#about to read 6, iclass 17, count 2 2006.190.07:25:04.96#ibcon#read 6, iclass 17, count 2 2006.190.07:25:04.96#ibcon#end of sib2, iclass 17, count 2 2006.190.07:25:04.96#ibcon#*after write, iclass 17, count 2 2006.190.07:25:04.96#ibcon#*before return 0, iclass 17, count 2 2006.190.07:25:04.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:04.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:04.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.07:25:04.96#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:04.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:05.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:05.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:05.08#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:25:05.08#ibcon#first serial, iclass 17, count 0 2006.190.07:25:05.08#ibcon#enter sib2, iclass 17, count 0 2006.190.07:25:05.08#ibcon#flushed, iclass 17, count 0 2006.190.07:25:05.08#ibcon#about to write, iclass 17, count 0 2006.190.07:25:05.08#ibcon#wrote, iclass 17, count 0 2006.190.07:25:05.08#ibcon#about to read 3, iclass 17, count 0 2006.190.07:25:05.10#ibcon#read 3, iclass 17, count 0 2006.190.07:25:05.10#ibcon#about to read 4, iclass 17, count 0 2006.190.07:25:05.10#ibcon#read 4, iclass 17, count 0 2006.190.07:25:05.10#ibcon#about to read 5, iclass 17, count 0 2006.190.07:25:05.10#ibcon#read 5, iclass 17, count 0 2006.190.07:25:05.10#ibcon#about to read 6, iclass 17, count 0 2006.190.07:25:05.10#ibcon#read 6, iclass 17, count 0 2006.190.07:25:05.10#ibcon#end of sib2, iclass 17, count 0 2006.190.07:25:05.10#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:25:05.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:25:05.10#ibcon#[25=USB\r\n] 2006.190.07:25:05.10#ibcon#*before write, iclass 17, count 0 2006.190.07:25:05.10#ibcon#enter sib2, iclass 17, count 0 2006.190.07:25:05.10#ibcon#flushed, iclass 17, count 0 2006.190.07:25:05.10#ibcon#about to write, iclass 17, count 0 2006.190.07:25:05.10#ibcon#wrote, iclass 17, count 0 2006.190.07:25:05.10#ibcon#about to read 3, iclass 17, count 0 2006.190.07:25:05.13#ibcon#read 3, iclass 17, count 0 2006.190.07:25:05.13#ibcon#about to read 4, iclass 17, count 0 2006.190.07:25:05.13#ibcon#read 4, iclass 17, count 0 2006.190.07:25:05.13#ibcon#about to read 5, iclass 17, count 0 2006.190.07:25:05.13#ibcon#read 5, iclass 17, count 0 2006.190.07:25:05.13#ibcon#about to read 6, iclass 17, count 0 2006.190.07:25:05.13#ibcon#read 6, iclass 17, count 0 2006.190.07:25:05.13#ibcon#end of sib2, iclass 17, count 0 2006.190.07:25:05.13#ibcon#*after write, iclass 17, count 0 2006.190.07:25:05.13#ibcon#*before return 0, iclass 17, count 0 2006.190.07:25:05.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:05.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:05.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:25:05.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:25:05.13$vc4f8/valo=5,652.99 2006.190.07:25:05.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:25:05.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:25:05.13#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:05.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:05.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:05.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:05.13#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:25:05.13#ibcon#first serial, iclass 19, count 0 2006.190.07:25:05.13#ibcon#enter sib2, iclass 19, count 0 2006.190.07:25:05.13#ibcon#flushed, iclass 19, count 0 2006.190.07:25:05.13#ibcon#about to write, iclass 19, count 0 2006.190.07:25:05.13#ibcon#wrote, iclass 19, count 0 2006.190.07:25:05.13#ibcon#about to read 3, iclass 19, count 0 2006.190.07:25:05.15#ibcon#read 3, iclass 19, count 0 2006.190.07:25:05.15#ibcon#about to read 4, iclass 19, count 0 2006.190.07:25:05.15#ibcon#read 4, iclass 19, count 0 2006.190.07:25:05.15#ibcon#about to read 5, iclass 19, count 0 2006.190.07:25:05.15#ibcon#read 5, iclass 19, count 0 2006.190.07:25:05.15#ibcon#about to read 6, iclass 19, count 0 2006.190.07:25:05.15#ibcon#read 6, iclass 19, count 0 2006.190.07:25:05.15#ibcon#end of sib2, iclass 19, count 0 2006.190.07:25:05.15#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:25:05.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:25:05.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:25:05.15#ibcon#*before write, iclass 19, count 0 2006.190.07:25:05.15#ibcon#enter sib2, iclass 19, count 0 2006.190.07:25:05.15#ibcon#flushed, iclass 19, count 0 2006.190.07:25:05.15#ibcon#about to write, iclass 19, count 0 2006.190.07:25:05.15#ibcon#wrote, iclass 19, count 0 2006.190.07:25:05.15#ibcon#about to read 3, iclass 19, count 0 2006.190.07:25:05.19#ibcon#read 3, iclass 19, count 0 2006.190.07:25:05.19#ibcon#about to read 4, iclass 19, count 0 2006.190.07:25:05.19#ibcon#read 4, iclass 19, count 0 2006.190.07:25:05.19#ibcon#about to read 5, iclass 19, count 0 2006.190.07:25:05.19#ibcon#read 5, iclass 19, count 0 2006.190.07:25:05.19#ibcon#about to read 6, iclass 19, count 0 2006.190.07:25:05.19#ibcon#read 6, iclass 19, count 0 2006.190.07:25:05.19#ibcon#end of sib2, iclass 19, count 0 2006.190.07:25:05.19#ibcon#*after write, iclass 19, count 0 2006.190.07:25:05.19#ibcon#*before return 0, iclass 19, count 0 2006.190.07:25:05.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:05.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:05.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:25:05.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:25:05.19$vc4f8/va=5,7 2006.190.07:25:05.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.07:25:05.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.07:25:05.19#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:05.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:05.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:05.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:05.25#ibcon#enter wrdev, iclass 21, count 2 2006.190.07:25:05.25#ibcon#first serial, iclass 21, count 2 2006.190.07:25:05.25#ibcon#enter sib2, iclass 21, count 2 2006.190.07:25:05.25#ibcon#flushed, iclass 21, count 2 2006.190.07:25:05.25#ibcon#about to write, iclass 21, count 2 2006.190.07:25:05.25#ibcon#wrote, iclass 21, count 2 2006.190.07:25:05.25#ibcon#about to read 3, iclass 21, count 2 2006.190.07:25:05.27#ibcon#read 3, iclass 21, count 2 2006.190.07:25:05.27#ibcon#about to read 4, iclass 21, count 2 2006.190.07:25:05.27#ibcon#read 4, iclass 21, count 2 2006.190.07:25:05.27#ibcon#about to read 5, iclass 21, count 2 2006.190.07:25:05.27#ibcon#read 5, iclass 21, count 2 2006.190.07:25:05.27#ibcon#about to read 6, iclass 21, count 2 2006.190.07:25:05.27#ibcon#read 6, iclass 21, count 2 2006.190.07:25:05.27#ibcon#end of sib2, iclass 21, count 2 2006.190.07:25:05.27#ibcon#*mode == 0, iclass 21, count 2 2006.190.07:25:05.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.07:25:05.27#ibcon#[25=AT05-07\r\n] 2006.190.07:25:05.27#ibcon#*before write, iclass 21, count 2 2006.190.07:25:05.27#ibcon#enter sib2, iclass 21, count 2 2006.190.07:25:05.27#ibcon#flushed, iclass 21, count 2 2006.190.07:25:05.27#ibcon#about to write, iclass 21, count 2 2006.190.07:25:05.27#ibcon#wrote, iclass 21, count 2 2006.190.07:25:05.27#ibcon#about to read 3, iclass 21, count 2 2006.190.07:25:05.30#ibcon#read 3, iclass 21, count 2 2006.190.07:25:05.30#ibcon#about to read 4, iclass 21, count 2 2006.190.07:25:05.30#ibcon#read 4, iclass 21, count 2 2006.190.07:25:05.30#ibcon#about to read 5, iclass 21, count 2 2006.190.07:25:05.30#ibcon#read 5, iclass 21, count 2 2006.190.07:25:05.30#ibcon#about to read 6, iclass 21, count 2 2006.190.07:25:05.30#ibcon#read 6, iclass 21, count 2 2006.190.07:25:05.30#ibcon#end of sib2, iclass 21, count 2 2006.190.07:25:05.30#ibcon#*after write, iclass 21, count 2 2006.190.07:25:05.30#ibcon#*before return 0, iclass 21, count 2 2006.190.07:25:05.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:05.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:05.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.07:25:05.30#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:05.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:05.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:05.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:05.42#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:25:05.42#ibcon#first serial, iclass 21, count 0 2006.190.07:25:05.42#ibcon#enter sib2, iclass 21, count 0 2006.190.07:25:05.42#ibcon#flushed, iclass 21, count 0 2006.190.07:25:05.42#ibcon#about to write, iclass 21, count 0 2006.190.07:25:05.42#ibcon#wrote, iclass 21, count 0 2006.190.07:25:05.42#ibcon#about to read 3, iclass 21, count 0 2006.190.07:25:05.44#ibcon#read 3, iclass 21, count 0 2006.190.07:25:05.44#ibcon#about to read 4, iclass 21, count 0 2006.190.07:25:05.44#ibcon#read 4, iclass 21, count 0 2006.190.07:25:05.44#ibcon#about to read 5, iclass 21, count 0 2006.190.07:25:05.44#ibcon#read 5, iclass 21, count 0 2006.190.07:25:05.44#ibcon#about to read 6, iclass 21, count 0 2006.190.07:25:05.44#ibcon#read 6, iclass 21, count 0 2006.190.07:25:05.44#ibcon#end of sib2, iclass 21, count 0 2006.190.07:25:05.44#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:25:05.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:25:05.44#ibcon#[25=USB\r\n] 2006.190.07:25:05.44#ibcon#*before write, iclass 21, count 0 2006.190.07:25:05.44#ibcon#enter sib2, iclass 21, count 0 2006.190.07:25:05.44#ibcon#flushed, iclass 21, count 0 2006.190.07:25:05.44#ibcon#about to write, iclass 21, count 0 2006.190.07:25:05.44#ibcon#wrote, iclass 21, count 0 2006.190.07:25:05.44#ibcon#about to read 3, iclass 21, count 0 2006.190.07:25:05.47#ibcon#read 3, iclass 21, count 0 2006.190.07:25:05.47#ibcon#about to read 4, iclass 21, count 0 2006.190.07:25:05.47#ibcon#read 4, iclass 21, count 0 2006.190.07:25:05.47#ibcon#about to read 5, iclass 21, count 0 2006.190.07:25:05.47#ibcon#read 5, iclass 21, count 0 2006.190.07:25:05.47#ibcon#about to read 6, iclass 21, count 0 2006.190.07:25:05.47#ibcon#read 6, iclass 21, count 0 2006.190.07:25:05.47#ibcon#end of sib2, iclass 21, count 0 2006.190.07:25:05.47#ibcon#*after write, iclass 21, count 0 2006.190.07:25:05.47#ibcon#*before return 0, iclass 21, count 0 2006.190.07:25:05.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:05.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:05.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:25:05.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:25:05.47$vc4f8/valo=6,772.99 2006.190.07:25:05.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.07:25:05.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.07:25:05.47#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:05.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:05.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:05.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:05.47#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:25:05.47#ibcon#first serial, iclass 23, count 0 2006.190.07:25:05.47#ibcon#enter sib2, iclass 23, count 0 2006.190.07:25:05.47#ibcon#flushed, iclass 23, count 0 2006.190.07:25:05.47#ibcon#about to write, iclass 23, count 0 2006.190.07:25:05.47#ibcon#wrote, iclass 23, count 0 2006.190.07:25:05.47#ibcon#about to read 3, iclass 23, count 0 2006.190.07:25:05.49#ibcon#read 3, iclass 23, count 0 2006.190.07:25:05.49#ibcon#about to read 4, iclass 23, count 0 2006.190.07:25:05.49#ibcon#read 4, iclass 23, count 0 2006.190.07:25:05.49#ibcon#about to read 5, iclass 23, count 0 2006.190.07:25:05.49#ibcon#read 5, iclass 23, count 0 2006.190.07:25:05.49#ibcon#about to read 6, iclass 23, count 0 2006.190.07:25:05.49#ibcon#read 6, iclass 23, count 0 2006.190.07:25:05.49#ibcon#end of sib2, iclass 23, count 0 2006.190.07:25:05.49#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:25:05.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:25:05.49#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:25:05.49#ibcon#*before write, iclass 23, count 0 2006.190.07:25:05.49#ibcon#enter sib2, iclass 23, count 0 2006.190.07:25:05.49#ibcon#flushed, iclass 23, count 0 2006.190.07:25:05.49#ibcon#about to write, iclass 23, count 0 2006.190.07:25:05.49#ibcon#wrote, iclass 23, count 0 2006.190.07:25:05.49#ibcon#about to read 3, iclass 23, count 0 2006.190.07:25:05.53#ibcon#read 3, iclass 23, count 0 2006.190.07:25:05.53#ibcon#about to read 4, iclass 23, count 0 2006.190.07:25:05.53#ibcon#read 4, iclass 23, count 0 2006.190.07:25:05.53#ibcon#about to read 5, iclass 23, count 0 2006.190.07:25:05.53#ibcon#read 5, iclass 23, count 0 2006.190.07:25:05.53#ibcon#about to read 6, iclass 23, count 0 2006.190.07:25:05.53#ibcon#read 6, iclass 23, count 0 2006.190.07:25:05.53#ibcon#end of sib2, iclass 23, count 0 2006.190.07:25:05.53#ibcon#*after write, iclass 23, count 0 2006.190.07:25:05.53#ibcon#*before return 0, iclass 23, count 0 2006.190.07:25:05.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:05.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:05.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:25:05.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:25:05.53$vc4f8/va=6,6 2006.190.07:25:05.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.07:25:05.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.07:25:05.53#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:05.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:25:05.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:25:05.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:25:05.59#ibcon#enter wrdev, iclass 25, count 2 2006.190.07:25:05.59#ibcon#first serial, iclass 25, count 2 2006.190.07:25:05.59#ibcon#enter sib2, iclass 25, count 2 2006.190.07:25:05.59#ibcon#flushed, iclass 25, count 2 2006.190.07:25:05.59#ibcon#about to write, iclass 25, count 2 2006.190.07:25:05.59#ibcon#wrote, iclass 25, count 2 2006.190.07:25:05.59#ibcon#about to read 3, iclass 25, count 2 2006.190.07:25:05.61#ibcon#read 3, iclass 25, count 2 2006.190.07:25:05.61#ibcon#about to read 4, iclass 25, count 2 2006.190.07:25:05.61#ibcon#read 4, iclass 25, count 2 2006.190.07:25:05.61#ibcon#about to read 5, iclass 25, count 2 2006.190.07:25:05.61#ibcon#read 5, iclass 25, count 2 2006.190.07:25:05.61#ibcon#about to read 6, iclass 25, count 2 2006.190.07:25:05.61#ibcon#read 6, iclass 25, count 2 2006.190.07:25:05.61#ibcon#end of sib2, iclass 25, count 2 2006.190.07:25:05.61#ibcon#*mode == 0, iclass 25, count 2 2006.190.07:25:05.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.07:25:05.61#ibcon#[25=AT06-06\r\n] 2006.190.07:25:05.61#ibcon#*before write, iclass 25, count 2 2006.190.07:25:05.61#ibcon#enter sib2, iclass 25, count 2 2006.190.07:25:05.61#ibcon#flushed, iclass 25, count 2 2006.190.07:25:05.61#ibcon#about to write, iclass 25, count 2 2006.190.07:25:05.61#ibcon#wrote, iclass 25, count 2 2006.190.07:25:05.61#ibcon#about to read 3, iclass 25, count 2 2006.190.07:25:05.64#ibcon#read 3, iclass 25, count 2 2006.190.07:25:05.64#ibcon#about to read 4, iclass 25, count 2 2006.190.07:25:05.64#ibcon#read 4, iclass 25, count 2 2006.190.07:25:05.64#ibcon#about to read 5, iclass 25, count 2 2006.190.07:25:05.64#ibcon#read 5, iclass 25, count 2 2006.190.07:25:05.64#ibcon#about to read 6, iclass 25, count 2 2006.190.07:25:05.64#ibcon#read 6, iclass 25, count 2 2006.190.07:25:05.64#ibcon#end of sib2, iclass 25, count 2 2006.190.07:25:05.64#ibcon#*after write, iclass 25, count 2 2006.190.07:25:05.64#ibcon#*before return 0, iclass 25, count 2 2006.190.07:25:05.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:25:05.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:25:05.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.07:25:05.64#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:05.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:25:05.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:25:05.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:25:05.76#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:25:05.76#ibcon#first serial, iclass 25, count 0 2006.190.07:25:05.76#ibcon#enter sib2, iclass 25, count 0 2006.190.07:25:05.76#ibcon#flushed, iclass 25, count 0 2006.190.07:25:05.76#ibcon#about to write, iclass 25, count 0 2006.190.07:25:05.76#ibcon#wrote, iclass 25, count 0 2006.190.07:25:05.76#ibcon#about to read 3, iclass 25, count 0 2006.190.07:25:05.78#ibcon#read 3, iclass 25, count 0 2006.190.07:25:05.78#ibcon#about to read 4, iclass 25, count 0 2006.190.07:25:05.78#ibcon#read 4, iclass 25, count 0 2006.190.07:25:05.78#ibcon#about to read 5, iclass 25, count 0 2006.190.07:25:05.78#ibcon#read 5, iclass 25, count 0 2006.190.07:25:05.78#ibcon#about to read 6, iclass 25, count 0 2006.190.07:25:05.78#ibcon#read 6, iclass 25, count 0 2006.190.07:25:05.78#ibcon#end of sib2, iclass 25, count 0 2006.190.07:25:05.78#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:25:05.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:25:05.78#ibcon#[25=USB\r\n] 2006.190.07:25:05.78#ibcon#*before write, iclass 25, count 0 2006.190.07:25:05.78#ibcon#enter sib2, iclass 25, count 0 2006.190.07:25:05.78#ibcon#flushed, iclass 25, count 0 2006.190.07:25:05.78#ibcon#about to write, iclass 25, count 0 2006.190.07:25:05.78#ibcon#wrote, iclass 25, count 0 2006.190.07:25:05.78#ibcon#about to read 3, iclass 25, count 0 2006.190.07:25:05.81#ibcon#read 3, iclass 25, count 0 2006.190.07:25:05.81#ibcon#about to read 4, iclass 25, count 0 2006.190.07:25:05.81#ibcon#read 4, iclass 25, count 0 2006.190.07:25:05.81#ibcon#about to read 5, iclass 25, count 0 2006.190.07:25:05.81#ibcon#read 5, iclass 25, count 0 2006.190.07:25:05.81#ibcon#about to read 6, iclass 25, count 0 2006.190.07:25:05.81#ibcon#read 6, iclass 25, count 0 2006.190.07:25:05.81#ibcon#end of sib2, iclass 25, count 0 2006.190.07:25:05.81#ibcon#*after write, iclass 25, count 0 2006.190.07:25:05.81#ibcon#*before return 0, iclass 25, count 0 2006.190.07:25:05.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:25:05.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:25:05.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:25:05.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:25:05.81$vc4f8/valo=7,832.99 2006.190.07:25:05.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.07:25:05.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.07:25:05.81#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:05.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:25:05.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:25:05.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:25:05.81#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:25:05.81#ibcon#first serial, iclass 27, count 0 2006.190.07:25:05.81#ibcon#enter sib2, iclass 27, count 0 2006.190.07:25:05.81#ibcon#flushed, iclass 27, count 0 2006.190.07:25:05.81#ibcon#about to write, iclass 27, count 0 2006.190.07:25:05.81#ibcon#wrote, iclass 27, count 0 2006.190.07:25:05.81#ibcon#about to read 3, iclass 27, count 0 2006.190.07:25:05.83#ibcon#read 3, iclass 27, count 0 2006.190.07:25:05.83#ibcon#about to read 4, iclass 27, count 0 2006.190.07:25:05.83#ibcon#read 4, iclass 27, count 0 2006.190.07:25:05.83#ibcon#about to read 5, iclass 27, count 0 2006.190.07:25:05.83#ibcon#read 5, iclass 27, count 0 2006.190.07:25:05.83#ibcon#about to read 6, iclass 27, count 0 2006.190.07:25:05.83#ibcon#read 6, iclass 27, count 0 2006.190.07:25:05.83#ibcon#end of sib2, iclass 27, count 0 2006.190.07:25:05.83#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:25:05.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:25:05.83#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:25:05.83#ibcon#*before write, iclass 27, count 0 2006.190.07:25:05.83#ibcon#enter sib2, iclass 27, count 0 2006.190.07:25:05.83#ibcon#flushed, iclass 27, count 0 2006.190.07:25:05.83#ibcon#about to write, iclass 27, count 0 2006.190.07:25:05.83#ibcon#wrote, iclass 27, count 0 2006.190.07:25:05.83#ibcon#about to read 3, iclass 27, count 0 2006.190.07:25:05.87#ibcon#read 3, iclass 27, count 0 2006.190.07:25:05.87#ibcon#about to read 4, iclass 27, count 0 2006.190.07:25:05.87#ibcon#read 4, iclass 27, count 0 2006.190.07:25:05.87#ibcon#about to read 5, iclass 27, count 0 2006.190.07:25:05.87#ibcon#read 5, iclass 27, count 0 2006.190.07:25:05.87#ibcon#about to read 6, iclass 27, count 0 2006.190.07:25:05.87#ibcon#read 6, iclass 27, count 0 2006.190.07:25:05.87#ibcon#end of sib2, iclass 27, count 0 2006.190.07:25:05.87#ibcon#*after write, iclass 27, count 0 2006.190.07:25:05.87#ibcon#*before return 0, iclass 27, count 0 2006.190.07:25:05.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:25:05.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:25:05.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:25:05.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:25:05.87$vc4f8/va=7,6 2006.190.07:25:05.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.07:25:05.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.07:25:05.87#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:05.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:25:05.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:25:05.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:25:05.93#ibcon#enter wrdev, iclass 29, count 2 2006.190.07:25:05.93#ibcon#first serial, iclass 29, count 2 2006.190.07:25:05.93#ibcon#enter sib2, iclass 29, count 2 2006.190.07:25:05.93#ibcon#flushed, iclass 29, count 2 2006.190.07:25:05.93#ibcon#about to write, iclass 29, count 2 2006.190.07:25:05.93#ibcon#wrote, iclass 29, count 2 2006.190.07:25:05.93#ibcon#about to read 3, iclass 29, count 2 2006.190.07:25:05.95#ibcon#read 3, iclass 29, count 2 2006.190.07:25:05.95#ibcon#about to read 4, iclass 29, count 2 2006.190.07:25:05.95#ibcon#read 4, iclass 29, count 2 2006.190.07:25:05.95#ibcon#about to read 5, iclass 29, count 2 2006.190.07:25:05.95#ibcon#read 5, iclass 29, count 2 2006.190.07:25:05.95#ibcon#about to read 6, iclass 29, count 2 2006.190.07:25:05.95#ibcon#read 6, iclass 29, count 2 2006.190.07:25:05.95#ibcon#end of sib2, iclass 29, count 2 2006.190.07:25:05.95#ibcon#*mode == 0, iclass 29, count 2 2006.190.07:25:05.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.07:25:05.95#ibcon#[25=AT07-06\r\n] 2006.190.07:25:05.95#ibcon#*before write, iclass 29, count 2 2006.190.07:25:05.95#ibcon#enter sib2, iclass 29, count 2 2006.190.07:25:05.95#ibcon#flushed, iclass 29, count 2 2006.190.07:25:05.95#ibcon#about to write, iclass 29, count 2 2006.190.07:25:05.95#ibcon#wrote, iclass 29, count 2 2006.190.07:25:05.95#ibcon#about to read 3, iclass 29, count 2 2006.190.07:25:05.98#ibcon#read 3, iclass 29, count 2 2006.190.07:25:05.98#ibcon#about to read 4, iclass 29, count 2 2006.190.07:25:05.98#ibcon#read 4, iclass 29, count 2 2006.190.07:25:05.98#ibcon#about to read 5, iclass 29, count 2 2006.190.07:25:05.98#ibcon#read 5, iclass 29, count 2 2006.190.07:25:05.98#ibcon#about to read 6, iclass 29, count 2 2006.190.07:25:05.98#ibcon#read 6, iclass 29, count 2 2006.190.07:25:05.98#ibcon#end of sib2, iclass 29, count 2 2006.190.07:25:05.98#ibcon#*after write, iclass 29, count 2 2006.190.07:25:05.98#ibcon#*before return 0, iclass 29, count 2 2006.190.07:25:05.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:25:05.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:25:05.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.07:25:05.98#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:05.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:25:06.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:25:06.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:25:06.10#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:25:06.10#ibcon#first serial, iclass 29, count 0 2006.190.07:25:06.10#ibcon#enter sib2, iclass 29, count 0 2006.190.07:25:06.10#ibcon#flushed, iclass 29, count 0 2006.190.07:25:06.10#ibcon#about to write, iclass 29, count 0 2006.190.07:25:06.10#ibcon#wrote, iclass 29, count 0 2006.190.07:25:06.10#ibcon#about to read 3, iclass 29, count 0 2006.190.07:25:06.12#ibcon#read 3, iclass 29, count 0 2006.190.07:25:06.12#ibcon#about to read 4, iclass 29, count 0 2006.190.07:25:06.12#ibcon#read 4, iclass 29, count 0 2006.190.07:25:06.12#ibcon#about to read 5, iclass 29, count 0 2006.190.07:25:06.12#ibcon#read 5, iclass 29, count 0 2006.190.07:25:06.12#ibcon#about to read 6, iclass 29, count 0 2006.190.07:25:06.12#ibcon#read 6, iclass 29, count 0 2006.190.07:25:06.12#ibcon#end of sib2, iclass 29, count 0 2006.190.07:25:06.12#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:25:06.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:25:06.12#ibcon#[25=USB\r\n] 2006.190.07:25:06.12#ibcon#*before write, iclass 29, count 0 2006.190.07:25:06.12#ibcon#enter sib2, iclass 29, count 0 2006.190.07:25:06.12#ibcon#flushed, iclass 29, count 0 2006.190.07:25:06.12#ibcon#about to write, iclass 29, count 0 2006.190.07:25:06.12#ibcon#wrote, iclass 29, count 0 2006.190.07:25:06.12#ibcon#about to read 3, iclass 29, count 0 2006.190.07:25:06.15#ibcon#read 3, iclass 29, count 0 2006.190.07:25:06.15#ibcon#about to read 4, iclass 29, count 0 2006.190.07:25:06.15#ibcon#read 4, iclass 29, count 0 2006.190.07:25:06.15#ibcon#about to read 5, iclass 29, count 0 2006.190.07:25:06.15#ibcon#read 5, iclass 29, count 0 2006.190.07:25:06.15#ibcon#about to read 6, iclass 29, count 0 2006.190.07:25:06.15#ibcon#read 6, iclass 29, count 0 2006.190.07:25:06.15#ibcon#end of sib2, iclass 29, count 0 2006.190.07:25:06.15#ibcon#*after write, iclass 29, count 0 2006.190.07:25:06.15#ibcon#*before return 0, iclass 29, count 0 2006.190.07:25:06.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:25:06.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:25:06.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:25:06.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:25:06.15$vc4f8/valo=8,852.99 2006.190.07:25:06.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.07:25:06.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.07:25:06.15#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:06.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:25:06.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:25:06.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:25:06.15#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:25:06.15#ibcon#first serial, iclass 31, count 0 2006.190.07:25:06.15#ibcon#enter sib2, iclass 31, count 0 2006.190.07:25:06.15#ibcon#flushed, iclass 31, count 0 2006.190.07:25:06.15#ibcon#about to write, iclass 31, count 0 2006.190.07:25:06.15#ibcon#wrote, iclass 31, count 0 2006.190.07:25:06.15#ibcon#about to read 3, iclass 31, count 0 2006.190.07:25:06.17#ibcon#read 3, iclass 31, count 0 2006.190.07:25:06.17#ibcon#about to read 4, iclass 31, count 0 2006.190.07:25:06.17#ibcon#read 4, iclass 31, count 0 2006.190.07:25:06.17#ibcon#about to read 5, iclass 31, count 0 2006.190.07:25:06.17#ibcon#read 5, iclass 31, count 0 2006.190.07:25:06.17#ibcon#about to read 6, iclass 31, count 0 2006.190.07:25:06.17#ibcon#read 6, iclass 31, count 0 2006.190.07:25:06.17#ibcon#end of sib2, iclass 31, count 0 2006.190.07:25:06.17#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:25:06.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:25:06.17#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:25:06.17#ibcon#*before write, iclass 31, count 0 2006.190.07:25:06.17#ibcon#enter sib2, iclass 31, count 0 2006.190.07:25:06.17#ibcon#flushed, iclass 31, count 0 2006.190.07:25:06.17#ibcon#about to write, iclass 31, count 0 2006.190.07:25:06.17#ibcon#wrote, iclass 31, count 0 2006.190.07:25:06.17#ibcon#about to read 3, iclass 31, count 0 2006.190.07:25:06.21#ibcon#read 3, iclass 31, count 0 2006.190.07:25:06.21#ibcon#about to read 4, iclass 31, count 0 2006.190.07:25:06.21#ibcon#read 4, iclass 31, count 0 2006.190.07:25:06.21#ibcon#about to read 5, iclass 31, count 0 2006.190.07:25:06.21#ibcon#read 5, iclass 31, count 0 2006.190.07:25:06.21#ibcon#about to read 6, iclass 31, count 0 2006.190.07:25:06.21#ibcon#read 6, iclass 31, count 0 2006.190.07:25:06.21#ibcon#end of sib2, iclass 31, count 0 2006.190.07:25:06.21#ibcon#*after write, iclass 31, count 0 2006.190.07:25:06.21#ibcon#*before return 0, iclass 31, count 0 2006.190.07:25:06.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:25:06.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:25:06.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:25:06.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:25:06.21$vc4f8/va=8,6 2006.190.07:25:06.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.190.07:25:06.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.190.07:25:06.21#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:06.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:25:06.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:25:06.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:25:06.27#ibcon#enter wrdev, iclass 33, count 2 2006.190.07:25:06.27#ibcon#first serial, iclass 33, count 2 2006.190.07:25:06.27#ibcon#enter sib2, iclass 33, count 2 2006.190.07:25:06.27#ibcon#flushed, iclass 33, count 2 2006.190.07:25:06.27#ibcon#about to write, iclass 33, count 2 2006.190.07:25:06.27#ibcon#wrote, iclass 33, count 2 2006.190.07:25:06.27#ibcon#about to read 3, iclass 33, count 2 2006.190.07:25:06.30#ibcon#read 3, iclass 33, count 2 2006.190.07:25:06.30#ibcon#about to read 4, iclass 33, count 2 2006.190.07:25:06.30#ibcon#read 4, iclass 33, count 2 2006.190.07:25:06.30#ibcon#about to read 5, iclass 33, count 2 2006.190.07:25:06.30#ibcon#read 5, iclass 33, count 2 2006.190.07:25:06.30#ibcon#about to read 6, iclass 33, count 2 2006.190.07:25:06.30#ibcon#read 6, iclass 33, count 2 2006.190.07:25:06.30#ibcon#end of sib2, iclass 33, count 2 2006.190.07:25:06.30#ibcon#*mode == 0, iclass 33, count 2 2006.190.07:25:06.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.190.07:25:06.30#ibcon#[25=AT08-06\r\n] 2006.190.07:25:06.30#ibcon#*before write, iclass 33, count 2 2006.190.07:25:06.30#ibcon#enter sib2, iclass 33, count 2 2006.190.07:25:06.30#ibcon#flushed, iclass 33, count 2 2006.190.07:25:06.30#ibcon#about to write, iclass 33, count 2 2006.190.07:25:06.30#ibcon#wrote, iclass 33, count 2 2006.190.07:25:06.30#ibcon#about to read 3, iclass 33, count 2 2006.190.07:25:06.32#ibcon#read 3, iclass 33, count 2 2006.190.07:25:06.32#ibcon#about to read 4, iclass 33, count 2 2006.190.07:25:06.32#ibcon#read 4, iclass 33, count 2 2006.190.07:25:06.32#ibcon#about to read 5, iclass 33, count 2 2006.190.07:25:06.32#ibcon#read 5, iclass 33, count 2 2006.190.07:25:06.32#ibcon#about to read 6, iclass 33, count 2 2006.190.07:25:06.32#ibcon#read 6, iclass 33, count 2 2006.190.07:25:06.32#ibcon#end of sib2, iclass 33, count 2 2006.190.07:25:06.32#ibcon#*after write, iclass 33, count 2 2006.190.07:25:06.32#ibcon#*before return 0, iclass 33, count 2 2006.190.07:25:06.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:25:06.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:25:06.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.190.07:25:06.32#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:06.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:25:06.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:25:06.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:25:06.44#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:25:06.44#ibcon#first serial, iclass 33, count 0 2006.190.07:25:06.44#ibcon#enter sib2, iclass 33, count 0 2006.190.07:25:06.44#ibcon#flushed, iclass 33, count 0 2006.190.07:25:06.44#ibcon#about to write, iclass 33, count 0 2006.190.07:25:06.44#ibcon#wrote, iclass 33, count 0 2006.190.07:25:06.44#ibcon#about to read 3, iclass 33, count 0 2006.190.07:25:06.46#ibcon#read 3, iclass 33, count 0 2006.190.07:25:06.46#ibcon#about to read 4, iclass 33, count 0 2006.190.07:25:06.46#ibcon#read 4, iclass 33, count 0 2006.190.07:25:06.46#ibcon#about to read 5, iclass 33, count 0 2006.190.07:25:06.46#ibcon#read 5, iclass 33, count 0 2006.190.07:25:06.46#ibcon#about to read 6, iclass 33, count 0 2006.190.07:25:06.46#ibcon#read 6, iclass 33, count 0 2006.190.07:25:06.46#ibcon#end of sib2, iclass 33, count 0 2006.190.07:25:06.46#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:25:06.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:25:06.46#ibcon#[25=USB\r\n] 2006.190.07:25:06.46#ibcon#*before write, iclass 33, count 0 2006.190.07:25:06.46#ibcon#enter sib2, iclass 33, count 0 2006.190.07:25:06.46#ibcon#flushed, iclass 33, count 0 2006.190.07:25:06.46#ibcon#about to write, iclass 33, count 0 2006.190.07:25:06.46#ibcon#wrote, iclass 33, count 0 2006.190.07:25:06.46#ibcon#about to read 3, iclass 33, count 0 2006.190.07:25:06.49#ibcon#read 3, iclass 33, count 0 2006.190.07:25:06.49#ibcon#about to read 4, iclass 33, count 0 2006.190.07:25:06.49#ibcon#read 4, iclass 33, count 0 2006.190.07:25:06.49#ibcon#about to read 5, iclass 33, count 0 2006.190.07:25:06.49#ibcon#read 5, iclass 33, count 0 2006.190.07:25:06.49#ibcon#about to read 6, iclass 33, count 0 2006.190.07:25:06.49#ibcon#read 6, iclass 33, count 0 2006.190.07:25:06.49#ibcon#end of sib2, iclass 33, count 0 2006.190.07:25:06.49#ibcon#*after write, iclass 33, count 0 2006.190.07:25:06.49#ibcon#*before return 0, iclass 33, count 0 2006.190.07:25:06.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:25:06.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:25:06.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:25:06.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:25:06.49$vc4f8/vblo=1,632.99 2006.190.07:25:06.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.07:25:06.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.07:25:06.49#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:06.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:25:06.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:25:06.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:25:06.49#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:25:06.49#ibcon#first serial, iclass 35, count 0 2006.190.07:25:06.49#ibcon#enter sib2, iclass 35, count 0 2006.190.07:25:06.49#ibcon#flushed, iclass 35, count 0 2006.190.07:25:06.49#ibcon#about to write, iclass 35, count 0 2006.190.07:25:06.49#ibcon#wrote, iclass 35, count 0 2006.190.07:25:06.49#ibcon#about to read 3, iclass 35, count 0 2006.190.07:25:06.51#ibcon#read 3, iclass 35, count 0 2006.190.07:25:06.51#ibcon#about to read 4, iclass 35, count 0 2006.190.07:25:06.51#ibcon#read 4, iclass 35, count 0 2006.190.07:25:06.51#ibcon#about to read 5, iclass 35, count 0 2006.190.07:25:06.51#ibcon#read 5, iclass 35, count 0 2006.190.07:25:06.51#ibcon#about to read 6, iclass 35, count 0 2006.190.07:25:06.51#ibcon#read 6, iclass 35, count 0 2006.190.07:25:06.51#ibcon#end of sib2, iclass 35, count 0 2006.190.07:25:06.51#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:25:06.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:25:06.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:25:06.51#ibcon#*before write, iclass 35, count 0 2006.190.07:25:06.51#ibcon#enter sib2, iclass 35, count 0 2006.190.07:25:06.51#ibcon#flushed, iclass 35, count 0 2006.190.07:25:06.51#ibcon#about to write, iclass 35, count 0 2006.190.07:25:06.51#ibcon#wrote, iclass 35, count 0 2006.190.07:25:06.51#ibcon#about to read 3, iclass 35, count 0 2006.190.07:25:06.55#ibcon#read 3, iclass 35, count 0 2006.190.07:25:06.55#ibcon#about to read 4, iclass 35, count 0 2006.190.07:25:06.55#ibcon#read 4, iclass 35, count 0 2006.190.07:25:06.55#ibcon#about to read 5, iclass 35, count 0 2006.190.07:25:06.55#ibcon#read 5, iclass 35, count 0 2006.190.07:25:06.55#ibcon#about to read 6, iclass 35, count 0 2006.190.07:25:06.55#ibcon#read 6, iclass 35, count 0 2006.190.07:25:06.55#ibcon#end of sib2, iclass 35, count 0 2006.190.07:25:06.55#ibcon#*after write, iclass 35, count 0 2006.190.07:25:06.55#ibcon#*before return 0, iclass 35, count 0 2006.190.07:25:06.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:25:06.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:25:06.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:25:06.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:25:06.55$vc4f8/vb=1,4 2006.190.07:25:06.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.07:25:06.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.07:25:06.55#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:06.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:25:06.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:25:06.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:25:06.55#ibcon#enter wrdev, iclass 37, count 2 2006.190.07:25:06.55#ibcon#first serial, iclass 37, count 2 2006.190.07:25:06.55#ibcon#enter sib2, iclass 37, count 2 2006.190.07:25:06.55#ibcon#flushed, iclass 37, count 2 2006.190.07:25:06.55#ibcon#about to write, iclass 37, count 2 2006.190.07:25:06.55#ibcon#wrote, iclass 37, count 2 2006.190.07:25:06.55#ibcon#about to read 3, iclass 37, count 2 2006.190.07:25:06.57#ibcon#read 3, iclass 37, count 2 2006.190.07:25:06.57#ibcon#about to read 4, iclass 37, count 2 2006.190.07:25:06.57#ibcon#read 4, iclass 37, count 2 2006.190.07:25:06.57#ibcon#about to read 5, iclass 37, count 2 2006.190.07:25:06.57#ibcon#read 5, iclass 37, count 2 2006.190.07:25:06.57#ibcon#about to read 6, iclass 37, count 2 2006.190.07:25:06.57#ibcon#read 6, iclass 37, count 2 2006.190.07:25:06.57#ibcon#end of sib2, iclass 37, count 2 2006.190.07:25:06.57#ibcon#*mode == 0, iclass 37, count 2 2006.190.07:25:06.57#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.07:25:06.57#ibcon#[27=AT01-04\r\n] 2006.190.07:25:06.57#ibcon#*before write, iclass 37, count 2 2006.190.07:25:06.57#ibcon#enter sib2, iclass 37, count 2 2006.190.07:25:06.57#ibcon#flushed, iclass 37, count 2 2006.190.07:25:06.57#ibcon#about to write, iclass 37, count 2 2006.190.07:25:06.57#ibcon#wrote, iclass 37, count 2 2006.190.07:25:06.57#ibcon#about to read 3, iclass 37, count 2 2006.190.07:25:06.60#ibcon#read 3, iclass 37, count 2 2006.190.07:25:06.60#ibcon#about to read 4, iclass 37, count 2 2006.190.07:25:06.60#ibcon#read 4, iclass 37, count 2 2006.190.07:25:06.60#ibcon#about to read 5, iclass 37, count 2 2006.190.07:25:06.60#ibcon#read 5, iclass 37, count 2 2006.190.07:25:06.60#ibcon#about to read 6, iclass 37, count 2 2006.190.07:25:06.60#ibcon#read 6, iclass 37, count 2 2006.190.07:25:06.60#ibcon#end of sib2, iclass 37, count 2 2006.190.07:25:06.60#ibcon#*after write, iclass 37, count 2 2006.190.07:25:06.60#ibcon#*before return 0, iclass 37, count 2 2006.190.07:25:06.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:25:06.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:25:06.60#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.07:25:06.60#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:06.60#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:25:06.72#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:25:06.72#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:25:06.72#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:25:06.72#ibcon#first serial, iclass 37, count 0 2006.190.07:25:06.72#ibcon#enter sib2, iclass 37, count 0 2006.190.07:25:06.72#ibcon#flushed, iclass 37, count 0 2006.190.07:25:06.72#ibcon#about to write, iclass 37, count 0 2006.190.07:25:06.72#ibcon#wrote, iclass 37, count 0 2006.190.07:25:06.72#ibcon#about to read 3, iclass 37, count 0 2006.190.07:25:06.74#ibcon#read 3, iclass 37, count 0 2006.190.07:25:06.74#ibcon#about to read 4, iclass 37, count 0 2006.190.07:25:06.74#ibcon#read 4, iclass 37, count 0 2006.190.07:25:06.74#ibcon#about to read 5, iclass 37, count 0 2006.190.07:25:06.74#ibcon#read 5, iclass 37, count 0 2006.190.07:25:06.74#ibcon#about to read 6, iclass 37, count 0 2006.190.07:25:06.74#ibcon#read 6, iclass 37, count 0 2006.190.07:25:06.74#ibcon#end of sib2, iclass 37, count 0 2006.190.07:25:06.74#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:25:06.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:25:06.74#ibcon#[27=USB\r\n] 2006.190.07:25:06.74#ibcon#*before write, iclass 37, count 0 2006.190.07:25:06.74#ibcon#enter sib2, iclass 37, count 0 2006.190.07:25:06.74#ibcon#flushed, iclass 37, count 0 2006.190.07:25:06.74#ibcon#about to write, iclass 37, count 0 2006.190.07:25:06.74#ibcon#wrote, iclass 37, count 0 2006.190.07:25:06.74#ibcon#about to read 3, iclass 37, count 0 2006.190.07:25:06.77#ibcon#read 3, iclass 37, count 0 2006.190.07:25:06.77#ibcon#about to read 4, iclass 37, count 0 2006.190.07:25:06.77#ibcon#read 4, iclass 37, count 0 2006.190.07:25:06.77#ibcon#about to read 5, iclass 37, count 0 2006.190.07:25:06.77#ibcon#read 5, iclass 37, count 0 2006.190.07:25:06.77#ibcon#about to read 6, iclass 37, count 0 2006.190.07:25:06.77#ibcon#read 6, iclass 37, count 0 2006.190.07:25:06.77#ibcon#end of sib2, iclass 37, count 0 2006.190.07:25:06.77#ibcon#*after write, iclass 37, count 0 2006.190.07:25:06.77#ibcon#*before return 0, iclass 37, count 0 2006.190.07:25:06.77#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:25:06.77#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:25:06.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:25:06.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:25:06.77$vc4f8/vblo=2,640.99 2006.190.07:25:06.77#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.07:25:06.77#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.07:25:06.77#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:06.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:06.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:06.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:06.77#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:25:06.77#ibcon#first serial, iclass 39, count 0 2006.190.07:25:06.77#ibcon#enter sib2, iclass 39, count 0 2006.190.07:25:06.77#ibcon#flushed, iclass 39, count 0 2006.190.07:25:06.77#ibcon#about to write, iclass 39, count 0 2006.190.07:25:06.77#ibcon#wrote, iclass 39, count 0 2006.190.07:25:06.77#ibcon#about to read 3, iclass 39, count 0 2006.190.07:25:06.79#ibcon#read 3, iclass 39, count 0 2006.190.07:25:06.79#ibcon#about to read 4, iclass 39, count 0 2006.190.07:25:06.79#ibcon#read 4, iclass 39, count 0 2006.190.07:25:06.79#ibcon#about to read 5, iclass 39, count 0 2006.190.07:25:06.79#ibcon#read 5, iclass 39, count 0 2006.190.07:25:06.79#ibcon#about to read 6, iclass 39, count 0 2006.190.07:25:06.79#ibcon#read 6, iclass 39, count 0 2006.190.07:25:06.79#ibcon#end of sib2, iclass 39, count 0 2006.190.07:25:06.79#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:25:06.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:25:06.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:25:06.79#ibcon#*before write, iclass 39, count 0 2006.190.07:25:06.79#ibcon#enter sib2, iclass 39, count 0 2006.190.07:25:06.79#ibcon#flushed, iclass 39, count 0 2006.190.07:25:06.79#ibcon#about to write, iclass 39, count 0 2006.190.07:25:06.79#ibcon#wrote, iclass 39, count 0 2006.190.07:25:06.79#ibcon#about to read 3, iclass 39, count 0 2006.190.07:25:06.83#ibcon#read 3, iclass 39, count 0 2006.190.07:25:06.83#ibcon#about to read 4, iclass 39, count 0 2006.190.07:25:06.83#ibcon#read 4, iclass 39, count 0 2006.190.07:25:06.83#ibcon#about to read 5, iclass 39, count 0 2006.190.07:25:06.83#ibcon#read 5, iclass 39, count 0 2006.190.07:25:06.83#ibcon#about to read 6, iclass 39, count 0 2006.190.07:25:06.83#ibcon#read 6, iclass 39, count 0 2006.190.07:25:06.83#ibcon#end of sib2, iclass 39, count 0 2006.190.07:25:06.83#ibcon#*after write, iclass 39, count 0 2006.190.07:25:06.83#ibcon#*before return 0, iclass 39, count 0 2006.190.07:25:06.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:06.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:25:06.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:25:06.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:25:06.83$vc4f8/vb=2,4 2006.190.07:25:06.83#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.07:25:06.83#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.07:25:06.83#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:06.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:06.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:06.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:06.89#ibcon#enter wrdev, iclass 3, count 2 2006.190.07:25:06.89#ibcon#first serial, iclass 3, count 2 2006.190.07:25:06.89#ibcon#enter sib2, iclass 3, count 2 2006.190.07:25:06.89#ibcon#flushed, iclass 3, count 2 2006.190.07:25:06.89#ibcon#about to write, iclass 3, count 2 2006.190.07:25:06.89#ibcon#wrote, iclass 3, count 2 2006.190.07:25:06.89#ibcon#about to read 3, iclass 3, count 2 2006.190.07:25:06.91#ibcon#read 3, iclass 3, count 2 2006.190.07:25:06.91#ibcon#about to read 4, iclass 3, count 2 2006.190.07:25:06.91#ibcon#read 4, iclass 3, count 2 2006.190.07:25:06.91#ibcon#about to read 5, iclass 3, count 2 2006.190.07:25:06.91#ibcon#read 5, iclass 3, count 2 2006.190.07:25:06.91#ibcon#about to read 6, iclass 3, count 2 2006.190.07:25:06.91#ibcon#read 6, iclass 3, count 2 2006.190.07:25:06.91#ibcon#end of sib2, iclass 3, count 2 2006.190.07:25:06.91#ibcon#*mode == 0, iclass 3, count 2 2006.190.07:25:06.91#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.07:25:06.91#ibcon#[27=AT02-04\r\n] 2006.190.07:25:06.91#ibcon#*before write, iclass 3, count 2 2006.190.07:25:06.91#ibcon#enter sib2, iclass 3, count 2 2006.190.07:25:06.91#ibcon#flushed, iclass 3, count 2 2006.190.07:25:06.91#ibcon#about to write, iclass 3, count 2 2006.190.07:25:06.91#ibcon#wrote, iclass 3, count 2 2006.190.07:25:06.91#ibcon#about to read 3, iclass 3, count 2 2006.190.07:25:06.94#ibcon#read 3, iclass 3, count 2 2006.190.07:25:06.94#ibcon#about to read 4, iclass 3, count 2 2006.190.07:25:06.94#ibcon#read 4, iclass 3, count 2 2006.190.07:25:06.94#ibcon#about to read 5, iclass 3, count 2 2006.190.07:25:06.94#ibcon#read 5, iclass 3, count 2 2006.190.07:25:06.94#ibcon#about to read 6, iclass 3, count 2 2006.190.07:25:06.94#ibcon#read 6, iclass 3, count 2 2006.190.07:25:06.94#ibcon#end of sib2, iclass 3, count 2 2006.190.07:25:06.94#ibcon#*after write, iclass 3, count 2 2006.190.07:25:06.94#ibcon#*before return 0, iclass 3, count 2 2006.190.07:25:06.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:06.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:25:06.94#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.07:25:06.94#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:06.94#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:07.06#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:07.06#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:07.06#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:25:07.06#ibcon#first serial, iclass 3, count 0 2006.190.07:25:07.06#ibcon#enter sib2, iclass 3, count 0 2006.190.07:25:07.06#ibcon#flushed, iclass 3, count 0 2006.190.07:25:07.06#ibcon#about to write, iclass 3, count 0 2006.190.07:25:07.06#ibcon#wrote, iclass 3, count 0 2006.190.07:25:07.06#ibcon#about to read 3, iclass 3, count 0 2006.190.07:25:07.08#ibcon#read 3, iclass 3, count 0 2006.190.07:25:07.08#ibcon#about to read 4, iclass 3, count 0 2006.190.07:25:07.08#ibcon#read 4, iclass 3, count 0 2006.190.07:25:07.08#ibcon#about to read 5, iclass 3, count 0 2006.190.07:25:07.08#ibcon#read 5, iclass 3, count 0 2006.190.07:25:07.08#ibcon#about to read 6, iclass 3, count 0 2006.190.07:25:07.08#ibcon#read 6, iclass 3, count 0 2006.190.07:25:07.08#ibcon#end of sib2, iclass 3, count 0 2006.190.07:25:07.08#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:25:07.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:25:07.08#ibcon#[27=USB\r\n] 2006.190.07:25:07.08#ibcon#*before write, iclass 3, count 0 2006.190.07:25:07.08#ibcon#enter sib2, iclass 3, count 0 2006.190.07:25:07.08#ibcon#flushed, iclass 3, count 0 2006.190.07:25:07.08#ibcon#about to write, iclass 3, count 0 2006.190.07:25:07.08#ibcon#wrote, iclass 3, count 0 2006.190.07:25:07.08#ibcon#about to read 3, iclass 3, count 0 2006.190.07:25:07.11#ibcon#read 3, iclass 3, count 0 2006.190.07:25:07.11#ibcon#about to read 4, iclass 3, count 0 2006.190.07:25:07.11#ibcon#read 4, iclass 3, count 0 2006.190.07:25:07.11#ibcon#about to read 5, iclass 3, count 0 2006.190.07:25:07.11#ibcon#read 5, iclass 3, count 0 2006.190.07:25:07.11#ibcon#about to read 6, iclass 3, count 0 2006.190.07:25:07.11#ibcon#read 6, iclass 3, count 0 2006.190.07:25:07.11#ibcon#end of sib2, iclass 3, count 0 2006.190.07:25:07.11#ibcon#*after write, iclass 3, count 0 2006.190.07:25:07.11#ibcon#*before return 0, iclass 3, count 0 2006.190.07:25:07.11#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:07.11#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:25:07.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:25:07.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:25:07.11$vc4f8/vblo=3,656.99 2006.190.07:25:07.11#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.07:25:07.11#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.07:25:07.11#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:07.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:07.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:07.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:07.11#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:25:07.11#ibcon#first serial, iclass 5, count 0 2006.190.07:25:07.11#ibcon#enter sib2, iclass 5, count 0 2006.190.07:25:07.11#ibcon#flushed, iclass 5, count 0 2006.190.07:25:07.11#ibcon#about to write, iclass 5, count 0 2006.190.07:25:07.11#ibcon#wrote, iclass 5, count 0 2006.190.07:25:07.11#ibcon#about to read 3, iclass 5, count 0 2006.190.07:25:07.13#ibcon#read 3, iclass 5, count 0 2006.190.07:25:07.13#ibcon#about to read 4, iclass 5, count 0 2006.190.07:25:07.13#ibcon#read 4, iclass 5, count 0 2006.190.07:25:07.13#ibcon#about to read 5, iclass 5, count 0 2006.190.07:25:07.13#ibcon#read 5, iclass 5, count 0 2006.190.07:25:07.13#ibcon#about to read 6, iclass 5, count 0 2006.190.07:25:07.13#ibcon#read 6, iclass 5, count 0 2006.190.07:25:07.13#ibcon#end of sib2, iclass 5, count 0 2006.190.07:25:07.13#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:25:07.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:25:07.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:25:07.13#ibcon#*before write, iclass 5, count 0 2006.190.07:25:07.13#ibcon#enter sib2, iclass 5, count 0 2006.190.07:25:07.13#ibcon#flushed, iclass 5, count 0 2006.190.07:25:07.13#ibcon#about to write, iclass 5, count 0 2006.190.07:25:07.13#ibcon#wrote, iclass 5, count 0 2006.190.07:25:07.13#ibcon#about to read 3, iclass 5, count 0 2006.190.07:25:07.17#ibcon#read 3, iclass 5, count 0 2006.190.07:25:07.17#ibcon#about to read 4, iclass 5, count 0 2006.190.07:25:07.17#ibcon#read 4, iclass 5, count 0 2006.190.07:25:07.17#ibcon#about to read 5, iclass 5, count 0 2006.190.07:25:07.17#ibcon#read 5, iclass 5, count 0 2006.190.07:25:07.17#ibcon#about to read 6, iclass 5, count 0 2006.190.07:25:07.17#ibcon#read 6, iclass 5, count 0 2006.190.07:25:07.17#ibcon#end of sib2, iclass 5, count 0 2006.190.07:25:07.17#ibcon#*after write, iclass 5, count 0 2006.190.07:25:07.17#ibcon#*before return 0, iclass 5, count 0 2006.190.07:25:07.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:07.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:25:07.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:25:07.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:25:07.17$vc4f8/vb=3,4 2006.190.07:25:07.17#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.07:25:07.17#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.07:25:07.17#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:07.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:07.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:07.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:07.23#ibcon#enter wrdev, iclass 7, count 2 2006.190.07:25:07.23#ibcon#first serial, iclass 7, count 2 2006.190.07:25:07.23#ibcon#enter sib2, iclass 7, count 2 2006.190.07:25:07.23#ibcon#flushed, iclass 7, count 2 2006.190.07:25:07.23#ibcon#about to write, iclass 7, count 2 2006.190.07:25:07.23#ibcon#wrote, iclass 7, count 2 2006.190.07:25:07.23#ibcon#about to read 3, iclass 7, count 2 2006.190.07:25:07.25#ibcon#read 3, iclass 7, count 2 2006.190.07:25:07.25#ibcon#about to read 4, iclass 7, count 2 2006.190.07:25:07.25#ibcon#read 4, iclass 7, count 2 2006.190.07:25:07.25#ibcon#about to read 5, iclass 7, count 2 2006.190.07:25:07.25#ibcon#read 5, iclass 7, count 2 2006.190.07:25:07.25#ibcon#about to read 6, iclass 7, count 2 2006.190.07:25:07.25#ibcon#read 6, iclass 7, count 2 2006.190.07:25:07.25#ibcon#end of sib2, iclass 7, count 2 2006.190.07:25:07.25#ibcon#*mode == 0, iclass 7, count 2 2006.190.07:25:07.25#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.07:25:07.25#ibcon#[27=AT03-04\r\n] 2006.190.07:25:07.25#ibcon#*before write, iclass 7, count 2 2006.190.07:25:07.25#ibcon#enter sib2, iclass 7, count 2 2006.190.07:25:07.25#ibcon#flushed, iclass 7, count 2 2006.190.07:25:07.25#ibcon#about to write, iclass 7, count 2 2006.190.07:25:07.25#ibcon#wrote, iclass 7, count 2 2006.190.07:25:07.25#ibcon#about to read 3, iclass 7, count 2 2006.190.07:25:07.28#ibcon#read 3, iclass 7, count 2 2006.190.07:25:07.28#ibcon#about to read 4, iclass 7, count 2 2006.190.07:25:07.28#ibcon#read 4, iclass 7, count 2 2006.190.07:25:07.28#ibcon#about to read 5, iclass 7, count 2 2006.190.07:25:07.28#ibcon#read 5, iclass 7, count 2 2006.190.07:25:07.28#ibcon#about to read 6, iclass 7, count 2 2006.190.07:25:07.28#ibcon#read 6, iclass 7, count 2 2006.190.07:25:07.28#ibcon#end of sib2, iclass 7, count 2 2006.190.07:25:07.28#ibcon#*after write, iclass 7, count 2 2006.190.07:25:07.28#ibcon#*before return 0, iclass 7, count 2 2006.190.07:25:07.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:07.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:25:07.28#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.07:25:07.28#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:07.28#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:07.40#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:07.40#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:07.40#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:25:07.40#ibcon#first serial, iclass 7, count 0 2006.190.07:25:07.40#ibcon#enter sib2, iclass 7, count 0 2006.190.07:25:07.40#ibcon#flushed, iclass 7, count 0 2006.190.07:25:07.40#ibcon#about to write, iclass 7, count 0 2006.190.07:25:07.40#ibcon#wrote, iclass 7, count 0 2006.190.07:25:07.40#ibcon#about to read 3, iclass 7, count 0 2006.190.07:25:07.42#ibcon#read 3, iclass 7, count 0 2006.190.07:25:07.42#ibcon#about to read 4, iclass 7, count 0 2006.190.07:25:07.42#ibcon#read 4, iclass 7, count 0 2006.190.07:25:07.42#ibcon#about to read 5, iclass 7, count 0 2006.190.07:25:07.42#ibcon#read 5, iclass 7, count 0 2006.190.07:25:07.42#ibcon#about to read 6, iclass 7, count 0 2006.190.07:25:07.42#ibcon#read 6, iclass 7, count 0 2006.190.07:25:07.42#ibcon#end of sib2, iclass 7, count 0 2006.190.07:25:07.42#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:25:07.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:25:07.42#ibcon#[27=USB\r\n] 2006.190.07:25:07.42#ibcon#*before write, iclass 7, count 0 2006.190.07:25:07.42#ibcon#enter sib2, iclass 7, count 0 2006.190.07:25:07.42#ibcon#flushed, iclass 7, count 0 2006.190.07:25:07.42#ibcon#about to write, iclass 7, count 0 2006.190.07:25:07.42#ibcon#wrote, iclass 7, count 0 2006.190.07:25:07.42#ibcon#about to read 3, iclass 7, count 0 2006.190.07:25:07.45#ibcon#read 3, iclass 7, count 0 2006.190.07:25:07.45#ibcon#about to read 4, iclass 7, count 0 2006.190.07:25:07.45#ibcon#read 4, iclass 7, count 0 2006.190.07:25:07.45#ibcon#about to read 5, iclass 7, count 0 2006.190.07:25:07.45#ibcon#read 5, iclass 7, count 0 2006.190.07:25:07.45#ibcon#about to read 6, iclass 7, count 0 2006.190.07:25:07.45#ibcon#read 6, iclass 7, count 0 2006.190.07:25:07.45#ibcon#end of sib2, iclass 7, count 0 2006.190.07:25:07.45#ibcon#*after write, iclass 7, count 0 2006.190.07:25:07.45#ibcon#*before return 0, iclass 7, count 0 2006.190.07:25:07.45#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:07.45#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:25:07.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:25:07.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:25:07.45$vc4f8/vblo=4,712.99 2006.190.07:25:07.45#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.07:25:07.45#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.07:25:07.45#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:07.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:07.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:07.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:07.45#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:25:07.45#ibcon#first serial, iclass 11, count 0 2006.190.07:25:07.45#ibcon#enter sib2, iclass 11, count 0 2006.190.07:25:07.45#ibcon#flushed, iclass 11, count 0 2006.190.07:25:07.45#ibcon#about to write, iclass 11, count 0 2006.190.07:25:07.45#ibcon#wrote, iclass 11, count 0 2006.190.07:25:07.45#ibcon#about to read 3, iclass 11, count 0 2006.190.07:25:07.47#ibcon#read 3, iclass 11, count 0 2006.190.07:25:07.47#ibcon#about to read 4, iclass 11, count 0 2006.190.07:25:07.47#ibcon#read 4, iclass 11, count 0 2006.190.07:25:07.47#ibcon#about to read 5, iclass 11, count 0 2006.190.07:25:07.47#ibcon#read 5, iclass 11, count 0 2006.190.07:25:07.47#ibcon#about to read 6, iclass 11, count 0 2006.190.07:25:07.47#ibcon#read 6, iclass 11, count 0 2006.190.07:25:07.47#ibcon#end of sib2, iclass 11, count 0 2006.190.07:25:07.47#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:25:07.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:25:07.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:25:07.47#ibcon#*before write, iclass 11, count 0 2006.190.07:25:07.47#ibcon#enter sib2, iclass 11, count 0 2006.190.07:25:07.47#ibcon#flushed, iclass 11, count 0 2006.190.07:25:07.47#ibcon#about to write, iclass 11, count 0 2006.190.07:25:07.47#ibcon#wrote, iclass 11, count 0 2006.190.07:25:07.47#ibcon#about to read 3, iclass 11, count 0 2006.190.07:25:07.51#ibcon#read 3, iclass 11, count 0 2006.190.07:25:07.51#ibcon#about to read 4, iclass 11, count 0 2006.190.07:25:07.51#ibcon#read 4, iclass 11, count 0 2006.190.07:25:07.51#ibcon#about to read 5, iclass 11, count 0 2006.190.07:25:07.51#ibcon#read 5, iclass 11, count 0 2006.190.07:25:07.51#ibcon#about to read 6, iclass 11, count 0 2006.190.07:25:07.51#ibcon#read 6, iclass 11, count 0 2006.190.07:25:07.51#ibcon#end of sib2, iclass 11, count 0 2006.190.07:25:07.51#ibcon#*after write, iclass 11, count 0 2006.190.07:25:07.51#ibcon#*before return 0, iclass 11, count 0 2006.190.07:25:07.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:07.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:25:07.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:25:07.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:25:07.51$vc4f8/vb=4,4 2006.190.07:25:07.51#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.07:25:07.51#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.07:25:07.51#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:07.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:07.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:07.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:07.57#ibcon#enter wrdev, iclass 13, count 2 2006.190.07:25:07.57#ibcon#first serial, iclass 13, count 2 2006.190.07:25:07.57#ibcon#enter sib2, iclass 13, count 2 2006.190.07:25:07.57#ibcon#flushed, iclass 13, count 2 2006.190.07:25:07.57#ibcon#about to write, iclass 13, count 2 2006.190.07:25:07.57#ibcon#wrote, iclass 13, count 2 2006.190.07:25:07.57#ibcon#about to read 3, iclass 13, count 2 2006.190.07:25:07.59#ibcon#read 3, iclass 13, count 2 2006.190.07:25:07.59#ibcon#about to read 4, iclass 13, count 2 2006.190.07:25:07.59#ibcon#read 4, iclass 13, count 2 2006.190.07:25:07.59#ibcon#about to read 5, iclass 13, count 2 2006.190.07:25:07.59#ibcon#read 5, iclass 13, count 2 2006.190.07:25:07.59#ibcon#about to read 6, iclass 13, count 2 2006.190.07:25:07.59#ibcon#read 6, iclass 13, count 2 2006.190.07:25:07.59#ibcon#end of sib2, iclass 13, count 2 2006.190.07:25:07.59#ibcon#*mode == 0, iclass 13, count 2 2006.190.07:25:07.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.07:25:07.59#ibcon#[27=AT04-04\r\n] 2006.190.07:25:07.59#ibcon#*before write, iclass 13, count 2 2006.190.07:25:07.59#ibcon#enter sib2, iclass 13, count 2 2006.190.07:25:07.59#ibcon#flushed, iclass 13, count 2 2006.190.07:25:07.59#ibcon#about to write, iclass 13, count 2 2006.190.07:25:07.59#ibcon#wrote, iclass 13, count 2 2006.190.07:25:07.59#ibcon#about to read 3, iclass 13, count 2 2006.190.07:25:07.62#ibcon#read 3, iclass 13, count 2 2006.190.07:25:07.62#ibcon#about to read 4, iclass 13, count 2 2006.190.07:25:07.62#ibcon#read 4, iclass 13, count 2 2006.190.07:25:07.62#ibcon#about to read 5, iclass 13, count 2 2006.190.07:25:07.62#ibcon#read 5, iclass 13, count 2 2006.190.07:25:07.62#ibcon#about to read 6, iclass 13, count 2 2006.190.07:25:07.62#ibcon#read 6, iclass 13, count 2 2006.190.07:25:07.62#ibcon#end of sib2, iclass 13, count 2 2006.190.07:25:07.62#ibcon#*after write, iclass 13, count 2 2006.190.07:25:07.62#ibcon#*before return 0, iclass 13, count 2 2006.190.07:25:07.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:07.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:25:07.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.07:25:07.62#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:07.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:07.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:07.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:07.74#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:25:07.74#ibcon#first serial, iclass 13, count 0 2006.190.07:25:07.74#ibcon#enter sib2, iclass 13, count 0 2006.190.07:25:07.74#ibcon#flushed, iclass 13, count 0 2006.190.07:25:07.74#ibcon#about to write, iclass 13, count 0 2006.190.07:25:07.74#ibcon#wrote, iclass 13, count 0 2006.190.07:25:07.74#ibcon#about to read 3, iclass 13, count 0 2006.190.07:25:07.76#ibcon#read 3, iclass 13, count 0 2006.190.07:25:07.76#ibcon#about to read 4, iclass 13, count 0 2006.190.07:25:07.76#ibcon#read 4, iclass 13, count 0 2006.190.07:25:07.76#ibcon#about to read 5, iclass 13, count 0 2006.190.07:25:07.76#ibcon#read 5, iclass 13, count 0 2006.190.07:25:07.76#ibcon#about to read 6, iclass 13, count 0 2006.190.07:25:07.76#ibcon#read 6, iclass 13, count 0 2006.190.07:25:07.76#ibcon#end of sib2, iclass 13, count 0 2006.190.07:25:07.76#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:25:07.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:25:07.76#ibcon#[27=USB\r\n] 2006.190.07:25:07.76#ibcon#*before write, iclass 13, count 0 2006.190.07:25:07.76#ibcon#enter sib2, iclass 13, count 0 2006.190.07:25:07.76#ibcon#flushed, iclass 13, count 0 2006.190.07:25:07.76#ibcon#about to write, iclass 13, count 0 2006.190.07:25:07.76#ibcon#wrote, iclass 13, count 0 2006.190.07:25:07.76#ibcon#about to read 3, iclass 13, count 0 2006.190.07:25:07.79#ibcon#read 3, iclass 13, count 0 2006.190.07:25:07.79#ibcon#about to read 4, iclass 13, count 0 2006.190.07:25:07.79#ibcon#read 4, iclass 13, count 0 2006.190.07:25:07.79#ibcon#about to read 5, iclass 13, count 0 2006.190.07:25:07.79#ibcon#read 5, iclass 13, count 0 2006.190.07:25:07.79#ibcon#about to read 6, iclass 13, count 0 2006.190.07:25:07.79#ibcon#read 6, iclass 13, count 0 2006.190.07:25:07.79#ibcon#end of sib2, iclass 13, count 0 2006.190.07:25:07.79#ibcon#*after write, iclass 13, count 0 2006.190.07:25:07.79#ibcon#*before return 0, iclass 13, count 0 2006.190.07:25:07.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:07.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:25:07.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:25:07.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:25:07.79$vc4f8/vblo=5,744.99 2006.190.07:25:07.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:25:07.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:25:07.79#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:07.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:07.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:07.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:07.79#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:25:07.79#ibcon#first serial, iclass 15, count 0 2006.190.07:25:07.79#ibcon#enter sib2, iclass 15, count 0 2006.190.07:25:07.79#ibcon#flushed, iclass 15, count 0 2006.190.07:25:07.79#ibcon#about to write, iclass 15, count 0 2006.190.07:25:07.79#ibcon#wrote, iclass 15, count 0 2006.190.07:25:07.79#ibcon#about to read 3, iclass 15, count 0 2006.190.07:25:07.81#ibcon#read 3, iclass 15, count 0 2006.190.07:25:07.81#ibcon#about to read 4, iclass 15, count 0 2006.190.07:25:07.81#ibcon#read 4, iclass 15, count 0 2006.190.07:25:07.81#ibcon#about to read 5, iclass 15, count 0 2006.190.07:25:07.81#ibcon#read 5, iclass 15, count 0 2006.190.07:25:07.81#ibcon#about to read 6, iclass 15, count 0 2006.190.07:25:07.81#ibcon#read 6, iclass 15, count 0 2006.190.07:25:07.81#ibcon#end of sib2, iclass 15, count 0 2006.190.07:25:07.81#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:25:07.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:25:07.81#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:25:07.81#ibcon#*before write, iclass 15, count 0 2006.190.07:25:07.81#ibcon#enter sib2, iclass 15, count 0 2006.190.07:25:07.81#ibcon#flushed, iclass 15, count 0 2006.190.07:25:07.81#ibcon#about to write, iclass 15, count 0 2006.190.07:25:07.81#ibcon#wrote, iclass 15, count 0 2006.190.07:25:07.81#ibcon#about to read 3, iclass 15, count 0 2006.190.07:25:07.85#ibcon#read 3, iclass 15, count 0 2006.190.07:25:07.85#ibcon#about to read 4, iclass 15, count 0 2006.190.07:25:07.85#ibcon#read 4, iclass 15, count 0 2006.190.07:25:07.85#ibcon#about to read 5, iclass 15, count 0 2006.190.07:25:07.85#ibcon#read 5, iclass 15, count 0 2006.190.07:25:07.85#ibcon#about to read 6, iclass 15, count 0 2006.190.07:25:07.85#ibcon#read 6, iclass 15, count 0 2006.190.07:25:07.85#ibcon#end of sib2, iclass 15, count 0 2006.190.07:25:07.85#ibcon#*after write, iclass 15, count 0 2006.190.07:25:07.85#ibcon#*before return 0, iclass 15, count 0 2006.190.07:25:07.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:07.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:25:07.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:25:07.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:25:07.85$vc4f8/vb=5,4 2006.190.07:25:07.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.07:25:07.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.07:25:07.85#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:07.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:07.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:07.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:07.91#ibcon#enter wrdev, iclass 17, count 2 2006.190.07:25:07.91#ibcon#first serial, iclass 17, count 2 2006.190.07:25:07.91#ibcon#enter sib2, iclass 17, count 2 2006.190.07:25:07.91#ibcon#flushed, iclass 17, count 2 2006.190.07:25:07.91#ibcon#about to write, iclass 17, count 2 2006.190.07:25:07.91#ibcon#wrote, iclass 17, count 2 2006.190.07:25:07.91#ibcon#about to read 3, iclass 17, count 2 2006.190.07:25:07.93#ibcon#read 3, iclass 17, count 2 2006.190.07:25:07.93#ibcon#about to read 4, iclass 17, count 2 2006.190.07:25:07.93#ibcon#read 4, iclass 17, count 2 2006.190.07:25:07.93#ibcon#about to read 5, iclass 17, count 2 2006.190.07:25:07.93#ibcon#read 5, iclass 17, count 2 2006.190.07:25:07.93#ibcon#about to read 6, iclass 17, count 2 2006.190.07:25:07.93#ibcon#read 6, iclass 17, count 2 2006.190.07:25:07.93#ibcon#end of sib2, iclass 17, count 2 2006.190.07:25:07.93#ibcon#*mode == 0, iclass 17, count 2 2006.190.07:25:07.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.07:25:07.93#ibcon#[27=AT05-04\r\n] 2006.190.07:25:07.93#ibcon#*before write, iclass 17, count 2 2006.190.07:25:07.93#ibcon#enter sib2, iclass 17, count 2 2006.190.07:25:07.93#ibcon#flushed, iclass 17, count 2 2006.190.07:25:07.93#ibcon#about to write, iclass 17, count 2 2006.190.07:25:07.93#ibcon#wrote, iclass 17, count 2 2006.190.07:25:07.93#ibcon#about to read 3, iclass 17, count 2 2006.190.07:25:07.96#ibcon#read 3, iclass 17, count 2 2006.190.07:25:07.96#ibcon#about to read 4, iclass 17, count 2 2006.190.07:25:07.96#ibcon#read 4, iclass 17, count 2 2006.190.07:25:07.96#ibcon#about to read 5, iclass 17, count 2 2006.190.07:25:07.96#ibcon#read 5, iclass 17, count 2 2006.190.07:25:07.96#ibcon#about to read 6, iclass 17, count 2 2006.190.07:25:07.96#ibcon#read 6, iclass 17, count 2 2006.190.07:25:07.96#ibcon#end of sib2, iclass 17, count 2 2006.190.07:25:07.96#ibcon#*after write, iclass 17, count 2 2006.190.07:25:07.96#ibcon#*before return 0, iclass 17, count 2 2006.190.07:25:07.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:07.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:25:07.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.07:25:07.96#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:07.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:08.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:08.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:08.08#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:25:08.08#ibcon#first serial, iclass 17, count 0 2006.190.07:25:08.08#ibcon#enter sib2, iclass 17, count 0 2006.190.07:25:08.08#ibcon#flushed, iclass 17, count 0 2006.190.07:25:08.08#ibcon#about to write, iclass 17, count 0 2006.190.07:25:08.08#ibcon#wrote, iclass 17, count 0 2006.190.07:25:08.08#ibcon#about to read 3, iclass 17, count 0 2006.190.07:25:08.10#ibcon#read 3, iclass 17, count 0 2006.190.07:25:08.10#ibcon#about to read 4, iclass 17, count 0 2006.190.07:25:08.10#ibcon#read 4, iclass 17, count 0 2006.190.07:25:08.10#ibcon#about to read 5, iclass 17, count 0 2006.190.07:25:08.10#ibcon#read 5, iclass 17, count 0 2006.190.07:25:08.10#ibcon#about to read 6, iclass 17, count 0 2006.190.07:25:08.10#ibcon#read 6, iclass 17, count 0 2006.190.07:25:08.10#ibcon#end of sib2, iclass 17, count 0 2006.190.07:25:08.10#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:25:08.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:25:08.10#ibcon#[27=USB\r\n] 2006.190.07:25:08.10#ibcon#*before write, iclass 17, count 0 2006.190.07:25:08.10#ibcon#enter sib2, iclass 17, count 0 2006.190.07:25:08.10#ibcon#flushed, iclass 17, count 0 2006.190.07:25:08.10#ibcon#about to write, iclass 17, count 0 2006.190.07:25:08.10#ibcon#wrote, iclass 17, count 0 2006.190.07:25:08.10#ibcon#about to read 3, iclass 17, count 0 2006.190.07:25:08.13#ibcon#read 3, iclass 17, count 0 2006.190.07:25:08.13#ibcon#about to read 4, iclass 17, count 0 2006.190.07:25:08.13#ibcon#read 4, iclass 17, count 0 2006.190.07:25:08.13#ibcon#about to read 5, iclass 17, count 0 2006.190.07:25:08.13#ibcon#read 5, iclass 17, count 0 2006.190.07:25:08.13#ibcon#about to read 6, iclass 17, count 0 2006.190.07:25:08.13#ibcon#read 6, iclass 17, count 0 2006.190.07:25:08.13#ibcon#end of sib2, iclass 17, count 0 2006.190.07:25:08.13#ibcon#*after write, iclass 17, count 0 2006.190.07:25:08.13#ibcon#*before return 0, iclass 17, count 0 2006.190.07:25:08.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:08.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:25:08.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:25:08.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:25:08.13$vc4f8/vblo=6,752.99 2006.190.07:25:08.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:25:08.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:25:08.13#ibcon#ireg 17 cls_cnt 0 2006.190.07:25:08.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:08.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:08.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:08.13#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:25:08.13#ibcon#first serial, iclass 19, count 0 2006.190.07:25:08.13#ibcon#enter sib2, iclass 19, count 0 2006.190.07:25:08.13#ibcon#flushed, iclass 19, count 0 2006.190.07:25:08.13#ibcon#about to write, iclass 19, count 0 2006.190.07:25:08.13#ibcon#wrote, iclass 19, count 0 2006.190.07:25:08.13#ibcon#about to read 3, iclass 19, count 0 2006.190.07:25:08.15#ibcon#read 3, iclass 19, count 0 2006.190.07:25:08.15#ibcon#about to read 4, iclass 19, count 0 2006.190.07:25:08.15#ibcon#read 4, iclass 19, count 0 2006.190.07:25:08.15#ibcon#about to read 5, iclass 19, count 0 2006.190.07:25:08.15#ibcon#read 5, iclass 19, count 0 2006.190.07:25:08.15#ibcon#about to read 6, iclass 19, count 0 2006.190.07:25:08.15#ibcon#read 6, iclass 19, count 0 2006.190.07:25:08.15#ibcon#end of sib2, iclass 19, count 0 2006.190.07:25:08.15#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:25:08.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:25:08.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:25:08.15#ibcon#*before write, iclass 19, count 0 2006.190.07:25:08.15#ibcon#enter sib2, iclass 19, count 0 2006.190.07:25:08.15#ibcon#flushed, iclass 19, count 0 2006.190.07:25:08.15#ibcon#about to write, iclass 19, count 0 2006.190.07:25:08.15#ibcon#wrote, iclass 19, count 0 2006.190.07:25:08.15#ibcon#about to read 3, iclass 19, count 0 2006.190.07:25:08.19#ibcon#read 3, iclass 19, count 0 2006.190.07:25:08.19#ibcon#about to read 4, iclass 19, count 0 2006.190.07:25:08.19#ibcon#read 4, iclass 19, count 0 2006.190.07:25:08.19#ibcon#about to read 5, iclass 19, count 0 2006.190.07:25:08.19#ibcon#read 5, iclass 19, count 0 2006.190.07:25:08.19#ibcon#about to read 6, iclass 19, count 0 2006.190.07:25:08.19#ibcon#read 6, iclass 19, count 0 2006.190.07:25:08.19#ibcon#end of sib2, iclass 19, count 0 2006.190.07:25:08.19#ibcon#*after write, iclass 19, count 0 2006.190.07:25:08.19#ibcon#*before return 0, iclass 19, count 0 2006.190.07:25:08.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:08.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:25:08.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:25:08.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:25:08.19$vc4f8/vb=6,4 2006.190.07:25:08.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.07:25:08.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.07:25:08.19#ibcon#ireg 11 cls_cnt 2 2006.190.07:25:08.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:08.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:08.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:08.25#ibcon#enter wrdev, iclass 21, count 2 2006.190.07:25:08.25#ibcon#first serial, iclass 21, count 2 2006.190.07:25:08.25#ibcon#enter sib2, iclass 21, count 2 2006.190.07:25:08.25#ibcon#flushed, iclass 21, count 2 2006.190.07:25:08.25#ibcon#about to write, iclass 21, count 2 2006.190.07:25:08.25#ibcon#wrote, iclass 21, count 2 2006.190.07:25:08.25#ibcon#about to read 3, iclass 21, count 2 2006.190.07:25:08.27#ibcon#read 3, iclass 21, count 2 2006.190.07:25:08.27#ibcon#about to read 4, iclass 21, count 2 2006.190.07:25:08.27#ibcon#read 4, iclass 21, count 2 2006.190.07:25:08.27#ibcon#about to read 5, iclass 21, count 2 2006.190.07:25:08.27#ibcon#read 5, iclass 21, count 2 2006.190.07:25:08.27#ibcon#about to read 6, iclass 21, count 2 2006.190.07:25:08.27#ibcon#read 6, iclass 21, count 2 2006.190.07:25:08.27#ibcon#end of sib2, iclass 21, count 2 2006.190.07:25:08.27#ibcon#*mode == 0, iclass 21, count 2 2006.190.07:25:08.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.07:25:08.27#ibcon#[27=AT06-04\r\n] 2006.190.07:25:08.27#ibcon#*before write, iclass 21, count 2 2006.190.07:25:08.27#ibcon#enter sib2, iclass 21, count 2 2006.190.07:25:08.27#ibcon#flushed, iclass 21, count 2 2006.190.07:25:08.27#ibcon#about to write, iclass 21, count 2 2006.190.07:25:08.27#ibcon#wrote, iclass 21, count 2 2006.190.07:25:08.27#ibcon#about to read 3, iclass 21, count 2 2006.190.07:25:08.30#ibcon#read 3, iclass 21, count 2 2006.190.07:25:08.30#ibcon#about to read 4, iclass 21, count 2 2006.190.07:25:08.30#ibcon#read 4, iclass 21, count 2 2006.190.07:25:08.30#ibcon#about to read 5, iclass 21, count 2 2006.190.07:25:08.30#ibcon#read 5, iclass 21, count 2 2006.190.07:25:08.30#ibcon#about to read 6, iclass 21, count 2 2006.190.07:25:08.30#ibcon#read 6, iclass 21, count 2 2006.190.07:25:08.30#ibcon#end of sib2, iclass 21, count 2 2006.190.07:25:08.30#ibcon#*after write, iclass 21, count 2 2006.190.07:25:08.30#ibcon#*before return 0, iclass 21, count 2 2006.190.07:25:08.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:08.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:25:08.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.07:25:08.30#ibcon#ireg 7 cls_cnt 0 2006.190.07:25:08.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:08.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:08.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:08.42#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:25:08.42#ibcon#first serial, iclass 21, count 0 2006.190.07:25:08.42#ibcon#enter sib2, iclass 21, count 0 2006.190.07:25:08.42#ibcon#flushed, iclass 21, count 0 2006.190.07:25:08.42#ibcon#about to write, iclass 21, count 0 2006.190.07:25:08.42#ibcon#wrote, iclass 21, count 0 2006.190.07:25:08.42#ibcon#about to read 3, iclass 21, count 0 2006.190.07:25:08.44#ibcon#read 3, iclass 21, count 0 2006.190.07:25:08.44#ibcon#about to read 4, iclass 21, count 0 2006.190.07:25:08.44#ibcon#read 4, iclass 21, count 0 2006.190.07:25:08.44#ibcon#about to read 5, iclass 21, count 0 2006.190.07:25:08.44#ibcon#read 5, iclass 21, count 0 2006.190.07:25:08.44#ibcon#about to read 6, iclass 21, count 0 2006.190.07:25:08.44#ibcon#read 6, iclass 21, count 0 2006.190.07:25:08.44#ibcon#end of sib2, iclass 21, count 0 2006.190.07:25:08.44#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:25:08.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:25:08.44#ibcon#[27=USB\r\n] 2006.190.07:25:08.44#ibcon#*before write, iclass 21, count 0 2006.190.07:25:08.44#ibcon#enter sib2, iclass 21, count 0 2006.190.07:25:08.44#ibcon#flushed, iclass 21, count 0 2006.190.07:25:08.44#ibcon#about to write, iclass 21, count 0 2006.190.07:25:08.44#ibcon#wrote, iclass 21, count 0 2006.190.07:25:08.44#ibcon#about to read 3, iclass 21, count 0 2006.190.07:25:08.47#ibcon#read 3, iclass 21, count 0 2006.190.07:25:08.47#ibcon#about to read 4, iclass 21, count 0 2006.190.07:25:08.47#ibcon#read 4, iclass 21, count 0 2006.190.07:25:08.47#ibcon#about to read 5, iclass 21, count 0 2006.190.07:25:08.47#ibcon#read 5, iclass 21, count 0 2006.190.07:25:08.47#ibcon#about to read 6, iclass 21, count 0 2006.190.07:25:08.47#ibcon#read 6, iclass 21, count 0 2006.190.07:25:08.47#ibcon#end of sib2, iclass 21, count 0 2006.190.07:25:08.47#ibcon#*after write, iclass 21, count 0 2006.190.07:25:08.47#ibcon#*before return 0, iclass 21, count 0 2006.190.07:25:08.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:08.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:25:08.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:25:08.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:25:08.47$vc4f8/vabw=wide 2006.190.07:25:08.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.07:25:08.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.07:25:08.47#ibcon#ireg 8 cls_cnt 0 2006.190.07:25:08.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:08.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:08.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:08.47#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:25:08.47#ibcon#first serial, iclass 23, count 0 2006.190.07:25:08.47#ibcon#enter sib2, iclass 23, count 0 2006.190.07:25:08.47#ibcon#flushed, iclass 23, count 0 2006.190.07:25:08.47#ibcon#about to write, iclass 23, count 0 2006.190.07:25:08.47#ibcon#wrote, iclass 23, count 0 2006.190.07:25:08.47#ibcon#about to read 3, iclass 23, count 0 2006.190.07:25:08.49#ibcon#read 3, iclass 23, count 0 2006.190.07:25:08.49#ibcon#about to read 4, iclass 23, count 0 2006.190.07:25:08.49#ibcon#read 4, iclass 23, count 0 2006.190.07:25:08.49#ibcon#about to read 5, iclass 23, count 0 2006.190.07:25:08.49#ibcon#read 5, iclass 23, count 0 2006.190.07:25:08.49#ibcon#about to read 6, iclass 23, count 0 2006.190.07:25:08.49#ibcon#read 6, iclass 23, count 0 2006.190.07:25:08.49#ibcon#end of sib2, iclass 23, count 0 2006.190.07:25:08.49#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:25:08.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:25:08.49#ibcon#[25=BW32\r\n] 2006.190.07:25:08.49#ibcon#*before write, iclass 23, count 0 2006.190.07:25:08.49#ibcon#enter sib2, iclass 23, count 0 2006.190.07:25:08.49#ibcon#flushed, iclass 23, count 0 2006.190.07:25:08.49#ibcon#about to write, iclass 23, count 0 2006.190.07:25:08.49#ibcon#wrote, iclass 23, count 0 2006.190.07:25:08.49#ibcon#about to read 3, iclass 23, count 0 2006.190.07:25:08.52#ibcon#read 3, iclass 23, count 0 2006.190.07:25:08.52#ibcon#about to read 4, iclass 23, count 0 2006.190.07:25:08.52#ibcon#read 4, iclass 23, count 0 2006.190.07:25:08.52#ibcon#about to read 5, iclass 23, count 0 2006.190.07:25:08.52#ibcon#read 5, iclass 23, count 0 2006.190.07:25:08.52#ibcon#about to read 6, iclass 23, count 0 2006.190.07:25:08.52#ibcon#read 6, iclass 23, count 0 2006.190.07:25:08.52#ibcon#end of sib2, iclass 23, count 0 2006.190.07:25:08.52#ibcon#*after write, iclass 23, count 0 2006.190.07:25:08.52#ibcon#*before return 0, iclass 23, count 0 2006.190.07:25:08.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:08.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:25:08.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:25:08.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:25:08.52$vc4f8/vbbw=wide 2006.190.07:25:08.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.07:25:08.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.07:25:08.52#ibcon#ireg 8 cls_cnt 0 2006.190.07:25:08.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:25:08.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:25:08.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:25:08.59#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:25:08.59#ibcon#first serial, iclass 25, count 0 2006.190.07:25:08.59#ibcon#enter sib2, iclass 25, count 0 2006.190.07:25:08.59#ibcon#flushed, iclass 25, count 0 2006.190.07:25:08.59#ibcon#about to write, iclass 25, count 0 2006.190.07:25:08.59#ibcon#wrote, iclass 25, count 0 2006.190.07:25:08.59#ibcon#about to read 3, iclass 25, count 0 2006.190.07:25:08.61#ibcon#read 3, iclass 25, count 0 2006.190.07:25:08.61#ibcon#about to read 4, iclass 25, count 0 2006.190.07:25:08.61#ibcon#read 4, iclass 25, count 0 2006.190.07:25:08.61#ibcon#about to read 5, iclass 25, count 0 2006.190.07:25:08.61#ibcon#read 5, iclass 25, count 0 2006.190.07:25:08.61#ibcon#about to read 6, iclass 25, count 0 2006.190.07:25:08.61#ibcon#read 6, iclass 25, count 0 2006.190.07:25:08.61#ibcon#end of sib2, iclass 25, count 0 2006.190.07:25:08.61#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:25:08.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:25:08.61#ibcon#[27=BW32\r\n] 2006.190.07:25:08.61#ibcon#*before write, iclass 25, count 0 2006.190.07:25:08.61#ibcon#enter sib2, iclass 25, count 0 2006.190.07:25:08.61#ibcon#flushed, iclass 25, count 0 2006.190.07:25:08.61#ibcon#about to write, iclass 25, count 0 2006.190.07:25:08.61#ibcon#wrote, iclass 25, count 0 2006.190.07:25:08.61#ibcon#about to read 3, iclass 25, count 0 2006.190.07:25:08.64#ibcon#read 3, iclass 25, count 0 2006.190.07:25:08.64#ibcon#about to read 4, iclass 25, count 0 2006.190.07:25:08.64#ibcon#read 4, iclass 25, count 0 2006.190.07:25:08.64#ibcon#about to read 5, iclass 25, count 0 2006.190.07:25:08.64#ibcon#read 5, iclass 25, count 0 2006.190.07:25:08.64#ibcon#about to read 6, iclass 25, count 0 2006.190.07:25:08.64#ibcon#read 6, iclass 25, count 0 2006.190.07:25:08.64#ibcon#end of sib2, iclass 25, count 0 2006.190.07:25:08.64#ibcon#*after write, iclass 25, count 0 2006.190.07:25:08.64#ibcon#*before return 0, iclass 25, count 0 2006.190.07:25:08.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:25:08.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:25:08.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:25:08.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:25:08.64$4f8m12a/ifd4f 2006.190.07:25:08.64&ifd4f/lo= 2006.190.07:25:08.64&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:25:08.64&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:25:08.64&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:25:08.64&ifd4f/patch= 2006.190.07:25:08.64&ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:25:08.64&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:25:08.64&ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:25:08.64$ifd4f/lo= 2006.190.07:25:08.64$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:25:08.64$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:25:08.64$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:25:08.65$ifd4f/patch= 2006.190.07:25:08.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:25:08.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:25:08.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:25:08.65$4f8m12a/"form=m,16.000,1:2 2006.190.07:25:08.65$4f8m12a/"tpicd 2006.190.07:25:08.65$4f8m12a/echo=off 2006.190.07:25:08.65$4f8m12a/xlog=off 2006.190.07:25:08.65:!2006.190.07:29:50 2006.190.07:29:50.01:preob 2006.190.07:29:50.01&preob/onsource 2006.190.07:29:51.13/onsource/TRACKING 2006.190.07:29:51.13:!2006.190.07:30:00 2006.190.07:30:00.00:data_valid=on 2006.190.07:30:00.00:midob 2006.190.07:30:00.00&midob/onsource 2006.190.07:30:00.00&midob/wx 2006.190.07:30:00.00&midob/cable 2006.190.07:30:00.00&midob/va 2006.190.07:30:00.00&midob/valo 2006.190.07:30:00.00&midob/vb 2006.190.07:30:00.00&midob/vblo 2006.190.07:30:00.00&midob/vabw 2006.190.07:30:00.00&midob/vbbw 2006.190.07:30:00.00&midob/"form 2006.190.07:30:00.00&midob/xfe 2006.190.07:30:00.00&midob/ifatt 2006.190.07:30:00.00&midob/clockoff 2006.190.07:30:00.00&midob/sy=logmail 2006.190.07:30:00.00&midob/"sy=run setcl adapt & 2006.190.07:30:00.13/onsource/TRACKING 2006.190.07:30:00.13/wx/24.60,1012.4,100 2006.190.07:30:00.36/cable/+6.4685E-03 2006.190.07:30:01.45/va/01,08,usb,yes,34,36 2006.190.07:30:01.45/va/02,07,usb,yes,35,36 2006.190.07:30:01.45/va/03,06,usb,yes,36,37 2006.190.07:30:01.45/va/04,07,usb,yes,36,38 2006.190.07:30:01.45/va/05,07,usb,yes,39,41 2006.190.07:30:01.45/va/06,06,usb,yes,38,38 2006.190.07:30:01.45/va/07,06,usb,yes,39,38 2006.190.07:30:01.45/va/08,06,usb,yes,41,41 2006.190.07:30:01.68/valo/01,532.99,yes,locked 2006.190.07:30:01.68/valo/02,572.99,yes,locked 2006.190.07:30:01.68/valo/03,672.99,yes,locked 2006.190.07:30:01.68/valo/04,832.99,yes,locked 2006.190.07:30:01.68/valo/05,652.99,yes,locked 2006.190.07:30:01.68/valo/06,772.99,yes,locked 2006.190.07:30:01.68/valo/07,832.99,yes,locked 2006.190.07:30:01.68/valo/08,852.99,yes,locked 2006.190.07:30:02.77/vb/01,04,usb,yes,30,28 2006.190.07:30:02.77/vb/02,04,usb,yes,31,33 2006.190.07:30:02.77/vb/03,04,usb,yes,28,31 2006.190.07:30:02.77/vb/04,04,usb,yes,28,29 2006.190.07:30:02.77/vb/05,04,usb,yes,27,31 2006.190.07:30:02.77/vb/06,04,usb,yes,28,31 2006.190.07:30:02.77/vb/07,04,usb,yes,30,30 2006.190.07:30:02.77/vb/08,04,usb,yes,28,31 2006.190.07:30:03.00/vblo/01,632.99,yes,locked 2006.190.07:30:03.00/vblo/02,640.99,yes,locked 2006.190.07:30:03.00/vblo/03,656.99,yes,locked 2006.190.07:30:03.00/vblo/04,712.99,yes,locked 2006.190.07:30:03.00/vblo/05,744.99,yes,locked 2006.190.07:30:03.00/vblo/06,752.99,yes,locked 2006.190.07:30:03.00/vblo/07,734.99,yes,locked 2006.190.07:30:03.00/vblo/08,744.99,yes,locked 2006.190.07:30:03.15/vabw/8 2006.190.07:30:03.30/vbbw/8 2006.190.07:30:03.39/xfe/off,on,14.7 2006.190.07:30:03.77/ifatt/23,28,28,28 2006.190.07:30:03.77&clockoff/"gps-fmout=1p 2006.190.07:30:03.77&clockoff/fmout-gps=1p 2006.190.07:30:04.07/fmout-gps/S +2.78E-07 2006.190.07:30:04.16:!2006.190.07:31:00 2006.190.07:31:00.01:data_valid=off 2006.190.07:31:00.02:postob 2006.190.07:31:00.02&postob/cable 2006.190.07:31:00.02&postob/wx 2006.190.07:31:00.03&postob/clockoff 2006.190.07:31:00.13/cable/+6.4702E-03 2006.190.07:31:00.14/wx/24.60,1012.3,100 2006.190.07:31:00.22/fmout-gps/S +2.79E-07 2006.190.07:31:00.23:scan_name=190-0733,k06190,60 2006.190.07:31:00.23:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.190.07:31:02.13#flagr#flagr/antenna,new-source 2006.190.07:31:02.14:checkk5 2006.190.07:31:02.14&checkk5/chk_autoobs=1 2006.190.07:31:02.14&checkk5/chk_autoobs=2 2006.190.07:31:02.15&checkk5/chk_autoobs=3 2006.190.07:31:02.15&checkk5/chk_autoobs=4 2006.190.07:31:02.16&checkk5/chk_obsdata=1 2006.190.07:31:02.16&checkk5/chk_obsdata=2 2006.190.07:31:02.16&checkk5/chk_obsdata=3 2006.190.07:31:02.17&checkk5/chk_obsdata=4 2006.190.07:31:02.17&checkk5/k5log=1 2006.190.07:31:02.18&checkk5/k5log=2 2006.190.07:31:02.18&checkk5/k5log=3 2006.190.07:31:02.18&checkk5/k5log=4 2006.190.07:31:02.18&checkk5/obsinfo 2006.190.07:31:02.62/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:31:02.99/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:31:03.38/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:31:03.76/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:31:04.14/chk_obsdata//k5ts1/T1900730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:31:04.52/chk_obsdata//k5ts2/T1900730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:31:04.90/chk_obsdata//k5ts3/T1900730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:31:05.28/chk_obsdata//k5ts4/T1900730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:31:05.99/k5log//k5ts1_log_newline 2006.190.07:31:06.69/k5log//k5ts2_log_newline 2006.190.07:31:07.39/k5log//k5ts3_log_newline 2006.190.07:31:08.09/k5log//k5ts4_log_newline 2006.190.07:31:08.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:31:08.11:4f8m12a=1 2006.190.07:31:08.11$4f8m12a/echo=on 2006.190.07:31:08.11$4f8m12a/pcalon 2006.190.07:31:08.11$pcalon/"no phase cal control is implemented here 2006.190.07:31:08.11$4f8m12a/"tpicd=stop 2006.190.07:31:08.11$4f8m12a/vc4f8 2006.190.07:31:08.11$vc4f8/valo=1,532.99 2006.190.07:31:08.12#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:31:08.12#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:31:08.12#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:08.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:08.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:08.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:08.12#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:31:08.12#ibcon#first serial, iclass 28, count 0 2006.190.07:31:08.12#ibcon#enter sib2, iclass 28, count 0 2006.190.07:31:08.12#ibcon#flushed, iclass 28, count 0 2006.190.07:31:08.12#ibcon#about to write, iclass 28, count 0 2006.190.07:31:08.12#ibcon#wrote, iclass 28, count 0 2006.190.07:31:08.12#ibcon#about to read 3, iclass 28, count 0 2006.190.07:31:08.17#ibcon#read 3, iclass 28, count 0 2006.190.07:31:08.17#ibcon#about to read 4, iclass 28, count 0 2006.190.07:31:08.17#ibcon#read 4, iclass 28, count 0 2006.190.07:31:08.17#ibcon#about to read 5, iclass 28, count 0 2006.190.07:31:08.17#ibcon#read 5, iclass 28, count 0 2006.190.07:31:08.17#ibcon#about to read 6, iclass 28, count 0 2006.190.07:31:08.17#ibcon#read 6, iclass 28, count 0 2006.190.07:31:08.17#ibcon#end of sib2, iclass 28, count 0 2006.190.07:31:08.17#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:31:08.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:31:08.17#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:31:08.17#ibcon#*before write, iclass 28, count 0 2006.190.07:31:08.17#ibcon#enter sib2, iclass 28, count 0 2006.190.07:31:08.17#ibcon#flushed, iclass 28, count 0 2006.190.07:31:08.17#ibcon#about to write, iclass 28, count 0 2006.190.07:31:08.17#ibcon#wrote, iclass 28, count 0 2006.190.07:31:08.17#ibcon#about to read 3, iclass 28, count 0 2006.190.07:31:08.21#ibcon#read 3, iclass 28, count 0 2006.190.07:31:08.21#ibcon#about to read 4, iclass 28, count 0 2006.190.07:31:08.21#ibcon#read 4, iclass 28, count 0 2006.190.07:31:08.21#ibcon#about to read 5, iclass 28, count 0 2006.190.07:31:08.21#ibcon#read 5, iclass 28, count 0 2006.190.07:31:08.21#ibcon#about to read 6, iclass 28, count 0 2006.190.07:31:08.21#ibcon#read 6, iclass 28, count 0 2006.190.07:31:08.21#ibcon#end of sib2, iclass 28, count 0 2006.190.07:31:08.21#ibcon#*after write, iclass 28, count 0 2006.190.07:31:08.21#ibcon#*before return 0, iclass 28, count 0 2006.190.07:31:08.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:08.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:08.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:31:08.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:31:08.21$vc4f8/va=1,8 2006.190.07:31:08.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:31:08.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:31:08.21#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:08.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:08.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:08.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:08.21#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:31:08.21#ibcon#first serial, iclass 30, count 2 2006.190.07:31:08.21#ibcon#enter sib2, iclass 30, count 2 2006.190.07:31:08.21#ibcon#flushed, iclass 30, count 2 2006.190.07:31:08.21#ibcon#about to write, iclass 30, count 2 2006.190.07:31:08.21#ibcon#wrote, iclass 30, count 2 2006.190.07:31:08.21#ibcon#about to read 3, iclass 30, count 2 2006.190.07:31:08.23#ibcon#read 3, iclass 30, count 2 2006.190.07:31:08.23#ibcon#about to read 4, iclass 30, count 2 2006.190.07:31:08.23#ibcon#read 4, iclass 30, count 2 2006.190.07:31:08.23#ibcon#about to read 5, iclass 30, count 2 2006.190.07:31:08.23#ibcon#read 5, iclass 30, count 2 2006.190.07:31:08.23#ibcon#about to read 6, iclass 30, count 2 2006.190.07:31:08.23#ibcon#read 6, iclass 30, count 2 2006.190.07:31:08.23#ibcon#end of sib2, iclass 30, count 2 2006.190.07:31:08.23#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:31:08.23#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:31:08.23#ibcon#[25=AT01-08\r\n] 2006.190.07:31:08.23#ibcon#*before write, iclass 30, count 2 2006.190.07:31:08.23#ibcon#enter sib2, iclass 30, count 2 2006.190.07:31:08.23#ibcon#flushed, iclass 30, count 2 2006.190.07:31:08.23#ibcon#about to write, iclass 30, count 2 2006.190.07:31:08.23#ibcon#wrote, iclass 30, count 2 2006.190.07:31:08.23#ibcon#about to read 3, iclass 30, count 2 2006.190.07:31:08.26#ibcon#read 3, iclass 30, count 2 2006.190.07:31:08.26#ibcon#about to read 4, iclass 30, count 2 2006.190.07:31:08.26#ibcon#read 4, iclass 30, count 2 2006.190.07:31:08.26#ibcon#about to read 5, iclass 30, count 2 2006.190.07:31:08.26#ibcon#read 5, iclass 30, count 2 2006.190.07:31:08.26#ibcon#about to read 6, iclass 30, count 2 2006.190.07:31:08.26#ibcon#read 6, iclass 30, count 2 2006.190.07:31:08.26#ibcon#end of sib2, iclass 30, count 2 2006.190.07:31:08.26#ibcon#*after write, iclass 30, count 2 2006.190.07:31:08.26#ibcon#*before return 0, iclass 30, count 2 2006.190.07:31:08.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:08.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:08.26#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:31:08.26#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:08.26#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:08.38#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:08.38#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:08.38#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:31:08.38#ibcon#first serial, iclass 30, count 0 2006.190.07:31:08.38#ibcon#enter sib2, iclass 30, count 0 2006.190.07:31:08.38#ibcon#flushed, iclass 30, count 0 2006.190.07:31:08.38#ibcon#about to write, iclass 30, count 0 2006.190.07:31:08.38#ibcon#wrote, iclass 30, count 0 2006.190.07:31:08.38#ibcon#about to read 3, iclass 30, count 0 2006.190.07:31:08.40#ibcon#read 3, iclass 30, count 0 2006.190.07:31:08.40#ibcon#about to read 4, iclass 30, count 0 2006.190.07:31:08.40#ibcon#read 4, iclass 30, count 0 2006.190.07:31:08.40#ibcon#about to read 5, iclass 30, count 0 2006.190.07:31:08.40#ibcon#read 5, iclass 30, count 0 2006.190.07:31:08.40#ibcon#about to read 6, iclass 30, count 0 2006.190.07:31:08.40#ibcon#read 6, iclass 30, count 0 2006.190.07:31:08.40#ibcon#end of sib2, iclass 30, count 0 2006.190.07:31:08.40#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:31:08.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:31:08.40#ibcon#[25=USB\r\n] 2006.190.07:31:08.40#ibcon#*before write, iclass 30, count 0 2006.190.07:31:08.40#ibcon#enter sib2, iclass 30, count 0 2006.190.07:31:08.40#ibcon#flushed, iclass 30, count 0 2006.190.07:31:08.40#ibcon#about to write, iclass 30, count 0 2006.190.07:31:08.40#ibcon#wrote, iclass 30, count 0 2006.190.07:31:08.40#ibcon#about to read 3, iclass 30, count 0 2006.190.07:31:08.43#ibcon#read 3, iclass 30, count 0 2006.190.07:31:08.43#ibcon#about to read 4, iclass 30, count 0 2006.190.07:31:08.43#ibcon#read 4, iclass 30, count 0 2006.190.07:31:08.43#ibcon#about to read 5, iclass 30, count 0 2006.190.07:31:08.43#ibcon#read 5, iclass 30, count 0 2006.190.07:31:08.43#ibcon#about to read 6, iclass 30, count 0 2006.190.07:31:08.43#ibcon#read 6, iclass 30, count 0 2006.190.07:31:08.43#ibcon#end of sib2, iclass 30, count 0 2006.190.07:31:08.43#ibcon#*after write, iclass 30, count 0 2006.190.07:31:08.43#ibcon#*before return 0, iclass 30, count 0 2006.190.07:31:08.43#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:08.43#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:08.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:31:08.43#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:31:08.43$vc4f8/valo=2,572.99 2006.190.07:31:08.43#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:31:08.43#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:31:08.43#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:08.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:08.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:08.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:08.43#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:31:08.43#ibcon#first serial, iclass 32, count 0 2006.190.07:31:08.43#ibcon#enter sib2, iclass 32, count 0 2006.190.07:31:08.43#ibcon#flushed, iclass 32, count 0 2006.190.07:31:08.43#ibcon#about to write, iclass 32, count 0 2006.190.07:31:08.43#ibcon#wrote, iclass 32, count 0 2006.190.07:31:08.43#ibcon#about to read 3, iclass 32, count 0 2006.190.07:31:08.45#ibcon#read 3, iclass 32, count 0 2006.190.07:31:08.45#ibcon#about to read 4, iclass 32, count 0 2006.190.07:31:08.45#ibcon#read 4, iclass 32, count 0 2006.190.07:31:08.45#ibcon#about to read 5, iclass 32, count 0 2006.190.07:31:08.45#ibcon#read 5, iclass 32, count 0 2006.190.07:31:08.45#ibcon#about to read 6, iclass 32, count 0 2006.190.07:31:08.45#ibcon#read 6, iclass 32, count 0 2006.190.07:31:08.45#ibcon#end of sib2, iclass 32, count 0 2006.190.07:31:08.45#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:31:08.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:31:08.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:31:08.45#ibcon#*before write, iclass 32, count 0 2006.190.07:31:08.45#ibcon#enter sib2, iclass 32, count 0 2006.190.07:31:08.45#ibcon#flushed, iclass 32, count 0 2006.190.07:31:08.45#ibcon#about to write, iclass 32, count 0 2006.190.07:31:08.45#ibcon#wrote, iclass 32, count 0 2006.190.07:31:08.45#ibcon#about to read 3, iclass 32, count 0 2006.190.07:31:08.49#ibcon#read 3, iclass 32, count 0 2006.190.07:31:08.49#ibcon#about to read 4, iclass 32, count 0 2006.190.07:31:08.49#ibcon#read 4, iclass 32, count 0 2006.190.07:31:08.49#ibcon#about to read 5, iclass 32, count 0 2006.190.07:31:08.49#ibcon#read 5, iclass 32, count 0 2006.190.07:31:08.49#ibcon#about to read 6, iclass 32, count 0 2006.190.07:31:08.49#ibcon#read 6, iclass 32, count 0 2006.190.07:31:08.49#ibcon#end of sib2, iclass 32, count 0 2006.190.07:31:08.50#ibcon#*after write, iclass 32, count 0 2006.190.07:31:08.50#ibcon#*before return 0, iclass 32, count 0 2006.190.07:31:08.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:08.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:08.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:31:08.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:31:08.50$vc4f8/va=2,7 2006.190.07:31:08.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:31:08.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:31:08.50#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:08.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:08.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:08.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:08.54#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:31:08.54#ibcon#first serial, iclass 34, count 2 2006.190.07:31:08.54#ibcon#enter sib2, iclass 34, count 2 2006.190.07:31:08.54#ibcon#flushed, iclass 34, count 2 2006.190.07:31:08.54#ibcon#about to write, iclass 34, count 2 2006.190.07:31:08.54#ibcon#wrote, iclass 34, count 2 2006.190.07:31:08.54#ibcon#about to read 3, iclass 34, count 2 2006.190.07:31:08.56#ibcon#read 3, iclass 34, count 2 2006.190.07:31:08.56#ibcon#about to read 4, iclass 34, count 2 2006.190.07:31:08.56#ibcon#read 4, iclass 34, count 2 2006.190.07:31:08.56#ibcon#about to read 5, iclass 34, count 2 2006.190.07:31:08.56#ibcon#read 5, iclass 34, count 2 2006.190.07:31:08.56#ibcon#about to read 6, iclass 34, count 2 2006.190.07:31:08.56#ibcon#read 6, iclass 34, count 2 2006.190.07:31:08.56#ibcon#end of sib2, iclass 34, count 2 2006.190.07:31:08.56#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:31:08.56#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:31:08.56#ibcon#[25=AT02-07\r\n] 2006.190.07:31:08.56#ibcon#*before write, iclass 34, count 2 2006.190.07:31:08.56#ibcon#enter sib2, iclass 34, count 2 2006.190.07:31:08.56#ibcon#flushed, iclass 34, count 2 2006.190.07:31:08.56#ibcon#about to write, iclass 34, count 2 2006.190.07:31:08.56#ibcon#wrote, iclass 34, count 2 2006.190.07:31:08.56#ibcon#about to read 3, iclass 34, count 2 2006.190.07:31:08.59#ibcon#read 3, iclass 34, count 2 2006.190.07:31:08.59#ibcon#about to read 4, iclass 34, count 2 2006.190.07:31:08.59#ibcon#read 4, iclass 34, count 2 2006.190.07:31:08.59#ibcon#about to read 5, iclass 34, count 2 2006.190.07:31:08.59#ibcon#read 5, iclass 34, count 2 2006.190.07:31:08.59#ibcon#about to read 6, iclass 34, count 2 2006.190.07:31:08.59#ibcon#read 6, iclass 34, count 2 2006.190.07:31:08.59#ibcon#end of sib2, iclass 34, count 2 2006.190.07:31:08.59#ibcon#*after write, iclass 34, count 2 2006.190.07:31:08.59#ibcon#*before return 0, iclass 34, count 2 2006.190.07:31:08.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:08.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:08.59#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:31:08.59#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:08.59#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:08.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:08.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:08.71#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:31:08.71#ibcon#first serial, iclass 34, count 0 2006.190.07:31:08.71#ibcon#enter sib2, iclass 34, count 0 2006.190.07:31:08.71#ibcon#flushed, iclass 34, count 0 2006.190.07:31:08.71#ibcon#about to write, iclass 34, count 0 2006.190.07:31:08.71#ibcon#wrote, iclass 34, count 0 2006.190.07:31:08.71#ibcon#about to read 3, iclass 34, count 0 2006.190.07:31:08.73#ibcon#read 3, iclass 34, count 0 2006.190.07:31:08.73#ibcon#about to read 4, iclass 34, count 0 2006.190.07:31:08.73#ibcon#read 4, iclass 34, count 0 2006.190.07:31:08.73#ibcon#about to read 5, iclass 34, count 0 2006.190.07:31:08.73#ibcon#read 5, iclass 34, count 0 2006.190.07:31:08.73#ibcon#about to read 6, iclass 34, count 0 2006.190.07:31:08.73#ibcon#read 6, iclass 34, count 0 2006.190.07:31:08.73#ibcon#end of sib2, iclass 34, count 0 2006.190.07:31:08.73#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:31:08.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:31:08.73#ibcon#[25=USB\r\n] 2006.190.07:31:08.73#ibcon#*before write, iclass 34, count 0 2006.190.07:31:08.73#ibcon#enter sib2, iclass 34, count 0 2006.190.07:31:08.73#ibcon#flushed, iclass 34, count 0 2006.190.07:31:08.73#ibcon#about to write, iclass 34, count 0 2006.190.07:31:08.73#ibcon#wrote, iclass 34, count 0 2006.190.07:31:08.73#ibcon#about to read 3, iclass 34, count 0 2006.190.07:31:08.76#ibcon#read 3, iclass 34, count 0 2006.190.07:31:08.76#ibcon#about to read 4, iclass 34, count 0 2006.190.07:31:08.76#ibcon#read 4, iclass 34, count 0 2006.190.07:31:08.76#ibcon#about to read 5, iclass 34, count 0 2006.190.07:31:08.76#ibcon#read 5, iclass 34, count 0 2006.190.07:31:08.76#ibcon#about to read 6, iclass 34, count 0 2006.190.07:31:08.76#ibcon#read 6, iclass 34, count 0 2006.190.07:31:08.76#ibcon#end of sib2, iclass 34, count 0 2006.190.07:31:08.76#ibcon#*after write, iclass 34, count 0 2006.190.07:31:08.76#ibcon#*before return 0, iclass 34, count 0 2006.190.07:31:08.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:08.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:08.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:31:08.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:31:08.76$vc4f8/valo=3,672.99 2006.190.07:31:08.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:31:08.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:31:08.76#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:08.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:08.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:08.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:08.76#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:31:08.76#ibcon#first serial, iclass 36, count 0 2006.190.07:31:08.76#ibcon#enter sib2, iclass 36, count 0 2006.190.07:31:08.76#ibcon#flushed, iclass 36, count 0 2006.190.07:31:08.76#ibcon#about to write, iclass 36, count 0 2006.190.07:31:08.76#ibcon#wrote, iclass 36, count 0 2006.190.07:31:08.76#ibcon#about to read 3, iclass 36, count 0 2006.190.07:31:08.78#ibcon#read 3, iclass 36, count 0 2006.190.07:31:08.78#ibcon#about to read 4, iclass 36, count 0 2006.190.07:31:08.78#ibcon#read 4, iclass 36, count 0 2006.190.07:31:08.78#ibcon#about to read 5, iclass 36, count 0 2006.190.07:31:08.78#ibcon#read 5, iclass 36, count 0 2006.190.07:31:08.78#ibcon#about to read 6, iclass 36, count 0 2006.190.07:31:08.78#ibcon#read 6, iclass 36, count 0 2006.190.07:31:08.78#ibcon#end of sib2, iclass 36, count 0 2006.190.07:31:08.78#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:31:08.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:31:08.78#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:31:08.78#ibcon#*before write, iclass 36, count 0 2006.190.07:31:08.78#ibcon#enter sib2, iclass 36, count 0 2006.190.07:31:08.78#ibcon#flushed, iclass 36, count 0 2006.190.07:31:08.78#ibcon#about to write, iclass 36, count 0 2006.190.07:31:08.78#ibcon#wrote, iclass 36, count 0 2006.190.07:31:08.78#ibcon#about to read 3, iclass 36, count 0 2006.190.07:31:08.82#ibcon#read 3, iclass 36, count 0 2006.190.07:31:08.82#ibcon#about to read 4, iclass 36, count 0 2006.190.07:31:08.82#ibcon#read 4, iclass 36, count 0 2006.190.07:31:08.82#ibcon#about to read 5, iclass 36, count 0 2006.190.07:31:08.82#ibcon#read 5, iclass 36, count 0 2006.190.07:31:08.82#ibcon#about to read 6, iclass 36, count 0 2006.190.07:31:08.82#ibcon#read 6, iclass 36, count 0 2006.190.07:31:08.82#ibcon#end of sib2, iclass 36, count 0 2006.190.07:31:08.82#ibcon#*after write, iclass 36, count 0 2006.190.07:31:08.82#ibcon#*before return 0, iclass 36, count 0 2006.190.07:31:08.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:08.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:08.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:31:08.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:31:08.83$vc4f8/va=3,6 2006.190.07:31:08.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.07:31:08.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.07:31:08.83#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:08.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:08.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:08.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:08.87#ibcon#enter wrdev, iclass 38, count 2 2006.190.07:31:08.87#ibcon#first serial, iclass 38, count 2 2006.190.07:31:08.87#ibcon#enter sib2, iclass 38, count 2 2006.190.07:31:08.87#ibcon#flushed, iclass 38, count 2 2006.190.07:31:08.87#ibcon#about to write, iclass 38, count 2 2006.190.07:31:08.87#ibcon#wrote, iclass 38, count 2 2006.190.07:31:08.87#ibcon#about to read 3, iclass 38, count 2 2006.190.07:31:08.89#ibcon#read 3, iclass 38, count 2 2006.190.07:31:08.89#ibcon#about to read 4, iclass 38, count 2 2006.190.07:31:08.89#ibcon#read 4, iclass 38, count 2 2006.190.07:31:08.89#ibcon#about to read 5, iclass 38, count 2 2006.190.07:31:08.89#ibcon#read 5, iclass 38, count 2 2006.190.07:31:08.89#ibcon#about to read 6, iclass 38, count 2 2006.190.07:31:08.89#ibcon#read 6, iclass 38, count 2 2006.190.07:31:08.89#ibcon#end of sib2, iclass 38, count 2 2006.190.07:31:08.89#ibcon#*mode == 0, iclass 38, count 2 2006.190.07:31:08.89#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.07:31:08.89#ibcon#[25=AT03-06\r\n] 2006.190.07:31:08.89#ibcon#*before write, iclass 38, count 2 2006.190.07:31:08.89#ibcon#enter sib2, iclass 38, count 2 2006.190.07:31:08.89#ibcon#flushed, iclass 38, count 2 2006.190.07:31:08.89#ibcon#about to write, iclass 38, count 2 2006.190.07:31:08.89#ibcon#wrote, iclass 38, count 2 2006.190.07:31:08.89#ibcon#about to read 3, iclass 38, count 2 2006.190.07:31:08.92#ibcon#read 3, iclass 38, count 2 2006.190.07:31:08.92#ibcon#about to read 4, iclass 38, count 2 2006.190.07:31:08.92#ibcon#read 4, iclass 38, count 2 2006.190.07:31:08.92#ibcon#about to read 5, iclass 38, count 2 2006.190.07:31:08.92#ibcon#read 5, iclass 38, count 2 2006.190.07:31:08.92#ibcon#about to read 6, iclass 38, count 2 2006.190.07:31:08.92#ibcon#read 6, iclass 38, count 2 2006.190.07:31:08.92#ibcon#end of sib2, iclass 38, count 2 2006.190.07:31:08.92#ibcon#*after write, iclass 38, count 2 2006.190.07:31:08.92#ibcon#*before return 0, iclass 38, count 2 2006.190.07:31:08.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:08.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:08.92#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.07:31:08.92#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:08.92#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:09.04#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:09.04#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:09.04#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:31:09.04#ibcon#first serial, iclass 38, count 0 2006.190.07:31:09.04#ibcon#enter sib2, iclass 38, count 0 2006.190.07:31:09.04#ibcon#flushed, iclass 38, count 0 2006.190.07:31:09.04#ibcon#about to write, iclass 38, count 0 2006.190.07:31:09.04#ibcon#wrote, iclass 38, count 0 2006.190.07:31:09.04#ibcon#about to read 3, iclass 38, count 0 2006.190.07:31:09.06#ibcon#read 3, iclass 38, count 0 2006.190.07:31:09.06#ibcon#about to read 4, iclass 38, count 0 2006.190.07:31:09.06#ibcon#read 4, iclass 38, count 0 2006.190.07:31:09.06#ibcon#about to read 5, iclass 38, count 0 2006.190.07:31:09.06#ibcon#read 5, iclass 38, count 0 2006.190.07:31:09.06#ibcon#about to read 6, iclass 38, count 0 2006.190.07:31:09.06#ibcon#read 6, iclass 38, count 0 2006.190.07:31:09.06#ibcon#end of sib2, iclass 38, count 0 2006.190.07:31:09.06#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:31:09.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:31:09.06#ibcon#[25=USB\r\n] 2006.190.07:31:09.06#ibcon#*before write, iclass 38, count 0 2006.190.07:31:09.06#ibcon#enter sib2, iclass 38, count 0 2006.190.07:31:09.06#ibcon#flushed, iclass 38, count 0 2006.190.07:31:09.06#ibcon#about to write, iclass 38, count 0 2006.190.07:31:09.06#ibcon#wrote, iclass 38, count 0 2006.190.07:31:09.06#ibcon#about to read 3, iclass 38, count 0 2006.190.07:31:09.09#ibcon#read 3, iclass 38, count 0 2006.190.07:31:09.09#ibcon#about to read 4, iclass 38, count 0 2006.190.07:31:09.09#ibcon#read 4, iclass 38, count 0 2006.190.07:31:09.09#ibcon#about to read 5, iclass 38, count 0 2006.190.07:31:09.09#ibcon#read 5, iclass 38, count 0 2006.190.07:31:09.09#ibcon#about to read 6, iclass 38, count 0 2006.190.07:31:09.09#ibcon#read 6, iclass 38, count 0 2006.190.07:31:09.09#ibcon#end of sib2, iclass 38, count 0 2006.190.07:31:09.09#ibcon#*after write, iclass 38, count 0 2006.190.07:31:09.09#ibcon#*before return 0, iclass 38, count 0 2006.190.07:31:09.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:09.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:09.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:31:09.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:31:09.09$vc4f8/valo=4,832.99 2006.190.07:31:09.09#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:31:09.09#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:31:09.09#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:09.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:09.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:09.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:09.09#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:31:09.09#ibcon#first serial, iclass 40, count 0 2006.190.07:31:09.09#ibcon#enter sib2, iclass 40, count 0 2006.190.07:31:09.09#ibcon#flushed, iclass 40, count 0 2006.190.07:31:09.09#ibcon#about to write, iclass 40, count 0 2006.190.07:31:09.09#ibcon#wrote, iclass 40, count 0 2006.190.07:31:09.09#ibcon#about to read 3, iclass 40, count 0 2006.190.07:31:09.11#ibcon#read 3, iclass 40, count 0 2006.190.07:31:09.11#ibcon#about to read 4, iclass 40, count 0 2006.190.07:31:09.11#ibcon#read 4, iclass 40, count 0 2006.190.07:31:09.11#ibcon#about to read 5, iclass 40, count 0 2006.190.07:31:09.11#ibcon#read 5, iclass 40, count 0 2006.190.07:31:09.11#ibcon#about to read 6, iclass 40, count 0 2006.190.07:31:09.11#ibcon#read 6, iclass 40, count 0 2006.190.07:31:09.11#ibcon#end of sib2, iclass 40, count 0 2006.190.07:31:09.11#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:31:09.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:31:09.11#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:31:09.11#ibcon#*before write, iclass 40, count 0 2006.190.07:31:09.11#ibcon#enter sib2, iclass 40, count 0 2006.190.07:31:09.11#ibcon#flushed, iclass 40, count 0 2006.190.07:31:09.11#ibcon#about to write, iclass 40, count 0 2006.190.07:31:09.11#ibcon#wrote, iclass 40, count 0 2006.190.07:31:09.11#ibcon#about to read 3, iclass 40, count 0 2006.190.07:31:09.15#ibcon#read 3, iclass 40, count 0 2006.190.07:31:09.15#ibcon#about to read 4, iclass 40, count 0 2006.190.07:31:09.15#ibcon#read 4, iclass 40, count 0 2006.190.07:31:09.15#ibcon#about to read 5, iclass 40, count 0 2006.190.07:31:09.15#ibcon#read 5, iclass 40, count 0 2006.190.07:31:09.15#ibcon#about to read 6, iclass 40, count 0 2006.190.07:31:09.15#ibcon#read 6, iclass 40, count 0 2006.190.07:31:09.15#ibcon#end of sib2, iclass 40, count 0 2006.190.07:31:09.15#ibcon#*after write, iclass 40, count 0 2006.190.07:31:09.15#ibcon#*before return 0, iclass 40, count 0 2006.190.07:31:09.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:09.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:09.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:31:09.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:31:09.15$vc4f8/va=4,7 2006.190.07:31:09.15#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:31:09.15#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:31:09.15#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:09.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:09.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:09.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:09.21#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:31:09.21#ibcon#first serial, iclass 4, count 2 2006.190.07:31:09.21#ibcon#enter sib2, iclass 4, count 2 2006.190.07:31:09.21#ibcon#flushed, iclass 4, count 2 2006.190.07:31:09.21#ibcon#about to write, iclass 4, count 2 2006.190.07:31:09.21#ibcon#wrote, iclass 4, count 2 2006.190.07:31:09.21#ibcon#about to read 3, iclass 4, count 2 2006.190.07:31:09.23#ibcon#read 3, iclass 4, count 2 2006.190.07:31:09.23#ibcon#about to read 4, iclass 4, count 2 2006.190.07:31:09.23#ibcon#read 4, iclass 4, count 2 2006.190.07:31:09.23#ibcon#about to read 5, iclass 4, count 2 2006.190.07:31:09.23#ibcon#read 5, iclass 4, count 2 2006.190.07:31:09.23#ibcon#about to read 6, iclass 4, count 2 2006.190.07:31:09.23#ibcon#read 6, iclass 4, count 2 2006.190.07:31:09.23#ibcon#end of sib2, iclass 4, count 2 2006.190.07:31:09.23#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:31:09.23#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:31:09.23#ibcon#[25=AT04-07\r\n] 2006.190.07:31:09.23#ibcon#*before write, iclass 4, count 2 2006.190.07:31:09.23#ibcon#enter sib2, iclass 4, count 2 2006.190.07:31:09.23#ibcon#flushed, iclass 4, count 2 2006.190.07:31:09.23#ibcon#about to write, iclass 4, count 2 2006.190.07:31:09.23#ibcon#wrote, iclass 4, count 2 2006.190.07:31:09.23#ibcon#about to read 3, iclass 4, count 2 2006.190.07:31:09.26#ibcon#read 3, iclass 4, count 2 2006.190.07:31:09.26#ibcon#about to read 4, iclass 4, count 2 2006.190.07:31:09.26#ibcon#read 4, iclass 4, count 2 2006.190.07:31:09.26#ibcon#about to read 5, iclass 4, count 2 2006.190.07:31:09.26#ibcon#read 5, iclass 4, count 2 2006.190.07:31:09.26#ibcon#about to read 6, iclass 4, count 2 2006.190.07:31:09.26#ibcon#read 6, iclass 4, count 2 2006.190.07:31:09.26#ibcon#end of sib2, iclass 4, count 2 2006.190.07:31:09.26#ibcon#*after write, iclass 4, count 2 2006.190.07:31:09.26#ibcon#*before return 0, iclass 4, count 2 2006.190.07:31:09.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:09.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:09.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:31:09.26#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:09.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:09.38#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:09.38#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:09.38#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:31:09.38#ibcon#first serial, iclass 4, count 0 2006.190.07:31:09.38#ibcon#enter sib2, iclass 4, count 0 2006.190.07:31:09.38#ibcon#flushed, iclass 4, count 0 2006.190.07:31:09.38#ibcon#about to write, iclass 4, count 0 2006.190.07:31:09.38#ibcon#wrote, iclass 4, count 0 2006.190.07:31:09.38#ibcon#about to read 3, iclass 4, count 0 2006.190.07:31:09.40#ibcon#read 3, iclass 4, count 0 2006.190.07:31:09.40#ibcon#about to read 4, iclass 4, count 0 2006.190.07:31:09.40#ibcon#read 4, iclass 4, count 0 2006.190.07:31:09.40#ibcon#about to read 5, iclass 4, count 0 2006.190.07:31:09.40#ibcon#read 5, iclass 4, count 0 2006.190.07:31:09.40#ibcon#about to read 6, iclass 4, count 0 2006.190.07:31:09.40#ibcon#read 6, iclass 4, count 0 2006.190.07:31:09.40#ibcon#end of sib2, iclass 4, count 0 2006.190.07:31:09.40#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:31:09.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:31:09.40#ibcon#[25=USB\r\n] 2006.190.07:31:09.40#ibcon#*before write, iclass 4, count 0 2006.190.07:31:09.40#ibcon#enter sib2, iclass 4, count 0 2006.190.07:31:09.40#ibcon#flushed, iclass 4, count 0 2006.190.07:31:09.40#ibcon#about to write, iclass 4, count 0 2006.190.07:31:09.40#ibcon#wrote, iclass 4, count 0 2006.190.07:31:09.40#ibcon#about to read 3, iclass 4, count 0 2006.190.07:31:09.43#ibcon#read 3, iclass 4, count 0 2006.190.07:31:09.43#ibcon#about to read 4, iclass 4, count 0 2006.190.07:31:09.43#ibcon#read 4, iclass 4, count 0 2006.190.07:31:09.43#ibcon#about to read 5, iclass 4, count 0 2006.190.07:31:09.43#ibcon#read 5, iclass 4, count 0 2006.190.07:31:09.43#ibcon#about to read 6, iclass 4, count 0 2006.190.07:31:09.43#ibcon#read 6, iclass 4, count 0 2006.190.07:31:09.43#ibcon#end of sib2, iclass 4, count 0 2006.190.07:31:09.43#ibcon#*after write, iclass 4, count 0 2006.190.07:31:09.43#ibcon#*before return 0, iclass 4, count 0 2006.190.07:31:09.43#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:09.43#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:09.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:31:09.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:31:09.43$vc4f8/valo=5,652.99 2006.190.07:31:09.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:31:09.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:31:09.43#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:09.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:09.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:09.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:09.43#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:31:09.43#ibcon#first serial, iclass 6, count 0 2006.190.07:31:09.43#ibcon#enter sib2, iclass 6, count 0 2006.190.07:31:09.43#ibcon#flushed, iclass 6, count 0 2006.190.07:31:09.43#ibcon#about to write, iclass 6, count 0 2006.190.07:31:09.43#ibcon#wrote, iclass 6, count 0 2006.190.07:31:09.43#ibcon#about to read 3, iclass 6, count 0 2006.190.07:31:09.45#ibcon#read 3, iclass 6, count 0 2006.190.07:31:09.45#ibcon#about to read 4, iclass 6, count 0 2006.190.07:31:09.45#ibcon#read 4, iclass 6, count 0 2006.190.07:31:09.45#ibcon#about to read 5, iclass 6, count 0 2006.190.07:31:09.45#ibcon#read 5, iclass 6, count 0 2006.190.07:31:09.45#ibcon#about to read 6, iclass 6, count 0 2006.190.07:31:09.45#ibcon#read 6, iclass 6, count 0 2006.190.07:31:09.45#ibcon#end of sib2, iclass 6, count 0 2006.190.07:31:09.45#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:31:09.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:31:09.45#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:31:09.45#ibcon#*before write, iclass 6, count 0 2006.190.07:31:09.45#ibcon#enter sib2, iclass 6, count 0 2006.190.07:31:09.45#ibcon#flushed, iclass 6, count 0 2006.190.07:31:09.45#ibcon#about to write, iclass 6, count 0 2006.190.07:31:09.45#ibcon#wrote, iclass 6, count 0 2006.190.07:31:09.45#ibcon#about to read 3, iclass 6, count 0 2006.190.07:31:09.49#ibcon#read 3, iclass 6, count 0 2006.190.07:31:09.49#ibcon#about to read 4, iclass 6, count 0 2006.190.07:31:09.49#ibcon#read 4, iclass 6, count 0 2006.190.07:31:09.49#ibcon#about to read 5, iclass 6, count 0 2006.190.07:31:09.49#ibcon#read 5, iclass 6, count 0 2006.190.07:31:09.49#ibcon#about to read 6, iclass 6, count 0 2006.190.07:31:09.49#ibcon#read 6, iclass 6, count 0 2006.190.07:31:09.49#ibcon#end of sib2, iclass 6, count 0 2006.190.07:31:09.49#ibcon#*after write, iclass 6, count 0 2006.190.07:31:09.49#ibcon#*before return 0, iclass 6, count 0 2006.190.07:31:09.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:09.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:09.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:31:09.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:31:09.49$vc4f8/va=5,7 2006.190.07:31:09.49#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:31:09.49#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:31:09.49#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:09.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:09.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:09.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:09.55#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:31:09.55#ibcon#first serial, iclass 10, count 2 2006.190.07:31:09.55#ibcon#enter sib2, iclass 10, count 2 2006.190.07:31:09.55#ibcon#flushed, iclass 10, count 2 2006.190.07:31:09.55#ibcon#about to write, iclass 10, count 2 2006.190.07:31:09.55#ibcon#wrote, iclass 10, count 2 2006.190.07:31:09.55#ibcon#about to read 3, iclass 10, count 2 2006.190.07:31:09.57#ibcon#read 3, iclass 10, count 2 2006.190.07:31:09.57#ibcon#about to read 4, iclass 10, count 2 2006.190.07:31:09.57#ibcon#read 4, iclass 10, count 2 2006.190.07:31:09.57#ibcon#about to read 5, iclass 10, count 2 2006.190.07:31:09.57#ibcon#read 5, iclass 10, count 2 2006.190.07:31:09.57#ibcon#about to read 6, iclass 10, count 2 2006.190.07:31:09.57#ibcon#read 6, iclass 10, count 2 2006.190.07:31:09.57#ibcon#end of sib2, iclass 10, count 2 2006.190.07:31:09.57#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:31:09.57#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:31:09.57#ibcon#[25=AT05-07\r\n] 2006.190.07:31:09.57#ibcon#*before write, iclass 10, count 2 2006.190.07:31:09.57#ibcon#enter sib2, iclass 10, count 2 2006.190.07:31:09.57#ibcon#flushed, iclass 10, count 2 2006.190.07:31:09.57#ibcon#about to write, iclass 10, count 2 2006.190.07:31:09.57#ibcon#wrote, iclass 10, count 2 2006.190.07:31:09.57#ibcon#about to read 3, iclass 10, count 2 2006.190.07:31:09.60#ibcon#read 3, iclass 10, count 2 2006.190.07:31:09.60#ibcon#about to read 4, iclass 10, count 2 2006.190.07:31:09.60#ibcon#read 4, iclass 10, count 2 2006.190.07:31:09.60#ibcon#about to read 5, iclass 10, count 2 2006.190.07:31:09.60#ibcon#read 5, iclass 10, count 2 2006.190.07:31:09.60#ibcon#about to read 6, iclass 10, count 2 2006.190.07:31:09.60#ibcon#read 6, iclass 10, count 2 2006.190.07:31:09.60#ibcon#end of sib2, iclass 10, count 2 2006.190.07:31:09.60#ibcon#*after write, iclass 10, count 2 2006.190.07:31:09.60#ibcon#*before return 0, iclass 10, count 2 2006.190.07:31:09.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:09.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:09.60#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:31:09.60#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:09.60#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:09.72#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:09.72#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:09.72#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:31:09.72#ibcon#first serial, iclass 10, count 0 2006.190.07:31:09.72#ibcon#enter sib2, iclass 10, count 0 2006.190.07:31:09.72#ibcon#flushed, iclass 10, count 0 2006.190.07:31:09.72#ibcon#about to write, iclass 10, count 0 2006.190.07:31:09.72#ibcon#wrote, iclass 10, count 0 2006.190.07:31:09.72#ibcon#about to read 3, iclass 10, count 0 2006.190.07:31:09.74#ibcon#read 3, iclass 10, count 0 2006.190.07:31:09.74#ibcon#about to read 4, iclass 10, count 0 2006.190.07:31:09.74#ibcon#read 4, iclass 10, count 0 2006.190.07:31:09.74#ibcon#about to read 5, iclass 10, count 0 2006.190.07:31:09.74#ibcon#read 5, iclass 10, count 0 2006.190.07:31:09.74#ibcon#about to read 6, iclass 10, count 0 2006.190.07:31:09.74#ibcon#read 6, iclass 10, count 0 2006.190.07:31:09.74#ibcon#end of sib2, iclass 10, count 0 2006.190.07:31:09.74#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:31:09.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:31:09.74#ibcon#[25=USB\r\n] 2006.190.07:31:09.74#ibcon#*before write, iclass 10, count 0 2006.190.07:31:09.74#ibcon#enter sib2, iclass 10, count 0 2006.190.07:31:09.74#ibcon#flushed, iclass 10, count 0 2006.190.07:31:09.74#ibcon#about to write, iclass 10, count 0 2006.190.07:31:09.74#ibcon#wrote, iclass 10, count 0 2006.190.07:31:09.74#ibcon#about to read 3, iclass 10, count 0 2006.190.07:31:09.77#ibcon#read 3, iclass 10, count 0 2006.190.07:31:09.77#ibcon#about to read 4, iclass 10, count 0 2006.190.07:31:09.77#ibcon#read 4, iclass 10, count 0 2006.190.07:31:09.77#ibcon#about to read 5, iclass 10, count 0 2006.190.07:31:09.77#ibcon#read 5, iclass 10, count 0 2006.190.07:31:09.77#ibcon#about to read 6, iclass 10, count 0 2006.190.07:31:09.77#ibcon#read 6, iclass 10, count 0 2006.190.07:31:09.77#ibcon#end of sib2, iclass 10, count 0 2006.190.07:31:09.77#ibcon#*after write, iclass 10, count 0 2006.190.07:31:09.77#ibcon#*before return 0, iclass 10, count 0 2006.190.07:31:09.77#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:09.77#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:09.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:31:09.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:31:09.77$vc4f8/valo=6,772.99 2006.190.07:31:09.77#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:31:09.77#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:31:09.77#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:09.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:09.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:09.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:09.77#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:31:09.77#ibcon#first serial, iclass 12, count 0 2006.190.07:31:09.77#ibcon#enter sib2, iclass 12, count 0 2006.190.07:31:09.77#ibcon#flushed, iclass 12, count 0 2006.190.07:31:09.77#ibcon#about to write, iclass 12, count 0 2006.190.07:31:09.77#ibcon#wrote, iclass 12, count 0 2006.190.07:31:09.77#ibcon#about to read 3, iclass 12, count 0 2006.190.07:31:09.79#ibcon#read 3, iclass 12, count 0 2006.190.07:31:09.79#ibcon#about to read 4, iclass 12, count 0 2006.190.07:31:09.79#ibcon#read 4, iclass 12, count 0 2006.190.07:31:09.79#ibcon#about to read 5, iclass 12, count 0 2006.190.07:31:09.79#ibcon#read 5, iclass 12, count 0 2006.190.07:31:09.79#ibcon#about to read 6, iclass 12, count 0 2006.190.07:31:09.79#ibcon#read 6, iclass 12, count 0 2006.190.07:31:09.79#ibcon#end of sib2, iclass 12, count 0 2006.190.07:31:09.79#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:31:09.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:31:09.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:31:09.79#ibcon#*before write, iclass 12, count 0 2006.190.07:31:09.79#ibcon#enter sib2, iclass 12, count 0 2006.190.07:31:09.79#ibcon#flushed, iclass 12, count 0 2006.190.07:31:09.79#ibcon#about to write, iclass 12, count 0 2006.190.07:31:09.79#ibcon#wrote, iclass 12, count 0 2006.190.07:31:09.79#ibcon#about to read 3, iclass 12, count 0 2006.190.07:31:09.83#ibcon#read 3, iclass 12, count 0 2006.190.07:31:09.83#ibcon#about to read 4, iclass 12, count 0 2006.190.07:31:09.83#ibcon#read 4, iclass 12, count 0 2006.190.07:31:09.83#ibcon#about to read 5, iclass 12, count 0 2006.190.07:31:09.83#ibcon#read 5, iclass 12, count 0 2006.190.07:31:09.83#ibcon#about to read 6, iclass 12, count 0 2006.190.07:31:09.83#ibcon#read 6, iclass 12, count 0 2006.190.07:31:09.83#ibcon#end of sib2, iclass 12, count 0 2006.190.07:31:09.83#ibcon#*after write, iclass 12, count 0 2006.190.07:31:09.83#ibcon#*before return 0, iclass 12, count 0 2006.190.07:31:09.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:09.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:09.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:31:09.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:31:09.83$vc4f8/va=6,6 2006.190.07:31:09.83#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:31:09.83#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:31:09.83#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:09.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:31:09.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:31:09.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:31:09.89#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:31:09.89#ibcon#first serial, iclass 14, count 2 2006.190.07:31:09.89#ibcon#enter sib2, iclass 14, count 2 2006.190.07:31:09.89#ibcon#flushed, iclass 14, count 2 2006.190.07:31:09.89#ibcon#about to write, iclass 14, count 2 2006.190.07:31:09.89#ibcon#wrote, iclass 14, count 2 2006.190.07:31:09.89#ibcon#about to read 3, iclass 14, count 2 2006.190.07:31:09.91#ibcon#read 3, iclass 14, count 2 2006.190.07:31:09.91#ibcon#about to read 4, iclass 14, count 2 2006.190.07:31:09.91#ibcon#read 4, iclass 14, count 2 2006.190.07:31:09.91#ibcon#about to read 5, iclass 14, count 2 2006.190.07:31:09.91#ibcon#read 5, iclass 14, count 2 2006.190.07:31:09.91#ibcon#about to read 6, iclass 14, count 2 2006.190.07:31:09.91#ibcon#read 6, iclass 14, count 2 2006.190.07:31:09.91#ibcon#end of sib2, iclass 14, count 2 2006.190.07:31:09.91#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:31:09.91#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:31:09.91#ibcon#[25=AT06-06\r\n] 2006.190.07:31:09.91#ibcon#*before write, iclass 14, count 2 2006.190.07:31:09.91#ibcon#enter sib2, iclass 14, count 2 2006.190.07:31:09.91#ibcon#flushed, iclass 14, count 2 2006.190.07:31:09.91#ibcon#about to write, iclass 14, count 2 2006.190.07:31:09.91#ibcon#wrote, iclass 14, count 2 2006.190.07:31:09.91#ibcon#about to read 3, iclass 14, count 2 2006.190.07:31:09.94#ibcon#read 3, iclass 14, count 2 2006.190.07:31:09.94#ibcon#about to read 4, iclass 14, count 2 2006.190.07:31:09.94#ibcon#read 4, iclass 14, count 2 2006.190.07:31:09.94#ibcon#about to read 5, iclass 14, count 2 2006.190.07:31:09.94#ibcon#read 5, iclass 14, count 2 2006.190.07:31:09.94#ibcon#about to read 6, iclass 14, count 2 2006.190.07:31:09.94#ibcon#read 6, iclass 14, count 2 2006.190.07:31:09.94#ibcon#end of sib2, iclass 14, count 2 2006.190.07:31:09.94#ibcon#*after write, iclass 14, count 2 2006.190.07:31:09.94#ibcon#*before return 0, iclass 14, count 2 2006.190.07:31:09.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:31:09.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:31:09.94#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:31:09.94#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:09.94#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:31:10.06#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:31:10.06#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:31:10.06#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:31:10.06#ibcon#first serial, iclass 14, count 0 2006.190.07:31:10.06#ibcon#enter sib2, iclass 14, count 0 2006.190.07:31:10.06#ibcon#flushed, iclass 14, count 0 2006.190.07:31:10.06#ibcon#about to write, iclass 14, count 0 2006.190.07:31:10.06#ibcon#wrote, iclass 14, count 0 2006.190.07:31:10.06#ibcon#about to read 3, iclass 14, count 0 2006.190.07:31:10.08#ibcon#read 3, iclass 14, count 0 2006.190.07:31:10.08#ibcon#about to read 4, iclass 14, count 0 2006.190.07:31:10.08#ibcon#read 4, iclass 14, count 0 2006.190.07:31:10.08#ibcon#about to read 5, iclass 14, count 0 2006.190.07:31:10.08#ibcon#read 5, iclass 14, count 0 2006.190.07:31:10.08#ibcon#about to read 6, iclass 14, count 0 2006.190.07:31:10.08#ibcon#read 6, iclass 14, count 0 2006.190.07:31:10.08#ibcon#end of sib2, iclass 14, count 0 2006.190.07:31:10.08#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:31:10.08#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:31:10.08#ibcon#[25=USB\r\n] 2006.190.07:31:10.08#ibcon#*before write, iclass 14, count 0 2006.190.07:31:10.08#ibcon#enter sib2, iclass 14, count 0 2006.190.07:31:10.08#ibcon#flushed, iclass 14, count 0 2006.190.07:31:10.08#ibcon#about to write, iclass 14, count 0 2006.190.07:31:10.08#ibcon#wrote, iclass 14, count 0 2006.190.07:31:10.08#ibcon#about to read 3, iclass 14, count 0 2006.190.07:31:10.11#ibcon#read 3, iclass 14, count 0 2006.190.07:31:10.11#ibcon#about to read 4, iclass 14, count 0 2006.190.07:31:10.11#ibcon#read 4, iclass 14, count 0 2006.190.07:31:10.11#ibcon#about to read 5, iclass 14, count 0 2006.190.07:31:10.11#ibcon#read 5, iclass 14, count 0 2006.190.07:31:10.11#ibcon#about to read 6, iclass 14, count 0 2006.190.07:31:10.11#ibcon#read 6, iclass 14, count 0 2006.190.07:31:10.11#ibcon#end of sib2, iclass 14, count 0 2006.190.07:31:10.11#ibcon#*after write, iclass 14, count 0 2006.190.07:31:10.11#ibcon#*before return 0, iclass 14, count 0 2006.190.07:31:10.11#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:31:10.11#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:31:10.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:31:10.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:31:10.11$vc4f8/valo=7,832.99 2006.190.07:31:10.11#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:31:10.11#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:31:10.11#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:10.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:31:10.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:31:10.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:31:10.11#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:31:10.11#ibcon#first serial, iclass 16, count 0 2006.190.07:31:10.11#ibcon#enter sib2, iclass 16, count 0 2006.190.07:31:10.11#ibcon#flushed, iclass 16, count 0 2006.190.07:31:10.11#ibcon#about to write, iclass 16, count 0 2006.190.07:31:10.11#ibcon#wrote, iclass 16, count 0 2006.190.07:31:10.11#ibcon#about to read 3, iclass 16, count 0 2006.190.07:31:10.13#ibcon#read 3, iclass 16, count 0 2006.190.07:31:10.13#ibcon#about to read 4, iclass 16, count 0 2006.190.07:31:10.13#ibcon#read 4, iclass 16, count 0 2006.190.07:31:10.13#ibcon#about to read 5, iclass 16, count 0 2006.190.07:31:10.13#ibcon#read 5, iclass 16, count 0 2006.190.07:31:10.13#ibcon#about to read 6, iclass 16, count 0 2006.190.07:31:10.13#ibcon#read 6, iclass 16, count 0 2006.190.07:31:10.13#ibcon#end of sib2, iclass 16, count 0 2006.190.07:31:10.13#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:31:10.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:31:10.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:31:10.13#ibcon#*before write, iclass 16, count 0 2006.190.07:31:10.13#ibcon#enter sib2, iclass 16, count 0 2006.190.07:31:10.13#ibcon#flushed, iclass 16, count 0 2006.190.07:31:10.13#ibcon#about to write, iclass 16, count 0 2006.190.07:31:10.13#ibcon#wrote, iclass 16, count 0 2006.190.07:31:10.13#ibcon#about to read 3, iclass 16, count 0 2006.190.07:31:10.17#ibcon#read 3, iclass 16, count 0 2006.190.07:31:10.17#ibcon#about to read 4, iclass 16, count 0 2006.190.07:31:10.17#ibcon#read 4, iclass 16, count 0 2006.190.07:31:10.17#ibcon#about to read 5, iclass 16, count 0 2006.190.07:31:10.17#ibcon#read 5, iclass 16, count 0 2006.190.07:31:10.17#ibcon#about to read 6, iclass 16, count 0 2006.190.07:31:10.17#ibcon#read 6, iclass 16, count 0 2006.190.07:31:10.17#ibcon#end of sib2, iclass 16, count 0 2006.190.07:31:10.17#ibcon#*after write, iclass 16, count 0 2006.190.07:31:10.17#ibcon#*before return 0, iclass 16, count 0 2006.190.07:31:10.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:31:10.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:31:10.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:31:10.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:31:10.17$vc4f8/va=7,6 2006.190.07:31:10.17#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.07:31:10.17#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.07:31:10.17#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:10.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:31:10.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:31:10.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:31:10.23#ibcon#enter wrdev, iclass 18, count 2 2006.190.07:31:10.23#ibcon#first serial, iclass 18, count 2 2006.190.07:31:10.23#ibcon#enter sib2, iclass 18, count 2 2006.190.07:31:10.23#ibcon#flushed, iclass 18, count 2 2006.190.07:31:10.23#ibcon#about to write, iclass 18, count 2 2006.190.07:31:10.23#ibcon#wrote, iclass 18, count 2 2006.190.07:31:10.23#ibcon#about to read 3, iclass 18, count 2 2006.190.07:31:10.25#ibcon#read 3, iclass 18, count 2 2006.190.07:31:10.25#ibcon#about to read 4, iclass 18, count 2 2006.190.07:31:10.25#ibcon#read 4, iclass 18, count 2 2006.190.07:31:10.25#ibcon#about to read 5, iclass 18, count 2 2006.190.07:31:10.25#ibcon#read 5, iclass 18, count 2 2006.190.07:31:10.25#ibcon#about to read 6, iclass 18, count 2 2006.190.07:31:10.25#ibcon#read 6, iclass 18, count 2 2006.190.07:31:10.25#ibcon#end of sib2, iclass 18, count 2 2006.190.07:31:10.25#ibcon#*mode == 0, iclass 18, count 2 2006.190.07:31:10.25#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.07:31:10.25#ibcon#[25=AT07-06\r\n] 2006.190.07:31:10.25#ibcon#*before write, iclass 18, count 2 2006.190.07:31:10.25#ibcon#enter sib2, iclass 18, count 2 2006.190.07:31:10.25#ibcon#flushed, iclass 18, count 2 2006.190.07:31:10.25#ibcon#about to write, iclass 18, count 2 2006.190.07:31:10.25#ibcon#wrote, iclass 18, count 2 2006.190.07:31:10.25#ibcon#about to read 3, iclass 18, count 2 2006.190.07:31:10.28#ibcon#read 3, iclass 18, count 2 2006.190.07:31:10.28#ibcon#about to read 4, iclass 18, count 2 2006.190.07:31:10.28#ibcon#read 4, iclass 18, count 2 2006.190.07:31:10.28#ibcon#about to read 5, iclass 18, count 2 2006.190.07:31:10.28#ibcon#read 5, iclass 18, count 2 2006.190.07:31:10.28#ibcon#about to read 6, iclass 18, count 2 2006.190.07:31:10.28#ibcon#read 6, iclass 18, count 2 2006.190.07:31:10.28#ibcon#end of sib2, iclass 18, count 2 2006.190.07:31:10.28#ibcon#*after write, iclass 18, count 2 2006.190.07:31:10.28#ibcon#*before return 0, iclass 18, count 2 2006.190.07:31:10.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:31:10.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:31:10.28#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.07:31:10.28#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:10.28#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:31:10.40#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:31:10.40#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:31:10.40#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:31:10.40#ibcon#first serial, iclass 18, count 0 2006.190.07:31:10.40#ibcon#enter sib2, iclass 18, count 0 2006.190.07:31:10.40#ibcon#flushed, iclass 18, count 0 2006.190.07:31:10.40#ibcon#about to write, iclass 18, count 0 2006.190.07:31:10.40#ibcon#wrote, iclass 18, count 0 2006.190.07:31:10.40#ibcon#about to read 3, iclass 18, count 0 2006.190.07:31:10.42#ibcon#read 3, iclass 18, count 0 2006.190.07:31:10.42#ibcon#about to read 4, iclass 18, count 0 2006.190.07:31:10.42#ibcon#read 4, iclass 18, count 0 2006.190.07:31:10.42#ibcon#about to read 5, iclass 18, count 0 2006.190.07:31:10.42#ibcon#read 5, iclass 18, count 0 2006.190.07:31:10.42#ibcon#about to read 6, iclass 18, count 0 2006.190.07:31:10.42#ibcon#read 6, iclass 18, count 0 2006.190.07:31:10.42#ibcon#end of sib2, iclass 18, count 0 2006.190.07:31:10.42#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:31:10.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:31:10.42#ibcon#[25=USB\r\n] 2006.190.07:31:10.42#ibcon#*before write, iclass 18, count 0 2006.190.07:31:10.42#ibcon#enter sib2, iclass 18, count 0 2006.190.07:31:10.42#ibcon#flushed, iclass 18, count 0 2006.190.07:31:10.42#ibcon#about to write, iclass 18, count 0 2006.190.07:31:10.42#ibcon#wrote, iclass 18, count 0 2006.190.07:31:10.42#ibcon#about to read 3, iclass 18, count 0 2006.190.07:31:10.45#ibcon#read 3, iclass 18, count 0 2006.190.07:31:10.45#ibcon#about to read 4, iclass 18, count 0 2006.190.07:31:10.45#ibcon#read 4, iclass 18, count 0 2006.190.07:31:10.45#ibcon#about to read 5, iclass 18, count 0 2006.190.07:31:10.45#ibcon#read 5, iclass 18, count 0 2006.190.07:31:10.45#ibcon#about to read 6, iclass 18, count 0 2006.190.07:31:10.45#ibcon#read 6, iclass 18, count 0 2006.190.07:31:10.45#ibcon#end of sib2, iclass 18, count 0 2006.190.07:31:10.45#ibcon#*after write, iclass 18, count 0 2006.190.07:31:10.45#ibcon#*before return 0, iclass 18, count 0 2006.190.07:31:10.45#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:31:10.45#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:31:10.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:31:10.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:31:10.45$vc4f8/valo=8,852.99 2006.190.07:31:10.45#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:31:10.45#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:31:10.45#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:10.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:31:10.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:31:10.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:31:10.45#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:31:10.45#ibcon#first serial, iclass 20, count 0 2006.190.07:31:10.45#ibcon#enter sib2, iclass 20, count 0 2006.190.07:31:10.45#ibcon#flushed, iclass 20, count 0 2006.190.07:31:10.45#ibcon#about to write, iclass 20, count 0 2006.190.07:31:10.45#ibcon#wrote, iclass 20, count 0 2006.190.07:31:10.45#ibcon#about to read 3, iclass 20, count 0 2006.190.07:31:10.47#ibcon#read 3, iclass 20, count 0 2006.190.07:31:10.47#ibcon#about to read 4, iclass 20, count 0 2006.190.07:31:10.47#ibcon#read 4, iclass 20, count 0 2006.190.07:31:10.47#ibcon#about to read 5, iclass 20, count 0 2006.190.07:31:10.47#ibcon#read 5, iclass 20, count 0 2006.190.07:31:10.47#ibcon#about to read 6, iclass 20, count 0 2006.190.07:31:10.47#ibcon#read 6, iclass 20, count 0 2006.190.07:31:10.47#ibcon#end of sib2, iclass 20, count 0 2006.190.07:31:10.47#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:31:10.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:31:10.47#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:31:10.47#ibcon#*before write, iclass 20, count 0 2006.190.07:31:10.47#ibcon#enter sib2, iclass 20, count 0 2006.190.07:31:10.47#ibcon#flushed, iclass 20, count 0 2006.190.07:31:10.47#ibcon#about to write, iclass 20, count 0 2006.190.07:31:10.47#ibcon#wrote, iclass 20, count 0 2006.190.07:31:10.47#ibcon#about to read 3, iclass 20, count 0 2006.190.07:31:10.51#ibcon#read 3, iclass 20, count 0 2006.190.07:31:10.51#ibcon#about to read 4, iclass 20, count 0 2006.190.07:31:10.51#ibcon#read 4, iclass 20, count 0 2006.190.07:31:10.51#ibcon#about to read 5, iclass 20, count 0 2006.190.07:31:10.51#ibcon#read 5, iclass 20, count 0 2006.190.07:31:10.51#ibcon#about to read 6, iclass 20, count 0 2006.190.07:31:10.51#ibcon#read 6, iclass 20, count 0 2006.190.07:31:10.51#ibcon#end of sib2, iclass 20, count 0 2006.190.07:31:10.51#ibcon#*after write, iclass 20, count 0 2006.190.07:31:10.51#ibcon#*before return 0, iclass 20, count 0 2006.190.07:31:10.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:31:10.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:31:10.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:31:10.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:31:10.51$vc4f8/va=8,6 2006.190.07:31:10.51#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:31:10.51#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:31:10.51#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:10.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:31:10.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:31:10.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:31:10.57#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:31:10.57#ibcon#first serial, iclass 22, count 2 2006.190.07:31:10.58#ibcon#enter sib2, iclass 22, count 2 2006.190.07:31:10.58#ibcon#flushed, iclass 22, count 2 2006.190.07:31:10.58#ibcon#about to write, iclass 22, count 2 2006.190.07:31:10.58#ibcon#wrote, iclass 22, count 2 2006.190.07:31:10.58#ibcon#about to read 3, iclass 22, count 2 2006.190.07:31:10.59#ibcon#read 3, iclass 22, count 2 2006.190.07:31:10.59#ibcon#about to read 4, iclass 22, count 2 2006.190.07:31:10.59#ibcon#read 4, iclass 22, count 2 2006.190.07:31:10.59#ibcon#about to read 5, iclass 22, count 2 2006.190.07:31:10.59#ibcon#read 5, iclass 22, count 2 2006.190.07:31:10.59#ibcon#about to read 6, iclass 22, count 2 2006.190.07:31:10.59#ibcon#read 6, iclass 22, count 2 2006.190.07:31:10.59#ibcon#end of sib2, iclass 22, count 2 2006.190.07:31:10.59#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:31:10.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:31:10.59#ibcon#[25=AT08-06\r\n] 2006.190.07:31:10.59#ibcon#*before write, iclass 22, count 2 2006.190.07:31:10.59#ibcon#enter sib2, iclass 22, count 2 2006.190.07:31:10.59#ibcon#flushed, iclass 22, count 2 2006.190.07:31:10.59#ibcon#about to write, iclass 22, count 2 2006.190.07:31:10.59#ibcon#wrote, iclass 22, count 2 2006.190.07:31:10.59#ibcon#about to read 3, iclass 22, count 2 2006.190.07:31:10.62#ibcon#read 3, iclass 22, count 2 2006.190.07:31:10.62#ibcon#about to read 4, iclass 22, count 2 2006.190.07:31:10.62#ibcon#read 4, iclass 22, count 2 2006.190.07:31:10.62#ibcon#about to read 5, iclass 22, count 2 2006.190.07:31:10.62#ibcon#read 5, iclass 22, count 2 2006.190.07:31:10.62#ibcon#about to read 6, iclass 22, count 2 2006.190.07:31:10.62#ibcon#read 6, iclass 22, count 2 2006.190.07:31:10.62#ibcon#end of sib2, iclass 22, count 2 2006.190.07:31:10.62#ibcon#*after write, iclass 22, count 2 2006.190.07:31:10.62#ibcon#*before return 0, iclass 22, count 2 2006.190.07:31:10.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:31:10.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:31:10.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:31:10.62#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:10.62#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:31:10.74#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:31:10.74#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:31:10.74#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:31:10.74#ibcon#first serial, iclass 22, count 0 2006.190.07:31:10.74#ibcon#enter sib2, iclass 22, count 0 2006.190.07:31:10.74#ibcon#flushed, iclass 22, count 0 2006.190.07:31:10.74#ibcon#about to write, iclass 22, count 0 2006.190.07:31:10.74#ibcon#wrote, iclass 22, count 0 2006.190.07:31:10.74#ibcon#about to read 3, iclass 22, count 0 2006.190.07:31:10.76#ibcon#read 3, iclass 22, count 0 2006.190.07:31:10.76#ibcon#about to read 4, iclass 22, count 0 2006.190.07:31:10.76#ibcon#read 4, iclass 22, count 0 2006.190.07:31:10.76#ibcon#about to read 5, iclass 22, count 0 2006.190.07:31:10.76#ibcon#read 5, iclass 22, count 0 2006.190.07:31:10.76#ibcon#about to read 6, iclass 22, count 0 2006.190.07:31:10.76#ibcon#read 6, iclass 22, count 0 2006.190.07:31:10.76#ibcon#end of sib2, iclass 22, count 0 2006.190.07:31:10.76#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:31:10.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:31:10.76#ibcon#[25=USB\r\n] 2006.190.07:31:10.76#ibcon#*before write, iclass 22, count 0 2006.190.07:31:10.76#ibcon#enter sib2, iclass 22, count 0 2006.190.07:31:10.76#ibcon#flushed, iclass 22, count 0 2006.190.07:31:10.76#ibcon#about to write, iclass 22, count 0 2006.190.07:31:10.76#ibcon#wrote, iclass 22, count 0 2006.190.07:31:10.76#ibcon#about to read 3, iclass 22, count 0 2006.190.07:31:10.79#ibcon#read 3, iclass 22, count 0 2006.190.07:31:10.79#ibcon#about to read 4, iclass 22, count 0 2006.190.07:31:10.79#ibcon#read 4, iclass 22, count 0 2006.190.07:31:10.79#ibcon#about to read 5, iclass 22, count 0 2006.190.07:31:10.79#ibcon#read 5, iclass 22, count 0 2006.190.07:31:10.79#ibcon#about to read 6, iclass 22, count 0 2006.190.07:31:10.79#ibcon#read 6, iclass 22, count 0 2006.190.07:31:10.79#ibcon#end of sib2, iclass 22, count 0 2006.190.07:31:10.79#ibcon#*after write, iclass 22, count 0 2006.190.07:31:10.79#ibcon#*before return 0, iclass 22, count 0 2006.190.07:31:10.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:31:10.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:31:10.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:31:10.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:31:10.79$vc4f8/vblo=1,632.99 2006.190.07:31:10.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.07:31:10.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.07:31:10.79#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:10.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:31:10.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:31:10.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:31:10.79#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:31:10.79#ibcon#first serial, iclass 24, count 0 2006.190.07:31:10.79#ibcon#enter sib2, iclass 24, count 0 2006.190.07:31:10.79#ibcon#flushed, iclass 24, count 0 2006.190.07:31:10.79#ibcon#about to write, iclass 24, count 0 2006.190.07:31:10.79#ibcon#wrote, iclass 24, count 0 2006.190.07:31:10.79#ibcon#about to read 3, iclass 24, count 0 2006.190.07:31:10.81#ibcon#read 3, iclass 24, count 0 2006.190.07:31:10.81#ibcon#about to read 4, iclass 24, count 0 2006.190.07:31:10.81#ibcon#read 4, iclass 24, count 0 2006.190.07:31:10.81#ibcon#about to read 5, iclass 24, count 0 2006.190.07:31:10.81#ibcon#read 5, iclass 24, count 0 2006.190.07:31:10.81#ibcon#about to read 6, iclass 24, count 0 2006.190.07:31:10.81#ibcon#read 6, iclass 24, count 0 2006.190.07:31:10.81#ibcon#end of sib2, iclass 24, count 0 2006.190.07:31:10.81#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:31:10.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:31:10.81#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:31:10.81#ibcon#*before write, iclass 24, count 0 2006.190.07:31:10.81#ibcon#enter sib2, iclass 24, count 0 2006.190.07:31:10.81#ibcon#flushed, iclass 24, count 0 2006.190.07:31:10.81#ibcon#about to write, iclass 24, count 0 2006.190.07:31:10.81#ibcon#wrote, iclass 24, count 0 2006.190.07:31:10.81#ibcon#about to read 3, iclass 24, count 0 2006.190.07:31:10.85#ibcon#read 3, iclass 24, count 0 2006.190.07:31:10.85#ibcon#about to read 4, iclass 24, count 0 2006.190.07:31:10.85#ibcon#read 4, iclass 24, count 0 2006.190.07:31:10.85#ibcon#about to read 5, iclass 24, count 0 2006.190.07:31:10.85#ibcon#read 5, iclass 24, count 0 2006.190.07:31:10.85#ibcon#about to read 6, iclass 24, count 0 2006.190.07:31:10.85#ibcon#read 6, iclass 24, count 0 2006.190.07:31:10.85#ibcon#end of sib2, iclass 24, count 0 2006.190.07:31:10.85#ibcon#*after write, iclass 24, count 0 2006.190.07:31:10.85#ibcon#*before return 0, iclass 24, count 0 2006.190.07:31:10.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:31:10.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:31:10.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:31:10.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:31:10.85$vc4f8/vb=1,4 2006.190.07:31:10.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.07:31:10.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.07:31:10.85#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:10.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:31:10.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:31:10.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:31:10.85#ibcon#enter wrdev, iclass 26, count 2 2006.190.07:31:10.85#ibcon#first serial, iclass 26, count 2 2006.190.07:31:10.85#ibcon#enter sib2, iclass 26, count 2 2006.190.07:31:10.85#ibcon#flushed, iclass 26, count 2 2006.190.07:31:10.85#ibcon#about to write, iclass 26, count 2 2006.190.07:31:10.85#ibcon#wrote, iclass 26, count 2 2006.190.07:31:10.85#ibcon#about to read 3, iclass 26, count 2 2006.190.07:31:10.87#ibcon#read 3, iclass 26, count 2 2006.190.07:31:10.87#ibcon#about to read 4, iclass 26, count 2 2006.190.07:31:10.87#ibcon#read 4, iclass 26, count 2 2006.190.07:31:10.87#ibcon#about to read 5, iclass 26, count 2 2006.190.07:31:10.87#ibcon#read 5, iclass 26, count 2 2006.190.07:31:10.87#ibcon#about to read 6, iclass 26, count 2 2006.190.07:31:10.87#ibcon#read 6, iclass 26, count 2 2006.190.07:31:10.87#ibcon#end of sib2, iclass 26, count 2 2006.190.07:31:10.87#ibcon#*mode == 0, iclass 26, count 2 2006.190.07:31:10.87#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.07:31:10.87#ibcon#[27=AT01-04\r\n] 2006.190.07:31:10.87#ibcon#*before write, iclass 26, count 2 2006.190.07:31:10.87#ibcon#enter sib2, iclass 26, count 2 2006.190.07:31:10.87#ibcon#flushed, iclass 26, count 2 2006.190.07:31:10.87#ibcon#about to write, iclass 26, count 2 2006.190.07:31:10.87#ibcon#wrote, iclass 26, count 2 2006.190.07:31:10.87#ibcon#about to read 3, iclass 26, count 2 2006.190.07:31:10.90#ibcon#read 3, iclass 26, count 2 2006.190.07:31:10.90#ibcon#about to read 4, iclass 26, count 2 2006.190.07:31:10.90#ibcon#read 4, iclass 26, count 2 2006.190.07:31:10.90#ibcon#about to read 5, iclass 26, count 2 2006.190.07:31:10.90#ibcon#read 5, iclass 26, count 2 2006.190.07:31:10.90#ibcon#about to read 6, iclass 26, count 2 2006.190.07:31:10.90#ibcon#read 6, iclass 26, count 2 2006.190.07:31:10.90#ibcon#end of sib2, iclass 26, count 2 2006.190.07:31:10.90#ibcon#*after write, iclass 26, count 2 2006.190.07:31:10.90#ibcon#*before return 0, iclass 26, count 2 2006.190.07:31:10.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:31:10.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:31:10.90#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.07:31:10.90#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:10.90#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:31:11.02#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:31:11.02#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:31:11.02#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:31:11.02#ibcon#first serial, iclass 26, count 0 2006.190.07:31:11.02#ibcon#enter sib2, iclass 26, count 0 2006.190.07:31:11.02#ibcon#flushed, iclass 26, count 0 2006.190.07:31:11.02#ibcon#about to write, iclass 26, count 0 2006.190.07:31:11.02#ibcon#wrote, iclass 26, count 0 2006.190.07:31:11.02#ibcon#about to read 3, iclass 26, count 0 2006.190.07:31:11.04#ibcon#read 3, iclass 26, count 0 2006.190.07:31:11.04#ibcon#about to read 4, iclass 26, count 0 2006.190.07:31:11.04#ibcon#read 4, iclass 26, count 0 2006.190.07:31:11.04#ibcon#about to read 5, iclass 26, count 0 2006.190.07:31:11.04#ibcon#read 5, iclass 26, count 0 2006.190.07:31:11.04#ibcon#about to read 6, iclass 26, count 0 2006.190.07:31:11.04#ibcon#read 6, iclass 26, count 0 2006.190.07:31:11.04#ibcon#end of sib2, iclass 26, count 0 2006.190.07:31:11.04#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:31:11.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:31:11.04#ibcon#[27=USB\r\n] 2006.190.07:31:11.04#ibcon#*before write, iclass 26, count 0 2006.190.07:31:11.04#ibcon#enter sib2, iclass 26, count 0 2006.190.07:31:11.04#ibcon#flushed, iclass 26, count 0 2006.190.07:31:11.04#ibcon#about to write, iclass 26, count 0 2006.190.07:31:11.04#ibcon#wrote, iclass 26, count 0 2006.190.07:31:11.04#ibcon#about to read 3, iclass 26, count 0 2006.190.07:31:11.07#ibcon#read 3, iclass 26, count 0 2006.190.07:31:11.07#ibcon#about to read 4, iclass 26, count 0 2006.190.07:31:11.07#ibcon#read 4, iclass 26, count 0 2006.190.07:31:11.07#ibcon#about to read 5, iclass 26, count 0 2006.190.07:31:11.07#ibcon#read 5, iclass 26, count 0 2006.190.07:31:11.07#ibcon#about to read 6, iclass 26, count 0 2006.190.07:31:11.07#ibcon#read 6, iclass 26, count 0 2006.190.07:31:11.07#ibcon#end of sib2, iclass 26, count 0 2006.190.07:31:11.07#ibcon#*after write, iclass 26, count 0 2006.190.07:31:11.07#ibcon#*before return 0, iclass 26, count 0 2006.190.07:31:11.07#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:31:11.07#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:31:11.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:31:11.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:31:11.07$vc4f8/vblo=2,640.99 2006.190.07:31:11.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:31:11.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:31:11.07#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:11.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:11.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:11.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:11.07#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:31:11.07#ibcon#first serial, iclass 28, count 0 2006.190.07:31:11.07#ibcon#enter sib2, iclass 28, count 0 2006.190.07:31:11.07#ibcon#flushed, iclass 28, count 0 2006.190.07:31:11.07#ibcon#about to write, iclass 28, count 0 2006.190.07:31:11.07#ibcon#wrote, iclass 28, count 0 2006.190.07:31:11.07#ibcon#about to read 3, iclass 28, count 0 2006.190.07:31:11.09#ibcon#read 3, iclass 28, count 0 2006.190.07:31:11.09#ibcon#about to read 4, iclass 28, count 0 2006.190.07:31:11.09#ibcon#read 4, iclass 28, count 0 2006.190.07:31:11.09#ibcon#about to read 5, iclass 28, count 0 2006.190.07:31:11.09#ibcon#read 5, iclass 28, count 0 2006.190.07:31:11.09#ibcon#about to read 6, iclass 28, count 0 2006.190.07:31:11.09#ibcon#read 6, iclass 28, count 0 2006.190.07:31:11.09#ibcon#end of sib2, iclass 28, count 0 2006.190.07:31:11.09#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:31:11.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:31:11.09#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:31:11.09#ibcon#*before write, iclass 28, count 0 2006.190.07:31:11.09#ibcon#enter sib2, iclass 28, count 0 2006.190.07:31:11.09#ibcon#flushed, iclass 28, count 0 2006.190.07:31:11.09#ibcon#about to write, iclass 28, count 0 2006.190.07:31:11.09#ibcon#wrote, iclass 28, count 0 2006.190.07:31:11.09#ibcon#about to read 3, iclass 28, count 0 2006.190.07:31:11.13#ibcon#read 3, iclass 28, count 0 2006.190.07:31:11.13#ibcon#about to read 4, iclass 28, count 0 2006.190.07:31:11.13#ibcon#read 4, iclass 28, count 0 2006.190.07:31:11.13#ibcon#about to read 5, iclass 28, count 0 2006.190.07:31:11.13#ibcon#read 5, iclass 28, count 0 2006.190.07:31:11.13#ibcon#about to read 6, iclass 28, count 0 2006.190.07:31:11.13#ibcon#read 6, iclass 28, count 0 2006.190.07:31:11.13#ibcon#end of sib2, iclass 28, count 0 2006.190.07:31:11.13#ibcon#*after write, iclass 28, count 0 2006.190.07:31:11.13#ibcon#*before return 0, iclass 28, count 0 2006.190.07:31:11.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:11.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:31:11.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:31:11.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:31:11.13$vc4f8/vb=2,4 2006.190.07:31:11.13#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:31:11.13#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:31:11.13#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:11.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:11.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:11.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:11.19#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:31:11.19#ibcon#first serial, iclass 30, count 2 2006.190.07:31:11.19#ibcon#enter sib2, iclass 30, count 2 2006.190.07:31:11.19#ibcon#flushed, iclass 30, count 2 2006.190.07:31:11.19#ibcon#about to write, iclass 30, count 2 2006.190.07:31:11.19#ibcon#wrote, iclass 30, count 2 2006.190.07:31:11.19#ibcon#about to read 3, iclass 30, count 2 2006.190.07:31:11.21#ibcon#read 3, iclass 30, count 2 2006.190.07:31:11.21#ibcon#about to read 4, iclass 30, count 2 2006.190.07:31:11.21#ibcon#read 4, iclass 30, count 2 2006.190.07:31:11.21#ibcon#about to read 5, iclass 30, count 2 2006.190.07:31:11.21#ibcon#read 5, iclass 30, count 2 2006.190.07:31:11.21#ibcon#about to read 6, iclass 30, count 2 2006.190.07:31:11.21#ibcon#read 6, iclass 30, count 2 2006.190.07:31:11.21#ibcon#end of sib2, iclass 30, count 2 2006.190.07:31:11.21#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:31:11.21#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:31:11.21#ibcon#[27=AT02-04\r\n] 2006.190.07:31:11.21#ibcon#*before write, iclass 30, count 2 2006.190.07:31:11.21#ibcon#enter sib2, iclass 30, count 2 2006.190.07:31:11.21#ibcon#flushed, iclass 30, count 2 2006.190.07:31:11.21#ibcon#about to write, iclass 30, count 2 2006.190.07:31:11.21#ibcon#wrote, iclass 30, count 2 2006.190.07:31:11.21#ibcon#about to read 3, iclass 30, count 2 2006.190.07:31:11.24#ibcon#read 3, iclass 30, count 2 2006.190.07:31:11.24#ibcon#about to read 4, iclass 30, count 2 2006.190.07:31:11.24#ibcon#read 4, iclass 30, count 2 2006.190.07:31:11.24#ibcon#about to read 5, iclass 30, count 2 2006.190.07:31:11.24#ibcon#read 5, iclass 30, count 2 2006.190.07:31:11.24#ibcon#about to read 6, iclass 30, count 2 2006.190.07:31:11.24#ibcon#read 6, iclass 30, count 2 2006.190.07:31:11.24#ibcon#end of sib2, iclass 30, count 2 2006.190.07:31:11.24#ibcon#*after write, iclass 30, count 2 2006.190.07:31:11.24#ibcon#*before return 0, iclass 30, count 2 2006.190.07:31:11.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:11.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:31:11.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:31:11.24#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:11.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:11.36#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:11.36#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:11.36#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:31:11.36#ibcon#first serial, iclass 30, count 0 2006.190.07:31:11.36#ibcon#enter sib2, iclass 30, count 0 2006.190.07:31:11.36#ibcon#flushed, iclass 30, count 0 2006.190.07:31:11.36#ibcon#about to write, iclass 30, count 0 2006.190.07:31:11.36#ibcon#wrote, iclass 30, count 0 2006.190.07:31:11.36#ibcon#about to read 3, iclass 30, count 0 2006.190.07:31:11.38#ibcon#read 3, iclass 30, count 0 2006.190.07:31:11.38#ibcon#about to read 4, iclass 30, count 0 2006.190.07:31:11.38#ibcon#read 4, iclass 30, count 0 2006.190.07:31:11.38#ibcon#about to read 5, iclass 30, count 0 2006.190.07:31:11.38#ibcon#read 5, iclass 30, count 0 2006.190.07:31:11.38#ibcon#about to read 6, iclass 30, count 0 2006.190.07:31:11.38#ibcon#read 6, iclass 30, count 0 2006.190.07:31:11.38#ibcon#end of sib2, iclass 30, count 0 2006.190.07:31:11.38#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:31:11.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:31:11.38#ibcon#[27=USB\r\n] 2006.190.07:31:11.38#ibcon#*before write, iclass 30, count 0 2006.190.07:31:11.38#ibcon#enter sib2, iclass 30, count 0 2006.190.07:31:11.38#ibcon#flushed, iclass 30, count 0 2006.190.07:31:11.38#ibcon#about to write, iclass 30, count 0 2006.190.07:31:11.38#ibcon#wrote, iclass 30, count 0 2006.190.07:31:11.38#ibcon#about to read 3, iclass 30, count 0 2006.190.07:31:11.41#ibcon#read 3, iclass 30, count 0 2006.190.07:31:11.41#ibcon#about to read 4, iclass 30, count 0 2006.190.07:31:11.41#ibcon#read 4, iclass 30, count 0 2006.190.07:31:11.41#ibcon#about to read 5, iclass 30, count 0 2006.190.07:31:11.41#ibcon#read 5, iclass 30, count 0 2006.190.07:31:11.41#ibcon#about to read 6, iclass 30, count 0 2006.190.07:31:11.41#ibcon#read 6, iclass 30, count 0 2006.190.07:31:11.41#ibcon#end of sib2, iclass 30, count 0 2006.190.07:31:11.41#ibcon#*after write, iclass 30, count 0 2006.190.07:31:11.41#ibcon#*before return 0, iclass 30, count 0 2006.190.07:31:11.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:11.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:31:11.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:31:11.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:31:11.41$vc4f8/vblo=3,656.99 2006.190.07:31:11.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:31:11.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:31:11.41#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:11.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:11.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:11.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:11.41#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:31:11.41#ibcon#first serial, iclass 32, count 0 2006.190.07:31:11.41#ibcon#enter sib2, iclass 32, count 0 2006.190.07:31:11.41#ibcon#flushed, iclass 32, count 0 2006.190.07:31:11.41#ibcon#about to write, iclass 32, count 0 2006.190.07:31:11.41#ibcon#wrote, iclass 32, count 0 2006.190.07:31:11.41#ibcon#about to read 3, iclass 32, count 0 2006.190.07:31:11.43#ibcon#read 3, iclass 32, count 0 2006.190.07:31:11.43#ibcon#about to read 4, iclass 32, count 0 2006.190.07:31:11.43#ibcon#read 4, iclass 32, count 0 2006.190.07:31:11.43#ibcon#about to read 5, iclass 32, count 0 2006.190.07:31:11.43#ibcon#read 5, iclass 32, count 0 2006.190.07:31:11.43#ibcon#about to read 6, iclass 32, count 0 2006.190.07:31:11.43#ibcon#read 6, iclass 32, count 0 2006.190.07:31:11.43#ibcon#end of sib2, iclass 32, count 0 2006.190.07:31:11.43#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:31:11.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:31:11.43#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:31:11.43#ibcon#*before write, iclass 32, count 0 2006.190.07:31:11.43#ibcon#enter sib2, iclass 32, count 0 2006.190.07:31:11.43#ibcon#flushed, iclass 32, count 0 2006.190.07:31:11.43#ibcon#about to write, iclass 32, count 0 2006.190.07:31:11.43#ibcon#wrote, iclass 32, count 0 2006.190.07:31:11.43#ibcon#about to read 3, iclass 32, count 0 2006.190.07:31:11.47#ibcon#read 3, iclass 32, count 0 2006.190.07:31:11.47#ibcon#about to read 4, iclass 32, count 0 2006.190.07:31:11.47#ibcon#read 4, iclass 32, count 0 2006.190.07:31:11.47#ibcon#about to read 5, iclass 32, count 0 2006.190.07:31:11.47#ibcon#read 5, iclass 32, count 0 2006.190.07:31:11.47#ibcon#about to read 6, iclass 32, count 0 2006.190.07:31:11.47#ibcon#read 6, iclass 32, count 0 2006.190.07:31:11.47#ibcon#end of sib2, iclass 32, count 0 2006.190.07:31:11.47#ibcon#*after write, iclass 32, count 0 2006.190.07:31:11.47#ibcon#*before return 0, iclass 32, count 0 2006.190.07:31:11.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:11.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:31:11.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:31:11.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:31:11.47$vc4f8/vb=3,4 2006.190.07:31:11.47#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:31:11.47#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:31:11.47#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:11.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:11.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:11.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:11.53#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:31:11.53#ibcon#first serial, iclass 34, count 2 2006.190.07:31:11.53#ibcon#enter sib2, iclass 34, count 2 2006.190.07:31:11.53#ibcon#flushed, iclass 34, count 2 2006.190.07:31:11.53#ibcon#about to write, iclass 34, count 2 2006.190.07:31:11.53#ibcon#wrote, iclass 34, count 2 2006.190.07:31:11.53#ibcon#about to read 3, iclass 34, count 2 2006.190.07:31:11.55#ibcon#read 3, iclass 34, count 2 2006.190.07:31:11.55#ibcon#about to read 4, iclass 34, count 2 2006.190.07:31:11.55#ibcon#read 4, iclass 34, count 2 2006.190.07:31:11.55#ibcon#about to read 5, iclass 34, count 2 2006.190.07:31:11.55#ibcon#read 5, iclass 34, count 2 2006.190.07:31:11.55#ibcon#about to read 6, iclass 34, count 2 2006.190.07:31:11.55#ibcon#read 6, iclass 34, count 2 2006.190.07:31:11.55#ibcon#end of sib2, iclass 34, count 2 2006.190.07:31:11.55#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:31:11.55#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:31:11.55#ibcon#[27=AT03-04\r\n] 2006.190.07:31:11.55#ibcon#*before write, iclass 34, count 2 2006.190.07:31:11.55#ibcon#enter sib2, iclass 34, count 2 2006.190.07:31:11.55#ibcon#flushed, iclass 34, count 2 2006.190.07:31:11.55#ibcon#about to write, iclass 34, count 2 2006.190.07:31:11.55#ibcon#wrote, iclass 34, count 2 2006.190.07:31:11.55#ibcon#about to read 3, iclass 34, count 2 2006.190.07:31:11.58#ibcon#read 3, iclass 34, count 2 2006.190.07:31:11.58#ibcon#about to read 4, iclass 34, count 2 2006.190.07:31:11.58#ibcon#read 4, iclass 34, count 2 2006.190.07:31:11.58#ibcon#about to read 5, iclass 34, count 2 2006.190.07:31:11.58#ibcon#read 5, iclass 34, count 2 2006.190.07:31:11.58#ibcon#about to read 6, iclass 34, count 2 2006.190.07:31:11.58#ibcon#read 6, iclass 34, count 2 2006.190.07:31:11.58#ibcon#end of sib2, iclass 34, count 2 2006.190.07:31:11.58#ibcon#*after write, iclass 34, count 2 2006.190.07:31:11.58#ibcon#*before return 0, iclass 34, count 2 2006.190.07:31:11.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:11.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:31:11.58#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:31:11.58#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:11.58#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:11.70#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:11.70#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:11.70#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:31:11.70#ibcon#first serial, iclass 34, count 0 2006.190.07:31:11.70#ibcon#enter sib2, iclass 34, count 0 2006.190.07:31:11.70#ibcon#flushed, iclass 34, count 0 2006.190.07:31:11.70#ibcon#about to write, iclass 34, count 0 2006.190.07:31:11.70#ibcon#wrote, iclass 34, count 0 2006.190.07:31:11.70#ibcon#about to read 3, iclass 34, count 0 2006.190.07:31:11.72#ibcon#read 3, iclass 34, count 0 2006.190.07:31:11.72#ibcon#about to read 4, iclass 34, count 0 2006.190.07:31:11.72#ibcon#read 4, iclass 34, count 0 2006.190.07:31:11.72#ibcon#about to read 5, iclass 34, count 0 2006.190.07:31:11.72#ibcon#read 5, iclass 34, count 0 2006.190.07:31:11.72#ibcon#about to read 6, iclass 34, count 0 2006.190.07:31:11.72#ibcon#read 6, iclass 34, count 0 2006.190.07:31:11.72#ibcon#end of sib2, iclass 34, count 0 2006.190.07:31:11.72#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:31:11.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:31:11.72#ibcon#[27=USB\r\n] 2006.190.07:31:11.72#ibcon#*before write, iclass 34, count 0 2006.190.07:31:11.72#ibcon#enter sib2, iclass 34, count 0 2006.190.07:31:11.72#ibcon#flushed, iclass 34, count 0 2006.190.07:31:11.72#ibcon#about to write, iclass 34, count 0 2006.190.07:31:11.72#ibcon#wrote, iclass 34, count 0 2006.190.07:31:11.72#ibcon#about to read 3, iclass 34, count 0 2006.190.07:31:11.75#ibcon#read 3, iclass 34, count 0 2006.190.07:31:11.75#ibcon#about to read 4, iclass 34, count 0 2006.190.07:31:11.75#ibcon#read 4, iclass 34, count 0 2006.190.07:31:11.75#ibcon#about to read 5, iclass 34, count 0 2006.190.07:31:11.75#ibcon#read 5, iclass 34, count 0 2006.190.07:31:11.75#ibcon#about to read 6, iclass 34, count 0 2006.190.07:31:11.75#ibcon#read 6, iclass 34, count 0 2006.190.07:31:11.75#ibcon#end of sib2, iclass 34, count 0 2006.190.07:31:11.75#ibcon#*after write, iclass 34, count 0 2006.190.07:31:11.75#ibcon#*before return 0, iclass 34, count 0 2006.190.07:31:11.75#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:11.75#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:31:11.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:31:11.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:31:11.75$vc4f8/vblo=4,712.99 2006.190.07:31:11.75#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:31:11.75#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:31:11.75#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:11.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:11.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:11.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:11.75#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:31:11.75#ibcon#first serial, iclass 36, count 0 2006.190.07:31:11.75#ibcon#enter sib2, iclass 36, count 0 2006.190.07:31:11.75#ibcon#flushed, iclass 36, count 0 2006.190.07:31:11.75#ibcon#about to write, iclass 36, count 0 2006.190.07:31:11.75#ibcon#wrote, iclass 36, count 0 2006.190.07:31:11.75#ibcon#about to read 3, iclass 36, count 0 2006.190.07:31:11.77#ibcon#read 3, iclass 36, count 0 2006.190.07:31:11.77#ibcon#about to read 4, iclass 36, count 0 2006.190.07:31:11.77#ibcon#read 4, iclass 36, count 0 2006.190.07:31:11.77#ibcon#about to read 5, iclass 36, count 0 2006.190.07:31:11.77#ibcon#read 5, iclass 36, count 0 2006.190.07:31:11.77#ibcon#about to read 6, iclass 36, count 0 2006.190.07:31:11.77#ibcon#read 6, iclass 36, count 0 2006.190.07:31:11.77#ibcon#end of sib2, iclass 36, count 0 2006.190.07:31:11.77#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:31:11.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:31:11.77#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:31:11.77#ibcon#*before write, iclass 36, count 0 2006.190.07:31:11.77#ibcon#enter sib2, iclass 36, count 0 2006.190.07:31:11.77#ibcon#flushed, iclass 36, count 0 2006.190.07:31:11.77#ibcon#about to write, iclass 36, count 0 2006.190.07:31:11.77#ibcon#wrote, iclass 36, count 0 2006.190.07:31:11.77#ibcon#about to read 3, iclass 36, count 0 2006.190.07:31:11.81#ibcon#read 3, iclass 36, count 0 2006.190.07:31:11.81#ibcon#about to read 4, iclass 36, count 0 2006.190.07:31:11.81#ibcon#read 4, iclass 36, count 0 2006.190.07:31:11.81#ibcon#about to read 5, iclass 36, count 0 2006.190.07:31:11.81#ibcon#read 5, iclass 36, count 0 2006.190.07:31:11.81#ibcon#about to read 6, iclass 36, count 0 2006.190.07:31:11.81#ibcon#read 6, iclass 36, count 0 2006.190.07:31:11.81#ibcon#end of sib2, iclass 36, count 0 2006.190.07:31:11.81#ibcon#*after write, iclass 36, count 0 2006.190.07:31:11.81#ibcon#*before return 0, iclass 36, count 0 2006.190.07:31:11.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:11.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:31:11.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:31:11.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:31:11.81$vc4f8/vb=4,4 2006.190.07:31:11.81#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.07:31:11.81#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.07:31:11.81#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:11.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:11.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:11.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:11.87#ibcon#enter wrdev, iclass 38, count 2 2006.190.07:31:11.87#ibcon#first serial, iclass 38, count 2 2006.190.07:31:11.87#ibcon#enter sib2, iclass 38, count 2 2006.190.07:31:11.87#ibcon#flushed, iclass 38, count 2 2006.190.07:31:11.87#ibcon#about to write, iclass 38, count 2 2006.190.07:31:11.87#ibcon#wrote, iclass 38, count 2 2006.190.07:31:11.87#ibcon#about to read 3, iclass 38, count 2 2006.190.07:31:11.89#ibcon#read 3, iclass 38, count 2 2006.190.07:31:11.89#ibcon#about to read 4, iclass 38, count 2 2006.190.07:31:11.89#ibcon#read 4, iclass 38, count 2 2006.190.07:31:11.89#ibcon#about to read 5, iclass 38, count 2 2006.190.07:31:11.89#ibcon#read 5, iclass 38, count 2 2006.190.07:31:11.89#ibcon#about to read 6, iclass 38, count 2 2006.190.07:31:11.89#ibcon#read 6, iclass 38, count 2 2006.190.07:31:11.89#ibcon#end of sib2, iclass 38, count 2 2006.190.07:31:11.89#ibcon#*mode == 0, iclass 38, count 2 2006.190.07:31:11.89#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.07:31:11.89#ibcon#[27=AT04-04\r\n] 2006.190.07:31:11.89#ibcon#*before write, iclass 38, count 2 2006.190.07:31:11.89#ibcon#enter sib2, iclass 38, count 2 2006.190.07:31:11.89#ibcon#flushed, iclass 38, count 2 2006.190.07:31:11.89#ibcon#about to write, iclass 38, count 2 2006.190.07:31:11.89#ibcon#wrote, iclass 38, count 2 2006.190.07:31:11.89#ibcon#about to read 3, iclass 38, count 2 2006.190.07:31:11.92#ibcon#read 3, iclass 38, count 2 2006.190.07:31:11.92#ibcon#about to read 4, iclass 38, count 2 2006.190.07:31:11.92#ibcon#read 4, iclass 38, count 2 2006.190.07:31:11.92#ibcon#about to read 5, iclass 38, count 2 2006.190.07:31:11.92#ibcon#read 5, iclass 38, count 2 2006.190.07:31:11.92#ibcon#about to read 6, iclass 38, count 2 2006.190.07:31:11.92#ibcon#read 6, iclass 38, count 2 2006.190.07:31:11.92#ibcon#end of sib2, iclass 38, count 2 2006.190.07:31:11.92#ibcon#*after write, iclass 38, count 2 2006.190.07:31:11.92#ibcon#*before return 0, iclass 38, count 2 2006.190.07:31:11.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:11.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:31:11.92#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.07:31:11.92#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:11.92#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:12.04#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:12.04#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:12.04#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:31:12.04#ibcon#first serial, iclass 38, count 0 2006.190.07:31:12.04#ibcon#enter sib2, iclass 38, count 0 2006.190.07:31:12.04#ibcon#flushed, iclass 38, count 0 2006.190.07:31:12.04#ibcon#about to write, iclass 38, count 0 2006.190.07:31:12.04#ibcon#wrote, iclass 38, count 0 2006.190.07:31:12.04#ibcon#about to read 3, iclass 38, count 0 2006.190.07:31:12.06#ibcon#read 3, iclass 38, count 0 2006.190.07:31:12.06#ibcon#about to read 4, iclass 38, count 0 2006.190.07:31:12.06#ibcon#read 4, iclass 38, count 0 2006.190.07:31:12.06#ibcon#about to read 5, iclass 38, count 0 2006.190.07:31:12.06#ibcon#read 5, iclass 38, count 0 2006.190.07:31:12.06#ibcon#about to read 6, iclass 38, count 0 2006.190.07:31:12.06#ibcon#read 6, iclass 38, count 0 2006.190.07:31:12.06#ibcon#end of sib2, iclass 38, count 0 2006.190.07:31:12.06#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:31:12.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:31:12.06#ibcon#[27=USB\r\n] 2006.190.07:31:12.06#ibcon#*before write, iclass 38, count 0 2006.190.07:31:12.06#ibcon#enter sib2, iclass 38, count 0 2006.190.07:31:12.06#ibcon#flushed, iclass 38, count 0 2006.190.07:31:12.06#ibcon#about to write, iclass 38, count 0 2006.190.07:31:12.06#ibcon#wrote, iclass 38, count 0 2006.190.07:31:12.06#ibcon#about to read 3, iclass 38, count 0 2006.190.07:31:12.09#ibcon#read 3, iclass 38, count 0 2006.190.07:31:12.09#ibcon#about to read 4, iclass 38, count 0 2006.190.07:31:12.09#ibcon#read 4, iclass 38, count 0 2006.190.07:31:12.09#ibcon#about to read 5, iclass 38, count 0 2006.190.07:31:12.09#ibcon#read 5, iclass 38, count 0 2006.190.07:31:12.09#ibcon#about to read 6, iclass 38, count 0 2006.190.07:31:12.09#ibcon#read 6, iclass 38, count 0 2006.190.07:31:12.09#ibcon#end of sib2, iclass 38, count 0 2006.190.07:31:12.09#ibcon#*after write, iclass 38, count 0 2006.190.07:31:12.09#ibcon#*before return 0, iclass 38, count 0 2006.190.07:31:12.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:12.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:31:12.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:31:12.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:31:12.09$vc4f8/vblo=5,744.99 2006.190.07:31:12.09#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:31:12.09#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:31:12.09#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:12.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:12.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:12.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:12.09#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:31:12.09#ibcon#first serial, iclass 40, count 0 2006.190.07:31:12.09#ibcon#enter sib2, iclass 40, count 0 2006.190.07:31:12.09#ibcon#flushed, iclass 40, count 0 2006.190.07:31:12.09#ibcon#about to write, iclass 40, count 0 2006.190.07:31:12.09#ibcon#wrote, iclass 40, count 0 2006.190.07:31:12.09#ibcon#about to read 3, iclass 40, count 0 2006.190.07:31:12.11#ibcon#read 3, iclass 40, count 0 2006.190.07:31:12.11#ibcon#about to read 4, iclass 40, count 0 2006.190.07:31:12.11#ibcon#read 4, iclass 40, count 0 2006.190.07:31:12.11#ibcon#about to read 5, iclass 40, count 0 2006.190.07:31:12.11#ibcon#read 5, iclass 40, count 0 2006.190.07:31:12.11#ibcon#about to read 6, iclass 40, count 0 2006.190.07:31:12.11#ibcon#read 6, iclass 40, count 0 2006.190.07:31:12.11#ibcon#end of sib2, iclass 40, count 0 2006.190.07:31:12.11#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:31:12.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:31:12.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:31:12.11#ibcon#*before write, iclass 40, count 0 2006.190.07:31:12.11#ibcon#enter sib2, iclass 40, count 0 2006.190.07:31:12.11#ibcon#flushed, iclass 40, count 0 2006.190.07:31:12.11#ibcon#about to write, iclass 40, count 0 2006.190.07:31:12.11#ibcon#wrote, iclass 40, count 0 2006.190.07:31:12.11#ibcon#about to read 3, iclass 40, count 0 2006.190.07:31:12.15#ibcon#read 3, iclass 40, count 0 2006.190.07:31:12.15#ibcon#about to read 4, iclass 40, count 0 2006.190.07:31:12.15#ibcon#read 4, iclass 40, count 0 2006.190.07:31:12.15#ibcon#about to read 5, iclass 40, count 0 2006.190.07:31:12.15#ibcon#read 5, iclass 40, count 0 2006.190.07:31:12.15#ibcon#about to read 6, iclass 40, count 0 2006.190.07:31:12.15#ibcon#read 6, iclass 40, count 0 2006.190.07:31:12.15#ibcon#end of sib2, iclass 40, count 0 2006.190.07:31:12.15#ibcon#*after write, iclass 40, count 0 2006.190.07:31:12.15#ibcon#*before return 0, iclass 40, count 0 2006.190.07:31:12.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:12.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:31:12.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:31:12.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:31:12.15$vc4f8/vb=5,4 2006.190.07:31:12.15#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:31:12.15#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:31:12.15#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:12.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:12.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:12.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:12.21#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:31:12.21#ibcon#first serial, iclass 4, count 2 2006.190.07:31:12.21#ibcon#enter sib2, iclass 4, count 2 2006.190.07:31:12.21#ibcon#flushed, iclass 4, count 2 2006.190.07:31:12.21#ibcon#about to write, iclass 4, count 2 2006.190.07:31:12.21#ibcon#wrote, iclass 4, count 2 2006.190.07:31:12.21#ibcon#about to read 3, iclass 4, count 2 2006.190.07:31:12.23#ibcon#read 3, iclass 4, count 2 2006.190.07:31:12.23#ibcon#about to read 4, iclass 4, count 2 2006.190.07:31:12.23#ibcon#read 4, iclass 4, count 2 2006.190.07:31:12.23#ibcon#about to read 5, iclass 4, count 2 2006.190.07:31:12.23#ibcon#read 5, iclass 4, count 2 2006.190.07:31:12.23#ibcon#about to read 6, iclass 4, count 2 2006.190.07:31:12.23#ibcon#read 6, iclass 4, count 2 2006.190.07:31:12.23#ibcon#end of sib2, iclass 4, count 2 2006.190.07:31:12.23#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:31:12.23#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:31:12.23#ibcon#[27=AT05-04\r\n] 2006.190.07:31:12.23#ibcon#*before write, iclass 4, count 2 2006.190.07:31:12.23#ibcon#enter sib2, iclass 4, count 2 2006.190.07:31:12.23#ibcon#flushed, iclass 4, count 2 2006.190.07:31:12.23#ibcon#about to write, iclass 4, count 2 2006.190.07:31:12.23#ibcon#wrote, iclass 4, count 2 2006.190.07:31:12.23#ibcon#about to read 3, iclass 4, count 2 2006.190.07:31:12.26#ibcon#read 3, iclass 4, count 2 2006.190.07:31:12.26#ibcon#about to read 4, iclass 4, count 2 2006.190.07:31:12.26#ibcon#read 4, iclass 4, count 2 2006.190.07:31:12.26#ibcon#about to read 5, iclass 4, count 2 2006.190.07:31:12.26#ibcon#read 5, iclass 4, count 2 2006.190.07:31:12.26#ibcon#about to read 6, iclass 4, count 2 2006.190.07:31:12.26#ibcon#read 6, iclass 4, count 2 2006.190.07:31:12.26#ibcon#end of sib2, iclass 4, count 2 2006.190.07:31:12.26#ibcon#*after write, iclass 4, count 2 2006.190.07:31:12.26#ibcon#*before return 0, iclass 4, count 2 2006.190.07:31:12.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:12.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:31:12.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:31:12.26#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:12.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:12.38#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:12.38#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:12.38#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:31:12.38#ibcon#first serial, iclass 4, count 0 2006.190.07:31:12.38#ibcon#enter sib2, iclass 4, count 0 2006.190.07:31:12.38#ibcon#flushed, iclass 4, count 0 2006.190.07:31:12.38#ibcon#about to write, iclass 4, count 0 2006.190.07:31:12.38#ibcon#wrote, iclass 4, count 0 2006.190.07:31:12.38#ibcon#about to read 3, iclass 4, count 0 2006.190.07:31:12.40#ibcon#read 3, iclass 4, count 0 2006.190.07:31:12.40#ibcon#about to read 4, iclass 4, count 0 2006.190.07:31:12.40#ibcon#read 4, iclass 4, count 0 2006.190.07:31:12.40#ibcon#about to read 5, iclass 4, count 0 2006.190.07:31:12.40#ibcon#read 5, iclass 4, count 0 2006.190.07:31:12.40#ibcon#about to read 6, iclass 4, count 0 2006.190.07:31:12.40#ibcon#read 6, iclass 4, count 0 2006.190.07:31:12.40#ibcon#end of sib2, iclass 4, count 0 2006.190.07:31:12.40#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:31:12.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:31:12.40#ibcon#[27=USB\r\n] 2006.190.07:31:12.40#ibcon#*before write, iclass 4, count 0 2006.190.07:31:12.40#ibcon#enter sib2, iclass 4, count 0 2006.190.07:31:12.40#ibcon#flushed, iclass 4, count 0 2006.190.07:31:12.40#ibcon#about to write, iclass 4, count 0 2006.190.07:31:12.40#ibcon#wrote, iclass 4, count 0 2006.190.07:31:12.40#ibcon#about to read 3, iclass 4, count 0 2006.190.07:31:12.43#ibcon#read 3, iclass 4, count 0 2006.190.07:31:12.43#ibcon#about to read 4, iclass 4, count 0 2006.190.07:31:12.43#ibcon#read 4, iclass 4, count 0 2006.190.07:31:12.43#ibcon#about to read 5, iclass 4, count 0 2006.190.07:31:12.43#ibcon#read 5, iclass 4, count 0 2006.190.07:31:12.43#ibcon#about to read 6, iclass 4, count 0 2006.190.07:31:12.43#ibcon#read 6, iclass 4, count 0 2006.190.07:31:12.43#ibcon#end of sib2, iclass 4, count 0 2006.190.07:31:12.43#ibcon#*after write, iclass 4, count 0 2006.190.07:31:12.43#ibcon#*before return 0, iclass 4, count 0 2006.190.07:31:12.43#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:12.43#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:31:12.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:31:12.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:31:12.43$vc4f8/vblo=6,752.99 2006.190.07:31:12.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:31:12.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:31:12.43#ibcon#ireg 17 cls_cnt 0 2006.190.07:31:12.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:12.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:12.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:12.43#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:31:12.43#ibcon#first serial, iclass 6, count 0 2006.190.07:31:12.43#ibcon#enter sib2, iclass 6, count 0 2006.190.07:31:12.43#ibcon#flushed, iclass 6, count 0 2006.190.07:31:12.43#ibcon#about to write, iclass 6, count 0 2006.190.07:31:12.43#ibcon#wrote, iclass 6, count 0 2006.190.07:31:12.43#ibcon#about to read 3, iclass 6, count 0 2006.190.07:31:12.45#ibcon#read 3, iclass 6, count 0 2006.190.07:31:12.45#ibcon#about to read 4, iclass 6, count 0 2006.190.07:31:12.45#ibcon#read 4, iclass 6, count 0 2006.190.07:31:12.45#ibcon#about to read 5, iclass 6, count 0 2006.190.07:31:12.45#ibcon#read 5, iclass 6, count 0 2006.190.07:31:12.45#ibcon#about to read 6, iclass 6, count 0 2006.190.07:31:12.45#ibcon#read 6, iclass 6, count 0 2006.190.07:31:12.45#ibcon#end of sib2, iclass 6, count 0 2006.190.07:31:12.45#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:31:12.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:31:12.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:31:12.45#ibcon#*before write, iclass 6, count 0 2006.190.07:31:12.45#ibcon#enter sib2, iclass 6, count 0 2006.190.07:31:12.45#ibcon#flushed, iclass 6, count 0 2006.190.07:31:12.45#ibcon#about to write, iclass 6, count 0 2006.190.07:31:12.45#ibcon#wrote, iclass 6, count 0 2006.190.07:31:12.45#ibcon#about to read 3, iclass 6, count 0 2006.190.07:31:12.49#ibcon#read 3, iclass 6, count 0 2006.190.07:31:12.49#ibcon#about to read 4, iclass 6, count 0 2006.190.07:31:12.49#ibcon#read 4, iclass 6, count 0 2006.190.07:31:12.49#ibcon#about to read 5, iclass 6, count 0 2006.190.07:31:12.49#ibcon#read 5, iclass 6, count 0 2006.190.07:31:12.49#ibcon#about to read 6, iclass 6, count 0 2006.190.07:31:12.49#ibcon#read 6, iclass 6, count 0 2006.190.07:31:12.49#ibcon#end of sib2, iclass 6, count 0 2006.190.07:31:12.49#ibcon#*after write, iclass 6, count 0 2006.190.07:31:12.49#ibcon#*before return 0, iclass 6, count 0 2006.190.07:31:12.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:12.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:31:12.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:31:12.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:31:12.49$vc4f8/vb=6,4 2006.190.07:31:12.49#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:31:12.49#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:31:12.49#ibcon#ireg 11 cls_cnt 2 2006.190.07:31:12.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:12.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:12.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:12.55#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:31:12.55#ibcon#first serial, iclass 10, count 2 2006.190.07:31:12.55#ibcon#enter sib2, iclass 10, count 2 2006.190.07:31:12.55#ibcon#flushed, iclass 10, count 2 2006.190.07:31:12.55#ibcon#about to write, iclass 10, count 2 2006.190.07:31:12.55#ibcon#wrote, iclass 10, count 2 2006.190.07:31:12.55#ibcon#about to read 3, iclass 10, count 2 2006.190.07:31:12.57#ibcon#read 3, iclass 10, count 2 2006.190.07:31:12.57#ibcon#about to read 4, iclass 10, count 2 2006.190.07:31:12.57#ibcon#read 4, iclass 10, count 2 2006.190.07:31:12.57#ibcon#about to read 5, iclass 10, count 2 2006.190.07:31:12.57#ibcon#read 5, iclass 10, count 2 2006.190.07:31:12.57#ibcon#about to read 6, iclass 10, count 2 2006.190.07:31:12.57#ibcon#read 6, iclass 10, count 2 2006.190.07:31:12.57#ibcon#end of sib2, iclass 10, count 2 2006.190.07:31:12.57#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:31:12.57#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:31:12.57#ibcon#[27=AT06-04\r\n] 2006.190.07:31:12.57#ibcon#*before write, iclass 10, count 2 2006.190.07:31:12.57#ibcon#enter sib2, iclass 10, count 2 2006.190.07:31:12.57#ibcon#flushed, iclass 10, count 2 2006.190.07:31:12.57#ibcon#about to write, iclass 10, count 2 2006.190.07:31:12.57#ibcon#wrote, iclass 10, count 2 2006.190.07:31:12.57#ibcon#about to read 3, iclass 10, count 2 2006.190.07:31:12.60#ibcon#read 3, iclass 10, count 2 2006.190.07:31:12.60#ibcon#about to read 4, iclass 10, count 2 2006.190.07:31:12.60#ibcon#read 4, iclass 10, count 2 2006.190.07:31:12.60#ibcon#about to read 5, iclass 10, count 2 2006.190.07:31:12.60#ibcon#read 5, iclass 10, count 2 2006.190.07:31:12.60#ibcon#about to read 6, iclass 10, count 2 2006.190.07:31:12.60#ibcon#read 6, iclass 10, count 2 2006.190.07:31:12.60#ibcon#end of sib2, iclass 10, count 2 2006.190.07:31:12.60#ibcon#*after write, iclass 10, count 2 2006.190.07:31:12.60#ibcon#*before return 0, iclass 10, count 2 2006.190.07:31:12.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:12.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:31:12.60#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:31:12.60#ibcon#ireg 7 cls_cnt 0 2006.190.07:31:12.60#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:12.72#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:12.72#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:12.72#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:31:12.72#ibcon#first serial, iclass 10, count 0 2006.190.07:31:12.72#ibcon#enter sib2, iclass 10, count 0 2006.190.07:31:12.72#ibcon#flushed, iclass 10, count 0 2006.190.07:31:12.72#ibcon#about to write, iclass 10, count 0 2006.190.07:31:12.72#ibcon#wrote, iclass 10, count 0 2006.190.07:31:12.72#ibcon#about to read 3, iclass 10, count 0 2006.190.07:31:12.74#ibcon#read 3, iclass 10, count 0 2006.190.07:31:12.74#ibcon#about to read 4, iclass 10, count 0 2006.190.07:31:12.74#ibcon#read 4, iclass 10, count 0 2006.190.07:31:12.74#ibcon#about to read 5, iclass 10, count 0 2006.190.07:31:12.74#ibcon#read 5, iclass 10, count 0 2006.190.07:31:12.74#ibcon#about to read 6, iclass 10, count 0 2006.190.07:31:12.74#ibcon#read 6, iclass 10, count 0 2006.190.07:31:12.74#ibcon#end of sib2, iclass 10, count 0 2006.190.07:31:12.74#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:31:12.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:31:12.74#ibcon#[27=USB\r\n] 2006.190.07:31:12.74#ibcon#*before write, iclass 10, count 0 2006.190.07:31:12.74#ibcon#enter sib2, iclass 10, count 0 2006.190.07:31:12.74#ibcon#flushed, iclass 10, count 0 2006.190.07:31:12.74#ibcon#about to write, iclass 10, count 0 2006.190.07:31:12.74#ibcon#wrote, iclass 10, count 0 2006.190.07:31:12.74#ibcon#about to read 3, iclass 10, count 0 2006.190.07:31:12.77#ibcon#read 3, iclass 10, count 0 2006.190.07:31:12.77#ibcon#about to read 4, iclass 10, count 0 2006.190.07:31:12.77#ibcon#read 4, iclass 10, count 0 2006.190.07:31:12.77#ibcon#about to read 5, iclass 10, count 0 2006.190.07:31:12.77#ibcon#read 5, iclass 10, count 0 2006.190.07:31:12.77#ibcon#about to read 6, iclass 10, count 0 2006.190.07:31:12.77#ibcon#read 6, iclass 10, count 0 2006.190.07:31:12.77#ibcon#end of sib2, iclass 10, count 0 2006.190.07:31:12.77#ibcon#*after write, iclass 10, count 0 2006.190.07:31:12.77#ibcon#*before return 0, iclass 10, count 0 2006.190.07:31:12.77#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:12.77#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:31:12.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:31:12.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:31:12.77$vc4f8/vabw=wide 2006.190.07:31:12.77#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:31:12.77#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:31:12.77#ibcon#ireg 8 cls_cnt 0 2006.190.07:31:12.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:12.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:12.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:12.77#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:31:12.77#ibcon#first serial, iclass 12, count 0 2006.190.07:31:12.77#ibcon#enter sib2, iclass 12, count 0 2006.190.07:31:12.77#ibcon#flushed, iclass 12, count 0 2006.190.07:31:12.77#ibcon#about to write, iclass 12, count 0 2006.190.07:31:12.77#ibcon#wrote, iclass 12, count 0 2006.190.07:31:12.77#ibcon#about to read 3, iclass 12, count 0 2006.190.07:31:12.79#ibcon#read 3, iclass 12, count 0 2006.190.07:31:12.79#ibcon#about to read 4, iclass 12, count 0 2006.190.07:31:12.79#ibcon#read 4, iclass 12, count 0 2006.190.07:31:12.79#ibcon#about to read 5, iclass 12, count 0 2006.190.07:31:12.79#ibcon#read 5, iclass 12, count 0 2006.190.07:31:12.79#ibcon#about to read 6, iclass 12, count 0 2006.190.07:31:12.79#ibcon#read 6, iclass 12, count 0 2006.190.07:31:12.79#ibcon#end of sib2, iclass 12, count 0 2006.190.07:31:12.79#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:31:12.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:31:12.79#ibcon#[25=BW32\r\n] 2006.190.07:31:12.79#ibcon#*before write, iclass 12, count 0 2006.190.07:31:12.79#ibcon#enter sib2, iclass 12, count 0 2006.190.07:31:12.79#ibcon#flushed, iclass 12, count 0 2006.190.07:31:12.79#ibcon#about to write, iclass 12, count 0 2006.190.07:31:12.79#ibcon#wrote, iclass 12, count 0 2006.190.07:31:12.79#ibcon#about to read 3, iclass 12, count 0 2006.190.07:31:12.82#ibcon#read 3, iclass 12, count 0 2006.190.07:31:12.82#ibcon#about to read 4, iclass 12, count 0 2006.190.07:31:12.82#ibcon#read 4, iclass 12, count 0 2006.190.07:31:12.82#ibcon#about to read 5, iclass 12, count 0 2006.190.07:31:12.82#ibcon#read 5, iclass 12, count 0 2006.190.07:31:12.82#ibcon#about to read 6, iclass 12, count 0 2006.190.07:31:12.82#ibcon#read 6, iclass 12, count 0 2006.190.07:31:12.82#ibcon#end of sib2, iclass 12, count 0 2006.190.07:31:12.82#ibcon#*after write, iclass 12, count 0 2006.190.07:31:12.82#ibcon#*before return 0, iclass 12, count 0 2006.190.07:31:12.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:12.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:31:12.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:31:12.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:31:12.82$vc4f8/vbbw=wide 2006.190.07:31:12.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.07:31:12.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.07:31:12.82#ibcon#ireg 8 cls_cnt 0 2006.190.07:31:12.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:31:12.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:31:12.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:31:12.89#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:31:12.89#ibcon#first serial, iclass 14, count 0 2006.190.07:31:12.89#ibcon#enter sib2, iclass 14, count 0 2006.190.07:31:12.89#ibcon#flushed, iclass 14, count 0 2006.190.07:31:12.89#ibcon#about to write, iclass 14, count 0 2006.190.07:31:12.89#ibcon#wrote, iclass 14, count 0 2006.190.07:31:12.89#ibcon#about to read 3, iclass 14, count 0 2006.190.07:31:12.91#ibcon#read 3, iclass 14, count 0 2006.190.07:31:12.91#ibcon#about to read 4, iclass 14, count 0 2006.190.07:31:12.91#ibcon#read 4, iclass 14, count 0 2006.190.07:31:12.91#ibcon#about to read 5, iclass 14, count 0 2006.190.07:31:12.91#ibcon#read 5, iclass 14, count 0 2006.190.07:31:12.91#ibcon#about to read 6, iclass 14, count 0 2006.190.07:31:12.91#ibcon#read 6, iclass 14, count 0 2006.190.07:31:12.91#ibcon#end of sib2, iclass 14, count 0 2006.190.07:31:12.91#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:31:12.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:31:12.91#ibcon#[27=BW32\r\n] 2006.190.07:31:12.91#ibcon#*before write, iclass 14, count 0 2006.190.07:31:12.91#ibcon#enter sib2, iclass 14, count 0 2006.190.07:31:12.91#ibcon#flushed, iclass 14, count 0 2006.190.07:31:12.91#ibcon#about to write, iclass 14, count 0 2006.190.07:31:12.91#ibcon#wrote, iclass 14, count 0 2006.190.07:31:12.91#ibcon#about to read 3, iclass 14, count 0 2006.190.07:31:12.94#ibcon#read 3, iclass 14, count 0 2006.190.07:31:12.94#ibcon#about to read 4, iclass 14, count 0 2006.190.07:31:12.94#ibcon#read 4, iclass 14, count 0 2006.190.07:31:12.94#ibcon#about to read 5, iclass 14, count 0 2006.190.07:31:12.94#ibcon#read 5, iclass 14, count 0 2006.190.07:31:12.94#ibcon#about to read 6, iclass 14, count 0 2006.190.07:31:12.94#ibcon#read 6, iclass 14, count 0 2006.190.07:31:12.94#ibcon#end of sib2, iclass 14, count 0 2006.190.07:31:12.94#ibcon#*after write, iclass 14, count 0 2006.190.07:31:12.94#ibcon#*before return 0, iclass 14, count 0 2006.190.07:31:12.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:31:12.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:31:12.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:31:12.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:31:12.94$4f8m12a/ifd4f 2006.190.07:31:12.94$ifd4f/lo= 2006.190.07:31:12.94$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:31:12.94$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:31:12.94$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:31:12.94$ifd4f/patch= 2006.190.07:31:12.94$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:31:12.94$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:31:12.94$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:31:12.94$4f8m12a/"form=m,16.000,1:2 2006.190.07:31:12.94$4f8m12a/"tpicd 2006.190.07:31:12.94$4f8m12a/echo=off 2006.190.07:31:12.94$4f8m12a/xlog=off 2006.190.07:31:12.94:!2006.190.07:33:20 2006.190.07:31:54.14#trakl#Source acquired 2006.190.07:31:54.14#flagr#flagr/antenna,acquired 2006.190.07:33:20.00:preob 2006.190.07:33:20.14/onsource/TRACKING 2006.190.07:33:20.14:!2006.190.07:33:30 2006.190.07:33:30.00:data_valid=on 2006.190.07:33:30.00:midob 2006.190.07:33:30.14/onsource/TRACKING 2006.190.07:33:30.14/wx/24.58,1012.3,100 2006.190.07:33:30.21/cable/+6.4705E-03 2006.190.07:33:31.30/va/01,08,usb,yes,43,46 2006.190.07:33:31.30/va/02,07,usb,yes,44,46 2006.190.07:33:31.30/va/03,06,usb,yes,46,47 2006.190.07:33:31.30/va/04,07,usb,yes,45,49 2006.190.07:33:31.30/va/05,07,usb,yes,50,53 2006.190.07:33:31.30/va/06,06,usb,yes,49,49 2006.190.07:33:31.30/va/07,06,usb,yes,50,49 2006.190.07:33:31.30/va/08,06,usb,yes,53,52 2006.190.07:33:31.53/valo/01,532.99,yes,locked 2006.190.07:33:31.53/valo/02,572.99,yes,locked 2006.190.07:33:31.53/valo/03,672.99,yes,locked 2006.190.07:33:31.53/valo/04,832.99,yes,locked 2006.190.07:33:31.53/valo/05,652.99,yes,locked 2006.190.07:33:31.53/valo/06,772.99,yes,locked 2006.190.07:33:31.53/valo/07,832.99,yes,locked 2006.190.07:33:31.53/valo/08,852.99,yes,locked 2006.190.07:33:32.62/vb/01,04,usb,yes,32,31 2006.190.07:33:32.62/vb/02,04,usb,yes,34,36 2006.190.07:33:32.62/vb/03,04,usb,yes,30,34 2006.190.07:33:32.62/vb/04,04,usb,yes,31,31 2006.190.07:33:32.62/vb/05,04,usb,yes,30,34 2006.190.07:33:32.62/vb/06,04,usb,yes,31,34 2006.190.07:33:32.62/vb/07,04,usb,yes,33,33 2006.190.07:33:32.62/vb/08,04,usb,yes,30,34 2006.190.07:33:32.85/vblo/01,632.99,yes,locked 2006.190.07:33:32.85/vblo/02,640.99,yes,locked 2006.190.07:33:32.85/vblo/03,656.99,yes,locked 2006.190.07:33:32.85/vblo/04,712.99,yes,locked 2006.190.07:33:32.85/vblo/05,744.99,yes,locked 2006.190.07:33:32.85/vblo/06,752.99,yes,locked 2006.190.07:33:32.85/vblo/07,734.99,yes,locked 2006.190.07:33:32.85/vblo/08,744.99,yes,locked 2006.190.07:33:33.00/vabw/8 2006.190.07:33:33.15/vbbw/8 2006.190.07:33:33.25/xfe/off,on,14.5 2006.190.07:33:33.62/ifatt/23,28,28,28 2006.190.07:33:34.08/fmout-gps/S +2.81E-07 2006.190.07:33:34.17:!2006.190.07:34:30 2006.190.07:34:30.01:data_valid=off 2006.190.07:34:30.02:postob 2006.190.07:34:30.10/cable/+6.4711E-03 2006.190.07:34:30.11/wx/24.56,1012.3,100 2006.190.07:34:31.08/fmout-gps/S +2.81E-07 2006.190.07:34:31.09:scan_name=190-0735,k06190,60 2006.190.07:34:31.09:source=oj287,085448.87,200630.6,2000.0,ccw 2006.190.07:34:31.14#flagr#flagr/antenna,new-source 2006.190.07:34:32.14:checkk5 2006.190.07:34:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:34:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:34:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:34:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:34:34.05/chk_obsdata//k5ts1/T1900733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:34:34.42/chk_obsdata//k5ts2/T1900733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:34:34.80/chk_obsdata//k5ts3/T1900733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:34:35.17/chk_obsdata//k5ts4/T1900733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:34:35.87/k5log//k5ts1_log_newline 2006.190.07:34:36.58/k5log//k5ts2_log_newline 2006.190.07:34:37.28/k5log//k5ts3_log_newline 2006.190.07:34:37.97/k5log//k5ts4_log_newline 2006.190.07:34:38.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:34:38.00:4f8m12a=1 2006.190.07:34:38.00$4f8m12a/echo=on 2006.190.07:34:38.00$4f8m12a/pcalon 2006.190.07:34:38.00$pcalon/"no phase cal control is implemented here 2006.190.07:34:38.00$4f8m12a/"tpicd=stop 2006.190.07:34:38.00$4f8m12a/vc4f8 2006.190.07:34:38.00$vc4f8/valo=1,532.99 2006.190.07:34:38.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.07:34:38.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.07:34:38.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:38.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:38.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:38.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:38.00#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:34:38.00#ibcon#first serial, iclass 25, count 0 2006.190.07:34:38.00#ibcon#enter sib2, iclass 25, count 0 2006.190.07:34:38.00#ibcon#flushed, iclass 25, count 0 2006.190.07:34:38.00#ibcon#about to write, iclass 25, count 0 2006.190.07:34:38.00#ibcon#wrote, iclass 25, count 0 2006.190.07:34:38.00#ibcon#about to read 3, iclass 25, count 0 2006.190.07:34:38.05#ibcon#read 3, iclass 25, count 0 2006.190.07:34:38.05#ibcon#about to read 4, iclass 25, count 0 2006.190.07:34:38.05#ibcon#read 4, iclass 25, count 0 2006.190.07:34:38.05#ibcon#about to read 5, iclass 25, count 0 2006.190.07:34:38.05#ibcon#read 5, iclass 25, count 0 2006.190.07:34:38.05#ibcon#about to read 6, iclass 25, count 0 2006.190.07:34:38.05#ibcon#read 6, iclass 25, count 0 2006.190.07:34:38.05#ibcon#end of sib2, iclass 25, count 0 2006.190.07:34:38.05#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:34:38.05#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:34:38.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:34:38.05#ibcon#*before write, iclass 25, count 0 2006.190.07:34:38.05#ibcon#enter sib2, iclass 25, count 0 2006.190.07:34:38.05#ibcon#flushed, iclass 25, count 0 2006.190.07:34:38.05#ibcon#about to write, iclass 25, count 0 2006.190.07:34:38.05#ibcon#wrote, iclass 25, count 0 2006.190.07:34:38.05#ibcon#about to read 3, iclass 25, count 0 2006.190.07:34:38.10#ibcon#read 3, iclass 25, count 0 2006.190.07:34:38.10#ibcon#about to read 4, iclass 25, count 0 2006.190.07:34:38.10#ibcon#read 4, iclass 25, count 0 2006.190.07:34:38.10#ibcon#about to read 5, iclass 25, count 0 2006.190.07:34:38.10#ibcon#read 5, iclass 25, count 0 2006.190.07:34:38.10#ibcon#about to read 6, iclass 25, count 0 2006.190.07:34:38.10#ibcon#read 6, iclass 25, count 0 2006.190.07:34:38.10#ibcon#end of sib2, iclass 25, count 0 2006.190.07:34:38.10#ibcon#*after write, iclass 25, count 0 2006.190.07:34:38.10#ibcon#*before return 0, iclass 25, count 0 2006.190.07:34:38.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:38.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:38.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:34:38.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:34:38.10$vc4f8/va=1,8 2006.190.07:34:38.10#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.07:34:38.10#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.07:34:38.10#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:38.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:38.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:38.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:38.10#ibcon#enter wrdev, iclass 27, count 2 2006.190.07:34:38.10#ibcon#first serial, iclass 27, count 2 2006.190.07:34:38.10#ibcon#enter sib2, iclass 27, count 2 2006.190.07:34:38.10#ibcon#flushed, iclass 27, count 2 2006.190.07:34:38.10#ibcon#about to write, iclass 27, count 2 2006.190.07:34:38.10#ibcon#wrote, iclass 27, count 2 2006.190.07:34:38.10#ibcon#about to read 3, iclass 27, count 2 2006.190.07:34:38.12#ibcon#read 3, iclass 27, count 2 2006.190.07:34:38.12#ibcon#about to read 4, iclass 27, count 2 2006.190.07:34:38.12#ibcon#read 4, iclass 27, count 2 2006.190.07:34:38.12#ibcon#about to read 5, iclass 27, count 2 2006.190.07:34:38.12#ibcon#read 5, iclass 27, count 2 2006.190.07:34:38.12#ibcon#about to read 6, iclass 27, count 2 2006.190.07:34:38.12#ibcon#read 6, iclass 27, count 2 2006.190.07:34:38.12#ibcon#end of sib2, iclass 27, count 2 2006.190.07:34:38.12#ibcon#*mode == 0, iclass 27, count 2 2006.190.07:34:38.12#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.07:34:38.12#ibcon#[25=AT01-08\r\n] 2006.190.07:34:38.12#ibcon#*before write, iclass 27, count 2 2006.190.07:34:38.12#ibcon#enter sib2, iclass 27, count 2 2006.190.07:34:38.12#ibcon#flushed, iclass 27, count 2 2006.190.07:34:38.12#ibcon#about to write, iclass 27, count 2 2006.190.07:34:38.12#ibcon#wrote, iclass 27, count 2 2006.190.07:34:38.12#ibcon#about to read 3, iclass 27, count 2 2006.190.07:34:38.15#ibcon#read 3, iclass 27, count 2 2006.190.07:34:38.15#ibcon#about to read 4, iclass 27, count 2 2006.190.07:34:38.15#ibcon#read 4, iclass 27, count 2 2006.190.07:34:38.15#ibcon#about to read 5, iclass 27, count 2 2006.190.07:34:38.15#ibcon#read 5, iclass 27, count 2 2006.190.07:34:38.15#ibcon#about to read 6, iclass 27, count 2 2006.190.07:34:38.15#ibcon#read 6, iclass 27, count 2 2006.190.07:34:38.15#ibcon#end of sib2, iclass 27, count 2 2006.190.07:34:38.15#ibcon#*after write, iclass 27, count 2 2006.190.07:34:38.15#ibcon#*before return 0, iclass 27, count 2 2006.190.07:34:38.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:38.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:38.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.07:34:38.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:38.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:38.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:38.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:38.27#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:34:38.27#ibcon#first serial, iclass 27, count 0 2006.190.07:34:38.27#ibcon#enter sib2, iclass 27, count 0 2006.190.07:34:38.27#ibcon#flushed, iclass 27, count 0 2006.190.07:34:38.27#ibcon#about to write, iclass 27, count 0 2006.190.07:34:38.27#ibcon#wrote, iclass 27, count 0 2006.190.07:34:38.27#ibcon#about to read 3, iclass 27, count 0 2006.190.07:34:38.29#ibcon#read 3, iclass 27, count 0 2006.190.07:34:38.29#ibcon#about to read 4, iclass 27, count 0 2006.190.07:34:38.29#ibcon#read 4, iclass 27, count 0 2006.190.07:34:38.29#ibcon#about to read 5, iclass 27, count 0 2006.190.07:34:38.29#ibcon#read 5, iclass 27, count 0 2006.190.07:34:38.29#ibcon#about to read 6, iclass 27, count 0 2006.190.07:34:38.29#ibcon#read 6, iclass 27, count 0 2006.190.07:34:38.29#ibcon#end of sib2, iclass 27, count 0 2006.190.07:34:38.29#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:34:38.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:34:38.29#ibcon#[25=USB\r\n] 2006.190.07:34:38.29#ibcon#*before write, iclass 27, count 0 2006.190.07:34:38.29#ibcon#enter sib2, iclass 27, count 0 2006.190.07:34:38.29#ibcon#flushed, iclass 27, count 0 2006.190.07:34:38.29#ibcon#about to write, iclass 27, count 0 2006.190.07:34:38.29#ibcon#wrote, iclass 27, count 0 2006.190.07:34:38.29#ibcon#about to read 3, iclass 27, count 0 2006.190.07:34:38.32#ibcon#read 3, iclass 27, count 0 2006.190.07:34:38.32#ibcon#about to read 4, iclass 27, count 0 2006.190.07:34:38.32#ibcon#read 4, iclass 27, count 0 2006.190.07:34:38.32#ibcon#about to read 5, iclass 27, count 0 2006.190.07:34:38.32#ibcon#read 5, iclass 27, count 0 2006.190.07:34:38.32#ibcon#about to read 6, iclass 27, count 0 2006.190.07:34:38.32#ibcon#read 6, iclass 27, count 0 2006.190.07:34:38.32#ibcon#end of sib2, iclass 27, count 0 2006.190.07:34:38.32#ibcon#*after write, iclass 27, count 0 2006.190.07:34:38.32#ibcon#*before return 0, iclass 27, count 0 2006.190.07:34:38.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:38.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:38.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:34:38.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:34:38.32$vc4f8/valo=2,572.99 2006.190.07:34:38.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.07:34:38.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.07:34:38.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:38.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:38.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:38.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:38.32#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:34:38.32#ibcon#first serial, iclass 29, count 0 2006.190.07:34:38.32#ibcon#enter sib2, iclass 29, count 0 2006.190.07:34:38.32#ibcon#flushed, iclass 29, count 0 2006.190.07:34:38.32#ibcon#about to write, iclass 29, count 0 2006.190.07:34:38.32#ibcon#wrote, iclass 29, count 0 2006.190.07:34:38.32#ibcon#about to read 3, iclass 29, count 0 2006.190.07:34:38.34#ibcon#read 3, iclass 29, count 0 2006.190.07:34:38.34#ibcon#about to read 4, iclass 29, count 0 2006.190.07:34:38.34#ibcon#read 4, iclass 29, count 0 2006.190.07:34:38.34#ibcon#about to read 5, iclass 29, count 0 2006.190.07:34:38.34#ibcon#read 5, iclass 29, count 0 2006.190.07:34:38.34#ibcon#about to read 6, iclass 29, count 0 2006.190.07:34:38.34#ibcon#read 6, iclass 29, count 0 2006.190.07:34:38.34#ibcon#end of sib2, iclass 29, count 0 2006.190.07:34:38.34#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:34:38.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:34:38.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:34:38.34#ibcon#*before write, iclass 29, count 0 2006.190.07:34:38.34#ibcon#enter sib2, iclass 29, count 0 2006.190.07:34:38.34#ibcon#flushed, iclass 29, count 0 2006.190.07:34:38.34#ibcon#about to write, iclass 29, count 0 2006.190.07:34:38.34#ibcon#wrote, iclass 29, count 0 2006.190.07:34:38.34#ibcon#about to read 3, iclass 29, count 0 2006.190.07:34:38.38#ibcon#read 3, iclass 29, count 0 2006.190.07:34:38.38#ibcon#about to read 4, iclass 29, count 0 2006.190.07:34:38.38#ibcon#read 4, iclass 29, count 0 2006.190.07:34:38.38#ibcon#about to read 5, iclass 29, count 0 2006.190.07:34:38.38#ibcon#read 5, iclass 29, count 0 2006.190.07:34:38.38#ibcon#about to read 6, iclass 29, count 0 2006.190.07:34:38.38#ibcon#read 6, iclass 29, count 0 2006.190.07:34:38.38#ibcon#end of sib2, iclass 29, count 0 2006.190.07:34:38.38#ibcon#*after write, iclass 29, count 0 2006.190.07:34:38.38#ibcon#*before return 0, iclass 29, count 0 2006.190.07:34:38.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:38.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:38.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:34:38.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:34:38.38$vc4f8/va=2,7 2006.190.07:34:38.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.07:34:38.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.07:34:38.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:38.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:38.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:38.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:38.44#ibcon#enter wrdev, iclass 31, count 2 2006.190.07:34:38.44#ibcon#first serial, iclass 31, count 2 2006.190.07:34:38.44#ibcon#enter sib2, iclass 31, count 2 2006.190.07:34:38.44#ibcon#flushed, iclass 31, count 2 2006.190.07:34:38.44#ibcon#about to write, iclass 31, count 2 2006.190.07:34:38.44#ibcon#wrote, iclass 31, count 2 2006.190.07:34:38.44#ibcon#about to read 3, iclass 31, count 2 2006.190.07:34:38.46#ibcon#read 3, iclass 31, count 2 2006.190.07:34:38.46#ibcon#about to read 4, iclass 31, count 2 2006.190.07:34:38.46#ibcon#read 4, iclass 31, count 2 2006.190.07:34:38.46#ibcon#about to read 5, iclass 31, count 2 2006.190.07:34:38.46#ibcon#read 5, iclass 31, count 2 2006.190.07:34:38.46#ibcon#about to read 6, iclass 31, count 2 2006.190.07:34:38.46#ibcon#read 6, iclass 31, count 2 2006.190.07:34:38.46#ibcon#end of sib2, iclass 31, count 2 2006.190.07:34:38.46#ibcon#*mode == 0, iclass 31, count 2 2006.190.07:34:38.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.07:34:38.46#ibcon#[25=AT02-07\r\n] 2006.190.07:34:38.46#ibcon#*before write, iclass 31, count 2 2006.190.07:34:38.46#ibcon#enter sib2, iclass 31, count 2 2006.190.07:34:38.46#ibcon#flushed, iclass 31, count 2 2006.190.07:34:38.46#ibcon#about to write, iclass 31, count 2 2006.190.07:34:38.46#ibcon#wrote, iclass 31, count 2 2006.190.07:34:38.46#ibcon#about to read 3, iclass 31, count 2 2006.190.07:34:38.49#ibcon#read 3, iclass 31, count 2 2006.190.07:34:38.49#ibcon#about to read 4, iclass 31, count 2 2006.190.07:34:38.49#ibcon#read 4, iclass 31, count 2 2006.190.07:34:38.49#ibcon#about to read 5, iclass 31, count 2 2006.190.07:34:38.49#ibcon#read 5, iclass 31, count 2 2006.190.07:34:38.49#ibcon#about to read 6, iclass 31, count 2 2006.190.07:34:38.49#ibcon#read 6, iclass 31, count 2 2006.190.07:34:38.49#ibcon#end of sib2, iclass 31, count 2 2006.190.07:34:38.49#ibcon#*after write, iclass 31, count 2 2006.190.07:34:38.49#ibcon#*before return 0, iclass 31, count 2 2006.190.07:34:38.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:38.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:38.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.07:34:38.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:38.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:38.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:38.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:38.61#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:34:38.61#ibcon#first serial, iclass 31, count 0 2006.190.07:34:38.61#ibcon#enter sib2, iclass 31, count 0 2006.190.07:34:38.61#ibcon#flushed, iclass 31, count 0 2006.190.07:34:38.61#ibcon#about to write, iclass 31, count 0 2006.190.07:34:38.61#ibcon#wrote, iclass 31, count 0 2006.190.07:34:38.61#ibcon#about to read 3, iclass 31, count 0 2006.190.07:34:38.63#ibcon#read 3, iclass 31, count 0 2006.190.07:34:38.63#ibcon#about to read 4, iclass 31, count 0 2006.190.07:34:38.63#ibcon#read 4, iclass 31, count 0 2006.190.07:34:38.63#ibcon#about to read 5, iclass 31, count 0 2006.190.07:34:38.63#ibcon#read 5, iclass 31, count 0 2006.190.07:34:38.63#ibcon#about to read 6, iclass 31, count 0 2006.190.07:34:38.63#ibcon#read 6, iclass 31, count 0 2006.190.07:34:38.63#ibcon#end of sib2, iclass 31, count 0 2006.190.07:34:38.63#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:34:38.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:34:38.63#ibcon#[25=USB\r\n] 2006.190.07:34:38.63#ibcon#*before write, iclass 31, count 0 2006.190.07:34:38.63#ibcon#enter sib2, iclass 31, count 0 2006.190.07:34:38.63#ibcon#flushed, iclass 31, count 0 2006.190.07:34:38.63#ibcon#about to write, iclass 31, count 0 2006.190.07:34:38.63#ibcon#wrote, iclass 31, count 0 2006.190.07:34:38.63#ibcon#about to read 3, iclass 31, count 0 2006.190.07:34:38.66#ibcon#read 3, iclass 31, count 0 2006.190.07:34:38.66#ibcon#about to read 4, iclass 31, count 0 2006.190.07:34:38.66#ibcon#read 4, iclass 31, count 0 2006.190.07:34:38.66#ibcon#about to read 5, iclass 31, count 0 2006.190.07:34:38.66#ibcon#read 5, iclass 31, count 0 2006.190.07:34:38.66#ibcon#about to read 6, iclass 31, count 0 2006.190.07:34:38.66#ibcon#read 6, iclass 31, count 0 2006.190.07:34:38.66#ibcon#end of sib2, iclass 31, count 0 2006.190.07:34:38.66#ibcon#*after write, iclass 31, count 0 2006.190.07:34:38.66#ibcon#*before return 0, iclass 31, count 0 2006.190.07:34:38.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:38.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:38.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:34:38.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:34:38.66$vc4f8/valo=3,672.99 2006.190.07:34:38.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.07:34:38.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.07:34:38.66#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:38.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:38.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:38.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:38.66#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:34:38.66#ibcon#first serial, iclass 33, count 0 2006.190.07:34:38.66#ibcon#enter sib2, iclass 33, count 0 2006.190.07:34:38.66#ibcon#flushed, iclass 33, count 0 2006.190.07:34:38.66#ibcon#about to write, iclass 33, count 0 2006.190.07:34:38.66#ibcon#wrote, iclass 33, count 0 2006.190.07:34:38.66#ibcon#about to read 3, iclass 33, count 0 2006.190.07:34:38.68#ibcon#read 3, iclass 33, count 0 2006.190.07:34:38.68#ibcon#about to read 4, iclass 33, count 0 2006.190.07:34:38.68#ibcon#read 4, iclass 33, count 0 2006.190.07:34:38.68#ibcon#about to read 5, iclass 33, count 0 2006.190.07:34:38.68#ibcon#read 5, iclass 33, count 0 2006.190.07:34:38.68#ibcon#about to read 6, iclass 33, count 0 2006.190.07:34:38.68#ibcon#read 6, iclass 33, count 0 2006.190.07:34:38.68#ibcon#end of sib2, iclass 33, count 0 2006.190.07:34:38.68#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:34:38.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:34:38.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:34:38.68#ibcon#*before write, iclass 33, count 0 2006.190.07:34:38.68#ibcon#enter sib2, iclass 33, count 0 2006.190.07:34:38.68#ibcon#flushed, iclass 33, count 0 2006.190.07:34:38.68#ibcon#about to write, iclass 33, count 0 2006.190.07:34:38.68#ibcon#wrote, iclass 33, count 0 2006.190.07:34:38.68#ibcon#about to read 3, iclass 33, count 0 2006.190.07:34:38.72#ibcon#read 3, iclass 33, count 0 2006.190.07:34:38.72#ibcon#about to read 4, iclass 33, count 0 2006.190.07:34:38.72#ibcon#read 4, iclass 33, count 0 2006.190.07:34:38.72#ibcon#about to read 5, iclass 33, count 0 2006.190.07:34:38.72#ibcon#read 5, iclass 33, count 0 2006.190.07:34:38.72#ibcon#about to read 6, iclass 33, count 0 2006.190.07:34:38.72#ibcon#read 6, iclass 33, count 0 2006.190.07:34:38.72#ibcon#end of sib2, iclass 33, count 0 2006.190.07:34:38.72#ibcon#*after write, iclass 33, count 0 2006.190.07:34:38.72#ibcon#*before return 0, iclass 33, count 0 2006.190.07:34:38.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:38.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:38.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:34:38.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:34:38.72$vc4f8/va=3,6 2006.190.07:34:38.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.07:34:38.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.07:34:38.72#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:38.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:38.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:38.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:38.78#ibcon#enter wrdev, iclass 35, count 2 2006.190.07:34:38.78#ibcon#first serial, iclass 35, count 2 2006.190.07:34:38.78#ibcon#enter sib2, iclass 35, count 2 2006.190.07:34:38.78#ibcon#flushed, iclass 35, count 2 2006.190.07:34:38.78#ibcon#about to write, iclass 35, count 2 2006.190.07:34:38.78#ibcon#wrote, iclass 35, count 2 2006.190.07:34:38.78#ibcon#about to read 3, iclass 35, count 2 2006.190.07:34:38.80#ibcon#read 3, iclass 35, count 2 2006.190.07:34:38.80#ibcon#about to read 4, iclass 35, count 2 2006.190.07:34:38.80#ibcon#read 4, iclass 35, count 2 2006.190.07:34:38.80#ibcon#about to read 5, iclass 35, count 2 2006.190.07:34:38.80#ibcon#read 5, iclass 35, count 2 2006.190.07:34:38.80#ibcon#about to read 6, iclass 35, count 2 2006.190.07:34:38.80#ibcon#read 6, iclass 35, count 2 2006.190.07:34:38.80#ibcon#end of sib2, iclass 35, count 2 2006.190.07:34:38.80#ibcon#*mode == 0, iclass 35, count 2 2006.190.07:34:38.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.07:34:38.80#ibcon#[25=AT03-06\r\n] 2006.190.07:34:38.80#ibcon#*before write, iclass 35, count 2 2006.190.07:34:38.80#ibcon#enter sib2, iclass 35, count 2 2006.190.07:34:38.80#ibcon#flushed, iclass 35, count 2 2006.190.07:34:38.80#ibcon#about to write, iclass 35, count 2 2006.190.07:34:38.80#ibcon#wrote, iclass 35, count 2 2006.190.07:34:38.80#ibcon#about to read 3, iclass 35, count 2 2006.190.07:34:38.83#ibcon#read 3, iclass 35, count 2 2006.190.07:34:38.83#ibcon#about to read 4, iclass 35, count 2 2006.190.07:34:38.83#ibcon#read 4, iclass 35, count 2 2006.190.07:34:38.83#ibcon#about to read 5, iclass 35, count 2 2006.190.07:34:38.83#ibcon#read 5, iclass 35, count 2 2006.190.07:34:38.83#ibcon#about to read 6, iclass 35, count 2 2006.190.07:34:38.83#ibcon#read 6, iclass 35, count 2 2006.190.07:34:38.83#ibcon#end of sib2, iclass 35, count 2 2006.190.07:34:38.83#ibcon#*after write, iclass 35, count 2 2006.190.07:34:38.83#ibcon#*before return 0, iclass 35, count 2 2006.190.07:34:38.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:38.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:38.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.07:34:38.83#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:38.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:38.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:38.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:38.95#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:34:38.95#ibcon#first serial, iclass 35, count 0 2006.190.07:34:38.95#ibcon#enter sib2, iclass 35, count 0 2006.190.07:34:38.95#ibcon#flushed, iclass 35, count 0 2006.190.07:34:38.95#ibcon#about to write, iclass 35, count 0 2006.190.07:34:38.95#ibcon#wrote, iclass 35, count 0 2006.190.07:34:38.95#ibcon#about to read 3, iclass 35, count 0 2006.190.07:34:38.97#ibcon#read 3, iclass 35, count 0 2006.190.07:34:38.97#ibcon#about to read 4, iclass 35, count 0 2006.190.07:34:38.97#ibcon#read 4, iclass 35, count 0 2006.190.07:34:38.97#ibcon#about to read 5, iclass 35, count 0 2006.190.07:34:38.97#ibcon#read 5, iclass 35, count 0 2006.190.07:34:38.97#ibcon#about to read 6, iclass 35, count 0 2006.190.07:34:38.97#ibcon#read 6, iclass 35, count 0 2006.190.07:34:38.97#ibcon#end of sib2, iclass 35, count 0 2006.190.07:34:38.97#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:34:38.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:34:38.97#ibcon#[25=USB\r\n] 2006.190.07:34:38.97#ibcon#*before write, iclass 35, count 0 2006.190.07:34:38.97#ibcon#enter sib2, iclass 35, count 0 2006.190.07:34:38.97#ibcon#flushed, iclass 35, count 0 2006.190.07:34:38.97#ibcon#about to write, iclass 35, count 0 2006.190.07:34:38.97#ibcon#wrote, iclass 35, count 0 2006.190.07:34:38.97#ibcon#about to read 3, iclass 35, count 0 2006.190.07:34:39.00#ibcon#read 3, iclass 35, count 0 2006.190.07:34:39.00#ibcon#about to read 4, iclass 35, count 0 2006.190.07:34:39.00#ibcon#read 4, iclass 35, count 0 2006.190.07:34:39.00#ibcon#about to read 5, iclass 35, count 0 2006.190.07:34:39.00#ibcon#read 5, iclass 35, count 0 2006.190.07:34:39.00#ibcon#about to read 6, iclass 35, count 0 2006.190.07:34:39.00#ibcon#read 6, iclass 35, count 0 2006.190.07:34:39.00#ibcon#end of sib2, iclass 35, count 0 2006.190.07:34:39.00#ibcon#*after write, iclass 35, count 0 2006.190.07:34:39.00#ibcon#*before return 0, iclass 35, count 0 2006.190.07:34:39.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:39.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:39.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:34:39.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:34:39.00$vc4f8/valo=4,832.99 2006.190.07:34:39.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.07:34:39.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.07:34:39.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:39.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:39.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:39.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:39.00#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:34:39.00#ibcon#first serial, iclass 37, count 0 2006.190.07:34:39.00#ibcon#enter sib2, iclass 37, count 0 2006.190.07:34:39.00#ibcon#flushed, iclass 37, count 0 2006.190.07:34:39.00#ibcon#about to write, iclass 37, count 0 2006.190.07:34:39.00#ibcon#wrote, iclass 37, count 0 2006.190.07:34:39.00#ibcon#about to read 3, iclass 37, count 0 2006.190.07:34:39.02#ibcon#read 3, iclass 37, count 0 2006.190.07:34:39.02#ibcon#about to read 4, iclass 37, count 0 2006.190.07:34:39.02#ibcon#read 4, iclass 37, count 0 2006.190.07:34:39.02#ibcon#about to read 5, iclass 37, count 0 2006.190.07:34:39.02#ibcon#read 5, iclass 37, count 0 2006.190.07:34:39.02#ibcon#about to read 6, iclass 37, count 0 2006.190.07:34:39.02#ibcon#read 6, iclass 37, count 0 2006.190.07:34:39.02#ibcon#end of sib2, iclass 37, count 0 2006.190.07:34:39.02#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:34:39.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:34:39.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:34:39.02#ibcon#*before write, iclass 37, count 0 2006.190.07:34:39.02#ibcon#enter sib2, iclass 37, count 0 2006.190.07:34:39.02#ibcon#flushed, iclass 37, count 0 2006.190.07:34:39.02#ibcon#about to write, iclass 37, count 0 2006.190.07:34:39.02#ibcon#wrote, iclass 37, count 0 2006.190.07:34:39.02#ibcon#about to read 3, iclass 37, count 0 2006.190.07:34:39.06#ibcon#read 3, iclass 37, count 0 2006.190.07:34:39.06#ibcon#about to read 4, iclass 37, count 0 2006.190.07:34:39.06#ibcon#read 4, iclass 37, count 0 2006.190.07:34:39.06#ibcon#about to read 5, iclass 37, count 0 2006.190.07:34:39.06#ibcon#read 5, iclass 37, count 0 2006.190.07:34:39.06#ibcon#about to read 6, iclass 37, count 0 2006.190.07:34:39.06#ibcon#read 6, iclass 37, count 0 2006.190.07:34:39.06#ibcon#end of sib2, iclass 37, count 0 2006.190.07:34:39.06#ibcon#*after write, iclass 37, count 0 2006.190.07:34:39.06#ibcon#*before return 0, iclass 37, count 0 2006.190.07:34:39.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:39.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:39.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:34:39.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:34:39.06$vc4f8/va=4,7 2006.190.07:34:39.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.07:34:39.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.07:34:39.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:39.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:39.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:39.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:39.12#ibcon#enter wrdev, iclass 39, count 2 2006.190.07:34:39.12#ibcon#first serial, iclass 39, count 2 2006.190.07:34:39.12#ibcon#enter sib2, iclass 39, count 2 2006.190.07:34:39.12#ibcon#flushed, iclass 39, count 2 2006.190.07:34:39.12#ibcon#about to write, iclass 39, count 2 2006.190.07:34:39.12#ibcon#wrote, iclass 39, count 2 2006.190.07:34:39.12#ibcon#about to read 3, iclass 39, count 2 2006.190.07:34:39.14#ibcon#read 3, iclass 39, count 2 2006.190.07:34:39.14#ibcon#about to read 4, iclass 39, count 2 2006.190.07:34:39.14#ibcon#read 4, iclass 39, count 2 2006.190.07:34:39.14#ibcon#about to read 5, iclass 39, count 2 2006.190.07:34:39.14#ibcon#read 5, iclass 39, count 2 2006.190.07:34:39.14#ibcon#about to read 6, iclass 39, count 2 2006.190.07:34:39.14#ibcon#read 6, iclass 39, count 2 2006.190.07:34:39.14#ibcon#end of sib2, iclass 39, count 2 2006.190.07:34:39.14#ibcon#*mode == 0, iclass 39, count 2 2006.190.07:34:39.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.07:34:39.14#ibcon#[25=AT04-07\r\n] 2006.190.07:34:39.14#ibcon#*before write, iclass 39, count 2 2006.190.07:34:39.14#ibcon#enter sib2, iclass 39, count 2 2006.190.07:34:39.14#ibcon#flushed, iclass 39, count 2 2006.190.07:34:39.14#ibcon#about to write, iclass 39, count 2 2006.190.07:34:39.14#ibcon#wrote, iclass 39, count 2 2006.190.07:34:39.14#ibcon#about to read 3, iclass 39, count 2 2006.190.07:34:39.17#ibcon#read 3, iclass 39, count 2 2006.190.07:34:39.17#ibcon#about to read 4, iclass 39, count 2 2006.190.07:34:39.17#ibcon#read 4, iclass 39, count 2 2006.190.07:34:39.17#ibcon#about to read 5, iclass 39, count 2 2006.190.07:34:39.17#ibcon#read 5, iclass 39, count 2 2006.190.07:34:39.17#ibcon#about to read 6, iclass 39, count 2 2006.190.07:34:39.17#ibcon#read 6, iclass 39, count 2 2006.190.07:34:39.17#ibcon#end of sib2, iclass 39, count 2 2006.190.07:34:39.17#ibcon#*after write, iclass 39, count 2 2006.190.07:34:39.17#ibcon#*before return 0, iclass 39, count 2 2006.190.07:34:39.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:39.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:39.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.07:34:39.17#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:39.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:39.18#abcon#<5=/04 1.7 3.0 24.561001012.3\r\n> 2006.190.07:34:39.20#abcon#{5=INTERFACE CLEAR} 2006.190.07:34:39.26#abcon#[5=S1D000X0/0*\r\n] 2006.190.07:34:39.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:39.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:39.29#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:34:39.29#ibcon#first serial, iclass 39, count 0 2006.190.07:34:39.29#ibcon#enter sib2, iclass 39, count 0 2006.190.07:34:39.29#ibcon#flushed, iclass 39, count 0 2006.190.07:34:39.29#ibcon#about to write, iclass 39, count 0 2006.190.07:34:39.29#ibcon#wrote, iclass 39, count 0 2006.190.07:34:39.29#ibcon#about to read 3, iclass 39, count 0 2006.190.07:34:39.31#ibcon#read 3, iclass 39, count 0 2006.190.07:34:39.31#ibcon#about to read 4, iclass 39, count 0 2006.190.07:34:39.31#ibcon#read 4, iclass 39, count 0 2006.190.07:34:39.31#ibcon#about to read 5, iclass 39, count 0 2006.190.07:34:39.31#ibcon#read 5, iclass 39, count 0 2006.190.07:34:39.31#ibcon#about to read 6, iclass 39, count 0 2006.190.07:34:39.31#ibcon#read 6, iclass 39, count 0 2006.190.07:34:39.31#ibcon#end of sib2, iclass 39, count 0 2006.190.07:34:39.31#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:34:39.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:34:39.31#ibcon#[25=USB\r\n] 2006.190.07:34:39.31#ibcon#*before write, iclass 39, count 0 2006.190.07:34:39.31#ibcon#enter sib2, iclass 39, count 0 2006.190.07:34:39.31#ibcon#flushed, iclass 39, count 0 2006.190.07:34:39.31#ibcon#about to write, iclass 39, count 0 2006.190.07:34:39.31#ibcon#wrote, iclass 39, count 0 2006.190.07:34:39.31#ibcon#about to read 3, iclass 39, count 0 2006.190.07:34:39.34#ibcon#read 3, iclass 39, count 0 2006.190.07:34:39.34#ibcon#about to read 4, iclass 39, count 0 2006.190.07:34:39.34#ibcon#read 4, iclass 39, count 0 2006.190.07:34:39.34#ibcon#about to read 5, iclass 39, count 0 2006.190.07:34:39.34#ibcon#read 5, iclass 39, count 0 2006.190.07:34:39.34#ibcon#about to read 6, iclass 39, count 0 2006.190.07:34:39.34#ibcon#read 6, iclass 39, count 0 2006.190.07:34:39.34#ibcon#end of sib2, iclass 39, count 0 2006.190.07:34:39.34#ibcon#*after write, iclass 39, count 0 2006.190.07:34:39.34#ibcon#*before return 0, iclass 39, count 0 2006.190.07:34:39.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:39.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:39.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:34:39.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:34:39.34$vc4f8/valo=5,652.99 2006.190.07:34:39.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.07:34:39.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.07:34:39.34#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:39.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:39.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:39.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:39.34#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:34:39.34#ibcon#first serial, iclass 7, count 0 2006.190.07:34:39.34#ibcon#enter sib2, iclass 7, count 0 2006.190.07:34:39.34#ibcon#flushed, iclass 7, count 0 2006.190.07:34:39.34#ibcon#about to write, iclass 7, count 0 2006.190.07:34:39.34#ibcon#wrote, iclass 7, count 0 2006.190.07:34:39.34#ibcon#about to read 3, iclass 7, count 0 2006.190.07:34:39.36#ibcon#read 3, iclass 7, count 0 2006.190.07:34:39.36#ibcon#about to read 4, iclass 7, count 0 2006.190.07:34:39.36#ibcon#read 4, iclass 7, count 0 2006.190.07:34:39.36#ibcon#about to read 5, iclass 7, count 0 2006.190.07:34:39.36#ibcon#read 5, iclass 7, count 0 2006.190.07:34:39.36#ibcon#about to read 6, iclass 7, count 0 2006.190.07:34:39.36#ibcon#read 6, iclass 7, count 0 2006.190.07:34:39.36#ibcon#end of sib2, iclass 7, count 0 2006.190.07:34:39.36#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:34:39.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:34:39.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:34:39.36#ibcon#*before write, iclass 7, count 0 2006.190.07:34:39.36#ibcon#enter sib2, iclass 7, count 0 2006.190.07:34:39.36#ibcon#flushed, iclass 7, count 0 2006.190.07:34:39.36#ibcon#about to write, iclass 7, count 0 2006.190.07:34:39.36#ibcon#wrote, iclass 7, count 0 2006.190.07:34:39.36#ibcon#about to read 3, iclass 7, count 0 2006.190.07:34:39.40#ibcon#read 3, iclass 7, count 0 2006.190.07:34:39.40#ibcon#about to read 4, iclass 7, count 0 2006.190.07:34:39.40#ibcon#read 4, iclass 7, count 0 2006.190.07:34:39.40#ibcon#about to read 5, iclass 7, count 0 2006.190.07:34:39.40#ibcon#read 5, iclass 7, count 0 2006.190.07:34:39.40#ibcon#about to read 6, iclass 7, count 0 2006.190.07:34:39.40#ibcon#read 6, iclass 7, count 0 2006.190.07:34:39.40#ibcon#end of sib2, iclass 7, count 0 2006.190.07:34:39.40#ibcon#*after write, iclass 7, count 0 2006.190.07:34:39.40#ibcon#*before return 0, iclass 7, count 0 2006.190.07:34:39.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:39.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:39.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:34:39.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:34:39.40$vc4f8/va=5,7 2006.190.07:34:39.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.07:34:39.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.07:34:39.40#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:39.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:39.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:39.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:39.46#ibcon#enter wrdev, iclass 11, count 2 2006.190.07:34:39.46#ibcon#first serial, iclass 11, count 2 2006.190.07:34:39.46#ibcon#enter sib2, iclass 11, count 2 2006.190.07:34:39.46#ibcon#flushed, iclass 11, count 2 2006.190.07:34:39.46#ibcon#about to write, iclass 11, count 2 2006.190.07:34:39.46#ibcon#wrote, iclass 11, count 2 2006.190.07:34:39.46#ibcon#about to read 3, iclass 11, count 2 2006.190.07:34:39.48#ibcon#read 3, iclass 11, count 2 2006.190.07:34:39.48#ibcon#about to read 4, iclass 11, count 2 2006.190.07:34:39.48#ibcon#read 4, iclass 11, count 2 2006.190.07:34:39.48#ibcon#about to read 5, iclass 11, count 2 2006.190.07:34:39.48#ibcon#read 5, iclass 11, count 2 2006.190.07:34:39.48#ibcon#about to read 6, iclass 11, count 2 2006.190.07:34:39.48#ibcon#read 6, iclass 11, count 2 2006.190.07:34:39.48#ibcon#end of sib2, iclass 11, count 2 2006.190.07:34:39.48#ibcon#*mode == 0, iclass 11, count 2 2006.190.07:34:39.48#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.07:34:39.48#ibcon#[25=AT05-07\r\n] 2006.190.07:34:39.48#ibcon#*before write, iclass 11, count 2 2006.190.07:34:39.48#ibcon#enter sib2, iclass 11, count 2 2006.190.07:34:39.48#ibcon#flushed, iclass 11, count 2 2006.190.07:34:39.48#ibcon#about to write, iclass 11, count 2 2006.190.07:34:39.48#ibcon#wrote, iclass 11, count 2 2006.190.07:34:39.48#ibcon#about to read 3, iclass 11, count 2 2006.190.07:34:39.51#ibcon#read 3, iclass 11, count 2 2006.190.07:34:39.51#ibcon#about to read 4, iclass 11, count 2 2006.190.07:34:39.51#ibcon#read 4, iclass 11, count 2 2006.190.07:34:39.51#ibcon#about to read 5, iclass 11, count 2 2006.190.07:34:39.51#ibcon#read 5, iclass 11, count 2 2006.190.07:34:39.51#ibcon#about to read 6, iclass 11, count 2 2006.190.07:34:39.51#ibcon#read 6, iclass 11, count 2 2006.190.07:34:39.51#ibcon#end of sib2, iclass 11, count 2 2006.190.07:34:39.51#ibcon#*after write, iclass 11, count 2 2006.190.07:34:39.51#ibcon#*before return 0, iclass 11, count 2 2006.190.07:34:39.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:39.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:39.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.07:34:39.51#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:39.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:39.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:39.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:39.63#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:34:39.63#ibcon#first serial, iclass 11, count 0 2006.190.07:34:39.63#ibcon#enter sib2, iclass 11, count 0 2006.190.07:34:39.63#ibcon#flushed, iclass 11, count 0 2006.190.07:34:39.63#ibcon#about to write, iclass 11, count 0 2006.190.07:34:39.63#ibcon#wrote, iclass 11, count 0 2006.190.07:34:39.63#ibcon#about to read 3, iclass 11, count 0 2006.190.07:34:39.65#ibcon#read 3, iclass 11, count 0 2006.190.07:34:39.65#ibcon#about to read 4, iclass 11, count 0 2006.190.07:34:39.65#ibcon#read 4, iclass 11, count 0 2006.190.07:34:39.65#ibcon#about to read 5, iclass 11, count 0 2006.190.07:34:39.65#ibcon#read 5, iclass 11, count 0 2006.190.07:34:39.65#ibcon#about to read 6, iclass 11, count 0 2006.190.07:34:39.65#ibcon#read 6, iclass 11, count 0 2006.190.07:34:39.65#ibcon#end of sib2, iclass 11, count 0 2006.190.07:34:39.65#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:34:39.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:34:39.65#ibcon#[25=USB\r\n] 2006.190.07:34:39.65#ibcon#*before write, iclass 11, count 0 2006.190.07:34:39.65#ibcon#enter sib2, iclass 11, count 0 2006.190.07:34:39.65#ibcon#flushed, iclass 11, count 0 2006.190.07:34:39.65#ibcon#about to write, iclass 11, count 0 2006.190.07:34:39.65#ibcon#wrote, iclass 11, count 0 2006.190.07:34:39.65#ibcon#about to read 3, iclass 11, count 0 2006.190.07:34:39.68#ibcon#read 3, iclass 11, count 0 2006.190.07:34:39.68#ibcon#about to read 4, iclass 11, count 0 2006.190.07:34:39.68#ibcon#read 4, iclass 11, count 0 2006.190.07:34:39.68#ibcon#about to read 5, iclass 11, count 0 2006.190.07:34:39.68#ibcon#read 5, iclass 11, count 0 2006.190.07:34:39.68#ibcon#about to read 6, iclass 11, count 0 2006.190.07:34:39.68#ibcon#read 6, iclass 11, count 0 2006.190.07:34:39.68#ibcon#end of sib2, iclass 11, count 0 2006.190.07:34:39.68#ibcon#*after write, iclass 11, count 0 2006.190.07:34:39.68#ibcon#*before return 0, iclass 11, count 0 2006.190.07:34:39.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:39.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:39.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:34:39.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:34:39.68$vc4f8/valo=6,772.99 2006.190.07:34:39.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.07:34:39.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.07:34:39.68#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:39.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:39.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:39.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:39.68#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:34:39.68#ibcon#first serial, iclass 13, count 0 2006.190.07:34:39.68#ibcon#enter sib2, iclass 13, count 0 2006.190.07:34:39.68#ibcon#flushed, iclass 13, count 0 2006.190.07:34:39.68#ibcon#about to write, iclass 13, count 0 2006.190.07:34:39.68#ibcon#wrote, iclass 13, count 0 2006.190.07:34:39.68#ibcon#about to read 3, iclass 13, count 0 2006.190.07:34:39.70#ibcon#read 3, iclass 13, count 0 2006.190.07:34:39.70#ibcon#about to read 4, iclass 13, count 0 2006.190.07:34:39.70#ibcon#read 4, iclass 13, count 0 2006.190.07:34:39.70#ibcon#about to read 5, iclass 13, count 0 2006.190.07:34:39.70#ibcon#read 5, iclass 13, count 0 2006.190.07:34:39.70#ibcon#about to read 6, iclass 13, count 0 2006.190.07:34:39.70#ibcon#read 6, iclass 13, count 0 2006.190.07:34:39.70#ibcon#end of sib2, iclass 13, count 0 2006.190.07:34:39.70#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:34:39.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:34:39.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:34:39.70#ibcon#*before write, iclass 13, count 0 2006.190.07:34:39.70#ibcon#enter sib2, iclass 13, count 0 2006.190.07:34:39.70#ibcon#flushed, iclass 13, count 0 2006.190.07:34:39.70#ibcon#about to write, iclass 13, count 0 2006.190.07:34:39.70#ibcon#wrote, iclass 13, count 0 2006.190.07:34:39.70#ibcon#about to read 3, iclass 13, count 0 2006.190.07:34:39.74#ibcon#read 3, iclass 13, count 0 2006.190.07:34:39.74#ibcon#about to read 4, iclass 13, count 0 2006.190.07:34:39.74#ibcon#read 4, iclass 13, count 0 2006.190.07:34:39.74#ibcon#about to read 5, iclass 13, count 0 2006.190.07:34:39.74#ibcon#read 5, iclass 13, count 0 2006.190.07:34:39.74#ibcon#about to read 6, iclass 13, count 0 2006.190.07:34:39.74#ibcon#read 6, iclass 13, count 0 2006.190.07:34:39.74#ibcon#end of sib2, iclass 13, count 0 2006.190.07:34:39.74#ibcon#*after write, iclass 13, count 0 2006.190.07:34:39.74#ibcon#*before return 0, iclass 13, count 0 2006.190.07:34:39.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:39.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:39.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:34:39.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:34:39.74$vc4f8/va=6,6 2006.190.07:34:39.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.07:34:39.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.07:34:39.74#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:39.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:34:39.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:34:39.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:34:39.80#ibcon#enter wrdev, iclass 15, count 2 2006.190.07:34:39.80#ibcon#first serial, iclass 15, count 2 2006.190.07:34:39.80#ibcon#enter sib2, iclass 15, count 2 2006.190.07:34:39.80#ibcon#flushed, iclass 15, count 2 2006.190.07:34:39.80#ibcon#about to write, iclass 15, count 2 2006.190.07:34:39.80#ibcon#wrote, iclass 15, count 2 2006.190.07:34:39.80#ibcon#about to read 3, iclass 15, count 2 2006.190.07:34:39.82#ibcon#read 3, iclass 15, count 2 2006.190.07:34:39.82#ibcon#about to read 4, iclass 15, count 2 2006.190.07:34:39.82#ibcon#read 4, iclass 15, count 2 2006.190.07:34:39.82#ibcon#about to read 5, iclass 15, count 2 2006.190.07:34:39.82#ibcon#read 5, iclass 15, count 2 2006.190.07:34:39.82#ibcon#about to read 6, iclass 15, count 2 2006.190.07:34:39.82#ibcon#read 6, iclass 15, count 2 2006.190.07:34:39.82#ibcon#end of sib2, iclass 15, count 2 2006.190.07:34:39.82#ibcon#*mode == 0, iclass 15, count 2 2006.190.07:34:39.82#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.07:34:39.82#ibcon#[25=AT06-06\r\n] 2006.190.07:34:39.82#ibcon#*before write, iclass 15, count 2 2006.190.07:34:39.82#ibcon#enter sib2, iclass 15, count 2 2006.190.07:34:39.82#ibcon#flushed, iclass 15, count 2 2006.190.07:34:39.82#ibcon#about to write, iclass 15, count 2 2006.190.07:34:39.82#ibcon#wrote, iclass 15, count 2 2006.190.07:34:39.82#ibcon#about to read 3, iclass 15, count 2 2006.190.07:34:39.85#ibcon#read 3, iclass 15, count 2 2006.190.07:34:39.85#ibcon#about to read 4, iclass 15, count 2 2006.190.07:34:39.85#ibcon#read 4, iclass 15, count 2 2006.190.07:34:39.85#ibcon#about to read 5, iclass 15, count 2 2006.190.07:34:39.85#ibcon#read 5, iclass 15, count 2 2006.190.07:34:39.85#ibcon#about to read 6, iclass 15, count 2 2006.190.07:34:39.85#ibcon#read 6, iclass 15, count 2 2006.190.07:34:39.85#ibcon#end of sib2, iclass 15, count 2 2006.190.07:34:39.85#ibcon#*after write, iclass 15, count 2 2006.190.07:34:39.85#ibcon#*before return 0, iclass 15, count 2 2006.190.07:34:39.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:34:39.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:34:39.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.07:34:39.85#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:39.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:34:39.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:34:39.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:34:39.97#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:34:39.97#ibcon#first serial, iclass 15, count 0 2006.190.07:34:39.97#ibcon#enter sib2, iclass 15, count 0 2006.190.07:34:39.97#ibcon#flushed, iclass 15, count 0 2006.190.07:34:39.97#ibcon#about to write, iclass 15, count 0 2006.190.07:34:39.97#ibcon#wrote, iclass 15, count 0 2006.190.07:34:39.97#ibcon#about to read 3, iclass 15, count 0 2006.190.07:34:39.99#ibcon#read 3, iclass 15, count 0 2006.190.07:34:39.99#ibcon#about to read 4, iclass 15, count 0 2006.190.07:34:39.99#ibcon#read 4, iclass 15, count 0 2006.190.07:34:39.99#ibcon#about to read 5, iclass 15, count 0 2006.190.07:34:39.99#ibcon#read 5, iclass 15, count 0 2006.190.07:34:39.99#ibcon#about to read 6, iclass 15, count 0 2006.190.07:34:39.99#ibcon#read 6, iclass 15, count 0 2006.190.07:34:39.99#ibcon#end of sib2, iclass 15, count 0 2006.190.07:34:39.99#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:34:39.99#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:34:39.99#ibcon#[25=USB\r\n] 2006.190.07:34:39.99#ibcon#*before write, iclass 15, count 0 2006.190.07:34:39.99#ibcon#enter sib2, iclass 15, count 0 2006.190.07:34:39.99#ibcon#flushed, iclass 15, count 0 2006.190.07:34:39.99#ibcon#about to write, iclass 15, count 0 2006.190.07:34:39.99#ibcon#wrote, iclass 15, count 0 2006.190.07:34:39.99#ibcon#about to read 3, iclass 15, count 0 2006.190.07:34:40.02#ibcon#read 3, iclass 15, count 0 2006.190.07:34:40.02#ibcon#about to read 4, iclass 15, count 0 2006.190.07:34:40.02#ibcon#read 4, iclass 15, count 0 2006.190.07:34:40.02#ibcon#about to read 5, iclass 15, count 0 2006.190.07:34:40.02#ibcon#read 5, iclass 15, count 0 2006.190.07:34:40.02#ibcon#about to read 6, iclass 15, count 0 2006.190.07:34:40.02#ibcon#read 6, iclass 15, count 0 2006.190.07:34:40.02#ibcon#end of sib2, iclass 15, count 0 2006.190.07:34:40.02#ibcon#*after write, iclass 15, count 0 2006.190.07:34:40.02#ibcon#*before return 0, iclass 15, count 0 2006.190.07:34:40.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:34:40.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:34:40.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:34:40.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:34:40.02$vc4f8/valo=7,832.99 2006.190.07:34:40.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.07:34:40.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.07:34:40.02#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:40.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:34:40.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:34:40.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:34:40.02#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:34:40.02#ibcon#first serial, iclass 17, count 0 2006.190.07:34:40.02#ibcon#enter sib2, iclass 17, count 0 2006.190.07:34:40.02#ibcon#flushed, iclass 17, count 0 2006.190.07:34:40.02#ibcon#about to write, iclass 17, count 0 2006.190.07:34:40.02#ibcon#wrote, iclass 17, count 0 2006.190.07:34:40.02#ibcon#about to read 3, iclass 17, count 0 2006.190.07:34:40.04#ibcon#read 3, iclass 17, count 0 2006.190.07:34:40.04#ibcon#about to read 4, iclass 17, count 0 2006.190.07:34:40.04#ibcon#read 4, iclass 17, count 0 2006.190.07:34:40.04#ibcon#about to read 5, iclass 17, count 0 2006.190.07:34:40.04#ibcon#read 5, iclass 17, count 0 2006.190.07:34:40.04#ibcon#about to read 6, iclass 17, count 0 2006.190.07:34:40.04#ibcon#read 6, iclass 17, count 0 2006.190.07:34:40.04#ibcon#end of sib2, iclass 17, count 0 2006.190.07:34:40.04#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:34:40.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:34:40.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:34:40.04#ibcon#*before write, iclass 17, count 0 2006.190.07:34:40.04#ibcon#enter sib2, iclass 17, count 0 2006.190.07:34:40.04#ibcon#flushed, iclass 17, count 0 2006.190.07:34:40.04#ibcon#about to write, iclass 17, count 0 2006.190.07:34:40.04#ibcon#wrote, iclass 17, count 0 2006.190.07:34:40.04#ibcon#about to read 3, iclass 17, count 0 2006.190.07:34:40.08#ibcon#read 3, iclass 17, count 0 2006.190.07:34:40.08#ibcon#about to read 4, iclass 17, count 0 2006.190.07:34:40.08#ibcon#read 4, iclass 17, count 0 2006.190.07:34:40.08#ibcon#about to read 5, iclass 17, count 0 2006.190.07:34:40.08#ibcon#read 5, iclass 17, count 0 2006.190.07:34:40.08#ibcon#about to read 6, iclass 17, count 0 2006.190.07:34:40.08#ibcon#read 6, iclass 17, count 0 2006.190.07:34:40.08#ibcon#end of sib2, iclass 17, count 0 2006.190.07:34:40.08#ibcon#*after write, iclass 17, count 0 2006.190.07:34:40.08#ibcon#*before return 0, iclass 17, count 0 2006.190.07:34:40.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:34:40.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:34:40.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:34:40.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:34:40.08$vc4f8/va=7,6 2006.190.07:34:40.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.07:34:40.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.07:34:40.08#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:40.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:34:40.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:34:40.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:34:40.14#ibcon#enter wrdev, iclass 19, count 2 2006.190.07:34:40.14#ibcon#first serial, iclass 19, count 2 2006.190.07:34:40.14#ibcon#enter sib2, iclass 19, count 2 2006.190.07:34:40.14#ibcon#flushed, iclass 19, count 2 2006.190.07:34:40.14#ibcon#about to write, iclass 19, count 2 2006.190.07:34:40.14#ibcon#wrote, iclass 19, count 2 2006.190.07:34:40.14#ibcon#about to read 3, iclass 19, count 2 2006.190.07:34:40.16#ibcon#read 3, iclass 19, count 2 2006.190.07:34:40.16#ibcon#about to read 4, iclass 19, count 2 2006.190.07:34:40.16#ibcon#read 4, iclass 19, count 2 2006.190.07:34:40.16#ibcon#about to read 5, iclass 19, count 2 2006.190.07:34:40.16#ibcon#read 5, iclass 19, count 2 2006.190.07:34:40.16#ibcon#about to read 6, iclass 19, count 2 2006.190.07:34:40.16#ibcon#read 6, iclass 19, count 2 2006.190.07:34:40.16#ibcon#end of sib2, iclass 19, count 2 2006.190.07:34:40.16#ibcon#*mode == 0, iclass 19, count 2 2006.190.07:34:40.16#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.07:34:40.16#ibcon#[25=AT07-06\r\n] 2006.190.07:34:40.16#ibcon#*before write, iclass 19, count 2 2006.190.07:34:40.16#ibcon#enter sib2, iclass 19, count 2 2006.190.07:34:40.16#ibcon#flushed, iclass 19, count 2 2006.190.07:34:40.16#ibcon#about to write, iclass 19, count 2 2006.190.07:34:40.16#ibcon#wrote, iclass 19, count 2 2006.190.07:34:40.16#ibcon#about to read 3, iclass 19, count 2 2006.190.07:34:40.19#ibcon#read 3, iclass 19, count 2 2006.190.07:34:40.19#ibcon#about to read 4, iclass 19, count 2 2006.190.07:34:40.19#ibcon#read 4, iclass 19, count 2 2006.190.07:34:40.19#ibcon#about to read 5, iclass 19, count 2 2006.190.07:34:40.19#ibcon#read 5, iclass 19, count 2 2006.190.07:34:40.19#ibcon#about to read 6, iclass 19, count 2 2006.190.07:34:40.19#ibcon#read 6, iclass 19, count 2 2006.190.07:34:40.19#ibcon#end of sib2, iclass 19, count 2 2006.190.07:34:40.19#ibcon#*after write, iclass 19, count 2 2006.190.07:34:40.19#ibcon#*before return 0, iclass 19, count 2 2006.190.07:34:40.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:34:40.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:34:40.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.07:34:40.19#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:40.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:34:40.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:34:40.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:34:40.31#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:34:40.31#ibcon#first serial, iclass 19, count 0 2006.190.07:34:40.31#ibcon#enter sib2, iclass 19, count 0 2006.190.07:34:40.31#ibcon#flushed, iclass 19, count 0 2006.190.07:34:40.31#ibcon#about to write, iclass 19, count 0 2006.190.07:34:40.31#ibcon#wrote, iclass 19, count 0 2006.190.07:34:40.31#ibcon#about to read 3, iclass 19, count 0 2006.190.07:34:40.33#ibcon#read 3, iclass 19, count 0 2006.190.07:34:40.33#ibcon#about to read 4, iclass 19, count 0 2006.190.07:34:40.33#ibcon#read 4, iclass 19, count 0 2006.190.07:34:40.33#ibcon#about to read 5, iclass 19, count 0 2006.190.07:34:40.33#ibcon#read 5, iclass 19, count 0 2006.190.07:34:40.33#ibcon#about to read 6, iclass 19, count 0 2006.190.07:34:40.33#ibcon#read 6, iclass 19, count 0 2006.190.07:34:40.33#ibcon#end of sib2, iclass 19, count 0 2006.190.07:34:40.33#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:34:40.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:34:40.33#ibcon#[25=USB\r\n] 2006.190.07:34:40.33#ibcon#*before write, iclass 19, count 0 2006.190.07:34:40.33#ibcon#enter sib2, iclass 19, count 0 2006.190.07:34:40.33#ibcon#flushed, iclass 19, count 0 2006.190.07:34:40.33#ibcon#about to write, iclass 19, count 0 2006.190.07:34:40.33#ibcon#wrote, iclass 19, count 0 2006.190.07:34:40.33#ibcon#about to read 3, iclass 19, count 0 2006.190.07:34:40.36#ibcon#read 3, iclass 19, count 0 2006.190.07:34:40.36#ibcon#about to read 4, iclass 19, count 0 2006.190.07:34:40.36#ibcon#read 4, iclass 19, count 0 2006.190.07:34:40.36#ibcon#about to read 5, iclass 19, count 0 2006.190.07:34:40.36#ibcon#read 5, iclass 19, count 0 2006.190.07:34:40.36#ibcon#about to read 6, iclass 19, count 0 2006.190.07:34:40.36#ibcon#read 6, iclass 19, count 0 2006.190.07:34:40.36#ibcon#end of sib2, iclass 19, count 0 2006.190.07:34:40.36#ibcon#*after write, iclass 19, count 0 2006.190.07:34:40.36#ibcon#*before return 0, iclass 19, count 0 2006.190.07:34:40.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:34:40.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:34:40.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:34:40.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:34:40.36$vc4f8/valo=8,852.99 2006.190.07:34:40.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.07:34:40.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.07:34:40.36#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:40.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:34:40.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:34:40.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:34:40.36#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:34:40.36#ibcon#first serial, iclass 21, count 0 2006.190.07:34:40.36#ibcon#enter sib2, iclass 21, count 0 2006.190.07:34:40.36#ibcon#flushed, iclass 21, count 0 2006.190.07:34:40.36#ibcon#about to write, iclass 21, count 0 2006.190.07:34:40.36#ibcon#wrote, iclass 21, count 0 2006.190.07:34:40.36#ibcon#about to read 3, iclass 21, count 0 2006.190.07:34:40.38#ibcon#read 3, iclass 21, count 0 2006.190.07:34:40.38#ibcon#about to read 4, iclass 21, count 0 2006.190.07:34:40.38#ibcon#read 4, iclass 21, count 0 2006.190.07:34:40.38#ibcon#about to read 5, iclass 21, count 0 2006.190.07:34:40.38#ibcon#read 5, iclass 21, count 0 2006.190.07:34:40.38#ibcon#about to read 6, iclass 21, count 0 2006.190.07:34:40.38#ibcon#read 6, iclass 21, count 0 2006.190.07:34:40.38#ibcon#end of sib2, iclass 21, count 0 2006.190.07:34:40.38#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:34:40.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:34:40.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:34:40.38#ibcon#*before write, iclass 21, count 0 2006.190.07:34:40.38#ibcon#enter sib2, iclass 21, count 0 2006.190.07:34:40.38#ibcon#flushed, iclass 21, count 0 2006.190.07:34:40.38#ibcon#about to write, iclass 21, count 0 2006.190.07:34:40.38#ibcon#wrote, iclass 21, count 0 2006.190.07:34:40.38#ibcon#about to read 3, iclass 21, count 0 2006.190.07:34:40.42#ibcon#read 3, iclass 21, count 0 2006.190.07:34:40.42#ibcon#about to read 4, iclass 21, count 0 2006.190.07:34:40.42#ibcon#read 4, iclass 21, count 0 2006.190.07:34:40.42#ibcon#about to read 5, iclass 21, count 0 2006.190.07:34:40.42#ibcon#read 5, iclass 21, count 0 2006.190.07:34:40.42#ibcon#about to read 6, iclass 21, count 0 2006.190.07:34:40.42#ibcon#read 6, iclass 21, count 0 2006.190.07:34:40.42#ibcon#end of sib2, iclass 21, count 0 2006.190.07:34:40.42#ibcon#*after write, iclass 21, count 0 2006.190.07:34:40.42#ibcon#*before return 0, iclass 21, count 0 2006.190.07:34:40.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:34:40.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:34:40.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:34:40.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:34:40.42$vc4f8/va=8,6 2006.190.07:34:40.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.07:34:40.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.07:34:40.42#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:40.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:34:40.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:34:40.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:34:40.48#ibcon#enter wrdev, iclass 23, count 2 2006.190.07:34:40.48#ibcon#first serial, iclass 23, count 2 2006.190.07:34:40.48#ibcon#enter sib2, iclass 23, count 2 2006.190.07:34:40.48#ibcon#flushed, iclass 23, count 2 2006.190.07:34:40.48#ibcon#about to write, iclass 23, count 2 2006.190.07:34:40.48#ibcon#wrote, iclass 23, count 2 2006.190.07:34:40.48#ibcon#about to read 3, iclass 23, count 2 2006.190.07:34:40.50#ibcon#read 3, iclass 23, count 2 2006.190.07:34:40.50#ibcon#about to read 4, iclass 23, count 2 2006.190.07:34:40.50#ibcon#read 4, iclass 23, count 2 2006.190.07:34:40.50#ibcon#about to read 5, iclass 23, count 2 2006.190.07:34:40.50#ibcon#read 5, iclass 23, count 2 2006.190.07:34:40.50#ibcon#about to read 6, iclass 23, count 2 2006.190.07:34:40.50#ibcon#read 6, iclass 23, count 2 2006.190.07:34:40.50#ibcon#end of sib2, iclass 23, count 2 2006.190.07:34:40.50#ibcon#*mode == 0, iclass 23, count 2 2006.190.07:34:40.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.07:34:40.50#ibcon#[25=AT08-06\r\n] 2006.190.07:34:40.50#ibcon#*before write, iclass 23, count 2 2006.190.07:34:40.50#ibcon#enter sib2, iclass 23, count 2 2006.190.07:34:40.50#ibcon#flushed, iclass 23, count 2 2006.190.07:34:40.50#ibcon#about to write, iclass 23, count 2 2006.190.07:34:40.50#ibcon#wrote, iclass 23, count 2 2006.190.07:34:40.50#ibcon#about to read 3, iclass 23, count 2 2006.190.07:34:40.53#ibcon#read 3, iclass 23, count 2 2006.190.07:34:40.53#ibcon#about to read 4, iclass 23, count 2 2006.190.07:34:40.53#ibcon#read 4, iclass 23, count 2 2006.190.07:34:40.53#ibcon#about to read 5, iclass 23, count 2 2006.190.07:34:40.53#ibcon#read 5, iclass 23, count 2 2006.190.07:34:40.53#ibcon#about to read 6, iclass 23, count 2 2006.190.07:34:40.53#ibcon#read 6, iclass 23, count 2 2006.190.07:34:40.53#ibcon#end of sib2, iclass 23, count 2 2006.190.07:34:40.53#ibcon#*after write, iclass 23, count 2 2006.190.07:34:40.53#ibcon#*before return 0, iclass 23, count 2 2006.190.07:34:40.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:34:40.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:34:40.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.07:34:40.53#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:40.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:34:40.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:34:40.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:34:40.65#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:34:40.65#ibcon#first serial, iclass 23, count 0 2006.190.07:34:40.65#ibcon#enter sib2, iclass 23, count 0 2006.190.07:34:40.65#ibcon#flushed, iclass 23, count 0 2006.190.07:34:40.65#ibcon#about to write, iclass 23, count 0 2006.190.07:34:40.65#ibcon#wrote, iclass 23, count 0 2006.190.07:34:40.65#ibcon#about to read 3, iclass 23, count 0 2006.190.07:34:40.67#ibcon#read 3, iclass 23, count 0 2006.190.07:34:40.67#ibcon#about to read 4, iclass 23, count 0 2006.190.07:34:40.67#ibcon#read 4, iclass 23, count 0 2006.190.07:34:40.67#ibcon#about to read 5, iclass 23, count 0 2006.190.07:34:40.67#ibcon#read 5, iclass 23, count 0 2006.190.07:34:40.67#ibcon#about to read 6, iclass 23, count 0 2006.190.07:34:40.67#ibcon#read 6, iclass 23, count 0 2006.190.07:34:40.67#ibcon#end of sib2, iclass 23, count 0 2006.190.07:34:40.67#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:34:40.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:34:40.67#ibcon#[25=USB\r\n] 2006.190.07:34:40.67#ibcon#*before write, iclass 23, count 0 2006.190.07:34:40.67#ibcon#enter sib2, iclass 23, count 0 2006.190.07:34:40.67#ibcon#flushed, iclass 23, count 0 2006.190.07:34:40.67#ibcon#about to write, iclass 23, count 0 2006.190.07:34:40.67#ibcon#wrote, iclass 23, count 0 2006.190.07:34:40.67#ibcon#about to read 3, iclass 23, count 0 2006.190.07:34:40.70#ibcon#read 3, iclass 23, count 0 2006.190.07:34:40.70#ibcon#about to read 4, iclass 23, count 0 2006.190.07:34:40.70#ibcon#read 4, iclass 23, count 0 2006.190.07:34:40.70#ibcon#about to read 5, iclass 23, count 0 2006.190.07:34:40.70#ibcon#read 5, iclass 23, count 0 2006.190.07:34:40.70#ibcon#about to read 6, iclass 23, count 0 2006.190.07:34:40.70#ibcon#read 6, iclass 23, count 0 2006.190.07:34:40.70#ibcon#end of sib2, iclass 23, count 0 2006.190.07:34:40.70#ibcon#*after write, iclass 23, count 0 2006.190.07:34:40.70#ibcon#*before return 0, iclass 23, count 0 2006.190.07:34:40.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:34:40.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:34:40.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:34:40.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:34:40.70$vc4f8/vblo=1,632.99 2006.190.07:34:40.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.07:34:40.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.07:34:40.70#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:40.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:40.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:40.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:40.70#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:34:40.70#ibcon#first serial, iclass 25, count 0 2006.190.07:34:40.70#ibcon#enter sib2, iclass 25, count 0 2006.190.07:34:40.70#ibcon#flushed, iclass 25, count 0 2006.190.07:34:40.70#ibcon#about to write, iclass 25, count 0 2006.190.07:34:40.70#ibcon#wrote, iclass 25, count 0 2006.190.07:34:40.70#ibcon#about to read 3, iclass 25, count 0 2006.190.07:34:40.72#ibcon#read 3, iclass 25, count 0 2006.190.07:34:40.72#ibcon#about to read 4, iclass 25, count 0 2006.190.07:34:40.72#ibcon#read 4, iclass 25, count 0 2006.190.07:34:40.72#ibcon#about to read 5, iclass 25, count 0 2006.190.07:34:40.72#ibcon#read 5, iclass 25, count 0 2006.190.07:34:40.72#ibcon#about to read 6, iclass 25, count 0 2006.190.07:34:40.72#ibcon#read 6, iclass 25, count 0 2006.190.07:34:40.72#ibcon#end of sib2, iclass 25, count 0 2006.190.07:34:40.72#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:34:40.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:34:40.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:34:40.72#ibcon#*before write, iclass 25, count 0 2006.190.07:34:40.72#ibcon#enter sib2, iclass 25, count 0 2006.190.07:34:40.72#ibcon#flushed, iclass 25, count 0 2006.190.07:34:40.72#ibcon#about to write, iclass 25, count 0 2006.190.07:34:40.72#ibcon#wrote, iclass 25, count 0 2006.190.07:34:40.72#ibcon#about to read 3, iclass 25, count 0 2006.190.07:34:40.76#ibcon#read 3, iclass 25, count 0 2006.190.07:34:40.76#ibcon#about to read 4, iclass 25, count 0 2006.190.07:34:40.76#ibcon#read 4, iclass 25, count 0 2006.190.07:34:40.76#ibcon#about to read 5, iclass 25, count 0 2006.190.07:34:40.76#ibcon#read 5, iclass 25, count 0 2006.190.07:34:40.76#ibcon#about to read 6, iclass 25, count 0 2006.190.07:34:40.76#ibcon#read 6, iclass 25, count 0 2006.190.07:34:40.76#ibcon#end of sib2, iclass 25, count 0 2006.190.07:34:40.76#ibcon#*after write, iclass 25, count 0 2006.190.07:34:40.76#ibcon#*before return 0, iclass 25, count 0 2006.190.07:34:40.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:40.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:34:40.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:34:40.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:34:40.76$vc4f8/vb=1,4 2006.190.07:34:40.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.07:34:40.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.07:34:40.76#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:40.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:40.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:40.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:40.76#ibcon#enter wrdev, iclass 27, count 2 2006.190.07:34:40.76#ibcon#first serial, iclass 27, count 2 2006.190.07:34:40.76#ibcon#enter sib2, iclass 27, count 2 2006.190.07:34:40.76#ibcon#flushed, iclass 27, count 2 2006.190.07:34:40.76#ibcon#about to write, iclass 27, count 2 2006.190.07:34:40.76#ibcon#wrote, iclass 27, count 2 2006.190.07:34:40.76#ibcon#about to read 3, iclass 27, count 2 2006.190.07:34:40.78#ibcon#read 3, iclass 27, count 2 2006.190.07:34:40.78#ibcon#about to read 4, iclass 27, count 2 2006.190.07:34:40.78#ibcon#read 4, iclass 27, count 2 2006.190.07:34:40.78#ibcon#about to read 5, iclass 27, count 2 2006.190.07:34:40.78#ibcon#read 5, iclass 27, count 2 2006.190.07:34:40.78#ibcon#about to read 6, iclass 27, count 2 2006.190.07:34:40.78#ibcon#read 6, iclass 27, count 2 2006.190.07:34:40.78#ibcon#end of sib2, iclass 27, count 2 2006.190.07:34:40.78#ibcon#*mode == 0, iclass 27, count 2 2006.190.07:34:40.78#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.07:34:40.78#ibcon#[27=AT01-04\r\n] 2006.190.07:34:40.78#ibcon#*before write, iclass 27, count 2 2006.190.07:34:40.78#ibcon#enter sib2, iclass 27, count 2 2006.190.07:34:40.78#ibcon#flushed, iclass 27, count 2 2006.190.07:34:40.78#ibcon#about to write, iclass 27, count 2 2006.190.07:34:40.78#ibcon#wrote, iclass 27, count 2 2006.190.07:34:40.78#ibcon#about to read 3, iclass 27, count 2 2006.190.07:34:40.81#ibcon#read 3, iclass 27, count 2 2006.190.07:34:40.81#ibcon#about to read 4, iclass 27, count 2 2006.190.07:34:40.81#ibcon#read 4, iclass 27, count 2 2006.190.07:34:40.81#ibcon#about to read 5, iclass 27, count 2 2006.190.07:34:40.81#ibcon#read 5, iclass 27, count 2 2006.190.07:34:40.81#ibcon#about to read 6, iclass 27, count 2 2006.190.07:34:40.81#ibcon#read 6, iclass 27, count 2 2006.190.07:34:40.81#ibcon#end of sib2, iclass 27, count 2 2006.190.07:34:40.81#ibcon#*after write, iclass 27, count 2 2006.190.07:34:40.81#ibcon#*before return 0, iclass 27, count 2 2006.190.07:34:40.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:40.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:34:40.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.07:34:40.81#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:40.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:40.93#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:40.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:40.93#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:34:40.93#ibcon#first serial, iclass 27, count 0 2006.190.07:34:40.93#ibcon#enter sib2, iclass 27, count 0 2006.190.07:34:40.93#ibcon#flushed, iclass 27, count 0 2006.190.07:34:40.93#ibcon#about to write, iclass 27, count 0 2006.190.07:34:40.93#ibcon#wrote, iclass 27, count 0 2006.190.07:34:40.93#ibcon#about to read 3, iclass 27, count 0 2006.190.07:34:40.95#ibcon#read 3, iclass 27, count 0 2006.190.07:34:40.95#ibcon#about to read 4, iclass 27, count 0 2006.190.07:34:40.95#ibcon#read 4, iclass 27, count 0 2006.190.07:34:40.95#ibcon#about to read 5, iclass 27, count 0 2006.190.07:34:40.95#ibcon#read 5, iclass 27, count 0 2006.190.07:34:40.95#ibcon#about to read 6, iclass 27, count 0 2006.190.07:34:40.95#ibcon#read 6, iclass 27, count 0 2006.190.07:34:40.95#ibcon#end of sib2, iclass 27, count 0 2006.190.07:34:40.95#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:34:40.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:34:40.95#ibcon#[27=USB\r\n] 2006.190.07:34:40.95#ibcon#*before write, iclass 27, count 0 2006.190.07:34:40.95#ibcon#enter sib2, iclass 27, count 0 2006.190.07:34:40.95#ibcon#flushed, iclass 27, count 0 2006.190.07:34:40.95#ibcon#about to write, iclass 27, count 0 2006.190.07:34:40.95#ibcon#wrote, iclass 27, count 0 2006.190.07:34:40.95#ibcon#about to read 3, iclass 27, count 0 2006.190.07:34:40.98#ibcon#read 3, iclass 27, count 0 2006.190.07:34:40.98#ibcon#about to read 4, iclass 27, count 0 2006.190.07:34:40.98#ibcon#read 4, iclass 27, count 0 2006.190.07:34:40.98#ibcon#about to read 5, iclass 27, count 0 2006.190.07:34:40.98#ibcon#read 5, iclass 27, count 0 2006.190.07:34:40.98#ibcon#about to read 6, iclass 27, count 0 2006.190.07:34:40.98#ibcon#read 6, iclass 27, count 0 2006.190.07:34:40.98#ibcon#end of sib2, iclass 27, count 0 2006.190.07:34:40.98#ibcon#*after write, iclass 27, count 0 2006.190.07:34:40.98#ibcon#*before return 0, iclass 27, count 0 2006.190.07:34:40.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:40.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:34:40.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:34:40.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:34:40.98$vc4f8/vblo=2,640.99 2006.190.07:34:40.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.07:34:40.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.07:34:40.98#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:40.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:40.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:40.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:40.98#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:34:40.98#ibcon#first serial, iclass 29, count 0 2006.190.07:34:40.98#ibcon#enter sib2, iclass 29, count 0 2006.190.07:34:40.98#ibcon#flushed, iclass 29, count 0 2006.190.07:34:40.98#ibcon#about to write, iclass 29, count 0 2006.190.07:34:40.98#ibcon#wrote, iclass 29, count 0 2006.190.07:34:40.98#ibcon#about to read 3, iclass 29, count 0 2006.190.07:34:41.00#ibcon#read 3, iclass 29, count 0 2006.190.07:34:41.00#ibcon#about to read 4, iclass 29, count 0 2006.190.07:34:41.00#ibcon#read 4, iclass 29, count 0 2006.190.07:34:41.00#ibcon#about to read 5, iclass 29, count 0 2006.190.07:34:41.00#ibcon#read 5, iclass 29, count 0 2006.190.07:34:41.00#ibcon#about to read 6, iclass 29, count 0 2006.190.07:34:41.00#ibcon#read 6, iclass 29, count 0 2006.190.07:34:41.00#ibcon#end of sib2, iclass 29, count 0 2006.190.07:34:41.00#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:34:41.00#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:34:41.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:34:41.00#ibcon#*before write, iclass 29, count 0 2006.190.07:34:41.00#ibcon#enter sib2, iclass 29, count 0 2006.190.07:34:41.00#ibcon#flushed, iclass 29, count 0 2006.190.07:34:41.00#ibcon#about to write, iclass 29, count 0 2006.190.07:34:41.00#ibcon#wrote, iclass 29, count 0 2006.190.07:34:41.00#ibcon#about to read 3, iclass 29, count 0 2006.190.07:34:41.04#ibcon#read 3, iclass 29, count 0 2006.190.07:34:41.04#ibcon#about to read 4, iclass 29, count 0 2006.190.07:34:41.04#ibcon#read 4, iclass 29, count 0 2006.190.07:34:41.04#ibcon#about to read 5, iclass 29, count 0 2006.190.07:34:41.04#ibcon#read 5, iclass 29, count 0 2006.190.07:34:41.04#ibcon#about to read 6, iclass 29, count 0 2006.190.07:34:41.04#ibcon#read 6, iclass 29, count 0 2006.190.07:34:41.04#ibcon#end of sib2, iclass 29, count 0 2006.190.07:34:41.04#ibcon#*after write, iclass 29, count 0 2006.190.07:34:41.04#ibcon#*before return 0, iclass 29, count 0 2006.190.07:34:41.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:41.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:34:41.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:34:41.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:34:41.04$vc4f8/vb=2,4 2006.190.07:34:41.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.07:34:41.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.07:34:41.04#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:41.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:41.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:41.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:41.10#ibcon#enter wrdev, iclass 31, count 2 2006.190.07:34:41.10#ibcon#first serial, iclass 31, count 2 2006.190.07:34:41.10#ibcon#enter sib2, iclass 31, count 2 2006.190.07:34:41.10#ibcon#flushed, iclass 31, count 2 2006.190.07:34:41.10#ibcon#about to write, iclass 31, count 2 2006.190.07:34:41.10#ibcon#wrote, iclass 31, count 2 2006.190.07:34:41.10#ibcon#about to read 3, iclass 31, count 2 2006.190.07:34:41.12#ibcon#read 3, iclass 31, count 2 2006.190.07:34:41.12#ibcon#about to read 4, iclass 31, count 2 2006.190.07:34:41.12#ibcon#read 4, iclass 31, count 2 2006.190.07:34:41.12#ibcon#about to read 5, iclass 31, count 2 2006.190.07:34:41.12#ibcon#read 5, iclass 31, count 2 2006.190.07:34:41.12#ibcon#about to read 6, iclass 31, count 2 2006.190.07:34:41.12#ibcon#read 6, iclass 31, count 2 2006.190.07:34:41.12#ibcon#end of sib2, iclass 31, count 2 2006.190.07:34:41.12#ibcon#*mode == 0, iclass 31, count 2 2006.190.07:34:41.12#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.07:34:41.12#ibcon#[27=AT02-04\r\n] 2006.190.07:34:41.12#ibcon#*before write, iclass 31, count 2 2006.190.07:34:41.12#ibcon#enter sib2, iclass 31, count 2 2006.190.07:34:41.12#ibcon#flushed, iclass 31, count 2 2006.190.07:34:41.12#ibcon#about to write, iclass 31, count 2 2006.190.07:34:41.12#ibcon#wrote, iclass 31, count 2 2006.190.07:34:41.12#ibcon#about to read 3, iclass 31, count 2 2006.190.07:34:41.15#ibcon#read 3, iclass 31, count 2 2006.190.07:34:41.15#ibcon#about to read 4, iclass 31, count 2 2006.190.07:34:41.15#ibcon#read 4, iclass 31, count 2 2006.190.07:34:41.15#ibcon#about to read 5, iclass 31, count 2 2006.190.07:34:41.15#ibcon#read 5, iclass 31, count 2 2006.190.07:34:41.15#ibcon#about to read 6, iclass 31, count 2 2006.190.07:34:41.15#ibcon#read 6, iclass 31, count 2 2006.190.07:34:41.15#ibcon#end of sib2, iclass 31, count 2 2006.190.07:34:41.15#ibcon#*after write, iclass 31, count 2 2006.190.07:34:41.15#ibcon#*before return 0, iclass 31, count 2 2006.190.07:34:41.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:41.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:34:41.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.07:34:41.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:41.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:41.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:41.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:41.27#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:34:41.27#ibcon#first serial, iclass 31, count 0 2006.190.07:34:41.27#ibcon#enter sib2, iclass 31, count 0 2006.190.07:34:41.27#ibcon#flushed, iclass 31, count 0 2006.190.07:34:41.27#ibcon#about to write, iclass 31, count 0 2006.190.07:34:41.27#ibcon#wrote, iclass 31, count 0 2006.190.07:34:41.27#ibcon#about to read 3, iclass 31, count 0 2006.190.07:34:41.29#ibcon#read 3, iclass 31, count 0 2006.190.07:34:41.29#ibcon#about to read 4, iclass 31, count 0 2006.190.07:34:41.29#ibcon#read 4, iclass 31, count 0 2006.190.07:34:41.29#ibcon#about to read 5, iclass 31, count 0 2006.190.07:34:41.29#ibcon#read 5, iclass 31, count 0 2006.190.07:34:41.29#ibcon#about to read 6, iclass 31, count 0 2006.190.07:34:41.29#ibcon#read 6, iclass 31, count 0 2006.190.07:34:41.29#ibcon#end of sib2, iclass 31, count 0 2006.190.07:34:41.29#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:34:41.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:34:41.29#ibcon#[27=USB\r\n] 2006.190.07:34:41.29#ibcon#*before write, iclass 31, count 0 2006.190.07:34:41.29#ibcon#enter sib2, iclass 31, count 0 2006.190.07:34:41.29#ibcon#flushed, iclass 31, count 0 2006.190.07:34:41.29#ibcon#about to write, iclass 31, count 0 2006.190.07:34:41.29#ibcon#wrote, iclass 31, count 0 2006.190.07:34:41.29#ibcon#about to read 3, iclass 31, count 0 2006.190.07:34:41.32#ibcon#read 3, iclass 31, count 0 2006.190.07:34:41.32#ibcon#about to read 4, iclass 31, count 0 2006.190.07:34:41.32#ibcon#read 4, iclass 31, count 0 2006.190.07:34:41.32#ibcon#about to read 5, iclass 31, count 0 2006.190.07:34:41.32#ibcon#read 5, iclass 31, count 0 2006.190.07:34:41.32#ibcon#about to read 6, iclass 31, count 0 2006.190.07:34:41.32#ibcon#read 6, iclass 31, count 0 2006.190.07:34:41.32#ibcon#end of sib2, iclass 31, count 0 2006.190.07:34:41.32#ibcon#*after write, iclass 31, count 0 2006.190.07:34:41.32#ibcon#*before return 0, iclass 31, count 0 2006.190.07:34:41.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:41.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:34:41.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:34:41.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:34:41.32$vc4f8/vblo=3,656.99 2006.190.07:34:41.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.07:34:41.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.07:34:41.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:41.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:41.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:41.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:41.32#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:34:41.32#ibcon#first serial, iclass 33, count 0 2006.190.07:34:41.32#ibcon#enter sib2, iclass 33, count 0 2006.190.07:34:41.32#ibcon#flushed, iclass 33, count 0 2006.190.07:34:41.32#ibcon#about to write, iclass 33, count 0 2006.190.07:34:41.32#ibcon#wrote, iclass 33, count 0 2006.190.07:34:41.32#ibcon#about to read 3, iclass 33, count 0 2006.190.07:34:41.34#ibcon#read 3, iclass 33, count 0 2006.190.07:34:41.34#ibcon#about to read 4, iclass 33, count 0 2006.190.07:34:41.34#ibcon#read 4, iclass 33, count 0 2006.190.07:34:41.34#ibcon#about to read 5, iclass 33, count 0 2006.190.07:34:41.34#ibcon#read 5, iclass 33, count 0 2006.190.07:34:41.34#ibcon#about to read 6, iclass 33, count 0 2006.190.07:34:41.34#ibcon#read 6, iclass 33, count 0 2006.190.07:34:41.34#ibcon#end of sib2, iclass 33, count 0 2006.190.07:34:41.34#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:34:41.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:34:41.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:34:41.34#ibcon#*before write, iclass 33, count 0 2006.190.07:34:41.34#ibcon#enter sib2, iclass 33, count 0 2006.190.07:34:41.34#ibcon#flushed, iclass 33, count 0 2006.190.07:34:41.34#ibcon#about to write, iclass 33, count 0 2006.190.07:34:41.34#ibcon#wrote, iclass 33, count 0 2006.190.07:34:41.34#ibcon#about to read 3, iclass 33, count 0 2006.190.07:34:41.38#ibcon#read 3, iclass 33, count 0 2006.190.07:34:41.38#ibcon#about to read 4, iclass 33, count 0 2006.190.07:34:41.38#ibcon#read 4, iclass 33, count 0 2006.190.07:34:41.38#ibcon#about to read 5, iclass 33, count 0 2006.190.07:34:41.38#ibcon#read 5, iclass 33, count 0 2006.190.07:34:41.38#ibcon#about to read 6, iclass 33, count 0 2006.190.07:34:41.38#ibcon#read 6, iclass 33, count 0 2006.190.07:34:41.38#ibcon#end of sib2, iclass 33, count 0 2006.190.07:34:41.38#ibcon#*after write, iclass 33, count 0 2006.190.07:34:41.38#ibcon#*before return 0, iclass 33, count 0 2006.190.07:34:41.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:41.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:34:41.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:34:41.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:34:41.38$vc4f8/vb=3,4 2006.190.07:34:41.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.07:34:41.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.07:34:41.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:41.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:41.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:41.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:41.44#ibcon#enter wrdev, iclass 35, count 2 2006.190.07:34:41.44#ibcon#first serial, iclass 35, count 2 2006.190.07:34:41.44#ibcon#enter sib2, iclass 35, count 2 2006.190.07:34:41.44#ibcon#flushed, iclass 35, count 2 2006.190.07:34:41.44#ibcon#about to write, iclass 35, count 2 2006.190.07:34:41.44#ibcon#wrote, iclass 35, count 2 2006.190.07:34:41.44#ibcon#about to read 3, iclass 35, count 2 2006.190.07:34:41.46#ibcon#read 3, iclass 35, count 2 2006.190.07:34:41.46#ibcon#about to read 4, iclass 35, count 2 2006.190.07:34:41.46#ibcon#read 4, iclass 35, count 2 2006.190.07:34:41.46#ibcon#about to read 5, iclass 35, count 2 2006.190.07:34:41.46#ibcon#read 5, iclass 35, count 2 2006.190.07:34:41.46#ibcon#about to read 6, iclass 35, count 2 2006.190.07:34:41.46#ibcon#read 6, iclass 35, count 2 2006.190.07:34:41.46#ibcon#end of sib2, iclass 35, count 2 2006.190.07:34:41.46#ibcon#*mode == 0, iclass 35, count 2 2006.190.07:34:41.46#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.07:34:41.46#ibcon#[27=AT03-04\r\n] 2006.190.07:34:41.46#ibcon#*before write, iclass 35, count 2 2006.190.07:34:41.46#ibcon#enter sib2, iclass 35, count 2 2006.190.07:34:41.46#ibcon#flushed, iclass 35, count 2 2006.190.07:34:41.46#ibcon#about to write, iclass 35, count 2 2006.190.07:34:41.46#ibcon#wrote, iclass 35, count 2 2006.190.07:34:41.46#ibcon#about to read 3, iclass 35, count 2 2006.190.07:34:41.49#ibcon#read 3, iclass 35, count 2 2006.190.07:34:41.49#ibcon#about to read 4, iclass 35, count 2 2006.190.07:34:41.49#ibcon#read 4, iclass 35, count 2 2006.190.07:34:41.49#ibcon#about to read 5, iclass 35, count 2 2006.190.07:34:41.49#ibcon#read 5, iclass 35, count 2 2006.190.07:34:41.49#ibcon#about to read 6, iclass 35, count 2 2006.190.07:34:41.49#ibcon#read 6, iclass 35, count 2 2006.190.07:34:41.49#ibcon#end of sib2, iclass 35, count 2 2006.190.07:34:41.49#ibcon#*after write, iclass 35, count 2 2006.190.07:34:41.49#ibcon#*before return 0, iclass 35, count 2 2006.190.07:34:41.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:41.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:34:41.49#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.07:34:41.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:41.49#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:41.61#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:41.61#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:41.61#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:34:41.61#ibcon#first serial, iclass 35, count 0 2006.190.07:34:41.61#ibcon#enter sib2, iclass 35, count 0 2006.190.07:34:41.61#ibcon#flushed, iclass 35, count 0 2006.190.07:34:41.61#ibcon#about to write, iclass 35, count 0 2006.190.07:34:41.61#ibcon#wrote, iclass 35, count 0 2006.190.07:34:41.61#ibcon#about to read 3, iclass 35, count 0 2006.190.07:34:41.63#ibcon#read 3, iclass 35, count 0 2006.190.07:34:41.63#ibcon#about to read 4, iclass 35, count 0 2006.190.07:34:41.63#ibcon#read 4, iclass 35, count 0 2006.190.07:34:41.63#ibcon#about to read 5, iclass 35, count 0 2006.190.07:34:41.63#ibcon#read 5, iclass 35, count 0 2006.190.07:34:41.63#ibcon#about to read 6, iclass 35, count 0 2006.190.07:34:41.63#ibcon#read 6, iclass 35, count 0 2006.190.07:34:41.63#ibcon#end of sib2, iclass 35, count 0 2006.190.07:34:41.63#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:34:41.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:34:41.63#ibcon#[27=USB\r\n] 2006.190.07:34:41.63#ibcon#*before write, iclass 35, count 0 2006.190.07:34:41.63#ibcon#enter sib2, iclass 35, count 0 2006.190.07:34:41.63#ibcon#flushed, iclass 35, count 0 2006.190.07:34:41.63#ibcon#about to write, iclass 35, count 0 2006.190.07:34:41.63#ibcon#wrote, iclass 35, count 0 2006.190.07:34:41.63#ibcon#about to read 3, iclass 35, count 0 2006.190.07:34:41.66#ibcon#read 3, iclass 35, count 0 2006.190.07:34:41.66#ibcon#about to read 4, iclass 35, count 0 2006.190.07:34:41.66#ibcon#read 4, iclass 35, count 0 2006.190.07:34:41.66#ibcon#about to read 5, iclass 35, count 0 2006.190.07:34:41.66#ibcon#read 5, iclass 35, count 0 2006.190.07:34:41.66#ibcon#about to read 6, iclass 35, count 0 2006.190.07:34:41.66#ibcon#read 6, iclass 35, count 0 2006.190.07:34:41.66#ibcon#end of sib2, iclass 35, count 0 2006.190.07:34:41.66#ibcon#*after write, iclass 35, count 0 2006.190.07:34:41.66#ibcon#*before return 0, iclass 35, count 0 2006.190.07:34:41.66#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:41.66#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:34:41.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:34:41.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:34:41.66$vc4f8/vblo=4,712.99 2006.190.07:34:41.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.07:34:41.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.07:34:41.66#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:41.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:41.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:41.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:41.66#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:34:41.66#ibcon#first serial, iclass 37, count 0 2006.190.07:34:41.66#ibcon#enter sib2, iclass 37, count 0 2006.190.07:34:41.66#ibcon#flushed, iclass 37, count 0 2006.190.07:34:41.66#ibcon#about to write, iclass 37, count 0 2006.190.07:34:41.66#ibcon#wrote, iclass 37, count 0 2006.190.07:34:41.66#ibcon#about to read 3, iclass 37, count 0 2006.190.07:34:41.68#ibcon#read 3, iclass 37, count 0 2006.190.07:34:41.68#ibcon#about to read 4, iclass 37, count 0 2006.190.07:34:41.68#ibcon#read 4, iclass 37, count 0 2006.190.07:34:41.68#ibcon#about to read 5, iclass 37, count 0 2006.190.07:34:41.68#ibcon#read 5, iclass 37, count 0 2006.190.07:34:41.68#ibcon#about to read 6, iclass 37, count 0 2006.190.07:34:41.68#ibcon#read 6, iclass 37, count 0 2006.190.07:34:41.68#ibcon#end of sib2, iclass 37, count 0 2006.190.07:34:41.68#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:34:41.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:34:41.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:34:41.68#ibcon#*before write, iclass 37, count 0 2006.190.07:34:41.68#ibcon#enter sib2, iclass 37, count 0 2006.190.07:34:41.68#ibcon#flushed, iclass 37, count 0 2006.190.07:34:41.68#ibcon#about to write, iclass 37, count 0 2006.190.07:34:41.68#ibcon#wrote, iclass 37, count 0 2006.190.07:34:41.68#ibcon#about to read 3, iclass 37, count 0 2006.190.07:34:41.72#ibcon#read 3, iclass 37, count 0 2006.190.07:34:41.72#ibcon#about to read 4, iclass 37, count 0 2006.190.07:34:41.72#ibcon#read 4, iclass 37, count 0 2006.190.07:34:41.72#ibcon#about to read 5, iclass 37, count 0 2006.190.07:34:41.72#ibcon#read 5, iclass 37, count 0 2006.190.07:34:41.72#ibcon#about to read 6, iclass 37, count 0 2006.190.07:34:41.72#ibcon#read 6, iclass 37, count 0 2006.190.07:34:41.72#ibcon#end of sib2, iclass 37, count 0 2006.190.07:34:41.72#ibcon#*after write, iclass 37, count 0 2006.190.07:34:41.72#ibcon#*before return 0, iclass 37, count 0 2006.190.07:34:41.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:41.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:34:41.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:34:41.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:34:41.72$vc4f8/vb=4,4 2006.190.07:34:41.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.07:34:41.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.07:34:41.72#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:41.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:41.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:41.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:41.78#ibcon#enter wrdev, iclass 39, count 2 2006.190.07:34:41.78#ibcon#first serial, iclass 39, count 2 2006.190.07:34:41.78#ibcon#enter sib2, iclass 39, count 2 2006.190.07:34:41.78#ibcon#flushed, iclass 39, count 2 2006.190.07:34:41.78#ibcon#about to write, iclass 39, count 2 2006.190.07:34:41.78#ibcon#wrote, iclass 39, count 2 2006.190.07:34:41.78#ibcon#about to read 3, iclass 39, count 2 2006.190.07:34:41.80#ibcon#read 3, iclass 39, count 2 2006.190.07:34:41.80#ibcon#about to read 4, iclass 39, count 2 2006.190.07:34:41.80#ibcon#read 4, iclass 39, count 2 2006.190.07:34:41.80#ibcon#about to read 5, iclass 39, count 2 2006.190.07:34:41.80#ibcon#read 5, iclass 39, count 2 2006.190.07:34:41.80#ibcon#about to read 6, iclass 39, count 2 2006.190.07:34:41.80#ibcon#read 6, iclass 39, count 2 2006.190.07:34:41.80#ibcon#end of sib2, iclass 39, count 2 2006.190.07:34:41.80#ibcon#*mode == 0, iclass 39, count 2 2006.190.07:34:41.80#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.07:34:41.80#ibcon#[27=AT04-04\r\n] 2006.190.07:34:41.80#ibcon#*before write, iclass 39, count 2 2006.190.07:34:41.80#ibcon#enter sib2, iclass 39, count 2 2006.190.07:34:41.80#ibcon#flushed, iclass 39, count 2 2006.190.07:34:41.80#ibcon#about to write, iclass 39, count 2 2006.190.07:34:41.80#ibcon#wrote, iclass 39, count 2 2006.190.07:34:41.80#ibcon#about to read 3, iclass 39, count 2 2006.190.07:34:41.83#ibcon#read 3, iclass 39, count 2 2006.190.07:34:41.83#ibcon#about to read 4, iclass 39, count 2 2006.190.07:34:41.83#ibcon#read 4, iclass 39, count 2 2006.190.07:34:41.83#ibcon#about to read 5, iclass 39, count 2 2006.190.07:34:41.83#ibcon#read 5, iclass 39, count 2 2006.190.07:34:41.83#ibcon#about to read 6, iclass 39, count 2 2006.190.07:34:41.83#ibcon#read 6, iclass 39, count 2 2006.190.07:34:41.83#ibcon#end of sib2, iclass 39, count 2 2006.190.07:34:41.83#ibcon#*after write, iclass 39, count 2 2006.190.07:34:41.83#ibcon#*before return 0, iclass 39, count 2 2006.190.07:34:41.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:41.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:34:41.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.07:34:41.83#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:41.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:41.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:41.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:41.95#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:34:41.95#ibcon#first serial, iclass 39, count 0 2006.190.07:34:41.95#ibcon#enter sib2, iclass 39, count 0 2006.190.07:34:41.95#ibcon#flushed, iclass 39, count 0 2006.190.07:34:41.95#ibcon#about to write, iclass 39, count 0 2006.190.07:34:41.95#ibcon#wrote, iclass 39, count 0 2006.190.07:34:41.95#ibcon#about to read 3, iclass 39, count 0 2006.190.07:34:41.97#ibcon#read 3, iclass 39, count 0 2006.190.07:34:41.97#ibcon#about to read 4, iclass 39, count 0 2006.190.07:34:41.97#ibcon#read 4, iclass 39, count 0 2006.190.07:34:41.97#ibcon#about to read 5, iclass 39, count 0 2006.190.07:34:41.97#ibcon#read 5, iclass 39, count 0 2006.190.07:34:41.97#ibcon#about to read 6, iclass 39, count 0 2006.190.07:34:41.97#ibcon#read 6, iclass 39, count 0 2006.190.07:34:41.97#ibcon#end of sib2, iclass 39, count 0 2006.190.07:34:41.97#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:34:41.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:34:41.97#ibcon#[27=USB\r\n] 2006.190.07:34:41.97#ibcon#*before write, iclass 39, count 0 2006.190.07:34:41.97#ibcon#enter sib2, iclass 39, count 0 2006.190.07:34:41.97#ibcon#flushed, iclass 39, count 0 2006.190.07:34:41.97#ibcon#about to write, iclass 39, count 0 2006.190.07:34:41.97#ibcon#wrote, iclass 39, count 0 2006.190.07:34:41.97#ibcon#about to read 3, iclass 39, count 0 2006.190.07:34:42.00#ibcon#read 3, iclass 39, count 0 2006.190.07:34:42.00#ibcon#about to read 4, iclass 39, count 0 2006.190.07:34:42.00#ibcon#read 4, iclass 39, count 0 2006.190.07:34:42.00#ibcon#about to read 5, iclass 39, count 0 2006.190.07:34:42.00#ibcon#read 5, iclass 39, count 0 2006.190.07:34:42.00#ibcon#about to read 6, iclass 39, count 0 2006.190.07:34:42.00#ibcon#read 6, iclass 39, count 0 2006.190.07:34:42.00#ibcon#end of sib2, iclass 39, count 0 2006.190.07:34:42.00#ibcon#*after write, iclass 39, count 0 2006.190.07:34:42.00#ibcon#*before return 0, iclass 39, count 0 2006.190.07:34:42.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:42.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:34:42.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:34:42.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:34:42.00$vc4f8/vblo=5,744.99 2006.190.07:34:42.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.07:34:42.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.07:34:42.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:42.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:34:42.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:34:42.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:34:42.00#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:34:42.00#ibcon#first serial, iclass 3, count 0 2006.190.07:34:42.00#ibcon#enter sib2, iclass 3, count 0 2006.190.07:34:42.00#ibcon#flushed, iclass 3, count 0 2006.190.07:34:42.00#ibcon#about to write, iclass 3, count 0 2006.190.07:34:42.00#ibcon#wrote, iclass 3, count 0 2006.190.07:34:42.00#ibcon#about to read 3, iclass 3, count 0 2006.190.07:34:42.02#ibcon#read 3, iclass 3, count 0 2006.190.07:34:42.02#ibcon#about to read 4, iclass 3, count 0 2006.190.07:34:42.02#ibcon#read 4, iclass 3, count 0 2006.190.07:34:42.02#ibcon#about to read 5, iclass 3, count 0 2006.190.07:34:42.02#ibcon#read 5, iclass 3, count 0 2006.190.07:34:42.02#ibcon#about to read 6, iclass 3, count 0 2006.190.07:34:42.02#ibcon#read 6, iclass 3, count 0 2006.190.07:34:42.02#ibcon#end of sib2, iclass 3, count 0 2006.190.07:34:42.02#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:34:42.02#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:34:42.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:34:42.02#ibcon#*before write, iclass 3, count 0 2006.190.07:34:42.02#ibcon#enter sib2, iclass 3, count 0 2006.190.07:34:42.02#ibcon#flushed, iclass 3, count 0 2006.190.07:34:42.02#ibcon#about to write, iclass 3, count 0 2006.190.07:34:42.02#ibcon#wrote, iclass 3, count 0 2006.190.07:34:42.02#ibcon#about to read 3, iclass 3, count 0 2006.190.07:34:42.06#ibcon#read 3, iclass 3, count 0 2006.190.07:34:42.06#ibcon#about to read 4, iclass 3, count 0 2006.190.07:34:42.06#ibcon#read 4, iclass 3, count 0 2006.190.07:34:42.06#ibcon#about to read 5, iclass 3, count 0 2006.190.07:34:42.06#ibcon#read 5, iclass 3, count 0 2006.190.07:34:42.06#ibcon#about to read 6, iclass 3, count 0 2006.190.07:34:42.06#ibcon#read 6, iclass 3, count 0 2006.190.07:34:42.06#ibcon#end of sib2, iclass 3, count 0 2006.190.07:34:42.06#ibcon#*after write, iclass 3, count 0 2006.190.07:34:42.06#ibcon#*before return 0, iclass 3, count 0 2006.190.07:34:42.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:34:42.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:34:42.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:34:42.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:34:42.06$vc4f8/vb=5,4 2006.190.07:34:42.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.07:34:42.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.07:34:42.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:42.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:34:42.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:34:42.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:34:42.12#ibcon#enter wrdev, iclass 5, count 2 2006.190.07:34:42.12#ibcon#first serial, iclass 5, count 2 2006.190.07:34:42.12#ibcon#enter sib2, iclass 5, count 2 2006.190.07:34:42.12#ibcon#flushed, iclass 5, count 2 2006.190.07:34:42.12#ibcon#about to write, iclass 5, count 2 2006.190.07:34:42.12#ibcon#wrote, iclass 5, count 2 2006.190.07:34:42.12#ibcon#about to read 3, iclass 5, count 2 2006.190.07:34:42.14#ibcon#read 3, iclass 5, count 2 2006.190.07:34:42.14#ibcon#about to read 4, iclass 5, count 2 2006.190.07:34:42.14#ibcon#read 4, iclass 5, count 2 2006.190.07:34:42.14#ibcon#about to read 5, iclass 5, count 2 2006.190.07:34:42.14#ibcon#read 5, iclass 5, count 2 2006.190.07:34:42.14#ibcon#about to read 6, iclass 5, count 2 2006.190.07:34:42.14#ibcon#read 6, iclass 5, count 2 2006.190.07:34:42.14#ibcon#end of sib2, iclass 5, count 2 2006.190.07:34:42.14#ibcon#*mode == 0, iclass 5, count 2 2006.190.07:34:42.14#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.07:34:42.14#ibcon#[27=AT05-04\r\n] 2006.190.07:34:42.14#ibcon#*before write, iclass 5, count 2 2006.190.07:34:42.14#ibcon#enter sib2, iclass 5, count 2 2006.190.07:34:42.14#ibcon#flushed, iclass 5, count 2 2006.190.07:34:42.14#ibcon#about to write, iclass 5, count 2 2006.190.07:34:42.14#ibcon#wrote, iclass 5, count 2 2006.190.07:34:42.14#ibcon#about to read 3, iclass 5, count 2 2006.190.07:34:42.17#ibcon#read 3, iclass 5, count 2 2006.190.07:34:42.17#ibcon#about to read 4, iclass 5, count 2 2006.190.07:34:42.17#ibcon#read 4, iclass 5, count 2 2006.190.07:34:42.17#ibcon#about to read 5, iclass 5, count 2 2006.190.07:34:42.17#ibcon#read 5, iclass 5, count 2 2006.190.07:34:42.17#ibcon#about to read 6, iclass 5, count 2 2006.190.07:34:42.17#ibcon#read 6, iclass 5, count 2 2006.190.07:34:42.17#ibcon#end of sib2, iclass 5, count 2 2006.190.07:34:42.17#ibcon#*after write, iclass 5, count 2 2006.190.07:34:42.17#ibcon#*before return 0, iclass 5, count 2 2006.190.07:34:42.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:34:42.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:34:42.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.07:34:42.17#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:42.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:34:42.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:34:42.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:34:42.29#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:34:42.29#ibcon#first serial, iclass 5, count 0 2006.190.07:34:42.29#ibcon#enter sib2, iclass 5, count 0 2006.190.07:34:42.29#ibcon#flushed, iclass 5, count 0 2006.190.07:34:42.29#ibcon#about to write, iclass 5, count 0 2006.190.07:34:42.29#ibcon#wrote, iclass 5, count 0 2006.190.07:34:42.29#ibcon#about to read 3, iclass 5, count 0 2006.190.07:34:42.31#ibcon#read 3, iclass 5, count 0 2006.190.07:34:42.31#ibcon#about to read 4, iclass 5, count 0 2006.190.07:34:42.31#ibcon#read 4, iclass 5, count 0 2006.190.07:34:42.31#ibcon#about to read 5, iclass 5, count 0 2006.190.07:34:42.31#ibcon#read 5, iclass 5, count 0 2006.190.07:34:42.31#ibcon#about to read 6, iclass 5, count 0 2006.190.07:34:42.31#ibcon#read 6, iclass 5, count 0 2006.190.07:34:42.31#ibcon#end of sib2, iclass 5, count 0 2006.190.07:34:42.31#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:34:42.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:34:42.31#ibcon#[27=USB\r\n] 2006.190.07:34:42.31#ibcon#*before write, iclass 5, count 0 2006.190.07:34:42.31#ibcon#enter sib2, iclass 5, count 0 2006.190.07:34:42.31#ibcon#flushed, iclass 5, count 0 2006.190.07:34:42.31#ibcon#about to write, iclass 5, count 0 2006.190.07:34:42.31#ibcon#wrote, iclass 5, count 0 2006.190.07:34:42.31#ibcon#about to read 3, iclass 5, count 0 2006.190.07:34:42.34#ibcon#read 3, iclass 5, count 0 2006.190.07:34:42.34#ibcon#about to read 4, iclass 5, count 0 2006.190.07:34:42.34#ibcon#read 4, iclass 5, count 0 2006.190.07:34:42.34#ibcon#about to read 5, iclass 5, count 0 2006.190.07:34:42.34#ibcon#read 5, iclass 5, count 0 2006.190.07:34:42.34#ibcon#about to read 6, iclass 5, count 0 2006.190.07:34:42.34#ibcon#read 6, iclass 5, count 0 2006.190.07:34:42.34#ibcon#end of sib2, iclass 5, count 0 2006.190.07:34:42.34#ibcon#*after write, iclass 5, count 0 2006.190.07:34:42.34#ibcon#*before return 0, iclass 5, count 0 2006.190.07:34:42.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:34:42.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:34:42.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:34:42.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:34:42.34$vc4f8/vblo=6,752.99 2006.190.07:34:42.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.07:34:42.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.07:34:42.34#ibcon#ireg 17 cls_cnt 0 2006.190.07:34:42.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:42.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:42.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:42.34#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:34:42.34#ibcon#first serial, iclass 7, count 0 2006.190.07:34:42.34#ibcon#enter sib2, iclass 7, count 0 2006.190.07:34:42.34#ibcon#flushed, iclass 7, count 0 2006.190.07:34:42.34#ibcon#about to write, iclass 7, count 0 2006.190.07:34:42.34#ibcon#wrote, iclass 7, count 0 2006.190.07:34:42.34#ibcon#about to read 3, iclass 7, count 0 2006.190.07:34:42.36#ibcon#read 3, iclass 7, count 0 2006.190.07:34:42.36#ibcon#about to read 4, iclass 7, count 0 2006.190.07:34:42.36#ibcon#read 4, iclass 7, count 0 2006.190.07:34:42.36#ibcon#about to read 5, iclass 7, count 0 2006.190.07:34:42.36#ibcon#read 5, iclass 7, count 0 2006.190.07:34:42.36#ibcon#about to read 6, iclass 7, count 0 2006.190.07:34:42.36#ibcon#read 6, iclass 7, count 0 2006.190.07:34:42.36#ibcon#end of sib2, iclass 7, count 0 2006.190.07:34:42.36#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:34:42.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:34:42.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:34:42.36#ibcon#*before write, iclass 7, count 0 2006.190.07:34:42.36#ibcon#enter sib2, iclass 7, count 0 2006.190.07:34:42.36#ibcon#flushed, iclass 7, count 0 2006.190.07:34:42.36#ibcon#about to write, iclass 7, count 0 2006.190.07:34:42.36#ibcon#wrote, iclass 7, count 0 2006.190.07:34:42.36#ibcon#about to read 3, iclass 7, count 0 2006.190.07:34:42.40#ibcon#read 3, iclass 7, count 0 2006.190.07:34:42.40#ibcon#about to read 4, iclass 7, count 0 2006.190.07:34:42.40#ibcon#read 4, iclass 7, count 0 2006.190.07:34:42.40#ibcon#about to read 5, iclass 7, count 0 2006.190.07:34:42.40#ibcon#read 5, iclass 7, count 0 2006.190.07:34:42.40#ibcon#about to read 6, iclass 7, count 0 2006.190.07:34:42.40#ibcon#read 6, iclass 7, count 0 2006.190.07:34:42.40#ibcon#end of sib2, iclass 7, count 0 2006.190.07:34:42.40#ibcon#*after write, iclass 7, count 0 2006.190.07:34:42.40#ibcon#*before return 0, iclass 7, count 0 2006.190.07:34:42.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:42.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:34:42.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:34:42.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:34:42.40$vc4f8/vb=6,4 2006.190.07:34:42.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.07:34:42.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.07:34:42.40#ibcon#ireg 11 cls_cnt 2 2006.190.07:34:42.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:42.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:42.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:42.46#ibcon#enter wrdev, iclass 11, count 2 2006.190.07:34:42.46#ibcon#first serial, iclass 11, count 2 2006.190.07:34:42.46#ibcon#enter sib2, iclass 11, count 2 2006.190.07:34:42.46#ibcon#flushed, iclass 11, count 2 2006.190.07:34:42.46#ibcon#about to write, iclass 11, count 2 2006.190.07:34:42.46#ibcon#wrote, iclass 11, count 2 2006.190.07:34:42.46#ibcon#about to read 3, iclass 11, count 2 2006.190.07:34:42.48#ibcon#read 3, iclass 11, count 2 2006.190.07:34:42.48#ibcon#about to read 4, iclass 11, count 2 2006.190.07:34:42.48#ibcon#read 4, iclass 11, count 2 2006.190.07:34:42.48#ibcon#about to read 5, iclass 11, count 2 2006.190.07:34:42.48#ibcon#read 5, iclass 11, count 2 2006.190.07:34:42.48#ibcon#about to read 6, iclass 11, count 2 2006.190.07:34:42.48#ibcon#read 6, iclass 11, count 2 2006.190.07:34:42.48#ibcon#end of sib2, iclass 11, count 2 2006.190.07:34:42.48#ibcon#*mode == 0, iclass 11, count 2 2006.190.07:34:42.48#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.07:34:42.48#ibcon#[27=AT06-04\r\n] 2006.190.07:34:42.48#ibcon#*before write, iclass 11, count 2 2006.190.07:34:42.48#ibcon#enter sib2, iclass 11, count 2 2006.190.07:34:42.48#ibcon#flushed, iclass 11, count 2 2006.190.07:34:42.48#ibcon#about to write, iclass 11, count 2 2006.190.07:34:42.48#ibcon#wrote, iclass 11, count 2 2006.190.07:34:42.48#ibcon#about to read 3, iclass 11, count 2 2006.190.07:34:42.51#ibcon#read 3, iclass 11, count 2 2006.190.07:34:42.51#ibcon#about to read 4, iclass 11, count 2 2006.190.07:34:42.51#ibcon#read 4, iclass 11, count 2 2006.190.07:34:42.51#ibcon#about to read 5, iclass 11, count 2 2006.190.07:34:42.51#ibcon#read 5, iclass 11, count 2 2006.190.07:34:42.51#ibcon#about to read 6, iclass 11, count 2 2006.190.07:34:42.51#ibcon#read 6, iclass 11, count 2 2006.190.07:34:42.51#ibcon#end of sib2, iclass 11, count 2 2006.190.07:34:42.51#ibcon#*after write, iclass 11, count 2 2006.190.07:34:42.51#ibcon#*before return 0, iclass 11, count 2 2006.190.07:34:42.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:42.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:34:42.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.07:34:42.51#ibcon#ireg 7 cls_cnt 0 2006.190.07:34:42.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:42.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:42.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:42.63#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:34:42.63#ibcon#first serial, iclass 11, count 0 2006.190.07:34:42.63#ibcon#enter sib2, iclass 11, count 0 2006.190.07:34:42.63#ibcon#flushed, iclass 11, count 0 2006.190.07:34:42.63#ibcon#about to write, iclass 11, count 0 2006.190.07:34:42.63#ibcon#wrote, iclass 11, count 0 2006.190.07:34:42.63#ibcon#about to read 3, iclass 11, count 0 2006.190.07:34:42.65#ibcon#read 3, iclass 11, count 0 2006.190.07:34:42.65#ibcon#about to read 4, iclass 11, count 0 2006.190.07:34:42.65#ibcon#read 4, iclass 11, count 0 2006.190.07:34:42.65#ibcon#about to read 5, iclass 11, count 0 2006.190.07:34:42.65#ibcon#read 5, iclass 11, count 0 2006.190.07:34:42.65#ibcon#about to read 6, iclass 11, count 0 2006.190.07:34:42.65#ibcon#read 6, iclass 11, count 0 2006.190.07:34:42.65#ibcon#end of sib2, iclass 11, count 0 2006.190.07:34:42.65#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:34:42.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:34:42.65#ibcon#[27=USB\r\n] 2006.190.07:34:42.65#ibcon#*before write, iclass 11, count 0 2006.190.07:34:42.65#ibcon#enter sib2, iclass 11, count 0 2006.190.07:34:42.65#ibcon#flushed, iclass 11, count 0 2006.190.07:34:42.65#ibcon#about to write, iclass 11, count 0 2006.190.07:34:42.65#ibcon#wrote, iclass 11, count 0 2006.190.07:34:42.65#ibcon#about to read 3, iclass 11, count 0 2006.190.07:34:42.68#ibcon#read 3, iclass 11, count 0 2006.190.07:34:42.68#ibcon#about to read 4, iclass 11, count 0 2006.190.07:34:42.68#ibcon#read 4, iclass 11, count 0 2006.190.07:34:42.68#ibcon#about to read 5, iclass 11, count 0 2006.190.07:34:42.68#ibcon#read 5, iclass 11, count 0 2006.190.07:34:42.68#ibcon#about to read 6, iclass 11, count 0 2006.190.07:34:42.68#ibcon#read 6, iclass 11, count 0 2006.190.07:34:42.68#ibcon#end of sib2, iclass 11, count 0 2006.190.07:34:42.68#ibcon#*after write, iclass 11, count 0 2006.190.07:34:42.68#ibcon#*before return 0, iclass 11, count 0 2006.190.07:34:42.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:42.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:34:42.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:34:42.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:34:42.68$vc4f8/vabw=wide 2006.190.07:34:42.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.07:34:42.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.07:34:42.68#ibcon#ireg 8 cls_cnt 0 2006.190.07:34:42.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:42.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:42.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:42.68#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:34:42.68#ibcon#first serial, iclass 13, count 0 2006.190.07:34:42.68#ibcon#enter sib2, iclass 13, count 0 2006.190.07:34:42.68#ibcon#flushed, iclass 13, count 0 2006.190.07:34:42.68#ibcon#about to write, iclass 13, count 0 2006.190.07:34:42.68#ibcon#wrote, iclass 13, count 0 2006.190.07:34:42.68#ibcon#about to read 3, iclass 13, count 0 2006.190.07:34:42.70#ibcon#read 3, iclass 13, count 0 2006.190.07:34:42.70#ibcon#about to read 4, iclass 13, count 0 2006.190.07:34:42.70#ibcon#read 4, iclass 13, count 0 2006.190.07:34:42.70#ibcon#about to read 5, iclass 13, count 0 2006.190.07:34:42.70#ibcon#read 5, iclass 13, count 0 2006.190.07:34:42.70#ibcon#about to read 6, iclass 13, count 0 2006.190.07:34:42.70#ibcon#read 6, iclass 13, count 0 2006.190.07:34:42.70#ibcon#end of sib2, iclass 13, count 0 2006.190.07:34:42.70#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:34:42.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:34:42.70#ibcon#[25=BW32\r\n] 2006.190.07:34:42.70#ibcon#*before write, iclass 13, count 0 2006.190.07:34:42.70#ibcon#enter sib2, iclass 13, count 0 2006.190.07:34:42.70#ibcon#flushed, iclass 13, count 0 2006.190.07:34:42.70#ibcon#about to write, iclass 13, count 0 2006.190.07:34:42.70#ibcon#wrote, iclass 13, count 0 2006.190.07:34:42.70#ibcon#about to read 3, iclass 13, count 0 2006.190.07:34:42.73#ibcon#read 3, iclass 13, count 0 2006.190.07:34:42.73#ibcon#about to read 4, iclass 13, count 0 2006.190.07:34:42.73#ibcon#read 4, iclass 13, count 0 2006.190.07:34:42.73#ibcon#about to read 5, iclass 13, count 0 2006.190.07:34:42.73#ibcon#read 5, iclass 13, count 0 2006.190.07:34:42.73#ibcon#about to read 6, iclass 13, count 0 2006.190.07:34:42.73#ibcon#read 6, iclass 13, count 0 2006.190.07:34:42.73#ibcon#end of sib2, iclass 13, count 0 2006.190.07:34:42.73#ibcon#*after write, iclass 13, count 0 2006.190.07:34:42.73#ibcon#*before return 0, iclass 13, count 0 2006.190.07:34:42.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:42.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:34:42.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:34:42.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:34:42.73$vc4f8/vbbw=wide 2006.190.07:34:42.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:34:42.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:34:42.73#ibcon#ireg 8 cls_cnt 0 2006.190.07:34:42.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:34:42.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:34:42.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:34:42.80#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:34:42.80#ibcon#first serial, iclass 15, count 0 2006.190.07:34:42.80#ibcon#enter sib2, iclass 15, count 0 2006.190.07:34:42.80#ibcon#flushed, iclass 15, count 0 2006.190.07:34:42.80#ibcon#about to write, iclass 15, count 0 2006.190.07:34:42.80#ibcon#wrote, iclass 15, count 0 2006.190.07:34:42.80#ibcon#about to read 3, iclass 15, count 0 2006.190.07:34:42.82#ibcon#read 3, iclass 15, count 0 2006.190.07:34:42.82#ibcon#about to read 4, iclass 15, count 0 2006.190.07:34:42.82#ibcon#read 4, iclass 15, count 0 2006.190.07:34:42.82#ibcon#about to read 5, iclass 15, count 0 2006.190.07:34:42.82#ibcon#read 5, iclass 15, count 0 2006.190.07:34:42.82#ibcon#about to read 6, iclass 15, count 0 2006.190.07:34:42.82#ibcon#read 6, iclass 15, count 0 2006.190.07:34:42.82#ibcon#end of sib2, iclass 15, count 0 2006.190.07:34:42.82#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:34:42.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:34:42.82#ibcon#[27=BW32\r\n] 2006.190.07:34:42.82#ibcon#*before write, iclass 15, count 0 2006.190.07:34:42.82#ibcon#enter sib2, iclass 15, count 0 2006.190.07:34:42.82#ibcon#flushed, iclass 15, count 0 2006.190.07:34:42.82#ibcon#about to write, iclass 15, count 0 2006.190.07:34:42.82#ibcon#wrote, iclass 15, count 0 2006.190.07:34:42.82#ibcon#about to read 3, iclass 15, count 0 2006.190.07:34:42.85#ibcon#read 3, iclass 15, count 0 2006.190.07:34:42.85#ibcon#about to read 4, iclass 15, count 0 2006.190.07:34:42.85#ibcon#read 4, iclass 15, count 0 2006.190.07:34:42.85#ibcon#about to read 5, iclass 15, count 0 2006.190.07:34:42.85#ibcon#read 5, iclass 15, count 0 2006.190.07:34:42.85#ibcon#about to read 6, iclass 15, count 0 2006.190.07:34:42.85#ibcon#read 6, iclass 15, count 0 2006.190.07:34:42.85#ibcon#end of sib2, iclass 15, count 0 2006.190.07:34:42.85#ibcon#*after write, iclass 15, count 0 2006.190.07:34:42.85#ibcon#*before return 0, iclass 15, count 0 2006.190.07:34:42.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:34:42.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:34:42.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:34:42.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:34:42.85$4f8m12a/ifd4f 2006.190.07:34:42.85$ifd4f/lo= 2006.190.07:34:42.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:34:42.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:34:42.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:34:42.85$ifd4f/patch= 2006.190.07:34:42.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:34:42.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:34:42.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:34:42.85$4f8m12a/"form=m,16.000,1:2 2006.190.07:34:42.85$4f8m12a/"tpicd 2006.190.07:34:42.85$4f8m12a/echo=off 2006.190.07:34:42.85$4f8m12a/xlog=off 2006.190.07:34:42.85:!2006.190.07:35:10 2006.190.07:34:56.14#trakl#Source acquired 2006.190.07:34:58.14#flagr#flagr/antenna,acquired 2006.190.07:35:10.00:preob 2006.190.07:35:11.14/onsource/TRACKING 2006.190.07:35:11.14:!2006.190.07:35:20 2006.190.07:35:20.00:data_valid=on 2006.190.07:35:20.00:midob 2006.190.07:35:20.14/onsource/TRACKING 2006.190.07:35:20.14/wx/24.56,1012.2,100 2006.190.07:35:20.30/cable/+6.4696E-03 2006.190.07:35:21.39/va/01,08,usb,yes,32,34 2006.190.07:35:21.39/va/02,07,usb,yes,33,34 2006.190.07:35:21.39/va/03,06,usb,yes,35,35 2006.190.07:35:21.39/va/04,07,usb,yes,34,36 2006.190.07:35:21.39/va/05,07,usb,yes,37,39 2006.190.07:35:21.39/va/06,06,usb,yes,36,36 2006.190.07:35:21.39/va/07,06,usb,yes,36,36 2006.190.07:35:21.39/va/08,06,usb,yes,39,38 2006.190.07:35:21.62/valo/01,532.99,yes,locked 2006.190.07:35:21.62/valo/02,572.99,yes,locked 2006.190.07:35:21.62/valo/03,672.99,yes,locked 2006.190.07:35:21.62/valo/04,832.99,yes,locked 2006.190.07:35:21.62/valo/05,652.99,yes,locked 2006.190.07:35:21.62/valo/06,772.99,yes,locked 2006.190.07:35:21.62/valo/07,832.99,yes,locked 2006.190.07:35:21.62/valo/08,852.99,yes,locked 2006.190.07:35:22.71/vb/01,04,usb,yes,29,27 2006.190.07:35:22.71/vb/02,04,usb,yes,31,32 2006.190.07:35:22.71/vb/03,04,usb,yes,27,31 2006.190.07:35:22.71/vb/04,04,usb,yes,28,28 2006.190.07:35:22.71/vb/05,04,usb,yes,26,30 2006.190.07:35:22.71/vb/06,04,usb,yes,27,30 2006.190.07:35:22.71/vb/07,04,usb,yes,29,29 2006.190.07:35:22.71/vb/08,04,usb,yes,27,30 2006.190.07:35:22.94/vblo/01,632.99,yes,locked 2006.190.07:35:22.94/vblo/02,640.99,yes,locked 2006.190.07:35:22.94/vblo/03,656.99,yes,locked 2006.190.07:35:22.94/vblo/04,712.99,yes,locked 2006.190.07:35:22.94/vblo/05,744.99,yes,locked 2006.190.07:35:22.94/vblo/06,752.99,yes,locked 2006.190.07:35:22.94/vblo/07,734.99,yes,locked 2006.190.07:35:22.94/vblo/08,744.99,yes,locked 2006.190.07:35:23.09/vabw/8 2006.190.07:35:23.24/vbbw/8 2006.190.07:35:23.33/xfe/off,on,15.2 2006.190.07:35:23.70/ifatt/23,28,28,28 2006.190.07:35:24.07/fmout-gps/S +2.82E-07 2006.190.07:35:24.14:!2006.190.07:36:20 2006.190.07:36:20.01:data_valid=off 2006.190.07:36:20.02:postob 2006.190.07:36:20.09/cable/+6.4708E-03 2006.190.07:36:20.10/wx/24.55,1012.2,100 2006.190.07:36:21.08/fmout-gps/S +2.82E-07 2006.190.07:36:21.08:scan_name=190-0737,k06190,60 2006.190.07:36:21.09:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.190.07:36:21.14#flagr#flagr/antenna,new-source 2006.190.07:36:22.14:checkk5 2006.190.07:36:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:36:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:36:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:36:23.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:36:24.04/chk_obsdata//k5ts1/T1900735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:36:24.42/chk_obsdata//k5ts2/T1900735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:36:24.80/chk_obsdata//k5ts3/T1900735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:36:25.18/chk_obsdata//k5ts4/T1900735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:36:25.88/k5log//k5ts1_log_newline 2006.190.07:36:26.58/k5log//k5ts2_log_newline 2006.190.07:36:27.28/k5log//k5ts3_log_newline 2006.190.07:36:27.97/k5log//k5ts4_log_newline 2006.190.07:36:28.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:36:28.00:4f8m12a=1 2006.190.07:36:28.00$4f8m12a/echo=on 2006.190.07:36:28.00$4f8m12a/pcalon 2006.190.07:36:28.00$pcalon/"no phase cal control is implemented here 2006.190.07:36:28.00$4f8m12a/"tpicd=stop 2006.190.07:36:28.00$4f8m12a/vc4f8 2006.190.07:36:28.00$vc4f8/valo=1,532.99 2006.190.07:36:28.01#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.07:36:28.01#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.07:36:28.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:28.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:28.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:28.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:28.01#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:36:28.01#ibcon#first serial, iclass 22, count 0 2006.190.07:36:28.01#ibcon#enter sib2, iclass 22, count 0 2006.190.07:36:28.01#ibcon#flushed, iclass 22, count 0 2006.190.07:36:28.01#ibcon#about to write, iclass 22, count 0 2006.190.07:36:28.01#ibcon#wrote, iclass 22, count 0 2006.190.07:36:28.01#ibcon#about to read 3, iclass 22, count 0 2006.190.07:36:28.05#ibcon#read 3, iclass 22, count 0 2006.190.07:36:28.05#ibcon#about to read 4, iclass 22, count 0 2006.190.07:36:28.05#ibcon#read 4, iclass 22, count 0 2006.190.07:36:28.05#ibcon#about to read 5, iclass 22, count 0 2006.190.07:36:28.05#ibcon#read 5, iclass 22, count 0 2006.190.07:36:28.05#ibcon#about to read 6, iclass 22, count 0 2006.190.07:36:28.05#ibcon#read 6, iclass 22, count 0 2006.190.07:36:28.05#ibcon#end of sib2, iclass 22, count 0 2006.190.07:36:28.05#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:36:28.05#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:36:28.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:36:28.05#ibcon#*before write, iclass 22, count 0 2006.190.07:36:28.05#ibcon#enter sib2, iclass 22, count 0 2006.190.07:36:28.05#ibcon#flushed, iclass 22, count 0 2006.190.07:36:28.05#ibcon#about to write, iclass 22, count 0 2006.190.07:36:28.05#ibcon#wrote, iclass 22, count 0 2006.190.07:36:28.05#ibcon#about to read 3, iclass 22, count 0 2006.190.07:36:28.10#ibcon#read 3, iclass 22, count 0 2006.190.07:36:28.10#ibcon#about to read 4, iclass 22, count 0 2006.190.07:36:28.10#ibcon#read 4, iclass 22, count 0 2006.190.07:36:28.10#ibcon#about to read 5, iclass 22, count 0 2006.190.07:36:28.10#ibcon#read 5, iclass 22, count 0 2006.190.07:36:28.10#ibcon#about to read 6, iclass 22, count 0 2006.190.07:36:28.10#ibcon#read 6, iclass 22, count 0 2006.190.07:36:28.10#ibcon#end of sib2, iclass 22, count 0 2006.190.07:36:28.10#ibcon#*after write, iclass 22, count 0 2006.190.07:36:28.10#ibcon#*before return 0, iclass 22, count 0 2006.190.07:36:28.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:28.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:28.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:36:28.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:36:28.10$vc4f8/va=1,8 2006.190.07:36:28.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.07:36:28.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.07:36:28.10#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:28.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:36:28.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:36:28.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:36:28.10#ibcon#enter wrdev, iclass 24, count 2 2006.190.07:36:28.10#ibcon#first serial, iclass 24, count 2 2006.190.07:36:28.10#ibcon#enter sib2, iclass 24, count 2 2006.190.07:36:28.10#ibcon#flushed, iclass 24, count 2 2006.190.07:36:28.10#ibcon#about to write, iclass 24, count 2 2006.190.07:36:28.10#ibcon#wrote, iclass 24, count 2 2006.190.07:36:28.10#ibcon#about to read 3, iclass 24, count 2 2006.190.07:36:28.12#ibcon#read 3, iclass 24, count 2 2006.190.07:36:28.12#ibcon#about to read 4, iclass 24, count 2 2006.190.07:36:28.12#ibcon#read 4, iclass 24, count 2 2006.190.07:36:28.12#ibcon#about to read 5, iclass 24, count 2 2006.190.07:36:28.12#ibcon#read 5, iclass 24, count 2 2006.190.07:36:28.12#ibcon#about to read 6, iclass 24, count 2 2006.190.07:36:28.12#ibcon#read 6, iclass 24, count 2 2006.190.07:36:28.12#ibcon#end of sib2, iclass 24, count 2 2006.190.07:36:28.12#ibcon#*mode == 0, iclass 24, count 2 2006.190.07:36:28.12#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.07:36:28.12#ibcon#[25=AT01-08\r\n] 2006.190.07:36:28.12#ibcon#*before write, iclass 24, count 2 2006.190.07:36:28.12#ibcon#enter sib2, iclass 24, count 2 2006.190.07:36:28.12#ibcon#flushed, iclass 24, count 2 2006.190.07:36:28.12#ibcon#about to write, iclass 24, count 2 2006.190.07:36:28.12#ibcon#wrote, iclass 24, count 2 2006.190.07:36:28.12#ibcon#about to read 3, iclass 24, count 2 2006.190.07:36:28.15#ibcon#read 3, iclass 24, count 2 2006.190.07:36:28.15#ibcon#about to read 4, iclass 24, count 2 2006.190.07:36:28.15#ibcon#read 4, iclass 24, count 2 2006.190.07:36:28.15#ibcon#about to read 5, iclass 24, count 2 2006.190.07:36:28.15#ibcon#read 5, iclass 24, count 2 2006.190.07:36:28.15#ibcon#about to read 6, iclass 24, count 2 2006.190.07:36:28.15#ibcon#read 6, iclass 24, count 2 2006.190.07:36:28.15#ibcon#end of sib2, iclass 24, count 2 2006.190.07:36:28.15#ibcon#*after write, iclass 24, count 2 2006.190.07:36:28.15#ibcon#*before return 0, iclass 24, count 2 2006.190.07:36:28.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:36:28.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:36:28.15#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.07:36:28.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:28.15#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:36:28.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:36:28.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:36:28.27#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:36:28.27#ibcon#first serial, iclass 24, count 0 2006.190.07:36:28.27#ibcon#enter sib2, iclass 24, count 0 2006.190.07:36:28.27#ibcon#flushed, iclass 24, count 0 2006.190.07:36:28.27#ibcon#about to write, iclass 24, count 0 2006.190.07:36:28.27#ibcon#wrote, iclass 24, count 0 2006.190.07:36:28.27#ibcon#about to read 3, iclass 24, count 0 2006.190.07:36:28.29#ibcon#read 3, iclass 24, count 0 2006.190.07:36:28.29#ibcon#about to read 4, iclass 24, count 0 2006.190.07:36:28.29#ibcon#read 4, iclass 24, count 0 2006.190.07:36:28.29#ibcon#about to read 5, iclass 24, count 0 2006.190.07:36:28.29#ibcon#read 5, iclass 24, count 0 2006.190.07:36:28.29#ibcon#about to read 6, iclass 24, count 0 2006.190.07:36:28.29#ibcon#read 6, iclass 24, count 0 2006.190.07:36:28.29#ibcon#end of sib2, iclass 24, count 0 2006.190.07:36:28.29#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:36:28.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:36:28.29#ibcon#[25=USB\r\n] 2006.190.07:36:28.29#ibcon#*before write, iclass 24, count 0 2006.190.07:36:28.29#ibcon#enter sib2, iclass 24, count 0 2006.190.07:36:28.29#ibcon#flushed, iclass 24, count 0 2006.190.07:36:28.29#ibcon#about to write, iclass 24, count 0 2006.190.07:36:28.29#ibcon#wrote, iclass 24, count 0 2006.190.07:36:28.29#ibcon#about to read 3, iclass 24, count 0 2006.190.07:36:28.32#ibcon#read 3, iclass 24, count 0 2006.190.07:36:28.32#ibcon#about to read 4, iclass 24, count 0 2006.190.07:36:28.32#ibcon#read 4, iclass 24, count 0 2006.190.07:36:28.32#ibcon#about to read 5, iclass 24, count 0 2006.190.07:36:28.32#ibcon#read 5, iclass 24, count 0 2006.190.07:36:28.32#ibcon#about to read 6, iclass 24, count 0 2006.190.07:36:28.32#ibcon#read 6, iclass 24, count 0 2006.190.07:36:28.32#ibcon#end of sib2, iclass 24, count 0 2006.190.07:36:28.32#ibcon#*after write, iclass 24, count 0 2006.190.07:36:28.32#ibcon#*before return 0, iclass 24, count 0 2006.190.07:36:28.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:36:28.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:36:28.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:36:28.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:36:28.32$vc4f8/valo=2,572.99 2006.190.07:36:28.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.07:36:28.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.07:36:28.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:28.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:36:28.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:36:28.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:36:28.32#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:36:28.32#ibcon#first serial, iclass 26, count 0 2006.190.07:36:28.32#ibcon#enter sib2, iclass 26, count 0 2006.190.07:36:28.32#ibcon#flushed, iclass 26, count 0 2006.190.07:36:28.32#ibcon#about to write, iclass 26, count 0 2006.190.07:36:28.32#ibcon#wrote, iclass 26, count 0 2006.190.07:36:28.32#ibcon#about to read 3, iclass 26, count 0 2006.190.07:36:28.34#ibcon#read 3, iclass 26, count 0 2006.190.07:36:28.34#ibcon#about to read 4, iclass 26, count 0 2006.190.07:36:28.34#ibcon#read 4, iclass 26, count 0 2006.190.07:36:28.34#ibcon#about to read 5, iclass 26, count 0 2006.190.07:36:28.34#ibcon#read 5, iclass 26, count 0 2006.190.07:36:28.34#ibcon#about to read 6, iclass 26, count 0 2006.190.07:36:28.34#ibcon#read 6, iclass 26, count 0 2006.190.07:36:28.34#ibcon#end of sib2, iclass 26, count 0 2006.190.07:36:28.34#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:36:28.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:36:28.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:36:28.34#ibcon#*before write, iclass 26, count 0 2006.190.07:36:28.34#ibcon#enter sib2, iclass 26, count 0 2006.190.07:36:28.34#ibcon#flushed, iclass 26, count 0 2006.190.07:36:28.34#ibcon#about to write, iclass 26, count 0 2006.190.07:36:28.34#ibcon#wrote, iclass 26, count 0 2006.190.07:36:28.34#ibcon#about to read 3, iclass 26, count 0 2006.190.07:36:28.38#ibcon#read 3, iclass 26, count 0 2006.190.07:36:28.38#ibcon#about to read 4, iclass 26, count 0 2006.190.07:36:28.38#ibcon#read 4, iclass 26, count 0 2006.190.07:36:28.38#ibcon#about to read 5, iclass 26, count 0 2006.190.07:36:28.38#ibcon#read 5, iclass 26, count 0 2006.190.07:36:28.38#ibcon#about to read 6, iclass 26, count 0 2006.190.07:36:28.38#ibcon#read 6, iclass 26, count 0 2006.190.07:36:28.38#ibcon#end of sib2, iclass 26, count 0 2006.190.07:36:28.38#ibcon#*after write, iclass 26, count 0 2006.190.07:36:28.38#ibcon#*before return 0, iclass 26, count 0 2006.190.07:36:28.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:36:28.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:36:28.38#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:36:28.38#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:36:28.38$vc4f8/va=2,7 2006.190.07:36:28.38#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.07:36:28.38#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.07:36:28.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:28.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:36:28.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:36:28.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:36:28.44#ibcon#enter wrdev, iclass 28, count 2 2006.190.07:36:28.44#ibcon#first serial, iclass 28, count 2 2006.190.07:36:28.44#ibcon#enter sib2, iclass 28, count 2 2006.190.07:36:28.44#ibcon#flushed, iclass 28, count 2 2006.190.07:36:28.44#ibcon#about to write, iclass 28, count 2 2006.190.07:36:28.44#ibcon#wrote, iclass 28, count 2 2006.190.07:36:28.44#ibcon#about to read 3, iclass 28, count 2 2006.190.07:36:28.46#ibcon#read 3, iclass 28, count 2 2006.190.07:36:28.46#ibcon#about to read 4, iclass 28, count 2 2006.190.07:36:28.46#ibcon#read 4, iclass 28, count 2 2006.190.07:36:28.46#ibcon#about to read 5, iclass 28, count 2 2006.190.07:36:28.46#ibcon#read 5, iclass 28, count 2 2006.190.07:36:28.46#ibcon#about to read 6, iclass 28, count 2 2006.190.07:36:28.46#ibcon#read 6, iclass 28, count 2 2006.190.07:36:28.46#ibcon#end of sib2, iclass 28, count 2 2006.190.07:36:28.46#ibcon#*mode == 0, iclass 28, count 2 2006.190.07:36:28.46#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.07:36:28.46#ibcon#[25=AT02-07\r\n] 2006.190.07:36:28.46#ibcon#*before write, iclass 28, count 2 2006.190.07:36:28.46#ibcon#enter sib2, iclass 28, count 2 2006.190.07:36:28.46#ibcon#flushed, iclass 28, count 2 2006.190.07:36:28.46#ibcon#about to write, iclass 28, count 2 2006.190.07:36:28.46#ibcon#wrote, iclass 28, count 2 2006.190.07:36:28.46#ibcon#about to read 3, iclass 28, count 2 2006.190.07:36:28.49#ibcon#read 3, iclass 28, count 2 2006.190.07:36:28.49#ibcon#about to read 4, iclass 28, count 2 2006.190.07:36:28.49#ibcon#read 4, iclass 28, count 2 2006.190.07:36:28.49#ibcon#about to read 5, iclass 28, count 2 2006.190.07:36:28.49#ibcon#read 5, iclass 28, count 2 2006.190.07:36:28.49#ibcon#about to read 6, iclass 28, count 2 2006.190.07:36:28.49#ibcon#read 6, iclass 28, count 2 2006.190.07:36:28.49#ibcon#end of sib2, iclass 28, count 2 2006.190.07:36:28.49#ibcon#*after write, iclass 28, count 2 2006.190.07:36:28.49#ibcon#*before return 0, iclass 28, count 2 2006.190.07:36:28.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:36:28.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:36:28.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.07:36:28.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:28.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:36:28.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:36:28.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:36:28.62#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:36:28.62#ibcon#first serial, iclass 28, count 0 2006.190.07:36:28.62#ibcon#enter sib2, iclass 28, count 0 2006.190.07:36:28.62#ibcon#flushed, iclass 28, count 0 2006.190.07:36:28.62#ibcon#about to write, iclass 28, count 0 2006.190.07:36:28.62#ibcon#wrote, iclass 28, count 0 2006.190.07:36:28.62#ibcon#about to read 3, iclass 28, count 0 2006.190.07:36:28.63#ibcon#read 3, iclass 28, count 0 2006.190.07:36:28.63#ibcon#about to read 4, iclass 28, count 0 2006.190.07:36:28.63#ibcon#read 4, iclass 28, count 0 2006.190.07:36:28.63#ibcon#about to read 5, iclass 28, count 0 2006.190.07:36:28.63#ibcon#read 5, iclass 28, count 0 2006.190.07:36:28.63#ibcon#about to read 6, iclass 28, count 0 2006.190.07:36:28.63#ibcon#read 6, iclass 28, count 0 2006.190.07:36:28.63#ibcon#end of sib2, iclass 28, count 0 2006.190.07:36:28.63#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:36:28.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:36:28.63#ibcon#[25=USB\r\n] 2006.190.07:36:28.63#ibcon#*before write, iclass 28, count 0 2006.190.07:36:28.63#ibcon#enter sib2, iclass 28, count 0 2006.190.07:36:28.63#ibcon#flushed, iclass 28, count 0 2006.190.07:36:28.63#ibcon#about to write, iclass 28, count 0 2006.190.07:36:28.63#ibcon#wrote, iclass 28, count 0 2006.190.07:36:28.63#ibcon#about to read 3, iclass 28, count 0 2006.190.07:36:28.66#ibcon#read 3, iclass 28, count 0 2006.190.07:36:28.66#ibcon#about to read 4, iclass 28, count 0 2006.190.07:36:28.66#ibcon#read 4, iclass 28, count 0 2006.190.07:36:28.66#ibcon#about to read 5, iclass 28, count 0 2006.190.07:36:28.66#ibcon#read 5, iclass 28, count 0 2006.190.07:36:28.66#ibcon#about to read 6, iclass 28, count 0 2006.190.07:36:28.66#ibcon#read 6, iclass 28, count 0 2006.190.07:36:28.66#ibcon#end of sib2, iclass 28, count 0 2006.190.07:36:28.66#ibcon#*after write, iclass 28, count 0 2006.190.07:36:28.66#ibcon#*before return 0, iclass 28, count 0 2006.190.07:36:28.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:36:28.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:36:28.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:36:28.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:36:28.66$vc4f8/valo=3,672.99 2006.190.07:36:28.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.07:36:28.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.07:36:28.66#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:28.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:28.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:28.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:28.66#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:36:28.66#ibcon#first serial, iclass 30, count 0 2006.190.07:36:28.66#ibcon#enter sib2, iclass 30, count 0 2006.190.07:36:28.66#ibcon#flushed, iclass 30, count 0 2006.190.07:36:28.66#ibcon#about to write, iclass 30, count 0 2006.190.07:36:28.66#ibcon#wrote, iclass 30, count 0 2006.190.07:36:28.66#ibcon#about to read 3, iclass 30, count 0 2006.190.07:36:28.68#ibcon#read 3, iclass 30, count 0 2006.190.07:36:28.68#ibcon#about to read 4, iclass 30, count 0 2006.190.07:36:28.68#ibcon#read 4, iclass 30, count 0 2006.190.07:36:28.68#ibcon#about to read 5, iclass 30, count 0 2006.190.07:36:28.68#ibcon#read 5, iclass 30, count 0 2006.190.07:36:28.68#ibcon#about to read 6, iclass 30, count 0 2006.190.07:36:28.68#ibcon#read 6, iclass 30, count 0 2006.190.07:36:28.68#ibcon#end of sib2, iclass 30, count 0 2006.190.07:36:28.68#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:36:28.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:36:28.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:36:28.68#ibcon#*before write, iclass 30, count 0 2006.190.07:36:28.68#ibcon#enter sib2, iclass 30, count 0 2006.190.07:36:28.68#ibcon#flushed, iclass 30, count 0 2006.190.07:36:28.68#ibcon#about to write, iclass 30, count 0 2006.190.07:36:28.68#ibcon#wrote, iclass 30, count 0 2006.190.07:36:28.68#ibcon#about to read 3, iclass 30, count 0 2006.190.07:36:28.72#ibcon#read 3, iclass 30, count 0 2006.190.07:36:28.72#ibcon#about to read 4, iclass 30, count 0 2006.190.07:36:28.72#ibcon#read 4, iclass 30, count 0 2006.190.07:36:28.72#ibcon#about to read 5, iclass 30, count 0 2006.190.07:36:28.72#ibcon#read 5, iclass 30, count 0 2006.190.07:36:28.72#ibcon#about to read 6, iclass 30, count 0 2006.190.07:36:28.72#ibcon#read 6, iclass 30, count 0 2006.190.07:36:28.72#ibcon#end of sib2, iclass 30, count 0 2006.190.07:36:28.72#ibcon#*after write, iclass 30, count 0 2006.190.07:36:28.72#ibcon#*before return 0, iclass 30, count 0 2006.190.07:36:28.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:28.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:28.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:36:28.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:36:28.72$vc4f8/va=3,6 2006.190.07:36:28.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.07:36:28.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.07:36:28.72#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:28.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:28.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:28.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:28.78#ibcon#enter wrdev, iclass 32, count 2 2006.190.07:36:28.78#ibcon#first serial, iclass 32, count 2 2006.190.07:36:28.78#ibcon#enter sib2, iclass 32, count 2 2006.190.07:36:28.78#ibcon#flushed, iclass 32, count 2 2006.190.07:36:28.78#ibcon#about to write, iclass 32, count 2 2006.190.07:36:28.78#ibcon#wrote, iclass 32, count 2 2006.190.07:36:28.78#ibcon#about to read 3, iclass 32, count 2 2006.190.07:36:28.80#ibcon#read 3, iclass 32, count 2 2006.190.07:36:28.80#ibcon#about to read 4, iclass 32, count 2 2006.190.07:36:28.80#ibcon#read 4, iclass 32, count 2 2006.190.07:36:28.80#ibcon#about to read 5, iclass 32, count 2 2006.190.07:36:28.80#ibcon#read 5, iclass 32, count 2 2006.190.07:36:28.80#ibcon#about to read 6, iclass 32, count 2 2006.190.07:36:28.80#ibcon#read 6, iclass 32, count 2 2006.190.07:36:28.80#ibcon#end of sib2, iclass 32, count 2 2006.190.07:36:28.80#ibcon#*mode == 0, iclass 32, count 2 2006.190.07:36:28.80#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.07:36:28.80#ibcon#[25=AT03-06\r\n] 2006.190.07:36:28.80#ibcon#*before write, iclass 32, count 2 2006.190.07:36:28.80#ibcon#enter sib2, iclass 32, count 2 2006.190.07:36:28.80#ibcon#flushed, iclass 32, count 2 2006.190.07:36:28.80#ibcon#about to write, iclass 32, count 2 2006.190.07:36:28.80#ibcon#wrote, iclass 32, count 2 2006.190.07:36:28.80#ibcon#about to read 3, iclass 32, count 2 2006.190.07:36:28.83#ibcon#read 3, iclass 32, count 2 2006.190.07:36:28.83#ibcon#about to read 4, iclass 32, count 2 2006.190.07:36:28.83#ibcon#read 4, iclass 32, count 2 2006.190.07:36:28.83#ibcon#about to read 5, iclass 32, count 2 2006.190.07:36:28.83#ibcon#read 5, iclass 32, count 2 2006.190.07:36:28.83#ibcon#about to read 6, iclass 32, count 2 2006.190.07:36:28.83#ibcon#read 6, iclass 32, count 2 2006.190.07:36:28.83#ibcon#end of sib2, iclass 32, count 2 2006.190.07:36:28.83#ibcon#*after write, iclass 32, count 2 2006.190.07:36:28.83#ibcon#*before return 0, iclass 32, count 2 2006.190.07:36:28.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:28.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:28.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.07:36:28.83#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:28.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:28.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:28.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:28.95#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:36:28.95#ibcon#first serial, iclass 32, count 0 2006.190.07:36:28.95#ibcon#enter sib2, iclass 32, count 0 2006.190.07:36:28.95#ibcon#flushed, iclass 32, count 0 2006.190.07:36:28.95#ibcon#about to write, iclass 32, count 0 2006.190.07:36:28.95#ibcon#wrote, iclass 32, count 0 2006.190.07:36:28.95#ibcon#about to read 3, iclass 32, count 0 2006.190.07:36:28.97#ibcon#read 3, iclass 32, count 0 2006.190.07:36:28.97#ibcon#about to read 4, iclass 32, count 0 2006.190.07:36:28.97#ibcon#read 4, iclass 32, count 0 2006.190.07:36:28.97#ibcon#about to read 5, iclass 32, count 0 2006.190.07:36:28.97#ibcon#read 5, iclass 32, count 0 2006.190.07:36:28.97#ibcon#about to read 6, iclass 32, count 0 2006.190.07:36:28.97#ibcon#read 6, iclass 32, count 0 2006.190.07:36:28.97#ibcon#end of sib2, iclass 32, count 0 2006.190.07:36:28.97#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:36:28.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:36:28.97#ibcon#[25=USB\r\n] 2006.190.07:36:28.97#ibcon#*before write, iclass 32, count 0 2006.190.07:36:28.97#ibcon#enter sib2, iclass 32, count 0 2006.190.07:36:28.97#ibcon#flushed, iclass 32, count 0 2006.190.07:36:28.97#ibcon#about to write, iclass 32, count 0 2006.190.07:36:28.97#ibcon#wrote, iclass 32, count 0 2006.190.07:36:28.97#ibcon#about to read 3, iclass 32, count 0 2006.190.07:36:29.00#ibcon#read 3, iclass 32, count 0 2006.190.07:36:29.00#ibcon#about to read 4, iclass 32, count 0 2006.190.07:36:29.00#ibcon#read 4, iclass 32, count 0 2006.190.07:36:29.00#ibcon#about to read 5, iclass 32, count 0 2006.190.07:36:29.00#ibcon#read 5, iclass 32, count 0 2006.190.07:36:29.00#ibcon#about to read 6, iclass 32, count 0 2006.190.07:36:29.00#ibcon#read 6, iclass 32, count 0 2006.190.07:36:29.00#ibcon#end of sib2, iclass 32, count 0 2006.190.07:36:29.00#ibcon#*after write, iclass 32, count 0 2006.190.07:36:29.00#ibcon#*before return 0, iclass 32, count 0 2006.190.07:36:29.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:29.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:29.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:36:29.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:36:29.00$vc4f8/valo=4,832.99 2006.190.07:36:29.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.07:36:29.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.07:36:29.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:29.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:29.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:29.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:29.00#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:36:29.00#ibcon#first serial, iclass 34, count 0 2006.190.07:36:29.00#ibcon#enter sib2, iclass 34, count 0 2006.190.07:36:29.00#ibcon#flushed, iclass 34, count 0 2006.190.07:36:29.00#ibcon#about to write, iclass 34, count 0 2006.190.07:36:29.00#ibcon#wrote, iclass 34, count 0 2006.190.07:36:29.00#ibcon#about to read 3, iclass 34, count 0 2006.190.07:36:29.02#ibcon#read 3, iclass 34, count 0 2006.190.07:36:29.02#ibcon#about to read 4, iclass 34, count 0 2006.190.07:36:29.02#ibcon#read 4, iclass 34, count 0 2006.190.07:36:29.02#ibcon#about to read 5, iclass 34, count 0 2006.190.07:36:29.02#ibcon#read 5, iclass 34, count 0 2006.190.07:36:29.02#ibcon#about to read 6, iclass 34, count 0 2006.190.07:36:29.02#ibcon#read 6, iclass 34, count 0 2006.190.07:36:29.02#ibcon#end of sib2, iclass 34, count 0 2006.190.07:36:29.02#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:36:29.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:36:29.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:36:29.02#ibcon#*before write, iclass 34, count 0 2006.190.07:36:29.02#ibcon#enter sib2, iclass 34, count 0 2006.190.07:36:29.02#ibcon#flushed, iclass 34, count 0 2006.190.07:36:29.02#ibcon#about to write, iclass 34, count 0 2006.190.07:36:29.02#ibcon#wrote, iclass 34, count 0 2006.190.07:36:29.02#ibcon#about to read 3, iclass 34, count 0 2006.190.07:36:29.06#ibcon#read 3, iclass 34, count 0 2006.190.07:36:29.06#ibcon#about to read 4, iclass 34, count 0 2006.190.07:36:29.06#ibcon#read 4, iclass 34, count 0 2006.190.07:36:29.06#ibcon#about to read 5, iclass 34, count 0 2006.190.07:36:29.06#ibcon#read 5, iclass 34, count 0 2006.190.07:36:29.06#ibcon#about to read 6, iclass 34, count 0 2006.190.07:36:29.06#ibcon#read 6, iclass 34, count 0 2006.190.07:36:29.06#ibcon#end of sib2, iclass 34, count 0 2006.190.07:36:29.06#ibcon#*after write, iclass 34, count 0 2006.190.07:36:29.06#ibcon#*before return 0, iclass 34, count 0 2006.190.07:36:29.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:29.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:29.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:36:29.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:36:29.06$vc4f8/va=4,7 2006.190.07:36:29.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.07:36:29.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.07:36:29.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:29.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:29.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:29.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:29.12#ibcon#enter wrdev, iclass 36, count 2 2006.190.07:36:29.12#ibcon#first serial, iclass 36, count 2 2006.190.07:36:29.12#ibcon#enter sib2, iclass 36, count 2 2006.190.07:36:29.12#ibcon#flushed, iclass 36, count 2 2006.190.07:36:29.12#ibcon#about to write, iclass 36, count 2 2006.190.07:36:29.12#ibcon#wrote, iclass 36, count 2 2006.190.07:36:29.12#ibcon#about to read 3, iclass 36, count 2 2006.190.07:36:29.14#ibcon#read 3, iclass 36, count 2 2006.190.07:36:29.14#ibcon#about to read 4, iclass 36, count 2 2006.190.07:36:29.14#ibcon#read 4, iclass 36, count 2 2006.190.07:36:29.14#ibcon#about to read 5, iclass 36, count 2 2006.190.07:36:29.14#ibcon#read 5, iclass 36, count 2 2006.190.07:36:29.14#ibcon#about to read 6, iclass 36, count 2 2006.190.07:36:29.14#ibcon#read 6, iclass 36, count 2 2006.190.07:36:29.14#ibcon#end of sib2, iclass 36, count 2 2006.190.07:36:29.14#ibcon#*mode == 0, iclass 36, count 2 2006.190.07:36:29.14#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.07:36:29.14#ibcon#[25=AT04-07\r\n] 2006.190.07:36:29.14#ibcon#*before write, iclass 36, count 2 2006.190.07:36:29.14#ibcon#enter sib2, iclass 36, count 2 2006.190.07:36:29.14#ibcon#flushed, iclass 36, count 2 2006.190.07:36:29.14#ibcon#about to write, iclass 36, count 2 2006.190.07:36:29.14#ibcon#wrote, iclass 36, count 2 2006.190.07:36:29.14#ibcon#about to read 3, iclass 36, count 2 2006.190.07:36:29.17#ibcon#read 3, iclass 36, count 2 2006.190.07:36:29.17#ibcon#about to read 4, iclass 36, count 2 2006.190.07:36:29.17#ibcon#read 4, iclass 36, count 2 2006.190.07:36:29.17#ibcon#about to read 5, iclass 36, count 2 2006.190.07:36:29.17#ibcon#read 5, iclass 36, count 2 2006.190.07:36:29.17#ibcon#about to read 6, iclass 36, count 2 2006.190.07:36:29.17#ibcon#read 6, iclass 36, count 2 2006.190.07:36:29.17#ibcon#end of sib2, iclass 36, count 2 2006.190.07:36:29.17#ibcon#*after write, iclass 36, count 2 2006.190.07:36:29.17#ibcon#*before return 0, iclass 36, count 2 2006.190.07:36:29.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:29.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:29.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.07:36:29.17#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:29.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:29.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:29.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:29.29#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:36:29.29#ibcon#first serial, iclass 36, count 0 2006.190.07:36:29.29#ibcon#enter sib2, iclass 36, count 0 2006.190.07:36:29.29#ibcon#flushed, iclass 36, count 0 2006.190.07:36:29.29#ibcon#about to write, iclass 36, count 0 2006.190.07:36:29.29#ibcon#wrote, iclass 36, count 0 2006.190.07:36:29.29#ibcon#about to read 3, iclass 36, count 0 2006.190.07:36:29.31#ibcon#read 3, iclass 36, count 0 2006.190.07:36:29.31#ibcon#about to read 4, iclass 36, count 0 2006.190.07:36:29.31#ibcon#read 4, iclass 36, count 0 2006.190.07:36:29.31#ibcon#about to read 5, iclass 36, count 0 2006.190.07:36:29.31#ibcon#read 5, iclass 36, count 0 2006.190.07:36:29.31#ibcon#about to read 6, iclass 36, count 0 2006.190.07:36:29.31#ibcon#read 6, iclass 36, count 0 2006.190.07:36:29.31#ibcon#end of sib2, iclass 36, count 0 2006.190.07:36:29.31#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:36:29.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:36:29.31#ibcon#[25=USB\r\n] 2006.190.07:36:29.31#ibcon#*before write, iclass 36, count 0 2006.190.07:36:29.31#ibcon#enter sib2, iclass 36, count 0 2006.190.07:36:29.31#ibcon#flushed, iclass 36, count 0 2006.190.07:36:29.31#ibcon#about to write, iclass 36, count 0 2006.190.07:36:29.31#ibcon#wrote, iclass 36, count 0 2006.190.07:36:29.31#ibcon#about to read 3, iclass 36, count 0 2006.190.07:36:29.34#ibcon#read 3, iclass 36, count 0 2006.190.07:36:29.34#ibcon#about to read 4, iclass 36, count 0 2006.190.07:36:29.34#ibcon#read 4, iclass 36, count 0 2006.190.07:36:29.34#ibcon#about to read 5, iclass 36, count 0 2006.190.07:36:29.34#ibcon#read 5, iclass 36, count 0 2006.190.07:36:29.34#ibcon#about to read 6, iclass 36, count 0 2006.190.07:36:29.34#ibcon#read 6, iclass 36, count 0 2006.190.07:36:29.34#ibcon#end of sib2, iclass 36, count 0 2006.190.07:36:29.34#ibcon#*after write, iclass 36, count 0 2006.190.07:36:29.34#ibcon#*before return 0, iclass 36, count 0 2006.190.07:36:29.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:29.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:29.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:36:29.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:36:29.34$vc4f8/valo=5,652.99 2006.190.07:36:29.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.07:36:29.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.07:36:29.34#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:29.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:29.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:29.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:29.34#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:36:29.34#ibcon#first serial, iclass 38, count 0 2006.190.07:36:29.34#ibcon#enter sib2, iclass 38, count 0 2006.190.07:36:29.34#ibcon#flushed, iclass 38, count 0 2006.190.07:36:29.34#ibcon#about to write, iclass 38, count 0 2006.190.07:36:29.34#ibcon#wrote, iclass 38, count 0 2006.190.07:36:29.34#ibcon#about to read 3, iclass 38, count 0 2006.190.07:36:29.36#ibcon#read 3, iclass 38, count 0 2006.190.07:36:29.36#ibcon#about to read 4, iclass 38, count 0 2006.190.07:36:29.36#ibcon#read 4, iclass 38, count 0 2006.190.07:36:29.36#ibcon#about to read 5, iclass 38, count 0 2006.190.07:36:29.36#ibcon#read 5, iclass 38, count 0 2006.190.07:36:29.36#ibcon#about to read 6, iclass 38, count 0 2006.190.07:36:29.36#ibcon#read 6, iclass 38, count 0 2006.190.07:36:29.36#ibcon#end of sib2, iclass 38, count 0 2006.190.07:36:29.36#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:36:29.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:36:29.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:36:29.36#ibcon#*before write, iclass 38, count 0 2006.190.07:36:29.36#ibcon#enter sib2, iclass 38, count 0 2006.190.07:36:29.36#ibcon#flushed, iclass 38, count 0 2006.190.07:36:29.36#ibcon#about to write, iclass 38, count 0 2006.190.07:36:29.36#ibcon#wrote, iclass 38, count 0 2006.190.07:36:29.36#ibcon#about to read 3, iclass 38, count 0 2006.190.07:36:29.40#ibcon#read 3, iclass 38, count 0 2006.190.07:36:29.40#ibcon#about to read 4, iclass 38, count 0 2006.190.07:36:29.40#ibcon#read 4, iclass 38, count 0 2006.190.07:36:29.40#ibcon#about to read 5, iclass 38, count 0 2006.190.07:36:29.40#ibcon#read 5, iclass 38, count 0 2006.190.07:36:29.40#ibcon#about to read 6, iclass 38, count 0 2006.190.07:36:29.40#ibcon#read 6, iclass 38, count 0 2006.190.07:36:29.40#ibcon#end of sib2, iclass 38, count 0 2006.190.07:36:29.40#ibcon#*after write, iclass 38, count 0 2006.190.07:36:29.40#ibcon#*before return 0, iclass 38, count 0 2006.190.07:36:29.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:29.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:29.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:36:29.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:36:29.40$vc4f8/va=5,7 2006.190.07:36:29.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.07:36:29.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.07:36:29.40#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:29.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:29.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:29.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:29.46#ibcon#enter wrdev, iclass 40, count 2 2006.190.07:36:29.46#ibcon#first serial, iclass 40, count 2 2006.190.07:36:29.46#ibcon#enter sib2, iclass 40, count 2 2006.190.07:36:29.46#ibcon#flushed, iclass 40, count 2 2006.190.07:36:29.46#ibcon#about to write, iclass 40, count 2 2006.190.07:36:29.46#ibcon#wrote, iclass 40, count 2 2006.190.07:36:29.46#ibcon#about to read 3, iclass 40, count 2 2006.190.07:36:29.48#ibcon#read 3, iclass 40, count 2 2006.190.07:36:29.48#ibcon#about to read 4, iclass 40, count 2 2006.190.07:36:29.48#ibcon#read 4, iclass 40, count 2 2006.190.07:36:29.48#ibcon#about to read 5, iclass 40, count 2 2006.190.07:36:29.48#ibcon#read 5, iclass 40, count 2 2006.190.07:36:29.48#ibcon#about to read 6, iclass 40, count 2 2006.190.07:36:29.48#ibcon#read 6, iclass 40, count 2 2006.190.07:36:29.48#ibcon#end of sib2, iclass 40, count 2 2006.190.07:36:29.48#ibcon#*mode == 0, iclass 40, count 2 2006.190.07:36:29.48#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.07:36:29.48#ibcon#[25=AT05-07\r\n] 2006.190.07:36:29.48#ibcon#*before write, iclass 40, count 2 2006.190.07:36:29.48#ibcon#enter sib2, iclass 40, count 2 2006.190.07:36:29.48#ibcon#flushed, iclass 40, count 2 2006.190.07:36:29.48#ibcon#about to write, iclass 40, count 2 2006.190.07:36:29.48#ibcon#wrote, iclass 40, count 2 2006.190.07:36:29.48#ibcon#about to read 3, iclass 40, count 2 2006.190.07:36:29.51#ibcon#read 3, iclass 40, count 2 2006.190.07:36:29.51#ibcon#about to read 4, iclass 40, count 2 2006.190.07:36:29.51#ibcon#read 4, iclass 40, count 2 2006.190.07:36:29.51#ibcon#about to read 5, iclass 40, count 2 2006.190.07:36:29.51#ibcon#read 5, iclass 40, count 2 2006.190.07:36:29.51#ibcon#about to read 6, iclass 40, count 2 2006.190.07:36:29.51#ibcon#read 6, iclass 40, count 2 2006.190.07:36:29.51#ibcon#end of sib2, iclass 40, count 2 2006.190.07:36:29.51#ibcon#*after write, iclass 40, count 2 2006.190.07:36:29.51#ibcon#*before return 0, iclass 40, count 2 2006.190.07:36:29.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:29.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:29.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.07:36:29.51#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:29.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:29.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:29.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:29.63#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:36:29.63#ibcon#first serial, iclass 40, count 0 2006.190.07:36:29.63#ibcon#enter sib2, iclass 40, count 0 2006.190.07:36:29.63#ibcon#flushed, iclass 40, count 0 2006.190.07:36:29.63#ibcon#about to write, iclass 40, count 0 2006.190.07:36:29.63#ibcon#wrote, iclass 40, count 0 2006.190.07:36:29.63#ibcon#about to read 3, iclass 40, count 0 2006.190.07:36:29.65#ibcon#read 3, iclass 40, count 0 2006.190.07:36:29.65#ibcon#about to read 4, iclass 40, count 0 2006.190.07:36:29.65#ibcon#read 4, iclass 40, count 0 2006.190.07:36:29.65#ibcon#about to read 5, iclass 40, count 0 2006.190.07:36:29.65#ibcon#read 5, iclass 40, count 0 2006.190.07:36:29.65#ibcon#about to read 6, iclass 40, count 0 2006.190.07:36:29.65#ibcon#read 6, iclass 40, count 0 2006.190.07:36:29.65#ibcon#end of sib2, iclass 40, count 0 2006.190.07:36:29.65#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:36:29.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:36:29.65#ibcon#[25=USB\r\n] 2006.190.07:36:29.65#ibcon#*before write, iclass 40, count 0 2006.190.07:36:29.65#ibcon#enter sib2, iclass 40, count 0 2006.190.07:36:29.65#ibcon#flushed, iclass 40, count 0 2006.190.07:36:29.65#ibcon#about to write, iclass 40, count 0 2006.190.07:36:29.65#ibcon#wrote, iclass 40, count 0 2006.190.07:36:29.65#ibcon#about to read 3, iclass 40, count 0 2006.190.07:36:29.68#ibcon#read 3, iclass 40, count 0 2006.190.07:36:29.68#ibcon#about to read 4, iclass 40, count 0 2006.190.07:36:29.68#ibcon#read 4, iclass 40, count 0 2006.190.07:36:29.68#ibcon#about to read 5, iclass 40, count 0 2006.190.07:36:29.68#ibcon#read 5, iclass 40, count 0 2006.190.07:36:29.68#ibcon#about to read 6, iclass 40, count 0 2006.190.07:36:29.68#ibcon#read 6, iclass 40, count 0 2006.190.07:36:29.68#ibcon#end of sib2, iclass 40, count 0 2006.190.07:36:29.68#ibcon#*after write, iclass 40, count 0 2006.190.07:36:29.68#ibcon#*before return 0, iclass 40, count 0 2006.190.07:36:29.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:29.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:29.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:36:29.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:36:29.68$vc4f8/valo=6,772.99 2006.190.07:36:29.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.07:36:29.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.07:36:29.68#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:29.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:29.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:29.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:29.68#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:36:29.68#ibcon#first serial, iclass 4, count 0 2006.190.07:36:29.68#ibcon#enter sib2, iclass 4, count 0 2006.190.07:36:29.68#ibcon#flushed, iclass 4, count 0 2006.190.07:36:29.68#ibcon#about to write, iclass 4, count 0 2006.190.07:36:29.68#ibcon#wrote, iclass 4, count 0 2006.190.07:36:29.68#ibcon#about to read 3, iclass 4, count 0 2006.190.07:36:29.70#ibcon#read 3, iclass 4, count 0 2006.190.07:36:29.70#ibcon#about to read 4, iclass 4, count 0 2006.190.07:36:29.70#ibcon#read 4, iclass 4, count 0 2006.190.07:36:29.70#ibcon#about to read 5, iclass 4, count 0 2006.190.07:36:29.70#ibcon#read 5, iclass 4, count 0 2006.190.07:36:29.70#ibcon#about to read 6, iclass 4, count 0 2006.190.07:36:29.70#ibcon#read 6, iclass 4, count 0 2006.190.07:36:29.70#ibcon#end of sib2, iclass 4, count 0 2006.190.07:36:29.70#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:36:29.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:36:29.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:36:29.70#ibcon#*before write, iclass 4, count 0 2006.190.07:36:29.70#ibcon#enter sib2, iclass 4, count 0 2006.190.07:36:29.70#ibcon#flushed, iclass 4, count 0 2006.190.07:36:29.70#ibcon#about to write, iclass 4, count 0 2006.190.07:36:29.70#ibcon#wrote, iclass 4, count 0 2006.190.07:36:29.70#ibcon#about to read 3, iclass 4, count 0 2006.190.07:36:29.74#ibcon#read 3, iclass 4, count 0 2006.190.07:36:29.74#ibcon#about to read 4, iclass 4, count 0 2006.190.07:36:29.74#ibcon#read 4, iclass 4, count 0 2006.190.07:36:29.74#ibcon#about to read 5, iclass 4, count 0 2006.190.07:36:29.74#ibcon#read 5, iclass 4, count 0 2006.190.07:36:29.74#ibcon#about to read 6, iclass 4, count 0 2006.190.07:36:29.74#ibcon#read 6, iclass 4, count 0 2006.190.07:36:29.74#ibcon#end of sib2, iclass 4, count 0 2006.190.07:36:29.74#ibcon#*after write, iclass 4, count 0 2006.190.07:36:29.74#ibcon#*before return 0, iclass 4, count 0 2006.190.07:36:29.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:29.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:29.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:36:29.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:36:29.74$vc4f8/va=6,6 2006.190.07:36:29.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.07:36:29.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.07:36:29.74#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:29.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:29.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:29.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:29.80#ibcon#enter wrdev, iclass 6, count 2 2006.190.07:36:29.80#ibcon#first serial, iclass 6, count 2 2006.190.07:36:29.80#ibcon#enter sib2, iclass 6, count 2 2006.190.07:36:29.80#ibcon#flushed, iclass 6, count 2 2006.190.07:36:29.80#ibcon#about to write, iclass 6, count 2 2006.190.07:36:29.80#ibcon#wrote, iclass 6, count 2 2006.190.07:36:29.80#ibcon#about to read 3, iclass 6, count 2 2006.190.07:36:29.82#ibcon#read 3, iclass 6, count 2 2006.190.07:36:29.82#ibcon#about to read 4, iclass 6, count 2 2006.190.07:36:29.82#ibcon#read 4, iclass 6, count 2 2006.190.07:36:29.82#ibcon#about to read 5, iclass 6, count 2 2006.190.07:36:29.82#ibcon#read 5, iclass 6, count 2 2006.190.07:36:29.82#ibcon#about to read 6, iclass 6, count 2 2006.190.07:36:29.82#ibcon#read 6, iclass 6, count 2 2006.190.07:36:29.82#ibcon#end of sib2, iclass 6, count 2 2006.190.07:36:29.82#ibcon#*mode == 0, iclass 6, count 2 2006.190.07:36:29.82#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.07:36:29.82#ibcon#[25=AT06-06\r\n] 2006.190.07:36:29.82#ibcon#*before write, iclass 6, count 2 2006.190.07:36:29.82#ibcon#enter sib2, iclass 6, count 2 2006.190.07:36:29.82#ibcon#flushed, iclass 6, count 2 2006.190.07:36:29.82#ibcon#about to write, iclass 6, count 2 2006.190.07:36:29.82#ibcon#wrote, iclass 6, count 2 2006.190.07:36:29.82#ibcon#about to read 3, iclass 6, count 2 2006.190.07:36:29.85#ibcon#read 3, iclass 6, count 2 2006.190.07:36:29.85#ibcon#about to read 4, iclass 6, count 2 2006.190.07:36:29.85#ibcon#read 4, iclass 6, count 2 2006.190.07:36:29.85#ibcon#about to read 5, iclass 6, count 2 2006.190.07:36:29.85#ibcon#read 5, iclass 6, count 2 2006.190.07:36:29.85#ibcon#about to read 6, iclass 6, count 2 2006.190.07:36:29.85#ibcon#read 6, iclass 6, count 2 2006.190.07:36:29.85#ibcon#end of sib2, iclass 6, count 2 2006.190.07:36:29.85#ibcon#*after write, iclass 6, count 2 2006.190.07:36:29.85#ibcon#*before return 0, iclass 6, count 2 2006.190.07:36:29.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:29.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:29.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.07:36:29.85#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:29.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:29.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:29.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:29.97#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:36:29.97#ibcon#first serial, iclass 6, count 0 2006.190.07:36:29.97#ibcon#enter sib2, iclass 6, count 0 2006.190.07:36:29.97#ibcon#flushed, iclass 6, count 0 2006.190.07:36:29.97#ibcon#about to write, iclass 6, count 0 2006.190.07:36:29.97#ibcon#wrote, iclass 6, count 0 2006.190.07:36:29.97#ibcon#about to read 3, iclass 6, count 0 2006.190.07:36:29.99#ibcon#read 3, iclass 6, count 0 2006.190.07:36:29.99#ibcon#about to read 4, iclass 6, count 0 2006.190.07:36:29.99#ibcon#read 4, iclass 6, count 0 2006.190.07:36:29.99#ibcon#about to read 5, iclass 6, count 0 2006.190.07:36:29.99#ibcon#read 5, iclass 6, count 0 2006.190.07:36:29.99#ibcon#about to read 6, iclass 6, count 0 2006.190.07:36:29.99#ibcon#read 6, iclass 6, count 0 2006.190.07:36:29.99#ibcon#end of sib2, iclass 6, count 0 2006.190.07:36:29.99#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:36:29.99#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:36:29.99#ibcon#[25=USB\r\n] 2006.190.07:36:29.99#ibcon#*before write, iclass 6, count 0 2006.190.07:36:29.99#ibcon#enter sib2, iclass 6, count 0 2006.190.07:36:29.99#ibcon#flushed, iclass 6, count 0 2006.190.07:36:29.99#ibcon#about to write, iclass 6, count 0 2006.190.07:36:29.99#ibcon#wrote, iclass 6, count 0 2006.190.07:36:29.99#ibcon#about to read 3, iclass 6, count 0 2006.190.07:36:30.02#ibcon#read 3, iclass 6, count 0 2006.190.07:36:30.02#ibcon#about to read 4, iclass 6, count 0 2006.190.07:36:30.02#ibcon#read 4, iclass 6, count 0 2006.190.07:36:30.02#ibcon#about to read 5, iclass 6, count 0 2006.190.07:36:30.02#ibcon#read 5, iclass 6, count 0 2006.190.07:36:30.02#ibcon#about to read 6, iclass 6, count 0 2006.190.07:36:30.02#ibcon#read 6, iclass 6, count 0 2006.190.07:36:30.02#ibcon#end of sib2, iclass 6, count 0 2006.190.07:36:30.02#ibcon#*after write, iclass 6, count 0 2006.190.07:36:30.02#ibcon#*before return 0, iclass 6, count 0 2006.190.07:36:30.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:30.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:30.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:36:30.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:36:30.02$vc4f8/valo=7,832.99 2006.190.07:36:30.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.07:36:30.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.07:36:30.02#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:30.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:30.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:30.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:30.02#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:36:30.02#ibcon#first serial, iclass 10, count 0 2006.190.07:36:30.02#ibcon#enter sib2, iclass 10, count 0 2006.190.07:36:30.02#ibcon#flushed, iclass 10, count 0 2006.190.07:36:30.02#ibcon#about to write, iclass 10, count 0 2006.190.07:36:30.02#ibcon#wrote, iclass 10, count 0 2006.190.07:36:30.02#ibcon#about to read 3, iclass 10, count 0 2006.190.07:36:30.04#ibcon#read 3, iclass 10, count 0 2006.190.07:36:30.04#ibcon#about to read 4, iclass 10, count 0 2006.190.07:36:30.04#ibcon#read 4, iclass 10, count 0 2006.190.07:36:30.04#ibcon#about to read 5, iclass 10, count 0 2006.190.07:36:30.04#ibcon#read 5, iclass 10, count 0 2006.190.07:36:30.04#ibcon#about to read 6, iclass 10, count 0 2006.190.07:36:30.04#ibcon#read 6, iclass 10, count 0 2006.190.07:36:30.04#ibcon#end of sib2, iclass 10, count 0 2006.190.07:36:30.04#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:36:30.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:36:30.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:36:30.04#ibcon#*before write, iclass 10, count 0 2006.190.07:36:30.04#ibcon#enter sib2, iclass 10, count 0 2006.190.07:36:30.04#ibcon#flushed, iclass 10, count 0 2006.190.07:36:30.04#ibcon#about to write, iclass 10, count 0 2006.190.07:36:30.04#ibcon#wrote, iclass 10, count 0 2006.190.07:36:30.04#ibcon#about to read 3, iclass 10, count 0 2006.190.07:36:30.08#ibcon#read 3, iclass 10, count 0 2006.190.07:36:30.08#ibcon#about to read 4, iclass 10, count 0 2006.190.07:36:30.08#ibcon#read 4, iclass 10, count 0 2006.190.07:36:30.08#ibcon#about to read 5, iclass 10, count 0 2006.190.07:36:30.08#ibcon#read 5, iclass 10, count 0 2006.190.07:36:30.08#ibcon#about to read 6, iclass 10, count 0 2006.190.07:36:30.08#ibcon#read 6, iclass 10, count 0 2006.190.07:36:30.08#ibcon#end of sib2, iclass 10, count 0 2006.190.07:36:30.08#ibcon#*after write, iclass 10, count 0 2006.190.07:36:30.08#ibcon#*before return 0, iclass 10, count 0 2006.190.07:36:30.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:30.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:30.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:36:30.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:36:30.08$vc4f8/va=7,6 2006.190.07:36:30.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.07:36:30.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.07:36:30.08#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:30.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:36:30.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:36:30.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:36:30.14#ibcon#enter wrdev, iclass 12, count 2 2006.190.07:36:30.14#ibcon#first serial, iclass 12, count 2 2006.190.07:36:30.14#ibcon#enter sib2, iclass 12, count 2 2006.190.07:36:30.14#ibcon#flushed, iclass 12, count 2 2006.190.07:36:30.14#ibcon#about to write, iclass 12, count 2 2006.190.07:36:30.14#ibcon#wrote, iclass 12, count 2 2006.190.07:36:30.14#ibcon#about to read 3, iclass 12, count 2 2006.190.07:36:30.16#ibcon#read 3, iclass 12, count 2 2006.190.07:36:30.16#ibcon#about to read 4, iclass 12, count 2 2006.190.07:36:30.16#ibcon#read 4, iclass 12, count 2 2006.190.07:36:30.16#ibcon#about to read 5, iclass 12, count 2 2006.190.07:36:30.16#ibcon#read 5, iclass 12, count 2 2006.190.07:36:30.16#ibcon#about to read 6, iclass 12, count 2 2006.190.07:36:30.16#ibcon#read 6, iclass 12, count 2 2006.190.07:36:30.16#ibcon#end of sib2, iclass 12, count 2 2006.190.07:36:30.16#ibcon#*mode == 0, iclass 12, count 2 2006.190.07:36:30.16#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.07:36:30.16#ibcon#[25=AT07-06\r\n] 2006.190.07:36:30.16#ibcon#*before write, iclass 12, count 2 2006.190.07:36:30.16#ibcon#enter sib2, iclass 12, count 2 2006.190.07:36:30.16#ibcon#flushed, iclass 12, count 2 2006.190.07:36:30.16#ibcon#about to write, iclass 12, count 2 2006.190.07:36:30.16#ibcon#wrote, iclass 12, count 2 2006.190.07:36:30.16#ibcon#about to read 3, iclass 12, count 2 2006.190.07:36:30.19#ibcon#read 3, iclass 12, count 2 2006.190.07:36:30.19#ibcon#about to read 4, iclass 12, count 2 2006.190.07:36:30.19#ibcon#read 4, iclass 12, count 2 2006.190.07:36:30.19#ibcon#about to read 5, iclass 12, count 2 2006.190.07:36:30.19#ibcon#read 5, iclass 12, count 2 2006.190.07:36:30.19#ibcon#about to read 6, iclass 12, count 2 2006.190.07:36:30.19#ibcon#read 6, iclass 12, count 2 2006.190.07:36:30.19#ibcon#end of sib2, iclass 12, count 2 2006.190.07:36:30.19#ibcon#*after write, iclass 12, count 2 2006.190.07:36:30.19#ibcon#*before return 0, iclass 12, count 2 2006.190.07:36:30.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:36:30.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:36:30.19#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.07:36:30.19#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:30.19#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:36:30.31#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:36:30.31#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:36:30.31#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:36:30.31#ibcon#first serial, iclass 12, count 0 2006.190.07:36:30.31#ibcon#enter sib2, iclass 12, count 0 2006.190.07:36:30.31#ibcon#flushed, iclass 12, count 0 2006.190.07:36:30.31#ibcon#about to write, iclass 12, count 0 2006.190.07:36:30.31#ibcon#wrote, iclass 12, count 0 2006.190.07:36:30.31#ibcon#about to read 3, iclass 12, count 0 2006.190.07:36:30.33#ibcon#read 3, iclass 12, count 0 2006.190.07:36:30.33#ibcon#about to read 4, iclass 12, count 0 2006.190.07:36:30.33#ibcon#read 4, iclass 12, count 0 2006.190.07:36:30.33#ibcon#about to read 5, iclass 12, count 0 2006.190.07:36:30.33#ibcon#read 5, iclass 12, count 0 2006.190.07:36:30.33#ibcon#about to read 6, iclass 12, count 0 2006.190.07:36:30.33#ibcon#read 6, iclass 12, count 0 2006.190.07:36:30.33#ibcon#end of sib2, iclass 12, count 0 2006.190.07:36:30.33#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:36:30.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:36:30.33#ibcon#[25=USB\r\n] 2006.190.07:36:30.33#ibcon#*before write, iclass 12, count 0 2006.190.07:36:30.33#ibcon#enter sib2, iclass 12, count 0 2006.190.07:36:30.33#ibcon#flushed, iclass 12, count 0 2006.190.07:36:30.33#ibcon#about to write, iclass 12, count 0 2006.190.07:36:30.33#ibcon#wrote, iclass 12, count 0 2006.190.07:36:30.33#ibcon#about to read 3, iclass 12, count 0 2006.190.07:36:30.36#ibcon#read 3, iclass 12, count 0 2006.190.07:36:30.36#ibcon#about to read 4, iclass 12, count 0 2006.190.07:36:30.36#ibcon#read 4, iclass 12, count 0 2006.190.07:36:30.36#ibcon#about to read 5, iclass 12, count 0 2006.190.07:36:30.36#ibcon#read 5, iclass 12, count 0 2006.190.07:36:30.36#ibcon#about to read 6, iclass 12, count 0 2006.190.07:36:30.36#ibcon#read 6, iclass 12, count 0 2006.190.07:36:30.36#ibcon#end of sib2, iclass 12, count 0 2006.190.07:36:30.36#ibcon#*after write, iclass 12, count 0 2006.190.07:36:30.36#ibcon#*before return 0, iclass 12, count 0 2006.190.07:36:30.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:36:30.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:36:30.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:36:30.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:36:30.36$vc4f8/valo=8,852.99 2006.190.07:36:30.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.07:36:30.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.07:36:30.36#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:30.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:36:30.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:36:30.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:36:30.36#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:36:30.36#ibcon#first serial, iclass 14, count 0 2006.190.07:36:30.36#ibcon#enter sib2, iclass 14, count 0 2006.190.07:36:30.36#ibcon#flushed, iclass 14, count 0 2006.190.07:36:30.36#ibcon#about to write, iclass 14, count 0 2006.190.07:36:30.36#ibcon#wrote, iclass 14, count 0 2006.190.07:36:30.36#ibcon#about to read 3, iclass 14, count 0 2006.190.07:36:30.38#ibcon#read 3, iclass 14, count 0 2006.190.07:36:30.38#ibcon#about to read 4, iclass 14, count 0 2006.190.07:36:30.38#ibcon#read 4, iclass 14, count 0 2006.190.07:36:30.38#ibcon#about to read 5, iclass 14, count 0 2006.190.07:36:30.38#ibcon#read 5, iclass 14, count 0 2006.190.07:36:30.38#ibcon#about to read 6, iclass 14, count 0 2006.190.07:36:30.38#ibcon#read 6, iclass 14, count 0 2006.190.07:36:30.38#ibcon#end of sib2, iclass 14, count 0 2006.190.07:36:30.38#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:36:30.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:36:30.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:36:30.38#ibcon#*before write, iclass 14, count 0 2006.190.07:36:30.38#ibcon#enter sib2, iclass 14, count 0 2006.190.07:36:30.38#ibcon#flushed, iclass 14, count 0 2006.190.07:36:30.38#ibcon#about to write, iclass 14, count 0 2006.190.07:36:30.38#ibcon#wrote, iclass 14, count 0 2006.190.07:36:30.38#ibcon#about to read 3, iclass 14, count 0 2006.190.07:36:30.42#ibcon#read 3, iclass 14, count 0 2006.190.07:36:30.42#ibcon#about to read 4, iclass 14, count 0 2006.190.07:36:30.42#ibcon#read 4, iclass 14, count 0 2006.190.07:36:30.42#ibcon#about to read 5, iclass 14, count 0 2006.190.07:36:30.42#ibcon#read 5, iclass 14, count 0 2006.190.07:36:30.42#ibcon#about to read 6, iclass 14, count 0 2006.190.07:36:30.42#ibcon#read 6, iclass 14, count 0 2006.190.07:36:30.42#ibcon#end of sib2, iclass 14, count 0 2006.190.07:36:30.42#ibcon#*after write, iclass 14, count 0 2006.190.07:36:30.42#ibcon#*before return 0, iclass 14, count 0 2006.190.07:36:30.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:36:30.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:36:30.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:36:30.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:36:30.42$vc4f8/va=8,6 2006.190.07:36:30.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.07:36:30.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.07:36:30.42#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:30.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:36:30.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:36:30.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:36:30.48#ibcon#enter wrdev, iclass 16, count 2 2006.190.07:36:30.48#ibcon#first serial, iclass 16, count 2 2006.190.07:36:30.48#ibcon#enter sib2, iclass 16, count 2 2006.190.07:36:30.48#ibcon#flushed, iclass 16, count 2 2006.190.07:36:30.48#ibcon#about to write, iclass 16, count 2 2006.190.07:36:30.48#ibcon#wrote, iclass 16, count 2 2006.190.07:36:30.48#ibcon#about to read 3, iclass 16, count 2 2006.190.07:36:30.50#ibcon#read 3, iclass 16, count 2 2006.190.07:36:30.50#ibcon#about to read 4, iclass 16, count 2 2006.190.07:36:30.50#ibcon#read 4, iclass 16, count 2 2006.190.07:36:30.50#ibcon#about to read 5, iclass 16, count 2 2006.190.07:36:30.50#ibcon#read 5, iclass 16, count 2 2006.190.07:36:30.50#ibcon#about to read 6, iclass 16, count 2 2006.190.07:36:30.50#ibcon#read 6, iclass 16, count 2 2006.190.07:36:30.50#ibcon#end of sib2, iclass 16, count 2 2006.190.07:36:30.50#ibcon#*mode == 0, iclass 16, count 2 2006.190.07:36:30.50#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.07:36:30.50#ibcon#[25=AT08-06\r\n] 2006.190.07:36:30.50#ibcon#*before write, iclass 16, count 2 2006.190.07:36:30.50#ibcon#enter sib2, iclass 16, count 2 2006.190.07:36:30.50#ibcon#flushed, iclass 16, count 2 2006.190.07:36:30.50#ibcon#about to write, iclass 16, count 2 2006.190.07:36:30.50#ibcon#wrote, iclass 16, count 2 2006.190.07:36:30.50#ibcon#about to read 3, iclass 16, count 2 2006.190.07:36:30.53#ibcon#read 3, iclass 16, count 2 2006.190.07:36:30.53#ibcon#about to read 4, iclass 16, count 2 2006.190.07:36:30.53#ibcon#read 4, iclass 16, count 2 2006.190.07:36:30.53#ibcon#about to read 5, iclass 16, count 2 2006.190.07:36:30.53#ibcon#read 5, iclass 16, count 2 2006.190.07:36:30.53#ibcon#about to read 6, iclass 16, count 2 2006.190.07:36:30.53#ibcon#read 6, iclass 16, count 2 2006.190.07:36:30.53#ibcon#end of sib2, iclass 16, count 2 2006.190.07:36:30.53#ibcon#*after write, iclass 16, count 2 2006.190.07:36:30.53#ibcon#*before return 0, iclass 16, count 2 2006.190.07:36:30.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:36:30.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:36:30.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.07:36:30.53#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:30.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:36:30.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:36:30.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:36:30.65#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:36:30.65#ibcon#first serial, iclass 16, count 0 2006.190.07:36:30.65#ibcon#enter sib2, iclass 16, count 0 2006.190.07:36:30.65#ibcon#flushed, iclass 16, count 0 2006.190.07:36:30.65#ibcon#about to write, iclass 16, count 0 2006.190.07:36:30.65#ibcon#wrote, iclass 16, count 0 2006.190.07:36:30.65#ibcon#about to read 3, iclass 16, count 0 2006.190.07:36:30.67#ibcon#read 3, iclass 16, count 0 2006.190.07:36:30.67#ibcon#about to read 4, iclass 16, count 0 2006.190.07:36:30.67#ibcon#read 4, iclass 16, count 0 2006.190.07:36:30.67#ibcon#about to read 5, iclass 16, count 0 2006.190.07:36:30.67#ibcon#read 5, iclass 16, count 0 2006.190.07:36:30.67#ibcon#about to read 6, iclass 16, count 0 2006.190.07:36:30.67#ibcon#read 6, iclass 16, count 0 2006.190.07:36:30.67#ibcon#end of sib2, iclass 16, count 0 2006.190.07:36:30.67#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:36:30.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:36:30.67#ibcon#[25=USB\r\n] 2006.190.07:36:30.67#ibcon#*before write, iclass 16, count 0 2006.190.07:36:30.67#ibcon#enter sib2, iclass 16, count 0 2006.190.07:36:30.67#ibcon#flushed, iclass 16, count 0 2006.190.07:36:30.67#ibcon#about to write, iclass 16, count 0 2006.190.07:36:30.67#ibcon#wrote, iclass 16, count 0 2006.190.07:36:30.67#ibcon#about to read 3, iclass 16, count 0 2006.190.07:36:30.70#ibcon#read 3, iclass 16, count 0 2006.190.07:36:30.70#ibcon#about to read 4, iclass 16, count 0 2006.190.07:36:30.70#ibcon#read 4, iclass 16, count 0 2006.190.07:36:30.70#ibcon#about to read 5, iclass 16, count 0 2006.190.07:36:30.70#ibcon#read 5, iclass 16, count 0 2006.190.07:36:30.70#ibcon#about to read 6, iclass 16, count 0 2006.190.07:36:30.70#ibcon#read 6, iclass 16, count 0 2006.190.07:36:30.70#ibcon#end of sib2, iclass 16, count 0 2006.190.07:36:30.70#ibcon#*after write, iclass 16, count 0 2006.190.07:36:30.70#ibcon#*before return 0, iclass 16, count 0 2006.190.07:36:30.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:36:30.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:36:30.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:36:30.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:36:30.70$vc4f8/vblo=1,632.99 2006.190.07:36:30.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.07:36:30.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.07:36:30.70#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:30.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:36:30.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:36:30.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:36:30.70#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:36:30.70#ibcon#first serial, iclass 18, count 0 2006.190.07:36:30.70#ibcon#enter sib2, iclass 18, count 0 2006.190.07:36:30.70#ibcon#flushed, iclass 18, count 0 2006.190.07:36:30.70#ibcon#about to write, iclass 18, count 0 2006.190.07:36:30.70#ibcon#wrote, iclass 18, count 0 2006.190.07:36:30.70#ibcon#about to read 3, iclass 18, count 0 2006.190.07:36:30.72#ibcon#read 3, iclass 18, count 0 2006.190.07:36:30.72#ibcon#about to read 4, iclass 18, count 0 2006.190.07:36:30.72#ibcon#read 4, iclass 18, count 0 2006.190.07:36:30.72#ibcon#about to read 5, iclass 18, count 0 2006.190.07:36:30.72#ibcon#read 5, iclass 18, count 0 2006.190.07:36:30.72#ibcon#about to read 6, iclass 18, count 0 2006.190.07:36:30.72#ibcon#read 6, iclass 18, count 0 2006.190.07:36:30.72#ibcon#end of sib2, iclass 18, count 0 2006.190.07:36:30.72#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:36:30.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:36:30.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:36:30.72#ibcon#*before write, iclass 18, count 0 2006.190.07:36:30.72#ibcon#enter sib2, iclass 18, count 0 2006.190.07:36:30.72#ibcon#flushed, iclass 18, count 0 2006.190.07:36:30.72#ibcon#about to write, iclass 18, count 0 2006.190.07:36:30.72#ibcon#wrote, iclass 18, count 0 2006.190.07:36:30.72#ibcon#about to read 3, iclass 18, count 0 2006.190.07:36:30.76#ibcon#read 3, iclass 18, count 0 2006.190.07:36:30.76#ibcon#about to read 4, iclass 18, count 0 2006.190.07:36:30.76#ibcon#read 4, iclass 18, count 0 2006.190.07:36:30.76#ibcon#about to read 5, iclass 18, count 0 2006.190.07:36:30.76#ibcon#read 5, iclass 18, count 0 2006.190.07:36:30.76#ibcon#about to read 6, iclass 18, count 0 2006.190.07:36:30.76#ibcon#read 6, iclass 18, count 0 2006.190.07:36:30.76#ibcon#end of sib2, iclass 18, count 0 2006.190.07:36:30.76#ibcon#*after write, iclass 18, count 0 2006.190.07:36:30.76#ibcon#*before return 0, iclass 18, count 0 2006.190.07:36:30.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:36:30.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:36:30.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:36:30.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:36:30.76$vc4f8/vb=1,4 2006.190.07:36:30.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.190.07:36:30.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.190.07:36:30.76#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:30.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:36:30.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:36:30.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:36:30.76#ibcon#enter wrdev, iclass 20, count 2 2006.190.07:36:30.76#ibcon#first serial, iclass 20, count 2 2006.190.07:36:30.76#ibcon#enter sib2, iclass 20, count 2 2006.190.07:36:30.76#ibcon#flushed, iclass 20, count 2 2006.190.07:36:30.76#ibcon#about to write, iclass 20, count 2 2006.190.07:36:30.76#ibcon#wrote, iclass 20, count 2 2006.190.07:36:30.76#ibcon#about to read 3, iclass 20, count 2 2006.190.07:36:30.78#ibcon#read 3, iclass 20, count 2 2006.190.07:36:30.78#ibcon#about to read 4, iclass 20, count 2 2006.190.07:36:30.78#ibcon#read 4, iclass 20, count 2 2006.190.07:36:30.78#ibcon#about to read 5, iclass 20, count 2 2006.190.07:36:30.78#ibcon#read 5, iclass 20, count 2 2006.190.07:36:30.78#ibcon#about to read 6, iclass 20, count 2 2006.190.07:36:30.78#ibcon#read 6, iclass 20, count 2 2006.190.07:36:30.78#ibcon#end of sib2, iclass 20, count 2 2006.190.07:36:30.78#ibcon#*mode == 0, iclass 20, count 2 2006.190.07:36:30.78#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.190.07:36:30.78#ibcon#[27=AT01-04\r\n] 2006.190.07:36:30.78#ibcon#*before write, iclass 20, count 2 2006.190.07:36:30.78#ibcon#enter sib2, iclass 20, count 2 2006.190.07:36:30.78#ibcon#flushed, iclass 20, count 2 2006.190.07:36:30.78#ibcon#about to write, iclass 20, count 2 2006.190.07:36:30.78#ibcon#wrote, iclass 20, count 2 2006.190.07:36:30.78#ibcon#about to read 3, iclass 20, count 2 2006.190.07:36:30.81#ibcon#read 3, iclass 20, count 2 2006.190.07:36:30.81#ibcon#about to read 4, iclass 20, count 2 2006.190.07:36:30.81#ibcon#read 4, iclass 20, count 2 2006.190.07:36:30.81#ibcon#about to read 5, iclass 20, count 2 2006.190.07:36:30.81#ibcon#read 5, iclass 20, count 2 2006.190.07:36:30.81#ibcon#about to read 6, iclass 20, count 2 2006.190.07:36:30.81#ibcon#read 6, iclass 20, count 2 2006.190.07:36:30.81#ibcon#end of sib2, iclass 20, count 2 2006.190.07:36:30.81#ibcon#*after write, iclass 20, count 2 2006.190.07:36:30.81#ibcon#*before return 0, iclass 20, count 2 2006.190.07:36:30.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:36:30.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:36:30.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.190.07:36:30.81#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:30.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:36:30.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:36:30.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:36:30.93#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:36:30.93#ibcon#first serial, iclass 20, count 0 2006.190.07:36:30.93#ibcon#enter sib2, iclass 20, count 0 2006.190.07:36:30.93#ibcon#flushed, iclass 20, count 0 2006.190.07:36:30.93#ibcon#about to write, iclass 20, count 0 2006.190.07:36:30.93#ibcon#wrote, iclass 20, count 0 2006.190.07:36:30.93#ibcon#about to read 3, iclass 20, count 0 2006.190.07:36:30.95#ibcon#read 3, iclass 20, count 0 2006.190.07:36:30.95#ibcon#about to read 4, iclass 20, count 0 2006.190.07:36:30.95#ibcon#read 4, iclass 20, count 0 2006.190.07:36:30.95#ibcon#about to read 5, iclass 20, count 0 2006.190.07:36:30.95#ibcon#read 5, iclass 20, count 0 2006.190.07:36:30.95#ibcon#about to read 6, iclass 20, count 0 2006.190.07:36:30.95#ibcon#read 6, iclass 20, count 0 2006.190.07:36:30.95#ibcon#end of sib2, iclass 20, count 0 2006.190.07:36:30.95#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:36:30.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:36:30.95#ibcon#[27=USB\r\n] 2006.190.07:36:30.95#ibcon#*before write, iclass 20, count 0 2006.190.07:36:30.95#ibcon#enter sib2, iclass 20, count 0 2006.190.07:36:30.95#ibcon#flushed, iclass 20, count 0 2006.190.07:36:30.95#ibcon#about to write, iclass 20, count 0 2006.190.07:36:30.95#ibcon#wrote, iclass 20, count 0 2006.190.07:36:30.95#ibcon#about to read 3, iclass 20, count 0 2006.190.07:36:30.98#ibcon#read 3, iclass 20, count 0 2006.190.07:36:30.98#ibcon#about to read 4, iclass 20, count 0 2006.190.07:36:30.98#ibcon#read 4, iclass 20, count 0 2006.190.07:36:30.98#ibcon#about to read 5, iclass 20, count 0 2006.190.07:36:30.98#ibcon#read 5, iclass 20, count 0 2006.190.07:36:30.98#ibcon#about to read 6, iclass 20, count 0 2006.190.07:36:30.98#ibcon#read 6, iclass 20, count 0 2006.190.07:36:30.98#ibcon#end of sib2, iclass 20, count 0 2006.190.07:36:30.98#ibcon#*after write, iclass 20, count 0 2006.190.07:36:30.98#ibcon#*before return 0, iclass 20, count 0 2006.190.07:36:30.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:36:30.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:36:30.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:36:30.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:36:30.98$vc4f8/vblo=2,640.99 2006.190.07:36:30.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.07:36:30.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.07:36:30.98#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:30.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:30.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:30.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:30.98#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:36:30.98#ibcon#first serial, iclass 22, count 0 2006.190.07:36:30.98#ibcon#enter sib2, iclass 22, count 0 2006.190.07:36:30.98#ibcon#flushed, iclass 22, count 0 2006.190.07:36:30.98#ibcon#about to write, iclass 22, count 0 2006.190.07:36:30.98#ibcon#wrote, iclass 22, count 0 2006.190.07:36:30.98#ibcon#about to read 3, iclass 22, count 0 2006.190.07:36:31.00#ibcon#read 3, iclass 22, count 0 2006.190.07:36:31.00#ibcon#about to read 4, iclass 22, count 0 2006.190.07:36:31.00#ibcon#read 4, iclass 22, count 0 2006.190.07:36:31.00#ibcon#about to read 5, iclass 22, count 0 2006.190.07:36:31.00#ibcon#read 5, iclass 22, count 0 2006.190.07:36:31.00#ibcon#about to read 6, iclass 22, count 0 2006.190.07:36:31.00#ibcon#read 6, iclass 22, count 0 2006.190.07:36:31.00#ibcon#end of sib2, iclass 22, count 0 2006.190.07:36:31.00#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:36:31.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:36:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:36:31.00#ibcon#*before write, iclass 22, count 0 2006.190.07:36:31.00#ibcon#enter sib2, iclass 22, count 0 2006.190.07:36:31.00#ibcon#flushed, iclass 22, count 0 2006.190.07:36:31.00#ibcon#about to write, iclass 22, count 0 2006.190.07:36:31.00#ibcon#wrote, iclass 22, count 0 2006.190.07:36:31.00#ibcon#about to read 3, iclass 22, count 0 2006.190.07:36:31.04#ibcon#read 3, iclass 22, count 0 2006.190.07:36:31.04#ibcon#about to read 4, iclass 22, count 0 2006.190.07:36:31.04#ibcon#read 4, iclass 22, count 0 2006.190.07:36:31.04#ibcon#about to read 5, iclass 22, count 0 2006.190.07:36:31.04#ibcon#read 5, iclass 22, count 0 2006.190.07:36:31.04#ibcon#about to read 6, iclass 22, count 0 2006.190.07:36:31.04#ibcon#read 6, iclass 22, count 0 2006.190.07:36:31.04#ibcon#end of sib2, iclass 22, count 0 2006.190.07:36:31.04#ibcon#*after write, iclass 22, count 0 2006.190.07:36:31.04#ibcon#*before return 0, iclass 22, count 0 2006.190.07:36:31.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:31.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:36:31.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:36:31.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:36:31.04$vc4f8/vb=2,4 2006.190.07:36:31.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.07:36:31.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.07:36:31.04#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:31.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:36:31.05#abcon#<5=/04 1.7 3.0 24.551001012.3\r\n> 2006.190.07:36:31.07#abcon#{5=INTERFACE CLEAR} 2006.190.07:36:31.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:36:31.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:36:31.10#ibcon#enter wrdev, iclass 25, count 2 2006.190.07:36:31.10#ibcon#first serial, iclass 25, count 2 2006.190.07:36:31.10#ibcon#enter sib2, iclass 25, count 2 2006.190.07:36:31.10#ibcon#flushed, iclass 25, count 2 2006.190.07:36:31.10#ibcon#about to write, iclass 25, count 2 2006.190.07:36:31.10#ibcon#wrote, iclass 25, count 2 2006.190.07:36:31.10#ibcon#about to read 3, iclass 25, count 2 2006.190.07:36:31.12#ibcon#read 3, iclass 25, count 2 2006.190.07:36:31.12#ibcon#about to read 4, iclass 25, count 2 2006.190.07:36:31.12#ibcon#read 4, iclass 25, count 2 2006.190.07:36:31.12#ibcon#about to read 5, iclass 25, count 2 2006.190.07:36:31.12#ibcon#read 5, iclass 25, count 2 2006.190.07:36:31.12#ibcon#about to read 6, iclass 25, count 2 2006.190.07:36:31.12#ibcon#read 6, iclass 25, count 2 2006.190.07:36:31.12#ibcon#end of sib2, iclass 25, count 2 2006.190.07:36:31.12#ibcon#*mode == 0, iclass 25, count 2 2006.190.07:36:31.12#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.07:36:31.12#ibcon#[27=AT02-04\r\n] 2006.190.07:36:31.12#ibcon#*before write, iclass 25, count 2 2006.190.07:36:31.12#ibcon#enter sib2, iclass 25, count 2 2006.190.07:36:31.12#ibcon#flushed, iclass 25, count 2 2006.190.07:36:31.12#ibcon#about to write, iclass 25, count 2 2006.190.07:36:31.12#ibcon#wrote, iclass 25, count 2 2006.190.07:36:31.12#ibcon#about to read 3, iclass 25, count 2 2006.190.07:36:31.14#abcon#[5=S1D000X0/0*\r\n] 2006.190.07:36:31.15#ibcon#read 3, iclass 25, count 2 2006.190.07:36:31.15#ibcon#about to read 4, iclass 25, count 2 2006.190.07:36:31.15#ibcon#read 4, iclass 25, count 2 2006.190.07:36:31.15#ibcon#about to read 5, iclass 25, count 2 2006.190.07:36:31.15#ibcon#read 5, iclass 25, count 2 2006.190.07:36:31.15#ibcon#about to read 6, iclass 25, count 2 2006.190.07:36:31.15#ibcon#read 6, iclass 25, count 2 2006.190.07:36:31.15#ibcon#end of sib2, iclass 25, count 2 2006.190.07:36:31.15#ibcon#*after write, iclass 25, count 2 2006.190.07:36:31.15#ibcon#*before return 0, iclass 25, count 2 2006.190.07:36:31.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:36:31.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:36:31.15#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.07:36:31.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:31.15#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:36:31.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:36:31.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:36:31.27#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:36:31.27#ibcon#first serial, iclass 25, count 0 2006.190.07:36:31.27#ibcon#enter sib2, iclass 25, count 0 2006.190.07:36:31.27#ibcon#flushed, iclass 25, count 0 2006.190.07:36:31.27#ibcon#about to write, iclass 25, count 0 2006.190.07:36:31.27#ibcon#wrote, iclass 25, count 0 2006.190.07:36:31.27#ibcon#about to read 3, iclass 25, count 0 2006.190.07:36:31.29#ibcon#read 3, iclass 25, count 0 2006.190.07:36:31.29#ibcon#about to read 4, iclass 25, count 0 2006.190.07:36:31.29#ibcon#read 4, iclass 25, count 0 2006.190.07:36:31.29#ibcon#about to read 5, iclass 25, count 0 2006.190.07:36:31.29#ibcon#read 5, iclass 25, count 0 2006.190.07:36:31.29#ibcon#about to read 6, iclass 25, count 0 2006.190.07:36:31.29#ibcon#read 6, iclass 25, count 0 2006.190.07:36:31.29#ibcon#end of sib2, iclass 25, count 0 2006.190.07:36:31.29#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:36:31.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:36:31.29#ibcon#[27=USB\r\n] 2006.190.07:36:31.29#ibcon#*before write, iclass 25, count 0 2006.190.07:36:31.29#ibcon#enter sib2, iclass 25, count 0 2006.190.07:36:31.29#ibcon#flushed, iclass 25, count 0 2006.190.07:36:31.29#ibcon#about to write, iclass 25, count 0 2006.190.07:36:31.29#ibcon#wrote, iclass 25, count 0 2006.190.07:36:31.29#ibcon#about to read 3, iclass 25, count 0 2006.190.07:36:31.32#ibcon#read 3, iclass 25, count 0 2006.190.07:36:31.32#ibcon#about to read 4, iclass 25, count 0 2006.190.07:36:31.32#ibcon#read 4, iclass 25, count 0 2006.190.07:36:31.32#ibcon#about to read 5, iclass 25, count 0 2006.190.07:36:31.32#ibcon#read 5, iclass 25, count 0 2006.190.07:36:31.32#ibcon#about to read 6, iclass 25, count 0 2006.190.07:36:31.32#ibcon#read 6, iclass 25, count 0 2006.190.07:36:31.32#ibcon#end of sib2, iclass 25, count 0 2006.190.07:36:31.32#ibcon#*after write, iclass 25, count 0 2006.190.07:36:31.32#ibcon#*before return 0, iclass 25, count 0 2006.190.07:36:31.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:36:31.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:36:31.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:36:31.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:36:31.32$vc4f8/vblo=3,656.99 2006.190.07:36:31.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.07:36:31.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.07:36:31.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:31.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:31.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:31.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:31.32#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:36:31.32#ibcon#first serial, iclass 30, count 0 2006.190.07:36:31.32#ibcon#enter sib2, iclass 30, count 0 2006.190.07:36:31.32#ibcon#flushed, iclass 30, count 0 2006.190.07:36:31.32#ibcon#about to write, iclass 30, count 0 2006.190.07:36:31.32#ibcon#wrote, iclass 30, count 0 2006.190.07:36:31.32#ibcon#about to read 3, iclass 30, count 0 2006.190.07:36:31.34#ibcon#read 3, iclass 30, count 0 2006.190.07:36:31.34#ibcon#about to read 4, iclass 30, count 0 2006.190.07:36:31.34#ibcon#read 4, iclass 30, count 0 2006.190.07:36:31.34#ibcon#about to read 5, iclass 30, count 0 2006.190.07:36:31.34#ibcon#read 5, iclass 30, count 0 2006.190.07:36:31.34#ibcon#about to read 6, iclass 30, count 0 2006.190.07:36:31.34#ibcon#read 6, iclass 30, count 0 2006.190.07:36:31.34#ibcon#end of sib2, iclass 30, count 0 2006.190.07:36:31.34#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:36:31.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:36:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:36:31.34#ibcon#*before write, iclass 30, count 0 2006.190.07:36:31.34#ibcon#enter sib2, iclass 30, count 0 2006.190.07:36:31.34#ibcon#flushed, iclass 30, count 0 2006.190.07:36:31.34#ibcon#about to write, iclass 30, count 0 2006.190.07:36:31.34#ibcon#wrote, iclass 30, count 0 2006.190.07:36:31.34#ibcon#about to read 3, iclass 30, count 0 2006.190.07:36:31.38#ibcon#read 3, iclass 30, count 0 2006.190.07:36:31.38#ibcon#about to read 4, iclass 30, count 0 2006.190.07:36:31.38#ibcon#read 4, iclass 30, count 0 2006.190.07:36:31.38#ibcon#about to read 5, iclass 30, count 0 2006.190.07:36:31.38#ibcon#read 5, iclass 30, count 0 2006.190.07:36:31.38#ibcon#about to read 6, iclass 30, count 0 2006.190.07:36:31.38#ibcon#read 6, iclass 30, count 0 2006.190.07:36:31.38#ibcon#end of sib2, iclass 30, count 0 2006.190.07:36:31.38#ibcon#*after write, iclass 30, count 0 2006.190.07:36:31.38#ibcon#*before return 0, iclass 30, count 0 2006.190.07:36:31.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:31.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:36:31.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:36:31.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:36:31.38$vc4f8/vb=3,4 2006.190.07:36:31.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.07:36:31.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.07:36:31.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:31.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:31.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:31.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:31.44#ibcon#enter wrdev, iclass 32, count 2 2006.190.07:36:31.44#ibcon#first serial, iclass 32, count 2 2006.190.07:36:31.44#ibcon#enter sib2, iclass 32, count 2 2006.190.07:36:31.44#ibcon#flushed, iclass 32, count 2 2006.190.07:36:31.44#ibcon#about to write, iclass 32, count 2 2006.190.07:36:31.44#ibcon#wrote, iclass 32, count 2 2006.190.07:36:31.44#ibcon#about to read 3, iclass 32, count 2 2006.190.07:36:31.46#ibcon#read 3, iclass 32, count 2 2006.190.07:36:31.46#ibcon#about to read 4, iclass 32, count 2 2006.190.07:36:31.46#ibcon#read 4, iclass 32, count 2 2006.190.07:36:31.46#ibcon#about to read 5, iclass 32, count 2 2006.190.07:36:31.46#ibcon#read 5, iclass 32, count 2 2006.190.07:36:31.46#ibcon#about to read 6, iclass 32, count 2 2006.190.07:36:31.46#ibcon#read 6, iclass 32, count 2 2006.190.07:36:31.46#ibcon#end of sib2, iclass 32, count 2 2006.190.07:36:31.46#ibcon#*mode == 0, iclass 32, count 2 2006.190.07:36:31.46#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.07:36:31.46#ibcon#[27=AT03-04\r\n] 2006.190.07:36:31.46#ibcon#*before write, iclass 32, count 2 2006.190.07:36:31.46#ibcon#enter sib2, iclass 32, count 2 2006.190.07:36:31.46#ibcon#flushed, iclass 32, count 2 2006.190.07:36:31.46#ibcon#about to write, iclass 32, count 2 2006.190.07:36:31.46#ibcon#wrote, iclass 32, count 2 2006.190.07:36:31.46#ibcon#about to read 3, iclass 32, count 2 2006.190.07:36:31.49#ibcon#read 3, iclass 32, count 2 2006.190.07:36:31.49#ibcon#about to read 4, iclass 32, count 2 2006.190.07:36:31.49#ibcon#read 4, iclass 32, count 2 2006.190.07:36:31.49#ibcon#about to read 5, iclass 32, count 2 2006.190.07:36:31.49#ibcon#read 5, iclass 32, count 2 2006.190.07:36:31.49#ibcon#about to read 6, iclass 32, count 2 2006.190.07:36:31.49#ibcon#read 6, iclass 32, count 2 2006.190.07:36:31.49#ibcon#end of sib2, iclass 32, count 2 2006.190.07:36:31.49#ibcon#*after write, iclass 32, count 2 2006.190.07:36:31.49#ibcon#*before return 0, iclass 32, count 2 2006.190.07:36:31.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:31.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:36:31.49#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.07:36:31.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:31.49#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:31.61#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:31.61#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:31.61#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:36:31.61#ibcon#first serial, iclass 32, count 0 2006.190.07:36:31.61#ibcon#enter sib2, iclass 32, count 0 2006.190.07:36:31.61#ibcon#flushed, iclass 32, count 0 2006.190.07:36:31.61#ibcon#about to write, iclass 32, count 0 2006.190.07:36:31.61#ibcon#wrote, iclass 32, count 0 2006.190.07:36:31.61#ibcon#about to read 3, iclass 32, count 0 2006.190.07:36:31.63#ibcon#read 3, iclass 32, count 0 2006.190.07:36:31.63#ibcon#about to read 4, iclass 32, count 0 2006.190.07:36:31.63#ibcon#read 4, iclass 32, count 0 2006.190.07:36:31.63#ibcon#about to read 5, iclass 32, count 0 2006.190.07:36:31.63#ibcon#read 5, iclass 32, count 0 2006.190.07:36:31.63#ibcon#about to read 6, iclass 32, count 0 2006.190.07:36:31.63#ibcon#read 6, iclass 32, count 0 2006.190.07:36:31.63#ibcon#end of sib2, iclass 32, count 0 2006.190.07:36:31.63#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:36:31.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:36:31.63#ibcon#[27=USB\r\n] 2006.190.07:36:31.63#ibcon#*before write, iclass 32, count 0 2006.190.07:36:31.63#ibcon#enter sib2, iclass 32, count 0 2006.190.07:36:31.63#ibcon#flushed, iclass 32, count 0 2006.190.07:36:31.63#ibcon#about to write, iclass 32, count 0 2006.190.07:36:31.63#ibcon#wrote, iclass 32, count 0 2006.190.07:36:31.63#ibcon#about to read 3, iclass 32, count 0 2006.190.07:36:31.66#ibcon#read 3, iclass 32, count 0 2006.190.07:36:31.66#ibcon#about to read 4, iclass 32, count 0 2006.190.07:36:31.66#ibcon#read 4, iclass 32, count 0 2006.190.07:36:31.66#ibcon#about to read 5, iclass 32, count 0 2006.190.07:36:31.66#ibcon#read 5, iclass 32, count 0 2006.190.07:36:31.66#ibcon#about to read 6, iclass 32, count 0 2006.190.07:36:31.66#ibcon#read 6, iclass 32, count 0 2006.190.07:36:31.66#ibcon#end of sib2, iclass 32, count 0 2006.190.07:36:31.66#ibcon#*after write, iclass 32, count 0 2006.190.07:36:31.66#ibcon#*before return 0, iclass 32, count 0 2006.190.07:36:31.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:31.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:36:31.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:36:31.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:36:31.66$vc4f8/vblo=4,712.99 2006.190.07:36:31.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.07:36:31.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.07:36:31.66#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:31.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:31.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:31.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:31.66#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:36:31.66#ibcon#first serial, iclass 34, count 0 2006.190.07:36:31.66#ibcon#enter sib2, iclass 34, count 0 2006.190.07:36:31.66#ibcon#flushed, iclass 34, count 0 2006.190.07:36:31.66#ibcon#about to write, iclass 34, count 0 2006.190.07:36:31.66#ibcon#wrote, iclass 34, count 0 2006.190.07:36:31.66#ibcon#about to read 3, iclass 34, count 0 2006.190.07:36:31.68#ibcon#read 3, iclass 34, count 0 2006.190.07:36:31.68#ibcon#about to read 4, iclass 34, count 0 2006.190.07:36:31.68#ibcon#read 4, iclass 34, count 0 2006.190.07:36:31.68#ibcon#about to read 5, iclass 34, count 0 2006.190.07:36:31.68#ibcon#read 5, iclass 34, count 0 2006.190.07:36:31.68#ibcon#about to read 6, iclass 34, count 0 2006.190.07:36:31.68#ibcon#read 6, iclass 34, count 0 2006.190.07:36:31.68#ibcon#end of sib2, iclass 34, count 0 2006.190.07:36:31.68#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:36:31.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:36:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:36:31.68#ibcon#*before write, iclass 34, count 0 2006.190.07:36:31.68#ibcon#enter sib2, iclass 34, count 0 2006.190.07:36:31.68#ibcon#flushed, iclass 34, count 0 2006.190.07:36:31.68#ibcon#about to write, iclass 34, count 0 2006.190.07:36:31.68#ibcon#wrote, iclass 34, count 0 2006.190.07:36:31.68#ibcon#about to read 3, iclass 34, count 0 2006.190.07:36:31.72#ibcon#read 3, iclass 34, count 0 2006.190.07:36:31.72#ibcon#about to read 4, iclass 34, count 0 2006.190.07:36:31.72#ibcon#read 4, iclass 34, count 0 2006.190.07:36:31.72#ibcon#about to read 5, iclass 34, count 0 2006.190.07:36:31.72#ibcon#read 5, iclass 34, count 0 2006.190.07:36:31.72#ibcon#about to read 6, iclass 34, count 0 2006.190.07:36:31.72#ibcon#read 6, iclass 34, count 0 2006.190.07:36:31.72#ibcon#end of sib2, iclass 34, count 0 2006.190.07:36:31.72#ibcon#*after write, iclass 34, count 0 2006.190.07:36:31.72#ibcon#*before return 0, iclass 34, count 0 2006.190.07:36:31.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:31.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:36:31.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:36:31.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:36:31.72$vc4f8/vb=4,4 2006.190.07:36:31.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.07:36:31.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.07:36:31.72#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:31.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:31.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:31.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:31.78#ibcon#enter wrdev, iclass 36, count 2 2006.190.07:36:31.78#ibcon#first serial, iclass 36, count 2 2006.190.07:36:31.78#ibcon#enter sib2, iclass 36, count 2 2006.190.07:36:31.78#ibcon#flushed, iclass 36, count 2 2006.190.07:36:31.78#ibcon#about to write, iclass 36, count 2 2006.190.07:36:31.78#ibcon#wrote, iclass 36, count 2 2006.190.07:36:31.78#ibcon#about to read 3, iclass 36, count 2 2006.190.07:36:31.80#ibcon#read 3, iclass 36, count 2 2006.190.07:36:31.80#ibcon#about to read 4, iclass 36, count 2 2006.190.07:36:31.80#ibcon#read 4, iclass 36, count 2 2006.190.07:36:31.80#ibcon#about to read 5, iclass 36, count 2 2006.190.07:36:31.80#ibcon#read 5, iclass 36, count 2 2006.190.07:36:31.80#ibcon#about to read 6, iclass 36, count 2 2006.190.07:36:31.80#ibcon#read 6, iclass 36, count 2 2006.190.07:36:31.80#ibcon#end of sib2, iclass 36, count 2 2006.190.07:36:31.80#ibcon#*mode == 0, iclass 36, count 2 2006.190.07:36:31.80#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.07:36:31.80#ibcon#[27=AT04-04\r\n] 2006.190.07:36:31.80#ibcon#*before write, iclass 36, count 2 2006.190.07:36:31.80#ibcon#enter sib2, iclass 36, count 2 2006.190.07:36:31.80#ibcon#flushed, iclass 36, count 2 2006.190.07:36:31.80#ibcon#about to write, iclass 36, count 2 2006.190.07:36:31.80#ibcon#wrote, iclass 36, count 2 2006.190.07:36:31.80#ibcon#about to read 3, iclass 36, count 2 2006.190.07:36:31.83#ibcon#read 3, iclass 36, count 2 2006.190.07:36:31.83#ibcon#about to read 4, iclass 36, count 2 2006.190.07:36:31.83#ibcon#read 4, iclass 36, count 2 2006.190.07:36:31.83#ibcon#about to read 5, iclass 36, count 2 2006.190.07:36:31.83#ibcon#read 5, iclass 36, count 2 2006.190.07:36:31.83#ibcon#about to read 6, iclass 36, count 2 2006.190.07:36:31.83#ibcon#read 6, iclass 36, count 2 2006.190.07:36:31.83#ibcon#end of sib2, iclass 36, count 2 2006.190.07:36:31.83#ibcon#*after write, iclass 36, count 2 2006.190.07:36:31.83#ibcon#*before return 0, iclass 36, count 2 2006.190.07:36:31.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:31.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:36:31.83#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.07:36:31.83#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:31.83#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:31.95#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:31.95#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:31.95#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:36:31.95#ibcon#first serial, iclass 36, count 0 2006.190.07:36:31.95#ibcon#enter sib2, iclass 36, count 0 2006.190.07:36:31.95#ibcon#flushed, iclass 36, count 0 2006.190.07:36:31.95#ibcon#about to write, iclass 36, count 0 2006.190.07:36:31.95#ibcon#wrote, iclass 36, count 0 2006.190.07:36:31.95#ibcon#about to read 3, iclass 36, count 0 2006.190.07:36:31.97#ibcon#read 3, iclass 36, count 0 2006.190.07:36:31.97#ibcon#about to read 4, iclass 36, count 0 2006.190.07:36:31.97#ibcon#read 4, iclass 36, count 0 2006.190.07:36:31.97#ibcon#about to read 5, iclass 36, count 0 2006.190.07:36:31.97#ibcon#read 5, iclass 36, count 0 2006.190.07:36:31.97#ibcon#about to read 6, iclass 36, count 0 2006.190.07:36:31.97#ibcon#read 6, iclass 36, count 0 2006.190.07:36:31.97#ibcon#end of sib2, iclass 36, count 0 2006.190.07:36:31.97#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:36:31.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:36:31.97#ibcon#[27=USB\r\n] 2006.190.07:36:31.97#ibcon#*before write, iclass 36, count 0 2006.190.07:36:31.97#ibcon#enter sib2, iclass 36, count 0 2006.190.07:36:31.97#ibcon#flushed, iclass 36, count 0 2006.190.07:36:31.97#ibcon#about to write, iclass 36, count 0 2006.190.07:36:31.97#ibcon#wrote, iclass 36, count 0 2006.190.07:36:31.97#ibcon#about to read 3, iclass 36, count 0 2006.190.07:36:32.00#ibcon#read 3, iclass 36, count 0 2006.190.07:36:32.00#ibcon#about to read 4, iclass 36, count 0 2006.190.07:36:32.00#ibcon#read 4, iclass 36, count 0 2006.190.07:36:32.00#ibcon#about to read 5, iclass 36, count 0 2006.190.07:36:32.00#ibcon#read 5, iclass 36, count 0 2006.190.07:36:32.00#ibcon#about to read 6, iclass 36, count 0 2006.190.07:36:32.00#ibcon#read 6, iclass 36, count 0 2006.190.07:36:32.00#ibcon#end of sib2, iclass 36, count 0 2006.190.07:36:32.00#ibcon#*after write, iclass 36, count 0 2006.190.07:36:32.00#ibcon#*before return 0, iclass 36, count 0 2006.190.07:36:32.00#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:32.00#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:36:32.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:36:32.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:36:32.00$vc4f8/vblo=5,744.99 2006.190.07:36:32.00#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.07:36:32.00#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.07:36:32.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:32.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:32.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:32.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:32.00#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:36:32.00#ibcon#first serial, iclass 38, count 0 2006.190.07:36:32.00#ibcon#enter sib2, iclass 38, count 0 2006.190.07:36:32.00#ibcon#flushed, iclass 38, count 0 2006.190.07:36:32.00#ibcon#about to write, iclass 38, count 0 2006.190.07:36:32.00#ibcon#wrote, iclass 38, count 0 2006.190.07:36:32.00#ibcon#about to read 3, iclass 38, count 0 2006.190.07:36:32.02#ibcon#read 3, iclass 38, count 0 2006.190.07:36:32.02#ibcon#about to read 4, iclass 38, count 0 2006.190.07:36:32.02#ibcon#read 4, iclass 38, count 0 2006.190.07:36:32.02#ibcon#about to read 5, iclass 38, count 0 2006.190.07:36:32.02#ibcon#read 5, iclass 38, count 0 2006.190.07:36:32.02#ibcon#about to read 6, iclass 38, count 0 2006.190.07:36:32.02#ibcon#read 6, iclass 38, count 0 2006.190.07:36:32.02#ibcon#end of sib2, iclass 38, count 0 2006.190.07:36:32.02#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:36:32.02#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:36:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:36:32.02#ibcon#*before write, iclass 38, count 0 2006.190.07:36:32.02#ibcon#enter sib2, iclass 38, count 0 2006.190.07:36:32.02#ibcon#flushed, iclass 38, count 0 2006.190.07:36:32.02#ibcon#about to write, iclass 38, count 0 2006.190.07:36:32.02#ibcon#wrote, iclass 38, count 0 2006.190.07:36:32.02#ibcon#about to read 3, iclass 38, count 0 2006.190.07:36:32.06#ibcon#read 3, iclass 38, count 0 2006.190.07:36:32.06#ibcon#about to read 4, iclass 38, count 0 2006.190.07:36:32.06#ibcon#read 4, iclass 38, count 0 2006.190.07:36:32.06#ibcon#about to read 5, iclass 38, count 0 2006.190.07:36:32.06#ibcon#read 5, iclass 38, count 0 2006.190.07:36:32.06#ibcon#about to read 6, iclass 38, count 0 2006.190.07:36:32.06#ibcon#read 6, iclass 38, count 0 2006.190.07:36:32.06#ibcon#end of sib2, iclass 38, count 0 2006.190.07:36:32.06#ibcon#*after write, iclass 38, count 0 2006.190.07:36:32.06#ibcon#*before return 0, iclass 38, count 0 2006.190.07:36:32.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:32.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:36:32.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:36:32.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:36:32.06$vc4f8/vb=5,4 2006.190.07:36:32.06#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.07:36:32.06#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.07:36:32.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:32.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:32.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:32.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:32.12#ibcon#enter wrdev, iclass 40, count 2 2006.190.07:36:32.12#ibcon#first serial, iclass 40, count 2 2006.190.07:36:32.12#ibcon#enter sib2, iclass 40, count 2 2006.190.07:36:32.12#ibcon#flushed, iclass 40, count 2 2006.190.07:36:32.12#ibcon#about to write, iclass 40, count 2 2006.190.07:36:32.12#ibcon#wrote, iclass 40, count 2 2006.190.07:36:32.12#ibcon#about to read 3, iclass 40, count 2 2006.190.07:36:32.14#ibcon#read 3, iclass 40, count 2 2006.190.07:36:32.14#ibcon#about to read 4, iclass 40, count 2 2006.190.07:36:32.14#ibcon#read 4, iclass 40, count 2 2006.190.07:36:32.14#ibcon#about to read 5, iclass 40, count 2 2006.190.07:36:32.14#ibcon#read 5, iclass 40, count 2 2006.190.07:36:32.14#ibcon#about to read 6, iclass 40, count 2 2006.190.07:36:32.14#ibcon#read 6, iclass 40, count 2 2006.190.07:36:32.14#ibcon#end of sib2, iclass 40, count 2 2006.190.07:36:32.14#ibcon#*mode == 0, iclass 40, count 2 2006.190.07:36:32.14#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.07:36:32.14#ibcon#[27=AT05-04\r\n] 2006.190.07:36:32.14#ibcon#*before write, iclass 40, count 2 2006.190.07:36:32.14#ibcon#enter sib2, iclass 40, count 2 2006.190.07:36:32.14#ibcon#flushed, iclass 40, count 2 2006.190.07:36:32.14#ibcon#about to write, iclass 40, count 2 2006.190.07:36:32.14#ibcon#wrote, iclass 40, count 2 2006.190.07:36:32.14#ibcon#about to read 3, iclass 40, count 2 2006.190.07:36:32.17#ibcon#read 3, iclass 40, count 2 2006.190.07:36:32.17#ibcon#about to read 4, iclass 40, count 2 2006.190.07:36:32.17#ibcon#read 4, iclass 40, count 2 2006.190.07:36:32.17#ibcon#about to read 5, iclass 40, count 2 2006.190.07:36:32.17#ibcon#read 5, iclass 40, count 2 2006.190.07:36:32.17#ibcon#about to read 6, iclass 40, count 2 2006.190.07:36:32.17#ibcon#read 6, iclass 40, count 2 2006.190.07:36:32.17#ibcon#end of sib2, iclass 40, count 2 2006.190.07:36:32.17#ibcon#*after write, iclass 40, count 2 2006.190.07:36:32.17#ibcon#*before return 0, iclass 40, count 2 2006.190.07:36:32.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:32.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:36:32.17#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.07:36:32.17#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:32.17#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:32.29#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:32.29#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:32.29#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:36:32.29#ibcon#first serial, iclass 40, count 0 2006.190.07:36:32.29#ibcon#enter sib2, iclass 40, count 0 2006.190.07:36:32.29#ibcon#flushed, iclass 40, count 0 2006.190.07:36:32.29#ibcon#about to write, iclass 40, count 0 2006.190.07:36:32.29#ibcon#wrote, iclass 40, count 0 2006.190.07:36:32.29#ibcon#about to read 3, iclass 40, count 0 2006.190.07:36:32.31#ibcon#read 3, iclass 40, count 0 2006.190.07:36:32.31#ibcon#about to read 4, iclass 40, count 0 2006.190.07:36:32.31#ibcon#read 4, iclass 40, count 0 2006.190.07:36:32.31#ibcon#about to read 5, iclass 40, count 0 2006.190.07:36:32.31#ibcon#read 5, iclass 40, count 0 2006.190.07:36:32.31#ibcon#about to read 6, iclass 40, count 0 2006.190.07:36:32.31#ibcon#read 6, iclass 40, count 0 2006.190.07:36:32.31#ibcon#end of sib2, iclass 40, count 0 2006.190.07:36:32.31#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:36:32.31#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:36:32.31#ibcon#[27=USB\r\n] 2006.190.07:36:32.31#ibcon#*before write, iclass 40, count 0 2006.190.07:36:32.31#ibcon#enter sib2, iclass 40, count 0 2006.190.07:36:32.31#ibcon#flushed, iclass 40, count 0 2006.190.07:36:32.31#ibcon#about to write, iclass 40, count 0 2006.190.07:36:32.31#ibcon#wrote, iclass 40, count 0 2006.190.07:36:32.31#ibcon#about to read 3, iclass 40, count 0 2006.190.07:36:32.34#ibcon#read 3, iclass 40, count 0 2006.190.07:36:32.34#ibcon#about to read 4, iclass 40, count 0 2006.190.07:36:32.34#ibcon#read 4, iclass 40, count 0 2006.190.07:36:32.34#ibcon#about to read 5, iclass 40, count 0 2006.190.07:36:32.34#ibcon#read 5, iclass 40, count 0 2006.190.07:36:32.34#ibcon#about to read 6, iclass 40, count 0 2006.190.07:36:32.34#ibcon#read 6, iclass 40, count 0 2006.190.07:36:32.34#ibcon#end of sib2, iclass 40, count 0 2006.190.07:36:32.34#ibcon#*after write, iclass 40, count 0 2006.190.07:36:32.34#ibcon#*before return 0, iclass 40, count 0 2006.190.07:36:32.34#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:32.34#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:36:32.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:36:32.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:36:32.34$vc4f8/vblo=6,752.99 2006.190.07:36:32.34#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.07:36:32.34#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.07:36:32.34#ibcon#ireg 17 cls_cnt 0 2006.190.07:36:32.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:32.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:32.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:32.34#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:36:32.34#ibcon#first serial, iclass 4, count 0 2006.190.07:36:32.34#ibcon#enter sib2, iclass 4, count 0 2006.190.07:36:32.34#ibcon#flushed, iclass 4, count 0 2006.190.07:36:32.34#ibcon#about to write, iclass 4, count 0 2006.190.07:36:32.34#ibcon#wrote, iclass 4, count 0 2006.190.07:36:32.34#ibcon#about to read 3, iclass 4, count 0 2006.190.07:36:32.36#ibcon#read 3, iclass 4, count 0 2006.190.07:36:32.36#ibcon#about to read 4, iclass 4, count 0 2006.190.07:36:32.36#ibcon#read 4, iclass 4, count 0 2006.190.07:36:32.36#ibcon#about to read 5, iclass 4, count 0 2006.190.07:36:32.36#ibcon#read 5, iclass 4, count 0 2006.190.07:36:32.36#ibcon#about to read 6, iclass 4, count 0 2006.190.07:36:32.36#ibcon#read 6, iclass 4, count 0 2006.190.07:36:32.36#ibcon#end of sib2, iclass 4, count 0 2006.190.07:36:32.36#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:36:32.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:36:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:36:32.36#ibcon#*before write, iclass 4, count 0 2006.190.07:36:32.36#ibcon#enter sib2, iclass 4, count 0 2006.190.07:36:32.36#ibcon#flushed, iclass 4, count 0 2006.190.07:36:32.36#ibcon#about to write, iclass 4, count 0 2006.190.07:36:32.36#ibcon#wrote, iclass 4, count 0 2006.190.07:36:32.36#ibcon#about to read 3, iclass 4, count 0 2006.190.07:36:32.40#ibcon#read 3, iclass 4, count 0 2006.190.07:36:32.40#ibcon#about to read 4, iclass 4, count 0 2006.190.07:36:32.40#ibcon#read 4, iclass 4, count 0 2006.190.07:36:32.40#ibcon#about to read 5, iclass 4, count 0 2006.190.07:36:32.40#ibcon#read 5, iclass 4, count 0 2006.190.07:36:32.40#ibcon#about to read 6, iclass 4, count 0 2006.190.07:36:32.40#ibcon#read 6, iclass 4, count 0 2006.190.07:36:32.40#ibcon#end of sib2, iclass 4, count 0 2006.190.07:36:32.40#ibcon#*after write, iclass 4, count 0 2006.190.07:36:32.40#ibcon#*before return 0, iclass 4, count 0 2006.190.07:36:32.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:32.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:36:32.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:36:32.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:36:32.40$vc4f8/vb=6,4 2006.190.07:36:32.40#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.07:36:32.40#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.07:36:32.40#ibcon#ireg 11 cls_cnt 2 2006.190.07:36:32.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:32.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:32.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:32.46#ibcon#enter wrdev, iclass 6, count 2 2006.190.07:36:32.46#ibcon#first serial, iclass 6, count 2 2006.190.07:36:32.46#ibcon#enter sib2, iclass 6, count 2 2006.190.07:36:32.46#ibcon#flushed, iclass 6, count 2 2006.190.07:36:32.46#ibcon#about to write, iclass 6, count 2 2006.190.07:36:32.46#ibcon#wrote, iclass 6, count 2 2006.190.07:36:32.46#ibcon#about to read 3, iclass 6, count 2 2006.190.07:36:32.48#ibcon#read 3, iclass 6, count 2 2006.190.07:36:32.48#ibcon#about to read 4, iclass 6, count 2 2006.190.07:36:32.48#ibcon#read 4, iclass 6, count 2 2006.190.07:36:32.48#ibcon#about to read 5, iclass 6, count 2 2006.190.07:36:32.48#ibcon#read 5, iclass 6, count 2 2006.190.07:36:32.48#ibcon#about to read 6, iclass 6, count 2 2006.190.07:36:32.48#ibcon#read 6, iclass 6, count 2 2006.190.07:36:32.48#ibcon#end of sib2, iclass 6, count 2 2006.190.07:36:32.48#ibcon#*mode == 0, iclass 6, count 2 2006.190.07:36:32.48#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.07:36:32.48#ibcon#[27=AT06-04\r\n] 2006.190.07:36:32.48#ibcon#*before write, iclass 6, count 2 2006.190.07:36:32.48#ibcon#enter sib2, iclass 6, count 2 2006.190.07:36:32.48#ibcon#flushed, iclass 6, count 2 2006.190.07:36:32.48#ibcon#about to write, iclass 6, count 2 2006.190.07:36:32.48#ibcon#wrote, iclass 6, count 2 2006.190.07:36:32.48#ibcon#about to read 3, iclass 6, count 2 2006.190.07:36:32.51#ibcon#read 3, iclass 6, count 2 2006.190.07:36:32.51#ibcon#about to read 4, iclass 6, count 2 2006.190.07:36:32.51#ibcon#read 4, iclass 6, count 2 2006.190.07:36:32.51#ibcon#about to read 5, iclass 6, count 2 2006.190.07:36:32.51#ibcon#read 5, iclass 6, count 2 2006.190.07:36:32.51#ibcon#about to read 6, iclass 6, count 2 2006.190.07:36:32.51#ibcon#read 6, iclass 6, count 2 2006.190.07:36:32.51#ibcon#end of sib2, iclass 6, count 2 2006.190.07:36:32.51#ibcon#*after write, iclass 6, count 2 2006.190.07:36:32.51#ibcon#*before return 0, iclass 6, count 2 2006.190.07:36:32.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:32.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:36:32.51#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.07:36:32.51#ibcon#ireg 7 cls_cnt 0 2006.190.07:36:32.51#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:32.63#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:32.63#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:32.63#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:36:32.63#ibcon#first serial, iclass 6, count 0 2006.190.07:36:32.63#ibcon#enter sib2, iclass 6, count 0 2006.190.07:36:32.63#ibcon#flushed, iclass 6, count 0 2006.190.07:36:32.63#ibcon#about to write, iclass 6, count 0 2006.190.07:36:32.63#ibcon#wrote, iclass 6, count 0 2006.190.07:36:32.63#ibcon#about to read 3, iclass 6, count 0 2006.190.07:36:32.65#ibcon#read 3, iclass 6, count 0 2006.190.07:36:32.65#ibcon#about to read 4, iclass 6, count 0 2006.190.07:36:32.65#ibcon#read 4, iclass 6, count 0 2006.190.07:36:32.65#ibcon#about to read 5, iclass 6, count 0 2006.190.07:36:32.65#ibcon#read 5, iclass 6, count 0 2006.190.07:36:32.65#ibcon#about to read 6, iclass 6, count 0 2006.190.07:36:32.65#ibcon#read 6, iclass 6, count 0 2006.190.07:36:32.65#ibcon#end of sib2, iclass 6, count 0 2006.190.07:36:32.65#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:36:32.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:36:32.65#ibcon#[27=USB\r\n] 2006.190.07:36:32.65#ibcon#*before write, iclass 6, count 0 2006.190.07:36:32.65#ibcon#enter sib2, iclass 6, count 0 2006.190.07:36:32.65#ibcon#flushed, iclass 6, count 0 2006.190.07:36:32.65#ibcon#about to write, iclass 6, count 0 2006.190.07:36:32.65#ibcon#wrote, iclass 6, count 0 2006.190.07:36:32.65#ibcon#about to read 3, iclass 6, count 0 2006.190.07:36:32.68#ibcon#read 3, iclass 6, count 0 2006.190.07:36:32.68#ibcon#about to read 4, iclass 6, count 0 2006.190.07:36:32.68#ibcon#read 4, iclass 6, count 0 2006.190.07:36:32.68#ibcon#about to read 5, iclass 6, count 0 2006.190.07:36:32.68#ibcon#read 5, iclass 6, count 0 2006.190.07:36:32.68#ibcon#about to read 6, iclass 6, count 0 2006.190.07:36:32.68#ibcon#read 6, iclass 6, count 0 2006.190.07:36:32.68#ibcon#end of sib2, iclass 6, count 0 2006.190.07:36:32.68#ibcon#*after write, iclass 6, count 0 2006.190.07:36:32.68#ibcon#*before return 0, iclass 6, count 0 2006.190.07:36:32.68#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:32.68#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:36:32.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:36:32.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:36:32.68$vc4f8/vabw=wide 2006.190.07:36:32.68#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.07:36:32.68#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.07:36:32.68#ibcon#ireg 8 cls_cnt 0 2006.190.07:36:32.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:32.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:32.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:32.68#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:36:32.68#ibcon#first serial, iclass 10, count 0 2006.190.07:36:32.68#ibcon#enter sib2, iclass 10, count 0 2006.190.07:36:32.68#ibcon#flushed, iclass 10, count 0 2006.190.07:36:32.68#ibcon#about to write, iclass 10, count 0 2006.190.07:36:32.68#ibcon#wrote, iclass 10, count 0 2006.190.07:36:32.68#ibcon#about to read 3, iclass 10, count 0 2006.190.07:36:32.70#ibcon#read 3, iclass 10, count 0 2006.190.07:36:32.70#ibcon#about to read 4, iclass 10, count 0 2006.190.07:36:32.70#ibcon#read 4, iclass 10, count 0 2006.190.07:36:32.70#ibcon#about to read 5, iclass 10, count 0 2006.190.07:36:32.70#ibcon#read 5, iclass 10, count 0 2006.190.07:36:32.70#ibcon#about to read 6, iclass 10, count 0 2006.190.07:36:32.70#ibcon#read 6, iclass 10, count 0 2006.190.07:36:32.70#ibcon#end of sib2, iclass 10, count 0 2006.190.07:36:32.70#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:36:32.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:36:32.70#ibcon#[25=BW32\r\n] 2006.190.07:36:32.70#ibcon#*before write, iclass 10, count 0 2006.190.07:36:32.70#ibcon#enter sib2, iclass 10, count 0 2006.190.07:36:32.70#ibcon#flushed, iclass 10, count 0 2006.190.07:36:32.70#ibcon#about to write, iclass 10, count 0 2006.190.07:36:32.70#ibcon#wrote, iclass 10, count 0 2006.190.07:36:32.70#ibcon#about to read 3, iclass 10, count 0 2006.190.07:36:32.73#ibcon#read 3, iclass 10, count 0 2006.190.07:36:32.73#ibcon#about to read 4, iclass 10, count 0 2006.190.07:36:32.73#ibcon#read 4, iclass 10, count 0 2006.190.07:36:32.73#ibcon#about to read 5, iclass 10, count 0 2006.190.07:36:32.73#ibcon#read 5, iclass 10, count 0 2006.190.07:36:32.73#ibcon#about to read 6, iclass 10, count 0 2006.190.07:36:32.73#ibcon#read 6, iclass 10, count 0 2006.190.07:36:32.73#ibcon#end of sib2, iclass 10, count 0 2006.190.07:36:32.73#ibcon#*after write, iclass 10, count 0 2006.190.07:36:32.73#ibcon#*before return 0, iclass 10, count 0 2006.190.07:36:32.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:32.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:36:32.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:36:32.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:36:32.73$vc4f8/vbbw=wide 2006.190.07:36:32.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:36:32.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:36:32.73#ibcon#ireg 8 cls_cnt 0 2006.190.07:36:32.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:36:32.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:36:32.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:36:32.80#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:36:32.80#ibcon#first serial, iclass 12, count 0 2006.190.07:36:32.80#ibcon#enter sib2, iclass 12, count 0 2006.190.07:36:32.80#ibcon#flushed, iclass 12, count 0 2006.190.07:36:32.80#ibcon#about to write, iclass 12, count 0 2006.190.07:36:32.80#ibcon#wrote, iclass 12, count 0 2006.190.07:36:32.80#ibcon#about to read 3, iclass 12, count 0 2006.190.07:36:32.82#ibcon#read 3, iclass 12, count 0 2006.190.07:36:32.82#ibcon#about to read 4, iclass 12, count 0 2006.190.07:36:32.82#ibcon#read 4, iclass 12, count 0 2006.190.07:36:32.82#ibcon#about to read 5, iclass 12, count 0 2006.190.07:36:32.82#ibcon#read 5, iclass 12, count 0 2006.190.07:36:32.82#ibcon#about to read 6, iclass 12, count 0 2006.190.07:36:32.82#ibcon#read 6, iclass 12, count 0 2006.190.07:36:32.82#ibcon#end of sib2, iclass 12, count 0 2006.190.07:36:32.82#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:36:32.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:36:32.82#ibcon#[27=BW32\r\n] 2006.190.07:36:32.82#ibcon#*before write, iclass 12, count 0 2006.190.07:36:32.82#ibcon#enter sib2, iclass 12, count 0 2006.190.07:36:32.82#ibcon#flushed, iclass 12, count 0 2006.190.07:36:32.82#ibcon#about to write, iclass 12, count 0 2006.190.07:36:32.82#ibcon#wrote, iclass 12, count 0 2006.190.07:36:32.82#ibcon#about to read 3, iclass 12, count 0 2006.190.07:36:32.85#ibcon#read 3, iclass 12, count 0 2006.190.07:36:32.85#ibcon#about to read 4, iclass 12, count 0 2006.190.07:36:32.85#ibcon#read 4, iclass 12, count 0 2006.190.07:36:32.85#ibcon#about to read 5, iclass 12, count 0 2006.190.07:36:32.85#ibcon#read 5, iclass 12, count 0 2006.190.07:36:32.85#ibcon#about to read 6, iclass 12, count 0 2006.190.07:36:32.85#ibcon#read 6, iclass 12, count 0 2006.190.07:36:32.85#ibcon#end of sib2, iclass 12, count 0 2006.190.07:36:32.85#ibcon#*after write, iclass 12, count 0 2006.190.07:36:32.85#ibcon#*before return 0, iclass 12, count 0 2006.190.07:36:32.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:36:32.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:36:32.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:36:32.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:36:32.85$4f8m12a/ifd4f 2006.190.07:36:32.85$ifd4f/lo= 2006.190.07:36:32.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:36:32.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:36:32.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:36:32.85$ifd4f/patch= 2006.190.07:36:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:36:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:36:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:36:32.85$4f8m12a/"form=m,16.000,1:2 2006.190.07:36:32.85$4f8m12a/"tpicd 2006.190.07:36:32.85$4f8m12a/echo=off 2006.190.07:36:32.85$4f8m12a/xlog=off 2006.190.07:36:32.85:!2006.190.07:37:00 2006.190.07:36:46.14#trakl#Source acquired 2006.190.07:36:48.14#flagr#flagr/antenna,acquired 2006.190.07:37:00.00:preob 2006.190.07:37:01.14/onsource/TRACKING 2006.190.07:37:01.14:!2006.190.07:37:10 2006.190.07:37:10.00:data_valid=on 2006.190.07:37:10.00:midob 2006.190.07:37:10.14/onsource/TRACKING 2006.190.07:37:10.14/wx/24.55,1012.2,100 2006.190.07:37:10.29/cable/+6.4724E-03 2006.190.07:37:11.38/va/01,08,usb,yes,48,51 2006.190.07:37:11.38/va/02,07,usb,yes,49,51 2006.190.07:37:11.38/va/03,06,usb,yes,52,52 2006.190.07:37:11.38/va/04,07,usb,yes,51,54 2006.190.07:37:11.38/va/05,07,usb,yes,56,59 2006.190.07:37:11.38/va/06,06,usb,yes,55,55 2006.190.07:37:11.38/va/07,06,usb,yes,56,56 2006.190.07:37:11.38/va/08,06,usb,yes,59,58 2006.190.07:37:11.61/valo/01,532.99,yes,locked 2006.190.07:37:11.61/valo/02,572.99,yes,locked 2006.190.07:37:11.61/valo/03,672.99,yes,locked 2006.190.07:37:11.61/valo/04,832.99,yes,locked 2006.190.07:37:11.61/valo/05,652.99,yes,locked 2006.190.07:37:11.61/valo/06,772.99,yes,locked 2006.190.07:37:11.61/valo/07,832.99,yes,locked 2006.190.07:37:11.61/valo/08,852.99,yes,locked 2006.190.07:37:12.70/vb/01,04,usb,yes,31,29 2006.190.07:37:12.70/vb/02,04,usb,yes,32,34 2006.190.07:37:12.70/vb/03,04,usb,yes,29,33 2006.190.07:37:12.70/vb/04,04,usb,yes,30,30 2006.190.07:37:12.70/vb/05,04,usb,yes,28,32 2006.190.07:37:12.70/vb/06,04,usb,yes,29,32 2006.190.07:37:12.70/vb/07,04,usb,yes,31,31 2006.190.07:37:12.70/vb/08,04,usb,yes,29,32 2006.190.07:37:12.94/vblo/01,632.99,yes,locked 2006.190.07:37:12.94/vblo/02,640.99,yes,locked 2006.190.07:37:12.94/vblo/03,656.99,yes,locked 2006.190.07:37:12.94/vblo/04,712.99,yes,locked 2006.190.07:37:12.94/vblo/05,744.99,yes,locked 2006.190.07:37:12.94/vblo/06,752.99,yes,locked 2006.190.07:37:12.94/vblo/07,734.99,yes,locked 2006.190.07:37:12.94/vblo/08,744.99,yes,locked 2006.190.07:37:13.09/vabw/8 2006.190.07:37:13.24/vbbw/8 2006.190.07:37:13.33/xfe/off,on,15.5 2006.190.07:37:13.70/ifatt/23,28,28,28 2006.190.07:37:14.07/fmout-gps/S +2.83E-07 2006.190.07:37:14.15:!2006.190.07:38:10 2006.190.07:38:10.01:data_valid=off 2006.190.07:38:10.01:postob 2006.190.07:38:10.17/cable/+6.4702E-03 2006.190.07:38:10.18/wx/24.54,1012.2,100 2006.190.07:38:11.07/fmout-gps/S +2.84E-07 2006.190.07:38:11.07:scan_name=190-0739,k06190,60 2006.190.07:38:11.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.190.07:38:11.16#flagr#flagr/antenna,new-source 2006.190.07:38:12.12:checkk5 2006.190.07:38:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:38:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:38:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:38:14.02/chk_obsdata//k5ts1/T1900737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:38:14.40/chk_obsdata//k5ts2/T1900737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:38:14.78/chk_obsdata//k5ts3/T1900737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:38:15.16/chk_obsdata//k5ts4/T1900737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:38:15.85/k5log//k5ts1_log_newline 2006.190.07:38:16.56/k5log//k5ts2_log_newline 2006.190.07:38:17.25/k5log//k5ts3_log_newline 2006.190.07:38:17.94/k5log//k5ts4_log_newline 2006.190.07:38:17.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:38:17.97:4f8m12a=1 2006.190.07:38:17.97$4f8m12a/echo=on 2006.190.07:38:17.97$4f8m12a/pcalon 2006.190.07:38:17.97$pcalon/"no phase cal control is implemented here 2006.190.07:38:17.97$4f8m12a/"tpicd=stop 2006.190.07:38:17.97$4f8m12a/vc4f8 2006.190.07:38:17.97$vc4f8/valo=1,532.99 2006.190.07:38:17.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:38:17.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:38:17.98#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:17.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:17.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:17.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:17.98#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:38:17.98#ibcon#first serial, iclass 19, count 0 2006.190.07:38:17.98#ibcon#enter sib2, iclass 19, count 0 2006.190.07:38:17.98#ibcon#flushed, iclass 19, count 0 2006.190.07:38:17.98#ibcon#about to write, iclass 19, count 0 2006.190.07:38:17.98#ibcon#wrote, iclass 19, count 0 2006.190.07:38:17.98#ibcon#about to read 3, iclass 19, count 0 2006.190.07:38:18.02#ibcon#read 3, iclass 19, count 0 2006.190.07:38:18.02#ibcon#about to read 4, iclass 19, count 0 2006.190.07:38:18.02#ibcon#read 4, iclass 19, count 0 2006.190.07:38:18.02#ibcon#about to read 5, iclass 19, count 0 2006.190.07:38:18.02#ibcon#read 5, iclass 19, count 0 2006.190.07:38:18.02#ibcon#about to read 6, iclass 19, count 0 2006.190.07:38:18.02#ibcon#read 6, iclass 19, count 0 2006.190.07:38:18.02#ibcon#end of sib2, iclass 19, count 0 2006.190.07:38:18.02#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:38:18.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:38:18.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:38:18.02#ibcon#*before write, iclass 19, count 0 2006.190.07:38:18.02#ibcon#enter sib2, iclass 19, count 0 2006.190.07:38:18.02#ibcon#flushed, iclass 19, count 0 2006.190.07:38:18.02#ibcon#about to write, iclass 19, count 0 2006.190.07:38:18.02#ibcon#wrote, iclass 19, count 0 2006.190.07:38:18.02#ibcon#about to read 3, iclass 19, count 0 2006.190.07:38:18.07#ibcon#read 3, iclass 19, count 0 2006.190.07:38:18.07#ibcon#about to read 4, iclass 19, count 0 2006.190.07:38:18.07#ibcon#read 4, iclass 19, count 0 2006.190.07:38:18.07#ibcon#about to read 5, iclass 19, count 0 2006.190.07:38:18.07#ibcon#read 5, iclass 19, count 0 2006.190.07:38:18.07#ibcon#about to read 6, iclass 19, count 0 2006.190.07:38:18.07#ibcon#read 6, iclass 19, count 0 2006.190.07:38:18.07#ibcon#end of sib2, iclass 19, count 0 2006.190.07:38:18.07#ibcon#*after write, iclass 19, count 0 2006.190.07:38:18.07#ibcon#*before return 0, iclass 19, count 0 2006.190.07:38:18.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:18.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:18.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:38:18.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:38:18.07$vc4f8/va=1,8 2006.190.07:38:18.07#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.07:38:18.07#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.07:38:18.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:18.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:18.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:18.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:18.07#ibcon#enter wrdev, iclass 21, count 2 2006.190.07:38:18.07#ibcon#first serial, iclass 21, count 2 2006.190.07:38:18.07#ibcon#enter sib2, iclass 21, count 2 2006.190.07:38:18.07#ibcon#flushed, iclass 21, count 2 2006.190.07:38:18.07#ibcon#about to write, iclass 21, count 2 2006.190.07:38:18.07#ibcon#wrote, iclass 21, count 2 2006.190.07:38:18.07#ibcon#about to read 3, iclass 21, count 2 2006.190.07:38:18.09#ibcon#read 3, iclass 21, count 2 2006.190.07:38:18.09#ibcon#about to read 4, iclass 21, count 2 2006.190.07:38:18.09#ibcon#read 4, iclass 21, count 2 2006.190.07:38:18.09#ibcon#about to read 5, iclass 21, count 2 2006.190.07:38:18.09#ibcon#read 5, iclass 21, count 2 2006.190.07:38:18.09#ibcon#about to read 6, iclass 21, count 2 2006.190.07:38:18.09#ibcon#read 6, iclass 21, count 2 2006.190.07:38:18.09#ibcon#end of sib2, iclass 21, count 2 2006.190.07:38:18.09#ibcon#*mode == 0, iclass 21, count 2 2006.190.07:38:18.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.07:38:18.09#ibcon#[25=AT01-08\r\n] 2006.190.07:38:18.09#ibcon#*before write, iclass 21, count 2 2006.190.07:38:18.09#ibcon#enter sib2, iclass 21, count 2 2006.190.07:38:18.09#ibcon#flushed, iclass 21, count 2 2006.190.07:38:18.09#ibcon#about to write, iclass 21, count 2 2006.190.07:38:18.09#ibcon#wrote, iclass 21, count 2 2006.190.07:38:18.09#ibcon#about to read 3, iclass 21, count 2 2006.190.07:38:18.12#ibcon#read 3, iclass 21, count 2 2006.190.07:38:18.12#ibcon#about to read 4, iclass 21, count 2 2006.190.07:38:18.12#ibcon#read 4, iclass 21, count 2 2006.190.07:38:18.12#ibcon#about to read 5, iclass 21, count 2 2006.190.07:38:18.12#ibcon#read 5, iclass 21, count 2 2006.190.07:38:18.12#ibcon#about to read 6, iclass 21, count 2 2006.190.07:38:18.12#ibcon#read 6, iclass 21, count 2 2006.190.07:38:18.12#ibcon#end of sib2, iclass 21, count 2 2006.190.07:38:18.12#ibcon#*after write, iclass 21, count 2 2006.190.07:38:18.12#ibcon#*before return 0, iclass 21, count 2 2006.190.07:38:18.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:18.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:18.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.07:38:18.12#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:18.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:18.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:18.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:18.24#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:38:18.24#ibcon#first serial, iclass 21, count 0 2006.190.07:38:18.24#ibcon#enter sib2, iclass 21, count 0 2006.190.07:38:18.24#ibcon#flushed, iclass 21, count 0 2006.190.07:38:18.24#ibcon#about to write, iclass 21, count 0 2006.190.07:38:18.24#ibcon#wrote, iclass 21, count 0 2006.190.07:38:18.24#ibcon#about to read 3, iclass 21, count 0 2006.190.07:38:18.26#ibcon#read 3, iclass 21, count 0 2006.190.07:38:18.26#ibcon#about to read 4, iclass 21, count 0 2006.190.07:38:18.26#ibcon#read 4, iclass 21, count 0 2006.190.07:38:18.26#ibcon#about to read 5, iclass 21, count 0 2006.190.07:38:18.26#ibcon#read 5, iclass 21, count 0 2006.190.07:38:18.26#ibcon#about to read 6, iclass 21, count 0 2006.190.07:38:18.26#ibcon#read 6, iclass 21, count 0 2006.190.07:38:18.26#ibcon#end of sib2, iclass 21, count 0 2006.190.07:38:18.26#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:38:18.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:38:18.26#ibcon#[25=USB\r\n] 2006.190.07:38:18.26#ibcon#*before write, iclass 21, count 0 2006.190.07:38:18.26#ibcon#enter sib2, iclass 21, count 0 2006.190.07:38:18.26#ibcon#flushed, iclass 21, count 0 2006.190.07:38:18.26#ibcon#about to write, iclass 21, count 0 2006.190.07:38:18.26#ibcon#wrote, iclass 21, count 0 2006.190.07:38:18.26#ibcon#about to read 3, iclass 21, count 0 2006.190.07:38:18.29#ibcon#read 3, iclass 21, count 0 2006.190.07:38:18.29#ibcon#about to read 4, iclass 21, count 0 2006.190.07:38:18.29#ibcon#read 4, iclass 21, count 0 2006.190.07:38:18.29#ibcon#about to read 5, iclass 21, count 0 2006.190.07:38:18.29#ibcon#read 5, iclass 21, count 0 2006.190.07:38:18.29#ibcon#about to read 6, iclass 21, count 0 2006.190.07:38:18.29#ibcon#read 6, iclass 21, count 0 2006.190.07:38:18.29#ibcon#end of sib2, iclass 21, count 0 2006.190.07:38:18.29#ibcon#*after write, iclass 21, count 0 2006.190.07:38:18.29#ibcon#*before return 0, iclass 21, count 0 2006.190.07:38:18.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:18.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:18.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:38:18.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:38:18.29$vc4f8/valo=2,572.99 2006.190.07:38:18.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.07:38:18.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.07:38:18.29#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:18.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:18.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:18.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:18.29#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:38:18.29#ibcon#first serial, iclass 23, count 0 2006.190.07:38:18.29#ibcon#enter sib2, iclass 23, count 0 2006.190.07:38:18.29#ibcon#flushed, iclass 23, count 0 2006.190.07:38:18.29#ibcon#about to write, iclass 23, count 0 2006.190.07:38:18.29#ibcon#wrote, iclass 23, count 0 2006.190.07:38:18.29#ibcon#about to read 3, iclass 23, count 0 2006.190.07:38:18.31#ibcon#read 3, iclass 23, count 0 2006.190.07:38:18.31#ibcon#about to read 4, iclass 23, count 0 2006.190.07:38:18.31#ibcon#read 4, iclass 23, count 0 2006.190.07:38:18.31#ibcon#about to read 5, iclass 23, count 0 2006.190.07:38:18.31#ibcon#read 5, iclass 23, count 0 2006.190.07:38:18.31#ibcon#about to read 6, iclass 23, count 0 2006.190.07:38:18.31#ibcon#read 6, iclass 23, count 0 2006.190.07:38:18.31#ibcon#end of sib2, iclass 23, count 0 2006.190.07:38:18.31#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:38:18.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:38:18.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:38:18.31#ibcon#*before write, iclass 23, count 0 2006.190.07:38:18.31#ibcon#enter sib2, iclass 23, count 0 2006.190.07:38:18.31#ibcon#flushed, iclass 23, count 0 2006.190.07:38:18.31#ibcon#about to write, iclass 23, count 0 2006.190.07:38:18.31#ibcon#wrote, iclass 23, count 0 2006.190.07:38:18.31#ibcon#about to read 3, iclass 23, count 0 2006.190.07:38:18.35#ibcon#read 3, iclass 23, count 0 2006.190.07:38:18.35#ibcon#about to read 4, iclass 23, count 0 2006.190.07:38:18.35#ibcon#read 4, iclass 23, count 0 2006.190.07:38:18.35#ibcon#about to read 5, iclass 23, count 0 2006.190.07:38:18.35#ibcon#read 5, iclass 23, count 0 2006.190.07:38:18.35#ibcon#about to read 6, iclass 23, count 0 2006.190.07:38:18.35#ibcon#read 6, iclass 23, count 0 2006.190.07:38:18.35#ibcon#end of sib2, iclass 23, count 0 2006.190.07:38:18.35#ibcon#*after write, iclass 23, count 0 2006.190.07:38:18.35#ibcon#*before return 0, iclass 23, count 0 2006.190.07:38:18.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:18.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:18.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:38:18.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:38:18.35$vc4f8/va=2,7 2006.190.07:38:18.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.07:38:18.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.07:38:18.35#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:18.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:18.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:18.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:18.41#ibcon#enter wrdev, iclass 25, count 2 2006.190.07:38:18.41#ibcon#first serial, iclass 25, count 2 2006.190.07:38:18.41#ibcon#enter sib2, iclass 25, count 2 2006.190.07:38:18.41#ibcon#flushed, iclass 25, count 2 2006.190.07:38:18.41#ibcon#about to write, iclass 25, count 2 2006.190.07:38:18.41#ibcon#wrote, iclass 25, count 2 2006.190.07:38:18.41#ibcon#about to read 3, iclass 25, count 2 2006.190.07:38:18.43#ibcon#read 3, iclass 25, count 2 2006.190.07:38:18.43#ibcon#about to read 4, iclass 25, count 2 2006.190.07:38:18.43#ibcon#read 4, iclass 25, count 2 2006.190.07:38:18.43#ibcon#about to read 5, iclass 25, count 2 2006.190.07:38:18.43#ibcon#read 5, iclass 25, count 2 2006.190.07:38:18.43#ibcon#about to read 6, iclass 25, count 2 2006.190.07:38:18.43#ibcon#read 6, iclass 25, count 2 2006.190.07:38:18.43#ibcon#end of sib2, iclass 25, count 2 2006.190.07:38:18.43#ibcon#*mode == 0, iclass 25, count 2 2006.190.07:38:18.43#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.07:38:18.43#ibcon#[25=AT02-07\r\n] 2006.190.07:38:18.43#ibcon#*before write, iclass 25, count 2 2006.190.07:38:18.43#ibcon#enter sib2, iclass 25, count 2 2006.190.07:38:18.43#ibcon#flushed, iclass 25, count 2 2006.190.07:38:18.43#ibcon#about to write, iclass 25, count 2 2006.190.07:38:18.43#ibcon#wrote, iclass 25, count 2 2006.190.07:38:18.43#ibcon#about to read 3, iclass 25, count 2 2006.190.07:38:18.46#ibcon#read 3, iclass 25, count 2 2006.190.07:38:18.46#ibcon#about to read 4, iclass 25, count 2 2006.190.07:38:18.46#ibcon#read 4, iclass 25, count 2 2006.190.07:38:18.46#ibcon#about to read 5, iclass 25, count 2 2006.190.07:38:18.46#ibcon#read 5, iclass 25, count 2 2006.190.07:38:18.46#ibcon#about to read 6, iclass 25, count 2 2006.190.07:38:18.46#ibcon#read 6, iclass 25, count 2 2006.190.07:38:18.46#ibcon#end of sib2, iclass 25, count 2 2006.190.07:38:18.46#ibcon#*after write, iclass 25, count 2 2006.190.07:38:18.46#ibcon#*before return 0, iclass 25, count 2 2006.190.07:38:18.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:18.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:18.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.07:38:18.46#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:18.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:18.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:18.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:18.58#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:38:18.58#ibcon#first serial, iclass 25, count 0 2006.190.07:38:18.58#ibcon#enter sib2, iclass 25, count 0 2006.190.07:38:18.58#ibcon#flushed, iclass 25, count 0 2006.190.07:38:18.58#ibcon#about to write, iclass 25, count 0 2006.190.07:38:18.58#ibcon#wrote, iclass 25, count 0 2006.190.07:38:18.58#ibcon#about to read 3, iclass 25, count 0 2006.190.07:38:18.60#ibcon#read 3, iclass 25, count 0 2006.190.07:38:18.60#ibcon#about to read 4, iclass 25, count 0 2006.190.07:38:18.60#ibcon#read 4, iclass 25, count 0 2006.190.07:38:18.60#ibcon#about to read 5, iclass 25, count 0 2006.190.07:38:18.60#ibcon#read 5, iclass 25, count 0 2006.190.07:38:18.60#ibcon#about to read 6, iclass 25, count 0 2006.190.07:38:18.60#ibcon#read 6, iclass 25, count 0 2006.190.07:38:18.60#ibcon#end of sib2, iclass 25, count 0 2006.190.07:38:18.60#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:38:18.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:38:18.60#ibcon#[25=USB\r\n] 2006.190.07:38:18.60#ibcon#*before write, iclass 25, count 0 2006.190.07:38:18.60#ibcon#enter sib2, iclass 25, count 0 2006.190.07:38:18.60#ibcon#flushed, iclass 25, count 0 2006.190.07:38:18.60#ibcon#about to write, iclass 25, count 0 2006.190.07:38:18.60#ibcon#wrote, iclass 25, count 0 2006.190.07:38:18.60#ibcon#about to read 3, iclass 25, count 0 2006.190.07:38:18.63#ibcon#read 3, iclass 25, count 0 2006.190.07:38:18.63#ibcon#about to read 4, iclass 25, count 0 2006.190.07:38:18.63#ibcon#read 4, iclass 25, count 0 2006.190.07:38:18.63#ibcon#about to read 5, iclass 25, count 0 2006.190.07:38:18.63#ibcon#read 5, iclass 25, count 0 2006.190.07:38:18.63#ibcon#about to read 6, iclass 25, count 0 2006.190.07:38:18.63#ibcon#read 6, iclass 25, count 0 2006.190.07:38:18.63#ibcon#end of sib2, iclass 25, count 0 2006.190.07:38:18.63#ibcon#*after write, iclass 25, count 0 2006.190.07:38:18.63#ibcon#*before return 0, iclass 25, count 0 2006.190.07:38:18.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:18.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:18.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:38:18.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:38:18.63$vc4f8/valo=3,672.99 2006.190.07:38:18.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.07:38:18.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.07:38:18.63#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:18.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:18.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:18.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:18.63#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:38:18.63#ibcon#first serial, iclass 27, count 0 2006.190.07:38:18.63#ibcon#enter sib2, iclass 27, count 0 2006.190.07:38:18.63#ibcon#flushed, iclass 27, count 0 2006.190.07:38:18.63#ibcon#about to write, iclass 27, count 0 2006.190.07:38:18.63#ibcon#wrote, iclass 27, count 0 2006.190.07:38:18.63#ibcon#about to read 3, iclass 27, count 0 2006.190.07:38:18.65#ibcon#read 3, iclass 27, count 0 2006.190.07:38:18.65#ibcon#about to read 4, iclass 27, count 0 2006.190.07:38:18.65#ibcon#read 4, iclass 27, count 0 2006.190.07:38:18.65#ibcon#about to read 5, iclass 27, count 0 2006.190.07:38:18.65#ibcon#read 5, iclass 27, count 0 2006.190.07:38:18.65#ibcon#about to read 6, iclass 27, count 0 2006.190.07:38:18.65#ibcon#read 6, iclass 27, count 0 2006.190.07:38:18.65#ibcon#end of sib2, iclass 27, count 0 2006.190.07:38:18.65#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:38:18.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:38:18.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:38:18.65#ibcon#*before write, iclass 27, count 0 2006.190.07:38:18.65#ibcon#enter sib2, iclass 27, count 0 2006.190.07:38:18.65#ibcon#flushed, iclass 27, count 0 2006.190.07:38:18.65#ibcon#about to write, iclass 27, count 0 2006.190.07:38:18.65#ibcon#wrote, iclass 27, count 0 2006.190.07:38:18.65#ibcon#about to read 3, iclass 27, count 0 2006.190.07:38:18.69#ibcon#read 3, iclass 27, count 0 2006.190.07:38:18.69#ibcon#about to read 4, iclass 27, count 0 2006.190.07:38:18.69#ibcon#read 4, iclass 27, count 0 2006.190.07:38:18.69#ibcon#about to read 5, iclass 27, count 0 2006.190.07:38:18.69#ibcon#read 5, iclass 27, count 0 2006.190.07:38:18.69#ibcon#about to read 6, iclass 27, count 0 2006.190.07:38:18.69#ibcon#read 6, iclass 27, count 0 2006.190.07:38:18.69#ibcon#end of sib2, iclass 27, count 0 2006.190.07:38:18.69#ibcon#*after write, iclass 27, count 0 2006.190.07:38:18.69#ibcon#*before return 0, iclass 27, count 0 2006.190.07:38:18.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:18.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:18.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:38:18.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:38:18.69$vc4f8/va=3,6 2006.190.07:38:18.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.07:38:18.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.07:38:18.69#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:18.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:18.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:18.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:18.75#ibcon#enter wrdev, iclass 29, count 2 2006.190.07:38:18.75#ibcon#first serial, iclass 29, count 2 2006.190.07:38:18.75#ibcon#enter sib2, iclass 29, count 2 2006.190.07:38:18.75#ibcon#flushed, iclass 29, count 2 2006.190.07:38:18.75#ibcon#about to write, iclass 29, count 2 2006.190.07:38:18.75#ibcon#wrote, iclass 29, count 2 2006.190.07:38:18.75#ibcon#about to read 3, iclass 29, count 2 2006.190.07:38:18.77#ibcon#read 3, iclass 29, count 2 2006.190.07:38:18.77#ibcon#about to read 4, iclass 29, count 2 2006.190.07:38:18.77#ibcon#read 4, iclass 29, count 2 2006.190.07:38:18.77#ibcon#about to read 5, iclass 29, count 2 2006.190.07:38:18.77#ibcon#read 5, iclass 29, count 2 2006.190.07:38:18.77#ibcon#about to read 6, iclass 29, count 2 2006.190.07:38:18.77#ibcon#read 6, iclass 29, count 2 2006.190.07:38:18.77#ibcon#end of sib2, iclass 29, count 2 2006.190.07:38:18.77#ibcon#*mode == 0, iclass 29, count 2 2006.190.07:38:18.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.07:38:18.77#ibcon#[25=AT03-06\r\n] 2006.190.07:38:18.77#ibcon#*before write, iclass 29, count 2 2006.190.07:38:18.77#ibcon#enter sib2, iclass 29, count 2 2006.190.07:38:18.77#ibcon#flushed, iclass 29, count 2 2006.190.07:38:18.77#ibcon#about to write, iclass 29, count 2 2006.190.07:38:18.77#ibcon#wrote, iclass 29, count 2 2006.190.07:38:18.77#ibcon#about to read 3, iclass 29, count 2 2006.190.07:38:18.80#ibcon#read 3, iclass 29, count 2 2006.190.07:38:18.80#ibcon#about to read 4, iclass 29, count 2 2006.190.07:38:18.80#ibcon#read 4, iclass 29, count 2 2006.190.07:38:18.80#ibcon#about to read 5, iclass 29, count 2 2006.190.07:38:18.80#ibcon#read 5, iclass 29, count 2 2006.190.07:38:18.80#ibcon#about to read 6, iclass 29, count 2 2006.190.07:38:18.80#ibcon#read 6, iclass 29, count 2 2006.190.07:38:18.80#ibcon#end of sib2, iclass 29, count 2 2006.190.07:38:18.80#ibcon#*after write, iclass 29, count 2 2006.190.07:38:18.80#ibcon#*before return 0, iclass 29, count 2 2006.190.07:38:18.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:18.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:18.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.07:38:18.80#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:18.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:18.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:18.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:18.92#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:38:18.92#ibcon#first serial, iclass 29, count 0 2006.190.07:38:18.92#ibcon#enter sib2, iclass 29, count 0 2006.190.07:38:18.92#ibcon#flushed, iclass 29, count 0 2006.190.07:38:18.92#ibcon#about to write, iclass 29, count 0 2006.190.07:38:18.92#ibcon#wrote, iclass 29, count 0 2006.190.07:38:18.92#ibcon#about to read 3, iclass 29, count 0 2006.190.07:38:18.94#ibcon#read 3, iclass 29, count 0 2006.190.07:38:18.94#ibcon#about to read 4, iclass 29, count 0 2006.190.07:38:18.94#ibcon#read 4, iclass 29, count 0 2006.190.07:38:18.94#ibcon#about to read 5, iclass 29, count 0 2006.190.07:38:18.94#ibcon#read 5, iclass 29, count 0 2006.190.07:38:18.94#ibcon#about to read 6, iclass 29, count 0 2006.190.07:38:18.94#ibcon#read 6, iclass 29, count 0 2006.190.07:38:18.94#ibcon#end of sib2, iclass 29, count 0 2006.190.07:38:18.94#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:38:18.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:38:18.94#ibcon#[25=USB\r\n] 2006.190.07:38:18.94#ibcon#*before write, iclass 29, count 0 2006.190.07:38:18.94#ibcon#enter sib2, iclass 29, count 0 2006.190.07:38:18.94#ibcon#flushed, iclass 29, count 0 2006.190.07:38:18.94#ibcon#about to write, iclass 29, count 0 2006.190.07:38:18.94#ibcon#wrote, iclass 29, count 0 2006.190.07:38:18.94#ibcon#about to read 3, iclass 29, count 0 2006.190.07:38:18.97#ibcon#read 3, iclass 29, count 0 2006.190.07:38:18.97#ibcon#about to read 4, iclass 29, count 0 2006.190.07:38:18.97#ibcon#read 4, iclass 29, count 0 2006.190.07:38:18.97#ibcon#about to read 5, iclass 29, count 0 2006.190.07:38:18.97#ibcon#read 5, iclass 29, count 0 2006.190.07:38:18.97#ibcon#about to read 6, iclass 29, count 0 2006.190.07:38:18.97#ibcon#read 6, iclass 29, count 0 2006.190.07:38:18.97#ibcon#end of sib2, iclass 29, count 0 2006.190.07:38:18.97#ibcon#*after write, iclass 29, count 0 2006.190.07:38:18.97#ibcon#*before return 0, iclass 29, count 0 2006.190.07:38:18.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:18.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:18.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:38:18.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:38:18.97$vc4f8/valo=4,832.99 2006.190.07:38:18.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.07:38:18.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.07:38:18.97#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:18.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:18.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:18.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:18.97#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:38:18.97#ibcon#first serial, iclass 31, count 0 2006.190.07:38:18.97#ibcon#enter sib2, iclass 31, count 0 2006.190.07:38:18.97#ibcon#flushed, iclass 31, count 0 2006.190.07:38:18.97#ibcon#about to write, iclass 31, count 0 2006.190.07:38:18.97#ibcon#wrote, iclass 31, count 0 2006.190.07:38:18.97#ibcon#about to read 3, iclass 31, count 0 2006.190.07:38:18.99#ibcon#read 3, iclass 31, count 0 2006.190.07:38:18.99#ibcon#about to read 4, iclass 31, count 0 2006.190.07:38:18.99#ibcon#read 4, iclass 31, count 0 2006.190.07:38:18.99#ibcon#about to read 5, iclass 31, count 0 2006.190.07:38:18.99#ibcon#read 5, iclass 31, count 0 2006.190.07:38:18.99#ibcon#about to read 6, iclass 31, count 0 2006.190.07:38:18.99#ibcon#read 6, iclass 31, count 0 2006.190.07:38:18.99#ibcon#end of sib2, iclass 31, count 0 2006.190.07:38:18.99#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:38:18.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:38:18.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:38:18.99#ibcon#*before write, iclass 31, count 0 2006.190.07:38:18.99#ibcon#enter sib2, iclass 31, count 0 2006.190.07:38:18.99#ibcon#flushed, iclass 31, count 0 2006.190.07:38:18.99#ibcon#about to write, iclass 31, count 0 2006.190.07:38:18.99#ibcon#wrote, iclass 31, count 0 2006.190.07:38:18.99#ibcon#about to read 3, iclass 31, count 0 2006.190.07:38:19.03#ibcon#read 3, iclass 31, count 0 2006.190.07:38:19.03#ibcon#about to read 4, iclass 31, count 0 2006.190.07:38:19.03#ibcon#read 4, iclass 31, count 0 2006.190.07:38:19.03#ibcon#about to read 5, iclass 31, count 0 2006.190.07:38:19.03#ibcon#read 5, iclass 31, count 0 2006.190.07:38:19.03#ibcon#about to read 6, iclass 31, count 0 2006.190.07:38:19.03#ibcon#read 6, iclass 31, count 0 2006.190.07:38:19.03#ibcon#end of sib2, iclass 31, count 0 2006.190.07:38:19.03#ibcon#*after write, iclass 31, count 0 2006.190.07:38:19.03#ibcon#*before return 0, iclass 31, count 0 2006.190.07:38:19.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:19.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:19.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:38:19.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:38:19.03$vc4f8/va=4,7 2006.190.07:38:19.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.190.07:38:19.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.190.07:38:19.03#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:19.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:19.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:19.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:19.09#ibcon#enter wrdev, iclass 33, count 2 2006.190.07:38:19.09#ibcon#first serial, iclass 33, count 2 2006.190.07:38:19.09#ibcon#enter sib2, iclass 33, count 2 2006.190.07:38:19.09#ibcon#flushed, iclass 33, count 2 2006.190.07:38:19.09#ibcon#about to write, iclass 33, count 2 2006.190.07:38:19.09#ibcon#wrote, iclass 33, count 2 2006.190.07:38:19.09#ibcon#about to read 3, iclass 33, count 2 2006.190.07:38:19.11#ibcon#read 3, iclass 33, count 2 2006.190.07:38:19.11#ibcon#about to read 4, iclass 33, count 2 2006.190.07:38:19.11#ibcon#read 4, iclass 33, count 2 2006.190.07:38:19.11#ibcon#about to read 5, iclass 33, count 2 2006.190.07:38:19.11#ibcon#read 5, iclass 33, count 2 2006.190.07:38:19.11#ibcon#about to read 6, iclass 33, count 2 2006.190.07:38:19.11#ibcon#read 6, iclass 33, count 2 2006.190.07:38:19.11#ibcon#end of sib2, iclass 33, count 2 2006.190.07:38:19.11#ibcon#*mode == 0, iclass 33, count 2 2006.190.07:38:19.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.190.07:38:19.11#ibcon#[25=AT04-07\r\n] 2006.190.07:38:19.11#ibcon#*before write, iclass 33, count 2 2006.190.07:38:19.11#ibcon#enter sib2, iclass 33, count 2 2006.190.07:38:19.11#ibcon#flushed, iclass 33, count 2 2006.190.07:38:19.11#ibcon#about to write, iclass 33, count 2 2006.190.07:38:19.11#ibcon#wrote, iclass 33, count 2 2006.190.07:38:19.11#ibcon#about to read 3, iclass 33, count 2 2006.190.07:38:19.14#ibcon#read 3, iclass 33, count 2 2006.190.07:38:19.14#ibcon#about to read 4, iclass 33, count 2 2006.190.07:38:19.14#ibcon#read 4, iclass 33, count 2 2006.190.07:38:19.14#ibcon#about to read 5, iclass 33, count 2 2006.190.07:38:19.14#ibcon#read 5, iclass 33, count 2 2006.190.07:38:19.14#ibcon#about to read 6, iclass 33, count 2 2006.190.07:38:19.14#ibcon#read 6, iclass 33, count 2 2006.190.07:38:19.14#ibcon#end of sib2, iclass 33, count 2 2006.190.07:38:19.14#ibcon#*after write, iclass 33, count 2 2006.190.07:38:19.14#ibcon#*before return 0, iclass 33, count 2 2006.190.07:38:19.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:19.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:19.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.190.07:38:19.14#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:19.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:19.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:19.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:19.26#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:38:19.26#ibcon#first serial, iclass 33, count 0 2006.190.07:38:19.26#ibcon#enter sib2, iclass 33, count 0 2006.190.07:38:19.26#ibcon#flushed, iclass 33, count 0 2006.190.07:38:19.26#ibcon#about to write, iclass 33, count 0 2006.190.07:38:19.26#ibcon#wrote, iclass 33, count 0 2006.190.07:38:19.26#ibcon#about to read 3, iclass 33, count 0 2006.190.07:38:19.28#ibcon#read 3, iclass 33, count 0 2006.190.07:38:19.28#ibcon#about to read 4, iclass 33, count 0 2006.190.07:38:19.28#ibcon#read 4, iclass 33, count 0 2006.190.07:38:19.28#ibcon#about to read 5, iclass 33, count 0 2006.190.07:38:19.28#ibcon#read 5, iclass 33, count 0 2006.190.07:38:19.28#ibcon#about to read 6, iclass 33, count 0 2006.190.07:38:19.28#ibcon#read 6, iclass 33, count 0 2006.190.07:38:19.28#ibcon#end of sib2, iclass 33, count 0 2006.190.07:38:19.28#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:38:19.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:38:19.28#ibcon#[25=USB\r\n] 2006.190.07:38:19.28#ibcon#*before write, iclass 33, count 0 2006.190.07:38:19.28#ibcon#enter sib2, iclass 33, count 0 2006.190.07:38:19.28#ibcon#flushed, iclass 33, count 0 2006.190.07:38:19.28#ibcon#about to write, iclass 33, count 0 2006.190.07:38:19.28#ibcon#wrote, iclass 33, count 0 2006.190.07:38:19.28#ibcon#about to read 3, iclass 33, count 0 2006.190.07:38:19.31#ibcon#read 3, iclass 33, count 0 2006.190.07:38:19.31#ibcon#about to read 4, iclass 33, count 0 2006.190.07:38:19.31#ibcon#read 4, iclass 33, count 0 2006.190.07:38:19.31#ibcon#about to read 5, iclass 33, count 0 2006.190.07:38:19.31#ibcon#read 5, iclass 33, count 0 2006.190.07:38:19.31#ibcon#about to read 6, iclass 33, count 0 2006.190.07:38:19.31#ibcon#read 6, iclass 33, count 0 2006.190.07:38:19.31#ibcon#end of sib2, iclass 33, count 0 2006.190.07:38:19.31#ibcon#*after write, iclass 33, count 0 2006.190.07:38:19.31#ibcon#*before return 0, iclass 33, count 0 2006.190.07:38:19.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:19.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:19.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:38:19.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:38:19.31$vc4f8/valo=5,652.99 2006.190.07:38:19.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.07:38:19.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.07:38:19.31#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:19.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:19.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:19.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:19.31#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:38:19.31#ibcon#first serial, iclass 35, count 0 2006.190.07:38:19.31#ibcon#enter sib2, iclass 35, count 0 2006.190.07:38:19.31#ibcon#flushed, iclass 35, count 0 2006.190.07:38:19.31#ibcon#about to write, iclass 35, count 0 2006.190.07:38:19.31#ibcon#wrote, iclass 35, count 0 2006.190.07:38:19.31#ibcon#about to read 3, iclass 35, count 0 2006.190.07:38:19.33#ibcon#read 3, iclass 35, count 0 2006.190.07:38:19.33#ibcon#about to read 4, iclass 35, count 0 2006.190.07:38:19.33#ibcon#read 4, iclass 35, count 0 2006.190.07:38:19.33#ibcon#about to read 5, iclass 35, count 0 2006.190.07:38:19.33#ibcon#read 5, iclass 35, count 0 2006.190.07:38:19.33#ibcon#about to read 6, iclass 35, count 0 2006.190.07:38:19.33#ibcon#read 6, iclass 35, count 0 2006.190.07:38:19.33#ibcon#end of sib2, iclass 35, count 0 2006.190.07:38:19.33#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:38:19.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:38:19.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:38:19.33#ibcon#*before write, iclass 35, count 0 2006.190.07:38:19.33#ibcon#enter sib2, iclass 35, count 0 2006.190.07:38:19.33#ibcon#flushed, iclass 35, count 0 2006.190.07:38:19.33#ibcon#about to write, iclass 35, count 0 2006.190.07:38:19.33#ibcon#wrote, iclass 35, count 0 2006.190.07:38:19.33#ibcon#about to read 3, iclass 35, count 0 2006.190.07:38:19.37#ibcon#read 3, iclass 35, count 0 2006.190.07:38:19.37#ibcon#about to read 4, iclass 35, count 0 2006.190.07:38:19.37#ibcon#read 4, iclass 35, count 0 2006.190.07:38:19.37#ibcon#about to read 5, iclass 35, count 0 2006.190.07:38:19.37#ibcon#read 5, iclass 35, count 0 2006.190.07:38:19.37#ibcon#about to read 6, iclass 35, count 0 2006.190.07:38:19.37#ibcon#read 6, iclass 35, count 0 2006.190.07:38:19.37#ibcon#end of sib2, iclass 35, count 0 2006.190.07:38:19.37#ibcon#*after write, iclass 35, count 0 2006.190.07:38:19.37#ibcon#*before return 0, iclass 35, count 0 2006.190.07:38:19.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:19.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:19.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:38:19.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:38:19.37$vc4f8/va=5,7 2006.190.07:38:19.37#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.07:38:19.37#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.07:38:19.37#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:19.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:19.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:19.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:19.43#ibcon#enter wrdev, iclass 37, count 2 2006.190.07:38:19.43#ibcon#first serial, iclass 37, count 2 2006.190.07:38:19.43#ibcon#enter sib2, iclass 37, count 2 2006.190.07:38:19.43#ibcon#flushed, iclass 37, count 2 2006.190.07:38:19.43#ibcon#about to write, iclass 37, count 2 2006.190.07:38:19.43#ibcon#wrote, iclass 37, count 2 2006.190.07:38:19.43#ibcon#about to read 3, iclass 37, count 2 2006.190.07:38:19.45#ibcon#read 3, iclass 37, count 2 2006.190.07:38:19.45#ibcon#about to read 4, iclass 37, count 2 2006.190.07:38:19.45#ibcon#read 4, iclass 37, count 2 2006.190.07:38:19.45#ibcon#about to read 5, iclass 37, count 2 2006.190.07:38:19.45#ibcon#read 5, iclass 37, count 2 2006.190.07:38:19.45#ibcon#about to read 6, iclass 37, count 2 2006.190.07:38:19.45#ibcon#read 6, iclass 37, count 2 2006.190.07:38:19.45#ibcon#end of sib2, iclass 37, count 2 2006.190.07:38:19.45#ibcon#*mode == 0, iclass 37, count 2 2006.190.07:38:19.45#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.07:38:19.45#ibcon#[25=AT05-07\r\n] 2006.190.07:38:19.45#ibcon#*before write, iclass 37, count 2 2006.190.07:38:19.45#ibcon#enter sib2, iclass 37, count 2 2006.190.07:38:19.45#ibcon#flushed, iclass 37, count 2 2006.190.07:38:19.45#ibcon#about to write, iclass 37, count 2 2006.190.07:38:19.45#ibcon#wrote, iclass 37, count 2 2006.190.07:38:19.45#ibcon#about to read 3, iclass 37, count 2 2006.190.07:38:19.48#ibcon#read 3, iclass 37, count 2 2006.190.07:38:19.48#ibcon#about to read 4, iclass 37, count 2 2006.190.07:38:19.48#ibcon#read 4, iclass 37, count 2 2006.190.07:38:19.48#ibcon#about to read 5, iclass 37, count 2 2006.190.07:38:19.48#ibcon#read 5, iclass 37, count 2 2006.190.07:38:19.48#ibcon#about to read 6, iclass 37, count 2 2006.190.07:38:19.48#ibcon#read 6, iclass 37, count 2 2006.190.07:38:19.48#ibcon#end of sib2, iclass 37, count 2 2006.190.07:38:19.48#ibcon#*after write, iclass 37, count 2 2006.190.07:38:19.48#ibcon#*before return 0, iclass 37, count 2 2006.190.07:38:19.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:19.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:19.48#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.07:38:19.48#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:19.48#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:19.60#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:19.60#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:19.60#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:38:19.60#ibcon#first serial, iclass 37, count 0 2006.190.07:38:19.60#ibcon#enter sib2, iclass 37, count 0 2006.190.07:38:19.60#ibcon#flushed, iclass 37, count 0 2006.190.07:38:19.60#ibcon#about to write, iclass 37, count 0 2006.190.07:38:19.60#ibcon#wrote, iclass 37, count 0 2006.190.07:38:19.60#ibcon#about to read 3, iclass 37, count 0 2006.190.07:38:19.62#ibcon#read 3, iclass 37, count 0 2006.190.07:38:19.62#ibcon#about to read 4, iclass 37, count 0 2006.190.07:38:19.62#ibcon#read 4, iclass 37, count 0 2006.190.07:38:19.62#ibcon#about to read 5, iclass 37, count 0 2006.190.07:38:19.62#ibcon#read 5, iclass 37, count 0 2006.190.07:38:19.62#ibcon#about to read 6, iclass 37, count 0 2006.190.07:38:19.62#ibcon#read 6, iclass 37, count 0 2006.190.07:38:19.62#ibcon#end of sib2, iclass 37, count 0 2006.190.07:38:19.62#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:38:19.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:38:19.62#ibcon#[25=USB\r\n] 2006.190.07:38:19.62#ibcon#*before write, iclass 37, count 0 2006.190.07:38:19.62#ibcon#enter sib2, iclass 37, count 0 2006.190.07:38:19.62#ibcon#flushed, iclass 37, count 0 2006.190.07:38:19.62#ibcon#about to write, iclass 37, count 0 2006.190.07:38:19.62#ibcon#wrote, iclass 37, count 0 2006.190.07:38:19.62#ibcon#about to read 3, iclass 37, count 0 2006.190.07:38:19.65#ibcon#read 3, iclass 37, count 0 2006.190.07:38:19.65#ibcon#about to read 4, iclass 37, count 0 2006.190.07:38:19.65#ibcon#read 4, iclass 37, count 0 2006.190.07:38:19.65#ibcon#about to read 5, iclass 37, count 0 2006.190.07:38:19.65#ibcon#read 5, iclass 37, count 0 2006.190.07:38:19.65#ibcon#about to read 6, iclass 37, count 0 2006.190.07:38:19.65#ibcon#read 6, iclass 37, count 0 2006.190.07:38:19.65#ibcon#end of sib2, iclass 37, count 0 2006.190.07:38:19.65#ibcon#*after write, iclass 37, count 0 2006.190.07:38:19.65#ibcon#*before return 0, iclass 37, count 0 2006.190.07:38:19.65#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:19.65#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:19.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:38:19.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:38:19.65$vc4f8/valo=6,772.99 2006.190.07:38:19.65#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.07:38:19.65#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.07:38:19.65#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:19.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:19.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:19.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:19.65#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:38:19.65#ibcon#first serial, iclass 39, count 0 2006.190.07:38:19.65#ibcon#enter sib2, iclass 39, count 0 2006.190.07:38:19.65#ibcon#flushed, iclass 39, count 0 2006.190.07:38:19.65#ibcon#about to write, iclass 39, count 0 2006.190.07:38:19.65#ibcon#wrote, iclass 39, count 0 2006.190.07:38:19.65#ibcon#about to read 3, iclass 39, count 0 2006.190.07:38:19.67#ibcon#read 3, iclass 39, count 0 2006.190.07:38:19.67#ibcon#about to read 4, iclass 39, count 0 2006.190.07:38:19.67#ibcon#read 4, iclass 39, count 0 2006.190.07:38:19.67#ibcon#about to read 5, iclass 39, count 0 2006.190.07:38:19.67#ibcon#read 5, iclass 39, count 0 2006.190.07:38:19.67#ibcon#about to read 6, iclass 39, count 0 2006.190.07:38:19.67#ibcon#read 6, iclass 39, count 0 2006.190.07:38:19.67#ibcon#end of sib2, iclass 39, count 0 2006.190.07:38:19.67#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:38:19.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:38:19.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:38:19.67#ibcon#*before write, iclass 39, count 0 2006.190.07:38:19.67#ibcon#enter sib2, iclass 39, count 0 2006.190.07:38:19.67#ibcon#flushed, iclass 39, count 0 2006.190.07:38:19.67#ibcon#about to write, iclass 39, count 0 2006.190.07:38:19.67#ibcon#wrote, iclass 39, count 0 2006.190.07:38:19.67#ibcon#about to read 3, iclass 39, count 0 2006.190.07:38:19.71#ibcon#read 3, iclass 39, count 0 2006.190.07:38:19.71#ibcon#about to read 4, iclass 39, count 0 2006.190.07:38:19.71#ibcon#read 4, iclass 39, count 0 2006.190.07:38:19.71#ibcon#about to read 5, iclass 39, count 0 2006.190.07:38:19.71#ibcon#read 5, iclass 39, count 0 2006.190.07:38:19.71#ibcon#about to read 6, iclass 39, count 0 2006.190.07:38:19.71#ibcon#read 6, iclass 39, count 0 2006.190.07:38:19.71#ibcon#end of sib2, iclass 39, count 0 2006.190.07:38:19.71#ibcon#*after write, iclass 39, count 0 2006.190.07:38:19.71#ibcon#*before return 0, iclass 39, count 0 2006.190.07:38:19.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:19.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:19.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:38:19.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:38:19.71$vc4f8/va=6,6 2006.190.07:38:19.71#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.07:38:19.71#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.07:38:19.71#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:19.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:38:19.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:38:19.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:38:19.77#ibcon#enter wrdev, iclass 3, count 2 2006.190.07:38:19.77#ibcon#first serial, iclass 3, count 2 2006.190.07:38:19.77#ibcon#enter sib2, iclass 3, count 2 2006.190.07:38:19.77#ibcon#flushed, iclass 3, count 2 2006.190.07:38:19.77#ibcon#about to write, iclass 3, count 2 2006.190.07:38:19.77#ibcon#wrote, iclass 3, count 2 2006.190.07:38:19.77#ibcon#about to read 3, iclass 3, count 2 2006.190.07:38:19.79#ibcon#read 3, iclass 3, count 2 2006.190.07:38:19.79#ibcon#about to read 4, iclass 3, count 2 2006.190.07:38:19.79#ibcon#read 4, iclass 3, count 2 2006.190.07:38:19.79#ibcon#about to read 5, iclass 3, count 2 2006.190.07:38:19.79#ibcon#read 5, iclass 3, count 2 2006.190.07:38:19.79#ibcon#about to read 6, iclass 3, count 2 2006.190.07:38:19.79#ibcon#read 6, iclass 3, count 2 2006.190.07:38:19.79#ibcon#end of sib2, iclass 3, count 2 2006.190.07:38:19.79#ibcon#*mode == 0, iclass 3, count 2 2006.190.07:38:19.79#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.07:38:19.79#ibcon#[25=AT06-06\r\n] 2006.190.07:38:19.79#ibcon#*before write, iclass 3, count 2 2006.190.07:38:19.79#ibcon#enter sib2, iclass 3, count 2 2006.190.07:38:19.79#ibcon#flushed, iclass 3, count 2 2006.190.07:38:19.79#ibcon#about to write, iclass 3, count 2 2006.190.07:38:19.79#ibcon#wrote, iclass 3, count 2 2006.190.07:38:19.79#ibcon#about to read 3, iclass 3, count 2 2006.190.07:38:19.82#ibcon#read 3, iclass 3, count 2 2006.190.07:38:19.82#ibcon#about to read 4, iclass 3, count 2 2006.190.07:38:19.82#ibcon#read 4, iclass 3, count 2 2006.190.07:38:19.82#ibcon#about to read 5, iclass 3, count 2 2006.190.07:38:19.82#ibcon#read 5, iclass 3, count 2 2006.190.07:38:19.82#ibcon#about to read 6, iclass 3, count 2 2006.190.07:38:19.82#ibcon#read 6, iclass 3, count 2 2006.190.07:38:19.82#ibcon#end of sib2, iclass 3, count 2 2006.190.07:38:19.82#ibcon#*after write, iclass 3, count 2 2006.190.07:38:19.82#ibcon#*before return 0, iclass 3, count 2 2006.190.07:38:19.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:38:19.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:38:19.82#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.07:38:19.82#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:19.82#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:38:19.94#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:38:19.94#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:38:19.94#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:38:19.94#ibcon#first serial, iclass 3, count 0 2006.190.07:38:19.94#ibcon#enter sib2, iclass 3, count 0 2006.190.07:38:19.94#ibcon#flushed, iclass 3, count 0 2006.190.07:38:19.94#ibcon#about to write, iclass 3, count 0 2006.190.07:38:19.94#ibcon#wrote, iclass 3, count 0 2006.190.07:38:19.94#ibcon#about to read 3, iclass 3, count 0 2006.190.07:38:19.96#ibcon#read 3, iclass 3, count 0 2006.190.07:38:19.96#ibcon#about to read 4, iclass 3, count 0 2006.190.07:38:19.96#ibcon#read 4, iclass 3, count 0 2006.190.07:38:19.96#ibcon#about to read 5, iclass 3, count 0 2006.190.07:38:19.96#ibcon#read 5, iclass 3, count 0 2006.190.07:38:19.96#ibcon#about to read 6, iclass 3, count 0 2006.190.07:38:19.96#ibcon#read 6, iclass 3, count 0 2006.190.07:38:19.96#ibcon#end of sib2, iclass 3, count 0 2006.190.07:38:19.96#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:38:19.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:38:19.96#ibcon#[25=USB\r\n] 2006.190.07:38:19.96#ibcon#*before write, iclass 3, count 0 2006.190.07:38:19.96#ibcon#enter sib2, iclass 3, count 0 2006.190.07:38:19.96#ibcon#flushed, iclass 3, count 0 2006.190.07:38:19.96#ibcon#about to write, iclass 3, count 0 2006.190.07:38:19.96#ibcon#wrote, iclass 3, count 0 2006.190.07:38:19.96#ibcon#about to read 3, iclass 3, count 0 2006.190.07:38:19.99#ibcon#read 3, iclass 3, count 0 2006.190.07:38:19.99#ibcon#about to read 4, iclass 3, count 0 2006.190.07:38:19.99#ibcon#read 4, iclass 3, count 0 2006.190.07:38:19.99#ibcon#about to read 5, iclass 3, count 0 2006.190.07:38:19.99#ibcon#read 5, iclass 3, count 0 2006.190.07:38:19.99#ibcon#about to read 6, iclass 3, count 0 2006.190.07:38:19.99#ibcon#read 6, iclass 3, count 0 2006.190.07:38:19.99#ibcon#end of sib2, iclass 3, count 0 2006.190.07:38:19.99#ibcon#*after write, iclass 3, count 0 2006.190.07:38:19.99#ibcon#*before return 0, iclass 3, count 0 2006.190.07:38:19.99#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:38:19.99#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:38:19.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:38:19.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:38:19.99$vc4f8/valo=7,832.99 2006.190.07:38:19.99#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.07:38:19.99#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.07:38:19.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:19.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:38:19.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:38:19.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:38:19.99#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:38:19.99#ibcon#first serial, iclass 5, count 0 2006.190.07:38:19.99#ibcon#enter sib2, iclass 5, count 0 2006.190.07:38:19.99#ibcon#flushed, iclass 5, count 0 2006.190.07:38:19.99#ibcon#about to write, iclass 5, count 0 2006.190.07:38:19.99#ibcon#wrote, iclass 5, count 0 2006.190.07:38:19.99#ibcon#about to read 3, iclass 5, count 0 2006.190.07:38:20.01#ibcon#read 3, iclass 5, count 0 2006.190.07:38:20.01#ibcon#about to read 4, iclass 5, count 0 2006.190.07:38:20.01#ibcon#read 4, iclass 5, count 0 2006.190.07:38:20.01#ibcon#about to read 5, iclass 5, count 0 2006.190.07:38:20.01#ibcon#read 5, iclass 5, count 0 2006.190.07:38:20.01#ibcon#about to read 6, iclass 5, count 0 2006.190.07:38:20.01#ibcon#read 6, iclass 5, count 0 2006.190.07:38:20.01#ibcon#end of sib2, iclass 5, count 0 2006.190.07:38:20.01#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:38:20.01#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:38:20.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:38:20.01#ibcon#*before write, iclass 5, count 0 2006.190.07:38:20.01#ibcon#enter sib2, iclass 5, count 0 2006.190.07:38:20.01#ibcon#flushed, iclass 5, count 0 2006.190.07:38:20.01#ibcon#about to write, iclass 5, count 0 2006.190.07:38:20.01#ibcon#wrote, iclass 5, count 0 2006.190.07:38:20.01#ibcon#about to read 3, iclass 5, count 0 2006.190.07:38:20.05#ibcon#read 3, iclass 5, count 0 2006.190.07:38:20.05#ibcon#about to read 4, iclass 5, count 0 2006.190.07:38:20.05#ibcon#read 4, iclass 5, count 0 2006.190.07:38:20.05#ibcon#about to read 5, iclass 5, count 0 2006.190.07:38:20.05#ibcon#read 5, iclass 5, count 0 2006.190.07:38:20.05#ibcon#about to read 6, iclass 5, count 0 2006.190.07:38:20.05#ibcon#read 6, iclass 5, count 0 2006.190.07:38:20.05#ibcon#end of sib2, iclass 5, count 0 2006.190.07:38:20.05#ibcon#*after write, iclass 5, count 0 2006.190.07:38:20.05#ibcon#*before return 0, iclass 5, count 0 2006.190.07:38:20.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:38:20.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:38:20.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:38:20.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:38:20.05$vc4f8/va=7,6 2006.190.07:38:20.05#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.07:38:20.05#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.07:38:20.05#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:20.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:38:20.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:38:20.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:38:20.11#ibcon#enter wrdev, iclass 7, count 2 2006.190.07:38:20.11#ibcon#first serial, iclass 7, count 2 2006.190.07:38:20.11#ibcon#enter sib2, iclass 7, count 2 2006.190.07:38:20.11#ibcon#flushed, iclass 7, count 2 2006.190.07:38:20.11#ibcon#about to write, iclass 7, count 2 2006.190.07:38:20.11#ibcon#wrote, iclass 7, count 2 2006.190.07:38:20.11#ibcon#about to read 3, iclass 7, count 2 2006.190.07:38:20.13#ibcon#read 3, iclass 7, count 2 2006.190.07:38:20.13#ibcon#about to read 4, iclass 7, count 2 2006.190.07:38:20.13#ibcon#read 4, iclass 7, count 2 2006.190.07:38:20.13#ibcon#about to read 5, iclass 7, count 2 2006.190.07:38:20.13#ibcon#read 5, iclass 7, count 2 2006.190.07:38:20.13#ibcon#about to read 6, iclass 7, count 2 2006.190.07:38:20.13#ibcon#read 6, iclass 7, count 2 2006.190.07:38:20.13#ibcon#end of sib2, iclass 7, count 2 2006.190.07:38:20.13#ibcon#*mode == 0, iclass 7, count 2 2006.190.07:38:20.13#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.07:38:20.13#ibcon#[25=AT07-06\r\n] 2006.190.07:38:20.13#ibcon#*before write, iclass 7, count 2 2006.190.07:38:20.13#ibcon#enter sib2, iclass 7, count 2 2006.190.07:38:20.13#ibcon#flushed, iclass 7, count 2 2006.190.07:38:20.13#ibcon#about to write, iclass 7, count 2 2006.190.07:38:20.13#ibcon#wrote, iclass 7, count 2 2006.190.07:38:20.13#ibcon#about to read 3, iclass 7, count 2 2006.190.07:38:20.16#ibcon#read 3, iclass 7, count 2 2006.190.07:38:20.16#ibcon#about to read 4, iclass 7, count 2 2006.190.07:38:20.16#ibcon#read 4, iclass 7, count 2 2006.190.07:38:20.16#ibcon#about to read 5, iclass 7, count 2 2006.190.07:38:20.16#ibcon#read 5, iclass 7, count 2 2006.190.07:38:20.16#ibcon#about to read 6, iclass 7, count 2 2006.190.07:38:20.16#ibcon#read 6, iclass 7, count 2 2006.190.07:38:20.16#ibcon#end of sib2, iclass 7, count 2 2006.190.07:38:20.16#ibcon#*after write, iclass 7, count 2 2006.190.07:38:20.16#ibcon#*before return 0, iclass 7, count 2 2006.190.07:38:20.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:38:20.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:38:20.16#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.07:38:20.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:20.16#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:38:20.28#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:38:20.28#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:38:20.28#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:38:20.28#ibcon#first serial, iclass 7, count 0 2006.190.07:38:20.28#ibcon#enter sib2, iclass 7, count 0 2006.190.07:38:20.28#ibcon#flushed, iclass 7, count 0 2006.190.07:38:20.28#ibcon#about to write, iclass 7, count 0 2006.190.07:38:20.28#ibcon#wrote, iclass 7, count 0 2006.190.07:38:20.28#ibcon#about to read 3, iclass 7, count 0 2006.190.07:38:20.30#ibcon#read 3, iclass 7, count 0 2006.190.07:38:20.30#ibcon#about to read 4, iclass 7, count 0 2006.190.07:38:20.30#ibcon#read 4, iclass 7, count 0 2006.190.07:38:20.30#ibcon#about to read 5, iclass 7, count 0 2006.190.07:38:20.30#ibcon#read 5, iclass 7, count 0 2006.190.07:38:20.30#ibcon#about to read 6, iclass 7, count 0 2006.190.07:38:20.30#ibcon#read 6, iclass 7, count 0 2006.190.07:38:20.30#ibcon#end of sib2, iclass 7, count 0 2006.190.07:38:20.30#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:38:20.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:38:20.30#ibcon#[25=USB\r\n] 2006.190.07:38:20.30#ibcon#*before write, iclass 7, count 0 2006.190.07:38:20.30#ibcon#enter sib2, iclass 7, count 0 2006.190.07:38:20.30#ibcon#flushed, iclass 7, count 0 2006.190.07:38:20.30#ibcon#about to write, iclass 7, count 0 2006.190.07:38:20.30#ibcon#wrote, iclass 7, count 0 2006.190.07:38:20.30#ibcon#about to read 3, iclass 7, count 0 2006.190.07:38:20.33#ibcon#read 3, iclass 7, count 0 2006.190.07:38:20.33#ibcon#about to read 4, iclass 7, count 0 2006.190.07:38:20.33#ibcon#read 4, iclass 7, count 0 2006.190.07:38:20.33#ibcon#about to read 5, iclass 7, count 0 2006.190.07:38:20.33#ibcon#read 5, iclass 7, count 0 2006.190.07:38:20.33#ibcon#about to read 6, iclass 7, count 0 2006.190.07:38:20.33#ibcon#read 6, iclass 7, count 0 2006.190.07:38:20.33#ibcon#end of sib2, iclass 7, count 0 2006.190.07:38:20.33#ibcon#*after write, iclass 7, count 0 2006.190.07:38:20.33#ibcon#*before return 0, iclass 7, count 0 2006.190.07:38:20.33#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:38:20.33#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:38:20.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:38:20.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:38:20.33$vc4f8/valo=8,852.99 2006.190.07:38:20.33#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.07:38:20.33#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.07:38:20.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:20.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:38:20.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:38:20.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:38:20.33#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:38:20.33#ibcon#first serial, iclass 11, count 0 2006.190.07:38:20.33#ibcon#enter sib2, iclass 11, count 0 2006.190.07:38:20.33#ibcon#flushed, iclass 11, count 0 2006.190.07:38:20.33#ibcon#about to write, iclass 11, count 0 2006.190.07:38:20.33#ibcon#wrote, iclass 11, count 0 2006.190.07:38:20.33#ibcon#about to read 3, iclass 11, count 0 2006.190.07:38:20.35#ibcon#read 3, iclass 11, count 0 2006.190.07:38:20.35#ibcon#about to read 4, iclass 11, count 0 2006.190.07:38:20.35#ibcon#read 4, iclass 11, count 0 2006.190.07:38:20.35#ibcon#about to read 5, iclass 11, count 0 2006.190.07:38:20.35#ibcon#read 5, iclass 11, count 0 2006.190.07:38:20.35#ibcon#about to read 6, iclass 11, count 0 2006.190.07:38:20.35#ibcon#read 6, iclass 11, count 0 2006.190.07:38:20.35#ibcon#end of sib2, iclass 11, count 0 2006.190.07:38:20.35#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:38:20.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:38:20.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:38:20.35#ibcon#*before write, iclass 11, count 0 2006.190.07:38:20.35#ibcon#enter sib2, iclass 11, count 0 2006.190.07:38:20.35#ibcon#flushed, iclass 11, count 0 2006.190.07:38:20.35#ibcon#about to write, iclass 11, count 0 2006.190.07:38:20.35#ibcon#wrote, iclass 11, count 0 2006.190.07:38:20.35#ibcon#about to read 3, iclass 11, count 0 2006.190.07:38:20.39#ibcon#read 3, iclass 11, count 0 2006.190.07:38:20.39#ibcon#about to read 4, iclass 11, count 0 2006.190.07:38:20.39#ibcon#read 4, iclass 11, count 0 2006.190.07:38:20.39#ibcon#about to read 5, iclass 11, count 0 2006.190.07:38:20.39#ibcon#read 5, iclass 11, count 0 2006.190.07:38:20.39#ibcon#about to read 6, iclass 11, count 0 2006.190.07:38:20.39#ibcon#read 6, iclass 11, count 0 2006.190.07:38:20.39#ibcon#end of sib2, iclass 11, count 0 2006.190.07:38:20.39#ibcon#*after write, iclass 11, count 0 2006.190.07:38:20.39#ibcon#*before return 0, iclass 11, count 0 2006.190.07:38:20.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:38:20.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:38:20.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:38:20.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:38:20.39$vc4f8/va=8,6 2006.190.07:38:20.39#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.07:38:20.39#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.07:38:20.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:20.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:38:20.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:38:20.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:38:20.45#ibcon#enter wrdev, iclass 13, count 2 2006.190.07:38:20.45#ibcon#first serial, iclass 13, count 2 2006.190.07:38:20.45#ibcon#enter sib2, iclass 13, count 2 2006.190.07:38:20.45#ibcon#flushed, iclass 13, count 2 2006.190.07:38:20.45#ibcon#about to write, iclass 13, count 2 2006.190.07:38:20.45#ibcon#wrote, iclass 13, count 2 2006.190.07:38:20.45#ibcon#about to read 3, iclass 13, count 2 2006.190.07:38:20.47#ibcon#read 3, iclass 13, count 2 2006.190.07:38:20.47#ibcon#about to read 4, iclass 13, count 2 2006.190.07:38:20.47#ibcon#read 4, iclass 13, count 2 2006.190.07:38:20.47#ibcon#about to read 5, iclass 13, count 2 2006.190.07:38:20.47#ibcon#read 5, iclass 13, count 2 2006.190.07:38:20.47#ibcon#about to read 6, iclass 13, count 2 2006.190.07:38:20.47#ibcon#read 6, iclass 13, count 2 2006.190.07:38:20.47#ibcon#end of sib2, iclass 13, count 2 2006.190.07:38:20.47#ibcon#*mode == 0, iclass 13, count 2 2006.190.07:38:20.47#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.07:38:20.47#ibcon#[25=AT08-06\r\n] 2006.190.07:38:20.47#ibcon#*before write, iclass 13, count 2 2006.190.07:38:20.47#ibcon#enter sib2, iclass 13, count 2 2006.190.07:38:20.47#ibcon#flushed, iclass 13, count 2 2006.190.07:38:20.47#ibcon#about to write, iclass 13, count 2 2006.190.07:38:20.47#ibcon#wrote, iclass 13, count 2 2006.190.07:38:20.47#ibcon#about to read 3, iclass 13, count 2 2006.190.07:38:20.50#ibcon#read 3, iclass 13, count 2 2006.190.07:38:20.50#ibcon#about to read 4, iclass 13, count 2 2006.190.07:38:20.50#ibcon#read 4, iclass 13, count 2 2006.190.07:38:20.50#ibcon#about to read 5, iclass 13, count 2 2006.190.07:38:20.50#ibcon#read 5, iclass 13, count 2 2006.190.07:38:20.50#ibcon#about to read 6, iclass 13, count 2 2006.190.07:38:20.50#ibcon#read 6, iclass 13, count 2 2006.190.07:38:20.50#ibcon#end of sib2, iclass 13, count 2 2006.190.07:38:20.50#ibcon#*after write, iclass 13, count 2 2006.190.07:38:20.50#ibcon#*before return 0, iclass 13, count 2 2006.190.07:38:20.50#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:38:20.50#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:38:20.50#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.07:38:20.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:20.50#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:38:20.62#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:38:20.62#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:38:20.62#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:38:20.62#ibcon#first serial, iclass 13, count 0 2006.190.07:38:20.62#ibcon#enter sib2, iclass 13, count 0 2006.190.07:38:20.62#ibcon#flushed, iclass 13, count 0 2006.190.07:38:20.62#ibcon#about to write, iclass 13, count 0 2006.190.07:38:20.62#ibcon#wrote, iclass 13, count 0 2006.190.07:38:20.62#ibcon#about to read 3, iclass 13, count 0 2006.190.07:38:20.64#ibcon#read 3, iclass 13, count 0 2006.190.07:38:20.64#ibcon#about to read 4, iclass 13, count 0 2006.190.07:38:20.64#ibcon#read 4, iclass 13, count 0 2006.190.07:38:20.64#ibcon#about to read 5, iclass 13, count 0 2006.190.07:38:20.64#ibcon#read 5, iclass 13, count 0 2006.190.07:38:20.64#ibcon#about to read 6, iclass 13, count 0 2006.190.07:38:20.64#ibcon#read 6, iclass 13, count 0 2006.190.07:38:20.64#ibcon#end of sib2, iclass 13, count 0 2006.190.07:38:20.64#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:38:20.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:38:20.64#ibcon#[25=USB\r\n] 2006.190.07:38:20.64#ibcon#*before write, iclass 13, count 0 2006.190.07:38:20.64#ibcon#enter sib2, iclass 13, count 0 2006.190.07:38:20.64#ibcon#flushed, iclass 13, count 0 2006.190.07:38:20.64#ibcon#about to write, iclass 13, count 0 2006.190.07:38:20.64#ibcon#wrote, iclass 13, count 0 2006.190.07:38:20.64#ibcon#about to read 3, iclass 13, count 0 2006.190.07:38:20.67#ibcon#read 3, iclass 13, count 0 2006.190.07:38:20.67#ibcon#about to read 4, iclass 13, count 0 2006.190.07:38:20.67#ibcon#read 4, iclass 13, count 0 2006.190.07:38:20.67#ibcon#about to read 5, iclass 13, count 0 2006.190.07:38:20.67#ibcon#read 5, iclass 13, count 0 2006.190.07:38:20.67#ibcon#about to read 6, iclass 13, count 0 2006.190.07:38:20.67#ibcon#read 6, iclass 13, count 0 2006.190.07:38:20.67#ibcon#end of sib2, iclass 13, count 0 2006.190.07:38:20.67#ibcon#*after write, iclass 13, count 0 2006.190.07:38:20.67#ibcon#*before return 0, iclass 13, count 0 2006.190.07:38:20.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:38:20.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:38:20.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:38:20.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:38:20.67$vc4f8/vblo=1,632.99 2006.190.07:38:20.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:38:20.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:38:20.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:20.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:38:20.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:38:20.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:38:20.67#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:38:20.67#ibcon#first serial, iclass 15, count 0 2006.190.07:38:20.67#ibcon#enter sib2, iclass 15, count 0 2006.190.07:38:20.67#ibcon#flushed, iclass 15, count 0 2006.190.07:38:20.67#ibcon#about to write, iclass 15, count 0 2006.190.07:38:20.67#ibcon#wrote, iclass 15, count 0 2006.190.07:38:20.67#ibcon#about to read 3, iclass 15, count 0 2006.190.07:38:20.69#ibcon#read 3, iclass 15, count 0 2006.190.07:38:20.69#ibcon#about to read 4, iclass 15, count 0 2006.190.07:38:20.69#ibcon#read 4, iclass 15, count 0 2006.190.07:38:20.69#ibcon#about to read 5, iclass 15, count 0 2006.190.07:38:20.69#ibcon#read 5, iclass 15, count 0 2006.190.07:38:20.69#ibcon#about to read 6, iclass 15, count 0 2006.190.07:38:20.69#ibcon#read 6, iclass 15, count 0 2006.190.07:38:20.69#ibcon#end of sib2, iclass 15, count 0 2006.190.07:38:20.69#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:38:20.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:38:20.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:38:20.69#ibcon#*before write, iclass 15, count 0 2006.190.07:38:20.69#ibcon#enter sib2, iclass 15, count 0 2006.190.07:38:20.69#ibcon#flushed, iclass 15, count 0 2006.190.07:38:20.69#ibcon#about to write, iclass 15, count 0 2006.190.07:38:20.69#ibcon#wrote, iclass 15, count 0 2006.190.07:38:20.69#ibcon#about to read 3, iclass 15, count 0 2006.190.07:38:20.73#ibcon#read 3, iclass 15, count 0 2006.190.07:38:20.73#ibcon#about to read 4, iclass 15, count 0 2006.190.07:38:20.73#ibcon#read 4, iclass 15, count 0 2006.190.07:38:20.73#ibcon#about to read 5, iclass 15, count 0 2006.190.07:38:20.73#ibcon#read 5, iclass 15, count 0 2006.190.07:38:20.73#ibcon#about to read 6, iclass 15, count 0 2006.190.07:38:20.73#ibcon#read 6, iclass 15, count 0 2006.190.07:38:20.73#ibcon#end of sib2, iclass 15, count 0 2006.190.07:38:20.73#ibcon#*after write, iclass 15, count 0 2006.190.07:38:20.73#ibcon#*before return 0, iclass 15, count 0 2006.190.07:38:20.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:38:20.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:38:20.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:38:20.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:38:20.73$vc4f8/vb=1,4 2006.190.07:38:20.73#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.07:38:20.73#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.07:38:20.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:20.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:38:20.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:38:20.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:38:20.73#ibcon#enter wrdev, iclass 17, count 2 2006.190.07:38:20.73#ibcon#first serial, iclass 17, count 2 2006.190.07:38:20.73#ibcon#enter sib2, iclass 17, count 2 2006.190.07:38:20.73#ibcon#flushed, iclass 17, count 2 2006.190.07:38:20.73#ibcon#about to write, iclass 17, count 2 2006.190.07:38:20.73#ibcon#wrote, iclass 17, count 2 2006.190.07:38:20.73#ibcon#about to read 3, iclass 17, count 2 2006.190.07:38:20.75#ibcon#read 3, iclass 17, count 2 2006.190.07:38:20.75#ibcon#about to read 4, iclass 17, count 2 2006.190.07:38:20.75#ibcon#read 4, iclass 17, count 2 2006.190.07:38:20.75#ibcon#about to read 5, iclass 17, count 2 2006.190.07:38:20.75#ibcon#read 5, iclass 17, count 2 2006.190.07:38:20.75#ibcon#about to read 6, iclass 17, count 2 2006.190.07:38:20.75#ibcon#read 6, iclass 17, count 2 2006.190.07:38:20.75#ibcon#end of sib2, iclass 17, count 2 2006.190.07:38:20.75#ibcon#*mode == 0, iclass 17, count 2 2006.190.07:38:20.75#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.07:38:20.75#ibcon#[27=AT01-04\r\n] 2006.190.07:38:20.75#ibcon#*before write, iclass 17, count 2 2006.190.07:38:20.75#ibcon#enter sib2, iclass 17, count 2 2006.190.07:38:20.75#ibcon#flushed, iclass 17, count 2 2006.190.07:38:20.75#ibcon#about to write, iclass 17, count 2 2006.190.07:38:20.75#ibcon#wrote, iclass 17, count 2 2006.190.07:38:20.75#ibcon#about to read 3, iclass 17, count 2 2006.190.07:38:20.78#ibcon#read 3, iclass 17, count 2 2006.190.07:38:20.78#ibcon#about to read 4, iclass 17, count 2 2006.190.07:38:20.78#ibcon#read 4, iclass 17, count 2 2006.190.07:38:20.78#ibcon#about to read 5, iclass 17, count 2 2006.190.07:38:20.78#ibcon#read 5, iclass 17, count 2 2006.190.07:38:20.78#ibcon#about to read 6, iclass 17, count 2 2006.190.07:38:20.78#ibcon#read 6, iclass 17, count 2 2006.190.07:38:20.78#ibcon#end of sib2, iclass 17, count 2 2006.190.07:38:20.78#ibcon#*after write, iclass 17, count 2 2006.190.07:38:20.78#ibcon#*before return 0, iclass 17, count 2 2006.190.07:38:20.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:38:20.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:38:20.78#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.07:38:20.78#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:20.78#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:38:20.90#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:38:20.90#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:38:20.90#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:38:20.90#ibcon#first serial, iclass 17, count 0 2006.190.07:38:20.90#ibcon#enter sib2, iclass 17, count 0 2006.190.07:38:20.90#ibcon#flushed, iclass 17, count 0 2006.190.07:38:20.90#ibcon#about to write, iclass 17, count 0 2006.190.07:38:20.90#ibcon#wrote, iclass 17, count 0 2006.190.07:38:20.90#ibcon#about to read 3, iclass 17, count 0 2006.190.07:38:20.92#ibcon#read 3, iclass 17, count 0 2006.190.07:38:20.92#ibcon#about to read 4, iclass 17, count 0 2006.190.07:38:20.92#ibcon#read 4, iclass 17, count 0 2006.190.07:38:20.92#ibcon#about to read 5, iclass 17, count 0 2006.190.07:38:20.92#ibcon#read 5, iclass 17, count 0 2006.190.07:38:20.92#ibcon#about to read 6, iclass 17, count 0 2006.190.07:38:20.92#ibcon#read 6, iclass 17, count 0 2006.190.07:38:20.92#ibcon#end of sib2, iclass 17, count 0 2006.190.07:38:20.92#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:38:20.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:38:20.92#ibcon#[27=USB\r\n] 2006.190.07:38:20.92#ibcon#*before write, iclass 17, count 0 2006.190.07:38:20.92#ibcon#enter sib2, iclass 17, count 0 2006.190.07:38:20.92#ibcon#flushed, iclass 17, count 0 2006.190.07:38:20.92#ibcon#about to write, iclass 17, count 0 2006.190.07:38:20.92#ibcon#wrote, iclass 17, count 0 2006.190.07:38:20.92#ibcon#about to read 3, iclass 17, count 0 2006.190.07:38:20.95#ibcon#read 3, iclass 17, count 0 2006.190.07:38:20.95#ibcon#about to read 4, iclass 17, count 0 2006.190.07:38:20.95#ibcon#read 4, iclass 17, count 0 2006.190.07:38:20.95#ibcon#about to read 5, iclass 17, count 0 2006.190.07:38:20.95#ibcon#read 5, iclass 17, count 0 2006.190.07:38:20.95#ibcon#about to read 6, iclass 17, count 0 2006.190.07:38:20.95#ibcon#read 6, iclass 17, count 0 2006.190.07:38:20.95#ibcon#end of sib2, iclass 17, count 0 2006.190.07:38:20.95#ibcon#*after write, iclass 17, count 0 2006.190.07:38:20.95#ibcon#*before return 0, iclass 17, count 0 2006.190.07:38:20.95#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:38:20.95#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:38:20.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:38:20.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:38:20.95$vc4f8/vblo=2,640.99 2006.190.07:38:20.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:38:20.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:38:20.95#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:20.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:20.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:20.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:20.95#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:38:20.95#ibcon#first serial, iclass 19, count 0 2006.190.07:38:20.95#ibcon#enter sib2, iclass 19, count 0 2006.190.07:38:20.95#ibcon#flushed, iclass 19, count 0 2006.190.07:38:20.95#ibcon#about to write, iclass 19, count 0 2006.190.07:38:20.95#ibcon#wrote, iclass 19, count 0 2006.190.07:38:20.95#ibcon#about to read 3, iclass 19, count 0 2006.190.07:38:20.97#ibcon#read 3, iclass 19, count 0 2006.190.07:38:20.97#ibcon#about to read 4, iclass 19, count 0 2006.190.07:38:20.97#ibcon#read 4, iclass 19, count 0 2006.190.07:38:20.97#ibcon#about to read 5, iclass 19, count 0 2006.190.07:38:20.97#ibcon#read 5, iclass 19, count 0 2006.190.07:38:20.97#ibcon#about to read 6, iclass 19, count 0 2006.190.07:38:20.97#ibcon#read 6, iclass 19, count 0 2006.190.07:38:20.97#ibcon#end of sib2, iclass 19, count 0 2006.190.07:38:20.97#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:38:20.97#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:38:20.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:38:20.97#ibcon#*before write, iclass 19, count 0 2006.190.07:38:20.97#ibcon#enter sib2, iclass 19, count 0 2006.190.07:38:20.97#ibcon#flushed, iclass 19, count 0 2006.190.07:38:20.97#ibcon#about to write, iclass 19, count 0 2006.190.07:38:20.97#ibcon#wrote, iclass 19, count 0 2006.190.07:38:20.97#ibcon#about to read 3, iclass 19, count 0 2006.190.07:38:21.01#ibcon#read 3, iclass 19, count 0 2006.190.07:38:21.01#ibcon#about to read 4, iclass 19, count 0 2006.190.07:38:21.01#ibcon#read 4, iclass 19, count 0 2006.190.07:38:21.01#ibcon#about to read 5, iclass 19, count 0 2006.190.07:38:21.01#ibcon#read 5, iclass 19, count 0 2006.190.07:38:21.01#ibcon#about to read 6, iclass 19, count 0 2006.190.07:38:21.01#ibcon#read 6, iclass 19, count 0 2006.190.07:38:21.01#ibcon#end of sib2, iclass 19, count 0 2006.190.07:38:21.01#ibcon#*after write, iclass 19, count 0 2006.190.07:38:21.01#ibcon#*before return 0, iclass 19, count 0 2006.190.07:38:21.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:21.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:38:21.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:38:21.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:38:21.01$vc4f8/vb=2,4 2006.190.07:38:21.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.07:38:21.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.07:38:21.01#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:21.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:21.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:21.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:21.07#ibcon#enter wrdev, iclass 21, count 2 2006.190.07:38:21.07#ibcon#first serial, iclass 21, count 2 2006.190.07:38:21.07#ibcon#enter sib2, iclass 21, count 2 2006.190.07:38:21.07#ibcon#flushed, iclass 21, count 2 2006.190.07:38:21.07#ibcon#about to write, iclass 21, count 2 2006.190.07:38:21.07#ibcon#wrote, iclass 21, count 2 2006.190.07:38:21.07#ibcon#about to read 3, iclass 21, count 2 2006.190.07:38:21.09#ibcon#read 3, iclass 21, count 2 2006.190.07:38:21.09#ibcon#about to read 4, iclass 21, count 2 2006.190.07:38:21.09#ibcon#read 4, iclass 21, count 2 2006.190.07:38:21.09#ibcon#about to read 5, iclass 21, count 2 2006.190.07:38:21.09#ibcon#read 5, iclass 21, count 2 2006.190.07:38:21.09#ibcon#about to read 6, iclass 21, count 2 2006.190.07:38:21.09#ibcon#read 6, iclass 21, count 2 2006.190.07:38:21.09#ibcon#end of sib2, iclass 21, count 2 2006.190.07:38:21.09#ibcon#*mode == 0, iclass 21, count 2 2006.190.07:38:21.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.07:38:21.09#ibcon#[27=AT02-04\r\n] 2006.190.07:38:21.09#ibcon#*before write, iclass 21, count 2 2006.190.07:38:21.09#ibcon#enter sib2, iclass 21, count 2 2006.190.07:38:21.09#ibcon#flushed, iclass 21, count 2 2006.190.07:38:21.09#ibcon#about to write, iclass 21, count 2 2006.190.07:38:21.09#ibcon#wrote, iclass 21, count 2 2006.190.07:38:21.09#ibcon#about to read 3, iclass 21, count 2 2006.190.07:38:21.12#ibcon#read 3, iclass 21, count 2 2006.190.07:38:21.12#ibcon#about to read 4, iclass 21, count 2 2006.190.07:38:21.12#ibcon#read 4, iclass 21, count 2 2006.190.07:38:21.12#ibcon#about to read 5, iclass 21, count 2 2006.190.07:38:21.12#ibcon#read 5, iclass 21, count 2 2006.190.07:38:21.12#ibcon#about to read 6, iclass 21, count 2 2006.190.07:38:21.12#ibcon#read 6, iclass 21, count 2 2006.190.07:38:21.12#ibcon#end of sib2, iclass 21, count 2 2006.190.07:38:21.12#ibcon#*after write, iclass 21, count 2 2006.190.07:38:21.12#ibcon#*before return 0, iclass 21, count 2 2006.190.07:38:21.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:21.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:38:21.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.07:38:21.12#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:21.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:21.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:21.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:21.24#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:38:21.24#ibcon#first serial, iclass 21, count 0 2006.190.07:38:21.24#ibcon#enter sib2, iclass 21, count 0 2006.190.07:38:21.24#ibcon#flushed, iclass 21, count 0 2006.190.07:38:21.24#ibcon#about to write, iclass 21, count 0 2006.190.07:38:21.24#ibcon#wrote, iclass 21, count 0 2006.190.07:38:21.24#ibcon#about to read 3, iclass 21, count 0 2006.190.07:38:21.26#ibcon#read 3, iclass 21, count 0 2006.190.07:38:21.26#ibcon#about to read 4, iclass 21, count 0 2006.190.07:38:21.26#ibcon#read 4, iclass 21, count 0 2006.190.07:38:21.26#ibcon#about to read 5, iclass 21, count 0 2006.190.07:38:21.26#ibcon#read 5, iclass 21, count 0 2006.190.07:38:21.26#ibcon#about to read 6, iclass 21, count 0 2006.190.07:38:21.26#ibcon#read 6, iclass 21, count 0 2006.190.07:38:21.26#ibcon#end of sib2, iclass 21, count 0 2006.190.07:38:21.26#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:38:21.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:38:21.26#ibcon#[27=USB\r\n] 2006.190.07:38:21.26#ibcon#*before write, iclass 21, count 0 2006.190.07:38:21.26#ibcon#enter sib2, iclass 21, count 0 2006.190.07:38:21.26#ibcon#flushed, iclass 21, count 0 2006.190.07:38:21.26#ibcon#about to write, iclass 21, count 0 2006.190.07:38:21.26#ibcon#wrote, iclass 21, count 0 2006.190.07:38:21.26#ibcon#about to read 3, iclass 21, count 0 2006.190.07:38:21.29#ibcon#read 3, iclass 21, count 0 2006.190.07:38:21.29#ibcon#about to read 4, iclass 21, count 0 2006.190.07:38:21.29#ibcon#read 4, iclass 21, count 0 2006.190.07:38:21.29#ibcon#about to read 5, iclass 21, count 0 2006.190.07:38:21.29#ibcon#read 5, iclass 21, count 0 2006.190.07:38:21.29#ibcon#about to read 6, iclass 21, count 0 2006.190.07:38:21.29#ibcon#read 6, iclass 21, count 0 2006.190.07:38:21.29#ibcon#end of sib2, iclass 21, count 0 2006.190.07:38:21.29#ibcon#*after write, iclass 21, count 0 2006.190.07:38:21.29#ibcon#*before return 0, iclass 21, count 0 2006.190.07:38:21.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:21.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:38:21.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:38:21.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:38:21.29$vc4f8/vblo=3,656.99 2006.190.07:38:21.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.07:38:21.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.07:38:21.29#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:21.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:21.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:21.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:21.29#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:38:21.29#ibcon#first serial, iclass 23, count 0 2006.190.07:38:21.29#ibcon#enter sib2, iclass 23, count 0 2006.190.07:38:21.29#ibcon#flushed, iclass 23, count 0 2006.190.07:38:21.29#ibcon#about to write, iclass 23, count 0 2006.190.07:38:21.29#ibcon#wrote, iclass 23, count 0 2006.190.07:38:21.29#ibcon#about to read 3, iclass 23, count 0 2006.190.07:38:21.31#ibcon#read 3, iclass 23, count 0 2006.190.07:38:21.31#ibcon#about to read 4, iclass 23, count 0 2006.190.07:38:21.31#ibcon#read 4, iclass 23, count 0 2006.190.07:38:21.31#ibcon#about to read 5, iclass 23, count 0 2006.190.07:38:21.31#ibcon#read 5, iclass 23, count 0 2006.190.07:38:21.31#ibcon#about to read 6, iclass 23, count 0 2006.190.07:38:21.31#ibcon#read 6, iclass 23, count 0 2006.190.07:38:21.31#ibcon#end of sib2, iclass 23, count 0 2006.190.07:38:21.31#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:38:21.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:38:21.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:38:21.31#ibcon#*before write, iclass 23, count 0 2006.190.07:38:21.31#ibcon#enter sib2, iclass 23, count 0 2006.190.07:38:21.31#ibcon#flushed, iclass 23, count 0 2006.190.07:38:21.31#ibcon#about to write, iclass 23, count 0 2006.190.07:38:21.31#ibcon#wrote, iclass 23, count 0 2006.190.07:38:21.31#ibcon#about to read 3, iclass 23, count 0 2006.190.07:38:21.35#ibcon#read 3, iclass 23, count 0 2006.190.07:38:21.35#ibcon#about to read 4, iclass 23, count 0 2006.190.07:38:21.35#ibcon#read 4, iclass 23, count 0 2006.190.07:38:21.35#ibcon#about to read 5, iclass 23, count 0 2006.190.07:38:21.35#ibcon#read 5, iclass 23, count 0 2006.190.07:38:21.35#ibcon#about to read 6, iclass 23, count 0 2006.190.07:38:21.35#ibcon#read 6, iclass 23, count 0 2006.190.07:38:21.35#ibcon#end of sib2, iclass 23, count 0 2006.190.07:38:21.35#ibcon#*after write, iclass 23, count 0 2006.190.07:38:21.35#ibcon#*before return 0, iclass 23, count 0 2006.190.07:38:21.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:21.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:38:21.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:38:21.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:38:21.35$vc4f8/vb=3,4 2006.190.07:38:21.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.07:38:21.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.07:38:21.35#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:21.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:21.41#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:21.41#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:21.41#ibcon#enter wrdev, iclass 25, count 2 2006.190.07:38:21.41#ibcon#first serial, iclass 25, count 2 2006.190.07:38:21.41#ibcon#enter sib2, iclass 25, count 2 2006.190.07:38:21.41#ibcon#flushed, iclass 25, count 2 2006.190.07:38:21.41#ibcon#about to write, iclass 25, count 2 2006.190.07:38:21.41#ibcon#wrote, iclass 25, count 2 2006.190.07:38:21.41#ibcon#about to read 3, iclass 25, count 2 2006.190.07:38:21.43#ibcon#read 3, iclass 25, count 2 2006.190.07:38:21.43#ibcon#about to read 4, iclass 25, count 2 2006.190.07:38:21.43#ibcon#read 4, iclass 25, count 2 2006.190.07:38:21.43#ibcon#about to read 5, iclass 25, count 2 2006.190.07:38:21.43#ibcon#read 5, iclass 25, count 2 2006.190.07:38:21.43#ibcon#about to read 6, iclass 25, count 2 2006.190.07:38:21.43#ibcon#read 6, iclass 25, count 2 2006.190.07:38:21.43#ibcon#end of sib2, iclass 25, count 2 2006.190.07:38:21.43#ibcon#*mode == 0, iclass 25, count 2 2006.190.07:38:21.43#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.07:38:21.43#ibcon#[27=AT03-04\r\n] 2006.190.07:38:21.43#ibcon#*before write, iclass 25, count 2 2006.190.07:38:21.43#ibcon#enter sib2, iclass 25, count 2 2006.190.07:38:21.43#ibcon#flushed, iclass 25, count 2 2006.190.07:38:21.43#ibcon#about to write, iclass 25, count 2 2006.190.07:38:21.43#ibcon#wrote, iclass 25, count 2 2006.190.07:38:21.43#ibcon#about to read 3, iclass 25, count 2 2006.190.07:38:21.46#ibcon#read 3, iclass 25, count 2 2006.190.07:38:21.46#ibcon#about to read 4, iclass 25, count 2 2006.190.07:38:21.46#ibcon#read 4, iclass 25, count 2 2006.190.07:38:21.46#ibcon#about to read 5, iclass 25, count 2 2006.190.07:38:21.46#ibcon#read 5, iclass 25, count 2 2006.190.07:38:21.46#ibcon#about to read 6, iclass 25, count 2 2006.190.07:38:21.46#ibcon#read 6, iclass 25, count 2 2006.190.07:38:21.46#ibcon#end of sib2, iclass 25, count 2 2006.190.07:38:21.46#ibcon#*after write, iclass 25, count 2 2006.190.07:38:21.46#ibcon#*before return 0, iclass 25, count 2 2006.190.07:38:21.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:21.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:38:21.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.07:38:21.46#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:21.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:21.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:21.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:21.58#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:38:21.58#ibcon#first serial, iclass 25, count 0 2006.190.07:38:21.58#ibcon#enter sib2, iclass 25, count 0 2006.190.07:38:21.58#ibcon#flushed, iclass 25, count 0 2006.190.07:38:21.58#ibcon#about to write, iclass 25, count 0 2006.190.07:38:21.58#ibcon#wrote, iclass 25, count 0 2006.190.07:38:21.58#ibcon#about to read 3, iclass 25, count 0 2006.190.07:38:21.60#ibcon#read 3, iclass 25, count 0 2006.190.07:38:21.60#ibcon#about to read 4, iclass 25, count 0 2006.190.07:38:21.60#ibcon#read 4, iclass 25, count 0 2006.190.07:38:21.60#ibcon#about to read 5, iclass 25, count 0 2006.190.07:38:21.60#ibcon#read 5, iclass 25, count 0 2006.190.07:38:21.60#ibcon#about to read 6, iclass 25, count 0 2006.190.07:38:21.60#ibcon#read 6, iclass 25, count 0 2006.190.07:38:21.60#ibcon#end of sib2, iclass 25, count 0 2006.190.07:38:21.60#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:38:21.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:38:21.60#ibcon#[27=USB\r\n] 2006.190.07:38:21.60#ibcon#*before write, iclass 25, count 0 2006.190.07:38:21.60#ibcon#enter sib2, iclass 25, count 0 2006.190.07:38:21.60#ibcon#flushed, iclass 25, count 0 2006.190.07:38:21.60#ibcon#about to write, iclass 25, count 0 2006.190.07:38:21.60#ibcon#wrote, iclass 25, count 0 2006.190.07:38:21.60#ibcon#about to read 3, iclass 25, count 0 2006.190.07:38:21.63#ibcon#read 3, iclass 25, count 0 2006.190.07:38:21.63#ibcon#about to read 4, iclass 25, count 0 2006.190.07:38:21.63#ibcon#read 4, iclass 25, count 0 2006.190.07:38:21.63#ibcon#about to read 5, iclass 25, count 0 2006.190.07:38:21.63#ibcon#read 5, iclass 25, count 0 2006.190.07:38:21.63#ibcon#about to read 6, iclass 25, count 0 2006.190.07:38:21.63#ibcon#read 6, iclass 25, count 0 2006.190.07:38:21.63#ibcon#end of sib2, iclass 25, count 0 2006.190.07:38:21.63#ibcon#*after write, iclass 25, count 0 2006.190.07:38:21.63#ibcon#*before return 0, iclass 25, count 0 2006.190.07:38:21.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:21.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:38:21.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:38:21.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:38:21.63$vc4f8/vblo=4,712.99 2006.190.07:38:21.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.07:38:21.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.07:38:21.63#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:21.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:21.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:21.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:21.63#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:38:21.63#ibcon#first serial, iclass 27, count 0 2006.190.07:38:21.63#ibcon#enter sib2, iclass 27, count 0 2006.190.07:38:21.63#ibcon#flushed, iclass 27, count 0 2006.190.07:38:21.63#ibcon#about to write, iclass 27, count 0 2006.190.07:38:21.63#ibcon#wrote, iclass 27, count 0 2006.190.07:38:21.63#ibcon#about to read 3, iclass 27, count 0 2006.190.07:38:21.65#ibcon#read 3, iclass 27, count 0 2006.190.07:38:21.65#ibcon#about to read 4, iclass 27, count 0 2006.190.07:38:21.65#ibcon#read 4, iclass 27, count 0 2006.190.07:38:21.65#ibcon#about to read 5, iclass 27, count 0 2006.190.07:38:21.65#ibcon#read 5, iclass 27, count 0 2006.190.07:38:21.65#ibcon#about to read 6, iclass 27, count 0 2006.190.07:38:21.65#ibcon#read 6, iclass 27, count 0 2006.190.07:38:21.65#ibcon#end of sib2, iclass 27, count 0 2006.190.07:38:21.65#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:38:21.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:38:21.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:38:21.65#ibcon#*before write, iclass 27, count 0 2006.190.07:38:21.65#ibcon#enter sib2, iclass 27, count 0 2006.190.07:38:21.65#ibcon#flushed, iclass 27, count 0 2006.190.07:38:21.65#ibcon#about to write, iclass 27, count 0 2006.190.07:38:21.65#ibcon#wrote, iclass 27, count 0 2006.190.07:38:21.65#ibcon#about to read 3, iclass 27, count 0 2006.190.07:38:21.69#ibcon#read 3, iclass 27, count 0 2006.190.07:38:21.69#ibcon#about to read 4, iclass 27, count 0 2006.190.07:38:21.69#ibcon#read 4, iclass 27, count 0 2006.190.07:38:21.69#ibcon#about to read 5, iclass 27, count 0 2006.190.07:38:21.69#ibcon#read 5, iclass 27, count 0 2006.190.07:38:21.69#ibcon#about to read 6, iclass 27, count 0 2006.190.07:38:21.69#ibcon#read 6, iclass 27, count 0 2006.190.07:38:21.69#ibcon#end of sib2, iclass 27, count 0 2006.190.07:38:21.69#ibcon#*after write, iclass 27, count 0 2006.190.07:38:21.69#ibcon#*before return 0, iclass 27, count 0 2006.190.07:38:21.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:21.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:38:21.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:38:21.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:38:21.69$vc4f8/vb=4,4 2006.190.07:38:21.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.07:38:21.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.07:38:21.69#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:21.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:21.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:21.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:21.75#ibcon#enter wrdev, iclass 29, count 2 2006.190.07:38:21.75#ibcon#first serial, iclass 29, count 2 2006.190.07:38:21.75#ibcon#enter sib2, iclass 29, count 2 2006.190.07:38:21.75#ibcon#flushed, iclass 29, count 2 2006.190.07:38:21.75#ibcon#about to write, iclass 29, count 2 2006.190.07:38:21.75#ibcon#wrote, iclass 29, count 2 2006.190.07:38:21.75#ibcon#about to read 3, iclass 29, count 2 2006.190.07:38:21.77#ibcon#read 3, iclass 29, count 2 2006.190.07:38:21.77#ibcon#about to read 4, iclass 29, count 2 2006.190.07:38:21.77#ibcon#read 4, iclass 29, count 2 2006.190.07:38:21.77#ibcon#about to read 5, iclass 29, count 2 2006.190.07:38:21.77#ibcon#read 5, iclass 29, count 2 2006.190.07:38:21.77#ibcon#about to read 6, iclass 29, count 2 2006.190.07:38:21.77#ibcon#read 6, iclass 29, count 2 2006.190.07:38:21.77#ibcon#end of sib2, iclass 29, count 2 2006.190.07:38:21.77#ibcon#*mode == 0, iclass 29, count 2 2006.190.07:38:21.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.07:38:21.77#ibcon#[27=AT04-04\r\n] 2006.190.07:38:21.77#ibcon#*before write, iclass 29, count 2 2006.190.07:38:21.77#ibcon#enter sib2, iclass 29, count 2 2006.190.07:38:21.77#ibcon#flushed, iclass 29, count 2 2006.190.07:38:21.77#ibcon#about to write, iclass 29, count 2 2006.190.07:38:21.77#ibcon#wrote, iclass 29, count 2 2006.190.07:38:21.77#ibcon#about to read 3, iclass 29, count 2 2006.190.07:38:21.80#ibcon#read 3, iclass 29, count 2 2006.190.07:38:21.80#ibcon#about to read 4, iclass 29, count 2 2006.190.07:38:21.80#ibcon#read 4, iclass 29, count 2 2006.190.07:38:21.80#ibcon#about to read 5, iclass 29, count 2 2006.190.07:38:21.80#ibcon#read 5, iclass 29, count 2 2006.190.07:38:21.80#ibcon#about to read 6, iclass 29, count 2 2006.190.07:38:21.80#ibcon#read 6, iclass 29, count 2 2006.190.07:38:21.80#ibcon#end of sib2, iclass 29, count 2 2006.190.07:38:21.80#ibcon#*after write, iclass 29, count 2 2006.190.07:38:21.80#ibcon#*before return 0, iclass 29, count 2 2006.190.07:38:21.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:21.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:38:21.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.07:38:21.80#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:21.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:21.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:21.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:21.92#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:38:21.92#ibcon#first serial, iclass 29, count 0 2006.190.07:38:21.92#ibcon#enter sib2, iclass 29, count 0 2006.190.07:38:21.92#ibcon#flushed, iclass 29, count 0 2006.190.07:38:21.92#ibcon#about to write, iclass 29, count 0 2006.190.07:38:21.92#ibcon#wrote, iclass 29, count 0 2006.190.07:38:21.92#ibcon#about to read 3, iclass 29, count 0 2006.190.07:38:21.94#ibcon#read 3, iclass 29, count 0 2006.190.07:38:21.94#ibcon#about to read 4, iclass 29, count 0 2006.190.07:38:21.94#ibcon#read 4, iclass 29, count 0 2006.190.07:38:21.94#ibcon#about to read 5, iclass 29, count 0 2006.190.07:38:21.94#ibcon#read 5, iclass 29, count 0 2006.190.07:38:21.94#ibcon#about to read 6, iclass 29, count 0 2006.190.07:38:21.94#ibcon#read 6, iclass 29, count 0 2006.190.07:38:21.94#ibcon#end of sib2, iclass 29, count 0 2006.190.07:38:21.94#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:38:21.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:38:21.94#ibcon#[27=USB\r\n] 2006.190.07:38:21.94#ibcon#*before write, iclass 29, count 0 2006.190.07:38:21.94#ibcon#enter sib2, iclass 29, count 0 2006.190.07:38:21.94#ibcon#flushed, iclass 29, count 0 2006.190.07:38:21.94#ibcon#about to write, iclass 29, count 0 2006.190.07:38:21.94#ibcon#wrote, iclass 29, count 0 2006.190.07:38:21.94#ibcon#about to read 3, iclass 29, count 0 2006.190.07:38:21.97#ibcon#read 3, iclass 29, count 0 2006.190.07:38:21.97#ibcon#about to read 4, iclass 29, count 0 2006.190.07:38:21.97#ibcon#read 4, iclass 29, count 0 2006.190.07:38:21.97#ibcon#about to read 5, iclass 29, count 0 2006.190.07:38:21.97#ibcon#read 5, iclass 29, count 0 2006.190.07:38:21.97#ibcon#about to read 6, iclass 29, count 0 2006.190.07:38:21.97#ibcon#read 6, iclass 29, count 0 2006.190.07:38:21.97#ibcon#end of sib2, iclass 29, count 0 2006.190.07:38:21.97#ibcon#*after write, iclass 29, count 0 2006.190.07:38:21.97#ibcon#*before return 0, iclass 29, count 0 2006.190.07:38:21.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:21.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:38:21.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:38:21.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:38:21.97$vc4f8/vblo=5,744.99 2006.190.07:38:21.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.07:38:21.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.07:38:21.97#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:21.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:21.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:21.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:21.97#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:38:21.97#ibcon#first serial, iclass 31, count 0 2006.190.07:38:21.97#ibcon#enter sib2, iclass 31, count 0 2006.190.07:38:21.97#ibcon#flushed, iclass 31, count 0 2006.190.07:38:21.97#ibcon#about to write, iclass 31, count 0 2006.190.07:38:21.97#ibcon#wrote, iclass 31, count 0 2006.190.07:38:21.97#ibcon#about to read 3, iclass 31, count 0 2006.190.07:38:21.99#ibcon#read 3, iclass 31, count 0 2006.190.07:38:21.99#ibcon#about to read 4, iclass 31, count 0 2006.190.07:38:21.99#ibcon#read 4, iclass 31, count 0 2006.190.07:38:21.99#ibcon#about to read 5, iclass 31, count 0 2006.190.07:38:21.99#ibcon#read 5, iclass 31, count 0 2006.190.07:38:21.99#ibcon#about to read 6, iclass 31, count 0 2006.190.07:38:21.99#ibcon#read 6, iclass 31, count 0 2006.190.07:38:21.99#ibcon#end of sib2, iclass 31, count 0 2006.190.07:38:21.99#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:38:21.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:38:21.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:38:21.99#ibcon#*before write, iclass 31, count 0 2006.190.07:38:21.99#ibcon#enter sib2, iclass 31, count 0 2006.190.07:38:21.99#ibcon#flushed, iclass 31, count 0 2006.190.07:38:21.99#ibcon#about to write, iclass 31, count 0 2006.190.07:38:21.99#ibcon#wrote, iclass 31, count 0 2006.190.07:38:21.99#ibcon#about to read 3, iclass 31, count 0 2006.190.07:38:22.03#ibcon#read 3, iclass 31, count 0 2006.190.07:38:22.03#ibcon#about to read 4, iclass 31, count 0 2006.190.07:38:22.03#ibcon#read 4, iclass 31, count 0 2006.190.07:38:22.03#ibcon#about to read 5, iclass 31, count 0 2006.190.07:38:22.03#ibcon#read 5, iclass 31, count 0 2006.190.07:38:22.03#ibcon#about to read 6, iclass 31, count 0 2006.190.07:38:22.03#ibcon#read 6, iclass 31, count 0 2006.190.07:38:22.03#ibcon#end of sib2, iclass 31, count 0 2006.190.07:38:22.03#ibcon#*after write, iclass 31, count 0 2006.190.07:38:22.03#ibcon#*before return 0, iclass 31, count 0 2006.190.07:38:22.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:22.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:38:22.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:38:22.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:38:22.03$vc4f8/vb=5,4 2006.190.07:38:22.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.190.07:38:22.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.190.07:38:22.03#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:22.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:22.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:22.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:22.09#ibcon#enter wrdev, iclass 33, count 2 2006.190.07:38:22.09#ibcon#first serial, iclass 33, count 2 2006.190.07:38:22.09#ibcon#enter sib2, iclass 33, count 2 2006.190.07:38:22.09#ibcon#flushed, iclass 33, count 2 2006.190.07:38:22.09#ibcon#about to write, iclass 33, count 2 2006.190.07:38:22.09#ibcon#wrote, iclass 33, count 2 2006.190.07:38:22.09#ibcon#about to read 3, iclass 33, count 2 2006.190.07:38:22.11#ibcon#read 3, iclass 33, count 2 2006.190.07:38:22.11#ibcon#about to read 4, iclass 33, count 2 2006.190.07:38:22.11#ibcon#read 4, iclass 33, count 2 2006.190.07:38:22.11#ibcon#about to read 5, iclass 33, count 2 2006.190.07:38:22.11#ibcon#read 5, iclass 33, count 2 2006.190.07:38:22.11#ibcon#about to read 6, iclass 33, count 2 2006.190.07:38:22.11#ibcon#read 6, iclass 33, count 2 2006.190.07:38:22.11#ibcon#end of sib2, iclass 33, count 2 2006.190.07:38:22.11#ibcon#*mode == 0, iclass 33, count 2 2006.190.07:38:22.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.190.07:38:22.11#ibcon#[27=AT05-04\r\n] 2006.190.07:38:22.11#ibcon#*before write, iclass 33, count 2 2006.190.07:38:22.11#ibcon#enter sib2, iclass 33, count 2 2006.190.07:38:22.11#ibcon#flushed, iclass 33, count 2 2006.190.07:38:22.11#ibcon#about to write, iclass 33, count 2 2006.190.07:38:22.11#ibcon#wrote, iclass 33, count 2 2006.190.07:38:22.11#ibcon#about to read 3, iclass 33, count 2 2006.190.07:38:22.14#ibcon#read 3, iclass 33, count 2 2006.190.07:38:22.14#ibcon#about to read 4, iclass 33, count 2 2006.190.07:38:22.14#ibcon#read 4, iclass 33, count 2 2006.190.07:38:22.14#ibcon#about to read 5, iclass 33, count 2 2006.190.07:38:22.14#ibcon#read 5, iclass 33, count 2 2006.190.07:38:22.14#ibcon#about to read 6, iclass 33, count 2 2006.190.07:38:22.14#ibcon#read 6, iclass 33, count 2 2006.190.07:38:22.14#ibcon#end of sib2, iclass 33, count 2 2006.190.07:38:22.14#ibcon#*after write, iclass 33, count 2 2006.190.07:38:22.14#ibcon#*before return 0, iclass 33, count 2 2006.190.07:38:22.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:22.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:38:22.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.190.07:38:22.14#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:22.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:22.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:22.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:22.26#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:38:22.26#ibcon#first serial, iclass 33, count 0 2006.190.07:38:22.26#ibcon#enter sib2, iclass 33, count 0 2006.190.07:38:22.26#ibcon#flushed, iclass 33, count 0 2006.190.07:38:22.26#ibcon#about to write, iclass 33, count 0 2006.190.07:38:22.26#ibcon#wrote, iclass 33, count 0 2006.190.07:38:22.26#ibcon#about to read 3, iclass 33, count 0 2006.190.07:38:22.28#ibcon#read 3, iclass 33, count 0 2006.190.07:38:22.28#ibcon#about to read 4, iclass 33, count 0 2006.190.07:38:22.28#ibcon#read 4, iclass 33, count 0 2006.190.07:38:22.28#ibcon#about to read 5, iclass 33, count 0 2006.190.07:38:22.28#ibcon#read 5, iclass 33, count 0 2006.190.07:38:22.28#ibcon#about to read 6, iclass 33, count 0 2006.190.07:38:22.28#ibcon#read 6, iclass 33, count 0 2006.190.07:38:22.28#ibcon#end of sib2, iclass 33, count 0 2006.190.07:38:22.28#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:38:22.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:38:22.28#ibcon#[27=USB\r\n] 2006.190.07:38:22.28#ibcon#*before write, iclass 33, count 0 2006.190.07:38:22.28#ibcon#enter sib2, iclass 33, count 0 2006.190.07:38:22.28#ibcon#flushed, iclass 33, count 0 2006.190.07:38:22.28#ibcon#about to write, iclass 33, count 0 2006.190.07:38:22.28#ibcon#wrote, iclass 33, count 0 2006.190.07:38:22.28#ibcon#about to read 3, iclass 33, count 0 2006.190.07:38:22.31#ibcon#read 3, iclass 33, count 0 2006.190.07:38:22.31#ibcon#about to read 4, iclass 33, count 0 2006.190.07:38:22.31#ibcon#read 4, iclass 33, count 0 2006.190.07:38:22.31#ibcon#about to read 5, iclass 33, count 0 2006.190.07:38:22.31#ibcon#read 5, iclass 33, count 0 2006.190.07:38:22.31#ibcon#about to read 6, iclass 33, count 0 2006.190.07:38:22.31#ibcon#read 6, iclass 33, count 0 2006.190.07:38:22.31#ibcon#end of sib2, iclass 33, count 0 2006.190.07:38:22.31#ibcon#*after write, iclass 33, count 0 2006.190.07:38:22.31#ibcon#*before return 0, iclass 33, count 0 2006.190.07:38:22.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:22.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:38:22.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:38:22.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:38:22.31$vc4f8/vblo=6,752.99 2006.190.07:38:22.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.07:38:22.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.07:38:22.31#ibcon#ireg 17 cls_cnt 0 2006.190.07:38:22.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:22.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:22.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:22.31#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:38:22.31#ibcon#first serial, iclass 35, count 0 2006.190.07:38:22.31#ibcon#enter sib2, iclass 35, count 0 2006.190.07:38:22.31#ibcon#flushed, iclass 35, count 0 2006.190.07:38:22.31#ibcon#about to write, iclass 35, count 0 2006.190.07:38:22.31#ibcon#wrote, iclass 35, count 0 2006.190.07:38:22.31#ibcon#about to read 3, iclass 35, count 0 2006.190.07:38:22.33#ibcon#read 3, iclass 35, count 0 2006.190.07:38:22.33#ibcon#about to read 4, iclass 35, count 0 2006.190.07:38:22.33#ibcon#read 4, iclass 35, count 0 2006.190.07:38:22.33#ibcon#about to read 5, iclass 35, count 0 2006.190.07:38:22.33#ibcon#read 5, iclass 35, count 0 2006.190.07:38:22.33#ibcon#about to read 6, iclass 35, count 0 2006.190.07:38:22.33#ibcon#read 6, iclass 35, count 0 2006.190.07:38:22.33#ibcon#end of sib2, iclass 35, count 0 2006.190.07:38:22.33#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:38:22.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:38:22.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:38:22.33#ibcon#*before write, iclass 35, count 0 2006.190.07:38:22.33#ibcon#enter sib2, iclass 35, count 0 2006.190.07:38:22.33#ibcon#flushed, iclass 35, count 0 2006.190.07:38:22.33#ibcon#about to write, iclass 35, count 0 2006.190.07:38:22.33#ibcon#wrote, iclass 35, count 0 2006.190.07:38:22.33#ibcon#about to read 3, iclass 35, count 0 2006.190.07:38:22.37#ibcon#read 3, iclass 35, count 0 2006.190.07:38:22.37#ibcon#about to read 4, iclass 35, count 0 2006.190.07:38:22.37#ibcon#read 4, iclass 35, count 0 2006.190.07:38:22.37#ibcon#about to read 5, iclass 35, count 0 2006.190.07:38:22.37#ibcon#read 5, iclass 35, count 0 2006.190.07:38:22.37#ibcon#about to read 6, iclass 35, count 0 2006.190.07:38:22.37#ibcon#read 6, iclass 35, count 0 2006.190.07:38:22.37#ibcon#end of sib2, iclass 35, count 0 2006.190.07:38:22.37#ibcon#*after write, iclass 35, count 0 2006.190.07:38:22.37#ibcon#*before return 0, iclass 35, count 0 2006.190.07:38:22.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:22.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:38:22.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:38:22.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:38:22.37$vc4f8/vb=6,4 2006.190.07:38:22.37#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.07:38:22.37#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.07:38:22.37#ibcon#ireg 11 cls_cnt 2 2006.190.07:38:22.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:22.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:22.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:22.43#ibcon#enter wrdev, iclass 37, count 2 2006.190.07:38:22.43#ibcon#first serial, iclass 37, count 2 2006.190.07:38:22.43#ibcon#enter sib2, iclass 37, count 2 2006.190.07:38:22.43#ibcon#flushed, iclass 37, count 2 2006.190.07:38:22.43#ibcon#about to write, iclass 37, count 2 2006.190.07:38:22.43#ibcon#wrote, iclass 37, count 2 2006.190.07:38:22.43#ibcon#about to read 3, iclass 37, count 2 2006.190.07:38:22.45#ibcon#read 3, iclass 37, count 2 2006.190.07:38:22.45#ibcon#about to read 4, iclass 37, count 2 2006.190.07:38:22.45#ibcon#read 4, iclass 37, count 2 2006.190.07:38:22.45#ibcon#about to read 5, iclass 37, count 2 2006.190.07:38:22.45#ibcon#read 5, iclass 37, count 2 2006.190.07:38:22.45#ibcon#about to read 6, iclass 37, count 2 2006.190.07:38:22.45#ibcon#read 6, iclass 37, count 2 2006.190.07:38:22.45#ibcon#end of sib2, iclass 37, count 2 2006.190.07:38:22.45#ibcon#*mode == 0, iclass 37, count 2 2006.190.07:38:22.45#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.07:38:22.45#ibcon#[27=AT06-04\r\n] 2006.190.07:38:22.45#ibcon#*before write, iclass 37, count 2 2006.190.07:38:22.45#ibcon#enter sib2, iclass 37, count 2 2006.190.07:38:22.45#ibcon#flushed, iclass 37, count 2 2006.190.07:38:22.45#ibcon#about to write, iclass 37, count 2 2006.190.07:38:22.45#ibcon#wrote, iclass 37, count 2 2006.190.07:38:22.45#ibcon#about to read 3, iclass 37, count 2 2006.190.07:38:22.48#ibcon#read 3, iclass 37, count 2 2006.190.07:38:22.48#ibcon#about to read 4, iclass 37, count 2 2006.190.07:38:22.48#ibcon#read 4, iclass 37, count 2 2006.190.07:38:22.48#ibcon#about to read 5, iclass 37, count 2 2006.190.07:38:22.48#ibcon#read 5, iclass 37, count 2 2006.190.07:38:22.48#ibcon#about to read 6, iclass 37, count 2 2006.190.07:38:22.48#ibcon#read 6, iclass 37, count 2 2006.190.07:38:22.48#ibcon#end of sib2, iclass 37, count 2 2006.190.07:38:22.48#ibcon#*after write, iclass 37, count 2 2006.190.07:38:22.48#ibcon#*before return 0, iclass 37, count 2 2006.190.07:38:22.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:22.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:38:22.48#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.07:38:22.48#ibcon#ireg 7 cls_cnt 0 2006.190.07:38:22.48#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:22.60#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:22.60#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:22.60#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:38:22.60#ibcon#first serial, iclass 37, count 0 2006.190.07:38:22.60#ibcon#enter sib2, iclass 37, count 0 2006.190.07:38:22.60#ibcon#flushed, iclass 37, count 0 2006.190.07:38:22.60#ibcon#about to write, iclass 37, count 0 2006.190.07:38:22.60#ibcon#wrote, iclass 37, count 0 2006.190.07:38:22.60#ibcon#about to read 3, iclass 37, count 0 2006.190.07:38:22.62#ibcon#read 3, iclass 37, count 0 2006.190.07:38:22.62#ibcon#about to read 4, iclass 37, count 0 2006.190.07:38:22.62#ibcon#read 4, iclass 37, count 0 2006.190.07:38:22.62#ibcon#about to read 5, iclass 37, count 0 2006.190.07:38:22.62#ibcon#read 5, iclass 37, count 0 2006.190.07:38:22.62#ibcon#about to read 6, iclass 37, count 0 2006.190.07:38:22.62#ibcon#read 6, iclass 37, count 0 2006.190.07:38:22.62#ibcon#end of sib2, iclass 37, count 0 2006.190.07:38:22.62#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:38:22.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:38:22.62#ibcon#[27=USB\r\n] 2006.190.07:38:22.62#ibcon#*before write, iclass 37, count 0 2006.190.07:38:22.62#ibcon#enter sib2, iclass 37, count 0 2006.190.07:38:22.62#ibcon#flushed, iclass 37, count 0 2006.190.07:38:22.62#ibcon#about to write, iclass 37, count 0 2006.190.07:38:22.62#ibcon#wrote, iclass 37, count 0 2006.190.07:38:22.62#ibcon#about to read 3, iclass 37, count 0 2006.190.07:38:22.65#ibcon#read 3, iclass 37, count 0 2006.190.07:38:22.65#ibcon#about to read 4, iclass 37, count 0 2006.190.07:38:22.65#ibcon#read 4, iclass 37, count 0 2006.190.07:38:22.65#ibcon#about to read 5, iclass 37, count 0 2006.190.07:38:22.65#ibcon#read 5, iclass 37, count 0 2006.190.07:38:22.65#ibcon#about to read 6, iclass 37, count 0 2006.190.07:38:22.65#ibcon#read 6, iclass 37, count 0 2006.190.07:38:22.65#ibcon#end of sib2, iclass 37, count 0 2006.190.07:38:22.65#ibcon#*after write, iclass 37, count 0 2006.190.07:38:22.65#ibcon#*before return 0, iclass 37, count 0 2006.190.07:38:22.65#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:22.65#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:38:22.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:38:22.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:38:22.65$vc4f8/vabw=wide 2006.190.07:38:22.65#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.07:38:22.65#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.07:38:22.65#ibcon#ireg 8 cls_cnt 0 2006.190.07:38:22.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:22.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:22.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:22.65#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:38:22.65#ibcon#first serial, iclass 39, count 0 2006.190.07:38:22.65#ibcon#enter sib2, iclass 39, count 0 2006.190.07:38:22.65#ibcon#flushed, iclass 39, count 0 2006.190.07:38:22.65#ibcon#about to write, iclass 39, count 0 2006.190.07:38:22.65#ibcon#wrote, iclass 39, count 0 2006.190.07:38:22.65#ibcon#about to read 3, iclass 39, count 0 2006.190.07:38:22.67#ibcon#read 3, iclass 39, count 0 2006.190.07:38:22.67#ibcon#about to read 4, iclass 39, count 0 2006.190.07:38:22.67#ibcon#read 4, iclass 39, count 0 2006.190.07:38:22.67#ibcon#about to read 5, iclass 39, count 0 2006.190.07:38:22.67#ibcon#read 5, iclass 39, count 0 2006.190.07:38:22.67#ibcon#about to read 6, iclass 39, count 0 2006.190.07:38:22.67#ibcon#read 6, iclass 39, count 0 2006.190.07:38:22.67#ibcon#end of sib2, iclass 39, count 0 2006.190.07:38:22.67#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:38:22.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:38:22.67#ibcon#[25=BW32\r\n] 2006.190.07:38:22.67#ibcon#*before write, iclass 39, count 0 2006.190.07:38:22.67#ibcon#enter sib2, iclass 39, count 0 2006.190.07:38:22.67#ibcon#flushed, iclass 39, count 0 2006.190.07:38:22.67#ibcon#about to write, iclass 39, count 0 2006.190.07:38:22.67#ibcon#wrote, iclass 39, count 0 2006.190.07:38:22.67#ibcon#about to read 3, iclass 39, count 0 2006.190.07:38:22.70#ibcon#read 3, iclass 39, count 0 2006.190.07:38:22.70#ibcon#about to read 4, iclass 39, count 0 2006.190.07:38:22.70#ibcon#read 4, iclass 39, count 0 2006.190.07:38:22.70#ibcon#about to read 5, iclass 39, count 0 2006.190.07:38:22.70#ibcon#read 5, iclass 39, count 0 2006.190.07:38:22.70#ibcon#about to read 6, iclass 39, count 0 2006.190.07:38:22.70#ibcon#read 6, iclass 39, count 0 2006.190.07:38:22.70#ibcon#end of sib2, iclass 39, count 0 2006.190.07:38:22.70#ibcon#*after write, iclass 39, count 0 2006.190.07:38:22.70#ibcon#*before return 0, iclass 39, count 0 2006.190.07:38:22.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:22.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:38:22.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:38:22.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:38:22.70$vc4f8/vbbw=wide 2006.190.07:38:22.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.07:38:22.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.07:38:22.70#ibcon#ireg 8 cls_cnt 0 2006.190.07:38:22.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:38:22.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:38:22.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:38:22.77#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:38:22.77#ibcon#first serial, iclass 3, count 0 2006.190.07:38:22.77#ibcon#enter sib2, iclass 3, count 0 2006.190.07:38:22.77#ibcon#flushed, iclass 3, count 0 2006.190.07:38:22.77#ibcon#about to write, iclass 3, count 0 2006.190.07:38:22.77#ibcon#wrote, iclass 3, count 0 2006.190.07:38:22.77#ibcon#about to read 3, iclass 3, count 0 2006.190.07:38:22.79#ibcon#read 3, iclass 3, count 0 2006.190.07:38:22.79#ibcon#about to read 4, iclass 3, count 0 2006.190.07:38:22.79#ibcon#read 4, iclass 3, count 0 2006.190.07:38:22.79#ibcon#about to read 5, iclass 3, count 0 2006.190.07:38:22.79#ibcon#read 5, iclass 3, count 0 2006.190.07:38:22.79#ibcon#about to read 6, iclass 3, count 0 2006.190.07:38:22.79#ibcon#read 6, iclass 3, count 0 2006.190.07:38:22.79#ibcon#end of sib2, iclass 3, count 0 2006.190.07:38:22.79#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:38:22.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:38:22.79#ibcon#[27=BW32\r\n] 2006.190.07:38:22.79#ibcon#*before write, iclass 3, count 0 2006.190.07:38:22.79#ibcon#enter sib2, iclass 3, count 0 2006.190.07:38:22.79#ibcon#flushed, iclass 3, count 0 2006.190.07:38:22.79#ibcon#about to write, iclass 3, count 0 2006.190.07:38:22.79#ibcon#wrote, iclass 3, count 0 2006.190.07:38:22.79#ibcon#about to read 3, iclass 3, count 0 2006.190.07:38:22.82#ibcon#read 3, iclass 3, count 0 2006.190.07:38:22.82#ibcon#about to read 4, iclass 3, count 0 2006.190.07:38:22.82#ibcon#read 4, iclass 3, count 0 2006.190.07:38:22.82#ibcon#about to read 5, iclass 3, count 0 2006.190.07:38:22.82#ibcon#read 5, iclass 3, count 0 2006.190.07:38:22.82#ibcon#about to read 6, iclass 3, count 0 2006.190.07:38:22.82#ibcon#read 6, iclass 3, count 0 2006.190.07:38:22.82#ibcon#end of sib2, iclass 3, count 0 2006.190.07:38:22.82#ibcon#*after write, iclass 3, count 0 2006.190.07:38:22.82#ibcon#*before return 0, iclass 3, count 0 2006.190.07:38:22.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:38:22.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:38:22.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:38:22.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:38:22.82$4f8m12a/ifd4f 2006.190.07:38:22.82$ifd4f/lo= 2006.190.07:38:22.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:38:22.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:38:22.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:38:22.82$ifd4f/patch= 2006.190.07:38:22.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:38:22.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:38:22.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:38:22.82$4f8m12a/"form=m,16.000,1:2 2006.190.07:38:22.82$4f8m12a/"tpicd 2006.190.07:38:22.82$4f8m12a/echo=off 2006.190.07:38:22.82$4f8m12a/xlog=off 2006.190.07:38:22.82:!2006.190.07:38:50 2006.190.07:38:37.13#trakl#Source acquired 2006.190.07:38:38.13#flagr#flagr/antenna,acquired 2006.190.07:38:50.00:preob 2006.190.07:38:51.13/onsource/TRACKING 2006.190.07:38:51.13:!2006.190.07:39:00 2006.190.07:39:00.00:data_valid=on 2006.190.07:39:00.00:midob 2006.190.07:39:00.13/onsource/TRACKING 2006.190.07:39:00.13/wx/24.54,1012.2,100 2006.190.07:39:00.33/cable/+6.4702E-03 2006.190.07:39:01.42/va/01,08,usb,yes,40,43 2006.190.07:39:01.42/va/02,07,usb,yes,41,43 2006.190.07:39:01.42/va/03,06,usb,yes,43,44 2006.190.07:39:01.42/va/04,07,usb,yes,42,45 2006.190.07:39:01.42/va/05,07,usb,yes,47,49 2006.190.07:39:01.42/va/06,06,usb,yes,46,46 2006.190.07:39:01.42/va/07,06,usb,yes,47,46 2006.190.07:39:01.42/va/08,06,usb,yes,50,49 2006.190.07:39:01.65/valo/01,532.99,yes,locked 2006.190.07:39:01.65/valo/02,572.99,yes,locked 2006.190.07:39:01.65/valo/03,672.99,yes,locked 2006.190.07:39:01.65/valo/04,832.99,yes,locked 2006.190.07:39:01.65/valo/05,652.99,yes,locked 2006.190.07:39:01.65/valo/06,772.99,yes,locked 2006.190.07:39:01.65/valo/07,832.99,yes,locked 2006.190.07:39:01.65/valo/08,852.99,yes,locked 2006.190.07:39:02.74/vb/01,04,usb,yes,29,28 2006.190.07:39:02.74/vb/02,04,usb,yes,31,32 2006.190.07:39:02.74/vb/03,04,usb,yes,28,31 2006.190.07:39:02.74/vb/04,04,usb,yes,29,29 2006.190.07:39:02.74/vb/05,04,usb,yes,27,31 2006.190.07:39:02.74/vb/06,04,usb,yes,28,31 2006.190.07:39:02.74/vb/07,04,usb,yes,30,30 2006.190.07:39:02.74/vb/08,04,usb,yes,28,31 2006.190.07:39:02.98/vblo/01,632.99,yes,locked 2006.190.07:39:02.98/vblo/02,640.99,yes,locked 2006.190.07:39:02.98/vblo/03,656.99,yes,locked 2006.190.07:39:02.98/vblo/04,712.99,yes,locked 2006.190.07:39:02.98/vblo/05,744.99,yes,locked 2006.190.07:39:02.98/vblo/06,752.99,yes,locked 2006.190.07:39:02.98/vblo/07,734.99,yes,locked 2006.190.07:39:02.98/vblo/08,744.99,yes,locked 2006.190.07:39:03.13/vabw/8 2006.190.07:39:03.28/vbbw/8 2006.190.07:39:03.37/xfe/off,on,15.0 2006.190.07:39:03.75/ifatt/23,28,28,28 2006.190.07:39:04.07/fmout-gps/S +2.84E-07 2006.190.07:39:04.15:!2006.190.07:40:00 2006.190.07:40:00.01:data_valid=off 2006.190.07:40:00.01:postob 2006.190.07:40:00.12/cable/+6.4720E-03 2006.190.07:40:00.12/wx/24.54,1012.2,100 2006.190.07:40:01.07/fmout-gps/S +2.84E-07 2006.190.07:40:01.07:scan_name=190-0740,k06190,60 2006.190.07:40:01.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.190.07:40:01.14#flagr#flagr/antenna,new-source 2006.190.07:40:02.14:checkk5 2006.190.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:40:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:40:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:40:03.68/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:40:04.05/chk_obsdata//k5ts1/T1900739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:40:04.43/chk_obsdata//k5ts2/T1900739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:40:04.81/chk_obsdata//k5ts3/T1900739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:40:05.19/chk_obsdata//k5ts4/T1900739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:40:05.89/k5log//k5ts1_log_newline 2006.190.07:40:06.60/k5log//k5ts2_log_newline 2006.190.07:40:07.29/k5log//k5ts3_log_newline 2006.190.07:40:07.98/k5log//k5ts4_log_newline 2006.190.07:40:08.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:40:08.01:4f8m12a=1 2006.190.07:40:08.01$4f8m12a/echo=on 2006.190.07:40:08.01$4f8m12a/pcalon 2006.190.07:40:08.01$pcalon/"no phase cal control is implemented here 2006.190.07:40:08.01$4f8m12a/"tpicd=stop 2006.190.07:40:08.01$4f8m12a/vc4f8 2006.190.07:40:08.01$vc4f8/valo=1,532.99 2006.190.07:40:08.02#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:40:08.02#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:40:08.02#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:08.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:08.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:08.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:08.02#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:40:08.02#ibcon#first serial, iclass 16, count 0 2006.190.07:40:08.02#ibcon#enter sib2, iclass 16, count 0 2006.190.07:40:08.02#ibcon#flushed, iclass 16, count 0 2006.190.07:40:08.02#ibcon#about to write, iclass 16, count 0 2006.190.07:40:08.02#ibcon#wrote, iclass 16, count 0 2006.190.07:40:08.02#ibcon#about to read 3, iclass 16, count 0 2006.190.07:40:08.10#ibcon#read 3, iclass 16, count 0 2006.190.07:40:08.10#ibcon#about to read 4, iclass 16, count 0 2006.190.07:40:08.10#ibcon#read 4, iclass 16, count 0 2006.190.07:40:08.10#ibcon#about to read 5, iclass 16, count 0 2006.190.07:40:08.10#ibcon#read 5, iclass 16, count 0 2006.190.07:40:08.10#ibcon#about to read 6, iclass 16, count 0 2006.190.07:40:08.10#ibcon#read 6, iclass 16, count 0 2006.190.07:40:08.10#ibcon#end of sib2, iclass 16, count 0 2006.190.07:40:08.10#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:40:08.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:40:08.10#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:40:08.10#ibcon#*before write, iclass 16, count 0 2006.190.07:40:08.10#ibcon#enter sib2, iclass 16, count 0 2006.190.07:40:08.10#ibcon#flushed, iclass 16, count 0 2006.190.07:40:08.10#ibcon#about to write, iclass 16, count 0 2006.190.07:40:08.10#ibcon#wrote, iclass 16, count 0 2006.190.07:40:08.10#ibcon#about to read 3, iclass 16, count 0 2006.190.07:40:08.15#ibcon#read 3, iclass 16, count 0 2006.190.07:40:08.15#ibcon#about to read 4, iclass 16, count 0 2006.190.07:40:08.15#ibcon#read 4, iclass 16, count 0 2006.190.07:40:08.15#ibcon#about to read 5, iclass 16, count 0 2006.190.07:40:08.15#ibcon#read 5, iclass 16, count 0 2006.190.07:40:08.15#ibcon#about to read 6, iclass 16, count 0 2006.190.07:40:08.15#ibcon#read 6, iclass 16, count 0 2006.190.07:40:08.15#ibcon#end of sib2, iclass 16, count 0 2006.190.07:40:08.15#ibcon#*after write, iclass 16, count 0 2006.190.07:40:08.15#ibcon#*before return 0, iclass 16, count 0 2006.190.07:40:08.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:08.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:08.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:40:08.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:40:08.15$vc4f8/va=1,8 2006.190.07:40:08.15#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.07:40:08.15#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.07:40:08.15#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:08.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:08.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:08.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:08.15#ibcon#enter wrdev, iclass 18, count 2 2006.190.07:40:08.15#ibcon#first serial, iclass 18, count 2 2006.190.07:40:08.15#ibcon#enter sib2, iclass 18, count 2 2006.190.07:40:08.15#ibcon#flushed, iclass 18, count 2 2006.190.07:40:08.15#ibcon#about to write, iclass 18, count 2 2006.190.07:40:08.15#ibcon#wrote, iclass 18, count 2 2006.190.07:40:08.15#ibcon#about to read 3, iclass 18, count 2 2006.190.07:40:08.17#ibcon#read 3, iclass 18, count 2 2006.190.07:40:08.17#ibcon#about to read 4, iclass 18, count 2 2006.190.07:40:08.17#ibcon#read 4, iclass 18, count 2 2006.190.07:40:08.17#ibcon#about to read 5, iclass 18, count 2 2006.190.07:40:08.17#ibcon#read 5, iclass 18, count 2 2006.190.07:40:08.17#ibcon#about to read 6, iclass 18, count 2 2006.190.07:40:08.17#ibcon#read 6, iclass 18, count 2 2006.190.07:40:08.17#ibcon#end of sib2, iclass 18, count 2 2006.190.07:40:08.17#ibcon#*mode == 0, iclass 18, count 2 2006.190.07:40:08.17#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.07:40:08.17#ibcon#[25=AT01-08\r\n] 2006.190.07:40:08.17#ibcon#*before write, iclass 18, count 2 2006.190.07:40:08.17#ibcon#enter sib2, iclass 18, count 2 2006.190.07:40:08.17#ibcon#flushed, iclass 18, count 2 2006.190.07:40:08.17#ibcon#about to write, iclass 18, count 2 2006.190.07:40:08.17#ibcon#wrote, iclass 18, count 2 2006.190.07:40:08.17#ibcon#about to read 3, iclass 18, count 2 2006.190.07:40:08.20#ibcon#read 3, iclass 18, count 2 2006.190.07:40:08.20#ibcon#about to read 4, iclass 18, count 2 2006.190.07:40:08.20#ibcon#read 4, iclass 18, count 2 2006.190.07:40:08.20#ibcon#about to read 5, iclass 18, count 2 2006.190.07:40:08.20#ibcon#read 5, iclass 18, count 2 2006.190.07:40:08.20#ibcon#about to read 6, iclass 18, count 2 2006.190.07:40:08.20#ibcon#read 6, iclass 18, count 2 2006.190.07:40:08.20#ibcon#end of sib2, iclass 18, count 2 2006.190.07:40:08.20#ibcon#*after write, iclass 18, count 2 2006.190.07:40:08.20#ibcon#*before return 0, iclass 18, count 2 2006.190.07:40:08.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:08.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:08.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.07:40:08.20#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:08.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:08.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:08.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:08.32#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:40:08.32#ibcon#first serial, iclass 18, count 0 2006.190.07:40:08.32#ibcon#enter sib2, iclass 18, count 0 2006.190.07:40:08.32#ibcon#flushed, iclass 18, count 0 2006.190.07:40:08.32#ibcon#about to write, iclass 18, count 0 2006.190.07:40:08.32#ibcon#wrote, iclass 18, count 0 2006.190.07:40:08.32#ibcon#about to read 3, iclass 18, count 0 2006.190.07:40:08.34#ibcon#read 3, iclass 18, count 0 2006.190.07:40:08.34#ibcon#about to read 4, iclass 18, count 0 2006.190.07:40:08.34#ibcon#read 4, iclass 18, count 0 2006.190.07:40:08.34#ibcon#about to read 5, iclass 18, count 0 2006.190.07:40:08.34#ibcon#read 5, iclass 18, count 0 2006.190.07:40:08.34#ibcon#about to read 6, iclass 18, count 0 2006.190.07:40:08.34#ibcon#read 6, iclass 18, count 0 2006.190.07:40:08.34#ibcon#end of sib2, iclass 18, count 0 2006.190.07:40:08.34#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:40:08.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:40:08.34#ibcon#[25=USB\r\n] 2006.190.07:40:08.34#ibcon#*before write, iclass 18, count 0 2006.190.07:40:08.34#ibcon#enter sib2, iclass 18, count 0 2006.190.07:40:08.34#ibcon#flushed, iclass 18, count 0 2006.190.07:40:08.34#ibcon#about to write, iclass 18, count 0 2006.190.07:40:08.34#ibcon#wrote, iclass 18, count 0 2006.190.07:40:08.34#ibcon#about to read 3, iclass 18, count 0 2006.190.07:40:08.37#ibcon#read 3, iclass 18, count 0 2006.190.07:40:08.37#ibcon#about to read 4, iclass 18, count 0 2006.190.07:40:08.37#ibcon#read 4, iclass 18, count 0 2006.190.07:40:08.37#ibcon#about to read 5, iclass 18, count 0 2006.190.07:40:08.37#ibcon#read 5, iclass 18, count 0 2006.190.07:40:08.37#ibcon#about to read 6, iclass 18, count 0 2006.190.07:40:08.37#ibcon#read 6, iclass 18, count 0 2006.190.07:40:08.37#ibcon#end of sib2, iclass 18, count 0 2006.190.07:40:08.37#ibcon#*after write, iclass 18, count 0 2006.190.07:40:08.37#ibcon#*before return 0, iclass 18, count 0 2006.190.07:40:08.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:08.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:08.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:40:08.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:40:08.37$vc4f8/valo=2,572.99 2006.190.07:40:08.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:40:08.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:40:08.37#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:08.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:08.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:08.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:08.37#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:40:08.37#ibcon#first serial, iclass 20, count 0 2006.190.07:40:08.37#ibcon#enter sib2, iclass 20, count 0 2006.190.07:40:08.37#ibcon#flushed, iclass 20, count 0 2006.190.07:40:08.37#ibcon#about to write, iclass 20, count 0 2006.190.07:40:08.37#ibcon#wrote, iclass 20, count 0 2006.190.07:40:08.37#ibcon#about to read 3, iclass 20, count 0 2006.190.07:40:08.39#ibcon#read 3, iclass 20, count 0 2006.190.07:40:08.39#ibcon#about to read 4, iclass 20, count 0 2006.190.07:40:08.39#ibcon#read 4, iclass 20, count 0 2006.190.07:40:08.39#ibcon#about to read 5, iclass 20, count 0 2006.190.07:40:08.39#ibcon#read 5, iclass 20, count 0 2006.190.07:40:08.39#ibcon#about to read 6, iclass 20, count 0 2006.190.07:40:08.39#ibcon#read 6, iclass 20, count 0 2006.190.07:40:08.39#ibcon#end of sib2, iclass 20, count 0 2006.190.07:40:08.39#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:40:08.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:40:08.39#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:40:08.39#ibcon#*before write, iclass 20, count 0 2006.190.07:40:08.39#ibcon#enter sib2, iclass 20, count 0 2006.190.07:40:08.39#ibcon#flushed, iclass 20, count 0 2006.190.07:40:08.39#ibcon#about to write, iclass 20, count 0 2006.190.07:40:08.39#ibcon#wrote, iclass 20, count 0 2006.190.07:40:08.39#ibcon#about to read 3, iclass 20, count 0 2006.190.07:40:08.43#ibcon#read 3, iclass 20, count 0 2006.190.07:40:08.43#ibcon#about to read 4, iclass 20, count 0 2006.190.07:40:08.43#ibcon#read 4, iclass 20, count 0 2006.190.07:40:08.43#ibcon#about to read 5, iclass 20, count 0 2006.190.07:40:08.43#ibcon#read 5, iclass 20, count 0 2006.190.07:40:08.43#ibcon#about to read 6, iclass 20, count 0 2006.190.07:40:08.43#ibcon#read 6, iclass 20, count 0 2006.190.07:40:08.43#ibcon#end of sib2, iclass 20, count 0 2006.190.07:40:08.43#ibcon#*after write, iclass 20, count 0 2006.190.07:40:08.43#ibcon#*before return 0, iclass 20, count 0 2006.190.07:40:08.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:08.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:08.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:40:08.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:40:08.43$vc4f8/va=2,7 2006.190.07:40:08.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:40:08.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:40:08.43#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:08.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:08.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:08.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:08.50#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:40:08.50#ibcon#first serial, iclass 22, count 2 2006.190.07:40:08.50#ibcon#enter sib2, iclass 22, count 2 2006.190.07:40:08.50#ibcon#flushed, iclass 22, count 2 2006.190.07:40:08.50#ibcon#about to write, iclass 22, count 2 2006.190.07:40:08.50#ibcon#wrote, iclass 22, count 2 2006.190.07:40:08.50#ibcon#about to read 3, iclass 22, count 2 2006.190.07:40:08.51#ibcon#read 3, iclass 22, count 2 2006.190.07:40:08.51#ibcon#about to read 4, iclass 22, count 2 2006.190.07:40:08.51#ibcon#read 4, iclass 22, count 2 2006.190.07:40:08.51#ibcon#about to read 5, iclass 22, count 2 2006.190.07:40:08.51#ibcon#read 5, iclass 22, count 2 2006.190.07:40:08.51#ibcon#about to read 6, iclass 22, count 2 2006.190.07:40:08.51#ibcon#read 6, iclass 22, count 2 2006.190.07:40:08.51#ibcon#end of sib2, iclass 22, count 2 2006.190.07:40:08.51#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:40:08.51#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:40:08.51#ibcon#[25=AT02-07\r\n] 2006.190.07:40:08.51#ibcon#*before write, iclass 22, count 2 2006.190.07:40:08.51#ibcon#enter sib2, iclass 22, count 2 2006.190.07:40:08.51#ibcon#flushed, iclass 22, count 2 2006.190.07:40:08.51#ibcon#about to write, iclass 22, count 2 2006.190.07:40:08.51#ibcon#wrote, iclass 22, count 2 2006.190.07:40:08.51#ibcon#about to read 3, iclass 22, count 2 2006.190.07:40:08.54#ibcon#read 3, iclass 22, count 2 2006.190.07:40:08.54#ibcon#about to read 4, iclass 22, count 2 2006.190.07:40:08.54#ibcon#read 4, iclass 22, count 2 2006.190.07:40:08.54#ibcon#about to read 5, iclass 22, count 2 2006.190.07:40:08.54#ibcon#read 5, iclass 22, count 2 2006.190.07:40:08.54#ibcon#about to read 6, iclass 22, count 2 2006.190.07:40:08.54#ibcon#read 6, iclass 22, count 2 2006.190.07:40:08.54#ibcon#end of sib2, iclass 22, count 2 2006.190.07:40:08.54#ibcon#*after write, iclass 22, count 2 2006.190.07:40:08.54#ibcon#*before return 0, iclass 22, count 2 2006.190.07:40:08.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:08.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:08.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:40:08.54#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:08.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:08.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:08.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:08.66#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:40:08.66#ibcon#first serial, iclass 22, count 0 2006.190.07:40:08.66#ibcon#enter sib2, iclass 22, count 0 2006.190.07:40:08.66#ibcon#flushed, iclass 22, count 0 2006.190.07:40:08.66#ibcon#about to write, iclass 22, count 0 2006.190.07:40:08.66#ibcon#wrote, iclass 22, count 0 2006.190.07:40:08.66#ibcon#about to read 3, iclass 22, count 0 2006.190.07:40:08.68#ibcon#read 3, iclass 22, count 0 2006.190.07:40:08.68#ibcon#about to read 4, iclass 22, count 0 2006.190.07:40:08.68#ibcon#read 4, iclass 22, count 0 2006.190.07:40:08.68#ibcon#about to read 5, iclass 22, count 0 2006.190.07:40:08.68#ibcon#read 5, iclass 22, count 0 2006.190.07:40:08.68#ibcon#about to read 6, iclass 22, count 0 2006.190.07:40:08.68#ibcon#read 6, iclass 22, count 0 2006.190.07:40:08.68#ibcon#end of sib2, iclass 22, count 0 2006.190.07:40:08.68#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:40:08.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:40:08.68#ibcon#[25=USB\r\n] 2006.190.07:40:08.68#ibcon#*before write, iclass 22, count 0 2006.190.07:40:08.68#ibcon#enter sib2, iclass 22, count 0 2006.190.07:40:08.68#ibcon#flushed, iclass 22, count 0 2006.190.07:40:08.68#ibcon#about to write, iclass 22, count 0 2006.190.07:40:08.68#ibcon#wrote, iclass 22, count 0 2006.190.07:40:08.68#ibcon#about to read 3, iclass 22, count 0 2006.190.07:40:08.71#ibcon#read 3, iclass 22, count 0 2006.190.07:40:08.71#ibcon#about to read 4, iclass 22, count 0 2006.190.07:40:08.71#ibcon#read 4, iclass 22, count 0 2006.190.07:40:08.71#ibcon#about to read 5, iclass 22, count 0 2006.190.07:40:08.71#ibcon#read 5, iclass 22, count 0 2006.190.07:40:08.71#ibcon#about to read 6, iclass 22, count 0 2006.190.07:40:08.71#ibcon#read 6, iclass 22, count 0 2006.190.07:40:08.71#ibcon#end of sib2, iclass 22, count 0 2006.190.07:40:08.71#ibcon#*after write, iclass 22, count 0 2006.190.07:40:08.71#ibcon#*before return 0, iclass 22, count 0 2006.190.07:40:08.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:08.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:08.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:40:08.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:40:08.71$vc4f8/valo=3,672.99 2006.190.07:40:08.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.07:40:08.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.07:40:08.71#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:08.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:08.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:08.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:08.71#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:40:08.71#ibcon#first serial, iclass 24, count 0 2006.190.07:40:08.71#ibcon#enter sib2, iclass 24, count 0 2006.190.07:40:08.71#ibcon#flushed, iclass 24, count 0 2006.190.07:40:08.71#ibcon#about to write, iclass 24, count 0 2006.190.07:40:08.71#ibcon#wrote, iclass 24, count 0 2006.190.07:40:08.71#ibcon#about to read 3, iclass 24, count 0 2006.190.07:40:08.73#ibcon#read 3, iclass 24, count 0 2006.190.07:40:08.73#ibcon#about to read 4, iclass 24, count 0 2006.190.07:40:08.73#ibcon#read 4, iclass 24, count 0 2006.190.07:40:08.73#ibcon#about to read 5, iclass 24, count 0 2006.190.07:40:08.73#ibcon#read 5, iclass 24, count 0 2006.190.07:40:08.73#ibcon#about to read 6, iclass 24, count 0 2006.190.07:40:08.73#ibcon#read 6, iclass 24, count 0 2006.190.07:40:08.73#ibcon#end of sib2, iclass 24, count 0 2006.190.07:40:08.73#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:40:08.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:40:08.73#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:40:08.73#ibcon#*before write, iclass 24, count 0 2006.190.07:40:08.73#ibcon#enter sib2, iclass 24, count 0 2006.190.07:40:08.73#ibcon#flushed, iclass 24, count 0 2006.190.07:40:08.73#ibcon#about to write, iclass 24, count 0 2006.190.07:40:08.73#ibcon#wrote, iclass 24, count 0 2006.190.07:40:08.73#ibcon#about to read 3, iclass 24, count 0 2006.190.07:40:08.77#ibcon#read 3, iclass 24, count 0 2006.190.07:40:08.77#ibcon#about to read 4, iclass 24, count 0 2006.190.07:40:08.77#ibcon#read 4, iclass 24, count 0 2006.190.07:40:08.77#ibcon#about to read 5, iclass 24, count 0 2006.190.07:40:08.77#ibcon#read 5, iclass 24, count 0 2006.190.07:40:08.77#ibcon#about to read 6, iclass 24, count 0 2006.190.07:40:08.77#ibcon#read 6, iclass 24, count 0 2006.190.07:40:08.77#ibcon#end of sib2, iclass 24, count 0 2006.190.07:40:08.77#ibcon#*after write, iclass 24, count 0 2006.190.07:40:08.77#ibcon#*before return 0, iclass 24, count 0 2006.190.07:40:08.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:08.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:08.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:40:08.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:40:08.77$vc4f8/va=3,6 2006.190.07:40:08.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.07:40:08.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.07:40:08.77#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:08.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:08.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:08.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:08.83#ibcon#enter wrdev, iclass 26, count 2 2006.190.07:40:08.83#ibcon#first serial, iclass 26, count 2 2006.190.07:40:08.83#ibcon#enter sib2, iclass 26, count 2 2006.190.07:40:08.83#ibcon#flushed, iclass 26, count 2 2006.190.07:40:08.83#ibcon#about to write, iclass 26, count 2 2006.190.07:40:08.83#ibcon#wrote, iclass 26, count 2 2006.190.07:40:08.83#ibcon#about to read 3, iclass 26, count 2 2006.190.07:40:08.85#ibcon#read 3, iclass 26, count 2 2006.190.07:40:08.85#ibcon#about to read 4, iclass 26, count 2 2006.190.07:40:08.85#ibcon#read 4, iclass 26, count 2 2006.190.07:40:08.85#ibcon#about to read 5, iclass 26, count 2 2006.190.07:40:08.85#ibcon#read 5, iclass 26, count 2 2006.190.07:40:08.85#ibcon#about to read 6, iclass 26, count 2 2006.190.07:40:08.85#ibcon#read 6, iclass 26, count 2 2006.190.07:40:08.85#ibcon#end of sib2, iclass 26, count 2 2006.190.07:40:08.85#ibcon#*mode == 0, iclass 26, count 2 2006.190.07:40:08.85#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.07:40:08.85#ibcon#[25=AT03-06\r\n] 2006.190.07:40:08.85#ibcon#*before write, iclass 26, count 2 2006.190.07:40:08.85#ibcon#enter sib2, iclass 26, count 2 2006.190.07:40:08.85#ibcon#flushed, iclass 26, count 2 2006.190.07:40:08.85#ibcon#about to write, iclass 26, count 2 2006.190.07:40:08.85#ibcon#wrote, iclass 26, count 2 2006.190.07:40:08.85#ibcon#about to read 3, iclass 26, count 2 2006.190.07:40:08.88#ibcon#read 3, iclass 26, count 2 2006.190.07:40:08.88#ibcon#about to read 4, iclass 26, count 2 2006.190.07:40:08.88#ibcon#read 4, iclass 26, count 2 2006.190.07:40:08.88#ibcon#about to read 5, iclass 26, count 2 2006.190.07:40:08.88#ibcon#read 5, iclass 26, count 2 2006.190.07:40:08.88#ibcon#about to read 6, iclass 26, count 2 2006.190.07:40:08.88#ibcon#read 6, iclass 26, count 2 2006.190.07:40:08.88#ibcon#end of sib2, iclass 26, count 2 2006.190.07:40:08.88#ibcon#*after write, iclass 26, count 2 2006.190.07:40:08.88#ibcon#*before return 0, iclass 26, count 2 2006.190.07:40:08.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:08.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:08.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.07:40:08.88#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:08.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:09.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:09.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:09.00#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:40:09.00#ibcon#first serial, iclass 26, count 0 2006.190.07:40:09.00#ibcon#enter sib2, iclass 26, count 0 2006.190.07:40:09.00#ibcon#flushed, iclass 26, count 0 2006.190.07:40:09.00#ibcon#about to write, iclass 26, count 0 2006.190.07:40:09.00#ibcon#wrote, iclass 26, count 0 2006.190.07:40:09.00#ibcon#about to read 3, iclass 26, count 0 2006.190.07:40:09.02#ibcon#read 3, iclass 26, count 0 2006.190.07:40:09.02#ibcon#about to read 4, iclass 26, count 0 2006.190.07:40:09.02#ibcon#read 4, iclass 26, count 0 2006.190.07:40:09.02#ibcon#about to read 5, iclass 26, count 0 2006.190.07:40:09.02#ibcon#read 5, iclass 26, count 0 2006.190.07:40:09.02#ibcon#about to read 6, iclass 26, count 0 2006.190.07:40:09.02#ibcon#read 6, iclass 26, count 0 2006.190.07:40:09.02#ibcon#end of sib2, iclass 26, count 0 2006.190.07:40:09.02#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:40:09.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:40:09.02#ibcon#[25=USB\r\n] 2006.190.07:40:09.02#ibcon#*before write, iclass 26, count 0 2006.190.07:40:09.02#ibcon#enter sib2, iclass 26, count 0 2006.190.07:40:09.02#ibcon#flushed, iclass 26, count 0 2006.190.07:40:09.02#ibcon#about to write, iclass 26, count 0 2006.190.07:40:09.02#ibcon#wrote, iclass 26, count 0 2006.190.07:40:09.02#ibcon#about to read 3, iclass 26, count 0 2006.190.07:40:09.05#ibcon#read 3, iclass 26, count 0 2006.190.07:40:09.05#ibcon#about to read 4, iclass 26, count 0 2006.190.07:40:09.05#ibcon#read 4, iclass 26, count 0 2006.190.07:40:09.05#ibcon#about to read 5, iclass 26, count 0 2006.190.07:40:09.05#ibcon#read 5, iclass 26, count 0 2006.190.07:40:09.05#ibcon#about to read 6, iclass 26, count 0 2006.190.07:40:09.05#ibcon#read 6, iclass 26, count 0 2006.190.07:40:09.05#ibcon#end of sib2, iclass 26, count 0 2006.190.07:40:09.05#ibcon#*after write, iclass 26, count 0 2006.190.07:40:09.05#ibcon#*before return 0, iclass 26, count 0 2006.190.07:40:09.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:09.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:09.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:40:09.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:40:09.05$vc4f8/valo=4,832.99 2006.190.07:40:09.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:40:09.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:40:09.05#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:09.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:09.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:09.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:09.05#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:40:09.05#ibcon#first serial, iclass 28, count 0 2006.190.07:40:09.05#ibcon#enter sib2, iclass 28, count 0 2006.190.07:40:09.05#ibcon#flushed, iclass 28, count 0 2006.190.07:40:09.05#ibcon#about to write, iclass 28, count 0 2006.190.07:40:09.05#ibcon#wrote, iclass 28, count 0 2006.190.07:40:09.05#ibcon#about to read 3, iclass 28, count 0 2006.190.07:40:09.07#ibcon#read 3, iclass 28, count 0 2006.190.07:40:09.07#ibcon#about to read 4, iclass 28, count 0 2006.190.07:40:09.07#ibcon#read 4, iclass 28, count 0 2006.190.07:40:09.07#ibcon#about to read 5, iclass 28, count 0 2006.190.07:40:09.07#ibcon#read 5, iclass 28, count 0 2006.190.07:40:09.07#ibcon#about to read 6, iclass 28, count 0 2006.190.07:40:09.07#ibcon#read 6, iclass 28, count 0 2006.190.07:40:09.07#ibcon#end of sib2, iclass 28, count 0 2006.190.07:40:09.07#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:40:09.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:40:09.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:40:09.07#ibcon#*before write, iclass 28, count 0 2006.190.07:40:09.07#ibcon#enter sib2, iclass 28, count 0 2006.190.07:40:09.07#ibcon#flushed, iclass 28, count 0 2006.190.07:40:09.07#ibcon#about to write, iclass 28, count 0 2006.190.07:40:09.07#ibcon#wrote, iclass 28, count 0 2006.190.07:40:09.07#ibcon#about to read 3, iclass 28, count 0 2006.190.07:40:09.11#ibcon#read 3, iclass 28, count 0 2006.190.07:40:09.11#ibcon#about to read 4, iclass 28, count 0 2006.190.07:40:09.11#ibcon#read 4, iclass 28, count 0 2006.190.07:40:09.11#ibcon#about to read 5, iclass 28, count 0 2006.190.07:40:09.11#ibcon#read 5, iclass 28, count 0 2006.190.07:40:09.11#ibcon#about to read 6, iclass 28, count 0 2006.190.07:40:09.11#ibcon#read 6, iclass 28, count 0 2006.190.07:40:09.11#ibcon#end of sib2, iclass 28, count 0 2006.190.07:40:09.11#ibcon#*after write, iclass 28, count 0 2006.190.07:40:09.11#ibcon#*before return 0, iclass 28, count 0 2006.190.07:40:09.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:09.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:09.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:40:09.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:40:09.11$vc4f8/va=4,7 2006.190.07:40:09.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:40:09.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:40:09.11#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:09.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:09.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:09.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:09.17#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:40:09.17#ibcon#first serial, iclass 30, count 2 2006.190.07:40:09.17#ibcon#enter sib2, iclass 30, count 2 2006.190.07:40:09.17#ibcon#flushed, iclass 30, count 2 2006.190.07:40:09.17#ibcon#about to write, iclass 30, count 2 2006.190.07:40:09.17#ibcon#wrote, iclass 30, count 2 2006.190.07:40:09.17#ibcon#about to read 3, iclass 30, count 2 2006.190.07:40:09.19#ibcon#read 3, iclass 30, count 2 2006.190.07:40:09.19#ibcon#about to read 4, iclass 30, count 2 2006.190.07:40:09.19#ibcon#read 4, iclass 30, count 2 2006.190.07:40:09.19#ibcon#about to read 5, iclass 30, count 2 2006.190.07:40:09.19#ibcon#read 5, iclass 30, count 2 2006.190.07:40:09.19#ibcon#about to read 6, iclass 30, count 2 2006.190.07:40:09.19#ibcon#read 6, iclass 30, count 2 2006.190.07:40:09.19#ibcon#end of sib2, iclass 30, count 2 2006.190.07:40:09.19#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:40:09.19#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:40:09.19#ibcon#[25=AT04-07\r\n] 2006.190.07:40:09.19#ibcon#*before write, iclass 30, count 2 2006.190.07:40:09.19#ibcon#enter sib2, iclass 30, count 2 2006.190.07:40:09.19#ibcon#flushed, iclass 30, count 2 2006.190.07:40:09.19#ibcon#about to write, iclass 30, count 2 2006.190.07:40:09.19#ibcon#wrote, iclass 30, count 2 2006.190.07:40:09.19#ibcon#about to read 3, iclass 30, count 2 2006.190.07:40:09.22#ibcon#read 3, iclass 30, count 2 2006.190.07:40:09.22#ibcon#about to read 4, iclass 30, count 2 2006.190.07:40:09.22#ibcon#read 4, iclass 30, count 2 2006.190.07:40:09.22#ibcon#about to read 5, iclass 30, count 2 2006.190.07:40:09.22#ibcon#read 5, iclass 30, count 2 2006.190.07:40:09.22#ibcon#about to read 6, iclass 30, count 2 2006.190.07:40:09.22#ibcon#read 6, iclass 30, count 2 2006.190.07:40:09.22#ibcon#end of sib2, iclass 30, count 2 2006.190.07:40:09.22#ibcon#*after write, iclass 30, count 2 2006.190.07:40:09.22#ibcon#*before return 0, iclass 30, count 2 2006.190.07:40:09.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:09.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:09.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:40:09.22#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:09.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:09.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:09.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:09.34#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:40:09.34#ibcon#first serial, iclass 30, count 0 2006.190.07:40:09.34#ibcon#enter sib2, iclass 30, count 0 2006.190.07:40:09.34#ibcon#flushed, iclass 30, count 0 2006.190.07:40:09.34#ibcon#about to write, iclass 30, count 0 2006.190.07:40:09.34#ibcon#wrote, iclass 30, count 0 2006.190.07:40:09.34#ibcon#about to read 3, iclass 30, count 0 2006.190.07:40:09.36#ibcon#read 3, iclass 30, count 0 2006.190.07:40:09.36#ibcon#about to read 4, iclass 30, count 0 2006.190.07:40:09.36#ibcon#read 4, iclass 30, count 0 2006.190.07:40:09.36#ibcon#about to read 5, iclass 30, count 0 2006.190.07:40:09.36#ibcon#read 5, iclass 30, count 0 2006.190.07:40:09.36#ibcon#about to read 6, iclass 30, count 0 2006.190.07:40:09.36#ibcon#read 6, iclass 30, count 0 2006.190.07:40:09.36#ibcon#end of sib2, iclass 30, count 0 2006.190.07:40:09.36#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:40:09.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:40:09.36#ibcon#[25=USB\r\n] 2006.190.07:40:09.36#ibcon#*before write, iclass 30, count 0 2006.190.07:40:09.36#ibcon#enter sib2, iclass 30, count 0 2006.190.07:40:09.36#ibcon#flushed, iclass 30, count 0 2006.190.07:40:09.36#ibcon#about to write, iclass 30, count 0 2006.190.07:40:09.36#ibcon#wrote, iclass 30, count 0 2006.190.07:40:09.36#ibcon#about to read 3, iclass 30, count 0 2006.190.07:40:09.39#ibcon#read 3, iclass 30, count 0 2006.190.07:40:09.39#ibcon#about to read 4, iclass 30, count 0 2006.190.07:40:09.39#ibcon#read 4, iclass 30, count 0 2006.190.07:40:09.39#ibcon#about to read 5, iclass 30, count 0 2006.190.07:40:09.39#ibcon#read 5, iclass 30, count 0 2006.190.07:40:09.39#ibcon#about to read 6, iclass 30, count 0 2006.190.07:40:09.39#ibcon#read 6, iclass 30, count 0 2006.190.07:40:09.39#ibcon#end of sib2, iclass 30, count 0 2006.190.07:40:09.39#ibcon#*after write, iclass 30, count 0 2006.190.07:40:09.39#ibcon#*before return 0, iclass 30, count 0 2006.190.07:40:09.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:09.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:09.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:40:09.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:40:09.39$vc4f8/valo=5,652.99 2006.190.07:40:09.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:40:09.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:40:09.39#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:09.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:09.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:09.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:09.39#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:40:09.39#ibcon#first serial, iclass 32, count 0 2006.190.07:40:09.39#ibcon#enter sib2, iclass 32, count 0 2006.190.07:40:09.39#ibcon#flushed, iclass 32, count 0 2006.190.07:40:09.39#ibcon#about to write, iclass 32, count 0 2006.190.07:40:09.39#ibcon#wrote, iclass 32, count 0 2006.190.07:40:09.39#ibcon#about to read 3, iclass 32, count 0 2006.190.07:40:09.41#ibcon#read 3, iclass 32, count 0 2006.190.07:40:09.41#ibcon#about to read 4, iclass 32, count 0 2006.190.07:40:09.41#ibcon#read 4, iclass 32, count 0 2006.190.07:40:09.41#ibcon#about to read 5, iclass 32, count 0 2006.190.07:40:09.41#ibcon#read 5, iclass 32, count 0 2006.190.07:40:09.41#ibcon#about to read 6, iclass 32, count 0 2006.190.07:40:09.41#ibcon#read 6, iclass 32, count 0 2006.190.07:40:09.41#ibcon#end of sib2, iclass 32, count 0 2006.190.07:40:09.41#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:40:09.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:40:09.41#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:40:09.41#ibcon#*before write, iclass 32, count 0 2006.190.07:40:09.41#ibcon#enter sib2, iclass 32, count 0 2006.190.07:40:09.41#ibcon#flushed, iclass 32, count 0 2006.190.07:40:09.41#ibcon#about to write, iclass 32, count 0 2006.190.07:40:09.41#ibcon#wrote, iclass 32, count 0 2006.190.07:40:09.41#ibcon#about to read 3, iclass 32, count 0 2006.190.07:40:09.45#ibcon#read 3, iclass 32, count 0 2006.190.07:40:09.45#ibcon#about to read 4, iclass 32, count 0 2006.190.07:40:09.45#ibcon#read 4, iclass 32, count 0 2006.190.07:40:09.45#ibcon#about to read 5, iclass 32, count 0 2006.190.07:40:09.45#ibcon#read 5, iclass 32, count 0 2006.190.07:40:09.45#ibcon#about to read 6, iclass 32, count 0 2006.190.07:40:09.45#ibcon#read 6, iclass 32, count 0 2006.190.07:40:09.45#ibcon#end of sib2, iclass 32, count 0 2006.190.07:40:09.45#ibcon#*after write, iclass 32, count 0 2006.190.07:40:09.45#ibcon#*before return 0, iclass 32, count 0 2006.190.07:40:09.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:09.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:09.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:40:09.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:40:09.45$vc4f8/va=5,7 2006.190.07:40:09.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:40:09.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:40:09.45#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:09.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:09.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:09.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:09.51#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:40:09.51#ibcon#first serial, iclass 34, count 2 2006.190.07:40:09.51#ibcon#enter sib2, iclass 34, count 2 2006.190.07:40:09.51#ibcon#flushed, iclass 34, count 2 2006.190.07:40:09.51#ibcon#about to write, iclass 34, count 2 2006.190.07:40:09.51#ibcon#wrote, iclass 34, count 2 2006.190.07:40:09.51#ibcon#about to read 3, iclass 34, count 2 2006.190.07:40:09.53#ibcon#read 3, iclass 34, count 2 2006.190.07:40:09.53#ibcon#about to read 4, iclass 34, count 2 2006.190.07:40:09.53#ibcon#read 4, iclass 34, count 2 2006.190.07:40:09.53#ibcon#about to read 5, iclass 34, count 2 2006.190.07:40:09.53#ibcon#read 5, iclass 34, count 2 2006.190.07:40:09.53#ibcon#about to read 6, iclass 34, count 2 2006.190.07:40:09.53#ibcon#read 6, iclass 34, count 2 2006.190.07:40:09.53#ibcon#end of sib2, iclass 34, count 2 2006.190.07:40:09.53#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:40:09.53#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:40:09.53#ibcon#[25=AT05-07\r\n] 2006.190.07:40:09.53#ibcon#*before write, iclass 34, count 2 2006.190.07:40:09.53#ibcon#enter sib2, iclass 34, count 2 2006.190.07:40:09.53#ibcon#flushed, iclass 34, count 2 2006.190.07:40:09.53#ibcon#about to write, iclass 34, count 2 2006.190.07:40:09.53#ibcon#wrote, iclass 34, count 2 2006.190.07:40:09.53#ibcon#about to read 3, iclass 34, count 2 2006.190.07:40:09.56#ibcon#read 3, iclass 34, count 2 2006.190.07:40:09.56#ibcon#about to read 4, iclass 34, count 2 2006.190.07:40:09.56#ibcon#read 4, iclass 34, count 2 2006.190.07:40:09.56#ibcon#about to read 5, iclass 34, count 2 2006.190.07:40:09.56#ibcon#read 5, iclass 34, count 2 2006.190.07:40:09.56#ibcon#about to read 6, iclass 34, count 2 2006.190.07:40:09.56#ibcon#read 6, iclass 34, count 2 2006.190.07:40:09.56#ibcon#end of sib2, iclass 34, count 2 2006.190.07:40:09.56#ibcon#*after write, iclass 34, count 2 2006.190.07:40:09.56#ibcon#*before return 0, iclass 34, count 2 2006.190.07:40:09.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:09.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:09.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:40:09.56#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:09.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:09.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:09.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:09.68#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:40:09.68#ibcon#first serial, iclass 34, count 0 2006.190.07:40:09.68#ibcon#enter sib2, iclass 34, count 0 2006.190.07:40:09.68#ibcon#flushed, iclass 34, count 0 2006.190.07:40:09.68#ibcon#about to write, iclass 34, count 0 2006.190.07:40:09.68#ibcon#wrote, iclass 34, count 0 2006.190.07:40:09.68#ibcon#about to read 3, iclass 34, count 0 2006.190.07:40:09.70#ibcon#read 3, iclass 34, count 0 2006.190.07:40:09.70#ibcon#about to read 4, iclass 34, count 0 2006.190.07:40:09.70#ibcon#read 4, iclass 34, count 0 2006.190.07:40:09.70#ibcon#about to read 5, iclass 34, count 0 2006.190.07:40:09.70#ibcon#read 5, iclass 34, count 0 2006.190.07:40:09.70#ibcon#about to read 6, iclass 34, count 0 2006.190.07:40:09.70#ibcon#read 6, iclass 34, count 0 2006.190.07:40:09.70#ibcon#end of sib2, iclass 34, count 0 2006.190.07:40:09.70#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:40:09.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:40:09.70#ibcon#[25=USB\r\n] 2006.190.07:40:09.70#ibcon#*before write, iclass 34, count 0 2006.190.07:40:09.70#ibcon#enter sib2, iclass 34, count 0 2006.190.07:40:09.70#ibcon#flushed, iclass 34, count 0 2006.190.07:40:09.70#ibcon#about to write, iclass 34, count 0 2006.190.07:40:09.70#ibcon#wrote, iclass 34, count 0 2006.190.07:40:09.70#ibcon#about to read 3, iclass 34, count 0 2006.190.07:40:09.73#ibcon#read 3, iclass 34, count 0 2006.190.07:40:09.73#ibcon#about to read 4, iclass 34, count 0 2006.190.07:40:09.73#ibcon#read 4, iclass 34, count 0 2006.190.07:40:09.73#ibcon#about to read 5, iclass 34, count 0 2006.190.07:40:09.73#ibcon#read 5, iclass 34, count 0 2006.190.07:40:09.73#ibcon#about to read 6, iclass 34, count 0 2006.190.07:40:09.73#ibcon#read 6, iclass 34, count 0 2006.190.07:40:09.73#ibcon#end of sib2, iclass 34, count 0 2006.190.07:40:09.73#ibcon#*after write, iclass 34, count 0 2006.190.07:40:09.73#ibcon#*before return 0, iclass 34, count 0 2006.190.07:40:09.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:09.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:09.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:40:09.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:40:09.73$vc4f8/valo=6,772.99 2006.190.07:40:09.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:40:09.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:40:09.73#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:09.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:09.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:09.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:09.73#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:40:09.73#ibcon#first serial, iclass 36, count 0 2006.190.07:40:09.73#ibcon#enter sib2, iclass 36, count 0 2006.190.07:40:09.73#ibcon#flushed, iclass 36, count 0 2006.190.07:40:09.73#ibcon#about to write, iclass 36, count 0 2006.190.07:40:09.73#ibcon#wrote, iclass 36, count 0 2006.190.07:40:09.73#ibcon#about to read 3, iclass 36, count 0 2006.190.07:40:09.75#ibcon#read 3, iclass 36, count 0 2006.190.07:40:09.75#ibcon#about to read 4, iclass 36, count 0 2006.190.07:40:09.75#ibcon#read 4, iclass 36, count 0 2006.190.07:40:09.75#ibcon#about to read 5, iclass 36, count 0 2006.190.07:40:09.75#ibcon#read 5, iclass 36, count 0 2006.190.07:40:09.75#ibcon#about to read 6, iclass 36, count 0 2006.190.07:40:09.75#ibcon#read 6, iclass 36, count 0 2006.190.07:40:09.75#ibcon#end of sib2, iclass 36, count 0 2006.190.07:40:09.75#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:40:09.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:40:09.75#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:40:09.75#ibcon#*before write, iclass 36, count 0 2006.190.07:40:09.75#ibcon#enter sib2, iclass 36, count 0 2006.190.07:40:09.75#ibcon#flushed, iclass 36, count 0 2006.190.07:40:09.75#ibcon#about to write, iclass 36, count 0 2006.190.07:40:09.75#ibcon#wrote, iclass 36, count 0 2006.190.07:40:09.75#ibcon#about to read 3, iclass 36, count 0 2006.190.07:40:09.79#ibcon#read 3, iclass 36, count 0 2006.190.07:40:09.79#ibcon#about to read 4, iclass 36, count 0 2006.190.07:40:09.79#ibcon#read 4, iclass 36, count 0 2006.190.07:40:09.79#ibcon#about to read 5, iclass 36, count 0 2006.190.07:40:09.79#ibcon#read 5, iclass 36, count 0 2006.190.07:40:09.79#ibcon#about to read 6, iclass 36, count 0 2006.190.07:40:09.79#ibcon#read 6, iclass 36, count 0 2006.190.07:40:09.79#ibcon#end of sib2, iclass 36, count 0 2006.190.07:40:09.79#ibcon#*after write, iclass 36, count 0 2006.190.07:40:09.79#ibcon#*before return 0, iclass 36, count 0 2006.190.07:40:09.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:09.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:09.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:40:09.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:40:09.79$vc4f8/va=6,6 2006.190.07:40:09.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.07:40:09.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.07:40:09.79#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:09.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:40:09.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:40:09.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:40:09.85#ibcon#enter wrdev, iclass 38, count 2 2006.190.07:40:09.85#ibcon#first serial, iclass 38, count 2 2006.190.07:40:09.85#ibcon#enter sib2, iclass 38, count 2 2006.190.07:40:09.85#ibcon#flushed, iclass 38, count 2 2006.190.07:40:09.85#ibcon#about to write, iclass 38, count 2 2006.190.07:40:09.85#ibcon#wrote, iclass 38, count 2 2006.190.07:40:09.85#ibcon#about to read 3, iclass 38, count 2 2006.190.07:40:09.87#ibcon#read 3, iclass 38, count 2 2006.190.07:40:09.87#ibcon#about to read 4, iclass 38, count 2 2006.190.07:40:09.87#ibcon#read 4, iclass 38, count 2 2006.190.07:40:09.87#ibcon#about to read 5, iclass 38, count 2 2006.190.07:40:09.87#ibcon#read 5, iclass 38, count 2 2006.190.07:40:09.87#ibcon#about to read 6, iclass 38, count 2 2006.190.07:40:09.87#ibcon#read 6, iclass 38, count 2 2006.190.07:40:09.87#ibcon#end of sib2, iclass 38, count 2 2006.190.07:40:09.87#ibcon#*mode == 0, iclass 38, count 2 2006.190.07:40:09.87#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.07:40:09.87#ibcon#[25=AT06-06\r\n] 2006.190.07:40:09.87#ibcon#*before write, iclass 38, count 2 2006.190.07:40:09.87#ibcon#enter sib2, iclass 38, count 2 2006.190.07:40:09.87#ibcon#flushed, iclass 38, count 2 2006.190.07:40:09.87#ibcon#about to write, iclass 38, count 2 2006.190.07:40:09.87#ibcon#wrote, iclass 38, count 2 2006.190.07:40:09.87#ibcon#about to read 3, iclass 38, count 2 2006.190.07:40:09.90#ibcon#read 3, iclass 38, count 2 2006.190.07:40:09.90#ibcon#about to read 4, iclass 38, count 2 2006.190.07:40:09.90#ibcon#read 4, iclass 38, count 2 2006.190.07:40:09.90#ibcon#about to read 5, iclass 38, count 2 2006.190.07:40:09.90#ibcon#read 5, iclass 38, count 2 2006.190.07:40:09.90#ibcon#about to read 6, iclass 38, count 2 2006.190.07:40:09.90#ibcon#read 6, iclass 38, count 2 2006.190.07:40:09.90#ibcon#end of sib2, iclass 38, count 2 2006.190.07:40:09.90#ibcon#*after write, iclass 38, count 2 2006.190.07:40:09.90#ibcon#*before return 0, iclass 38, count 2 2006.190.07:40:09.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:40:09.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:40:09.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.07:40:09.90#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:09.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:40:10.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:40:10.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:40:10.02#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:40:10.02#ibcon#first serial, iclass 38, count 0 2006.190.07:40:10.02#ibcon#enter sib2, iclass 38, count 0 2006.190.07:40:10.02#ibcon#flushed, iclass 38, count 0 2006.190.07:40:10.02#ibcon#about to write, iclass 38, count 0 2006.190.07:40:10.02#ibcon#wrote, iclass 38, count 0 2006.190.07:40:10.02#ibcon#about to read 3, iclass 38, count 0 2006.190.07:40:10.04#ibcon#read 3, iclass 38, count 0 2006.190.07:40:10.04#ibcon#about to read 4, iclass 38, count 0 2006.190.07:40:10.04#ibcon#read 4, iclass 38, count 0 2006.190.07:40:10.04#ibcon#about to read 5, iclass 38, count 0 2006.190.07:40:10.04#ibcon#read 5, iclass 38, count 0 2006.190.07:40:10.04#ibcon#about to read 6, iclass 38, count 0 2006.190.07:40:10.04#ibcon#read 6, iclass 38, count 0 2006.190.07:40:10.04#ibcon#end of sib2, iclass 38, count 0 2006.190.07:40:10.04#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:40:10.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:40:10.04#ibcon#[25=USB\r\n] 2006.190.07:40:10.04#ibcon#*before write, iclass 38, count 0 2006.190.07:40:10.04#ibcon#enter sib2, iclass 38, count 0 2006.190.07:40:10.04#ibcon#flushed, iclass 38, count 0 2006.190.07:40:10.04#ibcon#about to write, iclass 38, count 0 2006.190.07:40:10.04#ibcon#wrote, iclass 38, count 0 2006.190.07:40:10.04#ibcon#about to read 3, iclass 38, count 0 2006.190.07:40:10.07#ibcon#read 3, iclass 38, count 0 2006.190.07:40:10.07#ibcon#about to read 4, iclass 38, count 0 2006.190.07:40:10.07#ibcon#read 4, iclass 38, count 0 2006.190.07:40:10.07#ibcon#about to read 5, iclass 38, count 0 2006.190.07:40:10.07#ibcon#read 5, iclass 38, count 0 2006.190.07:40:10.07#ibcon#about to read 6, iclass 38, count 0 2006.190.07:40:10.07#ibcon#read 6, iclass 38, count 0 2006.190.07:40:10.07#ibcon#end of sib2, iclass 38, count 0 2006.190.07:40:10.07#ibcon#*after write, iclass 38, count 0 2006.190.07:40:10.07#ibcon#*before return 0, iclass 38, count 0 2006.190.07:40:10.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:40:10.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:40:10.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:40:10.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:40:10.07$vc4f8/valo=7,832.99 2006.190.07:40:10.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:40:10.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:40:10.07#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:10.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:40:10.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:40:10.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:40:10.07#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:40:10.07#ibcon#first serial, iclass 40, count 0 2006.190.07:40:10.07#ibcon#enter sib2, iclass 40, count 0 2006.190.07:40:10.07#ibcon#flushed, iclass 40, count 0 2006.190.07:40:10.07#ibcon#about to write, iclass 40, count 0 2006.190.07:40:10.07#ibcon#wrote, iclass 40, count 0 2006.190.07:40:10.07#ibcon#about to read 3, iclass 40, count 0 2006.190.07:40:10.09#ibcon#read 3, iclass 40, count 0 2006.190.07:40:10.09#ibcon#about to read 4, iclass 40, count 0 2006.190.07:40:10.09#ibcon#read 4, iclass 40, count 0 2006.190.07:40:10.09#ibcon#about to read 5, iclass 40, count 0 2006.190.07:40:10.09#ibcon#read 5, iclass 40, count 0 2006.190.07:40:10.09#ibcon#about to read 6, iclass 40, count 0 2006.190.07:40:10.09#ibcon#read 6, iclass 40, count 0 2006.190.07:40:10.09#ibcon#end of sib2, iclass 40, count 0 2006.190.07:40:10.09#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:40:10.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:40:10.09#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:40:10.09#ibcon#*before write, iclass 40, count 0 2006.190.07:40:10.09#ibcon#enter sib2, iclass 40, count 0 2006.190.07:40:10.09#ibcon#flushed, iclass 40, count 0 2006.190.07:40:10.09#ibcon#about to write, iclass 40, count 0 2006.190.07:40:10.09#ibcon#wrote, iclass 40, count 0 2006.190.07:40:10.09#ibcon#about to read 3, iclass 40, count 0 2006.190.07:40:10.13#ibcon#read 3, iclass 40, count 0 2006.190.07:40:10.13#ibcon#about to read 4, iclass 40, count 0 2006.190.07:40:10.13#ibcon#read 4, iclass 40, count 0 2006.190.07:40:10.13#ibcon#about to read 5, iclass 40, count 0 2006.190.07:40:10.13#ibcon#read 5, iclass 40, count 0 2006.190.07:40:10.13#ibcon#about to read 6, iclass 40, count 0 2006.190.07:40:10.13#ibcon#read 6, iclass 40, count 0 2006.190.07:40:10.13#ibcon#end of sib2, iclass 40, count 0 2006.190.07:40:10.13#ibcon#*after write, iclass 40, count 0 2006.190.07:40:10.13#ibcon#*before return 0, iclass 40, count 0 2006.190.07:40:10.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:40:10.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:40:10.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:40:10.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:40:10.13$vc4f8/va=7,6 2006.190.07:40:10.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:40:10.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:40:10.13#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:10.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:40:10.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:40:10.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:40:10.19#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:40:10.19#ibcon#first serial, iclass 4, count 2 2006.190.07:40:10.19#ibcon#enter sib2, iclass 4, count 2 2006.190.07:40:10.19#ibcon#flushed, iclass 4, count 2 2006.190.07:40:10.19#ibcon#about to write, iclass 4, count 2 2006.190.07:40:10.19#ibcon#wrote, iclass 4, count 2 2006.190.07:40:10.19#ibcon#about to read 3, iclass 4, count 2 2006.190.07:40:10.21#ibcon#read 3, iclass 4, count 2 2006.190.07:40:10.21#ibcon#about to read 4, iclass 4, count 2 2006.190.07:40:10.21#ibcon#read 4, iclass 4, count 2 2006.190.07:40:10.21#ibcon#about to read 5, iclass 4, count 2 2006.190.07:40:10.21#ibcon#read 5, iclass 4, count 2 2006.190.07:40:10.21#ibcon#about to read 6, iclass 4, count 2 2006.190.07:40:10.21#ibcon#read 6, iclass 4, count 2 2006.190.07:40:10.21#ibcon#end of sib2, iclass 4, count 2 2006.190.07:40:10.21#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:40:10.21#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:40:10.21#ibcon#[25=AT07-06\r\n] 2006.190.07:40:10.21#ibcon#*before write, iclass 4, count 2 2006.190.07:40:10.21#ibcon#enter sib2, iclass 4, count 2 2006.190.07:40:10.21#ibcon#flushed, iclass 4, count 2 2006.190.07:40:10.21#ibcon#about to write, iclass 4, count 2 2006.190.07:40:10.21#ibcon#wrote, iclass 4, count 2 2006.190.07:40:10.21#ibcon#about to read 3, iclass 4, count 2 2006.190.07:40:10.24#ibcon#read 3, iclass 4, count 2 2006.190.07:40:10.24#ibcon#about to read 4, iclass 4, count 2 2006.190.07:40:10.24#ibcon#read 4, iclass 4, count 2 2006.190.07:40:10.24#ibcon#about to read 5, iclass 4, count 2 2006.190.07:40:10.24#ibcon#read 5, iclass 4, count 2 2006.190.07:40:10.24#ibcon#about to read 6, iclass 4, count 2 2006.190.07:40:10.24#ibcon#read 6, iclass 4, count 2 2006.190.07:40:10.24#ibcon#end of sib2, iclass 4, count 2 2006.190.07:40:10.24#ibcon#*after write, iclass 4, count 2 2006.190.07:40:10.24#ibcon#*before return 0, iclass 4, count 2 2006.190.07:40:10.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:40:10.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:40:10.24#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:40:10.24#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:10.24#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:40:10.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:40:10.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:40:10.36#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:40:10.36#ibcon#first serial, iclass 4, count 0 2006.190.07:40:10.36#ibcon#enter sib2, iclass 4, count 0 2006.190.07:40:10.36#ibcon#flushed, iclass 4, count 0 2006.190.07:40:10.36#ibcon#about to write, iclass 4, count 0 2006.190.07:40:10.36#ibcon#wrote, iclass 4, count 0 2006.190.07:40:10.36#ibcon#about to read 3, iclass 4, count 0 2006.190.07:40:10.38#ibcon#read 3, iclass 4, count 0 2006.190.07:40:10.38#ibcon#about to read 4, iclass 4, count 0 2006.190.07:40:10.38#ibcon#read 4, iclass 4, count 0 2006.190.07:40:10.38#ibcon#about to read 5, iclass 4, count 0 2006.190.07:40:10.38#ibcon#read 5, iclass 4, count 0 2006.190.07:40:10.38#ibcon#about to read 6, iclass 4, count 0 2006.190.07:40:10.38#ibcon#read 6, iclass 4, count 0 2006.190.07:40:10.38#ibcon#end of sib2, iclass 4, count 0 2006.190.07:40:10.38#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:40:10.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:40:10.38#ibcon#[25=USB\r\n] 2006.190.07:40:10.38#ibcon#*before write, iclass 4, count 0 2006.190.07:40:10.38#ibcon#enter sib2, iclass 4, count 0 2006.190.07:40:10.38#ibcon#flushed, iclass 4, count 0 2006.190.07:40:10.38#ibcon#about to write, iclass 4, count 0 2006.190.07:40:10.38#ibcon#wrote, iclass 4, count 0 2006.190.07:40:10.38#ibcon#about to read 3, iclass 4, count 0 2006.190.07:40:10.41#ibcon#read 3, iclass 4, count 0 2006.190.07:40:10.41#ibcon#about to read 4, iclass 4, count 0 2006.190.07:40:10.41#ibcon#read 4, iclass 4, count 0 2006.190.07:40:10.41#ibcon#about to read 5, iclass 4, count 0 2006.190.07:40:10.41#ibcon#read 5, iclass 4, count 0 2006.190.07:40:10.41#ibcon#about to read 6, iclass 4, count 0 2006.190.07:40:10.41#ibcon#read 6, iclass 4, count 0 2006.190.07:40:10.41#ibcon#end of sib2, iclass 4, count 0 2006.190.07:40:10.41#ibcon#*after write, iclass 4, count 0 2006.190.07:40:10.41#ibcon#*before return 0, iclass 4, count 0 2006.190.07:40:10.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:40:10.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:40:10.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:40:10.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:40:10.41$vc4f8/valo=8,852.99 2006.190.07:40:10.41#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:40:10.41#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:40:10.41#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:10.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:40:10.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:40:10.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:40:10.41#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:40:10.41#ibcon#first serial, iclass 6, count 0 2006.190.07:40:10.41#ibcon#enter sib2, iclass 6, count 0 2006.190.07:40:10.41#ibcon#flushed, iclass 6, count 0 2006.190.07:40:10.41#ibcon#about to write, iclass 6, count 0 2006.190.07:40:10.41#ibcon#wrote, iclass 6, count 0 2006.190.07:40:10.41#ibcon#about to read 3, iclass 6, count 0 2006.190.07:40:10.43#ibcon#read 3, iclass 6, count 0 2006.190.07:40:10.43#ibcon#about to read 4, iclass 6, count 0 2006.190.07:40:10.43#ibcon#read 4, iclass 6, count 0 2006.190.07:40:10.43#ibcon#about to read 5, iclass 6, count 0 2006.190.07:40:10.43#ibcon#read 5, iclass 6, count 0 2006.190.07:40:10.43#ibcon#about to read 6, iclass 6, count 0 2006.190.07:40:10.43#ibcon#read 6, iclass 6, count 0 2006.190.07:40:10.43#ibcon#end of sib2, iclass 6, count 0 2006.190.07:40:10.43#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:40:10.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:40:10.43#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:40:10.43#ibcon#*before write, iclass 6, count 0 2006.190.07:40:10.43#ibcon#enter sib2, iclass 6, count 0 2006.190.07:40:10.43#ibcon#flushed, iclass 6, count 0 2006.190.07:40:10.43#ibcon#about to write, iclass 6, count 0 2006.190.07:40:10.43#ibcon#wrote, iclass 6, count 0 2006.190.07:40:10.43#ibcon#about to read 3, iclass 6, count 0 2006.190.07:40:10.47#ibcon#read 3, iclass 6, count 0 2006.190.07:40:10.47#ibcon#about to read 4, iclass 6, count 0 2006.190.07:40:10.47#ibcon#read 4, iclass 6, count 0 2006.190.07:40:10.47#ibcon#about to read 5, iclass 6, count 0 2006.190.07:40:10.47#ibcon#read 5, iclass 6, count 0 2006.190.07:40:10.47#ibcon#about to read 6, iclass 6, count 0 2006.190.07:40:10.47#ibcon#read 6, iclass 6, count 0 2006.190.07:40:10.47#ibcon#end of sib2, iclass 6, count 0 2006.190.07:40:10.47#ibcon#*after write, iclass 6, count 0 2006.190.07:40:10.47#ibcon#*before return 0, iclass 6, count 0 2006.190.07:40:10.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:40:10.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:40:10.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:40:10.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:40:10.47$vc4f8/va=8,6 2006.190.07:40:10.47#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:40:10.47#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:40:10.47#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:10.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:40:10.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:40:10.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:40:10.53#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:40:10.53#ibcon#first serial, iclass 10, count 2 2006.190.07:40:10.53#ibcon#enter sib2, iclass 10, count 2 2006.190.07:40:10.53#ibcon#flushed, iclass 10, count 2 2006.190.07:40:10.53#ibcon#about to write, iclass 10, count 2 2006.190.07:40:10.53#ibcon#wrote, iclass 10, count 2 2006.190.07:40:10.53#ibcon#about to read 3, iclass 10, count 2 2006.190.07:40:10.55#ibcon#read 3, iclass 10, count 2 2006.190.07:40:10.55#ibcon#about to read 4, iclass 10, count 2 2006.190.07:40:10.55#ibcon#read 4, iclass 10, count 2 2006.190.07:40:10.55#ibcon#about to read 5, iclass 10, count 2 2006.190.07:40:10.55#ibcon#read 5, iclass 10, count 2 2006.190.07:40:10.55#ibcon#about to read 6, iclass 10, count 2 2006.190.07:40:10.55#ibcon#read 6, iclass 10, count 2 2006.190.07:40:10.55#ibcon#end of sib2, iclass 10, count 2 2006.190.07:40:10.55#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:40:10.55#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:40:10.55#ibcon#[25=AT08-06\r\n] 2006.190.07:40:10.55#ibcon#*before write, iclass 10, count 2 2006.190.07:40:10.55#ibcon#enter sib2, iclass 10, count 2 2006.190.07:40:10.55#ibcon#flushed, iclass 10, count 2 2006.190.07:40:10.55#ibcon#about to write, iclass 10, count 2 2006.190.07:40:10.55#ibcon#wrote, iclass 10, count 2 2006.190.07:40:10.55#ibcon#about to read 3, iclass 10, count 2 2006.190.07:40:10.58#ibcon#read 3, iclass 10, count 2 2006.190.07:40:10.58#ibcon#about to read 4, iclass 10, count 2 2006.190.07:40:10.58#ibcon#read 4, iclass 10, count 2 2006.190.07:40:10.58#ibcon#about to read 5, iclass 10, count 2 2006.190.07:40:10.58#ibcon#read 5, iclass 10, count 2 2006.190.07:40:10.58#ibcon#about to read 6, iclass 10, count 2 2006.190.07:40:10.58#ibcon#read 6, iclass 10, count 2 2006.190.07:40:10.58#ibcon#end of sib2, iclass 10, count 2 2006.190.07:40:10.58#ibcon#*after write, iclass 10, count 2 2006.190.07:40:10.58#ibcon#*before return 0, iclass 10, count 2 2006.190.07:40:10.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:40:10.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:40:10.58#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:40:10.58#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:10.58#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:40:10.70#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:40:10.70#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:40:10.70#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:40:10.70#ibcon#first serial, iclass 10, count 0 2006.190.07:40:10.70#ibcon#enter sib2, iclass 10, count 0 2006.190.07:40:10.70#ibcon#flushed, iclass 10, count 0 2006.190.07:40:10.70#ibcon#about to write, iclass 10, count 0 2006.190.07:40:10.70#ibcon#wrote, iclass 10, count 0 2006.190.07:40:10.70#ibcon#about to read 3, iclass 10, count 0 2006.190.07:40:10.72#ibcon#read 3, iclass 10, count 0 2006.190.07:40:10.72#ibcon#about to read 4, iclass 10, count 0 2006.190.07:40:10.72#ibcon#read 4, iclass 10, count 0 2006.190.07:40:10.72#ibcon#about to read 5, iclass 10, count 0 2006.190.07:40:10.72#ibcon#read 5, iclass 10, count 0 2006.190.07:40:10.72#ibcon#about to read 6, iclass 10, count 0 2006.190.07:40:10.72#ibcon#read 6, iclass 10, count 0 2006.190.07:40:10.72#ibcon#end of sib2, iclass 10, count 0 2006.190.07:40:10.72#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:40:10.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:40:10.72#ibcon#[25=USB\r\n] 2006.190.07:40:10.72#ibcon#*before write, iclass 10, count 0 2006.190.07:40:10.72#ibcon#enter sib2, iclass 10, count 0 2006.190.07:40:10.72#ibcon#flushed, iclass 10, count 0 2006.190.07:40:10.72#ibcon#about to write, iclass 10, count 0 2006.190.07:40:10.72#ibcon#wrote, iclass 10, count 0 2006.190.07:40:10.72#ibcon#about to read 3, iclass 10, count 0 2006.190.07:40:10.75#ibcon#read 3, iclass 10, count 0 2006.190.07:40:10.75#ibcon#about to read 4, iclass 10, count 0 2006.190.07:40:10.75#ibcon#read 4, iclass 10, count 0 2006.190.07:40:10.75#ibcon#about to read 5, iclass 10, count 0 2006.190.07:40:10.75#ibcon#read 5, iclass 10, count 0 2006.190.07:40:10.75#ibcon#about to read 6, iclass 10, count 0 2006.190.07:40:10.75#ibcon#read 6, iclass 10, count 0 2006.190.07:40:10.75#ibcon#end of sib2, iclass 10, count 0 2006.190.07:40:10.75#ibcon#*after write, iclass 10, count 0 2006.190.07:40:10.75#ibcon#*before return 0, iclass 10, count 0 2006.190.07:40:10.75#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:40:10.75#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:40:10.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:40:10.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:40:10.75$vc4f8/vblo=1,632.99 2006.190.07:40:10.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:40:10.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:40:10.75#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:10.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:40:10.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:40:10.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:40:10.75#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:40:10.75#ibcon#first serial, iclass 12, count 0 2006.190.07:40:10.75#ibcon#enter sib2, iclass 12, count 0 2006.190.07:40:10.75#ibcon#flushed, iclass 12, count 0 2006.190.07:40:10.75#ibcon#about to write, iclass 12, count 0 2006.190.07:40:10.75#ibcon#wrote, iclass 12, count 0 2006.190.07:40:10.75#ibcon#about to read 3, iclass 12, count 0 2006.190.07:40:10.77#ibcon#read 3, iclass 12, count 0 2006.190.07:40:10.77#ibcon#about to read 4, iclass 12, count 0 2006.190.07:40:10.77#ibcon#read 4, iclass 12, count 0 2006.190.07:40:10.77#ibcon#about to read 5, iclass 12, count 0 2006.190.07:40:10.77#ibcon#read 5, iclass 12, count 0 2006.190.07:40:10.77#ibcon#about to read 6, iclass 12, count 0 2006.190.07:40:10.77#ibcon#read 6, iclass 12, count 0 2006.190.07:40:10.77#ibcon#end of sib2, iclass 12, count 0 2006.190.07:40:10.77#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:40:10.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:40:10.77#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:40:10.77#ibcon#*before write, iclass 12, count 0 2006.190.07:40:10.77#ibcon#enter sib2, iclass 12, count 0 2006.190.07:40:10.77#ibcon#flushed, iclass 12, count 0 2006.190.07:40:10.77#ibcon#about to write, iclass 12, count 0 2006.190.07:40:10.77#ibcon#wrote, iclass 12, count 0 2006.190.07:40:10.77#ibcon#about to read 3, iclass 12, count 0 2006.190.07:40:10.81#ibcon#read 3, iclass 12, count 0 2006.190.07:40:10.81#ibcon#about to read 4, iclass 12, count 0 2006.190.07:40:10.81#ibcon#read 4, iclass 12, count 0 2006.190.07:40:10.81#ibcon#about to read 5, iclass 12, count 0 2006.190.07:40:10.81#ibcon#read 5, iclass 12, count 0 2006.190.07:40:10.81#ibcon#about to read 6, iclass 12, count 0 2006.190.07:40:10.81#ibcon#read 6, iclass 12, count 0 2006.190.07:40:10.81#ibcon#end of sib2, iclass 12, count 0 2006.190.07:40:10.81#ibcon#*after write, iclass 12, count 0 2006.190.07:40:10.81#ibcon#*before return 0, iclass 12, count 0 2006.190.07:40:10.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:40:10.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:40:10.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:40:10.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:40:10.81$vc4f8/vb=1,4 2006.190.07:40:10.81#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:40:10.81#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:40:10.81#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:10.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:40:10.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:40:10.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:40:10.81#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:40:10.81#ibcon#first serial, iclass 14, count 2 2006.190.07:40:10.81#ibcon#enter sib2, iclass 14, count 2 2006.190.07:40:10.81#ibcon#flushed, iclass 14, count 2 2006.190.07:40:10.81#ibcon#about to write, iclass 14, count 2 2006.190.07:40:10.81#ibcon#wrote, iclass 14, count 2 2006.190.07:40:10.81#ibcon#about to read 3, iclass 14, count 2 2006.190.07:40:10.83#ibcon#read 3, iclass 14, count 2 2006.190.07:40:10.83#ibcon#about to read 4, iclass 14, count 2 2006.190.07:40:10.83#ibcon#read 4, iclass 14, count 2 2006.190.07:40:10.83#ibcon#about to read 5, iclass 14, count 2 2006.190.07:40:10.83#ibcon#read 5, iclass 14, count 2 2006.190.07:40:10.83#ibcon#about to read 6, iclass 14, count 2 2006.190.07:40:10.83#ibcon#read 6, iclass 14, count 2 2006.190.07:40:10.83#ibcon#end of sib2, iclass 14, count 2 2006.190.07:40:10.83#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:40:10.83#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:40:10.83#ibcon#[27=AT01-04\r\n] 2006.190.07:40:10.83#ibcon#*before write, iclass 14, count 2 2006.190.07:40:10.83#ibcon#enter sib2, iclass 14, count 2 2006.190.07:40:10.83#ibcon#flushed, iclass 14, count 2 2006.190.07:40:10.83#ibcon#about to write, iclass 14, count 2 2006.190.07:40:10.83#ibcon#wrote, iclass 14, count 2 2006.190.07:40:10.83#ibcon#about to read 3, iclass 14, count 2 2006.190.07:40:10.86#ibcon#read 3, iclass 14, count 2 2006.190.07:40:10.86#ibcon#about to read 4, iclass 14, count 2 2006.190.07:40:10.86#ibcon#read 4, iclass 14, count 2 2006.190.07:40:10.86#ibcon#about to read 5, iclass 14, count 2 2006.190.07:40:10.86#ibcon#read 5, iclass 14, count 2 2006.190.07:40:10.86#ibcon#about to read 6, iclass 14, count 2 2006.190.07:40:10.86#ibcon#read 6, iclass 14, count 2 2006.190.07:40:10.86#ibcon#end of sib2, iclass 14, count 2 2006.190.07:40:10.86#ibcon#*after write, iclass 14, count 2 2006.190.07:40:10.86#ibcon#*before return 0, iclass 14, count 2 2006.190.07:40:10.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:40:10.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:40:10.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:40:10.86#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:10.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:40:10.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:40:10.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:40:10.98#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:40:10.98#ibcon#first serial, iclass 14, count 0 2006.190.07:40:10.98#ibcon#enter sib2, iclass 14, count 0 2006.190.07:40:10.98#ibcon#flushed, iclass 14, count 0 2006.190.07:40:10.98#ibcon#about to write, iclass 14, count 0 2006.190.07:40:10.98#ibcon#wrote, iclass 14, count 0 2006.190.07:40:10.98#ibcon#about to read 3, iclass 14, count 0 2006.190.07:40:11.00#ibcon#read 3, iclass 14, count 0 2006.190.07:40:11.00#ibcon#about to read 4, iclass 14, count 0 2006.190.07:40:11.00#ibcon#read 4, iclass 14, count 0 2006.190.07:40:11.00#ibcon#about to read 5, iclass 14, count 0 2006.190.07:40:11.00#ibcon#read 5, iclass 14, count 0 2006.190.07:40:11.00#ibcon#about to read 6, iclass 14, count 0 2006.190.07:40:11.00#ibcon#read 6, iclass 14, count 0 2006.190.07:40:11.00#ibcon#end of sib2, iclass 14, count 0 2006.190.07:40:11.00#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:40:11.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:40:11.00#ibcon#[27=USB\r\n] 2006.190.07:40:11.00#ibcon#*before write, iclass 14, count 0 2006.190.07:40:11.00#ibcon#enter sib2, iclass 14, count 0 2006.190.07:40:11.00#ibcon#flushed, iclass 14, count 0 2006.190.07:40:11.00#ibcon#about to write, iclass 14, count 0 2006.190.07:40:11.00#ibcon#wrote, iclass 14, count 0 2006.190.07:40:11.00#ibcon#about to read 3, iclass 14, count 0 2006.190.07:40:11.03#ibcon#read 3, iclass 14, count 0 2006.190.07:40:11.03#ibcon#about to read 4, iclass 14, count 0 2006.190.07:40:11.03#ibcon#read 4, iclass 14, count 0 2006.190.07:40:11.03#ibcon#about to read 5, iclass 14, count 0 2006.190.07:40:11.03#ibcon#read 5, iclass 14, count 0 2006.190.07:40:11.03#ibcon#about to read 6, iclass 14, count 0 2006.190.07:40:11.03#ibcon#read 6, iclass 14, count 0 2006.190.07:40:11.03#ibcon#end of sib2, iclass 14, count 0 2006.190.07:40:11.03#ibcon#*after write, iclass 14, count 0 2006.190.07:40:11.03#ibcon#*before return 0, iclass 14, count 0 2006.190.07:40:11.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:40:11.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:40:11.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:40:11.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:40:11.03$vc4f8/vblo=2,640.99 2006.190.07:40:11.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:40:11.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:40:11.03#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:11.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:11.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:11.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:11.03#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:40:11.03#ibcon#first serial, iclass 16, count 0 2006.190.07:40:11.03#ibcon#enter sib2, iclass 16, count 0 2006.190.07:40:11.03#ibcon#flushed, iclass 16, count 0 2006.190.07:40:11.03#ibcon#about to write, iclass 16, count 0 2006.190.07:40:11.03#ibcon#wrote, iclass 16, count 0 2006.190.07:40:11.03#ibcon#about to read 3, iclass 16, count 0 2006.190.07:40:11.05#ibcon#read 3, iclass 16, count 0 2006.190.07:40:11.05#ibcon#about to read 4, iclass 16, count 0 2006.190.07:40:11.05#ibcon#read 4, iclass 16, count 0 2006.190.07:40:11.05#ibcon#about to read 5, iclass 16, count 0 2006.190.07:40:11.05#ibcon#read 5, iclass 16, count 0 2006.190.07:40:11.05#ibcon#about to read 6, iclass 16, count 0 2006.190.07:40:11.05#ibcon#read 6, iclass 16, count 0 2006.190.07:40:11.05#ibcon#end of sib2, iclass 16, count 0 2006.190.07:40:11.05#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:40:11.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:40:11.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:40:11.05#ibcon#*before write, iclass 16, count 0 2006.190.07:40:11.05#ibcon#enter sib2, iclass 16, count 0 2006.190.07:40:11.05#ibcon#flushed, iclass 16, count 0 2006.190.07:40:11.05#ibcon#about to write, iclass 16, count 0 2006.190.07:40:11.05#ibcon#wrote, iclass 16, count 0 2006.190.07:40:11.05#ibcon#about to read 3, iclass 16, count 0 2006.190.07:40:11.09#ibcon#read 3, iclass 16, count 0 2006.190.07:40:11.09#ibcon#about to read 4, iclass 16, count 0 2006.190.07:40:11.09#ibcon#read 4, iclass 16, count 0 2006.190.07:40:11.09#ibcon#about to read 5, iclass 16, count 0 2006.190.07:40:11.09#ibcon#read 5, iclass 16, count 0 2006.190.07:40:11.09#ibcon#about to read 6, iclass 16, count 0 2006.190.07:40:11.09#ibcon#read 6, iclass 16, count 0 2006.190.07:40:11.09#ibcon#end of sib2, iclass 16, count 0 2006.190.07:40:11.09#ibcon#*after write, iclass 16, count 0 2006.190.07:40:11.09#ibcon#*before return 0, iclass 16, count 0 2006.190.07:40:11.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:11.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:40:11.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:40:11.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:40:11.09$vc4f8/vb=2,4 2006.190.07:40:11.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.07:40:11.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.07:40:11.09#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:11.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:11.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:11.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:11.15#ibcon#enter wrdev, iclass 18, count 2 2006.190.07:40:11.15#ibcon#first serial, iclass 18, count 2 2006.190.07:40:11.15#ibcon#enter sib2, iclass 18, count 2 2006.190.07:40:11.15#ibcon#flushed, iclass 18, count 2 2006.190.07:40:11.15#ibcon#about to write, iclass 18, count 2 2006.190.07:40:11.15#ibcon#wrote, iclass 18, count 2 2006.190.07:40:11.15#ibcon#about to read 3, iclass 18, count 2 2006.190.07:40:11.17#ibcon#read 3, iclass 18, count 2 2006.190.07:40:11.17#ibcon#about to read 4, iclass 18, count 2 2006.190.07:40:11.17#ibcon#read 4, iclass 18, count 2 2006.190.07:40:11.17#ibcon#about to read 5, iclass 18, count 2 2006.190.07:40:11.17#ibcon#read 5, iclass 18, count 2 2006.190.07:40:11.17#ibcon#about to read 6, iclass 18, count 2 2006.190.07:40:11.17#ibcon#read 6, iclass 18, count 2 2006.190.07:40:11.17#ibcon#end of sib2, iclass 18, count 2 2006.190.07:40:11.17#ibcon#*mode == 0, iclass 18, count 2 2006.190.07:40:11.17#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.07:40:11.17#ibcon#[27=AT02-04\r\n] 2006.190.07:40:11.17#ibcon#*before write, iclass 18, count 2 2006.190.07:40:11.17#ibcon#enter sib2, iclass 18, count 2 2006.190.07:40:11.17#ibcon#flushed, iclass 18, count 2 2006.190.07:40:11.17#ibcon#about to write, iclass 18, count 2 2006.190.07:40:11.17#ibcon#wrote, iclass 18, count 2 2006.190.07:40:11.17#ibcon#about to read 3, iclass 18, count 2 2006.190.07:40:11.20#ibcon#read 3, iclass 18, count 2 2006.190.07:40:11.20#ibcon#about to read 4, iclass 18, count 2 2006.190.07:40:11.20#ibcon#read 4, iclass 18, count 2 2006.190.07:40:11.20#ibcon#about to read 5, iclass 18, count 2 2006.190.07:40:11.20#ibcon#read 5, iclass 18, count 2 2006.190.07:40:11.20#ibcon#about to read 6, iclass 18, count 2 2006.190.07:40:11.20#ibcon#read 6, iclass 18, count 2 2006.190.07:40:11.20#ibcon#end of sib2, iclass 18, count 2 2006.190.07:40:11.20#ibcon#*after write, iclass 18, count 2 2006.190.07:40:11.20#ibcon#*before return 0, iclass 18, count 2 2006.190.07:40:11.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:11.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:40:11.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.07:40:11.20#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:11.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:11.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:11.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:11.32#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:40:11.32#ibcon#first serial, iclass 18, count 0 2006.190.07:40:11.32#ibcon#enter sib2, iclass 18, count 0 2006.190.07:40:11.32#ibcon#flushed, iclass 18, count 0 2006.190.07:40:11.32#ibcon#about to write, iclass 18, count 0 2006.190.07:40:11.32#ibcon#wrote, iclass 18, count 0 2006.190.07:40:11.32#ibcon#about to read 3, iclass 18, count 0 2006.190.07:40:11.34#ibcon#read 3, iclass 18, count 0 2006.190.07:40:11.34#ibcon#about to read 4, iclass 18, count 0 2006.190.07:40:11.34#ibcon#read 4, iclass 18, count 0 2006.190.07:40:11.34#ibcon#about to read 5, iclass 18, count 0 2006.190.07:40:11.34#ibcon#read 5, iclass 18, count 0 2006.190.07:40:11.34#ibcon#about to read 6, iclass 18, count 0 2006.190.07:40:11.34#ibcon#read 6, iclass 18, count 0 2006.190.07:40:11.34#ibcon#end of sib2, iclass 18, count 0 2006.190.07:40:11.34#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:40:11.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:40:11.34#ibcon#[27=USB\r\n] 2006.190.07:40:11.34#ibcon#*before write, iclass 18, count 0 2006.190.07:40:11.34#ibcon#enter sib2, iclass 18, count 0 2006.190.07:40:11.34#ibcon#flushed, iclass 18, count 0 2006.190.07:40:11.34#ibcon#about to write, iclass 18, count 0 2006.190.07:40:11.34#ibcon#wrote, iclass 18, count 0 2006.190.07:40:11.34#ibcon#about to read 3, iclass 18, count 0 2006.190.07:40:11.37#ibcon#read 3, iclass 18, count 0 2006.190.07:40:11.37#ibcon#about to read 4, iclass 18, count 0 2006.190.07:40:11.37#ibcon#read 4, iclass 18, count 0 2006.190.07:40:11.37#ibcon#about to read 5, iclass 18, count 0 2006.190.07:40:11.37#ibcon#read 5, iclass 18, count 0 2006.190.07:40:11.37#ibcon#about to read 6, iclass 18, count 0 2006.190.07:40:11.37#ibcon#read 6, iclass 18, count 0 2006.190.07:40:11.37#ibcon#end of sib2, iclass 18, count 0 2006.190.07:40:11.37#ibcon#*after write, iclass 18, count 0 2006.190.07:40:11.37#ibcon#*before return 0, iclass 18, count 0 2006.190.07:40:11.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:11.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:40:11.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:40:11.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:40:11.37$vc4f8/vblo=3,656.99 2006.190.07:40:11.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:40:11.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:40:11.37#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:11.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:11.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:11.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:11.37#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:40:11.37#ibcon#first serial, iclass 20, count 0 2006.190.07:40:11.37#ibcon#enter sib2, iclass 20, count 0 2006.190.07:40:11.37#ibcon#flushed, iclass 20, count 0 2006.190.07:40:11.37#ibcon#about to write, iclass 20, count 0 2006.190.07:40:11.37#ibcon#wrote, iclass 20, count 0 2006.190.07:40:11.37#ibcon#about to read 3, iclass 20, count 0 2006.190.07:40:11.39#ibcon#read 3, iclass 20, count 0 2006.190.07:40:11.39#ibcon#about to read 4, iclass 20, count 0 2006.190.07:40:11.39#ibcon#read 4, iclass 20, count 0 2006.190.07:40:11.39#ibcon#about to read 5, iclass 20, count 0 2006.190.07:40:11.39#ibcon#read 5, iclass 20, count 0 2006.190.07:40:11.39#ibcon#about to read 6, iclass 20, count 0 2006.190.07:40:11.39#ibcon#read 6, iclass 20, count 0 2006.190.07:40:11.39#ibcon#end of sib2, iclass 20, count 0 2006.190.07:40:11.39#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:40:11.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:40:11.39#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:40:11.39#ibcon#*before write, iclass 20, count 0 2006.190.07:40:11.39#ibcon#enter sib2, iclass 20, count 0 2006.190.07:40:11.39#ibcon#flushed, iclass 20, count 0 2006.190.07:40:11.39#ibcon#about to write, iclass 20, count 0 2006.190.07:40:11.39#ibcon#wrote, iclass 20, count 0 2006.190.07:40:11.39#ibcon#about to read 3, iclass 20, count 0 2006.190.07:40:11.43#ibcon#read 3, iclass 20, count 0 2006.190.07:40:11.43#ibcon#about to read 4, iclass 20, count 0 2006.190.07:40:11.43#ibcon#read 4, iclass 20, count 0 2006.190.07:40:11.43#ibcon#about to read 5, iclass 20, count 0 2006.190.07:40:11.43#ibcon#read 5, iclass 20, count 0 2006.190.07:40:11.43#ibcon#about to read 6, iclass 20, count 0 2006.190.07:40:11.43#ibcon#read 6, iclass 20, count 0 2006.190.07:40:11.43#ibcon#end of sib2, iclass 20, count 0 2006.190.07:40:11.43#ibcon#*after write, iclass 20, count 0 2006.190.07:40:11.43#ibcon#*before return 0, iclass 20, count 0 2006.190.07:40:11.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:11.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:40:11.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:40:11.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:40:11.43$vc4f8/vb=3,4 2006.190.07:40:11.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:40:11.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:40:11.43#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:11.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:11.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:11.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:11.49#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:40:11.49#ibcon#first serial, iclass 22, count 2 2006.190.07:40:11.49#ibcon#enter sib2, iclass 22, count 2 2006.190.07:40:11.49#ibcon#flushed, iclass 22, count 2 2006.190.07:40:11.49#ibcon#about to write, iclass 22, count 2 2006.190.07:40:11.49#ibcon#wrote, iclass 22, count 2 2006.190.07:40:11.49#ibcon#about to read 3, iclass 22, count 2 2006.190.07:40:11.51#ibcon#read 3, iclass 22, count 2 2006.190.07:40:11.51#ibcon#about to read 4, iclass 22, count 2 2006.190.07:40:11.51#ibcon#read 4, iclass 22, count 2 2006.190.07:40:11.51#ibcon#about to read 5, iclass 22, count 2 2006.190.07:40:11.51#ibcon#read 5, iclass 22, count 2 2006.190.07:40:11.51#ibcon#about to read 6, iclass 22, count 2 2006.190.07:40:11.51#ibcon#read 6, iclass 22, count 2 2006.190.07:40:11.51#ibcon#end of sib2, iclass 22, count 2 2006.190.07:40:11.51#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:40:11.51#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:40:11.51#ibcon#[27=AT03-04\r\n] 2006.190.07:40:11.51#ibcon#*before write, iclass 22, count 2 2006.190.07:40:11.51#ibcon#enter sib2, iclass 22, count 2 2006.190.07:40:11.51#ibcon#flushed, iclass 22, count 2 2006.190.07:40:11.51#ibcon#about to write, iclass 22, count 2 2006.190.07:40:11.51#ibcon#wrote, iclass 22, count 2 2006.190.07:40:11.51#ibcon#about to read 3, iclass 22, count 2 2006.190.07:40:11.54#ibcon#read 3, iclass 22, count 2 2006.190.07:40:11.54#ibcon#about to read 4, iclass 22, count 2 2006.190.07:40:11.54#ibcon#read 4, iclass 22, count 2 2006.190.07:40:11.54#ibcon#about to read 5, iclass 22, count 2 2006.190.07:40:11.54#ibcon#read 5, iclass 22, count 2 2006.190.07:40:11.54#ibcon#about to read 6, iclass 22, count 2 2006.190.07:40:11.54#ibcon#read 6, iclass 22, count 2 2006.190.07:40:11.54#ibcon#end of sib2, iclass 22, count 2 2006.190.07:40:11.54#ibcon#*after write, iclass 22, count 2 2006.190.07:40:11.54#ibcon#*before return 0, iclass 22, count 2 2006.190.07:40:11.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:11.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:40:11.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:40:11.54#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:11.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:11.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:11.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:11.66#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:40:11.66#ibcon#first serial, iclass 22, count 0 2006.190.07:40:11.66#ibcon#enter sib2, iclass 22, count 0 2006.190.07:40:11.66#ibcon#flushed, iclass 22, count 0 2006.190.07:40:11.66#ibcon#about to write, iclass 22, count 0 2006.190.07:40:11.66#ibcon#wrote, iclass 22, count 0 2006.190.07:40:11.66#ibcon#about to read 3, iclass 22, count 0 2006.190.07:40:11.68#ibcon#read 3, iclass 22, count 0 2006.190.07:40:11.68#ibcon#about to read 4, iclass 22, count 0 2006.190.07:40:11.68#ibcon#read 4, iclass 22, count 0 2006.190.07:40:11.68#ibcon#about to read 5, iclass 22, count 0 2006.190.07:40:11.68#ibcon#read 5, iclass 22, count 0 2006.190.07:40:11.68#ibcon#about to read 6, iclass 22, count 0 2006.190.07:40:11.68#ibcon#read 6, iclass 22, count 0 2006.190.07:40:11.68#ibcon#end of sib2, iclass 22, count 0 2006.190.07:40:11.68#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:40:11.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:40:11.68#ibcon#[27=USB\r\n] 2006.190.07:40:11.68#ibcon#*before write, iclass 22, count 0 2006.190.07:40:11.68#ibcon#enter sib2, iclass 22, count 0 2006.190.07:40:11.68#ibcon#flushed, iclass 22, count 0 2006.190.07:40:11.68#ibcon#about to write, iclass 22, count 0 2006.190.07:40:11.68#ibcon#wrote, iclass 22, count 0 2006.190.07:40:11.68#ibcon#about to read 3, iclass 22, count 0 2006.190.07:40:11.71#ibcon#read 3, iclass 22, count 0 2006.190.07:40:11.71#ibcon#about to read 4, iclass 22, count 0 2006.190.07:40:11.71#ibcon#read 4, iclass 22, count 0 2006.190.07:40:11.71#ibcon#about to read 5, iclass 22, count 0 2006.190.07:40:11.71#ibcon#read 5, iclass 22, count 0 2006.190.07:40:11.71#ibcon#about to read 6, iclass 22, count 0 2006.190.07:40:11.71#ibcon#read 6, iclass 22, count 0 2006.190.07:40:11.71#ibcon#end of sib2, iclass 22, count 0 2006.190.07:40:11.71#ibcon#*after write, iclass 22, count 0 2006.190.07:40:11.71#ibcon#*before return 0, iclass 22, count 0 2006.190.07:40:11.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:11.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:40:11.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:40:11.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:40:11.71$vc4f8/vblo=4,712.99 2006.190.07:40:11.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.07:40:11.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.07:40:11.71#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:11.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:11.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:11.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:11.71#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:40:11.71#ibcon#first serial, iclass 24, count 0 2006.190.07:40:11.71#ibcon#enter sib2, iclass 24, count 0 2006.190.07:40:11.71#ibcon#flushed, iclass 24, count 0 2006.190.07:40:11.71#ibcon#about to write, iclass 24, count 0 2006.190.07:40:11.71#ibcon#wrote, iclass 24, count 0 2006.190.07:40:11.71#ibcon#about to read 3, iclass 24, count 0 2006.190.07:40:11.73#ibcon#read 3, iclass 24, count 0 2006.190.07:40:11.73#ibcon#about to read 4, iclass 24, count 0 2006.190.07:40:11.73#ibcon#read 4, iclass 24, count 0 2006.190.07:40:11.73#ibcon#about to read 5, iclass 24, count 0 2006.190.07:40:11.73#ibcon#read 5, iclass 24, count 0 2006.190.07:40:11.73#ibcon#about to read 6, iclass 24, count 0 2006.190.07:40:11.73#ibcon#read 6, iclass 24, count 0 2006.190.07:40:11.73#ibcon#end of sib2, iclass 24, count 0 2006.190.07:40:11.73#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:40:11.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:40:11.73#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:40:11.73#ibcon#*before write, iclass 24, count 0 2006.190.07:40:11.73#ibcon#enter sib2, iclass 24, count 0 2006.190.07:40:11.73#ibcon#flushed, iclass 24, count 0 2006.190.07:40:11.73#ibcon#about to write, iclass 24, count 0 2006.190.07:40:11.73#ibcon#wrote, iclass 24, count 0 2006.190.07:40:11.73#ibcon#about to read 3, iclass 24, count 0 2006.190.07:40:11.77#ibcon#read 3, iclass 24, count 0 2006.190.07:40:11.77#ibcon#about to read 4, iclass 24, count 0 2006.190.07:40:11.77#ibcon#read 4, iclass 24, count 0 2006.190.07:40:11.77#ibcon#about to read 5, iclass 24, count 0 2006.190.07:40:11.77#ibcon#read 5, iclass 24, count 0 2006.190.07:40:11.77#ibcon#about to read 6, iclass 24, count 0 2006.190.07:40:11.77#ibcon#read 6, iclass 24, count 0 2006.190.07:40:11.77#ibcon#end of sib2, iclass 24, count 0 2006.190.07:40:11.77#ibcon#*after write, iclass 24, count 0 2006.190.07:40:11.77#ibcon#*before return 0, iclass 24, count 0 2006.190.07:40:11.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:11.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:40:11.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:40:11.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:40:11.77$vc4f8/vb=4,4 2006.190.07:40:11.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.07:40:11.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.07:40:11.77#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:11.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:11.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:11.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:11.83#ibcon#enter wrdev, iclass 26, count 2 2006.190.07:40:11.83#ibcon#first serial, iclass 26, count 2 2006.190.07:40:11.83#ibcon#enter sib2, iclass 26, count 2 2006.190.07:40:11.83#ibcon#flushed, iclass 26, count 2 2006.190.07:40:11.83#ibcon#about to write, iclass 26, count 2 2006.190.07:40:11.83#ibcon#wrote, iclass 26, count 2 2006.190.07:40:11.83#ibcon#about to read 3, iclass 26, count 2 2006.190.07:40:11.85#ibcon#read 3, iclass 26, count 2 2006.190.07:40:11.85#ibcon#about to read 4, iclass 26, count 2 2006.190.07:40:11.85#ibcon#read 4, iclass 26, count 2 2006.190.07:40:11.85#ibcon#about to read 5, iclass 26, count 2 2006.190.07:40:11.85#ibcon#read 5, iclass 26, count 2 2006.190.07:40:11.85#ibcon#about to read 6, iclass 26, count 2 2006.190.07:40:11.85#ibcon#read 6, iclass 26, count 2 2006.190.07:40:11.85#ibcon#end of sib2, iclass 26, count 2 2006.190.07:40:11.85#ibcon#*mode == 0, iclass 26, count 2 2006.190.07:40:11.85#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.07:40:11.85#ibcon#[27=AT04-04\r\n] 2006.190.07:40:11.85#ibcon#*before write, iclass 26, count 2 2006.190.07:40:11.85#ibcon#enter sib2, iclass 26, count 2 2006.190.07:40:11.85#ibcon#flushed, iclass 26, count 2 2006.190.07:40:11.85#ibcon#about to write, iclass 26, count 2 2006.190.07:40:11.85#ibcon#wrote, iclass 26, count 2 2006.190.07:40:11.85#ibcon#about to read 3, iclass 26, count 2 2006.190.07:40:11.88#ibcon#read 3, iclass 26, count 2 2006.190.07:40:11.88#ibcon#about to read 4, iclass 26, count 2 2006.190.07:40:11.88#ibcon#read 4, iclass 26, count 2 2006.190.07:40:11.88#ibcon#about to read 5, iclass 26, count 2 2006.190.07:40:11.88#ibcon#read 5, iclass 26, count 2 2006.190.07:40:11.88#ibcon#about to read 6, iclass 26, count 2 2006.190.07:40:11.88#ibcon#read 6, iclass 26, count 2 2006.190.07:40:11.88#ibcon#end of sib2, iclass 26, count 2 2006.190.07:40:11.88#ibcon#*after write, iclass 26, count 2 2006.190.07:40:11.88#ibcon#*before return 0, iclass 26, count 2 2006.190.07:40:11.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:11.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:40:11.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.07:40:11.88#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:11.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:12.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:12.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:12.00#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:40:12.00#ibcon#first serial, iclass 26, count 0 2006.190.07:40:12.00#ibcon#enter sib2, iclass 26, count 0 2006.190.07:40:12.00#ibcon#flushed, iclass 26, count 0 2006.190.07:40:12.00#ibcon#about to write, iclass 26, count 0 2006.190.07:40:12.00#ibcon#wrote, iclass 26, count 0 2006.190.07:40:12.00#ibcon#about to read 3, iclass 26, count 0 2006.190.07:40:12.02#ibcon#read 3, iclass 26, count 0 2006.190.07:40:12.02#ibcon#about to read 4, iclass 26, count 0 2006.190.07:40:12.02#ibcon#read 4, iclass 26, count 0 2006.190.07:40:12.02#ibcon#about to read 5, iclass 26, count 0 2006.190.07:40:12.02#ibcon#read 5, iclass 26, count 0 2006.190.07:40:12.02#ibcon#about to read 6, iclass 26, count 0 2006.190.07:40:12.02#ibcon#read 6, iclass 26, count 0 2006.190.07:40:12.02#ibcon#end of sib2, iclass 26, count 0 2006.190.07:40:12.02#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:40:12.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:40:12.02#ibcon#[27=USB\r\n] 2006.190.07:40:12.02#ibcon#*before write, iclass 26, count 0 2006.190.07:40:12.02#ibcon#enter sib2, iclass 26, count 0 2006.190.07:40:12.02#ibcon#flushed, iclass 26, count 0 2006.190.07:40:12.02#ibcon#about to write, iclass 26, count 0 2006.190.07:40:12.02#ibcon#wrote, iclass 26, count 0 2006.190.07:40:12.02#ibcon#about to read 3, iclass 26, count 0 2006.190.07:40:12.05#ibcon#read 3, iclass 26, count 0 2006.190.07:40:12.05#ibcon#about to read 4, iclass 26, count 0 2006.190.07:40:12.05#ibcon#read 4, iclass 26, count 0 2006.190.07:40:12.05#ibcon#about to read 5, iclass 26, count 0 2006.190.07:40:12.05#ibcon#read 5, iclass 26, count 0 2006.190.07:40:12.05#ibcon#about to read 6, iclass 26, count 0 2006.190.07:40:12.05#ibcon#read 6, iclass 26, count 0 2006.190.07:40:12.05#ibcon#end of sib2, iclass 26, count 0 2006.190.07:40:12.05#ibcon#*after write, iclass 26, count 0 2006.190.07:40:12.05#ibcon#*before return 0, iclass 26, count 0 2006.190.07:40:12.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:12.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:40:12.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:40:12.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:40:12.05$vc4f8/vblo=5,744.99 2006.190.07:40:12.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:40:12.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:40:12.05#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:12.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:12.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:12.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:12.05#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:40:12.05#ibcon#first serial, iclass 28, count 0 2006.190.07:40:12.05#ibcon#enter sib2, iclass 28, count 0 2006.190.07:40:12.05#ibcon#flushed, iclass 28, count 0 2006.190.07:40:12.05#ibcon#about to write, iclass 28, count 0 2006.190.07:40:12.05#ibcon#wrote, iclass 28, count 0 2006.190.07:40:12.05#ibcon#about to read 3, iclass 28, count 0 2006.190.07:40:12.07#ibcon#read 3, iclass 28, count 0 2006.190.07:40:12.07#ibcon#about to read 4, iclass 28, count 0 2006.190.07:40:12.07#ibcon#read 4, iclass 28, count 0 2006.190.07:40:12.07#ibcon#about to read 5, iclass 28, count 0 2006.190.07:40:12.07#ibcon#read 5, iclass 28, count 0 2006.190.07:40:12.07#ibcon#about to read 6, iclass 28, count 0 2006.190.07:40:12.07#ibcon#read 6, iclass 28, count 0 2006.190.07:40:12.07#ibcon#end of sib2, iclass 28, count 0 2006.190.07:40:12.07#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:40:12.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:40:12.07#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:40:12.07#ibcon#*before write, iclass 28, count 0 2006.190.07:40:12.07#ibcon#enter sib2, iclass 28, count 0 2006.190.07:40:12.07#ibcon#flushed, iclass 28, count 0 2006.190.07:40:12.07#ibcon#about to write, iclass 28, count 0 2006.190.07:40:12.07#ibcon#wrote, iclass 28, count 0 2006.190.07:40:12.07#ibcon#about to read 3, iclass 28, count 0 2006.190.07:40:12.11#ibcon#read 3, iclass 28, count 0 2006.190.07:40:12.11#ibcon#about to read 4, iclass 28, count 0 2006.190.07:40:12.11#ibcon#read 4, iclass 28, count 0 2006.190.07:40:12.11#ibcon#about to read 5, iclass 28, count 0 2006.190.07:40:12.11#ibcon#read 5, iclass 28, count 0 2006.190.07:40:12.11#ibcon#about to read 6, iclass 28, count 0 2006.190.07:40:12.11#ibcon#read 6, iclass 28, count 0 2006.190.07:40:12.11#ibcon#end of sib2, iclass 28, count 0 2006.190.07:40:12.11#ibcon#*after write, iclass 28, count 0 2006.190.07:40:12.11#ibcon#*before return 0, iclass 28, count 0 2006.190.07:40:12.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:12.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:40:12.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:40:12.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:40:12.11$vc4f8/vb=5,4 2006.190.07:40:12.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:40:12.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:40:12.11#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:12.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:12.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:12.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:12.17#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:40:12.17#ibcon#first serial, iclass 30, count 2 2006.190.07:40:12.17#ibcon#enter sib2, iclass 30, count 2 2006.190.07:40:12.17#ibcon#flushed, iclass 30, count 2 2006.190.07:40:12.17#ibcon#about to write, iclass 30, count 2 2006.190.07:40:12.17#ibcon#wrote, iclass 30, count 2 2006.190.07:40:12.17#ibcon#about to read 3, iclass 30, count 2 2006.190.07:40:12.19#ibcon#read 3, iclass 30, count 2 2006.190.07:40:12.19#ibcon#about to read 4, iclass 30, count 2 2006.190.07:40:12.19#ibcon#read 4, iclass 30, count 2 2006.190.07:40:12.19#ibcon#about to read 5, iclass 30, count 2 2006.190.07:40:12.19#ibcon#read 5, iclass 30, count 2 2006.190.07:40:12.19#ibcon#about to read 6, iclass 30, count 2 2006.190.07:40:12.19#ibcon#read 6, iclass 30, count 2 2006.190.07:40:12.19#ibcon#end of sib2, iclass 30, count 2 2006.190.07:40:12.19#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:40:12.19#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:40:12.19#ibcon#[27=AT05-04\r\n] 2006.190.07:40:12.19#ibcon#*before write, iclass 30, count 2 2006.190.07:40:12.19#ibcon#enter sib2, iclass 30, count 2 2006.190.07:40:12.19#ibcon#flushed, iclass 30, count 2 2006.190.07:40:12.19#ibcon#about to write, iclass 30, count 2 2006.190.07:40:12.19#ibcon#wrote, iclass 30, count 2 2006.190.07:40:12.19#ibcon#about to read 3, iclass 30, count 2 2006.190.07:40:12.22#ibcon#read 3, iclass 30, count 2 2006.190.07:40:12.22#ibcon#about to read 4, iclass 30, count 2 2006.190.07:40:12.22#ibcon#read 4, iclass 30, count 2 2006.190.07:40:12.22#ibcon#about to read 5, iclass 30, count 2 2006.190.07:40:12.22#ibcon#read 5, iclass 30, count 2 2006.190.07:40:12.22#ibcon#about to read 6, iclass 30, count 2 2006.190.07:40:12.22#ibcon#read 6, iclass 30, count 2 2006.190.07:40:12.22#ibcon#end of sib2, iclass 30, count 2 2006.190.07:40:12.22#ibcon#*after write, iclass 30, count 2 2006.190.07:40:12.22#ibcon#*before return 0, iclass 30, count 2 2006.190.07:40:12.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:12.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:40:12.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:40:12.22#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:12.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:12.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:12.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:12.34#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:40:12.34#ibcon#first serial, iclass 30, count 0 2006.190.07:40:12.34#ibcon#enter sib2, iclass 30, count 0 2006.190.07:40:12.34#ibcon#flushed, iclass 30, count 0 2006.190.07:40:12.34#ibcon#about to write, iclass 30, count 0 2006.190.07:40:12.34#ibcon#wrote, iclass 30, count 0 2006.190.07:40:12.34#ibcon#about to read 3, iclass 30, count 0 2006.190.07:40:12.36#ibcon#read 3, iclass 30, count 0 2006.190.07:40:12.36#ibcon#about to read 4, iclass 30, count 0 2006.190.07:40:12.36#ibcon#read 4, iclass 30, count 0 2006.190.07:40:12.36#ibcon#about to read 5, iclass 30, count 0 2006.190.07:40:12.36#ibcon#read 5, iclass 30, count 0 2006.190.07:40:12.36#ibcon#about to read 6, iclass 30, count 0 2006.190.07:40:12.36#ibcon#read 6, iclass 30, count 0 2006.190.07:40:12.36#ibcon#end of sib2, iclass 30, count 0 2006.190.07:40:12.36#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:40:12.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:40:12.36#ibcon#[27=USB\r\n] 2006.190.07:40:12.36#ibcon#*before write, iclass 30, count 0 2006.190.07:40:12.36#ibcon#enter sib2, iclass 30, count 0 2006.190.07:40:12.36#ibcon#flushed, iclass 30, count 0 2006.190.07:40:12.36#ibcon#about to write, iclass 30, count 0 2006.190.07:40:12.36#ibcon#wrote, iclass 30, count 0 2006.190.07:40:12.36#ibcon#about to read 3, iclass 30, count 0 2006.190.07:40:12.39#ibcon#read 3, iclass 30, count 0 2006.190.07:40:12.39#ibcon#about to read 4, iclass 30, count 0 2006.190.07:40:12.39#ibcon#read 4, iclass 30, count 0 2006.190.07:40:12.39#ibcon#about to read 5, iclass 30, count 0 2006.190.07:40:12.39#ibcon#read 5, iclass 30, count 0 2006.190.07:40:12.39#ibcon#about to read 6, iclass 30, count 0 2006.190.07:40:12.39#ibcon#read 6, iclass 30, count 0 2006.190.07:40:12.39#ibcon#end of sib2, iclass 30, count 0 2006.190.07:40:12.39#ibcon#*after write, iclass 30, count 0 2006.190.07:40:12.39#ibcon#*before return 0, iclass 30, count 0 2006.190.07:40:12.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:12.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:40:12.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:40:12.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:40:12.39$vc4f8/vblo=6,752.99 2006.190.07:40:12.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:40:12.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:40:12.39#ibcon#ireg 17 cls_cnt 0 2006.190.07:40:12.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:12.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:12.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:12.39#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:40:12.39#ibcon#first serial, iclass 32, count 0 2006.190.07:40:12.39#ibcon#enter sib2, iclass 32, count 0 2006.190.07:40:12.39#ibcon#flushed, iclass 32, count 0 2006.190.07:40:12.39#ibcon#about to write, iclass 32, count 0 2006.190.07:40:12.39#ibcon#wrote, iclass 32, count 0 2006.190.07:40:12.39#ibcon#about to read 3, iclass 32, count 0 2006.190.07:40:12.41#ibcon#read 3, iclass 32, count 0 2006.190.07:40:12.41#ibcon#about to read 4, iclass 32, count 0 2006.190.07:40:12.41#ibcon#read 4, iclass 32, count 0 2006.190.07:40:12.41#ibcon#about to read 5, iclass 32, count 0 2006.190.07:40:12.41#ibcon#read 5, iclass 32, count 0 2006.190.07:40:12.41#ibcon#about to read 6, iclass 32, count 0 2006.190.07:40:12.41#ibcon#read 6, iclass 32, count 0 2006.190.07:40:12.41#ibcon#end of sib2, iclass 32, count 0 2006.190.07:40:12.41#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:40:12.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:40:12.41#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:40:12.41#ibcon#*before write, iclass 32, count 0 2006.190.07:40:12.41#ibcon#enter sib2, iclass 32, count 0 2006.190.07:40:12.41#ibcon#flushed, iclass 32, count 0 2006.190.07:40:12.41#ibcon#about to write, iclass 32, count 0 2006.190.07:40:12.41#ibcon#wrote, iclass 32, count 0 2006.190.07:40:12.41#ibcon#about to read 3, iclass 32, count 0 2006.190.07:40:12.45#ibcon#read 3, iclass 32, count 0 2006.190.07:40:12.45#ibcon#about to read 4, iclass 32, count 0 2006.190.07:40:12.45#ibcon#read 4, iclass 32, count 0 2006.190.07:40:12.45#ibcon#about to read 5, iclass 32, count 0 2006.190.07:40:12.45#ibcon#read 5, iclass 32, count 0 2006.190.07:40:12.45#ibcon#about to read 6, iclass 32, count 0 2006.190.07:40:12.45#ibcon#read 6, iclass 32, count 0 2006.190.07:40:12.45#ibcon#end of sib2, iclass 32, count 0 2006.190.07:40:12.45#ibcon#*after write, iclass 32, count 0 2006.190.07:40:12.45#ibcon#*before return 0, iclass 32, count 0 2006.190.07:40:12.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:12.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:40:12.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:40:12.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:40:12.45$vc4f8/vb=6,4 2006.190.07:40:12.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:40:12.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:40:12.45#ibcon#ireg 11 cls_cnt 2 2006.190.07:40:12.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:12.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:12.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:12.51#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:40:12.51#ibcon#first serial, iclass 34, count 2 2006.190.07:40:12.51#ibcon#enter sib2, iclass 34, count 2 2006.190.07:40:12.51#ibcon#flushed, iclass 34, count 2 2006.190.07:40:12.51#ibcon#about to write, iclass 34, count 2 2006.190.07:40:12.51#ibcon#wrote, iclass 34, count 2 2006.190.07:40:12.51#ibcon#about to read 3, iclass 34, count 2 2006.190.07:40:12.53#ibcon#read 3, iclass 34, count 2 2006.190.07:40:12.53#ibcon#about to read 4, iclass 34, count 2 2006.190.07:40:12.53#ibcon#read 4, iclass 34, count 2 2006.190.07:40:12.53#ibcon#about to read 5, iclass 34, count 2 2006.190.07:40:12.53#ibcon#read 5, iclass 34, count 2 2006.190.07:40:12.53#ibcon#about to read 6, iclass 34, count 2 2006.190.07:40:12.53#ibcon#read 6, iclass 34, count 2 2006.190.07:40:12.53#ibcon#end of sib2, iclass 34, count 2 2006.190.07:40:12.53#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:40:12.53#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:40:12.53#ibcon#[27=AT06-04\r\n] 2006.190.07:40:12.53#ibcon#*before write, iclass 34, count 2 2006.190.07:40:12.53#ibcon#enter sib2, iclass 34, count 2 2006.190.07:40:12.53#ibcon#flushed, iclass 34, count 2 2006.190.07:40:12.53#ibcon#about to write, iclass 34, count 2 2006.190.07:40:12.53#ibcon#wrote, iclass 34, count 2 2006.190.07:40:12.53#ibcon#about to read 3, iclass 34, count 2 2006.190.07:40:12.56#ibcon#read 3, iclass 34, count 2 2006.190.07:40:12.56#ibcon#about to read 4, iclass 34, count 2 2006.190.07:40:12.56#ibcon#read 4, iclass 34, count 2 2006.190.07:40:12.56#ibcon#about to read 5, iclass 34, count 2 2006.190.07:40:12.56#ibcon#read 5, iclass 34, count 2 2006.190.07:40:12.56#ibcon#about to read 6, iclass 34, count 2 2006.190.07:40:12.56#ibcon#read 6, iclass 34, count 2 2006.190.07:40:12.56#ibcon#end of sib2, iclass 34, count 2 2006.190.07:40:12.56#ibcon#*after write, iclass 34, count 2 2006.190.07:40:12.56#ibcon#*before return 0, iclass 34, count 2 2006.190.07:40:12.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:12.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:40:12.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:40:12.56#ibcon#ireg 7 cls_cnt 0 2006.190.07:40:12.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:12.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:12.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:12.68#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:40:12.68#ibcon#first serial, iclass 34, count 0 2006.190.07:40:12.68#ibcon#enter sib2, iclass 34, count 0 2006.190.07:40:12.68#ibcon#flushed, iclass 34, count 0 2006.190.07:40:12.68#ibcon#about to write, iclass 34, count 0 2006.190.07:40:12.68#ibcon#wrote, iclass 34, count 0 2006.190.07:40:12.68#ibcon#about to read 3, iclass 34, count 0 2006.190.07:40:12.70#ibcon#read 3, iclass 34, count 0 2006.190.07:40:12.70#ibcon#about to read 4, iclass 34, count 0 2006.190.07:40:12.70#ibcon#read 4, iclass 34, count 0 2006.190.07:40:12.70#ibcon#about to read 5, iclass 34, count 0 2006.190.07:40:12.70#ibcon#read 5, iclass 34, count 0 2006.190.07:40:12.70#ibcon#about to read 6, iclass 34, count 0 2006.190.07:40:12.70#ibcon#read 6, iclass 34, count 0 2006.190.07:40:12.70#ibcon#end of sib2, iclass 34, count 0 2006.190.07:40:12.70#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:40:12.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:40:12.70#ibcon#[27=USB\r\n] 2006.190.07:40:12.70#ibcon#*before write, iclass 34, count 0 2006.190.07:40:12.70#ibcon#enter sib2, iclass 34, count 0 2006.190.07:40:12.70#ibcon#flushed, iclass 34, count 0 2006.190.07:40:12.70#ibcon#about to write, iclass 34, count 0 2006.190.07:40:12.70#ibcon#wrote, iclass 34, count 0 2006.190.07:40:12.70#ibcon#about to read 3, iclass 34, count 0 2006.190.07:40:12.73#ibcon#read 3, iclass 34, count 0 2006.190.07:40:12.73#ibcon#about to read 4, iclass 34, count 0 2006.190.07:40:12.73#ibcon#read 4, iclass 34, count 0 2006.190.07:40:12.73#ibcon#about to read 5, iclass 34, count 0 2006.190.07:40:12.73#ibcon#read 5, iclass 34, count 0 2006.190.07:40:12.73#ibcon#about to read 6, iclass 34, count 0 2006.190.07:40:12.73#ibcon#read 6, iclass 34, count 0 2006.190.07:40:12.73#ibcon#end of sib2, iclass 34, count 0 2006.190.07:40:12.73#ibcon#*after write, iclass 34, count 0 2006.190.07:40:12.73#ibcon#*before return 0, iclass 34, count 0 2006.190.07:40:12.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:12.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:40:12.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:40:12.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:40:12.73$vc4f8/vabw=wide 2006.190.07:40:12.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:40:12.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:40:12.73#ibcon#ireg 8 cls_cnt 0 2006.190.07:40:12.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:12.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:12.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:12.73#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:40:12.73#ibcon#first serial, iclass 36, count 0 2006.190.07:40:12.73#ibcon#enter sib2, iclass 36, count 0 2006.190.07:40:12.73#ibcon#flushed, iclass 36, count 0 2006.190.07:40:12.73#ibcon#about to write, iclass 36, count 0 2006.190.07:40:12.73#ibcon#wrote, iclass 36, count 0 2006.190.07:40:12.73#ibcon#about to read 3, iclass 36, count 0 2006.190.07:40:12.75#ibcon#read 3, iclass 36, count 0 2006.190.07:40:12.75#ibcon#about to read 4, iclass 36, count 0 2006.190.07:40:12.75#ibcon#read 4, iclass 36, count 0 2006.190.07:40:12.75#ibcon#about to read 5, iclass 36, count 0 2006.190.07:40:12.75#ibcon#read 5, iclass 36, count 0 2006.190.07:40:12.75#ibcon#about to read 6, iclass 36, count 0 2006.190.07:40:12.75#ibcon#read 6, iclass 36, count 0 2006.190.07:40:12.75#ibcon#end of sib2, iclass 36, count 0 2006.190.07:40:12.75#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:40:12.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:40:12.75#ibcon#[25=BW32\r\n] 2006.190.07:40:12.75#ibcon#*before write, iclass 36, count 0 2006.190.07:40:12.75#ibcon#enter sib2, iclass 36, count 0 2006.190.07:40:12.75#ibcon#flushed, iclass 36, count 0 2006.190.07:40:12.75#ibcon#about to write, iclass 36, count 0 2006.190.07:40:12.75#ibcon#wrote, iclass 36, count 0 2006.190.07:40:12.75#ibcon#about to read 3, iclass 36, count 0 2006.190.07:40:12.78#ibcon#read 3, iclass 36, count 0 2006.190.07:40:12.78#ibcon#about to read 4, iclass 36, count 0 2006.190.07:40:12.78#ibcon#read 4, iclass 36, count 0 2006.190.07:40:12.78#ibcon#about to read 5, iclass 36, count 0 2006.190.07:40:12.78#ibcon#read 5, iclass 36, count 0 2006.190.07:40:12.78#ibcon#about to read 6, iclass 36, count 0 2006.190.07:40:12.78#ibcon#read 6, iclass 36, count 0 2006.190.07:40:12.78#ibcon#end of sib2, iclass 36, count 0 2006.190.07:40:12.78#ibcon#*after write, iclass 36, count 0 2006.190.07:40:12.78#ibcon#*before return 0, iclass 36, count 0 2006.190.07:40:12.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:12.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:40:12.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:40:12.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:40:12.78$vc4f8/vbbw=wide 2006.190.07:40:12.78#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.07:40:12.78#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.07:40:12.78#ibcon#ireg 8 cls_cnt 0 2006.190.07:40:12.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:40:12.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:40:12.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:40:12.85#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:40:12.85#ibcon#first serial, iclass 38, count 0 2006.190.07:40:12.85#ibcon#enter sib2, iclass 38, count 0 2006.190.07:40:12.85#ibcon#flushed, iclass 38, count 0 2006.190.07:40:12.85#ibcon#about to write, iclass 38, count 0 2006.190.07:40:12.85#ibcon#wrote, iclass 38, count 0 2006.190.07:40:12.85#ibcon#about to read 3, iclass 38, count 0 2006.190.07:40:12.87#ibcon#read 3, iclass 38, count 0 2006.190.07:40:12.87#ibcon#about to read 4, iclass 38, count 0 2006.190.07:40:12.87#ibcon#read 4, iclass 38, count 0 2006.190.07:40:12.87#ibcon#about to read 5, iclass 38, count 0 2006.190.07:40:12.87#ibcon#read 5, iclass 38, count 0 2006.190.07:40:12.87#ibcon#about to read 6, iclass 38, count 0 2006.190.07:40:12.87#ibcon#read 6, iclass 38, count 0 2006.190.07:40:12.87#ibcon#end of sib2, iclass 38, count 0 2006.190.07:40:12.87#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:40:12.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:40:12.87#ibcon#[27=BW32\r\n] 2006.190.07:40:12.87#ibcon#*before write, iclass 38, count 0 2006.190.07:40:12.87#ibcon#enter sib2, iclass 38, count 0 2006.190.07:40:12.87#ibcon#flushed, iclass 38, count 0 2006.190.07:40:12.87#ibcon#about to write, iclass 38, count 0 2006.190.07:40:12.87#ibcon#wrote, iclass 38, count 0 2006.190.07:40:12.87#ibcon#about to read 3, iclass 38, count 0 2006.190.07:40:12.90#ibcon#read 3, iclass 38, count 0 2006.190.07:40:12.90#ibcon#about to read 4, iclass 38, count 0 2006.190.07:40:12.90#ibcon#read 4, iclass 38, count 0 2006.190.07:40:12.90#ibcon#about to read 5, iclass 38, count 0 2006.190.07:40:12.90#ibcon#read 5, iclass 38, count 0 2006.190.07:40:12.90#ibcon#about to read 6, iclass 38, count 0 2006.190.07:40:12.90#ibcon#read 6, iclass 38, count 0 2006.190.07:40:12.90#ibcon#end of sib2, iclass 38, count 0 2006.190.07:40:12.90#ibcon#*after write, iclass 38, count 0 2006.190.07:40:12.90#ibcon#*before return 0, iclass 38, count 0 2006.190.07:40:12.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:40:12.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:40:12.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:40:12.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:40:12.90$4f8m12a/ifd4f 2006.190.07:40:12.90$ifd4f/lo= 2006.190.07:40:12.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:40:12.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:40:12.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:40:12.90$ifd4f/patch= 2006.190.07:40:12.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:40:12.90$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:40:12.90$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:40:12.90$4f8m12a/"form=m,16.000,1:2 2006.190.07:40:12.90$4f8m12a/"tpicd 2006.190.07:40:12.90$4f8m12a/echo=off 2006.190.07:40:12.90$4f8m12a/xlog=off 2006.190.07:40:12.90:!2006.190.07:40:40 2006.190.07:40:22.14#trakl#Source acquired 2006.190.07:40:22.14#flagr#flagr/antenna,acquired 2006.190.07:40:40.00:preob 2006.190.07:40:41.14/onsource/TRACKING 2006.190.07:40:41.14:!2006.190.07:40:50 2006.190.07:40:50.00:data_valid=on 2006.190.07:40:50.00:midob 2006.190.07:40:50.14/onsource/TRACKING 2006.190.07:40:50.14/wx/24.53,1012.2,100 2006.190.07:40:50.32/cable/+6.4714E-03 2006.190.07:40:51.41/va/01,08,usb,yes,39,41 2006.190.07:40:51.41/va/02,07,usb,yes,39,41 2006.190.07:40:51.41/va/03,06,usb,yes,42,42 2006.190.07:40:51.41/va/04,07,usb,yes,41,44 2006.190.07:40:51.41/va/05,07,usb,yes,45,47 2006.190.07:40:51.41/va/06,06,usb,yes,44,44 2006.190.07:40:51.41/va/07,06,usb,yes,45,44 2006.190.07:40:51.41/va/08,06,usb,yes,48,47 2006.190.07:40:51.64/valo/01,532.99,yes,locked 2006.190.07:40:51.64/valo/02,572.99,yes,locked 2006.190.07:40:51.64/valo/03,672.99,yes,locked 2006.190.07:40:51.64/valo/04,832.99,yes,locked 2006.190.07:40:51.64/valo/05,652.99,yes,locked 2006.190.07:40:51.64/valo/06,772.99,yes,locked 2006.190.07:40:51.64/valo/07,832.99,yes,locked 2006.190.07:40:51.64/valo/08,852.99,yes,locked 2006.190.07:40:52.73/vb/01,04,usb,yes,31,29 2006.190.07:40:52.73/vb/02,04,usb,yes,32,34 2006.190.07:40:52.73/vb/03,04,usb,yes,29,33 2006.190.07:40:52.73/vb/04,04,usb,yes,30,30 2006.190.07:40:52.73/vb/05,04,usb,yes,28,32 2006.190.07:40:52.73/vb/06,04,usb,yes,29,32 2006.190.07:40:52.73/vb/07,04,usb,yes,31,31 2006.190.07:40:52.73/vb/08,04,usb,yes,29,32 2006.190.07:40:52.96/vblo/01,632.99,yes,locked 2006.190.07:40:52.96/vblo/02,640.99,yes,locked 2006.190.07:40:52.96/vblo/03,656.99,yes,locked 2006.190.07:40:52.96/vblo/04,712.99,yes,locked 2006.190.07:40:52.96/vblo/05,744.99,yes,locked 2006.190.07:40:52.96/vblo/06,752.99,yes,locked 2006.190.07:40:52.96/vblo/07,734.99,yes,locked 2006.190.07:40:52.96/vblo/08,744.99,yes,locked 2006.190.07:40:53.11/vabw/8 2006.190.07:40:53.26/vbbw/8 2006.190.07:40:53.35/xfe/off,on,15.0 2006.190.07:40:53.74/ifatt/23,28,28,28 2006.190.07:40:54.07/fmout-gps/S +2.83E-07 2006.190.07:40:54.15:!2006.190.07:41:50 2006.190.07:41:50.01:data_valid=off 2006.190.07:41:50.01:postob 2006.190.07:41:50.17/cable/+6.4714E-03 2006.190.07:41:50.17/wx/24.52,1012.2,100 2006.190.07:41:51.07/fmout-gps/S +2.84E-07 2006.190.07:41:51.07:scan_name=190-0742,k06190,60 2006.190.07:41:51.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.190.07:41:51.14#flagr#flagr/antenna,new-source 2006.190.07:41:52.14:checkk5 2006.190.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:41:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:41:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:41:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:41:54.05/chk_obsdata//k5ts1/T1900740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:41:54.43/chk_obsdata//k5ts2/T1900740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:41:54.81/chk_obsdata//k5ts3/T1900740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:41:55.19/chk_obsdata//k5ts4/T1900740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:41:55.89/k5log//k5ts1_log_newline 2006.190.07:41:56.58/k5log//k5ts2_log_newline 2006.190.07:41:57.28/k5log//k5ts3_log_newline 2006.190.07:41:57.98/k5log//k5ts4_log_newline 2006.190.07:41:58.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:41:58.00:4f8m12a=1 2006.190.07:41:58.00$4f8m12a/echo=on 2006.190.07:41:58.00$4f8m12a/pcalon 2006.190.07:41:58.00$pcalon/"no phase cal control is implemented here 2006.190.07:41:58.00$4f8m12a/"tpicd=stop 2006.190.07:41:58.00$4f8m12a/vc4f8 2006.190.07:41:58.00$vc4f8/valo=1,532.99 2006.190.07:41:58.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:41:58.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:41:58.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:41:58.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:41:58.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:41:58.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:41:58.00#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:41:58.00#ibcon#first serial, iclass 40, count 0 2006.190.07:41:58.00#ibcon#enter sib2, iclass 40, count 0 2006.190.07:41:58.00#ibcon#flushed, iclass 40, count 0 2006.190.07:41:58.00#ibcon#about to write, iclass 40, count 0 2006.190.07:41:58.00#ibcon#wrote, iclass 40, count 0 2006.190.07:41:58.00#ibcon#about to read 3, iclass 40, count 0 2006.190.07:41:58.05#ibcon#read 3, iclass 40, count 0 2006.190.07:41:58.05#ibcon#about to read 4, iclass 40, count 0 2006.190.07:41:58.05#ibcon#read 4, iclass 40, count 0 2006.190.07:41:58.05#ibcon#about to read 5, iclass 40, count 0 2006.190.07:41:58.05#ibcon#read 5, iclass 40, count 0 2006.190.07:41:58.05#ibcon#about to read 6, iclass 40, count 0 2006.190.07:41:58.05#ibcon#read 6, iclass 40, count 0 2006.190.07:41:58.05#ibcon#end of sib2, iclass 40, count 0 2006.190.07:41:58.05#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:41:58.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:41:58.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:41:58.05#ibcon#*before write, iclass 40, count 0 2006.190.07:41:58.05#ibcon#enter sib2, iclass 40, count 0 2006.190.07:41:58.05#ibcon#flushed, iclass 40, count 0 2006.190.07:41:58.05#ibcon#about to write, iclass 40, count 0 2006.190.07:41:58.05#ibcon#wrote, iclass 40, count 0 2006.190.07:41:58.05#ibcon#about to read 3, iclass 40, count 0 2006.190.07:41:58.10#ibcon#read 3, iclass 40, count 0 2006.190.07:41:58.10#ibcon#about to read 4, iclass 40, count 0 2006.190.07:41:58.10#ibcon#read 4, iclass 40, count 0 2006.190.07:41:58.10#ibcon#about to read 5, iclass 40, count 0 2006.190.07:41:58.10#ibcon#read 5, iclass 40, count 0 2006.190.07:41:58.10#ibcon#about to read 6, iclass 40, count 0 2006.190.07:41:58.10#ibcon#read 6, iclass 40, count 0 2006.190.07:41:58.10#ibcon#end of sib2, iclass 40, count 0 2006.190.07:41:58.10#ibcon#*after write, iclass 40, count 0 2006.190.07:41:58.10#ibcon#*before return 0, iclass 40, count 0 2006.190.07:41:58.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:41:58.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:41:58.10#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:41:58.10#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:41:58.10$vc4f8/va=1,8 2006.190.07:41:58.10#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:41:58.10#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:41:58.10#ibcon#ireg 11 cls_cnt 2 2006.190.07:41:58.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:41:58.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:41:58.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:41:58.10#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:41:58.10#ibcon#first serial, iclass 4, count 2 2006.190.07:41:58.10#ibcon#enter sib2, iclass 4, count 2 2006.190.07:41:58.10#ibcon#flushed, iclass 4, count 2 2006.190.07:41:58.10#ibcon#about to write, iclass 4, count 2 2006.190.07:41:58.10#ibcon#wrote, iclass 4, count 2 2006.190.07:41:58.10#ibcon#about to read 3, iclass 4, count 2 2006.190.07:41:58.12#ibcon#read 3, iclass 4, count 2 2006.190.07:41:58.12#ibcon#about to read 4, iclass 4, count 2 2006.190.07:41:58.12#ibcon#read 4, iclass 4, count 2 2006.190.07:41:58.12#ibcon#about to read 5, iclass 4, count 2 2006.190.07:41:58.12#ibcon#read 5, iclass 4, count 2 2006.190.07:41:58.12#ibcon#about to read 6, iclass 4, count 2 2006.190.07:41:58.12#ibcon#read 6, iclass 4, count 2 2006.190.07:41:58.12#ibcon#end of sib2, iclass 4, count 2 2006.190.07:41:58.12#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:41:58.12#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:41:58.12#ibcon#[25=AT01-08\r\n] 2006.190.07:41:58.12#ibcon#*before write, iclass 4, count 2 2006.190.07:41:58.12#ibcon#enter sib2, iclass 4, count 2 2006.190.07:41:58.12#ibcon#flushed, iclass 4, count 2 2006.190.07:41:58.12#ibcon#about to write, iclass 4, count 2 2006.190.07:41:58.12#ibcon#wrote, iclass 4, count 2 2006.190.07:41:58.12#ibcon#about to read 3, iclass 4, count 2 2006.190.07:41:58.15#ibcon#read 3, iclass 4, count 2 2006.190.07:41:58.15#ibcon#about to read 4, iclass 4, count 2 2006.190.07:41:58.15#ibcon#read 4, iclass 4, count 2 2006.190.07:41:58.15#ibcon#about to read 5, iclass 4, count 2 2006.190.07:41:58.15#ibcon#read 5, iclass 4, count 2 2006.190.07:41:58.15#ibcon#about to read 6, iclass 4, count 2 2006.190.07:41:58.15#ibcon#read 6, iclass 4, count 2 2006.190.07:41:58.15#ibcon#end of sib2, iclass 4, count 2 2006.190.07:41:58.15#ibcon#*after write, iclass 4, count 2 2006.190.07:41:58.15#ibcon#*before return 0, iclass 4, count 2 2006.190.07:41:58.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:41:58.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:41:58.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:41:58.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:41:58.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:41:58.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:41:58.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:41:58.27#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:41:58.27#ibcon#first serial, iclass 4, count 0 2006.190.07:41:58.27#ibcon#enter sib2, iclass 4, count 0 2006.190.07:41:58.27#ibcon#flushed, iclass 4, count 0 2006.190.07:41:58.27#ibcon#about to write, iclass 4, count 0 2006.190.07:41:58.27#ibcon#wrote, iclass 4, count 0 2006.190.07:41:58.27#ibcon#about to read 3, iclass 4, count 0 2006.190.07:41:58.29#ibcon#read 3, iclass 4, count 0 2006.190.07:41:58.29#ibcon#about to read 4, iclass 4, count 0 2006.190.07:41:58.29#ibcon#read 4, iclass 4, count 0 2006.190.07:41:58.29#ibcon#about to read 5, iclass 4, count 0 2006.190.07:41:58.29#ibcon#read 5, iclass 4, count 0 2006.190.07:41:58.29#ibcon#about to read 6, iclass 4, count 0 2006.190.07:41:58.29#ibcon#read 6, iclass 4, count 0 2006.190.07:41:58.29#ibcon#end of sib2, iclass 4, count 0 2006.190.07:41:58.29#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:41:58.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:41:58.29#ibcon#[25=USB\r\n] 2006.190.07:41:58.29#ibcon#*before write, iclass 4, count 0 2006.190.07:41:58.29#ibcon#enter sib2, iclass 4, count 0 2006.190.07:41:58.29#ibcon#flushed, iclass 4, count 0 2006.190.07:41:58.29#ibcon#about to write, iclass 4, count 0 2006.190.07:41:58.29#ibcon#wrote, iclass 4, count 0 2006.190.07:41:58.29#ibcon#about to read 3, iclass 4, count 0 2006.190.07:41:58.32#ibcon#read 3, iclass 4, count 0 2006.190.07:41:58.32#ibcon#about to read 4, iclass 4, count 0 2006.190.07:41:58.32#ibcon#read 4, iclass 4, count 0 2006.190.07:41:58.32#ibcon#about to read 5, iclass 4, count 0 2006.190.07:41:58.32#ibcon#read 5, iclass 4, count 0 2006.190.07:41:58.32#ibcon#about to read 6, iclass 4, count 0 2006.190.07:41:58.32#ibcon#read 6, iclass 4, count 0 2006.190.07:41:58.32#ibcon#end of sib2, iclass 4, count 0 2006.190.07:41:58.32#ibcon#*after write, iclass 4, count 0 2006.190.07:41:58.32#ibcon#*before return 0, iclass 4, count 0 2006.190.07:41:58.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:41:58.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:41:58.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:41:58.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:41:58.32$vc4f8/valo=2,572.99 2006.190.07:41:58.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:41:58.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:41:58.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:41:58.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:41:58.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:41:58.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:41:58.32#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:41:58.32#ibcon#first serial, iclass 6, count 0 2006.190.07:41:58.32#ibcon#enter sib2, iclass 6, count 0 2006.190.07:41:58.32#ibcon#flushed, iclass 6, count 0 2006.190.07:41:58.32#ibcon#about to write, iclass 6, count 0 2006.190.07:41:58.32#ibcon#wrote, iclass 6, count 0 2006.190.07:41:58.32#ibcon#about to read 3, iclass 6, count 0 2006.190.07:41:58.34#ibcon#read 3, iclass 6, count 0 2006.190.07:41:58.34#ibcon#about to read 4, iclass 6, count 0 2006.190.07:41:58.34#ibcon#read 4, iclass 6, count 0 2006.190.07:41:58.34#ibcon#about to read 5, iclass 6, count 0 2006.190.07:41:58.34#ibcon#read 5, iclass 6, count 0 2006.190.07:41:58.34#ibcon#about to read 6, iclass 6, count 0 2006.190.07:41:58.34#ibcon#read 6, iclass 6, count 0 2006.190.07:41:58.34#ibcon#end of sib2, iclass 6, count 0 2006.190.07:41:58.34#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:41:58.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:41:58.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:41:58.34#ibcon#*before write, iclass 6, count 0 2006.190.07:41:58.34#ibcon#enter sib2, iclass 6, count 0 2006.190.07:41:58.34#ibcon#flushed, iclass 6, count 0 2006.190.07:41:58.34#ibcon#about to write, iclass 6, count 0 2006.190.07:41:58.34#ibcon#wrote, iclass 6, count 0 2006.190.07:41:58.34#ibcon#about to read 3, iclass 6, count 0 2006.190.07:41:58.38#ibcon#read 3, iclass 6, count 0 2006.190.07:41:58.38#ibcon#about to read 4, iclass 6, count 0 2006.190.07:41:58.38#ibcon#read 4, iclass 6, count 0 2006.190.07:41:58.38#ibcon#about to read 5, iclass 6, count 0 2006.190.07:41:58.38#ibcon#read 5, iclass 6, count 0 2006.190.07:41:58.38#ibcon#about to read 6, iclass 6, count 0 2006.190.07:41:58.38#ibcon#read 6, iclass 6, count 0 2006.190.07:41:58.38#ibcon#end of sib2, iclass 6, count 0 2006.190.07:41:58.38#ibcon#*after write, iclass 6, count 0 2006.190.07:41:58.38#ibcon#*before return 0, iclass 6, count 0 2006.190.07:41:58.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:41:58.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:41:58.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:41:58.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:41:58.38$vc4f8/va=2,7 2006.190.07:41:58.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:41:58.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:41:58.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:41:58.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:41:58.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:41:58.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:41:58.44#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:41:58.44#ibcon#first serial, iclass 10, count 2 2006.190.07:41:58.44#ibcon#enter sib2, iclass 10, count 2 2006.190.07:41:58.44#ibcon#flushed, iclass 10, count 2 2006.190.07:41:58.44#ibcon#about to write, iclass 10, count 2 2006.190.07:41:58.44#ibcon#wrote, iclass 10, count 2 2006.190.07:41:58.44#ibcon#about to read 3, iclass 10, count 2 2006.190.07:41:58.46#ibcon#read 3, iclass 10, count 2 2006.190.07:41:58.46#ibcon#about to read 4, iclass 10, count 2 2006.190.07:41:58.46#ibcon#read 4, iclass 10, count 2 2006.190.07:41:58.46#ibcon#about to read 5, iclass 10, count 2 2006.190.07:41:58.46#ibcon#read 5, iclass 10, count 2 2006.190.07:41:58.46#ibcon#about to read 6, iclass 10, count 2 2006.190.07:41:58.46#ibcon#read 6, iclass 10, count 2 2006.190.07:41:58.46#ibcon#end of sib2, iclass 10, count 2 2006.190.07:41:58.46#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:41:58.46#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:41:58.46#ibcon#[25=AT02-07\r\n] 2006.190.07:41:58.46#ibcon#*before write, iclass 10, count 2 2006.190.07:41:58.46#ibcon#enter sib2, iclass 10, count 2 2006.190.07:41:58.46#ibcon#flushed, iclass 10, count 2 2006.190.07:41:58.46#ibcon#about to write, iclass 10, count 2 2006.190.07:41:58.46#ibcon#wrote, iclass 10, count 2 2006.190.07:41:58.46#ibcon#about to read 3, iclass 10, count 2 2006.190.07:41:58.49#ibcon#read 3, iclass 10, count 2 2006.190.07:41:58.49#ibcon#about to read 4, iclass 10, count 2 2006.190.07:41:58.49#ibcon#read 4, iclass 10, count 2 2006.190.07:41:58.49#ibcon#about to read 5, iclass 10, count 2 2006.190.07:41:58.49#ibcon#read 5, iclass 10, count 2 2006.190.07:41:58.49#ibcon#about to read 6, iclass 10, count 2 2006.190.07:41:58.49#ibcon#read 6, iclass 10, count 2 2006.190.07:41:58.49#ibcon#end of sib2, iclass 10, count 2 2006.190.07:41:58.49#ibcon#*after write, iclass 10, count 2 2006.190.07:41:58.49#ibcon#*before return 0, iclass 10, count 2 2006.190.07:41:58.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:41:58.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:41:58.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:41:58.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:41:58.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:41:58.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:41:58.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:41:58.61#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:41:58.61#ibcon#first serial, iclass 10, count 0 2006.190.07:41:58.61#ibcon#enter sib2, iclass 10, count 0 2006.190.07:41:58.61#ibcon#flushed, iclass 10, count 0 2006.190.07:41:58.61#ibcon#about to write, iclass 10, count 0 2006.190.07:41:58.61#ibcon#wrote, iclass 10, count 0 2006.190.07:41:58.61#ibcon#about to read 3, iclass 10, count 0 2006.190.07:41:58.63#ibcon#read 3, iclass 10, count 0 2006.190.07:41:58.63#ibcon#about to read 4, iclass 10, count 0 2006.190.07:41:58.63#ibcon#read 4, iclass 10, count 0 2006.190.07:41:58.63#ibcon#about to read 5, iclass 10, count 0 2006.190.07:41:58.63#ibcon#read 5, iclass 10, count 0 2006.190.07:41:58.63#ibcon#about to read 6, iclass 10, count 0 2006.190.07:41:58.63#ibcon#read 6, iclass 10, count 0 2006.190.07:41:58.63#ibcon#end of sib2, iclass 10, count 0 2006.190.07:41:58.63#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:41:58.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:41:58.63#ibcon#[25=USB\r\n] 2006.190.07:41:58.63#ibcon#*before write, iclass 10, count 0 2006.190.07:41:58.63#ibcon#enter sib2, iclass 10, count 0 2006.190.07:41:58.63#ibcon#flushed, iclass 10, count 0 2006.190.07:41:58.63#ibcon#about to write, iclass 10, count 0 2006.190.07:41:58.63#ibcon#wrote, iclass 10, count 0 2006.190.07:41:58.63#ibcon#about to read 3, iclass 10, count 0 2006.190.07:41:58.66#ibcon#read 3, iclass 10, count 0 2006.190.07:41:58.66#ibcon#about to read 4, iclass 10, count 0 2006.190.07:41:58.66#ibcon#read 4, iclass 10, count 0 2006.190.07:41:58.66#ibcon#about to read 5, iclass 10, count 0 2006.190.07:41:58.66#ibcon#read 5, iclass 10, count 0 2006.190.07:41:58.66#ibcon#about to read 6, iclass 10, count 0 2006.190.07:41:58.66#ibcon#read 6, iclass 10, count 0 2006.190.07:41:58.66#ibcon#end of sib2, iclass 10, count 0 2006.190.07:41:58.66#ibcon#*after write, iclass 10, count 0 2006.190.07:41:58.66#ibcon#*before return 0, iclass 10, count 0 2006.190.07:41:58.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:41:58.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:41:58.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:41:58.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:41:58.66$vc4f8/valo=3,672.99 2006.190.07:41:58.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:41:58.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:41:58.66#ibcon#ireg 17 cls_cnt 0 2006.190.07:41:58.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:41:58.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:41:58.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:41:58.66#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:41:58.66#ibcon#first serial, iclass 12, count 0 2006.190.07:41:58.66#ibcon#enter sib2, iclass 12, count 0 2006.190.07:41:58.66#ibcon#flushed, iclass 12, count 0 2006.190.07:41:58.66#ibcon#about to write, iclass 12, count 0 2006.190.07:41:58.66#ibcon#wrote, iclass 12, count 0 2006.190.07:41:58.66#ibcon#about to read 3, iclass 12, count 0 2006.190.07:41:58.68#ibcon#read 3, iclass 12, count 0 2006.190.07:41:58.68#ibcon#about to read 4, iclass 12, count 0 2006.190.07:41:58.68#ibcon#read 4, iclass 12, count 0 2006.190.07:41:58.68#ibcon#about to read 5, iclass 12, count 0 2006.190.07:41:58.68#ibcon#read 5, iclass 12, count 0 2006.190.07:41:58.68#ibcon#about to read 6, iclass 12, count 0 2006.190.07:41:58.68#ibcon#read 6, iclass 12, count 0 2006.190.07:41:58.68#ibcon#end of sib2, iclass 12, count 0 2006.190.07:41:58.68#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:41:58.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:41:58.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:41:58.68#ibcon#*before write, iclass 12, count 0 2006.190.07:41:58.68#ibcon#enter sib2, iclass 12, count 0 2006.190.07:41:58.68#ibcon#flushed, iclass 12, count 0 2006.190.07:41:58.68#ibcon#about to write, iclass 12, count 0 2006.190.07:41:58.68#ibcon#wrote, iclass 12, count 0 2006.190.07:41:58.68#ibcon#about to read 3, iclass 12, count 0 2006.190.07:41:58.72#ibcon#read 3, iclass 12, count 0 2006.190.07:41:58.72#ibcon#about to read 4, iclass 12, count 0 2006.190.07:41:58.72#ibcon#read 4, iclass 12, count 0 2006.190.07:41:58.72#ibcon#about to read 5, iclass 12, count 0 2006.190.07:41:58.72#ibcon#read 5, iclass 12, count 0 2006.190.07:41:58.72#ibcon#about to read 6, iclass 12, count 0 2006.190.07:41:58.72#ibcon#read 6, iclass 12, count 0 2006.190.07:41:58.72#ibcon#end of sib2, iclass 12, count 0 2006.190.07:41:58.72#ibcon#*after write, iclass 12, count 0 2006.190.07:41:58.72#ibcon#*before return 0, iclass 12, count 0 2006.190.07:41:58.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:41:58.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:41:58.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:41:58.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:41:58.72$vc4f8/va=3,6 2006.190.07:41:58.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:41:58.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:41:58.72#ibcon#ireg 11 cls_cnt 2 2006.190.07:41:58.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:41:58.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:41:58.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:41:58.78#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:41:58.78#ibcon#first serial, iclass 14, count 2 2006.190.07:41:58.78#ibcon#enter sib2, iclass 14, count 2 2006.190.07:41:58.78#ibcon#flushed, iclass 14, count 2 2006.190.07:41:58.78#ibcon#about to write, iclass 14, count 2 2006.190.07:41:58.78#ibcon#wrote, iclass 14, count 2 2006.190.07:41:58.78#ibcon#about to read 3, iclass 14, count 2 2006.190.07:41:58.80#ibcon#read 3, iclass 14, count 2 2006.190.07:41:58.80#ibcon#about to read 4, iclass 14, count 2 2006.190.07:41:58.80#ibcon#read 4, iclass 14, count 2 2006.190.07:41:58.80#ibcon#about to read 5, iclass 14, count 2 2006.190.07:41:58.80#ibcon#read 5, iclass 14, count 2 2006.190.07:41:58.80#ibcon#about to read 6, iclass 14, count 2 2006.190.07:41:58.80#ibcon#read 6, iclass 14, count 2 2006.190.07:41:58.80#ibcon#end of sib2, iclass 14, count 2 2006.190.07:41:58.80#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:41:58.80#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:41:58.80#ibcon#[25=AT03-06\r\n] 2006.190.07:41:58.80#ibcon#*before write, iclass 14, count 2 2006.190.07:41:58.80#ibcon#enter sib2, iclass 14, count 2 2006.190.07:41:58.80#ibcon#flushed, iclass 14, count 2 2006.190.07:41:58.80#ibcon#about to write, iclass 14, count 2 2006.190.07:41:58.80#ibcon#wrote, iclass 14, count 2 2006.190.07:41:58.80#ibcon#about to read 3, iclass 14, count 2 2006.190.07:41:58.83#ibcon#read 3, iclass 14, count 2 2006.190.07:41:58.83#ibcon#about to read 4, iclass 14, count 2 2006.190.07:41:58.83#ibcon#read 4, iclass 14, count 2 2006.190.07:41:58.83#ibcon#about to read 5, iclass 14, count 2 2006.190.07:41:58.83#ibcon#read 5, iclass 14, count 2 2006.190.07:41:58.83#ibcon#about to read 6, iclass 14, count 2 2006.190.07:41:58.83#ibcon#read 6, iclass 14, count 2 2006.190.07:41:58.83#ibcon#end of sib2, iclass 14, count 2 2006.190.07:41:58.83#ibcon#*after write, iclass 14, count 2 2006.190.07:41:58.83#ibcon#*before return 0, iclass 14, count 2 2006.190.07:41:58.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:41:58.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:41:58.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:41:58.83#ibcon#ireg 7 cls_cnt 0 2006.190.07:41:58.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:41:58.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:41:58.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:41:58.95#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:41:58.95#ibcon#first serial, iclass 14, count 0 2006.190.07:41:58.95#ibcon#enter sib2, iclass 14, count 0 2006.190.07:41:58.95#ibcon#flushed, iclass 14, count 0 2006.190.07:41:58.95#ibcon#about to write, iclass 14, count 0 2006.190.07:41:58.95#ibcon#wrote, iclass 14, count 0 2006.190.07:41:58.95#ibcon#about to read 3, iclass 14, count 0 2006.190.07:41:58.97#ibcon#read 3, iclass 14, count 0 2006.190.07:41:58.97#ibcon#about to read 4, iclass 14, count 0 2006.190.07:41:58.97#ibcon#read 4, iclass 14, count 0 2006.190.07:41:58.97#ibcon#about to read 5, iclass 14, count 0 2006.190.07:41:58.97#ibcon#read 5, iclass 14, count 0 2006.190.07:41:58.97#ibcon#about to read 6, iclass 14, count 0 2006.190.07:41:58.97#ibcon#read 6, iclass 14, count 0 2006.190.07:41:58.97#ibcon#end of sib2, iclass 14, count 0 2006.190.07:41:58.97#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:41:58.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:41:58.97#ibcon#[25=USB\r\n] 2006.190.07:41:58.97#ibcon#*before write, iclass 14, count 0 2006.190.07:41:58.97#ibcon#enter sib2, iclass 14, count 0 2006.190.07:41:58.97#ibcon#flushed, iclass 14, count 0 2006.190.07:41:58.97#ibcon#about to write, iclass 14, count 0 2006.190.07:41:58.97#ibcon#wrote, iclass 14, count 0 2006.190.07:41:58.97#ibcon#about to read 3, iclass 14, count 0 2006.190.07:41:59.00#ibcon#read 3, iclass 14, count 0 2006.190.07:41:59.00#ibcon#about to read 4, iclass 14, count 0 2006.190.07:41:59.00#ibcon#read 4, iclass 14, count 0 2006.190.07:41:59.00#ibcon#about to read 5, iclass 14, count 0 2006.190.07:41:59.00#ibcon#read 5, iclass 14, count 0 2006.190.07:41:59.00#ibcon#about to read 6, iclass 14, count 0 2006.190.07:41:59.00#ibcon#read 6, iclass 14, count 0 2006.190.07:41:59.00#ibcon#end of sib2, iclass 14, count 0 2006.190.07:41:59.00#ibcon#*after write, iclass 14, count 0 2006.190.07:41:59.00#ibcon#*before return 0, iclass 14, count 0 2006.190.07:41:59.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:41:59.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:41:59.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:41:59.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:41:59.00$vc4f8/valo=4,832.99 2006.190.07:41:59.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:41:59.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:41:59.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:41:59.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:41:59.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:41:59.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:41:59.00#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:41:59.00#ibcon#first serial, iclass 16, count 0 2006.190.07:41:59.00#ibcon#enter sib2, iclass 16, count 0 2006.190.07:41:59.00#ibcon#flushed, iclass 16, count 0 2006.190.07:41:59.00#ibcon#about to write, iclass 16, count 0 2006.190.07:41:59.00#ibcon#wrote, iclass 16, count 0 2006.190.07:41:59.00#ibcon#about to read 3, iclass 16, count 0 2006.190.07:41:59.02#ibcon#read 3, iclass 16, count 0 2006.190.07:41:59.02#ibcon#about to read 4, iclass 16, count 0 2006.190.07:41:59.02#ibcon#read 4, iclass 16, count 0 2006.190.07:41:59.02#ibcon#about to read 5, iclass 16, count 0 2006.190.07:41:59.02#ibcon#read 5, iclass 16, count 0 2006.190.07:41:59.02#ibcon#about to read 6, iclass 16, count 0 2006.190.07:41:59.02#ibcon#read 6, iclass 16, count 0 2006.190.07:41:59.02#ibcon#end of sib2, iclass 16, count 0 2006.190.07:41:59.02#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:41:59.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:41:59.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:41:59.02#ibcon#*before write, iclass 16, count 0 2006.190.07:41:59.02#ibcon#enter sib2, iclass 16, count 0 2006.190.07:41:59.02#ibcon#flushed, iclass 16, count 0 2006.190.07:41:59.02#ibcon#about to write, iclass 16, count 0 2006.190.07:41:59.02#ibcon#wrote, iclass 16, count 0 2006.190.07:41:59.02#ibcon#about to read 3, iclass 16, count 0 2006.190.07:41:59.06#ibcon#read 3, iclass 16, count 0 2006.190.07:41:59.06#ibcon#about to read 4, iclass 16, count 0 2006.190.07:41:59.06#ibcon#read 4, iclass 16, count 0 2006.190.07:41:59.06#ibcon#about to read 5, iclass 16, count 0 2006.190.07:41:59.06#ibcon#read 5, iclass 16, count 0 2006.190.07:41:59.06#ibcon#about to read 6, iclass 16, count 0 2006.190.07:41:59.06#ibcon#read 6, iclass 16, count 0 2006.190.07:41:59.06#ibcon#end of sib2, iclass 16, count 0 2006.190.07:41:59.06#ibcon#*after write, iclass 16, count 0 2006.190.07:41:59.06#ibcon#*before return 0, iclass 16, count 0 2006.190.07:41:59.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:41:59.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:41:59.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:41:59.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:41:59.06$vc4f8/va=4,7 2006.190.07:41:59.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.07:41:59.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.07:41:59.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:41:59.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:41:59.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:41:59.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:41:59.12#ibcon#enter wrdev, iclass 18, count 2 2006.190.07:41:59.12#ibcon#first serial, iclass 18, count 2 2006.190.07:41:59.12#ibcon#enter sib2, iclass 18, count 2 2006.190.07:41:59.12#ibcon#flushed, iclass 18, count 2 2006.190.07:41:59.12#ibcon#about to write, iclass 18, count 2 2006.190.07:41:59.12#ibcon#wrote, iclass 18, count 2 2006.190.07:41:59.12#ibcon#about to read 3, iclass 18, count 2 2006.190.07:41:59.14#ibcon#read 3, iclass 18, count 2 2006.190.07:41:59.14#ibcon#about to read 4, iclass 18, count 2 2006.190.07:41:59.14#ibcon#read 4, iclass 18, count 2 2006.190.07:41:59.14#ibcon#about to read 5, iclass 18, count 2 2006.190.07:41:59.14#ibcon#read 5, iclass 18, count 2 2006.190.07:41:59.14#ibcon#about to read 6, iclass 18, count 2 2006.190.07:41:59.14#ibcon#read 6, iclass 18, count 2 2006.190.07:41:59.14#ibcon#end of sib2, iclass 18, count 2 2006.190.07:41:59.14#ibcon#*mode == 0, iclass 18, count 2 2006.190.07:41:59.14#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.07:41:59.14#ibcon#[25=AT04-07\r\n] 2006.190.07:41:59.14#ibcon#*before write, iclass 18, count 2 2006.190.07:41:59.14#ibcon#enter sib2, iclass 18, count 2 2006.190.07:41:59.14#ibcon#flushed, iclass 18, count 2 2006.190.07:41:59.14#ibcon#about to write, iclass 18, count 2 2006.190.07:41:59.14#ibcon#wrote, iclass 18, count 2 2006.190.07:41:59.14#ibcon#about to read 3, iclass 18, count 2 2006.190.07:41:59.17#ibcon#read 3, iclass 18, count 2 2006.190.07:41:59.17#ibcon#about to read 4, iclass 18, count 2 2006.190.07:41:59.17#ibcon#read 4, iclass 18, count 2 2006.190.07:41:59.17#ibcon#about to read 5, iclass 18, count 2 2006.190.07:41:59.17#ibcon#read 5, iclass 18, count 2 2006.190.07:41:59.17#ibcon#about to read 6, iclass 18, count 2 2006.190.07:41:59.17#ibcon#read 6, iclass 18, count 2 2006.190.07:41:59.17#ibcon#end of sib2, iclass 18, count 2 2006.190.07:41:59.17#ibcon#*after write, iclass 18, count 2 2006.190.07:41:59.17#ibcon#*before return 0, iclass 18, count 2 2006.190.07:41:59.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:41:59.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:41:59.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.07:41:59.17#ibcon#ireg 7 cls_cnt 0 2006.190.07:41:59.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:41:59.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:41:59.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:41:59.29#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:41:59.29#ibcon#first serial, iclass 18, count 0 2006.190.07:41:59.29#ibcon#enter sib2, iclass 18, count 0 2006.190.07:41:59.29#ibcon#flushed, iclass 18, count 0 2006.190.07:41:59.29#ibcon#about to write, iclass 18, count 0 2006.190.07:41:59.29#ibcon#wrote, iclass 18, count 0 2006.190.07:41:59.29#ibcon#about to read 3, iclass 18, count 0 2006.190.07:41:59.31#ibcon#read 3, iclass 18, count 0 2006.190.07:41:59.31#ibcon#about to read 4, iclass 18, count 0 2006.190.07:41:59.31#ibcon#read 4, iclass 18, count 0 2006.190.07:41:59.31#ibcon#about to read 5, iclass 18, count 0 2006.190.07:41:59.31#ibcon#read 5, iclass 18, count 0 2006.190.07:41:59.31#ibcon#about to read 6, iclass 18, count 0 2006.190.07:41:59.31#ibcon#read 6, iclass 18, count 0 2006.190.07:41:59.31#ibcon#end of sib2, iclass 18, count 0 2006.190.07:41:59.31#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:41:59.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:41:59.31#ibcon#[25=USB\r\n] 2006.190.07:41:59.31#ibcon#*before write, iclass 18, count 0 2006.190.07:41:59.31#ibcon#enter sib2, iclass 18, count 0 2006.190.07:41:59.31#ibcon#flushed, iclass 18, count 0 2006.190.07:41:59.31#ibcon#about to write, iclass 18, count 0 2006.190.07:41:59.31#ibcon#wrote, iclass 18, count 0 2006.190.07:41:59.31#ibcon#about to read 3, iclass 18, count 0 2006.190.07:41:59.34#ibcon#read 3, iclass 18, count 0 2006.190.07:41:59.34#ibcon#about to read 4, iclass 18, count 0 2006.190.07:41:59.34#ibcon#read 4, iclass 18, count 0 2006.190.07:41:59.34#ibcon#about to read 5, iclass 18, count 0 2006.190.07:41:59.34#ibcon#read 5, iclass 18, count 0 2006.190.07:41:59.34#ibcon#about to read 6, iclass 18, count 0 2006.190.07:41:59.34#ibcon#read 6, iclass 18, count 0 2006.190.07:41:59.34#ibcon#end of sib2, iclass 18, count 0 2006.190.07:41:59.34#ibcon#*after write, iclass 18, count 0 2006.190.07:41:59.34#ibcon#*before return 0, iclass 18, count 0 2006.190.07:41:59.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:41:59.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:41:59.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:41:59.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:41:59.34$vc4f8/valo=5,652.99 2006.190.07:41:59.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:41:59.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:41:59.34#ibcon#ireg 17 cls_cnt 0 2006.190.07:41:59.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:41:59.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:41:59.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:41:59.34#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:41:59.34#ibcon#first serial, iclass 20, count 0 2006.190.07:41:59.34#ibcon#enter sib2, iclass 20, count 0 2006.190.07:41:59.34#ibcon#flushed, iclass 20, count 0 2006.190.07:41:59.34#ibcon#about to write, iclass 20, count 0 2006.190.07:41:59.34#ibcon#wrote, iclass 20, count 0 2006.190.07:41:59.34#ibcon#about to read 3, iclass 20, count 0 2006.190.07:41:59.36#ibcon#read 3, iclass 20, count 0 2006.190.07:41:59.36#ibcon#about to read 4, iclass 20, count 0 2006.190.07:41:59.36#ibcon#read 4, iclass 20, count 0 2006.190.07:41:59.36#ibcon#about to read 5, iclass 20, count 0 2006.190.07:41:59.36#ibcon#read 5, iclass 20, count 0 2006.190.07:41:59.36#ibcon#about to read 6, iclass 20, count 0 2006.190.07:41:59.36#ibcon#read 6, iclass 20, count 0 2006.190.07:41:59.36#ibcon#end of sib2, iclass 20, count 0 2006.190.07:41:59.36#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:41:59.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:41:59.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:41:59.36#ibcon#*before write, iclass 20, count 0 2006.190.07:41:59.36#ibcon#enter sib2, iclass 20, count 0 2006.190.07:41:59.36#ibcon#flushed, iclass 20, count 0 2006.190.07:41:59.36#ibcon#about to write, iclass 20, count 0 2006.190.07:41:59.36#ibcon#wrote, iclass 20, count 0 2006.190.07:41:59.36#ibcon#about to read 3, iclass 20, count 0 2006.190.07:41:59.40#ibcon#read 3, iclass 20, count 0 2006.190.07:41:59.40#ibcon#about to read 4, iclass 20, count 0 2006.190.07:41:59.40#ibcon#read 4, iclass 20, count 0 2006.190.07:41:59.40#ibcon#about to read 5, iclass 20, count 0 2006.190.07:41:59.40#ibcon#read 5, iclass 20, count 0 2006.190.07:41:59.40#ibcon#about to read 6, iclass 20, count 0 2006.190.07:41:59.40#ibcon#read 6, iclass 20, count 0 2006.190.07:41:59.40#ibcon#end of sib2, iclass 20, count 0 2006.190.07:41:59.40#ibcon#*after write, iclass 20, count 0 2006.190.07:41:59.40#ibcon#*before return 0, iclass 20, count 0 2006.190.07:41:59.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:41:59.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:41:59.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:41:59.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:41:59.40$vc4f8/va=5,7 2006.190.07:41:59.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:41:59.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:41:59.40#ibcon#ireg 11 cls_cnt 2 2006.190.07:41:59.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:41:59.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:41:59.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:41:59.46#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:41:59.46#ibcon#first serial, iclass 22, count 2 2006.190.07:41:59.46#ibcon#enter sib2, iclass 22, count 2 2006.190.07:41:59.46#ibcon#flushed, iclass 22, count 2 2006.190.07:41:59.46#ibcon#about to write, iclass 22, count 2 2006.190.07:41:59.46#ibcon#wrote, iclass 22, count 2 2006.190.07:41:59.46#ibcon#about to read 3, iclass 22, count 2 2006.190.07:41:59.48#ibcon#read 3, iclass 22, count 2 2006.190.07:41:59.48#ibcon#about to read 4, iclass 22, count 2 2006.190.07:41:59.48#ibcon#read 4, iclass 22, count 2 2006.190.07:41:59.48#ibcon#about to read 5, iclass 22, count 2 2006.190.07:41:59.48#ibcon#read 5, iclass 22, count 2 2006.190.07:41:59.48#ibcon#about to read 6, iclass 22, count 2 2006.190.07:41:59.48#ibcon#read 6, iclass 22, count 2 2006.190.07:41:59.48#ibcon#end of sib2, iclass 22, count 2 2006.190.07:41:59.48#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:41:59.48#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:41:59.48#ibcon#[25=AT05-07\r\n] 2006.190.07:41:59.48#ibcon#*before write, iclass 22, count 2 2006.190.07:41:59.48#ibcon#enter sib2, iclass 22, count 2 2006.190.07:41:59.48#ibcon#flushed, iclass 22, count 2 2006.190.07:41:59.48#ibcon#about to write, iclass 22, count 2 2006.190.07:41:59.48#ibcon#wrote, iclass 22, count 2 2006.190.07:41:59.48#ibcon#about to read 3, iclass 22, count 2 2006.190.07:41:59.51#ibcon#read 3, iclass 22, count 2 2006.190.07:41:59.51#ibcon#about to read 4, iclass 22, count 2 2006.190.07:41:59.51#ibcon#read 4, iclass 22, count 2 2006.190.07:41:59.51#ibcon#about to read 5, iclass 22, count 2 2006.190.07:41:59.51#ibcon#read 5, iclass 22, count 2 2006.190.07:41:59.51#ibcon#about to read 6, iclass 22, count 2 2006.190.07:41:59.51#ibcon#read 6, iclass 22, count 2 2006.190.07:41:59.51#ibcon#end of sib2, iclass 22, count 2 2006.190.07:41:59.51#ibcon#*after write, iclass 22, count 2 2006.190.07:41:59.51#ibcon#*before return 0, iclass 22, count 2 2006.190.07:41:59.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:41:59.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:41:59.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:41:59.51#ibcon#ireg 7 cls_cnt 0 2006.190.07:41:59.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:41:59.53#abcon#<5=/04 1.7 2.9 24.521001012.2\r\n> 2006.190.07:41:59.55#abcon#{5=INTERFACE CLEAR} 2006.190.07:41:59.61#abcon#[5=S1D000X0/0*\r\n] 2006.190.07:41:59.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:41:59.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:41:59.63#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:41:59.63#ibcon#first serial, iclass 22, count 0 2006.190.07:41:59.63#ibcon#enter sib2, iclass 22, count 0 2006.190.07:41:59.63#ibcon#flushed, iclass 22, count 0 2006.190.07:41:59.63#ibcon#about to write, iclass 22, count 0 2006.190.07:41:59.63#ibcon#wrote, iclass 22, count 0 2006.190.07:41:59.63#ibcon#about to read 3, iclass 22, count 0 2006.190.07:41:59.65#ibcon#read 3, iclass 22, count 0 2006.190.07:41:59.65#ibcon#about to read 4, iclass 22, count 0 2006.190.07:41:59.65#ibcon#read 4, iclass 22, count 0 2006.190.07:41:59.65#ibcon#about to read 5, iclass 22, count 0 2006.190.07:41:59.65#ibcon#read 5, iclass 22, count 0 2006.190.07:41:59.65#ibcon#about to read 6, iclass 22, count 0 2006.190.07:41:59.65#ibcon#read 6, iclass 22, count 0 2006.190.07:41:59.65#ibcon#end of sib2, iclass 22, count 0 2006.190.07:41:59.65#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:41:59.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:41:59.65#ibcon#[25=USB\r\n] 2006.190.07:41:59.65#ibcon#*before write, iclass 22, count 0 2006.190.07:41:59.65#ibcon#enter sib2, iclass 22, count 0 2006.190.07:41:59.65#ibcon#flushed, iclass 22, count 0 2006.190.07:41:59.65#ibcon#about to write, iclass 22, count 0 2006.190.07:41:59.65#ibcon#wrote, iclass 22, count 0 2006.190.07:41:59.65#ibcon#about to read 3, iclass 22, count 0 2006.190.07:41:59.68#ibcon#read 3, iclass 22, count 0 2006.190.07:41:59.68#ibcon#about to read 4, iclass 22, count 0 2006.190.07:41:59.68#ibcon#read 4, iclass 22, count 0 2006.190.07:41:59.68#ibcon#about to read 5, iclass 22, count 0 2006.190.07:41:59.68#ibcon#read 5, iclass 22, count 0 2006.190.07:41:59.68#ibcon#about to read 6, iclass 22, count 0 2006.190.07:41:59.68#ibcon#read 6, iclass 22, count 0 2006.190.07:41:59.68#ibcon#end of sib2, iclass 22, count 0 2006.190.07:41:59.68#ibcon#*after write, iclass 22, count 0 2006.190.07:41:59.68#ibcon#*before return 0, iclass 22, count 0 2006.190.07:41:59.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:41:59.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:41:59.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:41:59.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:41:59.68$vc4f8/valo=6,772.99 2006.190.07:41:59.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:41:59.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:41:59.68#ibcon#ireg 17 cls_cnt 0 2006.190.07:41:59.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:41:59.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:41:59.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:41:59.68#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:41:59.68#ibcon#first serial, iclass 28, count 0 2006.190.07:41:59.68#ibcon#enter sib2, iclass 28, count 0 2006.190.07:41:59.68#ibcon#flushed, iclass 28, count 0 2006.190.07:41:59.68#ibcon#about to write, iclass 28, count 0 2006.190.07:41:59.68#ibcon#wrote, iclass 28, count 0 2006.190.07:41:59.68#ibcon#about to read 3, iclass 28, count 0 2006.190.07:41:59.70#ibcon#read 3, iclass 28, count 0 2006.190.07:41:59.70#ibcon#about to read 4, iclass 28, count 0 2006.190.07:41:59.70#ibcon#read 4, iclass 28, count 0 2006.190.07:41:59.70#ibcon#about to read 5, iclass 28, count 0 2006.190.07:41:59.70#ibcon#read 5, iclass 28, count 0 2006.190.07:41:59.70#ibcon#about to read 6, iclass 28, count 0 2006.190.07:41:59.70#ibcon#read 6, iclass 28, count 0 2006.190.07:41:59.70#ibcon#end of sib2, iclass 28, count 0 2006.190.07:41:59.70#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:41:59.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:41:59.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:41:59.70#ibcon#*before write, iclass 28, count 0 2006.190.07:41:59.70#ibcon#enter sib2, iclass 28, count 0 2006.190.07:41:59.70#ibcon#flushed, iclass 28, count 0 2006.190.07:41:59.70#ibcon#about to write, iclass 28, count 0 2006.190.07:41:59.70#ibcon#wrote, iclass 28, count 0 2006.190.07:41:59.70#ibcon#about to read 3, iclass 28, count 0 2006.190.07:41:59.74#ibcon#read 3, iclass 28, count 0 2006.190.07:41:59.74#ibcon#about to read 4, iclass 28, count 0 2006.190.07:41:59.74#ibcon#read 4, iclass 28, count 0 2006.190.07:41:59.74#ibcon#about to read 5, iclass 28, count 0 2006.190.07:41:59.74#ibcon#read 5, iclass 28, count 0 2006.190.07:41:59.74#ibcon#about to read 6, iclass 28, count 0 2006.190.07:41:59.74#ibcon#read 6, iclass 28, count 0 2006.190.07:41:59.74#ibcon#end of sib2, iclass 28, count 0 2006.190.07:41:59.74#ibcon#*after write, iclass 28, count 0 2006.190.07:41:59.74#ibcon#*before return 0, iclass 28, count 0 2006.190.07:41:59.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:41:59.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:41:59.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:41:59.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:41:59.74$vc4f8/va=6,6 2006.190.07:41:59.74#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:41:59.74#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:41:59.74#ibcon#ireg 11 cls_cnt 2 2006.190.07:41:59.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:41:59.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:41:59.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:41:59.80#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:41:59.80#ibcon#first serial, iclass 30, count 2 2006.190.07:41:59.80#ibcon#enter sib2, iclass 30, count 2 2006.190.07:41:59.80#ibcon#flushed, iclass 30, count 2 2006.190.07:41:59.80#ibcon#about to write, iclass 30, count 2 2006.190.07:41:59.80#ibcon#wrote, iclass 30, count 2 2006.190.07:41:59.80#ibcon#about to read 3, iclass 30, count 2 2006.190.07:41:59.82#ibcon#read 3, iclass 30, count 2 2006.190.07:41:59.82#ibcon#about to read 4, iclass 30, count 2 2006.190.07:41:59.82#ibcon#read 4, iclass 30, count 2 2006.190.07:41:59.82#ibcon#about to read 5, iclass 30, count 2 2006.190.07:41:59.82#ibcon#read 5, iclass 30, count 2 2006.190.07:41:59.82#ibcon#about to read 6, iclass 30, count 2 2006.190.07:41:59.82#ibcon#read 6, iclass 30, count 2 2006.190.07:41:59.82#ibcon#end of sib2, iclass 30, count 2 2006.190.07:41:59.82#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:41:59.82#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:41:59.82#ibcon#[25=AT06-06\r\n] 2006.190.07:41:59.82#ibcon#*before write, iclass 30, count 2 2006.190.07:41:59.82#ibcon#enter sib2, iclass 30, count 2 2006.190.07:41:59.82#ibcon#flushed, iclass 30, count 2 2006.190.07:41:59.82#ibcon#about to write, iclass 30, count 2 2006.190.07:41:59.82#ibcon#wrote, iclass 30, count 2 2006.190.07:41:59.82#ibcon#about to read 3, iclass 30, count 2 2006.190.07:41:59.85#ibcon#read 3, iclass 30, count 2 2006.190.07:41:59.85#ibcon#about to read 4, iclass 30, count 2 2006.190.07:41:59.85#ibcon#read 4, iclass 30, count 2 2006.190.07:41:59.85#ibcon#about to read 5, iclass 30, count 2 2006.190.07:41:59.85#ibcon#read 5, iclass 30, count 2 2006.190.07:41:59.85#ibcon#about to read 6, iclass 30, count 2 2006.190.07:41:59.85#ibcon#read 6, iclass 30, count 2 2006.190.07:41:59.85#ibcon#end of sib2, iclass 30, count 2 2006.190.07:41:59.85#ibcon#*after write, iclass 30, count 2 2006.190.07:41:59.85#ibcon#*before return 0, iclass 30, count 2 2006.190.07:41:59.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:41:59.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:41:59.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:41:59.85#ibcon#ireg 7 cls_cnt 0 2006.190.07:41:59.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:41:59.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:41:59.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:41:59.97#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:41:59.97#ibcon#first serial, iclass 30, count 0 2006.190.07:41:59.97#ibcon#enter sib2, iclass 30, count 0 2006.190.07:41:59.97#ibcon#flushed, iclass 30, count 0 2006.190.07:41:59.97#ibcon#about to write, iclass 30, count 0 2006.190.07:41:59.97#ibcon#wrote, iclass 30, count 0 2006.190.07:41:59.97#ibcon#about to read 3, iclass 30, count 0 2006.190.07:41:59.99#ibcon#read 3, iclass 30, count 0 2006.190.07:41:59.99#ibcon#about to read 4, iclass 30, count 0 2006.190.07:41:59.99#ibcon#read 4, iclass 30, count 0 2006.190.07:41:59.99#ibcon#about to read 5, iclass 30, count 0 2006.190.07:41:59.99#ibcon#read 5, iclass 30, count 0 2006.190.07:41:59.99#ibcon#about to read 6, iclass 30, count 0 2006.190.07:41:59.99#ibcon#read 6, iclass 30, count 0 2006.190.07:41:59.99#ibcon#end of sib2, iclass 30, count 0 2006.190.07:41:59.99#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:41:59.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:41:59.99#ibcon#[25=USB\r\n] 2006.190.07:41:59.99#ibcon#*before write, iclass 30, count 0 2006.190.07:41:59.99#ibcon#enter sib2, iclass 30, count 0 2006.190.07:41:59.99#ibcon#flushed, iclass 30, count 0 2006.190.07:41:59.99#ibcon#about to write, iclass 30, count 0 2006.190.07:41:59.99#ibcon#wrote, iclass 30, count 0 2006.190.07:41:59.99#ibcon#about to read 3, iclass 30, count 0 2006.190.07:42:00.02#ibcon#read 3, iclass 30, count 0 2006.190.07:42:00.02#ibcon#about to read 4, iclass 30, count 0 2006.190.07:42:00.02#ibcon#read 4, iclass 30, count 0 2006.190.07:42:00.02#ibcon#about to read 5, iclass 30, count 0 2006.190.07:42:00.02#ibcon#read 5, iclass 30, count 0 2006.190.07:42:00.02#ibcon#about to read 6, iclass 30, count 0 2006.190.07:42:00.02#ibcon#read 6, iclass 30, count 0 2006.190.07:42:00.02#ibcon#end of sib2, iclass 30, count 0 2006.190.07:42:00.02#ibcon#*after write, iclass 30, count 0 2006.190.07:42:00.02#ibcon#*before return 0, iclass 30, count 0 2006.190.07:42:00.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:42:00.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:42:00.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:42:00.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:42:00.02$vc4f8/valo=7,832.99 2006.190.07:42:00.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:42:00.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:42:00.02#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:00.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:42:00.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:42:00.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:42:00.02#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:42:00.02#ibcon#first serial, iclass 32, count 0 2006.190.07:42:00.02#ibcon#enter sib2, iclass 32, count 0 2006.190.07:42:00.02#ibcon#flushed, iclass 32, count 0 2006.190.07:42:00.02#ibcon#about to write, iclass 32, count 0 2006.190.07:42:00.02#ibcon#wrote, iclass 32, count 0 2006.190.07:42:00.02#ibcon#about to read 3, iclass 32, count 0 2006.190.07:42:00.04#ibcon#read 3, iclass 32, count 0 2006.190.07:42:00.04#ibcon#about to read 4, iclass 32, count 0 2006.190.07:42:00.04#ibcon#read 4, iclass 32, count 0 2006.190.07:42:00.04#ibcon#about to read 5, iclass 32, count 0 2006.190.07:42:00.04#ibcon#read 5, iclass 32, count 0 2006.190.07:42:00.04#ibcon#about to read 6, iclass 32, count 0 2006.190.07:42:00.04#ibcon#read 6, iclass 32, count 0 2006.190.07:42:00.04#ibcon#end of sib2, iclass 32, count 0 2006.190.07:42:00.04#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:42:00.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:42:00.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:42:00.04#ibcon#*before write, iclass 32, count 0 2006.190.07:42:00.04#ibcon#enter sib2, iclass 32, count 0 2006.190.07:42:00.04#ibcon#flushed, iclass 32, count 0 2006.190.07:42:00.04#ibcon#about to write, iclass 32, count 0 2006.190.07:42:00.04#ibcon#wrote, iclass 32, count 0 2006.190.07:42:00.04#ibcon#about to read 3, iclass 32, count 0 2006.190.07:42:00.08#ibcon#read 3, iclass 32, count 0 2006.190.07:42:00.08#ibcon#about to read 4, iclass 32, count 0 2006.190.07:42:00.08#ibcon#read 4, iclass 32, count 0 2006.190.07:42:00.08#ibcon#about to read 5, iclass 32, count 0 2006.190.07:42:00.08#ibcon#read 5, iclass 32, count 0 2006.190.07:42:00.08#ibcon#about to read 6, iclass 32, count 0 2006.190.07:42:00.08#ibcon#read 6, iclass 32, count 0 2006.190.07:42:00.08#ibcon#end of sib2, iclass 32, count 0 2006.190.07:42:00.08#ibcon#*after write, iclass 32, count 0 2006.190.07:42:00.08#ibcon#*before return 0, iclass 32, count 0 2006.190.07:42:00.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:42:00.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:42:00.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:42:00.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:42:00.08$vc4f8/va=7,6 2006.190.07:42:00.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:42:00.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:42:00.08#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:00.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:42:00.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:42:00.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:42:00.14#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:42:00.14#ibcon#first serial, iclass 34, count 2 2006.190.07:42:00.14#ibcon#enter sib2, iclass 34, count 2 2006.190.07:42:00.14#ibcon#flushed, iclass 34, count 2 2006.190.07:42:00.14#ibcon#about to write, iclass 34, count 2 2006.190.07:42:00.14#ibcon#wrote, iclass 34, count 2 2006.190.07:42:00.14#ibcon#about to read 3, iclass 34, count 2 2006.190.07:42:00.16#ibcon#read 3, iclass 34, count 2 2006.190.07:42:00.16#ibcon#about to read 4, iclass 34, count 2 2006.190.07:42:00.16#ibcon#read 4, iclass 34, count 2 2006.190.07:42:00.16#ibcon#about to read 5, iclass 34, count 2 2006.190.07:42:00.16#ibcon#read 5, iclass 34, count 2 2006.190.07:42:00.16#ibcon#about to read 6, iclass 34, count 2 2006.190.07:42:00.16#ibcon#read 6, iclass 34, count 2 2006.190.07:42:00.16#ibcon#end of sib2, iclass 34, count 2 2006.190.07:42:00.16#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:42:00.16#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:42:00.16#ibcon#[25=AT07-06\r\n] 2006.190.07:42:00.16#ibcon#*before write, iclass 34, count 2 2006.190.07:42:00.16#ibcon#enter sib2, iclass 34, count 2 2006.190.07:42:00.16#ibcon#flushed, iclass 34, count 2 2006.190.07:42:00.16#ibcon#about to write, iclass 34, count 2 2006.190.07:42:00.16#ibcon#wrote, iclass 34, count 2 2006.190.07:42:00.16#ibcon#about to read 3, iclass 34, count 2 2006.190.07:42:00.19#ibcon#read 3, iclass 34, count 2 2006.190.07:42:00.19#ibcon#about to read 4, iclass 34, count 2 2006.190.07:42:00.19#ibcon#read 4, iclass 34, count 2 2006.190.07:42:00.19#ibcon#about to read 5, iclass 34, count 2 2006.190.07:42:00.19#ibcon#read 5, iclass 34, count 2 2006.190.07:42:00.19#ibcon#about to read 6, iclass 34, count 2 2006.190.07:42:00.19#ibcon#read 6, iclass 34, count 2 2006.190.07:42:00.19#ibcon#end of sib2, iclass 34, count 2 2006.190.07:42:00.19#ibcon#*after write, iclass 34, count 2 2006.190.07:42:00.19#ibcon#*before return 0, iclass 34, count 2 2006.190.07:42:00.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:42:00.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:42:00.19#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:42:00.19#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:00.19#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:42:00.31#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:42:00.31#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:42:00.31#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:42:00.31#ibcon#first serial, iclass 34, count 0 2006.190.07:42:00.31#ibcon#enter sib2, iclass 34, count 0 2006.190.07:42:00.31#ibcon#flushed, iclass 34, count 0 2006.190.07:42:00.31#ibcon#about to write, iclass 34, count 0 2006.190.07:42:00.31#ibcon#wrote, iclass 34, count 0 2006.190.07:42:00.31#ibcon#about to read 3, iclass 34, count 0 2006.190.07:42:00.33#ibcon#read 3, iclass 34, count 0 2006.190.07:42:00.33#ibcon#about to read 4, iclass 34, count 0 2006.190.07:42:00.33#ibcon#read 4, iclass 34, count 0 2006.190.07:42:00.33#ibcon#about to read 5, iclass 34, count 0 2006.190.07:42:00.33#ibcon#read 5, iclass 34, count 0 2006.190.07:42:00.33#ibcon#about to read 6, iclass 34, count 0 2006.190.07:42:00.33#ibcon#read 6, iclass 34, count 0 2006.190.07:42:00.33#ibcon#end of sib2, iclass 34, count 0 2006.190.07:42:00.33#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:42:00.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:42:00.33#ibcon#[25=USB\r\n] 2006.190.07:42:00.33#ibcon#*before write, iclass 34, count 0 2006.190.07:42:00.33#ibcon#enter sib2, iclass 34, count 0 2006.190.07:42:00.33#ibcon#flushed, iclass 34, count 0 2006.190.07:42:00.33#ibcon#about to write, iclass 34, count 0 2006.190.07:42:00.33#ibcon#wrote, iclass 34, count 0 2006.190.07:42:00.33#ibcon#about to read 3, iclass 34, count 0 2006.190.07:42:00.36#ibcon#read 3, iclass 34, count 0 2006.190.07:42:00.36#ibcon#about to read 4, iclass 34, count 0 2006.190.07:42:00.36#ibcon#read 4, iclass 34, count 0 2006.190.07:42:00.36#ibcon#about to read 5, iclass 34, count 0 2006.190.07:42:00.36#ibcon#read 5, iclass 34, count 0 2006.190.07:42:00.36#ibcon#about to read 6, iclass 34, count 0 2006.190.07:42:00.36#ibcon#read 6, iclass 34, count 0 2006.190.07:42:00.36#ibcon#end of sib2, iclass 34, count 0 2006.190.07:42:00.36#ibcon#*after write, iclass 34, count 0 2006.190.07:42:00.36#ibcon#*before return 0, iclass 34, count 0 2006.190.07:42:00.36#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:42:00.36#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:42:00.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:42:00.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:42:00.36$vc4f8/valo=8,852.99 2006.190.07:42:00.36#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:42:00.36#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:42:00.36#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:00.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:42:00.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:42:00.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:42:00.36#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:42:00.36#ibcon#first serial, iclass 36, count 0 2006.190.07:42:00.36#ibcon#enter sib2, iclass 36, count 0 2006.190.07:42:00.36#ibcon#flushed, iclass 36, count 0 2006.190.07:42:00.36#ibcon#about to write, iclass 36, count 0 2006.190.07:42:00.36#ibcon#wrote, iclass 36, count 0 2006.190.07:42:00.36#ibcon#about to read 3, iclass 36, count 0 2006.190.07:42:00.38#ibcon#read 3, iclass 36, count 0 2006.190.07:42:00.38#ibcon#about to read 4, iclass 36, count 0 2006.190.07:42:00.38#ibcon#read 4, iclass 36, count 0 2006.190.07:42:00.38#ibcon#about to read 5, iclass 36, count 0 2006.190.07:42:00.38#ibcon#read 5, iclass 36, count 0 2006.190.07:42:00.38#ibcon#about to read 6, iclass 36, count 0 2006.190.07:42:00.38#ibcon#read 6, iclass 36, count 0 2006.190.07:42:00.38#ibcon#end of sib2, iclass 36, count 0 2006.190.07:42:00.38#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:42:00.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:42:00.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:42:00.38#ibcon#*before write, iclass 36, count 0 2006.190.07:42:00.38#ibcon#enter sib2, iclass 36, count 0 2006.190.07:42:00.38#ibcon#flushed, iclass 36, count 0 2006.190.07:42:00.38#ibcon#about to write, iclass 36, count 0 2006.190.07:42:00.38#ibcon#wrote, iclass 36, count 0 2006.190.07:42:00.38#ibcon#about to read 3, iclass 36, count 0 2006.190.07:42:00.42#ibcon#read 3, iclass 36, count 0 2006.190.07:42:00.42#ibcon#about to read 4, iclass 36, count 0 2006.190.07:42:00.42#ibcon#read 4, iclass 36, count 0 2006.190.07:42:00.42#ibcon#about to read 5, iclass 36, count 0 2006.190.07:42:00.42#ibcon#read 5, iclass 36, count 0 2006.190.07:42:00.42#ibcon#about to read 6, iclass 36, count 0 2006.190.07:42:00.42#ibcon#read 6, iclass 36, count 0 2006.190.07:42:00.42#ibcon#end of sib2, iclass 36, count 0 2006.190.07:42:00.42#ibcon#*after write, iclass 36, count 0 2006.190.07:42:00.42#ibcon#*before return 0, iclass 36, count 0 2006.190.07:42:00.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:42:00.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:42:00.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:42:00.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:42:00.42$vc4f8/va=8,6 2006.190.07:42:00.42#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.07:42:00.42#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.07:42:00.42#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:00.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:42:00.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:42:00.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:42:00.48#ibcon#enter wrdev, iclass 38, count 2 2006.190.07:42:00.48#ibcon#first serial, iclass 38, count 2 2006.190.07:42:00.48#ibcon#enter sib2, iclass 38, count 2 2006.190.07:42:00.48#ibcon#flushed, iclass 38, count 2 2006.190.07:42:00.48#ibcon#about to write, iclass 38, count 2 2006.190.07:42:00.48#ibcon#wrote, iclass 38, count 2 2006.190.07:42:00.48#ibcon#about to read 3, iclass 38, count 2 2006.190.07:42:00.50#ibcon#read 3, iclass 38, count 2 2006.190.07:42:00.50#ibcon#about to read 4, iclass 38, count 2 2006.190.07:42:00.50#ibcon#read 4, iclass 38, count 2 2006.190.07:42:00.50#ibcon#about to read 5, iclass 38, count 2 2006.190.07:42:00.50#ibcon#read 5, iclass 38, count 2 2006.190.07:42:00.50#ibcon#about to read 6, iclass 38, count 2 2006.190.07:42:00.50#ibcon#read 6, iclass 38, count 2 2006.190.07:42:00.50#ibcon#end of sib2, iclass 38, count 2 2006.190.07:42:00.50#ibcon#*mode == 0, iclass 38, count 2 2006.190.07:42:00.50#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.07:42:00.50#ibcon#[25=AT08-06\r\n] 2006.190.07:42:00.50#ibcon#*before write, iclass 38, count 2 2006.190.07:42:00.50#ibcon#enter sib2, iclass 38, count 2 2006.190.07:42:00.50#ibcon#flushed, iclass 38, count 2 2006.190.07:42:00.50#ibcon#about to write, iclass 38, count 2 2006.190.07:42:00.50#ibcon#wrote, iclass 38, count 2 2006.190.07:42:00.50#ibcon#about to read 3, iclass 38, count 2 2006.190.07:42:00.53#ibcon#read 3, iclass 38, count 2 2006.190.07:42:00.53#ibcon#about to read 4, iclass 38, count 2 2006.190.07:42:00.53#ibcon#read 4, iclass 38, count 2 2006.190.07:42:00.53#ibcon#about to read 5, iclass 38, count 2 2006.190.07:42:00.53#ibcon#read 5, iclass 38, count 2 2006.190.07:42:00.53#ibcon#about to read 6, iclass 38, count 2 2006.190.07:42:00.53#ibcon#read 6, iclass 38, count 2 2006.190.07:42:00.53#ibcon#end of sib2, iclass 38, count 2 2006.190.07:42:00.53#ibcon#*after write, iclass 38, count 2 2006.190.07:42:00.53#ibcon#*before return 0, iclass 38, count 2 2006.190.07:42:00.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:42:00.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:42:00.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.07:42:00.53#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:00.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:42:00.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:42:00.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:42:00.65#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:42:00.65#ibcon#first serial, iclass 38, count 0 2006.190.07:42:00.65#ibcon#enter sib2, iclass 38, count 0 2006.190.07:42:00.65#ibcon#flushed, iclass 38, count 0 2006.190.07:42:00.65#ibcon#about to write, iclass 38, count 0 2006.190.07:42:00.65#ibcon#wrote, iclass 38, count 0 2006.190.07:42:00.65#ibcon#about to read 3, iclass 38, count 0 2006.190.07:42:00.67#ibcon#read 3, iclass 38, count 0 2006.190.07:42:00.67#ibcon#about to read 4, iclass 38, count 0 2006.190.07:42:00.67#ibcon#read 4, iclass 38, count 0 2006.190.07:42:00.67#ibcon#about to read 5, iclass 38, count 0 2006.190.07:42:00.67#ibcon#read 5, iclass 38, count 0 2006.190.07:42:00.67#ibcon#about to read 6, iclass 38, count 0 2006.190.07:42:00.67#ibcon#read 6, iclass 38, count 0 2006.190.07:42:00.67#ibcon#end of sib2, iclass 38, count 0 2006.190.07:42:00.67#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:42:00.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:42:00.67#ibcon#[25=USB\r\n] 2006.190.07:42:00.67#ibcon#*before write, iclass 38, count 0 2006.190.07:42:00.67#ibcon#enter sib2, iclass 38, count 0 2006.190.07:42:00.67#ibcon#flushed, iclass 38, count 0 2006.190.07:42:00.67#ibcon#about to write, iclass 38, count 0 2006.190.07:42:00.67#ibcon#wrote, iclass 38, count 0 2006.190.07:42:00.67#ibcon#about to read 3, iclass 38, count 0 2006.190.07:42:00.70#ibcon#read 3, iclass 38, count 0 2006.190.07:42:00.70#ibcon#about to read 4, iclass 38, count 0 2006.190.07:42:00.70#ibcon#read 4, iclass 38, count 0 2006.190.07:42:00.70#ibcon#about to read 5, iclass 38, count 0 2006.190.07:42:00.70#ibcon#read 5, iclass 38, count 0 2006.190.07:42:00.70#ibcon#about to read 6, iclass 38, count 0 2006.190.07:42:00.70#ibcon#read 6, iclass 38, count 0 2006.190.07:42:00.70#ibcon#end of sib2, iclass 38, count 0 2006.190.07:42:00.70#ibcon#*after write, iclass 38, count 0 2006.190.07:42:00.70#ibcon#*before return 0, iclass 38, count 0 2006.190.07:42:00.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:42:00.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:42:00.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:42:00.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:42:00.70$vc4f8/vblo=1,632.99 2006.190.07:42:00.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:42:00.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:42:00.70#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:00.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:42:00.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:42:00.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:42:00.70#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:42:00.70#ibcon#first serial, iclass 40, count 0 2006.190.07:42:00.70#ibcon#enter sib2, iclass 40, count 0 2006.190.07:42:00.70#ibcon#flushed, iclass 40, count 0 2006.190.07:42:00.70#ibcon#about to write, iclass 40, count 0 2006.190.07:42:00.70#ibcon#wrote, iclass 40, count 0 2006.190.07:42:00.70#ibcon#about to read 3, iclass 40, count 0 2006.190.07:42:00.72#ibcon#read 3, iclass 40, count 0 2006.190.07:42:00.72#ibcon#about to read 4, iclass 40, count 0 2006.190.07:42:00.72#ibcon#read 4, iclass 40, count 0 2006.190.07:42:00.72#ibcon#about to read 5, iclass 40, count 0 2006.190.07:42:00.72#ibcon#read 5, iclass 40, count 0 2006.190.07:42:00.72#ibcon#about to read 6, iclass 40, count 0 2006.190.07:42:00.72#ibcon#read 6, iclass 40, count 0 2006.190.07:42:00.72#ibcon#end of sib2, iclass 40, count 0 2006.190.07:42:00.72#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:42:00.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:42:00.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:42:00.72#ibcon#*before write, iclass 40, count 0 2006.190.07:42:00.72#ibcon#enter sib2, iclass 40, count 0 2006.190.07:42:00.72#ibcon#flushed, iclass 40, count 0 2006.190.07:42:00.72#ibcon#about to write, iclass 40, count 0 2006.190.07:42:00.72#ibcon#wrote, iclass 40, count 0 2006.190.07:42:00.72#ibcon#about to read 3, iclass 40, count 0 2006.190.07:42:00.76#ibcon#read 3, iclass 40, count 0 2006.190.07:42:00.76#ibcon#about to read 4, iclass 40, count 0 2006.190.07:42:00.76#ibcon#read 4, iclass 40, count 0 2006.190.07:42:00.76#ibcon#about to read 5, iclass 40, count 0 2006.190.07:42:00.76#ibcon#read 5, iclass 40, count 0 2006.190.07:42:00.76#ibcon#about to read 6, iclass 40, count 0 2006.190.07:42:00.76#ibcon#read 6, iclass 40, count 0 2006.190.07:42:00.76#ibcon#end of sib2, iclass 40, count 0 2006.190.07:42:00.76#ibcon#*after write, iclass 40, count 0 2006.190.07:42:00.76#ibcon#*before return 0, iclass 40, count 0 2006.190.07:42:00.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:42:00.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:42:00.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:42:00.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:42:00.76$vc4f8/vb=1,4 2006.190.07:42:00.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:42:00.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:42:00.76#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:00.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:42:00.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:42:00.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:42:00.76#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:42:00.76#ibcon#first serial, iclass 4, count 2 2006.190.07:42:00.76#ibcon#enter sib2, iclass 4, count 2 2006.190.07:42:00.76#ibcon#flushed, iclass 4, count 2 2006.190.07:42:00.76#ibcon#about to write, iclass 4, count 2 2006.190.07:42:00.76#ibcon#wrote, iclass 4, count 2 2006.190.07:42:00.76#ibcon#about to read 3, iclass 4, count 2 2006.190.07:42:00.78#ibcon#read 3, iclass 4, count 2 2006.190.07:42:00.78#ibcon#about to read 4, iclass 4, count 2 2006.190.07:42:00.78#ibcon#read 4, iclass 4, count 2 2006.190.07:42:00.78#ibcon#about to read 5, iclass 4, count 2 2006.190.07:42:00.78#ibcon#read 5, iclass 4, count 2 2006.190.07:42:00.78#ibcon#about to read 6, iclass 4, count 2 2006.190.07:42:00.78#ibcon#read 6, iclass 4, count 2 2006.190.07:42:00.78#ibcon#end of sib2, iclass 4, count 2 2006.190.07:42:00.78#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:42:00.78#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:42:00.78#ibcon#[27=AT01-04\r\n] 2006.190.07:42:00.78#ibcon#*before write, iclass 4, count 2 2006.190.07:42:00.78#ibcon#enter sib2, iclass 4, count 2 2006.190.07:42:00.78#ibcon#flushed, iclass 4, count 2 2006.190.07:42:00.78#ibcon#about to write, iclass 4, count 2 2006.190.07:42:00.78#ibcon#wrote, iclass 4, count 2 2006.190.07:42:00.78#ibcon#about to read 3, iclass 4, count 2 2006.190.07:42:00.81#ibcon#read 3, iclass 4, count 2 2006.190.07:42:00.81#ibcon#about to read 4, iclass 4, count 2 2006.190.07:42:00.81#ibcon#read 4, iclass 4, count 2 2006.190.07:42:00.81#ibcon#about to read 5, iclass 4, count 2 2006.190.07:42:00.81#ibcon#read 5, iclass 4, count 2 2006.190.07:42:00.81#ibcon#about to read 6, iclass 4, count 2 2006.190.07:42:00.81#ibcon#read 6, iclass 4, count 2 2006.190.07:42:00.81#ibcon#end of sib2, iclass 4, count 2 2006.190.07:42:00.81#ibcon#*after write, iclass 4, count 2 2006.190.07:42:00.81#ibcon#*before return 0, iclass 4, count 2 2006.190.07:42:00.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:42:00.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:42:00.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:42:00.81#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:00.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:42:00.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:42:00.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:42:00.93#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:42:00.93#ibcon#first serial, iclass 4, count 0 2006.190.07:42:00.93#ibcon#enter sib2, iclass 4, count 0 2006.190.07:42:00.93#ibcon#flushed, iclass 4, count 0 2006.190.07:42:00.93#ibcon#about to write, iclass 4, count 0 2006.190.07:42:00.93#ibcon#wrote, iclass 4, count 0 2006.190.07:42:00.93#ibcon#about to read 3, iclass 4, count 0 2006.190.07:42:00.95#ibcon#read 3, iclass 4, count 0 2006.190.07:42:00.95#ibcon#about to read 4, iclass 4, count 0 2006.190.07:42:00.95#ibcon#read 4, iclass 4, count 0 2006.190.07:42:00.95#ibcon#about to read 5, iclass 4, count 0 2006.190.07:42:00.95#ibcon#read 5, iclass 4, count 0 2006.190.07:42:00.95#ibcon#about to read 6, iclass 4, count 0 2006.190.07:42:00.95#ibcon#read 6, iclass 4, count 0 2006.190.07:42:00.95#ibcon#end of sib2, iclass 4, count 0 2006.190.07:42:00.95#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:42:00.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:42:00.95#ibcon#[27=USB\r\n] 2006.190.07:42:00.95#ibcon#*before write, iclass 4, count 0 2006.190.07:42:00.95#ibcon#enter sib2, iclass 4, count 0 2006.190.07:42:00.95#ibcon#flushed, iclass 4, count 0 2006.190.07:42:00.95#ibcon#about to write, iclass 4, count 0 2006.190.07:42:00.95#ibcon#wrote, iclass 4, count 0 2006.190.07:42:00.95#ibcon#about to read 3, iclass 4, count 0 2006.190.07:42:00.98#ibcon#read 3, iclass 4, count 0 2006.190.07:42:00.98#ibcon#about to read 4, iclass 4, count 0 2006.190.07:42:00.98#ibcon#read 4, iclass 4, count 0 2006.190.07:42:00.98#ibcon#about to read 5, iclass 4, count 0 2006.190.07:42:00.98#ibcon#read 5, iclass 4, count 0 2006.190.07:42:00.98#ibcon#about to read 6, iclass 4, count 0 2006.190.07:42:00.98#ibcon#read 6, iclass 4, count 0 2006.190.07:42:00.98#ibcon#end of sib2, iclass 4, count 0 2006.190.07:42:00.98#ibcon#*after write, iclass 4, count 0 2006.190.07:42:00.98#ibcon#*before return 0, iclass 4, count 0 2006.190.07:42:00.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:42:00.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:42:00.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:42:00.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:42:00.98$vc4f8/vblo=2,640.99 2006.190.07:42:00.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:42:00.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:42:00.98#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:00.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:42:00.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:42:00.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:42:00.98#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:42:00.98#ibcon#first serial, iclass 6, count 0 2006.190.07:42:00.98#ibcon#enter sib2, iclass 6, count 0 2006.190.07:42:00.98#ibcon#flushed, iclass 6, count 0 2006.190.07:42:00.98#ibcon#about to write, iclass 6, count 0 2006.190.07:42:00.98#ibcon#wrote, iclass 6, count 0 2006.190.07:42:00.98#ibcon#about to read 3, iclass 6, count 0 2006.190.07:42:01.00#ibcon#read 3, iclass 6, count 0 2006.190.07:42:01.00#ibcon#about to read 4, iclass 6, count 0 2006.190.07:42:01.00#ibcon#read 4, iclass 6, count 0 2006.190.07:42:01.00#ibcon#about to read 5, iclass 6, count 0 2006.190.07:42:01.00#ibcon#read 5, iclass 6, count 0 2006.190.07:42:01.00#ibcon#about to read 6, iclass 6, count 0 2006.190.07:42:01.00#ibcon#read 6, iclass 6, count 0 2006.190.07:42:01.00#ibcon#end of sib2, iclass 6, count 0 2006.190.07:42:01.00#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:42:01.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:42:01.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:42:01.00#ibcon#*before write, iclass 6, count 0 2006.190.07:42:01.00#ibcon#enter sib2, iclass 6, count 0 2006.190.07:42:01.00#ibcon#flushed, iclass 6, count 0 2006.190.07:42:01.00#ibcon#about to write, iclass 6, count 0 2006.190.07:42:01.00#ibcon#wrote, iclass 6, count 0 2006.190.07:42:01.00#ibcon#about to read 3, iclass 6, count 0 2006.190.07:42:01.04#ibcon#read 3, iclass 6, count 0 2006.190.07:42:01.04#ibcon#about to read 4, iclass 6, count 0 2006.190.07:42:01.04#ibcon#read 4, iclass 6, count 0 2006.190.07:42:01.04#ibcon#about to read 5, iclass 6, count 0 2006.190.07:42:01.04#ibcon#read 5, iclass 6, count 0 2006.190.07:42:01.04#ibcon#about to read 6, iclass 6, count 0 2006.190.07:42:01.04#ibcon#read 6, iclass 6, count 0 2006.190.07:42:01.04#ibcon#end of sib2, iclass 6, count 0 2006.190.07:42:01.04#ibcon#*after write, iclass 6, count 0 2006.190.07:42:01.04#ibcon#*before return 0, iclass 6, count 0 2006.190.07:42:01.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:42:01.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:42:01.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:42:01.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:42:01.04$vc4f8/vb=2,4 2006.190.07:42:01.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:42:01.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:42:01.04#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:01.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:42:01.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:42:01.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:42:01.10#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:42:01.10#ibcon#first serial, iclass 10, count 2 2006.190.07:42:01.10#ibcon#enter sib2, iclass 10, count 2 2006.190.07:42:01.10#ibcon#flushed, iclass 10, count 2 2006.190.07:42:01.10#ibcon#about to write, iclass 10, count 2 2006.190.07:42:01.10#ibcon#wrote, iclass 10, count 2 2006.190.07:42:01.10#ibcon#about to read 3, iclass 10, count 2 2006.190.07:42:01.12#ibcon#read 3, iclass 10, count 2 2006.190.07:42:01.12#ibcon#about to read 4, iclass 10, count 2 2006.190.07:42:01.12#ibcon#read 4, iclass 10, count 2 2006.190.07:42:01.12#ibcon#about to read 5, iclass 10, count 2 2006.190.07:42:01.12#ibcon#read 5, iclass 10, count 2 2006.190.07:42:01.12#ibcon#about to read 6, iclass 10, count 2 2006.190.07:42:01.12#ibcon#read 6, iclass 10, count 2 2006.190.07:42:01.12#ibcon#end of sib2, iclass 10, count 2 2006.190.07:42:01.12#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:42:01.12#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:42:01.12#ibcon#[27=AT02-04\r\n] 2006.190.07:42:01.12#ibcon#*before write, iclass 10, count 2 2006.190.07:42:01.12#ibcon#enter sib2, iclass 10, count 2 2006.190.07:42:01.12#ibcon#flushed, iclass 10, count 2 2006.190.07:42:01.12#ibcon#about to write, iclass 10, count 2 2006.190.07:42:01.12#ibcon#wrote, iclass 10, count 2 2006.190.07:42:01.12#ibcon#about to read 3, iclass 10, count 2 2006.190.07:42:01.15#ibcon#read 3, iclass 10, count 2 2006.190.07:42:01.15#ibcon#about to read 4, iclass 10, count 2 2006.190.07:42:01.15#ibcon#read 4, iclass 10, count 2 2006.190.07:42:01.15#ibcon#about to read 5, iclass 10, count 2 2006.190.07:42:01.15#ibcon#read 5, iclass 10, count 2 2006.190.07:42:01.15#ibcon#about to read 6, iclass 10, count 2 2006.190.07:42:01.15#ibcon#read 6, iclass 10, count 2 2006.190.07:42:01.15#ibcon#end of sib2, iclass 10, count 2 2006.190.07:42:01.15#ibcon#*after write, iclass 10, count 2 2006.190.07:42:01.15#ibcon#*before return 0, iclass 10, count 2 2006.190.07:42:01.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:42:01.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:42:01.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:42:01.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:01.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:42:01.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:42:01.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:42:01.27#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:42:01.27#ibcon#first serial, iclass 10, count 0 2006.190.07:42:01.27#ibcon#enter sib2, iclass 10, count 0 2006.190.07:42:01.27#ibcon#flushed, iclass 10, count 0 2006.190.07:42:01.27#ibcon#about to write, iclass 10, count 0 2006.190.07:42:01.27#ibcon#wrote, iclass 10, count 0 2006.190.07:42:01.27#ibcon#about to read 3, iclass 10, count 0 2006.190.07:42:01.29#ibcon#read 3, iclass 10, count 0 2006.190.07:42:01.29#ibcon#about to read 4, iclass 10, count 0 2006.190.07:42:01.29#ibcon#read 4, iclass 10, count 0 2006.190.07:42:01.29#ibcon#about to read 5, iclass 10, count 0 2006.190.07:42:01.29#ibcon#read 5, iclass 10, count 0 2006.190.07:42:01.29#ibcon#about to read 6, iclass 10, count 0 2006.190.07:42:01.29#ibcon#read 6, iclass 10, count 0 2006.190.07:42:01.29#ibcon#end of sib2, iclass 10, count 0 2006.190.07:42:01.29#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:42:01.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:42:01.29#ibcon#[27=USB\r\n] 2006.190.07:42:01.29#ibcon#*before write, iclass 10, count 0 2006.190.07:42:01.29#ibcon#enter sib2, iclass 10, count 0 2006.190.07:42:01.29#ibcon#flushed, iclass 10, count 0 2006.190.07:42:01.29#ibcon#about to write, iclass 10, count 0 2006.190.07:42:01.29#ibcon#wrote, iclass 10, count 0 2006.190.07:42:01.29#ibcon#about to read 3, iclass 10, count 0 2006.190.07:42:01.32#ibcon#read 3, iclass 10, count 0 2006.190.07:42:01.32#ibcon#about to read 4, iclass 10, count 0 2006.190.07:42:01.32#ibcon#read 4, iclass 10, count 0 2006.190.07:42:01.32#ibcon#about to read 5, iclass 10, count 0 2006.190.07:42:01.32#ibcon#read 5, iclass 10, count 0 2006.190.07:42:01.32#ibcon#about to read 6, iclass 10, count 0 2006.190.07:42:01.32#ibcon#read 6, iclass 10, count 0 2006.190.07:42:01.32#ibcon#end of sib2, iclass 10, count 0 2006.190.07:42:01.32#ibcon#*after write, iclass 10, count 0 2006.190.07:42:01.32#ibcon#*before return 0, iclass 10, count 0 2006.190.07:42:01.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:42:01.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:42:01.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:42:01.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:42:01.32$vc4f8/vblo=3,656.99 2006.190.07:42:01.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:42:01.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:42:01.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:01.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:42:01.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:42:01.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:42:01.32#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:42:01.32#ibcon#first serial, iclass 12, count 0 2006.190.07:42:01.32#ibcon#enter sib2, iclass 12, count 0 2006.190.07:42:01.32#ibcon#flushed, iclass 12, count 0 2006.190.07:42:01.32#ibcon#about to write, iclass 12, count 0 2006.190.07:42:01.32#ibcon#wrote, iclass 12, count 0 2006.190.07:42:01.32#ibcon#about to read 3, iclass 12, count 0 2006.190.07:42:01.34#ibcon#read 3, iclass 12, count 0 2006.190.07:42:01.34#ibcon#about to read 4, iclass 12, count 0 2006.190.07:42:01.34#ibcon#read 4, iclass 12, count 0 2006.190.07:42:01.34#ibcon#about to read 5, iclass 12, count 0 2006.190.07:42:01.34#ibcon#read 5, iclass 12, count 0 2006.190.07:42:01.34#ibcon#about to read 6, iclass 12, count 0 2006.190.07:42:01.34#ibcon#read 6, iclass 12, count 0 2006.190.07:42:01.34#ibcon#end of sib2, iclass 12, count 0 2006.190.07:42:01.34#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:42:01.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:42:01.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:42:01.34#ibcon#*before write, iclass 12, count 0 2006.190.07:42:01.34#ibcon#enter sib2, iclass 12, count 0 2006.190.07:42:01.34#ibcon#flushed, iclass 12, count 0 2006.190.07:42:01.34#ibcon#about to write, iclass 12, count 0 2006.190.07:42:01.34#ibcon#wrote, iclass 12, count 0 2006.190.07:42:01.34#ibcon#about to read 3, iclass 12, count 0 2006.190.07:42:01.38#ibcon#read 3, iclass 12, count 0 2006.190.07:42:01.38#ibcon#about to read 4, iclass 12, count 0 2006.190.07:42:01.38#ibcon#read 4, iclass 12, count 0 2006.190.07:42:01.38#ibcon#about to read 5, iclass 12, count 0 2006.190.07:42:01.38#ibcon#read 5, iclass 12, count 0 2006.190.07:42:01.38#ibcon#about to read 6, iclass 12, count 0 2006.190.07:42:01.38#ibcon#read 6, iclass 12, count 0 2006.190.07:42:01.38#ibcon#end of sib2, iclass 12, count 0 2006.190.07:42:01.38#ibcon#*after write, iclass 12, count 0 2006.190.07:42:01.38#ibcon#*before return 0, iclass 12, count 0 2006.190.07:42:01.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:42:01.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:42:01.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:42:01.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:42:01.38$vc4f8/vb=3,4 2006.190.07:42:01.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:42:01.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:42:01.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:01.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:42:01.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:42:01.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:42:01.44#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:42:01.44#ibcon#first serial, iclass 14, count 2 2006.190.07:42:01.44#ibcon#enter sib2, iclass 14, count 2 2006.190.07:42:01.44#ibcon#flushed, iclass 14, count 2 2006.190.07:42:01.44#ibcon#about to write, iclass 14, count 2 2006.190.07:42:01.44#ibcon#wrote, iclass 14, count 2 2006.190.07:42:01.44#ibcon#about to read 3, iclass 14, count 2 2006.190.07:42:01.46#ibcon#read 3, iclass 14, count 2 2006.190.07:42:01.46#ibcon#about to read 4, iclass 14, count 2 2006.190.07:42:01.46#ibcon#read 4, iclass 14, count 2 2006.190.07:42:01.46#ibcon#about to read 5, iclass 14, count 2 2006.190.07:42:01.46#ibcon#read 5, iclass 14, count 2 2006.190.07:42:01.46#ibcon#about to read 6, iclass 14, count 2 2006.190.07:42:01.46#ibcon#read 6, iclass 14, count 2 2006.190.07:42:01.46#ibcon#end of sib2, iclass 14, count 2 2006.190.07:42:01.46#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:42:01.46#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:42:01.46#ibcon#[27=AT03-04\r\n] 2006.190.07:42:01.46#ibcon#*before write, iclass 14, count 2 2006.190.07:42:01.46#ibcon#enter sib2, iclass 14, count 2 2006.190.07:42:01.46#ibcon#flushed, iclass 14, count 2 2006.190.07:42:01.46#ibcon#about to write, iclass 14, count 2 2006.190.07:42:01.46#ibcon#wrote, iclass 14, count 2 2006.190.07:42:01.46#ibcon#about to read 3, iclass 14, count 2 2006.190.07:42:01.49#ibcon#read 3, iclass 14, count 2 2006.190.07:42:01.49#ibcon#about to read 4, iclass 14, count 2 2006.190.07:42:01.49#ibcon#read 4, iclass 14, count 2 2006.190.07:42:01.49#ibcon#about to read 5, iclass 14, count 2 2006.190.07:42:01.49#ibcon#read 5, iclass 14, count 2 2006.190.07:42:01.49#ibcon#about to read 6, iclass 14, count 2 2006.190.07:42:01.49#ibcon#read 6, iclass 14, count 2 2006.190.07:42:01.49#ibcon#end of sib2, iclass 14, count 2 2006.190.07:42:01.49#ibcon#*after write, iclass 14, count 2 2006.190.07:42:01.49#ibcon#*before return 0, iclass 14, count 2 2006.190.07:42:01.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:42:01.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:42:01.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:42:01.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:01.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:42:01.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:42:01.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:42:01.61#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:42:01.61#ibcon#first serial, iclass 14, count 0 2006.190.07:42:01.61#ibcon#enter sib2, iclass 14, count 0 2006.190.07:42:01.61#ibcon#flushed, iclass 14, count 0 2006.190.07:42:01.61#ibcon#about to write, iclass 14, count 0 2006.190.07:42:01.61#ibcon#wrote, iclass 14, count 0 2006.190.07:42:01.61#ibcon#about to read 3, iclass 14, count 0 2006.190.07:42:01.63#ibcon#read 3, iclass 14, count 0 2006.190.07:42:01.63#ibcon#about to read 4, iclass 14, count 0 2006.190.07:42:01.63#ibcon#read 4, iclass 14, count 0 2006.190.07:42:01.63#ibcon#about to read 5, iclass 14, count 0 2006.190.07:42:01.63#ibcon#read 5, iclass 14, count 0 2006.190.07:42:01.63#ibcon#about to read 6, iclass 14, count 0 2006.190.07:42:01.63#ibcon#read 6, iclass 14, count 0 2006.190.07:42:01.63#ibcon#end of sib2, iclass 14, count 0 2006.190.07:42:01.63#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:42:01.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:42:01.63#ibcon#[27=USB\r\n] 2006.190.07:42:01.63#ibcon#*before write, iclass 14, count 0 2006.190.07:42:01.63#ibcon#enter sib2, iclass 14, count 0 2006.190.07:42:01.63#ibcon#flushed, iclass 14, count 0 2006.190.07:42:01.63#ibcon#about to write, iclass 14, count 0 2006.190.07:42:01.63#ibcon#wrote, iclass 14, count 0 2006.190.07:42:01.63#ibcon#about to read 3, iclass 14, count 0 2006.190.07:42:01.66#ibcon#read 3, iclass 14, count 0 2006.190.07:42:01.66#ibcon#about to read 4, iclass 14, count 0 2006.190.07:42:01.66#ibcon#read 4, iclass 14, count 0 2006.190.07:42:01.66#ibcon#about to read 5, iclass 14, count 0 2006.190.07:42:01.66#ibcon#read 5, iclass 14, count 0 2006.190.07:42:01.66#ibcon#about to read 6, iclass 14, count 0 2006.190.07:42:01.66#ibcon#read 6, iclass 14, count 0 2006.190.07:42:01.66#ibcon#end of sib2, iclass 14, count 0 2006.190.07:42:01.66#ibcon#*after write, iclass 14, count 0 2006.190.07:42:01.66#ibcon#*before return 0, iclass 14, count 0 2006.190.07:42:01.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:42:01.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:42:01.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:42:01.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:42:01.66$vc4f8/vblo=4,712.99 2006.190.07:42:01.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:42:01.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:42:01.66#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:01.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:42:01.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:42:01.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:42:01.66#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:42:01.66#ibcon#first serial, iclass 16, count 0 2006.190.07:42:01.66#ibcon#enter sib2, iclass 16, count 0 2006.190.07:42:01.66#ibcon#flushed, iclass 16, count 0 2006.190.07:42:01.66#ibcon#about to write, iclass 16, count 0 2006.190.07:42:01.66#ibcon#wrote, iclass 16, count 0 2006.190.07:42:01.66#ibcon#about to read 3, iclass 16, count 0 2006.190.07:42:01.68#ibcon#read 3, iclass 16, count 0 2006.190.07:42:01.68#ibcon#about to read 4, iclass 16, count 0 2006.190.07:42:01.68#ibcon#read 4, iclass 16, count 0 2006.190.07:42:01.68#ibcon#about to read 5, iclass 16, count 0 2006.190.07:42:01.68#ibcon#read 5, iclass 16, count 0 2006.190.07:42:01.68#ibcon#about to read 6, iclass 16, count 0 2006.190.07:42:01.68#ibcon#read 6, iclass 16, count 0 2006.190.07:42:01.68#ibcon#end of sib2, iclass 16, count 0 2006.190.07:42:01.68#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:42:01.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:42:01.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:42:01.68#ibcon#*before write, iclass 16, count 0 2006.190.07:42:01.68#ibcon#enter sib2, iclass 16, count 0 2006.190.07:42:01.68#ibcon#flushed, iclass 16, count 0 2006.190.07:42:01.68#ibcon#about to write, iclass 16, count 0 2006.190.07:42:01.68#ibcon#wrote, iclass 16, count 0 2006.190.07:42:01.68#ibcon#about to read 3, iclass 16, count 0 2006.190.07:42:01.72#ibcon#read 3, iclass 16, count 0 2006.190.07:42:01.72#ibcon#about to read 4, iclass 16, count 0 2006.190.07:42:01.72#ibcon#read 4, iclass 16, count 0 2006.190.07:42:01.72#ibcon#about to read 5, iclass 16, count 0 2006.190.07:42:01.72#ibcon#read 5, iclass 16, count 0 2006.190.07:42:01.72#ibcon#about to read 6, iclass 16, count 0 2006.190.07:42:01.72#ibcon#read 6, iclass 16, count 0 2006.190.07:42:01.72#ibcon#end of sib2, iclass 16, count 0 2006.190.07:42:01.72#ibcon#*after write, iclass 16, count 0 2006.190.07:42:01.72#ibcon#*before return 0, iclass 16, count 0 2006.190.07:42:01.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:42:01.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:42:01.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:42:01.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:42:01.72$vc4f8/vb=4,4 2006.190.07:42:01.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.07:42:01.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.07:42:01.72#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:01.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:42:01.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:42:01.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:42:01.78#ibcon#enter wrdev, iclass 18, count 2 2006.190.07:42:01.78#ibcon#first serial, iclass 18, count 2 2006.190.07:42:01.78#ibcon#enter sib2, iclass 18, count 2 2006.190.07:42:01.78#ibcon#flushed, iclass 18, count 2 2006.190.07:42:01.78#ibcon#about to write, iclass 18, count 2 2006.190.07:42:01.78#ibcon#wrote, iclass 18, count 2 2006.190.07:42:01.78#ibcon#about to read 3, iclass 18, count 2 2006.190.07:42:01.80#ibcon#read 3, iclass 18, count 2 2006.190.07:42:01.80#ibcon#about to read 4, iclass 18, count 2 2006.190.07:42:01.80#ibcon#read 4, iclass 18, count 2 2006.190.07:42:01.80#ibcon#about to read 5, iclass 18, count 2 2006.190.07:42:01.80#ibcon#read 5, iclass 18, count 2 2006.190.07:42:01.80#ibcon#about to read 6, iclass 18, count 2 2006.190.07:42:01.80#ibcon#read 6, iclass 18, count 2 2006.190.07:42:01.80#ibcon#end of sib2, iclass 18, count 2 2006.190.07:42:01.80#ibcon#*mode == 0, iclass 18, count 2 2006.190.07:42:01.80#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.07:42:01.80#ibcon#[27=AT04-04\r\n] 2006.190.07:42:01.80#ibcon#*before write, iclass 18, count 2 2006.190.07:42:01.80#ibcon#enter sib2, iclass 18, count 2 2006.190.07:42:01.80#ibcon#flushed, iclass 18, count 2 2006.190.07:42:01.80#ibcon#about to write, iclass 18, count 2 2006.190.07:42:01.80#ibcon#wrote, iclass 18, count 2 2006.190.07:42:01.80#ibcon#about to read 3, iclass 18, count 2 2006.190.07:42:01.83#ibcon#read 3, iclass 18, count 2 2006.190.07:42:01.83#ibcon#about to read 4, iclass 18, count 2 2006.190.07:42:01.83#ibcon#read 4, iclass 18, count 2 2006.190.07:42:01.83#ibcon#about to read 5, iclass 18, count 2 2006.190.07:42:01.83#ibcon#read 5, iclass 18, count 2 2006.190.07:42:01.83#ibcon#about to read 6, iclass 18, count 2 2006.190.07:42:01.83#ibcon#read 6, iclass 18, count 2 2006.190.07:42:01.83#ibcon#end of sib2, iclass 18, count 2 2006.190.07:42:01.83#ibcon#*after write, iclass 18, count 2 2006.190.07:42:01.83#ibcon#*before return 0, iclass 18, count 2 2006.190.07:42:01.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:42:01.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:42:01.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.07:42:01.83#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:01.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:42:01.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:42:01.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:42:01.95#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:42:01.95#ibcon#first serial, iclass 18, count 0 2006.190.07:42:01.95#ibcon#enter sib2, iclass 18, count 0 2006.190.07:42:01.95#ibcon#flushed, iclass 18, count 0 2006.190.07:42:01.95#ibcon#about to write, iclass 18, count 0 2006.190.07:42:01.95#ibcon#wrote, iclass 18, count 0 2006.190.07:42:01.95#ibcon#about to read 3, iclass 18, count 0 2006.190.07:42:01.97#ibcon#read 3, iclass 18, count 0 2006.190.07:42:01.97#ibcon#about to read 4, iclass 18, count 0 2006.190.07:42:01.97#ibcon#read 4, iclass 18, count 0 2006.190.07:42:01.97#ibcon#about to read 5, iclass 18, count 0 2006.190.07:42:01.97#ibcon#read 5, iclass 18, count 0 2006.190.07:42:01.97#ibcon#about to read 6, iclass 18, count 0 2006.190.07:42:01.97#ibcon#read 6, iclass 18, count 0 2006.190.07:42:01.97#ibcon#end of sib2, iclass 18, count 0 2006.190.07:42:01.97#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:42:01.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:42:01.97#ibcon#[27=USB\r\n] 2006.190.07:42:01.97#ibcon#*before write, iclass 18, count 0 2006.190.07:42:01.97#ibcon#enter sib2, iclass 18, count 0 2006.190.07:42:01.97#ibcon#flushed, iclass 18, count 0 2006.190.07:42:01.97#ibcon#about to write, iclass 18, count 0 2006.190.07:42:01.97#ibcon#wrote, iclass 18, count 0 2006.190.07:42:01.97#ibcon#about to read 3, iclass 18, count 0 2006.190.07:42:02.00#ibcon#read 3, iclass 18, count 0 2006.190.07:42:02.00#ibcon#about to read 4, iclass 18, count 0 2006.190.07:42:02.00#ibcon#read 4, iclass 18, count 0 2006.190.07:42:02.00#ibcon#about to read 5, iclass 18, count 0 2006.190.07:42:02.00#ibcon#read 5, iclass 18, count 0 2006.190.07:42:02.00#ibcon#about to read 6, iclass 18, count 0 2006.190.07:42:02.00#ibcon#read 6, iclass 18, count 0 2006.190.07:42:02.00#ibcon#end of sib2, iclass 18, count 0 2006.190.07:42:02.00#ibcon#*after write, iclass 18, count 0 2006.190.07:42:02.00#ibcon#*before return 0, iclass 18, count 0 2006.190.07:42:02.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:42:02.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:42:02.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:42:02.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:42:02.00$vc4f8/vblo=5,744.99 2006.190.07:42:02.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:42:02.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:42:02.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:02.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:42:02.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:42:02.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:42:02.00#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:42:02.00#ibcon#first serial, iclass 20, count 0 2006.190.07:42:02.00#ibcon#enter sib2, iclass 20, count 0 2006.190.07:42:02.00#ibcon#flushed, iclass 20, count 0 2006.190.07:42:02.00#ibcon#about to write, iclass 20, count 0 2006.190.07:42:02.00#ibcon#wrote, iclass 20, count 0 2006.190.07:42:02.00#ibcon#about to read 3, iclass 20, count 0 2006.190.07:42:02.02#ibcon#read 3, iclass 20, count 0 2006.190.07:42:02.02#ibcon#about to read 4, iclass 20, count 0 2006.190.07:42:02.02#ibcon#read 4, iclass 20, count 0 2006.190.07:42:02.02#ibcon#about to read 5, iclass 20, count 0 2006.190.07:42:02.02#ibcon#read 5, iclass 20, count 0 2006.190.07:42:02.02#ibcon#about to read 6, iclass 20, count 0 2006.190.07:42:02.02#ibcon#read 6, iclass 20, count 0 2006.190.07:42:02.02#ibcon#end of sib2, iclass 20, count 0 2006.190.07:42:02.02#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:42:02.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:42:02.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:42:02.02#ibcon#*before write, iclass 20, count 0 2006.190.07:42:02.02#ibcon#enter sib2, iclass 20, count 0 2006.190.07:42:02.02#ibcon#flushed, iclass 20, count 0 2006.190.07:42:02.02#ibcon#about to write, iclass 20, count 0 2006.190.07:42:02.02#ibcon#wrote, iclass 20, count 0 2006.190.07:42:02.02#ibcon#about to read 3, iclass 20, count 0 2006.190.07:42:02.06#ibcon#read 3, iclass 20, count 0 2006.190.07:42:02.06#ibcon#about to read 4, iclass 20, count 0 2006.190.07:42:02.06#ibcon#read 4, iclass 20, count 0 2006.190.07:42:02.06#ibcon#about to read 5, iclass 20, count 0 2006.190.07:42:02.06#ibcon#read 5, iclass 20, count 0 2006.190.07:42:02.06#ibcon#about to read 6, iclass 20, count 0 2006.190.07:42:02.06#ibcon#read 6, iclass 20, count 0 2006.190.07:42:02.06#ibcon#end of sib2, iclass 20, count 0 2006.190.07:42:02.06#ibcon#*after write, iclass 20, count 0 2006.190.07:42:02.06#ibcon#*before return 0, iclass 20, count 0 2006.190.07:42:02.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:42:02.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:42:02.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:42:02.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:42:02.06$vc4f8/vb=5,4 2006.190.07:42:02.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:42:02.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:42:02.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:02.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:42:02.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:42:02.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:42:02.12#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:42:02.12#ibcon#first serial, iclass 22, count 2 2006.190.07:42:02.12#ibcon#enter sib2, iclass 22, count 2 2006.190.07:42:02.12#ibcon#flushed, iclass 22, count 2 2006.190.07:42:02.12#ibcon#about to write, iclass 22, count 2 2006.190.07:42:02.12#ibcon#wrote, iclass 22, count 2 2006.190.07:42:02.12#ibcon#about to read 3, iclass 22, count 2 2006.190.07:42:02.15#ibcon#read 3, iclass 22, count 2 2006.190.07:42:02.15#ibcon#about to read 4, iclass 22, count 2 2006.190.07:42:02.15#ibcon#read 4, iclass 22, count 2 2006.190.07:42:02.15#ibcon#about to read 5, iclass 22, count 2 2006.190.07:42:02.15#ibcon#read 5, iclass 22, count 2 2006.190.07:42:02.15#ibcon#about to read 6, iclass 22, count 2 2006.190.07:42:02.15#ibcon#read 6, iclass 22, count 2 2006.190.07:42:02.15#ibcon#end of sib2, iclass 22, count 2 2006.190.07:42:02.15#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:42:02.15#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:42:02.15#ibcon#[27=AT05-04\r\n] 2006.190.07:42:02.15#ibcon#*before write, iclass 22, count 2 2006.190.07:42:02.15#ibcon#enter sib2, iclass 22, count 2 2006.190.07:42:02.15#ibcon#flushed, iclass 22, count 2 2006.190.07:42:02.15#ibcon#about to write, iclass 22, count 2 2006.190.07:42:02.15#ibcon#wrote, iclass 22, count 2 2006.190.07:42:02.15#ibcon#about to read 3, iclass 22, count 2 2006.190.07:42:02.18#ibcon#read 3, iclass 22, count 2 2006.190.07:42:02.18#ibcon#about to read 4, iclass 22, count 2 2006.190.07:42:02.18#ibcon#read 4, iclass 22, count 2 2006.190.07:42:02.18#ibcon#about to read 5, iclass 22, count 2 2006.190.07:42:02.18#ibcon#read 5, iclass 22, count 2 2006.190.07:42:02.18#ibcon#about to read 6, iclass 22, count 2 2006.190.07:42:02.18#ibcon#read 6, iclass 22, count 2 2006.190.07:42:02.18#ibcon#end of sib2, iclass 22, count 2 2006.190.07:42:02.18#ibcon#*after write, iclass 22, count 2 2006.190.07:42:02.18#ibcon#*before return 0, iclass 22, count 2 2006.190.07:42:02.18#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:42:02.18#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:42:02.18#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:42:02.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:02.18#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:42:02.30#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:42:02.30#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:42:02.30#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:42:02.30#ibcon#first serial, iclass 22, count 0 2006.190.07:42:02.30#ibcon#enter sib2, iclass 22, count 0 2006.190.07:42:02.30#ibcon#flushed, iclass 22, count 0 2006.190.07:42:02.30#ibcon#about to write, iclass 22, count 0 2006.190.07:42:02.30#ibcon#wrote, iclass 22, count 0 2006.190.07:42:02.30#ibcon#about to read 3, iclass 22, count 0 2006.190.07:42:02.32#ibcon#read 3, iclass 22, count 0 2006.190.07:42:02.32#ibcon#about to read 4, iclass 22, count 0 2006.190.07:42:02.32#ibcon#read 4, iclass 22, count 0 2006.190.07:42:02.32#ibcon#about to read 5, iclass 22, count 0 2006.190.07:42:02.32#ibcon#read 5, iclass 22, count 0 2006.190.07:42:02.32#ibcon#about to read 6, iclass 22, count 0 2006.190.07:42:02.32#ibcon#read 6, iclass 22, count 0 2006.190.07:42:02.32#ibcon#end of sib2, iclass 22, count 0 2006.190.07:42:02.32#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:42:02.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:42:02.32#ibcon#[27=USB\r\n] 2006.190.07:42:02.32#ibcon#*before write, iclass 22, count 0 2006.190.07:42:02.32#ibcon#enter sib2, iclass 22, count 0 2006.190.07:42:02.32#ibcon#flushed, iclass 22, count 0 2006.190.07:42:02.32#ibcon#about to write, iclass 22, count 0 2006.190.07:42:02.32#ibcon#wrote, iclass 22, count 0 2006.190.07:42:02.32#ibcon#about to read 3, iclass 22, count 0 2006.190.07:42:02.35#ibcon#read 3, iclass 22, count 0 2006.190.07:42:02.35#ibcon#about to read 4, iclass 22, count 0 2006.190.07:42:02.35#ibcon#read 4, iclass 22, count 0 2006.190.07:42:02.35#ibcon#about to read 5, iclass 22, count 0 2006.190.07:42:02.35#ibcon#read 5, iclass 22, count 0 2006.190.07:42:02.35#ibcon#about to read 6, iclass 22, count 0 2006.190.07:42:02.35#ibcon#read 6, iclass 22, count 0 2006.190.07:42:02.35#ibcon#end of sib2, iclass 22, count 0 2006.190.07:42:02.35#ibcon#*after write, iclass 22, count 0 2006.190.07:42:02.35#ibcon#*before return 0, iclass 22, count 0 2006.190.07:42:02.35#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:42:02.35#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:42:02.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:42:02.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:42:02.35$vc4f8/vblo=6,752.99 2006.190.07:42:02.35#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.07:42:02.35#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.07:42:02.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:42:02.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:42:02.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:42:02.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:42:02.35#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:42:02.35#ibcon#first serial, iclass 24, count 0 2006.190.07:42:02.35#ibcon#enter sib2, iclass 24, count 0 2006.190.07:42:02.35#ibcon#flushed, iclass 24, count 0 2006.190.07:42:02.35#ibcon#about to write, iclass 24, count 0 2006.190.07:42:02.35#ibcon#wrote, iclass 24, count 0 2006.190.07:42:02.35#ibcon#about to read 3, iclass 24, count 0 2006.190.07:42:02.37#ibcon#read 3, iclass 24, count 0 2006.190.07:42:02.37#ibcon#about to read 4, iclass 24, count 0 2006.190.07:42:02.37#ibcon#read 4, iclass 24, count 0 2006.190.07:42:02.37#ibcon#about to read 5, iclass 24, count 0 2006.190.07:42:02.37#ibcon#read 5, iclass 24, count 0 2006.190.07:42:02.37#ibcon#about to read 6, iclass 24, count 0 2006.190.07:42:02.37#ibcon#read 6, iclass 24, count 0 2006.190.07:42:02.37#ibcon#end of sib2, iclass 24, count 0 2006.190.07:42:02.37#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:42:02.37#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:42:02.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:42:02.37#ibcon#*before write, iclass 24, count 0 2006.190.07:42:02.37#ibcon#enter sib2, iclass 24, count 0 2006.190.07:42:02.37#ibcon#flushed, iclass 24, count 0 2006.190.07:42:02.37#ibcon#about to write, iclass 24, count 0 2006.190.07:42:02.37#ibcon#wrote, iclass 24, count 0 2006.190.07:42:02.37#ibcon#about to read 3, iclass 24, count 0 2006.190.07:42:02.41#ibcon#read 3, iclass 24, count 0 2006.190.07:42:02.41#ibcon#about to read 4, iclass 24, count 0 2006.190.07:42:02.41#ibcon#read 4, iclass 24, count 0 2006.190.07:42:02.41#ibcon#about to read 5, iclass 24, count 0 2006.190.07:42:02.41#ibcon#read 5, iclass 24, count 0 2006.190.07:42:02.41#ibcon#about to read 6, iclass 24, count 0 2006.190.07:42:02.41#ibcon#read 6, iclass 24, count 0 2006.190.07:42:02.41#ibcon#end of sib2, iclass 24, count 0 2006.190.07:42:02.41#ibcon#*after write, iclass 24, count 0 2006.190.07:42:02.41#ibcon#*before return 0, iclass 24, count 0 2006.190.07:42:02.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:42:02.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:42:02.41#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:42:02.41#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:42:02.41$vc4f8/vb=6,4 2006.190.07:42:02.41#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.07:42:02.41#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.07:42:02.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:42:02.41#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:42:02.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:42:02.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:42:02.47#ibcon#enter wrdev, iclass 26, count 2 2006.190.07:42:02.47#ibcon#first serial, iclass 26, count 2 2006.190.07:42:02.47#ibcon#enter sib2, iclass 26, count 2 2006.190.07:42:02.47#ibcon#flushed, iclass 26, count 2 2006.190.07:42:02.47#ibcon#about to write, iclass 26, count 2 2006.190.07:42:02.47#ibcon#wrote, iclass 26, count 2 2006.190.07:42:02.47#ibcon#about to read 3, iclass 26, count 2 2006.190.07:42:02.49#ibcon#read 3, iclass 26, count 2 2006.190.07:42:02.49#ibcon#about to read 4, iclass 26, count 2 2006.190.07:42:02.49#ibcon#read 4, iclass 26, count 2 2006.190.07:42:02.49#ibcon#about to read 5, iclass 26, count 2 2006.190.07:42:02.49#ibcon#read 5, iclass 26, count 2 2006.190.07:42:02.49#ibcon#about to read 6, iclass 26, count 2 2006.190.07:42:02.49#ibcon#read 6, iclass 26, count 2 2006.190.07:42:02.49#ibcon#end of sib2, iclass 26, count 2 2006.190.07:42:02.49#ibcon#*mode == 0, iclass 26, count 2 2006.190.07:42:02.49#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.07:42:02.49#ibcon#[27=AT06-04\r\n] 2006.190.07:42:02.49#ibcon#*before write, iclass 26, count 2 2006.190.07:42:02.49#ibcon#enter sib2, iclass 26, count 2 2006.190.07:42:02.49#ibcon#flushed, iclass 26, count 2 2006.190.07:42:02.49#ibcon#about to write, iclass 26, count 2 2006.190.07:42:02.49#ibcon#wrote, iclass 26, count 2 2006.190.07:42:02.49#ibcon#about to read 3, iclass 26, count 2 2006.190.07:42:02.52#ibcon#read 3, iclass 26, count 2 2006.190.07:42:02.52#ibcon#about to read 4, iclass 26, count 2 2006.190.07:42:02.52#ibcon#read 4, iclass 26, count 2 2006.190.07:42:02.52#ibcon#about to read 5, iclass 26, count 2 2006.190.07:42:02.52#ibcon#read 5, iclass 26, count 2 2006.190.07:42:02.52#ibcon#about to read 6, iclass 26, count 2 2006.190.07:42:02.52#ibcon#read 6, iclass 26, count 2 2006.190.07:42:02.52#ibcon#end of sib2, iclass 26, count 2 2006.190.07:42:02.52#ibcon#*after write, iclass 26, count 2 2006.190.07:42:02.52#ibcon#*before return 0, iclass 26, count 2 2006.190.07:42:02.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:42:02.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:42:02.52#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.07:42:02.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:42:02.52#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:42:02.64#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:42:02.64#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:42:02.64#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:42:02.64#ibcon#first serial, iclass 26, count 0 2006.190.07:42:02.64#ibcon#enter sib2, iclass 26, count 0 2006.190.07:42:02.64#ibcon#flushed, iclass 26, count 0 2006.190.07:42:02.64#ibcon#about to write, iclass 26, count 0 2006.190.07:42:02.64#ibcon#wrote, iclass 26, count 0 2006.190.07:42:02.64#ibcon#about to read 3, iclass 26, count 0 2006.190.07:42:02.66#ibcon#read 3, iclass 26, count 0 2006.190.07:42:02.66#ibcon#about to read 4, iclass 26, count 0 2006.190.07:42:02.66#ibcon#read 4, iclass 26, count 0 2006.190.07:42:02.66#ibcon#about to read 5, iclass 26, count 0 2006.190.07:42:02.66#ibcon#read 5, iclass 26, count 0 2006.190.07:42:02.66#ibcon#about to read 6, iclass 26, count 0 2006.190.07:42:02.66#ibcon#read 6, iclass 26, count 0 2006.190.07:42:02.66#ibcon#end of sib2, iclass 26, count 0 2006.190.07:42:02.66#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:42:02.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:42:02.66#ibcon#[27=USB\r\n] 2006.190.07:42:02.66#ibcon#*before write, iclass 26, count 0 2006.190.07:42:02.66#ibcon#enter sib2, iclass 26, count 0 2006.190.07:42:02.66#ibcon#flushed, iclass 26, count 0 2006.190.07:42:02.66#ibcon#about to write, iclass 26, count 0 2006.190.07:42:02.66#ibcon#wrote, iclass 26, count 0 2006.190.07:42:02.66#ibcon#about to read 3, iclass 26, count 0 2006.190.07:42:02.69#ibcon#read 3, iclass 26, count 0 2006.190.07:42:02.69#ibcon#about to read 4, iclass 26, count 0 2006.190.07:42:02.69#ibcon#read 4, iclass 26, count 0 2006.190.07:42:02.69#ibcon#about to read 5, iclass 26, count 0 2006.190.07:42:02.69#ibcon#read 5, iclass 26, count 0 2006.190.07:42:02.69#ibcon#about to read 6, iclass 26, count 0 2006.190.07:42:02.69#ibcon#read 6, iclass 26, count 0 2006.190.07:42:02.69#ibcon#end of sib2, iclass 26, count 0 2006.190.07:42:02.69#ibcon#*after write, iclass 26, count 0 2006.190.07:42:02.69#ibcon#*before return 0, iclass 26, count 0 2006.190.07:42:02.69#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:42:02.69#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:42:02.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:42:02.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:42:02.69$vc4f8/vabw=wide 2006.190.07:42:02.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:42:02.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:42:02.69#ibcon#ireg 8 cls_cnt 0 2006.190.07:42:02.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:42:02.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:42:02.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:42:02.69#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:42:02.69#ibcon#first serial, iclass 28, count 0 2006.190.07:42:02.69#ibcon#enter sib2, iclass 28, count 0 2006.190.07:42:02.69#ibcon#flushed, iclass 28, count 0 2006.190.07:42:02.69#ibcon#about to write, iclass 28, count 0 2006.190.07:42:02.69#ibcon#wrote, iclass 28, count 0 2006.190.07:42:02.69#ibcon#about to read 3, iclass 28, count 0 2006.190.07:42:02.71#ibcon#read 3, iclass 28, count 0 2006.190.07:42:02.71#ibcon#about to read 4, iclass 28, count 0 2006.190.07:42:02.71#ibcon#read 4, iclass 28, count 0 2006.190.07:42:02.71#ibcon#about to read 5, iclass 28, count 0 2006.190.07:42:02.71#ibcon#read 5, iclass 28, count 0 2006.190.07:42:02.71#ibcon#about to read 6, iclass 28, count 0 2006.190.07:42:02.71#ibcon#read 6, iclass 28, count 0 2006.190.07:42:02.71#ibcon#end of sib2, iclass 28, count 0 2006.190.07:42:02.71#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:42:02.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:42:02.71#ibcon#[25=BW32\r\n] 2006.190.07:42:02.71#ibcon#*before write, iclass 28, count 0 2006.190.07:42:02.71#ibcon#enter sib2, iclass 28, count 0 2006.190.07:42:02.71#ibcon#flushed, iclass 28, count 0 2006.190.07:42:02.71#ibcon#about to write, iclass 28, count 0 2006.190.07:42:02.71#ibcon#wrote, iclass 28, count 0 2006.190.07:42:02.71#ibcon#about to read 3, iclass 28, count 0 2006.190.07:42:02.74#ibcon#read 3, iclass 28, count 0 2006.190.07:42:02.74#ibcon#about to read 4, iclass 28, count 0 2006.190.07:42:02.74#ibcon#read 4, iclass 28, count 0 2006.190.07:42:02.74#ibcon#about to read 5, iclass 28, count 0 2006.190.07:42:02.74#ibcon#read 5, iclass 28, count 0 2006.190.07:42:02.74#ibcon#about to read 6, iclass 28, count 0 2006.190.07:42:02.74#ibcon#read 6, iclass 28, count 0 2006.190.07:42:02.74#ibcon#end of sib2, iclass 28, count 0 2006.190.07:42:02.74#ibcon#*after write, iclass 28, count 0 2006.190.07:42:02.74#ibcon#*before return 0, iclass 28, count 0 2006.190.07:42:02.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:42:02.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:42:02.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:42:02.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:42:02.74$vc4f8/vbbw=wide 2006.190.07:42:02.74#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.07:42:02.74#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.07:42:02.74#ibcon#ireg 8 cls_cnt 0 2006.190.07:42:02.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:42:02.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:42:02.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:42:02.81#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:42:02.81#ibcon#first serial, iclass 30, count 0 2006.190.07:42:02.81#ibcon#enter sib2, iclass 30, count 0 2006.190.07:42:02.81#ibcon#flushed, iclass 30, count 0 2006.190.07:42:02.81#ibcon#about to write, iclass 30, count 0 2006.190.07:42:02.81#ibcon#wrote, iclass 30, count 0 2006.190.07:42:02.81#ibcon#about to read 3, iclass 30, count 0 2006.190.07:42:02.83#ibcon#read 3, iclass 30, count 0 2006.190.07:42:02.83#ibcon#about to read 4, iclass 30, count 0 2006.190.07:42:02.83#ibcon#read 4, iclass 30, count 0 2006.190.07:42:02.83#ibcon#about to read 5, iclass 30, count 0 2006.190.07:42:02.83#ibcon#read 5, iclass 30, count 0 2006.190.07:42:02.83#ibcon#about to read 6, iclass 30, count 0 2006.190.07:42:02.83#ibcon#read 6, iclass 30, count 0 2006.190.07:42:02.83#ibcon#end of sib2, iclass 30, count 0 2006.190.07:42:02.83#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:42:02.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:42:02.83#ibcon#[27=BW32\r\n] 2006.190.07:42:02.83#ibcon#*before write, iclass 30, count 0 2006.190.07:42:02.83#ibcon#enter sib2, iclass 30, count 0 2006.190.07:42:02.83#ibcon#flushed, iclass 30, count 0 2006.190.07:42:02.83#ibcon#about to write, iclass 30, count 0 2006.190.07:42:02.83#ibcon#wrote, iclass 30, count 0 2006.190.07:42:02.83#ibcon#about to read 3, iclass 30, count 0 2006.190.07:42:02.86#ibcon#read 3, iclass 30, count 0 2006.190.07:42:02.86#ibcon#about to read 4, iclass 30, count 0 2006.190.07:42:02.86#ibcon#read 4, iclass 30, count 0 2006.190.07:42:02.86#ibcon#about to read 5, iclass 30, count 0 2006.190.07:42:02.86#ibcon#read 5, iclass 30, count 0 2006.190.07:42:02.86#ibcon#about to read 6, iclass 30, count 0 2006.190.07:42:02.86#ibcon#read 6, iclass 30, count 0 2006.190.07:42:02.86#ibcon#end of sib2, iclass 30, count 0 2006.190.07:42:02.86#ibcon#*after write, iclass 30, count 0 2006.190.07:42:02.86#ibcon#*before return 0, iclass 30, count 0 2006.190.07:42:02.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:42:02.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:42:02.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:42:02.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:42:02.86$4f8m12a/ifd4f 2006.190.07:42:02.86$ifd4f/lo= 2006.190.07:42:02.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:42:02.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:42:02.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:42:02.86$ifd4f/patch= 2006.190.07:42:02.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:42:02.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:42:02.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:42:02.86$4f8m12a/"form=m,16.000,1:2 2006.190.07:42:02.86$4f8m12a/"tpicd 2006.190.07:42:02.86$4f8m12a/echo=off 2006.190.07:42:02.86$4f8m12a/xlog=off 2006.190.07:42:02.86:!2006.190.07:42:30 2006.190.07:42:15.14#trakl#Source acquired 2006.190.07:42:15.14#flagr#flagr/antenna,acquired 2006.190.07:42:30.00:preob 2006.190.07:42:31.14/onsource/TRACKING 2006.190.07:42:31.14:!2006.190.07:42:40 2006.190.07:42:40.00:data_valid=on 2006.190.07:42:40.00:midob 2006.190.07:42:40.14/onsource/TRACKING 2006.190.07:42:40.14/wx/24.51,1012.2,100 2006.190.07:42:40.26/cable/+6.4712E-03 2006.190.07:42:41.35/va/01,08,usb,yes,35,37 2006.190.07:42:41.35/va/02,07,usb,yes,36,38 2006.190.07:42:41.35/va/03,06,usb,yes,38,38 2006.190.07:42:41.35/va/04,07,usb,yes,37,40 2006.190.07:42:41.35/va/05,07,usb,yes,41,43 2006.190.07:42:41.35/va/06,06,usb,yes,40,40 2006.190.07:42:41.35/va/07,06,usb,yes,41,40 2006.190.07:42:41.35/va/08,06,usb,yes,43,42 2006.190.07:42:41.58/valo/01,532.99,yes,locked 2006.190.07:42:41.58/valo/02,572.99,yes,locked 2006.190.07:42:41.58/valo/03,672.99,yes,locked 2006.190.07:42:41.58/valo/04,832.99,yes,locked 2006.190.07:42:41.58/valo/05,652.99,yes,locked 2006.190.07:42:41.58/valo/06,772.99,yes,locked 2006.190.07:42:41.58/valo/07,832.99,yes,locked 2006.190.07:42:41.58/valo/08,852.99,yes,locked 2006.190.07:42:42.67/vb/01,04,usb,yes,29,28 2006.190.07:42:42.67/vb/02,04,usb,yes,31,32 2006.190.07:42:42.67/vb/03,04,usb,yes,27,31 2006.190.07:42:42.67/vb/04,04,usb,yes,28,28 2006.190.07:42:42.67/vb/05,04,usb,yes,27,30 2006.190.07:42:42.67/vb/06,04,usb,yes,27,30 2006.190.07:42:42.67/vb/07,04,usb,yes,29,29 2006.190.07:42:42.67/vb/08,04,usb,yes,27,30 2006.190.07:42:42.90/vblo/01,632.99,yes,locked 2006.190.07:42:42.90/vblo/02,640.99,yes,locked 2006.190.07:42:42.90/vblo/03,656.99,yes,locked 2006.190.07:42:42.90/vblo/04,712.99,yes,locked 2006.190.07:42:42.90/vblo/05,744.99,yes,locked 2006.190.07:42:42.90/vblo/06,752.99,yes,locked 2006.190.07:42:42.90/vblo/07,734.99,yes,locked 2006.190.07:42:42.90/vblo/08,744.99,yes,locked 2006.190.07:42:43.05/vabw/8 2006.190.07:42:43.20/vbbw/8 2006.190.07:42:43.29/xfe/off,on,14.7 2006.190.07:42:43.66/ifatt/23,28,28,28 2006.190.07:42:44.07/fmout-gps/S +2.84E-07 2006.190.07:42:44.15:!2006.190.07:43:40 2006.190.07:43:40.01:data_valid=off 2006.190.07:43:40.01:postob 2006.190.07:43:40.09/cable/+6.4700E-03 2006.190.07:43:40.09/wx/24.51,1012.2,100 2006.190.07:43:41.07/fmout-gps/S +2.86E-07 2006.190.07:43:41.07:scan_name=190-0744,k06190,60 2006.190.07:43:41.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.190.07:43:41.14#flagr#flagr/antenna,new-source 2006.190.07:43:42.14:checkk5 2006.190.07:43:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:43:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:43:43.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:43:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:43:44.05/chk_obsdata//k5ts1/T1900742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:43:44.43/chk_obsdata//k5ts2/T1900742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:43:44.80/chk_obsdata//k5ts3/T1900742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:43:45.18/chk_obsdata//k5ts4/T1900742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:43:45.88/k5log//k5ts1_log_newline 2006.190.07:43:46.58/k5log//k5ts2_log_newline 2006.190.07:43:47.28/k5log//k5ts3_log_newline 2006.190.07:43:47.97/k5log//k5ts4_log_newline 2006.190.07:43:47.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:43:47.99:4f8m12a=1 2006.190.07:43:47.99$4f8m12a/echo=on 2006.190.07:43:47.99$4f8m12a/pcalon 2006.190.07:43:47.99$pcalon/"no phase cal control is implemented here 2006.190.07:43:47.99$4f8m12a/"tpicd=stop 2006.190.07:43:47.99$4f8m12a/vc4f8 2006.190.07:43:47.99$vc4f8/valo=1,532.99 2006.190.07:43:47.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.07:43:47.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.07:43:47.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:47.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:47.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:47.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:47.99#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:43:47.99#ibcon#first serial, iclass 37, count 0 2006.190.07:43:47.99#ibcon#enter sib2, iclass 37, count 0 2006.190.07:43:47.99#ibcon#flushed, iclass 37, count 0 2006.190.07:43:47.99#ibcon#about to write, iclass 37, count 0 2006.190.07:43:47.99#ibcon#wrote, iclass 37, count 0 2006.190.07:43:47.99#ibcon#about to read 3, iclass 37, count 0 2006.190.07:43:48.01#ibcon#read 3, iclass 37, count 0 2006.190.07:43:48.01#ibcon#about to read 4, iclass 37, count 0 2006.190.07:43:48.01#ibcon#read 4, iclass 37, count 0 2006.190.07:43:48.01#ibcon#about to read 5, iclass 37, count 0 2006.190.07:43:48.01#ibcon#read 5, iclass 37, count 0 2006.190.07:43:48.01#ibcon#about to read 6, iclass 37, count 0 2006.190.07:43:48.01#ibcon#read 6, iclass 37, count 0 2006.190.07:43:48.01#ibcon#end of sib2, iclass 37, count 0 2006.190.07:43:48.01#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:43:48.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:43:48.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:43:48.01#ibcon#*before write, iclass 37, count 0 2006.190.07:43:48.01#ibcon#enter sib2, iclass 37, count 0 2006.190.07:43:48.01#ibcon#flushed, iclass 37, count 0 2006.190.07:43:48.01#ibcon#about to write, iclass 37, count 0 2006.190.07:43:48.01#ibcon#wrote, iclass 37, count 0 2006.190.07:43:48.01#ibcon#about to read 3, iclass 37, count 0 2006.190.07:43:48.06#ibcon#read 3, iclass 37, count 0 2006.190.07:43:48.06#ibcon#about to read 4, iclass 37, count 0 2006.190.07:43:48.06#ibcon#read 4, iclass 37, count 0 2006.190.07:43:48.06#ibcon#about to read 5, iclass 37, count 0 2006.190.07:43:48.06#ibcon#read 5, iclass 37, count 0 2006.190.07:43:48.06#ibcon#about to read 6, iclass 37, count 0 2006.190.07:43:48.06#ibcon#read 6, iclass 37, count 0 2006.190.07:43:48.06#ibcon#end of sib2, iclass 37, count 0 2006.190.07:43:48.06#ibcon#*after write, iclass 37, count 0 2006.190.07:43:48.06#ibcon#*before return 0, iclass 37, count 0 2006.190.07:43:48.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:48.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:48.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:43:48.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:43:48.06$vc4f8/va=1,8 2006.190.07:43:48.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.07:43:48.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.07:43:48.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:48.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:48.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:48.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:48.06#ibcon#enter wrdev, iclass 39, count 2 2006.190.07:43:48.06#ibcon#first serial, iclass 39, count 2 2006.190.07:43:48.06#ibcon#enter sib2, iclass 39, count 2 2006.190.07:43:48.06#ibcon#flushed, iclass 39, count 2 2006.190.07:43:48.06#ibcon#about to write, iclass 39, count 2 2006.190.07:43:48.06#ibcon#wrote, iclass 39, count 2 2006.190.07:43:48.06#ibcon#about to read 3, iclass 39, count 2 2006.190.07:43:48.08#ibcon#read 3, iclass 39, count 2 2006.190.07:43:48.08#ibcon#about to read 4, iclass 39, count 2 2006.190.07:43:48.08#ibcon#read 4, iclass 39, count 2 2006.190.07:43:48.08#ibcon#about to read 5, iclass 39, count 2 2006.190.07:43:48.08#ibcon#read 5, iclass 39, count 2 2006.190.07:43:48.08#ibcon#about to read 6, iclass 39, count 2 2006.190.07:43:48.08#ibcon#read 6, iclass 39, count 2 2006.190.07:43:48.08#ibcon#end of sib2, iclass 39, count 2 2006.190.07:43:48.08#ibcon#*mode == 0, iclass 39, count 2 2006.190.07:43:48.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.07:43:48.08#ibcon#[25=AT01-08\r\n] 2006.190.07:43:48.08#ibcon#*before write, iclass 39, count 2 2006.190.07:43:48.08#ibcon#enter sib2, iclass 39, count 2 2006.190.07:43:48.08#ibcon#flushed, iclass 39, count 2 2006.190.07:43:48.08#ibcon#about to write, iclass 39, count 2 2006.190.07:43:48.08#ibcon#wrote, iclass 39, count 2 2006.190.07:43:48.08#ibcon#about to read 3, iclass 39, count 2 2006.190.07:43:48.11#ibcon#read 3, iclass 39, count 2 2006.190.07:43:48.11#ibcon#about to read 4, iclass 39, count 2 2006.190.07:43:48.11#ibcon#read 4, iclass 39, count 2 2006.190.07:43:48.11#ibcon#about to read 5, iclass 39, count 2 2006.190.07:43:48.11#ibcon#read 5, iclass 39, count 2 2006.190.07:43:48.11#ibcon#about to read 6, iclass 39, count 2 2006.190.07:43:48.11#ibcon#read 6, iclass 39, count 2 2006.190.07:43:48.11#ibcon#end of sib2, iclass 39, count 2 2006.190.07:43:48.11#ibcon#*after write, iclass 39, count 2 2006.190.07:43:48.11#ibcon#*before return 0, iclass 39, count 2 2006.190.07:43:48.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:48.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:48.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.07:43:48.11#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:48.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:48.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:48.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:48.23#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:43:48.23#ibcon#first serial, iclass 39, count 0 2006.190.07:43:48.23#ibcon#enter sib2, iclass 39, count 0 2006.190.07:43:48.23#ibcon#flushed, iclass 39, count 0 2006.190.07:43:48.23#ibcon#about to write, iclass 39, count 0 2006.190.07:43:48.23#ibcon#wrote, iclass 39, count 0 2006.190.07:43:48.23#ibcon#about to read 3, iclass 39, count 0 2006.190.07:43:48.25#ibcon#read 3, iclass 39, count 0 2006.190.07:43:48.25#ibcon#about to read 4, iclass 39, count 0 2006.190.07:43:48.25#ibcon#read 4, iclass 39, count 0 2006.190.07:43:48.25#ibcon#about to read 5, iclass 39, count 0 2006.190.07:43:48.25#ibcon#read 5, iclass 39, count 0 2006.190.07:43:48.25#ibcon#about to read 6, iclass 39, count 0 2006.190.07:43:48.25#ibcon#read 6, iclass 39, count 0 2006.190.07:43:48.25#ibcon#end of sib2, iclass 39, count 0 2006.190.07:43:48.25#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:43:48.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:43:48.25#ibcon#[25=USB\r\n] 2006.190.07:43:48.25#ibcon#*before write, iclass 39, count 0 2006.190.07:43:48.25#ibcon#enter sib2, iclass 39, count 0 2006.190.07:43:48.25#ibcon#flushed, iclass 39, count 0 2006.190.07:43:48.25#ibcon#about to write, iclass 39, count 0 2006.190.07:43:48.26#ibcon#wrote, iclass 39, count 0 2006.190.07:43:48.26#ibcon#about to read 3, iclass 39, count 0 2006.190.07:43:48.29#ibcon#read 3, iclass 39, count 0 2006.190.07:43:48.29#ibcon#about to read 4, iclass 39, count 0 2006.190.07:43:48.29#ibcon#read 4, iclass 39, count 0 2006.190.07:43:48.29#ibcon#about to read 5, iclass 39, count 0 2006.190.07:43:48.29#ibcon#read 5, iclass 39, count 0 2006.190.07:43:48.29#ibcon#about to read 6, iclass 39, count 0 2006.190.07:43:48.29#ibcon#read 6, iclass 39, count 0 2006.190.07:43:48.29#ibcon#end of sib2, iclass 39, count 0 2006.190.07:43:48.29#ibcon#*after write, iclass 39, count 0 2006.190.07:43:48.29#ibcon#*before return 0, iclass 39, count 0 2006.190.07:43:48.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:48.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:48.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:43:48.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:43:48.29$vc4f8/valo=2,572.99 2006.190.07:43:48.29#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.07:43:48.29#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.07:43:48.29#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:48.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:48.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:48.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:48.29#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:43:48.29#ibcon#first serial, iclass 3, count 0 2006.190.07:43:48.29#ibcon#enter sib2, iclass 3, count 0 2006.190.07:43:48.29#ibcon#flushed, iclass 3, count 0 2006.190.07:43:48.29#ibcon#about to write, iclass 3, count 0 2006.190.07:43:48.29#ibcon#wrote, iclass 3, count 0 2006.190.07:43:48.29#ibcon#about to read 3, iclass 3, count 0 2006.190.07:43:48.31#ibcon#read 3, iclass 3, count 0 2006.190.07:43:48.31#ibcon#about to read 4, iclass 3, count 0 2006.190.07:43:48.31#ibcon#read 4, iclass 3, count 0 2006.190.07:43:48.31#ibcon#about to read 5, iclass 3, count 0 2006.190.07:43:48.31#ibcon#read 5, iclass 3, count 0 2006.190.07:43:48.31#ibcon#about to read 6, iclass 3, count 0 2006.190.07:43:48.31#ibcon#read 6, iclass 3, count 0 2006.190.07:43:48.31#ibcon#end of sib2, iclass 3, count 0 2006.190.07:43:48.31#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:43:48.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:43:48.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:43:48.31#ibcon#*before write, iclass 3, count 0 2006.190.07:43:48.31#ibcon#enter sib2, iclass 3, count 0 2006.190.07:43:48.31#ibcon#flushed, iclass 3, count 0 2006.190.07:43:48.31#ibcon#about to write, iclass 3, count 0 2006.190.07:43:48.31#ibcon#wrote, iclass 3, count 0 2006.190.07:43:48.31#ibcon#about to read 3, iclass 3, count 0 2006.190.07:43:48.35#ibcon#read 3, iclass 3, count 0 2006.190.07:43:48.35#ibcon#about to read 4, iclass 3, count 0 2006.190.07:43:48.35#ibcon#read 4, iclass 3, count 0 2006.190.07:43:48.35#ibcon#about to read 5, iclass 3, count 0 2006.190.07:43:48.35#ibcon#read 5, iclass 3, count 0 2006.190.07:43:48.35#ibcon#about to read 6, iclass 3, count 0 2006.190.07:43:48.35#ibcon#read 6, iclass 3, count 0 2006.190.07:43:48.35#ibcon#end of sib2, iclass 3, count 0 2006.190.07:43:48.35#ibcon#*after write, iclass 3, count 0 2006.190.07:43:48.35#ibcon#*before return 0, iclass 3, count 0 2006.190.07:43:48.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:48.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:48.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:43:48.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:43:48.35$vc4f8/va=2,7 2006.190.07:43:48.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.07:43:48.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.07:43:48.35#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:48.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:48.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:48.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:48.41#ibcon#enter wrdev, iclass 5, count 2 2006.190.07:43:48.41#ibcon#first serial, iclass 5, count 2 2006.190.07:43:48.41#ibcon#enter sib2, iclass 5, count 2 2006.190.07:43:48.41#ibcon#flushed, iclass 5, count 2 2006.190.07:43:48.41#ibcon#about to write, iclass 5, count 2 2006.190.07:43:48.41#ibcon#wrote, iclass 5, count 2 2006.190.07:43:48.41#ibcon#about to read 3, iclass 5, count 2 2006.190.07:43:48.43#ibcon#read 3, iclass 5, count 2 2006.190.07:43:48.43#ibcon#about to read 4, iclass 5, count 2 2006.190.07:43:48.43#ibcon#read 4, iclass 5, count 2 2006.190.07:43:48.43#ibcon#about to read 5, iclass 5, count 2 2006.190.07:43:48.43#ibcon#read 5, iclass 5, count 2 2006.190.07:43:48.43#ibcon#about to read 6, iclass 5, count 2 2006.190.07:43:48.43#ibcon#read 6, iclass 5, count 2 2006.190.07:43:48.43#ibcon#end of sib2, iclass 5, count 2 2006.190.07:43:48.43#ibcon#*mode == 0, iclass 5, count 2 2006.190.07:43:48.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.07:43:48.43#ibcon#[25=AT02-07\r\n] 2006.190.07:43:48.43#ibcon#*before write, iclass 5, count 2 2006.190.07:43:48.43#ibcon#enter sib2, iclass 5, count 2 2006.190.07:43:48.43#ibcon#flushed, iclass 5, count 2 2006.190.07:43:48.43#ibcon#about to write, iclass 5, count 2 2006.190.07:43:48.43#ibcon#wrote, iclass 5, count 2 2006.190.07:43:48.43#ibcon#about to read 3, iclass 5, count 2 2006.190.07:43:48.46#ibcon#read 3, iclass 5, count 2 2006.190.07:43:48.46#ibcon#about to read 4, iclass 5, count 2 2006.190.07:43:48.46#ibcon#read 4, iclass 5, count 2 2006.190.07:43:48.46#ibcon#about to read 5, iclass 5, count 2 2006.190.07:43:48.46#ibcon#read 5, iclass 5, count 2 2006.190.07:43:48.46#ibcon#about to read 6, iclass 5, count 2 2006.190.07:43:48.46#ibcon#read 6, iclass 5, count 2 2006.190.07:43:48.46#ibcon#end of sib2, iclass 5, count 2 2006.190.07:43:48.46#ibcon#*after write, iclass 5, count 2 2006.190.07:43:48.46#ibcon#*before return 0, iclass 5, count 2 2006.190.07:43:48.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:48.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:48.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.07:43:48.46#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:48.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:48.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:48.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:48.59#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:43:48.59#ibcon#first serial, iclass 5, count 0 2006.190.07:43:48.59#ibcon#enter sib2, iclass 5, count 0 2006.190.07:43:48.59#ibcon#flushed, iclass 5, count 0 2006.190.07:43:48.59#ibcon#about to write, iclass 5, count 0 2006.190.07:43:48.59#ibcon#wrote, iclass 5, count 0 2006.190.07:43:48.59#ibcon#about to read 3, iclass 5, count 0 2006.190.07:43:48.60#ibcon#read 3, iclass 5, count 0 2006.190.07:43:48.60#ibcon#about to read 4, iclass 5, count 0 2006.190.07:43:48.60#ibcon#read 4, iclass 5, count 0 2006.190.07:43:48.60#ibcon#about to read 5, iclass 5, count 0 2006.190.07:43:48.60#ibcon#read 5, iclass 5, count 0 2006.190.07:43:48.60#ibcon#about to read 6, iclass 5, count 0 2006.190.07:43:48.60#ibcon#read 6, iclass 5, count 0 2006.190.07:43:48.60#ibcon#end of sib2, iclass 5, count 0 2006.190.07:43:48.60#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:43:48.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:43:48.60#ibcon#[25=USB\r\n] 2006.190.07:43:48.60#ibcon#*before write, iclass 5, count 0 2006.190.07:43:48.60#ibcon#enter sib2, iclass 5, count 0 2006.190.07:43:48.60#ibcon#flushed, iclass 5, count 0 2006.190.07:43:48.60#ibcon#about to write, iclass 5, count 0 2006.190.07:43:48.60#ibcon#wrote, iclass 5, count 0 2006.190.07:43:48.60#ibcon#about to read 3, iclass 5, count 0 2006.190.07:43:48.63#ibcon#read 3, iclass 5, count 0 2006.190.07:43:48.63#ibcon#about to read 4, iclass 5, count 0 2006.190.07:43:48.63#ibcon#read 4, iclass 5, count 0 2006.190.07:43:48.63#ibcon#about to read 5, iclass 5, count 0 2006.190.07:43:48.63#ibcon#read 5, iclass 5, count 0 2006.190.07:43:48.63#ibcon#about to read 6, iclass 5, count 0 2006.190.07:43:48.63#ibcon#read 6, iclass 5, count 0 2006.190.07:43:48.63#ibcon#end of sib2, iclass 5, count 0 2006.190.07:43:48.63#ibcon#*after write, iclass 5, count 0 2006.190.07:43:48.63#ibcon#*before return 0, iclass 5, count 0 2006.190.07:43:48.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:48.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:48.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:43:48.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:43:48.63$vc4f8/valo=3,672.99 2006.190.07:43:48.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.07:43:48.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.07:43:48.63#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:48.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:43:48.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:43:48.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:43:48.63#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:43:48.63#ibcon#first serial, iclass 7, count 0 2006.190.07:43:48.63#ibcon#enter sib2, iclass 7, count 0 2006.190.07:43:48.63#ibcon#flushed, iclass 7, count 0 2006.190.07:43:48.63#ibcon#about to write, iclass 7, count 0 2006.190.07:43:48.63#ibcon#wrote, iclass 7, count 0 2006.190.07:43:48.63#ibcon#about to read 3, iclass 7, count 0 2006.190.07:43:48.65#ibcon#read 3, iclass 7, count 0 2006.190.07:43:48.65#ibcon#about to read 4, iclass 7, count 0 2006.190.07:43:48.65#ibcon#read 4, iclass 7, count 0 2006.190.07:43:48.65#ibcon#about to read 5, iclass 7, count 0 2006.190.07:43:48.65#ibcon#read 5, iclass 7, count 0 2006.190.07:43:48.65#ibcon#about to read 6, iclass 7, count 0 2006.190.07:43:48.65#ibcon#read 6, iclass 7, count 0 2006.190.07:43:48.65#ibcon#end of sib2, iclass 7, count 0 2006.190.07:43:48.65#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:43:48.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:43:48.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:43:48.65#ibcon#*before write, iclass 7, count 0 2006.190.07:43:48.65#ibcon#enter sib2, iclass 7, count 0 2006.190.07:43:48.65#ibcon#flushed, iclass 7, count 0 2006.190.07:43:48.65#ibcon#about to write, iclass 7, count 0 2006.190.07:43:48.65#ibcon#wrote, iclass 7, count 0 2006.190.07:43:48.65#ibcon#about to read 3, iclass 7, count 0 2006.190.07:43:48.69#ibcon#read 3, iclass 7, count 0 2006.190.07:43:48.69#ibcon#about to read 4, iclass 7, count 0 2006.190.07:43:48.69#ibcon#read 4, iclass 7, count 0 2006.190.07:43:48.69#ibcon#about to read 5, iclass 7, count 0 2006.190.07:43:48.69#ibcon#read 5, iclass 7, count 0 2006.190.07:43:48.69#ibcon#about to read 6, iclass 7, count 0 2006.190.07:43:48.69#ibcon#read 6, iclass 7, count 0 2006.190.07:43:48.69#ibcon#end of sib2, iclass 7, count 0 2006.190.07:43:48.69#ibcon#*after write, iclass 7, count 0 2006.190.07:43:48.69#ibcon#*before return 0, iclass 7, count 0 2006.190.07:43:48.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:43:48.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:43:48.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:43:48.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:43:48.69$vc4f8/va=3,6 2006.190.07:43:48.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.07:43:48.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.07:43:48.69#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:48.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:43:48.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:43:48.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:43:48.75#ibcon#enter wrdev, iclass 11, count 2 2006.190.07:43:48.75#ibcon#first serial, iclass 11, count 2 2006.190.07:43:48.75#ibcon#enter sib2, iclass 11, count 2 2006.190.07:43:48.75#ibcon#flushed, iclass 11, count 2 2006.190.07:43:48.75#ibcon#about to write, iclass 11, count 2 2006.190.07:43:48.75#ibcon#wrote, iclass 11, count 2 2006.190.07:43:48.75#ibcon#about to read 3, iclass 11, count 2 2006.190.07:43:48.77#ibcon#read 3, iclass 11, count 2 2006.190.07:43:48.77#ibcon#about to read 4, iclass 11, count 2 2006.190.07:43:48.77#ibcon#read 4, iclass 11, count 2 2006.190.07:43:48.77#ibcon#about to read 5, iclass 11, count 2 2006.190.07:43:48.77#ibcon#read 5, iclass 11, count 2 2006.190.07:43:48.77#ibcon#about to read 6, iclass 11, count 2 2006.190.07:43:48.77#ibcon#read 6, iclass 11, count 2 2006.190.07:43:48.77#ibcon#end of sib2, iclass 11, count 2 2006.190.07:43:48.77#ibcon#*mode == 0, iclass 11, count 2 2006.190.07:43:48.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.07:43:48.77#ibcon#[25=AT03-06\r\n] 2006.190.07:43:48.77#ibcon#*before write, iclass 11, count 2 2006.190.07:43:48.77#ibcon#enter sib2, iclass 11, count 2 2006.190.07:43:48.77#ibcon#flushed, iclass 11, count 2 2006.190.07:43:48.77#ibcon#about to write, iclass 11, count 2 2006.190.07:43:48.77#ibcon#wrote, iclass 11, count 2 2006.190.07:43:48.77#ibcon#about to read 3, iclass 11, count 2 2006.190.07:43:48.80#ibcon#read 3, iclass 11, count 2 2006.190.07:43:48.80#ibcon#about to read 4, iclass 11, count 2 2006.190.07:43:48.80#ibcon#read 4, iclass 11, count 2 2006.190.07:43:48.80#ibcon#about to read 5, iclass 11, count 2 2006.190.07:43:48.80#ibcon#read 5, iclass 11, count 2 2006.190.07:43:48.80#ibcon#about to read 6, iclass 11, count 2 2006.190.07:43:48.80#ibcon#read 6, iclass 11, count 2 2006.190.07:43:48.80#ibcon#end of sib2, iclass 11, count 2 2006.190.07:43:48.80#ibcon#*after write, iclass 11, count 2 2006.190.07:43:48.80#ibcon#*before return 0, iclass 11, count 2 2006.190.07:43:48.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:43:48.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:43:48.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.07:43:48.80#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:48.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:43:48.92#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:43:48.92#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:43:48.92#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:43:48.92#ibcon#first serial, iclass 11, count 0 2006.190.07:43:48.92#ibcon#enter sib2, iclass 11, count 0 2006.190.07:43:48.92#ibcon#flushed, iclass 11, count 0 2006.190.07:43:48.92#ibcon#about to write, iclass 11, count 0 2006.190.07:43:48.92#ibcon#wrote, iclass 11, count 0 2006.190.07:43:48.92#ibcon#about to read 3, iclass 11, count 0 2006.190.07:43:48.94#ibcon#read 3, iclass 11, count 0 2006.190.07:43:48.94#ibcon#about to read 4, iclass 11, count 0 2006.190.07:43:48.94#ibcon#read 4, iclass 11, count 0 2006.190.07:43:48.94#ibcon#about to read 5, iclass 11, count 0 2006.190.07:43:48.94#ibcon#read 5, iclass 11, count 0 2006.190.07:43:48.94#ibcon#about to read 6, iclass 11, count 0 2006.190.07:43:48.94#ibcon#read 6, iclass 11, count 0 2006.190.07:43:48.94#ibcon#end of sib2, iclass 11, count 0 2006.190.07:43:48.94#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:43:48.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:43:48.94#ibcon#[25=USB\r\n] 2006.190.07:43:48.94#ibcon#*before write, iclass 11, count 0 2006.190.07:43:48.94#ibcon#enter sib2, iclass 11, count 0 2006.190.07:43:48.94#ibcon#flushed, iclass 11, count 0 2006.190.07:43:48.94#ibcon#about to write, iclass 11, count 0 2006.190.07:43:48.94#ibcon#wrote, iclass 11, count 0 2006.190.07:43:48.94#ibcon#about to read 3, iclass 11, count 0 2006.190.07:43:48.97#ibcon#read 3, iclass 11, count 0 2006.190.07:43:48.97#ibcon#about to read 4, iclass 11, count 0 2006.190.07:43:48.97#ibcon#read 4, iclass 11, count 0 2006.190.07:43:48.97#ibcon#about to read 5, iclass 11, count 0 2006.190.07:43:48.97#ibcon#read 5, iclass 11, count 0 2006.190.07:43:48.97#ibcon#about to read 6, iclass 11, count 0 2006.190.07:43:48.97#ibcon#read 6, iclass 11, count 0 2006.190.07:43:48.97#ibcon#end of sib2, iclass 11, count 0 2006.190.07:43:48.97#ibcon#*after write, iclass 11, count 0 2006.190.07:43:48.97#ibcon#*before return 0, iclass 11, count 0 2006.190.07:43:48.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:43:48.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:43:48.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:43:48.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:43:48.97$vc4f8/valo=4,832.99 2006.190.07:43:48.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.07:43:48.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.07:43:48.97#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:48.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:48.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:48.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:48.97#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:43:48.97#ibcon#first serial, iclass 13, count 0 2006.190.07:43:48.97#ibcon#enter sib2, iclass 13, count 0 2006.190.07:43:48.97#ibcon#flushed, iclass 13, count 0 2006.190.07:43:48.97#ibcon#about to write, iclass 13, count 0 2006.190.07:43:48.97#ibcon#wrote, iclass 13, count 0 2006.190.07:43:48.97#ibcon#about to read 3, iclass 13, count 0 2006.190.07:43:48.99#ibcon#read 3, iclass 13, count 0 2006.190.07:43:48.99#ibcon#about to read 4, iclass 13, count 0 2006.190.07:43:48.99#ibcon#read 4, iclass 13, count 0 2006.190.07:43:48.99#ibcon#about to read 5, iclass 13, count 0 2006.190.07:43:48.99#ibcon#read 5, iclass 13, count 0 2006.190.07:43:48.99#ibcon#about to read 6, iclass 13, count 0 2006.190.07:43:48.99#ibcon#read 6, iclass 13, count 0 2006.190.07:43:48.99#ibcon#end of sib2, iclass 13, count 0 2006.190.07:43:48.99#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:43:48.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:43:48.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:43:48.99#ibcon#*before write, iclass 13, count 0 2006.190.07:43:48.99#ibcon#enter sib2, iclass 13, count 0 2006.190.07:43:48.99#ibcon#flushed, iclass 13, count 0 2006.190.07:43:48.99#ibcon#about to write, iclass 13, count 0 2006.190.07:43:48.99#ibcon#wrote, iclass 13, count 0 2006.190.07:43:48.99#ibcon#about to read 3, iclass 13, count 0 2006.190.07:43:49.03#ibcon#read 3, iclass 13, count 0 2006.190.07:43:49.03#ibcon#about to read 4, iclass 13, count 0 2006.190.07:43:49.03#ibcon#read 4, iclass 13, count 0 2006.190.07:43:49.03#ibcon#about to read 5, iclass 13, count 0 2006.190.07:43:49.03#ibcon#read 5, iclass 13, count 0 2006.190.07:43:49.03#ibcon#about to read 6, iclass 13, count 0 2006.190.07:43:49.03#ibcon#read 6, iclass 13, count 0 2006.190.07:43:49.03#ibcon#end of sib2, iclass 13, count 0 2006.190.07:43:49.03#ibcon#*after write, iclass 13, count 0 2006.190.07:43:49.03#ibcon#*before return 0, iclass 13, count 0 2006.190.07:43:49.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:49.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:49.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:43:49.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:43:49.03$vc4f8/va=4,7 2006.190.07:43:49.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.07:43:49.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.07:43:49.03#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:49.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:49.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:49.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:49.09#ibcon#enter wrdev, iclass 15, count 2 2006.190.07:43:49.09#ibcon#first serial, iclass 15, count 2 2006.190.07:43:49.09#ibcon#enter sib2, iclass 15, count 2 2006.190.07:43:49.09#ibcon#flushed, iclass 15, count 2 2006.190.07:43:49.09#ibcon#about to write, iclass 15, count 2 2006.190.07:43:49.09#ibcon#wrote, iclass 15, count 2 2006.190.07:43:49.09#ibcon#about to read 3, iclass 15, count 2 2006.190.07:43:49.11#ibcon#read 3, iclass 15, count 2 2006.190.07:43:49.11#ibcon#about to read 4, iclass 15, count 2 2006.190.07:43:49.11#ibcon#read 4, iclass 15, count 2 2006.190.07:43:49.11#ibcon#about to read 5, iclass 15, count 2 2006.190.07:43:49.11#ibcon#read 5, iclass 15, count 2 2006.190.07:43:49.11#ibcon#about to read 6, iclass 15, count 2 2006.190.07:43:49.11#ibcon#read 6, iclass 15, count 2 2006.190.07:43:49.11#ibcon#end of sib2, iclass 15, count 2 2006.190.07:43:49.11#ibcon#*mode == 0, iclass 15, count 2 2006.190.07:43:49.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.07:43:49.11#ibcon#[25=AT04-07\r\n] 2006.190.07:43:49.11#ibcon#*before write, iclass 15, count 2 2006.190.07:43:49.11#ibcon#enter sib2, iclass 15, count 2 2006.190.07:43:49.11#ibcon#flushed, iclass 15, count 2 2006.190.07:43:49.11#ibcon#about to write, iclass 15, count 2 2006.190.07:43:49.11#ibcon#wrote, iclass 15, count 2 2006.190.07:43:49.11#ibcon#about to read 3, iclass 15, count 2 2006.190.07:43:49.14#ibcon#read 3, iclass 15, count 2 2006.190.07:43:49.14#ibcon#about to read 4, iclass 15, count 2 2006.190.07:43:49.14#ibcon#read 4, iclass 15, count 2 2006.190.07:43:49.14#ibcon#about to read 5, iclass 15, count 2 2006.190.07:43:49.14#ibcon#read 5, iclass 15, count 2 2006.190.07:43:49.14#ibcon#about to read 6, iclass 15, count 2 2006.190.07:43:49.14#ibcon#read 6, iclass 15, count 2 2006.190.07:43:49.14#ibcon#end of sib2, iclass 15, count 2 2006.190.07:43:49.14#ibcon#*after write, iclass 15, count 2 2006.190.07:43:49.14#ibcon#*before return 0, iclass 15, count 2 2006.190.07:43:49.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:49.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:49.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.07:43:49.14#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:49.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:49.26#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:49.26#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:49.26#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:43:49.26#ibcon#first serial, iclass 15, count 0 2006.190.07:43:49.26#ibcon#enter sib2, iclass 15, count 0 2006.190.07:43:49.26#ibcon#flushed, iclass 15, count 0 2006.190.07:43:49.26#ibcon#about to write, iclass 15, count 0 2006.190.07:43:49.26#ibcon#wrote, iclass 15, count 0 2006.190.07:43:49.26#ibcon#about to read 3, iclass 15, count 0 2006.190.07:43:49.28#ibcon#read 3, iclass 15, count 0 2006.190.07:43:49.28#ibcon#about to read 4, iclass 15, count 0 2006.190.07:43:49.28#ibcon#read 4, iclass 15, count 0 2006.190.07:43:49.28#ibcon#about to read 5, iclass 15, count 0 2006.190.07:43:49.28#ibcon#read 5, iclass 15, count 0 2006.190.07:43:49.28#ibcon#about to read 6, iclass 15, count 0 2006.190.07:43:49.28#ibcon#read 6, iclass 15, count 0 2006.190.07:43:49.28#ibcon#end of sib2, iclass 15, count 0 2006.190.07:43:49.28#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:43:49.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:43:49.28#ibcon#[25=USB\r\n] 2006.190.07:43:49.28#ibcon#*before write, iclass 15, count 0 2006.190.07:43:49.28#ibcon#enter sib2, iclass 15, count 0 2006.190.07:43:49.28#ibcon#flushed, iclass 15, count 0 2006.190.07:43:49.28#ibcon#about to write, iclass 15, count 0 2006.190.07:43:49.28#ibcon#wrote, iclass 15, count 0 2006.190.07:43:49.28#ibcon#about to read 3, iclass 15, count 0 2006.190.07:43:49.31#ibcon#read 3, iclass 15, count 0 2006.190.07:43:49.31#ibcon#about to read 4, iclass 15, count 0 2006.190.07:43:49.31#ibcon#read 4, iclass 15, count 0 2006.190.07:43:49.31#ibcon#about to read 5, iclass 15, count 0 2006.190.07:43:49.31#ibcon#read 5, iclass 15, count 0 2006.190.07:43:49.31#ibcon#about to read 6, iclass 15, count 0 2006.190.07:43:49.31#ibcon#read 6, iclass 15, count 0 2006.190.07:43:49.31#ibcon#end of sib2, iclass 15, count 0 2006.190.07:43:49.31#ibcon#*after write, iclass 15, count 0 2006.190.07:43:49.31#ibcon#*before return 0, iclass 15, count 0 2006.190.07:43:49.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:49.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:49.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:43:49.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:43:49.31$vc4f8/valo=5,652.99 2006.190.07:43:49.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.07:43:49.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.07:43:49.31#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:49.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:49.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:49.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:49.31#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:43:49.31#ibcon#first serial, iclass 17, count 0 2006.190.07:43:49.31#ibcon#enter sib2, iclass 17, count 0 2006.190.07:43:49.31#ibcon#flushed, iclass 17, count 0 2006.190.07:43:49.31#ibcon#about to write, iclass 17, count 0 2006.190.07:43:49.31#ibcon#wrote, iclass 17, count 0 2006.190.07:43:49.31#ibcon#about to read 3, iclass 17, count 0 2006.190.07:43:49.33#ibcon#read 3, iclass 17, count 0 2006.190.07:43:49.33#ibcon#about to read 4, iclass 17, count 0 2006.190.07:43:49.33#ibcon#read 4, iclass 17, count 0 2006.190.07:43:49.33#ibcon#about to read 5, iclass 17, count 0 2006.190.07:43:49.33#ibcon#read 5, iclass 17, count 0 2006.190.07:43:49.33#ibcon#about to read 6, iclass 17, count 0 2006.190.07:43:49.33#ibcon#read 6, iclass 17, count 0 2006.190.07:43:49.33#ibcon#end of sib2, iclass 17, count 0 2006.190.07:43:49.33#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:43:49.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:43:49.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:43:49.33#ibcon#*before write, iclass 17, count 0 2006.190.07:43:49.33#ibcon#enter sib2, iclass 17, count 0 2006.190.07:43:49.33#ibcon#flushed, iclass 17, count 0 2006.190.07:43:49.33#ibcon#about to write, iclass 17, count 0 2006.190.07:43:49.33#ibcon#wrote, iclass 17, count 0 2006.190.07:43:49.33#ibcon#about to read 3, iclass 17, count 0 2006.190.07:43:49.37#ibcon#read 3, iclass 17, count 0 2006.190.07:43:49.37#ibcon#about to read 4, iclass 17, count 0 2006.190.07:43:49.37#ibcon#read 4, iclass 17, count 0 2006.190.07:43:49.37#ibcon#about to read 5, iclass 17, count 0 2006.190.07:43:49.37#ibcon#read 5, iclass 17, count 0 2006.190.07:43:49.37#ibcon#about to read 6, iclass 17, count 0 2006.190.07:43:49.37#ibcon#read 6, iclass 17, count 0 2006.190.07:43:49.37#ibcon#end of sib2, iclass 17, count 0 2006.190.07:43:49.37#ibcon#*after write, iclass 17, count 0 2006.190.07:43:49.37#ibcon#*before return 0, iclass 17, count 0 2006.190.07:43:49.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:49.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:49.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:43:49.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:43:49.37$vc4f8/va=5,7 2006.190.07:43:49.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.07:43:49.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.07:43:49.37#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:49.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:49.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:49.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:49.43#ibcon#enter wrdev, iclass 19, count 2 2006.190.07:43:49.43#ibcon#first serial, iclass 19, count 2 2006.190.07:43:49.43#ibcon#enter sib2, iclass 19, count 2 2006.190.07:43:49.43#ibcon#flushed, iclass 19, count 2 2006.190.07:43:49.43#ibcon#about to write, iclass 19, count 2 2006.190.07:43:49.43#ibcon#wrote, iclass 19, count 2 2006.190.07:43:49.43#ibcon#about to read 3, iclass 19, count 2 2006.190.07:43:49.45#ibcon#read 3, iclass 19, count 2 2006.190.07:43:49.45#ibcon#about to read 4, iclass 19, count 2 2006.190.07:43:49.45#ibcon#read 4, iclass 19, count 2 2006.190.07:43:49.45#ibcon#about to read 5, iclass 19, count 2 2006.190.07:43:49.45#ibcon#read 5, iclass 19, count 2 2006.190.07:43:49.45#ibcon#about to read 6, iclass 19, count 2 2006.190.07:43:49.45#ibcon#read 6, iclass 19, count 2 2006.190.07:43:49.45#ibcon#end of sib2, iclass 19, count 2 2006.190.07:43:49.45#ibcon#*mode == 0, iclass 19, count 2 2006.190.07:43:49.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.07:43:49.45#ibcon#[25=AT05-07\r\n] 2006.190.07:43:49.45#ibcon#*before write, iclass 19, count 2 2006.190.07:43:49.45#ibcon#enter sib2, iclass 19, count 2 2006.190.07:43:49.45#ibcon#flushed, iclass 19, count 2 2006.190.07:43:49.45#ibcon#about to write, iclass 19, count 2 2006.190.07:43:49.45#ibcon#wrote, iclass 19, count 2 2006.190.07:43:49.45#ibcon#about to read 3, iclass 19, count 2 2006.190.07:43:49.48#ibcon#read 3, iclass 19, count 2 2006.190.07:43:49.48#ibcon#about to read 4, iclass 19, count 2 2006.190.07:43:49.48#ibcon#read 4, iclass 19, count 2 2006.190.07:43:49.48#ibcon#about to read 5, iclass 19, count 2 2006.190.07:43:49.48#ibcon#read 5, iclass 19, count 2 2006.190.07:43:49.48#ibcon#about to read 6, iclass 19, count 2 2006.190.07:43:49.48#ibcon#read 6, iclass 19, count 2 2006.190.07:43:49.48#ibcon#end of sib2, iclass 19, count 2 2006.190.07:43:49.48#ibcon#*after write, iclass 19, count 2 2006.190.07:43:49.48#ibcon#*before return 0, iclass 19, count 2 2006.190.07:43:49.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:49.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:49.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.07:43:49.48#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:49.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:49.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:49.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:49.60#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:43:49.60#ibcon#first serial, iclass 19, count 0 2006.190.07:43:49.60#ibcon#enter sib2, iclass 19, count 0 2006.190.07:43:49.60#ibcon#flushed, iclass 19, count 0 2006.190.07:43:49.60#ibcon#about to write, iclass 19, count 0 2006.190.07:43:49.60#ibcon#wrote, iclass 19, count 0 2006.190.07:43:49.60#ibcon#about to read 3, iclass 19, count 0 2006.190.07:43:49.62#ibcon#read 3, iclass 19, count 0 2006.190.07:43:49.62#ibcon#about to read 4, iclass 19, count 0 2006.190.07:43:49.62#ibcon#read 4, iclass 19, count 0 2006.190.07:43:49.62#ibcon#about to read 5, iclass 19, count 0 2006.190.07:43:49.62#ibcon#read 5, iclass 19, count 0 2006.190.07:43:49.62#ibcon#about to read 6, iclass 19, count 0 2006.190.07:43:49.62#ibcon#read 6, iclass 19, count 0 2006.190.07:43:49.62#ibcon#end of sib2, iclass 19, count 0 2006.190.07:43:49.62#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:43:49.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:43:49.62#ibcon#[25=USB\r\n] 2006.190.07:43:49.62#ibcon#*before write, iclass 19, count 0 2006.190.07:43:49.62#ibcon#enter sib2, iclass 19, count 0 2006.190.07:43:49.62#ibcon#flushed, iclass 19, count 0 2006.190.07:43:49.62#ibcon#about to write, iclass 19, count 0 2006.190.07:43:49.62#ibcon#wrote, iclass 19, count 0 2006.190.07:43:49.62#ibcon#about to read 3, iclass 19, count 0 2006.190.07:43:49.65#ibcon#read 3, iclass 19, count 0 2006.190.07:43:49.65#ibcon#about to read 4, iclass 19, count 0 2006.190.07:43:49.65#ibcon#read 4, iclass 19, count 0 2006.190.07:43:49.65#ibcon#about to read 5, iclass 19, count 0 2006.190.07:43:49.65#ibcon#read 5, iclass 19, count 0 2006.190.07:43:49.65#ibcon#about to read 6, iclass 19, count 0 2006.190.07:43:49.65#ibcon#read 6, iclass 19, count 0 2006.190.07:43:49.65#ibcon#end of sib2, iclass 19, count 0 2006.190.07:43:49.65#ibcon#*after write, iclass 19, count 0 2006.190.07:43:49.65#ibcon#*before return 0, iclass 19, count 0 2006.190.07:43:49.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:49.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:49.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:43:49.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:43:49.65$vc4f8/valo=6,772.99 2006.190.07:43:49.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.07:43:49.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.07:43:49.65#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:49.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:49.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:49.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:49.65#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:43:49.65#ibcon#first serial, iclass 21, count 0 2006.190.07:43:49.65#ibcon#enter sib2, iclass 21, count 0 2006.190.07:43:49.65#ibcon#flushed, iclass 21, count 0 2006.190.07:43:49.65#ibcon#about to write, iclass 21, count 0 2006.190.07:43:49.65#ibcon#wrote, iclass 21, count 0 2006.190.07:43:49.65#ibcon#about to read 3, iclass 21, count 0 2006.190.07:43:49.67#ibcon#read 3, iclass 21, count 0 2006.190.07:43:49.67#ibcon#about to read 4, iclass 21, count 0 2006.190.07:43:49.67#ibcon#read 4, iclass 21, count 0 2006.190.07:43:49.67#ibcon#about to read 5, iclass 21, count 0 2006.190.07:43:49.67#ibcon#read 5, iclass 21, count 0 2006.190.07:43:49.67#ibcon#about to read 6, iclass 21, count 0 2006.190.07:43:49.67#ibcon#read 6, iclass 21, count 0 2006.190.07:43:49.67#ibcon#end of sib2, iclass 21, count 0 2006.190.07:43:49.67#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:43:49.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:43:49.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:43:49.67#ibcon#*before write, iclass 21, count 0 2006.190.07:43:49.67#ibcon#enter sib2, iclass 21, count 0 2006.190.07:43:49.67#ibcon#flushed, iclass 21, count 0 2006.190.07:43:49.67#ibcon#about to write, iclass 21, count 0 2006.190.07:43:49.67#ibcon#wrote, iclass 21, count 0 2006.190.07:43:49.67#ibcon#about to read 3, iclass 21, count 0 2006.190.07:43:49.71#ibcon#read 3, iclass 21, count 0 2006.190.07:43:49.71#ibcon#about to read 4, iclass 21, count 0 2006.190.07:43:49.71#ibcon#read 4, iclass 21, count 0 2006.190.07:43:49.71#ibcon#about to read 5, iclass 21, count 0 2006.190.07:43:49.71#ibcon#read 5, iclass 21, count 0 2006.190.07:43:49.71#ibcon#about to read 6, iclass 21, count 0 2006.190.07:43:49.71#ibcon#read 6, iclass 21, count 0 2006.190.07:43:49.71#ibcon#end of sib2, iclass 21, count 0 2006.190.07:43:49.71#ibcon#*after write, iclass 21, count 0 2006.190.07:43:49.71#ibcon#*before return 0, iclass 21, count 0 2006.190.07:43:49.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:49.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:49.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:43:49.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:43:49.71$vc4f8/va=6,6 2006.190.07:43:49.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.07:43:49.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.07:43:49.71#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:49.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:49.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:49.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:49.77#ibcon#enter wrdev, iclass 23, count 2 2006.190.07:43:49.77#ibcon#first serial, iclass 23, count 2 2006.190.07:43:49.77#ibcon#enter sib2, iclass 23, count 2 2006.190.07:43:49.77#ibcon#flushed, iclass 23, count 2 2006.190.07:43:49.77#ibcon#about to write, iclass 23, count 2 2006.190.07:43:49.77#ibcon#wrote, iclass 23, count 2 2006.190.07:43:49.77#ibcon#about to read 3, iclass 23, count 2 2006.190.07:43:49.79#ibcon#read 3, iclass 23, count 2 2006.190.07:43:49.79#ibcon#about to read 4, iclass 23, count 2 2006.190.07:43:49.79#ibcon#read 4, iclass 23, count 2 2006.190.07:43:49.79#ibcon#about to read 5, iclass 23, count 2 2006.190.07:43:49.79#ibcon#read 5, iclass 23, count 2 2006.190.07:43:49.79#ibcon#about to read 6, iclass 23, count 2 2006.190.07:43:49.79#ibcon#read 6, iclass 23, count 2 2006.190.07:43:49.79#ibcon#end of sib2, iclass 23, count 2 2006.190.07:43:49.79#ibcon#*mode == 0, iclass 23, count 2 2006.190.07:43:49.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.07:43:49.79#ibcon#[25=AT06-06\r\n] 2006.190.07:43:49.79#ibcon#*before write, iclass 23, count 2 2006.190.07:43:49.79#ibcon#enter sib2, iclass 23, count 2 2006.190.07:43:49.79#ibcon#flushed, iclass 23, count 2 2006.190.07:43:49.79#ibcon#about to write, iclass 23, count 2 2006.190.07:43:49.79#ibcon#wrote, iclass 23, count 2 2006.190.07:43:49.79#ibcon#about to read 3, iclass 23, count 2 2006.190.07:43:49.82#ibcon#read 3, iclass 23, count 2 2006.190.07:43:49.82#ibcon#about to read 4, iclass 23, count 2 2006.190.07:43:49.82#ibcon#read 4, iclass 23, count 2 2006.190.07:43:49.82#ibcon#about to read 5, iclass 23, count 2 2006.190.07:43:49.82#ibcon#read 5, iclass 23, count 2 2006.190.07:43:49.82#ibcon#about to read 6, iclass 23, count 2 2006.190.07:43:49.82#ibcon#read 6, iclass 23, count 2 2006.190.07:43:49.82#ibcon#end of sib2, iclass 23, count 2 2006.190.07:43:49.82#ibcon#*after write, iclass 23, count 2 2006.190.07:43:49.82#ibcon#*before return 0, iclass 23, count 2 2006.190.07:43:49.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:49.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:49.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.07:43:49.82#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:49.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:49.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:49.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:49.94#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:43:49.94#ibcon#first serial, iclass 23, count 0 2006.190.07:43:49.94#ibcon#enter sib2, iclass 23, count 0 2006.190.07:43:49.94#ibcon#flushed, iclass 23, count 0 2006.190.07:43:49.94#ibcon#about to write, iclass 23, count 0 2006.190.07:43:49.94#ibcon#wrote, iclass 23, count 0 2006.190.07:43:49.94#ibcon#about to read 3, iclass 23, count 0 2006.190.07:43:49.96#ibcon#read 3, iclass 23, count 0 2006.190.07:43:49.96#ibcon#about to read 4, iclass 23, count 0 2006.190.07:43:49.96#ibcon#read 4, iclass 23, count 0 2006.190.07:43:49.96#ibcon#about to read 5, iclass 23, count 0 2006.190.07:43:49.96#ibcon#read 5, iclass 23, count 0 2006.190.07:43:49.96#ibcon#about to read 6, iclass 23, count 0 2006.190.07:43:49.96#ibcon#read 6, iclass 23, count 0 2006.190.07:43:49.96#ibcon#end of sib2, iclass 23, count 0 2006.190.07:43:49.96#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:43:49.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:43:49.96#ibcon#[25=USB\r\n] 2006.190.07:43:49.96#ibcon#*before write, iclass 23, count 0 2006.190.07:43:49.96#ibcon#enter sib2, iclass 23, count 0 2006.190.07:43:49.96#ibcon#flushed, iclass 23, count 0 2006.190.07:43:49.96#ibcon#about to write, iclass 23, count 0 2006.190.07:43:49.96#ibcon#wrote, iclass 23, count 0 2006.190.07:43:49.96#ibcon#about to read 3, iclass 23, count 0 2006.190.07:43:49.99#ibcon#read 3, iclass 23, count 0 2006.190.07:43:49.99#ibcon#about to read 4, iclass 23, count 0 2006.190.07:43:49.99#ibcon#read 4, iclass 23, count 0 2006.190.07:43:49.99#ibcon#about to read 5, iclass 23, count 0 2006.190.07:43:49.99#ibcon#read 5, iclass 23, count 0 2006.190.07:43:49.99#ibcon#about to read 6, iclass 23, count 0 2006.190.07:43:49.99#ibcon#read 6, iclass 23, count 0 2006.190.07:43:49.99#ibcon#end of sib2, iclass 23, count 0 2006.190.07:43:49.99#ibcon#*after write, iclass 23, count 0 2006.190.07:43:49.99#ibcon#*before return 0, iclass 23, count 0 2006.190.07:43:49.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:49.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:49.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:43:49.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:43:49.99$vc4f8/valo=7,832.99 2006.190.07:43:49.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.07:43:49.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.07:43:49.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:49.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:49.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:49.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:49.99#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:43:49.99#ibcon#first serial, iclass 25, count 0 2006.190.07:43:49.99#ibcon#enter sib2, iclass 25, count 0 2006.190.07:43:49.99#ibcon#flushed, iclass 25, count 0 2006.190.07:43:49.99#ibcon#about to write, iclass 25, count 0 2006.190.07:43:49.99#ibcon#wrote, iclass 25, count 0 2006.190.07:43:49.99#ibcon#about to read 3, iclass 25, count 0 2006.190.07:43:50.01#ibcon#read 3, iclass 25, count 0 2006.190.07:43:50.01#ibcon#about to read 4, iclass 25, count 0 2006.190.07:43:50.01#ibcon#read 4, iclass 25, count 0 2006.190.07:43:50.01#ibcon#about to read 5, iclass 25, count 0 2006.190.07:43:50.01#ibcon#read 5, iclass 25, count 0 2006.190.07:43:50.01#ibcon#about to read 6, iclass 25, count 0 2006.190.07:43:50.01#ibcon#read 6, iclass 25, count 0 2006.190.07:43:50.01#ibcon#end of sib2, iclass 25, count 0 2006.190.07:43:50.01#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:43:50.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:43:50.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:43:50.01#ibcon#*before write, iclass 25, count 0 2006.190.07:43:50.01#ibcon#enter sib2, iclass 25, count 0 2006.190.07:43:50.01#ibcon#flushed, iclass 25, count 0 2006.190.07:43:50.01#ibcon#about to write, iclass 25, count 0 2006.190.07:43:50.01#ibcon#wrote, iclass 25, count 0 2006.190.07:43:50.01#ibcon#about to read 3, iclass 25, count 0 2006.190.07:43:50.05#ibcon#read 3, iclass 25, count 0 2006.190.07:43:50.05#ibcon#about to read 4, iclass 25, count 0 2006.190.07:43:50.05#ibcon#read 4, iclass 25, count 0 2006.190.07:43:50.05#ibcon#about to read 5, iclass 25, count 0 2006.190.07:43:50.05#ibcon#read 5, iclass 25, count 0 2006.190.07:43:50.05#ibcon#about to read 6, iclass 25, count 0 2006.190.07:43:50.05#ibcon#read 6, iclass 25, count 0 2006.190.07:43:50.05#ibcon#end of sib2, iclass 25, count 0 2006.190.07:43:50.05#ibcon#*after write, iclass 25, count 0 2006.190.07:43:50.05#ibcon#*before return 0, iclass 25, count 0 2006.190.07:43:50.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:50.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:50.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:43:50.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:43:50.05$vc4f8/va=7,6 2006.190.07:43:50.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.07:43:50.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.07:43:50.05#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:50.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:43:50.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:43:50.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:43:50.11#ibcon#enter wrdev, iclass 27, count 2 2006.190.07:43:50.11#ibcon#first serial, iclass 27, count 2 2006.190.07:43:50.11#ibcon#enter sib2, iclass 27, count 2 2006.190.07:43:50.11#ibcon#flushed, iclass 27, count 2 2006.190.07:43:50.11#ibcon#about to write, iclass 27, count 2 2006.190.07:43:50.11#ibcon#wrote, iclass 27, count 2 2006.190.07:43:50.11#ibcon#about to read 3, iclass 27, count 2 2006.190.07:43:50.13#ibcon#read 3, iclass 27, count 2 2006.190.07:43:50.13#ibcon#about to read 4, iclass 27, count 2 2006.190.07:43:50.13#ibcon#read 4, iclass 27, count 2 2006.190.07:43:50.13#ibcon#about to read 5, iclass 27, count 2 2006.190.07:43:50.13#ibcon#read 5, iclass 27, count 2 2006.190.07:43:50.13#ibcon#about to read 6, iclass 27, count 2 2006.190.07:43:50.13#ibcon#read 6, iclass 27, count 2 2006.190.07:43:50.13#ibcon#end of sib2, iclass 27, count 2 2006.190.07:43:50.13#ibcon#*mode == 0, iclass 27, count 2 2006.190.07:43:50.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.07:43:50.13#ibcon#[25=AT07-06\r\n] 2006.190.07:43:50.13#ibcon#*before write, iclass 27, count 2 2006.190.07:43:50.13#ibcon#enter sib2, iclass 27, count 2 2006.190.07:43:50.13#ibcon#flushed, iclass 27, count 2 2006.190.07:43:50.13#ibcon#about to write, iclass 27, count 2 2006.190.07:43:50.13#ibcon#wrote, iclass 27, count 2 2006.190.07:43:50.13#ibcon#about to read 3, iclass 27, count 2 2006.190.07:43:50.16#ibcon#read 3, iclass 27, count 2 2006.190.07:43:50.16#ibcon#about to read 4, iclass 27, count 2 2006.190.07:43:50.16#ibcon#read 4, iclass 27, count 2 2006.190.07:43:50.16#ibcon#about to read 5, iclass 27, count 2 2006.190.07:43:50.16#ibcon#read 5, iclass 27, count 2 2006.190.07:43:50.16#ibcon#about to read 6, iclass 27, count 2 2006.190.07:43:50.16#ibcon#read 6, iclass 27, count 2 2006.190.07:43:50.16#ibcon#end of sib2, iclass 27, count 2 2006.190.07:43:50.16#ibcon#*after write, iclass 27, count 2 2006.190.07:43:50.16#ibcon#*before return 0, iclass 27, count 2 2006.190.07:43:50.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:43:50.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:43:50.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.07:43:50.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:50.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:43:50.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:43:50.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:43:50.28#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:43:50.28#ibcon#first serial, iclass 27, count 0 2006.190.07:43:50.28#ibcon#enter sib2, iclass 27, count 0 2006.190.07:43:50.28#ibcon#flushed, iclass 27, count 0 2006.190.07:43:50.28#ibcon#about to write, iclass 27, count 0 2006.190.07:43:50.28#ibcon#wrote, iclass 27, count 0 2006.190.07:43:50.28#ibcon#about to read 3, iclass 27, count 0 2006.190.07:43:50.30#ibcon#read 3, iclass 27, count 0 2006.190.07:43:50.30#ibcon#about to read 4, iclass 27, count 0 2006.190.07:43:50.30#ibcon#read 4, iclass 27, count 0 2006.190.07:43:50.30#ibcon#about to read 5, iclass 27, count 0 2006.190.07:43:50.30#ibcon#read 5, iclass 27, count 0 2006.190.07:43:50.30#ibcon#about to read 6, iclass 27, count 0 2006.190.07:43:50.30#ibcon#read 6, iclass 27, count 0 2006.190.07:43:50.30#ibcon#end of sib2, iclass 27, count 0 2006.190.07:43:50.30#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:43:50.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:43:50.30#ibcon#[25=USB\r\n] 2006.190.07:43:50.30#ibcon#*before write, iclass 27, count 0 2006.190.07:43:50.30#ibcon#enter sib2, iclass 27, count 0 2006.190.07:43:50.30#ibcon#flushed, iclass 27, count 0 2006.190.07:43:50.30#ibcon#about to write, iclass 27, count 0 2006.190.07:43:50.30#ibcon#wrote, iclass 27, count 0 2006.190.07:43:50.30#ibcon#about to read 3, iclass 27, count 0 2006.190.07:43:50.33#ibcon#read 3, iclass 27, count 0 2006.190.07:43:50.33#ibcon#about to read 4, iclass 27, count 0 2006.190.07:43:50.33#ibcon#read 4, iclass 27, count 0 2006.190.07:43:50.33#ibcon#about to read 5, iclass 27, count 0 2006.190.07:43:50.33#ibcon#read 5, iclass 27, count 0 2006.190.07:43:50.33#ibcon#about to read 6, iclass 27, count 0 2006.190.07:43:50.33#ibcon#read 6, iclass 27, count 0 2006.190.07:43:50.33#ibcon#end of sib2, iclass 27, count 0 2006.190.07:43:50.33#ibcon#*after write, iclass 27, count 0 2006.190.07:43:50.33#ibcon#*before return 0, iclass 27, count 0 2006.190.07:43:50.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:43:50.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:43:50.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:43:50.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:43:50.33$vc4f8/valo=8,852.99 2006.190.07:43:50.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.07:43:50.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.07:43:50.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:50.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:43:50.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:43:50.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:43:50.33#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:43:50.33#ibcon#first serial, iclass 29, count 0 2006.190.07:43:50.33#ibcon#enter sib2, iclass 29, count 0 2006.190.07:43:50.33#ibcon#flushed, iclass 29, count 0 2006.190.07:43:50.33#ibcon#about to write, iclass 29, count 0 2006.190.07:43:50.33#ibcon#wrote, iclass 29, count 0 2006.190.07:43:50.33#ibcon#about to read 3, iclass 29, count 0 2006.190.07:43:50.35#ibcon#read 3, iclass 29, count 0 2006.190.07:43:50.35#ibcon#about to read 4, iclass 29, count 0 2006.190.07:43:50.35#ibcon#read 4, iclass 29, count 0 2006.190.07:43:50.35#ibcon#about to read 5, iclass 29, count 0 2006.190.07:43:50.35#ibcon#read 5, iclass 29, count 0 2006.190.07:43:50.35#ibcon#about to read 6, iclass 29, count 0 2006.190.07:43:50.35#ibcon#read 6, iclass 29, count 0 2006.190.07:43:50.35#ibcon#end of sib2, iclass 29, count 0 2006.190.07:43:50.35#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:43:50.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:43:50.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:43:50.35#ibcon#*before write, iclass 29, count 0 2006.190.07:43:50.35#ibcon#enter sib2, iclass 29, count 0 2006.190.07:43:50.35#ibcon#flushed, iclass 29, count 0 2006.190.07:43:50.35#ibcon#about to write, iclass 29, count 0 2006.190.07:43:50.35#ibcon#wrote, iclass 29, count 0 2006.190.07:43:50.35#ibcon#about to read 3, iclass 29, count 0 2006.190.07:43:50.39#ibcon#read 3, iclass 29, count 0 2006.190.07:43:50.39#ibcon#about to read 4, iclass 29, count 0 2006.190.07:43:50.39#ibcon#read 4, iclass 29, count 0 2006.190.07:43:50.39#ibcon#about to read 5, iclass 29, count 0 2006.190.07:43:50.39#ibcon#read 5, iclass 29, count 0 2006.190.07:43:50.39#ibcon#about to read 6, iclass 29, count 0 2006.190.07:43:50.39#ibcon#read 6, iclass 29, count 0 2006.190.07:43:50.39#ibcon#end of sib2, iclass 29, count 0 2006.190.07:43:50.39#ibcon#*after write, iclass 29, count 0 2006.190.07:43:50.39#ibcon#*before return 0, iclass 29, count 0 2006.190.07:43:50.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:43:50.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:43:50.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:43:50.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:43:50.39$vc4f8/va=8,6 2006.190.07:43:50.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.07:43:50.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.07:43:50.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:50.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:43:50.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:43:50.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:43:50.45#ibcon#enter wrdev, iclass 31, count 2 2006.190.07:43:50.45#ibcon#first serial, iclass 31, count 2 2006.190.07:43:50.45#ibcon#enter sib2, iclass 31, count 2 2006.190.07:43:50.45#ibcon#flushed, iclass 31, count 2 2006.190.07:43:50.45#ibcon#about to write, iclass 31, count 2 2006.190.07:43:50.45#ibcon#wrote, iclass 31, count 2 2006.190.07:43:50.45#ibcon#about to read 3, iclass 31, count 2 2006.190.07:43:50.47#ibcon#read 3, iclass 31, count 2 2006.190.07:43:50.47#ibcon#about to read 4, iclass 31, count 2 2006.190.07:43:50.47#ibcon#read 4, iclass 31, count 2 2006.190.07:43:50.47#ibcon#about to read 5, iclass 31, count 2 2006.190.07:43:50.47#ibcon#read 5, iclass 31, count 2 2006.190.07:43:50.47#ibcon#about to read 6, iclass 31, count 2 2006.190.07:43:50.47#ibcon#read 6, iclass 31, count 2 2006.190.07:43:50.47#ibcon#end of sib2, iclass 31, count 2 2006.190.07:43:50.47#ibcon#*mode == 0, iclass 31, count 2 2006.190.07:43:50.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.07:43:50.47#ibcon#[25=AT08-06\r\n] 2006.190.07:43:50.47#ibcon#*before write, iclass 31, count 2 2006.190.07:43:50.47#ibcon#enter sib2, iclass 31, count 2 2006.190.07:43:50.47#ibcon#flushed, iclass 31, count 2 2006.190.07:43:50.47#ibcon#about to write, iclass 31, count 2 2006.190.07:43:50.47#ibcon#wrote, iclass 31, count 2 2006.190.07:43:50.47#ibcon#about to read 3, iclass 31, count 2 2006.190.07:43:50.50#ibcon#read 3, iclass 31, count 2 2006.190.07:43:50.50#ibcon#about to read 4, iclass 31, count 2 2006.190.07:43:50.50#ibcon#read 4, iclass 31, count 2 2006.190.07:43:50.50#ibcon#about to read 5, iclass 31, count 2 2006.190.07:43:50.50#ibcon#read 5, iclass 31, count 2 2006.190.07:43:50.50#ibcon#about to read 6, iclass 31, count 2 2006.190.07:43:50.50#ibcon#read 6, iclass 31, count 2 2006.190.07:43:50.50#ibcon#end of sib2, iclass 31, count 2 2006.190.07:43:50.50#ibcon#*after write, iclass 31, count 2 2006.190.07:43:50.50#ibcon#*before return 0, iclass 31, count 2 2006.190.07:43:50.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:43:50.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:43:50.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.07:43:50.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:50.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:43:50.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:43:50.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:43:50.62#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:43:50.62#ibcon#first serial, iclass 31, count 0 2006.190.07:43:50.62#ibcon#enter sib2, iclass 31, count 0 2006.190.07:43:50.62#ibcon#flushed, iclass 31, count 0 2006.190.07:43:50.62#ibcon#about to write, iclass 31, count 0 2006.190.07:43:50.62#ibcon#wrote, iclass 31, count 0 2006.190.07:43:50.62#ibcon#about to read 3, iclass 31, count 0 2006.190.07:43:50.64#ibcon#read 3, iclass 31, count 0 2006.190.07:43:50.64#ibcon#about to read 4, iclass 31, count 0 2006.190.07:43:50.64#ibcon#read 4, iclass 31, count 0 2006.190.07:43:50.64#ibcon#about to read 5, iclass 31, count 0 2006.190.07:43:50.64#ibcon#read 5, iclass 31, count 0 2006.190.07:43:50.64#ibcon#about to read 6, iclass 31, count 0 2006.190.07:43:50.64#ibcon#read 6, iclass 31, count 0 2006.190.07:43:50.64#ibcon#end of sib2, iclass 31, count 0 2006.190.07:43:50.64#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:43:50.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:43:50.64#ibcon#[25=USB\r\n] 2006.190.07:43:50.64#ibcon#*before write, iclass 31, count 0 2006.190.07:43:50.64#ibcon#enter sib2, iclass 31, count 0 2006.190.07:43:50.64#ibcon#flushed, iclass 31, count 0 2006.190.07:43:50.64#ibcon#about to write, iclass 31, count 0 2006.190.07:43:50.64#ibcon#wrote, iclass 31, count 0 2006.190.07:43:50.64#ibcon#about to read 3, iclass 31, count 0 2006.190.07:43:50.67#ibcon#read 3, iclass 31, count 0 2006.190.07:43:50.67#ibcon#about to read 4, iclass 31, count 0 2006.190.07:43:50.67#ibcon#read 4, iclass 31, count 0 2006.190.07:43:50.67#ibcon#about to read 5, iclass 31, count 0 2006.190.07:43:50.67#ibcon#read 5, iclass 31, count 0 2006.190.07:43:50.67#ibcon#about to read 6, iclass 31, count 0 2006.190.07:43:50.67#ibcon#read 6, iclass 31, count 0 2006.190.07:43:50.67#ibcon#end of sib2, iclass 31, count 0 2006.190.07:43:50.67#ibcon#*after write, iclass 31, count 0 2006.190.07:43:50.67#ibcon#*before return 0, iclass 31, count 0 2006.190.07:43:50.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:43:50.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:43:50.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:43:50.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:43:50.67$vc4f8/vblo=1,632.99 2006.190.07:43:50.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.07:43:50.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.07:43:50.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:50.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:43:50.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:43:50.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:43:50.67#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:43:50.67#ibcon#first serial, iclass 33, count 0 2006.190.07:43:50.67#ibcon#enter sib2, iclass 33, count 0 2006.190.07:43:50.67#ibcon#flushed, iclass 33, count 0 2006.190.07:43:50.67#ibcon#about to write, iclass 33, count 0 2006.190.07:43:50.67#ibcon#wrote, iclass 33, count 0 2006.190.07:43:50.67#ibcon#about to read 3, iclass 33, count 0 2006.190.07:43:50.69#ibcon#read 3, iclass 33, count 0 2006.190.07:43:50.69#ibcon#about to read 4, iclass 33, count 0 2006.190.07:43:50.69#ibcon#read 4, iclass 33, count 0 2006.190.07:43:50.69#ibcon#about to read 5, iclass 33, count 0 2006.190.07:43:50.69#ibcon#read 5, iclass 33, count 0 2006.190.07:43:50.69#ibcon#about to read 6, iclass 33, count 0 2006.190.07:43:50.69#ibcon#read 6, iclass 33, count 0 2006.190.07:43:50.69#ibcon#end of sib2, iclass 33, count 0 2006.190.07:43:50.69#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:43:50.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:43:50.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:43:50.69#ibcon#*before write, iclass 33, count 0 2006.190.07:43:50.69#ibcon#enter sib2, iclass 33, count 0 2006.190.07:43:50.69#ibcon#flushed, iclass 33, count 0 2006.190.07:43:50.69#ibcon#about to write, iclass 33, count 0 2006.190.07:43:50.69#ibcon#wrote, iclass 33, count 0 2006.190.07:43:50.69#ibcon#about to read 3, iclass 33, count 0 2006.190.07:43:50.73#ibcon#read 3, iclass 33, count 0 2006.190.07:43:50.73#ibcon#about to read 4, iclass 33, count 0 2006.190.07:43:50.73#ibcon#read 4, iclass 33, count 0 2006.190.07:43:50.73#ibcon#about to read 5, iclass 33, count 0 2006.190.07:43:50.73#ibcon#read 5, iclass 33, count 0 2006.190.07:43:50.73#ibcon#about to read 6, iclass 33, count 0 2006.190.07:43:50.73#ibcon#read 6, iclass 33, count 0 2006.190.07:43:50.73#ibcon#end of sib2, iclass 33, count 0 2006.190.07:43:50.73#ibcon#*after write, iclass 33, count 0 2006.190.07:43:50.73#ibcon#*before return 0, iclass 33, count 0 2006.190.07:43:50.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:43:50.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:43:50.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:43:50.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:43:50.73$vc4f8/vb=1,4 2006.190.07:43:50.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.07:43:50.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.07:43:50.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:50.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:43:50.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:43:50.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:43:50.73#ibcon#enter wrdev, iclass 35, count 2 2006.190.07:43:50.73#ibcon#first serial, iclass 35, count 2 2006.190.07:43:50.73#ibcon#enter sib2, iclass 35, count 2 2006.190.07:43:50.73#ibcon#flushed, iclass 35, count 2 2006.190.07:43:50.73#ibcon#about to write, iclass 35, count 2 2006.190.07:43:50.73#ibcon#wrote, iclass 35, count 2 2006.190.07:43:50.73#ibcon#about to read 3, iclass 35, count 2 2006.190.07:43:50.75#ibcon#read 3, iclass 35, count 2 2006.190.07:43:50.75#ibcon#about to read 4, iclass 35, count 2 2006.190.07:43:50.75#ibcon#read 4, iclass 35, count 2 2006.190.07:43:50.75#ibcon#about to read 5, iclass 35, count 2 2006.190.07:43:50.75#ibcon#read 5, iclass 35, count 2 2006.190.07:43:50.75#ibcon#about to read 6, iclass 35, count 2 2006.190.07:43:50.75#ibcon#read 6, iclass 35, count 2 2006.190.07:43:50.75#ibcon#end of sib2, iclass 35, count 2 2006.190.07:43:50.75#ibcon#*mode == 0, iclass 35, count 2 2006.190.07:43:50.75#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.07:43:50.75#ibcon#[27=AT01-04\r\n] 2006.190.07:43:50.75#ibcon#*before write, iclass 35, count 2 2006.190.07:43:50.75#ibcon#enter sib2, iclass 35, count 2 2006.190.07:43:50.75#ibcon#flushed, iclass 35, count 2 2006.190.07:43:50.75#ibcon#about to write, iclass 35, count 2 2006.190.07:43:50.75#ibcon#wrote, iclass 35, count 2 2006.190.07:43:50.75#ibcon#about to read 3, iclass 35, count 2 2006.190.07:43:50.78#ibcon#read 3, iclass 35, count 2 2006.190.07:43:50.78#ibcon#about to read 4, iclass 35, count 2 2006.190.07:43:50.78#ibcon#read 4, iclass 35, count 2 2006.190.07:43:50.78#ibcon#about to read 5, iclass 35, count 2 2006.190.07:43:50.78#ibcon#read 5, iclass 35, count 2 2006.190.07:43:50.78#ibcon#about to read 6, iclass 35, count 2 2006.190.07:43:50.78#ibcon#read 6, iclass 35, count 2 2006.190.07:43:50.78#ibcon#end of sib2, iclass 35, count 2 2006.190.07:43:50.78#ibcon#*after write, iclass 35, count 2 2006.190.07:43:50.78#ibcon#*before return 0, iclass 35, count 2 2006.190.07:43:50.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:43:50.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:43:50.78#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.07:43:50.78#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:50.78#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:43:50.90#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:43:50.90#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:43:50.90#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:43:50.90#ibcon#first serial, iclass 35, count 0 2006.190.07:43:50.90#ibcon#enter sib2, iclass 35, count 0 2006.190.07:43:50.90#ibcon#flushed, iclass 35, count 0 2006.190.07:43:50.90#ibcon#about to write, iclass 35, count 0 2006.190.07:43:50.90#ibcon#wrote, iclass 35, count 0 2006.190.07:43:50.90#ibcon#about to read 3, iclass 35, count 0 2006.190.07:43:50.92#ibcon#read 3, iclass 35, count 0 2006.190.07:43:50.92#ibcon#about to read 4, iclass 35, count 0 2006.190.07:43:50.92#ibcon#read 4, iclass 35, count 0 2006.190.07:43:50.92#ibcon#about to read 5, iclass 35, count 0 2006.190.07:43:50.92#ibcon#read 5, iclass 35, count 0 2006.190.07:43:50.92#ibcon#about to read 6, iclass 35, count 0 2006.190.07:43:50.92#ibcon#read 6, iclass 35, count 0 2006.190.07:43:50.92#ibcon#end of sib2, iclass 35, count 0 2006.190.07:43:50.92#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:43:50.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:43:50.92#ibcon#[27=USB\r\n] 2006.190.07:43:50.92#ibcon#*before write, iclass 35, count 0 2006.190.07:43:50.92#ibcon#enter sib2, iclass 35, count 0 2006.190.07:43:50.92#ibcon#flushed, iclass 35, count 0 2006.190.07:43:50.92#ibcon#about to write, iclass 35, count 0 2006.190.07:43:50.92#ibcon#wrote, iclass 35, count 0 2006.190.07:43:50.92#ibcon#about to read 3, iclass 35, count 0 2006.190.07:43:50.95#ibcon#read 3, iclass 35, count 0 2006.190.07:43:50.95#ibcon#about to read 4, iclass 35, count 0 2006.190.07:43:50.95#ibcon#read 4, iclass 35, count 0 2006.190.07:43:50.95#ibcon#about to read 5, iclass 35, count 0 2006.190.07:43:50.95#ibcon#read 5, iclass 35, count 0 2006.190.07:43:50.95#ibcon#about to read 6, iclass 35, count 0 2006.190.07:43:50.95#ibcon#read 6, iclass 35, count 0 2006.190.07:43:50.95#ibcon#end of sib2, iclass 35, count 0 2006.190.07:43:50.95#ibcon#*after write, iclass 35, count 0 2006.190.07:43:50.95#ibcon#*before return 0, iclass 35, count 0 2006.190.07:43:50.95#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:43:50.95#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:43:50.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:43:50.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:43:50.95$vc4f8/vblo=2,640.99 2006.190.07:43:50.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.07:43:50.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.07:43:50.95#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:50.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:50.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:50.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:50.95#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:43:50.95#ibcon#first serial, iclass 37, count 0 2006.190.07:43:50.95#ibcon#enter sib2, iclass 37, count 0 2006.190.07:43:50.95#ibcon#flushed, iclass 37, count 0 2006.190.07:43:50.95#ibcon#about to write, iclass 37, count 0 2006.190.07:43:50.95#ibcon#wrote, iclass 37, count 0 2006.190.07:43:50.95#ibcon#about to read 3, iclass 37, count 0 2006.190.07:43:50.97#ibcon#read 3, iclass 37, count 0 2006.190.07:43:50.97#ibcon#about to read 4, iclass 37, count 0 2006.190.07:43:50.97#ibcon#read 4, iclass 37, count 0 2006.190.07:43:50.97#ibcon#about to read 5, iclass 37, count 0 2006.190.07:43:50.97#ibcon#read 5, iclass 37, count 0 2006.190.07:43:50.97#ibcon#about to read 6, iclass 37, count 0 2006.190.07:43:50.97#ibcon#read 6, iclass 37, count 0 2006.190.07:43:50.97#ibcon#end of sib2, iclass 37, count 0 2006.190.07:43:50.97#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:43:50.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:43:50.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:43:50.97#ibcon#*before write, iclass 37, count 0 2006.190.07:43:50.97#ibcon#enter sib2, iclass 37, count 0 2006.190.07:43:50.97#ibcon#flushed, iclass 37, count 0 2006.190.07:43:50.97#ibcon#about to write, iclass 37, count 0 2006.190.07:43:50.97#ibcon#wrote, iclass 37, count 0 2006.190.07:43:50.97#ibcon#about to read 3, iclass 37, count 0 2006.190.07:43:51.01#ibcon#read 3, iclass 37, count 0 2006.190.07:43:51.01#ibcon#about to read 4, iclass 37, count 0 2006.190.07:43:51.01#ibcon#read 4, iclass 37, count 0 2006.190.07:43:51.01#ibcon#about to read 5, iclass 37, count 0 2006.190.07:43:51.01#ibcon#read 5, iclass 37, count 0 2006.190.07:43:51.01#ibcon#about to read 6, iclass 37, count 0 2006.190.07:43:51.01#ibcon#read 6, iclass 37, count 0 2006.190.07:43:51.01#ibcon#end of sib2, iclass 37, count 0 2006.190.07:43:51.01#ibcon#*after write, iclass 37, count 0 2006.190.07:43:51.01#ibcon#*before return 0, iclass 37, count 0 2006.190.07:43:51.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:51.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:43:51.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:43:51.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:43:51.01$vc4f8/vb=2,4 2006.190.07:43:51.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.07:43:51.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.07:43:51.01#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:51.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:51.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:51.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:51.07#ibcon#enter wrdev, iclass 39, count 2 2006.190.07:43:51.07#ibcon#first serial, iclass 39, count 2 2006.190.07:43:51.07#ibcon#enter sib2, iclass 39, count 2 2006.190.07:43:51.07#ibcon#flushed, iclass 39, count 2 2006.190.07:43:51.07#ibcon#about to write, iclass 39, count 2 2006.190.07:43:51.07#ibcon#wrote, iclass 39, count 2 2006.190.07:43:51.07#ibcon#about to read 3, iclass 39, count 2 2006.190.07:43:51.09#ibcon#read 3, iclass 39, count 2 2006.190.07:43:51.09#ibcon#about to read 4, iclass 39, count 2 2006.190.07:43:51.09#ibcon#read 4, iclass 39, count 2 2006.190.07:43:51.09#ibcon#about to read 5, iclass 39, count 2 2006.190.07:43:51.09#ibcon#read 5, iclass 39, count 2 2006.190.07:43:51.09#ibcon#about to read 6, iclass 39, count 2 2006.190.07:43:51.09#ibcon#read 6, iclass 39, count 2 2006.190.07:43:51.09#ibcon#end of sib2, iclass 39, count 2 2006.190.07:43:51.09#ibcon#*mode == 0, iclass 39, count 2 2006.190.07:43:51.09#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.07:43:51.09#ibcon#[27=AT02-04\r\n] 2006.190.07:43:51.09#ibcon#*before write, iclass 39, count 2 2006.190.07:43:51.09#ibcon#enter sib2, iclass 39, count 2 2006.190.07:43:51.09#ibcon#flushed, iclass 39, count 2 2006.190.07:43:51.09#ibcon#about to write, iclass 39, count 2 2006.190.07:43:51.09#ibcon#wrote, iclass 39, count 2 2006.190.07:43:51.09#ibcon#about to read 3, iclass 39, count 2 2006.190.07:43:51.12#ibcon#read 3, iclass 39, count 2 2006.190.07:43:51.12#ibcon#about to read 4, iclass 39, count 2 2006.190.07:43:51.12#ibcon#read 4, iclass 39, count 2 2006.190.07:43:51.12#ibcon#about to read 5, iclass 39, count 2 2006.190.07:43:51.12#ibcon#read 5, iclass 39, count 2 2006.190.07:43:51.12#ibcon#about to read 6, iclass 39, count 2 2006.190.07:43:51.12#ibcon#read 6, iclass 39, count 2 2006.190.07:43:51.12#ibcon#end of sib2, iclass 39, count 2 2006.190.07:43:51.12#ibcon#*after write, iclass 39, count 2 2006.190.07:43:51.12#ibcon#*before return 0, iclass 39, count 2 2006.190.07:43:51.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:51.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:43:51.12#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.07:43:51.12#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:51.12#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:51.24#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:51.24#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:51.24#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:43:51.24#ibcon#first serial, iclass 39, count 0 2006.190.07:43:51.24#ibcon#enter sib2, iclass 39, count 0 2006.190.07:43:51.24#ibcon#flushed, iclass 39, count 0 2006.190.07:43:51.24#ibcon#about to write, iclass 39, count 0 2006.190.07:43:51.24#ibcon#wrote, iclass 39, count 0 2006.190.07:43:51.24#ibcon#about to read 3, iclass 39, count 0 2006.190.07:43:51.26#ibcon#read 3, iclass 39, count 0 2006.190.07:43:51.26#ibcon#about to read 4, iclass 39, count 0 2006.190.07:43:51.26#ibcon#read 4, iclass 39, count 0 2006.190.07:43:51.26#ibcon#about to read 5, iclass 39, count 0 2006.190.07:43:51.26#ibcon#read 5, iclass 39, count 0 2006.190.07:43:51.26#ibcon#about to read 6, iclass 39, count 0 2006.190.07:43:51.26#ibcon#read 6, iclass 39, count 0 2006.190.07:43:51.26#ibcon#end of sib2, iclass 39, count 0 2006.190.07:43:51.26#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:43:51.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:43:51.26#ibcon#[27=USB\r\n] 2006.190.07:43:51.26#ibcon#*before write, iclass 39, count 0 2006.190.07:43:51.26#ibcon#enter sib2, iclass 39, count 0 2006.190.07:43:51.26#ibcon#flushed, iclass 39, count 0 2006.190.07:43:51.26#ibcon#about to write, iclass 39, count 0 2006.190.07:43:51.26#ibcon#wrote, iclass 39, count 0 2006.190.07:43:51.26#ibcon#about to read 3, iclass 39, count 0 2006.190.07:43:51.29#ibcon#read 3, iclass 39, count 0 2006.190.07:43:51.29#ibcon#about to read 4, iclass 39, count 0 2006.190.07:43:51.29#ibcon#read 4, iclass 39, count 0 2006.190.07:43:51.29#ibcon#about to read 5, iclass 39, count 0 2006.190.07:43:51.29#ibcon#read 5, iclass 39, count 0 2006.190.07:43:51.29#ibcon#about to read 6, iclass 39, count 0 2006.190.07:43:51.29#ibcon#read 6, iclass 39, count 0 2006.190.07:43:51.29#ibcon#end of sib2, iclass 39, count 0 2006.190.07:43:51.29#ibcon#*after write, iclass 39, count 0 2006.190.07:43:51.29#ibcon#*before return 0, iclass 39, count 0 2006.190.07:43:51.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:51.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:43:51.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:43:51.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:43:51.29$vc4f8/vblo=3,656.99 2006.190.07:43:51.29#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.07:43:51.29#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.07:43:51.29#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:51.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:51.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:51.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:51.29#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:43:51.29#ibcon#first serial, iclass 3, count 0 2006.190.07:43:51.29#ibcon#enter sib2, iclass 3, count 0 2006.190.07:43:51.29#ibcon#flushed, iclass 3, count 0 2006.190.07:43:51.29#ibcon#about to write, iclass 3, count 0 2006.190.07:43:51.29#ibcon#wrote, iclass 3, count 0 2006.190.07:43:51.29#ibcon#about to read 3, iclass 3, count 0 2006.190.07:43:51.31#ibcon#read 3, iclass 3, count 0 2006.190.07:43:51.31#ibcon#about to read 4, iclass 3, count 0 2006.190.07:43:51.31#ibcon#read 4, iclass 3, count 0 2006.190.07:43:51.31#ibcon#about to read 5, iclass 3, count 0 2006.190.07:43:51.31#ibcon#read 5, iclass 3, count 0 2006.190.07:43:51.31#ibcon#about to read 6, iclass 3, count 0 2006.190.07:43:51.31#ibcon#read 6, iclass 3, count 0 2006.190.07:43:51.31#ibcon#end of sib2, iclass 3, count 0 2006.190.07:43:51.31#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:43:51.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:43:51.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:43:51.31#ibcon#*before write, iclass 3, count 0 2006.190.07:43:51.31#ibcon#enter sib2, iclass 3, count 0 2006.190.07:43:51.31#ibcon#flushed, iclass 3, count 0 2006.190.07:43:51.31#ibcon#about to write, iclass 3, count 0 2006.190.07:43:51.31#ibcon#wrote, iclass 3, count 0 2006.190.07:43:51.31#ibcon#about to read 3, iclass 3, count 0 2006.190.07:43:51.35#ibcon#read 3, iclass 3, count 0 2006.190.07:43:51.35#ibcon#about to read 4, iclass 3, count 0 2006.190.07:43:51.35#ibcon#read 4, iclass 3, count 0 2006.190.07:43:51.35#ibcon#about to read 5, iclass 3, count 0 2006.190.07:43:51.35#ibcon#read 5, iclass 3, count 0 2006.190.07:43:51.35#ibcon#about to read 6, iclass 3, count 0 2006.190.07:43:51.35#ibcon#read 6, iclass 3, count 0 2006.190.07:43:51.35#ibcon#end of sib2, iclass 3, count 0 2006.190.07:43:51.35#ibcon#*after write, iclass 3, count 0 2006.190.07:43:51.35#ibcon#*before return 0, iclass 3, count 0 2006.190.07:43:51.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:51.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:43:51.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:43:51.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:43:51.35$vc4f8/vb=3,4 2006.190.07:43:51.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.07:43:51.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.07:43:51.35#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:51.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:51.40#abcon#<5=/04 1.7 3.1 24.511001012.2\r\n> 2006.190.07:43:51.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:51.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:51.41#ibcon#enter wrdev, iclass 5, count 2 2006.190.07:43:51.41#ibcon#first serial, iclass 5, count 2 2006.190.07:43:51.41#ibcon#enter sib2, iclass 5, count 2 2006.190.07:43:51.41#ibcon#flushed, iclass 5, count 2 2006.190.07:43:51.41#ibcon#about to write, iclass 5, count 2 2006.190.07:43:51.41#ibcon#wrote, iclass 5, count 2 2006.190.07:43:51.41#ibcon#about to read 3, iclass 5, count 2 2006.190.07:43:51.42#abcon#{5=INTERFACE CLEAR} 2006.190.07:43:51.43#ibcon#read 3, iclass 5, count 2 2006.190.07:43:51.43#ibcon#about to read 4, iclass 5, count 2 2006.190.07:43:51.43#ibcon#read 4, iclass 5, count 2 2006.190.07:43:51.43#ibcon#about to read 5, iclass 5, count 2 2006.190.07:43:51.43#ibcon#read 5, iclass 5, count 2 2006.190.07:43:51.43#ibcon#about to read 6, iclass 5, count 2 2006.190.07:43:51.43#ibcon#read 6, iclass 5, count 2 2006.190.07:43:51.43#ibcon#end of sib2, iclass 5, count 2 2006.190.07:43:51.43#ibcon#*mode == 0, iclass 5, count 2 2006.190.07:43:51.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.07:43:51.43#ibcon#[27=AT03-04\r\n] 2006.190.07:43:51.43#ibcon#*before write, iclass 5, count 2 2006.190.07:43:51.43#ibcon#enter sib2, iclass 5, count 2 2006.190.07:43:51.43#ibcon#flushed, iclass 5, count 2 2006.190.07:43:51.43#ibcon#about to write, iclass 5, count 2 2006.190.07:43:51.43#ibcon#wrote, iclass 5, count 2 2006.190.07:43:51.43#ibcon#about to read 3, iclass 5, count 2 2006.190.07:43:51.46#ibcon#read 3, iclass 5, count 2 2006.190.07:43:51.46#ibcon#about to read 4, iclass 5, count 2 2006.190.07:43:51.46#ibcon#read 4, iclass 5, count 2 2006.190.07:43:51.46#ibcon#about to read 5, iclass 5, count 2 2006.190.07:43:51.46#ibcon#read 5, iclass 5, count 2 2006.190.07:43:51.46#ibcon#about to read 6, iclass 5, count 2 2006.190.07:43:51.46#ibcon#read 6, iclass 5, count 2 2006.190.07:43:51.46#ibcon#end of sib2, iclass 5, count 2 2006.190.07:43:51.46#ibcon#*after write, iclass 5, count 2 2006.190.07:43:51.46#ibcon#*before return 0, iclass 5, count 2 2006.190.07:43:51.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:51.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:43:51.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.07:43:51.46#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:51.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:51.48#abcon#[5=S1D000X0/0*\r\n] 2006.190.07:43:51.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:51.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:51.58#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:43:51.58#ibcon#first serial, iclass 5, count 0 2006.190.07:43:51.58#ibcon#enter sib2, iclass 5, count 0 2006.190.07:43:51.58#ibcon#flushed, iclass 5, count 0 2006.190.07:43:51.58#ibcon#about to write, iclass 5, count 0 2006.190.07:43:51.58#ibcon#wrote, iclass 5, count 0 2006.190.07:43:51.58#ibcon#about to read 3, iclass 5, count 0 2006.190.07:43:51.60#ibcon#read 3, iclass 5, count 0 2006.190.07:43:51.60#ibcon#about to read 4, iclass 5, count 0 2006.190.07:43:51.60#ibcon#read 4, iclass 5, count 0 2006.190.07:43:51.60#ibcon#about to read 5, iclass 5, count 0 2006.190.07:43:51.60#ibcon#read 5, iclass 5, count 0 2006.190.07:43:51.60#ibcon#about to read 6, iclass 5, count 0 2006.190.07:43:51.60#ibcon#read 6, iclass 5, count 0 2006.190.07:43:51.60#ibcon#end of sib2, iclass 5, count 0 2006.190.07:43:51.60#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:43:51.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:43:51.60#ibcon#[27=USB\r\n] 2006.190.07:43:51.60#ibcon#*before write, iclass 5, count 0 2006.190.07:43:51.60#ibcon#enter sib2, iclass 5, count 0 2006.190.07:43:51.60#ibcon#flushed, iclass 5, count 0 2006.190.07:43:51.60#ibcon#about to write, iclass 5, count 0 2006.190.07:43:51.60#ibcon#wrote, iclass 5, count 0 2006.190.07:43:51.60#ibcon#about to read 3, iclass 5, count 0 2006.190.07:43:51.63#ibcon#read 3, iclass 5, count 0 2006.190.07:43:51.63#ibcon#about to read 4, iclass 5, count 0 2006.190.07:43:51.63#ibcon#read 4, iclass 5, count 0 2006.190.07:43:51.63#ibcon#about to read 5, iclass 5, count 0 2006.190.07:43:51.63#ibcon#read 5, iclass 5, count 0 2006.190.07:43:51.63#ibcon#about to read 6, iclass 5, count 0 2006.190.07:43:51.63#ibcon#read 6, iclass 5, count 0 2006.190.07:43:51.63#ibcon#end of sib2, iclass 5, count 0 2006.190.07:43:51.63#ibcon#*after write, iclass 5, count 0 2006.190.07:43:51.63#ibcon#*before return 0, iclass 5, count 0 2006.190.07:43:51.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:51.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:43:51.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:43:51.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:43:51.63$vc4f8/vblo=4,712.99 2006.190.07:43:51.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.07:43:51.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.07:43:51.63#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:51.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:51.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:51.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:51.63#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:43:51.63#ibcon#first serial, iclass 13, count 0 2006.190.07:43:51.63#ibcon#enter sib2, iclass 13, count 0 2006.190.07:43:51.63#ibcon#flushed, iclass 13, count 0 2006.190.07:43:51.63#ibcon#about to write, iclass 13, count 0 2006.190.07:43:51.63#ibcon#wrote, iclass 13, count 0 2006.190.07:43:51.63#ibcon#about to read 3, iclass 13, count 0 2006.190.07:43:51.65#ibcon#read 3, iclass 13, count 0 2006.190.07:43:51.65#ibcon#about to read 4, iclass 13, count 0 2006.190.07:43:51.65#ibcon#read 4, iclass 13, count 0 2006.190.07:43:51.65#ibcon#about to read 5, iclass 13, count 0 2006.190.07:43:51.65#ibcon#read 5, iclass 13, count 0 2006.190.07:43:51.65#ibcon#about to read 6, iclass 13, count 0 2006.190.07:43:51.65#ibcon#read 6, iclass 13, count 0 2006.190.07:43:51.65#ibcon#end of sib2, iclass 13, count 0 2006.190.07:43:51.65#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:43:51.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:43:51.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:43:51.65#ibcon#*before write, iclass 13, count 0 2006.190.07:43:51.65#ibcon#enter sib2, iclass 13, count 0 2006.190.07:43:51.65#ibcon#flushed, iclass 13, count 0 2006.190.07:43:51.65#ibcon#about to write, iclass 13, count 0 2006.190.07:43:51.65#ibcon#wrote, iclass 13, count 0 2006.190.07:43:51.65#ibcon#about to read 3, iclass 13, count 0 2006.190.07:43:51.69#ibcon#read 3, iclass 13, count 0 2006.190.07:43:51.69#ibcon#about to read 4, iclass 13, count 0 2006.190.07:43:51.69#ibcon#read 4, iclass 13, count 0 2006.190.07:43:51.69#ibcon#about to read 5, iclass 13, count 0 2006.190.07:43:51.69#ibcon#read 5, iclass 13, count 0 2006.190.07:43:51.69#ibcon#about to read 6, iclass 13, count 0 2006.190.07:43:51.69#ibcon#read 6, iclass 13, count 0 2006.190.07:43:51.69#ibcon#end of sib2, iclass 13, count 0 2006.190.07:43:51.69#ibcon#*after write, iclass 13, count 0 2006.190.07:43:51.69#ibcon#*before return 0, iclass 13, count 0 2006.190.07:43:51.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:51.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:43:51.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:43:51.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:43:51.69$vc4f8/vb=4,4 2006.190.07:43:51.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.07:43:51.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.07:43:51.69#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:51.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:51.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:51.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:51.75#ibcon#enter wrdev, iclass 15, count 2 2006.190.07:43:51.75#ibcon#first serial, iclass 15, count 2 2006.190.07:43:51.75#ibcon#enter sib2, iclass 15, count 2 2006.190.07:43:51.75#ibcon#flushed, iclass 15, count 2 2006.190.07:43:51.75#ibcon#about to write, iclass 15, count 2 2006.190.07:43:51.75#ibcon#wrote, iclass 15, count 2 2006.190.07:43:51.75#ibcon#about to read 3, iclass 15, count 2 2006.190.07:43:51.77#ibcon#read 3, iclass 15, count 2 2006.190.07:43:51.77#ibcon#about to read 4, iclass 15, count 2 2006.190.07:43:51.77#ibcon#read 4, iclass 15, count 2 2006.190.07:43:51.77#ibcon#about to read 5, iclass 15, count 2 2006.190.07:43:51.77#ibcon#read 5, iclass 15, count 2 2006.190.07:43:51.77#ibcon#about to read 6, iclass 15, count 2 2006.190.07:43:51.77#ibcon#read 6, iclass 15, count 2 2006.190.07:43:51.77#ibcon#end of sib2, iclass 15, count 2 2006.190.07:43:51.77#ibcon#*mode == 0, iclass 15, count 2 2006.190.07:43:51.77#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.07:43:51.77#ibcon#[27=AT04-04\r\n] 2006.190.07:43:51.77#ibcon#*before write, iclass 15, count 2 2006.190.07:43:51.77#ibcon#enter sib2, iclass 15, count 2 2006.190.07:43:51.77#ibcon#flushed, iclass 15, count 2 2006.190.07:43:51.77#ibcon#about to write, iclass 15, count 2 2006.190.07:43:51.77#ibcon#wrote, iclass 15, count 2 2006.190.07:43:51.77#ibcon#about to read 3, iclass 15, count 2 2006.190.07:43:51.80#ibcon#read 3, iclass 15, count 2 2006.190.07:43:51.80#ibcon#about to read 4, iclass 15, count 2 2006.190.07:43:51.80#ibcon#read 4, iclass 15, count 2 2006.190.07:43:51.80#ibcon#about to read 5, iclass 15, count 2 2006.190.07:43:51.80#ibcon#read 5, iclass 15, count 2 2006.190.07:43:51.80#ibcon#about to read 6, iclass 15, count 2 2006.190.07:43:51.80#ibcon#read 6, iclass 15, count 2 2006.190.07:43:51.80#ibcon#end of sib2, iclass 15, count 2 2006.190.07:43:51.80#ibcon#*after write, iclass 15, count 2 2006.190.07:43:51.80#ibcon#*before return 0, iclass 15, count 2 2006.190.07:43:51.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:51.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.07:43:51.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.07:43:51.80#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:51.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:51.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:51.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:51.92#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:43:51.92#ibcon#first serial, iclass 15, count 0 2006.190.07:43:51.92#ibcon#enter sib2, iclass 15, count 0 2006.190.07:43:51.92#ibcon#flushed, iclass 15, count 0 2006.190.07:43:51.92#ibcon#about to write, iclass 15, count 0 2006.190.07:43:51.92#ibcon#wrote, iclass 15, count 0 2006.190.07:43:51.92#ibcon#about to read 3, iclass 15, count 0 2006.190.07:43:51.94#ibcon#read 3, iclass 15, count 0 2006.190.07:43:51.94#ibcon#about to read 4, iclass 15, count 0 2006.190.07:43:51.94#ibcon#read 4, iclass 15, count 0 2006.190.07:43:51.94#ibcon#about to read 5, iclass 15, count 0 2006.190.07:43:51.94#ibcon#read 5, iclass 15, count 0 2006.190.07:43:51.94#ibcon#about to read 6, iclass 15, count 0 2006.190.07:43:51.94#ibcon#read 6, iclass 15, count 0 2006.190.07:43:51.94#ibcon#end of sib2, iclass 15, count 0 2006.190.07:43:51.94#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:43:51.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:43:51.94#ibcon#[27=USB\r\n] 2006.190.07:43:51.94#ibcon#*before write, iclass 15, count 0 2006.190.07:43:51.94#ibcon#enter sib2, iclass 15, count 0 2006.190.07:43:51.94#ibcon#flushed, iclass 15, count 0 2006.190.07:43:51.94#ibcon#about to write, iclass 15, count 0 2006.190.07:43:51.94#ibcon#wrote, iclass 15, count 0 2006.190.07:43:51.94#ibcon#about to read 3, iclass 15, count 0 2006.190.07:43:51.97#ibcon#read 3, iclass 15, count 0 2006.190.07:43:51.97#ibcon#about to read 4, iclass 15, count 0 2006.190.07:43:51.97#ibcon#read 4, iclass 15, count 0 2006.190.07:43:51.97#ibcon#about to read 5, iclass 15, count 0 2006.190.07:43:51.97#ibcon#read 5, iclass 15, count 0 2006.190.07:43:51.97#ibcon#about to read 6, iclass 15, count 0 2006.190.07:43:51.97#ibcon#read 6, iclass 15, count 0 2006.190.07:43:51.97#ibcon#end of sib2, iclass 15, count 0 2006.190.07:43:51.97#ibcon#*after write, iclass 15, count 0 2006.190.07:43:51.97#ibcon#*before return 0, iclass 15, count 0 2006.190.07:43:51.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:51.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.07:43:51.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:43:51.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:43:51.97$vc4f8/vblo=5,744.99 2006.190.07:43:51.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.07:43:51.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.07:43:51.97#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:51.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:51.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:51.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:51.97#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:43:51.97#ibcon#first serial, iclass 17, count 0 2006.190.07:43:51.97#ibcon#enter sib2, iclass 17, count 0 2006.190.07:43:51.97#ibcon#flushed, iclass 17, count 0 2006.190.07:43:51.97#ibcon#about to write, iclass 17, count 0 2006.190.07:43:51.97#ibcon#wrote, iclass 17, count 0 2006.190.07:43:51.97#ibcon#about to read 3, iclass 17, count 0 2006.190.07:43:51.99#ibcon#read 3, iclass 17, count 0 2006.190.07:43:51.99#ibcon#about to read 4, iclass 17, count 0 2006.190.07:43:51.99#ibcon#read 4, iclass 17, count 0 2006.190.07:43:51.99#ibcon#about to read 5, iclass 17, count 0 2006.190.07:43:51.99#ibcon#read 5, iclass 17, count 0 2006.190.07:43:51.99#ibcon#about to read 6, iclass 17, count 0 2006.190.07:43:51.99#ibcon#read 6, iclass 17, count 0 2006.190.07:43:51.99#ibcon#end of sib2, iclass 17, count 0 2006.190.07:43:51.99#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:43:51.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:43:51.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:43:51.99#ibcon#*before write, iclass 17, count 0 2006.190.07:43:51.99#ibcon#enter sib2, iclass 17, count 0 2006.190.07:43:51.99#ibcon#flushed, iclass 17, count 0 2006.190.07:43:51.99#ibcon#about to write, iclass 17, count 0 2006.190.07:43:51.99#ibcon#wrote, iclass 17, count 0 2006.190.07:43:51.99#ibcon#about to read 3, iclass 17, count 0 2006.190.07:43:52.03#ibcon#read 3, iclass 17, count 0 2006.190.07:43:52.03#ibcon#about to read 4, iclass 17, count 0 2006.190.07:43:52.03#ibcon#read 4, iclass 17, count 0 2006.190.07:43:52.03#ibcon#about to read 5, iclass 17, count 0 2006.190.07:43:52.03#ibcon#read 5, iclass 17, count 0 2006.190.07:43:52.03#ibcon#about to read 6, iclass 17, count 0 2006.190.07:43:52.03#ibcon#read 6, iclass 17, count 0 2006.190.07:43:52.03#ibcon#end of sib2, iclass 17, count 0 2006.190.07:43:52.03#ibcon#*after write, iclass 17, count 0 2006.190.07:43:52.03#ibcon#*before return 0, iclass 17, count 0 2006.190.07:43:52.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:52.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:43:52.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:43:52.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:43:52.03$vc4f8/vb=5,4 2006.190.07:43:52.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.07:43:52.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.07:43:52.03#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:52.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:52.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:52.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:52.09#ibcon#enter wrdev, iclass 19, count 2 2006.190.07:43:52.09#ibcon#first serial, iclass 19, count 2 2006.190.07:43:52.09#ibcon#enter sib2, iclass 19, count 2 2006.190.07:43:52.09#ibcon#flushed, iclass 19, count 2 2006.190.07:43:52.09#ibcon#about to write, iclass 19, count 2 2006.190.07:43:52.09#ibcon#wrote, iclass 19, count 2 2006.190.07:43:52.09#ibcon#about to read 3, iclass 19, count 2 2006.190.07:43:52.11#ibcon#read 3, iclass 19, count 2 2006.190.07:43:52.11#ibcon#about to read 4, iclass 19, count 2 2006.190.07:43:52.11#ibcon#read 4, iclass 19, count 2 2006.190.07:43:52.11#ibcon#about to read 5, iclass 19, count 2 2006.190.07:43:52.11#ibcon#read 5, iclass 19, count 2 2006.190.07:43:52.11#ibcon#about to read 6, iclass 19, count 2 2006.190.07:43:52.11#ibcon#read 6, iclass 19, count 2 2006.190.07:43:52.11#ibcon#end of sib2, iclass 19, count 2 2006.190.07:43:52.11#ibcon#*mode == 0, iclass 19, count 2 2006.190.07:43:52.11#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.07:43:52.11#ibcon#[27=AT05-04\r\n] 2006.190.07:43:52.11#ibcon#*before write, iclass 19, count 2 2006.190.07:43:52.11#ibcon#enter sib2, iclass 19, count 2 2006.190.07:43:52.11#ibcon#flushed, iclass 19, count 2 2006.190.07:43:52.11#ibcon#about to write, iclass 19, count 2 2006.190.07:43:52.11#ibcon#wrote, iclass 19, count 2 2006.190.07:43:52.11#ibcon#about to read 3, iclass 19, count 2 2006.190.07:43:52.14#ibcon#read 3, iclass 19, count 2 2006.190.07:43:52.14#ibcon#about to read 4, iclass 19, count 2 2006.190.07:43:52.14#ibcon#read 4, iclass 19, count 2 2006.190.07:43:52.14#ibcon#about to read 5, iclass 19, count 2 2006.190.07:43:52.14#ibcon#read 5, iclass 19, count 2 2006.190.07:43:52.14#ibcon#about to read 6, iclass 19, count 2 2006.190.07:43:52.14#ibcon#read 6, iclass 19, count 2 2006.190.07:43:52.14#ibcon#end of sib2, iclass 19, count 2 2006.190.07:43:52.14#ibcon#*after write, iclass 19, count 2 2006.190.07:43:52.14#ibcon#*before return 0, iclass 19, count 2 2006.190.07:43:52.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:52.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:43:52.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.07:43:52.14#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:52.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:52.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:52.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:52.26#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:43:52.26#ibcon#first serial, iclass 19, count 0 2006.190.07:43:52.26#ibcon#enter sib2, iclass 19, count 0 2006.190.07:43:52.26#ibcon#flushed, iclass 19, count 0 2006.190.07:43:52.26#ibcon#about to write, iclass 19, count 0 2006.190.07:43:52.26#ibcon#wrote, iclass 19, count 0 2006.190.07:43:52.26#ibcon#about to read 3, iclass 19, count 0 2006.190.07:43:52.28#ibcon#read 3, iclass 19, count 0 2006.190.07:43:52.28#ibcon#about to read 4, iclass 19, count 0 2006.190.07:43:52.28#ibcon#read 4, iclass 19, count 0 2006.190.07:43:52.28#ibcon#about to read 5, iclass 19, count 0 2006.190.07:43:52.28#ibcon#read 5, iclass 19, count 0 2006.190.07:43:52.28#ibcon#about to read 6, iclass 19, count 0 2006.190.07:43:52.28#ibcon#read 6, iclass 19, count 0 2006.190.07:43:52.28#ibcon#end of sib2, iclass 19, count 0 2006.190.07:43:52.28#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:43:52.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:43:52.28#ibcon#[27=USB\r\n] 2006.190.07:43:52.28#ibcon#*before write, iclass 19, count 0 2006.190.07:43:52.28#ibcon#enter sib2, iclass 19, count 0 2006.190.07:43:52.28#ibcon#flushed, iclass 19, count 0 2006.190.07:43:52.28#ibcon#about to write, iclass 19, count 0 2006.190.07:43:52.28#ibcon#wrote, iclass 19, count 0 2006.190.07:43:52.28#ibcon#about to read 3, iclass 19, count 0 2006.190.07:43:52.31#ibcon#read 3, iclass 19, count 0 2006.190.07:43:52.31#ibcon#about to read 4, iclass 19, count 0 2006.190.07:43:52.31#ibcon#read 4, iclass 19, count 0 2006.190.07:43:52.31#ibcon#about to read 5, iclass 19, count 0 2006.190.07:43:52.31#ibcon#read 5, iclass 19, count 0 2006.190.07:43:52.31#ibcon#about to read 6, iclass 19, count 0 2006.190.07:43:52.31#ibcon#read 6, iclass 19, count 0 2006.190.07:43:52.31#ibcon#end of sib2, iclass 19, count 0 2006.190.07:43:52.31#ibcon#*after write, iclass 19, count 0 2006.190.07:43:52.31#ibcon#*before return 0, iclass 19, count 0 2006.190.07:43:52.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:52.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:43:52.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:43:52.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:43:52.31$vc4f8/vblo=6,752.99 2006.190.07:43:52.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.07:43:52.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.07:43:52.31#ibcon#ireg 17 cls_cnt 0 2006.190.07:43:52.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:52.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:52.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:52.31#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:43:52.31#ibcon#first serial, iclass 21, count 0 2006.190.07:43:52.31#ibcon#enter sib2, iclass 21, count 0 2006.190.07:43:52.31#ibcon#flushed, iclass 21, count 0 2006.190.07:43:52.31#ibcon#about to write, iclass 21, count 0 2006.190.07:43:52.31#ibcon#wrote, iclass 21, count 0 2006.190.07:43:52.31#ibcon#about to read 3, iclass 21, count 0 2006.190.07:43:52.33#ibcon#read 3, iclass 21, count 0 2006.190.07:43:52.33#ibcon#about to read 4, iclass 21, count 0 2006.190.07:43:52.33#ibcon#read 4, iclass 21, count 0 2006.190.07:43:52.33#ibcon#about to read 5, iclass 21, count 0 2006.190.07:43:52.33#ibcon#read 5, iclass 21, count 0 2006.190.07:43:52.33#ibcon#about to read 6, iclass 21, count 0 2006.190.07:43:52.33#ibcon#read 6, iclass 21, count 0 2006.190.07:43:52.33#ibcon#end of sib2, iclass 21, count 0 2006.190.07:43:52.33#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:43:52.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:43:52.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:43:52.33#ibcon#*before write, iclass 21, count 0 2006.190.07:43:52.33#ibcon#enter sib2, iclass 21, count 0 2006.190.07:43:52.33#ibcon#flushed, iclass 21, count 0 2006.190.07:43:52.33#ibcon#about to write, iclass 21, count 0 2006.190.07:43:52.33#ibcon#wrote, iclass 21, count 0 2006.190.07:43:52.33#ibcon#about to read 3, iclass 21, count 0 2006.190.07:43:52.37#ibcon#read 3, iclass 21, count 0 2006.190.07:43:52.37#ibcon#about to read 4, iclass 21, count 0 2006.190.07:43:52.37#ibcon#read 4, iclass 21, count 0 2006.190.07:43:52.37#ibcon#about to read 5, iclass 21, count 0 2006.190.07:43:52.37#ibcon#read 5, iclass 21, count 0 2006.190.07:43:52.37#ibcon#about to read 6, iclass 21, count 0 2006.190.07:43:52.37#ibcon#read 6, iclass 21, count 0 2006.190.07:43:52.37#ibcon#end of sib2, iclass 21, count 0 2006.190.07:43:52.37#ibcon#*after write, iclass 21, count 0 2006.190.07:43:52.37#ibcon#*before return 0, iclass 21, count 0 2006.190.07:43:52.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:52.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:43:52.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:43:52.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:43:52.37$vc4f8/vb=6,4 2006.190.07:43:52.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.07:43:52.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.07:43:52.37#ibcon#ireg 11 cls_cnt 2 2006.190.07:43:52.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:52.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:52.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:52.43#ibcon#enter wrdev, iclass 23, count 2 2006.190.07:43:52.43#ibcon#first serial, iclass 23, count 2 2006.190.07:43:52.43#ibcon#enter sib2, iclass 23, count 2 2006.190.07:43:52.43#ibcon#flushed, iclass 23, count 2 2006.190.07:43:52.43#ibcon#about to write, iclass 23, count 2 2006.190.07:43:52.43#ibcon#wrote, iclass 23, count 2 2006.190.07:43:52.43#ibcon#about to read 3, iclass 23, count 2 2006.190.07:43:52.45#ibcon#read 3, iclass 23, count 2 2006.190.07:43:52.45#ibcon#about to read 4, iclass 23, count 2 2006.190.07:43:52.45#ibcon#read 4, iclass 23, count 2 2006.190.07:43:52.45#ibcon#about to read 5, iclass 23, count 2 2006.190.07:43:52.45#ibcon#read 5, iclass 23, count 2 2006.190.07:43:52.45#ibcon#about to read 6, iclass 23, count 2 2006.190.07:43:52.45#ibcon#read 6, iclass 23, count 2 2006.190.07:43:52.45#ibcon#end of sib2, iclass 23, count 2 2006.190.07:43:52.45#ibcon#*mode == 0, iclass 23, count 2 2006.190.07:43:52.45#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.07:43:52.45#ibcon#[27=AT06-04\r\n] 2006.190.07:43:52.45#ibcon#*before write, iclass 23, count 2 2006.190.07:43:52.45#ibcon#enter sib2, iclass 23, count 2 2006.190.07:43:52.45#ibcon#flushed, iclass 23, count 2 2006.190.07:43:52.45#ibcon#about to write, iclass 23, count 2 2006.190.07:43:52.45#ibcon#wrote, iclass 23, count 2 2006.190.07:43:52.45#ibcon#about to read 3, iclass 23, count 2 2006.190.07:43:52.48#ibcon#read 3, iclass 23, count 2 2006.190.07:43:52.48#ibcon#about to read 4, iclass 23, count 2 2006.190.07:43:52.48#ibcon#read 4, iclass 23, count 2 2006.190.07:43:52.48#ibcon#about to read 5, iclass 23, count 2 2006.190.07:43:52.48#ibcon#read 5, iclass 23, count 2 2006.190.07:43:52.48#ibcon#about to read 6, iclass 23, count 2 2006.190.07:43:52.48#ibcon#read 6, iclass 23, count 2 2006.190.07:43:52.48#ibcon#end of sib2, iclass 23, count 2 2006.190.07:43:52.48#ibcon#*after write, iclass 23, count 2 2006.190.07:43:52.48#ibcon#*before return 0, iclass 23, count 2 2006.190.07:43:52.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:52.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:43:52.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.07:43:52.48#ibcon#ireg 7 cls_cnt 0 2006.190.07:43:52.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:52.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:52.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:52.60#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:43:52.60#ibcon#first serial, iclass 23, count 0 2006.190.07:43:52.60#ibcon#enter sib2, iclass 23, count 0 2006.190.07:43:52.60#ibcon#flushed, iclass 23, count 0 2006.190.07:43:52.60#ibcon#about to write, iclass 23, count 0 2006.190.07:43:52.60#ibcon#wrote, iclass 23, count 0 2006.190.07:43:52.60#ibcon#about to read 3, iclass 23, count 0 2006.190.07:43:52.62#ibcon#read 3, iclass 23, count 0 2006.190.07:43:52.62#ibcon#about to read 4, iclass 23, count 0 2006.190.07:43:52.62#ibcon#read 4, iclass 23, count 0 2006.190.07:43:52.62#ibcon#about to read 5, iclass 23, count 0 2006.190.07:43:52.62#ibcon#read 5, iclass 23, count 0 2006.190.07:43:52.62#ibcon#about to read 6, iclass 23, count 0 2006.190.07:43:52.62#ibcon#read 6, iclass 23, count 0 2006.190.07:43:52.62#ibcon#end of sib2, iclass 23, count 0 2006.190.07:43:52.62#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:43:52.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:43:52.62#ibcon#[27=USB\r\n] 2006.190.07:43:52.62#ibcon#*before write, iclass 23, count 0 2006.190.07:43:52.62#ibcon#enter sib2, iclass 23, count 0 2006.190.07:43:52.62#ibcon#flushed, iclass 23, count 0 2006.190.07:43:52.62#ibcon#about to write, iclass 23, count 0 2006.190.07:43:52.62#ibcon#wrote, iclass 23, count 0 2006.190.07:43:52.62#ibcon#about to read 3, iclass 23, count 0 2006.190.07:43:52.65#ibcon#read 3, iclass 23, count 0 2006.190.07:43:52.65#ibcon#about to read 4, iclass 23, count 0 2006.190.07:43:52.65#ibcon#read 4, iclass 23, count 0 2006.190.07:43:52.65#ibcon#about to read 5, iclass 23, count 0 2006.190.07:43:52.65#ibcon#read 5, iclass 23, count 0 2006.190.07:43:52.65#ibcon#about to read 6, iclass 23, count 0 2006.190.07:43:52.65#ibcon#read 6, iclass 23, count 0 2006.190.07:43:52.65#ibcon#end of sib2, iclass 23, count 0 2006.190.07:43:52.65#ibcon#*after write, iclass 23, count 0 2006.190.07:43:52.65#ibcon#*before return 0, iclass 23, count 0 2006.190.07:43:52.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:52.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:43:52.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:43:52.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:43:52.65$vc4f8/vabw=wide 2006.190.07:43:52.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.07:43:52.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.07:43:52.65#ibcon#ireg 8 cls_cnt 0 2006.190.07:43:52.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:52.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:52.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:52.65#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:43:52.65#ibcon#first serial, iclass 25, count 0 2006.190.07:43:52.65#ibcon#enter sib2, iclass 25, count 0 2006.190.07:43:52.65#ibcon#flushed, iclass 25, count 0 2006.190.07:43:52.65#ibcon#about to write, iclass 25, count 0 2006.190.07:43:52.65#ibcon#wrote, iclass 25, count 0 2006.190.07:43:52.65#ibcon#about to read 3, iclass 25, count 0 2006.190.07:43:52.67#ibcon#read 3, iclass 25, count 0 2006.190.07:43:52.67#ibcon#about to read 4, iclass 25, count 0 2006.190.07:43:52.67#ibcon#read 4, iclass 25, count 0 2006.190.07:43:52.67#ibcon#about to read 5, iclass 25, count 0 2006.190.07:43:52.67#ibcon#read 5, iclass 25, count 0 2006.190.07:43:52.67#ibcon#about to read 6, iclass 25, count 0 2006.190.07:43:52.67#ibcon#read 6, iclass 25, count 0 2006.190.07:43:52.67#ibcon#end of sib2, iclass 25, count 0 2006.190.07:43:52.67#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:43:52.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:43:52.67#ibcon#[25=BW32\r\n] 2006.190.07:43:52.67#ibcon#*before write, iclass 25, count 0 2006.190.07:43:52.67#ibcon#enter sib2, iclass 25, count 0 2006.190.07:43:52.67#ibcon#flushed, iclass 25, count 0 2006.190.07:43:52.67#ibcon#about to write, iclass 25, count 0 2006.190.07:43:52.67#ibcon#wrote, iclass 25, count 0 2006.190.07:43:52.67#ibcon#about to read 3, iclass 25, count 0 2006.190.07:43:52.70#ibcon#read 3, iclass 25, count 0 2006.190.07:43:52.70#ibcon#about to read 4, iclass 25, count 0 2006.190.07:43:52.70#ibcon#read 4, iclass 25, count 0 2006.190.07:43:52.70#ibcon#about to read 5, iclass 25, count 0 2006.190.07:43:52.70#ibcon#read 5, iclass 25, count 0 2006.190.07:43:52.70#ibcon#about to read 6, iclass 25, count 0 2006.190.07:43:52.70#ibcon#read 6, iclass 25, count 0 2006.190.07:43:52.70#ibcon#end of sib2, iclass 25, count 0 2006.190.07:43:52.70#ibcon#*after write, iclass 25, count 0 2006.190.07:43:52.70#ibcon#*before return 0, iclass 25, count 0 2006.190.07:43:52.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:52.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:43:52.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:43:52.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:43:52.70$vc4f8/vbbw=wide 2006.190.07:43:52.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.07:43:52.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.07:43:52.70#ibcon#ireg 8 cls_cnt 0 2006.190.07:43:52.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:43:52.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:43:52.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:43:52.77#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:43:52.77#ibcon#first serial, iclass 27, count 0 2006.190.07:43:52.77#ibcon#enter sib2, iclass 27, count 0 2006.190.07:43:52.77#ibcon#flushed, iclass 27, count 0 2006.190.07:43:52.77#ibcon#about to write, iclass 27, count 0 2006.190.07:43:52.77#ibcon#wrote, iclass 27, count 0 2006.190.07:43:52.77#ibcon#about to read 3, iclass 27, count 0 2006.190.07:43:52.79#ibcon#read 3, iclass 27, count 0 2006.190.07:43:52.79#ibcon#about to read 4, iclass 27, count 0 2006.190.07:43:52.79#ibcon#read 4, iclass 27, count 0 2006.190.07:43:52.79#ibcon#about to read 5, iclass 27, count 0 2006.190.07:43:52.79#ibcon#read 5, iclass 27, count 0 2006.190.07:43:52.79#ibcon#about to read 6, iclass 27, count 0 2006.190.07:43:52.79#ibcon#read 6, iclass 27, count 0 2006.190.07:43:52.79#ibcon#end of sib2, iclass 27, count 0 2006.190.07:43:52.79#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:43:52.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:43:52.79#ibcon#[27=BW32\r\n] 2006.190.07:43:52.79#ibcon#*before write, iclass 27, count 0 2006.190.07:43:52.79#ibcon#enter sib2, iclass 27, count 0 2006.190.07:43:52.79#ibcon#flushed, iclass 27, count 0 2006.190.07:43:52.79#ibcon#about to write, iclass 27, count 0 2006.190.07:43:52.79#ibcon#wrote, iclass 27, count 0 2006.190.07:43:52.79#ibcon#about to read 3, iclass 27, count 0 2006.190.07:43:52.82#ibcon#read 3, iclass 27, count 0 2006.190.07:43:52.82#ibcon#about to read 4, iclass 27, count 0 2006.190.07:43:52.82#ibcon#read 4, iclass 27, count 0 2006.190.07:43:52.82#ibcon#about to read 5, iclass 27, count 0 2006.190.07:43:52.82#ibcon#read 5, iclass 27, count 0 2006.190.07:43:52.82#ibcon#about to read 6, iclass 27, count 0 2006.190.07:43:52.82#ibcon#read 6, iclass 27, count 0 2006.190.07:43:52.82#ibcon#end of sib2, iclass 27, count 0 2006.190.07:43:52.82#ibcon#*after write, iclass 27, count 0 2006.190.07:43:52.82#ibcon#*before return 0, iclass 27, count 0 2006.190.07:43:52.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:43:52.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:43:52.82#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:43:52.82#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:43:52.82$4f8m12a/ifd4f 2006.190.07:43:52.82$ifd4f/lo= 2006.190.07:43:52.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:43:52.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:43:52.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:43:52.82$ifd4f/patch= 2006.190.07:43:52.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:43:52.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:43:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:43:52.82$4f8m12a/"form=m,16.000,1:2 2006.190.07:43:52.82$4f8m12a/"tpicd 2006.190.07:43:52.82$4f8m12a/echo=off 2006.190.07:43:52.82$4f8m12a/xlog=off 2006.190.07:43:52.82:!2006.190.07:44:20 2006.190.07:44:03.14#trakl#Source acquired 2006.190.07:44:05.14#flagr#flagr/antenna,acquired 2006.190.07:44:20.00:preob 2006.190.07:44:21.14/onsource/TRACKING 2006.190.07:44:21.14:!2006.190.07:44:30 2006.190.07:44:30.00:data_valid=on 2006.190.07:44:30.00:midob 2006.190.07:44:30.14/onsource/TRACKING 2006.190.07:44:30.14/wx/24.50,1012.2,100 2006.190.07:44:30.24/cable/+6.4711E-03 2006.190.07:44:31.33/va/01,08,usb,yes,36,38 2006.190.07:44:31.33/va/02,07,usb,yes,37,38 2006.190.07:44:31.33/va/03,06,usb,yes,39,39 2006.190.07:44:31.33/va/04,07,usb,yes,38,40 2006.190.07:44:31.33/va/05,07,usb,yes,41,43 2006.190.07:44:31.33/va/06,06,usb,yes,41,40 2006.190.07:44:31.33/va/07,06,usb,yes,41,41 2006.190.07:44:31.33/va/08,06,usb,yes,44,43 2006.190.07:44:31.56/valo/01,532.99,yes,locked 2006.190.07:44:31.56/valo/02,572.99,yes,locked 2006.190.07:44:31.56/valo/03,672.99,yes,locked 2006.190.07:44:31.56/valo/04,832.99,yes,locked 2006.190.07:44:31.56/valo/05,652.99,yes,locked 2006.190.07:44:31.56/valo/06,772.99,yes,locked 2006.190.07:44:31.56/valo/07,832.99,yes,locked 2006.190.07:44:31.56/valo/08,852.99,yes,locked 2006.190.07:44:32.65/vb/01,04,usb,yes,30,28 2006.190.07:44:32.65/vb/02,04,usb,yes,31,33 2006.190.07:44:32.65/vb/03,04,usb,yes,28,32 2006.190.07:44:32.65/vb/04,04,usb,yes,29,29 2006.190.07:44:32.65/vb/05,04,usb,yes,27,31 2006.190.07:44:32.65/vb/06,04,usb,yes,28,31 2006.190.07:44:32.65/vb/07,04,usb,yes,30,30 2006.190.07:44:32.65/vb/08,04,usb,yes,28,31 2006.190.07:44:32.89/vblo/01,632.99,yes,locked 2006.190.07:44:32.89/vblo/02,640.99,yes,locked 2006.190.07:44:32.89/vblo/03,656.99,yes,locked 2006.190.07:44:32.89/vblo/04,712.99,yes,locked 2006.190.07:44:32.89/vblo/05,744.99,yes,locked 2006.190.07:44:32.89/vblo/06,752.99,yes,locked 2006.190.07:44:32.89/vblo/07,734.99,yes,locked 2006.190.07:44:32.89/vblo/08,744.99,yes,locked 2006.190.07:44:33.04/vabw/8 2006.190.07:44:33.19/vbbw/8 2006.190.07:44:33.28/xfe/off,on,14.7 2006.190.07:44:33.67/ifatt/23,28,28,28 2006.190.07:44:34.08/fmout-gps/S +2.87E-07 2006.190.07:44:34.16:!2006.190.07:45:30 2006.190.07:45:30.01:data_valid=off 2006.190.07:45:30.01:postob 2006.190.07:45:30.20/cable/+6.4699E-03 2006.190.07:45:30.20/wx/24.51,1012.1,100 2006.190.07:45:31.08/fmout-gps/S +2.87E-07 2006.190.07:45:31.08:scan_name=190-0746,k06190,60 2006.190.07:45:31.09:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.190.07:45:31.14#flagr#flagr/antenna,new-source 2006.190.07:45:32.14:checkk5 2006.190.07:45:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:45:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:45:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:45:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:45:34.05/chk_obsdata//k5ts1/T1900744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:45:34.42/chk_obsdata//k5ts2/T1900744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:45:34.81/chk_obsdata//k5ts3/T1900744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:45:35.19/chk_obsdata//k5ts4/T1900744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:45:35.90/k5log//k5ts1_log_newline 2006.190.07:45:36.61/k5log//k5ts2_log_newline 2006.190.07:45:37.33/k5log//k5ts3_log_newline 2006.190.07:45:38.03/k5log//k5ts4_log_newline 2006.190.07:45:38.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:45:38.10:4f8m12a=1 2006.190.07:45:38.10$4f8m12a/echo=on 2006.190.07:45:38.10$4f8m12a/pcalon 2006.190.07:45:38.10$pcalon/"no phase cal control is implemented here 2006.190.07:45:38.10$4f8m12a/"tpicd=stop 2006.190.07:45:38.10$4f8m12a/vc4f8 2006.190.07:45:38.10$vc4f8/valo=1,532.99 2006.190.07:45:38.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.07:45:38.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.07:45:38.10#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:38.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:38.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:38.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:38.10#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:45:38.10#ibcon#first serial, iclass 34, count 0 2006.190.07:45:38.10#ibcon#enter sib2, iclass 34, count 0 2006.190.07:45:38.10#ibcon#flushed, iclass 34, count 0 2006.190.07:45:38.10#ibcon#about to write, iclass 34, count 0 2006.190.07:45:38.10#ibcon#wrote, iclass 34, count 0 2006.190.07:45:38.10#ibcon#about to read 3, iclass 34, count 0 2006.190.07:45:38.12#ibcon#read 3, iclass 34, count 0 2006.190.07:45:38.12#ibcon#about to read 4, iclass 34, count 0 2006.190.07:45:38.12#ibcon#read 4, iclass 34, count 0 2006.190.07:45:38.12#ibcon#about to read 5, iclass 34, count 0 2006.190.07:45:38.12#ibcon#read 5, iclass 34, count 0 2006.190.07:45:38.12#ibcon#about to read 6, iclass 34, count 0 2006.190.07:45:38.12#ibcon#read 6, iclass 34, count 0 2006.190.07:45:38.12#ibcon#end of sib2, iclass 34, count 0 2006.190.07:45:38.12#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:45:38.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:45:38.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:45:38.12#ibcon#*before write, iclass 34, count 0 2006.190.07:45:38.12#ibcon#enter sib2, iclass 34, count 0 2006.190.07:45:38.12#ibcon#flushed, iclass 34, count 0 2006.190.07:45:38.12#ibcon#about to write, iclass 34, count 0 2006.190.07:45:38.12#ibcon#wrote, iclass 34, count 0 2006.190.07:45:38.12#ibcon#about to read 3, iclass 34, count 0 2006.190.07:45:38.17#ibcon#read 3, iclass 34, count 0 2006.190.07:45:38.17#ibcon#about to read 4, iclass 34, count 0 2006.190.07:45:38.17#ibcon#read 4, iclass 34, count 0 2006.190.07:45:38.17#ibcon#about to read 5, iclass 34, count 0 2006.190.07:45:38.17#ibcon#read 5, iclass 34, count 0 2006.190.07:45:38.17#ibcon#about to read 6, iclass 34, count 0 2006.190.07:45:38.17#ibcon#read 6, iclass 34, count 0 2006.190.07:45:38.17#ibcon#end of sib2, iclass 34, count 0 2006.190.07:45:38.17#ibcon#*after write, iclass 34, count 0 2006.190.07:45:38.17#ibcon#*before return 0, iclass 34, count 0 2006.190.07:45:38.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:38.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:38.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:45:38.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:45:38.17$vc4f8/va=1,8 2006.190.07:45:38.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.07:45:38.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.07:45:38.17#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:38.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:38.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:38.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:38.17#ibcon#enter wrdev, iclass 36, count 2 2006.190.07:45:38.17#ibcon#first serial, iclass 36, count 2 2006.190.07:45:38.17#ibcon#enter sib2, iclass 36, count 2 2006.190.07:45:38.17#ibcon#flushed, iclass 36, count 2 2006.190.07:45:38.17#ibcon#about to write, iclass 36, count 2 2006.190.07:45:38.17#ibcon#wrote, iclass 36, count 2 2006.190.07:45:38.17#ibcon#about to read 3, iclass 36, count 2 2006.190.07:45:38.19#ibcon#read 3, iclass 36, count 2 2006.190.07:45:38.19#ibcon#about to read 4, iclass 36, count 2 2006.190.07:45:38.19#ibcon#read 4, iclass 36, count 2 2006.190.07:45:38.19#ibcon#about to read 5, iclass 36, count 2 2006.190.07:45:38.19#ibcon#read 5, iclass 36, count 2 2006.190.07:45:38.19#ibcon#about to read 6, iclass 36, count 2 2006.190.07:45:38.19#ibcon#read 6, iclass 36, count 2 2006.190.07:45:38.19#ibcon#end of sib2, iclass 36, count 2 2006.190.07:45:38.19#ibcon#*mode == 0, iclass 36, count 2 2006.190.07:45:38.19#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.07:45:38.19#ibcon#[25=AT01-08\r\n] 2006.190.07:45:38.19#ibcon#*before write, iclass 36, count 2 2006.190.07:45:38.19#ibcon#enter sib2, iclass 36, count 2 2006.190.07:45:38.19#ibcon#flushed, iclass 36, count 2 2006.190.07:45:38.19#ibcon#about to write, iclass 36, count 2 2006.190.07:45:38.19#ibcon#wrote, iclass 36, count 2 2006.190.07:45:38.19#ibcon#about to read 3, iclass 36, count 2 2006.190.07:45:38.22#ibcon#read 3, iclass 36, count 2 2006.190.07:45:38.22#ibcon#about to read 4, iclass 36, count 2 2006.190.07:45:38.22#ibcon#read 4, iclass 36, count 2 2006.190.07:45:38.22#ibcon#about to read 5, iclass 36, count 2 2006.190.07:45:38.22#ibcon#read 5, iclass 36, count 2 2006.190.07:45:38.22#ibcon#about to read 6, iclass 36, count 2 2006.190.07:45:38.22#ibcon#read 6, iclass 36, count 2 2006.190.07:45:38.22#ibcon#end of sib2, iclass 36, count 2 2006.190.07:45:38.22#ibcon#*after write, iclass 36, count 2 2006.190.07:45:38.22#ibcon#*before return 0, iclass 36, count 2 2006.190.07:45:38.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:38.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:38.22#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.07:45:38.22#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:38.22#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:38.34#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:38.34#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:38.34#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:45:38.34#ibcon#first serial, iclass 36, count 0 2006.190.07:45:38.34#ibcon#enter sib2, iclass 36, count 0 2006.190.07:45:38.34#ibcon#flushed, iclass 36, count 0 2006.190.07:45:38.34#ibcon#about to write, iclass 36, count 0 2006.190.07:45:38.34#ibcon#wrote, iclass 36, count 0 2006.190.07:45:38.34#ibcon#about to read 3, iclass 36, count 0 2006.190.07:45:38.36#ibcon#read 3, iclass 36, count 0 2006.190.07:45:38.36#ibcon#about to read 4, iclass 36, count 0 2006.190.07:45:38.36#ibcon#read 4, iclass 36, count 0 2006.190.07:45:38.36#ibcon#about to read 5, iclass 36, count 0 2006.190.07:45:38.36#ibcon#read 5, iclass 36, count 0 2006.190.07:45:38.36#ibcon#about to read 6, iclass 36, count 0 2006.190.07:45:38.36#ibcon#read 6, iclass 36, count 0 2006.190.07:45:38.36#ibcon#end of sib2, iclass 36, count 0 2006.190.07:45:38.36#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:45:38.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:45:38.36#ibcon#[25=USB\r\n] 2006.190.07:45:38.36#ibcon#*before write, iclass 36, count 0 2006.190.07:45:38.36#ibcon#enter sib2, iclass 36, count 0 2006.190.07:45:38.36#ibcon#flushed, iclass 36, count 0 2006.190.07:45:38.36#ibcon#about to write, iclass 36, count 0 2006.190.07:45:38.36#ibcon#wrote, iclass 36, count 0 2006.190.07:45:38.36#ibcon#about to read 3, iclass 36, count 0 2006.190.07:45:38.39#ibcon#read 3, iclass 36, count 0 2006.190.07:45:38.39#ibcon#about to read 4, iclass 36, count 0 2006.190.07:45:38.39#ibcon#read 4, iclass 36, count 0 2006.190.07:45:38.39#ibcon#about to read 5, iclass 36, count 0 2006.190.07:45:38.39#ibcon#read 5, iclass 36, count 0 2006.190.07:45:38.39#ibcon#about to read 6, iclass 36, count 0 2006.190.07:45:38.39#ibcon#read 6, iclass 36, count 0 2006.190.07:45:38.39#ibcon#end of sib2, iclass 36, count 0 2006.190.07:45:38.39#ibcon#*after write, iclass 36, count 0 2006.190.07:45:38.39#ibcon#*before return 0, iclass 36, count 0 2006.190.07:45:38.39#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:38.39#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:38.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:45:38.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:45:38.39$vc4f8/valo=2,572.99 2006.190.07:45:38.39#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.07:45:38.39#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.07:45:38.39#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:38.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:38.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:38.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:38.39#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:45:38.39#ibcon#first serial, iclass 38, count 0 2006.190.07:45:38.39#ibcon#enter sib2, iclass 38, count 0 2006.190.07:45:38.39#ibcon#flushed, iclass 38, count 0 2006.190.07:45:38.39#ibcon#about to write, iclass 38, count 0 2006.190.07:45:38.39#ibcon#wrote, iclass 38, count 0 2006.190.07:45:38.39#ibcon#about to read 3, iclass 38, count 0 2006.190.07:45:38.41#ibcon#read 3, iclass 38, count 0 2006.190.07:45:38.41#ibcon#about to read 4, iclass 38, count 0 2006.190.07:45:38.41#ibcon#read 4, iclass 38, count 0 2006.190.07:45:38.41#ibcon#about to read 5, iclass 38, count 0 2006.190.07:45:38.41#ibcon#read 5, iclass 38, count 0 2006.190.07:45:38.41#ibcon#about to read 6, iclass 38, count 0 2006.190.07:45:38.41#ibcon#read 6, iclass 38, count 0 2006.190.07:45:38.41#ibcon#end of sib2, iclass 38, count 0 2006.190.07:45:38.41#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:45:38.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:45:38.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:45:38.41#ibcon#*before write, iclass 38, count 0 2006.190.07:45:38.41#ibcon#enter sib2, iclass 38, count 0 2006.190.07:45:38.41#ibcon#flushed, iclass 38, count 0 2006.190.07:45:38.41#ibcon#about to write, iclass 38, count 0 2006.190.07:45:38.41#ibcon#wrote, iclass 38, count 0 2006.190.07:45:38.41#ibcon#about to read 3, iclass 38, count 0 2006.190.07:45:38.45#ibcon#read 3, iclass 38, count 0 2006.190.07:45:38.45#ibcon#about to read 4, iclass 38, count 0 2006.190.07:45:38.45#ibcon#read 4, iclass 38, count 0 2006.190.07:45:38.45#ibcon#about to read 5, iclass 38, count 0 2006.190.07:45:38.45#ibcon#read 5, iclass 38, count 0 2006.190.07:45:38.45#ibcon#about to read 6, iclass 38, count 0 2006.190.07:45:38.45#ibcon#read 6, iclass 38, count 0 2006.190.07:45:38.45#ibcon#end of sib2, iclass 38, count 0 2006.190.07:45:38.45#ibcon#*after write, iclass 38, count 0 2006.190.07:45:38.45#ibcon#*before return 0, iclass 38, count 0 2006.190.07:45:38.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:38.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:38.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:45:38.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:45:38.45$vc4f8/va=2,7 2006.190.07:45:38.45#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.07:45:38.45#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.07:45:38.45#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:38.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:38.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:38.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:38.51#ibcon#enter wrdev, iclass 40, count 2 2006.190.07:45:38.51#ibcon#first serial, iclass 40, count 2 2006.190.07:45:38.51#ibcon#enter sib2, iclass 40, count 2 2006.190.07:45:38.51#ibcon#flushed, iclass 40, count 2 2006.190.07:45:38.51#ibcon#about to write, iclass 40, count 2 2006.190.07:45:38.51#ibcon#wrote, iclass 40, count 2 2006.190.07:45:38.51#ibcon#about to read 3, iclass 40, count 2 2006.190.07:45:38.53#ibcon#read 3, iclass 40, count 2 2006.190.07:45:38.53#ibcon#about to read 4, iclass 40, count 2 2006.190.07:45:38.53#ibcon#read 4, iclass 40, count 2 2006.190.07:45:38.53#ibcon#about to read 5, iclass 40, count 2 2006.190.07:45:38.53#ibcon#read 5, iclass 40, count 2 2006.190.07:45:38.53#ibcon#about to read 6, iclass 40, count 2 2006.190.07:45:38.53#ibcon#read 6, iclass 40, count 2 2006.190.07:45:38.53#ibcon#end of sib2, iclass 40, count 2 2006.190.07:45:38.53#ibcon#*mode == 0, iclass 40, count 2 2006.190.07:45:38.53#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.07:45:38.53#ibcon#[25=AT02-07\r\n] 2006.190.07:45:38.53#ibcon#*before write, iclass 40, count 2 2006.190.07:45:38.53#ibcon#enter sib2, iclass 40, count 2 2006.190.07:45:38.53#ibcon#flushed, iclass 40, count 2 2006.190.07:45:38.53#ibcon#about to write, iclass 40, count 2 2006.190.07:45:38.53#ibcon#wrote, iclass 40, count 2 2006.190.07:45:38.53#ibcon#about to read 3, iclass 40, count 2 2006.190.07:45:38.56#ibcon#read 3, iclass 40, count 2 2006.190.07:45:38.56#ibcon#about to read 4, iclass 40, count 2 2006.190.07:45:38.56#ibcon#read 4, iclass 40, count 2 2006.190.07:45:38.56#ibcon#about to read 5, iclass 40, count 2 2006.190.07:45:38.56#ibcon#read 5, iclass 40, count 2 2006.190.07:45:38.56#ibcon#about to read 6, iclass 40, count 2 2006.190.07:45:38.56#ibcon#read 6, iclass 40, count 2 2006.190.07:45:38.56#ibcon#end of sib2, iclass 40, count 2 2006.190.07:45:38.56#ibcon#*after write, iclass 40, count 2 2006.190.07:45:38.56#ibcon#*before return 0, iclass 40, count 2 2006.190.07:45:38.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:38.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:38.56#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.07:45:38.56#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:38.56#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:38.68#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:38.68#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:38.68#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:45:38.68#ibcon#first serial, iclass 40, count 0 2006.190.07:45:38.68#ibcon#enter sib2, iclass 40, count 0 2006.190.07:45:38.68#ibcon#flushed, iclass 40, count 0 2006.190.07:45:38.68#ibcon#about to write, iclass 40, count 0 2006.190.07:45:38.68#ibcon#wrote, iclass 40, count 0 2006.190.07:45:38.68#ibcon#about to read 3, iclass 40, count 0 2006.190.07:45:38.70#ibcon#read 3, iclass 40, count 0 2006.190.07:45:38.70#ibcon#about to read 4, iclass 40, count 0 2006.190.07:45:38.70#ibcon#read 4, iclass 40, count 0 2006.190.07:45:38.70#ibcon#about to read 5, iclass 40, count 0 2006.190.07:45:38.70#ibcon#read 5, iclass 40, count 0 2006.190.07:45:38.70#ibcon#about to read 6, iclass 40, count 0 2006.190.07:45:38.70#ibcon#read 6, iclass 40, count 0 2006.190.07:45:38.70#ibcon#end of sib2, iclass 40, count 0 2006.190.07:45:38.70#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:45:38.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:45:38.70#ibcon#[25=USB\r\n] 2006.190.07:45:38.70#ibcon#*before write, iclass 40, count 0 2006.190.07:45:38.70#ibcon#enter sib2, iclass 40, count 0 2006.190.07:45:38.70#ibcon#flushed, iclass 40, count 0 2006.190.07:45:38.70#ibcon#about to write, iclass 40, count 0 2006.190.07:45:38.70#ibcon#wrote, iclass 40, count 0 2006.190.07:45:38.70#ibcon#about to read 3, iclass 40, count 0 2006.190.07:45:38.73#ibcon#read 3, iclass 40, count 0 2006.190.07:45:38.73#ibcon#about to read 4, iclass 40, count 0 2006.190.07:45:38.73#ibcon#read 4, iclass 40, count 0 2006.190.07:45:38.73#ibcon#about to read 5, iclass 40, count 0 2006.190.07:45:38.73#ibcon#read 5, iclass 40, count 0 2006.190.07:45:38.73#ibcon#about to read 6, iclass 40, count 0 2006.190.07:45:38.73#ibcon#read 6, iclass 40, count 0 2006.190.07:45:38.73#ibcon#end of sib2, iclass 40, count 0 2006.190.07:45:38.73#ibcon#*after write, iclass 40, count 0 2006.190.07:45:38.73#ibcon#*before return 0, iclass 40, count 0 2006.190.07:45:38.73#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:38.73#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:38.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:45:38.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:45:38.73$vc4f8/valo=3,672.99 2006.190.07:45:38.73#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.07:45:38.73#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.07:45:38.73#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:38.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:38.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:38.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:38.73#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:45:38.73#ibcon#first serial, iclass 4, count 0 2006.190.07:45:38.73#ibcon#enter sib2, iclass 4, count 0 2006.190.07:45:38.73#ibcon#flushed, iclass 4, count 0 2006.190.07:45:38.73#ibcon#about to write, iclass 4, count 0 2006.190.07:45:38.73#ibcon#wrote, iclass 4, count 0 2006.190.07:45:38.73#ibcon#about to read 3, iclass 4, count 0 2006.190.07:45:38.75#ibcon#read 3, iclass 4, count 0 2006.190.07:45:38.75#ibcon#about to read 4, iclass 4, count 0 2006.190.07:45:38.75#ibcon#read 4, iclass 4, count 0 2006.190.07:45:38.75#ibcon#about to read 5, iclass 4, count 0 2006.190.07:45:38.75#ibcon#read 5, iclass 4, count 0 2006.190.07:45:38.75#ibcon#about to read 6, iclass 4, count 0 2006.190.07:45:38.75#ibcon#read 6, iclass 4, count 0 2006.190.07:45:38.75#ibcon#end of sib2, iclass 4, count 0 2006.190.07:45:38.75#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:45:38.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:45:38.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:45:38.75#ibcon#*before write, iclass 4, count 0 2006.190.07:45:38.75#ibcon#enter sib2, iclass 4, count 0 2006.190.07:45:38.75#ibcon#flushed, iclass 4, count 0 2006.190.07:45:38.75#ibcon#about to write, iclass 4, count 0 2006.190.07:45:38.75#ibcon#wrote, iclass 4, count 0 2006.190.07:45:38.75#ibcon#about to read 3, iclass 4, count 0 2006.190.07:45:38.79#ibcon#read 3, iclass 4, count 0 2006.190.07:45:38.79#ibcon#about to read 4, iclass 4, count 0 2006.190.07:45:38.79#ibcon#read 4, iclass 4, count 0 2006.190.07:45:38.79#ibcon#about to read 5, iclass 4, count 0 2006.190.07:45:38.79#ibcon#read 5, iclass 4, count 0 2006.190.07:45:38.79#ibcon#about to read 6, iclass 4, count 0 2006.190.07:45:38.79#ibcon#read 6, iclass 4, count 0 2006.190.07:45:38.79#ibcon#end of sib2, iclass 4, count 0 2006.190.07:45:38.79#ibcon#*after write, iclass 4, count 0 2006.190.07:45:38.79#ibcon#*before return 0, iclass 4, count 0 2006.190.07:45:38.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:38.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:38.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:45:38.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:45:38.79$vc4f8/va=3,6 2006.190.07:45:38.79#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.07:45:38.79#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.07:45:38.79#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:38.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:38.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:38.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:38.85#ibcon#enter wrdev, iclass 6, count 2 2006.190.07:45:38.85#ibcon#first serial, iclass 6, count 2 2006.190.07:45:38.85#ibcon#enter sib2, iclass 6, count 2 2006.190.07:45:38.85#ibcon#flushed, iclass 6, count 2 2006.190.07:45:38.85#ibcon#about to write, iclass 6, count 2 2006.190.07:45:38.85#ibcon#wrote, iclass 6, count 2 2006.190.07:45:38.85#ibcon#about to read 3, iclass 6, count 2 2006.190.07:45:38.87#ibcon#read 3, iclass 6, count 2 2006.190.07:45:38.87#ibcon#about to read 4, iclass 6, count 2 2006.190.07:45:38.87#ibcon#read 4, iclass 6, count 2 2006.190.07:45:38.87#ibcon#about to read 5, iclass 6, count 2 2006.190.07:45:38.87#ibcon#read 5, iclass 6, count 2 2006.190.07:45:38.87#ibcon#about to read 6, iclass 6, count 2 2006.190.07:45:38.87#ibcon#read 6, iclass 6, count 2 2006.190.07:45:38.87#ibcon#end of sib2, iclass 6, count 2 2006.190.07:45:38.87#ibcon#*mode == 0, iclass 6, count 2 2006.190.07:45:38.87#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.07:45:38.87#ibcon#[25=AT03-06\r\n] 2006.190.07:45:38.87#ibcon#*before write, iclass 6, count 2 2006.190.07:45:38.87#ibcon#enter sib2, iclass 6, count 2 2006.190.07:45:38.87#ibcon#flushed, iclass 6, count 2 2006.190.07:45:38.87#ibcon#about to write, iclass 6, count 2 2006.190.07:45:38.87#ibcon#wrote, iclass 6, count 2 2006.190.07:45:38.87#ibcon#about to read 3, iclass 6, count 2 2006.190.07:45:38.90#ibcon#read 3, iclass 6, count 2 2006.190.07:45:38.90#ibcon#about to read 4, iclass 6, count 2 2006.190.07:45:38.90#ibcon#read 4, iclass 6, count 2 2006.190.07:45:38.90#ibcon#about to read 5, iclass 6, count 2 2006.190.07:45:38.90#ibcon#read 5, iclass 6, count 2 2006.190.07:45:38.90#ibcon#about to read 6, iclass 6, count 2 2006.190.07:45:38.90#ibcon#read 6, iclass 6, count 2 2006.190.07:45:38.90#ibcon#end of sib2, iclass 6, count 2 2006.190.07:45:38.90#ibcon#*after write, iclass 6, count 2 2006.190.07:45:38.90#ibcon#*before return 0, iclass 6, count 2 2006.190.07:45:38.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:38.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:38.90#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.07:45:38.90#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:38.90#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:39.02#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:39.02#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:39.02#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:45:39.02#ibcon#first serial, iclass 6, count 0 2006.190.07:45:39.02#ibcon#enter sib2, iclass 6, count 0 2006.190.07:45:39.02#ibcon#flushed, iclass 6, count 0 2006.190.07:45:39.02#ibcon#about to write, iclass 6, count 0 2006.190.07:45:39.02#ibcon#wrote, iclass 6, count 0 2006.190.07:45:39.02#ibcon#about to read 3, iclass 6, count 0 2006.190.07:45:39.04#ibcon#read 3, iclass 6, count 0 2006.190.07:45:39.04#ibcon#about to read 4, iclass 6, count 0 2006.190.07:45:39.04#ibcon#read 4, iclass 6, count 0 2006.190.07:45:39.04#ibcon#about to read 5, iclass 6, count 0 2006.190.07:45:39.04#ibcon#read 5, iclass 6, count 0 2006.190.07:45:39.04#ibcon#about to read 6, iclass 6, count 0 2006.190.07:45:39.04#ibcon#read 6, iclass 6, count 0 2006.190.07:45:39.04#ibcon#end of sib2, iclass 6, count 0 2006.190.07:45:39.04#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:45:39.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:45:39.04#ibcon#[25=USB\r\n] 2006.190.07:45:39.04#ibcon#*before write, iclass 6, count 0 2006.190.07:45:39.04#ibcon#enter sib2, iclass 6, count 0 2006.190.07:45:39.04#ibcon#flushed, iclass 6, count 0 2006.190.07:45:39.04#ibcon#about to write, iclass 6, count 0 2006.190.07:45:39.04#ibcon#wrote, iclass 6, count 0 2006.190.07:45:39.04#ibcon#about to read 3, iclass 6, count 0 2006.190.07:45:39.07#ibcon#read 3, iclass 6, count 0 2006.190.07:45:39.07#ibcon#about to read 4, iclass 6, count 0 2006.190.07:45:39.07#ibcon#read 4, iclass 6, count 0 2006.190.07:45:39.07#ibcon#about to read 5, iclass 6, count 0 2006.190.07:45:39.07#ibcon#read 5, iclass 6, count 0 2006.190.07:45:39.07#ibcon#about to read 6, iclass 6, count 0 2006.190.07:45:39.07#ibcon#read 6, iclass 6, count 0 2006.190.07:45:39.07#ibcon#end of sib2, iclass 6, count 0 2006.190.07:45:39.07#ibcon#*after write, iclass 6, count 0 2006.190.07:45:39.07#ibcon#*before return 0, iclass 6, count 0 2006.190.07:45:39.07#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:39.07#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:39.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:45:39.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:45:39.07$vc4f8/valo=4,832.99 2006.190.07:45:39.07#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.07:45:39.07#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.07:45:39.07#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:39.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:39.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:39.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:39.07#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:45:39.07#ibcon#first serial, iclass 10, count 0 2006.190.07:45:39.07#ibcon#enter sib2, iclass 10, count 0 2006.190.07:45:39.07#ibcon#flushed, iclass 10, count 0 2006.190.07:45:39.07#ibcon#about to write, iclass 10, count 0 2006.190.07:45:39.07#ibcon#wrote, iclass 10, count 0 2006.190.07:45:39.07#ibcon#about to read 3, iclass 10, count 0 2006.190.07:45:39.09#ibcon#read 3, iclass 10, count 0 2006.190.07:45:39.09#ibcon#about to read 4, iclass 10, count 0 2006.190.07:45:39.09#ibcon#read 4, iclass 10, count 0 2006.190.07:45:39.09#ibcon#about to read 5, iclass 10, count 0 2006.190.07:45:39.09#ibcon#read 5, iclass 10, count 0 2006.190.07:45:39.09#ibcon#about to read 6, iclass 10, count 0 2006.190.07:45:39.09#ibcon#read 6, iclass 10, count 0 2006.190.07:45:39.09#ibcon#end of sib2, iclass 10, count 0 2006.190.07:45:39.09#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:45:39.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:45:39.09#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:45:39.09#ibcon#*before write, iclass 10, count 0 2006.190.07:45:39.09#ibcon#enter sib2, iclass 10, count 0 2006.190.07:45:39.09#ibcon#flushed, iclass 10, count 0 2006.190.07:45:39.09#ibcon#about to write, iclass 10, count 0 2006.190.07:45:39.09#ibcon#wrote, iclass 10, count 0 2006.190.07:45:39.09#ibcon#about to read 3, iclass 10, count 0 2006.190.07:45:39.13#ibcon#read 3, iclass 10, count 0 2006.190.07:45:39.13#ibcon#about to read 4, iclass 10, count 0 2006.190.07:45:39.13#ibcon#read 4, iclass 10, count 0 2006.190.07:45:39.13#ibcon#about to read 5, iclass 10, count 0 2006.190.07:45:39.13#ibcon#read 5, iclass 10, count 0 2006.190.07:45:39.13#ibcon#about to read 6, iclass 10, count 0 2006.190.07:45:39.13#ibcon#read 6, iclass 10, count 0 2006.190.07:45:39.13#ibcon#end of sib2, iclass 10, count 0 2006.190.07:45:39.13#ibcon#*after write, iclass 10, count 0 2006.190.07:45:39.13#ibcon#*before return 0, iclass 10, count 0 2006.190.07:45:39.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:39.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:39.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:45:39.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:45:39.13$vc4f8/va=4,7 2006.190.07:45:39.13#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.07:45:39.13#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.07:45:39.13#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:39.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:39.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:39.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:39.19#ibcon#enter wrdev, iclass 12, count 2 2006.190.07:45:39.19#ibcon#first serial, iclass 12, count 2 2006.190.07:45:39.19#ibcon#enter sib2, iclass 12, count 2 2006.190.07:45:39.19#ibcon#flushed, iclass 12, count 2 2006.190.07:45:39.19#ibcon#about to write, iclass 12, count 2 2006.190.07:45:39.19#ibcon#wrote, iclass 12, count 2 2006.190.07:45:39.19#ibcon#about to read 3, iclass 12, count 2 2006.190.07:45:39.21#ibcon#read 3, iclass 12, count 2 2006.190.07:45:39.21#ibcon#about to read 4, iclass 12, count 2 2006.190.07:45:39.21#ibcon#read 4, iclass 12, count 2 2006.190.07:45:39.21#ibcon#about to read 5, iclass 12, count 2 2006.190.07:45:39.21#ibcon#read 5, iclass 12, count 2 2006.190.07:45:39.21#ibcon#about to read 6, iclass 12, count 2 2006.190.07:45:39.21#ibcon#read 6, iclass 12, count 2 2006.190.07:45:39.21#ibcon#end of sib2, iclass 12, count 2 2006.190.07:45:39.21#ibcon#*mode == 0, iclass 12, count 2 2006.190.07:45:39.21#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.07:45:39.21#ibcon#[25=AT04-07\r\n] 2006.190.07:45:39.21#ibcon#*before write, iclass 12, count 2 2006.190.07:45:39.21#ibcon#enter sib2, iclass 12, count 2 2006.190.07:45:39.21#ibcon#flushed, iclass 12, count 2 2006.190.07:45:39.21#ibcon#about to write, iclass 12, count 2 2006.190.07:45:39.21#ibcon#wrote, iclass 12, count 2 2006.190.07:45:39.21#ibcon#about to read 3, iclass 12, count 2 2006.190.07:45:39.24#ibcon#read 3, iclass 12, count 2 2006.190.07:45:39.24#ibcon#about to read 4, iclass 12, count 2 2006.190.07:45:39.24#ibcon#read 4, iclass 12, count 2 2006.190.07:45:39.24#ibcon#about to read 5, iclass 12, count 2 2006.190.07:45:39.24#ibcon#read 5, iclass 12, count 2 2006.190.07:45:39.24#ibcon#about to read 6, iclass 12, count 2 2006.190.07:45:39.24#ibcon#read 6, iclass 12, count 2 2006.190.07:45:39.24#ibcon#end of sib2, iclass 12, count 2 2006.190.07:45:39.24#ibcon#*after write, iclass 12, count 2 2006.190.07:45:39.24#ibcon#*before return 0, iclass 12, count 2 2006.190.07:45:39.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:39.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:39.24#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.07:45:39.24#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:39.24#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:39.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:39.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:39.36#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:45:39.36#ibcon#first serial, iclass 12, count 0 2006.190.07:45:39.36#ibcon#enter sib2, iclass 12, count 0 2006.190.07:45:39.36#ibcon#flushed, iclass 12, count 0 2006.190.07:45:39.36#ibcon#about to write, iclass 12, count 0 2006.190.07:45:39.36#ibcon#wrote, iclass 12, count 0 2006.190.07:45:39.36#ibcon#about to read 3, iclass 12, count 0 2006.190.07:45:39.38#ibcon#read 3, iclass 12, count 0 2006.190.07:45:39.38#ibcon#about to read 4, iclass 12, count 0 2006.190.07:45:39.38#ibcon#read 4, iclass 12, count 0 2006.190.07:45:39.38#ibcon#about to read 5, iclass 12, count 0 2006.190.07:45:39.38#ibcon#read 5, iclass 12, count 0 2006.190.07:45:39.38#ibcon#about to read 6, iclass 12, count 0 2006.190.07:45:39.38#ibcon#read 6, iclass 12, count 0 2006.190.07:45:39.38#ibcon#end of sib2, iclass 12, count 0 2006.190.07:45:39.38#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:45:39.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:45:39.38#ibcon#[25=USB\r\n] 2006.190.07:45:39.38#ibcon#*before write, iclass 12, count 0 2006.190.07:45:39.38#ibcon#enter sib2, iclass 12, count 0 2006.190.07:45:39.38#ibcon#flushed, iclass 12, count 0 2006.190.07:45:39.38#ibcon#about to write, iclass 12, count 0 2006.190.07:45:39.38#ibcon#wrote, iclass 12, count 0 2006.190.07:45:39.38#ibcon#about to read 3, iclass 12, count 0 2006.190.07:45:39.41#ibcon#read 3, iclass 12, count 0 2006.190.07:45:39.41#ibcon#about to read 4, iclass 12, count 0 2006.190.07:45:39.41#ibcon#read 4, iclass 12, count 0 2006.190.07:45:39.41#ibcon#about to read 5, iclass 12, count 0 2006.190.07:45:39.41#ibcon#read 5, iclass 12, count 0 2006.190.07:45:39.41#ibcon#about to read 6, iclass 12, count 0 2006.190.07:45:39.41#ibcon#read 6, iclass 12, count 0 2006.190.07:45:39.41#ibcon#end of sib2, iclass 12, count 0 2006.190.07:45:39.41#ibcon#*after write, iclass 12, count 0 2006.190.07:45:39.41#ibcon#*before return 0, iclass 12, count 0 2006.190.07:45:39.41#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:39.41#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:39.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:45:39.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:45:39.41$vc4f8/valo=5,652.99 2006.190.07:45:39.41#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.07:45:39.41#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.07:45:39.41#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:39.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:39.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:39.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:39.41#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:45:39.41#ibcon#first serial, iclass 14, count 0 2006.190.07:45:39.41#ibcon#enter sib2, iclass 14, count 0 2006.190.07:45:39.41#ibcon#flushed, iclass 14, count 0 2006.190.07:45:39.41#ibcon#about to write, iclass 14, count 0 2006.190.07:45:39.41#ibcon#wrote, iclass 14, count 0 2006.190.07:45:39.41#ibcon#about to read 3, iclass 14, count 0 2006.190.07:45:39.43#ibcon#read 3, iclass 14, count 0 2006.190.07:45:39.43#ibcon#about to read 4, iclass 14, count 0 2006.190.07:45:39.43#ibcon#read 4, iclass 14, count 0 2006.190.07:45:39.43#ibcon#about to read 5, iclass 14, count 0 2006.190.07:45:39.43#ibcon#read 5, iclass 14, count 0 2006.190.07:45:39.43#ibcon#about to read 6, iclass 14, count 0 2006.190.07:45:39.43#ibcon#read 6, iclass 14, count 0 2006.190.07:45:39.43#ibcon#end of sib2, iclass 14, count 0 2006.190.07:45:39.43#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:45:39.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:45:39.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:45:39.43#ibcon#*before write, iclass 14, count 0 2006.190.07:45:39.43#ibcon#enter sib2, iclass 14, count 0 2006.190.07:45:39.43#ibcon#flushed, iclass 14, count 0 2006.190.07:45:39.43#ibcon#about to write, iclass 14, count 0 2006.190.07:45:39.43#ibcon#wrote, iclass 14, count 0 2006.190.07:45:39.43#ibcon#about to read 3, iclass 14, count 0 2006.190.07:45:39.47#ibcon#read 3, iclass 14, count 0 2006.190.07:45:39.47#ibcon#about to read 4, iclass 14, count 0 2006.190.07:45:39.47#ibcon#read 4, iclass 14, count 0 2006.190.07:45:39.47#ibcon#about to read 5, iclass 14, count 0 2006.190.07:45:39.47#ibcon#read 5, iclass 14, count 0 2006.190.07:45:39.47#ibcon#about to read 6, iclass 14, count 0 2006.190.07:45:39.47#ibcon#read 6, iclass 14, count 0 2006.190.07:45:39.47#ibcon#end of sib2, iclass 14, count 0 2006.190.07:45:39.47#ibcon#*after write, iclass 14, count 0 2006.190.07:45:39.47#ibcon#*before return 0, iclass 14, count 0 2006.190.07:45:39.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:39.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:39.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:45:39.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:45:39.47$vc4f8/va=5,7 2006.190.07:45:39.47#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.07:45:39.47#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.07:45:39.47#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:39.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:39.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:39.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:39.53#ibcon#enter wrdev, iclass 16, count 2 2006.190.07:45:39.53#ibcon#first serial, iclass 16, count 2 2006.190.07:45:39.53#ibcon#enter sib2, iclass 16, count 2 2006.190.07:45:39.53#ibcon#flushed, iclass 16, count 2 2006.190.07:45:39.53#ibcon#about to write, iclass 16, count 2 2006.190.07:45:39.53#ibcon#wrote, iclass 16, count 2 2006.190.07:45:39.53#ibcon#about to read 3, iclass 16, count 2 2006.190.07:45:39.55#ibcon#read 3, iclass 16, count 2 2006.190.07:45:39.55#ibcon#about to read 4, iclass 16, count 2 2006.190.07:45:39.55#ibcon#read 4, iclass 16, count 2 2006.190.07:45:39.55#ibcon#about to read 5, iclass 16, count 2 2006.190.07:45:39.55#ibcon#read 5, iclass 16, count 2 2006.190.07:45:39.55#ibcon#about to read 6, iclass 16, count 2 2006.190.07:45:39.55#ibcon#read 6, iclass 16, count 2 2006.190.07:45:39.55#ibcon#end of sib2, iclass 16, count 2 2006.190.07:45:39.55#ibcon#*mode == 0, iclass 16, count 2 2006.190.07:45:39.55#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.07:45:39.55#ibcon#[25=AT05-07\r\n] 2006.190.07:45:39.55#ibcon#*before write, iclass 16, count 2 2006.190.07:45:39.55#ibcon#enter sib2, iclass 16, count 2 2006.190.07:45:39.55#ibcon#flushed, iclass 16, count 2 2006.190.07:45:39.55#ibcon#about to write, iclass 16, count 2 2006.190.07:45:39.55#ibcon#wrote, iclass 16, count 2 2006.190.07:45:39.55#ibcon#about to read 3, iclass 16, count 2 2006.190.07:45:39.58#ibcon#read 3, iclass 16, count 2 2006.190.07:45:39.58#ibcon#about to read 4, iclass 16, count 2 2006.190.07:45:39.58#ibcon#read 4, iclass 16, count 2 2006.190.07:45:39.58#ibcon#about to read 5, iclass 16, count 2 2006.190.07:45:39.58#ibcon#read 5, iclass 16, count 2 2006.190.07:45:39.58#ibcon#about to read 6, iclass 16, count 2 2006.190.07:45:39.58#ibcon#read 6, iclass 16, count 2 2006.190.07:45:39.58#ibcon#end of sib2, iclass 16, count 2 2006.190.07:45:39.58#ibcon#*after write, iclass 16, count 2 2006.190.07:45:39.58#ibcon#*before return 0, iclass 16, count 2 2006.190.07:45:39.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:39.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:39.58#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.07:45:39.58#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:39.58#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:39.70#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:39.70#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:39.70#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:45:39.70#ibcon#first serial, iclass 16, count 0 2006.190.07:45:39.70#ibcon#enter sib2, iclass 16, count 0 2006.190.07:45:39.70#ibcon#flushed, iclass 16, count 0 2006.190.07:45:39.70#ibcon#about to write, iclass 16, count 0 2006.190.07:45:39.70#ibcon#wrote, iclass 16, count 0 2006.190.07:45:39.70#ibcon#about to read 3, iclass 16, count 0 2006.190.07:45:39.72#ibcon#read 3, iclass 16, count 0 2006.190.07:45:39.72#ibcon#about to read 4, iclass 16, count 0 2006.190.07:45:39.72#ibcon#read 4, iclass 16, count 0 2006.190.07:45:39.72#ibcon#about to read 5, iclass 16, count 0 2006.190.07:45:39.72#ibcon#read 5, iclass 16, count 0 2006.190.07:45:39.72#ibcon#about to read 6, iclass 16, count 0 2006.190.07:45:39.72#ibcon#read 6, iclass 16, count 0 2006.190.07:45:39.72#ibcon#end of sib2, iclass 16, count 0 2006.190.07:45:39.72#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:45:39.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:45:39.72#ibcon#[25=USB\r\n] 2006.190.07:45:39.72#ibcon#*before write, iclass 16, count 0 2006.190.07:45:39.72#ibcon#enter sib2, iclass 16, count 0 2006.190.07:45:39.72#ibcon#flushed, iclass 16, count 0 2006.190.07:45:39.72#ibcon#about to write, iclass 16, count 0 2006.190.07:45:39.72#ibcon#wrote, iclass 16, count 0 2006.190.07:45:39.72#ibcon#about to read 3, iclass 16, count 0 2006.190.07:45:39.75#ibcon#read 3, iclass 16, count 0 2006.190.07:45:39.75#ibcon#about to read 4, iclass 16, count 0 2006.190.07:45:39.75#ibcon#read 4, iclass 16, count 0 2006.190.07:45:39.75#ibcon#about to read 5, iclass 16, count 0 2006.190.07:45:39.75#ibcon#read 5, iclass 16, count 0 2006.190.07:45:39.75#ibcon#about to read 6, iclass 16, count 0 2006.190.07:45:39.75#ibcon#read 6, iclass 16, count 0 2006.190.07:45:39.75#ibcon#end of sib2, iclass 16, count 0 2006.190.07:45:39.75#ibcon#*after write, iclass 16, count 0 2006.190.07:45:39.75#ibcon#*before return 0, iclass 16, count 0 2006.190.07:45:39.75#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:39.75#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:39.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:45:39.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:45:39.75$vc4f8/valo=6,772.99 2006.190.07:45:39.75#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.07:45:39.75#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.07:45:39.75#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:39.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:39.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:39.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:39.75#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:45:39.75#ibcon#first serial, iclass 18, count 0 2006.190.07:45:39.75#ibcon#enter sib2, iclass 18, count 0 2006.190.07:45:39.75#ibcon#flushed, iclass 18, count 0 2006.190.07:45:39.75#ibcon#about to write, iclass 18, count 0 2006.190.07:45:39.75#ibcon#wrote, iclass 18, count 0 2006.190.07:45:39.75#ibcon#about to read 3, iclass 18, count 0 2006.190.07:45:39.77#ibcon#read 3, iclass 18, count 0 2006.190.07:45:39.77#ibcon#about to read 4, iclass 18, count 0 2006.190.07:45:39.77#ibcon#read 4, iclass 18, count 0 2006.190.07:45:39.77#ibcon#about to read 5, iclass 18, count 0 2006.190.07:45:39.77#ibcon#read 5, iclass 18, count 0 2006.190.07:45:39.77#ibcon#about to read 6, iclass 18, count 0 2006.190.07:45:39.77#ibcon#read 6, iclass 18, count 0 2006.190.07:45:39.77#ibcon#end of sib2, iclass 18, count 0 2006.190.07:45:39.77#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:45:39.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:45:39.77#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:45:39.77#ibcon#*before write, iclass 18, count 0 2006.190.07:45:39.77#ibcon#enter sib2, iclass 18, count 0 2006.190.07:45:39.77#ibcon#flushed, iclass 18, count 0 2006.190.07:45:39.77#ibcon#about to write, iclass 18, count 0 2006.190.07:45:39.77#ibcon#wrote, iclass 18, count 0 2006.190.07:45:39.77#ibcon#about to read 3, iclass 18, count 0 2006.190.07:45:39.81#ibcon#read 3, iclass 18, count 0 2006.190.07:45:39.81#ibcon#about to read 4, iclass 18, count 0 2006.190.07:45:39.81#ibcon#read 4, iclass 18, count 0 2006.190.07:45:39.81#ibcon#about to read 5, iclass 18, count 0 2006.190.07:45:39.81#ibcon#read 5, iclass 18, count 0 2006.190.07:45:39.81#ibcon#about to read 6, iclass 18, count 0 2006.190.07:45:39.81#ibcon#read 6, iclass 18, count 0 2006.190.07:45:39.81#ibcon#end of sib2, iclass 18, count 0 2006.190.07:45:39.81#ibcon#*after write, iclass 18, count 0 2006.190.07:45:39.81#ibcon#*before return 0, iclass 18, count 0 2006.190.07:45:39.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:39.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:39.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:45:39.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:45:39.81$vc4f8/va=6,6 2006.190.07:45:39.81#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.190.07:45:39.81#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.190.07:45:39.81#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:39.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:45:39.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:45:39.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:45:39.87#ibcon#enter wrdev, iclass 20, count 2 2006.190.07:45:39.87#ibcon#first serial, iclass 20, count 2 2006.190.07:45:39.87#ibcon#enter sib2, iclass 20, count 2 2006.190.07:45:39.87#ibcon#flushed, iclass 20, count 2 2006.190.07:45:39.87#ibcon#about to write, iclass 20, count 2 2006.190.07:45:39.87#ibcon#wrote, iclass 20, count 2 2006.190.07:45:39.87#ibcon#about to read 3, iclass 20, count 2 2006.190.07:45:39.89#ibcon#read 3, iclass 20, count 2 2006.190.07:45:39.89#ibcon#about to read 4, iclass 20, count 2 2006.190.07:45:39.89#ibcon#read 4, iclass 20, count 2 2006.190.07:45:39.89#ibcon#about to read 5, iclass 20, count 2 2006.190.07:45:39.89#ibcon#read 5, iclass 20, count 2 2006.190.07:45:39.89#ibcon#about to read 6, iclass 20, count 2 2006.190.07:45:39.89#ibcon#read 6, iclass 20, count 2 2006.190.07:45:39.89#ibcon#end of sib2, iclass 20, count 2 2006.190.07:45:39.89#ibcon#*mode == 0, iclass 20, count 2 2006.190.07:45:39.89#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.190.07:45:39.89#ibcon#[25=AT06-06\r\n] 2006.190.07:45:39.89#ibcon#*before write, iclass 20, count 2 2006.190.07:45:39.89#ibcon#enter sib2, iclass 20, count 2 2006.190.07:45:39.89#ibcon#flushed, iclass 20, count 2 2006.190.07:45:39.89#ibcon#about to write, iclass 20, count 2 2006.190.07:45:39.89#ibcon#wrote, iclass 20, count 2 2006.190.07:45:39.89#ibcon#about to read 3, iclass 20, count 2 2006.190.07:45:39.92#ibcon#read 3, iclass 20, count 2 2006.190.07:45:39.92#ibcon#about to read 4, iclass 20, count 2 2006.190.07:45:39.92#ibcon#read 4, iclass 20, count 2 2006.190.07:45:39.92#ibcon#about to read 5, iclass 20, count 2 2006.190.07:45:39.92#ibcon#read 5, iclass 20, count 2 2006.190.07:45:39.92#ibcon#about to read 6, iclass 20, count 2 2006.190.07:45:39.92#ibcon#read 6, iclass 20, count 2 2006.190.07:45:39.92#ibcon#end of sib2, iclass 20, count 2 2006.190.07:45:39.92#ibcon#*after write, iclass 20, count 2 2006.190.07:45:39.92#ibcon#*before return 0, iclass 20, count 2 2006.190.07:45:39.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:45:39.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:45:39.92#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.190.07:45:39.92#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:39.92#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:45:40.04#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:45:40.04#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:45:40.04#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:45:40.04#ibcon#first serial, iclass 20, count 0 2006.190.07:45:40.04#ibcon#enter sib2, iclass 20, count 0 2006.190.07:45:40.04#ibcon#flushed, iclass 20, count 0 2006.190.07:45:40.04#ibcon#about to write, iclass 20, count 0 2006.190.07:45:40.04#ibcon#wrote, iclass 20, count 0 2006.190.07:45:40.04#ibcon#about to read 3, iclass 20, count 0 2006.190.07:45:40.06#ibcon#read 3, iclass 20, count 0 2006.190.07:45:40.06#ibcon#about to read 4, iclass 20, count 0 2006.190.07:45:40.06#ibcon#read 4, iclass 20, count 0 2006.190.07:45:40.06#ibcon#about to read 5, iclass 20, count 0 2006.190.07:45:40.06#ibcon#read 5, iclass 20, count 0 2006.190.07:45:40.06#ibcon#about to read 6, iclass 20, count 0 2006.190.07:45:40.06#ibcon#read 6, iclass 20, count 0 2006.190.07:45:40.06#ibcon#end of sib2, iclass 20, count 0 2006.190.07:45:40.06#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:45:40.06#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:45:40.06#ibcon#[25=USB\r\n] 2006.190.07:45:40.06#ibcon#*before write, iclass 20, count 0 2006.190.07:45:40.06#ibcon#enter sib2, iclass 20, count 0 2006.190.07:45:40.06#ibcon#flushed, iclass 20, count 0 2006.190.07:45:40.06#ibcon#about to write, iclass 20, count 0 2006.190.07:45:40.06#ibcon#wrote, iclass 20, count 0 2006.190.07:45:40.06#ibcon#about to read 3, iclass 20, count 0 2006.190.07:45:40.09#ibcon#read 3, iclass 20, count 0 2006.190.07:45:40.09#ibcon#about to read 4, iclass 20, count 0 2006.190.07:45:40.09#ibcon#read 4, iclass 20, count 0 2006.190.07:45:40.09#ibcon#about to read 5, iclass 20, count 0 2006.190.07:45:40.09#ibcon#read 5, iclass 20, count 0 2006.190.07:45:40.09#ibcon#about to read 6, iclass 20, count 0 2006.190.07:45:40.09#ibcon#read 6, iclass 20, count 0 2006.190.07:45:40.09#ibcon#end of sib2, iclass 20, count 0 2006.190.07:45:40.09#ibcon#*after write, iclass 20, count 0 2006.190.07:45:40.09#ibcon#*before return 0, iclass 20, count 0 2006.190.07:45:40.09#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:45:40.09#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:45:40.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:45:40.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:45:40.09$vc4f8/valo=7,832.99 2006.190.07:45:40.09#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.07:45:40.09#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.07:45:40.09#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:40.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:45:40.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:45:40.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:45:40.09#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:45:40.09#ibcon#first serial, iclass 22, count 0 2006.190.07:45:40.09#ibcon#enter sib2, iclass 22, count 0 2006.190.07:45:40.09#ibcon#flushed, iclass 22, count 0 2006.190.07:45:40.09#ibcon#about to write, iclass 22, count 0 2006.190.07:45:40.09#ibcon#wrote, iclass 22, count 0 2006.190.07:45:40.09#ibcon#about to read 3, iclass 22, count 0 2006.190.07:45:40.11#ibcon#read 3, iclass 22, count 0 2006.190.07:45:40.11#ibcon#about to read 4, iclass 22, count 0 2006.190.07:45:40.11#ibcon#read 4, iclass 22, count 0 2006.190.07:45:40.11#ibcon#about to read 5, iclass 22, count 0 2006.190.07:45:40.11#ibcon#read 5, iclass 22, count 0 2006.190.07:45:40.11#ibcon#about to read 6, iclass 22, count 0 2006.190.07:45:40.11#ibcon#read 6, iclass 22, count 0 2006.190.07:45:40.11#ibcon#end of sib2, iclass 22, count 0 2006.190.07:45:40.11#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:45:40.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:45:40.11#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:45:40.11#ibcon#*before write, iclass 22, count 0 2006.190.07:45:40.11#ibcon#enter sib2, iclass 22, count 0 2006.190.07:45:40.11#ibcon#flushed, iclass 22, count 0 2006.190.07:45:40.11#ibcon#about to write, iclass 22, count 0 2006.190.07:45:40.11#ibcon#wrote, iclass 22, count 0 2006.190.07:45:40.11#ibcon#about to read 3, iclass 22, count 0 2006.190.07:45:40.15#ibcon#read 3, iclass 22, count 0 2006.190.07:45:40.15#ibcon#about to read 4, iclass 22, count 0 2006.190.07:45:40.15#ibcon#read 4, iclass 22, count 0 2006.190.07:45:40.15#ibcon#about to read 5, iclass 22, count 0 2006.190.07:45:40.15#ibcon#read 5, iclass 22, count 0 2006.190.07:45:40.15#ibcon#about to read 6, iclass 22, count 0 2006.190.07:45:40.15#ibcon#read 6, iclass 22, count 0 2006.190.07:45:40.15#ibcon#end of sib2, iclass 22, count 0 2006.190.07:45:40.15#ibcon#*after write, iclass 22, count 0 2006.190.07:45:40.15#ibcon#*before return 0, iclass 22, count 0 2006.190.07:45:40.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:45:40.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:45:40.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:45:40.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:45:40.15$vc4f8/va=7,6 2006.190.07:45:40.15#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.07:45:40.15#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.07:45:40.15#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:40.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:45:40.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:45:40.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:45:40.21#ibcon#enter wrdev, iclass 24, count 2 2006.190.07:45:40.21#ibcon#first serial, iclass 24, count 2 2006.190.07:45:40.21#ibcon#enter sib2, iclass 24, count 2 2006.190.07:45:40.21#ibcon#flushed, iclass 24, count 2 2006.190.07:45:40.21#ibcon#about to write, iclass 24, count 2 2006.190.07:45:40.21#ibcon#wrote, iclass 24, count 2 2006.190.07:45:40.21#ibcon#about to read 3, iclass 24, count 2 2006.190.07:45:40.23#ibcon#read 3, iclass 24, count 2 2006.190.07:45:40.23#ibcon#about to read 4, iclass 24, count 2 2006.190.07:45:40.23#ibcon#read 4, iclass 24, count 2 2006.190.07:45:40.23#ibcon#about to read 5, iclass 24, count 2 2006.190.07:45:40.23#ibcon#read 5, iclass 24, count 2 2006.190.07:45:40.23#ibcon#about to read 6, iclass 24, count 2 2006.190.07:45:40.23#ibcon#read 6, iclass 24, count 2 2006.190.07:45:40.23#ibcon#end of sib2, iclass 24, count 2 2006.190.07:45:40.23#ibcon#*mode == 0, iclass 24, count 2 2006.190.07:45:40.23#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.07:45:40.23#ibcon#[25=AT07-06\r\n] 2006.190.07:45:40.23#ibcon#*before write, iclass 24, count 2 2006.190.07:45:40.23#ibcon#enter sib2, iclass 24, count 2 2006.190.07:45:40.23#ibcon#flushed, iclass 24, count 2 2006.190.07:45:40.23#ibcon#about to write, iclass 24, count 2 2006.190.07:45:40.23#ibcon#wrote, iclass 24, count 2 2006.190.07:45:40.23#ibcon#about to read 3, iclass 24, count 2 2006.190.07:45:40.26#ibcon#read 3, iclass 24, count 2 2006.190.07:45:40.26#ibcon#about to read 4, iclass 24, count 2 2006.190.07:45:40.26#ibcon#read 4, iclass 24, count 2 2006.190.07:45:40.26#ibcon#about to read 5, iclass 24, count 2 2006.190.07:45:40.26#ibcon#read 5, iclass 24, count 2 2006.190.07:45:40.26#ibcon#about to read 6, iclass 24, count 2 2006.190.07:45:40.26#ibcon#read 6, iclass 24, count 2 2006.190.07:45:40.26#ibcon#end of sib2, iclass 24, count 2 2006.190.07:45:40.26#ibcon#*after write, iclass 24, count 2 2006.190.07:45:40.26#ibcon#*before return 0, iclass 24, count 2 2006.190.07:45:40.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:45:40.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:45:40.26#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.07:45:40.26#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:40.26#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:45:40.38#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:45:40.38#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:45:40.38#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:45:40.38#ibcon#first serial, iclass 24, count 0 2006.190.07:45:40.38#ibcon#enter sib2, iclass 24, count 0 2006.190.07:45:40.38#ibcon#flushed, iclass 24, count 0 2006.190.07:45:40.38#ibcon#about to write, iclass 24, count 0 2006.190.07:45:40.38#ibcon#wrote, iclass 24, count 0 2006.190.07:45:40.38#ibcon#about to read 3, iclass 24, count 0 2006.190.07:45:40.40#ibcon#read 3, iclass 24, count 0 2006.190.07:45:40.40#ibcon#about to read 4, iclass 24, count 0 2006.190.07:45:40.40#ibcon#read 4, iclass 24, count 0 2006.190.07:45:40.40#ibcon#about to read 5, iclass 24, count 0 2006.190.07:45:40.40#ibcon#read 5, iclass 24, count 0 2006.190.07:45:40.40#ibcon#about to read 6, iclass 24, count 0 2006.190.07:45:40.40#ibcon#read 6, iclass 24, count 0 2006.190.07:45:40.40#ibcon#end of sib2, iclass 24, count 0 2006.190.07:45:40.40#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:45:40.40#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:45:40.40#ibcon#[25=USB\r\n] 2006.190.07:45:40.40#ibcon#*before write, iclass 24, count 0 2006.190.07:45:40.40#ibcon#enter sib2, iclass 24, count 0 2006.190.07:45:40.40#ibcon#flushed, iclass 24, count 0 2006.190.07:45:40.40#ibcon#about to write, iclass 24, count 0 2006.190.07:45:40.40#ibcon#wrote, iclass 24, count 0 2006.190.07:45:40.40#ibcon#about to read 3, iclass 24, count 0 2006.190.07:45:40.43#ibcon#read 3, iclass 24, count 0 2006.190.07:45:40.43#ibcon#about to read 4, iclass 24, count 0 2006.190.07:45:40.43#ibcon#read 4, iclass 24, count 0 2006.190.07:45:40.43#ibcon#about to read 5, iclass 24, count 0 2006.190.07:45:40.43#ibcon#read 5, iclass 24, count 0 2006.190.07:45:40.43#ibcon#about to read 6, iclass 24, count 0 2006.190.07:45:40.43#ibcon#read 6, iclass 24, count 0 2006.190.07:45:40.43#ibcon#end of sib2, iclass 24, count 0 2006.190.07:45:40.43#ibcon#*after write, iclass 24, count 0 2006.190.07:45:40.43#ibcon#*before return 0, iclass 24, count 0 2006.190.07:45:40.43#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:45:40.43#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:45:40.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:45:40.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:45:40.43$vc4f8/valo=8,852.99 2006.190.07:45:40.43#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.07:45:40.43#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.07:45:40.43#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:40.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:45:40.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:45:40.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:45:40.43#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:45:40.43#ibcon#first serial, iclass 26, count 0 2006.190.07:45:40.43#ibcon#enter sib2, iclass 26, count 0 2006.190.07:45:40.43#ibcon#flushed, iclass 26, count 0 2006.190.07:45:40.43#ibcon#about to write, iclass 26, count 0 2006.190.07:45:40.43#ibcon#wrote, iclass 26, count 0 2006.190.07:45:40.43#ibcon#about to read 3, iclass 26, count 0 2006.190.07:45:40.45#ibcon#read 3, iclass 26, count 0 2006.190.07:45:40.45#ibcon#about to read 4, iclass 26, count 0 2006.190.07:45:40.45#ibcon#read 4, iclass 26, count 0 2006.190.07:45:40.45#ibcon#about to read 5, iclass 26, count 0 2006.190.07:45:40.45#ibcon#read 5, iclass 26, count 0 2006.190.07:45:40.45#ibcon#about to read 6, iclass 26, count 0 2006.190.07:45:40.45#ibcon#read 6, iclass 26, count 0 2006.190.07:45:40.45#ibcon#end of sib2, iclass 26, count 0 2006.190.07:45:40.45#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:45:40.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:45:40.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:45:40.45#ibcon#*before write, iclass 26, count 0 2006.190.07:45:40.45#ibcon#enter sib2, iclass 26, count 0 2006.190.07:45:40.45#ibcon#flushed, iclass 26, count 0 2006.190.07:45:40.45#ibcon#about to write, iclass 26, count 0 2006.190.07:45:40.45#ibcon#wrote, iclass 26, count 0 2006.190.07:45:40.45#ibcon#about to read 3, iclass 26, count 0 2006.190.07:45:40.49#ibcon#read 3, iclass 26, count 0 2006.190.07:45:40.49#ibcon#about to read 4, iclass 26, count 0 2006.190.07:45:40.49#ibcon#read 4, iclass 26, count 0 2006.190.07:45:40.49#ibcon#about to read 5, iclass 26, count 0 2006.190.07:45:40.49#ibcon#read 5, iclass 26, count 0 2006.190.07:45:40.49#ibcon#about to read 6, iclass 26, count 0 2006.190.07:45:40.49#ibcon#read 6, iclass 26, count 0 2006.190.07:45:40.49#ibcon#end of sib2, iclass 26, count 0 2006.190.07:45:40.49#ibcon#*after write, iclass 26, count 0 2006.190.07:45:40.49#ibcon#*before return 0, iclass 26, count 0 2006.190.07:45:40.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:45:40.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:45:40.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:45:40.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:45:40.49$vc4f8/va=8,6 2006.190.07:45:40.49#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.07:45:40.49#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.07:45:40.49#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:40.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:45:40.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:45:40.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:45:40.55#ibcon#enter wrdev, iclass 28, count 2 2006.190.07:45:40.55#ibcon#first serial, iclass 28, count 2 2006.190.07:45:40.55#ibcon#enter sib2, iclass 28, count 2 2006.190.07:45:40.55#ibcon#flushed, iclass 28, count 2 2006.190.07:45:40.55#ibcon#about to write, iclass 28, count 2 2006.190.07:45:40.55#ibcon#wrote, iclass 28, count 2 2006.190.07:45:40.55#ibcon#about to read 3, iclass 28, count 2 2006.190.07:45:40.57#ibcon#read 3, iclass 28, count 2 2006.190.07:45:40.57#ibcon#about to read 4, iclass 28, count 2 2006.190.07:45:40.57#ibcon#read 4, iclass 28, count 2 2006.190.07:45:40.57#ibcon#about to read 5, iclass 28, count 2 2006.190.07:45:40.57#ibcon#read 5, iclass 28, count 2 2006.190.07:45:40.57#ibcon#about to read 6, iclass 28, count 2 2006.190.07:45:40.57#ibcon#read 6, iclass 28, count 2 2006.190.07:45:40.57#ibcon#end of sib2, iclass 28, count 2 2006.190.07:45:40.57#ibcon#*mode == 0, iclass 28, count 2 2006.190.07:45:40.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.07:45:40.57#ibcon#[25=AT08-06\r\n] 2006.190.07:45:40.57#ibcon#*before write, iclass 28, count 2 2006.190.07:45:40.57#ibcon#enter sib2, iclass 28, count 2 2006.190.07:45:40.57#ibcon#flushed, iclass 28, count 2 2006.190.07:45:40.57#ibcon#about to write, iclass 28, count 2 2006.190.07:45:40.57#ibcon#wrote, iclass 28, count 2 2006.190.07:45:40.57#ibcon#about to read 3, iclass 28, count 2 2006.190.07:45:40.60#ibcon#read 3, iclass 28, count 2 2006.190.07:45:40.60#ibcon#about to read 4, iclass 28, count 2 2006.190.07:45:40.60#ibcon#read 4, iclass 28, count 2 2006.190.07:45:40.60#ibcon#about to read 5, iclass 28, count 2 2006.190.07:45:40.60#ibcon#read 5, iclass 28, count 2 2006.190.07:45:40.60#ibcon#about to read 6, iclass 28, count 2 2006.190.07:45:40.60#ibcon#read 6, iclass 28, count 2 2006.190.07:45:40.60#ibcon#end of sib2, iclass 28, count 2 2006.190.07:45:40.60#ibcon#*after write, iclass 28, count 2 2006.190.07:45:40.60#ibcon#*before return 0, iclass 28, count 2 2006.190.07:45:40.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:45:40.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:45:40.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.07:45:40.60#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:40.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:45:40.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:45:40.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:45:40.72#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:45:40.72#ibcon#first serial, iclass 28, count 0 2006.190.07:45:40.72#ibcon#enter sib2, iclass 28, count 0 2006.190.07:45:40.72#ibcon#flushed, iclass 28, count 0 2006.190.07:45:40.72#ibcon#about to write, iclass 28, count 0 2006.190.07:45:40.72#ibcon#wrote, iclass 28, count 0 2006.190.07:45:40.72#ibcon#about to read 3, iclass 28, count 0 2006.190.07:45:40.74#ibcon#read 3, iclass 28, count 0 2006.190.07:45:40.74#ibcon#about to read 4, iclass 28, count 0 2006.190.07:45:40.74#ibcon#read 4, iclass 28, count 0 2006.190.07:45:40.74#ibcon#about to read 5, iclass 28, count 0 2006.190.07:45:40.74#ibcon#read 5, iclass 28, count 0 2006.190.07:45:40.74#ibcon#about to read 6, iclass 28, count 0 2006.190.07:45:40.74#ibcon#read 6, iclass 28, count 0 2006.190.07:45:40.74#ibcon#end of sib2, iclass 28, count 0 2006.190.07:45:40.74#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:45:40.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:45:40.74#ibcon#[25=USB\r\n] 2006.190.07:45:40.74#ibcon#*before write, iclass 28, count 0 2006.190.07:45:40.74#ibcon#enter sib2, iclass 28, count 0 2006.190.07:45:40.74#ibcon#flushed, iclass 28, count 0 2006.190.07:45:40.74#ibcon#about to write, iclass 28, count 0 2006.190.07:45:40.74#ibcon#wrote, iclass 28, count 0 2006.190.07:45:40.74#ibcon#about to read 3, iclass 28, count 0 2006.190.07:45:40.77#ibcon#read 3, iclass 28, count 0 2006.190.07:45:40.77#ibcon#about to read 4, iclass 28, count 0 2006.190.07:45:40.77#ibcon#read 4, iclass 28, count 0 2006.190.07:45:40.77#ibcon#about to read 5, iclass 28, count 0 2006.190.07:45:40.77#ibcon#read 5, iclass 28, count 0 2006.190.07:45:40.77#ibcon#about to read 6, iclass 28, count 0 2006.190.07:45:40.77#ibcon#read 6, iclass 28, count 0 2006.190.07:45:40.77#ibcon#end of sib2, iclass 28, count 0 2006.190.07:45:40.77#ibcon#*after write, iclass 28, count 0 2006.190.07:45:40.77#ibcon#*before return 0, iclass 28, count 0 2006.190.07:45:40.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:45:40.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:45:40.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:45:40.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:45:40.77$vc4f8/vblo=1,632.99 2006.190.07:45:40.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.07:45:40.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.07:45:40.77#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:40.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:45:40.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:45:40.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:45:40.77#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:45:40.77#ibcon#first serial, iclass 30, count 0 2006.190.07:45:40.77#ibcon#enter sib2, iclass 30, count 0 2006.190.07:45:40.77#ibcon#flushed, iclass 30, count 0 2006.190.07:45:40.77#ibcon#about to write, iclass 30, count 0 2006.190.07:45:40.77#ibcon#wrote, iclass 30, count 0 2006.190.07:45:40.77#ibcon#about to read 3, iclass 30, count 0 2006.190.07:45:40.79#ibcon#read 3, iclass 30, count 0 2006.190.07:45:40.79#ibcon#about to read 4, iclass 30, count 0 2006.190.07:45:40.79#ibcon#read 4, iclass 30, count 0 2006.190.07:45:40.79#ibcon#about to read 5, iclass 30, count 0 2006.190.07:45:40.79#ibcon#read 5, iclass 30, count 0 2006.190.07:45:40.79#ibcon#about to read 6, iclass 30, count 0 2006.190.07:45:40.79#ibcon#read 6, iclass 30, count 0 2006.190.07:45:40.79#ibcon#end of sib2, iclass 30, count 0 2006.190.07:45:40.79#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:45:40.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:45:40.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:45:40.79#ibcon#*before write, iclass 30, count 0 2006.190.07:45:40.79#ibcon#enter sib2, iclass 30, count 0 2006.190.07:45:40.79#ibcon#flushed, iclass 30, count 0 2006.190.07:45:40.79#ibcon#about to write, iclass 30, count 0 2006.190.07:45:40.79#ibcon#wrote, iclass 30, count 0 2006.190.07:45:40.79#ibcon#about to read 3, iclass 30, count 0 2006.190.07:45:40.83#ibcon#read 3, iclass 30, count 0 2006.190.07:45:40.83#ibcon#about to read 4, iclass 30, count 0 2006.190.07:45:40.83#ibcon#read 4, iclass 30, count 0 2006.190.07:45:40.83#ibcon#about to read 5, iclass 30, count 0 2006.190.07:45:40.83#ibcon#read 5, iclass 30, count 0 2006.190.07:45:40.83#ibcon#about to read 6, iclass 30, count 0 2006.190.07:45:40.83#ibcon#read 6, iclass 30, count 0 2006.190.07:45:40.83#ibcon#end of sib2, iclass 30, count 0 2006.190.07:45:40.83#ibcon#*after write, iclass 30, count 0 2006.190.07:45:40.83#ibcon#*before return 0, iclass 30, count 0 2006.190.07:45:40.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:45:40.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:45:40.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:45:40.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:45:40.83$vc4f8/vb=1,4 2006.190.07:45:40.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.07:45:40.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.07:45:40.83#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:40.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:45:40.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:45:40.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:45:40.83#ibcon#enter wrdev, iclass 32, count 2 2006.190.07:45:40.83#ibcon#first serial, iclass 32, count 2 2006.190.07:45:40.83#ibcon#enter sib2, iclass 32, count 2 2006.190.07:45:40.83#ibcon#flushed, iclass 32, count 2 2006.190.07:45:40.83#ibcon#about to write, iclass 32, count 2 2006.190.07:45:40.83#ibcon#wrote, iclass 32, count 2 2006.190.07:45:40.83#ibcon#about to read 3, iclass 32, count 2 2006.190.07:45:40.85#ibcon#read 3, iclass 32, count 2 2006.190.07:45:40.85#ibcon#about to read 4, iclass 32, count 2 2006.190.07:45:40.85#ibcon#read 4, iclass 32, count 2 2006.190.07:45:40.85#ibcon#about to read 5, iclass 32, count 2 2006.190.07:45:40.85#ibcon#read 5, iclass 32, count 2 2006.190.07:45:40.85#ibcon#about to read 6, iclass 32, count 2 2006.190.07:45:40.85#ibcon#read 6, iclass 32, count 2 2006.190.07:45:40.85#ibcon#end of sib2, iclass 32, count 2 2006.190.07:45:40.85#ibcon#*mode == 0, iclass 32, count 2 2006.190.07:45:40.85#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.07:45:40.85#ibcon#[27=AT01-04\r\n] 2006.190.07:45:40.85#ibcon#*before write, iclass 32, count 2 2006.190.07:45:40.85#ibcon#enter sib2, iclass 32, count 2 2006.190.07:45:40.85#ibcon#flushed, iclass 32, count 2 2006.190.07:45:40.85#ibcon#about to write, iclass 32, count 2 2006.190.07:45:40.85#ibcon#wrote, iclass 32, count 2 2006.190.07:45:40.85#ibcon#about to read 3, iclass 32, count 2 2006.190.07:45:40.88#ibcon#read 3, iclass 32, count 2 2006.190.07:45:40.88#ibcon#about to read 4, iclass 32, count 2 2006.190.07:45:40.88#ibcon#read 4, iclass 32, count 2 2006.190.07:45:40.88#ibcon#about to read 5, iclass 32, count 2 2006.190.07:45:40.88#ibcon#read 5, iclass 32, count 2 2006.190.07:45:40.88#ibcon#about to read 6, iclass 32, count 2 2006.190.07:45:40.88#ibcon#read 6, iclass 32, count 2 2006.190.07:45:40.88#ibcon#end of sib2, iclass 32, count 2 2006.190.07:45:40.88#ibcon#*after write, iclass 32, count 2 2006.190.07:45:40.88#ibcon#*before return 0, iclass 32, count 2 2006.190.07:45:40.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:45:40.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:45:40.88#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.07:45:40.88#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:40.88#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:45:41.00#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:45:41.00#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:45:41.00#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:45:41.00#ibcon#first serial, iclass 32, count 0 2006.190.07:45:41.00#ibcon#enter sib2, iclass 32, count 0 2006.190.07:45:41.00#ibcon#flushed, iclass 32, count 0 2006.190.07:45:41.00#ibcon#about to write, iclass 32, count 0 2006.190.07:45:41.00#ibcon#wrote, iclass 32, count 0 2006.190.07:45:41.00#ibcon#about to read 3, iclass 32, count 0 2006.190.07:45:41.02#ibcon#read 3, iclass 32, count 0 2006.190.07:45:41.02#ibcon#about to read 4, iclass 32, count 0 2006.190.07:45:41.02#ibcon#read 4, iclass 32, count 0 2006.190.07:45:41.02#ibcon#about to read 5, iclass 32, count 0 2006.190.07:45:41.02#ibcon#read 5, iclass 32, count 0 2006.190.07:45:41.02#ibcon#about to read 6, iclass 32, count 0 2006.190.07:45:41.02#ibcon#read 6, iclass 32, count 0 2006.190.07:45:41.02#ibcon#end of sib2, iclass 32, count 0 2006.190.07:45:41.02#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:45:41.02#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:45:41.02#ibcon#[27=USB\r\n] 2006.190.07:45:41.02#ibcon#*before write, iclass 32, count 0 2006.190.07:45:41.02#ibcon#enter sib2, iclass 32, count 0 2006.190.07:45:41.02#ibcon#flushed, iclass 32, count 0 2006.190.07:45:41.02#ibcon#about to write, iclass 32, count 0 2006.190.07:45:41.02#ibcon#wrote, iclass 32, count 0 2006.190.07:45:41.02#ibcon#about to read 3, iclass 32, count 0 2006.190.07:45:41.05#ibcon#read 3, iclass 32, count 0 2006.190.07:45:41.05#ibcon#about to read 4, iclass 32, count 0 2006.190.07:45:41.05#ibcon#read 4, iclass 32, count 0 2006.190.07:45:41.05#ibcon#about to read 5, iclass 32, count 0 2006.190.07:45:41.05#ibcon#read 5, iclass 32, count 0 2006.190.07:45:41.05#ibcon#about to read 6, iclass 32, count 0 2006.190.07:45:41.05#ibcon#read 6, iclass 32, count 0 2006.190.07:45:41.05#ibcon#end of sib2, iclass 32, count 0 2006.190.07:45:41.05#ibcon#*after write, iclass 32, count 0 2006.190.07:45:41.05#ibcon#*before return 0, iclass 32, count 0 2006.190.07:45:41.05#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:45:41.05#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:45:41.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:45:41.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:45:41.05$vc4f8/vblo=2,640.99 2006.190.07:45:41.05#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.07:45:41.05#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.07:45:41.05#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:41.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:41.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:41.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:41.05#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:45:41.05#ibcon#first serial, iclass 34, count 0 2006.190.07:45:41.05#ibcon#enter sib2, iclass 34, count 0 2006.190.07:45:41.05#ibcon#flushed, iclass 34, count 0 2006.190.07:45:41.05#ibcon#about to write, iclass 34, count 0 2006.190.07:45:41.05#ibcon#wrote, iclass 34, count 0 2006.190.07:45:41.05#ibcon#about to read 3, iclass 34, count 0 2006.190.07:45:41.07#ibcon#read 3, iclass 34, count 0 2006.190.07:45:41.07#ibcon#about to read 4, iclass 34, count 0 2006.190.07:45:41.07#ibcon#read 4, iclass 34, count 0 2006.190.07:45:41.07#ibcon#about to read 5, iclass 34, count 0 2006.190.07:45:41.07#ibcon#read 5, iclass 34, count 0 2006.190.07:45:41.07#ibcon#about to read 6, iclass 34, count 0 2006.190.07:45:41.07#ibcon#read 6, iclass 34, count 0 2006.190.07:45:41.07#ibcon#end of sib2, iclass 34, count 0 2006.190.07:45:41.07#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:45:41.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:45:41.07#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:45:41.07#ibcon#*before write, iclass 34, count 0 2006.190.07:45:41.07#ibcon#enter sib2, iclass 34, count 0 2006.190.07:45:41.07#ibcon#flushed, iclass 34, count 0 2006.190.07:45:41.07#ibcon#about to write, iclass 34, count 0 2006.190.07:45:41.07#ibcon#wrote, iclass 34, count 0 2006.190.07:45:41.07#ibcon#about to read 3, iclass 34, count 0 2006.190.07:45:41.11#ibcon#read 3, iclass 34, count 0 2006.190.07:45:41.11#ibcon#about to read 4, iclass 34, count 0 2006.190.07:45:41.11#ibcon#read 4, iclass 34, count 0 2006.190.07:45:41.11#ibcon#about to read 5, iclass 34, count 0 2006.190.07:45:41.11#ibcon#read 5, iclass 34, count 0 2006.190.07:45:41.11#ibcon#about to read 6, iclass 34, count 0 2006.190.07:45:41.11#ibcon#read 6, iclass 34, count 0 2006.190.07:45:41.11#ibcon#end of sib2, iclass 34, count 0 2006.190.07:45:41.11#ibcon#*after write, iclass 34, count 0 2006.190.07:45:41.11#ibcon#*before return 0, iclass 34, count 0 2006.190.07:45:41.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:41.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:45:41.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:45:41.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:45:41.11$vc4f8/vb=2,4 2006.190.07:45:41.11#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.07:45:41.11#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.07:45:41.11#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:41.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:41.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:41.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:41.17#ibcon#enter wrdev, iclass 36, count 2 2006.190.07:45:41.17#ibcon#first serial, iclass 36, count 2 2006.190.07:45:41.17#ibcon#enter sib2, iclass 36, count 2 2006.190.07:45:41.17#ibcon#flushed, iclass 36, count 2 2006.190.07:45:41.17#ibcon#about to write, iclass 36, count 2 2006.190.07:45:41.17#ibcon#wrote, iclass 36, count 2 2006.190.07:45:41.17#ibcon#about to read 3, iclass 36, count 2 2006.190.07:45:41.19#ibcon#read 3, iclass 36, count 2 2006.190.07:45:41.19#ibcon#about to read 4, iclass 36, count 2 2006.190.07:45:41.19#ibcon#read 4, iclass 36, count 2 2006.190.07:45:41.19#ibcon#about to read 5, iclass 36, count 2 2006.190.07:45:41.19#ibcon#read 5, iclass 36, count 2 2006.190.07:45:41.19#ibcon#about to read 6, iclass 36, count 2 2006.190.07:45:41.19#ibcon#read 6, iclass 36, count 2 2006.190.07:45:41.19#ibcon#end of sib2, iclass 36, count 2 2006.190.07:45:41.19#ibcon#*mode == 0, iclass 36, count 2 2006.190.07:45:41.19#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.07:45:41.19#ibcon#[27=AT02-04\r\n] 2006.190.07:45:41.19#ibcon#*before write, iclass 36, count 2 2006.190.07:45:41.19#ibcon#enter sib2, iclass 36, count 2 2006.190.07:45:41.19#ibcon#flushed, iclass 36, count 2 2006.190.07:45:41.19#ibcon#about to write, iclass 36, count 2 2006.190.07:45:41.19#ibcon#wrote, iclass 36, count 2 2006.190.07:45:41.19#ibcon#about to read 3, iclass 36, count 2 2006.190.07:45:41.22#ibcon#read 3, iclass 36, count 2 2006.190.07:45:41.22#ibcon#about to read 4, iclass 36, count 2 2006.190.07:45:41.22#ibcon#read 4, iclass 36, count 2 2006.190.07:45:41.22#ibcon#about to read 5, iclass 36, count 2 2006.190.07:45:41.22#ibcon#read 5, iclass 36, count 2 2006.190.07:45:41.22#ibcon#about to read 6, iclass 36, count 2 2006.190.07:45:41.22#ibcon#read 6, iclass 36, count 2 2006.190.07:45:41.22#ibcon#end of sib2, iclass 36, count 2 2006.190.07:45:41.22#ibcon#*after write, iclass 36, count 2 2006.190.07:45:41.22#ibcon#*before return 0, iclass 36, count 2 2006.190.07:45:41.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:41.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:45:41.22#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.07:45:41.22#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:41.22#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:41.34#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:41.34#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:41.34#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:45:41.34#ibcon#first serial, iclass 36, count 0 2006.190.07:45:41.34#ibcon#enter sib2, iclass 36, count 0 2006.190.07:45:41.34#ibcon#flushed, iclass 36, count 0 2006.190.07:45:41.34#ibcon#about to write, iclass 36, count 0 2006.190.07:45:41.34#ibcon#wrote, iclass 36, count 0 2006.190.07:45:41.34#ibcon#about to read 3, iclass 36, count 0 2006.190.07:45:41.36#ibcon#read 3, iclass 36, count 0 2006.190.07:45:41.36#ibcon#about to read 4, iclass 36, count 0 2006.190.07:45:41.36#ibcon#read 4, iclass 36, count 0 2006.190.07:45:41.36#ibcon#about to read 5, iclass 36, count 0 2006.190.07:45:41.36#ibcon#read 5, iclass 36, count 0 2006.190.07:45:41.36#ibcon#about to read 6, iclass 36, count 0 2006.190.07:45:41.36#ibcon#read 6, iclass 36, count 0 2006.190.07:45:41.36#ibcon#end of sib2, iclass 36, count 0 2006.190.07:45:41.36#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:45:41.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:45:41.36#ibcon#[27=USB\r\n] 2006.190.07:45:41.36#ibcon#*before write, iclass 36, count 0 2006.190.07:45:41.36#ibcon#enter sib2, iclass 36, count 0 2006.190.07:45:41.36#ibcon#flushed, iclass 36, count 0 2006.190.07:45:41.36#ibcon#about to write, iclass 36, count 0 2006.190.07:45:41.36#ibcon#wrote, iclass 36, count 0 2006.190.07:45:41.36#ibcon#about to read 3, iclass 36, count 0 2006.190.07:45:41.39#ibcon#read 3, iclass 36, count 0 2006.190.07:45:41.39#ibcon#about to read 4, iclass 36, count 0 2006.190.07:45:41.39#ibcon#read 4, iclass 36, count 0 2006.190.07:45:41.39#ibcon#about to read 5, iclass 36, count 0 2006.190.07:45:41.39#ibcon#read 5, iclass 36, count 0 2006.190.07:45:41.39#ibcon#about to read 6, iclass 36, count 0 2006.190.07:45:41.39#ibcon#read 6, iclass 36, count 0 2006.190.07:45:41.39#ibcon#end of sib2, iclass 36, count 0 2006.190.07:45:41.39#ibcon#*after write, iclass 36, count 0 2006.190.07:45:41.39#ibcon#*before return 0, iclass 36, count 0 2006.190.07:45:41.39#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:41.39#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:45:41.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:45:41.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:45:41.39$vc4f8/vblo=3,656.99 2006.190.07:45:41.39#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.07:45:41.39#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.07:45:41.39#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:41.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:41.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:41.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:41.39#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:45:41.39#ibcon#first serial, iclass 38, count 0 2006.190.07:45:41.39#ibcon#enter sib2, iclass 38, count 0 2006.190.07:45:41.39#ibcon#flushed, iclass 38, count 0 2006.190.07:45:41.39#ibcon#about to write, iclass 38, count 0 2006.190.07:45:41.39#ibcon#wrote, iclass 38, count 0 2006.190.07:45:41.39#ibcon#about to read 3, iclass 38, count 0 2006.190.07:45:41.41#ibcon#read 3, iclass 38, count 0 2006.190.07:45:41.41#ibcon#about to read 4, iclass 38, count 0 2006.190.07:45:41.41#ibcon#read 4, iclass 38, count 0 2006.190.07:45:41.41#ibcon#about to read 5, iclass 38, count 0 2006.190.07:45:41.41#ibcon#read 5, iclass 38, count 0 2006.190.07:45:41.41#ibcon#about to read 6, iclass 38, count 0 2006.190.07:45:41.41#ibcon#read 6, iclass 38, count 0 2006.190.07:45:41.41#ibcon#end of sib2, iclass 38, count 0 2006.190.07:45:41.41#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:45:41.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:45:41.41#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:45:41.41#ibcon#*before write, iclass 38, count 0 2006.190.07:45:41.41#ibcon#enter sib2, iclass 38, count 0 2006.190.07:45:41.41#ibcon#flushed, iclass 38, count 0 2006.190.07:45:41.41#ibcon#about to write, iclass 38, count 0 2006.190.07:45:41.41#ibcon#wrote, iclass 38, count 0 2006.190.07:45:41.41#ibcon#about to read 3, iclass 38, count 0 2006.190.07:45:41.45#ibcon#read 3, iclass 38, count 0 2006.190.07:45:41.45#ibcon#about to read 4, iclass 38, count 0 2006.190.07:45:41.45#ibcon#read 4, iclass 38, count 0 2006.190.07:45:41.45#ibcon#about to read 5, iclass 38, count 0 2006.190.07:45:41.45#ibcon#read 5, iclass 38, count 0 2006.190.07:45:41.45#ibcon#about to read 6, iclass 38, count 0 2006.190.07:45:41.45#ibcon#read 6, iclass 38, count 0 2006.190.07:45:41.45#ibcon#end of sib2, iclass 38, count 0 2006.190.07:45:41.45#ibcon#*after write, iclass 38, count 0 2006.190.07:45:41.45#ibcon#*before return 0, iclass 38, count 0 2006.190.07:45:41.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:41.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:45:41.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:45:41.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:45:41.45$vc4f8/vb=3,4 2006.190.07:45:41.45#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.07:45:41.45#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.07:45:41.45#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:41.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:41.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:41.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:41.51#ibcon#enter wrdev, iclass 40, count 2 2006.190.07:45:41.51#ibcon#first serial, iclass 40, count 2 2006.190.07:45:41.51#ibcon#enter sib2, iclass 40, count 2 2006.190.07:45:41.51#ibcon#flushed, iclass 40, count 2 2006.190.07:45:41.51#ibcon#about to write, iclass 40, count 2 2006.190.07:45:41.51#ibcon#wrote, iclass 40, count 2 2006.190.07:45:41.51#ibcon#about to read 3, iclass 40, count 2 2006.190.07:45:41.53#ibcon#read 3, iclass 40, count 2 2006.190.07:45:41.53#ibcon#about to read 4, iclass 40, count 2 2006.190.07:45:41.53#ibcon#read 4, iclass 40, count 2 2006.190.07:45:41.53#ibcon#about to read 5, iclass 40, count 2 2006.190.07:45:41.53#ibcon#read 5, iclass 40, count 2 2006.190.07:45:41.53#ibcon#about to read 6, iclass 40, count 2 2006.190.07:45:41.53#ibcon#read 6, iclass 40, count 2 2006.190.07:45:41.53#ibcon#end of sib2, iclass 40, count 2 2006.190.07:45:41.53#ibcon#*mode == 0, iclass 40, count 2 2006.190.07:45:41.53#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.07:45:41.53#ibcon#[27=AT03-04\r\n] 2006.190.07:45:41.53#ibcon#*before write, iclass 40, count 2 2006.190.07:45:41.53#ibcon#enter sib2, iclass 40, count 2 2006.190.07:45:41.53#ibcon#flushed, iclass 40, count 2 2006.190.07:45:41.53#ibcon#about to write, iclass 40, count 2 2006.190.07:45:41.53#ibcon#wrote, iclass 40, count 2 2006.190.07:45:41.53#ibcon#about to read 3, iclass 40, count 2 2006.190.07:45:41.56#ibcon#read 3, iclass 40, count 2 2006.190.07:45:41.56#ibcon#about to read 4, iclass 40, count 2 2006.190.07:45:41.56#ibcon#read 4, iclass 40, count 2 2006.190.07:45:41.56#ibcon#about to read 5, iclass 40, count 2 2006.190.07:45:41.56#ibcon#read 5, iclass 40, count 2 2006.190.07:45:41.56#ibcon#about to read 6, iclass 40, count 2 2006.190.07:45:41.56#ibcon#read 6, iclass 40, count 2 2006.190.07:45:41.56#ibcon#end of sib2, iclass 40, count 2 2006.190.07:45:41.56#ibcon#*after write, iclass 40, count 2 2006.190.07:45:41.56#ibcon#*before return 0, iclass 40, count 2 2006.190.07:45:41.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:41.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:45:41.56#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.07:45:41.56#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:41.56#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:41.68#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:41.68#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:41.68#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:45:41.68#ibcon#first serial, iclass 40, count 0 2006.190.07:45:41.68#ibcon#enter sib2, iclass 40, count 0 2006.190.07:45:41.68#ibcon#flushed, iclass 40, count 0 2006.190.07:45:41.68#ibcon#about to write, iclass 40, count 0 2006.190.07:45:41.68#ibcon#wrote, iclass 40, count 0 2006.190.07:45:41.68#ibcon#about to read 3, iclass 40, count 0 2006.190.07:45:41.70#ibcon#read 3, iclass 40, count 0 2006.190.07:45:41.70#ibcon#about to read 4, iclass 40, count 0 2006.190.07:45:41.70#ibcon#read 4, iclass 40, count 0 2006.190.07:45:41.70#ibcon#about to read 5, iclass 40, count 0 2006.190.07:45:41.70#ibcon#read 5, iclass 40, count 0 2006.190.07:45:41.70#ibcon#about to read 6, iclass 40, count 0 2006.190.07:45:41.70#ibcon#read 6, iclass 40, count 0 2006.190.07:45:41.70#ibcon#end of sib2, iclass 40, count 0 2006.190.07:45:41.70#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:45:41.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:45:41.70#ibcon#[27=USB\r\n] 2006.190.07:45:41.70#ibcon#*before write, iclass 40, count 0 2006.190.07:45:41.70#ibcon#enter sib2, iclass 40, count 0 2006.190.07:45:41.70#ibcon#flushed, iclass 40, count 0 2006.190.07:45:41.70#ibcon#about to write, iclass 40, count 0 2006.190.07:45:41.70#ibcon#wrote, iclass 40, count 0 2006.190.07:45:41.70#ibcon#about to read 3, iclass 40, count 0 2006.190.07:45:41.73#ibcon#read 3, iclass 40, count 0 2006.190.07:45:41.73#ibcon#about to read 4, iclass 40, count 0 2006.190.07:45:41.73#ibcon#read 4, iclass 40, count 0 2006.190.07:45:41.73#ibcon#about to read 5, iclass 40, count 0 2006.190.07:45:41.73#ibcon#read 5, iclass 40, count 0 2006.190.07:45:41.73#ibcon#about to read 6, iclass 40, count 0 2006.190.07:45:41.73#ibcon#read 6, iclass 40, count 0 2006.190.07:45:41.73#ibcon#end of sib2, iclass 40, count 0 2006.190.07:45:41.73#ibcon#*after write, iclass 40, count 0 2006.190.07:45:41.73#ibcon#*before return 0, iclass 40, count 0 2006.190.07:45:41.73#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:41.73#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:45:41.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:45:41.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:45:41.73$vc4f8/vblo=4,712.99 2006.190.07:45:41.73#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.07:45:41.73#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.07:45:41.73#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:41.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:41.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:41.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:41.73#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:45:41.73#ibcon#first serial, iclass 4, count 0 2006.190.07:45:41.73#ibcon#enter sib2, iclass 4, count 0 2006.190.07:45:41.73#ibcon#flushed, iclass 4, count 0 2006.190.07:45:41.73#ibcon#about to write, iclass 4, count 0 2006.190.07:45:41.73#ibcon#wrote, iclass 4, count 0 2006.190.07:45:41.73#ibcon#about to read 3, iclass 4, count 0 2006.190.07:45:41.75#ibcon#read 3, iclass 4, count 0 2006.190.07:45:41.75#ibcon#about to read 4, iclass 4, count 0 2006.190.07:45:41.75#ibcon#read 4, iclass 4, count 0 2006.190.07:45:41.75#ibcon#about to read 5, iclass 4, count 0 2006.190.07:45:41.75#ibcon#read 5, iclass 4, count 0 2006.190.07:45:41.75#ibcon#about to read 6, iclass 4, count 0 2006.190.07:45:41.75#ibcon#read 6, iclass 4, count 0 2006.190.07:45:41.75#ibcon#end of sib2, iclass 4, count 0 2006.190.07:45:41.75#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:45:41.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:45:41.75#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:45:41.75#ibcon#*before write, iclass 4, count 0 2006.190.07:45:41.75#ibcon#enter sib2, iclass 4, count 0 2006.190.07:45:41.75#ibcon#flushed, iclass 4, count 0 2006.190.07:45:41.75#ibcon#about to write, iclass 4, count 0 2006.190.07:45:41.75#ibcon#wrote, iclass 4, count 0 2006.190.07:45:41.75#ibcon#about to read 3, iclass 4, count 0 2006.190.07:45:41.79#ibcon#read 3, iclass 4, count 0 2006.190.07:45:41.79#ibcon#about to read 4, iclass 4, count 0 2006.190.07:45:41.79#ibcon#read 4, iclass 4, count 0 2006.190.07:45:41.79#ibcon#about to read 5, iclass 4, count 0 2006.190.07:45:41.79#ibcon#read 5, iclass 4, count 0 2006.190.07:45:41.79#ibcon#about to read 6, iclass 4, count 0 2006.190.07:45:41.79#ibcon#read 6, iclass 4, count 0 2006.190.07:45:41.79#ibcon#end of sib2, iclass 4, count 0 2006.190.07:45:41.79#ibcon#*after write, iclass 4, count 0 2006.190.07:45:41.79#ibcon#*before return 0, iclass 4, count 0 2006.190.07:45:41.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:41.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:45:41.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:45:41.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:45:41.79$vc4f8/vb=4,4 2006.190.07:45:41.79#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.07:45:41.79#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.07:45:41.79#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:41.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:41.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:41.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:41.85#ibcon#enter wrdev, iclass 6, count 2 2006.190.07:45:41.85#ibcon#first serial, iclass 6, count 2 2006.190.07:45:41.85#ibcon#enter sib2, iclass 6, count 2 2006.190.07:45:41.85#ibcon#flushed, iclass 6, count 2 2006.190.07:45:41.85#ibcon#about to write, iclass 6, count 2 2006.190.07:45:41.85#ibcon#wrote, iclass 6, count 2 2006.190.07:45:41.85#ibcon#about to read 3, iclass 6, count 2 2006.190.07:45:41.87#ibcon#read 3, iclass 6, count 2 2006.190.07:45:41.87#ibcon#about to read 4, iclass 6, count 2 2006.190.07:45:41.87#ibcon#read 4, iclass 6, count 2 2006.190.07:45:41.87#ibcon#about to read 5, iclass 6, count 2 2006.190.07:45:41.87#ibcon#read 5, iclass 6, count 2 2006.190.07:45:41.87#ibcon#about to read 6, iclass 6, count 2 2006.190.07:45:41.87#ibcon#read 6, iclass 6, count 2 2006.190.07:45:41.87#ibcon#end of sib2, iclass 6, count 2 2006.190.07:45:41.87#ibcon#*mode == 0, iclass 6, count 2 2006.190.07:45:41.87#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.07:45:41.87#ibcon#[27=AT04-04\r\n] 2006.190.07:45:41.87#ibcon#*before write, iclass 6, count 2 2006.190.07:45:41.87#ibcon#enter sib2, iclass 6, count 2 2006.190.07:45:41.87#ibcon#flushed, iclass 6, count 2 2006.190.07:45:41.87#ibcon#about to write, iclass 6, count 2 2006.190.07:45:41.87#ibcon#wrote, iclass 6, count 2 2006.190.07:45:41.87#ibcon#about to read 3, iclass 6, count 2 2006.190.07:45:41.90#ibcon#read 3, iclass 6, count 2 2006.190.07:45:41.90#ibcon#about to read 4, iclass 6, count 2 2006.190.07:45:41.90#ibcon#read 4, iclass 6, count 2 2006.190.07:45:41.90#ibcon#about to read 5, iclass 6, count 2 2006.190.07:45:41.90#ibcon#read 5, iclass 6, count 2 2006.190.07:45:41.90#ibcon#about to read 6, iclass 6, count 2 2006.190.07:45:41.90#ibcon#read 6, iclass 6, count 2 2006.190.07:45:41.90#ibcon#end of sib2, iclass 6, count 2 2006.190.07:45:41.90#ibcon#*after write, iclass 6, count 2 2006.190.07:45:41.90#ibcon#*before return 0, iclass 6, count 2 2006.190.07:45:41.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:41.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:45:41.90#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.07:45:41.90#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:41.90#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:42.02#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:42.02#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:42.02#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:45:42.02#ibcon#first serial, iclass 6, count 0 2006.190.07:45:42.02#ibcon#enter sib2, iclass 6, count 0 2006.190.07:45:42.02#ibcon#flushed, iclass 6, count 0 2006.190.07:45:42.02#ibcon#about to write, iclass 6, count 0 2006.190.07:45:42.02#ibcon#wrote, iclass 6, count 0 2006.190.07:45:42.02#ibcon#about to read 3, iclass 6, count 0 2006.190.07:45:42.04#ibcon#read 3, iclass 6, count 0 2006.190.07:45:42.04#ibcon#about to read 4, iclass 6, count 0 2006.190.07:45:42.04#ibcon#read 4, iclass 6, count 0 2006.190.07:45:42.04#ibcon#about to read 5, iclass 6, count 0 2006.190.07:45:42.04#ibcon#read 5, iclass 6, count 0 2006.190.07:45:42.04#ibcon#about to read 6, iclass 6, count 0 2006.190.07:45:42.04#ibcon#read 6, iclass 6, count 0 2006.190.07:45:42.04#ibcon#end of sib2, iclass 6, count 0 2006.190.07:45:42.04#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:45:42.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:45:42.04#ibcon#[27=USB\r\n] 2006.190.07:45:42.04#ibcon#*before write, iclass 6, count 0 2006.190.07:45:42.04#ibcon#enter sib2, iclass 6, count 0 2006.190.07:45:42.04#ibcon#flushed, iclass 6, count 0 2006.190.07:45:42.04#ibcon#about to write, iclass 6, count 0 2006.190.07:45:42.04#ibcon#wrote, iclass 6, count 0 2006.190.07:45:42.04#ibcon#about to read 3, iclass 6, count 0 2006.190.07:45:42.07#ibcon#read 3, iclass 6, count 0 2006.190.07:45:42.07#ibcon#about to read 4, iclass 6, count 0 2006.190.07:45:42.07#ibcon#read 4, iclass 6, count 0 2006.190.07:45:42.07#ibcon#about to read 5, iclass 6, count 0 2006.190.07:45:42.07#ibcon#read 5, iclass 6, count 0 2006.190.07:45:42.07#ibcon#about to read 6, iclass 6, count 0 2006.190.07:45:42.07#ibcon#read 6, iclass 6, count 0 2006.190.07:45:42.07#ibcon#end of sib2, iclass 6, count 0 2006.190.07:45:42.07#ibcon#*after write, iclass 6, count 0 2006.190.07:45:42.07#ibcon#*before return 0, iclass 6, count 0 2006.190.07:45:42.07#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:42.07#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:45:42.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:45:42.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:45:42.07$vc4f8/vblo=5,744.99 2006.190.07:45:42.07#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.07:45:42.07#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.07:45:42.07#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:42.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:42.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:42.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:42.07#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:45:42.07#ibcon#first serial, iclass 10, count 0 2006.190.07:45:42.07#ibcon#enter sib2, iclass 10, count 0 2006.190.07:45:42.07#ibcon#flushed, iclass 10, count 0 2006.190.07:45:42.07#ibcon#about to write, iclass 10, count 0 2006.190.07:45:42.07#ibcon#wrote, iclass 10, count 0 2006.190.07:45:42.07#ibcon#about to read 3, iclass 10, count 0 2006.190.07:45:42.09#ibcon#read 3, iclass 10, count 0 2006.190.07:45:42.09#ibcon#about to read 4, iclass 10, count 0 2006.190.07:45:42.09#ibcon#read 4, iclass 10, count 0 2006.190.07:45:42.09#ibcon#about to read 5, iclass 10, count 0 2006.190.07:45:42.09#ibcon#read 5, iclass 10, count 0 2006.190.07:45:42.09#ibcon#about to read 6, iclass 10, count 0 2006.190.07:45:42.09#ibcon#read 6, iclass 10, count 0 2006.190.07:45:42.09#ibcon#end of sib2, iclass 10, count 0 2006.190.07:45:42.09#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:45:42.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:45:42.09#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:45:42.09#ibcon#*before write, iclass 10, count 0 2006.190.07:45:42.09#ibcon#enter sib2, iclass 10, count 0 2006.190.07:45:42.09#ibcon#flushed, iclass 10, count 0 2006.190.07:45:42.09#ibcon#about to write, iclass 10, count 0 2006.190.07:45:42.09#ibcon#wrote, iclass 10, count 0 2006.190.07:45:42.09#ibcon#about to read 3, iclass 10, count 0 2006.190.07:45:42.13#ibcon#read 3, iclass 10, count 0 2006.190.07:45:42.13#ibcon#about to read 4, iclass 10, count 0 2006.190.07:45:42.13#ibcon#read 4, iclass 10, count 0 2006.190.07:45:42.13#ibcon#about to read 5, iclass 10, count 0 2006.190.07:45:42.13#ibcon#read 5, iclass 10, count 0 2006.190.07:45:42.13#ibcon#about to read 6, iclass 10, count 0 2006.190.07:45:42.13#ibcon#read 6, iclass 10, count 0 2006.190.07:45:42.13#ibcon#end of sib2, iclass 10, count 0 2006.190.07:45:42.13#ibcon#*after write, iclass 10, count 0 2006.190.07:45:42.13#ibcon#*before return 0, iclass 10, count 0 2006.190.07:45:42.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:42.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:45:42.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:45:42.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:45:42.13$vc4f8/vb=5,4 2006.190.07:45:42.13#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.07:45:42.13#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.07:45:42.13#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:42.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:42.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:42.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:42.19#ibcon#enter wrdev, iclass 12, count 2 2006.190.07:45:42.19#ibcon#first serial, iclass 12, count 2 2006.190.07:45:42.19#ibcon#enter sib2, iclass 12, count 2 2006.190.07:45:42.19#ibcon#flushed, iclass 12, count 2 2006.190.07:45:42.19#ibcon#about to write, iclass 12, count 2 2006.190.07:45:42.19#ibcon#wrote, iclass 12, count 2 2006.190.07:45:42.19#ibcon#about to read 3, iclass 12, count 2 2006.190.07:45:42.21#ibcon#read 3, iclass 12, count 2 2006.190.07:45:42.21#ibcon#about to read 4, iclass 12, count 2 2006.190.07:45:42.21#ibcon#read 4, iclass 12, count 2 2006.190.07:45:42.21#ibcon#about to read 5, iclass 12, count 2 2006.190.07:45:42.21#ibcon#read 5, iclass 12, count 2 2006.190.07:45:42.21#ibcon#about to read 6, iclass 12, count 2 2006.190.07:45:42.21#ibcon#read 6, iclass 12, count 2 2006.190.07:45:42.21#ibcon#end of sib2, iclass 12, count 2 2006.190.07:45:42.21#ibcon#*mode == 0, iclass 12, count 2 2006.190.07:45:42.21#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.07:45:42.21#ibcon#[27=AT05-04\r\n] 2006.190.07:45:42.21#ibcon#*before write, iclass 12, count 2 2006.190.07:45:42.21#ibcon#enter sib2, iclass 12, count 2 2006.190.07:45:42.21#ibcon#flushed, iclass 12, count 2 2006.190.07:45:42.21#ibcon#about to write, iclass 12, count 2 2006.190.07:45:42.21#ibcon#wrote, iclass 12, count 2 2006.190.07:45:42.21#ibcon#about to read 3, iclass 12, count 2 2006.190.07:45:42.24#ibcon#read 3, iclass 12, count 2 2006.190.07:45:42.24#ibcon#about to read 4, iclass 12, count 2 2006.190.07:45:42.24#ibcon#read 4, iclass 12, count 2 2006.190.07:45:42.24#ibcon#about to read 5, iclass 12, count 2 2006.190.07:45:42.24#ibcon#read 5, iclass 12, count 2 2006.190.07:45:42.24#ibcon#about to read 6, iclass 12, count 2 2006.190.07:45:42.24#ibcon#read 6, iclass 12, count 2 2006.190.07:45:42.24#ibcon#end of sib2, iclass 12, count 2 2006.190.07:45:42.24#ibcon#*after write, iclass 12, count 2 2006.190.07:45:42.24#ibcon#*before return 0, iclass 12, count 2 2006.190.07:45:42.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:42.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:45:42.24#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.07:45:42.24#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:42.24#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:42.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:42.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:42.36#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:45:42.36#ibcon#first serial, iclass 12, count 0 2006.190.07:45:42.36#ibcon#enter sib2, iclass 12, count 0 2006.190.07:45:42.36#ibcon#flushed, iclass 12, count 0 2006.190.07:45:42.36#ibcon#about to write, iclass 12, count 0 2006.190.07:45:42.36#ibcon#wrote, iclass 12, count 0 2006.190.07:45:42.36#ibcon#about to read 3, iclass 12, count 0 2006.190.07:45:42.38#ibcon#read 3, iclass 12, count 0 2006.190.07:45:42.38#ibcon#about to read 4, iclass 12, count 0 2006.190.07:45:42.38#ibcon#read 4, iclass 12, count 0 2006.190.07:45:42.38#ibcon#about to read 5, iclass 12, count 0 2006.190.07:45:42.38#ibcon#read 5, iclass 12, count 0 2006.190.07:45:42.38#ibcon#about to read 6, iclass 12, count 0 2006.190.07:45:42.38#ibcon#read 6, iclass 12, count 0 2006.190.07:45:42.38#ibcon#end of sib2, iclass 12, count 0 2006.190.07:45:42.38#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:45:42.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:45:42.38#ibcon#[27=USB\r\n] 2006.190.07:45:42.38#ibcon#*before write, iclass 12, count 0 2006.190.07:45:42.38#ibcon#enter sib2, iclass 12, count 0 2006.190.07:45:42.38#ibcon#flushed, iclass 12, count 0 2006.190.07:45:42.38#ibcon#about to write, iclass 12, count 0 2006.190.07:45:42.38#ibcon#wrote, iclass 12, count 0 2006.190.07:45:42.38#ibcon#about to read 3, iclass 12, count 0 2006.190.07:45:42.41#ibcon#read 3, iclass 12, count 0 2006.190.07:45:42.41#ibcon#about to read 4, iclass 12, count 0 2006.190.07:45:42.41#ibcon#read 4, iclass 12, count 0 2006.190.07:45:42.41#ibcon#about to read 5, iclass 12, count 0 2006.190.07:45:42.41#ibcon#read 5, iclass 12, count 0 2006.190.07:45:42.41#ibcon#about to read 6, iclass 12, count 0 2006.190.07:45:42.41#ibcon#read 6, iclass 12, count 0 2006.190.07:45:42.41#ibcon#end of sib2, iclass 12, count 0 2006.190.07:45:42.41#ibcon#*after write, iclass 12, count 0 2006.190.07:45:42.41#ibcon#*before return 0, iclass 12, count 0 2006.190.07:45:42.41#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:42.41#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:45:42.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:45:42.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:45:42.41$vc4f8/vblo=6,752.99 2006.190.07:45:42.41#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.07:45:42.41#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.07:45:42.41#ibcon#ireg 17 cls_cnt 0 2006.190.07:45:42.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:42.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:42.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:42.41#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:45:42.41#ibcon#first serial, iclass 14, count 0 2006.190.07:45:42.41#ibcon#enter sib2, iclass 14, count 0 2006.190.07:45:42.41#ibcon#flushed, iclass 14, count 0 2006.190.07:45:42.41#ibcon#about to write, iclass 14, count 0 2006.190.07:45:42.41#ibcon#wrote, iclass 14, count 0 2006.190.07:45:42.41#ibcon#about to read 3, iclass 14, count 0 2006.190.07:45:42.43#ibcon#read 3, iclass 14, count 0 2006.190.07:45:42.43#ibcon#about to read 4, iclass 14, count 0 2006.190.07:45:42.43#ibcon#read 4, iclass 14, count 0 2006.190.07:45:42.43#ibcon#about to read 5, iclass 14, count 0 2006.190.07:45:42.43#ibcon#read 5, iclass 14, count 0 2006.190.07:45:42.43#ibcon#about to read 6, iclass 14, count 0 2006.190.07:45:42.43#ibcon#read 6, iclass 14, count 0 2006.190.07:45:42.43#ibcon#end of sib2, iclass 14, count 0 2006.190.07:45:42.43#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:45:42.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:45:42.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:45:42.43#ibcon#*before write, iclass 14, count 0 2006.190.07:45:42.43#ibcon#enter sib2, iclass 14, count 0 2006.190.07:45:42.43#ibcon#flushed, iclass 14, count 0 2006.190.07:45:42.43#ibcon#about to write, iclass 14, count 0 2006.190.07:45:42.43#ibcon#wrote, iclass 14, count 0 2006.190.07:45:42.43#ibcon#about to read 3, iclass 14, count 0 2006.190.07:45:42.47#ibcon#read 3, iclass 14, count 0 2006.190.07:45:42.47#ibcon#about to read 4, iclass 14, count 0 2006.190.07:45:42.47#ibcon#read 4, iclass 14, count 0 2006.190.07:45:42.47#ibcon#about to read 5, iclass 14, count 0 2006.190.07:45:42.47#ibcon#read 5, iclass 14, count 0 2006.190.07:45:42.47#ibcon#about to read 6, iclass 14, count 0 2006.190.07:45:42.47#ibcon#read 6, iclass 14, count 0 2006.190.07:45:42.47#ibcon#end of sib2, iclass 14, count 0 2006.190.07:45:42.47#ibcon#*after write, iclass 14, count 0 2006.190.07:45:42.47#ibcon#*before return 0, iclass 14, count 0 2006.190.07:45:42.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:42.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:45:42.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:45:42.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:45:42.47$vc4f8/vb=6,4 2006.190.07:45:42.47#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.07:45:42.47#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.07:45:42.47#ibcon#ireg 11 cls_cnt 2 2006.190.07:45:42.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:42.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:42.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:42.53#ibcon#enter wrdev, iclass 16, count 2 2006.190.07:45:42.53#ibcon#first serial, iclass 16, count 2 2006.190.07:45:42.53#ibcon#enter sib2, iclass 16, count 2 2006.190.07:45:42.53#ibcon#flushed, iclass 16, count 2 2006.190.07:45:42.53#ibcon#about to write, iclass 16, count 2 2006.190.07:45:42.53#ibcon#wrote, iclass 16, count 2 2006.190.07:45:42.53#ibcon#about to read 3, iclass 16, count 2 2006.190.07:45:42.55#ibcon#read 3, iclass 16, count 2 2006.190.07:45:42.55#ibcon#about to read 4, iclass 16, count 2 2006.190.07:45:42.55#ibcon#read 4, iclass 16, count 2 2006.190.07:45:42.55#ibcon#about to read 5, iclass 16, count 2 2006.190.07:45:42.55#ibcon#read 5, iclass 16, count 2 2006.190.07:45:42.55#ibcon#about to read 6, iclass 16, count 2 2006.190.07:45:42.55#ibcon#read 6, iclass 16, count 2 2006.190.07:45:42.55#ibcon#end of sib2, iclass 16, count 2 2006.190.07:45:42.55#ibcon#*mode == 0, iclass 16, count 2 2006.190.07:45:42.55#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.07:45:42.55#ibcon#[27=AT06-04\r\n] 2006.190.07:45:42.55#ibcon#*before write, iclass 16, count 2 2006.190.07:45:42.55#ibcon#enter sib2, iclass 16, count 2 2006.190.07:45:42.55#ibcon#flushed, iclass 16, count 2 2006.190.07:45:42.55#ibcon#about to write, iclass 16, count 2 2006.190.07:45:42.55#ibcon#wrote, iclass 16, count 2 2006.190.07:45:42.55#ibcon#about to read 3, iclass 16, count 2 2006.190.07:45:42.58#ibcon#read 3, iclass 16, count 2 2006.190.07:45:42.58#ibcon#about to read 4, iclass 16, count 2 2006.190.07:45:42.58#ibcon#read 4, iclass 16, count 2 2006.190.07:45:42.58#ibcon#about to read 5, iclass 16, count 2 2006.190.07:45:42.58#ibcon#read 5, iclass 16, count 2 2006.190.07:45:42.58#ibcon#about to read 6, iclass 16, count 2 2006.190.07:45:42.58#ibcon#read 6, iclass 16, count 2 2006.190.07:45:42.58#ibcon#end of sib2, iclass 16, count 2 2006.190.07:45:42.58#ibcon#*after write, iclass 16, count 2 2006.190.07:45:42.58#ibcon#*before return 0, iclass 16, count 2 2006.190.07:45:42.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:42.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:45:42.58#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.07:45:42.58#ibcon#ireg 7 cls_cnt 0 2006.190.07:45:42.58#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:42.70#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:42.70#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:42.70#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:45:42.70#ibcon#first serial, iclass 16, count 0 2006.190.07:45:42.70#ibcon#enter sib2, iclass 16, count 0 2006.190.07:45:42.70#ibcon#flushed, iclass 16, count 0 2006.190.07:45:42.70#ibcon#about to write, iclass 16, count 0 2006.190.07:45:42.70#ibcon#wrote, iclass 16, count 0 2006.190.07:45:42.70#ibcon#about to read 3, iclass 16, count 0 2006.190.07:45:42.72#ibcon#read 3, iclass 16, count 0 2006.190.07:45:42.72#ibcon#about to read 4, iclass 16, count 0 2006.190.07:45:42.72#ibcon#read 4, iclass 16, count 0 2006.190.07:45:42.72#ibcon#about to read 5, iclass 16, count 0 2006.190.07:45:42.72#ibcon#read 5, iclass 16, count 0 2006.190.07:45:42.72#ibcon#about to read 6, iclass 16, count 0 2006.190.07:45:42.72#ibcon#read 6, iclass 16, count 0 2006.190.07:45:42.72#ibcon#end of sib2, iclass 16, count 0 2006.190.07:45:42.72#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:45:42.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:45:42.72#ibcon#[27=USB\r\n] 2006.190.07:45:42.72#ibcon#*before write, iclass 16, count 0 2006.190.07:45:42.72#ibcon#enter sib2, iclass 16, count 0 2006.190.07:45:42.72#ibcon#flushed, iclass 16, count 0 2006.190.07:45:42.72#ibcon#about to write, iclass 16, count 0 2006.190.07:45:42.72#ibcon#wrote, iclass 16, count 0 2006.190.07:45:42.72#ibcon#about to read 3, iclass 16, count 0 2006.190.07:45:42.75#ibcon#read 3, iclass 16, count 0 2006.190.07:45:42.75#ibcon#about to read 4, iclass 16, count 0 2006.190.07:45:42.75#ibcon#read 4, iclass 16, count 0 2006.190.07:45:42.75#ibcon#about to read 5, iclass 16, count 0 2006.190.07:45:42.75#ibcon#read 5, iclass 16, count 0 2006.190.07:45:42.75#ibcon#about to read 6, iclass 16, count 0 2006.190.07:45:42.75#ibcon#read 6, iclass 16, count 0 2006.190.07:45:42.75#ibcon#end of sib2, iclass 16, count 0 2006.190.07:45:42.75#ibcon#*after write, iclass 16, count 0 2006.190.07:45:42.75#ibcon#*before return 0, iclass 16, count 0 2006.190.07:45:42.75#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:42.75#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:45:42.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:45:42.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:45:42.75$vc4f8/vabw=wide 2006.190.07:45:42.75#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.07:45:42.75#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.07:45:42.75#ibcon#ireg 8 cls_cnt 0 2006.190.07:45:42.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:42.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:42.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:42.75#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:45:42.75#ibcon#first serial, iclass 18, count 0 2006.190.07:45:42.75#ibcon#enter sib2, iclass 18, count 0 2006.190.07:45:42.75#ibcon#flushed, iclass 18, count 0 2006.190.07:45:42.75#ibcon#about to write, iclass 18, count 0 2006.190.07:45:42.75#ibcon#wrote, iclass 18, count 0 2006.190.07:45:42.75#ibcon#about to read 3, iclass 18, count 0 2006.190.07:45:42.77#ibcon#read 3, iclass 18, count 0 2006.190.07:45:42.77#ibcon#about to read 4, iclass 18, count 0 2006.190.07:45:42.77#ibcon#read 4, iclass 18, count 0 2006.190.07:45:42.77#ibcon#about to read 5, iclass 18, count 0 2006.190.07:45:42.77#ibcon#read 5, iclass 18, count 0 2006.190.07:45:42.77#ibcon#about to read 6, iclass 18, count 0 2006.190.07:45:42.77#ibcon#read 6, iclass 18, count 0 2006.190.07:45:42.77#ibcon#end of sib2, iclass 18, count 0 2006.190.07:45:42.77#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:45:42.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:45:42.77#ibcon#[25=BW32\r\n] 2006.190.07:45:42.77#ibcon#*before write, iclass 18, count 0 2006.190.07:45:42.77#ibcon#enter sib2, iclass 18, count 0 2006.190.07:45:42.77#ibcon#flushed, iclass 18, count 0 2006.190.07:45:42.77#ibcon#about to write, iclass 18, count 0 2006.190.07:45:42.77#ibcon#wrote, iclass 18, count 0 2006.190.07:45:42.77#ibcon#about to read 3, iclass 18, count 0 2006.190.07:45:42.80#ibcon#read 3, iclass 18, count 0 2006.190.07:45:42.80#ibcon#about to read 4, iclass 18, count 0 2006.190.07:45:42.80#ibcon#read 4, iclass 18, count 0 2006.190.07:45:42.80#ibcon#about to read 5, iclass 18, count 0 2006.190.07:45:42.80#ibcon#read 5, iclass 18, count 0 2006.190.07:45:42.80#ibcon#about to read 6, iclass 18, count 0 2006.190.07:45:42.80#ibcon#read 6, iclass 18, count 0 2006.190.07:45:42.80#ibcon#end of sib2, iclass 18, count 0 2006.190.07:45:42.80#ibcon#*after write, iclass 18, count 0 2006.190.07:45:42.80#ibcon#*before return 0, iclass 18, count 0 2006.190.07:45:42.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:42.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:45:42.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:45:42.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:45:42.80$vc4f8/vbbw=wide 2006.190.07:45:42.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:45:42.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:45:42.80#ibcon#ireg 8 cls_cnt 0 2006.190.07:45:42.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:45:42.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:45:42.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:45:42.87#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:45:42.87#ibcon#first serial, iclass 20, count 0 2006.190.07:45:42.87#ibcon#enter sib2, iclass 20, count 0 2006.190.07:45:42.87#ibcon#flushed, iclass 20, count 0 2006.190.07:45:42.87#ibcon#about to write, iclass 20, count 0 2006.190.07:45:42.87#ibcon#wrote, iclass 20, count 0 2006.190.07:45:42.87#ibcon#about to read 3, iclass 20, count 0 2006.190.07:45:42.89#ibcon#read 3, iclass 20, count 0 2006.190.07:45:42.89#ibcon#about to read 4, iclass 20, count 0 2006.190.07:45:42.89#ibcon#read 4, iclass 20, count 0 2006.190.07:45:42.89#ibcon#about to read 5, iclass 20, count 0 2006.190.07:45:42.89#ibcon#read 5, iclass 20, count 0 2006.190.07:45:42.89#ibcon#about to read 6, iclass 20, count 0 2006.190.07:45:42.89#ibcon#read 6, iclass 20, count 0 2006.190.07:45:42.89#ibcon#end of sib2, iclass 20, count 0 2006.190.07:45:42.89#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:45:42.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:45:42.89#ibcon#[27=BW32\r\n] 2006.190.07:45:42.89#ibcon#*before write, iclass 20, count 0 2006.190.07:45:42.89#ibcon#enter sib2, iclass 20, count 0 2006.190.07:45:42.89#ibcon#flushed, iclass 20, count 0 2006.190.07:45:42.89#ibcon#about to write, iclass 20, count 0 2006.190.07:45:42.89#ibcon#wrote, iclass 20, count 0 2006.190.07:45:42.89#ibcon#about to read 3, iclass 20, count 0 2006.190.07:45:42.92#ibcon#read 3, iclass 20, count 0 2006.190.07:45:42.92#ibcon#about to read 4, iclass 20, count 0 2006.190.07:45:42.92#ibcon#read 4, iclass 20, count 0 2006.190.07:45:42.92#ibcon#about to read 5, iclass 20, count 0 2006.190.07:45:42.92#ibcon#read 5, iclass 20, count 0 2006.190.07:45:42.92#ibcon#about to read 6, iclass 20, count 0 2006.190.07:45:42.92#ibcon#read 6, iclass 20, count 0 2006.190.07:45:42.92#ibcon#end of sib2, iclass 20, count 0 2006.190.07:45:42.92#ibcon#*after write, iclass 20, count 0 2006.190.07:45:42.92#ibcon#*before return 0, iclass 20, count 0 2006.190.07:45:42.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:45:42.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:45:42.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:45:42.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:45:42.92$4f8m12a/ifd4f 2006.190.07:45:42.92$ifd4f/lo= 2006.190.07:45:42.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:45:42.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:45:42.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:45:42.92$ifd4f/patch= 2006.190.07:45:42.92$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:45:42.92$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:45:42.92$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:45:42.92$4f8m12a/"form=m,16.000,1:2 2006.190.07:45:42.92$4f8m12a/"tpicd 2006.190.07:45:42.92$4f8m12a/echo=off 2006.190.07:45:42.92$4f8m12a/xlog=off 2006.190.07:45:42.92:!2006.190.07:46:20 2006.190.07:45:58.13#trakl#Source acquired 2006.190.07:45:58.13#flagr#flagr/antenna,acquired 2006.190.07:46:20.00:preob 2006.190.07:46:20.13/onsource/TRACKING 2006.190.07:46:20.13:!2006.190.07:46:30 2006.190.07:46:30.00:data_valid=on 2006.190.07:46:30.00:midob 2006.190.07:46:31.13/onsource/TRACKING 2006.190.07:46:31.13/wx/24.52,1012.1,100 2006.190.07:46:31.20/cable/+6.4700E-03 2006.190.07:46:32.29/va/01,08,usb,yes,35,37 2006.190.07:46:32.29/va/02,07,usb,yes,35,37 2006.190.07:46:32.29/va/03,06,usb,yes,37,38 2006.190.07:46:32.29/va/04,07,usb,yes,36,39 2006.190.07:46:32.29/va/05,07,usb,yes,40,42 2006.190.07:46:32.29/va/06,06,usb,yes,39,39 2006.190.07:46:32.29/va/07,06,usb,yes,40,40 2006.190.07:46:32.29/va/08,06,usb,yes,43,42 2006.190.07:46:32.52/valo/01,532.99,yes,locked 2006.190.07:46:32.52/valo/02,572.99,yes,locked 2006.190.07:46:32.52/valo/03,672.99,yes,locked 2006.190.07:46:32.52/valo/04,832.99,yes,locked 2006.190.07:46:32.52/valo/05,652.99,yes,locked 2006.190.07:46:32.52/valo/06,772.99,yes,locked 2006.190.07:46:32.52/valo/07,832.99,yes,locked 2006.190.07:46:32.52/valo/08,852.99,yes,locked 2006.190.07:46:33.61/vb/01,04,usb,yes,30,28 2006.190.07:46:33.61/vb/02,04,usb,yes,31,33 2006.190.07:46:33.61/vb/03,04,usb,yes,28,31 2006.190.07:46:33.61/vb/04,04,usb,yes,29,29 2006.190.07:46:33.61/vb/05,04,usb,yes,27,31 2006.190.07:46:33.61/vb/06,04,usb,yes,28,31 2006.190.07:46:33.61/vb/07,04,usb,yes,30,30 2006.190.07:46:33.61/vb/08,04,usb,yes,28,31 2006.190.07:46:33.84/vblo/01,632.99,yes,locked 2006.190.07:46:33.84/vblo/02,640.99,yes,locked 2006.190.07:46:33.84/vblo/03,656.99,yes,locked 2006.190.07:46:33.84/vblo/04,712.99,yes,locked 2006.190.07:46:33.84/vblo/05,744.99,yes,locked 2006.190.07:46:33.84/vblo/06,752.99,yes,locked 2006.190.07:46:33.84/vblo/07,734.99,yes,locked 2006.190.07:46:33.84/vblo/08,744.99,yes,locked 2006.190.07:46:33.99/vabw/8 2006.190.07:46:34.14/vbbw/8 2006.190.07:46:34.23/xfe/off,on,15.0 2006.190.07:46:34.66/ifatt/23,28,28,28 2006.190.07:46:35.08/fmout-gps/S +2.88E-07 2006.190.07:46:35.16:!2006.190.07:47:30 2006.190.07:47:30.00:data_valid=off 2006.190.07:47:30.00:postob 2006.190.07:47:30.16/cable/+6.4718E-03 2006.190.07:47:30.16/wx/24.52,1012.1,100 2006.190.07:47:31.08/fmout-gps/S +2.89E-07 2006.190.07:47:31.08:scan_name=190-0748,k06190,60 2006.190.07:47:31.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.190.07:47:31.13#flagr#flagr/antenna,new-source 2006.190.07:47:32.13:checkk5 2006.190.07:47:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:47:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:47:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:47:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:47:34.04/chk_obsdata//k5ts1/T1900746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:47:34.42/chk_obsdata//k5ts2/T1900746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:47:34.80/chk_obsdata//k5ts3/T1900746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:47:35.18/chk_obsdata//k5ts4/T1900746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:47:35.87/k5log//k5ts1_log_newline 2006.190.07:47:36.59/k5log//k5ts2_log_newline 2006.190.07:47:37.29/k5log//k5ts3_log_newline 2006.190.07:47:37.99/k5log//k5ts4_log_newline 2006.190.07:47:38.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:47:38.01:4f8m12a=1 2006.190.07:47:38.01$4f8m12a/echo=on 2006.190.07:47:38.01$4f8m12a/pcalon 2006.190.07:47:38.01$pcalon/"no phase cal control is implemented here 2006.190.07:47:38.01$4f8m12a/"tpicd=stop 2006.190.07:47:38.01$4f8m12a/vc4f8 2006.190.07:47:38.01$vc4f8/valo=1,532.99 2006.190.07:47:38.01#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.07:47:38.01#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.07:47:38.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:38.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:38.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:38.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:38.01#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:47:38.01#ibcon#first serial, iclass 35, count 0 2006.190.07:47:38.01#ibcon#enter sib2, iclass 35, count 0 2006.190.07:47:38.01#ibcon#flushed, iclass 35, count 0 2006.190.07:47:38.01#ibcon#about to write, iclass 35, count 0 2006.190.07:47:38.01#ibcon#wrote, iclass 35, count 0 2006.190.07:47:38.01#ibcon#about to read 3, iclass 35, count 0 2006.190.07:47:38.03#ibcon#read 3, iclass 35, count 0 2006.190.07:47:38.03#ibcon#about to read 4, iclass 35, count 0 2006.190.07:47:38.03#ibcon#read 4, iclass 35, count 0 2006.190.07:47:38.03#ibcon#about to read 5, iclass 35, count 0 2006.190.07:47:38.03#ibcon#read 5, iclass 35, count 0 2006.190.07:47:38.03#ibcon#about to read 6, iclass 35, count 0 2006.190.07:47:38.03#ibcon#read 6, iclass 35, count 0 2006.190.07:47:38.03#ibcon#end of sib2, iclass 35, count 0 2006.190.07:47:38.03#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:47:38.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:47:38.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:47:38.03#ibcon#*before write, iclass 35, count 0 2006.190.07:47:38.03#ibcon#enter sib2, iclass 35, count 0 2006.190.07:47:38.03#ibcon#flushed, iclass 35, count 0 2006.190.07:47:38.03#ibcon#about to write, iclass 35, count 0 2006.190.07:47:38.03#ibcon#wrote, iclass 35, count 0 2006.190.07:47:38.03#ibcon#about to read 3, iclass 35, count 0 2006.190.07:47:38.08#ibcon#read 3, iclass 35, count 0 2006.190.07:47:38.08#ibcon#about to read 4, iclass 35, count 0 2006.190.07:47:38.08#ibcon#read 4, iclass 35, count 0 2006.190.07:47:38.08#ibcon#about to read 5, iclass 35, count 0 2006.190.07:47:38.08#ibcon#read 5, iclass 35, count 0 2006.190.07:47:38.08#ibcon#about to read 6, iclass 35, count 0 2006.190.07:47:38.08#ibcon#read 6, iclass 35, count 0 2006.190.07:47:38.08#ibcon#end of sib2, iclass 35, count 0 2006.190.07:47:38.08#ibcon#*after write, iclass 35, count 0 2006.190.07:47:38.08#ibcon#*before return 0, iclass 35, count 0 2006.190.07:47:38.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:38.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:38.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:47:38.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:47:38.08$vc4f8/va=1,8 2006.190.07:47:38.08#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.07:47:38.08#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.07:47:38.08#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:38.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:38.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:38.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:38.08#ibcon#enter wrdev, iclass 37, count 2 2006.190.07:47:38.08#ibcon#first serial, iclass 37, count 2 2006.190.07:47:38.08#ibcon#enter sib2, iclass 37, count 2 2006.190.07:47:38.08#ibcon#flushed, iclass 37, count 2 2006.190.07:47:38.08#ibcon#about to write, iclass 37, count 2 2006.190.07:47:38.08#ibcon#wrote, iclass 37, count 2 2006.190.07:47:38.08#ibcon#about to read 3, iclass 37, count 2 2006.190.07:47:38.10#ibcon#read 3, iclass 37, count 2 2006.190.07:47:38.10#ibcon#about to read 4, iclass 37, count 2 2006.190.07:47:38.10#ibcon#read 4, iclass 37, count 2 2006.190.07:47:38.10#ibcon#about to read 5, iclass 37, count 2 2006.190.07:47:38.10#ibcon#read 5, iclass 37, count 2 2006.190.07:47:38.10#ibcon#about to read 6, iclass 37, count 2 2006.190.07:47:38.10#ibcon#read 6, iclass 37, count 2 2006.190.07:47:38.10#ibcon#end of sib2, iclass 37, count 2 2006.190.07:47:38.10#ibcon#*mode == 0, iclass 37, count 2 2006.190.07:47:38.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.07:47:38.10#ibcon#[25=AT01-08\r\n] 2006.190.07:47:38.10#ibcon#*before write, iclass 37, count 2 2006.190.07:47:38.10#ibcon#enter sib2, iclass 37, count 2 2006.190.07:47:38.10#ibcon#flushed, iclass 37, count 2 2006.190.07:47:38.10#ibcon#about to write, iclass 37, count 2 2006.190.07:47:38.10#ibcon#wrote, iclass 37, count 2 2006.190.07:47:38.10#ibcon#about to read 3, iclass 37, count 2 2006.190.07:47:38.13#ibcon#read 3, iclass 37, count 2 2006.190.07:47:38.13#ibcon#about to read 4, iclass 37, count 2 2006.190.07:47:38.13#ibcon#read 4, iclass 37, count 2 2006.190.07:47:38.13#ibcon#about to read 5, iclass 37, count 2 2006.190.07:47:38.13#ibcon#read 5, iclass 37, count 2 2006.190.07:47:38.13#ibcon#about to read 6, iclass 37, count 2 2006.190.07:47:38.13#ibcon#read 6, iclass 37, count 2 2006.190.07:47:38.13#ibcon#end of sib2, iclass 37, count 2 2006.190.07:47:38.13#ibcon#*after write, iclass 37, count 2 2006.190.07:47:38.13#ibcon#*before return 0, iclass 37, count 2 2006.190.07:47:38.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:38.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:38.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.07:47:38.13#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:38.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:38.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:38.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:38.26#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:47:38.26#ibcon#first serial, iclass 37, count 0 2006.190.07:47:38.26#ibcon#enter sib2, iclass 37, count 0 2006.190.07:47:38.26#ibcon#flushed, iclass 37, count 0 2006.190.07:47:38.26#ibcon#about to write, iclass 37, count 0 2006.190.07:47:38.26#ibcon#wrote, iclass 37, count 0 2006.190.07:47:38.26#ibcon#about to read 3, iclass 37, count 0 2006.190.07:47:38.28#ibcon#read 3, iclass 37, count 0 2006.190.07:47:38.28#ibcon#about to read 4, iclass 37, count 0 2006.190.07:47:38.28#ibcon#read 4, iclass 37, count 0 2006.190.07:47:38.28#ibcon#about to read 5, iclass 37, count 0 2006.190.07:47:38.28#ibcon#read 5, iclass 37, count 0 2006.190.07:47:38.28#ibcon#about to read 6, iclass 37, count 0 2006.190.07:47:38.28#ibcon#read 6, iclass 37, count 0 2006.190.07:47:38.28#ibcon#end of sib2, iclass 37, count 0 2006.190.07:47:38.28#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:47:38.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:47:38.28#ibcon#[25=USB\r\n] 2006.190.07:47:38.28#ibcon#*before write, iclass 37, count 0 2006.190.07:47:38.28#ibcon#enter sib2, iclass 37, count 0 2006.190.07:47:38.28#ibcon#flushed, iclass 37, count 0 2006.190.07:47:38.28#ibcon#about to write, iclass 37, count 0 2006.190.07:47:38.28#ibcon#wrote, iclass 37, count 0 2006.190.07:47:38.28#ibcon#about to read 3, iclass 37, count 0 2006.190.07:47:38.31#ibcon#read 3, iclass 37, count 0 2006.190.07:47:38.31#ibcon#about to read 4, iclass 37, count 0 2006.190.07:47:38.31#ibcon#read 4, iclass 37, count 0 2006.190.07:47:38.31#ibcon#about to read 5, iclass 37, count 0 2006.190.07:47:38.31#ibcon#read 5, iclass 37, count 0 2006.190.07:47:38.31#ibcon#about to read 6, iclass 37, count 0 2006.190.07:47:38.31#ibcon#read 6, iclass 37, count 0 2006.190.07:47:38.31#ibcon#end of sib2, iclass 37, count 0 2006.190.07:47:38.31#ibcon#*after write, iclass 37, count 0 2006.190.07:47:38.31#ibcon#*before return 0, iclass 37, count 0 2006.190.07:47:38.31#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:38.31#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:38.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:47:38.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:47:38.31$vc4f8/valo=2,572.99 2006.190.07:47:38.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.07:47:38.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.07:47:38.31#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:38.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:38.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:38.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:38.31#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:47:38.31#ibcon#first serial, iclass 39, count 0 2006.190.07:47:38.31#ibcon#enter sib2, iclass 39, count 0 2006.190.07:47:38.31#ibcon#flushed, iclass 39, count 0 2006.190.07:47:38.31#ibcon#about to write, iclass 39, count 0 2006.190.07:47:38.31#ibcon#wrote, iclass 39, count 0 2006.190.07:47:38.31#ibcon#about to read 3, iclass 39, count 0 2006.190.07:47:38.33#ibcon#read 3, iclass 39, count 0 2006.190.07:47:38.33#ibcon#about to read 4, iclass 39, count 0 2006.190.07:47:38.33#ibcon#read 4, iclass 39, count 0 2006.190.07:47:38.33#ibcon#about to read 5, iclass 39, count 0 2006.190.07:47:38.33#ibcon#read 5, iclass 39, count 0 2006.190.07:47:38.33#ibcon#about to read 6, iclass 39, count 0 2006.190.07:47:38.33#ibcon#read 6, iclass 39, count 0 2006.190.07:47:38.33#ibcon#end of sib2, iclass 39, count 0 2006.190.07:47:38.33#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:47:38.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:47:38.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:47:38.33#ibcon#*before write, iclass 39, count 0 2006.190.07:47:38.33#ibcon#enter sib2, iclass 39, count 0 2006.190.07:47:38.33#ibcon#flushed, iclass 39, count 0 2006.190.07:47:38.33#ibcon#about to write, iclass 39, count 0 2006.190.07:47:38.33#ibcon#wrote, iclass 39, count 0 2006.190.07:47:38.33#ibcon#about to read 3, iclass 39, count 0 2006.190.07:47:38.38#ibcon#read 3, iclass 39, count 0 2006.190.07:47:38.38#ibcon#about to read 4, iclass 39, count 0 2006.190.07:47:38.38#ibcon#read 4, iclass 39, count 0 2006.190.07:47:38.38#ibcon#about to read 5, iclass 39, count 0 2006.190.07:47:38.38#ibcon#read 5, iclass 39, count 0 2006.190.07:47:38.38#ibcon#about to read 6, iclass 39, count 0 2006.190.07:47:38.38#ibcon#read 6, iclass 39, count 0 2006.190.07:47:38.38#ibcon#end of sib2, iclass 39, count 0 2006.190.07:47:38.38#ibcon#*after write, iclass 39, count 0 2006.190.07:47:38.38#ibcon#*before return 0, iclass 39, count 0 2006.190.07:47:38.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:38.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:38.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:47:38.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:47:38.38$vc4f8/va=2,7 2006.190.07:47:38.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.07:47:38.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.07:47:38.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:38.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:38.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:38.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:38.42#ibcon#enter wrdev, iclass 3, count 2 2006.190.07:47:38.42#ibcon#first serial, iclass 3, count 2 2006.190.07:47:38.42#ibcon#enter sib2, iclass 3, count 2 2006.190.07:47:38.42#ibcon#flushed, iclass 3, count 2 2006.190.07:47:38.42#ibcon#about to write, iclass 3, count 2 2006.190.07:47:38.42#ibcon#wrote, iclass 3, count 2 2006.190.07:47:38.42#ibcon#about to read 3, iclass 3, count 2 2006.190.07:47:38.44#ibcon#read 3, iclass 3, count 2 2006.190.07:47:38.44#ibcon#about to read 4, iclass 3, count 2 2006.190.07:47:38.44#ibcon#read 4, iclass 3, count 2 2006.190.07:47:38.44#ibcon#about to read 5, iclass 3, count 2 2006.190.07:47:38.44#ibcon#read 5, iclass 3, count 2 2006.190.07:47:38.44#ibcon#about to read 6, iclass 3, count 2 2006.190.07:47:38.44#ibcon#read 6, iclass 3, count 2 2006.190.07:47:38.44#ibcon#end of sib2, iclass 3, count 2 2006.190.07:47:38.44#ibcon#*mode == 0, iclass 3, count 2 2006.190.07:47:38.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.07:47:38.44#ibcon#[25=AT02-07\r\n] 2006.190.07:47:38.44#ibcon#*before write, iclass 3, count 2 2006.190.07:47:38.44#ibcon#enter sib2, iclass 3, count 2 2006.190.07:47:38.44#ibcon#flushed, iclass 3, count 2 2006.190.07:47:38.44#ibcon#about to write, iclass 3, count 2 2006.190.07:47:38.44#ibcon#wrote, iclass 3, count 2 2006.190.07:47:38.44#ibcon#about to read 3, iclass 3, count 2 2006.190.07:47:38.47#ibcon#read 3, iclass 3, count 2 2006.190.07:47:38.47#ibcon#about to read 4, iclass 3, count 2 2006.190.07:47:38.47#ibcon#read 4, iclass 3, count 2 2006.190.07:47:38.47#ibcon#about to read 5, iclass 3, count 2 2006.190.07:47:38.47#ibcon#read 5, iclass 3, count 2 2006.190.07:47:38.47#ibcon#about to read 6, iclass 3, count 2 2006.190.07:47:38.47#ibcon#read 6, iclass 3, count 2 2006.190.07:47:38.47#ibcon#end of sib2, iclass 3, count 2 2006.190.07:47:38.47#ibcon#*after write, iclass 3, count 2 2006.190.07:47:38.47#ibcon#*before return 0, iclass 3, count 2 2006.190.07:47:38.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:38.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:38.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.07:47:38.47#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:38.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:38.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:38.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:38.59#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:47:38.59#ibcon#first serial, iclass 3, count 0 2006.190.07:47:38.59#ibcon#enter sib2, iclass 3, count 0 2006.190.07:47:38.59#ibcon#flushed, iclass 3, count 0 2006.190.07:47:38.59#ibcon#about to write, iclass 3, count 0 2006.190.07:47:38.59#ibcon#wrote, iclass 3, count 0 2006.190.07:47:38.59#ibcon#about to read 3, iclass 3, count 0 2006.190.07:47:38.61#ibcon#read 3, iclass 3, count 0 2006.190.07:47:38.61#ibcon#about to read 4, iclass 3, count 0 2006.190.07:47:38.61#ibcon#read 4, iclass 3, count 0 2006.190.07:47:38.61#ibcon#about to read 5, iclass 3, count 0 2006.190.07:47:38.61#ibcon#read 5, iclass 3, count 0 2006.190.07:47:38.61#ibcon#about to read 6, iclass 3, count 0 2006.190.07:47:38.61#ibcon#read 6, iclass 3, count 0 2006.190.07:47:38.61#ibcon#end of sib2, iclass 3, count 0 2006.190.07:47:38.61#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:47:38.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:47:38.61#ibcon#[25=USB\r\n] 2006.190.07:47:38.61#ibcon#*before write, iclass 3, count 0 2006.190.07:47:38.61#ibcon#enter sib2, iclass 3, count 0 2006.190.07:47:38.61#ibcon#flushed, iclass 3, count 0 2006.190.07:47:38.61#ibcon#about to write, iclass 3, count 0 2006.190.07:47:38.61#ibcon#wrote, iclass 3, count 0 2006.190.07:47:38.61#ibcon#about to read 3, iclass 3, count 0 2006.190.07:47:38.64#ibcon#read 3, iclass 3, count 0 2006.190.07:47:38.64#ibcon#about to read 4, iclass 3, count 0 2006.190.07:47:38.64#ibcon#read 4, iclass 3, count 0 2006.190.07:47:38.64#ibcon#about to read 5, iclass 3, count 0 2006.190.07:47:38.64#ibcon#read 5, iclass 3, count 0 2006.190.07:47:38.64#ibcon#about to read 6, iclass 3, count 0 2006.190.07:47:38.64#ibcon#read 6, iclass 3, count 0 2006.190.07:47:38.64#ibcon#end of sib2, iclass 3, count 0 2006.190.07:47:38.64#ibcon#*after write, iclass 3, count 0 2006.190.07:47:38.64#ibcon#*before return 0, iclass 3, count 0 2006.190.07:47:38.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:38.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:38.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:47:38.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:47:38.64$vc4f8/valo=3,672.99 2006.190.07:47:38.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.07:47:38.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.07:47:38.64#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:38.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:38.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:38.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:38.64#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:47:38.64#ibcon#first serial, iclass 5, count 0 2006.190.07:47:38.64#ibcon#enter sib2, iclass 5, count 0 2006.190.07:47:38.64#ibcon#flushed, iclass 5, count 0 2006.190.07:47:38.64#ibcon#about to write, iclass 5, count 0 2006.190.07:47:38.64#ibcon#wrote, iclass 5, count 0 2006.190.07:47:38.64#ibcon#about to read 3, iclass 5, count 0 2006.190.07:47:38.66#ibcon#read 3, iclass 5, count 0 2006.190.07:47:38.66#ibcon#about to read 4, iclass 5, count 0 2006.190.07:47:38.66#ibcon#read 4, iclass 5, count 0 2006.190.07:47:38.66#ibcon#about to read 5, iclass 5, count 0 2006.190.07:47:38.66#ibcon#read 5, iclass 5, count 0 2006.190.07:47:38.66#ibcon#about to read 6, iclass 5, count 0 2006.190.07:47:38.66#ibcon#read 6, iclass 5, count 0 2006.190.07:47:38.66#ibcon#end of sib2, iclass 5, count 0 2006.190.07:47:38.66#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:47:38.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:47:38.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:47:38.66#ibcon#*before write, iclass 5, count 0 2006.190.07:47:38.66#ibcon#enter sib2, iclass 5, count 0 2006.190.07:47:38.66#ibcon#flushed, iclass 5, count 0 2006.190.07:47:38.66#ibcon#about to write, iclass 5, count 0 2006.190.07:47:38.66#ibcon#wrote, iclass 5, count 0 2006.190.07:47:38.66#ibcon#about to read 3, iclass 5, count 0 2006.190.07:47:38.70#ibcon#read 3, iclass 5, count 0 2006.190.07:47:38.70#ibcon#about to read 4, iclass 5, count 0 2006.190.07:47:38.70#ibcon#read 4, iclass 5, count 0 2006.190.07:47:38.70#ibcon#about to read 5, iclass 5, count 0 2006.190.07:47:38.70#ibcon#read 5, iclass 5, count 0 2006.190.07:47:38.70#ibcon#about to read 6, iclass 5, count 0 2006.190.07:47:38.70#ibcon#read 6, iclass 5, count 0 2006.190.07:47:38.70#ibcon#end of sib2, iclass 5, count 0 2006.190.07:47:38.70#ibcon#*after write, iclass 5, count 0 2006.190.07:47:38.70#ibcon#*before return 0, iclass 5, count 0 2006.190.07:47:38.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:38.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:38.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:47:38.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:47:38.70$vc4f8/va=3,6 2006.190.07:47:38.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.07:47:38.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.07:47:38.70#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:38.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:38.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:38.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:38.76#ibcon#enter wrdev, iclass 7, count 2 2006.190.07:47:38.76#ibcon#first serial, iclass 7, count 2 2006.190.07:47:38.76#ibcon#enter sib2, iclass 7, count 2 2006.190.07:47:38.76#ibcon#flushed, iclass 7, count 2 2006.190.07:47:38.76#ibcon#about to write, iclass 7, count 2 2006.190.07:47:38.76#ibcon#wrote, iclass 7, count 2 2006.190.07:47:38.76#ibcon#about to read 3, iclass 7, count 2 2006.190.07:47:38.78#ibcon#read 3, iclass 7, count 2 2006.190.07:47:38.78#ibcon#about to read 4, iclass 7, count 2 2006.190.07:47:38.78#ibcon#read 4, iclass 7, count 2 2006.190.07:47:38.78#ibcon#about to read 5, iclass 7, count 2 2006.190.07:47:38.78#ibcon#read 5, iclass 7, count 2 2006.190.07:47:38.78#ibcon#about to read 6, iclass 7, count 2 2006.190.07:47:38.78#ibcon#read 6, iclass 7, count 2 2006.190.07:47:38.78#ibcon#end of sib2, iclass 7, count 2 2006.190.07:47:38.78#ibcon#*mode == 0, iclass 7, count 2 2006.190.07:47:38.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.07:47:38.78#ibcon#[25=AT03-06\r\n] 2006.190.07:47:38.78#ibcon#*before write, iclass 7, count 2 2006.190.07:47:38.78#ibcon#enter sib2, iclass 7, count 2 2006.190.07:47:38.78#ibcon#flushed, iclass 7, count 2 2006.190.07:47:38.78#ibcon#about to write, iclass 7, count 2 2006.190.07:47:38.78#ibcon#wrote, iclass 7, count 2 2006.190.07:47:38.78#ibcon#about to read 3, iclass 7, count 2 2006.190.07:47:38.81#ibcon#read 3, iclass 7, count 2 2006.190.07:47:38.81#ibcon#about to read 4, iclass 7, count 2 2006.190.07:47:38.81#ibcon#read 4, iclass 7, count 2 2006.190.07:47:38.81#ibcon#about to read 5, iclass 7, count 2 2006.190.07:47:38.81#ibcon#read 5, iclass 7, count 2 2006.190.07:47:38.81#ibcon#about to read 6, iclass 7, count 2 2006.190.07:47:38.81#ibcon#read 6, iclass 7, count 2 2006.190.07:47:38.81#ibcon#end of sib2, iclass 7, count 2 2006.190.07:47:38.81#ibcon#*after write, iclass 7, count 2 2006.190.07:47:38.81#ibcon#*before return 0, iclass 7, count 2 2006.190.07:47:38.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:38.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:38.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.07:47:38.81#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:38.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:38.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:38.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:38.93#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:47:38.93#ibcon#first serial, iclass 7, count 0 2006.190.07:47:38.93#ibcon#enter sib2, iclass 7, count 0 2006.190.07:47:38.93#ibcon#flushed, iclass 7, count 0 2006.190.07:47:38.93#ibcon#about to write, iclass 7, count 0 2006.190.07:47:38.93#ibcon#wrote, iclass 7, count 0 2006.190.07:47:38.93#ibcon#about to read 3, iclass 7, count 0 2006.190.07:47:38.95#ibcon#read 3, iclass 7, count 0 2006.190.07:47:38.95#ibcon#about to read 4, iclass 7, count 0 2006.190.07:47:38.95#ibcon#read 4, iclass 7, count 0 2006.190.07:47:38.95#ibcon#about to read 5, iclass 7, count 0 2006.190.07:47:38.95#ibcon#read 5, iclass 7, count 0 2006.190.07:47:38.95#ibcon#about to read 6, iclass 7, count 0 2006.190.07:47:38.95#ibcon#read 6, iclass 7, count 0 2006.190.07:47:38.95#ibcon#end of sib2, iclass 7, count 0 2006.190.07:47:38.95#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:47:38.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:47:38.95#ibcon#[25=USB\r\n] 2006.190.07:47:38.95#ibcon#*before write, iclass 7, count 0 2006.190.07:47:38.95#ibcon#enter sib2, iclass 7, count 0 2006.190.07:47:38.95#ibcon#flushed, iclass 7, count 0 2006.190.07:47:38.95#ibcon#about to write, iclass 7, count 0 2006.190.07:47:38.95#ibcon#wrote, iclass 7, count 0 2006.190.07:47:38.95#ibcon#about to read 3, iclass 7, count 0 2006.190.07:47:38.98#ibcon#read 3, iclass 7, count 0 2006.190.07:47:38.98#ibcon#about to read 4, iclass 7, count 0 2006.190.07:47:38.98#ibcon#read 4, iclass 7, count 0 2006.190.07:47:38.98#ibcon#about to read 5, iclass 7, count 0 2006.190.07:47:38.98#ibcon#read 5, iclass 7, count 0 2006.190.07:47:38.98#ibcon#about to read 6, iclass 7, count 0 2006.190.07:47:38.98#ibcon#read 6, iclass 7, count 0 2006.190.07:47:38.98#ibcon#end of sib2, iclass 7, count 0 2006.190.07:47:38.98#ibcon#*after write, iclass 7, count 0 2006.190.07:47:38.98#ibcon#*before return 0, iclass 7, count 0 2006.190.07:47:38.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:38.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:38.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:47:38.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:47:38.98$vc4f8/valo=4,832.99 2006.190.07:47:38.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.07:47:38.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.07:47:38.98#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:38.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:38.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:38.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:38.98#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:47:38.98#ibcon#first serial, iclass 11, count 0 2006.190.07:47:38.98#ibcon#enter sib2, iclass 11, count 0 2006.190.07:47:38.98#ibcon#flushed, iclass 11, count 0 2006.190.07:47:38.98#ibcon#about to write, iclass 11, count 0 2006.190.07:47:38.98#ibcon#wrote, iclass 11, count 0 2006.190.07:47:38.98#ibcon#about to read 3, iclass 11, count 0 2006.190.07:47:39.00#ibcon#read 3, iclass 11, count 0 2006.190.07:47:39.00#ibcon#about to read 4, iclass 11, count 0 2006.190.07:47:39.00#ibcon#read 4, iclass 11, count 0 2006.190.07:47:39.00#ibcon#about to read 5, iclass 11, count 0 2006.190.07:47:39.00#ibcon#read 5, iclass 11, count 0 2006.190.07:47:39.00#ibcon#about to read 6, iclass 11, count 0 2006.190.07:47:39.00#ibcon#read 6, iclass 11, count 0 2006.190.07:47:39.00#ibcon#end of sib2, iclass 11, count 0 2006.190.07:47:39.00#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:47:39.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:47:39.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:47:39.00#ibcon#*before write, iclass 11, count 0 2006.190.07:47:39.00#ibcon#enter sib2, iclass 11, count 0 2006.190.07:47:39.00#ibcon#flushed, iclass 11, count 0 2006.190.07:47:39.00#ibcon#about to write, iclass 11, count 0 2006.190.07:47:39.00#ibcon#wrote, iclass 11, count 0 2006.190.07:47:39.00#ibcon#about to read 3, iclass 11, count 0 2006.190.07:47:39.04#ibcon#read 3, iclass 11, count 0 2006.190.07:47:39.04#ibcon#about to read 4, iclass 11, count 0 2006.190.07:47:39.04#ibcon#read 4, iclass 11, count 0 2006.190.07:47:39.04#ibcon#about to read 5, iclass 11, count 0 2006.190.07:47:39.04#ibcon#read 5, iclass 11, count 0 2006.190.07:47:39.04#ibcon#about to read 6, iclass 11, count 0 2006.190.07:47:39.04#ibcon#read 6, iclass 11, count 0 2006.190.07:47:39.04#ibcon#end of sib2, iclass 11, count 0 2006.190.07:47:39.04#ibcon#*after write, iclass 11, count 0 2006.190.07:47:39.04#ibcon#*before return 0, iclass 11, count 0 2006.190.07:47:39.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:39.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:39.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:47:39.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:47:39.04$vc4f8/va=4,7 2006.190.07:47:39.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.07:47:39.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.07:47:39.04#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:39.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:39.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:39.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:39.10#ibcon#enter wrdev, iclass 13, count 2 2006.190.07:47:39.10#ibcon#first serial, iclass 13, count 2 2006.190.07:47:39.10#ibcon#enter sib2, iclass 13, count 2 2006.190.07:47:39.10#ibcon#flushed, iclass 13, count 2 2006.190.07:47:39.10#ibcon#about to write, iclass 13, count 2 2006.190.07:47:39.10#ibcon#wrote, iclass 13, count 2 2006.190.07:47:39.10#ibcon#about to read 3, iclass 13, count 2 2006.190.07:47:39.12#ibcon#read 3, iclass 13, count 2 2006.190.07:47:39.12#ibcon#about to read 4, iclass 13, count 2 2006.190.07:47:39.12#ibcon#read 4, iclass 13, count 2 2006.190.07:47:39.12#ibcon#about to read 5, iclass 13, count 2 2006.190.07:47:39.12#ibcon#read 5, iclass 13, count 2 2006.190.07:47:39.12#ibcon#about to read 6, iclass 13, count 2 2006.190.07:47:39.12#ibcon#read 6, iclass 13, count 2 2006.190.07:47:39.12#ibcon#end of sib2, iclass 13, count 2 2006.190.07:47:39.12#ibcon#*mode == 0, iclass 13, count 2 2006.190.07:47:39.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.07:47:39.12#ibcon#[25=AT04-07\r\n] 2006.190.07:47:39.12#ibcon#*before write, iclass 13, count 2 2006.190.07:47:39.12#ibcon#enter sib2, iclass 13, count 2 2006.190.07:47:39.12#ibcon#flushed, iclass 13, count 2 2006.190.07:47:39.12#ibcon#about to write, iclass 13, count 2 2006.190.07:47:39.12#ibcon#wrote, iclass 13, count 2 2006.190.07:47:39.12#ibcon#about to read 3, iclass 13, count 2 2006.190.07:47:39.15#ibcon#read 3, iclass 13, count 2 2006.190.07:47:39.15#ibcon#about to read 4, iclass 13, count 2 2006.190.07:47:39.15#ibcon#read 4, iclass 13, count 2 2006.190.07:47:39.15#ibcon#about to read 5, iclass 13, count 2 2006.190.07:47:39.15#ibcon#read 5, iclass 13, count 2 2006.190.07:47:39.15#ibcon#about to read 6, iclass 13, count 2 2006.190.07:47:39.15#ibcon#read 6, iclass 13, count 2 2006.190.07:47:39.15#ibcon#end of sib2, iclass 13, count 2 2006.190.07:47:39.15#ibcon#*after write, iclass 13, count 2 2006.190.07:47:39.15#ibcon#*before return 0, iclass 13, count 2 2006.190.07:47:39.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:39.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:39.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.07:47:39.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:39.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:39.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:39.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:39.27#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:47:39.27#ibcon#first serial, iclass 13, count 0 2006.190.07:47:39.27#ibcon#enter sib2, iclass 13, count 0 2006.190.07:47:39.27#ibcon#flushed, iclass 13, count 0 2006.190.07:47:39.27#ibcon#about to write, iclass 13, count 0 2006.190.07:47:39.27#ibcon#wrote, iclass 13, count 0 2006.190.07:47:39.27#ibcon#about to read 3, iclass 13, count 0 2006.190.07:47:39.29#ibcon#read 3, iclass 13, count 0 2006.190.07:47:39.29#ibcon#about to read 4, iclass 13, count 0 2006.190.07:47:39.29#ibcon#read 4, iclass 13, count 0 2006.190.07:47:39.29#ibcon#about to read 5, iclass 13, count 0 2006.190.07:47:39.29#ibcon#read 5, iclass 13, count 0 2006.190.07:47:39.29#ibcon#about to read 6, iclass 13, count 0 2006.190.07:47:39.29#ibcon#read 6, iclass 13, count 0 2006.190.07:47:39.29#ibcon#end of sib2, iclass 13, count 0 2006.190.07:47:39.29#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:47:39.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:47:39.29#ibcon#[25=USB\r\n] 2006.190.07:47:39.29#ibcon#*before write, iclass 13, count 0 2006.190.07:47:39.29#ibcon#enter sib2, iclass 13, count 0 2006.190.07:47:39.29#ibcon#flushed, iclass 13, count 0 2006.190.07:47:39.29#ibcon#about to write, iclass 13, count 0 2006.190.07:47:39.29#ibcon#wrote, iclass 13, count 0 2006.190.07:47:39.29#ibcon#about to read 3, iclass 13, count 0 2006.190.07:47:39.32#ibcon#read 3, iclass 13, count 0 2006.190.07:47:39.32#ibcon#about to read 4, iclass 13, count 0 2006.190.07:47:39.32#ibcon#read 4, iclass 13, count 0 2006.190.07:47:39.32#ibcon#about to read 5, iclass 13, count 0 2006.190.07:47:39.32#ibcon#read 5, iclass 13, count 0 2006.190.07:47:39.32#ibcon#about to read 6, iclass 13, count 0 2006.190.07:47:39.32#ibcon#read 6, iclass 13, count 0 2006.190.07:47:39.32#ibcon#end of sib2, iclass 13, count 0 2006.190.07:47:39.32#ibcon#*after write, iclass 13, count 0 2006.190.07:47:39.32#ibcon#*before return 0, iclass 13, count 0 2006.190.07:47:39.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:39.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:39.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:47:39.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:47:39.32$vc4f8/valo=5,652.99 2006.190.07:47:39.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:47:39.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:47:39.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:39.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:39.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:39.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:39.32#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:47:39.32#ibcon#first serial, iclass 15, count 0 2006.190.07:47:39.32#ibcon#enter sib2, iclass 15, count 0 2006.190.07:47:39.32#ibcon#flushed, iclass 15, count 0 2006.190.07:47:39.32#ibcon#about to write, iclass 15, count 0 2006.190.07:47:39.32#ibcon#wrote, iclass 15, count 0 2006.190.07:47:39.32#ibcon#about to read 3, iclass 15, count 0 2006.190.07:47:39.34#ibcon#read 3, iclass 15, count 0 2006.190.07:47:39.34#ibcon#about to read 4, iclass 15, count 0 2006.190.07:47:39.34#ibcon#read 4, iclass 15, count 0 2006.190.07:47:39.34#ibcon#about to read 5, iclass 15, count 0 2006.190.07:47:39.34#ibcon#read 5, iclass 15, count 0 2006.190.07:47:39.34#ibcon#about to read 6, iclass 15, count 0 2006.190.07:47:39.34#ibcon#read 6, iclass 15, count 0 2006.190.07:47:39.34#ibcon#end of sib2, iclass 15, count 0 2006.190.07:47:39.34#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:47:39.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:47:39.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:47:39.34#ibcon#*before write, iclass 15, count 0 2006.190.07:47:39.34#ibcon#enter sib2, iclass 15, count 0 2006.190.07:47:39.34#ibcon#flushed, iclass 15, count 0 2006.190.07:47:39.34#ibcon#about to write, iclass 15, count 0 2006.190.07:47:39.34#ibcon#wrote, iclass 15, count 0 2006.190.07:47:39.34#ibcon#about to read 3, iclass 15, count 0 2006.190.07:47:39.38#ibcon#read 3, iclass 15, count 0 2006.190.07:47:39.38#ibcon#about to read 4, iclass 15, count 0 2006.190.07:47:39.38#ibcon#read 4, iclass 15, count 0 2006.190.07:47:39.38#ibcon#about to read 5, iclass 15, count 0 2006.190.07:47:39.38#ibcon#read 5, iclass 15, count 0 2006.190.07:47:39.38#ibcon#about to read 6, iclass 15, count 0 2006.190.07:47:39.38#ibcon#read 6, iclass 15, count 0 2006.190.07:47:39.38#ibcon#end of sib2, iclass 15, count 0 2006.190.07:47:39.38#ibcon#*after write, iclass 15, count 0 2006.190.07:47:39.38#ibcon#*before return 0, iclass 15, count 0 2006.190.07:47:39.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:39.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:39.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:47:39.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:47:39.38$vc4f8/va=5,7 2006.190.07:47:39.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.07:47:39.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.07:47:39.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:39.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:39.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:39.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:39.44#ibcon#enter wrdev, iclass 17, count 2 2006.190.07:47:39.44#ibcon#first serial, iclass 17, count 2 2006.190.07:47:39.44#ibcon#enter sib2, iclass 17, count 2 2006.190.07:47:39.44#ibcon#flushed, iclass 17, count 2 2006.190.07:47:39.44#ibcon#about to write, iclass 17, count 2 2006.190.07:47:39.44#ibcon#wrote, iclass 17, count 2 2006.190.07:47:39.44#ibcon#about to read 3, iclass 17, count 2 2006.190.07:47:39.46#ibcon#read 3, iclass 17, count 2 2006.190.07:47:39.46#ibcon#about to read 4, iclass 17, count 2 2006.190.07:47:39.46#ibcon#read 4, iclass 17, count 2 2006.190.07:47:39.46#ibcon#about to read 5, iclass 17, count 2 2006.190.07:47:39.46#ibcon#read 5, iclass 17, count 2 2006.190.07:47:39.46#ibcon#about to read 6, iclass 17, count 2 2006.190.07:47:39.46#ibcon#read 6, iclass 17, count 2 2006.190.07:47:39.46#ibcon#end of sib2, iclass 17, count 2 2006.190.07:47:39.46#ibcon#*mode == 0, iclass 17, count 2 2006.190.07:47:39.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.07:47:39.46#ibcon#[25=AT05-07\r\n] 2006.190.07:47:39.46#ibcon#*before write, iclass 17, count 2 2006.190.07:47:39.46#ibcon#enter sib2, iclass 17, count 2 2006.190.07:47:39.46#ibcon#flushed, iclass 17, count 2 2006.190.07:47:39.46#ibcon#about to write, iclass 17, count 2 2006.190.07:47:39.46#ibcon#wrote, iclass 17, count 2 2006.190.07:47:39.46#ibcon#about to read 3, iclass 17, count 2 2006.190.07:47:39.49#ibcon#read 3, iclass 17, count 2 2006.190.07:47:39.49#ibcon#about to read 4, iclass 17, count 2 2006.190.07:47:39.49#ibcon#read 4, iclass 17, count 2 2006.190.07:47:39.49#ibcon#about to read 5, iclass 17, count 2 2006.190.07:47:39.49#ibcon#read 5, iclass 17, count 2 2006.190.07:47:39.49#ibcon#about to read 6, iclass 17, count 2 2006.190.07:47:39.49#ibcon#read 6, iclass 17, count 2 2006.190.07:47:39.49#ibcon#end of sib2, iclass 17, count 2 2006.190.07:47:39.49#ibcon#*after write, iclass 17, count 2 2006.190.07:47:39.49#ibcon#*before return 0, iclass 17, count 2 2006.190.07:47:39.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:39.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:39.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.07:47:39.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:39.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:39.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:39.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:39.61#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:47:39.61#ibcon#first serial, iclass 17, count 0 2006.190.07:47:39.61#ibcon#enter sib2, iclass 17, count 0 2006.190.07:47:39.61#ibcon#flushed, iclass 17, count 0 2006.190.07:47:39.61#ibcon#about to write, iclass 17, count 0 2006.190.07:47:39.61#ibcon#wrote, iclass 17, count 0 2006.190.07:47:39.61#ibcon#about to read 3, iclass 17, count 0 2006.190.07:47:39.63#ibcon#read 3, iclass 17, count 0 2006.190.07:47:39.63#ibcon#about to read 4, iclass 17, count 0 2006.190.07:47:39.63#ibcon#read 4, iclass 17, count 0 2006.190.07:47:39.63#ibcon#about to read 5, iclass 17, count 0 2006.190.07:47:39.63#ibcon#read 5, iclass 17, count 0 2006.190.07:47:39.63#ibcon#about to read 6, iclass 17, count 0 2006.190.07:47:39.63#ibcon#read 6, iclass 17, count 0 2006.190.07:47:39.63#ibcon#end of sib2, iclass 17, count 0 2006.190.07:47:39.63#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:47:39.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:47:39.63#ibcon#[25=USB\r\n] 2006.190.07:47:39.63#ibcon#*before write, iclass 17, count 0 2006.190.07:47:39.63#ibcon#enter sib2, iclass 17, count 0 2006.190.07:47:39.63#ibcon#flushed, iclass 17, count 0 2006.190.07:47:39.63#ibcon#about to write, iclass 17, count 0 2006.190.07:47:39.63#ibcon#wrote, iclass 17, count 0 2006.190.07:47:39.63#ibcon#about to read 3, iclass 17, count 0 2006.190.07:47:39.66#ibcon#read 3, iclass 17, count 0 2006.190.07:47:39.66#ibcon#about to read 4, iclass 17, count 0 2006.190.07:47:39.66#ibcon#read 4, iclass 17, count 0 2006.190.07:47:39.66#ibcon#about to read 5, iclass 17, count 0 2006.190.07:47:39.66#ibcon#read 5, iclass 17, count 0 2006.190.07:47:39.66#ibcon#about to read 6, iclass 17, count 0 2006.190.07:47:39.66#ibcon#read 6, iclass 17, count 0 2006.190.07:47:39.66#ibcon#end of sib2, iclass 17, count 0 2006.190.07:47:39.66#ibcon#*after write, iclass 17, count 0 2006.190.07:47:39.66#ibcon#*before return 0, iclass 17, count 0 2006.190.07:47:39.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:39.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:39.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:47:39.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:47:39.66$vc4f8/valo=6,772.99 2006.190.07:47:39.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:47:39.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:47:39.66#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:39.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:39.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:39.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:39.66#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:47:39.66#ibcon#first serial, iclass 19, count 0 2006.190.07:47:39.66#ibcon#enter sib2, iclass 19, count 0 2006.190.07:47:39.66#ibcon#flushed, iclass 19, count 0 2006.190.07:47:39.66#ibcon#about to write, iclass 19, count 0 2006.190.07:47:39.66#ibcon#wrote, iclass 19, count 0 2006.190.07:47:39.66#ibcon#about to read 3, iclass 19, count 0 2006.190.07:47:39.68#ibcon#read 3, iclass 19, count 0 2006.190.07:47:39.68#ibcon#about to read 4, iclass 19, count 0 2006.190.07:47:39.68#ibcon#read 4, iclass 19, count 0 2006.190.07:47:39.68#ibcon#about to read 5, iclass 19, count 0 2006.190.07:47:39.68#ibcon#read 5, iclass 19, count 0 2006.190.07:47:39.68#ibcon#about to read 6, iclass 19, count 0 2006.190.07:47:39.68#ibcon#read 6, iclass 19, count 0 2006.190.07:47:39.68#ibcon#end of sib2, iclass 19, count 0 2006.190.07:47:39.68#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:47:39.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:47:39.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:47:39.68#ibcon#*before write, iclass 19, count 0 2006.190.07:47:39.68#ibcon#enter sib2, iclass 19, count 0 2006.190.07:47:39.68#ibcon#flushed, iclass 19, count 0 2006.190.07:47:39.68#ibcon#about to write, iclass 19, count 0 2006.190.07:47:39.68#ibcon#wrote, iclass 19, count 0 2006.190.07:47:39.68#ibcon#about to read 3, iclass 19, count 0 2006.190.07:47:39.72#ibcon#read 3, iclass 19, count 0 2006.190.07:47:39.72#ibcon#about to read 4, iclass 19, count 0 2006.190.07:47:39.72#ibcon#read 4, iclass 19, count 0 2006.190.07:47:39.72#ibcon#about to read 5, iclass 19, count 0 2006.190.07:47:39.72#ibcon#read 5, iclass 19, count 0 2006.190.07:47:39.72#ibcon#about to read 6, iclass 19, count 0 2006.190.07:47:39.72#ibcon#read 6, iclass 19, count 0 2006.190.07:47:39.72#ibcon#end of sib2, iclass 19, count 0 2006.190.07:47:39.72#ibcon#*after write, iclass 19, count 0 2006.190.07:47:39.72#ibcon#*before return 0, iclass 19, count 0 2006.190.07:47:39.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:39.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:39.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:47:39.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:47:39.72$vc4f8/va=6,6 2006.190.07:47:39.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.07:47:39.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.07:47:39.72#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:39.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:47:39.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:47:39.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:47:39.78#ibcon#enter wrdev, iclass 21, count 2 2006.190.07:47:39.78#ibcon#first serial, iclass 21, count 2 2006.190.07:47:39.78#ibcon#enter sib2, iclass 21, count 2 2006.190.07:47:39.78#ibcon#flushed, iclass 21, count 2 2006.190.07:47:39.78#ibcon#about to write, iclass 21, count 2 2006.190.07:47:39.78#ibcon#wrote, iclass 21, count 2 2006.190.07:47:39.78#ibcon#about to read 3, iclass 21, count 2 2006.190.07:47:39.80#ibcon#read 3, iclass 21, count 2 2006.190.07:47:39.80#ibcon#about to read 4, iclass 21, count 2 2006.190.07:47:39.80#ibcon#read 4, iclass 21, count 2 2006.190.07:47:39.80#ibcon#about to read 5, iclass 21, count 2 2006.190.07:47:39.80#ibcon#read 5, iclass 21, count 2 2006.190.07:47:39.80#ibcon#about to read 6, iclass 21, count 2 2006.190.07:47:39.80#ibcon#read 6, iclass 21, count 2 2006.190.07:47:39.80#ibcon#end of sib2, iclass 21, count 2 2006.190.07:47:39.80#ibcon#*mode == 0, iclass 21, count 2 2006.190.07:47:39.80#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.07:47:39.80#ibcon#[25=AT06-06\r\n] 2006.190.07:47:39.80#ibcon#*before write, iclass 21, count 2 2006.190.07:47:39.80#ibcon#enter sib2, iclass 21, count 2 2006.190.07:47:39.80#ibcon#flushed, iclass 21, count 2 2006.190.07:47:39.80#ibcon#about to write, iclass 21, count 2 2006.190.07:47:39.80#ibcon#wrote, iclass 21, count 2 2006.190.07:47:39.80#ibcon#about to read 3, iclass 21, count 2 2006.190.07:47:39.83#ibcon#read 3, iclass 21, count 2 2006.190.07:47:39.83#ibcon#about to read 4, iclass 21, count 2 2006.190.07:47:39.83#ibcon#read 4, iclass 21, count 2 2006.190.07:47:39.83#ibcon#about to read 5, iclass 21, count 2 2006.190.07:47:39.83#ibcon#read 5, iclass 21, count 2 2006.190.07:47:39.83#ibcon#about to read 6, iclass 21, count 2 2006.190.07:47:39.83#ibcon#read 6, iclass 21, count 2 2006.190.07:47:39.83#ibcon#end of sib2, iclass 21, count 2 2006.190.07:47:39.83#ibcon#*after write, iclass 21, count 2 2006.190.07:47:39.83#ibcon#*before return 0, iclass 21, count 2 2006.190.07:47:39.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:47:39.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:47:39.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.07:47:39.83#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:39.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:47:39.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:47:39.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:47:39.95#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:47:39.95#ibcon#first serial, iclass 21, count 0 2006.190.07:47:39.95#ibcon#enter sib2, iclass 21, count 0 2006.190.07:47:39.95#ibcon#flushed, iclass 21, count 0 2006.190.07:47:39.95#ibcon#about to write, iclass 21, count 0 2006.190.07:47:39.95#ibcon#wrote, iclass 21, count 0 2006.190.07:47:39.95#ibcon#about to read 3, iclass 21, count 0 2006.190.07:47:39.97#ibcon#read 3, iclass 21, count 0 2006.190.07:47:39.97#ibcon#about to read 4, iclass 21, count 0 2006.190.07:47:39.97#ibcon#read 4, iclass 21, count 0 2006.190.07:47:39.97#ibcon#about to read 5, iclass 21, count 0 2006.190.07:47:39.97#ibcon#read 5, iclass 21, count 0 2006.190.07:47:39.97#ibcon#about to read 6, iclass 21, count 0 2006.190.07:47:39.97#ibcon#read 6, iclass 21, count 0 2006.190.07:47:39.97#ibcon#end of sib2, iclass 21, count 0 2006.190.07:47:39.97#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:47:39.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:47:39.97#ibcon#[25=USB\r\n] 2006.190.07:47:39.97#ibcon#*before write, iclass 21, count 0 2006.190.07:47:39.97#ibcon#enter sib2, iclass 21, count 0 2006.190.07:47:39.97#ibcon#flushed, iclass 21, count 0 2006.190.07:47:39.97#ibcon#about to write, iclass 21, count 0 2006.190.07:47:39.97#ibcon#wrote, iclass 21, count 0 2006.190.07:47:39.97#ibcon#about to read 3, iclass 21, count 0 2006.190.07:47:40.00#ibcon#read 3, iclass 21, count 0 2006.190.07:47:40.00#ibcon#about to read 4, iclass 21, count 0 2006.190.07:47:40.00#ibcon#read 4, iclass 21, count 0 2006.190.07:47:40.00#ibcon#about to read 5, iclass 21, count 0 2006.190.07:47:40.00#ibcon#read 5, iclass 21, count 0 2006.190.07:47:40.00#ibcon#about to read 6, iclass 21, count 0 2006.190.07:47:40.00#ibcon#read 6, iclass 21, count 0 2006.190.07:47:40.00#ibcon#end of sib2, iclass 21, count 0 2006.190.07:47:40.00#ibcon#*after write, iclass 21, count 0 2006.190.07:47:40.00#ibcon#*before return 0, iclass 21, count 0 2006.190.07:47:40.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:47:40.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:47:40.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:47:40.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:47:40.00$vc4f8/valo=7,832.99 2006.190.07:47:40.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.07:47:40.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.07:47:40.00#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:40.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:47:40.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:47:40.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:47:40.00#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:47:40.00#ibcon#first serial, iclass 23, count 0 2006.190.07:47:40.00#ibcon#enter sib2, iclass 23, count 0 2006.190.07:47:40.00#ibcon#flushed, iclass 23, count 0 2006.190.07:47:40.00#ibcon#about to write, iclass 23, count 0 2006.190.07:47:40.00#ibcon#wrote, iclass 23, count 0 2006.190.07:47:40.00#ibcon#about to read 3, iclass 23, count 0 2006.190.07:47:40.02#ibcon#read 3, iclass 23, count 0 2006.190.07:47:40.02#ibcon#about to read 4, iclass 23, count 0 2006.190.07:47:40.02#ibcon#read 4, iclass 23, count 0 2006.190.07:47:40.02#ibcon#about to read 5, iclass 23, count 0 2006.190.07:47:40.02#ibcon#read 5, iclass 23, count 0 2006.190.07:47:40.02#ibcon#about to read 6, iclass 23, count 0 2006.190.07:47:40.02#ibcon#read 6, iclass 23, count 0 2006.190.07:47:40.02#ibcon#end of sib2, iclass 23, count 0 2006.190.07:47:40.02#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:47:40.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:47:40.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:47:40.02#ibcon#*before write, iclass 23, count 0 2006.190.07:47:40.02#ibcon#enter sib2, iclass 23, count 0 2006.190.07:47:40.02#ibcon#flushed, iclass 23, count 0 2006.190.07:47:40.02#ibcon#about to write, iclass 23, count 0 2006.190.07:47:40.02#ibcon#wrote, iclass 23, count 0 2006.190.07:47:40.02#ibcon#about to read 3, iclass 23, count 0 2006.190.07:47:40.06#ibcon#read 3, iclass 23, count 0 2006.190.07:47:40.06#ibcon#about to read 4, iclass 23, count 0 2006.190.07:47:40.06#ibcon#read 4, iclass 23, count 0 2006.190.07:47:40.06#ibcon#about to read 5, iclass 23, count 0 2006.190.07:47:40.06#ibcon#read 5, iclass 23, count 0 2006.190.07:47:40.06#ibcon#about to read 6, iclass 23, count 0 2006.190.07:47:40.06#ibcon#read 6, iclass 23, count 0 2006.190.07:47:40.06#ibcon#end of sib2, iclass 23, count 0 2006.190.07:47:40.06#ibcon#*after write, iclass 23, count 0 2006.190.07:47:40.06#ibcon#*before return 0, iclass 23, count 0 2006.190.07:47:40.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:47:40.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:47:40.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:47:40.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:47:40.06$vc4f8/va=7,6 2006.190.07:47:40.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.07:47:40.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.07:47:40.06#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:40.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:47:40.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:47:40.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:47:40.12#ibcon#enter wrdev, iclass 25, count 2 2006.190.07:47:40.12#ibcon#first serial, iclass 25, count 2 2006.190.07:47:40.12#ibcon#enter sib2, iclass 25, count 2 2006.190.07:47:40.12#ibcon#flushed, iclass 25, count 2 2006.190.07:47:40.12#ibcon#about to write, iclass 25, count 2 2006.190.07:47:40.12#ibcon#wrote, iclass 25, count 2 2006.190.07:47:40.12#ibcon#about to read 3, iclass 25, count 2 2006.190.07:47:40.14#ibcon#read 3, iclass 25, count 2 2006.190.07:47:40.14#ibcon#about to read 4, iclass 25, count 2 2006.190.07:47:40.14#ibcon#read 4, iclass 25, count 2 2006.190.07:47:40.14#ibcon#about to read 5, iclass 25, count 2 2006.190.07:47:40.14#ibcon#read 5, iclass 25, count 2 2006.190.07:47:40.14#ibcon#about to read 6, iclass 25, count 2 2006.190.07:47:40.14#ibcon#read 6, iclass 25, count 2 2006.190.07:47:40.14#ibcon#end of sib2, iclass 25, count 2 2006.190.07:47:40.14#ibcon#*mode == 0, iclass 25, count 2 2006.190.07:47:40.14#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.07:47:40.14#ibcon#[25=AT07-06\r\n] 2006.190.07:47:40.14#ibcon#*before write, iclass 25, count 2 2006.190.07:47:40.14#ibcon#enter sib2, iclass 25, count 2 2006.190.07:47:40.14#ibcon#flushed, iclass 25, count 2 2006.190.07:47:40.14#ibcon#about to write, iclass 25, count 2 2006.190.07:47:40.14#ibcon#wrote, iclass 25, count 2 2006.190.07:47:40.14#ibcon#about to read 3, iclass 25, count 2 2006.190.07:47:40.17#ibcon#read 3, iclass 25, count 2 2006.190.07:47:40.17#ibcon#about to read 4, iclass 25, count 2 2006.190.07:47:40.17#ibcon#read 4, iclass 25, count 2 2006.190.07:47:40.17#ibcon#about to read 5, iclass 25, count 2 2006.190.07:47:40.17#ibcon#read 5, iclass 25, count 2 2006.190.07:47:40.17#ibcon#about to read 6, iclass 25, count 2 2006.190.07:47:40.17#ibcon#read 6, iclass 25, count 2 2006.190.07:47:40.17#ibcon#end of sib2, iclass 25, count 2 2006.190.07:47:40.17#ibcon#*after write, iclass 25, count 2 2006.190.07:47:40.17#ibcon#*before return 0, iclass 25, count 2 2006.190.07:47:40.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:47:40.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:47:40.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.07:47:40.17#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:40.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:47:40.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:47:40.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:47:40.29#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:47:40.29#ibcon#first serial, iclass 25, count 0 2006.190.07:47:40.29#ibcon#enter sib2, iclass 25, count 0 2006.190.07:47:40.29#ibcon#flushed, iclass 25, count 0 2006.190.07:47:40.29#ibcon#about to write, iclass 25, count 0 2006.190.07:47:40.29#ibcon#wrote, iclass 25, count 0 2006.190.07:47:40.29#ibcon#about to read 3, iclass 25, count 0 2006.190.07:47:40.31#ibcon#read 3, iclass 25, count 0 2006.190.07:47:40.31#ibcon#about to read 4, iclass 25, count 0 2006.190.07:47:40.31#ibcon#read 4, iclass 25, count 0 2006.190.07:47:40.31#ibcon#about to read 5, iclass 25, count 0 2006.190.07:47:40.31#ibcon#read 5, iclass 25, count 0 2006.190.07:47:40.31#ibcon#about to read 6, iclass 25, count 0 2006.190.07:47:40.31#ibcon#read 6, iclass 25, count 0 2006.190.07:47:40.31#ibcon#end of sib2, iclass 25, count 0 2006.190.07:47:40.31#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:47:40.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:47:40.31#ibcon#[25=USB\r\n] 2006.190.07:47:40.31#ibcon#*before write, iclass 25, count 0 2006.190.07:47:40.31#ibcon#enter sib2, iclass 25, count 0 2006.190.07:47:40.31#ibcon#flushed, iclass 25, count 0 2006.190.07:47:40.31#ibcon#about to write, iclass 25, count 0 2006.190.07:47:40.31#ibcon#wrote, iclass 25, count 0 2006.190.07:47:40.31#ibcon#about to read 3, iclass 25, count 0 2006.190.07:47:40.34#ibcon#read 3, iclass 25, count 0 2006.190.07:47:40.34#ibcon#about to read 4, iclass 25, count 0 2006.190.07:47:40.34#ibcon#read 4, iclass 25, count 0 2006.190.07:47:40.34#ibcon#about to read 5, iclass 25, count 0 2006.190.07:47:40.34#ibcon#read 5, iclass 25, count 0 2006.190.07:47:40.34#ibcon#about to read 6, iclass 25, count 0 2006.190.07:47:40.34#ibcon#read 6, iclass 25, count 0 2006.190.07:47:40.34#ibcon#end of sib2, iclass 25, count 0 2006.190.07:47:40.34#ibcon#*after write, iclass 25, count 0 2006.190.07:47:40.34#ibcon#*before return 0, iclass 25, count 0 2006.190.07:47:40.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:47:40.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:47:40.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:47:40.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:47:40.34$vc4f8/valo=8,852.99 2006.190.07:47:40.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.07:47:40.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.07:47:40.34#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:40.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:47:40.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:47:40.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:47:40.34#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:47:40.34#ibcon#first serial, iclass 27, count 0 2006.190.07:47:40.34#ibcon#enter sib2, iclass 27, count 0 2006.190.07:47:40.34#ibcon#flushed, iclass 27, count 0 2006.190.07:47:40.34#ibcon#about to write, iclass 27, count 0 2006.190.07:47:40.34#ibcon#wrote, iclass 27, count 0 2006.190.07:47:40.34#ibcon#about to read 3, iclass 27, count 0 2006.190.07:47:40.36#ibcon#read 3, iclass 27, count 0 2006.190.07:47:40.36#ibcon#about to read 4, iclass 27, count 0 2006.190.07:47:40.36#ibcon#read 4, iclass 27, count 0 2006.190.07:47:40.36#ibcon#about to read 5, iclass 27, count 0 2006.190.07:47:40.36#ibcon#read 5, iclass 27, count 0 2006.190.07:47:40.36#ibcon#about to read 6, iclass 27, count 0 2006.190.07:47:40.36#ibcon#read 6, iclass 27, count 0 2006.190.07:47:40.36#ibcon#end of sib2, iclass 27, count 0 2006.190.07:47:40.36#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:47:40.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:47:40.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:47:40.36#ibcon#*before write, iclass 27, count 0 2006.190.07:47:40.36#ibcon#enter sib2, iclass 27, count 0 2006.190.07:47:40.36#ibcon#flushed, iclass 27, count 0 2006.190.07:47:40.36#ibcon#about to write, iclass 27, count 0 2006.190.07:47:40.36#ibcon#wrote, iclass 27, count 0 2006.190.07:47:40.36#ibcon#about to read 3, iclass 27, count 0 2006.190.07:47:40.40#ibcon#read 3, iclass 27, count 0 2006.190.07:47:40.40#ibcon#about to read 4, iclass 27, count 0 2006.190.07:47:40.40#ibcon#read 4, iclass 27, count 0 2006.190.07:47:40.40#ibcon#about to read 5, iclass 27, count 0 2006.190.07:47:40.40#ibcon#read 5, iclass 27, count 0 2006.190.07:47:40.40#ibcon#about to read 6, iclass 27, count 0 2006.190.07:47:40.40#ibcon#read 6, iclass 27, count 0 2006.190.07:47:40.40#ibcon#end of sib2, iclass 27, count 0 2006.190.07:47:40.40#ibcon#*after write, iclass 27, count 0 2006.190.07:47:40.40#ibcon#*before return 0, iclass 27, count 0 2006.190.07:47:40.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:47:40.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:47:40.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:47:40.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:47:40.40$vc4f8/va=8,6 2006.190.07:47:40.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.07:47:40.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.07:47:40.40#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:40.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:47:40.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:47:40.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:47:40.46#ibcon#enter wrdev, iclass 29, count 2 2006.190.07:47:40.46#ibcon#first serial, iclass 29, count 2 2006.190.07:47:40.46#ibcon#enter sib2, iclass 29, count 2 2006.190.07:47:40.46#ibcon#flushed, iclass 29, count 2 2006.190.07:47:40.46#ibcon#about to write, iclass 29, count 2 2006.190.07:47:40.46#ibcon#wrote, iclass 29, count 2 2006.190.07:47:40.46#ibcon#about to read 3, iclass 29, count 2 2006.190.07:47:40.48#ibcon#read 3, iclass 29, count 2 2006.190.07:47:40.48#ibcon#about to read 4, iclass 29, count 2 2006.190.07:47:40.48#ibcon#read 4, iclass 29, count 2 2006.190.07:47:40.48#ibcon#about to read 5, iclass 29, count 2 2006.190.07:47:40.48#ibcon#read 5, iclass 29, count 2 2006.190.07:47:40.48#ibcon#about to read 6, iclass 29, count 2 2006.190.07:47:40.48#ibcon#read 6, iclass 29, count 2 2006.190.07:47:40.48#ibcon#end of sib2, iclass 29, count 2 2006.190.07:47:40.48#ibcon#*mode == 0, iclass 29, count 2 2006.190.07:47:40.48#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.07:47:40.48#ibcon#[25=AT08-06\r\n] 2006.190.07:47:40.48#ibcon#*before write, iclass 29, count 2 2006.190.07:47:40.48#ibcon#enter sib2, iclass 29, count 2 2006.190.07:47:40.48#ibcon#flushed, iclass 29, count 2 2006.190.07:47:40.48#ibcon#about to write, iclass 29, count 2 2006.190.07:47:40.48#ibcon#wrote, iclass 29, count 2 2006.190.07:47:40.48#ibcon#about to read 3, iclass 29, count 2 2006.190.07:47:40.51#ibcon#read 3, iclass 29, count 2 2006.190.07:47:40.51#ibcon#about to read 4, iclass 29, count 2 2006.190.07:47:40.51#ibcon#read 4, iclass 29, count 2 2006.190.07:47:40.51#ibcon#about to read 5, iclass 29, count 2 2006.190.07:47:40.51#ibcon#read 5, iclass 29, count 2 2006.190.07:47:40.51#ibcon#about to read 6, iclass 29, count 2 2006.190.07:47:40.51#ibcon#read 6, iclass 29, count 2 2006.190.07:47:40.51#ibcon#end of sib2, iclass 29, count 2 2006.190.07:47:40.51#ibcon#*after write, iclass 29, count 2 2006.190.07:47:40.51#ibcon#*before return 0, iclass 29, count 2 2006.190.07:47:40.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:47:40.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:47:40.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.07:47:40.51#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:40.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:47:40.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:47:40.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:47:40.63#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:47:40.63#ibcon#first serial, iclass 29, count 0 2006.190.07:47:40.63#ibcon#enter sib2, iclass 29, count 0 2006.190.07:47:40.63#ibcon#flushed, iclass 29, count 0 2006.190.07:47:40.63#ibcon#about to write, iclass 29, count 0 2006.190.07:47:40.63#ibcon#wrote, iclass 29, count 0 2006.190.07:47:40.63#ibcon#about to read 3, iclass 29, count 0 2006.190.07:47:40.65#ibcon#read 3, iclass 29, count 0 2006.190.07:47:40.65#ibcon#about to read 4, iclass 29, count 0 2006.190.07:47:40.65#ibcon#read 4, iclass 29, count 0 2006.190.07:47:40.65#ibcon#about to read 5, iclass 29, count 0 2006.190.07:47:40.65#ibcon#read 5, iclass 29, count 0 2006.190.07:47:40.65#ibcon#about to read 6, iclass 29, count 0 2006.190.07:47:40.65#ibcon#read 6, iclass 29, count 0 2006.190.07:47:40.65#ibcon#end of sib2, iclass 29, count 0 2006.190.07:47:40.65#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:47:40.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:47:40.65#ibcon#[25=USB\r\n] 2006.190.07:47:40.65#ibcon#*before write, iclass 29, count 0 2006.190.07:47:40.65#ibcon#enter sib2, iclass 29, count 0 2006.190.07:47:40.65#ibcon#flushed, iclass 29, count 0 2006.190.07:47:40.65#ibcon#about to write, iclass 29, count 0 2006.190.07:47:40.65#ibcon#wrote, iclass 29, count 0 2006.190.07:47:40.65#ibcon#about to read 3, iclass 29, count 0 2006.190.07:47:40.68#ibcon#read 3, iclass 29, count 0 2006.190.07:47:40.68#ibcon#about to read 4, iclass 29, count 0 2006.190.07:47:40.68#ibcon#read 4, iclass 29, count 0 2006.190.07:47:40.68#ibcon#about to read 5, iclass 29, count 0 2006.190.07:47:40.68#ibcon#read 5, iclass 29, count 0 2006.190.07:47:40.68#ibcon#about to read 6, iclass 29, count 0 2006.190.07:47:40.68#ibcon#read 6, iclass 29, count 0 2006.190.07:47:40.68#ibcon#end of sib2, iclass 29, count 0 2006.190.07:47:40.68#ibcon#*after write, iclass 29, count 0 2006.190.07:47:40.68#ibcon#*before return 0, iclass 29, count 0 2006.190.07:47:40.68#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:47:40.68#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:47:40.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:47:40.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:47:40.68$vc4f8/vblo=1,632.99 2006.190.07:47:40.68#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.07:47:40.68#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.07:47:40.68#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:40.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:47:40.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:47:40.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:47:40.68#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:47:40.68#ibcon#first serial, iclass 31, count 0 2006.190.07:47:40.68#ibcon#enter sib2, iclass 31, count 0 2006.190.07:47:40.68#ibcon#flushed, iclass 31, count 0 2006.190.07:47:40.68#ibcon#about to write, iclass 31, count 0 2006.190.07:47:40.68#ibcon#wrote, iclass 31, count 0 2006.190.07:47:40.68#ibcon#about to read 3, iclass 31, count 0 2006.190.07:47:40.70#ibcon#read 3, iclass 31, count 0 2006.190.07:47:40.70#ibcon#about to read 4, iclass 31, count 0 2006.190.07:47:40.70#ibcon#read 4, iclass 31, count 0 2006.190.07:47:40.70#ibcon#about to read 5, iclass 31, count 0 2006.190.07:47:40.70#ibcon#read 5, iclass 31, count 0 2006.190.07:47:40.70#ibcon#about to read 6, iclass 31, count 0 2006.190.07:47:40.70#ibcon#read 6, iclass 31, count 0 2006.190.07:47:40.70#ibcon#end of sib2, iclass 31, count 0 2006.190.07:47:40.70#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:47:40.70#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:47:40.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:47:40.70#ibcon#*before write, iclass 31, count 0 2006.190.07:47:40.70#ibcon#enter sib2, iclass 31, count 0 2006.190.07:47:40.70#ibcon#flushed, iclass 31, count 0 2006.190.07:47:40.70#ibcon#about to write, iclass 31, count 0 2006.190.07:47:40.70#ibcon#wrote, iclass 31, count 0 2006.190.07:47:40.70#ibcon#about to read 3, iclass 31, count 0 2006.190.07:47:40.74#ibcon#read 3, iclass 31, count 0 2006.190.07:47:40.74#ibcon#about to read 4, iclass 31, count 0 2006.190.07:47:40.74#ibcon#read 4, iclass 31, count 0 2006.190.07:47:40.74#ibcon#about to read 5, iclass 31, count 0 2006.190.07:47:40.74#ibcon#read 5, iclass 31, count 0 2006.190.07:47:40.74#ibcon#about to read 6, iclass 31, count 0 2006.190.07:47:40.74#ibcon#read 6, iclass 31, count 0 2006.190.07:47:40.74#ibcon#end of sib2, iclass 31, count 0 2006.190.07:47:40.74#ibcon#*after write, iclass 31, count 0 2006.190.07:47:40.74#ibcon#*before return 0, iclass 31, count 0 2006.190.07:47:40.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:47:40.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:47:40.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:47:40.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:47:40.74$vc4f8/vb=1,4 2006.190.07:47:40.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.190.07:47:40.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.190.07:47:40.74#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:40.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:47:40.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:47:40.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:47:40.74#ibcon#enter wrdev, iclass 33, count 2 2006.190.07:47:40.74#ibcon#first serial, iclass 33, count 2 2006.190.07:47:40.74#ibcon#enter sib2, iclass 33, count 2 2006.190.07:47:40.74#ibcon#flushed, iclass 33, count 2 2006.190.07:47:40.74#ibcon#about to write, iclass 33, count 2 2006.190.07:47:40.74#ibcon#wrote, iclass 33, count 2 2006.190.07:47:40.74#ibcon#about to read 3, iclass 33, count 2 2006.190.07:47:40.76#ibcon#read 3, iclass 33, count 2 2006.190.07:47:40.76#ibcon#about to read 4, iclass 33, count 2 2006.190.07:47:40.76#ibcon#read 4, iclass 33, count 2 2006.190.07:47:40.76#ibcon#about to read 5, iclass 33, count 2 2006.190.07:47:40.76#ibcon#read 5, iclass 33, count 2 2006.190.07:47:40.76#ibcon#about to read 6, iclass 33, count 2 2006.190.07:47:40.76#ibcon#read 6, iclass 33, count 2 2006.190.07:47:40.76#ibcon#end of sib2, iclass 33, count 2 2006.190.07:47:40.76#ibcon#*mode == 0, iclass 33, count 2 2006.190.07:47:40.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.190.07:47:40.76#ibcon#[27=AT01-04\r\n] 2006.190.07:47:40.76#ibcon#*before write, iclass 33, count 2 2006.190.07:47:40.76#ibcon#enter sib2, iclass 33, count 2 2006.190.07:47:40.76#ibcon#flushed, iclass 33, count 2 2006.190.07:47:40.76#ibcon#about to write, iclass 33, count 2 2006.190.07:47:40.76#ibcon#wrote, iclass 33, count 2 2006.190.07:47:40.76#ibcon#about to read 3, iclass 33, count 2 2006.190.07:47:40.79#ibcon#read 3, iclass 33, count 2 2006.190.07:47:40.79#ibcon#about to read 4, iclass 33, count 2 2006.190.07:47:40.79#ibcon#read 4, iclass 33, count 2 2006.190.07:47:40.79#ibcon#about to read 5, iclass 33, count 2 2006.190.07:47:40.79#ibcon#read 5, iclass 33, count 2 2006.190.07:47:40.79#ibcon#about to read 6, iclass 33, count 2 2006.190.07:47:40.79#ibcon#read 6, iclass 33, count 2 2006.190.07:47:40.79#ibcon#end of sib2, iclass 33, count 2 2006.190.07:47:40.79#ibcon#*after write, iclass 33, count 2 2006.190.07:47:40.79#ibcon#*before return 0, iclass 33, count 2 2006.190.07:47:40.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:47:40.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:47:40.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.190.07:47:40.79#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:40.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:47:40.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:47:40.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:47:40.91#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:47:40.91#ibcon#first serial, iclass 33, count 0 2006.190.07:47:40.91#ibcon#enter sib2, iclass 33, count 0 2006.190.07:47:40.91#ibcon#flushed, iclass 33, count 0 2006.190.07:47:40.91#ibcon#about to write, iclass 33, count 0 2006.190.07:47:40.91#ibcon#wrote, iclass 33, count 0 2006.190.07:47:40.91#ibcon#about to read 3, iclass 33, count 0 2006.190.07:47:40.93#ibcon#read 3, iclass 33, count 0 2006.190.07:47:40.93#ibcon#about to read 4, iclass 33, count 0 2006.190.07:47:40.93#ibcon#read 4, iclass 33, count 0 2006.190.07:47:40.93#ibcon#about to read 5, iclass 33, count 0 2006.190.07:47:40.93#ibcon#read 5, iclass 33, count 0 2006.190.07:47:40.93#ibcon#about to read 6, iclass 33, count 0 2006.190.07:47:40.93#ibcon#read 6, iclass 33, count 0 2006.190.07:47:40.93#ibcon#end of sib2, iclass 33, count 0 2006.190.07:47:40.93#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:47:40.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:47:40.93#ibcon#[27=USB\r\n] 2006.190.07:47:40.93#ibcon#*before write, iclass 33, count 0 2006.190.07:47:40.93#ibcon#enter sib2, iclass 33, count 0 2006.190.07:47:40.93#ibcon#flushed, iclass 33, count 0 2006.190.07:47:40.93#ibcon#about to write, iclass 33, count 0 2006.190.07:47:40.93#ibcon#wrote, iclass 33, count 0 2006.190.07:47:40.93#ibcon#about to read 3, iclass 33, count 0 2006.190.07:47:40.96#ibcon#read 3, iclass 33, count 0 2006.190.07:47:40.96#ibcon#about to read 4, iclass 33, count 0 2006.190.07:47:40.96#ibcon#read 4, iclass 33, count 0 2006.190.07:47:40.96#ibcon#about to read 5, iclass 33, count 0 2006.190.07:47:40.96#ibcon#read 5, iclass 33, count 0 2006.190.07:47:40.96#ibcon#about to read 6, iclass 33, count 0 2006.190.07:47:40.96#ibcon#read 6, iclass 33, count 0 2006.190.07:47:40.96#ibcon#end of sib2, iclass 33, count 0 2006.190.07:47:40.96#ibcon#*after write, iclass 33, count 0 2006.190.07:47:40.96#ibcon#*before return 0, iclass 33, count 0 2006.190.07:47:40.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:47:40.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:47:40.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:47:40.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:47:40.96$vc4f8/vblo=2,640.99 2006.190.07:47:40.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.07:47:40.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.07:47:40.96#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:40.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:40.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:40.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:40.96#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:47:40.96#ibcon#first serial, iclass 35, count 0 2006.190.07:47:40.96#ibcon#enter sib2, iclass 35, count 0 2006.190.07:47:40.96#ibcon#flushed, iclass 35, count 0 2006.190.07:47:40.96#ibcon#about to write, iclass 35, count 0 2006.190.07:47:40.96#ibcon#wrote, iclass 35, count 0 2006.190.07:47:40.96#ibcon#about to read 3, iclass 35, count 0 2006.190.07:47:40.98#ibcon#read 3, iclass 35, count 0 2006.190.07:47:40.98#ibcon#about to read 4, iclass 35, count 0 2006.190.07:47:40.98#ibcon#read 4, iclass 35, count 0 2006.190.07:47:40.98#ibcon#about to read 5, iclass 35, count 0 2006.190.07:47:40.98#ibcon#read 5, iclass 35, count 0 2006.190.07:47:40.98#ibcon#about to read 6, iclass 35, count 0 2006.190.07:47:40.98#ibcon#read 6, iclass 35, count 0 2006.190.07:47:40.98#ibcon#end of sib2, iclass 35, count 0 2006.190.07:47:40.98#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:47:40.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:47:40.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:47:40.98#ibcon#*before write, iclass 35, count 0 2006.190.07:47:40.98#ibcon#enter sib2, iclass 35, count 0 2006.190.07:47:40.98#ibcon#flushed, iclass 35, count 0 2006.190.07:47:40.98#ibcon#about to write, iclass 35, count 0 2006.190.07:47:40.98#ibcon#wrote, iclass 35, count 0 2006.190.07:47:40.98#ibcon#about to read 3, iclass 35, count 0 2006.190.07:47:41.02#ibcon#read 3, iclass 35, count 0 2006.190.07:47:41.02#ibcon#about to read 4, iclass 35, count 0 2006.190.07:47:41.02#ibcon#read 4, iclass 35, count 0 2006.190.07:47:41.02#ibcon#about to read 5, iclass 35, count 0 2006.190.07:47:41.02#ibcon#read 5, iclass 35, count 0 2006.190.07:47:41.02#ibcon#about to read 6, iclass 35, count 0 2006.190.07:47:41.02#ibcon#read 6, iclass 35, count 0 2006.190.07:47:41.02#ibcon#end of sib2, iclass 35, count 0 2006.190.07:47:41.02#ibcon#*after write, iclass 35, count 0 2006.190.07:47:41.02#ibcon#*before return 0, iclass 35, count 0 2006.190.07:47:41.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:41.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:47:41.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:47:41.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:47:41.02$vc4f8/vb=2,4 2006.190.07:47:41.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.07:47:41.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.07:47:41.02#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:41.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:41.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:41.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:41.08#ibcon#enter wrdev, iclass 37, count 2 2006.190.07:47:41.08#ibcon#first serial, iclass 37, count 2 2006.190.07:47:41.08#ibcon#enter sib2, iclass 37, count 2 2006.190.07:47:41.08#ibcon#flushed, iclass 37, count 2 2006.190.07:47:41.08#ibcon#about to write, iclass 37, count 2 2006.190.07:47:41.08#ibcon#wrote, iclass 37, count 2 2006.190.07:47:41.08#ibcon#about to read 3, iclass 37, count 2 2006.190.07:47:41.10#ibcon#read 3, iclass 37, count 2 2006.190.07:47:41.10#ibcon#about to read 4, iclass 37, count 2 2006.190.07:47:41.10#ibcon#read 4, iclass 37, count 2 2006.190.07:47:41.10#ibcon#about to read 5, iclass 37, count 2 2006.190.07:47:41.10#ibcon#read 5, iclass 37, count 2 2006.190.07:47:41.10#ibcon#about to read 6, iclass 37, count 2 2006.190.07:47:41.10#ibcon#read 6, iclass 37, count 2 2006.190.07:47:41.10#ibcon#end of sib2, iclass 37, count 2 2006.190.07:47:41.10#ibcon#*mode == 0, iclass 37, count 2 2006.190.07:47:41.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.07:47:41.10#ibcon#[27=AT02-04\r\n] 2006.190.07:47:41.10#ibcon#*before write, iclass 37, count 2 2006.190.07:47:41.10#ibcon#enter sib2, iclass 37, count 2 2006.190.07:47:41.10#ibcon#flushed, iclass 37, count 2 2006.190.07:47:41.10#ibcon#about to write, iclass 37, count 2 2006.190.07:47:41.10#ibcon#wrote, iclass 37, count 2 2006.190.07:47:41.10#ibcon#about to read 3, iclass 37, count 2 2006.190.07:47:41.13#ibcon#read 3, iclass 37, count 2 2006.190.07:47:41.13#ibcon#about to read 4, iclass 37, count 2 2006.190.07:47:41.13#ibcon#read 4, iclass 37, count 2 2006.190.07:47:41.13#ibcon#about to read 5, iclass 37, count 2 2006.190.07:47:41.13#ibcon#read 5, iclass 37, count 2 2006.190.07:47:41.13#ibcon#about to read 6, iclass 37, count 2 2006.190.07:47:41.13#ibcon#read 6, iclass 37, count 2 2006.190.07:47:41.13#ibcon#end of sib2, iclass 37, count 2 2006.190.07:47:41.13#ibcon#*after write, iclass 37, count 2 2006.190.07:47:41.13#ibcon#*before return 0, iclass 37, count 2 2006.190.07:47:41.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:41.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:47:41.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.07:47:41.13#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:41.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:41.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:41.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:41.25#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:47:41.25#ibcon#first serial, iclass 37, count 0 2006.190.07:47:41.25#ibcon#enter sib2, iclass 37, count 0 2006.190.07:47:41.25#ibcon#flushed, iclass 37, count 0 2006.190.07:47:41.25#ibcon#about to write, iclass 37, count 0 2006.190.07:47:41.25#ibcon#wrote, iclass 37, count 0 2006.190.07:47:41.25#ibcon#about to read 3, iclass 37, count 0 2006.190.07:47:41.27#ibcon#read 3, iclass 37, count 0 2006.190.07:47:41.27#ibcon#about to read 4, iclass 37, count 0 2006.190.07:47:41.27#ibcon#read 4, iclass 37, count 0 2006.190.07:47:41.27#ibcon#about to read 5, iclass 37, count 0 2006.190.07:47:41.27#ibcon#read 5, iclass 37, count 0 2006.190.07:47:41.27#ibcon#about to read 6, iclass 37, count 0 2006.190.07:47:41.27#ibcon#read 6, iclass 37, count 0 2006.190.07:47:41.27#ibcon#end of sib2, iclass 37, count 0 2006.190.07:47:41.27#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:47:41.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:47:41.27#ibcon#[27=USB\r\n] 2006.190.07:47:41.27#ibcon#*before write, iclass 37, count 0 2006.190.07:47:41.27#ibcon#enter sib2, iclass 37, count 0 2006.190.07:47:41.27#ibcon#flushed, iclass 37, count 0 2006.190.07:47:41.27#ibcon#about to write, iclass 37, count 0 2006.190.07:47:41.27#ibcon#wrote, iclass 37, count 0 2006.190.07:47:41.27#ibcon#about to read 3, iclass 37, count 0 2006.190.07:47:41.30#ibcon#read 3, iclass 37, count 0 2006.190.07:47:41.30#ibcon#about to read 4, iclass 37, count 0 2006.190.07:47:41.30#ibcon#read 4, iclass 37, count 0 2006.190.07:47:41.30#ibcon#about to read 5, iclass 37, count 0 2006.190.07:47:41.30#ibcon#read 5, iclass 37, count 0 2006.190.07:47:41.30#ibcon#about to read 6, iclass 37, count 0 2006.190.07:47:41.30#ibcon#read 6, iclass 37, count 0 2006.190.07:47:41.30#ibcon#end of sib2, iclass 37, count 0 2006.190.07:47:41.30#ibcon#*after write, iclass 37, count 0 2006.190.07:47:41.30#ibcon#*before return 0, iclass 37, count 0 2006.190.07:47:41.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:41.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:47:41.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:47:41.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:47:41.30$vc4f8/vblo=3,656.99 2006.190.07:47:41.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.07:47:41.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.07:47:41.30#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:41.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:41.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:41.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:41.30#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:47:41.30#ibcon#first serial, iclass 39, count 0 2006.190.07:47:41.30#ibcon#enter sib2, iclass 39, count 0 2006.190.07:47:41.30#ibcon#flushed, iclass 39, count 0 2006.190.07:47:41.30#ibcon#about to write, iclass 39, count 0 2006.190.07:47:41.30#ibcon#wrote, iclass 39, count 0 2006.190.07:47:41.30#ibcon#about to read 3, iclass 39, count 0 2006.190.07:47:41.32#ibcon#read 3, iclass 39, count 0 2006.190.07:47:41.32#ibcon#about to read 4, iclass 39, count 0 2006.190.07:47:41.32#ibcon#read 4, iclass 39, count 0 2006.190.07:47:41.32#ibcon#about to read 5, iclass 39, count 0 2006.190.07:47:41.32#ibcon#read 5, iclass 39, count 0 2006.190.07:47:41.32#ibcon#about to read 6, iclass 39, count 0 2006.190.07:47:41.32#ibcon#read 6, iclass 39, count 0 2006.190.07:47:41.32#ibcon#end of sib2, iclass 39, count 0 2006.190.07:47:41.32#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:47:41.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:47:41.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:47:41.32#ibcon#*before write, iclass 39, count 0 2006.190.07:47:41.32#ibcon#enter sib2, iclass 39, count 0 2006.190.07:47:41.32#ibcon#flushed, iclass 39, count 0 2006.190.07:47:41.32#ibcon#about to write, iclass 39, count 0 2006.190.07:47:41.32#ibcon#wrote, iclass 39, count 0 2006.190.07:47:41.32#ibcon#about to read 3, iclass 39, count 0 2006.190.07:47:41.36#ibcon#read 3, iclass 39, count 0 2006.190.07:47:41.36#ibcon#about to read 4, iclass 39, count 0 2006.190.07:47:41.36#ibcon#read 4, iclass 39, count 0 2006.190.07:47:41.36#ibcon#about to read 5, iclass 39, count 0 2006.190.07:47:41.36#ibcon#read 5, iclass 39, count 0 2006.190.07:47:41.36#ibcon#about to read 6, iclass 39, count 0 2006.190.07:47:41.36#ibcon#read 6, iclass 39, count 0 2006.190.07:47:41.36#ibcon#end of sib2, iclass 39, count 0 2006.190.07:47:41.36#ibcon#*after write, iclass 39, count 0 2006.190.07:47:41.36#ibcon#*before return 0, iclass 39, count 0 2006.190.07:47:41.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:41.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:47:41.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:47:41.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:47:41.36$vc4f8/vb=3,4 2006.190.07:47:41.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.07:47:41.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.07:47:41.36#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:41.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:41.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:41.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:41.42#ibcon#enter wrdev, iclass 3, count 2 2006.190.07:47:41.42#ibcon#first serial, iclass 3, count 2 2006.190.07:47:41.42#ibcon#enter sib2, iclass 3, count 2 2006.190.07:47:41.42#ibcon#flushed, iclass 3, count 2 2006.190.07:47:41.42#ibcon#about to write, iclass 3, count 2 2006.190.07:47:41.42#ibcon#wrote, iclass 3, count 2 2006.190.07:47:41.42#ibcon#about to read 3, iclass 3, count 2 2006.190.07:47:41.44#ibcon#read 3, iclass 3, count 2 2006.190.07:47:41.44#ibcon#about to read 4, iclass 3, count 2 2006.190.07:47:41.44#ibcon#read 4, iclass 3, count 2 2006.190.07:47:41.44#ibcon#about to read 5, iclass 3, count 2 2006.190.07:47:41.44#ibcon#read 5, iclass 3, count 2 2006.190.07:47:41.44#ibcon#about to read 6, iclass 3, count 2 2006.190.07:47:41.44#ibcon#read 6, iclass 3, count 2 2006.190.07:47:41.44#ibcon#end of sib2, iclass 3, count 2 2006.190.07:47:41.44#ibcon#*mode == 0, iclass 3, count 2 2006.190.07:47:41.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.07:47:41.44#ibcon#[27=AT03-04\r\n] 2006.190.07:47:41.44#ibcon#*before write, iclass 3, count 2 2006.190.07:47:41.44#ibcon#enter sib2, iclass 3, count 2 2006.190.07:47:41.44#ibcon#flushed, iclass 3, count 2 2006.190.07:47:41.44#ibcon#about to write, iclass 3, count 2 2006.190.07:47:41.44#ibcon#wrote, iclass 3, count 2 2006.190.07:47:41.44#ibcon#about to read 3, iclass 3, count 2 2006.190.07:47:41.47#ibcon#read 3, iclass 3, count 2 2006.190.07:47:41.47#ibcon#about to read 4, iclass 3, count 2 2006.190.07:47:41.47#ibcon#read 4, iclass 3, count 2 2006.190.07:47:41.47#ibcon#about to read 5, iclass 3, count 2 2006.190.07:47:41.47#ibcon#read 5, iclass 3, count 2 2006.190.07:47:41.47#ibcon#about to read 6, iclass 3, count 2 2006.190.07:47:41.47#ibcon#read 6, iclass 3, count 2 2006.190.07:47:41.47#ibcon#end of sib2, iclass 3, count 2 2006.190.07:47:41.47#ibcon#*after write, iclass 3, count 2 2006.190.07:47:41.47#ibcon#*before return 0, iclass 3, count 2 2006.190.07:47:41.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:41.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:47:41.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.07:47:41.47#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:41.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:41.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:41.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:41.59#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:47:41.59#ibcon#first serial, iclass 3, count 0 2006.190.07:47:41.59#ibcon#enter sib2, iclass 3, count 0 2006.190.07:47:41.59#ibcon#flushed, iclass 3, count 0 2006.190.07:47:41.59#ibcon#about to write, iclass 3, count 0 2006.190.07:47:41.59#ibcon#wrote, iclass 3, count 0 2006.190.07:47:41.59#ibcon#about to read 3, iclass 3, count 0 2006.190.07:47:41.61#ibcon#read 3, iclass 3, count 0 2006.190.07:47:41.61#ibcon#about to read 4, iclass 3, count 0 2006.190.07:47:41.61#ibcon#read 4, iclass 3, count 0 2006.190.07:47:41.61#ibcon#about to read 5, iclass 3, count 0 2006.190.07:47:41.61#ibcon#read 5, iclass 3, count 0 2006.190.07:47:41.61#ibcon#about to read 6, iclass 3, count 0 2006.190.07:47:41.61#ibcon#read 6, iclass 3, count 0 2006.190.07:47:41.61#ibcon#end of sib2, iclass 3, count 0 2006.190.07:47:41.61#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:47:41.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:47:41.61#ibcon#[27=USB\r\n] 2006.190.07:47:41.61#ibcon#*before write, iclass 3, count 0 2006.190.07:47:41.61#ibcon#enter sib2, iclass 3, count 0 2006.190.07:47:41.61#ibcon#flushed, iclass 3, count 0 2006.190.07:47:41.61#ibcon#about to write, iclass 3, count 0 2006.190.07:47:41.61#ibcon#wrote, iclass 3, count 0 2006.190.07:47:41.61#ibcon#about to read 3, iclass 3, count 0 2006.190.07:47:41.64#ibcon#read 3, iclass 3, count 0 2006.190.07:47:41.64#ibcon#about to read 4, iclass 3, count 0 2006.190.07:47:41.64#ibcon#read 4, iclass 3, count 0 2006.190.07:47:41.64#ibcon#about to read 5, iclass 3, count 0 2006.190.07:47:41.64#ibcon#read 5, iclass 3, count 0 2006.190.07:47:41.64#ibcon#about to read 6, iclass 3, count 0 2006.190.07:47:41.64#ibcon#read 6, iclass 3, count 0 2006.190.07:47:41.64#ibcon#end of sib2, iclass 3, count 0 2006.190.07:47:41.64#ibcon#*after write, iclass 3, count 0 2006.190.07:47:41.64#ibcon#*before return 0, iclass 3, count 0 2006.190.07:47:41.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:41.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:47:41.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:47:41.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:47:41.64$vc4f8/vblo=4,712.99 2006.190.07:47:41.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.07:47:41.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.07:47:41.64#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:41.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:41.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:41.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:41.64#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:47:41.64#ibcon#first serial, iclass 5, count 0 2006.190.07:47:41.64#ibcon#enter sib2, iclass 5, count 0 2006.190.07:47:41.64#ibcon#flushed, iclass 5, count 0 2006.190.07:47:41.64#ibcon#about to write, iclass 5, count 0 2006.190.07:47:41.64#ibcon#wrote, iclass 5, count 0 2006.190.07:47:41.64#ibcon#about to read 3, iclass 5, count 0 2006.190.07:47:41.66#ibcon#read 3, iclass 5, count 0 2006.190.07:47:41.66#ibcon#about to read 4, iclass 5, count 0 2006.190.07:47:41.66#ibcon#read 4, iclass 5, count 0 2006.190.07:47:41.66#ibcon#about to read 5, iclass 5, count 0 2006.190.07:47:41.66#ibcon#read 5, iclass 5, count 0 2006.190.07:47:41.66#ibcon#about to read 6, iclass 5, count 0 2006.190.07:47:41.66#ibcon#read 6, iclass 5, count 0 2006.190.07:47:41.66#ibcon#end of sib2, iclass 5, count 0 2006.190.07:47:41.66#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:47:41.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:47:41.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:47:41.66#ibcon#*before write, iclass 5, count 0 2006.190.07:47:41.66#ibcon#enter sib2, iclass 5, count 0 2006.190.07:47:41.66#ibcon#flushed, iclass 5, count 0 2006.190.07:47:41.66#ibcon#about to write, iclass 5, count 0 2006.190.07:47:41.66#ibcon#wrote, iclass 5, count 0 2006.190.07:47:41.66#ibcon#about to read 3, iclass 5, count 0 2006.190.07:47:41.70#ibcon#read 3, iclass 5, count 0 2006.190.07:47:41.70#ibcon#about to read 4, iclass 5, count 0 2006.190.07:47:41.70#ibcon#read 4, iclass 5, count 0 2006.190.07:47:41.70#ibcon#about to read 5, iclass 5, count 0 2006.190.07:47:41.70#ibcon#read 5, iclass 5, count 0 2006.190.07:47:41.70#ibcon#about to read 6, iclass 5, count 0 2006.190.07:47:41.70#ibcon#read 6, iclass 5, count 0 2006.190.07:47:41.70#ibcon#end of sib2, iclass 5, count 0 2006.190.07:47:41.70#ibcon#*after write, iclass 5, count 0 2006.190.07:47:41.70#ibcon#*before return 0, iclass 5, count 0 2006.190.07:47:41.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:41.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:47:41.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:47:41.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:47:41.70$vc4f8/vb=4,4 2006.190.07:47:41.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.07:47:41.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.07:47:41.70#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:41.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:41.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:41.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:41.76#ibcon#enter wrdev, iclass 7, count 2 2006.190.07:47:41.76#ibcon#first serial, iclass 7, count 2 2006.190.07:47:41.76#ibcon#enter sib2, iclass 7, count 2 2006.190.07:47:41.76#ibcon#flushed, iclass 7, count 2 2006.190.07:47:41.76#ibcon#about to write, iclass 7, count 2 2006.190.07:47:41.76#ibcon#wrote, iclass 7, count 2 2006.190.07:47:41.76#ibcon#about to read 3, iclass 7, count 2 2006.190.07:47:41.78#ibcon#read 3, iclass 7, count 2 2006.190.07:47:41.78#ibcon#about to read 4, iclass 7, count 2 2006.190.07:47:41.78#ibcon#read 4, iclass 7, count 2 2006.190.07:47:41.78#ibcon#about to read 5, iclass 7, count 2 2006.190.07:47:41.78#ibcon#read 5, iclass 7, count 2 2006.190.07:47:41.78#ibcon#about to read 6, iclass 7, count 2 2006.190.07:47:41.78#ibcon#read 6, iclass 7, count 2 2006.190.07:47:41.78#ibcon#end of sib2, iclass 7, count 2 2006.190.07:47:41.78#ibcon#*mode == 0, iclass 7, count 2 2006.190.07:47:41.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.07:47:41.78#ibcon#[27=AT04-04\r\n] 2006.190.07:47:41.78#ibcon#*before write, iclass 7, count 2 2006.190.07:47:41.78#ibcon#enter sib2, iclass 7, count 2 2006.190.07:47:41.78#ibcon#flushed, iclass 7, count 2 2006.190.07:47:41.78#ibcon#about to write, iclass 7, count 2 2006.190.07:47:41.78#ibcon#wrote, iclass 7, count 2 2006.190.07:47:41.78#ibcon#about to read 3, iclass 7, count 2 2006.190.07:47:41.81#ibcon#read 3, iclass 7, count 2 2006.190.07:47:41.81#ibcon#about to read 4, iclass 7, count 2 2006.190.07:47:41.81#ibcon#read 4, iclass 7, count 2 2006.190.07:47:41.81#ibcon#about to read 5, iclass 7, count 2 2006.190.07:47:41.81#ibcon#read 5, iclass 7, count 2 2006.190.07:47:41.81#ibcon#about to read 6, iclass 7, count 2 2006.190.07:47:41.81#ibcon#read 6, iclass 7, count 2 2006.190.07:47:41.81#ibcon#end of sib2, iclass 7, count 2 2006.190.07:47:41.81#ibcon#*after write, iclass 7, count 2 2006.190.07:47:41.81#ibcon#*before return 0, iclass 7, count 2 2006.190.07:47:41.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:41.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:47:41.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.07:47:41.81#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:41.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:41.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:41.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:41.93#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:47:41.93#ibcon#first serial, iclass 7, count 0 2006.190.07:47:41.93#ibcon#enter sib2, iclass 7, count 0 2006.190.07:47:41.93#ibcon#flushed, iclass 7, count 0 2006.190.07:47:41.93#ibcon#about to write, iclass 7, count 0 2006.190.07:47:41.93#ibcon#wrote, iclass 7, count 0 2006.190.07:47:41.93#ibcon#about to read 3, iclass 7, count 0 2006.190.07:47:41.95#ibcon#read 3, iclass 7, count 0 2006.190.07:47:41.95#ibcon#about to read 4, iclass 7, count 0 2006.190.07:47:41.95#ibcon#read 4, iclass 7, count 0 2006.190.07:47:41.95#ibcon#about to read 5, iclass 7, count 0 2006.190.07:47:41.95#ibcon#read 5, iclass 7, count 0 2006.190.07:47:41.95#ibcon#about to read 6, iclass 7, count 0 2006.190.07:47:41.95#ibcon#read 6, iclass 7, count 0 2006.190.07:47:41.95#ibcon#end of sib2, iclass 7, count 0 2006.190.07:47:41.95#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:47:41.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:47:41.95#ibcon#[27=USB\r\n] 2006.190.07:47:41.95#ibcon#*before write, iclass 7, count 0 2006.190.07:47:41.95#ibcon#enter sib2, iclass 7, count 0 2006.190.07:47:41.95#ibcon#flushed, iclass 7, count 0 2006.190.07:47:41.95#ibcon#about to write, iclass 7, count 0 2006.190.07:47:41.95#ibcon#wrote, iclass 7, count 0 2006.190.07:47:41.95#ibcon#about to read 3, iclass 7, count 0 2006.190.07:47:41.98#ibcon#read 3, iclass 7, count 0 2006.190.07:47:41.98#ibcon#about to read 4, iclass 7, count 0 2006.190.07:47:41.98#ibcon#read 4, iclass 7, count 0 2006.190.07:47:41.98#ibcon#about to read 5, iclass 7, count 0 2006.190.07:47:41.98#ibcon#read 5, iclass 7, count 0 2006.190.07:47:41.98#ibcon#about to read 6, iclass 7, count 0 2006.190.07:47:41.98#ibcon#read 6, iclass 7, count 0 2006.190.07:47:41.98#ibcon#end of sib2, iclass 7, count 0 2006.190.07:47:41.98#ibcon#*after write, iclass 7, count 0 2006.190.07:47:41.98#ibcon#*before return 0, iclass 7, count 0 2006.190.07:47:41.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:41.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:47:41.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:47:41.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:47:41.98$vc4f8/vblo=5,744.99 2006.190.07:47:41.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.07:47:41.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.07:47:41.98#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:41.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:41.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:41.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:41.98#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:47:41.98#ibcon#first serial, iclass 11, count 0 2006.190.07:47:41.98#ibcon#enter sib2, iclass 11, count 0 2006.190.07:47:41.98#ibcon#flushed, iclass 11, count 0 2006.190.07:47:41.98#ibcon#about to write, iclass 11, count 0 2006.190.07:47:41.98#ibcon#wrote, iclass 11, count 0 2006.190.07:47:41.98#ibcon#about to read 3, iclass 11, count 0 2006.190.07:47:42.00#ibcon#read 3, iclass 11, count 0 2006.190.07:47:42.00#ibcon#about to read 4, iclass 11, count 0 2006.190.07:47:42.00#ibcon#read 4, iclass 11, count 0 2006.190.07:47:42.00#ibcon#about to read 5, iclass 11, count 0 2006.190.07:47:42.00#ibcon#read 5, iclass 11, count 0 2006.190.07:47:42.00#ibcon#about to read 6, iclass 11, count 0 2006.190.07:47:42.00#ibcon#read 6, iclass 11, count 0 2006.190.07:47:42.00#ibcon#end of sib2, iclass 11, count 0 2006.190.07:47:42.00#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:47:42.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:47:42.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:47:42.00#ibcon#*before write, iclass 11, count 0 2006.190.07:47:42.00#ibcon#enter sib2, iclass 11, count 0 2006.190.07:47:42.00#ibcon#flushed, iclass 11, count 0 2006.190.07:47:42.00#ibcon#about to write, iclass 11, count 0 2006.190.07:47:42.00#ibcon#wrote, iclass 11, count 0 2006.190.07:47:42.00#ibcon#about to read 3, iclass 11, count 0 2006.190.07:47:42.04#ibcon#read 3, iclass 11, count 0 2006.190.07:47:42.04#ibcon#about to read 4, iclass 11, count 0 2006.190.07:47:42.04#ibcon#read 4, iclass 11, count 0 2006.190.07:47:42.04#ibcon#about to read 5, iclass 11, count 0 2006.190.07:47:42.04#ibcon#read 5, iclass 11, count 0 2006.190.07:47:42.04#ibcon#about to read 6, iclass 11, count 0 2006.190.07:47:42.04#ibcon#read 6, iclass 11, count 0 2006.190.07:47:42.04#ibcon#end of sib2, iclass 11, count 0 2006.190.07:47:42.04#ibcon#*after write, iclass 11, count 0 2006.190.07:47:42.04#ibcon#*before return 0, iclass 11, count 0 2006.190.07:47:42.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:42.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:47:42.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:47:42.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:47:42.04$vc4f8/vb=5,4 2006.190.07:47:42.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.07:47:42.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.07:47:42.04#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:42.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:42.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:42.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:42.10#ibcon#enter wrdev, iclass 13, count 2 2006.190.07:47:42.10#ibcon#first serial, iclass 13, count 2 2006.190.07:47:42.10#ibcon#enter sib2, iclass 13, count 2 2006.190.07:47:42.10#ibcon#flushed, iclass 13, count 2 2006.190.07:47:42.10#ibcon#about to write, iclass 13, count 2 2006.190.07:47:42.10#ibcon#wrote, iclass 13, count 2 2006.190.07:47:42.10#ibcon#about to read 3, iclass 13, count 2 2006.190.07:47:42.12#ibcon#read 3, iclass 13, count 2 2006.190.07:47:42.12#ibcon#about to read 4, iclass 13, count 2 2006.190.07:47:42.12#ibcon#read 4, iclass 13, count 2 2006.190.07:47:42.12#ibcon#about to read 5, iclass 13, count 2 2006.190.07:47:42.12#ibcon#read 5, iclass 13, count 2 2006.190.07:47:42.12#ibcon#about to read 6, iclass 13, count 2 2006.190.07:47:42.12#ibcon#read 6, iclass 13, count 2 2006.190.07:47:42.12#ibcon#end of sib2, iclass 13, count 2 2006.190.07:47:42.12#ibcon#*mode == 0, iclass 13, count 2 2006.190.07:47:42.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.07:47:42.12#ibcon#[27=AT05-04\r\n] 2006.190.07:47:42.12#ibcon#*before write, iclass 13, count 2 2006.190.07:47:42.12#ibcon#enter sib2, iclass 13, count 2 2006.190.07:47:42.12#ibcon#flushed, iclass 13, count 2 2006.190.07:47:42.12#ibcon#about to write, iclass 13, count 2 2006.190.07:47:42.12#ibcon#wrote, iclass 13, count 2 2006.190.07:47:42.12#ibcon#about to read 3, iclass 13, count 2 2006.190.07:47:42.15#ibcon#read 3, iclass 13, count 2 2006.190.07:47:42.15#ibcon#about to read 4, iclass 13, count 2 2006.190.07:47:42.15#ibcon#read 4, iclass 13, count 2 2006.190.07:47:42.15#ibcon#about to read 5, iclass 13, count 2 2006.190.07:47:42.15#ibcon#read 5, iclass 13, count 2 2006.190.07:47:42.15#ibcon#about to read 6, iclass 13, count 2 2006.190.07:47:42.15#ibcon#read 6, iclass 13, count 2 2006.190.07:47:42.15#ibcon#end of sib2, iclass 13, count 2 2006.190.07:47:42.15#ibcon#*after write, iclass 13, count 2 2006.190.07:47:42.15#ibcon#*before return 0, iclass 13, count 2 2006.190.07:47:42.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:42.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:47:42.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.07:47:42.15#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:42.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:42.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:42.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:42.27#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:47:42.27#ibcon#first serial, iclass 13, count 0 2006.190.07:47:42.27#ibcon#enter sib2, iclass 13, count 0 2006.190.07:47:42.27#ibcon#flushed, iclass 13, count 0 2006.190.07:47:42.27#ibcon#about to write, iclass 13, count 0 2006.190.07:47:42.27#ibcon#wrote, iclass 13, count 0 2006.190.07:47:42.27#ibcon#about to read 3, iclass 13, count 0 2006.190.07:47:42.29#ibcon#read 3, iclass 13, count 0 2006.190.07:47:42.29#ibcon#about to read 4, iclass 13, count 0 2006.190.07:47:42.29#ibcon#read 4, iclass 13, count 0 2006.190.07:47:42.29#ibcon#about to read 5, iclass 13, count 0 2006.190.07:47:42.29#ibcon#read 5, iclass 13, count 0 2006.190.07:47:42.29#ibcon#about to read 6, iclass 13, count 0 2006.190.07:47:42.29#ibcon#read 6, iclass 13, count 0 2006.190.07:47:42.29#ibcon#end of sib2, iclass 13, count 0 2006.190.07:47:42.29#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:47:42.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:47:42.29#ibcon#[27=USB\r\n] 2006.190.07:47:42.29#ibcon#*before write, iclass 13, count 0 2006.190.07:47:42.29#ibcon#enter sib2, iclass 13, count 0 2006.190.07:47:42.29#ibcon#flushed, iclass 13, count 0 2006.190.07:47:42.29#ibcon#about to write, iclass 13, count 0 2006.190.07:47:42.29#ibcon#wrote, iclass 13, count 0 2006.190.07:47:42.29#ibcon#about to read 3, iclass 13, count 0 2006.190.07:47:42.32#ibcon#read 3, iclass 13, count 0 2006.190.07:47:42.32#ibcon#about to read 4, iclass 13, count 0 2006.190.07:47:42.32#ibcon#read 4, iclass 13, count 0 2006.190.07:47:42.32#ibcon#about to read 5, iclass 13, count 0 2006.190.07:47:42.32#ibcon#read 5, iclass 13, count 0 2006.190.07:47:42.32#ibcon#about to read 6, iclass 13, count 0 2006.190.07:47:42.32#ibcon#read 6, iclass 13, count 0 2006.190.07:47:42.32#ibcon#end of sib2, iclass 13, count 0 2006.190.07:47:42.32#ibcon#*after write, iclass 13, count 0 2006.190.07:47:42.32#ibcon#*before return 0, iclass 13, count 0 2006.190.07:47:42.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:42.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:47:42.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:47:42.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:47:42.32$vc4f8/vblo=6,752.99 2006.190.07:47:42.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:47:42.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:47:42.32#ibcon#ireg 17 cls_cnt 0 2006.190.07:47:42.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:42.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:42.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:42.32#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:47:42.32#ibcon#first serial, iclass 15, count 0 2006.190.07:47:42.32#ibcon#enter sib2, iclass 15, count 0 2006.190.07:47:42.32#ibcon#flushed, iclass 15, count 0 2006.190.07:47:42.32#ibcon#about to write, iclass 15, count 0 2006.190.07:47:42.32#ibcon#wrote, iclass 15, count 0 2006.190.07:47:42.32#ibcon#about to read 3, iclass 15, count 0 2006.190.07:47:42.34#ibcon#read 3, iclass 15, count 0 2006.190.07:47:42.34#ibcon#about to read 4, iclass 15, count 0 2006.190.07:47:42.34#ibcon#read 4, iclass 15, count 0 2006.190.07:47:42.34#ibcon#about to read 5, iclass 15, count 0 2006.190.07:47:42.34#ibcon#read 5, iclass 15, count 0 2006.190.07:47:42.34#ibcon#about to read 6, iclass 15, count 0 2006.190.07:47:42.34#ibcon#read 6, iclass 15, count 0 2006.190.07:47:42.34#ibcon#end of sib2, iclass 15, count 0 2006.190.07:47:42.34#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:47:42.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:47:42.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:47:42.34#ibcon#*before write, iclass 15, count 0 2006.190.07:47:42.34#ibcon#enter sib2, iclass 15, count 0 2006.190.07:47:42.34#ibcon#flushed, iclass 15, count 0 2006.190.07:47:42.34#ibcon#about to write, iclass 15, count 0 2006.190.07:47:42.34#ibcon#wrote, iclass 15, count 0 2006.190.07:47:42.34#ibcon#about to read 3, iclass 15, count 0 2006.190.07:47:42.38#ibcon#read 3, iclass 15, count 0 2006.190.07:47:42.38#ibcon#about to read 4, iclass 15, count 0 2006.190.07:47:42.38#ibcon#read 4, iclass 15, count 0 2006.190.07:47:42.38#ibcon#about to read 5, iclass 15, count 0 2006.190.07:47:42.38#ibcon#read 5, iclass 15, count 0 2006.190.07:47:42.38#ibcon#about to read 6, iclass 15, count 0 2006.190.07:47:42.38#ibcon#read 6, iclass 15, count 0 2006.190.07:47:42.38#ibcon#end of sib2, iclass 15, count 0 2006.190.07:47:42.38#ibcon#*after write, iclass 15, count 0 2006.190.07:47:42.38#ibcon#*before return 0, iclass 15, count 0 2006.190.07:47:42.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:42.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:47:42.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:47:42.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:47:42.38$vc4f8/vb=6,4 2006.190.07:47:42.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.07:47:42.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.07:47:42.38#ibcon#ireg 11 cls_cnt 2 2006.190.07:47:42.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:42.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:42.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:42.44#ibcon#enter wrdev, iclass 17, count 2 2006.190.07:47:42.44#ibcon#first serial, iclass 17, count 2 2006.190.07:47:42.44#ibcon#enter sib2, iclass 17, count 2 2006.190.07:47:42.44#ibcon#flushed, iclass 17, count 2 2006.190.07:47:42.44#ibcon#about to write, iclass 17, count 2 2006.190.07:47:42.44#ibcon#wrote, iclass 17, count 2 2006.190.07:47:42.44#ibcon#about to read 3, iclass 17, count 2 2006.190.07:47:42.46#ibcon#read 3, iclass 17, count 2 2006.190.07:47:42.46#ibcon#about to read 4, iclass 17, count 2 2006.190.07:47:42.46#ibcon#read 4, iclass 17, count 2 2006.190.07:47:42.46#ibcon#about to read 5, iclass 17, count 2 2006.190.07:47:42.46#ibcon#read 5, iclass 17, count 2 2006.190.07:47:42.46#ibcon#about to read 6, iclass 17, count 2 2006.190.07:47:42.46#ibcon#read 6, iclass 17, count 2 2006.190.07:47:42.46#ibcon#end of sib2, iclass 17, count 2 2006.190.07:47:42.46#ibcon#*mode == 0, iclass 17, count 2 2006.190.07:47:42.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.07:47:42.46#ibcon#[27=AT06-04\r\n] 2006.190.07:47:42.46#ibcon#*before write, iclass 17, count 2 2006.190.07:47:42.46#ibcon#enter sib2, iclass 17, count 2 2006.190.07:47:42.46#ibcon#flushed, iclass 17, count 2 2006.190.07:47:42.46#ibcon#about to write, iclass 17, count 2 2006.190.07:47:42.46#ibcon#wrote, iclass 17, count 2 2006.190.07:47:42.46#ibcon#about to read 3, iclass 17, count 2 2006.190.07:47:42.49#ibcon#read 3, iclass 17, count 2 2006.190.07:47:42.49#ibcon#about to read 4, iclass 17, count 2 2006.190.07:47:42.49#ibcon#read 4, iclass 17, count 2 2006.190.07:47:42.49#ibcon#about to read 5, iclass 17, count 2 2006.190.07:47:42.49#ibcon#read 5, iclass 17, count 2 2006.190.07:47:42.49#ibcon#about to read 6, iclass 17, count 2 2006.190.07:47:42.49#ibcon#read 6, iclass 17, count 2 2006.190.07:47:42.49#ibcon#end of sib2, iclass 17, count 2 2006.190.07:47:42.49#ibcon#*after write, iclass 17, count 2 2006.190.07:47:42.49#ibcon#*before return 0, iclass 17, count 2 2006.190.07:47:42.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:42.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:47:42.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.07:47:42.49#ibcon#ireg 7 cls_cnt 0 2006.190.07:47:42.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:42.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:42.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:42.61#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:47:42.61#ibcon#first serial, iclass 17, count 0 2006.190.07:47:42.61#ibcon#enter sib2, iclass 17, count 0 2006.190.07:47:42.61#ibcon#flushed, iclass 17, count 0 2006.190.07:47:42.61#ibcon#about to write, iclass 17, count 0 2006.190.07:47:42.61#ibcon#wrote, iclass 17, count 0 2006.190.07:47:42.61#ibcon#about to read 3, iclass 17, count 0 2006.190.07:47:42.63#ibcon#read 3, iclass 17, count 0 2006.190.07:47:42.63#ibcon#about to read 4, iclass 17, count 0 2006.190.07:47:42.63#ibcon#read 4, iclass 17, count 0 2006.190.07:47:42.63#ibcon#about to read 5, iclass 17, count 0 2006.190.07:47:42.63#ibcon#read 5, iclass 17, count 0 2006.190.07:47:42.63#ibcon#about to read 6, iclass 17, count 0 2006.190.07:47:42.63#ibcon#read 6, iclass 17, count 0 2006.190.07:47:42.63#ibcon#end of sib2, iclass 17, count 0 2006.190.07:47:42.63#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:47:42.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:47:42.63#ibcon#[27=USB\r\n] 2006.190.07:47:42.63#ibcon#*before write, iclass 17, count 0 2006.190.07:47:42.63#ibcon#enter sib2, iclass 17, count 0 2006.190.07:47:42.63#ibcon#flushed, iclass 17, count 0 2006.190.07:47:42.63#ibcon#about to write, iclass 17, count 0 2006.190.07:47:42.63#ibcon#wrote, iclass 17, count 0 2006.190.07:47:42.63#ibcon#about to read 3, iclass 17, count 0 2006.190.07:47:42.66#ibcon#read 3, iclass 17, count 0 2006.190.07:47:42.66#ibcon#about to read 4, iclass 17, count 0 2006.190.07:47:42.66#ibcon#read 4, iclass 17, count 0 2006.190.07:47:42.66#ibcon#about to read 5, iclass 17, count 0 2006.190.07:47:42.66#ibcon#read 5, iclass 17, count 0 2006.190.07:47:42.66#ibcon#about to read 6, iclass 17, count 0 2006.190.07:47:42.66#ibcon#read 6, iclass 17, count 0 2006.190.07:47:42.66#ibcon#end of sib2, iclass 17, count 0 2006.190.07:47:42.66#ibcon#*after write, iclass 17, count 0 2006.190.07:47:42.66#ibcon#*before return 0, iclass 17, count 0 2006.190.07:47:42.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:42.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:47:42.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:47:42.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:47:42.66$vc4f8/vabw=wide 2006.190.07:47:42.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:47:42.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:47:42.66#ibcon#ireg 8 cls_cnt 0 2006.190.07:47:42.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:42.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:42.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:42.66#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:47:42.66#ibcon#first serial, iclass 19, count 0 2006.190.07:47:42.66#ibcon#enter sib2, iclass 19, count 0 2006.190.07:47:42.66#ibcon#flushed, iclass 19, count 0 2006.190.07:47:42.66#ibcon#about to write, iclass 19, count 0 2006.190.07:47:42.66#ibcon#wrote, iclass 19, count 0 2006.190.07:47:42.66#ibcon#about to read 3, iclass 19, count 0 2006.190.07:47:42.68#ibcon#read 3, iclass 19, count 0 2006.190.07:47:42.68#ibcon#about to read 4, iclass 19, count 0 2006.190.07:47:42.68#ibcon#read 4, iclass 19, count 0 2006.190.07:47:42.68#ibcon#about to read 5, iclass 19, count 0 2006.190.07:47:42.68#ibcon#read 5, iclass 19, count 0 2006.190.07:47:42.68#ibcon#about to read 6, iclass 19, count 0 2006.190.07:47:42.68#ibcon#read 6, iclass 19, count 0 2006.190.07:47:42.68#ibcon#end of sib2, iclass 19, count 0 2006.190.07:47:42.68#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:47:42.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:47:42.68#ibcon#[25=BW32\r\n] 2006.190.07:47:42.68#ibcon#*before write, iclass 19, count 0 2006.190.07:47:42.68#ibcon#enter sib2, iclass 19, count 0 2006.190.07:47:42.68#ibcon#flushed, iclass 19, count 0 2006.190.07:47:42.68#ibcon#about to write, iclass 19, count 0 2006.190.07:47:42.68#ibcon#wrote, iclass 19, count 0 2006.190.07:47:42.68#ibcon#about to read 3, iclass 19, count 0 2006.190.07:47:42.71#ibcon#read 3, iclass 19, count 0 2006.190.07:47:42.71#ibcon#about to read 4, iclass 19, count 0 2006.190.07:47:42.71#ibcon#read 4, iclass 19, count 0 2006.190.07:47:42.71#ibcon#about to read 5, iclass 19, count 0 2006.190.07:47:42.71#ibcon#read 5, iclass 19, count 0 2006.190.07:47:42.71#ibcon#about to read 6, iclass 19, count 0 2006.190.07:47:42.71#ibcon#read 6, iclass 19, count 0 2006.190.07:47:42.71#ibcon#end of sib2, iclass 19, count 0 2006.190.07:47:42.71#ibcon#*after write, iclass 19, count 0 2006.190.07:47:42.71#ibcon#*before return 0, iclass 19, count 0 2006.190.07:47:42.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:42.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:47:42.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:47:42.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:47:42.71$vc4f8/vbbw=wide 2006.190.07:47:42.71#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.07:47:42.71#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.07:47:42.71#ibcon#ireg 8 cls_cnt 0 2006.190.07:47:42.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:47:42.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:47:42.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:47:42.78#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:47:42.78#ibcon#first serial, iclass 21, count 0 2006.190.07:47:42.78#ibcon#enter sib2, iclass 21, count 0 2006.190.07:47:42.78#ibcon#flushed, iclass 21, count 0 2006.190.07:47:42.78#ibcon#about to write, iclass 21, count 0 2006.190.07:47:42.78#ibcon#wrote, iclass 21, count 0 2006.190.07:47:42.78#ibcon#about to read 3, iclass 21, count 0 2006.190.07:47:42.80#ibcon#read 3, iclass 21, count 0 2006.190.07:47:42.80#ibcon#about to read 4, iclass 21, count 0 2006.190.07:47:42.80#ibcon#read 4, iclass 21, count 0 2006.190.07:47:42.80#ibcon#about to read 5, iclass 21, count 0 2006.190.07:47:42.80#ibcon#read 5, iclass 21, count 0 2006.190.07:47:42.80#ibcon#about to read 6, iclass 21, count 0 2006.190.07:47:42.80#ibcon#read 6, iclass 21, count 0 2006.190.07:47:42.80#ibcon#end of sib2, iclass 21, count 0 2006.190.07:47:42.80#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:47:42.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:47:42.80#ibcon#[27=BW32\r\n] 2006.190.07:47:42.80#ibcon#*before write, iclass 21, count 0 2006.190.07:47:42.80#ibcon#enter sib2, iclass 21, count 0 2006.190.07:47:42.80#ibcon#flushed, iclass 21, count 0 2006.190.07:47:42.80#ibcon#about to write, iclass 21, count 0 2006.190.07:47:42.80#ibcon#wrote, iclass 21, count 0 2006.190.07:47:42.80#ibcon#about to read 3, iclass 21, count 0 2006.190.07:47:42.83#ibcon#read 3, iclass 21, count 0 2006.190.07:47:42.83#ibcon#about to read 4, iclass 21, count 0 2006.190.07:47:42.83#ibcon#read 4, iclass 21, count 0 2006.190.07:47:42.83#ibcon#about to read 5, iclass 21, count 0 2006.190.07:47:42.83#ibcon#read 5, iclass 21, count 0 2006.190.07:47:42.83#ibcon#about to read 6, iclass 21, count 0 2006.190.07:47:42.83#ibcon#read 6, iclass 21, count 0 2006.190.07:47:42.83#ibcon#end of sib2, iclass 21, count 0 2006.190.07:47:42.83#ibcon#*after write, iclass 21, count 0 2006.190.07:47:42.83#ibcon#*before return 0, iclass 21, count 0 2006.190.07:47:42.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:47:42.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:47:42.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:47:42.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:47:42.83$4f8m12a/ifd4f 2006.190.07:47:42.83$ifd4f/lo= 2006.190.07:47:42.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:47:42.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:47:42.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:47:42.83$ifd4f/patch= 2006.190.07:47:42.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:47:42.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:47:42.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:47:42.83$4f8m12a/"form=m,16.000,1:2 2006.190.07:47:42.83$4f8m12a/"tpicd 2006.190.07:47:42.83$4f8m12a/echo=off 2006.190.07:47:42.83$4f8m12a/xlog=off 2006.190.07:47:42.83:!2006.190.07:48:10 2006.190.07:47:50.13#trakl#Source acquired 2006.190.07:47:52.13#flagr#flagr/antenna,acquired 2006.190.07:48:10.00:preob 2006.190.07:48:11.14/onsource/TRACKING 2006.190.07:48:11.14:!2006.190.07:48:20 2006.190.07:48:20.00:data_valid=on 2006.190.07:48:20.00:midob 2006.190.07:48:20.14/onsource/TRACKING 2006.190.07:48:20.14/wx/24.52,1012.1,100 2006.190.07:48:20.32/cable/+6.4706E-03 2006.190.07:48:21.41/va/01,08,usb,yes,34,36 2006.190.07:48:21.41/va/02,07,usb,yes,35,36 2006.190.07:48:21.41/va/03,06,usb,yes,36,37 2006.190.07:48:21.41/va/04,07,usb,yes,36,38 2006.190.07:48:21.41/va/05,07,usb,yes,39,41 2006.190.07:48:21.41/va/06,06,usb,yes,38,38 2006.190.07:48:21.41/va/07,06,usb,yes,39,38 2006.190.07:48:21.41/va/08,06,usb,yes,41,41 2006.190.07:48:21.64/valo/01,532.99,yes,locked 2006.190.07:48:21.64/valo/02,572.99,yes,locked 2006.190.07:48:21.64/valo/03,672.99,yes,locked 2006.190.07:48:21.64/valo/04,832.99,yes,locked 2006.190.07:48:21.64/valo/05,652.99,yes,locked 2006.190.07:48:21.64/valo/06,772.99,yes,locked 2006.190.07:48:21.64/valo/07,832.99,yes,locked 2006.190.07:48:21.64/valo/08,852.99,yes,locked 2006.190.07:48:22.73/vb/01,04,usb,yes,29,28 2006.190.07:48:22.73/vb/02,04,usb,yes,31,32 2006.190.07:48:22.73/vb/03,04,usb,yes,28,31 2006.190.07:48:22.73/vb/04,04,usb,yes,28,29 2006.190.07:48:22.73/vb/05,04,usb,yes,27,31 2006.190.07:48:22.73/vb/06,04,usb,yes,28,31 2006.190.07:48:22.73/vb/07,04,usb,yes,30,30 2006.190.07:48:22.73/vb/08,04,usb,yes,28,31 2006.190.07:48:22.96/vblo/01,632.99,yes,locked 2006.190.07:48:22.96/vblo/02,640.99,yes,locked 2006.190.07:48:22.96/vblo/03,656.99,yes,locked 2006.190.07:48:22.96/vblo/04,712.99,yes,locked 2006.190.07:48:22.96/vblo/05,744.99,yes,locked 2006.190.07:48:22.96/vblo/06,752.99,yes,locked 2006.190.07:48:22.96/vblo/07,734.99,yes,locked 2006.190.07:48:22.96/vblo/08,744.99,yes,locked 2006.190.07:48:23.11/vabw/8 2006.190.07:48:23.26/vbbw/8 2006.190.07:48:23.47/xfe/off,on,14.5 2006.190.07:48:23.86/ifatt/23,28,28,28 2006.190.07:48:24.07/fmout-gps/S +2.89E-07 2006.190.07:48:24.15:!2006.190.07:49:20 2006.190.07:49:20.01:data_valid=off 2006.190.07:49:20.01:postob 2006.190.07:49:20.13/cable/+6.4694E-03 2006.190.07:49:20.13/wx/24.53,1012.0,100 2006.190.07:49:21.08/fmout-gps/S +2.90E-07 2006.190.07:49:21.08:scan_name=190-0750,k06190,60 2006.190.07:49:21.09:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.190.07:49:21.14#flagr#flagr/antenna,new-source 2006.190.07:49:22.14:checkk5 2006.190.07:49:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:49:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:49:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:49:23.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:49:24.05/chk_obsdata//k5ts1/T1900748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:49:24.43/chk_obsdata//k5ts2/T1900748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:49:24.81/chk_obsdata//k5ts3/T1900748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:49:25.19/chk_obsdata//k5ts4/T1900748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:49:25.88/k5log//k5ts1_log_newline 2006.190.07:49:26.58/k5log//k5ts2_log_newline 2006.190.07:49:27.28/k5log//k5ts3_log_newline 2006.190.07:49:27.98/k5log//k5ts4_log_newline 2006.190.07:49:28.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:49:28.00:4f8m12a=1 2006.190.07:49:28.00$4f8m12a/echo=on 2006.190.07:49:28.00$4f8m12a/pcalon 2006.190.07:49:28.00$pcalon/"no phase cal control is implemented here 2006.190.07:49:28.00$4f8m12a/"tpicd=stop 2006.190.07:49:28.00$4f8m12a/vc4f8 2006.190.07:49:28.00$vc4f8/valo=1,532.99 2006.190.07:49:28.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:49:28.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:49:28.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:28.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:28.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:28.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:28.01#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:49:28.01#ibcon#first serial, iclass 32, count 0 2006.190.07:49:28.01#ibcon#enter sib2, iclass 32, count 0 2006.190.07:49:28.01#ibcon#flushed, iclass 32, count 0 2006.190.07:49:28.01#ibcon#about to write, iclass 32, count 0 2006.190.07:49:28.01#ibcon#wrote, iclass 32, count 0 2006.190.07:49:28.01#ibcon#about to read 3, iclass 32, count 0 2006.190.07:49:28.06#ibcon#read 3, iclass 32, count 0 2006.190.07:49:28.06#ibcon#about to read 4, iclass 32, count 0 2006.190.07:49:28.06#ibcon#read 4, iclass 32, count 0 2006.190.07:49:28.06#ibcon#about to read 5, iclass 32, count 0 2006.190.07:49:28.06#ibcon#read 5, iclass 32, count 0 2006.190.07:49:28.06#ibcon#about to read 6, iclass 32, count 0 2006.190.07:49:28.06#ibcon#read 6, iclass 32, count 0 2006.190.07:49:28.06#ibcon#end of sib2, iclass 32, count 0 2006.190.07:49:28.06#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:49:28.06#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:49:28.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:49:28.06#ibcon#*before write, iclass 32, count 0 2006.190.07:49:28.06#ibcon#enter sib2, iclass 32, count 0 2006.190.07:49:28.06#ibcon#flushed, iclass 32, count 0 2006.190.07:49:28.06#ibcon#about to write, iclass 32, count 0 2006.190.07:49:28.06#ibcon#wrote, iclass 32, count 0 2006.190.07:49:28.06#ibcon#about to read 3, iclass 32, count 0 2006.190.07:49:28.11#ibcon#read 3, iclass 32, count 0 2006.190.07:49:28.11#ibcon#about to read 4, iclass 32, count 0 2006.190.07:49:28.11#ibcon#read 4, iclass 32, count 0 2006.190.07:49:28.11#ibcon#about to read 5, iclass 32, count 0 2006.190.07:49:28.11#ibcon#read 5, iclass 32, count 0 2006.190.07:49:28.11#ibcon#about to read 6, iclass 32, count 0 2006.190.07:49:28.11#ibcon#read 6, iclass 32, count 0 2006.190.07:49:28.11#ibcon#end of sib2, iclass 32, count 0 2006.190.07:49:28.11#ibcon#*after write, iclass 32, count 0 2006.190.07:49:28.11#ibcon#*before return 0, iclass 32, count 0 2006.190.07:49:28.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:28.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:28.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:49:28.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:49:28.11$vc4f8/va=1,8 2006.190.07:49:28.11#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:49:28.11#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:49:28.11#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:28.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:28.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:28.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:28.11#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:49:28.11#ibcon#first serial, iclass 34, count 2 2006.190.07:49:28.11#ibcon#enter sib2, iclass 34, count 2 2006.190.07:49:28.11#ibcon#flushed, iclass 34, count 2 2006.190.07:49:28.11#ibcon#about to write, iclass 34, count 2 2006.190.07:49:28.11#ibcon#wrote, iclass 34, count 2 2006.190.07:49:28.11#ibcon#about to read 3, iclass 34, count 2 2006.190.07:49:28.13#ibcon#read 3, iclass 34, count 2 2006.190.07:49:28.13#ibcon#about to read 4, iclass 34, count 2 2006.190.07:49:28.13#ibcon#read 4, iclass 34, count 2 2006.190.07:49:28.13#ibcon#about to read 5, iclass 34, count 2 2006.190.07:49:28.13#ibcon#read 5, iclass 34, count 2 2006.190.07:49:28.13#ibcon#about to read 6, iclass 34, count 2 2006.190.07:49:28.13#ibcon#read 6, iclass 34, count 2 2006.190.07:49:28.13#ibcon#end of sib2, iclass 34, count 2 2006.190.07:49:28.13#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:49:28.13#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:49:28.13#ibcon#[25=AT01-08\r\n] 2006.190.07:49:28.13#ibcon#*before write, iclass 34, count 2 2006.190.07:49:28.13#ibcon#enter sib2, iclass 34, count 2 2006.190.07:49:28.13#ibcon#flushed, iclass 34, count 2 2006.190.07:49:28.13#ibcon#about to write, iclass 34, count 2 2006.190.07:49:28.13#ibcon#wrote, iclass 34, count 2 2006.190.07:49:28.13#ibcon#about to read 3, iclass 34, count 2 2006.190.07:49:28.16#ibcon#read 3, iclass 34, count 2 2006.190.07:49:28.16#ibcon#about to read 4, iclass 34, count 2 2006.190.07:49:28.16#ibcon#read 4, iclass 34, count 2 2006.190.07:49:28.16#ibcon#about to read 5, iclass 34, count 2 2006.190.07:49:28.16#ibcon#read 5, iclass 34, count 2 2006.190.07:49:28.16#ibcon#about to read 6, iclass 34, count 2 2006.190.07:49:28.16#ibcon#read 6, iclass 34, count 2 2006.190.07:49:28.16#ibcon#end of sib2, iclass 34, count 2 2006.190.07:49:28.16#ibcon#*after write, iclass 34, count 2 2006.190.07:49:28.16#ibcon#*before return 0, iclass 34, count 2 2006.190.07:49:28.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:28.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:28.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:49:28.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:28.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:28.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:28.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:28.28#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:49:28.28#ibcon#first serial, iclass 34, count 0 2006.190.07:49:28.28#ibcon#enter sib2, iclass 34, count 0 2006.190.07:49:28.28#ibcon#flushed, iclass 34, count 0 2006.190.07:49:28.28#ibcon#about to write, iclass 34, count 0 2006.190.07:49:28.28#ibcon#wrote, iclass 34, count 0 2006.190.07:49:28.28#ibcon#about to read 3, iclass 34, count 0 2006.190.07:49:28.30#ibcon#read 3, iclass 34, count 0 2006.190.07:49:28.30#ibcon#about to read 4, iclass 34, count 0 2006.190.07:49:28.30#ibcon#read 4, iclass 34, count 0 2006.190.07:49:28.30#ibcon#about to read 5, iclass 34, count 0 2006.190.07:49:28.30#ibcon#read 5, iclass 34, count 0 2006.190.07:49:28.30#ibcon#about to read 6, iclass 34, count 0 2006.190.07:49:28.30#ibcon#read 6, iclass 34, count 0 2006.190.07:49:28.30#ibcon#end of sib2, iclass 34, count 0 2006.190.07:49:28.30#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:49:28.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:49:28.30#ibcon#[25=USB\r\n] 2006.190.07:49:28.30#ibcon#*before write, iclass 34, count 0 2006.190.07:49:28.30#ibcon#enter sib2, iclass 34, count 0 2006.190.07:49:28.30#ibcon#flushed, iclass 34, count 0 2006.190.07:49:28.30#ibcon#about to write, iclass 34, count 0 2006.190.07:49:28.30#ibcon#wrote, iclass 34, count 0 2006.190.07:49:28.30#ibcon#about to read 3, iclass 34, count 0 2006.190.07:49:28.33#ibcon#read 3, iclass 34, count 0 2006.190.07:49:28.33#ibcon#about to read 4, iclass 34, count 0 2006.190.07:49:28.33#ibcon#read 4, iclass 34, count 0 2006.190.07:49:28.33#ibcon#about to read 5, iclass 34, count 0 2006.190.07:49:28.33#ibcon#read 5, iclass 34, count 0 2006.190.07:49:28.33#ibcon#about to read 6, iclass 34, count 0 2006.190.07:49:28.33#ibcon#read 6, iclass 34, count 0 2006.190.07:49:28.33#ibcon#end of sib2, iclass 34, count 0 2006.190.07:49:28.33#ibcon#*after write, iclass 34, count 0 2006.190.07:49:28.33#ibcon#*before return 0, iclass 34, count 0 2006.190.07:49:28.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:28.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:28.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:49:28.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:49:28.33$vc4f8/valo=2,572.99 2006.190.07:49:28.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:49:28.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:49:28.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:28.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:28.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:28.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:28.33#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:49:28.33#ibcon#first serial, iclass 36, count 0 2006.190.07:49:28.33#ibcon#enter sib2, iclass 36, count 0 2006.190.07:49:28.33#ibcon#flushed, iclass 36, count 0 2006.190.07:49:28.33#ibcon#about to write, iclass 36, count 0 2006.190.07:49:28.33#ibcon#wrote, iclass 36, count 0 2006.190.07:49:28.33#ibcon#about to read 3, iclass 36, count 0 2006.190.07:49:28.35#ibcon#read 3, iclass 36, count 0 2006.190.07:49:28.35#ibcon#about to read 4, iclass 36, count 0 2006.190.07:49:28.35#ibcon#read 4, iclass 36, count 0 2006.190.07:49:28.35#ibcon#about to read 5, iclass 36, count 0 2006.190.07:49:28.35#ibcon#read 5, iclass 36, count 0 2006.190.07:49:28.35#ibcon#about to read 6, iclass 36, count 0 2006.190.07:49:28.35#ibcon#read 6, iclass 36, count 0 2006.190.07:49:28.35#ibcon#end of sib2, iclass 36, count 0 2006.190.07:49:28.35#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:49:28.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:49:28.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:49:28.35#ibcon#*before write, iclass 36, count 0 2006.190.07:49:28.35#ibcon#enter sib2, iclass 36, count 0 2006.190.07:49:28.35#ibcon#flushed, iclass 36, count 0 2006.190.07:49:28.35#ibcon#about to write, iclass 36, count 0 2006.190.07:49:28.35#ibcon#wrote, iclass 36, count 0 2006.190.07:49:28.35#ibcon#about to read 3, iclass 36, count 0 2006.190.07:49:28.39#ibcon#read 3, iclass 36, count 0 2006.190.07:49:28.39#ibcon#about to read 4, iclass 36, count 0 2006.190.07:49:28.39#ibcon#read 4, iclass 36, count 0 2006.190.07:49:28.39#ibcon#about to read 5, iclass 36, count 0 2006.190.07:49:28.39#ibcon#read 5, iclass 36, count 0 2006.190.07:49:28.39#ibcon#about to read 6, iclass 36, count 0 2006.190.07:49:28.39#ibcon#read 6, iclass 36, count 0 2006.190.07:49:28.39#ibcon#end of sib2, iclass 36, count 0 2006.190.07:49:28.39#ibcon#*after write, iclass 36, count 0 2006.190.07:49:28.39#ibcon#*before return 0, iclass 36, count 0 2006.190.07:49:28.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:28.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:28.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:49:28.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:49:28.39$vc4f8/va=2,7 2006.190.07:49:28.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.07:49:28.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.07:49:28.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:28.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:28.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:28.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:28.45#ibcon#enter wrdev, iclass 38, count 2 2006.190.07:49:28.45#ibcon#first serial, iclass 38, count 2 2006.190.07:49:28.45#ibcon#enter sib2, iclass 38, count 2 2006.190.07:49:28.45#ibcon#flushed, iclass 38, count 2 2006.190.07:49:28.45#ibcon#about to write, iclass 38, count 2 2006.190.07:49:28.45#ibcon#wrote, iclass 38, count 2 2006.190.07:49:28.45#ibcon#about to read 3, iclass 38, count 2 2006.190.07:49:28.47#ibcon#read 3, iclass 38, count 2 2006.190.07:49:28.47#ibcon#about to read 4, iclass 38, count 2 2006.190.07:49:28.47#ibcon#read 4, iclass 38, count 2 2006.190.07:49:28.47#ibcon#about to read 5, iclass 38, count 2 2006.190.07:49:28.47#ibcon#read 5, iclass 38, count 2 2006.190.07:49:28.47#ibcon#about to read 6, iclass 38, count 2 2006.190.07:49:28.47#ibcon#read 6, iclass 38, count 2 2006.190.07:49:28.47#ibcon#end of sib2, iclass 38, count 2 2006.190.07:49:28.47#ibcon#*mode == 0, iclass 38, count 2 2006.190.07:49:28.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.07:49:28.47#ibcon#[25=AT02-07\r\n] 2006.190.07:49:28.47#ibcon#*before write, iclass 38, count 2 2006.190.07:49:28.47#ibcon#enter sib2, iclass 38, count 2 2006.190.07:49:28.47#ibcon#flushed, iclass 38, count 2 2006.190.07:49:28.47#ibcon#about to write, iclass 38, count 2 2006.190.07:49:28.47#ibcon#wrote, iclass 38, count 2 2006.190.07:49:28.47#ibcon#about to read 3, iclass 38, count 2 2006.190.07:49:28.50#ibcon#read 3, iclass 38, count 2 2006.190.07:49:28.50#ibcon#about to read 4, iclass 38, count 2 2006.190.07:49:28.50#ibcon#read 4, iclass 38, count 2 2006.190.07:49:28.50#ibcon#about to read 5, iclass 38, count 2 2006.190.07:49:28.50#ibcon#read 5, iclass 38, count 2 2006.190.07:49:28.50#ibcon#about to read 6, iclass 38, count 2 2006.190.07:49:28.50#ibcon#read 6, iclass 38, count 2 2006.190.07:49:28.50#ibcon#end of sib2, iclass 38, count 2 2006.190.07:49:28.50#ibcon#*after write, iclass 38, count 2 2006.190.07:49:28.50#ibcon#*before return 0, iclass 38, count 2 2006.190.07:49:28.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:28.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:28.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.07:49:28.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:28.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:28.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:28.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:28.62#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:49:28.62#ibcon#first serial, iclass 38, count 0 2006.190.07:49:28.62#ibcon#enter sib2, iclass 38, count 0 2006.190.07:49:28.62#ibcon#flushed, iclass 38, count 0 2006.190.07:49:28.62#ibcon#about to write, iclass 38, count 0 2006.190.07:49:28.62#ibcon#wrote, iclass 38, count 0 2006.190.07:49:28.62#ibcon#about to read 3, iclass 38, count 0 2006.190.07:49:28.64#ibcon#read 3, iclass 38, count 0 2006.190.07:49:28.64#ibcon#about to read 4, iclass 38, count 0 2006.190.07:49:28.64#ibcon#read 4, iclass 38, count 0 2006.190.07:49:28.64#ibcon#about to read 5, iclass 38, count 0 2006.190.07:49:28.64#ibcon#read 5, iclass 38, count 0 2006.190.07:49:28.64#ibcon#about to read 6, iclass 38, count 0 2006.190.07:49:28.64#ibcon#read 6, iclass 38, count 0 2006.190.07:49:28.64#ibcon#end of sib2, iclass 38, count 0 2006.190.07:49:28.64#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:49:28.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:49:28.64#ibcon#[25=USB\r\n] 2006.190.07:49:28.64#ibcon#*before write, iclass 38, count 0 2006.190.07:49:28.64#ibcon#enter sib2, iclass 38, count 0 2006.190.07:49:28.64#ibcon#flushed, iclass 38, count 0 2006.190.07:49:28.64#ibcon#about to write, iclass 38, count 0 2006.190.07:49:28.64#ibcon#wrote, iclass 38, count 0 2006.190.07:49:28.64#ibcon#about to read 3, iclass 38, count 0 2006.190.07:49:28.67#ibcon#read 3, iclass 38, count 0 2006.190.07:49:28.67#ibcon#about to read 4, iclass 38, count 0 2006.190.07:49:28.67#ibcon#read 4, iclass 38, count 0 2006.190.07:49:28.67#ibcon#about to read 5, iclass 38, count 0 2006.190.07:49:28.67#ibcon#read 5, iclass 38, count 0 2006.190.07:49:28.67#ibcon#about to read 6, iclass 38, count 0 2006.190.07:49:28.67#ibcon#read 6, iclass 38, count 0 2006.190.07:49:28.67#ibcon#end of sib2, iclass 38, count 0 2006.190.07:49:28.67#ibcon#*after write, iclass 38, count 0 2006.190.07:49:28.67#ibcon#*before return 0, iclass 38, count 0 2006.190.07:49:28.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:28.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:28.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:49:28.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:49:28.67$vc4f8/valo=3,672.99 2006.190.07:49:28.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:49:28.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:49:28.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:28.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:28.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:28.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:28.67#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:49:28.67#ibcon#first serial, iclass 40, count 0 2006.190.07:49:28.67#ibcon#enter sib2, iclass 40, count 0 2006.190.07:49:28.67#ibcon#flushed, iclass 40, count 0 2006.190.07:49:28.67#ibcon#about to write, iclass 40, count 0 2006.190.07:49:28.67#ibcon#wrote, iclass 40, count 0 2006.190.07:49:28.67#ibcon#about to read 3, iclass 40, count 0 2006.190.07:49:28.69#ibcon#read 3, iclass 40, count 0 2006.190.07:49:28.69#ibcon#about to read 4, iclass 40, count 0 2006.190.07:49:28.69#ibcon#read 4, iclass 40, count 0 2006.190.07:49:28.69#ibcon#about to read 5, iclass 40, count 0 2006.190.07:49:28.69#ibcon#read 5, iclass 40, count 0 2006.190.07:49:28.69#ibcon#about to read 6, iclass 40, count 0 2006.190.07:49:28.69#ibcon#read 6, iclass 40, count 0 2006.190.07:49:28.69#ibcon#end of sib2, iclass 40, count 0 2006.190.07:49:28.69#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:49:28.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:49:28.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:49:28.69#ibcon#*before write, iclass 40, count 0 2006.190.07:49:28.69#ibcon#enter sib2, iclass 40, count 0 2006.190.07:49:28.69#ibcon#flushed, iclass 40, count 0 2006.190.07:49:28.69#ibcon#about to write, iclass 40, count 0 2006.190.07:49:28.69#ibcon#wrote, iclass 40, count 0 2006.190.07:49:28.69#ibcon#about to read 3, iclass 40, count 0 2006.190.07:49:28.73#ibcon#read 3, iclass 40, count 0 2006.190.07:49:28.73#ibcon#about to read 4, iclass 40, count 0 2006.190.07:49:28.73#ibcon#read 4, iclass 40, count 0 2006.190.07:49:28.73#ibcon#about to read 5, iclass 40, count 0 2006.190.07:49:28.73#ibcon#read 5, iclass 40, count 0 2006.190.07:49:28.73#ibcon#about to read 6, iclass 40, count 0 2006.190.07:49:28.73#ibcon#read 6, iclass 40, count 0 2006.190.07:49:28.73#ibcon#end of sib2, iclass 40, count 0 2006.190.07:49:28.73#ibcon#*after write, iclass 40, count 0 2006.190.07:49:28.73#ibcon#*before return 0, iclass 40, count 0 2006.190.07:49:28.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:28.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:28.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:49:28.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:49:28.73$vc4f8/va=3,6 2006.190.07:49:28.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:49:28.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:49:28.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:28.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:28.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:28.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:28.79#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:49:28.79#ibcon#first serial, iclass 4, count 2 2006.190.07:49:28.79#ibcon#enter sib2, iclass 4, count 2 2006.190.07:49:28.79#ibcon#flushed, iclass 4, count 2 2006.190.07:49:28.79#ibcon#about to write, iclass 4, count 2 2006.190.07:49:28.79#ibcon#wrote, iclass 4, count 2 2006.190.07:49:28.79#ibcon#about to read 3, iclass 4, count 2 2006.190.07:49:28.81#ibcon#read 3, iclass 4, count 2 2006.190.07:49:28.81#ibcon#about to read 4, iclass 4, count 2 2006.190.07:49:28.81#ibcon#read 4, iclass 4, count 2 2006.190.07:49:28.81#ibcon#about to read 5, iclass 4, count 2 2006.190.07:49:28.81#ibcon#read 5, iclass 4, count 2 2006.190.07:49:28.81#ibcon#about to read 6, iclass 4, count 2 2006.190.07:49:28.81#ibcon#read 6, iclass 4, count 2 2006.190.07:49:28.81#ibcon#end of sib2, iclass 4, count 2 2006.190.07:49:28.81#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:49:28.81#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:49:28.81#ibcon#[25=AT03-06\r\n] 2006.190.07:49:28.81#ibcon#*before write, iclass 4, count 2 2006.190.07:49:28.81#ibcon#enter sib2, iclass 4, count 2 2006.190.07:49:28.81#ibcon#flushed, iclass 4, count 2 2006.190.07:49:28.81#ibcon#about to write, iclass 4, count 2 2006.190.07:49:28.81#ibcon#wrote, iclass 4, count 2 2006.190.07:49:28.81#ibcon#about to read 3, iclass 4, count 2 2006.190.07:49:28.84#ibcon#read 3, iclass 4, count 2 2006.190.07:49:28.84#ibcon#about to read 4, iclass 4, count 2 2006.190.07:49:28.84#ibcon#read 4, iclass 4, count 2 2006.190.07:49:28.84#ibcon#about to read 5, iclass 4, count 2 2006.190.07:49:28.84#ibcon#read 5, iclass 4, count 2 2006.190.07:49:28.84#ibcon#about to read 6, iclass 4, count 2 2006.190.07:49:28.84#ibcon#read 6, iclass 4, count 2 2006.190.07:49:28.84#ibcon#end of sib2, iclass 4, count 2 2006.190.07:49:28.84#ibcon#*after write, iclass 4, count 2 2006.190.07:49:28.84#ibcon#*before return 0, iclass 4, count 2 2006.190.07:49:28.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:28.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:28.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:49:28.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:28.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:28.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:28.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:28.96#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:49:28.96#ibcon#first serial, iclass 4, count 0 2006.190.07:49:28.96#ibcon#enter sib2, iclass 4, count 0 2006.190.07:49:28.96#ibcon#flushed, iclass 4, count 0 2006.190.07:49:28.96#ibcon#about to write, iclass 4, count 0 2006.190.07:49:28.96#ibcon#wrote, iclass 4, count 0 2006.190.07:49:28.96#ibcon#about to read 3, iclass 4, count 0 2006.190.07:49:28.98#ibcon#read 3, iclass 4, count 0 2006.190.07:49:28.98#ibcon#about to read 4, iclass 4, count 0 2006.190.07:49:28.98#ibcon#read 4, iclass 4, count 0 2006.190.07:49:28.98#ibcon#about to read 5, iclass 4, count 0 2006.190.07:49:28.98#ibcon#read 5, iclass 4, count 0 2006.190.07:49:28.98#ibcon#about to read 6, iclass 4, count 0 2006.190.07:49:28.98#ibcon#read 6, iclass 4, count 0 2006.190.07:49:28.98#ibcon#end of sib2, iclass 4, count 0 2006.190.07:49:28.98#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:49:28.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:49:28.98#ibcon#[25=USB\r\n] 2006.190.07:49:28.98#ibcon#*before write, iclass 4, count 0 2006.190.07:49:28.98#ibcon#enter sib2, iclass 4, count 0 2006.190.07:49:28.98#ibcon#flushed, iclass 4, count 0 2006.190.07:49:28.98#ibcon#about to write, iclass 4, count 0 2006.190.07:49:28.98#ibcon#wrote, iclass 4, count 0 2006.190.07:49:28.98#ibcon#about to read 3, iclass 4, count 0 2006.190.07:49:29.01#ibcon#read 3, iclass 4, count 0 2006.190.07:49:29.01#ibcon#about to read 4, iclass 4, count 0 2006.190.07:49:29.01#ibcon#read 4, iclass 4, count 0 2006.190.07:49:29.01#ibcon#about to read 5, iclass 4, count 0 2006.190.07:49:29.01#ibcon#read 5, iclass 4, count 0 2006.190.07:49:29.01#ibcon#about to read 6, iclass 4, count 0 2006.190.07:49:29.01#ibcon#read 6, iclass 4, count 0 2006.190.07:49:29.01#ibcon#end of sib2, iclass 4, count 0 2006.190.07:49:29.01#ibcon#*after write, iclass 4, count 0 2006.190.07:49:29.01#ibcon#*before return 0, iclass 4, count 0 2006.190.07:49:29.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:29.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:29.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:49:29.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:49:29.01$vc4f8/valo=4,832.99 2006.190.07:49:29.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:49:29.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:49:29.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:29.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:29.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:29.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:29.01#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:49:29.01#ibcon#first serial, iclass 6, count 0 2006.190.07:49:29.01#ibcon#enter sib2, iclass 6, count 0 2006.190.07:49:29.01#ibcon#flushed, iclass 6, count 0 2006.190.07:49:29.01#ibcon#about to write, iclass 6, count 0 2006.190.07:49:29.01#ibcon#wrote, iclass 6, count 0 2006.190.07:49:29.01#ibcon#about to read 3, iclass 6, count 0 2006.190.07:49:29.03#ibcon#read 3, iclass 6, count 0 2006.190.07:49:29.03#ibcon#about to read 4, iclass 6, count 0 2006.190.07:49:29.03#ibcon#read 4, iclass 6, count 0 2006.190.07:49:29.03#ibcon#about to read 5, iclass 6, count 0 2006.190.07:49:29.03#ibcon#read 5, iclass 6, count 0 2006.190.07:49:29.03#ibcon#about to read 6, iclass 6, count 0 2006.190.07:49:29.03#ibcon#read 6, iclass 6, count 0 2006.190.07:49:29.03#ibcon#end of sib2, iclass 6, count 0 2006.190.07:49:29.03#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:49:29.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:49:29.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:49:29.03#ibcon#*before write, iclass 6, count 0 2006.190.07:49:29.03#ibcon#enter sib2, iclass 6, count 0 2006.190.07:49:29.03#ibcon#flushed, iclass 6, count 0 2006.190.07:49:29.03#ibcon#about to write, iclass 6, count 0 2006.190.07:49:29.03#ibcon#wrote, iclass 6, count 0 2006.190.07:49:29.03#ibcon#about to read 3, iclass 6, count 0 2006.190.07:49:29.07#ibcon#read 3, iclass 6, count 0 2006.190.07:49:29.07#ibcon#about to read 4, iclass 6, count 0 2006.190.07:49:29.07#ibcon#read 4, iclass 6, count 0 2006.190.07:49:29.07#ibcon#about to read 5, iclass 6, count 0 2006.190.07:49:29.07#ibcon#read 5, iclass 6, count 0 2006.190.07:49:29.07#ibcon#about to read 6, iclass 6, count 0 2006.190.07:49:29.07#ibcon#read 6, iclass 6, count 0 2006.190.07:49:29.07#ibcon#end of sib2, iclass 6, count 0 2006.190.07:49:29.07#ibcon#*after write, iclass 6, count 0 2006.190.07:49:29.07#ibcon#*before return 0, iclass 6, count 0 2006.190.07:49:29.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:29.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:29.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:49:29.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:49:29.07$vc4f8/va=4,7 2006.190.07:49:29.07#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:49:29.07#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:49:29.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:29.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:29.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:29.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:29.13#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:49:29.13#ibcon#first serial, iclass 10, count 2 2006.190.07:49:29.13#ibcon#enter sib2, iclass 10, count 2 2006.190.07:49:29.13#ibcon#flushed, iclass 10, count 2 2006.190.07:49:29.13#ibcon#about to write, iclass 10, count 2 2006.190.07:49:29.13#ibcon#wrote, iclass 10, count 2 2006.190.07:49:29.13#ibcon#about to read 3, iclass 10, count 2 2006.190.07:49:29.15#ibcon#read 3, iclass 10, count 2 2006.190.07:49:29.15#ibcon#about to read 4, iclass 10, count 2 2006.190.07:49:29.15#ibcon#read 4, iclass 10, count 2 2006.190.07:49:29.15#ibcon#about to read 5, iclass 10, count 2 2006.190.07:49:29.15#ibcon#read 5, iclass 10, count 2 2006.190.07:49:29.15#ibcon#about to read 6, iclass 10, count 2 2006.190.07:49:29.15#ibcon#read 6, iclass 10, count 2 2006.190.07:49:29.15#ibcon#end of sib2, iclass 10, count 2 2006.190.07:49:29.15#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:49:29.15#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:49:29.15#ibcon#[25=AT04-07\r\n] 2006.190.07:49:29.15#ibcon#*before write, iclass 10, count 2 2006.190.07:49:29.15#ibcon#enter sib2, iclass 10, count 2 2006.190.07:49:29.15#ibcon#flushed, iclass 10, count 2 2006.190.07:49:29.15#ibcon#about to write, iclass 10, count 2 2006.190.07:49:29.15#ibcon#wrote, iclass 10, count 2 2006.190.07:49:29.15#ibcon#about to read 3, iclass 10, count 2 2006.190.07:49:29.18#ibcon#read 3, iclass 10, count 2 2006.190.07:49:29.18#ibcon#about to read 4, iclass 10, count 2 2006.190.07:49:29.18#ibcon#read 4, iclass 10, count 2 2006.190.07:49:29.18#ibcon#about to read 5, iclass 10, count 2 2006.190.07:49:29.18#ibcon#read 5, iclass 10, count 2 2006.190.07:49:29.18#ibcon#about to read 6, iclass 10, count 2 2006.190.07:49:29.18#ibcon#read 6, iclass 10, count 2 2006.190.07:49:29.18#ibcon#end of sib2, iclass 10, count 2 2006.190.07:49:29.18#ibcon#*after write, iclass 10, count 2 2006.190.07:49:29.18#ibcon#*before return 0, iclass 10, count 2 2006.190.07:49:29.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:29.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:29.18#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:49:29.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:29.18#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:29.30#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:29.30#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:29.30#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:49:29.30#ibcon#first serial, iclass 10, count 0 2006.190.07:49:29.30#ibcon#enter sib2, iclass 10, count 0 2006.190.07:49:29.30#ibcon#flushed, iclass 10, count 0 2006.190.07:49:29.30#ibcon#about to write, iclass 10, count 0 2006.190.07:49:29.30#ibcon#wrote, iclass 10, count 0 2006.190.07:49:29.30#ibcon#about to read 3, iclass 10, count 0 2006.190.07:49:29.32#ibcon#read 3, iclass 10, count 0 2006.190.07:49:29.32#ibcon#about to read 4, iclass 10, count 0 2006.190.07:49:29.32#ibcon#read 4, iclass 10, count 0 2006.190.07:49:29.32#ibcon#about to read 5, iclass 10, count 0 2006.190.07:49:29.32#ibcon#read 5, iclass 10, count 0 2006.190.07:49:29.32#ibcon#about to read 6, iclass 10, count 0 2006.190.07:49:29.32#ibcon#read 6, iclass 10, count 0 2006.190.07:49:29.32#ibcon#end of sib2, iclass 10, count 0 2006.190.07:49:29.32#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:49:29.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:49:29.32#ibcon#[25=USB\r\n] 2006.190.07:49:29.32#ibcon#*before write, iclass 10, count 0 2006.190.07:49:29.32#ibcon#enter sib2, iclass 10, count 0 2006.190.07:49:29.32#ibcon#flushed, iclass 10, count 0 2006.190.07:49:29.32#ibcon#about to write, iclass 10, count 0 2006.190.07:49:29.32#ibcon#wrote, iclass 10, count 0 2006.190.07:49:29.32#ibcon#about to read 3, iclass 10, count 0 2006.190.07:49:29.35#ibcon#read 3, iclass 10, count 0 2006.190.07:49:29.35#ibcon#about to read 4, iclass 10, count 0 2006.190.07:49:29.35#ibcon#read 4, iclass 10, count 0 2006.190.07:49:29.35#ibcon#about to read 5, iclass 10, count 0 2006.190.07:49:29.35#ibcon#read 5, iclass 10, count 0 2006.190.07:49:29.35#ibcon#about to read 6, iclass 10, count 0 2006.190.07:49:29.35#ibcon#read 6, iclass 10, count 0 2006.190.07:49:29.35#ibcon#end of sib2, iclass 10, count 0 2006.190.07:49:29.35#ibcon#*after write, iclass 10, count 0 2006.190.07:49:29.35#ibcon#*before return 0, iclass 10, count 0 2006.190.07:49:29.35#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:29.35#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:29.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:49:29.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:49:29.35$vc4f8/valo=5,652.99 2006.190.07:49:29.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:49:29.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:49:29.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:29.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:29.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:29.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:29.35#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:49:29.35#ibcon#first serial, iclass 12, count 0 2006.190.07:49:29.35#ibcon#enter sib2, iclass 12, count 0 2006.190.07:49:29.35#ibcon#flushed, iclass 12, count 0 2006.190.07:49:29.35#ibcon#about to write, iclass 12, count 0 2006.190.07:49:29.35#ibcon#wrote, iclass 12, count 0 2006.190.07:49:29.35#ibcon#about to read 3, iclass 12, count 0 2006.190.07:49:29.37#ibcon#read 3, iclass 12, count 0 2006.190.07:49:29.37#ibcon#about to read 4, iclass 12, count 0 2006.190.07:49:29.37#ibcon#read 4, iclass 12, count 0 2006.190.07:49:29.37#ibcon#about to read 5, iclass 12, count 0 2006.190.07:49:29.37#ibcon#read 5, iclass 12, count 0 2006.190.07:49:29.37#ibcon#about to read 6, iclass 12, count 0 2006.190.07:49:29.37#ibcon#read 6, iclass 12, count 0 2006.190.07:49:29.37#ibcon#end of sib2, iclass 12, count 0 2006.190.07:49:29.37#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:49:29.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:49:29.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:49:29.37#ibcon#*before write, iclass 12, count 0 2006.190.07:49:29.37#ibcon#enter sib2, iclass 12, count 0 2006.190.07:49:29.37#ibcon#flushed, iclass 12, count 0 2006.190.07:49:29.37#ibcon#about to write, iclass 12, count 0 2006.190.07:49:29.37#ibcon#wrote, iclass 12, count 0 2006.190.07:49:29.37#ibcon#about to read 3, iclass 12, count 0 2006.190.07:49:29.41#ibcon#read 3, iclass 12, count 0 2006.190.07:49:29.41#ibcon#about to read 4, iclass 12, count 0 2006.190.07:49:29.41#ibcon#read 4, iclass 12, count 0 2006.190.07:49:29.41#ibcon#about to read 5, iclass 12, count 0 2006.190.07:49:29.41#ibcon#read 5, iclass 12, count 0 2006.190.07:49:29.41#ibcon#about to read 6, iclass 12, count 0 2006.190.07:49:29.41#ibcon#read 6, iclass 12, count 0 2006.190.07:49:29.41#ibcon#end of sib2, iclass 12, count 0 2006.190.07:49:29.41#ibcon#*after write, iclass 12, count 0 2006.190.07:49:29.41#ibcon#*before return 0, iclass 12, count 0 2006.190.07:49:29.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:29.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:29.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:49:29.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:49:29.41$vc4f8/va=5,7 2006.190.07:49:29.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:49:29.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:49:29.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:29.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:29.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:29.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:29.47#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:49:29.47#ibcon#first serial, iclass 14, count 2 2006.190.07:49:29.47#ibcon#enter sib2, iclass 14, count 2 2006.190.07:49:29.47#ibcon#flushed, iclass 14, count 2 2006.190.07:49:29.47#ibcon#about to write, iclass 14, count 2 2006.190.07:49:29.47#ibcon#wrote, iclass 14, count 2 2006.190.07:49:29.47#ibcon#about to read 3, iclass 14, count 2 2006.190.07:49:29.49#ibcon#read 3, iclass 14, count 2 2006.190.07:49:29.49#ibcon#about to read 4, iclass 14, count 2 2006.190.07:49:29.49#ibcon#read 4, iclass 14, count 2 2006.190.07:49:29.49#ibcon#about to read 5, iclass 14, count 2 2006.190.07:49:29.49#ibcon#read 5, iclass 14, count 2 2006.190.07:49:29.49#ibcon#about to read 6, iclass 14, count 2 2006.190.07:49:29.49#ibcon#read 6, iclass 14, count 2 2006.190.07:49:29.49#ibcon#end of sib2, iclass 14, count 2 2006.190.07:49:29.49#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:49:29.49#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:49:29.49#ibcon#[25=AT05-07\r\n] 2006.190.07:49:29.49#ibcon#*before write, iclass 14, count 2 2006.190.07:49:29.49#ibcon#enter sib2, iclass 14, count 2 2006.190.07:49:29.49#ibcon#flushed, iclass 14, count 2 2006.190.07:49:29.49#ibcon#about to write, iclass 14, count 2 2006.190.07:49:29.49#ibcon#wrote, iclass 14, count 2 2006.190.07:49:29.49#ibcon#about to read 3, iclass 14, count 2 2006.190.07:49:29.52#ibcon#read 3, iclass 14, count 2 2006.190.07:49:29.52#ibcon#about to read 4, iclass 14, count 2 2006.190.07:49:29.52#ibcon#read 4, iclass 14, count 2 2006.190.07:49:29.52#ibcon#about to read 5, iclass 14, count 2 2006.190.07:49:29.52#ibcon#read 5, iclass 14, count 2 2006.190.07:49:29.52#ibcon#about to read 6, iclass 14, count 2 2006.190.07:49:29.52#ibcon#read 6, iclass 14, count 2 2006.190.07:49:29.52#ibcon#end of sib2, iclass 14, count 2 2006.190.07:49:29.52#ibcon#*after write, iclass 14, count 2 2006.190.07:49:29.52#ibcon#*before return 0, iclass 14, count 2 2006.190.07:49:29.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:29.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:29.52#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:49:29.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:29.52#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:29.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:29.64#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:29.64#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:49:29.64#ibcon#first serial, iclass 14, count 0 2006.190.07:49:29.64#ibcon#enter sib2, iclass 14, count 0 2006.190.07:49:29.64#ibcon#flushed, iclass 14, count 0 2006.190.07:49:29.64#ibcon#about to write, iclass 14, count 0 2006.190.07:49:29.64#ibcon#wrote, iclass 14, count 0 2006.190.07:49:29.64#ibcon#about to read 3, iclass 14, count 0 2006.190.07:49:29.66#ibcon#read 3, iclass 14, count 0 2006.190.07:49:29.66#ibcon#about to read 4, iclass 14, count 0 2006.190.07:49:29.66#ibcon#read 4, iclass 14, count 0 2006.190.07:49:29.66#ibcon#about to read 5, iclass 14, count 0 2006.190.07:49:29.66#ibcon#read 5, iclass 14, count 0 2006.190.07:49:29.66#ibcon#about to read 6, iclass 14, count 0 2006.190.07:49:29.66#ibcon#read 6, iclass 14, count 0 2006.190.07:49:29.66#ibcon#end of sib2, iclass 14, count 0 2006.190.07:49:29.66#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:49:29.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:49:29.66#ibcon#[25=USB\r\n] 2006.190.07:49:29.66#ibcon#*before write, iclass 14, count 0 2006.190.07:49:29.66#ibcon#enter sib2, iclass 14, count 0 2006.190.07:49:29.66#ibcon#flushed, iclass 14, count 0 2006.190.07:49:29.66#ibcon#about to write, iclass 14, count 0 2006.190.07:49:29.66#ibcon#wrote, iclass 14, count 0 2006.190.07:49:29.66#ibcon#about to read 3, iclass 14, count 0 2006.190.07:49:29.69#ibcon#read 3, iclass 14, count 0 2006.190.07:49:29.69#ibcon#about to read 4, iclass 14, count 0 2006.190.07:49:29.69#ibcon#read 4, iclass 14, count 0 2006.190.07:49:29.69#ibcon#about to read 5, iclass 14, count 0 2006.190.07:49:29.69#ibcon#read 5, iclass 14, count 0 2006.190.07:49:29.69#ibcon#about to read 6, iclass 14, count 0 2006.190.07:49:29.69#ibcon#read 6, iclass 14, count 0 2006.190.07:49:29.69#ibcon#end of sib2, iclass 14, count 0 2006.190.07:49:29.69#ibcon#*after write, iclass 14, count 0 2006.190.07:49:29.69#ibcon#*before return 0, iclass 14, count 0 2006.190.07:49:29.69#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:29.69#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:29.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:49:29.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:49:29.69$vc4f8/valo=6,772.99 2006.190.07:49:29.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:49:29.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:49:29.69#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:29.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:29.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:29.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:29.69#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:49:29.69#ibcon#first serial, iclass 16, count 0 2006.190.07:49:29.69#ibcon#enter sib2, iclass 16, count 0 2006.190.07:49:29.69#ibcon#flushed, iclass 16, count 0 2006.190.07:49:29.69#ibcon#about to write, iclass 16, count 0 2006.190.07:49:29.69#ibcon#wrote, iclass 16, count 0 2006.190.07:49:29.69#ibcon#about to read 3, iclass 16, count 0 2006.190.07:49:29.71#ibcon#read 3, iclass 16, count 0 2006.190.07:49:29.71#ibcon#about to read 4, iclass 16, count 0 2006.190.07:49:29.71#ibcon#read 4, iclass 16, count 0 2006.190.07:49:29.71#ibcon#about to read 5, iclass 16, count 0 2006.190.07:49:29.71#ibcon#read 5, iclass 16, count 0 2006.190.07:49:29.71#ibcon#about to read 6, iclass 16, count 0 2006.190.07:49:29.71#ibcon#read 6, iclass 16, count 0 2006.190.07:49:29.71#ibcon#end of sib2, iclass 16, count 0 2006.190.07:49:29.71#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:49:29.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:49:29.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:49:29.71#ibcon#*before write, iclass 16, count 0 2006.190.07:49:29.71#ibcon#enter sib2, iclass 16, count 0 2006.190.07:49:29.71#ibcon#flushed, iclass 16, count 0 2006.190.07:49:29.71#ibcon#about to write, iclass 16, count 0 2006.190.07:49:29.71#ibcon#wrote, iclass 16, count 0 2006.190.07:49:29.71#ibcon#about to read 3, iclass 16, count 0 2006.190.07:49:29.75#ibcon#read 3, iclass 16, count 0 2006.190.07:49:29.75#ibcon#about to read 4, iclass 16, count 0 2006.190.07:49:29.75#ibcon#read 4, iclass 16, count 0 2006.190.07:49:29.75#ibcon#about to read 5, iclass 16, count 0 2006.190.07:49:29.75#ibcon#read 5, iclass 16, count 0 2006.190.07:49:29.75#ibcon#about to read 6, iclass 16, count 0 2006.190.07:49:29.75#ibcon#read 6, iclass 16, count 0 2006.190.07:49:29.75#ibcon#end of sib2, iclass 16, count 0 2006.190.07:49:29.75#ibcon#*after write, iclass 16, count 0 2006.190.07:49:29.75#ibcon#*before return 0, iclass 16, count 0 2006.190.07:49:29.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:29.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:29.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:49:29.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:49:29.75$vc4f8/va=6,6 2006.190.07:49:29.75#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.07:49:29.75#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.07:49:29.75#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:29.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:49:29.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:49:29.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:49:29.81#ibcon#enter wrdev, iclass 18, count 2 2006.190.07:49:29.81#ibcon#first serial, iclass 18, count 2 2006.190.07:49:29.81#ibcon#enter sib2, iclass 18, count 2 2006.190.07:49:29.81#ibcon#flushed, iclass 18, count 2 2006.190.07:49:29.81#ibcon#about to write, iclass 18, count 2 2006.190.07:49:29.81#ibcon#wrote, iclass 18, count 2 2006.190.07:49:29.81#ibcon#about to read 3, iclass 18, count 2 2006.190.07:49:29.83#ibcon#read 3, iclass 18, count 2 2006.190.07:49:29.83#ibcon#about to read 4, iclass 18, count 2 2006.190.07:49:29.83#ibcon#read 4, iclass 18, count 2 2006.190.07:49:29.83#ibcon#about to read 5, iclass 18, count 2 2006.190.07:49:29.83#ibcon#read 5, iclass 18, count 2 2006.190.07:49:29.83#ibcon#about to read 6, iclass 18, count 2 2006.190.07:49:29.83#ibcon#read 6, iclass 18, count 2 2006.190.07:49:29.83#ibcon#end of sib2, iclass 18, count 2 2006.190.07:49:29.83#ibcon#*mode == 0, iclass 18, count 2 2006.190.07:49:29.83#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.07:49:29.83#ibcon#[25=AT06-06\r\n] 2006.190.07:49:29.83#ibcon#*before write, iclass 18, count 2 2006.190.07:49:29.83#ibcon#enter sib2, iclass 18, count 2 2006.190.07:49:29.83#ibcon#flushed, iclass 18, count 2 2006.190.07:49:29.83#ibcon#about to write, iclass 18, count 2 2006.190.07:49:29.83#ibcon#wrote, iclass 18, count 2 2006.190.07:49:29.83#ibcon#about to read 3, iclass 18, count 2 2006.190.07:49:29.86#ibcon#read 3, iclass 18, count 2 2006.190.07:49:29.86#ibcon#about to read 4, iclass 18, count 2 2006.190.07:49:29.86#ibcon#read 4, iclass 18, count 2 2006.190.07:49:29.86#ibcon#about to read 5, iclass 18, count 2 2006.190.07:49:29.86#ibcon#read 5, iclass 18, count 2 2006.190.07:49:29.86#ibcon#about to read 6, iclass 18, count 2 2006.190.07:49:29.86#ibcon#read 6, iclass 18, count 2 2006.190.07:49:29.86#ibcon#end of sib2, iclass 18, count 2 2006.190.07:49:29.86#ibcon#*after write, iclass 18, count 2 2006.190.07:49:29.86#ibcon#*before return 0, iclass 18, count 2 2006.190.07:49:29.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:49:29.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:49:29.86#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.07:49:29.86#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:29.86#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:49:29.98#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:49:29.98#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:49:29.98#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:49:29.98#ibcon#first serial, iclass 18, count 0 2006.190.07:49:29.98#ibcon#enter sib2, iclass 18, count 0 2006.190.07:49:29.98#ibcon#flushed, iclass 18, count 0 2006.190.07:49:29.98#ibcon#about to write, iclass 18, count 0 2006.190.07:49:29.98#ibcon#wrote, iclass 18, count 0 2006.190.07:49:29.98#ibcon#about to read 3, iclass 18, count 0 2006.190.07:49:30.00#ibcon#read 3, iclass 18, count 0 2006.190.07:49:30.00#ibcon#about to read 4, iclass 18, count 0 2006.190.07:49:30.00#ibcon#read 4, iclass 18, count 0 2006.190.07:49:30.00#ibcon#about to read 5, iclass 18, count 0 2006.190.07:49:30.00#ibcon#read 5, iclass 18, count 0 2006.190.07:49:30.00#ibcon#about to read 6, iclass 18, count 0 2006.190.07:49:30.00#ibcon#read 6, iclass 18, count 0 2006.190.07:49:30.00#ibcon#end of sib2, iclass 18, count 0 2006.190.07:49:30.00#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:49:30.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:49:30.00#ibcon#[25=USB\r\n] 2006.190.07:49:30.00#ibcon#*before write, iclass 18, count 0 2006.190.07:49:30.00#ibcon#enter sib2, iclass 18, count 0 2006.190.07:49:30.00#ibcon#flushed, iclass 18, count 0 2006.190.07:49:30.00#ibcon#about to write, iclass 18, count 0 2006.190.07:49:30.00#ibcon#wrote, iclass 18, count 0 2006.190.07:49:30.00#ibcon#about to read 3, iclass 18, count 0 2006.190.07:49:30.03#ibcon#read 3, iclass 18, count 0 2006.190.07:49:30.03#ibcon#about to read 4, iclass 18, count 0 2006.190.07:49:30.03#ibcon#read 4, iclass 18, count 0 2006.190.07:49:30.03#ibcon#about to read 5, iclass 18, count 0 2006.190.07:49:30.03#ibcon#read 5, iclass 18, count 0 2006.190.07:49:30.03#ibcon#about to read 6, iclass 18, count 0 2006.190.07:49:30.03#ibcon#read 6, iclass 18, count 0 2006.190.07:49:30.03#ibcon#end of sib2, iclass 18, count 0 2006.190.07:49:30.03#ibcon#*after write, iclass 18, count 0 2006.190.07:49:30.03#ibcon#*before return 0, iclass 18, count 0 2006.190.07:49:30.03#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:49:30.03#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:49:30.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:49:30.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:49:30.03$vc4f8/valo=7,832.99 2006.190.07:49:30.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:49:30.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:49:30.03#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:30.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:49:30.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:49:30.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:49:30.03#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:49:30.03#ibcon#first serial, iclass 20, count 0 2006.190.07:49:30.03#ibcon#enter sib2, iclass 20, count 0 2006.190.07:49:30.03#ibcon#flushed, iclass 20, count 0 2006.190.07:49:30.03#ibcon#about to write, iclass 20, count 0 2006.190.07:49:30.03#ibcon#wrote, iclass 20, count 0 2006.190.07:49:30.03#ibcon#about to read 3, iclass 20, count 0 2006.190.07:49:30.05#ibcon#read 3, iclass 20, count 0 2006.190.07:49:30.05#ibcon#about to read 4, iclass 20, count 0 2006.190.07:49:30.05#ibcon#read 4, iclass 20, count 0 2006.190.07:49:30.05#ibcon#about to read 5, iclass 20, count 0 2006.190.07:49:30.05#ibcon#read 5, iclass 20, count 0 2006.190.07:49:30.05#ibcon#about to read 6, iclass 20, count 0 2006.190.07:49:30.05#ibcon#read 6, iclass 20, count 0 2006.190.07:49:30.05#ibcon#end of sib2, iclass 20, count 0 2006.190.07:49:30.05#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:49:30.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:49:30.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:49:30.05#ibcon#*before write, iclass 20, count 0 2006.190.07:49:30.05#ibcon#enter sib2, iclass 20, count 0 2006.190.07:49:30.05#ibcon#flushed, iclass 20, count 0 2006.190.07:49:30.05#ibcon#about to write, iclass 20, count 0 2006.190.07:49:30.05#ibcon#wrote, iclass 20, count 0 2006.190.07:49:30.05#ibcon#about to read 3, iclass 20, count 0 2006.190.07:49:30.09#ibcon#read 3, iclass 20, count 0 2006.190.07:49:30.09#ibcon#about to read 4, iclass 20, count 0 2006.190.07:49:30.09#ibcon#read 4, iclass 20, count 0 2006.190.07:49:30.09#ibcon#about to read 5, iclass 20, count 0 2006.190.07:49:30.09#ibcon#read 5, iclass 20, count 0 2006.190.07:49:30.09#ibcon#about to read 6, iclass 20, count 0 2006.190.07:49:30.09#ibcon#read 6, iclass 20, count 0 2006.190.07:49:30.09#ibcon#end of sib2, iclass 20, count 0 2006.190.07:49:30.09#ibcon#*after write, iclass 20, count 0 2006.190.07:49:30.09#ibcon#*before return 0, iclass 20, count 0 2006.190.07:49:30.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:49:30.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:49:30.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:49:30.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:49:30.09$vc4f8/va=7,6 2006.190.07:49:30.09#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:49:30.09#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:49:30.09#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:30.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:49:30.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:49:30.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:49:30.15#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:49:30.15#ibcon#first serial, iclass 22, count 2 2006.190.07:49:30.15#ibcon#enter sib2, iclass 22, count 2 2006.190.07:49:30.15#ibcon#flushed, iclass 22, count 2 2006.190.07:49:30.15#ibcon#about to write, iclass 22, count 2 2006.190.07:49:30.15#ibcon#wrote, iclass 22, count 2 2006.190.07:49:30.15#ibcon#about to read 3, iclass 22, count 2 2006.190.07:49:30.17#ibcon#read 3, iclass 22, count 2 2006.190.07:49:30.17#ibcon#about to read 4, iclass 22, count 2 2006.190.07:49:30.17#ibcon#read 4, iclass 22, count 2 2006.190.07:49:30.17#ibcon#about to read 5, iclass 22, count 2 2006.190.07:49:30.17#ibcon#read 5, iclass 22, count 2 2006.190.07:49:30.17#ibcon#about to read 6, iclass 22, count 2 2006.190.07:49:30.17#ibcon#read 6, iclass 22, count 2 2006.190.07:49:30.17#ibcon#end of sib2, iclass 22, count 2 2006.190.07:49:30.17#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:49:30.17#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:49:30.17#ibcon#[25=AT07-06\r\n] 2006.190.07:49:30.17#ibcon#*before write, iclass 22, count 2 2006.190.07:49:30.17#ibcon#enter sib2, iclass 22, count 2 2006.190.07:49:30.17#ibcon#flushed, iclass 22, count 2 2006.190.07:49:30.17#ibcon#about to write, iclass 22, count 2 2006.190.07:49:30.17#ibcon#wrote, iclass 22, count 2 2006.190.07:49:30.17#ibcon#about to read 3, iclass 22, count 2 2006.190.07:49:30.20#ibcon#read 3, iclass 22, count 2 2006.190.07:49:30.20#ibcon#about to read 4, iclass 22, count 2 2006.190.07:49:30.20#ibcon#read 4, iclass 22, count 2 2006.190.07:49:30.20#ibcon#about to read 5, iclass 22, count 2 2006.190.07:49:30.20#ibcon#read 5, iclass 22, count 2 2006.190.07:49:30.20#ibcon#about to read 6, iclass 22, count 2 2006.190.07:49:30.20#ibcon#read 6, iclass 22, count 2 2006.190.07:49:30.20#ibcon#end of sib2, iclass 22, count 2 2006.190.07:49:30.20#ibcon#*after write, iclass 22, count 2 2006.190.07:49:30.20#ibcon#*before return 0, iclass 22, count 2 2006.190.07:49:30.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:49:30.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:49:30.20#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:49:30.20#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:30.20#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:49:30.32#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:49:30.32#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:49:30.32#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:49:30.32#ibcon#first serial, iclass 22, count 0 2006.190.07:49:30.32#ibcon#enter sib2, iclass 22, count 0 2006.190.07:49:30.32#ibcon#flushed, iclass 22, count 0 2006.190.07:49:30.32#ibcon#about to write, iclass 22, count 0 2006.190.07:49:30.32#ibcon#wrote, iclass 22, count 0 2006.190.07:49:30.32#ibcon#about to read 3, iclass 22, count 0 2006.190.07:49:30.34#ibcon#read 3, iclass 22, count 0 2006.190.07:49:30.34#ibcon#about to read 4, iclass 22, count 0 2006.190.07:49:30.34#ibcon#read 4, iclass 22, count 0 2006.190.07:49:30.34#ibcon#about to read 5, iclass 22, count 0 2006.190.07:49:30.34#ibcon#read 5, iclass 22, count 0 2006.190.07:49:30.34#ibcon#about to read 6, iclass 22, count 0 2006.190.07:49:30.34#ibcon#read 6, iclass 22, count 0 2006.190.07:49:30.34#ibcon#end of sib2, iclass 22, count 0 2006.190.07:49:30.34#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:49:30.34#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:49:30.34#ibcon#[25=USB\r\n] 2006.190.07:49:30.34#ibcon#*before write, iclass 22, count 0 2006.190.07:49:30.34#ibcon#enter sib2, iclass 22, count 0 2006.190.07:49:30.34#ibcon#flushed, iclass 22, count 0 2006.190.07:49:30.34#ibcon#about to write, iclass 22, count 0 2006.190.07:49:30.34#ibcon#wrote, iclass 22, count 0 2006.190.07:49:30.34#ibcon#about to read 3, iclass 22, count 0 2006.190.07:49:30.37#ibcon#read 3, iclass 22, count 0 2006.190.07:49:30.37#ibcon#about to read 4, iclass 22, count 0 2006.190.07:49:30.37#ibcon#read 4, iclass 22, count 0 2006.190.07:49:30.37#ibcon#about to read 5, iclass 22, count 0 2006.190.07:49:30.37#ibcon#read 5, iclass 22, count 0 2006.190.07:49:30.37#ibcon#about to read 6, iclass 22, count 0 2006.190.07:49:30.37#ibcon#read 6, iclass 22, count 0 2006.190.07:49:30.37#ibcon#end of sib2, iclass 22, count 0 2006.190.07:49:30.37#ibcon#*after write, iclass 22, count 0 2006.190.07:49:30.37#ibcon#*before return 0, iclass 22, count 0 2006.190.07:49:30.37#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:49:30.37#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:49:30.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:49:30.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:49:30.37$vc4f8/valo=8,852.99 2006.190.07:49:30.37#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.07:49:30.37#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.07:49:30.37#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:30.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:49:30.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:49:30.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:49:30.37#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:49:30.37#ibcon#first serial, iclass 24, count 0 2006.190.07:49:30.37#ibcon#enter sib2, iclass 24, count 0 2006.190.07:49:30.37#ibcon#flushed, iclass 24, count 0 2006.190.07:49:30.37#ibcon#about to write, iclass 24, count 0 2006.190.07:49:30.37#ibcon#wrote, iclass 24, count 0 2006.190.07:49:30.37#ibcon#about to read 3, iclass 24, count 0 2006.190.07:49:30.39#ibcon#read 3, iclass 24, count 0 2006.190.07:49:30.39#ibcon#about to read 4, iclass 24, count 0 2006.190.07:49:30.39#ibcon#read 4, iclass 24, count 0 2006.190.07:49:30.39#ibcon#about to read 5, iclass 24, count 0 2006.190.07:49:30.39#ibcon#read 5, iclass 24, count 0 2006.190.07:49:30.39#ibcon#about to read 6, iclass 24, count 0 2006.190.07:49:30.39#ibcon#read 6, iclass 24, count 0 2006.190.07:49:30.39#ibcon#end of sib2, iclass 24, count 0 2006.190.07:49:30.39#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:49:30.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:49:30.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:49:30.39#ibcon#*before write, iclass 24, count 0 2006.190.07:49:30.39#ibcon#enter sib2, iclass 24, count 0 2006.190.07:49:30.39#ibcon#flushed, iclass 24, count 0 2006.190.07:49:30.39#ibcon#about to write, iclass 24, count 0 2006.190.07:49:30.39#ibcon#wrote, iclass 24, count 0 2006.190.07:49:30.39#ibcon#about to read 3, iclass 24, count 0 2006.190.07:49:30.43#ibcon#read 3, iclass 24, count 0 2006.190.07:49:30.43#ibcon#about to read 4, iclass 24, count 0 2006.190.07:49:30.43#ibcon#read 4, iclass 24, count 0 2006.190.07:49:30.43#ibcon#about to read 5, iclass 24, count 0 2006.190.07:49:30.43#ibcon#read 5, iclass 24, count 0 2006.190.07:49:30.43#ibcon#about to read 6, iclass 24, count 0 2006.190.07:49:30.43#ibcon#read 6, iclass 24, count 0 2006.190.07:49:30.43#ibcon#end of sib2, iclass 24, count 0 2006.190.07:49:30.43#ibcon#*after write, iclass 24, count 0 2006.190.07:49:30.43#ibcon#*before return 0, iclass 24, count 0 2006.190.07:49:30.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:49:30.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:49:30.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:49:30.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:49:30.43$vc4f8/va=8,6 2006.190.07:49:30.43#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.07:49:30.43#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.07:49:30.43#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:30.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:49:30.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:49:30.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:49:30.49#ibcon#enter wrdev, iclass 26, count 2 2006.190.07:49:30.49#ibcon#first serial, iclass 26, count 2 2006.190.07:49:30.49#ibcon#enter sib2, iclass 26, count 2 2006.190.07:49:30.49#ibcon#flushed, iclass 26, count 2 2006.190.07:49:30.49#ibcon#about to write, iclass 26, count 2 2006.190.07:49:30.49#ibcon#wrote, iclass 26, count 2 2006.190.07:49:30.49#ibcon#about to read 3, iclass 26, count 2 2006.190.07:49:30.51#ibcon#read 3, iclass 26, count 2 2006.190.07:49:30.51#ibcon#about to read 4, iclass 26, count 2 2006.190.07:49:30.51#ibcon#read 4, iclass 26, count 2 2006.190.07:49:30.51#ibcon#about to read 5, iclass 26, count 2 2006.190.07:49:30.51#ibcon#read 5, iclass 26, count 2 2006.190.07:49:30.51#ibcon#about to read 6, iclass 26, count 2 2006.190.07:49:30.51#ibcon#read 6, iclass 26, count 2 2006.190.07:49:30.51#ibcon#end of sib2, iclass 26, count 2 2006.190.07:49:30.51#ibcon#*mode == 0, iclass 26, count 2 2006.190.07:49:30.51#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.07:49:30.51#ibcon#[25=AT08-06\r\n] 2006.190.07:49:30.51#ibcon#*before write, iclass 26, count 2 2006.190.07:49:30.51#ibcon#enter sib2, iclass 26, count 2 2006.190.07:49:30.51#ibcon#flushed, iclass 26, count 2 2006.190.07:49:30.51#ibcon#about to write, iclass 26, count 2 2006.190.07:49:30.51#ibcon#wrote, iclass 26, count 2 2006.190.07:49:30.51#ibcon#about to read 3, iclass 26, count 2 2006.190.07:49:30.54#ibcon#read 3, iclass 26, count 2 2006.190.07:49:30.54#ibcon#about to read 4, iclass 26, count 2 2006.190.07:49:30.54#ibcon#read 4, iclass 26, count 2 2006.190.07:49:30.54#ibcon#about to read 5, iclass 26, count 2 2006.190.07:49:30.54#ibcon#read 5, iclass 26, count 2 2006.190.07:49:30.54#ibcon#about to read 6, iclass 26, count 2 2006.190.07:49:30.54#ibcon#read 6, iclass 26, count 2 2006.190.07:49:30.54#ibcon#end of sib2, iclass 26, count 2 2006.190.07:49:30.54#ibcon#*after write, iclass 26, count 2 2006.190.07:49:30.54#ibcon#*before return 0, iclass 26, count 2 2006.190.07:49:30.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:49:30.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:49:30.54#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.07:49:30.54#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:30.54#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:49:30.66#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:49:30.66#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:49:30.66#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:49:30.66#ibcon#first serial, iclass 26, count 0 2006.190.07:49:30.66#ibcon#enter sib2, iclass 26, count 0 2006.190.07:49:30.66#ibcon#flushed, iclass 26, count 0 2006.190.07:49:30.66#ibcon#about to write, iclass 26, count 0 2006.190.07:49:30.66#ibcon#wrote, iclass 26, count 0 2006.190.07:49:30.66#ibcon#about to read 3, iclass 26, count 0 2006.190.07:49:30.68#ibcon#read 3, iclass 26, count 0 2006.190.07:49:30.68#ibcon#about to read 4, iclass 26, count 0 2006.190.07:49:30.68#ibcon#read 4, iclass 26, count 0 2006.190.07:49:30.68#ibcon#about to read 5, iclass 26, count 0 2006.190.07:49:30.68#ibcon#read 5, iclass 26, count 0 2006.190.07:49:30.68#ibcon#about to read 6, iclass 26, count 0 2006.190.07:49:30.68#ibcon#read 6, iclass 26, count 0 2006.190.07:49:30.68#ibcon#end of sib2, iclass 26, count 0 2006.190.07:49:30.68#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:49:30.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:49:30.68#ibcon#[25=USB\r\n] 2006.190.07:49:30.68#ibcon#*before write, iclass 26, count 0 2006.190.07:49:30.68#ibcon#enter sib2, iclass 26, count 0 2006.190.07:49:30.68#ibcon#flushed, iclass 26, count 0 2006.190.07:49:30.68#ibcon#about to write, iclass 26, count 0 2006.190.07:49:30.68#ibcon#wrote, iclass 26, count 0 2006.190.07:49:30.68#ibcon#about to read 3, iclass 26, count 0 2006.190.07:49:30.71#ibcon#read 3, iclass 26, count 0 2006.190.07:49:30.71#ibcon#about to read 4, iclass 26, count 0 2006.190.07:49:30.71#ibcon#read 4, iclass 26, count 0 2006.190.07:49:30.71#ibcon#about to read 5, iclass 26, count 0 2006.190.07:49:30.71#ibcon#read 5, iclass 26, count 0 2006.190.07:49:30.71#ibcon#about to read 6, iclass 26, count 0 2006.190.07:49:30.71#ibcon#read 6, iclass 26, count 0 2006.190.07:49:30.71#ibcon#end of sib2, iclass 26, count 0 2006.190.07:49:30.71#ibcon#*after write, iclass 26, count 0 2006.190.07:49:30.71#ibcon#*before return 0, iclass 26, count 0 2006.190.07:49:30.71#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:49:30.71#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:49:30.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:49:30.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:49:30.71$vc4f8/vblo=1,632.99 2006.190.07:49:30.71#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:49:30.71#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:49:30.71#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:30.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:49:30.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:49:30.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:49:30.71#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:49:30.71#ibcon#first serial, iclass 28, count 0 2006.190.07:49:30.71#ibcon#enter sib2, iclass 28, count 0 2006.190.07:49:30.71#ibcon#flushed, iclass 28, count 0 2006.190.07:49:30.71#ibcon#about to write, iclass 28, count 0 2006.190.07:49:30.71#ibcon#wrote, iclass 28, count 0 2006.190.07:49:30.71#ibcon#about to read 3, iclass 28, count 0 2006.190.07:49:30.73#ibcon#read 3, iclass 28, count 0 2006.190.07:49:30.73#ibcon#about to read 4, iclass 28, count 0 2006.190.07:49:30.73#ibcon#read 4, iclass 28, count 0 2006.190.07:49:30.73#ibcon#about to read 5, iclass 28, count 0 2006.190.07:49:30.73#ibcon#read 5, iclass 28, count 0 2006.190.07:49:30.73#ibcon#about to read 6, iclass 28, count 0 2006.190.07:49:30.73#ibcon#read 6, iclass 28, count 0 2006.190.07:49:30.73#ibcon#end of sib2, iclass 28, count 0 2006.190.07:49:30.73#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:49:30.73#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:49:30.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:49:30.73#ibcon#*before write, iclass 28, count 0 2006.190.07:49:30.73#ibcon#enter sib2, iclass 28, count 0 2006.190.07:49:30.73#ibcon#flushed, iclass 28, count 0 2006.190.07:49:30.73#ibcon#about to write, iclass 28, count 0 2006.190.07:49:30.73#ibcon#wrote, iclass 28, count 0 2006.190.07:49:30.73#ibcon#about to read 3, iclass 28, count 0 2006.190.07:49:30.77#ibcon#read 3, iclass 28, count 0 2006.190.07:49:30.77#ibcon#about to read 4, iclass 28, count 0 2006.190.07:49:30.77#ibcon#read 4, iclass 28, count 0 2006.190.07:49:30.77#ibcon#about to read 5, iclass 28, count 0 2006.190.07:49:30.77#ibcon#read 5, iclass 28, count 0 2006.190.07:49:30.77#ibcon#about to read 6, iclass 28, count 0 2006.190.07:49:30.77#ibcon#read 6, iclass 28, count 0 2006.190.07:49:30.77#ibcon#end of sib2, iclass 28, count 0 2006.190.07:49:30.77#ibcon#*after write, iclass 28, count 0 2006.190.07:49:30.77#ibcon#*before return 0, iclass 28, count 0 2006.190.07:49:30.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:49:30.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:49:30.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:49:30.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:49:30.77$vc4f8/vb=1,4 2006.190.07:49:30.77#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:49:30.77#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:49:30.77#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:30.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:49:30.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:49:30.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:49:30.77#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:49:30.77#ibcon#first serial, iclass 30, count 2 2006.190.07:49:30.77#ibcon#enter sib2, iclass 30, count 2 2006.190.07:49:30.77#ibcon#flushed, iclass 30, count 2 2006.190.07:49:30.77#ibcon#about to write, iclass 30, count 2 2006.190.07:49:30.77#ibcon#wrote, iclass 30, count 2 2006.190.07:49:30.77#ibcon#about to read 3, iclass 30, count 2 2006.190.07:49:30.79#ibcon#read 3, iclass 30, count 2 2006.190.07:49:30.79#ibcon#about to read 4, iclass 30, count 2 2006.190.07:49:30.79#ibcon#read 4, iclass 30, count 2 2006.190.07:49:30.79#ibcon#about to read 5, iclass 30, count 2 2006.190.07:49:30.79#ibcon#read 5, iclass 30, count 2 2006.190.07:49:30.79#ibcon#about to read 6, iclass 30, count 2 2006.190.07:49:30.79#ibcon#read 6, iclass 30, count 2 2006.190.07:49:30.79#ibcon#end of sib2, iclass 30, count 2 2006.190.07:49:30.79#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:49:30.79#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:49:30.79#ibcon#[27=AT01-04\r\n] 2006.190.07:49:30.79#ibcon#*before write, iclass 30, count 2 2006.190.07:49:30.79#ibcon#enter sib2, iclass 30, count 2 2006.190.07:49:30.79#ibcon#flushed, iclass 30, count 2 2006.190.07:49:30.79#ibcon#about to write, iclass 30, count 2 2006.190.07:49:30.79#ibcon#wrote, iclass 30, count 2 2006.190.07:49:30.79#ibcon#about to read 3, iclass 30, count 2 2006.190.07:49:30.82#ibcon#read 3, iclass 30, count 2 2006.190.07:49:30.82#ibcon#about to read 4, iclass 30, count 2 2006.190.07:49:30.82#ibcon#read 4, iclass 30, count 2 2006.190.07:49:30.82#ibcon#about to read 5, iclass 30, count 2 2006.190.07:49:30.82#ibcon#read 5, iclass 30, count 2 2006.190.07:49:30.82#ibcon#about to read 6, iclass 30, count 2 2006.190.07:49:30.82#ibcon#read 6, iclass 30, count 2 2006.190.07:49:30.82#ibcon#end of sib2, iclass 30, count 2 2006.190.07:49:30.82#ibcon#*after write, iclass 30, count 2 2006.190.07:49:30.82#ibcon#*before return 0, iclass 30, count 2 2006.190.07:49:30.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:49:30.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:49:30.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:49:30.82#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:30.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:49:30.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:49:30.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:49:30.94#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:49:30.94#ibcon#first serial, iclass 30, count 0 2006.190.07:49:30.94#ibcon#enter sib2, iclass 30, count 0 2006.190.07:49:30.94#ibcon#flushed, iclass 30, count 0 2006.190.07:49:30.94#ibcon#about to write, iclass 30, count 0 2006.190.07:49:30.94#ibcon#wrote, iclass 30, count 0 2006.190.07:49:30.94#ibcon#about to read 3, iclass 30, count 0 2006.190.07:49:30.96#ibcon#read 3, iclass 30, count 0 2006.190.07:49:30.96#ibcon#about to read 4, iclass 30, count 0 2006.190.07:49:30.96#ibcon#read 4, iclass 30, count 0 2006.190.07:49:30.96#ibcon#about to read 5, iclass 30, count 0 2006.190.07:49:30.96#ibcon#read 5, iclass 30, count 0 2006.190.07:49:30.96#ibcon#about to read 6, iclass 30, count 0 2006.190.07:49:30.96#ibcon#read 6, iclass 30, count 0 2006.190.07:49:30.96#ibcon#end of sib2, iclass 30, count 0 2006.190.07:49:30.96#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:49:30.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:49:30.96#ibcon#[27=USB\r\n] 2006.190.07:49:30.96#ibcon#*before write, iclass 30, count 0 2006.190.07:49:30.96#ibcon#enter sib2, iclass 30, count 0 2006.190.07:49:30.96#ibcon#flushed, iclass 30, count 0 2006.190.07:49:30.96#ibcon#about to write, iclass 30, count 0 2006.190.07:49:30.96#ibcon#wrote, iclass 30, count 0 2006.190.07:49:30.96#ibcon#about to read 3, iclass 30, count 0 2006.190.07:49:30.99#ibcon#read 3, iclass 30, count 0 2006.190.07:49:30.99#ibcon#about to read 4, iclass 30, count 0 2006.190.07:49:30.99#ibcon#read 4, iclass 30, count 0 2006.190.07:49:30.99#ibcon#about to read 5, iclass 30, count 0 2006.190.07:49:30.99#ibcon#read 5, iclass 30, count 0 2006.190.07:49:30.99#ibcon#about to read 6, iclass 30, count 0 2006.190.07:49:30.99#ibcon#read 6, iclass 30, count 0 2006.190.07:49:30.99#ibcon#end of sib2, iclass 30, count 0 2006.190.07:49:30.99#ibcon#*after write, iclass 30, count 0 2006.190.07:49:30.99#ibcon#*before return 0, iclass 30, count 0 2006.190.07:49:30.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:49:30.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:49:30.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:49:30.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:49:30.99$vc4f8/vblo=2,640.99 2006.190.07:49:30.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:49:30.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:49:30.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:30.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:30.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:30.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:30.99#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:49:30.99#ibcon#first serial, iclass 32, count 0 2006.190.07:49:30.99#ibcon#enter sib2, iclass 32, count 0 2006.190.07:49:30.99#ibcon#flushed, iclass 32, count 0 2006.190.07:49:30.99#ibcon#about to write, iclass 32, count 0 2006.190.07:49:30.99#ibcon#wrote, iclass 32, count 0 2006.190.07:49:30.99#ibcon#about to read 3, iclass 32, count 0 2006.190.07:49:31.01#ibcon#read 3, iclass 32, count 0 2006.190.07:49:31.01#ibcon#about to read 4, iclass 32, count 0 2006.190.07:49:31.01#ibcon#read 4, iclass 32, count 0 2006.190.07:49:31.01#ibcon#about to read 5, iclass 32, count 0 2006.190.07:49:31.01#ibcon#read 5, iclass 32, count 0 2006.190.07:49:31.01#ibcon#about to read 6, iclass 32, count 0 2006.190.07:49:31.01#ibcon#read 6, iclass 32, count 0 2006.190.07:49:31.01#ibcon#end of sib2, iclass 32, count 0 2006.190.07:49:31.01#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:49:31.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:49:31.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:49:31.01#ibcon#*before write, iclass 32, count 0 2006.190.07:49:31.01#ibcon#enter sib2, iclass 32, count 0 2006.190.07:49:31.01#ibcon#flushed, iclass 32, count 0 2006.190.07:49:31.01#ibcon#about to write, iclass 32, count 0 2006.190.07:49:31.01#ibcon#wrote, iclass 32, count 0 2006.190.07:49:31.01#ibcon#about to read 3, iclass 32, count 0 2006.190.07:49:31.05#ibcon#read 3, iclass 32, count 0 2006.190.07:49:31.05#ibcon#about to read 4, iclass 32, count 0 2006.190.07:49:31.05#ibcon#read 4, iclass 32, count 0 2006.190.07:49:31.05#ibcon#about to read 5, iclass 32, count 0 2006.190.07:49:31.05#ibcon#read 5, iclass 32, count 0 2006.190.07:49:31.05#ibcon#about to read 6, iclass 32, count 0 2006.190.07:49:31.05#ibcon#read 6, iclass 32, count 0 2006.190.07:49:31.05#ibcon#end of sib2, iclass 32, count 0 2006.190.07:49:31.05#ibcon#*after write, iclass 32, count 0 2006.190.07:49:31.05#ibcon#*before return 0, iclass 32, count 0 2006.190.07:49:31.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:31.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:49:31.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:49:31.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:49:31.05$vc4f8/vb=2,4 2006.190.07:49:31.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:49:31.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:49:31.05#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:31.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:31.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:31.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:31.11#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:49:31.11#ibcon#first serial, iclass 34, count 2 2006.190.07:49:31.11#ibcon#enter sib2, iclass 34, count 2 2006.190.07:49:31.11#ibcon#flushed, iclass 34, count 2 2006.190.07:49:31.11#ibcon#about to write, iclass 34, count 2 2006.190.07:49:31.11#ibcon#wrote, iclass 34, count 2 2006.190.07:49:31.11#ibcon#about to read 3, iclass 34, count 2 2006.190.07:49:31.13#ibcon#read 3, iclass 34, count 2 2006.190.07:49:31.13#ibcon#about to read 4, iclass 34, count 2 2006.190.07:49:31.13#ibcon#read 4, iclass 34, count 2 2006.190.07:49:31.13#ibcon#about to read 5, iclass 34, count 2 2006.190.07:49:31.13#ibcon#read 5, iclass 34, count 2 2006.190.07:49:31.13#ibcon#about to read 6, iclass 34, count 2 2006.190.07:49:31.13#ibcon#read 6, iclass 34, count 2 2006.190.07:49:31.13#ibcon#end of sib2, iclass 34, count 2 2006.190.07:49:31.13#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:49:31.13#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:49:31.13#ibcon#[27=AT02-04\r\n] 2006.190.07:49:31.13#ibcon#*before write, iclass 34, count 2 2006.190.07:49:31.13#ibcon#enter sib2, iclass 34, count 2 2006.190.07:49:31.13#ibcon#flushed, iclass 34, count 2 2006.190.07:49:31.13#ibcon#about to write, iclass 34, count 2 2006.190.07:49:31.13#ibcon#wrote, iclass 34, count 2 2006.190.07:49:31.13#ibcon#about to read 3, iclass 34, count 2 2006.190.07:49:31.16#ibcon#read 3, iclass 34, count 2 2006.190.07:49:31.16#ibcon#about to read 4, iclass 34, count 2 2006.190.07:49:31.16#ibcon#read 4, iclass 34, count 2 2006.190.07:49:31.16#ibcon#about to read 5, iclass 34, count 2 2006.190.07:49:31.16#ibcon#read 5, iclass 34, count 2 2006.190.07:49:31.16#ibcon#about to read 6, iclass 34, count 2 2006.190.07:49:31.16#ibcon#read 6, iclass 34, count 2 2006.190.07:49:31.16#ibcon#end of sib2, iclass 34, count 2 2006.190.07:49:31.16#ibcon#*after write, iclass 34, count 2 2006.190.07:49:31.16#ibcon#*before return 0, iclass 34, count 2 2006.190.07:49:31.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:31.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:49:31.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:49:31.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:31.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:31.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:31.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:31.28#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:49:31.28#ibcon#first serial, iclass 34, count 0 2006.190.07:49:31.28#ibcon#enter sib2, iclass 34, count 0 2006.190.07:49:31.28#ibcon#flushed, iclass 34, count 0 2006.190.07:49:31.28#ibcon#about to write, iclass 34, count 0 2006.190.07:49:31.28#ibcon#wrote, iclass 34, count 0 2006.190.07:49:31.28#ibcon#about to read 3, iclass 34, count 0 2006.190.07:49:31.30#ibcon#read 3, iclass 34, count 0 2006.190.07:49:31.30#ibcon#about to read 4, iclass 34, count 0 2006.190.07:49:31.30#ibcon#read 4, iclass 34, count 0 2006.190.07:49:31.30#ibcon#about to read 5, iclass 34, count 0 2006.190.07:49:31.30#ibcon#read 5, iclass 34, count 0 2006.190.07:49:31.30#ibcon#about to read 6, iclass 34, count 0 2006.190.07:49:31.30#ibcon#read 6, iclass 34, count 0 2006.190.07:49:31.30#ibcon#end of sib2, iclass 34, count 0 2006.190.07:49:31.30#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:49:31.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:49:31.30#ibcon#[27=USB\r\n] 2006.190.07:49:31.30#ibcon#*before write, iclass 34, count 0 2006.190.07:49:31.30#ibcon#enter sib2, iclass 34, count 0 2006.190.07:49:31.30#ibcon#flushed, iclass 34, count 0 2006.190.07:49:31.30#ibcon#about to write, iclass 34, count 0 2006.190.07:49:31.30#ibcon#wrote, iclass 34, count 0 2006.190.07:49:31.30#ibcon#about to read 3, iclass 34, count 0 2006.190.07:49:31.33#ibcon#read 3, iclass 34, count 0 2006.190.07:49:31.33#ibcon#about to read 4, iclass 34, count 0 2006.190.07:49:31.33#ibcon#read 4, iclass 34, count 0 2006.190.07:49:31.33#ibcon#about to read 5, iclass 34, count 0 2006.190.07:49:31.33#ibcon#read 5, iclass 34, count 0 2006.190.07:49:31.33#ibcon#about to read 6, iclass 34, count 0 2006.190.07:49:31.33#ibcon#read 6, iclass 34, count 0 2006.190.07:49:31.33#ibcon#end of sib2, iclass 34, count 0 2006.190.07:49:31.33#ibcon#*after write, iclass 34, count 0 2006.190.07:49:31.33#ibcon#*before return 0, iclass 34, count 0 2006.190.07:49:31.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:31.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:49:31.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:49:31.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:49:31.33$vc4f8/vblo=3,656.99 2006.190.07:49:31.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:49:31.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:49:31.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:31.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:31.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:31.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:31.33#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:49:31.33#ibcon#first serial, iclass 36, count 0 2006.190.07:49:31.33#ibcon#enter sib2, iclass 36, count 0 2006.190.07:49:31.33#ibcon#flushed, iclass 36, count 0 2006.190.07:49:31.33#ibcon#about to write, iclass 36, count 0 2006.190.07:49:31.33#ibcon#wrote, iclass 36, count 0 2006.190.07:49:31.33#ibcon#about to read 3, iclass 36, count 0 2006.190.07:49:31.35#ibcon#read 3, iclass 36, count 0 2006.190.07:49:31.35#ibcon#about to read 4, iclass 36, count 0 2006.190.07:49:31.35#ibcon#read 4, iclass 36, count 0 2006.190.07:49:31.35#ibcon#about to read 5, iclass 36, count 0 2006.190.07:49:31.35#ibcon#read 5, iclass 36, count 0 2006.190.07:49:31.35#ibcon#about to read 6, iclass 36, count 0 2006.190.07:49:31.35#ibcon#read 6, iclass 36, count 0 2006.190.07:49:31.35#ibcon#end of sib2, iclass 36, count 0 2006.190.07:49:31.35#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:49:31.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:49:31.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:49:31.35#ibcon#*before write, iclass 36, count 0 2006.190.07:49:31.35#ibcon#enter sib2, iclass 36, count 0 2006.190.07:49:31.35#ibcon#flushed, iclass 36, count 0 2006.190.07:49:31.35#ibcon#about to write, iclass 36, count 0 2006.190.07:49:31.35#ibcon#wrote, iclass 36, count 0 2006.190.07:49:31.35#ibcon#about to read 3, iclass 36, count 0 2006.190.07:49:31.39#ibcon#read 3, iclass 36, count 0 2006.190.07:49:31.39#ibcon#about to read 4, iclass 36, count 0 2006.190.07:49:31.39#ibcon#read 4, iclass 36, count 0 2006.190.07:49:31.39#ibcon#about to read 5, iclass 36, count 0 2006.190.07:49:31.39#ibcon#read 5, iclass 36, count 0 2006.190.07:49:31.39#ibcon#about to read 6, iclass 36, count 0 2006.190.07:49:31.39#ibcon#read 6, iclass 36, count 0 2006.190.07:49:31.39#ibcon#end of sib2, iclass 36, count 0 2006.190.07:49:31.39#ibcon#*after write, iclass 36, count 0 2006.190.07:49:31.39#ibcon#*before return 0, iclass 36, count 0 2006.190.07:49:31.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:31.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:49:31.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:49:31.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:49:31.39$vc4f8/vb=3,4 2006.190.07:49:31.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.07:49:31.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.07:49:31.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:31.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:31.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:31.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:31.45#ibcon#enter wrdev, iclass 38, count 2 2006.190.07:49:31.45#ibcon#first serial, iclass 38, count 2 2006.190.07:49:31.45#ibcon#enter sib2, iclass 38, count 2 2006.190.07:49:31.45#ibcon#flushed, iclass 38, count 2 2006.190.07:49:31.45#ibcon#about to write, iclass 38, count 2 2006.190.07:49:31.45#ibcon#wrote, iclass 38, count 2 2006.190.07:49:31.45#ibcon#about to read 3, iclass 38, count 2 2006.190.07:49:31.47#ibcon#read 3, iclass 38, count 2 2006.190.07:49:31.47#ibcon#about to read 4, iclass 38, count 2 2006.190.07:49:31.47#ibcon#read 4, iclass 38, count 2 2006.190.07:49:31.47#ibcon#about to read 5, iclass 38, count 2 2006.190.07:49:31.47#ibcon#read 5, iclass 38, count 2 2006.190.07:49:31.47#ibcon#about to read 6, iclass 38, count 2 2006.190.07:49:31.47#ibcon#read 6, iclass 38, count 2 2006.190.07:49:31.47#ibcon#end of sib2, iclass 38, count 2 2006.190.07:49:31.47#ibcon#*mode == 0, iclass 38, count 2 2006.190.07:49:31.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.07:49:31.47#ibcon#[27=AT03-04\r\n] 2006.190.07:49:31.47#ibcon#*before write, iclass 38, count 2 2006.190.07:49:31.47#ibcon#enter sib2, iclass 38, count 2 2006.190.07:49:31.47#ibcon#flushed, iclass 38, count 2 2006.190.07:49:31.47#ibcon#about to write, iclass 38, count 2 2006.190.07:49:31.47#ibcon#wrote, iclass 38, count 2 2006.190.07:49:31.47#ibcon#about to read 3, iclass 38, count 2 2006.190.07:49:31.50#ibcon#read 3, iclass 38, count 2 2006.190.07:49:31.50#ibcon#about to read 4, iclass 38, count 2 2006.190.07:49:31.50#ibcon#read 4, iclass 38, count 2 2006.190.07:49:31.50#ibcon#about to read 5, iclass 38, count 2 2006.190.07:49:31.50#ibcon#read 5, iclass 38, count 2 2006.190.07:49:31.50#ibcon#about to read 6, iclass 38, count 2 2006.190.07:49:31.50#ibcon#read 6, iclass 38, count 2 2006.190.07:49:31.50#ibcon#end of sib2, iclass 38, count 2 2006.190.07:49:31.50#ibcon#*after write, iclass 38, count 2 2006.190.07:49:31.50#ibcon#*before return 0, iclass 38, count 2 2006.190.07:49:31.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:31.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:49:31.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.07:49:31.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:31.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:31.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:31.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:31.62#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:49:31.62#ibcon#first serial, iclass 38, count 0 2006.190.07:49:31.62#ibcon#enter sib2, iclass 38, count 0 2006.190.07:49:31.62#ibcon#flushed, iclass 38, count 0 2006.190.07:49:31.62#ibcon#about to write, iclass 38, count 0 2006.190.07:49:31.62#ibcon#wrote, iclass 38, count 0 2006.190.07:49:31.62#ibcon#about to read 3, iclass 38, count 0 2006.190.07:49:31.64#ibcon#read 3, iclass 38, count 0 2006.190.07:49:31.64#ibcon#about to read 4, iclass 38, count 0 2006.190.07:49:31.64#ibcon#read 4, iclass 38, count 0 2006.190.07:49:31.64#ibcon#about to read 5, iclass 38, count 0 2006.190.07:49:31.64#ibcon#read 5, iclass 38, count 0 2006.190.07:49:31.64#ibcon#about to read 6, iclass 38, count 0 2006.190.07:49:31.64#ibcon#read 6, iclass 38, count 0 2006.190.07:49:31.64#ibcon#end of sib2, iclass 38, count 0 2006.190.07:49:31.64#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:49:31.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:49:31.64#ibcon#[27=USB\r\n] 2006.190.07:49:31.64#ibcon#*before write, iclass 38, count 0 2006.190.07:49:31.64#ibcon#enter sib2, iclass 38, count 0 2006.190.07:49:31.64#ibcon#flushed, iclass 38, count 0 2006.190.07:49:31.64#ibcon#about to write, iclass 38, count 0 2006.190.07:49:31.64#ibcon#wrote, iclass 38, count 0 2006.190.07:49:31.64#ibcon#about to read 3, iclass 38, count 0 2006.190.07:49:31.67#ibcon#read 3, iclass 38, count 0 2006.190.07:49:31.67#ibcon#about to read 4, iclass 38, count 0 2006.190.07:49:31.67#ibcon#read 4, iclass 38, count 0 2006.190.07:49:31.67#ibcon#about to read 5, iclass 38, count 0 2006.190.07:49:31.67#ibcon#read 5, iclass 38, count 0 2006.190.07:49:31.67#ibcon#about to read 6, iclass 38, count 0 2006.190.07:49:31.67#ibcon#read 6, iclass 38, count 0 2006.190.07:49:31.67#ibcon#end of sib2, iclass 38, count 0 2006.190.07:49:31.67#ibcon#*after write, iclass 38, count 0 2006.190.07:49:31.67#ibcon#*before return 0, iclass 38, count 0 2006.190.07:49:31.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:31.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:49:31.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:49:31.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:49:31.67$vc4f8/vblo=4,712.99 2006.190.07:49:31.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:49:31.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:49:31.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:31.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:31.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:31.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:31.67#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:49:31.67#ibcon#first serial, iclass 40, count 0 2006.190.07:49:31.67#ibcon#enter sib2, iclass 40, count 0 2006.190.07:49:31.67#ibcon#flushed, iclass 40, count 0 2006.190.07:49:31.67#ibcon#about to write, iclass 40, count 0 2006.190.07:49:31.67#ibcon#wrote, iclass 40, count 0 2006.190.07:49:31.67#ibcon#about to read 3, iclass 40, count 0 2006.190.07:49:31.69#ibcon#read 3, iclass 40, count 0 2006.190.07:49:31.69#ibcon#about to read 4, iclass 40, count 0 2006.190.07:49:31.69#ibcon#read 4, iclass 40, count 0 2006.190.07:49:31.69#ibcon#about to read 5, iclass 40, count 0 2006.190.07:49:31.69#ibcon#read 5, iclass 40, count 0 2006.190.07:49:31.69#ibcon#about to read 6, iclass 40, count 0 2006.190.07:49:31.69#ibcon#read 6, iclass 40, count 0 2006.190.07:49:31.69#ibcon#end of sib2, iclass 40, count 0 2006.190.07:49:31.69#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:49:31.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:49:31.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:49:31.69#ibcon#*before write, iclass 40, count 0 2006.190.07:49:31.69#ibcon#enter sib2, iclass 40, count 0 2006.190.07:49:31.69#ibcon#flushed, iclass 40, count 0 2006.190.07:49:31.69#ibcon#about to write, iclass 40, count 0 2006.190.07:49:31.69#ibcon#wrote, iclass 40, count 0 2006.190.07:49:31.69#ibcon#about to read 3, iclass 40, count 0 2006.190.07:49:31.73#ibcon#read 3, iclass 40, count 0 2006.190.07:49:31.73#ibcon#about to read 4, iclass 40, count 0 2006.190.07:49:31.73#ibcon#read 4, iclass 40, count 0 2006.190.07:49:31.73#ibcon#about to read 5, iclass 40, count 0 2006.190.07:49:31.73#ibcon#read 5, iclass 40, count 0 2006.190.07:49:31.73#ibcon#about to read 6, iclass 40, count 0 2006.190.07:49:31.73#ibcon#read 6, iclass 40, count 0 2006.190.07:49:31.73#ibcon#end of sib2, iclass 40, count 0 2006.190.07:49:31.73#ibcon#*after write, iclass 40, count 0 2006.190.07:49:31.73#ibcon#*before return 0, iclass 40, count 0 2006.190.07:49:31.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:31.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:49:31.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:49:31.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:49:31.73$vc4f8/vb=4,4 2006.190.07:49:31.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:49:31.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:49:31.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:31.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:31.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:31.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:31.79#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:49:31.79#ibcon#first serial, iclass 4, count 2 2006.190.07:49:31.79#ibcon#enter sib2, iclass 4, count 2 2006.190.07:49:31.79#ibcon#flushed, iclass 4, count 2 2006.190.07:49:31.79#ibcon#about to write, iclass 4, count 2 2006.190.07:49:31.79#ibcon#wrote, iclass 4, count 2 2006.190.07:49:31.79#ibcon#about to read 3, iclass 4, count 2 2006.190.07:49:31.81#ibcon#read 3, iclass 4, count 2 2006.190.07:49:31.81#ibcon#about to read 4, iclass 4, count 2 2006.190.07:49:31.81#ibcon#read 4, iclass 4, count 2 2006.190.07:49:31.81#ibcon#about to read 5, iclass 4, count 2 2006.190.07:49:31.81#ibcon#read 5, iclass 4, count 2 2006.190.07:49:31.81#ibcon#about to read 6, iclass 4, count 2 2006.190.07:49:31.81#ibcon#read 6, iclass 4, count 2 2006.190.07:49:31.81#ibcon#end of sib2, iclass 4, count 2 2006.190.07:49:31.81#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:49:31.81#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:49:31.81#ibcon#[27=AT04-04\r\n] 2006.190.07:49:31.81#ibcon#*before write, iclass 4, count 2 2006.190.07:49:31.81#ibcon#enter sib2, iclass 4, count 2 2006.190.07:49:31.81#ibcon#flushed, iclass 4, count 2 2006.190.07:49:31.81#ibcon#about to write, iclass 4, count 2 2006.190.07:49:31.81#ibcon#wrote, iclass 4, count 2 2006.190.07:49:31.81#ibcon#about to read 3, iclass 4, count 2 2006.190.07:49:31.84#ibcon#read 3, iclass 4, count 2 2006.190.07:49:31.84#ibcon#about to read 4, iclass 4, count 2 2006.190.07:49:31.84#ibcon#read 4, iclass 4, count 2 2006.190.07:49:31.84#ibcon#about to read 5, iclass 4, count 2 2006.190.07:49:31.84#ibcon#read 5, iclass 4, count 2 2006.190.07:49:31.84#ibcon#about to read 6, iclass 4, count 2 2006.190.07:49:31.84#ibcon#read 6, iclass 4, count 2 2006.190.07:49:31.84#ibcon#end of sib2, iclass 4, count 2 2006.190.07:49:31.84#ibcon#*after write, iclass 4, count 2 2006.190.07:49:31.84#ibcon#*before return 0, iclass 4, count 2 2006.190.07:49:31.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:31.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:49:31.84#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:49:31.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:31.84#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:31.96#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:31.96#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:31.96#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:49:31.96#ibcon#first serial, iclass 4, count 0 2006.190.07:49:31.96#ibcon#enter sib2, iclass 4, count 0 2006.190.07:49:31.96#ibcon#flushed, iclass 4, count 0 2006.190.07:49:31.96#ibcon#about to write, iclass 4, count 0 2006.190.07:49:31.96#ibcon#wrote, iclass 4, count 0 2006.190.07:49:31.96#ibcon#about to read 3, iclass 4, count 0 2006.190.07:49:31.98#ibcon#read 3, iclass 4, count 0 2006.190.07:49:31.98#ibcon#about to read 4, iclass 4, count 0 2006.190.07:49:31.98#ibcon#read 4, iclass 4, count 0 2006.190.07:49:31.98#ibcon#about to read 5, iclass 4, count 0 2006.190.07:49:31.98#ibcon#read 5, iclass 4, count 0 2006.190.07:49:31.98#ibcon#about to read 6, iclass 4, count 0 2006.190.07:49:31.98#ibcon#read 6, iclass 4, count 0 2006.190.07:49:31.98#ibcon#end of sib2, iclass 4, count 0 2006.190.07:49:31.98#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:49:31.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:49:31.98#ibcon#[27=USB\r\n] 2006.190.07:49:31.98#ibcon#*before write, iclass 4, count 0 2006.190.07:49:31.98#ibcon#enter sib2, iclass 4, count 0 2006.190.07:49:31.98#ibcon#flushed, iclass 4, count 0 2006.190.07:49:31.98#ibcon#about to write, iclass 4, count 0 2006.190.07:49:31.98#ibcon#wrote, iclass 4, count 0 2006.190.07:49:31.98#ibcon#about to read 3, iclass 4, count 0 2006.190.07:49:32.01#ibcon#read 3, iclass 4, count 0 2006.190.07:49:32.01#ibcon#about to read 4, iclass 4, count 0 2006.190.07:49:32.01#ibcon#read 4, iclass 4, count 0 2006.190.07:49:32.01#ibcon#about to read 5, iclass 4, count 0 2006.190.07:49:32.01#ibcon#read 5, iclass 4, count 0 2006.190.07:49:32.01#ibcon#about to read 6, iclass 4, count 0 2006.190.07:49:32.01#ibcon#read 6, iclass 4, count 0 2006.190.07:49:32.01#ibcon#end of sib2, iclass 4, count 0 2006.190.07:49:32.01#ibcon#*after write, iclass 4, count 0 2006.190.07:49:32.01#ibcon#*before return 0, iclass 4, count 0 2006.190.07:49:32.01#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:32.01#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:49:32.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:49:32.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:49:32.01$vc4f8/vblo=5,744.99 2006.190.07:49:32.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:49:32.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:49:32.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:32.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:32.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:32.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:32.01#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:49:32.01#ibcon#first serial, iclass 6, count 0 2006.190.07:49:32.01#ibcon#enter sib2, iclass 6, count 0 2006.190.07:49:32.01#ibcon#flushed, iclass 6, count 0 2006.190.07:49:32.01#ibcon#about to write, iclass 6, count 0 2006.190.07:49:32.01#ibcon#wrote, iclass 6, count 0 2006.190.07:49:32.01#ibcon#about to read 3, iclass 6, count 0 2006.190.07:49:32.03#ibcon#read 3, iclass 6, count 0 2006.190.07:49:32.03#ibcon#about to read 4, iclass 6, count 0 2006.190.07:49:32.03#ibcon#read 4, iclass 6, count 0 2006.190.07:49:32.03#ibcon#about to read 5, iclass 6, count 0 2006.190.07:49:32.03#ibcon#read 5, iclass 6, count 0 2006.190.07:49:32.03#ibcon#about to read 6, iclass 6, count 0 2006.190.07:49:32.03#ibcon#read 6, iclass 6, count 0 2006.190.07:49:32.03#ibcon#end of sib2, iclass 6, count 0 2006.190.07:49:32.03#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:49:32.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:49:32.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:49:32.03#ibcon#*before write, iclass 6, count 0 2006.190.07:49:32.03#ibcon#enter sib2, iclass 6, count 0 2006.190.07:49:32.03#ibcon#flushed, iclass 6, count 0 2006.190.07:49:32.03#ibcon#about to write, iclass 6, count 0 2006.190.07:49:32.03#ibcon#wrote, iclass 6, count 0 2006.190.07:49:32.03#ibcon#about to read 3, iclass 6, count 0 2006.190.07:49:32.07#ibcon#read 3, iclass 6, count 0 2006.190.07:49:32.07#ibcon#about to read 4, iclass 6, count 0 2006.190.07:49:32.07#ibcon#read 4, iclass 6, count 0 2006.190.07:49:32.07#ibcon#about to read 5, iclass 6, count 0 2006.190.07:49:32.07#ibcon#read 5, iclass 6, count 0 2006.190.07:49:32.07#ibcon#about to read 6, iclass 6, count 0 2006.190.07:49:32.07#ibcon#read 6, iclass 6, count 0 2006.190.07:49:32.07#ibcon#end of sib2, iclass 6, count 0 2006.190.07:49:32.07#ibcon#*after write, iclass 6, count 0 2006.190.07:49:32.07#ibcon#*before return 0, iclass 6, count 0 2006.190.07:49:32.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:32.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:49:32.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:49:32.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:49:32.07$vc4f8/vb=5,4 2006.190.07:49:32.07#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:49:32.07#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:49:32.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:32.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:32.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:32.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:32.13#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:49:32.13#ibcon#first serial, iclass 10, count 2 2006.190.07:49:32.13#ibcon#enter sib2, iclass 10, count 2 2006.190.07:49:32.13#ibcon#flushed, iclass 10, count 2 2006.190.07:49:32.13#ibcon#about to write, iclass 10, count 2 2006.190.07:49:32.13#ibcon#wrote, iclass 10, count 2 2006.190.07:49:32.13#ibcon#about to read 3, iclass 10, count 2 2006.190.07:49:32.15#ibcon#read 3, iclass 10, count 2 2006.190.07:49:32.15#ibcon#about to read 4, iclass 10, count 2 2006.190.07:49:32.15#ibcon#read 4, iclass 10, count 2 2006.190.07:49:32.15#ibcon#about to read 5, iclass 10, count 2 2006.190.07:49:32.15#ibcon#read 5, iclass 10, count 2 2006.190.07:49:32.15#ibcon#about to read 6, iclass 10, count 2 2006.190.07:49:32.15#ibcon#read 6, iclass 10, count 2 2006.190.07:49:32.15#ibcon#end of sib2, iclass 10, count 2 2006.190.07:49:32.15#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:49:32.15#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:49:32.15#ibcon#[27=AT05-04\r\n] 2006.190.07:49:32.15#ibcon#*before write, iclass 10, count 2 2006.190.07:49:32.15#ibcon#enter sib2, iclass 10, count 2 2006.190.07:49:32.15#ibcon#flushed, iclass 10, count 2 2006.190.07:49:32.15#ibcon#about to write, iclass 10, count 2 2006.190.07:49:32.15#ibcon#wrote, iclass 10, count 2 2006.190.07:49:32.15#ibcon#about to read 3, iclass 10, count 2 2006.190.07:49:32.18#ibcon#read 3, iclass 10, count 2 2006.190.07:49:32.18#ibcon#about to read 4, iclass 10, count 2 2006.190.07:49:32.18#ibcon#read 4, iclass 10, count 2 2006.190.07:49:32.18#ibcon#about to read 5, iclass 10, count 2 2006.190.07:49:32.18#ibcon#read 5, iclass 10, count 2 2006.190.07:49:32.18#ibcon#about to read 6, iclass 10, count 2 2006.190.07:49:32.18#ibcon#read 6, iclass 10, count 2 2006.190.07:49:32.18#ibcon#end of sib2, iclass 10, count 2 2006.190.07:49:32.18#ibcon#*after write, iclass 10, count 2 2006.190.07:49:32.18#ibcon#*before return 0, iclass 10, count 2 2006.190.07:49:32.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:32.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:49:32.18#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:49:32.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:32.18#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:32.30#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:32.30#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:32.30#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:49:32.30#ibcon#first serial, iclass 10, count 0 2006.190.07:49:32.30#ibcon#enter sib2, iclass 10, count 0 2006.190.07:49:32.30#ibcon#flushed, iclass 10, count 0 2006.190.07:49:32.30#ibcon#about to write, iclass 10, count 0 2006.190.07:49:32.30#ibcon#wrote, iclass 10, count 0 2006.190.07:49:32.30#ibcon#about to read 3, iclass 10, count 0 2006.190.07:49:32.32#ibcon#read 3, iclass 10, count 0 2006.190.07:49:32.32#ibcon#about to read 4, iclass 10, count 0 2006.190.07:49:32.32#ibcon#read 4, iclass 10, count 0 2006.190.07:49:32.32#ibcon#about to read 5, iclass 10, count 0 2006.190.07:49:32.32#ibcon#read 5, iclass 10, count 0 2006.190.07:49:32.32#ibcon#about to read 6, iclass 10, count 0 2006.190.07:49:32.32#ibcon#read 6, iclass 10, count 0 2006.190.07:49:32.32#ibcon#end of sib2, iclass 10, count 0 2006.190.07:49:32.32#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:49:32.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:49:32.32#ibcon#[27=USB\r\n] 2006.190.07:49:32.32#ibcon#*before write, iclass 10, count 0 2006.190.07:49:32.32#ibcon#enter sib2, iclass 10, count 0 2006.190.07:49:32.32#ibcon#flushed, iclass 10, count 0 2006.190.07:49:32.32#ibcon#about to write, iclass 10, count 0 2006.190.07:49:32.32#ibcon#wrote, iclass 10, count 0 2006.190.07:49:32.32#ibcon#about to read 3, iclass 10, count 0 2006.190.07:49:32.35#ibcon#read 3, iclass 10, count 0 2006.190.07:49:32.35#ibcon#about to read 4, iclass 10, count 0 2006.190.07:49:32.35#ibcon#read 4, iclass 10, count 0 2006.190.07:49:32.35#ibcon#about to read 5, iclass 10, count 0 2006.190.07:49:32.35#ibcon#read 5, iclass 10, count 0 2006.190.07:49:32.35#ibcon#about to read 6, iclass 10, count 0 2006.190.07:49:32.35#ibcon#read 6, iclass 10, count 0 2006.190.07:49:32.35#ibcon#end of sib2, iclass 10, count 0 2006.190.07:49:32.35#ibcon#*after write, iclass 10, count 0 2006.190.07:49:32.35#ibcon#*before return 0, iclass 10, count 0 2006.190.07:49:32.35#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:32.35#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:49:32.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:49:32.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:49:32.35$vc4f8/vblo=6,752.99 2006.190.07:49:32.35#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:49:32.35#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:49:32.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:49:32.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:32.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:32.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:32.35#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:49:32.35#ibcon#first serial, iclass 12, count 0 2006.190.07:49:32.35#ibcon#enter sib2, iclass 12, count 0 2006.190.07:49:32.35#ibcon#flushed, iclass 12, count 0 2006.190.07:49:32.35#ibcon#about to write, iclass 12, count 0 2006.190.07:49:32.35#ibcon#wrote, iclass 12, count 0 2006.190.07:49:32.35#ibcon#about to read 3, iclass 12, count 0 2006.190.07:49:32.37#ibcon#read 3, iclass 12, count 0 2006.190.07:49:32.37#ibcon#about to read 4, iclass 12, count 0 2006.190.07:49:32.37#ibcon#read 4, iclass 12, count 0 2006.190.07:49:32.37#ibcon#about to read 5, iclass 12, count 0 2006.190.07:49:32.37#ibcon#read 5, iclass 12, count 0 2006.190.07:49:32.37#ibcon#about to read 6, iclass 12, count 0 2006.190.07:49:32.37#ibcon#read 6, iclass 12, count 0 2006.190.07:49:32.37#ibcon#end of sib2, iclass 12, count 0 2006.190.07:49:32.37#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:49:32.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:49:32.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:49:32.37#ibcon#*before write, iclass 12, count 0 2006.190.07:49:32.37#ibcon#enter sib2, iclass 12, count 0 2006.190.07:49:32.37#ibcon#flushed, iclass 12, count 0 2006.190.07:49:32.37#ibcon#about to write, iclass 12, count 0 2006.190.07:49:32.37#ibcon#wrote, iclass 12, count 0 2006.190.07:49:32.37#ibcon#about to read 3, iclass 12, count 0 2006.190.07:49:32.41#ibcon#read 3, iclass 12, count 0 2006.190.07:49:32.41#ibcon#about to read 4, iclass 12, count 0 2006.190.07:49:32.41#ibcon#read 4, iclass 12, count 0 2006.190.07:49:32.41#ibcon#about to read 5, iclass 12, count 0 2006.190.07:49:32.41#ibcon#read 5, iclass 12, count 0 2006.190.07:49:32.41#ibcon#about to read 6, iclass 12, count 0 2006.190.07:49:32.41#ibcon#read 6, iclass 12, count 0 2006.190.07:49:32.41#ibcon#end of sib2, iclass 12, count 0 2006.190.07:49:32.41#ibcon#*after write, iclass 12, count 0 2006.190.07:49:32.41#ibcon#*before return 0, iclass 12, count 0 2006.190.07:49:32.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:32.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:49:32.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:49:32.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:49:32.41$vc4f8/vb=6,4 2006.190.07:49:32.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:49:32.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:49:32.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:49:32.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:32.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:32.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:32.47#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:49:32.47#ibcon#first serial, iclass 14, count 2 2006.190.07:49:32.47#ibcon#enter sib2, iclass 14, count 2 2006.190.07:49:32.47#ibcon#flushed, iclass 14, count 2 2006.190.07:49:32.47#ibcon#about to write, iclass 14, count 2 2006.190.07:49:32.47#ibcon#wrote, iclass 14, count 2 2006.190.07:49:32.47#ibcon#about to read 3, iclass 14, count 2 2006.190.07:49:32.49#ibcon#read 3, iclass 14, count 2 2006.190.07:49:32.49#ibcon#about to read 4, iclass 14, count 2 2006.190.07:49:32.49#ibcon#read 4, iclass 14, count 2 2006.190.07:49:32.49#ibcon#about to read 5, iclass 14, count 2 2006.190.07:49:32.49#ibcon#read 5, iclass 14, count 2 2006.190.07:49:32.49#ibcon#about to read 6, iclass 14, count 2 2006.190.07:49:32.49#ibcon#read 6, iclass 14, count 2 2006.190.07:49:32.49#ibcon#end of sib2, iclass 14, count 2 2006.190.07:49:32.49#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:49:32.49#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:49:32.49#ibcon#[27=AT06-04\r\n] 2006.190.07:49:32.49#ibcon#*before write, iclass 14, count 2 2006.190.07:49:32.49#ibcon#enter sib2, iclass 14, count 2 2006.190.07:49:32.49#ibcon#flushed, iclass 14, count 2 2006.190.07:49:32.49#ibcon#about to write, iclass 14, count 2 2006.190.07:49:32.49#ibcon#wrote, iclass 14, count 2 2006.190.07:49:32.49#ibcon#about to read 3, iclass 14, count 2 2006.190.07:49:32.52#ibcon#read 3, iclass 14, count 2 2006.190.07:49:32.52#ibcon#about to read 4, iclass 14, count 2 2006.190.07:49:32.52#ibcon#read 4, iclass 14, count 2 2006.190.07:49:32.52#ibcon#about to read 5, iclass 14, count 2 2006.190.07:49:32.52#ibcon#read 5, iclass 14, count 2 2006.190.07:49:32.52#ibcon#about to read 6, iclass 14, count 2 2006.190.07:49:32.52#ibcon#read 6, iclass 14, count 2 2006.190.07:49:32.52#ibcon#end of sib2, iclass 14, count 2 2006.190.07:49:32.52#ibcon#*after write, iclass 14, count 2 2006.190.07:49:32.52#ibcon#*before return 0, iclass 14, count 2 2006.190.07:49:32.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:32.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:49:32.52#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:49:32.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:49:32.52#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:32.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:32.64#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:32.64#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:49:32.64#ibcon#first serial, iclass 14, count 0 2006.190.07:49:32.64#ibcon#enter sib2, iclass 14, count 0 2006.190.07:49:32.64#ibcon#flushed, iclass 14, count 0 2006.190.07:49:32.64#ibcon#about to write, iclass 14, count 0 2006.190.07:49:32.64#ibcon#wrote, iclass 14, count 0 2006.190.07:49:32.64#ibcon#about to read 3, iclass 14, count 0 2006.190.07:49:32.66#ibcon#read 3, iclass 14, count 0 2006.190.07:49:32.66#ibcon#about to read 4, iclass 14, count 0 2006.190.07:49:32.66#ibcon#read 4, iclass 14, count 0 2006.190.07:49:32.66#ibcon#about to read 5, iclass 14, count 0 2006.190.07:49:32.66#ibcon#read 5, iclass 14, count 0 2006.190.07:49:32.66#ibcon#about to read 6, iclass 14, count 0 2006.190.07:49:32.66#ibcon#read 6, iclass 14, count 0 2006.190.07:49:32.66#ibcon#end of sib2, iclass 14, count 0 2006.190.07:49:32.66#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:49:32.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:49:32.66#ibcon#[27=USB\r\n] 2006.190.07:49:32.66#ibcon#*before write, iclass 14, count 0 2006.190.07:49:32.66#ibcon#enter sib2, iclass 14, count 0 2006.190.07:49:32.66#ibcon#flushed, iclass 14, count 0 2006.190.07:49:32.66#ibcon#about to write, iclass 14, count 0 2006.190.07:49:32.66#ibcon#wrote, iclass 14, count 0 2006.190.07:49:32.66#ibcon#about to read 3, iclass 14, count 0 2006.190.07:49:32.69#ibcon#read 3, iclass 14, count 0 2006.190.07:49:32.69#ibcon#about to read 4, iclass 14, count 0 2006.190.07:49:32.69#ibcon#read 4, iclass 14, count 0 2006.190.07:49:32.69#ibcon#about to read 5, iclass 14, count 0 2006.190.07:49:32.69#ibcon#read 5, iclass 14, count 0 2006.190.07:49:32.69#ibcon#about to read 6, iclass 14, count 0 2006.190.07:49:32.69#ibcon#read 6, iclass 14, count 0 2006.190.07:49:32.69#ibcon#end of sib2, iclass 14, count 0 2006.190.07:49:32.69#ibcon#*after write, iclass 14, count 0 2006.190.07:49:32.69#ibcon#*before return 0, iclass 14, count 0 2006.190.07:49:32.69#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:32.69#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:49:32.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:49:32.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:49:32.69$vc4f8/vabw=wide 2006.190.07:49:32.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:49:32.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:49:32.69#ibcon#ireg 8 cls_cnt 0 2006.190.07:49:32.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:32.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:32.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:32.69#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:49:32.69#ibcon#first serial, iclass 16, count 0 2006.190.07:49:32.69#ibcon#enter sib2, iclass 16, count 0 2006.190.07:49:32.69#ibcon#flushed, iclass 16, count 0 2006.190.07:49:32.69#ibcon#about to write, iclass 16, count 0 2006.190.07:49:32.69#ibcon#wrote, iclass 16, count 0 2006.190.07:49:32.69#ibcon#about to read 3, iclass 16, count 0 2006.190.07:49:32.71#ibcon#read 3, iclass 16, count 0 2006.190.07:49:32.71#ibcon#about to read 4, iclass 16, count 0 2006.190.07:49:32.71#ibcon#read 4, iclass 16, count 0 2006.190.07:49:32.71#ibcon#about to read 5, iclass 16, count 0 2006.190.07:49:32.71#ibcon#read 5, iclass 16, count 0 2006.190.07:49:32.71#ibcon#about to read 6, iclass 16, count 0 2006.190.07:49:32.71#ibcon#read 6, iclass 16, count 0 2006.190.07:49:32.71#ibcon#end of sib2, iclass 16, count 0 2006.190.07:49:32.71#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:49:32.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:49:32.71#ibcon#[25=BW32\r\n] 2006.190.07:49:32.71#ibcon#*before write, iclass 16, count 0 2006.190.07:49:32.71#ibcon#enter sib2, iclass 16, count 0 2006.190.07:49:32.71#ibcon#flushed, iclass 16, count 0 2006.190.07:49:32.71#ibcon#about to write, iclass 16, count 0 2006.190.07:49:32.71#ibcon#wrote, iclass 16, count 0 2006.190.07:49:32.71#ibcon#about to read 3, iclass 16, count 0 2006.190.07:49:32.74#ibcon#read 3, iclass 16, count 0 2006.190.07:49:32.74#ibcon#about to read 4, iclass 16, count 0 2006.190.07:49:32.74#ibcon#read 4, iclass 16, count 0 2006.190.07:49:32.74#ibcon#about to read 5, iclass 16, count 0 2006.190.07:49:32.74#ibcon#read 5, iclass 16, count 0 2006.190.07:49:32.74#ibcon#about to read 6, iclass 16, count 0 2006.190.07:49:32.74#ibcon#read 6, iclass 16, count 0 2006.190.07:49:32.74#ibcon#end of sib2, iclass 16, count 0 2006.190.07:49:32.74#ibcon#*after write, iclass 16, count 0 2006.190.07:49:32.74#ibcon#*before return 0, iclass 16, count 0 2006.190.07:49:32.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:32.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:49:32.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:49:32.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:49:32.74$vc4f8/vbbw=wide 2006.190.07:49:32.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.07:49:32.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.07:49:32.74#ibcon#ireg 8 cls_cnt 0 2006.190.07:49:32.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:49:32.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:49:32.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:49:32.81#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:49:32.81#ibcon#first serial, iclass 18, count 0 2006.190.07:49:32.81#ibcon#enter sib2, iclass 18, count 0 2006.190.07:49:32.81#ibcon#flushed, iclass 18, count 0 2006.190.07:49:32.81#ibcon#about to write, iclass 18, count 0 2006.190.07:49:32.81#ibcon#wrote, iclass 18, count 0 2006.190.07:49:32.81#ibcon#about to read 3, iclass 18, count 0 2006.190.07:49:32.83#ibcon#read 3, iclass 18, count 0 2006.190.07:49:32.83#ibcon#about to read 4, iclass 18, count 0 2006.190.07:49:32.83#ibcon#read 4, iclass 18, count 0 2006.190.07:49:32.83#ibcon#about to read 5, iclass 18, count 0 2006.190.07:49:32.83#ibcon#read 5, iclass 18, count 0 2006.190.07:49:32.83#ibcon#about to read 6, iclass 18, count 0 2006.190.07:49:32.83#ibcon#read 6, iclass 18, count 0 2006.190.07:49:32.83#ibcon#end of sib2, iclass 18, count 0 2006.190.07:49:32.83#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:49:32.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:49:32.83#ibcon#[27=BW32\r\n] 2006.190.07:49:32.83#ibcon#*before write, iclass 18, count 0 2006.190.07:49:32.83#ibcon#enter sib2, iclass 18, count 0 2006.190.07:49:32.83#ibcon#flushed, iclass 18, count 0 2006.190.07:49:32.83#ibcon#about to write, iclass 18, count 0 2006.190.07:49:32.83#ibcon#wrote, iclass 18, count 0 2006.190.07:49:32.83#ibcon#about to read 3, iclass 18, count 0 2006.190.07:49:32.86#ibcon#read 3, iclass 18, count 0 2006.190.07:49:32.86#ibcon#about to read 4, iclass 18, count 0 2006.190.07:49:32.86#ibcon#read 4, iclass 18, count 0 2006.190.07:49:32.86#ibcon#about to read 5, iclass 18, count 0 2006.190.07:49:32.86#ibcon#read 5, iclass 18, count 0 2006.190.07:49:32.86#ibcon#about to read 6, iclass 18, count 0 2006.190.07:49:32.86#ibcon#read 6, iclass 18, count 0 2006.190.07:49:32.86#ibcon#end of sib2, iclass 18, count 0 2006.190.07:49:32.86#ibcon#*after write, iclass 18, count 0 2006.190.07:49:32.86#ibcon#*before return 0, iclass 18, count 0 2006.190.07:49:32.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:49:32.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:49:32.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:49:32.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:49:32.86$4f8m12a/ifd4f 2006.190.07:49:32.86$ifd4f/lo= 2006.190.07:49:32.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:49:32.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:49:32.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:49:32.86$ifd4f/patch= 2006.190.07:49:32.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:49:32.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:49:32.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:49:32.86$4f8m12a/"form=m,16.000,1:2 2006.190.07:49:32.86$4f8m12a/"tpicd 2006.190.07:49:32.86$4f8m12a/echo=off 2006.190.07:49:32.86$4f8m12a/xlog=off 2006.190.07:49:32.86:!2006.190.07:50:00 2006.190.07:49:43.14#trakl#Source acquired 2006.190.07:49:45.14#flagr#flagr/antenna,acquired 2006.190.07:50:00.00:preob 2006.190.07:50:01.14/onsource/TRACKING 2006.190.07:50:01.14:!2006.190.07:50:10 2006.190.07:50:10.00:data_valid=on 2006.190.07:50:10.00:midob 2006.190.07:50:10.14/onsource/TRACKING 2006.190.07:50:10.14/wx/24.52,1012.0,100 2006.190.07:50:10.28/cable/+6.4694E-03 2006.190.07:50:11.37/va/01,08,usb,yes,33,35 2006.190.07:50:11.37/va/02,07,usb,yes,33,35 2006.190.07:50:11.37/va/03,06,usb,yes,35,35 2006.190.07:50:11.37/va/04,07,usb,yes,34,37 2006.190.07:50:11.37/va/05,07,usb,yes,37,40 2006.190.07:50:11.37/va/06,06,usb,yes,37,36 2006.190.07:50:11.37/va/07,06,usb,yes,37,37 2006.190.07:50:11.37/va/08,06,usb,yes,40,39 2006.190.07:50:11.60/valo/01,532.99,yes,locked 2006.190.07:50:11.60/valo/02,572.99,yes,locked 2006.190.07:50:11.60/valo/03,672.99,yes,locked 2006.190.07:50:11.60/valo/04,832.99,yes,locked 2006.190.07:50:11.60/valo/05,652.99,yes,locked 2006.190.07:50:11.60/valo/06,772.99,yes,locked 2006.190.07:50:11.60/valo/07,832.99,yes,locked 2006.190.07:50:11.60/valo/08,852.99,yes,locked 2006.190.07:50:12.69/vb/01,04,usb,yes,29,27 2006.190.07:50:12.69/vb/02,04,usb,yes,30,32 2006.190.07:50:12.69/vb/03,04,usb,yes,27,30 2006.190.07:50:12.69/vb/04,04,usb,yes,28,28 2006.190.07:50:12.69/vb/05,04,usb,yes,26,30 2006.190.07:50:12.69/vb/06,04,usb,yes,27,30 2006.190.07:50:12.69/vb/07,04,usb,yes,29,29 2006.190.07:50:12.69/vb/08,04,usb,yes,27,30 2006.190.07:50:12.93/vblo/01,632.99,yes,locked 2006.190.07:50:12.93/vblo/02,640.99,yes,locked 2006.190.07:50:12.93/vblo/03,656.99,yes,locked 2006.190.07:50:12.93/vblo/04,712.99,yes,locked 2006.190.07:50:12.93/vblo/05,744.99,yes,locked 2006.190.07:50:12.93/vblo/06,752.99,yes,locked 2006.190.07:50:12.93/vblo/07,734.99,yes,locked 2006.190.07:50:12.93/vblo/08,744.99,yes,locked 2006.190.07:50:13.08/vabw/8 2006.190.07:50:13.23/vbbw/8 2006.190.07:50:13.35/xfe/off,on,14.7 2006.190.07:50:13.72/ifatt/23,28,28,28 2006.190.07:50:14.07/fmout-gps/S +2.88E-07 2006.190.07:50:14.15:!2006.190.07:51:10 2006.190.07:51:10.00:data_valid=off 2006.190.07:51:10.00:postob 2006.190.07:51:10.13/cable/+6.4708E-03 2006.190.07:51:10.13/wx/24.51,1012.0,100 2006.190.07:51:11.08/fmout-gps/S +2.89E-07 2006.190.07:51:11.08:scan_name=190-0752,k06190,60 2006.190.07:51:11.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.190.07:51:11.14#flagr#flagr/antenna,new-source 2006.190.07:51:12.14:checkk5 2006.190.07:51:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:51:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:51:13.30/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:51:13.68/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:51:14.06/chk_obsdata//k5ts1/T1900750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:51:14.44/chk_obsdata//k5ts2/T1900750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:51:14.81/chk_obsdata//k5ts3/T1900750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:51:15.19/chk_obsdata//k5ts4/T1900750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:51:15.89/k5log//k5ts1_log_newline 2006.190.07:51:16.59/k5log//k5ts2_log_newline 2006.190.07:51:17.29/k5log//k5ts3_log_newline 2006.190.07:51:17.99/k5log//k5ts4_log_newline 2006.190.07:51:18.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:51:18.01:4f8m12a=1 2006.190.07:51:18.01$4f8m12a/echo=on 2006.190.07:51:18.01$4f8m12a/pcalon 2006.190.07:51:18.01$pcalon/"no phase cal control is implemented here 2006.190.07:51:18.01$4f8m12a/"tpicd=stop 2006.190.07:51:18.01$4f8m12a/vc4f8 2006.190.07:51:18.01$vc4f8/valo=1,532.99 2006.190.07:51:18.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.07:51:18.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.07:51:18.02#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:18.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:18.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:18.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:18.02#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:51:18.02#ibcon#first serial, iclass 25, count 0 2006.190.07:51:18.02#ibcon#enter sib2, iclass 25, count 0 2006.190.07:51:18.02#ibcon#flushed, iclass 25, count 0 2006.190.07:51:18.02#ibcon#about to write, iclass 25, count 0 2006.190.07:51:18.02#ibcon#wrote, iclass 25, count 0 2006.190.07:51:18.02#ibcon#about to read 3, iclass 25, count 0 2006.190.07:51:18.06#ibcon#read 3, iclass 25, count 0 2006.190.07:51:18.06#ibcon#about to read 4, iclass 25, count 0 2006.190.07:51:18.06#ibcon#read 4, iclass 25, count 0 2006.190.07:51:18.06#ibcon#about to read 5, iclass 25, count 0 2006.190.07:51:18.06#ibcon#read 5, iclass 25, count 0 2006.190.07:51:18.06#ibcon#about to read 6, iclass 25, count 0 2006.190.07:51:18.06#ibcon#read 6, iclass 25, count 0 2006.190.07:51:18.06#ibcon#end of sib2, iclass 25, count 0 2006.190.07:51:18.06#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:51:18.06#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:51:18.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:51:18.06#ibcon#*before write, iclass 25, count 0 2006.190.07:51:18.06#ibcon#enter sib2, iclass 25, count 0 2006.190.07:51:18.06#ibcon#flushed, iclass 25, count 0 2006.190.07:51:18.06#ibcon#about to write, iclass 25, count 0 2006.190.07:51:18.06#ibcon#wrote, iclass 25, count 0 2006.190.07:51:18.06#ibcon#about to read 3, iclass 25, count 0 2006.190.07:51:18.11#ibcon#read 3, iclass 25, count 0 2006.190.07:51:18.11#ibcon#about to read 4, iclass 25, count 0 2006.190.07:51:18.11#ibcon#read 4, iclass 25, count 0 2006.190.07:51:18.11#ibcon#about to read 5, iclass 25, count 0 2006.190.07:51:18.11#ibcon#read 5, iclass 25, count 0 2006.190.07:51:18.11#ibcon#about to read 6, iclass 25, count 0 2006.190.07:51:18.11#ibcon#read 6, iclass 25, count 0 2006.190.07:51:18.11#ibcon#end of sib2, iclass 25, count 0 2006.190.07:51:18.11#ibcon#*after write, iclass 25, count 0 2006.190.07:51:18.11#ibcon#*before return 0, iclass 25, count 0 2006.190.07:51:18.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:18.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:18.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:51:18.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:51:18.11$vc4f8/va=1,8 2006.190.07:51:18.11#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.07:51:18.11#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.07:51:18.11#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:18.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:18.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:18.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:18.11#ibcon#enter wrdev, iclass 27, count 2 2006.190.07:51:18.11#ibcon#first serial, iclass 27, count 2 2006.190.07:51:18.11#ibcon#enter sib2, iclass 27, count 2 2006.190.07:51:18.11#ibcon#flushed, iclass 27, count 2 2006.190.07:51:18.11#ibcon#about to write, iclass 27, count 2 2006.190.07:51:18.11#ibcon#wrote, iclass 27, count 2 2006.190.07:51:18.11#ibcon#about to read 3, iclass 27, count 2 2006.190.07:51:18.13#ibcon#read 3, iclass 27, count 2 2006.190.07:51:18.13#ibcon#about to read 4, iclass 27, count 2 2006.190.07:51:18.13#ibcon#read 4, iclass 27, count 2 2006.190.07:51:18.13#ibcon#about to read 5, iclass 27, count 2 2006.190.07:51:18.13#ibcon#read 5, iclass 27, count 2 2006.190.07:51:18.13#ibcon#about to read 6, iclass 27, count 2 2006.190.07:51:18.13#ibcon#read 6, iclass 27, count 2 2006.190.07:51:18.13#ibcon#end of sib2, iclass 27, count 2 2006.190.07:51:18.13#ibcon#*mode == 0, iclass 27, count 2 2006.190.07:51:18.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.07:51:18.13#ibcon#[25=AT01-08\r\n] 2006.190.07:51:18.13#ibcon#*before write, iclass 27, count 2 2006.190.07:51:18.13#ibcon#enter sib2, iclass 27, count 2 2006.190.07:51:18.13#ibcon#flushed, iclass 27, count 2 2006.190.07:51:18.13#ibcon#about to write, iclass 27, count 2 2006.190.07:51:18.13#ibcon#wrote, iclass 27, count 2 2006.190.07:51:18.13#ibcon#about to read 3, iclass 27, count 2 2006.190.07:51:18.16#ibcon#read 3, iclass 27, count 2 2006.190.07:51:18.16#ibcon#about to read 4, iclass 27, count 2 2006.190.07:51:18.16#ibcon#read 4, iclass 27, count 2 2006.190.07:51:18.16#ibcon#about to read 5, iclass 27, count 2 2006.190.07:51:18.16#ibcon#read 5, iclass 27, count 2 2006.190.07:51:18.16#ibcon#about to read 6, iclass 27, count 2 2006.190.07:51:18.16#ibcon#read 6, iclass 27, count 2 2006.190.07:51:18.16#ibcon#end of sib2, iclass 27, count 2 2006.190.07:51:18.16#ibcon#*after write, iclass 27, count 2 2006.190.07:51:18.16#ibcon#*before return 0, iclass 27, count 2 2006.190.07:51:18.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:18.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:18.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.07:51:18.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:18.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:18.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:18.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:18.28#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:51:18.28#ibcon#first serial, iclass 27, count 0 2006.190.07:51:18.28#ibcon#enter sib2, iclass 27, count 0 2006.190.07:51:18.28#ibcon#flushed, iclass 27, count 0 2006.190.07:51:18.28#ibcon#about to write, iclass 27, count 0 2006.190.07:51:18.28#ibcon#wrote, iclass 27, count 0 2006.190.07:51:18.28#ibcon#about to read 3, iclass 27, count 0 2006.190.07:51:18.30#ibcon#read 3, iclass 27, count 0 2006.190.07:51:18.30#ibcon#about to read 4, iclass 27, count 0 2006.190.07:51:18.30#ibcon#read 4, iclass 27, count 0 2006.190.07:51:18.30#ibcon#about to read 5, iclass 27, count 0 2006.190.07:51:18.30#ibcon#read 5, iclass 27, count 0 2006.190.07:51:18.30#ibcon#about to read 6, iclass 27, count 0 2006.190.07:51:18.30#ibcon#read 6, iclass 27, count 0 2006.190.07:51:18.30#ibcon#end of sib2, iclass 27, count 0 2006.190.07:51:18.30#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:51:18.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:51:18.30#ibcon#[25=USB\r\n] 2006.190.07:51:18.30#ibcon#*before write, iclass 27, count 0 2006.190.07:51:18.30#ibcon#enter sib2, iclass 27, count 0 2006.190.07:51:18.30#ibcon#flushed, iclass 27, count 0 2006.190.07:51:18.30#ibcon#about to write, iclass 27, count 0 2006.190.07:51:18.30#ibcon#wrote, iclass 27, count 0 2006.190.07:51:18.30#ibcon#about to read 3, iclass 27, count 0 2006.190.07:51:18.33#ibcon#read 3, iclass 27, count 0 2006.190.07:51:18.33#ibcon#about to read 4, iclass 27, count 0 2006.190.07:51:18.33#ibcon#read 4, iclass 27, count 0 2006.190.07:51:18.33#ibcon#about to read 5, iclass 27, count 0 2006.190.07:51:18.33#ibcon#read 5, iclass 27, count 0 2006.190.07:51:18.33#ibcon#about to read 6, iclass 27, count 0 2006.190.07:51:18.33#ibcon#read 6, iclass 27, count 0 2006.190.07:51:18.33#ibcon#end of sib2, iclass 27, count 0 2006.190.07:51:18.33#ibcon#*after write, iclass 27, count 0 2006.190.07:51:18.33#ibcon#*before return 0, iclass 27, count 0 2006.190.07:51:18.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:18.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:18.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:51:18.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:51:18.33$vc4f8/valo=2,572.99 2006.190.07:51:18.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.07:51:18.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.07:51:18.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:18.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:18.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:18.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:18.33#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:51:18.33#ibcon#first serial, iclass 29, count 0 2006.190.07:51:18.33#ibcon#enter sib2, iclass 29, count 0 2006.190.07:51:18.33#ibcon#flushed, iclass 29, count 0 2006.190.07:51:18.33#ibcon#about to write, iclass 29, count 0 2006.190.07:51:18.33#ibcon#wrote, iclass 29, count 0 2006.190.07:51:18.33#ibcon#about to read 3, iclass 29, count 0 2006.190.07:51:18.35#ibcon#read 3, iclass 29, count 0 2006.190.07:51:18.35#ibcon#about to read 4, iclass 29, count 0 2006.190.07:51:18.35#ibcon#read 4, iclass 29, count 0 2006.190.07:51:18.35#ibcon#about to read 5, iclass 29, count 0 2006.190.07:51:18.35#ibcon#read 5, iclass 29, count 0 2006.190.07:51:18.35#ibcon#about to read 6, iclass 29, count 0 2006.190.07:51:18.35#ibcon#read 6, iclass 29, count 0 2006.190.07:51:18.35#ibcon#end of sib2, iclass 29, count 0 2006.190.07:51:18.35#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:51:18.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:51:18.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:51:18.35#ibcon#*before write, iclass 29, count 0 2006.190.07:51:18.35#ibcon#enter sib2, iclass 29, count 0 2006.190.07:51:18.35#ibcon#flushed, iclass 29, count 0 2006.190.07:51:18.35#ibcon#about to write, iclass 29, count 0 2006.190.07:51:18.35#ibcon#wrote, iclass 29, count 0 2006.190.07:51:18.35#ibcon#about to read 3, iclass 29, count 0 2006.190.07:51:18.39#ibcon#read 3, iclass 29, count 0 2006.190.07:51:18.39#ibcon#about to read 4, iclass 29, count 0 2006.190.07:51:18.39#ibcon#read 4, iclass 29, count 0 2006.190.07:51:18.39#ibcon#about to read 5, iclass 29, count 0 2006.190.07:51:18.39#ibcon#read 5, iclass 29, count 0 2006.190.07:51:18.39#ibcon#about to read 6, iclass 29, count 0 2006.190.07:51:18.39#ibcon#read 6, iclass 29, count 0 2006.190.07:51:18.39#ibcon#end of sib2, iclass 29, count 0 2006.190.07:51:18.39#ibcon#*after write, iclass 29, count 0 2006.190.07:51:18.39#ibcon#*before return 0, iclass 29, count 0 2006.190.07:51:18.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:18.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:18.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:51:18.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:51:18.39$vc4f8/va=2,7 2006.190.07:51:18.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.07:51:18.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.07:51:18.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:18.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:18.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:18.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:18.45#ibcon#enter wrdev, iclass 31, count 2 2006.190.07:51:18.45#ibcon#first serial, iclass 31, count 2 2006.190.07:51:18.45#ibcon#enter sib2, iclass 31, count 2 2006.190.07:51:18.45#ibcon#flushed, iclass 31, count 2 2006.190.07:51:18.45#ibcon#about to write, iclass 31, count 2 2006.190.07:51:18.45#ibcon#wrote, iclass 31, count 2 2006.190.07:51:18.45#ibcon#about to read 3, iclass 31, count 2 2006.190.07:51:18.47#ibcon#read 3, iclass 31, count 2 2006.190.07:51:18.47#ibcon#about to read 4, iclass 31, count 2 2006.190.07:51:18.47#ibcon#read 4, iclass 31, count 2 2006.190.07:51:18.47#ibcon#about to read 5, iclass 31, count 2 2006.190.07:51:18.47#ibcon#read 5, iclass 31, count 2 2006.190.07:51:18.47#ibcon#about to read 6, iclass 31, count 2 2006.190.07:51:18.47#ibcon#read 6, iclass 31, count 2 2006.190.07:51:18.47#ibcon#end of sib2, iclass 31, count 2 2006.190.07:51:18.47#ibcon#*mode == 0, iclass 31, count 2 2006.190.07:51:18.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.07:51:18.47#ibcon#[25=AT02-07\r\n] 2006.190.07:51:18.47#ibcon#*before write, iclass 31, count 2 2006.190.07:51:18.47#ibcon#enter sib2, iclass 31, count 2 2006.190.07:51:18.47#ibcon#flushed, iclass 31, count 2 2006.190.07:51:18.47#ibcon#about to write, iclass 31, count 2 2006.190.07:51:18.47#ibcon#wrote, iclass 31, count 2 2006.190.07:51:18.47#ibcon#about to read 3, iclass 31, count 2 2006.190.07:51:18.50#ibcon#read 3, iclass 31, count 2 2006.190.07:51:18.50#ibcon#about to read 4, iclass 31, count 2 2006.190.07:51:18.50#ibcon#read 4, iclass 31, count 2 2006.190.07:51:18.50#ibcon#about to read 5, iclass 31, count 2 2006.190.07:51:18.50#ibcon#read 5, iclass 31, count 2 2006.190.07:51:18.50#ibcon#about to read 6, iclass 31, count 2 2006.190.07:51:18.50#ibcon#read 6, iclass 31, count 2 2006.190.07:51:18.50#ibcon#end of sib2, iclass 31, count 2 2006.190.07:51:18.50#ibcon#*after write, iclass 31, count 2 2006.190.07:51:18.50#ibcon#*before return 0, iclass 31, count 2 2006.190.07:51:18.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:18.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:18.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.07:51:18.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:18.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:18.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:18.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:18.62#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:51:18.62#ibcon#first serial, iclass 31, count 0 2006.190.07:51:18.62#ibcon#enter sib2, iclass 31, count 0 2006.190.07:51:18.62#ibcon#flushed, iclass 31, count 0 2006.190.07:51:18.62#ibcon#about to write, iclass 31, count 0 2006.190.07:51:18.62#ibcon#wrote, iclass 31, count 0 2006.190.07:51:18.62#ibcon#about to read 3, iclass 31, count 0 2006.190.07:51:18.64#ibcon#read 3, iclass 31, count 0 2006.190.07:51:18.64#ibcon#about to read 4, iclass 31, count 0 2006.190.07:51:18.64#ibcon#read 4, iclass 31, count 0 2006.190.07:51:18.64#ibcon#about to read 5, iclass 31, count 0 2006.190.07:51:18.64#ibcon#read 5, iclass 31, count 0 2006.190.07:51:18.64#ibcon#about to read 6, iclass 31, count 0 2006.190.07:51:18.64#ibcon#read 6, iclass 31, count 0 2006.190.07:51:18.64#ibcon#end of sib2, iclass 31, count 0 2006.190.07:51:18.64#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:51:18.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:51:18.64#ibcon#[25=USB\r\n] 2006.190.07:51:18.64#ibcon#*before write, iclass 31, count 0 2006.190.07:51:18.64#ibcon#enter sib2, iclass 31, count 0 2006.190.07:51:18.64#ibcon#flushed, iclass 31, count 0 2006.190.07:51:18.64#ibcon#about to write, iclass 31, count 0 2006.190.07:51:18.64#ibcon#wrote, iclass 31, count 0 2006.190.07:51:18.64#ibcon#about to read 3, iclass 31, count 0 2006.190.07:51:18.67#ibcon#read 3, iclass 31, count 0 2006.190.07:51:18.67#ibcon#about to read 4, iclass 31, count 0 2006.190.07:51:18.67#ibcon#read 4, iclass 31, count 0 2006.190.07:51:18.67#ibcon#about to read 5, iclass 31, count 0 2006.190.07:51:18.67#ibcon#read 5, iclass 31, count 0 2006.190.07:51:18.67#ibcon#about to read 6, iclass 31, count 0 2006.190.07:51:18.67#ibcon#read 6, iclass 31, count 0 2006.190.07:51:18.67#ibcon#end of sib2, iclass 31, count 0 2006.190.07:51:18.67#ibcon#*after write, iclass 31, count 0 2006.190.07:51:18.67#ibcon#*before return 0, iclass 31, count 0 2006.190.07:51:18.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:18.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:18.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:51:18.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:51:18.67$vc4f8/valo=3,672.99 2006.190.07:51:18.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.07:51:18.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.07:51:18.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:18.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:18.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:18.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:18.67#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:51:18.67#ibcon#first serial, iclass 33, count 0 2006.190.07:51:18.67#ibcon#enter sib2, iclass 33, count 0 2006.190.07:51:18.67#ibcon#flushed, iclass 33, count 0 2006.190.07:51:18.67#ibcon#about to write, iclass 33, count 0 2006.190.07:51:18.67#ibcon#wrote, iclass 33, count 0 2006.190.07:51:18.67#ibcon#about to read 3, iclass 33, count 0 2006.190.07:51:18.69#ibcon#read 3, iclass 33, count 0 2006.190.07:51:18.69#ibcon#about to read 4, iclass 33, count 0 2006.190.07:51:18.69#ibcon#read 4, iclass 33, count 0 2006.190.07:51:18.69#ibcon#about to read 5, iclass 33, count 0 2006.190.07:51:18.69#ibcon#read 5, iclass 33, count 0 2006.190.07:51:18.69#ibcon#about to read 6, iclass 33, count 0 2006.190.07:51:18.69#ibcon#read 6, iclass 33, count 0 2006.190.07:51:18.69#ibcon#end of sib2, iclass 33, count 0 2006.190.07:51:18.69#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:51:18.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:51:18.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:51:18.69#ibcon#*before write, iclass 33, count 0 2006.190.07:51:18.69#ibcon#enter sib2, iclass 33, count 0 2006.190.07:51:18.69#ibcon#flushed, iclass 33, count 0 2006.190.07:51:18.69#ibcon#about to write, iclass 33, count 0 2006.190.07:51:18.69#ibcon#wrote, iclass 33, count 0 2006.190.07:51:18.69#ibcon#about to read 3, iclass 33, count 0 2006.190.07:51:18.73#ibcon#read 3, iclass 33, count 0 2006.190.07:51:18.73#ibcon#about to read 4, iclass 33, count 0 2006.190.07:51:18.73#ibcon#read 4, iclass 33, count 0 2006.190.07:51:18.73#ibcon#about to read 5, iclass 33, count 0 2006.190.07:51:18.73#ibcon#read 5, iclass 33, count 0 2006.190.07:51:18.73#ibcon#about to read 6, iclass 33, count 0 2006.190.07:51:18.73#ibcon#read 6, iclass 33, count 0 2006.190.07:51:18.73#ibcon#end of sib2, iclass 33, count 0 2006.190.07:51:18.73#ibcon#*after write, iclass 33, count 0 2006.190.07:51:18.73#ibcon#*before return 0, iclass 33, count 0 2006.190.07:51:18.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:18.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:18.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:51:18.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:51:18.73$vc4f8/va=3,6 2006.190.07:51:18.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.07:51:18.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.07:51:18.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:18.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:18.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:18.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:18.79#ibcon#enter wrdev, iclass 35, count 2 2006.190.07:51:18.79#ibcon#first serial, iclass 35, count 2 2006.190.07:51:18.79#ibcon#enter sib2, iclass 35, count 2 2006.190.07:51:18.79#ibcon#flushed, iclass 35, count 2 2006.190.07:51:18.79#ibcon#about to write, iclass 35, count 2 2006.190.07:51:18.79#ibcon#wrote, iclass 35, count 2 2006.190.07:51:18.79#ibcon#about to read 3, iclass 35, count 2 2006.190.07:51:18.81#ibcon#read 3, iclass 35, count 2 2006.190.07:51:18.81#ibcon#about to read 4, iclass 35, count 2 2006.190.07:51:18.81#ibcon#read 4, iclass 35, count 2 2006.190.07:51:18.81#ibcon#about to read 5, iclass 35, count 2 2006.190.07:51:18.81#ibcon#read 5, iclass 35, count 2 2006.190.07:51:18.81#ibcon#about to read 6, iclass 35, count 2 2006.190.07:51:18.81#ibcon#read 6, iclass 35, count 2 2006.190.07:51:18.81#ibcon#end of sib2, iclass 35, count 2 2006.190.07:51:18.81#ibcon#*mode == 0, iclass 35, count 2 2006.190.07:51:18.81#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.07:51:18.81#ibcon#[25=AT03-06\r\n] 2006.190.07:51:18.81#ibcon#*before write, iclass 35, count 2 2006.190.07:51:18.81#ibcon#enter sib2, iclass 35, count 2 2006.190.07:51:18.81#ibcon#flushed, iclass 35, count 2 2006.190.07:51:18.81#ibcon#about to write, iclass 35, count 2 2006.190.07:51:18.81#ibcon#wrote, iclass 35, count 2 2006.190.07:51:18.81#ibcon#about to read 3, iclass 35, count 2 2006.190.07:51:18.84#ibcon#read 3, iclass 35, count 2 2006.190.07:51:18.84#ibcon#about to read 4, iclass 35, count 2 2006.190.07:51:18.84#ibcon#read 4, iclass 35, count 2 2006.190.07:51:18.84#ibcon#about to read 5, iclass 35, count 2 2006.190.07:51:18.84#ibcon#read 5, iclass 35, count 2 2006.190.07:51:18.84#ibcon#about to read 6, iclass 35, count 2 2006.190.07:51:18.84#ibcon#read 6, iclass 35, count 2 2006.190.07:51:18.84#ibcon#end of sib2, iclass 35, count 2 2006.190.07:51:18.84#ibcon#*after write, iclass 35, count 2 2006.190.07:51:18.84#ibcon#*before return 0, iclass 35, count 2 2006.190.07:51:18.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:18.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:18.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.07:51:18.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:18.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:18.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:18.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:18.96#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:51:18.96#ibcon#first serial, iclass 35, count 0 2006.190.07:51:18.96#ibcon#enter sib2, iclass 35, count 0 2006.190.07:51:18.96#ibcon#flushed, iclass 35, count 0 2006.190.07:51:18.96#ibcon#about to write, iclass 35, count 0 2006.190.07:51:18.96#ibcon#wrote, iclass 35, count 0 2006.190.07:51:18.96#ibcon#about to read 3, iclass 35, count 0 2006.190.07:51:18.98#ibcon#read 3, iclass 35, count 0 2006.190.07:51:18.98#ibcon#about to read 4, iclass 35, count 0 2006.190.07:51:18.98#ibcon#read 4, iclass 35, count 0 2006.190.07:51:18.98#ibcon#about to read 5, iclass 35, count 0 2006.190.07:51:18.98#ibcon#read 5, iclass 35, count 0 2006.190.07:51:18.98#ibcon#about to read 6, iclass 35, count 0 2006.190.07:51:18.98#ibcon#read 6, iclass 35, count 0 2006.190.07:51:18.98#ibcon#end of sib2, iclass 35, count 0 2006.190.07:51:18.98#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:51:18.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:51:18.98#ibcon#[25=USB\r\n] 2006.190.07:51:18.98#ibcon#*before write, iclass 35, count 0 2006.190.07:51:18.98#ibcon#enter sib2, iclass 35, count 0 2006.190.07:51:18.98#ibcon#flushed, iclass 35, count 0 2006.190.07:51:18.98#ibcon#about to write, iclass 35, count 0 2006.190.07:51:18.98#ibcon#wrote, iclass 35, count 0 2006.190.07:51:18.98#ibcon#about to read 3, iclass 35, count 0 2006.190.07:51:19.01#ibcon#read 3, iclass 35, count 0 2006.190.07:51:19.01#ibcon#about to read 4, iclass 35, count 0 2006.190.07:51:19.01#ibcon#read 4, iclass 35, count 0 2006.190.07:51:19.01#ibcon#about to read 5, iclass 35, count 0 2006.190.07:51:19.01#ibcon#read 5, iclass 35, count 0 2006.190.07:51:19.01#ibcon#about to read 6, iclass 35, count 0 2006.190.07:51:19.01#ibcon#read 6, iclass 35, count 0 2006.190.07:51:19.01#ibcon#end of sib2, iclass 35, count 0 2006.190.07:51:19.01#ibcon#*after write, iclass 35, count 0 2006.190.07:51:19.01#ibcon#*before return 0, iclass 35, count 0 2006.190.07:51:19.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:19.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:19.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:51:19.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:51:19.01$vc4f8/valo=4,832.99 2006.190.07:51:19.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.07:51:19.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.07:51:19.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:19.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:19.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:19.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:19.01#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:51:19.01#ibcon#first serial, iclass 37, count 0 2006.190.07:51:19.01#ibcon#enter sib2, iclass 37, count 0 2006.190.07:51:19.01#ibcon#flushed, iclass 37, count 0 2006.190.07:51:19.01#ibcon#about to write, iclass 37, count 0 2006.190.07:51:19.01#ibcon#wrote, iclass 37, count 0 2006.190.07:51:19.01#ibcon#about to read 3, iclass 37, count 0 2006.190.07:51:19.03#ibcon#read 3, iclass 37, count 0 2006.190.07:51:19.03#ibcon#about to read 4, iclass 37, count 0 2006.190.07:51:19.03#ibcon#read 4, iclass 37, count 0 2006.190.07:51:19.03#ibcon#about to read 5, iclass 37, count 0 2006.190.07:51:19.03#ibcon#read 5, iclass 37, count 0 2006.190.07:51:19.03#ibcon#about to read 6, iclass 37, count 0 2006.190.07:51:19.03#ibcon#read 6, iclass 37, count 0 2006.190.07:51:19.03#ibcon#end of sib2, iclass 37, count 0 2006.190.07:51:19.03#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:51:19.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:51:19.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:51:19.03#ibcon#*before write, iclass 37, count 0 2006.190.07:51:19.03#ibcon#enter sib2, iclass 37, count 0 2006.190.07:51:19.03#ibcon#flushed, iclass 37, count 0 2006.190.07:51:19.03#ibcon#about to write, iclass 37, count 0 2006.190.07:51:19.03#ibcon#wrote, iclass 37, count 0 2006.190.07:51:19.03#ibcon#about to read 3, iclass 37, count 0 2006.190.07:51:19.07#ibcon#read 3, iclass 37, count 0 2006.190.07:51:19.07#ibcon#about to read 4, iclass 37, count 0 2006.190.07:51:19.07#ibcon#read 4, iclass 37, count 0 2006.190.07:51:19.07#ibcon#about to read 5, iclass 37, count 0 2006.190.07:51:19.07#ibcon#read 5, iclass 37, count 0 2006.190.07:51:19.07#ibcon#about to read 6, iclass 37, count 0 2006.190.07:51:19.07#ibcon#read 6, iclass 37, count 0 2006.190.07:51:19.07#ibcon#end of sib2, iclass 37, count 0 2006.190.07:51:19.07#ibcon#*after write, iclass 37, count 0 2006.190.07:51:19.07#ibcon#*before return 0, iclass 37, count 0 2006.190.07:51:19.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:19.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:19.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:51:19.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:51:19.07$vc4f8/va=4,7 2006.190.07:51:19.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.07:51:19.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.07:51:19.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:19.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:19.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:19.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:19.13#ibcon#enter wrdev, iclass 39, count 2 2006.190.07:51:19.13#ibcon#first serial, iclass 39, count 2 2006.190.07:51:19.13#ibcon#enter sib2, iclass 39, count 2 2006.190.07:51:19.13#ibcon#flushed, iclass 39, count 2 2006.190.07:51:19.13#ibcon#about to write, iclass 39, count 2 2006.190.07:51:19.13#ibcon#wrote, iclass 39, count 2 2006.190.07:51:19.13#ibcon#about to read 3, iclass 39, count 2 2006.190.07:51:19.15#ibcon#read 3, iclass 39, count 2 2006.190.07:51:19.15#ibcon#about to read 4, iclass 39, count 2 2006.190.07:51:19.15#ibcon#read 4, iclass 39, count 2 2006.190.07:51:19.15#ibcon#about to read 5, iclass 39, count 2 2006.190.07:51:19.15#ibcon#read 5, iclass 39, count 2 2006.190.07:51:19.15#ibcon#about to read 6, iclass 39, count 2 2006.190.07:51:19.15#ibcon#read 6, iclass 39, count 2 2006.190.07:51:19.15#ibcon#end of sib2, iclass 39, count 2 2006.190.07:51:19.15#ibcon#*mode == 0, iclass 39, count 2 2006.190.07:51:19.15#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.07:51:19.15#ibcon#[25=AT04-07\r\n] 2006.190.07:51:19.15#ibcon#*before write, iclass 39, count 2 2006.190.07:51:19.15#ibcon#enter sib2, iclass 39, count 2 2006.190.07:51:19.15#ibcon#flushed, iclass 39, count 2 2006.190.07:51:19.15#ibcon#about to write, iclass 39, count 2 2006.190.07:51:19.15#ibcon#wrote, iclass 39, count 2 2006.190.07:51:19.15#ibcon#about to read 3, iclass 39, count 2 2006.190.07:51:19.18#ibcon#read 3, iclass 39, count 2 2006.190.07:51:19.18#ibcon#about to read 4, iclass 39, count 2 2006.190.07:51:19.18#ibcon#read 4, iclass 39, count 2 2006.190.07:51:19.18#ibcon#about to read 5, iclass 39, count 2 2006.190.07:51:19.18#ibcon#read 5, iclass 39, count 2 2006.190.07:51:19.18#ibcon#about to read 6, iclass 39, count 2 2006.190.07:51:19.18#ibcon#read 6, iclass 39, count 2 2006.190.07:51:19.18#ibcon#end of sib2, iclass 39, count 2 2006.190.07:51:19.18#ibcon#*after write, iclass 39, count 2 2006.190.07:51:19.18#ibcon#*before return 0, iclass 39, count 2 2006.190.07:51:19.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:19.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:19.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.07:51:19.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:19.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:19.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:19.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:19.30#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:51:19.30#ibcon#first serial, iclass 39, count 0 2006.190.07:51:19.30#ibcon#enter sib2, iclass 39, count 0 2006.190.07:51:19.30#ibcon#flushed, iclass 39, count 0 2006.190.07:51:19.30#ibcon#about to write, iclass 39, count 0 2006.190.07:51:19.30#ibcon#wrote, iclass 39, count 0 2006.190.07:51:19.30#ibcon#about to read 3, iclass 39, count 0 2006.190.07:51:19.32#ibcon#read 3, iclass 39, count 0 2006.190.07:51:19.32#ibcon#about to read 4, iclass 39, count 0 2006.190.07:51:19.32#ibcon#read 4, iclass 39, count 0 2006.190.07:51:19.32#ibcon#about to read 5, iclass 39, count 0 2006.190.07:51:19.32#ibcon#read 5, iclass 39, count 0 2006.190.07:51:19.32#ibcon#about to read 6, iclass 39, count 0 2006.190.07:51:19.32#ibcon#read 6, iclass 39, count 0 2006.190.07:51:19.32#ibcon#end of sib2, iclass 39, count 0 2006.190.07:51:19.32#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:51:19.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:51:19.32#ibcon#[25=USB\r\n] 2006.190.07:51:19.32#ibcon#*before write, iclass 39, count 0 2006.190.07:51:19.32#ibcon#enter sib2, iclass 39, count 0 2006.190.07:51:19.32#ibcon#flushed, iclass 39, count 0 2006.190.07:51:19.32#ibcon#about to write, iclass 39, count 0 2006.190.07:51:19.32#ibcon#wrote, iclass 39, count 0 2006.190.07:51:19.32#ibcon#about to read 3, iclass 39, count 0 2006.190.07:51:19.35#ibcon#read 3, iclass 39, count 0 2006.190.07:51:19.35#ibcon#about to read 4, iclass 39, count 0 2006.190.07:51:19.35#ibcon#read 4, iclass 39, count 0 2006.190.07:51:19.35#ibcon#about to read 5, iclass 39, count 0 2006.190.07:51:19.35#ibcon#read 5, iclass 39, count 0 2006.190.07:51:19.35#ibcon#about to read 6, iclass 39, count 0 2006.190.07:51:19.35#ibcon#read 6, iclass 39, count 0 2006.190.07:51:19.35#ibcon#end of sib2, iclass 39, count 0 2006.190.07:51:19.35#ibcon#*after write, iclass 39, count 0 2006.190.07:51:19.35#ibcon#*before return 0, iclass 39, count 0 2006.190.07:51:19.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:19.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:19.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:51:19.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:51:19.35$vc4f8/valo=5,652.99 2006.190.07:51:19.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.07:51:19.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.07:51:19.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:19.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:19.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:19.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:19.35#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:51:19.35#ibcon#first serial, iclass 3, count 0 2006.190.07:51:19.35#ibcon#enter sib2, iclass 3, count 0 2006.190.07:51:19.35#ibcon#flushed, iclass 3, count 0 2006.190.07:51:19.35#ibcon#about to write, iclass 3, count 0 2006.190.07:51:19.35#ibcon#wrote, iclass 3, count 0 2006.190.07:51:19.35#ibcon#about to read 3, iclass 3, count 0 2006.190.07:51:19.37#ibcon#read 3, iclass 3, count 0 2006.190.07:51:19.37#ibcon#about to read 4, iclass 3, count 0 2006.190.07:51:19.37#ibcon#read 4, iclass 3, count 0 2006.190.07:51:19.37#ibcon#about to read 5, iclass 3, count 0 2006.190.07:51:19.37#ibcon#read 5, iclass 3, count 0 2006.190.07:51:19.37#ibcon#about to read 6, iclass 3, count 0 2006.190.07:51:19.37#ibcon#read 6, iclass 3, count 0 2006.190.07:51:19.37#ibcon#end of sib2, iclass 3, count 0 2006.190.07:51:19.37#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:51:19.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:51:19.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:51:19.37#ibcon#*before write, iclass 3, count 0 2006.190.07:51:19.37#ibcon#enter sib2, iclass 3, count 0 2006.190.07:51:19.37#ibcon#flushed, iclass 3, count 0 2006.190.07:51:19.37#ibcon#about to write, iclass 3, count 0 2006.190.07:51:19.37#ibcon#wrote, iclass 3, count 0 2006.190.07:51:19.37#ibcon#about to read 3, iclass 3, count 0 2006.190.07:51:19.41#ibcon#read 3, iclass 3, count 0 2006.190.07:51:19.41#ibcon#about to read 4, iclass 3, count 0 2006.190.07:51:19.41#ibcon#read 4, iclass 3, count 0 2006.190.07:51:19.41#ibcon#about to read 5, iclass 3, count 0 2006.190.07:51:19.41#ibcon#read 5, iclass 3, count 0 2006.190.07:51:19.41#ibcon#about to read 6, iclass 3, count 0 2006.190.07:51:19.41#ibcon#read 6, iclass 3, count 0 2006.190.07:51:19.41#ibcon#end of sib2, iclass 3, count 0 2006.190.07:51:19.41#ibcon#*after write, iclass 3, count 0 2006.190.07:51:19.41#ibcon#*before return 0, iclass 3, count 0 2006.190.07:51:19.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:19.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:19.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:51:19.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:51:19.41$vc4f8/va=5,7 2006.190.07:51:19.41#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.07:51:19.41#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.07:51:19.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:19.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:19.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:19.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:19.47#ibcon#enter wrdev, iclass 5, count 2 2006.190.07:51:19.47#ibcon#first serial, iclass 5, count 2 2006.190.07:51:19.47#ibcon#enter sib2, iclass 5, count 2 2006.190.07:51:19.47#ibcon#flushed, iclass 5, count 2 2006.190.07:51:19.47#ibcon#about to write, iclass 5, count 2 2006.190.07:51:19.47#ibcon#wrote, iclass 5, count 2 2006.190.07:51:19.47#ibcon#about to read 3, iclass 5, count 2 2006.190.07:51:19.49#ibcon#read 3, iclass 5, count 2 2006.190.07:51:19.49#ibcon#about to read 4, iclass 5, count 2 2006.190.07:51:19.49#ibcon#read 4, iclass 5, count 2 2006.190.07:51:19.49#ibcon#about to read 5, iclass 5, count 2 2006.190.07:51:19.49#ibcon#read 5, iclass 5, count 2 2006.190.07:51:19.49#ibcon#about to read 6, iclass 5, count 2 2006.190.07:51:19.49#ibcon#read 6, iclass 5, count 2 2006.190.07:51:19.49#ibcon#end of sib2, iclass 5, count 2 2006.190.07:51:19.49#ibcon#*mode == 0, iclass 5, count 2 2006.190.07:51:19.49#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.07:51:19.49#ibcon#[25=AT05-07\r\n] 2006.190.07:51:19.49#ibcon#*before write, iclass 5, count 2 2006.190.07:51:19.49#ibcon#enter sib2, iclass 5, count 2 2006.190.07:51:19.49#ibcon#flushed, iclass 5, count 2 2006.190.07:51:19.49#ibcon#about to write, iclass 5, count 2 2006.190.07:51:19.49#ibcon#wrote, iclass 5, count 2 2006.190.07:51:19.49#ibcon#about to read 3, iclass 5, count 2 2006.190.07:51:19.52#ibcon#read 3, iclass 5, count 2 2006.190.07:51:19.52#ibcon#about to read 4, iclass 5, count 2 2006.190.07:51:19.52#ibcon#read 4, iclass 5, count 2 2006.190.07:51:19.52#ibcon#about to read 5, iclass 5, count 2 2006.190.07:51:19.52#ibcon#read 5, iclass 5, count 2 2006.190.07:51:19.52#ibcon#about to read 6, iclass 5, count 2 2006.190.07:51:19.52#ibcon#read 6, iclass 5, count 2 2006.190.07:51:19.52#ibcon#end of sib2, iclass 5, count 2 2006.190.07:51:19.52#ibcon#*after write, iclass 5, count 2 2006.190.07:51:19.52#ibcon#*before return 0, iclass 5, count 2 2006.190.07:51:19.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:19.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:19.52#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.07:51:19.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:19.52#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:19.64#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:19.64#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:19.64#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:51:19.64#ibcon#first serial, iclass 5, count 0 2006.190.07:51:19.64#ibcon#enter sib2, iclass 5, count 0 2006.190.07:51:19.64#ibcon#flushed, iclass 5, count 0 2006.190.07:51:19.64#ibcon#about to write, iclass 5, count 0 2006.190.07:51:19.64#ibcon#wrote, iclass 5, count 0 2006.190.07:51:19.64#ibcon#about to read 3, iclass 5, count 0 2006.190.07:51:19.66#ibcon#read 3, iclass 5, count 0 2006.190.07:51:19.66#ibcon#about to read 4, iclass 5, count 0 2006.190.07:51:19.66#ibcon#read 4, iclass 5, count 0 2006.190.07:51:19.66#ibcon#about to read 5, iclass 5, count 0 2006.190.07:51:19.66#ibcon#read 5, iclass 5, count 0 2006.190.07:51:19.66#ibcon#about to read 6, iclass 5, count 0 2006.190.07:51:19.66#ibcon#read 6, iclass 5, count 0 2006.190.07:51:19.66#ibcon#end of sib2, iclass 5, count 0 2006.190.07:51:19.66#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:51:19.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:51:19.66#ibcon#[25=USB\r\n] 2006.190.07:51:19.66#ibcon#*before write, iclass 5, count 0 2006.190.07:51:19.66#ibcon#enter sib2, iclass 5, count 0 2006.190.07:51:19.66#ibcon#flushed, iclass 5, count 0 2006.190.07:51:19.66#ibcon#about to write, iclass 5, count 0 2006.190.07:51:19.66#ibcon#wrote, iclass 5, count 0 2006.190.07:51:19.66#ibcon#about to read 3, iclass 5, count 0 2006.190.07:51:19.69#ibcon#read 3, iclass 5, count 0 2006.190.07:51:19.69#ibcon#about to read 4, iclass 5, count 0 2006.190.07:51:19.69#ibcon#read 4, iclass 5, count 0 2006.190.07:51:19.69#ibcon#about to read 5, iclass 5, count 0 2006.190.07:51:19.69#ibcon#read 5, iclass 5, count 0 2006.190.07:51:19.69#ibcon#about to read 6, iclass 5, count 0 2006.190.07:51:19.69#ibcon#read 6, iclass 5, count 0 2006.190.07:51:19.69#ibcon#end of sib2, iclass 5, count 0 2006.190.07:51:19.69#ibcon#*after write, iclass 5, count 0 2006.190.07:51:19.69#ibcon#*before return 0, iclass 5, count 0 2006.190.07:51:19.69#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:19.69#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:19.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:51:19.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:51:19.69$vc4f8/valo=6,772.99 2006.190.07:51:19.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.07:51:19.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.07:51:19.69#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:19.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:51:19.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:51:19.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:51:19.69#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:51:19.69#ibcon#first serial, iclass 10, count 0 2006.190.07:51:19.69#ibcon#enter sib2, iclass 10, count 0 2006.190.07:51:19.69#ibcon#flushed, iclass 10, count 0 2006.190.07:51:19.69#ibcon#about to write, iclass 10, count 0 2006.190.07:51:19.69#ibcon#wrote, iclass 10, count 0 2006.190.07:51:19.69#ibcon#about to read 3, iclass 10, count 0 2006.190.07:51:19.70#abcon#<5=/04 2.1 3.6 24.511001012.0\r\n> 2006.190.07:51:19.71#ibcon#read 3, iclass 10, count 0 2006.190.07:51:19.71#ibcon#about to read 4, iclass 10, count 0 2006.190.07:51:19.71#ibcon#read 4, iclass 10, count 0 2006.190.07:51:19.71#ibcon#about to read 5, iclass 10, count 0 2006.190.07:51:19.71#ibcon#read 5, iclass 10, count 0 2006.190.07:51:19.71#ibcon#about to read 6, iclass 10, count 0 2006.190.07:51:19.71#ibcon#read 6, iclass 10, count 0 2006.190.07:51:19.71#ibcon#end of sib2, iclass 10, count 0 2006.190.07:51:19.71#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:51:19.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:51:19.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:51:19.71#ibcon#*before write, iclass 10, count 0 2006.190.07:51:19.71#ibcon#enter sib2, iclass 10, count 0 2006.190.07:51:19.71#ibcon#flushed, iclass 10, count 0 2006.190.07:51:19.71#ibcon#about to write, iclass 10, count 0 2006.190.07:51:19.71#ibcon#wrote, iclass 10, count 0 2006.190.07:51:19.71#ibcon#about to read 3, iclass 10, count 0 2006.190.07:51:19.72#abcon#{5=INTERFACE CLEAR} 2006.190.07:51:19.75#ibcon#read 3, iclass 10, count 0 2006.190.07:51:19.75#ibcon#about to read 4, iclass 10, count 0 2006.190.07:51:19.75#ibcon#read 4, iclass 10, count 0 2006.190.07:51:19.75#ibcon#about to read 5, iclass 10, count 0 2006.190.07:51:19.75#ibcon#read 5, iclass 10, count 0 2006.190.07:51:19.75#ibcon#about to read 6, iclass 10, count 0 2006.190.07:51:19.75#ibcon#read 6, iclass 10, count 0 2006.190.07:51:19.75#ibcon#end of sib2, iclass 10, count 0 2006.190.07:51:19.75#ibcon#*after write, iclass 10, count 0 2006.190.07:51:19.75#ibcon#*before return 0, iclass 10, count 0 2006.190.07:51:19.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:51:19.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:51:19.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:51:19.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:51:19.75$vc4f8/va=6,6 2006.190.07:51:19.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:51:19.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:51:19.75#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:19.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:51:19.78#abcon#[5=S1D000X0/0*\r\n] 2006.190.07:51:19.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:51:19.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:51:19.81#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:51:19.81#ibcon#first serial, iclass 14, count 2 2006.190.07:51:19.81#ibcon#enter sib2, iclass 14, count 2 2006.190.07:51:19.81#ibcon#flushed, iclass 14, count 2 2006.190.07:51:19.81#ibcon#about to write, iclass 14, count 2 2006.190.07:51:19.81#ibcon#wrote, iclass 14, count 2 2006.190.07:51:19.81#ibcon#about to read 3, iclass 14, count 2 2006.190.07:51:19.83#ibcon#read 3, iclass 14, count 2 2006.190.07:51:19.83#ibcon#about to read 4, iclass 14, count 2 2006.190.07:51:19.83#ibcon#read 4, iclass 14, count 2 2006.190.07:51:19.83#ibcon#about to read 5, iclass 14, count 2 2006.190.07:51:19.83#ibcon#read 5, iclass 14, count 2 2006.190.07:51:19.83#ibcon#about to read 6, iclass 14, count 2 2006.190.07:51:19.83#ibcon#read 6, iclass 14, count 2 2006.190.07:51:19.83#ibcon#end of sib2, iclass 14, count 2 2006.190.07:51:19.83#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:51:19.83#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:51:19.83#ibcon#[25=AT06-06\r\n] 2006.190.07:51:19.83#ibcon#*before write, iclass 14, count 2 2006.190.07:51:19.83#ibcon#enter sib2, iclass 14, count 2 2006.190.07:51:19.83#ibcon#flushed, iclass 14, count 2 2006.190.07:51:19.83#ibcon#about to write, iclass 14, count 2 2006.190.07:51:19.83#ibcon#wrote, iclass 14, count 2 2006.190.07:51:19.83#ibcon#about to read 3, iclass 14, count 2 2006.190.07:51:19.86#ibcon#read 3, iclass 14, count 2 2006.190.07:51:19.86#ibcon#about to read 4, iclass 14, count 2 2006.190.07:51:19.86#ibcon#read 4, iclass 14, count 2 2006.190.07:51:19.86#ibcon#about to read 5, iclass 14, count 2 2006.190.07:51:19.86#ibcon#read 5, iclass 14, count 2 2006.190.07:51:19.86#ibcon#about to read 6, iclass 14, count 2 2006.190.07:51:19.86#ibcon#read 6, iclass 14, count 2 2006.190.07:51:19.86#ibcon#end of sib2, iclass 14, count 2 2006.190.07:51:19.86#ibcon#*after write, iclass 14, count 2 2006.190.07:51:19.86#ibcon#*before return 0, iclass 14, count 2 2006.190.07:51:19.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:51:19.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:51:19.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:51:19.86#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:19.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:51:19.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:51:19.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:51:19.98#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:51:19.98#ibcon#first serial, iclass 14, count 0 2006.190.07:51:19.98#ibcon#enter sib2, iclass 14, count 0 2006.190.07:51:19.98#ibcon#flushed, iclass 14, count 0 2006.190.07:51:19.98#ibcon#about to write, iclass 14, count 0 2006.190.07:51:19.98#ibcon#wrote, iclass 14, count 0 2006.190.07:51:19.98#ibcon#about to read 3, iclass 14, count 0 2006.190.07:51:20.00#ibcon#read 3, iclass 14, count 0 2006.190.07:51:20.00#ibcon#about to read 4, iclass 14, count 0 2006.190.07:51:20.00#ibcon#read 4, iclass 14, count 0 2006.190.07:51:20.00#ibcon#about to read 5, iclass 14, count 0 2006.190.07:51:20.00#ibcon#read 5, iclass 14, count 0 2006.190.07:51:20.00#ibcon#about to read 6, iclass 14, count 0 2006.190.07:51:20.00#ibcon#read 6, iclass 14, count 0 2006.190.07:51:20.00#ibcon#end of sib2, iclass 14, count 0 2006.190.07:51:20.00#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:51:20.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:51:20.00#ibcon#[25=USB\r\n] 2006.190.07:51:20.00#ibcon#*before write, iclass 14, count 0 2006.190.07:51:20.00#ibcon#enter sib2, iclass 14, count 0 2006.190.07:51:20.00#ibcon#flushed, iclass 14, count 0 2006.190.07:51:20.00#ibcon#about to write, iclass 14, count 0 2006.190.07:51:20.00#ibcon#wrote, iclass 14, count 0 2006.190.07:51:20.00#ibcon#about to read 3, iclass 14, count 0 2006.190.07:51:20.03#ibcon#read 3, iclass 14, count 0 2006.190.07:51:20.03#ibcon#about to read 4, iclass 14, count 0 2006.190.07:51:20.03#ibcon#read 4, iclass 14, count 0 2006.190.07:51:20.03#ibcon#about to read 5, iclass 14, count 0 2006.190.07:51:20.03#ibcon#read 5, iclass 14, count 0 2006.190.07:51:20.03#ibcon#about to read 6, iclass 14, count 0 2006.190.07:51:20.03#ibcon#read 6, iclass 14, count 0 2006.190.07:51:20.03#ibcon#end of sib2, iclass 14, count 0 2006.190.07:51:20.03#ibcon#*after write, iclass 14, count 0 2006.190.07:51:20.03#ibcon#*before return 0, iclass 14, count 0 2006.190.07:51:20.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:51:20.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:51:20.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:51:20.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:51:20.03$vc4f8/valo=7,832.99 2006.190.07:51:20.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.07:51:20.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.07:51:20.03#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:20.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:51:20.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:51:20.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:51:20.03#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:51:20.03#ibcon#first serial, iclass 17, count 0 2006.190.07:51:20.03#ibcon#enter sib2, iclass 17, count 0 2006.190.07:51:20.03#ibcon#flushed, iclass 17, count 0 2006.190.07:51:20.03#ibcon#about to write, iclass 17, count 0 2006.190.07:51:20.03#ibcon#wrote, iclass 17, count 0 2006.190.07:51:20.03#ibcon#about to read 3, iclass 17, count 0 2006.190.07:51:20.05#ibcon#read 3, iclass 17, count 0 2006.190.07:51:20.05#ibcon#about to read 4, iclass 17, count 0 2006.190.07:51:20.05#ibcon#read 4, iclass 17, count 0 2006.190.07:51:20.05#ibcon#about to read 5, iclass 17, count 0 2006.190.07:51:20.05#ibcon#read 5, iclass 17, count 0 2006.190.07:51:20.05#ibcon#about to read 6, iclass 17, count 0 2006.190.07:51:20.05#ibcon#read 6, iclass 17, count 0 2006.190.07:51:20.05#ibcon#end of sib2, iclass 17, count 0 2006.190.07:51:20.05#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:51:20.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:51:20.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:51:20.05#ibcon#*before write, iclass 17, count 0 2006.190.07:51:20.05#ibcon#enter sib2, iclass 17, count 0 2006.190.07:51:20.05#ibcon#flushed, iclass 17, count 0 2006.190.07:51:20.05#ibcon#about to write, iclass 17, count 0 2006.190.07:51:20.05#ibcon#wrote, iclass 17, count 0 2006.190.07:51:20.05#ibcon#about to read 3, iclass 17, count 0 2006.190.07:51:20.09#ibcon#read 3, iclass 17, count 0 2006.190.07:51:20.09#ibcon#about to read 4, iclass 17, count 0 2006.190.07:51:20.09#ibcon#read 4, iclass 17, count 0 2006.190.07:51:20.09#ibcon#about to read 5, iclass 17, count 0 2006.190.07:51:20.09#ibcon#read 5, iclass 17, count 0 2006.190.07:51:20.09#ibcon#about to read 6, iclass 17, count 0 2006.190.07:51:20.09#ibcon#read 6, iclass 17, count 0 2006.190.07:51:20.09#ibcon#end of sib2, iclass 17, count 0 2006.190.07:51:20.09#ibcon#*after write, iclass 17, count 0 2006.190.07:51:20.09#ibcon#*before return 0, iclass 17, count 0 2006.190.07:51:20.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:51:20.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.07:51:20.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:51:20.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:51:20.09$vc4f8/va=7,6 2006.190.07:51:20.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.07:51:20.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.07:51:20.09#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:20.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:51:20.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:51:20.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:51:20.15#ibcon#enter wrdev, iclass 19, count 2 2006.190.07:51:20.15#ibcon#first serial, iclass 19, count 2 2006.190.07:51:20.15#ibcon#enter sib2, iclass 19, count 2 2006.190.07:51:20.15#ibcon#flushed, iclass 19, count 2 2006.190.07:51:20.15#ibcon#about to write, iclass 19, count 2 2006.190.07:51:20.15#ibcon#wrote, iclass 19, count 2 2006.190.07:51:20.15#ibcon#about to read 3, iclass 19, count 2 2006.190.07:51:20.17#ibcon#read 3, iclass 19, count 2 2006.190.07:51:20.17#ibcon#about to read 4, iclass 19, count 2 2006.190.07:51:20.17#ibcon#read 4, iclass 19, count 2 2006.190.07:51:20.17#ibcon#about to read 5, iclass 19, count 2 2006.190.07:51:20.17#ibcon#read 5, iclass 19, count 2 2006.190.07:51:20.17#ibcon#about to read 6, iclass 19, count 2 2006.190.07:51:20.17#ibcon#read 6, iclass 19, count 2 2006.190.07:51:20.17#ibcon#end of sib2, iclass 19, count 2 2006.190.07:51:20.17#ibcon#*mode == 0, iclass 19, count 2 2006.190.07:51:20.17#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.07:51:20.17#ibcon#[25=AT07-06\r\n] 2006.190.07:51:20.17#ibcon#*before write, iclass 19, count 2 2006.190.07:51:20.17#ibcon#enter sib2, iclass 19, count 2 2006.190.07:51:20.17#ibcon#flushed, iclass 19, count 2 2006.190.07:51:20.17#ibcon#about to write, iclass 19, count 2 2006.190.07:51:20.17#ibcon#wrote, iclass 19, count 2 2006.190.07:51:20.17#ibcon#about to read 3, iclass 19, count 2 2006.190.07:51:20.20#ibcon#read 3, iclass 19, count 2 2006.190.07:51:20.20#ibcon#about to read 4, iclass 19, count 2 2006.190.07:51:20.20#ibcon#read 4, iclass 19, count 2 2006.190.07:51:20.20#ibcon#about to read 5, iclass 19, count 2 2006.190.07:51:20.20#ibcon#read 5, iclass 19, count 2 2006.190.07:51:20.20#ibcon#about to read 6, iclass 19, count 2 2006.190.07:51:20.20#ibcon#read 6, iclass 19, count 2 2006.190.07:51:20.20#ibcon#end of sib2, iclass 19, count 2 2006.190.07:51:20.20#ibcon#*after write, iclass 19, count 2 2006.190.07:51:20.20#ibcon#*before return 0, iclass 19, count 2 2006.190.07:51:20.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:51:20.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.07:51:20.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.07:51:20.20#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:20.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:51:20.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:51:20.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:51:20.32#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:51:20.32#ibcon#first serial, iclass 19, count 0 2006.190.07:51:20.32#ibcon#enter sib2, iclass 19, count 0 2006.190.07:51:20.32#ibcon#flushed, iclass 19, count 0 2006.190.07:51:20.32#ibcon#about to write, iclass 19, count 0 2006.190.07:51:20.32#ibcon#wrote, iclass 19, count 0 2006.190.07:51:20.32#ibcon#about to read 3, iclass 19, count 0 2006.190.07:51:20.34#ibcon#read 3, iclass 19, count 0 2006.190.07:51:20.34#ibcon#about to read 4, iclass 19, count 0 2006.190.07:51:20.34#ibcon#read 4, iclass 19, count 0 2006.190.07:51:20.34#ibcon#about to read 5, iclass 19, count 0 2006.190.07:51:20.34#ibcon#read 5, iclass 19, count 0 2006.190.07:51:20.34#ibcon#about to read 6, iclass 19, count 0 2006.190.07:51:20.34#ibcon#read 6, iclass 19, count 0 2006.190.07:51:20.34#ibcon#end of sib2, iclass 19, count 0 2006.190.07:51:20.34#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:51:20.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:51:20.34#ibcon#[25=USB\r\n] 2006.190.07:51:20.34#ibcon#*before write, iclass 19, count 0 2006.190.07:51:20.34#ibcon#enter sib2, iclass 19, count 0 2006.190.07:51:20.34#ibcon#flushed, iclass 19, count 0 2006.190.07:51:20.34#ibcon#about to write, iclass 19, count 0 2006.190.07:51:20.34#ibcon#wrote, iclass 19, count 0 2006.190.07:51:20.34#ibcon#about to read 3, iclass 19, count 0 2006.190.07:51:20.37#ibcon#read 3, iclass 19, count 0 2006.190.07:51:20.37#ibcon#about to read 4, iclass 19, count 0 2006.190.07:51:20.37#ibcon#read 4, iclass 19, count 0 2006.190.07:51:20.37#ibcon#about to read 5, iclass 19, count 0 2006.190.07:51:20.37#ibcon#read 5, iclass 19, count 0 2006.190.07:51:20.37#ibcon#about to read 6, iclass 19, count 0 2006.190.07:51:20.37#ibcon#read 6, iclass 19, count 0 2006.190.07:51:20.37#ibcon#end of sib2, iclass 19, count 0 2006.190.07:51:20.37#ibcon#*after write, iclass 19, count 0 2006.190.07:51:20.37#ibcon#*before return 0, iclass 19, count 0 2006.190.07:51:20.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:51:20.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.07:51:20.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:51:20.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:51:20.37$vc4f8/valo=8,852.99 2006.190.07:51:20.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.07:51:20.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.07:51:20.37#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:20.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:51:20.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:51:20.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:51:20.37#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:51:20.37#ibcon#first serial, iclass 21, count 0 2006.190.07:51:20.37#ibcon#enter sib2, iclass 21, count 0 2006.190.07:51:20.37#ibcon#flushed, iclass 21, count 0 2006.190.07:51:20.37#ibcon#about to write, iclass 21, count 0 2006.190.07:51:20.37#ibcon#wrote, iclass 21, count 0 2006.190.07:51:20.37#ibcon#about to read 3, iclass 21, count 0 2006.190.07:51:20.39#ibcon#read 3, iclass 21, count 0 2006.190.07:51:20.39#ibcon#about to read 4, iclass 21, count 0 2006.190.07:51:20.39#ibcon#read 4, iclass 21, count 0 2006.190.07:51:20.39#ibcon#about to read 5, iclass 21, count 0 2006.190.07:51:20.39#ibcon#read 5, iclass 21, count 0 2006.190.07:51:20.39#ibcon#about to read 6, iclass 21, count 0 2006.190.07:51:20.39#ibcon#read 6, iclass 21, count 0 2006.190.07:51:20.39#ibcon#end of sib2, iclass 21, count 0 2006.190.07:51:20.39#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:51:20.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:51:20.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:51:20.39#ibcon#*before write, iclass 21, count 0 2006.190.07:51:20.39#ibcon#enter sib2, iclass 21, count 0 2006.190.07:51:20.39#ibcon#flushed, iclass 21, count 0 2006.190.07:51:20.39#ibcon#about to write, iclass 21, count 0 2006.190.07:51:20.39#ibcon#wrote, iclass 21, count 0 2006.190.07:51:20.39#ibcon#about to read 3, iclass 21, count 0 2006.190.07:51:20.43#ibcon#read 3, iclass 21, count 0 2006.190.07:51:20.43#ibcon#about to read 4, iclass 21, count 0 2006.190.07:51:20.43#ibcon#read 4, iclass 21, count 0 2006.190.07:51:20.43#ibcon#about to read 5, iclass 21, count 0 2006.190.07:51:20.43#ibcon#read 5, iclass 21, count 0 2006.190.07:51:20.43#ibcon#about to read 6, iclass 21, count 0 2006.190.07:51:20.43#ibcon#read 6, iclass 21, count 0 2006.190.07:51:20.43#ibcon#end of sib2, iclass 21, count 0 2006.190.07:51:20.43#ibcon#*after write, iclass 21, count 0 2006.190.07:51:20.43#ibcon#*before return 0, iclass 21, count 0 2006.190.07:51:20.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:51:20.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.07:51:20.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:51:20.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:51:20.43$vc4f8/va=8,6 2006.190.07:51:20.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.07:51:20.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.07:51:20.43#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:20.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:51:20.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:51:20.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:51:20.49#ibcon#enter wrdev, iclass 23, count 2 2006.190.07:51:20.49#ibcon#first serial, iclass 23, count 2 2006.190.07:51:20.49#ibcon#enter sib2, iclass 23, count 2 2006.190.07:51:20.49#ibcon#flushed, iclass 23, count 2 2006.190.07:51:20.49#ibcon#about to write, iclass 23, count 2 2006.190.07:51:20.49#ibcon#wrote, iclass 23, count 2 2006.190.07:51:20.49#ibcon#about to read 3, iclass 23, count 2 2006.190.07:51:20.51#ibcon#read 3, iclass 23, count 2 2006.190.07:51:20.51#ibcon#about to read 4, iclass 23, count 2 2006.190.07:51:20.51#ibcon#read 4, iclass 23, count 2 2006.190.07:51:20.51#ibcon#about to read 5, iclass 23, count 2 2006.190.07:51:20.51#ibcon#read 5, iclass 23, count 2 2006.190.07:51:20.51#ibcon#about to read 6, iclass 23, count 2 2006.190.07:51:20.51#ibcon#read 6, iclass 23, count 2 2006.190.07:51:20.51#ibcon#end of sib2, iclass 23, count 2 2006.190.07:51:20.51#ibcon#*mode == 0, iclass 23, count 2 2006.190.07:51:20.51#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.07:51:20.51#ibcon#[25=AT08-06\r\n] 2006.190.07:51:20.51#ibcon#*before write, iclass 23, count 2 2006.190.07:51:20.51#ibcon#enter sib2, iclass 23, count 2 2006.190.07:51:20.51#ibcon#flushed, iclass 23, count 2 2006.190.07:51:20.51#ibcon#about to write, iclass 23, count 2 2006.190.07:51:20.51#ibcon#wrote, iclass 23, count 2 2006.190.07:51:20.51#ibcon#about to read 3, iclass 23, count 2 2006.190.07:51:20.54#ibcon#read 3, iclass 23, count 2 2006.190.07:51:20.54#ibcon#about to read 4, iclass 23, count 2 2006.190.07:51:20.54#ibcon#read 4, iclass 23, count 2 2006.190.07:51:20.54#ibcon#about to read 5, iclass 23, count 2 2006.190.07:51:20.54#ibcon#read 5, iclass 23, count 2 2006.190.07:51:20.54#ibcon#about to read 6, iclass 23, count 2 2006.190.07:51:20.54#ibcon#read 6, iclass 23, count 2 2006.190.07:51:20.54#ibcon#end of sib2, iclass 23, count 2 2006.190.07:51:20.54#ibcon#*after write, iclass 23, count 2 2006.190.07:51:20.54#ibcon#*before return 0, iclass 23, count 2 2006.190.07:51:20.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:51:20.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.07:51:20.54#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.07:51:20.54#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:20.54#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:51:20.66#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:51:20.66#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:51:20.66#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:51:20.66#ibcon#first serial, iclass 23, count 0 2006.190.07:51:20.66#ibcon#enter sib2, iclass 23, count 0 2006.190.07:51:20.66#ibcon#flushed, iclass 23, count 0 2006.190.07:51:20.66#ibcon#about to write, iclass 23, count 0 2006.190.07:51:20.66#ibcon#wrote, iclass 23, count 0 2006.190.07:51:20.66#ibcon#about to read 3, iclass 23, count 0 2006.190.07:51:20.68#ibcon#read 3, iclass 23, count 0 2006.190.07:51:20.68#ibcon#about to read 4, iclass 23, count 0 2006.190.07:51:20.68#ibcon#read 4, iclass 23, count 0 2006.190.07:51:20.68#ibcon#about to read 5, iclass 23, count 0 2006.190.07:51:20.68#ibcon#read 5, iclass 23, count 0 2006.190.07:51:20.68#ibcon#about to read 6, iclass 23, count 0 2006.190.07:51:20.68#ibcon#read 6, iclass 23, count 0 2006.190.07:51:20.68#ibcon#end of sib2, iclass 23, count 0 2006.190.07:51:20.68#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:51:20.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:51:20.68#ibcon#[25=USB\r\n] 2006.190.07:51:20.68#ibcon#*before write, iclass 23, count 0 2006.190.07:51:20.68#ibcon#enter sib2, iclass 23, count 0 2006.190.07:51:20.68#ibcon#flushed, iclass 23, count 0 2006.190.07:51:20.68#ibcon#about to write, iclass 23, count 0 2006.190.07:51:20.68#ibcon#wrote, iclass 23, count 0 2006.190.07:51:20.68#ibcon#about to read 3, iclass 23, count 0 2006.190.07:51:20.71#ibcon#read 3, iclass 23, count 0 2006.190.07:51:20.71#ibcon#about to read 4, iclass 23, count 0 2006.190.07:51:20.71#ibcon#read 4, iclass 23, count 0 2006.190.07:51:20.71#ibcon#about to read 5, iclass 23, count 0 2006.190.07:51:20.71#ibcon#read 5, iclass 23, count 0 2006.190.07:51:20.71#ibcon#about to read 6, iclass 23, count 0 2006.190.07:51:20.71#ibcon#read 6, iclass 23, count 0 2006.190.07:51:20.71#ibcon#end of sib2, iclass 23, count 0 2006.190.07:51:20.71#ibcon#*after write, iclass 23, count 0 2006.190.07:51:20.71#ibcon#*before return 0, iclass 23, count 0 2006.190.07:51:20.71#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:51:20.71#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.07:51:20.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:51:20.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:51:20.71$vc4f8/vblo=1,632.99 2006.190.07:51:20.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.07:51:20.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.07:51:20.71#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:20.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:20.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:20.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:20.71#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:51:20.71#ibcon#first serial, iclass 25, count 0 2006.190.07:51:20.71#ibcon#enter sib2, iclass 25, count 0 2006.190.07:51:20.71#ibcon#flushed, iclass 25, count 0 2006.190.07:51:20.71#ibcon#about to write, iclass 25, count 0 2006.190.07:51:20.71#ibcon#wrote, iclass 25, count 0 2006.190.07:51:20.71#ibcon#about to read 3, iclass 25, count 0 2006.190.07:51:20.73#ibcon#read 3, iclass 25, count 0 2006.190.07:51:20.73#ibcon#about to read 4, iclass 25, count 0 2006.190.07:51:20.73#ibcon#read 4, iclass 25, count 0 2006.190.07:51:20.73#ibcon#about to read 5, iclass 25, count 0 2006.190.07:51:20.73#ibcon#read 5, iclass 25, count 0 2006.190.07:51:20.73#ibcon#about to read 6, iclass 25, count 0 2006.190.07:51:20.73#ibcon#read 6, iclass 25, count 0 2006.190.07:51:20.73#ibcon#end of sib2, iclass 25, count 0 2006.190.07:51:20.73#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:51:20.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:51:20.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:51:20.73#ibcon#*before write, iclass 25, count 0 2006.190.07:51:20.73#ibcon#enter sib2, iclass 25, count 0 2006.190.07:51:20.73#ibcon#flushed, iclass 25, count 0 2006.190.07:51:20.73#ibcon#about to write, iclass 25, count 0 2006.190.07:51:20.73#ibcon#wrote, iclass 25, count 0 2006.190.07:51:20.73#ibcon#about to read 3, iclass 25, count 0 2006.190.07:51:20.77#ibcon#read 3, iclass 25, count 0 2006.190.07:51:20.77#ibcon#about to read 4, iclass 25, count 0 2006.190.07:51:20.77#ibcon#read 4, iclass 25, count 0 2006.190.07:51:20.77#ibcon#about to read 5, iclass 25, count 0 2006.190.07:51:20.77#ibcon#read 5, iclass 25, count 0 2006.190.07:51:20.77#ibcon#about to read 6, iclass 25, count 0 2006.190.07:51:20.77#ibcon#read 6, iclass 25, count 0 2006.190.07:51:20.77#ibcon#end of sib2, iclass 25, count 0 2006.190.07:51:20.77#ibcon#*after write, iclass 25, count 0 2006.190.07:51:20.77#ibcon#*before return 0, iclass 25, count 0 2006.190.07:51:20.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:20.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.07:51:20.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:51:20.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:51:20.77$vc4f8/vb=1,4 2006.190.07:51:20.77#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.07:51:20.77#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.07:51:20.77#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:20.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:20.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:20.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:20.77#ibcon#enter wrdev, iclass 27, count 2 2006.190.07:51:20.77#ibcon#first serial, iclass 27, count 2 2006.190.07:51:20.77#ibcon#enter sib2, iclass 27, count 2 2006.190.07:51:20.77#ibcon#flushed, iclass 27, count 2 2006.190.07:51:20.77#ibcon#about to write, iclass 27, count 2 2006.190.07:51:20.77#ibcon#wrote, iclass 27, count 2 2006.190.07:51:20.77#ibcon#about to read 3, iclass 27, count 2 2006.190.07:51:20.79#ibcon#read 3, iclass 27, count 2 2006.190.07:51:20.79#ibcon#about to read 4, iclass 27, count 2 2006.190.07:51:20.79#ibcon#read 4, iclass 27, count 2 2006.190.07:51:20.79#ibcon#about to read 5, iclass 27, count 2 2006.190.07:51:20.79#ibcon#read 5, iclass 27, count 2 2006.190.07:51:20.79#ibcon#about to read 6, iclass 27, count 2 2006.190.07:51:20.79#ibcon#read 6, iclass 27, count 2 2006.190.07:51:20.79#ibcon#end of sib2, iclass 27, count 2 2006.190.07:51:20.79#ibcon#*mode == 0, iclass 27, count 2 2006.190.07:51:20.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.07:51:20.79#ibcon#[27=AT01-04\r\n] 2006.190.07:51:20.79#ibcon#*before write, iclass 27, count 2 2006.190.07:51:20.79#ibcon#enter sib2, iclass 27, count 2 2006.190.07:51:20.79#ibcon#flushed, iclass 27, count 2 2006.190.07:51:20.79#ibcon#about to write, iclass 27, count 2 2006.190.07:51:20.79#ibcon#wrote, iclass 27, count 2 2006.190.07:51:20.79#ibcon#about to read 3, iclass 27, count 2 2006.190.07:51:20.82#ibcon#read 3, iclass 27, count 2 2006.190.07:51:20.82#ibcon#about to read 4, iclass 27, count 2 2006.190.07:51:20.82#ibcon#read 4, iclass 27, count 2 2006.190.07:51:20.82#ibcon#about to read 5, iclass 27, count 2 2006.190.07:51:20.82#ibcon#read 5, iclass 27, count 2 2006.190.07:51:20.82#ibcon#about to read 6, iclass 27, count 2 2006.190.07:51:20.82#ibcon#read 6, iclass 27, count 2 2006.190.07:51:20.82#ibcon#end of sib2, iclass 27, count 2 2006.190.07:51:20.82#ibcon#*after write, iclass 27, count 2 2006.190.07:51:20.82#ibcon#*before return 0, iclass 27, count 2 2006.190.07:51:20.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:20.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.07:51:20.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.07:51:20.82#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:20.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:20.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:20.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:20.94#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:51:20.94#ibcon#first serial, iclass 27, count 0 2006.190.07:51:20.94#ibcon#enter sib2, iclass 27, count 0 2006.190.07:51:20.94#ibcon#flushed, iclass 27, count 0 2006.190.07:51:20.94#ibcon#about to write, iclass 27, count 0 2006.190.07:51:20.94#ibcon#wrote, iclass 27, count 0 2006.190.07:51:20.94#ibcon#about to read 3, iclass 27, count 0 2006.190.07:51:20.96#ibcon#read 3, iclass 27, count 0 2006.190.07:51:20.96#ibcon#about to read 4, iclass 27, count 0 2006.190.07:51:20.96#ibcon#read 4, iclass 27, count 0 2006.190.07:51:20.96#ibcon#about to read 5, iclass 27, count 0 2006.190.07:51:20.96#ibcon#read 5, iclass 27, count 0 2006.190.07:51:20.96#ibcon#about to read 6, iclass 27, count 0 2006.190.07:51:20.96#ibcon#read 6, iclass 27, count 0 2006.190.07:51:20.96#ibcon#end of sib2, iclass 27, count 0 2006.190.07:51:20.96#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:51:20.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:51:20.96#ibcon#[27=USB\r\n] 2006.190.07:51:20.96#ibcon#*before write, iclass 27, count 0 2006.190.07:51:20.96#ibcon#enter sib2, iclass 27, count 0 2006.190.07:51:20.96#ibcon#flushed, iclass 27, count 0 2006.190.07:51:20.96#ibcon#about to write, iclass 27, count 0 2006.190.07:51:20.96#ibcon#wrote, iclass 27, count 0 2006.190.07:51:20.96#ibcon#about to read 3, iclass 27, count 0 2006.190.07:51:20.99#ibcon#read 3, iclass 27, count 0 2006.190.07:51:20.99#ibcon#about to read 4, iclass 27, count 0 2006.190.07:51:20.99#ibcon#read 4, iclass 27, count 0 2006.190.07:51:20.99#ibcon#about to read 5, iclass 27, count 0 2006.190.07:51:20.99#ibcon#read 5, iclass 27, count 0 2006.190.07:51:20.99#ibcon#about to read 6, iclass 27, count 0 2006.190.07:51:20.99#ibcon#read 6, iclass 27, count 0 2006.190.07:51:20.99#ibcon#end of sib2, iclass 27, count 0 2006.190.07:51:20.99#ibcon#*after write, iclass 27, count 0 2006.190.07:51:20.99#ibcon#*before return 0, iclass 27, count 0 2006.190.07:51:20.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:20.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.07:51:20.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:51:20.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:51:20.99$vc4f8/vblo=2,640.99 2006.190.07:51:20.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.07:51:20.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.07:51:20.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:20.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:20.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:20.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:20.99#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:51:20.99#ibcon#first serial, iclass 29, count 0 2006.190.07:51:20.99#ibcon#enter sib2, iclass 29, count 0 2006.190.07:51:20.99#ibcon#flushed, iclass 29, count 0 2006.190.07:51:20.99#ibcon#about to write, iclass 29, count 0 2006.190.07:51:20.99#ibcon#wrote, iclass 29, count 0 2006.190.07:51:20.99#ibcon#about to read 3, iclass 29, count 0 2006.190.07:51:21.01#ibcon#read 3, iclass 29, count 0 2006.190.07:51:21.01#ibcon#about to read 4, iclass 29, count 0 2006.190.07:51:21.01#ibcon#read 4, iclass 29, count 0 2006.190.07:51:21.01#ibcon#about to read 5, iclass 29, count 0 2006.190.07:51:21.01#ibcon#read 5, iclass 29, count 0 2006.190.07:51:21.01#ibcon#about to read 6, iclass 29, count 0 2006.190.07:51:21.01#ibcon#read 6, iclass 29, count 0 2006.190.07:51:21.01#ibcon#end of sib2, iclass 29, count 0 2006.190.07:51:21.01#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:51:21.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:51:21.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:51:21.01#ibcon#*before write, iclass 29, count 0 2006.190.07:51:21.01#ibcon#enter sib2, iclass 29, count 0 2006.190.07:51:21.01#ibcon#flushed, iclass 29, count 0 2006.190.07:51:21.01#ibcon#about to write, iclass 29, count 0 2006.190.07:51:21.01#ibcon#wrote, iclass 29, count 0 2006.190.07:51:21.01#ibcon#about to read 3, iclass 29, count 0 2006.190.07:51:21.05#ibcon#read 3, iclass 29, count 0 2006.190.07:51:21.05#ibcon#about to read 4, iclass 29, count 0 2006.190.07:51:21.05#ibcon#read 4, iclass 29, count 0 2006.190.07:51:21.05#ibcon#about to read 5, iclass 29, count 0 2006.190.07:51:21.05#ibcon#read 5, iclass 29, count 0 2006.190.07:51:21.05#ibcon#about to read 6, iclass 29, count 0 2006.190.07:51:21.05#ibcon#read 6, iclass 29, count 0 2006.190.07:51:21.05#ibcon#end of sib2, iclass 29, count 0 2006.190.07:51:21.05#ibcon#*after write, iclass 29, count 0 2006.190.07:51:21.05#ibcon#*before return 0, iclass 29, count 0 2006.190.07:51:21.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:21.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.07:51:21.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:51:21.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:51:21.05$vc4f8/vb=2,4 2006.190.07:51:21.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.07:51:21.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.07:51:21.05#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:21.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:21.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:21.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:21.11#ibcon#enter wrdev, iclass 31, count 2 2006.190.07:51:21.11#ibcon#first serial, iclass 31, count 2 2006.190.07:51:21.11#ibcon#enter sib2, iclass 31, count 2 2006.190.07:51:21.11#ibcon#flushed, iclass 31, count 2 2006.190.07:51:21.11#ibcon#about to write, iclass 31, count 2 2006.190.07:51:21.11#ibcon#wrote, iclass 31, count 2 2006.190.07:51:21.11#ibcon#about to read 3, iclass 31, count 2 2006.190.07:51:21.13#ibcon#read 3, iclass 31, count 2 2006.190.07:51:21.13#ibcon#about to read 4, iclass 31, count 2 2006.190.07:51:21.13#ibcon#read 4, iclass 31, count 2 2006.190.07:51:21.13#ibcon#about to read 5, iclass 31, count 2 2006.190.07:51:21.13#ibcon#read 5, iclass 31, count 2 2006.190.07:51:21.13#ibcon#about to read 6, iclass 31, count 2 2006.190.07:51:21.13#ibcon#read 6, iclass 31, count 2 2006.190.07:51:21.13#ibcon#end of sib2, iclass 31, count 2 2006.190.07:51:21.13#ibcon#*mode == 0, iclass 31, count 2 2006.190.07:51:21.13#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.07:51:21.13#ibcon#[27=AT02-04\r\n] 2006.190.07:51:21.13#ibcon#*before write, iclass 31, count 2 2006.190.07:51:21.13#ibcon#enter sib2, iclass 31, count 2 2006.190.07:51:21.13#ibcon#flushed, iclass 31, count 2 2006.190.07:51:21.13#ibcon#about to write, iclass 31, count 2 2006.190.07:51:21.13#ibcon#wrote, iclass 31, count 2 2006.190.07:51:21.13#ibcon#about to read 3, iclass 31, count 2 2006.190.07:51:21.16#ibcon#read 3, iclass 31, count 2 2006.190.07:51:21.16#ibcon#about to read 4, iclass 31, count 2 2006.190.07:51:21.16#ibcon#read 4, iclass 31, count 2 2006.190.07:51:21.16#ibcon#about to read 5, iclass 31, count 2 2006.190.07:51:21.16#ibcon#read 5, iclass 31, count 2 2006.190.07:51:21.16#ibcon#about to read 6, iclass 31, count 2 2006.190.07:51:21.16#ibcon#read 6, iclass 31, count 2 2006.190.07:51:21.16#ibcon#end of sib2, iclass 31, count 2 2006.190.07:51:21.16#ibcon#*after write, iclass 31, count 2 2006.190.07:51:21.16#ibcon#*before return 0, iclass 31, count 2 2006.190.07:51:21.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:21.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.07:51:21.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.07:51:21.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:21.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:21.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:21.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:21.28#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:51:21.28#ibcon#first serial, iclass 31, count 0 2006.190.07:51:21.28#ibcon#enter sib2, iclass 31, count 0 2006.190.07:51:21.28#ibcon#flushed, iclass 31, count 0 2006.190.07:51:21.28#ibcon#about to write, iclass 31, count 0 2006.190.07:51:21.28#ibcon#wrote, iclass 31, count 0 2006.190.07:51:21.28#ibcon#about to read 3, iclass 31, count 0 2006.190.07:51:21.30#ibcon#read 3, iclass 31, count 0 2006.190.07:51:21.30#ibcon#about to read 4, iclass 31, count 0 2006.190.07:51:21.30#ibcon#read 4, iclass 31, count 0 2006.190.07:51:21.30#ibcon#about to read 5, iclass 31, count 0 2006.190.07:51:21.30#ibcon#read 5, iclass 31, count 0 2006.190.07:51:21.30#ibcon#about to read 6, iclass 31, count 0 2006.190.07:51:21.30#ibcon#read 6, iclass 31, count 0 2006.190.07:51:21.30#ibcon#end of sib2, iclass 31, count 0 2006.190.07:51:21.30#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:51:21.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:51:21.30#ibcon#[27=USB\r\n] 2006.190.07:51:21.30#ibcon#*before write, iclass 31, count 0 2006.190.07:51:21.30#ibcon#enter sib2, iclass 31, count 0 2006.190.07:51:21.30#ibcon#flushed, iclass 31, count 0 2006.190.07:51:21.30#ibcon#about to write, iclass 31, count 0 2006.190.07:51:21.30#ibcon#wrote, iclass 31, count 0 2006.190.07:51:21.30#ibcon#about to read 3, iclass 31, count 0 2006.190.07:51:21.33#ibcon#read 3, iclass 31, count 0 2006.190.07:51:21.33#ibcon#about to read 4, iclass 31, count 0 2006.190.07:51:21.33#ibcon#read 4, iclass 31, count 0 2006.190.07:51:21.33#ibcon#about to read 5, iclass 31, count 0 2006.190.07:51:21.33#ibcon#read 5, iclass 31, count 0 2006.190.07:51:21.33#ibcon#about to read 6, iclass 31, count 0 2006.190.07:51:21.33#ibcon#read 6, iclass 31, count 0 2006.190.07:51:21.33#ibcon#end of sib2, iclass 31, count 0 2006.190.07:51:21.33#ibcon#*after write, iclass 31, count 0 2006.190.07:51:21.33#ibcon#*before return 0, iclass 31, count 0 2006.190.07:51:21.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:21.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.07:51:21.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:51:21.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:51:21.33$vc4f8/vblo=3,656.99 2006.190.07:51:21.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.07:51:21.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.07:51:21.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:21.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:21.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:21.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:21.33#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:51:21.33#ibcon#first serial, iclass 33, count 0 2006.190.07:51:21.33#ibcon#enter sib2, iclass 33, count 0 2006.190.07:51:21.33#ibcon#flushed, iclass 33, count 0 2006.190.07:51:21.33#ibcon#about to write, iclass 33, count 0 2006.190.07:51:21.33#ibcon#wrote, iclass 33, count 0 2006.190.07:51:21.33#ibcon#about to read 3, iclass 33, count 0 2006.190.07:51:21.35#ibcon#read 3, iclass 33, count 0 2006.190.07:51:21.35#ibcon#about to read 4, iclass 33, count 0 2006.190.07:51:21.35#ibcon#read 4, iclass 33, count 0 2006.190.07:51:21.35#ibcon#about to read 5, iclass 33, count 0 2006.190.07:51:21.35#ibcon#read 5, iclass 33, count 0 2006.190.07:51:21.35#ibcon#about to read 6, iclass 33, count 0 2006.190.07:51:21.35#ibcon#read 6, iclass 33, count 0 2006.190.07:51:21.35#ibcon#end of sib2, iclass 33, count 0 2006.190.07:51:21.35#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:51:21.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:51:21.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:51:21.35#ibcon#*before write, iclass 33, count 0 2006.190.07:51:21.35#ibcon#enter sib2, iclass 33, count 0 2006.190.07:51:21.35#ibcon#flushed, iclass 33, count 0 2006.190.07:51:21.35#ibcon#about to write, iclass 33, count 0 2006.190.07:51:21.35#ibcon#wrote, iclass 33, count 0 2006.190.07:51:21.35#ibcon#about to read 3, iclass 33, count 0 2006.190.07:51:21.39#ibcon#read 3, iclass 33, count 0 2006.190.07:51:21.39#ibcon#about to read 4, iclass 33, count 0 2006.190.07:51:21.39#ibcon#read 4, iclass 33, count 0 2006.190.07:51:21.39#ibcon#about to read 5, iclass 33, count 0 2006.190.07:51:21.39#ibcon#read 5, iclass 33, count 0 2006.190.07:51:21.39#ibcon#about to read 6, iclass 33, count 0 2006.190.07:51:21.39#ibcon#read 6, iclass 33, count 0 2006.190.07:51:21.39#ibcon#end of sib2, iclass 33, count 0 2006.190.07:51:21.39#ibcon#*after write, iclass 33, count 0 2006.190.07:51:21.39#ibcon#*before return 0, iclass 33, count 0 2006.190.07:51:21.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:21.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:51:21.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:51:21.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:51:21.39$vc4f8/vb=3,4 2006.190.07:51:21.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.07:51:21.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.07:51:21.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:21.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:21.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:21.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:21.45#ibcon#enter wrdev, iclass 35, count 2 2006.190.07:51:21.45#ibcon#first serial, iclass 35, count 2 2006.190.07:51:21.45#ibcon#enter sib2, iclass 35, count 2 2006.190.07:51:21.45#ibcon#flushed, iclass 35, count 2 2006.190.07:51:21.45#ibcon#about to write, iclass 35, count 2 2006.190.07:51:21.45#ibcon#wrote, iclass 35, count 2 2006.190.07:51:21.45#ibcon#about to read 3, iclass 35, count 2 2006.190.07:51:21.47#ibcon#read 3, iclass 35, count 2 2006.190.07:51:21.47#ibcon#about to read 4, iclass 35, count 2 2006.190.07:51:21.47#ibcon#read 4, iclass 35, count 2 2006.190.07:51:21.47#ibcon#about to read 5, iclass 35, count 2 2006.190.07:51:21.47#ibcon#read 5, iclass 35, count 2 2006.190.07:51:21.47#ibcon#about to read 6, iclass 35, count 2 2006.190.07:51:21.47#ibcon#read 6, iclass 35, count 2 2006.190.07:51:21.47#ibcon#end of sib2, iclass 35, count 2 2006.190.07:51:21.47#ibcon#*mode == 0, iclass 35, count 2 2006.190.07:51:21.47#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.07:51:21.47#ibcon#[27=AT03-04\r\n] 2006.190.07:51:21.47#ibcon#*before write, iclass 35, count 2 2006.190.07:51:21.47#ibcon#enter sib2, iclass 35, count 2 2006.190.07:51:21.47#ibcon#flushed, iclass 35, count 2 2006.190.07:51:21.47#ibcon#about to write, iclass 35, count 2 2006.190.07:51:21.47#ibcon#wrote, iclass 35, count 2 2006.190.07:51:21.47#ibcon#about to read 3, iclass 35, count 2 2006.190.07:51:21.50#ibcon#read 3, iclass 35, count 2 2006.190.07:51:21.50#ibcon#about to read 4, iclass 35, count 2 2006.190.07:51:21.50#ibcon#read 4, iclass 35, count 2 2006.190.07:51:21.50#ibcon#about to read 5, iclass 35, count 2 2006.190.07:51:21.50#ibcon#read 5, iclass 35, count 2 2006.190.07:51:21.50#ibcon#about to read 6, iclass 35, count 2 2006.190.07:51:21.50#ibcon#read 6, iclass 35, count 2 2006.190.07:51:21.50#ibcon#end of sib2, iclass 35, count 2 2006.190.07:51:21.50#ibcon#*after write, iclass 35, count 2 2006.190.07:51:21.50#ibcon#*before return 0, iclass 35, count 2 2006.190.07:51:21.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:21.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.07:51:21.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.07:51:21.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:21.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:21.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:21.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:21.62#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:51:21.62#ibcon#first serial, iclass 35, count 0 2006.190.07:51:21.62#ibcon#enter sib2, iclass 35, count 0 2006.190.07:51:21.62#ibcon#flushed, iclass 35, count 0 2006.190.07:51:21.62#ibcon#about to write, iclass 35, count 0 2006.190.07:51:21.62#ibcon#wrote, iclass 35, count 0 2006.190.07:51:21.62#ibcon#about to read 3, iclass 35, count 0 2006.190.07:51:21.64#ibcon#read 3, iclass 35, count 0 2006.190.07:51:21.64#ibcon#about to read 4, iclass 35, count 0 2006.190.07:51:21.64#ibcon#read 4, iclass 35, count 0 2006.190.07:51:21.64#ibcon#about to read 5, iclass 35, count 0 2006.190.07:51:21.64#ibcon#read 5, iclass 35, count 0 2006.190.07:51:21.64#ibcon#about to read 6, iclass 35, count 0 2006.190.07:51:21.64#ibcon#read 6, iclass 35, count 0 2006.190.07:51:21.64#ibcon#end of sib2, iclass 35, count 0 2006.190.07:51:21.64#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:51:21.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:51:21.64#ibcon#[27=USB\r\n] 2006.190.07:51:21.64#ibcon#*before write, iclass 35, count 0 2006.190.07:51:21.64#ibcon#enter sib2, iclass 35, count 0 2006.190.07:51:21.64#ibcon#flushed, iclass 35, count 0 2006.190.07:51:21.64#ibcon#about to write, iclass 35, count 0 2006.190.07:51:21.64#ibcon#wrote, iclass 35, count 0 2006.190.07:51:21.64#ibcon#about to read 3, iclass 35, count 0 2006.190.07:51:21.67#ibcon#read 3, iclass 35, count 0 2006.190.07:51:21.67#ibcon#about to read 4, iclass 35, count 0 2006.190.07:51:21.67#ibcon#read 4, iclass 35, count 0 2006.190.07:51:21.67#ibcon#about to read 5, iclass 35, count 0 2006.190.07:51:21.67#ibcon#read 5, iclass 35, count 0 2006.190.07:51:21.67#ibcon#about to read 6, iclass 35, count 0 2006.190.07:51:21.67#ibcon#read 6, iclass 35, count 0 2006.190.07:51:21.67#ibcon#end of sib2, iclass 35, count 0 2006.190.07:51:21.67#ibcon#*after write, iclass 35, count 0 2006.190.07:51:21.67#ibcon#*before return 0, iclass 35, count 0 2006.190.07:51:21.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:21.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.07:51:21.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:51:21.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:51:21.67$vc4f8/vblo=4,712.99 2006.190.07:51:21.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.07:51:21.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.07:51:21.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:21.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:21.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:21.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:21.67#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:51:21.67#ibcon#first serial, iclass 37, count 0 2006.190.07:51:21.67#ibcon#enter sib2, iclass 37, count 0 2006.190.07:51:21.67#ibcon#flushed, iclass 37, count 0 2006.190.07:51:21.67#ibcon#about to write, iclass 37, count 0 2006.190.07:51:21.67#ibcon#wrote, iclass 37, count 0 2006.190.07:51:21.67#ibcon#about to read 3, iclass 37, count 0 2006.190.07:51:21.69#ibcon#read 3, iclass 37, count 0 2006.190.07:51:21.69#ibcon#about to read 4, iclass 37, count 0 2006.190.07:51:21.69#ibcon#read 4, iclass 37, count 0 2006.190.07:51:21.69#ibcon#about to read 5, iclass 37, count 0 2006.190.07:51:21.69#ibcon#read 5, iclass 37, count 0 2006.190.07:51:21.69#ibcon#about to read 6, iclass 37, count 0 2006.190.07:51:21.69#ibcon#read 6, iclass 37, count 0 2006.190.07:51:21.69#ibcon#end of sib2, iclass 37, count 0 2006.190.07:51:21.69#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:51:21.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:51:21.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:51:21.69#ibcon#*before write, iclass 37, count 0 2006.190.07:51:21.69#ibcon#enter sib2, iclass 37, count 0 2006.190.07:51:21.69#ibcon#flushed, iclass 37, count 0 2006.190.07:51:21.69#ibcon#about to write, iclass 37, count 0 2006.190.07:51:21.69#ibcon#wrote, iclass 37, count 0 2006.190.07:51:21.69#ibcon#about to read 3, iclass 37, count 0 2006.190.07:51:21.73#ibcon#read 3, iclass 37, count 0 2006.190.07:51:21.73#ibcon#about to read 4, iclass 37, count 0 2006.190.07:51:21.73#ibcon#read 4, iclass 37, count 0 2006.190.07:51:21.73#ibcon#about to read 5, iclass 37, count 0 2006.190.07:51:21.73#ibcon#read 5, iclass 37, count 0 2006.190.07:51:21.73#ibcon#about to read 6, iclass 37, count 0 2006.190.07:51:21.73#ibcon#read 6, iclass 37, count 0 2006.190.07:51:21.73#ibcon#end of sib2, iclass 37, count 0 2006.190.07:51:21.73#ibcon#*after write, iclass 37, count 0 2006.190.07:51:21.73#ibcon#*before return 0, iclass 37, count 0 2006.190.07:51:21.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:21.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.07:51:21.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:51:21.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:51:21.73$vc4f8/vb=4,4 2006.190.07:51:21.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.07:51:21.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.07:51:21.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:21.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:21.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:21.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:21.79#ibcon#enter wrdev, iclass 39, count 2 2006.190.07:51:21.79#ibcon#first serial, iclass 39, count 2 2006.190.07:51:21.79#ibcon#enter sib2, iclass 39, count 2 2006.190.07:51:21.79#ibcon#flushed, iclass 39, count 2 2006.190.07:51:21.79#ibcon#about to write, iclass 39, count 2 2006.190.07:51:21.79#ibcon#wrote, iclass 39, count 2 2006.190.07:51:21.79#ibcon#about to read 3, iclass 39, count 2 2006.190.07:51:21.81#ibcon#read 3, iclass 39, count 2 2006.190.07:51:21.81#ibcon#about to read 4, iclass 39, count 2 2006.190.07:51:21.81#ibcon#read 4, iclass 39, count 2 2006.190.07:51:21.81#ibcon#about to read 5, iclass 39, count 2 2006.190.07:51:21.81#ibcon#read 5, iclass 39, count 2 2006.190.07:51:21.81#ibcon#about to read 6, iclass 39, count 2 2006.190.07:51:21.81#ibcon#read 6, iclass 39, count 2 2006.190.07:51:21.81#ibcon#end of sib2, iclass 39, count 2 2006.190.07:51:21.81#ibcon#*mode == 0, iclass 39, count 2 2006.190.07:51:21.81#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.07:51:21.81#ibcon#[27=AT04-04\r\n] 2006.190.07:51:21.81#ibcon#*before write, iclass 39, count 2 2006.190.07:51:21.81#ibcon#enter sib2, iclass 39, count 2 2006.190.07:51:21.81#ibcon#flushed, iclass 39, count 2 2006.190.07:51:21.81#ibcon#about to write, iclass 39, count 2 2006.190.07:51:21.81#ibcon#wrote, iclass 39, count 2 2006.190.07:51:21.81#ibcon#about to read 3, iclass 39, count 2 2006.190.07:51:21.84#ibcon#read 3, iclass 39, count 2 2006.190.07:51:21.84#ibcon#about to read 4, iclass 39, count 2 2006.190.07:51:21.84#ibcon#read 4, iclass 39, count 2 2006.190.07:51:21.84#ibcon#about to read 5, iclass 39, count 2 2006.190.07:51:21.84#ibcon#read 5, iclass 39, count 2 2006.190.07:51:21.84#ibcon#about to read 6, iclass 39, count 2 2006.190.07:51:21.84#ibcon#read 6, iclass 39, count 2 2006.190.07:51:21.84#ibcon#end of sib2, iclass 39, count 2 2006.190.07:51:21.84#ibcon#*after write, iclass 39, count 2 2006.190.07:51:21.84#ibcon#*before return 0, iclass 39, count 2 2006.190.07:51:21.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:21.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.07:51:21.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.07:51:21.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:21.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:21.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:21.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:21.96#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:51:21.96#ibcon#first serial, iclass 39, count 0 2006.190.07:51:21.96#ibcon#enter sib2, iclass 39, count 0 2006.190.07:51:21.96#ibcon#flushed, iclass 39, count 0 2006.190.07:51:21.96#ibcon#about to write, iclass 39, count 0 2006.190.07:51:21.96#ibcon#wrote, iclass 39, count 0 2006.190.07:51:21.96#ibcon#about to read 3, iclass 39, count 0 2006.190.07:51:21.98#ibcon#read 3, iclass 39, count 0 2006.190.07:51:21.98#ibcon#about to read 4, iclass 39, count 0 2006.190.07:51:21.98#ibcon#read 4, iclass 39, count 0 2006.190.07:51:21.98#ibcon#about to read 5, iclass 39, count 0 2006.190.07:51:21.98#ibcon#read 5, iclass 39, count 0 2006.190.07:51:21.98#ibcon#about to read 6, iclass 39, count 0 2006.190.07:51:21.98#ibcon#read 6, iclass 39, count 0 2006.190.07:51:21.98#ibcon#end of sib2, iclass 39, count 0 2006.190.07:51:21.98#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:51:21.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:51:21.98#ibcon#[27=USB\r\n] 2006.190.07:51:21.98#ibcon#*before write, iclass 39, count 0 2006.190.07:51:21.98#ibcon#enter sib2, iclass 39, count 0 2006.190.07:51:21.98#ibcon#flushed, iclass 39, count 0 2006.190.07:51:21.98#ibcon#about to write, iclass 39, count 0 2006.190.07:51:21.98#ibcon#wrote, iclass 39, count 0 2006.190.07:51:21.98#ibcon#about to read 3, iclass 39, count 0 2006.190.07:51:22.01#ibcon#read 3, iclass 39, count 0 2006.190.07:51:22.01#ibcon#about to read 4, iclass 39, count 0 2006.190.07:51:22.01#ibcon#read 4, iclass 39, count 0 2006.190.07:51:22.01#ibcon#about to read 5, iclass 39, count 0 2006.190.07:51:22.01#ibcon#read 5, iclass 39, count 0 2006.190.07:51:22.01#ibcon#about to read 6, iclass 39, count 0 2006.190.07:51:22.01#ibcon#read 6, iclass 39, count 0 2006.190.07:51:22.01#ibcon#end of sib2, iclass 39, count 0 2006.190.07:51:22.01#ibcon#*after write, iclass 39, count 0 2006.190.07:51:22.01#ibcon#*before return 0, iclass 39, count 0 2006.190.07:51:22.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:22.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.07:51:22.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:51:22.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:51:22.01$vc4f8/vblo=5,744.99 2006.190.07:51:22.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.07:51:22.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.07:51:22.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:22.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:22.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:22.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:22.01#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:51:22.01#ibcon#first serial, iclass 3, count 0 2006.190.07:51:22.01#ibcon#enter sib2, iclass 3, count 0 2006.190.07:51:22.01#ibcon#flushed, iclass 3, count 0 2006.190.07:51:22.01#ibcon#about to write, iclass 3, count 0 2006.190.07:51:22.01#ibcon#wrote, iclass 3, count 0 2006.190.07:51:22.01#ibcon#about to read 3, iclass 3, count 0 2006.190.07:51:22.03#ibcon#read 3, iclass 3, count 0 2006.190.07:51:22.03#ibcon#about to read 4, iclass 3, count 0 2006.190.07:51:22.03#ibcon#read 4, iclass 3, count 0 2006.190.07:51:22.03#ibcon#about to read 5, iclass 3, count 0 2006.190.07:51:22.03#ibcon#read 5, iclass 3, count 0 2006.190.07:51:22.03#ibcon#about to read 6, iclass 3, count 0 2006.190.07:51:22.03#ibcon#read 6, iclass 3, count 0 2006.190.07:51:22.03#ibcon#end of sib2, iclass 3, count 0 2006.190.07:51:22.03#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:51:22.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:51:22.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:51:22.03#ibcon#*before write, iclass 3, count 0 2006.190.07:51:22.03#ibcon#enter sib2, iclass 3, count 0 2006.190.07:51:22.03#ibcon#flushed, iclass 3, count 0 2006.190.07:51:22.03#ibcon#about to write, iclass 3, count 0 2006.190.07:51:22.03#ibcon#wrote, iclass 3, count 0 2006.190.07:51:22.03#ibcon#about to read 3, iclass 3, count 0 2006.190.07:51:22.07#ibcon#read 3, iclass 3, count 0 2006.190.07:51:22.07#ibcon#about to read 4, iclass 3, count 0 2006.190.07:51:22.07#ibcon#read 4, iclass 3, count 0 2006.190.07:51:22.07#ibcon#about to read 5, iclass 3, count 0 2006.190.07:51:22.07#ibcon#read 5, iclass 3, count 0 2006.190.07:51:22.07#ibcon#about to read 6, iclass 3, count 0 2006.190.07:51:22.07#ibcon#read 6, iclass 3, count 0 2006.190.07:51:22.07#ibcon#end of sib2, iclass 3, count 0 2006.190.07:51:22.07#ibcon#*after write, iclass 3, count 0 2006.190.07:51:22.07#ibcon#*before return 0, iclass 3, count 0 2006.190.07:51:22.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:22.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.07:51:22.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:51:22.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:51:22.07$vc4f8/vb=5,4 2006.190.07:51:22.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.07:51:22.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.07:51:22.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:22.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:22.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:22.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:22.13#ibcon#enter wrdev, iclass 5, count 2 2006.190.07:51:22.13#ibcon#first serial, iclass 5, count 2 2006.190.07:51:22.13#ibcon#enter sib2, iclass 5, count 2 2006.190.07:51:22.13#ibcon#flushed, iclass 5, count 2 2006.190.07:51:22.13#ibcon#about to write, iclass 5, count 2 2006.190.07:51:22.13#ibcon#wrote, iclass 5, count 2 2006.190.07:51:22.13#ibcon#about to read 3, iclass 5, count 2 2006.190.07:51:22.15#ibcon#read 3, iclass 5, count 2 2006.190.07:51:22.15#ibcon#about to read 4, iclass 5, count 2 2006.190.07:51:22.15#ibcon#read 4, iclass 5, count 2 2006.190.07:51:22.15#ibcon#about to read 5, iclass 5, count 2 2006.190.07:51:22.15#ibcon#read 5, iclass 5, count 2 2006.190.07:51:22.15#ibcon#about to read 6, iclass 5, count 2 2006.190.07:51:22.15#ibcon#read 6, iclass 5, count 2 2006.190.07:51:22.15#ibcon#end of sib2, iclass 5, count 2 2006.190.07:51:22.15#ibcon#*mode == 0, iclass 5, count 2 2006.190.07:51:22.15#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.07:51:22.15#ibcon#[27=AT05-04\r\n] 2006.190.07:51:22.15#ibcon#*before write, iclass 5, count 2 2006.190.07:51:22.15#ibcon#enter sib2, iclass 5, count 2 2006.190.07:51:22.15#ibcon#flushed, iclass 5, count 2 2006.190.07:51:22.15#ibcon#about to write, iclass 5, count 2 2006.190.07:51:22.15#ibcon#wrote, iclass 5, count 2 2006.190.07:51:22.15#ibcon#about to read 3, iclass 5, count 2 2006.190.07:51:22.18#ibcon#read 3, iclass 5, count 2 2006.190.07:51:22.18#ibcon#about to read 4, iclass 5, count 2 2006.190.07:51:22.18#ibcon#read 4, iclass 5, count 2 2006.190.07:51:22.18#ibcon#about to read 5, iclass 5, count 2 2006.190.07:51:22.18#ibcon#read 5, iclass 5, count 2 2006.190.07:51:22.18#ibcon#about to read 6, iclass 5, count 2 2006.190.07:51:22.18#ibcon#read 6, iclass 5, count 2 2006.190.07:51:22.18#ibcon#end of sib2, iclass 5, count 2 2006.190.07:51:22.18#ibcon#*after write, iclass 5, count 2 2006.190.07:51:22.18#ibcon#*before return 0, iclass 5, count 2 2006.190.07:51:22.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:22.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.07:51:22.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.07:51:22.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:22.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:22.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:22.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:22.30#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:51:22.30#ibcon#first serial, iclass 5, count 0 2006.190.07:51:22.30#ibcon#enter sib2, iclass 5, count 0 2006.190.07:51:22.30#ibcon#flushed, iclass 5, count 0 2006.190.07:51:22.30#ibcon#about to write, iclass 5, count 0 2006.190.07:51:22.30#ibcon#wrote, iclass 5, count 0 2006.190.07:51:22.30#ibcon#about to read 3, iclass 5, count 0 2006.190.07:51:22.32#ibcon#read 3, iclass 5, count 0 2006.190.07:51:22.32#ibcon#about to read 4, iclass 5, count 0 2006.190.07:51:22.32#ibcon#read 4, iclass 5, count 0 2006.190.07:51:22.32#ibcon#about to read 5, iclass 5, count 0 2006.190.07:51:22.32#ibcon#read 5, iclass 5, count 0 2006.190.07:51:22.32#ibcon#about to read 6, iclass 5, count 0 2006.190.07:51:22.32#ibcon#read 6, iclass 5, count 0 2006.190.07:51:22.32#ibcon#end of sib2, iclass 5, count 0 2006.190.07:51:22.32#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:51:22.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:51:22.32#ibcon#[27=USB\r\n] 2006.190.07:51:22.32#ibcon#*before write, iclass 5, count 0 2006.190.07:51:22.32#ibcon#enter sib2, iclass 5, count 0 2006.190.07:51:22.32#ibcon#flushed, iclass 5, count 0 2006.190.07:51:22.32#ibcon#about to write, iclass 5, count 0 2006.190.07:51:22.32#ibcon#wrote, iclass 5, count 0 2006.190.07:51:22.32#ibcon#about to read 3, iclass 5, count 0 2006.190.07:51:22.35#ibcon#read 3, iclass 5, count 0 2006.190.07:51:22.35#ibcon#about to read 4, iclass 5, count 0 2006.190.07:51:22.35#ibcon#read 4, iclass 5, count 0 2006.190.07:51:22.35#ibcon#about to read 5, iclass 5, count 0 2006.190.07:51:22.35#ibcon#read 5, iclass 5, count 0 2006.190.07:51:22.35#ibcon#about to read 6, iclass 5, count 0 2006.190.07:51:22.35#ibcon#read 6, iclass 5, count 0 2006.190.07:51:22.35#ibcon#end of sib2, iclass 5, count 0 2006.190.07:51:22.35#ibcon#*after write, iclass 5, count 0 2006.190.07:51:22.35#ibcon#*before return 0, iclass 5, count 0 2006.190.07:51:22.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:22.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.07:51:22.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:51:22.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:51:22.35$vc4f8/vblo=6,752.99 2006.190.07:51:22.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.07:51:22.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.07:51:22.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:51:22.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:51:22.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:51:22.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:51:22.35#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:51:22.35#ibcon#first serial, iclass 7, count 0 2006.190.07:51:22.35#ibcon#enter sib2, iclass 7, count 0 2006.190.07:51:22.35#ibcon#flushed, iclass 7, count 0 2006.190.07:51:22.35#ibcon#about to write, iclass 7, count 0 2006.190.07:51:22.35#ibcon#wrote, iclass 7, count 0 2006.190.07:51:22.35#ibcon#about to read 3, iclass 7, count 0 2006.190.07:51:22.37#ibcon#read 3, iclass 7, count 0 2006.190.07:51:22.37#ibcon#about to read 4, iclass 7, count 0 2006.190.07:51:22.37#ibcon#read 4, iclass 7, count 0 2006.190.07:51:22.37#ibcon#about to read 5, iclass 7, count 0 2006.190.07:51:22.37#ibcon#read 5, iclass 7, count 0 2006.190.07:51:22.37#ibcon#about to read 6, iclass 7, count 0 2006.190.07:51:22.37#ibcon#read 6, iclass 7, count 0 2006.190.07:51:22.37#ibcon#end of sib2, iclass 7, count 0 2006.190.07:51:22.37#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:51:22.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:51:22.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:51:22.37#ibcon#*before write, iclass 7, count 0 2006.190.07:51:22.37#ibcon#enter sib2, iclass 7, count 0 2006.190.07:51:22.37#ibcon#flushed, iclass 7, count 0 2006.190.07:51:22.37#ibcon#about to write, iclass 7, count 0 2006.190.07:51:22.37#ibcon#wrote, iclass 7, count 0 2006.190.07:51:22.37#ibcon#about to read 3, iclass 7, count 0 2006.190.07:51:22.41#ibcon#read 3, iclass 7, count 0 2006.190.07:51:22.41#ibcon#about to read 4, iclass 7, count 0 2006.190.07:51:22.41#ibcon#read 4, iclass 7, count 0 2006.190.07:51:22.41#ibcon#about to read 5, iclass 7, count 0 2006.190.07:51:22.41#ibcon#read 5, iclass 7, count 0 2006.190.07:51:22.41#ibcon#about to read 6, iclass 7, count 0 2006.190.07:51:22.41#ibcon#read 6, iclass 7, count 0 2006.190.07:51:22.41#ibcon#end of sib2, iclass 7, count 0 2006.190.07:51:22.41#ibcon#*after write, iclass 7, count 0 2006.190.07:51:22.41#ibcon#*before return 0, iclass 7, count 0 2006.190.07:51:22.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:51:22.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.07:51:22.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:51:22.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:51:22.41$vc4f8/vb=6,4 2006.190.07:51:22.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.07:51:22.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.07:51:22.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:51:22.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:51:22.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:51:22.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:51:22.47#ibcon#enter wrdev, iclass 11, count 2 2006.190.07:51:22.47#ibcon#first serial, iclass 11, count 2 2006.190.07:51:22.47#ibcon#enter sib2, iclass 11, count 2 2006.190.07:51:22.47#ibcon#flushed, iclass 11, count 2 2006.190.07:51:22.47#ibcon#about to write, iclass 11, count 2 2006.190.07:51:22.47#ibcon#wrote, iclass 11, count 2 2006.190.07:51:22.47#ibcon#about to read 3, iclass 11, count 2 2006.190.07:51:22.49#ibcon#read 3, iclass 11, count 2 2006.190.07:51:22.49#ibcon#about to read 4, iclass 11, count 2 2006.190.07:51:22.49#ibcon#read 4, iclass 11, count 2 2006.190.07:51:22.49#ibcon#about to read 5, iclass 11, count 2 2006.190.07:51:22.49#ibcon#read 5, iclass 11, count 2 2006.190.07:51:22.49#ibcon#about to read 6, iclass 11, count 2 2006.190.07:51:22.49#ibcon#read 6, iclass 11, count 2 2006.190.07:51:22.49#ibcon#end of sib2, iclass 11, count 2 2006.190.07:51:22.49#ibcon#*mode == 0, iclass 11, count 2 2006.190.07:51:22.49#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.07:51:22.49#ibcon#[27=AT06-04\r\n] 2006.190.07:51:22.49#ibcon#*before write, iclass 11, count 2 2006.190.07:51:22.49#ibcon#enter sib2, iclass 11, count 2 2006.190.07:51:22.49#ibcon#flushed, iclass 11, count 2 2006.190.07:51:22.49#ibcon#about to write, iclass 11, count 2 2006.190.07:51:22.49#ibcon#wrote, iclass 11, count 2 2006.190.07:51:22.49#ibcon#about to read 3, iclass 11, count 2 2006.190.07:51:22.52#ibcon#read 3, iclass 11, count 2 2006.190.07:51:22.52#ibcon#about to read 4, iclass 11, count 2 2006.190.07:51:22.52#ibcon#read 4, iclass 11, count 2 2006.190.07:51:22.52#ibcon#about to read 5, iclass 11, count 2 2006.190.07:51:22.52#ibcon#read 5, iclass 11, count 2 2006.190.07:51:22.52#ibcon#about to read 6, iclass 11, count 2 2006.190.07:51:22.52#ibcon#read 6, iclass 11, count 2 2006.190.07:51:22.52#ibcon#end of sib2, iclass 11, count 2 2006.190.07:51:22.52#ibcon#*after write, iclass 11, count 2 2006.190.07:51:22.52#ibcon#*before return 0, iclass 11, count 2 2006.190.07:51:22.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:51:22.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.07:51:22.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.07:51:22.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:51:22.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:51:22.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:51:22.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:51:22.64#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:51:22.64#ibcon#first serial, iclass 11, count 0 2006.190.07:51:22.64#ibcon#enter sib2, iclass 11, count 0 2006.190.07:51:22.64#ibcon#flushed, iclass 11, count 0 2006.190.07:51:22.64#ibcon#about to write, iclass 11, count 0 2006.190.07:51:22.64#ibcon#wrote, iclass 11, count 0 2006.190.07:51:22.64#ibcon#about to read 3, iclass 11, count 0 2006.190.07:51:22.66#ibcon#read 3, iclass 11, count 0 2006.190.07:51:22.66#ibcon#about to read 4, iclass 11, count 0 2006.190.07:51:22.66#ibcon#read 4, iclass 11, count 0 2006.190.07:51:22.66#ibcon#about to read 5, iclass 11, count 0 2006.190.07:51:22.66#ibcon#read 5, iclass 11, count 0 2006.190.07:51:22.66#ibcon#about to read 6, iclass 11, count 0 2006.190.07:51:22.66#ibcon#read 6, iclass 11, count 0 2006.190.07:51:22.66#ibcon#end of sib2, iclass 11, count 0 2006.190.07:51:22.66#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:51:22.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:51:22.66#ibcon#[27=USB\r\n] 2006.190.07:51:22.66#ibcon#*before write, iclass 11, count 0 2006.190.07:51:22.66#ibcon#enter sib2, iclass 11, count 0 2006.190.07:51:22.66#ibcon#flushed, iclass 11, count 0 2006.190.07:51:22.66#ibcon#about to write, iclass 11, count 0 2006.190.07:51:22.66#ibcon#wrote, iclass 11, count 0 2006.190.07:51:22.66#ibcon#about to read 3, iclass 11, count 0 2006.190.07:51:22.69#ibcon#read 3, iclass 11, count 0 2006.190.07:51:22.69#ibcon#about to read 4, iclass 11, count 0 2006.190.07:51:22.69#ibcon#read 4, iclass 11, count 0 2006.190.07:51:22.69#ibcon#about to read 5, iclass 11, count 0 2006.190.07:51:22.69#ibcon#read 5, iclass 11, count 0 2006.190.07:51:22.69#ibcon#about to read 6, iclass 11, count 0 2006.190.07:51:22.69#ibcon#read 6, iclass 11, count 0 2006.190.07:51:22.69#ibcon#end of sib2, iclass 11, count 0 2006.190.07:51:22.69#ibcon#*after write, iclass 11, count 0 2006.190.07:51:22.69#ibcon#*before return 0, iclass 11, count 0 2006.190.07:51:22.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:51:22.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.07:51:22.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:51:22.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:51:22.69$vc4f8/vabw=wide 2006.190.07:51:22.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.07:51:22.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.07:51:22.69#ibcon#ireg 8 cls_cnt 0 2006.190.07:51:22.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:51:22.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:51:22.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:51:22.69#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:51:22.69#ibcon#first serial, iclass 13, count 0 2006.190.07:51:22.69#ibcon#enter sib2, iclass 13, count 0 2006.190.07:51:22.69#ibcon#flushed, iclass 13, count 0 2006.190.07:51:22.69#ibcon#about to write, iclass 13, count 0 2006.190.07:51:22.69#ibcon#wrote, iclass 13, count 0 2006.190.07:51:22.69#ibcon#about to read 3, iclass 13, count 0 2006.190.07:51:22.71#ibcon#read 3, iclass 13, count 0 2006.190.07:51:22.71#ibcon#about to read 4, iclass 13, count 0 2006.190.07:51:22.71#ibcon#read 4, iclass 13, count 0 2006.190.07:51:22.71#ibcon#about to read 5, iclass 13, count 0 2006.190.07:51:22.71#ibcon#read 5, iclass 13, count 0 2006.190.07:51:22.71#ibcon#about to read 6, iclass 13, count 0 2006.190.07:51:22.71#ibcon#read 6, iclass 13, count 0 2006.190.07:51:22.71#ibcon#end of sib2, iclass 13, count 0 2006.190.07:51:22.71#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:51:22.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:51:22.71#ibcon#[25=BW32\r\n] 2006.190.07:51:22.71#ibcon#*before write, iclass 13, count 0 2006.190.07:51:22.71#ibcon#enter sib2, iclass 13, count 0 2006.190.07:51:22.71#ibcon#flushed, iclass 13, count 0 2006.190.07:51:22.71#ibcon#about to write, iclass 13, count 0 2006.190.07:51:22.71#ibcon#wrote, iclass 13, count 0 2006.190.07:51:22.71#ibcon#about to read 3, iclass 13, count 0 2006.190.07:51:22.74#ibcon#read 3, iclass 13, count 0 2006.190.07:51:22.74#ibcon#about to read 4, iclass 13, count 0 2006.190.07:51:22.74#ibcon#read 4, iclass 13, count 0 2006.190.07:51:22.74#ibcon#about to read 5, iclass 13, count 0 2006.190.07:51:22.74#ibcon#read 5, iclass 13, count 0 2006.190.07:51:22.74#ibcon#about to read 6, iclass 13, count 0 2006.190.07:51:22.74#ibcon#read 6, iclass 13, count 0 2006.190.07:51:22.74#ibcon#end of sib2, iclass 13, count 0 2006.190.07:51:22.74#ibcon#*after write, iclass 13, count 0 2006.190.07:51:22.74#ibcon#*before return 0, iclass 13, count 0 2006.190.07:51:22.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:51:22.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.07:51:22.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:51:22.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:51:22.74$vc4f8/vbbw=wide 2006.190.07:51:22.74#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:51:22.74#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:51:22.74#ibcon#ireg 8 cls_cnt 0 2006.190.07:51:22.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:51:22.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:51:22.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:51:22.81#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:51:22.81#ibcon#first serial, iclass 15, count 0 2006.190.07:51:22.81#ibcon#enter sib2, iclass 15, count 0 2006.190.07:51:22.81#ibcon#flushed, iclass 15, count 0 2006.190.07:51:22.81#ibcon#about to write, iclass 15, count 0 2006.190.07:51:22.81#ibcon#wrote, iclass 15, count 0 2006.190.07:51:22.81#ibcon#about to read 3, iclass 15, count 0 2006.190.07:51:22.83#ibcon#read 3, iclass 15, count 0 2006.190.07:51:22.83#ibcon#about to read 4, iclass 15, count 0 2006.190.07:51:22.83#ibcon#read 4, iclass 15, count 0 2006.190.07:51:22.83#ibcon#about to read 5, iclass 15, count 0 2006.190.07:51:22.83#ibcon#read 5, iclass 15, count 0 2006.190.07:51:22.83#ibcon#about to read 6, iclass 15, count 0 2006.190.07:51:22.83#ibcon#read 6, iclass 15, count 0 2006.190.07:51:22.83#ibcon#end of sib2, iclass 15, count 0 2006.190.07:51:22.83#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:51:22.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:51:22.83#ibcon#[27=BW32\r\n] 2006.190.07:51:22.83#ibcon#*before write, iclass 15, count 0 2006.190.07:51:22.83#ibcon#enter sib2, iclass 15, count 0 2006.190.07:51:22.83#ibcon#flushed, iclass 15, count 0 2006.190.07:51:22.83#ibcon#about to write, iclass 15, count 0 2006.190.07:51:22.83#ibcon#wrote, iclass 15, count 0 2006.190.07:51:22.83#ibcon#about to read 3, iclass 15, count 0 2006.190.07:51:22.86#ibcon#read 3, iclass 15, count 0 2006.190.07:51:22.86#ibcon#about to read 4, iclass 15, count 0 2006.190.07:51:22.86#ibcon#read 4, iclass 15, count 0 2006.190.07:51:22.86#ibcon#about to read 5, iclass 15, count 0 2006.190.07:51:22.86#ibcon#read 5, iclass 15, count 0 2006.190.07:51:22.86#ibcon#about to read 6, iclass 15, count 0 2006.190.07:51:22.86#ibcon#read 6, iclass 15, count 0 2006.190.07:51:22.86#ibcon#end of sib2, iclass 15, count 0 2006.190.07:51:22.86#ibcon#*after write, iclass 15, count 0 2006.190.07:51:22.86#ibcon#*before return 0, iclass 15, count 0 2006.190.07:51:22.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:51:22.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:51:22.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:51:22.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:51:22.86$4f8m12a/ifd4f 2006.190.07:51:22.86$ifd4f/lo= 2006.190.07:51:22.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:51:22.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:51:22.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:51:22.86$ifd4f/patch= 2006.190.07:51:22.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:51:22.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:51:22.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:51:22.86$4f8m12a/"form=m,16.000,1:2 2006.190.07:51:22.86$4f8m12a/"tpicd 2006.190.07:51:22.86$4f8m12a/echo=off 2006.190.07:51:22.86$4f8m12a/xlog=off 2006.190.07:51:22.86:!2006.190.07:51:50 2006.190.07:51:37.14#trakl#Source acquired 2006.190.07:51:38.14#flagr#flagr/antenna,acquired 2006.190.07:51:50.00:preob 2006.190.07:51:51.14/onsource/TRACKING 2006.190.07:51:51.14:!2006.190.07:52:00 2006.190.07:52:00.00:data_valid=on 2006.190.07:52:00.00:midob 2006.190.07:52:00.14/onsource/TRACKING 2006.190.07:52:00.14/wx/24.51,1012.0,100 2006.190.07:52:00.21/cable/+6.4689E-03 2006.190.07:52:01.30/va/01,08,usb,yes,39,41 2006.190.07:52:01.30/va/02,07,usb,yes,40,41 2006.190.07:52:01.30/va/03,06,usb,yes,42,42 2006.190.07:52:01.30/va/04,07,usb,yes,41,44 2006.190.07:52:01.30/va/05,07,usb,yes,45,48 2006.190.07:52:01.30/va/06,06,usb,yes,44,44 2006.190.07:52:01.30/va/07,06,usb,yes,45,45 2006.190.07:52:01.30/va/08,06,usb,yes,48,47 2006.190.07:52:01.53/valo/01,532.99,yes,locked 2006.190.07:52:01.53/valo/02,572.99,yes,locked 2006.190.07:52:01.53/valo/03,672.99,yes,locked 2006.190.07:52:01.53/valo/04,832.99,yes,locked 2006.190.07:52:01.53/valo/05,652.99,yes,locked 2006.190.07:52:01.53/valo/06,772.99,yes,locked 2006.190.07:52:01.53/valo/07,832.99,yes,locked 2006.190.07:52:01.53/valo/08,852.99,yes,locked 2006.190.07:52:02.62/vb/01,04,usb,yes,32,31 2006.190.07:52:02.62/vb/02,04,usb,yes,34,36 2006.190.07:52:02.62/vb/03,04,usb,yes,30,34 2006.190.07:52:02.62/vb/04,04,usb,yes,33,32 2006.190.07:52:02.62/vb/05,04,usb,yes,30,36 2006.190.07:52:02.62/vb/06,04,usb,yes,31,34 2006.190.07:52:02.62/vb/07,04,usb,yes,33,36 2006.190.07:52:02.62/vb/08,04,usb,yes,31,36 2006.190.07:52:02.85/vblo/01,632.99,yes,locked 2006.190.07:52:02.85/vblo/02,640.99,yes,locked 2006.190.07:52:02.85/vblo/03,656.99,yes,locked 2006.190.07:52:02.85/vblo/04,712.99,yes,locked 2006.190.07:52:02.85/vblo/05,744.99,yes,locked 2006.190.07:52:02.85/vblo/06,752.99,yes,locked 2006.190.07:52:02.85/vblo/07,734.99,yes,locked 2006.190.07:52:02.85/vblo/08,744.99,yes,locked 2006.190.07:52:03.00/vabw/8 2006.190.07:52:03.15/vbbw/8 2006.190.07:52:03.24/xfe/off,on,15.2 2006.190.07:52:03.64/ifatt/23,28,28,28 2006.190.07:52:04.08/fmout-gps/S +2.88E-07 2006.190.07:52:04.16:!2006.190.07:53:00 2006.190.07:53:00.00:data_valid=off 2006.190.07:53:00.00:postob 2006.190.07:53:00.13/cable/+6.4713E-03 2006.190.07:53:00.13/wx/24.51,1012.0,100 2006.190.07:53:01.08/fmout-gps/S +2.87E-07 2006.190.07:53:01.08:scan_name=190-0755,k06190,60 2006.190.07:53:01.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.190.07:53:01.14#flagr#flagr/antenna,new-source 2006.190.07:53:02.14:checkk5 2006.190.07:53:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:53:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:53:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:53:03.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:53:04.05/chk_obsdata//k5ts1/T1900752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:53:04.43/chk_obsdata//k5ts2/T1900752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:53:04.80/chk_obsdata//k5ts3/T1900752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:53:05.18/chk_obsdata//k5ts4/T1900752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:53:05.88/k5log//k5ts1_log_newline 2006.190.07:53:06.58/k5log//k5ts2_log_newline 2006.190.07:53:07.27/k5log//k5ts3_log_newline 2006.190.07:53:07.98/k5log//k5ts4_log_newline 2006.190.07:53:08.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:53:08.00:4f8m12a=2 2006.190.07:53:08.00$4f8m12a/echo=on 2006.190.07:53:08.00$4f8m12a/pcalon 2006.190.07:53:08.00$pcalon/"no phase cal control is implemented here 2006.190.07:53:08.00$4f8m12a/"tpicd=stop 2006.190.07:53:08.00$4f8m12a/vc4f8 2006.190.07:53:08.00$vc4f8/valo=1,532.99 2006.190.07:53:08.01#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.07:53:08.01#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.07:53:08.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:08.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:08.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:08.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:08.01#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:53:08.01#ibcon#first serial, iclass 22, count 0 2006.190.07:53:08.01#ibcon#enter sib2, iclass 22, count 0 2006.190.07:53:08.01#ibcon#flushed, iclass 22, count 0 2006.190.07:53:08.01#ibcon#about to write, iclass 22, count 0 2006.190.07:53:08.01#ibcon#wrote, iclass 22, count 0 2006.190.07:53:08.01#ibcon#about to read 3, iclass 22, count 0 2006.190.07:53:08.06#ibcon#read 3, iclass 22, count 0 2006.190.07:53:08.06#ibcon#about to read 4, iclass 22, count 0 2006.190.07:53:08.06#ibcon#read 4, iclass 22, count 0 2006.190.07:53:08.06#ibcon#about to read 5, iclass 22, count 0 2006.190.07:53:08.06#ibcon#read 5, iclass 22, count 0 2006.190.07:53:08.06#ibcon#about to read 6, iclass 22, count 0 2006.190.07:53:08.06#ibcon#read 6, iclass 22, count 0 2006.190.07:53:08.06#ibcon#end of sib2, iclass 22, count 0 2006.190.07:53:08.06#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:53:08.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:53:08.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:53:08.06#ibcon#*before write, iclass 22, count 0 2006.190.07:53:08.06#ibcon#enter sib2, iclass 22, count 0 2006.190.07:53:08.06#ibcon#flushed, iclass 22, count 0 2006.190.07:53:08.06#ibcon#about to write, iclass 22, count 0 2006.190.07:53:08.06#ibcon#wrote, iclass 22, count 0 2006.190.07:53:08.06#ibcon#about to read 3, iclass 22, count 0 2006.190.07:53:08.11#ibcon#read 3, iclass 22, count 0 2006.190.07:53:08.11#ibcon#about to read 4, iclass 22, count 0 2006.190.07:53:08.11#ibcon#read 4, iclass 22, count 0 2006.190.07:53:08.11#ibcon#about to read 5, iclass 22, count 0 2006.190.07:53:08.11#ibcon#read 5, iclass 22, count 0 2006.190.07:53:08.11#ibcon#about to read 6, iclass 22, count 0 2006.190.07:53:08.11#ibcon#read 6, iclass 22, count 0 2006.190.07:53:08.11#ibcon#end of sib2, iclass 22, count 0 2006.190.07:53:08.11#ibcon#*after write, iclass 22, count 0 2006.190.07:53:08.11#ibcon#*before return 0, iclass 22, count 0 2006.190.07:53:08.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:08.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:08.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:53:08.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:53:08.11$vc4f8/va=1,8 2006.190.07:53:08.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.07:53:08.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.07:53:08.11#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:08.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:08.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:08.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:08.11#ibcon#enter wrdev, iclass 24, count 2 2006.190.07:53:08.11#ibcon#first serial, iclass 24, count 2 2006.190.07:53:08.11#ibcon#enter sib2, iclass 24, count 2 2006.190.07:53:08.11#ibcon#flushed, iclass 24, count 2 2006.190.07:53:08.11#ibcon#about to write, iclass 24, count 2 2006.190.07:53:08.11#ibcon#wrote, iclass 24, count 2 2006.190.07:53:08.11#ibcon#about to read 3, iclass 24, count 2 2006.190.07:53:08.13#ibcon#read 3, iclass 24, count 2 2006.190.07:53:08.13#ibcon#about to read 4, iclass 24, count 2 2006.190.07:53:08.13#ibcon#read 4, iclass 24, count 2 2006.190.07:53:08.13#ibcon#about to read 5, iclass 24, count 2 2006.190.07:53:08.13#ibcon#read 5, iclass 24, count 2 2006.190.07:53:08.13#ibcon#about to read 6, iclass 24, count 2 2006.190.07:53:08.13#ibcon#read 6, iclass 24, count 2 2006.190.07:53:08.13#ibcon#end of sib2, iclass 24, count 2 2006.190.07:53:08.13#ibcon#*mode == 0, iclass 24, count 2 2006.190.07:53:08.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.07:53:08.13#ibcon#[25=AT01-08\r\n] 2006.190.07:53:08.13#ibcon#*before write, iclass 24, count 2 2006.190.07:53:08.13#ibcon#enter sib2, iclass 24, count 2 2006.190.07:53:08.13#ibcon#flushed, iclass 24, count 2 2006.190.07:53:08.13#ibcon#about to write, iclass 24, count 2 2006.190.07:53:08.13#ibcon#wrote, iclass 24, count 2 2006.190.07:53:08.13#ibcon#about to read 3, iclass 24, count 2 2006.190.07:53:08.16#ibcon#read 3, iclass 24, count 2 2006.190.07:53:08.16#ibcon#about to read 4, iclass 24, count 2 2006.190.07:53:08.16#ibcon#read 4, iclass 24, count 2 2006.190.07:53:08.16#ibcon#about to read 5, iclass 24, count 2 2006.190.07:53:08.16#ibcon#read 5, iclass 24, count 2 2006.190.07:53:08.16#ibcon#about to read 6, iclass 24, count 2 2006.190.07:53:08.16#ibcon#read 6, iclass 24, count 2 2006.190.07:53:08.16#ibcon#end of sib2, iclass 24, count 2 2006.190.07:53:08.16#ibcon#*after write, iclass 24, count 2 2006.190.07:53:08.16#ibcon#*before return 0, iclass 24, count 2 2006.190.07:53:08.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:08.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:08.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.07:53:08.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:08.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:08.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:08.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:08.28#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:53:08.28#ibcon#first serial, iclass 24, count 0 2006.190.07:53:08.28#ibcon#enter sib2, iclass 24, count 0 2006.190.07:53:08.28#ibcon#flushed, iclass 24, count 0 2006.190.07:53:08.28#ibcon#about to write, iclass 24, count 0 2006.190.07:53:08.28#ibcon#wrote, iclass 24, count 0 2006.190.07:53:08.28#ibcon#about to read 3, iclass 24, count 0 2006.190.07:53:08.30#ibcon#read 3, iclass 24, count 0 2006.190.07:53:08.30#ibcon#about to read 4, iclass 24, count 0 2006.190.07:53:08.30#ibcon#read 4, iclass 24, count 0 2006.190.07:53:08.30#ibcon#about to read 5, iclass 24, count 0 2006.190.07:53:08.30#ibcon#read 5, iclass 24, count 0 2006.190.07:53:08.30#ibcon#about to read 6, iclass 24, count 0 2006.190.07:53:08.30#ibcon#read 6, iclass 24, count 0 2006.190.07:53:08.30#ibcon#end of sib2, iclass 24, count 0 2006.190.07:53:08.30#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:53:08.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:53:08.30#ibcon#[25=USB\r\n] 2006.190.07:53:08.30#ibcon#*before write, iclass 24, count 0 2006.190.07:53:08.30#ibcon#enter sib2, iclass 24, count 0 2006.190.07:53:08.30#ibcon#flushed, iclass 24, count 0 2006.190.07:53:08.30#ibcon#about to write, iclass 24, count 0 2006.190.07:53:08.30#ibcon#wrote, iclass 24, count 0 2006.190.07:53:08.30#ibcon#about to read 3, iclass 24, count 0 2006.190.07:53:08.33#ibcon#read 3, iclass 24, count 0 2006.190.07:53:08.33#ibcon#about to read 4, iclass 24, count 0 2006.190.07:53:08.33#ibcon#read 4, iclass 24, count 0 2006.190.07:53:08.33#ibcon#about to read 5, iclass 24, count 0 2006.190.07:53:08.33#ibcon#read 5, iclass 24, count 0 2006.190.07:53:08.33#ibcon#about to read 6, iclass 24, count 0 2006.190.07:53:08.33#ibcon#read 6, iclass 24, count 0 2006.190.07:53:08.33#ibcon#end of sib2, iclass 24, count 0 2006.190.07:53:08.33#ibcon#*after write, iclass 24, count 0 2006.190.07:53:08.33#ibcon#*before return 0, iclass 24, count 0 2006.190.07:53:08.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:08.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:08.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:53:08.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:53:08.33$vc4f8/valo=2,572.99 2006.190.07:53:08.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.07:53:08.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.07:53:08.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:08.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:08.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:08.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:08.33#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:53:08.33#ibcon#first serial, iclass 26, count 0 2006.190.07:53:08.33#ibcon#enter sib2, iclass 26, count 0 2006.190.07:53:08.33#ibcon#flushed, iclass 26, count 0 2006.190.07:53:08.33#ibcon#about to write, iclass 26, count 0 2006.190.07:53:08.33#ibcon#wrote, iclass 26, count 0 2006.190.07:53:08.33#ibcon#about to read 3, iclass 26, count 0 2006.190.07:53:08.35#ibcon#read 3, iclass 26, count 0 2006.190.07:53:08.35#ibcon#about to read 4, iclass 26, count 0 2006.190.07:53:08.35#ibcon#read 4, iclass 26, count 0 2006.190.07:53:08.35#ibcon#about to read 5, iclass 26, count 0 2006.190.07:53:08.35#ibcon#read 5, iclass 26, count 0 2006.190.07:53:08.35#ibcon#about to read 6, iclass 26, count 0 2006.190.07:53:08.35#ibcon#read 6, iclass 26, count 0 2006.190.07:53:08.35#ibcon#end of sib2, iclass 26, count 0 2006.190.07:53:08.35#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:53:08.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:53:08.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:53:08.35#ibcon#*before write, iclass 26, count 0 2006.190.07:53:08.35#ibcon#enter sib2, iclass 26, count 0 2006.190.07:53:08.35#ibcon#flushed, iclass 26, count 0 2006.190.07:53:08.35#ibcon#about to write, iclass 26, count 0 2006.190.07:53:08.35#ibcon#wrote, iclass 26, count 0 2006.190.07:53:08.35#ibcon#about to read 3, iclass 26, count 0 2006.190.07:53:08.39#ibcon#read 3, iclass 26, count 0 2006.190.07:53:08.39#ibcon#about to read 4, iclass 26, count 0 2006.190.07:53:08.39#ibcon#read 4, iclass 26, count 0 2006.190.07:53:08.39#ibcon#about to read 5, iclass 26, count 0 2006.190.07:53:08.39#ibcon#read 5, iclass 26, count 0 2006.190.07:53:08.39#ibcon#about to read 6, iclass 26, count 0 2006.190.07:53:08.39#ibcon#read 6, iclass 26, count 0 2006.190.07:53:08.39#ibcon#end of sib2, iclass 26, count 0 2006.190.07:53:08.39#ibcon#*after write, iclass 26, count 0 2006.190.07:53:08.39#ibcon#*before return 0, iclass 26, count 0 2006.190.07:53:08.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:08.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:08.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:53:08.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:53:08.39$vc4f8/va=2,7 2006.190.07:53:08.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.07:53:08.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.07:53:08.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:08.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:08.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:08.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:08.45#ibcon#enter wrdev, iclass 28, count 2 2006.190.07:53:08.45#ibcon#first serial, iclass 28, count 2 2006.190.07:53:08.45#ibcon#enter sib2, iclass 28, count 2 2006.190.07:53:08.45#ibcon#flushed, iclass 28, count 2 2006.190.07:53:08.45#ibcon#about to write, iclass 28, count 2 2006.190.07:53:08.45#ibcon#wrote, iclass 28, count 2 2006.190.07:53:08.45#ibcon#about to read 3, iclass 28, count 2 2006.190.07:53:08.47#ibcon#read 3, iclass 28, count 2 2006.190.07:53:08.47#ibcon#about to read 4, iclass 28, count 2 2006.190.07:53:08.47#ibcon#read 4, iclass 28, count 2 2006.190.07:53:08.47#ibcon#about to read 5, iclass 28, count 2 2006.190.07:53:08.47#ibcon#read 5, iclass 28, count 2 2006.190.07:53:08.47#ibcon#about to read 6, iclass 28, count 2 2006.190.07:53:08.47#ibcon#read 6, iclass 28, count 2 2006.190.07:53:08.47#ibcon#end of sib2, iclass 28, count 2 2006.190.07:53:08.47#ibcon#*mode == 0, iclass 28, count 2 2006.190.07:53:08.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.07:53:08.47#ibcon#[25=AT02-07\r\n] 2006.190.07:53:08.47#ibcon#*before write, iclass 28, count 2 2006.190.07:53:08.47#ibcon#enter sib2, iclass 28, count 2 2006.190.07:53:08.47#ibcon#flushed, iclass 28, count 2 2006.190.07:53:08.47#ibcon#about to write, iclass 28, count 2 2006.190.07:53:08.47#ibcon#wrote, iclass 28, count 2 2006.190.07:53:08.47#ibcon#about to read 3, iclass 28, count 2 2006.190.07:53:08.50#ibcon#read 3, iclass 28, count 2 2006.190.07:53:08.50#ibcon#about to read 4, iclass 28, count 2 2006.190.07:53:08.50#ibcon#read 4, iclass 28, count 2 2006.190.07:53:08.50#ibcon#about to read 5, iclass 28, count 2 2006.190.07:53:08.50#ibcon#read 5, iclass 28, count 2 2006.190.07:53:08.50#ibcon#about to read 6, iclass 28, count 2 2006.190.07:53:08.50#ibcon#read 6, iclass 28, count 2 2006.190.07:53:08.50#ibcon#end of sib2, iclass 28, count 2 2006.190.07:53:08.50#ibcon#*after write, iclass 28, count 2 2006.190.07:53:08.50#ibcon#*before return 0, iclass 28, count 2 2006.190.07:53:08.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:08.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:08.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.07:53:08.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:08.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:08.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:08.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:08.62#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:53:08.62#ibcon#first serial, iclass 28, count 0 2006.190.07:53:08.62#ibcon#enter sib2, iclass 28, count 0 2006.190.07:53:08.62#ibcon#flushed, iclass 28, count 0 2006.190.07:53:08.62#ibcon#about to write, iclass 28, count 0 2006.190.07:53:08.62#ibcon#wrote, iclass 28, count 0 2006.190.07:53:08.62#ibcon#about to read 3, iclass 28, count 0 2006.190.07:53:08.64#ibcon#read 3, iclass 28, count 0 2006.190.07:53:08.64#ibcon#about to read 4, iclass 28, count 0 2006.190.07:53:08.64#ibcon#read 4, iclass 28, count 0 2006.190.07:53:08.64#ibcon#about to read 5, iclass 28, count 0 2006.190.07:53:08.64#ibcon#read 5, iclass 28, count 0 2006.190.07:53:08.64#ibcon#about to read 6, iclass 28, count 0 2006.190.07:53:08.64#ibcon#read 6, iclass 28, count 0 2006.190.07:53:08.64#ibcon#end of sib2, iclass 28, count 0 2006.190.07:53:08.64#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:53:08.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:53:08.64#ibcon#[25=USB\r\n] 2006.190.07:53:08.64#ibcon#*before write, iclass 28, count 0 2006.190.07:53:08.64#ibcon#enter sib2, iclass 28, count 0 2006.190.07:53:08.64#ibcon#flushed, iclass 28, count 0 2006.190.07:53:08.64#ibcon#about to write, iclass 28, count 0 2006.190.07:53:08.64#ibcon#wrote, iclass 28, count 0 2006.190.07:53:08.64#ibcon#about to read 3, iclass 28, count 0 2006.190.07:53:08.67#ibcon#read 3, iclass 28, count 0 2006.190.07:53:08.67#ibcon#about to read 4, iclass 28, count 0 2006.190.07:53:08.67#ibcon#read 4, iclass 28, count 0 2006.190.07:53:08.67#ibcon#about to read 5, iclass 28, count 0 2006.190.07:53:08.67#ibcon#read 5, iclass 28, count 0 2006.190.07:53:08.67#ibcon#about to read 6, iclass 28, count 0 2006.190.07:53:08.67#ibcon#read 6, iclass 28, count 0 2006.190.07:53:08.67#ibcon#end of sib2, iclass 28, count 0 2006.190.07:53:08.67#ibcon#*after write, iclass 28, count 0 2006.190.07:53:08.67#ibcon#*before return 0, iclass 28, count 0 2006.190.07:53:08.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:08.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:08.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:53:08.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:53:08.67$vc4f8/valo=3,672.99 2006.190.07:53:08.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.07:53:08.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.07:53:08.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:08.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:53:08.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:53:08.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:53:08.67#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:53:08.67#ibcon#first serial, iclass 30, count 0 2006.190.07:53:08.67#ibcon#enter sib2, iclass 30, count 0 2006.190.07:53:08.67#ibcon#flushed, iclass 30, count 0 2006.190.07:53:08.67#ibcon#about to write, iclass 30, count 0 2006.190.07:53:08.67#ibcon#wrote, iclass 30, count 0 2006.190.07:53:08.67#ibcon#about to read 3, iclass 30, count 0 2006.190.07:53:08.69#ibcon#read 3, iclass 30, count 0 2006.190.07:53:08.69#ibcon#about to read 4, iclass 30, count 0 2006.190.07:53:08.69#ibcon#read 4, iclass 30, count 0 2006.190.07:53:08.69#ibcon#about to read 5, iclass 30, count 0 2006.190.07:53:08.69#ibcon#read 5, iclass 30, count 0 2006.190.07:53:08.69#ibcon#about to read 6, iclass 30, count 0 2006.190.07:53:08.69#ibcon#read 6, iclass 30, count 0 2006.190.07:53:08.69#ibcon#end of sib2, iclass 30, count 0 2006.190.07:53:08.69#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:53:08.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:53:08.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:53:08.69#ibcon#*before write, iclass 30, count 0 2006.190.07:53:08.69#ibcon#enter sib2, iclass 30, count 0 2006.190.07:53:08.69#ibcon#flushed, iclass 30, count 0 2006.190.07:53:08.69#ibcon#about to write, iclass 30, count 0 2006.190.07:53:08.69#ibcon#wrote, iclass 30, count 0 2006.190.07:53:08.69#ibcon#about to read 3, iclass 30, count 0 2006.190.07:53:08.73#ibcon#read 3, iclass 30, count 0 2006.190.07:53:08.73#ibcon#about to read 4, iclass 30, count 0 2006.190.07:53:08.73#ibcon#read 4, iclass 30, count 0 2006.190.07:53:08.73#ibcon#about to read 5, iclass 30, count 0 2006.190.07:53:08.73#ibcon#read 5, iclass 30, count 0 2006.190.07:53:08.73#ibcon#about to read 6, iclass 30, count 0 2006.190.07:53:08.73#ibcon#read 6, iclass 30, count 0 2006.190.07:53:08.73#ibcon#end of sib2, iclass 30, count 0 2006.190.07:53:08.73#ibcon#*after write, iclass 30, count 0 2006.190.07:53:08.73#ibcon#*before return 0, iclass 30, count 0 2006.190.07:53:08.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:53:08.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.07:53:08.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:53:08.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:53:08.73$vc4f8/va=3,6 2006.190.07:53:08.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.07:53:08.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.07:53:08.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:08.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:53:08.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:53:08.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:53:08.79#ibcon#enter wrdev, iclass 32, count 2 2006.190.07:53:08.79#ibcon#first serial, iclass 32, count 2 2006.190.07:53:08.79#ibcon#enter sib2, iclass 32, count 2 2006.190.07:53:08.79#ibcon#flushed, iclass 32, count 2 2006.190.07:53:08.79#ibcon#about to write, iclass 32, count 2 2006.190.07:53:08.79#ibcon#wrote, iclass 32, count 2 2006.190.07:53:08.79#ibcon#about to read 3, iclass 32, count 2 2006.190.07:53:08.81#ibcon#read 3, iclass 32, count 2 2006.190.07:53:08.81#ibcon#about to read 4, iclass 32, count 2 2006.190.07:53:08.81#ibcon#read 4, iclass 32, count 2 2006.190.07:53:08.81#ibcon#about to read 5, iclass 32, count 2 2006.190.07:53:08.81#ibcon#read 5, iclass 32, count 2 2006.190.07:53:08.81#ibcon#about to read 6, iclass 32, count 2 2006.190.07:53:08.81#ibcon#read 6, iclass 32, count 2 2006.190.07:53:08.81#ibcon#end of sib2, iclass 32, count 2 2006.190.07:53:08.81#ibcon#*mode == 0, iclass 32, count 2 2006.190.07:53:08.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.07:53:08.81#ibcon#[25=AT03-06\r\n] 2006.190.07:53:08.81#ibcon#*before write, iclass 32, count 2 2006.190.07:53:08.81#ibcon#enter sib2, iclass 32, count 2 2006.190.07:53:08.81#ibcon#flushed, iclass 32, count 2 2006.190.07:53:08.81#ibcon#about to write, iclass 32, count 2 2006.190.07:53:08.81#ibcon#wrote, iclass 32, count 2 2006.190.07:53:08.81#ibcon#about to read 3, iclass 32, count 2 2006.190.07:53:08.84#ibcon#read 3, iclass 32, count 2 2006.190.07:53:08.84#ibcon#about to read 4, iclass 32, count 2 2006.190.07:53:08.84#ibcon#read 4, iclass 32, count 2 2006.190.07:53:08.84#ibcon#about to read 5, iclass 32, count 2 2006.190.07:53:08.84#ibcon#read 5, iclass 32, count 2 2006.190.07:53:08.84#ibcon#about to read 6, iclass 32, count 2 2006.190.07:53:08.84#ibcon#read 6, iclass 32, count 2 2006.190.07:53:08.84#ibcon#end of sib2, iclass 32, count 2 2006.190.07:53:08.84#ibcon#*after write, iclass 32, count 2 2006.190.07:53:08.84#ibcon#*before return 0, iclass 32, count 2 2006.190.07:53:08.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:53:08.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.07:53:08.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.07:53:08.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:08.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:53:08.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:53:08.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:53:08.96#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:53:08.96#ibcon#first serial, iclass 32, count 0 2006.190.07:53:08.96#ibcon#enter sib2, iclass 32, count 0 2006.190.07:53:08.96#ibcon#flushed, iclass 32, count 0 2006.190.07:53:08.96#ibcon#about to write, iclass 32, count 0 2006.190.07:53:08.96#ibcon#wrote, iclass 32, count 0 2006.190.07:53:08.96#ibcon#about to read 3, iclass 32, count 0 2006.190.07:53:08.98#ibcon#read 3, iclass 32, count 0 2006.190.07:53:08.98#ibcon#about to read 4, iclass 32, count 0 2006.190.07:53:08.98#ibcon#read 4, iclass 32, count 0 2006.190.07:53:08.98#ibcon#about to read 5, iclass 32, count 0 2006.190.07:53:08.98#ibcon#read 5, iclass 32, count 0 2006.190.07:53:08.98#ibcon#about to read 6, iclass 32, count 0 2006.190.07:53:08.98#ibcon#read 6, iclass 32, count 0 2006.190.07:53:08.98#ibcon#end of sib2, iclass 32, count 0 2006.190.07:53:08.98#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:53:08.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:53:08.98#ibcon#[25=USB\r\n] 2006.190.07:53:08.98#ibcon#*before write, iclass 32, count 0 2006.190.07:53:08.98#ibcon#enter sib2, iclass 32, count 0 2006.190.07:53:08.98#ibcon#flushed, iclass 32, count 0 2006.190.07:53:08.98#ibcon#about to write, iclass 32, count 0 2006.190.07:53:08.98#ibcon#wrote, iclass 32, count 0 2006.190.07:53:08.98#ibcon#about to read 3, iclass 32, count 0 2006.190.07:53:09.01#ibcon#read 3, iclass 32, count 0 2006.190.07:53:09.01#ibcon#about to read 4, iclass 32, count 0 2006.190.07:53:09.01#ibcon#read 4, iclass 32, count 0 2006.190.07:53:09.01#ibcon#about to read 5, iclass 32, count 0 2006.190.07:53:09.01#ibcon#read 5, iclass 32, count 0 2006.190.07:53:09.01#ibcon#about to read 6, iclass 32, count 0 2006.190.07:53:09.01#ibcon#read 6, iclass 32, count 0 2006.190.07:53:09.01#ibcon#end of sib2, iclass 32, count 0 2006.190.07:53:09.01#ibcon#*after write, iclass 32, count 0 2006.190.07:53:09.01#ibcon#*before return 0, iclass 32, count 0 2006.190.07:53:09.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:53:09.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.07:53:09.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:53:09.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:53:09.01$vc4f8/valo=4,832.99 2006.190.07:53:09.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.07:53:09.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.07:53:09.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:09.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:09.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:09.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:09.01#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:53:09.01#ibcon#first serial, iclass 34, count 0 2006.190.07:53:09.01#ibcon#enter sib2, iclass 34, count 0 2006.190.07:53:09.01#ibcon#flushed, iclass 34, count 0 2006.190.07:53:09.01#ibcon#about to write, iclass 34, count 0 2006.190.07:53:09.01#ibcon#wrote, iclass 34, count 0 2006.190.07:53:09.01#ibcon#about to read 3, iclass 34, count 0 2006.190.07:53:09.03#ibcon#read 3, iclass 34, count 0 2006.190.07:53:09.03#ibcon#about to read 4, iclass 34, count 0 2006.190.07:53:09.03#ibcon#read 4, iclass 34, count 0 2006.190.07:53:09.03#ibcon#about to read 5, iclass 34, count 0 2006.190.07:53:09.03#ibcon#read 5, iclass 34, count 0 2006.190.07:53:09.03#ibcon#about to read 6, iclass 34, count 0 2006.190.07:53:09.03#ibcon#read 6, iclass 34, count 0 2006.190.07:53:09.03#ibcon#end of sib2, iclass 34, count 0 2006.190.07:53:09.03#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:53:09.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:53:09.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:53:09.03#ibcon#*before write, iclass 34, count 0 2006.190.07:53:09.03#ibcon#enter sib2, iclass 34, count 0 2006.190.07:53:09.03#ibcon#flushed, iclass 34, count 0 2006.190.07:53:09.03#ibcon#about to write, iclass 34, count 0 2006.190.07:53:09.03#ibcon#wrote, iclass 34, count 0 2006.190.07:53:09.03#ibcon#about to read 3, iclass 34, count 0 2006.190.07:53:09.07#ibcon#read 3, iclass 34, count 0 2006.190.07:53:09.07#ibcon#about to read 4, iclass 34, count 0 2006.190.07:53:09.07#ibcon#read 4, iclass 34, count 0 2006.190.07:53:09.07#ibcon#about to read 5, iclass 34, count 0 2006.190.07:53:09.07#ibcon#read 5, iclass 34, count 0 2006.190.07:53:09.07#ibcon#about to read 6, iclass 34, count 0 2006.190.07:53:09.07#ibcon#read 6, iclass 34, count 0 2006.190.07:53:09.07#ibcon#end of sib2, iclass 34, count 0 2006.190.07:53:09.07#ibcon#*after write, iclass 34, count 0 2006.190.07:53:09.07#ibcon#*before return 0, iclass 34, count 0 2006.190.07:53:09.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:09.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:09.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:53:09.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:53:09.07$vc4f8/va=4,7 2006.190.07:53:09.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.07:53:09.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.07:53:09.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:09.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:09.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:09.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:09.13#ibcon#enter wrdev, iclass 36, count 2 2006.190.07:53:09.13#ibcon#first serial, iclass 36, count 2 2006.190.07:53:09.13#ibcon#enter sib2, iclass 36, count 2 2006.190.07:53:09.13#ibcon#flushed, iclass 36, count 2 2006.190.07:53:09.13#ibcon#about to write, iclass 36, count 2 2006.190.07:53:09.13#ibcon#wrote, iclass 36, count 2 2006.190.07:53:09.13#ibcon#about to read 3, iclass 36, count 2 2006.190.07:53:09.15#ibcon#read 3, iclass 36, count 2 2006.190.07:53:09.15#ibcon#about to read 4, iclass 36, count 2 2006.190.07:53:09.15#ibcon#read 4, iclass 36, count 2 2006.190.07:53:09.15#ibcon#about to read 5, iclass 36, count 2 2006.190.07:53:09.15#ibcon#read 5, iclass 36, count 2 2006.190.07:53:09.15#ibcon#about to read 6, iclass 36, count 2 2006.190.07:53:09.15#ibcon#read 6, iclass 36, count 2 2006.190.07:53:09.15#ibcon#end of sib2, iclass 36, count 2 2006.190.07:53:09.15#ibcon#*mode == 0, iclass 36, count 2 2006.190.07:53:09.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.07:53:09.15#ibcon#[25=AT04-07\r\n] 2006.190.07:53:09.15#ibcon#*before write, iclass 36, count 2 2006.190.07:53:09.15#ibcon#enter sib2, iclass 36, count 2 2006.190.07:53:09.15#ibcon#flushed, iclass 36, count 2 2006.190.07:53:09.15#ibcon#about to write, iclass 36, count 2 2006.190.07:53:09.15#ibcon#wrote, iclass 36, count 2 2006.190.07:53:09.15#ibcon#about to read 3, iclass 36, count 2 2006.190.07:53:09.18#ibcon#read 3, iclass 36, count 2 2006.190.07:53:09.18#ibcon#about to read 4, iclass 36, count 2 2006.190.07:53:09.18#ibcon#read 4, iclass 36, count 2 2006.190.07:53:09.18#ibcon#about to read 5, iclass 36, count 2 2006.190.07:53:09.18#ibcon#read 5, iclass 36, count 2 2006.190.07:53:09.18#ibcon#about to read 6, iclass 36, count 2 2006.190.07:53:09.18#ibcon#read 6, iclass 36, count 2 2006.190.07:53:09.18#ibcon#end of sib2, iclass 36, count 2 2006.190.07:53:09.18#ibcon#*after write, iclass 36, count 2 2006.190.07:53:09.18#ibcon#*before return 0, iclass 36, count 2 2006.190.07:53:09.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:09.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:09.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.07:53:09.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:09.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:09.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:09.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:09.30#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:53:09.30#ibcon#first serial, iclass 36, count 0 2006.190.07:53:09.30#ibcon#enter sib2, iclass 36, count 0 2006.190.07:53:09.30#ibcon#flushed, iclass 36, count 0 2006.190.07:53:09.30#ibcon#about to write, iclass 36, count 0 2006.190.07:53:09.30#ibcon#wrote, iclass 36, count 0 2006.190.07:53:09.30#ibcon#about to read 3, iclass 36, count 0 2006.190.07:53:09.32#ibcon#read 3, iclass 36, count 0 2006.190.07:53:09.32#ibcon#about to read 4, iclass 36, count 0 2006.190.07:53:09.32#ibcon#read 4, iclass 36, count 0 2006.190.07:53:09.32#ibcon#about to read 5, iclass 36, count 0 2006.190.07:53:09.32#ibcon#read 5, iclass 36, count 0 2006.190.07:53:09.32#ibcon#about to read 6, iclass 36, count 0 2006.190.07:53:09.32#ibcon#read 6, iclass 36, count 0 2006.190.07:53:09.32#ibcon#end of sib2, iclass 36, count 0 2006.190.07:53:09.32#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:53:09.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:53:09.32#ibcon#[25=USB\r\n] 2006.190.07:53:09.32#ibcon#*before write, iclass 36, count 0 2006.190.07:53:09.32#ibcon#enter sib2, iclass 36, count 0 2006.190.07:53:09.32#ibcon#flushed, iclass 36, count 0 2006.190.07:53:09.32#ibcon#about to write, iclass 36, count 0 2006.190.07:53:09.32#ibcon#wrote, iclass 36, count 0 2006.190.07:53:09.32#ibcon#about to read 3, iclass 36, count 0 2006.190.07:53:09.35#ibcon#read 3, iclass 36, count 0 2006.190.07:53:09.35#ibcon#about to read 4, iclass 36, count 0 2006.190.07:53:09.35#ibcon#read 4, iclass 36, count 0 2006.190.07:53:09.35#ibcon#about to read 5, iclass 36, count 0 2006.190.07:53:09.35#ibcon#read 5, iclass 36, count 0 2006.190.07:53:09.35#ibcon#about to read 6, iclass 36, count 0 2006.190.07:53:09.35#ibcon#read 6, iclass 36, count 0 2006.190.07:53:09.35#ibcon#end of sib2, iclass 36, count 0 2006.190.07:53:09.35#ibcon#*after write, iclass 36, count 0 2006.190.07:53:09.35#ibcon#*before return 0, iclass 36, count 0 2006.190.07:53:09.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:09.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:09.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:53:09.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:53:09.35$vc4f8/valo=5,652.99 2006.190.07:53:09.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.07:53:09.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.07:53:09.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:09.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:09.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:09.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:09.35#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:53:09.35#ibcon#first serial, iclass 38, count 0 2006.190.07:53:09.35#ibcon#enter sib2, iclass 38, count 0 2006.190.07:53:09.35#ibcon#flushed, iclass 38, count 0 2006.190.07:53:09.35#ibcon#about to write, iclass 38, count 0 2006.190.07:53:09.35#ibcon#wrote, iclass 38, count 0 2006.190.07:53:09.35#ibcon#about to read 3, iclass 38, count 0 2006.190.07:53:09.37#ibcon#read 3, iclass 38, count 0 2006.190.07:53:09.37#ibcon#about to read 4, iclass 38, count 0 2006.190.07:53:09.37#ibcon#read 4, iclass 38, count 0 2006.190.07:53:09.37#ibcon#about to read 5, iclass 38, count 0 2006.190.07:53:09.37#ibcon#read 5, iclass 38, count 0 2006.190.07:53:09.37#ibcon#about to read 6, iclass 38, count 0 2006.190.07:53:09.37#ibcon#read 6, iclass 38, count 0 2006.190.07:53:09.37#ibcon#end of sib2, iclass 38, count 0 2006.190.07:53:09.37#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:53:09.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:53:09.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:53:09.37#ibcon#*before write, iclass 38, count 0 2006.190.07:53:09.37#ibcon#enter sib2, iclass 38, count 0 2006.190.07:53:09.37#ibcon#flushed, iclass 38, count 0 2006.190.07:53:09.37#ibcon#about to write, iclass 38, count 0 2006.190.07:53:09.37#ibcon#wrote, iclass 38, count 0 2006.190.07:53:09.37#ibcon#about to read 3, iclass 38, count 0 2006.190.07:53:09.41#ibcon#read 3, iclass 38, count 0 2006.190.07:53:09.41#ibcon#about to read 4, iclass 38, count 0 2006.190.07:53:09.41#ibcon#read 4, iclass 38, count 0 2006.190.07:53:09.41#ibcon#about to read 5, iclass 38, count 0 2006.190.07:53:09.41#ibcon#read 5, iclass 38, count 0 2006.190.07:53:09.41#ibcon#about to read 6, iclass 38, count 0 2006.190.07:53:09.41#ibcon#read 6, iclass 38, count 0 2006.190.07:53:09.41#ibcon#end of sib2, iclass 38, count 0 2006.190.07:53:09.41#ibcon#*after write, iclass 38, count 0 2006.190.07:53:09.41#ibcon#*before return 0, iclass 38, count 0 2006.190.07:53:09.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:09.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:09.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:53:09.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:53:09.41$vc4f8/va=5,7 2006.190.07:53:09.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.07:53:09.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.07:53:09.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:09.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:09.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:09.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:09.47#ibcon#enter wrdev, iclass 40, count 2 2006.190.07:53:09.47#ibcon#first serial, iclass 40, count 2 2006.190.07:53:09.47#ibcon#enter sib2, iclass 40, count 2 2006.190.07:53:09.47#ibcon#flushed, iclass 40, count 2 2006.190.07:53:09.47#ibcon#about to write, iclass 40, count 2 2006.190.07:53:09.47#ibcon#wrote, iclass 40, count 2 2006.190.07:53:09.47#ibcon#about to read 3, iclass 40, count 2 2006.190.07:53:09.49#ibcon#read 3, iclass 40, count 2 2006.190.07:53:09.49#ibcon#about to read 4, iclass 40, count 2 2006.190.07:53:09.49#ibcon#read 4, iclass 40, count 2 2006.190.07:53:09.49#ibcon#about to read 5, iclass 40, count 2 2006.190.07:53:09.49#ibcon#read 5, iclass 40, count 2 2006.190.07:53:09.49#ibcon#about to read 6, iclass 40, count 2 2006.190.07:53:09.49#ibcon#read 6, iclass 40, count 2 2006.190.07:53:09.49#ibcon#end of sib2, iclass 40, count 2 2006.190.07:53:09.49#ibcon#*mode == 0, iclass 40, count 2 2006.190.07:53:09.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.07:53:09.49#ibcon#[25=AT05-07\r\n] 2006.190.07:53:09.49#ibcon#*before write, iclass 40, count 2 2006.190.07:53:09.49#ibcon#enter sib2, iclass 40, count 2 2006.190.07:53:09.49#ibcon#flushed, iclass 40, count 2 2006.190.07:53:09.49#ibcon#about to write, iclass 40, count 2 2006.190.07:53:09.49#ibcon#wrote, iclass 40, count 2 2006.190.07:53:09.49#ibcon#about to read 3, iclass 40, count 2 2006.190.07:53:09.52#ibcon#read 3, iclass 40, count 2 2006.190.07:53:09.52#ibcon#about to read 4, iclass 40, count 2 2006.190.07:53:09.52#ibcon#read 4, iclass 40, count 2 2006.190.07:53:09.52#ibcon#about to read 5, iclass 40, count 2 2006.190.07:53:09.52#ibcon#read 5, iclass 40, count 2 2006.190.07:53:09.52#ibcon#about to read 6, iclass 40, count 2 2006.190.07:53:09.52#ibcon#read 6, iclass 40, count 2 2006.190.07:53:09.52#ibcon#end of sib2, iclass 40, count 2 2006.190.07:53:09.52#ibcon#*after write, iclass 40, count 2 2006.190.07:53:09.52#ibcon#*before return 0, iclass 40, count 2 2006.190.07:53:09.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:09.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:09.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.07:53:09.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:09.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:09.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:09.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:09.64#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:53:09.64#ibcon#first serial, iclass 40, count 0 2006.190.07:53:09.64#ibcon#enter sib2, iclass 40, count 0 2006.190.07:53:09.64#ibcon#flushed, iclass 40, count 0 2006.190.07:53:09.64#ibcon#about to write, iclass 40, count 0 2006.190.07:53:09.64#ibcon#wrote, iclass 40, count 0 2006.190.07:53:09.64#ibcon#about to read 3, iclass 40, count 0 2006.190.07:53:09.66#ibcon#read 3, iclass 40, count 0 2006.190.07:53:09.66#ibcon#about to read 4, iclass 40, count 0 2006.190.07:53:09.66#ibcon#read 4, iclass 40, count 0 2006.190.07:53:09.66#ibcon#about to read 5, iclass 40, count 0 2006.190.07:53:09.66#ibcon#read 5, iclass 40, count 0 2006.190.07:53:09.66#ibcon#about to read 6, iclass 40, count 0 2006.190.07:53:09.66#ibcon#read 6, iclass 40, count 0 2006.190.07:53:09.66#ibcon#end of sib2, iclass 40, count 0 2006.190.07:53:09.66#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:53:09.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:53:09.66#ibcon#[25=USB\r\n] 2006.190.07:53:09.66#ibcon#*before write, iclass 40, count 0 2006.190.07:53:09.66#ibcon#enter sib2, iclass 40, count 0 2006.190.07:53:09.66#ibcon#flushed, iclass 40, count 0 2006.190.07:53:09.66#ibcon#about to write, iclass 40, count 0 2006.190.07:53:09.66#ibcon#wrote, iclass 40, count 0 2006.190.07:53:09.66#ibcon#about to read 3, iclass 40, count 0 2006.190.07:53:09.69#ibcon#read 3, iclass 40, count 0 2006.190.07:53:09.69#ibcon#about to read 4, iclass 40, count 0 2006.190.07:53:09.69#ibcon#read 4, iclass 40, count 0 2006.190.07:53:09.69#ibcon#about to read 5, iclass 40, count 0 2006.190.07:53:09.69#ibcon#read 5, iclass 40, count 0 2006.190.07:53:09.69#ibcon#about to read 6, iclass 40, count 0 2006.190.07:53:09.69#ibcon#read 6, iclass 40, count 0 2006.190.07:53:09.69#ibcon#end of sib2, iclass 40, count 0 2006.190.07:53:09.69#ibcon#*after write, iclass 40, count 0 2006.190.07:53:09.69#ibcon#*before return 0, iclass 40, count 0 2006.190.07:53:09.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:09.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:09.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:53:09.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:53:09.69$vc4f8/valo=6,772.99 2006.190.07:53:09.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.07:53:09.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.07:53:09.69#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:09.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:09.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:09.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:09.69#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:53:09.69#ibcon#first serial, iclass 4, count 0 2006.190.07:53:09.69#ibcon#enter sib2, iclass 4, count 0 2006.190.07:53:09.69#ibcon#flushed, iclass 4, count 0 2006.190.07:53:09.69#ibcon#about to write, iclass 4, count 0 2006.190.07:53:09.69#ibcon#wrote, iclass 4, count 0 2006.190.07:53:09.69#ibcon#about to read 3, iclass 4, count 0 2006.190.07:53:09.71#ibcon#read 3, iclass 4, count 0 2006.190.07:53:09.71#ibcon#about to read 4, iclass 4, count 0 2006.190.07:53:09.71#ibcon#read 4, iclass 4, count 0 2006.190.07:53:09.71#ibcon#about to read 5, iclass 4, count 0 2006.190.07:53:09.71#ibcon#read 5, iclass 4, count 0 2006.190.07:53:09.71#ibcon#about to read 6, iclass 4, count 0 2006.190.07:53:09.71#ibcon#read 6, iclass 4, count 0 2006.190.07:53:09.71#ibcon#end of sib2, iclass 4, count 0 2006.190.07:53:09.71#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:53:09.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:53:09.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:53:09.71#ibcon#*before write, iclass 4, count 0 2006.190.07:53:09.71#ibcon#enter sib2, iclass 4, count 0 2006.190.07:53:09.71#ibcon#flushed, iclass 4, count 0 2006.190.07:53:09.71#ibcon#about to write, iclass 4, count 0 2006.190.07:53:09.71#ibcon#wrote, iclass 4, count 0 2006.190.07:53:09.71#ibcon#about to read 3, iclass 4, count 0 2006.190.07:53:09.75#ibcon#read 3, iclass 4, count 0 2006.190.07:53:09.75#ibcon#about to read 4, iclass 4, count 0 2006.190.07:53:09.75#ibcon#read 4, iclass 4, count 0 2006.190.07:53:09.75#ibcon#about to read 5, iclass 4, count 0 2006.190.07:53:09.75#ibcon#read 5, iclass 4, count 0 2006.190.07:53:09.75#ibcon#about to read 6, iclass 4, count 0 2006.190.07:53:09.75#ibcon#read 6, iclass 4, count 0 2006.190.07:53:09.75#ibcon#end of sib2, iclass 4, count 0 2006.190.07:53:09.75#ibcon#*after write, iclass 4, count 0 2006.190.07:53:09.75#ibcon#*before return 0, iclass 4, count 0 2006.190.07:53:09.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:09.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:09.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:53:09.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:53:09.75$vc4f8/va=6,6 2006.190.07:53:09.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.07:53:09.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.07:53:09.75#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:09.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:09.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:09.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:09.81#ibcon#enter wrdev, iclass 6, count 2 2006.190.07:53:09.81#ibcon#first serial, iclass 6, count 2 2006.190.07:53:09.81#ibcon#enter sib2, iclass 6, count 2 2006.190.07:53:09.81#ibcon#flushed, iclass 6, count 2 2006.190.07:53:09.81#ibcon#about to write, iclass 6, count 2 2006.190.07:53:09.81#ibcon#wrote, iclass 6, count 2 2006.190.07:53:09.81#ibcon#about to read 3, iclass 6, count 2 2006.190.07:53:09.83#ibcon#read 3, iclass 6, count 2 2006.190.07:53:09.83#ibcon#about to read 4, iclass 6, count 2 2006.190.07:53:09.83#ibcon#read 4, iclass 6, count 2 2006.190.07:53:09.83#ibcon#about to read 5, iclass 6, count 2 2006.190.07:53:09.83#ibcon#read 5, iclass 6, count 2 2006.190.07:53:09.83#ibcon#about to read 6, iclass 6, count 2 2006.190.07:53:09.83#ibcon#read 6, iclass 6, count 2 2006.190.07:53:09.83#ibcon#end of sib2, iclass 6, count 2 2006.190.07:53:09.83#ibcon#*mode == 0, iclass 6, count 2 2006.190.07:53:09.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.07:53:09.83#ibcon#[25=AT06-06\r\n] 2006.190.07:53:09.83#ibcon#*before write, iclass 6, count 2 2006.190.07:53:09.83#ibcon#enter sib2, iclass 6, count 2 2006.190.07:53:09.83#ibcon#flushed, iclass 6, count 2 2006.190.07:53:09.83#ibcon#about to write, iclass 6, count 2 2006.190.07:53:09.83#ibcon#wrote, iclass 6, count 2 2006.190.07:53:09.83#ibcon#about to read 3, iclass 6, count 2 2006.190.07:53:09.86#ibcon#read 3, iclass 6, count 2 2006.190.07:53:09.86#ibcon#about to read 4, iclass 6, count 2 2006.190.07:53:09.86#ibcon#read 4, iclass 6, count 2 2006.190.07:53:09.86#ibcon#about to read 5, iclass 6, count 2 2006.190.07:53:09.86#ibcon#read 5, iclass 6, count 2 2006.190.07:53:09.86#ibcon#about to read 6, iclass 6, count 2 2006.190.07:53:09.86#ibcon#read 6, iclass 6, count 2 2006.190.07:53:09.86#ibcon#end of sib2, iclass 6, count 2 2006.190.07:53:09.86#ibcon#*after write, iclass 6, count 2 2006.190.07:53:09.86#ibcon#*before return 0, iclass 6, count 2 2006.190.07:53:09.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:09.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:09.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.07:53:09.86#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:09.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:09.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:09.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:09.98#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:53:09.98#ibcon#first serial, iclass 6, count 0 2006.190.07:53:09.98#ibcon#enter sib2, iclass 6, count 0 2006.190.07:53:09.98#ibcon#flushed, iclass 6, count 0 2006.190.07:53:09.98#ibcon#about to write, iclass 6, count 0 2006.190.07:53:09.98#ibcon#wrote, iclass 6, count 0 2006.190.07:53:09.98#ibcon#about to read 3, iclass 6, count 0 2006.190.07:53:10.00#ibcon#read 3, iclass 6, count 0 2006.190.07:53:10.00#ibcon#about to read 4, iclass 6, count 0 2006.190.07:53:10.00#ibcon#read 4, iclass 6, count 0 2006.190.07:53:10.00#ibcon#about to read 5, iclass 6, count 0 2006.190.07:53:10.00#ibcon#read 5, iclass 6, count 0 2006.190.07:53:10.00#ibcon#about to read 6, iclass 6, count 0 2006.190.07:53:10.00#ibcon#read 6, iclass 6, count 0 2006.190.07:53:10.00#ibcon#end of sib2, iclass 6, count 0 2006.190.07:53:10.00#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:53:10.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:53:10.00#ibcon#[25=USB\r\n] 2006.190.07:53:10.00#ibcon#*before write, iclass 6, count 0 2006.190.07:53:10.00#ibcon#enter sib2, iclass 6, count 0 2006.190.07:53:10.00#ibcon#flushed, iclass 6, count 0 2006.190.07:53:10.00#ibcon#about to write, iclass 6, count 0 2006.190.07:53:10.00#ibcon#wrote, iclass 6, count 0 2006.190.07:53:10.00#ibcon#about to read 3, iclass 6, count 0 2006.190.07:53:10.03#ibcon#read 3, iclass 6, count 0 2006.190.07:53:10.03#ibcon#about to read 4, iclass 6, count 0 2006.190.07:53:10.03#ibcon#read 4, iclass 6, count 0 2006.190.07:53:10.03#ibcon#about to read 5, iclass 6, count 0 2006.190.07:53:10.03#ibcon#read 5, iclass 6, count 0 2006.190.07:53:10.03#ibcon#about to read 6, iclass 6, count 0 2006.190.07:53:10.03#ibcon#read 6, iclass 6, count 0 2006.190.07:53:10.03#ibcon#end of sib2, iclass 6, count 0 2006.190.07:53:10.03#ibcon#*after write, iclass 6, count 0 2006.190.07:53:10.03#ibcon#*before return 0, iclass 6, count 0 2006.190.07:53:10.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:10.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:10.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:53:10.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:53:10.03$vc4f8/valo=7,832.99 2006.190.07:53:10.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.07:53:10.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.07:53:10.03#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:10.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:10.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:10.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:10.03#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:53:10.03#ibcon#first serial, iclass 10, count 0 2006.190.07:53:10.03#ibcon#enter sib2, iclass 10, count 0 2006.190.07:53:10.03#ibcon#flushed, iclass 10, count 0 2006.190.07:53:10.03#ibcon#about to write, iclass 10, count 0 2006.190.07:53:10.03#ibcon#wrote, iclass 10, count 0 2006.190.07:53:10.03#ibcon#about to read 3, iclass 10, count 0 2006.190.07:53:10.05#ibcon#read 3, iclass 10, count 0 2006.190.07:53:10.05#ibcon#about to read 4, iclass 10, count 0 2006.190.07:53:10.05#ibcon#read 4, iclass 10, count 0 2006.190.07:53:10.05#ibcon#about to read 5, iclass 10, count 0 2006.190.07:53:10.05#ibcon#read 5, iclass 10, count 0 2006.190.07:53:10.05#ibcon#about to read 6, iclass 10, count 0 2006.190.07:53:10.05#ibcon#read 6, iclass 10, count 0 2006.190.07:53:10.05#ibcon#end of sib2, iclass 10, count 0 2006.190.07:53:10.05#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:53:10.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:53:10.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:53:10.05#ibcon#*before write, iclass 10, count 0 2006.190.07:53:10.05#ibcon#enter sib2, iclass 10, count 0 2006.190.07:53:10.05#ibcon#flushed, iclass 10, count 0 2006.190.07:53:10.05#ibcon#about to write, iclass 10, count 0 2006.190.07:53:10.05#ibcon#wrote, iclass 10, count 0 2006.190.07:53:10.05#ibcon#about to read 3, iclass 10, count 0 2006.190.07:53:10.09#ibcon#read 3, iclass 10, count 0 2006.190.07:53:10.09#ibcon#about to read 4, iclass 10, count 0 2006.190.07:53:10.09#ibcon#read 4, iclass 10, count 0 2006.190.07:53:10.09#ibcon#about to read 5, iclass 10, count 0 2006.190.07:53:10.09#ibcon#read 5, iclass 10, count 0 2006.190.07:53:10.09#ibcon#about to read 6, iclass 10, count 0 2006.190.07:53:10.09#ibcon#read 6, iclass 10, count 0 2006.190.07:53:10.09#ibcon#end of sib2, iclass 10, count 0 2006.190.07:53:10.09#ibcon#*after write, iclass 10, count 0 2006.190.07:53:10.09#ibcon#*before return 0, iclass 10, count 0 2006.190.07:53:10.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:10.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:10.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:53:10.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:53:10.09$vc4f8/va=7,6 2006.190.07:53:10.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.07:53:10.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.07:53:10.09#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:10.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:53:10.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:53:10.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:53:10.15#ibcon#enter wrdev, iclass 12, count 2 2006.190.07:53:10.15#ibcon#first serial, iclass 12, count 2 2006.190.07:53:10.15#ibcon#enter sib2, iclass 12, count 2 2006.190.07:53:10.15#ibcon#flushed, iclass 12, count 2 2006.190.07:53:10.15#ibcon#about to write, iclass 12, count 2 2006.190.07:53:10.15#ibcon#wrote, iclass 12, count 2 2006.190.07:53:10.15#ibcon#about to read 3, iclass 12, count 2 2006.190.07:53:10.17#ibcon#read 3, iclass 12, count 2 2006.190.07:53:10.17#ibcon#about to read 4, iclass 12, count 2 2006.190.07:53:10.17#ibcon#read 4, iclass 12, count 2 2006.190.07:53:10.17#ibcon#about to read 5, iclass 12, count 2 2006.190.07:53:10.17#ibcon#read 5, iclass 12, count 2 2006.190.07:53:10.17#ibcon#about to read 6, iclass 12, count 2 2006.190.07:53:10.17#ibcon#read 6, iclass 12, count 2 2006.190.07:53:10.17#ibcon#end of sib2, iclass 12, count 2 2006.190.07:53:10.17#ibcon#*mode == 0, iclass 12, count 2 2006.190.07:53:10.17#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.07:53:10.17#ibcon#[25=AT07-06\r\n] 2006.190.07:53:10.17#ibcon#*before write, iclass 12, count 2 2006.190.07:53:10.17#ibcon#enter sib2, iclass 12, count 2 2006.190.07:53:10.17#ibcon#flushed, iclass 12, count 2 2006.190.07:53:10.17#ibcon#about to write, iclass 12, count 2 2006.190.07:53:10.17#ibcon#wrote, iclass 12, count 2 2006.190.07:53:10.17#ibcon#about to read 3, iclass 12, count 2 2006.190.07:53:10.20#ibcon#read 3, iclass 12, count 2 2006.190.07:53:10.20#ibcon#about to read 4, iclass 12, count 2 2006.190.07:53:10.20#ibcon#read 4, iclass 12, count 2 2006.190.07:53:10.20#ibcon#about to read 5, iclass 12, count 2 2006.190.07:53:10.20#ibcon#read 5, iclass 12, count 2 2006.190.07:53:10.20#ibcon#about to read 6, iclass 12, count 2 2006.190.07:53:10.20#ibcon#read 6, iclass 12, count 2 2006.190.07:53:10.20#ibcon#end of sib2, iclass 12, count 2 2006.190.07:53:10.20#ibcon#*after write, iclass 12, count 2 2006.190.07:53:10.20#ibcon#*before return 0, iclass 12, count 2 2006.190.07:53:10.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:53:10.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.07:53:10.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.07:53:10.20#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:10.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:53:10.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:53:10.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:53:10.32#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:53:10.32#ibcon#first serial, iclass 12, count 0 2006.190.07:53:10.32#ibcon#enter sib2, iclass 12, count 0 2006.190.07:53:10.32#ibcon#flushed, iclass 12, count 0 2006.190.07:53:10.32#ibcon#about to write, iclass 12, count 0 2006.190.07:53:10.32#ibcon#wrote, iclass 12, count 0 2006.190.07:53:10.32#ibcon#about to read 3, iclass 12, count 0 2006.190.07:53:10.34#ibcon#read 3, iclass 12, count 0 2006.190.07:53:10.34#ibcon#about to read 4, iclass 12, count 0 2006.190.07:53:10.34#ibcon#read 4, iclass 12, count 0 2006.190.07:53:10.34#ibcon#about to read 5, iclass 12, count 0 2006.190.07:53:10.34#ibcon#read 5, iclass 12, count 0 2006.190.07:53:10.34#ibcon#about to read 6, iclass 12, count 0 2006.190.07:53:10.34#ibcon#read 6, iclass 12, count 0 2006.190.07:53:10.34#ibcon#end of sib2, iclass 12, count 0 2006.190.07:53:10.34#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:53:10.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:53:10.34#ibcon#[25=USB\r\n] 2006.190.07:53:10.34#ibcon#*before write, iclass 12, count 0 2006.190.07:53:10.34#ibcon#enter sib2, iclass 12, count 0 2006.190.07:53:10.34#ibcon#flushed, iclass 12, count 0 2006.190.07:53:10.34#ibcon#about to write, iclass 12, count 0 2006.190.07:53:10.34#ibcon#wrote, iclass 12, count 0 2006.190.07:53:10.34#ibcon#about to read 3, iclass 12, count 0 2006.190.07:53:10.37#ibcon#read 3, iclass 12, count 0 2006.190.07:53:10.37#ibcon#about to read 4, iclass 12, count 0 2006.190.07:53:10.37#ibcon#read 4, iclass 12, count 0 2006.190.07:53:10.37#ibcon#about to read 5, iclass 12, count 0 2006.190.07:53:10.37#ibcon#read 5, iclass 12, count 0 2006.190.07:53:10.37#ibcon#about to read 6, iclass 12, count 0 2006.190.07:53:10.37#ibcon#read 6, iclass 12, count 0 2006.190.07:53:10.37#ibcon#end of sib2, iclass 12, count 0 2006.190.07:53:10.37#ibcon#*after write, iclass 12, count 0 2006.190.07:53:10.37#ibcon#*before return 0, iclass 12, count 0 2006.190.07:53:10.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:53:10.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.07:53:10.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:53:10.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:53:10.37$vc4f8/valo=8,852.99 2006.190.07:53:10.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.07:53:10.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.07:53:10.37#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:10.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:53:10.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:53:10.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:53:10.37#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:53:10.37#ibcon#first serial, iclass 14, count 0 2006.190.07:53:10.37#ibcon#enter sib2, iclass 14, count 0 2006.190.07:53:10.37#ibcon#flushed, iclass 14, count 0 2006.190.07:53:10.37#ibcon#about to write, iclass 14, count 0 2006.190.07:53:10.37#ibcon#wrote, iclass 14, count 0 2006.190.07:53:10.37#ibcon#about to read 3, iclass 14, count 0 2006.190.07:53:10.39#ibcon#read 3, iclass 14, count 0 2006.190.07:53:10.39#ibcon#about to read 4, iclass 14, count 0 2006.190.07:53:10.39#ibcon#read 4, iclass 14, count 0 2006.190.07:53:10.39#ibcon#about to read 5, iclass 14, count 0 2006.190.07:53:10.39#ibcon#read 5, iclass 14, count 0 2006.190.07:53:10.39#ibcon#about to read 6, iclass 14, count 0 2006.190.07:53:10.39#ibcon#read 6, iclass 14, count 0 2006.190.07:53:10.39#ibcon#end of sib2, iclass 14, count 0 2006.190.07:53:10.39#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:53:10.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:53:10.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:53:10.39#ibcon#*before write, iclass 14, count 0 2006.190.07:53:10.39#ibcon#enter sib2, iclass 14, count 0 2006.190.07:53:10.39#ibcon#flushed, iclass 14, count 0 2006.190.07:53:10.39#ibcon#about to write, iclass 14, count 0 2006.190.07:53:10.39#ibcon#wrote, iclass 14, count 0 2006.190.07:53:10.39#ibcon#about to read 3, iclass 14, count 0 2006.190.07:53:10.43#ibcon#read 3, iclass 14, count 0 2006.190.07:53:10.43#ibcon#about to read 4, iclass 14, count 0 2006.190.07:53:10.43#ibcon#read 4, iclass 14, count 0 2006.190.07:53:10.43#ibcon#about to read 5, iclass 14, count 0 2006.190.07:53:10.43#ibcon#read 5, iclass 14, count 0 2006.190.07:53:10.43#ibcon#about to read 6, iclass 14, count 0 2006.190.07:53:10.43#ibcon#read 6, iclass 14, count 0 2006.190.07:53:10.43#ibcon#end of sib2, iclass 14, count 0 2006.190.07:53:10.43#ibcon#*after write, iclass 14, count 0 2006.190.07:53:10.43#ibcon#*before return 0, iclass 14, count 0 2006.190.07:53:10.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:53:10.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.07:53:10.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:53:10.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:53:10.43$vc4f8/va=8,6 2006.190.07:53:10.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.07:53:10.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.07:53:10.43#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:10.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:53:10.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:53:10.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:53:10.49#ibcon#enter wrdev, iclass 16, count 2 2006.190.07:53:10.49#ibcon#first serial, iclass 16, count 2 2006.190.07:53:10.49#ibcon#enter sib2, iclass 16, count 2 2006.190.07:53:10.49#ibcon#flushed, iclass 16, count 2 2006.190.07:53:10.49#ibcon#about to write, iclass 16, count 2 2006.190.07:53:10.49#ibcon#wrote, iclass 16, count 2 2006.190.07:53:10.49#ibcon#about to read 3, iclass 16, count 2 2006.190.07:53:10.51#ibcon#read 3, iclass 16, count 2 2006.190.07:53:10.51#ibcon#about to read 4, iclass 16, count 2 2006.190.07:53:10.51#ibcon#read 4, iclass 16, count 2 2006.190.07:53:10.51#ibcon#about to read 5, iclass 16, count 2 2006.190.07:53:10.51#ibcon#read 5, iclass 16, count 2 2006.190.07:53:10.51#ibcon#about to read 6, iclass 16, count 2 2006.190.07:53:10.51#ibcon#read 6, iclass 16, count 2 2006.190.07:53:10.51#ibcon#end of sib2, iclass 16, count 2 2006.190.07:53:10.51#ibcon#*mode == 0, iclass 16, count 2 2006.190.07:53:10.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.07:53:10.51#ibcon#[25=AT08-06\r\n] 2006.190.07:53:10.51#ibcon#*before write, iclass 16, count 2 2006.190.07:53:10.51#ibcon#enter sib2, iclass 16, count 2 2006.190.07:53:10.51#ibcon#flushed, iclass 16, count 2 2006.190.07:53:10.51#ibcon#about to write, iclass 16, count 2 2006.190.07:53:10.51#ibcon#wrote, iclass 16, count 2 2006.190.07:53:10.51#ibcon#about to read 3, iclass 16, count 2 2006.190.07:53:10.54#ibcon#read 3, iclass 16, count 2 2006.190.07:53:10.54#ibcon#about to read 4, iclass 16, count 2 2006.190.07:53:10.54#ibcon#read 4, iclass 16, count 2 2006.190.07:53:10.54#ibcon#about to read 5, iclass 16, count 2 2006.190.07:53:10.54#ibcon#read 5, iclass 16, count 2 2006.190.07:53:10.54#ibcon#about to read 6, iclass 16, count 2 2006.190.07:53:10.54#ibcon#read 6, iclass 16, count 2 2006.190.07:53:10.54#ibcon#end of sib2, iclass 16, count 2 2006.190.07:53:10.54#ibcon#*after write, iclass 16, count 2 2006.190.07:53:10.54#ibcon#*before return 0, iclass 16, count 2 2006.190.07:53:10.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:53:10.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.07:53:10.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.07:53:10.54#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:10.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:53:10.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:53:10.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:53:10.66#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:53:10.66#ibcon#first serial, iclass 16, count 0 2006.190.07:53:10.66#ibcon#enter sib2, iclass 16, count 0 2006.190.07:53:10.66#ibcon#flushed, iclass 16, count 0 2006.190.07:53:10.66#ibcon#about to write, iclass 16, count 0 2006.190.07:53:10.66#ibcon#wrote, iclass 16, count 0 2006.190.07:53:10.66#ibcon#about to read 3, iclass 16, count 0 2006.190.07:53:10.68#ibcon#read 3, iclass 16, count 0 2006.190.07:53:10.68#ibcon#about to read 4, iclass 16, count 0 2006.190.07:53:10.68#ibcon#read 4, iclass 16, count 0 2006.190.07:53:10.68#ibcon#about to read 5, iclass 16, count 0 2006.190.07:53:10.68#ibcon#read 5, iclass 16, count 0 2006.190.07:53:10.68#ibcon#about to read 6, iclass 16, count 0 2006.190.07:53:10.68#ibcon#read 6, iclass 16, count 0 2006.190.07:53:10.68#ibcon#end of sib2, iclass 16, count 0 2006.190.07:53:10.68#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:53:10.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:53:10.68#ibcon#[25=USB\r\n] 2006.190.07:53:10.68#ibcon#*before write, iclass 16, count 0 2006.190.07:53:10.68#ibcon#enter sib2, iclass 16, count 0 2006.190.07:53:10.68#ibcon#flushed, iclass 16, count 0 2006.190.07:53:10.68#ibcon#about to write, iclass 16, count 0 2006.190.07:53:10.68#ibcon#wrote, iclass 16, count 0 2006.190.07:53:10.68#ibcon#about to read 3, iclass 16, count 0 2006.190.07:53:10.71#ibcon#read 3, iclass 16, count 0 2006.190.07:53:10.71#ibcon#about to read 4, iclass 16, count 0 2006.190.07:53:10.71#ibcon#read 4, iclass 16, count 0 2006.190.07:53:10.71#ibcon#about to read 5, iclass 16, count 0 2006.190.07:53:10.71#ibcon#read 5, iclass 16, count 0 2006.190.07:53:10.71#ibcon#about to read 6, iclass 16, count 0 2006.190.07:53:10.71#ibcon#read 6, iclass 16, count 0 2006.190.07:53:10.71#ibcon#end of sib2, iclass 16, count 0 2006.190.07:53:10.71#ibcon#*after write, iclass 16, count 0 2006.190.07:53:10.71#ibcon#*before return 0, iclass 16, count 0 2006.190.07:53:10.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:53:10.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.07:53:10.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:53:10.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:53:10.71$vc4f8/vblo=1,632.99 2006.190.07:53:10.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.07:53:10.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.07:53:10.71#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:10.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:53:10.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:53:10.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:53:10.71#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:53:10.71#ibcon#first serial, iclass 18, count 0 2006.190.07:53:10.71#ibcon#enter sib2, iclass 18, count 0 2006.190.07:53:10.71#ibcon#flushed, iclass 18, count 0 2006.190.07:53:10.71#ibcon#about to write, iclass 18, count 0 2006.190.07:53:10.71#ibcon#wrote, iclass 18, count 0 2006.190.07:53:10.71#ibcon#about to read 3, iclass 18, count 0 2006.190.07:53:10.73#ibcon#read 3, iclass 18, count 0 2006.190.07:53:10.73#ibcon#about to read 4, iclass 18, count 0 2006.190.07:53:10.73#ibcon#read 4, iclass 18, count 0 2006.190.07:53:10.73#ibcon#about to read 5, iclass 18, count 0 2006.190.07:53:10.73#ibcon#read 5, iclass 18, count 0 2006.190.07:53:10.73#ibcon#about to read 6, iclass 18, count 0 2006.190.07:53:10.73#ibcon#read 6, iclass 18, count 0 2006.190.07:53:10.73#ibcon#end of sib2, iclass 18, count 0 2006.190.07:53:10.73#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:53:10.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:53:10.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:53:10.73#ibcon#*before write, iclass 18, count 0 2006.190.07:53:10.73#ibcon#enter sib2, iclass 18, count 0 2006.190.07:53:10.73#ibcon#flushed, iclass 18, count 0 2006.190.07:53:10.73#ibcon#about to write, iclass 18, count 0 2006.190.07:53:10.73#ibcon#wrote, iclass 18, count 0 2006.190.07:53:10.73#ibcon#about to read 3, iclass 18, count 0 2006.190.07:53:10.77#ibcon#read 3, iclass 18, count 0 2006.190.07:53:10.77#ibcon#about to read 4, iclass 18, count 0 2006.190.07:53:10.77#ibcon#read 4, iclass 18, count 0 2006.190.07:53:10.77#ibcon#about to read 5, iclass 18, count 0 2006.190.07:53:10.77#ibcon#read 5, iclass 18, count 0 2006.190.07:53:10.77#ibcon#about to read 6, iclass 18, count 0 2006.190.07:53:10.77#ibcon#read 6, iclass 18, count 0 2006.190.07:53:10.77#ibcon#end of sib2, iclass 18, count 0 2006.190.07:53:10.77#ibcon#*after write, iclass 18, count 0 2006.190.07:53:10.77#ibcon#*before return 0, iclass 18, count 0 2006.190.07:53:10.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:53:10.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.07:53:10.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:53:10.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:53:10.77$vc4f8/vb=1,4 2006.190.07:53:10.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.190.07:53:10.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.190.07:53:10.77#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:10.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:53:10.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:53:10.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:53:10.77#ibcon#enter wrdev, iclass 20, count 2 2006.190.07:53:10.77#ibcon#first serial, iclass 20, count 2 2006.190.07:53:10.77#ibcon#enter sib2, iclass 20, count 2 2006.190.07:53:10.77#ibcon#flushed, iclass 20, count 2 2006.190.07:53:10.77#ibcon#about to write, iclass 20, count 2 2006.190.07:53:10.77#ibcon#wrote, iclass 20, count 2 2006.190.07:53:10.77#ibcon#about to read 3, iclass 20, count 2 2006.190.07:53:10.79#ibcon#read 3, iclass 20, count 2 2006.190.07:53:10.79#ibcon#about to read 4, iclass 20, count 2 2006.190.07:53:10.79#ibcon#read 4, iclass 20, count 2 2006.190.07:53:10.79#ibcon#about to read 5, iclass 20, count 2 2006.190.07:53:10.79#ibcon#read 5, iclass 20, count 2 2006.190.07:53:10.79#ibcon#about to read 6, iclass 20, count 2 2006.190.07:53:10.79#ibcon#read 6, iclass 20, count 2 2006.190.07:53:10.79#ibcon#end of sib2, iclass 20, count 2 2006.190.07:53:10.79#ibcon#*mode == 0, iclass 20, count 2 2006.190.07:53:10.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.190.07:53:10.79#ibcon#[27=AT01-04\r\n] 2006.190.07:53:10.79#ibcon#*before write, iclass 20, count 2 2006.190.07:53:10.79#ibcon#enter sib2, iclass 20, count 2 2006.190.07:53:10.79#ibcon#flushed, iclass 20, count 2 2006.190.07:53:10.79#ibcon#about to write, iclass 20, count 2 2006.190.07:53:10.79#ibcon#wrote, iclass 20, count 2 2006.190.07:53:10.79#ibcon#about to read 3, iclass 20, count 2 2006.190.07:53:10.82#ibcon#read 3, iclass 20, count 2 2006.190.07:53:10.82#ibcon#about to read 4, iclass 20, count 2 2006.190.07:53:10.82#ibcon#read 4, iclass 20, count 2 2006.190.07:53:10.82#ibcon#about to read 5, iclass 20, count 2 2006.190.07:53:10.82#ibcon#read 5, iclass 20, count 2 2006.190.07:53:10.82#ibcon#about to read 6, iclass 20, count 2 2006.190.07:53:10.82#ibcon#read 6, iclass 20, count 2 2006.190.07:53:10.82#ibcon#end of sib2, iclass 20, count 2 2006.190.07:53:10.82#ibcon#*after write, iclass 20, count 2 2006.190.07:53:10.82#ibcon#*before return 0, iclass 20, count 2 2006.190.07:53:10.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:53:10.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.190.07:53:10.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.190.07:53:10.82#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:10.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:53:10.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:53:10.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:53:10.94#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:53:10.94#ibcon#first serial, iclass 20, count 0 2006.190.07:53:10.94#ibcon#enter sib2, iclass 20, count 0 2006.190.07:53:10.94#ibcon#flushed, iclass 20, count 0 2006.190.07:53:10.94#ibcon#about to write, iclass 20, count 0 2006.190.07:53:10.94#ibcon#wrote, iclass 20, count 0 2006.190.07:53:10.94#ibcon#about to read 3, iclass 20, count 0 2006.190.07:53:10.96#ibcon#read 3, iclass 20, count 0 2006.190.07:53:10.96#ibcon#about to read 4, iclass 20, count 0 2006.190.07:53:10.96#ibcon#read 4, iclass 20, count 0 2006.190.07:53:10.96#ibcon#about to read 5, iclass 20, count 0 2006.190.07:53:10.96#ibcon#read 5, iclass 20, count 0 2006.190.07:53:10.96#ibcon#about to read 6, iclass 20, count 0 2006.190.07:53:10.96#ibcon#read 6, iclass 20, count 0 2006.190.07:53:10.96#ibcon#end of sib2, iclass 20, count 0 2006.190.07:53:10.96#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:53:10.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:53:10.96#ibcon#[27=USB\r\n] 2006.190.07:53:10.96#ibcon#*before write, iclass 20, count 0 2006.190.07:53:10.96#ibcon#enter sib2, iclass 20, count 0 2006.190.07:53:10.96#ibcon#flushed, iclass 20, count 0 2006.190.07:53:10.96#ibcon#about to write, iclass 20, count 0 2006.190.07:53:10.96#ibcon#wrote, iclass 20, count 0 2006.190.07:53:10.96#ibcon#about to read 3, iclass 20, count 0 2006.190.07:53:10.99#ibcon#read 3, iclass 20, count 0 2006.190.07:53:10.99#ibcon#about to read 4, iclass 20, count 0 2006.190.07:53:10.99#ibcon#read 4, iclass 20, count 0 2006.190.07:53:10.99#ibcon#about to read 5, iclass 20, count 0 2006.190.07:53:10.99#ibcon#read 5, iclass 20, count 0 2006.190.07:53:10.99#ibcon#about to read 6, iclass 20, count 0 2006.190.07:53:10.99#ibcon#read 6, iclass 20, count 0 2006.190.07:53:10.99#ibcon#end of sib2, iclass 20, count 0 2006.190.07:53:10.99#ibcon#*after write, iclass 20, count 0 2006.190.07:53:10.99#ibcon#*before return 0, iclass 20, count 0 2006.190.07:53:10.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:53:10.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.190.07:53:10.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:53:10.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:53:10.99$vc4f8/vblo=2,640.99 2006.190.07:53:10.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.07:53:10.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.07:53:10.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:10.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:10.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:10.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:10.99#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:53:10.99#ibcon#first serial, iclass 22, count 0 2006.190.07:53:10.99#ibcon#enter sib2, iclass 22, count 0 2006.190.07:53:10.99#ibcon#flushed, iclass 22, count 0 2006.190.07:53:10.99#ibcon#about to write, iclass 22, count 0 2006.190.07:53:10.99#ibcon#wrote, iclass 22, count 0 2006.190.07:53:10.99#ibcon#about to read 3, iclass 22, count 0 2006.190.07:53:11.01#ibcon#read 3, iclass 22, count 0 2006.190.07:53:11.01#ibcon#about to read 4, iclass 22, count 0 2006.190.07:53:11.01#ibcon#read 4, iclass 22, count 0 2006.190.07:53:11.01#ibcon#about to read 5, iclass 22, count 0 2006.190.07:53:11.01#ibcon#read 5, iclass 22, count 0 2006.190.07:53:11.01#ibcon#about to read 6, iclass 22, count 0 2006.190.07:53:11.01#ibcon#read 6, iclass 22, count 0 2006.190.07:53:11.01#ibcon#end of sib2, iclass 22, count 0 2006.190.07:53:11.01#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:53:11.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:53:11.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:53:11.01#ibcon#*before write, iclass 22, count 0 2006.190.07:53:11.01#ibcon#enter sib2, iclass 22, count 0 2006.190.07:53:11.01#ibcon#flushed, iclass 22, count 0 2006.190.07:53:11.01#ibcon#about to write, iclass 22, count 0 2006.190.07:53:11.01#ibcon#wrote, iclass 22, count 0 2006.190.07:53:11.01#ibcon#about to read 3, iclass 22, count 0 2006.190.07:53:11.05#ibcon#read 3, iclass 22, count 0 2006.190.07:53:11.05#ibcon#about to read 4, iclass 22, count 0 2006.190.07:53:11.05#ibcon#read 4, iclass 22, count 0 2006.190.07:53:11.05#ibcon#about to read 5, iclass 22, count 0 2006.190.07:53:11.05#ibcon#read 5, iclass 22, count 0 2006.190.07:53:11.05#ibcon#about to read 6, iclass 22, count 0 2006.190.07:53:11.05#ibcon#read 6, iclass 22, count 0 2006.190.07:53:11.05#ibcon#end of sib2, iclass 22, count 0 2006.190.07:53:11.05#ibcon#*after write, iclass 22, count 0 2006.190.07:53:11.05#ibcon#*before return 0, iclass 22, count 0 2006.190.07:53:11.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:11.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.07:53:11.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:53:11.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:53:11.05$vc4f8/vb=2,4 2006.190.07:53:11.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.07:53:11.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.07:53:11.05#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:11.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:11.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:11.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:11.11#ibcon#enter wrdev, iclass 24, count 2 2006.190.07:53:11.11#ibcon#first serial, iclass 24, count 2 2006.190.07:53:11.11#ibcon#enter sib2, iclass 24, count 2 2006.190.07:53:11.11#ibcon#flushed, iclass 24, count 2 2006.190.07:53:11.11#ibcon#about to write, iclass 24, count 2 2006.190.07:53:11.11#ibcon#wrote, iclass 24, count 2 2006.190.07:53:11.11#ibcon#about to read 3, iclass 24, count 2 2006.190.07:53:11.13#ibcon#read 3, iclass 24, count 2 2006.190.07:53:11.13#ibcon#about to read 4, iclass 24, count 2 2006.190.07:53:11.13#ibcon#read 4, iclass 24, count 2 2006.190.07:53:11.13#ibcon#about to read 5, iclass 24, count 2 2006.190.07:53:11.13#ibcon#read 5, iclass 24, count 2 2006.190.07:53:11.13#ibcon#about to read 6, iclass 24, count 2 2006.190.07:53:11.13#ibcon#read 6, iclass 24, count 2 2006.190.07:53:11.13#ibcon#end of sib2, iclass 24, count 2 2006.190.07:53:11.13#ibcon#*mode == 0, iclass 24, count 2 2006.190.07:53:11.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.07:53:11.13#ibcon#[27=AT02-04\r\n] 2006.190.07:53:11.13#ibcon#*before write, iclass 24, count 2 2006.190.07:53:11.13#ibcon#enter sib2, iclass 24, count 2 2006.190.07:53:11.13#ibcon#flushed, iclass 24, count 2 2006.190.07:53:11.13#ibcon#about to write, iclass 24, count 2 2006.190.07:53:11.13#ibcon#wrote, iclass 24, count 2 2006.190.07:53:11.13#ibcon#about to read 3, iclass 24, count 2 2006.190.07:53:11.16#ibcon#read 3, iclass 24, count 2 2006.190.07:53:11.16#ibcon#about to read 4, iclass 24, count 2 2006.190.07:53:11.16#ibcon#read 4, iclass 24, count 2 2006.190.07:53:11.16#ibcon#about to read 5, iclass 24, count 2 2006.190.07:53:11.16#ibcon#read 5, iclass 24, count 2 2006.190.07:53:11.16#ibcon#about to read 6, iclass 24, count 2 2006.190.07:53:11.16#ibcon#read 6, iclass 24, count 2 2006.190.07:53:11.16#ibcon#end of sib2, iclass 24, count 2 2006.190.07:53:11.16#ibcon#*after write, iclass 24, count 2 2006.190.07:53:11.16#ibcon#*before return 0, iclass 24, count 2 2006.190.07:53:11.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:11.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.07:53:11.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.07:53:11.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:11.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:11.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:11.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:11.28#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:53:11.28#ibcon#first serial, iclass 24, count 0 2006.190.07:53:11.28#ibcon#enter sib2, iclass 24, count 0 2006.190.07:53:11.28#ibcon#flushed, iclass 24, count 0 2006.190.07:53:11.28#ibcon#about to write, iclass 24, count 0 2006.190.07:53:11.28#ibcon#wrote, iclass 24, count 0 2006.190.07:53:11.28#ibcon#about to read 3, iclass 24, count 0 2006.190.07:53:11.30#ibcon#read 3, iclass 24, count 0 2006.190.07:53:11.30#ibcon#about to read 4, iclass 24, count 0 2006.190.07:53:11.30#ibcon#read 4, iclass 24, count 0 2006.190.07:53:11.30#ibcon#about to read 5, iclass 24, count 0 2006.190.07:53:11.30#ibcon#read 5, iclass 24, count 0 2006.190.07:53:11.30#ibcon#about to read 6, iclass 24, count 0 2006.190.07:53:11.30#ibcon#read 6, iclass 24, count 0 2006.190.07:53:11.30#ibcon#end of sib2, iclass 24, count 0 2006.190.07:53:11.30#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:53:11.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:53:11.30#ibcon#[27=USB\r\n] 2006.190.07:53:11.30#ibcon#*before write, iclass 24, count 0 2006.190.07:53:11.30#ibcon#enter sib2, iclass 24, count 0 2006.190.07:53:11.30#ibcon#flushed, iclass 24, count 0 2006.190.07:53:11.30#ibcon#about to write, iclass 24, count 0 2006.190.07:53:11.30#ibcon#wrote, iclass 24, count 0 2006.190.07:53:11.30#ibcon#about to read 3, iclass 24, count 0 2006.190.07:53:11.33#ibcon#read 3, iclass 24, count 0 2006.190.07:53:11.33#ibcon#about to read 4, iclass 24, count 0 2006.190.07:53:11.33#ibcon#read 4, iclass 24, count 0 2006.190.07:53:11.33#ibcon#about to read 5, iclass 24, count 0 2006.190.07:53:11.33#ibcon#read 5, iclass 24, count 0 2006.190.07:53:11.33#ibcon#about to read 6, iclass 24, count 0 2006.190.07:53:11.33#ibcon#read 6, iclass 24, count 0 2006.190.07:53:11.33#ibcon#end of sib2, iclass 24, count 0 2006.190.07:53:11.33#ibcon#*after write, iclass 24, count 0 2006.190.07:53:11.33#ibcon#*before return 0, iclass 24, count 0 2006.190.07:53:11.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:11.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.07:53:11.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:53:11.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:53:11.33$vc4f8/vblo=3,656.99 2006.190.07:53:11.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.07:53:11.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.07:53:11.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:11.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:11.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:11.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:11.33#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:53:11.33#ibcon#first serial, iclass 26, count 0 2006.190.07:53:11.33#ibcon#enter sib2, iclass 26, count 0 2006.190.07:53:11.33#ibcon#flushed, iclass 26, count 0 2006.190.07:53:11.33#ibcon#about to write, iclass 26, count 0 2006.190.07:53:11.33#ibcon#wrote, iclass 26, count 0 2006.190.07:53:11.33#ibcon#about to read 3, iclass 26, count 0 2006.190.07:53:11.35#ibcon#read 3, iclass 26, count 0 2006.190.07:53:11.35#ibcon#about to read 4, iclass 26, count 0 2006.190.07:53:11.35#ibcon#read 4, iclass 26, count 0 2006.190.07:53:11.35#ibcon#about to read 5, iclass 26, count 0 2006.190.07:53:11.35#ibcon#read 5, iclass 26, count 0 2006.190.07:53:11.35#ibcon#about to read 6, iclass 26, count 0 2006.190.07:53:11.35#ibcon#read 6, iclass 26, count 0 2006.190.07:53:11.35#ibcon#end of sib2, iclass 26, count 0 2006.190.07:53:11.35#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:53:11.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:53:11.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:53:11.35#ibcon#*before write, iclass 26, count 0 2006.190.07:53:11.35#ibcon#enter sib2, iclass 26, count 0 2006.190.07:53:11.35#ibcon#flushed, iclass 26, count 0 2006.190.07:53:11.35#ibcon#about to write, iclass 26, count 0 2006.190.07:53:11.35#ibcon#wrote, iclass 26, count 0 2006.190.07:53:11.35#ibcon#about to read 3, iclass 26, count 0 2006.190.07:53:11.39#ibcon#read 3, iclass 26, count 0 2006.190.07:53:11.39#ibcon#about to read 4, iclass 26, count 0 2006.190.07:53:11.39#ibcon#read 4, iclass 26, count 0 2006.190.07:53:11.39#ibcon#about to read 5, iclass 26, count 0 2006.190.07:53:11.39#ibcon#read 5, iclass 26, count 0 2006.190.07:53:11.39#ibcon#about to read 6, iclass 26, count 0 2006.190.07:53:11.39#ibcon#read 6, iclass 26, count 0 2006.190.07:53:11.39#ibcon#end of sib2, iclass 26, count 0 2006.190.07:53:11.39#ibcon#*after write, iclass 26, count 0 2006.190.07:53:11.39#ibcon#*before return 0, iclass 26, count 0 2006.190.07:53:11.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:11.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.07:53:11.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:53:11.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:53:11.39$vc4f8/vb=3,4 2006.190.07:53:11.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.07:53:11.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.07:53:11.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:11.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:11.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:11.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:11.45#ibcon#enter wrdev, iclass 28, count 2 2006.190.07:53:11.45#ibcon#first serial, iclass 28, count 2 2006.190.07:53:11.45#ibcon#enter sib2, iclass 28, count 2 2006.190.07:53:11.45#ibcon#flushed, iclass 28, count 2 2006.190.07:53:11.45#ibcon#about to write, iclass 28, count 2 2006.190.07:53:11.45#ibcon#wrote, iclass 28, count 2 2006.190.07:53:11.45#ibcon#about to read 3, iclass 28, count 2 2006.190.07:53:11.47#ibcon#read 3, iclass 28, count 2 2006.190.07:53:11.47#ibcon#about to read 4, iclass 28, count 2 2006.190.07:53:11.47#ibcon#read 4, iclass 28, count 2 2006.190.07:53:11.47#ibcon#about to read 5, iclass 28, count 2 2006.190.07:53:11.47#ibcon#read 5, iclass 28, count 2 2006.190.07:53:11.47#ibcon#about to read 6, iclass 28, count 2 2006.190.07:53:11.47#ibcon#read 6, iclass 28, count 2 2006.190.07:53:11.47#ibcon#end of sib2, iclass 28, count 2 2006.190.07:53:11.47#ibcon#*mode == 0, iclass 28, count 2 2006.190.07:53:11.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.07:53:11.47#ibcon#[27=AT03-04\r\n] 2006.190.07:53:11.47#ibcon#*before write, iclass 28, count 2 2006.190.07:53:11.47#ibcon#enter sib2, iclass 28, count 2 2006.190.07:53:11.47#ibcon#flushed, iclass 28, count 2 2006.190.07:53:11.47#ibcon#about to write, iclass 28, count 2 2006.190.07:53:11.47#ibcon#wrote, iclass 28, count 2 2006.190.07:53:11.47#ibcon#about to read 3, iclass 28, count 2 2006.190.07:53:11.50#ibcon#read 3, iclass 28, count 2 2006.190.07:53:11.50#ibcon#about to read 4, iclass 28, count 2 2006.190.07:53:11.50#ibcon#read 4, iclass 28, count 2 2006.190.07:53:11.50#ibcon#about to read 5, iclass 28, count 2 2006.190.07:53:11.50#ibcon#read 5, iclass 28, count 2 2006.190.07:53:11.50#ibcon#about to read 6, iclass 28, count 2 2006.190.07:53:11.50#ibcon#read 6, iclass 28, count 2 2006.190.07:53:11.50#ibcon#end of sib2, iclass 28, count 2 2006.190.07:53:11.50#ibcon#*after write, iclass 28, count 2 2006.190.07:53:11.50#ibcon#*before return 0, iclass 28, count 2 2006.190.07:53:11.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:11.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.07:53:11.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.07:53:11.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:11.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:11.57#abcon#<5=/04 2.1 3.6 24.521001012.0\r\n> 2006.190.07:53:11.59#abcon#{5=INTERFACE CLEAR} 2006.190.07:53:11.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:11.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:11.62#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:53:11.62#ibcon#first serial, iclass 28, count 0 2006.190.07:53:11.62#ibcon#enter sib2, iclass 28, count 0 2006.190.07:53:11.62#ibcon#flushed, iclass 28, count 0 2006.190.07:53:11.62#ibcon#about to write, iclass 28, count 0 2006.190.07:53:11.62#ibcon#wrote, iclass 28, count 0 2006.190.07:53:11.62#ibcon#about to read 3, iclass 28, count 0 2006.190.07:53:11.64#ibcon#read 3, iclass 28, count 0 2006.190.07:53:11.64#ibcon#about to read 4, iclass 28, count 0 2006.190.07:53:11.64#ibcon#read 4, iclass 28, count 0 2006.190.07:53:11.64#ibcon#about to read 5, iclass 28, count 0 2006.190.07:53:11.64#ibcon#read 5, iclass 28, count 0 2006.190.07:53:11.64#ibcon#about to read 6, iclass 28, count 0 2006.190.07:53:11.64#ibcon#read 6, iclass 28, count 0 2006.190.07:53:11.64#ibcon#end of sib2, iclass 28, count 0 2006.190.07:53:11.64#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:53:11.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:53:11.64#ibcon#[27=USB\r\n] 2006.190.07:53:11.64#ibcon#*before write, iclass 28, count 0 2006.190.07:53:11.64#ibcon#enter sib2, iclass 28, count 0 2006.190.07:53:11.64#ibcon#flushed, iclass 28, count 0 2006.190.07:53:11.64#ibcon#about to write, iclass 28, count 0 2006.190.07:53:11.64#ibcon#wrote, iclass 28, count 0 2006.190.07:53:11.64#ibcon#about to read 3, iclass 28, count 0 2006.190.07:53:11.65#abcon#[5=S1D000X0/0*\r\n] 2006.190.07:53:11.67#ibcon#read 3, iclass 28, count 0 2006.190.07:53:11.67#ibcon#about to read 4, iclass 28, count 0 2006.190.07:53:11.67#ibcon#read 4, iclass 28, count 0 2006.190.07:53:11.67#ibcon#about to read 5, iclass 28, count 0 2006.190.07:53:11.67#ibcon#read 5, iclass 28, count 0 2006.190.07:53:11.67#ibcon#about to read 6, iclass 28, count 0 2006.190.07:53:11.67#ibcon#read 6, iclass 28, count 0 2006.190.07:53:11.67#ibcon#end of sib2, iclass 28, count 0 2006.190.07:53:11.67#ibcon#*after write, iclass 28, count 0 2006.190.07:53:11.67#ibcon#*before return 0, iclass 28, count 0 2006.190.07:53:11.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:11.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.07:53:11.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:53:11.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:53:11.67$vc4f8/vblo=4,712.99 2006.190.07:53:11.67#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.07:53:11.67#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.07:53:11.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:11.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:11.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:11.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:11.67#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:53:11.67#ibcon#first serial, iclass 34, count 0 2006.190.07:53:11.67#ibcon#enter sib2, iclass 34, count 0 2006.190.07:53:11.67#ibcon#flushed, iclass 34, count 0 2006.190.07:53:11.67#ibcon#about to write, iclass 34, count 0 2006.190.07:53:11.67#ibcon#wrote, iclass 34, count 0 2006.190.07:53:11.67#ibcon#about to read 3, iclass 34, count 0 2006.190.07:53:11.69#ibcon#read 3, iclass 34, count 0 2006.190.07:53:11.69#ibcon#about to read 4, iclass 34, count 0 2006.190.07:53:11.69#ibcon#read 4, iclass 34, count 0 2006.190.07:53:11.69#ibcon#about to read 5, iclass 34, count 0 2006.190.07:53:11.69#ibcon#read 5, iclass 34, count 0 2006.190.07:53:11.69#ibcon#about to read 6, iclass 34, count 0 2006.190.07:53:11.69#ibcon#read 6, iclass 34, count 0 2006.190.07:53:11.69#ibcon#end of sib2, iclass 34, count 0 2006.190.07:53:11.69#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:53:11.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:53:11.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:53:11.69#ibcon#*before write, iclass 34, count 0 2006.190.07:53:11.69#ibcon#enter sib2, iclass 34, count 0 2006.190.07:53:11.69#ibcon#flushed, iclass 34, count 0 2006.190.07:53:11.69#ibcon#about to write, iclass 34, count 0 2006.190.07:53:11.69#ibcon#wrote, iclass 34, count 0 2006.190.07:53:11.69#ibcon#about to read 3, iclass 34, count 0 2006.190.07:53:11.73#ibcon#read 3, iclass 34, count 0 2006.190.07:53:11.73#ibcon#about to read 4, iclass 34, count 0 2006.190.07:53:11.73#ibcon#read 4, iclass 34, count 0 2006.190.07:53:11.73#ibcon#about to read 5, iclass 34, count 0 2006.190.07:53:11.73#ibcon#read 5, iclass 34, count 0 2006.190.07:53:11.73#ibcon#about to read 6, iclass 34, count 0 2006.190.07:53:11.73#ibcon#read 6, iclass 34, count 0 2006.190.07:53:11.73#ibcon#end of sib2, iclass 34, count 0 2006.190.07:53:11.73#ibcon#*after write, iclass 34, count 0 2006.190.07:53:11.73#ibcon#*before return 0, iclass 34, count 0 2006.190.07:53:11.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:11.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:53:11.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:53:11.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:53:11.73$vc4f8/vb=4,4 2006.190.07:53:11.73#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.07:53:11.73#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.07:53:11.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:11.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:11.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:11.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:11.79#ibcon#enter wrdev, iclass 36, count 2 2006.190.07:53:11.79#ibcon#first serial, iclass 36, count 2 2006.190.07:53:11.79#ibcon#enter sib2, iclass 36, count 2 2006.190.07:53:11.79#ibcon#flushed, iclass 36, count 2 2006.190.07:53:11.79#ibcon#about to write, iclass 36, count 2 2006.190.07:53:11.79#ibcon#wrote, iclass 36, count 2 2006.190.07:53:11.79#ibcon#about to read 3, iclass 36, count 2 2006.190.07:53:11.81#ibcon#read 3, iclass 36, count 2 2006.190.07:53:11.81#ibcon#about to read 4, iclass 36, count 2 2006.190.07:53:11.81#ibcon#read 4, iclass 36, count 2 2006.190.07:53:11.81#ibcon#about to read 5, iclass 36, count 2 2006.190.07:53:11.81#ibcon#read 5, iclass 36, count 2 2006.190.07:53:11.81#ibcon#about to read 6, iclass 36, count 2 2006.190.07:53:11.81#ibcon#read 6, iclass 36, count 2 2006.190.07:53:11.81#ibcon#end of sib2, iclass 36, count 2 2006.190.07:53:11.81#ibcon#*mode == 0, iclass 36, count 2 2006.190.07:53:11.81#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.07:53:11.81#ibcon#[27=AT04-04\r\n] 2006.190.07:53:11.81#ibcon#*before write, iclass 36, count 2 2006.190.07:53:11.81#ibcon#enter sib2, iclass 36, count 2 2006.190.07:53:11.81#ibcon#flushed, iclass 36, count 2 2006.190.07:53:11.81#ibcon#about to write, iclass 36, count 2 2006.190.07:53:11.81#ibcon#wrote, iclass 36, count 2 2006.190.07:53:11.81#ibcon#about to read 3, iclass 36, count 2 2006.190.07:53:11.84#ibcon#read 3, iclass 36, count 2 2006.190.07:53:11.84#ibcon#about to read 4, iclass 36, count 2 2006.190.07:53:11.84#ibcon#read 4, iclass 36, count 2 2006.190.07:53:11.84#ibcon#about to read 5, iclass 36, count 2 2006.190.07:53:11.84#ibcon#read 5, iclass 36, count 2 2006.190.07:53:11.84#ibcon#about to read 6, iclass 36, count 2 2006.190.07:53:11.84#ibcon#read 6, iclass 36, count 2 2006.190.07:53:11.84#ibcon#end of sib2, iclass 36, count 2 2006.190.07:53:11.84#ibcon#*after write, iclass 36, count 2 2006.190.07:53:11.84#ibcon#*before return 0, iclass 36, count 2 2006.190.07:53:11.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:11.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.07:53:11.84#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.07:53:11.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:11.84#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:11.96#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:11.96#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:11.96#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:53:11.96#ibcon#first serial, iclass 36, count 0 2006.190.07:53:11.96#ibcon#enter sib2, iclass 36, count 0 2006.190.07:53:11.96#ibcon#flushed, iclass 36, count 0 2006.190.07:53:11.96#ibcon#about to write, iclass 36, count 0 2006.190.07:53:11.96#ibcon#wrote, iclass 36, count 0 2006.190.07:53:11.96#ibcon#about to read 3, iclass 36, count 0 2006.190.07:53:11.98#ibcon#read 3, iclass 36, count 0 2006.190.07:53:11.98#ibcon#about to read 4, iclass 36, count 0 2006.190.07:53:11.98#ibcon#read 4, iclass 36, count 0 2006.190.07:53:11.98#ibcon#about to read 5, iclass 36, count 0 2006.190.07:53:11.98#ibcon#read 5, iclass 36, count 0 2006.190.07:53:11.98#ibcon#about to read 6, iclass 36, count 0 2006.190.07:53:11.98#ibcon#read 6, iclass 36, count 0 2006.190.07:53:11.98#ibcon#end of sib2, iclass 36, count 0 2006.190.07:53:11.98#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:53:11.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:53:11.98#ibcon#[27=USB\r\n] 2006.190.07:53:11.98#ibcon#*before write, iclass 36, count 0 2006.190.07:53:11.98#ibcon#enter sib2, iclass 36, count 0 2006.190.07:53:11.98#ibcon#flushed, iclass 36, count 0 2006.190.07:53:11.98#ibcon#about to write, iclass 36, count 0 2006.190.07:53:11.98#ibcon#wrote, iclass 36, count 0 2006.190.07:53:11.98#ibcon#about to read 3, iclass 36, count 0 2006.190.07:53:12.01#ibcon#read 3, iclass 36, count 0 2006.190.07:53:12.01#ibcon#about to read 4, iclass 36, count 0 2006.190.07:53:12.01#ibcon#read 4, iclass 36, count 0 2006.190.07:53:12.01#ibcon#about to read 5, iclass 36, count 0 2006.190.07:53:12.01#ibcon#read 5, iclass 36, count 0 2006.190.07:53:12.01#ibcon#about to read 6, iclass 36, count 0 2006.190.07:53:12.01#ibcon#read 6, iclass 36, count 0 2006.190.07:53:12.01#ibcon#end of sib2, iclass 36, count 0 2006.190.07:53:12.01#ibcon#*after write, iclass 36, count 0 2006.190.07:53:12.01#ibcon#*before return 0, iclass 36, count 0 2006.190.07:53:12.01#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:12.01#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.07:53:12.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:53:12.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:53:12.01$vc4f8/vblo=5,744.99 2006.190.07:53:12.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.07:53:12.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.07:53:12.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:12.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:12.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:12.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:12.01#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:53:12.01#ibcon#first serial, iclass 38, count 0 2006.190.07:53:12.01#ibcon#enter sib2, iclass 38, count 0 2006.190.07:53:12.01#ibcon#flushed, iclass 38, count 0 2006.190.07:53:12.01#ibcon#about to write, iclass 38, count 0 2006.190.07:53:12.01#ibcon#wrote, iclass 38, count 0 2006.190.07:53:12.01#ibcon#about to read 3, iclass 38, count 0 2006.190.07:53:12.03#ibcon#read 3, iclass 38, count 0 2006.190.07:53:12.03#ibcon#about to read 4, iclass 38, count 0 2006.190.07:53:12.03#ibcon#read 4, iclass 38, count 0 2006.190.07:53:12.03#ibcon#about to read 5, iclass 38, count 0 2006.190.07:53:12.03#ibcon#read 5, iclass 38, count 0 2006.190.07:53:12.03#ibcon#about to read 6, iclass 38, count 0 2006.190.07:53:12.03#ibcon#read 6, iclass 38, count 0 2006.190.07:53:12.03#ibcon#end of sib2, iclass 38, count 0 2006.190.07:53:12.03#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:53:12.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:53:12.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:53:12.03#ibcon#*before write, iclass 38, count 0 2006.190.07:53:12.03#ibcon#enter sib2, iclass 38, count 0 2006.190.07:53:12.03#ibcon#flushed, iclass 38, count 0 2006.190.07:53:12.03#ibcon#about to write, iclass 38, count 0 2006.190.07:53:12.03#ibcon#wrote, iclass 38, count 0 2006.190.07:53:12.03#ibcon#about to read 3, iclass 38, count 0 2006.190.07:53:12.07#ibcon#read 3, iclass 38, count 0 2006.190.07:53:12.07#ibcon#about to read 4, iclass 38, count 0 2006.190.07:53:12.07#ibcon#read 4, iclass 38, count 0 2006.190.07:53:12.07#ibcon#about to read 5, iclass 38, count 0 2006.190.07:53:12.07#ibcon#read 5, iclass 38, count 0 2006.190.07:53:12.07#ibcon#about to read 6, iclass 38, count 0 2006.190.07:53:12.07#ibcon#read 6, iclass 38, count 0 2006.190.07:53:12.07#ibcon#end of sib2, iclass 38, count 0 2006.190.07:53:12.07#ibcon#*after write, iclass 38, count 0 2006.190.07:53:12.07#ibcon#*before return 0, iclass 38, count 0 2006.190.07:53:12.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:12.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.07:53:12.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:53:12.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:53:12.07$vc4f8/vb=5,4 2006.190.07:53:12.07#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.07:53:12.07#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.07:53:12.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:12.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:12.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:12.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:12.13#ibcon#enter wrdev, iclass 40, count 2 2006.190.07:53:12.13#ibcon#first serial, iclass 40, count 2 2006.190.07:53:12.13#ibcon#enter sib2, iclass 40, count 2 2006.190.07:53:12.13#ibcon#flushed, iclass 40, count 2 2006.190.07:53:12.13#ibcon#about to write, iclass 40, count 2 2006.190.07:53:12.13#ibcon#wrote, iclass 40, count 2 2006.190.07:53:12.13#ibcon#about to read 3, iclass 40, count 2 2006.190.07:53:12.15#ibcon#read 3, iclass 40, count 2 2006.190.07:53:12.15#ibcon#about to read 4, iclass 40, count 2 2006.190.07:53:12.15#ibcon#read 4, iclass 40, count 2 2006.190.07:53:12.15#ibcon#about to read 5, iclass 40, count 2 2006.190.07:53:12.15#ibcon#read 5, iclass 40, count 2 2006.190.07:53:12.15#ibcon#about to read 6, iclass 40, count 2 2006.190.07:53:12.15#ibcon#read 6, iclass 40, count 2 2006.190.07:53:12.15#ibcon#end of sib2, iclass 40, count 2 2006.190.07:53:12.15#ibcon#*mode == 0, iclass 40, count 2 2006.190.07:53:12.15#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.07:53:12.15#ibcon#[27=AT05-04\r\n] 2006.190.07:53:12.15#ibcon#*before write, iclass 40, count 2 2006.190.07:53:12.15#ibcon#enter sib2, iclass 40, count 2 2006.190.07:53:12.15#ibcon#flushed, iclass 40, count 2 2006.190.07:53:12.15#ibcon#about to write, iclass 40, count 2 2006.190.07:53:12.15#ibcon#wrote, iclass 40, count 2 2006.190.07:53:12.15#ibcon#about to read 3, iclass 40, count 2 2006.190.07:53:12.18#ibcon#read 3, iclass 40, count 2 2006.190.07:53:12.18#ibcon#about to read 4, iclass 40, count 2 2006.190.07:53:12.18#ibcon#read 4, iclass 40, count 2 2006.190.07:53:12.18#ibcon#about to read 5, iclass 40, count 2 2006.190.07:53:12.18#ibcon#read 5, iclass 40, count 2 2006.190.07:53:12.18#ibcon#about to read 6, iclass 40, count 2 2006.190.07:53:12.18#ibcon#read 6, iclass 40, count 2 2006.190.07:53:12.18#ibcon#end of sib2, iclass 40, count 2 2006.190.07:53:12.18#ibcon#*after write, iclass 40, count 2 2006.190.07:53:12.18#ibcon#*before return 0, iclass 40, count 2 2006.190.07:53:12.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:12.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.07:53:12.18#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.07:53:12.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:12.18#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:12.30#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:12.30#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:12.30#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:53:12.30#ibcon#first serial, iclass 40, count 0 2006.190.07:53:12.30#ibcon#enter sib2, iclass 40, count 0 2006.190.07:53:12.30#ibcon#flushed, iclass 40, count 0 2006.190.07:53:12.30#ibcon#about to write, iclass 40, count 0 2006.190.07:53:12.30#ibcon#wrote, iclass 40, count 0 2006.190.07:53:12.30#ibcon#about to read 3, iclass 40, count 0 2006.190.07:53:12.32#ibcon#read 3, iclass 40, count 0 2006.190.07:53:12.32#ibcon#about to read 4, iclass 40, count 0 2006.190.07:53:12.32#ibcon#read 4, iclass 40, count 0 2006.190.07:53:12.32#ibcon#about to read 5, iclass 40, count 0 2006.190.07:53:12.32#ibcon#read 5, iclass 40, count 0 2006.190.07:53:12.32#ibcon#about to read 6, iclass 40, count 0 2006.190.07:53:12.32#ibcon#read 6, iclass 40, count 0 2006.190.07:53:12.32#ibcon#end of sib2, iclass 40, count 0 2006.190.07:53:12.32#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:53:12.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:53:12.32#ibcon#[27=USB\r\n] 2006.190.07:53:12.32#ibcon#*before write, iclass 40, count 0 2006.190.07:53:12.32#ibcon#enter sib2, iclass 40, count 0 2006.190.07:53:12.32#ibcon#flushed, iclass 40, count 0 2006.190.07:53:12.32#ibcon#about to write, iclass 40, count 0 2006.190.07:53:12.32#ibcon#wrote, iclass 40, count 0 2006.190.07:53:12.32#ibcon#about to read 3, iclass 40, count 0 2006.190.07:53:12.35#ibcon#read 3, iclass 40, count 0 2006.190.07:53:12.35#ibcon#about to read 4, iclass 40, count 0 2006.190.07:53:12.35#ibcon#read 4, iclass 40, count 0 2006.190.07:53:12.35#ibcon#about to read 5, iclass 40, count 0 2006.190.07:53:12.35#ibcon#read 5, iclass 40, count 0 2006.190.07:53:12.35#ibcon#about to read 6, iclass 40, count 0 2006.190.07:53:12.35#ibcon#read 6, iclass 40, count 0 2006.190.07:53:12.35#ibcon#end of sib2, iclass 40, count 0 2006.190.07:53:12.35#ibcon#*after write, iclass 40, count 0 2006.190.07:53:12.35#ibcon#*before return 0, iclass 40, count 0 2006.190.07:53:12.35#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:12.35#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.07:53:12.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:53:12.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:53:12.35$vc4f8/vblo=6,752.99 2006.190.07:53:12.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.07:53:12.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.07:53:12.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:53:12.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:12.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:12.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:12.35#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:53:12.35#ibcon#first serial, iclass 4, count 0 2006.190.07:53:12.35#ibcon#enter sib2, iclass 4, count 0 2006.190.07:53:12.35#ibcon#flushed, iclass 4, count 0 2006.190.07:53:12.35#ibcon#about to write, iclass 4, count 0 2006.190.07:53:12.35#ibcon#wrote, iclass 4, count 0 2006.190.07:53:12.35#ibcon#about to read 3, iclass 4, count 0 2006.190.07:53:12.37#ibcon#read 3, iclass 4, count 0 2006.190.07:53:12.37#ibcon#about to read 4, iclass 4, count 0 2006.190.07:53:12.37#ibcon#read 4, iclass 4, count 0 2006.190.07:53:12.37#ibcon#about to read 5, iclass 4, count 0 2006.190.07:53:12.37#ibcon#read 5, iclass 4, count 0 2006.190.07:53:12.37#ibcon#about to read 6, iclass 4, count 0 2006.190.07:53:12.37#ibcon#read 6, iclass 4, count 0 2006.190.07:53:12.37#ibcon#end of sib2, iclass 4, count 0 2006.190.07:53:12.37#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:53:12.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:53:12.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:53:12.37#ibcon#*before write, iclass 4, count 0 2006.190.07:53:12.37#ibcon#enter sib2, iclass 4, count 0 2006.190.07:53:12.37#ibcon#flushed, iclass 4, count 0 2006.190.07:53:12.37#ibcon#about to write, iclass 4, count 0 2006.190.07:53:12.37#ibcon#wrote, iclass 4, count 0 2006.190.07:53:12.37#ibcon#about to read 3, iclass 4, count 0 2006.190.07:53:12.41#ibcon#read 3, iclass 4, count 0 2006.190.07:53:12.41#ibcon#about to read 4, iclass 4, count 0 2006.190.07:53:12.41#ibcon#read 4, iclass 4, count 0 2006.190.07:53:12.41#ibcon#about to read 5, iclass 4, count 0 2006.190.07:53:12.41#ibcon#read 5, iclass 4, count 0 2006.190.07:53:12.41#ibcon#about to read 6, iclass 4, count 0 2006.190.07:53:12.41#ibcon#read 6, iclass 4, count 0 2006.190.07:53:12.41#ibcon#end of sib2, iclass 4, count 0 2006.190.07:53:12.41#ibcon#*after write, iclass 4, count 0 2006.190.07:53:12.41#ibcon#*before return 0, iclass 4, count 0 2006.190.07:53:12.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:12.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.07:53:12.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:53:12.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:53:12.41$vc4f8/vb=6,4 2006.190.07:53:12.41#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.07:53:12.41#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.07:53:12.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:53:12.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:12.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:12.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:12.47#ibcon#enter wrdev, iclass 6, count 2 2006.190.07:53:12.47#ibcon#first serial, iclass 6, count 2 2006.190.07:53:12.47#ibcon#enter sib2, iclass 6, count 2 2006.190.07:53:12.47#ibcon#flushed, iclass 6, count 2 2006.190.07:53:12.47#ibcon#about to write, iclass 6, count 2 2006.190.07:53:12.47#ibcon#wrote, iclass 6, count 2 2006.190.07:53:12.47#ibcon#about to read 3, iclass 6, count 2 2006.190.07:53:12.49#ibcon#read 3, iclass 6, count 2 2006.190.07:53:12.49#ibcon#about to read 4, iclass 6, count 2 2006.190.07:53:12.49#ibcon#read 4, iclass 6, count 2 2006.190.07:53:12.49#ibcon#about to read 5, iclass 6, count 2 2006.190.07:53:12.49#ibcon#read 5, iclass 6, count 2 2006.190.07:53:12.49#ibcon#about to read 6, iclass 6, count 2 2006.190.07:53:12.49#ibcon#read 6, iclass 6, count 2 2006.190.07:53:12.49#ibcon#end of sib2, iclass 6, count 2 2006.190.07:53:12.49#ibcon#*mode == 0, iclass 6, count 2 2006.190.07:53:12.49#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.07:53:12.49#ibcon#[27=AT06-04\r\n] 2006.190.07:53:12.49#ibcon#*before write, iclass 6, count 2 2006.190.07:53:12.49#ibcon#enter sib2, iclass 6, count 2 2006.190.07:53:12.49#ibcon#flushed, iclass 6, count 2 2006.190.07:53:12.49#ibcon#about to write, iclass 6, count 2 2006.190.07:53:12.49#ibcon#wrote, iclass 6, count 2 2006.190.07:53:12.49#ibcon#about to read 3, iclass 6, count 2 2006.190.07:53:12.52#ibcon#read 3, iclass 6, count 2 2006.190.07:53:12.52#ibcon#about to read 4, iclass 6, count 2 2006.190.07:53:12.52#ibcon#read 4, iclass 6, count 2 2006.190.07:53:12.52#ibcon#about to read 5, iclass 6, count 2 2006.190.07:53:12.52#ibcon#read 5, iclass 6, count 2 2006.190.07:53:12.52#ibcon#about to read 6, iclass 6, count 2 2006.190.07:53:12.52#ibcon#read 6, iclass 6, count 2 2006.190.07:53:12.52#ibcon#end of sib2, iclass 6, count 2 2006.190.07:53:12.52#ibcon#*after write, iclass 6, count 2 2006.190.07:53:12.52#ibcon#*before return 0, iclass 6, count 2 2006.190.07:53:12.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:12.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.07:53:12.52#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.07:53:12.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:53:12.52#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:12.64#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:12.64#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:12.64#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:53:12.64#ibcon#first serial, iclass 6, count 0 2006.190.07:53:12.64#ibcon#enter sib2, iclass 6, count 0 2006.190.07:53:12.64#ibcon#flushed, iclass 6, count 0 2006.190.07:53:12.64#ibcon#about to write, iclass 6, count 0 2006.190.07:53:12.64#ibcon#wrote, iclass 6, count 0 2006.190.07:53:12.64#ibcon#about to read 3, iclass 6, count 0 2006.190.07:53:12.66#ibcon#read 3, iclass 6, count 0 2006.190.07:53:12.66#ibcon#about to read 4, iclass 6, count 0 2006.190.07:53:12.66#ibcon#read 4, iclass 6, count 0 2006.190.07:53:12.66#ibcon#about to read 5, iclass 6, count 0 2006.190.07:53:12.66#ibcon#read 5, iclass 6, count 0 2006.190.07:53:12.66#ibcon#about to read 6, iclass 6, count 0 2006.190.07:53:12.66#ibcon#read 6, iclass 6, count 0 2006.190.07:53:12.66#ibcon#end of sib2, iclass 6, count 0 2006.190.07:53:12.66#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:53:12.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:53:12.66#ibcon#[27=USB\r\n] 2006.190.07:53:12.66#ibcon#*before write, iclass 6, count 0 2006.190.07:53:12.66#ibcon#enter sib2, iclass 6, count 0 2006.190.07:53:12.66#ibcon#flushed, iclass 6, count 0 2006.190.07:53:12.66#ibcon#about to write, iclass 6, count 0 2006.190.07:53:12.66#ibcon#wrote, iclass 6, count 0 2006.190.07:53:12.66#ibcon#about to read 3, iclass 6, count 0 2006.190.07:53:12.69#ibcon#read 3, iclass 6, count 0 2006.190.07:53:12.69#ibcon#about to read 4, iclass 6, count 0 2006.190.07:53:12.69#ibcon#read 4, iclass 6, count 0 2006.190.07:53:12.69#ibcon#about to read 5, iclass 6, count 0 2006.190.07:53:12.69#ibcon#read 5, iclass 6, count 0 2006.190.07:53:12.69#ibcon#about to read 6, iclass 6, count 0 2006.190.07:53:12.69#ibcon#read 6, iclass 6, count 0 2006.190.07:53:12.69#ibcon#end of sib2, iclass 6, count 0 2006.190.07:53:12.69#ibcon#*after write, iclass 6, count 0 2006.190.07:53:12.69#ibcon#*before return 0, iclass 6, count 0 2006.190.07:53:12.69#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:12.69#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.07:53:12.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:53:12.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:53:12.69$vc4f8/vabw=wide 2006.190.07:53:12.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.07:53:12.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.07:53:12.69#ibcon#ireg 8 cls_cnt 0 2006.190.07:53:12.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:12.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:12.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:12.69#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:53:12.69#ibcon#first serial, iclass 10, count 0 2006.190.07:53:12.69#ibcon#enter sib2, iclass 10, count 0 2006.190.07:53:12.69#ibcon#flushed, iclass 10, count 0 2006.190.07:53:12.69#ibcon#about to write, iclass 10, count 0 2006.190.07:53:12.69#ibcon#wrote, iclass 10, count 0 2006.190.07:53:12.69#ibcon#about to read 3, iclass 10, count 0 2006.190.07:53:12.71#ibcon#read 3, iclass 10, count 0 2006.190.07:53:12.71#ibcon#about to read 4, iclass 10, count 0 2006.190.07:53:12.71#ibcon#read 4, iclass 10, count 0 2006.190.07:53:12.71#ibcon#about to read 5, iclass 10, count 0 2006.190.07:53:12.71#ibcon#read 5, iclass 10, count 0 2006.190.07:53:12.71#ibcon#about to read 6, iclass 10, count 0 2006.190.07:53:12.71#ibcon#read 6, iclass 10, count 0 2006.190.07:53:12.71#ibcon#end of sib2, iclass 10, count 0 2006.190.07:53:12.71#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:53:12.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:53:12.71#ibcon#[25=BW32\r\n] 2006.190.07:53:12.71#ibcon#*before write, iclass 10, count 0 2006.190.07:53:12.71#ibcon#enter sib2, iclass 10, count 0 2006.190.07:53:12.71#ibcon#flushed, iclass 10, count 0 2006.190.07:53:12.71#ibcon#about to write, iclass 10, count 0 2006.190.07:53:12.71#ibcon#wrote, iclass 10, count 0 2006.190.07:53:12.71#ibcon#about to read 3, iclass 10, count 0 2006.190.07:53:12.74#ibcon#read 3, iclass 10, count 0 2006.190.07:53:12.74#ibcon#about to read 4, iclass 10, count 0 2006.190.07:53:12.74#ibcon#read 4, iclass 10, count 0 2006.190.07:53:12.74#ibcon#about to read 5, iclass 10, count 0 2006.190.07:53:12.74#ibcon#read 5, iclass 10, count 0 2006.190.07:53:12.74#ibcon#about to read 6, iclass 10, count 0 2006.190.07:53:12.74#ibcon#read 6, iclass 10, count 0 2006.190.07:53:12.74#ibcon#end of sib2, iclass 10, count 0 2006.190.07:53:12.74#ibcon#*after write, iclass 10, count 0 2006.190.07:53:12.74#ibcon#*before return 0, iclass 10, count 0 2006.190.07:53:12.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:12.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.07:53:12.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:53:12.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:53:12.74$vc4f8/vbbw=wide 2006.190.07:53:12.74#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:53:12.74#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:53:12.74#ibcon#ireg 8 cls_cnt 0 2006.190.07:53:12.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:53:12.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:53:12.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:53:12.81#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:53:12.81#ibcon#first serial, iclass 12, count 0 2006.190.07:53:12.81#ibcon#enter sib2, iclass 12, count 0 2006.190.07:53:12.81#ibcon#flushed, iclass 12, count 0 2006.190.07:53:12.81#ibcon#about to write, iclass 12, count 0 2006.190.07:53:12.81#ibcon#wrote, iclass 12, count 0 2006.190.07:53:12.81#ibcon#about to read 3, iclass 12, count 0 2006.190.07:53:12.83#ibcon#read 3, iclass 12, count 0 2006.190.07:53:12.83#ibcon#about to read 4, iclass 12, count 0 2006.190.07:53:12.83#ibcon#read 4, iclass 12, count 0 2006.190.07:53:12.83#ibcon#about to read 5, iclass 12, count 0 2006.190.07:53:12.83#ibcon#read 5, iclass 12, count 0 2006.190.07:53:12.83#ibcon#about to read 6, iclass 12, count 0 2006.190.07:53:12.83#ibcon#read 6, iclass 12, count 0 2006.190.07:53:12.83#ibcon#end of sib2, iclass 12, count 0 2006.190.07:53:12.83#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:53:12.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:53:12.83#ibcon#[27=BW32\r\n] 2006.190.07:53:12.83#ibcon#*before write, iclass 12, count 0 2006.190.07:53:12.83#ibcon#enter sib2, iclass 12, count 0 2006.190.07:53:12.83#ibcon#flushed, iclass 12, count 0 2006.190.07:53:12.83#ibcon#about to write, iclass 12, count 0 2006.190.07:53:12.83#ibcon#wrote, iclass 12, count 0 2006.190.07:53:12.83#ibcon#about to read 3, iclass 12, count 0 2006.190.07:53:12.86#ibcon#read 3, iclass 12, count 0 2006.190.07:53:12.86#ibcon#about to read 4, iclass 12, count 0 2006.190.07:53:12.86#ibcon#read 4, iclass 12, count 0 2006.190.07:53:12.86#ibcon#about to read 5, iclass 12, count 0 2006.190.07:53:12.86#ibcon#read 5, iclass 12, count 0 2006.190.07:53:12.86#ibcon#about to read 6, iclass 12, count 0 2006.190.07:53:12.86#ibcon#read 6, iclass 12, count 0 2006.190.07:53:12.86#ibcon#end of sib2, iclass 12, count 0 2006.190.07:53:12.86#ibcon#*after write, iclass 12, count 0 2006.190.07:53:12.86#ibcon#*before return 0, iclass 12, count 0 2006.190.07:53:12.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:53:12.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:53:12.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:53:12.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:53:12.86$4f8m12a/ifd4f 2006.190.07:53:12.86$ifd4f/lo= 2006.190.07:53:12.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:53:12.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:53:12.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:53:12.86$ifd4f/patch= 2006.190.07:53:12.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:53:12.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:53:12.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:53:12.86$4f8m12a/"form=m,16.000,1:2 2006.190.07:53:12.86$4f8m12a/"tpicd 2006.190.07:53:12.86$4f8m12a/echo=off 2006.190.07:53:12.86$4f8m12a/xlog=off 2006.190.07:53:12.86:!2006.190.07:54:50 2006.190.07:53:29.14#trakl#Source acquired 2006.190.07:53:31.14#flagr#flagr/antenna,acquired 2006.190.07:54:50.00:preob 2006.190.07:54:50.13/onsource/TRACKING 2006.190.07:54:50.13:!2006.190.07:55:00 2006.190.07:55:00.00:data_valid=on 2006.190.07:55:00.00:midob 2006.190.07:55:01.13/onsource/TRACKING 2006.190.07:55:01.13/wx/24.52,1011.9,100 2006.190.07:55:01.32/cable/+6.4684E-03 2006.190.07:55:02.41/va/01,08,usb,yes,32,33 2006.190.07:55:02.41/va/02,07,usb,yes,32,33 2006.190.07:55:02.41/va/03,06,usb,yes,34,34 2006.190.07:55:02.41/va/04,07,usb,yes,33,35 2006.190.07:55:02.41/va/05,07,usb,yes,36,38 2006.190.07:55:02.41/va/06,06,usb,yes,35,35 2006.190.07:55:02.41/va/07,06,usb,yes,36,36 2006.190.07:55:02.41/va/08,06,usb,yes,38,38 2006.190.07:55:02.64/valo/01,532.99,yes,locked 2006.190.07:55:02.64/valo/02,572.99,yes,locked 2006.190.07:55:02.64/valo/03,672.99,yes,locked 2006.190.07:55:02.64/valo/04,832.99,yes,locked 2006.190.07:55:02.64/valo/05,652.99,yes,locked 2006.190.07:55:02.64/valo/06,772.99,yes,locked 2006.190.07:55:02.64/valo/07,832.99,yes,locked 2006.190.07:55:02.64/valo/08,852.99,yes,locked 2006.190.07:55:03.73/vb/01,04,usb,yes,28,27 2006.190.07:55:03.73/vb/02,04,usb,yes,30,32 2006.190.07:55:03.73/vb/03,04,usb,yes,27,30 2006.190.07:55:03.73/vb/04,04,usb,yes,28,28 2006.190.07:55:03.73/vb/05,04,usb,yes,26,30 2006.190.07:55:03.73/vb/06,04,usb,yes,27,30 2006.190.07:55:03.73/vb/07,04,usb,yes,29,29 2006.190.07:55:03.73/vb/08,04,usb,yes,27,30 2006.190.07:55:03.97/vblo/01,632.99,yes,locked 2006.190.07:55:03.97/vblo/02,640.99,yes,locked 2006.190.07:55:03.97/vblo/03,656.99,yes,locked 2006.190.07:55:03.97/vblo/04,712.99,yes,locked 2006.190.07:55:03.97/vblo/05,744.99,yes,locked 2006.190.07:55:03.97/vblo/06,752.99,yes,locked 2006.190.07:55:03.97/vblo/07,734.99,yes,locked 2006.190.07:55:03.97/vblo/08,744.99,yes,locked 2006.190.07:55:04.12/vabw/8 2006.190.07:55:04.27/vbbw/8 2006.190.07:55:04.37/xfe/off,on,15.2 2006.190.07:55:04.75/ifatt/23,28,28,28 2006.190.07:55:05.08/fmout-gps/S +2.88E-07 2006.190.07:55:05.16:!2006.190.07:56:00 2006.190.07:56:00.00:data_valid=off 2006.190.07:56:00.00:postob 2006.190.07:56:00.18/cable/+6.4684E-03 2006.190.07:56:00.18/wx/24.52,1011.9,100 2006.190.07:56:01.08/fmout-gps/S +2.87E-07 2006.190.07:56:01.08:scan_name=190-0758,k06190,60 2006.190.07:56:01.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.190.07:56:01.13#flagr#flagr/antenna,new-source 2006.190.07:56:02.13:checkk5 2006.190.07:56:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:56:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:56:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:56:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:56:04.03/chk_obsdata//k5ts1/T1900755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:56:04.41/chk_obsdata//k5ts2/T1900755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:56:04.78/chk_obsdata//k5ts3/T1900755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:56:05.16/chk_obsdata//k5ts4/T1900755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:56:05.86/k5log//k5ts1_log_newline 2006.190.07:56:06.55/k5log//k5ts2_log_newline 2006.190.07:56:07.24/k5log//k5ts3_log_newline 2006.190.07:56:07.94/k5log//k5ts4_log_newline 2006.190.07:56:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:56:07.96:4f8m12a=2 2006.190.07:56:07.96$4f8m12a/echo=on 2006.190.07:56:07.96$4f8m12a/pcalon 2006.190.07:56:07.96$pcalon/"no phase cal control is implemented here 2006.190.07:56:07.96$4f8m12a/"tpicd=stop 2006.190.07:56:07.96$4f8m12a/vc4f8 2006.190.07:56:07.96$vc4f8/valo=1,532.99 2006.190.07:56:07.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.07:56:07.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.07:56:07.97#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:07.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:07.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:07.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:07.97#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:56:07.97#ibcon#first serial, iclass 11, count 0 2006.190.07:56:07.97#ibcon#enter sib2, iclass 11, count 0 2006.190.07:56:07.97#ibcon#flushed, iclass 11, count 0 2006.190.07:56:07.97#ibcon#about to write, iclass 11, count 0 2006.190.07:56:07.97#ibcon#wrote, iclass 11, count 0 2006.190.07:56:07.97#ibcon#about to read 3, iclass 11, count 0 2006.190.07:56:08.02#ibcon#read 3, iclass 11, count 0 2006.190.07:56:08.02#ibcon#about to read 4, iclass 11, count 0 2006.190.07:56:08.02#ibcon#read 4, iclass 11, count 0 2006.190.07:56:08.02#ibcon#about to read 5, iclass 11, count 0 2006.190.07:56:08.02#ibcon#read 5, iclass 11, count 0 2006.190.07:56:08.02#ibcon#about to read 6, iclass 11, count 0 2006.190.07:56:08.02#ibcon#read 6, iclass 11, count 0 2006.190.07:56:08.02#ibcon#end of sib2, iclass 11, count 0 2006.190.07:56:08.02#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:56:08.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:56:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:56:08.02#ibcon#*before write, iclass 11, count 0 2006.190.07:56:08.02#ibcon#enter sib2, iclass 11, count 0 2006.190.07:56:08.02#ibcon#flushed, iclass 11, count 0 2006.190.07:56:08.02#ibcon#about to write, iclass 11, count 0 2006.190.07:56:08.02#ibcon#wrote, iclass 11, count 0 2006.190.07:56:08.02#ibcon#about to read 3, iclass 11, count 0 2006.190.07:56:08.06#ibcon#read 3, iclass 11, count 0 2006.190.07:56:08.06#ibcon#about to read 4, iclass 11, count 0 2006.190.07:56:08.07#ibcon#read 4, iclass 11, count 0 2006.190.07:56:08.07#ibcon#about to read 5, iclass 11, count 0 2006.190.07:56:08.07#ibcon#read 5, iclass 11, count 0 2006.190.07:56:08.07#ibcon#about to read 6, iclass 11, count 0 2006.190.07:56:08.07#ibcon#read 6, iclass 11, count 0 2006.190.07:56:08.07#ibcon#end of sib2, iclass 11, count 0 2006.190.07:56:08.07#ibcon#*after write, iclass 11, count 0 2006.190.07:56:08.07#ibcon#*before return 0, iclass 11, count 0 2006.190.07:56:08.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:08.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:08.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:56:08.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:56:08.07$vc4f8/va=1,8 2006.190.07:56:08.07#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.07:56:08.07#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.07:56:08.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:08.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:08.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:08.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:08.07#ibcon#enter wrdev, iclass 13, count 2 2006.190.07:56:08.07#ibcon#first serial, iclass 13, count 2 2006.190.07:56:08.07#ibcon#enter sib2, iclass 13, count 2 2006.190.07:56:08.07#ibcon#flushed, iclass 13, count 2 2006.190.07:56:08.07#ibcon#about to write, iclass 13, count 2 2006.190.07:56:08.07#ibcon#wrote, iclass 13, count 2 2006.190.07:56:08.07#ibcon#about to read 3, iclass 13, count 2 2006.190.07:56:08.08#ibcon#read 3, iclass 13, count 2 2006.190.07:56:08.09#ibcon#about to read 4, iclass 13, count 2 2006.190.07:56:08.09#ibcon#read 4, iclass 13, count 2 2006.190.07:56:08.09#ibcon#about to read 5, iclass 13, count 2 2006.190.07:56:08.09#ibcon#read 5, iclass 13, count 2 2006.190.07:56:08.09#ibcon#about to read 6, iclass 13, count 2 2006.190.07:56:08.09#ibcon#read 6, iclass 13, count 2 2006.190.07:56:08.09#ibcon#end of sib2, iclass 13, count 2 2006.190.07:56:08.09#ibcon#*mode == 0, iclass 13, count 2 2006.190.07:56:08.09#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.07:56:08.09#ibcon#[25=AT01-08\r\n] 2006.190.07:56:08.09#ibcon#*before write, iclass 13, count 2 2006.190.07:56:08.09#ibcon#enter sib2, iclass 13, count 2 2006.190.07:56:08.09#ibcon#flushed, iclass 13, count 2 2006.190.07:56:08.09#ibcon#about to write, iclass 13, count 2 2006.190.07:56:08.09#ibcon#wrote, iclass 13, count 2 2006.190.07:56:08.09#ibcon#about to read 3, iclass 13, count 2 2006.190.07:56:08.11#ibcon#read 3, iclass 13, count 2 2006.190.07:56:08.11#ibcon#about to read 4, iclass 13, count 2 2006.190.07:56:08.12#ibcon#read 4, iclass 13, count 2 2006.190.07:56:08.12#ibcon#about to read 5, iclass 13, count 2 2006.190.07:56:08.12#ibcon#read 5, iclass 13, count 2 2006.190.07:56:08.12#ibcon#about to read 6, iclass 13, count 2 2006.190.07:56:08.12#ibcon#read 6, iclass 13, count 2 2006.190.07:56:08.12#ibcon#end of sib2, iclass 13, count 2 2006.190.07:56:08.12#ibcon#*after write, iclass 13, count 2 2006.190.07:56:08.12#ibcon#*before return 0, iclass 13, count 2 2006.190.07:56:08.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:08.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:08.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.07:56:08.12#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:08.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:08.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:08.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:08.24#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:56:08.24#ibcon#first serial, iclass 13, count 0 2006.190.07:56:08.24#ibcon#enter sib2, iclass 13, count 0 2006.190.07:56:08.24#ibcon#flushed, iclass 13, count 0 2006.190.07:56:08.24#ibcon#about to write, iclass 13, count 0 2006.190.07:56:08.24#ibcon#wrote, iclass 13, count 0 2006.190.07:56:08.24#ibcon#about to read 3, iclass 13, count 0 2006.190.07:56:08.26#ibcon#read 3, iclass 13, count 0 2006.190.07:56:08.26#ibcon#about to read 4, iclass 13, count 0 2006.190.07:56:08.26#ibcon#read 4, iclass 13, count 0 2006.190.07:56:08.26#ibcon#about to read 5, iclass 13, count 0 2006.190.07:56:08.26#ibcon#read 5, iclass 13, count 0 2006.190.07:56:08.26#ibcon#about to read 6, iclass 13, count 0 2006.190.07:56:08.26#ibcon#read 6, iclass 13, count 0 2006.190.07:56:08.26#ibcon#end of sib2, iclass 13, count 0 2006.190.07:56:08.26#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:56:08.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:56:08.26#ibcon#[25=USB\r\n] 2006.190.07:56:08.26#ibcon#*before write, iclass 13, count 0 2006.190.07:56:08.26#ibcon#enter sib2, iclass 13, count 0 2006.190.07:56:08.26#ibcon#flushed, iclass 13, count 0 2006.190.07:56:08.26#ibcon#about to write, iclass 13, count 0 2006.190.07:56:08.26#ibcon#wrote, iclass 13, count 0 2006.190.07:56:08.26#ibcon#about to read 3, iclass 13, count 0 2006.190.07:56:08.28#ibcon#read 3, iclass 13, count 0 2006.190.07:56:08.28#ibcon#about to read 4, iclass 13, count 0 2006.190.07:56:08.29#ibcon#read 4, iclass 13, count 0 2006.190.07:56:08.29#ibcon#about to read 5, iclass 13, count 0 2006.190.07:56:08.29#ibcon#read 5, iclass 13, count 0 2006.190.07:56:08.29#ibcon#about to read 6, iclass 13, count 0 2006.190.07:56:08.29#ibcon#read 6, iclass 13, count 0 2006.190.07:56:08.29#ibcon#end of sib2, iclass 13, count 0 2006.190.07:56:08.29#ibcon#*after write, iclass 13, count 0 2006.190.07:56:08.29#ibcon#*before return 0, iclass 13, count 0 2006.190.07:56:08.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:08.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:08.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:56:08.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:56:08.29$vc4f8/valo=2,572.99 2006.190.07:56:08.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:56:08.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:56:08.29#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:08.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:08.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:08.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:08.29#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:56:08.29#ibcon#first serial, iclass 15, count 0 2006.190.07:56:08.29#ibcon#enter sib2, iclass 15, count 0 2006.190.07:56:08.29#ibcon#flushed, iclass 15, count 0 2006.190.07:56:08.29#ibcon#about to write, iclass 15, count 0 2006.190.07:56:08.29#ibcon#wrote, iclass 15, count 0 2006.190.07:56:08.29#ibcon#about to read 3, iclass 15, count 0 2006.190.07:56:08.30#ibcon#read 3, iclass 15, count 0 2006.190.07:56:08.31#ibcon#about to read 4, iclass 15, count 0 2006.190.07:56:08.31#ibcon#read 4, iclass 15, count 0 2006.190.07:56:08.31#ibcon#about to read 5, iclass 15, count 0 2006.190.07:56:08.31#ibcon#read 5, iclass 15, count 0 2006.190.07:56:08.31#ibcon#about to read 6, iclass 15, count 0 2006.190.07:56:08.31#ibcon#read 6, iclass 15, count 0 2006.190.07:56:08.31#ibcon#end of sib2, iclass 15, count 0 2006.190.07:56:08.31#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:56:08.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:56:08.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:56:08.31#ibcon#*before write, iclass 15, count 0 2006.190.07:56:08.31#ibcon#enter sib2, iclass 15, count 0 2006.190.07:56:08.31#ibcon#flushed, iclass 15, count 0 2006.190.07:56:08.31#ibcon#about to write, iclass 15, count 0 2006.190.07:56:08.31#ibcon#wrote, iclass 15, count 0 2006.190.07:56:08.31#ibcon#about to read 3, iclass 15, count 0 2006.190.07:56:08.35#ibcon#read 3, iclass 15, count 0 2006.190.07:56:08.35#ibcon#about to read 4, iclass 15, count 0 2006.190.07:56:08.35#ibcon#read 4, iclass 15, count 0 2006.190.07:56:08.35#ibcon#about to read 5, iclass 15, count 0 2006.190.07:56:08.35#ibcon#read 5, iclass 15, count 0 2006.190.07:56:08.35#ibcon#about to read 6, iclass 15, count 0 2006.190.07:56:08.35#ibcon#read 6, iclass 15, count 0 2006.190.07:56:08.35#ibcon#end of sib2, iclass 15, count 0 2006.190.07:56:08.35#ibcon#*after write, iclass 15, count 0 2006.190.07:56:08.35#ibcon#*before return 0, iclass 15, count 0 2006.190.07:56:08.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:08.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:08.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:56:08.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:56:08.35$vc4f8/va=2,7 2006.190.07:56:08.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.07:56:08.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.07:56:08.35#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:08.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:08.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:08.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:08.41#ibcon#enter wrdev, iclass 17, count 2 2006.190.07:56:08.41#ibcon#first serial, iclass 17, count 2 2006.190.07:56:08.41#ibcon#enter sib2, iclass 17, count 2 2006.190.07:56:08.41#ibcon#flushed, iclass 17, count 2 2006.190.07:56:08.41#ibcon#about to write, iclass 17, count 2 2006.190.07:56:08.41#ibcon#wrote, iclass 17, count 2 2006.190.07:56:08.41#ibcon#about to read 3, iclass 17, count 2 2006.190.07:56:08.43#ibcon#read 3, iclass 17, count 2 2006.190.07:56:08.43#ibcon#about to read 4, iclass 17, count 2 2006.190.07:56:08.43#ibcon#read 4, iclass 17, count 2 2006.190.07:56:08.43#ibcon#about to read 5, iclass 17, count 2 2006.190.07:56:08.43#ibcon#read 5, iclass 17, count 2 2006.190.07:56:08.43#ibcon#about to read 6, iclass 17, count 2 2006.190.07:56:08.43#ibcon#read 6, iclass 17, count 2 2006.190.07:56:08.43#ibcon#end of sib2, iclass 17, count 2 2006.190.07:56:08.43#ibcon#*mode == 0, iclass 17, count 2 2006.190.07:56:08.43#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.07:56:08.43#ibcon#[25=AT02-07\r\n] 2006.190.07:56:08.43#ibcon#*before write, iclass 17, count 2 2006.190.07:56:08.43#ibcon#enter sib2, iclass 17, count 2 2006.190.07:56:08.43#ibcon#flushed, iclass 17, count 2 2006.190.07:56:08.43#ibcon#about to write, iclass 17, count 2 2006.190.07:56:08.43#ibcon#wrote, iclass 17, count 2 2006.190.07:56:08.43#ibcon#about to read 3, iclass 17, count 2 2006.190.07:56:08.46#ibcon#read 3, iclass 17, count 2 2006.190.07:56:08.46#ibcon#about to read 4, iclass 17, count 2 2006.190.07:56:08.46#ibcon#read 4, iclass 17, count 2 2006.190.07:56:08.46#ibcon#about to read 5, iclass 17, count 2 2006.190.07:56:08.46#ibcon#read 5, iclass 17, count 2 2006.190.07:56:08.46#ibcon#about to read 6, iclass 17, count 2 2006.190.07:56:08.46#ibcon#read 6, iclass 17, count 2 2006.190.07:56:08.46#ibcon#end of sib2, iclass 17, count 2 2006.190.07:56:08.46#ibcon#*after write, iclass 17, count 2 2006.190.07:56:08.46#ibcon#*before return 0, iclass 17, count 2 2006.190.07:56:08.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:08.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:08.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.07:56:08.46#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:08.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:08.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:08.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:08.57#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:56:08.58#ibcon#first serial, iclass 17, count 0 2006.190.07:56:08.58#ibcon#enter sib2, iclass 17, count 0 2006.190.07:56:08.58#ibcon#flushed, iclass 17, count 0 2006.190.07:56:08.58#ibcon#about to write, iclass 17, count 0 2006.190.07:56:08.58#ibcon#wrote, iclass 17, count 0 2006.190.07:56:08.58#ibcon#about to read 3, iclass 17, count 0 2006.190.07:56:08.59#ibcon#read 3, iclass 17, count 0 2006.190.07:56:08.59#ibcon#about to read 4, iclass 17, count 0 2006.190.07:56:08.60#ibcon#read 4, iclass 17, count 0 2006.190.07:56:08.60#ibcon#about to read 5, iclass 17, count 0 2006.190.07:56:08.60#ibcon#read 5, iclass 17, count 0 2006.190.07:56:08.60#ibcon#about to read 6, iclass 17, count 0 2006.190.07:56:08.60#ibcon#read 6, iclass 17, count 0 2006.190.07:56:08.60#ibcon#end of sib2, iclass 17, count 0 2006.190.07:56:08.60#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:56:08.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:56:08.60#ibcon#[25=USB\r\n] 2006.190.07:56:08.60#ibcon#*before write, iclass 17, count 0 2006.190.07:56:08.60#ibcon#enter sib2, iclass 17, count 0 2006.190.07:56:08.60#ibcon#flushed, iclass 17, count 0 2006.190.07:56:08.60#ibcon#about to write, iclass 17, count 0 2006.190.07:56:08.60#ibcon#wrote, iclass 17, count 0 2006.190.07:56:08.60#ibcon#about to read 3, iclass 17, count 0 2006.190.07:56:08.62#ibcon#read 3, iclass 17, count 0 2006.190.07:56:08.62#ibcon#about to read 4, iclass 17, count 0 2006.190.07:56:08.63#ibcon#read 4, iclass 17, count 0 2006.190.07:56:08.63#ibcon#about to read 5, iclass 17, count 0 2006.190.07:56:08.63#ibcon#read 5, iclass 17, count 0 2006.190.07:56:08.63#ibcon#about to read 6, iclass 17, count 0 2006.190.07:56:08.63#ibcon#read 6, iclass 17, count 0 2006.190.07:56:08.63#ibcon#end of sib2, iclass 17, count 0 2006.190.07:56:08.63#ibcon#*after write, iclass 17, count 0 2006.190.07:56:08.63#ibcon#*before return 0, iclass 17, count 0 2006.190.07:56:08.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:08.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:08.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:56:08.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:56:08.63$vc4f8/valo=3,672.99 2006.190.07:56:08.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:56:08.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:56:08.63#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:08.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:08.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:08.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:08.63#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:56:08.63#ibcon#first serial, iclass 19, count 0 2006.190.07:56:08.63#ibcon#enter sib2, iclass 19, count 0 2006.190.07:56:08.63#ibcon#flushed, iclass 19, count 0 2006.190.07:56:08.63#ibcon#about to write, iclass 19, count 0 2006.190.07:56:08.63#ibcon#wrote, iclass 19, count 0 2006.190.07:56:08.63#ibcon#about to read 3, iclass 19, count 0 2006.190.07:56:08.64#ibcon#read 3, iclass 19, count 0 2006.190.07:56:08.65#ibcon#about to read 4, iclass 19, count 0 2006.190.07:56:08.65#ibcon#read 4, iclass 19, count 0 2006.190.07:56:08.65#ibcon#about to read 5, iclass 19, count 0 2006.190.07:56:08.65#ibcon#read 5, iclass 19, count 0 2006.190.07:56:08.65#ibcon#about to read 6, iclass 19, count 0 2006.190.07:56:08.65#ibcon#read 6, iclass 19, count 0 2006.190.07:56:08.65#ibcon#end of sib2, iclass 19, count 0 2006.190.07:56:08.65#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:56:08.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:56:08.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:56:08.65#ibcon#*before write, iclass 19, count 0 2006.190.07:56:08.65#ibcon#enter sib2, iclass 19, count 0 2006.190.07:56:08.65#ibcon#flushed, iclass 19, count 0 2006.190.07:56:08.65#ibcon#about to write, iclass 19, count 0 2006.190.07:56:08.65#ibcon#wrote, iclass 19, count 0 2006.190.07:56:08.65#ibcon#about to read 3, iclass 19, count 0 2006.190.07:56:08.68#ibcon#read 3, iclass 19, count 0 2006.190.07:56:08.68#ibcon#about to read 4, iclass 19, count 0 2006.190.07:56:08.69#ibcon#read 4, iclass 19, count 0 2006.190.07:56:08.69#ibcon#about to read 5, iclass 19, count 0 2006.190.07:56:08.69#ibcon#read 5, iclass 19, count 0 2006.190.07:56:08.69#ibcon#about to read 6, iclass 19, count 0 2006.190.07:56:08.69#ibcon#read 6, iclass 19, count 0 2006.190.07:56:08.69#ibcon#end of sib2, iclass 19, count 0 2006.190.07:56:08.69#ibcon#*after write, iclass 19, count 0 2006.190.07:56:08.69#ibcon#*before return 0, iclass 19, count 0 2006.190.07:56:08.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:08.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:08.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:56:08.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:56:08.69$vc4f8/va=3,6 2006.190.07:56:08.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.07:56:08.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.07:56:08.69#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:08.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:08.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:08.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:08.74#ibcon#enter wrdev, iclass 21, count 2 2006.190.07:56:08.74#ibcon#first serial, iclass 21, count 2 2006.190.07:56:08.75#ibcon#enter sib2, iclass 21, count 2 2006.190.07:56:08.75#ibcon#flushed, iclass 21, count 2 2006.190.07:56:08.75#ibcon#about to write, iclass 21, count 2 2006.190.07:56:08.75#ibcon#wrote, iclass 21, count 2 2006.190.07:56:08.75#ibcon#about to read 3, iclass 21, count 2 2006.190.07:56:08.76#ibcon#read 3, iclass 21, count 2 2006.190.07:56:08.76#ibcon#about to read 4, iclass 21, count 2 2006.190.07:56:08.77#ibcon#read 4, iclass 21, count 2 2006.190.07:56:08.77#ibcon#about to read 5, iclass 21, count 2 2006.190.07:56:08.77#ibcon#read 5, iclass 21, count 2 2006.190.07:56:08.77#ibcon#about to read 6, iclass 21, count 2 2006.190.07:56:08.77#ibcon#read 6, iclass 21, count 2 2006.190.07:56:08.77#ibcon#end of sib2, iclass 21, count 2 2006.190.07:56:08.77#ibcon#*mode == 0, iclass 21, count 2 2006.190.07:56:08.77#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.07:56:08.77#ibcon#[25=AT03-06\r\n] 2006.190.07:56:08.77#ibcon#*before write, iclass 21, count 2 2006.190.07:56:08.77#ibcon#enter sib2, iclass 21, count 2 2006.190.07:56:08.77#ibcon#flushed, iclass 21, count 2 2006.190.07:56:08.77#ibcon#about to write, iclass 21, count 2 2006.190.07:56:08.77#ibcon#wrote, iclass 21, count 2 2006.190.07:56:08.77#ibcon#about to read 3, iclass 21, count 2 2006.190.07:56:08.79#ibcon#read 3, iclass 21, count 2 2006.190.07:56:08.79#ibcon#about to read 4, iclass 21, count 2 2006.190.07:56:08.79#ibcon#read 4, iclass 21, count 2 2006.190.07:56:08.80#ibcon#about to read 5, iclass 21, count 2 2006.190.07:56:08.80#ibcon#read 5, iclass 21, count 2 2006.190.07:56:08.80#ibcon#about to read 6, iclass 21, count 2 2006.190.07:56:08.80#ibcon#read 6, iclass 21, count 2 2006.190.07:56:08.80#ibcon#end of sib2, iclass 21, count 2 2006.190.07:56:08.80#ibcon#*after write, iclass 21, count 2 2006.190.07:56:08.80#ibcon#*before return 0, iclass 21, count 2 2006.190.07:56:08.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:08.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:08.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.07:56:08.80#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:08.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:08.91#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:08.91#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:08.91#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:56:08.91#ibcon#first serial, iclass 21, count 0 2006.190.07:56:08.92#ibcon#enter sib2, iclass 21, count 0 2006.190.07:56:08.92#ibcon#flushed, iclass 21, count 0 2006.190.07:56:08.92#ibcon#about to write, iclass 21, count 0 2006.190.07:56:08.92#ibcon#wrote, iclass 21, count 0 2006.190.07:56:08.92#ibcon#about to read 3, iclass 21, count 0 2006.190.07:56:08.93#ibcon#read 3, iclass 21, count 0 2006.190.07:56:08.93#ibcon#about to read 4, iclass 21, count 0 2006.190.07:56:08.94#ibcon#read 4, iclass 21, count 0 2006.190.07:56:08.94#ibcon#about to read 5, iclass 21, count 0 2006.190.07:56:08.94#ibcon#read 5, iclass 21, count 0 2006.190.07:56:08.94#ibcon#about to read 6, iclass 21, count 0 2006.190.07:56:08.94#ibcon#read 6, iclass 21, count 0 2006.190.07:56:08.94#ibcon#end of sib2, iclass 21, count 0 2006.190.07:56:08.94#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:56:08.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:56:08.94#ibcon#[25=USB\r\n] 2006.190.07:56:08.94#ibcon#*before write, iclass 21, count 0 2006.190.07:56:08.94#ibcon#enter sib2, iclass 21, count 0 2006.190.07:56:08.94#ibcon#flushed, iclass 21, count 0 2006.190.07:56:08.94#ibcon#about to write, iclass 21, count 0 2006.190.07:56:08.94#ibcon#wrote, iclass 21, count 0 2006.190.07:56:08.94#ibcon#about to read 3, iclass 21, count 0 2006.190.07:56:08.96#ibcon#read 3, iclass 21, count 0 2006.190.07:56:08.96#ibcon#about to read 4, iclass 21, count 0 2006.190.07:56:08.97#ibcon#read 4, iclass 21, count 0 2006.190.07:56:08.97#ibcon#about to read 5, iclass 21, count 0 2006.190.07:56:08.97#ibcon#read 5, iclass 21, count 0 2006.190.07:56:08.97#ibcon#about to read 6, iclass 21, count 0 2006.190.07:56:08.97#ibcon#read 6, iclass 21, count 0 2006.190.07:56:08.97#ibcon#end of sib2, iclass 21, count 0 2006.190.07:56:08.97#ibcon#*after write, iclass 21, count 0 2006.190.07:56:08.97#ibcon#*before return 0, iclass 21, count 0 2006.190.07:56:08.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:08.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:08.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:56:08.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:56:08.97$vc4f8/valo=4,832.99 2006.190.07:56:08.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.07:56:08.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.07:56:08.97#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:08.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:08.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:08.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:08.97#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:56:08.97#ibcon#first serial, iclass 23, count 0 2006.190.07:56:08.97#ibcon#enter sib2, iclass 23, count 0 2006.190.07:56:08.97#ibcon#flushed, iclass 23, count 0 2006.190.07:56:08.97#ibcon#about to write, iclass 23, count 0 2006.190.07:56:08.97#ibcon#wrote, iclass 23, count 0 2006.190.07:56:08.97#ibcon#about to read 3, iclass 23, count 0 2006.190.07:56:08.98#ibcon#read 3, iclass 23, count 0 2006.190.07:56:08.98#ibcon#about to read 4, iclass 23, count 0 2006.190.07:56:08.98#ibcon#read 4, iclass 23, count 0 2006.190.07:56:08.99#ibcon#about to read 5, iclass 23, count 0 2006.190.07:56:08.99#ibcon#read 5, iclass 23, count 0 2006.190.07:56:08.99#ibcon#about to read 6, iclass 23, count 0 2006.190.07:56:08.99#ibcon#read 6, iclass 23, count 0 2006.190.07:56:08.99#ibcon#end of sib2, iclass 23, count 0 2006.190.07:56:08.99#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:56:08.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:56:08.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:56:08.99#ibcon#*before write, iclass 23, count 0 2006.190.07:56:08.99#ibcon#enter sib2, iclass 23, count 0 2006.190.07:56:08.99#ibcon#flushed, iclass 23, count 0 2006.190.07:56:08.99#ibcon#about to write, iclass 23, count 0 2006.190.07:56:08.99#ibcon#wrote, iclass 23, count 0 2006.190.07:56:08.99#ibcon#about to read 3, iclass 23, count 0 2006.190.07:56:09.02#ibcon#read 3, iclass 23, count 0 2006.190.07:56:09.02#ibcon#about to read 4, iclass 23, count 0 2006.190.07:56:09.02#ibcon#read 4, iclass 23, count 0 2006.190.07:56:09.03#ibcon#about to read 5, iclass 23, count 0 2006.190.07:56:09.03#ibcon#read 5, iclass 23, count 0 2006.190.07:56:09.03#ibcon#about to read 6, iclass 23, count 0 2006.190.07:56:09.03#ibcon#read 6, iclass 23, count 0 2006.190.07:56:09.03#ibcon#end of sib2, iclass 23, count 0 2006.190.07:56:09.03#ibcon#*after write, iclass 23, count 0 2006.190.07:56:09.03#ibcon#*before return 0, iclass 23, count 0 2006.190.07:56:09.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:09.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:09.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:56:09.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:56:09.03$vc4f8/va=4,7 2006.190.07:56:09.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.07:56:09.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.07:56:09.03#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:09.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:09.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:09.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:09.08#ibcon#enter wrdev, iclass 25, count 2 2006.190.07:56:09.08#ibcon#first serial, iclass 25, count 2 2006.190.07:56:09.09#ibcon#enter sib2, iclass 25, count 2 2006.190.07:56:09.09#ibcon#flushed, iclass 25, count 2 2006.190.07:56:09.09#ibcon#about to write, iclass 25, count 2 2006.190.07:56:09.09#ibcon#wrote, iclass 25, count 2 2006.190.07:56:09.09#ibcon#about to read 3, iclass 25, count 2 2006.190.07:56:09.10#ibcon#read 3, iclass 25, count 2 2006.190.07:56:09.10#ibcon#about to read 4, iclass 25, count 2 2006.190.07:56:09.10#ibcon#read 4, iclass 25, count 2 2006.190.07:56:09.11#ibcon#about to read 5, iclass 25, count 2 2006.190.07:56:09.11#ibcon#read 5, iclass 25, count 2 2006.190.07:56:09.11#ibcon#about to read 6, iclass 25, count 2 2006.190.07:56:09.11#ibcon#read 6, iclass 25, count 2 2006.190.07:56:09.11#ibcon#end of sib2, iclass 25, count 2 2006.190.07:56:09.11#ibcon#*mode == 0, iclass 25, count 2 2006.190.07:56:09.11#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.07:56:09.11#ibcon#[25=AT04-07\r\n] 2006.190.07:56:09.11#ibcon#*before write, iclass 25, count 2 2006.190.07:56:09.11#ibcon#enter sib2, iclass 25, count 2 2006.190.07:56:09.11#ibcon#flushed, iclass 25, count 2 2006.190.07:56:09.11#ibcon#about to write, iclass 25, count 2 2006.190.07:56:09.11#ibcon#wrote, iclass 25, count 2 2006.190.07:56:09.11#ibcon#about to read 3, iclass 25, count 2 2006.190.07:56:09.13#ibcon#read 3, iclass 25, count 2 2006.190.07:56:09.13#ibcon#about to read 4, iclass 25, count 2 2006.190.07:56:09.13#ibcon#read 4, iclass 25, count 2 2006.190.07:56:09.14#ibcon#about to read 5, iclass 25, count 2 2006.190.07:56:09.14#ibcon#read 5, iclass 25, count 2 2006.190.07:56:09.14#ibcon#about to read 6, iclass 25, count 2 2006.190.07:56:09.14#ibcon#read 6, iclass 25, count 2 2006.190.07:56:09.14#ibcon#end of sib2, iclass 25, count 2 2006.190.07:56:09.14#ibcon#*after write, iclass 25, count 2 2006.190.07:56:09.14#ibcon#*before return 0, iclass 25, count 2 2006.190.07:56:09.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:09.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:09.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.07:56:09.14#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:09.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:09.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:09.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:09.25#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:56:09.25#ibcon#first serial, iclass 25, count 0 2006.190.07:56:09.26#ibcon#enter sib2, iclass 25, count 0 2006.190.07:56:09.26#ibcon#flushed, iclass 25, count 0 2006.190.07:56:09.26#ibcon#about to write, iclass 25, count 0 2006.190.07:56:09.26#ibcon#wrote, iclass 25, count 0 2006.190.07:56:09.26#ibcon#about to read 3, iclass 25, count 0 2006.190.07:56:09.27#ibcon#read 3, iclass 25, count 0 2006.190.07:56:09.27#ibcon#about to read 4, iclass 25, count 0 2006.190.07:56:09.28#ibcon#read 4, iclass 25, count 0 2006.190.07:56:09.28#ibcon#about to read 5, iclass 25, count 0 2006.190.07:56:09.28#ibcon#read 5, iclass 25, count 0 2006.190.07:56:09.28#ibcon#about to read 6, iclass 25, count 0 2006.190.07:56:09.28#ibcon#read 6, iclass 25, count 0 2006.190.07:56:09.28#ibcon#end of sib2, iclass 25, count 0 2006.190.07:56:09.28#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:56:09.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:56:09.28#ibcon#[25=USB\r\n] 2006.190.07:56:09.28#ibcon#*before write, iclass 25, count 0 2006.190.07:56:09.28#ibcon#enter sib2, iclass 25, count 0 2006.190.07:56:09.28#ibcon#flushed, iclass 25, count 0 2006.190.07:56:09.28#ibcon#about to write, iclass 25, count 0 2006.190.07:56:09.28#ibcon#wrote, iclass 25, count 0 2006.190.07:56:09.28#ibcon#about to read 3, iclass 25, count 0 2006.190.07:56:09.30#ibcon#read 3, iclass 25, count 0 2006.190.07:56:09.30#ibcon#about to read 4, iclass 25, count 0 2006.190.07:56:09.31#ibcon#read 4, iclass 25, count 0 2006.190.07:56:09.31#ibcon#about to read 5, iclass 25, count 0 2006.190.07:56:09.31#ibcon#read 5, iclass 25, count 0 2006.190.07:56:09.31#ibcon#about to read 6, iclass 25, count 0 2006.190.07:56:09.31#ibcon#read 6, iclass 25, count 0 2006.190.07:56:09.31#ibcon#end of sib2, iclass 25, count 0 2006.190.07:56:09.31#ibcon#*after write, iclass 25, count 0 2006.190.07:56:09.31#ibcon#*before return 0, iclass 25, count 0 2006.190.07:56:09.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:09.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:09.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:56:09.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:56:09.31$vc4f8/valo=5,652.99 2006.190.07:56:09.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.07:56:09.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.07:56:09.31#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:09.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:09.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:09.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:09.31#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:56:09.31#ibcon#first serial, iclass 27, count 0 2006.190.07:56:09.31#ibcon#enter sib2, iclass 27, count 0 2006.190.07:56:09.31#ibcon#flushed, iclass 27, count 0 2006.190.07:56:09.31#ibcon#about to write, iclass 27, count 0 2006.190.07:56:09.31#ibcon#wrote, iclass 27, count 0 2006.190.07:56:09.31#ibcon#about to read 3, iclass 27, count 0 2006.190.07:56:09.32#ibcon#read 3, iclass 27, count 0 2006.190.07:56:09.32#ibcon#about to read 4, iclass 27, count 0 2006.190.07:56:09.32#ibcon#read 4, iclass 27, count 0 2006.190.07:56:09.33#ibcon#about to read 5, iclass 27, count 0 2006.190.07:56:09.33#ibcon#read 5, iclass 27, count 0 2006.190.07:56:09.33#ibcon#about to read 6, iclass 27, count 0 2006.190.07:56:09.33#ibcon#read 6, iclass 27, count 0 2006.190.07:56:09.33#ibcon#end of sib2, iclass 27, count 0 2006.190.07:56:09.33#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:56:09.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:56:09.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:56:09.33#ibcon#*before write, iclass 27, count 0 2006.190.07:56:09.33#ibcon#enter sib2, iclass 27, count 0 2006.190.07:56:09.33#ibcon#flushed, iclass 27, count 0 2006.190.07:56:09.33#ibcon#about to write, iclass 27, count 0 2006.190.07:56:09.33#ibcon#wrote, iclass 27, count 0 2006.190.07:56:09.33#ibcon#about to read 3, iclass 27, count 0 2006.190.07:56:09.36#ibcon#read 3, iclass 27, count 0 2006.190.07:56:09.36#ibcon#about to read 4, iclass 27, count 0 2006.190.07:56:09.36#ibcon#read 4, iclass 27, count 0 2006.190.07:56:09.37#ibcon#about to read 5, iclass 27, count 0 2006.190.07:56:09.37#ibcon#read 5, iclass 27, count 0 2006.190.07:56:09.37#ibcon#about to read 6, iclass 27, count 0 2006.190.07:56:09.37#ibcon#read 6, iclass 27, count 0 2006.190.07:56:09.37#ibcon#end of sib2, iclass 27, count 0 2006.190.07:56:09.37#ibcon#*after write, iclass 27, count 0 2006.190.07:56:09.37#ibcon#*before return 0, iclass 27, count 0 2006.190.07:56:09.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:09.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:09.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:56:09.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:56:09.37$vc4f8/va=5,7 2006.190.07:56:09.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.07:56:09.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.07:56:09.37#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:09.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:09.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:09.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:09.42#ibcon#enter wrdev, iclass 29, count 2 2006.190.07:56:09.42#ibcon#first serial, iclass 29, count 2 2006.190.07:56:09.43#ibcon#enter sib2, iclass 29, count 2 2006.190.07:56:09.43#ibcon#flushed, iclass 29, count 2 2006.190.07:56:09.43#ibcon#about to write, iclass 29, count 2 2006.190.07:56:09.43#ibcon#wrote, iclass 29, count 2 2006.190.07:56:09.43#ibcon#about to read 3, iclass 29, count 2 2006.190.07:56:09.44#ibcon#read 3, iclass 29, count 2 2006.190.07:56:09.44#ibcon#about to read 4, iclass 29, count 2 2006.190.07:56:09.45#ibcon#read 4, iclass 29, count 2 2006.190.07:56:09.45#ibcon#about to read 5, iclass 29, count 2 2006.190.07:56:09.45#ibcon#read 5, iclass 29, count 2 2006.190.07:56:09.45#ibcon#about to read 6, iclass 29, count 2 2006.190.07:56:09.45#ibcon#read 6, iclass 29, count 2 2006.190.07:56:09.45#ibcon#end of sib2, iclass 29, count 2 2006.190.07:56:09.45#ibcon#*mode == 0, iclass 29, count 2 2006.190.07:56:09.45#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.07:56:09.45#ibcon#[25=AT05-07\r\n] 2006.190.07:56:09.45#ibcon#*before write, iclass 29, count 2 2006.190.07:56:09.45#ibcon#enter sib2, iclass 29, count 2 2006.190.07:56:09.45#ibcon#flushed, iclass 29, count 2 2006.190.07:56:09.45#ibcon#about to write, iclass 29, count 2 2006.190.07:56:09.45#ibcon#wrote, iclass 29, count 2 2006.190.07:56:09.45#ibcon#about to read 3, iclass 29, count 2 2006.190.07:56:09.48#ibcon#read 3, iclass 29, count 2 2006.190.07:56:09.48#ibcon#about to read 4, iclass 29, count 2 2006.190.07:56:09.48#ibcon#read 4, iclass 29, count 2 2006.190.07:56:09.48#ibcon#about to read 5, iclass 29, count 2 2006.190.07:56:09.48#ibcon#read 5, iclass 29, count 2 2006.190.07:56:09.48#ibcon#about to read 6, iclass 29, count 2 2006.190.07:56:09.48#ibcon#read 6, iclass 29, count 2 2006.190.07:56:09.48#ibcon#end of sib2, iclass 29, count 2 2006.190.07:56:09.48#ibcon#*after write, iclass 29, count 2 2006.190.07:56:09.48#ibcon#*before return 0, iclass 29, count 2 2006.190.07:56:09.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:09.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:09.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.07:56:09.48#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:09.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:09.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:09.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:09.59#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:56:09.59#ibcon#first serial, iclass 29, count 0 2006.190.07:56:09.60#ibcon#enter sib2, iclass 29, count 0 2006.190.07:56:09.60#ibcon#flushed, iclass 29, count 0 2006.190.07:56:09.60#ibcon#about to write, iclass 29, count 0 2006.190.07:56:09.60#ibcon#wrote, iclass 29, count 0 2006.190.07:56:09.60#ibcon#about to read 3, iclass 29, count 0 2006.190.07:56:09.61#ibcon#read 3, iclass 29, count 0 2006.190.07:56:09.61#ibcon#about to read 4, iclass 29, count 0 2006.190.07:56:09.62#ibcon#read 4, iclass 29, count 0 2006.190.07:56:09.62#ibcon#about to read 5, iclass 29, count 0 2006.190.07:56:09.62#ibcon#read 5, iclass 29, count 0 2006.190.07:56:09.62#ibcon#about to read 6, iclass 29, count 0 2006.190.07:56:09.62#ibcon#read 6, iclass 29, count 0 2006.190.07:56:09.62#ibcon#end of sib2, iclass 29, count 0 2006.190.07:56:09.62#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:56:09.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:56:09.62#ibcon#[25=USB\r\n] 2006.190.07:56:09.62#ibcon#*before write, iclass 29, count 0 2006.190.07:56:09.62#ibcon#enter sib2, iclass 29, count 0 2006.190.07:56:09.62#ibcon#flushed, iclass 29, count 0 2006.190.07:56:09.62#ibcon#about to write, iclass 29, count 0 2006.190.07:56:09.62#ibcon#wrote, iclass 29, count 0 2006.190.07:56:09.62#ibcon#about to read 3, iclass 29, count 0 2006.190.07:56:09.64#ibcon#read 3, iclass 29, count 0 2006.190.07:56:09.64#ibcon#about to read 4, iclass 29, count 0 2006.190.07:56:09.65#ibcon#read 4, iclass 29, count 0 2006.190.07:56:09.65#ibcon#about to read 5, iclass 29, count 0 2006.190.07:56:09.65#ibcon#read 5, iclass 29, count 0 2006.190.07:56:09.65#ibcon#about to read 6, iclass 29, count 0 2006.190.07:56:09.65#ibcon#read 6, iclass 29, count 0 2006.190.07:56:09.65#ibcon#end of sib2, iclass 29, count 0 2006.190.07:56:09.65#ibcon#*after write, iclass 29, count 0 2006.190.07:56:09.65#ibcon#*before return 0, iclass 29, count 0 2006.190.07:56:09.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:09.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:09.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:56:09.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:56:09.65$vc4f8/valo=6,772.99 2006.190.07:56:09.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.07:56:09.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.07:56:09.65#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:09.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:09.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:09.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:09.65#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:56:09.65#ibcon#first serial, iclass 31, count 0 2006.190.07:56:09.65#ibcon#enter sib2, iclass 31, count 0 2006.190.07:56:09.65#ibcon#flushed, iclass 31, count 0 2006.190.07:56:09.65#ibcon#about to write, iclass 31, count 0 2006.190.07:56:09.65#ibcon#wrote, iclass 31, count 0 2006.190.07:56:09.65#ibcon#about to read 3, iclass 31, count 0 2006.190.07:56:09.66#ibcon#read 3, iclass 31, count 0 2006.190.07:56:09.66#ibcon#about to read 4, iclass 31, count 0 2006.190.07:56:09.66#ibcon#read 4, iclass 31, count 0 2006.190.07:56:09.67#ibcon#about to read 5, iclass 31, count 0 2006.190.07:56:09.67#ibcon#read 5, iclass 31, count 0 2006.190.07:56:09.67#ibcon#about to read 6, iclass 31, count 0 2006.190.07:56:09.67#ibcon#read 6, iclass 31, count 0 2006.190.07:56:09.67#ibcon#end of sib2, iclass 31, count 0 2006.190.07:56:09.67#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:56:09.67#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:56:09.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:56:09.67#ibcon#*before write, iclass 31, count 0 2006.190.07:56:09.67#ibcon#enter sib2, iclass 31, count 0 2006.190.07:56:09.67#ibcon#flushed, iclass 31, count 0 2006.190.07:56:09.67#ibcon#about to write, iclass 31, count 0 2006.190.07:56:09.67#ibcon#wrote, iclass 31, count 0 2006.190.07:56:09.67#ibcon#about to read 3, iclass 31, count 0 2006.190.07:56:09.70#ibcon#read 3, iclass 31, count 0 2006.190.07:56:09.70#ibcon#about to read 4, iclass 31, count 0 2006.190.07:56:09.70#ibcon#read 4, iclass 31, count 0 2006.190.07:56:09.71#ibcon#about to read 5, iclass 31, count 0 2006.190.07:56:09.71#ibcon#read 5, iclass 31, count 0 2006.190.07:56:09.71#ibcon#about to read 6, iclass 31, count 0 2006.190.07:56:09.71#ibcon#read 6, iclass 31, count 0 2006.190.07:56:09.71#ibcon#end of sib2, iclass 31, count 0 2006.190.07:56:09.71#ibcon#*after write, iclass 31, count 0 2006.190.07:56:09.71#ibcon#*before return 0, iclass 31, count 0 2006.190.07:56:09.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:09.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:09.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:56:09.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:56:09.71$vc4f8/va=6,6 2006.190.07:56:09.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.190.07:56:09.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.190.07:56:09.71#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:09.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:56:09.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:56:09.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:56:09.76#ibcon#enter wrdev, iclass 33, count 2 2006.190.07:56:09.76#ibcon#first serial, iclass 33, count 2 2006.190.07:56:09.77#ibcon#enter sib2, iclass 33, count 2 2006.190.07:56:09.77#ibcon#flushed, iclass 33, count 2 2006.190.07:56:09.77#ibcon#about to write, iclass 33, count 2 2006.190.07:56:09.77#ibcon#wrote, iclass 33, count 2 2006.190.07:56:09.77#ibcon#about to read 3, iclass 33, count 2 2006.190.07:56:09.78#ibcon#read 3, iclass 33, count 2 2006.190.07:56:09.78#ibcon#about to read 4, iclass 33, count 2 2006.190.07:56:09.79#ibcon#read 4, iclass 33, count 2 2006.190.07:56:09.79#ibcon#about to read 5, iclass 33, count 2 2006.190.07:56:09.79#ibcon#read 5, iclass 33, count 2 2006.190.07:56:09.79#ibcon#about to read 6, iclass 33, count 2 2006.190.07:56:09.79#ibcon#read 6, iclass 33, count 2 2006.190.07:56:09.79#ibcon#end of sib2, iclass 33, count 2 2006.190.07:56:09.79#ibcon#*mode == 0, iclass 33, count 2 2006.190.07:56:09.79#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.190.07:56:09.79#ibcon#[25=AT06-06\r\n] 2006.190.07:56:09.79#ibcon#*before write, iclass 33, count 2 2006.190.07:56:09.79#ibcon#enter sib2, iclass 33, count 2 2006.190.07:56:09.79#ibcon#flushed, iclass 33, count 2 2006.190.07:56:09.79#ibcon#about to write, iclass 33, count 2 2006.190.07:56:09.79#ibcon#wrote, iclass 33, count 2 2006.190.07:56:09.79#ibcon#about to read 3, iclass 33, count 2 2006.190.07:56:09.81#ibcon#read 3, iclass 33, count 2 2006.190.07:56:09.81#ibcon#about to read 4, iclass 33, count 2 2006.190.07:56:09.82#ibcon#read 4, iclass 33, count 2 2006.190.07:56:09.82#ibcon#about to read 5, iclass 33, count 2 2006.190.07:56:09.82#ibcon#read 5, iclass 33, count 2 2006.190.07:56:09.82#ibcon#about to read 6, iclass 33, count 2 2006.190.07:56:09.82#ibcon#read 6, iclass 33, count 2 2006.190.07:56:09.82#ibcon#end of sib2, iclass 33, count 2 2006.190.07:56:09.82#ibcon#*after write, iclass 33, count 2 2006.190.07:56:09.82#ibcon#*before return 0, iclass 33, count 2 2006.190.07:56:09.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:56:09.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.190.07:56:09.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.190.07:56:09.82#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:09.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:56:09.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:56:09.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:56:09.93#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:56:09.93#ibcon#first serial, iclass 33, count 0 2006.190.07:56:09.94#ibcon#enter sib2, iclass 33, count 0 2006.190.07:56:09.94#ibcon#flushed, iclass 33, count 0 2006.190.07:56:09.94#ibcon#about to write, iclass 33, count 0 2006.190.07:56:09.94#ibcon#wrote, iclass 33, count 0 2006.190.07:56:09.94#ibcon#about to read 3, iclass 33, count 0 2006.190.07:56:09.95#ibcon#read 3, iclass 33, count 0 2006.190.07:56:09.95#ibcon#about to read 4, iclass 33, count 0 2006.190.07:56:09.96#ibcon#read 4, iclass 33, count 0 2006.190.07:56:09.96#ibcon#about to read 5, iclass 33, count 0 2006.190.07:56:09.96#ibcon#read 5, iclass 33, count 0 2006.190.07:56:09.96#ibcon#about to read 6, iclass 33, count 0 2006.190.07:56:09.96#ibcon#read 6, iclass 33, count 0 2006.190.07:56:09.96#ibcon#end of sib2, iclass 33, count 0 2006.190.07:56:09.96#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:56:09.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:56:09.96#ibcon#[25=USB\r\n] 2006.190.07:56:09.96#ibcon#*before write, iclass 33, count 0 2006.190.07:56:09.96#ibcon#enter sib2, iclass 33, count 0 2006.190.07:56:09.96#ibcon#flushed, iclass 33, count 0 2006.190.07:56:09.96#ibcon#about to write, iclass 33, count 0 2006.190.07:56:09.96#ibcon#wrote, iclass 33, count 0 2006.190.07:56:09.96#ibcon#about to read 3, iclass 33, count 0 2006.190.07:56:09.98#ibcon#read 3, iclass 33, count 0 2006.190.07:56:09.98#ibcon#about to read 4, iclass 33, count 0 2006.190.07:56:09.99#ibcon#read 4, iclass 33, count 0 2006.190.07:56:09.99#ibcon#about to read 5, iclass 33, count 0 2006.190.07:56:09.99#ibcon#read 5, iclass 33, count 0 2006.190.07:56:09.99#ibcon#about to read 6, iclass 33, count 0 2006.190.07:56:09.99#ibcon#read 6, iclass 33, count 0 2006.190.07:56:09.99#ibcon#end of sib2, iclass 33, count 0 2006.190.07:56:09.99#ibcon#*after write, iclass 33, count 0 2006.190.07:56:09.99#ibcon#*before return 0, iclass 33, count 0 2006.190.07:56:09.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:56:09.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.190.07:56:09.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:56:09.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:56:09.99$vc4f8/valo=7,832.99 2006.190.07:56:09.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.07:56:09.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.07:56:09.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:09.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:56:09.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:56:09.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:56:09.99#ibcon#enter wrdev, iclass 35, count 0 2006.190.07:56:09.99#ibcon#first serial, iclass 35, count 0 2006.190.07:56:09.99#ibcon#enter sib2, iclass 35, count 0 2006.190.07:56:09.99#ibcon#flushed, iclass 35, count 0 2006.190.07:56:09.99#ibcon#about to write, iclass 35, count 0 2006.190.07:56:09.99#ibcon#wrote, iclass 35, count 0 2006.190.07:56:09.99#ibcon#about to read 3, iclass 35, count 0 2006.190.07:56:10.00#ibcon#read 3, iclass 35, count 0 2006.190.07:56:10.00#ibcon#about to read 4, iclass 35, count 0 2006.190.07:56:10.00#ibcon#read 4, iclass 35, count 0 2006.190.07:56:10.01#ibcon#about to read 5, iclass 35, count 0 2006.190.07:56:10.01#ibcon#read 5, iclass 35, count 0 2006.190.07:56:10.01#ibcon#about to read 6, iclass 35, count 0 2006.190.07:56:10.01#ibcon#read 6, iclass 35, count 0 2006.190.07:56:10.01#ibcon#end of sib2, iclass 35, count 0 2006.190.07:56:10.01#ibcon#*mode == 0, iclass 35, count 0 2006.190.07:56:10.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.07:56:10.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:56:10.01#ibcon#*before write, iclass 35, count 0 2006.190.07:56:10.01#ibcon#enter sib2, iclass 35, count 0 2006.190.07:56:10.01#ibcon#flushed, iclass 35, count 0 2006.190.07:56:10.01#ibcon#about to write, iclass 35, count 0 2006.190.07:56:10.01#ibcon#wrote, iclass 35, count 0 2006.190.07:56:10.01#ibcon#about to read 3, iclass 35, count 0 2006.190.07:56:10.04#ibcon#read 3, iclass 35, count 0 2006.190.07:56:10.04#ibcon#about to read 4, iclass 35, count 0 2006.190.07:56:10.04#ibcon#read 4, iclass 35, count 0 2006.190.07:56:10.05#ibcon#about to read 5, iclass 35, count 0 2006.190.07:56:10.05#ibcon#read 5, iclass 35, count 0 2006.190.07:56:10.05#ibcon#about to read 6, iclass 35, count 0 2006.190.07:56:10.05#ibcon#read 6, iclass 35, count 0 2006.190.07:56:10.05#ibcon#end of sib2, iclass 35, count 0 2006.190.07:56:10.05#ibcon#*after write, iclass 35, count 0 2006.190.07:56:10.05#ibcon#*before return 0, iclass 35, count 0 2006.190.07:56:10.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:56:10.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.07:56:10.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.07:56:10.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.07:56:10.05$vc4f8/va=7,6 2006.190.07:56:10.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.07:56:10.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.07:56:10.05#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:10.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:56:10.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:56:10.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:56:10.10#ibcon#enter wrdev, iclass 37, count 2 2006.190.07:56:10.11#ibcon#first serial, iclass 37, count 2 2006.190.07:56:10.11#ibcon#enter sib2, iclass 37, count 2 2006.190.07:56:10.11#ibcon#flushed, iclass 37, count 2 2006.190.07:56:10.11#ibcon#about to write, iclass 37, count 2 2006.190.07:56:10.11#ibcon#wrote, iclass 37, count 2 2006.190.07:56:10.11#ibcon#about to read 3, iclass 37, count 2 2006.190.07:56:10.12#ibcon#read 3, iclass 37, count 2 2006.190.07:56:10.12#ibcon#about to read 4, iclass 37, count 2 2006.190.07:56:10.12#ibcon#read 4, iclass 37, count 2 2006.190.07:56:10.13#ibcon#about to read 5, iclass 37, count 2 2006.190.07:56:10.13#ibcon#read 5, iclass 37, count 2 2006.190.07:56:10.13#ibcon#about to read 6, iclass 37, count 2 2006.190.07:56:10.13#ibcon#read 6, iclass 37, count 2 2006.190.07:56:10.13#ibcon#end of sib2, iclass 37, count 2 2006.190.07:56:10.13#ibcon#*mode == 0, iclass 37, count 2 2006.190.07:56:10.13#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.07:56:10.13#ibcon#[25=AT07-06\r\n] 2006.190.07:56:10.13#ibcon#*before write, iclass 37, count 2 2006.190.07:56:10.13#ibcon#enter sib2, iclass 37, count 2 2006.190.07:56:10.13#ibcon#flushed, iclass 37, count 2 2006.190.07:56:10.13#ibcon#about to write, iclass 37, count 2 2006.190.07:56:10.13#ibcon#wrote, iclass 37, count 2 2006.190.07:56:10.13#ibcon#about to read 3, iclass 37, count 2 2006.190.07:56:10.15#ibcon#read 3, iclass 37, count 2 2006.190.07:56:10.15#ibcon#about to read 4, iclass 37, count 2 2006.190.07:56:10.15#ibcon#read 4, iclass 37, count 2 2006.190.07:56:10.16#ibcon#about to read 5, iclass 37, count 2 2006.190.07:56:10.16#ibcon#read 5, iclass 37, count 2 2006.190.07:56:10.16#ibcon#about to read 6, iclass 37, count 2 2006.190.07:56:10.16#ibcon#read 6, iclass 37, count 2 2006.190.07:56:10.16#ibcon#end of sib2, iclass 37, count 2 2006.190.07:56:10.16#ibcon#*after write, iclass 37, count 2 2006.190.07:56:10.16#ibcon#*before return 0, iclass 37, count 2 2006.190.07:56:10.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:56:10.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.07:56:10.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.07:56:10.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:10.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:56:10.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:56:10.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:56:10.27#ibcon#enter wrdev, iclass 37, count 0 2006.190.07:56:10.27#ibcon#first serial, iclass 37, count 0 2006.190.07:56:10.28#ibcon#enter sib2, iclass 37, count 0 2006.190.07:56:10.28#ibcon#flushed, iclass 37, count 0 2006.190.07:56:10.28#ibcon#about to write, iclass 37, count 0 2006.190.07:56:10.28#ibcon#wrote, iclass 37, count 0 2006.190.07:56:10.28#ibcon#about to read 3, iclass 37, count 0 2006.190.07:56:10.29#ibcon#read 3, iclass 37, count 0 2006.190.07:56:10.29#ibcon#about to read 4, iclass 37, count 0 2006.190.07:56:10.30#ibcon#read 4, iclass 37, count 0 2006.190.07:56:10.30#ibcon#about to read 5, iclass 37, count 0 2006.190.07:56:10.30#ibcon#read 5, iclass 37, count 0 2006.190.07:56:10.30#ibcon#about to read 6, iclass 37, count 0 2006.190.07:56:10.30#ibcon#read 6, iclass 37, count 0 2006.190.07:56:10.30#ibcon#end of sib2, iclass 37, count 0 2006.190.07:56:10.30#ibcon#*mode == 0, iclass 37, count 0 2006.190.07:56:10.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.07:56:10.30#ibcon#[25=USB\r\n] 2006.190.07:56:10.30#ibcon#*before write, iclass 37, count 0 2006.190.07:56:10.30#ibcon#enter sib2, iclass 37, count 0 2006.190.07:56:10.30#ibcon#flushed, iclass 37, count 0 2006.190.07:56:10.30#ibcon#about to write, iclass 37, count 0 2006.190.07:56:10.30#ibcon#wrote, iclass 37, count 0 2006.190.07:56:10.30#ibcon#about to read 3, iclass 37, count 0 2006.190.07:56:10.32#ibcon#read 3, iclass 37, count 0 2006.190.07:56:10.32#ibcon#about to read 4, iclass 37, count 0 2006.190.07:56:10.33#ibcon#read 4, iclass 37, count 0 2006.190.07:56:10.33#ibcon#about to read 5, iclass 37, count 0 2006.190.07:56:10.33#ibcon#read 5, iclass 37, count 0 2006.190.07:56:10.33#ibcon#about to read 6, iclass 37, count 0 2006.190.07:56:10.33#ibcon#read 6, iclass 37, count 0 2006.190.07:56:10.33#ibcon#end of sib2, iclass 37, count 0 2006.190.07:56:10.33#ibcon#*after write, iclass 37, count 0 2006.190.07:56:10.33#ibcon#*before return 0, iclass 37, count 0 2006.190.07:56:10.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:56:10.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.07:56:10.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.07:56:10.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.07:56:10.33$vc4f8/valo=8,852.99 2006.190.07:56:10.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.07:56:10.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.07:56:10.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:10.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:56:10.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:56:10.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:56:10.33#ibcon#enter wrdev, iclass 39, count 0 2006.190.07:56:10.33#ibcon#first serial, iclass 39, count 0 2006.190.07:56:10.33#ibcon#enter sib2, iclass 39, count 0 2006.190.07:56:10.33#ibcon#flushed, iclass 39, count 0 2006.190.07:56:10.33#ibcon#about to write, iclass 39, count 0 2006.190.07:56:10.33#ibcon#wrote, iclass 39, count 0 2006.190.07:56:10.33#ibcon#about to read 3, iclass 39, count 0 2006.190.07:56:10.34#ibcon#read 3, iclass 39, count 0 2006.190.07:56:10.34#ibcon#about to read 4, iclass 39, count 0 2006.190.07:56:10.35#ibcon#read 4, iclass 39, count 0 2006.190.07:56:10.35#ibcon#about to read 5, iclass 39, count 0 2006.190.07:56:10.35#ibcon#read 5, iclass 39, count 0 2006.190.07:56:10.35#ibcon#about to read 6, iclass 39, count 0 2006.190.07:56:10.35#ibcon#read 6, iclass 39, count 0 2006.190.07:56:10.35#ibcon#end of sib2, iclass 39, count 0 2006.190.07:56:10.35#ibcon#*mode == 0, iclass 39, count 0 2006.190.07:56:10.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.07:56:10.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:56:10.35#ibcon#*before write, iclass 39, count 0 2006.190.07:56:10.35#ibcon#enter sib2, iclass 39, count 0 2006.190.07:56:10.35#ibcon#flushed, iclass 39, count 0 2006.190.07:56:10.35#ibcon#about to write, iclass 39, count 0 2006.190.07:56:10.35#ibcon#wrote, iclass 39, count 0 2006.190.07:56:10.35#ibcon#about to read 3, iclass 39, count 0 2006.190.07:56:10.39#ibcon#read 3, iclass 39, count 0 2006.190.07:56:10.39#ibcon#about to read 4, iclass 39, count 0 2006.190.07:56:10.39#ibcon#read 4, iclass 39, count 0 2006.190.07:56:10.39#ibcon#about to read 5, iclass 39, count 0 2006.190.07:56:10.39#ibcon#read 5, iclass 39, count 0 2006.190.07:56:10.39#ibcon#about to read 6, iclass 39, count 0 2006.190.07:56:10.39#ibcon#read 6, iclass 39, count 0 2006.190.07:56:10.39#ibcon#end of sib2, iclass 39, count 0 2006.190.07:56:10.39#ibcon#*after write, iclass 39, count 0 2006.190.07:56:10.39#ibcon#*before return 0, iclass 39, count 0 2006.190.07:56:10.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:56:10.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.07:56:10.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.07:56:10.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.07:56:10.39$vc4f8/va=8,6 2006.190.07:56:10.39#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.07:56:10.39#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.07:56:10.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:10.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:56:10.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:56:10.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:56:10.44#ibcon#enter wrdev, iclass 3, count 2 2006.190.07:56:10.44#ibcon#first serial, iclass 3, count 2 2006.190.07:56:10.45#ibcon#enter sib2, iclass 3, count 2 2006.190.07:56:10.45#ibcon#flushed, iclass 3, count 2 2006.190.07:56:10.45#ibcon#about to write, iclass 3, count 2 2006.190.07:56:10.45#ibcon#wrote, iclass 3, count 2 2006.190.07:56:10.45#ibcon#about to read 3, iclass 3, count 2 2006.190.07:56:10.46#ibcon#read 3, iclass 3, count 2 2006.190.07:56:10.46#ibcon#about to read 4, iclass 3, count 2 2006.190.07:56:10.47#ibcon#read 4, iclass 3, count 2 2006.190.07:56:10.47#ibcon#about to read 5, iclass 3, count 2 2006.190.07:56:10.47#ibcon#read 5, iclass 3, count 2 2006.190.07:56:10.47#ibcon#about to read 6, iclass 3, count 2 2006.190.07:56:10.47#ibcon#read 6, iclass 3, count 2 2006.190.07:56:10.47#ibcon#end of sib2, iclass 3, count 2 2006.190.07:56:10.47#ibcon#*mode == 0, iclass 3, count 2 2006.190.07:56:10.47#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.07:56:10.47#ibcon#[25=AT08-06\r\n] 2006.190.07:56:10.47#ibcon#*before write, iclass 3, count 2 2006.190.07:56:10.47#ibcon#enter sib2, iclass 3, count 2 2006.190.07:56:10.47#ibcon#flushed, iclass 3, count 2 2006.190.07:56:10.47#ibcon#about to write, iclass 3, count 2 2006.190.07:56:10.47#ibcon#wrote, iclass 3, count 2 2006.190.07:56:10.47#ibcon#about to read 3, iclass 3, count 2 2006.190.07:56:10.49#ibcon#read 3, iclass 3, count 2 2006.190.07:56:10.49#ibcon#about to read 4, iclass 3, count 2 2006.190.07:56:10.49#ibcon#read 4, iclass 3, count 2 2006.190.07:56:10.50#ibcon#about to read 5, iclass 3, count 2 2006.190.07:56:10.50#ibcon#read 5, iclass 3, count 2 2006.190.07:56:10.50#ibcon#about to read 6, iclass 3, count 2 2006.190.07:56:10.50#ibcon#read 6, iclass 3, count 2 2006.190.07:56:10.50#ibcon#end of sib2, iclass 3, count 2 2006.190.07:56:10.50#ibcon#*after write, iclass 3, count 2 2006.190.07:56:10.50#ibcon#*before return 0, iclass 3, count 2 2006.190.07:56:10.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:56:10.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.07:56:10.50#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.07:56:10.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:10.50#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:56:10.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:56:10.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:56:10.61#ibcon#enter wrdev, iclass 3, count 0 2006.190.07:56:10.61#ibcon#first serial, iclass 3, count 0 2006.190.07:56:10.62#ibcon#enter sib2, iclass 3, count 0 2006.190.07:56:10.62#ibcon#flushed, iclass 3, count 0 2006.190.07:56:10.62#ibcon#about to write, iclass 3, count 0 2006.190.07:56:10.62#ibcon#wrote, iclass 3, count 0 2006.190.07:56:10.62#ibcon#about to read 3, iclass 3, count 0 2006.190.07:56:10.63#ibcon#read 3, iclass 3, count 0 2006.190.07:56:10.63#ibcon#about to read 4, iclass 3, count 0 2006.190.07:56:10.64#ibcon#read 4, iclass 3, count 0 2006.190.07:56:10.64#ibcon#about to read 5, iclass 3, count 0 2006.190.07:56:10.64#ibcon#read 5, iclass 3, count 0 2006.190.07:56:10.64#ibcon#about to read 6, iclass 3, count 0 2006.190.07:56:10.64#ibcon#read 6, iclass 3, count 0 2006.190.07:56:10.64#ibcon#end of sib2, iclass 3, count 0 2006.190.07:56:10.64#ibcon#*mode == 0, iclass 3, count 0 2006.190.07:56:10.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.07:56:10.64#ibcon#[25=USB\r\n] 2006.190.07:56:10.64#ibcon#*before write, iclass 3, count 0 2006.190.07:56:10.64#ibcon#enter sib2, iclass 3, count 0 2006.190.07:56:10.64#ibcon#flushed, iclass 3, count 0 2006.190.07:56:10.64#ibcon#about to write, iclass 3, count 0 2006.190.07:56:10.64#ibcon#wrote, iclass 3, count 0 2006.190.07:56:10.64#ibcon#about to read 3, iclass 3, count 0 2006.190.07:56:10.66#ibcon#read 3, iclass 3, count 0 2006.190.07:56:10.66#ibcon#about to read 4, iclass 3, count 0 2006.190.07:56:10.66#ibcon#read 4, iclass 3, count 0 2006.190.07:56:10.67#ibcon#about to read 5, iclass 3, count 0 2006.190.07:56:10.67#ibcon#read 5, iclass 3, count 0 2006.190.07:56:10.67#ibcon#about to read 6, iclass 3, count 0 2006.190.07:56:10.67#ibcon#read 6, iclass 3, count 0 2006.190.07:56:10.67#ibcon#end of sib2, iclass 3, count 0 2006.190.07:56:10.67#ibcon#*after write, iclass 3, count 0 2006.190.07:56:10.67#ibcon#*before return 0, iclass 3, count 0 2006.190.07:56:10.67#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:56:10.67#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.07:56:10.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.07:56:10.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.07:56:10.67$vc4f8/vblo=1,632.99 2006.190.07:56:10.67#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.07:56:10.67#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.07:56:10.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:10.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:56:10.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:56:10.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:56:10.67#ibcon#enter wrdev, iclass 5, count 0 2006.190.07:56:10.67#ibcon#first serial, iclass 5, count 0 2006.190.07:56:10.67#ibcon#enter sib2, iclass 5, count 0 2006.190.07:56:10.67#ibcon#flushed, iclass 5, count 0 2006.190.07:56:10.67#ibcon#about to write, iclass 5, count 0 2006.190.07:56:10.67#ibcon#wrote, iclass 5, count 0 2006.190.07:56:10.67#ibcon#about to read 3, iclass 5, count 0 2006.190.07:56:10.68#ibcon#read 3, iclass 5, count 0 2006.190.07:56:10.68#ibcon#about to read 4, iclass 5, count 0 2006.190.07:56:10.68#ibcon#read 4, iclass 5, count 0 2006.190.07:56:10.69#ibcon#about to read 5, iclass 5, count 0 2006.190.07:56:10.69#ibcon#read 5, iclass 5, count 0 2006.190.07:56:10.69#ibcon#about to read 6, iclass 5, count 0 2006.190.07:56:10.69#ibcon#read 6, iclass 5, count 0 2006.190.07:56:10.69#ibcon#end of sib2, iclass 5, count 0 2006.190.07:56:10.69#ibcon#*mode == 0, iclass 5, count 0 2006.190.07:56:10.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.07:56:10.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:56:10.69#ibcon#*before write, iclass 5, count 0 2006.190.07:56:10.69#ibcon#enter sib2, iclass 5, count 0 2006.190.07:56:10.69#ibcon#flushed, iclass 5, count 0 2006.190.07:56:10.69#ibcon#about to write, iclass 5, count 0 2006.190.07:56:10.69#ibcon#wrote, iclass 5, count 0 2006.190.07:56:10.69#ibcon#about to read 3, iclass 5, count 0 2006.190.07:56:10.72#ibcon#read 3, iclass 5, count 0 2006.190.07:56:10.72#ibcon#about to read 4, iclass 5, count 0 2006.190.07:56:10.72#ibcon#read 4, iclass 5, count 0 2006.190.07:56:10.73#ibcon#about to read 5, iclass 5, count 0 2006.190.07:56:10.73#ibcon#read 5, iclass 5, count 0 2006.190.07:56:10.73#ibcon#about to read 6, iclass 5, count 0 2006.190.07:56:10.73#ibcon#read 6, iclass 5, count 0 2006.190.07:56:10.73#ibcon#end of sib2, iclass 5, count 0 2006.190.07:56:10.73#ibcon#*after write, iclass 5, count 0 2006.190.07:56:10.73#ibcon#*before return 0, iclass 5, count 0 2006.190.07:56:10.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:56:10.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.07:56:10.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.07:56:10.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.07:56:10.73$vc4f8/vb=1,4 2006.190.07:56:10.73#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.07:56:10.73#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.07:56:10.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:10.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:56:10.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:56:10.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:56:10.73#ibcon#enter wrdev, iclass 7, count 2 2006.190.07:56:10.73#ibcon#first serial, iclass 7, count 2 2006.190.07:56:10.73#ibcon#enter sib2, iclass 7, count 2 2006.190.07:56:10.73#ibcon#flushed, iclass 7, count 2 2006.190.07:56:10.73#ibcon#about to write, iclass 7, count 2 2006.190.07:56:10.73#ibcon#wrote, iclass 7, count 2 2006.190.07:56:10.73#ibcon#about to read 3, iclass 7, count 2 2006.190.07:56:10.74#ibcon#read 3, iclass 7, count 2 2006.190.07:56:10.74#ibcon#about to read 4, iclass 7, count 2 2006.190.07:56:10.75#ibcon#read 4, iclass 7, count 2 2006.190.07:56:10.75#ibcon#about to read 5, iclass 7, count 2 2006.190.07:56:10.75#ibcon#read 5, iclass 7, count 2 2006.190.07:56:10.75#ibcon#about to read 6, iclass 7, count 2 2006.190.07:56:10.75#ibcon#read 6, iclass 7, count 2 2006.190.07:56:10.75#ibcon#end of sib2, iclass 7, count 2 2006.190.07:56:10.75#ibcon#*mode == 0, iclass 7, count 2 2006.190.07:56:10.75#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.07:56:10.75#ibcon#[27=AT01-04\r\n] 2006.190.07:56:10.75#ibcon#*before write, iclass 7, count 2 2006.190.07:56:10.75#ibcon#enter sib2, iclass 7, count 2 2006.190.07:56:10.75#ibcon#flushed, iclass 7, count 2 2006.190.07:56:10.75#ibcon#about to write, iclass 7, count 2 2006.190.07:56:10.75#ibcon#wrote, iclass 7, count 2 2006.190.07:56:10.75#ibcon#about to read 3, iclass 7, count 2 2006.190.07:56:10.77#ibcon#read 3, iclass 7, count 2 2006.190.07:56:10.77#ibcon#about to read 4, iclass 7, count 2 2006.190.07:56:10.77#ibcon#read 4, iclass 7, count 2 2006.190.07:56:10.78#ibcon#about to read 5, iclass 7, count 2 2006.190.07:56:10.78#ibcon#read 5, iclass 7, count 2 2006.190.07:56:10.78#ibcon#about to read 6, iclass 7, count 2 2006.190.07:56:10.78#ibcon#read 6, iclass 7, count 2 2006.190.07:56:10.78#ibcon#end of sib2, iclass 7, count 2 2006.190.07:56:10.78#ibcon#*after write, iclass 7, count 2 2006.190.07:56:10.78#ibcon#*before return 0, iclass 7, count 2 2006.190.07:56:10.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:56:10.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.07:56:10.78#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.07:56:10.78#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:10.78#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:56:10.89#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:56:10.89#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:56:10.89#ibcon#enter wrdev, iclass 7, count 0 2006.190.07:56:10.89#ibcon#first serial, iclass 7, count 0 2006.190.07:56:10.89#ibcon#enter sib2, iclass 7, count 0 2006.190.07:56:10.90#ibcon#flushed, iclass 7, count 0 2006.190.07:56:10.90#ibcon#about to write, iclass 7, count 0 2006.190.07:56:10.90#ibcon#wrote, iclass 7, count 0 2006.190.07:56:10.90#ibcon#about to read 3, iclass 7, count 0 2006.190.07:56:10.91#ibcon#read 3, iclass 7, count 0 2006.190.07:56:10.91#ibcon#about to read 4, iclass 7, count 0 2006.190.07:56:10.91#ibcon#read 4, iclass 7, count 0 2006.190.07:56:10.92#ibcon#about to read 5, iclass 7, count 0 2006.190.07:56:10.92#ibcon#read 5, iclass 7, count 0 2006.190.07:56:10.92#ibcon#about to read 6, iclass 7, count 0 2006.190.07:56:10.92#ibcon#read 6, iclass 7, count 0 2006.190.07:56:10.92#ibcon#end of sib2, iclass 7, count 0 2006.190.07:56:10.92#ibcon#*mode == 0, iclass 7, count 0 2006.190.07:56:10.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.07:56:10.92#ibcon#[27=USB\r\n] 2006.190.07:56:10.92#ibcon#*before write, iclass 7, count 0 2006.190.07:56:10.92#ibcon#enter sib2, iclass 7, count 0 2006.190.07:56:10.92#ibcon#flushed, iclass 7, count 0 2006.190.07:56:10.92#ibcon#about to write, iclass 7, count 0 2006.190.07:56:10.92#ibcon#wrote, iclass 7, count 0 2006.190.07:56:10.92#ibcon#about to read 3, iclass 7, count 0 2006.190.07:56:10.94#ibcon#read 3, iclass 7, count 0 2006.190.07:56:10.95#ibcon#about to read 4, iclass 7, count 0 2006.190.07:56:10.95#ibcon#read 4, iclass 7, count 0 2006.190.07:56:10.95#ibcon#about to read 5, iclass 7, count 0 2006.190.07:56:10.95#ibcon#read 5, iclass 7, count 0 2006.190.07:56:10.95#ibcon#about to read 6, iclass 7, count 0 2006.190.07:56:10.95#ibcon#read 6, iclass 7, count 0 2006.190.07:56:10.95#ibcon#end of sib2, iclass 7, count 0 2006.190.07:56:10.95#ibcon#*after write, iclass 7, count 0 2006.190.07:56:10.95#ibcon#*before return 0, iclass 7, count 0 2006.190.07:56:10.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:56:10.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.07:56:10.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.07:56:10.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.07:56:10.95$vc4f8/vblo=2,640.99 2006.190.07:56:10.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.07:56:10.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.07:56:10.95#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:10.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:10.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:10.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:10.95#ibcon#enter wrdev, iclass 11, count 0 2006.190.07:56:10.95#ibcon#first serial, iclass 11, count 0 2006.190.07:56:10.95#ibcon#enter sib2, iclass 11, count 0 2006.190.07:56:10.95#ibcon#flushed, iclass 11, count 0 2006.190.07:56:10.95#ibcon#about to write, iclass 11, count 0 2006.190.07:56:10.95#ibcon#wrote, iclass 11, count 0 2006.190.07:56:10.95#ibcon#about to read 3, iclass 11, count 0 2006.190.07:56:10.96#ibcon#read 3, iclass 11, count 0 2006.190.07:56:10.96#ibcon#about to read 4, iclass 11, count 0 2006.190.07:56:10.97#ibcon#read 4, iclass 11, count 0 2006.190.07:56:10.97#ibcon#about to read 5, iclass 11, count 0 2006.190.07:56:10.97#ibcon#read 5, iclass 11, count 0 2006.190.07:56:10.97#ibcon#about to read 6, iclass 11, count 0 2006.190.07:56:10.97#ibcon#read 6, iclass 11, count 0 2006.190.07:56:10.97#ibcon#end of sib2, iclass 11, count 0 2006.190.07:56:10.97#ibcon#*mode == 0, iclass 11, count 0 2006.190.07:56:10.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.07:56:10.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:56:10.97#ibcon#*before write, iclass 11, count 0 2006.190.07:56:10.97#ibcon#enter sib2, iclass 11, count 0 2006.190.07:56:10.97#ibcon#flushed, iclass 11, count 0 2006.190.07:56:10.97#ibcon#about to write, iclass 11, count 0 2006.190.07:56:10.97#ibcon#wrote, iclass 11, count 0 2006.190.07:56:10.97#ibcon#about to read 3, iclass 11, count 0 2006.190.07:56:11.00#ibcon#read 3, iclass 11, count 0 2006.190.07:56:11.00#ibcon#about to read 4, iclass 11, count 0 2006.190.07:56:11.00#ibcon#read 4, iclass 11, count 0 2006.190.07:56:11.01#ibcon#about to read 5, iclass 11, count 0 2006.190.07:56:11.01#ibcon#read 5, iclass 11, count 0 2006.190.07:56:11.01#ibcon#about to read 6, iclass 11, count 0 2006.190.07:56:11.01#ibcon#read 6, iclass 11, count 0 2006.190.07:56:11.01#ibcon#end of sib2, iclass 11, count 0 2006.190.07:56:11.01#ibcon#*after write, iclass 11, count 0 2006.190.07:56:11.01#ibcon#*before return 0, iclass 11, count 0 2006.190.07:56:11.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:11.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.07:56:11.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.07:56:11.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.07:56:11.01$vc4f8/vb=2,4 2006.190.07:56:11.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.07:56:11.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.07:56:11.01#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:11.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:11.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:11.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:11.06#ibcon#enter wrdev, iclass 13, count 2 2006.190.07:56:11.06#ibcon#first serial, iclass 13, count 2 2006.190.07:56:11.07#ibcon#enter sib2, iclass 13, count 2 2006.190.07:56:11.07#ibcon#flushed, iclass 13, count 2 2006.190.07:56:11.07#ibcon#about to write, iclass 13, count 2 2006.190.07:56:11.07#ibcon#wrote, iclass 13, count 2 2006.190.07:56:11.07#ibcon#about to read 3, iclass 13, count 2 2006.190.07:56:11.08#ibcon#read 3, iclass 13, count 2 2006.190.07:56:11.08#ibcon#about to read 4, iclass 13, count 2 2006.190.07:56:11.08#ibcon#read 4, iclass 13, count 2 2006.190.07:56:11.09#ibcon#about to read 5, iclass 13, count 2 2006.190.07:56:11.09#ibcon#read 5, iclass 13, count 2 2006.190.07:56:11.09#ibcon#about to read 6, iclass 13, count 2 2006.190.07:56:11.09#ibcon#read 6, iclass 13, count 2 2006.190.07:56:11.09#ibcon#end of sib2, iclass 13, count 2 2006.190.07:56:11.09#ibcon#*mode == 0, iclass 13, count 2 2006.190.07:56:11.09#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.07:56:11.09#ibcon#[27=AT02-04\r\n] 2006.190.07:56:11.09#ibcon#*before write, iclass 13, count 2 2006.190.07:56:11.09#ibcon#enter sib2, iclass 13, count 2 2006.190.07:56:11.09#ibcon#flushed, iclass 13, count 2 2006.190.07:56:11.09#ibcon#about to write, iclass 13, count 2 2006.190.07:56:11.09#ibcon#wrote, iclass 13, count 2 2006.190.07:56:11.09#ibcon#about to read 3, iclass 13, count 2 2006.190.07:56:11.12#ibcon#read 3, iclass 13, count 2 2006.190.07:56:11.12#ibcon#about to read 4, iclass 13, count 2 2006.190.07:56:11.12#ibcon#read 4, iclass 13, count 2 2006.190.07:56:11.12#ibcon#about to read 5, iclass 13, count 2 2006.190.07:56:11.12#ibcon#read 5, iclass 13, count 2 2006.190.07:56:11.12#ibcon#about to read 6, iclass 13, count 2 2006.190.07:56:11.12#ibcon#read 6, iclass 13, count 2 2006.190.07:56:11.12#ibcon#end of sib2, iclass 13, count 2 2006.190.07:56:11.12#ibcon#*after write, iclass 13, count 2 2006.190.07:56:11.12#ibcon#*before return 0, iclass 13, count 2 2006.190.07:56:11.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:11.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.07:56:11.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.07:56:11.12#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:11.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:11.23#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:11.23#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:11.23#ibcon#enter wrdev, iclass 13, count 0 2006.190.07:56:11.23#ibcon#first serial, iclass 13, count 0 2006.190.07:56:11.24#ibcon#enter sib2, iclass 13, count 0 2006.190.07:56:11.24#ibcon#flushed, iclass 13, count 0 2006.190.07:56:11.24#ibcon#about to write, iclass 13, count 0 2006.190.07:56:11.24#ibcon#wrote, iclass 13, count 0 2006.190.07:56:11.24#ibcon#about to read 3, iclass 13, count 0 2006.190.07:56:11.25#ibcon#read 3, iclass 13, count 0 2006.190.07:56:11.25#ibcon#about to read 4, iclass 13, count 0 2006.190.07:56:11.25#ibcon#read 4, iclass 13, count 0 2006.190.07:56:11.26#ibcon#about to read 5, iclass 13, count 0 2006.190.07:56:11.26#ibcon#read 5, iclass 13, count 0 2006.190.07:56:11.26#ibcon#about to read 6, iclass 13, count 0 2006.190.07:56:11.26#ibcon#read 6, iclass 13, count 0 2006.190.07:56:11.26#ibcon#end of sib2, iclass 13, count 0 2006.190.07:56:11.26#ibcon#*mode == 0, iclass 13, count 0 2006.190.07:56:11.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.07:56:11.26#ibcon#[27=USB\r\n] 2006.190.07:56:11.26#ibcon#*before write, iclass 13, count 0 2006.190.07:56:11.26#ibcon#enter sib2, iclass 13, count 0 2006.190.07:56:11.26#ibcon#flushed, iclass 13, count 0 2006.190.07:56:11.26#ibcon#about to write, iclass 13, count 0 2006.190.07:56:11.26#ibcon#wrote, iclass 13, count 0 2006.190.07:56:11.26#ibcon#about to read 3, iclass 13, count 0 2006.190.07:56:11.28#ibcon#read 3, iclass 13, count 0 2006.190.07:56:11.28#ibcon#about to read 4, iclass 13, count 0 2006.190.07:56:11.28#ibcon#read 4, iclass 13, count 0 2006.190.07:56:11.29#ibcon#about to read 5, iclass 13, count 0 2006.190.07:56:11.29#ibcon#read 5, iclass 13, count 0 2006.190.07:56:11.29#ibcon#about to read 6, iclass 13, count 0 2006.190.07:56:11.29#ibcon#read 6, iclass 13, count 0 2006.190.07:56:11.29#ibcon#end of sib2, iclass 13, count 0 2006.190.07:56:11.29#ibcon#*after write, iclass 13, count 0 2006.190.07:56:11.29#ibcon#*before return 0, iclass 13, count 0 2006.190.07:56:11.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:11.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.07:56:11.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.07:56:11.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.07:56:11.29$vc4f8/vblo=3,656.99 2006.190.07:56:11.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.07:56:11.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.07:56:11.29#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:11.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:11.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:11.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:11.29#ibcon#enter wrdev, iclass 15, count 0 2006.190.07:56:11.29#ibcon#first serial, iclass 15, count 0 2006.190.07:56:11.29#ibcon#enter sib2, iclass 15, count 0 2006.190.07:56:11.29#ibcon#flushed, iclass 15, count 0 2006.190.07:56:11.29#ibcon#about to write, iclass 15, count 0 2006.190.07:56:11.29#ibcon#wrote, iclass 15, count 0 2006.190.07:56:11.29#ibcon#about to read 3, iclass 15, count 0 2006.190.07:56:11.30#ibcon#read 3, iclass 15, count 0 2006.190.07:56:11.31#ibcon#about to read 4, iclass 15, count 0 2006.190.07:56:11.31#ibcon#read 4, iclass 15, count 0 2006.190.07:56:11.31#ibcon#about to read 5, iclass 15, count 0 2006.190.07:56:11.31#ibcon#read 5, iclass 15, count 0 2006.190.07:56:11.31#ibcon#about to read 6, iclass 15, count 0 2006.190.07:56:11.31#ibcon#read 6, iclass 15, count 0 2006.190.07:56:11.31#ibcon#end of sib2, iclass 15, count 0 2006.190.07:56:11.31#ibcon#*mode == 0, iclass 15, count 0 2006.190.07:56:11.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.07:56:11.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:56:11.31#ibcon#*before write, iclass 15, count 0 2006.190.07:56:11.31#ibcon#enter sib2, iclass 15, count 0 2006.190.07:56:11.31#ibcon#flushed, iclass 15, count 0 2006.190.07:56:11.31#ibcon#about to write, iclass 15, count 0 2006.190.07:56:11.31#ibcon#wrote, iclass 15, count 0 2006.190.07:56:11.31#ibcon#about to read 3, iclass 15, count 0 2006.190.07:56:11.34#ibcon#read 3, iclass 15, count 0 2006.190.07:56:11.34#ibcon#about to read 4, iclass 15, count 0 2006.190.07:56:11.34#ibcon#read 4, iclass 15, count 0 2006.190.07:56:11.34#ibcon#about to read 5, iclass 15, count 0 2006.190.07:56:11.35#ibcon#read 5, iclass 15, count 0 2006.190.07:56:11.35#ibcon#about to read 6, iclass 15, count 0 2006.190.07:56:11.35#ibcon#read 6, iclass 15, count 0 2006.190.07:56:11.35#ibcon#end of sib2, iclass 15, count 0 2006.190.07:56:11.35#ibcon#*after write, iclass 15, count 0 2006.190.07:56:11.35#ibcon#*before return 0, iclass 15, count 0 2006.190.07:56:11.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:11.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.07:56:11.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.07:56:11.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.07:56:11.35$vc4f8/vb=3,4 2006.190.07:56:11.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.07:56:11.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.07:56:11.35#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:11.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:11.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:11.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:11.40#ibcon#enter wrdev, iclass 17, count 2 2006.190.07:56:11.40#ibcon#first serial, iclass 17, count 2 2006.190.07:56:11.41#ibcon#enter sib2, iclass 17, count 2 2006.190.07:56:11.41#ibcon#flushed, iclass 17, count 2 2006.190.07:56:11.41#ibcon#about to write, iclass 17, count 2 2006.190.07:56:11.41#ibcon#wrote, iclass 17, count 2 2006.190.07:56:11.41#ibcon#about to read 3, iclass 17, count 2 2006.190.07:56:11.42#ibcon#read 3, iclass 17, count 2 2006.190.07:56:11.43#ibcon#about to read 4, iclass 17, count 2 2006.190.07:56:11.43#ibcon#read 4, iclass 17, count 2 2006.190.07:56:11.43#ibcon#about to read 5, iclass 17, count 2 2006.190.07:56:11.43#ibcon#read 5, iclass 17, count 2 2006.190.07:56:11.43#ibcon#about to read 6, iclass 17, count 2 2006.190.07:56:11.43#ibcon#read 6, iclass 17, count 2 2006.190.07:56:11.43#ibcon#end of sib2, iclass 17, count 2 2006.190.07:56:11.43#ibcon#*mode == 0, iclass 17, count 2 2006.190.07:56:11.43#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.07:56:11.43#ibcon#[27=AT03-04\r\n] 2006.190.07:56:11.43#ibcon#*before write, iclass 17, count 2 2006.190.07:56:11.43#ibcon#enter sib2, iclass 17, count 2 2006.190.07:56:11.43#ibcon#flushed, iclass 17, count 2 2006.190.07:56:11.43#ibcon#about to write, iclass 17, count 2 2006.190.07:56:11.43#ibcon#wrote, iclass 17, count 2 2006.190.07:56:11.43#ibcon#about to read 3, iclass 17, count 2 2006.190.07:56:11.45#ibcon#read 3, iclass 17, count 2 2006.190.07:56:11.45#ibcon#about to read 4, iclass 17, count 2 2006.190.07:56:11.45#ibcon#read 4, iclass 17, count 2 2006.190.07:56:11.45#ibcon#about to read 5, iclass 17, count 2 2006.190.07:56:11.46#ibcon#read 5, iclass 17, count 2 2006.190.07:56:11.46#ibcon#about to read 6, iclass 17, count 2 2006.190.07:56:11.46#ibcon#read 6, iclass 17, count 2 2006.190.07:56:11.46#ibcon#end of sib2, iclass 17, count 2 2006.190.07:56:11.46#ibcon#*after write, iclass 17, count 2 2006.190.07:56:11.46#ibcon#*before return 0, iclass 17, count 2 2006.190.07:56:11.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:11.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.07:56:11.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.07:56:11.46#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:11.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:11.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:11.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:11.57#ibcon#enter wrdev, iclass 17, count 0 2006.190.07:56:11.57#ibcon#first serial, iclass 17, count 0 2006.190.07:56:11.57#ibcon#enter sib2, iclass 17, count 0 2006.190.07:56:11.58#ibcon#flushed, iclass 17, count 0 2006.190.07:56:11.58#ibcon#about to write, iclass 17, count 0 2006.190.07:56:11.58#ibcon#wrote, iclass 17, count 0 2006.190.07:56:11.58#ibcon#about to read 3, iclass 17, count 0 2006.190.07:56:11.59#ibcon#read 3, iclass 17, count 0 2006.190.07:56:11.59#ibcon#about to read 4, iclass 17, count 0 2006.190.07:56:11.59#ibcon#read 4, iclass 17, count 0 2006.190.07:56:11.60#ibcon#about to read 5, iclass 17, count 0 2006.190.07:56:11.60#ibcon#read 5, iclass 17, count 0 2006.190.07:56:11.60#ibcon#about to read 6, iclass 17, count 0 2006.190.07:56:11.60#ibcon#read 6, iclass 17, count 0 2006.190.07:56:11.60#ibcon#end of sib2, iclass 17, count 0 2006.190.07:56:11.60#ibcon#*mode == 0, iclass 17, count 0 2006.190.07:56:11.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.07:56:11.60#ibcon#[27=USB\r\n] 2006.190.07:56:11.60#ibcon#*before write, iclass 17, count 0 2006.190.07:56:11.60#ibcon#enter sib2, iclass 17, count 0 2006.190.07:56:11.60#ibcon#flushed, iclass 17, count 0 2006.190.07:56:11.60#ibcon#about to write, iclass 17, count 0 2006.190.07:56:11.60#ibcon#wrote, iclass 17, count 0 2006.190.07:56:11.60#ibcon#about to read 3, iclass 17, count 0 2006.190.07:56:11.62#ibcon#read 3, iclass 17, count 0 2006.190.07:56:11.62#ibcon#about to read 4, iclass 17, count 0 2006.190.07:56:11.63#ibcon#read 4, iclass 17, count 0 2006.190.07:56:11.63#ibcon#about to read 5, iclass 17, count 0 2006.190.07:56:11.63#ibcon#read 5, iclass 17, count 0 2006.190.07:56:11.63#ibcon#about to read 6, iclass 17, count 0 2006.190.07:56:11.63#ibcon#read 6, iclass 17, count 0 2006.190.07:56:11.63#ibcon#end of sib2, iclass 17, count 0 2006.190.07:56:11.63#ibcon#*after write, iclass 17, count 0 2006.190.07:56:11.63#ibcon#*before return 0, iclass 17, count 0 2006.190.07:56:11.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:11.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.07:56:11.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.07:56:11.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.07:56:11.63$vc4f8/vblo=4,712.99 2006.190.07:56:11.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.07:56:11.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.07:56:11.63#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:11.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:11.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:11.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:11.63#ibcon#enter wrdev, iclass 19, count 0 2006.190.07:56:11.63#ibcon#first serial, iclass 19, count 0 2006.190.07:56:11.63#ibcon#enter sib2, iclass 19, count 0 2006.190.07:56:11.63#ibcon#flushed, iclass 19, count 0 2006.190.07:56:11.63#ibcon#about to write, iclass 19, count 0 2006.190.07:56:11.63#ibcon#wrote, iclass 19, count 0 2006.190.07:56:11.63#ibcon#about to read 3, iclass 19, count 0 2006.190.07:56:11.64#ibcon#read 3, iclass 19, count 0 2006.190.07:56:11.64#ibcon#about to read 4, iclass 19, count 0 2006.190.07:56:11.65#ibcon#read 4, iclass 19, count 0 2006.190.07:56:11.65#ibcon#about to read 5, iclass 19, count 0 2006.190.07:56:11.65#ibcon#read 5, iclass 19, count 0 2006.190.07:56:11.65#ibcon#about to read 6, iclass 19, count 0 2006.190.07:56:11.65#ibcon#read 6, iclass 19, count 0 2006.190.07:56:11.65#ibcon#end of sib2, iclass 19, count 0 2006.190.07:56:11.65#ibcon#*mode == 0, iclass 19, count 0 2006.190.07:56:11.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.07:56:11.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:56:11.65#ibcon#*before write, iclass 19, count 0 2006.190.07:56:11.65#ibcon#enter sib2, iclass 19, count 0 2006.190.07:56:11.65#ibcon#flushed, iclass 19, count 0 2006.190.07:56:11.65#ibcon#about to write, iclass 19, count 0 2006.190.07:56:11.65#ibcon#wrote, iclass 19, count 0 2006.190.07:56:11.65#ibcon#about to read 3, iclass 19, count 0 2006.190.07:56:11.68#ibcon#read 3, iclass 19, count 0 2006.190.07:56:11.68#ibcon#about to read 4, iclass 19, count 0 2006.190.07:56:11.68#ibcon#read 4, iclass 19, count 0 2006.190.07:56:11.69#ibcon#about to read 5, iclass 19, count 0 2006.190.07:56:11.69#ibcon#read 5, iclass 19, count 0 2006.190.07:56:11.69#ibcon#about to read 6, iclass 19, count 0 2006.190.07:56:11.69#ibcon#read 6, iclass 19, count 0 2006.190.07:56:11.69#ibcon#end of sib2, iclass 19, count 0 2006.190.07:56:11.69#ibcon#*after write, iclass 19, count 0 2006.190.07:56:11.69#ibcon#*before return 0, iclass 19, count 0 2006.190.07:56:11.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:11.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.07:56:11.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.07:56:11.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.07:56:11.69$vc4f8/vb=4,4 2006.190.07:56:11.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.07:56:11.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.07:56:11.69#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:11.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:11.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:11.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:11.74#ibcon#enter wrdev, iclass 21, count 2 2006.190.07:56:11.74#ibcon#first serial, iclass 21, count 2 2006.190.07:56:11.75#ibcon#enter sib2, iclass 21, count 2 2006.190.07:56:11.75#ibcon#flushed, iclass 21, count 2 2006.190.07:56:11.75#ibcon#about to write, iclass 21, count 2 2006.190.07:56:11.75#ibcon#wrote, iclass 21, count 2 2006.190.07:56:11.75#ibcon#about to read 3, iclass 21, count 2 2006.190.07:56:11.76#ibcon#read 3, iclass 21, count 2 2006.190.07:56:11.76#ibcon#about to read 4, iclass 21, count 2 2006.190.07:56:11.76#ibcon#read 4, iclass 21, count 2 2006.190.07:56:11.77#ibcon#about to read 5, iclass 21, count 2 2006.190.07:56:11.77#ibcon#read 5, iclass 21, count 2 2006.190.07:56:11.77#ibcon#about to read 6, iclass 21, count 2 2006.190.07:56:11.77#ibcon#read 6, iclass 21, count 2 2006.190.07:56:11.77#ibcon#end of sib2, iclass 21, count 2 2006.190.07:56:11.77#ibcon#*mode == 0, iclass 21, count 2 2006.190.07:56:11.77#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.07:56:11.77#ibcon#[27=AT04-04\r\n] 2006.190.07:56:11.77#ibcon#*before write, iclass 21, count 2 2006.190.07:56:11.77#ibcon#enter sib2, iclass 21, count 2 2006.190.07:56:11.77#ibcon#flushed, iclass 21, count 2 2006.190.07:56:11.77#ibcon#about to write, iclass 21, count 2 2006.190.07:56:11.77#ibcon#wrote, iclass 21, count 2 2006.190.07:56:11.77#ibcon#about to read 3, iclass 21, count 2 2006.190.07:56:11.80#ibcon#read 3, iclass 21, count 2 2006.190.07:56:11.80#ibcon#about to read 4, iclass 21, count 2 2006.190.07:56:11.80#ibcon#read 4, iclass 21, count 2 2006.190.07:56:11.80#ibcon#about to read 5, iclass 21, count 2 2006.190.07:56:11.80#ibcon#read 5, iclass 21, count 2 2006.190.07:56:11.80#ibcon#about to read 6, iclass 21, count 2 2006.190.07:56:11.80#ibcon#read 6, iclass 21, count 2 2006.190.07:56:11.80#ibcon#end of sib2, iclass 21, count 2 2006.190.07:56:11.80#ibcon#*after write, iclass 21, count 2 2006.190.07:56:11.80#ibcon#*before return 0, iclass 21, count 2 2006.190.07:56:11.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:11.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.07:56:11.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.07:56:11.80#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:11.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:11.91#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:11.91#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:11.91#ibcon#enter wrdev, iclass 21, count 0 2006.190.07:56:11.91#ibcon#first serial, iclass 21, count 0 2006.190.07:56:11.91#ibcon#enter sib2, iclass 21, count 0 2006.190.07:56:11.92#ibcon#flushed, iclass 21, count 0 2006.190.07:56:11.92#ibcon#about to write, iclass 21, count 0 2006.190.07:56:11.92#ibcon#wrote, iclass 21, count 0 2006.190.07:56:11.92#ibcon#about to read 3, iclass 21, count 0 2006.190.07:56:11.93#ibcon#read 3, iclass 21, count 0 2006.190.07:56:11.93#ibcon#about to read 4, iclass 21, count 0 2006.190.07:56:11.93#ibcon#read 4, iclass 21, count 0 2006.190.07:56:11.94#ibcon#about to read 5, iclass 21, count 0 2006.190.07:56:11.94#ibcon#read 5, iclass 21, count 0 2006.190.07:56:11.94#ibcon#about to read 6, iclass 21, count 0 2006.190.07:56:11.94#ibcon#read 6, iclass 21, count 0 2006.190.07:56:11.94#ibcon#end of sib2, iclass 21, count 0 2006.190.07:56:11.94#ibcon#*mode == 0, iclass 21, count 0 2006.190.07:56:11.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.07:56:11.94#ibcon#[27=USB\r\n] 2006.190.07:56:11.94#ibcon#*before write, iclass 21, count 0 2006.190.07:56:11.94#ibcon#enter sib2, iclass 21, count 0 2006.190.07:56:11.94#ibcon#flushed, iclass 21, count 0 2006.190.07:56:11.94#ibcon#about to write, iclass 21, count 0 2006.190.07:56:11.94#ibcon#wrote, iclass 21, count 0 2006.190.07:56:11.94#ibcon#about to read 3, iclass 21, count 0 2006.190.07:56:11.96#ibcon#read 3, iclass 21, count 0 2006.190.07:56:11.97#ibcon#about to read 4, iclass 21, count 0 2006.190.07:56:11.97#ibcon#read 4, iclass 21, count 0 2006.190.07:56:11.97#ibcon#about to read 5, iclass 21, count 0 2006.190.07:56:11.97#ibcon#read 5, iclass 21, count 0 2006.190.07:56:11.97#ibcon#about to read 6, iclass 21, count 0 2006.190.07:56:11.97#ibcon#read 6, iclass 21, count 0 2006.190.07:56:11.97#ibcon#end of sib2, iclass 21, count 0 2006.190.07:56:11.97#ibcon#*after write, iclass 21, count 0 2006.190.07:56:11.97#ibcon#*before return 0, iclass 21, count 0 2006.190.07:56:11.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:11.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.07:56:11.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.07:56:11.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.07:56:11.97$vc4f8/vblo=5,744.99 2006.190.07:56:11.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.07:56:11.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.07:56:11.97#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:11.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:11.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:11.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:11.97#ibcon#enter wrdev, iclass 23, count 0 2006.190.07:56:11.97#ibcon#first serial, iclass 23, count 0 2006.190.07:56:11.97#ibcon#enter sib2, iclass 23, count 0 2006.190.07:56:11.97#ibcon#flushed, iclass 23, count 0 2006.190.07:56:11.97#ibcon#about to write, iclass 23, count 0 2006.190.07:56:11.97#ibcon#wrote, iclass 23, count 0 2006.190.07:56:11.97#ibcon#about to read 3, iclass 23, count 0 2006.190.07:56:11.98#ibcon#read 3, iclass 23, count 0 2006.190.07:56:11.98#ibcon#about to read 4, iclass 23, count 0 2006.190.07:56:11.98#ibcon#read 4, iclass 23, count 0 2006.190.07:56:11.99#ibcon#about to read 5, iclass 23, count 0 2006.190.07:56:11.99#ibcon#read 5, iclass 23, count 0 2006.190.07:56:11.99#ibcon#about to read 6, iclass 23, count 0 2006.190.07:56:11.99#ibcon#read 6, iclass 23, count 0 2006.190.07:56:11.99#ibcon#end of sib2, iclass 23, count 0 2006.190.07:56:11.99#ibcon#*mode == 0, iclass 23, count 0 2006.190.07:56:11.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.07:56:11.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:56:11.99#ibcon#*before write, iclass 23, count 0 2006.190.07:56:11.99#ibcon#enter sib2, iclass 23, count 0 2006.190.07:56:11.99#ibcon#flushed, iclass 23, count 0 2006.190.07:56:11.99#ibcon#about to write, iclass 23, count 0 2006.190.07:56:11.99#ibcon#wrote, iclass 23, count 0 2006.190.07:56:11.99#ibcon#about to read 3, iclass 23, count 0 2006.190.07:56:12.02#ibcon#read 3, iclass 23, count 0 2006.190.07:56:12.02#ibcon#about to read 4, iclass 23, count 0 2006.190.07:56:12.02#ibcon#read 4, iclass 23, count 0 2006.190.07:56:12.03#ibcon#about to read 5, iclass 23, count 0 2006.190.07:56:12.03#ibcon#read 5, iclass 23, count 0 2006.190.07:56:12.03#ibcon#about to read 6, iclass 23, count 0 2006.190.07:56:12.03#ibcon#read 6, iclass 23, count 0 2006.190.07:56:12.03#ibcon#end of sib2, iclass 23, count 0 2006.190.07:56:12.03#ibcon#*after write, iclass 23, count 0 2006.190.07:56:12.03#ibcon#*before return 0, iclass 23, count 0 2006.190.07:56:12.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:12.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.07:56:12.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.07:56:12.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.07:56:12.03$vc4f8/vb=5,4 2006.190.07:56:12.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.07:56:12.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.07:56:12.03#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:12.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:12.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:12.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:12.08#ibcon#enter wrdev, iclass 25, count 2 2006.190.07:56:12.08#ibcon#first serial, iclass 25, count 2 2006.190.07:56:12.08#ibcon#enter sib2, iclass 25, count 2 2006.190.07:56:12.09#ibcon#flushed, iclass 25, count 2 2006.190.07:56:12.09#ibcon#about to write, iclass 25, count 2 2006.190.07:56:12.09#ibcon#wrote, iclass 25, count 2 2006.190.07:56:12.09#ibcon#about to read 3, iclass 25, count 2 2006.190.07:56:12.10#ibcon#read 3, iclass 25, count 2 2006.190.07:56:12.10#ibcon#about to read 4, iclass 25, count 2 2006.190.07:56:12.10#ibcon#read 4, iclass 25, count 2 2006.190.07:56:12.11#ibcon#about to read 5, iclass 25, count 2 2006.190.07:56:12.11#ibcon#read 5, iclass 25, count 2 2006.190.07:56:12.11#ibcon#about to read 6, iclass 25, count 2 2006.190.07:56:12.11#ibcon#read 6, iclass 25, count 2 2006.190.07:56:12.11#ibcon#end of sib2, iclass 25, count 2 2006.190.07:56:12.11#ibcon#*mode == 0, iclass 25, count 2 2006.190.07:56:12.11#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.07:56:12.11#ibcon#[27=AT05-04\r\n] 2006.190.07:56:12.11#ibcon#*before write, iclass 25, count 2 2006.190.07:56:12.11#ibcon#enter sib2, iclass 25, count 2 2006.190.07:56:12.11#ibcon#flushed, iclass 25, count 2 2006.190.07:56:12.11#ibcon#about to write, iclass 25, count 2 2006.190.07:56:12.11#ibcon#wrote, iclass 25, count 2 2006.190.07:56:12.11#ibcon#about to read 3, iclass 25, count 2 2006.190.07:56:12.13#ibcon#read 3, iclass 25, count 2 2006.190.07:56:12.13#ibcon#about to read 4, iclass 25, count 2 2006.190.07:56:12.13#ibcon#read 4, iclass 25, count 2 2006.190.07:56:12.14#ibcon#about to read 5, iclass 25, count 2 2006.190.07:56:12.14#ibcon#read 5, iclass 25, count 2 2006.190.07:56:12.14#ibcon#about to read 6, iclass 25, count 2 2006.190.07:56:12.14#ibcon#read 6, iclass 25, count 2 2006.190.07:56:12.14#ibcon#end of sib2, iclass 25, count 2 2006.190.07:56:12.14#ibcon#*after write, iclass 25, count 2 2006.190.07:56:12.14#ibcon#*before return 0, iclass 25, count 2 2006.190.07:56:12.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:12.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.07:56:12.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.07:56:12.14#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:12.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:12.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:12.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:12.25#ibcon#enter wrdev, iclass 25, count 0 2006.190.07:56:12.25#ibcon#first serial, iclass 25, count 0 2006.190.07:56:12.26#ibcon#enter sib2, iclass 25, count 0 2006.190.07:56:12.26#ibcon#flushed, iclass 25, count 0 2006.190.07:56:12.26#ibcon#about to write, iclass 25, count 0 2006.190.07:56:12.26#ibcon#wrote, iclass 25, count 0 2006.190.07:56:12.26#ibcon#about to read 3, iclass 25, count 0 2006.190.07:56:12.27#ibcon#read 3, iclass 25, count 0 2006.190.07:56:12.27#ibcon#about to read 4, iclass 25, count 0 2006.190.07:56:12.27#ibcon#read 4, iclass 25, count 0 2006.190.07:56:12.28#ibcon#about to read 5, iclass 25, count 0 2006.190.07:56:12.28#ibcon#read 5, iclass 25, count 0 2006.190.07:56:12.28#ibcon#about to read 6, iclass 25, count 0 2006.190.07:56:12.28#ibcon#read 6, iclass 25, count 0 2006.190.07:56:12.28#ibcon#end of sib2, iclass 25, count 0 2006.190.07:56:12.28#ibcon#*mode == 0, iclass 25, count 0 2006.190.07:56:12.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.07:56:12.28#ibcon#[27=USB\r\n] 2006.190.07:56:12.28#ibcon#*before write, iclass 25, count 0 2006.190.07:56:12.28#ibcon#enter sib2, iclass 25, count 0 2006.190.07:56:12.28#ibcon#flushed, iclass 25, count 0 2006.190.07:56:12.28#ibcon#about to write, iclass 25, count 0 2006.190.07:56:12.28#ibcon#wrote, iclass 25, count 0 2006.190.07:56:12.28#ibcon#about to read 3, iclass 25, count 0 2006.190.07:56:12.30#ibcon#read 3, iclass 25, count 0 2006.190.07:56:12.30#ibcon#about to read 4, iclass 25, count 0 2006.190.07:56:12.30#ibcon#read 4, iclass 25, count 0 2006.190.07:56:12.31#ibcon#about to read 5, iclass 25, count 0 2006.190.07:56:12.31#ibcon#read 5, iclass 25, count 0 2006.190.07:56:12.31#ibcon#about to read 6, iclass 25, count 0 2006.190.07:56:12.31#ibcon#read 6, iclass 25, count 0 2006.190.07:56:12.31#ibcon#end of sib2, iclass 25, count 0 2006.190.07:56:12.31#ibcon#*after write, iclass 25, count 0 2006.190.07:56:12.31#ibcon#*before return 0, iclass 25, count 0 2006.190.07:56:12.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:12.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.07:56:12.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.07:56:12.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.07:56:12.31$vc4f8/vblo=6,752.99 2006.190.07:56:12.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.07:56:12.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.07:56:12.31#ibcon#ireg 17 cls_cnt 0 2006.190.07:56:12.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:12.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:12.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:12.31#ibcon#enter wrdev, iclass 27, count 0 2006.190.07:56:12.31#ibcon#first serial, iclass 27, count 0 2006.190.07:56:12.31#ibcon#enter sib2, iclass 27, count 0 2006.190.07:56:12.31#ibcon#flushed, iclass 27, count 0 2006.190.07:56:12.31#ibcon#about to write, iclass 27, count 0 2006.190.07:56:12.31#ibcon#wrote, iclass 27, count 0 2006.190.07:56:12.31#ibcon#about to read 3, iclass 27, count 0 2006.190.07:56:12.32#ibcon#read 3, iclass 27, count 0 2006.190.07:56:12.32#ibcon#about to read 4, iclass 27, count 0 2006.190.07:56:12.33#ibcon#read 4, iclass 27, count 0 2006.190.07:56:12.33#ibcon#about to read 5, iclass 27, count 0 2006.190.07:56:12.33#ibcon#read 5, iclass 27, count 0 2006.190.07:56:12.33#ibcon#about to read 6, iclass 27, count 0 2006.190.07:56:12.33#ibcon#read 6, iclass 27, count 0 2006.190.07:56:12.33#ibcon#end of sib2, iclass 27, count 0 2006.190.07:56:12.33#ibcon#*mode == 0, iclass 27, count 0 2006.190.07:56:12.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.07:56:12.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:56:12.33#ibcon#*before write, iclass 27, count 0 2006.190.07:56:12.33#ibcon#enter sib2, iclass 27, count 0 2006.190.07:56:12.33#ibcon#flushed, iclass 27, count 0 2006.190.07:56:12.33#ibcon#about to write, iclass 27, count 0 2006.190.07:56:12.33#ibcon#wrote, iclass 27, count 0 2006.190.07:56:12.33#ibcon#about to read 3, iclass 27, count 0 2006.190.07:56:12.36#ibcon#read 3, iclass 27, count 0 2006.190.07:56:12.36#ibcon#about to read 4, iclass 27, count 0 2006.190.07:56:12.36#ibcon#read 4, iclass 27, count 0 2006.190.07:56:12.37#ibcon#about to read 5, iclass 27, count 0 2006.190.07:56:12.37#ibcon#read 5, iclass 27, count 0 2006.190.07:56:12.37#ibcon#about to read 6, iclass 27, count 0 2006.190.07:56:12.37#ibcon#read 6, iclass 27, count 0 2006.190.07:56:12.37#ibcon#end of sib2, iclass 27, count 0 2006.190.07:56:12.37#ibcon#*after write, iclass 27, count 0 2006.190.07:56:12.37#ibcon#*before return 0, iclass 27, count 0 2006.190.07:56:12.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:12.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.07:56:12.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.07:56:12.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.07:56:12.37$vc4f8/vb=6,4 2006.190.07:56:12.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.07:56:12.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.07:56:12.37#ibcon#ireg 11 cls_cnt 2 2006.190.07:56:12.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:12.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:12.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:12.42#ibcon#enter wrdev, iclass 29, count 2 2006.190.07:56:12.42#ibcon#first serial, iclass 29, count 2 2006.190.07:56:12.42#ibcon#enter sib2, iclass 29, count 2 2006.190.07:56:12.43#ibcon#flushed, iclass 29, count 2 2006.190.07:56:12.43#ibcon#about to write, iclass 29, count 2 2006.190.07:56:12.43#ibcon#wrote, iclass 29, count 2 2006.190.07:56:12.43#ibcon#about to read 3, iclass 29, count 2 2006.190.07:56:12.44#ibcon#read 3, iclass 29, count 2 2006.190.07:56:12.44#ibcon#about to read 4, iclass 29, count 2 2006.190.07:56:12.44#ibcon#read 4, iclass 29, count 2 2006.190.07:56:12.45#ibcon#about to read 5, iclass 29, count 2 2006.190.07:56:12.45#ibcon#read 5, iclass 29, count 2 2006.190.07:56:12.45#ibcon#about to read 6, iclass 29, count 2 2006.190.07:56:12.45#ibcon#read 6, iclass 29, count 2 2006.190.07:56:12.45#ibcon#end of sib2, iclass 29, count 2 2006.190.07:56:12.45#ibcon#*mode == 0, iclass 29, count 2 2006.190.07:56:12.45#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.07:56:12.45#ibcon#[27=AT06-04\r\n] 2006.190.07:56:12.45#ibcon#*before write, iclass 29, count 2 2006.190.07:56:12.45#ibcon#enter sib2, iclass 29, count 2 2006.190.07:56:12.45#ibcon#flushed, iclass 29, count 2 2006.190.07:56:12.45#ibcon#about to write, iclass 29, count 2 2006.190.07:56:12.45#ibcon#wrote, iclass 29, count 2 2006.190.07:56:12.45#ibcon#about to read 3, iclass 29, count 2 2006.190.07:56:12.47#ibcon#read 3, iclass 29, count 2 2006.190.07:56:12.47#ibcon#about to read 4, iclass 29, count 2 2006.190.07:56:12.47#ibcon#read 4, iclass 29, count 2 2006.190.07:56:12.48#ibcon#about to read 5, iclass 29, count 2 2006.190.07:56:12.48#ibcon#read 5, iclass 29, count 2 2006.190.07:56:12.48#ibcon#about to read 6, iclass 29, count 2 2006.190.07:56:12.48#ibcon#read 6, iclass 29, count 2 2006.190.07:56:12.48#ibcon#end of sib2, iclass 29, count 2 2006.190.07:56:12.48#ibcon#*after write, iclass 29, count 2 2006.190.07:56:12.48#ibcon#*before return 0, iclass 29, count 2 2006.190.07:56:12.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:12.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.07:56:12.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.07:56:12.48#ibcon#ireg 7 cls_cnt 0 2006.190.07:56:12.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:12.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:12.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:12.59#ibcon#enter wrdev, iclass 29, count 0 2006.190.07:56:12.59#ibcon#first serial, iclass 29, count 0 2006.190.07:56:12.59#ibcon#enter sib2, iclass 29, count 0 2006.190.07:56:12.60#ibcon#flushed, iclass 29, count 0 2006.190.07:56:12.60#ibcon#about to write, iclass 29, count 0 2006.190.07:56:12.60#ibcon#wrote, iclass 29, count 0 2006.190.07:56:12.60#ibcon#about to read 3, iclass 29, count 0 2006.190.07:56:12.61#ibcon#read 3, iclass 29, count 0 2006.190.07:56:12.61#ibcon#about to read 4, iclass 29, count 0 2006.190.07:56:12.62#ibcon#read 4, iclass 29, count 0 2006.190.07:56:12.62#ibcon#about to read 5, iclass 29, count 0 2006.190.07:56:12.62#ibcon#read 5, iclass 29, count 0 2006.190.07:56:12.62#ibcon#about to read 6, iclass 29, count 0 2006.190.07:56:12.62#ibcon#read 6, iclass 29, count 0 2006.190.07:56:12.62#ibcon#end of sib2, iclass 29, count 0 2006.190.07:56:12.62#ibcon#*mode == 0, iclass 29, count 0 2006.190.07:56:12.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.07:56:12.62#ibcon#[27=USB\r\n] 2006.190.07:56:12.62#ibcon#*before write, iclass 29, count 0 2006.190.07:56:12.62#ibcon#enter sib2, iclass 29, count 0 2006.190.07:56:12.62#ibcon#flushed, iclass 29, count 0 2006.190.07:56:12.62#ibcon#about to write, iclass 29, count 0 2006.190.07:56:12.62#ibcon#wrote, iclass 29, count 0 2006.190.07:56:12.62#ibcon#about to read 3, iclass 29, count 0 2006.190.07:56:12.64#ibcon#read 3, iclass 29, count 0 2006.190.07:56:12.64#ibcon#about to read 4, iclass 29, count 0 2006.190.07:56:12.64#ibcon#read 4, iclass 29, count 0 2006.190.07:56:12.65#ibcon#about to read 5, iclass 29, count 0 2006.190.07:56:12.65#ibcon#read 5, iclass 29, count 0 2006.190.07:56:12.65#ibcon#about to read 6, iclass 29, count 0 2006.190.07:56:12.65#ibcon#read 6, iclass 29, count 0 2006.190.07:56:12.65#ibcon#end of sib2, iclass 29, count 0 2006.190.07:56:12.65#ibcon#*after write, iclass 29, count 0 2006.190.07:56:12.65#ibcon#*before return 0, iclass 29, count 0 2006.190.07:56:12.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:12.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.07:56:12.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.07:56:12.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.07:56:12.65$vc4f8/vabw=wide 2006.190.07:56:12.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.07:56:12.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.07:56:12.65#ibcon#ireg 8 cls_cnt 0 2006.190.07:56:12.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:12.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:12.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:12.65#ibcon#enter wrdev, iclass 31, count 0 2006.190.07:56:12.65#ibcon#first serial, iclass 31, count 0 2006.190.07:56:12.65#ibcon#enter sib2, iclass 31, count 0 2006.190.07:56:12.65#ibcon#flushed, iclass 31, count 0 2006.190.07:56:12.65#ibcon#about to write, iclass 31, count 0 2006.190.07:56:12.65#ibcon#wrote, iclass 31, count 0 2006.190.07:56:12.65#ibcon#about to read 3, iclass 31, count 0 2006.190.07:56:12.66#ibcon#read 3, iclass 31, count 0 2006.190.07:56:12.66#ibcon#about to read 4, iclass 31, count 0 2006.190.07:56:12.66#ibcon#read 4, iclass 31, count 0 2006.190.07:56:12.67#ibcon#about to read 5, iclass 31, count 0 2006.190.07:56:12.67#ibcon#read 5, iclass 31, count 0 2006.190.07:56:12.67#ibcon#about to read 6, iclass 31, count 0 2006.190.07:56:12.67#ibcon#read 6, iclass 31, count 0 2006.190.07:56:12.67#ibcon#end of sib2, iclass 31, count 0 2006.190.07:56:12.67#ibcon#*mode == 0, iclass 31, count 0 2006.190.07:56:12.67#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.07:56:12.67#ibcon#[25=BW32\r\n] 2006.190.07:56:12.67#ibcon#*before write, iclass 31, count 0 2006.190.07:56:12.67#ibcon#enter sib2, iclass 31, count 0 2006.190.07:56:12.67#ibcon#flushed, iclass 31, count 0 2006.190.07:56:12.67#ibcon#about to write, iclass 31, count 0 2006.190.07:56:12.67#ibcon#wrote, iclass 31, count 0 2006.190.07:56:12.67#ibcon#about to read 3, iclass 31, count 0 2006.190.07:56:12.69#ibcon#read 3, iclass 31, count 0 2006.190.07:56:12.69#ibcon#about to read 4, iclass 31, count 0 2006.190.07:56:12.69#ibcon#read 4, iclass 31, count 0 2006.190.07:56:12.70#ibcon#about to read 5, iclass 31, count 0 2006.190.07:56:12.70#ibcon#read 5, iclass 31, count 0 2006.190.07:56:12.70#ibcon#about to read 6, iclass 31, count 0 2006.190.07:56:12.70#ibcon#read 6, iclass 31, count 0 2006.190.07:56:12.70#ibcon#end of sib2, iclass 31, count 0 2006.190.07:56:12.70#ibcon#*after write, iclass 31, count 0 2006.190.07:56:12.70#ibcon#*before return 0, iclass 31, count 0 2006.190.07:56:12.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:12.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.07:56:12.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.07:56:12.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.07:56:12.70$vc4f8/vbbw=wide 2006.190.07:56:12.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.07:56:12.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.07:56:12.70#ibcon#ireg 8 cls_cnt 0 2006.190.07:56:12.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:56:12.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:56:12.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:56:12.76#ibcon#enter wrdev, iclass 33, count 0 2006.190.07:56:12.76#ibcon#first serial, iclass 33, count 0 2006.190.07:56:12.76#ibcon#enter sib2, iclass 33, count 0 2006.190.07:56:12.77#ibcon#flushed, iclass 33, count 0 2006.190.07:56:12.77#ibcon#about to write, iclass 33, count 0 2006.190.07:56:12.77#ibcon#wrote, iclass 33, count 0 2006.190.07:56:12.77#ibcon#about to read 3, iclass 33, count 0 2006.190.07:56:12.78#ibcon#read 3, iclass 33, count 0 2006.190.07:56:12.78#ibcon#about to read 4, iclass 33, count 0 2006.190.07:56:12.78#ibcon#read 4, iclass 33, count 0 2006.190.07:56:12.79#ibcon#about to read 5, iclass 33, count 0 2006.190.07:56:12.79#ibcon#read 5, iclass 33, count 0 2006.190.07:56:12.79#ibcon#about to read 6, iclass 33, count 0 2006.190.07:56:12.79#ibcon#read 6, iclass 33, count 0 2006.190.07:56:12.79#ibcon#end of sib2, iclass 33, count 0 2006.190.07:56:12.79#ibcon#*mode == 0, iclass 33, count 0 2006.190.07:56:12.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.07:56:12.79#ibcon#[27=BW32\r\n] 2006.190.07:56:12.79#ibcon#*before write, iclass 33, count 0 2006.190.07:56:12.79#ibcon#enter sib2, iclass 33, count 0 2006.190.07:56:12.79#ibcon#flushed, iclass 33, count 0 2006.190.07:56:12.79#ibcon#about to write, iclass 33, count 0 2006.190.07:56:12.79#ibcon#wrote, iclass 33, count 0 2006.190.07:56:12.79#ibcon#about to read 3, iclass 33, count 0 2006.190.07:56:12.81#ibcon#read 3, iclass 33, count 0 2006.190.07:56:12.81#ibcon#about to read 4, iclass 33, count 0 2006.190.07:56:12.81#ibcon#read 4, iclass 33, count 0 2006.190.07:56:12.82#ibcon#about to read 5, iclass 33, count 0 2006.190.07:56:12.82#ibcon#read 5, iclass 33, count 0 2006.190.07:56:12.82#ibcon#about to read 6, iclass 33, count 0 2006.190.07:56:12.82#ibcon#read 6, iclass 33, count 0 2006.190.07:56:12.82#ibcon#end of sib2, iclass 33, count 0 2006.190.07:56:12.82#ibcon#*after write, iclass 33, count 0 2006.190.07:56:12.82#ibcon#*before return 0, iclass 33, count 0 2006.190.07:56:12.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:56:12.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.07:56:12.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.07:56:12.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.07:56:12.82$4f8m12a/ifd4f 2006.190.07:56:12.82$ifd4f/lo= 2006.190.07:56:12.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:56:12.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:56:12.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:56:12.82$ifd4f/patch= 2006.190.07:56:12.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:56:12.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:56:12.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:56:12.82$4f8m12a/"form=m,16.000,1:2 2006.190.07:56:12.82$4f8m12a/"tpicd 2006.190.07:56:12.82$4f8m12a/echo=off 2006.190.07:56:12.82$4f8m12a/xlog=off 2006.190.07:56:12.82:!2006.190.07:58:20 2006.190.07:56:52.14#trakl#Source acquired 2006.190.07:56:52.15#flagr#flagr/antenna,acquired 2006.190.07:58:20.02:preob 2006.190.07:58:21.15/onsource/TRACKING 2006.190.07:58:21.15:!2006.190.07:58:30 2006.190.07:58:30.01:data_valid=on 2006.190.07:58:30.02:midob 2006.190.07:58:31.15/onsource/TRACKING 2006.190.07:58:31.15/wx/24.53,1011.9,100 2006.190.07:58:31.29/cable/+6.4717E-03 2006.190.07:58:32.38/va/01,08,usb,yes,32,34 2006.190.07:58:32.38/va/02,07,usb,yes,33,34 2006.190.07:58:32.38/va/03,06,usb,yes,34,35 2006.190.07:58:32.38/va/04,07,usb,yes,34,36 2006.190.07:58:32.38/va/05,07,usb,yes,36,39 2006.190.07:58:32.38/va/06,06,usb,yes,36,35 2006.190.07:58:32.38/va/07,06,usb,yes,36,36 2006.190.07:58:32.38/va/08,06,usb,yes,39,38 2006.190.07:58:32.61/valo/01,532.99,yes,locked 2006.190.07:58:32.61/valo/02,572.99,yes,locked 2006.190.07:58:32.61/valo/03,672.99,yes,locked 2006.190.07:58:32.61/valo/04,832.99,yes,locked 2006.190.07:58:32.61/valo/05,652.99,yes,locked 2006.190.07:58:32.61/valo/06,772.99,yes,locked 2006.190.07:58:32.61/valo/07,832.99,yes,locked 2006.190.07:58:32.61/valo/08,852.99,yes,locked 2006.190.07:58:33.70/vb/01,04,usb,yes,29,28 2006.190.07:58:33.70/vb/02,04,usb,yes,31,32 2006.190.07:58:33.70/vb/03,04,usb,yes,27,31 2006.190.07:58:33.70/vb/04,04,usb,yes,28,28 2006.190.07:58:33.70/vb/05,04,usb,yes,26,30 2006.190.07:58:33.70/vb/06,04,usb,yes,27,30 2006.190.07:58:33.70/vb/07,04,usb,yes,29,29 2006.190.07:58:33.70/vb/08,04,usb,yes,27,30 2006.190.07:58:33.94/vblo/01,632.99,yes,locked 2006.190.07:58:33.94/vblo/02,640.99,yes,locked 2006.190.07:58:33.94/vblo/03,656.99,yes,locked 2006.190.07:58:33.94/vblo/04,712.99,yes,locked 2006.190.07:58:33.94/vblo/05,744.99,yes,locked 2006.190.07:58:33.94/vblo/06,752.99,yes,locked 2006.190.07:58:33.94/vblo/07,734.99,yes,locked 2006.190.07:58:33.94/vblo/08,744.99,yes,locked 2006.190.07:58:34.09/vabw/8 2006.190.07:58:34.24/vbbw/8 2006.190.07:58:34.33/xfe/off,on,15.2 2006.190.07:58:34.70/ifatt/23,28,28,28 2006.190.07:58:35.07/fmout-gps/S +2.87E-07 2006.190.07:58:35.16:!2006.190.07:59:30 2006.190.07:59:30.01:data_valid=off 2006.190.07:59:30.02:postob 2006.190.07:59:30.20/cable/+6.4711E-03 2006.190.07:59:30.21/wx/24.53,1012.0,100 2006.190.07:59:31.07/fmout-gps/S +2.87E-07 2006.190.07:59:31.08:scan_name=190-0800,k06190,60 2006.190.07:59:31.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.190.07:59:32.14#flagr#flagr/antenna,new-source 2006.190.07:59:32.15:checkk5 2006.190.07:59:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.190.07:59:32.92/chk_autoobs//k5ts2/ autoobs is running! 2006.190.07:59:33.31/chk_autoobs//k5ts3/ autoobs is running! 2006.190.07:59:33.69/chk_autoobs//k5ts4/ autoobs is running! 2006.190.07:59:34.07/chk_obsdata//k5ts1/T1900758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:59:34.44/chk_obsdata//k5ts2/T1900758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:59:34.81/chk_obsdata//k5ts3/T1900758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:59:35.19/chk_obsdata//k5ts4/T1900758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.07:59:35.88/k5log//k5ts1_log_newline 2006.190.07:59:36.58/k5log//k5ts2_log_newline 2006.190.07:59:37.28/k5log//k5ts3_log_newline 2006.190.07:59:37.98/k5log//k5ts4_log_newline 2006.190.07:59:38.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.07:59:38.00:4f8m12a=2 2006.190.07:59:38.00$4f8m12a/echo=on 2006.190.07:59:38.00$4f8m12a/pcalon 2006.190.07:59:38.00$pcalon/"no phase cal control is implemented here 2006.190.07:59:38.00$4f8m12a/"tpicd=stop 2006.190.07:59:38.00$4f8m12a/vc4f8 2006.190.07:59:38.01$vc4f8/valo=1,532.99 2006.190.07:59:38.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:59:38.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:59:38.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:38.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:38.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:38.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:38.01#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:59:38.01#ibcon#first serial, iclass 6, count 0 2006.190.07:59:38.01#ibcon#enter sib2, iclass 6, count 0 2006.190.07:59:38.01#ibcon#flushed, iclass 6, count 0 2006.190.07:59:38.01#ibcon#about to write, iclass 6, count 0 2006.190.07:59:38.01#ibcon#wrote, iclass 6, count 0 2006.190.07:59:38.01#ibcon#about to read 3, iclass 6, count 0 2006.190.07:59:38.06#ibcon#read 3, iclass 6, count 0 2006.190.07:59:38.06#ibcon#about to read 4, iclass 6, count 0 2006.190.07:59:38.06#ibcon#read 4, iclass 6, count 0 2006.190.07:59:38.06#ibcon#about to read 5, iclass 6, count 0 2006.190.07:59:38.06#ibcon#read 5, iclass 6, count 0 2006.190.07:59:38.06#ibcon#about to read 6, iclass 6, count 0 2006.190.07:59:38.06#ibcon#read 6, iclass 6, count 0 2006.190.07:59:38.06#ibcon#end of sib2, iclass 6, count 0 2006.190.07:59:38.06#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:59:38.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:59:38.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.07:59:38.06#ibcon#*before write, iclass 6, count 0 2006.190.07:59:38.06#ibcon#enter sib2, iclass 6, count 0 2006.190.07:59:38.06#ibcon#flushed, iclass 6, count 0 2006.190.07:59:38.06#ibcon#about to write, iclass 6, count 0 2006.190.07:59:38.06#ibcon#wrote, iclass 6, count 0 2006.190.07:59:38.06#ibcon#about to read 3, iclass 6, count 0 2006.190.07:59:38.10#ibcon#read 3, iclass 6, count 0 2006.190.07:59:38.10#ibcon#about to read 4, iclass 6, count 0 2006.190.07:59:38.10#ibcon#read 4, iclass 6, count 0 2006.190.07:59:38.10#ibcon#about to read 5, iclass 6, count 0 2006.190.07:59:38.10#ibcon#read 5, iclass 6, count 0 2006.190.07:59:38.10#ibcon#about to read 6, iclass 6, count 0 2006.190.07:59:38.10#ibcon#read 6, iclass 6, count 0 2006.190.07:59:38.10#ibcon#end of sib2, iclass 6, count 0 2006.190.07:59:38.10#ibcon#*after write, iclass 6, count 0 2006.190.07:59:38.10#ibcon#*before return 0, iclass 6, count 0 2006.190.07:59:38.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:38.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:38.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:59:38.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:59:38.10$vc4f8/va=1,8 2006.190.07:59:38.10#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:59:38.10#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:59:38.10#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:38.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:38.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:38.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:38.10#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:59:38.10#ibcon#first serial, iclass 10, count 2 2006.190.07:59:38.10#ibcon#enter sib2, iclass 10, count 2 2006.190.07:59:38.10#ibcon#flushed, iclass 10, count 2 2006.190.07:59:38.10#ibcon#about to write, iclass 10, count 2 2006.190.07:59:38.10#ibcon#wrote, iclass 10, count 2 2006.190.07:59:38.10#ibcon#about to read 3, iclass 10, count 2 2006.190.07:59:38.14#ibcon#read 3, iclass 10, count 2 2006.190.07:59:38.14#ibcon#about to read 4, iclass 10, count 2 2006.190.07:59:38.14#ibcon#read 4, iclass 10, count 2 2006.190.07:59:38.14#ibcon#about to read 5, iclass 10, count 2 2006.190.07:59:38.14#ibcon#read 5, iclass 10, count 2 2006.190.07:59:38.14#ibcon#about to read 6, iclass 10, count 2 2006.190.07:59:38.14#ibcon#read 6, iclass 10, count 2 2006.190.07:59:38.14#ibcon#end of sib2, iclass 10, count 2 2006.190.07:59:38.14#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:59:38.14#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:59:38.14#ibcon#[25=AT01-08\r\n] 2006.190.07:59:38.14#ibcon#*before write, iclass 10, count 2 2006.190.07:59:38.14#ibcon#enter sib2, iclass 10, count 2 2006.190.07:59:38.14#ibcon#flushed, iclass 10, count 2 2006.190.07:59:38.14#ibcon#about to write, iclass 10, count 2 2006.190.07:59:38.14#ibcon#wrote, iclass 10, count 2 2006.190.07:59:38.14#ibcon#about to read 3, iclass 10, count 2 2006.190.07:59:38.17#ibcon#read 3, iclass 10, count 2 2006.190.07:59:38.17#ibcon#about to read 4, iclass 10, count 2 2006.190.07:59:38.17#ibcon#read 4, iclass 10, count 2 2006.190.07:59:38.17#ibcon#about to read 5, iclass 10, count 2 2006.190.07:59:38.17#ibcon#read 5, iclass 10, count 2 2006.190.07:59:38.17#ibcon#about to read 6, iclass 10, count 2 2006.190.07:59:38.17#ibcon#read 6, iclass 10, count 2 2006.190.07:59:38.17#ibcon#end of sib2, iclass 10, count 2 2006.190.07:59:38.17#ibcon#*after write, iclass 10, count 2 2006.190.07:59:38.17#ibcon#*before return 0, iclass 10, count 2 2006.190.07:59:38.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:38.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:38.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:59:38.17#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:38.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:38.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:38.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:38.29#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:59:38.29#ibcon#first serial, iclass 10, count 0 2006.190.07:59:38.29#ibcon#enter sib2, iclass 10, count 0 2006.190.07:59:38.29#ibcon#flushed, iclass 10, count 0 2006.190.07:59:38.29#ibcon#about to write, iclass 10, count 0 2006.190.07:59:38.29#ibcon#wrote, iclass 10, count 0 2006.190.07:59:38.29#ibcon#about to read 3, iclass 10, count 0 2006.190.07:59:38.31#ibcon#read 3, iclass 10, count 0 2006.190.07:59:38.31#ibcon#about to read 4, iclass 10, count 0 2006.190.07:59:38.31#ibcon#read 4, iclass 10, count 0 2006.190.07:59:38.31#ibcon#about to read 5, iclass 10, count 0 2006.190.07:59:38.31#ibcon#read 5, iclass 10, count 0 2006.190.07:59:38.31#ibcon#about to read 6, iclass 10, count 0 2006.190.07:59:38.31#ibcon#read 6, iclass 10, count 0 2006.190.07:59:38.31#ibcon#end of sib2, iclass 10, count 0 2006.190.07:59:38.31#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:59:38.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:59:38.31#ibcon#[25=USB\r\n] 2006.190.07:59:38.31#ibcon#*before write, iclass 10, count 0 2006.190.07:59:38.31#ibcon#enter sib2, iclass 10, count 0 2006.190.07:59:38.31#ibcon#flushed, iclass 10, count 0 2006.190.07:59:38.31#ibcon#about to write, iclass 10, count 0 2006.190.07:59:38.31#ibcon#wrote, iclass 10, count 0 2006.190.07:59:38.31#ibcon#about to read 3, iclass 10, count 0 2006.190.07:59:38.34#ibcon#read 3, iclass 10, count 0 2006.190.07:59:38.34#ibcon#about to read 4, iclass 10, count 0 2006.190.07:59:38.34#ibcon#read 4, iclass 10, count 0 2006.190.07:59:38.34#ibcon#about to read 5, iclass 10, count 0 2006.190.07:59:38.34#ibcon#read 5, iclass 10, count 0 2006.190.07:59:38.34#ibcon#about to read 6, iclass 10, count 0 2006.190.07:59:38.34#ibcon#read 6, iclass 10, count 0 2006.190.07:59:38.34#ibcon#end of sib2, iclass 10, count 0 2006.190.07:59:38.34#ibcon#*after write, iclass 10, count 0 2006.190.07:59:38.34#ibcon#*before return 0, iclass 10, count 0 2006.190.07:59:38.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:38.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:38.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:59:38.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:59:38.34$vc4f8/valo=2,572.99 2006.190.07:59:38.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:59:38.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:59:38.34#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:38.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:38.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:38.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:38.34#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:59:38.34#ibcon#first serial, iclass 12, count 0 2006.190.07:59:38.34#ibcon#enter sib2, iclass 12, count 0 2006.190.07:59:38.34#ibcon#flushed, iclass 12, count 0 2006.190.07:59:38.34#ibcon#about to write, iclass 12, count 0 2006.190.07:59:38.34#ibcon#wrote, iclass 12, count 0 2006.190.07:59:38.34#ibcon#about to read 3, iclass 12, count 0 2006.190.07:59:38.36#ibcon#read 3, iclass 12, count 0 2006.190.07:59:38.36#ibcon#about to read 4, iclass 12, count 0 2006.190.07:59:38.36#ibcon#read 4, iclass 12, count 0 2006.190.07:59:38.36#ibcon#about to read 5, iclass 12, count 0 2006.190.07:59:38.36#ibcon#read 5, iclass 12, count 0 2006.190.07:59:38.36#ibcon#about to read 6, iclass 12, count 0 2006.190.07:59:38.36#ibcon#read 6, iclass 12, count 0 2006.190.07:59:38.36#ibcon#end of sib2, iclass 12, count 0 2006.190.07:59:38.36#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:59:38.36#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:59:38.36#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.07:59:38.36#ibcon#*before write, iclass 12, count 0 2006.190.07:59:38.36#ibcon#enter sib2, iclass 12, count 0 2006.190.07:59:38.36#ibcon#flushed, iclass 12, count 0 2006.190.07:59:38.36#ibcon#about to write, iclass 12, count 0 2006.190.07:59:38.36#ibcon#wrote, iclass 12, count 0 2006.190.07:59:38.36#ibcon#about to read 3, iclass 12, count 0 2006.190.07:59:38.41#ibcon#read 3, iclass 12, count 0 2006.190.07:59:38.41#ibcon#about to read 4, iclass 12, count 0 2006.190.07:59:38.41#ibcon#read 4, iclass 12, count 0 2006.190.07:59:38.41#ibcon#about to read 5, iclass 12, count 0 2006.190.07:59:38.41#ibcon#read 5, iclass 12, count 0 2006.190.07:59:38.41#ibcon#about to read 6, iclass 12, count 0 2006.190.07:59:38.41#ibcon#read 6, iclass 12, count 0 2006.190.07:59:38.41#ibcon#end of sib2, iclass 12, count 0 2006.190.07:59:38.41#ibcon#*after write, iclass 12, count 0 2006.190.07:59:38.41#ibcon#*before return 0, iclass 12, count 0 2006.190.07:59:38.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:38.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:38.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:59:38.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:59:38.41$vc4f8/va=2,7 2006.190.07:59:38.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:59:38.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:59:38.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:38.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:38.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:38.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:38.45#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:59:38.45#ibcon#first serial, iclass 14, count 2 2006.190.07:59:38.45#ibcon#enter sib2, iclass 14, count 2 2006.190.07:59:38.45#ibcon#flushed, iclass 14, count 2 2006.190.07:59:38.45#ibcon#about to write, iclass 14, count 2 2006.190.07:59:38.45#ibcon#wrote, iclass 14, count 2 2006.190.07:59:38.45#ibcon#about to read 3, iclass 14, count 2 2006.190.07:59:38.47#ibcon#read 3, iclass 14, count 2 2006.190.07:59:38.47#ibcon#about to read 4, iclass 14, count 2 2006.190.07:59:38.47#ibcon#read 4, iclass 14, count 2 2006.190.07:59:38.47#ibcon#about to read 5, iclass 14, count 2 2006.190.07:59:38.47#ibcon#read 5, iclass 14, count 2 2006.190.07:59:38.47#ibcon#about to read 6, iclass 14, count 2 2006.190.07:59:38.47#ibcon#read 6, iclass 14, count 2 2006.190.07:59:38.47#ibcon#end of sib2, iclass 14, count 2 2006.190.07:59:38.47#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:59:38.47#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:59:38.47#ibcon#[25=AT02-07\r\n] 2006.190.07:59:38.47#ibcon#*before write, iclass 14, count 2 2006.190.07:59:38.47#ibcon#enter sib2, iclass 14, count 2 2006.190.07:59:38.47#ibcon#flushed, iclass 14, count 2 2006.190.07:59:38.47#ibcon#about to write, iclass 14, count 2 2006.190.07:59:38.47#ibcon#wrote, iclass 14, count 2 2006.190.07:59:38.47#ibcon#about to read 3, iclass 14, count 2 2006.190.07:59:38.50#ibcon#read 3, iclass 14, count 2 2006.190.07:59:38.50#ibcon#about to read 4, iclass 14, count 2 2006.190.07:59:38.50#ibcon#read 4, iclass 14, count 2 2006.190.07:59:38.50#ibcon#about to read 5, iclass 14, count 2 2006.190.07:59:38.50#ibcon#read 5, iclass 14, count 2 2006.190.07:59:38.50#ibcon#about to read 6, iclass 14, count 2 2006.190.07:59:38.50#ibcon#read 6, iclass 14, count 2 2006.190.07:59:38.50#ibcon#end of sib2, iclass 14, count 2 2006.190.07:59:38.50#ibcon#*after write, iclass 14, count 2 2006.190.07:59:38.50#ibcon#*before return 0, iclass 14, count 2 2006.190.07:59:38.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:38.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:38.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:59:38.51#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:38.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:38.52#abcon#<5=/05 2.2 3.6 24.531001012.0\r\n> 2006.190.07:59:38.53#abcon#{5=INTERFACE CLEAR} 2006.190.07:59:38.59#abcon#[5=S1D000X0/0*\r\n] 2006.190.07:59:38.62#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:38.62#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:38.62#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:59:38.62#ibcon#first serial, iclass 14, count 0 2006.190.07:59:38.62#ibcon#enter sib2, iclass 14, count 0 2006.190.07:59:38.62#ibcon#flushed, iclass 14, count 0 2006.190.07:59:38.62#ibcon#about to write, iclass 14, count 0 2006.190.07:59:38.62#ibcon#wrote, iclass 14, count 0 2006.190.07:59:38.62#ibcon#about to read 3, iclass 14, count 0 2006.190.07:59:38.64#ibcon#read 3, iclass 14, count 0 2006.190.07:59:38.64#ibcon#about to read 4, iclass 14, count 0 2006.190.07:59:38.64#ibcon#read 4, iclass 14, count 0 2006.190.07:59:38.64#ibcon#about to read 5, iclass 14, count 0 2006.190.07:59:38.64#ibcon#read 5, iclass 14, count 0 2006.190.07:59:38.64#ibcon#about to read 6, iclass 14, count 0 2006.190.07:59:38.64#ibcon#read 6, iclass 14, count 0 2006.190.07:59:38.64#ibcon#end of sib2, iclass 14, count 0 2006.190.07:59:38.64#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:59:38.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:59:38.64#ibcon#[25=USB\r\n] 2006.190.07:59:38.64#ibcon#*before write, iclass 14, count 0 2006.190.07:59:38.64#ibcon#enter sib2, iclass 14, count 0 2006.190.07:59:38.64#ibcon#flushed, iclass 14, count 0 2006.190.07:59:38.64#ibcon#about to write, iclass 14, count 0 2006.190.07:59:38.64#ibcon#wrote, iclass 14, count 0 2006.190.07:59:38.64#ibcon#about to read 3, iclass 14, count 0 2006.190.07:59:38.67#ibcon#read 3, iclass 14, count 0 2006.190.07:59:38.67#ibcon#about to read 4, iclass 14, count 0 2006.190.07:59:38.67#ibcon#read 4, iclass 14, count 0 2006.190.07:59:38.67#ibcon#about to read 5, iclass 14, count 0 2006.190.07:59:38.67#ibcon#read 5, iclass 14, count 0 2006.190.07:59:38.67#ibcon#about to read 6, iclass 14, count 0 2006.190.07:59:38.67#ibcon#read 6, iclass 14, count 0 2006.190.07:59:38.67#ibcon#end of sib2, iclass 14, count 0 2006.190.07:59:38.67#ibcon#*after write, iclass 14, count 0 2006.190.07:59:38.67#ibcon#*before return 0, iclass 14, count 0 2006.190.07:59:38.67#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:38.67#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:38.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:59:38.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:59:38.67$vc4f8/valo=3,672.99 2006.190.07:59:38.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:59:38.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:59:38.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:38.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:38.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:38.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:38.67#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:59:38.67#ibcon#first serial, iclass 20, count 0 2006.190.07:59:38.67#ibcon#enter sib2, iclass 20, count 0 2006.190.07:59:38.67#ibcon#flushed, iclass 20, count 0 2006.190.07:59:38.67#ibcon#about to write, iclass 20, count 0 2006.190.07:59:38.67#ibcon#wrote, iclass 20, count 0 2006.190.07:59:38.67#ibcon#about to read 3, iclass 20, count 0 2006.190.07:59:38.69#ibcon#read 3, iclass 20, count 0 2006.190.07:59:38.69#ibcon#about to read 4, iclass 20, count 0 2006.190.07:59:38.69#ibcon#read 4, iclass 20, count 0 2006.190.07:59:38.69#ibcon#about to read 5, iclass 20, count 0 2006.190.07:59:38.69#ibcon#read 5, iclass 20, count 0 2006.190.07:59:38.69#ibcon#about to read 6, iclass 20, count 0 2006.190.07:59:38.69#ibcon#read 6, iclass 20, count 0 2006.190.07:59:38.69#ibcon#end of sib2, iclass 20, count 0 2006.190.07:59:38.69#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:59:38.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:59:38.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.07:59:38.69#ibcon#*before write, iclass 20, count 0 2006.190.07:59:38.69#ibcon#enter sib2, iclass 20, count 0 2006.190.07:59:38.69#ibcon#flushed, iclass 20, count 0 2006.190.07:59:38.69#ibcon#about to write, iclass 20, count 0 2006.190.07:59:38.69#ibcon#wrote, iclass 20, count 0 2006.190.07:59:38.69#ibcon#about to read 3, iclass 20, count 0 2006.190.07:59:38.73#ibcon#read 3, iclass 20, count 0 2006.190.07:59:38.73#ibcon#about to read 4, iclass 20, count 0 2006.190.07:59:38.73#ibcon#read 4, iclass 20, count 0 2006.190.07:59:38.73#ibcon#about to read 5, iclass 20, count 0 2006.190.07:59:38.73#ibcon#read 5, iclass 20, count 0 2006.190.07:59:38.73#ibcon#about to read 6, iclass 20, count 0 2006.190.07:59:38.73#ibcon#read 6, iclass 20, count 0 2006.190.07:59:38.73#ibcon#end of sib2, iclass 20, count 0 2006.190.07:59:38.73#ibcon#*after write, iclass 20, count 0 2006.190.07:59:38.73#ibcon#*before return 0, iclass 20, count 0 2006.190.07:59:38.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:38.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:38.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:59:38.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:59:38.73$vc4f8/va=3,6 2006.190.07:59:38.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:59:38.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:59:38.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:38.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:38.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:38.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:38.79#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:59:38.79#ibcon#first serial, iclass 22, count 2 2006.190.07:59:38.79#ibcon#enter sib2, iclass 22, count 2 2006.190.07:59:38.79#ibcon#flushed, iclass 22, count 2 2006.190.07:59:38.79#ibcon#about to write, iclass 22, count 2 2006.190.07:59:38.79#ibcon#wrote, iclass 22, count 2 2006.190.07:59:38.79#ibcon#about to read 3, iclass 22, count 2 2006.190.07:59:38.81#ibcon#read 3, iclass 22, count 2 2006.190.07:59:38.81#ibcon#about to read 4, iclass 22, count 2 2006.190.07:59:38.81#ibcon#read 4, iclass 22, count 2 2006.190.07:59:38.81#ibcon#about to read 5, iclass 22, count 2 2006.190.07:59:38.81#ibcon#read 5, iclass 22, count 2 2006.190.07:59:38.81#ibcon#about to read 6, iclass 22, count 2 2006.190.07:59:38.81#ibcon#read 6, iclass 22, count 2 2006.190.07:59:38.81#ibcon#end of sib2, iclass 22, count 2 2006.190.07:59:38.81#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:59:38.81#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:59:38.81#ibcon#[25=AT03-06\r\n] 2006.190.07:59:38.81#ibcon#*before write, iclass 22, count 2 2006.190.07:59:38.81#ibcon#enter sib2, iclass 22, count 2 2006.190.07:59:38.81#ibcon#flushed, iclass 22, count 2 2006.190.07:59:38.81#ibcon#about to write, iclass 22, count 2 2006.190.07:59:38.81#ibcon#wrote, iclass 22, count 2 2006.190.07:59:38.81#ibcon#about to read 3, iclass 22, count 2 2006.190.07:59:38.84#ibcon#read 3, iclass 22, count 2 2006.190.07:59:38.84#ibcon#about to read 4, iclass 22, count 2 2006.190.07:59:38.84#ibcon#read 4, iclass 22, count 2 2006.190.07:59:38.84#ibcon#about to read 5, iclass 22, count 2 2006.190.07:59:38.84#ibcon#read 5, iclass 22, count 2 2006.190.07:59:38.84#ibcon#about to read 6, iclass 22, count 2 2006.190.07:59:38.84#ibcon#read 6, iclass 22, count 2 2006.190.07:59:38.84#ibcon#end of sib2, iclass 22, count 2 2006.190.07:59:38.84#ibcon#*after write, iclass 22, count 2 2006.190.07:59:38.84#ibcon#*before return 0, iclass 22, count 2 2006.190.07:59:38.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:38.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:38.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:59:38.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:38.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:38.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:38.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:38.96#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:59:38.96#ibcon#first serial, iclass 22, count 0 2006.190.07:59:38.96#ibcon#enter sib2, iclass 22, count 0 2006.190.07:59:38.96#ibcon#flushed, iclass 22, count 0 2006.190.07:59:38.96#ibcon#about to write, iclass 22, count 0 2006.190.07:59:38.96#ibcon#wrote, iclass 22, count 0 2006.190.07:59:38.96#ibcon#about to read 3, iclass 22, count 0 2006.190.07:59:38.98#ibcon#read 3, iclass 22, count 0 2006.190.07:59:38.98#ibcon#about to read 4, iclass 22, count 0 2006.190.07:59:38.98#ibcon#read 4, iclass 22, count 0 2006.190.07:59:38.98#ibcon#about to read 5, iclass 22, count 0 2006.190.07:59:38.98#ibcon#read 5, iclass 22, count 0 2006.190.07:59:38.98#ibcon#about to read 6, iclass 22, count 0 2006.190.07:59:38.98#ibcon#read 6, iclass 22, count 0 2006.190.07:59:38.98#ibcon#end of sib2, iclass 22, count 0 2006.190.07:59:38.98#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:59:38.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:59:38.98#ibcon#[25=USB\r\n] 2006.190.07:59:38.98#ibcon#*before write, iclass 22, count 0 2006.190.07:59:38.98#ibcon#enter sib2, iclass 22, count 0 2006.190.07:59:38.98#ibcon#flushed, iclass 22, count 0 2006.190.07:59:38.98#ibcon#about to write, iclass 22, count 0 2006.190.07:59:38.98#ibcon#wrote, iclass 22, count 0 2006.190.07:59:38.98#ibcon#about to read 3, iclass 22, count 0 2006.190.07:59:39.01#ibcon#read 3, iclass 22, count 0 2006.190.07:59:39.01#ibcon#about to read 4, iclass 22, count 0 2006.190.07:59:39.01#ibcon#read 4, iclass 22, count 0 2006.190.07:59:39.01#ibcon#about to read 5, iclass 22, count 0 2006.190.07:59:39.01#ibcon#read 5, iclass 22, count 0 2006.190.07:59:39.01#ibcon#about to read 6, iclass 22, count 0 2006.190.07:59:39.01#ibcon#read 6, iclass 22, count 0 2006.190.07:59:39.01#ibcon#end of sib2, iclass 22, count 0 2006.190.07:59:39.01#ibcon#*after write, iclass 22, count 0 2006.190.07:59:39.01#ibcon#*before return 0, iclass 22, count 0 2006.190.07:59:39.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:39.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:39.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:59:39.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:59:39.02$vc4f8/valo=4,832.99 2006.190.07:59:39.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.07:59:39.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.07:59:39.02#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:39.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:39.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:39.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:39.02#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:59:39.02#ibcon#first serial, iclass 24, count 0 2006.190.07:59:39.02#ibcon#enter sib2, iclass 24, count 0 2006.190.07:59:39.02#ibcon#flushed, iclass 24, count 0 2006.190.07:59:39.02#ibcon#about to write, iclass 24, count 0 2006.190.07:59:39.02#ibcon#wrote, iclass 24, count 0 2006.190.07:59:39.02#ibcon#about to read 3, iclass 24, count 0 2006.190.07:59:39.03#ibcon#read 3, iclass 24, count 0 2006.190.07:59:39.03#ibcon#about to read 4, iclass 24, count 0 2006.190.07:59:39.03#ibcon#read 4, iclass 24, count 0 2006.190.07:59:39.03#ibcon#about to read 5, iclass 24, count 0 2006.190.07:59:39.03#ibcon#read 5, iclass 24, count 0 2006.190.07:59:39.03#ibcon#about to read 6, iclass 24, count 0 2006.190.07:59:39.03#ibcon#read 6, iclass 24, count 0 2006.190.07:59:39.03#ibcon#end of sib2, iclass 24, count 0 2006.190.07:59:39.03#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:59:39.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:59:39.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.07:59:39.03#ibcon#*before write, iclass 24, count 0 2006.190.07:59:39.03#ibcon#enter sib2, iclass 24, count 0 2006.190.07:59:39.03#ibcon#flushed, iclass 24, count 0 2006.190.07:59:39.03#ibcon#about to write, iclass 24, count 0 2006.190.07:59:39.03#ibcon#wrote, iclass 24, count 0 2006.190.07:59:39.03#ibcon#about to read 3, iclass 24, count 0 2006.190.07:59:39.07#ibcon#read 3, iclass 24, count 0 2006.190.07:59:39.07#ibcon#about to read 4, iclass 24, count 0 2006.190.07:59:39.07#ibcon#read 4, iclass 24, count 0 2006.190.07:59:39.07#ibcon#about to read 5, iclass 24, count 0 2006.190.07:59:39.07#ibcon#read 5, iclass 24, count 0 2006.190.07:59:39.07#ibcon#about to read 6, iclass 24, count 0 2006.190.07:59:39.07#ibcon#read 6, iclass 24, count 0 2006.190.07:59:39.07#ibcon#end of sib2, iclass 24, count 0 2006.190.07:59:39.07#ibcon#*after write, iclass 24, count 0 2006.190.07:59:39.07#ibcon#*before return 0, iclass 24, count 0 2006.190.07:59:39.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:39.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:39.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:59:39.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:59:39.07$vc4f8/va=4,7 2006.190.07:59:39.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.07:59:39.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.07:59:39.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:39.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:39.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:39.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:39.13#ibcon#enter wrdev, iclass 26, count 2 2006.190.07:59:39.13#ibcon#first serial, iclass 26, count 2 2006.190.07:59:39.13#ibcon#enter sib2, iclass 26, count 2 2006.190.07:59:39.13#ibcon#flushed, iclass 26, count 2 2006.190.07:59:39.13#ibcon#about to write, iclass 26, count 2 2006.190.07:59:39.13#ibcon#wrote, iclass 26, count 2 2006.190.07:59:39.13#ibcon#about to read 3, iclass 26, count 2 2006.190.07:59:39.15#ibcon#read 3, iclass 26, count 2 2006.190.07:59:39.15#ibcon#about to read 4, iclass 26, count 2 2006.190.07:59:39.15#ibcon#read 4, iclass 26, count 2 2006.190.07:59:39.15#ibcon#about to read 5, iclass 26, count 2 2006.190.07:59:39.15#ibcon#read 5, iclass 26, count 2 2006.190.07:59:39.15#ibcon#about to read 6, iclass 26, count 2 2006.190.07:59:39.15#ibcon#read 6, iclass 26, count 2 2006.190.07:59:39.15#ibcon#end of sib2, iclass 26, count 2 2006.190.07:59:39.15#ibcon#*mode == 0, iclass 26, count 2 2006.190.07:59:39.15#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.07:59:39.15#ibcon#[25=AT04-07\r\n] 2006.190.07:59:39.15#ibcon#*before write, iclass 26, count 2 2006.190.07:59:39.15#ibcon#enter sib2, iclass 26, count 2 2006.190.07:59:39.15#ibcon#flushed, iclass 26, count 2 2006.190.07:59:39.15#ibcon#about to write, iclass 26, count 2 2006.190.07:59:39.15#ibcon#wrote, iclass 26, count 2 2006.190.07:59:39.15#ibcon#about to read 3, iclass 26, count 2 2006.190.07:59:39.18#ibcon#read 3, iclass 26, count 2 2006.190.07:59:39.18#ibcon#about to read 4, iclass 26, count 2 2006.190.07:59:39.18#ibcon#read 4, iclass 26, count 2 2006.190.07:59:39.18#ibcon#about to read 5, iclass 26, count 2 2006.190.07:59:39.18#ibcon#read 5, iclass 26, count 2 2006.190.07:59:39.18#ibcon#about to read 6, iclass 26, count 2 2006.190.07:59:39.18#ibcon#read 6, iclass 26, count 2 2006.190.07:59:39.18#ibcon#end of sib2, iclass 26, count 2 2006.190.07:59:39.18#ibcon#*after write, iclass 26, count 2 2006.190.07:59:39.18#ibcon#*before return 0, iclass 26, count 2 2006.190.07:59:39.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:39.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:39.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.07:59:39.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:39.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:39.30#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:39.30#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:39.30#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:59:39.30#ibcon#first serial, iclass 26, count 0 2006.190.07:59:39.30#ibcon#enter sib2, iclass 26, count 0 2006.190.07:59:39.30#ibcon#flushed, iclass 26, count 0 2006.190.07:59:39.30#ibcon#about to write, iclass 26, count 0 2006.190.07:59:39.30#ibcon#wrote, iclass 26, count 0 2006.190.07:59:39.30#ibcon#about to read 3, iclass 26, count 0 2006.190.07:59:39.32#ibcon#read 3, iclass 26, count 0 2006.190.07:59:39.32#ibcon#about to read 4, iclass 26, count 0 2006.190.07:59:39.32#ibcon#read 4, iclass 26, count 0 2006.190.07:59:39.32#ibcon#about to read 5, iclass 26, count 0 2006.190.07:59:39.32#ibcon#read 5, iclass 26, count 0 2006.190.07:59:39.32#ibcon#about to read 6, iclass 26, count 0 2006.190.07:59:39.32#ibcon#read 6, iclass 26, count 0 2006.190.07:59:39.32#ibcon#end of sib2, iclass 26, count 0 2006.190.07:59:39.32#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:59:39.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:59:39.32#ibcon#[25=USB\r\n] 2006.190.07:59:39.32#ibcon#*before write, iclass 26, count 0 2006.190.07:59:39.32#ibcon#enter sib2, iclass 26, count 0 2006.190.07:59:39.32#ibcon#flushed, iclass 26, count 0 2006.190.07:59:39.32#ibcon#about to write, iclass 26, count 0 2006.190.07:59:39.32#ibcon#wrote, iclass 26, count 0 2006.190.07:59:39.32#ibcon#about to read 3, iclass 26, count 0 2006.190.07:59:39.35#ibcon#read 3, iclass 26, count 0 2006.190.07:59:39.35#ibcon#about to read 4, iclass 26, count 0 2006.190.07:59:39.35#ibcon#read 4, iclass 26, count 0 2006.190.07:59:39.35#ibcon#about to read 5, iclass 26, count 0 2006.190.07:59:39.35#ibcon#read 5, iclass 26, count 0 2006.190.07:59:39.35#ibcon#about to read 6, iclass 26, count 0 2006.190.07:59:39.35#ibcon#read 6, iclass 26, count 0 2006.190.07:59:39.35#ibcon#end of sib2, iclass 26, count 0 2006.190.07:59:39.35#ibcon#*after write, iclass 26, count 0 2006.190.07:59:39.35#ibcon#*before return 0, iclass 26, count 0 2006.190.07:59:39.35#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:39.35#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:39.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:59:39.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:59:39.35$vc4f8/valo=5,652.99 2006.190.07:59:39.35#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:59:39.35#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:59:39.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:39.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:39.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:39.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:39.35#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:59:39.35#ibcon#first serial, iclass 28, count 0 2006.190.07:59:39.35#ibcon#enter sib2, iclass 28, count 0 2006.190.07:59:39.35#ibcon#flushed, iclass 28, count 0 2006.190.07:59:39.35#ibcon#about to write, iclass 28, count 0 2006.190.07:59:39.35#ibcon#wrote, iclass 28, count 0 2006.190.07:59:39.35#ibcon#about to read 3, iclass 28, count 0 2006.190.07:59:39.37#ibcon#read 3, iclass 28, count 0 2006.190.07:59:39.37#ibcon#about to read 4, iclass 28, count 0 2006.190.07:59:39.37#ibcon#read 4, iclass 28, count 0 2006.190.07:59:39.37#ibcon#about to read 5, iclass 28, count 0 2006.190.07:59:39.37#ibcon#read 5, iclass 28, count 0 2006.190.07:59:39.37#ibcon#about to read 6, iclass 28, count 0 2006.190.07:59:39.37#ibcon#read 6, iclass 28, count 0 2006.190.07:59:39.37#ibcon#end of sib2, iclass 28, count 0 2006.190.07:59:39.37#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:59:39.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:59:39.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.07:59:39.37#ibcon#*before write, iclass 28, count 0 2006.190.07:59:39.37#ibcon#enter sib2, iclass 28, count 0 2006.190.07:59:39.37#ibcon#flushed, iclass 28, count 0 2006.190.07:59:39.37#ibcon#about to write, iclass 28, count 0 2006.190.07:59:39.37#ibcon#wrote, iclass 28, count 0 2006.190.07:59:39.37#ibcon#about to read 3, iclass 28, count 0 2006.190.07:59:39.41#ibcon#read 3, iclass 28, count 0 2006.190.07:59:39.41#ibcon#about to read 4, iclass 28, count 0 2006.190.07:59:39.41#ibcon#read 4, iclass 28, count 0 2006.190.07:59:39.41#ibcon#about to read 5, iclass 28, count 0 2006.190.07:59:39.41#ibcon#read 5, iclass 28, count 0 2006.190.07:59:39.41#ibcon#about to read 6, iclass 28, count 0 2006.190.07:59:39.41#ibcon#read 6, iclass 28, count 0 2006.190.07:59:39.41#ibcon#end of sib2, iclass 28, count 0 2006.190.07:59:39.41#ibcon#*after write, iclass 28, count 0 2006.190.07:59:39.41#ibcon#*before return 0, iclass 28, count 0 2006.190.07:59:39.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:39.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:39.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:59:39.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:59:39.41$vc4f8/va=5,7 2006.190.07:59:39.41#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:59:39.41#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:59:39.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:39.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:39.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:39.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:39.47#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:59:39.47#ibcon#first serial, iclass 30, count 2 2006.190.07:59:39.47#ibcon#enter sib2, iclass 30, count 2 2006.190.07:59:39.47#ibcon#flushed, iclass 30, count 2 2006.190.07:59:39.47#ibcon#about to write, iclass 30, count 2 2006.190.07:59:39.47#ibcon#wrote, iclass 30, count 2 2006.190.07:59:39.47#ibcon#about to read 3, iclass 30, count 2 2006.190.07:59:39.49#ibcon#read 3, iclass 30, count 2 2006.190.07:59:39.49#ibcon#about to read 4, iclass 30, count 2 2006.190.07:59:39.49#ibcon#read 4, iclass 30, count 2 2006.190.07:59:39.49#ibcon#about to read 5, iclass 30, count 2 2006.190.07:59:39.49#ibcon#read 5, iclass 30, count 2 2006.190.07:59:39.49#ibcon#about to read 6, iclass 30, count 2 2006.190.07:59:39.49#ibcon#read 6, iclass 30, count 2 2006.190.07:59:39.49#ibcon#end of sib2, iclass 30, count 2 2006.190.07:59:39.49#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:59:39.49#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:59:39.49#ibcon#[25=AT05-07\r\n] 2006.190.07:59:39.49#ibcon#*before write, iclass 30, count 2 2006.190.07:59:39.49#ibcon#enter sib2, iclass 30, count 2 2006.190.07:59:39.49#ibcon#flushed, iclass 30, count 2 2006.190.07:59:39.49#ibcon#about to write, iclass 30, count 2 2006.190.07:59:39.49#ibcon#wrote, iclass 30, count 2 2006.190.07:59:39.49#ibcon#about to read 3, iclass 30, count 2 2006.190.07:59:39.52#ibcon#read 3, iclass 30, count 2 2006.190.07:59:39.52#ibcon#about to read 4, iclass 30, count 2 2006.190.07:59:39.52#ibcon#read 4, iclass 30, count 2 2006.190.07:59:39.52#ibcon#about to read 5, iclass 30, count 2 2006.190.07:59:39.52#ibcon#read 5, iclass 30, count 2 2006.190.07:59:39.52#ibcon#about to read 6, iclass 30, count 2 2006.190.07:59:39.52#ibcon#read 6, iclass 30, count 2 2006.190.07:59:39.52#ibcon#end of sib2, iclass 30, count 2 2006.190.07:59:39.52#ibcon#*after write, iclass 30, count 2 2006.190.07:59:39.52#ibcon#*before return 0, iclass 30, count 2 2006.190.07:59:39.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:39.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:39.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:59:39.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:39.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:39.64#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:39.64#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:39.64#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:59:39.64#ibcon#first serial, iclass 30, count 0 2006.190.07:59:39.64#ibcon#enter sib2, iclass 30, count 0 2006.190.07:59:39.64#ibcon#flushed, iclass 30, count 0 2006.190.07:59:39.64#ibcon#about to write, iclass 30, count 0 2006.190.07:59:39.64#ibcon#wrote, iclass 30, count 0 2006.190.07:59:39.64#ibcon#about to read 3, iclass 30, count 0 2006.190.07:59:39.66#ibcon#read 3, iclass 30, count 0 2006.190.07:59:39.66#ibcon#about to read 4, iclass 30, count 0 2006.190.07:59:39.66#ibcon#read 4, iclass 30, count 0 2006.190.07:59:39.66#ibcon#about to read 5, iclass 30, count 0 2006.190.07:59:39.66#ibcon#read 5, iclass 30, count 0 2006.190.07:59:39.66#ibcon#about to read 6, iclass 30, count 0 2006.190.07:59:39.66#ibcon#read 6, iclass 30, count 0 2006.190.07:59:39.66#ibcon#end of sib2, iclass 30, count 0 2006.190.07:59:39.66#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:59:39.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:59:39.66#ibcon#[25=USB\r\n] 2006.190.07:59:39.66#ibcon#*before write, iclass 30, count 0 2006.190.07:59:39.66#ibcon#enter sib2, iclass 30, count 0 2006.190.07:59:39.66#ibcon#flushed, iclass 30, count 0 2006.190.07:59:39.66#ibcon#about to write, iclass 30, count 0 2006.190.07:59:39.66#ibcon#wrote, iclass 30, count 0 2006.190.07:59:39.66#ibcon#about to read 3, iclass 30, count 0 2006.190.07:59:39.69#ibcon#read 3, iclass 30, count 0 2006.190.07:59:39.69#ibcon#about to read 4, iclass 30, count 0 2006.190.07:59:39.69#ibcon#read 4, iclass 30, count 0 2006.190.07:59:39.69#ibcon#about to read 5, iclass 30, count 0 2006.190.07:59:39.69#ibcon#read 5, iclass 30, count 0 2006.190.07:59:39.69#ibcon#about to read 6, iclass 30, count 0 2006.190.07:59:39.69#ibcon#read 6, iclass 30, count 0 2006.190.07:59:39.69#ibcon#end of sib2, iclass 30, count 0 2006.190.07:59:39.69#ibcon#*after write, iclass 30, count 0 2006.190.07:59:39.69#ibcon#*before return 0, iclass 30, count 0 2006.190.07:59:39.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:39.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:39.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:59:39.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:59:39.69$vc4f8/valo=6,772.99 2006.190.07:59:39.69#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:59:39.69#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:59:39.69#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:39.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:39.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:39.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:39.69#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:59:39.69#ibcon#first serial, iclass 32, count 0 2006.190.07:59:39.69#ibcon#enter sib2, iclass 32, count 0 2006.190.07:59:39.69#ibcon#flushed, iclass 32, count 0 2006.190.07:59:39.69#ibcon#about to write, iclass 32, count 0 2006.190.07:59:39.69#ibcon#wrote, iclass 32, count 0 2006.190.07:59:39.69#ibcon#about to read 3, iclass 32, count 0 2006.190.07:59:39.71#ibcon#read 3, iclass 32, count 0 2006.190.07:59:39.71#ibcon#about to read 4, iclass 32, count 0 2006.190.07:59:39.71#ibcon#read 4, iclass 32, count 0 2006.190.07:59:39.71#ibcon#about to read 5, iclass 32, count 0 2006.190.07:59:39.71#ibcon#read 5, iclass 32, count 0 2006.190.07:59:39.71#ibcon#about to read 6, iclass 32, count 0 2006.190.07:59:39.71#ibcon#read 6, iclass 32, count 0 2006.190.07:59:39.71#ibcon#end of sib2, iclass 32, count 0 2006.190.07:59:39.71#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:59:39.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:59:39.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.07:59:39.71#ibcon#*before write, iclass 32, count 0 2006.190.07:59:39.71#ibcon#enter sib2, iclass 32, count 0 2006.190.07:59:39.71#ibcon#flushed, iclass 32, count 0 2006.190.07:59:39.71#ibcon#about to write, iclass 32, count 0 2006.190.07:59:39.71#ibcon#wrote, iclass 32, count 0 2006.190.07:59:39.71#ibcon#about to read 3, iclass 32, count 0 2006.190.07:59:39.75#ibcon#read 3, iclass 32, count 0 2006.190.07:59:39.75#ibcon#about to read 4, iclass 32, count 0 2006.190.07:59:39.75#ibcon#read 4, iclass 32, count 0 2006.190.07:59:39.75#ibcon#about to read 5, iclass 32, count 0 2006.190.07:59:39.75#ibcon#read 5, iclass 32, count 0 2006.190.07:59:39.75#ibcon#about to read 6, iclass 32, count 0 2006.190.07:59:39.75#ibcon#read 6, iclass 32, count 0 2006.190.07:59:39.75#ibcon#end of sib2, iclass 32, count 0 2006.190.07:59:39.75#ibcon#*after write, iclass 32, count 0 2006.190.07:59:39.75#ibcon#*before return 0, iclass 32, count 0 2006.190.07:59:39.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:39.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:39.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:59:39.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:59:39.75$vc4f8/va=6,6 2006.190.07:59:39.75#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.07:59:39.75#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.07:59:39.75#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:39.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:59:39.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:59:39.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:59:39.81#ibcon#enter wrdev, iclass 34, count 2 2006.190.07:59:39.81#ibcon#first serial, iclass 34, count 2 2006.190.07:59:39.81#ibcon#enter sib2, iclass 34, count 2 2006.190.07:59:39.81#ibcon#flushed, iclass 34, count 2 2006.190.07:59:39.81#ibcon#about to write, iclass 34, count 2 2006.190.07:59:39.81#ibcon#wrote, iclass 34, count 2 2006.190.07:59:39.81#ibcon#about to read 3, iclass 34, count 2 2006.190.07:59:39.83#ibcon#read 3, iclass 34, count 2 2006.190.07:59:39.83#ibcon#about to read 4, iclass 34, count 2 2006.190.07:59:39.83#ibcon#read 4, iclass 34, count 2 2006.190.07:59:39.83#ibcon#about to read 5, iclass 34, count 2 2006.190.07:59:39.83#ibcon#read 5, iclass 34, count 2 2006.190.07:59:39.83#ibcon#about to read 6, iclass 34, count 2 2006.190.07:59:39.83#ibcon#read 6, iclass 34, count 2 2006.190.07:59:39.83#ibcon#end of sib2, iclass 34, count 2 2006.190.07:59:39.83#ibcon#*mode == 0, iclass 34, count 2 2006.190.07:59:39.83#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.07:59:39.83#ibcon#[25=AT06-06\r\n] 2006.190.07:59:39.83#ibcon#*before write, iclass 34, count 2 2006.190.07:59:39.83#ibcon#enter sib2, iclass 34, count 2 2006.190.07:59:39.83#ibcon#flushed, iclass 34, count 2 2006.190.07:59:39.83#ibcon#about to write, iclass 34, count 2 2006.190.07:59:39.83#ibcon#wrote, iclass 34, count 2 2006.190.07:59:39.83#ibcon#about to read 3, iclass 34, count 2 2006.190.07:59:39.86#ibcon#read 3, iclass 34, count 2 2006.190.07:59:39.86#ibcon#about to read 4, iclass 34, count 2 2006.190.07:59:39.86#ibcon#read 4, iclass 34, count 2 2006.190.07:59:39.86#ibcon#about to read 5, iclass 34, count 2 2006.190.07:59:39.86#ibcon#read 5, iclass 34, count 2 2006.190.07:59:39.86#ibcon#about to read 6, iclass 34, count 2 2006.190.07:59:39.86#ibcon#read 6, iclass 34, count 2 2006.190.07:59:39.86#ibcon#end of sib2, iclass 34, count 2 2006.190.07:59:39.86#ibcon#*after write, iclass 34, count 2 2006.190.07:59:39.86#ibcon#*before return 0, iclass 34, count 2 2006.190.07:59:39.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:59:39.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.07:59:39.86#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.07:59:39.86#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:39.86#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:59:39.98#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:59:39.98#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:59:39.98#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:59:39.98#ibcon#first serial, iclass 34, count 0 2006.190.07:59:39.98#ibcon#enter sib2, iclass 34, count 0 2006.190.07:59:39.98#ibcon#flushed, iclass 34, count 0 2006.190.07:59:39.98#ibcon#about to write, iclass 34, count 0 2006.190.07:59:39.98#ibcon#wrote, iclass 34, count 0 2006.190.07:59:39.98#ibcon#about to read 3, iclass 34, count 0 2006.190.07:59:40.00#ibcon#read 3, iclass 34, count 0 2006.190.07:59:40.00#ibcon#about to read 4, iclass 34, count 0 2006.190.07:59:40.00#ibcon#read 4, iclass 34, count 0 2006.190.07:59:40.00#ibcon#about to read 5, iclass 34, count 0 2006.190.07:59:40.00#ibcon#read 5, iclass 34, count 0 2006.190.07:59:40.00#ibcon#about to read 6, iclass 34, count 0 2006.190.07:59:40.00#ibcon#read 6, iclass 34, count 0 2006.190.07:59:40.00#ibcon#end of sib2, iclass 34, count 0 2006.190.07:59:40.00#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:59:40.00#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:59:40.00#ibcon#[25=USB\r\n] 2006.190.07:59:40.00#ibcon#*before write, iclass 34, count 0 2006.190.07:59:40.00#ibcon#enter sib2, iclass 34, count 0 2006.190.07:59:40.00#ibcon#flushed, iclass 34, count 0 2006.190.07:59:40.00#ibcon#about to write, iclass 34, count 0 2006.190.07:59:40.00#ibcon#wrote, iclass 34, count 0 2006.190.07:59:40.00#ibcon#about to read 3, iclass 34, count 0 2006.190.07:59:40.03#ibcon#read 3, iclass 34, count 0 2006.190.07:59:40.03#ibcon#about to read 4, iclass 34, count 0 2006.190.07:59:40.03#ibcon#read 4, iclass 34, count 0 2006.190.07:59:40.03#ibcon#about to read 5, iclass 34, count 0 2006.190.07:59:40.03#ibcon#read 5, iclass 34, count 0 2006.190.07:59:40.03#ibcon#about to read 6, iclass 34, count 0 2006.190.07:59:40.03#ibcon#read 6, iclass 34, count 0 2006.190.07:59:40.03#ibcon#end of sib2, iclass 34, count 0 2006.190.07:59:40.03#ibcon#*after write, iclass 34, count 0 2006.190.07:59:40.03#ibcon#*before return 0, iclass 34, count 0 2006.190.07:59:40.03#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:59:40.03#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.07:59:40.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:59:40.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:59:40.03$vc4f8/valo=7,832.99 2006.190.07:59:40.03#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.07:59:40.03#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.07:59:40.03#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:40.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:59:40.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:59:40.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:59:40.03#ibcon#enter wrdev, iclass 36, count 0 2006.190.07:59:40.03#ibcon#first serial, iclass 36, count 0 2006.190.07:59:40.03#ibcon#enter sib2, iclass 36, count 0 2006.190.07:59:40.03#ibcon#flushed, iclass 36, count 0 2006.190.07:59:40.03#ibcon#about to write, iclass 36, count 0 2006.190.07:59:40.03#ibcon#wrote, iclass 36, count 0 2006.190.07:59:40.03#ibcon#about to read 3, iclass 36, count 0 2006.190.07:59:40.05#ibcon#read 3, iclass 36, count 0 2006.190.07:59:40.05#ibcon#about to read 4, iclass 36, count 0 2006.190.07:59:40.05#ibcon#read 4, iclass 36, count 0 2006.190.07:59:40.05#ibcon#about to read 5, iclass 36, count 0 2006.190.07:59:40.05#ibcon#read 5, iclass 36, count 0 2006.190.07:59:40.05#ibcon#about to read 6, iclass 36, count 0 2006.190.07:59:40.05#ibcon#read 6, iclass 36, count 0 2006.190.07:59:40.05#ibcon#end of sib2, iclass 36, count 0 2006.190.07:59:40.05#ibcon#*mode == 0, iclass 36, count 0 2006.190.07:59:40.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.07:59:40.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.07:59:40.05#ibcon#*before write, iclass 36, count 0 2006.190.07:59:40.05#ibcon#enter sib2, iclass 36, count 0 2006.190.07:59:40.05#ibcon#flushed, iclass 36, count 0 2006.190.07:59:40.05#ibcon#about to write, iclass 36, count 0 2006.190.07:59:40.05#ibcon#wrote, iclass 36, count 0 2006.190.07:59:40.05#ibcon#about to read 3, iclass 36, count 0 2006.190.07:59:40.09#ibcon#read 3, iclass 36, count 0 2006.190.07:59:40.09#ibcon#about to read 4, iclass 36, count 0 2006.190.07:59:40.09#ibcon#read 4, iclass 36, count 0 2006.190.07:59:40.09#ibcon#about to read 5, iclass 36, count 0 2006.190.07:59:40.09#ibcon#read 5, iclass 36, count 0 2006.190.07:59:40.09#ibcon#about to read 6, iclass 36, count 0 2006.190.07:59:40.09#ibcon#read 6, iclass 36, count 0 2006.190.07:59:40.09#ibcon#end of sib2, iclass 36, count 0 2006.190.07:59:40.09#ibcon#*after write, iclass 36, count 0 2006.190.07:59:40.09#ibcon#*before return 0, iclass 36, count 0 2006.190.07:59:40.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:59:40.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.07:59:40.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.07:59:40.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.07:59:40.09$vc4f8/va=7,6 2006.190.07:59:40.09#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.07:59:40.09#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.07:59:40.09#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:40.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:59:40.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:59:40.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:59:40.15#ibcon#enter wrdev, iclass 38, count 2 2006.190.07:59:40.15#ibcon#first serial, iclass 38, count 2 2006.190.07:59:40.15#ibcon#enter sib2, iclass 38, count 2 2006.190.07:59:40.15#ibcon#flushed, iclass 38, count 2 2006.190.07:59:40.15#ibcon#about to write, iclass 38, count 2 2006.190.07:59:40.15#ibcon#wrote, iclass 38, count 2 2006.190.07:59:40.15#ibcon#about to read 3, iclass 38, count 2 2006.190.07:59:40.17#ibcon#read 3, iclass 38, count 2 2006.190.07:59:40.17#ibcon#about to read 4, iclass 38, count 2 2006.190.07:59:40.17#ibcon#read 4, iclass 38, count 2 2006.190.07:59:40.17#ibcon#about to read 5, iclass 38, count 2 2006.190.07:59:40.17#ibcon#read 5, iclass 38, count 2 2006.190.07:59:40.17#ibcon#about to read 6, iclass 38, count 2 2006.190.07:59:40.17#ibcon#read 6, iclass 38, count 2 2006.190.07:59:40.17#ibcon#end of sib2, iclass 38, count 2 2006.190.07:59:40.17#ibcon#*mode == 0, iclass 38, count 2 2006.190.07:59:40.17#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.07:59:40.17#ibcon#[25=AT07-06\r\n] 2006.190.07:59:40.17#ibcon#*before write, iclass 38, count 2 2006.190.07:59:40.17#ibcon#enter sib2, iclass 38, count 2 2006.190.07:59:40.17#ibcon#flushed, iclass 38, count 2 2006.190.07:59:40.17#ibcon#about to write, iclass 38, count 2 2006.190.07:59:40.17#ibcon#wrote, iclass 38, count 2 2006.190.07:59:40.17#ibcon#about to read 3, iclass 38, count 2 2006.190.07:59:40.20#ibcon#read 3, iclass 38, count 2 2006.190.07:59:40.20#ibcon#about to read 4, iclass 38, count 2 2006.190.07:59:40.20#ibcon#read 4, iclass 38, count 2 2006.190.07:59:40.20#ibcon#about to read 5, iclass 38, count 2 2006.190.07:59:40.20#ibcon#read 5, iclass 38, count 2 2006.190.07:59:40.20#ibcon#about to read 6, iclass 38, count 2 2006.190.07:59:40.20#ibcon#read 6, iclass 38, count 2 2006.190.07:59:40.20#ibcon#end of sib2, iclass 38, count 2 2006.190.07:59:40.20#ibcon#*after write, iclass 38, count 2 2006.190.07:59:40.20#ibcon#*before return 0, iclass 38, count 2 2006.190.07:59:40.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:59:40.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.07:59:40.20#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.07:59:40.20#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:40.20#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:59:40.32#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:59:40.32#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:59:40.32#ibcon#enter wrdev, iclass 38, count 0 2006.190.07:59:40.32#ibcon#first serial, iclass 38, count 0 2006.190.07:59:40.32#ibcon#enter sib2, iclass 38, count 0 2006.190.07:59:40.32#ibcon#flushed, iclass 38, count 0 2006.190.07:59:40.32#ibcon#about to write, iclass 38, count 0 2006.190.07:59:40.32#ibcon#wrote, iclass 38, count 0 2006.190.07:59:40.32#ibcon#about to read 3, iclass 38, count 0 2006.190.07:59:40.34#ibcon#read 3, iclass 38, count 0 2006.190.07:59:40.34#ibcon#about to read 4, iclass 38, count 0 2006.190.07:59:40.34#ibcon#read 4, iclass 38, count 0 2006.190.07:59:40.34#ibcon#about to read 5, iclass 38, count 0 2006.190.07:59:40.34#ibcon#read 5, iclass 38, count 0 2006.190.07:59:40.34#ibcon#about to read 6, iclass 38, count 0 2006.190.07:59:40.34#ibcon#read 6, iclass 38, count 0 2006.190.07:59:40.34#ibcon#end of sib2, iclass 38, count 0 2006.190.07:59:40.34#ibcon#*mode == 0, iclass 38, count 0 2006.190.07:59:40.34#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.07:59:40.34#ibcon#[25=USB\r\n] 2006.190.07:59:40.34#ibcon#*before write, iclass 38, count 0 2006.190.07:59:40.34#ibcon#enter sib2, iclass 38, count 0 2006.190.07:59:40.34#ibcon#flushed, iclass 38, count 0 2006.190.07:59:40.34#ibcon#about to write, iclass 38, count 0 2006.190.07:59:40.34#ibcon#wrote, iclass 38, count 0 2006.190.07:59:40.34#ibcon#about to read 3, iclass 38, count 0 2006.190.07:59:40.37#ibcon#read 3, iclass 38, count 0 2006.190.07:59:40.37#ibcon#about to read 4, iclass 38, count 0 2006.190.07:59:40.37#ibcon#read 4, iclass 38, count 0 2006.190.07:59:40.37#ibcon#about to read 5, iclass 38, count 0 2006.190.07:59:40.37#ibcon#read 5, iclass 38, count 0 2006.190.07:59:40.37#ibcon#about to read 6, iclass 38, count 0 2006.190.07:59:40.37#ibcon#read 6, iclass 38, count 0 2006.190.07:59:40.37#ibcon#end of sib2, iclass 38, count 0 2006.190.07:59:40.37#ibcon#*after write, iclass 38, count 0 2006.190.07:59:40.37#ibcon#*before return 0, iclass 38, count 0 2006.190.07:59:40.37#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:59:40.37#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.07:59:40.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.07:59:40.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.07:59:40.37$vc4f8/valo=8,852.99 2006.190.07:59:40.37#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.07:59:40.37#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.07:59:40.37#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:40.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:59:40.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:59:40.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:59:40.37#ibcon#enter wrdev, iclass 40, count 0 2006.190.07:59:40.37#ibcon#first serial, iclass 40, count 0 2006.190.07:59:40.37#ibcon#enter sib2, iclass 40, count 0 2006.190.07:59:40.37#ibcon#flushed, iclass 40, count 0 2006.190.07:59:40.37#ibcon#about to write, iclass 40, count 0 2006.190.07:59:40.37#ibcon#wrote, iclass 40, count 0 2006.190.07:59:40.37#ibcon#about to read 3, iclass 40, count 0 2006.190.07:59:40.39#ibcon#read 3, iclass 40, count 0 2006.190.07:59:40.39#ibcon#about to read 4, iclass 40, count 0 2006.190.07:59:40.39#ibcon#read 4, iclass 40, count 0 2006.190.07:59:40.39#ibcon#about to read 5, iclass 40, count 0 2006.190.07:59:40.39#ibcon#read 5, iclass 40, count 0 2006.190.07:59:40.39#ibcon#about to read 6, iclass 40, count 0 2006.190.07:59:40.39#ibcon#read 6, iclass 40, count 0 2006.190.07:59:40.39#ibcon#end of sib2, iclass 40, count 0 2006.190.07:59:40.39#ibcon#*mode == 0, iclass 40, count 0 2006.190.07:59:40.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.07:59:40.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.07:59:40.39#ibcon#*before write, iclass 40, count 0 2006.190.07:59:40.39#ibcon#enter sib2, iclass 40, count 0 2006.190.07:59:40.39#ibcon#flushed, iclass 40, count 0 2006.190.07:59:40.39#ibcon#about to write, iclass 40, count 0 2006.190.07:59:40.39#ibcon#wrote, iclass 40, count 0 2006.190.07:59:40.39#ibcon#about to read 3, iclass 40, count 0 2006.190.07:59:40.43#ibcon#read 3, iclass 40, count 0 2006.190.07:59:40.43#ibcon#about to read 4, iclass 40, count 0 2006.190.07:59:40.43#ibcon#read 4, iclass 40, count 0 2006.190.07:59:40.43#ibcon#about to read 5, iclass 40, count 0 2006.190.07:59:40.43#ibcon#read 5, iclass 40, count 0 2006.190.07:59:40.43#ibcon#about to read 6, iclass 40, count 0 2006.190.07:59:40.43#ibcon#read 6, iclass 40, count 0 2006.190.07:59:40.43#ibcon#end of sib2, iclass 40, count 0 2006.190.07:59:40.43#ibcon#*after write, iclass 40, count 0 2006.190.07:59:40.43#ibcon#*before return 0, iclass 40, count 0 2006.190.07:59:40.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:59:40.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.07:59:40.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.07:59:40.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.07:59:40.43$vc4f8/va=8,6 2006.190.07:59:40.43#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.07:59:40.43#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.07:59:40.43#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:40.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:59:40.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:59:40.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:59:40.49#ibcon#enter wrdev, iclass 4, count 2 2006.190.07:59:40.49#ibcon#first serial, iclass 4, count 2 2006.190.07:59:40.49#ibcon#enter sib2, iclass 4, count 2 2006.190.07:59:40.49#ibcon#flushed, iclass 4, count 2 2006.190.07:59:40.49#ibcon#about to write, iclass 4, count 2 2006.190.07:59:40.49#ibcon#wrote, iclass 4, count 2 2006.190.07:59:40.49#ibcon#about to read 3, iclass 4, count 2 2006.190.07:59:40.52#ibcon#read 3, iclass 4, count 2 2006.190.07:59:40.52#ibcon#about to read 4, iclass 4, count 2 2006.190.07:59:40.52#ibcon#read 4, iclass 4, count 2 2006.190.07:59:40.52#ibcon#about to read 5, iclass 4, count 2 2006.190.07:59:40.52#ibcon#read 5, iclass 4, count 2 2006.190.07:59:40.52#ibcon#about to read 6, iclass 4, count 2 2006.190.07:59:40.52#ibcon#read 6, iclass 4, count 2 2006.190.07:59:40.52#ibcon#end of sib2, iclass 4, count 2 2006.190.07:59:40.52#ibcon#*mode == 0, iclass 4, count 2 2006.190.07:59:40.52#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.07:59:40.52#ibcon#[25=AT08-06\r\n] 2006.190.07:59:40.52#ibcon#*before write, iclass 4, count 2 2006.190.07:59:40.52#ibcon#enter sib2, iclass 4, count 2 2006.190.07:59:40.52#ibcon#flushed, iclass 4, count 2 2006.190.07:59:40.52#ibcon#about to write, iclass 4, count 2 2006.190.07:59:40.52#ibcon#wrote, iclass 4, count 2 2006.190.07:59:40.52#ibcon#about to read 3, iclass 4, count 2 2006.190.07:59:40.54#ibcon#read 3, iclass 4, count 2 2006.190.07:59:40.54#ibcon#about to read 4, iclass 4, count 2 2006.190.07:59:40.54#ibcon#read 4, iclass 4, count 2 2006.190.07:59:40.54#ibcon#about to read 5, iclass 4, count 2 2006.190.07:59:40.54#ibcon#read 5, iclass 4, count 2 2006.190.07:59:40.54#ibcon#about to read 6, iclass 4, count 2 2006.190.07:59:40.54#ibcon#read 6, iclass 4, count 2 2006.190.07:59:40.54#ibcon#end of sib2, iclass 4, count 2 2006.190.07:59:40.54#ibcon#*after write, iclass 4, count 2 2006.190.07:59:40.54#ibcon#*before return 0, iclass 4, count 2 2006.190.07:59:40.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:59:40.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.07:59:40.54#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.07:59:40.54#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:40.54#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:59:40.66#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:59:40.66#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:59:40.66#ibcon#enter wrdev, iclass 4, count 0 2006.190.07:59:40.66#ibcon#first serial, iclass 4, count 0 2006.190.07:59:40.66#ibcon#enter sib2, iclass 4, count 0 2006.190.07:59:40.66#ibcon#flushed, iclass 4, count 0 2006.190.07:59:40.66#ibcon#about to write, iclass 4, count 0 2006.190.07:59:40.66#ibcon#wrote, iclass 4, count 0 2006.190.07:59:40.66#ibcon#about to read 3, iclass 4, count 0 2006.190.07:59:40.68#ibcon#read 3, iclass 4, count 0 2006.190.07:59:40.68#ibcon#about to read 4, iclass 4, count 0 2006.190.07:59:40.68#ibcon#read 4, iclass 4, count 0 2006.190.07:59:40.68#ibcon#about to read 5, iclass 4, count 0 2006.190.07:59:40.68#ibcon#read 5, iclass 4, count 0 2006.190.07:59:40.68#ibcon#about to read 6, iclass 4, count 0 2006.190.07:59:40.68#ibcon#read 6, iclass 4, count 0 2006.190.07:59:40.68#ibcon#end of sib2, iclass 4, count 0 2006.190.07:59:40.68#ibcon#*mode == 0, iclass 4, count 0 2006.190.07:59:40.68#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.07:59:40.68#ibcon#[25=USB\r\n] 2006.190.07:59:40.68#ibcon#*before write, iclass 4, count 0 2006.190.07:59:40.68#ibcon#enter sib2, iclass 4, count 0 2006.190.07:59:40.68#ibcon#flushed, iclass 4, count 0 2006.190.07:59:40.68#ibcon#about to write, iclass 4, count 0 2006.190.07:59:40.68#ibcon#wrote, iclass 4, count 0 2006.190.07:59:40.68#ibcon#about to read 3, iclass 4, count 0 2006.190.07:59:40.71#ibcon#read 3, iclass 4, count 0 2006.190.07:59:40.71#ibcon#about to read 4, iclass 4, count 0 2006.190.07:59:40.71#ibcon#read 4, iclass 4, count 0 2006.190.07:59:40.71#ibcon#about to read 5, iclass 4, count 0 2006.190.07:59:40.71#ibcon#read 5, iclass 4, count 0 2006.190.07:59:40.71#ibcon#about to read 6, iclass 4, count 0 2006.190.07:59:40.71#ibcon#read 6, iclass 4, count 0 2006.190.07:59:40.71#ibcon#end of sib2, iclass 4, count 0 2006.190.07:59:40.71#ibcon#*after write, iclass 4, count 0 2006.190.07:59:40.71#ibcon#*before return 0, iclass 4, count 0 2006.190.07:59:40.71#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:59:40.71#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.07:59:40.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.07:59:40.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.07:59:40.71$vc4f8/vblo=1,632.99 2006.190.07:59:40.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.07:59:40.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.07:59:40.71#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:40.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:40.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:40.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:40.71#ibcon#enter wrdev, iclass 6, count 0 2006.190.07:59:40.71#ibcon#first serial, iclass 6, count 0 2006.190.07:59:40.71#ibcon#enter sib2, iclass 6, count 0 2006.190.07:59:40.71#ibcon#flushed, iclass 6, count 0 2006.190.07:59:40.71#ibcon#about to write, iclass 6, count 0 2006.190.07:59:40.71#ibcon#wrote, iclass 6, count 0 2006.190.07:59:40.71#ibcon#about to read 3, iclass 6, count 0 2006.190.07:59:40.73#ibcon#read 3, iclass 6, count 0 2006.190.07:59:40.73#ibcon#about to read 4, iclass 6, count 0 2006.190.07:59:40.73#ibcon#read 4, iclass 6, count 0 2006.190.07:59:40.73#ibcon#about to read 5, iclass 6, count 0 2006.190.07:59:40.73#ibcon#read 5, iclass 6, count 0 2006.190.07:59:40.73#ibcon#about to read 6, iclass 6, count 0 2006.190.07:59:40.73#ibcon#read 6, iclass 6, count 0 2006.190.07:59:40.73#ibcon#end of sib2, iclass 6, count 0 2006.190.07:59:40.73#ibcon#*mode == 0, iclass 6, count 0 2006.190.07:59:40.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.07:59:40.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.07:59:40.73#ibcon#*before write, iclass 6, count 0 2006.190.07:59:40.73#ibcon#enter sib2, iclass 6, count 0 2006.190.07:59:40.73#ibcon#flushed, iclass 6, count 0 2006.190.07:59:40.73#ibcon#about to write, iclass 6, count 0 2006.190.07:59:40.73#ibcon#wrote, iclass 6, count 0 2006.190.07:59:40.73#ibcon#about to read 3, iclass 6, count 0 2006.190.07:59:40.77#ibcon#read 3, iclass 6, count 0 2006.190.07:59:40.77#ibcon#about to read 4, iclass 6, count 0 2006.190.07:59:40.77#ibcon#read 4, iclass 6, count 0 2006.190.07:59:40.77#ibcon#about to read 5, iclass 6, count 0 2006.190.07:59:40.77#ibcon#read 5, iclass 6, count 0 2006.190.07:59:40.77#ibcon#about to read 6, iclass 6, count 0 2006.190.07:59:40.77#ibcon#read 6, iclass 6, count 0 2006.190.07:59:40.77#ibcon#end of sib2, iclass 6, count 0 2006.190.07:59:40.77#ibcon#*after write, iclass 6, count 0 2006.190.07:59:40.77#ibcon#*before return 0, iclass 6, count 0 2006.190.07:59:40.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:40.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.07:59:40.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.07:59:40.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.07:59:40.77$vc4f8/vb=1,4 2006.190.07:59:40.77#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.07:59:40.77#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.07:59:40.77#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:40.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:40.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:40.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:40.77#ibcon#enter wrdev, iclass 10, count 2 2006.190.07:59:40.77#ibcon#first serial, iclass 10, count 2 2006.190.07:59:40.77#ibcon#enter sib2, iclass 10, count 2 2006.190.07:59:40.77#ibcon#flushed, iclass 10, count 2 2006.190.07:59:40.77#ibcon#about to write, iclass 10, count 2 2006.190.07:59:40.77#ibcon#wrote, iclass 10, count 2 2006.190.07:59:40.77#ibcon#about to read 3, iclass 10, count 2 2006.190.07:59:40.79#ibcon#read 3, iclass 10, count 2 2006.190.07:59:40.79#ibcon#about to read 4, iclass 10, count 2 2006.190.07:59:40.79#ibcon#read 4, iclass 10, count 2 2006.190.07:59:40.79#ibcon#about to read 5, iclass 10, count 2 2006.190.07:59:40.79#ibcon#read 5, iclass 10, count 2 2006.190.07:59:40.79#ibcon#about to read 6, iclass 10, count 2 2006.190.07:59:40.79#ibcon#read 6, iclass 10, count 2 2006.190.07:59:40.79#ibcon#end of sib2, iclass 10, count 2 2006.190.07:59:40.79#ibcon#*mode == 0, iclass 10, count 2 2006.190.07:59:40.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.07:59:40.79#ibcon#[27=AT01-04\r\n] 2006.190.07:59:40.79#ibcon#*before write, iclass 10, count 2 2006.190.07:59:40.79#ibcon#enter sib2, iclass 10, count 2 2006.190.07:59:40.79#ibcon#flushed, iclass 10, count 2 2006.190.07:59:40.79#ibcon#about to write, iclass 10, count 2 2006.190.07:59:40.79#ibcon#wrote, iclass 10, count 2 2006.190.07:59:40.79#ibcon#about to read 3, iclass 10, count 2 2006.190.07:59:40.82#ibcon#read 3, iclass 10, count 2 2006.190.07:59:40.82#ibcon#about to read 4, iclass 10, count 2 2006.190.07:59:40.82#ibcon#read 4, iclass 10, count 2 2006.190.07:59:40.82#ibcon#about to read 5, iclass 10, count 2 2006.190.07:59:40.82#ibcon#read 5, iclass 10, count 2 2006.190.07:59:40.82#ibcon#about to read 6, iclass 10, count 2 2006.190.07:59:40.82#ibcon#read 6, iclass 10, count 2 2006.190.07:59:40.82#ibcon#end of sib2, iclass 10, count 2 2006.190.07:59:40.82#ibcon#*after write, iclass 10, count 2 2006.190.07:59:40.82#ibcon#*before return 0, iclass 10, count 2 2006.190.07:59:40.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:40.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.07:59:40.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.07:59:40.82#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:40.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:40.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:40.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:40.94#ibcon#enter wrdev, iclass 10, count 0 2006.190.07:59:40.94#ibcon#first serial, iclass 10, count 0 2006.190.07:59:40.94#ibcon#enter sib2, iclass 10, count 0 2006.190.07:59:40.94#ibcon#flushed, iclass 10, count 0 2006.190.07:59:40.94#ibcon#about to write, iclass 10, count 0 2006.190.07:59:40.94#ibcon#wrote, iclass 10, count 0 2006.190.07:59:40.94#ibcon#about to read 3, iclass 10, count 0 2006.190.07:59:40.96#ibcon#read 3, iclass 10, count 0 2006.190.07:59:40.96#ibcon#about to read 4, iclass 10, count 0 2006.190.07:59:40.96#ibcon#read 4, iclass 10, count 0 2006.190.07:59:40.96#ibcon#about to read 5, iclass 10, count 0 2006.190.07:59:40.96#ibcon#read 5, iclass 10, count 0 2006.190.07:59:40.96#ibcon#about to read 6, iclass 10, count 0 2006.190.07:59:40.96#ibcon#read 6, iclass 10, count 0 2006.190.07:59:40.96#ibcon#end of sib2, iclass 10, count 0 2006.190.07:59:40.96#ibcon#*mode == 0, iclass 10, count 0 2006.190.07:59:40.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.07:59:40.96#ibcon#[27=USB\r\n] 2006.190.07:59:40.96#ibcon#*before write, iclass 10, count 0 2006.190.07:59:40.96#ibcon#enter sib2, iclass 10, count 0 2006.190.07:59:40.96#ibcon#flushed, iclass 10, count 0 2006.190.07:59:40.96#ibcon#about to write, iclass 10, count 0 2006.190.07:59:40.96#ibcon#wrote, iclass 10, count 0 2006.190.07:59:40.96#ibcon#about to read 3, iclass 10, count 0 2006.190.07:59:40.99#ibcon#read 3, iclass 10, count 0 2006.190.07:59:40.99#ibcon#about to read 4, iclass 10, count 0 2006.190.07:59:40.99#ibcon#read 4, iclass 10, count 0 2006.190.07:59:40.99#ibcon#about to read 5, iclass 10, count 0 2006.190.07:59:40.99#ibcon#read 5, iclass 10, count 0 2006.190.07:59:40.99#ibcon#about to read 6, iclass 10, count 0 2006.190.07:59:40.99#ibcon#read 6, iclass 10, count 0 2006.190.07:59:40.99#ibcon#end of sib2, iclass 10, count 0 2006.190.07:59:40.99#ibcon#*after write, iclass 10, count 0 2006.190.07:59:40.99#ibcon#*before return 0, iclass 10, count 0 2006.190.07:59:40.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:40.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.07:59:40.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.07:59:40.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.07:59:40.99$vc4f8/vblo=2,640.99 2006.190.07:59:40.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.07:59:40.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.07:59:40.99#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:40.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:40.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:40.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:40.99#ibcon#enter wrdev, iclass 12, count 0 2006.190.07:59:40.99#ibcon#first serial, iclass 12, count 0 2006.190.07:59:40.99#ibcon#enter sib2, iclass 12, count 0 2006.190.07:59:40.99#ibcon#flushed, iclass 12, count 0 2006.190.07:59:40.99#ibcon#about to write, iclass 12, count 0 2006.190.07:59:40.99#ibcon#wrote, iclass 12, count 0 2006.190.07:59:40.99#ibcon#about to read 3, iclass 12, count 0 2006.190.07:59:41.01#ibcon#read 3, iclass 12, count 0 2006.190.07:59:41.01#ibcon#about to read 4, iclass 12, count 0 2006.190.07:59:41.01#ibcon#read 4, iclass 12, count 0 2006.190.07:59:41.01#ibcon#about to read 5, iclass 12, count 0 2006.190.07:59:41.01#ibcon#read 5, iclass 12, count 0 2006.190.07:59:41.01#ibcon#about to read 6, iclass 12, count 0 2006.190.07:59:41.01#ibcon#read 6, iclass 12, count 0 2006.190.07:59:41.01#ibcon#end of sib2, iclass 12, count 0 2006.190.07:59:41.01#ibcon#*mode == 0, iclass 12, count 0 2006.190.07:59:41.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.07:59:41.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.07:59:41.01#ibcon#*before write, iclass 12, count 0 2006.190.07:59:41.01#ibcon#enter sib2, iclass 12, count 0 2006.190.07:59:41.01#ibcon#flushed, iclass 12, count 0 2006.190.07:59:41.01#ibcon#about to write, iclass 12, count 0 2006.190.07:59:41.01#ibcon#wrote, iclass 12, count 0 2006.190.07:59:41.01#ibcon#about to read 3, iclass 12, count 0 2006.190.07:59:41.05#ibcon#read 3, iclass 12, count 0 2006.190.07:59:41.05#ibcon#about to read 4, iclass 12, count 0 2006.190.07:59:41.05#ibcon#read 4, iclass 12, count 0 2006.190.07:59:41.05#ibcon#about to read 5, iclass 12, count 0 2006.190.07:59:41.05#ibcon#read 5, iclass 12, count 0 2006.190.07:59:41.05#ibcon#about to read 6, iclass 12, count 0 2006.190.07:59:41.05#ibcon#read 6, iclass 12, count 0 2006.190.07:59:41.05#ibcon#end of sib2, iclass 12, count 0 2006.190.07:59:41.05#ibcon#*after write, iclass 12, count 0 2006.190.07:59:41.05#ibcon#*before return 0, iclass 12, count 0 2006.190.07:59:41.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:41.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.07:59:41.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.07:59:41.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.07:59:41.05$vc4f8/vb=2,4 2006.190.07:59:41.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.07:59:41.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.07:59:41.05#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:41.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:41.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:41.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:41.11#ibcon#enter wrdev, iclass 14, count 2 2006.190.07:59:41.11#ibcon#first serial, iclass 14, count 2 2006.190.07:59:41.11#ibcon#enter sib2, iclass 14, count 2 2006.190.07:59:41.11#ibcon#flushed, iclass 14, count 2 2006.190.07:59:41.11#ibcon#about to write, iclass 14, count 2 2006.190.07:59:41.11#ibcon#wrote, iclass 14, count 2 2006.190.07:59:41.11#ibcon#about to read 3, iclass 14, count 2 2006.190.07:59:41.13#ibcon#read 3, iclass 14, count 2 2006.190.07:59:41.13#ibcon#about to read 4, iclass 14, count 2 2006.190.07:59:41.13#ibcon#read 4, iclass 14, count 2 2006.190.07:59:41.13#ibcon#about to read 5, iclass 14, count 2 2006.190.07:59:41.13#ibcon#read 5, iclass 14, count 2 2006.190.07:59:41.13#ibcon#about to read 6, iclass 14, count 2 2006.190.07:59:41.13#ibcon#read 6, iclass 14, count 2 2006.190.07:59:41.13#ibcon#end of sib2, iclass 14, count 2 2006.190.07:59:41.13#ibcon#*mode == 0, iclass 14, count 2 2006.190.07:59:41.13#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.07:59:41.13#ibcon#[27=AT02-04\r\n] 2006.190.07:59:41.13#ibcon#*before write, iclass 14, count 2 2006.190.07:59:41.13#ibcon#enter sib2, iclass 14, count 2 2006.190.07:59:41.13#ibcon#flushed, iclass 14, count 2 2006.190.07:59:41.13#ibcon#about to write, iclass 14, count 2 2006.190.07:59:41.13#ibcon#wrote, iclass 14, count 2 2006.190.07:59:41.13#ibcon#about to read 3, iclass 14, count 2 2006.190.07:59:41.16#ibcon#read 3, iclass 14, count 2 2006.190.07:59:41.16#ibcon#about to read 4, iclass 14, count 2 2006.190.07:59:41.16#ibcon#read 4, iclass 14, count 2 2006.190.07:59:41.16#ibcon#about to read 5, iclass 14, count 2 2006.190.07:59:41.16#ibcon#read 5, iclass 14, count 2 2006.190.07:59:41.16#ibcon#about to read 6, iclass 14, count 2 2006.190.07:59:41.16#ibcon#read 6, iclass 14, count 2 2006.190.07:59:41.16#ibcon#end of sib2, iclass 14, count 2 2006.190.07:59:41.16#ibcon#*after write, iclass 14, count 2 2006.190.07:59:41.16#ibcon#*before return 0, iclass 14, count 2 2006.190.07:59:41.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:41.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.07:59:41.16#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.07:59:41.16#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:41.16#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:41.28#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:41.28#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:41.28#ibcon#enter wrdev, iclass 14, count 0 2006.190.07:59:41.28#ibcon#first serial, iclass 14, count 0 2006.190.07:59:41.28#ibcon#enter sib2, iclass 14, count 0 2006.190.07:59:41.28#ibcon#flushed, iclass 14, count 0 2006.190.07:59:41.28#ibcon#about to write, iclass 14, count 0 2006.190.07:59:41.28#ibcon#wrote, iclass 14, count 0 2006.190.07:59:41.28#ibcon#about to read 3, iclass 14, count 0 2006.190.07:59:41.30#ibcon#read 3, iclass 14, count 0 2006.190.07:59:41.30#ibcon#about to read 4, iclass 14, count 0 2006.190.07:59:41.30#ibcon#read 4, iclass 14, count 0 2006.190.07:59:41.30#ibcon#about to read 5, iclass 14, count 0 2006.190.07:59:41.30#ibcon#read 5, iclass 14, count 0 2006.190.07:59:41.30#ibcon#about to read 6, iclass 14, count 0 2006.190.07:59:41.30#ibcon#read 6, iclass 14, count 0 2006.190.07:59:41.30#ibcon#end of sib2, iclass 14, count 0 2006.190.07:59:41.30#ibcon#*mode == 0, iclass 14, count 0 2006.190.07:59:41.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.07:59:41.30#ibcon#[27=USB\r\n] 2006.190.07:59:41.30#ibcon#*before write, iclass 14, count 0 2006.190.07:59:41.30#ibcon#enter sib2, iclass 14, count 0 2006.190.07:59:41.30#ibcon#flushed, iclass 14, count 0 2006.190.07:59:41.30#ibcon#about to write, iclass 14, count 0 2006.190.07:59:41.30#ibcon#wrote, iclass 14, count 0 2006.190.07:59:41.30#ibcon#about to read 3, iclass 14, count 0 2006.190.07:59:41.33#ibcon#read 3, iclass 14, count 0 2006.190.07:59:41.33#ibcon#about to read 4, iclass 14, count 0 2006.190.07:59:41.33#ibcon#read 4, iclass 14, count 0 2006.190.07:59:41.33#ibcon#about to read 5, iclass 14, count 0 2006.190.07:59:41.33#ibcon#read 5, iclass 14, count 0 2006.190.07:59:41.33#ibcon#about to read 6, iclass 14, count 0 2006.190.07:59:41.33#ibcon#read 6, iclass 14, count 0 2006.190.07:59:41.33#ibcon#end of sib2, iclass 14, count 0 2006.190.07:59:41.33#ibcon#*after write, iclass 14, count 0 2006.190.07:59:41.33#ibcon#*before return 0, iclass 14, count 0 2006.190.07:59:41.33#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:41.33#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.07:59:41.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.07:59:41.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.07:59:41.33$vc4f8/vblo=3,656.99 2006.190.07:59:41.33#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.07:59:41.33#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.07:59:41.33#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:41.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:59:41.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:59:41.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:59:41.33#ibcon#enter wrdev, iclass 16, count 0 2006.190.07:59:41.33#ibcon#first serial, iclass 16, count 0 2006.190.07:59:41.33#ibcon#enter sib2, iclass 16, count 0 2006.190.07:59:41.33#ibcon#flushed, iclass 16, count 0 2006.190.07:59:41.33#ibcon#about to write, iclass 16, count 0 2006.190.07:59:41.33#ibcon#wrote, iclass 16, count 0 2006.190.07:59:41.33#ibcon#about to read 3, iclass 16, count 0 2006.190.07:59:41.35#ibcon#read 3, iclass 16, count 0 2006.190.07:59:41.35#ibcon#about to read 4, iclass 16, count 0 2006.190.07:59:41.35#ibcon#read 4, iclass 16, count 0 2006.190.07:59:41.35#ibcon#about to read 5, iclass 16, count 0 2006.190.07:59:41.35#ibcon#read 5, iclass 16, count 0 2006.190.07:59:41.35#ibcon#about to read 6, iclass 16, count 0 2006.190.07:59:41.35#ibcon#read 6, iclass 16, count 0 2006.190.07:59:41.35#ibcon#end of sib2, iclass 16, count 0 2006.190.07:59:41.35#ibcon#*mode == 0, iclass 16, count 0 2006.190.07:59:41.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.07:59:41.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.07:59:41.35#ibcon#*before write, iclass 16, count 0 2006.190.07:59:41.35#ibcon#enter sib2, iclass 16, count 0 2006.190.07:59:41.35#ibcon#flushed, iclass 16, count 0 2006.190.07:59:41.35#ibcon#about to write, iclass 16, count 0 2006.190.07:59:41.35#ibcon#wrote, iclass 16, count 0 2006.190.07:59:41.35#ibcon#about to read 3, iclass 16, count 0 2006.190.07:59:41.39#ibcon#read 3, iclass 16, count 0 2006.190.07:59:41.39#ibcon#about to read 4, iclass 16, count 0 2006.190.07:59:41.39#ibcon#read 4, iclass 16, count 0 2006.190.07:59:41.39#ibcon#about to read 5, iclass 16, count 0 2006.190.07:59:41.39#ibcon#read 5, iclass 16, count 0 2006.190.07:59:41.39#ibcon#about to read 6, iclass 16, count 0 2006.190.07:59:41.39#ibcon#read 6, iclass 16, count 0 2006.190.07:59:41.39#ibcon#end of sib2, iclass 16, count 0 2006.190.07:59:41.39#ibcon#*after write, iclass 16, count 0 2006.190.07:59:41.39#ibcon#*before return 0, iclass 16, count 0 2006.190.07:59:41.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:59:41.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.07:59:41.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.07:59:41.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.07:59:41.39$vc4f8/vb=3,4 2006.190.07:59:41.39#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.07:59:41.39#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.07:59:41.39#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:41.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:59:41.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:59:41.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:59:41.45#ibcon#enter wrdev, iclass 18, count 2 2006.190.07:59:41.45#ibcon#first serial, iclass 18, count 2 2006.190.07:59:41.45#ibcon#enter sib2, iclass 18, count 2 2006.190.07:59:41.45#ibcon#flushed, iclass 18, count 2 2006.190.07:59:41.45#ibcon#about to write, iclass 18, count 2 2006.190.07:59:41.45#ibcon#wrote, iclass 18, count 2 2006.190.07:59:41.45#ibcon#about to read 3, iclass 18, count 2 2006.190.07:59:41.47#ibcon#read 3, iclass 18, count 2 2006.190.07:59:41.47#ibcon#about to read 4, iclass 18, count 2 2006.190.07:59:41.47#ibcon#read 4, iclass 18, count 2 2006.190.07:59:41.47#ibcon#about to read 5, iclass 18, count 2 2006.190.07:59:41.47#ibcon#read 5, iclass 18, count 2 2006.190.07:59:41.47#ibcon#about to read 6, iclass 18, count 2 2006.190.07:59:41.47#ibcon#read 6, iclass 18, count 2 2006.190.07:59:41.47#ibcon#end of sib2, iclass 18, count 2 2006.190.07:59:41.47#ibcon#*mode == 0, iclass 18, count 2 2006.190.07:59:41.47#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.07:59:41.47#ibcon#[27=AT03-04\r\n] 2006.190.07:59:41.47#ibcon#*before write, iclass 18, count 2 2006.190.07:59:41.47#ibcon#enter sib2, iclass 18, count 2 2006.190.07:59:41.47#ibcon#flushed, iclass 18, count 2 2006.190.07:59:41.47#ibcon#about to write, iclass 18, count 2 2006.190.07:59:41.47#ibcon#wrote, iclass 18, count 2 2006.190.07:59:41.47#ibcon#about to read 3, iclass 18, count 2 2006.190.07:59:41.50#ibcon#read 3, iclass 18, count 2 2006.190.07:59:41.50#ibcon#about to read 4, iclass 18, count 2 2006.190.07:59:41.50#ibcon#read 4, iclass 18, count 2 2006.190.07:59:41.50#ibcon#about to read 5, iclass 18, count 2 2006.190.07:59:41.50#ibcon#read 5, iclass 18, count 2 2006.190.07:59:41.50#ibcon#about to read 6, iclass 18, count 2 2006.190.07:59:41.50#ibcon#read 6, iclass 18, count 2 2006.190.07:59:41.50#ibcon#end of sib2, iclass 18, count 2 2006.190.07:59:41.50#ibcon#*after write, iclass 18, count 2 2006.190.07:59:41.50#ibcon#*before return 0, iclass 18, count 2 2006.190.07:59:41.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:59:41.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.07:59:41.50#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.07:59:41.50#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:41.50#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:59:41.62#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:59:41.62#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:59:41.62#ibcon#enter wrdev, iclass 18, count 0 2006.190.07:59:41.62#ibcon#first serial, iclass 18, count 0 2006.190.07:59:41.62#ibcon#enter sib2, iclass 18, count 0 2006.190.07:59:41.62#ibcon#flushed, iclass 18, count 0 2006.190.07:59:41.62#ibcon#about to write, iclass 18, count 0 2006.190.07:59:41.62#ibcon#wrote, iclass 18, count 0 2006.190.07:59:41.62#ibcon#about to read 3, iclass 18, count 0 2006.190.07:59:41.64#ibcon#read 3, iclass 18, count 0 2006.190.07:59:41.64#ibcon#about to read 4, iclass 18, count 0 2006.190.07:59:41.64#ibcon#read 4, iclass 18, count 0 2006.190.07:59:41.64#ibcon#about to read 5, iclass 18, count 0 2006.190.07:59:41.64#ibcon#read 5, iclass 18, count 0 2006.190.07:59:41.64#ibcon#about to read 6, iclass 18, count 0 2006.190.07:59:41.64#ibcon#read 6, iclass 18, count 0 2006.190.07:59:41.64#ibcon#end of sib2, iclass 18, count 0 2006.190.07:59:41.64#ibcon#*mode == 0, iclass 18, count 0 2006.190.07:59:41.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.07:59:41.64#ibcon#[27=USB\r\n] 2006.190.07:59:41.64#ibcon#*before write, iclass 18, count 0 2006.190.07:59:41.64#ibcon#enter sib2, iclass 18, count 0 2006.190.07:59:41.64#ibcon#flushed, iclass 18, count 0 2006.190.07:59:41.64#ibcon#about to write, iclass 18, count 0 2006.190.07:59:41.64#ibcon#wrote, iclass 18, count 0 2006.190.07:59:41.64#ibcon#about to read 3, iclass 18, count 0 2006.190.07:59:41.67#ibcon#read 3, iclass 18, count 0 2006.190.07:59:41.67#ibcon#about to read 4, iclass 18, count 0 2006.190.07:59:41.67#ibcon#read 4, iclass 18, count 0 2006.190.07:59:41.67#ibcon#about to read 5, iclass 18, count 0 2006.190.07:59:41.67#ibcon#read 5, iclass 18, count 0 2006.190.07:59:41.67#ibcon#about to read 6, iclass 18, count 0 2006.190.07:59:41.67#ibcon#read 6, iclass 18, count 0 2006.190.07:59:41.67#ibcon#end of sib2, iclass 18, count 0 2006.190.07:59:41.67#ibcon#*after write, iclass 18, count 0 2006.190.07:59:41.67#ibcon#*before return 0, iclass 18, count 0 2006.190.07:59:41.67#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:59:41.67#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.07:59:41.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.07:59:41.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.07:59:41.67$vc4f8/vblo=4,712.99 2006.190.07:59:41.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.07:59:41.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.07:59:41.67#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:41.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:41.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:41.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:41.67#ibcon#enter wrdev, iclass 20, count 0 2006.190.07:59:41.67#ibcon#first serial, iclass 20, count 0 2006.190.07:59:41.67#ibcon#enter sib2, iclass 20, count 0 2006.190.07:59:41.67#ibcon#flushed, iclass 20, count 0 2006.190.07:59:41.67#ibcon#about to write, iclass 20, count 0 2006.190.07:59:41.67#ibcon#wrote, iclass 20, count 0 2006.190.07:59:41.67#ibcon#about to read 3, iclass 20, count 0 2006.190.07:59:41.69#ibcon#read 3, iclass 20, count 0 2006.190.07:59:41.69#ibcon#about to read 4, iclass 20, count 0 2006.190.07:59:41.69#ibcon#read 4, iclass 20, count 0 2006.190.07:59:41.69#ibcon#about to read 5, iclass 20, count 0 2006.190.07:59:41.69#ibcon#read 5, iclass 20, count 0 2006.190.07:59:41.69#ibcon#about to read 6, iclass 20, count 0 2006.190.07:59:41.69#ibcon#read 6, iclass 20, count 0 2006.190.07:59:41.69#ibcon#end of sib2, iclass 20, count 0 2006.190.07:59:41.69#ibcon#*mode == 0, iclass 20, count 0 2006.190.07:59:41.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.07:59:41.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.07:59:41.69#ibcon#*before write, iclass 20, count 0 2006.190.07:59:41.69#ibcon#enter sib2, iclass 20, count 0 2006.190.07:59:41.69#ibcon#flushed, iclass 20, count 0 2006.190.07:59:41.69#ibcon#about to write, iclass 20, count 0 2006.190.07:59:41.69#ibcon#wrote, iclass 20, count 0 2006.190.07:59:41.69#ibcon#about to read 3, iclass 20, count 0 2006.190.07:59:41.73#ibcon#read 3, iclass 20, count 0 2006.190.07:59:41.73#ibcon#about to read 4, iclass 20, count 0 2006.190.07:59:41.73#ibcon#read 4, iclass 20, count 0 2006.190.07:59:41.73#ibcon#about to read 5, iclass 20, count 0 2006.190.07:59:41.73#ibcon#read 5, iclass 20, count 0 2006.190.07:59:41.73#ibcon#about to read 6, iclass 20, count 0 2006.190.07:59:41.73#ibcon#read 6, iclass 20, count 0 2006.190.07:59:41.73#ibcon#end of sib2, iclass 20, count 0 2006.190.07:59:41.73#ibcon#*after write, iclass 20, count 0 2006.190.07:59:41.73#ibcon#*before return 0, iclass 20, count 0 2006.190.07:59:41.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:41.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.07:59:41.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.07:59:41.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.07:59:41.73$vc4f8/vb=4,4 2006.190.07:59:41.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.07:59:41.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.07:59:41.73#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:41.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:41.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:41.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:41.79#ibcon#enter wrdev, iclass 22, count 2 2006.190.07:59:41.79#ibcon#first serial, iclass 22, count 2 2006.190.07:59:41.79#ibcon#enter sib2, iclass 22, count 2 2006.190.07:59:41.79#ibcon#flushed, iclass 22, count 2 2006.190.07:59:41.79#ibcon#about to write, iclass 22, count 2 2006.190.07:59:41.79#ibcon#wrote, iclass 22, count 2 2006.190.07:59:41.79#ibcon#about to read 3, iclass 22, count 2 2006.190.07:59:41.81#ibcon#read 3, iclass 22, count 2 2006.190.07:59:41.81#ibcon#about to read 4, iclass 22, count 2 2006.190.07:59:41.81#ibcon#read 4, iclass 22, count 2 2006.190.07:59:41.81#ibcon#about to read 5, iclass 22, count 2 2006.190.07:59:41.81#ibcon#read 5, iclass 22, count 2 2006.190.07:59:41.81#ibcon#about to read 6, iclass 22, count 2 2006.190.07:59:41.81#ibcon#read 6, iclass 22, count 2 2006.190.07:59:41.81#ibcon#end of sib2, iclass 22, count 2 2006.190.07:59:41.81#ibcon#*mode == 0, iclass 22, count 2 2006.190.07:59:41.81#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.07:59:41.81#ibcon#[27=AT04-04\r\n] 2006.190.07:59:41.81#ibcon#*before write, iclass 22, count 2 2006.190.07:59:41.81#ibcon#enter sib2, iclass 22, count 2 2006.190.07:59:41.81#ibcon#flushed, iclass 22, count 2 2006.190.07:59:41.81#ibcon#about to write, iclass 22, count 2 2006.190.07:59:41.81#ibcon#wrote, iclass 22, count 2 2006.190.07:59:41.81#ibcon#about to read 3, iclass 22, count 2 2006.190.07:59:41.84#ibcon#read 3, iclass 22, count 2 2006.190.07:59:41.84#ibcon#about to read 4, iclass 22, count 2 2006.190.07:59:41.84#ibcon#read 4, iclass 22, count 2 2006.190.07:59:41.84#ibcon#about to read 5, iclass 22, count 2 2006.190.07:59:41.84#ibcon#read 5, iclass 22, count 2 2006.190.07:59:41.84#ibcon#about to read 6, iclass 22, count 2 2006.190.07:59:41.84#ibcon#read 6, iclass 22, count 2 2006.190.07:59:41.84#ibcon#end of sib2, iclass 22, count 2 2006.190.07:59:41.84#ibcon#*after write, iclass 22, count 2 2006.190.07:59:41.84#ibcon#*before return 0, iclass 22, count 2 2006.190.07:59:41.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:41.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.07:59:41.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.07:59:41.84#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:41.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:41.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:41.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:41.96#ibcon#enter wrdev, iclass 22, count 0 2006.190.07:59:41.96#ibcon#first serial, iclass 22, count 0 2006.190.07:59:41.96#ibcon#enter sib2, iclass 22, count 0 2006.190.07:59:41.96#ibcon#flushed, iclass 22, count 0 2006.190.07:59:41.96#ibcon#about to write, iclass 22, count 0 2006.190.07:59:41.96#ibcon#wrote, iclass 22, count 0 2006.190.07:59:41.96#ibcon#about to read 3, iclass 22, count 0 2006.190.07:59:41.98#ibcon#read 3, iclass 22, count 0 2006.190.07:59:41.98#ibcon#about to read 4, iclass 22, count 0 2006.190.07:59:41.98#ibcon#read 4, iclass 22, count 0 2006.190.07:59:41.98#ibcon#about to read 5, iclass 22, count 0 2006.190.07:59:41.98#ibcon#read 5, iclass 22, count 0 2006.190.07:59:41.98#ibcon#about to read 6, iclass 22, count 0 2006.190.07:59:41.98#ibcon#read 6, iclass 22, count 0 2006.190.07:59:41.98#ibcon#end of sib2, iclass 22, count 0 2006.190.07:59:41.98#ibcon#*mode == 0, iclass 22, count 0 2006.190.07:59:41.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.07:59:41.98#ibcon#[27=USB\r\n] 2006.190.07:59:41.98#ibcon#*before write, iclass 22, count 0 2006.190.07:59:41.98#ibcon#enter sib2, iclass 22, count 0 2006.190.07:59:41.98#ibcon#flushed, iclass 22, count 0 2006.190.07:59:41.98#ibcon#about to write, iclass 22, count 0 2006.190.07:59:41.98#ibcon#wrote, iclass 22, count 0 2006.190.07:59:41.98#ibcon#about to read 3, iclass 22, count 0 2006.190.07:59:42.01#ibcon#read 3, iclass 22, count 0 2006.190.07:59:42.01#ibcon#about to read 4, iclass 22, count 0 2006.190.07:59:42.01#ibcon#read 4, iclass 22, count 0 2006.190.07:59:42.01#ibcon#about to read 5, iclass 22, count 0 2006.190.07:59:42.01#ibcon#read 5, iclass 22, count 0 2006.190.07:59:42.01#ibcon#about to read 6, iclass 22, count 0 2006.190.07:59:42.01#ibcon#read 6, iclass 22, count 0 2006.190.07:59:42.01#ibcon#end of sib2, iclass 22, count 0 2006.190.07:59:42.01#ibcon#*after write, iclass 22, count 0 2006.190.07:59:42.01#ibcon#*before return 0, iclass 22, count 0 2006.190.07:59:42.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:42.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.07:59:42.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.07:59:42.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.07:59:42.01$vc4f8/vblo=5,744.99 2006.190.07:59:42.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.07:59:42.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.07:59:42.01#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:42.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:42.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:42.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:42.01#ibcon#enter wrdev, iclass 24, count 0 2006.190.07:59:42.01#ibcon#first serial, iclass 24, count 0 2006.190.07:59:42.01#ibcon#enter sib2, iclass 24, count 0 2006.190.07:59:42.01#ibcon#flushed, iclass 24, count 0 2006.190.07:59:42.01#ibcon#about to write, iclass 24, count 0 2006.190.07:59:42.01#ibcon#wrote, iclass 24, count 0 2006.190.07:59:42.01#ibcon#about to read 3, iclass 24, count 0 2006.190.07:59:42.03#ibcon#read 3, iclass 24, count 0 2006.190.07:59:42.03#ibcon#about to read 4, iclass 24, count 0 2006.190.07:59:42.03#ibcon#read 4, iclass 24, count 0 2006.190.07:59:42.03#ibcon#about to read 5, iclass 24, count 0 2006.190.07:59:42.03#ibcon#read 5, iclass 24, count 0 2006.190.07:59:42.03#ibcon#about to read 6, iclass 24, count 0 2006.190.07:59:42.03#ibcon#read 6, iclass 24, count 0 2006.190.07:59:42.03#ibcon#end of sib2, iclass 24, count 0 2006.190.07:59:42.03#ibcon#*mode == 0, iclass 24, count 0 2006.190.07:59:42.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.07:59:42.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.07:59:42.03#ibcon#*before write, iclass 24, count 0 2006.190.07:59:42.03#ibcon#enter sib2, iclass 24, count 0 2006.190.07:59:42.03#ibcon#flushed, iclass 24, count 0 2006.190.07:59:42.03#ibcon#about to write, iclass 24, count 0 2006.190.07:59:42.03#ibcon#wrote, iclass 24, count 0 2006.190.07:59:42.03#ibcon#about to read 3, iclass 24, count 0 2006.190.07:59:42.07#ibcon#read 3, iclass 24, count 0 2006.190.07:59:42.07#ibcon#about to read 4, iclass 24, count 0 2006.190.07:59:42.07#ibcon#read 4, iclass 24, count 0 2006.190.07:59:42.07#ibcon#about to read 5, iclass 24, count 0 2006.190.07:59:42.07#ibcon#read 5, iclass 24, count 0 2006.190.07:59:42.07#ibcon#about to read 6, iclass 24, count 0 2006.190.07:59:42.07#ibcon#read 6, iclass 24, count 0 2006.190.07:59:42.07#ibcon#end of sib2, iclass 24, count 0 2006.190.07:59:42.07#ibcon#*after write, iclass 24, count 0 2006.190.07:59:42.07#ibcon#*before return 0, iclass 24, count 0 2006.190.07:59:42.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:42.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.07:59:42.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.07:59:42.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.07:59:42.07$vc4f8/vb=5,4 2006.190.07:59:42.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.07:59:42.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.07:59:42.07#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:42.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:42.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:42.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:42.13#ibcon#enter wrdev, iclass 26, count 2 2006.190.07:59:42.13#ibcon#first serial, iclass 26, count 2 2006.190.07:59:42.13#ibcon#enter sib2, iclass 26, count 2 2006.190.07:59:42.13#ibcon#flushed, iclass 26, count 2 2006.190.07:59:42.13#ibcon#about to write, iclass 26, count 2 2006.190.07:59:42.13#ibcon#wrote, iclass 26, count 2 2006.190.07:59:42.13#ibcon#about to read 3, iclass 26, count 2 2006.190.07:59:42.15#ibcon#read 3, iclass 26, count 2 2006.190.07:59:42.15#ibcon#about to read 4, iclass 26, count 2 2006.190.07:59:42.15#ibcon#read 4, iclass 26, count 2 2006.190.07:59:42.15#ibcon#about to read 5, iclass 26, count 2 2006.190.07:59:42.15#ibcon#read 5, iclass 26, count 2 2006.190.07:59:42.15#ibcon#about to read 6, iclass 26, count 2 2006.190.07:59:42.15#ibcon#read 6, iclass 26, count 2 2006.190.07:59:42.15#ibcon#end of sib2, iclass 26, count 2 2006.190.07:59:42.15#ibcon#*mode == 0, iclass 26, count 2 2006.190.07:59:42.15#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.07:59:42.15#ibcon#[27=AT05-04\r\n] 2006.190.07:59:42.15#ibcon#*before write, iclass 26, count 2 2006.190.07:59:42.15#ibcon#enter sib2, iclass 26, count 2 2006.190.07:59:42.15#ibcon#flushed, iclass 26, count 2 2006.190.07:59:42.15#ibcon#about to write, iclass 26, count 2 2006.190.07:59:42.15#ibcon#wrote, iclass 26, count 2 2006.190.07:59:42.15#ibcon#about to read 3, iclass 26, count 2 2006.190.07:59:42.18#ibcon#read 3, iclass 26, count 2 2006.190.07:59:42.18#ibcon#about to read 4, iclass 26, count 2 2006.190.07:59:42.18#ibcon#read 4, iclass 26, count 2 2006.190.07:59:42.18#ibcon#about to read 5, iclass 26, count 2 2006.190.07:59:42.18#ibcon#read 5, iclass 26, count 2 2006.190.07:59:42.18#ibcon#about to read 6, iclass 26, count 2 2006.190.07:59:42.18#ibcon#read 6, iclass 26, count 2 2006.190.07:59:42.18#ibcon#end of sib2, iclass 26, count 2 2006.190.07:59:42.18#ibcon#*after write, iclass 26, count 2 2006.190.07:59:42.18#ibcon#*before return 0, iclass 26, count 2 2006.190.07:59:42.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:42.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.07:59:42.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.07:59:42.18#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:42.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:42.30#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:42.30#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:42.30#ibcon#enter wrdev, iclass 26, count 0 2006.190.07:59:42.30#ibcon#first serial, iclass 26, count 0 2006.190.07:59:42.30#ibcon#enter sib2, iclass 26, count 0 2006.190.07:59:42.30#ibcon#flushed, iclass 26, count 0 2006.190.07:59:42.30#ibcon#about to write, iclass 26, count 0 2006.190.07:59:42.30#ibcon#wrote, iclass 26, count 0 2006.190.07:59:42.30#ibcon#about to read 3, iclass 26, count 0 2006.190.07:59:42.32#ibcon#read 3, iclass 26, count 0 2006.190.07:59:42.32#ibcon#about to read 4, iclass 26, count 0 2006.190.07:59:42.32#ibcon#read 4, iclass 26, count 0 2006.190.07:59:42.32#ibcon#about to read 5, iclass 26, count 0 2006.190.07:59:42.32#ibcon#read 5, iclass 26, count 0 2006.190.07:59:42.32#ibcon#about to read 6, iclass 26, count 0 2006.190.07:59:42.32#ibcon#read 6, iclass 26, count 0 2006.190.07:59:42.32#ibcon#end of sib2, iclass 26, count 0 2006.190.07:59:42.32#ibcon#*mode == 0, iclass 26, count 0 2006.190.07:59:42.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.07:59:42.32#ibcon#[27=USB\r\n] 2006.190.07:59:42.32#ibcon#*before write, iclass 26, count 0 2006.190.07:59:42.32#ibcon#enter sib2, iclass 26, count 0 2006.190.07:59:42.32#ibcon#flushed, iclass 26, count 0 2006.190.07:59:42.32#ibcon#about to write, iclass 26, count 0 2006.190.07:59:42.32#ibcon#wrote, iclass 26, count 0 2006.190.07:59:42.32#ibcon#about to read 3, iclass 26, count 0 2006.190.07:59:42.35#ibcon#read 3, iclass 26, count 0 2006.190.07:59:42.35#ibcon#about to read 4, iclass 26, count 0 2006.190.07:59:42.35#ibcon#read 4, iclass 26, count 0 2006.190.07:59:42.35#ibcon#about to read 5, iclass 26, count 0 2006.190.07:59:42.35#ibcon#read 5, iclass 26, count 0 2006.190.07:59:42.35#ibcon#about to read 6, iclass 26, count 0 2006.190.07:59:42.35#ibcon#read 6, iclass 26, count 0 2006.190.07:59:42.35#ibcon#end of sib2, iclass 26, count 0 2006.190.07:59:42.35#ibcon#*after write, iclass 26, count 0 2006.190.07:59:42.35#ibcon#*before return 0, iclass 26, count 0 2006.190.07:59:42.35#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:42.35#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.07:59:42.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.07:59:42.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.07:59:42.35$vc4f8/vblo=6,752.99 2006.190.07:59:42.35#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.07:59:42.35#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.07:59:42.35#ibcon#ireg 17 cls_cnt 0 2006.190.07:59:42.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:42.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:42.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:42.35#ibcon#enter wrdev, iclass 28, count 0 2006.190.07:59:42.35#ibcon#first serial, iclass 28, count 0 2006.190.07:59:42.35#ibcon#enter sib2, iclass 28, count 0 2006.190.07:59:42.35#ibcon#flushed, iclass 28, count 0 2006.190.07:59:42.35#ibcon#about to write, iclass 28, count 0 2006.190.07:59:42.35#ibcon#wrote, iclass 28, count 0 2006.190.07:59:42.35#ibcon#about to read 3, iclass 28, count 0 2006.190.07:59:42.37#ibcon#read 3, iclass 28, count 0 2006.190.07:59:42.37#ibcon#about to read 4, iclass 28, count 0 2006.190.07:59:42.37#ibcon#read 4, iclass 28, count 0 2006.190.07:59:42.37#ibcon#about to read 5, iclass 28, count 0 2006.190.07:59:42.37#ibcon#read 5, iclass 28, count 0 2006.190.07:59:42.37#ibcon#about to read 6, iclass 28, count 0 2006.190.07:59:42.37#ibcon#read 6, iclass 28, count 0 2006.190.07:59:42.37#ibcon#end of sib2, iclass 28, count 0 2006.190.07:59:42.37#ibcon#*mode == 0, iclass 28, count 0 2006.190.07:59:42.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.07:59:42.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.07:59:42.37#ibcon#*before write, iclass 28, count 0 2006.190.07:59:42.37#ibcon#enter sib2, iclass 28, count 0 2006.190.07:59:42.37#ibcon#flushed, iclass 28, count 0 2006.190.07:59:42.37#ibcon#about to write, iclass 28, count 0 2006.190.07:59:42.37#ibcon#wrote, iclass 28, count 0 2006.190.07:59:42.37#ibcon#about to read 3, iclass 28, count 0 2006.190.07:59:42.41#ibcon#read 3, iclass 28, count 0 2006.190.07:59:42.41#ibcon#about to read 4, iclass 28, count 0 2006.190.07:59:42.41#ibcon#read 4, iclass 28, count 0 2006.190.07:59:42.41#ibcon#about to read 5, iclass 28, count 0 2006.190.07:59:42.41#ibcon#read 5, iclass 28, count 0 2006.190.07:59:42.41#ibcon#about to read 6, iclass 28, count 0 2006.190.07:59:42.41#ibcon#read 6, iclass 28, count 0 2006.190.07:59:42.41#ibcon#end of sib2, iclass 28, count 0 2006.190.07:59:42.41#ibcon#*after write, iclass 28, count 0 2006.190.07:59:42.41#ibcon#*before return 0, iclass 28, count 0 2006.190.07:59:42.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:42.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.07:59:42.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.07:59:42.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.07:59:42.41$vc4f8/vb=6,4 2006.190.07:59:42.41#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.07:59:42.41#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.07:59:42.41#ibcon#ireg 11 cls_cnt 2 2006.190.07:59:42.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:42.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:42.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:42.47#ibcon#enter wrdev, iclass 30, count 2 2006.190.07:59:42.47#ibcon#first serial, iclass 30, count 2 2006.190.07:59:42.47#ibcon#enter sib2, iclass 30, count 2 2006.190.07:59:42.47#ibcon#flushed, iclass 30, count 2 2006.190.07:59:42.47#ibcon#about to write, iclass 30, count 2 2006.190.07:59:42.47#ibcon#wrote, iclass 30, count 2 2006.190.07:59:42.47#ibcon#about to read 3, iclass 30, count 2 2006.190.07:59:42.49#ibcon#read 3, iclass 30, count 2 2006.190.07:59:42.49#ibcon#about to read 4, iclass 30, count 2 2006.190.07:59:42.49#ibcon#read 4, iclass 30, count 2 2006.190.07:59:42.49#ibcon#about to read 5, iclass 30, count 2 2006.190.07:59:42.49#ibcon#read 5, iclass 30, count 2 2006.190.07:59:42.49#ibcon#about to read 6, iclass 30, count 2 2006.190.07:59:42.49#ibcon#read 6, iclass 30, count 2 2006.190.07:59:42.49#ibcon#end of sib2, iclass 30, count 2 2006.190.07:59:42.49#ibcon#*mode == 0, iclass 30, count 2 2006.190.07:59:42.49#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.07:59:42.49#ibcon#[27=AT06-04\r\n] 2006.190.07:59:42.49#ibcon#*before write, iclass 30, count 2 2006.190.07:59:42.49#ibcon#enter sib2, iclass 30, count 2 2006.190.07:59:42.49#ibcon#flushed, iclass 30, count 2 2006.190.07:59:42.49#ibcon#about to write, iclass 30, count 2 2006.190.07:59:42.49#ibcon#wrote, iclass 30, count 2 2006.190.07:59:42.49#ibcon#about to read 3, iclass 30, count 2 2006.190.07:59:42.52#ibcon#read 3, iclass 30, count 2 2006.190.07:59:42.52#ibcon#about to read 4, iclass 30, count 2 2006.190.07:59:42.52#ibcon#read 4, iclass 30, count 2 2006.190.07:59:42.52#ibcon#about to read 5, iclass 30, count 2 2006.190.07:59:42.52#ibcon#read 5, iclass 30, count 2 2006.190.07:59:42.52#ibcon#about to read 6, iclass 30, count 2 2006.190.07:59:42.52#ibcon#read 6, iclass 30, count 2 2006.190.07:59:42.52#ibcon#end of sib2, iclass 30, count 2 2006.190.07:59:42.52#ibcon#*after write, iclass 30, count 2 2006.190.07:59:42.52#ibcon#*before return 0, iclass 30, count 2 2006.190.07:59:42.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:42.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.07:59:42.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.07:59:42.52#ibcon#ireg 7 cls_cnt 0 2006.190.07:59:42.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:42.64#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:42.64#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:42.64#ibcon#enter wrdev, iclass 30, count 0 2006.190.07:59:42.64#ibcon#first serial, iclass 30, count 0 2006.190.07:59:42.64#ibcon#enter sib2, iclass 30, count 0 2006.190.07:59:42.64#ibcon#flushed, iclass 30, count 0 2006.190.07:59:42.64#ibcon#about to write, iclass 30, count 0 2006.190.07:59:42.64#ibcon#wrote, iclass 30, count 0 2006.190.07:59:42.64#ibcon#about to read 3, iclass 30, count 0 2006.190.07:59:42.66#ibcon#read 3, iclass 30, count 0 2006.190.07:59:42.66#ibcon#about to read 4, iclass 30, count 0 2006.190.07:59:42.66#ibcon#read 4, iclass 30, count 0 2006.190.07:59:42.66#ibcon#about to read 5, iclass 30, count 0 2006.190.07:59:42.66#ibcon#read 5, iclass 30, count 0 2006.190.07:59:42.66#ibcon#about to read 6, iclass 30, count 0 2006.190.07:59:42.66#ibcon#read 6, iclass 30, count 0 2006.190.07:59:42.66#ibcon#end of sib2, iclass 30, count 0 2006.190.07:59:42.66#ibcon#*mode == 0, iclass 30, count 0 2006.190.07:59:42.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.07:59:42.66#ibcon#[27=USB\r\n] 2006.190.07:59:42.66#ibcon#*before write, iclass 30, count 0 2006.190.07:59:42.66#ibcon#enter sib2, iclass 30, count 0 2006.190.07:59:42.66#ibcon#flushed, iclass 30, count 0 2006.190.07:59:42.66#ibcon#about to write, iclass 30, count 0 2006.190.07:59:42.66#ibcon#wrote, iclass 30, count 0 2006.190.07:59:42.66#ibcon#about to read 3, iclass 30, count 0 2006.190.07:59:42.69#ibcon#read 3, iclass 30, count 0 2006.190.07:59:42.69#ibcon#about to read 4, iclass 30, count 0 2006.190.07:59:42.69#ibcon#read 4, iclass 30, count 0 2006.190.07:59:42.69#ibcon#about to read 5, iclass 30, count 0 2006.190.07:59:42.69#ibcon#read 5, iclass 30, count 0 2006.190.07:59:42.69#ibcon#about to read 6, iclass 30, count 0 2006.190.07:59:42.69#ibcon#read 6, iclass 30, count 0 2006.190.07:59:42.69#ibcon#end of sib2, iclass 30, count 0 2006.190.07:59:42.69#ibcon#*after write, iclass 30, count 0 2006.190.07:59:42.69#ibcon#*before return 0, iclass 30, count 0 2006.190.07:59:42.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:42.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.07:59:42.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.07:59:42.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.07:59:42.69$vc4f8/vabw=wide 2006.190.07:59:42.69#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.07:59:42.69#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.07:59:42.69#ibcon#ireg 8 cls_cnt 0 2006.190.07:59:42.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:42.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:42.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:42.69#ibcon#enter wrdev, iclass 32, count 0 2006.190.07:59:42.69#ibcon#first serial, iclass 32, count 0 2006.190.07:59:42.69#ibcon#enter sib2, iclass 32, count 0 2006.190.07:59:42.69#ibcon#flushed, iclass 32, count 0 2006.190.07:59:42.69#ibcon#about to write, iclass 32, count 0 2006.190.07:59:42.69#ibcon#wrote, iclass 32, count 0 2006.190.07:59:42.69#ibcon#about to read 3, iclass 32, count 0 2006.190.07:59:42.71#ibcon#read 3, iclass 32, count 0 2006.190.07:59:42.71#ibcon#about to read 4, iclass 32, count 0 2006.190.07:59:42.71#ibcon#read 4, iclass 32, count 0 2006.190.07:59:42.71#ibcon#about to read 5, iclass 32, count 0 2006.190.07:59:42.71#ibcon#read 5, iclass 32, count 0 2006.190.07:59:42.71#ibcon#about to read 6, iclass 32, count 0 2006.190.07:59:42.71#ibcon#read 6, iclass 32, count 0 2006.190.07:59:42.71#ibcon#end of sib2, iclass 32, count 0 2006.190.07:59:42.71#ibcon#*mode == 0, iclass 32, count 0 2006.190.07:59:42.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.07:59:42.71#ibcon#[25=BW32\r\n] 2006.190.07:59:42.71#ibcon#*before write, iclass 32, count 0 2006.190.07:59:42.71#ibcon#enter sib2, iclass 32, count 0 2006.190.07:59:42.71#ibcon#flushed, iclass 32, count 0 2006.190.07:59:42.71#ibcon#about to write, iclass 32, count 0 2006.190.07:59:42.71#ibcon#wrote, iclass 32, count 0 2006.190.07:59:42.71#ibcon#about to read 3, iclass 32, count 0 2006.190.07:59:42.74#ibcon#read 3, iclass 32, count 0 2006.190.07:59:42.74#ibcon#about to read 4, iclass 32, count 0 2006.190.07:59:42.74#ibcon#read 4, iclass 32, count 0 2006.190.07:59:42.74#ibcon#about to read 5, iclass 32, count 0 2006.190.07:59:42.74#ibcon#read 5, iclass 32, count 0 2006.190.07:59:42.74#ibcon#about to read 6, iclass 32, count 0 2006.190.07:59:42.74#ibcon#read 6, iclass 32, count 0 2006.190.07:59:42.74#ibcon#end of sib2, iclass 32, count 0 2006.190.07:59:42.74#ibcon#*after write, iclass 32, count 0 2006.190.07:59:42.74#ibcon#*before return 0, iclass 32, count 0 2006.190.07:59:42.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:42.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.07:59:42.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.07:59:42.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.07:59:42.74$vc4f8/vbbw=wide 2006.190.07:59:42.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.07:59:42.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.07:59:42.74#ibcon#ireg 8 cls_cnt 0 2006.190.07:59:42.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:59:42.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:59:42.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:59:42.81#ibcon#enter wrdev, iclass 34, count 0 2006.190.07:59:42.81#ibcon#first serial, iclass 34, count 0 2006.190.07:59:42.81#ibcon#enter sib2, iclass 34, count 0 2006.190.07:59:42.81#ibcon#flushed, iclass 34, count 0 2006.190.07:59:42.81#ibcon#about to write, iclass 34, count 0 2006.190.07:59:42.81#ibcon#wrote, iclass 34, count 0 2006.190.07:59:42.81#ibcon#about to read 3, iclass 34, count 0 2006.190.07:59:42.83#ibcon#read 3, iclass 34, count 0 2006.190.07:59:42.83#ibcon#about to read 4, iclass 34, count 0 2006.190.07:59:42.83#ibcon#read 4, iclass 34, count 0 2006.190.07:59:42.83#ibcon#about to read 5, iclass 34, count 0 2006.190.07:59:42.84#ibcon#read 5, iclass 34, count 0 2006.190.07:59:42.84#ibcon#about to read 6, iclass 34, count 0 2006.190.07:59:42.84#ibcon#read 6, iclass 34, count 0 2006.190.07:59:42.84#ibcon#end of sib2, iclass 34, count 0 2006.190.07:59:42.84#ibcon#*mode == 0, iclass 34, count 0 2006.190.07:59:42.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.07:59:42.84#ibcon#[27=BW32\r\n] 2006.190.07:59:42.84#ibcon#*before write, iclass 34, count 0 2006.190.07:59:42.84#ibcon#enter sib2, iclass 34, count 0 2006.190.07:59:42.84#ibcon#flushed, iclass 34, count 0 2006.190.07:59:42.84#ibcon#about to write, iclass 34, count 0 2006.190.07:59:42.84#ibcon#wrote, iclass 34, count 0 2006.190.07:59:42.84#ibcon#about to read 3, iclass 34, count 0 2006.190.07:59:42.86#ibcon#read 3, iclass 34, count 0 2006.190.07:59:42.86#ibcon#about to read 4, iclass 34, count 0 2006.190.07:59:42.86#ibcon#read 4, iclass 34, count 0 2006.190.07:59:42.86#ibcon#about to read 5, iclass 34, count 0 2006.190.07:59:42.86#ibcon#read 5, iclass 34, count 0 2006.190.07:59:42.86#ibcon#about to read 6, iclass 34, count 0 2006.190.07:59:42.86#ibcon#read 6, iclass 34, count 0 2006.190.07:59:42.86#ibcon#end of sib2, iclass 34, count 0 2006.190.07:59:42.86#ibcon#*after write, iclass 34, count 0 2006.190.07:59:42.86#ibcon#*before return 0, iclass 34, count 0 2006.190.07:59:42.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:59:42.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.07:59:42.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.07:59:42.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.07:59:42.86$4f8m12a/ifd4f 2006.190.07:59:42.86$ifd4f/lo= 2006.190.07:59:42.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.07:59:42.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.07:59:42.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.07:59:42.87$ifd4f/patch= 2006.190.07:59:42.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.07:59:42.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.07:59:42.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.07:59:42.87$4f8m12a/"form=m,16.000,1:2 2006.190.07:59:42.87$4f8m12a/"tpicd 2006.190.07:59:42.87$4f8m12a/echo=off 2006.190.07:59:42.87$4f8m12a/xlog=off 2006.190.07:59:42.87:!2006.190.08:00:10 2006.190.07:59:50.14#trakl#Source acquired 2006.190.07:59:52.14#flagr#flagr/antenna,acquired 2006.190.08:00:10.01:preob 2006.190.08:00:11.14/onsource/TRACKING 2006.190.08:00:11.14:!2006.190.08:00:20 2006.190.08:00:20.00:data_valid=on 2006.190.08:00:20.00:midob 2006.190.08:00:20.14/onsource/TRACKING 2006.190.08:00:20.14/wx/24.53,1012.0,100 2006.190.08:00:20.32/cable/+6.4712E-03 2006.190.08:00:21.41/va/01,08,usb,yes,34,35 2006.190.08:00:21.41/va/02,07,usb,yes,34,36 2006.190.08:00:21.41/va/03,06,usb,yes,36,36 2006.190.08:00:21.41/va/04,07,usb,yes,35,38 2006.190.08:00:21.41/va/05,07,usb,yes,38,40 2006.190.08:00:21.41/va/06,06,usb,yes,37,37 2006.190.08:00:21.41/va/07,06,usb,yes,38,38 2006.190.08:00:21.41/va/08,06,usb,yes,40,40 2006.190.08:00:21.64/valo/01,532.99,yes,locked 2006.190.08:00:21.64/valo/02,572.99,yes,locked 2006.190.08:00:21.64/valo/03,672.99,yes,locked 2006.190.08:00:21.64/valo/04,832.99,yes,locked 2006.190.08:00:21.64/valo/05,652.99,yes,locked 2006.190.08:00:21.64/valo/06,772.99,yes,locked 2006.190.08:00:21.64/valo/07,832.99,yes,locked 2006.190.08:00:21.64/valo/08,852.99,yes,locked 2006.190.08:00:22.73/vb/01,04,usb,yes,30,28 2006.190.08:00:22.73/vb/02,04,usb,yes,31,33 2006.190.08:00:22.73/vb/03,04,usb,yes,28,31 2006.190.08:00:22.73/vb/04,04,usb,yes,29,29 2006.190.08:00:22.73/vb/05,04,usb,yes,27,31 2006.190.08:00:22.73/vb/06,04,usb,yes,28,31 2006.190.08:00:22.73/vb/07,04,usb,yes,30,30 2006.190.08:00:22.73/vb/08,04,usb,yes,28,31 2006.190.08:00:22.97/vblo/01,632.99,yes,locked 2006.190.08:00:22.97/vblo/02,640.99,yes,locked 2006.190.08:00:22.97/vblo/03,656.99,yes,locked 2006.190.08:00:22.97/vblo/04,712.99,yes,locked 2006.190.08:00:22.97/vblo/05,744.99,yes,locked 2006.190.08:00:22.97/vblo/06,752.99,yes,locked 2006.190.08:00:22.97/vblo/07,734.99,yes,locked 2006.190.08:00:22.97/vblo/08,744.99,yes,locked 2006.190.08:00:23.12/vabw/8 2006.190.08:00:23.27/vbbw/8 2006.190.08:00:23.36/xfe/off,on,14.7 2006.190.08:00:23.74/ifatt/23,28,28,28 2006.190.08:00:24.07/fmout-gps/S +2.86E-07 2006.190.08:00:24.16:!2006.190.08:01:20 2006.190.08:01:20.01:data_valid=off 2006.190.08:01:20.02:postob 2006.190.08:01:20.12/cable/+6.4708E-03 2006.190.08:01:20.13/wx/24.52,1012.0,100 2006.190.08:01:21.07/fmout-gps/S +2.86E-07 2006.190.08:01:21.08:scan_name=190-0802,k06190,60 2006.190.08:01:21.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.190.08:01:21.14#flagr#flagr/antenna,new-source 2006.190.08:01:22.14:checkk5 2006.190.08:01:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:01:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:01:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:01:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:01:24.05/chk_obsdata//k5ts1/T1900800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:01:24.43/chk_obsdata//k5ts2/T1900800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:01:24.81/chk_obsdata//k5ts3/T1900800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:01:25.18/chk_obsdata//k5ts4/T1900800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:01:25.88/k5log//k5ts1_log_newline 2006.190.08:01:26.59/k5log//k5ts2_log_newline 2006.190.08:01:27.29/k5log//k5ts3_log_newline 2006.190.08:01:27.98/k5log//k5ts4_log_newline 2006.190.08:01:28.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:01:28.00:4f8m12a=2 2006.190.08:01:28.00$4f8m12a/echo=on 2006.190.08:01:28.00$4f8m12a/pcalon 2006.190.08:01:28.00$pcalon/"no phase cal control is implemented here 2006.190.08:01:28.00$4f8m12a/"tpicd=stop 2006.190.08:01:28.00$4f8m12a/vc4f8 2006.190.08:01:28.00$vc4f8/valo=1,532.99 2006.190.08:01:28.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.08:01:28.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.08:01:28.01#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:28.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:28.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:28.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:28.01#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:01:28.01#ibcon#first serial, iclass 3, count 0 2006.190.08:01:28.01#ibcon#enter sib2, iclass 3, count 0 2006.190.08:01:28.01#ibcon#flushed, iclass 3, count 0 2006.190.08:01:28.01#ibcon#about to write, iclass 3, count 0 2006.190.08:01:28.01#ibcon#wrote, iclass 3, count 0 2006.190.08:01:28.01#ibcon#about to read 3, iclass 3, count 0 2006.190.08:01:28.06#ibcon#read 3, iclass 3, count 0 2006.190.08:01:28.06#ibcon#about to read 4, iclass 3, count 0 2006.190.08:01:28.06#ibcon#read 4, iclass 3, count 0 2006.190.08:01:28.06#ibcon#about to read 5, iclass 3, count 0 2006.190.08:01:28.06#ibcon#read 5, iclass 3, count 0 2006.190.08:01:28.06#ibcon#about to read 6, iclass 3, count 0 2006.190.08:01:28.06#ibcon#read 6, iclass 3, count 0 2006.190.08:01:28.06#ibcon#end of sib2, iclass 3, count 0 2006.190.08:01:28.06#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:01:28.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:01:28.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:01:28.06#ibcon#*before write, iclass 3, count 0 2006.190.08:01:28.06#ibcon#enter sib2, iclass 3, count 0 2006.190.08:01:28.06#ibcon#flushed, iclass 3, count 0 2006.190.08:01:28.06#ibcon#about to write, iclass 3, count 0 2006.190.08:01:28.06#ibcon#wrote, iclass 3, count 0 2006.190.08:01:28.06#ibcon#about to read 3, iclass 3, count 0 2006.190.08:01:28.10#ibcon#read 3, iclass 3, count 0 2006.190.08:01:28.10#ibcon#about to read 4, iclass 3, count 0 2006.190.08:01:28.10#ibcon#read 4, iclass 3, count 0 2006.190.08:01:28.10#ibcon#about to read 5, iclass 3, count 0 2006.190.08:01:28.10#ibcon#read 5, iclass 3, count 0 2006.190.08:01:28.10#ibcon#about to read 6, iclass 3, count 0 2006.190.08:01:28.10#ibcon#read 6, iclass 3, count 0 2006.190.08:01:28.10#ibcon#end of sib2, iclass 3, count 0 2006.190.08:01:28.10#ibcon#*after write, iclass 3, count 0 2006.190.08:01:28.10#ibcon#*before return 0, iclass 3, count 0 2006.190.08:01:28.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:28.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:28.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:01:28.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:01:28.10$vc4f8/va=1,8 2006.190.08:01:28.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.08:01:28.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.08:01:28.10#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:28.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:28.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:28.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:28.10#ibcon#enter wrdev, iclass 5, count 2 2006.190.08:01:28.10#ibcon#first serial, iclass 5, count 2 2006.190.08:01:28.10#ibcon#enter sib2, iclass 5, count 2 2006.190.08:01:28.10#ibcon#flushed, iclass 5, count 2 2006.190.08:01:28.10#ibcon#about to write, iclass 5, count 2 2006.190.08:01:28.10#ibcon#wrote, iclass 5, count 2 2006.190.08:01:28.10#ibcon#about to read 3, iclass 5, count 2 2006.190.08:01:28.12#ibcon#read 3, iclass 5, count 2 2006.190.08:01:28.12#ibcon#about to read 4, iclass 5, count 2 2006.190.08:01:28.12#ibcon#read 4, iclass 5, count 2 2006.190.08:01:28.12#ibcon#about to read 5, iclass 5, count 2 2006.190.08:01:28.12#ibcon#read 5, iclass 5, count 2 2006.190.08:01:28.12#ibcon#about to read 6, iclass 5, count 2 2006.190.08:01:28.12#ibcon#read 6, iclass 5, count 2 2006.190.08:01:28.12#ibcon#end of sib2, iclass 5, count 2 2006.190.08:01:28.12#ibcon#*mode == 0, iclass 5, count 2 2006.190.08:01:28.12#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.08:01:28.12#ibcon#[25=AT01-08\r\n] 2006.190.08:01:28.12#ibcon#*before write, iclass 5, count 2 2006.190.08:01:28.12#ibcon#enter sib2, iclass 5, count 2 2006.190.08:01:28.12#ibcon#flushed, iclass 5, count 2 2006.190.08:01:28.12#ibcon#about to write, iclass 5, count 2 2006.190.08:01:28.12#ibcon#wrote, iclass 5, count 2 2006.190.08:01:28.12#ibcon#about to read 3, iclass 5, count 2 2006.190.08:01:28.15#ibcon#read 3, iclass 5, count 2 2006.190.08:01:28.15#ibcon#about to read 4, iclass 5, count 2 2006.190.08:01:28.15#ibcon#read 4, iclass 5, count 2 2006.190.08:01:28.15#ibcon#about to read 5, iclass 5, count 2 2006.190.08:01:28.15#ibcon#read 5, iclass 5, count 2 2006.190.08:01:28.15#ibcon#about to read 6, iclass 5, count 2 2006.190.08:01:28.15#ibcon#read 6, iclass 5, count 2 2006.190.08:01:28.15#ibcon#end of sib2, iclass 5, count 2 2006.190.08:01:28.15#ibcon#*after write, iclass 5, count 2 2006.190.08:01:28.15#ibcon#*before return 0, iclass 5, count 2 2006.190.08:01:28.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:28.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:28.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.08:01:28.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:28.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:28.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:28.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:28.27#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:01:28.27#ibcon#first serial, iclass 5, count 0 2006.190.08:01:28.27#ibcon#enter sib2, iclass 5, count 0 2006.190.08:01:28.27#ibcon#flushed, iclass 5, count 0 2006.190.08:01:28.27#ibcon#about to write, iclass 5, count 0 2006.190.08:01:28.27#ibcon#wrote, iclass 5, count 0 2006.190.08:01:28.27#ibcon#about to read 3, iclass 5, count 0 2006.190.08:01:28.30#ibcon#read 3, iclass 5, count 0 2006.190.08:01:28.30#ibcon#about to read 4, iclass 5, count 0 2006.190.08:01:28.30#ibcon#read 4, iclass 5, count 0 2006.190.08:01:28.30#ibcon#about to read 5, iclass 5, count 0 2006.190.08:01:28.30#ibcon#read 5, iclass 5, count 0 2006.190.08:01:28.30#ibcon#about to read 6, iclass 5, count 0 2006.190.08:01:28.30#ibcon#read 6, iclass 5, count 0 2006.190.08:01:28.30#ibcon#end of sib2, iclass 5, count 0 2006.190.08:01:28.30#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:01:28.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:01:28.30#ibcon#[25=USB\r\n] 2006.190.08:01:28.30#ibcon#*before write, iclass 5, count 0 2006.190.08:01:28.30#ibcon#enter sib2, iclass 5, count 0 2006.190.08:01:28.30#ibcon#flushed, iclass 5, count 0 2006.190.08:01:28.30#ibcon#about to write, iclass 5, count 0 2006.190.08:01:28.30#ibcon#wrote, iclass 5, count 0 2006.190.08:01:28.30#ibcon#about to read 3, iclass 5, count 0 2006.190.08:01:28.32#ibcon#read 3, iclass 5, count 0 2006.190.08:01:28.32#ibcon#about to read 4, iclass 5, count 0 2006.190.08:01:28.32#ibcon#read 4, iclass 5, count 0 2006.190.08:01:28.32#ibcon#about to read 5, iclass 5, count 0 2006.190.08:01:28.32#ibcon#read 5, iclass 5, count 0 2006.190.08:01:28.32#ibcon#about to read 6, iclass 5, count 0 2006.190.08:01:28.32#ibcon#read 6, iclass 5, count 0 2006.190.08:01:28.32#ibcon#end of sib2, iclass 5, count 0 2006.190.08:01:28.32#ibcon#*after write, iclass 5, count 0 2006.190.08:01:28.32#ibcon#*before return 0, iclass 5, count 0 2006.190.08:01:28.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:28.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:28.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:01:28.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:01:28.32$vc4f8/valo=2,572.99 2006.190.08:01:28.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.08:01:28.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.08:01:28.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:28.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:28.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:28.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:28.32#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:01:28.32#ibcon#first serial, iclass 7, count 0 2006.190.08:01:28.32#ibcon#enter sib2, iclass 7, count 0 2006.190.08:01:28.32#ibcon#flushed, iclass 7, count 0 2006.190.08:01:28.32#ibcon#about to write, iclass 7, count 0 2006.190.08:01:28.32#ibcon#wrote, iclass 7, count 0 2006.190.08:01:28.32#ibcon#about to read 3, iclass 7, count 0 2006.190.08:01:28.34#ibcon#read 3, iclass 7, count 0 2006.190.08:01:28.34#ibcon#about to read 4, iclass 7, count 0 2006.190.08:01:28.34#ibcon#read 4, iclass 7, count 0 2006.190.08:01:28.34#ibcon#about to read 5, iclass 7, count 0 2006.190.08:01:28.34#ibcon#read 5, iclass 7, count 0 2006.190.08:01:28.34#ibcon#about to read 6, iclass 7, count 0 2006.190.08:01:28.34#ibcon#read 6, iclass 7, count 0 2006.190.08:01:28.34#ibcon#end of sib2, iclass 7, count 0 2006.190.08:01:28.34#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:01:28.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:01:28.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:01:28.34#ibcon#*before write, iclass 7, count 0 2006.190.08:01:28.34#ibcon#enter sib2, iclass 7, count 0 2006.190.08:01:28.34#ibcon#flushed, iclass 7, count 0 2006.190.08:01:28.34#ibcon#about to write, iclass 7, count 0 2006.190.08:01:28.34#ibcon#wrote, iclass 7, count 0 2006.190.08:01:28.34#ibcon#about to read 3, iclass 7, count 0 2006.190.08:01:28.38#ibcon#read 3, iclass 7, count 0 2006.190.08:01:28.38#ibcon#about to read 4, iclass 7, count 0 2006.190.08:01:28.38#ibcon#read 4, iclass 7, count 0 2006.190.08:01:28.38#ibcon#about to read 5, iclass 7, count 0 2006.190.08:01:28.39#ibcon#read 5, iclass 7, count 0 2006.190.08:01:28.39#ibcon#about to read 6, iclass 7, count 0 2006.190.08:01:28.39#ibcon#read 6, iclass 7, count 0 2006.190.08:01:28.39#ibcon#end of sib2, iclass 7, count 0 2006.190.08:01:28.39#ibcon#*after write, iclass 7, count 0 2006.190.08:01:28.39#ibcon#*before return 0, iclass 7, count 0 2006.190.08:01:28.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:28.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:28.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:01:28.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:01:28.39$vc4f8/va=2,7 2006.190.08:01:28.39#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.08:01:28.39#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.08:01:28.39#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:28.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:28.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:28.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:28.43#ibcon#enter wrdev, iclass 11, count 2 2006.190.08:01:28.43#ibcon#first serial, iclass 11, count 2 2006.190.08:01:28.43#ibcon#enter sib2, iclass 11, count 2 2006.190.08:01:28.43#ibcon#flushed, iclass 11, count 2 2006.190.08:01:28.43#ibcon#about to write, iclass 11, count 2 2006.190.08:01:28.43#ibcon#wrote, iclass 11, count 2 2006.190.08:01:28.43#ibcon#about to read 3, iclass 11, count 2 2006.190.08:01:28.45#ibcon#read 3, iclass 11, count 2 2006.190.08:01:28.45#ibcon#about to read 4, iclass 11, count 2 2006.190.08:01:28.45#ibcon#read 4, iclass 11, count 2 2006.190.08:01:28.45#ibcon#about to read 5, iclass 11, count 2 2006.190.08:01:28.45#ibcon#read 5, iclass 11, count 2 2006.190.08:01:28.45#ibcon#about to read 6, iclass 11, count 2 2006.190.08:01:28.45#ibcon#read 6, iclass 11, count 2 2006.190.08:01:28.45#ibcon#end of sib2, iclass 11, count 2 2006.190.08:01:28.45#ibcon#*mode == 0, iclass 11, count 2 2006.190.08:01:28.45#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.08:01:28.45#ibcon#[25=AT02-07\r\n] 2006.190.08:01:28.45#ibcon#*before write, iclass 11, count 2 2006.190.08:01:28.45#ibcon#enter sib2, iclass 11, count 2 2006.190.08:01:28.45#ibcon#flushed, iclass 11, count 2 2006.190.08:01:28.45#ibcon#about to write, iclass 11, count 2 2006.190.08:01:28.45#ibcon#wrote, iclass 11, count 2 2006.190.08:01:28.45#ibcon#about to read 3, iclass 11, count 2 2006.190.08:01:28.49#ibcon#read 3, iclass 11, count 2 2006.190.08:01:28.49#ibcon#about to read 4, iclass 11, count 2 2006.190.08:01:28.49#ibcon#read 4, iclass 11, count 2 2006.190.08:01:28.49#ibcon#about to read 5, iclass 11, count 2 2006.190.08:01:28.49#ibcon#read 5, iclass 11, count 2 2006.190.08:01:28.49#ibcon#about to read 6, iclass 11, count 2 2006.190.08:01:28.49#ibcon#read 6, iclass 11, count 2 2006.190.08:01:28.49#ibcon#end of sib2, iclass 11, count 2 2006.190.08:01:28.49#ibcon#*after write, iclass 11, count 2 2006.190.08:01:28.49#ibcon#*before return 0, iclass 11, count 2 2006.190.08:01:28.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:28.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:28.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.08:01:28.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:28.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:28.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:28.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:28.60#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:01:28.60#ibcon#first serial, iclass 11, count 0 2006.190.08:01:28.60#ibcon#enter sib2, iclass 11, count 0 2006.190.08:01:28.60#ibcon#flushed, iclass 11, count 0 2006.190.08:01:28.60#ibcon#about to write, iclass 11, count 0 2006.190.08:01:28.60#ibcon#wrote, iclass 11, count 0 2006.190.08:01:28.60#ibcon#about to read 3, iclass 11, count 0 2006.190.08:01:28.62#ibcon#read 3, iclass 11, count 0 2006.190.08:01:28.62#ibcon#about to read 4, iclass 11, count 0 2006.190.08:01:28.62#ibcon#read 4, iclass 11, count 0 2006.190.08:01:28.62#ibcon#about to read 5, iclass 11, count 0 2006.190.08:01:28.62#ibcon#read 5, iclass 11, count 0 2006.190.08:01:28.62#ibcon#about to read 6, iclass 11, count 0 2006.190.08:01:28.62#ibcon#read 6, iclass 11, count 0 2006.190.08:01:28.62#ibcon#end of sib2, iclass 11, count 0 2006.190.08:01:28.62#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:01:28.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:01:28.62#ibcon#[25=USB\r\n] 2006.190.08:01:28.62#ibcon#*before write, iclass 11, count 0 2006.190.08:01:28.62#ibcon#enter sib2, iclass 11, count 0 2006.190.08:01:28.62#ibcon#flushed, iclass 11, count 0 2006.190.08:01:28.62#ibcon#about to write, iclass 11, count 0 2006.190.08:01:28.62#ibcon#wrote, iclass 11, count 0 2006.190.08:01:28.62#ibcon#about to read 3, iclass 11, count 0 2006.190.08:01:28.65#ibcon#read 3, iclass 11, count 0 2006.190.08:01:28.65#ibcon#about to read 4, iclass 11, count 0 2006.190.08:01:28.65#ibcon#read 4, iclass 11, count 0 2006.190.08:01:28.65#ibcon#about to read 5, iclass 11, count 0 2006.190.08:01:28.65#ibcon#read 5, iclass 11, count 0 2006.190.08:01:28.65#ibcon#about to read 6, iclass 11, count 0 2006.190.08:01:28.65#ibcon#read 6, iclass 11, count 0 2006.190.08:01:28.65#ibcon#end of sib2, iclass 11, count 0 2006.190.08:01:28.65#ibcon#*after write, iclass 11, count 0 2006.190.08:01:28.65#ibcon#*before return 0, iclass 11, count 0 2006.190.08:01:28.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:28.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:28.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:01:28.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:01:28.65$vc4f8/valo=3,672.99 2006.190.08:01:28.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.08:01:28.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.08:01:28.65#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:28.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:28.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:28.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:28.65#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:01:28.65#ibcon#first serial, iclass 13, count 0 2006.190.08:01:28.65#ibcon#enter sib2, iclass 13, count 0 2006.190.08:01:28.65#ibcon#flushed, iclass 13, count 0 2006.190.08:01:28.65#ibcon#about to write, iclass 13, count 0 2006.190.08:01:28.65#ibcon#wrote, iclass 13, count 0 2006.190.08:01:28.65#ibcon#about to read 3, iclass 13, count 0 2006.190.08:01:28.67#ibcon#read 3, iclass 13, count 0 2006.190.08:01:28.67#ibcon#about to read 4, iclass 13, count 0 2006.190.08:01:28.67#ibcon#read 4, iclass 13, count 0 2006.190.08:01:28.67#ibcon#about to read 5, iclass 13, count 0 2006.190.08:01:28.67#ibcon#read 5, iclass 13, count 0 2006.190.08:01:28.67#ibcon#about to read 6, iclass 13, count 0 2006.190.08:01:28.67#ibcon#read 6, iclass 13, count 0 2006.190.08:01:28.67#ibcon#end of sib2, iclass 13, count 0 2006.190.08:01:28.67#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:01:28.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:01:28.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:01:28.67#ibcon#*before write, iclass 13, count 0 2006.190.08:01:28.67#ibcon#enter sib2, iclass 13, count 0 2006.190.08:01:28.67#ibcon#flushed, iclass 13, count 0 2006.190.08:01:28.67#ibcon#about to write, iclass 13, count 0 2006.190.08:01:28.67#ibcon#wrote, iclass 13, count 0 2006.190.08:01:28.67#ibcon#about to read 3, iclass 13, count 0 2006.190.08:01:28.71#ibcon#read 3, iclass 13, count 0 2006.190.08:01:28.71#ibcon#about to read 4, iclass 13, count 0 2006.190.08:01:28.71#ibcon#read 4, iclass 13, count 0 2006.190.08:01:28.71#ibcon#about to read 5, iclass 13, count 0 2006.190.08:01:28.71#ibcon#read 5, iclass 13, count 0 2006.190.08:01:28.71#ibcon#about to read 6, iclass 13, count 0 2006.190.08:01:28.71#ibcon#read 6, iclass 13, count 0 2006.190.08:01:28.71#ibcon#end of sib2, iclass 13, count 0 2006.190.08:01:28.71#ibcon#*after write, iclass 13, count 0 2006.190.08:01:28.71#ibcon#*before return 0, iclass 13, count 0 2006.190.08:01:28.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:28.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:28.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:01:28.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:01:28.71$vc4f8/va=3,6 2006.190.08:01:28.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.08:01:28.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.08:01:28.71#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:28.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:28.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:28.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:28.77#ibcon#enter wrdev, iclass 15, count 2 2006.190.08:01:28.77#ibcon#first serial, iclass 15, count 2 2006.190.08:01:28.77#ibcon#enter sib2, iclass 15, count 2 2006.190.08:01:28.77#ibcon#flushed, iclass 15, count 2 2006.190.08:01:28.77#ibcon#about to write, iclass 15, count 2 2006.190.08:01:28.77#ibcon#wrote, iclass 15, count 2 2006.190.08:01:28.77#ibcon#about to read 3, iclass 15, count 2 2006.190.08:01:28.79#ibcon#read 3, iclass 15, count 2 2006.190.08:01:28.79#ibcon#about to read 4, iclass 15, count 2 2006.190.08:01:28.79#ibcon#read 4, iclass 15, count 2 2006.190.08:01:28.79#ibcon#about to read 5, iclass 15, count 2 2006.190.08:01:28.79#ibcon#read 5, iclass 15, count 2 2006.190.08:01:28.79#ibcon#about to read 6, iclass 15, count 2 2006.190.08:01:28.79#ibcon#read 6, iclass 15, count 2 2006.190.08:01:28.79#ibcon#end of sib2, iclass 15, count 2 2006.190.08:01:28.80#ibcon#*mode == 0, iclass 15, count 2 2006.190.08:01:28.80#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.08:01:28.80#ibcon#[25=AT03-06\r\n] 2006.190.08:01:28.80#ibcon#*before write, iclass 15, count 2 2006.190.08:01:28.80#ibcon#enter sib2, iclass 15, count 2 2006.190.08:01:28.80#ibcon#flushed, iclass 15, count 2 2006.190.08:01:28.80#ibcon#about to write, iclass 15, count 2 2006.190.08:01:28.80#ibcon#wrote, iclass 15, count 2 2006.190.08:01:28.80#ibcon#about to read 3, iclass 15, count 2 2006.190.08:01:28.82#ibcon#read 3, iclass 15, count 2 2006.190.08:01:28.82#ibcon#about to read 4, iclass 15, count 2 2006.190.08:01:28.82#ibcon#read 4, iclass 15, count 2 2006.190.08:01:28.82#ibcon#about to read 5, iclass 15, count 2 2006.190.08:01:28.82#ibcon#read 5, iclass 15, count 2 2006.190.08:01:28.82#ibcon#about to read 6, iclass 15, count 2 2006.190.08:01:28.82#ibcon#read 6, iclass 15, count 2 2006.190.08:01:28.82#ibcon#end of sib2, iclass 15, count 2 2006.190.08:01:28.82#ibcon#*after write, iclass 15, count 2 2006.190.08:01:28.82#ibcon#*before return 0, iclass 15, count 2 2006.190.08:01:28.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:28.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:28.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.08:01:28.82#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:28.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:28.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:28.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:28.94#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:01:28.94#ibcon#first serial, iclass 15, count 0 2006.190.08:01:28.94#ibcon#enter sib2, iclass 15, count 0 2006.190.08:01:28.94#ibcon#flushed, iclass 15, count 0 2006.190.08:01:28.94#ibcon#about to write, iclass 15, count 0 2006.190.08:01:28.94#ibcon#wrote, iclass 15, count 0 2006.190.08:01:28.94#ibcon#about to read 3, iclass 15, count 0 2006.190.08:01:28.96#ibcon#read 3, iclass 15, count 0 2006.190.08:01:28.96#ibcon#about to read 4, iclass 15, count 0 2006.190.08:01:28.96#ibcon#read 4, iclass 15, count 0 2006.190.08:01:28.96#ibcon#about to read 5, iclass 15, count 0 2006.190.08:01:28.96#ibcon#read 5, iclass 15, count 0 2006.190.08:01:28.96#ibcon#about to read 6, iclass 15, count 0 2006.190.08:01:28.96#ibcon#read 6, iclass 15, count 0 2006.190.08:01:28.96#ibcon#end of sib2, iclass 15, count 0 2006.190.08:01:28.96#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:01:28.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:01:28.96#ibcon#[25=USB\r\n] 2006.190.08:01:28.96#ibcon#*before write, iclass 15, count 0 2006.190.08:01:28.96#ibcon#enter sib2, iclass 15, count 0 2006.190.08:01:28.96#ibcon#flushed, iclass 15, count 0 2006.190.08:01:28.96#ibcon#about to write, iclass 15, count 0 2006.190.08:01:28.96#ibcon#wrote, iclass 15, count 0 2006.190.08:01:28.96#ibcon#about to read 3, iclass 15, count 0 2006.190.08:01:28.99#ibcon#read 3, iclass 15, count 0 2006.190.08:01:28.99#ibcon#about to read 4, iclass 15, count 0 2006.190.08:01:28.99#ibcon#read 4, iclass 15, count 0 2006.190.08:01:28.99#ibcon#about to read 5, iclass 15, count 0 2006.190.08:01:28.99#ibcon#read 5, iclass 15, count 0 2006.190.08:01:28.99#ibcon#about to read 6, iclass 15, count 0 2006.190.08:01:28.99#ibcon#read 6, iclass 15, count 0 2006.190.08:01:28.99#ibcon#end of sib2, iclass 15, count 0 2006.190.08:01:28.99#ibcon#*after write, iclass 15, count 0 2006.190.08:01:28.99#ibcon#*before return 0, iclass 15, count 0 2006.190.08:01:28.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:28.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:28.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:01:28.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:01:28.99$vc4f8/valo=4,832.99 2006.190.08:01:28.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.08:01:28.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.08:01:28.99#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:28.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:28.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:28.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:28.99#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:01:28.99#ibcon#first serial, iclass 17, count 0 2006.190.08:01:28.99#ibcon#enter sib2, iclass 17, count 0 2006.190.08:01:28.99#ibcon#flushed, iclass 17, count 0 2006.190.08:01:28.99#ibcon#about to write, iclass 17, count 0 2006.190.08:01:28.99#ibcon#wrote, iclass 17, count 0 2006.190.08:01:28.99#ibcon#about to read 3, iclass 17, count 0 2006.190.08:01:29.01#ibcon#read 3, iclass 17, count 0 2006.190.08:01:29.01#ibcon#about to read 4, iclass 17, count 0 2006.190.08:01:29.01#ibcon#read 4, iclass 17, count 0 2006.190.08:01:29.01#ibcon#about to read 5, iclass 17, count 0 2006.190.08:01:29.01#ibcon#read 5, iclass 17, count 0 2006.190.08:01:29.01#ibcon#about to read 6, iclass 17, count 0 2006.190.08:01:29.01#ibcon#read 6, iclass 17, count 0 2006.190.08:01:29.01#ibcon#end of sib2, iclass 17, count 0 2006.190.08:01:29.01#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:01:29.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:01:29.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:01:29.01#ibcon#*before write, iclass 17, count 0 2006.190.08:01:29.01#ibcon#enter sib2, iclass 17, count 0 2006.190.08:01:29.01#ibcon#flushed, iclass 17, count 0 2006.190.08:01:29.01#ibcon#about to write, iclass 17, count 0 2006.190.08:01:29.01#ibcon#wrote, iclass 17, count 0 2006.190.08:01:29.01#ibcon#about to read 3, iclass 17, count 0 2006.190.08:01:29.05#ibcon#read 3, iclass 17, count 0 2006.190.08:01:29.05#ibcon#about to read 4, iclass 17, count 0 2006.190.08:01:29.05#ibcon#read 4, iclass 17, count 0 2006.190.08:01:29.05#ibcon#about to read 5, iclass 17, count 0 2006.190.08:01:29.05#ibcon#read 5, iclass 17, count 0 2006.190.08:01:29.05#ibcon#about to read 6, iclass 17, count 0 2006.190.08:01:29.05#ibcon#read 6, iclass 17, count 0 2006.190.08:01:29.05#ibcon#end of sib2, iclass 17, count 0 2006.190.08:01:29.05#ibcon#*after write, iclass 17, count 0 2006.190.08:01:29.05#ibcon#*before return 0, iclass 17, count 0 2006.190.08:01:29.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:29.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:29.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:01:29.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:01:29.05$vc4f8/va=4,7 2006.190.08:01:29.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.08:01:29.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.08:01:29.05#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:29.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:29.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:29.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:29.11#ibcon#enter wrdev, iclass 19, count 2 2006.190.08:01:29.11#ibcon#first serial, iclass 19, count 2 2006.190.08:01:29.11#ibcon#enter sib2, iclass 19, count 2 2006.190.08:01:29.11#ibcon#flushed, iclass 19, count 2 2006.190.08:01:29.11#ibcon#about to write, iclass 19, count 2 2006.190.08:01:29.11#ibcon#wrote, iclass 19, count 2 2006.190.08:01:29.11#ibcon#about to read 3, iclass 19, count 2 2006.190.08:01:29.13#ibcon#read 3, iclass 19, count 2 2006.190.08:01:29.13#ibcon#about to read 4, iclass 19, count 2 2006.190.08:01:29.13#ibcon#read 4, iclass 19, count 2 2006.190.08:01:29.13#ibcon#about to read 5, iclass 19, count 2 2006.190.08:01:29.13#ibcon#read 5, iclass 19, count 2 2006.190.08:01:29.13#ibcon#about to read 6, iclass 19, count 2 2006.190.08:01:29.13#ibcon#read 6, iclass 19, count 2 2006.190.08:01:29.13#ibcon#end of sib2, iclass 19, count 2 2006.190.08:01:29.13#ibcon#*mode == 0, iclass 19, count 2 2006.190.08:01:29.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.08:01:29.13#ibcon#[25=AT04-07\r\n] 2006.190.08:01:29.13#ibcon#*before write, iclass 19, count 2 2006.190.08:01:29.13#ibcon#enter sib2, iclass 19, count 2 2006.190.08:01:29.13#ibcon#flushed, iclass 19, count 2 2006.190.08:01:29.13#ibcon#about to write, iclass 19, count 2 2006.190.08:01:29.13#ibcon#wrote, iclass 19, count 2 2006.190.08:01:29.13#ibcon#about to read 3, iclass 19, count 2 2006.190.08:01:29.16#ibcon#read 3, iclass 19, count 2 2006.190.08:01:29.16#ibcon#about to read 4, iclass 19, count 2 2006.190.08:01:29.16#ibcon#read 4, iclass 19, count 2 2006.190.08:01:29.16#ibcon#about to read 5, iclass 19, count 2 2006.190.08:01:29.16#ibcon#read 5, iclass 19, count 2 2006.190.08:01:29.16#ibcon#about to read 6, iclass 19, count 2 2006.190.08:01:29.16#ibcon#read 6, iclass 19, count 2 2006.190.08:01:29.16#ibcon#end of sib2, iclass 19, count 2 2006.190.08:01:29.16#ibcon#*after write, iclass 19, count 2 2006.190.08:01:29.16#ibcon#*before return 0, iclass 19, count 2 2006.190.08:01:29.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:29.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:29.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.08:01:29.16#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:29.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:29.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:29.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:29.28#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:01:29.28#ibcon#first serial, iclass 19, count 0 2006.190.08:01:29.28#ibcon#enter sib2, iclass 19, count 0 2006.190.08:01:29.28#ibcon#flushed, iclass 19, count 0 2006.190.08:01:29.28#ibcon#about to write, iclass 19, count 0 2006.190.08:01:29.28#ibcon#wrote, iclass 19, count 0 2006.190.08:01:29.28#ibcon#about to read 3, iclass 19, count 0 2006.190.08:01:29.30#ibcon#read 3, iclass 19, count 0 2006.190.08:01:29.30#ibcon#about to read 4, iclass 19, count 0 2006.190.08:01:29.30#ibcon#read 4, iclass 19, count 0 2006.190.08:01:29.30#ibcon#about to read 5, iclass 19, count 0 2006.190.08:01:29.30#ibcon#read 5, iclass 19, count 0 2006.190.08:01:29.30#ibcon#about to read 6, iclass 19, count 0 2006.190.08:01:29.30#ibcon#read 6, iclass 19, count 0 2006.190.08:01:29.30#ibcon#end of sib2, iclass 19, count 0 2006.190.08:01:29.30#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:01:29.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:01:29.30#ibcon#[25=USB\r\n] 2006.190.08:01:29.30#ibcon#*before write, iclass 19, count 0 2006.190.08:01:29.30#ibcon#enter sib2, iclass 19, count 0 2006.190.08:01:29.30#ibcon#flushed, iclass 19, count 0 2006.190.08:01:29.30#ibcon#about to write, iclass 19, count 0 2006.190.08:01:29.30#ibcon#wrote, iclass 19, count 0 2006.190.08:01:29.30#ibcon#about to read 3, iclass 19, count 0 2006.190.08:01:29.33#ibcon#read 3, iclass 19, count 0 2006.190.08:01:29.33#ibcon#about to read 4, iclass 19, count 0 2006.190.08:01:29.33#ibcon#read 4, iclass 19, count 0 2006.190.08:01:29.33#ibcon#about to read 5, iclass 19, count 0 2006.190.08:01:29.33#ibcon#read 5, iclass 19, count 0 2006.190.08:01:29.33#ibcon#about to read 6, iclass 19, count 0 2006.190.08:01:29.33#ibcon#read 6, iclass 19, count 0 2006.190.08:01:29.33#ibcon#end of sib2, iclass 19, count 0 2006.190.08:01:29.33#ibcon#*after write, iclass 19, count 0 2006.190.08:01:29.33#ibcon#*before return 0, iclass 19, count 0 2006.190.08:01:29.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:29.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:29.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:01:29.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:01:29.33$vc4f8/valo=5,652.99 2006.190.08:01:29.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.08:01:29.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.08:01:29.33#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:29.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:29.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:29.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:29.33#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:01:29.33#ibcon#first serial, iclass 21, count 0 2006.190.08:01:29.33#ibcon#enter sib2, iclass 21, count 0 2006.190.08:01:29.33#ibcon#flushed, iclass 21, count 0 2006.190.08:01:29.33#ibcon#about to write, iclass 21, count 0 2006.190.08:01:29.33#ibcon#wrote, iclass 21, count 0 2006.190.08:01:29.33#ibcon#about to read 3, iclass 21, count 0 2006.190.08:01:29.35#ibcon#read 3, iclass 21, count 0 2006.190.08:01:29.35#ibcon#about to read 4, iclass 21, count 0 2006.190.08:01:29.35#ibcon#read 4, iclass 21, count 0 2006.190.08:01:29.35#ibcon#about to read 5, iclass 21, count 0 2006.190.08:01:29.35#ibcon#read 5, iclass 21, count 0 2006.190.08:01:29.35#ibcon#about to read 6, iclass 21, count 0 2006.190.08:01:29.35#ibcon#read 6, iclass 21, count 0 2006.190.08:01:29.35#ibcon#end of sib2, iclass 21, count 0 2006.190.08:01:29.35#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:01:29.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:01:29.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:01:29.35#ibcon#*before write, iclass 21, count 0 2006.190.08:01:29.35#ibcon#enter sib2, iclass 21, count 0 2006.190.08:01:29.35#ibcon#flushed, iclass 21, count 0 2006.190.08:01:29.35#ibcon#about to write, iclass 21, count 0 2006.190.08:01:29.35#ibcon#wrote, iclass 21, count 0 2006.190.08:01:29.35#ibcon#about to read 3, iclass 21, count 0 2006.190.08:01:29.39#ibcon#read 3, iclass 21, count 0 2006.190.08:01:29.39#ibcon#about to read 4, iclass 21, count 0 2006.190.08:01:29.39#ibcon#read 4, iclass 21, count 0 2006.190.08:01:29.39#ibcon#about to read 5, iclass 21, count 0 2006.190.08:01:29.39#ibcon#read 5, iclass 21, count 0 2006.190.08:01:29.39#ibcon#about to read 6, iclass 21, count 0 2006.190.08:01:29.39#ibcon#read 6, iclass 21, count 0 2006.190.08:01:29.39#ibcon#end of sib2, iclass 21, count 0 2006.190.08:01:29.39#ibcon#*after write, iclass 21, count 0 2006.190.08:01:29.39#ibcon#*before return 0, iclass 21, count 0 2006.190.08:01:29.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:29.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:29.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:01:29.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:01:29.39$vc4f8/va=5,7 2006.190.08:01:29.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.08:01:29.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.08:01:29.39#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:29.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:29.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:29.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:29.45#ibcon#enter wrdev, iclass 23, count 2 2006.190.08:01:29.45#ibcon#first serial, iclass 23, count 2 2006.190.08:01:29.45#ibcon#enter sib2, iclass 23, count 2 2006.190.08:01:29.45#ibcon#flushed, iclass 23, count 2 2006.190.08:01:29.45#ibcon#about to write, iclass 23, count 2 2006.190.08:01:29.45#ibcon#wrote, iclass 23, count 2 2006.190.08:01:29.45#ibcon#about to read 3, iclass 23, count 2 2006.190.08:01:29.47#ibcon#read 3, iclass 23, count 2 2006.190.08:01:29.47#ibcon#about to read 4, iclass 23, count 2 2006.190.08:01:29.47#ibcon#read 4, iclass 23, count 2 2006.190.08:01:29.47#ibcon#about to read 5, iclass 23, count 2 2006.190.08:01:29.47#ibcon#read 5, iclass 23, count 2 2006.190.08:01:29.47#ibcon#about to read 6, iclass 23, count 2 2006.190.08:01:29.47#ibcon#read 6, iclass 23, count 2 2006.190.08:01:29.47#ibcon#end of sib2, iclass 23, count 2 2006.190.08:01:29.47#ibcon#*mode == 0, iclass 23, count 2 2006.190.08:01:29.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.08:01:29.47#ibcon#[25=AT05-07\r\n] 2006.190.08:01:29.47#ibcon#*before write, iclass 23, count 2 2006.190.08:01:29.47#ibcon#enter sib2, iclass 23, count 2 2006.190.08:01:29.47#ibcon#flushed, iclass 23, count 2 2006.190.08:01:29.47#ibcon#about to write, iclass 23, count 2 2006.190.08:01:29.47#ibcon#wrote, iclass 23, count 2 2006.190.08:01:29.47#ibcon#about to read 3, iclass 23, count 2 2006.190.08:01:29.50#ibcon#read 3, iclass 23, count 2 2006.190.08:01:29.50#ibcon#about to read 4, iclass 23, count 2 2006.190.08:01:29.50#ibcon#read 4, iclass 23, count 2 2006.190.08:01:29.50#ibcon#about to read 5, iclass 23, count 2 2006.190.08:01:29.50#ibcon#read 5, iclass 23, count 2 2006.190.08:01:29.50#ibcon#about to read 6, iclass 23, count 2 2006.190.08:01:29.50#ibcon#read 6, iclass 23, count 2 2006.190.08:01:29.50#ibcon#end of sib2, iclass 23, count 2 2006.190.08:01:29.50#ibcon#*after write, iclass 23, count 2 2006.190.08:01:29.50#ibcon#*before return 0, iclass 23, count 2 2006.190.08:01:29.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:29.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:29.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.08:01:29.50#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:29.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:29.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:29.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:29.62#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:01:29.62#ibcon#first serial, iclass 23, count 0 2006.190.08:01:29.62#ibcon#enter sib2, iclass 23, count 0 2006.190.08:01:29.62#ibcon#flushed, iclass 23, count 0 2006.190.08:01:29.62#ibcon#about to write, iclass 23, count 0 2006.190.08:01:29.62#ibcon#wrote, iclass 23, count 0 2006.190.08:01:29.62#ibcon#about to read 3, iclass 23, count 0 2006.190.08:01:29.64#ibcon#read 3, iclass 23, count 0 2006.190.08:01:29.64#ibcon#about to read 4, iclass 23, count 0 2006.190.08:01:29.64#ibcon#read 4, iclass 23, count 0 2006.190.08:01:29.64#ibcon#about to read 5, iclass 23, count 0 2006.190.08:01:29.64#ibcon#read 5, iclass 23, count 0 2006.190.08:01:29.64#ibcon#about to read 6, iclass 23, count 0 2006.190.08:01:29.64#ibcon#read 6, iclass 23, count 0 2006.190.08:01:29.64#ibcon#end of sib2, iclass 23, count 0 2006.190.08:01:29.64#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:01:29.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:01:29.64#ibcon#[25=USB\r\n] 2006.190.08:01:29.64#ibcon#*before write, iclass 23, count 0 2006.190.08:01:29.64#ibcon#enter sib2, iclass 23, count 0 2006.190.08:01:29.64#ibcon#flushed, iclass 23, count 0 2006.190.08:01:29.64#ibcon#about to write, iclass 23, count 0 2006.190.08:01:29.64#ibcon#wrote, iclass 23, count 0 2006.190.08:01:29.64#ibcon#about to read 3, iclass 23, count 0 2006.190.08:01:29.67#ibcon#read 3, iclass 23, count 0 2006.190.08:01:29.67#ibcon#about to read 4, iclass 23, count 0 2006.190.08:01:29.67#ibcon#read 4, iclass 23, count 0 2006.190.08:01:29.67#ibcon#about to read 5, iclass 23, count 0 2006.190.08:01:29.67#ibcon#read 5, iclass 23, count 0 2006.190.08:01:29.67#ibcon#about to read 6, iclass 23, count 0 2006.190.08:01:29.67#ibcon#read 6, iclass 23, count 0 2006.190.08:01:29.67#ibcon#end of sib2, iclass 23, count 0 2006.190.08:01:29.67#ibcon#*after write, iclass 23, count 0 2006.190.08:01:29.67#ibcon#*before return 0, iclass 23, count 0 2006.190.08:01:29.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:29.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:29.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:01:29.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:01:29.67$vc4f8/valo=6,772.99 2006.190.08:01:29.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.08:01:29.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.08:01:29.67#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:29.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:29.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:29.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:29.67#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:01:29.67#ibcon#first serial, iclass 25, count 0 2006.190.08:01:29.67#ibcon#enter sib2, iclass 25, count 0 2006.190.08:01:29.67#ibcon#flushed, iclass 25, count 0 2006.190.08:01:29.67#ibcon#about to write, iclass 25, count 0 2006.190.08:01:29.67#ibcon#wrote, iclass 25, count 0 2006.190.08:01:29.67#ibcon#about to read 3, iclass 25, count 0 2006.190.08:01:29.69#ibcon#read 3, iclass 25, count 0 2006.190.08:01:29.69#ibcon#about to read 4, iclass 25, count 0 2006.190.08:01:29.69#ibcon#read 4, iclass 25, count 0 2006.190.08:01:29.69#ibcon#about to read 5, iclass 25, count 0 2006.190.08:01:29.69#ibcon#read 5, iclass 25, count 0 2006.190.08:01:29.69#ibcon#about to read 6, iclass 25, count 0 2006.190.08:01:29.69#ibcon#read 6, iclass 25, count 0 2006.190.08:01:29.69#ibcon#end of sib2, iclass 25, count 0 2006.190.08:01:29.69#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:01:29.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:01:29.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:01:29.69#ibcon#*before write, iclass 25, count 0 2006.190.08:01:29.69#ibcon#enter sib2, iclass 25, count 0 2006.190.08:01:29.69#ibcon#flushed, iclass 25, count 0 2006.190.08:01:29.69#ibcon#about to write, iclass 25, count 0 2006.190.08:01:29.69#ibcon#wrote, iclass 25, count 0 2006.190.08:01:29.69#ibcon#about to read 3, iclass 25, count 0 2006.190.08:01:29.73#ibcon#read 3, iclass 25, count 0 2006.190.08:01:29.73#ibcon#about to read 4, iclass 25, count 0 2006.190.08:01:29.73#ibcon#read 4, iclass 25, count 0 2006.190.08:01:29.73#ibcon#about to read 5, iclass 25, count 0 2006.190.08:01:29.73#ibcon#read 5, iclass 25, count 0 2006.190.08:01:29.73#ibcon#about to read 6, iclass 25, count 0 2006.190.08:01:29.73#ibcon#read 6, iclass 25, count 0 2006.190.08:01:29.73#ibcon#end of sib2, iclass 25, count 0 2006.190.08:01:29.73#ibcon#*after write, iclass 25, count 0 2006.190.08:01:29.73#ibcon#*before return 0, iclass 25, count 0 2006.190.08:01:29.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:29.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:29.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:01:29.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:01:29.73$vc4f8/va=6,6 2006.190.08:01:29.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.08:01:29.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.08:01:29.73#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:29.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:29.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:29.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:29.79#ibcon#enter wrdev, iclass 27, count 2 2006.190.08:01:29.79#ibcon#first serial, iclass 27, count 2 2006.190.08:01:29.79#ibcon#enter sib2, iclass 27, count 2 2006.190.08:01:29.79#ibcon#flushed, iclass 27, count 2 2006.190.08:01:29.79#ibcon#about to write, iclass 27, count 2 2006.190.08:01:29.79#ibcon#wrote, iclass 27, count 2 2006.190.08:01:29.79#ibcon#about to read 3, iclass 27, count 2 2006.190.08:01:29.81#ibcon#read 3, iclass 27, count 2 2006.190.08:01:29.81#ibcon#about to read 4, iclass 27, count 2 2006.190.08:01:29.81#ibcon#read 4, iclass 27, count 2 2006.190.08:01:29.81#ibcon#about to read 5, iclass 27, count 2 2006.190.08:01:29.81#ibcon#read 5, iclass 27, count 2 2006.190.08:01:29.81#ibcon#about to read 6, iclass 27, count 2 2006.190.08:01:29.81#ibcon#read 6, iclass 27, count 2 2006.190.08:01:29.81#ibcon#end of sib2, iclass 27, count 2 2006.190.08:01:29.81#ibcon#*mode == 0, iclass 27, count 2 2006.190.08:01:29.81#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.08:01:29.81#ibcon#[25=AT06-06\r\n] 2006.190.08:01:29.81#ibcon#*before write, iclass 27, count 2 2006.190.08:01:29.81#ibcon#enter sib2, iclass 27, count 2 2006.190.08:01:29.81#ibcon#flushed, iclass 27, count 2 2006.190.08:01:29.81#ibcon#about to write, iclass 27, count 2 2006.190.08:01:29.81#ibcon#wrote, iclass 27, count 2 2006.190.08:01:29.81#ibcon#about to read 3, iclass 27, count 2 2006.190.08:01:29.84#ibcon#read 3, iclass 27, count 2 2006.190.08:01:29.84#ibcon#about to read 4, iclass 27, count 2 2006.190.08:01:29.84#ibcon#read 4, iclass 27, count 2 2006.190.08:01:29.84#ibcon#about to read 5, iclass 27, count 2 2006.190.08:01:29.84#ibcon#read 5, iclass 27, count 2 2006.190.08:01:29.84#ibcon#about to read 6, iclass 27, count 2 2006.190.08:01:29.84#ibcon#read 6, iclass 27, count 2 2006.190.08:01:29.84#ibcon#end of sib2, iclass 27, count 2 2006.190.08:01:29.84#ibcon#*after write, iclass 27, count 2 2006.190.08:01:29.84#ibcon#*before return 0, iclass 27, count 2 2006.190.08:01:29.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:29.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:29.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.08:01:29.84#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:29.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:29.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:29.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:29.96#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:01:29.96#ibcon#first serial, iclass 27, count 0 2006.190.08:01:29.96#ibcon#enter sib2, iclass 27, count 0 2006.190.08:01:29.96#ibcon#flushed, iclass 27, count 0 2006.190.08:01:29.96#ibcon#about to write, iclass 27, count 0 2006.190.08:01:29.96#ibcon#wrote, iclass 27, count 0 2006.190.08:01:29.96#ibcon#about to read 3, iclass 27, count 0 2006.190.08:01:29.98#ibcon#read 3, iclass 27, count 0 2006.190.08:01:29.98#ibcon#about to read 4, iclass 27, count 0 2006.190.08:01:29.98#ibcon#read 4, iclass 27, count 0 2006.190.08:01:29.98#ibcon#about to read 5, iclass 27, count 0 2006.190.08:01:29.98#ibcon#read 5, iclass 27, count 0 2006.190.08:01:29.98#ibcon#about to read 6, iclass 27, count 0 2006.190.08:01:29.98#ibcon#read 6, iclass 27, count 0 2006.190.08:01:29.98#ibcon#end of sib2, iclass 27, count 0 2006.190.08:01:29.98#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:01:29.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:01:29.98#ibcon#[25=USB\r\n] 2006.190.08:01:29.98#ibcon#*before write, iclass 27, count 0 2006.190.08:01:29.98#ibcon#enter sib2, iclass 27, count 0 2006.190.08:01:29.98#ibcon#flushed, iclass 27, count 0 2006.190.08:01:29.98#ibcon#about to write, iclass 27, count 0 2006.190.08:01:29.98#ibcon#wrote, iclass 27, count 0 2006.190.08:01:29.98#ibcon#about to read 3, iclass 27, count 0 2006.190.08:01:30.01#ibcon#read 3, iclass 27, count 0 2006.190.08:01:30.01#ibcon#about to read 4, iclass 27, count 0 2006.190.08:01:30.01#ibcon#read 4, iclass 27, count 0 2006.190.08:01:30.01#ibcon#about to read 5, iclass 27, count 0 2006.190.08:01:30.01#ibcon#read 5, iclass 27, count 0 2006.190.08:01:30.01#ibcon#about to read 6, iclass 27, count 0 2006.190.08:01:30.01#ibcon#read 6, iclass 27, count 0 2006.190.08:01:30.01#ibcon#end of sib2, iclass 27, count 0 2006.190.08:01:30.01#ibcon#*after write, iclass 27, count 0 2006.190.08:01:30.01#ibcon#*before return 0, iclass 27, count 0 2006.190.08:01:30.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:30.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:30.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:01:30.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:01:30.01$vc4f8/valo=7,832.99 2006.190.08:01:30.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.08:01:30.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.08:01:30.01#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:30.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:30.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:30.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:30.01#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:01:30.01#ibcon#first serial, iclass 29, count 0 2006.190.08:01:30.01#ibcon#enter sib2, iclass 29, count 0 2006.190.08:01:30.01#ibcon#flushed, iclass 29, count 0 2006.190.08:01:30.01#ibcon#about to write, iclass 29, count 0 2006.190.08:01:30.01#ibcon#wrote, iclass 29, count 0 2006.190.08:01:30.01#ibcon#about to read 3, iclass 29, count 0 2006.190.08:01:30.03#ibcon#read 3, iclass 29, count 0 2006.190.08:01:30.03#ibcon#about to read 4, iclass 29, count 0 2006.190.08:01:30.03#ibcon#read 4, iclass 29, count 0 2006.190.08:01:30.03#ibcon#about to read 5, iclass 29, count 0 2006.190.08:01:30.03#ibcon#read 5, iclass 29, count 0 2006.190.08:01:30.03#ibcon#about to read 6, iclass 29, count 0 2006.190.08:01:30.03#ibcon#read 6, iclass 29, count 0 2006.190.08:01:30.03#ibcon#end of sib2, iclass 29, count 0 2006.190.08:01:30.03#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:01:30.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:01:30.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:01:30.03#ibcon#*before write, iclass 29, count 0 2006.190.08:01:30.03#ibcon#enter sib2, iclass 29, count 0 2006.190.08:01:30.03#ibcon#flushed, iclass 29, count 0 2006.190.08:01:30.03#ibcon#about to write, iclass 29, count 0 2006.190.08:01:30.03#ibcon#wrote, iclass 29, count 0 2006.190.08:01:30.03#ibcon#about to read 3, iclass 29, count 0 2006.190.08:01:30.07#ibcon#read 3, iclass 29, count 0 2006.190.08:01:30.07#ibcon#about to read 4, iclass 29, count 0 2006.190.08:01:30.07#ibcon#read 4, iclass 29, count 0 2006.190.08:01:30.07#ibcon#about to read 5, iclass 29, count 0 2006.190.08:01:30.07#ibcon#read 5, iclass 29, count 0 2006.190.08:01:30.07#ibcon#about to read 6, iclass 29, count 0 2006.190.08:01:30.07#ibcon#read 6, iclass 29, count 0 2006.190.08:01:30.07#ibcon#end of sib2, iclass 29, count 0 2006.190.08:01:30.07#ibcon#*after write, iclass 29, count 0 2006.190.08:01:30.07#ibcon#*before return 0, iclass 29, count 0 2006.190.08:01:30.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:30.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:30.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:01:30.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:01:30.07$vc4f8/va=7,6 2006.190.08:01:30.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.08:01:30.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.08:01:30.07#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:30.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:01:30.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:01:30.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:01:30.13#ibcon#enter wrdev, iclass 31, count 2 2006.190.08:01:30.13#ibcon#first serial, iclass 31, count 2 2006.190.08:01:30.13#ibcon#enter sib2, iclass 31, count 2 2006.190.08:01:30.13#ibcon#flushed, iclass 31, count 2 2006.190.08:01:30.13#ibcon#about to write, iclass 31, count 2 2006.190.08:01:30.13#ibcon#wrote, iclass 31, count 2 2006.190.08:01:30.13#ibcon#about to read 3, iclass 31, count 2 2006.190.08:01:30.15#ibcon#read 3, iclass 31, count 2 2006.190.08:01:30.15#ibcon#about to read 4, iclass 31, count 2 2006.190.08:01:30.15#ibcon#read 4, iclass 31, count 2 2006.190.08:01:30.15#ibcon#about to read 5, iclass 31, count 2 2006.190.08:01:30.15#ibcon#read 5, iclass 31, count 2 2006.190.08:01:30.15#ibcon#about to read 6, iclass 31, count 2 2006.190.08:01:30.15#ibcon#read 6, iclass 31, count 2 2006.190.08:01:30.15#ibcon#end of sib2, iclass 31, count 2 2006.190.08:01:30.15#ibcon#*mode == 0, iclass 31, count 2 2006.190.08:01:30.15#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.08:01:30.15#ibcon#[25=AT07-06\r\n] 2006.190.08:01:30.15#ibcon#*before write, iclass 31, count 2 2006.190.08:01:30.15#ibcon#enter sib2, iclass 31, count 2 2006.190.08:01:30.15#ibcon#flushed, iclass 31, count 2 2006.190.08:01:30.15#ibcon#about to write, iclass 31, count 2 2006.190.08:01:30.15#ibcon#wrote, iclass 31, count 2 2006.190.08:01:30.15#ibcon#about to read 3, iclass 31, count 2 2006.190.08:01:30.18#ibcon#read 3, iclass 31, count 2 2006.190.08:01:30.18#ibcon#about to read 4, iclass 31, count 2 2006.190.08:01:30.18#ibcon#read 4, iclass 31, count 2 2006.190.08:01:30.18#ibcon#about to read 5, iclass 31, count 2 2006.190.08:01:30.18#ibcon#read 5, iclass 31, count 2 2006.190.08:01:30.18#ibcon#about to read 6, iclass 31, count 2 2006.190.08:01:30.18#ibcon#read 6, iclass 31, count 2 2006.190.08:01:30.18#ibcon#end of sib2, iclass 31, count 2 2006.190.08:01:30.18#ibcon#*after write, iclass 31, count 2 2006.190.08:01:30.18#ibcon#*before return 0, iclass 31, count 2 2006.190.08:01:30.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:01:30.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:01:30.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.08:01:30.18#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:30.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:01:30.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:01:30.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:01:30.30#ibcon#enter wrdev, iclass 31, count 0 2006.190.08:01:30.30#ibcon#first serial, iclass 31, count 0 2006.190.08:01:30.30#ibcon#enter sib2, iclass 31, count 0 2006.190.08:01:30.30#ibcon#flushed, iclass 31, count 0 2006.190.08:01:30.30#ibcon#about to write, iclass 31, count 0 2006.190.08:01:30.30#ibcon#wrote, iclass 31, count 0 2006.190.08:01:30.30#ibcon#about to read 3, iclass 31, count 0 2006.190.08:01:30.32#ibcon#read 3, iclass 31, count 0 2006.190.08:01:30.32#ibcon#about to read 4, iclass 31, count 0 2006.190.08:01:30.32#ibcon#read 4, iclass 31, count 0 2006.190.08:01:30.32#ibcon#about to read 5, iclass 31, count 0 2006.190.08:01:30.32#ibcon#read 5, iclass 31, count 0 2006.190.08:01:30.32#ibcon#about to read 6, iclass 31, count 0 2006.190.08:01:30.32#ibcon#read 6, iclass 31, count 0 2006.190.08:01:30.32#ibcon#end of sib2, iclass 31, count 0 2006.190.08:01:30.32#ibcon#*mode == 0, iclass 31, count 0 2006.190.08:01:30.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.08:01:30.32#ibcon#[25=USB\r\n] 2006.190.08:01:30.32#ibcon#*before write, iclass 31, count 0 2006.190.08:01:30.32#ibcon#enter sib2, iclass 31, count 0 2006.190.08:01:30.32#ibcon#flushed, iclass 31, count 0 2006.190.08:01:30.32#ibcon#about to write, iclass 31, count 0 2006.190.08:01:30.32#ibcon#wrote, iclass 31, count 0 2006.190.08:01:30.32#ibcon#about to read 3, iclass 31, count 0 2006.190.08:01:30.35#ibcon#read 3, iclass 31, count 0 2006.190.08:01:30.35#ibcon#about to read 4, iclass 31, count 0 2006.190.08:01:30.35#ibcon#read 4, iclass 31, count 0 2006.190.08:01:30.35#ibcon#about to read 5, iclass 31, count 0 2006.190.08:01:30.35#ibcon#read 5, iclass 31, count 0 2006.190.08:01:30.35#ibcon#about to read 6, iclass 31, count 0 2006.190.08:01:30.35#ibcon#read 6, iclass 31, count 0 2006.190.08:01:30.35#ibcon#end of sib2, iclass 31, count 0 2006.190.08:01:30.35#ibcon#*after write, iclass 31, count 0 2006.190.08:01:30.35#ibcon#*before return 0, iclass 31, count 0 2006.190.08:01:30.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:01:30.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:01:30.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.08:01:30.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.08:01:30.35$vc4f8/valo=8,852.99 2006.190.08:01:30.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.08:01:30.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.08:01:30.35#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:30.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:01:30.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:01:30.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:01:30.35#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:01:30.35#ibcon#first serial, iclass 34, count 0 2006.190.08:01:30.35#ibcon#enter sib2, iclass 34, count 0 2006.190.08:01:30.35#ibcon#flushed, iclass 34, count 0 2006.190.08:01:30.35#ibcon#about to write, iclass 34, count 0 2006.190.08:01:30.35#ibcon#wrote, iclass 34, count 0 2006.190.08:01:30.35#ibcon#about to read 3, iclass 34, count 0 2006.190.08:01:30.37#ibcon#read 3, iclass 34, count 0 2006.190.08:01:30.37#ibcon#about to read 4, iclass 34, count 0 2006.190.08:01:30.37#ibcon#read 4, iclass 34, count 0 2006.190.08:01:30.37#ibcon#about to read 5, iclass 34, count 0 2006.190.08:01:30.37#ibcon#read 5, iclass 34, count 0 2006.190.08:01:30.37#ibcon#about to read 6, iclass 34, count 0 2006.190.08:01:30.37#ibcon#read 6, iclass 34, count 0 2006.190.08:01:30.37#ibcon#end of sib2, iclass 34, count 0 2006.190.08:01:30.37#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:01:30.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:01:30.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:01:30.37#ibcon#*before write, iclass 34, count 0 2006.190.08:01:30.37#ibcon#enter sib2, iclass 34, count 0 2006.190.08:01:30.37#ibcon#flushed, iclass 34, count 0 2006.190.08:01:30.37#ibcon#about to write, iclass 34, count 0 2006.190.08:01:30.37#ibcon#wrote, iclass 34, count 0 2006.190.08:01:30.37#ibcon#about to read 3, iclass 34, count 0 2006.190.08:01:30.39#abcon#<5=/05 2.3 4.0 24.521001012.0\r\n> 2006.190.08:01:30.40#abcon#{5=INTERFACE CLEAR} 2006.190.08:01:30.41#ibcon#read 3, iclass 34, count 0 2006.190.08:01:30.41#ibcon#about to read 4, iclass 34, count 0 2006.190.08:01:30.41#ibcon#read 4, iclass 34, count 0 2006.190.08:01:30.41#ibcon#about to read 5, iclass 34, count 0 2006.190.08:01:30.41#ibcon#read 5, iclass 34, count 0 2006.190.08:01:30.41#ibcon#about to read 6, iclass 34, count 0 2006.190.08:01:30.41#ibcon#read 6, iclass 34, count 0 2006.190.08:01:30.41#ibcon#end of sib2, iclass 34, count 0 2006.190.08:01:30.41#ibcon#*after write, iclass 34, count 0 2006.190.08:01:30.41#ibcon#*before return 0, iclass 34, count 0 2006.190.08:01:30.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:01:30.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:01:30.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:01:30.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:01:30.41$vc4f8/va=8,6 2006.190.08:01:30.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.08:01:30.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.08:01:30.41#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:30.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:01:30.46#abcon#[5=S1D000X0/0*\r\n] 2006.190.08:01:30.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:01:30.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:01:30.47#ibcon#enter wrdev, iclass 38, count 2 2006.190.08:01:30.47#ibcon#first serial, iclass 38, count 2 2006.190.08:01:30.47#ibcon#enter sib2, iclass 38, count 2 2006.190.08:01:30.47#ibcon#flushed, iclass 38, count 2 2006.190.08:01:30.47#ibcon#about to write, iclass 38, count 2 2006.190.08:01:30.47#ibcon#wrote, iclass 38, count 2 2006.190.08:01:30.47#ibcon#about to read 3, iclass 38, count 2 2006.190.08:01:30.49#ibcon#read 3, iclass 38, count 2 2006.190.08:01:30.49#ibcon#about to read 4, iclass 38, count 2 2006.190.08:01:30.49#ibcon#read 4, iclass 38, count 2 2006.190.08:01:30.49#ibcon#about to read 5, iclass 38, count 2 2006.190.08:01:30.49#ibcon#read 5, iclass 38, count 2 2006.190.08:01:30.49#ibcon#about to read 6, iclass 38, count 2 2006.190.08:01:30.49#ibcon#read 6, iclass 38, count 2 2006.190.08:01:30.49#ibcon#end of sib2, iclass 38, count 2 2006.190.08:01:30.49#ibcon#*mode == 0, iclass 38, count 2 2006.190.08:01:30.49#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.08:01:30.49#ibcon#[25=AT08-06\r\n] 2006.190.08:01:30.49#ibcon#*before write, iclass 38, count 2 2006.190.08:01:30.49#ibcon#enter sib2, iclass 38, count 2 2006.190.08:01:30.49#ibcon#flushed, iclass 38, count 2 2006.190.08:01:30.49#ibcon#about to write, iclass 38, count 2 2006.190.08:01:30.49#ibcon#wrote, iclass 38, count 2 2006.190.08:01:30.49#ibcon#about to read 3, iclass 38, count 2 2006.190.08:01:30.52#ibcon#read 3, iclass 38, count 2 2006.190.08:01:30.52#ibcon#about to read 4, iclass 38, count 2 2006.190.08:01:30.52#ibcon#read 4, iclass 38, count 2 2006.190.08:01:30.52#ibcon#about to read 5, iclass 38, count 2 2006.190.08:01:30.52#ibcon#read 5, iclass 38, count 2 2006.190.08:01:30.52#ibcon#about to read 6, iclass 38, count 2 2006.190.08:01:30.52#ibcon#read 6, iclass 38, count 2 2006.190.08:01:30.52#ibcon#end of sib2, iclass 38, count 2 2006.190.08:01:30.52#ibcon#*after write, iclass 38, count 2 2006.190.08:01:30.52#ibcon#*before return 0, iclass 38, count 2 2006.190.08:01:30.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:01:30.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:01:30.52#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.08:01:30.52#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:30.52#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:01:30.64#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:01:30.64#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:01:30.64#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:01:30.64#ibcon#first serial, iclass 38, count 0 2006.190.08:01:30.64#ibcon#enter sib2, iclass 38, count 0 2006.190.08:01:30.64#ibcon#flushed, iclass 38, count 0 2006.190.08:01:30.64#ibcon#about to write, iclass 38, count 0 2006.190.08:01:30.64#ibcon#wrote, iclass 38, count 0 2006.190.08:01:30.64#ibcon#about to read 3, iclass 38, count 0 2006.190.08:01:30.66#ibcon#read 3, iclass 38, count 0 2006.190.08:01:30.66#ibcon#about to read 4, iclass 38, count 0 2006.190.08:01:30.66#ibcon#read 4, iclass 38, count 0 2006.190.08:01:30.66#ibcon#about to read 5, iclass 38, count 0 2006.190.08:01:30.66#ibcon#read 5, iclass 38, count 0 2006.190.08:01:30.66#ibcon#about to read 6, iclass 38, count 0 2006.190.08:01:30.66#ibcon#read 6, iclass 38, count 0 2006.190.08:01:30.66#ibcon#end of sib2, iclass 38, count 0 2006.190.08:01:30.66#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:01:30.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:01:30.66#ibcon#[25=USB\r\n] 2006.190.08:01:30.66#ibcon#*before write, iclass 38, count 0 2006.190.08:01:30.66#ibcon#enter sib2, iclass 38, count 0 2006.190.08:01:30.66#ibcon#flushed, iclass 38, count 0 2006.190.08:01:30.66#ibcon#about to write, iclass 38, count 0 2006.190.08:01:30.66#ibcon#wrote, iclass 38, count 0 2006.190.08:01:30.66#ibcon#about to read 3, iclass 38, count 0 2006.190.08:01:30.69#ibcon#read 3, iclass 38, count 0 2006.190.08:01:30.69#ibcon#about to read 4, iclass 38, count 0 2006.190.08:01:30.69#ibcon#read 4, iclass 38, count 0 2006.190.08:01:30.69#ibcon#about to read 5, iclass 38, count 0 2006.190.08:01:30.69#ibcon#read 5, iclass 38, count 0 2006.190.08:01:30.69#ibcon#about to read 6, iclass 38, count 0 2006.190.08:01:30.69#ibcon#read 6, iclass 38, count 0 2006.190.08:01:30.69#ibcon#end of sib2, iclass 38, count 0 2006.190.08:01:30.69#ibcon#*after write, iclass 38, count 0 2006.190.08:01:30.69#ibcon#*before return 0, iclass 38, count 0 2006.190.08:01:30.69#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:01:30.69#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:01:30.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:01:30.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:01:30.69$vc4f8/vblo=1,632.99 2006.190.08:01:30.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.08:01:30.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.08:01:30.69#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:30.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:30.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:30.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:30.69#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:01:30.69#ibcon#first serial, iclass 3, count 0 2006.190.08:01:30.69#ibcon#enter sib2, iclass 3, count 0 2006.190.08:01:30.69#ibcon#flushed, iclass 3, count 0 2006.190.08:01:30.69#ibcon#about to write, iclass 3, count 0 2006.190.08:01:30.69#ibcon#wrote, iclass 3, count 0 2006.190.08:01:30.69#ibcon#about to read 3, iclass 3, count 0 2006.190.08:01:30.71#ibcon#read 3, iclass 3, count 0 2006.190.08:01:30.71#ibcon#about to read 4, iclass 3, count 0 2006.190.08:01:30.71#ibcon#read 4, iclass 3, count 0 2006.190.08:01:30.71#ibcon#about to read 5, iclass 3, count 0 2006.190.08:01:30.71#ibcon#read 5, iclass 3, count 0 2006.190.08:01:30.71#ibcon#about to read 6, iclass 3, count 0 2006.190.08:01:30.71#ibcon#read 6, iclass 3, count 0 2006.190.08:01:30.71#ibcon#end of sib2, iclass 3, count 0 2006.190.08:01:30.71#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:01:30.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:01:30.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:01:30.71#ibcon#*before write, iclass 3, count 0 2006.190.08:01:30.71#ibcon#enter sib2, iclass 3, count 0 2006.190.08:01:30.71#ibcon#flushed, iclass 3, count 0 2006.190.08:01:30.71#ibcon#about to write, iclass 3, count 0 2006.190.08:01:30.71#ibcon#wrote, iclass 3, count 0 2006.190.08:01:30.71#ibcon#about to read 3, iclass 3, count 0 2006.190.08:01:30.75#ibcon#read 3, iclass 3, count 0 2006.190.08:01:30.75#ibcon#about to read 4, iclass 3, count 0 2006.190.08:01:30.75#ibcon#read 4, iclass 3, count 0 2006.190.08:01:30.75#ibcon#about to read 5, iclass 3, count 0 2006.190.08:01:30.75#ibcon#read 5, iclass 3, count 0 2006.190.08:01:30.75#ibcon#about to read 6, iclass 3, count 0 2006.190.08:01:30.75#ibcon#read 6, iclass 3, count 0 2006.190.08:01:30.75#ibcon#end of sib2, iclass 3, count 0 2006.190.08:01:30.75#ibcon#*after write, iclass 3, count 0 2006.190.08:01:30.75#ibcon#*before return 0, iclass 3, count 0 2006.190.08:01:30.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:30.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:01:30.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:01:30.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:01:30.75$vc4f8/vb=1,4 2006.190.08:01:30.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.08:01:30.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.08:01:30.75#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:30.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:30.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:30.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:30.75#ibcon#enter wrdev, iclass 5, count 2 2006.190.08:01:30.75#ibcon#first serial, iclass 5, count 2 2006.190.08:01:30.75#ibcon#enter sib2, iclass 5, count 2 2006.190.08:01:30.75#ibcon#flushed, iclass 5, count 2 2006.190.08:01:30.75#ibcon#about to write, iclass 5, count 2 2006.190.08:01:30.75#ibcon#wrote, iclass 5, count 2 2006.190.08:01:30.75#ibcon#about to read 3, iclass 5, count 2 2006.190.08:01:30.77#ibcon#read 3, iclass 5, count 2 2006.190.08:01:30.77#ibcon#about to read 4, iclass 5, count 2 2006.190.08:01:30.77#ibcon#read 4, iclass 5, count 2 2006.190.08:01:30.77#ibcon#about to read 5, iclass 5, count 2 2006.190.08:01:30.77#ibcon#read 5, iclass 5, count 2 2006.190.08:01:30.77#ibcon#about to read 6, iclass 5, count 2 2006.190.08:01:30.77#ibcon#read 6, iclass 5, count 2 2006.190.08:01:30.77#ibcon#end of sib2, iclass 5, count 2 2006.190.08:01:30.77#ibcon#*mode == 0, iclass 5, count 2 2006.190.08:01:30.77#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.08:01:30.77#ibcon#[27=AT01-04\r\n] 2006.190.08:01:30.77#ibcon#*before write, iclass 5, count 2 2006.190.08:01:30.77#ibcon#enter sib2, iclass 5, count 2 2006.190.08:01:30.77#ibcon#flushed, iclass 5, count 2 2006.190.08:01:30.77#ibcon#about to write, iclass 5, count 2 2006.190.08:01:30.77#ibcon#wrote, iclass 5, count 2 2006.190.08:01:30.77#ibcon#about to read 3, iclass 5, count 2 2006.190.08:01:30.80#ibcon#read 3, iclass 5, count 2 2006.190.08:01:30.80#ibcon#about to read 4, iclass 5, count 2 2006.190.08:01:30.80#ibcon#read 4, iclass 5, count 2 2006.190.08:01:30.80#ibcon#about to read 5, iclass 5, count 2 2006.190.08:01:30.80#ibcon#read 5, iclass 5, count 2 2006.190.08:01:30.80#ibcon#about to read 6, iclass 5, count 2 2006.190.08:01:30.80#ibcon#read 6, iclass 5, count 2 2006.190.08:01:30.80#ibcon#end of sib2, iclass 5, count 2 2006.190.08:01:30.80#ibcon#*after write, iclass 5, count 2 2006.190.08:01:30.80#ibcon#*before return 0, iclass 5, count 2 2006.190.08:01:30.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:30.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:01:30.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.08:01:30.80#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:30.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:30.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:30.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:30.92#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:01:30.92#ibcon#first serial, iclass 5, count 0 2006.190.08:01:30.92#ibcon#enter sib2, iclass 5, count 0 2006.190.08:01:30.92#ibcon#flushed, iclass 5, count 0 2006.190.08:01:30.92#ibcon#about to write, iclass 5, count 0 2006.190.08:01:30.92#ibcon#wrote, iclass 5, count 0 2006.190.08:01:30.92#ibcon#about to read 3, iclass 5, count 0 2006.190.08:01:30.94#ibcon#read 3, iclass 5, count 0 2006.190.08:01:30.94#ibcon#about to read 4, iclass 5, count 0 2006.190.08:01:30.94#ibcon#read 4, iclass 5, count 0 2006.190.08:01:30.94#ibcon#about to read 5, iclass 5, count 0 2006.190.08:01:30.94#ibcon#read 5, iclass 5, count 0 2006.190.08:01:30.94#ibcon#about to read 6, iclass 5, count 0 2006.190.08:01:30.94#ibcon#read 6, iclass 5, count 0 2006.190.08:01:30.94#ibcon#end of sib2, iclass 5, count 0 2006.190.08:01:30.94#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:01:30.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:01:30.94#ibcon#[27=USB\r\n] 2006.190.08:01:30.94#ibcon#*before write, iclass 5, count 0 2006.190.08:01:30.94#ibcon#enter sib2, iclass 5, count 0 2006.190.08:01:30.94#ibcon#flushed, iclass 5, count 0 2006.190.08:01:30.94#ibcon#about to write, iclass 5, count 0 2006.190.08:01:30.94#ibcon#wrote, iclass 5, count 0 2006.190.08:01:30.94#ibcon#about to read 3, iclass 5, count 0 2006.190.08:01:30.97#ibcon#read 3, iclass 5, count 0 2006.190.08:01:30.97#ibcon#about to read 4, iclass 5, count 0 2006.190.08:01:30.97#ibcon#read 4, iclass 5, count 0 2006.190.08:01:30.97#ibcon#about to read 5, iclass 5, count 0 2006.190.08:01:30.97#ibcon#read 5, iclass 5, count 0 2006.190.08:01:30.97#ibcon#about to read 6, iclass 5, count 0 2006.190.08:01:30.97#ibcon#read 6, iclass 5, count 0 2006.190.08:01:30.97#ibcon#end of sib2, iclass 5, count 0 2006.190.08:01:30.97#ibcon#*after write, iclass 5, count 0 2006.190.08:01:30.97#ibcon#*before return 0, iclass 5, count 0 2006.190.08:01:30.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:30.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:01:30.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:01:30.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:01:30.97$vc4f8/vblo=2,640.99 2006.190.08:01:30.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.08:01:30.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.08:01:30.97#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:30.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:30.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:30.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:30.97#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:01:30.97#ibcon#first serial, iclass 7, count 0 2006.190.08:01:30.97#ibcon#enter sib2, iclass 7, count 0 2006.190.08:01:30.97#ibcon#flushed, iclass 7, count 0 2006.190.08:01:30.97#ibcon#about to write, iclass 7, count 0 2006.190.08:01:30.97#ibcon#wrote, iclass 7, count 0 2006.190.08:01:30.97#ibcon#about to read 3, iclass 7, count 0 2006.190.08:01:30.99#ibcon#read 3, iclass 7, count 0 2006.190.08:01:30.99#ibcon#about to read 4, iclass 7, count 0 2006.190.08:01:30.99#ibcon#read 4, iclass 7, count 0 2006.190.08:01:30.99#ibcon#about to read 5, iclass 7, count 0 2006.190.08:01:30.99#ibcon#read 5, iclass 7, count 0 2006.190.08:01:30.99#ibcon#about to read 6, iclass 7, count 0 2006.190.08:01:30.99#ibcon#read 6, iclass 7, count 0 2006.190.08:01:30.99#ibcon#end of sib2, iclass 7, count 0 2006.190.08:01:30.99#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:01:30.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:01:30.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:01:30.99#ibcon#*before write, iclass 7, count 0 2006.190.08:01:30.99#ibcon#enter sib2, iclass 7, count 0 2006.190.08:01:30.99#ibcon#flushed, iclass 7, count 0 2006.190.08:01:30.99#ibcon#about to write, iclass 7, count 0 2006.190.08:01:30.99#ibcon#wrote, iclass 7, count 0 2006.190.08:01:30.99#ibcon#about to read 3, iclass 7, count 0 2006.190.08:01:31.03#ibcon#read 3, iclass 7, count 0 2006.190.08:01:31.03#ibcon#about to read 4, iclass 7, count 0 2006.190.08:01:31.03#ibcon#read 4, iclass 7, count 0 2006.190.08:01:31.03#ibcon#about to read 5, iclass 7, count 0 2006.190.08:01:31.03#ibcon#read 5, iclass 7, count 0 2006.190.08:01:31.03#ibcon#about to read 6, iclass 7, count 0 2006.190.08:01:31.03#ibcon#read 6, iclass 7, count 0 2006.190.08:01:31.03#ibcon#end of sib2, iclass 7, count 0 2006.190.08:01:31.03#ibcon#*after write, iclass 7, count 0 2006.190.08:01:31.03#ibcon#*before return 0, iclass 7, count 0 2006.190.08:01:31.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:31.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:01:31.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:01:31.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:01:31.03$vc4f8/vb=2,4 2006.190.08:01:31.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.08:01:31.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.08:01:31.03#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:31.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:31.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:31.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:31.09#ibcon#enter wrdev, iclass 11, count 2 2006.190.08:01:31.09#ibcon#first serial, iclass 11, count 2 2006.190.08:01:31.09#ibcon#enter sib2, iclass 11, count 2 2006.190.08:01:31.09#ibcon#flushed, iclass 11, count 2 2006.190.08:01:31.09#ibcon#about to write, iclass 11, count 2 2006.190.08:01:31.09#ibcon#wrote, iclass 11, count 2 2006.190.08:01:31.09#ibcon#about to read 3, iclass 11, count 2 2006.190.08:01:31.11#ibcon#read 3, iclass 11, count 2 2006.190.08:01:31.11#ibcon#about to read 4, iclass 11, count 2 2006.190.08:01:31.11#ibcon#read 4, iclass 11, count 2 2006.190.08:01:31.11#ibcon#about to read 5, iclass 11, count 2 2006.190.08:01:31.11#ibcon#read 5, iclass 11, count 2 2006.190.08:01:31.11#ibcon#about to read 6, iclass 11, count 2 2006.190.08:01:31.11#ibcon#read 6, iclass 11, count 2 2006.190.08:01:31.11#ibcon#end of sib2, iclass 11, count 2 2006.190.08:01:31.11#ibcon#*mode == 0, iclass 11, count 2 2006.190.08:01:31.11#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.08:01:31.11#ibcon#[27=AT02-04\r\n] 2006.190.08:01:31.11#ibcon#*before write, iclass 11, count 2 2006.190.08:01:31.11#ibcon#enter sib2, iclass 11, count 2 2006.190.08:01:31.11#ibcon#flushed, iclass 11, count 2 2006.190.08:01:31.11#ibcon#about to write, iclass 11, count 2 2006.190.08:01:31.11#ibcon#wrote, iclass 11, count 2 2006.190.08:01:31.11#ibcon#about to read 3, iclass 11, count 2 2006.190.08:01:31.14#ibcon#read 3, iclass 11, count 2 2006.190.08:01:31.14#ibcon#about to read 4, iclass 11, count 2 2006.190.08:01:31.14#ibcon#read 4, iclass 11, count 2 2006.190.08:01:31.14#ibcon#about to read 5, iclass 11, count 2 2006.190.08:01:31.14#ibcon#read 5, iclass 11, count 2 2006.190.08:01:31.14#ibcon#about to read 6, iclass 11, count 2 2006.190.08:01:31.14#ibcon#read 6, iclass 11, count 2 2006.190.08:01:31.14#ibcon#end of sib2, iclass 11, count 2 2006.190.08:01:31.14#ibcon#*after write, iclass 11, count 2 2006.190.08:01:31.14#ibcon#*before return 0, iclass 11, count 2 2006.190.08:01:31.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:31.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:01:31.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.08:01:31.14#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:31.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:31.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:31.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:31.26#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:01:31.26#ibcon#first serial, iclass 11, count 0 2006.190.08:01:31.26#ibcon#enter sib2, iclass 11, count 0 2006.190.08:01:31.26#ibcon#flushed, iclass 11, count 0 2006.190.08:01:31.26#ibcon#about to write, iclass 11, count 0 2006.190.08:01:31.26#ibcon#wrote, iclass 11, count 0 2006.190.08:01:31.26#ibcon#about to read 3, iclass 11, count 0 2006.190.08:01:31.28#ibcon#read 3, iclass 11, count 0 2006.190.08:01:31.28#ibcon#about to read 4, iclass 11, count 0 2006.190.08:01:31.28#ibcon#read 4, iclass 11, count 0 2006.190.08:01:31.28#ibcon#about to read 5, iclass 11, count 0 2006.190.08:01:31.28#ibcon#read 5, iclass 11, count 0 2006.190.08:01:31.28#ibcon#about to read 6, iclass 11, count 0 2006.190.08:01:31.28#ibcon#read 6, iclass 11, count 0 2006.190.08:01:31.28#ibcon#end of sib2, iclass 11, count 0 2006.190.08:01:31.28#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:01:31.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:01:31.28#ibcon#[27=USB\r\n] 2006.190.08:01:31.28#ibcon#*before write, iclass 11, count 0 2006.190.08:01:31.28#ibcon#enter sib2, iclass 11, count 0 2006.190.08:01:31.28#ibcon#flushed, iclass 11, count 0 2006.190.08:01:31.28#ibcon#about to write, iclass 11, count 0 2006.190.08:01:31.28#ibcon#wrote, iclass 11, count 0 2006.190.08:01:31.28#ibcon#about to read 3, iclass 11, count 0 2006.190.08:01:31.31#ibcon#read 3, iclass 11, count 0 2006.190.08:01:31.31#ibcon#about to read 4, iclass 11, count 0 2006.190.08:01:31.31#ibcon#read 4, iclass 11, count 0 2006.190.08:01:31.31#ibcon#about to read 5, iclass 11, count 0 2006.190.08:01:31.31#ibcon#read 5, iclass 11, count 0 2006.190.08:01:31.31#ibcon#about to read 6, iclass 11, count 0 2006.190.08:01:31.31#ibcon#read 6, iclass 11, count 0 2006.190.08:01:31.31#ibcon#end of sib2, iclass 11, count 0 2006.190.08:01:31.31#ibcon#*after write, iclass 11, count 0 2006.190.08:01:31.31#ibcon#*before return 0, iclass 11, count 0 2006.190.08:01:31.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:31.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:01:31.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:01:31.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:01:31.31$vc4f8/vblo=3,656.99 2006.190.08:01:31.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.08:01:31.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.08:01:31.31#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:31.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:31.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:31.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:31.31#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:01:31.31#ibcon#first serial, iclass 13, count 0 2006.190.08:01:31.31#ibcon#enter sib2, iclass 13, count 0 2006.190.08:01:31.31#ibcon#flushed, iclass 13, count 0 2006.190.08:01:31.31#ibcon#about to write, iclass 13, count 0 2006.190.08:01:31.31#ibcon#wrote, iclass 13, count 0 2006.190.08:01:31.31#ibcon#about to read 3, iclass 13, count 0 2006.190.08:01:31.33#ibcon#read 3, iclass 13, count 0 2006.190.08:01:31.33#ibcon#about to read 4, iclass 13, count 0 2006.190.08:01:31.33#ibcon#read 4, iclass 13, count 0 2006.190.08:01:31.33#ibcon#about to read 5, iclass 13, count 0 2006.190.08:01:31.33#ibcon#read 5, iclass 13, count 0 2006.190.08:01:31.33#ibcon#about to read 6, iclass 13, count 0 2006.190.08:01:31.33#ibcon#read 6, iclass 13, count 0 2006.190.08:01:31.33#ibcon#end of sib2, iclass 13, count 0 2006.190.08:01:31.33#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:01:31.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:01:31.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:01:31.33#ibcon#*before write, iclass 13, count 0 2006.190.08:01:31.33#ibcon#enter sib2, iclass 13, count 0 2006.190.08:01:31.33#ibcon#flushed, iclass 13, count 0 2006.190.08:01:31.33#ibcon#about to write, iclass 13, count 0 2006.190.08:01:31.33#ibcon#wrote, iclass 13, count 0 2006.190.08:01:31.33#ibcon#about to read 3, iclass 13, count 0 2006.190.08:01:31.37#ibcon#read 3, iclass 13, count 0 2006.190.08:01:31.37#ibcon#about to read 4, iclass 13, count 0 2006.190.08:01:31.37#ibcon#read 4, iclass 13, count 0 2006.190.08:01:31.37#ibcon#about to read 5, iclass 13, count 0 2006.190.08:01:31.37#ibcon#read 5, iclass 13, count 0 2006.190.08:01:31.37#ibcon#about to read 6, iclass 13, count 0 2006.190.08:01:31.37#ibcon#read 6, iclass 13, count 0 2006.190.08:01:31.37#ibcon#end of sib2, iclass 13, count 0 2006.190.08:01:31.37#ibcon#*after write, iclass 13, count 0 2006.190.08:01:31.37#ibcon#*before return 0, iclass 13, count 0 2006.190.08:01:31.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:31.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:01:31.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:01:31.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:01:31.37$vc4f8/vb=3,4 2006.190.08:01:31.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.08:01:31.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.08:01:31.37#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:31.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:31.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:31.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:31.43#ibcon#enter wrdev, iclass 15, count 2 2006.190.08:01:31.43#ibcon#first serial, iclass 15, count 2 2006.190.08:01:31.43#ibcon#enter sib2, iclass 15, count 2 2006.190.08:01:31.43#ibcon#flushed, iclass 15, count 2 2006.190.08:01:31.43#ibcon#about to write, iclass 15, count 2 2006.190.08:01:31.43#ibcon#wrote, iclass 15, count 2 2006.190.08:01:31.43#ibcon#about to read 3, iclass 15, count 2 2006.190.08:01:31.45#ibcon#read 3, iclass 15, count 2 2006.190.08:01:31.45#ibcon#about to read 4, iclass 15, count 2 2006.190.08:01:31.45#ibcon#read 4, iclass 15, count 2 2006.190.08:01:31.45#ibcon#about to read 5, iclass 15, count 2 2006.190.08:01:31.45#ibcon#read 5, iclass 15, count 2 2006.190.08:01:31.45#ibcon#about to read 6, iclass 15, count 2 2006.190.08:01:31.45#ibcon#read 6, iclass 15, count 2 2006.190.08:01:31.45#ibcon#end of sib2, iclass 15, count 2 2006.190.08:01:31.45#ibcon#*mode == 0, iclass 15, count 2 2006.190.08:01:31.45#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.08:01:31.45#ibcon#[27=AT03-04\r\n] 2006.190.08:01:31.45#ibcon#*before write, iclass 15, count 2 2006.190.08:01:31.45#ibcon#enter sib2, iclass 15, count 2 2006.190.08:01:31.45#ibcon#flushed, iclass 15, count 2 2006.190.08:01:31.45#ibcon#about to write, iclass 15, count 2 2006.190.08:01:31.45#ibcon#wrote, iclass 15, count 2 2006.190.08:01:31.45#ibcon#about to read 3, iclass 15, count 2 2006.190.08:01:31.48#ibcon#read 3, iclass 15, count 2 2006.190.08:01:31.48#ibcon#about to read 4, iclass 15, count 2 2006.190.08:01:31.48#ibcon#read 4, iclass 15, count 2 2006.190.08:01:31.48#ibcon#about to read 5, iclass 15, count 2 2006.190.08:01:31.48#ibcon#read 5, iclass 15, count 2 2006.190.08:01:31.48#ibcon#about to read 6, iclass 15, count 2 2006.190.08:01:31.48#ibcon#read 6, iclass 15, count 2 2006.190.08:01:31.48#ibcon#end of sib2, iclass 15, count 2 2006.190.08:01:31.48#ibcon#*after write, iclass 15, count 2 2006.190.08:01:31.48#ibcon#*before return 0, iclass 15, count 2 2006.190.08:01:31.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:31.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:01:31.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.08:01:31.48#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:31.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:31.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:31.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:31.60#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:01:31.60#ibcon#first serial, iclass 15, count 0 2006.190.08:01:31.60#ibcon#enter sib2, iclass 15, count 0 2006.190.08:01:31.60#ibcon#flushed, iclass 15, count 0 2006.190.08:01:31.60#ibcon#about to write, iclass 15, count 0 2006.190.08:01:31.60#ibcon#wrote, iclass 15, count 0 2006.190.08:01:31.60#ibcon#about to read 3, iclass 15, count 0 2006.190.08:01:31.62#ibcon#read 3, iclass 15, count 0 2006.190.08:01:31.62#ibcon#about to read 4, iclass 15, count 0 2006.190.08:01:31.62#ibcon#read 4, iclass 15, count 0 2006.190.08:01:31.62#ibcon#about to read 5, iclass 15, count 0 2006.190.08:01:31.62#ibcon#read 5, iclass 15, count 0 2006.190.08:01:31.62#ibcon#about to read 6, iclass 15, count 0 2006.190.08:01:31.62#ibcon#read 6, iclass 15, count 0 2006.190.08:01:31.62#ibcon#end of sib2, iclass 15, count 0 2006.190.08:01:31.62#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:01:31.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:01:31.62#ibcon#[27=USB\r\n] 2006.190.08:01:31.62#ibcon#*before write, iclass 15, count 0 2006.190.08:01:31.62#ibcon#enter sib2, iclass 15, count 0 2006.190.08:01:31.62#ibcon#flushed, iclass 15, count 0 2006.190.08:01:31.62#ibcon#about to write, iclass 15, count 0 2006.190.08:01:31.62#ibcon#wrote, iclass 15, count 0 2006.190.08:01:31.62#ibcon#about to read 3, iclass 15, count 0 2006.190.08:01:31.65#ibcon#read 3, iclass 15, count 0 2006.190.08:01:31.65#ibcon#about to read 4, iclass 15, count 0 2006.190.08:01:31.65#ibcon#read 4, iclass 15, count 0 2006.190.08:01:31.65#ibcon#about to read 5, iclass 15, count 0 2006.190.08:01:31.65#ibcon#read 5, iclass 15, count 0 2006.190.08:01:31.65#ibcon#about to read 6, iclass 15, count 0 2006.190.08:01:31.65#ibcon#read 6, iclass 15, count 0 2006.190.08:01:31.65#ibcon#end of sib2, iclass 15, count 0 2006.190.08:01:31.65#ibcon#*after write, iclass 15, count 0 2006.190.08:01:31.65#ibcon#*before return 0, iclass 15, count 0 2006.190.08:01:31.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:31.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:01:31.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:01:31.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:01:31.65$vc4f8/vblo=4,712.99 2006.190.08:01:31.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.08:01:31.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.08:01:31.65#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:31.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:31.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:31.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:31.65#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:01:31.65#ibcon#first serial, iclass 17, count 0 2006.190.08:01:31.65#ibcon#enter sib2, iclass 17, count 0 2006.190.08:01:31.65#ibcon#flushed, iclass 17, count 0 2006.190.08:01:31.65#ibcon#about to write, iclass 17, count 0 2006.190.08:01:31.65#ibcon#wrote, iclass 17, count 0 2006.190.08:01:31.65#ibcon#about to read 3, iclass 17, count 0 2006.190.08:01:31.67#ibcon#read 3, iclass 17, count 0 2006.190.08:01:31.67#ibcon#about to read 4, iclass 17, count 0 2006.190.08:01:31.67#ibcon#read 4, iclass 17, count 0 2006.190.08:01:31.67#ibcon#about to read 5, iclass 17, count 0 2006.190.08:01:31.67#ibcon#read 5, iclass 17, count 0 2006.190.08:01:31.67#ibcon#about to read 6, iclass 17, count 0 2006.190.08:01:31.67#ibcon#read 6, iclass 17, count 0 2006.190.08:01:31.67#ibcon#end of sib2, iclass 17, count 0 2006.190.08:01:31.67#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:01:31.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:01:31.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:01:31.67#ibcon#*before write, iclass 17, count 0 2006.190.08:01:31.67#ibcon#enter sib2, iclass 17, count 0 2006.190.08:01:31.67#ibcon#flushed, iclass 17, count 0 2006.190.08:01:31.67#ibcon#about to write, iclass 17, count 0 2006.190.08:01:31.67#ibcon#wrote, iclass 17, count 0 2006.190.08:01:31.67#ibcon#about to read 3, iclass 17, count 0 2006.190.08:01:31.71#ibcon#read 3, iclass 17, count 0 2006.190.08:01:31.71#ibcon#about to read 4, iclass 17, count 0 2006.190.08:01:31.71#ibcon#read 4, iclass 17, count 0 2006.190.08:01:31.71#ibcon#about to read 5, iclass 17, count 0 2006.190.08:01:31.71#ibcon#read 5, iclass 17, count 0 2006.190.08:01:31.71#ibcon#about to read 6, iclass 17, count 0 2006.190.08:01:31.71#ibcon#read 6, iclass 17, count 0 2006.190.08:01:31.71#ibcon#end of sib2, iclass 17, count 0 2006.190.08:01:31.71#ibcon#*after write, iclass 17, count 0 2006.190.08:01:31.71#ibcon#*before return 0, iclass 17, count 0 2006.190.08:01:31.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:31.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:01:31.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:01:31.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:01:31.71$vc4f8/vb=4,4 2006.190.08:01:31.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.08:01:31.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.08:01:31.71#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:31.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:31.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:31.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:31.77#ibcon#enter wrdev, iclass 19, count 2 2006.190.08:01:31.77#ibcon#first serial, iclass 19, count 2 2006.190.08:01:31.77#ibcon#enter sib2, iclass 19, count 2 2006.190.08:01:31.77#ibcon#flushed, iclass 19, count 2 2006.190.08:01:31.77#ibcon#about to write, iclass 19, count 2 2006.190.08:01:31.77#ibcon#wrote, iclass 19, count 2 2006.190.08:01:31.77#ibcon#about to read 3, iclass 19, count 2 2006.190.08:01:31.79#ibcon#read 3, iclass 19, count 2 2006.190.08:01:31.79#ibcon#about to read 4, iclass 19, count 2 2006.190.08:01:31.79#ibcon#read 4, iclass 19, count 2 2006.190.08:01:31.79#ibcon#about to read 5, iclass 19, count 2 2006.190.08:01:31.79#ibcon#read 5, iclass 19, count 2 2006.190.08:01:31.79#ibcon#about to read 6, iclass 19, count 2 2006.190.08:01:31.79#ibcon#read 6, iclass 19, count 2 2006.190.08:01:31.79#ibcon#end of sib2, iclass 19, count 2 2006.190.08:01:31.79#ibcon#*mode == 0, iclass 19, count 2 2006.190.08:01:31.79#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.08:01:31.79#ibcon#[27=AT04-04\r\n] 2006.190.08:01:31.79#ibcon#*before write, iclass 19, count 2 2006.190.08:01:31.79#ibcon#enter sib2, iclass 19, count 2 2006.190.08:01:31.79#ibcon#flushed, iclass 19, count 2 2006.190.08:01:31.79#ibcon#about to write, iclass 19, count 2 2006.190.08:01:31.79#ibcon#wrote, iclass 19, count 2 2006.190.08:01:31.79#ibcon#about to read 3, iclass 19, count 2 2006.190.08:01:31.82#ibcon#read 3, iclass 19, count 2 2006.190.08:01:31.82#ibcon#about to read 4, iclass 19, count 2 2006.190.08:01:31.82#ibcon#read 4, iclass 19, count 2 2006.190.08:01:31.82#ibcon#about to read 5, iclass 19, count 2 2006.190.08:01:31.82#ibcon#read 5, iclass 19, count 2 2006.190.08:01:31.82#ibcon#about to read 6, iclass 19, count 2 2006.190.08:01:31.82#ibcon#read 6, iclass 19, count 2 2006.190.08:01:31.82#ibcon#end of sib2, iclass 19, count 2 2006.190.08:01:31.82#ibcon#*after write, iclass 19, count 2 2006.190.08:01:31.82#ibcon#*before return 0, iclass 19, count 2 2006.190.08:01:31.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:31.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:01:31.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.08:01:31.82#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:31.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:31.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:31.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:31.94#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:01:31.94#ibcon#first serial, iclass 19, count 0 2006.190.08:01:31.94#ibcon#enter sib2, iclass 19, count 0 2006.190.08:01:31.94#ibcon#flushed, iclass 19, count 0 2006.190.08:01:31.94#ibcon#about to write, iclass 19, count 0 2006.190.08:01:31.94#ibcon#wrote, iclass 19, count 0 2006.190.08:01:31.94#ibcon#about to read 3, iclass 19, count 0 2006.190.08:01:31.96#ibcon#read 3, iclass 19, count 0 2006.190.08:01:31.96#ibcon#about to read 4, iclass 19, count 0 2006.190.08:01:31.96#ibcon#read 4, iclass 19, count 0 2006.190.08:01:31.96#ibcon#about to read 5, iclass 19, count 0 2006.190.08:01:31.96#ibcon#read 5, iclass 19, count 0 2006.190.08:01:31.96#ibcon#about to read 6, iclass 19, count 0 2006.190.08:01:31.96#ibcon#read 6, iclass 19, count 0 2006.190.08:01:31.96#ibcon#end of sib2, iclass 19, count 0 2006.190.08:01:31.96#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:01:31.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:01:31.96#ibcon#[27=USB\r\n] 2006.190.08:01:31.96#ibcon#*before write, iclass 19, count 0 2006.190.08:01:31.96#ibcon#enter sib2, iclass 19, count 0 2006.190.08:01:31.96#ibcon#flushed, iclass 19, count 0 2006.190.08:01:31.96#ibcon#about to write, iclass 19, count 0 2006.190.08:01:31.96#ibcon#wrote, iclass 19, count 0 2006.190.08:01:31.96#ibcon#about to read 3, iclass 19, count 0 2006.190.08:01:31.99#ibcon#read 3, iclass 19, count 0 2006.190.08:01:31.99#ibcon#about to read 4, iclass 19, count 0 2006.190.08:01:31.99#ibcon#read 4, iclass 19, count 0 2006.190.08:01:31.99#ibcon#about to read 5, iclass 19, count 0 2006.190.08:01:31.99#ibcon#read 5, iclass 19, count 0 2006.190.08:01:31.99#ibcon#about to read 6, iclass 19, count 0 2006.190.08:01:31.99#ibcon#read 6, iclass 19, count 0 2006.190.08:01:31.99#ibcon#end of sib2, iclass 19, count 0 2006.190.08:01:31.99#ibcon#*after write, iclass 19, count 0 2006.190.08:01:31.99#ibcon#*before return 0, iclass 19, count 0 2006.190.08:01:31.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:31.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:01:31.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:01:31.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:01:31.99$vc4f8/vblo=5,744.99 2006.190.08:01:31.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.08:01:31.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.08:01:31.99#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:31.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:31.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:31.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:31.99#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:01:31.99#ibcon#first serial, iclass 21, count 0 2006.190.08:01:31.99#ibcon#enter sib2, iclass 21, count 0 2006.190.08:01:31.99#ibcon#flushed, iclass 21, count 0 2006.190.08:01:31.99#ibcon#about to write, iclass 21, count 0 2006.190.08:01:31.99#ibcon#wrote, iclass 21, count 0 2006.190.08:01:31.99#ibcon#about to read 3, iclass 21, count 0 2006.190.08:01:32.01#ibcon#read 3, iclass 21, count 0 2006.190.08:01:32.01#ibcon#about to read 4, iclass 21, count 0 2006.190.08:01:32.01#ibcon#read 4, iclass 21, count 0 2006.190.08:01:32.01#ibcon#about to read 5, iclass 21, count 0 2006.190.08:01:32.01#ibcon#read 5, iclass 21, count 0 2006.190.08:01:32.01#ibcon#about to read 6, iclass 21, count 0 2006.190.08:01:32.01#ibcon#read 6, iclass 21, count 0 2006.190.08:01:32.01#ibcon#end of sib2, iclass 21, count 0 2006.190.08:01:32.01#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:01:32.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:01:32.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:01:32.01#ibcon#*before write, iclass 21, count 0 2006.190.08:01:32.01#ibcon#enter sib2, iclass 21, count 0 2006.190.08:01:32.01#ibcon#flushed, iclass 21, count 0 2006.190.08:01:32.01#ibcon#about to write, iclass 21, count 0 2006.190.08:01:32.01#ibcon#wrote, iclass 21, count 0 2006.190.08:01:32.01#ibcon#about to read 3, iclass 21, count 0 2006.190.08:01:32.05#ibcon#read 3, iclass 21, count 0 2006.190.08:01:32.05#ibcon#about to read 4, iclass 21, count 0 2006.190.08:01:32.05#ibcon#read 4, iclass 21, count 0 2006.190.08:01:32.05#ibcon#about to read 5, iclass 21, count 0 2006.190.08:01:32.05#ibcon#read 5, iclass 21, count 0 2006.190.08:01:32.05#ibcon#about to read 6, iclass 21, count 0 2006.190.08:01:32.05#ibcon#read 6, iclass 21, count 0 2006.190.08:01:32.05#ibcon#end of sib2, iclass 21, count 0 2006.190.08:01:32.05#ibcon#*after write, iclass 21, count 0 2006.190.08:01:32.05#ibcon#*before return 0, iclass 21, count 0 2006.190.08:01:32.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:32.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:01:32.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:01:32.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:01:32.05$vc4f8/vb=5,4 2006.190.08:01:32.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.08:01:32.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.08:01:32.05#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:32.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:32.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:32.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:32.11#ibcon#enter wrdev, iclass 23, count 2 2006.190.08:01:32.11#ibcon#first serial, iclass 23, count 2 2006.190.08:01:32.11#ibcon#enter sib2, iclass 23, count 2 2006.190.08:01:32.11#ibcon#flushed, iclass 23, count 2 2006.190.08:01:32.11#ibcon#about to write, iclass 23, count 2 2006.190.08:01:32.11#ibcon#wrote, iclass 23, count 2 2006.190.08:01:32.11#ibcon#about to read 3, iclass 23, count 2 2006.190.08:01:32.13#ibcon#read 3, iclass 23, count 2 2006.190.08:01:32.13#ibcon#about to read 4, iclass 23, count 2 2006.190.08:01:32.13#ibcon#read 4, iclass 23, count 2 2006.190.08:01:32.13#ibcon#about to read 5, iclass 23, count 2 2006.190.08:01:32.13#ibcon#read 5, iclass 23, count 2 2006.190.08:01:32.13#ibcon#about to read 6, iclass 23, count 2 2006.190.08:01:32.13#ibcon#read 6, iclass 23, count 2 2006.190.08:01:32.13#ibcon#end of sib2, iclass 23, count 2 2006.190.08:01:32.13#ibcon#*mode == 0, iclass 23, count 2 2006.190.08:01:32.13#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.08:01:32.13#ibcon#[27=AT05-04\r\n] 2006.190.08:01:32.13#ibcon#*before write, iclass 23, count 2 2006.190.08:01:32.13#ibcon#enter sib2, iclass 23, count 2 2006.190.08:01:32.13#ibcon#flushed, iclass 23, count 2 2006.190.08:01:32.13#ibcon#about to write, iclass 23, count 2 2006.190.08:01:32.13#ibcon#wrote, iclass 23, count 2 2006.190.08:01:32.13#ibcon#about to read 3, iclass 23, count 2 2006.190.08:01:32.16#ibcon#read 3, iclass 23, count 2 2006.190.08:01:32.16#ibcon#about to read 4, iclass 23, count 2 2006.190.08:01:32.16#ibcon#read 4, iclass 23, count 2 2006.190.08:01:32.16#ibcon#about to read 5, iclass 23, count 2 2006.190.08:01:32.16#ibcon#read 5, iclass 23, count 2 2006.190.08:01:32.16#ibcon#about to read 6, iclass 23, count 2 2006.190.08:01:32.16#ibcon#read 6, iclass 23, count 2 2006.190.08:01:32.16#ibcon#end of sib2, iclass 23, count 2 2006.190.08:01:32.16#ibcon#*after write, iclass 23, count 2 2006.190.08:01:32.16#ibcon#*before return 0, iclass 23, count 2 2006.190.08:01:32.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:32.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:01:32.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.08:01:32.16#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:32.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:32.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:32.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:32.28#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:01:32.28#ibcon#first serial, iclass 23, count 0 2006.190.08:01:32.28#ibcon#enter sib2, iclass 23, count 0 2006.190.08:01:32.28#ibcon#flushed, iclass 23, count 0 2006.190.08:01:32.28#ibcon#about to write, iclass 23, count 0 2006.190.08:01:32.28#ibcon#wrote, iclass 23, count 0 2006.190.08:01:32.28#ibcon#about to read 3, iclass 23, count 0 2006.190.08:01:32.30#ibcon#read 3, iclass 23, count 0 2006.190.08:01:32.30#ibcon#about to read 4, iclass 23, count 0 2006.190.08:01:32.30#ibcon#read 4, iclass 23, count 0 2006.190.08:01:32.30#ibcon#about to read 5, iclass 23, count 0 2006.190.08:01:32.30#ibcon#read 5, iclass 23, count 0 2006.190.08:01:32.30#ibcon#about to read 6, iclass 23, count 0 2006.190.08:01:32.30#ibcon#read 6, iclass 23, count 0 2006.190.08:01:32.30#ibcon#end of sib2, iclass 23, count 0 2006.190.08:01:32.30#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:01:32.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:01:32.30#ibcon#[27=USB\r\n] 2006.190.08:01:32.30#ibcon#*before write, iclass 23, count 0 2006.190.08:01:32.30#ibcon#enter sib2, iclass 23, count 0 2006.190.08:01:32.30#ibcon#flushed, iclass 23, count 0 2006.190.08:01:32.30#ibcon#about to write, iclass 23, count 0 2006.190.08:01:32.30#ibcon#wrote, iclass 23, count 0 2006.190.08:01:32.30#ibcon#about to read 3, iclass 23, count 0 2006.190.08:01:32.33#ibcon#read 3, iclass 23, count 0 2006.190.08:01:32.33#ibcon#about to read 4, iclass 23, count 0 2006.190.08:01:32.33#ibcon#read 4, iclass 23, count 0 2006.190.08:01:32.33#ibcon#about to read 5, iclass 23, count 0 2006.190.08:01:32.33#ibcon#read 5, iclass 23, count 0 2006.190.08:01:32.33#ibcon#about to read 6, iclass 23, count 0 2006.190.08:01:32.33#ibcon#read 6, iclass 23, count 0 2006.190.08:01:32.33#ibcon#end of sib2, iclass 23, count 0 2006.190.08:01:32.33#ibcon#*after write, iclass 23, count 0 2006.190.08:01:32.33#ibcon#*before return 0, iclass 23, count 0 2006.190.08:01:32.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:32.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:01:32.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:01:32.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:01:32.33$vc4f8/vblo=6,752.99 2006.190.08:01:32.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.08:01:32.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.08:01:32.33#ibcon#ireg 17 cls_cnt 0 2006.190.08:01:32.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:32.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:32.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:32.33#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:01:32.33#ibcon#first serial, iclass 25, count 0 2006.190.08:01:32.33#ibcon#enter sib2, iclass 25, count 0 2006.190.08:01:32.33#ibcon#flushed, iclass 25, count 0 2006.190.08:01:32.33#ibcon#about to write, iclass 25, count 0 2006.190.08:01:32.33#ibcon#wrote, iclass 25, count 0 2006.190.08:01:32.33#ibcon#about to read 3, iclass 25, count 0 2006.190.08:01:32.35#ibcon#read 3, iclass 25, count 0 2006.190.08:01:32.35#ibcon#about to read 4, iclass 25, count 0 2006.190.08:01:32.35#ibcon#read 4, iclass 25, count 0 2006.190.08:01:32.35#ibcon#about to read 5, iclass 25, count 0 2006.190.08:01:32.35#ibcon#read 5, iclass 25, count 0 2006.190.08:01:32.35#ibcon#about to read 6, iclass 25, count 0 2006.190.08:01:32.35#ibcon#read 6, iclass 25, count 0 2006.190.08:01:32.35#ibcon#end of sib2, iclass 25, count 0 2006.190.08:01:32.35#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:01:32.35#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:01:32.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:01:32.35#ibcon#*before write, iclass 25, count 0 2006.190.08:01:32.35#ibcon#enter sib2, iclass 25, count 0 2006.190.08:01:32.35#ibcon#flushed, iclass 25, count 0 2006.190.08:01:32.35#ibcon#about to write, iclass 25, count 0 2006.190.08:01:32.35#ibcon#wrote, iclass 25, count 0 2006.190.08:01:32.35#ibcon#about to read 3, iclass 25, count 0 2006.190.08:01:32.39#ibcon#read 3, iclass 25, count 0 2006.190.08:01:32.39#ibcon#about to read 4, iclass 25, count 0 2006.190.08:01:32.39#ibcon#read 4, iclass 25, count 0 2006.190.08:01:32.39#ibcon#about to read 5, iclass 25, count 0 2006.190.08:01:32.39#ibcon#read 5, iclass 25, count 0 2006.190.08:01:32.39#ibcon#about to read 6, iclass 25, count 0 2006.190.08:01:32.39#ibcon#read 6, iclass 25, count 0 2006.190.08:01:32.39#ibcon#end of sib2, iclass 25, count 0 2006.190.08:01:32.39#ibcon#*after write, iclass 25, count 0 2006.190.08:01:32.39#ibcon#*before return 0, iclass 25, count 0 2006.190.08:01:32.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:32.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:01:32.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:01:32.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:01:32.39$vc4f8/vb=6,4 2006.190.08:01:32.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.08:01:32.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.08:01:32.39#ibcon#ireg 11 cls_cnt 2 2006.190.08:01:32.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:32.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:32.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:32.45#ibcon#enter wrdev, iclass 27, count 2 2006.190.08:01:32.45#ibcon#first serial, iclass 27, count 2 2006.190.08:01:32.45#ibcon#enter sib2, iclass 27, count 2 2006.190.08:01:32.45#ibcon#flushed, iclass 27, count 2 2006.190.08:01:32.45#ibcon#about to write, iclass 27, count 2 2006.190.08:01:32.45#ibcon#wrote, iclass 27, count 2 2006.190.08:01:32.45#ibcon#about to read 3, iclass 27, count 2 2006.190.08:01:32.47#ibcon#read 3, iclass 27, count 2 2006.190.08:01:32.47#ibcon#about to read 4, iclass 27, count 2 2006.190.08:01:32.47#ibcon#read 4, iclass 27, count 2 2006.190.08:01:32.47#ibcon#about to read 5, iclass 27, count 2 2006.190.08:01:32.47#ibcon#read 5, iclass 27, count 2 2006.190.08:01:32.47#ibcon#about to read 6, iclass 27, count 2 2006.190.08:01:32.47#ibcon#read 6, iclass 27, count 2 2006.190.08:01:32.47#ibcon#end of sib2, iclass 27, count 2 2006.190.08:01:32.47#ibcon#*mode == 0, iclass 27, count 2 2006.190.08:01:32.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.08:01:32.47#ibcon#[27=AT06-04\r\n] 2006.190.08:01:32.47#ibcon#*before write, iclass 27, count 2 2006.190.08:01:32.47#ibcon#enter sib2, iclass 27, count 2 2006.190.08:01:32.47#ibcon#flushed, iclass 27, count 2 2006.190.08:01:32.47#ibcon#about to write, iclass 27, count 2 2006.190.08:01:32.47#ibcon#wrote, iclass 27, count 2 2006.190.08:01:32.47#ibcon#about to read 3, iclass 27, count 2 2006.190.08:01:32.50#ibcon#read 3, iclass 27, count 2 2006.190.08:01:32.50#ibcon#about to read 4, iclass 27, count 2 2006.190.08:01:32.50#ibcon#read 4, iclass 27, count 2 2006.190.08:01:32.50#ibcon#about to read 5, iclass 27, count 2 2006.190.08:01:32.50#ibcon#read 5, iclass 27, count 2 2006.190.08:01:32.50#ibcon#about to read 6, iclass 27, count 2 2006.190.08:01:32.50#ibcon#read 6, iclass 27, count 2 2006.190.08:01:32.50#ibcon#end of sib2, iclass 27, count 2 2006.190.08:01:32.50#ibcon#*after write, iclass 27, count 2 2006.190.08:01:32.50#ibcon#*before return 0, iclass 27, count 2 2006.190.08:01:32.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:32.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:01:32.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.08:01:32.50#ibcon#ireg 7 cls_cnt 0 2006.190.08:01:32.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:32.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:32.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:32.62#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:01:32.62#ibcon#first serial, iclass 27, count 0 2006.190.08:01:32.62#ibcon#enter sib2, iclass 27, count 0 2006.190.08:01:32.62#ibcon#flushed, iclass 27, count 0 2006.190.08:01:32.62#ibcon#about to write, iclass 27, count 0 2006.190.08:01:32.62#ibcon#wrote, iclass 27, count 0 2006.190.08:01:32.62#ibcon#about to read 3, iclass 27, count 0 2006.190.08:01:32.64#ibcon#read 3, iclass 27, count 0 2006.190.08:01:32.64#ibcon#about to read 4, iclass 27, count 0 2006.190.08:01:32.64#ibcon#read 4, iclass 27, count 0 2006.190.08:01:32.64#ibcon#about to read 5, iclass 27, count 0 2006.190.08:01:32.64#ibcon#read 5, iclass 27, count 0 2006.190.08:01:32.64#ibcon#about to read 6, iclass 27, count 0 2006.190.08:01:32.64#ibcon#read 6, iclass 27, count 0 2006.190.08:01:32.64#ibcon#end of sib2, iclass 27, count 0 2006.190.08:01:32.64#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:01:32.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:01:32.64#ibcon#[27=USB\r\n] 2006.190.08:01:32.64#ibcon#*before write, iclass 27, count 0 2006.190.08:01:32.64#ibcon#enter sib2, iclass 27, count 0 2006.190.08:01:32.64#ibcon#flushed, iclass 27, count 0 2006.190.08:01:32.64#ibcon#about to write, iclass 27, count 0 2006.190.08:01:32.64#ibcon#wrote, iclass 27, count 0 2006.190.08:01:32.64#ibcon#about to read 3, iclass 27, count 0 2006.190.08:01:32.67#ibcon#read 3, iclass 27, count 0 2006.190.08:01:32.67#ibcon#about to read 4, iclass 27, count 0 2006.190.08:01:32.67#ibcon#read 4, iclass 27, count 0 2006.190.08:01:32.67#ibcon#about to read 5, iclass 27, count 0 2006.190.08:01:32.67#ibcon#read 5, iclass 27, count 0 2006.190.08:01:32.67#ibcon#about to read 6, iclass 27, count 0 2006.190.08:01:32.67#ibcon#read 6, iclass 27, count 0 2006.190.08:01:32.67#ibcon#end of sib2, iclass 27, count 0 2006.190.08:01:32.67#ibcon#*after write, iclass 27, count 0 2006.190.08:01:32.67#ibcon#*before return 0, iclass 27, count 0 2006.190.08:01:32.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:32.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:01:32.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:01:32.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:01:32.67$vc4f8/vabw=wide 2006.190.08:01:32.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.08:01:32.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.08:01:32.67#ibcon#ireg 8 cls_cnt 0 2006.190.08:01:32.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:32.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:32.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:32.67#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:01:32.67#ibcon#first serial, iclass 29, count 0 2006.190.08:01:32.67#ibcon#enter sib2, iclass 29, count 0 2006.190.08:01:32.67#ibcon#flushed, iclass 29, count 0 2006.190.08:01:32.67#ibcon#about to write, iclass 29, count 0 2006.190.08:01:32.67#ibcon#wrote, iclass 29, count 0 2006.190.08:01:32.67#ibcon#about to read 3, iclass 29, count 0 2006.190.08:01:32.69#ibcon#read 3, iclass 29, count 0 2006.190.08:01:32.69#ibcon#about to read 4, iclass 29, count 0 2006.190.08:01:32.69#ibcon#read 4, iclass 29, count 0 2006.190.08:01:32.69#ibcon#about to read 5, iclass 29, count 0 2006.190.08:01:32.69#ibcon#read 5, iclass 29, count 0 2006.190.08:01:32.69#ibcon#about to read 6, iclass 29, count 0 2006.190.08:01:32.69#ibcon#read 6, iclass 29, count 0 2006.190.08:01:32.69#ibcon#end of sib2, iclass 29, count 0 2006.190.08:01:32.69#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:01:32.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:01:32.69#ibcon#[25=BW32\r\n] 2006.190.08:01:32.69#ibcon#*before write, iclass 29, count 0 2006.190.08:01:32.69#ibcon#enter sib2, iclass 29, count 0 2006.190.08:01:32.69#ibcon#flushed, iclass 29, count 0 2006.190.08:01:32.69#ibcon#about to write, iclass 29, count 0 2006.190.08:01:32.69#ibcon#wrote, iclass 29, count 0 2006.190.08:01:32.69#ibcon#about to read 3, iclass 29, count 0 2006.190.08:01:32.72#ibcon#read 3, iclass 29, count 0 2006.190.08:01:32.72#ibcon#about to read 4, iclass 29, count 0 2006.190.08:01:32.72#ibcon#read 4, iclass 29, count 0 2006.190.08:01:32.72#ibcon#about to read 5, iclass 29, count 0 2006.190.08:01:32.72#ibcon#read 5, iclass 29, count 0 2006.190.08:01:32.72#ibcon#about to read 6, iclass 29, count 0 2006.190.08:01:32.72#ibcon#read 6, iclass 29, count 0 2006.190.08:01:32.72#ibcon#end of sib2, iclass 29, count 0 2006.190.08:01:32.72#ibcon#*after write, iclass 29, count 0 2006.190.08:01:32.72#ibcon#*before return 0, iclass 29, count 0 2006.190.08:01:32.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:32.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:01:32.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:01:32.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:01:32.72$vc4f8/vbbw=wide 2006.190.08:01:32.72#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.08:01:32.72#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.08:01:32.72#ibcon#ireg 8 cls_cnt 0 2006.190.08:01:32.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:01:32.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:01:32.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:01:32.79#ibcon#enter wrdev, iclass 31, count 0 2006.190.08:01:32.79#ibcon#first serial, iclass 31, count 0 2006.190.08:01:32.79#ibcon#enter sib2, iclass 31, count 0 2006.190.08:01:32.79#ibcon#flushed, iclass 31, count 0 2006.190.08:01:32.79#ibcon#about to write, iclass 31, count 0 2006.190.08:01:32.79#ibcon#wrote, iclass 31, count 0 2006.190.08:01:32.79#ibcon#about to read 3, iclass 31, count 0 2006.190.08:01:32.81#ibcon#read 3, iclass 31, count 0 2006.190.08:01:32.81#ibcon#about to read 4, iclass 31, count 0 2006.190.08:01:32.81#ibcon#read 4, iclass 31, count 0 2006.190.08:01:32.81#ibcon#about to read 5, iclass 31, count 0 2006.190.08:01:32.81#ibcon#read 5, iclass 31, count 0 2006.190.08:01:32.81#ibcon#about to read 6, iclass 31, count 0 2006.190.08:01:32.81#ibcon#read 6, iclass 31, count 0 2006.190.08:01:32.81#ibcon#end of sib2, iclass 31, count 0 2006.190.08:01:32.81#ibcon#*mode == 0, iclass 31, count 0 2006.190.08:01:32.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.08:01:32.81#ibcon#[27=BW32\r\n] 2006.190.08:01:32.81#ibcon#*before write, iclass 31, count 0 2006.190.08:01:32.81#ibcon#enter sib2, iclass 31, count 0 2006.190.08:01:32.81#ibcon#flushed, iclass 31, count 0 2006.190.08:01:32.81#ibcon#about to write, iclass 31, count 0 2006.190.08:01:32.81#ibcon#wrote, iclass 31, count 0 2006.190.08:01:32.81#ibcon#about to read 3, iclass 31, count 0 2006.190.08:01:32.84#ibcon#read 3, iclass 31, count 0 2006.190.08:01:32.84#ibcon#about to read 4, iclass 31, count 0 2006.190.08:01:32.84#ibcon#read 4, iclass 31, count 0 2006.190.08:01:32.84#ibcon#about to read 5, iclass 31, count 0 2006.190.08:01:32.84#ibcon#read 5, iclass 31, count 0 2006.190.08:01:32.84#ibcon#about to read 6, iclass 31, count 0 2006.190.08:01:32.84#ibcon#read 6, iclass 31, count 0 2006.190.08:01:32.84#ibcon#end of sib2, iclass 31, count 0 2006.190.08:01:32.84#ibcon#*after write, iclass 31, count 0 2006.190.08:01:32.84#ibcon#*before return 0, iclass 31, count 0 2006.190.08:01:32.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:01:32.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:01:32.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.08:01:32.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.08:01:32.84$4f8m12a/ifd4f 2006.190.08:01:32.84$ifd4f/lo= 2006.190.08:01:32.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:01:32.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:01:32.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:01:32.84$ifd4f/patch= 2006.190.08:01:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:01:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:01:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:01:32.85$4f8m12a/"form=m,16.000,1:2 2006.190.08:01:32.85$4f8m12a/"tpicd 2006.190.08:01:32.85$4f8m12a/echo=off 2006.190.08:01:32.85$4f8m12a/xlog=off 2006.190.08:01:32.85:!2006.190.08:02:00 2006.190.08:01:42.14#trakl#Source acquired 2006.190.08:01:42.14#flagr#flagr/antenna,acquired 2006.190.08:02:00.01:preob 2006.190.08:02:01.14/onsource/TRACKING 2006.190.08:02:01.14:!2006.190.08:02:10 2006.190.08:02:10.00:data_valid=on 2006.190.08:02:10.00:midob 2006.190.08:02:10.14/onsource/TRACKING 2006.190.08:02:10.14/wx/24.51,1012.0,100 2006.190.08:02:10.31/cable/+6.4723E-03 2006.190.08:02:11.40/va/01,08,usb,yes,32,34 2006.190.08:02:11.40/va/02,07,usb,yes,32,34 2006.190.08:02:11.40/va/03,06,usb,yes,34,34 2006.190.08:02:11.40/va/04,07,usb,yes,33,36 2006.190.08:02:11.40/va/05,07,usb,yes,37,39 2006.190.08:02:11.40/va/06,06,usb,yes,36,35 2006.190.08:02:11.40/va/07,06,usb,yes,36,36 2006.190.08:02:11.40/va/08,06,usb,yes,39,38 2006.190.08:02:11.63/valo/01,532.99,yes,locked 2006.190.08:02:11.63/valo/02,572.99,yes,locked 2006.190.08:02:11.63/valo/03,672.99,yes,locked 2006.190.08:02:11.63/valo/04,832.99,yes,locked 2006.190.08:02:11.63/valo/05,652.99,yes,locked 2006.190.08:02:11.63/valo/06,772.99,yes,locked 2006.190.08:02:11.63/valo/07,832.99,yes,locked 2006.190.08:02:11.63/valo/08,852.99,yes,locked 2006.190.08:02:12.72/vb/01,04,usb,yes,29,27 2006.190.08:02:12.72/vb/02,04,usb,yes,31,32 2006.190.08:02:12.72/vb/03,04,usb,yes,27,31 2006.190.08:02:12.72/vb/04,04,usb,yes,28,28 2006.190.08:02:12.72/vb/05,04,usb,yes,26,30 2006.190.08:02:12.72/vb/06,04,usb,yes,27,30 2006.190.08:02:12.72/vb/07,04,usb,yes,29,29 2006.190.08:02:12.72/vb/08,04,usb,yes,27,30 2006.190.08:02:12.95/vblo/01,632.99,yes,locked 2006.190.08:02:12.95/vblo/02,640.99,yes,locked 2006.190.08:02:12.95/vblo/03,656.99,yes,locked 2006.190.08:02:12.95/vblo/04,712.99,yes,locked 2006.190.08:02:12.95/vblo/05,744.99,yes,locked 2006.190.08:02:12.95/vblo/06,752.99,yes,locked 2006.190.08:02:12.95/vblo/07,734.99,yes,locked 2006.190.08:02:12.95/vblo/08,744.99,yes,locked 2006.190.08:02:13.10/vabw/8 2006.190.08:02:13.25/vbbw/8 2006.190.08:02:13.37/xfe/off,on,14.7 2006.190.08:02:13.74/ifatt/23,28,28,28 2006.190.08:02:14.07/fmout-gps/S +2.85E-07 2006.190.08:02:14.16:!2006.190.08:03:10 2006.190.08:03:10.01:data_valid=off 2006.190.08:03:10.02:postob 2006.190.08:03:10.13/cable/+6.4717E-03 2006.190.08:03:10.14/wx/24.50,1012.0,100 2006.190.08:03:11.07/fmout-gps/S +2.85E-07 2006.190.08:03:11.08:scan_name=190-0804,k06190,60 2006.190.08:03:11.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.190.08:03:11.13#flagr#flagr/antenna,new-source 2006.190.08:03:12.13:checkk5 2006.190.08:03:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:03:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:03:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:03:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:03:14.03/chk_obsdata//k5ts1/T1900802??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:03:14.41/chk_obsdata//k5ts2/T1900802??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:03:14.79/chk_obsdata//k5ts3/T1900802??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:03:15.16/chk_obsdata//k5ts4/T1900802??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:03:15.86/k5log//k5ts1_log_newline 2006.190.08:03:16.56/k5log//k5ts2_log_newline 2006.190.08:03:17.26/k5log//k5ts3_log_newline 2006.190.08:03:17.95/k5log//k5ts4_log_newline 2006.190.08:03:17.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:03:17.97:4f8m12a=2 2006.190.08:03:17.97$4f8m12a/echo=on 2006.190.08:03:17.97$4f8m12a/pcalon 2006.190.08:03:17.97$pcalon/"no phase cal control is implemented here 2006.190.08:03:17.97$4f8m12a/"tpicd=stop 2006.190.08:03:17.97$4f8m12a/vc4f8 2006.190.08:03:17.97$vc4f8/valo=1,532.99 2006.190.08:03:17.98#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.08:03:17.98#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.08:03:17.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:17.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:17.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:17.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:17.98#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:03:17.98#ibcon#first serial, iclass 38, count 0 2006.190.08:03:17.98#ibcon#enter sib2, iclass 38, count 0 2006.190.08:03:17.98#ibcon#flushed, iclass 38, count 0 2006.190.08:03:17.98#ibcon#about to write, iclass 38, count 0 2006.190.08:03:17.98#ibcon#wrote, iclass 38, count 0 2006.190.08:03:17.98#ibcon#about to read 3, iclass 38, count 0 2006.190.08:03:18.06#ibcon#read 3, iclass 38, count 0 2006.190.08:03:18.06#ibcon#about to read 4, iclass 38, count 0 2006.190.08:03:18.06#ibcon#read 4, iclass 38, count 0 2006.190.08:03:18.06#ibcon#about to read 5, iclass 38, count 0 2006.190.08:03:18.06#ibcon#read 5, iclass 38, count 0 2006.190.08:03:18.06#ibcon#about to read 6, iclass 38, count 0 2006.190.08:03:18.06#ibcon#read 6, iclass 38, count 0 2006.190.08:03:18.06#ibcon#end of sib2, iclass 38, count 0 2006.190.08:03:18.06#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:03:18.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:03:18.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:03:18.06#ibcon#*before write, iclass 38, count 0 2006.190.08:03:18.06#ibcon#enter sib2, iclass 38, count 0 2006.190.08:03:18.06#ibcon#flushed, iclass 38, count 0 2006.190.08:03:18.06#ibcon#about to write, iclass 38, count 0 2006.190.08:03:18.06#ibcon#wrote, iclass 38, count 0 2006.190.08:03:18.06#ibcon#about to read 3, iclass 38, count 0 2006.190.08:03:18.11#ibcon#read 3, iclass 38, count 0 2006.190.08:03:18.11#ibcon#about to read 4, iclass 38, count 0 2006.190.08:03:18.11#ibcon#read 4, iclass 38, count 0 2006.190.08:03:18.11#ibcon#about to read 5, iclass 38, count 0 2006.190.08:03:18.11#ibcon#read 5, iclass 38, count 0 2006.190.08:03:18.11#ibcon#about to read 6, iclass 38, count 0 2006.190.08:03:18.11#ibcon#read 6, iclass 38, count 0 2006.190.08:03:18.11#ibcon#end of sib2, iclass 38, count 0 2006.190.08:03:18.11#ibcon#*after write, iclass 38, count 0 2006.190.08:03:18.11#ibcon#*before return 0, iclass 38, count 0 2006.190.08:03:18.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:18.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:18.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:03:18.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:03:18.11$vc4f8/va=1,8 2006.190.08:03:18.11#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.08:03:18.11#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.08:03:18.11#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:18.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:18.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:18.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:18.11#ibcon#enter wrdev, iclass 40, count 2 2006.190.08:03:18.11#ibcon#first serial, iclass 40, count 2 2006.190.08:03:18.11#ibcon#enter sib2, iclass 40, count 2 2006.190.08:03:18.11#ibcon#flushed, iclass 40, count 2 2006.190.08:03:18.11#ibcon#about to write, iclass 40, count 2 2006.190.08:03:18.11#ibcon#wrote, iclass 40, count 2 2006.190.08:03:18.11#ibcon#about to read 3, iclass 40, count 2 2006.190.08:03:18.12#ibcon#read 3, iclass 40, count 2 2006.190.08:03:18.12#ibcon#about to read 4, iclass 40, count 2 2006.190.08:03:18.12#ibcon#read 4, iclass 40, count 2 2006.190.08:03:18.12#ibcon#about to read 5, iclass 40, count 2 2006.190.08:03:18.12#ibcon#read 5, iclass 40, count 2 2006.190.08:03:18.12#ibcon#about to read 6, iclass 40, count 2 2006.190.08:03:18.12#ibcon#read 6, iclass 40, count 2 2006.190.08:03:18.12#ibcon#end of sib2, iclass 40, count 2 2006.190.08:03:18.12#ibcon#*mode == 0, iclass 40, count 2 2006.190.08:03:18.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.08:03:18.12#ibcon#[25=AT01-08\r\n] 2006.190.08:03:18.12#ibcon#*before write, iclass 40, count 2 2006.190.08:03:18.12#ibcon#enter sib2, iclass 40, count 2 2006.190.08:03:18.12#ibcon#flushed, iclass 40, count 2 2006.190.08:03:18.12#ibcon#about to write, iclass 40, count 2 2006.190.08:03:18.12#ibcon#wrote, iclass 40, count 2 2006.190.08:03:18.12#ibcon#about to read 3, iclass 40, count 2 2006.190.08:03:18.15#ibcon#read 3, iclass 40, count 2 2006.190.08:03:18.15#ibcon#about to read 4, iclass 40, count 2 2006.190.08:03:18.15#ibcon#read 4, iclass 40, count 2 2006.190.08:03:18.15#ibcon#about to read 5, iclass 40, count 2 2006.190.08:03:18.15#ibcon#read 5, iclass 40, count 2 2006.190.08:03:18.15#ibcon#about to read 6, iclass 40, count 2 2006.190.08:03:18.15#ibcon#read 6, iclass 40, count 2 2006.190.08:03:18.15#ibcon#end of sib2, iclass 40, count 2 2006.190.08:03:18.15#ibcon#*after write, iclass 40, count 2 2006.190.08:03:18.15#ibcon#*before return 0, iclass 40, count 2 2006.190.08:03:18.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:18.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:18.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.08:03:18.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:18.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:18.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:18.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:18.27#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:03:18.27#ibcon#first serial, iclass 40, count 0 2006.190.08:03:18.27#ibcon#enter sib2, iclass 40, count 0 2006.190.08:03:18.27#ibcon#flushed, iclass 40, count 0 2006.190.08:03:18.27#ibcon#about to write, iclass 40, count 0 2006.190.08:03:18.27#ibcon#wrote, iclass 40, count 0 2006.190.08:03:18.27#ibcon#about to read 3, iclass 40, count 0 2006.190.08:03:18.29#ibcon#read 3, iclass 40, count 0 2006.190.08:03:18.29#ibcon#about to read 4, iclass 40, count 0 2006.190.08:03:18.29#ibcon#read 4, iclass 40, count 0 2006.190.08:03:18.29#ibcon#about to read 5, iclass 40, count 0 2006.190.08:03:18.29#ibcon#read 5, iclass 40, count 0 2006.190.08:03:18.29#ibcon#about to read 6, iclass 40, count 0 2006.190.08:03:18.29#ibcon#read 6, iclass 40, count 0 2006.190.08:03:18.29#ibcon#end of sib2, iclass 40, count 0 2006.190.08:03:18.29#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:03:18.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:03:18.29#ibcon#[25=USB\r\n] 2006.190.08:03:18.29#ibcon#*before write, iclass 40, count 0 2006.190.08:03:18.29#ibcon#enter sib2, iclass 40, count 0 2006.190.08:03:18.29#ibcon#flushed, iclass 40, count 0 2006.190.08:03:18.29#ibcon#about to write, iclass 40, count 0 2006.190.08:03:18.29#ibcon#wrote, iclass 40, count 0 2006.190.08:03:18.29#ibcon#about to read 3, iclass 40, count 0 2006.190.08:03:18.32#ibcon#read 3, iclass 40, count 0 2006.190.08:03:18.32#ibcon#about to read 4, iclass 40, count 0 2006.190.08:03:18.32#ibcon#read 4, iclass 40, count 0 2006.190.08:03:18.32#ibcon#about to read 5, iclass 40, count 0 2006.190.08:03:18.32#ibcon#read 5, iclass 40, count 0 2006.190.08:03:18.32#ibcon#about to read 6, iclass 40, count 0 2006.190.08:03:18.32#ibcon#read 6, iclass 40, count 0 2006.190.08:03:18.32#ibcon#end of sib2, iclass 40, count 0 2006.190.08:03:18.32#ibcon#*after write, iclass 40, count 0 2006.190.08:03:18.32#ibcon#*before return 0, iclass 40, count 0 2006.190.08:03:18.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:18.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:18.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:03:18.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:03:18.32$vc4f8/valo=2,572.99 2006.190.08:03:18.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.08:03:18.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.08:03:18.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:18.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:18.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:18.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:18.32#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:03:18.32#ibcon#first serial, iclass 4, count 0 2006.190.08:03:18.32#ibcon#enter sib2, iclass 4, count 0 2006.190.08:03:18.32#ibcon#flushed, iclass 4, count 0 2006.190.08:03:18.32#ibcon#about to write, iclass 4, count 0 2006.190.08:03:18.32#ibcon#wrote, iclass 4, count 0 2006.190.08:03:18.32#ibcon#about to read 3, iclass 4, count 0 2006.190.08:03:18.34#ibcon#read 3, iclass 4, count 0 2006.190.08:03:18.34#ibcon#about to read 4, iclass 4, count 0 2006.190.08:03:18.34#ibcon#read 4, iclass 4, count 0 2006.190.08:03:18.34#ibcon#about to read 5, iclass 4, count 0 2006.190.08:03:18.34#ibcon#read 5, iclass 4, count 0 2006.190.08:03:18.34#ibcon#about to read 6, iclass 4, count 0 2006.190.08:03:18.34#ibcon#read 6, iclass 4, count 0 2006.190.08:03:18.34#ibcon#end of sib2, iclass 4, count 0 2006.190.08:03:18.34#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:03:18.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:03:18.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:03:18.34#ibcon#*before write, iclass 4, count 0 2006.190.08:03:18.34#ibcon#enter sib2, iclass 4, count 0 2006.190.08:03:18.34#ibcon#flushed, iclass 4, count 0 2006.190.08:03:18.34#ibcon#about to write, iclass 4, count 0 2006.190.08:03:18.34#ibcon#wrote, iclass 4, count 0 2006.190.08:03:18.34#ibcon#about to read 3, iclass 4, count 0 2006.190.08:03:18.39#ibcon#read 3, iclass 4, count 0 2006.190.08:03:18.39#ibcon#about to read 4, iclass 4, count 0 2006.190.08:03:18.39#ibcon#read 4, iclass 4, count 0 2006.190.08:03:18.39#ibcon#about to read 5, iclass 4, count 0 2006.190.08:03:18.39#ibcon#read 5, iclass 4, count 0 2006.190.08:03:18.39#ibcon#about to read 6, iclass 4, count 0 2006.190.08:03:18.39#ibcon#read 6, iclass 4, count 0 2006.190.08:03:18.39#ibcon#end of sib2, iclass 4, count 0 2006.190.08:03:18.39#ibcon#*after write, iclass 4, count 0 2006.190.08:03:18.39#ibcon#*before return 0, iclass 4, count 0 2006.190.08:03:18.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:18.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:18.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:03:18.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:03:18.39$vc4f8/va=2,7 2006.190.08:03:18.39#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.08:03:18.39#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.08:03:18.39#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:18.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:18.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:18.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:18.43#ibcon#enter wrdev, iclass 6, count 2 2006.190.08:03:18.43#ibcon#first serial, iclass 6, count 2 2006.190.08:03:18.43#ibcon#enter sib2, iclass 6, count 2 2006.190.08:03:18.43#ibcon#flushed, iclass 6, count 2 2006.190.08:03:18.43#ibcon#about to write, iclass 6, count 2 2006.190.08:03:18.43#ibcon#wrote, iclass 6, count 2 2006.190.08:03:18.43#ibcon#about to read 3, iclass 6, count 2 2006.190.08:03:18.45#ibcon#read 3, iclass 6, count 2 2006.190.08:03:18.45#ibcon#about to read 4, iclass 6, count 2 2006.190.08:03:18.45#ibcon#read 4, iclass 6, count 2 2006.190.08:03:18.45#ibcon#about to read 5, iclass 6, count 2 2006.190.08:03:18.45#ibcon#read 5, iclass 6, count 2 2006.190.08:03:18.45#ibcon#about to read 6, iclass 6, count 2 2006.190.08:03:18.45#ibcon#read 6, iclass 6, count 2 2006.190.08:03:18.45#ibcon#end of sib2, iclass 6, count 2 2006.190.08:03:18.45#ibcon#*mode == 0, iclass 6, count 2 2006.190.08:03:18.45#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.08:03:18.45#ibcon#[25=AT02-07\r\n] 2006.190.08:03:18.45#ibcon#*before write, iclass 6, count 2 2006.190.08:03:18.45#ibcon#enter sib2, iclass 6, count 2 2006.190.08:03:18.45#ibcon#flushed, iclass 6, count 2 2006.190.08:03:18.45#ibcon#about to write, iclass 6, count 2 2006.190.08:03:18.45#ibcon#wrote, iclass 6, count 2 2006.190.08:03:18.45#ibcon#about to read 3, iclass 6, count 2 2006.190.08:03:18.48#ibcon#read 3, iclass 6, count 2 2006.190.08:03:18.48#ibcon#about to read 4, iclass 6, count 2 2006.190.08:03:18.48#ibcon#read 4, iclass 6, count 2 2006.190.08:03:18.48#ibcon#about to read 5, iclass 6, count 2 2006.190.08:03:18.48#ibcon#read 5, iclass 6, count 2 2006.190.08:03:18.48#ibcon#about to read 6, iclass 6, count 2 2006.190.08:03:18.48#ibcon#read 6, iclass 6, count 2 2006.190.08:03:18.48#ibcon#end of sib2, iclass 6, count 2 2006.190.08:03:18.48#ibcon#*after write, iclass 6, count 2 2006.190.08:03:18.48#ibcon#*before return 0, iclass 6, count 2 2006.190.08:03:18.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:18.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:18.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.08:03:18.48#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:18.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:18.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:18.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:18.60#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:03:18.60#ibcon#first serial, iclass 6, count 0 2006.190.08:03:18.60#ibcon#enter sib2, iclass 6, count 0 2006.190.08:03:18.60#ibcon#flushed, iclass 6, count 0 2006.190.08:03:18.60#ibcon#about to write, iclass 6, count 0 2006.190.08:03:18.60#ibcon#wrote, iclass 6, count 0 2006.190.08:03:18.60#ibcon#about to read 3, iclass 6, count 0 2006.190.08:03:18.62#ibcon#read 3, iclass 6, count 0 2006.190.08:03:18.62#ibcon#about to read 4, iclass 6, count 0 2006.190.08:03:18.62#ibcon#read 4, iclass 6, count 0 2006.190.08:03:18.62#ibcon#about to read 5, iclass 6, count 0 2006.190.08:03:18.62#ibcon#read 5, iclass 6, count 0 2006.190.08:03:18.62#ibcon#about to read 6, iclass 6, count 0 2006.190.08:03:18.62#ibcon#read 6, iclass 6, count 0 2006.190.08:03:18.62#ibcon#end of sib2, iclass 6, count 0 2006.190.08:03:18.62#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:03:18.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:03:18.62#ibcon#[25=USB\r\n] 2006.190.08:03:18.62#ibcon#*before write, iclass 6, count 0 2006.190.08:03:18.62#ibcon#enter sib2, iclass 6, count 0 2006.190.08:03:18.62#ibcon#flushed, iclass 6, count 0 2006.190.08:03:18.62#ibcon#about to write, iclass 6, count 0 2006.190.08:03:18.62#ibcon#wrote, iclass 6, count 0 2006.190.08:03:18.62#ibcon#about to read 3, iclass 6, count 0 2006.190.08:03:18.65#ibcon#read 3, iclass 6, count 0 2006.190.08:03:18.65#ibcon#about to read 4, iclass 6, count 0 2006.190.08:03:18.65#ibcon#read 4, iclass 6, count 0 2006.190.08:03:18.65#ibcon#about to read 5, iclass 6, count 0 2006.190.08:03:18.65#ibcon#read 5, iclass 6, count 0 2006.190.08:03:18.65#ibcon#about to read 6, iclass 6, count 0 2006.190.08:03:18.65#ibcon#read 6, iclass 6, count 0 2006.190.08:03:18.65#ibcon#end of sib2, iclass 6, count 0 2006.190.08:03:18.65#ibcon#*after write, iclass 6, count 0 2006.190.08:03:18.65#ibcon#*before return 0, iclass 6, count 0 2006.190.08:03:18.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:18.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:18.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:03:18.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:03:18.65$vc4f8/valo=3,672.99 2006.190.08:03:18.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.08:03:18.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.08:03:18.65#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:18.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:18.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:18.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:18.65#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:03:18.65#ibcon#first serial, iclass 10, count 0 2006.190.08:03:18.65#ibcon#enter sib2, iclass 10, count 0 2006.190.08:03:18.65#ibcon#flushed, iclass 10, count 0 2006.190.08:03:18.65#ibcon#about to write, iclass 10, count 0 2006.190.08:03:18.65#ibcon#wrote, iclass 10, count 0 2006.190.08:03:18.65#ibcon#about to read 3, iclass 10, count 0 2006.190.08:03:18.67#ibcon#read 3, iclass 10, count 0 2006.190.08:03:18.67#ibcon#about to read 4, iclass 10, count 0 2006.190.08:03:18.67#ibcon#read 4, iclass 10, count 0 2006.190.08:03:18.67#ibcon#about to read 5, iclass 10, count 0 2006.190.08:03:18.67#ibcon#read 5, iclass 10, count 0 2006.190.08:03:18.67#ibcon#about to read 6, iclass 10, count 0 2006.190.08:03:18.67#ibcon#read 6, iclass 10, count 0 2006.190.08:03:18.67#ibcon#end of sib2, iclass 10, count 0 2006.190.08:03:18.67#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:03:18.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:03:18.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:03:18.67#ibcon#*before write, iclass 10, count 0 2006.190.08:03:18.67#ibcon#enter sib2, iclass 10, count 0 2006.190.08:03:18.67#ibcon#flushed, iclass 10, count 0 2006.190.08:03:18.67#ibcon#about to write, iclass 10, count 0 2006.190.08:03:18.67#ibcon#wrote, iclass 10, count 0 2006.190.08:03:18.67#ibcon#about to read 3, iclass 10, count 0 2006.190.08:03:18.72#ibcon#read 3, iclass 10, count 0 2006.190.08:03:18.72#ibcon#about to read 4, iclass 10, count 0 2006.190.08:03:18.72#ibcon#read 4, iclass 10, count 0 2006.190.08:03:18.72#ibcon#about to read 5, iclass 10, count 0 2006.190.08:03:18.72#ibcon#read 5, iclass 10, count 0 2006.190.08:03:18.72#ibcon#about to read 6, iclass 10, count 0 2006.190.08:03:18.72#ibcon#read 6, iclass 10, count 0 2006.190.08:03:18.72#ibcon#end of sib2, iclass 10, count 0 2006.190.08:03:18.72#ibcon#*after write, iclass 10, count 0 2006.190.08:03:18.72#ibcon#*before return 0, iclass 10, count 0 2006.190.08:03:18.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:18.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:18.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:03:18.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:03:18.72$vc4f8/va=3,6 2006.190.08:03:18.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.08:03:18.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.08:03:18.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:18.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:18.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:18.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:18.76#ibcon#enter wrdev, iclass 12, count 2 2006.190.08:03:18.76#ibcon#first serial, iclass 12, count 2 2006.190.08:03:18.76#ibcon#enter sib2, iclass 12, count 2 2006.190.08:03:18.76#ibcon#flushed, iclass 12, count 2 2006.190.08:03:18.76#ibcon#about to write, iclass 12, count 2 2006.190.08:03:18.76#ibcon#wrote, iclass 12, count 2 2006.190.08:03:18.76#ibcon#about to read 3, iclass 12, count 2 2006.190.08:03:18.78#ibcon#read 3, iclass 12, count 2 2006.190.08:03:18.78#ibcon#about to read 4, iclass 12, count 2 2006.190.08:03:18.78#ibcon#read 4, iclass 12, count 2 2006.190.08:03:18.78#ibcon#about to read 5, iclass 12, count 2 2006.190.08:03:18.78#ibcon#read 5, iclass 12, count 2 2006.190.08:03:18.78#ibcon#about to read 6, iclass 12, count 2 2006.190.08:03:18.78#ibcon#read 6, iclass 12, count 2 2006.190.08:03:18.78#ibcon#end of sib2, iclass 12, count 2 2006.190.08:03:18.78#ibcon#*mode == 0, iclass 12, count 2 2006.190.08:03:18.78#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.08:03:18.78#ibcon#[25=AT03-06\r\n] 2006.190.08:03:18.78#ibcon#*before write, iclass 12, count 2 2006.190.08:03:18.78#ibcon#enter sib2, iclass 12, count 2 2006.190.08:03:18.78#ibcon#flushed, iclass 12, count 2 2006.190.08:03:18.78#ibcon#about to write, iclass 12, count 2 2006.190.08:03:18.78#ibcon#wrote, iclass 12, count 2 2006.190.08:03:18.78#ibcon#about to read 3, iclass 12, count 2 2006.190.08:03:18.81#ibcon#read 3, iclass 12, count 2 2006.190.08:03:18.81#ibcon#about to read 4, iclass 12, count 2 2006.190.08:03:18.81#ibcon#read 4, iclass 12, count 2 2006.190.08:03:18.81#ibcon#about to read 5, iclass 12, count 2 2006.190.08:03:18.81#ibcon#read 5, iclass 12, count 2 2006.190.08:03:18.81#ibcon#about to read 6, iclass 12, count 2 2006.190.08:03:18.81#ibcon#read 6, iclass 12, count 2 2006.190.08:03:18.81#ibcon#end of sib2, iclass 12, count 2 2006.190.08:03:18.81#ibcon#*after write, iclass 12, count 2 2006.190.08:03:18.81#ibcon#*before return 0, iclass 12, count 2 2006.190.08:03:18.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:18.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:18.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.08:03:18.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:18.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:18.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:18.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:18.93#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:03:18.93#ibcon#first serial, iclass 12, count 0 2006.190.08:03:18.93#ibcon#enter sib2, iclass 12, count 0 2006.190.08:03:18.93#ibcon#flushed, iclass 12, count 0 2006.190.08:03:18.93#ibcon#about to write, iclass 12, count 0 2006.190.08:03:18.93#ibcon#wrote, iclass 12, count 0 2006.190.08:03:18.93#ibcon#about to read 3, iclass 12, count 0 2006.190.08:03:18.95#ibcon#read 3, iclass 12, count 0 2006.190.08:03:18.95#ibcon#about to read 4, iclass 12, count 0 2006.190.08:03:18.95#ibcon#read 4, iclass 12, count 0 2006.190.08:03:18.95#ibcon#about to read 5, iclass 12, count 0 2006.190.08:03:18.95#ibcon#read 5, iclass 12, count 0 2006.190.08:03:18.95#ibcon#about to read 6, iclass 12, count 0 2006.190.08:03:18.95#ibcon#read 6, iclass 12, count 0 2006.190.08:03:18.95#ibcon#end of sib2, iclass 12, count 0 2006.190.08:03:18.95#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:03:18.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:03:18.95#ibcon#[25=USB\r\n] 2006.190.08:03:18.95#ibcon#*before write, iclass 12, count 0 2006.190.08:03:18.95#ibcon#enter sib2, iclass 12, count 0 2006.190.08:03:18.95#ibcon#flushed, iclass 12, count 0 2006.190.08:03:18.95#ibcon#about to write, iclass 12, count 0 2006.190.08:03:18.95#ibcon#wrote, iclass 12, count 0 2006.190.08:03:18.95#ibcon#about to read 3, iclass 12, count 0 2006.190.08:03:18.98#ibcon#read 3, iclass 12, count 0 2006.190.08:03:18.98#ibcon#about to read 4, iclass 12, count 0 2006.190.08:03:18.98#ibcon#read 4, iclass 12, count 0 2006.190.08:03:18.98#ibcon#about to read 5, iclass 12, count 0 2006.190.08:03:18.98#ibcon#read 5, iclass 12, count 0 2006.190.08:03:18.98#ibcon#about to read 6, iclass 12, count 0 2006.190.08:03:18.98#ibcon#read 6, iclass 12, count 0 2006.190.08:03:18.98#ibcon#end of sib2, iclass 12, count 0 2006.190.08:03:18.98#ibcon#*after write, iclass 12, count 0 2006.190.08:03:18.98#ibcon#*before return 0, iclass 12, count 0 2006.190.08:03:18.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:18.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:18.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:03:18.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:03:18.98$vc4f8/valo=4,832.99 2006.190.08:03:18.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.08:03:18.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.08:03:18.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:18.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:18.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:18.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:18.98#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:03:18.98#ibcon#first serial, iclass 14, count 0 2006.190.08:03:18.98#ibcon#enter sib2, iclass 14, count 0 2006.190.08:03:18.98#ibcon#flushed, iclass 14, count 0 2006.190.08:03:18.98#ibcon#about to write, iclass 14, count 0 2006.190.08:03:18.98#ibcon#wrote, iclass 14, count 0 2006.190.08:03:18.98#ibcon#about to read 3, iclass 14, count 0 2006.190.08:03:19.00#ibcon#read 3, iclass 14, count 0 2006.190.08:03:19.00#ibcon#about to read 4, iclass 14, count 0 2006.190.08:03:19.00#ibcon#read 4, iclass 14, count 0 2006.190.08:03:19.00#ibcon#about to read 5, iclass 14, count 0 2006.190.08:03:19.00#ibcon#read 5, iclass 14, count 0 2006.190.08:03:19.00#ibcon#about to read 6, iclass 14, count 0 2006.190.08:03:19.00#ibcon#read 6, iclass 14, count 0 2006.190.08:03:19.00#ibcon#end of sib2, iclass 14, count 0 2006.190.08:03:19.00#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:03:19.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:03:19.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:03:19.00#ibcon#*before write, iclass 14, count 0 2006.190.08:03:19.00#ibcon#enter sib2, iclass 14, count 0 2006.190.08:03:19.00#ibcon#flushed, iclass 14, count 0 2006.190.08:03:19.00#ibcon#about to write, iclass 14, count 0 2006.190.08:03:19.00#ibcon#wrote, iclass 14, count 0 2006.190.08:03:19.00#ibcon#about to read 3, iclass 14, count 0 2006.190.08:03:19.04#ibcon#read 3, iclass 14, count 0 2006.190.08:03:19.04#ibcon#about to read 4, iclass 14, count 0 2006.190.08:03:19.04#ibcon#read 4, iclass 14, count 0 2006.190.08:03:19.04#ibcon#about to read 5, iclass 14, count 0 2006.190.08:03:19.04#ibcon#read 5, iclass 14, count 0 2006.190.08:03:19.04#ibcon#about to read 6, iclass 14, count 0 2006.190.08:03:19.04#ibcon#read 6, iclass 14, count 0 2006.190.08:03:19.04#ibcon#end of sib2, iclass 14, count 0 2006.190.08:03:19.04#ibcon#*after write, iclass 14, count 0 2006.190.08:03:19.04#ibcon#*before return 0, iclass 14, count 0 2006.190.08:03:19.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:19.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:19.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:03:19.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:03:19.04$vc4f8/va=4,7 2006.190.08:03:19.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.08:03:19.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.08:03:19.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:19.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:19.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:19.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:19.10#ibcon#enter wrdev, iclass 16, count 2 2006.190.08:03:19.10#ibcon#first serial, iclass 16, count 2 2006.190.08:03:19.10#ibcon#enter sib2, iclass 16, count 2 2006.190.08:03:19.10#ibcon#flushed, iclass 16, count 2 2006.190.08:03:19.10#ibcon#about to write, iclass 16, count 2 2006.190.08:03:19.10#ibcon#wrote, iclass 16, count 2 2006.190.08:03:19.10#ibcon#about to read 3, iclass 16, count 2 2006.190.08:03:19.12#ibcon#read 3, iclass 16, count 2 2006.190.08:03:19.12#ibcon#about to read 4, iclass 16, count 2 2006.190.08:03:19.12#ibcon#read 4, iclass 16, count 2 2006.190.08:03:19.12#ibcon#about to read 5, iclass 16, count 2 2006.190.08:03:19.12#ibcon#read 5, iclass 16, count 2 2006.190.08:03:19.12#ibcon#about to read 6, iclass 16, count 2 2006.190.08:03:19.12#ibcon#read 6, iclass 16, count 2 2006.190.08:03:19.12#ibcon#end of sib2, iclass 16, count 2 2006.190.08:03:19.12#ibcon#*mode == 0, iclass 16, count 2 2006.190.08:03:19.12#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.08:03:19.12#ibcon#[25=AT04-07\r\n] 2006.190.08:03:19.12#ibcon#*before write, iclass 16, count 2 2006.190.08:03:19.12#ibcon#enter sib2, iclass 16, count 2 2006.190.08:03:19.12#ibcon#flushed, iclass 16, count 2 2006.190.08:03:19.12#ibcon#about to write, iclass 16, count 2 2006.190.08:03:19.12#ibcon#wrote, iclass 16, count 2 2006.190.08:03:19.12#ibcon#about to read 3, iclass 16, count 2 2006.190.08:03:19.15#ibcon#read 3, iclass 16, count 2 2006.190.08:03:19.15#ibcon#about to read 4, iclass 16, count 2 2006.190.08:03:19.15#ibcon#read 4, iclass 16, count 2 2006.190.08:03:19.15#ibcon#about to read 5, iclass 16, count 2 2006.190.08:03:19.15#ibcon#read 5, iclass 16, count 2 2006.190.08:03:19.15#ibcon#about to read 6, iclass 16, count 2 2006.190.08:03:19.15#ibcon#read 6, iclass 16, count 2 2006.190.08:03:19.15#ibcon#end of sib2, iclass 16, count 2 2006.190.08:03:19.15#ibcon#*after write, iclass 16, count 2 2006.190.08:03:19.15#ibcon#*before return 0, iclass 16, count 2 2006.190.08:03:19.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:19.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:19.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.08:03:19.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:19.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:19.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:19.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:19.27#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:03:19.27#ibcon#first serial, iclass 16, count 0 2006.190.08:03:19.27#ibcon#enter sib2, iclass 16, count 0 2006.190.08:03:19.27#ibcon#flushed, iclass 16, count 0 2006.190.08:03:19.27#ibcon#about to write, iclass 16, count 0 2006.190.08:03:19.27#ibcon#wrote, iclass 16, count 0 2006.190.08:03:19.27#ibcon#about to read 3, iclass 16, count 0 2006.190.08:03:19.29#ibcon#read 3, iclass 16, count 0 2006.190.08:03:19.29#ibcon#about to read 4, iclass 16, count 0 2006.190.08:03:19.29#ibcon#read 4, iclass 16, count 0 2006.190.08:03:19.29#ibcon#about to read 5, iclass 16, count 0 2006.190.08:03:19.29#ibcon#read 5, iclass 16, count 0 2006.190.08:03:19.29#ibcon#about to read 6, iclass 16, count 0 2006.190.08:03:19.29#ibcon#read 6, iclass 16, count 0 2006.190.08:03:19.29#ibcon#end of sib2, iclass 16, count 0 2006.190.08:03:19.29#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:03:19.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:03:19.29#ibcon#[25=USB\r\n] 2006.190.08:03:19.29#ibcon#*before write, iclass 16, count 0 2006.190.08:03:19.29#ibcon#enter sib2, iclass 16, count 0 2006.190.08:03:19.29#ibcon#flushed, iclass 16, count 0 2006.190.08:03:19.29#ibcon#about to write, iclass 16, count 0 2006.190.08:03:19.29#ibcon#wrote, iclass 16, count 0 2006.190.08:03:19.29#ibcon#about to read 3, iclass 16, count 0 2006.190.08:03:19.32#ibcon#read 3, iclass 16, count 0 2006.190.08:03:19.32#ibcon#about to read 4, iclass 16, count 0 2006.190.08:03:19.32#ibcon#read 4, iclass 16, count 0 2006.190.08:03:19.32#ibcon#about to read 5, iclass 16, count 0 2006.190.08:03:19.32#ibcon#read 5, iclass 16, count 0 2006.190.08:03:19.32#ibcon#about to read 6, iclass 16, count 0 2006.190.08:03:19.32#ibcon#read 6, iclass 16, count 0 2006.190.08:03:19.32#ibcon#end of sib2, iclass 16, count 0 2006.190.08:03:19.32#ibcon#*after write, iclass 16, count 0 2006.190.08:03:19.32#ibcon#*before return 0, iclass 16, count 0 2006.190.08:03:19.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:19.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:19.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:03:19.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:03:19.32$vc4f8/valo=5,652.99 2006.190.08:03:19.32#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.08:03:19.32#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.08:03:19.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:19.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:03:19.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:03:19.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:03:19.32#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:03:19.32#ibcon#first serial, iclass 18, count 0 2006.190.08:03:19.32#ibcon#enter sib2, iclass 18, count 0 2006.190.08:03:19.32#ibcon#flushed, iclass 18, count 0 2006.190.08:03:19.32#ibcon#about to write, iclass 18, count 0 2006.190.08:03:19.32#ibcon#wrote, iclass 18, count 0 2006.190.08:03:19.32#ibcon#about to read 3, iclass 18, count 0 2006.190.08:03:19.34#ibcon#read 3, iclass 18, count 0 2006.190.08:03:19.34#ibcon#about to read 4, iclass 18, count 0 2006.190.08:03:19.34#ibcon#read 4, iclass 18, count 0 2006.190.08:03:19.34#ibcon#about to read 5, iclass 18, count 0 2006.190.08:03:19.34#ibcon#read 5, iclass 18, count 0 2006.190.08:03:19.34#ibcon#about to read 6, iclass 18, count 0 2006.190.08:03:19.34#ibcon#read 6, iclass 18, count 0 2006.190.08:03:19.34#ibcon#end of sib2, iclass 18, count 0 2006.190.08:03:19.34#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:03:19.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:03:19.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:03:19.34#ibcon#*before write, iclass 18, count 0 2006.190.08:03:19.34#ibcon#enter sib2, iclass 18, count 0 2006.190.08:03:19.34#ibcon#flushed, iclass 18, count 0 2006.190.08:03:19.34#ibcon#about to write, iclass 18, count 0 2006.190.08:03:19.34#ibcon#wrote, iclass 18, count 0 2006.190.08:03:19.34#ibcon#about to read 3, iclass 18, count 0 2006.190.08:03:19.38#ibcon#read 3, iclass 18, count 0 2006.190.08:03:19.38#ibcon#about to read 4, iclass 18, count 0 2006.190.08:03:19.38#ibcon#read 4, iclass 18, count 0 2006.190.08:03:19.38#ibcon#about to read 5, iclass 18, count 0 2006.190.08:03:19.38#ibcon#read 5, iclass 18, count 0 2006.190.08:03:19.38#ibcon#about to read 6, iclass 18, count 0 2006.190.08:03:19.38#ibcon#read 6, iclass 18, count 0 2006.190.08:03:19.38#ibcon#end of sib2, iclass 18, count 0 2006.190.08:03:19.38#ibcon#*after write, iclass 18, count 0 2006.190.08:03:19.38#ibcon#*before return 0, iclass 18, count 0 2006.190.08:03:19.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:03:19.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:03:19.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:03:19.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:03:19.38$vc4f8/va=5,7 2006.190.08:03:19.38#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.190.08:03:19.38#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.190.08:03:19.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:19.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:03:19.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:03:19.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:03:19.44#ibcon#enter wrdev, iclass 20, count 2 2006.190.08:03:19.44#ibcon#first serial, iclass 20, count 2 2006.190.08:03:19.44#ibcon#enter sib2, iclass 20, count 2 2006.190.08:03:19.44#ibcon#flushed, iclass 20, count 2 2006.190.08:03:19.44#ibcon#about to write, iclass 20, count 2 2006.190.08:03:19.44#ibcon#wrote, iclass 20, count 2 2006.190.08:03:19.44#ibcon#about to read 3, iclass 20, count 2 2006.190.08:03:19.46#ibcon#read 3, iclass 20, count 2 2006.190.08:03:19.46#ibcon#about to read 4, iclass 20, count 2 2006.190.08:03:19.46#ibcon#read 4, iclass 20, count 2 2006.190.08:03:19.46#ibcon#about to read 5, iclass 20, count 2 2006.190.08:03:19.46#ibcon#read 5, iclass 20, count 2 2006.190.08:03:19.46#ibcon#about to read 6, iclass 20, count 2 2006.190.08:03:19.46#ibcon#read 6, iclass 20, count 2 2006.190.08:03:19.46#ibcon#end of sib2, iclass 20, count 2 2006.190.08:03:19.46#ibcon#*mode == 0, iclass 20, count 2 2006.190.08:03:19.46#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.190.08:03:19.46#ibcon#[25=AT05-07\r\n] 2006.190.08:03:19.46#ibcon#*before write, iclass 20, count 2 2006.190.08:03:19.46#ibcon#enter sib2, iclass 20, count 2 2006.190.08:03:19.46#ibcon#flushed, iclass 20, count 2 2006.190.08:03:19.46#ibcon#about to write, iclass 20, count 2 2006.190.08:03:19.46#ibcon#wrote, iclass 20, count 2 2006.190.08:03:19.46#ibcon#about to read 3, iclass 20, count 2 2006.190.08:03:19.49#ibcon#read 3, iclass 20, count 2 2006.190.08:03:19.49#ibcon#about to read 4, iclass 20, count 2 2006.190.08:03:19.49#ibcon#read 4, iclass 20, count 2 2006.190.08:03:19.49#ibcon#about to read 5, iclass 20, count 2 2006.190.08:03:19.49#ibcon#read 5, iclass 20, count 2 2006.190.08:03:19.49#ibcon#about to read 6, iclass 20, count 2 2006.190.08:03:19.49#ibcon#read 6, iclass 20, count 2 2006.190.08:03:19.49#ibcon#end of sib2, iclass 20, count 2 2006.190.08:03:19.49#ibcon#*after write, iclass 20, count 2 2006.190.08:03:19.49#ibcon#*before return 0, iclass 20, count 2 2006.190.08:03:19.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:03:19.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:03:19.49#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.190.08:03:19.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:19.49#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:03:19.61#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:03:19.61#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:03:19.61#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:03:19.61#ibcon#first serial, iclass 20, count 0 2006.190.08:03:19.61#ibcon#enter sib2, iclass 20, count 0 2006.190.08:03:19.61#ibcon#flushed, iclass 20, count 0 2006.190.08:03:19.61#ibcon#about to write, iclass 20, count 0 2006.190.08:03:19.61#ibcon#wrote, iclass 20, count 0 2006.190.08:03:19.61#ibcon#about to read 3, iclass 20, count 0 2006.190.08:03:19.63#ibcon#read 3, iclass 20, count 0 2006.190.08:03:19.63#ibcon#about to read 4, iclass 20, count 0 2006.190.08:03:19.63#ibcon#read 4, iclass 20, count 0 2006.190.08:03:19.63#ibcon#about to read 5, iclass 20, count 0 2006.190.08:03:19.63#ibcon#read 5, iclass 20, count 0 2006.190.08:03:19.63#ibcon#about to read 6, iclass 20, count 0 2006.190.08:03:19.63#ibcon#read 6, iclass 20, count 0 2006.190.08:03:19.63#ibcon#end of sib2, iclass 20, count 0 2006.190.08:03:19.63#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:03:19.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:03:19.63#ibcon#[25=USB\r\n] 2006.190.08:03:19.63#ibcon#*before write, iclass 20, count 0 2006.190.08:03:19.63#ibcon#enter sib2, iclass 20, count 0 2006.190.08:03:19.63#ibcon#flushed, iclass 20, count 0 2006.190.08:03:19.63#ibcon#about to write, iclass 20, count 0 2006.190.08:03:19.63#ibcon#wrote, iclass 20, count 0 2006.190.08:03:19.63#ibcon#about to read 3, iclass 20, count 0 2006.190.08:03:19.66#ibcon#read 3, iclass 20, count 0 2006.190.08:03:19.66#ibcon#about to read 4, iclass 20, count 0 2006.190.08:03:19.66#ibcon#read 4, iclass 20, count 0 2006.190.08:03:19.66#ibcon#about to read 5, iclass 20, count 0 2006.190.08:03:19.66#ibcon#read 5, iclass 20, count 0 2006.190.08:03:19.66#ibcon#about to read 6, iclass 20, count 0 2006.190.08:03:19.66#ibcon#read 6, iclass 20, count 0 2006.190.08:03:19.66#ibcon#end of sib2, iclass 20, count 0 2006.190.08:03:19.66#ibcon#*after write, iclass 20, count 0 2006.190.08:03:19.66#ibcon#*before return 0, iclass 20, count 0 2006.190.08:03:19.66#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:03:19.66#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:03:19.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:03:19.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:03:19.66$vc4f8/valo=6,772.99 2006.190.08:03:19.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.08:03:19.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.08:03:19.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:19.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:03:19.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:03:19.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:03:19.66#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:03:19.66#ibcon#first serial, iclass 22, count 0 2006.190.08:03:19.66#ibcon#enter sib2, iclass 22, count 0 2006.190.08:03:19.66#ibcon#flushed, iclass 22, count 0 2006.190.08:03:19.66#ibcon#about to write, iclass 22, count 0 2006.190.08:03:19.66#ibcon#wrote, iclass 22, count 0 2006.190.08:03:19.66#ibcon#about to read 3, iclass 22, count 0 2006.190.08:03:19.68#ibcon#read 3, iclass 22, count 0 2006.190.08:03:19.68#ibcon#about to read 4, iclass 22, count 0 2006.190.08:03:19.68#ibcon#read 4, iclass 22, count 0 2006.190.08:03:19.68#ibcon#about to read 5, iclass 22, count 0 2006.190.08:03:19.68#ibcon#read 5, iclass 22, count 0 2006.190.08:03:19.68#ibcon#about to read 6, iclass 22, count 0 2006.190.08:03:19.68#ibcon#read 6, iclass 22, count 0 2006.190.08:03:19.68#ibcon#end of sib2, iclass 22, count 0 2006.190.08:03:19.68#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:03:19.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:03:19.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:03:19.68#ibcon#*before write, iclass 22, count 0 2006.190.08:03:19.68#ibcon#enter sib2, iclass 22, count 0 2006.190.08:03:19.68#ibcon#flushed, iclass 22, count 0 2006.190.08:03:19.68#ibcon#about to write, iclass 22, count 0 2006.190.08:03:19.68#ibcon#wrote, iclass 22, count 0 2006.190.08:03:19.68#ibcon#about to read 3, iclass 22, count 0 2006.190.08:03:19.72#ibcon#read 3, iclass 22, count 0 2006.190.08:03:19.72#ibcon#about to read 4, iclass 22, count 0 2006.190.08:03:19.72#ibcon#read 4, iclass 22, count 0 2006.190.08:03:19.72#ibcon#about to read 5, iclass 22, count 0 2006.190.08:03:19.72#ibcon#read 5, iclass 22, count 0 2006.190.08:03:19.72#ibcon#about to read 6, iclass 22, count 0 2006.190.08:03:19.72#ibcon#read 6, iclass 22, count 0 2006.190.08:03:19.72#ibcon#end of sib2, iclass 22, count 0 2006.190.08:03:19.72#ibcon#*after write, iclass 22, count 0 2006.190.08:03:19.72#ibcon#*before return 0, iclass 22, count 0 2006.190.08:03:19.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:03:19.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:03:19.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:03:19.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:03:19.72$vc4f8/va=6,6 2006.190.08:03:19.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.08:03:19.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.08:03:19.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:19.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:19.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:19.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:19.78#ibcon#enter wrdev, iclass 24, count 2 2006.190.08:03:19.78#ibcon#first serial, iclass 24, count 2 2006.190.08:03:19.78#ibcon#enter sib2, iclass 24, count 2 2006.190.08:03:19.78#ibcon#flushed, iclass 24, count 2 2006.190.08:03:19.78#ibcon#about to write, iclass 24, count 2 2006.190.08:03:19.78#ibcon#wrote, iclass 24, count 2 2006.190.08:03:19.78#ibcon#about to read 3, iclass 24, count 2 2006.190.08:03:19.80#ibcon#read 3, iclass 24, count 2 2006.190.08:03:19.80#ibcon#about to read 4, iclass 24, count 2 2006.190.08:03:19.80#ibcon#read 4, iclass 24, count 2 2006.190.08:03:19.80#ibcon#about to read 5, iclass 24, count 2 2006.190.08:03:19.80#ibcon#read 5, iclass 24, count 2 2006.190.08:03:19.80#ibcon#about to read 6, iclass 24, count 2 2006.190.08:03:19.80#ibcon#read 6, iclass 24, count 2 2006.190.08:03:19.80#ibcon#end of sib2, iclass 24, count 2 2006.190.08:03:19.80#ibcon#*mode == 0, iclass 24, count 2 2006.190.08:03:19.80#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.08:03:19.80#ibcon#[25=AT06-06\r\n] 2006.190.08:03:19.80#ibcon#*before write, iclass 24, count 2 2006.190.08:03:19.80#ibcon#enter sib2, iclass 24, count 2 2006.190.08:03:19.80#ibcon#flushed, iclass 24, count 2 2006.190.08:03:19.80#ibcon#about to write, iclass 24, count 2 2006.190.08:03:19.80#ibcon#wrote, iclass 24, count 2 2006.190.08:03:19.80#ibcon#about to read 3, iclass 24, count 2 2006.190.08:03:19.83#ibcon#read 3, iclass 24, count 2 2006.190.08:03:19.83#ibcon#about to read 4, iclass 24, count 2 2006.190.08:03:19.83#ibcon#read 4, iclass 24, count 2 2006.190.08:03:19.83#ibcon#about to read 5, iclass 24, count 2 2006.190.08:03:19.83#ibcon#read 5, iclass 24, count 2 2006.190.08:03:19.83#ibcon#about to read 6, iclass 24, count 2 2006.190.08:03:19.83#ibcon#read 6, iclass 24, count 2 2006.190.08:03:19.83#ibcon#end of sib2, iclass 24, count 2 2006.190.08:03:19.83#ibcon#*after write, iclass 24, count 2 2006.190.08:03:19.83#ibcon#*before return 0, iclass 24, count 2 2006.190.08:03:19.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:19.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:19.83#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.08:03:19.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:19.83#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:19.95#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:19.95#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:19.95#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:03:19.95#ibcon#first serial, iclass 24, count 0 2006.190.08:03:19.95#ibcon#enter sib2, iclass 24, count 0 2006.190.08:03:19.95#ibcon#flushed, iclass 24, count 0 2006.190.08:03:19.95#ibcon#about to write, iclass 24, count 0 2006.190.08:03:19.95#ibcon#wrote, iclass 24, count 0 2006.190.08:03:19.95#ibcon#about to read 3, iclass 24, count 0 2006.190.08:03:19.97#ibcon#read 3, iclass 24, count 0 2006.190.08:03:19.97#ibcon#about to read 4, iclass 24, count 0 2006.190.08:03:19.97#ibcon#read 4, iclass 24, count 0 2006.190.08:03:19.97#ibcon#about to read 5, iclass 24, count 0 2006.190.08:03:19.97#ibcon#read 5, iclass 24, count 0 2006.190.08:03:19.97#ibcon#about to read 6, iclass 24, count 0 2006.190.08:03:19.97#ibcon#read 6, iclass 24, count 0 2006.190.08:03:19.97#ibcon#end of sib2, iclass 24, count 0 2006.190.08:03:19.97#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:03:19.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:03:19.97#ibcon#[25=USB\r\n] 2006.190.08:03:19.97#ibcon#*before write, iclass 24, count 0 2006.190.08:03:19.97#ibcon#enter sib2, iclass 24, count 0 2006.190.08:03:19.97#ibcon#flushed, iclass 24, count 0 2006.190.08:03:19.97#ibcon#about to write, iclass 24, count 0 2006.190.08:03:19.97#ibcon#wrote, iclass 24, count 0 2006.190.08:03:19.97#ibcon#about to read 3, iclass 24, count 0 2006.190.08:03:20.00#ibcon#read 3, iclass 24, count 0 2006.190.08:03:20.00#ibcon#about to read 4, iclass 24, count 0 2006.190.08:03:20.00#ibcon#read 4, iclass 24, count 0 2006.190.08:03:20.00#ibcon#about to read 5, iclass 24, count 0 2006.190.08:03:20.00#ibcon#read 5, iclass 24, count 0 2006.190.08:03:20.00#ibcon#about to read 6, iclass 24, count 0 2006.190.08:03:20.00#ibcon#read 6, iclass 24, count 0 2006.190.08:03:20.00#ibcon#end of sib2, iclass 24, count 0 2006.190.08:03:20.00#ibcon#*after write, iclass 24, count 0 2006.190.08:03:20.00#ibcon#*before return 0, iclass 24, count 0 2006.190.08:03:20.00#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:20.00#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:20.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:03:20.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:03:20.00$vc4f8/valo=7,832.99 2006.190.08:03:20.00#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.08:03:20.00#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.08:03:20.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:20.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:20.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:20.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:20.00#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:03:20.00#ibcon#first serial, iclass 26, count 0 2006.190.08:03:20.00#ibcon#enter sib2, iclass 26, count 0 2006.190.08:03:20.00#ibcon#flushed, iclass 26, count 0 2006.190.08:03:20.00#ibcon#about to write, iclass 26, count 0 2006.190.08:03:20.00#ibcon#wrote, iclass 26, count 0 2006.190.08:03:20.00#ibcon#about to read 3, iclass 26, count 0 2006.190.08:03:20.02#ibcon#read 3, iclass 26, count 0 2006.190.08:03:20.02#ibcon#about to read 4, iclass 26, count 0 2006.190.08:03:20.02#ibcon#read 4, iclass 26, count 0 2006.190.08:03:20.02#ibcon#about to read 5, iclass 26, count 0 2006.190.08:03:20.02#ibcon#read 5, iclass 26, count 0 2006.190.08:03:20.02#ibcon#about to read 6, iclass 26, count 0 2006.190.08:03:20.02#ibcon#read 6, iclass 26, count 0 2006.190.08:03:20.02#ibcon#end of sib2, iclass 26, count 0 2006.190.08:03:20.02#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:03:20.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:03:20.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:03:20.02#ibcon#*before write, iclass 26, count 0 2006.190.08:03:20.02#ibcon#enter sib2, iclass 26, count 0 2006.190.08:03:20.02#ibcon#flushed, iclass 26, count 0 2006.190.08:03:20.02#ibcon#about to write, iclass 26, count 0 2006.190.08:03:20.02#ibcon#wrote, iclass 26, count 0 2006.190.08:03:20.02#ibcon#about to read 3, iclass 26, count 0 2006.190.08:03:20.06#ibcon#read 3, iclass 26, count 0 2006.190.08:03:20.06#ibcon#about to read 4, iclass 26, count 0 2006.190.08:03:20.06#ibcon#read 4, iclass 26, count 0 2006.190.08:03:20.06#ibcon#about to read 5, iclass 26, count 0 2006.190.08:03:20.06#ibcon#read 5, iclass 26, count 0 2006.190.08:03:20.06#ibcon#about to read 6, iclass 26, count 0 2006.190.08:03:20.06#ibcon#read 6, iclass 26, count 0 2006.190.08:03:20.06#ibcon#end of sib2, iclass 26, count 0 2006.190.08:03:20.06#ibcon#*after write, iclass 26, count 0 2006.190.08:03:20.06#ibcon#*before return 0, iclass 26, count 0 2006.190.08:03:20.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:20.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:20.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:03:20.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:03:20.06$vc4f8/va=7,6 2006.190.08:03:20.06#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.08:03:20.06#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.08:03:20.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:20.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:03:20.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:03:20.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:03:20.12#ibcon#enter wrdev, iclass 28, count 2 2006.190.08:03:20.12#ibcon#first serial, iclass 28, count 2 2006.190.08:03:20.12#ibcon#enter sib2, iclass 28, count 2 2006.190.08:03:20.12#ibcon#flushed, iclass 28, count 2 2006.190.08:03:20.12#ibcon#about to write, iclass 28, count 2 2006.190.08:03:20.12#ibcon#wrote, iclass 28, count 2 2006.190.08:03:20.12#ibcon#about to read 3, iclass 28, count 2 2006.190.08:03:20.14#ibcon#read 3, iclass 28, count 2 2006.190.08:03:20.14#ibcon#about to read 4, iclass 28, count 2 2006.190.08:03:20.14#ibcon#read 4, iclass 28, count 2 2006.190.08:03:20.14#ibcon#about to read 5, iclass 28, count 2 2006.190.08:03:20.14#ibcon#read 5, iclass 28, count 2 2006.190.08:03:20.14#ibcon#about to read 6, iclass 28, count 2 2006.190.08:03:20.14#ibcon#read 6, iclass 28, count 2 2006.190.08:03:20.14#ibcon#end of sib2, iclass 28, count 2 2006.190.08:03:20.14#ibcon#*mode == 0, iclass 28, count 2 2006.190.08:03:20.14#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.08:03:20.14#ibcon#[25=AT07-06\r\n] 2006.190.08:03:20.14#ibcon#*before write, iclass 28, count 2 2006.190.08:03:20.14#ibcon#enter sib2, iclass 28, count 2 2006.190.08:03:20.14#ibcon#flushed, iclass 28, count 2 2006.190.08:03:20.14#ibcon#about to write, iclass 28, count 2 2006.190.08:03:20.14#ibcon#wrote, iclass 28, count 2 2006.190.08:03:20.14#ibcon#about to read 3, iclass 28, count 2 2006.190.08:03:20.17#ibcon#read 3, iclass 28, count 2 2006.190.08:03:20.17#ibcon#about to read 4, iclass 28, count 2 2006.190.08:03:20.17#ibcon#read 4, iclass 28, count 2 2006.190.08:03:20.17#ibcon#about to read 5, iclass 28, count 2 2006.190.08:03:20.17#ibcon#read 5, iclass 28, count 2 2006.190.08:03:20.17#ibcon#about to read 6, iclass 28, count 2 2006.190.08:03:20.17#ibcon#read 6, iclass 28, count 2 2006.190.08:03:20.17#ibcon#end of sib2, iclass 28, count 2 2006.190.08:03:20.17#ibcon#*after write, iclass 28, count 2 2006.190.08:03:20.17#ibcon#*before return 0, iclass 28, count 2 2006.190.08:03:20.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:03:20.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:03:20.17#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.08:03:20.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:20.17#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:03:20.29#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:03:20.29#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:03:20.29#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:03:20.29#ibcon#first serial, iclass 28, count 0 2006.190.08:03:20.29#ibcon#enter sib2, iclass 28, count 0 2006.190.08:03:20.29#ibcon#flushed, iclass 28, count 0 2006.190.08:03:20.29#ibcon#about to write, iclass 28, count 0 2006.190.08:03:20.29#ibcon#wrote, iclass 28, count 0 2006.190.08:03:20.29#ibcon#about to read 3, iclass 28, count 0 2006.190.08:03:20.31#ibcon#read 3, iclass 28, count 0 2006.190.08:03:20.31#ibcon#about to read 4, iclass 28, count 0 2006.190.08:03:20.31#ibcon#read 4, iclass 28, count 0 2006.190.08:03:20.31#ibcon#about to read 5, iclass 28, count 0 2006.190.08:03:20.31#ibcon#read 5, iclass 28, count 0 2006.190.08:03:20.31#ibcon#about to read 6, iclass 28, count 0 2006.190.08:03:20.31#ibcon#read 6, iclass 28, count 0 2006.190.08:03:20.31#ibcon#end of sib2, iclass 28, count 0 2006.190.08:03:20.31#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:03:20.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:03:20.31#ibcon#[25=USB\r\n] 2006.190.08:03:20.31#ibcon#*before write, iclass 28, count 0 2006.190.08:03:20.31#ibcon#enter sib2, iclass 28, count 0 2006.190.08:03:20.31#ibcon#flushed, iclass 28, count 0 2006.190.08:03:20.31#ibcon#about to write, iclass 28, count 0 2006.190.08:03:20.31#ibcon#wrote, iclass 28, count 0 2006.190.08:03:20.31#ibcon#about to read 3, iclass 28, count 0 2006.190.08:03:20.34#ibcon#read 3, iclass 28, count 0 2006.190.08:03:20.34#ibcon#about to read 4, iclass 28, count 0 2006.190.08:03:20.34#ibcon#read 4, iclass 28, count 0 2006.190.08:03:20.34#ibcon#about to read 5, iclass 28, count 0 2006.190.08:03:20.34#ibcon#read 5, iclass 28, count 0 2006.190.08:03:20.34#ibcon#about to read 6, iclass 28, count 0 2006.190.08:03:20.34#ibcon#read 6, iclass 28, count 0 2006.190.08:03:20.34#ibcon#end of sib2, iclass 28, count 0 2006.190.08:03:20.34#ibcon#*after write, iclass 28, count 0 2006.190.08:03:20.34#ibcon#*before return 0, iclass 28, count 0 2006.190.08:03:20.34#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:03:20.34#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:03:20.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:03:20.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:03:20.34$vc4f8/valo=8,852.99 2006.190.08:03:20.34#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.08:03:20.34#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.08:03:20.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:20.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:03:20.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:03:20.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:03:20.34#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:03:20.34#ibcon#first serial, iclass 30, count 0 2006.190.08:03:20.34#ibcon#enter sib2, iclass 30, count 0 2006.190.08:03:20.34#ibcon#flushed, iclass 30, count 0 2006.190.08:03:20.34#ibcon#about to write, iclass 30, count 0 2006.190.08:03:20.34#ibcon#wrote, iclass 30, count 0 2006.190.08:03:20.34#ibcon#about to read 3, iclass 30, count 0 2006.190.08:03:20.36#ibcon#read 3, iclass 30, count 0 2006.190.08:03:20.36#ibcon#about to read 4, iclass 30, count 0 2006.190.08:03:20.36#ibcon#read 4, iclass 30, count 0 2006.190.08:03:20.36#ibcon#about to read 5, iclass 30, count 0 2006.190.08:03:20.36#ibcon#read 5, iclass 30, count 0 2006.190.08:03:20.36#ibcon#about to read 6, iclass 30, count 0 2006.190.08:03:20.36#ibcon#read 6, iclass 30, count 0 2006.190.08:03:20.36#ibcon#end of sib2, iclass 30, count 0 2006.190.08:03:20.36#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:03:20.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:03:20.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:03:20.36#ibcon#*before write, iclass 30, count 0 2006.190.08:03:20.36#ibcon#enter sib2, iclass 30, count 0 2006.190.08:03:20.36#ibcon#flushed, iclass 30, count 0 2006.190.08:03:20.36#ibcon#about to write, iclass 30, count 0 2006.190.08:03:20.36#ibcon#wrote, iclass 30, count 0 2006.190.08:03:20.36#ibcon#about to read 3, iclass 30, count 0 2006.190.08:03:20.40#ibcon#read 3, iclass 30, count 0 2006.190.08:03:20.40#ibcon#about to read 4, iclass 30, count 0 2006.190.08:03:20.40#ibcon#read 4, iclass 30, count 0 2006.190.08:03:20.40#ibcon#about to read 5, iclass 30, count 0 2006.190.08:03:20.40#ibcon#read 5, iclass 30, count 0 2006.190.08:03:20.40#ibcon#about to read 6, iclass 30, count 0 2006.190.08:03:20.40#ibcon#read 6, iclass 30, count 0 2006.190.08:03:20.40#ibcon#end of sib2, iclass 30, count 0 2006.190.08:03:20.40#ibcon#*after write, iclass 30, count 0 2006.190.08:03:20.40#ibcon#*before return 0, iclass 30, count 0 2006.190.08:03:20.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:03:20.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:03:20.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:03:20.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:03:20.40$vc4f8/va=8,6 2006.190.08:03:20.40#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.08:03:20.40#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.08:03:20.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:20.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:03:20.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:03:20.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:03:20.46#ibcon#enter wrdev, iclass 32, count 2 2006.190.08:03:20.46#ibcon#first serial, iclass 32, count 2 2006.190.08:03:20.46#ibcon#enter sib2, iclass 32, count 2 2006.190.08:03:20.46#ibcon#flushed, iclass 32, count 2 2006.190.08:03:20.46#ibcon#about to write, iclass 32, count 2 2006.190.08:03:20.46#ibcon#wrote, iclass 32, count 2 2006.190.08:03:20.46#ibcon#about to read 3, iclass 32, count 2 2006.190.08:03:20.48#ibcon#read 3, iclass 32, count 2 2006.190.08:03:20.48#ibcon#about to read 4, iclass 32, count 2 2006.190.08:03:20.48#ibcon#read 4, iclass 32, count 2 2006.190.08:03:20.48#ibcon#about to read 5, iclass 32, count 2 2006.190.08:03:20.48#ibcon#read 5, iclass 32, count 2 2006.190.08:03:20.48#ibcon#about to read 6, iclass 32, count 2 2006.190.08:03:20.48#ibcon#read 6, iclass 32, count 2 2006.190.08:03:20.48#ibcon#end of sib2, iclass 32, count 2 2006.190.08:03:20.48#ibcon#*mode == 0, iclass 32, count 2 2006.190.08:03:20.48#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.08:03:20.48#ibcon#[25=AT08-06\r\n] 2006.190.08:03:20.48#ibcon#*before write, iclass 32, count 2 2006.190.08:03:20.48#ibcon#enter sib2, iclass 32, count 2 2006.190.08:03:20.48#ibcon#flushed, iclass 32, count 2 2006.190.08:03:20.48#ibcon#about to write, iclass 32, count 2 2006.190.08:03:20.48#ibcon#wrote, iclass 32, count 2 2006.190.08:03:20.48#ibcon#about to read 3, iclass 32, count 2 2006.190.08:03:20.51#ibcon#read 3, iclass 32, count 2 2006.190.08:03:20.51#ibcon#about to read 4, iclass 32, count 2 2006.190.08:03:20.51#ibcon#read 4, iclass 32, count 2 2006.190.08:03:20.51#ibcon#about to read 5, iclass 32, count 2 2006.190.08:03:20.51#ibcon#read 5, iclass 32, count 2 2006.190.08:03:20.51#ibcon#about to read 6, iclass 32, count 2 2006.190.08:03:20.51#ibcon#read 6, iclass 32, count 2 2006.190.08:03:20.51#ibcon#end of sib2, iclass 32, count 2 2006.190.08:03:20.51#ibcon#*after write, iclass 32, count 2 2006.190.08:03:20.51#ibcon#*before return 0, iclass 32, count 2 2006.190.08:03:20.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:03:20.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:03:20.51#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.08:03:20.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:20.51#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:03:20.63#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:03:20.63#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:03:20.63#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:03:20.63#ibcon#first serial, iclass 32, count 0 2006.190.08:03:20.63#ibcon#enter sib2, iclass 32, count 0 2006.190.08:03:20.63#ibcon#flushed, iclass 32, count 0 2006.190.08:03:20.63#ibcon#about to write, iclass 32, count 0 2006.190.08:03:20.63#ibcon#wrote, iclass 32, count 0 2006.190.08:03:20.63#ibcon#about to read 3, iclass 32, count 0 2006.190.08:03:20.65#ibcon#read 3, iclass 32, count 0 2006.190.08:03:20.65#ibcon#about to read 4, iclass 32, count 0 2006.190.08:03:20.65#ibcon#read 4, iclass 32, count 0 2006.190.08:03:20.65#ibcon#about to read 5, iclass 32, count 0 2006.190.08:03:20.65#ibcon#read 5, iclass 32, count 0 2006.190.08:03:20.65#ibcon#about to read 6, iclass 32, count 0 2006.190.08:03:20.65#ibcon#read 6, iclass 32, count 0 2006.190.08:03:20.65#ibcon#end of sib2, iclass 32, count 0 2006.190.08:03:20.65#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:03:20.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:03:20.65#ibcon#[25=USB\r\n] 2006.190.08:03:20.65#ibcon#*before write, iclass 32, count 0 2006.190.08:03:20.65#ibcon#enter sib2, iclass 32, count 0 2006.190.08:03:20.65#ibcon#flushed, iclass 32, count 0 2006.190.08:03:20.65#ibcon#about to write, iclass 32, count 0 2006.190.08:03:20.65#ibcon#wrote, iclass 32, count 0 2006.190.08:03:20.65#ibcon#about to read 3, iclass 32, count 0 2006.190.08:03:20.68#ibcon#read 3, iclass 32, count 0 2006.190.08:03:20.68#ibcon#about to read 4, iclass 32, count 0 2006.190.08:03:20.68#ibcon#read 4, iclass 32, count 0 2006.190.08:03:20.68#ibcon#about to read 5, iclass 32, count 0 2006.190.08:03:20.68#ibcon#read 5, iclass 32, count 0 2006.190.08:03:20.68#ibcon#about to read 6, iclass 32, count 0 2006.190.08:03:20.68#ibcon#read 6, iclass 32, count 0 2006.190.08:03:20.68#ibcon#end of sib2, iclass 32, count 0 2006.190.08:03:20.68#ibcon#*after write, iclass 32, count 0 2006.190.08:03:20.68#ibcon#*before return 0, iclass 32, count 0 2006.190.08:03:20.68#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:03:20.68#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:03:20.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:03:20.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:03:20.68$vc4f8/vblo=1,632.99 2006.190.08:03:20.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.08:03:20.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.08:03:20.68#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:20.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:03:20.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:03:20.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:03:20.68#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:03:20.68#ibcon#first serial, iclass 34, count 0 2006.190.08:03:20.68#ibcon#enter sib2, iclass 34, count 0 2006.190.08:03:20.68#ibcon#flushed, iclass 34, count 0 2006.190.08:03:20.68#ibcon#about to write, iclass 34, count 0 2006.190.08:03:20.68#ibcon#wrote, iclass 34, count 0 2006.190.08:03:20.68#ibcon#about to read 3, iclass 34, count 0 2006.190.08:03:20.70#ibcon#read 3, iclass 34, count 0 2006.190.08:03:20.70#ibcon#about to read 4, iclass 34, count 0 2006.190.08:03:20.70#ibcon#read 4, iclass 34, count 0 2006.190.08:03:20.70#ibcon#about to read 5, iclass 34, count 0 2006.190.08:03:20.70#ibcon#read 5, iclass 34, count 0 2006.190.08:03:20.70#ibcon#about to read 6, iclass 34, count 0 2006.190.08:03:20.70#ibcon#read 6, iclass 34, count 0 2006.190.08:03:20.70#ibcon#end of sib2, iclass 34, count 0 2006.190.08:03:20.70#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:03:20.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:03:20.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:03:20.70#ibcon#*before write, iclass 34, count 0 2006.190.08:03:20.70#ibcon#enter sib2, iclass 34, count 0 2006.190.08:03:20.70#ibcon#flushed, iclass 34, count 0 2006.190.08:03:20.70#ibcon#about to write, iclass 34, count 0 2006.190.08:03:20.70#ibcon#wrote, iclass 34, count 0 2006.190.08:03:20.70#ibcon#about to read 3, iclass 34, count 0 2006.190.08:03:20.74#ibcon#read 3, iclass 34, count 0 2006.190.08:03:20.74#ibcon#about to read 4, iclass 34, count 0 2006.190.08:03:20.74#ibcon#read 4, iclass 34, count 0 2006.190.08:03:20.74#ibcon#about to read 5, iclass 34, count 0 2006.190.08:03:20.74#ibcon#read 5, iclass 34, count 0 2006.190.08:03:20.74#ibcon#about to read 6, iclass 34, count 0 2006.190.08:03:20.74#ibcon#read 6, iclass 34, count 0 2006.190.08:03:20.74#ibcon#end of sib2, iclass 34, count 0 2006.190.08:03:20.74#ibcon#*after write, iclass 34, count 0 2006.190.08:03:20.74#ibcon#*before return 0, iclass 34, count 0 2006.190.08:03:20.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:03:20.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:03:20.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:03:20.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:03:20.74$vc4f8/vb=1,4 2006.190.08:03:20.74#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.08:03:20.74#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.08:03:20.74#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:20.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:03:20.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:03:20.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:03:20.74#ibcon#enter wrdev, iclass 36, count 2 2006.190.08:03:20.74#ibcon#first serial, iclass 36, count 2 2006.190.08:03:20.74#ibcon#enter sib2, iclass 36, count 2 2006.190.08:03:20.74#ibcon#flushed, iclass 36, count 2 2006.190.08:03:20.74#ibcon#about to write, iclass 36, count 2 2006.190.08:03:20.74#ibcon#wrote, iclass 36, count 2 2006.190.08:03:20.74#ibcon#about to read 3, iclass 36, count 2 2006.190.08:03:20.76#ibcon#read 3, iclass 36, count 2 2006.190.08:03:20.76#ibcon#about to read 4, iclass 36, count 2 2006.190.08:03:20.76#ibcon#read 4, iclass 36, count 2 2006.190.08:03:20.76#ibcon#about to read 5, iclass 36, count 2 2006.190.08:03:20.76#ibcon#read 5, iclass 36, count 2 2006.190.08:03:20.76#ibcon#about to read 6, iclass 36, count 2 2006.190.08:03:20.76#ibcon#read 6, iclass 36, count 2 2006.190.08:03:20.76#ibcon#end of sib2, iclass 36, count 2 2006.190.08:03:20.76#ibcon#*mode == 0, iclass 36, count 2 2006.190.08:03:20.76#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.08:03:20.76#ibcon#[27=AT01-04\r\n] 2006.190.08:03:20.76#ibcon#*before write, iclass 36, count 2 2006.190.08:03:20.76#ibcon#enter sib2, iclass 36, count 2 2006.190.08:03:20.76#ibcon#flushed, iclass 36, count 2 2006.190.08:03:20.76#ibcon#about to write, iclass 36, count 2 2006.190.08:03:20.76#ibcon#wrote, iclass 36, count 2 2006.190.08:03:20.76#ibcon#about to read 3, iclass 36, count 2 2006.190.08:03:20.79#ibcon#read 3, iclass 36, count 2 2006.190.08:03:20.79#ibcon#about to read 4, iclass 36, count 2 2006.190.08:03:20.79#ibcon#read 4, iclass 36, count 2 2006.190.08:03:20.79#ibcon#about to read 5, iclass 36, count 2 2006.190.08:03:20.79#ibcon#read 5, iclass 36, count 2 2006.190.08:03:20.79#ibcon#about to read 6, iclass 36, count 2 2006.190.08:03:20.79#ibcon#read 6, iclass 36, count 2 2006.190.08:03:20.79#ibcon#end of sib2, iclass 36, count 2 2006.190.08:03:20.79#ibcon#*after write, iclass 36, count 2 2006.190.08:03:20.79#ibcon#*before return 0, iclass 36, count 2 2006.190.08:03:20.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:03:20.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:03:20.79#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.08:03:20.79#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:20.79#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:03:20.91#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:03:20.91#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:03:20.91#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:03:20.91#ibcon#first serial, iclass 36, count 0 2006.190.08:03:20.91#ibcon#enter sib2, iclass 36, count 0 2006.190.08:03:20.91#ibcon#flushed, iclass 36, count 0 2006.190.08:03:20.91#ibcon#about to write, iclass 36, count 0 2006.190.08:03:20.91#ibcon#wrote, iclass 36, count 0 2006.190.08:03:20.91#ibcon#about to read 3, iclass 36, count 0 2006.190.08:03:20.93#ibcon#read 3, iclass 36, count 0 2006.190.08:03:20.93#ibcon#about to read 4, iclass 36, count 0 2006.190.08:03:20.93#ibcon#read 4, iclass 36, count 0 2006.190.08:03:20.93#ibcon#about to read 5, iclass 36, count 0 2006.190.08:03:20.93#ibcon#read 5, iclass 36, count 0 2006.190.08:03:20.93#ibcon#about to read 6, iclass 36, count 0 2006.190.08:03:20.93#ibcon#read 6, iclass 36, count 0 2006.190.08:03:20.93#ibcon#end of sib2, iclass 36, count 0 2006.190.08:03:20.93#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:03:20.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:03:20.93#ibcon#[27=USB\r\n] 2006.190.08:03:20.93#ibcon#*before write, iclass 36, count 0 2006.190.08:03:20.93#ibcon#enter sib2, iclass 36, count 0 2006.190.08:03:20.93#ibcon#flushed, iclass 36, count 0 2006.190.08:03:20.93#ibcon#about to write, iclass 36, count 0 2006.190.08:03:20.93#ibcon#wrote, iclass 36, count 0 2006.190.08:03:20.93#ibcon#about to read 3, iclass 36, count 0 2006.190.08:03:20.96#ibcon#read 3, iclass 36, count 0 2006.190.08:03:20.96#ibcon#about to read 4, iclass 36, count 0 2006.190.08:03:20.96#ibcon#read 4, iclass 36, count 0 2006.190.08:03:20.96#ibcon#about to read 5, iclass 36, count 0 2006.190.08:03:20.96#ibcon#read 5, iclass 36, count 0 2006.190.08:03:20.96#ibcon#about to read 6, iclass 36, count 0 2006.190.08:03:20.96#ibcon#read 6, iclass 36, count 0 2006.190.08:03:20.96#ibcon#end of sib2, iclass 36, count 0 2006.190.08:03:20.96#ibcon#*after write, iclass 36, count 0 2006.190.08:03:20.96#ibcon#*before return 0, iclass 36, count 0 2006.190.08:03:20.96#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:03:20.96#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:03:20.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:03:20.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:03:20.96$vc4f8/vblo=2,640.99 2006.190.08:03:20.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.08:03:20.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.08:03:20.96#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:20.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:20.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:20.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:20.96#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:03:20.96#ibcon#first serial, iclass 38, count 0 2006.190.08:03:20.96#ibcon#enter sib2, iclass 38, count 0 2006.190.08:03:20.96#ibcon#flushed, iclass 38, count 0 2006.190.08:03:20.96#ibcon#about to write, iclass 38, count 0 2006.190.08:03:20.96#ibcon#wrote, iclass 38, count 0 2006.190.08:03:20.96#ibcon#about to read 3, iclass 38, count 0 2006.190.08:03:20.98#ibcon#read 3, iclass 38, count 0 2006.190.08:03:20.98#ibcon#about to read 4, iclass 38, count 0 2006.190.08:03:20.98#ibcon#read 4, iclass 38, count 0 2006.190.08:03:20.98#ibcon#about to read 5, iclass 38, count 0 2006.190.08:03:20.98#ibcon#read 5, iclass 38, count 0 2006.190.08:03:20.98#ibcon#about to read 6, iclass 38, count 0 2006.190.08:03:20.98#ibcon#read 6, iclass 38, count 0 2006.190.08:03:20.98#ibcon#end of sib2, iclass 38, count 0 2006.190.08:03:20.98#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:03:20.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:03:20.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:03:20.98#ibcon#*before write, iclass 38, count 0 2006.190.08:03:20.98#ibcon#enter sib2, iclass 38, count 0 2006.190.08:03:20.98#ibcon#flushed, iclass 38, count 0 2006.190.08:03:20.98#ibcon#about to write, iclass 38, count 0 2006.190.08:03:20.98#ibcon#wrote, iclass 38, count 0 2006.190.08:03:20.98#ibcon#about to read 3, iclass 38, count 0 2006.190.08:03:21.02#ibcon#read 3, iclass 38, count 0 2006.190.08:03:21.02#ibcon#about to read 4, iclass 38, count 0 2006.190.08:03:21.02#ibcon#read 4, iclass 38, count 0 2006.190.08:03:21.02#ibcon#about to read 5, iclass 38, count 0 2006.190.08:03:21.02#ibcon#read 5, iclass 38, count 0 2006.190.08:03:21.02#ibcon#about to read 6, iclass 38, count 0 2006.190.08:03:21.02#ibcon#read 6, iclass 38, count 0 2006.190.08:03:21.02#ibcon#end of sib2, iclass 38, count 0 2006.190.08:03:21.02#ibcon#*after write, iclass 38, count 0 2006.190.08:03:21.02#ibcon#*before return 0, iclass 38, count 0 2006.190.08:03:21.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:21.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:03:21.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:03:21.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:03:21.02$vc4f8/vb=2,4 2006.190.08:03:21.02#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.08:03:21.02#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.08:03:21.02#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:21.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:21.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:21.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:21.08#ibcon#enter wrdev, iclass 40, count 2 2006.190.08:03:21.08#ibcon#first serial, iclass 40, count 2 2006.190.08:03:21.08#ibcon#enter sib2, iclass 40, count 2 2006.190.08:03:21.08#ibcon#flushed, iclass 40, count 2 2006.190.08:03:21.08#ibcon#about to write, iclass 40, count 2 2006.190.08:03:21.08#ibcon#wrote, iclass 40, count 2 2006.190.08:03:21.08#ibcon#about to read 3, iclass 40, count 2 2006.190.08:03:21.10#ibcon#read 3, iclass 40, count 2 2006.190.08:03:21.10#ibcon#about to read 4, iclass 40, count 2 2006.190.08:03:21.10#ibcon#read 4, iclass 40, count 2 2006.190.08:03:21.10#ibcon#about to read 5, iclass 40, count 2 2006.190.08:03:21.10#ibcon#read 5, iclass 40, count 2 2006.190.08:03:21.10#ibcon#about to read 6, iclass 40, count 2 2006.190.08:03:21.10#ibcon#read 6, iclass 40, count 2 2006.190.08:03:21.10#ibcon#end of sib2, iclass 40, count 2 2006.190.08:03:21.10#ibcon#*mode == 0, iclass 40, count 2 2006.190.08:03:21.10#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.08:03:21.10#ibcon#[27=AT02-04\r\n] 2006.190.08:03:21.10#ibcon#*before write, iclass 40, count 2 2006.190.08:03:21.10#ibcon#enter sib2, iclass 40, count 2 2006.190.08:03:21.10#ibcon#flushed, iclass 40, count 2 2006.190.08:03:21.10#ibcon#about to write, iclass 40, count 2 2006.190.08:03:21.10#ibcon#wrote, iclass 40, count 2 2006.190.08:03:21.10#ibcon#about to read 3, iclass 40, count 2 2006.190.08:03:21.13#ibcon#read 3, iclass 40, count 2 2006.190.08:03:21.13#ibcon#about to read 4, iclass 40, count 2 2006.190.08:03:21.13#ibcon#read 4, iclass 40, count 2 2006.190.08:03:21.13#ibcon#about to read 5, iclass 40, count 2 2006.190.08:03:21.13#ibcon#read 5, iclass 40, count 2 2006.190.08:03:21.13#ibcon#about to read 6, iclass 40, count 2 2006.190.08:03:21.13#ibcon#read 6, iclass 40, count 2 2006.190.08:03:21.13#ibcon#end of sib2, iclass 40, count 2 2006.190.08:03:21.13#ibcon#*after write, iclass 40, count 2 2006.190.08:03:21.13#ibcon#*before return 0, iclass 40, count 2 2006.190.08:03:21.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:21.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:03:21.13#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.08:03:21.13#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:21.13#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:21.25#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:21.25#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:21.25#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:03:21.25#ibcon#first serial, iclass 40, count 0 2006.190.08:03:21.25#ibcon#enter sib2, iclass 40, count 0 2006.190.08:03:21.25#ibcon#flushed, iclass 40, count 0 2006.190.08:03:21.25#ibcon#about to write, iclass 40, count 0 2006.190.08:03:21.25#ibcon#wrote, iclass 40, count 0 2006.190.08:03:21.25#ibcon#about to read 3, iclass 40, count 0 2006.190.08:03:21.27#ibcon#read 3, iclass 40, count 0 2006.190.08:03:21.27#ibcon#about to read 4, iclass 40, count 0 2006.190.08:03:21.27#ibcon#read 4, iclass 40, count 0 2006.190.08:03:21.27#ibcon#about to read 5, iclass 40, count 0 2006.190.08:03:21.27#ibcon#read 5, iclass 40, count 0 2006.190.08:03:21.27#ibcon#about to read 6, iclass 40, count 0 2006.190.08:03:21.27#ibcon#read 6, iclass 40, count 0 2006.190.08:03:21.27#ibcon#end of sib2, iclass 40, count 0 2006.190.08:03:21.27#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:03:21.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:03:21.27#ibcon#[27=USB\r\n] 2006.190.08:03:21.27#ibcon#*before write, iclass 40, count 0 2006.190.08:03:21.27#ibcon#enter sib2, iclass 40, count 0 2006.190.08:03:21.27#ibcon#flushed, iclass 40, count 0 2006.190.08:03:21.27#ibcon#about to write, iclass 40, count 0 2006.190.08:03:21.27#ibcon#wrote, iclass 40, count 0 2006.190.08:03:21.27#ibcon#about to read 3, iclass 40, count 0 2006.190.08:03:21.30#ibcon#read 3, iclass 40, count 0 2006.190.08:03:21.30#ibcon#about to read 4, iclass 40, count 0 2006.190.08:03:21.30#ibcon#read 4, iclass 40, count 0 2006.190.08:03:21.30#ibcon#about to read 5, iclass 40, count 0 2006.190.08:03:21.30#ibcon#read 5, iclass 40, count 0 2006.190.08:03:21.30#ibcon#about to read 6, iclass 40, count 0 2006.190.08:03:21.30#ibcon#read 6, iclass 40, count 0 2006.190.08:03:21.30#ibcon#end of sib2, iclass 40, count 0 2006.190.08:03:21.30#ibcon#*after write, iclass 40, count 0 2006.190.08:03:21.30#ibcon#*before return 0, iclass 40, count 0 2006.190.08:03:21.30#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:21.30#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:03:21.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:03:21.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:03:21.30$vc4f8/vblo=3,656.99 2006.190.08:03:21.30#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.08:03:21.30#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.08:03:21.30#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:21.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:21.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:21.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:21.30#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:03:21.30#ibcon#first serial, iclass 4, count 0 2006.190.08:03:21.30#ibcon#enter sib2, iclass 4, count 0 2006.190.08:03:21.30#ibcon#flushed, iclass 4, count 0 2006.190.08:03:21.30#ibcon#about to write, iclass 4, count 0 2006.190.08:03:21.30#ibcon#wrote, iclass 4, count 0 2006.190.08:03:21.30#ibcon#about to read 3, iclass 4, count 0 2006.190.08:03:21.32#ibcon#read 3, iclass 4, count 0 2006.190.08:03:21.32#ibcon#about to read 4, iclass 4, count 0 2006.190.08:03:21.32#ibcon#read 4, iclass 4, count 0 2006.190.08:03:21.32#ibcon#about to read 5, iclass 4, count 0 2006.190.08:03:21.32#ibcon#read 5, iclass 4, count 0 2006.190.08:03:21.32#ibcon#about to read 6, iclass 4, count 0 2006.190.08:03:21.32#ibcon#read 6, iclass 4, count 0 2006.190.08:03:21.32#ibcon#end of sib2, iclass 4, count 0 2006.190.08:03:21.32#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:03:21.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:03:21.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:03:21.32#ibcon#*before write, iclass 4, count 0 2006.190.08:03:21.32#ibcon#enter sib2, iclass 4, count 0 2006.190.08:03:21.32#ibcon#flushed, iclass 4, count 0 2006.190.08:03:21.32#ibcon#about to write, iclass 4, count 0 2006.190.08:03:21.32#ibcon#wrote, iclass 4, count 0 2006.190.08:03:21.32#ibcon#about to read 3, iclass 4, count 0 2006.190.08:03:21.36#ibcon#read 3, iclass 4, count 0 2006.190.08:03:21.36#ibcon#about to read 4, iclass 4, count 0 2006.190.08:03:21.36#ibcon#read 4, iclass 4, count 0 2006.190.08:03:21.36#ibcon#about to read 5, iclass 4, count 0 2006.190.08:03:21.36#ibcon#read 5, iclass 4, count 0 2006.190.08:03:21.36#ibcon#about to read 6, iclass 4, count 0 2006.190.08:03:21.36#ibcon#read 6, iclass 4, count 0 2006.190.08:03:21.36#ibcon#end of sib2, iclass 4, count 0 2006.190.08:03:21.36#ibcon#*after write, iclass 4, count 0 2006.190.08:03:21.36#ibcon#*before return 0, iclass 4, count 0 2006.190.08:03:21.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:21.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:03:21.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:03:21.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:03:21.36$vc4f8/vb=3,4 2006.190.08:03:21.36#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.08:03:21.36#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.08:03:21.36#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:21.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:21.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:21.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:21.42#ibcon#enter wrdev, iclass 6, count 2 2006.190.08:03:21.42#ibcon#first serial, iclass 6, count 2 2006.190.08:03:21.42#ibcon#enter sib2, iclass 6, count 2 2006.190.08:03:21.42#ibcon#flushed, iclass 6, count 2 2006.190.08:03:21.42#ibcon#about to write, iclass 6, count 2 2006.190.08:03:21.42#ibcon#wrote, iclass 6, count 2 2006.190.08:03:21.42#ibcon#about to read 3, iclass 6, count 2 2006.190.08:03:21.44#ibcon#read 3, iclass 6, count 2 2006.190.08:03:21.44#ibcon#about to read 4, iclass 6, count 2 2006.190.08:03:21.44#ibcon#read 4, iclass 6, count 2 2006.190.08:03:21.44#ibcon#about to read 5, iclass 6, count 2 2006.190.08:03:21.44#ibcon#read 5, iclass 6, count 2 2006.190.08:03:21.44#ibcon#about to read 6, iclass 6, count 2 2006.190.08:03:21.44#ibcon#read 6, iclass 6, count 2 2006.190.08:03:21.44#ibcon#end of sib2, iclass 6, count 2 2006.190.08:03:21.44#ibcon#*mode == 0, iclass 6, count 2 2006.190.08:03:21.44#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.08:03:21.44#ibcon#[27=AT03-04\r\n] 2006.190.08:03:21.44#ibcon#*before write, iclass 6, count 2 2006.190.08:03:21.44#ibcon#enter sib2, iclass 6, count 2 2006.190.08:03:21.44#ibcon#flushed, iclass 6, count 2 2006.190.08:03:21.44#ibcon#about to write, iclass 6, count 2 2006.190.08:03:21.44#ibcon#wrote, iclass 6, count 2 2006.190.08:03:21.44#ibcon#about to read 3, iclass 6, count 2 2006.190.08:03:21.47#ibcon#read 3, iclass 6, count 2 2006.190.08:03:21.47#ibcon#about to read 4, iclass 6, count 2 2006.190.08:03:21.47#ibcon#read 4, iclass 6, count 2 2006.190.08:03:21.47#ibcon#about to read 5, iclass 6, count 2 2006.190.08:03:21.47#ibcon#read 5, iclass 6, count 2 2006.190.08:03:21.47#ibcon#about to read 6, iclass 6, count 2 2006.190.08:03:21.47#ibcon#read 6, iclass 6, count 2 2006.190.08:03:21.47#ibcon#end of sib2, iclass 6, count 2 2006.190.08:03:21.47#ibcon#*after write, iclass 6, count 2 2006.190.08:03:21.47#ibcon#*before return 0, iclass 6, count 2 2006.190.08:03:21.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:21.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:03:21.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.08:03:21.47#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:21.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:21.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:21.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:21.59#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:03:21.59#ibcon#first serial, iclass 6, count 0 2006.190.08:03:21.59#ibcon#enter sib2, iclass 6, count 0 2006.190.08:03:21.59#ibcon#flushed, iclass 6, count 0 2006.190.08:03:21.59#ibcon#about to write, iclass 6, count 0 2006.190.08:03:21.59#ibcon#wrote, iclass 6, count 0 2006.190.08:03:21.59#ibcon#about to read 3, iclass 6, count 0 2006.190.08:03:21.61#ibcon#read 3, iclass 6, count 0 2006.190.08:03:21.61#ibcon#about to read 4, iclass 6, count 0 2006.190.08:03:21.61#ibcon#read 4, iclass 6, count 0 2006.190.08:03:21.61#ibcon#about to read 5, iclass 6, count 0 2006.190.08:03:21.61#ibcon#read 5, iclass 6, count 0 2006.190.08:03:21.61#ibcon#about to read 6, iclass 6, count 0 2006.190.08:03:21.61#ibcon#read 6, iclass 6, count 0 2006.190.08:03:21.61#ibcon#end of sib2, iclass 6, count 0 2006.190.08:03:21.61#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:03:21.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:03:21.61#ibcon#[27=USB\r\n] 2006.190.08:03:21.61#ibcon#*before write, iclass 6, count 0 2006.190.08:03:21.61#ibcon#enter sib2, iclass 6, count 0 2006.190.08:03:21.61#ibcon#flushed, iclass 6, count 0 2006.190.08:03:21.61#ibcon#about to write, iclass 6, count 0 2006.190.08:03:21.61#ibcon#wrote, iclass 6, count 0 2006.190.08:03:21.61#ibcon#about to read 3, iclass 6, count 0 2006.190.08:03:21.64#ibcon#read 3, iclass 6, count 0 2006.190.08:03:21.64#ibcon#about to read 4, iclass 6, count 0 2006.190.08:03:21.64#ibcon#read 4, iclass 6, count 0 2006.190.08:03:21.64#ibcon#about to read 5, iclass 6, count 0 2006.190.08:03:21.64#ibcon#read 5, iclass 6, count 0 2006.190.08:03:21.64#ibcon#about to read 6, iclass 6, count 0 2006.190.08:03:21.64#ibcon#read 6, iclass 6, count 0 2006.190.08:03:21.64#ibcon#end of sib2, iclass 6, count 0 2006.190.08:03:21.64#ibcon#*after write, iclass 6, count 0 2006.190.08:03:21.64#ibcon#*before return 0, iclass 6, count 0 2006.190.08:03:21.64#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:21.64#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:03:21.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:03:21.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:03:21.64$vc4f8/vblo=4,712.99 2006.190.08:03:21.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.08:03:21.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.08:03:21.64#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:21.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:21.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:21.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:21.64#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:03:21.64#ibcon#first serial, iclass 10, count 0 2006.190.08:03:21.64#ibcon#enter sib2, iclass 10, count 0 2006.190.08:03:21.64#ibcon#flushed, iclass 10, count 0 2006.190.08:03:21.64#ibcon#about to write, iclass 10, count 0 2006.190.08:03:21.64#ibcon#wrote, iclass 10, count 0 2006.190.08:03:21.64#ibcon#about to read 3, iclass 10, count 0 2006.190.08:03:21.66#ibcon#read 3, iclass 10, count 0 2006.190.08:03:21.66#ibcon#about to read 4, iclass 10, count 0 2006.190.08:03:21.66#ibcon#read 4, iclass 10, count 0 2006.190.08:03:21.66#ibcon#about to read 5, iclass 10, count 0 2006.190.08:03:21.66#ibcon#read 5, iclass 10, count 0 2006.190.08:03:21.66#ibcon#about to read 6, iclass 10, count 0 2006.190.08:03:21.66#ibcon#read 6, iclass 10, count 0 2006.190.08:03:21.66#ibcon#end of sib2, iclass 10, count 0 2006.190.08:03:21.66#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:03:21.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:03:21.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:03:21.66#ibcon#*before write, iclass 10, count 0 2006.190.08:03:21.66#ibcon#enter sib2, iclass 10, count 0 2006.190.08:03:21.66#ibcon#flushed, iclass 10, count 0 2006.190.08:03:21.66#ibcon#about to write, iclass 10, count 0 2006.190.08:03:21.66#ibcon#wrote, iclass 10, count 0 2006.190.08:03:21.66#ibcon#about to read 3, iclass 10, count 0 2006.190.08:03:21.70#ibcon#read 3, iclass 10, count 0 2006.190.08:03:21.70#ibcon#about to read 4, iclass 10, count 0 2006.190.08:03:21.70#ibcon#read 4, iclass 10, count 0 2006.190.08:03:21.70#ibcon#about to read 5, iclass 10, count 0 2006.190.08:03:21.70#ibcon#read 5, iclass 10, count 0 2006.190.08:03:21.70#ibcon#about to read 6, iclass 10, count 0 2006.190.08:03:21.70#ibcon#read 6, iclass 10, count 0 2006.190.08:03:21.70#ibcon#end of sib2, iclass 10, count 0 2006.190.08:03:21.70#ibcon#*after write, iclass 10, count 0 2006.190.08:03:21.70#ibcon#*before return 0, iclass 10, count 0 2006.190.08:03:21.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:21.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:03:21.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:03:21.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:03:21.70$vc4f8/vb=4,4 2006.190.08:03:21.70#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.08:03:21.70#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.08:03:21.70#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:21.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:21.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:21.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:21.76#ibcon#enter wrdev, iclass 12, count 2 2006.190.08:03:21.76#ibcon#first serial, iclass 12, count 2 2006.190.08:03:21.76#ibcon#enter sib2, iclass 12, count 2 2006.190.08:03:21.76#ibcon#flushed, iclass 12, count 2 2006.190.08:03:21.76#ibcon#about to write, iclass 12, count 2 2006.190.08:03:21.76#ibcon#wrote, iclass 12, count 2 2006.190.08:03:21.76#ibcon#about to read 3, iclass 12, count 2 2006.190.08:03:21.78#ibcon#read 3, iclass 12, count 2 2006.190.08:03:21.78#ibcon#about to read 4, iclass 12, count 2 2006.190.08:03:21.78#ibcon#read 4, iclass 12, count 2 2006.190.08:03:21.78#ibcon#about to read 5, iclass 12, count 2 2006.190.08:03:21.78#ibcon#read 5, iclass 12, count 2 2006.190.08:03:21.78#ibcon#about to read 6, iclass 12, count 2 2006.190.08:03:21.78#ibcon#read 6, iclass 12, count 2 2006.190.08:03:21.78#ibcon#end of sib2, iclass 12, count 2 2006.190.08:03:21.78#ibcon#*mode == 0, iclass 12, count 2 2006.190.08:03:21.78#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.08:03:21.78#ibcon#[27=AT04-04\r\n] 2006.190.08:03:21.78#ibcon#*before write, iclass 12, count 2 2006.190.08:03:21.78#ibcon#enter sib2, iclass 12, count 2 2006.190.08:03:21.78#ibcon#flushed, iclass 12, count 2 2006.190.08:03:21.78#ibcon#about to write, iclass 12, count 2 2006.190.08:03:21.78#ibcon#wrote, iclass 12, count 2 2006.190.08:03:21.78#ibcon#about to read 3, iclass 12, count 2 2006.190.08:03:21.81#ibcon#read 3, iclass 12, count 2 2006.190.08:03:21.81#ibcon#about to read 4, iclass 12, count 2 2006.190.08:03:21.81#ibcon#read 4, iclass 12, count 2 2006.190.08:03:21.81#ibcon#about to read 5, iclass 12, count 2 2006.190.08:03:21.81#ibcon#read 5, iclass 12, count 2 2006.190.08:03:21.81#ibcon#about to read 6, iclass 12, count 2 2006.190.08:03:21.81#ibcon#read 6, iclass 12, count 2 2006.190.08:03:21.81#ibcon#end of sib2, iclass 12, count 2 2006.190.08:03:21.81#ibcon#*after write, iclass 12, count 2 2006.190.08:03:21.81#ibcon#*before return 0, iclass 12, count 2 2006.190.08:03:21.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:21.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:03:21.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.08:03:21.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:21.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:21.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:21.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:21.93#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:03:21.93#ibcon#first serial, iclass 12, count 0 2006.190.08:03:21.93#ibcon#enter sib2, iclass 12, count 0 2006.190.08:03:21.93#ibcon#flushed, iclass 12, count 0 2006.190.08:03:21.93#ibcon#about to write, iclass 12, count 0 2006.190.08:03:21.93#ibcon#wrote, iclass 12, count 0 2006.190.08:03:21.93#ibcon#about to read 3, iclass 12, count 0 2006.190.08:03:21.95#ibcon#read 3, iclass 12, count 0 2006.190.08:03:21.95#ibcon#about to read 4, iclass 12, count 0 2006.190.08:03:21.95#ibcon#read 4, iclass 12, count 0 2006.190.08:03:21.95#ibcon#about to read 5, iclass 12, count 0 2006.190.08:03:21.95#ibcon#read 5, iclass 12, count 0 2006.190.08:03:21.95#ibcon#about to read 6, iclass 12, count 0 2006.190.08:03:21.95#ibcon#read 6, iclass 12, count 0 2006.190.08:03:21.95#ibcon#end of sib2, iclass 12, count 0 2006.190.08:03:21.95#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:03:21.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:03:21.95#ibcon#[27=USB\r\n] 2006.190.08:03:21.95#ibcon#*before write, iclass 12, count 0 2006.190.08:03:21.95#ibcon#enter sib2, iclass 12, count 0 2006.190.08:03:21.95#ibcon#flushed, iclass 12, count 0 2006.190.08:03:21.95#ibcon#about to write, iclass 12, count 0 2006.190.08:03:21.95#ibcon#wrote, iclass 12, count 0 2006.190.08:03:21.95#ibcon#about to read 3, iclass 12, count 0 2006.190.08:03:21.98#ibcon#read 3, iclass 12, count 0 2006.190.08:03:21.98#ibcon#about to read 4, iclass 12, count 0 2006.190.08:03:21.98#ibcon#read 4, iclass 12, count 0 2006.190.08:03:21.98#ibcon#about to read 5, iclass 12, count 0 2006.190.08:03:21.98#ibcon#read 5, iclass 12, count 0 2006.190.08:03:21.98#ibcon#about to read 6, iclass 12, count 0 2006.190.08:03:21.98#ibcon#read 6, iclass 12, count 0 2006.190.08:03:21.98#ibcon#end of sib2, iclass 12, count 0 2006.190.08:03:21.98#ibcon#*after write, iclass 12, count 0 2006.190.08:03:21.98#ibcon#*before return 0, iclass 12, count 0 2006.190.08:03:21.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:21.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:03:21.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:03:21.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:03:21.98$vc4f8/vblo=5,744.99 2006.190.08:03:21.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.08:03:21.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.08:03:21.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:21.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:21.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:21.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:21.98#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:03:21.98#ibcon#first serial, iclass 14, count 0 2006.190.08:03:21.98#ibcon#enter sib2, iclass 14, count 0 2006.190.08:03:21.98#ibcon#flushed, iclass 14, count 0 2006.190.08:03:21.98#ibcon#about to write, iclass 14, count 0 2006.190.08:03:21.98#ibcon#wrote, iclass 14, count 0 2006.190.08:03:21.98#ibcon#about to read 3, iclass 14, count 0 2006.190.08:03:22.00#ibcon#read 3, iclass 14, count 0 2006.190.08:03:22.00#ibcon#about to read 4, iclass 14, count 0 2006.190.08:03:22.00#ibcon#read 4, iclass 14, count 0 2006.190.08:03:22.00#ibcon#about to read 5, iclass 14, count 0 2006.190.08:03:22.00#ibcon#read 5, iclass 14, count 0 2006.190.08:03:22.00#ibcon#about to read 6, iclass 14, count 0 2006.190.08:03:22.00#ibcon#read 6, iclass 14, count 0 2006.190.08:03:22.00#ibcon#end of sib2, iclass 14, count 0 2006.190.08:03:22.00#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:03:22.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:03:22.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:03:22.00#ibcon#*before write, iclass 14, count 0 2006.190.08:03:22.00#ibcon#enter sib2, iclass 14, count 0 2006.190.08:03:22.00#ibcon#flushed, iclass 14, count 0 2006.190.08:03:22.00#ibcon#about to write, iclass 14, count 0 2006.190.08:03:22.00#ibcon#wrote, iclass 14, count 0 2006.190.08:03:22.00#ibcon#about to read 3, iclass 14, count 0 2006.190.08:03:22.04#ibcon#read 3, iclass 14, count 0 2006.190.08:03:22.04#ibcon#about to read 4, iclass 14, count 0 2006.190.08:03:22.04#ibcon#read 4, iclass 14, count 0 2006.190.08:03:22.04#ibcon#about to read 5, iclass 14, count 0 2006.190.08:03:22.04#ibcon#read 5, iclass 14, count 0 2006.190.08:03:22.04#ibcon#about to read 6, iclass 14, count 0 2006.190.08:03:22.04#ibcon#read 6, iclass 14, count 0 2006.190.08:03:22.04#ibcon#end of sib2, iclass 14, count 0 2006.190.08:03:22.04#ibcon#*after write, iclass 14, count 0 2006.190.08:03:22.04#ibcon#*before return 0, iclass 14, count 0 2006.190.08:03:22.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:22.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:03:22.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:03:22.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:03:22.04$vc4f8/vb=5,4 2006.190.08:03:22.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.08:03:22.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.08:03:22.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:22.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:22.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:22.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:22.10#ibcon#enter wrdev, iclass 16, count 2 2006.190.08:03:22.10#ibcon#first serial, iclass 16, count 2 2006.190.08:03:22.10#ibcon#enter sib2, iclass 16, count 2 2006.190.08:03:22.10#ibcon#flushed, iclass 16, count 2 2006.190.08:03:22.10#ibcon#about to write, iclass 16, count 2 2006.190.08:03:22.10#ibcon#wrote, iclass 16, count 2 2006.190.08:03:22.10#ibcon#about to read 3, iclass 16, count 2 2006.190.08:03:22.12#ibcon#read 3, iclass 16, count 2 2006.190.08:03:22.12#ibcon#about to read 4, iclass 16, count 2 2006.190.08:03:22.12#ibcon#read 4, iclass 16, count 2 2006.190.08:03:22.12#ibcon#about to read 5, iclass 16, count 2 2006.190.08:03:22.12#ibcon#read 5, iclass 16, count 2 2006.190.08:03:22.12#ibcon#about to read 6, iclass 16, count 2 2006.190.08:03:22.12#ibcon#read 6, iclass 16, count 2 2006.190.08:03:22.12#ibcon#end of sib2, iclass 16, count 2 2006.190.08:03:22.12#ibcon#*mode == 0, iclass 16, count 2 2006.190.08:03:22.12#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.08:03:22.12#ibcon#[27=AT05-04\r\n] 2006.190.08:03:22.12#ibcon#*before write, iclass 16, count 2 2006.190.08:03:22.12#ibcon#enter sib2, iclass 16, count 2 2006.190.08:03:22.12#ibcon#flushed, iclass 16, count 2 2006.190.08:03:22.12#ibcon#about to write, iclass 16, count 2 2006.190.08:03:22.12#ibcon#wrote, iclass 16, count 2 2006.190.08:03:22.12#ibcon#about to read 3, iclass 16, count 2 2006.190.08:03:22.15#ibcon#read 3, iclass 16, count 2 2006.190.08:03:22.15#ibcon#about to read 4, iclass 16, count 2 2006.190.08:03:22.15#ibcon#read 4, iclass 16, count 2 2006.190.08:03:22.15#ibcon#about to read 5, iclass 16, count 2 2006.190.08:03:22.15#ibcon#read 5, iclass 16, count 2 2006.190.08:03:22.15#ibcon#about to read 6, iclass 16, count 2 2006.190.08:03:22.15#ibcon#read 6, iclass 16, count 2 2006.190.08:03:22.15#ibcon#end of sib2, iclass 16, count 2 2006.190.08:03:22.15#ibcon#*after write, iclass 16, count 2 2006.190.08:03:22.15#ibcon#*before return 0, iclass 16, count 2 2006.190.08:03:22.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:22.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:03:22.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.08:03:22.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:22.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:22.27#abcon#<5=/05 2.4 4.3 24.501001012.0\r\n> 2006.190.08:03:22.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:22.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:22.27#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:03:22.27#ibcon#first serial, iclass 16, count 0 2006.190.08:03:22.27#ibcon#enter sib2, iclass 16, count 0 2006.190.08:03:22.27#ibcon#flushed, iclass 16, count 0 2006.190.08:03:22.27#ibcon#about to write, iclass 16, count 0 2006.190.08:03:22.27#ibcon#wrote, iclass 16, count 0 2006.190.08:03:22.27#ibcon#about to read 3, iclass 16, count 0 2006.190.08:03:22.29#ibcon#read 3, iclass 16, count 0 2006.190.08:03:22.29#ibcon#about to read 4, iclass 16, count 0 2006.190.08:03:22.29#ibcon#read 4, iclass 16, count 0 2006.190.08:03:22.29#ibcon#about to read 5, iclass 16, count 0 2006.190.08:03:22.29#ibcon#read 5, iclass 16, count 0 2006.190.08:03:22.29#ibcon#about to read 6, iclass 16, count 0 2006.190.08:03:22.29#ibcon#read 6, iclass 16, count 0 2006.190.08:03:22.29#ibcon#end of sib2, iclass 16, count 0 2006.190.08:03:22.29#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:03:22.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:03:22.29#ibcon#[27=USB\r\n] 2006.190.08:03:22.29#ibcon#*before write, iclass 16, count 0 2006.190.08:03:22.29#ibcon#enter sib2, iclass 16, count 0 2006.190.08:03:22.29#ibcon#flushed, iclass 16, count 0 2006.190.08:03:22.29#ibcon#about to write, iclass 16, count 0 2006.190.08:03:22.29#ibcon#wrote, iclass 16, count 0 2006.190.08:03:22.29#ibcon#about to read 3, iclass 16, count 0 2006.190.08:03:22.29#abcon#{5=INTERFACE CLEAR} 2006.190.08:03:22.32#ibcon#read 3, iclass 16, count 0 2006.190.08:03:22.32#ibcon#about to read 4, iclass 16, count 0 2006.190.08:03:22.32#ibcon#read 4, iclass 16, count 0 2006.190.08:03:22.32#ibcon#about to read 5, iclass 16, count 0 2006.190.08:03:22.32#ibcon#read 5, iclass 16, count 0 2006.190.08:03:22.32#ibcon#about to read 6, iclass 16, count 0 2006.190.08:03:22.32#ibcon#read 6, iclass 16, count 0 2006.190.08:03:22.32#ibcon#end of sib2, iclass 16, count 0 2006.190.08:03:22.32#ibcon#*after write, iclass 16, count 0 2006.190.08:03:22.32#ibcon#*before return 0, iclass 16, count 0 2006.190.08:03:22.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:22.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:03:22.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:03:22.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:03:22.32$vc4f8/vblo=6,752.99 2006.190.08:03:22.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.08:03:22.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.08:03:22.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:03:22.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:03:22.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:03:22.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:03:22.32#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:03:22.32#ibcon#first serial, iclass 21, count 0 2006.190.08:03:22.32#ibcon#enter sib2, iclass 21, count 0 2006.190.08:03:22.32#ibcon#flushed, iclass 21, count 0 2006.190.08:03:22.32#ibcon#about to write, iclass 21, count 0 2006.190.08:03:22.32#ibcon#wrote, iclass 21, count 0 2006.190.08:03:22.32#ibcon#about to read 3, iclass 21, count 0 2006.190.08:03:22.34#ibcon#read 3, iclass 21, count 0 2006.190.08:03:22.34#ibcon#about to read 4, iclass 21, count 0 2006.190.08:03:22.34#ibcon#read 4, iclass 21, count 0 2006.190.08:03:22.34#ibcon#about to read 5, iclass 21, count 0 2006.190.08:03:22.34#ibcon#read 5, iclass 21, count 0 2006.190.08:03:22.34#ibcon#about to read 6, iclass 21, count 0 2006.190.08:03:22.34#ibcon#read 6, iclass 21, count 0 2006.190.08:03:22.34#ibcon#end of sib2, iclass 21, count 0 2006.190.08:03:22.34#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:03:22.34#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:03:22.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:03:22.34#ibcon#*before write, iclass 21, count 0 2006.190.08:03:22.34#ibcon#enter sib2, iclass 21, count 0 2006.190.08:03:22.34#ibcon#flushed, iclass 21, count 0 2006.190.08:03:22.34#ibcon#about to write, iclass 21, count 0 2006.190.08:03:22.34#ibcon#wrote, iclass 21, count 0 2006.190.08:03:22.34#ibcon#about to read 3, iclass 21, count 0 2006.190.08:03:22.35#abcon#[5=S1D000X0/0*\r\n] 2006.190.08:03:22.38#ibcon#read 3, iclass 21, count 0 2006.190.08:03:22.38#ibcon#about to read 4, iclass 21, count 0 2006.190.08:03:22.38#ibcon#read 4, iclass 21, count 0 2006.190.08:03:22.38#ibcon#about to read 5, iclass 21, count 0 2006.190.08:03:22.38#ibcon#read 5, iclass 21, count 0 2006.190.08:03:22.38#ibcon#about to read 6, iclass 21, count 0 2006.190.08:03:22.38#ibcon#read 6, iclass 21, count 0 2006.190.08:03:22.38#ibcon#end of sib2, iclass 21, count 0 2006.190.08:03:22.38#ibcon#*after write, iclass 21, count 0 2006.190.08:03:22.38#ibcon#*before return 0, iclass 21, count 0 2006.190.08:03:22.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:03:22.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:03:22.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:03:22.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:03:22.38$vc4f8/vb=6,4 2006.190.08:03:22.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.08:03:22.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.08:03:22.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:03:22.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:22.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:22.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:22.44#ibcon#enter wrdev, iclass 24, count 2 2006.190.08:03:22.44#ibcon#first serial, iclass 24, count 2 2006.190.08:03:22.44#ibcon#enter sib2, iclass 24, count 2 2006.190.08:03:22.44#ibcon#flushed, iclass 24, count 2 2006.190.08:03:22.44#ibcon#about to write, iclass 24, count 2 2006.190.08:03:22.44#ibcon#wrote, iclass 24, count 2 2006.190.08:03:22.44#ibcon#about to read 3, iclass 24, count 2 2006.190.08:03:22.46#ibcon#read 3, iclass 24, count 2 2006.190.08:03:22.46#ibcon#about to read 4, iclass 24, count 2 2006.190.08:03:22.46#ibcon#read 4, iclass 24, count 2 2006.190.08:03:22.46#ibcon#about to read 5, iclass 24, count 2 2006.190.08:03:22.46#ibcon#read 5, iclass 24, count 2 2006.190.08:03:22.46#ibcon#about to read 6, iclass 24, count 2 2006.190.08:03:22.46#ibcon#read 6, iclass 24, count 2 2006.190.08:03:22.46#ibcon#end of sib2, iclass 24, count 2 2006.190.08:03:22.46#ibcon#*mode == 0, iclass 24, count 2 2006.190.08:03:22.46#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.08:03:22.46#ibcon#[27=AT06-04\r\n] 2006.190.08:03:22.46#ibcon#*before write, iclass 24, count 2 2006.190.08:03:22.46#ibcon#enter sib2, iclass 24, count 2 2006.190.08:03:22.46#ibcon#flushed, iclass 24, count 2 2006.190.08:03:22.46#ibcon#about to write, iclass 24, count 2 2006.190.08:03:22.46#ibcon#wrote, iclass 24, count 2 2006.190.08:03:22.46#ibcon#about to read 3, iclass 24, count 2 2006.190.08:03:22.49#ibcon#read 3, iclass 24, count 2 2006.190.08:03:22.49#ibcon#about to read 4, iclass 24, count 2 2006.190.08:03:22.49#ibcon#read 4, iclass 24, count 2 2006.190.08:03:22.49#ibcon#about to read 5, iclass 24, count 2 2006.190.08:03:22.49#ibcon#read 5, iclass 24, count 2 2006.190.08:03:22.49#ibcon#about to read 6, iclass 24, count 2 2006.190.08:03:22.49#ibcon#read 6, iclass 24, count 2 2006.190.08:03:22.49#ibcon#end of sib2, iclass 24, count 2 2006.190.08:03:22.49#ibcon#*after write, iclass 24, count 2 2006.190.08:03:22.49#ibcon#*before return 0, iclass 24, count 2 2006.190.08:03:22.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:22.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:03:22.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.08:03:22.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:03:22.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:22.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:22.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:22.61#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:03:22.61#ibcon#first serial, iclass 24, count 0 2006.190.08:03:22.61#ibcon#enter sib2, iclass 24, count 0 2006.190.08:03:22.61#ibcon#flushed, iclass 24, count 0 2006.190.08:03:22.61#ibcon#about to write, iclass 24, count 0 2006.190.08:03:22.61#ibcon#wrote, iclass 24, count 0 2006.190.08:03:22.61#ibcon#about to read 3, iclass 24, count 0 2006.190.08:03:22.63#ibcon#read 3, iclass 24, count 0 2006.190.08:03:22.63#ibcon#about to read 4, iclass 24, count 0 2006.190.08:03:22.63#ibcon#read 4, iclass 24, count 0 2006.190.08:03:22.63#ibcon#about to read 5, iclass 24, count 0 2006.190.08:03:22.63#ibcon#read 5, iclass 24, count 0 2006.190.08:03:22.63#ibcon#about to read 6, iclass 24, count 0 2006.190.08:03:22.63#ibcon#read 6, iclass 24, count 0 2006.190.08:03:22.63#ibcon#end of sib2, iclass 24, count 0 2006.190.08:03:22.63#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:03:22.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:03:22.63#ibcon#[27=USB\r\n] 2006.190.08:03:22.63#ibcon#*before write, iclass 24, count 0 2006.190.08:03:22.63#ibcon#enter sib2, iclass 24, count 0 2006.190.08:03:22.63#ibcon#flushed, iclass 24, count 0 2006.190.08:03:22.63#ibcon#about to write, iclass 24, count 0 2006.190.08:03:22.63#ibcon#wrote, iclass 24, count 0 2006.190.08:03:22.63#ibcon#about to read 3, iclass 24, count 0 2006.190.08:03:22.66#ibcon#read 3, iclass 24, count 0 2006.190.08:03:22.66#ibcon#about to read 4, iclass 24, count 0 2006.190.08:03:22.66#ibcon#read 4, iclass 24, count 0 2006.190.08:03:22.66#ibcon#about to read 5, iclass 24, count 0 2006.190.08:03:22.66#ibcon#read 5, iclass 24, count 0 2006.190.08:03:22.66#ibcon#about to read 6, iclass 24, count 0 2006.190.08:03:22.66#ibcon#read 6, iclass 24, count 0 2006.190.08:03:22.66#ibcon#end of sib2, iclass 24, count 0 2006.190.08:03:22.66#ibcon#*after write, iclass 24, count 0 2006.190.08:03:22.66#ibcon#*before return 0, iclass 24, count 0 2006.190.08:03:22.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:22.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:03:22.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:03:22.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:03:22.66$vc4f8/vabw=wide 2006.190.08:03:22.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.08:03:22.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.08:03:22.66#ibcon#ireg 8 cls_cnt 0 2006.190.08:03:22.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:22.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:22.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:22.66#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:03:22.66#ibcon#first serial, iclass 26, count 0 2006.190.08:03:22.66#ibcon#enter sib2, iclass 26, count 0 2006.190.08:03:22.66#ibcon#flushed, iclass 26, count 0 2006.190.08:03:22.66#ibcon#about to write, iclass 26, count 0 2006.190.08:03:22.66#ibcon#wrote, iclass 26, count 0 2006.190.08:03:22.66#ibcon#about to read 3, iclass 26, count 0 2006.190.08:03:22.68#ibcon#read 3, iclass 26, count 0 2006.190.08:03:22.68#ibcon#about to read 4, iclass 26, count 0 2006.190.08:03:22.68#ibcon#read 4, iclass 26, count 0 2006.190.08:03:22.68#ibcon#about to read 5, iclass 26, count 0 2006.190.08:03:22.68#ibcon#read 5, iclass 26, count 0 2006.190.08:03:22.68#ibcon#about to read 6, iclass 26, count 0 2006.190.08:03:22.68#ibcon#read 6, iclass 26, count 0 2006.190.08:03:22.68#ibcon#end of sib2, iclass 26, count 0 2006.190.08:03:22.68#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:03:22.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:03:22.68#ibcon#[25=BW32\r\n] 2006.190.08:03:22.68#ibcon#*before write, iclass 26, count 0 2006.190.08:03:22.68#ibcon#enter sib2, iclass 26, count 0 2006.190.08:03:22.68#ibcon#flushed, iclass 26, count 0 2006.190.08:03:22.68#ibcon#about to write, iclass 26, count 0 2006.190.08:03:22.68#ibcon#wrote, iclass 26, count 0 2006.190.08:03:22.68#ibcon#about to read 3, iclass 26, count 0 2006.190.08:03:22.71#ibcon#read 3, iclass 26, count 0 2006.190.08:03:22.71#ibcon#about to read 4, iclass 26, count 0 2006.190.08:03:22.71#ibcon#read 4, iclass 26, count 0 2006.190.08:03:22.71#ibcon#about to read 5, iclass 26, count 0 2006.190.08:03:22.71#ibcon#read 5, iclass 26, count 0 2006.190.08:03:22.71#ibcon#about to read 6, iclass 26, count 0 2006.190.08:03:22.71#ibcon#read 6, iclass 26, count 0 2006.190.08:03:22.71#ibcon#end of sib2, iclass 26, count 0 2006.190.08:03:22.71#ibcon#*after write, iclass 26, count 0 2006.190.08:03:22.71#ibcon#*before return 0, iclass 26, count 0 2006.190.08:03:22.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:22.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:03:22.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:03:22.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:03:22.71$vc4f8/vbbw=wide 2006.190.08:03:22.71#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.08:03:22.71#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.08:03:22.71#ibcon#ireg 8 cls_cnt 0 2006.190.08:03:22.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:03:22.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:03:22.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:03:22.78#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:03:22.78#ibcon#first serial, iclass 28, count 0 2006.190.08:03:22.78#ibcon#enter sib2, iclass 28, count 0 2006.190.08:03:22.78#ibcon#flushed, iclass 28, count 0 2006.190.08:03:22.78#ibcon#about to write, iclass 28, count 0 2006.190.08:03:22.78#ibcon#wrote, iclass 28, count 0 2006.190.08:03:22.78#ibcon#about to read 3, iclass 28, count 0 2006.190.08:03:22.80#ibcon#read 3, iclass 28, count 0 2006.190.08:03:22.80#ibcon#about to read 4, iclass 28, count 0 2006.190.08:03:22.80#ibcon#read 4, iclass 28, count 0 2006.190.08:03:22.80#ibcon#about to read 5, iclass 28, count 0 2006.190.08:03:22.80#ibcon#read 5, iclass 28, count 0 2006.190.08:03:22.80#ibcon#about to read 6, iclass 28, count 0 2006.190.08:03:22.80#ibcon#read 6, iclass 28, count 0 2006.190.08:03:22.80#ibcon#end of sib2, iclass 28, count 0 2006.190.08:03:22.80#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:03:22.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:03:22.80#ibcon#[27=BW32\r\n] 2006.190.08:03:22.80#ibcon#*before write, iclass 28, count 0 2006.190.08:03:22.80#ibcon#enter sib2, iclass 28, count 0 2006.190.08:03:22.80#ibcon#flushed, iclass 28, count 0 2006.190.08:03:22.80#ibcon#about to write, iclass 28, count 0 2006.190.08:03:22.80#ibcon#wrote, iclass 28, count 0 2006.190.08:03:22.80#ibcon#about to read 3, iclass 28, count 0 2006.190.08:03:22.83#ibcon#read 3, iclass 28, count 0 2006.190.08:03:22.83#ibcon#about to read 4, iclass 28, count 0 2006.190.08:03:22.83#ibcon#read 4, iclass 28, count 0 2006.190.08:03:22.83#ibcon#about to read 5, iclass 28, count 0 2006.190.08:03:22.83#ibcon#read 5, iclass 28, count 0 2006.190.08:03:22.83#ibcon#about to read 6, iclass 28, count 0 2006.190.08:03:22.83#ibcon#read 6, iclass 28, count 0 2006.190.08:03:22.83#ibcon#end of sib2, iclass 28, count 0 2006.190.08:03:22.83#ibcon#*after write, iclass 28, count 0 2006.190.08:03:22.83#ibcon#*before return 0, iclass 28, count 0 2006.190.08:03:22.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:03:22.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:03:22.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:03:22.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:03:22.83$4f8m12a/ifd4f 2006.190.08:03:22.83$ifd4f/lo= 2006.190.08:03:22.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:03:22.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:03:22.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:03:22.83$ifd4f/patch= 2006.190.08:03:22.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:03:22.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:03:22.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:03:22.84$4f8m12a/"form=m,16.000,1:2 2006.190.08:03:22.84$4f8m12a/"tpicd 2006.190.08:03:22.84$4f8m12a/echo=off 2006.190.08:03:22.84$4f8m12a/xlog=off 2006.190.08:03:22.84:!2006.190.08:03:50 2006.190.08:03:36.13#trakl#Source acquired 2006.190.08:03:38.13#flagr#flagr/antenna,acquired 2006.190.08:03:50.01:preob 2006.190.08:03:51.13/onsource/TRACKING 2006.190.08:03:51.13:!2006.190.08:04:00 2006.190.08:04:00.00:data_valid=on 2006.190.08:04:00.00:midob 2006.190.08:04:00.13/onsource/TRACKING 2006.190.08:04:00.13/wx/24.48,1012.0,100 2006.190.08:04:00.29/cable/+6.4700E-03 2006.190.08:04:01.38/va/01,08,usb,yes,38,40 2006.190.08:04:01.38/va/02,07,usb,yes,39,40 2006.190.08:04:01.38/va/03,06,usb,yes,40,41 2006.190.08:04:01.38/va/04,07,usb,yes,39,42 2006.190.08:04:01.38/va/05,07,usb,yes,44,46 2006.190.08:04:01.38/va/06,06,usb,yes,43,42 2006.190.08:04:01.38/va/07,06,usb,yes,43,43 2006.190.08:04:01.38/va/08,06,usb,yes,46,45 2006.190.08:04:01.61/valo/01,532.99,yes,locked 2006.190.08:04:01.61/valo/02,572.99,yes,locked 2006.190.08:04:01.61/valo/03,672.99,yes,locked 2006.190.08:04:01.61/valo/04,832.99,yes,locked 2006.190.08:04:01.61/valo/05,652.99,yes,locked 2006.190.08:04:01.61/valo/06,772.99,yes,locked 2006.190.08:04:01.61/valo/07,832.99,yes,locked 2006.190.08:04:01.61/valo/08,852.99,yes,locked 2006.190.08:04:02.70/vb/01,04,usb,yes,32,31 2006.190.08:04:02.70/vb/02,04,usb,yes,34,35 2006.190.08:04:02.70/vb/03,04,usb,yes,30,34 2006.190.08:04:02.70/vb/04,04,usb,yes,31,31 2006.190.08:04:02.70/vb/05,04,usb,yes,30,34 2006.190.08:04:02.70/vb/06,04,usb,yes,31,34 2006.190.08:04:02.70/vb/07,04,usb,yes,33,33 2006.190.08:04:02.70/vb/08,04,usb,yes,30,34 2006.190.08:04:02.94/vblo/01,632.99,yes,locked 2006.190.08:04:02.94/vblo/02,640.99,yes,locked 2006.190.08:04:02.94/vblo/03,656.99,yes,locked 2006.190.08:04:02.94/vblo/04,712.99,yes,locked 2006.190.08:04:02.94/vblo/05,744.99,yes,locked 2006.190.08:04:02.94/vblo/06,752.99,yes,locked 2006.190.08:04:02.94/vblo/07,734.99,yes,locked 2006.190.08:04:02.94/vblo/08,744.99,yes,locked 2006.190.08:04:03.09/vabw/8 2006.190.08:04:03.24/vbbw/8 2006.190.08:04:03.33/xfe/off,on,14.7 2006.190.08:04:03.70/ifatt/23,28,28,28 2006.190.08:04:04.07/fmout-gps/S +2.85E-07 2006.190.08:04:04.16:!2006.190.08:05:00 2006.190.08:05:00.01:data_valid=off 2006.190.08:05:00.02:postob 2006.190.08:05:00.12/cable/+6.4708E-03 2006.190.08:05:00.13/wx/24.47,1012.0,100 2006.190.08:05:01.07/fmout-gps/S +2.85E-07 2006.190.08:05:01.08:scan_name=190-0805,k06190,60 2006.190.08:05:01.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.190.08:05:01.16#flagr#flagr/antenna,new-source 2006.190.08:05:02.12:checkk5 2006.190.08:05:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:05:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:05:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:05:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:05:04.02/chk_obsdata//k5ts1/T1900804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:05:04.40/chk_obsdata//k5ts2/T1900804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:05:04.78/chk_obsdata//k5ts3/T1900804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:05:05.15/chk_obsdata//k5ts4/T1900804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:05:05.85/k5log//k5ts1_log_newline 2006.190.08:05:06.54/k5log//k5ts2_log_newline 2006.190.08:05:07.24/k5log//k5ts3_log_newline 2006.190.08:05:07.93/k5log//k5ts4_log_newline 2006.190.08:05:07.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:05:07.95:4f8m12a=2 2006.190.08:05:07.96$4f8m12a/echo=on 2006.190.08:05:07.96$4f8m12a/pcalon 2006.190.08:05:07.96$pcalon/"no phase cal control is implemented here 2006.190.08:05:07.96$4f8m12a/"tpicd=stop 2006.190.08:05:07.96$4f8m12a/vc4f8 2006.190.08:05:07.96$vc4f8/valo=1,532.99 2006.190.08:05:07.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.08:05:07.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.08:05:07.96#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:07.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:07.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:07.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:07.96#ibcon#enter wrdev, iclass 35, count 0 2006.190.08:05:07.96#ibcon#first serial, iclass 35, count 0 2006.190.08:05:07.96#ibcon#enter sib2, iclass 35, count 0 2006.190.08:05:07.96#ibcon#flushed, iclass 35, count 0 2006.190.08:05:07.96#ibcon#about to write, iclass 35, count 0 2006.190.08:05:07.96#ibcon#wrote, iclass 35, count 0 2006.190.08:05:07.96#ibcon#about to read 3, iclass 35, count 0 2006.190.08:05:07.97#ibcon#read 3, iclass 35, count 0 2006.190.08:05:07.97#ibcon#about to read 4, iclass 35, count 0 2006.190.08:05:07.97#ibcon#read 4, iclass 35, count 0 2006.190.08:05:07.97#ibcon#about to read 5, iclass 35, count 0 2006.190.08:05:07.97#ibcon#read 5, iclass 35, count 0 2006.190.08:05:07.97#ibcon#about to read 6, iclass 35, count 0 2006.190.08:05:07.97#ibcon#read 6, iclass 35, count 0 2006.190.08:05:07.97#ibcon#end of sib2, iclass 35, count 0 2006.190.08:05:07.97#ibcon#*mode == 0, iclass 35, count 0 2006.190.08:05:07.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.08:05:07.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:05:07.97#ibcon#*before write, iclass 35, count 0 2006.190.08:05:07.97#ibcon#enter sib2, iclass 35, count 0 2006.190.08:05:07.97#ibcon#flushed, iclass 35, count 0 2006.190.08:05:07.97#ibcon#about to write, iclass 35, count 0 2006.190.08:05:07.97#ibcon#wrote, iclass 35, count 0 2006.190.08:05:07.97#ibcon#about to read 3, iclass 35, count 0 2006.190.08:05:08.02#ibcon#read 3, iclass 35, count 0 2006.190.08:05:08.02#ibcon#about to read 4, iclass 35, count 0 2006.190.08:05:08.02#ibcon#read 4, iclass 35, count 0 2006.190.08:05:08.02#ibcon#about to read 5, iclass 35, count 0 2006.190.08:05:08.02#ibcon#read 5, iclass 35, count 0 2006.190.08:05:08.02#ibcon#about to read 6, iclass 35, count 0 2006.190.08:05:08.02#ibcon#read 6, iclass 35, count 0 2006.190.08:05:08.02#ibcon#end of sib2, iclass 35, count 0 2006.190.08:05:08.02#ibcon#*after write, iclass 35, count 0 2006.190.08:05:08.02#ibcon#*before return 0, iclass 35, count 0 2006.190.08:05:08.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:08.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:08.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.08:05:08.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.08:05:08.02$vc4f8/va=1,8 2006.190.08:05:08.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.08:05:08.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.08:05:08.02#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:08.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:08.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:08.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:08.02#ibcon#enter wrdev, iclass 37, count 2 2006.190.08:05:08.02#ibcon#first serial, iclass 37, count 2 2006.190.08:05:08.02#ibcon#enter sib2, iclass 37, count 2 2006.190.08:05:08.02#ibcon#flushed, iclass 37, count 2 2006.190.08:05:08.02#ibcon#about to write, iclass 37, count 2 2006.190.08:05:08.02#ibcon#wrote, iclass 37, count 2 2006.190.08:05:08.02#ibcon#about to read 3, iclass 37, count 2 2006.190.08:05:08.04#ibcon#read 3, iclass 37, count 2 2006.190.08:05:08.04#ibcon#about to read 4, iclass 37, count 2 2006.190.08:05:08.04#ibcon#read 4, iclass 37, count 2 2006.190.08:05:08.04#ibcon#about to read 5, iclass 37, count 2 2006.190.08:05:08.04#ibcon#read 5, iclass 37, count 2 2006.190.08:05:08.04#ibcon#about to read 6, iclass 37, count 2 2006.190.08:05:08.04#ibcon#read 6, iclass 37, count 2 2006.190.08:05:08.04#ibcon#end of sib2, iclass 37, count 2 2006.190.08:05:08.04#ibcon#*mode == 0, iclass 37, count 2 2006.190.08:05:08.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.08:05:08.04#ibcon#[25=AT01-08\r\n] 2006.190.08:05:08.04#ibcon#*before write, iclass 37, count 2 2006.190.08:05:08.04#ibcon#enter sib2, iclass 37, count 2 2006.190.08:05:08.04#ibcon#flushed, iclass 37, count 2 2006.190.08:05:08.04#ibcon#about to write, iclass 37, count 2 2006.190.08:05:08.04#ibcon#wrote, iclass 37, count 2 2006.190.08:05:08.04#ibcon#about to read 3, iclass 37, count 2 2006.190.08:05:08.07#ibcon#read 3, iclass 37, count 2 2006.190.08:05:08.07#ibcon#about to read 4, iclass 37, count 2 2006.190.08:05:08.07#ibcon#read 4, iclass 37, count 2 2006.190.08:05:08.07#ibcon#about to read 5, iclass 37, count 2 2006.190.08:05:08.07#ibcon#read 5, iclass 37, count 2 2006.190.08:05:08.07#ibcon#about to read 6, iclass 37, count 2 2006.190.08:05:08.07#ibcon#read 6, iclass 37, count 2 2006.190.08:05:08.07#ibcon#end of sib2, iclass 37, count 2 2006.190.08:05:08.07#ibcon#*after write, iclass 37, count 2 2006.190.08:05:08.07#ibcon#*before return 0, iclass 37, count 2 2006.190.08:05:08.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:08.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:08.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.08:05:08.07#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:08.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:08.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:08.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:08.20#ibcon#enter wrdev, iclass 37, count 0 2006.190.08:05:08.20#ibcon#first serial, iclass 37, count 0 2006.190.08:05:08.20#ibcon#enter sib2, iclass 37, count 0 2006.190.08:05:08.20#ibcon#flushed, iclass 37, count 0 2006.190.08:05:08.20#ibcon#about to write, iclass 37, count 0 2006.190.08:05:08.20#ibcon#wrote, iclass 37, count 0 2006.190.08:05:08.20#ibcon#about to read 3, iclass 37, count 0 2006.190.08:05:08.22#ibcon#read 3, iclass 37, count 0 2006.190.08:05:08.22#ibcon#about to read 4, iclass 37, count 0 2006.190.08:05:08.22#ibcon#read 4, iclass 37, count 0 2006.190.08:05:08.22#ibcon#about to read 5, iclass 37, count 0 2006.190.08:05:08.22#ibcon#read 5, iclass 37, count 0 2006.190.08:05:08.22#ibcon#about to read 6, iclass 37, count 0 2006.190.08:05:08.22#ibcon#read 6, iclass 37, count 0 2006.190.08:05:08.22#ibcon#end of sib2, iclass 37, count 0 2006.190.08:05:08.22#ibcon#*mode == 0, iclass 37, count 0 2006.190.08:05:08.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.08:05:08.22#ibcon#[25=USB\r\n] 2006.190.08:05:08.22#ibcon#*before write, iclass 37, count 0 2006.190.08:05:08.22#ibcon#enter sib2, iclass 37, count 0 2006.190.08:05:08.22#ibcon#flushed, iclass 37, count 0 2006.190.08:05:08.22#ibcon#about to write, iclass 37, count 0 2006.190.08:05:08.22#ibcon#wrote, iclass 37, count 0 2006.190.08:05:08.22#ibcon#about to read 3, iclass 37, count 0 2006.190.08:05:08.25#ibcon#read 3, iclass 37, count 0 2006.190.08:05:08.25#ibcon#about to read 4, iclass 37, count 0 2006.190.08:05:08.25#ibcon#read 4, iclass 37, count 0 2006.190.08:05:08.25#ibcon#about to read 5, iclass 37, count 0 2006.190.08:05:08.25#ibcon#read 5, iclass 37, count 0 2006.190.08:05:08.25#ibcon#about to read 6, iclass 37, count 0 2006.190.08:05:08.25#ibcon#read 6, iclass 37, count 0 2006.190.08:05:08.25#ibcon#end of sib2, iclass 37, count 0 2006.190.08:05:08.25#ibcon#*after write, iclass 37, count 0 2006.190.08:05:08.25#ibcon#*before return 0, iclass 37, count 0 2006.190.08:05:08.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:08.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:08.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.08:05:08.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.08:05:08.25$vc4f8/valo=2,572.99 2006.190.08:05:08.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.08:05:08.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.08:05:08.25#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:08.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:08.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:08.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:08.25#ibcon#enter wrdev, iclass 39, count 0 2006.190.08:05:08.25#ibcon#first serial, iclass 39, count 0 2006.190.08:05:08.25#ibcon#enter sib2, iclass 39, count 0 2006.190.08:05:08.25#ibcon#flushed, iclass 39, count 0 2006.190.08:05:08.25#ibcon#about to write, iclass 39, count 0 2006.190.08:05:08.25#ibcon#wrote, iclass 39, count 0 2006.190.08:05:08.25#ibcon#about to read 3, iclass 39, count 0 2006.190.08:05:08.27#ibcon#read 3, iclass 39, count 0 2006.190.08:05:08.27#ibcon#about to read 4, iclass 39, count 0 2006.190.08:05:08.27#ibcon#read 4, iclass 39, count 0 2006.190.08:05:08.27#ibcon#about to read 5, iclass 39, count 0 2006.190.08:05:08.27#ibcon#read 5, iclass 39, count 0 2006.190.08:05:08.27#ibcon#about to read 6, iclass 39, count 0 2006.190.08:05:08.27#ibcon#read 6, iclass 39, count 0 2006.190.08:05:08.27#ibcon#end of sib2, iclass 39, count 0 2006.190.08:05:08.27#ibcon#*mode == 0, iclass 39, count 0 2006.190.08:05:08.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.08:05:08.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:05:08.27#ibcon#*before write, iclass 39, count 0 2006.190.08:05:08.27#ibcon#enter sib2, iclass 39, count 0 2006.190.08:05:08.27#ibcon#flushed, iclass 39, count 0 2006.190.08:05:08.27#ibcon#about to write, iclass 39, count 0 2006.190.08:05:08.27#ibcon#wrote, iclass 39, count 0 2006.190.08:05:08.27#ibcon#about to read 3, iclass 39, count 0 2006.190.08:05:08.31#ibcon#read 3, iclass 39, count 0 2006.190.08:05:08.31#ibcon#about to read 4, iclass 39, count 0 2006.190.08:05:08.31#ibcon#read 4, iclass 39, count 0 2006.190.08:05:08.31#ibcon#about to read 5, iclass 39, count 0 2006.190.08:05:08.31#ibcon#read 5, iclass 39, count 0 2006.190.08:05:08.31#ibcon#about to read 6, iclass 39, count 0 2006.190.08:05:08.31#ibcon#read 6, iclass 39, count 0 2006.190.08:05:08.31#ibcon#end of sib2, iclass 39, count 0 2006.190.08:05:08.31#ibcon#*after write, iclass 39, count 0 2006.190.08:05:08.31#ibcon#*before return 0, iclass 39, count 0 2006.190.08:05:08.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:08.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:08.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.08:05:08.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.08:05:08.31$vc4f8/va=2,7 2006.190.08:05:08.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.08:05:08.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.08:05:08.31#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:08.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:08.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:08.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:08.37#ibcon#enter wrdev, iclass 3, count 2 2006.190.08:05:08.37#ibcon#first serial, iclass 3, count 2 2006.190.08:05:08.37#ibcon#enter sib2, iclass 3, count 2 2006.190.08:05:08.37#ibcon#flushed, iclass 3, count 2 2006.190.08:05:08.37#ibcon#about to write, iclass 3, count 2 2006.190.08:05:08.37#ibcon#wrote, iclass 3, count 2 2006.190.08:05:08.37#ibcon#about to read 3, iclass 3, count 2 2006.190.08:05:08.39#ibcon#read 3, iclass 3, count 2 2006.190.08:05:08.39#ibcon#about to read 4, iclass 3, count 2 2006.190.08:05:08.39#ibcon#read 4, iclass 3, count 2 2006.190.08:05:08.39#ibcon#about to read 5, iclass 3, count 2 2006.190.08:05:08.39#ibcon#read 5, iclass 3, count 2 2006.190.08:05:08.39#ibcon#about to read 6, iclass 3, count 2 2006.190.08:05:08.39#ibcon#read 6, iclass 3, count 2 2006.190.08:05:08.39#ibcon#end of sib2, iclass 3, count 2 2006.190.08:05:08.39#ibcon#*mode == 0, iclass 3, count 2 2006.190.08:05:08.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.08:05:08.39#ibcon#[25=AT02-07\r\n] 2006.190.08:05:08.39#ibcon#*before write, iclass 3, count 2 2006.190.08:05:08.39#ibcon#enter sib2, iclass 3, count 2 2006.190.08:05:08.39#ibcon#flushed, iclass 3, count 2 2006.190.08:05:08.39#ibcon#about to write, iclass 3, count 2 2006.190.08:05:08.39#ibcon#wrote, iclass 3, count 2 2006.190.08:05:08.39#ibcon#about to read 3, iclass 3, count 2 2006.190.08:05:08.43#ibcon#read 3, iclass 3, count 2 2006.190.08:05:08.43#ibcon#about to read 4, iclass 3, count 2 2006.190.08:05:08.43#ibcon#read 4, iclass 3, count 2 2006.190.08:05:08.43#ibcon#about to read 5, iclass 3, count 2 2006.190.08:05:08.43#ibcon#read 5, iclass 3, count 2 2006.190.08:05:08.43#ibcon#about to read 6, iclass 3, count 2 2006.190.08:05:08.43#ibcon#read 6, iclass 3, count 2 2006.190.08:05:08.43#ibcon#end of sib2, iclass 3, count 2 2006.190.08:05:08.43#ibcon#*after write, iclass 3, count 2 2006.190.08:05:08.43#ibcon#*before return 0, iclass 3, count 2 2006.190.08:05:08.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:08.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:08.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.08:05:08.43#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:08.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:08.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:08.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:08.55#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:05:08.55#ibcon#first serial, iclass 3, count 0 2006.190.08:05:08.55#ibcon#enter sib2, iclass 3, count 0 2006.190.08:05:08.55#ibcon#flushed, iclass 3, count 0 2006.190.08:05:08.55#ibcon#about to write, iclass 3, count 0 2006.190.08:05:08.55#ibcon#wrote, iclass 3, count 0 2006.190.08:05:08.55#ibcon#about to read 3, iclass 3, count 0 2006.190.08:05:08.56#ibcon#read 3, iclass 3, count 0 2006.190.08:05:08.56#ibcon#about to read 4, iclass 3, count 0 2006.190.08:05:08.56#ibcon#read 4, iclass 3, count 0 2006.190.08:05:08.56#ibcon#about to read 5, iclass 3, count 0 2006.190.08:05:08.56#ibcon#read 5, iclass 3, count 0 2006.190.08:05:08.56#ibcon#about to read 6, iclass 3, count 0 2006.190.08:05:08.56#ibcon#read 6, iclass 3, count 0 2006.190.08:05:08.56#ibcon#end of sib2, iclass 3, count 0 2006.190.08:05:08.56#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:05:08.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:05:08.56#ibcon#[25=USB\r\n] 2006.190.08:05:08.56#ibcon#*before write, iclass 3, count 0 2006.190.08:05:08.56#ibcon#enter sib2, iclass 3, count 0 2006.190.08:05:08.56#ibcon#flushed, iclass 3, count 0 2006.190.08:05:08.56#ibcon#about to write, iclass 3, count 0 2006.190.08:05:08.56#ibcon#wrote, iclass 3, count 0 2006.190.08:05:08.56#ibcon#about to read 3, iclass 3, count 0 2006.190.08:05:08.59#ibcon#read 3, iclass 3, count 0 2006.190.08:05:08.59#ibcon#about to read 4, iclass 3, count 0 2006.190.08:05:08.59#ibcon#read 4, iclass 3, count 0 2006.190.08:05:08.59#ibcon#about to read 5, iclass 3, count 0 2006.190.08:05:08.59#ibcon#read 5, iclass 3, count 0 2006.190.08:05:08.59#ibcon#about to read 6, iclass 3, count 0 2006.190.08:05:08.59#ibcon#read 6, iclass 3, count 0 2006.190.08:05:08.59#ibcon#end of sib2, iclass 3, count 0 2006.190.08:05:08.59#ibcon#*after write, iclass 3, count 0 2006.190.08:05:08.59#ibcon#*before return 0, iclass 3, count 0 2006.190.08:05:08.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:08.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:08.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:05:08.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:05:08.59$vc4f8/valo=3,672.99 2006.190.08:05:08.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.08:05:08.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.08:05:08.59#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:08.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:08.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:08.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:08.59#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:05:08.59#ibcon#first serial, iclass 5, count 0 2006.190.08:05:08.59#ibcon#enter sib2, iclass 5, count 0 2006.190.08:05:08.59#ibcon#flushed, iclass 5, count 0 2006.190.08:05:08.59#ibcon#about to write, iclass 5, count 0 2006.190.08:05:08.59#ibcon#wrote, iclass 5, count 0 2006.190.08:05:08.59#ibcon#about to read 3, iclass 5, count 0 2006.190.08:05:08.61#ibcon#read 3, iclass 5, count 0 2006.190.08:05:08.61#ibcon#about to read 4, iclass 5, count 0 2006.190.08:05:08.61#ibcon#read 4, iclass 5, count 0 2006.190.08:05:08.61#ibcon#about to read 5, iclass 5, count 0 2006.190.08:05:08.61#ibcon#read 5, iclass 5, count 0 2006.190.08:05:08.61#ibcon#about to read 6, iclass 5, count 0 2006.190.08:05:08.61#ibcon#read 6, iclass 5, count 0 2006.190.08:05:08.61#ibcon#end of sib2, iclass 5, count 0 2006.190.08:05:08.61#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:05:08.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:05:08.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:05:08.61#ibcon#*before write, iclass 5, count 0 2006.190.08:05:08.61#ibcon#enter sib2, iclass 5, count 0 2006.190.08:05:08.61#ibcon#flushed, iclass 5, count 0 2006.190.08:05:08.61#ibcon#about to write, iclass 5, count 0 2006.190.08:05:08.61#ibcon#wrote, iclass 5, count 0 2006.190.08:05:08.61#ibcon#about to read 3, iclass 5, count 0 2006.190.08:05:08.66#ibcon#read 3, iclass 5, count 0 2006.190.08:05:08.66#ibcon#about to read 4, iclass 5, count 0 2006.190.08:05:08.66#ibcon#read 4, iclass 5, count 0 2006.190.08:05:08.66#ibcon#about to read 5, iclass 5, count 0 2006.190.08:05:08.66#ibcon#read 5, iclass 5, count 0 2006.190.08:05:08.66#ibcon#about to read 6, iclass 5, count 0 2006.190.08:05:08.66#ibcon#read 6, iclass 5, count 0 2006.190.08:05:08.66#ibcon#end of sib2, iclass 5, count 0 2006.190.08:05:08.66#ibcon#*after write, iclass 5, count 0 2006.190.08:05:08.66#ibcon#*before return 0, iclass 5, count 0 2006.190.08:05:08.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:08.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:08.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:05:08.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:05:08.66$vc4f8/va=3,6 2006.190.08:05:08.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.08:05:08.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.08:05:08.66#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:08.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:08.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:08.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:08.70#ibcon#enter wrdev, iclass 7, count 2 2006.190.08:05:08.70#ibcon#first serial, iclass 7, count 2 2006.190.08:05:08.70#ibcon#enter sib2, iclass 7, count 2 2006.190.08:05:08.70#ibcon#flushed, iclass 7, count 2 2006.190.08:05:08.70#ibcon#about to write, iclass 7, count 2 2006.190.08:05:08.70#ibcon#wrote, iclass 7, count 2 2006.190.08:05:08.70#ibcon#about to read 3, iclass 7, count 2 2006.190.08:05:08.72#ibcon#read 3, iclass 7, count 2 2006.190.08:05:08.72#ibcon#about to read 4, iclass 7, count 2 2006.190.08:05:08.72#ibcon#read 4, iclass 7, count 2 2006.190.08:05:08.72#ibcon#about to read 5, iclass 7, count 2 2006.190.08:05:08.72#ibcon#read 5, iclass 7, count 2 2006.190.08:05:08.72#ibcon#about to read 6, iclass 7, count 2 2006.190.08:05:08.72#ibcon#read 6, iclass 7, count 2 2006.190.08:05:08.72#ibcon#end of sib2, iclass 7, count 2 2006.190.08:05:08.72#ibcon#*mode == 0, iclass 7, count 2 2006.190.08:05:08.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.08:05:08.72#ibcon#[25=AT03-06\r\n] 2006.190.08:05:08.72#ibcon#*before write, iclass 7, count 2 2006.190.08:05:08.72#ibcon#enter sib2, iclass 7, count 2 2006.190.08:05:08.72#ibcon#flushed, iclass 7, count 2 2006.190.08:05:08.72#ibcon#about to write, iclass 7, count 2 2006.190.08:05:08.72#ibcon#wrote, iclass 7, count 2 2006.190.08:05:08.72#ibcon#about to read 3, iclass 7, count 2 2006.190.08:05:08.75#ibcon#read 3, iclass 7, count 2 2006.190.08:05:08.75#ibcon#about to read 4, iclass 7, count 2 2006.190.08:05:08.75#ibcon#read 4, iclass 7, count 2 2006.190.08:05:08.75#ibcon#about to read 5, iclass 7, count 2 2006.190.08:05:08.75#ibcon#read 5, iclass 7, count 2 2006.190.08:05:08.75#ibcon#about to read 6, iclass 7, count 2 2006.190.08:05:08.75#ibcon#read 6, iclass 7, count 2 2006.190.08:05:08.75#ibcon#end of sib2, iclass 7, count 2 2006.190.08:05:08.75#ibcon#*after write, iclass 7, count 2 2006.190.08:05:08.75#ibcon#*before return 0, iclass 7, count 2 2006.190.08:05:08.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:08.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:08.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.08:05:08.75#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:08.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:08.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:08.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:08.87#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:05:08.87#ibcon#first serial, iclass 7, count 0 2006.190.08:05:08.87#ibcon#enter sib2, iclass 7, count 0 2006.190.08:05:08.87#ibcon#flushed, iclass 7, count 0 2006.190.08:05:08.87#ibcon#about to write, iclass 7, count 0 2006.190.08:05:08.87#ibcon#wrote, iclass 7, count 0 2006.190.08:05:08.87#ibcon#about to read 3, iclass 7, count 0 2006.190.08:05:08.89#ibcon#read 3, iclass 7, count 0 2006.190.08:05:08.89#ibcon#about to read 4, iclass 7, count 0 2006.190.08:05:08.89#ibcon#read 4, iclass 7, count 0 2006.190.08:05:08.89#ibcon#about to read 5, iclass 7, count 0 2006.190.08:05:08.89#ibcon#read 5, iclass 7, count 0 2006.190.08:05:08.89#ibcon#about to read 6, iclass 7, count 0 2006.190.08:05:08.89#ibcon#read 6, iclass 7, count 0 2006.190.08:05:08.89#ibcon#end of sib2, iclass 7, count 0 2006.190.08:05:08.89#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:05:08.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:05:08.89#ibcon#[25=USB\r\n] 2006.190.08:05:08.89#ibcon#*before write, iclass 7, count 0 2006.190.08:05:08.89#ibcon#enter sib2, iclass 7, count 0 2006.190.08:05:08.89#ibcon#flushed, iclass 7, count 0 2006.190.08:05:08.89#ibcon#about to write, iclass 7, count 0 2006.190.08:05:08.89#ibcon#wrote, iclass 7, count 0 2006.190.08:05:08.89#ibcon#about to read 3, iclass 7, count 0 2006.190.08:05:08.92#ibcon#read 3, iclass 7, count 0 2006.190.08:05:08.92#ibcon#about to read 4, iclass 7, count 0 2006.190.08:05:08.92#ibcon#read 4, iclass 7, count 0 2006.190.08:05:08.92#ibcon#about to read 5, iclass 7, count 0 2006.190.08:05:08.92#ibcon#read 5, iclass 7, count 0 2006.190.08:05:08.92#ibcon#about to read 6, iclass 7, count 0 2006.190.08:05:08.92#ibcon#read 6, iclass 7, count 0 2006.190.08:05:08.92#ibcon#end of sib2, iclass 7, count 0 2006.190.08:05:08.92#ibcon#*after write, iclass 7, count 0 2006.190.08:05:08.92#ibcon#*before return 0, iclass 7, count 0 2006.190.08:05:08.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:08.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:08.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:05:08.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:05:08.92$vc4f8/valo=4,832.99 2006.190.08:05:08.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.08:05:08.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.08:05:08.92#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:08.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:08.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:08.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:08.92#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:05:08.92#ibcon#first serial, iclass 11, count 0 2006.190.08:05:08.92#ibcon#enter sib2, iclass 11, count 0 2006.190.08:05:08.92#ibcon#flushed, iclass 11, count 0 2006.190.08:05:08.92#ibcon#about to write, iclass 11, count 0 2006.190.08:05:08.92#ibcon#wrote, iclass 11, count 0 2006.190.08:05:08.92#ibcon#about to read 3, iclass 11, count 0 2006.190.08:05:08.94#ibcon#read 3, iclass 11, count 0 2006.190.08:05:08.94#ibcon#about to read 4, iclass 11, count 0 2006.190.08:05:08.94#ibcon#read 4, iclass 11, count 0 2006.190.08:05:08.94#ibcon#about to read 5, iclass 11, count 0 2006.190.08:05:08.94#ibcon#read 5, iclass 11, count 0 2006.190.08:05:08.94#ibcon#about to read 6, iclass 11, count 0 2006.190.08:05:08.94#ibcon#read 6, iclass 11, count 0 2006.190.08:05:08.94#ibcon#end of sib2, iclass 11, count 0 2006.190.08:05:08.94#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:05:08.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:05:08.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:05:08.94#ibcon#*before write, iclass 11, count 0 2006.190.08:05:08.94#ibcon#enter sib2, iclass 11, count 0 2006.190.08:05:08.94#ibcon#flushed, iclass 11, count 0 2006.190.08:05:08.94#ibcon#about to write, iclass 11, count 0 2006.190.08:05:08.94#ibcon#wrote, iclass 11, count 0 2006.190.08:05:08.94#ibcon#about to read 3, iclass 11, count 0 2006.190.08:05:08.98#ibcon#read 3, iclass 11, count 0 2006.190.08:05:08.98#ibcon#about to read 4, iclass 11, count 0 2006.190.08:05:08.98#ibcon#read 4, iclass 11, count 0 2006.190.08:05:08.98#ibcon#about to read 5, iclass 11, count 0 2006.190.08:05:08.98#ibcon#read 5, iclass 11, count 0 2006.190.08:05:08.98#ibcon#about to read 6, iclass 11, count 0 2006.190.08:05:08.98#ibcon#read 6, iclass 11, count 0 2006.190.08:05:08.98#ibcon#end of sib2, iclass 11, count 0 2006.190.08:05:08.98#ibcon#*after write, iclass 11, count 0 2006.190.08:05:08.98#ibcon#*before return 0, iclass 11, count 0 2006.190.08:05:08.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:08.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:08.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:05:08.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:05:08.98$vc4f8/va=4,7 2006.190.08:05:08.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.08:05:08.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.08:05:08.98#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:08.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:09.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:09.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:09.04#ibcon#enter wrdev, iclass 13, count 2 2006.190.08:05:09.04#ibcon#first serial, iclass 13, count 2 2006.190.08:05:09.04#ibcon#enter sib2, iclass 13, count 2 2006.190.08:05:09.04#ibcon#flushed, iclass 13, count 2 2006.190.08:05:09.04#ibcon#about to write, iclass 13, count 2 2006.190.08:05:09.04#ibcon#wrote, iclass 13, count 2 2006.190.08:05:09.04#ibcon#about to read 3, iclass 13, count 2 2006.190.08:05:09.06#ibcon#read 3, iclass 13, count 2 2006.190.08:05:09.06#ibcon#about to read 4, iclass 13, count 2 2006.190.08:05:09.06#ibcon#read 4, iclass 13, count 2 2006.190.08:05:09.06#ibcon#about to read 5, iclass 13, count 2 2006.190.08:05:09.06#ibcon#read 5, iclass 13, count 2 2006.190.08:05:09.06#ibcon#about to read 6, iclass 13, count 2 2006.190.08:05:09.06#ibcon#read 6, iclass 13, count 2 2006.190.08:05:09.06#ibcon#end of sib2, iclass 13, count 2 2006.190.08:05:09.06#ibcon#*mode == 0, iclass 13, count 2 2006.190.08:05:09.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.08:05:09.06#ibcon#[25=AT04-07\r\n] 2006.190.08:05:09.06#ibcon#*before write, iclass 13, count 2 2006.190.08:05:09.06#ibcon#enter sib2, iclass 13, count 2 2006.190.08:05:09.06#ibcon#flushed, iclass 13, count 2 2006.190.08:05:09.06#ibcon#about to write, iclass 13, count 2 2006.190.08:05:09.06#ibcon#wrote, iclass 13, count 2 2006.190.08:05:09.06#ibcon#about to read 3, iclass 13, count 2 2006.190.08:05:09.09#ibcon#read 3, iclass 13, count 2 2006.190.08:05:09.09#ibcon#about to read 4, iclass 13, count 2 2006.190.08:05:09.09#ibcon#read 4, iclass 13, count 2 2006.190.08:05:09.09#ibcon#about to read 5, iclass 13, count 2 2006.190.08:05:09.09#ibcon#read 5, iclass 13, count 2 2006.190.08:05:09.09#ibcon#about to read 6, iclass 13, count 2 2006.190.08:05:09.09#ibcon#read 6, iclass 13, count 2 2006.190.08:05:09.09#ibcon#end of sib2, iclass 13, count 2 2006.190.08:05:09.09#ibcon#*after write, iclass 13, count 2 2006.190.08:05:09.09#ibcon#*before return 0, iclass 13, count 2 2006.190.08:05:09.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:09.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:09.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.08:05:09.09#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:09.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:09.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:09.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:09.21#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:05:09.21#ibcon#first serial, iclass 13, count 0 2006.190.08:05:09.21#ibcon#enter sib2, iclass 13, count 0 2006.190.08:05:09.21#ibcon#flushed, iclass 13, count 0 2006.190.08:05:09.21#ibcon#about to write, iclass 13, count 0 2006.190.08:05:09.21#ibcon#wrote, iclass 13, count 0 2006.190.08:05:09.21#ibcon#about to read 3, iclass 13, count 0 2006.190.08:05:09.23#ibcon#read 3, iclass 13, count 0 2006.190.08:05:09.23#ibcon#about to read 4, iclass 13, count 0 2006.190.08:05:09.23#ibcon#read 4, iclass 13, count 0 2006.190.08:05:09.23#ibcon#about to read 5, iclass 13, count 0 2006.190.08:05:09.23#ibcon#read 5, iclass 13, count 0 2006.190.08:05:09.23#ibcon#about to read 6, iclass 13, count 0 2006.190.08:05:09.23#ibcon#read 6, iclass 13, count 0 2006.190.08:05:09.23#ibcon#end of sib2, iclass 13, count 0 2006.190.08:05:09.23#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:05:09.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:05:09.23#ibcon#[25=USB\r\n] 2006.190.08:05:09.23#ibcon#*before write, iclass 13, count 0 2006.190.08:05:09.23#ibcon#enter sib2, iclass 13, count 0 2006.190.08:05:09.23#ibcon#flushed, iclass 13, count 0 2006.190.08:05:09.23#ibcon#about to write, iclass 13, count 0 2006.190.08:05:09.23#ibcon#wrote, iclass 13, count 0 2006.190.08:05:09.23#ibcon#about to read 3, iclass 13, count 0 2006.190.08:05:09.26#ibcon#read 3, iclass 13, count 0 2006.190.08:05:09.26#ibcon#about to read 4, iclass 13, count 0 2006.190.08:05:09.26#ibcon#read 4, iclass 13, count 0 2006.190.08:05:09.26#ibcon#about to read 5, iclass 13, count 0 2006.190.08:05:09.26#ibcon#read 5, iclass 13, count 0 2006.190.08:05:09.26#ibcon#about to read 6, iclass 13, count 0 2006.190.08:05:09.26#ibcon#read 6, iclass 13, count 0 2006.190.08:05:09.26#ibcon#end of sib2, iclass 13, count 0 2006.190.08:05:09.26#ibcon#*after write, iclass 13, count 0 2006.190.08:05:09.26#ibcon#*before return 0, iclass 13, count 0 2006.190.08:05:09.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:09.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:09.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:05:09.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:05:09.26$vc4f8/valo=5,652.99 2006.190.08:05:09.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.08:05:09.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.08:05:09.26#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:09.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:09.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:09.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:09.26#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:05:09.26#ibcon#first serial, iclass 15, count 0 2006.190.08:05:09.26#ibcon#enter sib2, iclass 15, count 0 2006.190.08:05:09.26#ibcon#flushed, iclass 15, count 0 2006.190.08:05:09.26#ibcon#about to write, iclass 15, count 0 2006.190.08:05:09.26#ibcon#wrote, iclass 15, count 0 2006.190.08:05:09.26#ibcon#about to read 3, iclass 15, count 0 2006.190.08:05:09.28#ibcon#read 3, iclass 15, count 0 2006.190.08:05:09.28#ibcon#about to read 4, iclass 15, count 0 2006.190.08:05:09.28#ibcon#read 4, iclass 15, count 0 2006.190.08:05:09.28#ibcon#about to read 5, iclass 15, count 0 2006.190.08:05:09.28#ibcon#read 5, iclass 15, count 0 2006.190.08:05:09.28#ibcon#about to read 6, iclass 15, count 0 2006.190.08:05:09.28#ibcon#read 6, iclass 15, count 0 2006.190.08:05:09.28#ibcon#end of sib2, iclass 15, count 0 2006.190.08:05:09.28#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:05:09.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:05:09.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:05:09.28#ibcon#*before write, iclass 15, count 0 2006.190.08:05:09.28#ibcon#enter sib2, iclass 15, count 0 2006.190.08:05:09.28#ibcon#flushed, iclass 15, count 0 2006.190.08:05:09.28#ibcon#about to write, iclass 15, count 0 2006.190.08:05:09.28#ibcon#wrote, iclass 15, count 0 2006.190.08:05:09.28#ibcon#about to read 3, iclass 15, count 0 2006.190.08:05:09.32#ibcon#read 3, iclass 15, count 0 2006.190.08:05:09.32#ibcon#about to read 4, iclass 15, count 0 2006.190.08:05:09.32#ibcon#read 4, iclass 15, count 0 2006.190.08:05:09.32#ibcon#about to read 5, iclass 15, count 0 2006.190.08:05:09.32#ibcon#read 5, iclass 15, count 0 2006.190.08:05:09.32#ibcon#about to read 6, iclass 15, count 0 2006.190.08:05:09.32#ibcon#read 6, iclass 15, count 0 2006.190.08:05:09.32#ibcon#end of sib2, iclass 15, count 0 2006.190.08:05:09.32#ibcon#*after write, iclass 15, count 0 2006.190.08:05:09.32#ibcon#*before return 0, iclass 15, count 0 2006.190.08:05:09.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:09.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:09.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:05:09.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:05:09.32$vc4f8/va=5,7 2006.190.08:05:09.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.08:05:09.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.08:05:09.32#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:09.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:09.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:09.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:09.38#ibcon#enter wrdev, iclass 17, count 2 2006.190.08:05:09.38#ibcon#first serial, iclass 17, count 2 2006.190.08:05:09.38#ibcon#enter sib2, iclass 17, count 2 2006.190.08:05:09.38#ibcon#flushed, iclass 17, count 2 2006.190.08:05:09.38#ibcon#about to write, iclass 17, count 2 2006.190.08:05:09.38#ibcon#wrote, iclass 17, count 2 2006.190.08:05:09.38#ibcon#about to read 3, iclass 17, count 2 2006.190.08:05:09.40#ibcon#read 3, iclass 17, count 2 2006.190.08:05:09.40#ibcon#about to read 4, iclass 17, count 2 2006.190.08:05:09.40#ibcon#read 4, iclass 17, count 2 2006.190.08:05:09.40#ibcon#about to read 5, iclass 17, count 2 2006.190.08:05:09.40#ibcon#read 5, iclass 17, count 2 2006.190.08:05:09.40#ibcon#about to read 6, iclass 17, count 2 2006.190.08:05:09.40#ibcon#read 6, iclass 17, count 2 2006.190.08:05:09.40#ibcon#end of sib2, iclass 17, count 2 2006.190.08:05:09.40#ibcon#*mode == 0, iclass 17, count 2 2006.190.08:05:09.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.08:05:09.40#ibcon#[25=AT05-07\r\n] 2006.190.08:05:09.40#ibcon#*before write, iclass 17, count 2 2006.190.08:05:09.40#ibcon#enter sib2, iclass 17, count 2 2006.190.08:05:09.40#ibcon#flushed, iclass 17, count 2 2006.190.08:05:09.40#ibcon#about to write, iclass 17, count 2 2006.190.08:05:09.40#ibcon#wrote, iclass 17, count 2 2006.190.08:05:09.40#ibcon#about to read 3, iclass 17, count 2 2006.190.08:05:09.43#ibcon#read 3, iclass 17, count 2 2006.190.08:05:09.43#ibcon#about to read 4, iclass 17, count 2 2006.190.08:05:09.43#ibcon#read 4, iclass 17, count 2 2006.190.08:05:09.43#ibcon#about to read 5, iclass 17, count 2 2006.190.08:05:09.43#ibcon#read 5, iclass 17, count 2 2006.190.08:05:09.43#ibcon#about to read 6, iclass 17, count 2 2006.190.08:05:09.43#ibcon#read 6, iclass 17, count 2 2006.190.08:05:09.43#ibcon#end of sib2, iclass 17, count 2 2006.190.08:05:09.43#ibcon#*after write, iclass 17, count 2 2006.190.08:05:09.43#ibcon#*before return 0, iclass 17, count 2 2006.190.08:05:09.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:09.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:09.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.08:05:09.43#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:09.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:09.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:09.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:09.55#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:05:09.55#ibcon#first serial, iclass 17, count 0 2006.190.08:05:09.55#ibcon#enter sib2, iclass 17, count 0 2006.190.08:05:09.55#ibcon#flushed, iclass 17, count 0 2006.190.08:05:09.55#ibcon#about to write, iclass 17, count 0 2006.190.08:05:09.55#ibcon#wrote, iclass 17, count 0 2006.190.08:05:09.55#ibcon#about to read 3, iclass 17, count 0 2006.190.08:05:09.57#ibcon#read 3, iclass 17, count 0 2006.190.08:05:09.57#ibcon#about to read 4, iclass 17, count 0 2006.190.08:05:09.57#ibcon#read 4, iclass 17, count 0 2006.190.08:05:09.57#ibcon#about to read 5, iclass 17, count 0 2006.190.08:05:09.57#ibcon#read 5, iclass 17, count 0 2006.190.08:05:09.57#ibcon#about to read 6, iclass 17, count 0 2006.190.08:05:09.57#ibcon#read 6, iclass 17, count 0 2006.190.08:05:09.57#ibcon#end of sib2, iclass 17, count 0 2006.190.08:05:09.57#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:05:09.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:05:09.57#ibcon#[25=USB\r\n] 2006.190.08:05:09.57#ibcon#*before write, iclass 17, count 0 2006.190.08:05:09.57#ibcon#enter sib2, iclass 17, count 0 2006.190.08:05:09.57#ibcon#flushed, iclass 17, count 0 2006.190.08:05:09.57#ibcon#about to write, iclass 17, count 0 2006.190.08:05:09.57#ibcon#wrote, iclass 17, count 0 2006.190.08:05:09.57#ibcon#about to read 3, iclass 17, count 0 2006.190.08:05:09.60#ibcon#read 3, iclass 17, count 0 2006.190.08:05:09.60#ibcon#about to read 4, iclass 17, count 0 2006.190.08:05:09.60#ibcon#read 4, iclass 17, count 0 2006.190.08:05:09.60#ibcon#about to read 5, iclass 17, count 0 2006.190.08:05:09.60#ibcon#read 5, iclass 17, count 0 2006.190.08:05:09.60#ibcon#about to read 6, iclass 17, count 0 2006.190.08:05:09.60#ibcon#read 6, iclass 17, count 0 2006.190.08:05:09.60#ibcon#end of sib2, iclass 17, count 0 2006.190.08:05:09.60#ibcon#*after write, iclass 17, count 0 2006.190.08:05:09.60#ibcon#*before return 0, iclass 17, count 0 2006.190.08:05:09.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:09.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:09.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:05:09.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:05:09.60$vc4f8/valo=6,772.99 2006.190.08:05:09.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.08:05:09.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.08:05:09.60#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:09.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:09.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:09.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:09.60#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:05:09.60#ibcon#first serial, iclass 19, count 0 2006.190.08:05:09.60#ibcon#enter sib2, iclass 19, count 0 2006.190.08:05:09.60#ibcon#flushed, iclass 19, count 0 2006.190.08:05:09.60#ibcon#about to write, iclass 19, count 0 2006.190.08:05:09.60#ibcon#wrote, iclass 19, count 0 2006.190.08:05:09.60#ibcon#about to read 3, iclass 19, count 0 2006.190.08:05:09.62#ibcon#read 3, iclass 19, count 0 2006.190.08:05:09.62#ibcon#about to read 4, iclass 19, count 0 2006.190.08:05:09.62#ibcon#read 4, iclass 19, count 0 2006.190.08:05:09.62#ibcon#about to read 5, iclass 19, count 0 2006.190.08:05:09.62#ibcon#read 5, iclass 19, count 0 2006.190.08:05:09.62#ibcon#about to read 6, iclass 19, count 0 2006.190.08:05:09.62#ibcon#read 6, iclass 19, count 0 2006.190.08:05:09.62#ibcon#end of sib2, iclass 19, count 0 2006.190.08:05:09.62#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:05:09.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:05:09.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:05:09.62#ibcon#*before write, iclass 19, count 0 2006.190.08:05:09.62#ibcon#enter sib2, iclass 19, count 0 2006.190.08:05:09.62#ibcon#flushed, iclass 19, count 0 2006.190.08:05:09.62#ibcon#about to write, iclass 19, count 0 2006.190.08:05:09.62#ibcon#wrote, iclass 19, count 0 2006.190.08:05:09.62#ibcon#about to read 3, iclass 19, count 0 2006.190.08:05:09.66#ibcon#read 3, iclass 19, count 0 2006.190.08:05:09.66#ibcon#about to read 4, iclass 19, count 0 2006.190.08:05:09.66#ibcon#read 4, iclass 19, count 0 2006.190.08:05:09.66#ibcon#about to read 5, iclass 19, count 0 2006.190.08:05:09.66#ibcon#read 5, iclass 19, count 0 2006.190.08:05:09.66#ibcon#about to read 6, iclass 19, count 0 2006.190.08:05:09.66#ibcon#read 6, iclass 19, count 0 2006.190.08:05:09.66#ibcon#end of sib2, iclass 19, count 0 2006.190.08:05:09.66#ibcon#*after write, iclass 19, count 0 2006.190.08:05:09.66#ibcon#*before return 0, iclass 19, count 0 2006.190.08:05:09.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:09.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:09.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:05:09.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:05:09.66$vc4f8/va=6,6 2006.190.08:05:09.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.08:05:09.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.08:05:09.66#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:09.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:05:09.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:05:09.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:05:09.72#ibcon#enter wrdev, iclass 21, count 2 2006.190.08:05:09.72#ibcon#first serial, iclass 21, count 2 2006.190.08:05:09.72#ibcon#enter sib2, iclass 21, count 2 2006.190.08:05:09.72#ibcon#flushed, iclass 21, count 2 2006.190.08:05:09.72#ibcon#about to write, iclass 21, count 2 2006.190.08:05:09.72#ibcon#wrote, iclass 21, count 2 2006.190.08:05:09.72#ibcon#about to read 3, iclass 21, count 2 2006.190.08:05:09.74#ibcon#read 3, iclass 21, count 2 2006.190.08:05:09.74#ibcon#about to read 4, iclass 21, count 2 2006.190.08:05:09.74#ibcon#read 4, iclass 21, count 2 2006.190.08:05:09.74#ibcon#about to read 5, iclass 21, count 2 2006.190.08:05:09.74#ibcon#read 5, iclass 21, count 2 2006.190.08:05:09.74#ibcon#about to read 6, iclass 21, count 2 2006.190.08:05:09.74#ibcon#read 6, iclass 21, count 2 2006.190.08:05:09.74#ibcon#end of sib2, iclass 21, count 2 2006.190.08:05:09.74#ibcon#*mode == 0, iclass 21, count 2 2006.190.08:05:09.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.08:05:09.74#ibcon#[25=AT06-06\r\n] 2006.190.08:05:09.74#ibcon#*before write, iclass 21, count 2 2006.190.08:05:09.74#ibcon#enter sib2, iclass 21, count 2 2006.190.08:05:09.74#ibcon#flushed, iclass 21, count 2 2006.190.08:05:09.74#ibcon#about to write, iclass 21, count 2 2006.190.08:05:09.74#ibcon#wrote, iclass 21, count 2 2006.190.08:05:09.74#ibcon#about to read 3, iclass 21, count 2 2006.190.08:05:09.77#ibcon#read 3, iclass 21, count 2 2006.190.08:05:09.77#ibcon#about to read 4, iclass 21, count 2 2006.190.08:05:09.77#ibcon#read 4, iclass 21, count 2 2006.190.08:05:09.77#ibcon#about to read 5, iclass 21, count 2 2006.190.08:05:09.77#ibcon#read 5, iclass 21, count 2 2006.190.08:05:09.77#ibcon#about to read 6, iclass 21, count 2 2006.190.08:05:09.77#ibcon#read 6, iclass 21, count 2 2006.190.08:05:09.77#ibcon#end of sib2, iclass 21, count 2 2006.190.08:05:09.77#ibcon#*after write, iclass 21, count 2 2006.190.08:05:09.77#ibcon#*before return 0, iclass 21, count 2 2006.190.08:05:09.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:05:09.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:05:09.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.08:05:09.77#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:09.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:05:09.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:05:09.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:05:09.89#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:05:09.89#ibcon#first serial, iclass 21, count 0 2006.190.08:05:09.89#ibcon#enter sib2, iclass 21, count 0 2006.190.08:05:09.89#ibcon#flushed, iclass 21, count 0 2006.190.08:05:09.89#ibcon#about to write, iclass 21, count 0 2006.190.08:05:09.89#ibcon#wrote, iclass 21, count 0 2006.190.08:05:09.89#ibcon#about to read 3, iclass 21, count 0 2006.190.08:05:09.91#ibcon#read 3, iclass 21, count 0 2006.190.08:05:09.91#ibcon#about to read 4, iclass 21, count 0 2006.190.08:05:09.91#ibcon#read 4, iclass 21, count 0 2006.190.08:05:09.91#ibcon#about to read 5, iclass 21, count 0 2006.190.08:05:09.91#ibcon#read 5, iclass 21, count 0 2006.190.08:05:09.91#ibcon#about to read 6, iclass 21, count 0 2006.190.08:05:09.91#ibcon#read 6, iclass 21, count 0 2006.190.08:05:09.91#ibcon#end of sib2, iclass 21, count 0 2006.190.08:05:09.91#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:05:09.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:05:09.91#ibcon#[25=USB\r\n] 2006.190.08:05:09.91#ibcon#*before write, iclass 21, count 0 2006.190.08:05:09.91#ibcon#enter sib2, iclass 21, count 0 2006.190.08:05:09.91#ibcon#flushed, iclass 21, count 0 2006.190.08:05:09.91#ibcon#about to write, iclass 21, count 0 2006.190.08:05:09.91#ibcon#wrote, iclass 21, count 0 2006.190.08:05:09.91#ibcon#about to read 3, iclass 21, count 0 2006.190.08:05:09.94#ibcon#read 3, iclass 21, count 0 2006.190.08:05:09.94#ibcon#about to read 4, iclass 21, count 0 2006.190.08:05:09.94#ibcon#read 4, iclass 21, count 0 2006.190.08:05:09.94#ibcon#about to read 5, iclass 21, count 0 2006.190.08:05:09.94#ibcon#read 5, iclass 21, count 0 2006.190.08:05:09.94#ibcon#about to read 6, iclass 21, count 0 2006.190.08:05:09.94#ibcon#read 6, iclass 21, count 0 2006.190.08:05:09.94#ibcon#end of sib2, iclass 21, count 0 2006.190.08:05:09.94#ibcon#*after write, iclass 21, count 0 2006.190.08:05:09.94#ibcon#*before return 0, iclass 21, count 0 2006.190.08:05:09.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:05:09.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:05:09.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:05:09.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:05:09.94$vc4f8/valo=7,832.99 2006.190.08:05:09.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.08:05:09.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.08:05:09.94#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:09.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:05:09.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:05:09.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:05:09.94#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:05:09.94#ibcon#first serial, iclass 23, count 0 2006.190.08:05:09.94#ibcon#enter sib2, iclass 23, count 0 2006.190.08:05:09.94#ibcon#flushed, iclass 23, count 0 2006.190.08:05:09.94#ibcon#about to write, iclass 23, count 0 2006.190.08:05:09.94#ibcon#wrote, iclass 23, count 0 2006.190.08:05:09.94#ibcon#about to read 3, iclass 23, count 0 2006.190.08:05:09.96#ibcon#read 3, iclass 23, count 0 2006.190.08:05:09.96#ibcon#about to read 4, iclass 23, count 0 2006.190.08:05:09.96#ibcon#read 4, iclass 23, count 0 2006.190.08:05:09.96#ibcon#about to read 5, iclass 23, count 0 2006.190.08:05:09.96#ibcon#read 5, iclass 23, count 0 2006.190.08:05:09.96#ibcon#about to read 6, iclass 23, count 0 2006.190.08:05:09.96#ibcon#read 6, iclass 23, count 0 2006.190.08:05:09.96#ibcon#end of sib2, iclass 23, count 0 2006.190.08:05:09.96#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:05:09.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:05:09.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:05:09.96#ibcon#*before write, iclass 23, count 0 2006.190.08:05:09.96#ibcon#enter sib2, iclass 23, count 0 2006.190.08:05:09.96#ibcon#flushed, iclass 23, count 0 2006.190.08:05:09.96#ibcon#about to write, iclass 23, count 0 2006.190.08:05:09.96#ibcon#wrote, iclass 23, count 0 2006.190.08:05:09.96#ibcon#about to read 3, iclass 23, count 0 2006.190.08:05:10.00#ibcon#read 3, iclass 23, count 0 2006.190.08:05:10.00#ibcon#about to read 4, iclass 23, count 0 2006.190.08:05:10.00#ibcon#read 4, iclass 23, count 0 2006.190.08:05:10.00#ibcon#about to read 5, iclass 23, count 0 2006.190.08:05:10.00#ibcon#read 5, iclass 23, count 0 2006.190.08:05:10.00#ibcon#about to read 6, iclass 23, count 0 2006.190.08:05:10.00#ibcon#read 6, iclass 23, count 0 2006.190.08:05:10.00#ibcon#end of sib2, iclass 23, count 0 2006.190.08:05:10.00#ibcon#*after write, iclass 23, count 0 2006.190.08:05:10.00#ibcon#*before return 0, iclass 23, count 0 2006.190.08:05:10.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:05:10.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:05:10.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:05:10.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:05:10.00$vc4f8/va=7,6 2006.190.08:05:10.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.08:05:10.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.08:05:10.00#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:10.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:05:10.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:05:10.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:05:10.06#ibcon#enter wrdev, iclass 25, count 2 2006.190.08:05:10.06#ibcon#first serial, iclass 25, count 2 2006.190.08:05:10.06#ibcon#enter sib2, iclass 25, count 2 2006.190.08:05:10.06#ibcon#flushed, iclass 25, count 2 2006.190.08:05:10.06#ibcon#about to write, iclass 25, count 2 2006.190.08:05:10.06#ibcon#wrote, iclass 25, count 2 2006.190.08:05:10.06#ibcon#about to read 3, iclass 25, count 2 2006.190.08:05:10.08#ibcon#read 3, iclass 25, count 2 2006.190.08:05:10.08#ibcon#about to read 4, iclass 25, count 2 2006.190.08:05:10.08#ibcon#read 4, iclass 25, count 2 2006.190.08:05:10.08#ibcon#about to read 5, iclass 25, count 2 2006.190.08:05:10.08#ibcon#read 5, iclass 25, count 2 2006.190.08:05:10.08#ibcon#about to read 6, iclass 25, count 2 2006.190.08:05:10.08#ibcon#read 6, iclass 25, count 2 2006.190.08:05:10.08#ibcon#end of sib2, iclass 25, count 2 2006.190.08:05:10.08#ibcon#*mode == 0, iclass 25, count 2 2006.190.08:05:10.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.08:05:10.08#ibcon#[25=AT07-06\r\n] 2006.190.08:05:10.08#ibcon#*before write, iclass 25, count 2 2006.190.08:05:10.08#ibcon#enter sib2, iclass 25, count 2 2006.190.08:05:10.08#ibcon#flushed, iclass 25, count 2 2006.190.08:05:10.08#ibcon#about to write, iclass 25, count 2 2006.190.08:05:10.08#ibcon#wrote, iclass 25, count 2 2006.190.08:05:10.08#ibcon#about to read 3, iclass 25, count 2 2006.190.08:05:10.11#ibcon#read 3, iclass 25, count 2 2006.190.08:05:10.11#ibcon#about to read 4, iclass 25, count 2 2006.190.08:05:10.11#ibcon#read 4, iclass 25, count 2 2006.190.08:05:10.11#ibcon#about to read 5, iclass 25, count 2 2006.190.08:05:10.11#ibcon#read 5, iclass 25, count 2 2006.190.08:05:10.11#ibcon#about to read 6, iclass 25, count 2 2006.190.08:05:10.11#ibcon#read 6, iclass 25, count 2 2006.190.08:05:10.11#ibcon#end of sib2, iclass 25, count 2 2006.190.08:05:10.11#ibcon#*after write, iclass 25, count 2 2006.190.08:05:10.11#ibcon#*before return 0, iclass 25, count 2 2006.190.08:05:10.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:05:10.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:05:10.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.08:05:10.11#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:10.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:05:10.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:05:10.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:05:10.23#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:05:10.23#ibcon#first serial, iclass 25, count 0 2006.190.08:05:10.23#ibcon#enter sib2, iclass 25, count 0 2006.190.08:05:10.23#ibcon#flushed, iclass 25, count 0 2006.190.08:05:10.23#ibcon#about to write, iclass 25, count 0 2006.190.08:05:10.23#ibcon#wrote, iclass 25, count 0 2006.190.08:05:10.23#ibcon#about to read 3, iclass 25, count 0 2006.190.08:05:10.25#ibcon#read 3, iclass 25, count 0 2006.190.08:05:10.25#ibcon#about to read 4, iclass 25, count 0 2006.190.08:05:10.25#ibcon#read 4, iclass 25, count 0 2006.190.08:05:10.25#ibcon#about to read 5, iclass 25, count 0 2006.190.08:05:10.25#ibcon#read 5, iclass 25, count 0 2006.190.08:05:10.25#ibcon#about to read 6, iclass 25, count 0 2006.190.08:05:10.25#ibcon#read 6, iclass 25, count 0 2006.190.08:05:10.25#ibcon#end of sib2, iclass 25, count 0 2006.190.08:05:10.25#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:05:10.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:05:10.25#ibcon#[25=USB\r\n] 2006.190.08:05:10.25#ibcon#*before write, iclass 25, count 0 2006.190.08:05:10.25#ibcon#enter sib2, iclass 25, count 0 2006.190.08:05:10.25#ibcon#flushed, iclass 25, count 0 2006.190.08:05:10.25#ibcon#about to write, iclass 25, count 0 2006.190.08:05:10.25#ibcon#wrote, iclass 25, count 0 2006.190.08:05:10.25#ibcon#about to read 3, iclass 25, count 0 2006.190.08:05:10.28#ibcon#read 3, iclass 25, count 0 2006.190.08:05:10.28#ibcon#about to read 4, iclass 25, count 0 2006.190.08:05:10.28#ibcon#read 4, iclass 25, count 0 2006.190.08:05:10.28#ibcon#about to read 5, iclass 25, count 0 2006.190.08:05:10.28#ibcon#read 5, iclass 25, count 0 2006.190.08:05:10.28#ibcon#about to read 6, iclass 25, count 0 2006.190.08:05:10.28#ibcon#read 6, iclass 25, count 0 2006.190.08:05:10.28#ibcon#end of sib2, iclass 25, count 0 2006.190.08:05:10.28#ibcon#*after write, iclass 25, count 0 2006.190.08:05:10.28#ibcon#*before return 0, iclass 25, count 0 2006.190.08:05:10.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:05:10.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:05:10.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:05:10.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:05:10.28$vc4f8/valo=8,852.99 2006.190.08:05:10.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.08:05:10.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.08:05:10.28#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:10.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:05:10.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:05:10.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:05:10.28#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:05:10.28#ibcon#first serial, iclass 27, count 0 2006.190.08:05:10.28#ibcon#enter sib2, iclass 27, count 0 2006.190.08:05:10.28#ibcon#flushed, iclass 27, count 0 2006.190.08:05:10.28#ibcon#about to write, iclass 27, count 0 2006.190.08:05:10.28#ibcon#wrote, iclass 27, count 0 2006.190.08:05:10.28#ibcon#about to read 3, iclass 27, count 0 2006.190.08:05:10.30#ibcon#read 3, iclass 27, count 0 2006.190.08:05:10.30#ibcon#about to read 4, iclass 27, count 0 2006.190.08:05:10.30#ibcon#read 4, iclass 27, count 0 2006.190.08:05:10.30#ibcon#about to read 5, iclass 27, count 0 2006.190.08:05:10.30#ibcon#read 5, iclass 27, count 0 2006.190.08:05:10.30#ibcon#about to read 6, iclass 27, count 0 2006.190.08:05:10.30#ibcon#read 6, iclass 27, count 0 2006.190.08:05:10.30#ibcon#end of sib2, iclass 27, count 0 2006.190.08:05:10.30#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:05:10.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:05:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:05:10.30#ibcon#*before write, iclass 27, count 0 2006.190.08:05:10.30#ibcon#enter sib2, iclass 27, count 0 2006.190.08:05:10.30#ibcon#flushed, iclass 27, count 0 2006.190.08:05:10.30#ibcon#about to write, iclass 27, count 0 2006.190.08:05:10.30#ibcon#wrote, iclass 27, count 0 2006.190.08:05:10.30#ibcon#about to read 3, iclass 27, count 0 2006.190.08:05:10.34#ibcon#read 3, iclass 27, count 0 2006.190.08:05:10.34#ibcon#about to read 4, iclass 27, count 0 2006.190.08:05:10.34#ibcon#read 4, iclass 27, count 0 2006.190.08:05:10.34#ibcon#about to read 5, iclass 27, count 0 2006.190.08:05:10.34#ibcon#read 5, iclass 27, count 0 2006.190.08:05:10.34#ibcon#about to read 6, iclass 27, count 0 2006.190.08:05:10.34#ibcon#read 6, iclass 27, count 0 2006.190.08:05:10.34#ibcon#end of sib2, iclass 27, count 0 2006.190.08:05:10.34#ibcon#*after write, iclass 27, count 0 2006.190.08:05:10.34#ibcon#*before return 0, iclass 27, count 0 2006.190.08:05:10.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:05:10.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:05:10.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:05:10.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:05:10.34$vc4f8/va=8,6 2006.190.08:05:10.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.08:05:10.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.08:05:10.34#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:10.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:05:10.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:05:10.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:05:10.41#ibcon#enter wrdev, iclass 29, count 2 2006.190.08:05:10.41#ibcon#first serial, iclass 29, count 2 2006.190.08:05:10.41#ibcon#enter sib2, iclass 29, count 2 2006.190.08:05:10.41#ibcon#flushed, iclass 29, count 2 2006.190.08:05:10.41#ibcon#about to write, iclass 29, count 2 2006.190.08:05:10.41#ibcon#wrote, iclass 29, count 2 2006.190.08:05:10.41#ibcon#about to read 3, iclass 29, count 2 2006.190.08:05:10.42#ibcon#read 3, iclass 29, count 2 2006.190.08:05:10.42#ibcon#about to read 4, iclass 29, count 2 2006.190.08:05:10.42#ibcon#read 4, iclass 29, count 2 2006.190.08:05:10.42#ibcon#about to read 5, iclass 29, count 2 2006.190.08:05:10.42#ibcon#read 5, iclass 29, count 2 2006.190.08:05:10.42#ibcon#about to read 6, iclass 29, count 2 2006.190.08:05:10.42#ibcon#read 6, iclass 29, count 2 2006.190.08:05:10.42#ibcon#end of sib2, iclass 29, count 2 2006.190.08:05:10.42#ibcon#*mode == 0, iclass 29, count 2 2006.190.08:05:10.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.08:05:10.42#ibcon#[25=AT08-06\r\n] 2006.190.08:05:10.42#ibcon#*before write, iclass 29, count 2 2006.190.08:05:10.42#ibcon#enter sib2, iclass 29, count 2 2006.190.08:05:10.42#ibcon#flushed, iclass 29, count 2 2006.190.08:05:10.42#ibcon#about to write, iclass 29, count 2 2006.190.08:05:10.42#ibcon#wrote, iclass 29, count 2 2006.190.08:05:10.42#ibcon#about to read 3, iclass 29, count 2 2006.190.08:05:10.45#ibcon#read 3, iclass 29, count 2 2006.190.08:05:10.45#ibcon#about to read 4, iclass 29, count 2 2006.190.08:05:10.45#ibcon#read 4, iclass 29, count 2 2006.190.08:05:10.45#ibcon#about to read 5, iclass 29, count 2 2006.190.08:05:10.45#ibcon#read 5, iclass 29, count 2 2006.190.08:05:10.45#ibcon#about to read 6, iclass 29, count 2 2006.190.08:05:10.45#ibcon#read 6, iclass 29, count 2 2006.190.08:05:10.45#ibcon#end of sib2, iclass 29, count 2 2006.190.08:05:10.45#ibcon#*after write, iclass 29, count 2 2006.190.08:05:10.45#ibcon#*before return 0, iclass 29, count 2 2006.190.08:05:10.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:05:10.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:05:10.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.08:05:10.45#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:10.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:05:10.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:05:10.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:05:10.57#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:05:10.57#ibcon#first serial, iclass 29, count 0 2006.190.08:05:10.57#ibcon#enter sib2, iclass 29, count 0 2006.190.08:05:10.57#ibcon#flushed, iclass 29, count 0 2006.190.08:05:10.57#ibcon#about to write, iclass 29, count 0 2006.190.08:05:10.57#ibcon#wrote, iclass 29, count 0 2006.190.08:05:10.57#ibcon#about to read 3, iclass 29, count 0 2006.190.08:05:10.59#ibcon#read 3, iclass 29, count 0 2006.190.08:05:10.59#ibcon#about to read 4, iclass 29, count 0 2006.190.08:05:10.59#ibcon#read 4, iclass 29, count 0 2006.190.08:05:10.59#ibcon#about to read 5, iclass 29, count 0 2006.190.08:05:10.59#ibcon#read 5, iclass 29, count 0 2006.190.08:05:10.59#ibcon#about to read 6, iclass 29, count 0 2006.190.08:05:10.59#ibcon#read 6, iclass 29, count 0 2006.190.08:05:10.59#ibcon#end of sib2, iclass 29, count 0 2006.190.08:05:10.59#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:05:10.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:05:10.59#ibcon#[25=USB\r\n] 2006.190.08:05:10.59#ibcon#*before write, iclass 29, count 0 2006.190.08:05:10.59#ibcon#enter sib2, iclass 29, count 0 2006.190.08:05:10.59#ibcon#flushed, iclass 29, count 0 2006.190.08:05:10.59#ibcon#about to write, iclass 29, count 0 2006.190.08:05:10.59#ibcon#wrote, iclass 29, count 0 2006.190.08:05:10.59#ibcon#about to read 3, iclass 29, count 0 2006.190.08:05:10.62#ibcon#read 3, iclass 29, count 0 2006.190.08:05:10.62#ibcon#about to read 4, iclass 29, count 0 2006.190.08:05:10.62#ibcon#read 4, iclass 29, count 0 2006.190.08:05:10.62#ibcon#about to read 5, iclass 29, count 0 2006.190.08:05:10.62#ibcon#read 5, iclass 29, count 0 2006.190.08:05:10.62#ibcon#about to read 6, iclass 29, count 0 2006.190.08:05:10.62#ibcon#read 6, iclass 29, count 0 2006.190.08:05:10.62#ibcon#end of sib2, iclass 29, count 0 2006.190.08:05:10.62#ibcon#*after write, iclass 29, count 0 2006.190.08:05:10.62#ibcon#*before return 0, iclass 29, count 0 2006.190.08:05:10.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:05:10.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:05:10.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:05:10.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:05:10.62$vc4f8/vblo=1,632.99 2006.190.08:05:10.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.08:05:10.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.08:05:10.62#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:10.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:05:10.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:05:10.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:05:10.62#ibcon#enter wrdev, iclass 31, count 0 2006.190.08:05:10.62#ibcon#first serial, iclass 31, count 0 2006.190.08:05:10.62#ibcon#enter sib2, iclass 31, count 0 2006.190.08:05:10.62#ibcon#flushed, iclass 31, count 0 2006.190.08:05:10.62#ibcon#about to write, iclass 31, count 0 2006.190.08:05:10.62#ibcon#wrote, iclass 31, count 0 2006.190.08:05:10.62#ibcon#about to read 3, iclass 31, count 0 2006.190.08:05:10.64#ibcon#read 3, iclass 31, count 0 2006.190.08:05:10.64#ibcon#about to read 4, iclass 31, count 0 2006.190.08:05:10.64#ibcon#read 4, iclass 31, count 0 2006.190.08:05:10.64#ibcon#about to read 5, iclass 31, count 0 2006.190.08:05:10.64#ibcon#read 5, iclass 31, count 0 2006.190.08:05:10.64#ibcon#about to read 6, iclass 31, count 0 2006.190.08:05:10.64#ibcon#read 6, iclass 31, count 0 2006.190.08:05:10.64#ibcon#end of sib2, iclass 31, count 0 2006.190.08:05:10.64#ibcon#*mode == 0, iclass 31, count 0 2006.190.08:05:10.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.08:05:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:05:10.64#ibcon#*before write, iclass 31, count 0 2006.190.08:05:10.64#ibcon#enter sib2, iclass 31, count 0 2006.190.08:05:10.64#ibcon#flushed, iclass 31, count 0 2006.190.08:05:10.64#ibcon#about to write, iclass 31, count 0 2006.190.08:05:10.64#ibcon#wrote, iclass 31, count 0 2006.190.08:05:10.64#ibcon#about to read 3, iclass 31, count 0 2006.190.08:05:10.68#ibcon#read 3, iclass 31, count 0 2006.190.08:05:10.68#ibcon#about to read 4, iclass 31, count 0 2006.190.08:05:10.68#ibcon#read 4, iclass 31, count 0 2006.190.08:05:10.68#ibcon#about to read 5, iclass 31, count 0 2006.190.08:05:10.68#ibcon#read 5, iclass 31, count 0 2006.190.08:05:10.68#ibcon#about to read 6, iclass 31, count 0 2006.190.08:05:10.68#ibcon#read 6, iclass 31, count 0 2006.190.08:05:10.68#ibcon#end of sib2, iclass 31, count 0 2006.190.08:05:10.68#ibcon#*after write, iclass 31, count 0 2006.190.08:05:10.68#ibcon#*before return 0, iclass 31, count 0 2006.190.08:05:10.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:05:10.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:05:10.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.08:05:10.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.08:05:10.68$vc4f8/vb=1,4 2006.190.08:05:10.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.190.08:05:10.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.190.08:05:10.68#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:10.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:05:10.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:05:10.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:05:10.68#ibcon#enter wrdev, iclass 33, count 2 2006.190.08:05:10.68#ibcon#first serial, iclass 33, count 2 2006.190.08:05:10.68#ibcon#enter sib2, iclass 33, count 2 2006.190.08:05:10.68#ibcon#flushed, iclass 33, count 2 2006.190.08:05:10.68#ibcon#about to write, iclass 33, count 2 2006.190.08:05:10.68#ibcon#wrote, iclass 33, count 2 2006.190.08:05:10.68#ibcon#about to read 3, iclass 33, count 2 2006.190.08:05:10.70#ibcon#read 3, iclass 33, count 2 2006.190.08:05:10.70#ibcon#about to read 4, iclass 33, count 2 2006.190.08:05:10.70#ibcon#read 4, iclass 33, count 2 2006.190.08:05:10.70#ibcon#about to read 5, iclass 33, count 2 2006.190.08:05:10.70#ibcon#read 5, iclass 33, count 2 2006.190.08:05:10.70#ibcon#about to read 6, iclass 33, count 2 2006.190.08:05:10.70#ibcon#read 6, iclass 33, count 2 2006.190.08:05:10.70#ibcon#end of sib2, iclass 33, count 2 2006.190.08:05:10.70#ibcon#*mode == 0, iclass 33, count 2 2006.190.08:05:10.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.190.08:05:10.70#ibcon#[27=AT01-04\r\n] 2006.190.08:05:10.70#ibcon#*before write, iclass 33, count 2 2006.190.08:05:10.70#ibcon#enter sib2, iclass 33, count 2 2006.190.08:05:10.70#ibcon#flushed, iclass 33, count 2 2006.190.08:05:10.70#ibcon#about to write, iclass 33, count 2 2006.190.08:05:10.70#ibcon#wrote, iclass 33, count 2 2006.190.08:05:10.70#ibcon#about to read 3, iclass 33, count 2 2006.190.08:05:10.73#ibcon#read 3, iclass 33, count 2 2006.190.08:05:10.73#ibcon#about to read 4, iclass 33, count 2 2006.190.08:05:10.73#ibcon#read 4, iclass 33, count 2 2006.190.08:05:10.73#ibcon#about to read 5, iclass 33, count 2 2006.190.08:05:10.73#ibcon#read 5, iclass 33, count 2 2006.190.08:05:10.73#ibcon#about to read 6, iclass 33, count 2 2006.190.08:05:10.73#ibcon#read 6, iclass 33, count 2 2006.190.08:05:10.73#ibcon#end of sib2, iclass 33, count 2 2006.190.08:05:10.73#ibcon#*after write, iclass 33, count 2 2006.190.08:05:10.73#ibcon#*before return 0, iclass 33, count 2 2006.190.08:05:10.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:05:10.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:05:10.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.190.08:05:10.73#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:10.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:05:10.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:05:10.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:05:10.85#ibcon#enter wrdev, iclass 33, count 0 2006.190.08:05:10.85#ibcon#first serial, iclass 33, count 0 2006.190.08:05:10.85#ibcon#enter sib2, iclass 33, count 0 2006.190.08:05:10.85#ibcon#flushed, iclass 33, count 0 2006.190.08:05:10.85#ibcon#about to write, iclass 33, count 0 2006.190.08:05:10.85#ibcon#wrote, iclass 33, count 0 2006.190.08:05:10.85#ibcon#about to read 3, iclass 33, count 0 2006.190.08:05:10.87#ibcon#read 3, iclass 33, count 0 2006.190.08:05:10.87#ibcon#about to read 4, iclass 33, count 0 2006.190.08:05:10.87#ibcon#read 4, iclass 33, count 0 2006.190.08:05:10.87#ibcon#about to read 5, iclass 33, count 0 2006.190.08:05:10.87#ibcon#read 5, iclass 33, count 0 2006.190.08:05:10.87#ibcon#about to read 6, iclass 33, count 0 2006.190.08:05:10.87#ibcon#read 6, iclass 33, count 0 2006.190.08:05:10.87#ibcon#end of sib2, iclass 33, count 0 2006.190.08:05:10.87#ibcon#*mode == 0, iclass 33, count 0 2006.190.08:05:10.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.08:05:10.87#ibcon#[27=USB\r\n] 2006.190.08:05:10.87#ibcon#*before write, iclass 33, count 0 2006.190.08:05:10.87#ibcon#enter sib2, iclass 33, count 0 2006.190.08:05:10.87#ibcon#flushed, iclass 33, count 0 2006.190.08:05:10.87#ibcon#about to write, iclass 33, count 0 2006.190.08:05:10.87#ibcon#wrote, iclass 33, count 0 2006.190.08:05:10.87#ibcon#about to read 3, iclass 33, count 0 2006.190.08:05:10.90#ibcon#read 3, iclass 33, count 0 2006.190.08:05:10.90#ibcon#about to read 4, iclass 33, count 0 2006.190.08:05:10.90#ibcon#read 4, iclass 33, count 0 2006.190.08:05:10.90#ibcon#about to read 5, iclass 33, count 0 2006.190.08:05:10.90#ibcon#read 5, iclass 33, count 0 2006.190.08:05:10.90#ibcon#about to read 6, iclass 33, count 0 2006.190.08:05:10.90#ibcon#read 6, iclass 33, count 0 2006.190.08:05:10.90#ibcon#end of sib2, iclass 33, count 0 2006.190.08:05:10.90#ibcon#*after write, iclass 33, count 0 2006.190.08:05:10.90#ibcon#*before return 0, iclass 33, count 0 2006.190.08:05:10.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:05:10.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:05:10.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.08:05:10.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.08:05:10.90$vc4f8/vblo=2,640.99 2006.190.08:05:10.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.08:05:10.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.08:05:10.90#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:10.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:10.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:10.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:10.90#ibcon#enter wrdev, iclass 35, count 0 2006.190.08:05:10.90#ibcon#first serial, iclass 35, count 0 2006.190.08:05:10.90#ibcon#enter sib2, iclass 35, count 0 2006.190.08:05:10.90#ibcon#flushed, iclass 35, count 0 2006.190.08:05:10.90#ibcon#about to write, iclass 35, count 0 2006.190.08:05:10.90#ibcon#wrote, iclass 35, count 0 2006.190.08:05:10.90#ibcon#about to read 3, iclass 35, count 0 2006.190.08:05:10.92#ibcon#read 3, iclass 35, count 0 2006.190.08:05:10.92#ibcon#about to read 4, iclass 35, count 0 2006.190.08:05:10.92#ibcon#read 4, iclass 35, count 0 2006.190.08:05:10.92#ibcon#about to read 5, iclass 35, count 0 2006.190.08:05:10.92#ibcon#read 5, iclass 35, count 0 2006.190.08:05:10.92#ibcon#about to read 6, iclass 35, count 0 2006.190.08:05:10.92#ibcon#read 6, iclass 35, count 0 2006.190.08:05:10.92#ibcon#end of sib2, iclass 35, count 0 2006.190.08:05:10.92#ibcon#*mode == 0, iclass 35, count 0 2006.190.08:05:10.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.08:05:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:05:10.92#ibcon#*before write, iclass 35, count 0 2006.190.08:05:10.92#ibcon#enter sib2, iclass 35, count 0 2006.190.08:05:10.92#ibcon#flushed, iclass 35, count 0 2006.190.08:05:10.92#ibcon#about to write, iclass 35, count 0 2006.190.08:05:10.92#ibcon#wrote, iclass 35, count 0 2006.190.08:05:10.92#ibcon#about to read 3, iclass 35, count 0 2006.190.08:05:10.96#ibcon#read 3, iclass 35, count 0 2006.190.08:05:10.96#ibcon#about to read 4, iclass 35, count 0 2006.190.08:05:10.96#ibcon#read 4, iclass 35, count 0 2006.190.08:05:10.96#ibcon#about to read 5, iclass 35, count 0 2006.190.08:05:10.96#ibcon#read 5, iclass 35, count 0 2006.190.08:05:10.96#ibcon#about to read 6, iclass 35, count 0 2006.190.08:05:10.96#ibcon#read 6, iclass 35, count 0 2006.190.08:05:10.96#ibcon#end of sib2, iclass 35, count 0 2006.190.08:05:10.96#ibcon#*after write, iclass 35, count 0 2006.190.08:05:10.96#ibcon#*before return 0, iclass 35, count 0 2006.190.08:05:10.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:10.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:05:10.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.08:05:10.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.08:05:10.96$vc4f8/vb=2,4 2006.190.08:05:10.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.08:05:10.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.08:05:10.96#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:10.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:11.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:11.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:11.02#ibcon#enter wrdev, iclass 37, count 2 2006.190.08:05:11.02#ibcon#first serial, iclass 37, count 2 2006.190.08:05:11.02#ibcon#enter sib2, iclass 37, count 2 2006.190.08:05:11.02#ibcon#flushed, iclass 37, count 2 2006.190.08:05:11.02#ibcon#about to write, iclass 37, count 2 2006.190.08:05:11.02#ibcon#wrote, iclass 37, count 2 2006.190.08:05:11.02#ibcon#about to read 3, iclass 37, count 2 2006.190.08:05:11.04#ibcon#read 3, iclass 37, count 2 2006.190.08:05:11.04#ibcon#about to read 4, iclass 37, count 2 2006.190.08:05:11.04#ibcon#read 4, iclass 37, count 2 2006.190.08:05:11.04#ibcon#about to read 5, iclass 37, count 2 2006.190.08:05:11.04#ibcon#read 5, iclass 37, count 2 2006.190.08:05:11.04#ibcon#about to read 6, iclass 37, count 2 2006.190.08:05:11.04#ibcon#read 6, iclass 37, count 2 2006.190.08:05:11.04#ibcon#end of sib2, iclass 37, count 2 2006.190.08:05:11.04#ibcon#*mode == 0, iclass 37, count 2 2006.190.08:05:11.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.08:05:11.04#ibcon#[27=AT02-04\r\n] 2006.190.08:05:11.04#ibcon#*before write, iclass 37, count 2 2006.190.08:05:11.04#ibcon#enter sib2, iclass 37, count 2 2006.190.08:05:11.04#ibcon#flushed, iclass 37, count 2 2006.190.08:05:11.04#ibcon#about to write, iclass 37, count 2 2006.190.08:05:11.04#ibcon#wrote, iclass 37, count 2 2006.190.08:05:11.04#ibcon#about to read 3, iclass 37, count 2 2006.190.08:05:11.07#ibcon#read 3, iclass 37, count 2 2006.190.08:05:11.07#ibcon#about to read 4, iclass 37, count 2 2006.190.08:05:11.07#ibcon#read 4, iclass 37, count 2 2006.190.08:05:11.07#ibcon#about to read 5, iclass 37, count 2 2006.190.08:05:11.07#ibcon#read 5, iclass 37, count 2 2006.190.08:05:11.07#ibcon#about to read 6, iclass 37, count 2 2006.190.08:05:11.07#ibcon#read 6, iclass 37, count 2 2006.190.08:05:11.07#ibcon#end of sib2, iclass 37, count 2 2006.190.08:05:11.07#ibcon#*after write, iclass 37, count 2 2006.190.08:05:11.07#ibcon#*before return 0, iclass 37, count 2 2006.190.08:05:11.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:11.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:05:11.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.08:05:11.07#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:11.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:11.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:11.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:11.19#ibcon#enter wrdev, iclass 37, count 0 2006.190.08:05:11.19#ibcon#first serial, iclass 37, count 0 2006.190.08:05:11.19#ibcon#enter sib2, iclass 37, count 0 2006.190.08:05:11.19#ibcon#flushed, iclass 37, count 0 2006.190.08:05:11.19#ibcon#about to write, iclass 37, count 0 2006.190.08:05:11.19#ibcon#wrote, iclass 37, count 0 2006.190.08:05:11.19#ibcon#about to read 3, iclass 37, count 0 2006.190.08:05:11.21#ibcon#read 3, iclass 37, count 0 2006.190.08:05:11.21#ibcon#about to read 4, iclass 37, count 0 2006.190.08:05:11.21#ibcon#read 4, iclass 37, count 0 2006.190.08:05:11.21#ibcon#about to read 5, iclass 37, count 0 2006.190.08:05:11.21#ibcon#read 5, iclass 37, count 0 2006.190.08:05:11.21#ibcon#about to read 6, iclass 37, count 0 2006.190.08:05:11.21#ibcon#read 6, iclass 37, count 0 2006.190.08:05:11.21#ibcon#end of sib2, iclass 37, count 0 2006.190.08:05:11.21#ibcon#*mode == 0, iclass 37, count 0 2006.190.08:05:11.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.08:05:11.21#ibcon#[27=USB\r\n] 2006.190.08:05:11.21#ibcon#*before write, iclass 37, count 0 2006.190.08:05:11.21#ibcon#enter sib2, iclass 37, count 0 2006.190.08:05:11.21#ibcon#flushed, iclass 37, count 0 2006.190.08:05:11.21#ibcon#about to write, iclass 37, count 0 2006.190.08:05:11.21#ibcon#wrote, iclass 37, count 0 2006.190.08:05:11.21#ibcon#about to read 3, iclass 37, count 0 2006.190.08:05:11.24#ibcon#read 3, iclass 37, count 0 2006.190.08:05:11.24#ibcon#about to read 4, iclass 37, count 0 2006.190.08:05:11.24#ibcon#read 4, iclass 37, count 0 2006.190.08:05:11.24#ibcon#about to read 5, iclass 37, count 0 2006.190.08:05:11.24#ibcon#read 5, iclass 37, count 0 2006.190.08:05:11.24#ibcon#about to read 6, iclass 37, count 0 2006.190.08:05:11.24#ibcon#read 6, iclass 37, count 0 2006.190.08:05:11.24#ibcon#end of sib2, iclass 37, count 0 2006.190.08:05:11.24#ibcon#*after write, iclass 37, count 0 2006.190.08:05:11.24#ibcon#*before return 0, iclass 37, count 0 2006.190.08:05:11.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:11.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:05:11.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.08:05:11.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.08:05:11.24$vc4f8/vblo=3,656.99 2006.190.08:05:11.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.08:05:11.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.08:05:11.24#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:11.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:11.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:11.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:11.24#ibcon#enter wrdev, iclass 39, count 0 2006.190.08:05:11.24#ibcon#first serial, iclass 39, count 0 2006.190.08:05:11.24#ibcon#enter sib2, iclass 39, count 0 2006.190.08:05:11.24#ibcon#flushed, iclass 39, count 0 2006.190.08:05:11.24#ibcon#about to write, iclass 39, count 0 2006.190.08:05:11.24#ibcon#wrote, iclass 39, count 0 2006.190.08:05:11.24#ibcon#about to read 3, iclass 39, count 0 2006.190.08:05:11.26#ibcon#read 3, iclass 39, count 0 2006.190.08:05:11.26#ibcon#about to read 4, iclass 39, count 0 2006.190.08:05:11.26#ibcon#read 4, iclass 39, count 0 2006.190.08:05:11.26#ibcon#about to read 5, iclass 39, count 0 2006.190.08:05:11.26#ibcon#read 5, iclass 39, count 0 2006.190.08:05:11.26#ibcon#about to read 6, iclass 39, count 0 2006.190.08:05:11.26#ibcon#read 6, iclass 39, count 0 2006.190.08:05:11.26#ibcon#end of sib2, iclass 39, count 0 2006.190.08:05:11.26#ibcon#*mode == 0, iclass 39, count 0 2006.190.08:05:11.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.08:05:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:05:11.26#ibcon#*before write, iclass 39, count 0 2006.190.08:05:11.26#ibcon#enter sib2, iclass 39, count 0 2006.190.08:05:11.26#ibcon#flushed, iclass 39, count 0 2006.190.08:05:11.26#ibcon#about to write, iclass 39, count 0 2006.190.08:05:11.26#ibcon#wrote, iclass 39, count 0 2006.190.08:05:11.26#ibcon#about to read 3, iclass 39, count 0 2006.190.08:05:11.30#ibcon#read 3, iclass 39, count 0 2006.190.08:05:11.30#ibcon#about to read 4, iclass 39, count 0 2006.190.08:05:11.30#ibcon#read 4, iclass 39, count 0 2006.190.08:05:11.30#ibcon#about to read 5, iclass 39, count 0 2006.190.08:05:11.30#ibcon#read 5, iclass 39, count 0 2006.190.08:05:11.30#ibcon#about to read 6, iclass 39, count 0 2006.190.08:05:11.30#ibcon#read 6, iclass 39, count 0 2006.190.08:05:11.30#ibcon#end of sib2, iclass 39, count 0 2006.190.08:05:11.30#ibcon#*after write, iclass 39, count 0 2006.190.08:05:11.30#ibcon#*before return 0, iclass 39, count 0 2006.190.08:05:11.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:11.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:05:11.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.08:05:11.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.08:05:11.30$vc4f8/vb=3,4 2006.190.08:05:11.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.08:05:11.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.08:05:11.30#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:11.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:11.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:11.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:11.36#ibcon#enter wrdev, iclass 3, count 2 2006.190.08:05:11.36#ibcon#first serial, iclass 3, count 2 2006.190.08:05:11.36#ibcon#enter sib2, iclass 3, count 2 2006.190.08:05:11.36#ibcon#flushed, iclass 3, count 2 2006.190.08:05:11.36#ibcon#about to write, iclass 3, count 2 2006.190.08:05:11.36#ibcon#wrote, iclass 3, count 2 2006.190.08:05:11.36#ibcon#about to read 3, iclass 3, count 2 2006.190.08:05:11.38#ibcon#read 3, iclass 3, count 2 2006.190.08:05:11.38#ibcon#about to read 4, iclass 3, count 2 2006.190.08:05:11.38#ibcon#read 4, iclass 3, count 2 2006.190.08:05:11.38#ibcon#about to read 5, iclass 3, count 2 2006.190.08:05:11.38#ibcon#read 5, iclass 3, count 2 2006.190.08:05:11.38#ibcon#about to read 6, iclass 3, count 2 2006.190.08:05:11.38#ibcon#read 6, iclass 3, count 2 2006.190.08:05:11.38#ibcon#end of sib2, iclass 3, count 2 2006.190.08:05:11.38#ibcon#*mode == 0, iclass 3, count 2 2006.190.08:05:11.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.08:05:11.38#ibcon#[27=AT03-04\r\n] 2006.190.08:05:11.38#ibcon#*before write, iclass 3, count 2 2006.190.08:05:11.38#ibcon#enter sib2, iclass 3, count 2 2006.190.08:05:11.38#ibcon#flushed, iclass 3, count 2 2006.190.08:05:11.38#ibcon#about to write, iclass 3, count 2 2006.190.08:05:11.38#ibcon#wrote, iclass 3, count 2 2006.190.08:05:11.38#ibcon#about to read 3, iclass 3, count 2 2006.190.08:05:11.41#ibcon#read 3, iclass 3, count 2 2006.190.08:05:11.41#ibcon#about to read 4, iclass 3, count 2 2006.190.08:05:11.41#ibcon#read 4, iclass 3, count 2 2006.190.08:05:11.41#ibcon#about to read 5, iclass 3, count 2 2006.190.08:05:11.41#ibcon#read 5, iclass 3, count 2 2006.190.08:05:11.41#ibcon#about to read 6, iclass 3, count 2 2006.190.08:05:11.41#ibcon#read 6, iclass 3, count 2 2006.190.08:05:11.41#ibcon#end of sib2, iclass 3, count 2 2006.190.08:05:11.41#ibcon#*after write, iclass 3, count 2 2006.190.08:05:11.41#ibcon#*before return 0, iclass 3, count 2 2006.190.08:05:11.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:11.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:05:11.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.08:05:11.41#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:11.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:11.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:11.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:11.53#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:05:11.53#ibcon#first serial, iclass 3, count 0 2006.190.08:05:11.53#ibcon#enter sib2, iclass 3, count 0 2006.190.08:05:11.53#ibcon#flushed, iclass 3, count 0 2006.190.08:05:11.53#ibcon#about to write, iclass 3, count 0 2006.190.08:05:11.53#ibcon#wrote, iclass 3, count 0 2006.190.08:05:11.53#ibcon#about to read 3, iclass 3, count 0 2006.190.08:05:11.55#ibcon#read 3, iclass 3, count 0 2006.190.08:05:11.55#ibcon#about to read 4, iclass 3, count 0 2006.190.08:05:11.55#ibcon#read 4, iclass 3, count 0 2006.190.08:05:11.55#ibcon#about to read 5, iclass 3, count 0 2006.190.08:05:11.55#ibcon#read 5, iclass 3, count 0 2006.190.08:05:11.55#ibcon#about to read 6, iclass 3, count 0 2006.190.08:05:11.55#ibcon#read 6, iclass 3, count 0 2006.190.08:05:11.55#ibcon#end of sib2, iclass 3, count 0 2006.190.08:05:11.55#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:05:11.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:05:11.55#ibcon#[27=USB\r\n] 2006.190.08:05:11.55#ibcon#*before write, iclass 3, count 0 2006.190.08:05:11.55#ibcon#enter sib2, iclass 3, count 0 2006.190.08:05:11.55#ibcon#flushed, iclass 3, count 0 2006.190.08:05:11.55#ibcon#about to write, iclass 3, count 0 2006.190.08:05:11.55#ibcon#wrote, iclass 3, count 0 2006.190.08:05:11.55#ibcon#about to read 3, iclass 3, count 0 2006.190.08:05:11.58#ibcon#read 3, iclass 3, count 0 2006.190.08:05:11.58#ibcon#about to read 4, iclass 3, count 0 2006.190.08:05:11.58#ibcon#read 4, iclass 3, count 0 2006.190.08:05:11.58#ibcon#about to read 5, iclass 3, count 0 2006.190.08:05:11.58#ibcon#read 5, iclass 3, count 0 2006.190.08:05:11.58#ibcon#about to read 6, iclass 3, count 0 2006.190.08:05:11.58#ibcon#read 6, iclass 3, count 0 2006.190.08:05:11.58#ibcon#end of sib2, iclass 3, count 0 2006.190.08:05:11.58#ibcon#*after write, iclass 3, count 0 2006.190.08:05:11.58#ibcon#*before return 0, iclass 3, count 0 2006.190.08:05:11.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:11.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:05:11.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:05:11.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:05:11.58$vc4f8/vblo=4,712.99 2006.190.08:05:11.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.08:05:11.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.08:05:11.58#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:11.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:11.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:11.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:11.58#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:05:11.58#ibcon#first serial, iclass 5, count 0 2006.190.08:05:11.58#ibcon#enter sib2, iclass 5, count 0 2006.190.08:05:11.58#ibcon#flushed, iclass 5, count 0 2006.190.08:05:11.58#ibcon#about to write, iclass 5, count 0 2006.190.08:05:11.58#ibcon#wrote, iclass 5, count 0 2006.190.08:05:11.58#ibcon#about to read 3, iclass 5, count 0 2006.190.08:05:11.60#ibcon#read 3, iclass 5, count 0 2006.190.08:05:11.60#ibcon#about to read 4, iclass 5, count 0 2006.190.08:05:11.60#ibcon#read 4, iclass 5, count 0 2006.190.08:05:11.60#ibcon#about to read 5, iclass 5, count 0 2006.190.08:05:11.60#ibcon#read 5, iclass 5, count 0 2006.190.08:05:11.60#ibcon#about to read 6, iclass 5, count 0 2006.190.08:05:11.60#ibcon#read 6, iclass 5, count 0 2006.190.08:05:11.60#ibcon#end of sib2, iclass 5, count 0 2006.190.08:05:11.60#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:05:11.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:05:11.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:05:11.60#ibcon#*before write, iclass 5, count 0 2006.190.08:05:11.60#ibcon#enter sib2, iclass 5, count 0 2006.190.08:05:11.60#ibcon#flushed, iclass 5, count 0 2006.190.08:05:11.60#ibcon#about to write, iclass 5, count 0 2006.190.08:05:11.60#ibcon#wrote, iclass 5, count 0 2006.190.08:05:11.60#ibcon#about to read 3, iclass 5, count 0 2006.190.08:05:11.64#ibcon#read 3, iclass 5, count 0 2006.190.08:05:11.64#ibcon#about to read 4, iclass 5, count 0 2006.190.08:05:11.64#ibcon#read 4, iclass 5, count 0 2006.190.08:05:11.64#ibcon#about to read 5, iclass 5, count 0 2006.190.08:05:11.64#ibcon#read 5, iclass 5, count 0 2006.190.08:05:11.64#ibcon#about to read 6, iclass 5, count 0 2006.190.08:05:11.64#ibcon#read 6, iclass 5, count 0 2006.190.08:05:11.64#ibcon#end of sib2, iclass 5, count 0 2006.190.08:05:11.64#ibcon#*after write, iclass 5, count 0 2006.190.08:05:11.64#ibcon#*before return 0, iclass 5, count 0 2006.190.08:05:11.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:11.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:05:11.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:05:11.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:05:11.64$vc4f8/vb=4,4 2006.190.08:05:11.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.08:05:11.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.08:05:11.64#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:11.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:11.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:11.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:11.70#ibcon#enter wrdev, iclass 7, count 2 2006.190.08:05:11.70#ibcon#first serial, iclass 7, count 2 2006.190.08:05:11.70#ibcon#enter sib2, iclass 7, count 2 2006.190.08:05:11.70#ibcon#flushed, iclass 7, count 2 2006.190.08:05:11.70#ibcon#about to write, iclass 7, count 2 2006.190.08:05:11.70#ibcon#wrote, iclass 7, count 2 2006.190.08:05:11.70#ibcon#about to read 3, iclass 7, count 2 2006.190.08:05:11.72#ibcon#read 3, iclass 7, count 2 2006.190.08:05:11.72#ibcon#about to read 4, iclass 7, count 2 2006.190.08:05:11.72#ibcon#read 4, iclass 7, count 2 2006.190.08:05:11.72#ibcon#about to read 5, iclass 7, count 2 2006.190.08:05:11.72#ibcon#read 5, iclass 7, count 2 2006.190.08:05:11.72#ibcon#about to read 6, iclass 7, count 2 2006.190.08:05:11.72#ibcon#read 6, iclass 7, count 2 2006.190.08:05:11.72#ibcon#end of sib2, iclass 7, count 2 2006.190.08:05:11.72#ibcon#*mode == 0, iclass 7, count 2 2006.190.08:05:11.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.08:05:11.72#ibcon#[27=AT04-04\r\n] 2006.190.08:05:11.72#ibcon#*before write, iclass 7, count 2 2006.190.08:05:11.72#ibcon#enter sib2, iclass 7, count 2 2006.190.08:05:11.72#ibcon#flushed, iclass 7, count 2 2006.190.08:05:11.72#ibcon#about to write, iclass 7, count 2 2006.190.08:05:11.72#ibcon#wrote, iclass 7, count 2 2006.190.08:05:11.72#ibcon#about to read 3, iclass 7, count 2 2006.190.08:05:11.75#ibcon#read 3, iclass 7, count 2 2006.190.08:05:11.75#ibcon#about to read 4, iclass 7, count 2 2006.190.08:05:11.75#ibcon#read 4, iclass 7, count 2 2006.190.08:05:11.75#ibcon#about to read 5, iclass 7, count 2 2006.190.08:05:11.75#ibcon#read 5, iclass 7, count 2 2006.190.08:05:11.75#ibcon#about to read 6, iclass 7, count 2 2006.190.08:05:11.75#ibcon#read 6, iclass 7, count 2 2006.190.08:05:11.75#ibcon#end of sib2, iclass 7, count 2 2006.190.08:05:11.75#ibcon#*after write, iclass 7, count 2 2006.190.08:05:11.75#ibcon#*before return 0, iclass 7, count 2 2006.190.08:05:11.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:11.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:05:11.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.08:05:11.75#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:11.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:11.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:11.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:11.87#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:05:11.87#ibcon#first serial, iclass 7, count 0 2006.190.08:05:11.87#ibcon#enter sib2, iclass 7, count 0 2006.190.08:05:11.87#ibcon#flushed, iclass 7, count 0 2006.190.08:05:11.87#ibcon#about to write, iclass 7, count 0 2006.190.08:05:11.87#ibcon#wrote, iclass 7, count 0 2006.190.08:05:11.87#ibcon#about to read 3, iclass 7, count 0 2006.190.08:05:11.89#ibcon#read 3, iclass 7, count 0 2006.190.08:05:11.89#ibcon#about to read 4, iclass 7, count 0 2006.190.08:05:11.89#ibcon#read 4, iclass 7, count 0 2006.190.08:05:11.89#ibcon#about to read 5, iclass 7, count 0 2006.190.08:05:11.89#ibcon#read 5, iclass 7, count 0 2006.190.08:05:11.89#ibcon#about to read 6, iclass 7, count 0 2006.190.08:05:11.89#ibcon#read 6, iclass 7, count 0 2006.190.08:05:11.89#ibcon#end of sib2, iclass 7, count 0 2006.190.08:05:11.89#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:05:11.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:05:11.89#ibcon#[27=USB\r\n] 2006.190.08:05:11.89#ibcon#*before write, iclass 7, count 0 2006.190.08:05:11.89#ibcon#enter sib2, iclass 7, count 0 2006.190.08:05:11.89#ibcon#flushed, iclass 7, count 0 2006.190.08:05:11.89#ibcon#about to write, iclass 7, count 0 2006.190.08:05:11.89#ibcon#wrote, iclass 7, count 0 2006.190.08:05:11.89#ibcon#about to read 3, iclass 7, count 0 2006.190.08:05:11.92#ibcon#read 3, iclass 7, count 0 2006.190.08:05:11.92#ibcon#about to read 4, iclass 7, count 0 2006.190.08:05:11.92#ibcon#read 4, iclass 7, count 0 2006.190.08:05:11.92#ibcon#about to read 5, iclass 7, count 0 2006.190.08:05:11.92#ibcon#read 5, iclass 7, count 0 2006.190.08:05:11.92#ibcon#about to read 6, iclass 7, count 0 2006.190.08:05:11.92#ibcon#read 6, iclass 7, count 0 2006.190.08:05:11.92#ibcon#end of sib2, iclass 7, count 0 2006.190.08:05:11.92#ibcon#*after write, iclass 7, count 0 2006.190.08:05:11.92#ibcon#*before return 0, iclass 7, count 0 2006.190.08:05:11.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:11.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:05:11.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:05:11.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:05:11.93$vc4f8/vblo=5,744.99 2006.190.08:05:11.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.08:05:11.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.08:05:11.93#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:11.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:11.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:11.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:11.93#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:05:11.93#ibcon#first serial, iclass 11, count 0 2006.190.08:05:11.93#ibcon#enter sib2, iclass 11, count 0 2006.190.08:05:11.93#ibcon#flushed, iclass 11, count 0 2006.190.08:05:11.93#ibcon#about to write, iclass 11, count 0 2006.190.08:05:11.93#ibcon#wrote, iclass 11, count 0 2006.190.08:05:11.93#ibcon#about to read 3, iclass 11, count 0 2006.190.08:05:11.94#ibcon#read 3, iclass 11, count 0 2006.190.08:05:11.94#ibcon#about to read 4, iclass 11, count 0 2006.190.08:05:11.94#ibcon#read 4, iclass 11, count 0 2006.190.08:05:11.94#ibcon#about to read 5, iclass 11, count 0 2006.190.08:05:11.94#ibcon#read 5, iclass 11, count 0 2006.190.08:05:11.94#ibcon#about to read 6, iclass 11, count 0 2006.190.08:05:11.94#ibcon#read 6, iclass 11, count 0 2006.190.08:05:11.94#ibcon#end of sib2, iclass 11, count 0 2006.190.08:05:11.94#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:05:11.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:05:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:05:11.94#ibcon#*before write, iclass 11, count 0 2006.190.08:05:11.94#ibcon#enter sib2, iclass 11, count 0 2006.190.08:05:11.94#ibcon#flushed, iclass 11, count 0 2006.190.08:05:11.94#ibcon#about to write, iclass 11, count 0 2006.190.08:05:11.94#ibcon#wrote, iclass 11, count 0 2006.190.08:05:11.94#ibcon#about to read 3, iclass 11, count 0 2006.190.08:05:11.98#ibcon#read 3, iclass 11, count 0 2006.190.08:05:11.98#ibcon#about to read 4, iclass 11, count 0 2006.190.08:05:11.98#ibcon#read 4, iclass 11, count 0 2006.190.08:05:11.98#ibcon#about to read 5, iclass 11, count 0 2006.190.08:05:11.98#ibcon#read 5, iclass 11, count 0 2006.190.08:05:11.98#ibcon#about to read 6, iclass 11, count 0 2006.190.08:05:11.98#ibcon#read 6, iclass 11, count 0 2006.190.08:05:11.98#ibcon#end of sib2, iclass 11, count 0 2006.190.08:05:11.98#ibcon#*after write, iclass 11, count 0 2006.190.08:05:11.98#ibcon#*before return 0, iclass 11, count 0 2006.190.08:05:11.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:11.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:05:11.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:05:11.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:05:11.98$vc4f8/vb=5,4 2006.190.08:05:11.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.08:05:11.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.08:05:11.98#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:11.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:12.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:12.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:12.04#ibcon#enter wrdev, iclass 13, count 2 2006.190.08:05:12.04#ibcon#first serial, iclass 13, count 2 2006.190.08:05:12.04#ibcon#enter sib2, iclass 13, count 2 2006.190.08:05:12.04#ibcon#flushed, iclass 13, count 2 2006.190.08:05:12.04#ibcon#about to write, iclass 13, count 2 2006.190.08:05:12.04#ibcon#wrote, iclass 13, count 2 2006.190.08:05:12.04#ibcon#about to read 3, iclass 13, count 2 2006.190.08:05:12.06#ibcon#read 3, iclass 13, count 2 2006.190.08:05:12.06#ibcon#about to read 4, iclass 13, count 2 2006.190.08:05:12.06#ibcon#read 4, iclass 13, count 2 2006.190.08:05:12.06#ibcon#about to read 5, iclass 13, count 2 2006.190.08:05:12.06#ibcon#read 5, iclass 13, count 2 2006.190.08:05:12.06#ibcon#about to read 6, iclass 13, count 2 2006.190.08:05:12.06#ibcon#read 6, iclass 13, count 2 2006.190.08:05:12.06#ibcon#end of sib2, iclass 13, count 2 2006.190.08:05:12.06#ibcon#*mode == 0, iclass 13, count 2 2006.190.08:05:12.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.08:05:12.06#ibcon#[27=AT05-04\r\n] 2006.190.08:05:12.06#ibcon#*before write, iclass 13, count 2 2006.190.08:05:12.06#ibcon#enter sib2, iclass 13, count 2 2006.190.08:05:12.06#ibcon#flushed, iclass 13, count 2 2006.190.08:05:12.06#ibcon#about to write, iclass 13, count 2 2006.190.08:05:12.06#ibcon#wrote, iclass 13, count 2 2006.190.08:05:12.06#ibcon#about to read 3, iclass 13, count 2 2006.190.08:05:12.09#ibcon#read 3, iclass 13, count 2 2006.190.08:05:12.09#ibcon#about to read 4, iclass 13, count 2 2006.190.08:05:12.09#ibcon#read 4, iclass 13, count 2 2006.190.08:05:12.09#ibcon#about to read 5, iclass 13, count 2 2006.190.08:05:12.09#ibcon#read 5, iclass 13, count 2 2006.190.08:05:12.09#ibcon#about to read 6, iclass 13, count 2 2006.190.08:05:12.09#ibcon#read 6, iclass 13, count 2 2006.190.08:05:12.09#ibcon#end of sib2, iclass 13, count 2 2006.190.08:05:12.09#ibcon#*after write, iclass 13, count 2 2006.190.08:05:12.09#ibcon#*before return 0, iclass 13, count 2 2006.190.08:05:12.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:12.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:05:12.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.08:05:12.09#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:12.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:12.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:12.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:12.21#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:05:12.21#ibcon#first serial, iclass 13, count 0 2006.190.08:05:12.21#ibcon#enter sib2, iclass 13, count 0 2006.190.08:05:12.21#ibcon#flushed, iclass 13, count 0 2006.190.08:05:12.21#ibcon#about to write, iclass 13, count 0 2006.190.08:05:12.21#ibcon#wrote, iclass 13, count 0 2006.190.08:05:12.21#ibcon#about to read 3, iclass 13, count 0 2006.190.08:05:12.23#ibcon#read 3, iclass 13, count 0 2006.190.08:05:12.23#ibcon#about to read 4, iclass 13, count 0 2006.190.08:05:12.23#ibcon#read 4, iclass 13, count 0 2006.190.08:05:12.23#ibcon#about to read 5, iclass 13, count 0 2006.190.08:05:12.23#ibcon#read 5, iclass 13, count 0 2006.190.08:05:12.23#ibcon#about to read 6, iclass 13, count 0 2006.190.08:05:12.23#ibcon#read 6, iclass 13, count 0 2006.190.08:05:12.23#ibcon#end of sib2, iclass 13, count 0 2006.190.08:05:12.23#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:05:12.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:05:12.23#ibcon#[27=USB\r\n] 2006.190.08:05:12.23#ibcon#*before write, iclass 13, count 0 2006.190.08:05:12.23#ibcon#enter sib2, iclass 13, count 0 2006.190.08:05:12.23#ibcon#flushed, iclass 13, count 0 2006.190.08:05:12.23#ibcon#about to write, iclass 13, count 0 2006.190.08:05:12.23#ibcon#wrote, iclass 13, count 0 2006.190.08:05:12.23#ibcon#about to read 3, iclass 13, count 0 2006.190.08:05:12.26#ibcon#read 3, iclass 13, count 0 2006.190.08:05:12.26#ibcon#about to read 4, iclass 13, count 0 2006.190.08:05:12.26#ibcon#read 4, iclass 13, count 0 2006.190.08:05:12.26#ibcon#about to read 5, iclass 13, count 0 2006.190.08:05:12.26#ibcon#read 5, iclass 13, count 0 2006.190.08:05:12.26#ibcon#about to read 6, iclass 13, count 0 2006.190.08:05:12.26#ibcon#read 6, iclass 13, count 0 2006.190.08:05:12.26#ibcon#end of sib2, iclass 13, count 0 2006.190.08:05:12.26#ibcon#*after write, iclass 13, count 0 2006.190.08:05:12.26#ibcon#*before return 0, iclass 13, count 0 2006.190.08:05:12.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:12.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:05:12.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:05:12.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:05:12.26$vc4f8/vblo=6,752.99 2006.190.08:05:12.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.08:05:12.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.08:05:12.26#ibcon#ireg 17 cls_cnt 0 2006.190.08:05:12.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:12.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:12.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:12.26#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:05:12.26#ibcon#first serial, iclass 15, count 0 2006.190.08:05:12.26#ibcon#enter sib2, iclass 15, count 0 2006.190.08:05:12.26#ibcon#flushed, iclass 15, count 0 2006.190.08:05:12.26#ibcon#about to write, iclass 15, count 0 2006.190.08:05:12.26#ibcon#wrote, iclass 15, count 0 2006.190.08:05:12.26#ibcon#about to read 3, iclass 15, count 0 2006.190.08:05:12.28#ibcon#read 3, iclass 15, count 0 2006.190.08:05:12.28#ibcon#about to read 4, iclass 15, count 0 2006.190.08:05:12.28#ibcon#read 4, iclass 15, count 0 2006.190.08:05:12.28#ibcon#about to read 5, iclass 15, count 0 2006.190.08:05:12.28#ibcon#read 5, iclass 15, count 0 2006.190.08:05:12.28#ibcon#about to read 6, iclass 15, count 0 2006.190.08:05:12.28#ibcon#read 6, iclass 15, count 0 2006.190.08:05:12.28#ibcon#end of sib2, iclass 15, count 0 2006.190.08:05:12.28#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:05:12.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:05:12.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:05:12.28#ibcon#*before write, iclass 15, count 0 2006.190.08:05:12.28#ibcon#enter sib2, iclass 15, count 0 2006.190.08:05:12.28#ibcon#flushed, iclass 15, count 0 2006.190.08:05:12.28#ibcon#about to write, iclass 15, count 0 2006.190.08:05:12.28#ibcon#wrote, iclass 15, count 0 2006.190.08:05:12.28#ibcon#about to read 3, iclass 15, count 0 2006.190.08:05:12.32#ibcon#read 3, iclass 15, count 0 2006.190.08:05:12.32#ibcon#about to read 4, iclass 15, count 0 2006.190.08:05:12.32#ibcon#read 4, iclass 15, count 0 2006.190.08:05:12.32#ibcon#about to read 5, iclass 15, count 0 2006.190.08:05:12.32#ibcon#read 5, iclass 15, count 0 2006.190.08:05:12.32#ibcon#about to read 6, iclass 15, count 0 2006.190.08:05:12.32#ibcon#read 6, iclass 15, count 0 2006.190.08:05:12.32#ibcon#end of sib2, iclass 15, count 0 2006.190.08:05:12.32#ibcon#*after write, iclass 15, count 0 2006.190.08:05:12.32#ibcon#*before return 0, iclass 15, count 0 2006.190.08:05:12.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:12.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:05:12.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:05:12.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:05:12.32$vc4f8/vb=6,4 2006.190.08:05:12.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.08:05:12.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.08:05:12.32#ibcon#ireg 11 cls_cnt 2 2006.190.08:05:12.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:12.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:12.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:12.38#ibcon#enter wrdev, iclass 17, count 2 2006.190.08:05:12.38#ibcon#first serial, iclass 17, count 2 2006.190.08:05:12.38#ibcon#enter sib2, iclass 17, count 2 2006.190.08:05:12.38#ibcon#flushed, iclass 17, count 2 2006.190.08:05:12.38#ibcon#about to write, iclass 17, count 2 2006.190.08:05:12.38#ibcon#wrote, iclass 17, count 2 2006.190.08:05:12.38#ibcon#about to read 3, iclass 17, count 2 2006.190.08:05:12.40#ibcon#read 3, iclass 17, count 2 2006.190.08:05:12.40#ibcon#about to read 4, iclass 17, count 2 2006.190.08:05:12.40#ibcon#read 4, iclass 17, count 2 2006.190.08:05:12.40#ibcon#about to read 5, iclass 17, count 2 2006.190.08:05:12.40#ibcon#read 5, iclass 17, count 2 2006.190.08:05:12.40#ibcon#about to read 6, iclass 17, count 2 2006.190.08:05:12.40#ibcon#read 6, iclass 17, count 2 2006.190.08:05:12.40#ibcon#end of sib2, iclass 17, count 2 2006.190.08:05:12.40#ibcon#*mode == 0, iclass 17, count 2 2006.190.08:05:12.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.08:05:12.40#ibcon#[27=AT06-04\r\n] 2006.190.08:05:12.40#ibcon#*before write, iclass 17, count 2 2006.190.08:05:12.40#ibcon#enter sib2, iclass 17, count 2 2006.190.08:05:12.40#ibcon#flushed, iclass 17, count 2 2006.190.08:05:12.40#ibcon#about to write, iclass 17, count 2 2006.190.08:05:12.40#ibcon#wrote, iclass 17, count 2 2006.190.08:05:12.40#ibcon#about to read 3, iclass 17, count 2 2006.190.08:05:12.43#ibcon#read 3, iclass 17, count 2 2006.190.08:05:12.43#ibcon#about to read 4, iclass 17, count 2 2006.190.08:05:12.43#ibcon#read 4, iclass 17, count 2 2006.190.08:05:12.43#ibcon#about to read 5, iclass 17, count 2 2006.190.08:05:12.43#ibcon#read 5, iclass 17, count 2 2006.190.08:05:12.43#ibcon#about to read 6, iclass 17, count 2 2006.190.08:05:12.43#ibcon#read 6, iclass 17, count 2 2006.190.08:05:12.43#ibcon#end of sib2, iclass 17, count 2 2006.190.08:05:12.43#ibcon#*after write, iclass 17, count 2 2006.190.08:05:12.43#ibcon#*before return 0, iclass 17, count 2 2006.190.08:05:12.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:12.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:05:12.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.08:05:12.43#ibcon#ireg 7 cls_cnt 0 2006.190.08:05:12.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:12.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:12.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:12.55#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:05:12.55#ibcon#first serial, iclass 17, count 0 2006.190.08:05:12.55#ibcon#enter sib2, iclass 17, count 0 2006.190.08:05:12.55#ibcon#flushed, iclass 17, count 0 2006.190.08:05:12.55#ibcon#about to write, iclass 17, count 0 2006.190.08:05:12.55#ibcon#wrote, iclass 17, count 0 2006.190.08:05:12.55#ibcon#about to read 3, iclass 17, count 0 2006.190.08:05:12.57#ibcon#read 3, iclass 17, count 0 2006.190.08:05:12.57#ibcon#about to read 4, iclass 17, count 0 2006.190.08:05:12.57#ibcon#read 4, iclass 17, count 0 2006.190.08:05:12.57#ibcon#about to read 5, iclass 17, count 0 2006.190.08:05:12.57#ibcon#read 5, iclass 17, count 0 2006.190.08:05:12.57#ibcon#about to read 6, iclass 17, count 0 2006.190.08:05:12.57#ibcon#read 6, iclass 17, count 0 2006.190.08:05:12.57#ibcon#end of sib2, iclass 17, count 0 2006.190.08:05:12.57#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:05:12.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:05:12.57#ibcon#[27=USB\r\n] 2006.190.08:05:12.57#ibcon#*before write, iclass 17, count 0 2006.190.08:05:12.57#ibcon#enter sib2, iclass 17, count 0 2006.190.08:05:12.57#ibcon#flushed, iclass 17, count 0 2006.190.08:05:12.57#ibcon#about to write, iclass 17, count 0 2006.190.08:05:12.57#ibcon#wrote, iclass 17, count 0 2006.190.08:05:12.57#ibcon#about to read 3, iclass 17, count 0 2006.190.08:05:12.61#ibcon#read 3, iclass 17, count 0 2006.190.08:05:12.61#ibcon#about to read 4, iclass 17, count 0 2006.190.08:05:12.61#ibcon#read 4, iclass 17, count 0 2006.190.08:05:12.61#ibcon#about to read 5, iclass 17, count 0 2006.190.08:05:12.61#ibcon#read 5, iclass 17, count 0 2006.190.08:05:12.61#ibcon#about to read 6, iclass 17, count 0 2006.190.08:05:12.61#ibcon#read 6, iclass 17, count 0 2006.190.08:05:12.61#ibcon#end of sib2, iclass 17, count 0 2006.190.08:05:12.61#ibcon#*after write, iclass 17, count 0 2006.190.08:05:12.61#ibcon#*before return 0, iclass 17, count 0 2006.190.08:05:12.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:12.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:05:12.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:05:12.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:05:12.61$vc4f8/vabw=wide 2006.190.08:05:12.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.08:05:12.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.08:05:12.61#ibcon#ireg 8 cls_cnt 0 2006.190.08:05:12.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:12.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:12.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:12.61#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:05:12.61#ibcon#first serial, iclass 19, count 0 2006.190.08:05:12.61#ibcon#enter sib2, iclass 19, count 0 2006.190.08:05:12.61#ibcon#flushed, iclass 19, count 0 2006.190.08:05:12.61#ibcon#about to write, iclass 19, count 0 2006.190.08:05:12.61#ibcon#wrote, iclass 19, count 0 2006.190.08:05:12.61#ibcon#about to read 3, iclass 19, count 0 2006.190.08:05:12.62#ibcon#read 3, iclass 19, count 0 2006.190.08:05:12.62#ibcon#about to read 4, iclass 19, count 0 2006.190.08:05:12.62#ibcon#read 4, iclass 19, count 0 2006.190.08:05:12.62#ibcon#about to read 5, iclass 19, count 0 2006.190.08:05:12.62#ibcon#read 5, iclass 19, count 0 2006.190.08:05:12.62#ibcon#about to read 6, iclass 19, count 0 2006.190.08:05:12.62#ibcon#read 6, iclass 19, count 0 2006.190.08:05:12.62#ibcon#end of sib2, iclass 19, count 0 2006.190.08:05:12.62#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:05:12.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:05:12.62#ibcon#[25=BW32\r\n] 2006.190.08:05:12.62#ibcon#*before write, iclass 19, count 0 2006.190.08:05:12.62#ibcon#enter sib2, iclass 19, count 0 2006.190.08:05:12.62#ibcon#flushed, iclass 19, count 0 2006.190.08:05:12.62#ibcon#about to write, iclass 19, count 0 2006.190.08:05:12.62#ibcon#wrote, iclass 19, count 0 2006.190.08:05:12.62#ibcon#about to read 3, iclass 19, count 0 2006.190.08:05:12.65#ibcon#read 3, iclass 19, count 0 2006.190.08:05:12.65#ibcon#about to read 4, iclass 19, count 0 2006.190.08:05:12.65#ibcon#read 4, iclass 19, count 0 2006.190.08:05:12.65#ibcon#about to read 5, iclass 19, count 0 2006.190.08:05:12.65#ibcon#read 5, iclass 19, count 0 2006.190.08:05:12.65#ibcon#about to read 6, iclass 19, count 0 2006.190.08:05:12.65#ibcon#read 6, iclass 19, count 0 2006.190.08:05:12.65#ibcon#end of sib2, iclass 19, count 0 2006.190.08:05:12.65#ibcon#*after write, iclass 19, count 0 2006.190.08:05:12.65#ibcon#*before return 0, iclass 19, count 0 2006.190.08:05:12.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:12.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:05:12.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:05:12.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:05:12.65$vc4f8/vbbw=wide 2006.190.08:05:12.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.08:05:12.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.08:05:12.65#ibcon#ireg 8 cls_cnt 0 2006.190.08:05:12.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:05:12.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:05:12.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:05:12.73#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:05:12.73#ibcon#first serial, iclass 21, count 0 2006.190.08:05:12.73#ibcon#enter sib2, iclass 21, count 0 2006.190.08:05:12.73#ibcon#flushed, iclass 21, count 0 2006.190.08:05:12.73#ibcon#about to write, iclass 21, count 0 2006.190.08:05:12.73#ibcon#wrote, iclass 21, count 0 2006.190.08:05:12.73#ibcon#about to read 3, iclass 21, count 0 2006.190.08:05:12.75#ibcon#read 3, iclass 21, count 0 2006.190.08:05:12.75#ibcon#about to read 4, iclass 21, count 0 2006.190.08:05:12.75#ibcon#read 4, iclass 21, count 0 2006.190.08:05:12.75#ibcon#about to read 5, iclass 21, count 0 2006.190.08:05:12.75#ibcon#read 5, iclass 21, count 0 2006.190.08:05:12.75#ibcon#about to read 6, iclass 21, count 0 2006.190.08:05:12.75#ibcon#read 6, iclass 21, count 0 2006.190.08:05:12.75#ibcon#end of sib2, iclass 21, count 0 2006.190.08:05:12.75#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:05:12.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:05:12.75#ibcon#[27=BW32\r\n] 2006.190.08:05:12.75#ibcon#*before write, iclass 21, count 0 2006.190.08:05:12.75#ibcon#enter sib2, iclass 21, count 0 2006.190.08:05:12.75#ibcon#flushed, iclass 21, count 0 2006.190.08:05:12.75#ibcon#about to write, iclass 21, count 0 2006.190.08:05:12.75#ibcon#wrote, iclass 21, count 0 2006.190.08:05:12.75#ibcon#about to read 3, iclass 21, count 0 2006.190.08:05:12.78#ibcon#read 3, iclass 21, count 0 2006.190.08:05:12.78#ibcon#about to read 4, iclass 21, count 0 2006.190.08:05:12.78#ibcon#read 4, iclass 21, count 0 2006.190.08:05:12.78#ibcon#about to read 5, iclass 21, count 0 2006.190.08:05:12.78#ibcon#read 5, iclass 21, count 0 2006.190.08:05:12.78#ibcon#about to read 6, iclass 21, count 0 2006.190.08:05:12.78#ibcon#read 6, iclass 21, count 0 2006.190.08:05:12.78#ibcon#end of sib2, iclass 21, count 0 2006.190.08:05:12.78#ibcon#*after write, iclass 21, count 0 2006.190.08:05:12.78#ibcon#*before return 0, iclass 21, count 0 2006.190.08:05:12.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:05:12.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:05:12.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:05:12.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:05:12.78$4f8m12a/ifd4f 2006.190.08:05:12.78$ifd4f/lo= 2006.190.08:05:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:05:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:05:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:05:12.78$ifd4f/patch= 2006.190.08:05:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:05:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:05:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:05:12.78$4f8m12a/"form=m,16.000,1:2 2006.190.08:05:12.78$4f8m12a/"tpicd 2006.190.08:05:12.78$4f8m12a/echo=off 2006.190.08:05:12.78$4f8m12a/xlog=off 2006.190.08:05:12.79:!2006.190.08:05:40 2006.190.08:05:19.14#trakl#Source acquired 2006.190.08:05:19.14#flagr#flagr/antenna,acquired 2006.190.08:05:40.01:preob 2006.190.08:05:41.14/onsource/TRACKING 2006.190.08:05:41.14:!2006.190.08:05:50 2006.190.08:05:50.00:data_valid=on 2006.190.08:05:50.00:midob 2006.190.08:05:50.14/onsource/TRACKING 2006.190.08:05:50.14/wx/24.46,1012.0,100 2006.190.08:05:50.22/cable/+6.4703E-03 2006.190.08:05:51.31/va/01,08,usb,yes,32,34 2006.190.08:05:51.31/va/02,07,usb,yes,32,34 2006.190.08:05:51.31/va/03,06,usb,yes,34,34 2006.190.08:05:51.31/va/04,07,usb,yes,33,36 2006.190.08:05:51.31/va/05,07,usb,yes,36,38 2006.190.08:05:51.31/va/06,06,usb,yes,35,35 2006.190.08:05:51.31/va/07,06,usb,yes,36,36 2006.190.08:05:51.31/va/08,06,usb,yes,38,38 2006.190.08:05:51.54/valo/01,532.99,yes,locked 2006.190.08:05:51.54/valo/02,572.99,yes,locked 2006.190.08:05:51.54/valo/03,672.99,yes,locked 2006.190.08:05:51.54/valo/04,832.99,yes,locked 2006.190.08:05:51.54/valo/05,652.99,yes,locked 2006.190.08:05:51.54/valo/06,772.99,yes,locked 2006.190.08:05:51.54/valo/07,832.99,yes,locked 2006.190.08:05:51.54/valo/08,852.99,yes,locked 2006.190.08:05:52.63/vb/01,04,usb,yes,29,28 2006.190.08:05:52.63/vb/02,04,usb,yes,31,32 2006.190.08:05:52.63/vb/03,04,usb,yes,28,31 2006.190.08:05:52.63/vb/04,04,usb,yes,28,28 2006.190.08:05:52.63/vb/05,04,usb,yes,27,31 2006.190.08:05:52.63/vb/06,04,usb,yes,28,31 2006.190.08:05:52.63/vb/07,04,usb,yes,30,30 2006.190.08:05:52.63/vb/08,04,usb,yes,27,31 2006.190.08:05:52.86/vblo/01,632.99,yes,locked 2006.190.08:05:52.86/vblo/02,640.99,yes,locked 2006.190.08:05:52.86/vblo/03,656.99,yes,locked 2006.190.08:05:52.86/vblo/04,712.99,yes,locked 2006.190.08:05:52.86/vblo/05,744.99,yes,locked 2006.190.08:05:52.86/vblo/06,752.99,yes,locked 2006.190.08:05:52.86/vblo/07,734.99,yes,locked 2006.190.08:05:52.86/vblo/08,744.99,yes,locked 2006.190.08:05:53.01/vabw/8 2006.190.08:05:53.16/vbbw/8 2006.190.08:05:53.25/xfe/off,on,14.5 2006.190.08:05:53.64/ifatt/23,28,28,28 2006.190.08:05:54.07/fmout-gps/S +2.84E-07 2006.190.08:05:54.16:!2006.190.08:06:50 2006.190.08:06:50.01:data_valid=off 2006.190.08:06:50.02:postob 2006.190.08:06:50.17/cable/+6.4719E-03 2006.190.08:06:50.18/wx/24.45,1012.0,100 2006.190.08:06:51.07/fmout-gps/S +2.83E-07 2006.190.08:06:51.08:scan_name=190-0808,k06190,110 2006.190.08:06:51.08:source=1004+141,100741.50,135629.6,2000.0,ccw 2006.190.08:06:51.14#flagr#flagr/antenna,new-source 2006.190.08:06:52.14:checkk5 2006.190.08:06:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:06:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:06:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:06:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:06:54.04/chk_obsdata//k5ts1/T1900805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:06:54.41/chk_obsdata//k5ts2/T1900805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:06:54.79/chk_obsdata//k5ts3/T1900805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:06:55.16/chk_obsdata//k5ts4/T1900805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:06:55.86/k5log//k5ts1_log_newline 2006.190.08:06:56.55/k5log//k5ts2_log_newline 2006.190.08:06:57.25/k5log//k5ts3_log_newline 2006.190.08:06:57.95/k5log//k5ts4_log_newline 2006.190.08:06:57.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:06:57.97:4f8m12a=2 2006.190.08:06:57.97$4f8m12a/echo=on 2006.190.08:06:57.97$4f8m12a/pcalon 2006.190.08:06:57.98$pcalon/"no phase cal control is implemented here 2006.190.08:06:57.98$4f8m12a/"tpicd=stop 2006.190.08:06:57.98$4f8m12a/vc4f8 2006.190.08:06:57.98$vc4f8/valo=1,532.99 2006.190.08:06:57.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.08:06:57.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.08:06:57.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:06:57.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:06:57.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:06:57.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:06:57.98#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:06:57.98#ibcon#first serial, iclass 32, count 0 2006.190.08:06:57.98#ibcon#enter sib2, iclass 32, count 0 2006.190.08:06:57.98#ibcon#flushed, iclass 32, count 0 2006.190.08:06:57.98#ibcon#about to write, iclass 32, count 0 2006.190.08:06:57.98#ibcon#wrote, iclass 32, count 0 2006.190.08:06:57.98#ibcon#about to read 3, iclass 32, count 0 2006.190.08:06:58.03#ibcon#read 3, iclass 32, count 0 2006.190.08:06:58.03#ibcon#about to read 4, iclass 32, count 0 2006.190.08:06:58.03#ibcon#read 4, iclass 32, count 0 2006.190.08:06:58.03#ibcon#about to read 5, iclass 32, count 0 2006.190.08:06:58.03#ibcon#read 5, iclass 32, count 0 2006.190.08:06:58.03#ibcon#about to read 6, iclass 32, count 0 2006.190.08:06:58.03#ibcon#read 6, iclass 32, count 0 2006.190.08:06:58.03#ibcon#end of sib2, iclass 32, count 0 2006.190.08:06:58.03#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:06:58.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:06:58.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:06:58.03#ibcon#*before write, iclass 32, count 0 2006.190.08:06:58.03#ibcon#enter sib2, iclass 32, count 0 2006.190.08:06:58.03#ibcon#flushed, iclass 32, count 0 2006.190.08:06:58.03#ibcon#about to write, iclass 32, count 0 2006.190.08:06:58.03#ibcon#wrote, iclass 32, count 0 2006.190.08:06:58.03#ibcon#about to read 3, iclass 32, count 0 2006.190.08:06:58.07#ibcon#read 3, iclass 32, count 0 2006.190.08:06:58.07#ibcon#about to read 4, iclass 32, count 0 2006.190.08:06:58.07#ibcon#read 4, iclass 32, count 0 2006.190.08:06:58.07#ibcon#about to read 5, iclass 32, count 0 2006.190.08:06:58.07#ibcon#read 5, iclass 32, count 0 2006.190.08:06:58.07#ibcon#about to read 6, iclass 32, count 0 2006.190.08:06:58.07#ibcon#read 6, iclass 32, count 0 2006.190.08:06:58.07#ibcon#end of sib2, iclass 32, count 0 2006.190.08:06:58.07#ibcon#*after write, iclass 32, count 0 2006.190.08:06:58.07#ibcon#*before return 0, iclass 32, count 0 2006.190.08:06:58.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:06:58.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:06:58.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:06:58.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:06:58.07$vc4f8/va=1,8 2006.190.08:06:58.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.08:06:58.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.08:06:58.07#ibcon#ireg 11 cls_cnt 2 2006.190.08:06:58.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:06:58.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:06:58.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:06:58.07#ibcon#enter wrdev, iclass 34, count 2 2006.190.08:06:58.07#ibcon#first serial, iclass 34, count 2 2006.190.08:06:58.07#ibcon#enter sib2, iclass 34, count 2 2006.190.08:06:58.07#ibcon#flushed, iclass 34, count 2 2006.190.08:06:58.07#ibcon#about to write, iclass 34, count 2 2006.190.08:06:58.07#ibcon#wrote, iclass 34, count 2 2006.190.08:06:58.07#ibcon#about to read 3, iclass 34, count 2 2006.190.08:06:58.09#ibcon#read 3, iclass 34, count 2 2006.190.08:06:58.09#ibcon#about to read 4, iclass 34, count 2 2006.190.08:06:58.09#ibcon#read 4, iclass 34, count 2 2006.190.08:06:58.09#ibcon#about to read 5, iclass 34, count 2 2006.190.08:06:58.09#ibcon#read 5, iclass 34, count 2 2006.190.08:06:58.09#ibcon#about to read 6, iclass 34, count 2 2006.190.08:06:58.09#ibcon#read 6, iclass 34, count 2 2006.190.08:06:58.09#ibcon#end of sib2, iclass 34, count 2 2006.190.08:06:58.09#ibcon#*mode == 0, iclass 34, count 2 2006.190.08:06:58.09#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.08:06:58.09#ibcon#[25=AT01-08\r\n] 2006.190.08:06:58.09#ibcon#*before write, iclass 34, count 2 2006.190.08:06:58.09#ibcon#enter sib2, iclass 34, count 2 2006.190.08:06:58.09#ibcon#flushed, iclass 34, count 2 2006.190.08:06:58.09#ibcon#about to write, iclass 34, count 2 2006.190.08:06:58.09#ibcon#wrote, iclass 34, count 2 2006.190.08:06:58.09#ibcon#about to read 3, iclass 34, count 2 2006.190.08:06:58.12#ibcon#read 3, iclass 34, count 2 2006.190.08:06:58.12#ibcon#about to read 4, iclass 34, count 2 2006.190.08:06:58.12#ibcon#read 4, iclass 34, count 2 2006.190.08:06:58.12#ibcon#about to read 5, iclass 34, count 2 2006.190.08:06:58.12#ibcon#read 5, iclass 34, count 2 2006.190.08:06:58.12#ibcon#about to read 6, iclass 34, count 2 2006.190.08:06:58.12#ibcon#read 6, iclass 34, count 2 2006.190.08:06:58.12#ibcon#end of sib2, iclass 34, count 2 2006.190.08:06:58.12#ibcon#*after write, iclass 34, count 2 2006.190.08:06:58.12#ibcon#*before return 0, iclass 34, count 2 2006.190.08:06:58.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:06:58.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:06:58.12#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.08:06:58.12#ibcon#ireg 7 cls_cnt 0 2006.190.08:06:58.12#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:06:58.24#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:06:58.24#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:06:58.24#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:06:58.24#ibcon#first serial, iclass 34, count 0 2006.190.08:06:58.24#ibcon#enter sib2, iclass 34, count 0 2006.190.08:06:58.24#ibcon#flushed, iclass 34, count 0 2006.190.08:06:58.24#ibcon#about to write, iclass 34, count 0 2006.190.08:06:58.24#ibcon#wrote, iclass 34, count 0 2006.190.08:06:58.24#ibcon#about to read 3, iclass 34, count 0 2006.190.08:06:58.26#ibcon#read 3, iclass 34, count 0 2006.190.08:06:58.26#ibcon#about to read 4, iclass 34, count 0 2006.190.08:06:58.26#ibcon#read 4, iclass 34, count 0 2006.190.08:06:58.26#ibcon#about to read 5, iclass 34, count 0 2006.190.08:06:58.26#ibcon#read 5, iclass 34, count 0 2006.190.08:06:58.26#ibcon#about to read 6, iclass 34, count 0 2006.190.08:06:58.26#ibcon#read 6, iclass 34, count 0 2006.190.08:06:58.26#ibcon#end of sib2, iclass 34, count 0 2006.190.08:06:58.26#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:06:58.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:06:58.26#ibcon#[25=USB\r\n] 2006.190.08:06:58.26#ibcon#*before write, iclass 34, count 0 2006.190.08:06:58.26#ibcon#enter sib2, iclass 34, count 0 2006.190.08:06:58.26#ibcon#flushed, iclass 34, count 0 2006.190.08:06:58.26#ibcon#about to write, iclass 34, count 0 2006.190.08:06:58.26#ibcon#wrote, iclass 34, count 0 2006.190.08:06:58.26#ibcon#about to read 3, iclass 34, count 0 2006.190.08:06:58.29#ibcon#read 3, iclass 34, count 0 2006.190.08:06:58.29#ibcon#about to read 4, iclass 34, count 0 2006.190.08:06:58.29#ibcon#read 4, iclass 34, count 0 2006.190.08:06:58.29#ibcon#about to read 5, iclass 34, count 0 2006.190.08:06:58.29#ibcon#read 5, iclass 34, count 0 2006.190.08:06:58.29#ibcon#about to read 6, iclass 34, count 0 2006.190.08:06:58.29#ibcon#read 6, iclass 34, count 0 2006.190.08:06:58.29#ibcon#end of sib2, iclass 34, count 0 2006.190.08:06:58.29#ibcon#*after write, iclass 34, count 0 2006.190.08:06:58.29#ibcon#*before return 0, iclass 34, count 0 2006.190.08:06:58.29#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:06:58.29#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:06:58.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:06:58.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:06:58.29$vc4f8/valo=2,572.99 2006.190.08:06:58.29#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.08:06:58.29#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.08:06:58.29#ibcon#ireg 17 cls_cnt 0 2006.190.08:06:58.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:06:58.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:06:58.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:06:58.29#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:06:58.29#ibcon#first serial, iclass 36, count 0 2006.190.08:06:58.29#ibcon#enter sib2, iclass 36, count 0 2006.190.08:06:58.29#ibcon#flushed, iclass 36, count 0 2006.190.08:06:58.29#ibcon#about to write, iclass 36, count 0 2006.190.08:06:58.29#ibcon#wrote, iclass 36, count 0 2006.190.08:06:58.29#ibcon#about to read 3, iclass 36, count 0 2006.190.08:06:58.31#ibcon#read 3, iclass 36, count 0 2006.190.08:06:58.31#ibcon#about to read 4, iclass 36, count 0 2006.190.08:06:58.31#ibcon#read 4, iclass 36, count 0 2006.190.08:06:58.31#ibcon#about to read 5, iclass 36, count 0 2006.190.08:06:58.31#ibcon#read 5, iclass 36, count 0 2006.190.08:06:58.31#ibcon#about to read 6, iclass 36, count 0 2006.190.08:06:58.31#ibcon#read 6, iclass 36, count 0 2006.190.08:06:58.31#ibcon#end of sib2, iclass 36, count 0 2006.190.08:06:58.31#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:06:58.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:06:58.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:06:58.31#ibcon#*before write, iclass 36, count 0 2006.190.08:06:58.31#ibcon#enter sib2, iclass 36, count 0 2006.190.08:06:58.31#ibcon#flushed, iclass 36, count 0 2006.190.08:06:58.31#ibcon#about to write, iclass 36, count 0 2006.190.08:06:58.31#ibcon#wrote, iclass 36, count 0 2006.190.08:06:58.31#ibcon#about to read 3, iclass 36, count 0 2006.190.08:06:58.36#ibcon#read 3, iclass 36, count 0 2006.190.08:06:58.36#ibcon#about to read 4, iclass 36, count 0 2006.190.08:06:58.36#ibcon#read 4, iclass 36, count 0 2006.190.08:06:58.36#ibcon#about to read 5, iclass 36, count 0 2006.190.08:06:58.36#ibcon#read 5, iclass 36, count 0 2006.190.08:06:58.36#ibcon#about to read 6, iclass 36, count 0 2006.190.08:06:58.36#ibcon#read 6, iclass 36, count 0 2006.190.08:06:58.36#ibcon#end of sib2, iclass 36, count 0 2006.190.08:06:58.36#ibcon#*after write, iclass 36, count 0 2006.190.08:06:58.36#ibcon#*before return 0, iclass 36, count 0 2006.190.08:06:58.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:06:58.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:06:58.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:06:58.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:06:58.36$vc4f8/va=2,7 2006.190.08:06:58.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.08:06:58.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.08:06:58.36#ibcon#ireg 11 cls_cnt 2 2006.190.08:06:58.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:06:58.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:06:58.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:06:58.40#ibcon#enter wrdev, iclass 38, count 2 2006.190.08:06:58.40#ibcon#first serial, iclass 38, count 2 2006.190.08:06:58.40#ibcon#enter sib2, iclass 38, count 2 2006.190.08:06:58.40#ibcon#flushed, iclass 38, count 2 2006.190.08:06:58.40#ibcon#about to write, iclass 38, count 2 2006.190.08:06:58.40#ibcon#wrote, iclass 38, count 2 2006.190.08:06:58.40#ibcon#about to read 3, iclass 38, count 2 2006.190.08:06:58.42#ibcon#read 3, iclass 38, count 2 2006.190.08:06:58.42#ibcon#about to read 4, iclass 38, count 2 2006.190.08:06:58.42#ibcon#read 4, iclass 38, count 2 2006.190.08:06:58.42#ibcon#about to read 5, iclass 38, count 2 2006.190.08:06:58.42#ibcon#read 5, iclass 38, count 2 2006.190.08:06:58.42#ibcon#about to read 6, iclass 38, count 2 2006.190.08:06:58.42#ibcon#read 6, iclass 38, count 2 2006.190.08:06:58.42#ibcon#end of sib2, iclass 38, count 2 2006.190.08:06:58.42#ibcon#*mode == 0, iclass 38, count 2 2006.190.08:06:58.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.08:06:58.42#ibcon#[25=AT02-07\r\n] 2006.190.08:06:58.42#ibcon#*before write, iclass 38, count 2 2006.190.08:06:58.42#ibcon#enter sib2, iclass 38, count 2 2006.190.08:06:58.42#ibcon#flushed, iclass 38, count 2 2006.190.08:06:58.42#ibcon#about to write, iclass 38, count 2 2006.190.08:06:58.42#ibcon#wrote, iclass 38, count 2 2006.190.08:06:58.42#ibcon#about to read 3, iclass 38, count 2 2006.190.08:06:58.45#ibcon#read 3, iclass 38, count 2 2006.190.08:06:58.45#ibcon#about to read 4, iclass 38, count 2 2006.190.08:06:58.45#ibcon#read 4, iclass 38, count 2 2006.190.08:06:58.45#ibcon#about to read 5, iclass 38, count 2 2006.190.08:06:58.45#ibcon#read 5, iclass 38, count 2 2006.190.08:06:58.45#ibcon#about to read 6, iclass 38, count 2 2006.190.08:06:58.45#ibcon#read 6, iclass 38, count 2 2006.190.08:06:58.45#ibcon#end of sib2, iclass 38, count 2 2006.190.08:06:58.45#ibcon#*after write, iclass 38, count 2 2006.190.08:06:58.45#ibcon#*before return 0, iclass 38, count 2 2006.190.08:06:58.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:06:58.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:06:58.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.08:06:58.45#ibcon#ireg 7 cls_cnt 0 2006.190.08:06:58.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:06:58.58#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:06:58.58#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:06:58.58#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:06:58.58#ibcon#first serial, iclass 38, count 0 2006.190.08:06:58.58#ibcon#enter sib2, iclass 38, count 0 2006.190.08:06:58.58#ibcon#flushed, iclass 38, count 0 2006.190.08:06:58.58#ibcon#about to write, iclass 38, count 0 2006.190.08:06:58.58#ibcon#wrote, iclass 38, count 0 2006.190.08:06:58.58#ibcon#about to read 3, iclass 38, count 0 2006.190.08:06:58.59#ibcon#read 3, iclass 38, count 0 2006.190.08:06:58.59#ibcon#about to read 4, iclass 38, count 0 2006.190.08:06:58.59#ibcon#read 4, iclass 38, count 0 2006.190.08:06:58.59#ibcon#about to read 5, iclass 38, count 0 2006.190.08:06:58.59#ibcon#read 5, iclass 38, count 0 2006.190.08:06:58.59#ibcon#about to read 6, iclass 38, count 0 2006.190.08:06:58.59#ibcon#read 6, iclass 38, count 0 2006.190.08:06:58.59#ibcon#end of sib2, iclass 38, count 0 2006.190.08:06:58.59#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:06:58.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:06:58.59#ibcon#[25=USB\r\n] 2006.190.08:06:58.59#ibcon#*before write, iclass 38, count 0 2006.190.08:06:58.59#ibcon#enter sib2, iclass 38, count 0 2006.190.08:06:58.59#ibcon#flushed, iclass 38, count 0 2006.190.08:06:58.59#ibcon#about to write, iclass 38, count 0 2006.190.08:06:58.59#ibcon#wrote, iclass 38, count 0 2006.190.08:06:58.59#ibcon#about to read 3, iclass 38, count 0 2006.190.08:06:58.62#ibcon#read 3, iclass 38, count 0 2006.190.08:06:58.62#ibcon#about to read 4, iclass 38, count 0 2006.190.08:06:58.62#ibcon#read 4, iclass 38, count 0 2006.190.08:06:58.62#ibcon#about to read 5, iclass 38, count 0 2006.190.08:06:58.62#ibcon#read 5, iclass 38, count 0 2006.190.08:06:58.62#ibcon#about to read 6, iclass 38, count 0 2006.190.08:06:58.62#ibcon#read 6, iclass 38, count 0 2006.190.08:06:58.62#ibcon#end of sib2, iclass 38, count 0 2006.190.08:06:58.62#ibcon#*after write, iclass 38, count 0 2006.190.08:06:58.62#ibcon#*before return 0, iclass 38, count 0 2006.190.08:06:58.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:06:58.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:06:58.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:06:58.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:06:58.62$vc4f8/valo=3,672.99 2006.190.08:06:58.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.08:06:58.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.08:06:58.62#ibcon#ireg 17 cls_cnt 0 2006.190.08:06:58.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:06:58.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:06:58.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:06:58.62#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:06:58.62#ibcon#first serial, iclass 40, count 0 2006.190.08:06:58.62#ibcon#enter sib2, iclass 40, count 0 2006.190.08:06:58.62#ibcon#flushed, iclass 40, count 0 2006.190.08:06:58.62#ibcon#about to write, iclass 40, count 0 2006.190.08:06:58.62#ibcon#wrote, iclass 40, count 0 2006.190.08:06:58.62#ibcon#about to read 3, iclass 40, count 0 2006.190.08:06:58.64#ibcon#read 3, iclass 40, count 0 2006.190.08:06:58.64#ibcon#about to read 4, iclass 40, count 0 2006.190.08:06:58.64#ibcon#read 4, iclass 40, count 0 2006.190.08:06:58.64#ibcon#about to read 5, iclass 40, count 0 2006.190.08:06:58.64#ibcon#read 5, iclass 40, count 0 2006.190.08:06:58.64#ibcon#about to read 6, iclass 40, count 0 2006.190.08:06:58.64#ibcon#read 6, iclass 40, count 0 2006.190.08:06:58.64#ibcon#end of sib2, iclass 40, count 0 2006.190.08:06:58.64#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:06:58.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:06:58.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:06:58.64#ibcon#*before write, iclass 40, count 0 2006.190.08:06:58.64#ibcon#enter sib2, iclass 40, count 0 2006.190.08:06:58.64#ibcon#flushed, iclass 40, count 0 2006.190.08:06:58.64#ibcon#about to write, iclass 40, count 0 2006.190.08:06:58.64#ibcon#wrote, iclass 40, count 0 2006.190.08:06:58.64#ibcon#about to read 3, iclass 40, count 0 2006.190.08:06:58.68#ibcon#read 3, iclass 40, count 0 2006.190.08:06:58.68#ibcon#about to read 4, iclass 40, count 0 2006.190.08:06:58.69#ibcon#read 4, iclass 40, count 0 2006.190.08:06:58.69#ibcon#about to read 5, iclass 40, count 0 2006.190.08:06:58.69#ibcon#read 5, iclass 40, count 0 2006.190.08:06:58.69#ibcon#about to read 6, iclass 40, count 0 2006.190.08:06:58.69#ibcon#read 6, iclass 40, count 0 2006.190.08:06:58.69#ibcon#end of sib2, iclass 40, count 0 2006.190.08:06:58.69#ibcon#*after write, iclass 40, count 0 2006.190.08:06:58.69#ibcon#*before return 0, iclass 40, count 0 2006.190.08:06:58.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:06:58.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:06:58.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:06:58.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:06:58.69$vc4f8/va=3,6 2006.190.08:06:58.69#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.08:06:58.69#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.08:06:58.69#ibcon#ireg 11 cls_cnt 2 2006.190.08:06:58.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:06:58.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:06:58.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:06:58.73#ibcon#enter wrdev, iclass 4, count 2 2006.190.08:06:58.73#ibcon#first serial, iclass 4, count 2 2006.190.08:06:58.73#ibcon#enter sib2, iclass 4, count 2 2006.190.08:06:58.73#ibcon#flushed, iclass 4, count 2 2006.190.08:06:58.73#ibcon#about to write, iclass 4, count 2 2006.190.08:06:58.73#ibcon#wrote, iclass 4, count 2 2006.190.08:06:58.73#ibcon#about to read 3, iclass 4, count 2 2006.190.08:06:58.75#ibcon#read 3, iclass 4, count 2 2006.190.08:06:58.75#ibcon#about to read 4, iclass 4, count 2 2006.190.08:06:58.75#ibcon#read 4, iclass 4, count 2 2006.190.08:06:58.75#ibcon#about to read 5, iclass 4, count 2 2006.190.08:06:58.75#ibcon#read 5, iclass 4, count 2 2006.190.08:06:58.75#ibcon#about to read 6, iclass 4, count 2 2006.190.08:06:58.75#ibcon#read 6, iclass 4, count 2 2006.190.08:06:58.75#ibcon#end of sib2, iclass 4, count 2 2006.190.08:06:58.75#ibcon#*mode == 0, iclass 4, count 2 2006.190.08:06:58.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.08:06:58.75#ibcon#[25=AT03-06\r\n] 2006.190.08:06:58.75#ibcon#*before write, iclass 4, count 2 2006.190.08:06:58.75#ibcon#enter sib2, iclass 4, count 2 2006.190.08:06:58.75#ibcon#flushed, iclass 4, count 2 2006.190.08:06:58.75#ibcon#about to write, iclass 4, count 2 2006.190.08:06:58.75#ibcon#wrote, iclass 4, count 2 2006.190.08:06:58.75#ibcon#about to read 3, iclass 4, count 2 2006.190.08:06:58.78#ibcon#read 3, iclass 4, count 2 2006.190.08:06:58.78#ibcon#about to read 4, iclass 4, count 2 2006.190.08:06:58.78#ibcon#read 4, iclass 4, count 2 2006.190.08:06:58.78#ibcon#about to read 5, iclass 4, count 2 2006.190.08:06:58.78#ibcon#read 5, iclass 4, count 2 2006.190.08:06:58.78#ibcon#about to read 6, iclass 4, count 2 2006.190.08:06:58.78#ibcon#read 6, iclass 4, count 2 2006.190.08:06:58.78#ibcon#end of sib2, iclass 4, count 2 2006.190.08:06:58.78#ibcon#*after write, iclass 4, count 2 2006.190.08:06:58.78#ibcon#*before return 0, iclass 4, count 2 2006.190.08:06:58.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:06:58.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:06:58.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.08:06:58.78#ibcon#ireg 7 cls_cnt 0 2006.190.08:06:58.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:06:58.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:06:58.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:06:58.90#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:06:58.90#ibcon#first serial, iclass 4, count 0 2006.190.08:06:58.90#ibcon#enter sib2, iclass 4, count 0 2006.190.08:06:58.90#ibcon#flushed, iclass 4, count 0 2006.190.08:06:58.90#ibcon#about to write, iclass 4, count 0 2006.190.08:06:58.90#ibcon#wrote, iclass 4, count 0 2006.190.08:06:58.90#ibcon#about to read 3, iclass 4, count 0 2006.190.08:06:58.92#ibcon#read 3, iclass 4, count 0 2006.190.08:06:58.92#ibcon#about to read 4, iclass 4, count 0 2006.190.08:06:58.92#ibcon#read 4, iclass 4, count 0 2006.190.08:06:58.92#ibcon#about to read 5, iclass 4, count 0 2006.190.08:06:58.92#ibcon#read 5, iclass 4, count 0 2006.190.08:06:58.92#ibcon#about to read 6, iclass 4, count 0 2006.190.08:06:58.92#ibcon#read 6, iclass 4, count 0 2006.190.08:06:58.92#ibcon#end of sib2, iclass 4, count 0 2006.190.08:06:58.92#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:06:58.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:06:58.92#ibcon#[25=USB\r\n] 2006.190.08:06:58.92#ibcon#*before write, iclass 4, count 0 2006.190.08:06:58.92#ibcon#enter sib2, iclass 4, count 0 2006.190.08:06:58.92#ibcon#flushed, iclass 4, count 0 2006.190.08:06:58.92#ibcon#about to write, iclass 4, count 0 2006.190.08:06:58.92#ibcon#wrote, iclass 4, count 0 2006.190.08:06:58.92#ibcon#about to read 3, iclass 4, count 0 2006.190.08:06:58.95#ibcon#read 3, iclass 4, count 0 2006.190.08:06:58.95#ibcon#about to read 4, iclass 4, count 0 2006.190.08:06:58.95#ibcon#read 4, iclass 4, count 0 2006.190.08:06:58.95#ibcon#about to read 5, iclass 4, count 0 2006.190.08:06:58.95#ibcon#read 5, iclass 4, count 0 2006.190.08:06:58.95#ibcon#about to read 6, iclass 4, count 0 2006.190.08:06:58.95#ibcon#read 6, iclass 4, count 0 2006.190.08:06:58.95#ibcon#end of sib2, iclass 4, count 0 2006.190.08:06:58.95#ibcon#*after write, iclass 4, count 0 2006.190.08:06:58.95#ibcon#*before return 0, iclass 4, count 0 2006.190.08:06:58.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:06:58.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:06:58.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:06:58.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:06:58.95$vc4f8/valo=4,832.99 2006.190.08:06:58.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:06:58.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:06:58.95#ibcon#ireg 17 cls_cnt 0 2006.190.08:06:58.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:06:58.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:06:58.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:06:58.95#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:06:58.95#ibcon#first serial, iclass 6, count 0 2006.190.08:06:58.95#ibcon#enter sib2, iclass 6, count 0 2006.190.08:06:58.95#ibcon#flushed, iclass 6, count 0 2006.190.08:06:58.95#ibcon#about to write, iclass 6, count 0 2006.190.08:06:58.95#ibcon#wrote, iclass 6, count 0 2006.190.08:06:58.95#ibcon#about to read 3, iclass 6, count 0 2006.190.08:06:58.97#ibcon#read 3, iclass 6, count 0 2006.190.08:06:58.97#ibcon#about to read 4, iclass 6, count 0 2006.190.08:06:58.97#ibcon#read 4, iclass 6, count 0 2006.190.08:06:58.97#ibcon#about to read 5, iclass 6, count 0 2006.190.08:06:58.97#ibcon#read 5, iclass 6, count 0 2006.190.08:06:58.97#ibcon#about to read 6, iclass 6, count 0 2006.190.08:06:58.97#ibcon#read 6, iclass 6, count 0 2006.190.08:06:58.97#ibcon#end of sib2, iclass 6, count 0 2006.190.08:06:58.97#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:06:58.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:06:58.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:06:58.97#ibcon#*before write, iclass 6, count 0 2006.190.08:06:58.97#ibcon#enter sib2, iclass 6, count 0 2006.190.08:06:58.97#ibcon#flushed, iclass 6, count 0 2006.190.08:06:58.97#ibcon#about to write, iclass 6, count 0 2006.190.08:06:58.97#ibcon#wrote, iclass 6, count 0 2006.190.08:06:58.97#ibcon#about to read 3, iclass 6, count 0 2006.190.08:06:59.01#ibcon#read 3, iclass 6, count 0 2006.190.08:06:59.01#ibcon#about to read 4, iclass 6, count 0 2006.190.08:06:59.01#ibcon#read 4, iclass 6, count 0 2006.190.08:06:59.01#ibcon#about to read 5, iclass 6, count 0 2006.190.08:06:59.01#ibcon#read 5, iclass 6, count 0 2006.190.08:06:59.01#ibcon#about to read 6, iclass 6, count 0 2006.190.08:06:59.01#ibcon#read 6, iclass 6, count 0 2006.190.08:06:59.01#ibcon#end of sib2, iclass 6, count 0 2006.190.08:06:59.01#ibcon#*after write, iclass 6, count 0 2006.190.08:06:59.01#ibcon#*before return 0, iclass 6, count 0 2006.190.08:06:59.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:06:59.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:06:59.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:06:59.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:06:59.01$vc4f8/va=4,7 2006.190.08:06:59.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.08:06:59.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.08:06:59.01#ibcon#ireg 11 cls_cnt 2 2006.190.08:06:59.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:06:59.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:06:59.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:06:59.07#ibcon#enter wrdev, iclass 10, count 2 2006.190.08:06:59.07#ibcon#first serial, iclass 10, count 2 2006.190.08:06:59.07#ibcon#enter sib2, iclass 10, count 2 2006.190.08:06:59.07#ibcon#flushed, iclass 10, count 2 2006.190.08:06:59.07#ibcon#about to write, iclass 10, count 2 2006.190.08:06:59.07#ibcon#wrote, iclass 10, count 2 2006.190.08:06:59.07#ibcon#about to read 3, iclass 10, count 2 2006.190.08:06:59.09#ibcon#read 3, iclass 10, count 2 2006.190.08:06:59.09#ibcon#about to read 4, iclass 10, count 2 2006.190.08:06:59.09#ibcon#read 4, iclass 10, count 2 2006.190.08:06:59.09#ibcon#about to read 5, iclass 10, count 2 2006.190.08:06:59.09#ibcon#read 5, iclass 10, count 2 2006.190.08:06:59.09#ibcon#about to read 6, iclass 10, count 2 2006.190.08:06:59.09#ibcon#read 6, iclass 10, count 2 2006.190.08:06:59.09#ibcon#end of sib2, iclass 10, count 2 2006.190.08:06:59.09#ibcon#*mode == 0, iclass 10, count 2 2006.190.08:06:59.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.08:06:59.09#ibcon#[25=AT04-07\r\n] 2006.190.08:06:59.09#ibcon#*before write, iclass 10, count 2 2006.190.08:06:59.09#ibcon#enter sib2, iclass 10, count 2 2006.190.08:06:59.09#ibcon#flushed, iclass 10, count 2 2006.190.08:06:59.09#ibcon#about to write, iclass 10, count 2 2006.190.08:06:59.09#ibcon#wrote, iclass 10, count 2 2006.190.08:06:59.09#ibcon#about to read 3, iclass 10, count 2 2006.190.08:06:59.12#ibcon#read 3, iclass 10, count 2 2006.190.08:06:59.12#ibcon#about to read 4, iclass 10, count 2 2006.190.08:06:59.12#ibcon#read 4, iclass 10, count 2 2006.190.08:06:59.12#ibcon#about to read 5, iclass 10, count 2 2006.190.08:06:59.12#ibcon#read 5, iclass 10, count 2 2006.190.08:06:59.12#ibcon#about to read 6, iclass 10, count 2 2006.190.08:06:59.12#ibcon#read 6, iclass 10, count 2 2006.190.08:06:59.12#ibcon#end of sib2, iclass 10, count 2 2006.190.08:06:59.12#ibcon#*after write, iclass 10, count 2 2006.190.08:06:59.12#ibcon#*before return 0, iclass 10, count 2 2006.190.08:06:59.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:06:59.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:06:59.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.08:06:59.12#ibcon#ireg 7 cls_cnt 0 2006.190.08:06:59.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:06:59.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:06:59.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:06:59.24#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:06:59.24#ibcon#first serial, iclass 10, count 0 2006.190.08:06:59.24#ibcon#enter sib2, iclass 10, count 0 2006.190.08:06:59.24#ibcon#flushed, iclass 10, count 0 2006.190.08:06:59.24#ibcon#about to write, iclass 10, count 0 2006.190.08:06:59.24#ibcon#wrote, iclass 10, count 0 2006.190.08:06:59.24#ibcon#about to read 3, iclass 10, count 0 2006.190.08:06:59.26#ibcon#read 3, iclass 10, count 0 2006.190.08:06:59.26#ibcon#about to read 4, iclass 10, count 0 2006.190.08:06:59.26#ibcon#read 4, iclass 10, count 0 2006.190.08:06:59.26#ibcon#about to read 5, iclass 10, count 0 2006.190.08:06:59.26#ibcon#read 5, iclass 10, count 0 2006.190.08:06:59.26#ibcon#about to read 6, iclass 10, count 0 2006.190.08:06:59.26#ibcon#read 6, iclass 10, count 0 2006.190.08:06:59.26#ibcon#end of sib2, iclass 10, count 0 2006.190.08:06:59.26#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:06:59.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:06:59.26#ibcon#[25=USB\r\n] 2006.190.08:06:59.26#ibcon#*before write, iclass 10, count 0 2006.190.08:06:59.26#ibcon#enter sib2, iclass 10, count 0 2006.190.08:06:59.26#ibcon#flushed, iclass 10, count 0 2006.190.08:06:59.26#ibcon#about to write, iclass 10, count 0 2006.190.08:06:59.26#ibcon#wrote, iclass 10, count 0 2006.190.08:06:59.26#ibcon#about to read 3, iclass 10, count 0 2006.190.08:06:59.29#ibcon#read 3, iclass 10, count 0 2006.190.08:06:59.29#ibcon#about to read 4, iclass 10, count 0 2006.190.08:06:59.29#ibcon#read 4, iclass 10, count 0 2006.190.08:06:59.29#ibcon#about to read 5, iclass 10, count 0 2006.190.08:06:59.29#ibcon#read 5, iclass 10, count 0 2006.190.08:06:59.29#ibcon#about to read 6, iclass 10, count 0 2006.190.08:06:59.29#ibcon#read 6, iclass 10, count 0 2006.190.08:06:59.29#ibcon#end of sib2, iclass 10, count 0 2006.190.08:06:59.29#ibcon#*after write, iclass 10, count 0 2006.190.08:06:59.29#ibcon#*before return 0, iclass 10, count 0 2006.190.08:06:59.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:06:59.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:06:59.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:06:59.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:06:59.29$vc4f8/valo=5,652.99 2006.190.08:06:59.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:06:59.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:06:59.29#ibcon#ireg 17 cls_cnt 0 2006.190.08:06:59.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:06:59.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:06:59.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:06:59.29#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:06:59.29#ibcon#first serial, iclass 12, count 0 2006.190.08:06:59.29#ibcon#enter sib2, iclass 12, count 0 2006.190.08:06:59.29#ibcon#flushed, iclass 12, count 0 2006.190.08:06:59.29#ibcon#about to write, iclass 12, count 0 2006.190.08:06:59.29#ibcon#wrote, iclass 12, count 0 2006.190.08:06:59.29#ibcon#about to read 3, iclass 12, count 0 2006.190.08:06:59.31#ibcon#read 3, iclass 12, count 0 2006.190.08:06:59.31#ibcon#about to read 4, iclass 12, count 0 2006.190.08:06:59.31#ibcon#read 4, iclass 12, count 0 2006.190.08:06:59.31#ibcon#about to read 5, iclass 12, count 0 2006.190.08:06:59.31#ibcon#read 5, iclass 12, count 0 2006.190.08:06:59.31#ibcon#about to read 6, iclass 12, count 0 2006.190.08:06:59.31#ibcon#read 6, iclass 12, count 0 2006.190.08:06:59.31#ibcon#end of sib2, iclass 12, count 0 2006.190.08:06:59.31#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:06:59.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:06:59.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:06:59.31#ibcon#*before write, iclass 12, count 0 2006.190.08:06:59.31#ibcon#enter sib2, iclass 12, count 0 2006.190.08:06:59.31#ibcon#flushed, iclass 12, count 0 2006.190.08:06:59.31#ibcon#about to write, iclass 12, count 0 2006.190.08:06:59.31#ibcon#wrote, iclass 12, count 0 2006.190.08:06:59.31#ibcon#about to read 3, iclass 12, count 0 2006.190.08:06:59.35#ibcon#read 3, iclass 12, count 0 2006.190.08:06:59.35#ibcon#about to read 4, iclass 12, count 0 2006.190.08:06:59.35#ibcon#read 4, iclass 12, count 0 2006.190.08:06:59.35#ibcon#about to read 5, iclass 12, count 0 2006.190.08:06:59.35#ibcon#read 5, iclass 12, count 0 2006.190.08:06:59.35#ibcon#about to read 6, iclass 12, count 0 2006.190.08:06:59.35#ibcon#read 6, iclass 12, count 0 2006.190.08:06:59.35#ibcon#end of sib2, iclass 12, count 0 2006.190.08:06:59.35#ibcon#*after write, iclass 12, count 0 2006.190.08:06:59.35#ibcon#*before return 0, iclass 12, count 0 2006.190.08:06:59.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:06:59.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:06:59.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:06:59.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:06:59.35$vc4f8/va=5,7 2006.190.08:06:59.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:06:59.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:06:59.35#ibcon#ireg 11 cls_cnt 2 2006.190.08:06:59.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:06:59.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:06:59.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:06:59.41#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:06:59.41#ibcon#first serial, iclass 14, count 2 2006.190.08:06:59.41#ibcon#enter sib2, iclass 14, count 2 2006.190.08:06:59.41#ibcon#flushed, iclass 14, count 2 2006.190.08:06:59.41#ibcon#about to write, iclass 14, count 2 2006.190.08:06:59.41#ibcon#wrote, iclass 14, count 2 2006.190.08:06:59.41#ibcon#about to read 3, iclass 14, count 2 2006.190.08:06:59.43#ibcon#read 3, iclass 14, count 2 2006.190.08:06:59.43#ibcon#about to read 4, iclass 14, count 2 2006.190.08:06:59.43#ibcon#read 4, iclass 14, count 2 2006.190.08:06:59.43#ibcon#about to read 5, iclass 14, count 2 2006.190.08:06:59.43#ibcon#read 5, iclass 14, count 2 2006.190.08:06:59.43#ibcon#about to read 6, iclass 14, count 2 2006.190.08:06:59.43#ibcon#read 6, iclass 14, count 2 2006.190.08:06:59.43#ibcon#end of sib2, iclass 14, count 2 2006.190.08:06:59.43#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:06:59.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:06:59.43#ibcon#[25=AT05-07\r\n] 2006.190.08:06:59.43#ibcon#*before write, iclass 14, count 2 2006.190.08:06:59.43#ibcon#enter sib2, iclass 14, count 2 2006.190.08:06:59.43#ibcon#flushed, iclass 14, count 2 2006.190.08:06:59.43#ibcon#about to write, iclass 14, count 2 2006.190.08:06:59.43#ibcon#wrote, iclass 14, count 2 2006.190.08:06:59.43#ibcon#about to read 3, iclass 14, count 2 2006.190.08:06:59.46#ibcon#read 3, iclass 14, count 2 2006.190.08:06:59.46#ibcon#about to read 4, iclass 14, count 2 2006.190.08:06:59.46#ibcon#read 4, iclass 14, count 2 2006.190.08:06:59.46#ibcon#about to read 5, iclass 14, count 2 2006.190.08:06:59.46#ibcon#read 5, iclass 14, count 2 2006.190.08:06:59.46#ibcon#about to read 6, iclass 14, count 2 2006.190.08:06:59.46#ibcon#read 6, iclass 14, count 2 2006.190.08:06:59.46#ibcon#end of sib2, iclass 14, count 2 2006.190.08:06:59.46#ibcon#*after write, iclass 14, count 2 2006.190.08:06:59.46#ibcon#*before return 0, iclass 14, count 2 2006.190.08:06:59.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:06:59.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:06:59.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:06:59.46#ibcon#ireg 7 cls_cnt 0 2006.190.08:06:59.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:06:59.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:06:59.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:06:59.58#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:06:59.58#ibcon#first serial, iclass 14, count 0 2006.190.08:06:59.58#ibcon#enter sib2, iclass 14, count 0 2006.190.08:06:59.58#ibcon#flushed, iclass 14, count 0 2006.190.08:06:59.58#ibcon#about to write, iclass 14, count 0 2006.190.08:06:59.58#ibcon#wrote, iclass 14, count 0 2006.190.08:06:59.58#ibcon#about to read 3, iclass 14, count 0 2006.190.08:06:59.60#ibcon#read 3, iclass 14, count 0 2006.190.08:06:59.60#ibcon#about to read 4, iclass 14, count 0 2006.190.08:06:59.60#ibcon#read 4, iclass 14, count 0 2006.190.08:06:59.60#ibcon#about to read 5, iclass 14, count 0 2006.190.08:06:59.60#ibcon#read 5, iclass 14, count 0 2006.190.08:06:59.60#ibcon#about to read 6, iclass 14, count 0 2006.190.08:06:59.60#ibcon#read 6, iclass 14, count 0 2006.190.08:06:59.60#ibcon#end of sib2, iclass 14, count 0 2006.190.08:06:59.60#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:06:59.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:06:59.60#ibcon#[25=USB\r\n] 2006.190.08:06:59.60#ibcon#*before write, iclass 14, count 0 2006.190.08:06:59.60#ibcon#enter sib2, iclass 14, count 0 2006.190.08:06:59.60#ibcon#flushed, iclass 14, count 0 2006.190.08:06:59.60#ibcon#about to write, iclass 14, count 0 2006.190.08:06:59.60#ibcon#wrote, iclass 14, count 0 2006.190.08:06:59.60#ibcon#about to read 3, iclass 14, count 0 2006.190.08:06:59.63#ibcon#read 3, iclass 14, count 0 2006.190.08:06:59.63#ibcon#about to read 4, iclass 14, count 0 2006.190.08:06:59.63#ibcon#read 4, iclass 14, count 0 2006.190.08:06:59.63#ibcon#about to read 5, iclass 14, count 0 2006.190.08:06:59.63#ibcon#read 5, iclass 14, count 0 2006.190.08:06:59.63#ibcon#about to read 6, iclass 14, count 0 2006.190.08:06:59.63#ibcon#read 6, iclass 14, count 0 2006.190.08:06:59.63#ibcon#end of sib2, iclass 14, count 0 2006.190.08:06:59.63#ibcon#*after write, iclass 14, count 0 2006.190.08:06:59.63#ibcon#*before return 0, iclass 14, count 0 2006.190.08:06:59.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:06:59.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:06:59.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:06:59.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:06:59.63$vc4f8/valo=6,772.99 2006.190.08:06:59.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:06:59.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:06:59.63#ibcon#ireg 17 cls_cnt 0 2006.190.08:06:59.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:06:59.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:06:59.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:06:59.63#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:06:59.63#ibcon#first serial, iclass 16, count 0 2006.190.08:06:59.63#ibcon#enter sib2, iclass 16, count 0 2006.190.08:06:59.63#ibcon#flushed, iclass 16, count 0 2006.190.08:06:59.63#ibcon#about to write, iclass 16, count 0 2006.190.08:06:59.63#ibcon#wrote, iclass 16, count 0 2006.190.08:06:59.63#ibcon#about to read 3, iclass 16, count 0 2006.190.08:06:59.65#ibcon#read 3, iclass 16, count 0 2006.190.08:06:59.65#ibcon#about to read 4, iclass 16, count 0 2006.190.08:06:59.65#ibcon#read 4, iclass 16, count 0 2006.190.08:06:59.65#ibcon#about to read 5, iclass 16, count 0 2006.190.08:06:59.65#ibcon#read 5, iclass 16, count 0 2006.190.08:06:59.65#ibcon#about to read 6, iclass 16, count 0 2006.190.08:06:59.65#ibcon#read 6, iclass 16, count 0 2006.190.08:06:59.65#ibcon#end of sib2, iclass 16, count 0 2006.190.08:06:59.65#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:06:59.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:06:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:06:59.65#ibcon#*before write, iclass 16, count 0 2006.190.08:06:59.65#ibcon#enter sib2, iclass 16, count 0 2006.190.08:06:59.65#ibcon#flushed, iclass 16, count 0 2006.190.08:06:59.65#ibcon#about to write, iclass 16, count 0 2006.190.08:06:59.65#ibcon#wrote, iclass 16, count 0 2006.190.08:06:59.65#ibcon#about to read 3, iclass 16, count 0 2006.190.08:06:59.69#ibcon#read 3, iclass 16, count 0 2006.190.08:06:59.69#ibcon#about to read 4, iclass 16, count 0 2006.190.08:06:59.69#ibcon#read 4, iclass 16, count 0 2006.190.08:06:59.69#ibcon#about to read 5, iclass 16, count 0 2006.190.08:06:59.69#ibcon#read 5, iclass 16, count 0 2006.190.08:06:59.69#ibcon#about to read 6, iclass 16, count 0 2006.190.08:06:59.69#ibcon#read 6, iclass 16, count 0 2006.190.08:06:59.69#ibcon#end of sib2, iclass 16, count 0 2006.190.08:06:59.69#ibcon#*after write, iclass 16, count 0 2006.190.08:06:59.69#ibcon#*before return 0, iclass 16, count 0 2006.190.08:06:59.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:06:59.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:06:59.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:06:59.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:06:59.69$vc4f8/va=6,6 2006.190.08:06:59.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.08:06:59.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.08:06:59.69#ibcon#ireg 11 cls_cnt 2 2006.190.08:06:59.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:06:59.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:06:59.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:06:59.75#ibcon#enter wrdev, iclass 18, count 2 2006.190.08:06:59.75#ibcon#first serial, iclass 18, count 2 2006.190.08:06:59.75#ibcon#enter sib2, iclass 18, count 2 2006.190.08:06:59.75#ibcon#flushed, iclass 18, count 2 2006.190.08:06:59.75#ibcon#about to write, iclass 18, count 2 2006.190.08:06:59.75#ibcon#wrote, iclass 18, count 2 2006.190.08:06:59.75#ibcon#about to read 3, iclass 18, count 2 2006.190.08:06:59.77#ibcon#read 3, iclass 18, count 2 2006.190.08:06:59.77#ibcon#about to read 4, iclass 18, count 2 2006.190.08:06:59.77#ibcon#read 4, iclass 18, count 2 2006.190.08:06:59.77#ibcon#about to read 5, iclass 18, count 2 2006.190.08:06:59.77#ibcon#read 5, iclass 18, count 2 2006.190.08:06:59.77#ibcon#about to read 6, iclass 18, count 2 2006.190.08:06:59.77#ibcon#read 6, iclass 18, count 2 2006.190.08:06:59.77#ibcon#end of sib2, iclass 18, count 2 2006.190.08:06:59.77#ibcon#*mode == 0, iclass 18, count 2 2006.190.08:06:59.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.08:06:59.77#ibcon#[25=AT06-06\r\n] 2006.190.08:06:59.77#ibcon#*before write, iclass 18, count 2 2006.190.08:06:59.77#ibcon#enter sib2, iclass 18, count 2 2006.190.08:06:59.77#ibcon#flushed, iclass 18, count 2 2006.190.08:06:59.77#ibcon#about to write, iclass 18, count 2 2006.190.08:06:59.77#ibcon#wrote, iclass 18, count 2 2006.190.08:06:59.77#ibcon#about to read 3, iclass 18, count 2 2006.190.08:06:59.80#ibcon#read 3, iclass 18, count 2 2006.190.08:06:59.80#ibcon#about to read 4, iclass 18, count 2 2006.190.08:06:59.80#ibcon#read 4, iclass 18, count 2 2006.190.08:06:59.80#ibcon#about to read 5, iclass 18, count 2 2006.190.08:06:59.80#ibcon#read 5, iclass 18, count 2 2006.190.08:06:59.80#ibcon#about to read 6, iclass 18, count 2 2006.190.08:06:59.80#ibcon#read 6, iclass 18, count 2 2006.190.08:06:59.80#ibcon#end of sib2, iclass 18, count 2 2006.190.08:06:59.80#ibcon#*after write, iclass 18, count 2 2006.190.08:06:59.80#ibcon#*before return 0, iclass 18, count 2 2006.190.08:06:59.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:06:59.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:06:59.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.08:06:59.80#ibcon#ireg 7 cls_cnt 0 2006.190.08:06:59.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:06:59.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:06:59.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:06:59.92#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:06:59.92#ibcon#first serial, iclass 18, count 0 2006.190.08:06:59.92#ibcon#enter sib2, iclass 18, count 0 2006.190.08:06:59.92#ibcon#flushed, iclass 18, count 0 2006.190.08:06:59.92#ibcon#about to write, iclass 18, count 0 2006.190.08:06:59.92#ibcon#wrote, iclass 18, count 0 2006.190.08:06:59.92#ibcon#about to read 3, iclass 18, count 0 2006.190.08:06:59.94#ibcon#read 3, iclass 18, count 0 2006.190.08:06:59.94#ibcon#about to read 4, iclass 18, count 0 2006.190.08:06:59.94#ibcon#read 4, iclass 18, count 0 2006.190.08:06:59.94#ibcon#about to read 5, iclass 18, count 0 2006.190.08:06:59.94#ibcon#read 5, iclass 18, count 0 2006.190.08:06:59.94#ibcon#about to read 6, iclass 18, count 0 2006.190.08:06:59.94#ibcon#read 6, iclass 18, count 0 2006.190.08:06:59.94#ibcon#end of sib2, iclass 18, count 0 2006.190.08:06:59.94#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:06:59.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:06:59.94#ibcon#[25=USB\r\n] 2006.190.08:06:59.94#ibcon#*before write, iclass 18, count 0 2006.190.08:06:59.94#ibcon#enter sib2, iclass 18, count 0 2006.190.08:06:59.94#ibcon#flushed, iclass 18, count 0 2006.190.08:06:59.94#ibcon#about to write, iclass 18, count 0 2006.190.08:06:59.94#ibcon#wrote, iclass 18, count 0 2006.190.08:06:59.94#ibcon#about to read 3, iclass 18, count 0 2006.190.08:06:59.97#ibcon#read 3, iclass 18, count 0 2006.190.08:06:59.97#ibcon#about to read 4, iclass 18, count 0 2006.190.08:06:59.97#ibcon#read 4, iclass 18, count 0 2006.190.08:06:59.97#ibcon#about to read 5, iclass 18, count 0 2006.190.08:06:59.97#ibcon#read 5, iclass 18, count 0 2006.190.08:06:59.97#ibcon#about to read 6, iclass 18, count 0 2006.190.08:06:59.97#ibcon#read 6, iclass 18, count 0 2006.190.08:06:59.97#ibcon#end of sib2, iclass 18, count 0 2006.190.08:06:59.97#ibcon#*after write, iclass 18, count 0 2006.190.08:06:59.97#ibcon#*before return 0, iclass 18, count 0 2006.190.08:06:59.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:06:59.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:06:59.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:06:59.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:06:59.97$vc4f8/valo=7,832.99 2006.190.08:06:59.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.08:06:59.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.08:06:59.97#ibcon#ireg 17 cls_cnt 0 2006.190.08:06:59.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:06:59.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:06:59.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:06:59.97#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:06:59.97#ibcon#first serial, iclass 20, count 0 2006.190.08:06:59.97#ibcon#enter sib2, iclass 20, count 0 2006.190.08:06:59.97#ibcon#flushed, iclass 20, count 0 2006.190.08:06:59.97#ibcon#about to write, iclass 20, count 0 2006.190.08:06:59.97#ibcon#wrote, iclass 20, count 0 2006.190.08:06:59.97#ibcon#about to read 3, iclass 20, count 0 2006.190.08:06:59.99#ibcon#read 3, iclass 20, count 0 2006.190.08:06:59.99#ibcon#about to read 4, iclass 20, count 0 2006.190.08:06:59.99#ibcon#read 4, iclass 20, count 0 2006.190.08:06:59.99#ibcon#about to read 5, iclass 20, count 0 2006.190.08:06:59.99#ibcon#read 5, iclass 20, count 0 2006.190.08:06:59.99#ibcon#about to read 6, iclass 20, count 0 2006.190.08:06:59.99#ibcon#read 6, iclass 20, count 0 2006.190.08:06:59.99#ibcon#end of sib2, iclass 20, count 0 2006.190.08:06:59.99#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:06:59.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:06:59.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:06:59.99#ibcon#*before write, iclass 20, count 0 2006.190.08:06:59.99#ibcon#enter sib2, iclass 20, count 0 2006.190.08:06:59.99#ibcon#flushed, iclass 20, count 0 2006.190.08:06:59.99#ibcon#about to write, iclass 20, count 0 2006.190.08:06:59.99#ibcon#wrote, iclass 20, count 0 2006.190.08:06:59.99#ibcon#about to read 3, iclass 20, count 0 2006.190.08:07:00.03#ibcon#read 3, iclass 20, count 0 2006.190.08:07:00.03#ibcon#about to read 4, iclass 20, count 0 2006.190.08:07:00.03#ibcon#read 4, iclass 20, count 0 2006.190.08:07:00.03#ibcon#about to read 5, iclass 20, count 0 2006.190.08:07:00.03#ibcon#read 5, iclass 20, count 0 2006.190.08:07:00.03#ibcon#about to read 6, iclass 20, count 0 2006.190.08:07:00.03#ibcon#read 6, iclass 20, count 0 2006.190.08:07:00.03#ibcon#end of sib2, iclass 20, count 0 2006.190.08:07:00.03#ibcon#*after write, iclass 20, count 0 2006.190.08:07:00.03#ibcon#*before return 0, iclass 20, count 0 2006.190.08:07:00.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:07:00.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:07:00.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:07:00.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:07:00.03$vc4f8/va=7,6 2006.190.08:07:00.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.08:07:00.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.08:07:00.03#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:00.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:07:00.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:07:00.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:07:00.09#ibcon#enter wrdev, iclass 22, count 2 2006.190.08:07:00.09#ibcon#first serial, iclass 22, count 2 2006.190.08:07:00.09#ibcon#enter sib2, iclass 22, count 2 2006.190.08:07:00.09#ibcon#flushed, iclass 22, count 2 2006.190.08:07:00.09#ibcon#about to write, iclass 22, count 2 2006.190.08:07:00.09#ibcon#wrote, iclass 22, count 2 2006.190.08:07:00.09#ibcon#about to read 3, iclass 22, count 2 2006.190.08:07:00.11#ibcon#read 3, iclass 22, count 2 2006.190.08:07:00.11#ibcon#about to read 4, iclass 22, count 2 2006.190.08:07:00.11#ibcon#read 4, iclass 22, count 2 2006.190.08:07:00.11#ibcon#about to read 5, iclass 22, count 2 2006.190.08:07:00.11#ibcon#read 5, iclass 22, count 2 2006.190.08:07:00.11#ibcon#about to read 6, iclass 22, count 2 2006.190.08:07:00.11#ibcon#read 6, iclass 22, count 2 2006.190.08:07:00.11#ibcon#end of sib2, iclass 22, count 2 2006.190.08:07:00.11#ibcon#*mode == 0, iclass 22, count 2 2006.190.08:07:00.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.08:07:00.11#ibcon#[25=AT07-06\r\n] 2006.190.08:07:00.11#ibcon#*before write, iclass 22, count 2 2006.190.08:07:00.11#ibcon#enter sib2, iclass 22, count 2 2006.190.08:07:00.11#ibcon#flushed, iclass 22, count 2 2006.190.08:07:00.11#ibcon#about to write, iclass 22, count 2 2006.190.08:07:00.11#ibcon#wrote, iclass 22, count 2 2006.190.08:07:00.11#ibcon#about to read 3, iclass 22, count 2 2006.190.08:07:00.14#ibcon#read 3, iclass 22, count 2 2006.190.08:07:00.14#ibcon#about to read 4, iclass 22, count 2 2006.190.08:07:00.14#ibcon#read 4, iclass 22, count 2 2006.190.08:07:00.14#ibcon#about to read 5, iclass 22, count 2 2006.190.08:07:00.14#ibcon#read 5, iclass 22, count 2 2006.190.08:07:00.14#ibcon#about to read 6, iclass 22, count 2 2006.190.08:07:00.14#ibcon#read 6, iclass 22, count 2 2006.190.08:07:00.14#ibcon#end of sib2, iclass 22, count 2 2006.190.08:07:00.14#ibcon#*after write, iclass 22, count 2 2006.190.08:07:00.14#ibcon#*before return 0, iclass 22, count 2 2006.190.08:07:00.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:07:00.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:07:00.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.08:07:00.14#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:00.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:07:00.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:07:00.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:07:00.26#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:07:00.26#ibcon#first serial, iclass 22, count 0 2006.190.08:07:00.26#ibcon#enter sib2, iclass 22, count 0 2006.190.08:07:00.26#ibcon#flushed, iclass 22, count 0 2006.190.08:07:00.26#ibcon#about to write, iclass 22, count 0 2006.190.08:07:00.26#ibcon#wrote, iclass 22, count 0 2006.190.08:07:00.26#ibcon#about to read 3, iclass 22, count 0 2006.190.08:07:00.28#ibcon#read 3, iclass 22, count 0 2006.190.08:07:00.28#ibcon#about to read 4, iclass 22, count 0 2006.190.08:07:00.28#ibcon#read 4, iclass 22, count 0 2006.190.08:07:00.28#ibcon#about to read 5, iclass 22, count 0 2006.190.08:07:00.28#ibcon#read 5, iclass 22, count 0 2006.190.08:07:00.28#ibcon#about to read 6, iclass 22, count 0 2006.190.08:07:00.28#ibcon#read 6, iclass 22, count 0 2006.190.08:07:00.28#ibcon#end of sib2, iclass 22, count 0 2006.190.08:07:00.28#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:07:00.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:07:00.28#ibcon#[25=USB\r\n] 2006.190.08:07:00.28#ibcon#*before write, iclass 22, count 0 2006.190.08:07:00.28#ibcon#enter sib2, iclass 22, count 0 2006.190.08:07:00.28#ibcon#flushed, iclass 22, count 0 2006.190.08:07:00.28#ibcon#about to write, iclass 22, count 0 2006.190.08:07:00.28#ibcon#wrote, iclass 22, count 0 2006.190.08:07:00.28#ibcon#about to read 3, iclass 22, count 0 2006.190.08:07:00.31#ibcon#read 3, iclass 22, count 0 2006.190.08:07:00.31#ibcon#about to read 4, iclass 22, count 0 2006.190.08:07:00.31#ibcon#read 4, iclass 22, count 0 2006.190.08:07:00.31#ibcon#about to read 5, iclass 22, count 0 2006.190.08:07:00.31#ibcon#read 5, iclass 22, count 0 2006.190.08:07:00.31#ibcon#about to read 6, iclass 22, count 0 2006.190.08:07:00.31#ibcon#read 6, iclass 22, count 0 2006.190.08:07:00.31#ibcon#end of sib2, iclass 22, count 0 2006.190.08:07:00.31#ibcon#*after write, iclass 22, count 0 2006.190.08:07:00.31#ibcon#*before return 0, iclass 22, count 0 2006.190.08:07:00.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:07:00.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:07:00.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:07:00.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:07:00.31$vc4f8/valo=8,852.99 2006.190.08:07:00.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.08:07:00.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.08:07:00.31#ibcon#ireg 17 cls_cnt 0 2006.190.08:07:00.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:07:00.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:07:00.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:07:00.31#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:07:00.31#ibcon#first serial, iclass 24, count 0 2006.190.08:07:00.31#ibcon#enter sib2, iclass 24, count 0 2006.190.08:07:00.31#ibcon#flushed, iclass 24, count 0 2006.190.08:07:00.31#ibcon#about to write, iclass 24, count 0 2006.190.08:07:00.31#ibcon#wrote, iclass 24, count 0 2006.190.08:07:00.31#ibcon#about to read 3, iclass 24, count 0 2006.190.08:07:00.33#ibcon#read 3, iclass 24, count 0 2006.190.08:07:00.33#ibcon#about to read 4, iclass 24, count 0 2006.190.08:07:00.33#ibcon#read 4, iclass 24, count 0 2006.190.08:07:00.33#ibcon#about to read 5, iclass 24, count 0 2006.190.08:07:00.33#ibcon#read 5, iclass 24, count 0 2006.190.08:07:00.33#ibcon#about to read 6, iclass 24, count 0 2006.190.08:07:00.33#ibcon#read 6, iclass 24, count 0 2006.190.08:07:00.33#ibcon#end of sib2, iclass 24, count 0 2006.190.08:07:00.33#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:07:00.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:07:00.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:07:00.33#ibcon#*before write, iclass 24, count 0 2006.190.08:07:00.33#ibcon#enter sib2, iclass 24, count 0 2006.190.08:07:00.33#ibcon#flushed, iclass 24, count 0 2006.190.08:07:00.33#ibcon#about to write, iclass 24, count 0 2006.190.08:07:00.33#ibcon#wrote, iclass 24, count 0 2006.190.08:07:00.33#ibcon#about to read 3, iclass 24, count 0 2006.190.08:07:00.37#ibcon#read 3, iclass 24, count 0 2006.190.08:07:00.37#ibcon#about to read 4, iclass 24, count 0 2006.190.08:07:00.37#ibcon#read 4, iclass 24, count 0 2006.190.08:07:00.37#ibcon#about to read 5, iclass 24, count 0 2006.190.08:07:00.37#ibcon#read 5, iclass 24, count 0 2006.190.08:07:00.37#ibcon#about to read 6, iclass 24, count 0 2006.190.08:07:00.37#ibcon#read 6, iclass 24, count 0 2006.190.08:07:00.37#ibcon#end of sib2, iclass 24, count 0 2006.190.08:07:00.37#ibcon#*after write, iclass 24, count 0 2006.190.08:07:00.37#ibcon#*before return 0, iclass 24, count 0 2006.190.08:07:00.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:07:00.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:07:00.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:07:00.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:07:00.37$vc4f8/va=8,6 2006.190.08:07:00.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.08:07:00.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.08:07:00.37#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:00.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:07:00.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:07:00.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:07:00.44#ibcon#enter wrdev, iclass 26, count 2 2006.190.08:07:00.44#ibcon#first serial, iclass 26, count 2 2006.190.08:07:00.44#ibcon#enter sib2, iclass 26, count 2 2006.190.08:07:00.44#ibcon#flushed, iclass 26, count 2 2006.190.08:07:00.44#ibcon#about to write, iclass 26, count 2 2006.190.08:07:00.44#ibcon#wrote, iclass 26, count 2 2006.190.08:07:00.44#ibcon#about to read 3, iclass 26, count 2 2006.190.08:07:00.45#ibcon#read 3, iclass 26, count 2 2006.190.08:07:00.45#ibcon#about to read 4, iclass 26, count 2 2006.190.08:07:00.45#ibcon#read 4, iclass 26, count 2 2006.190.08:07:00.45#ibcon#about to read 5, iclass 26, count 2 2006.190.08:07:00.45#ibcon#read 5, iclass 26, count 2 2006.190.08:07:00.45#ibcon#about to read 6, iclass 26, count 2 2006.190.08:07:00.45#ibcon#read 6, iclass 26, count 2 2006.190.08:07:00.45#ibcon#end of sib2, iclass 26, count 2 2006.190.08:07:00.45#ibcon#*mode == 0, iclass 26, count 2 2006.190.08:07:00.45#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.08:07:00.45#ibcon#[25=AT08-06\r\n] 2006.190.08:07:00.45#ibcon#*before write, iclass 26, count 2 2006.190.08:07:00.45#ibcon#enter sib2, iclass 26, count 2 2006.190.08:07:00.45#ibcon#flushed, iclass 26, count 2 2006.190.08:07:00.45#ibcon#about to write, iclass 26, count 2 2006.190.08:07:00.45#ibcon#wrote, iclass 26, count 2 2006.190.08:07:00.45#ibcon#about to read 3, iclass 26, count 2 2006.190.08:07:00.48#ibcon#read 3, iclass 26, count 2 2006.190.08:07:00.48#ibcon#about to read 4, iclass 26, count 2 2006.190.08:07:00.48#ibcon#read 4, iclass 26, count 2 2006.190.08:07:00.48#ibcon#about to read 5, iclass 26, count 2 2006.190.08:07:00.48#ibcon#read 5, iclass 26, count 2 2006.190.08:07:00.48#ibcon#about to read 6, iclass 26, count 2 2006.190.08:07:00.48#ibcon#read 6, iclass 26, count 2 2006.190.08:07:00.48#ibcon#end of sib2, iclass 26, count 2 2006.190.08:07:00.48#ibcon#*after write, iclass 26, count 2 2006.190.08:07:00.48#ibcon#*before return 0, iclass 26, count 2 2006.190.08:07:00.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:07:00.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:07:00.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.08:07:00.48#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:00.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:07:00.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:07:00.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:07:00.60#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:07:00.60#ibcon#first serial, iclass 26, count 0 2006.190.08:07:00.60#ibcon#enter sib2, iclass 26, count 0 2006.190.08:07:00.60#ibcon#flushed, iclass 26, count 0 2006.190.08:07:00.60#ibcon#about to write, iclass 26, count 0 2006.190.08:07:00.60#ibcon#wrote, iclass 26, count 0 2006.190.08:07:00.60#ibcon#about to read 3, iclass 26, count 0 2006.190.08:07:00.62#ibcon#read 3, iclass 26, count 0 2006.190.08:07:00.62#ibcon#about to read 4, iclass 26, count 0 2006.190.08:07:00.62#ibcon#read 4, iclass 26, count 0 2006.190.08:07:00.62#ibcon#about to read 5, iclass 26, count 0 2006.190.08:07:00.62#ibcon#read 5, iclass 26, count 0 2006.190.08:07:00.62#ibcon#about to read 6, iclass 26, count 0 2006.190.08:07:00.62#ibcon#read 6, iclass 26, count 0 2006.190.08:07:00.62#ibcon#end of sib2, iclass 26, count 0 2006.190.08:07:00.62#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:07:00.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:07:00.62#ibcon#[25=USB\r\n] 2006.190.08:07:00.62#ibcon#*before write, iclass 26, count 0 2006.190.08:07:00.62#ibcon#enter sib2, iclass 26, count 0 2006.190.08:07:00.62#ibcon#flushed, iclass 26, count 0 2006.190.08:07:00.62#ibcon#about to write, iclass 26, count 0 2006.190.08:07:00.62#ibcon#wrote, iclass 26, count 0 2006.190.08:07:00.62#ibcon#about to read 3, iclass 26, count 0 2006.190.08:07:00.65#ibcon#read 3, iclass 26, count 0 2006.190.08:07:00.65#ibcon#about to read 4, iclass 26, count 0 2006.190.08:07:00.65#ibcon#read 4, iclass 26, count 0 2006.190.08:07:00.65#ibcon#about to read 5, iclass 26, count 0 2006.190.08:07:00.65#ibcon#read 5, iclass 26, count 0 2006.190.08:07:00.65#ibcon#about to read 6, iclass 26, count 0 2006.190.08:07:00.65#ibcon#read 6, iclass 26, count 0 2006.190.08:07:00.65#ibcon#end of sib2, iclass 26, count 0 2006.190.08:07:00.65#ibcon#*after write, iclass 26, count 0 2006.190.08:07:00.65#ibcon#*before return 0, iclass 26, count 0 2006.190.08:07:00.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:07:00.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:07:00.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:07:00.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:07:00.65$vc4f8/vblo=1,632.99 2006.190.08:07:00.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.08:07:00.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.08:07:00.65#ibcon#ireg 17 cls_cnt 0 2006.190.08:07:00.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:07:00.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:07:00.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:07:00.65#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:07:00.65#ibcon#first serial, iclass 28, count 0 2006.190.08:07:00.65#ibcon#enter sib2, iclass 28, count 0 2006.190.08:07:00.65#ibcon#flushed, iclass 28, count 0 2006.190.08:07:00.65#ibcon#about to write, iclass 28, count 0 2006.190.08:07:00.65#ibcon#wrote, iclass 28, count 0 2006.190.08:07:00.65#ibcon#about to read 3, iclass 28, count 0 2006.190.08:07:00.67#ibcon#read 3, iclass 28, count 0 2006.190.08:07:00.67#ibcon#about to read 4, iclass 28, count 0 2006.190.08:07:00.67#ibcon#read 4, iclass 28, count 0 2006.190.08:07:00.67#ibcon#about to read 5, iclass 28, count 0 2006.190.08:07:00.67#ibcon#read 5, iclass 28, count 0 2006.190.08:07:00.67#ibcon#about to read 6, iclass 28, count 0 2006.190.08:07:00.67#ibcon#read 6, iclass 28, count 0 2006.190.08:07:00.67#ibcon#end of sib2, iclass 28, count 0 2006.190.08:07:00.67#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:07:00.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:07:00.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:07:00.67#ibcon#*before write, iclass 28, count 0 2006.190.08:07:00.67#ibcon#enter sib2, iclass 28, count 0 2006.190.08:07:00.67#ibcon#flushed, iclass 28, count 0 2006.190.08:07:00.67#ibcon#about to write, iclass 28, count 0 2006.190.08:07:00.67#ibcon#wrote, iclass 28, count 0 2006.190.08:07:00.67#ibcon#about to read 3, iclass 28, count 0 2006.190.08:07:00.71#ibcon#read 3, iclass 28, count 0 2006.190.08:07:00.71#ibcon#about to read 4, iclass 28, count 0 2006.190.08:07:00.71#ibcon#read 4, iclass 28, count 0 2006.190.08:07:00.71#ibcon#about to read 5, iclass 28, count 0 2006.190.08:07:00.71#ibcon#read 5, iclass 28, count 0 2006.190.08:07:00.71#ibcon#about to read 6, iclass 28, count 0 2006.190.08:07:00.71#ibcon#read 6, iclass 28, count 0 2006.190.08:07:00.71#ibcon#end of sib2, iclass 28, count 0 2006.190.08:07:00.71#ibcon#*after write, iclass 28, count 0 2006.190.08:07:00.71#ibcon#*before return 0, iclass 28, count 0 2006.190.08:07:00.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:07:00.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:07:00.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:07:00.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:07:00.71$vc4f8/vb=1,4 2006.190.08:07:00.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.08:07:00.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.08:07:00.71#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:00.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:07:00.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:07:00.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:07:00.71#ibcon#enter wrdev, iclass 30, count 2 2006.190.08:07:00.71#ibcon#first serial, iclass 30, count 2 2006.190.08:07:00.71#ibcon#enter sib2, iclass 30, count 2 2006.190.08:07:00.71#ibcon#flushed, iclass 30, count 2 2006.190.08:07:00.71#ibcon#about to write, iclass 30, count 2 2006.190.08:07:00.71#ibcon#wrote, iclass 30, count 2 2006.190.08:07:00.71#ibcon#about to read 3, iclass 30, count 2 2006.190.08:07:00.73#ibcon#read 3, iclass 30, count 2 2006.190.08:07:00.73#ibcon#about to read 4, iclass 30, count 2 2006.190.08:07:00.73#ibcon#read 4, iclass 30, count 2 2006.190.08:07:00.73#ibcon#about to read 5, iclass 30, count 2 2006.190.08:07:00.73#ibcon#read 5, iclass 30, count 2 2006.190.08:07:00.73#ibcon#about to read 6, iclass 30, count 2 2006.190.08:07:00.73#ibcon#read 6, iclass 30, count 2 2006.190.08:07:00.73#ibcon#end of sib2, iclass 30, count 2 2006.190.08:07:00.73#ibcon#*mode == 0, iclass 30, count 2 2006.190.08:07:00.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.08:07:00.73#ibcon#[27=AT01-04\r\n] 2006.190.08:07:00.73#ibcon#*before write, iclass 30, count 2 2006.190.08:07:00.73#ibcon#enter sib2, iclass 30, count 2 2006.190.08:07:00.73#ibcon#flushed, iclass 30, count 2 2006.190.08:07:00.73#ibcon#about to write, iclass 30, count 2 2006.190.08:07:00.73#ibcon#wrote, iclass 30, count 2 2006.190.08:07:00.73#ibcon#about to read 3, iclass 30, count 2 2006.190.08:07:00.76#ibcon#read 3, iclass 30, count 2 2006.190.08:07:00.76#ibcon#about to read 4, iclass 30, count 2 2006.190.08:07:00.76#ibcon#read 4, iclass 30, count 2 2006.190.08:07:00.76#ibcon#about to read 5, iclass 30, count 2 2006.190.08:07:00.76#ibcon#read 5, iclass 30, count 2 2006.190.08:07:00.76#ibcon#about to read 6, iclass 30, count 2 2006.190.08:07:00.76#ibcon#read 6, iclass 30, count 2 2006.190.08:07:00.76#ibcon#end of sib2, iclass 30, count 2 2006.190.08:07:00.76#ibcon#*after write, iclass 30, count 2 2006.190.08:07:00.76#ibcon#*before return 0, iclass 30, count 2 2006.190.08:07:00.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:07:00.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:07:00.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.08:07:00.76#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:00.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:07:00.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:07:00.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:07:00.88#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:07:00.88#ibcon#first serial, iclass 30, count 0 2006.190.08:07:00.88#ibcon#enter sib2, iclass 30, count 0 2006.190.08:07:00.88#ibcon#flushed, iclass 30, count 0 2006.190.08:07:00.88#ibcon#about to write, iclass 30, count 0 2006.190.08:07:00.88#ibcon#wrote, iclass 30, count 0 2006.190.08:07:00.88#ibcon#about to read 3, iclass 30, count 0 2006.190.08:07:00.90#ibcon#read 3, iclass 30, count 0 2006.190.08:07:00.90#ibcon#about to read 4, iclass 30, count 0 2006.190.08:07:00.90#ibcon#read 4, iclass 30, count 0 2006.190.08:07:00.90#ibcon#about to read 5, iclass 30, count 0 2006.190.08:07:00.90#ibcon#read 5, iclass 30, count 0 2006.190.08:07:00.90#ibcon#about to read 6, iclass 30, count 0 2006.190.08:07:00.90#ibcon#read 6, iclass 30, count 0 2006.190.08:07:00.90#ibcon#end of sib2, iclass 30, count 0 2006.190.08:07:00.90#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:07:00.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:07:00.90#ibcon#[27=USB\r\n] 2006.190.08:07:00.90#ibcon#*before write, iclass 30, count 0 2006.190.08:07:00.90#ibcon#enter sib2, iclass 30, count 0 2006.190.08:07:00.90#ibcon#flushed, iclass 30, count 0 2006.190.08:07:00.90#ibcon#about to write, iclass 30, count 0 2006.190.08:07:00.90#ibcon#wrote, iclass 30, count 0 2006.190.08:07:00.90#ibcon#about to read 3, iclass 30, count 0 2006.190.08:07:00.93#ibcon#read 3, iclass 30, count 0 2006.190.08:07:00.93#ibcon#about to read 4, iclass 30, count 0 2006.190.08:07:00.93#ibcon#read 4, iclass 30, count 0 2006.190.08:07:00.93#ibcon#about to read 5, iclass 30, count 0 2006.190.08:07:00.93#ibcon#read 5, iclass 30, count 0 2006.190.08:07:00.93#ibcon#about to read 6, iclass 30, count 0 2006.190.08:07:00.93#ibcon#read 6, iclass 30, count 0 2006.190.08:07:00.93#ibcon#end of sib2, iclass 30, count 0 2006.190.08:07:00.93#ibcon#*after write, iclass 30, count 0 2006.190.08:07:00.93#ibcon#*before return 0, iclass 30, count 0 2006.190.08:07:00.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:07:00.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:07:00.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:07:00.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:07:00.93$vc4f8/vblo=2,640.99 2006.190.08:07:00.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.08:07:00.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.08:07:00.93#ibcon#ireg 17 cls_cnt 0 2006.190.08:07:00.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:07:00.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:07:00.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:07:00.93#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:07:00.93#ibcon#first serial, iclass 32, count 0 2006.190.08:07:00.93#ibcon#enter sib2, iclass 32, count 0 2006.190.08:07:00.93#ibcon#flushed, iclass 32, count 0 2006.190.08:07:00.93#ibcon#about to write, iclass 32, count 0 2006.190.08:07:00.93#ibcon#wrote, iclass 32, count 0 2006.190.08:07:00.93#ibcon#about to read 3, iclass 32, count 0 2006.190.08:07:00.95#ibcon#read 3, iclass 32, count 0 2006.190.08:07:00.95#ibcon#about to read 4, iclass 32, count 0 2006.190.08:07:00.95#ibcon#read 4, iclass 32, count 0 2006.190.08:07:00.95#ibcon#about to read 5, iclass 32, count 0 2006.190.08:07:00.95#ibcon#read 5, iclass 32, count 0 2006.190.08:07:00.95#ibcon#about to read 6, iclass 32, count 0 2006.190.08:07:00.95#ibcon#read 6, iclass 32, count 0 2006.190.08:07:00.95#ibcon#end of sib2, iclass 32, count 0 2006.190.08:07:00.95#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:07:00.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:07:00.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:07:00.95#ibcon#*before write, iclass 32, count 0 2006.190.08:07:00.95#ibcon#enter sib2, iclass 32, count 0 2006.190.08:07:00.95#ibcon#flushed, iclass 32, count 0 2006.190.08:07:00.95#ibcon#about to write, iclass 32, count 0 2006.190.08:07:00.95#ibcon#wrote, iclass 32, count 0 2006.190.08:07:00.95#ibcon#about to read 3, iclass 32, count 0 2006.190.08:07:00.99#ibcon#read 3, iclass 32, count 0 2006.190.08:07:00.99#ibcon#about to read 4, iclass 32, count 0 2006.190.08:07:00.99#ibcon#read 4, iclass 32, count 0 2006.190.08:07:00.99#ibcon#about to read 5, iclass 32, count 0 2006.190.08:07:00.99#ibcon#read 5, iclass 32, count 0 2006.190.08:07:00.99#ibcon#about to read 6, iclass 32, count 0 2006.190.08:07:00.99#ibcon#read 6, iclass 32, count 0 2006.190.08:07:00.99#ibcon#end of sib2, iclass 32, count 0 2006.190.08:07:00.99#ibcon#*after write, iclass 32, count 0 2006.190.08:07:00.99#ibcon#*before return 0, iclass 32, count 0 2006.190.08:07:00.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:07:00.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:07:00.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:07:00.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:07:00.99$vc4f8/vb=2,4 2006.190.08:07:00.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.08:07:00.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.08:07:00.99#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:00.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:07:01.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:07:01.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:07:01.05#ibcon#enter wrdev, iclass 34, count 2 2006.190.08:07:01.05#ibcon#first serial, iclass 34, count 2 2006.190.08:07:01.05#ibcon#enter sib2, iclass 34, count 2 2006.190.08:07:01.05#ibcon#flushed, iclass 34, count 2 2006.190.08:07:01.05#ibcon#about to write, iclass 34, count 2 2006.190.08:07:01.05#ibcon#wrote, iclass 34, count 2 2006.190.08:07:01.05#ibcon#about to read 3, iclass 34, count 2 2006.190.08:07:01.07#ibcon#read 3, iclass 34, count 2 2006.190.08:07:01.07#ibcon#about to read 4, iclass 34, count 2 2006.190.08:07:01.07#ibcon#read 4, iclass 34, count 2 2006.190.08:07:01.07#ibcon#about to read 5, iclass 34, count 2 2006.190.08:07:01.07#ibcon#read 5, iclass 34, count 2 2006.190.08:07:01.07#ibcon#about to read 6, iclass 34, count 2 2006.190.08:07:01.07#ibcon#read 6, iclass 34, count 2 2006.190.08:07:01.07#ibcon#end of sib2, iclass 34, count 2 2006.190.08:07:01.07#ibcon#*mode == 0, iclass 34, count 2 2006.190.08:07:01.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.08:07:01.07#ibcon#[27=AT02-04\r\n] 2006.190.08:07:01.07#ibcon#*before write, iclass 34, count 2 2006.190.08:07:01.07#ibcon#enter sib2, iclass 34, count 2 2006.190.08:07:01.07#ibcon#flushed, iclass 34, count 2 2006.190.08:07:01.07#ibcon#about to write, iclass 34, count 2 2006.190.08:07:01.07#ibcon#wrote, iclass 34, count 2 2006.190.08:07:01.07#ibcon#about to read 3, iclass 34, count 2 2006.190.08:07:01.10#ibcon#read 3, iclass 34, count 2 2006.190.08:07:01.10#ibcon#about to read 4, iclass 34, count 2 2006.190.08:07:01.10#ibcon#read 4, iclass 34, count 2 2006.190.08:07:01.10#ibcon#about to read 5, iclass 34, count 2 2006.190.08:07:01.10#ibcon#read 5, iclass 34, count 2 2006.190.08:07:01.10#ibcon#about to read 6, iclass 34, count 2 2006.190.08:07:01.10#ibcon#read 6, iclass 34, count 2 2006.190.08:07:01.10#ibcon#end of sib2, iclass 34, count 2 2006.190.08:07:01.10#ibcon#*after write, iclass 34, count 2 2006.190.08:07:01.10#ibcon#*before return 0, iclass 34, count 2 2006.190.08:07:01.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:07:01.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:07:01.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.08:07:01.10#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:01.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:07:01.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:07:01.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:07:01.22#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:07:01.22#ibcon#first serial, iclass 34, count 0 2006.190.08:07:01.22#ibcon#enter sib2, iclass 34, count 0 2006.190.08:07:01.22#ibcon#flushed, iclass 34, count 0 2006.190.08:07:01.22#ibcon#about to write, iclass 34, count 0 2006.190.08:07:01.22#ibcon#wrote, iclass 34, count 0 2006.190.08:07:01.22#ibcon#about to read 3, iclass 34, count 0 2006.190.08:07:01.24#ibcon#read 3, iclass 34, count 0 2006.190.08:07:01.24#ibcon#about to read 4, iclass 34, count 0 2006.190.08:07:01.24#ibcon#read 4, iclass 34, count 0 2006.190.08:07:01.24#ibcon#about to read 5, iclass 34, count 0 2006.190.08:07:01.24#ibcon#read 5, iclass 34, count 0 2006.190.08:07:01.24#ibcon#about to read 6, iclass 34, count 0 2006.190.08:07:01.24#ibcon#read 6, iclass 34, count 0 2006.190.08:07:01.24#ibcon#end of sib2, iclass 34, count 0 2006.190.08:07:01.24#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:07:01.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:07:01.24#ibcon#[27=USB\r\n] 2006.190.08:07:01.24#ibcon#*before write, iclass 34, count 0 2006.190.08:07:01.24#ibcon#enter sib2, iclass 34, count 0 2006.190.08:07:01.24#ibcon#flushed, iclass 34, count 0 2006.190.08:07:01.24#ibcon#about to write, iclass 34, count 0 2006.190.08:07:01.24#ibcon#wrote, iclass 34, count 0 2006.190.08:07:01.24#ibcon#about to read 3, iclass 34, count 0 2006.190.08:07:01.27#ibcon#read 3, iclass 34, count 0 2006.190.08:07:01.27#ibcon#about to read 4, iclass 34, count 0 2006.190.08:07:01.27#ibcon#read 4, iclass 34, count 0 2006.190.08:07:01.27#ibcon#about to read 5, iclass 34, count 0 2006.190.08:07:01.27#ibcon#read 5, iclass 34, count 0 2006.190.08:07:01.27#ibcon#about to read 6, iclass 34, count 0 2006.190.08:07:01.27#ibcon#read 6, iclass 34, count 0 2006.190.08:07:01.27#ibcon#end of sib2, iclass 34, count 0 2006.190.08:07:01.27#ibcon#*after write, iclass 34, count 0 2006.190.08:07:01.27#ibcon#*before return 0, iclass 34, count 0 2006.190.08:07:01.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:07:01.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:07:01.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:07:01.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:07:01.27$vc4f8/vblo=3,656.99 2006.190.08:07:01.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.08:07:01.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.08:07:01.27#ibcon#ireg 17 cls_cnt 0 2006.190.08:07:01.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:07:01.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:07:01.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:07:01.27#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:07:01.27#ibcon#first serial, iclass 36, count 0 2006.190.08:07:01.27#ibcon#enter sib2, iclass 36, count 0 2006.190.08:07:01.27#ibcon#flushed, iclass 36, count 0 2006.190.08:07:01.27#ibcon#about to write, iclass 36, count 0 2006.190.08:07:01.27#ibcon#wrote, iclass 36, count 0 2006.190.08:07:01.27#ibcon#about to read 3, iclass 36, count 0 2006.190.08:07:01.29#ibcon#read 3, iclass 36, count 0 2006.190.08:07:01.29#ibcon#about to read 4, iclass 36, count 0 2006.190.08:07:01.29#ibcon#read 4, iclass 36, count 0 2006.190.08:07:01.29#ibcon#about to read 5, iclass 36, count 0 2006.190.08:07:01.29#ibcon#read 5, iclass 36, count 0 2006.190.08:07:01.29#ibcon#about to read 6, iclass 36, count 0 2006.190.08:07:01.29#ibcon#read 6, iclass 36, count 0 2006.190.08:07:01.29#ibcon#end of sib2, iclass 36, count 0 2006.190.08:07:01.29#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:07:01.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:07:01.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:07:01.29#ibcon#*before write, iclass 36, count 0 2006.190.08:07:01.29#ibcon#enter sib2, iclass 36, count 0 2006.190.08:07:01.29#ibcon#flushed, iclass 36, count 0 2006.190.08:07:01.29#ibcon#about to write, iclass 36, count 0 2006.190.08:07:01.29#ibcon#wrote, iclass 36, count 0 2006.190.08:07:01.29#ibcon#about to read 3, iclass 36, count 0 2006.190.08:07:01.33#ibcon#read 3, iclass 36, count 0 2006.190.08:07:01.33#ibcon#about to read 4, iclass 36, count 0 2006.190.08:07:01.33#ibcon#read 4, iclass 36, count 0 2006.190.08:07:01.33#ibcon#about to read 5, iclass 36, count 0 2006.190.08:07:01.33#ibcon#read 5, iclass 36, count 0 2006.190.08:07:01.33#ibcon#about to read 6, iclass 36, count 0 2006.190.08:07:01.33#ibcon#read 6, iclass 36, count 0 2006.190.08:07:01.33#ibcon#end of sib2, iclass 36, count 0 2006.190.08:07:01.33#ibcon#*after write, iclass 36, count 0 2006.190.08:07:01.33#ibcon#*before return 0, iclass 36, count 0 2006.190.08:07:01.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:07:01.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:07:01.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:07:01.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:07:01.33$vc4f8/vb=3,4 2006.190.08:07:01.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.08:07:01.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.08:07:01.33#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:01.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:07:01.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:07:01.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:07:01.39#ibcon#enter wrdev, iclass 38, count 2 2006.190.08:07:01.39#ibcon#first serial, iclass 38, count 2 2006.190.08:07:01.39#ibcon#enter sib2, iclass 38, count 2 2006.190.08:07:01.39#ibcon#flushed, iclass 38, count 2 2006.190.08:07:01.39#ibcon#about to write, iclass 38, count 2 2006.190.08:07:01.39#ibcon#wrote, iclass 38, count 2 2006.190.08:07:01.39#ibcon#about to read 3, iclass 38, count 2 2006.190.08:07:01.41#ibcon#read 3, iclass 38, count 2 2006.190.08:07:01.41#ibcon#about to read 4, iclass 38, count 2 2006.190.08:07:01.41#ibcon#read 4, iclass 38, count 2 2006.190.08:07:01.41#ibcon#about to read 5, iclass 38, count 2 2006.190.08:07:01.41#ibcon#read 5, iclass 38, count 2 2006.190.08:07:01.41#ibcon#about to read 6, iclass 38, count 2 2006.190.08:07:01.41#ibcon#read 6, iclass 38, count 2 2006.190.08:07:01.41#ibcon#end of sib2, iclass 38, count 2 2006.190.08:07:01.41#ibcon#*mode == 0, iclass 38, count 2 2006.190.08:07:01.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.08:07:01.41#ibcon#[27=AT03-04\r\n] 2006.190.08:07:01.41#ibcon#*before write, iclass 38, count 2 2006.190.08:07:01.41#ibcon#enter sib2, iclass 38, count 2 2006.190.08:07:01.41#ibcon#flushed, iclass 38, count 2 2006.190.08:07:01.41#ibcon#about to write, iclass 38, count 2 2006.190.08:07:01.41#ibcon#wrote, iclass 38, count 2 2006.190.08:07:01.41#ibcon#about to read 3, iclass 38, count 2 2006.190.08:07:01.44#ibcon#read 3, iclass 38, count 2 2006.190.08:07:01.44#ibcon#about to read 4, iclass 38, count 2 2006.190.08:07:01.44#ibcon#read 4, iclass 38, count 2 2006.190.08:07:01.44#ibcon#about to read 5, iclass 38, count 2 2006.190.08:07:01.44#ibcon#read 5, iclass 38, count 2 2006.190.08:07:01.44#ibcon#about to read 6, iclass 38, count 2 2006.190.08:07:01.44#ibcon#read 6, iclass 38, count 2 2006.190.08:07:01.44#ibcon#end of sib2, iclass 38, count 2 2006.190.08:07:01.44#ibcon#*after write, iclass 38, count 2 2006.190.08:07:01.44#ibcon#*before return 0, iclass 38, count 2 2006.190.08:07:01.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:07:01.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:07:01.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.08:07:01.44#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:01.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:07:01.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:07:01.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:07:01.56#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:07:01.56#ibcon#first serial, iclass 38, count 0 2006.190.08:07:01.56#ibcon#enter sib2, iclass 38, count 0 2006.190.08:07:01.56#ibcon#flushed, iclass 38, count 0 2006.190.08:07:01.56#ibcon#about to write, iclass 38, count 0 2006.190.08:07:01.56#ibcon#wrote, iclass 38, count 0 2006.190.08:07:01.56#ibcon#about to read 3, iclass 38, count 0 2006.190.08:07:01.58#ibcon#read 3, iclass 38, count 0 2006.190.08:07:01.58#ibcon#about to read 4, iclass 38, count 0 2006.190.08:07:01.58#ibcon#read 4, iclass 38, count 0 2006.190.08:07:01.58#ibcon#about to read 5, iclass 38, count 0 2006.190.08:07:01.58#ibcon#read 5, iclass 38, count 0 2006.190.08:07:01.58#ibcon#about to read 6, iclass 38, count 0 2006.190.08:07:01.58#ibcon#read 6, iclass 38, count 0 2006.190.08:07:01.58#ibcon#end of sib2, iclass 38, count 0 2006.190.08:07:01.58#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:07:01.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:07:01.58#ibcon#[27=USB\r\n] 2006.190.08:07:01.58#ibcon#*before write, iclass 38, count 0 2006.190.08:07:01.58#ibcon#enter sib2, iclass 38, count 0 2006.190.08:07:01.58#ibcon#flushed, iclass 38, count 0 2006.190.08:07:01.58#ibcon#about to write, iclass 38, count 0 2006.190.08:07:01.58#ibcon#wrote, iclass 38, count 0 2006.190.08:07:01.58#ibcon#about to read 3, iclass 38, count 0 2006.190.08:07:01.61#ibcon#read 3, iclass 38, count 0 2006.190.08:07:01.61#ibcon#about to read 4, iclass 38, count 0 2006.190.08:07:01.61#ibcon#read 4, iclass 38, count 0 2006.190.08:07:01.61#ibcon#about to read 5, iclass 38, count 0 2006.190.08:07:01.61#ibcon#read 5, iclass 38, count 0 2006.190.08:07:01.61#ibcon#about to read 6, iclass 38, count 0 2006.190.08:07:01.61#ibcon#read 6, iclass 38, count 0 2006.190.08:07:01.61#ibcon#end of sib2, iclass 38, count 0 2006.190.08:07:01.61#ibcon#*after write, iclass 38, count 0 2006.190.08:07:01.61#ibcon#*before return 0, iclass 38, count 0 2006.190.08:07:01.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:07:01.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:07:01.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:07:01.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:07:01.61$vc4f8/vblo=4,712.99 2006.190.08:07:01.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.08:07:01.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.08:07:01.61#ibcon#ireg 17 cls_cnt 0 2006.190.08:07:01.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:07:01.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:07:01.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:07:01.61#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:07:01.61#ibcon#first serial, iclass 40, count 0 2006.190.08:07:01.61#ibcon#enter sib2, iclass 40, count 0 2006.190.08:07:01.61#ibcon#flushed, iclass 40, count 0 2006.190.08:07:01.61#ibcon#about to write, iclass 40, count 0 2006.190.08:07:01.61#ibcon#wrote, iclass 40, count 0 2006.190.08:07:01.61#ibcon#about to read 3, iclass 40, count 0 2006.190.08:07:01.63#ibcon#read 3, iclass 40, count 0 2006.190.08:07:01.63#ibcon#about to read 4, iclass 40, count 0 2006.190.08:07:01.63#ibcon#read 4, iclass 40, count 0 2006.190.08:07:01.63#ibcon#about to read 5, iclass 40, count 0 2006.190.08:07:01.63#ibcon#read 5, iclass 40, count 0 2006.190.08:07:01.63#ibcon#about to read 6, iclass 40, count 0 2006.190.08:07:01.63#ibcon#read 6, iclass 40, count 0 2006.190.08:07:01.63#ibcon#end of sib2, iclass 40, count 0 2006.190.08:07:01.63#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:07:01.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:07:01.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:07:01.63#ibcon#*before write, iclass 40, count 0 2006.190.08:07:01.63#ibcon#enter sib2, iclass 40, count 0 2006.190.08:07:01.63#ibcon#flushed, iclass 40, count 0 2006.190.08:07:01.63#ibcon#about to write, iclass 40, count 0 2006.190.08:07:01.63#ibcon#wrote, iclass 40, count 0 2006.190.08:07:01.63#ibcon#about to read 3, iclass 40, count 0 2006.190.08:07:01.67#ibcon#read 3, iclass 40, count 0 2006.190.08:07:01.67#ibcon#about to read 4, iclass 40, count 0 2006.190.08:07:01.67#ibcon#read 4, iclass 40, count 0 2006.190.08:07:01.67#ibcon#about to read 5, iclass 40, count 0 2006.190.08:07:01.67#ibcon#read 5, iclass 40, count 0 2006.190.08:07:01.67#ibcon#about to read 6, iclass 40, count 0 2006.190.08:07:01.67#ibcon#read 6, iclass 40, count 0 2006.190.08:07:01.67#ibcon#end of sib2, iclass 40, count 0 2006.190.08:07:01.67#ibcon#*after write, iclass 40, count 0 2006.190.08:07:01.67#ibcon#*before return 0, iclass 40, count 0 2006.190.08:07:01.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:07:01.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:07:01.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:07:01.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:07:01.67$vc4f8/vb=4,4 2006.190.08:07:01.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.08:07:01.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.08:07:01.67#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:01.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:07:01.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:07:01.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:07:01.73#ibcon#enter wrdev, iclass 4, count 2 2006.190.08:07:01.73#ibcon#first serial, iclass 4, count 2 2006.190.08:07:01.73#ibcon#enter sib2, iclass 4, count 2 2006.190.08:07:01.73#ibcon#flushed, iclass 4, count 2 2006.190.08:07:01.73#ibcon#about to write, iclass 4, count 2 2006.190.08:07:01.73#ibcon#wrote, iclass 4, count 2 2006.190.08:07:01.73#ibcon#about to read 3, iclass 4, count 2 2006.190.08:07:01.75#ibcon#read 3, iclass 4, count 2 2006.190.08:07:01.75#ibcon#about to read 4, iclass 4, count 2 2006.190.08:07:01.75#ibcon#read 4, iclass 4, count 2 2006.190.08:07:01.75#ibcon#about to read 5, iclass 4, count 2 2006.190.08:07:01.75#ibcon#read 5, iclass 4, count 2 2006.190.08:07:01.75#ibcon#about to read 6, iclass 4, count 2 2006.190.08:07:01.75#ibcon#read 6, iclass 4, count 2 2006.190.08:07:01.75#ibcon#end of sib2, iclass 4, count 2 2006.190.08:07:01.75#ibcon#*mode == 0, iclass 4, count 2 2006.190.08:07:01.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.08:07:01.75#ibcon#[27=AT04-04\r\n] 2006.190.08:07:01.75#ibcon#*before write, iclass 4, count 2 2006.190.08:07:01.75#ibcon#enter sib2, iclass 4, count 2 2006.190.08:07:01.75#ibcon#flushed, iclass 4, count 2 2006.190.08:07:01.75#ibcon#about to write, iclass 4, count 2 2006.190.08:07:01.75#ibcon#wrote, iclass 4, count 2 2006.190.08:07:01.75#ibcon#about to read 3, iclass 4, count 2 2006.190.08:07:01.78#ibcon#read 3, iclass 4, count 2 2006.190.08:07:01.78#ibcon#about to read 4, iclass 4, count 2 2006.190.08:07:01.78#ibcon#read 4, iclass 4, count 2 2006.190.08:07:01.78#ibcon#about to read 5, iclass 4, count 2 2006.190.08:07:01.78#ibcon#read 5, iclass 4, count 2 2006.190.08:07:01.78#ibcon#about to read 6, iclass 4, count 2 2006.190.08:07:01.78#ibcon#read 6, iclass 4, count 2 2006.190.08:07:01.78#ibcon#end of sib2, iclass 4, count 2 2006.190.08:07:01.78#ibcon#*after write, iclass 4, count 2 2006.190.08:07:01.78#ibcon#*before return 0, iclass 4, count 2 2006.190.08:07:01.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:07:01.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:07:01.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.08:07:01.78#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:01.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:07:01.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:07:01.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:07:01.90#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:07:01.90#ibcon#first serial, iclass 4, count 0 2006.190.08:07:01.90#ibcon#enter sib2, iclass 4, count 0 2006.190.08:07:01.90#ibcon#flushed, iclass 4, count 0 2006.190.08:07:01.90#ibcon#about to write, iclass 4, count 0 2006.190.08:07:01.90#ibcon#wrote, iclass 4, count 0 2006.190.08:07:01.90#ibcon#about to read 3, iclass 4, count 0 2006.190.08:07:01.92#ibcon#read 3, iclass 4, count 0 2006.190.08:07:01.92#ibcon#about to read 4, iclass 4, count 0 2006.190.08:07:01.92#ibcon#read 4, iclass 4, count 0 2006.190.08:07:01.92#ibcon#about to read 5, iclass 4, count 0 2006.190.08:07:01.92#ibcon#read 5, iclass 4, count 0 2006.190.08:07:01.92#ibcon#about to read 6, iclass 4, count 0 2006.190.08:07:01.92#ibcon#read 6, iclass 4, count 0 2006.190.08:07:01.92#ibcon#end of sib2, iclass 4, count 0 2006.190.08:07:01.92#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:07:01.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:07:01.92#ibcon#[27=USB\r\n] 2006.190.08:07:01.92#ibcon#*before write, iclass 4, count 0 2006.190.08:07:01.92#ibcon#enter sib2, iclass 4, count 0 2006.190.08:07:01.92#ibcon#flushed, iclass 4, count 0 2006.190.08:07:01.92#ibcon#about to write, iclass 4, count 0 2006.190.08:07:01.92#ibcon#wrote, iclass 4, count 0 2006.190.08:07:01.92#ibcon#about to read 3, iclass 4, count 0 2006.190.08:07:01.95#ibcon#read 3, iclass 4, count 0 2006.190.08:07:01.95#ibcon#about to read 4, iclass 4, count 0 2006.190.08:07:01.95#ibcon#read 4, iclass 4, count 0 2006.190.08:07:01.95#ibcon#about to read 5, iclass 4, count 0 2006.190.08:07:01.95#ibcon#read 5, iclass 4, count 0 2006.190.08:07:01.95#ibcon#about to read 6, iclass 4, count 0 2006.190.08:07:01.95#ibcon#read 6, iclass 4, count 0 2006.190.08:07:01.95#ibcon#end of sib2, iclass 4, count 0 2006.190.08:07:01.95#ibcon#*after write, iclass 4, count 0 2006.190.08:07:01.95#ibcon#*before return 0, iclass 4, count 0 2006.190.08:07:01.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:07:01.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:07:01.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:07:01.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:07:01.95$vc4f8/vblo=5,744.99 2006.190.08:07:01.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:07:01.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:07:01.95#ibcon#ireg 17 cls_cnt 0 2006.190.08:07:01.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:07:01.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:07:01.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:07:01.95#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:07:01.95#ibcon#first serial, iclass 6, count 0 2006.190.08:07:01.95#ibcon#enter sib2, iclass 6, count 0 2006.190.08:07:01.95#ibcon#flushed, iclass 6, count 0 2006.190.08:07:01.95#ibcon#about to write, iclass 6, count 0 2006.190.08:07:01.95#ibcon#wrote, iclass 6, count 0 2006.190.08:07:01.95#ibcon#about to read 3, iclass 6, count 0 2006.190.08:07:01.97#ibcon#read 3, iclass 6, count 0 2006.190.08:07:01.97#ibcon#about to read 4, iclass 6, count 0 2006.190.08:07:01.97#ibcon#read 4, iclass 6, count 0 2006.190.08:07:01.97#ibcon#about to read 5, iclass 6, count 0 2006.190.08:07:01.97#ibcon#read 5, iclass 6, count 0 2006.190.08:07:01.97#ibcon#about to read 6, iclass 6, count 0 2006.190.08:07:01.97#ibcon#read 6, iclass 6, count 0 2006.190.08:07:01.97#ibcon#end of sib2, iclass 6, count 0 2006.190.08:07:01.97#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:07:01.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:07:01.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:07:01.97#ibcon#*before write, iclass 6, count 0 2006.190.08:07:01.97#ibcon#enter sib2, iclass 6, count 0 2006.190.08:07:01.97#ibcon#flushed, iclass 6, count 0 2006.190.08:07:01.97#ibcon#about to write, iclass 6, count 0 2006.190.08:07:01.97#ibcon#wrote, iclass 6, count 0 2006.190.08:07:01.97#ibcon#about to read 3, iclass 6, count 0 2006.190.08:07:02.01#ibcon#read 3, iclass 6, count 0 2006.190.08:07:02.01#ibcon#about to read 4, iclass 6, count 0 2006.190.08:07:02.01#ibcon#read 4, iclass 6, count 0 2006.190.08:07:02.01#ibcon#about to read 5, iclass 6, count 0 2006.190.08:07:02.01#ibcon#read 5, iclass 6, count 0 2006.190.08:07:02.01#ibcon#about to read 6, iclass 6, count 0 2006.190.08:07:02.01#ibcon#read 6, iclass 6, count 0 2006.190.08:07:02.01#ibcon#end of sib2, iclass 6, count 0 2006.190.08:07:02.01#ibcon#*after write, iclass 6, count 0 2006.190.08:07:02.01#ibcon#*before return 0, iclass 6, count 0 2006.190.08:07:02.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:07:02.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:07:02.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:07:02.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:07:02.01$vc4f8/vb=5,4 2006.190.08:07:02.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.08:07:02.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.08:07:02.01#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:02.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:07:02.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:07:02.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:07:02.07#ibcon#enter wrdev, iclass 10, count 2 2006.190.08:07:02.07#ibcon#first serial, iclass 10, count 2 2006.190.08:07:02.07#ibcon#enter sib2, iclass 10, count 2 2006.190.08:07:02.07#ibcon#flushed, iclass 10, count 2 2006.190.08:07:02.07#ibcon#about to write, iclass 10, count 2 2006.190.08:07:02.07#ibcon#wrote, iclass 10, count 2 2006.190.08:07:02.07#ibcon#about to read 3, iclass 10, count 2 2006.190.08:07:02.09#ibcon#read 3, iclass 10, count 2 2006.190.08:07:02.09#ibcon#about to read 4, iclass 10, count 2 2006.190.08:07:02.09#ibcon#read 4, iclass 10, count 2 2006.190.08:07:02.09#ibcon#about to read 5, iclass 10, count 2 2006.190.08:07:02.09#ibcon#read 5, iclass 10, count 2 2006.190.08:07:02.09#ibcon#about to read 6, iclass 10, count 2 2006.190.08:07:02.09#ibcon#read 6, iclass 10, count 2 2006.190.08:07:02.09#ibcon#end of sib2, iclass 10, count 2 2006.190.08:07:02.09#ibcon#*mode == 0, iclass 10, count 2 2006.190.08:07:02.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.08:07:02.09#ibcon#[27=AT05-04\r\n] 2006.190.08:07:02.09#ibcon#*before write, iclass 10, count 2 2006.190.08:07:02.09#ibcon#enter sib2, iclass 10, count 2 2006.190.08:07:02.09#ibcon#flushed, iclass 10, count 2 2006.190.08:07:02.09#ibcon#about to write, iclass 10, count 2 2006.190.08:07:02.09#ibcon#wrote, iclass 10, count 2 2006.190.08:07:02.09#ibcon#about to read 3, iclass 10, count 2 2006.190.08:07:02.12#ibcon#read 3, iclass 10, count 2 2006.190.08:07:02.12#ibcon#about to read 4, iclass 10, count 2 2006.190.08:07:02.12#ibcon#read 4, iclass 10, count 2 2006.190.08:07:02.12#ibcon#about to read 5, iclass 10, count 2 2006.190.08:07:02.12#ibcon#read 5, iclass 10, count 2 2006.190.08:07:02.12#ibcon#about to read 6, iclass 10, count 2 2006.190.08:07:02.12#ibcon#read 6, iclass 10, count 2 2006.190.08:07:02.12#ibcon#end of sib2, iclass 10, count 2 2006.190.08:07:02.12#ibcon#*after write, iclass 10, count 2 2006.190.08:07:02.12#ibcon#*before return 0, iclass 10, count 2 2006.190.08:07:02.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:07:02.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:07:02.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.08:07:02.12#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:02.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:07:02.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:07:02.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:07:02.24#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:07:02.24#ibcon#first serial, iclass 10, count 0 2006.190.08:07:02.24#ibcon#enter sib2, iclass 10, count 0 2006.190.08:07:02.24#ibcon#flushed, iclass 10, count 0 2006.190.08:07:02.24#ibcon#about to write, iclass 10, count 0 2006.190.08:07:02.24#ibcon#wrote, iclass 10, count 0 2006.190.08:07:02.24#ibcon#about to read 3, iclass 10, count 0 2006.190.08:07:02.26#ibcon#read 3, iclass 10, count 0 2006.190.08:07:02.26#ibcon#about to read 4, iclass 10, count 0 2006.190.08:07:02.26#ibcon#read 4, iclass 10, count 0 2006.190.08:07:02.26#ibcon#about to read 5, iclass 10, count 0 2006.190.08:07:02.26#ibcon#read 5, iclass 10, count 0 2006.190.08:07:02.26#ibcon#about to read 6, iclass 10, count 0 2006.190.08:07:02.26#ibcon#read 6, iclass 10, count 0 2006.190.08:07:02.26#ibcon#end of sib2, iclass 10, count 0 2006.190.08:07:02.26#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:07:02.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:07:02.26#ibcon#[27=USB\r\n] 2006.190.08:07:02.26#ibcon#*before write, iclass 10, count 0 2006.190.08:07:02.26#ibcon#enter sib2, iclass 10, count 0 2006.190.08:07:02.26#ibcon#flushed, iclass 10, count 0 2006.190.08:07:02.26#ibcon#about to write, iclass 10, count 0 2006.190.08:07:02.26#ibcon#wrote, iclass 10, count 0 2006.190.08:07:02.26#ibcon#about to read 3, iclass 10, count 0 2006.190.08:07:02.29#ibcon#read 3, iclass 10, count 0 2006.190.08:07:02.29#ibcon#about to read 4, iclass 10, count 0 2006.190.08:07:02.29#ibcon#read 4, iclass 10, count 0 2006.190.08:07:02.29#ibcon#about to read 5, iclass 10, count 0 2006.190.08:07:02.29#ibcon#read 5, iclass 10, count 0 2006.190.08:07:02.29#ibcon#about to read 6, iclass 10, count 0 2006.190.08:07:02.29#ibcon#read 6, iclass 10, count 0 2006.190.08:07:02.29#ibcon#end of sib2, iclass 10, count 0 2006.190.08:07:02.29#ibcon#*after write, iclass 10, count 0 2006.190.08:07:02.29#ibcon#*before return 0, iclass 10, count 0 2006.190.08:07:02.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:07:02.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:07:02.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:07:02.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:07:02.29$vc4f8/vblo=6,752.99 2006.190.08:07:02.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:07:02.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:07:02.29#ibcon#ireg 17 cls_cnt 0 2006.190.08:07:02.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:07:02.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:07:02.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:07:02.29#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:07:02.29#ibcon#first serial, iclass 12, count 0 2006.190.08:07:02.29#ibcon#enter sib2, iclass 12, count 0 2006.190.08:07:02.29#ibcon#flushed, iclass 12, count 0 2006.190.08:07:02.29#ibcon#about to write, iclass 12, count 0 2006.190.08:07:02.29#ibcon#wrote, iclass 12, count 0 2006.190.08:07:02.29#ibcon#about to read 3, iclass 12, count 0 2006.190.08:07:02.31#ibcon#read 3, iclass 12, count 0 2006.190.08:07:02.31#ibcon#about to read 4, iclass 12, count 0 2006.190.08:07:02.31#ibcon#read 4, iclass 12, count 0 2006.190.08:07:02.31#ibcon#about to read 5, iclass 12, count 0 2006.190.08:07:02.31#ibcon#read 5, iclass 12, count 0 2006.190.08:07:02.31#ibcon#about to read 6, iclass 12, count 0 2006.190.08:07:02.31#ibcon#read 6, iclass 12, count 0 2006.190.08:07:02.31#ibcon#end of sib2, iclass 12, count 0 2006.190.08:07:02.31#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:07:02.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:07:02.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:07:02.31#ibcon#*before write, iclass 12, count 0 2006.190.08:07:02.31#ibcon#enter sib2, iclass 12, count 0 2006.190.08:07:02.31#ibcon#flushed, iclass 12, count 0 2006.190.08:07:02.31#ibcon#about to write, iclass 12, count 0 2006.190.08:07:02.31#ibcon#wrote, iclass 12, count 0 2006.190.08:07:02.31#ibcon#about to read 3, iclass 12, count 0 2006.190.08:07:02.35#ibcon#read 3, iclass 12, count 0 2006.190.08:07:02.35#ibcon#about to read 4, iclass 12, count 0 2006.190.08:07:02.35#ibcon#read 4, iclass 12, count 0 2006.190.08:07:02.35#ibcon#about to read 5, iclass 12, count 0 2006.190.08:07:02.35#ibcon#read 5, iclass 12, count 0 2006.190.08:07:02.35#ibcon#about to read 6, iclass 12, count 0 2006.190.08:07:02.35#ibcon#read 6, iclass 12, count 0 2006.190.08:07:02.35#ibcon#end of sib2, iclass 12, count 0 2006.190.08:07:02.35#ibcon#*after write, iclass 12, count 0 2006.190.08:07:02.35#ibcon#*before return 0, iclass 12, count 0 2006.190.08:07:02.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:07:02.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:07:02.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:07:02.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:07:02.35$vc4f8/vb=6,4 2006.190.08:07:02.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:07:02.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:07:02.35#ibcon#ireg 11 cls_cnt 2 2006.190.08:07:02.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:07:02.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:07:02.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:07:02.41#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:07:02.41#ibcon#first serial, iclass 14, count 2 2006.190.08:07:02.41#ibcon#enter sib2, iclass 14, count 2 2006.190.08:07:02.41#ibcon#flushed, iclass 14, count 2 2006.190.08:07:02.41#ibcon#about to write, iclass 14, count 2 2006.190.08:07:02.41#ibcon#wrote, iclass 14, count 2 2006.190.08:07:02.41#ibcon#about to read 3, iclass 14, count 2 2006.190.08:07:02.43#ibcon#read 3, iclass 14, count 2 2006.190.08:07:02.43#ibcon#about to read 4, iclass 14, count 2 2006.190.08:07:02.43#ibcon#read 4, iclass 14, count 2 2006.190.08:07:02.43#ibcon#about to read 5, iclass 14, count 2 2006.190.08:07:02.43#ibcon#read 5, iclass 14, count 2 2006.190.08:07:02.43#ibcon#about to read 6, iclass 14, count 2 2006.190.08:07:02.43#ibcon#read 6, iclass 14, count 2 2006.190.08:07:02.43#ibcon#end of sib2, iclass 14, count 2 2006.190.08:07:02.43#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:07:02.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:07:02.43#ibcon#[27=AT06-04\r\n] 2006.190.08:07:02.43#ibcon#*before write, iclass 14, count 2 2006.190.08:07:02.43#ibcon#enter sib2, iclass 14, count 2 2006.190.08:07:02.43#ibcon#flushed, iclass 14, count 2 2006.190.08:07:02.43#ibcon#about to write, iclass 14, count 2 2006.190.08:07:02.43#ibcon#wrote, iclass 14, count 2 2006.190.08:07:02.43#ibcon#about to read 3, iclass 14, count 2 2006.190.08:07:02.46#ibcon#read 3, iclass 14, count 2 2006.190.08:07:02.46#ibcon#about to read 4, iclass 14, count 2 2006.190.08:07:02.46#ibcon#read 4, iclass 14, count 2 2006.190.08:07:02.46#ibcon#about to read 5, iclass 14, count 2 2006.190.08:07:02.46#ibcon#read 5, iclass 14, count 2 2006.190.08:07:02.46#ibcon#about to read 6, iclass 14, count 2 2006.190.08:07:02.46#ibcon#read 6, iclass 14, count 2 2006.190.08:07:02.46#ibcon#end of sib2, iclass 14, count 2 2006.190.08:07:02.46#ibcon#*after write, iclass 14, count 2 2006.190.08:07:02.46#ibcon#*before return 0, iclass 14, count 2 2006.190.08:07:02.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:07:02.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:07:02.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:07:02.46#ibcon#ireg 7 cls_cnt 0 2006.190.08:07:02.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:07:02.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:07:02.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:07:02.58#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:07:02.58#ibcon#first serial, iclass 14, count 0 2006.190.08:07:02.58#ibcon#enter sib2, iclass 14, count 0 2006.190.08:07:02.58#ibcon#flushed, iclass 14, count 0 2006.190.08:07:02.58#ibcon#about to write, iclass 14, count 0 2006.190.08:07:02.58#ibcon#wrote, iclass 14, count 0 2006.190.08:07:02.58#ibcon#about to read 3, iclass 14, count 0 2006.190.08:07:02.60#ibcon#read 3, iclass 14, count 0 2006.190.08:07:02.60#ibcon#about to read 4, iclass 14, count 0 2006.190.08:07:02.60#ibcon#read 4, iclass 14, count 0 2006.190.08:07:02.60#ibcon#about to read 5, iclass 14, count 0 2006.190.08:07:02.60#ibcon#read 5, iclass 14, count 0 2006.190.08:07:02.60#ibcon#about to read 6, iclass 14, count 0 2006.190.08:07:02.60#ibcon#read 6, iclass 14, count 0 2006.190.08:07:02.60#ibcon#end of sib2, iclass 14, count 0 2006.190.08:07:02.60#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:07:02.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:07:02.60#ibcon#[27=USB\r\n] 2006.190.08:07:02.60#ibcon#*before write, iclass 14, count 0 2006.190.08:07:02.60#ibcon#enter sib2, iclass 14, count 0 2006.190.08:07:02.60#ibcon#flushed, iclass 14, count 0 2006.190.08:07:02.60#ibcon#about to write, iclass 14, count 0 2006.190.08:07:02.60#ibcon#wrote, iclass 14, count 0 2006.190.08:07:02.60#ibcon#about to read 3, iclass 14, count 0 2006.190.08:07:02.63#ibcon#read 3, iclass 14, count 0 2006.190.08:07:02.63#ibcon#about to read 4, iclass 14, count 0 2006.190.08:07:02.63#ibcon#read 4, iclass 14, count 0 2006.190.08:07:02.63#ibcon#about to read 5, iclass 14, count 0 2006.190.08:07:02.63#ibcon#read 5, iclass 14, count 0 2006.190.08:07:02.63#ibcon#about to read 6, iclass 14, count 0 2006.190.08:07:02.63#ibcon#read 6, iclass 14, count 0 2006.190.08:07:02.63#ibcon#end of sib2, iclass 14, count 0 2006.190.08:07:02.63#ibcon#*after write, iclass 14, count 0 2006.190.08:07:02.63#ibcon#*before return 0, iclass 14, count 0 2006.190.08:07:02.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:07:02.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:07:02.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:07:02.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:07:02.63$vc4f8/vabw=wide 2006.190.08:07:02.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:07:02.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:07:02.63#ibcon#ireg 8 cls_cnt 0 2006.190.08:07:02.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:07:02.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:07:02.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:07:02.63#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:07:02.63#ibcon#first serial, iclass 16, count 0 2006.190.08:07:02.63#ibcon#enter sib2, iclass 16, count 0 2006.190.08:07:02.63#ibcon#flushed, iclass 16, count 0 2006.190.08:07:02.63#ibcon#about to write, iclass 16, count 0 2006.190.08:07:02.63#ibcon#wrote, iclass 16, count 0 2006.190.08:07:02.63#ibcon#about to read 3, iclass 16, count 0 2006.190.08:07:02.65#ibcon#read 3, iclass 16, count 0 2006.190.08:07:02.65#ibcon#about to read 4, iclass 16, count 0 2006.190.08:07:02.65#ibcon#read 4, iclass 16, count 0 2006.190.08:07:02.65#ibcon#about to read 5, iclass 16, count 0 2006.190.08:07:02.65#ibcon#read 5, iclass 16, count 0 2006.190.08:07:02.65#ibcon#about to read 6, iclass 16, count 0 2006.190.08:07:02.65#ibcon#read 6, iclass 16, count 0 2006.190.08:07:02.65#ibcon#end of sib2, iclass 16, count 0 2006.190.08:07:02.65#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:07:02.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:07:02.65#ibcon#[25=BW32\r\n] 2006.190.08:07:02.65#ibcon#*before write, iclass 16, count 0 2006.190.08:07:02.65#ibcon#enter sib2, iclass 16, count 0 2006.190.08:07:02.65#ibcon#flushed, iclass 16, count 0 2006.190.08:07:02.65#ibcon#about to write, iclass 16, count 0 2006.190.08:07:02.65#ibcon#wrote, iclass 16, count 0 2006.190.08:07:02.65#ibcon#about to read 3, iclass 16, count 0 2006.190.08:07:02.68#ibcon#read 3, iclass 16, count 0 2006.190.08:07:02.68#ibcon#about to read 4, iclass 16, count 0 2006.190.08:07:02.68#ibcon#read 4, iclass 16, count 0 2006.190.08:07:02.68#ibcon#about to read 5, iclass 16, count 0 2006.190.08:07:02.68#ibcon#read 5, iclass 16, count 0 2006.190.08:07:02.68#ibcon#about to read 6, iclass 16, count 0 2006.190.08:07:02.68#ibcon#read 6, iclass 16, count 0 2006.190.08:07:02.68#ibcon#end of sib2, iclass 16, count 0 2006.190.08:07:02.68#ibcon#*after write, iclass 16, count 0 2006.190.08:07:02.68#ibcon#*before return 0, iclass 16, count 0 2006.190.08:07:02.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:07:02.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:07:02.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:07:02.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:07:02.68$vc4f8/vbbw=wide 2006.190.08:07:02.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.08:07:02.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.08:07:02.68#ibcon#ireg 8 cls_cnt 0 2006.190.08:07:02.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:07:02.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:07:02.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:07:02.76#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:07:02.76#ibcon#first serial, iclass 18, count 0 2006.190.08:07:02.76#ibcon#enter sib2, iclass 18, count 0 2006.190.08:07:02.76#ibcon#flushed, iclass 18, count 0 2006.190.08:07:02.76#ibcon#about to write, iclass 18, count 0 2006.190.08:07:02.76#ibcon#wrote, iclass 18, count 0 2006.190.08:07:02.76#ibcon#about to read 3, iclass 18, count 0 2006.190.08:07:02.77#ibcon#read 3, iclass 18, count 0 2006.190.08:07:02.77#ibcon#about to read 4, iclass 18, count 0 2006.190.08:07:02.77#ibcon#read 4, iclass 18, count 0 2006.190.08:07:02.77#ibcon#about to read 5, iclass 18, count 0 2006.190.08:07:02.77#ibcon#read 5, iclass 18, count 0 2006.190.08:07:02.77#ibcon#about to read 6, iclass 18, count 0 2006.190.08:07:02.77#ibcon#read 6, iclass 18, count 0 2006.190.08:07:02.77#ibcon#end of sib2, iclass 18, count 0 2006.190.08:07:02.77#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:07:02.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:07:02.77#ibcon#[27=BW32\r\n] 2006.190.08:07:02.77#ibcon#*before write, iclass 18, count 0 2006.190.08:07:02.77#ibcon#enter sib2, iclass 18, count 0 2006.190.08:07:02.77#ibcon#flushed, iclass 18, count 0 2006.190.08:07:02.77#ibcon#about to write, iclass 18, count 0 2006.190.08:07:02.77#ibcon#wrote, iclass 18, count 0 2006.190.08:07:02.77#ibcon#about to read 3, iclass 18, count 0 2006.190.08:07:02.80#ibcon#read 3, iclass 18, count 0 2006.190.08:07:02.80#ibcon#about to read 4, iclass 18, count 0 2006.190.08:07:02.80#ibcon#read 4, iclass 18, count 0 2006.190.08:07:02.80#ibcon#about to read 5, iclass 18, count 0 2006.190.08:07:02.80#ibcon#read 5, iclass 18, count 0 2006.190.08:07:02.80#ibcon#about to read 6, iclass 18, count 0 2006.190.08:07:02.80#ibcon#read 6, iclass 18, count 0 2006.190.08:07:02.80#ibcon#end of sib2, iclass 18, count 0 2006.190.08:07:02.80#ibcon#*after write, iclass 18, count 0 2006.190.08:07:02.80#ibcon#*before return 0, iclass 18, count 0 2006.190.08:07:02.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:07:02.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:07:02.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:07:02.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:07:02.80$4f8m12a/ifd4f 2006.190.08:07:02.80$ifd4f/lo= 2006.190.08:07:02.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:07:02.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:07:02.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:07:02.80$ifd4f/patch= 2006.190.08:07:02.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:07:02.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:07:02.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:07:02.80$4f8m12a/"form=m,16.000,1:2 2006.190.08:07:02.80$4f8m12a/"tpicd 2006.190.08:07:02.80$4f8m12a/echo=off 2006.190.08:07:02.80$4f8m12a/xlog=off 2006.190.08:07:02.80:!2006.190.08:07:50 2006.190.08:07:29.14#trakl#Source acquired 2006.190.08:07:30.14#flagr#flagr/antenna,acquired 2006.190.08:07:50.00:preob 2006.190.08:07:50.14/onsource/TRACKING 2006.190.08:07:50.14:!2006.190.08:08:00 2006.190.08:08:00.00:data_valid=on 2006.190.08:08:00.00:midob 2006.190.08:08:00.14/onsource/TRACKING 2006.190.08:08:00.14/wx/24.43,1012.1,100 2006.190.08:08:00.29/cable/+6.4718E-03 2006.190.08:08:01.38/va/01,08,usb,yes,31,32 2006.190.08:08:01.38/va/02,07,usb,yes,31,32 2006.190.08:08:01.38/va/03,06,usb,yes,33,33 2006.190.08:08:01.38/va/04,07,usb,yes,32,34 2006.190.08:08:01.38/va/05,07,usb,yes,35,37 2006.190.08:08:01.38/va/06,06,usb,yes,34,34 2006.190.08:08:01.38/va/07,06,usb,yes,34,34 2006.190.08:08:01.38/va/08,06,usb,yes,37,36 2006.190.08:08:01.61/valo/01,532.99,yes,locked 2006.190.08:08:01.61/valo/02,572.99,yes,locked 2006.190.08:08:01.61/valo/03,672.99,yes,locked 2006.190.08:08:01.61/valo/04,832.99,yes,locked 2006.190.08:08:01.61/valo/05,652.99,yes,locked 2006.190.08:08:01.61/valo/06,772.99,yes,locked 2006.190.08:08:01.61/valo/07,832.99,yes,locked 2006.190.08:08:01.61/valo/08,852.99,yes,locked 2006.190.08:08:02.70/vb/01,04,usb,yes,28,27 2006.190.08:08:02.70/vb/02,04,usb,yes,30,32 2006.190.08:08:02.70/vb/03,04,usb,yes,27,30 2006.190.08:08:02.70/vb/04,04,usb,yes,28,28 2006.190.08:08:02.70/vb/05,04,usb,yes,26,30 2006.190.08:08:02.70/vb/06,04,usb,yes,27,30 2006.190.08:08:02.70/vb/07,04,usb,yes,29,29 2006.190.08:08:02.70/vb/08,04,usb,yes,27,30 2006.190.08:08:02.93/vblo/01,632.99,yes,locked 2006.190.08:08:02.93/vblo/02,640.99,yes,locked 2006.190.08:08:02.93/vblo/03,656.99,yes,locked 2006.190.08:08:02.93/vblo/04,712.99,yes,locked 2006.190.08:08:02.93/vblo/05,744.99,yes,locked 2006.190.08:08:02.93/vblo/06,752.99,yes,locked 2006.190.08:08:02.93/vblo/07,734.99,yes,locked 2006.190.08:08:02.93/vblo/08,744.99,yes,locked 2006.190.08:08:03.08/vabw/8 2006.190.08:08:03.23/vbbw/8 2006.190.08:08:03.43/xfe/off,on,14.7 2006.190.08:08:03.81/ifatt/23,28,28,28 2006.190.08:08:04.07/fmout-gps/S +2.85E-07 2006.190.08:08:04.16:!2006.190.08:09:50 2006.190.08:09:50.01:data_valid=off 2006.190.08:09:50.02:postob 2006.190.08:09:50.09/cable/+6.4715E-03 2006.190.08:09:50.10/wx/24.42,1012.1,100 2006.190.08:09:51.07/fmout-gps/S +2.85E-07 2006.190.08:09:51.08:scan_name=190-0811,k06190,60 2006.190.08:09:51.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.190.08:09:52.14#flagr#flagr/antenna,new-source 2006.190.08:09:52.15:checkk5 2006.190.08:09:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:09:52.92/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:09:53.30/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:09:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:09:54.04/chk_obsdata//k5ts1/T1900808??a.dat file size is correct (nominal:880MB, actual:872MB). 2006.190.08:09:54.42/chk_obsdata//k5ts2/T1900808??b.dat file size is correct (nominal:880MB, actual:872MB). 2006.190.08:09:54.80/chk_obsdata//k5ts3/T1900808??c.dat file size is correct (nominal:880MB, actual:872MB). 2006.190.08:09:55.18/chk_obsdata//k5ts4/T1900808??d.dat file size is correct (nominal:880MB, actual:872MB). 2006.190.08:09:55.89/k5log//k5ts1_log_newline 2006.190.08:09:56.59/k5log//k5ts2_log_newline 2006.190.08:09:57.29/k5log//k5ts3_log_newline 2006.190.08:09:57.99/k5log//k5ts4_log_newline 2006.190.08:09:58.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:09:58.02:4f8m12a=2 2006.190.08:09:58.02$4f8m12a/echo=on 2006.190.08:09:58.02$4f8m12a/pcalon 2006.190.08:09:58.02$pcalon/"no phase cal control is implemented here 2006.190.08:09:58.02$4f8m12a/"tpicd=stop 2006.190.08:09:58.02$4f8m12a/vc4f8 2006.190.08:09:58.02$vc4f8/valo=1,532.99 2006.190.08:09:58.02#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:09:58.02#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:09:58.02#ibcon#ireg 17 cls_cnt 0 2006.190.08:09:58.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:09:58.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:09:58.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:09:58.02#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:09:58.02#ibcon#first serial, iclass 12, count 0 2006.190.08:09:58.02#ibcon#enter sib2, iclass 12, count 0 2006.190.08:09:58.02#ibcon#flushed, iclass 12, count 0 2006.190.08:09:58.02#ibcon#about to write, iclass 12, count 0 2006.190.08:09:58.02#ibcon#wrote, iclass 12, count 0 2006.190.08:09:58.02#ibcon#about to read 3, iclass 12, count 0 2006.190.08:09:58.03#ibcon#read 3, iclass 12, count 0 2006.190.08:09:58.03#ibcon#about to read 4, iclass 12, count 0 2006.190.08:09:58.03#ibcon#read 4, iclass 12, count 0 2006.190.08:09:58.03#ibcon#about to read 5, iclass 12, count 0 2006.190.08:09:58.03#ibcon#read 5, iclass 12, count 0 2006.190.08:09:58.03#ibcon#about to read 6, iclass 12, count 0 2006.190.08:09:58.03#ibcon#read 6, iclass 12, count 0 2006.190.08:09:58.03#ibcon#end of sib2, iclass 12, count 0 2006.190.08:09:58.03#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:09:58.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:09:58.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:09:58.03#ibcon#*before write, iclass 12, count 0 2006.190.08:09:58.03#ibcon#enter sib2, iclass 12, count 0 2006.190.08:09:58.03#ibcon#flushed, iclass 12, count 0 2006.190.08:09:58.03#ibcon#about to write, iclass 12, count 0 2006.190.08:09:58.03#ibcon#wrote, iclass 12, count 0 2006.190.08:09:58.03#ibcon#about to read 3, iclass 12, count 0 2006.190.08:09:58.09#ibcon#read 3, iclass 12, count 0 2006.190.08:09:58.09#ibcon#about to read 4, iclass 12, count 0 2006.190.08:09:58.09#ibcon#read 4, iclass 12, count 0 2006.190.08:09:58.09#ibcon#about to read 5, iclass 12, count 0 2006.190.08:09:58.09#ibcon#read 5, iclass 12, count 0 2006.190.08:09:58.09#ibcon#about to read 6, iclass 12, count 0 2006.190.08:09:58.09#ibcon#read 6, iclass 12, count 0 2006.190.08:09:58.09#ibcon#end of sib2, iclass 12, count 0 2006.190.08:09:58.09#ibcon#*after write, iclass 12, count 0 2006.190.08:09:58.09#ibcon#*before return 0, iclass 12, count 0 2006.190.08:09:58.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:09:58.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:09:58.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:09:58.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:09:58.09$vc4f8/va=1,8 2006.190.08:09:58.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:09:58.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:09:58.09#ibcon#ireg 11 cls_cnt 2 2006.190.08:09:58.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:09:58.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:09:58.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:09:58.09#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:09:58.09#ibcon#first serial, iclass 14, count 2 2006.190.08:09:58.09#ibcon#enter sib2, iclass 14, count 2 2006.190.08:09:58.09#ibcon#flushed, iclass 14, count 2 2006.190.08:09:58.09#ibcon#about to write, iclass 14, count 2 2006.190.08:09:58.09#ibcon#wrote, iclass 14, count 2 2006.190.08:09:58.09#ibcon#about to read 3, iclass 14, count 2 2006.190.08:09:58.10#ibcon#read 3, iclass 14, count 2 2006.190.08:09:58.10#ibcon#about to read 4, iclass 14, count 2 2006.190.08:09:58.10#ibcon#read 4, iclass 14, count 2 2006.190.08:09:58.10#ibcon#about to read 5, iclass 14, count 2 2006.190.08:09:58.10#ibcon#read 5, iclass 14, count 2 2006.190.08:09:58.10#ibcon#about to read 6, iclass 14, count 2 2006.190.08:09:58.10#ibcon#read 6, iclass 14, count 2 2006.190.08:09:58.10#ibcon#end of sib2, iclass 14, count 2 2006.190.08:09:58.10#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:09:58.10#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:09:58.10#ibcon#[25=AT01-08\r\n] 2006.190.08:09:58.10#ibcon#*before write, iclass 14, count 2 2006.190.08:09:58.10#ibcon#enter sib2, iclass 14, count 2 2006.190.08:09:58.10#ibcon#flushed, iclass 14, count 2 2006.190.08:09:58.10#ibcon#about to write, iclass 14, count 2 2006.190.08:09:58.10#ibcon#wrote, iclass 14, count 2 2006.190.08:09:58.10#ibcon#about to read 3, iclass 14, count 2 2006.190.08:09:58.13#ibcon#read 3, iclass 14, count 2 2006.190.08:09:58.13#ibcon#about to read 4, iclass 14, count 2 2006.190.08:09:58.13#ibcon#read 4, iclass 14, count 2 2006.190.08:09:58.13#ibcon#about to read 5, iclass 14, count 2 2006.190.08:09:58.13#ibcon#read 5, iclass 14, count 2 2006.190.08:09:58.13#ibcon#about to read 6, iclass 14, count 2 2006.190.08:09:58.13#ibcon#read 6, iclass 14, count 2 2006.190.08:09:58.13#ibcon#end of sib2, iclass 14, count 2 2006.190.08:09:58.13#ibcon#*after write, iclass 14, count 2 2006.190.08:09:58.13#ibcon#*before return 0, iclass 14, count 2 2006.190.08:09:58.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:09:58.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:09:58.13#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:09:58.13#ibcon#ireg 7 cls_cnt 0 2006.190.08:09:58.13#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:09:58.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:09:58.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:09:58.27#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:09:58.27#ibcon#first serial, iclass 14, count 0 2006.190.08:09:58.27#ibcon#enter sib2, iclass 14, count 0 2006.190.08:09:58.27#ibcon#flushed, iclass 14, count 0 2006.190.08:09:58.27#ibcon#about to write, iclass 14, count 0 2006.190.08:09:58.27#ibcon#wrote, iclass 14, count 0 2006.190.08:09:58.27#ibcon#about to read 3, iclass 14, count 0 2006.190.08:09:58.29#ibcon#read 3, iclass 14, count 0 2006.190.08:09:58.29#ibcon#about to read 4, iclass 14, count 0 2006.190.08:09:58.29#ibcon#read 4, iclass 14, count 0 2006.190.08:09:58.29#ibcon#about to read 5, iclass 14, count 0 2006.190.08:09:58.29#ibcon#read 5, iclass 14, count 0 2006.190.08:09:58.29#ibcon#about to read 6, iclass 14, count 0 2006.190.08:09:58.29#ibcon#read 6, iclass 14, count 0 2006.190.08:09:58.29#ibcon#end of sib2, iclass 14, count 0 2006.190.08:09:58.29#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:09:58.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:09:58.29#ibcon#[25=USB\r\n] 2006.190.08:09:58.29#ibcon#*before write, iclass 14, count 0 2006.190.08:09:58.29#ibcon#enter sib2, iclass 14, count 0 2006.190.08:09:58.29#ibcon#flushed, iclass 14, count 0 2006.190.08:09:58.29#ibcon#about to write, iclass 14, count 0 2006.190.08:09:58.29#ibcon#wrote, iclass 14, count 0 2006.190.08:09:58.29#ibcon#about to read 3, iclass 14, count 0 2006.190.08:09:58.31#ibcon#read 3, iclass 14, count 0 2006.190.08:09:58.31#ibcon#about to read 4, iclass 14, count 0 2006.190.08:09:58.31#ibcon#read 4, iclass 14, count 0 2006.190.08:09:58.31#ibcon#about to read 5, iclass 14, count 0 2006.190.08:09:58.31#ibcon#read 5, iclass 14, count 0 2006.190.08:09:58.31#ibcon#about to read 6, iclass 14, count 0 2006.190.08:09:58.31#ibcon#read 6, iclass 14, count 0 2006.190.08:09:58.31#ibcon#end of sib2, iclass 14, count 0 2006.190.08:09:58.31#ibcon#*after write, iclass 14, count 0 2006.190.08:09:58.31#ibcon#*before return 0, iclass 14, count 0 2006.190.08:09:58.31#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:09:58.31#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:09:58.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:09:58.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:09:58.31$vc4f8/valo=2,572.99 2006.190.08:09:58.31#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:09:58.31#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:09:58.31#ibcon#ireg 17 cls_cnt 0 2006.190.08:09:58.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:09:58.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:09:58.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:09:58.31#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:09:58.31#ibcon#first serial, iclass 16, count 0 2006.190.08:09:58.31#ibcon#enter sib2, iclass 16, count 0 2006.190.08:09:58.31#ibcon#flushed, iclass 16, count 0 2006.190.08:09:58.31#ibcon#about to write, iclass 16, count 0 2006.190.08:09:58.31#ibcon#wrote, iclass 16, count 0 2006.190.08:09:58.31#ibcon#about to read 3, iclass 16, count 0 2006.190.08:09:58.33#ibcon#read 3, iclass 16, count 0 2006.190.08:09:58.33#ibcon#about to read 4, iclass 16, count 0 2006.190.08:09:58.33#ibcon#read 4, iclass 16, count 0 2006.190.08:09:58.33#ibcon#about to read 5, iclass 16, count 0 2006.190.08:09:58.33#ibcon#read 5, iclass 16, count 0 2006.190.08:09:58.33#ibcon#about to read 6, iclass 16, count 0 2006.190.08:09:58.33#ibcon#read 6, iclass 16, count 0 2006.190.08:09:58.33#ibcon#end of sib2, iclass 16, count 0 2006.190.08:09:58.33#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:09:58.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:09:58.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:09:58.33#ibcon#*before write, iclass 16, count 0 2006.190.08:09:58.33#ibcon#enter sib2, iclass 16, count 0 2006.190.08:09:58.33#ibcon#flushed, iclass 16, count 0 2006.190.08:09:58.33#ibcon#about to write, iclass 16, count 0 2006.190.08:09:58.33#ibcon#wrote, iclass 16, count 0 2006.190.08:09:58.33#ibcon#about to read 3, iclass 16, count 0 2006.190.08:09:58.38#ibcon#read 3, iclass 16, count 0 2006.190.08:09:58.38#ibcon#about to read 4, iclass 16, count 0 2006.190.08:09:58.38#ibcon#read 4, iclass 16, count 0 2006.190.08:09:58.38#ibcon#about to read 5, iclass 16, count 0 2006.190.08:09:58.38#ibcon#read 5, iclass 16, count 0 2006.190.08:09:58.38#ibcon#about to read 6, iclass 16, count 0 2006.190.08:09:58.38#ibcon#read 6, iclass 16, count 0 2006.190.08:09:58.38#ibcon#end of sib2, iclass 16, count 0 2006.190.08:09:58.38#ibcon#*after write, iclass 16, count 0 2006.190.08:09:58.38#ibcon#*before return 0, iclass 16, count 0 2006.190.08:09:58.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:09:58.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:09:58.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:09:58.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:09:58.38$vc4f8/va=2,7 2006.190.08:09:58.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.08:09:58.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.08:09:58.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:09:58.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:09:58.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:09:58.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:09:58.42#ibcon#enter wrdev, iclass 18, count 2 2006.190.08:09:58.42#ibcon#first serial, iclass 18, count 2 2006.190.08:09:58.42#ibcon#enter sib2, iclass 18, count 2 2006.190.08:09:58.42#ibcon#flushed, iclass 18, count 2 2006.190.08:09:58.42#ibcon#about to write, iclass 18, count 2 2006.190.08:09:58.42#ibcon#wrote, iclass 18, count 2 2006.190.08:09:58.42#ibcon#about to read 3, iclass 18, count 2 2006.190.08:09:58.44#ibcon#read 3, iclass 18, count 2 2006.190.08:09:58.44#ibcon#about to read 4, iclass 18, count 2 2006.190.08:09:58.44#ibcon#read 4, iclass 18, count 2 2006.190.08:09:58.44#ibcon#about to read 5, iclass 18, count 2 2006.190.08:09:58.44#ibcon#read 5, iclass 18, count 2 2006.190.08:09:58.44#ibcon#about to read 6, iclass 18, count 2 2006.190.08:09:58.44#ibcon#read 6, iclass 18, count 2 2006.190.08:09:58.44#ibcon#end of sib2, iclass 18, count 2 2006.190.08:09:58.44#ibcon#*mode == 0, iclass 18, count 2 2006.190.08:09:58.44#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.08:09:58.44#ibcon#[25=AT02-07\r\n] 2006.190.08:09:58.44#ibcon#*before write, iclass 18, count 2 2006.190.08:09:58.44#ibcon#enter sib2, iclass 18, count 2 2006.190.08:09:58.44#ibcon#flushed, iclass 18, count 2 2006.190.08:09:58.44#ibcon#about to write, iclass 18, count 2 2006.190.08:09:58.44#ibcon#wrote, iclass 18, count 2 2006.190.08:09:58.44#ibcon#about to read 3, iclass 18, count 2 2006.190.08:09:58.47#ibcon#read 3, iclass 18, count 2 2006.190.08:09:58.47#ibcon#about to read 4, iclass 18, count 2 2006.190.08:09:58.47#ibcon#read 4, iclass 18, count 2 2006.190.08:09:58.47#ibcon#about to read 5, iclass 18, count 2 2006.190.08:09:58.47#ibcon#read 5, iclass 18, count 2 2006.190.08:09:58.47#ibcon#about to read 6, iclass 18, count 2 2006.190.08:09:58.47#ibcon#read 6, iclass 18, count 2 2006.190.08:09:58.47#ibcon#end of sib2, iclass 18, count 2 2006.190.08:09:58.47#ibcon#*after write, iclass 18, count 2 2006.190.08:09:58.47#ibcon#*before return 0, iclass 18, count 2 2006.190.08:09:58.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:09:58.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:09:58.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.08:09:58.47#ibcon#ireg 7 cls_cnt 0 2006.190.08:09:58.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:09:58.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:09:58.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:09:58.59#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:09:58.59#ibcon#first serial, iclass 18, count 0 2006.190.08:09:58.59#ibcon#enter sib2, iclass 18, count 0 2006.190.08:09:58.59#ibcon#flushed, iclass 18, count 0 2006.190.08:09:58.59#ibcon#about to write, iclass 18, count 0 2006.190.08:09:58.59#ibcon#wrote, iclass 18, count 0 2006.190.08:09:58.59#ibcon#about to read 3, iclass 18, count 0 2006.190.08:09:58.61#ibcon#read 3, iclass 18, count 0 2006.190.08:09:58.61#ibcon#about to read 4, iclass 18, count 0 2006.190.08:09:58.61#ibcon#read 4, iclass 18, count 0 2006.190.08:09:58.61#ibcon#about to read 5, iclass 18, count 0 2006.190.08:09:58.61#ibcon#read 5, iclass 18, count 0 2006.190.08:09:58.61#ibcon#about to read 6, iclass 18, count 0 2006.190.08:09:58.61#ibcon#read 6, iclass 18, count 0 2006.190.08:09:58.61#ibcon#end of sib2, iclass 18, count 0 2006.190.08:09:58.61#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:09:58.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:09:58.61#ibcon#[25=USB\r\n] 2006.190.08:09:58.61#ibcon#*before write, iclass 18, count 0 2006.190.08:09:58.61#ibcon#enter sib2, iclass 18, count 0 2006.190.08:09:58.61#ibcon#flushed, iclass 18, count 0 2006.190.08:09:58.61#ibcon#about to write, iclass 18, count 0 2006.190.08:09:58.61#ibcon#wrote, iclass 18, count 0 2006.190.08:09:58.61#ibcon#about to read 3, iclass 18, count 0 2006.190.08:09:58.64#ibcon#read 3, iclass 18, count 0 2006.190.08:09:58.64#ibcon#about to read 4, iclass 18, count 0 2006.190.08:09:58.64#ibcon#read 4, iclass 18, count 0 2006.190.08:09:58.64#ibcon#about to read 5, iclass 18, count 0 2006.190.08:09:58.64#ibcon#read 5, iclass 18, count 0 2006.190.08:09:58.64#ibcon#about to read 6, iclass 18, count 0 2006.190.08:09:58.64#ibcon#read 6, iclass 18, count 0 2006.190.08:09:58.64#ibcon#end of sib2, iclass 18, count 0 2006.190.08:09:58.64#ibcon#*after write, iclass 18, count 0 2006.190.08:09:58.64#ibcon#*before return 0, iclass 18, count 0 2006.190.08:09:58.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:09:58.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:09:58.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:09:58.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:09:58.64$vc4f8/valo=3,672.99 2006.190.08:09:58.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.08:09:58.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.08:09:58.64#ibcon#ireg 17 cls_cnt 0 2006.190.08:09:58.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:09:58.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:09:58.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:09:58.64#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:09:58.64#ibcon#first serial, iclass 20, count 0 2006.190.08:09:58.64#ibcon#enter sib2, iclass 20, count 0 2006.190.08:09:58.64#ibcon#flushed, iclass 20, count 0 2006.190.08:09:58.64#ibcon#about to write, iclass 20, count 0 2006.190.08:09:58.64#ibcon#wrote, iclass 20, count 0 2006.190.08:09:58.64#ibcon#about to read 3, iclass 20, count 0 2006.190.08:09:58.66#ibcon#read 3, iclass 20, count 0 2006.190.08:09:58.66#ibcon#about to read 4, iclass 20, count 0 2006.190.08:09:58.66#ibcon#read 4, iclass 20, count 0 2006.190.08:09:58.66#ibcon#about to read 5, iclass 20, count 0 2006.190.08:09:58.66#ibcon#read 5, iclass 20, count 0 2006.190.08:09:58.66#ibcon#about to read 6, iclass 20, count 0 2006.190.08:09:58.66#ibcon#read 6, iclass 20, count 0 2006.190.08:09:58.66#ibcon#end of sib2, iclass 20, count 0 2006.190.08:09:58.66#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:09:58.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:09:58.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:09:58.66#ibcon#*before write, iclass 20, count 0 2006.190.08:09:58.66#ibcon#enter sib2, iclass 20, count 0 2006.190.08:09:58.66#ibcon#flushed, iclass 20, count 0 2006.190.08:09:58.66#ibcon#about to write, iclass 20, count 0 2006.190.08:09:58.66#ibcon#wrote, iclass 20, count 0 2006.190.08:09:58.66#ibcon#about to read 3, iclass 20, count 0 2006.190.08:09:58.70#ibcon#read 3, iclass 20, count 0 2006.190.08:09:58.70#ibcon#about to read 4, iclass 20, count 0 2006.190.08:09:58.70#ibcon#read 4, iclass 20, count 0 2006.190.08:09:58.70#ibcon#about to read 5, iclass 20, count 0 2006.190.08:09:58.70#ibcon#read 5, iclass 20, count 0 2006.190.08:09:58.70#ibcon#about to read 6, iclass 20, count 0 2006.190.08:09:58.70#ibcon#read 6, iclass 20, count 0 2006.190.08:09:58.70#ibcon#end of sib2, iclass 20, count 0 2006.190.08:09:58.70#ibcon#*after write, iclass 20, count 0 2006.190.08:09:58.70#ibcon#*before return 0, iclass 20, count 0 2006.190.08:09:58.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:09:58.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:09:58.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:09:58.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:09:58.70$vc4f8/va=3,6 2006.190.08:09:58.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.08:09:58.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.08:09:58.70#ibcon#ireg 11 cls_cnt 2 2006.190.08:09:58.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:09:58.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:09:58.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:09:58.76#ibcon#enter wrdev, iclass 22, count 2 2006.190.08:09:58.76#ibcon#first serial, iclass 22, count 2 2006.190.08:09:58.76#ibcon#enter sib2, iclass 22, count 2 2006.190.08:09:58.76#ibcon#flushed, iclass 22, count 2 2006.190.08:09:58.76#ibcon#about to write, iclass 22, count 2 2006.190.08:09:58.76#ibcon#wrote, iclass 22, count 2 2006.190.08:09:58.76#ibcon#about to read 3, iclass 22, count 2 2006.190.08:09:58.78#ibcon#read 3, iclass 22, count 2 2006.190.08:09:58.78#ibcon#about to read 4, iclass 22, count 2 2006.190.08:09:58.78#ibcon#read 4, iclass 22, count 2 2006.190.08:09:58.78#ibcon#about to read 5, iclass 22, count 2 2006.190.08:09:58.78#ibcon#read 5, iclass 22, count 2 2006.190.08:09:58.78#ibcon#about to read 6, iclass 22, count 2 2006.190.08:09:58.78#ibcon#read 6, iclass 22, count 2 2006.190.08:09:58.78#ibcon#end of sib2, iclass 22, count 2 2006.190.08:09:58.78#ibcon#*mode == 0, iclass 22, count 2 2006.190.08:09:58.78#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.08:09:58.78#ibcon#[25=AT03-06\r\n] 2006.190.08:09:58.78#ibcon#*before write, iclass 22, count 2 2006.190.08:09:58.78#ibcon#enter sib2, iclass 22, count 2 2006.190.08:09:58.78#ibcon#flushed, iclass 22, count 2 2006.190.08:09:58.78#ibcon#about to write, iclass 22, count 2 2006.190.08:09:58.78#ibcon#wrote, iclass 22, count 2 2006.190.08:09:58.78#ibcon#about to read 3, iclass 22, count 2 2006.190.08:09:58.81#ibcon#read 3, iclass 22, count 2 2006.190.08:09:58.81#ibcon#about to read 4, iclass 22, count 2 2006.190.08:09:58.81#ibcon#read 4, iclass 22, count 2 2006.190.08:09:58.81#ibcon#about to read 5, iclass 22, count 2 2006.190.08:09:58.81#ibcon#read 5, iclass 22, count 2 2006.190.08:09:58.81#ibcon#about to read 6, iclass 22, count 2 2006.190.08:09:58.81#ibcon#read 6, iclass 22, count 2 2006.190.08:09:58.81#ibcon#end of sib2, iclass 22, count 2 2006.190.08:09:58.81#ibcon#*after write, iclass 22, count 2 2006.190.08:09:58.81#ibcon#*before return 0, iclass 22, count 2 2006.190.08:09:58.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:09:58.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:09:58.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.08:09:58.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:09:58.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:09:58.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:09:58.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:09:58.93#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:09:58.93#ibcon#first serial, iclass 22, count 0 2006.190.08:09:58.93#ibcon#enter sib2, iclass 22, count 0 2006.190.08:09:58.93#ibcon#flushed, iclass 22, count 0 2006.190.08:09:58.93#ibcon#about to write, iclass 22, count 0 2006.190.08:09:58.93#ibcon#wrote, iclass 22, count 0 2006.190.08:09:58.93#ibcon#about to read 3, iclass 22, count 0 2006.190.08:09:58.95#ibcon#read 3, iclass 22, count 0 2006.190.08:09:58.95#ibcon#about to read 4, iclass 22, count 0 2006.190.08:09:58.95#ibcon#read 4, iclass 22, count 0 2006.190.08:09:58.95#ibcon#about to read 5, iclass 22, count 0 2006.190.08:09:58.95#ibcon#read 5, iclass 22, count 0 2006.190.08:09:58.95#ibcon#about to read 6, iclass 22, count 0 2006.190.08:09:58.95#ibcon#read 6, iclass 22, count 0 2006.190.08:09:58.95#ibcon#end of sib2, iclass 22, count 0 2006.190.08:09:58.95#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:09:58.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:09:58.95#ibcon#[25=USB\r\n] 2006.190.08:09:58.95#ibcon#*before write, iclass 22, count 0 2006.190.08:09:58.95#ibcon#enter sib2, iclass 22, count 0 2006.190.08:09:58.95#ibcon#flushed, iclass 22, count 0 2006.190.08:09:58.95#ibcon#about to write, iclass 22, count 0 2006.190.08:09:58.95#ibcon#wrote, iclass 22, count 0 2006.190.08:09:58.95#ibcon#about to read 3, iclass 22, count 0 2006.190.08:09:58.98#ibcon#read 3, iclass 22, count 0 2006.190.08:09:58.98#ibcon#about to read 4, iclass 22, count 0 2006.190.08:09:58.98#ibcon#read 4, iclass 22, count 0 2006.190.08:09:58.98#ibcon#about to read 5, iclass 22, count 0 2006.190.08:09:58.98#ibcon#read 5, iclass 22, count 0 2006.190.08:09:58.98#ibcon#about to read 6, iclass 22, count 0 2006.190.08:09:58.98#ibcon#read 6, iclass 22, count 0 2006.190.08:09:58.98#ibcon#end of sib2, iclass 22, count 0 2006.190.08:09:58.98#ibcon#*after write, iclass 22, count 0 2006.190.08:09:58.98#ibcon#*before return 0, iclass 22, count 0 2006.190.08:09:58.98#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:09:58.98#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:09:58.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:09:58.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:09:58.98$vc4f8/valo=4,832.99 2006.190.08:09:58.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.08:09:58.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.08:09:58.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:09:58.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:09:58.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:09:58.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:09:58.98#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:09:58.98#ibcon#first serial, iclass 24, count 0 2006.190.08:09:58.98#ibcon#enter sib2, iclass 24, count 0 2006.190.08:09:58.98#ibcon#flushed, iclass 24, count 0 2006.190.08:09:58.98#ibcon#about to write, iclass 24, count 0 2006.190.08:09:58.98#ibcon#wrote, iclass 24, count 0 2006.190.08:09:58.98#ibcon#about to read 3, iclass 24, count 0 2006.190.08:09:59.00#ibcon#read 3, iclass 24, count 0 2006.190.08:09:59.00#ibcon#about to read 4, iclass 24, count 0 2006.190.08:09:59.00#ibcon#read 4, iclass 24, count 0 2006.190.08:09:59.00#ibcon#about to read 5, iclass 24, count 0 2006.190.08:09:59.00#ibcon#read 5, iclass 24, count 0 2006.190.08:09:59.00#ibcon#about to read 6, iclass 24, count 0 2006.190.08:09:59.00#ibcon#read 6, iclass 24, count 0 2006.190.08:09:59.00#ibcon#end of sib2, iclass 24, count 0 2006.190.08:09:59.00#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:09:59.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:09:59.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:09:59.00#ibcon#*before write, iclass 24, count 0 2006.190.08:09:59.00#ibcon#enter sib2, iclass 24, count 0 2006.190.08:09:59.00#ibcon#flushed, iclass 24, count 0 2006.190.08:09:59.00#ibcon#about to write, iclass 24, count 0 2006.190.08:09:59.00#ibcon#wrote, iclass 24, count 0 2006.190.08:09:59.00#ibcon#about to read 3, iclass 24, count 0 2006.190.08:09:59.04#ibcon#read 3, iclass 24, count 0 2006.190.08:09:59.04#ibcon#about to read 4, iclass 24, count 0 2006.190.08:09:59.04#ibcon#read 4, iclass 24, count 0 2006.190.08:09:59.04#ibcon#about to read 5, iclass 24, count 0 2006.190.08:09:59.04#ibcon#read 5, iclass 24, count 0 2006.190.08:09:59.04#ibcon#about to read 6, iclass 24, count 0 2006.190.08:09:59.04#ibcon#read 6, iclass 24, count 0 2006.190.08:09:59.04#ibcon#end of sib2, iclass 24, count 0 2006.190.08:09:59.04#ibcon#*after write, iclass 24, count 0 2006.190.08:09:59.04#ibcon#*before return 0, iclass 24, count 0 2006.190.08:09:59.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:09:59.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:09:59.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:09:59.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:09:59.04$vc4f8/va=4,7 2006.190.08:09:59.04#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.08:09:59.04#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.08:09:59.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:09:59.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:09:59.10#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:09:59.10#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:09:59.10#ibcon#enter wrdev, iclass 26, count 2 2006.190.08:09:59.10#ibcon#first serial, iclass 26, count 2 2006.190.08:09:59.10#ibcon#enter sib2, iclass 26, count 2 2006.190.08:09:59.10#ibcon#flushed, iclass 26, count 2 2006.190.08:09:59.10#ibcon#about to write, iclass 26, count 2 2006.190.08:09:59.10#ibcon#wrote, iclass 26, count 2 2006.190.08:09:59.10#ibcon#about to read 3, iclass 26, count 2 2006.190.08:09:59.12#ibcon#read 3, iclass 26, count 2 2006.190.08:09:59.12#ibcon#about to read 4, iclass 26, count 2 2006.190.08:09:59.12#ibcon#read 4, iclass 26, count 2 2006.190.08:09:59.12#ibcon#about to read 5, iclass 26, count 2 2006.190.08:09:59.12#ibcon#read 5, iclass 26, count 2 2006.190.08:09:59.12#ibcon#about to read 6, iclass 26, count 2 2006.190.08:09:59.12#ibcon#read 6, iclass 26, count 2 2006.190.08:09:59.12#ibcon#end of sib2, iclass 26, count 2 2006.190.08:09:59.12#ibcon#*mode == 0, iclass 26, count 2 2006.190.08:09:59.12#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.08:09:59.12#ibcon#[25=AT04-07\r\n] 2006.190.08:09:59.12#ibcon#*before write, iclass 26, count 2 2006.190.08:09:59.12#ibcon#enter sib2, iclass 26, count 2 2006.190.08:09:59.12#ibcon#flushed, iclass 26, count 2 2006.190.08:09:59.12#ibcon#about to write, iclass 26, count 2 2006.190.08:09:59.12#ibcon#wrote, iclass 26, count 2 2006.190.08:09:59.12#ibcon#about to read 3, iclass 26, count 2 2006.190.08:09:59.15#ibcon#read 3, iclass 26, count 2 2006.190.08:09:59.15#ibcon#about to read 4, iclass 26, count 2 2006.190.08:09:59.15#ibcon#read 4, iclass 26, count 2 2006.190.08:09:59.15#ibcon#about to read 5, iclass 26, count 2 2006.190.08:09:59.15#ibcon#read 5, iclass 26, count 2 2006.190.08:09:59.15#ibcon#about to read 6, iclass 26, count 2 2006.190.08:09:59.15#ibcon#read 6, iclass 26, count 2 2006.190.08:09:59.15#ibcon#end of sib2, iclass 26, count 2 2006.190.08:09:59.15#ibcon#*after write, iclass 26, count 2 2006.190.08:09:59.15#ibcon#*before return 0, iclass 26, count 2 2006.190.08:09:59.15#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:09:59.15#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:09:59.15#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.08:09:59.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:09:59.15#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:09:59.27#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:09:59.27#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:09:59.27#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:09:59.27#ibcon#first serial, iclass 26, count 0 2006.190.08:09:59.27#ibcon#enter sib2, iclass 26, count 0 2006.190.08:09:59.27#ibcon#flushed, iclass 26, count 0 2006.190.08:09:59.27#ibcon#about to write, iclass 26, count 0 2006.190.08:09:59.27#ibcon#wrote, iclass 26, count 0 2006.190.08:09:59.27#ibcon#about to read 3, iclass 26, count 0 2006.190.08:09:59.29#ibcon#read 3, iclass 26, count 0 2006.190.08:09:59.29#ibcon#about to read 4, iclass 26, count 0 2006.190.08:09:59.29#ibcon#read 4, iclass 26, count 0 2006.190.08:09:59.29#ibcon#about to read 5, iclass 26, count 0 2006.190.08:09:59.29#ibcon#read 5, iclass 26, count 0 2006.190.08:09:59.29#ibcon#about to read 6, iclass 26, count 0 2006.190.08:09:59.29#ibcon#read 6, iclass 26, count 0 2006.190.08:09:59.29#ibcon#end of sib2, iclass 26, count 0 2006.190.08:09:59.29#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:09:59.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:09:59.29#ibcon#[25=USB\r\n] 2006.190.08:09:59.29#ibcon#*before write, iclass 26, count 0 2006.190.08:09:59.29#ibcon#enter sib2, iclass 26, count 0 2006.190.08:09:59.29#ibcon#flushed, iclass 26, count 0 2006.190.08:09:59.29#ibcon#about to write, iclass 26, count 0 2006.190.08:09:59.29#ibcon#wrote, iclass 26, count 0 2006.190.08:09:59.29#ibcon#about to read 3, iclass 26, count 0 2006.190.08:09:59.32#ibcon#read 3, iclass 26, count 0 2006.190.08:09:59.32#ibcon#about to read 4, iclass 26, count 0 2006.190.08:09:59.32#ibcon#read 4, iclass 26, count 0 2006.190.08:09:59.32#ibcon#about to read 5, iclass 26, count 0 2006.190.08:09:59.32#ibcon#read 5, iclass 26, count 0 2006.190.08:09:59.32#ibcon#about to read 6, iclass 26, count 0 2006.190.08:09:59.32#ibcon#read 6, iclass 26, count 0 2006.190.08:09:59.32#ibcon#end of sib2, iclass 26, count 0 2006.190.08:09:59.32#ibcon#*after write, iclass 26, count 0 2006.190.08:09:59.32#ibcon#*before return 0, iclass 26, count 0 2006.190.08:09:59.32#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:09:59.32#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:09:59.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:09:59.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:09:59.32$vc4f8/valo=5,652.99 2006.190.08:09:59.32#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.08:09:59.32#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.08:09:59.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:09:59.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:09:59.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:09:59.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:09:59.32#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:09:59.32#ibcon#first serial, iclass 28, count 0 2006.190.08:09:59.32#ibcon#enter sib2, iclass 28, count 0 2006.190.08:09:59.32#ibcon#flushed, iclass 28, count 0 2006.190.08:09:59.32#ibcon#about to write, iclass 28, count 0 2006.190.08:09:59.32#ibcon#wrote, iclass 28, count 0 2006.190.08:09:59.32#ibcon#about to read 3, iclass 28, count 0 2006.190.08:09:59.34#ibcon#read 3, iclass 28, count 0 2006.190.08:09:59.34#ibcon#about to read 4, iclass 28, count 0 2006.190.08:09:59.34#ibcon#read 4, iclass 28, count 0 2006.190.08:09:59.34#ibcon#about to read 5, iclass 28, count 0 2006.190.08:09:59.34#ibcon#read 5, iclass 28, count 0 2006.190.08:09:59.34#ibcon#about to read 6, iclass 28, count 0 2006.190.08:09:59.34#ibcon#read 6, iclass 28, count 0 2006.190.08:09:59.34#ibcon#end of sib2, iclass 28, count 0 2006.190.08:09:59.34#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:09:59.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:09:59.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:09:59.34#ibcon#*before write, iclass 28, count 0 2006.190.08:09:59.34#ibcon#enter sib2, iclass 28, count 0 2006.190.08:09:59.34#ibcon#flushed, iclass 28, count 0 2006.190.08:09:59.34#ibcon#about to write, iclass 28, count 0 2006.190.08:09:59.34#ibcon#wrote, iclass 28, count 0 2006.190.08:09:59.34#ibcon#about to read 3, iclass 28, count 0 2006.190.08:09:59.38#ibcon#read 3, iclass 28, count 0 2006.190.08:09:59.38#ibcon#about to read 4, iclass 28, count 0 2006.190.08:09:59.38#ibcon#read 4, iclass 28, count 0 2006.190.08:09:59.38#ibcon#about to read 5, iclass 28, count 0 2006.190.08:09:59.38#ibcon#read 5, iclass 28, count 0 2006.190.08:09:59.38#ibcon#about to read 6, iclass 28, count 0 2006.190.08:09:59.38#ibcon#read 6, iclass 28, count 0 2006.190.08:09:59.38#ibcon#end of sib2, iclass 28, count 0 2006.190.08:09:59.38#ibcon#*after write, iclass 28, count 0 2006.190.08:09:59.38#ibcon#*before return 0, iclass 28, count 0 2006.190.08:09:59.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:09:59.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:09:59.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:09:59.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:09:59.38$vc4f8/va=5,7 2006.190.08:09:59.38#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.08:09:59.38#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.08:09:59.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:09:59.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:09:59.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:09:59.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:09:59.44#ibcon#enter wrdev, iclass 30, count 2 2006.190.08:09:59.44#ibcon#first serial, iclass 30, count 2 2006.190.08:09:59.44#ibcon#enter sib2, iclass 30, count 2 2006.190.08:09:59.44#ibcon#flushed, iclass 30, count 2 2006.190.08:09:59.44#ibcon#about to write, iclass 30, count 2 2006.190.08:09:59.44#ibcon#wrote, iclass 30, count 2 2006.190.08:09:59.44#ibcon#about to read 3, iclass 30, count 2 2006.190.08:09:59.46#ibcon#read 3, iclass 30, count 2 2006.190.08:09:59.46#ibcon#about to read 4, iclass 30, count 2 2006.190.08:09:59.46#ibcon#read 4, iclass 30, count 2 2006.190.08:09:59.46#ibcon#about to read 5, iclass 30, count 2 2006.190.08:09:59.46#ibcon#read 5, iclass 30, count 2 2006.190.08:09:59.46#ibcon#about to read 6, iclass 30, count 2 2006.190.08:09:59.46#ibcon#read 6, iclass 30, count 2 2006.190.08:09:59.46#ibcon#end of sib2, iclass 30, count 2 2006.190.08:09:59.46#ibcon#*mode == 0, iclass 30, count 2 2006.190.08:09:59.46#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.08:09:59.46#ibcon#[25=AT05-07\r\n] 2006.190.08:09:59.46#ibcon#*before write, iclass 30, count 2 2006.190.08:09:59.46#ibcon#enter sib2, iclass 30, count 2 2006.190.08:09:59.46#ibcon#flushed, iclass 30, count 2 2006.190.08:09:59.46#ibcon#about to write, iclass 30, count 2 2006.190.08:09:59.46#ibcon#wrote, iclass 30, count 2 2006.190.08:09:59.46#ibcon#about to read 3, iclass 30, count 2 2006.190.08:09:59.49#ibcon#read 3, iclass 30, count 2 2006.190.08:09:59.49#ibcon#about to read 4, iclass 30, count 2 2006.190.08:09:59.49#ibcon#read 4, iclass 30, count 2 2006.190.08:09:59.49#ibcon#about to read 5, iclass 30, count 2 2006.190.08:09:59.49#ibcon#read 5, iclass 30, count 2 2006.190.08:09:59.49#ibcon#about to read 6, iclass 30, count 2 2006.190.08:09:59.49#ibcon#read 6, iclass 30, count 2 2006.190.08:09:59.49#ibcon#end of sib2, iclass 30, count 2 2006.190.08:09:59.49#ibcon#*after write, iclass 30, count 2 2006.190.08:09:59.49#ibcon#*before return 0, iclass 30, count 2 2006.190.08:09:59.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:09:59.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:09:59.49#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.08:09:59.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:09:59.49#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:09:59.61#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:09:59.61#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:09:59.61#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:09:59.61#ibcon#first serial, iclass 30, count 0 2006.190.08:09:59.61#ibcon#enter sib2, iclass 30, count 0 2006.190.08:09:59.61#ibcon#flushed, iclass 30, count 0 2006.190.08:09:59.61#ibcon#about to write, iclass 30, count 0 2006.190.08:09:59.61#ibcon#wrote, iclass 30, count 0 2006.190.08:09:59.61#ibcon#about to read 3, iclass 30, count 0 2006.190.08:09:59.63#ibcon#read 3, iclass 30, count 0 2006.190.08:09:59.63#ibcon#about to read 4, iclass 30, count 0 2006.190.08:09:59.63#ibcon#read 4, iclass 30, count 0 2006.190.08:09:59.63#ibcon#about to read 5, iclass 30, count 0 2006.190.08:09:59.63#ibcon#read 5, iclass 30, count 0 2006.190.08:09:59.63#ibcon#about to read 6, iclass 30, count 0 2006.190.08:09:59.63#ibcon#read 6, iclass 30, count 0 2006.190.08:09:59.63#ibcon#end of sib2, iclass 30, count 0 2006.190.08:09:59.63#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:09:59.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:09:59.63#ibcon#[25=USB\r\n] 2006.190.08:09:59.63#ibcon#*before write, iclass 30, count 0 2006.190.08:09:59.63#ibcon#enter sib2, iclass 30, count 0 2006.190.08:09:59.63#ibcon#flushed, iclass 30, count 0 2006.190.08:09:59.63#ibcon#about to write, iclass 30, count 0 2006.190.08:09:59.63#ibcon#wrote, iclass 30, count 0 2006.190.08:09:59.63#ibcon#about to read 3, iclass 30, count 0 2006.190.08:09:59.66#ibcon#read 3, iclass 30, count 0 2006.190.08:09:59.66#ibcon#about to read 4, iclass 30, count 0 2006.190.08:09:59.66#ibcon#read 4, iclass 30, count 0 2006.190.08:09:59.66#ibcon#about to read 5, iclass 30, count 0 2006.190.08:09:59.66#ibcon#read 5, iclass 30, count 0 2006.190.08:09:59.66#ibcon#about to read 6, iclass 30, count 0 2006.190.08:09:59.66#ibcon#read 6, iclass 30, count 0 2006.190.08:09:59.66#ibcon#end of sib2, iclass 30, count 0 2006.190.08:09:59.66#ibcon#*after write, iclass 30, count 0 2006.190.08:09:59.66#ibcon#*before return 0, iclass 30, count 0 2006.190.08:09:59.66#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:09:59.66#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:09:59.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:09:59.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:09:59.66$vc4f8/valo=6,772.99 2006.190.08:09:59.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.08:09:59.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.08:09:59.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:09:59.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:09:59.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:09:59.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:09:59.66#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:09:59.66#ibcon#first serial, iclass 32, count 0 2006.190.08:09:59.66#ibcon#enter sib2, iclass 32, count 0 2006.190.08:09:59.66#ibcon#flushed, iclass 32, count 0 2006.190.08:09:59.66#ibcon#about to write, iclass 32, count 0 2006.190.08:09:59.66#ibcon#wrote, iclass 32, count 0 2006.190.08:09:59.66#ibcon#about to read 3, iclass 32, count 0 2006.190.08:09:59.68#ibcon#read 3, iclass 32, count 0 2006.190.08:09:59.68#ibcon#about to read 4, iclass 32, count 0 2006.190.08:09:59.68#ibcon#read 4, iclass 32, count 0 2006.190.08:09:59.68#ibcon#about to read 5, iclass 32, count 0 2006.190.08:09:59.68#ibcon#read 5, iclass 32, count 0 2006.190.08:09:59.68#ibcon#about to read 6, iclass 32, count 0 2006.190.08:09:59.68#ibcon#read 6, iclass 32, count 0 2006.190.08:09:59.68#ibcon#end of sib2, iclass 32, count 0 2006.190.08:09:59.68#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:09:59.68#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:09:59.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:09:59.68#ibcon#*before write, iclass 32, count 0 2006.190.08:09:59.68#ibcon#enter sib2, iclass 32, count 0 2006.190.08:09:59.68#ibcon#flushed, iclass 32, count 0 2006.190.08:09:59.68#ibcon#about to write, iclass 32, count 0 2006.190.08:09:59.68#ibcon#wrote, iclass 32, count 0 2006.190.08:09:59.68#ibcon#about to read 3, iclass 32, count 0 2006.190.08:09:59.72#ibcon#read 3, iclass 32, count 0 2006.190.08:09:59.72#ibcon#about to read 4, iclass 32, count 0 2006.190.08:09:59.72#ibcon#read 4, iclass 32, count 0 2006.190.08:09:59.72#ibcon#about to read 5, iclass 32, count 0 2006.190.08:09:59.72#ibcon#read 5, iclass 32, count 0 2006.190.08:09:59.72#ibcon#about to read 6, iclass 32, count 0 2006.190.08:09:59.72#ibcon#read 6, iclass 32, count 0 2006.190.08:09:59.72#ibcon#end of sib2, iclass 32, count 0 2006.190.08:09:59.72#ibcon#*after write, iclass 32, count 0 2006.190.08:09:59.72#ibcon#*before return 0, iclass 32, count 0 2006.190.08:09:59.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:09:59.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:09:59.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:09:59.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:09:59.72$vc4f8/va=6,6 2006.190.08:09:59.72#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.08:09:59.72#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.08:09:59.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:09:59.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:09:59.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:09:59.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:09:59.78#ibcon#enter wrdev, iclass 34, count 2 2006.190.08:09:59.78#ibcon#first serial, iclass 34, count 2 2006.190.08:09:59.78#ibcon#enter sib2, iclass 34, count 2 2006.190.08:09:59.78#ibcon#flushed, iclass 34, count 2 2006.190.08:09:59.78#ibcon#about to write, iclass 34, count 2 2006.190.08:09:59.78#ibcon#wrote, iclass 34, count 2 2006.190.08:09:59.78#ibcon#about to read 3, iclass 34, count 2 2006.190.08:09:59.80#ibcon#read 3, iclass 34, count 2 2006.190.08:09:59.80#ibcon#about to read 4, iclass 34, count 2 2006.190.08:09:59.80#ibcon#read 4, iclass 34, count 2 2006.190.08:09:59.80#ibcon#about to read 5, iclass 34, count 2 2006.190.08:09:59.80#ibcon#read 5, iclass 34, count 2 2006.190.08:09:59.80#ibcon#about to read 6, iclass 34, count 2 2006.190.08:09:59.80#ibcon#read 6, iclass 34, count 2 2006.190.08:09:59.80#ibcon#end of sib2, iclass 34, count 2 2006.190.08:09:59.80#ibcon#*mode == 0, iclass 34, count 2 2006.190.08:09:59.80#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.08:09:59.80#ibcon#[25=AT06-06\r\n] 2006.190.08:09:59.80#ibcon#*before write, iclass 34, count 2 2006.190.08:09:59.80#ibcon#enter sib2, iclass 34, count 2 2006.190.08:09:59.80#ibcon#flushed, iclass 34, count 2 2006.190.08:09:59.80#ibcon#about to write, iclass 34, count 2 2006.190.08:09:59.80#ibcon#wrote, iclass 34, count 2 2006.190.08:09:59.80#ibcon#about to read 3, iclass 34, count 2 2006.190.08:09:59.83#ibcon#read 3, iclass 34, count 2 2006.190.08:09:59.83#ibcon#about to read 4, iclass 34, count 2 2006.190.08:09:59.83#ibcon#read 4, iclass 34, count 2 2006.190.08:09:59.83#ibcon#about to read 5, iclass 34, count 2 2006.190.08:09:59.83#ibcon#read 5, iclass 34, count 2 2006.190.08:09:59.83#ibcon#about to read 6, iclass 34, count 2 2006.190.08:09:59.83#ibcon#read 6, iclass 34, count 2 2006.190.08:09:59.83#ibcon#end of sib2, iclass 34, count 2 2006.190.08:09:59.83#ibcon#*after write, iclass 34, count 2 2006.190.08:09:59.83#ibcon#*before return 0, iclass 34, count 2 2006.190.08:09:59.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:09:59.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:09:59.83#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.08:09:59.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:09:59.83#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:09:59.95#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:09:59.95#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:09:59.95#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:09:59.95#ibcon#first serial, iclass 34, count 0 2006.190.08:09:59.95#ibcon#enter sib2, iclass 34, count 0 2006.190.08:09:59.95#ibcon#flushed, iclass 34, count 0 2006.190.08:09:59.95#ibcon#about to write, iclass 34, count 0 2006.190.08:09:59.95#ibcon#wrote, iclass 34, count 0 2006.190.08:09:59.95#ibcon#about to read 3, iclass 34, count 0 2006.190.08:09:59.97#ibcon#read 3, iclass 34, count 0 2006.190.08:09:59.97#ibcon#about to read 4, iclass 34, count 0 2006.190.08:09:59.97#ibcon#read 4, iclass 34, count 0 2006.190.08:09:59.97#ibcon#about to read 5, iclass 34, count 0 2006.190.08:09:59.97#ibcon#read 5, iclass 34, count 0 2006.190.08:09:59.97#ibcon#about to read 6, iclass 34, count 0 2006.190.08:09:59.97#ibcon#read 6, iclass 34, count 0 2006.190.08:09:59.97#ibcon#end of sib2, iclass 34, count 0 2006.190.08:09:59.97#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:09:59.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:09:59.97#ibcon#[25=USB\r\n] 2006.190.08:09:59.97#ibcon#*before write, iclass 34, count 0 2006.190.08:09:59.97#ibcon#enter sib2, iclass 34, count 0 2006.190.08:09:59.97#ibcon#flushed, iclass 34, count 0 2006.190.08:09:59.97#ibcon#about to write, iclass 34, count 0 2006.190.08:09:59.97#ibcon#wrote, iclass 34, count 0 2006.190.08:09:59.97#ibcon#about to read 3, iclass 34, count 0 2006.190.08:10:00.00#ibcon#read 3, iclass 34, count 0 2006.190.08:10:00.00#ibcon#about to read 4, iclass 34, count 0 2006.190.08:10:00.00#ibcon#read 4, iclass 34, count 0 2006.190.08:10:00.00#ibcon#about to read 5, iclass 34, count 0 2006.190.08:10:00.00#ibcon#read 5, iclass 34, count 0 2006.190.08:10:00.00#ibcon#about to read 6, iclass 34, count 0 2006.190.08:10:00.00#ibcon#read 6, iclass 34, count 0 2006.190.08:10:00.00#ibcon#end of sib2, iclass 34, count 0 2006.190.08:10:00.00#ibcon#*after write, iclass 34, count 0 2006.190.08:10:00.00#ibcon#*before return 0, iclass 34, count 0 2006.190.08:10:00.00#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:10:00.00#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:10:00.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:10:00.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:10:00.00$vc4f8/valo=7,832.99 2006.190.08:10:00.00#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.08:10:00.00#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.08:10:00.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:00.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:00.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:00.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:00.00#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:10:00.00#ibcon#first serial, iclass 36, count 0 2006.190.08:10:00.00#ibcon#enter sib2, iclass 36, count 0 2006.190.08:10:00.00#ibcon#flushed, iclass 36, count 0 2006.190.08:10:00.00#ibcon#about to write, iclass 36, count 0 2006.190.08:10:00.00#ibcon#wrote, iclass 36, count 0 2006.190.08:10:00.00#ibcon#about to read 3, iclass 36, count 0 2006.190.08:10:00.02#ibcon#read 3, iclass 36, count 0 2006.190.08:10:00.02#ibcon#about to read 4, iclass 36, count 0 2006.190.08:10:00.02#ibcon#read 4, iclass 36, count 0 2006.190.08:10:00.02#ibcon#about to read 5, iclass 36, count 0 2006.190.08:10:00.02#ibcon#read 5, iclass 36, count 0 2006.190.08:10:00.02#ibcon#about to read 6, iclass 36, count 0 2006.190.08:10:00.02#ibcon#read 6, iclass 36, count 0 2006.190.08:10:00.02#ibcon#end of sib2, iclass 36, count 0 2006.190.08:10:00.02#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:10:00.02#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:10:00.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:10:00.02#ibcon#*before write, iclass 36, count 0 2006.190.08:10:00.02#ibcon#enter sib2, iclass 36, count 0 2006.190.08:10:00.02#ibcon#flushed, iclass 36, count 0 2006.190.08:10:00.02#ibcon#about to write, iclass 36, count 0 2006.190.08:10:00.02#ibcon#wrote, iclass 36, count 0 2006.190.08:10:00.02#ibcon#about to read 3, iclass 36, count 0 2006.190.08:10:00.06#ibcon#read 3, iclass 36, count 0 2006.190.08:10:00.06#ibcon#about to read 4, iclass 36, count 0 2006.190.08:10:00.06#ibcon#read 4, iclass 36, count 0 2006.190.08:10:00.06#ibcon#about to read 5, iclass 36, count 0 2006.190.08:10:00.06#ibcon#read 5, iclass 36, count 0 2006.190.08:10:00.06#ibcon#about to read 6, iclass 36, count 0 2006.190.08:10:00.06#ibcon#read 6, iclass 36, count 0 2006.190.08:10:00.06#ibcon#end of sib2, iclass 36, count 0 2006.190.08:10:00.06#ibcon#*after write, iclass 36, count 0 2006.190.08:10:00.06#ibcon#*before return 0, iclass 36, count 0 2006.190.08:10:00.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:00.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:00.06#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:10:00.06#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:10:00.06$vc4f8/va=7,6 2006.190.08:10:00.06#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.08:10:00.06#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.08:10:00.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:00.06#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:10:00.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:10:00.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:10:00.12#ibcon#enter wrdev, iclass 38, count 2 2006.190.08:10:00.12#ibcon#first serial, iclass 38, count 2 2006.190.08:10:00.12#ibcon#enter sib2, iclass 38, count 2 2006.190.08:10:00.12#ibcon#flushed, iclass 38, count 2 2006.190.08:10:00.12#ibcon#about to write, iclass 38, count 2 2006.190.08:10:00.12#ibcon#wrote, iclass 38, count 2 2006.190.08:10:00.12#ibcon#about to read 3, iclass 38, count 2 2006.190.08:10:00.14#ibcon#read 3, iclass 38, count 2 2006.190.08:10:00.14#ibcon#about to read 4, iclass 38, count 2 2006.190.08:10:00.14#ibcon#read 4, iclass 38, count 2 2006.190.08:10:00.14#ibcon#about to read 5, iclass 38, count 2 2006.190.08:10:00.14#ibcon#read 5, iclass 38, count 2 2006.190.08:10:00.14#ibcon#about to read 6, iclass 38, count 2 2006.190.08:10:00.14#ibcon#read 6, iclass 38, count 2 2006.190.08:10:00.14#ibcon#end of sib2, iclass 38, count 2 2006.190.08:10:00.14#ibcon#*mode == 0, iclass 38, count 2 2006.190.08:10:00.14#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.08:10:00.14#ibcon#[25=AT07-06\r\n] 2006.190.08:10:00.14#ibcon#*before write, iclass 38, count 2 2006.190.08:10:00.14#ibcon#enter sib2, iclass 38, count 2 2006.190.08:10:00.14#ibcon#flushed, iclass 38, count 2 2006.190.08:10:00.14#ibcon#about to write, iclass 38, count 2 2006.190.08:10:00.14#ibcon#wrote, iclass 38, count 2 2006.190.08:10:00.14#ibcon#about to read 3, iclass 38, count 2 2006.190.08:10:00.17#ibcon#read 3, iclass 38, count 2 2006.190.08:10:00.17#ibcon#about to read 4, iclass 38, count 2 2006.190.08:10:00.17#ibcon#read 4, iclass 38, count 2 2006.190.08:10:00.17#ibcon#about to read 5, iclass 38, count 2 2006.190.08:10:00.17#ibcon#read 5, iclass 38, count 2 2006.190.08:10:00.17#ibcon#about to read 6, iclass 38, count 2 2006.190.08:10:00.17#ibcon#read 6, iclass 38, count 2 2006.190.08:10:00.17#ibcon#end of sib2, iclass 38, count 2 2006.190.08:10:00.17#ibcon#*after write, iclass 38, count 2 2006.190.08:10:00.17#ibcon#*before return 0, iclass 38, count 2 2006.190.08:10:00.17#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:10:00.17#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:10:00.17#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.08:10:00.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:00.17#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:10:00.29#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:10:00.29#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:10:00.29#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:10:00.29#ibcon#first serial, iclass 38, count 0 2006.190.08:10:00.29#ibcon#enter sib2, iclass 38, count 0 2006.190.08:10:00.29#ibcon#flushed, iclass 38, count 0 2006.190.08:10:00.29#ibcon#about to write, iclass 38, count 0 2006.190.08:10:00.29#ibcon#wrote, iclass 38, count 0 2006.190.08:10:00.29#ibcon#about to read 3, iclass 38, count 0 2006.190.08:10:00.31#ibcon#read 3, iclass 38, count 0 2006.190.08:10:00.31#ibcon#about to read 4, iclass 38, count 0 2006.190.08:10:00.31#ibcon#read 4, iclass 38, count 0 2006.190.08:10:00.31#ibcon#about to read 5, iclass 38, count 0 2006.190.08:10:00.31#ibcon#read 5, iclass 38, count 0 2006.190.08:10:00.31#ibcon#about to read 6, iclass 38, count 0 2006.190.08:10:00.31#ibcon#read 6, iclass 38, count 0 2006.190.08:10:00.31#ibcon#end of sib2, iclass 38, count 0 2006.190.08:10:00.31#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:10:00.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:10:00.31#ibcon#[25=USB\r\n] 2006.190.08:10:00.31#ibcon#*before write, iclass 38, count 0 2006.190.08:10:00.31#ibcon#enter sib2, iclass 38, count 0 2006.190.08:10:00.31#ibcon#flushed, iclass 38, count 0 2006.190.08:10:00.31#ibcon#about to write, iclass 38, count 0 2006.190.08:10:00.31#ibcon#wrote, iclass 38, count 0 2006.190.08:10:00.31#ibcon#about to read 3, iclass 38, count 0 2006.190.08:10:00.34#ibcon#read 3, iclass 38, count 0 2006.190.08:10:00.34#ibcon#about to read 4, iclass 38, count 0 2006.190.08:10:00.34#ibcon#read 4, iclass 38, count 0 2006.190.08:10:00.34#ibcon#about to read 5, iclass 38, count 0 2006.190.08:10:00.34#ibcon#read 5, iclass 38, count 0 2006.190.08:10:00.34#ibcon#about to read 6, iclass 38, count 0 2006.190.08:10:00.34#ibcon#read 6, iclass 38, count 0 2006.190.08:10:00.34#ibcon#end of sib2, iclass 38, count 0 2006.190.08:10:00.34#ibcon#*after write, iclass 38, count 0 2006.190.08:10:00.34#ibcon#*before return 0, iclass 38, count 0 2006.190.08:10:00.34#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:10:00.34#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:10:00.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:10:00.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:10:00.34$vc4f8/valo=8,852.99 2006.190.08:10:00.34#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.08:10:00.34#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.08:10:00.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:00.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:10:00.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:10:00.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:10:00.34#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:10:00.34#ibcon#first serial, iclass 40, count 0 2006.190.08:10:00.34#ibcon#enter sib2, iclass 40, count 0 2006.190.08:10:00.34#ibcon#flushed, iclass 40, count 0 2006.190.08:10:00.34#ibcon#about to write, iclass 40, count 0 2006.190.08:10:00.34#ibcon#wrote, iclass 40, count 0 2006.190.08:10:00.34#ibcon#about to read 3, iclass 40, count 0 2006.190.08:10:00.36#ibcon#read 3, iclass 40, count 0 2006.190.08:10:00.36#ibcon#about to read 4, iclass 40, count 0 2006.190.08:10:00.36#ibcon#read 4, iclass 40, count 0 2006.190.08:10:00.36#ibcon#about to read 5, iclass 40, count 0 2006.190.08:10:00.36#ibcon#read 5, iclass 40, count 0 2006.190.08:10:00.36#ibcon#about to read 6, iclass 40, count 0 2006.190.08:10:00.36#ibcon#read 6, iclass 40, count 0 2006.190.08:10:00.36#ibcon#end of sib2, iclass 40, count 0 2006.190.08:10:00.36#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:10:00.36#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:10:00.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:10:00.36#ibcon#*before write, iclass 40, count 0 2006.190.08:10:00.36#ibcon#enter sib2, iclass 40, count 0 2006.190.08:10:00.36#ibcon#flushed, iclass 40, count 0 2006.190.08:10:00.36#ibcon#about to write, iclass 40, count 0 2006.190.08:10:00.36#ibcon#wrote, iclass 40, count 0 2006.190.08:10:00.36#ibcon#about to read 3, iclass 40, count 0 2006.190.08:10:00.40#ibcon#read 3, iclass 40, count 0 2006.190.08:10:00.40#ibcon#about to read 4, iclass 40, count 0 2006.190.08:10:00.40#ibcon#read 4, iclass 40, count 0 2006.190.08:10:00.40#ibcon#about to read 5, iclass 40, count 0 2006.190.08:10:00.40#ibcon#read 5, iclass 40, count 0 2006.190.08:10:00.40#ibcon#about to read 6, iclass 40, count 0 2006.190.08:10:00.40#ibcon#read 6, iclass 40, count 0 2006.190.08:10:00.40#ibcon#end of sib2, iclass 40, count 0 2006.190.08:10:00.40#ibcon#*after write, iclass 40, count 0 2006.190.08:10:00.40#ibcon#*before return 0, iclass 40, count 0 2006.190.08:10:00.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:10:00.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:10:00.40#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:10:00.40#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:10:00.40$vc4f8/va=8,6 2006.190.08:10:00.40#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.08:10:00.40#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.08:10:00.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:00.40#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:10:00.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:10:00.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:10:00.46#ibcon#enter wrdev, iclass 4, count 2 2006.190.08:10:00.46#ibcon#first serial, iclass 4, count 2 2006.190.08:10:00.46#ibcon#enter sib2, iclass 4, count 2 2006.190.08:10:00.46#ibcon#flushed, iclass 4, count 2 2006.190.08:10:00.46#ibcon#about to write, iclass 4, count 2 2006.190.08:10:00.46#ibcon#wrote, iclass 4, count 2 2006.190.08:10:00.46#ibcon#about to read 3, iclass 4, count 2 2006.190.08:10:00.48#ibcon#read 3, iclass 4, count 2 2006.190.08:10:00.48#ibcon#about to read 4, iclass 4, count 2 2006.190.08:10:00.48#ibcon#read 4, iclass 4, count 2 2006.190.08:10:00.48#ibcon#about to read 5, iclass 4, count 2 2006.190.08:10:00.48#ibcon#read 5, iclass 4, count 2 2006.190.08:10:00.48#ibcon#about to read 6, iclass 4, count 2 2006.190.08:10:00.48#ibcon#read 6, iclass 4, count 2 2006.190.08:10:00.48#ibcon#end of sib2, iclass 4, count 2 2006.190.08:10:00.48#ibcon#*mode == 0, iclass 4, count 2 2006.190.08:10:00.48#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.08:10:00.48#ibcon#[25=AT08-06\r\n] 2006.190.08:10:00.48#ibcon#*before write, iclass 4, count 2 2006.190.08:10:00.48#ibcon#enter sib2, iclass 4, count 2 2006.190.08:10:00.48#ibcon#flushed, iclass 4, count 2 2006.190.08:10:00.48#ibcon#about to write, iclass 4, count 2 2006.190.08:10:00.48#ibcon#wrote, iclass 4, count 2 2006.190.08:10:00.48#ibcon#about to read 3, iclass 4, count 2 2006.190.08:10:00.51#ibcon#read 3, iclass 4, count 2 2006.190.08:10:00.51#ibcon#about to read 4, iclass 4, count 2 2006.190.08:10:00.51#ibcon#read 4, iclass 4, count 2 2006.190.08:10:00.51#ibcon#about to read 5, iclass 4, count 2 2006.190.08:10:00.51#ibcon#read 5, iclass 4, count 2 2006.190.08:10:00.51#ibcon#about to read 6, iclass 4, count 2 2006.190.08:10:00.51#ibcon#read 6, iclass 4, count 2 2006.190.08:10:00.51#ibcon#end of sib2, iclass 4, count 2 2006.190.08:10:00.51#ibcon#*after write, iclass 4, count 2 2006.190.08:10:00.51#ibcon#*before return 0, iclass 4, count 2 2006.190.08:10:00.51#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:10:00.51#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:10:00.51#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.08:10:00.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:00.51#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:10:00.63#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:10:00.63#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:10:00.63#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:10:00.63#ibcon#first serial, iclass 4, count 0 2006.190.08:10:00.63#ibcon#enter sib2, iclass 4, count 0 2006.190.08:10:00.63#ibcon#flushed, iclass 4, count 0 2006.190.08:10:00.63#ibcon#about to write, iclass 4, count 0 2006.190.08:10:00.63#ibcon#wrote, iclass 4, count 0 2006.190.08:10:00.63#ibcon#about to read 3, iclass 4, count 0 2006.190.08:10:00.65#ibcon#read 3, iclass 4, count 0 2006.190.08:10:00.65#ibcon#about to read 4, iclass 4, count 0 2006.190.08:10:00.65#ibcon#read 4, iclass 4, count 0 2006.190.08:10:00.65#ibcon#about to read 5, iclass 4, count 0 2006.190.08:10:00.65#ibcon#read 5, iclass 4, count 0 2006.190.08:10:00.65#ibcon#about to read 6, iclass 4, count 0 2006.190.08:10:00.65#ibcon#read 6, iclass 4, count 0 2006.190.08:10:00.65#ibcon#end of sib2, iclass 4, count 0 2006.190.08:10:00.65#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:10:00.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:10:00.65#ibcon#[25=USB\r\n] 2006.190.08:10:00.65#ibcon#*before write, iclass 4, count 0 2006.190.08:10:00.65#ibcon#enter sib2, iclass 4, count 0 2006.190.08:10:00.65#ibcon#flushed, iclass 4, count 0 2006.190.08:10:00.65#ibcon#about to write, iclass 4, count 0 2006.190.08:10:00.65#ibcon#wrote, iclass 4, count 0 2006.190.08:10:00.65#ibcon#about to read 3, iclass 4, count 0 2006.190.08:10:00.68#ibcon#read 3, iclass 4, count 0 2006.190.08:10:00.68#ibcon#about to read 4, iclass 4, count 0 2006.190.08:10:00.68#ibcon#read 4, iclass 4, count 0 2006.190.08:10:00.68#ibcon#about to read 5, iclass 4, count 0 2006.190.08:10:00.68#ibcon#read 5, iclass 4, count 0 2006.190.08:10:00.68#ibcon#about to read 6, iclass 4, count 0 2006.190.08:10:00.68#ibcon#read 6, iclass 4, count 0 2006.190.08:10:00.68#ibcon#end of sib2, iclass 4, count 0 2006.190.08:10:00.68#ibcon#*after write, iclass 4, count 0 2006.190.08:10:00.68#ibcon#*before return 0, iclass 4, count 0 2006.190.08:10:00.68#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:10:00.68#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:10:00.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:10:00.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:10:00.68$vc4f8/vblo=1,632.99 2006.190.08:10:00.68#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:10:00.68#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:10:00.68#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:00.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:10:00.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:10:00.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:10:00.68#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:10:00.68#ibcon#first serial, iclass 6, count 0 2006.190.08:10:00.68#ibcon#enter sib2, iclass 6, count 0 2006.190.08:10:00.68#ibcon#flushed, iclass 6, count 0 2006.190.08:10:00.68#ibcon#about to write, iclass 6, count 0 2006.190.08:10:00.68#ibcon#wrote, iclass 6, count 0 2006.190.08:10:00.68#ibcon#about to read 3, iclass 6, count 0 2006.190.08:10:00.70#ibcon#read 3, iclass 6, count 0 2006.190.08:10:00.70#ibcon#about to read 4, iclass 6, count 0 2006.190.08:10:00.70#ibcon#read 4, iclass 6, count 0 2006.190.08:10:00.70#ibcon#about to read 5, iclass 6, count 0 2006.190.08:10:00.70#ibcon#read 5, iclass 6, count 0 2006.190.08:10:00.70#ibcon#about to read 6, iclass 6, count 0 2006.190.08:10:00.70#ibcon#read 6, iclass 6, count 0 2006.190.08:10:00.70#ibcon#end of sib2, iclass 6, count 0 2006.190.08:10:00.70#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:10:00.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:10:00.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:10:00.70#ibcon#*before write, iclass 6, count 0 2006.190.08:10:00.70#ibcon#enter sib2, iclass 6, count 0 2006.190.08:10:00.70#ibcon#flushed, iclass 6, count 0 2006.190.08:10:00.70#ibcon#about to write, iclass 6, count 0 2006.190.08:10:00.70#ibcon#wrote, iclass 6, count 0 2006.190.08:10:00.70#ibcon#about to read 3, iclass 6, count 0 2006.190.08:10:00.74#ibcon#read 3, iclass 6, count 0 2006.190.08:10:00.74#ibcon#about to read 4, iclass 6, count 0 2006.190.08:10:00.74#ibcon#read 4, iclass 6, count 0 2006.190.08:10:00.74#ibcon#about to read 5, iclass 6, count 0 2006.190.08:10:00.74#ibcon#read 5, iclass 6, count 0 2006.190.08:10:00.74#ibcon#about to read 6, iclass 6, count 0 2006.190.08:10:00.74#ibcon#read 6, iclass 6, count 0 2006.190.08:10:00.74#ibcon#end of sib2, iclass 6, count 0 2006.190.08:10:00.74#ibcon#*after write, iclass 6, count 0 2006.190.08:10:00.74#ibcon#*before return 0, iclass 6, count 0 2006.190.08:10:00.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:10:00.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:10:00.74#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:10:00.74#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:10:00.74$vc4f8/vb=1,4 2006.190.08:10:00.74#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.08:10:00.74#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.08:10:00.74#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:00.74#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:10:00.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:10:00.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:10:00.74#ibcon#enter wrdev, iclass 10, count 2 2006.190.08:10:00.74#ibcon#first serial, iclass 10, count 2 2006.190.08:10:00.74#ibcon#enter sib2, iclass 10, count 2 2006.190.08:10:00.74#ibcon#flushed, iclass 10, count 2 2006.190.08:10:00.74#ibcon#about to write, iclass 10, count 2 2006.190.08:10:00.74#ibcon#wrote, iclass 10, count 2 2006.190.08:10:00.74#ibcon#about to read 3, iclass 10, count 2 2006.190.08:10:00.76#ibcon#read 3, iclass 10, count 2 2006.190.08:10:00.76#ibcon#about to read 4, iclass 10, count 2 2006.190.08:10:00.76#ibcon#read 4, iclass 10, count 2 2006.190.08:10:00.76#ibcon#about to read 5, iclass 10, count 2 2006.190.08:10:00.76#ibcon#read 5, iclass 10, count 2 2006.190.08:10:00.76#ibcon#about to read 6, iclass 10, count 2 2006.190.08:10:00.76#ibcon#read 6, iclass 10, count 2 2006.190.08:10:00.76#ibcon#end of sib2, iclass 10, count 2 2006.190.08:10:00.76#ibcon#*mode == 0, iclass 10, count 2 2006.190.08:10:00.76#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.08:10:00.76#ibcon#[27=AT01-04\r\n] 2006.190.08:10:00.76#ibcon#*before write, iclass 10, count 2 2006.190.08:10:00.76#ibcon#enter sib2, iclass 10, count 2 2006.190.08:10:00.76#ibcon#flushed, iclass 10, count 2 2006.190.08:10:00.76#ibcon#about to write, iclass 10, count 2 2006.190.08:10:00.76#ibcon#wrote, iclass 10, count 2 2006.190.08:10:00.76#ibcon#about to read 3, iclass 10, count 2 2006.190.08:10:00.79#ibcon#read 3, iclass 10, count 2 2006.190.08:10:00.79#ibcon#about to read 4, iclass 10, count 2 2006.190.08:10:00.79#ibcon#read 4, iclass 10, count 2 2006.190.08:10:00.79#ibcon#about to read 5, iclass 10, count 2 2006.190.08:10:00.79#ibcon#read 5, iclass 10, count 2 2006.190.08:10:00.79#ibcon#about to read 6, iclass 10, count 2 2006.190.08:10:00.79#ibcon#read 6, iclass 10, count 2 2006.190.08:10:00.79#ibcon#end of sib2, iclass 10, count 2 2006.190.08:10:00.79#ibcon#*after write, iclass 10, count 2 2006.190.08:10:00.79#ibcon#*before return 0, iclass 10, count 2 2006.190.08:10:00.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:10:00.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:10:00.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.08:10:00.79#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:00.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:10:00.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:10:00.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:10:00.91#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:10:00.91#ibcon#first serial, iclass 10, count 0 2006.190.08:10:00.91#ibcon#enter sib2, iclass 10, count 0 2006.190.08:10:00.91#ibcon#flushed, iclass 10, count 0 2006.190.08:10:00.91#ibcon#about to write, iclass 10, count 0 2006.190.08:10:00.91#ibcon#wrote, iclass 10, count 0 2006.190.08:10:00.91#ibcon#about to read 3, iclass 10, count 0 2006.190.08:10:00.93#ibcon#read 3, iclass 10, count 0 2006.190.08:10:00.93#ibcon#about to read 4, iclass 10, count 0 2006.190.08:10:00.93#ibcon#read 4, iclass 10, count 0 2006.190.08:10:00.93#ibcon#about to read 5, iclass 10, count 0 2006.190.08:10:00.93#ibcon#read 5, iclass 10, count 0 2006.190.08:10:00.93#ibcon#about to read 6, iclass 10, count 0 2006.190.08:10:00.93#ibcon#read 6, iclass 10, count 0 2006.190.08:10:00.93#ibcon#end of sib2, iclass 10, count 0 2006.190.08:10:00.93#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:10:00.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:10:00.93#ibcon#[27=USB\r\n] 2006.190.08:10:00.93#ibcon#*before write, iclass 10, count 0 2006.190.08:10:00.93#ibcon#enter sib2, iclass 10, count 0 2006.190.08:10:00.93#ibcon#flushed, iclass 10, count 0 2006.190.08:10:00.93#ibcon#about to write, iclass 10, count 0 2006.190.08:10:00.93#ibcon#wrote, iclass 10, count 0 2006.190.08:10:00.93#ibcon#about to read 3, iclass 10, count 0 2006.190.08:10:00.96#ibcon#read 3, iclass 10, count 0 2006.190.08:10:00.96#ibcon#about to read 4, iclass 10, count 0 2006.190.08:10:00.96#ibcon#read 4, iclass 10, count 0 2006.190.08:10:00.96#ibcon#about to read 5, iclass 10, count 0 2006.190.08:10:00.96#ibcon#read 5, iclass 10, count 0 2006.190.08:10:00.96#ibcon#about to read 6, iclass 10, count 0 2006.190.08:10:00.96#ibcon#read 6, iclass 10, count 0 2006.190.08:10:00.96#ibcon#end of sib2, iclass 10, count 0 2006.190.08:10:00.96#ibcon#*after write, iclass 10, count 0 2006.190.08:10:00.96#ibcon#*before return 0, iclass 10, count 0 2006.190.08:10:00.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:10:00.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:10:00.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:10:00.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:10:00.96$vc4f8/vblo=2,640.99 2006.190.08:10:00.96#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:10:00.96#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:10:00.96#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:00.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:10:00.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:10:00.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:10:00.96#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:10:00.96#ibcon#first serial, iclass 12, count 0 2006.190.08:10:00.96#ibcon#enter sib2, iclass 12, count 0 2006.190.08:10:00.96#ibcon#flushed, iclass 12, count 0 2006.190.08:10:00.96#ibcon#about to write, iclass 12, count 0 2006.190.08:10:00.96#ibcon#wrote, iclass 12, count 0 2006.190.08:10:00.96#ibcon#about to read 3, iclass 12, count 0 2006.190.08:10:00.98#ibcon#read 3, iclass 12, count 0 2006.190.08:10:00.98#ibcon#about to read 4, iclass 12, count 0 2006.190.08:10:00.98#ibcon#read 4, iclass 12, count 0 2006.190.08:10:00.98#ibcon#about to read 5, iclass 12, count 0 2006.190.08:10:00.98#ibcon#read 5, iclass 12, count 0 2006.190.08:10:00.98#ibcon#about to read 6, iclass 12, count 0 2006.190.08:10:00.98#ibcon#read 6, iclass 12, count 0 2006.190.08:10:00.98#ibcon#end of sib2, iclass 12, count 0 2006.190.08:10:00.98#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:10:00.98#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:10:00.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:10:00.98#ibcon#*before write, iclass 12, count 0 2006.190.08:10:00.98#ibcon#enter sib2, iclass 12, count 0 2006.190.08:10:00.98#ibcon#flushed, iclass 12, count 0 2006.190.08:10:00.98#ibcon#about to write, iclass 12, count 0 2006.190.08:10:00.98#ibcon#wrote, iclass 12, count 0 2006.190.08:10:00.98#ibcon#about to read 3, iclass 12, count 0 2006.190.08:10:01.02#ibcon#read 3, iclass 12, count 0 2006.190.08:10:01.02#ibcon#about to read 4, iclass 12, count 0 2006.190.08:10:01.02#ibcon#read 4, iclass 12, count 0 2006.190.08:10:01.02#ibcon#about to read 5, iclass 12, count 0 2006.190.08:10:01.02#ibcon#read 5, iclass 12, count 0 2006.190.08:10:01.02#ibcon#about to read 6, iclass 12, count 0 2006.190.08:10:01.02#ibcon#read 6, iclass 12, count 0 2006.190.08:10:01.02#ibcon#end of sib2, iclass 12, count 0 2006.190.08:10:01.02#ibcon#*after write, iclass 12, count 0 2006.190.08:10:01.02#ibcon#*before return 0, iclass 12, count 0 2006.190.08:10:01.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:10:01.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:10:01.02#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:10:01.02#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:10:01.02$vc4f8/vb=2,4 2006.190.08:10:01.02#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:10:01.02#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:10:01.02#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:01.02#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:10:01.08#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:10:01.08#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:10:01.08#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:10:01.08#ibcon#first serial, iclass 14, count 2 2006.190.08:10:01.08#ibcon#enter sib2, iclass 14, count 2 2006.190.08:10:01.08#ibcon#flushed, iclass 14, count 2 2006.190.08:10:01.08#ibcon#about to write, iclass 14, count 2 2006.190.08:10:01.08#ibcon#wrote, iclass 14, count 2 2006.190.08:10:01.08#ibcon#about to read 3, iclass 14, count 2 2006.190.08:10:01.10#ibcon#read 3, iclass 14, count 2 2006.190.08:10:01.10#ibcon#about to read 4, iclass 14, count 2 2006.190.08:10:01.10#ibcon#read 4, iclass 14, count 2 2006.190.08:10:01.10#ibcon#about to read 5, iclass 14, count 2 2006.190.08:10:01.10#ibcon#read 5, iclass 14, count 2 2006.190.08:10:01.10#ibcon#about to read 6, iclass 14, count 2 2006.190.08:10:01.10#ibcon#read 6, iclass 14, count 2 2006.190.08:10:01.10#ibcon#end of sib2, iclass 14, count 2 2006.190.08:10:01.10#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:10:01.10#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:10:01.10#ibcon#[27=AT02-04\r\n] 2006.190.08:10:01.10#ibcon#*before write, iclass 14, count 2 2006.190.08:10:01.10#ibcon#enter sib2, iclass 14, count 2 2006.190.08:10:01.10#ibcon#flushed, iclass 14, count 2 2006.190.08:10:01.10#ibcon#about to write, iclass 14, count 2 2006.190.08:10:01.10#ibcon#wrote, iclass 14, count 2 2006.190.08:10:01.10#ibcon#about to read 3, iclass 14, count 2 2006.190.08:10:01.13#ibcon#read 3, iclass 14, count 2 2006.190.08:10:01.13#ibcon#about to read 4, iclass 14, count 2 2006.190.08:10:01.13#ibcon#read 4, iclass 14, count 2 2006.190.08:10:01.13#ibcon#about to read 5, iclass 14, count 2 2006.190.08:10:01.13#ibcon#read 5, iclass 14, count 2 2006.190.08:10:01.13#ibcon#about to read 6, iclass 14, count 2 2006.190.08:10:01.13#ibcon#read 6, iclass 14, count 2 2006.190.08:10:01.13#ibcon#end of sib2, iclass 14, count 2 2006.190.08:10:01.13#ibcon#*after write, iclass 14, count 2 2006.190.08:10:01.13#ibcon#*before return 0, iclass 14, count 2 2006.190.08:10:01.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:10:01.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:10:01.13#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:10:01.13#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:01.13#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:10:01.25#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:10:01.25#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:10:01.25#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:10:01.25#ibcon#first serial, iclass 14, count 0 2006.190.08:10:01.25#ibcon#enter sib2, iclass 14, count 0 2006.190.08:10:01.25#ibcon#flushed, iclass 14, count 0 2006.190.08:10:01.25#ibcon#about to write, iclass 14, count 0 2006.190.08:10:01.25#ibcon#wrote, iclass 14, count 0 2006.190.08:10:01.25#ibcon#about to read 3, iclass 14, count 0 2006.190.08:10:01.27#ibcon#read 3, iclass 14, count 0 2006.190.08:10:01.27#ibcon#about to read 4, iclass 14, count 0 2006.190.08:10:01.27#ibcon#read 4, iclass 14, count 0 2006.190.08:10:01.27#ibcon#about to read 5, iclass 14, count 0 2006.190.08:10:01.27#ibcon#read 5, iclass 14, count 0 2006.190.08:10:01.27#ibcon#about to read 6, iclass 14, count 0 2006.190.08:10:01.27#ibcon#read 6, iclass 14, count 0 2006.190.08:10:01.27#ibcon#end of sib2, iclass 14, count 0 2006.190.08:10:01.27#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:10:01.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:10:01.27#ibcon#[27=USB\r\n] 2006.190.08:10:01.27#ibcon#*before write, iclass 14, count 0 2006.190.08:10:01.27#ibcon#enter sib2, iclass 14, count 0 2006.190.08:10:01.27#ibcon#flushed, iclass 14, count 0 2006.190.08:10:01.27#ibcon#about to write, iclass 14, count 0 2006.190.08:10:01.27#ibcon#wrote, iclass 14, count 0 2006.190.08:10:01.27#ibcon#about to read 3, iclass 14, count 0 2006.190.08:10:01.30#ibcon#read 3, iclass 14, count 0 2006.190.08:10:01.30#ibcon#about to read 4, iclass 14, count 0 2006.190.08:10:01.30#ibcon#read 4, iclass 14, count 0 2006.190.08:10:01.30#ibcon#about to read 5, iclass 14, count 0 2006.190.08:10:01.30#ibcon#read 5, iclass 14, count 0 2006.190.08:10:01.30#ibcon#about to read 6, iclass 14, count 0 2006.190.08:10:01.30#ibcon#read 6, iclass 14, count 0 2006.190.08:10:01.30#ibcon#end of sib2, iclass 14, count 0 2006.190.08:10:01.30#ibcon#*after write, iclass 14, count 0 2006.190.08:10:01.30#ibcon#*before return 0, iclass 14, count 0 2006.190.08:10:01.30#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:10:01.30#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:10:01.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:10:01.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:10:01.30$vc4f8/vblo=3,656.99 2006.190.08:10:01.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:10:01.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:10:01.30#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:01.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:10:01.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:10:01.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:10:01.30#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:10:01.30#ibcon#first serial, iclass 16, count 0 2006.190.08:10:01.30#ibcon#enter sib2, iclass 16, count 0 2006.190.08:10:01.30#ibcon#flushed, iclass 16, count 0 2006.190.08:10:01.30#ibcon#about to write, iclass 16, count 0 2006.190.08:10:01.30#ibcon#wrote, iclass 16, count 0 2006.190.08:10:01.30#ibcon#about to read 3, iclass 16, count 0 2006.190.08:10:01.32#ibcon#read 3, iclass 16, count 0 2006.190.08:10:01.32#ibcon#about to read 4, iclass 16, count 0 2006.190.08:10:01.32#ibcon#read 4, iclass 16, count 0 2006.190.08:10:01.32#ibcon#about to read 5, iclass 16, count 0 2006.190.08:10:01.32#ibcon#read 5, iclass 16, count 0 2006.190.08:10:01.32#ibcon#about to read 6, iclass 16, count 0 2006.190.08:10:01.32#ibcon#read 6, iclass 16, count 0 2006.190.08:10:01.32#ibcon#end of sib2, iclass 16, count 0 2006.190.08:10:01.32#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:10:01.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:10:01.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:10:01.32#ibcon#*before write, iclass 16, count 0 2006.190.08:10:01.32#ibcon#enter sib2, iclass 16, count 0 2006.190.08:10:01.32#ibcon#flushed, iclass 16, count 0 2006.190.08:10:01.32#ibcon#about to write, iclass 16, count 0 2006.190.08:10:01.32#ibcon#wrote, iclass 16, count 0 2006.190.08:10:01.32#ibcon#about to read 3, iclass 16, count 0 2006.190.08:10:01.36#ibcon#read 3, iclass 16, count 0 2006.190.08:10:01.36#ibcon#about to read 4, iclass 16, count 0 2006.190.08:10:01.36#ibcon#read 4, iclass 16, count 0 2006.190.08:10:01.36#ibcon#about to read 5, iclass 16, count 0 2006.190.08:10:01.36#ibcon#read 5, iclass 16, count 0 2006.190.08:10:01.36#ibcon#about to read 6, iclass 16, count 0 2006.190.08:10:01.36#ibcon#read 6, iclass 16, count 0 2006.190.08:10:01.36#ibcon#end of sib2, iclass 16, count 0 2006.190.08:10:01.36#ibcon#*after write, iclass 16, count 0 2006.190.08:10:01.36#ibcon#*before return 0, iclass 16, count 0 2006.190.08:10:01.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:10:01.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:10:01.36#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:10:01.36#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:10:01.36$vc4f8/vb=3,4 2006.190.08:10:01.36#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.08:10:01.36#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.08:10:01.36#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:01.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:10:01.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:10:01.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:10:01.42#ibcon#enter wrdev, iclass 18, count 2 2006.190.08:10:01.42#ibcon#first serial, iclass 18, count 2 2006.190.08:10:01.42#ibcon#enter sib2, iclass 18, count 2 2006.190.08:10:01.42#ibcon#flushed, iclass 18, count 2 2006.190.08:10:01.42#ibcon#about to write, iclass 18, count 2 2006.190.08:10:01.42#ibcon#wrote, iclass 18, count 2 2006.190.08:10:01.42#ibcon#about to read 3, iclass 18, count 2 2006.190.08:10:01.44#ibcon#read 3, iclass 18, count 2 2006.190.08:10:01.44#ibcon#about to read 4, iclass 18, count 2 2006.190.08:10:01.44#ibcon#read 4, iclass 18, count 2 2006.190.08:10:01.44#ibcon#about to read 5, iclass 18, count 2 2006.190.08:10:01.44#ibcon#read 5, iclass 18, count 2 2006.190.08:10:01.44#ibcon#about to read 6, iclass 18, count 2 2006.190.08:10:01.44#ibcon#read 6, iclass 18, count 2 2006.190.08:10:01.44#ibcon#end of sib2, iclass 18, count 2 2006.190.08:10:01.44#ibcon#*mode == 0, iclass 18, count 2 2006.190.08:10:01.44#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.08:10:01.44#ibcon#[27=AT03-04\r\n] 2006.190.08:10:01.44#ibcon#*before write, iclass 18, count 2 2006.190.08:10:01.44#ibcon#enter sib2, iclass 18, count 2 2006.190.08:10:01.44#ibcon#flushed, iclass 18, count 2 2006.190.08:10:01.44#ibcon#about to write, iclass 18, count 2 2006.190.08:10:01.44#ibcon#wrote, iclass 18, count 2 2006.190.08:10:01.44#ibcon#about to read 3, iclass 18, count 2 2006.190.08:10:01.47#ibcon#read 3, iclass 18, count 2 2006.190.08:10:01.47#ibcon#about to read 4, iclass 18, count 2 2006.190.08:10:01.47#ibcon#read 4, iclass 18, count 2 2006.190.08:10:01.47#ibcon#about to read 5, iclass 18, count 2 2006.190.08:10:01.47#ibcon#read 5, iclass 18, count 2 2006.190.08:10:01.47#ibcon#about to read 6, iclass 18, count 2 2006.190.08:10:01.47#ibcon#read 6, iclass 18, count 2 2006.190.08:10:01.47#ibcon#end of sib2, iclass 18, count 2 2006.190.08:10:01.47#ibcon#*after write, iclass 18, count 2 2006.190.08:10:01.47#ibcon#*before return 0, iclass 18, count 2 2006.190.08:10:01.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:10:01.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:10:01.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.08:10:01.47#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:01.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:10:01.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:10:01.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:10:01.59#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:10:01.59#ibcon#first serial, iclass 18, count 0 2006.190.08:10:01.59#ibcon#enter sib2, iclass 18, count 0 2006.190.08:10:01.59#ibcon#flushed, iclass 18, count 0 2006.190.08:10:01.59#ibcon#about to write, iclass 18, count 0 2006.190.08:10:01.59#ibcon#wrote, iclass 18, count 0 2006.190.08:10:01.59#ibcon#about to read 3, iclass 18, count 0 2006.190.08:10:01.61#ibcon#read 3, iclass 18, count 0 2006.190.08:10:01.61#ibcon#about to read 4, iclass 18, count 0 2006.190.08:10:01.61#ibcon#read 4, iclass 18, count 0 2006.190.08:10:01.61#ibcon#about to read 5, iclass 18, count 0 2006.190.08:10:01.61#ibcon#read 5, iclass 18, count 0 2006.190.08:10:01.61#ibcon#about to read 6, iclass 18, count 0 2006.190.08:10:01.61#ibcon#read 6, iclass 18, count 0 2006.190.08:10:01.61#ibcon#end of sib2, iclass 18, count 0 2006.190.08:10:01.61#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:10:01.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:10:01.61#ibcon#[27=USB\r\n] 2006.190.08:10:01.61#ibcon#*before write, iclass 18, count 0 2006.190.08:10:01.61#ibcon#enter sib2, iclass 18, count 0 2006.190.08:10:01.61#ibcon#flushed, iclass 18, count 0 2006.190.08:10:01.61#ibcon#about to write, iclass 18, count 0 2006.190.08:10:01.61#ibcon#wrote, iclass 18, count 0 2006.190.08:10:01.61#ibcon#about to read 3, iclass 18, count 0 2006.190.08:10:01.64#ibcon#read 3, iclass 18, count 0 2006.190.08:10:01.64#ibcon#about to read 4, iclass 18, count 0 2006.190.08:10:01.64#ibcon#read 4, iclass 18, count 0 2006.190.08:10:01.64#ibcon#about to read 5, iclass 18, count 0 2006.190.08:10:01.64#ibcon#read 5, iclass 18, count 0 2006.190.08:10:01.64#ibcon#about to read 6, iclass 18, count 0 2006.190.08:10:01.64#ibcon#read 6, iclass 18, count 0 2006.190.08:10:01.64#ibcon#end of sib2, iclass 18, count 0 2006.190.08:10:01.64#ibcon#*after write, iclass 18, count 0 2006.190.08:10:01.64#ibcon#*before return 0, iclass 18, count 0 2006.190.08:10:01.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:10:01.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:10:01.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:10:01.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:10:01.64$vc4f8/vblo=4,712.99 2006.190.08:10:01.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.08:10:01.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.08:10:01.64#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:01.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:10:01.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:10:01.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:10:01.64#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:10:01.64#ibcon#first serial, iclass 20, count 0 2006.190.08:10:01.64#ibcon#enter sib2, iclass 20, count 0 2006.190.08:10:01.64#ibcon#flushed, iclass 20, count 0 2006.190.08:10:01.64#ibcon#about to write, iclass 20, count 0 2006.190.08:10:01.64#ibcon#wrote, iclass 20, count 0 2006.190.08:10:01.64#ibcon#about to read 3, iclass 20, count 0 2006.190.08:10:01.66#ibcon#read 3, iclass 20, count 0 2006.190.08:10:01.66#ibcon#about to read 4, iclass 20, count 0 2006.190.08:10:01.66#ibcon#read 4, iclass 20, count 0 2006.190.08:10:01.66#ibcon#about to read 5, iclass 20, count 0 2006.190.08:10:01.66#ibcon#read 5, iclass 20, count 0 2006.190.08:10:01.66#ibcon#about to read 6, iclass 20, count 0 2006.190.08:10:01.66#ibcon#read 6, iclass 20, count 0 2006.190.08:10:01.66#ibcon#end of sib2, iclass 20, count 0 2006.190.08:10:01.66#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:10:01.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:10:01.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:10:01.66#ibcon#*before write, iclass 20, count 0 2006.190.08:10:01.66#ibcon#enter sib2, iclass 20, count 0 2006.190.08:10:01.66#ibcon#flushed, iclass 20, count 0 2006.190.08:10:01.66#ibcon#about to write, iclass 20, count 0 2006.190.08:10:01.66#ibcon#wrote, iclass 20, count 0 2006.190.08:10:01.66#ibcon#about to read 3, iclass 20, count 0 2006.190.08:10:01.70#ibcon#read 3, iclass 20, count 0 2006.190.08:10:01.70#ibcon#about to read 4, iclass 20, count 0 2006.190.08:10:01.70#ibcon#read 4, iclass 20, count 0 2006.190.08:10:01.70#ibcon#about to read 5, iclass 20, count 0 2006.190.08:10:01.70#ibcon#read 5, iclass 20, count 0 2006.190.08:10:01.70#ibcon#about to read 6, iclass 20, count 0 2006.190.08:10:01.70#ibcon#read 6, iclass 20, count 0 2006.190.08:10:01.70#ibcon#end of sib2, iclass 20, count 0 2006.190.08:10:01.70#ibcon#*after write, iclass 20, count 0 2006.190.08:10:01.70#ibcon#*before return 0, iclass 20, count 0 2006.190.08:10:01.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:10:01.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:10:01.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:10:01.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:10:01.70$vc4f8/vb=4,4 2006.190.08:10:01.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.08:10:01.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.08:10:01.70#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:01.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:10:01.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:10:01.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:10:01.76#ibcon#enter wrdev, iclass 22, count 2 2006.190.08:10:01.76#ibcon#first serial, iclass 22, count 2 2006.190.08:10:01.76#ibcon#enter sib2, iclass 22, count 2 2006.190.08:10:01.76#ibcon#flushed, iclass 22, count 2 2006.190.08:10:01.76#ibcon#about to write, iclass 22, count 2 2006.190.08:10:01.76#ibcon#wrote, iclass 22, count 2 2006.190.08:10:01.76#ibcon#about to read 3, iclass 22, count 2 2006.190.08:10:01.78#ibcon#read 3, iclass 22, count 2 2006.190.08:10:01.78#ibcon#about to read 4, iclass 22, count 2 2006.190.08:10:01.78#ibcon#read 4, iclass 22, count 2 2006.190.08:10:01.78#ibcon#about to read 5, iclass 22, count 2 2006.190.08:10:01.78#ibcon#read 5, iclass 22, count 2 2006.190.08:10:01.78#ibcon#about to read 6, iclass 22, count 2 2006.190.08:10:01.78#ibcon#read 6, iclass 22, count 2 2006.190.08:10:01.78#ibcon#end of sib2, iclass 22, count 2 2006.190.08:10:01.78#ibcon#*mode == 0, iclass 22, count 2 2006.190.08:10:01.78#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.08:10:01.78#ibcon#[27=AT04-04\r\n] 2006.190.08:10:01.78#ibcon#*before write, iclass 22, count 2 2006.190.08:10:01.78#ibcon#enter sib2, iclass 22, count 2 2006.190.08:10:01.78#ibcon#flushed, iclass 22, count 2 2006.190.08:10:01.78#ibcon#about to write, iclass 22, count 2 2006.190.08:10:01.78#ibcon#wrote, iclass 22, count 2 2006.190.08:10:01.78#ibcon#about to read 3, iclass 22, count 2 2006.190.08:10:01.81#ibcon#read 3, iclass 22, count 2 2006.190.08:10:01.81#ibcon#about to read 4, iclass 22, count 2 2006.190.08:10:01.81#ibcon#read 4, iclass 22, count 2 2006.190.08:10:01.81#ibcon#about to read 5, iclass 22, count 2 2006.190.08:10:01.81#ibcon#read 5, iclass 22, count 2 2006.190.08:10:01.81#ibcon#about to read 6, iclass 22, count 2 2006.190.08:10:01.81#ibcon#read 6, iclass 22, count 2 2006.190.08:10:01.81#ibcon#end of sib2, iclass 22, count 2 2006.190.08:10:01.81#ibcon#*after write, iclass 22, count 2 2006.190.08:10:01.81#ibcon#*before return 0, iclass 22, count 2 2006.190.08:10:01.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:10:01.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:10:01.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.08:10:01.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:01.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:10:01.86#abcon#<5=/04 2.5 4.3 24.421001012.1\r\n> 2006.190.08:10:01.88#abcon#{5=INTERFACE CLEAR} 2006.190.08:10:01.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:10:01.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:10:01.93#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:10:01.93#ibcon#first serial, iclass 22, count 0 2006.190.08:10:01.93#ibcon#enter sib2, iclass 22, count 0 2006.190.08:10:01.93#ibcon#flushed, iclass 22, count 0 2006.190.08:10:01.93#ibcon#about to write, iclass 22, count 0 2006.190.08:10:01.93#ibcon#wrote, iclass 22, count 0 2006.190.08:10:01.93#ibcon#about to read 3, iclass 22, count 0 2006.190.08:10:01.94#abcon#[5=S1D000X0/0*\r\n] 2006.190.08:10:01.95#ibcon#read 3, iclass 22, count 0 2006.190.08:10:01.95#ibcon#about to read 4, iclass 22, count 0 2006.190.08:10:01.95#ibcon#read 4, iclass 22, count 0 2006.190.08:10:01.95#ibcon#about to read 5, iclass 22, count 0 2006.190.08:10:01.95#ibcon#read 5, iclass 22, count 0 2006.190.08:10:01.95#ibcon#about to read 6, iclass 22, count 0 2006.190.08:10:01.95#ibcon#read 6, iclass 22, count 0 2006.190.08:10:01.95#ibcon#end of sib2, iclass 22, count 0 2006.190.08:10:01.95#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:10:01.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:10:01.95#ibcon#[27=USB\r\n] 2006.190.08:10:01.95#ibcon#*before write, iclass 22, count 0 2006.190.08:10:01.95#ibcon#enter sib2, iclass 22, count 0 2006.190.08:10:01.95#ibcon#flushed, iclass 22, count 0 2006.190.08:10:01.95#ibcon#about to write, iclass 22, count 0 2006.190.08:10:01.95#ibcon#wrote, iclass 22, count 0 2006.190.08:10:01.95#ibcon#about to read 3, iclass 22, count 0 2006.190.08:10:01.98#ibcon#read 3, iclass 22, count 0 2006.190.08:10:01.98#ibcon#about to read 4, iclass 22, count 0 2006.190.08:10:01.98#ibcon#read 4, iclass 22, count 0 2006.190.08:10:01.98#ibcon#about to read 5, iclass 22, count 0 2006.190.08:10:01.98#ibcon#read 5, iclass 22, count 0 2006.190.08:10:01.98#ibcon#about to read 6, iclass 22, count 0 2006.190.08:10:01.98#ibcon#read 6, iclass 22, count 0 2006.190.08:10:01.98#ibcon#end of sib2, iclass 22, count 0 2006.190.08:10:01.98#ibcon#*after write, iclass 22, count 0 2006.190.08:10:01.98#ibcon#*before return 0, iclass 22, count 0 2006.190.08:10:01.98#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:10:01.98#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:10:01.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:10:01.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:10:01.98$vc4f8/vblo=5,744.99 2006.190.08:10:01.98#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.08:10:01.98#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.08:10:01.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:01.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:10:01.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:10:01.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:10:01.98#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:10:01.98#ibcon#first serial, iclass 28, count 0 2006.190.08:10:01.98#ibcon#enter sib2, iclass 28, count 0 2006.190.08:10:01.98#ibcon#flushed, iclass 28, count 0 2006.190.08:10:01.98#ibcon#about to write, iclass 28, count 0 2006.190.08:10:01.98#ibcon#wrote, iclass 28, count 0 2006.190.08:10:01.98#ibcon#about to read 3, iclass 28, count 0 2006.190.08:10:02.00#ibcon#read 3, iclass 28, count 0 2006.190.08:10:02.00#ibcon#about to read 4, iclass 28, count 0 2006.190.08:10:02.00#ibcon#read 4, iclass 28, count 0 2006.190.08:10:02.00#ibcon#about to read 5, iclass 28, count 0 2006.190.08:10:02.00#ibcon#read 5, iclass 28, count 0 2006.190.08:10:02.00#ibcon#about to read 6, iclass 28, count 0 2006.190.08:10:02.00#ibcon#read 6, iclass 28, count 0 2006.190.08:10:02.00#ibcon#end of sib2, iclass 28, count 0 2006.190.08:10:02.00#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:10:02.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:10:02.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:10:02.00#ibcon#*before write, iclass 28, count 0 2006.190.08:10:02.00#ibcon#enter sib2, iclass 28, count 0 2006.190.08:10:02.00#ibcon#flushed, iclass 28, count 0 2006.190.08:10:02.00#ibcon#about to write, iclass 28, count 0 2006.190.08:10:02.00#ibcon#wrote, iclass 28, count 0 2006.190.08:10:02.00#ibcon#about to read 3, iclass 28, count 0 2006.190.08:10:02.04#ibcon#read 3, iclass 28, count 0 2006.190.08:10:02.04#ibcon#about to read 4, iclass 28, count 0 2006.190.08:10:02.04#ibcon#read 4, iclass 28, count 0 2006.190.08:10:02.04#ibcon#about to read 5, iclass 28, count 0 2006.190.08:10:02.04#ibcon#read 5, iclass 28, count 0 2006.190.08:10:02.04#ibcon#about to read 6, iclass 28, count 0 2006.190.08:10:02.04#ibcon#read 6, iclass 28, count 0 2006.190.08:10:02.04#ibcon#end of sib2, iclass 28, count 0 2006.190.08:10:02.04#ibcon#*after write, iclass 28, count 0 2006.190.08:10:02.04#ibcon#*before return 0, iclass 28, count 0 2006.190.08:10:02.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:10:02.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:10:02.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:10:02.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:10:02.04$vc4f8/vb=5,4 2006.190.08:10:02.04#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.08:10:02.04#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.08:10:02.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:02.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:10:02.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:10:02.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:10:02.10#ibcon#enter wrdev, iclass 30, count 2 2006.190.08:10:02.10#ibcon#first serial, iclass 30, count 2 2006.190.08:10:02.10#ibcon#enter sib2, iclass 30, count 2 2006.190.08:10:02.10#ibcon#flushed, iclass 30, count 2 2006.190.08:10:02.10#ibcon#about to write, iclass 30, count 2 2006.190.08:10:02.10#ibcon#wrote, iclass 30, count 2 2006.190.08:10:02.10#ibcon#about to read 3, iclass 30, count 2 2006.190.08:10:02.12#ibcon#read 3, iclass 30, count 2 2006.190.08:10:02.12#ibcon#about to read 4, iclass 30, count 2 2006.190.08:10:02.12#ibcon#read 4, iclass 30, count 2 2006.190.08:10:02.12#ibcon#about to read 5, iclass 30, count 2 2006.190.08:10:02.12#ibcon#read 5, iclass 30, count 2 2006.190.08:10:02.12#ibcon#about to read 6, iclass 30, count 2 2006.190.08:10:02.12#ibcon#read 6, iclass 30, count 2 2006.190.08:10:02.12#ibcon#end of sib2, iclass 30, count 2 2006.190.08:10:02.12#ibcon#*mode == 0, iclass 30, count 2 2006.190.08:10:02.12#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.08:10:02.12#ibcon#[27=AT05-04\r\n] 2006.190.08:10:02.12#ibcon#*before write, iclass 30, count 2 2006.190.08:10:02.12#ibcon#enter sib2, iclass 30, count 2 2006.190.08:10:02.12#ibcon#flushed, iclass 30, count 2 2006.190.08:10:02.12#ibcon#about to write, iclass 30, count 2 2006.190.08:10:02.12#ibcon#wrote, iclass 30, count 2 2006.190.08:10:02.12#ibcon#about to read 3, iclass 30, count 2 2006.190.08:10:02.15#ibcon#read 3, iclass 30, count 2 2006.190.08:10:02.15#ibcon#about to read 4, iclass 30, count 2 2006.190.08:10:02.15#ibcon#read 4, iclass 30, count 2 2006.190.08:10:02.15#ibcon#about to read 5, iclass 30, count 2 2006.190.08:10:02.15#ibcon#read 5, iclass 30, count 2 2006.190.08:10:02.15#ibcon#about to read 6, iclass 30, count 2 2006.190.08:10:02.15#ibcon#read 6, iclass 30, count 2 2006.190.08:10:02.15#ibcon#end of sib2, iclass 30, count 2 2006.190.08:10:02.15#ibcon#*after write, iclass 30, count 2 2006.190.08:10:02.15#ibcon#*before return 0, iclass 30, count 2 2006.190.08:10:02.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:10:02.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:10:02.15#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.08:10:02.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:02.15#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:10:02.27#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:10:02.27#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:10:02.27#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:10:02.27#ibcon#first serial, iclass 30, count 0 2006.190.08:10:02.27#ibcon#enter sib2, iclass 30, count 0 2006.190.08:10:02.27#ibcon#flushed, iclass 30, count 0 2006.190.08:10:02.27#ibcon#about to write, iclass 30, count 0 2006.190.08:10:02.27#ibcon#wrote, iclass 30, count 0 2006.190.08:10:02.27#ibcon#about to read 3, iclass 30, count 0 2006.190.08:10:02.29#ibcon#read 3, iclass 30, count 0 2006.190.08:10:02.29#ibcon#about to read 4, iclass 30, count 0 2006.190.08:10:02.29#ibcon#read 4, iclass 30, count 0 2006.190.08:10:02.29#ibcon#about to read 5, iclass 30, count 0 2006.190.08:10:02.29#ibcon#read 5, iclass 30, count 0 2006.190.08:10:02.29#ibcon#about to read 6, iclass 30, count 0 2006.190.08:10:02.29#ibcon#read 6, iclass 30, count 0 2006.190.08:10:02.29#ibcon#end of sib2, iclass 30, count 0 2006.190.08:10:02.29#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:10:02.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:10:02.29#ibcon#[27=USB\r\n] 2006.190.08:10:02.29#ibcon#*before write, iclass 30, count 0 2006.190.08:10:02.29#ibcon#enter sib2, iclass 30, count 0 2006.190.08:10:02.29#ibcon#flushed, iclass 30, count 0 2006.190.08:10:02.29#ibcon#about to write, iclass 30, count 0 2006.190.08:10:02.29#ibcon#wrote, iclass 30, count 0 2006.190.08:10:02.29#ibcon#about to read 3, iclass 30, count 0 2006.190.08:10:02.32#ibcon#read 3, iclass 30, count 0 2006.190.08:10:02.32#ibcon#about to read 4, iclass 30, count 0 2006.190.08:10:02.32#ibcon#read 4, iclass 30, count 0 2006.190.08:10:02.32#ibcon#about to read 5, iclass 30, count 0 2006.190.08:10:02.32#ibcon#read 5, iclass 30, count 0 2006.190.08:10:02.32#ibcon#about to read 6, iclass 30, count 0 2006.190.08:10:02.32#ibcon#read 6, iclass 30, count 0 2006.190.08:10:02.32#ibcon#end of sib2, iclass 30, count 0 2006.190.08:10:02.32#ibcon#*after write, iclass 30, count 0 2006.190.08:10:02.32#ibcon#*before return 0, iclass 30, count 0 2006.190.08:10:02.32#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:10:02.32#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:10:02.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:10:02.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:10:02.32$vc4f8/vblo=6,752.99 2006.190.08:10:02.32#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.08:10:02.32#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.08:10:02.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:10:02.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:10:02.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:10:02.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:10:02.32#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:10:02.32#ibcon#first serial, iclass 32, count 0 2006.190.08:10:02.32#ibcon#enter sib2, iclass 32, count 0 2006.190.08:10:02.32#ibcon#flushed, iclass 32, count 0 2006.190.08:10:02.32#ibcon#about to write, iclass 32, count 0 2006.190.08:10:02.32#ibcon#wrote, iclass 32, count 0 2006.190.08:10:02.32#ibcon#about to read 3, iclass 32, count 0 2006.190.08:10:02.34#ibcon#read 3, iclass 32, count 0 2006.190.08:10:02.34#ibcon#about to read 4, iclass 32, count 0 2006.190.08:10:02.34#ibcon#read 4, iclass 32, count 0 2006.190.08:10:02.34#ibcon#about to read 5, iclass 32, count 0 2006.190.08:10:02.34#ibcon#read 5, iclass 32, count 0 2006.190.08:10:02.34#ibcon#about to read 6, iclass 32, count 0 2006.190.08:10:02.34#ibcon#read 6, iclass 32, count 0 2006.190.08:10:02.34#ibcon#end of sib2, iclass 32, count 0 2006.190.08:10:02.34#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:10:02.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:10:02.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:10:02.34#ibcon#*before write, iclass 32, count 0 2006.190.08:10:02.34#ibcon#enter sib2, iclass 32, count 0 2006.190.08:10:02.34#ibcon#flushed, iclass 32, count 0 2006.190.08:10:02.34#ibcon#about to write, iclass 32, count 0 2006.190.08:10:02.34#ibcon#wrote, iclass 32, count 0 2006.190.08:10:02.34#ibcon#about to read 3, iclass 32, count 0 2006.190.08:10:02.38#ibcon#read 3, iclass 32, count 0 2006.190.08:10:02.38#ibcon#about to read 4, iclass 32, count 0 2006.190.08:10:02.38#ibcon#read 4, iclass 32, count 0 2006.190.08:10:02.38#ibcon#about to read 5, iclass 32, count 0 2006.190.08:10:02.38#ibcon#read 5, iclass 32, count 0 2006.190.08:10:02.38#ibcon#about to read 6, iclass 32, count 0 2006.190.08:10:02.38#ibcon#read 6, iclass 32, count 0 2006.190.08:10:02.38#ibcon#end of sib2, iclass 32, count 0 2006.190.08:10:02.38#ibcon#*after write, iclass 32, count 0 2006.190.08:10:02.38#ibcon#*before return 0, iclass 32, count 0 2006.190.08:10:02.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:10:02.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:10:02.38#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:10:02.38#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:10:02.38$vc4f8/vb=6,4 2006.190.08:10:02.38#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.08:10:02.38#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.08:10:02.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:10:02.38#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:10:02.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:10:02.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:10:02.44#ibcon#enter wrdev, iclass 34, count 2 2006.190.08:10:02.44#ibcon#first serial, iclass 34, count 2 2006.190.08:10:02.44#ibcon#enter sib2, iclass 34, count 2 2006.190.08:10:02.44#ibcon#flushed, iclass 34, count 2 2006.190.08:10:02.44#ibcon#about to write, iclass 34, count 2 2006.190.08:10:02.44#ibcon#wrote, iclass 34, count 2 2006.190.08:10:02.44#ibcon#about to read 3, iclass 34, count 2 2006.190.08:10:02.46#ibcon#read 3, iclass 34, count 2 2006.190.08:10:02.46#ibcon#about to read 4, iclass 34, count 2 2006.190.08:10:02.46#ibcon#read 4, iclass 34, count 2 2006.190.08:10:02.46#ibcon#about to read 5, iclass 34, count 2 2006.190.08:10:02.46#ibcon#read 5, iclass 34, count 2 2006.190.08:10:02.46#ibcon#about to read 6, iclass 34, count 2 2006.190.08:10:02.46#ibcon#read 6, iclass 34, count 2 2006.190.08:10:02.46#ibcon#end of sib2, iclass 34, count 2 2006.190.08:10:02.46#ibcon#*mode == 0, iclass 34, count 2 2006.190.08:10:02.46#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.08:10:02.46#ibcon#[27=AT06-04\r\n] 2006.190.08:10:02.46#ibcon#*before write, iclass 34, count 2 2006.190.08:10:02.46#ibcon#enter sib2, iclass 34, count 2 2006.190.08:10:02.46#ibcon#flushed, iclass 34, count 2 2006.190.08:10:02.46#ibcon#about to write, iclass 34, count 2 2006.190.08:10:02.46#ibcon#wrote, iclass 34, count 2 2006.190.08:10:02.46#ibcon#about to read 3, iclass 34, count 2 2006.190.08:10:02.49#ibcon#read 3, iclass 34, count 2 2006.190.08:10:02.49#ibcon#about to read 4, iclass 34, count 2 2006.190.08:10:02.49#ibcon#read 4, iclass 34, count 2 2006.190.08:10:02.49#ibcon#about to read 5, iclass 34, count 2 2006.190.08:10:02.49#ibcon#read 5, iclass 34, count 2 2006.190.08:10:02.49#ibcon#about to read 6, iclass 34, count 2 2006.190.08:10:02.49#ibcon#read 6, iclass 34, count 2 2006.190.08:10:02.49#ibcon#end of sib2, iclass 34, count 2 2006.190.08:10:02.49#ibcon#*after write, iclass 34, count 2 2006.190.08:10:02.49#ibcon#*before return 0, iclass 34, count 2 2006.190.08:10:02.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:10:02.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:10:02.49#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.08:10:02.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:10:02.49#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:10:02.61#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:10:02.61#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:10:02.61#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:10:02.61#ibcon#first serial, iclass 34, count 0 2006.190.08:10:02.61#ibcon#enter sib2, iclass 34, count 0 2006.190.08:10:02.61#ibcon#flushed, iclass 34, count 0 2006.190.08:10:02.61#ibcon#about to write, iclass 34, count 0 2006.190.08:10:02.61#ibcon#wrote, iclass 34, count 0 2006.190.08:10:02.61#ibcon#about to read 3, iclass 34, count 0 2006.190.08:10:02.63#ibcon#read 3, iclass 34, count 0 2006.190.08:10:02.63#ibcon#about to read 4, iclass 34, count 0 2006.190.08:10:02.63#ibcon#read 4, iclass 34, count 0 2006.190.08:10:02.63#ibcon#about to read 5, iclass 34, count 0 2006.190.08:10:02.63#ibcon#read 5, iclass 34, count 0 2006.190.08:10:02.63#ibcon#about to read 6, iclass 34, count 0 2006.190.08:10:02.63#ibcon#read 6, iclass 34, count 0 2006.190.08:10:02.63#ibcon#end of sib2, iclass 34, count 0 2006.190.08:10:02.63#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:10:02.63#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:10:02.63#ibcon#[27=USB\r\n] 2006.190.08:10:02.63#ibcon#*before write, iclass 34, count 0 2006.190.08:10:02.63#ibcon#enter sib2, iclass 34, count 0 2006.190.08:10:02.63#ibcon#flushed, iclass 34, count 0 2006.190.08:10:02.63#ibcon#about to write, iclass 34, count 0 2006.190.08:10:02.63#ibcon#wrote, iclass 34, count 0 2006.190.08:10:02.63#ibcon#about to read 3, iclass 34, count 0 2006.190.08:10:02.66#ibcon#read 3, iclass 34, count 0 2006.190.08:10:02.66#ibcon#about to read 4, iclass 34, count 0 2006.190.08:10:02.66#ibcon#read 4, iclass 34, count 0 2006.190.08:10:02.66#ibcon#about to read 5, iclass 34, count 0 2006.190.08:10:02.66#ibcon#read 5, iclass 34, count 0 2006.190.08:10:02.66#ibcon#about to read 6, iclass 34, count 0 2006.190.08:10:02.66#ibcon#read 6, iclass 34, count 0 2006.190.08:10:02.66#ibcon#end of sib2, iclass 34, count 0 2006.190.08:10:02.66#ibcon#*after write, iclass 34, count 0 2006.190.08:10:02.66#ibcon#*before return 0, iclass 34, count 0 2006.190.08:10:02.66#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:10:02.66#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:10:02.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:10:02.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:10:02.66$vc4f8/vabw=wide 2006.190.08:10:02.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.08:10:02.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.08:10:02.66#ibcon#ireg 8 cls_cnt 0 2006.190.08:10:02.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:02.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:02.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:02.66#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:10:02.66#ibcon#first serial, iclass 36, count 0 2006.190.08:10:02.66#ibcon#enter sib2, iclass 36, count 0 2006.190.08:10:02.66#ibcon#flushed, iclass 36, count 0 2006.190.08:10:02.66#ibcon#about to write, iclass 36, count 0 2006.190.08:10:02.66#ibcon#wrote, iclass 36, count 0 2006.190.08:10:02.66#ibcon#about to read 3, iclass 36, count 0 2006.190.08:10:02.68#ibcon#read 3, iclass 36, count 0 2006.190.08:10:02.68#ibcon#about to read 4, iclass 36, count 0 2006.190.08:10:02.68#ibcon#read 4, iclass 36, count 0 2006.190.08:10:02.68#ibcon#about to read 5, iclass 36, count 0 2006.190.08:10:02.68#ibcon#read 5, iclass 36, count 0 2006.190.08:10:02.68#ibcon#about to read 6, iclass 36, count 0 2006.190.08:10:02.68#ibcon#read 6, iclass 36, count 0 2006.190.08:10:02.68#ibcon#end of sib2, iclass 36, count 0 2006.190.08:10:02.68#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:10:02.68#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:10:02.68#ibcon#[25=BW32\r\n] 2006.190.08:10:02.68#ibcon#*before write, iclass 36, count 0 2006.190.08:10:02.68#ibcon#enter sib2, iclass 36, count 0 2006.190.08:10:02.68#ibcon#flushed, iclass 36, count 0 2006.190.08:10:02.68#ibcon#about to write, iclass 36, count 0 2006.190.08:10:02.68#ibcon#wrote, iclass 36, count 0 2006.190.08:10:02.68#ibcon#about to read 3, iclass 36, count 0 2006.190.08:10:02.71#ibcon#read 3, iclass 36, count 0 2006.190.08:10:02.71#ibcon#about to read 4, iclass 36, count 0 2006.190.08:10:02.71#ibcon#read 4, iclass 36, count 0 2006.190.08:10:02.71#ibcon#about to read 5, iclass 36, count 0 2006.190.08:10:02.71#ibcon#read 5, iclass 36, count 0 2006.190.08:10:02.71#ibcon#about to read 6, iclass 36, count 0 2006.190.08:10:02.71#ibcon#read 6, iclass 36, count 0 2006.190.08:10:02.71#ibcon#end of sib2, iclass 36, count 0 2006.190.08:10:02.71#ibcon#*after write, iclass 36, count 0 2006.190.08:10:02.71#ibcon#*before return 0, iclass 36, count 0 2006.190.08:10:02.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:02.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:10:02.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:10:02.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:10:02.71$vc4f8/vbbw=wide 2006.190.08:10:02.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.08:10:02.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.08:10:02.71#ibcon#ireg 8 cls_cnt 0 2006.190.08:10:02.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:10:02.78#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:10:02.78#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:10:02.78#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:10:02.78#ibcon#first serial, iclass 38, count 0 2006.190.08:10:02.78#ibcon#enter sib2, iclass 38, count 0 2006.190.08:10:02.78#ibcon#flushed, iclass 38, count 0 2006.190.08:10:02.78#ibcon#about to write, iclass 38, count 0 2006.190.08:10:02.78#ibcon#wrote, iclass 38, count 0 2006.190.08:10:02.78#ibcon#about to read 3, iclass 38, count 0 2006.190.08:10:02.80#ibcon#read 3, iclass 38, count 0 2006.190.08:10:02.80#ibcon#about to read 4, iclass 38, count 0 2006.190.08:10:02.80#ibcon#read 4, iclass 38, count 0 2006.190.08:10:02.80#ibcon#about to read 5, iclass 38, count 0 2006.190.08:10:02.80#ibcon#read 5, iclass 38, count 0 2006.190.08:10:02.80#ibcon#about to read 6, iclass 38, count 0 2006.190.08:10:02.80#ibcon#read 6, iclass 38, count 0 2006.190.08:10:02.80#ibcon#end of sib2, iclass 38, count 0 2006.190.08:10:02.80#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:10:02.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:10:02.80#ibcon#[27=BW32\r\n] 2006.190.08:10:02.80#ibcon#*before write, iclass 38, count 0 2006.190.08:10:02.80#ibcon#enter sib2, iclass 38, count 0 2006.190.08:10:02.80#ibcon#flushed, iclass 38, count 0 2006.190.08:10:02.80#ibcon#about to write, iclass 38, count 0 2006.190.08:10:02.80#ibcon#wrote, iclass 38, count 0 2006.190.08:10:02.80#ibcon#about to read 3, iclass 38, count 0 2006.190.08:10:02.83#ibcon#read 3, iclass 38, count 0 2006.190.08:10:02.83#ibcon#about to read 4, iclass 38, count 0 2006.190.08:10:02.83#ibcon#read 4, iclass 38, count 0 2006.190.08:10:02.83#ibcon#about to read 5, iclass 38, count 0 2006.190.08:10:02.83#ibcon#read 5, iclass 38, count 0 2006.190.08:10:02.83#ibcon#about to read 6, iclass 38, count 0 2006.190.08:10:02.83#ibcon#read 6, iclass 38, count 0 2006.190.08:10:02.83#ibcon#end of sib2, iclass 38, count 0 2006.190.08:10:02.83#ibcon#*after write, iclass 38, count 0 2006.190.08:10:02.83#ibcon#*before return 0, iclass 38, count 0 2006.190.08:10:02.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:10:02.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:10:02.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:10:02.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:10:02.83$4f8m12a/ifd4f 2006.190.08:10:02.83$ifd4f/lo= 2006.190.08:10:02.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:10:02.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:10:02.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:10:02.83$ifd4f/patch= 2006.190.08:10:02.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:10:02.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:10:02.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:10:02.83$4f8m12a/"form=m,16.000,1:2 2006.190.08:10:02.83$4f8m12a/"tpicd 2006.190.08:10:02.83$4f8m12a/echo=off 2006.190.08:10:02.83$4f8m12a/xlog=off 2006.190.08:10:02.83:!2006.190.08:11:10 2006.190.08:10:51.14#trakl#Source acquired 2006.190.08:10:51.14#flagr#flagr/antenna,acquired 2006.190.08:11:10.00:preob 2006.190.08:11:10.13/onsource/TRACKING 2006.190.08:11:10.13:!2006.190.08:11:20 2006.190.08:11:20.00:data_valid=on 2006.190.08:11:20.00:midob 2006.190.08:11:21.13/onsource/TRACKING 2006.190.08:11:21.13/wx/24.41,1012.1,100 2006.190.08:11:21.24/cable/+6.4701E-03 2006.190.08:11:22.33/va/01,08,usb,yes,31,33 2006.190.08:11:22.33/va/02,07,usb,yes,31,33 2006.190.08:11:22.33/va/03,06,usb,yes,33,33 2006.190.08:11:22.33/va/04,07,usb,yes,32,34 2006.190.08:11:22.33/va/05,07,usb,yes,35,37 2006.190.08:11:22.33/va/06,06,usb,yes,35,34 2006.190.08:11:22.33/va/07,06,usb,yes,35,35 2006.190.08:11:22.33/va/08,06,usb,yes,37,37 2006.190.08:11:22.56/valo/01,532.99,yes,locked 2006.190.08:11:22.56/valo/02,572.99,yes,locked 2006.190.08:11:22.56/valo/03,672.99,yes,locked 2006.190.08:11:22.56/valo/04,832.99,yes,locked 2006.190.08:11:22.56/valo/05,652.99,yes,locked 2006.190.08:11:22.56/valo/06,772.99,yes,locked 2006.190.08:11:22.56/valo/07,832.99,yes,locked 2006.190.08:11:22.56/valo/08,852.99,yes,locked 2006.190.08:11:23.65/vb/01,04,usb,yes,29,27 2006.190.08:11:23.65/vb/02,04,usb,yes,31,32 2006.190.08:11:23.65/vb/03,04,usb,yes,27,31 2006.190.08:11:23.65/vb/04,04,usb,yes,28,28 2006.190.08:11:23.65/vb/05,04,usb,yes,27,30 2006.190.08:11:23.65/vb/06,04,usb,yes,28,30 2006.190.08:11:23.65/vb/07,04,usb,yes,29,29 2006.190.08:11:23.65/vb/08,04,usb,yes,27,30 2006.190.08:11:23.88/vblo/01,632.99,yes,locked 2006.190.08:11:23.88/vblo/02,640.99,yes,locked 2006.190.08:11:23.88/vblo/03,656.99,yes,locked 2006.190.08:11:23.88/vblo/04,712.99,yes,locked 2006.190.08:11:23.88/vblo/05,744.99,yes,locked 2006.190.08:11:23.88/vblo/06,752.99,yes,locked 2006.190.08:11:23.88/vblo/07,734.99,yes,locked 2006.190.08:11:23.88/vblo/08,744.99,yes,locked 2006.190.08:11:24.03/vabw/8 2006.190.08:11:24.18/vbbw/8 2006.190.08:11:24.27/xfe/off,on,14.7 2006.190.08:11:24.65/ifatt/23,28,28,28 2006.190.08:11:25.08/fmout-gps/S +2.86E-07 2006.190.08:11:25.16:!2006.190.08:12:20 2006.190.08:12:20.01:data_valid=off 2006.190.08:12:20.02:postob 2006.190.08:12:20.13/cable/+6.4716E-03 2006.190.08:12:20.14/wx/24.40,1012.1,100 2006.190.08:12:21.07/fmout-gps/S +2.85E-07 2006.190.08:12:21.07:scan_name=190-0813,k06190,60 2006.190.08:12:21.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.190.08:12:21.13#flagr#flagr/antenna,new-source 2006.190.08:12:22.13:checkk5 2006.190.08:12:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:12:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:12:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:12:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:12:24.03/chk_obsdata//k5ts1/T1900811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:12:24.42/chk_obsdata//k5ts2/T1900811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:12:24.79/chk_obsdata//k5ts3/T1900811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:12:25.17/chk_obsdata//k5ts4/T1900811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:12:25.87/k5log//k5ts1_log_newline 2006.190.08:12:26.56/k5log//k5ts2_log_newline 2006.190.08:12:27.26/k5log//k5ts3_log_newline 2006.190.08:12:27.96/k5log//k5ts4_log_newline 2006.190.08:12:27.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:12:27.99:4f8m12a=2 2006.190.08:12:27.99$4f8m12a/echo=on 2006.190.08:12:27.99$4f8m12a/pcalon 2006.190.08:12:27.99$pcalon/"no phase cal control is implemented here 2006.190.08:12:27.99$4f8m12a/"tpicd=stop 2006.190.08:12:27.99$4f8m12a/vc4f8 2006.190.08:12:27.99$vc4f8/valo=1,532.99 2006.190.08:12:27.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.08:12:27.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.08:12:27.99#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:27.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:27.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:27.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:27.99#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:12:27.99#ibcon#first serial, iclass 25, count 0 2006.190.08:12:27.99#ibcon#enter sib2, iclass 25, count 0 2006.190.08:12:27.99#ibcon#flushed, iclass 25, count 0 2006.190.08:12:27.99#ibcon#about to write, iclass 25, count 0 2006.190.08:12:27.99#ibcon#wrote, iclass 25, count 0 2006.190.08:12:27.99#ibcon#about to read 3, iclass 25, count 0 2006.190.08:12:28.00#ibcon#read 3, iclass 25, count 0 2006.190.08:12:28.00#ibcon#about to read 4, iclass 25, count 0 2006.190.08:12:28.00#ibcon#read 4, iclass 25, count 0 2006.190.08:12:28.00#ibcon#about to read 5, iclass 25, count 0 2006.190.08:12:28.00#ibcon#read 5, iclass 25, count 0 2006.190.08:12:28.00#ibcon#about to read 6, iclass 25, count 0 2006.190.08:12:28.00#ibcon#read 6, iclass 25, count 0 2006.190.08:12:28.00#ibcon#end of sib2, iclass 25, count 0 2006.190.08:12:28.00#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:12:28.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:12:28.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:12:28.00#ibcon#*before write, iclass 25, count 0 2006.190.08:12:28.00#ibcon#enter sib2, iclass 25, count 0 2006.190.08:12:28.00#ibcon#flushed, iclass 25, count 0 2006.190.08:12:28.00#ibcon#about to write, iclass 25, count 0 2006.190.08:12:28.00#ibcon#wrote, iclass 25, count 0 2006.190.08:12:28.00#ibcon#about to read 3, iclass 25, count 0 2006.190.08:12:28.05#ibcon#read 3, iclass 25, count 0 2006.190.08:12:28.05#ibcon#about to read 4, iclass 25, count 0 2006.190.08:12:28.05#ibcon#read 4, iclass 25, count 0 2006.190.08:12:28.05#ibcon#about to read 5, iclass 25, count 0 2006.190.08:12:28.05#ibcon#read 5, iclass 25, count 0 2006.190.08:12:28.05#ibcon#about to read 6, iclass 25, count 0 2006.190.08:12:28.05#ibcon#read 6, iclass 25, count 0 2006.190.08:12:28.05#ibcon#end of sib2, iclass 25, count 0 2006.190.08:12:28.05#ibcon#*after write, iclass 25, count 0 2006.190.08:12:28.05#ibcon#*before return 0, iclass 25, count 0 2006.190.08:12:28.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:28.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:28.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:12:28.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:12:28.05$vc4f8/va=1,8 2006.190.08:12:28.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.08:12:28.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.08:12:28.05#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:28.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:28.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:28.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:28.05#ibcon#enter wrdev, iclass 27, count 2 2006.190.08:12:28.05#ibcon#first serial, iclass 27, count 2 2006.190.08:12:28.05#ibcon#enter sib2, iclass 27, count 2 2006.190.08:12:28.05#ibcon#flushed, iclass 27, count 2 2006.190.08:12:28.05#ibcon#about to write, iclass 27, count 2 2006.190.08:12:28.05#ibcon#wrote, iclass 27, count 2 2006.190.08:12:28.05#ibcon#about to read 3, iclass 27, count 2 2006.190.08:12:28.07#ibcon#read 3, iclass 27, count 2 2006.190.08:12:28.07#ibcon#about to read 4, iclass 27, count 2 2006.190.08:12:28.07#ibcon#read 4, iclass 27, count 2 2006.190.08:12:28.07#ibcon#about to read 5, iclass 27, count 2 2006.190.08:12:28.07#ibcon#read 5, iclass 27, count 2 2006.190.08:12:28.07#ibcon#about to read 6, iclass 27, count 2 2006.190.08:12:28.07#ibcon#read 6, iclass 27, count 2 2006.190.08:12:28.07#ibcon#end of sib2, iclass 27, count 2 2006.190.08:12:28.07#ibcon#*mode == 0, iclass 27, count 2 2006.190.08:12:28.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.08:12:28.07#ibcon#[25=AT01-08\r\n] 2006.190.08:12:28.07#ibcon#*before write, iclass 27, count 2 2006.190.08:12:28.07#ibcon#enter sib2, iclass 27, count 2 2006.190.08:12:28.07#ibcon#flushed, iclass 27, count 2 2006.190.08:12:28.07#ibcon#about to write, iclass 27, count 2 2006.190.08:12:28.07#ibcon#wrote, iclass 27, count 2 2006.190.08:12:28.07#ibcon#about to read 3, iclass 27, count 2 2006.190.08:12:28.11#ibcon#read 3, iclass 27, count 2 2006.190.08:12:28.11#ibcon#about to read 4, iclass 27, count 2 2006.190.08:12:28.11#ibcon#read 4, iclass 27, count 2 2006.190.08:12:28.11#ibcon#about to read 5, iclass 27, count 2 2006.190.08:12:28.11#ibcon#read 5, iclass 27, count 2 2006.190.08:12:28.11#ibcon#about to read 6, iclass 27, count 2 2006.190.08:12:28.11#ibcon#read 6, iclass 27, count 2 2006.190.08:12:28.11#ibcon#end of sib2, iclass 27, count 2 2006.190.08:12:28.11#ibcon#*after write, iclass 27, count 2 2006.190.08:12:28.11#ibcon#*before return 0, iclass 27, count 2 2006.190.08:12:28.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:28.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:28.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.08:12:28.11#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:28.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:28.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:28.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:28.22#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:12:28.22#ibcon#first serial, iclass 27, count 0 2006.190.08:12:28.22#ibcon#enter sib2, iclass 27, count 0 2006.190.08:12:28.22#ibcon#flushed, iclass 27, count 0 2006.190.08:12:28.22#ibcon#about to write, iclass 27, count 0 2006.190.08:12:28.23#ibcon#wrote, iclass 27, count 0 2006.190.08:12:28.23#ibcon#about to read 3, iclass 27, count 0 2006.190.08:12:28.25#ibcon#read 3, iclass 27, count 0 2006.190.08:12:28.25#ibcon#about to read 4, iclass 27, count 0 2006.190.08:12:28.25#ibcon#read 4, iclass 27, count 0 2006.190.08:12:28.25#ibcon#about to read 5, iclass 27, count 0 2006.190.08:12:28.25#ibcon#read 5, iclass 27, count 0 2006.190.08:12:28.25#ibcon#about to read 6, iclass 27, count 0 2006.190.08:12:28.25#ibcon#read 6, iclass 27, count 0 2006.190.08:12:28.25#ibcon#end of sib2, iclass 27, count 0 2006.190.08:12:28.25#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:12:28.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:12:28.25#ibcon#[25=USB\r\n] 2006.190.08:12:28.25#ibcon#*before write, iclass 27, count 0 2006.190.08:12:28.25#ibcon#enter sib2, iclass 27, count 0 2006.190.08:12:28.25#ibcon#flushed, iclass 27, count 0 2006.190.08:12:28.25#ibcon#about to write, iclass 27, count 0 2006.190.08:12:28.25#ibcon#wrote, iclass 27, count 0 2006.190.08:12:28.25#ibcon#about to read 3, iclass 27, count 0 2006.190.08:12:28.28#ibcon#read 3, iclass 27, count 0 2006.190.08:12:28.28#ibcon#about to read 4, iclass 27, count 0 2006.190.08:12:28.28#ibcon#read 4, iclass 27, count 0 2006.190.08:12:28.28#ibcon#about to read 5, iclass 27, count 0 2006.190.08:12:28.28#ibcon#read 5, iclass 27, count 0 2006.190.08:12:28.28#ibcon#about to read 6, iclass 27, count 0 2006.190.08:12:28.28#ibcon#read 6, iclass 27, count 0 2006.190.08:12:28.28#ibcon#end of sib2, iclass 27, count 0 2006.190.08:12:28.28#ibcon#*after write, iclass 27, count 0 2006.190.08:12:28.28#ibcon#*before return 0, iclass 27, count 0 2006.190.08:12:28.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:28.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:28.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:12:28.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:12:28.28$vc4f8/valo=2,572.99 2006.190.08:12:28.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.08:12:28.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.08:12:28.28#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:28.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:28.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:28.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:28.28#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:12:28.28#ibcon#first serial, iclass 29, count 0 2006.190.08:12:28.28#ibcon#enter sib2, iclass 29, count 0 2006.190.08:12:28.28#ibcon#flushed, iclass 29, count 0 2006.190.08:12:28.28#ibcon#about to write, iclass 29, count 0 2006.190.08:12:28.28#ibcon#wrote, iclass 29, count 0 2006.190.08:12:28.28#ibcon#about to read 3, iclass 29, count 0 2006.190.08:12:28.30#ibcon#read 3, iclass 29, count 0 2006.190.08:12:28.30#ibcon#about to read 4, iclass 29, count 0 2006.190.08:12:28.30#ibcon#read 4, iclass 29, count 0 2006.190.08:12:28.30#ibcon#about to read 5, iclass 29, count 0 2006.190.08:12:28.30#ibcon#read 5, iclass 29, count 0 2006.190.08:12:28.30#ibcon#about to read 6, iclass 29, count 0 2006.190.08:12:28.30#ibcon#read 6, iclass 29, count 0 2006.190.08:12:28.30#ibcon#end of sib2, iclass 29, count 0 2006.190.08:12:28.30#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:12:28.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:12:28.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:12:28.30#ibcon#*before write, iclass 29, count 0 2006.190.08:12:28.30#ibcon#enter sib2, iclass 29, count 0 2006.190.08:12:28.30#ibcon#flushed, iclass 29, count 0 2006.190.08:12:28.30#ibcon#about to write, iclass 29, count 0 2006.190.08:12:28.30#ibcon#wrote, iclass 29, count 0 2006.190.08:12:28.30#ibcon#about to read 3, iclass 29, count 0 2006.190.08:12:28.34#ibcon#read 3, iclass 29, count 0 2006.190.08:12:28.34#ibcon#about to read 4, iclass 29, count 0 2006.190.08:12:28.34#ibcon#read 4, iclass 29, count 0 2006.190.08:12:28.34#ibcon#about to read 5, iclass 29, count 0 2006.190.08:12:28.34#ibcon#read 5, iclass 29, count 0 2006.190.08:12:28.34#ibcon#about to read 6, iclass 29, count 0 2006.190.08:12:28.34#ibcon#read 6, iclass 29, count 0 2006.190.08:12:28.34#ibcon#end of sib2, iclass 29, count 0 2006.190.08:12:28.34#ibcon#*after write, iclass 29, count 0 2006.190.08:12:28.34#ibcon#*before return 0, iclass 29, count 0 2006.190.08:12:28.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:28.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:28.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:12:28.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:12:28.34$vc4f8/va=2,7 2006.190.08:12:28.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.08:12:28.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.08:12:28.34#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:28.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:28.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:28.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:28.40#ibcon#enter wrdev, iclass 31, count 2 2006.190.08:12:28.40#ibcon#first serial, iclass 31, count 2 2006.190.08:12:28.40#ibcon#enter sib2, iclass 31, count 2 2006.190.08:12:28.40#ibcon#flushed, iclass 31, count 2 2006.190.08:12:28.40#ibcon#about to write, iclass 31, count 2 2006.190.08:12:28.40#ibcon#wrote, iclass 31, count 2 2006.190.08:12:28.40#ibcon#about to read 3, iclass 31, count 2 2006.190.08:12:28.42#ibcon#read 3, iclass 31, count 2 2006.190.08:12:28.42#ibcon#about to read 4, iclass 31, count 2 2006.190.08:12:28.42#ibcon#read 4, iclass 31, count 2 2006.190.08:12:28.42#ibcon#about to read 5, iclass 31, count 2 2006.190.08:12:28.42#ibcon#read 5, iclass 31, count 2 2006.190.08:12:28.42#ibcon#about to read 6, iclass 31, count 2 2006.190.08:12:28.42#ibcon#read 6, iclass 31, count 2 2006.190.08:12:28.42#ibcon#end of sib2, iclass 31, count 2 2006.190.08:12:28.42#ibcon#*mode == 0, iclass 31, count 2 2006.190.08:12:28.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.08:12:28.42#ibcon#[25=AT02-07\r\n] 2006.190.08:12:28.42#ibcon#*before write, iclass 31, count 2 2006.190.08:12:28.42#ibcon#enter sib2, iclass 31, count 2 2006.190.08:12:28.42#ibcon#flushed, iclass 31, count 2 2006.190.08:12:28.42#ibcon#about to write, iclass 31, count 2 2006.190.08:12:28.42#ibcon#wrote, iclass 31, count 2 2006.190.08:12:28.42#ibcon#about to read 3, iclass 31, count 2 2006.190.08:12:28.45#ibcon#read 3, iclass 31, count 2 2006.190.08:12:28.45#ibcon#about to read 4, iclass 31, count 2 2006.190.08:12:28.45#ibcon#read 4, iclass 31, count 2 2006.190.08:12:28.45#ibcon#about to read 5, iclass 31, count 2 2006.190.08:12:28.45#ibcon#read 5, iclass 31, count 2 2006.190.08:12:28.45#ibcon#about to read 6, iclass 31, count 2 2006.190.08:12:28.45#ibcon#read 6, iclass 31, count 2 2006.190.08:12:28.45#ibcon#end of sib2, iclass 31, count 2 2006.190.08:12:28.45#ibcon#*after write, iclass 31, count 2 2006.190.08:12:28.45#ibcon#*before return 0, iclass 31, count 2 2006.190.08:12:28.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:28.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:28.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.08:12:28.45#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:28.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:28.58#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:28.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:28.58#ibcon#enter wrdev, iclass 31, count 0 2006.190.08:12:28.58#ibcon#first serial, iclass 31, count 0 2006.190.08:12:28.58#ibcon#enter sib2, iclass 31, count 0 2006.190.08:12:28.58#ibcon#flushed, iclass 31, count 0 2006.190.08:12:28.58#ibcon#about to write, iclass 31, count 0 2006.190.08:12:28.58#ibcon#wrote, iclass 31, count 0 2006.190.08:12:28.58#ibcon#about to read 3, iclass 31, count 0 2006.190.08:12:28.59#ibcon#read 3, iclass 31, count 0 2006.190.08:12:28.59#ibcon#about to read 4, iclass 31, count 0 2006.190.08:12:28.59#ibcon#read 4, iclass 31, count 0 2006.190.08:12:28.59#ibcon#about to read 5, iclass 31, count 0 2006.190.08:12:28.59#ibcon#read 5, iclass 31, count 0 2006.190.08:12:28.59#ibcon#about to read 6, iclass 31, count 0 2006.190.08:12:28.59#ibcon#read 6, iclass 31, count 0 2006.190.08:12:28.59#ibcon#end of sib2, iclass 31, count 0 2006.190.08:12:28.59#ibcon#*mode == 0, iclass 31, count 0 2006.190.08:12:28.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.08:12:28.59#ibcon#[25=USB\r\n] 2006.190.08:12:28.59#ibcon#*before write, iclass 31, count 0 2006.190.08:12:28.59#ibcon#enter sib2, iclass 31, count 0 2006.190.08:12:28.59#ibcon#flushed, iclass 31, count 0 2006.190.08:12:28.59#ibcon#about to write, iclass 31, count 0 2006.190.08:12:28.59#ibcon#wrote, iclass 31, count 0 2006.190.08:12:28.59#ibcon#about to read 3, iclass 31, count 0 2006.190.08:12:28.62#ibcon#read 3, iclass 31, count 0 2006.190.08:12:28.62#ibcon#about to read 4, iclass 31, count 0 2006.190.08:12:28.62#ibcon#read 4, iclass 31, count 0 2006.190.08:12:28.62#ibcon#about to read 5, iclass 31, count 0 2006.190.08:12:28.62#ibcon#read 5, iclass 31, count 0 2006.190.08:12:28.62#ibcon#about to read 6, iclass 31, count 0 2006.190.08:12:28.62#ibcon#read 6, iclass 31, count 0 2006.190.08:12:28.62#ibcon#end of sib2, iclass 31, count 0 2006.190.08:12:28.62#ibcon#*after write, iclass 31, count 0 2006.190.08:12:28.62#ibcon#*before return 0, iclass 31, count 0 2006.190.08:12:28.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:28.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:28.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.08:12:28.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.08:12:28.62$vc4f8/valo=3,672.99 2006.190.08:12:28.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.08:12:28.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.08:12:28.62#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:28.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:28.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:28.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:28.62#ibcon#enter wrdev, iclass 33, count 0 2006.190.08:12:28.62#ibcon#first serial, iclass 33, count 0 2006.190.08:12:28.62#ibcon#enter sib2, iclass 33, count 0 2006.190.08:12:28.62#ibcon#flushed, iclass 33, count 0 2006.190.08:12:28.62#ibcon#about to write, iclass 33, count 0 2006.190.08:12:28.62#ibcon#wrote, iclass 33, count 0 2006.190.08:12:28.62#ibcon#about to read 3, iclass 33, count 0 2006.190.08:12:28.64#ibcon#read 3, iclass 33, count 0 2006.190.08:12:28.64#ibcon#about to read 4, iclass 33, count 0 2006.190.08:12:28.64#ibcon#read 4, iclass 33, count 0 2006.190.08:12:28.64#ibcon#about to read 5, iclass 33, count 0 2006.190.08:12:28.64#ibcon#read 5, iclass 33, count 0 2006.190.08:12:28.64#ibcon#about to read 6, iclass 33, count 0 2006.190.08:12:28.64#ibcon#read 6, iclass 33, count 0 2006.190.08:12:28.64#ibcon#end of sib2, iclass 33, count 0 2006.190.08:12:28.64#ibcon#*mode == 0, iclass 33, count 0 2006.190.08:12:28.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.08:12:28.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:12:28.64#ibcon#*before write, iclass 33, count 0 2006.190.08:12:28.64#ibcon#enter sib2, iclass 33, count 0 2006.190.08:12:28.64#ibcon#flushed, iclass 33, count 0 2006.190.08:12:28.64#ibcon#about to write, iclass 33, count 0 2006.190.08:12:28.64#ibcon#wrote, iclass 33, count 0 2006.190.08:12:28.64#ibcon#about to read 3, iclass 33, count 0 2006.190.08:12:28.68#ibcon#read 3, iclass 33, count 0 2006.190.08:12:28.68#ibcon#about to read 4, iclass 33, count 0 2006.190.08:12:28.68#ibcon#read 4, iclass 33, count 0 2006.190.08:12:28.68#ibcon#about to read 5, iclass 33, count 0 2006.190.08:12:28.68#ibcon#read 5, iclass 33, count 0 2006.190.08:12:28.68#ibcon#about to read 6, iclass 33, count 0 2006.190.08:12:28.68#ibcon#read 6, iclass 33, count 0 2006.190.08:12:28.68#ibcon#end of sib2, iclass 33, count 0 2006.190.08:12:28.68#ibcon#*after write, iclass 33, count 0 2006.190.08:12:28.68#ibcon#*before return 0, iclass 33, count 0 2006.190.08:12:28.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:28.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:28.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.08:12:28.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.08:12:28.68$vc4f8/va=3,6 2006.190.08:12:28.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.08:12:28.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.08:12:28.68#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:28.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:28.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:28.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:28.74#ibcon#enter wrdev, iclass 35, count 2 2006.190.08:12:28.74#ibcon#first serial, iclass 35, count 2 2006.190.08:12:28.74#ibcon#enter sib2, iclass 35, count 2 2006.190.08:12:28.74#ibcon#flushed, iclass 35, count 2 2006.190.08:12:28.74#ibcon#about to write, iclass 35, count 2 2006.190.08:12:28.74#ibcon#wrote, iclass 35, count 2 2006.190.08:12:28.74#ibcon#about to read 3, iclass 35, count 2 2006.190.08:12:28.76#ibcon#read 3, iclass 35, count 2 2006.190.08:12:28.76#ibcon#about to read 4, iclass 35, count 2 2006.190.08:12:28.76#ibcon#read 4, iclass 35, count 2 2006.190.08:12:28.76#ibcon#about to read 5, iclass 35, count 2 2006.190.08:12:28.76#ibcon#read 5, iclass 35, count 2 2006.190.08:12:28.76#ibcon#about to read 6, iclass 35, count 2 2006.190.08:12:28.76#ibcon#read 6, iclass 35, count 2 2006.190.08:12:28.76#ibcon#end of sib2, iclass 35, count 2 2006.190.08:12:28.76#ibcon#*mode == 0, iclass 35, count 2 2006.190.08:12:28.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.08:12:28.76#ibcon#[25=AT03-06\r\n] 2006.190.08:12:28.76#ibcon#*before write, iclass 35, count 2 2006.190.08:12:28.76#ibcon#enter sib2, iclass 35, count 2 2006.190.08:12:28.76#ibcon#flushed, iclass 35, count 2 2006.190.08:12:28.76#ibcon#about to write, iclass 35, count 2 2006.190.08:12:28.76#ibcon#wrote, iclass 35, count 2 2006.190.08:12:28.76#ibcon#about to read 3, iclass 35, count 2 2006.190.08:12:28.79#ibcon#read 3, iclass 35, count 2 2006.190.08:12:28.79#ibcon#about to read 4, iclass 35, count 2 2006.190.08:12:28.79#ibcon#read 4, iclass 35, count 2 2006.190.08:12:28.79#ibcon#about to read 5, iclass 35, count 2 2006.190.08:12:28.79#ibcon#read 5, iclass 35, count 2 2006.190.08:12:28.79#ibcon#about to read 6, iclass 35, count 2 2006.190.08:12:28.79#ibcon#read 6, iclass 35, count 2 2006.190.08:12:28.79#ibcon#end of sib2, iclass 35, count 2 2006.190.08:12:28.79#ibcon#*after write, iclass 35, count 2 2006.190.08:12:28.79#ibcon#*before return 0, iclass 35, count 2 2006.190.08:12:28.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:28.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:28.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.08:12:28.79#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:28.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:28.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:28.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:28.91#ibcon#enter wrdev, iclass 35, count 0 2006.190.08:12:28.91#ibcon#first serial, iclass 35, count 0 2006.190.08:12:28.91#ibcon#enter sib2, iclass 35, count 0 2006.190.08:12:28.91#ibcon#flushed, iclass 35, count 0 2006.190.08:12:28.91#ibcon#about to write, iclass 35, count 0 2006.190.08:12:28.91#ibcon#wrote, iclass 35, count 0 2006.190.08:12:28.91#ibcon#about to read 3, iclass 35, count 0 2006.190.08:12:28.93#ibcon#read 3, iclass 35, count 0 2006.190.08:12:28.93#ibcon#about to read 4, iclass 35, count 0 2006.190.08:12:28.93#ibcon#read 4, iclass 35, count 0 2006.190.08:12:28.93#ibcon#about to read 5, iclass 35, count 0 2006.190.08:12:28.93#ibcon#read 5, iclass 35, count 0 2006.190.08:12:28.93#ibcon#about to read 6, iclass 35, count 0 2006.190.08:12:28.93#ibcon#read 6, iclass 35, count 0 2006.190.08:12:28.93#ibcon#end of sib2, iclass 35, count 0 2006.190.08:12:28.93#ibcon#*mode == 0, iclass 35, count 0 2006.190.08:12:28.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.08:12:28.93#ibcon#[25=USB\r\n] 2006.190.08:12:28.93#ibcon#*before write, iclass 35, count 0 2006.190.08:12:28.93#ibcon#enter sib2, iclass 35, count 0 2006.190.08:12:28.93#ibcon#flushed, iclass 35, count 0 2006.190.08:12:28.93#ibcon#about to write, iclass 35, count 0 2006.190.08:12:28.93#ibcon#wrote, iclass 35, count 0 2006.190.08:12:28.93#ibcon#about to read 3, iclass 35, count 0 2006.190.08:12:28.96#ibcon#read 3, iclass 35, count 0 2006.190.08:12:28.96#ibcon#about to read 4, iclass 35, count 0 2006.190.08:12:28.96#ibcon#read 4, iclass 35, count 0 2006.190.08:12:28.96#ibcon#about to read 5, iclass 35, count 0 2006.190.08:12:28.96#ibcon#read 5, iclass 35, count 0 2006.190.08:12:28.96#ibcon#about to read 6, iclass 35, count 0 2006.190.08:12:28.96#ibcon#read 6, iclass 35, count 0 2006.190.08:12:28.96#ibcon#end of sib2, iclass 35, count 0 2006.190.08:12:28.96#ibcon#*after write, iclass 35, count 0 2006.190.08:12:28.96#ibcon#*before return 0, iclass 35, count 0 2006.190.08:12:28.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:28.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:28.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.08:12:28.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.08:12:28.96$vc4f8/valo=4,832.99 2006.190.08:12:28.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.08:12:28.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.08:12:28.96#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:28.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:28.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:28.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:28.96#ibcon#enter wrdev, iclass 37, count 0 2006.190.08:12:28.96#ibcon#first serial, iclass 37, count 0 2006.190.08:12:28.96#ibcon#enter sib2, iclass 37, count 0 2006.190.08:12:28.96#ibcon#flushed, iclass 37, count 0 2006.190.08:12:28.96#ibcon#about to write, iclass 37, count 0 2006.190.08:12:28.96#ibcon#wrote, iclass 37, count 0 2006.190.08:12:28.96#ibcon#about to read 3, iclass 37, count 0 2006.190.08:12:28.98#ibcon#read 3, iclass 37, count 0 2006.190.08:12:28.98#ibcon#about to read 4, iclass 37, count 0 2006.190.08:12:28.98#ibcon#read 4, iclass 37, count 0 2006.190.08:12:28.98#ibcon#about to read 5, iclass 37, count 0 2006.190.08:12:28.98#ibcon#read 5, iclass 37, count 0 2006.190.08:12:28.98#ibcon#about to read 6, iclass 37, count 0 2006.190.08:12:28.98#ibcon#read 6, iclass 37, count 0 2006.190.08:12:28.98#ibcon#end of sib2, iclass 37, count 0 2006.190.08:12:28.98#ibcon#*mode == 0, iclass 37, count 0 2006.190.08:12:28.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.08:12:28.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:12:28.98#ibcon#*before write, iclass 37, count 0 2006.190.08:12:28.98#ibcon#enter sib2, iclass 37, count 0 2006.190.08:12:28.98#ibcon#flushed, iclass 37, count 0 2006.190.08:12:28.98#ibcon#about to write, iclass 37, count 0 2006.190.08:12:28.98#ibcon#wrote, iclass 37, count 0 2006.190.08:12:28.98#ibcon#about to read 3, iclass 37, count 0 2006.190.08:12:29.02#ibcon#read 3, iclass 37, count 0 2006.190.08:12:29.02#ibcon#about to read 4, iclass 37, count 0 2006.190.08:12:29.02#ibcon#read 4, iclass 37, count 0 2006.190.08:12:29.02#ibcon#about to read 5, iclass 37, count 0 2006.190.08:12:29.02#ibcon#read 5, iclass 37, count 0 2006.190.08:12:29.02#ibcon#about to read 6, iclass 37, count 0 2006.190.08:12:29.02#ibcon#read 6, iclass 37, count 0 2006.190.08:12:29.02#ibcon#end of sib2, iclass 37, count 0 2006.190.08:12:29.02#ibcon#*after write, iclass 37, count 0 2006.190.08:12:29.02#ibcon#*before return 0, iclass 37, count 0 2006.190.08:12:29.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:29.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:29.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.08:12:29.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.08:12:29.02$vc4f8/va=4,7 2006.190.08:12:29.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.08:12:29.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.08:12:29.02#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:29.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:29.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:29.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:29.08#ibcon#enter wrdev, iclass 39, count 2 2006.190.08:12:29.08#ibcon#first serial, iclass 39, count 2 2006.190.08:12:29.08#ibcon#enter sib2, iclass 39, count 2 2006.190.08:12:29.08#ibcon#flushed, iclass 39, count 2 2006.190.08:12:29.08#ibcon#about to write, iclass 39, count 2 2006.190.08:12:29.08#ibcon#wrote, iclass 39, count 2 2006.190.08:12:29.08#ibcon#about to read 3, iclass 39, count 2 2006.190.08:12:29.10#ibcon#read 3, iclass 39, count 2 2006.190.08:12:29.10#ibcon#about to read 4, iclass 39, count 2 2006.190.08:12:29.10#ibcon#read 4, iclass 39, count 2 2006.190.08:12:29.10#ibcon#about to read 5, iclass 39, count 2 2006.190.08:12:29.10#ibcon#read 5, iclass 39, count 2 2006.190.08:12:29.10#ibcon#about to read 6, iclass 39, count 2 2006.190.08:12:29.10#ibcon#read 6, iclass 39, count 2 2006.190.08:12:29.10#ibcon#end of sib2, iclass 39, count 2 2006.190.08:12:29.10#ibcon#*mode == 0, iclass 39, count 2 2006.190.08:12:29.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.08:12:29.10#ibcon#[25=AT04-07\r\n] 2006.190.08:12:29.10#ibcon#*before write, iclass 39, count 2 2006.190.08:12:29.10#ibcon#enter sib2, iclass 39, count 2 2006.190.08:12:29.10#ibcon#flushed, iclass 39, count 2 2006.190.08:12:29.10#ibcon#about to write, iclass 39, count 2 2006.190.08:12:29.10#ibcon#wrote, iclass 39, count 2 2006.190.08:12:29.10#ibcon#about to read 3, iclass 39, count 2 2006.190.08:12:29.13#ibcon#read 3, iclass 39, count 2 2006.190.08:12:29.13#ibcon#about to read 4, iclass 39, count 2 2006.190.08:12:29.13#ibcon#read 4, iclass 39, count 2 2006.190.08:12:29.13#ibcon#about to read 5, iclass 39, count 2 2006.190.08:12:29.13#ibcon#read 5, iclass 39, count 2 2006.190.08:12:29.13#ibcon#about to read 6, iclass 39, count 2 2006.190.08:12:29.13#ibcon#read 6, iclass 39, count 2 2006.190.08:12:29.13#ibcon#end of sib2, iclass 39, count 2 2006.190.08:12:29.13#ibcon#*after write, iclass 39, count 2 2006.190.08:12:29.13#ibcon#*before return 0, iclass 39, count 2 2006.190.08:12:29.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:29.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:29.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.08:12:29.13#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:29.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:29.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:29.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:29.25#ibcon#enter wrdev, iclass 39, count 0 2006.190.08:12:29.25#ibcon#first serial, iclass 39, count 0 2006.190.08:12:29.25#ibcon#enter sib2, iclass 39, count 0 2006.190.08:12:29.25#ibcon#flushed, iclass 39, count 0 2006.190.08:12:29.25#ibcon#about to write, iclass 39, count 0 2006.190.08:12:29.25#ibcon#wrote, iclass 39, count 0 2006.190.08:12:29.25#ibcon#about to read 3, iclass 39, count 0 2006.190.08:12:29.27#ibcon#read 3, iclass 39, count 0 2006.190.08:12:29.27#ibcon#about to read 4, iclass 39, count 0 2006.190.08:12:29.27#ibcon#read 4, iclass 39, count 0 2006.190.08:12:29.27#ibcon#about to read 5, iclass 39, count 0 2006.190.08:12:29.27#ibcon#read 5, iclass 39, count 0 2006.190.08:12:29.27#ibcon#about to read 6, iclass 39, count 0 2006.190.08:12:29.27#ibcon#read 6, iclass 39, count 0 2006.190.08:12:29.27#ibcon#end of sib2, iclass 39, count 0 2006.190.08:12:29.27#ibcon#*mode == 0, iclass 39, count 0 2006.190.08:12:29.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.08:12:29.27#ibcon#[25=USB\r\n] 2006.190.08:12:29.27#ibcon#*before write, iclass 39, count 0 2006.190.08:12:29.27#ibcon#enter sib2, iclass 39, count 0 2006.190.08:12:29.27#ibcon#flushed, iclass 39, count 0 2006.190.08:12:29.27#ibcon#about to write, iclass 39, count 0 2006.190.08:12:29.27#ibcon#wrote, iclass 39, count 0 2006.190.08:12:29.27#ibcon#about to read 3, iclass 39, count 0 2006.190.08:12:29.30#ibcon#read 3, iclass 39, count 0 2006.190.08:12:29.30#ibcon#about to read 4, iclass 39, count 0 2006.190.08:12:29.30#ibcon#read 4, iclass 39, count 0 2006.190.08:12:29.30#ibcon#about to read 5, iclass 39, count 0 2006.190.08:12:29.30#ibcon#read 5, iclass 39, count 0 2006.190.08:12:29.30#ibcon#about to read 6, iclass 39, count 0 2006.190.08:12:29.30#ibcon#read 6, iclass 39, count 0 2006.190.08:12:29.30#ibcon#end of sib2, iclass 39, count 0 2006.190.08:12:29.30#ibcon#*after write, iclass 39, count 0 2006.190.08:12:29.30#ibcon#*before return 0, iclass 39, count 0 2006.190.08:12:29.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:29.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:29.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.08:12:29.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.08:12:29.30$vc4f8/valo=5,652.99 2006.190.08:12:29.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.08:12:29.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.08:12:29.30#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:29.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:29.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:29.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:29.30#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:12:29.30#ibcon#first serial, iclass 3, count 0 2006.190.08:12:29.30#ibcon#enter sib2, iclass 3, count 0 2006.190.08:12:29.30#ibcon#flushed, iclass 3, count 0 2006.190.08:12:29.30#ibcon#about to write, iclass 3, count 0 2006.190.08:12:29.30#ibcon#wrote, iclass 3, count 0 2006.190.08:12:29.30#ibcon#about to read 3, iclass 3, count 0 2006.190.08:12:29.32#ibcon#read 3, iclass 3, count 0 2006.190.08:12:29.32#ibcon#about to read 4, iclass 3, count 0 2006.190.08:12:29.32#ibcon#read 4, iclass 3, count 0 2006.190.08:12:29.32#ibcon#about to read 5, iclass 3, count 0 2006.190.08:12:29.32#ibcon#read 5, iclass 3, count 0 2006.190.08:12:29.32#ibcon#about to read 6, iclass 3, count 0 2006.190.08:12:29.32#ibcon#read 6, iclass 3, count 0 2006.190.08:12:29.32#ibcon#end of sib2, iclass 3, count 0 2006.190.08:12:29.32#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:12:29.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:12:29.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:12:29.32#ibcon#*before write, iclass 3, count 0 2006.190.08:12:29.32#ibcon#enter sib2, iclass 3, count 0 2006.190.08:12:29.32#ibcon#flushed, iclass 3, count 0 2006.190.08:12:29.32#ibcon#about to write, iclass 3, count 0 2006.190.08:12:29.32#ibcon#wrote, iclass 3, count 0 2006.190.08:12:29.32#ibcon#about to read 3, iclass 3, count 0 2006.190.08:12:29.36#ibcon#read 3, iclass 3, count 0 2006.190.08:12:29.36#ibcon#about to read 4, iclass 3, count 0 2006.190.08:12:29.36#ibcon#read 4, iclass 3, count 0 2006.190.08:12:29.36#ibcon#about to read 5, iclass 3, count 0 2006.190.08:12:29.36#ibcon#read 5, iclass 3, count 0 2006.190.08:12:29.36#ibcon#about to read 6, iclass 3, count 0 2006.190.08:12:29.36#ibcon#read 6, iclass 3, count 0 2006.190.08:12:29.36#ibcon#end of sib2, iclass 3, count 0 2006.190.08:12:29.36#ibcon#*after write, iclass 3, count 0 2006.190.08:12:29.36#ibcon#*before return 0, iclass 3, count 0 2006.190.08:12:29.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:29.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:29.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:12:29.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:12:29.36$vc4f8/va=5,7 2006.190.08:12:29.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.08:12:29.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.08:12:29.36#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:29.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:29.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:29.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:29.42#ibcon#enter wrdev, iclass 5, count 2 2006.190.08:12:29.42#ibcon#first serial, iclass 5, count 2 2006.190.08:12:29.42#ibcon#enter sib2, iclass 5, count 2 2006.190.08:12:29.42#ibcon#flushed, iclass 5, count 2 2006.190.08:12:29.42#ibcon#about to write, iclass 5, count 2 2006.190.08:12:29.42#ibcon#wrote, iclass 5, count 2 2006.190.08:12:29.42#ibcon#about to read 3, iclass 5, count 2 2006.190.08:12:29.44#ibcon#read 3, iclass 5, count 2 2006.190.08:12:29.44#ibcon#about to read 4, iclass 5, count 2 2006.190.08:12:29.44#ibcon#read 4, iclass 5, count 2 2006.190.08:12:29.44#ibcon#about to read 5, iclass 5, count 2 2006.190.08:12:29.44#ibcon#read 5, iclass 5, count 2 2006.190.08:12:29.44#ibcon#about to read 6, iclass 5, count 2 2006.190.08:12:29.44#ibcon#read 6, iclass 5, count 2 2006.190.08:12:29.44#ibcon#end of sib2, iclass 5, count 2 2006.190.08:12:29.44#ibcon#*mode == 0, iclass 5, count 2 2006.190.08:12:29.44#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.08:12:29.44#ibcon#[25=AT05-07\r\n] 2006.190.08:12:29.44#ibcon#*before write, iclass 5, count 2 2006.190.08:12:29.44#ibcon#enter sib2, iclass 5, count 2 2006.190.08:12:29.44#ibcon#flushed, iclass 5, count 2 2006.190.08:12:29.44#ibcon#about to write, iclass 5, count 2 2006.190.08:12:29.44#ibcon#wrote, iclass 5, count 2 2006.190.08:12:29.44#ibcon#about to read 3, iclass 5, count 2 2006.190.08:12:29.47#ibcon#read 3, iclass 5, count 2 2006.190.08:12:29.47#ibcon#about to read 4, iclass 5, count 2 2006.190.08:12:29.47#ibcon#read 4, iclass 5, count 2 2006.190.08:12:29.47#ibcon#about to read 5, iclass 5, count 2 2006.190.08:12:29.47#ibcon#read 5, iclass 5, count 2 2006.190.08:12:29.47#ibcon#about to read 6, iclass 5, count 2 2006.190.08:12:29.47#ibcon#read 6, iclass 5, count 2 2006.190.08:12:29.47#ibcon#end of sib2, iclass 5, count 2 2006.190.08:12:29.47#ibcon#*after write, iclass 5, count 2 2006.190.08:12:29.47#ibcon#*before return 0, iclass 5, count 2 2006.190.08:12:29.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:29.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:29.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.08:12:29.47#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:29.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:29.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:29.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:29.59#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:12:29.59#ibcon#first serial, iclass 5, count 0 2006.190.08:12:29.59#ibcon#enter sib2, iclass 5, count 0 2006.190.08:12:29.59#ibcon#flushed, iclass 5, count 0 2006.190.08:12:29.59#ibcon#about to write, iclass 5, count 0 2006.190.08:12:29.59#ibcon#wrote, iclass 5, count 0 2006.190.08:12:29.59#ibcon#about to read 3, iclass 5, count 0 2006.190.08:12:29.61#ibcon#read 3, iclass 5, count 0 2006.190.08:12:29.61#ibcon#about to read 4, iclass 5, count 0 2006.190.08:12:29.61#ibcon#read 4, iclass 5, count 0 2006.190.08:12:29.61#ibcon#about to read 5, iclass 5, count 0 2006.190.08:12:29.61#ibcon#read 5, iclass 5, count 0 2006.190.08:12:29.61#ibcon#about to read 6, iclass 5, count 0 2006.190.08:12:29.61#ibcon#read 6, iclass 5, count 0 2006.190.08:12:29.61#ibcon#end of sib2, iclass 5, count 0 2006.190.08:12:29.61#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:12:29.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:12:29.61#ibcon#[25=USB\r\n] 2006.190.08:12:29.61#ibcon#*before write, iclass 5, count 0 2006.190.08:12:29.61#ibcon#enter sib2, iclass 5, count 0 2006.190.08:12:29.61#ibcon#flushed, iclass 5, count 0 2006.190.08:12:29.61#ibcon#about to write, iclass 5, count 0 2006.190.08:12:29.61#ibcon#wrote, iclass 5, count 0 2006.190.08:12:29.61#ibcon#about to read 3, iclass 5, count 0 2006.190.08:12:29.64#ibcon#read 3, iclass 5, count 0 2006.190.08:12:29.64#ibcon#about to read 4, iclass 5, count 0 2006.190.08:12:29.64#ibcon#read 4, iclass 5, count 0 2006.190.08:12:29.64#ibcon#about to read 5, iclass 5, count 0 2006.190.08:12:29.64#ibcon#read 5, iclass 5, count 0 2006.190.08:12:29.64#ibcon#about to read 6, iclass 5, count 0 2006.190.08:12:29.64#ibcon#read 6, iclass 5, count 0 2006.190.08:12:29.64#ibcon#end of sib2, iclass 5, count 0 2006.190.08:12:29.64#ibcon#*after write, iclass 5, count 0 2006.190.08:12:29.64#ibcon#*before return 0, iclass 5, count 0 2006.190.08:12:29.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:29.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:29.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:12:29.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:12:29.64$vc4f8/valo=6,772.99 2006.190.08:12:29.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.08:12:29.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.08:12:29.64#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:29.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:29.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:29.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:29.64#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:12:29.64#ibcon#first serial, iclass 7, count 0 2006.190.08:12:29.64#ibcon#enter sib2, iclass 7, count 0 2006.190.08:12:29.64#ibcon#flushed, iclass 7, count 0 2006.190.08:12:29.64#ibcon#about to write, iclass 7, count 0 2006.190.08:12:29.64#ibcon#wrote, iclass 7, count 0 2006.190.08:12:29.64#ibcon#about to read 3, iclass 7, count 0 2006.190.08:12:29.66#ibcon#read 3, iclass 7, count 0 2006.190.08:12:29.66#ibcon#about to read 4, iclass 7, count 0 2006.190.08:12:29.66#ibcon#read 4, iclass 7, count 0 2006.190.08:12:29.66#ibcon#about to read 5, iclass 7, count 0 2006.190.08:12:29.66#ibcon#read 5, iclass 7, count 0 2006.190.08:12:29.66#ibcon#about to read 6, iclass 7, count 0 2006.190.08:12:29.66#ibcon#read 6, iclass 7, count 0 2006.190.08:12:29.66#ibcon#end of sib2, iclass 7, count 0 2006.190.08:12:29.66#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:12:29.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:12:29.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:12:29.66#ibcon#*before write, iclass 7, count 0 2006.190.08:12:29.66#ibcon#enter sib2, iclass 7, count 0 2006.190.08:12:29.66#ibcon#flushed, iclass 7, count 0 2006.190.08:12:29.66#ibcon#about to write, iclass 7, count 0 2006.190.08:12:29.66#ibcon#wrote, iclass 7, count 0 2006.190.08:12:29.66#ibcon#about to read 3, iclass 7, count 0 2006.190.08:12:29.70#ibcon#read 3, iclass 7, count 0 2006.190.08:12:29.70#ibcon#about to read 4, iclass 7, count 0 2006.190.08:12:29.70#ibcon#read 4, iclass 7, count 0 2006.190.08:12:29.70#ibcon#about to read 5, iclass 7, count 0 2006.190.08:12:29.70#ibcon#read 5, iclass 7, count 0 2006.190.08:12:29.70#ibcon#about to read 6, iclass 7, count 0 2006.190.08:12:29.70#ibcon#read 6, iclass 7, count 0 2006.190.08:12:29.70#ibcon#end of sib2, iclass 7, count 0 2006.190.08:12:29.70#ibcon#*after write, iclass 7, count 0 2006.190.08:12:29.70#ibcon#*before return 0, iclass 7, count 0 2006.190.08:12:29.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:29.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:29.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:12:29.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:12:29.70$vc4f8/va=6,6 2006.190.08:12:29.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.08:12:29.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.08:12:29.70#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:29.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:12:29.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:12:29.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:12:29.76#ibcon#enter wrdev, iclass 11, count 2 2006.190.08:12:29.76#ibcon#first serial, iclass 11, count 2 2006.190.08:12:29.76#ibcon#enter sib2, iclass 11, count 2 2006.190.08:12:29.76#ibcon#flushed, iclass 11, count 2 2006.190.08:12:29.76#ibcon#about to write, iclass 11, count 2 2006.190.08:12:29.76#ibcon#wrote, iclass 11, count 2 2006.190.08:12:29.76#ibcon#about to read 3, iclass 11, count 2 2006.190.08:12:29.78#ibcon#read 3, iclass 11, count 2 2006.190.08:12:29.78#ibcon#about to read 4, iclass 11, count 2 2006.190.08:12:29.78#ibcon#read 4, iclass 11, count 2 2006.190.08:12:29.78#ibcon#about to read 5, iclass 11, count 2 2006.190.08:12:29.78#ibcon#read 5, iclass 11, count 2 2006.190.08:12:29.78#ibcon#about to read 6, iclass 11, count 2 2006.190.08:12:29.78#ibcon#read 6, iclass 11, count 2 2006.190.08:12:29.78#ibcon#end of sib2, iclass 11, count 2 2006.190.08:12:29.78#ibcon#*mode == 0, iclass 11, count 2 2006.190.08:12:29.78#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.08:12:29.78#ibcon#[25=AT06-06\r\n] 2006.190.08:12:29.78#ibcon#*before write, iclass 11, count 2 2006.190.08:12:29.78#ibcon#enter sib2, iclass 11, count 2 2006.190.08:12:29.78#ibcon#flushed, iclass 11, count 2 2006.190.08:12:29.78#ibcon#about to write, iclass 11, count 2 2006.190.08:12:29.78#ibcon#wrote, iclass 11, count 2 2006.190.08:12:29.78#ibcon#about to read 3, iclass 11, count 2 2006.190.08:12:29.81#ibcon#read 3, iclass 11, count 2 2006.190.08:12:29.81#ibcon#about to read 4, iclass 11, count 2 2006.190.08:12:29.81#ibcon#read 4, iclass 11, count 2 2006.190.08:12:29.81#ibcon#about to read 5, iclass 11, count 2 2006.190.08:12:29.81#ibcon#read 5, iclass 11, count 2 2006.190.08:12:29.81#ibcon#about to read 6, iclass 11, count 2 2006.190.08:12:29.81#ibcon#read 6, iclass 11, count 2 2006.190.08:12:29.81#ibcon#end of sib2, iclass 11, count 2 2006.190.08:12:29.81#ibcon#*after write, iclass 11, count 2 2006.190.08:12:29.81#ibcon#*before return 0, iclass 11, count 2 2006.190.08:12:29.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:12:29.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:12:29.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.08:12:29.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:29.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:12:29.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:12:29.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:12:29.93#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:12:29.93#ibcon#first serial, iclass 11, count 0 2006.190.08:12:29.93#ibcon#enter sib2, iclass 11, count 0 2006.190.08:12:29.93#ibcon#flushed, iclass 11, count 0 2006.190.08:12:29.93#ibcon#about to write, iclass 11, count 0 2006.190.08:12:29.93#ibcon#wrote, iclass 11, count 0 2006.190.08:12:29.93#ibcon#about to read 3, iclass 11, count 0 2006.190.08:12:29.95#ibcon#read 3, iclass 11, count 0 2006.190.08:12:29.95#ibcon#about to read 4, iclass 11, count 0 2006.190.08:12:29.95#ibcon#read 4, iclass 11, count 0 2006.190.08:12:29.95#ibcon#about to read 5, iclass 11, count 0 2006.190.08:12:29.95#ibcon#read 5, iclass 11, count 0 2006.190.08:12:29.95#ibcon#about to read 6, iclass 11, count 0 2006.190.08:12:29.95#ibcon#read 6, iclass 11, count 0 2006.190.08:12:29.95#ibcon#end of sib2, iclass 11, count 0 2006.190.08:12:29.95#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:12:29.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:12:29.95#ibcon#[25=USB\r\n] 2006.190.08:12:29.95#ibcon#*before write, iclass 11, count 0 2006.190.08:12:29.95#ibcon#enter sib2, iclass 11, count 0 2006.190.08:12:29.95#ibcon#flushed, iclass 11, count 0 2006.190.08:12:29.95#ibcon#about to write, iclass 11, count 0 2006.190.08:12:29.95#ibcon#wrote, iclass 11, count 0 2006.190.08:12:29.95#ibcon#about to read 3, iclass 11, count 0 2006.190.08:12:29.98#ibcon#read 3, iclass 11, count 0 2006.190.08:12:29.98#ibcon#about to read 4, iclass 11, count 0 2006.190.08:12:29.98#ibcon#read 4, iclass 11, count 0 2006.190.08:12:29.98#ibcon#about to read 5, iclass 11, count 0 2006.190.08:12:29.98#ibcon#read 5, iclass 11, count 0 2006.190.08:12:29.98#ibcon#about to read 6, iclass 11, count 0 2006.190.08:12:29.98#ibcon#read 6, iclass 11, count 0 2006.190.08:12:29.98#ibcon#end of sib2, iclass 11, count 0 2006.190.08:12:29.98#ibcon#*after write, iclass 11, count 0 2006.190.08:12:29.98#ibcon#*before return 0, iclass 11, count 0 2006.190.08:12:29.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:12:29.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:12:29.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:12:29.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:12:29.98$vc4f8/valo=7,832.99 2006.190.08:12:29.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.08:12:29.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.08:12:29.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:29.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:12:29.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:12:29.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:12:29.98#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:12:29.98#ibcon#first serial, iclass 13, count 0 2006.190.08:12:29.98#ibcon#enter sib2, iclass 13, count 0 2006.190.08:12:29.98#ibcon#flushed, iclass 13, count 0 2006.190.08:12:29.98#ibcon#about to write, iclass 13, count 0 2006.190.08:12:29.98#ibcon#wrote, iclass 13, count 0 2006.190.08:12:29.98#ibcon#about to read 3, iclass 13, count 0 2006.190.08:12:30.00#ibcon#read 3, iclass 13, count 0 2006.190.08:12:30.00#ibcon#about to read 4, iclass 13, count 0 2006.190.08:12:30.00#ibcon#read 4, iclass 13, count 0 2006.190.08:12:30.00#ibcon#about to read 5, iclass 13, count 0 2006.190.08:12:30.00#ibcon#read 5, iclass 13, count 0 2006.190.08:12:30.00#ibcon#about to read 6, iclass 13, count 0 2006.190.08:12:30.00#ibcon#read 6, iclass 13, count 0 2006.190.08:12:30.00#ibcon#end of sib2, iclass 13, count 0 2006.190.08:12:30.00#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:12:30.00#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:12:30.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:12:30.00#ibcon#*before write, iclass 13, count 0 2006.190.08:12:30.00#ibcon#enter sib2, iclass 13, count 0 2006.190.08:12:30.00#ibcon#flushed, iclass 13, count 0 2006.190.08:12:30.00#ibcon#about to write, iclass 13, count 0 2006.190.08:12:30.00#ibcon#wrote, iclass 13, count 0 2006.190.08:12:30.00#ibcon#about to read 3, iclass 13, count 0 2006.190.08:12:30.04#ibcon#read 3, iclass 13, count 0 2006.190.08:12:30.04#ibcon#about to read 4, iclass 13, count 0 2006.190.08:12:30.04#ibcon#read 4, iclass 13, count 0 2006.190.08:12:30.04#ibcon#about to read 5, iclass 13, count 0 2006.190.08:12:30.04#ibcon#read 5, iclass 13, count 0 2006.190.08:12:30.04#ibcon#about to read 6, iclass 13, count 0 2006.190.08:12:30.04#ibcon#read 6, iclass 13, count 0 2006.190.08:12:30.04#ibcon#end of sib2, iclass 13, count 0 2006.190.08:12:30.04#ibcon#*after write, iclass 13, count 0 2006.190.08:12:30.04#ibcon#*before return 0, iclass 13, count 0 2006.190.08:12:30.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:12:30.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:12:30.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:12:30.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:12:30.04$vc4f8/va=7,6 2006.190.08:12:30.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.08:12:30.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.08:12:30.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:30.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:12:30.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:12:30.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:12:30.10#ibcon#enter wrdev, iclass 15, count 2 2006.190.08:12:30.10#ibcon#first serial, iclass 15, count 2 2006.190.08:12:30.10#ibcon#enter sib2, iclass 15, count 2 2006.190.08:12:30.10#ibcon#flushed, iclass 15, count 2 2006.190.08:12:30.10#ibcon#about to write, iclass 15, count 2 2006.190.08:12:30.10#ibcon#wrote, iclass 15, count 2 2006.190.08:12:30.10#ibcon#about to read 3, iclass 15, count 2 2006.190.08:12:30.12#ibcon#read 3, iclass 15, count 2 2006.190.08:12:30.12#ibcon#about to read 4, iclass 15, count 2 2006.190.08:12:30.12#ibcon#read 4, iclass 15, count 2 2006.190.08:12:30.12#ibcon#about to read 5, iclass 15, count 2 2006.190.08:12:30.12#ibcon#read 5, iclass 15, count 2 2006.190.08:12:30.12#ibcon#about to read 6, iclass 15, count 2 2006.190.08:12:30.12#ibcon#read 6, iclass 15, count 2 2006.190.08:12:30.12#ibcon#end of sib2, iclass 15, count 2 2006.190.08:12:30.12#ibcon#*mode == 0, iclass 15, count 2 2006.190.08:12:30.12#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.08:12:30.12#ibcon#[25=AT07-06\r\n] 2006.190.08:12:30.12#ibcon#*before write, iclass 15, count 2 2006.190.08:12:30.12#ibcon#enter sib2, iclass 15, count 2 2006.190.08:12:30.12#ibcon#flushed, iclass 15, count 2 2006.190.08:12:30.12#ibcon#about to write, iclass 15, count 2 2006.190.08:12:30.12#ibcon#wrote, iclass 15, count 2 2006.190.08:12:30.12#ibcon#about to read 3, iclass 15, count 2 2006.190.08:12:30.15#ibcon#read 3, iclass 15, count 2 2006.190.08:12:30.15#ibcon#about to read 4, iclass 15, count 2 2006.190.08:12:30.15#ibcon#read 4, iclass 15, count 2 2006.190.08:12:30.15#ibcon#about to read 5, iclass 15, count 2 2006.190.08:12:30.15#ibcon#read 5, iclass 15, count 2 2006.190.08:12:30.15#ibcon#about to read 6, iclass 15, count 2 2006.190.08:12:30.15#ibcon#read 6, iclass 15, count 2 2006.190.08:12:30.15#ibcon#end of sib2, iclass 15, count 2 2006.190.08:12:30.15#ibcon#*after write, iclass 15, count 2 2006.190.08:12:30.15#ibcon#*before return 0, iclass 15, count 2 2006.190.08:12:30.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:12:30.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:12:30.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.08:12:30.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:30.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:12:30.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:12:30.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:12:30.27#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:12:30.27#ibcon#first serial, iclass 15, count 0 2006.190.08:12:30.27#ibcon#enter sib2, iclass 15, count 0 2006.190.08:12:30.27#ibcon#flushed, iclass 15, count 0 2006.190.08:12:30.27#ibcon#about to write, iclass 15, count 0 2006.190.08:12:30.27#ibcon#wrote, iclass 15, count 0 2006.190.08:12:30.27#ibcon#about to read 3, iclass 15, count 0 2006.190.08:12:30.29#ibcon#read 3, iclass 15, count 0 2006.190.08:12:30.29#ibcon#about to read 4, iclass 15, count 0 2006.190.08:12:30.29#ibcon#read 4, iclass 15, count 0 2006.190.08:12:30.29#ibcon#about to read 5, iclass 15, count 0 2006.190.08:12:30.29#ibcon#read 5, iclass 15, count 0 2006.190.08:12:30.29#ibcon#about to read 6, iclass 15, count 0 2006.190.08:12:30.29#ibcon#read 6, iclass 15, count 0 2006.190.08:12:30.29#ibcon#end of sib2, iclass 15, count 0 2006.190.08:12:30.29#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:12:30.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:12:30.29#ibcon#[25=USB\r\n] 2006.190.08:12:30.29#ibcon#*before write, iclass 15, count 0 2006.190.08:12:30.29#ibcon#enter sib2, iclass 15, count 0 2006.190.08:12:30.29#ibcon#flushed, iclass 15, count 0 2006.190.08:12:30.29#ibcon#about to write, iclass 15, count 0 2006.190.08:12:30.29#ibcon#wrote, iclass 15, count 0 2006.190.08:12:30.29#ibcon#about to read 3, iclass 15, count 0 2006.190.08:12:30.32#ibcon#read 3, iclass 15, count 0 2006.190.08:12:30.32#ibcon#about to read 4, iclass 15, count 0 2006.190.08:12:30.32#ibcon#read 4, iclass 15, count 0 2006.190.08:12:30.32#ibcon#about to read 5, iclass 15, count 0 2006.190.08:12:30.32#ibcon#read 5, iclass 15, count 0 2006.190.08:12:30.32#ibcon#about to read 6, iclass 15, count 0 2006.190.08:12:30.32#ibcon#read 6, iclass 15, count 0 2006.190.08:12:30.32#ibcon#end of sib2, iclass 15, count 0 2006.190.08:12:30.32#ibcon#*after write, iclass 15, count 0 2006.190.08:12:30.32#ibcon#*before return 0, iclass 15, count 0 2006.190.08:12:30.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:12:30.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:12:30.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:12:30.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:12:30.32$vc4f8/valo=8,852.99 2006.190.08:12:30.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.08:12:30.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.08:12:30.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:30.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:12:30.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:12:30.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:12:30.32#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:12:30.32#ibcon#first serial, iclass 17, count 0 2006.190.08:12:30.32#ibcon#enter sib2, iclass 17, count 0 2006.190.08:12:30.32#ibcon#flushed, iclass 17, count 0 2006.190.08:12:30.32#ibcon#about to write, iclass 17, count 0 2006.190.08:12:30.32#ibcon#wrote, iclass 17, count 0 2006.190.08:12:30.32#ibcon#about to read 3, iclass 17, count 0 2006.190.08:12:30.34#ibcon#read 3, iclass 17, count 0 2006.190.08:12:30.34#ibcon#about to read 4, iclass 17, count 0 2006.190.08:12:30.34#ibcon#read 4, iclass 17, count 0 2006.190.08:12:30.34#ibcon#about to read 5, iclass 17, count 0 2006.190.08:12:30.34#ibcon#read 5, iclass 17, count 0 2006.190.08:12:30.34#ibcon#about to read 6, iclass 17, count 0 2006.190.08:12:30.34#ibcon#read 6, iclass 17, count 0 2006.190.08:12:30.34#ibcon#end of sib2, iclass 17, count 0 2006.190.08:12:30.34#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:12:30.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:12:30.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:12:30.34#ibcon#*before write, iclass 17, count 0 2006.190.08:12:30.34#ibcon#enter sib2, iclass 17, count 0 2006.190.08:12:30.34#ibcon#flushed, iclass 17, count 0 2006.190.08:12:30.34#ibcon#about to write, iclass 17, count 0 2006.190.08:12:30.34#ibcon#wrote, iclass 17, count 0 2006.190.08:12:30.34#ibcon#about to read 3, iclass 17, count 0 2006.190.08:12:30.38#ibcon#read 3, iclass 17, count 0 2006.190.08:12:30.38#ibcon#about to read 4, iclass 17, count 0 2006.190.08:12:30.38#ibcon#read 4, iclass 17, count 0 2006.190.08:12:30.38#ibcon#about to read 5, iclass 17, count 0 2006.190.08:12:30.38#ibcon#read 5, iclass 17, count 0 2006.190.08:12:30.38#ibcon#about to read 6, iclass 17, count 0 2006.190.08:12:30.38#ibcon#read 6, iclass 17, count 0 2006.190.08:12:30.38#ibcon#end of sib2, iclass 17, count 0 2006.190.08:12:30.38#ibcon#*after write, iclass 17, count 0 2006.190.08:12:30.38#ibcon#*before return 0, iclass 17, count 0 2006.190.08:12:30.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:12:30.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:12:30.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:12:30.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:12:30.38$vc4f8/va=8,6 2006.190.08:12:30.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.08:12:30.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.08:12:30.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:30.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:12:30.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:12:30.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:12:30.44#ibcon#enter wrdev, iclass 19, count 2 2006.190.08:12:30.44#ibcon#first serial, iclass 19, count 2 2006.190.08:12:30.44#ibcon#enter sib2, iclass 19, count 2 2006.190.08:12:30.44#ibcon#flushed, iclass 19, count 2 2006.190.08:12:30.44#ibcon#about to write, iclass 19, count 2 2006.190.08:12:30.44#ibcon#wrote, iclass 19, count 2 2006.190.08:12:30.44#ibcon#about to read 3, iclass 19, count 2 2006.190.08:12:30.46#ibcon#read 3, iclass 19, count 2 2006.190.08:12:30.46#ibcon#about to read 4, iclass 19, count 2 2006.190.08:12:30.46#ibcon#read 4, iclass 19, count 2 2006.190.08:12:30.46#ibcon#about to read 5, iclass 19, count 2 2006.190.08:12:30.46#ibcon#read 5, iclass 19, count 2 2006.190.08:12:30.46#ibcon#about to read 6, iclass 19, count 2 2006.190.08:12:30.46#ibcon#read 6, iclass 19, count 2 2006.190.08:12:30.46#ibcon#end of sib2, iclass 19, count 2 2006.190.08:12:30.46#ibcon#*mode == 0, iclass 19, count 2 2006.190.08:12:30.46#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.08:12:30.46#ibcon#[25=AT08-06\r\n] 2006.190.08:12:30.46#ibcon#*before write, iclass 19, count 2 2006.190.08:12:30.46#ibcon#enter sib2, iclass 19, count 2 2006.190.08:12:30.46#ibcon#flushed, iclass 19, count 2 2006.190.08:12:30.46#ibcon#about to write, iclass 19, count 2 2006.190.08:12:30.46#ibcon#wrote, iclass 19, count 2 2006.190.08:12:30.46#ibcon#about to read 3, iclass 19, count 2 2006.190.08:12:30.49#ibcon#read 3, iclass 19, count 2 2006.190.08:12:30.49#ibcon#about to read 4, iclass 19, count 2 2006.190.08:12:30.49#ibcon#read 4, iclass 19, count 2 2006.190.08:12:30.49#ibcon#about to read 5, iclass 19, count 2 2006.190.08:12:30.49#ibcon#read 5, iclass 19, count 2 2006.190.08:12:30.49#ibcon#about to read 6, iclass 19, count 2 2006.190.08:12:30.49#ibcon#read 6, iclass 19, count 2 2006.190.08:12:30.49#ibcon#end of sib2, iclass 19, count 2 2006.190.08:12:30.49#ibcon#*after write, iclass 19, count 2 2006.190.08:12:30.49#ibcon#*before return 0, iclass 19, count 2 2006.190.08:12:30.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:12:30.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:12:30.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.08:12:30.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:30.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:12:30.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:12:30.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:12:30.61#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:12:30.61#ibcon#first serial, iclass 19, count 0 2006.190.08:12:30.61#ibcon#enter sib2, iclass 19, count 0 2006.190.08:12:30.61#ibcon#flushed, iclass 19, count 0 2006.190.08:12:30.61#ibcon#about to write, iclass 19, count 0 2006.190.08:12:30.61#ibcon#wrote, iclass 19, count 0 2006.190.08:12:30.61#ibcon#about to read 3, iclass 19, count 0 2006.190.08:12:30.63#ibcon#read 3, iclass 19, count 0 2006.190.08:12:30.63#ibcon#about to read 4, iclass 19, count 0 2006.190.08:12:30.63#ibcon#read 4, iclass 19, count 0 2006.190.08:12:30.63#ibcon#about to read 5, iclass 19, count 0 2006.190.08:12:30.63#ibcon#read 5, iclass 19, count 0 2006.190.08:12:30.63#ibcon#about to read 6, iclass 19, count 0 2006.190.08:12:30.63#ibcon#read 6, iclass 19, count 0 2006.190.08:12:30.63#ibcon#end of sib2, iclass 19, count 0 2006.190.08:12:30.63#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:12:30.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:12:30.63#ibcon#[25=USB\r\n] 2006.190.08:12:30.63#ibcon#*before write, iclass 19, count 0 2006.190.08:12:30.63#ibcon#enter sib2, iclass 19, count 0 2006.190.08:12:30.63#ibcon#flushed, iclass 19, count 0 2006.190.08:12:30.63#ibcon#about to write, iclass 19, count 0 2006.190.08:12:30.63#ibcon#wrote, iclass 19, count 0 2006.190.08:12:30.63#ibcon#about to read 3, iclass 19, count 0 2006.190.08:12:30.66#ibcon#read 3, iclass 19, count 0 2006.190.08:12:30.66#ibcon#about to read 4, iclass 19, count 0 2006.190.08:12:30.66#ibcon#read 4, iclass 19, count 0 2006.190.08:12:30.66#ibcon#about to read 5, iclass 19, count 0 2006.190.08:12:30.66#ibcon#read 5, iclass 19, count 0 2006.190.08:12:30.66#ibcon#about to read 6, iclass 19, count 0 2006.190.08:12:30.66#ibcon#read 6, iclass 19, count 0 2006.190.08:12:30.66#ibcon#end of sib2, iclass 19, count 0 2006.190.08:12:30.66#ibcon#*after write, iclass 19, count 0 2006.190.08:12:30.66#ibcon#*before return 0, iclass 19, count 0 2006.190.08:12:30.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:12:30.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:12:30.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:12:30.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:12:30.66$vc4f8/vblo=1,632.99 2006.190.08:12:30.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.08:12:30.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.08:12:30.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:30.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:12:30.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:12:30.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:12:30.66#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:12:30.66#ibcon#first serial, iclass 21, count 0 2006.190.08:12:30.66#ibcon#enter sib2, iclass 21, count 0 2006.190.08:12:30.66#ibcon#flushed, iclass 21, count 0 2006.190.08:12:30.66#ibcon#about to write, iclass 21, count 0 2006.190.08:12:30.66#ibcon#wrote, iclass 21, count 0 2006.190.08:12:30.66#ibcon#about to read 3, iclass 21, count 0 2006.190.08:12:30.68#ibcon#read 3, iclass 21, count 0 2006.190.08:12:30.68#ibcon#about to read 4, iclass 21, count 0 2006.190.08:12:30.68#ibcon#read 4, iclass 21, count 0 2006.190.08:12:30.68#ibcon#about to read 5, iclass 21, count 0 2006.190.08:12:30.68#ibcon#read 5, iclass 21, count 0 2006.190.08:12:30.68#ibcon#about to read 6, iclass 21, count 0 2006.190.08:12:30.68#ibcon#read 6, iclass 21, count 0 2006.190.08:12:30.68#ibcon#end of sib2, iclass 21, count 0 2006.190.08:12:30.68#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:12:30.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:12:30.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:12:30.68#ibcon#*before write, iclass 21, count 0 2006.190.08:12:30.68#ibcon#enter sib2, iclass 21, count 0 2006.190.08:12:30.68#ibcon#flushed, iclass 21, count 0 2006.190.08:12:30.68#ibcon#about to write, iclass 21, count 0 2006.190.08:12:30.68#ibcon#wrote, iclass 21, count 0 2006.190.08:12:30.68#ibcon#about to read 3, iclass 21, count 0 2006.190.08:12:30.72#ibcon#read 3, iclass 21, count 0 2006.190.08:12:30.72#ibcon#about to read 4, iclass 21, count 0 2006.190.08:12:30.72#ibcon#read 4, iclass 21, count 0 2006.190.08:12:30.72#ibcon#about to read 5, iclass 21, count 0 2006.190.08:12:30.72#ibcon#read 5, iclass 21, count 0 2006.190.08:12:30.72#ibcon#about to read 6, iclass 21, count 0 2006.190.08:12:30.72#ibcon#read 6, iclass 21, count 0 2006.190.08:12:30.72#ibcon#end of sib2, iclass 21, count 0 2006.190.08:12:30.72#ibcon#*after write, iclass 21, count 0 2006.190.08:12:30.72#ibcon#*before return 0, iclass 21, count 0 2006.190.08:12:30.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:12:30.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:12:30.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:12:30.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:12:30.72$vc4f8/vb=1,4 2006.190.08:12:30.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.08:12:30.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.08:12:30.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:30.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:12:30.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:12:30.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:12:30.72#ibcon#enter wrdev, iclass 23, count 2 2006.190.08:12:30.72#ibcon#first serial, iclass 23, count 2 2006.190.08:12:30.72#ibcon#enter sib2, iclass 23, count 2 2006.190.08:12:30.72#ibcon#flushed, iclass 23, count 2 2006.190.08:12:30.72#ibcon#about to write, iclass 23, count 2 2006.190.08:12:30.72#ibcon#wrote, iclass 23, count 2 2006.190.08:12:30.72#ibcon#about to read 3, iclass 23, count 2 2006.190.08:12:30.74#ibcon#read 3, iclass 23, count 2 2006.190.08:12:30.74#ibcon#about to read 4, iclass 23, count 2 2006.190.08:12:30.74#ibcon#read 4, iclass 23, count 2 2006.190.08:12:30.74#ibcon#about to read 5, iclass 23, count 2 2006.190.08:12:30.74#ibcon#read 5, iclass 23, count 2 2006.190.08:12:30.74#ibcon#about to read 6, iclass 23, count 2 2006.190.08:12:30.74#ibcon#read 6, iclass 23, count 2 2006.190.08:12:30.74#ibcon#end of sib2, iclass 23, count 2 2006.190.08:12:30.74#ibcon#*mode == 0, iclass 23, count 2 2006.190.08:12:30.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.08:12:30.74#ibcon#[27=AT01-04\r\n] 2006.190.08:12:30.74#ibcon#*before write, iclass 23, count 2 2006.190.08:12:30.74#ibcon#enter sib2, iclass 23, count 2 2006.190.08:12:30.74#ibcon#flushed, iclass 23, count 2 2006.190.08:12:30.74#ibcon#about to write, iclass 23, count 2 2006.190.08:12:30.74#ibcon#wrote, iclass 23, count 2 2006.190.08:12:30.74#ibcon#about to read 3, iclass 23, count 2 2006.190.08:12:30.77#ibcon#read 3, iclass 23, count 2 2006.190.08:12:30.77#ibcon#about to read 4, iclass 23, count 2 2006.190.08:12:30.77#ibcon#read 4, iclass 23, count 2 2006.190.08:12:30.77#ibcon#about to read 5, iclass 23, count 2 2006.190.08:12:30.77#ibcon#read 5, iclass 23, count 2 2006.190.08:12:30.77#ibcon#about to read 6, iclass 23, count 2 2006.190.08:12:30.77#ibcon#read 6, iclass 23, count 2 2006.190.08:12:30.77#ibcon#end of sib2, iclass 23, count 2 2006.190.08:12:30.77#ibcon#*after write, iclass 23, count 2 2006.190.08:12:30.77#ibcon#*before return 0, iclass 23, count 2 2006.190.08:12:30.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:12:30.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:12:30.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.08:12:30.77#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:30.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:12:30.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:12:30.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:12:30.89#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:12:30.89#ibcon#first serial, iclass 23, count 0 2006.190.08:12:30.89#ibcon#enter sib2, iclass 23, count 0 2006.190.08:12:30.89#ibcon#flushed, iclass 23, count 0 2006.190.08:12:30.89#ibcon#about to write, iclass 23, count 0 2006.190.08:12:30.89#ibcon#wrote, iclass 23, count 0 2006.190.08:12:30.89#ibcon#about to read 3, iclass 23, count 0 2006.190.08:12:30.91#ibcon#read 3, iclass 23, count 0 2006.190.08:12:30.91#ibcon#about to read 4, iclass 23, count 0 2006.190.08:12:30.91#ibcon#read 4, iclass 23, count 0 2006.190.08:12:30.91#ibcon#about to read 5, iclass 23, count 0 2006.190.08:12:30.91#ibcon#read 5, iclass 23, count 0 2006.190.08:12:30.91#ibcon#about to read 6, iclass 23, count 0 2006.190.08:12:30.91#ibcon#read 6, iclass 23, count 0 2006.190.08:12:30.91#ibcon#end of sib2, iclass 23, count 0 2006.190.08:12:30.91#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:12:30.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:12:30.91#ibcon#[27=USB\r\n] 2006.190.08:12:30.91#ibcon#*before write, iclass 23, count 0 2006.190.08:12:30.91#ibcon#enter sib2, iclass 23, count 0 2006.190.08:12:30.91#ibcon#flushed, iclass 23, count 0 2006.190.08:12:30.91#ibcon#about to write, iclass 23, count 0 2006.190.08:12:30.91#ibcon#wrote, iclass 23, count 0 2006.190.08:12:30.91#ibcon#about to read 3, iclass 23, count 0 2006.190.08:12:30.94#ibcon#read 3, iclass 23, count 0 2006.190.08:12:30.94#ibcon#about to read 4, iclass 23, count 0 2006.190.08:12:30.94#ibcon#read 4, iclass 23, count 0 2006.190.08:12:30.94#ibcon#about to read 5, iclass 23, count 0 2006.190.08:12:30.94#ibcon#read 5, iclass 23, count 0 2006.190.08:12:30.94#ibcon#about to read 6, iclass 23, count 0 2006.190.08:12:30.94#ibcon#read 6, iclass 23, count 0 2006.190.08:12:30.94#ibcon#end of sib2, iclass 23, count 0 2006.190.08:12:30.94#ibcon#*after write, iclass 23, count 0 2006.190.08:12:30.94#ibcon#*before return 0, iclass 23, count 0 2006.190.08:12:30.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:12:30.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:12:30.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:12:30.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:12:30.94$vc4f8/vblo=2,640.99 2006.190.08:12:30.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.08:12:30.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.08:12:30.94#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:30.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:30.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:30.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:30.94#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:12:30.94#ibcon#first serial, iclass 25, count 0 2006.190.08:12:30.94#ibcon#enter sib2, iclass 25, count 0 2006.190.08:12:30.94#ibcon#flushed, iclass 25, count 0 2006.190.08:12:30.94#ibcon#about to write, iclass 25, count 0 2006.190.08:12:30.94#ibcon#wrote, iclass 25, count 0 2006.190.08:12:30.94#ibcon#about to read 3, iclass 25, count 0 2006.190.08:12:30.96#ibcon#read 3, iclass 25, count 0 2006.190.08:12:30.96#ibcon#about to read 4, iclass 25, count 0 2006.190.08:12:30.96#ibcon#read 4, iclass 25, count 0 2006.190.08:12:30.96#ibcon#about to read 5, iclass 25, count 0 2006.190.08:12:30.96#ibcon#read 5, iclass 25, count 0 2006.190.08:12:30.96#ibcon#about to read 6, iclass 25, count 0 2006.190.08:12:30.96#ibcon#read 6, iclass 25, count 0 2006.190.08:12:30.96#ibcon#end of sib2, iclass 25, count 0 2006.190.08:12:30.96#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:12:30.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:12:30.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:12:30.96#ibcon#*before write, iclass 25, count 0 2006.190.08:12:30.96#ibcon#enter sib2, iclass 25, count 0 2006.190.08:12:30.96#ibcon#flushed, iclass 25, count 0 2006.190.08:12:30.96#ibcon#about to write, iclass 25, count 0 2006.190.08:12:30.96#ibcon#wrote, iclass 25, count 0 2006.190.08:12:30.96#ibcon#about to read 3, iclass 25, count 0 2006.190.08:12:31.00#ibcon#read 3, iclass 25, count 0 2006.190.08:12:31.00#ibcon#about to read 4, iclass 25, count 0 2006.190.08:12:31.00#ibcon#read 4, iclass 25, count 0 2006.190.08:12:31.00#ibcon#about to read 5, iclass 25, count 0 2006.190.08:12:31.00#ibcon#read 5, iclass 25, count 0 2006.190.08:12:31.00#ibcon#about to read 6, iclass 25, count 0 2006.190.08:12:31.00#ibcon#read 6, iclass 25, count 0 2006.190.08:12:31.00#ibcon#end of sib2, iclass 25, count 0 2006.190.08:12:31.00#ibcon#*after write, iclass 25, count 0 2006.190.08:12:31.00#ibcon#*before return 0, iclass 25, count 0 2006.190.08:12:31.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:31.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:12:31.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:12:31.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:12:31.00$vc4f8/vb=2,4 2006.190.08:12:31.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.08:12:31.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.08:12:31.00#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:31.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:31.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:31.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:31.06#ibcon#enter wrdev, iclass 27, count 2 2006.190.08:12:31.06#ibcon#first serial, iclass 27, count 2 2006.190.08:12:31.06#ibcon#enter sib2, iclass 27, count 2 2006.190.08:12:31.06#ibcon#flushed, iclass 27, count 2 2006.190.08:12:31.06#ibcon#about to write, iclass 27, count 2 2006.190.08:12:31.06#ibcon#wrote, iclass 27, count 2 2006.190.08:12:31.06#ibcon#about to read 3, iclass 27, count 2 2006.190.08:12:31.08#ibcon#read 3, iclass 27, count 2 2006.190.08:12:31.08#ibcon#about to read 4, iclass 27, count 2 2006.190.08:12:31.08#ibcon#read 4, iclass 27, count 2 2006.190.08:12:31.08#ibcon#about to read 5, iclass 27, count 2 2006.190.08:12:31.08#ibcon#read 5, iclass 27, count 2 2006.190.08:12:31.08#ibcon#about to read 6, iclass 27, count 2 2006.190.08:12:31.08#ibcon#read 6, iclass 27, count 2 2006.190.08:12:31.08#ibcon#end of sib2, iclass 27, count 2 2006.190.08:12:31.08#ibcon#*mode == 0, iclass 27, count 2 2006.190.08:12:31.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.08:12:31.08#ibcon#[27=AT02-04\r\n] 2006.190.08:12:31.08#ibcon#*before write, iclass 27, count 2 2006.190.08:12:31.08#ibcon#enter sib2, iclass 27, count 2 2006.190.08:12:31.08#ibcon#flushed, iclass 27, count 2 2006.190.08:12:31.08#ibcon#about to write, iclass 27, count 2 2006.190.08:12:31.08#ibcon#wrote, iclass 27, count 2 2006.190.08:12:31.08#ibcon#about to read 3, iclass 27, count 2 2006.190.08:12:31.11#ibcon#read 3, iclass 27, count 2 2006.190.08:12:31.11#ibcon#about to read 4, iclass 27, count 2 2006.190.08:12:31.11#ibcon#read 4, iclass 27, count 2 2006.190.08:12:31.11#ibcon#about to read 5, iclass 27, count 2 2006.190.08:12:31.11#ibcon#read 5, iclass 27, count 2 2006.190.08:12:31.11#ibcon#about to read 6, iclass 27, count 2 2006.190.08:12:31.11#ibcon#read 6, iclass 27, count 2 2006.190.08:12:31.11#ibcon#end of sib2, iclass 27, count 2 2006.190.08:12:31.11#ibcon#*after write, iclass 27, count 2 2006.190.08:12:31.11#ibcon#*before return 0, iclass 27, count 2 2006.190.08:12:31.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:31.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:12:31.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.08:12:31.11#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:31.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:31.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:31.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:31.23#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:12:31.23#ibcon#first serial, iclass 27, count 0 2006.190.08:12:31.23#ibcon#enter sib2, iclass 27, count 0 2006.190.08:12:31.23#ibcon#flushed, iclass 27, count 0 2006.190.08:12:31.23#ibcon#about to write, iclass 27, count 0 2006.190.08:12:31.23#ibcon#wrote, iclass 27, count 0 2006.190.08:12:31.23#ibcon#about to read 3, iclass 27, count 0 2006.190.08:12:31.25#ibcon#read 3, iclass 27, count 0 2006.190.08:12:31.25#ibcon#about to read 4, iclass 27, count 0 2006.190.08:12:31.25#ibcon#read 4, iclass 27, count 0 2006.190.08:12:31.25#ibcon#about to read 5, iclass 27, count 0 2006.190.08:12:31.25#ibcon#read 5, iclass 27, count 0 2006.190.08:12:31.25#ibcon#about to read 6, iclass 27, count 0 2006.190.08:12:31.25#ibcon#read 6, iclass 27, count 0 2006.190.08:12:31.25#ibcon#end of sib2, iclass 27, count 0 2006.190.08:12:31.25#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:12:31.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:12:31.25#ibcon#[27=USB\r\n] 2006.190.08:12:31.25#ibcon#*before write, iclass 27, count 0 2006.190.08:12:31.25#ibcon#enter sib2, iclass 27, count 0 2006.190.08:12:31.25#ibcon#flushed, iclass 27, count 0 2006.190.08:12:31.25#ibcon#about to write, iclass 27, count 0 2006.190.08:12:31.25#ibcon#wrote, iclass 27, count 0 2006.190.08:12:31.25#ibcon#about to read 3, iclass 27, count 0 2006.190.08:12:31.28#ibcon#read 3, iclass 27, count 0 2006.190.08:12:31.28#ibcon#about to read 4, iclass 27, count 0 2006.190.08:12:31.28#ibcon#read 4, iclass 27, count 0 2006.190.08:12:31.28#ibcon#about to read 5, iclass 27, count 0 2006.190.08:12:31.28#ibcon#read 5, iclass 27, count 0 2006.190.08:12:31.28#ibcon#about to read 6, iclass 27, count 0 2006.190.08:12:31.28#ibcon#read 6, iclass 27, count 0 2006.190.08:12:31.28#ibcon#end of sib2, iclass 27, count 0 2006.190.08:12:31.28#ibcon#*after write, iclass 27, count 0 2006.190.08:12:31.28#ibcon#*before return 0, iclass 27, count 0 2006.190.08:12:31.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:31.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:12:31.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:12:31.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:12:31.28$vc4f8/vblo=3,656.99 2006.190.08:12:31.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.08:12:31.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.08:12:31.28#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:31.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:31.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:31.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:31.28#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:12:31.28#ibcon#first serial, iclass 29, count 0 2006.190.08:12:31.28#ibcon#enter sib2, iclass 29, count 0 2006.190.08:12:31.28#ibcon#flushed, iclass 29, count 0 2006.190.08:12:31.28#ibcon#about to write, iclass 29, count 0 2006.190.08:12:31.28#ibcon#wrote, iclass 29, count 0 2006.190.08:12:31.28#ibcon#about to read 3, iclass 29, count 0 2006.190.08:12:31.30#ibcon#read 3, iclass 29, count 0 2006.190.08:12:31.30#ibcon#about to read 4, iclass 29, count 0 2006.190.08:12:31.30#ibcon#read 4, iclass 29, count 0 2006.190.08:12:31.30#ibcon#about to read 5, iclass 29, count 0 2006.190.08:12:31.30#ibcon#read 5, iclass 29, count 0 2006.190.08:12:31.30#ibcon#about to read 6, iclass 29, count 0 2006.190.08:12:31.30#ibcon#read 6, iclass 29, count 0 2006.190.08:12:31.30#ibcon#end of sib2, iclass 29, count 0 2006.190.08:12:31.30#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:12:31.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:12:31.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:12:31.30#ibcon#*before write, iclass 29, count 0 2006.190.08:12:31.30#ibcon#enter sib2, iclass 29, count 0 2006.190.08:12:31.30#ibcon#flushed, iclass 29, count 0 2006.190.08:12:31.30#ibcon#about to write, iclass 29, count 0 2006.190.08:12:31.30#ibcon#wrote, iclass 29, count 0 2006.190.08:12:31.30#ibcon#about to read 3, iclass 29, count 0 2006.190.08:12:31.34#ibcon#read 3, iclass 29, count 0 2006.190.08:12:31.34#ibcon#about to read 4, iclass 29, count 0 2006.190.08:12:31.34#ibcon#read 4, iclass 29, count 0 2006.190.08:12:31.34#ibcon#about to read 5, iclass 29, count 0 2006.190.08:12:31.34#ibcon#read 5, iclass 29, count 0 2006.190.08:12:31.34#ibcon#about to read 6, iclass 29, count 0 2006.190.08:12:31.34#ibcon#read 6, iclass 29, count 0 2006.190.08:12:31.34#ibcon#end of sib2, iclass 29, count 0 2006.190.08:12:31.34#ibcon#*after write, iclass 29, count 0 2006.190.08:12:31.34#ibcon#*before return 0, iclass 29, count 0 2006.190.08:12:31.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:31.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:12:31.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:12:31.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:12:31.34$vc4f8/vb=3,4 2006.190.08:12:31.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.08:12:31.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.08:12:31.34#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:31.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:31.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:31.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:31.40#ibcon#enter wrdev, iclass 31, count 2 2006.190.08:12:31.40#ibcon#first serial, iclass 31, count 2 2006.190.08:12:31.40#ibcon#enter sib2, iclass 31, count 2 2006.190.08:12:31.40#ibcon#flushed, iclass 31, count 2 2006.190.08:12:31.40#ibcon#about to write, iclass 31, count 2 2006.190.08:12:31.40#ibcon#wrote, iclass 31, count 2 2006.190.08:12:31.40#ibcon#about to read 3, iclass 31, count 2 2006.190.08:12:31.42#ibcon#read 3, iclass 31, count 2 2006.190.08:12:31.42#ibcon#about to read 4, iclass 31, count 2 2006.190.08:12:31.42#ibcon#read 4, iclass 31, count 2 2006.190.08:12:31.42#ibcon#about to read 5, iclass 31, count 2 2006.190.08:12:31.42#ibcon#read 5, iclass 31, count 2 2006.190.08:12:31.42#ibcon#about to read 6, iclass 31, count 2 2006.190.08:12:31.42#ibcon#read 6, iclass 31, count 2 2006.190.08:12:31.42#ibcon#end of sib2, iclass 31, count 2 2006.190.08:12:31.42#ibcon#*mode == 0, iclass 31, count 2 2006.190.08:12:31.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.08:12:31.42#ibcon#[27=AT03-04\r\n] 2006.190.08:12:31.42#ibcon#*before write, iclass 31, count 2 2006.190.08:12:31.42#ibcon#enter sib2, iclass 31, count 2 2006.190.08:12:31.42#ibcon#flushed, iclass 31, count 2 2006.190.08:12:31.42#ibcon#about to write, iclass 31, count 2 2006.190.08:12:31.42#ibcon#wrote, iclass 31, count 2 2006.190.08:12:31.42#ibcon#about to read 3, iclass 31, count 2 2006.190.08:12:31.45#ibcon#read 3, iclass 31, count 2 2006.190.08:12:31.45#ibcon#about to read 4, iclass 31, count 2 2006.190.08:12:31.45#ibcon#read 4, iclass 31, count 2 2006.190.08:12:31.45#ibcon#about to read 5, iclass 31, count 2 2006.190.08:12:31.45#ibcon#read 5, iclass 31, count 2 2006.190.08:12:31.45#ibcon#about to read 6, iclass 31, count 2 2006.190.08:12:31.45#ibcon#read 6, iclass 31, count 2 2006.190.08:12:31.45#ibcon#end of sib2, iclass 31, count 2 2006.190.08:12:31.45#ibcon#*after write, iclass 31, count 2 2006.190.08:12:31.45#ibcon#*before return 0, iclass 31, count 2 2006.190.08:12:31.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:31.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:12:31.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.08:12:31.45#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:31.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:31.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:31.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:31.57#ibcon#enter wrdev, iclass 31, count 0 2006.190.08:12:31.57#ibcon#first serial, iclass 31, count 0 2006.190.08:12:31.57#ibcon#enter sib2, iclass 31, count 0 2006.190.08:12:31.57#ibcon#flushed, iclass 31, count 0 2006.190.08:12:31.57#ibcon#about to write, iclass 31, count 0 2006.190.08:12:31.57#ibcon#wrote, iclass 31, count 0 2006.190.08:12:31.57#ibcon#about to read 3, iclass 31, count 0 2006.190.08:12:31.59#ibcon#read 3, iclass 31, count 0 2006.190.08:12:31.59#ibcon#about to read 4, iclass 31, count 0 2006.190.08:12:31.59#ibcon#read 4, iclass 31, count 0 2006.190.08:12:31.59#ibcon#about to read 5, iclass 31, count 0 2006.190.08:12:31.59#ibcon#read 5, iclass 31, count 0 2006.190.08:12:31.59#ibcon#about to read 6, iclass 31, count 0 2006.190.08:12:31.59#ibcon#read 6, iclass 31, count 0 2006.190.08:12:31.59#ibcon#end of sib2, iclass 31, count 0 2006.190.08:12:31.59#ibcon#*mode == 0, iclass 31, count 0 2006.190.08:12:31.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.08:12:31.59#ibcon#[27=USB\r\n] 2006.190.08:12:31.59#ibcon#*before write, iclass 31, count 0 2006.190.08:12:31.59#ibcon#enter sib2, iclass 31, count 0 2006.190.08:12:31.59#ibcon#flushed, iclass 31, count 0 2006.190.08:12:31.59#ibcon#about to write, iclass 31, count 0 2006.190.08:12:31.59#ibcon#wrote, iclass 31, count 0 2006.190.08:12:31.59#ibcon#about to read 3, iclass 31, count 0 2006.190.08:12:31.62#ibcon#read 3, iclass 31, count 0 2006.190.08:12:31.62#ibcon#about to read 4, iclass 31, count 0 2006.190.08:12:31.62#ibcon#read 4, iclass 31, count 0 2006.190.08:12:31.62#ibcon#about to read 5, iclass 31, count 0 2006.190.08:12:31.62#ibcon#read 5, iclass 31, count 0 2006.190.08:12:31.62#ibcon#about to read 6, iclass 31, count 0 2006.190.08:12:31.62#ibcon#read 6, iclass 31, count 0 2006.190.08:12:31.62#ibcon#end of sib2, iclass 31, count 0 2006.190.08:12:31.62#ibcon#*after write, iclass 31, count 0 2006.190.08:12:31.62#ibcon#*before return 0, iclass 31, count 0 2006.190.08:12:31.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:31.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:12:31.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.08:12:31.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.08:12:31.62$vc4f8/vblo=4,712.99 2006.190.08:12:31.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.08:12:31.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.08:12:31.62#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:31.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:31.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:31.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:31.62#ibcon#enter wrdev, iclass 33, count 0 2006.190.08:12:31.62#ibcon#first serial, iclass 33, count 0 2006.190.08:12:31.62#ibcon#enter sib2, iclass 33, count 0 2006.190.08:12:31.62#ibcon#flushed, iclass 33, count 0 2006.190.08:12:31.62#ibcon#about to write, iclass 33, count 0 2006.190.08:12:31.62#ibcon#wrote, iclass 33, count 0 2006.190.08:12:31.62#ibcon#about to read 3, iclass 33, count 0 2006.190.08:12:31.64#ibcon#read 3, iclass 33, count 0 2006.190.08:12:31.64#ibcon#about to read 4, iclass 33, count 0 2006.190.08:12:31.64#ibcon#read 4, iclass 33, count 0 2006.190.08:12:31.64#ibcon#about to read 5, iclass 33, count 0 2006.190.08:12:31.64#ibcon#read 5, iclass 33, count 0 2006.190.08:12:31.64#ibcon#about to read 6, iclass 33, count 0 2006.190.08:12:31.64#ibcon#read 6, iclass 33, count 0 2006.190.08:12:31.64#ibcon#end of sib2, iclass 33, count 0 2006.190.08:12:31.64#ibcon#*mode == 0, iclass 33, count 0 2006.190.08:12:31.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.08:12:31.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:12:31.64#ibcon#*before write, iclass 33, count 0 2006.190.08:12:31.64#ibcon#enter sib2, iclass 33, count 0 2006.190.08:12:31.64#ibcon#flushed, iclass 33, count 0 2006.190.08:12:31.64#ibcon#about to write, iclass 33, count 0 2006.190.08:12:31.64#ibcon#wrote, iclass 33, count 0 2006.190.08:12:31.64#ibcon#about to read 3, iclass 33, count 0 2006.190.08:12:31.68#ibcon#read 3, iclass 33, count 0 2006.190.08:12:31.68#ibcon#about to read 4, iclass 33, count 0 2006.190.08:12:31.68#ibcon#read 4, iclass 33, count 0 2006.190.08:12:31.68#ibcon#about to read 5, iclass 33, count 0 2006.190.08:12:31.68#ibcon#read 5, iclass 33, count 0 2006.190.08:12:31.68#ibcon#about to read 6, iclass 33, count 0 2006.190.08:12:31.68#ibcon#read 6, iclass 33, count 0 2006.190.08:12:31.68#ibcon#end of sib2, iclass 33, count 0 2006.190.08:12:31.68#ibcon#*after write, iclass 33, count 0 2006.190.08:12:31.68#ibcon#*before return 0, iclass 33, count 0 2006.190.08:12:31.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:31.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:12:31.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.08:12:31.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.08:12:31.68$vc4f8/vb=4,4 2006.190.08:12:31.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.08:12:31.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.08:12:31.68#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:31.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:31.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:31.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:31.74#ibcon#enter wrdev, iclass 35, count 2 2006.190.08:12:31.74#ibcon#first serial, iclass 35, count 2 2006.190.08:12:31.74#ibcon#enter sib2, iclass 35, count 2 2006.190.08:12:31.74#ibcon#flushed, iclass 35, count 2 2006.190.08:12:31.74#ibcon#about to write, iclass 35, count 2 2006.190.08:12:31.74#ibcon#wrote, iclass 35, count 2 2006.190.08:12:31.74#ibcon#about to read 3, iclass 35, count 2 2006.190.08:12:31.76#ibcon#read 3, iclass 35, count 2 2006.190.08:12:31.76#ibcon#about to read 4, iclass 35, count 2 2006.190.08:12:31.76#ibcon#read 4, iclass 35, count 2 2006.190.08:12:31.76#ibcon#about to read 5, iclass 35, count 2 2006.190.08:12:31.76#ibcon#read 5, iclass 35, count 2 2006.190.08:12:31.76#ibcon#about to read 6, iclass 35, count 2 2006.190.08:12:31.76#ibcon#read 6, iclass 35, count 2 2006.190.08:12:31.76#ibcon#end of sib2, iclass 35, count 2 2006.190.08:12:31.76#ibcon#*mode == 0, iclass 35, count 2 2006.190.08:12:31.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.08:12:31.76#ibcon#[27=AT04-04\r\n] 2006.190.08:12:31.76#ibcon#*before write, iclass 35, count 2 2006.190.08:12:31.76#ibcon#enter sib2, iclass 35, count 2 2006.190.08:12:31.76#ibcon#flushed, iclass 35, count 2 2006.190.08:12:31.76#ibcon#about to write, iclass 35, count 2 2006.190.08:12:31.76#ibcon#wrote, iclass 35, count 2 2006.190.08:12:31.76#ibcon#about to read 3, iclass 35, count 2 2006.190.08:12:31.79#ibcon#read 3, iclass 35, count 2 2006.190.08:12:31.79#ibcon#about to read 4, iclass 35, count 2 2006.190.08:12:31.79#ibcon#read 4, iclass 35, count 2 2006.190.08:12:31.79#ibcon#about to read 5, iclass 35, count 2 2006.190.08:12:31.79#ibcon#read 5, iclass 35, count 2 2006.190.08:12:31.79#ibcon#about to read 6, iclass 35, count 2 2006.190.08:12:31.79#ibcon#read 6, iclass 35, count 2 2006.190.08:12:31.79#ibcon#end of sib2, iclass 35, count 2 2006.190.08:12:31.79#ibcon#*after write, iclass 35, count 2 2006.190.08:12:31.79#ibcon#*before return 0, iclass 35, count 2 2006.190.08:12:31.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:31.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:12:31.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.08:12:31.79#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:31.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:31.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:31.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:31.91#ibcon#enter wrdev, iclass 35, count 0 2006.190.08:12:31.91#ibcon#first serial, iclass 35, count 0 2006.190.08:12:31.91#ibcon#enter sib2, iclass 35, count 0 2006.190.08:12:31.91#ibcon#flushed, iclass 35, count 0 2006.190.08:12:31.91#ibcon#about to write, iclass 35, count 0 2006.190.08:12:31.91#ibcon#wrote, iclass 35, count 0 2006.190.08:12:31.91#ibcon#about to read 3, iclass 35, count 0 2006.190.08:12:31.93#ibcon#read 3, iclass 35, count 0 2006.190.08:12:31.93#ibcon#about to read 4, iclass 35, count 0 2006.190.08:12:31.93#ibcon#read 4, iclass 35, count 0 2006.190.08:12:31.93#ibcon#about to read 5, iclass 35, count 0 2006.190.08:12:31.93#ibcon#read 5, iclass 35, count 0 2006.190.08:12:31.93#ibcon#about to read 6, iclass 35, count 0 2006.190.08:12:31.93#ibcon#read 6, iclass 35, count 0 2006.190.08:12:31.93#ibcon#end of sib2, iclass 35, count 0 2006.190.08:12:31.93#ibcon#*mode == 0, iclass 35, count 0 2006.190.08:12:31.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.08:12:31.93#ibcon#[27=USB\r\n] 2006.190.08:12:31.93#ibcon#*before write, iclass 35, count 0 2006.190.08:12:31.93#ibcon#enter sib2, iclass 35, count 0 2006.190.08:12:31.93#ibcon#flushed, iclass 35, count 0 2006.190.08:12:31.93#ibcon#about to write, iclass 35, count 0 2006.190.08:12:31.93#ibcon#wrote, iclass 35, count 0 2006.190.08:12:31.93#ibcon#about to read 3, iclass 35, count 0 2006.190.08:12:31.96#ibcon#read 3, iclass 35, count 0 2006.190.08:12:31.96#ibcon#about to read 4, iclass 35, count 0 2006.190.08:12:31.96#ibcon#read 4, iclass 35, count 0 2006.190.08:12:31.96#ibcon#about to read 5, iclass 35, count 0 2006.190.08:12:31.96#ibcon#read 5, iclass 35, count 0 2006.190.08:12:31.96#ibcon#about to read 6, iclass 35, count 0 2006.190.08:12:31.96#ibcon#read 6, iclass 35, count 0 2006.190.08:12:31.96#ibcon#end of sib2, iclass 35, count 0 2006.190.08:12:31.96#ibcon#*after write, iclass 35, count 0 2006.190.08:12:31.96#ibcon#*before return 0, iclass 35, count 0 2006.190.08:12:31.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:31.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:12:31.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.08:12:31.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.08:12:31.96$vc4f8/vblo=5,744.99 2006.190.08:12:31.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.08:12:31.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.08:12:31.96#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:31.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:31.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:31.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:31.96#ibcon#enter wrdev, iclass 37, count 0 2006.190.08:12:31.96#ibcon#first serial, iclass 37, count 0 2006.190.08:12:31.96#ibcon#enter sib2, iclass 37, count 0 2006.190.08:12:31.96#ibcon#flushed, iclass 37, count 0 2006.190.08:12:31.96#ibcon#about to write, iclass 37, count 0 2006.190.08:12:31.96#ibcon#wrote, iclass 37, count 0 2006.190.08:12:31.96#ibcon#about to read 3, iclass 37, count 0 2006.190.08:12:31.98#ibcon#read 3, iclass 37, count 0 2006.190.08:12:31.98#ibcon#about to read 4, iclass 37, count 0 2006.190.08:12:31.98#ibcon#read 4, iclass 37, count 0 2006.190.08:12:31.98#ibcon#about to read 5, iclass 37, count 0 2006.190.08:12:31.98#ibcon#read 5, iclass 37, count 0 2006.190.08:12:31.98#ibcon#about to read 6, iclass 37, count 0 2006.190.08:12:31.98#ibcon#read 6, iclass 37, count 0 2006.190.08:12:31.98#ibcon#end of sib2, iclass 37, count 0 2006.190.08:12:31.98#ibcon#*mode == 0, iclass 37, count 0 2006.190.08:12:31.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.08:12:31.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:12:31.98#ibcon#*before write, iclass 37, count 0 2006.190.08:12:31.98#ibcon#enter sib2, iclass 37, count 0 2006.190.08:12:31.98#ibcon#flushed, iclass 37, count 0 2006.190.08:12:31.98#ibcon#about to write, iclass 37, count 0 2006.190.08:12:31.98#ibcon#wrote, iclass 37, count 0 2006.190.08:12:31.98#ibcon#about to read 3, iclass 37, count 0 2006.190.08:12:32.02#ibcon#read 3, iclass 37, count 0 2006.190.08:12:32.02#ibcon#about to read 4, iclass 37, count 0 2006.190.08:12:32.02#ibcon#read 4, iclass 37, count 0 2006.190.08:12:32.02#ibcon#about to read 5, iclass 37, count 0 2006.190.08:12:32.02#ibcon#read 5, iclass 37, count 0 2006.190.08:12:32.02#ibcon#about to read 6, iclass 37, count 0 2006.190.08:12:32.02#ibcon#read 6, iclass 37, count 0 2006.190.08:12:32.02#ibcon#end of sib2, iclass 37, count 0 2006.190.08:12:32.02#ibcon#*after write, iclass 37, count 0 2006.190.08:12:32.02#ibcon#*before return 0, iclass 37, count 0 2006.190.08:12:32.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:32.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:12:32.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.08:12:32.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.08:12:32.02$vc4f8/vb=5,4 2006.190.08:12:32.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.08:12:32.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.08:12:32.02#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:32.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:32.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:32.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:32.08#ibcon#enter wrdev, iclass 39, count 2 2006.190.08:12:32.08#ibcon#first serial, iclass 39, count 2 2006.190.08:12:32.08#ibcon#enter sib2, iclass 39, count 2 2006.190.08:12:32.08#ibcon#flushed, iclass 39, count 2 2006.190.08:12:32.08#ibcon#about to write, iclass 39, count 2 2006.190.08:12:32.08#ibcon#wrote, iclass 39, count 2 2006.190.08:12:32.08#ibcon#about to read 3, iclass 39, count 2 2006.190.08:12:32.11#ibcon#read 3, iclass 39, count 2 2006.190.08:12:32.11#ibcon#about to read 4, iclass 39, count 2 2006.190.08:12:32.11#ibcon#read 4, iclass 39, count 2 2006.190.08:12:32.11#ibcon#about to read 5, iclass 39, count 2 2006.190.08:12:32.11#ibcon#read 5, iclass 39, count 2 2006.190.08:12:32.11#ibcon#about to read 6, iclass 39, count 2 2006.190.08:12:32.11#ibcon#read 6, iclass 39, count 2 2006.190.08:12:32.11#ibcon#end of sib2, iclass 39, count 2 2006.190.08:12:32.11#ibcon#*mode == 0, iclass 39, count 2 2006.190.08:12:32.11#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.08:12:32.11#ibcon#[27=AT05-04\r\n] 2006.190.08:12:32.11#ibcon#*before write, iclass 39, count 2 2006.190.08:12:32.11#ibcon#enter sib2, iclass 39, count 2 2006.190.08:12:32.11#ibcon#flushed, iclass 39, count 2 2006.190.08:12:32.11#ibcon#about to write, iclass 39, count 2 2006.190.08:12:32.11#ibcon#wrote, iclass 39, count 2 2006.190.08:12:32.11#ibcon#about to read 3, iclass 39, count 2 2006.190.08:12:32.14#ibcon#read 3, iclass 39, count 2 2006.190.08:12:32.14#ibcon#about to read 4, iclass 39, count 2 2006.190.08:12:32.14#ibcon#read 4, iclass 39, count 2 2006.190.08:12:32.14#ibcon#about to read 5, iclass 39, count 2 2006.190.08:12:32.14#ibcon#read 5, iclass 39, count 2 2006.190.08:12:32.14#ibcon#about to read 6, iclass 39, count 2 2006.190.08:12:32.14#ibcon#read 6, iclass 39, count 2 2006.190.08:12:32.14#ibcon#end of sib2, iclass 39, count 2 2006.190.08:12:32.14#ibcon#*after write, iclass 39, count 2 2006.190.08:12:32.14#ibcon#*before return 0, iclass 39, count 2 2006.190.08:12:32.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:32.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:12:32.14#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.08:12:32.14#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:32.14#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:32.26#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:32.26#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:32.26#ibcon#enter wrdev, iclass 39, count 0 2006.190.08:12:32.26#ibcon#first serial, iclass 39, count 0 2006.190.08:12:32.26#ibcon#enter sib2, iclass 39, count 0 2006.190.08:12:32.26#ibcon#flushed, iclass 39, count 0 2006.190.08:12:32.26#ibcon#about to write, iclass 39, count 0 2006.190.08:12:32.26#ibcon#wrote, iclass 39, count 0 2006.190.08:12:32.26#ibcon#about to read 3, iclass 39, count 0 2006.190.08:12:32.28#ibcon#read 3, iclass 39, count 0 2006.190.08:12:32.28#ibcon#about to read 4, iclass 39, count 0 2006.190.08:12:32.28#ibcon#read 4, iclass 39, count 0 2006.190.08:12:32.28#ibcon#about to read 5, iclass 39, count 0 2006.190.08:12:32.28#ibcon#read 5, iclass 39, count 0 2006.190.08:12:32.28#ibcon#about to read 6, iclass 39, count 0 2006.190.08:12:32.28#ibcon#read 6, iclass 39, count 0 2006.190.08:12:32.28#ibcon#end of sib2, iclass 39, count 0 2006.190.08:12:32.28#ibcon#*mode == 0, iclass 39, count 0 2006.190.08:12:32.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.08:12:32.28#ibcon#[27=USB\r\n] 2006.190.08:12:32.28#ibcon#*before write, iclass 39, count 0 2006.190.08:12:32.28#ibcon#enter sib2, iclass 39, count 0 2006.190.08:12:32.28#ibcon#flushed, iclass 39, count 0 2006.190.08:12:32.28#ibcon#about to write, iclass 39, count 0 2006.190.08:12:32.28#ibcon#wrote, iclass 39, count 0 2006.190.08:12:32.28#ibcon#about to read 3, iclass 39, count 0 2006.190.08:12:32.31#ibcon#read 3, iclass 39, count 0 2006.190.08:12:32.31#ibcon#about to read 4, iclass 39, count 0 2006.190.08:12:32.31#ibcon#read 4, iclass 39, count 0 2006.190.08:12:32.31#ibcon#about to read 5, iclass 39, count 0 2006.190.08:12:32.31#ibcon#read 5, iclass 39, count 0 2006.190.08:12:32.31#ibcon#about to read 6, iclass 39, count 0 2006.190.08:12:32.31#ibcon#read 6, iclass 39, count 0 2006.190.08:12:32.31#ibcon#end of sib2, iclass 39, count 0 2006.190.08:12:32.31#ibcon#*after write, iclass 39, count 0 2006.190.08:12:32.31#ibcon#*before return 0, iclass 39, count 0 2006.190.08:12:32.31#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:32.31#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:12:32.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.08:12:32.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.08:12:32.31$vc4f8/vblo=6,752.99 2006.190.08:12:32.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.08:12:32.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.08:12:32.31#ibcon#ireg 17 cls_cnt 0 2006.190.08:12:32.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:32.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:32.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:32.31#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:12:32.31#ibcon#first serial, iclass 3, count 0 2006.190.08:12:32.31#ibcon#enter sib2, iclass 3, count 0 2006.190.08:12:32.31#ibcon#flushed, iclass 3, count 0 2006.190.08:12:32.31#ibcon#about to write, iclass 3, count 0 2006.190.08:12:32.31#ibcon#wrote, iclass 3, count 0 2006.190.08:12:32.31#ibcon#about to read 3, iclass 3, count 0 2006.190.08:12:32.33#ibcon#read 3, iclass 3, count 0 2006.190.08:12:32.33#ibcon#about to read 4, iclass 3, count 0 2006.190.08:12:32.33#ibcon#read 4, iclass 3, count 0 2006.190.08:12:32.33#ibcon#about to read 5, iclass 3, count 0 2006.190.08:12:32.33#ibcon#read 5, iclass 3, count 0 2006.190.08:12:32.33#ibcon#about to read 6, iclass 3, count 0 2006.190.08:12:32.33#ibcon#read 6, iclass 3, count 0 2006.190.08:12:32.33#ibcon#end of sib2, iclass 3, count 0 2006.190.08:12:32.33#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:12:32.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:12:32.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:12:32.33#ibcon#*before write, iclass 3, count 0 2006.190.08:12:32.33#ibcon#enter sib2, iclass 3, count 0 2006.190.08:12:32.33#ibcon#flushed, iclass 3, count 0 2006.190.08:12:32.33#ibcon#about to write, iclass 3, count 0 2006.190.08:12:32.33#ibcon#wrote, iclass 3, count 0 2006.190.08:12:32.33#ibcon#about to read 3, iclass 3, count 0 2006.190.08:12:32.37#ibcon#read 3, iclass 3, count 0 2006.190.08:12:32.37#ibcon#about to read 4, iclass 3, count 0 2006.190.08:12:32.37#ibcon#read 4, iclass 3, count 0 2006.190.08:12:32.37#ibcon#about to read 5, iclass 3, count 0 2006.190.08:12:32.37#ibcon#read 5, iclass 3, count 0 2006.190.08:12:32.37#ibcon#about to read 6, iclass 3, count 0 2006.190.08:12:32.37#ibcon#read 6, iclass 3, count 0 2006.190.08:12:32.37#ibcon#end of sib2, iclass 3, count 0 2006.190.08:12:32.37#ibcon#*after write, iclass 3, count 0 2006.190.08:12:32.37#ibcon#*before return 0, iclass 3, count 0 2006.190.08:12:32.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:32.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:12:32.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:12:32.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:12:32.37$vc4f8/vb=6,4 2006.190.08:12:32.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.08:12:32.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.08:12:32.37#ibcon#ireg 11 cls_cnt 2 2006.190.08:12:32.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:32.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:32.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:32.43#ibcon#enter wrdev, iclass 5, count 2 2006.190.08:12:32.43#ibcon#first serial, iclass 5, count 2 2006.190.08:12:32.43#ibcon#enter sib2, iclass 5, count 2 2006.190.08:12:32.43#ibcon#flushed, iclass 5, count 2 2006.190.08:12:32.43#ibcon#about to write, iclass 5, count 2 2006.190.08:12:32.43#ibcon#wrote, iclass 5, count 2 2006.190.08:12:32.43#ibcon#about to read 3, iclass 5, count 2 2006.190.08:12:32.45#ibcon#read 3, iclass 5, count 2 2006.190.08:12:32.45#ibcon#about to read 4, iclass 5, count 2 2006.190.08:12:32.45#ibcon#read 4, iclass 5, count 2 2006.190.08:12:32.45#ibcon#about to read 5, iclass 5, count 2 2006.190.08:12:32.45#ibcon#read 5, iclass 5, count 2 2006.190.08:12:32.45#ibcon#about to read 6, iclass 5, count 2 2006.190.08:12:32.45#ibcon#read 6, iclass 5, count 2 2006.190.08:12:32.45#ibcon#end of sib2, iclass 5, count 2 2006.190.08:12:32.45#ibcon#*mode == 0, iclass 5, count 2 2006.190.08:12:32.45#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.08:12:32.45#ibcon#[27=AT06-04\r\n] 2006.190.08:12:32.45#ibcon#*before write, iclass 5, count 2 2006.190.08:12:32.45#ibcon#enter sib2, iclass 5, count 2 2006.190.08:12:32.45#ibcon#flushed, iclass 5, count 2 2006.190.08:12:32.45#ibcon#about to write, iclass 5, count 2 2006.190.08:12:32.45#ibcon#wrote, iclass 5, count 2 2006.190.08:12:32.45#ibcon#about to read 3, iclass 5, count 2 2006.190.08:12:32.48#ibcon#read 3, iclass 5, count 2 2006.190.08:12:32.48#ibcon#about to read 4, iclass 5, count 2 2006.190.08:12:32.48#ibcon#read 4, iclass 5, count 2 2006.190.08:12:32.48#ibcon#about to read 5, iclass 5, count 2 2006.190.08:12:32.48#ibcon#read 5, iclass 5, count 2 2006.190.08:12:32.48#ibcon#about to read 6, iclass 5, count 2 2006.190.08:12:32.48#ibcon#read 6, iclass 5, count 2 2006.190.08:12:32.48#ibcon#end of sib2, iclass 5, count 2 2006.190.08:12:32.48#ibcon#*after write, iclass 5, count 2 2006.190.08:12:32.48#ibcon#*before return 0, iclass 5, count 2 2006.190.08:12:32.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:32.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:12:32.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.08:12:32.48#ibcon#ireg 7 cls_cnt 0 2006.190.08:12:32.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:32.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:32.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:32.60#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:12:32.60#ibcon#first serial, iclass 5, count 0 2006.190.08:12:32.60#ibcon#enter sib2, iclass 5, count 0 2006.190.08:12:32.60#ibcon#flushed, iclass 5, count 0 2006.190.08:12:32.60#ibcon#about to write, iclass 5, count 0 2006.190.08:12:32.60#ibcon#wrote, iclass 5, count 0 2006.190.08:12:32.60#ibcon#about to read 3, iclass 5, count 0 2006.190.08:12:32.62#ibcon#read 3, iclass 5, count 0 2006.190.08:12:32.62#ibcon#about to read 4, iclass 5, count 0 2006.190.08:12:32.62#ibcon#read 4, iclass 5, count 0 2006.190.08:12:32.62#ibcon#about to read 5, iclass 5, count 0 2006.190.08:12:32.62#ibcon#read 5, iclass 5, count 0 2006.190.08:12:32.62#ibcon#about to read 6, iclass 5, count 0 2006.190.08:12:32.62#ibcon#read 6, iclass 5, count 0 2006.190.08:12:32.62#ibcon#end of sib2, iclass 5, count 0 2006.190.08:12:32.62#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:12:32.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:12:32.62#ibcon#[27=USB\r\n] 2006.190.08:12:32.62#ibcon#*before write, iclass 5, count 0 2006.190.08:12:32.62#ibcon#enter sib2, iclass 5, count 0 2006.190.08:12:32.62#ibcon#flushed, iclass 5, count 0 2006.190.08:12:32.62#ibcon#about to write, iclass 5, count 0 2006.190.08:12:32.62#ibcon#wrote, iclass 5, count 0 2006.190.08:12:32.62#ibcon#about to read 3, iclass 5, count 0 2006.190.08:12:32.65#ibcon#read 3, iclass 5, count 0 2006.190.08:12:32.65#ibcon#about to read 4, iclass 5, count 0 2006.190.08:12:32.65#ibcon#read 4, iclass 5, count 0 2006.190.08:12:32.65#ibcon#about to read 5, iclass 5, count 0 2006.190.08:12:32.65#ibcon#read 5, iclass 5, count 0 2006.190.08:12:32.65#ibcon#about to read 6, iclass 5, count 0 2006.190.08:12:32.65#ibcon#read 6, iclass 5, count 0 2006.190.08:12:32.65#ibcon#end of sib2, iclass 5, count 0 2006.190.08:12:32.65#ibcon#*after write, iclass 5, count 0 2006.190.08:12:32.65#ibcon#*before return 0, iclass 5, count 0 2006.190.08:12:32.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:32.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:12:32.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:12:32.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:12:32.65$vc4f8/vabw=wide 2006.190.08:12:32.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.08:12:32.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.08:12:32.65#ibcon#ireg 8 cls_cnt 0 2006.190.08:12:32.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:32.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:32.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:32.65#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:12:32.65#ibcon#first serial, iclass 7, count 0 2006.190.08:12:32.65#ibcon#enter sib2, iclass 7, count 0 2006.190.08:12:32.65#ibcon#flushed, iclass 7, count 0 2006.190.08:12:32.65#ibcon#about to write, iclass 7, count 0 2006.190.08:12:32.65#ibcon#wrote, iclass 7, count 0 2006.190.08:12:32.65#ibcon#about to read 3, iclass 7, count 0 2006.190.08:12:32.67#ibcon#read 3, iclass 7, count 0 2006.190.08:12:32.67#ibcon#about to read 4, iclass 7, count 0 2006.190.08:12:32.67#ibcon#read 4, iclass 7, count 0 2006.190.08:12:32.67#ibcon#about to read 5, iclass 7, count 0 2006.190.08:12:32.67#ibcon#read 5, iclass 7, count 0 2006.190.08:12:32.67#ibcon#about to read 6, iclass 7, count 0 2006.190.08:12:32.67#ibcon#read 6, iclass 7, count 0 2006.190.08:12:32.67#ibcon#end of sib2, iclass 7, count 0 2006.190.08:12:32.67#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:12:32.67#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:12:32.67#ibcon#[25=BW32\r\n] 2006.190.08:12:32.67#ibcon#*before write, iclass 7, count 0 2006.190.08:12:32.67#ibcon#enter sib2, iclass 7, count 0 2006.190.08:12:32.67#ibcon#flushed, iclass 7, count 0 2006.190.08:12:32.67#ibcon#about to write, iclass 7, count 0 2006.190.08:12:32.67#ibcon#wrote, iclass 7, count 0 2006.190.08:12:32.67#ibcon#about to read 3, iclass 7, count 0 2006.190.08:12:32.70#ibcon#read 3, iclass 7, count 0 2006.190.08:12:32.70#ibcon#about to read 4, iclass 7, count 0 2006.190.08:12:32.70#ibcon#read 4, iclass 7, count 0 2006.190.08:12:32.70#ibcon#about to read 5, iclass 7, count 0 2006.190.08:12:32.70#ibcon#read 5, iclass 7, count 0 2006.190.08:12:32.70#ibcon#about to read 6, iclass 7, count 0 2006.190.08:12:32.70#ibcon#read 6, iclass 7, count 0 2006.190.08:12:32.70#ibcon#end of sib2, iclass 7, count 0 2006.190.08:12:32.70#ibcon#*after write, iclass 7, count 0 2006.190.08:12:32.70#ibcon#*before return 0, iclass 7, count 0 2006.190.08:12:32.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:32.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:12:32.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:12:32.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:12:32.70$vc4f8/vbbw=wide 2006.190.08:12:32.70#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.08:12:32.70#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.08:12:32.70#ibcon#ireg 8 cls_cnt 0 2006.190.08:12:32.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:12:32.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:12:32.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:12:32.77#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:12:32.77#ibcon#first serial, iclass 11, count 0 2006.190.08:12:32.77#ibcon#enter sib2, iclass 11, count 0 2006.190.08:12:32.77#ibcon#flushed, iclass 11, count 0 2006.190.08:12:32.77#ibcon#about to write, iclass 11, count 0 2006.190.08:12:32.77#ibcon#wrote, iclass 11, count 0 2006.190.08:12:32.77#ibcon#about to read 3, iclass 11, count 0 2006.190.08:12:32.79#ibcon#read 3, iclass 11, count 0 2006.190.08:12:32.79#ibcon#about to read 4, iclass 11, count 0 2006.190.08:12:32.79#ibcon#read 4, iclass 11, count 0 2006.190.08:12:32.79#ibcon#about to read 5, iclass 11, count 0 2006.190.08:12:32.79#ibcon#read 5, iclass 11, count 0 2006.190.08:12:32.79#ibcon#about to read 6, iclass 11, count 0 2006.190.08:12:32.79#ibcon#read 6, iclass 11, count 0 2006.190.08:12:32.79#ibcon#end of sib2, iclass 11, count 0 2006.190.08:12:32.79#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:12:32.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:12:32.79#ibcon#[27=BW32\r\n] 2006.190.08:12:32.79#ibcon#*before write, iclass 11, count 0 2006.190.08:12:32.79#ibcon#enter sib2, iclass 11, count 0 2006.190.08:12:32.79#ibcon#flushed, iclass 11, count 0 2006.190.08:12:32.79#ibcon#about to write, iclass 11, count 0 2006.190.08:12:32.79#ibcon#wrote, iclass 11, count 0 2006.190.08:12:32.79#ibcon#about to read 3, iclass 11, count 0 2006.190.08:12:32.82#ibcon#read 3, iclass 11, count 0 2006.190.08:12:32.82#ibcon#about to read 4, iclass 11, count 0 2006.190.08:12:32.82#ibcon#read 4, iclass 11, count 0 2006.190.08:12:32.82#ibcon#about to read 5, iclass 11, count 0 2006.190.08:12:32.82#ibcon#read 5, iclass 11, count 0 2006.190.08:12:32.82#ibcon#about to read 6, iclass 11, count 0 2006.190.08:12:32.82#ibcon#read 6, iclass 11, count 0 2006.190.08:12:32.82#ibcon#end of sib2, iclass 11, count 0 2006.190.08:12:32.82#ibcon#*after write, iclass 11, count 0 2006.190.08:12:32.82#ibcon#*before return 0, iclass 11, count 0 2006.190.08:12:32.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:12:32.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:12:32.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:12:32.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:12:32.82$4f8m12a/ifd4f 2006.190.08:12:32.82$ifd4f/lo= 2006.190.08:12:32.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:12:32.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:12:32.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:12:32.82$ifd4f/patch= 2006.190.08:12:32.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:12:32.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:12:32.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:12:32.82$4f8m12a/"form=m,16.000,1:2 2006.190.08:12:32.82$4f8m12a/"tpicd 2006.190.08:12:32.82$4f8m12a/echo=off 2006.190.08:12:32.82$4f8m12a/xlog=off 2006.190.08:12:32.82:!2006.190.08:13:00 2006.190.08:12:43.13#trakl#Source acquired 2006.190.08:12:45.13#flagr#flagr/antenna,acquired 2006.190.08:13:00.00:preob 2006.190.08:13:01.13/onsource/TRACKING 2006.190.08:13:01.13:!2006.190.08:13:10 2006.190.08:13:10.00:data_valid=on 2006.190.08:13:10.00:midob 2006.190.08:13:10.14/onsource/TRACKING 2006.190.08:13:10.14/wx/24.40,1012.1,100 2006.190.08:13:10.25/cable/+6.4705E-03 2006.190.08:13:11.34/va/01,08,usb,yes,36,38 2006.190.08:13:11.34/va/02,07,usb,yes,37,38 2006.190.08:13:11.34/va/03,06,usb,yes,39,39 2006.190.08:13:11.34/va/04,07,usb,yes,38,41 2006.190.08:13:11.34/va/05,07,usb,yes,42,44 2006.190.08:13:11.34/va/06,06,usb,yes,41,41 2006.190.08:13:11.34/va/07,06,usb,yes,42,41 2006.190.08:13:11.34/va/08,06,usb,yes,44,44 2006.190.08:13:11.57/valo/01,532.99,yes,locked 2006.190.08:13:11.57/valo/02,572.99,yes,locked 2006.190.08:13:11.57/valo/03,672.99,yes,locked 2006.190.08:13:11.57/valo/04,832.99,yes,locked 2006.190.08:13:11.57/valo/05,652.99,yes,locked 2006.190.08:13:11.57/valo/06,772.99,yes,locked 2006.190.08:13:11.57/valo/07,832.99,yes,locked 2006.190.08:13:11.57/valo/08,852.99,yes,locked 2006.190.08:13:12.66/vb/01,04,usb,yes,32,30 2006.190.08:13:12.66/vb/02,04,usb,yes,34,35 2006.190.08:13:12.66/vb/03,04,usb,yes,30,34 2006.190.08:13:12.66/vb/04,04,usb,yes,31,31 2006.190.08:13:12.66/vb/05,04,usb,yes,29,34 2006.190.08:13:12.66/vb/06,04,usb,yes,30,33 2006.190.08:13:12.66/vb/07,04,usb,yes,33,34 2006.190.08:13:12.66/vb/08,04,usb,yes,30,34 2006.190.08:13:12.90/vblo/01,632.99,yes,locked 2006.190.08:13:12.90/vblo/02,640.99,yes,locked 2006.190.08:13:12.90/vblo/03,656.99,yes,locked 2006.190.08:13:12.90/vblo/04,712.99,yes,locked 2006.190.08:13:12.90/vblo/05,744.99,yes,locked 2006.190.08:13:12.90/vblo/06,752.99,yes,locked 2006.190.08:13:12.90/vblo/07,734.99,yes,locked 2006.190.08:13:12.90/vblo/08,744.99,yes,locked 2006.190.08:13:13.05/vabw/8 2006.190.08:13:13.20/vbbw/8 2006.190.08:13:13.30/xfe/off,on,14.7 2006.190.08:13:13.67/ifatt/23,28,28,28 2006.190.08:13:14.07/fmout-gps/S +2.86E-07 2006.190.08:13:14.15:!2006.190.08:14:10 2006.190.08:14:10.01:data_valid=off 2006.190.08:14:10.02:postob 2006.190.08:14:10.12/cable/+6.4687E-03 2006.190.08:14:10.12/wx/24.40,1012.1,100 2006.190.08:14:11.07/fmout-gps/S +2.85E-07 2006.190.08:14:11.07:scan_name=190-0815,k06190,60 2006.190.08:14:11.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.190.08:14:11.14#flagr#flagr/antenna,new-source 2006.190.08:14:12.14:checkk5 2006.190.08:14:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:14:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:14:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:14:13.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:14:14.04/chk_obsdata//k5ts1/T1900813??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:14:14.43/chk_obsdata//k5ts2/T1900813??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:14:14.80/chk_obsdata//k5ts3/T1900813??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:14:15.18/chk_obsdata//k5ts4/T1900813??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:14:15.88/k5log//k5ts1_log_newline 2006.190.08:14:16.59/k5log//k5ts2_log_newline 2006.190.08:14:17.28/k5log//k5ts3_log_newline 2006.190.08:14:17.98/k5log//k5ts4_log_newline 2006.190.08:14:18.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:14:18.01:4f8m12a=2 2006.190.08:14:18.01$4f8m12a/echo=on 2006.190.08:14:18.01$4f8m12a/pcalon 2006.190.08:14:18.01$pcalon/"no phase cal control is implemented here 2006.190.08:14:18.01$4f8m12a/"tpicd=stop 2006.190.08:14:18.01$4f8m12a/vc4f8 2006.190.08:14:18.01$vc4f8/valo=1,532.99 2006.190.08:14:18.01#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.08:14:18.01#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.08:14:18.01#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:18.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:18.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:18.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:18.01#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:14:18.01#ibcon#first serial, iclass 22, count 0 2006.190.08:14:18.01#ibcon#enter sib2, iclass 22, count 0 2006.190.08:14:18.01#ibcon#flushed, iclass 22, count 0 2006.190.08:14:18.01#ibcon#about to write, iclass 22, count 0 2006.190.08:14:18.01#ibcon#wrote, iclass 22, count 0 2006.190.08:14:18.01#ibcon#about to read 3, iclass 22, count 0 2006.190.08:14:18.06#ibcon#read 3, iclass 22, count 0 2006.190.08:14:18.06#ibcon#about to read 4, iclass 22, count 0 2006.190.08:14:18.06#ibcon#read 4, iclass 22, count 0 2006.190.08:14:18.06#ibcon#about to read 5, iclass 22, count 0 2006.190.08:14:18.06#ibcon#read 5, iclass 22, count 0 2006.190.08:14:18.06#ibcon#about to read 6, iclass 22, count 0 2006.190.08:14:18.06#ibcon#read 6, iclass 22, count 0 2006.190.08:14:18.06#ibcon#end of sib2, iclass 22, count 0 2006.190.08:14:18.06#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:14:18.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:14:18.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:14:18.06#ibcon#*before write, iclass 22, count 0 2006.190.08:14:18.06#ibcon#enter sib2, iclass 22, count 0 2006.190.08:14:18.06#ibcon#flushed, iclass 22, count 0 2006.190.08:14:18.06#ibcon#about to write, iclass 22, count 0 2006.190.08:14:18.06#ibcon#wrote, iclass 22, count 0 2006.190.08:14:18.06#ibcon#about to read 3, iclass 22, count 0 2006.190.08:14:18.11#ibcon#read 3, iclass 22, count 0 2006.190.08:14:18.11#ibcon#about to read 4, iclass 22, count 0 2006.190.08:14:18.11#ibcon#read 4, iclass 22, count 0 2006.190.08:14:18.11#ibcon#about to read 5, iclass 22, count 0 2006.190.08:14:18.11#ibcon#read 5, iclass 22, count 0 2006.190.08:14:18.11#ibcon#about to read 6, iclass 22, count 0 2006.190.08:14:18.11#ibcon#read 6, iclass 22, count 0 2006.190.08:14:18.11#ibcon#end of sib2, iclass 22, count 0 2006.190.08:14:18.11#ibcon#*after write, iclass 22, count 0 2006.190.08:14:18.11#ibcon#*before return 0, iclass 22, count 0 2006.190.08:14:18.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:18.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:18.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:14:18.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:14:18.11$vc4f8/va=1,8 2006.190.08:14:18.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.08:14:18.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.08:14:18.11#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:18.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:18.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:18.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:18.11#ibcon#enter wrdev, iclass 24, count 2 2006.190.08:14:18.11#ibcon#first serial, iclass 24, count 2 2006.190.08:14:18.11#ibcon#enter sib2, iclass 24, count 2 2006.190.08:14:18.11#ibcon#flushed, iclass 24, count 2 2006.190.08:14:18.11#ibcon#about to write, iclass 24, count 2 2006.190.08:14:18.11#ibcon#wrote, iclass 24, count 2 2006.190.08:14:18.11#ibcon#about to read 3, iclass 24, count 2 2006.190.08:14:18.13#ibcon#read 3, iclass 24, count 2 2006.190.08:14:18.13#ibcon#about to read 4, iclass 24, count 2 2006.190.08:14:18.13#ibcon#read 4, iclass 24, count 2 2006.190.08:14:18.13#ibcon#about to read 5, iclass 24, count 2 2006.190.08:14:18.13#ibcon#read 5, iclass 24, count 2 2006.190.08:14:18.13#ibcon#about to read 6, iclass 24, count 2 2006.190.08:14:18.13#ibcon#read 6, iclass 24, count 2 2006.190.08:14:18.13#ibcon#end of sib2, iclass 24, count 2 2006.190.08:14:18.13#ibcon#*mode == 0, iclass 24, count 2 2006.190.08:14:18.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.08:14:18.13#ibcon#[25=AT01-08\r\n] 2006.190.08:14:18.13#ibcon#*before write, iclass 24, count 2 2006.190.08:14:18.13#ibcon#enter sib2, iclass 24, count 2 2006.190.08:14:18.13#ibcon#flushed, iclass 24, count 2 2006.190.08:14:18.13#ibcon#about to write, iclass 24, count 2 2006.190.08:14:18.13#ibcon#wrote, iclass 24, count 2 2006.190.08:14:18.13#ibcon#about to read 3, iclass 24, count 2 2006.190.08:14:18.16#ibcon#read 3, iclass 24, count 2 2006.190.08:14:18.16#ibcon#about to read 4, iclass 24, count 2 2006.190.08:14:18.16#ibcon#read 4, iclass 24, count 2 2006.190.08:14:18.16#ibcon#about to read 5, iclass 24, count 2 2006.190.08:14:18.16#ibcon#read 5, iclass 24, count 2 2006.190.08:14:18.16#ibcon#about to read 6, iclass 24, count 2 2006.190.08:14:18.16#ibcon#read 6, iclass 24, count 2 2006.190.08:14:18.16#ibcon#end of sib2, iclass 24, count 2 2006.190.08:14:18.16#ibcon#*after write, iclass 24, count 2 2006.190.08:14:18.16#ibcon#*before return 0, iclass 24, count 2 2006.190.08:14:18.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:18.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:18.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.08:14:18.16#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:18.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:18.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:18.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:18.28#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:14:18.28#ibcon#first serial, iclass 24, count 0 2006.190.08:14:18.28#ibcon#enter sib2, iclass 24, count 0 2006.190.08:14:18.28#ibcon#flushed, iclass 24, count 0 2006.190.08:14:18.28#ibcon#about to write, iclass 24, count 0 2006.190.08:14:18.28#ibcon#wrote, iclass 24, count 0 2006.190.08:14:18.28#ibcon#about to read 3, iclass 24, count 0 2006.190.08:14:18.30#ibcon#read 3, iclass 24, count 0 2006.190.08:14:18.30#ibcon#about to read 4, iclass 24, count 0 2006.190.08:14:18.30#ibcon#read 4, iclass 24, count 0 2006.190.08:14:18.30#ibcon#about to read 5, iclass 24, count 0 2006.190.08:14:18.30#ibcon#read 5, iclass 24, count 0 2006.190.08:14:18.30#ibcon#about to read 6, iclass 24, count 0 2006.190.08:14:18.30#ibcon#read 6, iclass 24, count 0 2006.190.08:14:18.30#ibcon#end of sib2, iclass 24, count 0 2006.190.08:14:18.30#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:14:18.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:14:18.30#ibcon#[25=USB\r\n] 2006.190.08:14:18.30#ibcon#*before write, iclass 24, count 0 2006.190.08:14:18.30#ibcon#enter sib2, iclass 24, count 0 2006.190.08:14:18.30#ibcon#flushed, iclass 24, count 0 2006.190.08:14:18.30#ibcon#about to write, iclass 24, count 0 2006.190.08:14:18.30#ibcon#wrote, iclass 24, count 0 2006.190.08:14:18.30#ibcon#about to read 3, iclass 24, count 0 2006.190.08:14:18.33#ibcon#read 3, iclass 24, count 0 2006.190.08:14:18.33#ibcon#about to read 4, iclass 24, count 0 2006.190.08:14:18.33#ibcon#read 4, iclass 24, count 0 2006.190.08:14:18.33#ibcon#about to read 5, iclass 24, count 0 2006.190.08:14:18.33#ibcon#read 5, iclass 24, count 0 2006.190.08:14:18.33#ibcon#about to read 6, iclass 24, count 0 2006.190.08:14:18.33#ibcon#read 6, iclass 24, count 0 2006.190.08:14:18.33#ibcon#end of sib2, iclass 24, count 0 2006.190.08:14:18.33#ibcon#*after write, iclass 24, count 0 2006.190.08:14:18.33#ibcon#*before return 0, iclass 24, count 0 2006.190.08:14:18.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:18.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:18.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:14:18.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:14:18.33$vc4f8/valo=2,572.99 2006.190.08:14:18.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.08:14:18.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.08:14:18.33#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:18.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:18.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:18.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:18.33#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:14:18.33#ibcon#first serial, iclass 26, count 0 2006.190.08:14:18.33#ibcon#enter sib2, iclass 26, count 0 2006.190.08:14:18.33#ibcon#flushed, iclass 26, count 0 2006.190.08:14:18.33#ibcon#about to write, iclass 26, count 0 2006.190.08:14:18.33#ibcon#wrote, iclass 26, count 0 2006.190.08:14:18.33#ibcon#about to read 3, iclass 26, count 0 2006.190.08:14:18.35#ibcon#read 3, iclass 26, count 0 2006.190.08:14:18.35#ibcon#about to read 4, iclass 26, count 0 2006.190.08:14:18.35#ibcon#read 4, iclass 26, count 0 2006.190.08:14:18.35#ibcon#about to read 5, iclass 26, count 0 2006.190.08:14:18.35#ibcon#read 5, iclass 26, count 0 2006.190.08:14:18.35#ibcon#about to read 6, iclass 26, count 0 2006.190.08:14:18.35#ibcon#read 6, iclass 26, count 0 2006.190.08:14:18.35#ibcon#end of sib2, iclass 26, count 0 2006.190.08:14:18.35#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:14:18.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:14:18.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:14:18.35#ibcon#*before write, iclass 26, count 0 2006.190.08:14:18.35#ibcon#enter sib2, iclass 26, count 0 2006.190.08:14:18.35#ibcon#flushed, iclass 26, count 0 2006.190.08:14:18.35#ibcon#about to write, iclass 26, count 0 2006.190.08:14:18.35#ibcon#wrote, iclass 26, count 0 2006.190.08:14:18.35#ibcon#about to read 3, iclass 26, count 0 2006.190.08:14:18.39#ibcon#read 3, iclass 26, count 0 2006.190.08:14:18.39#ibcon#about to read 4, iclass 26, count 0 2006.190.08:14:18.39#ibcon#read 4, iclass 26, count 0 2006.190.08:14:18.39#ibcon#about to read 5, iclass 26, count 0 2006.190.08:14:18.39#ibcon#read 5, iclass 26, count 0 2006.190.08:14:18.39#ibcon#about to read 6, iclass 26, count 0 2006.190.08:14:18.39#ibcon#read 6, iclass 26, count 0 2006.190.08:14:18.39#ibcon#end of sib2, iclass 26, count 0 2006.190.08:14:18.39#ibcon#*after write, iclass 26, count 0 2006.190.08:14:18.39#ibcon#*before return 0, iclass 26, count 0 2006.190.08:14:18.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:18.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:18.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:14:18.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:14:18.39$vc4f8/va=2,7 2006.190.08:14:18.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.08:14:18.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.08:14:18.39#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:18.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:18.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:18.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:18.45#ibcon#enter wrdev, iclass 28, count 2 2006.190.08:14:18.45#ibcon#first serial, iclass 28, count 2 2006.190.08:14:18.45#ibcon#enter sib2, iclass 28, count 2 2006.190.08:14:18.45#ibcon#flushed, iclass 28, count 2 2006.190.08:14:18.45#ibcon#about to write, iclass 28, count 2 2006.190.08:14:18.45#ibcon#wrote, iclass 28, count 2 2006.190.08:14:18.45#ibcon#about to read 3, iclass 28, count 2 2006.190.08:14:18.47#ibcon#read 3, iclass 28, count 2 2006.190.08:14:18.47#ibcon#about to read 4, iclass 28, count 2 2006.190.08:14:18.47#ibcon#read 4, iclass 28, count 2 2006.190.08:14:18.47#ibcon#about to read 5, iclass 28, count 2 2006.190.08:14:18.47#ibcon#read 5, iclass 28, count 2 2006.190.08:14:18.47#ibcon#about to read 6, iclass 28, count 2 2006.190.08:14:18.47#ibcon#read 6, iclass 28, count 2 2006.190.08:14:18.47#ibcon#end of sib2, iclass 28, count 2 2006.190.08:14:18.47#ibcon#*mode == 0, iclass 28, count 2 2006.190.08:14:18.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.08:14:18.47#ibcon#[25=AT02-07\r\n] 2006.190.08:14:18.47#ibcon#*before write, iclass 28, count 2 2006.190.08:14:18.47#ibcon#enter sib2, iclass 28, count 2 2006.190.08:14:18.47#ibcon#flushed, iclass 28, count 2 2006.190.08:14:18.47#ibcon#about to write, iclass 28, count 2 2006.190.08:14:18.47#ibcon#wrote, iclass 28, count 2 2006.190.08:14:18.47#ibcon#about to read 3, iclass 28, count 2 2006.190.08:14:18.50#ibcon#read 3, iclass 28, count 2 2006.190.08:14:18.50#ibcon#about to read 4, iclass 28, count 2 2006.190.08:14:18.50#ibcon#read 4, iclass 28, count 2 2006.190.08:14:18.50#ibcon#about to read 5, iclass 28, count 2 2006.190.08:14:18.50#ibcon#read 5, iclass 28, count 2 2006.190.08:14:18.50#ibcon#about to read 6, iclass 28, count 2 2006.190.08:14:18.50#ibcon#read 6, iclass 28, count 2 2006.190.08:14:18.50#ibcon#end of sib2, iclass 28, count 2 2006.190.08:14:18.50#ibcon#*after write, iclass 28, count 2 2006.190.08:14:18.50#ibcon#*before return 0, iclass 28, count 2 2006.190.08:14:18.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:18.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:18.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.08:14:18.50#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:18.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:18.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:18.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:18.62#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:14:18.62#ibcon#first serial, iclass 28, count 0 2006.190.08:14:18.62#ibcon#enter sib2, iclass 28, count 0 2006.190.08:14:18.62#ibcon#flushed, iclass 28, count 0 2006.190.08:14:18.62#ibcon#about to write, iclass 28, count 0 2006.190.08:14:18.62#ibcon#wrote, iclass 28, count 0 2006.190.08:14:18.62#ibcon#about to read 3, iclass 28, count 0 2006.190.08:14:18.64#ibcon#read 3, iclass 28, count 0 2006.190.08:14:18.64#ibcon#about to read 4, iclass 28, count 0 2006.190.08:14:18.64#ibcon#read 4, iclass 28, count 0 2006.190.08:14:18.64#ibcon#about to read 5, iclass 28, count 0 2006.190.08:14:18.64#ibcon#read 5, iclass 28, count 0 2006.190.08:14:18.64#ibcon#about to read 6, iclass 28, count 0 2006.190.08:14:18.64#ibcon#read 6, iclass 28, count 0 2006.190.08:14:18.64#ibcon#end of sib2, iclass 28, count 0 2006.190.08:14:18.64#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:14:18.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:14:18.64#ibcon#[25=USB\r\n] 2006.190.08:14:18.64#ibcon#*before write, iclass 28, count 0 2006.190.08:14:18.64#ibcon#enter sib2, iclass 28, count 0 2006.190.08:14:18.64#ibcon#flushed, iclass 28, count 0 2006.190.08:14:18.64#ibcon#about to write, iclass 28, count 0 2006.190.08:14:18.64#ibcon#wrote, iclass 28, count 0 2006.190.08:14:18.64#ibcon#about to read 3, iclass 28, count 0 2006.190.08:14:18.67#ibcon#read 3, iclass 28, count 0 2006.190.08:14:18.67#ibcon#about to read 4, iclass 28, count 0 2006.190.08:14:18.67#ibcon#read 4, iclass 28, count 0 2006.190.08:14:18.67#ibcon#about to read 5, iclass 28, count 0 2006.190.08:14:18.67#ibcon#read 5, iclass 28, count 0 2006.190.08:14:18.67#ibcon#about to read 6, iclass 28, count 0 2006.190.08:14:18.67#ibcon#read 6, iclass 28, count 0 2006.190.08:14:18.67#ibcon#end of sib2, iclass 28, count 0 2006.190.08:14:18.67#ibcon#*after write, iclass 28, count 0 2006.190.08:14:18.67#ibcon#*before return 0, iclass 28, count 0 2006.190.08:14:18.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:18.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:18.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:14:18.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:14:18.67$vc4f8/valo=3,672.99 2006.190.08:14:18.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.08:14:18.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.08:14:18.67#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:18.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:18.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:18.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:18.67#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:14:18.67#ibcon#first serial, iclass 30, count 0 2006.190.08:14:18.67#ibcon#enter sib2, iclass 30, count 0 2006.190.08:14:18.67#ibcon#flushed, iclass 30, count 0 2006.190.08:14:18.67#ibcon#about to write, iclass 30, count 0 2006.190.08:14:18.67#ibcon#wrote, iclass 30, count 0 2006.190.08:14:18.67#ibcon#about to read 3, iclass 30, count 0 2006.190.08:14:18.69#ibcon#read 3, iclass 30, count 0 2006.190.08:14:18.69#ibcon#about to read 4, iclass 30, count 0 2006.190.08:14:18.69#ibcon#read 4, iclass 30, count 0 2006.190.08:14:18.69#ibcon#about to read 5, iclass 30, count 0 2006.190.08:14:18.69#ibcon#read 5, iclass 30, count 0 2006.190.08:14:18.69#ibcon#about to read 6, iclass 30, count 0 2006.190.08:14:18.69#ibcon#read 6, iclass 30, count 0 2006.190.08:14:18.69#ibcon#end of sib2, iclass 30, count 0 2006.190.08:14:18.69#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:14:18.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:14:18.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:14:18.69#ibcon#*before write, iclass 30, count 0 2006.190.08:14:18.69#ibcon#enter sib2, iclass 30, count 0 2006.190.08:14:18.69#ibcon#flushed, iclass 30, count 0 2006.190.08:14:18.69#ibcon#about to write, iclass 30, count 0 2006.190.08:14:18.69#ibcon#wrote, iclass 30, count 0 2006.190.08:14:18.69#ibcon#about to read 3, iclass 30, count 0 2006.190.08:14:18.73#ibcon#read 3, iclass 30, count 0 2006.190.08:14:18.73#ibcon#about to read 4, iclass 30, count 0 2006.190.08:14:18.73#ibcon#read 4, iclass 30, count 0 2006.190.08:14:18.73#ibcon#about to read 5, iclass 30, count 0 2006.190.08:14:18.73#ibcon#read 5, iclass 30, count 0 2006.190.08:14:18.73#ibcon#about to read 6, iclass 30, count 0 2006.190.08:14:18.73#ibcon#read 6, iclass 30, count 0 2006.190.08:14:18.73#ibcon#end of sib2, iclass 30, count 0 2006.190.08:14:18.73#ibcon#*after write, iclass 30, count 0 2006.190.08:14:18.73#ibcon#*before return 0, iclass 30, count 0 2006.190.08:14:18.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:18.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:18.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:14:18.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:14:18.73$vc4f8/va=3,6 2006.190.08:14:18.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.08:14:18.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.08:14:18.73#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:18.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:18.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:18.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:18.79#ibcon#enter wrdev, iclass 32, count 2 2006.190.08:14:18.79#ibcon#first serial, iclass 32, count 2 2006.190.08:14:18.79#ibcon#enter sib2, iclass 32, count 2 2006.190.08:14:18.79#ibcon#flushed, iclass 32, count 2 2006.190.08:14:18.79#ibcon#about to write, iclass 32, count 2 2006.190.08:14:18.79#ibcon#wrote, iclass 32, count 2 2006.190.08:14:18.79#ibcon#about to read 3, iclass 32, count 2 2006.190.08:14:18.81#ibcon#read 3, iclass 32, count 2 2006.190.08:14:18.81#ibcon#about to read 4, iclass 32, count 2 2006.190.08:14:18.81#ibcon#read 4, iclass 32, count 2 2006.190.08:14:18.81#ibcon#about to read 5, iclass 32, count 2 2006.190.08:14:18.81#ibcon#read 5, iclass 32, count 2 2006.190.08:14:18.81#ibcon#about to read 6, iclass 32, count 2 2006.190.08:14:18.81#ibcon#read 6, iclass 32, count 2 2006.190.08:14:18.81#ibcon#end of sib2, iclass 32, count 2 2006.190.08:14:18.81#ibcon#*mode == 0, iclass 32, count 2 2006.190.08:14:18.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.08:14:18.81#ibcon#[25=AT03-06\r\n] 2006.190.08:14:18.81#ibcon#*before write, iclass 32, count 2 2006.190.08:14:18.81#ibcon#enter sib2, iclass 32, count 2 2006.190.08:14:18.81#ibcon#flushed, iclass 32, count 2 2006.190.08:14:18.81#ibcon#about to write, iclass 32, count 2 2006.190.08:14:18.81#ibcon#wrote, iclass 32, count 2 2006.190.08:14:18.81#ibcon#about to read 3, iclass 32, count 2 2006.190.08:14:18.84#ibcon#read 3, iclass 32, count 2 2006.190.08:14:18.84#ibcon#about to read 4, iclass 32, count 2 2006.190.08:14:18.84#ibcon#read 4, iclass 32, count 2 2006.190.08:14:18.84#ibcon#about to read 5, iclass 32, count 2 2006.190.08:14:18.84#ibcon#read 5, iclass 32, count 2 2006.190.08:14:18.84#ibcon#about to read 6, iclass 32, count 2 2006.190.08:14:18.84#ibcon#read 6, iclass 32, count 2 2006.190.08:14:18.84#ibcon#end of sib2, iclass 32, count 2 2006.190.08:14:18.84#ibcon#*after write, iclass 32, count 2 2006.190.08:14:18.84#ibcon#*before return 0, iclass 32, count 2 2006.190.08:14:18.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:18.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:18.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.08:14:18.84#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:18.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:18.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:18.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:18.96#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:14:18.96#ibcon#first serial, iclass 32, count 0 2006.190.08:14:18.96#ibcon#enter sib2, iclass 32, count 0 2006.190.08:14:18.96#ibcon#flushed, iclass 32, count 0 2006.190.08:14:18.96#ibcon#about to write, iclass 32, count 0 2006.190.08:14:18.96#ibcon#wrote, iclass 32, count 0 2006.190.08:14:18.96#ibcon#about to read 3, iclass 32, count 0 2006.190.08:14:18.98#ibcon#read 3, iclass 32, count 0 2006.190.08:14:18.98#ibcon#about to read 4, iclass 32, count 0 2006.190.08:14:18.98#ibcon#read 4, iclass 32, count 0 2006.190.08:14:18.98#ibcon#about to read 5, iclass 32, count 0 2006.190.08:14:18.98#ibcon#read 5, iclass 32, count 0 2006.190.08:14:18.98#ibcon#about to read 6, iclass 32, count 0 2006.190.08:14:18.98#ibcon#read 6, iclass 32, count 0 2006.190.08:14:18.98#ibcon#end of sib2, iclass 32, count 0 2006.190.08:14:18.98#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:14:18.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:14:18.98#ibcon#[25=USB\r\n] 2006.190.08:14:18.98#ibcon#*before write, iclass 32, count 0 2006.190.08:14:18.98#ibcon#enter sib2, iclass 32, count 0 2006.190.08:14:18.98#ibcon#flushed, iclass 32, count 0 2006.190.08:14:18.98#ibcon#about to write, iclass 32, count 0 2006.190.08:14:18.98#ibcon#wrote, iclass 32, count 0 2006.190.08:14:18.98#ibcon#about to read 3, iclass 32, count 0 2006.190.08:14:19.01#ibcon#read 3, iclass 32, count 0 2006.190.08:14:19.01#ibcon#about to read 4, iclass 32, count 0 2006.190.08:14:19.01#ibcon#read 4, iclass 32, count 0 2006.190.08:14:19.01#ibcon#about to read 5, iclass 32, count 0 2006.190.08:14:19.01#ibcon#read 5, iclass 32, count 0 2006.190.08:14:19.01#ibcon#about to read 6, iclass 32, count 0 2006.190.08:14:19.01#ibcon#read 6, iclass 32, count 0 2006.190.08:14:19.01#ibcon#end of sib2, iclass 32, count 0 2006.190.08:14:19.01#ibcon#*after write, iclass 32, count 0 2006.190.08:14:19.01#ibcon#*before return 0, iclass 32, count 0 2006.190.08:14:19.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:19.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:19.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:14:19.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:14:19.01$vc4f8/valo=4,832.99 2006.190.08:14:19.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.08:14:19.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.08:14:19.01#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:19.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:19.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:19.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:19.01#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:14:19.01#ibcon#first serial, iclass 34, count 0 2006.190.08:14:19.01#ibcon#enter sib2, iclass 34, count 0 2006.190.08:14:19.01#ibcon#flushed, iclass 34, count 0 2006.190.08:14:19.01#ibcon#about to write, iclass 34, count 0 2006.190.08:14:19.01#ibcon#wrote, iclass 34, count 0 2006.190.08:14:19.01#ibcon#about to read 3, iclass 34, count 0 2006.190.08:14:19.03#ibcon#read 3, iclass 34, count 0 2006.190.08:14:19.03#ibcon#about to read 4, iclass 34, count 0 2006.190.08:14:19.03#ibcon#read 4, iclass 34, count 0 2006.190.08:14:19.03#ibcon#about to read 5, iclass 34, count 0 2006.190.08:14:19.03#ibcon#read 5, iclass 34, count 0 2006.190.08:14:19.03#ibcon#about to read 6, iclass 34, count 0 2006.190.08:14:19.03#ibcon#read 6, iclass 34, count 0 2006.190.08:14:19.03#ibcon#end of sib2, iclass 34, count 0 2006.190.08:14:19.03#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:14:19.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:14:19.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:14:19.03#ibcon#*before write, iclass 34, count 0 2006.190.08:14:19.03#ibcon#enter sib2, iclass 34, count 0 2006.190.08:14:19.03#ibcon#flushed, iclass 34, count 0 2006.190.08:14:19.03#ibcon#about to write, iclass 34, count 0 2006.190.08:14:19.03#ibcon#wrote, iclass 34, count 0 2006.190.08:14:19.03#ibcon#about to read 3, iclass 34, count 0 2006.190.08:14:19.07#ibcon#read 3, iclass 34, count 0 2006.190.08:14:19.07#ibcon#about to read 4, iclass 34, count 0 2006.190.08:14:19.07#ibcon#read 4, iclass 34, count 0 2006.190.08:14:19.07#ibcon#about to read 5, iclass 34, count 0 2006.190.08:14:19.07#ibcon#read 5, iclass 34, count 0 2006.190.08:14:19.07#ibcon#about to read 6, iclass 34, count 0 2006.190.08:14:19.07#ibcon#read 6, iclass 34, count 0 2006.190.08:14:19.07#ibcon#end of sib2, iclass 34, count 0 2006.190.08:14:19.07#ibcon#*after write, iclass 34, count 0 2006.190.08:14:19.07#ibcon#*before return 0, iclass 34, count 0 2006.190.08:14:19.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:19.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:19.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:14:19.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:14:19.07$vc4f8/va=4,7 2006.190.08:14:19.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.08:14:19.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.08:14:19.07#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:19.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:19.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:19.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:19.13#ibcon#enter wrdev, iclass 36, count 2 2006.190.08:14:19.13#ibcon#first serial, iclass 36, count 2 2006.190.08:14:19.13#ibcon#enter sib2, iclass 36, count 2 2006.190.08:14:19.13#ibcon#flushed, iclass 36, count 2 2006.190.08:14:19.13#ibcon#about to write, iclass 36, count 2 2006.190.08:14:19.13#ibcon#wrote, iclass 36, count 2 2006.190.08:14:19.13#ibcon#about to read 3, iclass 36, count 2 2006.190.08:14:19.15#ibcon#read 3, iclass 36, count 2 2006.190.08:14:19.15#ibcon#about to read 4, iclass 36, count 2 2006.190.08:14:19.15#ibcon#read 4, iclass 36, count 2 2006.190.08:14:19.15#ibcon#about to read 5, iclass 36, count 2 2006.190.08:14:19.15#ibcon#read 5, iclass 36, count 2 2006.190.08:14:19.15#ibcon#about to read 6, iclass 36, count 2 2006.190.08:14:19.15#ibcon#read 6, iclass 36, count 2 2006.190.08:14:19.15#ibcon#end of sib2, iclass 36, count 2 2006.190.08:14:19.15#ibcon#*mode == 0, iclass 36, count 2 2006.190.08:14:19.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.08:14:19.15#ibcon#[25=AT04-07\r\n] 2006.190.08:14:19.15#ibcon#*before write, iclass 36, count 2 2006.190.08:14:19.15#ibcon#enter sib2, iclass 36, count 2 2006.190.08:14:19.15#ibcon#flushed, iclass 36, count 2 2006.190.08:14:19.15#ibcon#about to write, iclass 36, count 2 2006.190.08:14:19.15#ibcon#wrote, iclass 36, count 2 2006.190.08:14:19.15#ibcon#about to read 3, iclass 36, count 2 2006.190.08:14:19.18#ibcon#read 3, iclass 36, count 2 2006.190.08:14:19.18#ibcon#about to read 4, iclass 36, count 2 2006.190.08:14:19.18#ibcon#read 4, iclass 36, count 2 2006.190.08:14:19.18#ibcon#about to read 5, iclass 36, count 2 2006.190.08:14:19.18#ibcon#read 5, iclass 36, count 2 2006.190.08:14:19.18#ibcon#about to read 6, iclass 36, count 2 2006.190.08:14:19.18#ibcon#read 6, iclass 36, count 2 2006.190.08:14:19.18#ibcon#end of sib2, iclass 36, count 2 2006.190.08:14:19.18#ibcon#*after write, iclass 36, count 2 2006.190.08:14:19.18#ibcon#*before return 0, iclass 36, count 2 2006.190.08:14:19.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:19.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:19.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.08:14:19.18#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:19.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:19.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:19.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:19.30#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:14:19.30#ibcon#first serial, iclass 36, count 0 2006.190.08:14:19.30#ibcon#enter sib2, iclass 36, count 0 2006.190.08:14:19.30#ibcon#flushed, iclass 36, count 0 2006.190.08:14:19.30#ibcon#about to write, iclass 36, count 0 2006.190.08:14:19.30#ibcon#wrote, iclass 36, count 0 2006.190.08:14:19.30#ibcon#about to read 3, iclass 36, count 0 2006.190.08:14:19.32#ibcon#read 3, iclass 36, count 0 2006.190.08:14:19.32#ibcon#about to read 4, iclass 36, count 0 2006.190.08:14:19.32#ibcon#read 4, iclass 36, count 0 2006.190.08:14:19.32#ibcon#about to read 5, iclass 36, count 0 2006.190.08:14:19.32#ibcon#read 5, iclass 36, count 0 2006.190.08:14:19.32#ibcon#about to read 6, iclass 36, count 0 2006.190.08:14:19.32#ibcon#read 6, iclass 36, count 0 2006.190.08:14:19.32#ibcon#end of sib2, iclass 36, count 0 2006.190.08:14:19.32#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:14:19.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:14:19.32#ibcon#[25=USB\r\n] 2006.190.08:14:19.32#ibcon#*before write, iclass 36, count 0 2006.190.08:14:19.32#ibcon#enter sib2, iclass 36, count 0 2006.190.08:14:19.32#ibcon#flushed, iclass 36, count 0 2006.190.08:14:19.32#ibcon#about to write, iclass 36, count 0 2006.190.08:14:19.32#ibcon#wrote, iclass 36, count 0 2006.190.08:14:19.32#ibcon#about to read 3, iclass 36, count 0 2006.190.08:14:19.35#ibcon#read 3, iclass 36, count 0 2006.190.08:14:19.35#ibcon#about to read 4, iclass 36, count 0 2006.190.08:14:19.35#ibcon#read 4, iclass 36, count 0 2006.190.08:14:19.35#ibcon#about to read 5, iclass 36, count 0 2006.190.08:14:19.35#ibcon#read 5, iclass 36, count 0 2006.190.08:14:19.35#ibcon#about to read 6, iclass 36, count 0 2006.190.08:14:19.35#ibcon#read 6, iclass 36, count 0 2006.190.08:14:19.35#ibcon#end of sib2, iclass 36, count 0 2006.190.08:14:19.35#ibcon#*after write, iclass 36, count 0 2006.190.08:14:19.35#ibcon#*before return 0, iclass 36, count 0 2006.190.08:14:19.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:19.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:19.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:14:19.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:14:19.35$vc4f8/valo=5,652.99 2006.190.08:14:19.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.08:14:19.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.08:14:19.35#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:19.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:19.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:19.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:19.35#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:14:19.35#ibcon#first serial, iclass 38, count 0 2006.190.08:14:19.35#ibcon#enter sib2, iclass 38, count 0 2006.190.08:14:19.35#ibcon#flushed, iclass 38, count 0 2006.190.08:14:19.35#ibcon#about to write, iclass 38, count 0 2006.190.08:14:19.35#ibcon#wrote, iclass 38, count 0 2006.190.08:14:19.35#ibcon#about to read 3, iclass 38, count 0 2006.190.08:14:19.37#ibcon#read 3, iclass 38, count 0 2006.190.08:14:19.37#ibcon#about to read 4, iclass 38, count 0 2006.190.08:14:19.37#ibcon#read 4, iclass 38, count 0 2006.190.08:14:19.37#ibcon#about to read 5, iclass 38, count 0 2006.190.08:14:19.37#ibcon#read 5, iclass 38, count 0 2006.190.08:14:19.37#ibcon#about to read 6, iclass 38, count 0 2006.190.08:14:19.37#ibcon#read 6, iclass 38, count 0 2006.190.08:14:19.37#ibcon#end of sib2, iclass 38, count 0 2006.190.08:14:19.37#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:14:19.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:14:19.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:14:19.37#ibcon#*before write, iclass 38, count 0 2006.190.08:14:19.37#ibcon#enter sib2, iclass 38, count 0 2006.190.08:14:19.37#ibcon#flushed, iclass 38, count 0 2006.190.08:14:19.37#ibcon#about to write, iclass 38, count 0 2006.190.08:14:19.37#ibcon#wrote, iclass 38, count 0 2006.190.08:14:19.37#ibcon#about to read 3, iclass 38, count 0 2006.190.08:14:19.41#ibcon#read 3, iclass 38, count 0 2006.190.08:14:19.41#ibcon#about to read 4, iclass 38, count 0 2006.190.08:14:19.41#ibcon#read 4, iclass 38, count 0 2006.190.08:14:19.41#ibcon#about to read 5, iclass 38, count 0 2006.190.08:14:19.41#ibcon#read 5, iclass 38, count 0 2006.190.08:14:19.41#ibcon#about to read 6, iclass 38, count 0 2006.190.08:14:19.41#ibcon#read 6, iclass 38, count 0 2006.190.08:14:19.41#ibcon#end of sib2, iclass 38, count 0 2006.190.08:14:19.41#ibcon#*after write, iclass 38, count 0 2006.190.08:14:19.41#ibcon#*before return 0, iclass 38, count 0 2006.190.08:14:19.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:19.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:19.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:14:19.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:14:19.41$vc4f8/va=5,7 2006.190.08:14:19.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.08:14:19.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.08:14:19.41#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:19.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:19.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:19.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:19.47#ibcon#enter wrdev, iclass 40, count 2 2006.190.08:14:19.47#ibcon#first serial, iclass 40, count 2 2006.190.08:14:19.47#ibcon#enter sib2, iclass 40, count 2 2006.190.08:14:19.47#ibcon#flushed, iclass 40, count 2 2006.190.08:14:19.47#ibcon#about to write, iclass 40, count 2 2006.190.08:14:19.47#ibcon#wrote, iclass 40, count 2 2006.190.08:14:19.47#ibcon#about to read 3, iclass 40, count 2 2006.190.08:14:19.49#ibcon#read 3, iclass 40, count 2 2006.190.08:14:19.49#ibcon#about to read 4, iclass 40, count 2 2006.190.08:14:19.49#ibcon#read 4, iclass 40, count 2 2006.190.08:14:19.49#ibcon#about to read 5, iclass 40, count 2 2006.190.08:14:19.49#ibcon#read 5, iclass 40, count 2 2006.190.08:14:19.49#ibcon#about to read 6, iclass 40, count 2 2006.190.08:14:19.49#ibcon#read 6, iclass 40, count 2 2006.190.08:14:19.49#ibcon#end of sib2, iclass 40, count 2 2006.190.08:14:19.49#ibcon#*mode == 0, iclass 40, count 2 2006.190.08:14:19.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.08:14:19.49#ibcon#[25=AT05-07\r\n] 2006.190.08:14:19.49#ibcon#*before write, iclass 40, count 2 2006.190.08:14:19.49#ibcon#enter sib2, iclass 40, count 2 2006.190.08:14:19.49#ibcon#flushed, iclass 40, count 2 2006.190.08:14:19.49#ibcon#about to write, iclass 40, count 2 2006.190.08:14:19.49#ibcon#wrote, iclass 40, count 2 2006.190.08:14:19.49#ibcon#about to read 3, iclass 40, count 2 2006.190.08:14:19.52#ibcon#read 3, iclass 40, count 2 2006.190.08:14:19.52#ibcon#about to read 4, iclass 40, count 2 2006.190.08:14:19.52#ibcon#read 4, iclass 40, count 2 2006.190.08:14:19.52#ibcon#about to read 5, iclass 40, count 2 2006.190.08:14:19.52#ibcon#read 5, iclass 40, count 2 2006.190.08:14:19.52#ibcon#about to read 6, iclass 40, count 2 2006.190.08:14:19.52#ibcon#read 6, iclass 40, count 2 2006.190.08:14:19.52#ibcon#end of sib2, iclass 40, count 2 2006.190.08:14:19.52#ibcon#*after write, iclass 40, count 2 2006.190.08:14:19.52#ibcon#*before return 0, iclass 40, count 2 2006.190.08:14:19.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:19.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:19.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.08:14:19.52#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:19.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:19.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:19.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:19.64#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:14:19.64#ibcon#first serial, iclass 40, count 0 2006.190.08:14:19.64#ibcon#enter sib2, iclass 40, count 0 2006.190.08:14:19.64#ibcon#flushed, iclass 40, count 0 2006.190.08:14:19.64#ibcon#about to write, iclass 40, count 0 2006.190.08:14:19.64#ibcon#wrote, iclass 40, count 0 2006.190.08:14:19.64#ibcon#about to read 3, iclass 40, count 0 2006.190.08:14:19.66#ibcon#read 3, iclass 40, count 0 2006.190.08:14:19.66#ibcon#about to read 4, iclass 40, count 0 2006.190.08:14:19.66#ibcon#read 4, iclass 40, count 0 2006.190.08:14:19.66#ibcon#about to read 5, iclass 40, count 0 2006.190.08:14:19.66#ibcon#read 5, iclass 40, count 0 2006.190.08:14:19.66#ibcon#about to read 6, iclass 40, count 0 2006.190.08:14:19.66#ibcon#read 6, iclass 40, count 0 2006.190.08:14:19.66#ibcon#end of sib2, iclass 40, count 0 2006.190.08:14:19.66#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:14:19.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:14:19.66#ibcon#[25=USB\r\n] 2006.190.08:14:19.66#ibcon#*before write, iclass 40, count 0 2006.190.08:14:19.66#ibcon#enter sib2, iclass 40, count 0 2006.190.08:14:19.66#ibcon#flushed, iclass 40, count 0 2006.190.08:14:19.66#ibcon#about to write, iclass 40, count 0 2006.190.08:14:19.66#ibcon#wrote, iclass 40, count 0 2006.190.08:14:19.66#ibcon#about to read 3, iclass 40, count 0 2006.190.08:14:19.69#ibcon#read 3, iclass 40, count 0 2006.190.08:14:19.69#ibcon#about to read 4, iclass 40, count 0 2006.190.08:14:19.69#ibcon#read 4, iclass 40, count 0 2006.190.08:14:19.69#ibcon#about to read 5, iclass 40, count 0 2006.190.08:14:19.69#ibcon#read 5, iclass 40, count 0 2006.190.08:14:19.69#ibcon#about to read 6, iclass 40, count 0 2006.190.08:14:19.69#ibcon#read 6, iclass 40, count 0 2006.190.08:14:19.69#ibcon#end of sib2, iclass 40, count 0 2006.190.08:14:19.69#ibcon#*after write, iclass 40, count 0 2006.190.08:14:19.69#ibcon#*before return 0, iclass 40, count 0 2006.190.08:14:19.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:19.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:19.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:14:19.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:14:19.69$vc4f8/valo=6,772.99 2006.190.08:14:19.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.08:14:19.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.08:14:19.69#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:19.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:19.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:19.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:19.69#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:14:19.69#ibcon#first serial, iclass 4, count 0 2006.190.08:14:19.69#ibcon#enter sib2, iclass 4, count 0 2006.190.08:14:19.69#ibcon#flushed, iclass 4, count 0 2006.190.08:14:19.69#ibcon#about to write, iclass 4, count 0 2006.190.08:14:19.69#ibcon#wrote, iclass 4, count 0 2006.190.08:14:19.69#ibcon#about to read 3, iclass 4, count 0 2006.190.08:14:19.71#ibcon#read 3, iclass 4, count 0 2006.190.08:14:19.71#ibcon#about to read 4, iclass 4, count 0 2006.190.08:14:19.71#ibcon#read 4, iclass 4, count 0 2006.190.08:14:19.71#ibcon#about to read 5, iclass 4, count 0 2006.190.08:14:19.71#ibcon#read 5, iclass 4, count 0 2006.190.08:14:19.71#ibcon#about to read 6, iclass 4, count 0 2006.190.08:14:19.71#ibcon#read 6, iclass 4, count 0 2006.190.08:14:19.71#ibcon#end of sib2, iclass 4, count 0 2006.190.08:14:19.71#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:14:19.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:14:19.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:14:19.71#ibcon#*before write, iclass 4, count 0 2006.190.08:14:19.71#ibcon#enter sib2, iclass 4, count 0 2006.190.08:14:19.71#ibcon#flushed, iclass 4, count 0 2006.190.08:14:19.71#ibcon#about to write, iclass 4, count 0 2006.190.08:14:19.71#ibcon#wrote, iclass 4, count 0 2006.190.08:14:19.71#ibcon#about to read 3, iclass 4, count 0 2006.190.08:14:19.75#ibcon#read 3, iclass 4, count 0 2006.190.08:14:19.75#ibcon#about to read 4, iclass 4, count 0 2006.190.08:14:19.75#ibcon#read 4, iclass 4, count 0 2006.190.08:14:19.75#ibcon#about to read 5, iclass 4, count 0 2006.190.08:14:19.75#ibcon#read 5, iclass 4, count 0 2006.190.08:14:19.75#ibcon#about to read 6, iclass 4, count 0 2006.190.08:14:19.75#ibcon#read 6, iclass 4, count 0 2006.190.08:14:19.75#ibcon#end of sib2, iclass 4, count 0 2006.190.08:14:19.75#ibcon#*after write, iclass 4, count 0 2006.190.08:14:19.75#ibcon#*before return 0, iclass 4, count 0 2006.190.08:14:19.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:19.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:19.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:14:19.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:14:19.75$vc4f8/va=6,6 2006.190.08:14:19.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.08:14:19.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.08:14:19.75#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:19.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:14:19.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:14:19.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:14:19.81#ibcon#enter wrdev, iclass 6, count 2 2006.190.08:14:19.81#ibcon#first serial, iclass 6, count 2 2006.190.08:14:19.81#ibcon#enter sib2, iclass 6, count 2 2006.190.08:14:19.81#ibcon#flushed, iclass 6, count 2 2006.190.08:14:19.81#ibcon#about to write, iclass 6, count 2 2006.190.08:14:19.81#ibcon#wrote, iclass 6, count 2 2006.190.08:14:19.81#ibcon#about to read 3, iclass 6, count 2 2006.190.08:14:19.83#ibcon#read 3, iclass 6, count 2 2006.190.08:14:19.83#ibcon#about to read 4, iclass 6, count 2 2006.190.08:14:19.83#ibcon#read 4, iclass 6, count 2 2006.190.08:14:19.83#ibcon#about to read 5, iclass 6, count 2 2006.190.08:14:19.83#ibcon#read 5, iclass 6, count 2 2006.190.08:14:19.83#ibcon#about to read 6, iclass 6, count 2 2006.190.08:14:19.83#ibcon#read 6, iclass 6, count 2 2006.190.08:14:19.83#ibcon#end of sib2, iclass 6, count 2 2006.190.08:14:19.83#ibcon#*mode == 0, iclass 6, count 2 2006.190.08:14:19.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.08:14:19.83#ibcon#[25=AT06-06\r\n] 2006.190.08:14:19.83#ibcon#*before write, iclass 6, count 2 2006.190.08:14:19.83#ibcon#enter sib2, iclass 6, count 2 2006.190.08:14:19.83#ibcon#flushed, iclass 6, count 2 2006.190.08:14:19.83#ibcon#about to write, iclass 6, count 2 2006.190.08:14:19.83#ibcon#wrote, iclass 6, count 2 2006.190.08:14:19.83#ibcon#about to read 3, iclass 6, count 2 2006.190.08:14:19.86#ibcon#read 3, iclass 6, count 2 2006.190.08:14:19.86#ibcon#about to read 4, iclass 6, count 2 2006.190.08:14:19.86#ibcon#read 4, iclass 6, count 2 2006.190.08:14:19.86#ibcon#about to read 5, iclass 6, count 2 2006.190.08:14:19.86#ibcon#read 5, iclass 6, count 2 2006.190.08:14:19.86#ibcon#about to read 6, iclass 6, count 2 2006.190.08:14:19.86#ibcon#read 6, iclass 6, count 2 2006.190.08:14:19.86#ibcon#end of sib2, iclass 6, count 2 2006.190.08:14:19.86#ibcon#*after write, iclass 6, count 2 2006.190.08:14:19.86#ibcon#*before return 0, iclass 6, count 2 2006.190.08:14:19.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:14:19.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:14:19.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.08:14:19.86#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:19.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:14:19.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:14:19.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:14:19.98#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:14:19.98#ibcon#first serial, iclass 6, count 0 2006.190.08:14:19.98#ibcon#enter sib2, iclass 6, count 0 2006.190.08:14:19.98#ibcon#flushed, iclass 6, count 0 2006.190.08:14:19.98#ibcon#about to write, iclass 6, count 0 2006.190.08:14:19.98#ibcon#wrote, iclass 6, count 0 2006.190.08:14:19.98#ibcon#about to read 3, iclass 6, count 0 2006.190.08:14:20.00#ibcon#read 3, iclass 6, count 0 2006.190.08:14:20.00#ibcon#about to read 4, iclass 6, count 0 2006.190.08:14:20.00#ibcon#read 4, iclass 6, count 0 2006.190.08:14:20.00#ibcon#about to read 5, iclass 6, count 0 2006.190.08:14:20.00#ibcon#read 5, iclass 6, count 0 2006.190.08:14:20.00#ibcon#about to read 6, iclass 6, count 0 2006.190.08:14:20.00#ibcon#read 6, iclass 6, count 0 2006.190.08:14:20.00#ibcon#end of sib2, iclass 6, count 0 2006.190.08:14:20.00#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:14:20.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:14:20.00#ibcon#[25=USB\r\n] 2006.190.08:14:20.00#ibcon#*before write, iclass 6, count 0 2006.190.08:14:20.00#ibcon#enter sib2, iclass 6, count 0 2006.190.08:14:20.00#ibcon#flushed, iclass 6, count 0 2006.190.08:14:20.00#ibcon#about to write, iclass 6, count 0 2006.190.08:14:20.00#ibcon#wrote, iclass 6, count 0 2006.190.08:14:20.00#ibcon#about to read 3, iclass 6, count 0 2006.190.08:14:20.03#ibcon#read 3, iclass 6, count 0 2006.190.08:14:20.03#ibcon#about to read 4, iclass 6, count 0 2006.190.08:14:20.03#ibcon#read 4, iclass 6, count 0 2006.190.08:14:20.03#ibcon#about to read 5, iclass 6, count 0 2006.190.08:14:20.03#ibcon#read 5, iclass 6, count 0 2006.190.08:14:20.03#ibcon#about to read 6, iclass 6, count 0 2006.190.08:14:20.03#ibcon#read 6, iclass 6, count 0 2006.190.08:14:20.03#ibcon#end of sib2, iclass 6, count 0 2006.190.08:14:20.03#ibcon#*after write, iclass 6, count 0 2006.190.08:14:20.03#ibcon#*before return 0, iclass 6, count 0 2006.190.08:14:20.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:14:20.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:14:20.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:14:20.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:14:20.03$vc4f8/valo=7,832.99 2006.190.08:14:20.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.08:14:20.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.08:14:20.03#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:20.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:14:20.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:14:20.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:14:20.03#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:14:20.03#ibcon#first serial, iclass 10, count 0 2006.190.08:14:20.03#ibcon#enter sib2, iclass 10, count 0 2006.190.08:14:20.03#ibcon#flushed, iclass 10, count 0 2006.190.08:14:20.03#ibcon#about to write, iclass 10, count 0 2006.190.08:14:20.03#ibcon#wrote, iclass 10, count 0 2006.190.08:14:20.03#ibcon#about to read 3, iclass 10, count 0 2006.190.08:14:20.05#ibcon#read 3, iclass 10, count 0 2006.190.08:14:20.05#ibcon#about to read 4, iclass 10, count 0 2006.190.08:14:20.05#ibcon#read 4, iclass 10, count 0 2006.190.08:14:20.05#ibcon#about to read 5, iclass 10, count 0 2006.190.08:14:20.05#ibcon#read 5, iclass 10, count 0 2006.190.08:14:20.05#ibcon#about to read 6, iclass 10, count 0 2006.190.08:14:20.05#ibcon#read 6, iclass 10, count 0 2006.190.08:14:20.05#ibcon#end of sib2, iclass 10, count 0 2006.190.08:14:20.05#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:14:20.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:14:20.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:14:20.05#ibcon#*before write, iclass 10, count 0 2006.190.08:14:20.05#ibcon#enter sib2, iclass 10, count 0 2006.190.08:14:20.05#ibcon#flushed, iclass 10, count 0 2006.190.08:14:20.05#ibcon#about to write, iclass 10, count 0 2006.190.08:14:20.05#ibcon#wrote, iclass 10, count 0 2006.190.08:14:20.05#ibcon#about to read 3, iclass 10, count 0 2006.190.08:14:20.09#ibcon#read 3, iclass 10, count 0 2006.190.08:14:20.09#ibcon#about to read 4, iclass 10, count 0 2006.190.08:14:20.09#ibcon#read 4, iclass 10, count 0 2006.190.08:14:20.09#ibcon#about to read 5, iclass 10, count 0 2006.190.08:14:20.09#ibcon#read 5, iclass 10, count 0 2006.190.08:14:20.09#ibcon#about to read 6, iclass 10, count 0 2006.190.08:14:20.09#ibcon#read 6, iclass 10, count 0 2006.190.08:14:20.09#ibcon#end of sib2, iclass 10, count 0 2006.190.08:14:20.09#ibcon#*after write, iclass 10, count 0 2006.190.08:14:20.09#ibcon#*before return 0, iclass 10, count 0 2006.190.08:14:20.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:14:20.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:14:20.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:14:20.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:14:20.09$vc4f8/va=7,6 2006.190.08:14:20.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.08:14:20.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.08:14:20.09#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:20.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:14:20.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:14:20.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:14:20.15#ibcon#enter wrdev, iclass 12, count 2 2006.190.08:14:20.15#ibcon#first serial, iclass 12, count 2 2006.190.08:14:20.15#ibcon#enter sib2, iclass 12, count 2 2006.190.08:14:20.15#ibcon#flushed, iclass 12, count 2 2006.190.08:14:20.15#ibcon#about to write, iclass 12, count 2 2006.190.08:14:20.15#ibcon#wrote, iclass 12, count 2 2006.190.08:14:20.15#ibcon#about to read 3, iclass 12, count 2 2006.190.08:14:20.17#ibcon#read 3, iclass 12, count 2 2006.190.08:14:20.17#ibcon#about to read 4, iclass 12, count 2 2006.190.08:14:20.17#ibcon#read 4, iclass 12, count 2 2006.190.08:14:20.17#ibcon#about to read 5, iclass 12, count 2 2006.190.08:14:20.17#ibcon#read 5, iclass 12, count 2 2006.190.08:14:20.17#ibcon#about to read 6, iclass 12, count 2 2006.190.08:14:20.17#ibcon#read 6, iclass 12, count 2 2006.190.08:14:20.17#ibcon#end of sib2, iclass 12, count 2 2006.190.08:14:20.17#ibcon#*mode == 0, iclass 12, count 2 2006.190.08:14:20.17#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.08:14:20.17#ibcon#[25=AT07-06\r\n] 2006.190.08:14:20.17#ibcon#*before write, iclass 12, count 2 2006.190.08:14:20.17#ibcon#enter sib2, iclass 12, count 2 2006.190.08:14:20.17#ibcon#flushed, iclass 12, count 2 2006.190.08:14:20.17#ibcon#about to write, iclass 12, count 2 2006.190.08:14:20.17#ibcon#wrote, iclass 12, count 2 2006.190.08:14:20.17#ibcon#about to read 3, iclass 12, count 2 2006.190.08:14:20.20#ibcon#read 3, iclass 12, count 2 2006.190.08:14:20.20#ibcon#about to read 4, iclass 12, count 2 2006.190.08:14:20.20#ibcon#read 4, iclass 12, count 2 2006.190.08:14:20.20#ibcon#about to read 5, iclass 12, count 2 2006.190.08:14:20.20#ibcon#read 5, iclass 12, count 2 2006.190.08:14:20.20#ibcon#about to read 6, iclass 12, count 2 2006.190.08:14:20.20#ibcon#read 6, iclass 12, count 2 2006.190.08:14:20.20#ibcon#end of sib2, iclass 12, count 2 2006.190.08:14:20.20#ibcon#*after write, iclass 12, count 2 2006.190.08:14:20.20#ibcon#*before return 0, iclass 12, count 2 2006.190.08:14:20.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:14:20.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:14:20.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.08:14:20.20#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:20.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:14:20.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:14:20.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:14:20.32#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:14:20.32#ibcon#first serial, iclass 12, count 0 2006.190.08:14:20.32#ibcon#enter sib2, iclass 12, count 0 2006.190.08:14:20.32#ibcon#flushed, iclass 12, count 0 2006.190.08:14:20.32#ibcon#about to write, iclass 12, count 0 2006.190.08:14:20.32#ibcon#wrote, iclass 12, count 0 2006.190.08:14:20.32#ibcon#about to read 3, iclass 12, count 0 2006.190.08:14:20.34#ibcon#read 3, iclass 12, count 0 2006.190.08:14:20.34#ibcon#about to read 4, iclass 12, count 0 2006.190.08:14:20.34#ibcon#read 4, iclass 12, count 0 2006.190.08:14:20.34#ibcon#about to read 5, iclass 12, count 0 2006.190.08:14:20.34#ibcon#read 5, iclass 12, count 0 2006.190.08:14:20.34#ibcon#about to read 6, iclass 12, count 0 2006.190.08:14:20.34#ibcon#read 6, iclass 12, count 0 2006.190.08:14:20.34#ibcon#end of sib2, iclass 12, count 0 2006.190.08:14:20.34#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:14:20.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:14:20.34#ibcon#[25=USB\r\n] 2006.190.08:14:20.34#ibcon#*before write, iclass 12, count 0 2006.190.08:14:20.34#ibcon#enter sib2, iclass 12, count 0 2006.190.08:14:20.34#ibcon#flushed, iclass 12, count 0 2006.190.08:14:20.34#ibcon#about to write, iclass 12, count 0 2006.190.08:14:20.34#ibcon#wrote, iclass 12, count 0 2006.190.08:14:20.34#ibcon#about to read 3, iclass 12, count 0 2006.190.08:14:20.37#ibcon#read 3, iclass 12, count 0 2006.190.08:14:20.37#ibcon#about to read 4, iclass 12, count 0 2006.190.08:14:20.37#ibcon#read 4, iclass 12, count 0 2006.190.08:14:20.37#ibcon#about to read 5, iclass 12, count 0 2006.190.08:14:20.37#ibcon#read 5, iclass 12, count 0 2006.190.08:14:20.37#ibcon#about to read 6, iclass 12, count 0 2006.190.08:14:20.37#ibcon#read 6, iclass 12, count 0 2006.190.08:14:20.37#ibcon#end of sib2, iclass 12, count 0 2006.190.08:14:20.37#ibcon#*after write, iclass 12, count 0 2006.190.08:14:20.37#ibcon#*before return 0, iclass 12, count 0 2006.190.08:14:20.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:14:20.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:14:20.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:14:20.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:14:20.37$vc4f8/valo=8,852.99 2006.190.08:14:20.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.08:14:20.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.08:14:20.37#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:20.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:14:20.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:14:20.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:14:20.37#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:14:20.37#ibcon#first serial, iclass 14, count 0 2006.190.08:14:20.37#ibcon#enter sib2, iclass 14, count 0 2006.190.08:14:20.37#ibcon#flushed, iclass 14, count 0 2006.190.08:14:20.37#ibcon#about to write, iclass 14, count 0 2006.190.08:14:20.37#ibcon#wrote, iclass 14, count 0 2006.190.08:14:20.37#ibcon#about to read 3, iclass 14, count 0 2006.190.08:14:20.39#ibcon#read 3, iclass 14, count 0 2006.190.08:14:20.39#ibcon#about to read 4, iclass 14, count 0 2006.190.08:14:20.39#ibcon#read 4, iclass 14, count 0 2006.190.08:14:20.39#ibcon#about to read 5, iclass 14, count 0 2006.190.08:14:20.39#ibcon#read 5, iclass 14, count 0 2006.190.08:14:20.39#ibcon#about to read 6, iclass 14, count 0 2006.190.08:14:20.39#ibcon#read 6, iclass 14, count 0 2006.190.08:14:20.39#ibcon#end of sib2, iclass 14, count 0 2006.190.08:14:20.39#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:14:20.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:14:20.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:14:20.39#ibcon#*before write, iclass 14, count 0 2006.190.08:14:20.39#ibcon#enter sib2, iclass 14, count 0 2006.190.08:14:20.39#ibcon#flushed, iclass 14, count 0 2006.190.08:14:20.39#ibcon#about to write, iclass 14, count 0 2006.190.08:14:20.39#ibcon#wrote, iclass 14, count 0 2006.190.08:14:20.39#ibcon#about to read 3, iclass 14, count 0 2006.190.08:14:20.43#ibcon#read 3, iclass 14, count 0 2006.190.08:14:20.43#ibcon#about to read 4, iclass 14, count 0 2006.190.08:14:20.43#ibcon#read 4, iclass 14, count 0 2006.190.08:14:20.43#ibcon#about to read 5, iclass 14, count 0 2006.190.08:14:20.43#ibcon#read 5, iclass 14, count 0 2006.190.08:14:20.43#ibcon#about to read 6, iclass 14, count 0 2006.190.08:14:20.43#ibcon#read 6, iclass 14, count 0 2006.190.08:14:20.43#ibcon#end of sib2, iclass 14, count 0 2006.190.08:14:20.43#ibcon#*after write, iclass 14, count 0 2006.190.08:14:20.43#ibcon#*before return 0, iclass 14, count 0 2006.190.08:14:20.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:14:20.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:14:20.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:14:20.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:14:20.43$vc4f8/va=8,6 2006.190.08:14:20.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.08:14:20.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.08:14:20.43#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:20.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:14:20.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:14:20.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:14:20.49#ibcon#enter wrdev, iclass 16, count 2 2006.190.08:14:20.49#ibcon#first serial, iclass 16, count 2 2006.190.08:14:20.49#ibcon#enter sib2, iclass 16, count 2 2006.190.08:14:20.49#ibcon#flushed, iclass 16, count 2 2006.190.08:14:20.49#ibcon#about to write, iclass 16, count 2 2006.190.08:14:20.49#ibcon#wrote, iclass 16, count 2 2006.190.08:14:20.49#ibcon#about to read 3, iclass 16, count 2 2006.190.08:14:20.51#ibcon#read 3, iclass 16, count 2 2006.190.08:14:20.51#ibcon#about to read 4, iclass 16, count 2 2006.190.08:14:20.51#ibcon#read 4, iclass 16, count 2 2006.190.08:14:20.51#ibcon#about to read 5, iclass 16, count 2 2006.190.08:14:20.51#ibcon#read 5, iclass 16, count 2 2006.190.08:14:20.51#ibcon#about to read 6, iclass 16, count 2 2006.190.08:14:20.51#ibcon#read 6, iclass 16, count 2 2006.190.08:14:20.51#ibcon#end of sib2, iclass 16, count 2 2006.190.08:14:20.51#ibcon#*mode == 0, iclass 16, count 2 2006.190.08:14:20.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.08:14:20.51#ibcon#[25=AT08-06\r\n] 2006.190.08:14:20.51#ibcon#*before write, iclass 16, count 2 2006.190.08:14:20.51#ibcon#enter sib2, iclass 16, count 2 2006.190.08:14:20.51#ibcon#flushed, iclass 16, count 2 2006.190.08:14:20.51#ibcon#about to write, iclass 16, count 2 2006.190.08:14:20.51#ibcon#wrote, iclass 16, count 2 2006.190.08:14:20.51#ibcon#about to read 3, iclass 16, count 2 2006.190.08:14:20.54#ibcon#read 3, iclass 16, count 2 2006.190.08:14:20.54#ibcon#about to read 4, iclass 16, count 2 2006.190.08:14:20.54#ibcon#read 4, iclass 16, count 2 2006.190.08:14:20.54#ibcon#about to read 5, iclass 16, count 2 2006.190.08:14:20.54#ibcon#read 5, iclass 16, count 2 2006.190.08:14:20.54#ibcon#about to read 6, iclass 16, count 2 2006.190.08:14:20.54#ibcon#read 6, iclass 16, count 2 2006.190.08:14:20.54#ibcon#end of sib2, iclass 16, count 2 2006.190.08:14:20.54#ibcon#*after write, iclass 16, count 2 2006.190.08:14:20.54#ibcon#*before return 0, iclass 16, count 2 2006.190.08:14:20.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:14:20.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:14:20.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.08:14:20.54#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:20.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:14:20.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:14:20.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:14:20.66#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:14:20.66#ibcon#first serial, iclass 16, count 0 2006.190.08:14:20.66#ibcon#enter sib2, iclass 16, count 0 2006.190.08:14:20.66#ibcon#flushed, iclass 16, count 0 2006.190.08:14:20.66#ibcon#about to write, iclass 16, count 0 2006.190.08:14:20.66#ibcon#wrote, iclass 16, count 0 2006.190.08:14:20.66#ibcon#about to read 3, iclass 16, count 0 2006.190.08:14:20.68#ibcon#read 3, iclass 16, count 0 2006.190.08:14:20.68#ibcon#about to read 4, iclass 16, count 0 2006.190.08:14:20.68#ibcon#read 4, iclass 16, count 0 2006.190.08:14:20.68#ibcon#about to read 5, iclass 16, count 0 2006.190.08:14:20.68#ibcon#read 5, iclass 16, count 0 2006.190.08:14:20.68#ibcon#about to read 6, iclass 16, count 0 2006.190.08:14:20.68#ibcon#read 6, iclass 16, count 0 2006.190.08:14:20.68#ibcon#end of sib2, iclass 16, count 0 2006.190.08:14:20.68#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:14:20.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:14:20.68#ibcon#[25=USB\r\n] 2006.190.08:14:20.68#ibcon#*before write, iclass 16, count 0 2006.190.08:14:20.68#ibcon#enter sib2, iclass 16, count 0 2006.190.08:14:20.68#ibcon#flushed, iclass 16, count 0 2006.190.08:14:20.68#ibcon#about to write, iclass 16, count 0 2006.190.08:14:20.68#ibcon#wrote, iclass 16, count 0 2006.190.08:14:20.68#ibcon#about to read 3, iclass 16, count 0 2006.190.08:14:20.71#ibcon#read 3, iclass 16, count 0 2006.190.08:14:20.71#ibcon#about to read 4, iclass 16, count 0 2006.190.08:14:20.71#ibcon#read 4, iclass 16, count 0 2006.190.08:14:20.71#ibcon#about to read 5, iclass 16, count 0 2006.190.08:14:20.71#ibcon#read 5, iclass 16, count 0 2006.190.08:14:20.71#ibcon#about to read 6, iclass 16, count 0 2006.190.08:14:20.71#ibcon#read 6, iclass 16, count 0 2006.190.08:14:20.71#ibcon#end of sib2, iclass 16, count 0 2006.190.08:14:20.71#ibcon#*after write, iclass 16, count 0 2006.190.08:14:20.71#ibcon#*before return 0, iclass 16, count 0 2006.190.08:14:20.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:14:20.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:14:20.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:14:20.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:14:20.71$vc4f8/vblo=1,632.99 2006.190.08:14:20.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.08:14:20.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.08:14:20.71#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:20.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:14:20.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:14:20.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:14:20.71#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:14:20.71#ibcon#first serial, iclass 18, count 0 2006.190.08:14:20.71#ibcon#enter sib2, iclass 18, count 0 2006.190.08:14:20.71#ibcon#flushed, iclass 18, count 0 2006.190.08:14:20.71#ibcon#about to write, iclass 18, count 0 2006.190.08:14:20.71#ibcon#wrote, iclass 18, count 0 2006.190.08:14:20.71#ibcon#about to read 3, iclass 18, count 0 2006.190.08:14:20.73#ibcon#read 3, iclass 18, count 0 2006.190.08:14:20.73#ibcon#about to read 4, iclass 18, count 0 2006.190.08:14:20.73#ibcon#read 4, iclass 18, count 0 2006.190.08:14:20.73#ibcon#about to read 5, iclass 18, count 0 2006.190.08:14:20.73#ibcon#read 5, iclass 18, count 0 2006.190.08:14:20.73#ibcon#about to read 6, iclass 18, count 0 2006.190.08:14:20.73#ibcon#read 6, iclass 18, count 0 2006.190.08:14:20.73#ibcon#end of sib2, iclass 18, count 0 2006.190.08:14:20.73#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:14:20.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:14:20.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:14:20.73#ibcon#*before write, iclass 18, count 0 2006.190.08:14:20.73#ibcon#enter sib2, iclass 18, count 0 2006.190.08:14:20.73#ibcon#flushed, iclass 18, count 0 2006.190.08:14:20.73#ibcon#about to write, iclass 18, count 0 2006.190.08:14:20.73#ibcon#wrote, iclass 18, count 0 2006.190.08:14:20.73#ibcon#about to read 3, iclass 18, count 0 2006.190.08:14:20.77#ibcon#read 3, iclass 18, count 0 2006.190.08:14:20.77#ibcon#about to read 4, iclass 18, count 0 2006.190.08:14:20.77#ibcon#read 4, iclass 18, count 0 2006.190.08:14:20.77#ibcon#about to read 5, iclass 18, count 0 2006.190.08:14:20.77#ibcon#read 5, iclass 18, count 0 2006.190.08:14:20.77#ibcon#about to read 6, iclass 18, count 0 2006.190.08:14:20.77#ibcon#read 6, iclass 18, count 0 2006.190.08:14:20.77#ibcon#end of sib2, iclass 18, count 0 2006.190.08:14:20.77#ibcon#*after write, iclass 18, count 0 2006.190.08:14:20.77#ibcon#*before return 0, iclass 18, count 0 2006.190.08:14:20.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:14:20.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:14:20.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:14:20.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:14:20.77$vc4f8/vb=1,4 2006.190.08:14:20.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.190.08:14:20.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.190.08:14:20.77#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:20.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:14:20.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:14:20.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:14:20.77#ibcon#enter wrdev, iclass 20, count 2 2006.190.08:14:20.77#ibcon#first serial, iclass 20, count 2 2006.190.08:14:20.77#ibcon#enter sib2, iclass 20, count 2 2006.190.08:14:20.77#ibcon#flushed, iclass 20, count 2 2006.190.08:14:20.77#ibcon#about to write, iclass 20, count 2 2006.190.08:14:20.77#ibcon#wrote, iclass 20, count 2 2006.190.08:14:20.77#ibcon#about to read 3, iclass 20, count 2 2006.190.08:14:20.79#ibcon#read 3, iclass 20, count 2 2006.190.08:14:20.79#ibcon#about to read 4, iclass 20, count 2 2006.190.08:14:20.79#ibcon#read 4, iclass 20, count 2 2006.190.08:14:20.79#ibcon#about to read 5, iclass 20, count 2 2006.190.08:14:20.79#ibcon#read 5, iclass 20, count 2 2006.190.08:14:20.79#ibcon#about to read 6, iclass 20, count 2 2006.190.08:14:20.79#ibcon#read 6, iclass 20, count 2 2006.190.08:14:20.79#ibcon#end of sib2, iclass 20, count 2 2006.190.08:14:20.79#ibcon#*mode == 0, iclass 20, count 2 2006.190.08:14:20.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.190.08:14:20.79#ibcon#[27=AT01-04\r\n] 2006.190.08:14:20.79#ibcon#*before write, iclass 20, count 2 2006.190.08:14:20.79#ibcon#enter sib2, iclass 20, count 2 2006.190.08:14:20.79#ibcon#flushed, iclass 20, count 2 2006.190.08:14:20.79#ibcon#about to write, iclass 20, count 2 2006.190.08:14:20.79#ibcon#wrote, iclass 20, count 2 2006.190.08:14:20.79#ibcon#about to read 3, iclass 20, count 2 2006.190.08:14:20.82#ibcon#read 3, iclass 20, count 2 2006.190.08:14:20.82#ibcon#about to read 4, iclass 20, count 2 2006.190.08:14:20.82#ibcon#read 4, iclass 20, count 2 2006.190.08:14:20.82#ibcon#about to read 5, iclass 20, count 2 2006.190.08:14:20.82#ibcon#read 5, iclass 20, count 2 2006.190.08:14:20.82#ibcon#about to read 6, iclass 20, count 2 2006.190.08:14:20.82#ibcon#read 6, iclass 20, count 2 2006.190.08:14:20.82#ibcon#end of sib2, iclass 20, count 2 2006.190.08:14:20.82#ibcon#*after write, iclass 20, count 2 2006.190.08:14:20.82#ibcon#*before return 0, iclass 20, count 2 2006.190.08:14:20.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:14:20.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:14:20.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.190.08:14:20.82#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:20.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:14:20.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:14:20.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:14:20.94#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:14:20.94#ibcon#first serial, iclass 20, count 0 2006.190.08:14:20.94#ibcon#enter sib2, iclass 20, count 0 2006.190.08:14:20.94#ibcon#flushed, iclass 20, count 0 2006.190.08:14:20.94#ibcon#about to write, iclass 20, count 0 2006.190.08:14:20.94#ibcon#wrote, iclass 20, count 0 2006.190.08:14:20.94#ibcon#about to read 3, iclass 20, count 0 2006.190.08:14:20.96#ibcon#read 3, iclass 20, count 0 2006.190.08:14:20.96#ibcon#about to read 4, iclass 20, count 0 2006.190.08:14:20.96#ibcon#read 4, iclass 20, count 0 2006.190.08:14:20.96#ibcon#about to read 5, iclass 20, count 0 2006.190.08:14:20.96#ibcon#read 5, iclass 20, count 0 2006.190.08:14:20.96#ibcon#about to read 6, iclass 20, count 0 2006.190.08:14:20.96#ibcon#read 6, iclass 20, count 0 2006.190.08:14:20.96#ibcon#end of sib2, iclass 20, count 0 2006.190.08:14:20.96#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:14:20.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:14:20.96#ibcon#[27=USB\r\n] 2006.190.08:14:20.96#ibcon#*before write, iclass 20, count 0 2006.190.08:14:20.96#ibcon#enter sib2, iclass 20, count 0 2006.190.08:14:20.96#ibcon#flushed, iclass 20, count 0 2006.190.08:14:20.96#ibcon#about to write, iclass 20, count 0 2006.190.08:14:20.96#ibcon#wrote, iclass 20, count 0 2006.190.08:14:20.96#ibcon#about to read 3, iclass 20, count 0 2006.190.08:14:20.99#ibcon#read 3, iclass 20, count 0 2006.190.08:14:20.99#ibcon#about to read 4, iclass 20, count 0 2006.190.08:14:20.99#ibcon#read 4, iclass 20, count 0 2006.190.08:14:20.99#ibcon#about to read 5, iclass 20, count 0 2006.190.08:14:20.99#ibcon#read 5, iclass 20, count 0 2006.190.08:14:20.99#ibcon#about to read 6, iclass 20, count 0 2006.190.08:14:20.99#ibcon#read 6, iclass 20, count 0 2006.190.08:14:20.99#ibcon#end of sib2, iclass 20, count 0 2006.190.08:14:20.99#ibcon#*after write, iclass 20, count 0 2006.190.08:14:20.99#ibcon#*before return 0, iclass 20, count 0 2006.190.08:14:20.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:14:20.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:14:20.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:14:20.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:14:20.99$vc4f8/vblo=2,640.99 2006.190.08:14:20.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.08:14:20.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.08:14:20.99#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:20.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:20.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:20.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:20.99#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:14:20.99#ibcon#first serial, iclass 22, count 0 2006.190.08:14:20.99#ibcon#enter sib2, iclass 22, count 0 2006.190.08:14:20.99#ibcon#flushed, iclass 22, count 0 2006.190.08:14:20.99#ibcon#about to write, iclass 22, count 0 2006.190.08:14:20.99#ibcon#wrote, iclass 22, count 0 2006.190.08:14:20.99#ibcon#about to read 3, iclass 22, count 0 2006.190.08:14:21.01#ibcon#read 3, iclass 22, count 0 2006.190.08:14:21.01#ibcon#about to read 4, iclass 22, count 0 2006.190.08:14:21.01#ibcon#read 4, iclass 22, count 0 2006.190.08:14:21.01#ibcon#about to read 5, iclass 22, count 0 2006.190.08:14:21.01#ibcon#read 5, iclass 22, count 0 2006.190.08:14:21.01#ibcon#about to read 6, iclass 22, count 0 2006.190.08:14:21.01#ibcon#read 6, iclass 22, count 0 2006.190.08:14:21.01#ibcon#end of sib2, iclass 22, count 0 2006.190.08:14:21.01#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:14:21.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:14:21.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:14:21.01#ibcon#*before write, iclass 22, count 0 2006.190.08:14:21.01#ibcon#enter sib2, iclass 22, count 0 2006.190.08:14:21.01#ibcon#flushed, iclass 22, count 0 2006.190.08:14:21.01#ibcon#about to write, iclass 22, count 0 2006.190.08:14:21.01#ibcon#wrote, iclass 22, count 0 2006.190.08:14:21.01#ibcon#about to read 3, iclass 22, count 0 2006.190.08:14:21.05#ibcon#read 3, iclass 22, count 0 2006.190.08:14:21.05#ibcon#about to read 4, iclass 22, count 0 2006.190.08:14:21.05#ibcon#read 4, iclass 22, count 0 2006.190.08:14:21.05#ibcon#about to read 5, iclass 22, count 0 2006.190.08:14:21.05#ibcon#read 5, iclass 22, count 0 2006.190.08:14:21.05#ibcon#about to read 6, iclass 22, count 0 2006.190.08:14:21.05#ibcon#read 6, iclass 22, count 0 2006.190.08:14:21.05#ibcon#end of sib2, iclass 22, count 0 2006.190.08:14:21.05#ibcon#*after write, iclass 22, count 0 2006.190.08:14:21.05#ibcon#*before return 0, iclass 22, count 0 2006.190.08:14:21.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:21.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:14:21.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:14:21.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:14:21.05$vc4f8/vb=2,4 2006.190.08:14:21.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.08:14:21.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.08:14:21.05#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:21.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:21.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:21.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:21.11#ibcon#enter wrdev, iclass 24, count 2 2006.190.08:14:21.11#ibcon#first serial, iclass 24, count 2 2006.190.08:14:21.11#ibcon#enter sib2, iclass 24, count 2 2006.190.08:14:21.11#ibcon#flushed, iclass 24, count 2 2006.190.08:14:21.11#ibcon#about to write, iclass 24, count 2 2006.190.08:14:21.11#ibcon#wrote, iclass 24, count 2 2006.190.08:14:21.11#ibcon#about to read 3, iclass 24, count 2 2006.190.08:14:21.13#ibcon#read 3, iclass 24, count 2 2006.190.08:14:21.13#ibcon#about to read 4, iclass 24, count 2 2006.190.08:14:21.13#ibcon#read 4, iclass 24, count 2 2006.190.08:14:21.13#ibcon#about to read 5, iclass 24, count 2 2006.190.08:14:21.13#ibcon#read 5, iclass 24, count 2 2006.190.08:14:21.13#ibcon#about to read 6, iclass 24, count 2 2006.190.08:14:21.13#ibcon#read 6, iclass 24, count 2 2006.190.08:14:21.13#ibcon#end of sib2, iclass 24, count 2 2006.190.08:14:21.13#ibcon#*mode == 0, iclass 24, count 2 2006.190.08:14:21.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.08:14:21.13#ibcon#[27=AT02-04\r\n] 2006.190.08:14:21.13#ibcon#*before write, iclass 24, count 2 2006.190.08:14:21.13#ibcon#enter sib2, iclass 24, count 2 2006.190.08:14:21.13#ibcon#flushed, iclass 24, count 2 2006.190.08:14:21.13#ibcon#about to write, iclass 24, count 2 2006.190.08:14:21.13#ibcon#wrote, iclass 24, count 2 2006.190.08:14:21.13#ibcon#about to read 3, iclass 24, count 2 2006.190.08:14:21.16#ibcon#read 3, iclass 24, count 2 2006.190.08:14:21.16#ibcon#about to read 4, iclass 24, count 2 2006.190.08:14:21.16#ibcon#read 4, iclass 24, count 2 2006.190.08:14:21.16#ibcon#about to read 5, iclass 24, count 2 2006.190.08:14:21.16#ibcon#read 5, iclass 24, count 2 2006.190.08:14:21.16#ibcon#about to read 6, iclass 24, count 2 2006.190.08:14:21.16#ibcon#read 6, iclass 24, count 2 2006.190.08:14:21.16#ibcon#end of sib2, iclass 24, count 2 2006.190.08:14:21.16#ibcon#*after write, iclass 24, count 2 2006.190.08:14:21.16#ibcon#*before return 0, iclass 24, count 2 2006.190.08:14:21.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:21.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:14:21.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.08:14:21.16#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:21.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:21.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:21.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:21.28#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:14:21.28#ibcon#first serial, iclass 24, count 0 2006.190.08:14:21.28#ibcon#enter sib2, iclass 24, count 0 2006.190.08:14:21.28#ibcon#flushed, iclass 24, count 0 2006.190.08:14:21.28#ibcon#about to write, iclass 24, count 0 2006.190.08:14:21.28#ibcon#wrote, iclass 24, count 0 2006.190.08:14:21.28#ibcon#about to read 3, iclass 24, count 0 2006.190.08:14:21.30#ibcon#read 3, iclass 24, count 0 2006.190.08:14:21.30#ibcon#about to read 4, iclass 24, count 0 2006.190.08:14:21.30#ibcon#read 4, iclass 24, count 0 2006.190.08:14:21.30#ibcon#about to read 5, iclass 24, count 0 2006.190.08:14:21.30#ibcon#read 5, iclass 24, count 0 2006.190.08:14:21.30#ibcon#about to read 6, iclass 24, count 0 2006.190.08:14:21.30#ibcon#read 6, iclass 24, count 0 2006.190.08:14:21.30#ibcon#end of sib2, iclass 24, count 0 2006.190.08:14:21.30#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:14:21.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:14:21.30#ibcon#[27=USB\r\n] 2006.190.08:14:21.30#ibcon#*before write, iclass 24, count 0 2006.190.08:14:21.30#ibcon#enter sib2, iclass 24, count 0 2006.190.08:14:21.30#ibcon#flushed, iclass 24, count 0 2006.190.08:14:21.30#ibcon#about to write, iclass 24, count 0 2006.190.08:14:21.30#ibcon#wrote, iclass 24, count 0 2006.190.08:14:21.30#ibcon#about to read 3, iclass 24, count 0 2006.190.08:14:21.33#ibcon#read 3, iclass 24, count 0 2006.190.08:14:21.33#ibcon#about to read 4, iclass 24, count 0 2006.190.08:14:21.33#ibcon#read 4, iclass 24, count 0 2006.190.08:14:21.33#ibcon#about to read 5, iclass 24, count 0 2006.190.08:14:21.33#ibcon#read 5, iclass 24, count 0 2006.190.08:14:21.33#ibcon#about to read 6, iclass 24, count 0 2006.190.08:14:21.33#ibcon#read 6, iclass 24, count 0 2006.190.08:14:21.33#ibcon#end of sib2, iclass 24, count 0 2006.190.08:14:21.33#ibcon#*after write, iclass 24, count 0 2006.190.08:14:21.33#ibcon#*before return 0, iclass 24, count 0 2006.190.08:14:21.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:21.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:14:21.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:14:21.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:14:21.33$vc4f8/vblo=3,656.99 2006.190.08:14:21.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.08:14:21.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.08:14:21.33#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:21.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:21.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:21.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:21.33#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:14:21.33#ibcon#first serial, iclass 26, count 0 2006.190.08:14:21.33#ibcon#enter sib2, iclass 26, count 0 2006.190.08:14:21.33#ibcon#flushed, iclass 26, count 0 2006.190.08:14:21.33#ibcon#about to write, iclass 26, count 0 2006.190.08:14:21.33#ibcon#wrote, iclass 26, count 0 2006.190.08:14:21.33#ibcon#about to read 3, iclass 26, count 0 2006.190.08:14:21.35#ibcon#read 3, iclass 26, count 0 2006.190.08:14:21.35#ibcon#about to read 4, iclass 26, count 0 2006.190.08:14:21.35#ibcon#read 4, iclass 26, count 0 2006.190.08:14:21.35#ibcon#about to read 5, iclass 26, count 0 2006.190.08:14:21.35#ibcon#read 5, iclass 26, count 0 2006.190.08:14:21.35#ibcon#about to read 6, iclass 26, count 0 2006.190.08:14:21.35#ibcon#read 6, iclass 26, count 0 2006.190.08:14:21.35#ibcon#end of sib2, iclass 26, count 0 2006.190.08:14:21.35#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:14:21.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:14:21.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:14:21.35#ibcon#*before write, iclass 26, count 0 2006.190.08:14:21.35#ibcon#enter sib2, iclass 26, count 0 2006.190.08:14:21.35#ibcon#flushed, iclass 26, count 0 2006.190.08:14:21.35#ibcon#about to write, iclass 26, count 0 2006.190.08:14:21.35#ibcon#wrote, iclass 26, count 0 2006.190.08:14:21.35#ibcon#about to read 3, iclass 26, count 0 2006.190.08:14:21.39#ibcon#read 3, iclass 26, count 0 2006.190.08:14:21.39#ibcon#about to read 4, iclass 26, count 0 2006.190.08:14:21.39#ibcon#read 4, iclass 26, count 0 2006.190.08:14:21.39#ibcon#about to read 5, iclass 26, count 0 2006.190.08:14:21.39#ibcon#read 5, iclass 26, count 0 2006.190.08:14:21.39#ibcon#about to read 6, iclass 26, count 0 2006.190.08:14:21.39#ibcon#read 6, iclass 26, count 0 2006.190.08:14:21.39#ibcon#end of sib2, iclass 26, count 0 2006.190.08:14:21.39#ibcon#*after write, iclass 26, count 0 2006.190.08:14:21.39#ibcon#*before return 0, iclass 26, count 0 2006.190.08:14:21.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:21.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:14:21.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:14:21.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:14:21.39$vc4f8/vb=3,4 2006.190.08:14:21.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.08:14:21.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.08:14:21.39#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:21.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:21.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:21.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:21.45#ibcon#enter wrdev, iclass 28, count 2 2006.190.08:14:21.45#ibcon#first serial, iclass 28, count 2 2006.190.08:14:21.45#ibcon#enter sib2, iclass 28, count 2 2006.190.08:14:21.45#ibcon#flushed, iclass 28, count 2 2006.190.08:14:21.45#ibcon#about to write, iclass 28, count 2 2006.190.08:14:21.45#ibcon#wrote, iclass 28, count 2 2006.190.08:14:21.45#ibcon#about to read 3, iclass 28, count 2 2006.190.08:14:21.47#ibcon#read 3, iclass 28, count 2 2006.190.08:14:21.47#ibcon#about to read 4, iclass 28, count 2 2006.190.08:14:21.47#ibcon#read 4, iclass 28, count 2 2006.190.08:14:21.47#ibcon#about to read 5, iclass 28, count 2 2006.190.08:14:21.47#ibcon#read 5, iclass 28, count 2 2006.190.08:14:21.47#ibcon#about to read 6, iclass 28, count 2 2006.190.08:14:21.47#ibcon#read 6, iclass 28, count 2 2006.190.08:14:21.47#ibcon#end of sib2, iclass 28, count 2 2006.190.08:14:21.47#ibcon#*mode == 0, iclass 28, count 2 2006.190.08:14:21.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.08:14:21.47#ibcon#[27=AT03-04\r\n] 2006.190.08:14:21.47#ibcon#*before write, iclass 28, count 2 2006.190.08:14:21.47#ibcon#enter sib2, iclass 28, count 2 2006.190.08:14:21.47#ibcon#flushed, iclass 28, count 2 2006.190.08:14:21.47#ibcon#about to write, iclass 28, count 2 2006.190.08:14:21.47#ibcon#wrote, iclass 28, count 2 2006.190.08:14:21.47#ibcon#about to read 3, iclass 28, count 2 2006.190.08:14:21.50#ibcon#read 3, iclass 28, count 2 2006.190.08:14:21.50#ibcon#about to read 4, iclass 28, count 2 2006.190.08:14:21.50#ibcon#read 4, iclass 28, count 2 2006.190.08:14:21.50#ibcon#about to read 5, iclass 28, count 2 2006.190.08:14:21.50#ibcon#read 5, iclass 28, count 2 2006.190.08:14:21.50#ibcon#about to read 6, iclass 28, count 2 2006.190.08:14:21.50#ibcon#read 6, iclass 28, count 2 2006.190.08:14:21.50#ibcon#end of sib2, iclass 28, count 2 2006.190.08:14:21.50#ibcon#*after write, iclass 28, count 2 2006.190.08:14:21.50#ibcon#*before return 0, iclass 28, count 2 2006.190.08:14:21.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:21.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:14:21.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.08:14:21.50#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:21.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:21.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:21.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:21.62#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:14:21.62#ibcon#first serial, iclass 28, count 0 2006.190.08:14:21.62#ibcon#enter sib2, iclass 28, count 0 2006.190.08:14:21.62#ibcon#flushed, iclass 28, count 0 2006.190.08:14:21.62#ibcon#about to write, iclass 28, count 0 2006.190.08:14:21.62#ibcon#wrote, iclass 28, count 0 2006.190.08:14:21.62#ibcon#about to read 3, iclass 28, count 0 2006.190.08:14:21.64#ibcon#read 3, iclass 28, count 0 2006.190.08:14:21.64#ibcon#about to read 4, iclass 28, count 0 2006.190.08:14:21.64#ibcon#read 4, iclass 28, count 0 2006.190.08:14:21.64#ibcon#about to read 5, iclass 28, count 0 2006.190.08:14:21.64#ibcon#read 5, iclass 28, count 0 2006.190.08:14:21.64#ibcon#about to read 6, iclass 28, count 0 2006.190.08:14:21.64#ibcon#read 6, iclass 28, count 0 2006.190.08:14:21.64#ibcon#end of sib2, iclass 28, count 0 2006.190.08:14:21.64#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:14:21.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:14:21.64#ibcon#[27=USB\r\n] 2006.190.08:14:21.64#ibcon#*before write, iclass 28, count 0 2006.190.08:14:21.64#ibcon#enter sib2, iclass 28, count 0 2006.190.08:14:21.64#ibcon#flushed, iclass 28, count 0 2006.190.08:14:21.64#ibcon#about to write, iclass 28, count 0 2006.190.08:14:21.64#ibcon#wrote, iclass 28, count 0 2006.190.08:14:21.64#ibcon#about to read 3, iclass 28, count 0 2006.190.08:14:21.67#ibcon#read 3, iclass 28, count 0 2006.190.08:14:21.67#ibcon#about to read 4, iclass 28, count 0 2006.190.08:14:21.67#ibcon#read 4, iclass 28, count 0 2006.190.08:14:21.67#ibcon#about to read 5, iclass 28, count 0 2006.190.08:14:21.67#ibcon#read 5, iclass 28, count 0 2006.190.08:14:21.67#ibcon#about to read 6, iclass 28, count 0 2006.190.08:14:21.67#ibcon#read 6, iclass 28, count 0 2006.190.08:14:21.67#ibcon#end of sib2, iclass 28, count 0 2006.190.08:14:21.67#ibcon#*after write, iclass 28, count 0 2006.190.08:14:21.67#ibcon#*before return 0, iclass 28, count 0 2006.190.08:14:21.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:21.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:14:21.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:14:21.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:14:21.67$vc4f8/vblo=4,712.99 2006.190.08:14:21.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.08:14:21.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.08:14:21.67#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:21.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:21.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:21.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:21.67#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:14:21.67#ibcon#first serial, iclass 30, count 0 2006.190.08:14:21.67#ibcon#enter sib2, iclass 30, count 0 2006.190.08:14:21.67#ibcon#flushed, iclass 30, count 0 2006.190.08:14:21.67#ibcon#about to write, iclass 30, count 0 2006.190.08:14:21.67#ibcon#wrote, iclass 30, count 0 2006.190.08:14:21.67#ibcon#about to read 3, iclass 30, count 0 2006.190.08:14:21.69#ibcon#read 3, iclass 30, count 0 2006.190.08:14:21.69#ibcon#about to read 4, iclass 30, count 0 2006.190.08:14:21.69#ibcon#read 4, iclass 30, count 0 2006.190.08:14:21.69#ibcon#about to read 5, iclass 30, count 0 2006.190.08:14:21.69#ibcon#read 5, iclass 30, count 0 2006.190.08:14:21.69#ibcon#about to read 6, iclass 30, count 0 2006.190.08:14:21.69#ibcon#read 6, iclass 30, count 0 2006.190.08:14:21.69#ibcon#end of sib2, iclass 30, count 0 2006.190.08:14:21.69#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:14:21.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:14:21.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:14:21.69#ibcon#*before write, iclass 30, count 0 2006.190.08:14:21.69#ibcon#enter sib2, iclass 30, count 0 2006.190.08:14:21.69#ibcon#flushed, iclass 30, count 0 2006.190.08:14:21.69#ibcon#about to write, iclass 30, count 0 2006.190.08:14:21.69#ibcon#wrote, iclass 30, count 0 2006.190.08:14:21.69#ibcon#about to read 3, iclass 30, count 0 2006.190.08:14:21.73#ibcon#read 3, iclass 30, count 0 2006.190.08:14:21.73#ibcon#about to read 4, iclass 30, count 0 2006.190.08:14:21.73#ibcon#read 4, iclass 30, count 0 2006.190.08:14:21.73#ibcon#about to read 5, iclass 30, count 0 2006.190.08:14:21.73#ibcon#read 5, iclass 30, count 0 2006.190.08:14:21.73#ibcon#about to read 6, iclass 30, count 0 2006.190.08:14:21.73#ibcon#read 6, iclass 30, count 0 2006.190.08:14:21.73#ibcon#end of sib2, iclass 30, count 0 2006.190.08:14:21.73#ibcon#*after write, iclass 30, count 0 2006.190.08:14:21.73#ibcon#*before return 0, iclass 30, count 0 2006.190.08:14:21.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:21.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:14:21.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:14:21.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:14:21.73$vc4f8/vb=4,4 2006.190.08:14:21.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.08:14:21.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.08:14:21.73#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:21.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:21.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:21.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:21.79#ibcon#enter wrdev, iclass 32, count 2 2006.190.08:14:21.79#ibcon#first serial, iclass 32, count 2 2006.190.08:14:21.79#ibcon#enter sib2, iclass 32, count 2 2006.190.08:14:21.79#ibcon#flushed, iclass 32, count 2 2006.190.08:14:21.79#ibcon#about to write, iclass 32, count 2 2006.190.08:14:21.79#ibcon#wrote, iclass 32, count 2 2006.190.08:14:21.79#ibcon#about to read 3, iclass 32, count 2 2006.190.08:14:21.81#ibcon#read 3, iclass 32, count 2 2006.190.08:14:21.81#ibcon#about to read 4, iclass 32, count 2 2006.190.08:14:21.81#ibcon#read 4, iclass 32, count 2 2006.190.08:14:21.81#ibcon#about to read 5, iclass 32, count 2 2006.190.08:14:21.81#ibcon#read 5, iclass 32, count 2 2006.190.08:14:21.81#ibcon#about to read 6, iclass 32, count 2 2006.190.08:14:21.81#ibcon#read 6, iclass 32, count 2 2006.190.08:14:21.81#ibcon#end of sib2, iclass 32, count 2 2006.190.08:14:21.81#ibcon#*mode == 0, iclass 32, count 2 2006.190.08:14:21.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.08:14:21.81#ibcon#[27=AT04-04\r\n] 2006.190.08:14:21.81#ibcon#*before write, iclass 32, count 2 2006.190.08:14:21.81#ibcon#enter sib2, iclass 32, count 2 2006.190.08:14:21.81#ibcon#flushed, iclass 32, count 2 2006.190.08:14:21.81#ibcon#about to write, iclass 32, count 2 2006.190.08:14:21.81#ibcon#wrote, iclass 32, count 2 2006.190.08:14:21.81#ibcon#about to read 3, iclass 32, count 2 2006.190.08:14:21.84#ibcon#read 3, iclass 32, count 2 2006.190.08:14:21.84#ibcon#about to read 4, iclass 32, count 2 2006.190.08:14:21.84#ibcon#read 4, iclass 32, count 2 2006.190.08:14:21.84#ibcon#about to read 5, iclass 32, count 2 2006.190.08:14:21.84#ibcon#read 5, iclass 32, count 2 2006.190.08:14:21.84#ibcon#about to read 6, iclass 32, count 2 2006.190.08:14:21.84#ibcon#read 6, iclass 32, count 2 2006.190.08:14:21.84#ibcon#end of sib2, iclass 32, count 2 2006.190.08:14:21.84#ibcon#*after write, iclass 32, count 2 2006.190.08:14:21.84#ibcon#*before return 0, iclass 32, count 2 2006.190.08:14:21.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:21.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:14:21.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.08:14:21.84#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:21.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:21.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:21.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:21.96#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:14:21.96#ibcon#first serial, iclass 32, count 0 2006.190.08:14:21.96#ibcon#enter sib2, iclass 32, count 0 2006.190.08:14:21.96#ibcon#flushed, iclass 32, count 0 2006.190.08:14:21.96#ibcon#about to write, iclass 32, count 0 2006.190.08:14:21.96#ibcon#wrote, iclass 32, count 0 2006.190.08:14:21.96#ibcon#about to read 3, iclass 32, count 0 2006.190.08:14:21.98#ibcon#read 3, iclass 32, count 0 2006.190.08:14:21.98#ibcon#about to read 4, iclass 32, count 0 2006.190.08:14:21.98#ibcon#read 4, iclass 32, count 0 2006.190.08:14:21.98#ibcon#about to read 5, iclass 32, count 0 2006.190.08:14:21.98#ibcon#read 5, iclass 32, count 0 2006.190.08:14:21.98#ibcon#about to read 6, iclass 32, count 0 2006.190.08:14:21.98#ibcon#read 6, iclass 32, count 0 2006.190.08:14:21.98#ibcon#end of sib2, iclass 32, count 0 2006.190.08:14:21.98#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:14:21.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:14:21.98#ibcon#[27=USB\r\n] 2006.190.08:14:21.98#ibcon#*before write, iclass 32, count 0 2006.190.08:14:21.98#ibcon#enter sib2, iclass 32, count 0 2006.190.08:14:21.98#ibcon#flushed, iclass 32, count 0 2006.190.08:14:21.98#ibcon#about to write, iclass 32, count 0 2006.190.08:14:21.98#ibcon#wrote, iclass 32, count 0 2006.190.08:14:21.98#ibcon#about to read 3, iclass 32, count 0 2006.190.08:14:22.01#ibcon#read 3, iclass 32, count 0 2006.190.08:14:22.01#ibcon#about to read 4, iclass 32, count 0 2006.190.08:14:22.01#ibcon#read 4, iclass 32, count 0 2006.190.08:14:22.01#ibcon#about to read 5, iclass 32, count 0 2006.190.08:14:22.01#ibcon#read 5, iclass 32, count 0 2006.190.08:14:22.01#ibcon#about to read 6, iclass 32, count 0 2006.190.08:14:22.01#ibcon#read 6, iclass 32, count 0 2006.190.08:14:22.01#ibcon#end of sib2, iclass 32, count 0 2006.190.08:14:22.01#ibcon#*after write, iclass 32, count 0 2006.190.08:14:22.01#ibcon#*before return 0, iclass 32, count 0 2006.190.08:14:22.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:22.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:14:22.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:14:22.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:14:22.01$vc4f8/vblo=5,744.99 2006.190.08:14:22.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.08:14:22.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.08:14:22.01#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:22.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:22.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:22.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:22.01#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:14:22.01#ibcon#first serial, iclass 34, count 0 2006.190.08:14:22.01#ibcon#enter sib2, iclass 34, count 0 2006.190.08:14:22.01#ibcon#flushed, iclass 34, count 0 2006.190.08:14:22.01#ibcon#about to write, iclass 34, count 0 2006.190.08:14:22.01#ibcon#wrote, iclass 34, count 0 2006.190.08:14:22.01#ibcon#about to read 3, iclass 34, count 0 2006.190.08:14:22.03#ibcon#read 3, iclass 34, count 0 2006.190.08:14:22.03#ibcon#about to read 4, iclass 34, count 0 2006.190.08:14:22.03#ibcon#read 4, iclass 34, count 0 2006.190.08:14:22.03#ibcon#about to read 5, iclass 34, count 0 2006.190.08:14:22.03#ibcon#read 5, iclass 34, count 0 2006.190.08:14:22.03#ibcon#about to read 6, iclass 34, count 0 2006.190.08:14:22.03#ibcon#read 6, iclass 34, count 0 2006.190.08:14:22.03#ibcon#end of sib2, iclass 34, count 0 2006.190.08:14:22.03#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:14:22.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:14:22.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:14:22.03#ibcon#*before write, iclass 34, count 0 2006.190.08:14:22.03#ibcon#enter sib2, iclass 34, count 0 2006.190.08:14:22.03#ibcon#flushed, iclass 34, count 0 2006.190.08:14:22.03#ibcon#about to write, iclass 34, count 0 2006.190.08:14:22.03#ibcon#wrote, iclass 34, count 0 2006.190.08:14:22.03#ibcon#about to read 3, iclass 34, count 0 2006.190.08:14:22.07#ibcon#read 3, iclass 34, count 0 2006.190.08:14:22.07#ibcon#about to read 4, iclass 34, count 0 2006.190.08:14:22.07#ibcon#read 4, iclass 34, count 0 2006.190.08:14:22.07#ibcon#about to read 5, iclass 34, count 0 2006.190.08:14:22.07#ibcon#read 5, iclass 34, count 0 2006.190.08:14:22.07#ibcon#about to read 6, iclass 34, count 0 2006.190.08:14:22.07#ibcon#read 6, iclass 34, count 0 2006.190.08:14:22.07#ibcon#end of sib2, iclass 34, count 0 2006.190.08:14:22.07#ibcon#*after write, iclass 34, count 0 2006.190.08:14:22.07#ibcon#*before return 0, iclass 34, count 0 2006.190.08:14:22.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:22.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:14:22.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:14:22.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:14:22.07$vc4f8/vb=5,4 2006.190.08:14:22.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.08:14:22.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.08:14:22.07#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:22.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:22.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:22.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:22.13#ibcon#enter wrdev, iclass 36, count 2 2006.190.08:14:22.13#ibcon#first serial, iclass 36, count 2 2006.190.08:14:22.13#ibcon#enter sib2, iclass 36, count 2 2006.190.08:14:22.13#ibcon#flushed, iclass 36, count 2 2006.190.08:14:22.13#ibcon#about to write, iclass 36, count 2 2006.190.08:14:22.13#ibcon#wrote, iclass 36, count 2 2006.190.08:14:22.13#ibcon#about to read 3, iclass 36, count 2 2006.190.08:14:22.15#ibcon#read 3, iclass 36, count 2 2006.190.08:14:22.15#ibcon#about to read 4, iclass 36, count 2 2006.190.08:14:22.15#ibcon#read 4, iclass 36, count 2 2006.190.08:14:22.15#ibcon#about to read 5, iclass 36, count 2 2006.190.08:14:22.15#ibcon#read 5, iclass 36, count 2 2006.190.08:14:22.15#ibcon#about to read 6, iclass 36, count 2 2006.190.08:14:22.15#ibcon#read 6, iclass 36, count 2 2006.190.08:14:22.15#ibcon#end of sib2, iclass 36, count 2 2006.190.08:14:22.15#ibcon#*mode == 0, iclass 36, count 2 2006.190.08:14:22.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.08:14:22.15#ibcon#[27=AT05-04\r\n] 2006.190.08:14:22.15#ibcon#*before write, iclass 36, count 2 2006.190.08:14:22.15#ibcon#enter sib2, iclass 36, count 2 2006.190.08:14:22.15#ibcon#flushed, iclass 36, count 2 2006.190.08:14:22.15#ibcon#about to write, iclass 36, count 2 2006.190.08:14:22.15#ibcon#wrote, iclass 36, count 2 2006.190.08:14:22.15#ibcon#about to read 3, iclass 36, count 2 2006.190.08:14:22.18#ibcon#read 3, iclass 36, count 2 2006.190.08:14:22.18#ibcon#about to read 4, iclass 36, count 2 2006.190.08:14:22.18#ibcon#read 4, iclass 36, count 2 2006.190.08:14:22.18#ibcon#about to read 5, iclass 36, count 2 2006.190.08:14:22.18#ibcon#read 5, iclass 36, count 2 2006.190.08:14:22.18#ibcon#about to read 6, iclass 36, count 2 2006.190.08:14:22.18#ibcon#read 6, iclass 36, count 2 2006.190.08:14:22.18#ibcon#end of sib2, iclass 36, count 2 2006.190.08:14:22.18#ibcon#*after write, iclass 36, count 2 2006.190.08:14:22.18#ibcon#*before return 0, iclass 36, count 2 2006.190.08:14:22.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:22.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:14:22.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.08:14:22.18#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:22.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:22.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:22.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:22.30#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:14:22.30#ibcon#first serial, iclass 36, count 0 2006.190.08:14:22.30#ibcon#enter sib2, iclass 36, count 0 2006.190.08:14:22.30#ibcon#flushed, iclass 36, count 0 2006.190.08:14:22.30#ibcon#about to write, iclass 36, count 0 2006.190.08:14:22.30#ibcon#wrote, iclass 36, count 0 2006.190.08:14:22.30#ibcon#about to read 3, iclass 36, count 0 2006.190.08:14:22.32#ibcon#read 3, iclass 36, count 0 2006.190.08:14:22.32#ibcon#about to read 4, iclass 36, count 0 2006.190.08:14:22.32#ibcon#read 4, iclass 36, count 0 2006.190.08:14:22.32#ibcon#about to read 5, iclass 36, count 0 2006.190.08:14:22.32#ibcon#read 5, iclass 36, count 0 2006.190.08:14:22.32#ibcon#about to read 6, iclass 36, count 0 2006.190.08:14:22.32#ibcon#read 6, iclass 36, count 0 2006.190.08:14:22.32#ibcon#end of sib2, iclass 36, count 0 2006.190.08:14:22.32#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:14:22.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:14:22.32#ibcon#[27=USB\r\n] 2006.190.08:14:22.32#ibcon#*before write, iclass 36, count 0 2006.190.08:14:22.32#ibcon#enter sib2, iclass 36, count 0 2006.190.08:14:22.32#ibcon#flushed, iclass 36, count 0 2006.190.08:14:22.32#ibcon#about to write, iclass 36, count 0 2006.190.08:14:22.32#ibcon#wrote, iclass 36, count 0 2006.190.08:14:22.32#ibcon#about to read 3, iclass 36, count 0 2006.190.08:14:22.35#ibcon#read 3, iclass 36, count 0 2006.190.08:14:22.35#ibcon#about to read 4, iclass 36, count 0 2006.190.08:14:22.35#ibcon#read 4, iclass 36, count 0 2006.190.08:14:22.35#ibcon#about to read 5, iclass 36, count 0 2006.190.08:14:22.35#ibcon#read 5, iclass 36, count 0 2006.190.08:14:22.35#ibcon#about to read 6, iclass 36, count 0 2006.190.08:14:22.35#ibcon#read 6, iclass 36, count 0 2006.190.08:14:22.35#ibcon#end of sib2, iclass 36, count 0 2006.190.08:14:22.35#ibcon#*after write, iclass 36, count 0 2006.190.08:14:22.35#ibcon#*before return 0, iclass 36, count 0 2006.190.08:14:22.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:22.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:14:22.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:14:22.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:14:22.35$vc4f8/vblo=6,752.99 2006.190.08:14:22.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.08:14:22.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.08:14:22.35#ibcon#ireg 17 cls_cnt 0 2006.190.08:14:22.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:22.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:22.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:22.35#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:14:22.35#ibcon#first serial, iclass 38, count 0 2006.190.08:14:22.35#ibcon#enter sib2, iclass 38, count 0 2006.190.08:14:22.35#ibcon#flushed, iclass 38, count 0 2006.190.08:14:22.35#ibcon#about to write, iclass 38, count 0 2006.190.08:14:22.35#ibcon#wrote, iclass 38, count 0 2006.190.08:14:22.35#ibcon#about to read 3, iclass 38, count 0 2006.190.08:14:22.37#ibcon#read 3, iclass 38, count 0 2006.190.08:14:22.37#ibcon#about to read 4, iclass 38, count 0 2006.190.08:14:22.37#ibcon#read 4, iclass 38, count 0 2006.190.08:14:22.37#ibcon#about to read 5, iclass 38, count 0 2006.190.08:14:22.37#ibcon#read 5, iclass 38, count 0 2006.190.08:14:22.37#ibcon#about to read 6, iclass 38, count 0 2006.190.08:14:22.37#ibcon#read 6, iclass 38, count 0 2006.190.08:14:22.37#ibcon#end of sib2, iclass 38, count 0 2006.190.08:14:22.37#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:14:22.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:14:22.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:14:22.37#ibcon#*before write, iclass 38, count 0 2006.190.08:14:22.37#ibcon#enter sib2, iclass 38, count 0 2006.190.08:14:22.37#ibcon#flushed, iclass 38, count 0 2006.190.08:14:22.37#ibcon#about to write, iclass 38, count 0 2006.190.08:14:22.37#ibcon#wrote, iclass 38, count 0 2006.190.08:14:22.37#ibcon#about to read 3, iclass 38, count 0 2006.190.08:14:22.41#ibcon#read 3, iclass 38, count 0 2006.190.08:14:22.41#ibcon#about to read 4, iclass 38, count 0 2006.190.08:14:22.41#ibcon#read 4, iclass 38, count 0 2006.190.08:14:22.41#ibcon#about to read 5, iclass 38, count 0 2006.190.08:14:22.41#ibcon#read 5, iclass 38, count 0 2006.190.08:14:22.41#ibcon#about to read 6, iclass 38, count 0 2006.190.08:14:22.41#ibcon#read 6, iclass 38, count 0 2006.190.08:14:22.41#ibcon#end of sib2, iclass 38, count 0 2006.190.08:14:22.41#ibcon#*after write, iclass 38, count 0 2006.190.08:14:22.41#ibcon#*before return 0, iclass 38, count 0 2006.190.08:14:22.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:22.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:14:22.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:14:22.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:14:22.41$vc4f8/vb=6,4 2006.190.08:14:22.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.08:14:22.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.08:14:22.41#ibcon#ireg 11 cls_cnt 2 2006.190.08:14:22.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:22.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:22.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:22.47#ibcon#enter wrdev, iclass 40, count 2 2006.190.08:14:22.47#ibcon#first serial, iclass 40, count 2 2006.190.08:14:22.47#ibcon#enter sib2, iclass 40, count 2 2006.190.08:14:22.47#ibcon#flushed, iclass 40, count 2 2006.190.08:14:22.47#ibcon#about to write, iclass 40, count 2 2006.190.08:14:22.47#ibcon#wrote, iclass 40, count 2 2006.190.08:14:22.47#ibcon#about to read 3, iclass 40, count 2 2006.190.08:14:22.49#ibcon#read 3, iclass 40, count 2 2006.190.08:14:22.49#ibcon#about to read 4, iclass 40, count 2 2006.190.08:14:22.49#ibcon#read 4, iclass 40, count 2 2006.190.08:14:22.49#ibcon#about to read 5, iclass 40, count 2 2006.190.08:14:22.49#ibcon#read 5, iclass 40, count 2 2006.190.08:14:22.49#ibcon#about to read 6, iclass 40, count 2 2006.190.08:14:22.49#ibcon#read 6, iclass 40, count 2 2006.190.08:14:22.49#ibcon#end of sib2, iclass 40, count 2 2006.190.08:14:22.49#ibcon#*mode == 0, iclass 40, count 2 2006.190.08:14:22.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.08:14:22.49#ibcon#[27=AT06-04\r\n] 2006.190.08:14:22.49#ibcon#*before write, iclass 40, count 2 2006.190.08:14:22.49#ibcon#enter sib2, iclass 40, count 2 2006.190.08:14:22.49#ibcon#flushed, iclass 40, count 2 2006.190.08:14:22.49#ibcon#about to write, iclass 40, count 2 2006.190.08:14:22.49#ibcon#wrote, iclass 40, count 2 2006.190.08:14:22.49#ibcon#about to read 3, iclass 40, count 2 2006.190.08:14:22.52#ibcon#read 3, iclass 40, count 2 2006.190.08:14:22.52#ibcon#about to read 4, iclass 40, count 2 2006.190.08:14:22.52#ibcon#read 4, iclass 40, count 2 2006.190.08:14:22.52#ibcon#about to read 5, iclass 40, count 2 2006.190.08:14:22.52#ibcon#read 5, iclass 40, count 2 2006.190.08:14:22.52#ibcon#about to read 6, iclass 40, count 2 2006.190.08:14:22.52#ibcon#read 6, iclass 40, count 2 2006.190.08:14:22.52#ibcon#end of sib2, iclass 40, count 2 2006.190.08:14:22.52#ibcon#*after write, iclass 40, count 2 2006.190.08:14:22.52#ibcon#*before return 0, iclass 40, count 2 2006.190.08:14:22.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:22.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:14:22.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.08:14:22.52#ibcon#ireg 7 cls_cnt 0 2006.190.08:14:22.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:22.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:22.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:22.64#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:14:22.64#ibcon#first serial, iclass 40, count 0 2006.190.08:14:22.64#ibcon#enter sib2, iclass 40, count 0 2006.190.08:14:22.64#ibcon#flushed, iclass 40, count 0 2006.190.08:14:22.64#ibcon#about to write, iclass 40, count 0 2006.190.08:14:22.64#ibcon#wrote, iclass 40, count 0 2006.190.08:14:22.64#ibcon#about to read 3, iclass 40, count 0 2006.190.08:14:22.66#ibcon#read 3, iclass 40, count 0 2006.190.08:14:22.66#ibcon#about to read 4, iclass 40, count 0 2006.190.08:14:22.66#ibcon#read 4, iclass 40, count 0 2006.190.08:14:22.66#ibcon#about to read 5, iclass 40, count 0 2006.190.08:14:22.66#ibcon#read 5, iclass 40, count 0 2006.190.08:14:22.66#ibcon#about to read 6, iclass 40, count 0 2006.190.08:14:22.66#ibcon#read 6, iclass 40, count 0 2006.190.08:14:22.66#ibcon#end of sib2, iclass 40, count 0 2006.190.08:14:22.66#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:14:22.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:14:22.66#ibcon#[27=USB\r\n] 2006.190.08:14:22.66#ibcon#*before write, iclass 40, count 0 2006.190.08:14:22.66#ibcon#enter sib2, iclass 40, count 0 2006.190.08:14:22.66#ibcon#flushed, iclass 40, count 0 2006.190.08:14:22.66#ibcon#about to write, iclass 40, count 0 2006.190.08:14:22.66#ibcon#wrote, iclass 40, count 0 2006.190.08:14:22.66#ibcon#about to read 3, iclass 40, count 0 2006.190.08:14:22.69#ibcon#read 3, iclass 40, count 0 2006.190.08:14:22.69#ibcon#about to read 4, iclass 40, count 0 2006.190.08:14:22.69#ibcon#read 4, iclass 40, count 0 2006.190.08:14:22.69#ibcon#about to read 5, iclass 40, count 0 2006.190.08:14:22.69#ibcon#read 5, iclass 40, count 0 2006.190.08:14:22.69#ibcon#about to read 6, iclass 40, count 0 2006.190.08:14:22.69#ibcon#read 6, iclass 40, count 0 2006.190.08:14:22.69#ibcon#end of sib2, iclass 40, count 0 2006.190.08:14:22.69#ibcon#*after write, iclass 40, count 0 2006.190.08:14:22.69#ibcon#*before return 0, iclass 40, count 0 2006.190.08:14:22.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:22.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:14:22.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:14:22.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:14:22.69$vc4f8/vabw=wide 2006.190.08:14:22.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.08:14:22.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.08:14:22.69#ibcon#ireg 8 cls_cnt 0 2006.190.08:14:22.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:22.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:22.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:22.69#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:14:22.69#ibcon#first serial, iclass 4, count 0 2006.190.08:14:22.69#ibcon#enter sib2, iclass 4, count 0 2006.190.08:14:22.69#ibcon#flushed, iclass 4, count 0 2006.190.08:14:22.69#ibcon#about to write, iclass 4, count 0 2006.190.08:14:22.69#ibcon#wrote, iclass 4, count 0 2006.190.08:14:22.69#ibcon#about to read 3, iclass 4, count 0 2006.190.08:14:22.71#ibcon#read 3, iclass 4, count 0 2006.190.08:14:22.71#ibcon#about to read 4, iclass 4, count 0 2006.190.08:14:22.71#ibcon#read 4, iclass 4, count 0 2006.190.08:14:22.71#ibcon#about to read 5, iclass 4, count 0 2006.190.08:14:22.71#ibcon#read 5, iclass 4, count 0 2006.190.08:14:22.71#ibcon#about to read 6, iclass 4, count 0 2006.190.08:14:22.71#ibcon#read 6, iclass 4, count 0 2006.190.08:14:22.71#ibcon#end of sib2, iclass 4, count 0 2006.190.08:14:22.71#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:14:22.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:14:22.71#ibcon#[25=BW32\r\n] 2006.190.08:14:22.71#ibcon#*before write, iclass 4, count 0 2006.190.08:14:22.71#ibcon#enter sib2, iclass 4, count 0 2006.190.08:14:22.71#ibcon#flushed, iclass 4, count 0 2006.190.08:14:22.71#ibcon#about to write, iclass 4, count 0 2006.190.08:14:22.71#ibcon#wrote, iclass 4, count 0 2006.190.08:14:22.71#ibcon#about to read 3, iclass 4, count 0 2006.190.08:14:22.74#ibcon#read 3, iclass 4, count 0 2006.190.08:14:22.74#ibcon#about to read 4, iclass 4, count 0 2006.190.08:14:22.74#ibcon#read 4, iclass 4, count 0 2006.190.08:14:22.74#ibcon#about to read 5, iclass 4, count 0 2006.190.08:14:22.74#ibcon#read 5, iclass 4, count 0 2006.190.08:14:22.74#ibcon#about to read 6, iclass 4, count 0 2006.190.08:14:22.74#ibcon#read 6, iclass 4, count 0 2006.190.08:14:22.74#ibcon#end of sib2, iclass 4, count 0 2006.190.08:14:22.74#ibcon#*after write, iclass 4, count 0 2006.190.08:14:22.74#ibcon#*before return 0, iclass 4, count 0 2006.190.08:14:22.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:22.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:14:22.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:14:22.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:14:22.74$vc4f8/vbbw=wide 2006.190.08:14:22.74#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:14:22.74#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:14:22.74#ibcon#ireg 8 cls_cnt 0 2006.190.08:14:22.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:14:22.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:14:22.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:14:22.81#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:14:22.81#ibcon#first serial, iclass 6, count 0 2006.190.08:14:22.81#ibcon#enter sib2, iclass 6, count 0 2006.190.08:14:22.81#ibcon#flushed, iclass 6, count 0 2006.190.08:14:22.81#ibcon#about to write, iclass 6, count 0 2006.190.08:14:22.81#ibcon#wrote, iclass 6, count 0 2006.190.08:14:22.81#ibcon#about to read 3, iclass 6, count 0 2006.190.08:14:22.83#ibcon#read 3, iclass 6, count 0 2006.190.08:14:22.83#ibcon#about to read 4, iclass 6, count 0 2006.190.08:14:22.83#ibcon#read 4, iclass 6, count 0 2006.190.08:14:22.83#ibcon#about to read 5, iclass 6, count 0 2006.190.08:14:22.83#ibcon#read 5, iclass 6, count 0 2006.190.08:14:22.83#ibcon#about to read 6, iclass 6, count 0 2006.190.08:14:22.83#ibcon#read 6, iclass 6, count 0 2006.190.08:14:22.83#ibcon#end of sib2, iclass 6, count 0 2006.190.08:14:22.83#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:14:22.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:14:22.83#ibcon#[27=BW32\r\n] 2006.190.08:14:22.83#ibcon#*before write, iclass 6, count 0 2006.190.08:14:22.83#ibcon#enter sib2, iclass 6, count 0 2006.190.08:14:22.83#ibcon#flushed, iclass 6, count 0 2006.190.08:14:22.83#ibcon#about to write, iclass 6, count 0 2006.190.08:14:22.83#ibcon#wrote, iclass 6, count 0 2006.190.08:14:22.83#ibcon#about to read 3, iclass 6, count 0 2006.190.08:14:22.86#ibcon#read 3, iclass 6, count 0 2006.190.08:14:22.86#ibcon#about to read 4, iclass 6, count 0 2006.190.08:14:22.86#ibcon#read 4, iclass 6, count 0 2006.190.08:14:22.86#ibcon#about to read 5, iclass 6, count 0 2006.190.08:14:22.86#ibcon#read 5, iclass 6, count 0 2006.190.08:14:22.86#ibcon#about to read 6, iclass 6, count 0 2006.190.08:14:22.86#ibcon#read 6, iclass 6, count 0 2006.190.08:14:22.86#ibcon#end of sib2, iclass 6, count 0 2006.190.08:14:22.86#ibcon#*after write, iclass 6, count 0 2006.190.08:14:22.86#ibcon#*before return 0, iclass 6, count 0 2006.190.08:14:22.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:14:22.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:14:22.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:14:22.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:14:22.86$4f8m12a/ifd4f 2006.190.08:14:22.86$ifd4f/lo= 2006.190.08:14:22.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:14:22.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:14:22.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:14:22.86$ifd4f/patch= 2006.190.08:14:22.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:14:22.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:14:22.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:14:22.86$4f8m12a/"form=m,16.000,1:2 2006.190.08:14:22.86$4f8m12a/"tpicd 2006.190.08:14:22.86$4f8m12a/echo=off 2006.190.08:14:22.86$4f8m12a/xlog=off 2006.190.08:14:22.86:!2006.190.08:14:50 2006.190.08:14:34.14#trakl#Source acquired 2006.190.08:14:35.14#flagr#flagr/antenna,acquired 2006.190.08:14:50.00:preob 2006.190.08:14:51.14/onsource/TRACKING 2006.190.08:14:51.14:!2006.190.08:15:00 2006.190.08:15:00.00:data_valid=on 2006.190.08:15:00.00:midob 2006.190.08:15:00.14/onsource/TRACKING 2006.190.08:15:00.14/wx/24.40,1012.1,100 2006.190.08:15:00.36/cable/+6.4700E-03 2006.190.08:15:01.45/va/01,08,usb,yes,30,32 2006.190.08:15:01.45/va/02,07,usb,yes,31,32 2006.190.08:15:01.45/va/03,06,usb,yes,32,32 2006.190.08:15:01.45/va/04,07,usb,yes,32,34 2006.190.08:15:01.45/va/05,07,usb,yes,34,36 2006.190.08:15:01.45/va/06,06,usb,yes,33,33 2006.190.08:15:01.45/va/07,06,usb,yes,34,34 2006.190.08:15:01.45/va/08,06,usb,yes,36,36 2006.190.08:15:01.68/valo/01,532.99,yes,locked 2006.190.08:15:01.68/valo/02,572.99,yes,locked 2006.190.08:15:01.68/valo/03,672.99,yes,locked 2006.190.08:15:01.68/valo/04,832.99,yes,locked 2006.190.08:15:01.68/valo/05,652.99,yes,locked 2006.190.08:15:01.68/valo/06,772.99,yes,locked 2006.190.08:15:01.68/valo/07,832.99,yes,locked 2006.190.08:15:01.68/valo/08,852.99,yes,locked 2006.190.08:15:02.77/vb/01,04,usb,yes,29,27 2006.190.08:15:02.77/vb/02,04,usb,yes,30,32 2006.190.08:15:02.77/vb/03,04,usb,yes,27,30 2006.190.08:15:02.77/vb/04,04,usb,yes,28,28 2006.190.08:15:02.77/vb/05,04,usb,yes,26,30 2006.190.08:15:02.77/vb/06,04,usb,yes,27,30 2006.190.08:15:02.77/vb/07,04,usb,yes,29,29 2006.190.08:15:02.77/vb/08,04,usb,yes,27,30 2006.190.08:15:03.00/vblo/01,632.99,yes,locked 2006.190.08:15:03.00/vblo/02,640.99,yes,locked 2006.190.08:15:03.00/vblo/03,656.99,yes,locked 2006.190.08:15:03.00/vblo/04,712.99,yes,locked 2006.190.08:15:03.00/vblo/05,744.99,yes,locked 2006.190.08:15:03.00/vblo/06,752.99,yes,locked 2006.190.08:15:03.00/vblo/07,734.99,yes,locked 2006.190.08:15:03.00/vblo/08,744.99,yes,locked 2006.190.08:15:03.15/vabw/8 2006.190.08:15:03.30/vbbw/8 2006.190.08:15:03.39/xfe/off,on,15.0 2006.190.08:15:03.78/ifatt/23,28,28,28 2006.190.08:15:04.07/fmout-gps/S +2.85E-07 2006.190.08:15:04.15:!2006.190.08:16:00 2006.190.08:16:00.01:data_valid=off 2006.190.08:16:00.01:postob 2006.190.08:16:00.22/cable/+6.4713E-03 2006.190.08:16:00.22/wx/24.41,1012.1,100 2006.190.08:16:01.07/fmout-gps/S +2.85E-07 2006.190.08:16:01.07:scan_name=190-0816,k06190,60 2006.190.08:16:01.08:source=1300+580,130252.47,574837.6,2000.0,neutral 2006.190.08:16:01.14#flagr#flagr/antenna,new-source 2006.190.08:16:02.14:checkk5 2006.190.08:16:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:16:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:16:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:16:03.68/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:16:04.05/chk_obsdata//k5ts1/T1900815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:16:04.43/chk_obsdata//k5ts2/T1900815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:16:04.80/chk_obsdata//k5ts3/T1900815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:16:05.18/chk_obsdata//k5ts4/T1900815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:16:05.89/k5log//k5ts1_log_newline 2006.190.08:16:06.60/k5log//k5ts2_log_newline 2006.190.08:16:07.31/k5log//k5ts3_log_newline 2006.190.08:16:08.01/k5log//k5ts4_log_newline 2006.190.08:16:08.03/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:16:08.03:4f8m12a=2 2006.190.08:16:08.03$4f8m12a/echo=on 2006.190.08:16:08.03$4f8m12a/pcalon 2006.190.08:16:08.03$pcalon/"no phase cal control is implemented here 2006.190.08:16:08.03$4f8m12a/"tpicd=stop 2006.190.08:16:08.03$4f8m12a/vc4f8 2006.190.08:16:08.03$vc4f8/valo=1,532.99 2006.190.08:16:08.04#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.190.08:16:08.04#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.190.08:16:08.04#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:08.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:16:08.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:16:08.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:16:08.04#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:16:08.04#ibcon#first serial, iclass 10, count 0 2006.190.08:16:08.04#ibcon#enter sib2, iclass 10, count 0 2006.190.08:16:08.04#ibcon#flushed, iclass 10, count 0 2006.190.08:16:08.04#ibcon#about to write, iclass 10, count 0 2006.190.08:16:08.04#ibcon#wrote, iclass 10, count 0 2006.190.08:16:08.04#ibcon#about to read 3, iclass 10, count 0 2006.190.08:16:08.05#ibcon#read 3, iclass 10, count 0 2006.190.08:16:08.05#ibcon#about to read 4, iclass 10, count 0 2006.190.08:16:08.05#ibcon#read 4, iclass 10, count 0 2006.190.08:16:08.05#ibcon#about to read 5, iclass 10, count 0 2006.190.08:16:08.05#ibcon#read 5, iclass 10, count 0 2006.190.08:16:08.05#ibcon#about to read 6, iclass 10, count 0 2006.190.08:16:08.05#ibcon#read 6, iclass 10, count 0 2006.190.08:16:08.05#ibcon#end of sib2, iclass 10, count 0 2006.190.08:16:08.05#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:16:08.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:16:08.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:16:08.05#ibcon#*before write, iclass 10, count 0 2006.190.08:16:08.05#ibcon#enter sib2, iclass 10, count 0 2006.190.08:16:08.05#ibcon#flushed, iclass 10, count 0 2006.190.08:16:08.05#ibcon#about to write, iclass 10, count 0 2006.190.08:16:08.05#ibcon#wrote, iclass 10, count 0 2006.190.08:16:08.05#ibcon#about to read 3, iclass 10, count 0 2006.190.08:16:08.10#ibcon#read 3, iclass 10, count 0 2006.190.08:16:08.11#ibcon#about to read 4, iclass 10, count 0 2006.190.08:16:08.11#ibcon#read 4, iclass 10, count 0 2006.190.08:16:08.11#ibcon#about to read 5, iclass 10, count 0 2006.190.08:16:08.11#ibcon#read 5, iclass 10, count 0 2006.190.08:16:08.11#ibcon#about to read 6, iclass 10, count 0 2006.190.08:16:08.11#ibcon#read 6, iclass 10, count 0 2006.190.08:16:08.11#ibcon#end of sib2, iclass 10, count 0 2006.190.08:16:08.11#ibcon#*after write, iclass 10, count 0 2006.190.08:16:08.11#ibcon#*before return 0, iclass 10, count 0 2006.190.08:16:08.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:16:08.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.190.08:16:08.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:16:08.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:16:08.11$vc4f8/va=1,8 2006.190.08:16:08.11#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.190.08:16:08.11#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.190.08:16:08.11#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:08.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:16:08.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:16:08.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:16:08.11#ibcon#enter wrdev, iclass 12, count 2 2006.190.08:16:08.11#ibcon#first serial, iclass 12, count 2 2006.190.08:16:08.11#ibcon#enter sib2, iclass 12, count 2 2006.190.08:16:08.11#ibcon#flushed, iclass 12, count 2 2006.190.08:16:08.11#ibcon#about to write, iclass 12, count 2 2006.190.08:16:08.11#ibcon#wrote, iclass 12, count 2 2006.190.08:16:08.11#ibcon#about to read 3, iclass 12, count 2 2006.190.08:16:08.12#ibcon#read 3, iclass 12, count 2 2006.190.08:16:08.12#ibcon#about to read 4, iclass 12, count 2 2006.190.08:16:08.12#ibcon#read 4, iclass 12, count 2 2006.190.08:16:08.12#ibcon#about to read 5, iclass 12, count 2 2006.190.08:16:08.12#ibcon#read 5, iclass 12, count 2 2006.190.08:16:08.12#ibcon#about to read 6, iclass 12, count 2 2006.190.08:16:08.12#ibcon#read 6, iclass 12, count 2 2006.190.08:16:08.12#ibcon#end of sib2, iclass 12, count 2 2006.190.08:16:08.12#ibcon#*mode == 0, iclass 12, count 2 2006.190.08:16:08.12#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.190.08:16:08.12#ibcon#[25=AT01-08\r\n] 2006.190.08:16:08.12#ibcon#*before write, iclass 12, count 2 2006.190.08:16:08.12#ibcon#enter sib2, iclass 12, count 2 2006.190.08:16:08.12#ibcon#flushed, iclass 12, count 2 2006.190.08:16:08.12#ibcon#about to write, iclass 12, count 2 2006.190.08:16:08.12#ibcon#wrote, iclass 12, count 2 2006.190.08:16:08.12#ibcon#about to read 3, iclass 12, count 2 2006.190.08:16:08.15#ibcon#read 3, iclass 12, count 2 2006.190.08:16:08.15#ibcon#about to read 4, iclass 12, count 2 2006.190.08:16:08.15#ibcon#read 4, iclass 12, count 2 2006.190.08:16:08.15#ibcon#about to read 5, iclass 12, count 2 2006.190.08:16:08.15#ibcon#read 5, iclass 12, count 2 2006.190.08:16:08.15#ibcon#about to read 6, iclass 12, count 2 2006.190.08:16:08.15#ibcon#read 6, iclass 12, count 2 2006.190.08:16:08.15#ibcon#end of sib2, iclass 12, count 2 2006.190.08:16:08.15#ibcon#*after write, iclass 12, count 2 2006.190.08:16:08.15#ibcon#*before return 0, iclass 12, count 2 2006.190.08:16:08.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:16:08.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.190.08:16:08.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.190.08:16:08.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:08.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:16:08.29#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:16:08.29#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:16:08.29#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:16:08.29#ibcon#first serial, iclass 12, count 0 2006.190.08:16:08.29#ibcon#enter sib2, iclass 12, count 0 2006.190.08:16:08.29#ibcon#flushed, iclass 12, count 0 2006.190.08:16:08.29#ibcon#about to write, iclass 12, count 0 2006.190.08:16:08.29#ibcon#wrote, iclass 12, count 0 2006.190.08:16:08.29#ibcon#about to read 3, iclass 12, count 0 2006.190.08:16:08.30#ibcon#read 3, iclass 12, count 0 2006.190.08:16:08.30#ibcon#about to read 4, iclass 12, count 0 2006.190.08:16:08.30#ibcon#read 4, iclass 12, count 0 2006.190.08:16:08.30#ibcon#about to read 5, iclass 12, count 0 2006.190.08:16:08.30#ibcon#read 5, iclass 12, count 0 2006.190.08:16:08.30#ibcon#about to read 6, iclass 12, count 0 2006.190.08:16:08.30#ibcon#read 6, iclass 12, count 0 2006.190.08:16:08.30#ibcon#end of sib2, iclass 12, count 0 2006.190.08:16:08.30#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:16:08.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:16:08.30#ibcon#[25=USB\r\n] 2006.190.08:16:08.30#ibcon#*before write, iclass 12, count 0 2006.190.08:16:08.30#ibcon#enter sib2, iclass 12, count 0 2006.190.08:16:08.30#ibcon#flushed, iclass 12, count 0 2006.190.08:16:08.30#ibcon#about to write, iclass 12, count 0 2006.190.08:16:08.30#ibcon#wrote, iclass 12, count 0 2006.190.08:16:08.30#ibcon#about to read 3, iclass 12, count 0 2006.190.08:16:08.33#ibcon#read 3, iclass 12, count 0 2006.190.08:16:08.33#ibcon#about to read 4, iclass 12, count 0 2006.190.08:16:08.33#ibcon#read 4, iclass 12, count 0 2006.190.08:16:08.33#ibcon#about to read 5, iclass 12, count 0 2006.190.08:16:08.33#ibcon#read 5, iclass 12, count 0 2006.190.08:16:08.33#ibcon#about to read 6, iclass 12, count 0 2006.190.08:16:08.33#ibcon#read 6, iclass 12, count 0 2006.190.08:16:08.33#ibcon#end of sib2, iclass 12, count 0 2006.190.08:16:08.33#ibcon#*after write, iclass 12, count 0 2006.190.08:16:08.33#ibcon#*before return 0, iclass 12, count 0 2006.190.08:16:08.33#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:16:08.33#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.190.08:16:08.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:16:08.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:16:08.33$vc4f8/valo=2,572.99 2006.190.08:16:08.33#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.08:16:08.33#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.08:16:08.33#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:08.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:08.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:08.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:08.33#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:16:08.33#ibcon#first serial, iclass 14, count 0 2006.190.08:16:08.33#ibcon#enter sib2, iclass 14, count 0 2006.190.08:16:08.33#ibcon#flushed, iclass 14, count 0 2006.190.08:16:08.33#ibcon#about to write, iclass 14, count 0 2006.190.08:16:08.33#ibcon#wrote, iclass 14, count 0 2006.190.08:16:08.33#ibcon#about to read 3, iclass 14, count 0 2006.190.08:16:08.35#ibcon#read 3, iclass 14, count 0 2006.190.08:16:08.35#ibcon#about to read 4, iclass 14, count 0 2006.190.08:16:08.35#ibcon#read 4, iclass 14, count 0 2006.190.08:16:08.35#ibcon#about to read 5, iclass 14, count 0 2006.190.08:16:08.35#ibcon#read 5, iclass 14, count 0 2006.190.08:16:08.35#ibcon#about to read 6, iclass 14, count 0 2006.190.08:16:08.35#ibcon#read 6, iclass 14, count 0 2006.190.08:16:08.35#ibcon#end of sib2, iclass 14, count 0 2006.190.08:16:08.35#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:16:08.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:16:08.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:16:08.35#ibcon#*before write, iclass 14, count 0 2006.190.08:16:08.35#ibcon#enter sib2, iclass 14, count 0 2006.190.08:16:08.35#ibcon#flushed, iclass 14, count 0 2006.190.08:16:08.35#ibcon#about to write, iclass 14, count 0 2006.190.08:16:08.35#ibcon#wrote, iclass 14, count 0 2006.190.08:16:08.35#ibcon#about to read 3, iclass 14, count 0 2006.190.08:16:08.39#ibcon#read 3, iclass 14, count 0 2006.190.08:16:08.39#ibcon#about to read 4, iclass 14, count 0 2006.190.08:16:08.39#ibcon#read 4, iclass 14, count 0 2006.190.08:16:08.39#ibcon#about to read 5, iclass 14, count 0 2006.190.08:16:08.39#ibcon#read 5, iclass 14, count 0 2006.190.08:16:08.39#ibcon#about to read 6, iclass 14, count 0 2006.190.08:16:08.39#ibcon#read 6, iclass 14, count 0 2006.190.08:16:08.39#ibcon#end of sib2, iclass 14, count 0 2006.190.08:16:08.39#ibcon#*after write, iclass 14, count 0 2006.190.08:16:08.39#ibcon#*before return 0, iclass 14, count 0 2006.190.08:16:08.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:08.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:08.39#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:16:08.39#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:16:08.39$vc4f8/va=2,7 2006.190.08:16:08.39#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.08:16:08.39#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.08:16:08.39#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:08.39#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:08.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:08.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:08.45#ibcon#enter wrdev, iclass 16, count 2 2006.190.08:16:08.45#ibcon#first serial, iclass 16, count 2 2006.190.08:16:08.45#ibcon#enter sib2, iclass 16, count 2 2006.190.08:16:08.45#ibcon#flushed, iclass 16, count 2 2006.190.08:16:08.45#ibcon#about to write, iclass 16, count 2 2006.190.08:16:08.45#ibcon#wrote, iclass 16, count 2 2006.190.08:16:08.45#ibcon#about to read 3, iclass 16, count 2 2006.190.08:16:08.48#ibcon#read 3, iclass 16, count 2 2006.190.08:16:08.48#ibcon#about to read 4, iclass 16, count 2 2006.190.08:16:08.48#ibcon#read 4, iclass 16, count 2 2006.190.08:16:08.48#ibcon#about to read 5, iclass 16, count 2 2006.190.08:16:08.48#ibcon#read 5, iclass 16, count 2 2006.190.08:16:08.48#ibcon#about to read 6, iclass 16, count 2 2006.190.08:16:08.48#ibcon#read 6, iclass 16, count 2 2006.190.08:16:08.48#ibcon#end of sib2, iclass 16, count 2 2006.190.08:16:08.48#ibcon#*mode == 0, iclass 16, count 2 2006.190.08:16:08.48#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.08:16:08.48#ibcon#[25=AT02-07\r\n] 2006.190.08:16:08.48#ibcon#*before write, iclass 16, count 2 2006.190.08:16:08.48#ibcon#enter sib2, iclass 16, count 2 2006.190.08:16:08.48#ibcon#flushed, iclass 16, count 2 2006.190.08:16:08.48#ibcon#about to write, iclass 16, count 2 2006.190.08:16:08.48#ibcon#wrote, iclass 16, count 2 2006.190.08:16:08.48#ibcon#about to read 3, iclass 16, count 2 2006.190.08:16:08.51#ibcon#read 3, iclass 16, count 2 2006.190.08:16:08.51#ibcon#about to read 4, iclass 16, count 2 2006.190.08:16:08.51#ibcon#read 4, iclass 16, count 2 2006.190.08:16:08.51#ibcon#about to read 5, iclass 16, count 2 2006.190.08:16:08.51#ibcon#read 5, iclass 16, count 2 2006.190.08:16:08.51#ibcon#about to read 6, iclass 16, count 2 2006.190.08:16:08.51#ibcon#read 6, iclass 16, count 2 2006.190.08:16:08.51#ibcon#end of sib2, iclass 16, count 2 2006.190.08:16:08.51#ibcon#*after write, iclass 16, count 2 2006.190.08:16:08.51#ibcon#*before return 0, iclass 16, count 2 2006.190.08:16:08.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:08.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:08.51#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.08:16:08.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:08.51#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:08.63#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:08.63#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:08.63#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:16:08.63#ibcon#first serial, iclass 16, count 0 2006.190.08:16:08.63#ibcon#enter sib2, iclass 16, count 0 2006.190.08:16:08.63#ibcon#flushed, iclass 16, count 0 2006.190.08:16:08.63#ibcon#about to write, iclass 16, count 0 2006.190.08:16:08.63#ibcon#wrote, iclass 16, count 0 2006.190.08:16:08.63#ibcon#about to read 3, iclass 16, count 0 2006.190.08:16:08.65#ibcon#read 3, iclass 16, count 0 2006.190.08:16:08.65#ibcon#about to read 4, iclass 16, count 0 2006.190.08:16:08.65#ibcon#read 4, iclass 16, count 0 2006.190.08:16:08.65#ibcon#about to read 5, iclass 16, count 0 2006.190.08:16:08.65#ibcon#read 5, iclass 16, count 0 2006.190.08:16:08.65#ibcon#about to read 6, iclass 16, count 0 2006.190.08:16:08.65#ibcon#read 6, iclass 16, count 0 2006.190.08:16:08.65#ibcon#end of sib2, iclass 16, count 0 2006.190.08:16:08.65#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:16:08.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:16:08.65#ibcon#[25=USB\r\n] 2006.190.08:16:08.65#ibcon#*before write, iclass 16, count 0 2006.190.08:16:08.65#ibcon#enter sib2, iclass 16, count 0 2006.190.08:16:08.65#ibcon#flushed, iclass 16, count 0 2006.190.08:16:08.65#ibcon#about to write, iclass 16, count 0 2006.190.08:16:08.65#ibcon#wrote, iclass 16, count 0 2006.190.08:16:08.65#ibcon#about to read 3, iclass 16, count 0 2006.190.08:16:08.68#ibcon#read 3, iclass 16, count 0 2006.190.08:16:08.68#ibcon#about to read 4, iclass 16, count 0 2006.190.08:16:08.68#ibcon#read 4, iclass 16, count 0 2006.190.08:16:08.68#ibcon#about to read 5, iclass 16, count 0 2006.190.08:16:08.68#ibcon#read 5, iclass 16, count 0 2006.190.08:16:08.68#ibcon#about to read 6, iclass 16, count 0 2006.190.08:16:08.68#ibcon#read 6, iclass 16, count 0 2006.190.08:16:08.68#ibcon#end of sib2, iclass 16, count 0 2006.190.08:16:08.68#ibcon#*after write, iclass 16, count 0 2006.190.08:16:08.68#ibcon#*before return 0, iclass 16, count 0 2006.190.08:16:08.68#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:08.68#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:08.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:16:08.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:16:08.68$vc4f8/valo=3,672.99 2006.190.08:16:08.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.08:16:08.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.08:16:08.68#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:08.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:08.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:08.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:08.68#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:16:08.68#ibcon#first serial, iclass 18, count 0 2006.190.08:16:08.68#ibcon#enter sib2, iclass 18, count 0 2006.190.08:16:08.68#ibcon#flushed, iclass 18, count 0 2006.190.08:16:08.68#ibcon#about to write, iclass 18, count 0 2006.190.08:16:08.68#ibcon#wrote, iclass 18, count 0 2006.190.08:16:08.68#ibcon#about to read 3, iclass 18, count 0 2006.190.08:16:08.70#ibcon#read 3, iclass 18, count 0 2006.190.08:16:08.70#ibcon#about to read 4, iclass 18, count 0 2006.190.08:16:08.70#ibcon#read 4, iclass 18, count 0 2006.190.08:16:08.70#ibcon#about to read 5, iclass 18, count 0 2006.190.08:16:08.70#ibcon#read 5, iclass 18, count 0 2006.190.08:16:08.70#ibcon#about to read 6, iclass 18, count 0 2006.190.08:16:08.70#ibcon#read 6, iclass 18, count 0 2006.190.08:16:08.70#ibcon#end of sib2, iclass 18, count 0 2006.190.08:16:08.70#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:16:08.70#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:16:08.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:16:08.70#ibcon#*before write, iclass 18, count 0 2006.190.08:16:08.70#ibcon#enter sib2, iclass 18, count 0 2006.190.08:16:08.70#ibcon#flushed, iclass 18, count 0 2006.190.08:16:08.70#ibcon#about to write, iclass 18, count 0 2006.190.08:16:08.70#ibcon#wrote, iclass 18, count 0 2006.190.08:16:08.70#ibcon#about to read 3, iclass 18, count 0 2006.190.08:16:08.74#ibcon#read 3, iclass 18, count 0 2006.190.08:16:08.74#ibcon#about to read 4, iclass 18, count 0 2006.190.08:16:08.74#ibcon#read 4, iclass 18, count 0 2006.190.08:16:08.74#ibcon#about to read 5, iclass 18, count 0 2006.190.08:16:08.74#ibcon#read 5, iclass 18, count 0 2006.190.08:16:08.74#ibcon#about to read 6, iclass 18, count 0 2006.190.08:16:08.74#ibcon#read 6, iclass 18, count 0 2006.190.08:16:08.74#ibcon#end of sib2, iclass 18, count 0 2006.190.08:16:08.74#ibcon#*after write, iclass 18, count 0 2006.190.08:16:08.74#ibcon#*before return 0, iclass 18, count 0 2006.190.08:16:08.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:08.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:08.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:16:08.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:16:08.74$vc4f8/va=3,6 2006.190.08:16:08.74#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.190.08:16:08.74#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.190.08:16:08.74#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:08.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:08.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:08.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:08.80#ibcon#enter wrdev, iclass 20, count 2 2006.190.08:16:08.80#ibcon#first serial, iclass 20, count 2 2006.190.08:16:08.80#ibcon#enter sib2, iclass 20, count 2 2006.190.08:16:08.80#ibcon#flushed, iclass 20, count 2 2006.190.08:16:08.80#ibcon#about to write, iclass 20, count 2 2006.190.08:16:08.80#ibcon#wrote, iclass 20, count 2 2006.190.08:16:08.80#ibcon#about to read 3, iclass 20, count 2 2006.190.08:16:08.82#ibcon#read 3, iclass 20, count 2 2006.190.08:16:08.82#ibcon#about to read 4, iclass 20, count 2 2006.190.08:16:08.82#ibcon#read 4, iclass 20, count 2 2006.190.08:16:08.82#ibcon#about to read 5, iclass 20, count 2 2006.190.08:16:08.82#ibcon#read 5, iclass 20, count 2 2006.190.08:16:08.82#ibcon#about to read 6, iclass 20, count 2 2006.190.08:16:08.82#ibcon#read 6, iclass 20, count 2 2006.190.08:16:08.82#ibcon#end of sib2, iclass 20, count 2 2006.190.08:16:08.82#ibcon#*mode == 0, iclass 20, count 2 2006.190.08:16:08.82#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.190.08:16:08.82#ibcon#[25=AT03-06\r\n] 2006.190.08:16:08.82#ibcon#*before write, iclass 20, count 2 2006.190.08:16:08.82#ibcon#enter sib2, iclass 20, count 2 2006.190.08:16:08.82#ibcon#flushed, iclass 20, count 2 2006.190.08:16:08.82#ibcon#about to write, iclass 20, count 2 2006.190.08:16:08.82#ibcon#wrote, iclass 20, count 2 2006.190.08:16:08.82#ibcon#about to read 3, iclass 20, count 2 2006.190.08:16:08.85#ibcon#read 3, iclass 20, count 2 2006.190.08:16:08.85#ibcon#about to read 4, iclass 20, count 2 2006.190.08:16:08.85#ibcon#read 4, iclass 20, count 2 2006.190.08:16:08.85#ibcon#about to read 5, iclass 20, count 2 2006.190.08:16:08.85#ibcon#read 5, iclass 20, count 2 2006.190.08:16:08.85#ibcon#about to read 6, iclass 20, count 2 2006.190.08:16:08.85#ibcon#read 6, iclass 20, count 2 2006.190.08:16:08.85#ibcon#end of sib2, iclass 20, count 2 2006.190.08:16:08.85#ibcon#*after write, iclass 20, count 2 2006.190.08:16:08.85#ibcon#*before return 0, iclass 20, count 2 2006.190.08:16:08.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:08.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:08.85#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.190.08:16:08.85#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:08.85#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:08.97#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:08.97#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:08.97#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:16:08.97#ibcon#first serial, iclass 20, count 0 2006.190.08:16:08.97#ibcon#enter sib2, iclass 20, count 0 2006.190.08:16:08.97#ibcon#flushed, iclass 20, count 0 2006.190.08:16:08.97#ibcon#about to write, iclass 20, count 0 2006.190.08:16:08.97#ibcon#wrote, iclass 20, count 0 2006.190.08:16:08.97#ibcon#about to read 3, iclass 20, count 0 2006.190.08:16:08.99#ibcon#read 3, iclass 20, count 0 2006.190.08:16:08.99#ibcon#about to read 4, iclass 20, count 0 2006.190.08:16:08.99#ibcon#read 4, iclass 20, count 0 2006.190.08:16:08.99#ibcon#about to read 5, iclass 20, count 0 2006.190.08:16:08.99#ibcon#read 5, iclass 20, count 0 2006.190.08:16:08.99#ibcon#about to read 6, iclass 20, count 0 2006.190.08:16:08.99#ibcon#read 6, iclass 20, count 0 2006.190.08:16:08.99#ibcon#end of sib2, iclass 20, count 0 2006.190.08:16:08.99#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:16:08.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:16:08.99#ibcon#[25=USB\r\n] 2006.190.08:16:08.99#ibcon#*before write, iclass 20, count 0 2006.190.08:16:08.99#ibcon#enter sib2, iclass 20, count 0 2006.190.08:16:08.99#ibcon#flushed, iclass 20, count 0 2006.190.08:16:08.99#ibcon#about to write, iclass 20, count 0 2006.190.08:16:08.99#ibcon#wrote, iclass 20, count 0 2006.190.08:16:08.99#ibcon#about to read 3, iclass 20, count 0 2006.190.08:16:09.02#ibcon#read 3, iclass 20, count 0 2006.190.08:16:09.02#ibcon#about to read 4, iclass 20, count 0 2006.190.08:16:09.02#ibcon#read 4, iclass 20, count 0 2006.190.08:16:09.02#ibcon#about to read 5, iclass 20, count 0 2006.190.08:16:09.02#ibcon#read 5, iclass 20, count 0 2006.190.08:16:09.02#ibcon#about to read 6, iclass 20, count 0 2006.190.08:16:09.02#ibcon#read 6, iclass 20, count 0 2006.190.08:16:09.02#ibcon#end of sib2, iclass 20, count 0 2006.190.08:16:09.02#ibcon#*after write, iclass 20, count 0 2006.190.08:16:09.02#ibcon#*before return 0, iclass 20, count 0 2006.190.08:16:09.02#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:09.02#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:09.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:16:09.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:16:09.02$vc4f8/valo=4,832.99 2006.190.08:16:09.02#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.08:16:09.02#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.08:16:09.02#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:09.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:09.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:09.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:09.02#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:16:09.02#ibcon#first serial, iclass 22, count 0 2006.190.08:16:09.02#ibcon#enter sib2, iclass 22, count 0 2006.190.08:16:09.02#ibcon#flushed, iclass 22, count 0 2006.190.08:16:09.02#ibcon#about to write, iclass 22, count 0 2006.190.08:16:09.02#ibcon#wrote, iclass 22, count 0 2006.190.08:16:09.02#ibcon#about to read 3, iclass 22, count 0 2006.190.08:16:09.04#ibcon#read 3, iclass 22, count 0 2006.190.08:16:09.04#ibcon#about to read 4, iclass 22, count 0 2006.190.08:16:09.04#ibcon#read 4, iclass 22, count 0 2006.190.08:16:09.04#ibcon#about to read 5, iclass 22, count 0 2006.190.08:16:09.04#ibcon#read 5, iclass 22, count 0 2006.190.08:16:09.04#ibcon#about to read 6, iclass 22, count 0 2006.190.08:16:09.04#ibcon#read 6, iclass 22, count 0 2006.190.08:16:09.04#ibcon#end of sib2, iclass 22, count 0 2006.190.08:16:09.04#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:16:09.04#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:16:09.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:16:09.04#ibcon#*before write, iclass 22, count 0 2006.190.08:16:09.04#ibcon#enter sib2, iclass 22, count 0 2006.190.08:16:09.04#ibcon#flushed, iclass 22, count 0 2006.190.08:16:09.04#ibcon#about to write, iclass 22, count 0 2006.190.08:16:09.04#ibcon#wrote, iclass 22, count 0 2006.190.08:16:09.04#ibcon#about to read 3, iclass 22, count 0 2006.190.08:16:09.08#ibcon#read 3, iclass 22, count 0 2006.190.08:16:09.08#ibcon#about to read 4, iclass 22, count 0 2006.190.08:16:09.08#ibcon#read 4, iclass 22, count 0 2006.190.08:16:09.08#ibcon#about to read 5, iclass 22, count 0 2006.190.08:16:09.08#ibcon#read 5, iclass 22, count 0 2006.190.08:16:09.08#ibcon#about to read 6, iclass 22, count 0 2006.190.08:16:09.08#ibcon#read 6, iclass 22, count 0 2006.190.08:16:09.08#ibcon#end of sib2, iclass 22, count 0 2006.190.08:16:09.08#ibcon#*after write, iclass 22, count 0 2006.190.08:16:09.08#ibcon#*before return 0, iclass 22, count 0 2006.190.08:16:09.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:09.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:09.08#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:16:09.08#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:16:09.08$vc4f8/va=4,7 2006.190.08:16:09.08#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.08:16:09.08#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.08:16:09.08#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:09.08#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:09.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:09.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:09.14#ibcon#enter wrdev, iclass 24, count 2 2006.190.08:16:09.14#ibcon#first serial, iclass 24, count 2 2006.190.08:16:09.14#ibcon#enter sib2, iclass 24, count 2 2006.190.08:16:09.14#ibcon#flushed, iclass 24, count 2 2006.190.08:16:09.14#ibcon#about to write, iclass 24, count 2 2006.190.08:16:09.14#ibcon#wrote, iclass 24, count 2 2006.190.08:16:09.14#ibcon#about to read 3, iclass 24, count 2 2006.190.08:16:09.16#ibcon#read 3, iclass 24, count 2 2006.190.08:16:09.16#ibcon#about to read 4, iclass 24, count 2 2006.190.08:16:09.16#ibcon#read 4, iclass 24, count 2 2006.190.08:16:09.16#ibcon#about to read 5, iclass 24, count 2 2006.190.08:16:09.16#ibcon#read 5, iclass 24, count 2 2006.190.08:16:09.16#ibcon#about to read 6, iclass 24, count 2 2006.190.08:16:09.16#ibcon#read 6, iclass 24, count 2 2006.190.08:16:09.16#ibcon#end of sib2, iclass 24, count 2 2006.190.08:16:09.16#ibcon#*mode == 0, iclass 24, count 2 2006.190.08:16:09.16#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.08:16:09.16#ibcon#[25=AT04-07\r\n] 2006.190.08:16:09.16#ibcon#*before write, iclass 24, count 2 2006.190.08:16:09.16#ibcon#enter sib2, iclass 24, count 2 2006.190.08:16:09.16#ibcon#flushed, iclass 24, count 2 2006.190.08:16:09.16#ibcon#about to write, iclass 24, count 2 2006.190.08:16:09.16#ibcon#wrote, iclass 24, count 2 2006.190.08:16:09.16#ibcon#about to read 3, iclass 24, count 2 2006.190.08:16:09.19#ibcon#read 3, iclass 24, count 2 2006.190.08:16:09.19#ibcon#about to read 4, iclass 24, count 2 2006.190.08:16:09.19#ibcon#read 4, iclass 24, count 2 2006.190.08:16:09.19#ibcon#about to read 5, iclass 24, count 2 2006.190.08:16:09.19#ibcon#read 5, iclass 24, count 2 2006.190.08:16:09.19#ibcon#about to read 6, iclass 24, count 2 2006.190.08:16:09.19#ibcon#read 6, iclass 24, count 2 2006.190.08:16:09.19#ibcon#end of sib2, iclass 24, count 2 2006.190.08:16:09.19#ibcon#*after write, iclass 24, count 2 2006.190.08:16:09.19#ibcon#*before return 0, iclass 24, count 2 2006.190.08:16:09.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:09.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:09.19#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.08:16:09.19#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:09.19#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:09.31#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:09.31#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:09.31#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:16:09.31#ibcon#first serial, iclass 24, count 0 2006.190.08:16:09.31#ibcon#enter sib2, iclass 24, count 0 2006.190.08:16:09.31#ibcon#flushed, iclass 24, count 0 2006.190.08:16:09.31#ibcon#about to write, iclass 24, count 0 2006.190.08:16:09.31#ibcon#wrote, iclass 24, count 0 2006.190.08:16:09.31#ibcon#about to read 3, iclass 24, count 0 2006.190.08:16:09.33#ibcon#read 3, iclass 24, count 0 2006.190.08:16:09.33#ibcon#about to read 4, iclass 24, count 0 2006.190.08:16:09.33#ibcon#read 4, iclass 24, count 0 2006.190.08:16:09.33#ibcon#about to read 5, iclass 24, count 0 2006.190.08:16:09.33#ibcon#read 5, iclass 24, count 0 2006.190.08:16:09.33#ibcon#about to read 6, iclass 24, count 0 2006.190.08:16:09.33#ibcon#read 6, iclass 24, count 0 2006.190.08:16:09.33#ibcon#end of sib2, iclass 24, count 0 2006.190.08:16:09.33#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:16:09.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:16:09.33#ibcon#[25=USB\r\n] 2006.190.08:16:09.33#ibcon#*before write, iclass 24, count 0 2006.190.08:16:09.33#ibcon#enter sib2, iclass 24, count 0 2006.190.08:16:09.33#ibcon#flushed, iclass 24, count 0 2006.190.08:16:09.33#ibcon#about to write, iclass 24, count 0 2006.190.08:16:09.33#ibcon#wrote, iclass 24, count 0 2006.190.08:16:09.33#ibcon#about to read 3, iclass 24, count 0 2006.190.08:16:09.36#ibcon#read 3, iclass 24, count 0 2006.190.08:16:09.36#ibcon#about to read 4, iclass 24, count 0 2006.190.08:16:09.36#ibcon#read 4, iclass 24, count 0 2006.190.08:16:09.36#ibcon#about to read 5, iclass 24, count 0 2006.190.08:16:09.36#ibcon#read 5, iclass 24, count 0 2006.190.08:16:09.36#ibcon#about to read 6, iclass 24, count 0 2006.190.08:16:09.36#ibcon#read 6, iclass 24, count 0 2006.190.08:16:09.36#ibcon#end of sib2, iclass 24, count 0 2006.190.08:16:09.36#ibcon#*after write, iclass 24, count 0 2006.190.08:16:09.36#ibcon#*before return 0, iclass 24, count 0 2006.190.08:16:09.36#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:09.36#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:09.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:16:09.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:16:09.36$vc4f8/valo=5,652.99 2006.190.08:16:09.36#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.08:16:09.36#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.08:16:09.36#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:09.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:09.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:09.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:09.36#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:16:09.36#ibcon#first serial, iclass 26, count 0 2006.190.08:16:09.36#ibcon#enter sib2, iclass 26, count 0 2006.190.08:16:09.36#ibcon#flushed, iclass 26, count 0 2006.190.08:16:09.36#ibcon#about to write, iclass 26, count 0 2006.190.08:16:09.36#ibcon#wrote, iclass 26, count 0 2006.190.08:16:09.36#ibcon#about to read 3, iclass 26, count 0 2006.190.08:16:09.38#ibcon#read 3, iclass 26, count 0 2006.190.08:16:09.38#ibcon#about to read 4, iclass 26, count 0 2006.190.08:16:09.38#ibcon#read 4, iclass 26, count 0 2006.190.08:16:09.38#ibcon#about to read 5, iclass 26, count 0 2006.190.08:16:09.38#ibcon#read 5, iclass 26, count 0 2006.190.08:16:09.38#ibcon#about to read 6, iclass 26, count 0 2006.190.08:16:09.38#ibcon#read 6, iclass 26, count 0 2006.190.08:16:09.38#ibcon#end of sib2, iclass 26, count 0 2006.190.08:16:09.38#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:16:09.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:16:09.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:16:09.38#ibcon#*before write, iclass 26, count 0 2006.190.08:16:09.38#ibcon#enter sib2, iclass 26, count 0 2006.190.08:16:09.38#ibcon#flushed, iclass 26, count 0 2006.190.08:16:09.38#ibcon#about to write, iclass 26, count 0 2006.190.08:16:09.38#ibcon#wrote, iclass 26, count 0 2006.190.08:16:09.38#ibcon#about to read 3, iclass 26, count 0 2006.190.08:16:09.42#ibcon#read 3, iclass 26, count 0 2006.190.08:16:09.42#ibcon#about to read 4, iclass 26, count 0 2006.190.08:16:09.42#ibcon#read 4, iclass 26, count 0 2006.190.08:16:09.42#ibcon#about to read 5, iclass 26, count 0 2006.190.08:16:09.42#ibcon#read 5, iclass 26, count 0 2006.190.08:16:09.42#ibcon#about to read 6, iclass 26, count 0 2006.190.08:16:09.42#ibcon#read 6, iclass 26, count 0 2006.190.08:16:09.42#ibcon#end of sib2, iclass 26, count 0 2006.190.08:16:09.42#ibcon#*after write, iclass 26, count 0 2006.190.08:16:09.42#ibcon#*before return 0, iclass 26, count 0 2006.190.08:16:09.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:09.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:09.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:16:09.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:16:09.42$vc4f8/va=5,7 2006.190.08:16:09.42#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.08:16:09.42#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.08:16:09.42#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:09.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:09.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:09.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:09.48#ibcon#enter wrdev, iclass 28, count 2 2006.190.08:16:09.48#ibcon#first serial, iclass 28, count 2 2006.190.08:16:09.48#ibcon#enter sib2, iclass 28, count 2 2006.190.08:16:09.48#ibcon#flushed, iclass 28, count 2 2006.190.08:16:09.48#ibcon#about to write, iclass 28, count 2 2006.190.08:16:09.48#ibcon#wrote, iclass 28, count 2 2006.190.08:16:09.48#ibcon#about to read 3, iclass 28, count 2 2006.190.08:16:09.50#ibcon#read 3, iclass 28, count 2 2006.190.08:16:09.50#ibcon#about to read 4, iclass 28, count 2 2006.190.08:16:09.50#ibcon#read 4, iclass 28, count 2 2006.190.08:16:09.50#ibcon#about to read 5, iclass 28, count 2 2006.190.08:16:09.50#ibcon#read 5, iclass 28, count 2 2006.190.08:16:09.50#ibcon#about to read 6, iclass 28, count 2 2006.190.08:16:09.50#ibcon#read 6, iclass 28, count 2 2006.190.08:16:09.50#ibcon#end of sib2, iclass 28, count 2 2006.190.08:16:09.50#ibcon#*mode == 0, iclass 28, count 2 2006.190.08:16:09.50#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.08:16:09.50#ibcon#[25=AT05-07\r\n] 2006.190.08:16:09.50#ibcon#*before write, iclass 28, count 2 2006.190.08:16:09.50#ibcon#enter sib2, iclass 28, count 2 2006.190.08:16:09.50#ibcon#flushed, iclass 28, count 2 2006.190.08:16:09.50#ibcon#about to write, iclass 28, count 2 2006.190.08:16:09.50#ibcon#wrote, iclass 28, count 2 2006.190.08:16:09.50#ibcon#about to read 3, iclass 28, count 2 2006.190.08:16:09.53#ibcon#read 3, iclass 28, count 2 2006.190.08:16:09.53#ibcon#about to read 4, iclass 28, count 2 2006.190.08:16:09.53#ibcon#read 4, iclass 28, count 2 2006.190.08:16:09.53#ibcon#about to read 5, iclass 28, count 2 2006.190.08:16:09.53#ibcon#read 5, iclass 28, count 2 2006.190.08:16:09.53#ibcon#about to read 6, iclass 28, count 2 2006.190.08:16:09.53#ibcon#read 6, iclass 28, count 2 2006.190.08:16:09.53#ibcon#end of sib2, iclass 28, count 2 2006.190.08:16:09.53#ibcon#*after write, iclass 28, count 2 2006.190.08:16:09.53#ibcon#*before return 0, iclass 28, count 2 2006.190.08:16:09.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:09.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:09.53#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.08:16:09.53#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:09.53#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:09.65#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:09.65#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:09.65#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:16:09.65#ibcon#first serial, iclass 28, count 0 2006.190.08:16:09.65#ibcon#enter sib2, iclass 28, count 0 2006.190.08:16:09.65#ibcon#flushed, iclass 28, count 0 2006.190.08:16:09.65#ibcon#about to write, iclass 28, count 0 2006.190.08:16:09.65#ibcon#wrote, iclass 28, count 0 2006.190.08:16:09.65#ibcon#about to read 3, iclass 28, count 0 2006.190.08:16:09.67#ibcon#read 3, iclass 28, count 0 2006.190.08:16:09.67#ibcon#about to read 4, iclass 28, count 0 2006.190.08:16:09.67#ibcon#read 4, iclass 28, count 0 2006.190.08:16:09.67#ibcon#about to read 5, iclass 28, count 0 2006.190.08:16:09.67#ibcon#read 5, iclass 28, count 0 2006.190.08:16:09.67#ibcon#about to read 6, iclass 28, count 0 2006.190.08:16:09.67#ibcon#read 6, iclass 28, count 0 2006.190.08:16:09.67#ibcon#end of sib2, iclass 28, count 0 2006.190.08:16:09.67#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:16:09.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:16:09.67#ibcon#[25=USB\r\n] 2006.190.08:16:09.67#ibcon#*before write, iclass 28, count 0 2006.190.08:16:09.67#ibcon#enter sib2, iclass 28, count 0 2006.190.08:16:09.67#ibcon#flushed, iclass 28, count 0 2006.190.08:16:09.67#ibcon#about to write, iclass 28, count 0 2006.190.08:16:09.67#ibcon#wrote, iclass 28, count 0 2006.190.08:16:09.67#ibcon#about to read 3, iclass 28, count 0 2006.190.08:16:09.70#ibcon#read 3, iclass 28, count 0 2006.190.08:16:09.70#ibcon#about to read 4, iclass 28, count 0 2006.190.08:16:09.70#ibcon#read 4, iclass 28, count 0 2006.190.08:16:09.70#ibcon#about to read 5, iclass 28, count 0 2006.190.08:16:09.70#ibcon#read 5, iclass 28, count 0 2006.190.08:16:09.70#ibcon#about to read 6, iclass 28, count 0 2006.190.08:16:09.70#ibcon#read 6, iclass 28, count 0 2006.190.08:16:09.70#ibcon#end of sib2, iclass 28, count 0 2006.190.08:16:09.70#ibcon#*after write, iclass 28, count 0 2006.190.08:16:09.70#ibcon#*before return 0, iclass 28, count 0 2006.190.08:16:09.70#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:09.70#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:09.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:16:09.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:16:09.70$vc4f8/valo=6,772.99 2006.190.08:16:09.70#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.08:16:09.70#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.08:16:09.70#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:09.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:09.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:09.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:09.70#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:16:09.70#ibcon#first serial, iclass 30, count 0 2006.190.08:16:09.70#ibcon#enter sib2, iclass 30, count 0 2006.190.08:16:09.70#ibcon#flushed, iclass 30, count 0 2006.190.08:16:09.70#ibcon#about to write, iclass 30, count 0 2006.190.08:16:09.70#ibcon#wrote, iclass 30, count 0 2006.190.08:16:09.70#ibcon#about to read 3, iclass 30, count 0 2006.190.08:16:09.72#ibcon#read 3, iclass 30, count 0 2006.190.08:16:09.72#ibcon#about to read 4, iclass 30, count 0 2006.190.08:16:09.72#ibcon#read 4, iclass 30, count 0 2006.190.08:16:09.72#ibcon#about to read 5, iclass 30, count 0 2006.190.08:16:09.72#ibcon#read 5, iclass 30, count 0 2006.190.08:16:09.72#ibcon#about to read 6, iclass 30, count 0 2006.190.08:16:09.72#ibcon#read 6, iclass 30, count 0 2006.190.08:16:09.72#ibcon#end of sib2, iclass 30, count 0 2006.190.08:16:09.72#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:16:09.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:16:09.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:16:09.72#ibcon#*before write, iclass 30, count 0 2006.190.08:16:09.72#ibcon#enter sib2, iclass 30, count 0 2006.190.08:16:09.72#ibcon#flushed, iclass 30, count 0 2006.190.08:16:09.72#ibcon#about to write, iclass 30, count 0 2006.190.08:16:09.72#ibcon#wrote, iclass 30, count 0 2006.190.08:16:09.72#ibcon#about to read 3, iclass 30, count 0 2006.190.08:16:09.76#ibcon#read 3, iclass 30, count 0 2006.190.08:16:09.76#ibcon#about to read 4, iclass 30, count 0 2006.190.08:16:09.76#ibcon#read 4, iclass 30, count 0 2006.190.08:16:09.76#ibcon#about to read 5, iclass 30, count 0 2006.190.08:16:09.76#ibcon#read 5, iclass 30, count 0 2006.190.08:16:09.76#ibcon#about to read 6, iclass 30, count 0 2006.190.08:16:09.76#ibcon#read 6, iclass 30, count 0 2006.190.08:16:09.76#ibcon#end of sib2, iclass 30, count 0 2006.190.08:16:09.76#ibcon#*after write, iclass 30, count 0 2006.190.08:16:09.76#ibcon#*before return 0, iclass 30, count 0 2006.190.08:16:09.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:09.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:09.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:16:09.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:16:09.76$vc4f8/va=6,6 2006.190.08:16:09.76#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.08:16:09.76#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.08:16:09.76#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:09.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:09.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:09.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:09.82#ibcon#enter wrdev, iclass 32, count 2 2006.190.08:16:09.82#ibcon#first serial, iclass 32, count 2 2006.190.08:16:09.82#ibcon#enter sib2, iclass 32, count 2 2006.190.08:16:09.82#ibcon#flushed, iclass 32, count 2 2006.190.08:16:09.82#ibcon#about to write, iclass 32, count 2 2006.190.08:16:09.82#ibcon#wrote, iclass 32, count 2 2006.190.08:16:09.82#ibcon#about to read 3, iclass 32, count 2 2006.190.08:16:09.84#ibcon#read 3, iclass 32, count 2 2006.190.08:16:09.84#ibcon#about to read 4, iclass 32, count 2 2006.190.08:16:09.84#ibcon#read 4, iclass 32, count 2 2006.190.08:16:09.84#ibcon#about to read 5, iclass 32, count 2 2006.190.08:16:09.84#ibcon#read 5, iclass 32, count 2 2006.190.08:16:09.84#ibcon#about to read 6, iclass 32, count 2 2006.190.08:16:09.84#ibcon#read 6, iclass 32, count 2 2006.190.08:16:09.84#ibcon#end of sib2, iclass 32, count 2 2006.190.08:16:09.84#ibcon#*mode == 0, iclass 32, count 2 2006.190.08:16:09.84#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.08:16:09.84#ibcon#[25=AT06-06\r\n] 2006.190.08:16:09.84#ibcon#*before write, iclass 32, count 2 2006.190.08:16:09.84#ibcon#enter sib2, iclass 32, count 2 2006.190.08:16:09.84#ibcon#flushed, iclass 32, count 2 2006.190.08:16:09.84#ibcon#about to write, iclass 32, count 2 2006.190.08:16:09.84#ibcon#wrote, iclass 32, count 2 2006.190.08:16:09.84#ibcon#about to read 3, iclass 32, count 2 2006.190.08:16:09.87#ibcon#read 3, iclass 32, count 2 2006.190.08:16:09.87#ibcon#about to read 4, iclass 32, count 2 2006.190.08:16:09.87#ibcon#read 4, iclass 32, count 2 2006.190.08:16:09.87#ibcon#about to read 5, iclass 32, count 2 2006.190.08:16:09.87#ibcon#read 5, iclass 32, count 2 2006.190.08:16:09.87#ibcon#about to read 6, iclass 32, count 2 2006.190.08:16:09.87#ibcon#read 6, iclass 32, count 2 2006.190.08:16:09.87#ibcon#end of sib2, iclass 32, count 2 2006.190.08:16:09.87#ibcon#*after write, iclass 32, count 2 2006.190.08:16:09.87#ibcon#*before return 0, iclass 32, count 2 2006.190.08:16:09.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:09.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:09.87#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.08:16:09.87#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:09.87#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:09.99#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:09.99#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:09.99#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:16:09.99#ibcon#first serial, iclass 32, count 0 2006.190.08:16:09.99#ibcon#enter sib2, iclass 32, count 0 2006.190.08:16:09.99#ibcon#flushed, iclass 32, count 0 2006.190.08:16:09.99#ibcon#about to write, iclass 32, count 0 2006.190.08:16:09.99#ibcon#wrote, iclass 32, count 0 2006.190.08:16:09.99#ibcon#about to read 3, iclass 32, count 0 2006.190.08:16:10.01#ibcon#read 3, iclass 32, count 0 2006.190.08:16:10.01#ibcon#about to read 4, iclass 32, count 0 2006.190.08:16:10.01#ibcon#read 4, iclass 32, count 0 2006.190.08:16:10.01#ibcon#about to read 5, iclass 32, count 0 2006.190.08:16:10.01#ibcon#read 5, iclass 32, count 0 2006.190.08:16:10.01#ibcon#about to read 6, iclass 32, count 0 2006.190.08:16:10.01#ibcon#read 6, iclass 32, count 0 2006.190.08:16:10.01#ibcon#end of sib2, iclass 32, count 0 2006.190.08:16:10.01#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:16:10.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:16:10.01#ibcon#[25=USB\r\n] 2006.190.08:16:10.01#ibcon#*before write, iclass 32, count 0 2006.190.08:16:10.01#ibcon#enter sib2, iclass 32, count 0 2006.190.08:16:10.01#ibcon#flushed, iclass 32, count 0 2006.190.08:16:10.01#ibcon#about to write, iclass 32, count 0 2006.190.08:16:10.01#ibcon#wrote, iclass 32, count 0 2006.190.08:16:10.01#ibcon#about to read 3, iclass 32, count 0 2006.190.08:16:10.04#ibcon#read 3, iclass 32, count 0 2006.190.08:16:10.04#ibcon#about to read 4, iclass 32, count 0 2006.190.08:16:10.04#ibcon#read 4, iclass 32, count 0 2006.190.08:16:10.04#ibcon#about to read 5, iclass 32, count 0 2006.190.08:16:10.04#ibcon#read 5, iclass 32, count 0 2006.190.08:16:10.04#ibcon#about to read 6, iclass 32, count 0 2006.190.08:16:10.04#ibcon#read 6, iclass 32, count 0 2006.190.08:16:10.04#ibcon#end of sib2, iclass 32, count 0 2006.190.08:16:10.04#ibcon#*after write, iclass 32, count 0 2006.190.08:16:10.04#ibcon#*before return 0, iclass 32, count 0 2006.190.08:16:10.04#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:10.04#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:10.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:16:10.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:16:10.04$vc4f8/valo=7,832.99 2006.190.08:16:10.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.08:16:10.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.08:16:10.04#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:10.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:10.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:10.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:10.04#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:16:10.04#ibcon#first serial, iclass 34, count 0 2006.190.08:16:10.04#ibcon#enter sib2, iclass 34, count 0 2006.190.08:16:10.04#ibcon#flushed, iclass 34, count 0 2006.190.08:16:10.04#ibcon#about to write, iclass 34, count 0 2006.190.08:16:10.04#ibcon#wrote, iclass 34, count 0 2006.190.08:16:10.04#ibcon#about to read 3, iclass 34, count 0 2006.190.08:16:10.06#ibcon#read 3, iclass 34, count 0 2006.190.08:16:10.06#ibcon#about to read 4, iclass 34, count 0 2006.190.08:16:10.06#ibcon#read 4, iclass 34, count 0 2006.190.08:16:10.06#ibcon#about to read 5, iclass 34, count 0 2006.190.08:16:10.06#ibcon#read 5, iclass 34, count 0 2006.190.08:16:10.06#ibcon#about to read 6, iclass 34, count 0 2006.190.08:16:10.06#ibcon#read 6, iclass 34, count 0 2006.190.08:16:10.06#ibcon#end of sib2, iclass 34, count 0 2006.190.08:16:10.06#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:16:10.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:16:10.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:16:10.06#ibcon#*before write, iclass 34, count 0 2006.190.08:16:10.06#ibcon#enter sib2, iclass 34, count 0 2006.190.08:16:10.06#ibcon#flushed, iclass 34, count 0 2006.190.08:16:10.06#ibcon#about to write, iclass 34, count 0 2006.190.08:16:10.06#ibcon#wrote, iclass 34, count 0 2006.190.08:16:10.06#ibcon#about to read 3, iclass 34, count 0 2006.190.08:16:10.10#ibcon#read 3, iclass 34, count 0 2006.190.08:16:10.10#ibcon#about to read 4, iclass 34, count 0 2006.190.08:16:10.10#ibcon#read 4, iclass 34, count 0 2006.190.08:16:10.10#ibcon#about to read 5, iclass 34, count 0 2006.190.08:16:10.10#ibcon#read 5, iclass 34, count 0 2006.190.08:16:10.10#ibcon#about to read 6, iclass 34, count 0 2006.190.08:16:10.10#ibcon#read 6, iclass 34, count 0 2006.190.08:16:10.10#ibcon#end of sib2, iclass 34, count 0 2006.190.08:16:10.10#ibcon#*after write, iclass 34, count 0 2006.190.08:16:10.10#ibcon#*before return 0, iclass 34, count 0 2006.190.08:16:10.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:10.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:10.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:16:10.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:16:10.10$vc4f8/va=7,6 2006.190.08:16:10.10#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.190.08:16:10.10#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.190.08:16:10.10#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:10.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:16:10.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:16:10.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:16:10.16#ibcon#enter wrdev, iclass 36, count 2 2006.190.08:16:10.16#ibcon#first serial, iclass 36, count 2 2006.190.08:16:10.16#ibcon#enter sib2, iclass 36, count 2 2006.190.08:16:10.16#ibcon#flushed, iclass 36, count 2 2006.190.08:16:10.16#ibcon#about to write, iclass 36, count 2 2006.190.08:16:10.16#ibcon#wrote, iclass 36, count 2 2006.190.08:16:10.16#ibcon#about to read 3, iclass 36, count 2 2006.190.08:16:10.18#ibcon#read 3, iclass 36, count 2 2006.190.08:16:10.18#ibcon#about to read 4, iclass 36, count 2 2006.190.08:16:10.18#ibcon#read 4, iclass 36, count 2 2006.190.08:16:10.18#ibcon#about to read 5, iclass 36, count 2 2006.190.08:16:10.18#ibcon#read 5, iclass 36, count 2 2006.190.08:16:10.18#ibcon#about to read 6, iclass 36, count 2 2006.190.08:16:10.18#ibcon#read 6, iclass 36, count 2 2006.190.08:16:10.18#ibcon#end of sib2, iclass 36, count 2 2006.190.08:16:10.18#ibcon#*mode == 0, iclass 36, count 2 2006.190.08:16:10.18#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.190.08:16:10.18#ibcon#[25=AT07-06\r\n] 2006.190.08:16:10.18#ibcon#*before write, iclass 36, count 2 2006.190.08:16:10.18#ibcon#enter sib2, iclass 36, count 2 2006.190.08:16:10.18#ibcon#flushed, iclass 36, count 2 2006.190.08:16:10.18#ibcon#about to write, iclass 36, count 2 2006.190.08:16:10.18#ibcon#wrote, iclass 36, count 2 2006.190.08:16:10.18#ibcon#about to read 3, iclass 36, count 2 2006.190.08:16:10.21#ibcon#read 3, iclass 36, count 2 2006.190.08:16:10.21#ibcon#about to read 4, iclass 36, count 2 2006.190.08:16:10.21#ibcon#read 4, iclass 36, count 2 2006.190.08:16:10.21#ibcon#about to read 5, iclass 36, count 2 2006.190.08:16:10.21#ibcon#read 5, iclass 36, count 2 2006.190.08:16:10.21#ibcon#about to read 6, iclass 36, count 2 2006.190.08:16:10.21#ibcon#read 6, iclass 36, count 2 2006.190.08:16:10.21#ibcon#end of sib2, iclass 36, count 2 2006.190.08:16:10.21#ibcon#*after write, iclass 36, count 2 2006.190.08:16:10.21#ibcon#*before return 0, iclass 36, count 2 2006.190.08:16:10.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:16:10.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.190.08:16:10.21#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.190.08:16:10.21#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:10.21#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:16:10.33#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:16:10.33#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:16:10.33#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:16:10.33#ibcon#first serial, iclass 36, count 0 2006.190.08:16:10.33#ibcon#enter sib2, iclass 36, count 0 2006.190.08:16:10.33#ibcon#flushed, iclass 36, count 0 2006.190.08:16:10.33#ibcon#about to write, iclass 36, count 0 2006.190.08:16:10.33#ibcon#wrote, iclass 36, count 0 2006.190.08:16:10.33#ibcon#about to read 3, iclass 36, count 0 2006.190.08:16:10.35#ibcon#read 3, iclass 36, count 0 2006.190.08:16:10.35#ibcon#about to read 4, iclass 36, count 0 2006.190.08:16:10.35#ibcon#read 4, iclass 36, count 0 2006.190.08:16:10.35#ibcon#about to read 5, iclass 36, count 0 2006.190.08:16:10.35#ibcon#read 5, iclass 36, count 0 2006.190.08:16:10.35#ibcon#about to read 6, iclass 36, count 0 2006.190.08:16:10.35#ibcon#read 6, iclass 36, count 0 2006.190.08:16:10.35#ibcon#end of sib2, iclass 36, count 0 2006.190.08:16:10.35#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:16:10.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:16:10.35#ibcon#[25=USB\r\n] 2006.190.08:16:10.35#ibcon#*before write, iclass 36, count 0 2006.190.08:16:10.35#ibcon#enter sib2, iclass 36, count 0 2006.190.08:16:10.35#ibcon#flushed, iclass 36, count 0 2006.190.08:16:10.35#ibcon#about to write, iclass 36, count 0 2006.190.08:16:10.35#ibcon#wrote, iclass 36, count 0 2006.190.08:16:10.35#ibcon#about to read 3, iclass 36, count 0 2006.190.08:16:10.38#ibcon#read 3, iclass 36, count 0 2006.190.08:16:10.38#ibcon#about to read 4, iclass 36, count 0 2006.190.08:16:10.38#ibcon#read 4, iclass 36, count 0 2006.190.08:16:10.38#ibcon#about to read 5, iclass 36, count 0 2006.190.08:16:10.38#ibcon#read 5, iclass 36, count 0 2006.190.08:16:10.38#ibcon#about to read 6, iclass 36, count 0 2006.190.08:16:10.38#ibcon#read 6, iclass 36, count 0 2006.190.08:16:10.38#ibcon#end of sib2, iclass 36, count 0 2006.190.08:16:10.38#ibcon#*after write, iclass 36, count 0 2006.190.08:16:10.38#ibcon#*before return 0, iclass 36, count 0 2006.190.08:16:10.38#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:16:10.38#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.190.08:16:10.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:16:10.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:16:10.38$vc4f8/valo=8,852.99 2006.190.08:16:10.38#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.190.08:16:10.38#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.190.08:16:10.38#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:10.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:16:10.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:16:10.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:16:10.38#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:16:10.38#ibcon#first serial, iclass 38, count 0 2006.190.08:16:10.38#ibcon#enter sib2, iclass 38, count 0 2006.190.08:16:10.38#ibcon#flushed, iclass 38, count 0 2006.190.08:16:10.38#ibcon#about to write, iclass 38, count 0 2006.190.08:16:10.38#ibcon#wrote, iclass 38, count 0 2006.190.08:16:10.38#ibcon#about to read 3, iclass 38, count 0 2006.190.08:16:10.40#ibcon#read 3, iclass 38, count 0 2006.190.08:16:10.40#ibcon#about to read 4, iclass 38, count 0 2006.190.08:16:10.40#ibcon#read 4, iclass 38, count 0 2006.190.08:16:10.40#ibcon#about to read 5, iclass 38, count 0 2006.190.08:16:10.40#ibcon#read 5, iclass 38, count 0 2006.190.08:16:10.40#ibcon#about to read 6, iclass 38, count 0 2006.190.08:16:10.40#ibcon#read 6, iclass 38, count 0 2006.190.08:16:10.40#ibcon#end of sib2, iclass 38, count 0 2006.190.08:16:10.40#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:16:10.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:16:10.40#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:16:10.40#ibcon#*before write, iclass 38, count 0 2006.190.08:16:10.40#ibcon#enter sib2, iclass 38, count 0 2006.190.08:16:10.40#ibcon#flushed, iclass 38, count 0 2006.190.08:16:10.40#ibcon#about to write, iclass 38, count 0 2006.190.08:16:10.40#ibcon#wrote, iclass 38, count 0 2006.190.08:16:10.40#ibcon#about to read 3, iclass 38, count 0 2006.190.08:16:10.44#ibcon#read 3, iclass 38, count 0 2006.190.08:16:10.44#ibcon#about to read 4, iclass 38, count 0 2006.190.08:16:10.44#ibcon#read 4, iclass 38, count 0 2006.190.08:16:10.44#ibcon#about to read 5, iclass 38, count 0 2006.190.08:16:10.44#ibcon#read 5, iclass 38, count 0 2006.190.08:16:10.44#ibcon#about to read 6, iclass 38, count 0 2006.190.08:16:10.44#ibcon#read 6, iclass 38, count 0 2006.190.08:16:10.44#ibcon#end of sib2, iclass 38, count 0 2006.190.08:16:10.44#ibcon#*after write, iclass 38, count 0 2006.190.08:16:10.44#ibcon#*before return 0, iclass 38, count 0 2006.190.08:16:10.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:16:10.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.190.08:16:10.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:16:10.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:16:10.44$vc4f8/va=8,6 2006.190.08:16:10.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.190.08:16:10.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.190.08:16:10.44#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:10.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:16:10.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:16:10.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:16:10.50#ibcon#enter wrdev, iclass 40, count 2 2006.190.08:16:10.50#ibcon#first serial, iclass 40, count 2 2006.190.08:16:10.50#ibcon#enter sib2, iclass 40, count 2 2006.190.08:16:10.50#ibcon#flushed, iclass 40, count 2 2006.190.08:16:10.50#ibcon#about to write, iclass 40, count 2 2006.190.08:16:10.50#ibcon#wrote, iclass 40, count 2 2006.190.08:16:10.50#ibcon#about to read 3, iclass 40, count 2 2006.190.08:16:10.52#ibcon#read 3, iclass 40, count 2 2006.190.08:16:10.52#ibcon#about to read 4, iclass 40, count 2 2006.190.08:16:10.52#ibcon#read 4, iclass 40, count 2 2006.190.08:16:10.52#ibcon#about to read 5, iclass 40, count 2 2006.190.08:16:10.52#ibcon#read 5, iclass 40, count 2 2006.190.08:16:10.52#ibcon#about to read 6, iclass 40, count 2 2006.190.08:16:10.52#ibcon#read 6, iclass 40, count 2 2006.190.08:16:10.52#ibcon#end of sib2, iclass 40, count 2 2006.190.08:16:10.52#ibcon#*mode == 0, iclass 40, count 2 2006.190.08:16:10.52#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.190.08:16:10.52#ibcon#[25=AT08-06\r\n] 2006.190.08:16:10.52#ibcon#*before write, iclass 40, count 2 2006.190.08:16:10.52#ibcon#enter sib2, iclass 40, count 2 2006.190.08:16:10.52#ibcon#flushed, iclass 40, count 2 2006.190.08:16:10.52#ibcon#about to write, iclass 40, count 2 2006.190.08:16:10.52#ibcon#wrote, iclass 40, count 2 2006.190.08:16:10.52#ibcon#about to read 3, iclass 40, count 2 2006.190.08:16:10.55#ibcon#read 3, iclass 40, count 2 2006.190.08:16:10.55#ibcon#about to read 4, iclass 40, count 2 2006.190.08:16:10.55#ibcon#read 4, iclass 40, count 2 2006.190.08:16:10.55#ibcon#about to read 5, iclass 40, count 2 2006.190.08:16:10.55#ibcon#read 5, iclass 40, count 2 2006.190.08:16:10.55#ibcon#about to read 6, iclass 40, count 2 2006.190.08:16:10.55#ibcon#read 6, iclass 40, count 2 2006.190.08:16:10.55#ibcon#end of sib2, iclass 40, count 2 2006.190.08:16:10.55#ibcon#*after write, iclass 40, count 2 2006.190.08:16:10.55#ibcon#*before return 0, iclass 40, count 2 2006.190.08:16:10.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:16:10.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.190.08:16:10.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.190.08:16:10.55#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:10.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:16:10.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:16:10.67#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:16:10.67#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:16:10.67#ibcon#first serial, iclass 40, count 0 2006.190.08:16:10.67#ibcon#enter sib2, iclass 40, count 0 2006.190.08:16:10.67#ibcon#flushed, iclass 40, count 0 2006.190.08:16:10.67#ibcon#about to write, iclass 40, count 0 2006.190.08:16:10.67#ibcon#wrote, iclass 40, count 0 2006.190.08:16:10.67#ibcon#about to read 3, iclass 40, count 0 2006.190.08:16:10.69#ibcon#read 3, iclass 40, count 0 2006.190.08:16:10.69#ibcon#about to read 4, iclass 40, count 0 2006.190.08:16:10.69#ibcon#read 4, iclass 40, count 0 2006.190.08:16:10.69#ibcon#about to read 5, iclass 40, count 0 2006.190.08:16:10.69#ibcon#read 5, iclass 40, count 0 2006.190.08:16:10.69#ibcon#about to read 6, iclass 40, count 0 2006.190.08:16:10.69#ibcon#read 6, iclass 40, count 0 2006.190.08:16:10.69#ibcon#end of sib2, iclass 40, count 0 2006.190.08:16:10.69#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:16:10.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:16:10.69#ibcon#[25=USB\r\n] 2006.190.08:16:10.69#ibcon#*before write, iclass 40, count 0 2006.190.08:16:10.69#ibcon#enter sib2, iclass 40, count 0 2006.190.08:16:10.69#ibcon#flushed, iclass 40, count 0 2006.190.08:16:10.69#ibcon#about to write, iclass 40, count 0 2006.190.08:16:10.69#ibcon#wrote, iclass 40, count 0 2006.190.08:16:10.69#ibcon#about to read 3, iclass 40, count 0 2006.190.08:16:10.72#ibcon#read 3, iclass 40, count 0 2006.190.08:16:10.72#ibcon#about to read 4, iclass 40, count 0 2006.190.08:16:10.72#ibcon#read 4, iclass 40, count 0 2006.190.08:16:10.72#ibcon#about to read 5, iclass 40, count 0 2006.190.08:16:10.72#ibcon#read 5, iclass 40, count 0 2006.190.08:16:10.72#ibcon#about to read 6, iclass 40, count 0 2006.190.08:16:10.72#ibcon#read 6, iclass 40, count 0 2006.190.08:16:10.72#ibcon#end of sib2, iclass 40, count 0 2006.190.08:16:10.72#ibcon#*after write, iclass 40, count 0 2006.190.08:16:10.72#ibcon#*before return 0, iclass 40, count 0 2006.190.08:16:10.72#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:16:10.72#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.190.08:16:10.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:16:10.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:16:10.72$vc4f8/vblo=1,632.99 2006.190.08:16:10.72#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.190.08:16:10.72#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.190.08:16:10.72#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:10.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:16:10.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:16:10.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:16:10.72#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:16:10.72#ibcon#first serial, iclass 4, count 0 2006.190.08:16:10.72#ibcon#enter sib2, iclass 4, count 0 2006.190.08:16:10.72#ibcon#flushed, iclass 4, count 0 2006.190.08:16:10.72#ibcon#about to write, iclass 4, count 0 2006.190.08:16:10.72#ibcon#wrote, iclass 4, count 0 2006.190.08:16:10.72#ibcon#about to read 3, iclass 4, count 0 2006.190.08:16:10.74#ibcon#read 3, iclass 4, count 0 2006.190.08:16:10.74#ibcon#about to read 4, iclass 4, count 0 2006.190.08:16:10.74#ibcon#read 4, iclass 4, count 0 2006.190.08:16:10.74#ibcon#about to read 5, iclass 4, count 0 2006.190.08:16:10.74#ibcon#read 5, iclass 4, count 0 2006.190.08:16:10.74#ibcon#about to read 6, iclass 4, count 0 2006.190.08:16:10.74#ibcon#read 6, iclass 4, count 0 2006.190.08:16:10.74#ibcon#end of sib2, iclass 4, count 0 2006.190.08:16:10.74#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:16:10.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:16:10.74#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:16:10.74#ibcon#*before write, iclass 4, count 0 2006.190.08:16:10.74#ibcon#enter sib2, iclass 4, count 0 2006.190.08:16:10.74#ibcon#flushed, iclass 4, count 0 2006.190.08:16:10.74#ibcon#about to write, iclass 4, count 0 2006.190.08:16:10.74#ibcon#wrote, iclass 4, count 0 2006.190.08:16:10.74#ibcon#about to read 3, iclass 4, count 0 2006.190.08:16:10.78#ibcon#read 3, iclass 4, count 0 2006.190.08:16:10.78#ibcon#about to read 4, iclass 4, count 0 2006.190.08:16:10.78#ibcon#read 4, iclass 4, count 0 2006.190.08:16:10.78#ibcon#about to read 5, iclass 4, count 0 2006.190.08:16:10.78#ibcon#read 5, iclass 4, count 0 2006.190.08:16:10.78#ibcon#about to read 6, iclass 4, count 0 2006.190.08:16:10.78#ibcon#read 6, iclass 4, count 0 2006.190.08:16:10.78#ibcon#end of sib2, iclass 4, count 0 2006.190.08:16:10.78#ibcon#*after write, iclass 4, count 0 2006.190.08:16:10.78#ibcon#*before return 0, iclass 4, count 0 2006.190.08:16:10.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:16:10.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.190.08:16:10.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:16:10.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:16:10.78$vc4f8/vb=1,4 2006.190.08:16:10.78#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.190.08:16:10.78#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.190.08:16:10.78#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:10.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:16:10.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:16:10.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:16:10.78#ibcon#enter wrdev, iclass 6, count 2 2006.190.08:16:10.78#ibcon#first serial, iclass 6, count 2 2006.190.08:16:10.78#ibcon#enter sib2, iclass 6, count 2 2006.190.08:16:10.78#ibcon#flushed, iclass 6, count 2 2006.190.08:16:10.78#ibcon#about to write, iclass 6, count 2 2006.190.08:16:10.78#ibcon#wrote, iclass 6, count 2 2006.190.08:16:10.78#ibcon#about to read 3, iclass 6, count 2 2006.190.08:16:10.80#ibcon#read 3, iclass 6, count 2 2006.190.08:16:10.80#ibcon#about to read 4, iclass 6, count 2 2006.190.08:16:10.80#ibcon#read 4, iclass 6, count 2 2006.190.08:16:10.80#ibcon#about to read 5, iclass 6, count 2 2006.190.08:16:10.80#ibcon#read 5, iclass 6, count 2 2006.190.08:16:10.80#ibcon#about to read 6, iclass 6, count 2 2006.190.08:16:10.80#ibcon#read 6, iclass 6, count 2 2006.190.08:16:10.80#ibcon#end of sib2, iclass 6, count 2 2006.190.08:16:10.80#ibcon#*mode == 0, iclass 6, count 2 2006.190.08:16:10.80#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.190.08:16:10.80#ibcon#[27=AT01-04\r\n] 2006.190.08:16:10.80#ibcon#*before write, iclass 6, count 2 2006.190.08:16:10.80#ibcon#enter sib2, iclass 6, count 2 2006.190.08:16:10.80#ibcon#flushed, iclass 6, count 2 2006.190.08:16:10.80#ibcon#about to write, iclass 6, count 2 2006.190.08:16:10.80#ibcon#wrote, iclass 6, count 2 2006.190.08:16:10.80#ibcon#about to read 3, iclass 6, count 2 2006.190.08:16:10.83#ibcon#read 3, iclass 6, count 2 2006.190.08:16:10.83#ibcon#about to read 4, iclass 6, count 2 2006.190.08:16:10.83#ibcon#read 4, iclass 6, count 2 2006.190.08:16:10.83#ibcon#about to read 5, iclass 6, count 2 2006.190.08:16:10.83#ibcon#read 5, iclass 6, count 2 2006.190.08:16:10.83#ibcon#about to read 6, iclass 6, count 2 2006.190.08:16:10.83#ibcon#read 6, iclass 6, count 2 2006.190.08:16:10.83#ibcon#end of sib2, iclass 6, count 2 2006.190.08:16:10.83#ibcon#*after write, iclass 6, count 2 2006.190.08:16:10.83#ibcon#*before return 0, iclass 6, count 2 2006.190.08:16:10.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:16:10.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.190.08:16:10.83#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.190.08:16:10.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:10.83#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:16:10.90#abcon#<5=/04 2.3 4.3 24.411001012.1\r\n> 2006.190.08:16:10.92#abcon#{5=INTERFACE CLEAR} 2006.190.08:16:10.95#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:16:10.95#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:16:10.95#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:16:10.95#ibcon#first serial, iclass 6, count 0 2006.190.08:16:10.95#ibcon#enter sib2, iclass 6, count 0 2006.190.08:16:10.95#ibcon#flushed, iclass 6, count 0 2006.190.08:16:10.95#ibcon#about to write, iclass 6, count 0 2006.190.08:16:10.95#ibcon#wrote, iclass 6, count 0 2006.190.08:16:10.95#ibcon#about to read 3, iclass 6, count 0 2006.190.08:16:10.97#ibcon#read 3, iclass 6, count 0 2006.190.08:16:10.97#ibcon#about to read 4, iclass 6, count 0 2006.190.08:16:10.97#ibcon#read 4, iclass 6, count 0 2006.190.08:16:10.97#ibcon#about to read 5, iclass 6, count 0 2006.190.08:16:10.97#ibcon#read 5, iclass 6, count 0 2006.190.08:16:10.97#ibcon#about to read 6, iclass 6, count 0 2006.190.08:16:10.97#ibcon#read 6, iclass 6, count 0 2006.190.08:16:10.97#ibcon#end of sib2, iclass 6, count 0 2006.190.08:16:10.97#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:16:10.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:16:10.97#ibcon#[27=USB\r\n] 2006.190.08:16:10.97#ibcon#*before write, iclass 6, count 0 2006.190.08:16:10.97#ibcon#enter sib2, iclass 6, count 0 2006.190.08:16:10.97#ibcon#flushed, iclass 6, count 0 2006.190.08:16:10.97#ibcon#about to write, iclass 6, count 0 2006.190.08:16:10.97#ibcon#wrote, iclass 6, count 0 2006.190.08:16:10.97#ibcon#about to read 3, iclass 6, count 0 2006.190.08:16:10.98#abcon#[5=S1D000X0/0*\r\n] 2006.190.08:16:11.00#ibcon#read 3, iclass 6, count 0 2006.190.08:16:11.00#ibcon#about to read 4, iclass 6, count 0 2006.190.08:16:11.00#ibcon#read 4, iclass 6, count 0 2006.190.08:16:11.00#ibcon#about to read 5, iclass 6, count 0 2006.190.08:16:11.00#ibcon#read 5, iclass 6, count 0 2006.190.08:16:11.00#ibcon#about to read 6, iclass 6, count 0 2006.190.08:16:11.00#ibcon#read 6, iclass 6, count 0 2006.190.08:16:11.00#ibcon#end of sib2, iclass 6, count 0 2006.190.08:16:11.00#ibcon#*after write, iclass 6, count 0 2006.190.08:16:11.00#ibcon#*before return 0, iclass 6, count 0 2006.190.08:16:11.00#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:16:11.00#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.190.08:16:11.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:16:11.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:16:11.00$vc4f8/vblo=2,640.99 2006.190.08:16:11.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.190.08:16:11.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.190.08:16:11.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:11.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:11.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:11.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:11.00#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:16:11.00#ibcon#first serial, iclass 14, count 0 2006.190.08:16:11.00#ibcon#enter sib2, iclass 14, count 0 2006.190.08:16:11.00#ibcon#flushed, iclass 14, count 0 2006.190.08:16:11.00#ibcon#about to write, iclass 14, count 0 2006.190.08:16:11.00#ibcon#wrote, iclass 14, count 0 2006.190.08:16:11.00#ibcon#about to read 3, iclass 14, count 0 2006.190.08:16:11.02#ibcon#read 3, iclass 14, count 0 2006.190.08:16:11.02#ibcon#about to read 4, iclass 14, count 0 2006.190.08:16:11.02#ibcon#read 4, iclass 14, count 0 2006.190.08:16:11.02#ibcon#about to read 5, iclass 14, count 0 2006.190.08:16:11.02#ibcon#read 5, iclass 14, count 0 2006.190.08:16:11.02#ibcon#about to read 6, iclass 14, count 0 2006.190.08:16:11.02#ibcon#read 6, iclass 14, count 0 2006.190.08:16:11.02#ibcon#end of sib2, iclass 14, count 0 2006.190.08:16:11.02#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:16:11.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:16:11.02#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:16:11.02#ibcon#*before write, iclass 14, count 0 2006.190.08:16:11.02#ibcon#enter sib2, iclass 14, count 0 2006.190.08:16:11.02#ibcon#flushed, iclass 14, count 0 2006.190.08:16:11.02#ibcon#about to write, iclass 14, count 0 2006.190.08:16:11.02#ibcon#wrote, iclass 14, count 0 2006.190.08:16:11.02#ibcon#about to read 3, iclass 14, count 0 2006.190.08:16:11.06#ibcon#read 3, iclass 14, count 0 2006.190.08:16:11.06#ibcon#about to read 4, iclass 14, count 0 2006.190.08:16:11.06#ibcon#read 4, iclass 14, count 0 2006.190.08:16:11.06#ibcon#about to read 5, iclass 14, count 0 2006.190.08:16:11.06#ibcon#read 5, iclass 14, count 0 2006.190.08:16:11.06#ibcon#about to read 6, iclass 14, count 0 2006.190.08:16:11.06#ibcon#read 6, iclass 14, count 0 2006.190.08:16:11.06#ibcon#end of sib2, iclass 14, count 0 2006.190.08:16:11.06#ibcon#*after write, iclass 14, count 0 2006.190.08:16:11.06#ibcon#*before return 0, iclass 14, count 0 2006.190.08:16:11.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:11.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.190.08:16:11.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:16:11.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:16:11.06$vc4f8/vb=2,4 2006.190.08:16:11.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.190.08:16:11.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.190.08:16:11.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:11.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:11.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:11.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:11.12#ibcon#enter wrdev, iclass 16, count 2 2006.190.08:16:11.12#ibcon#first serial, iclass 16, count 2 2006.190.08:16:11.12#ibcon#enter sib2, iclass 16, count 2 2006.190.08:16:11.12#ibcon#flushed, iclass 16, count 2 2006.190.08:16:11.12#ibcon#about to write, iclass 16, count 2 2006.190.08:16:11.12#ibcon#wrote, iclass 16, count 2 2006.190.08:16:11.12#ibcon#about to read 3, iclass 16, count 2 2006.190.08:16:11.14#ibcon#read 3, iclass 16, count 2 2006.190.08:16:11.14#ibcon#about to read 4, iclass 16, count 2 2006.190.08:16:11.14#ibcon#read 4, iclass 16, count 2 2006.190.08:16:11.14#ibcon#about to read 5, iclass 16, count 2 2006.190.08:16:11.14#ibcon#read 5, iclass 16, count 2 2006.190.08:16:11.14#ibcon#about to read 6, iclass 16, count 2 2006.190.08:16:11.14#ibcon#read 6, iclass 16, count 2 2006.190.08:16:11.14#ibcon#end of sib2, iclass 16, count 2 2006.190.08:16:11.14#ibcon#*mode == 0, iclass 16, count 2 2006.190.08:16:11.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.190.08:16:11.14#ibcon#[27=AT02-04\r\n] 2006.190.08:16:11.14#ibcon#*before write, iclass 16, count 2 2006.190.08:16:11.14#ibcon#enter sib2, iclass 16, count 2 2006.190.08:16:11.14#ibcon#flushed, iclass 16, count 2 2006.190.08:16:11.14#ibcon#about to write, iclass 16, count 2 2006.190.08:16:11.14#ibcon#wrote, iclass 16, count 2 2006.190.08:16:11.14#ibcon#about to read 3, iclass 16, count 2 2006.190.08:16:11.17#ibcon#read 3, iclass 16, count 2 2006.190.08:16:11.17#ibcon#about to read 4, iclass 16, count 2 2006.190.08:16:11.17#ibcon#read 4, iclass 16, count 2 2006.190.08:16:11.17#ibcon#about to read 5, iclass 16, count 2 2006.190.08:16:11.17#ibcon#read 5, iclass 16, count 2 2006.190.08:16:11.17#ibcon#about to read 6, iclass 16, count 2 2006.190.08:16:11.17#ibcon#read 6, iclass 16, count 2 2006.190.08:16:11.17#ibcon#end of sib2, iclass 16, count 2 2006.190.08:16:11.17#ibcon#*after write, iclass 16, count 2 2006.190.08:16:11.17#ibcon#*before return 0, iclass 16, count 2 2006.190.08:16:11.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:11.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.190.08:16:11.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.190.08:16:11.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:11.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:11.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:11.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:11.29#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:16:11.29#ibcon#first serial, iclass 16, count 0 2006.190.08:16:11.29#ibcon#enter sib2, iclass 16, count 0 2006.190.08:16:11.29#ibcon#flushed, iclass 16, count 0 2006.190.08:16:11.29#ibcon#about to write, iclass 16, count 0 2006.190.08:16:11.29#ibcon#wrote, iclass 16, count 0 2006.190.08:16:11.29#ibcon#about to read 3, iclass 16, count 0 2006.190.08:16:11.31#ibcon#read 3, iclass 16, count 0 2006.190.08:16:11.31#ibcon#about to read 4, iclass 16, count 0 2006.190.08:16:11.31#ibcon#read 4, iclass 16, count 0 2006.190.08:16:11.31#ibcon#about to read 5, iclass 16, count 0 2006.190.08:16:11.31#ibcon#read 5, iclass 16, count 0 2006.190.08:16:11.31#ibcon#about to read 6, iclass 16, count 0 2006.190.08:16:11.31#ibcon#read 6, iclass 16, count 0 2006.190.08:16:11.31#ibcon#end of sib2, iclass 16, count 0 2006.190.08:16:11.31#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:16:11.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:16:11.31#ibcon#[27=USB\r\n] 2006.190.08:16:11.31#ibcon#*before write, iclass 16, count 0 2006.190.08:16:11.31#ibcon#enter sib2, iclass 16, count 0 2006.190.08:16:11.31#ibcon#flushed, iclass 16, count 0 2006.190.08:16:11.31#ibcon#about to write, iclass 16, count 0 2006.190.08:16:11.31#ibcon#wrote, iclass 16, count 0 2006.190.08:16:11.31#ibcon#about to read 3, iclass 16, count 0 2006.190.08:16:11.34#ibcon#read 3, iclass 16, count 0 2006.190.08:16:11.34#ibcon#about to read 4, iclass 16, count 0 2006.190.08:16:11.34#ibcon#read 4, iclass 16, count 0 2006.190.08:16:11.34#ibcon#about to read 5, iclass 16, count 0 2006.190.08:16:11.34#ibcon#read 5, iclass 16, count 0 2006.190.08:16:11.34#ibcon#about to read 6, iclass 16, count 0 2006.190.08:16:11.34#ibcon#read 6, iclass 16, count 0 2006.190.08:16:11.34#ibcon#end of sib2, iclass 16, count 0 2006.190.08:16:11.34#ibcon#*after write, iclass 16, count 0 2006.190.08:16:11.34#ibcon#*before return 0, iclass 16, count 0 2006.190.08:16:11.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:11.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.190.08:16:11.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:16:11.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:16:11.34$vc4f8/vblo=3,656.99 2006.190.08:16:11.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.190.08:16:11.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.190.08:16:11.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:11.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:11.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:11.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:11.34#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:16:11.34#ibcon#first serial, iclass 18, count 0 2006.190.08:16:11.34#ibcon#enter sib2, iclass 18, count 0 2006.190.08:16:11.34#ibcon#flushed, iclass 18, count 0 2006.190.08:16:11.34#ibcon#about to write, iclass 18, count 0 2006.190.08:16:11.34#ibcon#wrote, iclass 18, count 0 2006.190.08:16:11.34#ibcon#about to read 3, iclass 18, count 0 2006.190.08:16:11.36#ibcon#read 3, iclass 18, count 0 2006.190.08:16:11.36#ibcon#about to read 4, iclass 18, count 0 2006.190.08:16:11.36#ibcon#read 4, iclass 18, count 0 2006.190.08:16:11.36#ibcon#about to read 5, iclass 18, count 0 2006.190.08:16:11.36#ibcon#read 5, iclass 18, count 0 2006.190.08:16:11.36#ibcon#about to read 6, iclass 18, count 0 2006.190.08:16:11.36#ibcon#read 6, iclass 18, count 0 2006.190.08:16:11.36#ibcon#end of sib2, iclass 18, count 0 2006.190.08:16:11.36#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:16:11.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:16:11.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:16:11.36#ibcon#*before write, iclass 18, count 0 2006.190.08:16:11.36#ibcon#enter sib2, iclass 18, count 0 2006.190.08:16:11.36#ibcon#flushed, iclass 18, count 0 2006.190.08:16:11.36#ibcon#about to write, iclass 18, count 0 2006.190.08:16:11.36#ibcon#wrote, iclass 18, count 0 2006.190.08:16:11.36#ibcon#about to read 3, iclass 18, count 0 2006.190.08:16:11.40#ibcon#read 3, iclass 18, count 0 2006.190.08:16:11.40#ibcon#about to read 4, iclass 18, count 0 2006.190.08:16:11.40#ibcon#read 4, iclass 18, count 0 2006.190.08:16:11.40#ibcon#about to read 5, iclass 18, count 0 2006.190.08:16:11.40#ibcon#read 5, iclass 18, count 0 2006.190.08:16:11.40#ibcon#about to read 6, iclass 18, count 0 2006.190.08:16:11.40#ibcon#read 6, iclass 18, count 0 2006.190.08:16:11.40#ibcon#end of sib2, iclass 18, count 0 2006.190.08:16:11.40#ibcon#*after write, iclass 18, count 0 2006.190.08:16:11.40#ibcon#*before return 0, iclass 18, count 0 2006.190.08:16:11.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:11.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.190.08:16:11.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:16:11.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:16:11.40$vc4f8/vb=3,4 2006.190.08:16:11.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.190.08:16:11.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.190.08:16:11.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:11.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:11.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:11.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:11.46#ibcon#enter wrdev, iclass 20, count 2 2006.190.08:16:11.46#ibcon#first serial, iclass 20, count 2 2006.190.08:16:11.46#ibcon#enter sib2, iclass 20, count 2 2006.190.08:16:11.46#ibcon#flushed, iclass 20, count 2 2006.190.08:16:11.46#ibcon#about to write, iclass 20, count 2 2006.190.08:16:11.46#ibcon#wrote, iclass 20, count 2 2006.190.08:16:11.46#ibcon#about to read 3, iclass 20, count 2 2006.190.08:16:11.48#ibcon#read 3, iclass 20, count 2 2006.190.08:16:11.48#ibcon#about to read 4, iclass 20, count 2 2006.190.08:16:11.48#ibcon#read 4, iclass 20, count 2 2006.190.08:16:11.48#ibcon#about to read 5, iclass 20, count 2 2006.190.08:16:11.48#ibcon#read 5, iclass 20, count 2 2006.190.08:16:11.48#ibcon#about to read 6, iclass 20, count 2 2006.190.08:16:11.48#ibcon#read 6, iclass 20, count 2 2006.190.08:16:11.48#ibcon#end of sib2, iclass 20, count 2 2006.190.08:16:11.48#ibcon#*mode == 0, iclass 20, count 2 2006.190.08:16:11.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.190.08:16:11.48#ibcon#[27=AT03-04\r\n] 2006.190.08:16:11.48#ibcon#*before write, iclass 20, count 2 2006.190.08:16:11.48#ibcon#enter sib2, iclass 20, count 2 2006.190.08:16:11.48#ibcon#flushed, iclass 20, count 2 2006.190.08:16:11.48#ibcon#about to write, iclass 20, count 2 2006.190.08:16:11.48#ibcon#wrote, iclass 20, count 2 2006.190.08:16:11.48#ibcon#about to read 3, iclass 20, count 2 2006.190.08:16:11.51#ibcon#read 3, iclass 20, count 2 2006.190.08:16:11.51#ibcon#about to read 4, iclass 20, count 2 2006.190.08:16:11.51#ibcon#read 4, iclass 20, count 2 2006.190.08:16:11.51#ibcon#about to read 5, iclass 20, count 2 2006.190.08:16:11.51#ibcon#read 5, iclass 20, count 2 2006.190.08:16:11.51#ibcon#about to read 6, iclass 20, count 2 2006.190.08:16:11.51#ibcon#read 6, iclass 20, count 2 2006.190.08:16:11.51#ibcon#end of sib2, iclass 20, count 2 2006.190.08:16:11.51#ibcon#*after write, iclass 20, count 2 2006.190.08:16:11.51#ibcon#*before return 0, iclass 20, count 2 2006.190.08:16:11.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:11.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.190.08:16:11.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.190.08:16:11.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:11.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:11.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:11.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:11.63#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:16:11.63#ibcon#first serial, iclass 20, count 0 2006.190.08:16:11.63#ibcon#enter sib2, iclass 20, count 0 2006.190.08:16:11.63#ibcon#flushed, iclass 20, count 0 2006.190.08:16:11.63#ibcon#about to write, iclass 20, count 0 2006.190.08:16:11.63#ibcon#wrote, iclass 20, count 0 2006.190.08:16:11.63#ibcon#about to read 3, iclass 20, count 0 2006.190.08:16:11.65#ibcon#read 3, iclass 20, count 0 2006.190.08:16:11.65#ibcon#about to read 4, iclass 20, count 0 2006.190.08:16:11.65#ibcon#read 4, iclass 20, count 0 2006.190.08:16:11.65#ibcon#about to read 5, iclass 20, count 0 2006.190.08:16:11.65#ibcon#read 5, iclass 20, count 0 2006.190.08:16:11.65#ibcon#about to read 6, iclass 20, count 0 2006.190.08:16:11.65#ibcon#read 6, iclass 20, count 0 2006.190.08:16:11.65#ibcon#end of sib2, iclass 20, count 0 2006.190.08:16:11.65#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:16:11.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:16:11.65#ibcon#[27=USB\r\n] 2006.190.08:16:11.65#ibcon#*before write, iclass 20, count 0 2006.190.08:16:11.65#ibcon#enter sib2, iclass 20, count 0 2006.190.08:16:11.65#ibcon#flushed, iclass 20, count 0 2006.190.08:16:11.65#ibcon#about to write, iclass 20, count 0 2006.190.08:16:11.65#ibcon#wrote, iclass 20, count 0 2006.190.08:16:11.65#ibcon#about to read 3, iclass 20, count 0 2006.190.08:16:11.68#ibcon#read 3, iclass 20, count 0 2006.190.08:16:11.68#ibcon#about to read 4, iclass 20, count 0 2006.190.08:16:11.68#ibcon#read 4, iclass 20, count 0 2006.190.08:16:11.68#ibcon#about to read 5, iclass 20, count 0 2006.190.08:16:11.68#ibcon#read 5, iclass 20, count 0 2006.190.08:16:11.68#ibcon#about to read 6, iclass 20, count 0 2006.190.08:16:11.68#ibcon#read 6, iclass 20, count 0 2006.190.08:16:11.68#ibcon#end of sib2, iclass 20, count 0 2006.190.08:16:11.68#ibcon#*after write, iclass 20, count 0 2006.190.08:16:11.68#ibcon#*before return 0, iclass 20, count 0 2006.190.08:16:11.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:11.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.190.08:16:11.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:16:11.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:16:11.68$vc4f8/vblo=4,712.99 2006.190.08:16:11.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.190.08:16:11.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.190.08:16:11.68#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:11.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:11.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:11.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:11.68#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:16:11.68#ibcon#first serial, iclass 22, count 0 2006.190.08:16:11.68#ibcon#enter sib2, iclass 22, count 0 2006.190.08:16:11.68#ibcon#flushed, iclass 22, count 0 2006.190.08:16:11.68#ibcon#about to write, iclass 22, count 0 2006.190.08:16:11.68#ibcon#wrote, iclass 22, count 0 2006.190.08:16:11.68#ibcon#about to read 3, iclass 22, count 0 2006.190.08:16:11.70#ibcon#read 3, iclass 22, count 0 2006.190.08:16:11.70#ibcon#about to read 4, iclass 22, count 0 2006.190.08:16:11.70#ibcon#read 4, iclass 22, count 0 2006.190.08:16:11.70#ibcon#about to read 5, iclass 22, count 0 2006.190.08:16:11.70#ibcon#read 5, iclass 22, count 0 2006.190.08:16:11.70#ibcon#about to read 6, iclass 22, count 0 2006.190.08:16:11.70#ibcon#read 6, iclass 22, count 0 2006.190.08:16:11.70#ibcon#end of sib2, iclass 22, count 0 2006.190.08:16:11.70#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:16:11.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:16:11.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:16:11.70#ibcon#*before write, iclass 22, count 0 2006.190.08:16:11.70#ibcon#enter sib2, iclass 22, count 0 2006.190.08:16:11.70#ibcon#flushed, iclass 22, count 0 2006.190.08:16:11.70#ibcon#about to write, iclass 22, count 0 2006.190.08:16:11.70#ibcon#wrote, iclass 22, count 0 2006.190.08:16:11.70#ibcon#about to read 3, iclass 22, count 0 2006.190.08:16:11.74#ibcon#read 3, iclass 22, count 0 2006.190.08:16:11.74#ibcon#about to read 4, iclass 22, count 0 2006.190.08:16:11.74#ibcon#read 4, iclass 22, count 0 2006.190.08:16:11.74#ibcon#about to read 5, iclass 22, count 0 2006.190.08:16:11.74#ibcon#read 5, iclass 22, count 0 2006.190.08:16:11.74#ibcon#about to read 6, iclass 22, count 0 2006.190.08:16:11.74#ibcon#read 6, iclass 22, count 0 2006.190.08:16:11.74#ibcon#end of sib2, iclass 22, count 0 2006.190.08:16:11.74#ibcon#*after write, iclass 22, count 0 2006.190.08:16:11.74#ibcon#*before return 0, iclass 22, count 0 2006.190.08:16:11.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:11.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.190.08:16:11.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:16:11.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:16:11.74$vc4f8/vb=4,4 2006.190.08:16:11.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.190.08:16:11.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.190.08:16:11.74#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:11.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:11.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:11.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:11.80#ibcon#enter wrdev, iclass 24, count 2 2006.190.08:16:11.80#ibcon#first serial, iclass 24, count 2 2006.190.08:16:11.80#ibcon#enter sib2, iclass 24, count 2 2006.190.08:16:11.80#ibcon#flushed, iclass 24, count 2 2006.190.08:16:11.80#ibcon#about to write, iclass 24, count 2 2006.190.08:16:11.80#ibcon#wrote, iclass 24, count 2 2006.190.08:16:11.80#ibcon#about to read 3, iclass 24, count 2 2006.190.08:16:11.82#ibcon#read 3, iclass 24, count 2 2006.190.08:16:11.82#ibcon#about to read 4, iclass 24, count 2 2006.190.08:16:11.82#ibcon#read 4, iclass 24, count 2 2006.190.08:16:11.82#ibcon#about to read 5, iclass 24, count 2 2006.190.08:16:11.82#ibcon#read 5, iclass 24, count 2 2006.190.08:16:11.82#ibcon#about to read 6, iclass 24, count 2 2006.190.08:16:11.82#ibcon#read 6, iclass 24, count 2 2006.190.08:16:11.82#ibcon#end of sib2, iclass 24, count 2 2006.190.08:16:11.82#ibcon#*mode == 0, iclass 24, count 2 2006.190.08:16:11.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.190.08:16:11.82#ibcon#[27=AT04-04\r\n] 2006.190.08:16:11.82#ibcon#*before write, iclass 24, count 2 2006.190.08:16:11.82#ibcon#enter sib2, iclass 24, count 2 2006.190.08:16:11.82#ibcon#flushed, iclass 24, count 2 2006.190.08:16:11.82#ibcon#about to write, iclass 24, count 2 2006.190.08:16:11.82#ibcon#wrote, iclass 24, count 2 2006.190.08:16:11.82#ibcon#about to read 3, iclass 24, count 2 2006.190.08:16:11.85#ibcon#read 3, iclass 24, count 2 2006.190.08:16:11.85#ibcon#about to read 4, iclass 24, count 2 2006.190.08:16:11.85#ibcon#read 4, iclass 24, count 2 2006.190.08:16:11.85#ibcon#about to read 5, iclass 24, count 2 2006.190.08:16:11.85#ibcon#read 5, iclass 24, count 2 2006.190.08:16:11.85#ibcon#about to read 6, iclass 24, count 2 2006.190.08:16:11.85#ibcon#read 6, iclass 24, count 2 2006.190.08:16:11.85#ibcon#end of sib2, iclass 24, count 2 2006.190.08:16:11.85#ibcon#*after write, iclass 24, count 2 2006.190.08:16:11.85#ibcon#*before return 0, iclass 24, count 2 2006.190.08:16:11.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:11.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.190.08:16:11.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.190.08:16:11.85#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:11.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:11.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:11.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:11.97#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:16:11.97#ibcon#first serial, iclass 24, count 0 2006.190.08:16:11.97#ibcon#enter sib2, iclass 24, count 0 2006.190.08:16:11.97#ibcon#flushed, iclass 24, count 0 2006.190.08:16:11.97#ibcon#about to write, iclass 24, count 0 2006.190.08:16:11.97#ibcon#wrote, iclass 24, count 0 2006.190.08:16:11.97#ibcon#about to read 3, iclass 24, count 0 2006.190.08:16:11.99#ibcon#read 3, iclass 24, count 0 2006.190.08:16:11.99#ibcon#about to read 4, iclass 24, count 0 2006.190.08:16:11.99#ibcon#read 4, iclass 24, count 0 2006.190.08:16:11.99#ibcon#about to read 5, iclass 24, count 0 2006.190.08:16:11.99#ibcon#read 5, iclass 24, count 0 2006.190.08:16:11.99#ibcon#about to read 6, iclass 24, count 0 2006.190.08:16:11.99#ibcon#read 6, iclass 24, count 0 2006.190.08:16:11.99#ibcon#end of sib2, iclass 24, count 0 2006.190.08:16:11.99#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:16:11.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:16:11.99#ibcon#[27=USB\r\n] 2006.190.08:16:11.99#ibcon#*before write, iclass 24, count 0 2006.190.08:16:11.99#ibcon#enter sib2, iclass 24, count 0 2006.190.08:16:11.99#ibcon#flushed, iclass 24, count 0 2006.190.08:16:11.99#ibcon#about to write, iclass 24, count 0 2006.190.08:16:11.99#ibcon#wrote, iclass 24, count 0 2006.190.08:16:11.99#ibcon#about to read 3, iclass 24, count 0 2006.190.08:16:12.02#ibcon#read 3, iclass 24, count 0 2006.190.08:16:12.02#ibcon#about to read 4, iclass 24, count 0 2006.190.08:16:12.02#ibcon#read 4, iclass 24, count 0 2006.190.08:16:12.02#ibcon#about to read 5, iclass 24, count 0 2006.190.08:16:12.02#ibcon#read 5, iclass 24, count 0 2006.190.08:16:12.02#ibcon#about to read 6, iclass 24, count 0 2006.190.08:16:12.02#ibcon#read 6, iclass 24, count 0 2006.190.08:16:12.02#ibcon#end of sib2, iclass 24, count 0 2006.190.08:16:12.02#ibcon#*after write, iclass 24, count 0 2006.190.08:16:12.02#ibcon#*before return 0, iclass 24, count 0 2006.190.08:16:12.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:12.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.190.08:16:12.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:16:12.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:16:12.02$vc4f8/vblo=5,744.99 2006.190.08:16:12.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.190.08:16:12.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.190.08:16:12.02#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:12.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:12.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:12.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:12.02#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:16:12.02#ibcon#first serial, iclass 26, count 0 2006.190.08:16:12.02#ibcon#enter sib2, iclass 26, count 0 2006.190.08:16:12.02#ibcon#flushed, iclass 26, count 0 2006.190.08:16:12.02#ibcon#about to write, iclass 26, count 0 2006.190.08:16:12.02#ibcon#wrote, iclass 26, count 0 2006.190.08:16:12.02#ibcon#about to read 3, iclass 26, count 0 2006.190.08:16:12.04#ibcon#read 3, iclass 26, count 0 2006.190.08:16:12.04#ibcon#about to read 4, iclass 26, count 0 2006.190.08:16:12.04#ibcon#read 4, iclass 26, count 0 2006.190.08:16:12.04#ibcon#about to read 5, iclass 26, count 0 2006.190.08:16:12.04#ibcon#read 5, iclass 26, count 0 2006.190.08:16:12.04#ibcon#about to read 6, iclass 26, count 0 2006.190.08:16:12.04#ibcon#read 6, iclass 26, count 0 2006.190.08:16:12.04#ibcon#end of sib2, iclass 26, count 0 2006.190.08:16:12.04#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:16:12.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:16:12.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:16:12.04#ibcon#*before write, iclass 26, count 0 2006.190.08:16:12.04#ibcon#enter sib2, iclass 26, count 0 2006.190.08:16:12.04#ibcon#flushed, iclass 26, count 0 2006.190.08:16:12.04#ibcon#about to write, iclass 26, count 0 2006.190.08:16:12.04#ibcon#wrote, iclass 26, count 0 2006.190.08:16:12.04#ibcon#about to read 3, iclass 26, count 0 2006.190.08:16:12.08#ibcon#read 3, iclass 26, count 0 2006.190.08:16:12.08#ibcon#about to read 4, iclass 26, count 0 2006.190.08:16:12.08#ibcon#read 4, iclass 26, count 0 2006.190.08:16:12.08#ibcon#about to read 5, iclass 26, count 0 2006.190.08:16:12.08#ibcon#read 5, iclass 26, count 0 2006.190.08:16:12.08#ibcon#about to read 6, iclass 26, count 0 2006.190.08:16:12.08#ibcon#read 6, iclass 26, count 0 2006.190.08:16:12.08#ibcon#end of sib2, iclass 26, count 0 2006.190.08:16:12.08#ibcon#*after write, iclass 26, count 0 2006.190.08:16:12.08#ibcon#*before return 0, iclass 26, count 0 2006.190.08:16:12.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:12.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.190.08:16:12.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:16:12.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:16:12.08$vc4f8/vb=5,4 2006.190.08:16:12.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.190.08:16:12.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.190.08:16:12.08#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:12.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:12.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:12.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:12.14#ibcon#enter wrdev, iclass 28, count 2 2006.190.08:16:12.14#ibcon#first serial, iclass 28, count 2 2006.190.08:16:12.14#ibcon#enter sib2, iclass 28, count 2 2006.190.08:16:12.14#ibcon#flushed, iclass 28, count 2 2006.190.08:16:12.14#ibcon#about to write, iclass 28, count 2 2006.190.08:16:12.14#ibcon#wrote, iclass 28, count 2 2006.190.08:16:12.14#ibcon#about to read 3, iclass 28, count 2 2006.190.08:16:12.16#ibcon#read 3, iclass 28, count 2 2006.190.08:16:12.16#ibcon#about to read 4, iclass 28, count 2 2006.190.08:16:12.16#ibcon#read 4, iclass 28, count 2 2006.190.08:16:12.16#ibcon#about to read 5, iclass 28, count 2 2006.190.08:16:12.16#ibcon#read 5, iclass 28, count 2 2006.190.08:16:12.16#ibcon#about to read 6, iclass 28, count 2 2006.190.08:16:12.16#ibcon#read 6, iclass 28, count 2 2006.190.08:16:12.16#ibcon#end of sib2, iclass 28, count 2 2006.190.08:16:12.16#ibcon#*mode == 0, iclass 28, count 2 2006.190.08:16:12.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.190.08:16:12.16#ibcon#[27=AT05-04\r\n] 2006.190.08:16:12.16#ibcon#*before write, iclass 28, count 2 2006.190.08:16:12.16#ibcon#enter sib2, iclass 28, count 2 2006.190.08:16:12.16#ibcon#flushed, iclass 28, count 2 2006.190.08:16:12.16#ibcon#about to write, iclass 28, count 2 2006.190.08:16:12.16#ibcon#wrote, iclass 28, count 2 2006.190.08:16:12.16#ibcon#about to read 3, iclass 28, count 2 2006.190.08:16:12.19#ibcon#read 3, iclass 28, count 2 2006.190.08:16:12.19#ibcon#about to read 4, iclass 28, count 2 2006.190.08:16:12.19#ibcon#read 4, iclass 28, count 2 2006.190.08:16:12.19#ibcon#about to read 5, iclass 28, count 2 2006.190.08:16:12.19#ibcon#read 5, iclass 28, count 2 2006.190.08:16:12.19#ibcon#about to read 6, iclass 28, count 2 2006.190.08:16:12.19#ibcon#read 6, iclass 28, count 2 2006.190.08:16:12.19#ibcon#end of sib2, iclass 28, count 2 2006.190.08:16:12.19#ibcon#*after write, iclass 28, count 2 2006.190.08:16:12.19#ibcon#*before return 0, iclass 28, count 2 2006.190.08:16:12.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:12.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.190.08:16:12.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.190.08:16:12.19#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:12.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:12.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:12.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:12.31#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:16:12.31#ibcon#first serial, iclass 28, count 0 2006.190.08:16:12.31#ibcon#enter sib2, iclass 28, count 0 2006.190.08:16:12.31#ibcon#flushed, iclass 28, count 0 2006.190.08:16:12.31#ibcon#about to write, iclass 28, count 0 2006.190.08:16:12.31#ibcon#wrote, iclass 28, count 0 2006.190.08:16:12.31#ibcon#about to read 3, iclass 28, count 0 2006.190.08:16:12.33#ibcon#read 3, iclass 28, count 0 2006.190.08:16:12.33#ibcon#about to read 4, iclass 28, count 0 2006.190.08:16:12.33#ibcon#read 4, iclass 28, count 0 2006.190.08:16:12.33#ibcon#about to read 5, iclass 28, count 0 2006.190.08:16:12.33#ibcon#read 5, iclass 28, count 0 2006.190.08:16:12.33#ibcon#about to read 6, iclass 28, count 0 2006.190.08:16:12.33#ibcon#read 6, iclass 28, count 0 2006.190.08:16:12.33#ibcon#end of sib2, iclass 28, count 0 2006.190.08:16:12.33#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:16:12.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:16:12.33#ibcon#[27=USB\r\n] 2006.190.08:16:12.33#ibcon#*before write, iclass 28, count 0 2006.190.08:16:12.33#ibcon#enter sib2, iclass 28, count 0 2006.190.08:16:12.33#ibcon#flushed, iclass 28, count 0 2006.190.08:16:12.33#ibcon#about to write, iclass 28, count 0 2006.190.08:16:12.33#ibcon#wrote, iclass 28, count 0 2006.190.08:16:12.33#ibcon#about to read 3, iclass 28, count 0 2006.190.08:16:12.36#ibcon#read 3, iclass 28, count 0 2006.190.08:16:12.36#ibcon#about to read 4, iclass 28, count 0 2006.190.08:16:12.36#ibcon#read 4, iclass 28, count 0 2006.190.08:16:12.36#ibcon#about to read 5, iclass 28, count 0 2006.190.08:16:12.36#ibcon#read 5, iclass 28, count 0 2006.190.08:16:12.36#ibcon#about to read 6, iclass 28, count 0 2006.190.08:16:12.36#ibcon#read 6, iclass 28, count 0 2006.190.08:16:12.36#ibcon#end of sib2, iclass 28, count 0 2006.190.08:16:12.36#ibcon#*after write, iclass 28, count 0 2006.190.08:16:12.36#ibcon#*before return 0, iclass 28, count 0 2006.190.08:16:12.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:12.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.190.08:16:12.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:16:12.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:16:12.36$vc4f8/vblo=6,752.99 2006.190.08:16:12.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.08:16:12.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.08:16:12.36#ibcon#ireg 17 cls_cnt 0 2006.190.08:16:12.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:12.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:12.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:12.36#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:16:12.36#ibcon#first serial, iclass 30, count 0 2006.190.08:16:12.36#ibcon#enter sib2, iclass 30, count 0 2006.190.08:16:12.36#ibcon#flushed, iclass 30, count 0 2006.190.08:16:12.36#ibcon#about to write, iclass 30, count 0 2006.190.08:16:12.36#ibcon#wrote, iclass 30, count 0 2006.190.08:16:12.36#ibcon#about to read 3, iclass 30, count 0 2006.190.08:16:12.38#ibcon#read 3, iclass 30, count 0 2006.190.08:16:12.38#ibcon#about to read 4, iclass 30, count 0 2006.190.08:16:12.38#ibcon#read 4, iclass 30, count 0 2006.190.08:16:12.38#ibcon#about to read 5, iclass 30, count 0 2006.190.08:16:12.38#ibcon#read 5, iclass 30, count 0 2006.190.08:16:12.38#ibcon#about to read 6, iclass 30, count 0 2006.190.08:16:12.38#ibcon#read 6, iclass 30, count 0 2006.190.08:16:12.38#ibcon#end of sib2, iclass 30, count 0 2006.190.08:16:12.38#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:16:12.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:16:12.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:16:12.38#ibcon#*before write, iclass 30, count 0 2006.190.08:16:12.38#ibcon#enter sib2, iclass 30, count 0 2006.190.08:16:12.38#ibcon#flushed, iclass 30, count 0 2006.190.08:16:12.38#ibcon#about to write, iclass 30, count 0 2006.190.08:16:12.38#ibcon#wrote, iclass 30, count 0 2006.190.08:16:12.38#ibcon#about to read 3, iclass 30, count 0 2006.190.08:16:12.42#ibcon#read 3, iclass 30, count 0 2006.190.08:16:12.42#ibcon#about to read 4, iclass 30, count 0 2006.190.08:16:12.42#ibcon#read 4, iclass 30, count 0 2006.190.08:16:12.42#ibcon#about to read 5, iclass 30, count 0 2006.190.08:16:12.42#ibcon#read 5, iclass 30, count 0 2006.190.08:16:12.42#ibcon#about to read 6, iclass 30, count 0 2006.190.08:16:12.42#ibcon#read 6, iclass 30, count 0 2006.190.08:16:12.42#ibcon#end of sib2, iclass 30, count 0 2006.190.08:16:12.42#ibcon#*after write, iclass 30, count 0 2006.190.08:16:12.42#ibcon#*before return 0, iclass 30, count 0 2006.190.08:16:12.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:12.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:16:12.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:16:12.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:16:12.42$vc4f8/vb=6,4 2006.190.08:16:12.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.190.08:16:12.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.190.08:16:12.42#ibcon#ireg 11 cls_cnt 2 2006.190.08:16:12.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:12.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:12.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:12.48#ibcon#enter wrdev, iclass 32, count 2 2006.190.08:16:12.48#ibcon#first serial, iclass 32, count 2 2006.190.08:16:12.48#ibcon#enter sib2, iclass 32, count 2 2006.190.08:16:12.48#ibcon#flushed, iclass 32, count 2 2006.190.08:16:12.48#ibcon#about to write, iclass 32, count 2 2006.190.08:16:12.48#ibcon#wrote, iclass 32, count 2 2006.190.08:16:12.48#ibcon#about to read 3, iclass 32, count 2 2006.190.08:16:12.50#ibcon#read 3, iclass 32, count 2 2006.190.08:16:12.50#ibcon#about to read 4, iclass 32, count 2 2006.190.08:16:12.50#ibcon#read 4, iclass 32, count 2 2006.190.08:16:12.50#ibcon#about to read 5, iclass 32, count 2 2006.190.08:16:12.50#ibcon#read 5, iclass 32, count 2 2006.190.08:16:12.50#ibcon#about to read 6, iclass 32, count 2 2006.190.08:16:12.50#ibcon#read 6, iclass 32, count 2 2006.190.08:16:12.50#ibcon#end of sib2, iclass 32, count 2 2006.190.08:16:12.50#ibcon#*mode == 0, iclass 32, count 2 2006.190.08:16:12.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.190.08:16:12.50#ibcon#[27=AT06-04\r\n] 2006.190.08:16:12.50#ibcon#*before write, iclass 32, count 2 2006.190.08:16:12.50#ibcon#enter sib2, iclass 32, count 2 2006.190.08:16:12.50#ibcon#flushed, iclass 32, count 2 2006.190.08:16:12.50#ibcon#about to write, iclass 32, count 2 2006.190.08:16:12.50#ibcon#wrote, iclass 32, count 2 2006.190.08:16:12.50#ibcon#about to read 3, iclass 32, count 2 2006.190.08:16:12.53#ibcon#read 3, iclass 32, count 2 2006.190.08:16:12.53#ibcon#about to read 4, iclass 32, count 2 2006.190.08:16:12.53#ibcon#read 4, iclass 32, count 2 2006.190.08:16:12.53#ibcon#about to read 5, iclass 32, count 2 2006.190.08:16:12.53#ibcon#read 5, iclass 32, count 2 2006.190.08:16:12.53#ibcon#about to read 6, iclass 32, count 2 2006.190.08:16:12.53#ibcon#read 6, iclass 32, count 2 2006.190.08:16:12.53#ibcon#end of sib2, iclass 32, count 2 2006.190.08:16:12.53#ibcon#*after write, iclass 32, count 2 2006.190.08:16:12.53#ibcon#*before return 0, iclass 32, count 2 2006.190.08:16:12.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:12.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.190.08:16:12.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.190.08:16:12.53#ibcon#ireg 7 cls_cnt 0 2006.190.08:16:12.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:12.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:12.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:12.65#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:16:12.65#ibcon#first serial, iclass 32, count 0 2006.190.08:16:12.65#ibcon#enter sib2, iclass 32, count 0 2006.190.08:16:12.65#ibcon#flushed, iclass 32, count 0 2006.190.08:16:12.65#ibcon#about to write, iclass 32, count 0 2006.190.08:16:12.65#ibcon#wrote, iclass 32, count 0 2006.190.08:16:12.65#ibcon#about to read 3, iclass 32, count 0 2006.190.08:16:12.67#ibcon#read 3, iclass 32, count 0 2006.190.08:16:12.67#ibcon#about to read 4, iclass 32, count 0 2006.190.08:16:12.67#ibcon#read 4, iclass 32, count 0 2006.190.08:16:12.67#ibcon#about to read 5, iclass 32, count 0 2006.190.08:16:12.67#ibcon#read 5, iclass 32, count 0 2006.190.08:16:12.67#ibcon#about to read 6, iclass 32, count 0 2006.190.08:16:12.67#ibcon#read 6, iclass 32, count 0 2006.190.08:16:12.67#ibcon#end of sib2, iclass 32, count 0 2006.190.08:16:12.67#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:16:12.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:16:12.67#ibcon#[27=USB\r\n] 2006.190.08:16:12.67#ibcon#*before write, iclass 32, count 0 2006.190.08:16:12.67#ibcon#enter sib2, iclass 32, count 0 2006.190.08:16:12.67#ibcon#flushed, iclass 32, count 0 2006.190.08:16:12.67#ibcon#about to write, iclass 32, count 0 2006.190.08:16:12.67#ibcon#wrote, iclass 32, count 0 2006.190.08:16:12.67#ibcon#about to read 3, iclass 32, count 0 2006.190.08:16:12.70#ibcon#read 3, iclass 32, count 0 2006.190.08:16:12.70#ibcon#about to read 4, iclass 32, count 0 2006.190.08:16:12.70#ibcon#read 4, iclass 32, count 0 2006.190.08:16:12.70#ibcon#about to read 5, iclass 32, count 0 2006.190.08:16:12.70#ibcon#read 5, iclass 32, count 0 2006.190.08:16:12.70#ibcon#about to read 6, iclass 32, count 0 2006.190.08:16:12.70#ibcon#read 6, iclass 32, count 0 2006.190.08:16:12.70#ibcon#end of sib2, iclass 32, count 0 2006.190.08:16:12.70#ibcon#*after write, iclass 32, count 0 2006.190.08:16:12.70#ibcon#*before return 0, iclass 32, count 0 2006.190.08:16:12.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:12.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.190.08:16:12.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:16:12.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:16:12.70$vc4f8/vabw=wide 2006.190.08:16:12.70#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.190.08:16:12.70#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.190.08:16:12.70#ibcon#ireg 8 cls_cnt 0 2006.190.08:16:12.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:12.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:12.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:12.70#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:16:12.70#ibcon#first serial, iclass 34, count 0 2006.190.08:16:12.70#ibcon#enter sib2, iclass 34, count 0 2006.190.08:16:12.70#ibcon#flushed, iclass 34, count 0 2006.190.08:16:12.70#ibcon#about to write, iclass 34, count 0 2006.190.08:16:12.70#ibcon#wrote, iclass 34, count 0 2006.190.08:16:12.70#ibcon#about to read 3, iclass 34, count 0 2006.190.08:16:12.72#ibcon#read 3, iclass 34, count 0 2006.190.08:16:12.72#ibcon#about to read 4, iclass 34, count 0 2006.190.08:16:12.72#ibcon#read 4, iclass 34, count 0 2006.190.08:16:12.72#ibcon#about to read 5, iclass 34, count 0 2006.190.08:16:12.72#ibcon#read 5, iclass 34, count 0 2006.190.08:16:12.72#ibcon#about to read 6, iclass 34, count 0 2006.190.08:16:12.72#ibcon#read 6, iclass 34, count 0 2006.190.08:16:12.72#ibcon#end of sib2, iclass 34, count 0 2006.190.08:16:12.72#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:16:12.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:16:12.72#ibcon#[25=BW32\r\n] 2006.190.08:16:12.72#ibcon#*before write, iclass 34, count 0 2006.190.08:16:12.72#ibcon#enter sib2, iclass 34, count 0 2006.190.08:16:12.72#ibcon#flushed, iclass 34, count 0 2006.190.08:16:12.72#ibcon#about to write, iclass 34, count 0 2006.190.08:16:12.72#ibcon#wrote, iclass 34, count 0 2006.190.08:16:12.72#ibcon#about to read 3, iclass 34, count 0 2006.190.08:16:12.75#ibcon#read 3, iclass 34, count 0 2006.190.08:16:12.75#ibcon#about to read 4, iclass 34, count 0 2006.190.08:16:12.75#ibcon#read 4, iclass 34, count 0 2006.190.08:16:12.75#ibcon#about to read 5, iclass 34, count 0 2006.190.08:16:12.75#ibcon#read 5, iclass 34, count 0 2006.190.08:16:12.75#ibcon#about to read 6, iclass 34, count 0 2006.190.08:16:12.75#ibcon#read 6, iclass 34, count 0 2006.190.08:16:12.75#ibcon#end of sib2, iclass 34, count 0 2006.190.08:16:12.75#ibcon#*after write, iclass 34, count 0 2006.190.08:16:12.75#ibcon#*before return 0, iclass 34, count 0 2006.190.08:16:12.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:12.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.190.08:16:12.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:16:12.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:16:12.75$vc4f8/vbbw=wide 2006.190.08:16:12.75#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.08:16:12.75#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.08:16:12.75#ibcon#ireg 8 cls_cnt 0 2006.190.08:16:12.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:16:12.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:16:12.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:16:12.82#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:16:12.82#ibcon#first serial, iclass 36, count 0 2006.190.08:16:12.82#ibcon#enter sib2, iclass 36, count 0 2006.190.08:16:12.82#ibcon#flushed, iclass 36, count 0 2006.190.08:16:12.82#ibcon#about to write, iclass 36, count 0 2006.190.08:16:12.82#ibcon#wrote, iclass 36, count 0 2006.190.08:16:12.82#ibcon#about to read 3, iclass 36, count 0 2006.190.08:16:12.84#ibcon#read 3, iclass 36, count 0 2006.190.08:16:12.84#ibcon#about to read 4, iclass 36, count 0 2006.190.08:16:12.84#ibcon#read 4, iclass 36, count 0 2006.190.08:16:12.84#ibcon#about to read 5, iclass 36, count 0 2006.190.08:16:12.84#ibcon#read 5, iclass 36, count 0 2006.190.08:16:12.84#ibcon#about to read 6, iclass 36, count 0 2006.190.08:16:12.84#ibcon#read 6, iclass 36, count 0 2006.190.08:16:12.84#ibcon#end of sib2, iclass 36, count 0 2006.190.08:16:12.84#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:16:12.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:16:12.84#ibcon#[27=BW32\r\n] 2006.190.08:16:12.84#ibcon#*before write, iclass 36, count 0 2006.190.08:16:12.84#ibcon#enter sib2, iclass 36, count 0 2006.190.08:16:12.84#ibcon#flushed, iclass 36, count 0 2006.190.08:16:12.84#ibcon#about to write, iclass 36, count 0 2006.190.08:16:12.84#ibcon#wrote, iclass 36, count 0 2006.190.08:16:12.84#ibcon#about to read 3, iclass 36, count 0 2006.190.08:16:12.87#ibcon#read 3, iclass 36, count 0 2006.190.08:16:12.87#ibcon#about to read 4, iclass 36, count 0 2006.190.08:16:12.87#ibcon#read 4, iclass 36, count 0 2006.190.08:16:12.87#ibcon#about to read 5, iclass 36, count 0 2006.190.08:16:12.87#ibcon#read 5, iclass 36, count 0 2006.190.08:16:12.87#ibcon#about to read 6, iclass 36, count 0 2006.190.08:16:12.87#ibcon#read 6, iclass 36, count 0 2006.190.08:16:12.87#ibcon#end of sib2, iclass 36, count 0 2006.190.08:16:12.87#ibcon#*after write, iclass 36, count 0 2006.190.08:16:12.87#ibcon#*before return 0, iclass 36, count 0 2006.190.08:16:12.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:16:12.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:16:12.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:16:12.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:16:12.87$4f8m12a/ifd4f 2006.190.08:16:12.87$ifd4f/lo= 2006.190.08:16:12.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:16:12.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:16:12.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:16:12.87$ifd4f/patch= 2006.190.08:16:12.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:16:12.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:16:12.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:16:12.87$4f8m12a/"form=m,16.000,1:2 2006.190.08:16:12.87$4f8m12a/"tpicd 2006.190.08:16:12.87$4f8m12a/echo=off 2006.190.08:16:12.87$4f8m12a/xlog=off 2006.190.08:16:12.87:!2006.190.08:16:40 2006.190.08:16:19.14#trakl#Source acquired 2006.190.08:16:19.14#flagr#flagr/antenna,acquired 2006.190.08:16:40.00:preob 2006.190.08:16:41.14/onsource/TRACKING 2006.190.08:16:41.14:!2006.190.08:16:50 2006.190.08:16:50.00:data_valid=on 2006.190.08:16:50.00:midob 2006.190.08:16:50.14/onsource/TRACKING 2006.190.08:16:50.14/wx/24.41,1012.1,100 2006.190.08:16:50.25/cable/+6.4717E-03 2006.190.08:16:51.34/va/01,08,usb,yes,30,31 2006.190.08:16:51.34/va/02,07,usb,yes,30,31 2006.190.08:16:51.34/va/03,06,usb,yes,32,32 2006.190.08:16:51.34/va/04,07,usb,yes,31,33 2006.190.08:16:51.34/va/05,07,usb,yes,34,35 2006.190.08:16:51.34/va/06,06,usb,yes,33,33 2006.190.08:16:51.34/va/07,06,usb,yes,33,33 2006.190.08:16:51.34/va/08,06,usb,yes,36,35 2006.190.08:16:51.57/valo/01,532.99,yes,locked 2006.190.08:16:51.57/valo/02,572.99,yes,locked 2006.190.08:16:51.57/valo/03,672.99,yes,locked 2006.190.08:16:51.57/valo/04,832.99,yes,locked 2006.190.08:16:51.57/valo/05,652.99,yes,locked 2006.190.08:16:51.57/valo/06,772.99,yes,locked 2006.190.08:16:51.57/valo/07,832.99,yes,locked 2006.190.08:16:51.57/valo/08,852.99,yes,locked 2006.190.08:16:52.66/vb/01,04,usb,yes,28,27 2006.190.08:16:52.66/vb/02,04,usb,yes,30,31 2006.190.08:16:52.66/vb/03,04,usb,yes,27,30 2006.190.08:16:52.66/vb/04,04,usb,yes,27,27 2006.190.08:16:52.66/vb/05,04,usb,yes,26,30 2006.190.08:16:52.66/vb/06,04,usb,yes,27,29 2006.190.08:16:52.66/vb/07,04,usb,yes,29,29 2006.190.08:16:52.66/vb/08,04,usb,yes,27,30 2006.190.08:16:52.90/vblo/01,632.99,yes,locked 2006.190.08:16:52.90/vblo/02,640.99,yes,locked 2006.190.08:16:52.90/vblo/03,656.99,yes,locked 2006.190.08:16:52.90/vblo/04,712.99,yes,locked 2006.190.08:16:52.90/vblo/05,744.99,yes,locked 2006.190.08:16:52.90/vblo/06,752.99,yes,locked 2006.190.08:16:52.90/vblo/07,734.99,yes,locked 2006.190.08:16:52.90/vblo/08,744.99,yes,locked 2006.190.08:16:53.05/vabw/8 2006.190.08:16:53.20/vbbw/8 2006.190.08:16:53.29/xfe/off,on,15.5 2006.190.08:16:53.68/ifatt/23,28,28,28 2006.190.08:16:54.07/fmout-gps/S +2.85E-07 2006.190.08:16:54.14:!2006.190.08:17:50 2006.190.08:17:50.01:data_valid=off 2006.190.08:17:50.01:postob 2006.190.08:17:50.17/cable/+6.4698E-03 2006.190.08:17:50.17/wx/24.41,1012.2,100 2006.190.08:17:51.07/fmout-gps/S +2.84E-07 2006.190.08:17:51.07:scan_name=190-0818,k06190,60 2006.190.08:17:51.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.190.08:17:51.14#flagr#flagr/antenna,new-source 2006.190.08:17:52.14:checkk5 2006.190.08:17:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:17:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:17:53.30/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:17:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:17:54.05/chk_obsdata//k5ts1/T1900816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:17:54.43/chk_obsdata//k5ts2/T1900816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:17:54.80/chk_obsdata//k5ts3/T1900816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:17:55.18/chk_obsdata//k5ts4/T1900816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:17:55.89/k5log//k5ts1_log_newline 2006.190.08:17:56.60/k5log//k5ts2_log_newline 2006.190.08:17:57.31/k5log//k5ts3_log_newline 2006.190.08:17:58.01/k5log//k5ts4_log_newline 2006.190.08:17:58.04/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:17:58.04:4f8m12a=2 2006.190.08:17:58.04$4f8m12a/echo=on 2006.190.08:17:58.04$4f8m12a/pcalon 2006.190.08:17:58.04$pcalon/"no phase cal control is implemented here 2006.190.08:17:58.04$4f8m12a/"tpicd=stop 2006.190.08:17:58.04$4f8m12a/vc4f8 2006.190.08:17:58.04$vc4f8/valo=1,532.99 2006.190.08:17:58.04#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.08:17:58.04#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.08:17:58.04#ibcon#ireg 17 cls_cnt 0 2006.190.08:17:58.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:17:58.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:17:58.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:17:58.04#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:17:58.04#ibcon#first serial, iclass 5, count 0 2006.190.08:17:58.04#ibcon#enter sib2, iclass 5, count 0 2006.190.08:17:58.04#ibcon#flushed, iclass 5, count 0 2006.190.08:17:58.04#ibcon#about to write, iclass 5, count 0 2006.190.08:17:58.04#ibcon#wrote, iclass 5, count 0 2006.190.08:17:58.04#ibcon#about to read 3, iclass 5, count 0 2006.190.08:17:58.09#ibcon#read 3, iclass 5, count 0 2006.190.08:17:58.09#ibcon#about to read 4, iclass 5, count 0 2006.190.08:17:58.09#ibcon#read 4, iclass 5, count 0 2006.190.08:17:58.09#ibcon#about to read 5, iclass 5, count 0 2006.190.08:17:58.09#ibcon#read 5, iclass 5, count 0 2006.190.08:17:58.09#ibcon#about to read 6, iclass 5, count 0 2006.190.08:17:58.09#ibcon#read 6, iclass 5, count 0 2006.190.08:17:58.09#ibcon#end of sib2, iclass 5, count 0 2006.190.08:17:58.09#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:17:58.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:17:58.09#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:17:58.09#ibcon#*before write, iclass 5, count 0 2006.190.08:17:58.09#ibcon#enter sib2, iclass 5, count 0 2006.190.08:17:58.09#ibcon#flushed, iclass 5, count 0 2006.190.08:17:58.09#ibcon#about to write, iclass 5, count 0 2006.190.08:17:58.09#ibcon#wrote, iclass 5, count 0 2006.190.08:17:58.09#ibcon#about to read 3, iclass 5, count 0 2006.190.08:17:58.14#ibcon#read 3, iclass 5, count 0 2006.190.08:17:58.14#ibcon#about to read 4, iclass 5, count 0 2006.190.08:17:58.14#ibcon#read 4, iclass 5, count 0 2006.190.08:17:58.14#ibcon#about to read 5, iclass 5, count 0 2006.190.08:17:58.14#ibcon#read 5, iclass 5, count 0 2006.190.08:17:58.14#ibcon#about to read 6, iclass 5, count 0 2006.190.08:17:58.14#ibcon#read 6, iclass 5, count 0 2006.190.08:17:58.14#ibcon#end of sib2, iclass 5, count 0 2006.190.08:17:58.14#ibcon#*after write, iclass 5, count 0 2006.190.08:17:58.14#ibcon#*before return 0, iclass 5, count 0 2006.190.08:17:58.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:17:58.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:17:58.14#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:17:58.14#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:17:58.14$vc4f8/va=1,8 2006.190.08:17:58.14#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.08:17:58.14#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.08:17:58.14#ibcon#ireg 11 cls_cnt 2 2006.190.08:17:58.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:17:58.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:17:58.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:17:58.14#ibcon#enter wrdev, iclass 7, count 2 2006.190.08:17:58.14#ibcon#first serial, iclass 7, count 2 2006.190.08:17:58.14#ibcon#enter sib2, iclass 7, count 2 2006.190.08:17:58.14#ibcon#flushed, iclass 7, count 2 2006.190.08:17:58.14#ibcon#about to write, iclass 7, count 2 2006.190.08:17:58.14#ibcon#wrote, iclass 7, count 2 2006.190.08:17:58.14#ibcon#about to read 3, iclass 7, count 2 2006.190.08:17:58.17#ibcon#read 3, iclass 7, count 2 2006.190.08:17:58.17#ibcon#about to read 4, iclass 7, count 2 2006.190.08:17:58.17#ibcon#read 4, iclass 7, count 2 2006.190.08:17:58.17#ibcon#about to read 5, iclass 7, count 2 2006.190.08:17:58.17#ibcon#read 5, iclass 7, count 2 2006.190.08:17:58.17#ibcon#about to read 6, iclass 7, count 2 2006.190.08:17:58.17#ibcon#read 6, iclass 7, count 2 2006.190.08:17:58.17#ibcon#end of sib2, iclass 7, count 2 2006.190.08:17:58.17#ibcon#*mode == 0, iclass 7, count 2 2006.190.08:17:58.17#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.08:17:58.17#ibcon#[25=AT01-08\r\n] 2006.190.08:17:58.17#ibcon#*before write, iclass 7, count 2 2006.190.08:17:58.17#ibcon#enter sib2, iclass 7, count 2 2006.190.08:17:58.17#ibcon#flushed, iclass 7, count 2 2006.190.08:17:58.17#ibcon#about to write, iclass 7, count 2 2006.190.08:17:58.17#ibcon#wrote, iclass 7, count 2 2006.190.08:17:58.17#ibcon#about to read 3, iclass 7, count 2 2006.190.08:17:58.20#ibcon#read 3, iclass 7, count 2 2006.190.08:17:58.20#ibcon#about to read 4, iclass 7, count 2 2006.190.08:17:58.20#ibcon#read 4, iclass 7, count 2 2006.190.08:17:58.20#ibcon#about to read 5, iclass 7, count 2 2006.190.08:17:58.20#ibcon#read 5, iclass 7, count 2 2006.190.08:17:58.20#ibcon#about to read 6, iclass 7, count 2 2006.190.08:17:58.20#ibcon#read 6, iclass 7, count 2 2006.190.08:17:58.20#ibcon#end of sib2, iclass 7, count 2 2006.190.08:17:58.20#ibcon#*after write, iclass 7, count 2 2006.190.08:17:58.20#ibcon#*before return 0, iclass 7, count 2 2006.190.08:17:58.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:17:58.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:17:58.20#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.08:17:58.20#ibcon#ireg 7 cls_cnt 0 2006.190.08:17:58.20#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:17:58.32#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:17:58.32#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:17:58.32#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:17:58.32#ibcon#first serial, iclass 7, count 0 2006.190.08:17:58.32#ibcon#enter sib2, iclass 7, count 0 2006.190.08:17:58.32#ibcon#flushed, iclass 7, count 0 2006.190.08:17:58.32#ibcon#about to write, iclass 7, count 0 2006.190.08:17:58.32#ibcon#wrote, iclass 7, count 0 2006.190.08:17:58.32#ibcon#about to read 3, iclass 7, count 0 2006.190.08:17:58.34#ibcon#read 3, iclass 7, count 0 2006.190.08:17:58.34#ibcon#about to read 4, iclass 7, count 0 2006.190.08:17:58.34#ibcon#read 4, iclass 7, count 0 2006.190.08:17:58.34#ibcon#about to read 5, iclass 7, count 0 2006.190.08:17:58.34#ibcon#read 5, iclass 7, count 0 2006.190.08:17:58.34#ibcon#about to read 6, iclass 7, count 0 2006.190.08:17:58.34#ibcon#read 6, iclass 7, count 0 2006.190.08:17:58.34#ibcon#end of sib2, iclass 7, count 0 2006.190.08:17:58.34#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:17:58.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:17:58.34#ibcon#[25=USB\r\n] 2006.190.08:17:58.34#ibcon#*before write, iclass 7, count 0 2006.190.08:17:58.34#ibcon#enter sib2, iclass 7, count 0 2006.190.08:17:58.34#ibcon#flushed, iclass 7, count 0 2006.190.08:17:58.34#ibcon#about to write, iclass 7, count 0 2006.190.08:17:58.34#ibcon#wrote, iclass 7, count 0 2006.190.08:17:58.34#ibcon#about to read 3, iclass 7, count 0 2006.190.08:17:58.37#ibcon#read 3, iclass 7, count 0 2006.190.08:17:58.37#ibcon#about to read 4, iclass 7, count 0 2006.190.08:17:58.37#ibcon#read 4, iclass 7, count 0 2006.190.08:17:58.37#ibcon#about to read 5, iclass 7, count 0 2006.190.08:17:58.37#ibcon#read 5, iclass 7, count 0 2006.190.08:17:58.37#ibcon#about to read 6, iclass 7, count 0 2006.190.08:17:58.37#ibcon#read 6, iclass 7, count 0 2006.190.08:17:58.37#ibcon#end of sib2, iclass 7, count 0 2006.190.08:17:58.37#ibcon#*after write, iclass 7, count 0 2006.190.08:17:58.37#ibcon#*before return 0, iclass 7, count 0 2006.190.08:17:58.37#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:17:58.37#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:17:58.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:17:58.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:17:58.37$vc4f8/valo=2,572.99 2006.190.08:17:58.37#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.08:17:58.37#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.08:17:58.37#ibcon#ireg 17 cls_cnt 0 2006.190.08:17:58.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:17:58.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:17:58.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:17:58.37#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:17:58.37#ibcon#first serial, iclass 11, count 0 2006.190.08:17:58.37#ibcon#enter sib2, iclass 11, count 0 2006.190.08:17:58.37#ibcon#flushed, iclass 11, count 0 2006.190.08:17:58.37#ibcon#about to write, iclass 11, count 0 2006.190.08:17:58.37#ibcon#wrote, iclass 11, count 0 2006.190.08:17:58.37#ibcon#about to read 3, iclass 11, count 0 2006.190.08:17:58.39#ibcon#read 3, iclass 11, count 0 2006.190.08:17:58.39#ibcon#about to read 4, iclass 11, count 0 2006.190.08:17:58.39#ibcon#read 4, iclass 11, count 0 2006.190.08:17:58.39#ibcon#about to read 5, iclass 11, count 0 2006.190.08:17:58.39#ibcon#read 5, iclass 11, count 0 2006.190.08:17:58.39#ibcon#about to read 6, iclass 11, count 0 2006.190.08:17:58.39#ibcon#read 6, iclass 11, count 0 2006.190.08:17:58.39#ibcon#end of sib2, iclass 11, count 0 2006.190.08:17:58.39#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:17:58.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:17:58.39#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:17:58.39#ibcon#*before write, iclass 11, count 0 2006.190.08:17:58.39#ibcon#enter sib2, iclass 11, count 0 2006.190.08:17:58.39#ibcon#flushed, iclass 11, count 0 2006.190.08:17:58.39#ibcon#about to write, iclass 11, count 0 2006.190.08:17:58.39#ibcon#wrote, iclass 11, count 0 2006.190.08:17:58.39#ibcon#about to read 3, iclass 11, count 0 2006.190.08:17:58.43#ibcon#read 3, iclass 11, count 0 2006.190.08:17:58.43#ibcon#about to read 4, iclass 11, count 0 2006.190.08:17:58.43#ibcon#read 4, iclass 11, count 0 2006.190.08:17:58.43#ibcon#about to read 5, iclass 11, count 0 2006.190.08:17:58.43#ibcon#read 5, iclass 11, count 0 2006.190.08:17:58.43#ibcon#about to read 6, iclass 11, count 0 2006.190.08:17:58.43#ibcon#read 6, iclass 11, count 0 2006.190.08:17:58.43#ibcon#end of sib2, iclass 11, count 0 2006.190.08:17:58.43#ibcon#*after write, iclass 11, count 0 2006.190.08:17:58.43#ibcon#*before return 0, iclass 11, count 0 2006.190.08:17:58.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:17:58.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:17:58.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:17:58.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:17:58.43$vc4f8/va=2,7 2006.190.08:17:58.43#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.08:17:58.43#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.08:17:58.43#ibcon#ireg 11 cls_cnt 2 2006.190.08:17:58.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:17:58.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:17:58.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:17:58.49#ibcon#enter wrdev, iclass 13, count 2 2006.190.08:17:58.49#ibcon#first serial, iclass 13, count 2 2006.190.08:17:58.49#ibcon#enter sib2, iclass 13, count 2 2006.190.08:17:58.49#ibcon#flushed, iclass 13, count 2 2006.190.08:17:58.49#ibcon#about to write, iclass 13, count 2 2006.190.08:17:58.49#ibcon#wrote, iclass 13, count 2 2006.190.08:17:58.49#ibcon#about to read 3, iclass 13, count 2 2006.190.08:17:58.51#ibcon#read 3, iclass 13, count 2 2006.190.08:17:58.51#ibcon#about to read 4, iclass 13, count 2 2006.190.08:17:58.51#ibcon#read 4, iclass 13, count 2 2006.190.08:17:58.51#ibcon#about to read 5, iclass 13, count 2 2006.190.08:17:58.51#ibcon#read 5, iclass 13, count 2 2006.190.08:17:58.51#ibcon#about to read 6, iclass 13, count 2 2006.190.08:17:58.51#ibcon#read 6, iclass 13, count 2 2006.190.08:17:58.51#ibcon#end of sib2, iclass 13, count 2 2006.190.08:17:58.51#ibcon#*mode == 0, iclass 13, count 2 2006.190.08:17:58.51#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.08:17:58.51#ibcon#[25=AT02-07\r\n] 2006.190.08:17:58.51#ibcon#*before write, iclass 13, count 2 2006.190.08:17:58.51#ibcon#enter sib2, iclass 13, count 2 2006.190.08:17:58.51#ibcon#flushed, iclass 13, count 2 2006.190.08:17:58.51#ibcon#about to write, iclass 13, count 2 2006.190.08:17:58.51#ibcon#wrote, iclass 13, count 2 2006.190.08:17:58.51#ibcon#about to read 3, iclass 13, count 2 2006.190.08:17:58.54#ibcon#read 3, iclass 13, count 2 2006.190.08:17:58.54#ibcon#about to read 4, iclass 13, count 2 2006.190.08:17:58.54#ibcon#read 4, iclass 13, count 2 2006.190.08:17:58.54#ibcon#about to read 5, iclass 13, count 2 2006.190.08:17:58.54#ibcon#read 5, iclass 13, count 2 2006.190.08:17:58.54#ibcon#about to read 6, iclass 13, count 2 2006.190.08:17:58.54#ibcon#read 6, iclass 13, count 2 2006.190.08:17:58.54#ibcon#end of sib2, iclass 13, count 2 2006.190.08:17:58.54#ibcon#*after write, iclass 13, count 2 2006.190.08:17:58.54#ibcon#*before return 0, iclass 13, count 2 2006.190.08:17:58.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:17:58.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:17:58.54#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.08:17:58.54#ibcon#ireg 7 cls_cnt 0 2006.190.08:17:58.54#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:17:58.66#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:17:58.66#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:17:58.66#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:17:58.66#ibcon#first serial, iclass 13, count 0 2006.190.08:17:58.66#ibcon#enter sib2, iclass 13, count 0 2006.190.08:17:58.66#ibcon#flushed, iclass 13, count 0 2006.190.08:17:58.66#ibcon#about to write, iclass 13, count 0 2006.190.08:17:58.66#ibcon#wrote, iclass 13, count 0 2006.190.08:17:58.66#ibcon#about to read 3, iclass 13, count 0 2006.190.08:17:58.68#ibcon#read 3, iclass 13, count 0 2006.190.08:17:58.68#ibcon#about to read 4, iclass 13, count 0 2006.190.08:17:58.68#ibcon#read 4, iclass 13, count 0 2006.190.08:17:58.68#ibcon#about to read 5, iclass 13, count 0 2006.190.08:17:58.68#ibcon#read 5, iclass 13, count 0 2006.190.08:17:58.68#ibcon#about to read 6, iclass 13, count 0 2006.190.08:17:58.68#ibcon#read 6, iclass 13, count 0 2006.190.08:17:58.68#ibcon#end of sib2, iclass 13, count 0 2006.190.08:17:58.68#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:17:58.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:17:58.68#ibcon#[25=USB\r\n] 2006.190.08:17:58.68#ibcon#*before write, iclass 13, count 0 2006.190.08:17:58.68#ibcon#enter sib2, iclass 13, count 0 2006.190.08:17:58.68#ibcon#flushed, iclass 13, count 0 2006.190.08:17:58.68#ibcon#about to write, iclass 13, count 0 2006.190.08:17:58.68#ibcon#wrote, iclass 13, count 0 2006.190.08:17:58.68#ibcon#about to read 3, iclass 13, count 0 2006.190.08:17:58.71#ibcon#read 3, iclass 13, count 0 2006.190.08:17:58.71#ibcon#about to read 4, iclass 13, count 0 2006.190.08:17:58.71#ibcon#read 4, iclass 13, count 0 2006.190.08:17:58.71#ibcon#about to read 5, iclass 13, count 0 2006.190.08:17:58.71#ibcon#read 5, iclass 13, count 0 2006.190.08:17:58.71#ibcon#about to read 6, iclass 13, count 0 2006.190.08:17:58.71#ibcon#read 6, iclass 13, count 0 2006.190.08:17:58.71#ibcon#end of sib2, iclass 13, count 0 2006.190.08:17:58.71#ibcon#*after write, iclass 13, count 0 2006.190.08:17:58.71#ibcon#*before return 0, iclass 13, count 0 2006.190.08:17:58.71#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:17:58.71#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:17:58.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:17:58.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:17:58.71$vc4f8/valo=3,672.99 2006.190.08:17:58.71#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.08:17:58.71#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.08:17:58.71#ibcon#ireg 17 cls_cnt 0 2006.190.08:17:58.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:17:58.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:17:58.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:17:58.71#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:17:58.71#ibcon#first serial, iclass 15, count 0 2006.190.08:17:58.71#ibcon#enter sib2, iclass 15, count 0 2006.190.08:17:58.71#ibcon#flushed, iclass 15, count 0 2006.190.08:17:58.71#ibcon#about to write, iclass 15, count 0 2006.190.08:17:58.71#ibcon#wrote, iclass 15, count 0 2006.190.08:17:58.71#ibcon#about to read 3, iclass 15, count 0 2006.190.08:17:58.73#ibcon#read 3, iclass 15, count 0 2006.190.08:17:58.73#ibcon#about to read 4, iclass 15, count 0 2006.190.08:17:58.73#ibcon#read 4, iclass 15, count 0 2006.190.08:17:58.73#ibcon#about to read 5, iclass 15, count 0 2006.190.08:17:58.73#ibcon#read 5, iclass 15, count 0 2006.190.08:17:58.73#ibcon#about to read 6, iclass 15, count 0 2006.190.08:17:58.73#ibcon#read 6, iclass 15, count 0 2006.190.08:17:58.73#ibcon#end of sib2, iclass 15, count 0 2006.190.08:17:58.73#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:17:58.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:17:58.73#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:17:58.73#ibcon#*before write, iclass 15, count 0 2006.190.08:17:58.73#ibcon#enter sib2, iclass 15, count 0 2006.190.08:17:58.73#ibcon#flushed, iclass 15, count 0 2006.190.08:17:58.73#ibcon#about to write, iclass 15, count 0 2006.190.08:17:58.73#ibcon#wrote, iclass 15, count 0 2006.190.08:17:58.73#ibcon#about to read 3, iclass 15, count 0 2006.190.08:17:58.77#ibcon#read 3, iclass 15, count 0 2006.190.08:17:58.77#ibcon#about to read 4, iclass 15, count 0 2006.190.08:17:58.77#ibcon#read 4, iclass 15, count 0 2006.190.08:17:58.77#ibcon#about to read 5, iclass 15, count 0 2006.190.08:17:58.77#ibcon#read 5, iclass 15, count 0 2006.190.08:17:58.77#ibcon#about to read 6, iclass 15, count 0 2006.190.08:17:58.77#ibcon#read 6, iclass 15, count 0 2006.190.08:17:58.77#ibcon#end of sib2, iclass 15, count 0 2006.190.08:17:58.77#ibcon#*after write, iclass 15, count 0 2006.190.08:17:58.77#ibcon#*before return 0, iclass 15, count 0 2006.190.08:17:58.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:17:58.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:17:58.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:17:58.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:17:58.77$vc4f8/va=3,6 2006.190.08:17:58.77#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.08:17:58.77#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.08:17:58.77#ibcon#ireg 11 cls_cnt 2 2006.190.08:17:58.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:17:58.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:17:58.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:17:58.83#ibcon#enter wrdev, iclass 17, count 2 2006.190.08:17:58.83#ibcon#first serial, iclass 17, count 2 2006.190.08:17:58.83#ibcon#enter sib2, iclass 17, count 2 2006.190.08:17:58.83#ibcon#flushed, iclass 17, count 2 2006.190.08:17:58.83#ibcon#about to write, iclass 17, count 2 2006.190.08:17:58.83#ibcon#wrote, iclass 17, count 2 2006.190.08:17:58.83#ibcon#about to read 3, iclass 17, count 2 2006.190.08:17:58.85#ibcon#read 3, iclass 17, count 2 2006.190.08:17:58.85#ibcon#about to read 4, iclass 17, count 2 2006.190.08:17:58.85#ibcon#read 4, iclass 17, count 2 2006.190.08:17:58.85#ibcon#about to read 5, iclass 17, count 2 2006.190.08:17:58.85#ibcon#read 5, iclass 17, count 2 2006.190.08:17:58.85#ibcon#about to read 6, iclass 17, count 2 2006.190.08:17:58.85#ibcon#read 6, iclass 17, count 2 2006.190.08:17:58.85#ibcon#end of sib2, iclass 17, count 2 2006.190.08:17:58.85#ibcon#*mode == 0, iclass 17, count 2 2006.190.08:17:58.85#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.08:17:58.85#ibcon#[25=AT03-06\r\n] 2006.190.08:17:58.85#ibcon#*before write, iclass 17, count 2 2006.190.08:17:58.85#ibcon#enter sib2, iclass 17, count 2 2006.190.08:17:58.85#ibcon#flushed, iclass 17, count 2 2006.190.08:17:58.85#ibcon#about to write, iclass 17, count 2 2006.190.08:17:58.85#ibcon#wrote, iclass 17, count 2 2006.190.08:17:58.85#ibcon#about to read 3, iclass 17, count 2 2006.190.08:17:58.88#ibcon#read 3, iclass 17, count 2 2006.190.08:17:58.88#ibcon#about to read 4, iclass 17, count 2 2006.190.08:17:58.88#ibcon#read 4, iclass 17, count 2 2006.190.08:17:58.88#ibcon#about to read 5, iclass 17, count 2 2006.190.08:17:58.88#ibcon#read 5, iclass 17, count 2 2006.190.08:17:58.88#ibcon#about to read 6, iclass 17, count 2 2006.190.08:17:58.88#ibcon#read 6, iclass 17, count 2 2006.190.08:17:58.88#ibcon#end of sib2, iclass 17, count 2 2006.190.08:17:58.88#ibcon#*after write, iclass 17, count 2 2006.190.08:17:58.88#ibcon#*before return 0, iclass 17, count 2 2006.190.08:17:58.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:17:58.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:17:58.88#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.08:17:58.88#ibcon#ireg 7 cls_cnt 0 2006.190.08:17:58.88#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:17:59.00#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:17:59.00#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:17:59.00#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:17:59.00#ibcon#first serial, iclass 17, count 0 2006.190.08:17:59.00#ibcon#enter sib2, iclass 17, count 0 2006.190.08:17:59.00#ibcon#flushed, iclass 17, count 0 2006.190.08:17:59.00#ibcon#about to write, iclass 17, count 0 2006.190.08:17:59.00#ibcon#wrote, iclass 17, count 0 2006.190.08:17:59.00#ibcon#about to read 3, iclass 17, count 0 2006.190.08:17:59.02#ibcon#read 3, iclass 17, count 0 2006.190.08:17:59.02#ibcon#about to read 4, iclass 17, count 0 2006.190.08:17:59.02#ibcon#read 4, iclass 17, count 0 2006.190.08:17:59.02#ibcon#about to read 5, iclass 17, count 0 2006.190.08:17:59.02#ibcon#read 5, iclass 17, count 0 2006.190.08:17:59.02#ibcon#about to read 6, iclass 17, count 0 2006.190.08:17:59.02#ibcon#read 6, iclass 17, count 0 2006.190.08:17:59.02#ibcon#end of sib2, iclass 17, count 0 2006.190.08:17:59.02#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:17:59.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:17:59.02#ibcon#[25=USB\r\n] 2006.190.08:17:59.02#ibcon#*before write, iclass 17, count 0 2006.190.08:17:59.02#ibcon#enter sib2, iclass 17, count 0 2006.190.08:17:59.02#ibcon#flushed, iclass 17, count 0 2006.190.08:17:59.02#ibcon#about to write, iclass 17, count 0 2006.190.08:17:59.02#ibcon#wrote, iclass 17, count 0 2006.190.08:17:59.02#ibcon#about to read 3, iclass 17, count 0 2006.190.08:17:59.05#ibcon#read 3, iclass 17, count 0 2006.190.08:17:59.05#ibcon#about to read 4, iclass 17, count 0 2006.190.08:17:59.05#ibcon#read 4, iclass 17, count 0 2006.190.08:17:59.05#ibcon#about to read 5, iclass 17, count 0 2006.190.08:17:59.05#ibcon#read 5, iclass 17, count 0 2006.190.08:17:59.05#ibcon#about to read 6, iclass 17, count 0 2006.190.08:17:59.05#ibcon#read 6, iclass 17, count 0 2006.190.08:17:59.05#ibcon#end of sib2, iclass 17, count 0 2006.190.08:17:59.05#ibcon#*after write, iclass 17, count 0 2006.190.08:17:59.05#ibcon#*before return 0, iclass 17, count 0 2006.190.08:17:59.05#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:17:59.05#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:17:59.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:17:59.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:17:59.05$vc4f8/valo=4,832.99 2006.190.08:17:59.05#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.08:17:59.05#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.08:17:59.05#ibcon#ireg 17 cls_cnt 0 2006.190.08:17:59.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:17:59.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:17:59.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:17:59.05#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:17:59.05#ibcon#first serial, iclass 19, count 0 2006.190.08:17:59.05#ibcon#enter sib2, iclass 19, count 0 2006.190.08:17:59.05#ibcon#flushed, iclass 19, count 0 2006.190.08:17:59.05#ibcon#about to write, iclass 19, count 0 2006.190.08:17:59.05#ibcon#wrote, iclass 19, count 0 2006.190.08:17:59.05#ibcon#about to read 3, iclass 19, count 0 2006.190.08:17:59.07#ibcon#read 3, iclass 19, count 0 2006.190.08:17:59.07#ibcon#about to read 4, iclass 19, count 0 2006.190.08:17:59.07#ibcon#read 4, iclass 19, count 0 2006.190.08:17:59.07#ibcon#about to read 5, iclass 19, count 0 2006.190.08:17:59.07#ibcon#read 5, iclass 19, count 0 2006.190.08:17:59.07#ibcon#about to read 6, iclass 19, count 0 2006.190.08:17:59.07#ibcon#read 6, iclass 19, count 0 2006.190.08:17:59.07#ibcon#end of sib2, iclass 19, count 0 2006.190.08:17:59.07#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:17:59.07#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:17:59.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:17:59.07#ibcon#*before write, iclass 19, count 0 2006.190.08:17:59.07#ibcon#enter sib2, iclass 19, count 0 2006.190.08:17:59.07#ibcon#flushed, iclass 19, count 0 2006.190.08:17:59.07#ibcon#about to write, iclass 19, count 0 2006.190.08:17:59.07#ibcon#wrote, iclass 19, count 0 2006.190.08:17:59.07#ibcon#about to read 3, iclass 19, count 0 2006.190.08:17:59.11#ibcon#read 3, iclass 19, count 0 2006.190.08:17:59.11#ibcon#about to read 4, iclass 19, count 0 2006.190.08:17:59.11#ibcon#read 4, iclass 19, count 0 2006.190.08:17:59.11#ibcon#about to read 5, iclass 19, count 0 2006.190.08:17:59.11#ibcon#read 5, iclass 19, count 0 2006.190.08:17:59.11#ibcon#about to read 6, iclass 19, count 0 2006.190.08:17:59.11#ibcon#read 6, iclass 19, count 0 2006.190.08:17:59.11#ibcon#end of sib2, iclass 19, count 0 2006.190.08:17:59.11#ibcon#*after write, iclass 19, count 0 2006.190.08:17:59.11#ibcon#*before return 0, iclass 19, count 0 2006.190.08:17:59.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:17:59.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:17:59.11#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:17:59.11#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:17:59.11$vc4f8/va=4,7 2006.190.08:17:59.11#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.08:17:59.11#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.08:17:59.11#ibcon#ireg 11 cls_cnt 2 2006.190.08:17:59.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:17:59.17#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:17:59.17#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:17:59.17#ibcon#enter wrdev, iclass 21, count 2 2006.190.08:17:59.17#ibcon#first serial, iclass 21, count 2 2006.190.08:17:59.17#ibcon#enter sib2, iclass 21, count 2 2006.190.08:17:59.17#ibcon#flushed, iclass 21, count 2 2006.190.08:17:59.17#ibcon#about to write, iclass 21, count 2 2006.190.08:17:59.17#ibcon#wrote, iclass 21, count 2 2006.190.08:17:59.17#ibcon#about to read 3, iclass 21, count 2 2006.190.08:17:59.19#ibcon#read 3, iclass 21, count 2 2006.190.08:17:59.19#ibcon#about to read 4, iclass 21, count 2 2006.190.08:17:59.19#ibcon#read 4, iclass 21, count 2 2006.190.08:17:59.19#ibcon#about to read 5, iclass 21, count 2 2006.190.08:17:59.19#ibcon#read 5, iclass 21, count 2 2006.190.08:17:59.19#ibcon#about to read 6, iclass 21, count 2 2006.190.08:17:59.19#ibcon#read 6, iclass 21, count 2 2006.190.08:17:59.19#ibcon#end of sib2, iclass 21, count 2 2006.190.08:17:59.19#ibcon#*mode == 0, iclass 21, count 2 2006.190.08:17:59.19#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.08:17:59.19#ibcon#[25=AT04-07\r\n] 2006.190.08:17:59.19#ibcon#*before write, iclass 21, count 2 2006.190.08:17:59.19#ibcon#enter sib2, iclass 21, count 2 2006.190.08:17:59.19#ibcon#flushed, iclass 21, count 2 2006.190.08:17:59.19#ibcon#about to write, iclass 21, count 2 2006.190.08:17:59.19#ibcon#wrote, iclass 21, count 2 2006.190.08:17:59.19#ibcon#about to read 3, iclass 21, count 2 2006.190.08:17:59.22#ibcon#read 3, iclass 21, count 2 2006.190.08:17:59.22#ibcon#about to read 4, iclass 21, count 2 2006.190.08:17:59.22#ibcon#read 4, iclass 21, count 2 2006.190.08:17:59.22#ibcon#about to read 5, iclass 21, count 2 2006.190.08:17:59.22#ibcon#read 5, iclass 21, count 2 2006.190.08:17:59.22#ibcon#about to read 6, iclass 21, count 2 2006.190.08:17:59.22#ibcon#read 6, iclass 21, count 2 2006.190.08:17:59.22#ibcon#end of sib2, iclass 21, count 2 2006.190.08:17:59.22#ibcon#*after write, iclass 21, count 2 2006.190.08:17:59.22#ibcon#*before return 0, iclass 21, count 2 2006.190.08:17:59.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:17:59.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:17:59.22#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.08:17:59.22#ibcon#ireg 7 cls_cnt 0 2006.190.08:17:59.22#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:17:59.34#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:17:59.34#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:17:59.34#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:17:59.34#ibcon#first serial, iclass 21, count 0 2006.190.08:17:59.34#ibcon#enter sib2, iclass 21, count 0 2006.190.08:17:59.34#ibcon#flushed, iclass 21, count 0 2006.190.08:17:59.34#ibcon#about to write, iclass 21, count 0 2006.190.08:17:59.34#ibcon#wrote, iclass 21, count 0 2006.190.08:17:59.34#ibcon#about to read 3, iclass 21, count 0 2006.190.08:17:59.36#ibcon#read 3, iclass 21, count 0 2006.190.08:17:59.36#ibcon#about to read 4, iclass 21, count 0 2006.190.08:17:59.36#ibcon#read 4, iclass 21, count 0 2006.190.08:17:59.36#ibcon#about to read 5, iclass 21, count 0 2006.190.08:17:59.36#ibcon#read 5, iclass 21, count 0 2006.190.08:17:59.36#ibcon#about to read 6, iclass 21, count 0 2006.190.08:17:59.36#ibcon#read 6, iclass 21, count 0 2006.190.08:17:59.36#ibcon#end of sib2, iclass 21, count 0 2006.190.08:17:59.36#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:17:59.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:17:59.36#ibcon#[25=USB\r\n] 2006.190.08:17:59.36#ibcon#*before write, iclass 21, count 0 2006.190.08:17:59.36#ibcon#enter sib2, iclass 21, count 0 2006.190.08:17:59.36#ibcon#flushed, iclass 21, count 0 2006.190.08:17:59.36#ibcon#about to write, iclass 21, count 0 2006.190.08:17:59.36#ibcon#wrote, iclass 21, count 0 2006.190.08:17:59.36#ibcon#about to read 3, iclass 21, count 0 2006.190.08:17:59.39#ibcon#read 3, iclass 21, count 0 2006.190.08:17:59.39#ibcon#about to read 4, iclass 21, count 0 2006.190.08:17:59.39#ibcon#read 4, iclass 21, count 0 2006.190.08:17:59.39#ibcon#about to read 5, iclass 21, count 0 2006.190.08:17:59.39#ibcon#read 5, iclass 21, count 0 2006.190.08:17:59.39#ibcon#about to read 6, iclass 21, count 0 2006.190.08:17:59.39#ibcon#read 6, iclass 21, count 0 2006.190.08:17:59.39#ibcon#end of sib2, iclass 21, count 0 2006.190.08:17:59.39#ibcon#*after write, iclass 21, count 0 2006.190.08:17:59.39#ibcon#*before return 0, iclass 21, count 0 2006.190.08:17:59.39#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:17:59.39#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:17:59.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:17:59.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:17:59.39$vc4f8/valo=5,652.99 2006.190.08:17:59.39#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.08:17:59.39#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.08:17:59.39#ibcon#ireg 17 cls_cnt 0 2006.190.08:17:59.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:17:59.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:17:59.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:17:59.39#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:17:59.39#ibcon#first serial, iclass 23, count 0 2006.190.08:17:59.39#ibcon#enter sib2, iclass 23, count 0 2006.190.08:17:59.39#ibcon#flushed, iclass 23, count 0 2006.190.08:17:59.39#ibcon#about to write, iclass 23, count 0 2006.190.08:17:59.39#ibcon#wrote, iclass 23, count 0 2006.190.08:17:59.39#ibcon#about to read 3, iclass 23, count 0 2006.190.08:17:59.41#ibcon#read 3, iclass 23, count 0 2006.190.08:17:59.41#ibcon#about to read 4, iclass 23, count 0 2006.190.08:17:59.41#ibcon#read 4, iclass 23, count 0 2006.190.08:17:59.41#ibcon#about to read 5, iclass 23, count 0 2006.190.08:17:59.41#ibcon#read 5, iclass 23, count 0 2006.190.08:17:59.41#ibcon#about to read 6, iclass 23, count 0 2006.190.08:17:59.41#ibcon#read 6, iclass 23, count 0 2006.190.08:17:59.41#ibcon#end of sib2, iclass 23, count 0 2006.190.08:17:59.41#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:17:59.41#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:17:59.41#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:17:59.41#ibcon#*before write, iclass 23, count 0 2006.190.08:17:59.41#ibcon#enter sib2, iclass 23, count 0 2006.190.08:17:59.41#ibcon#flushed, iclass 23, count 0 2006.190.08:17:59.41#ibcon#about to write, iclass 23, count 0 2006.190.08:17:59.41#ibcon#wrote, iclass 23, count 0 2006.190.08:17:59.41#ibcon#about to read 3, iclass 23, count 0 2006.190.08:17:59.45#ibcon#read 3, iclass 23, count 0 2006.190.08:17:59.45#ibcon#about to read 4, iclass 23, count 0 2006.190.08:17:59.45#ibcon#read 4, iclass 23, count 0 2006.190.08:17:59.45#ibcon#about to read 5, iclass 23, count 0 2006.190.08:17:59.45#ibcon#read 5, iclass 23, count 0 2006.190.08:17:59.45#ibcon#about to read 6, iclass 23, count 0 2006.190.08:17:59.45#ibcon#read 6, iclass 23, count 0 2006.190.08:17:59.45#ibcon#end of sib2, iclass 23, count 0 2006.190.08:17:59.45#ibcon#*after write, iclass 23, count 0 2006.190.08:17:59.45#ibcon#*before return 0, iclass 23, count 0 2006.190.08:17:59.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:17:59.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:17:59.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:17:59.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:17:59.45$vc4f8/va=5,7 2006.190.08:17:59.45#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.08:17:59.45#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.08:17:59.45#ibcon#ireg 11 cls_cnt 2 2006.190.08:17:59.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:17:59.51#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:17:59.51#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:17:59.51#ibcon#enter wrdev, iclass 25, count 2 2006.190.08:17:59.51#ibcon#first serial, iclass 25, count 2 2006.190.08:17:59.51#ibcon#enter sib2, iclass 25, count 2 2006.190.08:17:59.51#ibcon#flushed, iclass 25, count 2 2006.190.08:17:59.51#ibcon#about to write, iclass 25, count 2 2006.190.08:17:59.51#ibcon#wrote, iclass 25, count 2 2006.190.08:17:59.51#ibcon#about to read 3, iclass 25, count 2 2006.190.08:17:59.53#ibcon#read 3, iclass 25, count 2 2006.190.08:17:59.53#ibcon#about to read 4, iclass 25, count 2 2006.190.08:17:59.53#ibcon#read 4, iclass 25, count 2 2006.190.08:17:59.53#ibcon#about to read 5, iclass 25, count 2 2006.190.08:17:59.53#ibcon#read 5, iclass 25, count 2 2006.190.08:17:59.53#ibcon#about to read 6, iclass 25, count 2 2006.190.08:17:59.53#ibcon#read 6, iclass 25, count 2 2006.190.08:17:59.53#ibcon#end of sib2, iclass 25, count 2 2006.190.08:17:59.53#ibcon#*mode == 0, iclass 25, count 2 2006.190.08:17:59.53#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.08:17:59.53#ibcon#[25=AT05-07\r\n] 2006.190.08:17:59.53#ibcon#*before write, iclass 25, count 2 2006.190.08:17:59.53#ibcon#enter sib2, iclass 25, count 2 2006.190.08:17:59.53#ibcon#flushed, iclass 25, count 2 2006.190.08:17:59.53#ibcon#about to write, iclass 25, count 2 2006.190.08:17:59.53#ibcon#wrote, iclass 25, count 2 2006.190.08:17:59.53#ibcon#about to read 3, iclass 25, count 2 2006.190.08:17:59.56#ibcon#read 3, iclass 25, count 2 2006.190.08:17:59.56#ibcon#about to read 4, iclass 25, count 2 2006.190.08:17:59.56#ibcon#read 4, iclass 25, count 2 2006.190.08:17:59.56#ibcon#about to read 5, iclass 25, count 2 2006.190.08:17:59.56#ibcon#read 5, iclass 25, count 2 2006.190.08:17:59.56#ibcon#about to read 6, iclass 25, count 2 2006.190.08:17:59.56#ibcon#read 6, iclass 25, count 2 2006.190.08:17:59.56#ibcon#end of sib2, iclass 25, count 2 2006.190.08:17:59.56#ibcon#*after write, iclass 25, count 2 2006.190.08:17:59.56#ibcon#*before return 0, iclass 25, count 2 2006.190.08:17:59.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:17:59.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:17:59.56#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.08:17:59.56#ibcon#ireg 7 cls_cnt 0 2006.190.08:17:59.56#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:17:59.68#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:17:59.68#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:17:59.68#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:17:59.68#ibcon#first serial, iclass 25, count 0 2006.190.08:17:59.68#ibcon#enter sib2, iclass 25, count 0 2006.190.08:17:59.68#ibcon#flushed, iclass 25, count 0 2006.190.08:17:59.68#ibcon#about to write, iclass 25, count 0 2006.190.08:17:59.68#ibcon#wrote, iclass 25, count 0 2006.190.08:17:59.68#ibcon#about to read 3, iclass 25, count 0 2006.190.08:17:59.70#ibcon#read 3, iclass 25, count 0 2006.190.08:17:59.70#ibcon#about to read 4, iclass 25, count 0 2006.190.08:17:59.70#ibcon#read 4, iclass 25, count 0 2006.190.08:17:59.70#ibcon#about to read 5, iclass 25, count 0 2006.190.08:17:59.70#ibcon#read 5, iclass 25, count 0 2006.190.08:17:59.70#ibcon#about to read 6, iclass 25, count 0 2006.190.08:17:59.70#ibcon#read 6, iclass 25, count 0 2006.190.08:17:59.70#ibcon#end of sib2, iclass 25, count 0 2006.190.08:17:59.70#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:17:59.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:17:59.70#ibcon#[25=USB\r\n] 2006.190.08:17:59.70#ibcon#*before write, iclass 25, count 0 2006.190.08:17:59.70#ibcon#enter sib2, iclass 25, count 0 2006.190.08:17:59.70#ibcon#flushed, iclass 25, count 0 2006.190.08:17:59.70#ibcon#about to write, iclass 25, count 0 2006.190.08:17:59.70#ibcon#wrote, iclass 25, count 0 2006.190.08:17:59.70#ibcon#about to read 3, iclass 25, count 0 2006.190.08:17:59.73#ibcon#read 3, iclass 25, count 0 2006.190.08:17:59.73#ibcon#about to read 4, iclass 25, count 0 2006.190.08:17:59.73#ibcon#read 4, iclass 25, count 0 2006.190.08:17:59.73#ibcon#about to read 5, iclass 25, count 0 2006.190.08:17:59.73#ibcon#read 5, iclass 25, count 0 2006.190.08:17:59.73#ibcon#about to read 6, iclass 25, count 0 2006.190.08:17:59.73#ibcon#read 6, iclass 25, count 0 2006.190.08:17:59.73#ibcon#end of sib2, iclass 25, count 0 2006.190.08:17:59.73#ibcon#*after write, iclass 25, count 0 2006.190.08:17:59.73#ibcon#*before return 0, iclass 25, count 0 2006.190.08:17:59.73#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:17:59.73#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:17:59.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:17:59.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:17:59.73$vc4f8/valo=6,772.99 2006.190.08:17:59.73#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.08:17:59.73#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.08:17:59.73#ibcon#ireg 17 cls_cnt 0 2006.190.08:17:59.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:17:59.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:17:59.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:17:59.73#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:17:59.73#ibcon#first serial, iclass 27, count 0 2006.190.08:17:59.73#ibcon#enter sib2, iclass 27, count 0 2006.190.08:17:59.73#ibcon#flushed, iclass 27, count 0 2006.190.08:17:59.73#ibcon#about to write, iclass 27, count 0 2006.190.08:17:59.73#ibcon#wrote, iclass 27, count 0 2006.190.08:17:59.73#ibcon#about to read 3, iclass 27, count 0 2006.190.08:17:59.75#ibcon#read 3, iclass 27, count 0 2006.190.08:17:59.75#ibcon#about to read 4, iclass 27, count 0 2006.190.08:17:59.75#ibcon#read 4, iclass 27, count 0 2006.190.08:17:59.75#ibcon#about to read 5, iclass 27, count 0 2006.190.08:17:59.75#ibcon#read 5, iclass 27, count 0 2006.190.08:17:59.75#ibcon#about to read 6, iclass 27, count 0 2006.190.08:17:59.75#ibcon#read 6, iclass 27, count 0 2006.190.08:17:59.75#ibcon#end of sib2, iclass 27, count 0 2006.190.08:17:59.75#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:17:59.75#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:17:59.75#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:17:59.75#ibcon#*before write, iclass 27, count 0 2006.190.08:17:59.75#ibcon#enter sib2, iclass 27, count 0 2006.190.08:17:59.75#ibcon#flushed, iclass 27, count 0 2006.190.08:17:59.75#ibcon#about to write, iclass 27, count 0 2006.190.08:17:59.75#ibcon#wrote, iclass 27, count 0 2006.190.08:17:59.75#ibcon#about to read 3, iclass 27, count 0 2006.190.08:17:59.79#ibcon#read 3, iclass 27, count 0 2006.190.08:17:59.79#ibcon#about to read 4, iclass 27, count 0 2006.190.08:17:59.79#ibcon#read 4, iclass 27, count 0 2006.190.08:17:59.79#ibcon#about to read 5, iclass 27, count 0 2006.190.08:17:59.79#ibcon#read 5, iclass 27, count 0 2006.190.08:17:59.79#ibcon#about to read 6, iclass 27, count 0 2006.190.08:17:59.79#ibcon#read 6, iclass 27, count 0 2006.190.08:17:59.79#ibcon#end of sib2, iclass 27, count 0 2006.190.08:17:59.79#ibcon#*after write, iclass 27, count 0 2006.190.08:17:59.79#ibcon#*before return 0, iclass 27, count 0 2006.190.08:17:59.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:17:59.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:17:59.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:17:59.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:17:59.79$vc4f8/va=6,6 2006.190.08:17:59.79#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.08:17:59.79#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.08:17:59.79#ibcon#ireg 11 cls_cnt 2 2006.190.08:17:59.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:17:59.85#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:17:59.85#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:17:59.85#ibcon#enter wrdev, iclass 29, count 2 2006.190.08:17:59.85#ibcon#first serial, iclass 29, count 2 2006.190.08:17:59.85#ibcon#enter sib2, iclass 29, count 2 2006.190.08:17:59.85#ibcon#flushed, iclass 29, count 2 2006.190.08:17:59.85#ibcon#about to write, iclass 29, count 2 2006.190.08:17:59.85#ibcon#wrote, iclass 29, count 2 2006.190.08:17:59.85#ibcon#about to read 3, iclass 29, count 2 2006.190.08:17:59.87#ibcon#read 3, iclass 29, count 2 2006.190.08:17:59.87#ibcon#about to read 4, iclass 29, count 2 2006.190.08:17:59.87#ibcon#read 4, iclass 29, count 2 2006.190.08:17:59.87#ibcon#about to read 5, iclass 29, count 2 2006.190.08:17:59.87#ibcon#read 5, iclass 29, count 2 2006.190.08:17:59.87#ibcon#about to read 6, iclass 29, count 2 2006.190.08:17:59.87#ibcon#read 6, iclass 29, count 2 2006.190.08:17:59.87#ibcon#end of sib2, iclass 29, count 2 2006.190.08:17:59.87#ibcon#*mode == 0, iclass 29, count 2 2006.190.08:17:59.87#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.08:17:59.87#ibcon#[25=AT06-06\r\n] 2006.190.08:17:59.87#ibcon#*before write, iclass 29, count 2 2006.190.08:17:59.87#ibcon#enter sib2, iclass 29, count 2 2006.190.08:17:59.87#ibcon#flushed, iclass 29, count 2 2006.190.08:17:59.87#ibcon#about to write, iclass 29, count 2 2006.190.08:17:59.87#ibcon#wrote, iclass 29, count 2 2006.190.08:17:59.87#ibcon#about to read 3, iclass 29, count 2 2006.190.08:17:59.90#ibcon#read 3, iclass 29, count 2 2006.190.08:17:59.90#ibcon#about to read 4, iclass 29, count 2 2006.190.08:17:59.90#ibcon#read 4, iclass 29, count 2 2006.190.08:17:59.90#ibcon#about to read 5, iclass 29, count 2 2006.190.08:17:59.90#ibcon#read 5, iclass 29, count 2 2006.190.08:17:59.90#ibcon#about to read 6, iclass 29, count 2 2006.190.08:17:59.90#ibcon#read 6, iclass 29, count 2 2006.190.08:17:59.90#ibcon#end of sib2, iclass 29, count 2 2006.190.08:17:59.90#ibcon#*after write, iclass 29, count 2 2006.190.08:17:59.90#ibcon#*before return 0, iclass 29, count 2 2006.190.08:17:59.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:17:59.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:17:59.90#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.08:17:59.90#ibcon#ireg 7 cls_cnt 0 2006.190.08:17:59.90#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:18:00.02#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:18:00.02#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:18:00.02#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:18:00.02#ibcon#first serial, iclass 29, count 0 2006.190.08:18:00.02#ibcon#enter sib2, iclass 29, count 0 2006.190.08:18:00.02#ibcon#flushed, iclass 29, count 0 2006.190.08:18:00.02#ibcon#about to write, iclass 29, count 0 2006.190.08:18:00.02#ibcon#wrote, iclass 29, count 0 2006.190.08:18:00.02#ibcon#about to read 3, iclass 29, count 0 2006.190.08:18:00.04#ibcon#read 3, iclass 29, count 0 2006.190.08:18:00.04#ibcon#about to read 4, iclass 29, count 0 2006.190.08:18:00.04#ibcon#read 4, iclass 29, count 0 2006.190.08:18:00.04#ibcon#about to read 5, iclass 29, count 0 2006.190.08:18:00.04#ibcon#read 5, iclass 29, count 0 2006.190.08:18:00.04#ibcon#about to read 6, iclass 29, count 0 2006.190.08:18:00.04#ibcon#read 6, iclass 29, count 0 2006.190.08:18:00.04#ibcon#end of sib2, iclass 29, count 0 2006.190.08:18:00.04#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:18:00.04#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:18:00.04#ibcon#[25=USB\r\n] 2006.190.08:18:00.04#ibcon#*before write, iclass 29, count 0 2006.190.08:18:00.04#ibcon#enter sib2, iclass 29, count 0 2006.190.08:18:00.04#ibcon#flushed, iclass 29, count 0 2006.190.08:18:00.04#ibcon#about to write, iclass 29, count 0 2006.190.08:18:00.04#ibcon#wrote, iclass 29, count 0 2006.190.08:18:00.04#ibcon#about to read 3, iclass 29, count 0 2006.190.08:18:00.07#ibcon#read 3, iclass 29, count 0 2006.190.08:18:00.07#ibcon#about to read 4, iclass 29, count 0 2006.190.08:18:00.07#ibcon#read 4, iclass 29, count 0 2006.190.08:18:00.07#ibcon#about to read 5, iclass 29, count 0 2006.190.08:18:00.07#ibcon#read 5, iclass 29, count 0 2006.190.08:18:00.07#ibcon#about to read 6, iclass 29, count 0 2006.190.08:18:00.07#ibcon#read 6, iclass 29, count 0 2006.190.08:18:00.07#ibcon#end of sib2, iclass 29, count 0 2006.190.08:18:00.07#ibcon#*after write, iclass 29, count 0 2006.190.08:18:00.07#ibcon#*before return 0, iclass 29, count 0 2006.190.08:18:00.07#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:18:00.07#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:18:00.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:18:00.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:18:00.07$vc4f8/valo=7,832.99 2006.190.08:18:00.07#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.190.08:18:00.07#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.190.08:18:00.07#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:00.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:18:00.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:18:00.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:18:00.07#ibcon#enter wrdev, iclass 31, count 0 2006.190.08:18:00.07#ibcon#first serial, iclass 31, count 0 2006.190.08:18:00.07#ibcon#enter sib2, iclass 31, count 0 2006.190.08:18:00.07#ibcon#flushed, iclass 31, count 0 2006.190.08:18:00.07#ibcon#about to write, iclass 31, count 0 2006.190.08:18:00.07#ibcon#wrote, iclass 31, count 0 2006.190.08:18:00.07#ibcon#about to read 3, iclass 31, count 0 2006.190.08:18:00.09#ibcon#read 3, iclass 31, count 0 2006.190.08:18:00.09#ibcon#about to read 4, iclass 31, count 0 2006.190.08:18:00.09#ibcon#read 4, iclass 31, count 0 2006.190.08:18:00.09#ibcon#about to read 5, iclass 31, count 0 2006.190.08:18:00.09#ibcon#read 5, iclass 31, count 0 2006.190.08:18:00.09#ibcon#about to read 6, iclass 31, count 0 2006.190.08:18:00.09#ibcon#read 6, iclass 31, count 0 2006.190.08:18:00.09#ibcon#end of sib2, iclass 31, count 0 2006.190.08:18:00.09#ibcon#*mode == 0, iclass 31, count 0 2006.190.08:18:00.09#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.08:18:00.09#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:18:00.09#ibcon#*before write, iclass 31, count 0 2006.190.08:18:00.09#ibcon#enter sib2, iclass 31, count 0 2006.190.08:18:00.09#ibcon#flushed, iclass 31, count 0 2006.190.08:18:00.09#ibcon#about to write, iclass 31, count 0 2006.190.08:18:00.09#ibcon#wrote, iclass 31, count 0 2006.190.08:18:00.09#ibcon#about to read 3, iclass 31, count 0 2006.190.08:18:00.13#ibcon#read 3, iclass 31, count 0 2006.190.08:18:00.13#ibcon#about to read 4, iclass 31, count 0 2006.190.08:18:00.13#ibcon#read 4, iclass 31, count 0 2006.190.08:18:00.13#ibcon#about to read 5, iclass 31, count 0 2006.190.08:18:00.13#ibcon#read 5, iclass 31, count 0 2006.190.08:18:00.13#ibcon#about to read 6, iclass 31, count 0 2006.190.08:18:00.13#ibcon#read 6, iclass 31, count 0 2006.190.08:18:00.13#ibcon#end of sib2, iclass 31, count 0 2006.190.08:18:00.13#ibcon#*after write, iclass 31, count 0 2006.190.08:18:00.13#ibcon#*before return 0, iclass 31, count 0 2006.190.08:18:00.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:18:00.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.190.08:18:00.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.08:18:00.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.08:18:00.13$vc4f8/va=7,6 2006.190.08:18:00.13#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.190.08:18:00.13#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.190.08:18:00.13#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:00.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:18:00.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:18:00.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:18:00.19#ibcon#enter wrdev, iclass 33, count 2 2006.190.08:18:00.19#ibcon#first serial, iclass 33, count 2 2006.190.08:18:00.19#ibcon#enter sib2, iclass 33, count 2 2006.190.08:18:00.19#ibcon#flushed, iclass 33, count 2 2006.190.08:18:00.19#ibcon#about to write, iclass 33, count 2 2006.190.08:18:00.19#ibcon#wrote, iclass 33, count 2 2006.190.08:18:00.19#ibcon#about to read 3, iclass 33, count 2 2006.190.08:18:00.21#ibcon#read 3, iclass 33, count 2 2006.190.08:18:00.21#ibcon#about to read 4, iclass 33, count 2 2006.190.08:18:00.21#ibcon#read 4, iclass 33, count 2 2006.190.08:18:00.21#ibcon#about to read 5, iclass 33, count 2 2006.190.08:18:00.21#ibcon#read 5, iclass 33, count 2 2006.190.08:18:00.21#ibcon#about to read 6, iclass 33, count 2 2006.190.08:18:00.21#ibcon#read 6, iclass 33, count 2 2006.190.08:18:00.21#ibcon#end of sib2, iclass 33, count 2 2006.190.08:18:00.21#ibcon#*mode == 0, iclass 33, count 2 2006.190.08:18:00.21#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.190.08:18:00.21#ibcon#[25=AT07-06\r\n] 2006.190.08:18:00.21#ibcon#*before write, iclass 33, count 2 2006.190.08:18:00.21#ibcon#enter sib2, iclass 33, count 2 2006.190.08:18:00.21#ibcon#flushed, iclass 33, count 2 2006.190.08:18:00.21#ibcon#about to write, iclass 33, count 2 2006.190.08:18:00.21#ibcon#wrote, iclass 33, count 2 2006.190.08:18:00.21#ibcon#about to read 3, iclass 33, count 2 2006.190.08:18:00.24#ibcon#read 3, iclass 33, count 2 2006.190.08:18:00.24#ibcon#about to read 4, iclass 33, count 2 2006.190.08:18:00.24#ibcon#read 4, iclass 33, count 2 2006.190.08:18:00.24#ibcon#about to read 5, iclass 33, count 2 2006.190.08:18:00.24#ibcon#read 5, iclass 33, count 2 2006.190.08:18:00.24#ibcon#about to read 6, iclass 33, count 2 2006.190.08:18:00.24#ibcon#read 6, iclass 33, count 2 2006.190.08:18:00.24#ibcon#end of sib2, iclass 33, count 2 2006.190.08:18:00.24#ibcon#*after write, iclass 33, count 2 2006.190.08:18:00.24#ibcon#*before return 0, iclass 33, count 2 2006.190.08:18:00.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:18:00.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.190.08:18:00.24#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.190.08:18:00.24#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:00.24#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:18:00.36#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:18:00.36#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:18:00.36#ibcon#enter wrdev, iclass 33, count 0 2006.190.08:18:00.36#ibcon#first serial, iclass 33, count 0 2006.190.08:18:00.36#ibcon#enter sib2, iclass 33, count 0 2006.190.08:18:00.36#ibcon#flushed, iclass 33, count 0 2006.190.08:18:00.36#ibcon#about to write, iclass 33, count 0 2006.190.08:18:00.36#ibcon#wrote, iclass 33, count 0 2006.190.08:18:00.36#ibcon#about to read 3, iclass 33, count 0 2006.190.08:18:00.38#ibcon#read 3, iclass 33, count 0 2006.190.08:18:00.38#ibcon#about to read 4, iclass 33, count 0 2006.190.08:18:00.38#ibcon#read 4, iclass 33, count 0 2006.190.08:18:00.38#ibcon#about to read 5, iclass 33, count 0 2006.190.08:18:00.38#ibcon#read 5, iclass 33, count 0 2006.190.08:18:00.38#ibcon#about to read 6, iclass 33, count 0 2006.190.08:18:00.38#ibcon#read 6, iclass 33, count 0 2006.190.08:18:00.38#ibcon#end of sib2, iclass 33, count 0 2006.190.08:18:00.38#ibcon#*mode == 0, iclass 33, count 0 2006.190.08:18:00.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.08:18:00.38#ibcon#[25=USB\r\n] 2006.190.08:18:00.38#ibcon#*before write, iclass 33, count 0 2006.190.08:18:00.38#ibcon#enter sib2, iclass 33, count 0 2006.190.08:18:00.38#ibcon#flushed, iclass 33, count 0 2006.190.08:18:00.38#ibcon#about to write, iclass 33, count 0 2006.190.08:18:00.38#ibcon#wrote, iclass 33, count 0 2006.190.08:18:00.38#ibcon#about to read 3, iclass 33, count 0 2006.190.08:18:00.41#ibcon#read 3, iclass 33, count 0 2006.190.08:18:00.41#ibcon#about to read 4, iclass 33, count 0 2006.190.08:18:00.41#ibcon#read 4, iclass 33, count 0 2006.190.08:18:00.41#ibcon#about to read 5, iclass 33, count 0 2006.190.08:18:00.41#ibcon#read 5, iclass 33, count 0 2006.190.08:18:00.41#ibcon#about to read 6, iclass 33, count 0 2006.190.08:18:00.41#ibcon#read 6, iclass 33, count 0 2006.190.08:18:00.41#ibcon#end of sib2, iclass 33, count 0 2006.190.08:18:00.41#ibcon#*after write, iclass 33, count 0 2006.190.08:18:00.41#ibcon#*before return 0, iclass 33, count 0 2006.190.08:18:00.41#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:18:00.41#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.190.08:18:00.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.08:18:00.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.08:18:00.41$vc4f8/valo=8,852.99 2006.190.08:18:00.41#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.190.08:18:00.41#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.190.08:18:00.41#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:00.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:18:00.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:18:00.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:18:00.41#ibcon#enter wrdev, iclass 35, count 0 2006.190.08:18:00.41#ibcon#first serial, iclass 35, count 0 2006.190.08:18:00.41#ibcon#enter sib2, iclass 35, count 0 2006.190.08:18:00.41#ibcon#flushed, iclass 35, count 0 2006.190.08:18:00.41#ibcon#about to write, iclass 35, count 0 2006.190.08:18:00.41#ibcon#wrote, iclass 35, count 0 2006.190.08:18:00.41#ibcon#about to read 3, iclass 35, count 0 2006.190.08:18:00.43#ibcon#read 3, iclass 35, count 0 2006.190.08:18:00.43#ibcon#about to read 4, iclass 35, count 0 2006.190.08:18:00.43#ibcon#read 4, iclass 35, count 0 2006.190.08:18:00.43#ibcon#about to read 5, iclass 35, count 0 2006.190.08:18:00.43#ibcon#read 5, iclass 35, count 0 2006.190.08:18:00.43#ibcon#about to read 6, iclass 35, count 0 2006.190.08:18:00.43#ibcon#read 6, iclass 35, count 0 2006.190.08:18:00.43#ibcon#end of sib2, iclass 35, count 0 2006.190.08:18:00.43#ibcon#*mode == 0, iclass 35, count 0 2006.190.08:18:00.43#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.08:18:00.43#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:18:00.43#ibcon#*before write, iclass 35, count 0 2006.190.08:18:00.43#ibcon#enter sib2, iclass 35, count 0 2006.190.08:18:00.43#ibcon#flushed, iclass 35, count 0 2006.190.08:18:00.43#ibcon#about to write, iclass 35, count 0 2006.190.08:18:00.43#ibcon#wrote, iclass 35, count 0 2006.190.08:18:00.43#ibcon#about to read 3, iclass 35, count 0 2006.190.08:18:00.47#ibcon#read 3, iclass 35, count 0 2006.190.08:18:00.47#ibcon#about to read 4, iclass 35, count 0 2006.190.08:18:00.47#ibcon#read 4, iclass 35, count 0 2006.190.08:18:00.47#ibcon#about to read 5, iclass 35, count 0 2006.190.08:18:00.47#ibcon#read 5, iclass 35, count 0 2006.190.08:18:00.47#ibcon#about to read 6, iclass 35, count 0 2006.190.08:18:00.47#ibcon#read 6, iclass 35, count 0 2006.190.08:18:00.47#ibcon#end of sib2, iclass 35, count 0 2006.190.08:18:00.47#ibcon#*after write, iclass 35, count 0 2006.190.08:18:00.47#ibcon#*before return 0, iclass 35, count 0 2006.190.08:18:00.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:18:00.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.190.08:18:00.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.08:18:00.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.08:18:00.47$vc4f8/va=8,6 2006.190.08:18:00.47#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.190.08:18:00.47#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.190.08:18:00.47#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:00.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:18:00.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:18:00.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:18:00.53#ibcon#enter wrdev, iclass 37, count 2 2006.190.08:18:00.53#ibcon#first serial, iclass 37, count 2 2006.190.08:18:00.53#ibcon#enter sib2, iclass 37, count 2 2006.190.08:18:00.53#ibcon#flushed, iclass 37, count 2 2006.190.08:18:00.53#ibcon#about to write, iclass 37, count 2 2006.190.08:18:00.53#ibcon#wrote, iclass 37, count 2 2006.190.08:18:00.53#ibcon#about to read 3, iclass 37, count 2 2006.190.08:18:00.55#ibcon#read 3, iclass 37, count 2 2006.190.08:18:00.55#ibcon#about to read 4, iclass 37, count 2 2006.190.08:18:00.55#ibcon#read 4, iclass 37, count 2 2006.190.08:18:00.55#ibcon#about to read 5, iclass 37, count 2 2006.190.08:18:00.55#ibcon#read 5, iclass 37, count 2 2006.190.08:18:00.55#ibcon#about to read 6, iclass 37, count 2 2006.190.08:18:00.55#ibcon#read 6, iclass 37, count 2 2006.190.08:18:00.55#ibcon#end of sib2, iclass 37, count 2 2006.190.08:18:00.55#ibcon#*mode == 0, iclass 37, count 2 2006.190.08:18:00.55#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.190.08:18:00.55#ibcon#[25=AT08-06\r\n] 2006.190.08:18:00.55#ibcon#*before write, iclass 37, count 2 2006.190.08:18:00.55#ibcon#enter sib2, iclass 37, count 2 2006.190.08:18:00.55#ibcon#flushed, iclass 37, count 2 2006.190.08:18:00.55#ibcon#about to write, iclass 37, count 2 2006.190.08:18:00.55#ibcon#wrote, iclass 37, count 2 2006.190.08:18:00.55#ibcon#about to read 3, iclass 37, count 2 2006.190.08:18:00.58#ibcon#read 3, iclass 37, count 2 2006.190.08:18:00.58#ibcon#about to read 4, iclass 37, count 2 2006.190.08:18:00.58#ibcon#read 4, iclass 37, count 2 2006.190.08:18:00.58#ibcon#about to read 5, iclass 37, count 2 2006.190.08:18:00.58#ibcon#read 5, iclass 37, count 2 2006.190.08:18:00.58#ibcon#about to read 6, iclass 37, count 2 2006.190.08:18:00.58#ibcon#read 6, iclass 37, count 2 2006.190.08:18:00.58#ibcon#end of sib2, iclass 37, count 2 2006.190.08:18:00.58#ibcon#*after write, iclass 37, count 2 2006.190.08:18:00.58#ibcon#*before return 0, iclass 37, count 2 2006.190.08:18:00.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:18:00.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.190.08:18:00.58#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.190.08:18:00.58#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:00.58#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:18:00.70#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:18:00.70#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:18:00.70#ibcon#enter wrdev, iclass 37, count 0 2006.190.08:18:00.70#ibcon#first serial, iclass 37, count 0 2006.190.08:18:00.70#ibcon#enter sib2, iclass 37, count 0 2006.190.08:18:00.70#ibcon#flushed, iclass 37, count 0 2006.190.08:18:00.70#ibcon#about to write, iclass 37, count 0 2006.190.08:18:00.70#ibcon#wrote, iclass 37, count 0 2006.190.08:18:00.70#ibcon#about to read 3, iclass 37, count 0 2006.190.08:18:00.72#ibcon#read 3, iclass 37, count 0 2006.190.08:18:00.72#ibcon#about to read 4, iclass 37, count 0 2006.190.08:18:00.72#ibcon#read 4, iclass 37, count 0 2006.190.08:18:00.72#ibcon#about to read 5, iclass 37, count 0 2006.190.08:18:00.72#ibcon#read 5, iclass 37, count 0 2006.190.08:18:00.72#ibcon#about to read 6, iclass 37, count 0 2006.190.08:18:00.72#ibcon#read 6, iclass 37, count 0 2006.190.08:18:00.72#ibcon#end of sib2, iclass 37, count 0 2006.190.08:18:00.72#ibcon#*mode == 0, iclass 37, count 0 2006.190.08:18:00.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.08:18:00.72#ibcon#[25=USB\r\n] 2006.190.08:18:00.72#ibcon#*before write, iclass 37, count 0 2006.190.08:18:00.72#ibcon#enter sib2, iclass 37, count 0 2006.190.08:18:00.72#ibcon#flushed, iclass 37, count 0 2006.190.08:18:00.72#ibcon#about to write, iclass 37, count 0 2006.190.08:18:00.72#ibcon#wrote, iclass 37, count 0 2006.190.08:18:00.72#ibcon#about to read 3, iclass 37, count 0 2006.190.08:18:00.75#ibcon#read 3, iclass 37, count 0 2006.190.08:18:00.75#ibcon#about to read 4, iclass 37, count 0 2006.190.08:18:00.75#ibcon#read 4, iclass 37, count 0 2006.190.08:18:00.75#ibcon#about to read 5, iclass 37, count 0 2006.190.08:18:00.75#ibcon#read 5, iclass 37, count 0 2006.190.08:18:00.75#ibcon#about to read 6, iclass 37, count 0 2006.190.08:18:00.75#ibcon#read 6, iclass 37, count 0 2006.190.08:18:00.75#ibcon#end of sib2, iclass 37, count 0 2006.190.08:18:00.75#ibcon#*after write, iclass 37, count 0 2006.190.08:18:00.75#ibcon#*before return 0, iclass 37, count 0 2006.190.08:18:00.75#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:18:00.75#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.190.08:18:00.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.08:18:00.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.08:18:00.75$vc4f8/vblo=1,632.99 2006.190.08:18:00.75#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.190.08:18:00.75#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.190.08:18:00.75#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:00.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:18:00.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:18:00.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:18:00.75#ibcon#enter wrdev, iclass 39, count 0 2006.190.08:18:00.75#ibcon#first serial, iclass 39, count 0 2006.190.08:18:00.75#ibcon#enter sib2, iclass 39, count 0 2006.190.08:18:00.75#ibcon#flushed, iclass 39, count 0 2006.190.08:18:00.75#ibcon#about to write, iclass 39, count 0 2006.190.08:18:00.75#ibcon#wrote, iclass 39, count 0 2006.190.08:18:00.75#ibcon#about to read 3, iclass 39, count 0 2006.190.08:18:00.77#ibcon#read 3, iclass 39, count 0 2006.190.08:18:00.77#ibcon#about to read 4, iclass 39, count 0 2006.190.08:18:00.77#ibcon#read 4, iclass 39, count 0 2006.190.08:18:00.77#ibcon#about to read 5, iclass 39, count 0 2006.190.08:18:00.77#ibcon#read 5, iclass 39, count 0 2006.190.08:18:00.77#ibcon#about to read 6, iclass 39, count 0 2006.190.08:18:00.77#ibcon#read 6, iclass 39, count 0 2006.190.08:18:00.77#ibcon#end of sib2, iclass 39, count 0 2006.190.08:18:00.77#ibcon#*mode == 0, iclass 39, count 0 2006.190.08:18:00.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.08:18:00.77#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:18:00.77#ibcon#*before write, iclass 39, count 0 2006.190.08:18:00.77#ibcon#enter sib2, iclass 39, count 0 2006.190.08:18:00.77#ibcon#flushed, iclass 39, count 0 2006.190.08:18:00.77#ibcon#about to write, iclass 39, count 0 2006.190.08:18:00.77#ibcon#wrote, iclass 39, count 0 2006.190.08:18:00.77#ibcon#about to read 3, iclass 39, count 0 2006.190.08:18:00.81#ibcon#read 3, iclass 39, count 0 2006.190.08:18:00.81#ibcon#about to read 4, iclass 39, count 0 2006.190.08:18:00.81#ibcon#read 4, iclass 39, count 0 2006.190.08:18:00.81#ibcon#about to read 5, iclass 39, count 0 2006.190.08:18:00.81#ibcon#read 5, iclass 39, count 0 2006.190.08:18:00.81#ibcon#about to read 6, iclass 39, count 0 2006.190.08:18:00.81#ibcon#read 6, iclass 39, count 0 2006.190.08:18:00.81#ibcon#end of sib2, iclass 39, count 0 2006.190.08:18:00.81#ibcon#*after write, iclass 39, count 0 2006.190.08:18:00.81#ibcon#*before return 0, iclass 39, count 0 2006.190.08:18:00.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:18:00.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.190.08:18:00.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.08:18:00.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.08:18:00.81$vc4f8/vb=1,4 2006.190.08:18:00.81#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.190.08:18:00.81#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.190.08:18:00.81#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:00.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:18:00.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:18:00.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:18:00.81#ibcon#enter wrdev, iclass 3, count 2 2006.190.08:18:00.81#ibcon#first serial, iclass 3, count 2 2006.190.08:18:00.81#ibcon#enter sib2, iclass 3, count 2 2006.190.08:18:00.81#ibcon#flushed, iclass 3, count 2 2006.190.08:18:00.81#ibcon#about to write, iclass 3, count 2 2006.190.08:18:00.81#ibcon#wrote, iclass 3, count 2 2006.190.08:18:00.81#ibcon#about to read 3, iclass 3, count 2 2006.190.08:18:00.83#ibcon#read 3, iclass 3, count 2 2006.190.08:18:00.83#ibcon#about to read 4, iclass 3, count 2 2006.190.08:18:00.83#ibcon#read 4, iclass 3, count 2 2006.190.08:18:00.83#ibcon#about to read 5, iclass 3, count 2 2006.190.08:18:00.83#ibcon#read 5, iclass 3, count 2 2006.190.08:18:00.83#ibcon#about to read 6, iclass 3, count 2 2006.190.08:18:00.83#ibcon#read 6, iclass 3, count 2 2006.190.08:18:00.83#ibcon#end of sib2, iclass 3, count 2 2006.190.08:18:00.83#ibcon#*mode == 0, iclass 3, count 2 2006.190.08:18:00.83#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.190.08:18:00.83#ibcon#[27=AT01-04\r\n] 2006.190.08:18:00.83#ibcon#*before write, iclass 3, count 2 2006.190.08:18:00.83#ibcon#enter sib2, iclass 3, count 2 2006.190.08:18:00.83#ibcon#flushed, iclass 3, count 2 2006.190.08:18:00.83#ibcon#about to write, iclass 3, count 2 2006.190.08:18:00.83#ibcon#wrote, iclass 3, count 2 2006.190.08:18:00.83#ibcon#about to read 3, iclass 3, count 2 2006.190.08:18:00.86#ibcon#read 3, iclass 3, count 2 2006.190.08:18:00.86#ibcon#about to read 4, iclass 3, count 2 2006.190.08:18:00.86#ibcon#read 4, iclass 3, count 2 2006.190.08:18:00.86#ibcon#about to read 5, iclass 3, count 2 2006.190.08:18:00.86#ibcon#read 5, iclass 3, count 2 2006.190.08:18:00.86#ibcon#about to read 6, iclass 3, count 2 2006.190.08:18:00.86#ibcon#read 6, iclass 3, count 2 2006.190.08:18:00.86#ibcon#end of sib2, iclass 3, count 2 2006.190.08:18:00.86#ibcon#*after write, iclass 3, count 2 2006.190.08:18:00.86#ibcon#*before return 0, iclass 3, count 2 2006.190.08:18:00.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:18:00.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.190.08:18:00.86#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.190.08:18:00.86#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:00.86#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:18:00.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:18:00.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:18:00.98#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:18:00.98#ibcon#first serial, iclass 3, count 0 2006.190.08:18:00.98#ibcon#enter sib2, iclass 3, count 0 2006.190.08:18:00.98#ibcon#flushed, iclass 3, count 0 2006.190.08:18:00.98#ibcon#about to write, iclass 3, count 0 2006.190.08:18:00.98#ibcon#wrote, iclass 3, count 0 2006.190.08:18:00.98#ibcon#about to read 3, iclass 3, count 0 2006.190.08:18:01.00#ibcon#read 3, iclass 3, count 0 2006.190.08:18:01.00#ibcon#about to read 4, iclass 3, count 0 2006.190.08:18:01.00#ibcon#read 4, iclass 3, count 0 2006.190.08:18:01.00#ibcon#about to read 5, iclass 3, count 0 2006.190.08:18:01.00#ibcon#read 5, iclass 3, count 0 2006.190.08:18:01.00#ibcon#about to read 6, iclass 3, count 0 2006.190.08:18:01.00#ibcon#read 6, iclass 3, count 0 2006.190.08:18:01.00#ibcon#end of sib2, iclass 3, count 0 2006.190.08:18:01.00#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:18:01.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:18:01.00#ibcon#[27=USB\r\n] 2006.190.08:18:01.00#ibcon#*before write, iclass 3, count 0 2006.190.08:18:01.00#ibcon#enter sib2, iclass 3, count 0 2006.190.08:18:01.00#ibcon#flushed, iclass 3, count 0 2006.190.08:18:01.00#ibcon#about to write, iclass 3, count 0 2006.190.08:18:01.00#ibcon#wrote, iclass 3, count 0 2006.190.08:18:01.00#ibcon#about to read 3, iclass 3, count 0 2006.190.08:18:01.03#ibcon#read 3, iclass 3, count 0 2006.190.08:18:01.03#ibcon#about to read 4, iclass 3, count 0 2006.190.08:18:01.03#ibcon#read 4, iclass 3, count 0 2006.190.08:18:01.03#ibcon#about to read 5, iclass 3, count 0 2006.190.08:18:01.03#ibcon#read 5, iclass 3, count 0 2006.190.08:18:01.03#ibcon#about to read 6, iclass 3, count 0 2006.190.08:18:01.03#ibcon#read 6, iclass 3, count 0 2006.190.08:18:01.03#ibcon#end of sib2, iclass 3, count 0 2006.190.08:18:01.03#ibcon#*after write, iclass 3, count 0 2006.190.08:18:01.03#ibcon#*before return 0, iclass 3, count 0 2006.190.08:18:01.03#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:18:01.03#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.190.08:18:01.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:18:01.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:18:01.03$vc4f8/vblo=2,640.99 2006.190.08:18:01.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.190.08:18:01.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.190.08:18:01.03#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:01.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:18:01.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:18:01.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:18:01.03#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:18:01.03#ibcon#first serial, iclass 5, count 0 2006.190.08:18:01.03#ibcon#enter sib2, iclass 5, count 0 2006.190.08:18:01.03#ibcon#flushed, iclass 5, count 0 2006.190.08:18:01.03#ibcon#about to write, iclass 5, count 0 2006.190.08:18:01.03#ibcon#wrote, iclass 5, count 0 2006.190.08:18:01.03#ibcon#about to read 3, iclass 5, count 0 2006.190.08:18:01.05#ibcon#read 3, iclass 5, count 0 2006.190.08:18:01.05#ibcon#about to read 4, iclass 5, count 0 2006.190.08:18:01.05#ibcon#read 4, iclass 5, count 0 2006.190.08:18:01.05#ibcon#about to read 5, iclass 5, count 0 2006.190.08:18:01.05#ibcon#read 5, iclass 5, count 0 2006.190.08:18:01.05#ibcon#about to read 6, iclass 5, count 0 2006.190.08:18:01.05#ibcon#read 6, iclass 5, count 0 2006.190.08:18:01.05#ibcon#end of sib2, iclass 5, count 0 2006.190.08:18:01.05#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:18:01.05#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:18:01.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:18:01.05#ibcon#*before write, iclass 5, count 0 2006.190.08:18:01.05#ibcon#enter sib2, iclass 5, count 0 2006.190.08:18:01.05#ibcon#flushed, iclass 5, count 0 2006.190.08:18:01.05#ibcon#about to write, iclass 5, count 0 2006.190.08:18:01.05#ibcon#wrote, iclass 5, count 0 2006.190.08:18:01.05#ibcon#about to read 3, iclass 5, count 0 2006.190.08:18:01.09#ibcon#read 3, iclass 5, count 0 2006.190.08:18:01.09#ibcon#about to read 4, iclass 5, count 0 2006.190.08:18:01.09#ibcon#read 4, iclass 5, count 0 2006.190.08:18:01.09#ibcon#about to read 5, iclass 5, count 0 2006.190.08:18:01.09#ibcon#read 5, iclass 5, count 0 2006.190.08:18:01.09#ibcon#about to read 6, iclass 5, count 0 2006.190.08:18:01.09#ibcon#read 6, iclass 5, count 0 2006.190.08:18:01.09#ibcon#end of sib2, iclass 5, count 0 2006.190.08:18:01.09#ibcon#*after write, iclass 5, count 0 2006.190.08:18:01.09#ibcon#*before return 0, iclass 5, count 0 2006.190.08:18:01.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:18:01.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.190.08:18:01.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:18:01.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:18:01.09$vc4f8/vb=2,4 2006.190.08:18:01.09#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.190.08:18:01.09#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.190.08:18:01.09#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:01.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:18:01.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:18:01.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:18:01.15#ibcon#enter wrdev, iclass 7, count 2 2006.190.08:18:01.15#ibcon#first serial, iclass 7, count 2 2006.190.08:18:01.15#ibcon#enter sib2, iclass 7, count 2 2006.190.08:18:01.15#ibcon#flushed, iclass 7, count 2 2006.190.08:18:01.15#ibcon#about to write, iclass 7, count 2 2006.190.08:18:01.15#ibcon#wrote, iclass 7, count 2 2006.190.08:18:01.15#ibcon#about to read 3, iclass 7, count 2 2006.190.08:18:01.17#ibcon#read 3, iclass 7, count 2 2006.190.08:18:01.17#ibcon#about to read 4, iclass 7, count 2 2006.190.08:18:01.17#ibcon#read 4, iclass 7, count 2 2006.190.08:18:01.17#ibcon#about to read 5, iclass 7, count 2 2006.190.08:18:01.17#ibcon#read 5, iclass 7, count 2 2006.190.08:18:01.17#ibcon#about to read 6, iclass 7, count 2 2006.190.08:18:01.17#ibcon#read 6, iclass 7, count 2 2006.190.08:18:01.17#ibcon#end of sib2, iclass 7, count 2 2006.190.08:18:01.17#ibcon#*mode == 0, iclass 7, count 2 2006.190.08:18:01.17#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.190.08:18:01.17#ibcon#[27=AT02-04\r\n] 2006.190.08:18:01.17#ibcon#*before write, iclass 7, count 2 2006.190.08:18:01.17#ibcon#enter sib2, iclass 7, count 2 2006.190.08:18:01.17#ibcon#flushed, iclass 7, count 2 2006.190.08:18:01.17#ibcon#about to write, iclass 7, count 2 2006.190.08:18:01.17#ibcon#wrote, iclass 7, count 2 2006.190.08:18:01.17#ibcon#about to read 3, iclass 7, count 2 2006.190.08:18:01.20#ibcon#read 3, iclass 7, count 2 2006.190.08:18:01.20#ibcon#about to read 4, iclass 7, count 2 2006.190.08:18:01.20#ibcon#read 4, iclass 7, count 2 2006.190.08:18:01.20#ibcon#about to read 5, iclass 7, count 2 2006.190.08:18:01.20#ibcon#read 5, iclass 7, count 2 2006.190.08:18:01.20#ibcon#about to read 6, iclass 7, count 2 2006.190.08:18:01.20#ibcon#read 6, iclass 7, count 2 2006.190.08:18:01.20#ibcon#end of sib2, iclass 7, count 2 2006.190.08:18:01.20#ibcon#*after write, iclass 7, count 2 2006.190.08:18:01.20#ibcon#*before return 0, iclass 7, count 2 2006.190.08:18:01.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:18:01.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.190.08:18:01.20#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.190.08:18:01.20#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:01.20#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:18:01.32#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:18:01.32#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:18:01.32#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:18:01.32#ibcon#first serial, iclass 7, count 0 2006.190.08:18:01.32#ibcon#enter sib2, iclass 7, count 0 2006.190.08:18:01.32#ibcon#flushed, iclass 7, count 0 2006.190.08:18:01.32#ibcon#about to write, iclass 7, count 0 2006.190.08:18:01.32#ibcon#wrote, iclass 7, count 0 2006.190.08:18:01.32#ibcon#about to read 3, iclass 7, count 0 2006.190.08:18:01.34#ibcon#read 3, iclass 7, count 0 2006.190.08:18:01.34#ibcon#about to read 4, iclass 7, count 0 2006.190.08:18:01.34#ibcon#read 4, iclass 7, count 0 2006.190.08:18:01.34#ibcon#about to read 5, iclass 7, count 0 2006.190.08:18:01.34#ibcon#read 5, iclass 7, count 0 2006.190.08:18:01.34#ibcon#about to read 6, iclass 7, count 0 2006.190.08:18:01.34#ibcon#read 6, iclass 7, count 0 2006.190.08:18:01.34#ibcon#end of sib2, iclass 7, count 0 2006.190.08:18:01.34#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:18:01.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:18:01.34#ibcon#[27=USB\r\n] 2006.190.08:18:01.34#ibcon#*before write, iclass 7, count 0 2006.190.08:18:01.34#ibcon#enter sib2, iclass 7, count 0 2006.190.08:18:01.34#ibcon#flushed, iclass 7, count 0 2006.190.08:18:01.34#ibcon#about to write, iclass 7, count 0 2006.190.08:18:01.34#ibcon#wrote, iclass 7, count 0 2006.190.08:18:01.34#ibcon#about to read 3, iclass 7, count 0 2006.190.08:18:01.37#ibcon#read 3, iclass 7, count 0 2006.190.08:18:01.37#ibcon#about to read 4, iclass 7, count 0 2006.190.08:18:01.37#ibcon#read 4, iclass 7, count 0 2006.190.08:18:01.37#ibcon#about to read 5, iclass 7, count 0 2006.190.08:18:01.37#ibcon#read 5, iclass 7, count 0 2006.190.08:18:01.37#ibcon#about to read 6, iclass 7, count 0 2006.190.08:18:01.37#ibcon#read 6, iclass 7, count 0 2006.190.08:18:01.37#ibcon#end of sib2, iclass 7, count 0 2006.190.08:18:01.37#ibcon#*after write, iclass 7, count 0 2006.190.08:18:01.37#ibcon#*before return 0, iclass 7, count 0 2006.190.08:18:01.37#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:18:01.37#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.190.08:18:01.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:18:01.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:18:01.37$vc4f8/vblo=3,656.99 2006.190.08:18:01.37#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.190.08:18:01.37#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.190.08:18:01.37#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:01.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:18:01.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:18:01.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:18:01.37#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:18:01.37#ibcon#first serial, iclass 11, count 0 2006.190.08:18:01.37#ibcon#enter sib2, iclass 11, count 0 2006.190.08:18:01.37#ibcon#flushed, iclass 11, count 0 2006.190.08:18:01.37#ibcon#about to write, iclass 11, count 0 2006.190.08:18:01.37#ibcon#wrote, iclass 11, count 0 2006.190.08:18:01.37#ibcon#about to read 3, iclass 11, count 0 2006.190.08:18:01.39#ibcon#read 3, iclass 11, count 0 2006.190.08:18:01.39#ibcon#about to read 4, iclass 11, count 0 2006.190.08:18:01.39#ibcon#read 4, iclass 11, count 0 2006.190.08:18:01.39#ibcon#about to read 5, iclass 11, count 0 2006.190.08:18:01.39#ibcon#read 5, iclass 11, count 0 2006.190.08:18:01.39#ibcon#about to read 6, iclass 11, count 0 2006.190.08:18:01.39#ibcon#read 6, iclass 11, count 0 2006.190.08:18:01.39#ibcon#end of sib2, iclass 11, count 0 2006.190.08:18:01.39#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:18:01.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:18:01.39#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:18:01.39#ibcon#*before write, iclass 11, count 0 2006.190.08:18:01.39#ibcon#enter sib2, iclass 11, count 0 2006.190.08:18:01.39#ibcon#flushed, iclass 11, count 0 2006.190.08:18:01.39#ibcon#about to write, iclass 11, count 0 2006.190.08:18:01.39#ibcon#wrote, iclass 11, count 0 2006.190.08:18:01.39#ibcon#about to read 3, iclass 11, count 0 2006.190.08:18:01.43#ibcon#read 3, iclass 11, count 0 2006.190.08:18:01.43#ibcon#about to read 4, iclass 11, count 0 2006.190.08:18:01.43#ibcon#read 4, iclass 11, count 0 2006.190.08:18:01.43#ibcon#about to read 5, iclass 11, count 0 2006.190.08:18:01.43#ibcon#read 5, iclass 11, count 0 2006.190.08:18:01.43#ibcon#about to read 6, iclass 11, count 0 2006.190.08:18:01.43#ibcon#read 6, iclass 11, count 0 2006.190.08:18:01.43#ibcon#end of sib2, iclass 11, count 0 2006.190.08:18:01.43#ibcon#*after write, iclass 11, count 0 2006.190.08:18:01.43#ibcon#*before return 0, iclass 11, count 0 2006.190.08:18:01.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:18:01.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.190.08:18:01.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:18:01.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:18:01.43$vc4f8/vb=3,4 2006.190.08:18:01.43#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.190.08:18:01.43#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.190.08:18:01.43#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:01.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:18:01.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:18:01.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:18:01.49#ibcon#enter wrdev, iclass 13, count 2 2006.190.08:18:01.49#ibcon#first serial, iclass 13, count 2 2006.190.08:18:01.49#ibcon#enter sib2, iclass 13, count 2 2006.190.08:18:01.49#ibcon#flushed, iclass 13, count 2 2006.190.08:18:01.49#ibcon#about to write, iclass 13, count 2 2006.190.08:18:01.49#ibcon#wrote, iclass 13, count 2 2006.190.08:18:01.49#ibcon#about to read 3, iclass 13, count 2 2006.190.08:18:01.51#ibcon#read 3, iclass 13, count 2 2006.190.08:18:01.51#ibcon#about to read 4, iclass 13, count 2 2006.190.08:18:01.51#ibcon#read 4, iclass 13, count 2 2006.190.08:18:01.51#ibcon#about to read 5, iclass 13, count 2 2006.190.08:18:01.51#ibcon#read 5, iclass 13, count 2 2006.190.08:18:01.51#ibcon#about to read 6, iclass 13, count 2 2006.190.08:18:01.51#ibcon#read 6, iclass 13, count 2 2006.190.08:18:01.51#ibcon#end of sib2, iclass 13, count 2 2006.190.08:18:01.51#ibcon#*mode == 0, iclass 13, count 2 2006.190.08:18:01.51#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.190.08:18:01.51#ibcon#[27=AT03-04\r\n] 2006.190.08:18:01.51#ibcon#*before write, iclass 13, count 2 2006.190.08:18:01.51#ibcon#enter sib2, iclass 13, count 2 2006.190.08:18:01.51#ibcon#flushed, iclass 13, count 2 2006.190.08:18:01.51#ibcon#about to write, iclass 13, count 2 2006.190.08:18:01.51#ibcon#wrote, iclass 13, count 2 2006.190.08:18:01.51#ibcon#about to read 3, iclass 13, count 2 2006.190.08:18:01.54#ibcon#read 3, iclass 13, count 2 2006.190.08:18:01.54#ibcon#about to read 4, iclass 13, count 2 2006.190.08:18:01.54#ibcon#read 4, iclass 13, count 2 2006.190.08:18:01.54#ibcon#about to read 5, iclass 13, count 2 2006.190.08:18:01.54#ibcon#read 5, iclass 13, count 2 2006.190.08:18:01.54#ibcon#about to read 6, iclass 13, count 2 2006.190.08:18:01.54#ibcon#read 6, iclass 13, count 2 2006.190.08:18:01.54#ibcon#end of sib2, iclass 13, count 2 2006.190.08:18:01.54#ibcon#*after write, iclass 13, count 2 2006.190.08:18:01.54#ibcon#*before return 0, iclass 13, count 2 2006.190.08:18:01.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:18:01.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.190.08:18:01.54#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.190.08:18:01.54#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:01.54#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:18:01.66#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:18:01.66#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:18:01.66#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:18:01.66#ibcon#first serial, iclass 13, count 0 2006.190.08:18:01.66#ibcon#enter sib2, iclass 13, count 0 2006.190.08:18:01.66#ibcon#flushed, iclass 13, count 0 2006.190.08:18:01.66#ibcon#about to write, iclass 13, count 0 2006.190.08:18:01.66#ibcon#wrote, iclass 13, count 0 2006.190.08:18:01.66#ibcon#about to read 3, iclass 13, count 0 2006.190.08:18:01.68#ibcon#read 3, iclass 13, count 0 2006.190.08:18:01.68#ibcon#about to read 4, iclass 13, count 0 2006.190.08:18:01.68#ibcon#read 4, iclass 13, count 0 2006.190.08:18:01.68#ibcon#about to read 5, iclass 13, count 0 2006.190.08:18:01.68#ibcon#read 5, iclass 13, count 0 2006.190.08:18:01.68#ibcon#about to read 6, iclass 13, count 0 2006.190.08:18:01.68#ibcon#read 6, iclass 13, count 0 2006.190.08:18:01.68#ibcon#end of sib2, iclass 13, count 0 2006.190.08:18:01.68#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:18:01.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:18:01.68#ibcon#[27=USB\r\n] 2006.190.08:18:01.68#ibcon#*before write, iclass 13, count 0 2006.190.08:18:01.68#ibcon#enter sib2, iclass 13, count 0 2006.190.08:18:01.68#ibcon#flushed, iclass 13, count 0 2006.190.08:18:01.68#ibcon#about to write, iclass 13, count 0 2006.190.08:18:01.68#ibcon#wrote, iclass 13, count 0 2006.190.08:18:01.68#ibcon#about to read 3, iclass 13, count 0 2006.190.08:18:01.71#ibcon#read 3, iclass 13, count 0 2006.190.08:18:01.71#ibcon#about to read 4, iclass 13, count 0 2006.190.08:18:01.71#ibcon#read 4, iclass 13, count 0 2006.190.08:18:01.71#ibcon#about to read 5, iclass 13, count 0 2006.190.08:18:01.71#ibcon#read 5, iclass 13, count 0 2006.190.08:18:01.71#ibcon#about to read 6, iclass 13, count 0 2006.190.08:18:01.71#ibcon#read 6, iclass 13, count 0 2006.190.08:18:01.71#ibcon#end of sib2, iclass 13, count 0 2006.190.08:18:01.71#ibcon#*after write, iclass 13, count 0 2006.190.08:18:01.71#ibcon#*before return 0, iclass 13, count 0 2006.190.08:18:01.71#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:18:01.71#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.190.08:18:01.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:18:01.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:18:01.71$vc4f8/vblo=4,712.99 2006.190.08:18:01.71#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.190.08:18:01.71#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.190.08:18:01.71#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:01.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:18:01.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:18:01.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:18:01.71#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:18:01.71#ibcon#first serial, iclass 15, count 0 2006.190.08:18:01.71#ibcon#enter sib2, iclass 15, count 0 2006.190.08:18:01.71#ibcon#flushed, iclass 15, count 0 2006.190.08:18:01.71#ibcon#about to write, iclass 15, count 0 2006.190.08:18:01.71#ibcon#wrote, iclass 15, count 0 2006.190.08:18:01.71#ibcon#about to read 3, iclass 15, count 0 2006.190.08:18:01.73#ibcon#read 3, iclass 15, count 0 2006.190.08:18:01.73#ibcon#about to read 4, iclass 15, count 0 2006.190.08:18:01.73#ibcon#read 4, iclass 15, count 0 2006.190.08:18:01.73#ibcon#about to read 5, iclass 15, count 0 2006.190.08:18:01.73#ibcon#read 5, iclass 15, count 0 2006.190.08:18:01.73#ibcon#about to read 6, iclass 15, count 0 2006.190.08:18:01.73#ibcon#read 6, iclass 15, count 0 2006.190.08:18:01.73#ibcon#end of sib2, iclass 15, count 0 2006.190.08:18:01.73#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:18:01.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:18:01.73#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:18:01.73#ibcon#*before write, iclass 15, count 0 2006.190.08:18:01.73#ibcon#enter sib2, iclass 15, count 0 2006.190.08:18:01.73#ibcon#flushed, iclass 15, count 0 2006.190.08:18:01.73#ibcon#about to write, iclass 15, count 0 2006.190.08:18:01.73#ibcon#wrote, iclass 15, count 0 2006.190.08:18:01.73#ibcon#about to read 3, iclass 15, count 0 2006.190.08:18:01.77#ibcon#read 3, iclass 15, count 0 2006.190.08:18:01.77#ibcon#about to read 4, iclass 15, count 0 2006.190.08:18:01.77#ibcon#read 4, iclass 15, count 0 2006.190.08:18:01.77#ibcon#about to read 5, iclass 15, count 0 2006.190.08:18:01.77#ibcon#read 5, iclass 15, count 0 2006.190.08:18:01.77#ibcon#about to read 6, iclass 15, count 0 2006.190.08:18:01.77#ibcon#read 6, iclass 15, count 0 2006.190.08:18:01.77#ibcon#end of sib2, iclass 15, count 0 2006.190.08:18:01.77#ibcon#*after write, iclass 15, count 0 2006.190.08:18:01.77#ibcon#*before return 0, iclass 15, count 0 2006.190.08:18:01.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:18:01.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.190.08:18:01.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:18:01.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:18:01.77$vc4f8/vb=4,4 2006.190.08:18:01.77#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.190.08:18:01.77#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.190.08:18:01.77#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:01.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:18:01.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:18:01.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:18:01.83#ibcon#enter wrdev, iclass 17, count 2 2006.190.08:18:01.83#ibcon#first serial, iclass 17, count 2 2006.190.08:18:01.83#ibcon#enter sib2, iclass 17, count 2 2006.190.08:18:01.83#ibcon#flushed, iclass 17, count 2 2006.190.08:18:01.83#ibcon#about to write, iclass 17, count 2 2006.190.08:18:01.83#ibcon#wrote, iclass 17, count 2 2006.190.08:18:01.83#ibcon#about to read 3, iclass 17, count 2 2006.190.08:18:01.85#ibcon#read 3, iclass 17, count 2 2006.190.08:18:01.85#ibcon#about to read 4, iclass 17, count 2 2006.190.08:18:01.85#ibcon#read 4, iclass 17, count 2 2006.190.08:18:01.85#ibcon#about to read 5, iclass 17, count 2 2006.190.08:18:01.85#ibcon#read 5, iclass 17, count 2 2006.190.08:18:01.85#ibcon#about to read 6, iclass 17, count 2 2006.190.08:18:01.85#ibcon#read 6, iclass 17, count 2 2006.190.08:18:01.85#ibcon#end of sib2, iclass 17, count 2 2006.190.08:18:01.85#ibcon#*mode == 0, iclass 17, count 2 2006.190.08:18:01.85#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.190.08:18:01.85#ibcon#[27=AT04-04\r\n] 2006.190.08:18:01.85#ibcon#*before write, iclass 17, count 2 2006.190.08:18:01.85#ibcon#enter sib2, iclass 17, count 2 2006.190.08:18:01.85#ibcon#flushed, iclass 17, count 2 2006.190.08:18:01.85#ibcon#about to write, iclass 17, count 2 2006.190.08:18:01.85#ibcon#wrote, iclass 17, count 2 2006.190.08:18:01.85#ibcon#about to read 3, iclass 17, count 2 2006.190.08:18:01.88#ibcon#read 3, iclass 17, count 2 2006.190.08:18:01.88#ibcon#about to read 4, iclass 17, count 2 2006.190.08:18:01.88#ibcon#read 4, iclass 17, count 2 2006.190.08:18:01.88#ibcon#about to read 5, iclass 17, count 2 2006.190.08:18:01.88#ibcon#read 5, iclass 17, count 2 2006.190.08:18:01.88#ibcon#about to read 6, iclass 17, count 2 2006.190.08:18:01.88#ibcon#read 6, iclass 17, count 2 2006.190.08:18:01.88#ibcon#end of sib2, iclass 17, count 2 2006.190.08:18:01.88#ibcon#*after write, iclass 17, count 2 2006.190.08:18:01.88#ibcon#*before return 0, iclass 17, count 2 2006.190.08:18:01.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:18:01.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.190.08:18:01.88#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.190.08:18:01.88#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:01.88#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:18:02.00#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:18:02.00#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:18:02.00#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:18:02.00#ibcon#first serial, iclass 17, count 0 2006.190.08:18:02.00#ibcon#enter sib2, iclass 17, count 0 2006.190.08:18:02.00#ibcon#flushed, iclass 17, count 0 2006.190.08:18:02.00#ibcon#about to write, iclass 17, count 0 2006.190.08:18:02.00#ibcon#wrote, iclass 17, count 0 2006.190.08:18:02.00#ibcon#about to read 3, iclass 17, count 0 2006.190.08:18:02.02#ibcon#read 3, iclass 17, count 0 2006.190.08:18:02.02#ibcon#about to read 4, iclass 17, count 0 2006.190.08:18:02.02#ibcon#read 4, iclass 17, count 0 2006.190.08:18:02.02#ibcon#about to read 5, iclass 17, count 0 2006.190.08:18:02.02#ibcon#read 5, iclass 17, count 0 2006.190.08:18:02.02#ibcon#about to read 6, iclass 17, count 0 2006.190.08:18:02.02#ibcon#read 6, iclass 17, count 0 2006.190.08:18:02.02#ibcon#end of sib2, iclass 17, count 0 2006.190.08:18:02.02#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:18:02.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:18:02.02#ibcon#[27=USB\r\n] 2006.190.08:18:02.02#ibcon#*before write, iclass 17, count 0 2006.190.08:18:02.02#ibcon#enter sib2, iclass 17, count 0 2006.190.08:18:02.02#ibcon#flushed, iclass 17, count 0 2006.190.08:18:02.02#ibcon#about to write, iclass 17, count 0 2006.190.08:18:02.02#ibcon#wrote, iclass 17, count 0 2006.190.08:18:02.02#ibcon#about to read 3, iclass 17, count 0 2006.190.08:18:02.05#ibcon#read 3, iclass 17, count 0 2006.190.08:18:02.05#ibcon#about to read 4, iclass 17, count 0 2006.190.08:18:02.05#ibcon#read 4, iclass 17, count 0 2006.190.08:18:02.05#ibcon#about to read 5, iclass 17, count 0 2006.190.08:18:02.05#ibcon#read 5, iclass 17, count 0 2006.190.08:18:02.05#ibcon#about to read 6, iclass 17, count 0 2006.190.08:18:02.05#ibcon#read 6, iclass 17, count 0 2006.190.08:18:02.05#ibcon#end of sib2, iclass 17, count 0 2006.190.08:18:02.05#ibcon#*after write, iclass 17, count 0 2006.190.08:18:02.05#ibcon#*before return 0, iclass 17, count 0 2006.190.08:18:02.05#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:18:02.05#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.190.08:18:02.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:18:02.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:18:02.05$vc4f8/vblo=5,744.99 2006.190.08:18:02.05#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.190.08:18:02.05#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.190.08:18:02.05#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:02.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:18:02.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:18:02.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:18:02.05#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:18:02.05#ibcon#first serial, iclass 19, count 0 2006.190.08:18:02.05#ibcon#enter sib2, iclass 19, count 0 2006.190.08:18:02.05#ibcon#flushed, iclass 19, count 0 2006.190.08:18:02.05#ibcon#about to write, iclass 19, count 0 2006.190.08:18:02.05#ibcon#wrote, iclass 19, count 0 2006.190.08:18:02.05#ibcon#about to read 3, iclass 19, count 0 2006.190.08:18:02.07#ibcon#read 3, iclass 19, count 0 2006.190.08:18:02.07#ibcon#about to read 4, iclass 19, count 0 2006.190.08:18:02.07#ibcon#read 4, iclass 19, count 0 2006.190.08:18:02.07#ibcon#about to read 5, iclass 19, count 0 2006.190.08:18:02.07#ibcon#read 5, iclass 19, count 0 2006.190.08:18:02.07#ibcon#about to read 6, iclass 19, count 0 2006.190.08:18:02.07#ibcon#read 6, iclass 19, count 0 2006.190.08:18:02.07#ibcon#end of sib2, iclass 19, count 0 2006.190.08:18:02.07#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:18:02.07#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:18:02.07#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:18:02.07#ibcon#*before write, iclass 19, count 0 2006.190.08:18:02.07#ibcon#enter sib2, iclass 19, count 0 2006.190.08:18:02.07#ibcon#flushed, iclass 19, count 0 2006.190.08:18:02.07#ibcon#about to write, iclass 19, count 0 2006.190.08:18:02.07#ibcon#wrote, iclass 19, count 0 2006.190.08:18:02.07#ibcon#about to read 3, iclass 19, count 0 2006.190.08:18:02.11#ibcon#read 3, iclass 19, count 0 2006.190.08:18:02.11#ibcon#about to read 4, iclass 19, count 0 2006.190.08:18:02.11#ibcon#read 4, iclass 19, count 0 2006.190.08:18:02.11#ibcon#about to read 5, iclass 19, count 0 2006.190.08:18:02.11#ibcon#read 5, iclass 19, count 0 2006.190.08:18:02.11#ibcon#about to read 6, iclass 19, count 0 2006.190.08:18:02.11#ibcon#read 6, iclass 19, count 0 2006.190.08:18:02.11#ibcon#end of sib2, iclass 19, count 0 2006.190.08:18:02.11#ibcon#*after write, iclass 19, count 0 2006.190.08:18:02.11#ibcon#*before return 0, iclass 19, count 0 2006.190.08:18:02.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:18:02.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.190.08:18:02.11#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:18:02.11#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:18:02.11$vc4f8/vb=5,4 2006.190.08:18:02.11#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.190.08:18:02.11#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.190.08:18:02.11#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:02.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:18:02.17#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:18:02.17#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:18:02.17#ibcon#enter wrdev, iclass 21, count 2 2006.190.08:18:02.17#ibcon#first serial, iclass 21, count 2 2006.190.08:18:02.17#ibcon#enter sib2, iclass 21, count 2 2006.190.08:18:02.17#ibcon#flushed, iclass 21, count 2 2006.190.08:18:02.17#ibcon#about to write, iclass 21, count 2 2006.190.08:18:02.17#ibcon#wrote, iclass 21, count 2 2006.190.08:18:02.17#ibcon#about to read 3, iclass 21, count 2 2006.190.08:18:02.19#ibcon#read 3, iclass 21, count 2 2006.190.08:18:02.19#ibcon#about to read 4, iclass 21, count 2 2006.190.08:18:02.19#ibcon#read 4, iclass 21, count 2 2006.190.08:18:02.19#ibcon#about to read 5, iclass 21, count 2 2006.190.08:18:02.19#ibcon#read 5, iclass 21, count 2 2006.190.08:18:02.19#ibcon#about to read 6, iclass 21, count 2 2006.190.08:18:02.19#ibcon#read 6, iclass 21, count 2 2006.190.08:18:02.19#ibcon#end of sib2, iclass 21, count 2 2006.190.08:18:02.19#ibcon#*mode == 0, iclass 21, count 2 2006.190.08:18:02.19#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.190.08:18:02.19#ibcon#[27=AT05-04\r\n] 2006.190.08:18:02.19#ibcon#*before write, iclass 21, count 2 2006.190.08:18:02.19#ibcon#enter sib2, iclass 21, count 2 2006.190.08:18:02.19#ibcon#flushed, iclass 21, count 2 2006.190.08:18:02.19#ibcon#about to write, iclass 21, count 2 2006.190.08:18:02.19#ibcon#wrote, iclass 21, count 2 2006.190.08:18:02.19#ibcon#about to read 3, iclass 21, count 2 2006.190.08:18:02.22#ibcon#read 3, iclass 21, count 2 2006.190.08:18:02.22#ibcon#about to read 4, iclass 21, count 2 2006.190.08:18:02.22#ibcon#read 4, iclass 21, count 2 2006.190.08:18:02.22#ibcon#about to read 5, iclass 21, count 2 2006.190.08:18:02.22#ibcon#read 5, iclass 21, count 2 2006.190.08:18:02.22#ibcon#about to read 6, iclass 21, count 2 2006.190.08:18:02.22#ibcon#read 6, iclass 21, count 2 2006.190.08:18:02.22#ibcon#end of sib2, iclass 21, count 2 2006.190.08:18:02.22#ibcon#*after write, iclass 21, count 2 2006.190.08:18:02.22#ibcon#*before return 0, iclass 21, count 2 2006.190.08:18:02.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:18:02.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.190.08:18:02.22#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.190.08:18:02.22#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:02.22#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:18:02.34#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:18:02.34#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:18:02.34#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:18:02.34#ibcon#first serial, iclass 21, count 0 2006.190.08:18:02.34#ibcon#enter sib2, iclass 21, count 0 2006.190.08:18:02.34#ibcon#flushed, iclass 21, count 0 2006.190.08:18:02.34#ibcon#about to write, iclass 21, count 0 2006.190.08:18:02.34#ibcon#wrote, iclass 21, count 0 2006.190.08:18:02.34#ibcon#about to read 3, iclass 21, count 0 2006.190.08:18:02.36#ibcon#read 3, iclass 21, count 0 2006.190.08:18:02.36#ibcon#about to read 4, iclass 21, count 0 2006.190.08:18:02.36#ibcon#read 4, iclass 21, count 0 2006.190.08:18:02.36#ibcon#about to read 5, iclass 21, count 0 2006.190.08:18:02.36#ibcon#read 5, iclass 21, count 0 2006.190.08:18:02.36#ibcon#about to read 6, iclass 21, count 0 2006.190.08:18:02.36#ibcon#read 6, iclass 21, count 0 2006.190.08:18:02.36#ibcon#end of sib2, iclass 21, count 0 2006.190.08:18:02.36#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:18:02.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:18:02.36#ibcon#[27=USB\r\n] 2006.190.08:18:02.36#ibcon#*before write, iclass 21, count 0 2006.190.08:18:02.36#ibcon#enter sib2, iclass 21, count 0 2006.190.08:18:02.36#ibcon#flushed, iclass 21, count 0 2006.190.08:18:02.36#ibcon#about to write, iclass 21, count 0 2006.190.08:18:02.36#ibcon#wrote, iclass 21, count 0 2006.190.08:18:02.36#ibcon#about to read 3, iclass 21, count 0 2006.190.08:18:02.39#ibcon#read 3, iclass 21, count 0 2006.190.08:18:02.39#ibcon#about to read 4, iclass 21, count 0 2006.190.08:18:02.39#ibcon#read 4, iclass 21, count 0 2006.190.08:18:02.39#ibcon#about to read 5, iclass 21, count 0 2006.190.08:18:02.39#ibcon#read 5, iclass 21, count 0 2006.190.08:18:02.39#ibcon#about to read 6, iclass 21, count 0 2006.190.08:18:02.39#ibcon#read 6, iclass 21, count 0 2006.190.08:18:02.39#ibcon#end of sib2, iclass 21, count 0 2006.190.08:18:02.39#ibcon#*after write, iclass 21, count 0 2006.190.08:18:02.39#ibcon#*before return 0, iclass 21, count 0 2006.190.08:18:02.39#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:18:02.39#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.190.08:18:02.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:18:02.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:18:02.39$vc4f8/vblo=6,752.99 2006.190.08:18:02.39#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.190.08:18:02.39#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.190.08:18:02.39#ibcon#ireg 17 cls_cnt 0 2006.190.08:18:02.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:18:02.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:18:02.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:18:02.39#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:18:02.39#ibcon#first serial, iclass 23, count 0 2006.190.08:18:02.39#ibcon#enter sib2, iclass 23, count 0 2006.190.08:18:02.39#ibcon#flushed, iclass 23, count 0 2006.190.08:18:02.39#ibcon#about to write, iclass 23, count 0 2006.190.08:18:02.39#ibcon#wrote, iclass 23, count 0 2006.190.08:18:02.39#ibcon#about to read 3, iclass 23, count 0 2006.190.08:18:02.41#ibcon#read 3, iclass 23, count 0 2006.190.08:18:02.41#ibcon#about to read 4, iclass 23, count 0 2006.190.08:18:02.41#ibcon#read 4, iclass 23, count 0 2006.190.08:18:02.41#ibcon#about to read 5, iclass 23, count 0 2006.190.08:18:02.41#ibcon#read 5, iclass 23, count 0 2006.190.08:18:02.41#ibcon#about to read 6, iclass 23, count 0 2006.190.08:18:02.41#ibcon#read 6, iclass 23, count 0 2006.190.08:18:02.41#ibcon#end of sib2, iclass 23, count 0 2006.190.08:18:02.41#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:18:02.41#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:18:02.41#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:18:02.41#ibcon#*before write, iclass 23, count 0 2006.190.08:18:02.41#ibcon#enter sib2, iclass 23, count 0 2006.190.08:18:02.41#ibcon#flushed, iclass 23, count 0 2006.190.08:18:02.41#ibcon#about to write, iclass 23, count 0 2006.190.08:18:02.41#ibcon#wrote, iclass 23, count 0 2006.190.08:18:02.41#ibcon#about to read 3, iclass 23, count 0 2006.190.08:18:02.45#ibcon#read 3, iclass 23, count 0 2006.190.08:18:02.45#ibcon#about to read 4, iclass 23, count 0 2006.190.08:18:02.45#ibcon#read 4, iclass 23, count 0 2006.190.08:18:02.45#ibcon#about to read 5, iclass 23, count 0 2006.190.08:18:02.45#ibcon#read 5, iclass 23, count 0 2006.190.08:18:02.45#ibcon#about to read 6, iclass 23, count 0 2006.190.08:18:02.45#ibcon#read 6, iclass 23, count 0 2006.190.08:18:02.45#ibcon#end of sib2, iclass 23, count 0 2006.190.08:18:02.45#ibcon#*after write, iclass 23, count 0 2006.190.08:18:02.45#ibcon#*before return 0, iclass 23, count 0 2006.190.08:18:02.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:18:02.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.190.08:18:02.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:18:02.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:18:02.45$vc4f8/vb=6,4 2006.190.08:18:02.45#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.190.08:18:02.45#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.190.08:18:02.45#ibcon#ireg 11 cls_cnt 2 2006.190.08:18:02.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:18:02.51#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:18:02.51#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:18:02.51#ibcon#enter wrdev, iclass 25, count 2 2006.190.08:18:02.51#ibcon#first serial, iclass 25, count 2 2006.190.08:18:02.51#ibcon#enter sib2, iclass 25, count 2 2006.190.08:18:02.51#ibcon#flushed, iclass 25, count 2 2006.190.08:18:02.51#ibcon#about to write, iclass 25, count 2 2006.190.08:18:02.51#ibcon#wrote, iclass 25, count 2 2006.190.08:18:02.51#ibcon#about to read 3, iclass 25, count 2 2006.190.08:18:02.53#ibcon#read 3, iclass 25, count 2 2006.190.08:18:02.53#ibcon#about to read 4, iclass 25, count 2 2006.190.08:18:02.53#ibcon#read 4, iclass 25, count 2 2006.190.08:18:02.53#ibcon#about to read 5, iclass 25, count 2 2006.190.08:18:02.53#ibcon#read 5, iclass 25, count 2 2006.190.08:18:02.53#ibcon#about to read 6, iclass 25, count 2 2006.190.08:18:02.53#ibcon#read 6, iclass 25, count 2 2006.190.08:18:02.53#ibcon#end of sib2, iclass 25, count 2 2006.190.08:18:02.53#ibcon#*mode == 0, iclass 25, count 2 2006.190.08:18:02.53#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.190.08:18:02.53#ibcon#[27=AT06-04\r\n] 2006.190.08:18:02.53#ibcon#*before write, iclass 25, count 2 2006.190.08:18:02.53#ibcon#enter sib2, iclass 25, count 2 2006.190.08:18:02.53#ibcon#flushed, iclass 25, count 2 2006.190.08:18:02.53#ibcon#about to write, iclass 25, count 2 2006.190.08:18:02.53#ibcon#wrote, iclass 25, count 2 2006.190.08:18:02.53#ibcon#about to read 3, iclass 25, count 2 2006.190.08:18:02.56#ibcon#read 3, iclass 25, count 2 2006.190.08:18:02.56#ibcon#about to read 4, iclass 25, count 2 2006.190.08:18:02.56#ibcon#read 4, iclass 25, count 2 2006.190.08:18:02.56#ibcon#about to read 5, iclass 25, count 2 2006.190.08:18:02.56#ibcon#read 5, iclass 25, count 2 2006.190.08:18:02.56#ibcon#about to read 6, iclass 25, count 2 2006.190.08:18:02.56#ibcon#read 6, iclass 25, count 2 2006.190.08:18:02.56#ibcon#end of sib2, iclass 25, count 2 2006.190.08:18:02.56#ibcon#*after write, iclass 25, count 2 2006.190.08:18:02.56#ibcon#*before return 0, iclass 25, count 2 2006.190.08:18:02.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:18:02.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.190.08:18:02.56#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.190.08:18:02.56#ibcon#ireg 7 cls_cnt 0 2006.190.08:18:02.56#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:18:02.68#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:18:02.68#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:18:02.68#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:18:02.68#ibcon#first serial, iclass 25, count 0 2006.190.08:18:02.68#ibcon#enter sib2, iclass 25, count 0 2006.190.08:18:02.68#ibcon#flushed, iclass 25, count 0 2006.190.08:18:02.68#ibcon#about to write, iclass 25, count 0 2006.190.08:18:02.68#ibcon#wrote, iclass 25, count 0 2006.190.08:18:02.68#ibcon#about to read 3, iclass 25, count 0 2006.190.08:18:02.70#ibcon#read 3, iclass 25, count 0 2006.190.08:18:02.70#ibcon#about to read 4, iclass 25, count 0 2006.190.08:18:02.70#ibcon#read 4, iclass 25, count 0 2006.190.08:18:02.70#ibcon#about to read 5, iclass 25, count 0 2006.190.08:18:02.70#ibcon#read 5, iclass 25, count 0 2006.190.08:18:02.70#ibcon#about to read 6, iclass 25, count 0 2006.190.08:18:02.70#ibcon#read 6, iclass 25, count 0 2006.190.08:18:02.70#ibcon#end of sib2, iclass 25, count 0 2006.190.08:18:02.70#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:18:02.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:18:02.70#ibcon#[27=USB\r\n] 2006.190.08:18:02.70#ibcon#*before write, iclass 25, count 0 2006.190.08:18:02.70#ibcon#enter sib2, iclass 25, count 0 2006.190.08:18:02.70#ibcon#flushed, iclass 25, count 0 2006.190.08:18:02.70#ibcon#about to write, iclass 25, count 0 2006.190.08:18:02.70#ibcon#wrote, iclass 25, count 0 2006.190.08:18:02.70#ibcon#about to read 3, iclass 25, count 0 2006.190.08:18:02.73#ibcon#read 3, iclass 25, count 0 2006.190.08:18:02.73#ibcon#about to read 4, iclass 25, count 0 2006.190.08:18:02.73#ibcon#read 4, iclass 25, count 0 2006.190.08:18:02.73#ibcon#about to read 5, iclass 25, count 0 2006.190.08:18:02.73#ibcon#read 5, iclass 25, count 0 2006.190.08:18:02.73#ibcon#about to read 6, iclass 25, count 0 2006.190.08:18:02.73#ibcon#read 6, iclass 25, count 0 2006.190.08:18:02.73#ibcon#end of sib2, iclass 25, count 0 2006.190.08:18:02.73#ibcon#*after write, iclass 25, count 0 2006.190.08:18:02.73#ibcon#*before return 0, iclass 25, count 0 2006.190.08:18:02.73#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:18:02.73#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.190.08:18:02.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:18:02.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:18:02.73$vc4f8/vabw=wide 2006.190.08:18:02.73#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.08:18:02.73#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.08:18:02.73#ibcon#ireg 8 cls_cnt 0 2006.190.08:18:02.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:18:02.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:18:02.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:18:02.73#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:18:02.73#ibcon#first serial, iclass 27, count 0 2006.190.08:18:02.73#ibcon#enter sib2, iclass 27, count 0 2006.190.08:18:02.73#ibcon#flushed, iclass 27, count 0 2006.190.08:18:02.73#ibcon#about to write, iclass 27, count 0 2006.190.08:18:02.73#ibcon#wrote, iclass 27, count 0 2006.190.08:18:02.73#ibcon#about to read 3, iclass 27, count 0 2006.190.08:18:02.75#ibcon#read 3, iclass 27, count 0 2006.190.08:18:02.75#ibcon#about to read 4, iclass 27, count 0 2006.190.08:18:02.75#ibcon#read 4, iclass 27, count 0 2006.190.08:18:02.75#ibcon#about to read 5, iclass 27, count 0 2006.190.08:18:02.75#ibcon#read 5, iclass 27, count 0 2006.190.08:18:02.75#ibcon#about to read 6, iclass 27, count 0 2006.190.08:18:02.75#ibcon#read 6, iclass 27, count 0 2006.190.08:18:02.75#ibcon#end of sib2, iclass 27, count 0 2006.190.08:18:02.75#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:18:02.75#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:18:02.75#ibcon#[25=BW32\r\n] 2006.190.08:18:02.75#ibcon#*before write, iclass 27, count 0 2006.190.08:18:02.75#ibcon#enter sib2, iclass 27, count 0 2006.190.08:18:02.75#ibcon#flushed, iclass 27, count 0 2006.190.08:18:02.75#ibcon#about to write, iclass 27, count 0 2006.190.08:18:02.75#ibcon#wrote, iclass 27, count 0 2006.190.08:18:02.75#ibcon#about to read 3, iclass 27, count 0 2006.190.08:18:02.78#abcon#<5=/04 2.2 4.4 24.411001012.2\r\n> 2006.190.08:18:02.78#ibcon#read 3, iclass 27, count 0 2006.190.08:18:02.78#ibcon#about to read 4, iclass 27, count 0 2006.190.08:18:02.78#ibcon#read 4, iclass 27, count 0 2006.190.08:18:02.78#ibcon#about to read 5, iclass 27, count 0 2006.190.08:18:02.78#ibcon#read 5, iclass 27, count 0 2006.190.08:18:02.78#ibcon#about to read 6, iclass 27, count 0 2006.190.08:18:02.78#ibcon#read 6, iclass 27, count 0 2006.190.08:18:02.78#ibcon#end of sib2, iclass 27, count 0 2006.190.08:18:02.78#ibcon#*after write, iclass 27, count 0 2006.190.08:18:02.78#ibcon#*before return 0, iclass 27, count 0 2006.190.08:18:02.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:18:02.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:18:02.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:18:02.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:18:02.78$vc4f8/vbbw=wide 2006.190.08:18:02.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.08:18:02.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.08:18:02.78#ibcon#ireg 8 cls_cnt 0 2006.190.08:18:02.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:18:02.80#abcon#{5=INTERFACE CLEAR} 2006.190.08:18:02.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:18:02.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:18:02.85#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:18:02.85#ibcon#first serial, iclass 32, count 0 2006.190.08:18:02.85#ibcon#enter sib2, iclass 32, count 0 2006.190.08:18:02.85#ibcon#flushed, iclass 32, count 0 2006.190.08:18:02.85#ibcon#about to write, iclass 32, count 0 2006.190.08:18:02.85#ibcon#wrote, iclass 32, count 0 2006.190.08:18:02.85#ibcon#about to read 3, iclass 32, count 0 2006.190.08:18:02.86#abcon#[5=S1D000X0/0*\r\n] 2006.190.08:18:02.87#ibcon#read 3, iclass 32, count 0 2006.190.08:18:02.87#ibcon#about to read 4, iclass 32, count 0 2006.190.08:18:02.87#ibcon#read 4, iclass 32, count 0 2006.190.08:18:02.87#ibcon#about to read 5, iclass 32, count 0 2006.190.08:18:02.87#ibcon#read 5, iclass 32, count 0 2006.190.08:18:02.87#ibcon#about to read 6, iclass 32, count 0 2006.190.08:18:02.87#ibcon#read 6, iclass 32, count 0 2006.190.08:18:02.87#ibcon#end of sib2, iclass 32, count 0 2006.190.08:18:02.87#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:18:02.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:18:02.87#ibcon#[27=BW32\r\n] 2006.190.08:18:02.87#ibcon#*before write, iclass 32, count 0 2006.190.08:18:02.87#ibcon#enter sib2, iclass 32, count 0 2006.190.08:18:02.87#ibcon#flushed, iclass 32, count 0 2006.190.08:18:02.87#ibcon#about to write, iclass 32, count 0 2006.190.08:18:02.87#ibcon#wrote, iclass 32, count 0 2006.190.08:18:02.87#ibcon#about to read 3, iclass 32, count 0 2006.190.08:18:02.90#ibcon#read 3, iclass 32, count 0 2006.190.08:18:02.90#ibcon#about to read 4, iclass 32, count 0 2006.190.08:18:02.90#ibcon#read 4, iclass 32, count 0 2006.190.08:18:02.90#ibcon#about to read 5, iclass 32, count 0 2006.190.08:18:02.90#ibcon#read 5, iclass 32, count 0 2006.190.08:18:02.90#ibcon#about to read 6, iclass 32, count 0 2006.190.08:18:02.90#ibcon#read 6, iclass 32, count 0 2006.190.08:18:02.90#ibcon#end of sib2, iclass 32, count 0 2006.190.08:18:02.90#ibcon#*after write, iclass 32, count 0 2006.190.08:18:02.90#ibcon#*before return 0, iclass 32, count 0 2006.190.08:18:02.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:18:02.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:18:02.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:18:02.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:18:02.90$4f8m12a/ifd4f 2006.190.08:18:02.90$ifd4f/lo= 2006.190.08:18:02.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:18:02.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:18:02.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:18:02.90$ifd4f/patch= 2006.190.08:18:02.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:18:02.90$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:18:02.90$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:18:02.90$4f8m12a/"form=m,16.000,1:2 2006.190.08:18:02.90$4f8m12a/"tpicd 2006.190.08:18:02.90$4f8m12a/echo=off 2006.190.08:18:02.90$4f8m12a/xlog=off 2006.190.08:18:02.90:!2006.190.08:18:40 2006.190.08:18:22.14#trakl#Source acquired 2006.190.08:18:24.14#flagr#flagr/antenna,acquired 2006.190.08:18:40.00:preob 2006.190.08:18:40.14/onsource/TRACKING 2006.190.08:18:40.14:!2006.190.08:18:50 2006.190.08:18:50.00:data_valid=on 2006.190.08:18:50.00:midob 2006.190.08:18:51.14/onsource/TRACKING 2006.190.08:18:51.14/wx/24.41,1012.2,100 2006.190.08:18:51.32/cable/+6.4715E-03 2006.190.08:18:52.41/va/01,08,usb,yes,42,45 2006.190.08:18:52.41/va/02,07,usb,yes,43,45 2006.190.08:18:52.41/va/03,06,usb,yes,45,45 2006.190.08:18:52.41/va/04,07,usb,yes,43,47 2006.190.08:18:52.41/va/05,07,usb,yes,48,51 2006.190.08:18:52.41/va/06,06,usb,yes,47,46 2006.190.08:18:52.41/va/07,06,usb,yes,47,47 2006.190.08:18:52.41/va/08,06,usb,yes,50,49 2006.190.08:18:52.64/valo/01,532.99,yes,locked 2006.190.08:18:52.64/valo/02,572.99,yes,locked 2006.190.08:18:52.64/valo/03,672.99,yes,locked 2006.190.08:18:52.64/valo/04,832.99,yes,locked 2006.190.08:18:52.64/valo/05,652.99,yes,locked 2006.190.08:18:52.64/valo/06,772.99,yes,locked 2006.190.08:18:52.64/valo/07,832.99,yes,locked 2006.190.08:18:52.64/valo/08,852.99,yes,locked 2006.190.08:18:53.73/vb/01,04,usb,yes,35,34 2006.190.08:18:53.73/vb/02,04,usb,yes,37,39 2006.190.08:18:53.73/vb/03,04,usb,yes,33,38 2006.190.08:18:53.73/vb/04,04,usb,yes,35,35 2006.190.08:18:53.73/vb/05,04,usb,yes,33,37 2006.190.08:18:53.73/vb/06,04,usb,yes,34,37 2006.190.08:18:53.73/vb/07,04,usb,yes,36,36 2006.190.08:18:53.73/vb/08,04,usb,yes,33,37 2006.190.08:18:53.96/vblo/01,632.99,yes,locked 2006.190.08:18:53.96/vblo/02,640.99,yes,locked 2006.190.08:18:53.96/vblo/03,656.99,yes,locked 2006.190.08:18:53.96/vblo/04,712.99,yes,locked 2006.190.08:18:53.96/vblo/05,744.99,yes,locked 2006.190.08:18:53.96/vblo/06,752.99,yes,locked 2006.190.08:18:53.96/vblo/07,734.99,yes,locked 2006.190.08:18:53.96/vblo/08,744.99,yes,locked 2006.190.08:18:54.11/vabw/8 2006.190.08:18:54.26/vbbw/8 2006.190.08:18:54.35/xfe/off,on,15.0 2006.190.08:18:54.74/ifatt/23,28,28,28 2006.190.08:18:55.08/fmout-gps/S +2.86E-07 2006.190.08:18:55.16:!2006.190.08:19:50 2006.190.08:19:50.01:data_valid=off 2006.190.08:19:50.01:postob 2006.190.08:19:50.12/cable/+6.4715E-03 2006.190.08:19:50.12/wx/24.41,1012.2,100 2006.190.08:19:51.07/fmout-gps/S +2.87E-07 2006.190.08:19:51.07:scan_name=190-0821,k06190,60 2006.190.08:19:51.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.190.08:19:51.16#flagr#flagr/antenna,new-source 2006.190.08:19:52.12:checkk5 2006.190.08:19:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:19:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:19:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:19:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:19:54.02/chk_obsdata//k5ts1/T1900818??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:19:54.40/chk_obsdata//k5ts2/T1900818??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:19:54.78/chk_obsdata//k5ts3/T1900818??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:19:55.15/chk_obsdata//k5ts4/T1900818??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:19:55.86/k5log//k5ts1_log_newline 2006.190.08:19:56.55/k5log//k5ts2_log_newline 2006.190.08:19:57.25/k5log//k5ts3_log_newline 2006.190.08:19:57.95/k5log//k5ts4_log_newline 2006.190.08:19:57.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:19:57.98:4f8m12a=3 2006.190.08:19:57.98$4f8m12a/echo=on 2006.190.08:19:57.98$4f8m12a/pcalon 2006.190.08:19:57.98$pcalon/"no phase cal control is implemented here 2006.190.08:19:57.98$4f8m12a/"tpicd=stop 2006.190.08:19:57.98$4f8m12a/vc4f8 2006.190.08:19:57.98$vc4f8/valo=1,532.99 2006.190.08:19:57.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:19:57.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:19:57.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:19:57.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:19:57.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:19:57.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:19:57.98#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:19:57.98#ibcon#first serial, iclass 6, count 0 2006.190.08:19:57.98#ibcon#enter sib2, iclass 6, count 0 2006.190.08:19:57.98#ibcon#flushed, iclass 6, count 0 2006.190.08:19:57.98#ibcon#about to write, iclass 6, count 0 2006.190.08:19:57.98#ibcon#wrote, iclass 6, count 0 2006.190.08:19:57.98#ibcon#about to read 3, iclass 6, count 0 2006.190.08:19:58.03#ibcon#read 3, iclass 6, count 0 2006.190.08:19:58.03#ibcon#about to read 4, iclass 6, count 0 2006.190.08:19:58.03#ibcon#read 4, iclass 6, count 0 2006.190.08:19:58.03#ibcon#about to read 5, iclass 6, count 0 2006.190.08:19:58.03#ibcon#read 5, iclass 6, count 0 2006.190.08:19:58.03#ibcon#about to read 6, iclass 6, count 0 2006.190.08:19:58.03#ibcon#read 6, iclass 6, count 0 2006.190.08:19:58.03#ibcon#end of sib2, iclass 6, count 0 2006.190.08:19:58.03#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:19:58.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:19:58.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:19:58.03#ibcon#*before write, iclass 6, count 0 2006.190.08:19:58.03#ibcon#enter sib2, iclass 6, count 0 2006.190.08:19:58.03#ibcon#flushed, iclass 6, count 0 2006.190.08:19:58.03#ibcon#about to write, iclass 6, count 0 2006.190.08:19:58.03#ibcon#wrote, iclass 6, count 0 2006.190.08:19:58.03#ibcon#about to read 3, iclass 6, count 0 2006.190.08:19:58.08#ibcon#read 3, iclass 6, count 0 2006.190.08:19:58.08#ibcon#about to read 4, iclass 6, count 0 2006.190.08:19:58.08#ibcon#read 4, iclass 6, count 0 2006.190.08:19:58.08#ibcon#about to read 5, iclass 6, count 0 2006.190.08:19:58.08#ibcon#read 5, iclass 6, count 0 2006.190.08:19:58.08#ibcon#about to read 6, iclass 6, count 0 2006.190.08:19:58.08#ibcon#read 6, iclass 6, count 0 2006.190.08:19:58.08#ibcon#end of sib2, iclass 6, count 0 2006.190.08:19:58.08#ibcon#*after write, iclass 6, count 0 2006.190.08:19:58.08#ibcon#*before return 0, iclass 6, count 0 2006.190.08:19:58.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:19:58.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:19:58.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:19:58.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:19:58.08$vc4f8/va=1,8 2006.190.08:19:58.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.08:19:58.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.08:19:58.08#ibcon#ireg 11 cls_cnt 2 2006.190.08:19:58.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:19:58.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:19:58.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:19:58.08#ibcon#enter wrdev, iclass 10, count 2 2006.190.08:19:58.08#ibcon#first serial, iclass 10, count 2 2006.190.08:19:58.08#ibcon#enter sib2, iclass 10, count 2 2006.190.08:19:58.08#ibcon#flushed, iclass 10, count 2 2006.190.08:19:58.08#ibcon#about to write, iclass 10, count 2 2006.190.08:19:58.08#ibcon#wrote, iclass 10, count 2 2006.190.08:19:58.08#ibcon#about to read 3, iclass 10, count 2 2006.190.08:19:58.10#ibcon#read 3, iclass 10, count 2 2006.190.08:19:58.10#ibcon#about to read 4, iclass 10, count 2 2006.190.08:19:58.10#ibcon#read 4, iclass 10, count 2 2006.190.08:19:58.10#ibcon#about to read 5, iclass 10, count 2 2006.190.08:19:58.10#ibcon#read 5, iclass 10, count 2 2006.190.08:19:58.10#ibcon#about to read 6, iclass 10, count 2 2006.190.08:19:58.10#ibcon#read 6, iclass 10, count 2 2006.190.08:19:58.10#ibcon#end of sib2, iclass 10, count 2 2006.190.08:19:58.10#ibcon#*mode == 0, iclass 10, count 2 2006.190.08:19:58.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.08:19:58.10#ibcon#[25=AT01-08\r\n] 2006.190.08:19:58.10#ibcon#*before write, iclass 10, count 2 2006.190.08:19:58.10#ibcon#enter sib2, iclass 10, count 2 2006.190.08:19:58.10#ibcon#flushed, iclass 10, count 2 2006.190.08:19:58.10#ibcon#about to write, iclass 10, count 2 2006.190.08:19:58.10#ibcon#wrote, iclass 10, count 2 2006.190.08:19:58.10#ibcon#about to read 3, iclass 10, count 2 2006.190.08:19:58.13#ibcon#read 3, iclass 10, count 2 2006.190.08:19:58.13#ibcon#about to read 4, iclass 10, count 2 2006.190.08:19:58.13#ibcon#read 4, iclass 10, count 2 2006.190.08:19:58.13#ibcon#about to read 5, iclass 10, count 2 2006.190.08:19:58.13#ibcon#read 5, iclass 10, count 2 2006.190.08:19:58.13#ibcon#about to read 6, iclass 10, count 2 2006.190.08:19:58.13#ibcon#read 6, iclass 10, count 2 2006.190.08:19:58.13#ibcon#end of sib2, iclass 10, count 2 2006.190.08:19:58.13#ibcon#*after write, iclass 10, count 2 2006.190.08:19:58.13#ibcon#*before return 0, iclass 10, count 2 2006.190.08:19:58.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:19:58.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:19:58.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.08:19:58.13#ibcon#ireg 7 cls_cnt 0 2006.190.08:19:58.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:19:58.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:19:58.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:19:58.25#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:19:58.25#ibcon#first serial, iclass 10, count 0 2006.190.08:19:58.25#ibcon#enter sib2, iclass 10, count 0 2006.190.08:19:58.25#ibcon#flushed, iclass 10, count 0 2006.190.08:19:58.25#ibcon#about to write, iclass 10, count 0 2006.190.08:19:58.25#ibcon#wrote, iclass 10, count 0 2006.190.08:19:58.25#ibcon#about to read 3, iclass 10, count 0 2006.190.08:19:58.27#ibcon#read 3, iclass 10, count 0 2006.190.08:19:58.27#ibcon#about to read 4, iclass 10, count 0 2006.190.08:19:58.27#ibcon#read 4, iclass 10, count 0 2006.190.08:19:58.27#ibcon#about to read 5, iclass 10, count 0 2006.190.08:19:58.27#ibcon#read 5, iclass 10, count 0 2006.190.08:19:58.27#ibcon#about to read 6, iclass 10, count 0 2006.190.08:19:58.27#ibcon#read 6, iclass 10, count 0 2006.190.08:19:58.27#ibcon#end of sib2, iclass 10, count 0 2006.190.08:19:58.27#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:19:58.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:19:58.27#ibcon#[25=USB\r\n] 2006.190.08:19:58.27#ibcon#*before write, iclass 10, count 0 2006.190.08:19:58.27#ibcon#enter sib2, iclass 10, count 0 2006.190.08:19:58.27#ibcon#flushed, iclass 10, count 0 2006.190.08:19:58.27#ibcon#about to write, iclass 10, count 0 2006.190.08:19:58.27#ibcon#wrote, iclass 10, count 0 2006.190.08:19:58.27#ibcon#about to read 3, iclass 10, count 0 2006.190.08:19:58.30#ibcon#read 3, iclass 10, count 0 2006.190.08:19:58.30#ibcon#about to read 4, iclass 10, count 0 2006.190.08:19:58.30#ibcon#read 4, iclass 10, count 0 2006.190.08:19:58.30#ibcon#about to read 5, iclass 10, count 0 2006.190.08:19:58.30#ibcon#read 5, iclass 10, count 0 2006.190.08:19:58.30#ibcon#about to read 6, iclass 10, count 0 2006.190.08:19:58.30#ibcon#read 6, iclass 10, count 0 2006.190.08:19:58.30#ibcon#end of sib2, iclass 10, count 0 2006.190.08:19:58.30#ibcon#*after write, iclass 10, count 0 2006.190.08:19:58.30#ibcon#*before return 0, iclass 10, count 0 2006.190.08:19:58.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:19:58.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:19:58.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:19:58.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:19:58.30$vc4f8/valo=2,572.99 2006.190.08:19:58.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:19:58.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:19:58.30#ibcon#ireg 17 cls_cnt 0 2006.190.08:19:58.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:19:58.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:19:58.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:19:58.30#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:19:58.30#ibcon#first serial, iclass 12, count 0 2006.190.08:19:58.30#ibcon#enter sib2, iclass 12, count 0 2006.190.08:19:58.30#ibcon#flushed, iclass 12, count 0 2006.190.08:19:58.30#ibcon#about to write, iclass 12, count 0 2006.190.08:19:58.30#ibcon#wrote, iclass 12, count 0 2006.190.08:19:58.30#ibcon#about to read 3, iclass 12, count 0 2006.190.08:19:58.32#ibcon#read 3, iclass 12, count 0 2006.190.08:19:58.32#ibcon#about to read 4, iclass 12, count 0 2006.190.08:19:58.32#ibcon#read 4, iclass 12, count 0 2006.190.08:19:58.32#ibcon#about to read 5, iclass 12, count 0 2006.190.08:19:58.32#ibcon#read 5, iclass 12, count 0 2006.190.08:19:58.32#ibcon#about to read 6, iclass 12, count 0 2006.190.08:19:58.32#ibcon#read 6, iclass 12, count 0 2006.190.08:19:58.32#ibcon#end of sib2, iclass 12, count 0 2006.190.08:19:58.32#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:19:58.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:19:58.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:19:58.32#ibcon#*before write, iclass 12, count 0 2006.190.08:19:58.32#ibcon#enter sib2, iclass 12, count 0 2006.190.08:19:58.32#ibcon#flushed, iclass 12, count 0 2006.190.08:19:58.32#ibcon#about to write, iclass 12, count 0 2006.190.08:19:58.32#ibcon#wrote, iclass 12, count 0 2006.190.08:19:58.32#ibcon#about to read 3, iclass 12, count 0 2006.190.08:19:58.36#ibcon#read 3, iclass 12, count 0 2006.190.08:19:58.36#ibcon#about to read 4, iclass 12, count 0 2006.190.08:19:58.36#ibcon#read 4, iclass 12, count 0 2006.190.08:19:58.36#ibcon#about to read 5, iclass 12, count 0 2006.190.08:19:58.36#ibcon#read 5, iclass 12, count 0 2006.190.08:19:58.36#ibcon#about to read 6, iclass 12, count 0 2006.190.08:19:58.36#ibcon#read 6, iclass 12, count 0 2006.190.08:19:58.36#ibcon#end of sib2, iclass 12, count 0 2006.190.08:19:58.36#ibcon#*after write, iclass 12, count 0 2006.190.08:19:58.36#ibcon#*before return 0, iclass 12, count 0 2006.190.08:19:58.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:19:58.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:19:58.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:19:58.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:19:58.36$vc4f8/va=2,7 2006.190.08:19:58.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:19:58.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:19:58.36#ibcon#ireg 11 cls_cnt 2 2006.190.08:19:58.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:19:58.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:19:58.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:19:58.42#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:19:58.42#ibcon#first serial, iclass 14, count 2 2006.190.08:19:58.42#ibcon#enter sib2, iclass 14, count 2 2006.190.08:19:58.42#ibcon#flushed, iclass 14, count 2 2006.190.08:19:58.42#ibcon#about to write, iclass 14, count 2 2006.190.08:19:58.42#ibcon#wrote, iclass 14, count 2 2006.190.08:19:58.42#ibcon#about to read 3, iclass 14, count 2 2006.190.08:19:58.44#ibcon#read 3, iclass 14, count 2 2006.190.08:19:58.44#ibcon#about to read 4, iclass 14, count 2 2006.190.08:19:58.44#ibcon#read 4, iclass 14, count 2 2006.190.08:19:58.44#ibcon#about to read 5, iclass 14, count 2 2006.190.08:19:58.44#ibcon#read 5, iclass 14, count 2 2006.190.08:19:58.44#ibcon#about to read 6, iclass 14, count 2 2006.190.08:19:58.44#ibcon#read 6, iclass 14, count 2 2006.190.08:19:58.44#ibcon#end of sib2, iclass 14, count 2 2006.190.08:19:58.44#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:19:58.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:19:58.44#ibcon#[25=AT02-07\r\n] 2006.190.08:19:58.44#ibcon#*before write, iclass 14, count 2 2006.190.08:19:58.44#ibcon#enter sib2, iclass 14, count 2 2006.190.08:19:58.44#ibcon#flushed, iclass 14, count 2 2006.190.08:19:58.44#ibcon#about to write, iclass 14, count 2 2006.190.08:19:58.44#ibcon#wrote, iclass 14, count 2 2006.190.08:19:58.44#ibcon#about to read 3, iclass 14, count 2 2006.190.08:19:58.47#ibcon#read 3, iclass 14, count 2 2006.190.08:19:58.47#ibcon#about to read 4, iclass 14, count 2 2006.190.08:19:58.47#ibcon#read 4, iclass 14, count 2 2006.190.08:19:58.47#ibcon#about to read 5, iclass 14, count 2 2006.190.08:19:58.47#ibcon#read 5, iclass 14, count 2 2006.190.08:19:58.47#ibcon#about to read 6, iclass 14, count 2 2006.190.08:19:58.47#ibcon#read 6, iclass 14, count 2 2006.190.08:19:58.47#ibcon#end of sib2, iclass 14, count 2 2006.190.08:19:58.47#ibcon#*after write, iclass 14, count 2 2006.190.08:19:58.47#ibcon#*before return 0, iclass 14, count 2 2006.190.08:19:58.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:19:58.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:19:58.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:19:58.47#ibcon#ireg 7 cls_cnt 0 2006.190.08:19:58.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:19:58.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:19:58.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:19:58.59#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:19:58.59#ibcon#first serial, iclass 14, count 0 2006.190.08:19:58.59#ibcon#enter sib2, iclass 14, count 0 2006.190.08:19:58.59#ibcon#flushed, iclass 14, count 0 2006.190.08:19:58.59#ibcon#about to write, iclass 14, count 0 2006.190.08:19:58.59#ibcon#wrote, iclass 14, count 0 2006.190.08:19:58.59#ibcon#about to read 3, iclass 14, count 0 2006.190.08:19:58.61#ibcon#read 3, iclass 14, count 0 2006.190.08:19:58.61#ibcon#about to read 4, iclass 14, count 0 2006.190.08:19:58.61#ibcon#read 4, iclass 14, count 0 2006.190.08:19:58.61#ibcon#about to read 5, iclass 14, count 0 2006.190.08:19:58.61#ibcon#read 5, iclass 14, count 0 2006.190.08:19:58.61#ibcon#about to read 6, iclass 14, count 0 2006.190.08:19:58.61#ibcon#read 6, iclass 14, count 0 2006.190.08:19:58.61#ibcon#end of sib2, iclass 14, count 0 2006.190.08:19:58.61#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:19:58.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:19:58.61#ibcon#[25=USB\r\n] 2006.190.08:19:58.61#ibcon#*before write, iclass 14, count 0 2006.190.08:19:58.61#ibcon#enter sib2, iclass 14, count 0 2006.190.08:19:58.61#ibcon#flushed, iclass 14, count 0 2006.190.08:19:58.61#ibcon#about to write, iclass 14, count 0 2006.190.08:19:58.61#ibcon#wrote, iclass 14, count 0 2006.190.08:19:58.61#ibcon#about to read 3, iclass 14, count 0 2006.190.08:19:58.64#ibcon#read 3, iclass 14, count 0 2006.190.08:19:58.64#ibcon#about to read 4, iclass 14, count 0 2006.190.08:19:58.64#ibcon#read 4, iclass 14, count 0 2006.190.08:19:58.64#ibcon#about to read 5, iclass 14, count 0 2006.190.08:19:58.64#ibcon#read 5, iclass 14, count 0 2006.190.08:19:58.64#ibcon#about to read 6, iclass 14, count 0 2006.190.08:19:58.64#ibcon#read 6, iclass 14, count 0 2006.190.08:19:58.64#ibcon#end of sib2, iclass 14, count 0 2006.190.08:19:58.64#ibcon#*after write, iclass 14, count 0 2006.190.08:19:58.64#ibcon#*before return 0, iclass 14, count 0 2006.190.08:19:58.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:19:58.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:19:58.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:19:58.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:19:58.64$vc4f8/valo=3,672.99 2006.190.08:19:58.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:19:58.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:19:58.64#ibcon#ireg 17 cls_cnt 0 2006.190.08:19:58.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:19:58.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:19:58.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:19:58.64#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:19:58.64#ibcon#first serial, iclass 16, count 0 2006.190.08:19:58.64#ibcon#enter sib2, iclass 16, count 0 2006.190.08:19:58.64#ibcon#flushed, iclass 16, count 0 2006.190.08:19:58.64#ibcon#about to write, iclass 16, count 0 2006.190.08:19:58.64#ibcon#wrote, iclass 16, count 0 2006.190.08:19:58.64#ibcon#about to read 3, iclass 16, count 0 2006.190.08:19:58.66#ibcon#read 3, iclass 16, count 0 2006.190.08:19:58.66#ibcon#about to read 4, iclass 16, count 0 2006.190.08:19:58.66#ibcon#read 4, iclass 16, count 0 2006.190.08:19:58.66#ibcon#about to read 5, iclass 16, count 0 2006.190.08:19:58.66#ibcon#read 5, iclass 16, count 0 2006.190.08:19:58.66#ibcon#about to read 6, iclass 16, count 0 2006.190.08:19:58.66#ibcon#read 6, iclass 16, count 0 2006.190.08:19:58.66#ibcon#end of sib2, iclass 16, count 0 2006.190.08:19:58.66#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:19:58.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:19:58.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:19:58.66#ibcon#*before write, iclass 16, count 0 2006.190.08:19:58.66#ibcon#enter sib2, iclass 16, count 0 2006.190.08:19:58.66#ibcon#flushed, iclass 16, count 0 2006.190.08:19:58.66#ibcon#about to write, iclass 16, count 0 2006.190.08:19:58.66#ibcon#wrote, iclass 16, count 0 2006.190.08:19:58.66#ibcon#about to read 3, iclass 16, count 0 2006.190.08:19:58.70#ibcon#read 3, iclass 16, count 0 2006.190.08:19:58.70#ibcon#about to read 4, iclass 16, count 0 2006.190.08:19:58.70#ibcon#read 4, iclass 16, count 0 2006.190.08:19:58.70#ibcon#about to read 5, iclass 16, count 0 2006.190.08:19:58.70#ibcon#read 5, iclass 16, count 0 2006.190.08:19:58.70#ibcon#about to read 6, iclass 16, count 0 2006.190.08:19:58.70#ibcon#read 6, iclass 16, count 0 2006.190.08:19:58.70#ibcon#end of sib2, iclass 16, count 0 2006.190.08:19:58.70#ibcon#*after write, iclass 16, count 0 2006.190.08:19:58.70#ibcon#*before return 0, iclass 16, count 0 2006.190.08:19:58.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:19:58.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:19:58.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:19:58.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:19:58.70$vc4f8/va=3,6 2006.190.08:19:58.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.08:19:58.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.08:19:58.70#ibcon#ireg 11 cls_cnt 2 2006.190.08:19:58.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:19:58.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:19:58.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:19:58.76#ibcon#enter wrdev, iclass 18, count 2 2006.190.08:19:58.76#ibcon#first serial, iclass 18, count 2 2006.190.08:19:58.76#ibcon#enter sib2, iclass 18, count 2 2006.190.08:19:58.76#ibcon#flushed, iclass 18, count 2 2006.190.08:19:58.76#ibcon#about to write, iclass 18, count 2 2006.190.08:19:58.76#ibcon#wrote, iclass 18, count 2 2006.190.08:19:58.76#ibcon#about to read 3, iclass 18, count 2 2006.190.08:19:58.78#ibcon#read 3, iclass 18, count 2 2006.190.08:19:58.78#ibcon#about to read 4, iclass 18, count 2 2006.190.08:19:58.78#ibcon#read 4, iclass 18, count 2 2006.190.08:19:58.78#ibcon#about to read 5, iclass 18, count 2 2006.190.08:19:58.78#ibcon#read 5, iclass 18, count 2 2006.190.08:19:58.78#ibcon#about to read 6, iclass 18, count 2 2006.190.08:19:58.78#ibcon#read 6, iclass 18, count 2 2006.190.08:19:58.78#ibcon#end of sib2, iclass 18, count 2 2006.190.08:19:58.78#ibcon#*mode == 0, iclass 18, count 2 2006.190.08:19:58.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.08:19:58.78#ibcon#[25=AT03-06\r\n] 2006.190.08:19:58.78#ibcon#*before write, iclass 18, count 2 2006.190.08:19:58.78#ibcon#enter sib2, iclass 18, count 2 2006.190.08:19:58.78#ibcon#flushed, iclass 18, count 2 2006.190.08:19:58.78#ibcon#about to write, iclass 18, count 2 2006.190.08:19:58.78#ibcon#wrote, iclass 18, count 2 2006.190.08:19:58.78#ibcon#about to read 3, iclass 18, count 2 2006.190.08:19:58.81#ibcon#read 3, iclass 18, count 2 2006.190.08:19:58.81#ibcon#about to read 4, iclass 18, count 2 2006.190.08:19:58.81#ibcon#read 4, iclass 18, count 2 2006.190.08:19:58.81#ibcon#about to read 5, iclass 18, count 2 2006.190.08:19:58.81#ibcon#read 5, iclass 18, count 2 2006.190.08:19:58.81#ibcon#about to read 6, iclass 18, count 2 2006.190.08:19:58.81#ibcon#read 6, iclass 18, count 2 2006.190.08:19:58.81#ibcon#end of sib2, iclass 18, count 2 2006.190.08:19:58.81#ibcon#*after write, iclass 18, count 2 2006.190.08:19:58.81#ibcon#*before return 0, iclass 18, count 2 2006.190.08:19:58.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:19:58.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:19:58.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.08:19:58.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:19:58.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:19:58.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:19:58.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:19:58.93#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:19:58.93#ibcon#first serial, iclass 18, count 0 2006.190.08:19:58.93#ibcon#enter sib2, iclass 18, count 0 2006.190.08:19:58.93#ibcon#flushed, iclass 18, count 0 2006.190.08:19:58.93#ibcon#about to write, iclass 18, count 0 2006.190.08:19:58.93#ibcon#wrote, iclass 18, count 0 2006.190.08:19:58.93#ibcon#about to read 3, iclass 18, count 0 2006.190.08:19:58.95#ibcon#read 3, iclass 18, count 0 2006.190.08:19:58.95#ibcon#about to read 4, iclass 18, count 0 2006.190.08:19:58.95#ibcon#read 4, iclass 18, count 0 2006.190.08:19:58.95#ibcon#about to read 5, iclass 18, count 0 2006.190.08:19:58.95#ibcon#read 5, iclass 18, count 0 2006.190.08:19:58.95#ibcon#about to read 6, iclass 18, count 0 2006.190.08:19:58.95#ibcon#read 6, iclass 18, count 0 2006.190.08:19:58.95#ibcon#end of sib2, iclass 18, count 0 2006.190.08:19:58.95#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:19:58.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:19:58.95#ibcon#[25=USB\r\n] 2006.190.08:19:58.95#ibcon#*before write, iclass 18, count 0 2006.190.08:19:58.95#ibcon#enter sib2, iclass 18, count 0 2006.190.08:19:58.95#ibcon#flushed, iclass 18, count 0 2006.190.08:19:58.95#ibcon#about to write, iclass 18, count 0 2006.190.08:19:58.95#ibcon#wrote, iclass 18, count 0 2006.190.08:19:58.95#ibcon#about to read 3, iclass 18, count 0 2006.190.08:19:58.98#ibcon#read 3, iclass 18, count 0 2006.190.08:19:58.98#ibcon#about to read 4, iclass 18, count 0 2006.190.08:19:58.98#ibcon#read 4, iclass 18, count 0 2006.190.08:19:58.98#ibcon#about to read 5, iclass 18, count 0 2006.190.08:19:58.98#ibcon#read 5, iclass 18, count 0 2006.190.08:19:58.98#ibcon#about to read 6, iclass 18, count 0 2006.190.08:19:58.98#ibcon#read 6, iclass 18, count 0 2006.190.08:19:58.98#ibcon#end of sib2, iclass 18, count 0 2006.190.08:19:58.98#ibcon#*after write, iclass 18, count 0 2006.190.08:19:58.98#ibcon#*before return 0, iclass 18, count 0 2006.190.08:19:58.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:19:58.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:19:58.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:19:58.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:19:58.98$vc4f8/valo=4,832.99 2006.190.08:19:58.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.08:19:58.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.08:19:58.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:19:58.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:19:58.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:19:58.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:19:58.98#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:19:58.98#ibcon#first serial, iclass 20, count 0 2006.190.08:19:58.98#ibcon#enter sib2, iclass 20, count 0 2006.190.08:19:58.98#ibcon#flushed, iclass 20, count 0 2006.190.08:19:58.98#ibcon#about to write, iclass 20, count 0 2006.190.08:19:58.98#ibcon#wrote, iclass 20, count 0 2006.190.08:19:58.98#ibcon#about to read 3, iclass 20, count 0 2006.190.08:19:59.00#ibcon#read 3, iclass 20, count 0 2006.190.08:19:59.00#ibcon#about to read 4, iclass 20, count 0 2006.190.08:19:59.00#ibcon#read 4, iclass 20, count 0 2006.190.08:19:59.00#ibcon#about to read 5, iclass 20, count 0 2006.190.08:19:59.00#ibcon#read 5, iclass 20, count 0 2006.190.08:19:59.00#ibcon#about to read 6, iclass 20, count 0 2006.190.08:19:59.00#ibcon#read 6, iclass 20, count 0 2006.190.08:19:59.00#ibcon#end of sib2, iclass 20, count 0 2006.190.08:19:59.00#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:19:59.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:19:59.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:19:59.00#ibcon#*before write, iclass 20, count 0 2006.190.08:19:59.00#ibcon#enter sib2, iclass 20, count 0 2006.190.08:19:59.00#ibcon#flushed, iclass 20, count 0 2006.190.08:19:59.00#ibcon#about to write, iclass 20, count 0 2006.190.08:19:59.00#ibcon#wrote, iclass 20, count 0 2006.190.08:19:59.00#ibcon#about to read 3, iclass 20, count 0 2006.190.08:19:59.04#ibcon#read 3, iclass 20, count 0 2006.190.08:19:59.04#ibcon#about to read 4, iclass 20, count 0 2006.190.08:19:59.04#ibcon#read 4, iclass 20, count 0 2006.190.08:19:59.04#ibcon#about to read 5, iclass 20, count 0 2006.190.08:19:59.04#ibcon#read 5, iclass 20, count 0 2006.190.08:19:59.04#ibcon#about to read 6, iclass 20, count 0 2006.190.08:19:59.04#ibcon#read 6, iclass 20, count 0 2006.190.08:19:59.04#ibcon#end of sib2, iclass 20, count 0 2006.190.08:19:59.04#ibcon#*after write, iclass 20, count 0 2006.190.08:19:59.04#ibcon#*before return 0, iclass 20, count 0 2006.190.08:19:59.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:19:59.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:19:59.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:19:59.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:19:59.04$vc4f8/va=4,7 2006.190.08:19:59.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.08:19:59.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.08:19:59.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:19:59.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:19:59.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:19:59.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:19:59.10#ibcon#enter wrdev, iclass 22, count 2 2006.190.08:19:59.10#ibcon#first serial, iclass 22, count 2 2006.190.08:19:59.10#ibcon#enter sib2, iclass 22, count 2 2006.190.08:19:59.10#ibcon#flushed, iclass 22, count 2 2006.190.08:19:59.10#ibcon#about to write, iclass 22, count 2 2006.190.08:19:59.10#ibcon#wrote, iclass 22, count 2 2006.190.08:19:59.10#ibcon#about to read 3, iclass 22, count 2 2006.190.08:19:59.12#ibcon#read 3, iclass 22, count 2 2006.190.08:19:59.12#ibcon#about to read 4, iclass 22, count 2 2006.190.08:19:59.12#ibcon#read 4, iclass 22, count 2 2006.190.08:19:59.12#ibcon#about to read 5, iclass 22, count 2 2006.190.08:19:59.12#ibcon#read 5, iclass 22, count 2 2006.190.08:19:59.12#ibcon#about to read 6, iclass 22, count 2 2006.190.08:19:59.12#ibcon#read 6, iclass 22, count 2 2006.190.08:19:59.12#ibcon#end of sib2, iclass 22, count 2 2006.190.08:19:59.12#ibcon#*mode == 0, iclass 22, count 2 2006.190.08:19:59.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.08:19:59.12#ibcon#[25=AT04-07\r\n] 2006.190.08:19:59.12#ibcon#*before write, iclass 22, count 2 2006.190.08:19:59.12#ibcon#enter sib2, iclass 22, count 2 2006.190.08:19:59.12#ibcon#flushed, iclass 22, count 2 2006.190.08:19:59.12#ibcon#about to write, iclass 22, count 2 2006.190.08:19:59.12#ibcon#wrote, iclass 22, count 2 2006.190.08:19:59.12#ibcon#about to read 3, iclass 22, count 2 2006.190.08:19:59.15#ibcon#read 3, iclass 22, count 2 2006.190.08:19:59.15#ibcon#about to read 4, iclass 22, count 2 2006.190.08:19:59.15#ibcon#read 4, iclass 22, count 2 2006.190.08:19:59.15#ibcon#about to read 5, iclass 22, count 2 2006.190.08:19:59.15#ibcon#read 5, iclass 22, count 2 2006.190.08:19:59.15#ibcon#about to read 6, iclass 22, count 2 2006.190.08:19:59.15#ibcon#read 6, iclass 22, count 2 2006.190.08:19:59.15#ibcon#end of sib2, iclass 22, count 2 2006.190.08:19:59.15#ibcon#*after write, iclass 22, count 2 2006.190.08:19:59.15#ibcon#*before return 0, iclass 22, count 2 2006.190.08:19:59.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:19:59.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:19:59.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.08:19:59.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:19:59.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:19:59.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:19:59.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:19:59.27#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:19:59.27#ibcon#first serial, iclass 22, count 0 2006.190.08:19:59.27#ibcon#enter sib2, iclass 22, count 0 2006.190.08:19:59.27#ibcon#flushed, iclass 22, count 0 2006.190.08:19:59.27#ibcon#about to write, iclass 22, count 0 2006.190.08:19:59.27#ibcon#wrote, iclass 22, count 0 2006.190.08:19:59.27#ibcon#about to read 3, iclass 22, count 0 2006.190.08:19:59.29#ibcon#read 3, iclass 22, count 0 2006.190.08:19:59.29#ibcon#about to read 4, iclass 22, count 0 2006.190.08:19:59.29#ibcon#read 4, iclass 22, count 0 2006.190.08:19:59.29#ibcon#about to read 5, iclass 22, count 0 2006.190.08:19:59.29#ibcon#read 5, iclass 22, count 0 2006.190.08:19:59.29#ibcon#about to read 6, iclass 22, count 0 2006.190.08:19:59.29#ibcon#read 6, iclass 22, count 0 2006.190.08:19:59.29#ibcon#end of sib2, iclass 22, count 0 2006.190.08:19:59.29#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:19:59.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:19:59.29#ibcon#[25=USB\r\n] 2006.190.08:19:59.29#ibcon#*before write, iclass 22, count 0 2006.190.08:19:59.29#ibcon#enter sib2, iclass 22, count 0 2006.190.08:19:59.29#ibcon#flushed, iclass 22, count 0 2006.190.08:19:59.29#ibcon#about to write, iclass 22, count 0 2006.190.08:19:59.29#ibcon#wrote, iclass 22, count 0 2006.190.08:19:59.29#ibcon#about to read 3, iclass 22, count 0 2006.190.08:19:59.32#ibcon#read 3, iclass 22, count 0 2006.190.08:19:59.32#ibcon#about to read 4, iclass 22, count 0 2006.190.08:19:59.32#ibcon#read 4, iclass 22, count 0 2006.190.08:19:59.32#ibcon#about to read 5, iclass 22, count 0 2006.190.08:19:59.32#ibcon#read 5, iclass 22, count 0 2006.190.08:19:59.32#ibcon#about to read 6, iclass 22, count 0 2006.190.08:19:59.32#ibcon#read 6, iclass 22, count 0 2006.190.08:19:59.32#ibcon#end of sib2, iclass 22, count 0 2006.190.08:19:59.32#ibcon#*after write, iclass 22, count 0 2006.190.08:19:59.32#ibcon#*before return 0, iclass 22, count 0 2006.190.08:19:59.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:19:59.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:19:59.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:19:59.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:19:59.32$vc4f8/valo=5,652.99 2006.190.08:19:59.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.08:19:59.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.08:19:59.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:19:59.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:19:59.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:19:59.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:19:59.32#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:19:59.32#ibcon#first serial, iclass 24, count 0 2006.190.08:19:59.32#ibcon#enter sib2, iclass 24, count 0 2006.190.08:19:59.32#ibcon#flushed, iclass 24, count 0 2006.190.08:19:59.32#ibcon#about to write, iclass 24, count 0 2006.190.08:19:59.32#ibcon#wrote, iclass 24, count 0 2006.190.08:19:59.32#ibcon#about to read 3, iclass 24, count 0 2006.190.08:19:59.34#ibcon#read 3, iclass 24, count 0 2006.190.08:19:59.34#ibcon#about to read 4, iclass 24, count 0 2006.190.08:19:59.34#ibcon#read 4, iclass 24, count 0 2006.190.08:19:59.34#ibcon#about to read 5, iclass 24, count 0 2006.190.08:19:59.34#ibcon#read 5, iclass 24, count 0 2006.190.08:19:59.34#ibcon#about to read 6, iclass 24, count 0 2006.190.08:19:59.34#ibcon#read 6, iclass 24, count 0 2006.190.08:19:59.34#ibcon#end of sib2, iclass 24, count 0 2006.190.08:19:59.34#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:19:59.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:19:59.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:19:59.34#ibcon#*before write, iclass 24, count 0 2006.190.08:19:59.34#ibcon#enter sib2, iclass 24, count 0 2006.190.08:19:59.34#ibcon#flushed, iclass 24, count 0 2006.190.08:19:59.34#ibcon#about to write, iclass 24, count 0 2006.190.08:19:59.34#ibcon#wrote, iclass 24, count 0 2006.190.08:19:59.34#ibcon#about to read 3, iclass 24, count 0 2006.190.08:19:59.38#ibcon#read 3, iclass 24, count 0 2006.190.08:19:59.38#ibcon#about to read 4, iclass 24, count 0 2006.190.08:19:59.38#ibcon#read 4, iclass 24, count 0 2006.190.08:19:59.38#ibcon#about to read 5, iclass 24, count 0 2006.190.08:19:59.38#ibcon#read 5, iclass 24, count 0 2006.190.08:19:59.38#ibcon#about to read 6, iclass 24, count 0 2006.190.08:19:59.38#ibcon#read 6, iclass 24, count 0 2006.190.08:19:59.38#ibcon#end of sib2, iclass 24, count 0 2006.190.08:19:59.38#ibcon#*after write, iclass 24, count 0 2006.190.08:19:59.38#ibcon#*before return 0, iclass 24, count 0 2006.190.08:19:59.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:19:59.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:19:59.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:19:59.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:19:59.38$vc4f8/va=5,7 2006.190.08:19:59.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.08:19:59.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.08:19:59.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:19:59.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:19:59.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:19:59.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:19:59.44#ibcon#enter wrdev, iclass 26, count 2 2006.190.08:19:59.44#ibcon#first serial, iclass 26, count 2 2006.190.08:19:59.44#ibcon#enter sib2, iclass 26, count 2 2006.190.08:19:59.44#ibcon#flushed, iclass 26, count 2 2006.190.08:19:59.44#ibcon#about to write, iclass 26, count 2 2006.190.08:19:59.44#ibcon#wrote, iclass 26, count 2 2006.190.08:19:59.44#ibcon#about to read 3, iclass 26, count 2 2006.190.08:19:59.46#ibcon#read 3, iclass 26, count 2 2006.190.08:19:59.46#ibcon#about to read 4, iclass 26, count 2 2006.190.08:19:59.46#ibcon#read 4, iclass 26, count 2 2006.190.08:19:59.46#ibcon#about to read 5, iclass 26, count 2 2006.190.08:19:59.46#ibcon#read 5, iclass 26, count 2 2006.190.08:19:59.46#ibcon#about to read 6, iclass 26, count 2 2006.190.08:19:59.46#ibcon#read 6, iclass 26, count 2 2006.190.08:19:59.46#ibcon#end of sib2, iclass 26, count 2 2006.190.08:19:59.46#ibcon#*mode == 0, iclass 26, count 2 2006.190.08:19:59.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.08:19:59.46#ibcon#[25=AT05-07\r\n] 2006.190.08:19:59.46#ibcon#*before write, iclass 26, count 2 2006.190.08:19:59.46#ibcon#enter sib2, iclass 26, count 2 2006.190.08:19:59.46#ibcon#flushed, iclass 26, count 2 2006.190.08:19:59.46#ibcon#about to write, iclass 26, count 2 2006.190.08:19:59.46#ibcon#wrote, iclass 26, count 2 2006.190.08:19:59.46#ibcon#about to read 3, iclass 26, count 2 2006.190.08:19:59.49#ibcon#read 3, iclass 26, count 2 2006.190.08:19:59.49#ibcon#about to read 4, iclass 26, count 2 2006.190.08:19:59.49#ibcon#read 4, iclass 26, count 2 2006.190.08:19:59.49#ibcon#about to read 5, iclass 26, count 2 2006.190.08:19:59.49#ibcon#read 5, iclass 26, count 2 2006.190.08:19:59.49#ibcon#about to read 6, iclass 26, count 2 2006.190.08:19:59.49#ibcon#read 6, iclass 26, count 2 2006.190.08:19:59.49#ibcon#end of sib2, iclass 26, count 2 2006.190.08:19:59.49#ibcon#*after write, iclass 26, count 2 2006.190.08:19:59.49#ibcon#*before return 0, iclass 26, count 2 2006.190.08:19:59.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:19:59.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:19:59.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.08:19:59.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:19:59.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:19:59.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:19:59.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:19:59.61#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:19:59.61#ibcon#first serial, iclass 26, count 0 2006.190.08:19:59.61#ibcon#enter sib2, iclass 26, count 0 2006.190.08:19:59.61#ibcon#flushed, iclass 26, count 0 2006.190.08:19:59.61#ibcon#about to write, iclass 26, count 0 2006.190.08:19:59.61#ibcon#wrote, iclass 26, count 0 2006.190.08:19:59.61#ibcon#about to read 3, iclass 26, count 0 2006.190.08:19:59.63#ibcon#read 3, iclass 26, count 0 2006.190.08:19:59.63#ibcon#about to read 4, iclass 26, count 0 2006.190.08:19:59.63#ibcon#read 4, iclass 26, count 0 2006.190.08:19:59.63#ibcon#about to read 5, iclass 26, count 0 2006.190.08:19:59.63#ibcon#read 5, iclass 26, count 0 2006.190.08:19:59.63#ibcon#about to read 6, iclass 26, count 0 2006.190.08:19:59.63#ibcon#read 6, iclass 26, count 0 2006.190.08:19:59.63#ibcon#end of sib2, iclass 26, count 0 2006.190.08:19:59.63#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:19:59.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:19:59.63#ibcon#[25=USB\r\n] 2006.190.08:19:59.63#ibcon#*before write, iclass 26, count 0 2006.190.08:19:59.63#ibcon#enter sib2, iclass 26, count 0 2006.190.08:19:59.63#ibcon#flushed, iclass 26, count 0 2006.190.08:19:59.63#ibcon#about to write, iclass 26, count 0 2006.190.08:19:59.63#ibcon#wrote, iclass 26, count 0 2006.190.08:19:59.63#ibcon#about to read 3, iclass 26, count 0 2006.190.08:19:59.66#ibcon#read 3, iclass 26, count 0 2006.190.08:19:59.66#ibcon#about to read 4, iclass 26, count 0 2006.190.08:19:59.66#ibcon#read 4, iclass 26, count 0 2006.190.08:19:59.66#ibcon#about to read 5, iclass 26, count 0 2006.190.08:19:59.66#ibcon#read 5, iclass 26, count 0 2006.190.08:19:59.66#ibcon#about to read 6, iclass 26, count 0 2006.190.08:19:59.66#ibcon#read 6, iclass 26, count 0 2006.190.08:19:59.66#ibcon#end of sib2, iclass 26, count 0 2006.190.08:19:59.66#ibcon#*after write, iclass 26, count 0 2006.190.08:19:59.66#ibcon#*before return 0, iclass 26, count 0 2006.190.08:19:59.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:19:59.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:19:59.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:19:59.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:19:59.66$vc4f8/valo=6,772.99 2006.190.08:19:59.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.08:19:59.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.08:19:59.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:19:59.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:19:59.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:19:59.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:19:59.66#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:19:59.66#ibcon#first serial, iclass 28, count 0 2006.190.08:19:59.66#ibcon#enter sib2, iclass 28, count 0 2006.190.08:19:59.66#ibcon#flushed, iclass 28, count 0 2006.190.08:19:59.66#ibcon#about to write, iclass 28, count 0 2006.190.08:19:59.66#ibcon#wrote, iclass 28, count 0 2006.190.08:19:59.66#ibcon#about to read 3, iclass 28, count 0 2006.190.08:19:59.68#ibcon#read 3, iclass 28, count 0 2006.190.08:19:59.68#ibcon#about to read 4, iclass 28, count 0 2006.190.08:19:59.68#ibcon#read 4, iclass 28, count 0 2006.190.08:19:59.68#ibcon#about to read 5, iclass 28, count 0 2006.190.08:19:59.68#ibcon#read 5, iclass 28, count 0 2006.190.08:19:59.68#ibcon#about to read 6, iclass 28, count 0 2006.190.08:19:59.68#ibcon#read 6, iclass 28, count 0 2006.190.08:19:59.68#ibcon#end of sib2, iclass 28, count 0 2006.190.08:19:59.68#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:19:59.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:19:59.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:19:59.68#ibcon#*before write, iclass 28, count 0 2006.190.08:19:59.68#ibcon#enter sib2, iclass 28, count 0 2006.190.08:19:59.68#ibcon#flushed, iclass 28, count 0 2006.190.08:19:59.68#ibcon#about to write, iclass 28, count 0 2006.190.08:19:59.68#ibcon#wrote, iclass 28, count 0 2006.190.08:19:59.68#ibcon#about to read 3, iclass 28, count 0 2006.190.08:19:59.72#ibcon#read 3, iclass 28, count 0 2006.190.08:19:59.72#ibcon#about to read 4, iclass 28, count 0 2006.190.08:19:59.72#ibcon#read 4, iclass 28, count 0 2006.190.08:19:59.72#ibcon#about to read 5, iclass 28, count 0 2006.190.08:19:59.72#ibcon#read 5, iclass 28, count 0 2006.190.08:19:59.72#ibcon#about to read 6, iclass 28, count 0 2006.190.08:19:59.72#ibcon#read 6, iclass 28, count 0 2006.190.08:19:59.72#ibcon#end of sib2, iclass 28, count 0 2006.190.08:19:59.72#ibcon#*after write, iclass 28, count 0 2006.190.08:19:59.72#ibcon#*before return 0, iclass 28, count 0 2006.190.08:19:59.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:19:59.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:19:59.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:19:59.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:19:59.72$vc4f8/va=6,6 2006.190.08:19:59.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.190.08:19:59.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.190.08:19:59.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:19:59.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:19:59.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:19:59.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:19:59.78#ibcon#enter wrdev, iclass 30, count 2 2006.190.08:19:59.78#ibcon#first serial, iclass 30, count 2 2006.190.08:19:59.78#ibcon#enter sib2, iclass 30, count 2 2006.190.08:19:59.78#ibcon#flushed, iclass 30, count 2 2006.190.08:19:59.78#ibcon#about to write, iclass 30, count 2 2006.190.08:19:59.78#ibcon#wrote, iclass 30, count 2 2006.190.08:19:59.78#ibcon#about to read 3, iclass 30, count 2 2006.190.08:19:59.80#ibcon#read 3, iclass 30, count 2 2006.190.08:19:59.80#ibcon#about to read 4, iclass 30, count 2 2006.190.08:19:59.80#ibcon#read 4, iclass 30, count 2 2006.190.08:19:59.80#ibcon#about to read 5, iclass 30, count 2 2006.190.08:19:59.80#ibcon#read 5, iclass 30, count 2 2006.190.08:19:59.80#ibcon#about to read 6, iclass 30, count 2 2006.190.08:19:59.80#ibcon#read 6, iclass 30, count 2 2006.190.08:19:59.80#ibcon#end of sib2, iclass 30, count 2 2006.190.08:19:59.80#ibcon#*mode == 0, iclass 30, count 2 2006.190.08:19:59.80#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.190.08:19:59.80#ibcon#[25=AT06-06\r\n] 2006.190.08:19:59.80#ibcon#*before write, iclass 30, count 2 2006.190.08:19:59.80#ibcon#enter sib2, iclass 30, count 2 2006.190.08:19:59.80#ibcon#flushed, iclass 30, count 2 2006.190.08:19:59.80#ibcon#about to write, iclass 30, count 2 2006.190.08:19:59.80#ibcon#wrote, iclass 30, count 2 2006.190.08:19:59.80#ibcon#about to read 3, iclass 30, count 2 2006.190.08:19:59.83#ibcon#read 3, iclass 30, count 2 2006.190.08:19:59.83#ibcon#about to read 4, iclass 30, count 2 2006.190.08:19:59.83#ibcon#read 4, iclass 30, count 2 2006.190.08:19:59.83#ibcon#about to read 5, iclass 30, count 2 2006.190.08:19:59.83#ibcon#read 5, iclass 30, count 2 2006.190.08:19:59.83#ibcon#about to read 6, iclass 30, count 2 2006.190.08:19:59.83#ibcon#read 6, iclass 30, count 2 2006.190.08:19:59.83#ibcon#end of sib2, iclass 30, count 2 2006.190.08:19:59.83#ibcon#*after write, iclass 30, count 2 2006.190.08:19:59.83#ibcon#*before return 0, iclass 30, count 2 2006.190.08:19:59.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:19:59.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.190.08:19:59.83#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.190.08:19:59.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:19:59.83#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:19:59.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:19:59.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:19:59.95#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:19:59.95#ibcon#first serial, iclass 30, count 0 2006.190.08:19:59.95#ibcon#enter sib2, iclass 30, count 0 2006.190.08:19:59.95#ibcon#flushed, iclass 30, count 0 2006.190.08:19:59.95#ibcon#about to write, iclass 30, count 0 2006.190.08:19:59.95#ibcon#wrote, iclass 30, count 0 2006.190.08:19:59.95#ibcon#about to read 3, iclass 30, count 0 2006.190.08:19:59.97#ibcon#read 3, iclass 30, count 0 2006.190.08:19:59.97#ibcon#about to read 4, iclass 30, count 0 2006.190.08:19:59.97#ibcon#read 4, iclass 30, count 0 2006.190.08:19:59.97#ibcon#about to read 5, iclass 30, count 0 2006.190.08:19:59.97#ibcon#read 5, iclass 30, count 0 2006.190.08:19:59.97#ibcon#about to read 6, iclass 30, count 0 2006.190.08:19:59.97#ibcon#read 6, iclass 30, count 0 2006.190.08:19:59.97#ibcon#end of sib2, iclass 30, count 0 2006.190.08:19:59.97#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:19:59.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:19:59.97#ibcon#[25=USB\r\n] 2006.190.08:19:59.97#ibcon#*before write, iclass 30, count 0 2006.190.08:19:59.97#ibcon#enter sib2, iclass 30, count 0 2006.190.08:19:59.97#ibcon#flushed, iclass 30, count 0 2006.190.08:19:59.97#ibcon#about to write, iclass 30, count 0 2006.190.08:19:59.97#ibcon#wrote, iclass 30, count 0 2006.190.08:19:59.97#ibcon#about to read 3, iclass 30, count 0 2006.190.08:20:00.00#ibcon#read 3, iclass 30, count 0 2006.190.08:20:00.00#ibcon#about to read 4, iclass 30, count 0 2006.190.08:20:00.00#ibcon#read 4, iclass 30, count 0 2006.190.08:20:00.00#ibcon#about to read 5, iclass 30, count 0 2006.190.08:20:00.00#ibcon#read 5, iclass 30, count 0 2006.190.08:20:00.00#ibcon#about to read 6, iclass 30, count 0 2006.190.08:20:00.00#ibcon#read 6, iclass 30, count 0 2006.190.08:20:00.00#ibcon#end of sib2, iclass 30, count 0 2006.190.08:20:00.00#ibcon#*after write, iclass 30, count 0 2006.190.08:20:00.00#ibcon#*before return 0, iclass 30, count 0 2006.190.08:20:00.00#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:20:00.00#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.190.08:20:00.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:20:00.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:20:00.00$vc4f8/valo=7,832.99 2006.190.08:20:00.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.08:20:00.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.08:20:00.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:00.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:20:00.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:20:00.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:20:00.00#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:20:00.00#ibcon#first serial, iclass 32, count 0 2006.190.08:20:00.00#ibcon#enter sib2, iclass 32, count 0 2006.190.08:20:00.00#ibcon#flushed, iclass 32, count 0 2006.190.08:20:00.00#ibcon#about to write, iclass 32, count 0 2006.190.08:20:00.00#ibcon#wrote, iclass 32, count 0 2006.190.08:20:00.00#ibcon#about to read 3, iclass 32, count 0 2006.190.08:20:00.02#ibcon#read 3, iclass 32, count 0 2006.190.08:20:00.02#ibcon#about to read 4, iclass 32, count 0 2006.190.08:20:00.02#ibcon#read 4, iclass 32, count 0 2006.190.08:20:00.02#ibcon#about to read 5, iclass 32, count 0 2006.190.08:20:00.02#ibcon#read 5, iclass 32, count 0 2006.190.08:20:00.02#ibcon#about to read 6, iclass 32, count 0 2006.190.08:20:00.02#ibcon#read 6, iclass 32, count 0 2006.190.08:20:00.02#ibcon#end of sib2, iclass 32, count 0 2006.190.08:20:00.02#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:20:00.02#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:20:00.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:20:00.02#ibcon#*before write, iclass 32, count 0 2006.190.08:20:00.02#ibcon#enter sib2, iclass 32, count 0 2006.190.08:20:00.02#ibcon#flushed, iclass 32, count 0 2006.190.08:20:00.02#ibcon#about to write, iclass 32, count 0 2006.190.08:20:00.02#ibcon#wrote, iclass 32, count 0 2006.190.08:20:00.02#ibcon#about to read 3, iclass 32, count 0 2006.190.08:20:00.06#ibcon#read 3, iclass 32, count 0 2006.190.08:20:00.06#ibcon#about to read 4, iclass 32, count 0 2006.190.08:20:00.06#ibcon#read 4, iclass 32, count 0 2006.190.08:20:00.06#ibcon#about to read 5, iclass 32, count 0 2006.190.08:20:00.06#ibcon#read 5, iclass 32, count 0 2006.190.08:20:00.06#ibcon#about to read 6, iclass 32, count 0 2006.190.08:20:00.06#ibcon#read 6, iclass 32, count 0 2006.190.08:20:00.06#ibcon#end of sib2, iclass 32, count 0 2006.190.08:20:00.06#ibcon#*after write, iclass 32, count 0 2006.190.08:20:00.06#ibcon#*before return 0, iclass 32, count 0 2006.190.08:20:00.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:20:00.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:20:00.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:20:00.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:20:00.06$vc4f8/va=7,6 2006.190.08:20:00.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.08:20:00.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.08:20:00.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:00.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:20:00.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:20:00.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:20:00.12#ibcon#enter wrdev, iclass 34, count 2 2006.190.08:20:00.12#ibcon#first serial, iclass 34, count 2 2006.190.08:20:00.12#ibcon#enter sib2, iclass 34, count 2 2006.190.08:20:00.12#ibcon#flushed, iclass 34, count 2 2006.190.08:20:00.12#ibcon#about to write, iclass 34, count 2 2006.190.08:20:00.12#ibcon#wrote, iclass 34, count 2 2006.190.08:20:00.12#ibcon#about to read 3, iclass 34, count 2 2006.190.08:20:00.14#ibcon#read 3, iclass 34, count 2 2006.190.08:20:00.14#ibcon#about to read 4, iclass 34, count 2 2006.190.08:20:00.14#ibcon#read 4, iclass 34, count 2 2006.190.08:20:00.14#ibcon#about to read 5, iclass 34, count 2 2006.190.08:20:00.14#ibcon#read 5, iclass 34, count 2 2006.190.08:20:00.14#ibcon#about to read 6, iclass 34, count 2 2006.190.08:20:00.14#ibcon#read 6, iclass 34, count 2 2006.190.08:20:00.14#ibcon#end of sib2, iclass 34, count 2 2006.190.08:20:00.14#ibcon#*mode == 0, iclass 34, count 2 2006.190.08:20:00.14#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.08:20:00.14#ibcon#[25=AT07-06\r\n] 2006.190.08:20:00.14#ibcon#*before write, iclass 34, count 2 2006.190.08:20:00.14#ibcon#enter sib2, iclass 34, count 2 2006.190.08:20:00.14#ibcon#flushed, iclass 34, count 2 2006.190.08:20:00.14#ibcon#about to write, iclass 34, count 2 2006.190.08:20:00.14#ibcon#wrote, iclass 34, count 2 2006.190.08:20:00.14#ibcon#about to read 3, iclass 34, count 2 2006.190.08:20:00.17#ibcon#read 3, iclass 34, count 2 2006.190.08:20:00.17#ibcon#about to read 4, iclass 34, count 2 2006.190.08:20:00.17#ibcon#read 4, iclass 34, count 2 2006.190.08:20:00.17#ibcon#about to read 5, iclass 34, count 2 2006.190.08:20:00.17#ibcon#read 5, iclass 34, count 2 2006.190.08:20:00.17#ibcon#about to read 6, iclass 34, count 2 2006.190.08:20:00.17#ibcon#read 6, iclass 34, count 2 2006.190.08:20:00.17#ibcon#end of sib2, iclass 34, count 2 2006.190.08:20:00.17#ibcon#*after write, iclass 34, count 2 2006.190.08:20:00.17#ibcon#*before return 0, iclass 34, count 2 2006.190.08:20:00.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:20:00.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:20:00.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.08:20:00.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:00.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:20:00.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:20:00.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:20:00.29#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:20:00.29#ibcon#first serial, iclass 34, count 0 2006.190.08:20:00.29#ibcon#enter sib2, iclass 34, count 0 2006.190.08:20:00.29#ibcon#flushed, iclass 34, count 0 2006.190.08:20:00.29#ibcon#about to write, iclass 34, count 0 2006.190.08:20:00.29#ibcon#wrote, iclass 34, count 0 2006.190.08:20:00.29#ibcon#about to read 3, iclass 34, count 0 2006.190.08:20:00.31#ibcon#read 3, iclass 34, count 0 2006.190.08:20:00.31#ibcon#about to read 4, iclass 34, count 0 2006.190.08:20:00.31#ibcon#read 4, iclass 34, count 0 2006.190.08:20:00.31#ibcon#about to read 5, iclass 34, count 0 2006.190.08:20:00.31#ibcon#read 5, iclass 34, count 0 2006.190.08:20:00.31#ibcon#about to read 6, iclass 34, count 0 2006.190.08:20:00.31#ibcon#read 6, iclass 34, count 0 2006.190.08:20:00.31#ibcon#end of sib2, iclass 34, count 0 2006.190.08:20:00.31#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:20:00.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:20:00.31#ibcon#[25=USB\r\n] 2006.190.08:20:00.31#ibcon#*before write, iclass 34, count 0 2006.190.08:20:00.31#ibcon#enter sib2, iclass 34, count 0 2006.190.08:20:00.31#ibcon#flushed, iclass 34, count 0 2006.190.08:20:00.31#ibcon#about to write, iclass 34, count 0 2006.190.08:20:00.31#ibcon#wrote, iclass 34, count 0 2006.190.08:20:00.31#ibcon#about to read 3, iclass 34, count 0 2006.190.08:20:00.34#ibcon#read 3, iclass 34, count 0 2006.190.08:20:00.34#ibcon#about to read 4, iclass 34, count 0 2006.190.08:20:00.34#ibcon#read 4, iclass 34, count 0 2006.190.08:20:00.34#ibcon#about to read 5, iclass 34, count 0 2006.190.08:20:00.34#ibcon#read 5, iclass 34, count 0 2006.190.08:20:00.34#ibcon#about to read 6, iclass 34, count 0 2006.190.08:20:00.34#ibcon#read 6, iclass 34, count 0 2006.190.08:20:00.34#ibcon#end of sib2, iclass 34, count 0 2006.190.08:20:00.34#ibcon#*after write, iclass 34, count 0 2006.190.08:20:00.34#ibcon#*before return 0, iclass 34, count 0 2006.190.08:20:00.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:20:00.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:20:00.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:20:00.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:20:00.34$vc4f8/valo=8,852.99 2006.190.08:20:00.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.08:20:00.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.08:20:00.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:00.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:20:00.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:20:00.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:20:00.34#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:20:00.34#ibcon#first serial, iclass 36, count 0 2006.190.08:20:00.34#ibcon#enter sib2, iclass 36, count 0 2006.190.08:20:00.34#ibcon#flushed, iclass 36, count 0 2006.190.08:20:00.34#ibcon#about to write, iclass 36, count 0 2006.190.08:20:00.34#ibcon#wrote, iclass 36, count 0 2006.190.08:20:00.34#ibcon#about to read 3, iclass 36, count 0 2006.190.08:20:00.36#ibcon#read 3, iclass 36, count 0 2006.190.08:20:00.36#ibcon#about to read 4, iclass 36, count 0 2006.190.08:20:00.36#ibcon#read 4, iclass 36, count 0 2006.190.08:20:00.36#ibcon#about to read 5, iclass 36, count 0 2006.190.08:20:00.36#ibcon#read 5, iclass 36, count 0 2006.190.08:20:00.36#ibcon#about to read 6, iclass 36, count 0 2006.190.08:20:00.36#ibcon#read 6, iclass 36, count 0 2006.190.08:20:00.36#ibcon#end of sib2, iclass 36, count 0 2006.190.08:20:00.36#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:20:00.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:20:00.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:20:00.36#ibcon#*before write, iclass 36, count 0 2006.190.08:20:00.36#ibcon#enter sib2, iclass 36, count 0 2006.190.08:20:00.36#ibcon#flushed, iclass 36, count 0 2006.190.08:20:00.36#ibcon#about to write, iclass 36, count 0 2006.190.08:20:00.36#ibcon#wrote, iclass 36, count 0 2006.190.08:20:00.36#ibcon#about to read 3, iclass 36, count 0 2006.190.08:20:00.40#ibcon#read 3, iclass 36, count 0 2006.190.08:20:00.40#ibcon#about to read 4, iclass 36, count 0 2006.190.08:20:00.40#ibcon#read 4, iclass 36, count 0 2006.190.08:20:00.40#ibcon#about to read 5, iclass 36, count 0 2006.190.08:20:00.40#ibcon#read 5, iclass 36, count 0 2006.190.08:20:00.40#ibcon#about to read 6, iclass 36, count 0 2006.190.08:20:00.40#ibcon#read 6, iclass 36, count 0 2006.190.08:20:00.40#ibcon#end of sib2, iclass 36, count 0 2006.190.08:20:00.40#ibcon#*after write, iclass 36, count 0 2006.190.08:20:00.40#ibcon#*before return 0, iclass 36, count 0 2006.190.08:20:00.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:20:00.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:20:00.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:20:00.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:20:00.40$vc4f8/va=8,6 2006.190.08:20:00.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.08:20:00.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.08:20:00.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:00.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:20:00.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:20:00.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:20:00.46#ibcon#enter wrdev, iclass 38, count 2 2006.190.08:20:00.46#ibcon#first serial, iclass 38, count 2 2006.190.08:20:00.46#ibcon#enter sib2, iclass 38, count 2 2006.190.08:20:00.46#ibcon#flushed, iclass 38, count 2 2006.190.08:20:00.46#ibcon#about to write, iclass 38, count 2 2006.190.08:20:00.46#ibcon#wrote, iclass 38, count 2 2006.190.08:20:00.46#ibcon#about to read 3, iclass 38, count 2 2006.190.08:20:00.48#ibcon#read 3, iclass 38, count 2 2006.190.08:20:00.48#ibcon#about to read 4, iclass 38, count 2 2006.190.08:20:00.48#ibcon#read 4, iclass 38, count 2 2006.190.08:20:00.48#ibcon#about to read 5, iclass 38, count 2 2006.190.08:20:00.48#ibcon#read 5, iclass 38, count 2 2006.190.08:20:00.48#ibcon#about to read 6, iclass 38, count 2 2006.190.08:20:00.48#ibcon#read 6, iclass 38, count 2 2006.190.08:20:00.48#ibcon#end of sib2, iclass 38, count 2 2006.190.08:20:00.48#ibcon#*mode == 0, iclass 38, count 2 2006.190.08:20:00.48#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.08:20:00.48#ibcon#[25=AT08-06\r\n] 2006.190.08:20:00.48#ibcon#*before write, iclass 38, count 2 2006.190.08:20:00.48#ibcon#enter sib2, iclass 38, count 2 2006.190.08:20:00.48#ibcon#flushed, iclass 38, count 2 2006.190.08:20:00.48#ibcon#about to write, iclass 38, count 2 2006.190.08:20:00.48#ibcon#wrote, iclass 38, count 2 2006.190.08:20:00.48#ibcon#about to read 3, iclass 38, count 2 2006.190.08:20:00.51#ibcon#read 3, iclass 38, count 2 2006.190.08:20:00.51#ibcon#about to read 4, iclass 38, count 2 2006.190.08:20:00.51#ibcon#read 4, iclass 38, count 2 2006.190.08:20:00.51#ibcon#about to read 5, iclass 38, count 2 2006.190.08:20:00.51#ibcon#read 5, iclass 38, count 2 2006.190.08:20:00.51#ibcon#about to read 6, iclass 38, count 2 2006.190.08:20:00.51#ibcon#read 6, iclass 38, count 2 2006.190.08:20:00.51#ibcon#end of sib2, iclass 38, count 2 2006.190.08:20:00.51#ibcon#*after write, iclass 38, count 2 2006.190.08:20:00.51#ibcon#*before return 0, iclass 38, count 2 2006.190.08:20:00.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:20:00.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:20:00.51#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.08:20:00.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:00.51#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:20:00.63#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:20:00.63#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:20:00.63#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:20:00.63#ibcon#first serial, iclass 38, count 0 2006.190.08:20:00.63#ibcon#enter sib2, iclass 38, count 0 2006.190.08:20:00.63#ibcon#flushed, iclass 38, count 0 2006.190.08:20:00.63#ibcon#about to write, iclass 38, count 0 2006.190.08:20:00.63#ibcon#wrote, iclass 38, count 0 2006.190.08:20:00.63#ibcon#about to read 3, iclass 38, count 0 2006.190.08:20:00.65#ibcon#read 3, iclass 38, count 0 2006.190.08:20:00.65#ibcon#about to read 4, iclass 38, count 0 2006.190.08:20:00.65#ibcon#read 4, iclass 38, count 0 2006.190.08:20:00.65#ibcon#about to read 5, iclass 38, count 0 2006.190.08:20:00.65#ibcon#read 5, iclass 38, count 0 2006.190.08:20:00.65#ibcon#about to read 6, iclass 38, count 0 2006.190.08:20:00.65#ibcon#read 6, iclass 38, count 0 2006.190.08:20:00.65#ibcon#end of sib2, iclass 38, count 0 2006.190.08:20:00.65#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:20:00.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:20:00.65#ibcon#[25=USB\r\n] 2006.190.08:20:00.65#ibcon#*before write, iclass 38, count 0 2006.190.08:20:00.65#ibcon#enter sib2, iclass 38, count 0 2006.190.08:20:00.65#ibcon#flushed, iclass 38, count 0 2006.190.08:20:00.65#ibcon#about to write, iclass 38, count 0 2006.190.08:20:00.65#ibcon#wrote, iclass 38, count 0 2006.190.08:20:00.65#ibcon#about to read 3, iclass 38, count 0 2006.190.08:20:00.68#ibcon#read 3, iclass 38, count 0 2006.190.08:20:00.68#ibcon#about to read 4, iclass 38, count 0 2006.190.08:20:00.68#ibcon#read 4, iclass 38, count 0 2006.190.08:20:00.68#ibcon#about to read 5, iclass 38, count 0 2006.190.08:20:00.68#ibcon#read 5, iclass 38, count 0 2006.190.08:20:00.68#ibcon#about to read 6, iclass 38, count 0 2006.190.08:20:00.68#ibcon#read 6, iclass 38, count 0 2006.190.08:20:00.68#ibcon#end of sib2, iclass 38, count 0 2006.190.08:20:00.68#ibcon#*after write, iclass 38, count 0 2006.190.08:20:00.68#ibcon#*before return 0, iclass 38, count 0 2006.190.08:20:00.68#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:20:00.68#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:20:00.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:20:00.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:20:00.68$vc4f8/vblo=1,632.99 2006.190.08:20:00.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.08:20:00.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.08:20:00.68#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:00.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:20:00.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:20:00.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:20:00.68#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:20:00.68#ibcon#first serial, iclass 40, count 0 2006.190.08:20:00.68#ibcon#enter sib2, iclass 40, count 0 2006.190.08:20:00.68#ibcon#flushed, iclass 40, count 0 2006.190.08:20:00.68#ibcon#about to write, iclass 40, count 0 2006.190.08:20:00.68#ibcon#wrote, iclass 40, count 0 2006.190.08:20:00.68#ibcon#about to read 3, iclass 40, count 0 2006.190.08:20:00.70#ibcon#read 3, iclass 40, count 0 2006.190.08:20:00.70#ibcon#about to read 4, iclass 40, count 0 2006.190.08:20:00.70#ibcon#read 4, iclass 40, count 0 2006.190.08:20:00.70#ibcon#about to read 5, iclass 40, count 0 2006.190.08:20:00.70#ibcon#read 5, iclass 40, count 0 2006.190.08:20:00.70#ibcon#about to read 6, iclass 40, count 0 2006.190.08:20:00.70#ibcon#read 6, iclass 40, count 0 2006.190.08:20:00.70#ibcon#end of sib2, iclass 40, count 0 2006.190.08:20:00.70#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:20:00.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:20:00.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:20:00.70#ibcon#*before write, iclass 40, count 0 2006.190.08:20:00.70#ibcon#enter sib2, iclass 40, count 0 2006.190.08:20:00.70#ibcon#flushed, iclass 40, count 0 2006.190.08:20:00.70#ibcon#about to write, iclass 40, count 0 2006.190.08:20:00.70#ibcon#wrote, iclass 40, count 0 2006.190.08:20:00.70#ibcon#about to read 3, iclass 40, count 0 2006.190.08:20:00.74#ibcon#read 3, iclass 40, count 0 2006.190.08:20:00.74#ibcon#about to read 4, iclass 40, count 0 2006.190.08:20:00.74#ibcon#read 4, iclass 40, count 0 2006.190.08:20:00.74#ibcon#about to read 5, iclass 40, count 0 2006.190.08:20:00.74#ibcon#read 5, iclass 40, count 0 2006.190.08:20:00.74#ibcon#about to read 6, iclass 40, count 0 2006.190.08:20:00.74#ibcon#read 6, iclass 40, count 0 2006.190.08:20:00.74#ibcon#end of sib2, iclass 40, count 0 2006.190.08:20:00.74#ibcon#*after write, iclass 40, count 0 2006.190.08:20:00.74#ibcon#*before return 0, iclass 40, count 0 2006.190.08:20:00.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:20:00.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:20:00.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:20:00.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:20:00.74$vc4f8/vb=1,4 2006.190.08:20:00.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.08:20:00.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.08:20:00.74#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:00.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:20:00.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:20:00.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:20:00.74#ibcon#enter wrdev, iclass 4, count 2 2006.190.08:20:00.74#ibcon#first serial, iclass 4, count 2 2006.190.08:20:00.74#ibcon#enter sib2, iclass 4, count 2 2006.190.08:20:00.74#ibcon#flushed, iclass 4, count 2 2006.190.08:20:00.74#ibcon#about to write, iclass 4, count 2 2006.190.08:20:00.74#ibcon#wrote, iclass 4, count 2 2006.190.08:20:00.74#ibcon#about to read 3, iclass 4, count 2 2006.190.08:20:00.76#ibcon#read 3, iclass 4, count 2 2006.190.08:20:00.76#ibcon#about to read 4, iclass 4, count 2 2006.190.08:20:00.76#ibcon#read 4, iclass 4, count 2 2006.190.08:20:00.76#ibcon#about to read 5, iclass 4, count 2 2006.190.08:20:00.76#ibcon#read 5, iclass 4, count 2 2006.190.08:20:00.76#ibcon#about to read 6, iclass 4, count 2 2006.190.08:20:00.76#ibcon#read 6, iclass 4, count 2 2006.190.08:20:00.76#ibcon#end of sib2, iclass 4, count 2 2006.190.08:20:00.76#ibcon#*mode == 0, iclass 4, count 2 2006.190.08:20:00.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.08:20:00.76#ibcon#[27=AT01-04\r\n] 2006.190.08:20:00.76#ibcon#*before write, iclass 4, count 2 2006.190.08:20:00.76#ibcon#enter sib2, iclass 4, count 2 2006.190.08:20:00.76#ibcon#flushed, iclass 4, count 2 2006.190.08:20:00.76#ibcon#about to write, iclass 4, count 2 2006.190.08:20:00.76#ibcon#wrote, iclass 4, count 2 2006.190.08:20:00.76#ibcon#about to read 3, iclass 4, count 2 2006.190.08:20:00.79#ibcon#read 3, iclass 4, count 2 2006.190.08:20:00.79#ibcon#about to read 4, iclass 4, count 2 2006.190.08:20:00.79#ibcon#read 4, iclass 4, count 2 2006.190.08:20:00.79#ibcon#about to read 5, iclass 4, count 2 2006.190.08:20:00.79#ibcon#read 5, iclass 4, count 2 2006.190.08:20:00.79#ibcon#about to read 6, iclass 4, count 2 2006.190.08:20:00.79#ibcon#read 6, iclass 4, count 2 2006.190.08:20:00.79#ibcon#end of sib2, iclass 4, count 2 2006.190.08:20:00.79#ibcon#*after write, iclass 4, count 2 2006.190.08:20:00.79#ibcon#*before return 0, iclass 4, count 2 2006.190.08:20:00.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:20:00.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:20:00.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.08:20:00.79#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:00.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:20:00.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:20:00.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:20:00.91#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:20:00.91#ibcon#first serial, iclass 4, count 0 2006.190.08:20:00.91#ibcon#enter sib2, iclass 4, count 0 2006.190.08:20:00.91#ibcon#flushed, iclass 4, count 0 2006.190.08:20:00.91#ibcon#about to write, iclass 4, count 0 2006.190.08:20:00.91#ibcon#wrote, iclass 4, count 0 2006.190.08:20:00.91#ibcon#about to read 3, iclass 4, count 0 2006.190.08:20:00.93#ibcon#read 3, iclass 4, count 0 2006.190.08:20:00.93#ibcon#about to read 4, iclass 4, count 0 2006.190.08:20:00.93#ibcon#read 4, iclass 4, count 0 2006.190.08:20:00.93#ibcon#about to read 5, iclass 4, count 0 2006.190.08:20:00.93#ibcon#read 5, iclass 4, count 0 2006.190.08:20:00.93#ibcon#about to read 6, iclass 4, count 0 2006.190.08:20:00.93#ibcon#read 6, iclass 4, count 0 2006.190.08:20:00.93#ibcon#end of sib2, iclass 4, count 0 2006.190.08:20:00.93#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:20:00.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:20:00.93#ibcon#[27=USB\r\n] 2006.190.08:20:00.93#ibcon#*before write, iclass 4, count 0 2006.190.08:20:00.93#ibcon#enter sib2, iclass 4, count 0 2006.190.08:20:00.93#ibcon#flushed, iclass 4, count 0 2006.190.08:20:00.93#ibcon#about to write, iclass 4, count 0 2006.190.08:20:00.93#ibcon#wrote, iclass 4, count 0 2006.190.08:20:00.93#ibcon#about to read 3, iclass 4, count 0 2006.190.08:20:00.96#ibcon#read 3, iclass 4, count 0 2006.190.08:20:00.96#ibcon#about to read 4, iclass 4, count 0 2006.190.08:20:00.96#ibcon#read 4, iclass 4, count 0 2006.190.08:20:00.96#ibcon#about to read 5, iclass 4, count 0 2006.190.08:20:00.96#ibcon#read 5, iclass 4, count 0 2006.190.08:20:00.96#ibcon#about to read 6, iclass 4, count 0 2006.190.08:20:00.96#ibcon#read 6, iclass 4, count 0 2006.190.08:20:00.96#ibcon#end of sib2, iclass 4, count 0 2006.190.08:20:00.96#ibcon#*after write, iclass 4, count 0 2006.190.08:20:00.96#ibcon#*before return 0, iclass 4, count 0 2006.190.08:20:00.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:20:00.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:20:00.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:20:00.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:20:00.96$vc4f8/vblo=2,640.99 2006.190.08:20:00.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:20:00.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:20:00.96#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:00.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:20:00.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:20:00.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:20:00.96#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:20:00.96#ibcon#first serial, iclass 6, count 0 2006.190.08:20:00.96#ibcon#enter sib2, iclass 6, count 0 2006.190.08:20:00.96#ibcon#flushed, iclass 6, count 0 2006.190.08:20:00.96#ibcon#about to write, iclass 6, count 0 2006.190.08:20:00.96#ibcon#wrote, iclass 6, count 0 2006.190.08:20:00.96#ibcon#about to read 3, iclass 6, count 0 2006.190.08:20:00.98#ibcon#read 3, iclass 6, count 0 2006.190.08:20:00.98#ibcon#about to read 4, iclass 6, count 0 2006.190.08:20:00.98#ibcon#read 4, iclass 6, count 0 2006.190.08:20:00.98#ibcon#about to read 5, iclass 6, count 0 2006.190.08:20:00.98#ibcon#read 5, iclass 6, count 0 2006.190.08:20:00.98#ibcon#about to read 6, iclass 6, count 0 2006.190.08:20:00.98#ibcon#read 6, iclass 6, count 0 2006.190.08:20:00.98#ibcon#end of sib2, iclass 6, count 0 2006.190.08:20:00.98#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:20:00.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:20:00.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:20:00.98#ibcon#*before write, iclass 6, count 0 2006.190.08:20:00.98#ibcon#enter sib2, iclass 6, count 0 2006.190.08:20:00.98#ibcon#flushed, iclass 6, count 0 2006.190.08:20:00.98#ibcon#about to write, iclass 6, count 0 2006.190.08:20:00.98#ibcon#wrote, iclass 6, count 0 2006.190.08:20:00.98#ibcon#about to read 3, iclass 6, count 0 2006.190.08:20:01.02#ibcon#read 3, iclass 6, count 0 2006.190.08:20:01.02#ibcon#about to read 4, iclass 6, count 0 2006.190.08:20:01.02#ibcon#read 4, iclass 6, count 0 2006.190.08:20:01.02#ibcon#about to read 5, iclass 6, count 0 2006.190.08:20:01.02#ibcon#read 5, iclass 6, count 0 2006.190.08:20:01.02#ibcon#about to read 6, iclass 6, count 0 2006.190.08:20:01.02#ibcon#read 6, iclass 6, count 0 2006.190.08:20:01.02#ibcon#end of sib2, iclass 6, count 0 2006.190.08:20:01.02#ibcon#*after write, iclass 6, count 0 2006.190.08:20:01.02#ibcon#*before return 0, iclass 6, count 0 2006.190.08:20:01.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:20:01.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:20:01.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:20:01.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:20:01.02$vc4f8/vb=2,4 2006.190.08:20:01.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.08:20:01.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.08:20:01.02#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:01.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:20:01.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:20:01.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:20:01.08#ibcon#enter wrdev, iclass 10, count 2 2006.190.08:20:01.08#ibcon#first serial, iclass 10, count 2 2006.190.08:20:01.08#ibcon#enter sib2, iclass 10, count 2 2006.190.08:20:01.08#ibcon#flushed, iclass 10, count 2 2006.190.08:20:01.08#ibcon#about to write, iclass 10, count 2 2006.190.08:20:01.08#ibcon#wrote, iclass 10, count 2 2006.190.08:20:01.08#ibcon#about to read 3, iclass 10, count 2 2006.190.08:20:01.10#ibcon#read 3, iclass 10, count 2 2006.190.08:20:01.10#ibcon#about to read 4, iclass 10, count 2 2006.190.08:20:01.10#ibcon#read 4, iclass 10, count 2 2006.190.08:20:01.10#ibcon#about to read 5, iclass 10, count 2 2006.190.08:20:01.10#ibcon#read 5, iclass 10, count 2 2006.190.08:20:01.10#ibcon#about to read 6, iclass 10, count 2 2006.190.08:20:01.10#ibcon#read 6, iclass 10, count 2 2006.190.08:20:01.10#ibcon#end of sib2, iclass 10, count 2 2006.190.08:20:01.10#ibcon#*mode == 0, iclass 10, count 2 2006.190.08:20:01.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.08:20:01.10#ibcon#[27=AT02-04\r\n] 2006.190.08:20:01.10#ibcon#*before write, iclass 10, count 2 2006.190.08:20:01.10#ibcon#enter sib2, iclass 10, count 2 2006.190.08:20:01.10#ibcon#flushed, iclass 10, count 2 2006.190.08:20:01.10#ibcon#about to write, iclass 10, count 2 2006.190.08:20:01.10#ibcon#wrote, iclass 10, count 2 2006.190.08:20:01.10#ibcon#about to read 3, iclass 10, count 2 2006.190.08:20:01.13#ibcon#read 3, iclass 10, count 2 2006.190.08:20:01.13#ibcon#about to read 4, iclass 10, count 2 2006.190.08:20:01.13#ibcon#read 4, iclass 10, count 2 2006.190.08:20:01.13#ibcon#about to read 5, iclass 10, count 2 2006.190.08:20:01.13#ibcon#read 5, iclass 10, count 2 2006.190.08:20:01.13#ibcon#about to read 6, iclass 10, count 2 2006.190.08:20:01.13#ibcon#read 6, iclass 10, count 2 2006.190.08:20:01.13#ibcon#end of sib2, iclass 10, count 2 2006.190.08:20:01.13#ibcon#*after write, iclass 10, count 2 2006.190.08:20:01.13#ibcon#*before return 0, iclass 10, count 2 2006.190.08:20:01.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:20:01.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:20:01.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.08:20:01.13#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:01.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:20:01.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:20:01.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:20:01.25#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:20:01.25#ibcon#first serial, iclass 10, count 0 2006.190.08:20:01.25#ibcon#enter sib2, iclass 10, count 0 2006.190.08:20:01.25#ibcon#flushed, iclass 10, count 0 2006.190.08:20:01.25#ibcon#about to write, iclass 10, count 0 2006.190.08:20:01.25#ibcon#wrote, iclass 10, count 0 2006.190.08:20:01.25#ibcon#about to read 3, iclass 10, count 0 2006.190.08:20:01.27#ibcon#read 3, iclass 10, count 0 2006.190.08:20:01.27#ibcon#about to read 4, iclass 10, count 0 2006.190.08:20:01.27#ibcon#read 4, iclass 10, count 0 2006.190.08:20:01.27#ibcon#about to read 5, iclass 10, count 0 2006.190.08:20:01.27#ibcon#read 5, iclass 10, count 0 2006.190.08:20:01.27#ibcon#about to read 6, iclass 10, count 0 2006.190.08:20:01.27#ibcon#read 6, iclass 10, count 0 2006.190.08:20:01.27#ibcon#end of sib2, iclass 10, count 0 2006.190.08:20:01.27#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:20:01.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:20:01.27#ibcon#[27=USB\r\n] 2006.190.08:20:01.27#ibcon#*before write, iclass 10, count 0 2006.190.08:20:01.27#ibcon#enter sib2, iclass 10, count 0 2006.190.08:20:01.27#ibcon#flushed, iclass 10, count 0 2006.190.08:20:01.27#ibcon#about to write, iclass 10, count 0 2006.190.08:20:01.27#ibcon#wrote, iclass 10, count 0 2006.190.08:20:01.27#ibcon#about to read 3, iclass 10, count 0 2006.190.08:20:01.30#ibcon#read 3, iclass 10, count 0 2006.190.08:20:01.30#ibcon#about to read 4, iclass 10, count 0 2006.190.08:20:01.30#ibcon#read 4, iclass 10, count 0 2006.190.08:20:01.30#ibcon#about to read 5, iclass 10, count 0 2006.190.08:20:01.30#ibcon#read 5, iclass 10, count 0 2006.190.08:20:01.30#ibcon#about to read 6, iclass 10, count 0 2006.190.08:20:01.30#ibcon#read 6, iclass 10, count 0 2006.190.08:20:01.30#ibcon#end of sib2, iclass 10, count 0 2006.190.08:20:01.30#ibcon#*after write, iclass 10, count 0 2006.190.08:20:01.30#ibcon#*before return 0, iclass 10, count 0 2006.190.08:20:01.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:20:01.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:20:01.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:20:01.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:20:01.30$vc4f8/vblo=3,656.99 2006.190.08:20:01.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:20:01.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:20:01.30#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:01.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:20:01.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:20:01.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:20:01.30#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:20:01.30#ibcon#first serial, iclass 12, count 0 2006.190.08:20:01.30#ibcon#enter sib2, iclass 12, count 0 2006.190.08:20:01.30#ibcon#flushed, iclass 12, count 0 2006.190.08:20:01.30#ibcon#about to write, iclass 12, count 0 2006.190.08:20:01.30#ibcon#wrote, iclass 12, count 0 2006.190.08:20:01.30#ibcon#about to read 3, iclass 12, count 0 2006.190.08:20:01.32#ibcon#read 3, iclass 12, count 0 2006.190.08:20:01.32#ibcon#about to read 4, iclass 12, count 0 2006.190.08:20:01.32#ibcon#read 4, iclass 12, count 0 2006.190.08:20:01.32#ibcon#about to read 5, iclass 12, count 0 2006.190.08:20:01.32#ibcon#read 5, iclass 12, count 0 2006.190.08:20:01.32#ibcon#about to read 6, iclass 12, count 0 2006.190.08:20:01.32#ibcon#read 6, iclass 12, count 0 2006.190.08:20:01.32#ibcon#end of sib2, iclass 12, count 0 2006.190.08:20:01.32#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:20:01.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:20:01.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:20:01.32#ibcon#*before write, iclass 12, count 0 2006.190.08:20:01.32#ibcon#enter sib2, iclass 12, count 0 2006.190.08:20:01.32#ibcon#flushed, iclass 12, count 0 2006.190.08:20:01.32#ibcon#about to write, iclass 12, count 0 2006.190.08:20:01.32#ibcon#wrote, iclass 12, count 0 2006.190.08:20:01.32#ibcon#about to read 3, iclass 12, count 0 2006.190.08:20:01.36#ibcon#read 3, iclass 12, count 0 2006.190.08:20:01.36#ibcon#about to read 4, iclass 12, count 0 2006.190.08:20:01.36#ibcon#read 4, iclass 12, count 0 2006.190.08:20:01.36#ibcon#about to read 5, iclass 12, count 0 2006.190.08:20:01.36#ibcon#read 5, iclass 12, count 0 2006.190.08:20:01.36#ibcon#about to read 6, iclass 12, count 0 2006.190.08:20:01.36#ibcon#read 6, iclass 12, count 0 2006.190.08:20:01.36#ibcon#end of sib2, iclass 12, count 0 2006.190.08:20:01.36#ibcon#*after write, iclass 12, count 0 2006.190.08:20:01.36#ibcon#*before return 0, iclass 12, count 0 2006.190.08:20:01.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:20:01.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:20:01.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:20:01.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:20:01.36$vc4f8/vb=3,4 2006.190.08:20:01.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:20:01.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:20:01.36#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:01.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:20:01.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:20:01.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:20:01.42#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:20:01.42#ibcon#first serial, iclass 14, count 2 2006.190.08:20:01.42#ibcon#enter sib2, iclass 14, count 2 2006.190.08:20:01.42#ibcon#flushed, iclass 14, count 2 2006.190.08:20:01.42#ibcon#about to write, iclass 14, count 2 2006.190.08:20:01.42#ibcon#wrote, iclass 14, count 2 2006.190.08:20:01.42#ibcon#about to read 3, iclass 14, count 2 2006.190.08:20:01.44#ibcon#read 3, iclass 14, count 2 2006.190.08:20:01.44#ibcon#about to read 4, iclass 14, count 2 2006.190.08:20:01.44#ibcon#read 4, iclass 14, count 2 2006.190.08:20:01.44#ibcon#about to read 5, iclass 14, count 2 2006.190.08:20:01.44#ibcon#read 5, iclass 14, count 2 2006.190.08:20:01.44#ibcon#about to read 6, iclass 14, count 2 2006.190.08:20:01.44#ibcon#read 6, iclass 14, count 2 2006.190.08:20:01.44#ibcon#end of sib2, iclass 14, count 2 2006.190.08:20:01.44#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:20:01.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:20:01.44#ibcon#[27=AT03-04\r\n] 2006.190.08:20:01.44#ibcon#*before write, iclass 14, count 2 2006.190.08:20:01.44#ibcon#enter sib2, iclass 14, count 2 2006.190.08:20:01.44#ibcon#flushed, iclass 14, count 2 2006.190.08:20:01.44#ibcon#about to write, iclass 14, count 2 2006.190.08:20:01.44#ibcon#wrote, iclass 14, count 2 2006.190.08:20:01.44#ibcon#about to read 3, iclass 14, count 2 2006.190.08:20:01.47#ibcon#read 3, iclass 14, count 2 2006.190.08:20:01.47#ibcon#about to read 4, iclass 14, count 2 2006.190.08:20:01.47#ibcon#read 4, iclass 14, count 2 2006.190.08:20:01.47#ibcon#about to read 5, iclass 14, count 2 2006.190.08:20:01.47#ibcon#read 5, iclass 14, count 2 2006.190.08:20:01.47#ibcon#about to read 6, iclass 14, count 2 2006.190.08:20:01.47#ibcon#read 6, iclass 14, count 2 2006.190.08:20:01.47#ibcon#end of sib2, iclass 14, count 2 2006.190.08:20:01.47#ibcon#*after write, iclass 14, count 2 2006.190.08:20:01.47#ibcon#*before return 0, iclass 14, count 2 2006.190.08:20:01.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:20:01.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:20:01.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:20:01.47#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:01.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:20:01.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:20:01.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:20:01.59#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:20:01.59#ibcon#first serial, iclass 14, count 0 2006.190.08:20:01.59#ibcon#enter sib2, iclass 14, count 0 2006.190.08:20:01.59#ibcon#flushed, iclass 14, count 0 2006.190.08:20:01.59#ibcon#about to write, iclass 14, count 0 2006.190.08:20:01.59#ibcon#wrote, iclass 14, count 0 2006.190.08:20:01.59#ibcon#about to read 3, iclass 14, count 0 2006.190.08:20:01.61#ibcon#read 3, iclass 14, count 0 2006.190.08:20:01.61#ibcon#about to read 4, iclass 14, count 0 2006.190.08:20:01.61#ibcon#read 4, iclass 14, count 0 2006.190.08:20:01.61#ibcon#about to read 5, iclass 14, count 0 2006.190.08:20:01.61#ibcon#read 5, iclass 14, count 0 2006.190.08:20:01.61#ibcon#about to read 6, iclass 14, count 0 2006.190.08:20:01.61#ibcon#read 6, iclass 14, count 0 2006.190.08:20:01.61#ibcon#end of sib2, iclass 14, count 0 2006.190.08:20:01.61#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:20:01.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:20:01.61#ibcon#[27=USB\r\n] 2006.190.08:20:01.61#ibcon#*before write, iclass 14, count 0 2006.190.08:20:01.61#ibcon#enter sib2, iclass 14, count 0 2006.190.08:20:01.61#ibcon#flushed, iclass 14, count 0 2006.190.08:20:01.61#ibcon#about to write, iclass 14, count 0 2006.190.08:20:01.61#ibcon#wrote, iclass 14, count 0 2006.190.08:20:01.61#ibcon#about to read 3, iclass 14, count 0 2006.190.08:20:01.64#ibcon#read 3, iclass 14, count 0 2006.190.08:20:01.64#ibcon#about to read 4, iclass 14, count 0 2006.190.08:20:01.64#ibcon#read 4, iclass 14, count 0 2006.190.08:20:01.64#ibcon#about to read 5, iclass 14, count 0 2006.190.08:20:01.64#ibcon#read 5, iclass 14, count 0 2006.190.08:20:01.64#ibcon#about to read 6, iclass 14, count 0 2006.190.08:20:01.64#ibcon#read 6, iclass 14, count 0 2006.190.08:20:01.64#ibcon#end of sib2, iclass 14, count 0 2006.190.08:20:01.64#ibcon#*after write, iclass 14, count 0 2006.190.08:20:01.64#ibcon#*before return 0, iclass 14, count 0 2006.190.08:20:01.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:20:01.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:20:01.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:20:01.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:20:01.64$vc4f8/vblo=4,712.99 2006.190.08:20:01.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:20:01.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:20:01.64#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:01.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:20:01.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:20:01.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:20:01.64#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:20:01.64#ibcon#first serial, iclass 16, count 0 2006.190.08:20:01.64#ibcon#enter sib2, iclass 16, count 0 2006.190.08:20:01.64#ibcon#flushed, iclass 16, count 0 2006.190.08:20:01.64#ibcon#about to write, iclass 16, count 0 2006.190.08:20:01.64#ibcon#wrote, iclass 16, count 0 2006.190.08:20:01.64#ibcon#about to read 3, iclass 16, count 0 2006.190.08:20:01.66#ibcon#read 3, iclass 16, count 0 2006.190.08:20:01.66#ibcon#about to read 4, iclass 16, count 0 2006.190.08:20:01.66#ibcon#read 4, iclass 16, count 0 2006.190.08:20:01.66#ibcon#about to read 5, iclass 16, count 0 2006.190.08:20:01.66#ibcon#read 5, iclass 16, count 0 2006.190.08:20:01.66#ibcon#about to read 6, iclass 16, count 0 2006.190.08:20:01.66#ibcon#read 6, iclass 16, count 0 2006.190.08:20:01.66#ibcon#end of sib2, iclass 16, count 0 2006.190.08:20:01.66#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:20:01.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:20:01.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:20:01.66#ibcon#*before write, iclass 16, count 0 2006.190.08:20:01.66#ibcon#enter sib2, iclass 16, count 0 2006.190.08:20:01.66#ibcon#flushed, iclass 16, count 0 2006.190.08:20:01.66#ibcon#about to write, iclass 16, count 0 2006.190.08:20:01.66#ibcon#wrote, iclass 16, count 0 2006.190.08:20:01.66#ibcon#about to read 3, iclass 16, count 0 2006.190.08:20:01.70#ibcon#read 3, iclass 16, count 0 2006.190.08:20:01.70#ibcon#about to read 4, iclass 16, count 0 2006.190.08:20:01.70#ibcon#read 4, iclass 16, count 0 2006.190.08:20:01.70#ibcon#about to read 5, iclass 16, count 0 2006.190.08:20:01.70#ibcon#read 5, iclass 16, count 0 2006.190.08:20:01.70#ibcon#about to read 6, iclass 16, count 0 2006.190.08:20:01.70#ibcon#read 6, iclass 16, count 0 2006.190.08:20:01.70#ibcon#end of sib2, iclass 16, count 0 2006.190.08:20:01.70#ibcon#*after write, iclass 16, count 0 2006.190.08:20:01.70#ibcon#*before return 0, iclass 16, count 0 2006.190.08:20:01.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:20:01.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:20:01.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:20:01.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:20:01.70$vc4f8/vb=4,4 2006.190.08:20:01.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.08:20:01.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.08:20:01.70#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:01.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:20:01.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:20:01.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:20:01.76#ibcon#enter wrdev, iclass 18, count 2 2006.190.08:20:01.76#ibcon#first serial, iclass 18, count 2 2006.190.08:20:01.76#ibcon#enter sib2, iclass 18, count 2 2006.190.08:20:01.76#ibcon#flushed, iclass 18, count 2 2006.190.08:20:01.76#ibcon#about to write, iclass 18, count 2 2006.190.08:20:01.76#ibcon#wrote, iclass 18, count 2 2006.190.08:20:01.76#ibcon#about to read 3, iclass 18, count 2 2006.190.08:20:01.78#ibcon#read 3, iclass 18, count 2 2006.190.08:20:01.78#ibcon#about to read 4, iclass 18, count 2 2006.190.08:20:01.78#ibcon#read 4, iclass 18, count 2 2006.190.08:20:01.78#ibcon#about to read 5, iclass 18, count 2 2006.190.08:20:01.78#ibcon#read 5, iclass 18, count 2 2006.190.08:20:01.78#ibcon#about to read 6, iclass 18, count 2 2006.190.08:20:01.78#ibcon#read 6, iclass 18, count 2 2006.190.08:20:01.78#ibcon#end of sib2, iclass 18, count 2 2006.190.08:20:01.78#ibcon#*mode == 0, iclass 18, count 2 2006.190.08:20:01.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.08:20:01.78#ibcon#[27=AT04-04\r\n] 2006.190.08:20:01.78#ibcon#*before write, iclass 18, count 2 2006.190.08:20:01.78#ibcon#enter sib2, iclass 18, count 2 2006.190.08:20:01.78#ibcon#flushed, iclass 18, count 2 2006.190.08:20:01.78#ibcon#about to write, iclass 18, count 2 2006.190.08:20:01.78#ibcon#wrote, iclass 18, count 2 2006.190.08:20:01.78#ibcon#about to read 3, iclass 18, count 2 2006.190.08:20:01.81#ibcon#read 3, iclass 18, count 2 2006.190.08:20:01.81#ibcon#about to read 4, iclass 18, count 2 2006.190.08:20:01.81#ibcon#read 4, iclass 18, count 2 2006.190.08:20:01.81#ibcon#about to read 5, iclass 18, count 2 2006.190.08:20:01.81#ibcon#read 5, iclass 18, count 2 2006.190.08:20:01.81#ibcon#about to read 6, iclass 18, count 2 2006.190.08:20:01.81#ibcon#read 6, iclass 18, count 2 2006.190.08:20:01.81#ibcon#end of sib2, iclass 18, count 2 2006.190.08:20:01.81#ibcon#*after write, iclass 18, count 2 2006.190.08:20:01.81#ibcon#*before return 0, iclass 18, count 2 2006.190.08:20:01.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:20:01.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:20:01.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.08:20:01.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:01.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:20:01.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:20:01.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:20:01.93#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:20:01.93#ibcon#first serial, iclass 18, count 0 2006.190.08:20:01.93#ibcon#enter sib2, iclass 18, count 0 2006.190.08:20:01.93#ibcon#flushed, iclass 18, count 0 2006.190.08:20:01.93#ibcon#about to write, iclass 18, count 0 2006.190.08:20:01.93#ibcon#wrote, iclass 18, count 0 2006.190.08:20:01.93#ibcon#about to read 3, iclass 18, count 0 2006.190.08:20:01.95#ibcon#read 3, iclass 18, count 0 2006.190.08:20:01.95#ibcon#about to read 4, iclass 18, count 0 2006.190.08:20:01.95#ibcon#read 4, iclass 18, count 0 2006.190.08:20:01.95#ibcon#about to read 5, iclass 18, count 0 2006.190.08:20:01.95#ibcon#read 5, iclass 18, count 0 2006.190.08:20:01.95#ibcon#about to read 6, iclass 18, count 0 2006.190.08:20:01.95#ibcon#read 6, iclass 18, count 0 2006.190.08:20:01.95#ibcon#end of sib2, iclass 18, count 0 2006.190.08:20:01.95#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:20:01.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:20:01.95#ibcon#[27=USB\r\n] 2006.190.08:20:01.95#ibcon#*before write, iclass 18, count 0 2006.190.08:20:01.95#ibcon#enter sib2, iclass 18, count 0 2006.190.08:20:01.95#ibcon#flushed, iclass 18, count 0 2006.190.08:20:01.95#ibcon#about to write, iclass 18, count 0 2006.190.08:20:01.95#ibcon#wrote, iclass 18, count 0 2006.190.08:20:01.95#ibcon#about to read 3, iclass 18, count 0 2006.190.08:20:01.98#ibcon#read 3, iclass 18, count 0 2006.190.08:20:01.98#ibcon#about to read 4, iclass 18, count 0 2006.190.08:20:01.98#ibcon#read 4, iclass 18, count 0 2006.190.08:20:01.98#ibcon#about to read 5, iclass 18, count 0 2006.190.08:20:01.98#ibcon#read 5, iclass 18, count 0 2006.190.08:20:01.98#ibcon#about to read 6, iclass 18, count 0 2006.190.08:20:01.98#ibcon#read 6, iclass 18, count 0 2006.190.08:20:01.98#ibcon#end of sib2, iclass 18, count 0 2006.190.08:20:01.98#ibcon#*after write, iclass 18, count 0 2006.190.08:20:01.98#ibcon#*before return 0, iclass 18, count 0 2006.190.08:20:01.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:20:01.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:20:01.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:20:01.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:20:01.98$vc4f8/vblo=5,744.99 2006.190.08:20:01.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.08:20:01.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.08:20:01.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:01.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:20:01.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:20:01.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:20:01.98#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:20:01.98#ibcon#first serial, iclass 20, count 0 2006.190.08:20:01.98#ibcon#enter sib2, iclass 20, count 0 2006.190.08:20:01.98#ibcon#flushed, iclass 20, count 0 2006.190.08:20:01.98#ibcon#about to write, iclass 20, count 0 2006.190.08:20:01.98#ibcon#wrote, iclass 20, count 0 2006.190.08:20:01.98#ibcon#about to read 3, iclass 20, count 0 2006.190.08:20:02.00#ibcon#read 3, iclass 20, count 0 2006.190.08:20:02.00#ibcon#about to read 4, iclass 20, count 0 2006.190.08:20:02.00#ibcon#read 4, iclass 20, count 0 2006.190.08:20:02.00#ibcon#about to read 5, iclass 20, count 0 2006.190.08:20:02.00#ibcon#read 5, iclass 20, count 0 2006.190.08:20:02.00#ibcon#about to read 6, iclass 20, count 0 2006.190.08:20:02.00#ibcon#read 6, iclass 20, count 0 2006.190.08:20:02.00#ibcon#end of sib2, iclass 20, count 0 2006.190.08:20:02.00#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:20:02.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:20:02.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:20:02.00#ibcon#*before write, iclass 20, count 0 2006.190.08:20:02.00#ibcon#enter sib2, iclass 20, count 0 2006.190.08:20:02.00#ibcon#flushed, iclass 20, count 0 2006.190.08:20:02.00#ibcon#about to write, iclass 20, count 0 2006.190.08:20:02.00#ibcon#wrote, iclass 20, count 0 2006.190.08:20:02.00#ibcon#about to read 3, iclass 20, count 0 2006.190.08:20:02.04#ibcon#read 3, iclass 20, count 0 2006.190.08:20:02.04#ibcon#about to read 4, iclass 20, count 0 2006.190.08:20:02.04#ibcon#read 4, iclass 20, count 0 2006.190.08:20:02.04#ibcon#about to read 5, iclass 20, count 0 2006.190.08:20:02.04#ibcon#read 5, iclass 20, count 0 2006.190.08:20:02.04#ibcon#about to read 6, iclass 20, count 0 2006.190.08:20:02.04#ibcon#read 6, iclass 20, count 0 2006.190.08:20:02.04#ibcon#end of sib2, iclass 20, count 0 2006.190.08:20:02.04#ibcon#*after write, iclass 20, count 0 2006.190.08:20:02.04#ibcon#*before return 0, iclass 20, count 0 2006.190.08:20:02.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:20:02.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:20:02.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:20:02.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:20:02.04$vc4f8/vb=5,4 2006.190.08:20:02.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.08:20:02.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.08:20:02.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:02.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:20:02.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:20:02.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:20:02.10#ibcon#enter wrdev, iclass 22, count 2 2006.190.08:20:02.10#ibcon#first serial, iclass 22, count 2 2006.190.08:20:02.10#ibcon#enter sib2, iclass 22, count 2 2006.190.08:20:02.10#ibcon#flushed, iclass 22, count 2 2006.190.08:20:02.10#ibcon#about to write, iclass 22, count 2 2006.190.08:20:02.10#ibcon#wrote, iclass 22, count 2 2006.190.08:20:02.10#ibcon#about to read 3, iclass 22, count 2 2006.190.08:20:02.12#ibcon#read 3, iclass 22, count 2 2006.190.08:20:02.12#ibcon#about to read 4, iclass 22, count 2 2006.190.08:20:02.12#ibcon#read 4, iclass 22, count 2 2006.190.08:20:02.12#ibcon#about to read 5, iclass 22, count 2 2006.190.08:20:02.12#ibcon#read 5, iclass 22, count 2 2006.190.08:20:02.12#ibcon#about to read 6, iclass 22, count 2 2006.190.08:20:02.12#ibcon#read 6, iclass 22, count 2 2006.190.08:20:02.12#ibcon#end of sib2, iclass 22, count 2 2006.190.08:20:02.12#ibcon#*mode == 0, iclass 22, count 2 2006.190.08:20:02.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.08:20:02.12#ibcon#[27=AT05-04\r\n] 2006.190.08:20:02.12#ibcon#*before write, iclass 22, count 2 2006.190.08:20:02.12#ibcon#enter sib2, iclass 22, count 2 2006.190.08:20:02.12#ibcon#flushed, iclass 22, count 2 2006.190.08:20:02.12#ibcon#about to write, iclass 22, count 2 2006.190.08:20:02.12#ibcon#wrote, iclass 22, count 2 2006.190.08:20:02.12#ibcon#about to read 3, iclass 22, count 2 2006.190.08:20:02.15#ibcon#read 3, iclass 22, count 2 2006.190.08:20:02.15#ibcon#about to read 4, iclass 22, count 2 2006.190.08:20:02.15#ibcon#read 4, iclass 22, count 2 2006.190.08:20:02.15#ibcon#about to read 5, iclass 22, count 2 2006.190.08:20:02.15#ibcon#read 5, iclass 22, count 2 2006.190.08:20:02.15#ibcon#about to read 6, iclass 22, count 2 2006.190.08:20:02.15#ibcon#read 6, iclass 22, count 2 2006.190.08:20:02.15#ibcon#end of sib2, iclass 22, count 2 2006.190.08:20:02.15#ibcon#*after write, iclass 22, count 2 2006.190.08:20:02.15#ibcon#*before return 0, iclass 22, count 2 2006.190.08:20:02.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:20:02.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:20:02.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.08:20:02.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:02.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:20:02.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:20:02.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:20:02.27#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:20:02.27#ibcon#first serial, iclass 22, count 0 2006.190.08:20:02.27#ibcon#enter sib2, iclass 22, count 0 2006.190.08:20:02.27#ibcon#flushed, iclass 22, count 0 2006.190.08:20:02.27#ibcon#about to write, iclass 22, count 0 2006.190.08:20:02.27#ibcon#wrote, iclass 22, count 0 2006.190.08:20:02.27#ibcon#about to read 3, iclass 22, count 0 2006.190.08:20:02.29#ibcon#read 3, iclass 22, count 0 2006.190.08:20:02.29#ibcon#about to read 4, iclass 22, count 0 2006.190.08:20:02.29#ibcon#read 4, iclass 22, count 0 2006.190.08:20:02.29#ibcon#about to read 5, iclass 22, count 0 2006.190.08:20:02.29#ibcon#read 5, iclass 22, count 0 2006.190.08:20:02.29#ibcon#about to read 6, iclass 22, count 0 2006.190.08:20:02.29#ibcon#read 6, iclass 22, count 0 2006.190.08:20:02.29#ibcon#end of sib2, iclass 22, count 0 2006.190.08:20:02.29#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:20:02.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:20:02.29#ibcon#[27=USB\r\n] 2006.190.08:20:02.29#ibcon#*before write, iclass 22, count 0 2006.190.08:20:02.29#ibcon#enter sib2, iclass 22, count 0 2006.190.08:20:02.29#ibcon#flushed, iclass 22, count 0 2006.190.08:20:02.29#ibcon#about to write, iclass 22, count 0 2006.190.08:20:02.29#ibcon#wrote, iclass 22, count 0 2006.190.08:20:02.29#ibcon#about to read 3, iclass 22, count 0 2006.190.08:20:02.32#ibcon#read 3, iclass 22, count 0 2006.190.08:20:02.32#ibcon#about to read 4, iclass 22, count 0 2006.190.08:20:02.32#ibcon#read 4, iclass 22, count 0 2006.190.08:20:02.32#ibcon#about to read 5, iclass 22, count 0 2006.190.08:20:02.32#ibcon#read 5, iclass 22, count 0 2006.190.08:20:02.32#ibcon#about to read 6, iclass 22, count 0 2006.190.08:20:02.32#ibcon#read 6, iclass 22, count 0 2006.190.08:20:02.32#ibcon#end of sib2, iclass 22, count 0 2006.190.08:20:02.32#ibcon#*after write, iclass 22, count 0 2006.190.08:20:02.32#ibcon#*before return 0, iclass 22, count 0 2006.190.08:20:02.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:20:02.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:20:02.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:20:02.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:20:02.32$vc4f8/vblo=6,752.99 2006.190.08:20:02.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.08:20:02.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.08:20:02.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:20:02.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:20:02.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:20:02.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:20:02.32#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:20:02.32#ibcon#first serial, iclass 24, count 0 2006.190.08:20:02.32#ibcon#enter sib2, iclass 24, count 0 2006.190.08:20:02.32#ibcon#flushed, iclass 24, count 0 2006.190.08:20:02.32#ibcon#about to write, iclass 24, count 0 2006.190.08:20:02.32#ibcon#wrote, iclass 24, count 0 2006.190.08:20:02.32#ibcon#about to read 3, iclass 24, count 0 2006.190.08:20:02.34#ibcon#read 3, iclass 24, count 0 2006.190.08:20:02.34#ibcon#about to read 4, iclass 24, count 0 2006.190.08:20:02.34#ibcon#read 4, iclass 24, count 0 2006.190.08:20:02.34#ibcon#about to read 5, iclass 24, count 0 2006.190.08:20:02.34#ibcon#read 5, iclass 24, count 0 2006.190.08:20:02.34#ibcon#about to read 6, iclass 24, count 0 2006.190.08:20:02.34#ibcon#read 6, iclass 24, count 0 2006.190.08:20:02.34#ibcon#end of sib2, iclass 24, count 0 2006.190.08:20:02.34#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:20:02.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:20:02.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:20:02.34#ibcon#*before write, iclass 24, count 0 2006.190.08:20:02.34#ibcon#enter sib2, iclass 24, count 0 2006.190.08:20:02.34#ibcon#flushed, iclass 24, count 0 2006.190.08:20:02.34#ibcon#about to write, iclass 24, count 0 2006.190.08:20:02.34#ibcon#wrote, iclass 24, count 0 2006.190.08:20:02.34#ibcon#about to read 3, iclass 24, count 0 2006.190.08:20:02.38#ibcon#read 3, iclass 24, count 0 2006.190.08:20:02.38#ibcon#about to read 4, iclass 24, count 0 2006.190.08:20:02.38#ibcon#read 4, iclass 24, count 0 2006.190.08:20:02.38#ibcon#about to read 5, iclass 24, count 0 2006.190.08:20:02.38#ibcon#read 5, iclass 24, count 0 2006.190.08:20:02.38#ibcon#about to read 6, iclass 24, count 0 2006.190.08:20:02.38#ibcon#read 6, iclass 24, count 0 2006.190.08:20:02.38#ibcon#end of sib2, iclass 24, count 0 2006.190.08:20:02.38#ibcon#*after write, iclass 24, count 0 2006.190.08:20:02.38#ibcon#*before return 0, iclass 24, count 0 2006.190.08:20:02.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:20:02.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:20:02.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:20:02.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:20:02.38$vc4f8/vb=6,4 2006.190.08:20:02.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.08:20:02.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.08:20:02.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:20:02.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:20:02.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:20:02.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:20:02.44#ibcon#enter wrdev, iclass 26, count 2 2006.190.08:20:02.44#ibcon#first serial, iclass 26, count 2 2006.190.08:20:02.44#ibcon#enter sib2, iclass 26, count 2 2006.190.08:20:02.44#ibcon#flushed, iclass 26, count 2 2006.190.08:20:02.44#ibcon#about to write, iclass 26, count 2 2006.190.08:20:02.44#ibcon#wrote, iclass 26, count 2 2006.190.08:20:02.44#ibcon#about to read 3, iclass 26, count 2 2006.190.08:20:02.46#ibcon#read 3, iclass 26, count 2 2006.190.08:20:02.46#ibcon#about to read 4, iclass 26, count 2 2006.190.08:20:02.46#ibcon#read 4, iclass 26, count 2 2006.190.08:20:02.46#ibcon#about to read 5, iclass 26, count 2 2006.190.08:20:02.46#ibcon#read 5, iclass 26, count 2 2006.190.08:20:02.46#ibcon#about to read 6, iclass 26, count 2 2006.190.08:20:02.46#ibcon#read 6, iclass 26, count 2 2006.190.08:20:02.46#ibcon#end of sib2, iclass 26, count 2 2006.190.08:20:02.46#ibcon#*mode == 0, iclass 26, count 2 2006.190.08:20:02.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.08:20:02.46#ibcon#[27=AT06-04\r\n] 2006.190.08:20:02.46#ibcon#*before write, iclass 26, count 2 2006.190.08:20:02.46#ibcon#enter sib2, iclass 26, count 2 2006.190.08:20:02.46#ibcon#flushed, iclass 26, count 2 2006.190.08:20:02.46#ibcon#about to write, iclass 26, count 2 2006.190.08:20:02.46#ibcon#wrote, iclass 26, count 2 2006.190.08:20:02.46#ibcon#about to read 3, iclass 26, count 2 2006.190.08:20:02.49#ibcon#read 3, iclass 26, count 2 2006.190.08:20:02.49#ibcon#about to read 4, iclass 26, count 2 2006.190.08:20:02.49#ibcon#read 4, iclass 26, count 2 2006.190.08:20:02.49#ibcon#about to read 5, iclass 26, count 2 2006.190.08:20:02.49#ibcon#read 5, iclass 26, count 2 2006.190.08:20:02.49#ibcon#about to read 6, iclass 26, count 2 2006.190.08:20:02.49#ibcon#read 6, iclass 26, count 2 2006.190.08:20:02.49#ibcon#end of sib2, iclass 26, count 2 2006.190.08:20:02.49#ibcon#*after write, iclass 26, count 2 2006.190.08:20:02.49#ibcon#*before return 0, iclass 26, count 2 2006.190.08:20:02.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:20:02.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:20:02.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.08:20:02.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:20:02.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:20:02.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:20:02.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:20:02.61#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:20:02.61#ibcon#first serial, iclass 26, count 0 2006.190.08:20:02.61#ibcon#enter sib2, iclass 26, count 0 2006.190.08:20:02.61#ibcon#flushed, iclass 26, count 0 2006.190.08:20:02.61#ibcon#about to write, iclass 26, count 0 2006.190.08:20:02.61#ibcon#wrote, iclass 26, count 0 2006.190.08:20:02.61#ibcon#about to read 3, iclass 26, count 0 2006.190.08:20:02.63#ibcon#read 3, iclass 26, count 0 2006.190.08:20:02.63#ibcon#about to read 4, iclass 26, count 0 2006.190.08:20:02.63#ibcon#read 4, iclass 26, count 0 2006.190.08:20:02.63#ibcon#about to read 5, iclass 26, count 0 2006.190.08:20:02.63#ibcon#read 5, iclass 26, count 0 2006.190.08:20:02.63#ibcon#about to read 6, iclass 26, count 0 2006.190.08:20:02.63#ibcon#read 6, iclass 26, count 0 2006.190.08:20:02.63#ibcon#end of sib2, iclass 26, count 0 2006.190.08:20:02.63#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:20:02.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:20:02.63#ibcon#[27=USB\r\n] 2006.190.08:20:02.63#ibcon#*before write, iclass 26, count 0 2006.190.08:20:02.63#ibcon#enter sib2, iclass 26, count 0 2006.190.08:20:02.63#ibcon#flushed, iclass 26, count 0 2006.190.08:20:02.63#ibcon#about to write, iclass 26, count 0 2006.190.08:20:02.63#ibcon#wrote, iclass 26, count 0 2006.190.08:20:02.63#ibcon#about to read 3, iclass 26, count 0 2006.190.08:20:02.66#ibcon#read 3, iclass 26, count 0 2006.190.08:20:02.66#ibcon#about to read 4, iclass 26, count 0 2006.190.08:20:02.66#ibcon#read 4, iclass 26, count 0 2006.190.08:20:02.66#ibcon#about to read 5, iclass 26, count 0 2006.190.08:20:02.66#ibcon#read 5, iclass 26, count 0 2006.190.08:20:02.66#ibcon#about to read 6, iclass 26, count 0 2006.190.08:20:02.66#ibcon#read 6, iclass 26, count 0 2006.190.08:20:02.66#ibcon#end of sib2, iclass 26, count 0 2006.190.08:20:02.66#ibcon#*after write, iclass 26, count 0 2006.190.08:20:02.66#ibcon#*before return 0, iclass 26, count 0 2006.190.08:20:02.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:20:02.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:20:02.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:20:02.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:20:02.66$vc4f8/vabw=wide 2006.190.08:20:02.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.08:20:02.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.08:20:02.66#ibcon#ireg 8 cls_cnt 0 2006.190.08:20:02.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:20:02.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:20:02.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:20:02.66#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:20:02.66#ibcon#first serial, iclass 28, count 0 2006.190.08:20:02.66#ibcon#enter sib2, iclass 28, count 0 2006.190.08:20:02.66#ibcon#flushed, iclass 28, count 0 2006.190.08:20:02.66#ibcon#about to write, iclass 28, count 0 2006.190.08:20:02.66#ibcon#wrote, iclass 28, count 0 2006.190.08:20:02.66#ibcon#about to read 3, iclass 28, count 0 2006.190.08:20:02.68#ibcon#read 3, iclass 28, count 0 2006.190.08:20:02.68#ibcon#about to read 4, iclass 28, count 0 2006.190.08:20:02.68#ibcon#read 4, iclass 28, count 0 2006.190.08:20:02.68#ibcon#about to read 5, iclass 28, count 0 2006.190.08:20:02.68#ibcon#read 5, iclass 28, count 0 2006.190.08:20:02.68#ibcon#about to read 6, iclass 28, count 0 2006.190.08:20:02.68#ibcon#read 6, iclass 28, count 0 2006.190.08:20:02.68#ibcon#end of sib2, iclass 28, count 0 2006.190.08:20:02.68#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:20:02.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:20:02.68#ibcon#[25=BW32\r\n] 2006.190.08:20:02.68#ibcon#*before write, iclass 28, count 0 2006.190.08:20:02.68#ibcon#enter sib2, iclass 28, count 0 2006.190.08:20:02.68#ibcon#flushed, iclass 28, count 0 2006.190.08:20:02.68#ibcon#about to write, iclass 28, count 0 2006.190.08:20:02.68#ibcon#wrote, iclass 28, count 0 2006.190.08:20:02.68#ibcon#about to read 3, iclass 28, count 0 2006.190.08:20:02.71#ibcon#read 3, iclass 28, count 0 2006.190.08:20:02.71#ibcon#about to read 4, iclass 28, count 0 2006.190.08:20:02.71#ibcon#read 4, iclass 28, count 0 2006.190.08:20:02.71#ibcon#about to read 5, iclass 28, count 0 2006.190.08:20:02.71#ibcon#read 5, iclass 28, count 0 2006.190.08:20:02.71#ibcon#about to read 6, iclass 28, count 0 2006.190.08:20:02.71#ibcon#read 6, iclass 28, count 0 2006.190.08:20:02.71#ibcon#end of sib2, iclass 28, count 0 2006.190.08:20:02.71#ibcon#*after write, iclass 28, count 0 2006.190.08:20:02.71#ibcon#*before return 0, iclass 28, count 0 2006.190.08:20:02.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:20:02.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:20:02.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:20:02.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:20:02.71$vc4f8/vbbw=wide 2006.190.08:20:02.71#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.08:20:02.71#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.08:20:02.71#ibcon#ireg 8 cls_cnt 0 2006.190.08:20:02.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:20:02.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:20:02.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:20:02.78#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:20:02.78#ibcon#first serial, iclass 30, count 0 2006.190.08:20:02.78#ibcon#enter sib2, iclass 30, count 0 2006.190.08:20:02.78#ibcon#flushed, iclass 30, count 0 2006.190.08:20:02.78#ibcon#about to write, iclass 30, count 0 2006.190.08:20:02.78#ibcon#wrote, iclass 30, count 0 2006.190.08:20:02.78#ibcon#about to read 3, iclass 30, count 0 2006.190.08:20:02.80#ibcon#read 3, iclass 30, count 0 2006.190.08:20:02.80#ibcon#about to read 4, iclass 30, count 0 2006.190.08:20:02.80#ibcon#read 4, iclass 30, count 0 2006.190.08:20:02.80#ibcon#about to read 5, iclass 30, count 0 2006.190.08:20:02.80#ibcon#read 5, iclass 30, count 0 2006.190.08:20:02.80#ibcon#about to read 6, iclass 30, count 0 2006.190.08:20:02.80#ibcon#read 6, iclass 30, count 0 2006.190.08:20:02.80#ibcon#end of sib2, iclass 30, count 0 2006.190.08:20:02.80#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:20:02.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:20:02.80#ibcon#[27=BW32\r\n] 2006.190.08:20:02.80#ibcon#*before write, iclass 30, count 0 2006.190.08:20:02.80#ibcon#enter sib2, iclass 30, count 0 2006.190.08:20:02.80#ibcon#flushed, iclass 30, count 0 2006.190.08:20:02.80#ibcon#about to write, iclass 30, count 0 2006.190.08:20:02.80#ibcon#wrote, iclass 30, count 0 2006.190.08:20:02.80#ibcon#about to read 3, iclass 30, count 0 2006.190.08:20:02.83#ibcon#read 3, iclass 30, count 0 2006.190.08:20:02.83#ibcon#about to read 4, iclass 30, count 0 2006.190.08:20:02.83#ibcon#read 4, iclass 30, count 0 2006.190.08:20:02.83#ibcon#about to read 5, iclass 30, count 0 2006.190.08:20:02.83#ibcon#read 5, iclass 30, count 0 2006.190.08:20:02.83#ibcon#about to read 6, iclass 30, count 0 2006.190.08:20:02.83#ibcon#read 6, iclass 30, count 0 2006.190.08:20:02.83#ibcon#end of sib2, iclass 30, count 0 2006.190.08:20:02.83#ibcon#*after write, iclass 30, count 0 2006.190.08:20:02.83#ibcon#*before return 0, iclass 30, count 0 2006.190.08:20:02.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:20:02.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:20:02.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:20:02.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:20:02.83$4f8m12a/ifd4f 2006.190.08:20:02.83$ifd4f/lo= 2006.190.08:20:02.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:20:02.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:20:02.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:20:02.83$ifd4f/patch= 2006.190.08:20:02.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:20:02.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:20:02.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:20:02.83$4f8m12a/"form=m,16.000,1:2 2006.190.08:20:02.83$4f8m12a/"tpicd 2006.190.08:20:02.83$4f8m12a/echo=off 2006.190.08:20:02.83$4f8m12a/xlog=off 2006.190.08:20:02.83:!2006.190.08:20:50 2006.190.08:20:18.13#trakl#Source acquired 2006.190.08:20:18.13#flagr#flagr/antenna,acquired 2006.190.08:20:50.00:preob 2006.190.08:20:50.13/onsource/TRACKING 2006.190.08:20:50.13:!2006.190.08:21:00 2006.190.08:21:00.00:data_valid=on 2006.190.08:21:00.00:midob 2006.190.08:21:00.13/onsource/TRACKING 2006.190.08:21:00.13/wx/24.41,1012.2,100 2006.190.08:21:00.28/cable/+6.4723E-03 2006.190.08:21:01.37/va/01,08,usb,yes,33,35 2006.190.08:21:01.37/va/02,07,usb,yes,33,35 2006.190.08:21:01.37/va/03,06,usb,yes,35,35 2006.190.08:21:01.37/va/04,07,usb,yes,34,37 2006.190.08:21:01.37/va/05,07,usb,yes,37,39 2006.190.08:21:01.37/va/06,06,usb,yes,36,36 2006.190.08:21:01.37/va/07,06,usb,yes,37,37 2006.190.08:21:01.37/va/08,06,usb,yes,39,39 2006.190.08:21:01.60/valo/01,532.99,yes,locked 2006.190.08:21:01.60/valo/02,572.99,yes,locked 2006.190.08:21:01.60/valo/03,672.99,yes,locked 2006.190.08:21:01.60/valo/04,832.99,yes,locked 2006.190.08:21:01.60/valo/05,652.99,yes,locked 2006.190.08:21:01.60/valo/06,772.99,yes,locked 2006.190.08:21:01.60/valo/07,832.99,yes,locked 2006.190.08:21:01.60/valo/08,852.99,yes,locked 2006.190.08:21:02.69/vb/01,04,usb,yes,29,28 2006.190.08:21:02.69/vb/02,04,usb,yes,31,33 2006.190.08:21:02.69/vb/03,04,usb,yes,28,31 2006.190.08:21:02.69/vb/04,04,usb,yes,28,29 2006.190.08:21:02.69/vb/05,04,usb,yes,27,31 2006.190.08:21:02.69/vb/06,04,usb,yes,28,31 2006.190.08:21:02.69/vb/07,04,usb,yes,30,30 2006.190.08:21:02.69/vb/08,04,usb,yes,28,31 2006.190.08:21:02.93/vblo/01,632.99,yes,locked 2006.190.08:21:02.93/vblo/02,640.99,yes,locked 2006.190.08:21:02.93/vblo/03,656.99,yes,locked 2006.190.08:21:02.93/vblo/04,712.99,yes,locked 2006.190.08:21:02.93/vblo/05,744.99,yes,locked 2006.190.08:21:02.93/vblo/06,752.99,yes,locked 2006.190.08:21:02.93/vblo/07,734.99,yes,locked 2006.190.08:21:02.93/vblo/08,744.99,yes,locked 2006.190.08:21:03.08/vabw/8 2006.190.08:21:03.23/vbbw/8 2006.190.08:21:03.32/xfe/off,on,14.7 2006.190.08:21:03.70/ifatt/23,28,28,28 2006.190.08:21:04.08/fmout-gps/S +2.88E-07 2006.190.08:21:04.16:!2006.190.08:22:00 2006.190.08:22:00.01:data_valid=off 2006.190.08:22:00.01:postob 2006.190.08:22:00.14/cable/+6.4734E-03 2006.190.08:22:00.14/wx/24.41,1012.2,100 2006.190.08:22:01.08/fmout-gps/S +2.88E-07 2006.190.08:22:01.08:scan_name=190-0824,k06190,60 2006.190.08:22:01.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.190.08:22:01.14#flagr#flagr/antenna,new-source 2006.190.08:22:02.14:checkk5 2006.190.08:22:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:22:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:22:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:22:03.67/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:22:04.05/chk_obsdata//k5ts1/T1900821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:22:04.42/chk_obsdata//k5ts2/T1900821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:22:04.80/chk_obsdata//k5ts3/T1900821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:22:05.17/chk_obsdata//k5ts4/T1900821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:22:05.87/k5log//k5ts1_log_newline 2006.190.08:22:06.58/k5log//k5ts2_log_newline 2006.190.08:22:07.27/k5log//k5ts3_log_newline 2006.190.08:22:07.97/k5log//k5ts4_log_newline 2006.190.08:22:08.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:22:08.00:4f8m12a=3 2006.190.08:22:08.00$4f8m12a/echo=on 2006.190.08:22:08.00$4f8m12a/pcalon 2006.190.08:22:08.00$pcalon/"no phase cal control is implemented here 2006.190.08:22:08.00$4f8m12a/"tpicd=stop 2006.190.08:22:08.00$4f8m12a/vc4f8 2006.190.08:22:08.00$vc4f8/valo=1,532.99 2006.190.08:22:08.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.08:22:08.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.08:22:08.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:08.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:08.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:08.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:08.00#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:22:08.00#ibcon#first serial, iclass 40, count 0 2006.190.08:22:08.00#ibcon#enter sib2, iclass 40, count 0 2006.190.08:22:08.00#ibcon#flushed, iclass 40, count 0 2006.190.08:22:08.00#ibcon#about to write, iclass 40, count 0 2006.190.08:22:08.00#ibcon#wrote, iclass 40, count 0 2006.190.08:22:08.00#ibcon#about to read 3, iclass 40, count 0 2006.190.08:22:08.05#ibcon#read 3, iclass 40, count 0 2006.190.08:22:08.05#ibcon#about to read 4, iclass 40, count 0 2006.190.08:22:08.05#ibcon#read 4, iclass 40, count 0 2006.190.08:22:08.05#ibcon#about to read 5, iclass 40, count 0 2006.190.08:22:08.05#ibcon#read 5, iclass 40, count 0 2006.190.08:22:08.05#ibcon#about to read 6, iclass 40, count 0 2006.190.08:22:08.05#ibcon#read 6, iclass 40, count 0 2006.190.08:22:08.05#ibcon#end of sib2, iclass 40, count 0 2006.190.08:22:08.05#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:22:08.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:22:08.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:22:08.05#ibcon#*before write, iclass 40, count 0 2006.190.08:22:08.05#ibcon#enter sib2, iclass 40, count 0 2006.190.08:22:08.05#ibcon#flushed, iclass 40, count 0 2006.190.08:22:08.05#ibcon#about to write, iclass 40, count 0 2006.190.08:22:08.05#ibcon#wrote, iclass 40, count 0 2006.190.08:22:08.05#ibcon#about to read 3, iclass 40, count 0 2006.190.08:22:08.10#ibcon#read 3, iclass 40, count 0 2006.190.08:22:08.10#ibcon#about to read 4, iclass 40, count 0 2006.190.08:22:08.10#ibcon#read 4, iclass 40, count 0 2006.190.08:22:08.10#ibcon#about to read 5, iclass 40, count 0 2006.190.08:22:08.10#ibcon#read 5, iclass 40, count 0 2006.190.08:22:08.10#ibcon#about to read 6, iclass 40, count 0 2006.190.08:22:08.10#ibcon#read 6, iclass 40, count 0 2006.190.08:22:08.10#ibcon#end of sib2, iclass 40, count 0 2006.190.08:22:08.10#ibcon#*after write, iclass 40, count 0 2006.190.08:22:08.10#ibcon#*before return 0, iclass 40, count 0 2006.190.08:22:08.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:08.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:08.10#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:22:08.10#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:22:08.10$vc4f8/va=1,8 2006.190.08:22:08.10#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.08:22:08.10#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.08:22:08.10#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:08.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:08.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:08.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:08.10#ibcon#enter wrdev, iclass 4, count 2 2006.190.08:22:08.10#ibcon#first serial, iclass 4, count 2 2006.190.08:22:08.10#ibcon#enter sib2, iclass 4, count 2 2006.190.08:22:08.10#ibcon#flushed, iclass 4, count 2 2006.190.08:22:08.10#ibcon#about to write, iclass 4, count 2 2006.190.08:22:08.10#ibcon#wrote, iclass 4, count 2 2006.190.08:22:08.10#ibcon#about to read 3, iclass 4, count 2 2006.190.08:22:08.12#ibcon#read 3, iclass 4, count 2 2006.190.08:22:08.12#ibcon#about to read 4, iclass 4, count 2 2006.190.08:22:08.12#ibcon#read 4, iclass 4, count 2 2006.190.08:22:08.12#ibcon#about to read 5, iclass 4, count 2 2006.190.08:22:08.12#ibcon#read 5, iclass 4, count 2 2006.190.08:22:08.12#ibcon#about to read 6, iclass 4, count 2 2006.190.08:22:08.12#ibcon#read 6, iclass 4, count 2 2006.190.08:22:08.12#ibcon#end of sib2, iclass 4, count 2 2006.190.08:22:08.12#ibcon#*mode == 0, iclass 4, count 2 2006.190.08:22:08.12#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.08:22:08.12#ibcon#[25=AT01-08\r\n] 2006.190.08:22:08.12#ibcon#*before write, iclass 4, count 2 2006.190.08:22:08.12#ibcon#enter sib2, iclass 4, count 2 2006.190.08:22:08.12#ibcon#flushed, iclass 4, count 2 2006.190.08:22:08.12#ibcon#about to write, iclass 4, count 2 2006.190.08:22:08.12#ibcon#wrote, iclass 4, count 2 2006.190.08:22:08.12#ibcon#about to read 3, iclass 4, count 2 2006.190.08:22:08.15#ibcon#read 3, iclass 4, count 2 2006.190.08:22:08.15#ibcon#about to read 4, iclass 4, count 2 2006.190.08:22:08.15#ibcon#read 4, iclass 4, count 2 2006.190.08:22:08.15#ibcon#about to read 5, iclass 4, count 2 2006.190.08:22:08.15#ibcon#read 5, iclass 4, count 2 2006.190.08:22:08.15#ibcon#about to read 6, iclass 4, count 2 2006.190.08:22:08.15#ibcon#read 6, iclass 4, count 2 2006.190.08:22:08.15#ibcon#end of sib2, iclass 4, count 2 2006.190.08:22:08.15#ibcon#*after write, iclass 4, count 2 2006.190.08:22:08.15#ibcon#*before return 0, iclass 4, count 2 2006.190.08:22:08.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:08.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:08.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.08:22:08.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:08.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:08.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:08.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:08.27#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:22:08.27#ibcon#first serial, iclass 4, count 0 2006.190.08:22:08.27#ibcon#enter sib2, iclass 4, count 0 2006.190.08:22:08.27#ibcon#flushed, iclass 4, count 0 2006.190.08:22:08.27#ibcon#about to write, iclass 4, count 0 2006.190.08:22:08.27#ibcon#wrote, iclass 4, count 0 2006.190.08:22:08.27#ibcon#about to read 3, iclass 4, count 0 2006.190.08:22:08.29#ibcon#read 3, iclass 4, count 0 2006.190.08:22:08.29#ibcon#about to read 4, iclass 4, count 0 2006.190.08:22:08.29#ibcon#read 4, iclass 4, count 0 2006.190.08:22:08.29#ibcon#about to read 5, iclass 4, count 0 2006.190.08:22:08.29#ibcon#read 5, iclass 4, count 0 2006.190.08:22:08.29#ibcon#about to read 6, iclass 4, count 0 2006.190.08:22:08.29#ibcon#read 6, iclass 4, count 0 2006.190.08:22:08.29#ibcon#end of sib2, iclass 4, count 0 2006.190.08:22:08.29#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:22:08.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:22:08.29#ibcon#[25=USB\r\n] 2006.190.08:22:08.29#ibcon#*before write, iclass 4, count 0 2006.190.08:22:08.29#ibcon#enter sib2, iclass 4, count 0 2006.190.08:22:08.29#ibcon#flushed, iclass 4, count 0 2006.190.08:22:08.29#ibcon#about to write, iclass 4, count 0 2006.190.08:22:08.29#ibcon#wrote, iclass 4, count 0 2006.190.08:22:08.29#ibcon#about to read 3, iclass 4, count 0 2006.190.08:22:08.32#ibcon#read 3, iclass 4, count 0 2006.190.08:22:08.32#ibcon#about to read 4, iclass 4, count 0 2006.190.08:22:08.32#ibcon#read 4, iclass 4, count 0 2006.190.08:22:08.32#ibcon#about to read 5, iclass 4, count 0 2006.190.08:22:08.32#ibcon#read 5, iclass 4, count 0 2006.190.08:22:08.32#ibcon#about to read 6, iclass 4, count 0 2006.190.08:22:08.32#ibcon#read 6, iclass 4, count 0 2006.190.08:22:08.32#ibcon#end of sib2, iclass 4, count 0 2006.190.08:22:08.32#ibcon#*after write, iclass 4, count 0 2006.190.08:22:08.32#ibcon#*before return 0, iclass 4, count 0 2006.190.08:22:08.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:08.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:08.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:22:08.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:22:08.32$vc4f8/valo=2,572.99 2006.190.08:22:08.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:22:08.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:22:08.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:08.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:08.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:08.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:08.32#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:22:08.32#ibcon#first serial, iclass 6, count 0 2006.190.08:22:08.32#ibcon#enter sib2, iclass 6, count 0 2006.190.08:22:08.32#ibcon#flushed, iclass 6, count 0 2006.190.08:22:08.32#ibcon#about to write, iclass 6, count 0 2006.190.08:22:08.32#ibcon#wrote, iclass 6, count 0 2006.190.08:22:08.32#ibcon#about to read 3, iclass 6, count 0 2006.190.08:22:08.34#ibcon#read 3, iclass 6, count 0 2006.190.08:22:08.34#ibcon#about to read 4, iclass 6, count 0 2006.190.08:22:08.34#ibcon#read 4, iclass 6, count 0 2006.190.08:22:08.34#ibcon#about to read 5, iclass 6, count 0 2006.190.08:22:08.34#ibcon#read 5, iclass 6, count 0 2006.190.08:22:08.34#ibcon#about to read 6, iclass 6, count 0 2006.190.08:22:08.34#ibcon#read 6, iclass 6, count 0 2006.190.08:22:08.34#ibcon#end of sib2, iclass 6, count 0 2006.190.08:22:08.34#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:22:08.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:22:08.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:22:08.34#ibcon#*before write, iclass 6, count 0 2006.190.08:22:08.34#ibcon#enter sib2, iclass 6, count 0 2006.190.08:22:08.34#ibcon#flushed, iclass 6, count 0 2006.190.08:22:08.34#ibcon#about to write, iclass 6, count 0 2006.190.08:22:08.34#ibcon#wrote, iclass 6, count 0 2006.190.08:22:08.34#ibcon#about to read 3, iclass 6, count 0 2006.190.08:22:08.38#ibcon#read 3, iclass 6, count 0 2006.190.08:22:08.38#ibcon#about to read 4, iclass 6, count 0 2006.190.08:22:08.38#ibcon#read 4, iclass 6, count 0 2006.190.08:22:08.38#ibcon#about to read 5, iclass 6, count 0 2006.190.08:22:08.38#ibcon#read 5, iclass 6, count 0 2006.190.08:22:08.38#ibcon#about to read 6, iclass 6, count 0 2006.190.08:22:08.38#ibcon#read 6, iclass 6, count 0 2006.190.08:22:08.38#ibcon#end of sib2, iclass 6, count 0 2006.190.08:22:08.38#ibcon#*after write, iclass 6, count 0 2006.190.08:22:08.38#ibcon#*before return 0, iclass 6, count 0 2006.190.08:22:08.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:08.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:08.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:22:08.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:22:08.38$vc4f8/va=2,7 2006.190.08:22:08.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.08:22:08.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.08:22:08.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:08.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:08.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:08.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:08.44#ibcon#enter wrdev, iclass 10, count 2 2006.190.08:22:08.44#ibcon#first serial, iclass 10, count 2 2006.190.08:22:08.44#ibcon#enter sib2, iclass 10, count 2 2006.190.08:22:08.44#ibcon#flushed, iclass 10, count 2 2006.190.08:22:08.44#ibcon#about to write, iclass 10, count 2 2006.190.08:22:08.44#ibcon#wrote, iclass 10, count 2 2006.190.08:22:08.44#ibcon#about to read 3, iclass 10, count 2 2006.190.08:22:08.46#ibcon#read 3, iclass 10, count 2 2006.190.08:22:08.46#ibcon#about to read 4, iclass 10, count 2 2006.190.08:22:08.46#ibcon#read 4, iclass 10, count 2 2006.190.08:22:08.46#ibcon#about to read 5, iclass 10, count 2 2006.190.08:22:08.46#ibcon#read 5, iclass 10, count 2 2006.190.08:22:08.46#ibcon#about to read 6, iclass 10, count 2 2006.190.08:22:08.46#ibcon#read 6, iclass 10, count 2 2006.190.08:22:08.46#ibcon#end of sib2, iclass 10, count 2 2006.190.08:22:08.46#ibcon#*mode == 0, iclass 10, count 2 2006.190.08:22:08.46#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.08:22:08.46#ibcon#[25=AT02-07\r\n] 2006.190.08:22:08.46#ibcon#*before write, iclass 10, count 2 2006.190.08:22:08.46#ibcon#enter sib2, iclass 10, count 2 2006.190.08:22:08.46#ibcon#flushed, iclass 10, count 2 2006.190.08:22:08.46#ibcon#about to write, iclass 10, count 2 2006.190.08:22:08.46#ibcon#wrote, iclass 10, count 2 2006.190.08:22:08.46#ibcon#about to read 3, iclass 10, count 2 2006.190.08:22:08.49#ibcon#read 3, iclass 10, count 2 2006.190.08:22:08.49#ibcon#about to read 4, iclass 10, count 2 2006.190.08:22:08.49#ibcon#read 4, iclass 10, count 2 2006.190.08:22:08.49#ibcon#about to read 5, iclass 10, count 2 2006.190.08:22:08.49#ibcon#read 5, iclass 10, count 2 2006.190.08:22:08.49#ibcon#about to read 6, iclass 10, count 2 2006.190.08:22:08.49#ibcon#read 6, iclass 10, count 2 2006.190.08:22:08.49#ibcon#end of sib2, iclass 10, count 2 2006.190.08:22:08.49#ibcon#*after write, iclass 10, count 2 2006.190.08:22:08.49#ibcon#*before return 0, iclass 10, count 2 2006.190.08:22:08.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:08.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:08.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.08:22:08.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:08.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:08.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:08.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:08.61#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:22:08.61#ibcon#first serial, iclass 10, count 0 2006.190.08:22:08.61#ibcon#enter sib2, iclass 10, count 0 2006.190.08:22:08.61#ibcon#flushed, iclass 10, count 0 2006.190.08:22:08.61#ibcon#about to write, iclass 10, count 0 2006.190.08:22:08.61#ibcon#wrote, iclass 10, count 0 2006.190.08:22:08.61#ibcon#about to read 3, iclass 10, count 0 2006.190.08:22:08.63#ibcon#read 3, iclass 10, count 0 2006.190.08:22:08.63#ibcon#about to read 4, iclass 10, count 0 2006.190.08:22:08.63#ibcon#read 4, iclass 10, count 0 2006.190.08:22:08.63#ibcon#about to read 5, iclass 10, count 0 2006.190.08:22:08.63#ibcon#read 5, iclass 10, count 0 2006.190.08:22:08.63#ibcon#about to read 6, iclass 10, count 0 2006.190.08:22:08.63#ibcon#read 6, iclass 10, count 0 2006.190.08:22:08.63#ibcon#end of sib2, iclass 10, count 0 2006.190.08:22:08.63#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:22:08.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:22:08.63#ibcon#[25=USB\r\n] 2006.190.08:22:08.63#ibcon#*before write, iclass 10, count 0 2006.190.08:22:08.63#ibcon#enter sib2, iclass 10, count 0 2006.190.08:22:08.63#ibcon#flushed, iclass 10, count 0 2006.190.08:22:08.63#ibcon#about to write, iclass 10, count 0 2006.190.08:22:08.63#ibcon#wrote, iclass 10, count 0 2006.190.08:22:08.63#ibcon#about to read 3, iclass 10, count 0 2006.190.08:22:08.66#ibcon#read 3, iclass 10, count 0 2006.190.08:22:08.66#ibcon#about to read 4, iclass 10, count 0 2006.190.08:22:08.66#ibcon#read 4, iclass 10, count 0 2006.190.08:22:08.66#ibcon#about to read 5, iclass 10, count 0 2006.190.08:22:08.66#ibcon#read 5, iclass 10, count 0 2006.190.08:22:08.66#ibcon#about to read 6, iclass 10, count 0 2006.190.08:22:08.66#ibcon#read 6, iclass 10, count 0 2006.190.08:22:08.66#ibcon#end of sib2, iclass 10, count 0 2006.190.08:22:08.66#ibcon#*after write, iclass 10, count 0 2006.190.08:22:08.66#ibcon#*before return 0, iclass 10, count 0 2006.190.08:22:08.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:08.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:08.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:22:08.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:22:08.66$vc4f8/valo=3,672.99 2006.190.08:22:08.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:22:08.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:22:08.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:08.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:08.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:08.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:08.66#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:22:08.66#ibcon#first serial, iclass 12, count 0 2006.190.08:22:08.66#ibcon#enter sib2, iclass 12, count 0 2006.190.08:22:08.66#ibcon#flushed, iclass 12, count 0 2006.190.08:22:08.66#ibcon#about to write, iclass 12, count 0 2006.190.08:22:08.66#ibcon#wrote, iclass 12, count 0 2006.190.08:22:08.66#ibcon#about to read 3, iclass 12, count 0 2006.190.08:22:08.68#ibcon#read 3, iclass 12, count 0 2006.190.08:22:08.68#ibcon#about to read 4, iclass 12, count 0 2006.190.08:22:08.68#ibcon#read 4, iclass 12, count 0 2006.190.08:22:08.68#ibcon#about to read 5, iclass 12, count 0 2006.190.08:22:08.68#ibcon#read 5, iclass 12, count 0 2006.190.08:22:08.68#ibcon#about to read 6, iclass 12, count 0 2006.190.08:22:08.68#ibcon#read 6, iclass 12, count 0 2006.190.08:22:08.68#ibcon#end of sib2, iclass 12, count 0 2006.190.08:22:08.68#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:22:08.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:22:08.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:22:08.68#ibcon#*before write, iclass 12, count 0 2006.190.08:22:08.68#ibcon#enter sib2, iclass 12, count 0 2006.190.08:22:08.68#ibcon#flushed, iclass 12, count 0 2006.190.08:22:08.68#ibcon#about to write, iclass 12, count 0 2006.190.08:22:08.68#ibcon#wrote, iclass 12, count 0 2006.190.08:22:08.68#ibcon#about to read 3, iclass 12, count 0 2006.190.08:22:08.72#ibcon#read 3, iclass 12, count 0 2006.190.08:22:08.72#ibcon#about to read 4, iclass 12, count 0 2006.190.08:22:08.72#ibcon#read 4, iclass 12, count 0 2006.190.08:22:08.72#ibcon#about to read 5, iclass 12, count 0 2006.190.08:22:08.72#ibcon#read 5, iclass 12, count 0 2006.190.08:22:08.72#ibcon#about to read 6, iclass 12, count 0 2006.190.08:22:08.72#ibcon#read 6, iclass 12, count 0 2006.190.08:22:08.72#ibcon#end of sib2, iclass 12, count 0 2006.190.08:22:08.72#ibcon#*after write, iclass 12, count 0 2006.190.08:22:08.72#ibcon#*before return 0, iclass 12, count 0 2006.190.08:22:08.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:08.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:08.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:22:08.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:22:08.72$vc4f8/va=3,6 2006.190.08:22:08.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:22:08.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:22:08.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:08.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:08.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:08.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:08.78#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:22:08.78#ibcon#first serial, iclass 14, count 2 2006.190.08:22:08.78#ibcon#enter sib2, iclass 14, count 2 2006.190.08:22:08.78#ibcon#flushed, iclass 14, count 2 2006.190.08:22:08.78#ibcon#about to write, iclass 14, count 2 2006.190.08:22:08.78#ibcon#wrote, iclass 14, count 2 2006.190.08:22:08.78#ibcon#about to read 3, iclass 14, count 2 2006.190.08:22:08.80#ibcon#read 3, iclass 14, count 2 2006.190.08:22:08.80#ibcon#about to read 4, iclass 14, count 2 2006.190.08:22:08.80#ibcon#read 4, iclass 14, count 2 2006.190.08:22:08.80#ibcon#about to read 5, iclass 14, count 2 2006.190.08:22:08.80#ibcon#read 5, iclass 14, count 2 2006.190.08:22:08.80#ibcon#about to read 6, iclass 14, count 2 2006.190.08:22:08.80#ibcon#read 6, iclass 14, count 2 2006.190.08:22:08.80#ibcon#end of sib2, iclass 14, count 2 2006.190.08:22:08.80#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:22:08.80#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:22:08.80#ibcon#[25=AT03-06\r\n] 2006.190.08:22:08.80#ibcon#*before write, iclass 14, count 2 2006.190.08:22:08.80#ibcon#enter sib2, iclass 14, count 2 2006.190.08:22:08.80#ibcon#flushed, iclass 14, count 2 2006.190.08:22:08.80#ibcon#about to write, iclass 14, count 2 2006.190.08:22:08.80#ibcon#wrote, iclass 14, count 2 2006.190.08:22:08.80#ibcon#about to read 3, iclass 14, count 2 2006.190.08:22:08.83#ibcon#read 3, iclass 14, count 2 2006.190.08:22:08.83#ibcon#about to read 4, iclass 14, count 2 2006.190.08:22:08.83#ibcon#read 4, iclass 14, count 2 2006.190.08:22:08.83#ibcon#about to read 5, iclass 14, count 2 2006.190.08:22:08.83#ibcon#read 5, iclass 14, count 2 2006.190.08:22:08.83#ibcon#about to read 6, iclass 14, count 2 2006.190.08:22:08.83#ibcon#read 6, iclass 14, count 2 2006.190.08:22:08.83#ibcon#end of sib2, iclass 14, count 2 2006.190.08:22:08.83#ibcon#*after write, iclass 14, count 2 2006.190.08:22:08.83#ibcon#*before return 0, iclass 14, count 2 2006.190.08:22:08.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:08.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:08.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:22:08.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:08.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:08.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:08.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:08.95#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:22:08.95#ibcon#first serial, iclass 14, count 0 2006.190.08:22:08.95#ibcon#enter sib2, iclass 14, count 0 2006.190.08:22:08.95#ibcon#flushed, iclass 14, count 0 2006.190.08:22:08.95#ibcon#about to write, iclass 14, count 0 2006.190.08:22:08.95#ibcon#wrote, iclass 14, count 0 2006.190.08:22:08.95#ibcon#about to read 3, iclass 14, count 0 2006.190.08:22:08.97#ibcon#read 3, iclass 14, count 0 2006.190.08:22:08.97#ibcon#about to read 4, iclass 14, count 0 2006.190.08:22:08.97#ibcon#read 4, iclass 14, count 0 2006.190.08:22:08.97#ibcon#about to read 5, iclass 14, count 0 2006.190.08:22:08.97#ibcon#read 5, iclass 14, count 0 2006.190.08:22:08.97#ibcon#about to read 6, iclass 14, count 0 2006.190.08:22:08.97#ibcon#read 6, iclass 14, count 0 2006.190.08:22:08.97#ibcon#end of sib2, iclass 14, count 0 2006.190.08:22:08.97#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:22:08.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:22:08.97#ibcon#[25=USB\r\n] 2006.190.08:22:08.97#ibcon#*before write, iclass 14, count 0 2006.190.08:22:08.97#ibcon#enter sib2, iclass 14, count 0 2006.190.08:22:08.97#ibcon#flushed, iclass 14, count 0 2006.190.08:22:08.97#ibcon#about to write, iclass 14, count 0 2006.190.08:22:08.97#ibcon#wrote, iclass 14, count 0 2006.190.08:22:08.97#ibcon#about to read 3, iclass 14, count 0 2006.190.08:22:09.00#ibcon#read 3, iclass 14, count 0 2006.190.08:22:09.00#ibcon#about to read 4, iclass 14, count 0 2006.190.08:22:09.00#ibcon#read 4, iclass 14, count 0 2006.190.08:22:09.00#ibcon#about to read 5, iclass 14, count 0 2006.190.08:22:09.00#ibcon#read 5, iclass 14, count 0 2006.190.08:22:09.00#ibcon#about to read 6, iclass 14, count 0 2006.190.08:22:09.00#ibcon#read 6, iclass 14, count 0 2006.190.08:22:09.00#ibcon#end of sib2, iclass 14, count 0 2006.190.08:22:09.00#ibcon#*after write, iclass 14, count 0 2006.190.08:22:09.00#ibcon#*before return 0, iclass 14, count 0 2006.190.08:22:09.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:09.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:09.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:22:09.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:22:09.00$vc4f8/valo=4,832.99 2006.190.08:22:09.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:22:09.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:22:09.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:09.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:09.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:09.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:09.00#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:22:09.00#ibcon#first serial, iclass 16, count 0 2006.190.08:22:09.00#ibcon#enter sib2, iclass 16, count 0 2006.190.08:22:09.00#ibcon#flushed, iclass 16, count 0 2006.190.08:22:09.00#ibcon#about to write, iclass 16, count 0 2006.190.08:22:09.00#ibcon#wrote, iclass 16, count 0 2006.190.08:22:09.00#ibcon#about to read 3, iclass 16, count 0 2006.190.08:22:09.02#ibcon#read 3, iclass 16, count 0 2006.190.08:22:09.02#ibcon#about to read 4, iclass 16, count 0 2006.190.08:22:09.02#ibcon#read 4, iclass 16, count 0 2006.190.08:22:09.02#ibcon#about to read 5, iclass 16, count 0 2006.190.08:22:09.02#ibcon#read 5, iclass 16, count 0 2006.190.08:22:09.02#ibcon#about to read 6, iclass 16, count 0 2006.190.08:22:09.02#ibcon#read 6, iclass 16, count 0 2006.190.08:22:09.02#ibcon#end of sib2, iclass 16, count 0 2006.190.08:22:09.02#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:22:09.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:22:09.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:22:09.02#ibcon#*before write, iclass 16, count 0 2006.190.08:22:09.02#ibcon#enter sib2, iclass 16, count 0 2006.190.08:22:09.02#ibcon#flushed, iclass 16, count 0 2006.190.08:22:09.02#ibcon#about to write, iclass 16, count 0 2006.190.08:22:09.02#ibcon#wrote, iclass 16, count 0 2006.190.08:22:09.02#ibcon#about to read 3, iclass 16, count 0 2006.190.08:22:09.06#ibcon#read 3, iclass 16, count 0 2006.190.08:22:09.06#ibcon#about to read 4, iclass 16, count 0 2006.190.08:22:09.06#ibcon#read 4, iclass 16, count 0 2006.190.08:22:09.06#ibcon#about to read 5, iclass 16, count 0 2006.190.08:22:09.06#ibcon#read 5, iclass 16, count 0 2006.190.08:22:09.06#ibcon#about to read 6, iclass 16, count 0 2006.190.08:22:09.06#ibcon#read 6, iclass 16, count 0 2006.190.08:22:09.06#ibcon#end of sib2, iclass 16, count 0 2006.190.08:22:09.06#ibcon#*after write, iclass 16, count 0 2006.190.08:22:09.06#ibcon#*before return 0, iclass 16, count 0 2006.190.08:22:09.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:09.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:09.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:22:09.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:22:09.06$vc4f8/va=4,7 2006.190.08:22:09.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.08:22:09.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.08:22:09.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:09.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:09.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:09.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:09.12#ibcon#enter wrdev, iclass 18, count 2 2006.190.08:22:09.12#ibcon#first serial, iclass 18, count 2 2006.190.08:22:09.12#ibcon#enter sib2, iclass 18, count 2 2006.190.08:22:09.12#ibcon#flushed, iclass 18, count 2 2006.190.08:22:09.12#ibcon#about to write, iclass 18, count 2 2006.190.08:22:09.12#ibcon#wrote, iclass 18, count 2 2006.190.08:22:09.12#ibcon#about to read 3, iclass 18, count 2 2006.190.08:22:09.14#ibcon#read 3, iclass 18, count 2 2006.190.08:22:09.14#ibcon#about to read 4, iclass 18, count 2 2006.190.08:22:09.14#ibcon#read 4, iclass 18, count 2 2006.190.08:22:09.14#ibcon#about to read 5, iclass 18, count 2 2006.190.08:22:09.14#ibcon#read 5, iclass 18, count 2 2006.190.08:22:09.14#ibcon#about to read 6, iclass 18, count 2 2006.190.08:22:09.14#ibcon#read 6, iclass 18, count 2 2006.190.08:22:09.14#ibcon#end of sib2, iclass 18, count 2 2006.190.08:22:09.14#ibcon#*mode == 0, iclass 18, count 2 2006.190.08:22:09.14#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.08:22:09.14#ibcon#[25=AT04-07\r\n] 2006.190.08:22:09.14#ibcon#*before write, iclass 18, count 2 2006.190.08:22:09.14#ibcon#enter sib2, iclass 18, count 2 2006.190.08:22:09.14#ibcon#flushed, iclass 18, count 2 2006.190.08:22:09.14#ibcon#about to write, iclass 18, count 2 2006.190.08:22:09.14#ibcon#wrote, iclass 18, count 2 2006.190.08:22:09.14#ibcon#about to read 3, iclass 18, count 2 2006.190.08:22:09.17#ibcon#read 3, iclass 18, count 2 2006.190.08:22:09.17#ibcon#about to read 4, iclass 18, count 2 2006.190.08:22:09.17#ibcon#read 4, iclass 18, count 2 2006.190.08:22:09.17#ibcon#about to read 5, iclass 18, count 2 2006.190.08:22:09.17#ibcon#read 5, iclass 18, count 2 2006.190.08:22:09.17#ibcon#about to read 6, iclass 18, count 2 2006.190.08:22:09.17#ibcon#read 6, iclass 18, count 2 2006.190.08:22:09.17#ibcon#end of sib2, iclass 18, count 2 2006.190.08:22:09.17#ibcon#*after write, iclass 18, count 2 2006.190.08:22:09.17#ibcon#*before return 0, iclass 18, count 2 2006.190.08:22:09.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:09.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:09.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.08:22:09.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:09.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:09.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:09.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:09.29#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:22:09.29#ibcon#first serial, iclass 18, count 0 2006.190.08:22:09.29#ibcon#enter sib2, iclass 18, count 0 2006.190.08:22:09.29#ibcon#flushed, iclass 18, count 0 2006.190.08:22:09.29#ibcon#about to write, iclass 18, count 0 2006.190.08:22:09.29#ibcon#wrote, iclass 18, count 0 2006.190.08:22:09.29#ibcon#about to read 3, iclass 18, count 0 2006.190.08:22:09.31#ibcon#read 3, iclass 18, count 0 2006.190.08:22:09.31#ibcon#about to read 4, iclass 18, count 0 2006.190.08:22:09.31#ibcon#read 4, iclass 18, count 0 2006.190.08:22:09.31#ibcon#about to read 5, iclass 18, count 0 2006.190.08:22:09.31#ibcon#read 5, iclass 18, count 0 2006.190.08:22:09.31#ibcon#about to read 6, iclass 18, count 0 2006.190.08:22:09.31#ibcon#read 6, iclass 18, count 0 2006.190.08:22:09.31#ibcon#end of sib2, iclass 18, count 0 2006.190.08:22:09.31#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:22:09.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:22:09.31#ibcon#[25=USB\r\n] 2006.190.08:22:09.31#ibcon#*before write, iclass 18, count 0 2006.190.08:22:09.31#ibcon#enter sib2, iclass 18, count 0 2006.190.08:22:09.31#ibcon#flushed, iclass 18, count 0 2006.190.08:22:09.31#ibcon#about to write, iclass 18, count 0 2006.190.08:22:09.31#ibcon#wrote, iclass 18, count 0 2006.190.08:22:09.31#ibcon#about to read 3, iclass 18, count 0 2006.190.08:22:09.34#ibcon#read 3, iclass 18, count 0 2006.190.08:22:09.34#ibcon#about to read 4, iclass 18, count 0 2006.190.08:22:09.34#ibcon#read 4, iclass 18, count 0 2006.190.08:22:09.34#ibcon#about to read 5, iclass 18, count 0 2006.190.08:22:09.34#ibcon#read 5, iclass 18, count 0 2006.190.08:22:09.34#ibcon#about to read 6, iclass 18, count 0 2006.190.08:22:09.34#ibcon#read 6, iclass 18, count 0 2006.190.08:22:09.34#ibcon#end of sib2, iclass 18, count 0 2006.190.08:22:09.34#ibcon#*after write, iclass 18, count 0 2006.190.08:22:09.34#ibcon#*before return 0, iclass 18, count 0 2006.190.08:22:09.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:09.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:09.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:22:09.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:22:09.34$vc4f8/valo=5,652.99 2006.190.08:22:09.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.08:22:09.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.08:22:09.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:09.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:09.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:09.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:09.34#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:22:09.34#ibcon#first serial, iclass 20, count 0 2006.190.08:22:09.34#ibcon#enter sib2, iclass 20, count 0 2006.190.08:22:09.34#ibcon#flushed, iclass 20, count 0 2006.190.08:22:09.34#ibcon#about to write, iclass 20, count 0 2006.190.08:22:09.34#ibcon#wrote, iclass 20, count 0 2006.190.08:22:09.34#ibcon#about to read 3, iclass 20, count 0 2006.190.08:22:09.36#ibcon#read 3, iclass 20, count 0 2006.190.08:22:09.36#ibcon#about to read 4, iclass 20, count 0 2006.190.08:22:09.36#ibcon#read 4, iclass 20, count 0 2006.190.08:22:09.36#ibcon#about to read 5, iclass 20, count 0 2006.190.08:22:09.36#ibcon#read 5, iclass 20, count 0 2006.190.08:22:09.36#ibcon#about to read 6, iclass 20, count 0 2006.190.08:22:09.36#ibcon#read 6, iclass 20, count 0 2006.190.08:22:09.36#ibcon#end of sib2, iclass 20, count 0 2006.190.08:22:09.36#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:22:09.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:22:09.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:22:09.36#ibcon#*before write, iclass 20, count 0 2006.190.08:22:09.36#ibcon#enter sib2, iclass 20, count 0 2006.190.08:22:09.36#ibcon#flushed, iclass 20, count 0 2006.190.08:22:09.36#ibcon#about to write, iclass 20, count 0 2006.190.08:22:09.36#ibcon#wrote, iclass 20, count 0 2006.190.08:22:09.36#ibcon#about to read 3, iclass 20, count 0 2006.190.08:22:09.40#ibcon#read 3, iclass 20, count 0 2006.190.08:22:09.40#ibcon#about to read 4, iclass 20, count 0 2006.190.08:22:09.40#ibcon#read 4, iclass 20, count 0 2006.190.08:22:09.40#ibcon#about to read 5, iclass 20, count 0 2006.190.08:22:09.40#ibcon#read 5, iclass 20, count 0 2006.190.08:22:09.40#ibcon#about to read 6, iclass 20, count 0 2006.190.08:22:09.40#ibcon#read 6, iclass 20, count 0 2006.190.08:22:09.40#ibcon#end of sib2, iclass 20, count 0 2006.190.08:22:09.40#ibcon#*after write, iclass 20, count 0 2006.190.08:22:09.40#ibcon#*before return 0, iclass 20, count 0 2006.190.08:22:09.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:09.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:09.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:22:09.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:22:09.40$vc4f8/va=5,7 2006.190.08:22:09.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.08:22:09.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.08:22:09.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:09.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:09.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:09.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:09.46#ibcon#enter wrdev, iclass 22, count 2 2006.190.08:22:09.46#ibcon#first serial, iclass 22, count 2 2006.190.08:22:09.46#ibcon#enter sib2, iclass 22, count 2 2006.190.08:22:09.46#ibcon#flushed, iclass 22, count 2 2006.190.08:22:09.46#ibcon#about to write, iclass 22, count 2 2006.190.08:22:09.46#ibcon#wrote, iclass 22, count 2 2006.190.08:22:09.46#ibcon#about to read 3, iclass 22, count 2 2006.190.08:22:09.48#ibcon#read 3, iclass 22, count 2 2006.190.08:22:09.48#ibcon#about to read 4, iclass 22, count 2 2006.190.08:22:09.48#ibcon#read 4, iclass 22, count 2 2006.190.08:22:09.48#ibcon#about to read 5, iclass 22, count 2 2006.190.08:22:09.48#ibcon#read 5, iclass 22, count 2 2006.190.08:22:09.48#ibcon#about to read 6, iclass 22, count 2 2006.190.08:22:09.48#ibcon#read 6, iclass 22, count 2 2006.190.08:22:09.48#ibcon#end of sib2, iclass 22, count 2 2006.190.08:22:09.48#ibcon#*mode == 0, iclass 22, count 2 2006.190.08:22:09.48#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.08:22:09.48#ibcon#[25=AT05-07\r\n] 2006.190.08:22:09.48#ibcon#*before write, iclass 22, count 2 2006.190.08:22:09.48#ibcon#enter sib2, iclass 22, count 2 2006.190.08:22:09.48#ibcon#flushed, iclass 22, count 2 2006.190.08:22:09.48#ibcon#about to write, iclass 22, count 2 2006.190.08:22:09.48#ibcon#wrote, iclass 22, count 2 2006.190.08:22:09.48#ibcon#about to read 3, iclass 22, count 2 2006.190.08:22:09.51#ibcon#read 3, iclass 22, count 2 2006.190.08:22:09.51#ibcon#about to read 4, iclass 22, count 2 2006.190.08:22:09.51#ibcon#read 4, iclass 22, count 2 2006.190.08:22:09.51#ibcon#about to read 5, iclass 22, count 2 2006.190.08:22:09.51#ibcon#read 5, iclass 22, count 2 2006.190.08:22:09.51#ibcon#about to read 6, iclass 22, count 2 2006.190.08:22:09.51#ibcon#read 6, iclass 22, count 2 2006.190.08:22:09.51#ibcon#end of sib2, iclass 22, count 2 2006.190.08:22:09.51#ibcon#*after write, iclass 22, count 2 2006.190.08:22:09.51#ibcon#*before return 0, iclass 22, count 2 2006.190.08:22:09.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:09.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:09.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.08:22:09.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:09.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:09.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:09.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:09.63#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:22:09.63#ibcon#first serial, iclass 22, count 0 2006.190.08:22:09.63#ibcon#enter sib2, iclass 22, count 0 2006.190.08:22:09.63#ibcon#flushed, iclass 22, count 0 2006.190.08:22:09.63#ibcon#about to write, iclass 22, count 0 2006.190.08:22:09.63#ibcon#wrote, iclass 22, count 0 2006.190.08:22:09.63#ibcon#about to read 3, iclass 22, count 0 2006.190.08:22:09.65#ibcon#read 3, iclass 22, count 0 2006.190.08:22:09.65#ibcon#about to read 4, iclass 22, count 0 2006.190.08:22:09.65#ibcon#read 4, iclass 22, count 0 2006.190.08:22:09.65#ibcon#about to read 5, iclass 22, count 0 2006.190.08:22:09.65#ibcon#read 5, iclass 22, count 0 2006.190.08:22:09.65#ibcon#about to read 6, iclass 22, count 0 2006.190.08:22:09.65#ibcon#read 6, iclass 22, count 0 2006.190.08:22:09.65#ibcon#end of sib2, iclass 22, count 0 2006.190.08:22:09.65#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:22:09.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:22:09.65#ibcon#[25=USB\r\n] 2006.190.08:22:09.65#ibcon#*before write, iclass 22, count 0 2006.190.08:22:09.65#ibcon#enter sib2, iclass 22, count 0 2006.190.08:22:09.65#ibcon#flushed, iclass 22, count 0 2006.190.08:22:09.65#ibcon#about to write, iclass 22, count 0 2006.190.08:22:09.65#ibcon#wrote, iclass 22, count 0 2006.190.08:22:09.65#ibcon#about to read 3, iclass 22, count 0 2006.190.08:22:09.68#ibcon#read 3, iclass 22, count 0 2006.190.08:22:09.68#ibcon#about to read 4, iclass 22, count 0 2006.190.08:22:09.68#ibcon#read 4, iclass 22, count 0 2006.190.08:22:09.68#ibcon#about to read 5, iclass 22, count 0 2006.190.08:22:09.68#ibcon#read 5, iclass 22, count 0 2006.190.08:22:09.68#ibcon#about to read 6, iclass 22, count 0 2006.190.08:22:09.68#ibcon#read 6, iclass 22, count 0 2006.190.08:22:09.68#ibcon#end of sib2, iclass 22, count 0 2006.190.08:22:09.68#ibcon#*after write, iclass 22, count 0 2006.190.08:22:09.68#ibcon#*before return 0, iclass 22, count 0 2006.190.08:22:09.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:09.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:09.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:22:09.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:22:09.68$vc4f8/valo=6,772.99 2006.190.08:22:09.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.08:22:09.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.08:22:09.68#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:09.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:22:09.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:22:09.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:22:09.68#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:22:09.68#ibcon#first serial, iclass 25, count 0 2006.190.08:22:09.68#ibcon#enter sib2, iclass 25, count 0 2006.190.08:22:09.68#ibcon#flushed, iclass 25, count 0 2006.190.08:22:09.68#ibcon#about to write, iclass 25, count 0 2006.190.08:22:09.68#ibcon#wrote, iclass 25, count 0 2006.190.08:22:09.68#ibcon#about to read 3, iclass 25, count 0 2006.190.08:22:09.69#abcon#<5=/04 1.9 4.4 24.411001012.2\r\n> 2006.190.08:22:09.70#ibcon#read 3, iclass 25, count 0 2006.190.08:22:09.70#ibcon#about to read 4, iclass 25, count 0 2006.190.08:22:09.70#ibcon#read 4, iclass 25, count 0 2006.190.08:22:09.70#ibcon#about to read 5, iclass 25, count 0 2006.190.08:22:09.70#ibcon#read 5, iclass 25, count 0 2006.190.08:22:09.70#ibcon#about to read 6, iclass 25, count 0 2006.190.08:22:09.70#ibcon#read 6, iclass 25, count 0 2006.190.08:22:09.70#ibcon#end of sib2, iclass 25, count 0 2006.190.08:22:09.70#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:22:09.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:22:09.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:22:09.70#ibcon#*before write, iclass 25, count 0 2006.190.08:22:09.70#ibcon#enter sib2, iclass 25, count 0 2006.190.08:22:09.70#ibcon#flushed, iclass 25, count 0 2006.190.08:22:09.70#ibcon#about to write, iclass 25, count 0 2006.190.08:22:09.70#ibcon#wrote, iclass 25, count 0 2006.190.08:22:09.70#ibcon#about to read 3, iclass 25, count 0 2006.190.08:22:09.71#abcon#{5=INTERFACE CLEAR} 2006.190.08:22:09.74#ibcon#read 3, iclass 25, count 0 2006.190.08:22:09.74#ibcon#about to read 4, iclass 25, count 0 2006.190.08:22:09.74#ibcon#read 4, iclass 25, count 0 2006.190.08:22:09.74#ibcon#about to read 5, iclass 25, count 0 2006.190.08:22:09.74#ibcon#read 5, iclass 25, count 0 2006.190.08:22:09.74#ibcon#about to read 6, iclass 25, count 0 2006.190.08:22:09.74#ibcon#read 6, iclass 25, count 0 2006.190.08:22:09.74#ibcon#end of sib2, iclass 25, count 0 2006.190.08:22:09.74#ibcon#*after write, iclass 25, count 0 2006.190.08:22:09.74#ibcon#*before return 0, iclass 25, count 0 2006.190.08:22:09.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:22:09.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:22:09.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:22:09.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:22:09.74$vc4f8/va=6,6 2006.190.08:22:09.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.190.08:22:09.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.190.08:22:09.74#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:09.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:22:09.77#abcon#[5=S1D000X0/0*\r\n] 2006.190.08:22:09.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:22:09.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:22:09.80#ibcon#enter wrdev, iclass 29, count 2 2006.190.08:22:09.80#ibcon#first serial, iclass 29, count 2 2006.190.08:22:09.80#ibcon#enter sib2, iclass 29, count 2 2006.190.08:22:09.80#ibcon#flushed, iclass 29, count 2 2006.190.08:22:09.80#ibcon#about to write, iclass 29, count 2 2006.190.08:22:09.80#ibcon#wrote, iclass 29, count 2 2006.190.08:22:09.80#ibcon#about to read 3, iclass 29, count 2 2006.190.08:22:09.82#ibcon#read 3, iclass 29, count 2 2006.190.08:22:09.82#ibcon#about to read 4, iclass 29, count 2 2006.190.08:22:09.82#ibcon#read 4, iclass 29, count 2 2006.190.08:22:09.82#ibcon#about to read 5, iclass 29, count 2 2006.190.08:22:09.82#ibcon#read 5, iclass 29, count 2 2006.190.08:22:09.82#ibcon#about to read 6, iclass 29, count 2 2006.190.08:22:09.82#ibcon#read 6, iclass 29, count 2 2006.190.08:22:09.82#ibcon#end of sib2, iclass 29, count 2 2006.190.08:22:09.82#ibcon#*mode == 0, iclass 29, count 2 2006.190.08:22:09.82#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.190.08:22:09.82#ibcon#[25=AT06-06\r\n] 2006.190.08:22:09.82#ibcon#*before write, iclass 29, count 2 2006.190.08:22:09.82#ibcon#enter sib2, iclass 29, count 2 2006.190.08:22:09.82#ibcon#flushed, iclass 29, count 2 2006.190.08:22:09.82#ibcon#about to write, iclass 29, count 2 2006.190.08:22:09.82#ibcon#wrote, iclass 29, count 2 2006.190.08:22:09.82#ibcon#about to read 3, iclass 29, count 2 2006.190.08:22:09.85#ibcon#read 3, iclass 29, count 2 2006.190.08:22:09.85#ibcon#about to read 4, iclass 29, count 2 2006.190.08:22:09.85#ibcon#read 4, iclass 29, count 2 2006.190.08:22:09.85#ibcon#about to read 5, iclass 29, count 2 2006.190.08:22:09.85#ibcon#read 5, iclass 29, count 2 2006.190.08:22:09.85#ibcon#about to read 6, iclass 29, count 2 2006.190.08:22:09.85#ibcon#read 6, iclass 29, count 2 2006.190.08:22:09.85#ibcon#end of sib2, iclass 29, count 2 2006.190.08:22:09.85#ibcon#*after write, iclass 29, count 2 2006.190.08:22:09.85#ibcon#*before return 0, iclass 29, count 2 2006.190.08:22:09.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:22:09.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.190.08:22:09.85#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.190.08:22:09.85#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:09.85#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:22:09.97#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:22:09.97#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:22:09.97#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:22:09.97#ibcon#first serial, iclass 29, count 0 2006.190.08:22:09.97#ibcon#enter sib2, iclass 29, count 0 2006.190.08:22:09.97#ibcon#flushed, iclass 29, count 0 2006.190.08:22:09.97#ibcon#about to write, iclass 29, count 0 2006.190.08:22:09.97#ibcon#wrote, iclass 29, count 0 2006.190.08:22:09.97#ibcon#about to read 3, iclass 29, count 0 2006.190.08:22:09.99#ibcon#read 3, iclass 29, count 0 2006.190.08:22:09.99#ibcon#about to read 4, iclass 29, count 0 2006.190.08:22:09.99#ibcon#read 4, iclass 29, count 0 2006.190.08:22:09.99#ibcon#about to read 5, iclass 29, count 0 2006.190.08:22:09.99#ibcon#read 5, iclass 29, count 0 2006.190.08:22:09.99#ibcon#about to read 6, iclass 29, count 0 2006.190.08:22:09.99#ibcon#read 6, iclass 29, count 0 2006.190.08:22:09.99#ibcon#end of sib2, iclass 29, count 0 2006.190.08:22:09.99#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:22:09.99#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:22:09.99#ibcon#[25=USB\r\n] 2006.190.08:22:09.99#ibcon#*before write, iclass 29, count 0 2006.190.08:22:09.99#ibcon#enter sib2, iclass 29, count 0 2006.190.08:22:09.99#ibcon#flushed, iclass 29, count 0 2006.190.08:22:09.99#ibcon#about to write, iclass 29, count 0 2006.190.08:22:09.99#ibcon#wrote, iclass 29, count 0 2006.190.08:22:09.99#ibcon#about to read 3, iclass 29, count 0 2006.190.08:22:10.02#ibcon#read 3, iclass 29, count 0 2006.190.08:22:10.02#ibcon#about to read 4, iclass 29, count 0 2006.190.08:22:10.02#ibcon#read 4, iclass 29, count 0 2006.190.08:22:10.02#ibcon#about to read 5, iclass 29, count 0 2006.190.08:22:10.02#ibcon#read 5, iclass 29, count 0 2006.190.08:22:10.02#ibcon#about to read 6, iclass 29, count 0 2006.190.08:22:10.02#ibcon#read 6, iclass 29, count 0 2006.190.08:22:10.02#ibcon#end of sib2, iclass 29, count 0 2006.190.08:22:10.02#ibcon#*after write, iclass 29, count 0 2006.190.08:22:10.02#ibcon#*before return 0, iclass 29, count 0 2006.190.08:22:10.02#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:22:10.02#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.190.08:22:10.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:22:10.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:22:10.02$vc4f8/valo=7,832.99 2006.190.08:22:10.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.190.08:22:10.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.190.08:22:10.02#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:10.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:22:10.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:22:10.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:22:10.02#ibcon#enter wrdev, iclass 32, count 0 2006.190.08:22:10.02#ibcon#first serial, iclass 32, count 0 2006.190.08:22:10.02#ibcon#enter sib2, iclass 32, count 0 2006.190.08:22:10.02#ibcon#flushed, iclass 32, count 0 2006.190.08:22:10.02#ibcon#about to write, iclass 32, count 0 2006.190.08:22:10.02#ibcon#wrote, iclass 32, count 0 2006.190.08:22:10.02#ibcon#about to read 3, iclass 32, count 0 2006.190.08:22:10.04#ibcon#read 3, iclass 32, count 0 2006.190.08:22:10.04#ibcon#about to read 4, iclass 32, count 0 2006.190.08:22:10.04#ibcon#read 4, iclass 32, count 0 2006.190.08:22:10.04#ibcon#about to read 5, iclass 32, count 0 2006.190.08:22:10.04#ibcon#read 5, iclass 32, count 0 2006.190.08:22:10.04#ibcon#about to read 6, iclass 32, count 0 2006.190.08:22:10.04#ibcon#read 6, iclass 32, count 0 2006.190.08:22:10.04#ibcon#end of sib2, iclass 32, count 0 2006.190.08:22:10.04#ibcon#*mode == 0, iclass 32, count 0 2006.190.08:22:10.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.190.08:22:10.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:22:10.04#ibcon#*before write, iclass 32, count 0 2006.190.08:22:10.04#ibcon#enter sib2, iclass 32, count 0 2006.190.08:22:10.04#ibcon#flushed, iclass 32, count 0 2006.190.08:22:10.04#ibcon#about to write, iclass 32, count 0 2006.190.08:22:10.04#ibcon#wrote, iclass 32, count 0 2006.190.08:22:10.04#ibcon#about to read 3, iclass 32, count 0 2006.190.08:22:10.08#ibcon#read 3, iclass 32, count 0 2006.190.08:22:10.08#ibcon#about to read 4, iclass 32, count 0 2006.190.08:22:10.08#ibcon#read 4, iclass 32, count 0 2006.190.08:22:10.08#ibcon#about to read 5, iclass 32, count 0 2006.190.08:22:10.08#ibcon#read 5, iclass 32, count 0 2006.190.08:22:10.08#ibcon#about to read 6, iclass 32, count 0 2006.190.08:22:10.08#ibcon#read 6, iclass 32, count 0 2006.190.08:22:10.08#ibcon#end of sib2, iclass 32, count 0 2006.190.08:22:10.08#ibcon#*after write, iclass 32, count 0 2006.190.08:22:10.08#ibcon#*before return 0, iclass 32, count 0 2006.190.08:22:10.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:22:10.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.190.08:22:10.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.190.08:22:10.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.190.08:22:10.08$vc4f8/va=7,6 2006.190.08:22:10.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.190.08:22:10.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.190.08:22:10.08#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:10.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:22:10.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:22:10.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:22:10.14#ibcon#enter wrdev, iclass 34, count 2 2006.190.08:22:10.14#ibcon#first serial, iclass 34, count 2 2006.190.08:22:10.14#ibcon#enter sib2, iclass 34, count 2 2006.190.08:22:10.14#ibcon#flushed, iclass 34, count 2 2006.190.08:22:10.14#ibcon#about to write, iclass 34, count 2 2006.190.08:22:10.14#ibcon#wrote, iclass 34, count 2 2006.190.08:22:10.14#ibcon#about to read 3, iclass 34, count 2 2006.190.08:22:10.16#ibcon#read 3, iclass 34, count 2 2006.190.08:22:10.16#ibcon#about to read 4, iclass 34, count 2 2006.190.08:22:10.16#ibcon#read 4, iclass 34, count 2 2006.190.08:22:10.16#ibcon#about to read 5, iclass 34, count 2 2006.190.08:22:10.16#ibcon#read 5, iclass 34, count 2 2006.190.08:22:10.16#ibcon#about to read 6, iclass 34, count 2 2006.190.08:22:10.16#ibcon#read 6, iclass 34, count 2 2006.190.08:22:10.16#ibcon#end of sib2, iclass 34, count 2 2006.190.08:22:10.16#ibcon#*mode == 0, iclass 34, count 2 2006.190.08:22:10.16#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.190.08:22:10.16#ibcon#[25=AT07-06\r\n] 2006.190.08:22:10.16#ibcon#*before write, iclass 34, count 2 2006.190.08:22:10.16#ibcon#enter sib2, iclass 34, count 2 2006.190.08:22:10.16#ibcon#flushed, iclass 34, count 2 2006.190.08:22:10.16#ibcon#about to write, iclass 34, count 2 2006.190.08:22:10.16#ibcon#wrote, iclass 34, count 2 2006.190.08:22:10.16#ibcon#about to read 3, iclass 34, count 2 2006.190.08:22:10.19#ibcon#read 3, iclass 34, count 2 2006.190.08:22:10.19#ibcon#about to read 4, iclass 34, count 2 2006.190.08:22:10.19#ibcon#read 4, iclass 34, count 2 2006.190.08:22:10.19#ibcon#about to read 5, iclass 34, count 2 2006.190.08:22:10.19#ibcon#read 5, iclass 34, count 2 2006.190.08:22:10.19#ibcon#about to read 6, iclass 34, count 2 2006.190.08:22:10.19#ibcon#read 6, iclass 34, count 2 2006.190.08:22:10.19#ibcon#end of sib2, iclass 34, count 2 2006.190.08:22:10.19#ibcon#*after write, iclass 34, count 2 2006.190.08:22:10.19#ibcon#*before return 0, iclass 34, count 2 2006.190.08:22:10.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:22:10.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.190.08:22:10.19#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.190.08:22:10.19#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:10.19#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:22:10.31#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:22:10.31#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:22:10.31#ibcon#enter wrdev, iclass 34, count 0 2006.190.08:22:10.31#ibcon#first serial, iclass 34, count 0 2006.190.08:22:10.31#ibcon#enter sib2, iclass 34, count 0 2006.190.08:22:10.31#ibcon#flushed, iclass 34, count 0 2006.190.08:22:10.31#ibcon#about to write, iclass 34, count 0 2006.190.08:22:10.31#ibcon#wrote, iclass 34, count 0 2006.190.08:22:10.31#ibcon#about to read 3, iclass 34, count 0 2006.190.08:22:10.33#ibcon#read 3, iclass 34, count 0 2006.190.08:22:10.33#ibcon#about to read 4, iclass 34, count 0 2006.190.08:22:10.33#ibcon#read 4, iclass 34, count 0 2006.190.08:22:10.33#ibcon#about to read 5, iclass 34, count 0 2006.190.08:22:10.33#ibcon#read 5, iclass 34, count 0 2006.190.08:22:10.33#ibcon#about to read 6, iclass 34, count 0 2006.190.08:22:10.33#ibcon#read 6, iclass 34, count 0 2006.190.08:22:10.33#ibcon#end of sib2, iclass 34, count 0 2006.190.08:22:10.33#ibcon#*mode == 0, iclass 34, count 0 2006.190.08:22:10.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.190.08:22:10.33#ibcon#[25=USB\r\n] 2006.190.08:22:10.33#ibcon#*before write, iclass 34, count 0 2006.190.08:22:10.33#ibcon#enter sib2, iclass 34, count 0 2006.190.08:22:10.33#ibcon#flushed, iclass 34, count 0 2006.190.08:22:10.33#ibcon#about to write, iclass 34, count 0 2006.190.08:22:10.33#ibcon#wrote, iclass 34, count 0 2006.190.08:22:10.33#ibcon#about to read 3, iclass 34, count 0 2006.190.08:22:10.36#ibcon#read 3, iclass 34, count 0 2006.190.08:22:10.36#ibcon#about to read 4, iclass 34, count 0 2006.190.08:22:10.36#ibcon#read 4, iclass 34, count 0 2006.190.08:22:10.36#ibcon#about to read 5, iclass 34, count 0 2006.190.08:22:10.36#ibcon#read 5, iclass 34, count 0 2006.190.08:22:10.36#ibcon#about to read 6, iclass 34, count 0 2006.190.08:22:10.36#ibcon#read 6, iclass 34, count 0 2006.190.08:22:10.36#ibcon#end of sib2, iclass 34, count 0 2006.190.08:22:10.36#ibcon#*after write, iclass 34, count 0 2006.190.08:22:10.36#ibcon#*before return 0, iclass 34, count 0 2006.190.08:22:10.36#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:22:10.36#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.190.08:22:10.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.190.08:22:10.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.190.08:22:10.36$vc4f8/valo=8,852.99 2006.190.08:22:10.36#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.190.08:22:10.36#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.190.08:22:10.36#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:10.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:22:10.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:22:10.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:22:10.36#ibcon#enter wrdev, iclass 36, count 0 2006.190.08:22:10.36#ibcon#first serial, iclass 36, count 0 2006.190.08:22:10.36#ibcon#enter sib2, iclass 36, count 0 2006.190.08:22:10.36#ibcon#flushed, iclass 36, count 0 2006.190.08:22:10.36#ibcon#about to write, iclass 36, count 0 2006.190.08:22:10.36#ibcon#wrote, iclass 36, count 0 2006.190.08:22:10.36#ibcon#about to read 3, iclass 36, count 0 2006.190.08:22:10.38#ibcon#read 3, iclass 36, count 0 2006.190.08:22:10.38#ibcon#about to read 4, iclass 36, count 0 2006.190.08:22:10.38#ibcon#read 4, iclass 36, count 0 2006.190.08:22:10.38#ibcon#about to read 5, iclass 36, count 0 2006.190.08:22:10.38#ibcon#read 5, iclass 36, count 0 2006.190.08:22:10.38#ibcon#about to read 6, iclass 36, count 0 2006.190.08:22:10.38#ibcon#read 6, iclass 36, count 0 2006.190.08:22:10.38#ibcon#end of sib2, iclass 36, count 0 2006.190.08:22:10.38#ibcon#*mode == 0, iclass 36, count 0 2006.190.08:22:10.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.190.08:22:10.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:22:10.38#ibcon#*before write, iclass 36, count 0 2006.190.08:22:10.38#ibcon#enter sib2, iclass 36, count 0 2006.190.08:22:10.38#ibcon#flushed, iclass 36, count 0 2006.190.08:22:10.38#ibcon#about to write, iclass 36, count 0 2006.190.08:22:10.38#ibcon#wrote, iclass 36, count 0 2006.190.08:22:10.38#ibcon#about to read 3, iclass 36, count 0 2006.190.08:22:10.42#ibcon#read 3, iclass 36, count 0 2006.190.08:22:10.42#ibcon#about to read 4, iclass 36, count 0 2006.190.08:22:10.42#ibcon#read 4, iclass 36, count 0 2006.190.08:22:10.42#ibcon#about to read 5, iclass 36, count 0 2006.190.08:22:10.42#ibcon#read 5, iclass 36, count 0 2006.190.08:22:10.42#ibcon#about to read 6, iclass 36, count 0 2006.190.08:22:10.42#ibcon#read 6, iclass 36, count 0 2006.190.08:22:10.42#ibcon#end of sib2, iclass 36, count 0 2006.190.08:22:10.42#ibcon#*after write, iclass 36, count 0 2006.190.08:22:10.42#ibcon#*before return 0, iclass 36, count 0 2006.190.08:22:10.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:22:10.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.190.08:22:10.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.190.08:22:10.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.190.08:22:10.42$vc4f8/va=8,6 2006.190.08:22:10.42#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.190.08:22:10.42#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.190.08:22:10.42#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:10.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:22:10.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:22:10.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:22:10.48#ibcon#enter wrdev, iclass 38, count 2 2006.190.08:22:10.48#ibcon#first serial, iclass 38, count 2 2006.190.08:22:10.48#ibcon#enter sib2, iclass 38, count 2 2006.190.08:22:10.48#ibcon#flushed, iclass 38, count 2 2006.190.08:22:10.48#ibcon#about to write, iclass 38, count 2 2006.190.08:22:10.48#ibcon#wrote, iclass 38, count 2 2006.190.08:22:10.48#ibcon#about to read 3, iclass 38, count 2 2006.190.08:22:10.50#ibcon#read 3, iclass 38, count 2 2006.190.08:22:10.50#ibcon#about to read 4, iclass 38, count 2 2006.190.08:22:10.50#ibcon#read 4, iclass 38, count 2 2006.190.08:22:10.50#ibcon#about to read 5, iclass 38, count 2 2006.190.08:22:10.50#ibcon#read 5, iclass 38, count 2 2006.190.08:22:10.50#ibcon#about to read 6, iclass 38, count 2 2006.190.08:22:10.50#ibcon#read 6, iclass 38, count 2 2006.190.08:22:10.50#ibcon#end of sib2, iclass 38, count 2 2006.190.08:22:10.50#ibcon#*mode == 0, iclass 38, count 2 2006.190.08:22:10.50#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.190.08:22:10.50#ibcon#[25=AT08-06\r\n] 2006.190.08:22:10.50#ibcon#*before write, iclass 38, count 2 2006.190.08:22:10.50#ibcon#enter sib2, iclass 38, count 2 2006.190.08:22:10.50#ibcon#flushed, iclass 38, count 2 2006.190.08:22:10.50#ibcon#about to write, iclass 38, count 2 2006.190.08:22:10.50#ibcon#wrote, iclass 38, count 2 2006.190.08:22:10.50#ibcon#about to read 3, iclass 38, count 2 2006.190.08:22:10.53#ibcon#read 3, iclass 38, count 2 2006.190.08:22:10.53#ibcon#about to read 4, iclass 38, count 2 2006.190.08:22:10.53#ibcon#read 4, iclass 38, count 2 2006.190.08:22:10.53#ibcon#about to read 5, iclass 38, count 2 2006.190.08:22:10.53#ibcon#read 5, iclass 38, count 2 2006.190.08:22:10.53#ibcon#about to read 6, iclass 38, count 2 2006.190.08:22:10.53#ibcon#read 6, iclass 38, count 2 2006.190.08:22:10.53#ibcon#end of sib2, iclass 38, count 2 2006.190.08:22:10.53#ibcon#*after write, iclass 38, count 2 2006.190.08:22:10.53#ibcon#*before return 0, iclass 38, count 2 2006.190.08:22:10.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:22:10.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.190.08:22:10.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.190.08:22:10.53#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:10.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:22:10.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:22:10.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:22:10.65#ibcon#enter wrdev, iclass 38, count 0 2006.190.08:22:10.65#ibcon#first serial, iclass 38, count 0 2006.190.08:22:10.65#ibcon#enter sib2, iclass 38, count 0 2006.190.08:22:10.65#ibcon#flushed, iclass 38, count 0 2006.190.08:22:10.65#ibcon#about to write, iclass 38, count 0 2006.190.08:22:10.65#ibcon#wrote, iclass 38, count 0 2006.190.08:22:10.65#ibcon#about to read 3, iclass 38, count 0 2006.190.08:22:10.67#ibcon#read 3, iclass 38, count 0 2006.190.08:22:10.67#ibcon#about to read 4, iclass 38, count 0 2006.190.08:22:10.67#ibcon#read 4, iclass 38, count 0 2006.190.08:22:10.67#ibcon#about to read 5, iclass 38, count 0 2006.190.08:22:10.67#ibcon#read 5, iclass 38, count 0 2006.190.08:22:10.67#ibcon#about to read 6, iclass 38, count 0 2006.190.08:22:10.67#ibcon#read 6, iclass 38, count 0 2006.190.08:22:10.67#ibcon#end of sib2, iclass 38, count 0 2006.190.08:22:10.67#ibcon#*mode == 0, iclass 38, count 0 2006.190.08:22:10.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.190.08:22:10.67#ibcon#[25=USB\r\n] 2006.190.08:22:10.67#ibcon#*before write, iclass 38, count 0 2006.190.08:22:10.67#ibcon#enter sib2, iclass 38, count 0 2006.190.08:22:10.67#ibcon#flushed, iclass 38, count 0 2006.190.08:22:10.67#ibcon#about to write, iclass 38, count 0 2006.190.08:22:10.67#ibcon#wrote, iclass 38, count 0 2006.190.08:22:10.67#ibcon#about to read 3, iclass 38, count 0 2006.190.08:22:10.70#ibcon#read 3, iclass 38, count 0 2006.190.08:22:10.70#ibcon#about to read 4, iclass 38, count 0 2006.190.08:22:10.70#ibcon#read 4, iclass 38, count 0 2006.190.08:22:10.70#ibcon#about to read 5, iclass 38, count 0 2006.190.08:22:10.70#ibcon#read 5, iclass 38, count 0 2006.190.08:22:10.70#ibcon#about to read 6, iclass 38, count 0 2006.190.08:22:10.70#ibcon#read 6, iclass 38, count 0 2006.190.08:22:10.70#ibcon#end of sib2, iclass 38, count 0 2006.190.08:22:10.70#ibcon#*after write, iclass 38, count 0 2006.190.08:22:10.70#ibcon#*before return 0, iclass 38, count 0 2006.190.08:22:10.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:22:10.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.190.08:22:10.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.190.08:22:10.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.190.08:22:10.70$vc4f8/vblo=1,632.99 2006.190.08:22:10.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.190.08:22:10.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.190.08:22:10.70#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:10.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:10.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:10.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:10.70#ibcon#enter wrdev, iclass 40, count 0 2006.190.08:22:10.70#ibcon#first serial, iclass 40, count 0 2006.190.08:22:10.70#ibcon#enter sib2, iclass 40, count 0 2006.190.08:22:10.70#ibcon#flushed, iclass 40, count 0 2006.190.08:22:10.70#ibcon#about to write, iclass 40, count 0 2006.190.08:22:10.70#ibcon#wrote, iclass 40, count 0 2006.190.08:22:10.70#ibcon#about to read 3, iclass 40, count 0 2006.190.08:22:10.72#ibcon#read 3, iclass 40, count 0 2006.190.08:22:10.72#ibcon#about to read 4, iclass 40, count 0 2006.190.08:22:10.72#ibcon#read 4, iclass 40, count 0 2006.190.08:22:10.72#ibcon#about to read 5, iclass 40, count 0 2006.190.08:22:10.72#ibcon#read 5, iclass 40, count 0 2006.190.08:22:10.72#ibcon#about to read 6, iclass 40, count 0 2006.190.08:22:10.72#ibcon#read 6, iclass 40, count 0 2006.190.08:22:10.72#ibcon#end of sib2, iclass 40, count 0 2006.190.08:22:10.72#ibcon#*mode == 0, iclass 40, count 0 2006.190.08:22:10.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.190.08:22:10.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:22:10.72#ibcon#*before write, iclass 40, count 0 2006.190.08:22:10.72#ibcon#enter sib2, iclass 40, count 0 2006.190.08:22:10.72#ibcon#flushed, iclass 40, count 0 2006.190.08:22:10.72#ibcon#about to write, iclass 40, count 0 2006.190.08:22:10.72#ibcon#wrote, iclass 40, count 0 2006.190.08:22:10.72#ibcon#about to read 3, iclass 40, count 0 2006.190.08:22:10.76#ibcon#read 3, iclass 40, count 0 2006.190.08:22:10.76#ibcon#about to read 4, iclass 40, count 0 2006.190.08:22:10.76#ibcon#read 4, iclass 40, count 0 2006.190.08:22:10.76#ibcon#about to read 5, iclass 40, count 0 2006.190.08:22:10.76#ibcon#read 5, iclass 40, count 0 2006.190.08:22:10.76#ibcon#about to read 6, iclass 40, count 0 2006.190.08:22:10.76#ibcon#read 6, iclass 40, count 0 2006.190.08:22:10.76#ibcon#end of sib2, iclass 40, count 0 2006.190.08:22:10.76#ibcon#*after write, iclass 40, count 0 2006.190.08:22:10.76#ibcon#*before return 0, iclass 40, count 0 2006.190.08:22:10.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:10.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.190.08:22:10.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.190.08:22:10.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.190.08:22:10.76$vc4f8/vb=1,4 2006.190.08:22:10.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.190.08:22:10.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.190.08:22:10.76#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:10.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:10.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:10.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:10.76#ibcon#enter wrdev, iclass 4, count 2 2006.190.08:22:10.76#ibcon#first serial, iclass 4, count 2 2006.190.08:22:10.76#ibcon#enter sib2, iclass 4, count 2 2006.190.08:22:10.76#ibcon#flushed, iclass 4, count 2 2006.190.08:22:10.76#ibcon#about to write, iclass 4, count 2 2006.190.08:22:10.76#ibcon#wrote, iclass 4, count 2 2006.190.08:22:10.76#ibcon#about to read 3, iclass 4, count 2 2006.190.08:22:10.78#ibcon#read 3, iclass 4, count 2 2006.190.08:22:10.78#ibcon#about to read 4, iclass 4, count 2 2006.190.08:22:10.78#ibcon#read 4, iclass 4, count 2 2006.190.08:22:10.78#ibcon#about to read 5, iclass 4, count 2 2006.190.08:22:10.78#ibcon#read 5, iclass 4, count 2 2006.190.08:22:10.78#ibcon#about to read 6, iclass 4, count 2 2006.190.08:22:10.78#ibcon#read 6, iclass 4, count 2 2006.190.08:22:10.78#ibcon#end of sib2, iclass 4, count 2 2006.190.08:22:10.78#ibcon#*mode == 0, iclass 4, count 2 2006.190.08:22:10.78#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.190.08:22:10.78#ibcon#[27=AT01-04\r\n] 2006.190.08:22:10.78#ibcon#*before write, iclass 4, count 2 2006.190.08:22:10.78#ibcon#enter sib2, iclass 4, count 2 2006.190.08:22:10.78#ibcon#flushed, iclass 4, count 2 2006.190.08:22:10.78#ibcon#about to write, iclass 4, count 2 2006.190.08:22:10.78#ibcon#wrote, iclass 4, count 2 2006.190.08:22:10.78#ibcon#about to read 3, iclass 4, count 2 2006.190.08:22:10.81#ibcon#read 3, iclass 4, count 2 2006.190.08:22:10.81#ibcon#about to read 4, iclass 4, count 2 2006.190.08:22:10.81#ibcon#read 4, iclass 4, count 2 2006.190.08:22:10.81#ibcon#about to read 5, iclass 4, count 2 2006.190.08:22:10.81#ibcon#read 5, iclass 4, count 2 2006.190.08:22:10.81#ibcon#about to read 6, iclass 4, count 2 2006.190.08:22:10.81#ibcon#read 6, iclass 4, count 2 2006.190.08:22:10.81#ibcon#end of sib2, iclass 4, count 2 2006.190.08:22:10.81#ibcon#*after write, iclass 4, count 2 2006.190.08:22:10.81#ibcon#*before return 0, iclass 4, count 2 2006.190.08:22:10.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:10.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.190.08:22:10.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.190.08:22:10.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:10.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:10.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:10.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:10.93#ibcon#enter wrdev, iclass 4, count 0 2006.190.08:22:10.93#ibcon#first serial, iclass 4, count 0 2006.190.08:22:10.93#ibcon#enter sib2, iclass 4, count 0 2006.190.08:22:10.93#ibcon#flushed, iclass 4, count 0 2006.190.08:22:10.93#ibcon#about to write, iclass 4, count 0 2006.190.08:22:10.93#ibcon#wrote, iclass 4, count 0 2006.190.08:22:10.93#ibcon#about to read 3, iclass 4, count 0 2006.190.08:22:10.95#ibcon#read 3, iclass 4, count 0 2006.190.08:22:10.95#ibcon#about to read 4, iclass 4, count 0 2006.190.08:22:10.95#ibcon#read 4, iclass 4, count 0 2006.190.08:22:10.95#ibcon#about to read 5, iclass 4, count 0 2006.190.08:22:10.95#ibcon#read 5, iclass 4, count 0 2006.190.08:22:10.95#ibcon#about to read 6, iclass 4, count 0 2006.190.08:22:10.95#ibcon#read 6, iclass 4, count 0 2006.190.08:22:10.95#ibcon#end of sib2, iclass 4, count 0 2006.190.08:22:10.95#ibcon#*mode == 0, iclass 4, count 0 2006.190.08:22:10.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.190.08:22:10.95#ibcon#[27=USB\r\n] 2006.190.08:22:10.95#ibcon#*before write, iclass 4, count 0 2006.190.08:22:10.95#ibcon#enter sib2, iclass 4, count 0 2006.190.08:22:10.95#ibcon#flushed, iclass 4, count 0 2006.190.08:22:10.95#ibcon#about to write, iclass 4, count 0 2006.190.08:22:10.95#ibcon#wrote, iclass 4, count 0 2006.190.08:22:10.95#ibcon#about to read 3, iclass 4, count 0 2006.190.08:22:10.98#ibcon#read 3, iclass 4, count 0 2006.190.08:22:10.98#ibcon#about to read 4, iclass 4, count 0 2006.190.08:22:10.98#ibcon#read 4, iclass 4, count 0 2006.190.08:22:10.98#ibcon#about to read 5, iclass 4, count 0 2006.190.08:22:10.98#ibcon#read 5, iclass 4, count 0 2006.190.08:22:10.98#ibcon#about to read 6, iclass 4, count 0 2006.190.08:22:10.98#ibcon#read 6, iclass 4, count 0 2006.190.08:22:10.98#ibcon#end of sib2, iclass 4, count 0 2006.190.08:22:10.98#ibcon#*after write, iclass 4, count 0 2006.190.08:22:10.98#ibcon#*before return 0, iclass 4, count 0 2006.190.08:22:10.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:10.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.190.08:22:10.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.190.08:22:10.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.190.08:22:10.98$vc4f8/vblo=2,640.99 2006.190.08:22:10.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.190.08:22:10.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.190.08:22:10.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:10.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:10.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:10.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:10.98#ibcon#enter wrdev, iclass 6, count 0 2006.190.08:22:10.98#ibcon#first serial, iclass 6, count 0 2006.190.08:22:10.98#ibcon#enter sib2, iclass 6, count 0 2006.190.08:22:10.98#ibcon#flushed, iclass 6, count 0 2006.190.08:22:10.98#ibcon#about to write, iclass 6, count 0 2006.190.08:22:10.98#ibcon#wrote, iclass 6, count 0 2006.190.08:22:10.98#ibcon#about to read 3, iclass 6, count 0 2006.190.08:22:11.00#ibcon#read 3, iclass 6, count 0 2006.190.08:22:11.00#ibcon#about to read 4, iclass 6, count 0 2006.190.08:22:11.00#ibcon#read 4, iclass 6, count 0 2006.190.08:22:11.00#ibcon#about to read 5, iclass 6, count 0 2006.190.08:22:11.00#ibcon#read 5, iclass 6, count 0 2006.190.08:22:11.00#ibcon#about to read 6, iclass 6, count 0 2006.190.08:22:11.00#ibcon#read 6, iclass 6, count 0 2006.190.08:22:11.00#ibcon#end of sib2, iclass 6, count 0 2006.190.08:22:11.00#ibcon#*mode == 0, iclass 6, count 0 2006.190.08:22:11.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.190.08:22:11.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:22:11.00#ibcon#*before write, iclass 6, count 0 2006.190.08:22:11.00#ibcon#enter sib2, iclass 6, count 0 2006.190.08:22:11.00#ibcon#flushed, iclass 6, count 0 2006.190.08:22:11.00#ibcon#about to write, iclass 6, count 0 2006.190.08:22:11.00#ibcon#wrote, iclass 6, count 0 2006.190.08:22:11.00#ibcon#about to read 3, iclass 6, count 0 2006.190.08:22:11.04#ibcon#read 3, iclass 6, count 0 2006.190.08:22:11.04#ibcon#about to read 4, iclass 6, count 0 2006.190.08:22:11.04#ibcon#read 4, iclass 6, count 0 2006.190.08:22:11.04#ibcon#about to read 5, iclass 6, count 0 2006.190.08:22:11.04#ibcon#read 5, iclass 6, count 0 2006.190.08:22:11.04#ibcon#about to read 6, iclass 6, count 0 2006.190.08:22:11.04#ibcon#read 6, iclass 6, count 0 2006.190.08:22:11.04#ibcon#end of sib2, iclass 6, count 0 2006.190.08:22:11.04#ibcon#*after write, iclass 6, count 0 2006.190.08:22:11.04#ibcon#*before return 0, iclass 6, count 0 2006.190.08:22:11.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:11.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.190.08:22:11.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.190.08:22:11.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.190.08:22:11.04$vc4f8/vb=2,4 2006.190.08:22:11.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.190.08:22:11.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.190.08:22:11.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:11.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:11.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:11.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:11.10#ibcon#enter wrdev, iclass 10, count 2 2006.190.08:22:11.10#ibcon#first serial, iclass 10, count 2 2006.190.08:22:11.10#ibcon#enter sib2, iclass 10, count 2 2006.190.08:22:11.10#ibcon#flushed, iclass 10, count 2 2006.190.08:22:11.10#ibcon#about to write, iclass 10, count 2 2006.190.08:22:11.10#ibcon#wrote, iclass 10, count 2 2006.190.08:22:11.10#ibcon#about to read 3, iclass 10, count 2 2006.190.08:22:11.12#ibcon#read 3, iclass 10, count 2 2006.190.08:22:11.12#ibcon#about to read 4, iclass 10, count 2 2006.190.08:22:11.12#ibcon#read 4, iclass 10, count 2 2006.190.08:22:11.12#ibcon#about to read 5, iclass 10, count 2 2006.190.08:22:11.12#ibcon#read 5, iclass 10, count 2 2006.190.08:22:11.12#ibcon#about to read 6, iclass 10, count 2 2006.190.08:22:11.12#ibcon#read 6, iclass 10, count 2 2006.190.08:22:11.12#ibcon#end of sib2, iclass 10, count 2 2006.190.08:22:11.12#ibcon#*mode == 0, iclass 10, count 2 2006.190.08:22:11.12#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.190.08:22:11.12#ibcon#[27=AT02-04\r\n] 2006.190.08:22:11.12#ibcon#*before write, iclass 10, count 2 2006.190.08:22:11.12#ibcon#enter sib2, iclass 10, count 2 2006.190.08:22:11.12#ibcon#flushed, iclass 10, count 2 2006.190.08:22:11.12#ibcon#about to write, iclass 10, count 2 2006.190.08:22:11.12#ibcon#wrote, iclass 10, count 2 2006.190.08:22:11.12#ibcon#about to read 3, iclass 10, count 2 2006.190.08:22:11.15#ibcon#read 3, iclass 10, count 2 2006.190.08:22:11.15#ibcon#about to read 4, iclass 10, count 2 2006.190.08:22:11.15#ibcon#read 4, iclass 10, count 2 2006.190.08:22:11.15#ibcon#about to read 5, iclass 10, count 2 2006.190.08:22:11.15#ibcon#read 5, iclass 10, count 2 2006.190.08:22:11.15#ibcon#about to read 6, iclass 10, count 2 2006.190.08:22:11.15#ibcon#read 6, iclass 10, count 2 2006.190.08:22:11.15#ibcon#end of sib2, iclass 10, count 2 2006.190.08:22:11.15#ibcon#*after write, iclass 10, count 2 2006.190.08:22:11.15#ibcon#*before return 0, iclass 10, count 2 2006.190.08:22:11.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:11.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.190.08:22:11.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.190.08:22:11.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:11.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:11.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:11.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:11.27#ibcon#enter wrdev, iclass 10, count 0 2006.190.08:22:11.27#ibcon#first serial, iclass 10, count 0 2006.190.08:22:11.27#ibcon#enter sib2, iclass 10, count 0 2006.190.08:22:11.27#ibcon#flushed, iclass 10, count 0 2006.190.08:22:11.27#ibcon#about to write, iclass 10, count 0 2006.190.08:22:11.27#ibcon#wrote, iclass 10, count 0 2006.190.08:22:11.27#ibcon#about to read 3, iclass 10, count 0 2006.190.08:22:11.29#ibcon#read 3, iclass 10, count 0 2006.190.08:22:11.29#ibcon#about to read 4, iclass 10, count 0 2006.190.08:22:11.29#ibcon#read 4, iclass 10, count 0 2006.190.08:22:11.29#ibcon#about to read 5, iclass 10, count 0 2006.190.08:22:11.29#ibcon#read 5, iclass 10, count 0 2006.190.08:22:11.29#ibcon#about to read 6, iclass 10, count 0 2006.190.08:22:11.29#ibcon#read 6, iclass 10, count 0 2006.190.08:22:11.29#ibcon#end of sib2, iclass 10, count 0 2006.190.08:22:11.29#ibcon#*mode == 0, iclass 10, count 0 2006.190.08:22:11.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.190.08:22:11.29#ibcon#[27=USB\r\n] 2006.190.08:22:11.29#ibcon#*before write, iclass 10, count 0 2006.190.08:22:11.29#ibcon#enter sib2, iclass 10, count 0 2006.190.08:22:11.29#ibcon#flushed, iclass 10, count 0 2006.190.08:22:11.29#ibcon#about to write, iclass 10, count 0 2006.190.08:22:11.29#ibcon#wrote, iclass 10, count 0 2006.190.08:22:11.29#ibcon#about to read 3, iclass 10, count 0 2006.190.08:22:11.32#ibcon#read 3, iclass 10, count 0 2006.190.08:22:11.32#ibcon#about to read 4, iclass 10, count 0 2006.190.08:22:11.32#ibcon#read 4, iclass 10, count 0 2006.190.08:22:11.32#ibcon#about to read 5, iclass 10, count 0 2006.190.08:22:11.32#ibcon#read 5, iclass 10, count 0 2006.190.08:22:11.32#ibcon#about to read 6, iclass 10, count 0 2006.190.08:22:11.32#ibcon#read 6, iclass 10, count 0 2006.190.08:22:11.32#ibcon#end of sib2, iclass 10, count 0 2006.190.08:22:11.32#ibcon#*after write, iclass 10, count 0 2006.190.08:22:11.32#ibcon#*before return 0, iclass 10, count 0 2006.190.08:22:11.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:11.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.190.08:22:11.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.190.08:22:11.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.190.08:22:11.32$vc4f8/vblo=3,656.99 2006.190.08:22:11.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.190.08:22:11.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.190.08:22:11.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:11.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:11.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:11.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:11.32#ibcon#enter wrdev, iclass 12, count 0 2006.190.08:22:11.32#ibcon#first serial, iclass 12, count 0 2006.190.08:22:11.32#ibcon#enter sib2, iclass 12, count 0 2006.190.08:22:11.32#ibcon#flushed, iclass 12, count 0 2006.190.08:22:11.32#ibcon#about to write, iclass 12, count 0 2006.190.08:22:11.32#ibcon#wrote, iclass 12, count 0 2006.190.08:22:11.32#ibcon#about to read 3, iclass 12, count 0 2006.190.08:22:11.34#ibcon#read 3, iclass 12, count 0 2006.190.08:22:11.34#ibcon#about to read 4, iclass 12, count 0 2006.190.08:22:11.34#ibcon#read 4, iclass 12, count 0 2006.190.08:22:11.34#ibcon#about to read 5, iclass 12, count 0 2006.190.08:22:11.34#ibcon#read 5, iclass 12, count 0 2006.190.08:22:11.34#ibcon#about to read 6, iclass 12, count 0 2006.190.08:22:11.34#ibcon#read 6, iclass 12, count 0 2006.190.08:22:11.34#ibcon#end of sib2, iclass 12, count 0 2006.190.08:22:11.34#ibcon#*mode == 0, iclass 12, count 0 2006.190.08:22:11.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.190.08:22:11.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:22:11.34#ibcon#*before write, iclass 12, count 0 2006.190.08:22:11.34#ibcon#enter sib2, iclass 12, count 0 2006.190.08:22:11.34#ibcon#flushed, iclass 12, count 0 2006.190.08:22:11.34#ibcon#about to write, iclass 12, count 0 2006.190.08:22:11.34#ibcon#wrote, iclass 12, count 0 2006.190.08:22:11.34#ibcon#about to read 3, iclass 12, count 0 2006.190.08:22:11.38#ibcon#read 3, iclass 12, count 0 2006.190.08:22:11.38#ibcon#about to read 4, iclass 12, count 0 2006.190.08:22:11.38#ibcon#read 4, iclass 12, count 0 2006.190.08:22:11.38#ibcon#about to read 5, iclass 12, count 0 2006.190.08:22:11.38#ibcon#read 5, iclass 12, count 0 2006.190.08:22:11.38#ibcon#about to read 6, iclass 12, count 0 2006.190.08:22:11.38#ibcon#read 6, iclass 12, count 0 2006.190.08:22:11.38#ibcon#end of sib2, iclass 12, count 0 2006.190.08:22:11.38#ibcon#*after write, iclass 12, count 0 2006.190.08:22:11.38#ibcon#*before return 0, iclass 12, count 0 2006.190.08:22:11.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:11.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.190.08:22:11.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.190.08:22:11.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.190.08:22:11.38$vc4f8/vb=3,4 2006.190.08:22:11.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.190.08:22:11.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.190.08:22:11.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:11.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:11.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:11.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:11.44#ibcon#enter wrdev, iclass 14, count 2 2006.190.08:22:11.44#ibcon#first serial, iclass 14, count 2 2006.190.08:22:11.44#ibcon#enter sib2, iclass 14, count 2 2006.190.08:22:11.44#ibcon#flushed, iclass 14, count 2 2006.190.08:22:11.44#ibcon#about to write, iclass 14, count 2 2006.190.08:22:11.44#ibcon#wrote, iclass 14, count 2 2006.190.08:22:11.44#ibcon#about to read 3, iclass 14, count 2 2006.190.08:22:11.46#ibcon#read 3, iclass 14, count 2 2006.190.08:22:11.46#ibcon#about to read 4, iclass 14, count 2 2006.190.08:22:11.46#ibcon#read 4, iclass 14, count 2 2006.190.08:22:11.46#ibcon#about to read 5, iclass 14, count 2 2006.190.08:22:11.46#ibcon#read 5, iclass 14, count 2 2006.190.08:22:11.46#ibcon#about to read 6, iclass 14, count 2 2006.190.08:22:11.46#ibcon#read 6, iclass 14, count 2 2006.190.08:22:11.46#ibcon#end of sib2, iclass 14, count 2 2006.190.08:22:11.46#ibcon#*mode == 0, iclass 14, count 2 2006.190.08:22:11.46#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.190.08:22:11.46#ibcon#[27=AT03-04\r\n] 2006.190.08:22:11.46#ibcon#*before write, iclass 14, count 2 2006.190.08:22:11.46#ibcon#enter sib2, iclass 14, count 2 2006.190.08:22:11.46#ibcon#flushed, iclass 14, count 2 2006.190.08:22:11.46#ibcon#about to write, iclass 14, count 2 2006.190.08:22:11.46#ibcon#wrote, iclass 14, count 2 2006.190.08:22:11.46#ibcon#about to read 3, iclass 14, count 2 2006.190.08:22:11.49#ibcon#read 3, iclass 14, count 2 2006.190.08:22:11.49#ibcon#about to read 4, iclass 14, count 2 2006.190.08:22:11.49#ibcon#read 4, iclass 14, count 2 2006.190.08:22:11.49#ibcon#about to read 5, iclass 14, count 2 2006.190.08:22:11.49#ibcon#read 5, iclass 14, count 2 2006.190.08:22:11.49#ibcon#about to read 6, iclass 14, count 2 2006.190.08:22:11.49#ibcon#read 6, iclass 14, count 2 2006.190.08:22:11.49#ibcon#end of sib2, iclass 14, count 2 2006.190.08:22:11.49#ibcon#*after write, iclass 14, count 2 2006.190.08:22:11.49#ibcon#*before return 0, iclass 14, count 2 2006.190.08:22:11.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:11.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.190.08:22:11.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.190.08:22:11.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:11.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:11.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:11.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:11.61#ibcon#enter wrdev, iclass 14, count 0 2006.190.08:22:11.61#ibcon#first serial, iclass 14, count 0 2006.190.08:22:11.61#ibcon#enter sib2, iclass 14, count 0 2006.190.08:22:11.61#ibcon#flushed, iclass 14, count 0 2006.190.08:22:11.61#ibcon#about to write, iclass 14, count 0 2006.190.08:22:11.61#ibcon#wrote, iclass 14, count 0 2006.190.08:22:11.61#ibcon#about to read 3, iclass 14, count 0 2006.190.08:22:11.63#ibcon#read 3, iclass 14, count 0 2006.190.08:22:11.63#ibcon#about to read 4, iclass 14, count 0 2006.190.08:22:11.63#ibcon#read 4, iclass 14, count 0 2006.190.08:22:11.63#ibcon#about to read 5, iclass 14, count 0 2006.190.08:22:11.63#ibcon#read 5, iclass 14, count 0 2006.190.08:22:11.63#ibcon#about to read 6, iclass 14, count 0 2006.190.08:22:11.63#ibcon#read 6, iclass 14, count 0 2006.190.08:22:11.63#ibcon#end of sib2, iclass 14, count 0 2006.190.08:22:11.63#ibcon#*mode == 0, iclass 14, count 0 2006.190.08:22:11.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.190.08:22:11.63#ibcon#[27=USB\r\n] 2006.190.08:22:11.63#ibcon#*before write, iclass 14, count 0 2006.190.08:22:11.63#ibcon#enter sib2, iclass 14, count 0 2006.190.08:22:11.63#ibcon#flushed, iclass 14, count 0 2006.190.08:22:11.63#ibcon#about to write, iclass 14, count 0 2006.190.08:22:11.63#ibcon#wrote, iclass 14, count 0 2006.190.08:22:11.63#ibcon#about to read 3, iclass 14, count 0 2006.190.08:22:11.66#ibcon#read 3, iclass 14, count 0 2006.190.08:22:11.66#ibcon#about to read 4, iclass 14, count 0 2006.190.08:22:11.66#ibcon#read 4, iclass 14, count 0 2006.190.08:22:11.66#ibcon#about to read 5, iclass 14, count 0 2006.190.08:22:11.66#ibcon#read 5, iclass 14, count 0 2006.190.08:22:11.66#ibcon#about to read 6, iclass 14, count 0 2006.190.08:22:11.66#ibcon#read 6, iclass 14, count 0 2006.190.08:22:11.66#ibcon#end of sib2, iclass 14, count 0 2006.190.08:22:11.66#ibcon#*after write, iclass 14, count 0 2006.190.08:22:11.66#ibcon#*before return 0, iclass 14, count 0 2006.190.08:22:11.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:11.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.190.08:22:11.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.190.08:22:11.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.190.08:22:11.66$vc4f8/vblo=4,712.99 2006.190.08:22:11.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.190.08:22:11.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.190.08:22:11.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:11.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:11.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:11.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:11.66#ibcon#enter wrdev, iclass 16, count 0 2006.190.08:22:11.66#ibcon#first serial, iclass 16, count 0 2006.190.08:22:11.66#ibcon#enter sib2, iclass 16, count 0 2006.190.08:22:11.66#ibcon#flushed, iclass 16, count 0 2006.190.08:22:11.66#ibcon#about to write, iclass 16, count 0 2006.190.08:22:11.66#ibcon#wrote, iclass 16, count 0 2006.190.08:22:11.66#ibcon#about to read 3, iclass 16, count 0 2006.190.08:22:11.68#ibcon#read 3, iclass 16, count 0 2006.190.08:22:11.68#ibcon#about to read 4, iclass 16, count 0 2006.190.08:22:11.68#ibcon#read 4, iclass 16, count 0 2006.190.08:22:11.68#ibcon#about to read 5, iclass 16, count 0 2006.190.08:22:11.68#ibcon#read 5, iclass 16, count 0 2006.190.08:22:11.68#ibcon#about to read 6, iclass 16, count 0 2006.190.08:22:11.68#ibcon#read 6, iclass 16, count 0 2006.190.08:22:11.68#ibcon#end of sib2, iclass 16, count 0 2006.190.08:22:11.68#ibcon#*mode == 0, iclass 16, count 0 2006.190.08:22:11.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.190.08:22:11.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:22:11.68#ibcon#*before write, iclass 16, count 0 2006.190.08:22:11.68#ibcon#enter sib2, iclass 16, count 0 2006.190.08:22:11.68#ibcon#flushed, iclass 16, count 0 2006.190.08:22:11.68#ibcon#about to write, iclass 16, count 0 2006.190.08:22:11.68#ibcon#wrote, iclass 16, count 0 2006.190.08:22:11.68#ibcon#about to read 3, iclass 16, count 0 2006.190.08:22:11.72#ibcon#read 3, iclass 16, count 0 2006.190.08:22:11.72#ibcon#about to read 4, iclass 16, count 0 2006.190.08:22:11.72#ibcon#read 4, iclass 16, count 0 2006.190.08:22:11.72#ibcon#about to read 5, iclass 16, count 0 2006.190.08:22:11.72#ibcon#read 5, iclass 16, count 0 2006.190.08:22:11.72#ibcon#about to read 6, iclass 16, count 0 2006.190.08:22:11.72#ibcon#read 6, iclass 16, count 0 2006.190.08:22:11.72#ibcon#end of sib2, iclass 16, count 0 2006.190.08:22:11.72#ibcon#*after write, iclass 16, count 0 2006.190.08:22:11.72#ibcon#*before return 0, iclass 16, count 0 2006.190.08:22:11.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:11.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.190.08:22:11.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.190.08:22:11.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.190.08:22:11.72$vc4f8/vb=4,4 2006.190.08:22:11.72#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.190.08:22:11.72#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.190.08:22:11.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:11.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:11.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:11.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:11.78#ibcon#enter wrdev, iclass 18, count 2 2006.190.08:22:11.78#ibcon#first serial, iclass 18, count 2 2006.190.08:22:11.78#ibcon#enter sib2, iclass 18, count 2 2006.190.08:22:11.78#ibcon#flushed, iclass 18, count 2 2006.190.08:22:11.78#ibcon#about to write, iclass 18, count 2 2006.190.08:22:11.78#ibcon#wrote, iclass 18, count 2 2006.190.08:22:11.78#ibcon#about to read 3, iclass 18, count 2 2006.190.08:22:11.80#ibcon#read 3, iclass 18, count 2 2006.190.08:22:11.80#ibcon#about to read 4, iclass 18, count 2 2006.190.08:22:11.80#ibcon#read 4, iclass 18, count 2 2006.190.08:22:11.80#ibcon#about to read 5, iclass 18, count 2 2006.190.08:22:11.80#ibcon#read 5, iclass 18, count 2 2006.190.08:22:11.80#ibcon#about to read 6, iclass 18, count 2 2006.190.08:22:11.80#ibcon#read 6, iclass 18, count 2 2006.190.08:22:11.80#ibcon#end of sib2, iclass 18, count 2 2006.190.08:22:11.80#ibcon#*mode == 0, iclass 18, count 2 2006.190.08:22:11.80#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.190.08:22:11.80#ibcon#[27=AT04-04\r\n] 2006.190.08:22:11.80#ibcon#*before write, iclass 18, count 2 2006.190.08:22:11.80#ibcon#enter sib2, iclass 18, count 2 2006.190.08:22:11.80#ibcon#flushed, iclass 18, count 2 2006.190.08:22:11.80#ibcon#about to write, iclass 18, count 2 2006.190.08:22:11.80#ibcon#wrote, iclass 18, count 2 2006.190.08:22:11.80#ibcon#about to read 3, iclass 18, count 2 2006.190.08:22:11.83#ibcon#read 3, iclass 18, count 2 2006.190.08:22:11.83#ibcon#about to read 4, iclass 18, count 2 2006.190.08:22:11.83#ibcon#read 4, iclass 18, count 2 2006.190.08:22:11.83#ibcon#about to read 5, iclass 18, count 2 2006.190.08:22:11.83#ibcon#read 5, iclass 18, count 2 2006.190.08:22:11.83#ibcon#about to read 6, iclass 18, count 2 2006.190.08:22:11.83#ibcon#read 6, iclass 18, count 2 2006.190.08:22:11.83#ibcon#end of sib2, iclass 18, count 2 2006.190.08:22:11.83#ibcon#*after write, iclass 18, count 2 2006.190.08:22:11.83#ibcon#*before return 0, iclass 18, count 2 2006.190.08:22:11.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:11.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.190.08:22:11.83#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.190.08:22:11.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:11.83#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:11.95#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:11.95#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:11.95#ibcon#enter wrdev, iclass 18, count 0 2006.190.08:22:11.95#ibcon#first serial, iclass 18, count 0 2006.190.08:22:11.95#ibcon#enter sib2, iclass 18, count 0 2006.190.08:22:11.95#ibcon#flushed, iclass 18, count 0 2006.190.08:22:11.95#ibcon#about to write, iclass 18, count 0 2006.190.08:22:11.95#ibcon#wrote, iclass 18, count 0 2006.190.08:22:11.95#ibcon#about to read 3, iclass 18, count 0 2006.190.08:22:11.97#ibcon#read 3, iclass 18, count 0 2006.190.08:22:11.97#ibcon#about to read 4, iclass 18, count 0 2006.190.08:22:11.97#ibcon#read 4, iclass 18, count 0 2006.190.08:22:11.97#ibcon#about to read 5, iclass 18, count 0 2006.190.08:22:11.97#ibcon#read 5, iclass 18, count 0 2006.190.08:22:11.97#ibcon#about to read 6, iclass 18, count 0 2006.190.08:22:11.97#ibcon#read 6, iclass 18, count 0 2006.190.08:22:11.97#ibcon#end of sib2, iclass 18, count 0 2006.190.08:22:11.97#ibcon#*mode == 0, iclass 18, count 0 2006.190.08:22:11.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.190.08:22:11.97#ibcon#[27=USB\r\n] 2006.190.08:22:11.97#ibcon#*before write, iclass 18, count 0 2006.190.08:22:11.97#ibcon#enter sib2, iclass 18, count 0 2006.190.08:22:11.97#ibcon#flushed, iclass 18, count 0 2006.190.08:22:11.97#ibcon#about to write, iclass 18, count 0 2006.190.08:22:11.97#ibcon#wrote, iclass 18, count 0 2006.190.08:22:11.97#ibcon#about to read 3, iclass 18, count 0 2006.190.08:22:12.00#ibcon#read 3, iclass 18, count 0 2006.190.08:22:12.00#ibcon#about to read 4, iclass 18, count 0 2006.190.08:22:12.00#ibcon#read 4, iclass 18, count 0 2006.190.08:22:12.00#ibcon#about to read 5, iclass 18, count 0 2006.190.08:22:12.00#ibcon#read 5, iclass 18, count 0 2006.190.08:22:12.00#ibcon#about to read 6, iclass 18, count 0 2006.190.08:22:12.00#ibcon#read 6, iclass 18, count 0 2006.190.08:22:12.00#ibcon#end of sib2, iclass 18, count 0 2006.190.08:22:12.00#ibcon#*after write, iclass 18, count 0 2006.190.08:22:12.00#ibcon#*before return 0, iclass 18, count 0 2006.190.08:22:12.00#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:12.00#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.190.08:22:12.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.190.08:22:12.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.190.08:22:12.00$vc4f8/vblo=5,744.99 2006.190.08:22:12.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.190.08:22:12.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.190.08:22:12.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:12.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:12.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:12.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:12.00#ibcon#enter wrdev, iclass 20, count 0 2006.190.08:22:12.00#ibcon#first serial, iclass 20, count 0 2006.190.08:22:12.00#ibcon#enter sib2, iclass 20, count 0 2006.190.08:22:12.00#ibcon#flushed, iclass 20, count 0 2006.190.08:22:12.00#ibcon#about to write, iclass 20, count 0 2006.190.08:22:12.00#ibcon#wrote, iclass 20, count 0 2006.190.08:22:12.00#ibcon#about to read 3, iclass 20, count 0 2006.190.08:22:12.02#ibcon#read 3, iclass 20, count 0 2006.190.08:22:12.02#ibcon#about to read 4, iclass 20, count 0 2006.190.08:22:12.02#ibcon#read 4, iclass 20, count 0 2006.190.08:22:12.02#ibcon#about to read 5, iclass 20, count 0 2006.190.08:22:12.02#ibcon#read 5, iclass 20, count 0 2006.190.08:22:12.02#ibcon#about to read 6, iclass 20, count 0 2006.190.08:22:12.02#ibcon#read 6, iclass 20, count 0 2006.190.08:22:12.02#ibcon#end of sib2, iclass 20, count 0 2006.190.08:22:12.02#ibcon#*mode == 0, iclass 20, count 0 2006.190.08:22:12.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.190.08:22:12.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:22:12.02#ibcon#*before write, iclass 20, count 0 2006.190.08:22:12.02#ibcon#enter sib2, iclass 20, count 0 2006.190.08:22:12.02#ibcon#flushed, iclass 20, count 0 2006.190.08:22:12.02#ibcon#about to write, iclass 20, count 0 2006.190.08:22:12.02#ibcon#wrote, iclass 20, count 0 2006.190.08:22:12.02#ibcon#about to read 3, iclass 20, count 0 2006.190.08:22:12.06#ibcon#read 3, iclass 20, count 0 2006.190.08:22:12.06#ibcon#about to read 4, iclass 20, count 0 2006.190.08:22:12.06#ibcon#read 4, iclass 20, count 0 2006.190.08:22:12.06#ibcon#about to read 5, iclass 20, count 0 2006.190.08:22:12.06#ibcon#read 5, iclass 20, count 0 2006.190.08:22:12.06#ibcon#about to read 6, iclass 20, count 0 2006.190.08:22:12.06#ibcon#read 6, iclass 20, count 0 2006.190.08:22:12.06#ibcon#end of sib2, iclass 20, count 0 2006.190.08:22:12.06#ibcon#*after write, iclass 20, count 0 2006.190.08:22:12.06#ibcon#*before return 0, iclass 20, count 0 2006.190.08:22:12.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:12.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.190.08:22:12.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.190.08:22:12.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.190.08:22:12.06$vc4f8/vb=5,4 2006.190.08:22:12.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.190.08:22:12.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.190.08:22:12.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:12.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:12.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:12.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:12.12#ibcon#enter wrdev, iclass 22, count 2 2006.190.08:22:12.12#ibcon#first serial, iclass 22, count 2 2006.190.08:22:12.12#ibcon#enter sib2, iclass 22, count 2 2006.190.08:22:12.12#ibcon#flushed, iclass 22, count 2 2006.190.08:22:12.12#ibcon#about to write, iclass 22, count 2 2006.190.08:22:12.12#ibcon#wrote, iclass 22, count 2 2006.190.08:22:12.12#ibcon#about to read 3, iclass 22, count 2 2006.190.08:22:12.14#ibcon#read 3, iclass 22, count 2 2006.190.08:22:12.14#ibcon#about to read 4, iclass 22, count 2 2006.190.08:22:12.14#ibcon#read 4, iclass 22, count 2 2006.190.08:22:12.14#ibcon#about to read 5, iclass 22, count 2 2006.190.08:22:12.14#ibcon#read 5, iclass 22, count 2 2006.190.08:22:12.14#ibcon#about to read 6, iclass 22, count 2 2006.190.08:22:12.14#ibcon#read 6, iclass 22, count 2 2006.190.08:22:12.14#ibcon#end of sib2, iclass 22, count 2 2006.190.08:22:12.14#ibcon#*mode == 0, iclass 22, count 2 2006.190.08:22:12.14#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.190.08:22:12.14#ibcon#[27=AT05-04\r\n] 2006.190.08:22:12.14#ibcon#*before write, iclass 22, count 2 2006.190.08:22:12.14#ibcon#enter sib2, iclass 22, count 2 2006.190.08:22:12.14#ibcon#flushed, iclass 22, count 2 2006.190.08:22:12.14#ibcon#about to write, iclass 22, count 2 2006.190.08:22:12.14#ibcon#wrote, iclass 22, count 2 2006.190.08:22:12.14#ibcon#about to read 3, iclass 22, count 2 2006.190.08:22:12.17#ibcon#read 3, iclass 22, count 2 2006.190.08:22:12.17#ibcon#about to read 4, iclass 22, count 2 2006.190.08:22:12.17#ibcon#read 4, iclass 22, count 2 2006.190.08:22:12.17#ibcon#about to read 5, iclass 22, count 2 2006.190.08:22:12.17#ibcon#read 5, iclass 22, count 2 2006.190.08:22:12.17#ibcon#about to read 6, iclass 22, count 2 2006.190.08:22:12.17#ibcon#read 6, iclass 22, count 2 2006.190.08:22:12.17#ibcon#end of sib2, iclass 22, count 2 2006.190.08:22:12.17#ibcon#*after write, iclass 22, count 2 2006.190.08:22:12.17#ibcon#*before return 0, iclass 22, count 2 2006.190.08:22:12.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:12.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.190.08:22:12.17#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.190.08:22:12.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:12.17#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:12.29#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:12.29#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:12.29#ibcon#enter wrdev, iclass 22, count 0 2006.190.08:22:12.29#ibcon#first serial, iclass 22, count 0 2006.190.08:22:12.29#ibcon#enter sib2, iclass 22, count 0 2006.190.08:22:12.29#ibcon#flushed, iclass 22, count 0 2006.190.08:22:12.29#ibcon#about to write, iclass 22, count 0 2006.190.08:22:12.29#ibcon#wrote, iclass 22, count 0 2006.190.08:22:12.29#ibcon#about to read 3, iclass 22, count 0 2006.190.08:22:12.31#ibcon#read 3, iclass 22, count 0 2006.190.08:22:12.31#ibcon#about to read 4, iclass 22, count 0 2006.190.08:22:12.31#ibcon#read 4, iclass 22, count 0 2006.190.08:22:12.31#ibcon#about to read 5, iclass 22, count 0 2006.190.08:22:12.31#ibcon#read 5, iclass 22, count 0 2006.190.08:22:12.31#ibcon#about to read 6, iclass 22, count 0 2006.190.08:22:12.31#ibcon#read 6, iclass 22, count 0 2006.190.08:22:12.31#ibcon#end of sib2, iclass 22, count 0 2006.190.08:22:12.31#ibcon#*mode == 0, iclass 22, count 0 2006.190.08:22:12.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.190.08:22:12.31#ibcon#[27=USB\r\n] 2006.190.08:22:12.31#ibcon#*before write, iclass 22, count 0 2006.190.08:22:12.31#ibcon#enter sib2, iclass 22, count 0 2006.190.08:22:12.31#ibcon#flushed, iclass 22, count 0 2006.190.08:22:12.31#ibcon#about to write, iclass 22, count 0 2006.190.08:22:12.31#ibcon#wrote, iclass 22, count 0 2006.190.08:22:12.31#ibcon#about to read 3, iclass 22, count 0 2006.190.08:22:12.34#ibcon#read 3, iclass 22, count 0 2006.190.08:22:12.34#ibcon#about to read 4, iclass 22, count 0 2006.190.08:22:12.34#ibcon#read 4, iclass 22, count 0 2006.190.08:22:12.34#ibcon#about to read 5, iclass 22, count 0 2006.190.08:22:12.34#ibcon#read 5, iclass 22, count 0 2006.190.08:22:12.34#ibcon#about to read 6, iclass 22, count 0 2006.190.08:22:12.34#ibcon#read 6, iclass 22, count 0 2006.190.08:22:12.34#ibcon#end of sib2, iclass 22, count 0 2006.190.08:22:12.34#ibcon#*after write, iclass 22, count 0 2006.190.08:22:12.34#ibcon#*before return 0, iclass 22, count 0 2006.190.08:22:12.34#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:12.34#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.190.08:22:12.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.190.08:22:12.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.190.08:22:12.34$vc4f8/vblo=6,752.99 2006.190.08:22:12.34#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.190.08:22:12.34#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.190.08:22:12.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:22:12.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:22:12.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:22:12.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:22:12.34#ibcon#enter wrdev, iclass 24, count 0 2006.190.08:22:12.34#ibcon#first serial, iclass 24, count 0 2006.190.08:22:12.34#ibcon#enter sib2, iclass 24, count 0 2006.190.08:22:12.34#ibcon#flushed, iclass 24, count 0 2006.190.08:22:12.34#ibcon#about to write, iclass 24, count 0 2006.190.08:22:12.34#ibcon#wrote, iclass 24, count 0 2006.190.08:22:12.34#ibcon#about to read 3, iclass 24, count 0 2006.190.08:22:12.36#ibcon#read 3, iclass 24, count 0 2006.190.08:22:12.36#ibcon#about to read 4, iclass 24, count 0 2006.190.08:22:12.36#ibcon#read 4, iclass 24, count 0 2006.190.08:22:12.36#ibcon#about to read 5, iclass 24, count 0 2006.190.08:22:12.36#ibcon#read 5, iclass 24, count 0 2006.190.08:22:12.36#ibcon#about to read 6, iclass 24, count 0 2006.190.08:22:12.36#ibcon#read 6, iclass 24, count 0 2006.190.08:22:12.36#ibcon#end of sib2, iclass 24, count 0 2006.190.08:22:12.36#ibcon#*mode == 0, iclass 24, count 0 2006.190.08:22:12.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.190.08:22:12.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:22:12.36#ibcon#*before write, iclass 24, count 0 2006.190.08:22:12.36#ibcon#enter sib2, iclass 24, count 0 2006.190.08:22:12.36#ibcon#flushed, iclass 24, count 0 2006.190.08:22:12.36#ibcon#about to write, iclass 24, count 0 2006.190.08:22:12.36#ibcon#wrote, iclass 24, count 0 2006.190.08:22:12.36#ibcon#about to read 3, iclass 24, count 0 2006.190.08:22:12.40#ibcon#read 3, iclass 24, count 0 2006.190.08:22:12.40#ibcon#about to read 4, iclass 24, count 0 2006.190.08:22:12.40#ibcon#read 4, iclass 24, count 0 2006.190.08:22:12.40#ibcon#about to read 5, iclass 24, count 0 2006.190.08:22:12.40#ibcon#read 5, iclass 24, count 0 2006.190.08:22:12.40#ibcon#about to read 6, iclass 24, count 0 2006.190.08:22:12.40#ibcon#read 6, iclass 24, count 0 2006.190.08:22:12.40#ibcon#end of sib2, iclass 24, count 0 2006.190.08:22:12.40#ibcon#*after write, iclass 24, count 0 2006.190.08:22:12.40#ibcon#*before return 0, iclass 24, count 0 2006.190.08:22:12.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:22:12.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.190.08:22:12.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.190.08:22:12.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.190.08:22:12.40$vc4f8/vb=6,4 2006.190.08:22:12.40#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.190.08:22:12.40#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.190.08:22:12.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:22:12.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:22:12.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:22:12.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:22:12.46#ibcon#enter wrdev, iclass 26, count 2 2006.190.08:22:12.46#ibcon#first serial, iclass 26, count 2 2006.190.08:22:12.46#ibcon#enter sib2, iclass 26, count 2 2006.190.08:22:12.46#ibcon#flushed, iclass 26, count 2 2006.190.08:22:12.46#ibcon#about to write, iclass 26, count 2 2006.190.08:22:12.46#ibcon#wrote, iclass 26, count 2 2006.190.08:22:12.46#ibcon#about to read 3, iclass 26, count 2 2006.190.08:22:12.48#ibcon#read 3, iclass 26, count 2 2006.190.08:22:12.48#ibcon#about to read 4, iclass 26, count 2 2006.190.08:22:12.48#ibcon#read 4, iclass 26, count 2 2006.190.08:22:12.48#ibcon#about to read 5, iclass 26, count 2 2006.190.08:22:12.48#ibcon#read 5, iclass 26, count 2 2006.190.08:22:12.48#ibcon#about to read 6, iclass 26, count 2 2006.190.08:22:12.48#ibcon#read 6, iclass 26, count 2 2006.190.08:22:12.48#ibcon#end of sib2, iclass 26, count 2 2006.190.08:22:12.48#ibcon#*mode == 0, iclass 26, count 2 2006.190.08:22:12.48#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.190.08:22:12.48#ibcon#[27=AT06-04\r\n] 2006.190.08:22:12.48#ibcon#*before write, iclass 26, count 2 2006.190.08:22:12.48#ibcon#enter sib2, iclass 26, count 2 2006.190.08:22:12.48#ibcon#flushed, iclass 26, count 2 2006.190.08:22:12.48#ibcon#about to write, iclass 26, count 2 2006.190.08:22:12.48#ibcon#wrote, iclass 26, count 2 2006.190.08:22:12.48#ibcon#about to read 3, iclass 26, count 2 2006.190.08:22:12.51#ibcon#read 3, iclass 26, count 2 2006.190.08:22:12.51#ibcon#about to read 4, iclass 26, count 2 2006.190.08:22:12.51#ibcon#read 4, iclass 26, count 2 2006.190.08:22:12.51#ibcon#about to read 5, iclass 26, count 2 2006.190.08:22:12.51#ibcon#read 5, iclass 26, count 2 2006.190.08:22:12.51#ibcon#about to read 6, iclass 26, count 2 2006.190.08:22:12.51#ibcon#read 6, iclass 26, count 2 2006.190.08:22:12.51#ibcon#end of sib2, iclass 26, count 2 2006.190.08:22:12.51#ibcon#*after write, iclass 26, count 2 2006.190.08:22:12.51#ibcon#*before return 0, iclass 26, count 2 2006.190.08:22:12.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:22:12.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.190.08:22:12.51#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.190.08:22:12.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:22:12.51#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:22:12.63#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:22:12.63#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:22:12.63#ibcon#enter wrdev, iclass 26, count 0 2006.190.08:22:12.63#ibcon#first serial, iclass 26, count 0 2006.190.08:22:12.63#ibcon#enter sib2, iclass 26, count 0 2006.190.08:22:12.63#ibcon#flushed, iclass 26, count 0 2006.190.08:22:12.63#ibcon#about to write, iclass 26, count 0 2006.190.08:22:12.63#ibcon#wrote, iclass 26, count 0 2006.190.08:22:12.63#ibcon#about to read 3, iclass 26, count 0 2006.190.08:22:12.65#ibcon#read 3, iclass 26, count 0 2006.190.08:22:12.65#ibcon#about to read 4, iclass 26, count 0 2006.190.08:22:12.65#ibcon#read 4, iclass 26, count 0 2006.190.08:22:12.65#ibcon#about to read 5, iclass 26, count 0 2006.190.08:22:12.65#ibcon#read 5, iclass 26, count 0 2006.190.08:22:12.65#ibcon#about to read 6, iclass 26, count 0 2006.190.08:22:12.65#ibcon#read 6, iclass 26, count 0 2006.190.08:22:12.65#ibcon#end of sib2, iclass 26, count 0 2006.190.08:22:12.65#ibcon#*mode == 0, iclass 26, count 0 2006.190.08:22:12.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.190.08:22:12.65#ibcon#[27=USB\r\n] 2006.190.08:22:12.65#ibcon#*before write, iclass 26, count 0 2006.190.08:22:12.65#ibcon#enter sib2, iclass 26, count 0 2006.190.08:22:12.65#ibcon#flushed, iclass 26, count 0 2006.190.08:22:12.65#ibcon#about to write, iclass 26, count 0 2006.190.08:22:12.65#ibcon#wrote, iclass 26, count 0 2006.190.08:22:12.65#ibcon#about to read 3, iclass 26, count 0 2006.190.08:22:12.68#ibcon#read 3, iclass 26, count 0 2006.190.08:22:12.68#ibcon#about to read 4, iclass 26, count 0 2006.190.08:22:12.68#ibcon#read 4, iclass 26, count 0 2006.190.08:22:12.68#ibcon#about to read 5, iclass 26, count 0 2006.190.08:22:12.68#ibcon#read 5, iclass 26, count 0 2006.190.08:22:12.68#ibcon#about to read 6, iclass 26, count 0 2006.190.08:22:12.68#ibcon#read 6, iclass 26, count 0 2006.190.08:22:12.68#ibcon#end of sib2, iclass 26, count 0 2006.190.08:22:12.68#ibcon#*after write, iclass 26, count 0 2006.190.08:22:12.68#ibcon#*before return 0, iclass 26, count 0 2006.190.08:22:12.68#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:22:12.68#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.190.08:22:12.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.190.08:22:12.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.190.08:22:12.68$vc4f8/vabw=wide 2006.190.08:22:12.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.190.08:22:12.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.190.08:22:12.68#ibcon#ireg 8 cls_cnt 0 2006.190.08:22:12.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:22:12.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:22:12.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:22:12.68#ibcon#enter wrdev, iclass 28, count 0 2006.190.08:22:12.68#ibcon#first serial, iclass 28, count 0 2006.190.08:22:12.68#ibcon#enter sib2, iclass 28, count 0 2006.190.08:22:12.68#ibcon#flushed, iclass 28, count 0 2006.190.08:22:12.68#ibcon#about to write, iclass 28, count 0 2006.190.08:22:12.68#ibcon#wrote, iclass 28, count 0 2006.190.08:22:12.68#ibcon#about to read 3, iclass 28, count 0 2006.190.08:22:12.70#ibcon#read 3, iclass 28, count 0 2006.190.08:22:12.70#ibcon#about to read 4, iclass 28, count 0 2006.190.08:22:12.70#ibcon#read 4, iclass 28, count 0 2006.190.08:22:12.70#ibcon#about to read 5, iclass 28, count 0 2006.190.08:22:12.70#ibcon#read 5, iclass 28, count 0 2006.190.08:22:12.70#ibcon#about to read 6, iclass 28, count 0 2006.190.08:22:12.70#ibcon#read 6, iclass 28, count 0 2006.190.08:22:12.70#ibcon#end of sib2, iclass 28, count 0 2006.190.08:22:12.70#ibcon#*mode == 0, iclass 28, count 0 2006.190.08:22:12.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.190.08:22:12.70#ibcon#[25=BW32\r\n] 2006.190.08:22:12.70#ibcon#*before write, iclass 28, count 0 2006.190.08:22:12.70#ibcon#enter sib2, iclass 28, count 0 2006.190.08:22:12.70#ibcon#flushed, iclass 28, count 0 2006.190.08:22:12.70#ibcon#about to write, iclass 28, count 0 2006.190.08:22:12.70#ibcon#wrote, iclass 28, count 0 2006.190.08:22:12.70#ibcon#about to read 3, iclass 28, count 0 2006.190.08:22:12.73#ibcon#read 3, iclass 28, count 0 2006.190.08:22:12.73#ibcon#about to read 4, iclass 28, count 0 2006.190.08:22:12.73#ibcon#read 4, iclass 28, count 0 2006.190.08:22:12.73#ibcon#about to read 5, iclass 28, count 0 2006.190.08:22:12.73#ibcon#read 5, iclass 28, count 0 2006.190.08:22:12.73#ibcon#about to read 6, iclass 28, count 0 2006.190.08:22:12.73#ibcon#read 6, iclass 28, count 0 2006.190.08:22:12.73#ibcon#end of sib2, iclass 28, count 0 2006.190.08:22:12.73#ibcon#*after write, iclass 28, count 0 2006.190.08:22:12.73#ibcon#*before return 0, iclass 28, count 0 2006.190.08:22:12.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:22:12.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.190.08:22:12.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.190.08:22:12.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.190.08:22:12.73$vc4f8/vbbw=wide 2006.190.08:22:12.73#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.190.08:22:12.73#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.190.08:22:12.73#ibcon#ireg 8 cls_cnt 0 2006.190.08:22:12.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:22:12.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:22:12.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:22:12.80#ibcon#enter wrdev, iclass 30, count 0 2006.190.08:22:12.80#ibcon#first serial, iclass 30, count 0 2006.190.08:22:12.80#ibcon#enter sib2, iclass 30, count 0 2006.190.08:22:12.80#ibcon#flushed, iclass 30, count 0 2006.190.08:22:12.80#ibcon#about to write, iclass 30, count 0 2006.190.08:22:12.80#ibcon#wrote, iclass 30, count 0 2006.190.08:22:12.80#ibcon#about to read 3, iclass 30, count 0 2006.190.08:22:12.82#ibcon#read 3, iclass 30, count 0 2006.190.08:22:12.82#ibcon#about to read 4, iclass 30, count 0 2006.190.08:22:12.82#ibcon#read 4, iclass 30, count 0 2006.190.08:22:12.82#ibcon#about to read 5, iclass 30, count 0 2006.190.08:22:12.82#ibcon#read 5, iclass 30, count 0 2006.190.08:22:12.82#ibcon#about to read 6, iclass 30, count 0 2006.190.08:22:12.82#ibcon#read 6, iclass 30, count 0 2006.190.08:22:12.82#ibcon#end of sib2, iclass 30, count 0 2006.190.08:22:12.82#ibcon#*mode == 0, iclass 30, count 0 2006.190.08:22:12.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.190.08:22:12.82#ibcon#[27=BW32\r\n] 2006.190.08:22:12.82#ibcon#*before write, iclass 30, count 0 2006.190.08:22:12.82#ibcon#enter sib2, iclass 30, count 0 2006.190.08:22:12.82#ibcon#flushed, iclass 30, count 0 2006.190.08:22:12.82#ibcon#about to write, iclass 30, count 0 2006.190.08:22:12.82#ibcon#wrote, iclass 30, count 0 2006.190.08:22:12.82#ibcon#about to read 3, iclass 30, count 0 2006.190.08:22:12.85#ibcon#read 3, iclass 30, count 0 2006.190.08:22:12.85#ibcon#about to read 4, iclass 30, count 0 2006.190.08:22:12.85#ibcon#read 4, iclass 30, count 0 2006.190.08:22:12.85#ibcon#about to read 5, iclass 30, count 0 2006.190.08:22:12.85#ibcon#read 5, iclass 30, count 0 2006.190.08:22:12.85#ibcon#about to read 6, iclass 30, count 0 2006.190.08:22:12.85#ibcon#read 6, iclass 30, count 0 2006.190.08:22:12.85#ibcon#end of sib2, iclass 30, count 0 2006.190.08:22:12.85#ibcon#*after write, iclass 30, count 0 2006.190.08:22:12.85#ibcon#*before return 0, iclass 30, count 0 2006.190.08:22:12.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:22:12.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.190.08:22:12.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.190.08:22:12.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.190.08:22:12.85$4f8m12a/ifd4f 2006.190.08:22:12.85$ifd4f/lo= 2006.190.08:22:12.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:22:12.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:22:12.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:22:12.85$ifd4f/patch= 2006.190.08:22:12.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:22:12.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:22:12.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:22:12.85$4f8m12a/"form=m,16.000,1:2 2006.190.08:22:12.85$4f8m12a/"tpicd 2006.190.08:22:12.85$4f8m12a/echo=off 2006.190.08:22:12.85$4f8m12a/xlog=off 2006.190.08:22:12.85:!2006.190.08:24:20 2006.190.08:22:58.14#trakl#Source acquired 2006.190.08:22:58.14#flagr#flagr/antenna,acquired 2006.190.08:24:20.00:preob 2006.190.08:24:20.14/onsource/TRACKING 2006.190.08:24:20.14:!2006.190.08:24:30 2006.190.08:24:30.00:data_valid=on 2006.190.08:24:30.00:midob 2006.190.08:24:31.14/onsource/TRACKING 2006.190.08:24:31.14/wx/24.40,1012.2,100 2006.190.08:24:31.25/cable/+6.4710E-03 2006.190.08:24:32.34/va/01,08,usb,yes,30,32 2006.190.08:24:32.34/va/02,07,usb,yes,31,32 2006.190.08:24:32.34/va/03,06,usb,yes,32,32 2006.190.08:24:32.34/va/04,07,usb,yes,32,34 2006.190.08:24:32.34/va/05,07,usb,yes,35,37 2006.190.08:24:32.34/va/06,06,usb,yes,34,34 2006.190.08:24:32.34/va/07,06,usb,yes,34,34 2006.190.08:24:32.34/va/08,06,usb,yes,37,36 2006.190.08:24:32.57/valo/01,532.99,yes,locked 2006.190.08:24:32.57/valo/02,572.99,yes,locked 2006.190.08:24:32.57/valo/03,672.99,yes,locked 2006.190.08:24:32.57/valo/04,832.99,yes,locked 2006.190.08:24:32.57/valo/05,652.99,yes,locked 2006.190.08:24:32.57/valo/06,772.99,yes,locked 2006.190.08:24:32.57/valo/07,832.99,yes,locked 2006.190.08:24:32.57/valo/08,852.99,yes,locked 2006.190.08:24:33.66/vb/01,04,usb,yes,29,27 2006.190.08:24:33.66/vb/02,04,usb,yes,31,32 2006.190.08:24:33.66/vb/03,04,usb,yes,27,31 2006.190.08:24:33.66/vb/04,04,usb,yes,28,28 2006.190.08:24:33.66/vb/05,04,usb,yes,27,30 2006.190.08:24:33.66/vb/06,04,usb,yes,27,30 2006.190.08:24:33.66/vb/07,04,usb,yes,29,29 2006.190.08:24:33.66/vb/08,04,usb,yes,27,30 2006.190.08:24:33.89/vblo/01,632.99,yes,locked 2006.190.08:24:33.89/vblo/02,640.99,yes,locked 2006.190.08:24:33.89/vblo/03,656.99,yes,locked 2006.190.08:24:33.89/vblo/04,712.99,yes,locked 2006.190.08:24:33.89/vblo/05,744.99,yes,locked 2006.190.08:24:33.89/vblo/06,752.99,yes,locked 2006.190.08:24:33.89/vblo/07,734.99,yes,locked 2006.190.08:24:33.89/vblo/08,744.99,yes,locked 2006.190.08:24:34.04/vabw/8 2006.190.08:24:34.19/vbbw/8 2006.190.08:24:34.31/xfe/off,on,15.2 2006.190.08:24:34.69/ifatt/23,28,28,28 2006.190.08:24:35.08/fmout-gps/S +2.89E-07 2006.190.08:24:35.16:!2006.190.08:25:30 2006.190.08:25:30.01:data_valid=off 2006.190.08:25:30.01:postob 2006.190.08:25:30.13/cable/+6.4711E-03 2006.190.08:25:30.13/wx/24.39,1012.2,100 2006.190.08:25:31.07/fmout-gps/S +2.90E-07 2006.190.08:25:31.07:scan_name=190-0826,k06190,60 2006.190.08:25:31.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.190.08:25:31.14#flagr#flagr/antenna,new-source 2006.190.08:25:32.14:checkk5 2006.190.08:25:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.190.08:25:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.190.08:25:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.190.08:25:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.190.08:25:34.04/chk_obsdata//k5ts1/T1900824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:25:34.42/chk_obsdata//k5ts2/T1900824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:25:34.79/chk_obsdata//k5ts3/T1900824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:25:35.17/chk_obsdata//k5ts4/T1900824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.190.08:25:35.87/k5log//k5ts1_log_newline 2006.190.08:25:36.58/k5log//k5ts2_log_newline 2006.190.08:25:37.27/k5log//k5ts3_log_newline 2006.190.08:25:37.97/k5log//k5ts4_log_newline 2006.190.08:25:38.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:25:38.00:4f8m12a=3 2006.190.08:25:38.00$4f8m12a/echo=on 2006.190.08:25:38.00$4f8m12a/pcalon 2006.190.08:25:38.00$pcalon/"no phase cal control is implemented here 2006.190.08:25:38.00$4f8m12a/"tpicd=stop 2006.190.08:25:38.00$4f8m12a/vc4f8 2006.190.08:25:38.00$vc4f8/valo=1,532.99 2006.190.08:25:38.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.08:25:38.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.08:25:38.01#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:38.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:38.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:38.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:38.01#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:25:38.01#ibcon#first serial, iclass 3, count 0 2006.190.08:25:38.01#ibcon#enter sib2, iclass 3, count 0 2006.190.08:25:38.01#ibcon#flushed, iclass 3, count 0 2006.190.08:25:38.01#ibcon#about to write, iclass 3, count 0 2006.190.08:25:38.01#ibcon#wrote, iclass 3, count 0 2006.190.08:25:38.01#ibcon#about to read 3, iclass 3, count 0 2006.190.08:25:38.05#ibcon#read 3, iclass 3, count 0 2006.190.08:25:38.05#ibcon#about to read 4, iclass 3, count 0 2006.190.08:25:38.05#ibcon#read 4, iclass 3, count 0 2006.190.08:25:38.05#ibcon#about to read 5, iclass 3, count 0 2006.190.08:25:38.05#ibcon#read 5, iclass 3, count 0 2006.190.08:25:38.05#ibcon#about to read 6, iclass 3, count 0 2006.190.08:25:38.05#ibcon#read 6, iclass 3, count 0 2006.190.08:25:38.05#ibcon#end of sib2, iclass 3, count 0 2006.190.08:25:38.05#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:25:38.05#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:25:38.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.190.08:25:38.05#ibcon#*before write, iclass 3, count 0 2006.190.08:25:38.05#ibcon#enter sib2, iclass 3, count 0 2006.190.08:25:38.05#ibcon#flushed, iclass 3, count 0 2006.190.08:25:38.05#ibcon#about to write, iclass 3, count 0 2006.190.08:25:38.05#ibcon#wrote, iclass 3, count 0 2006.190.08:25:38.05#ibcon#about to read 3, iclass 3, count 0 2006.190.08:25:38.10#ibcon#read 3, iclass 3, count 0 2006.190.08:25:38.10#ibcon#about to read 4, iclass 3, count 0 2006.190.08:25:38.10#ibcon#read 4, iclass 3, count 0 2006.190.08:25:38.10#ibcon#about to read 5, iclass 3, count 0 2006.190.08:25:38.10#ibcon#read 5, iclass 3, count 0 2006.190.08:25:38.10#ibcon#about to read 6, iclass 3, count 0 2006.190.08:25:38.10#ibcon#read 6, iclass 3, count 0 2006.190.08:25:38.10#ibcon#end of sib2, iclass 3, count 0 2006.190.08:25:38.10#ibcon#*after write, iclass 3, count 0 2006.190.08:25:38.10#ibcon#*before return 0, iclass 3, count 0 2006.190.08:25:38.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:38.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:38.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:25:38.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:25:38.10$vc4f8/va=1,8 2006.190.08:25:38.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.08:25:38.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.08:25:38.10#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:38.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:38.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:38.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:38.10#ibcon#enter wrdev, iclass 5, count 2 2006.190.08:25:38.10#ibcon#first serial, iclass 5, count 2 2006.190.08:25:38.10#ibcon#enter sib2, iclass 5, count 2 2006.190.08:25:38.10#ibcon#flushed, iclass 5, count 2 2006.190.08:25:38.10#ibcon#about to write, iclass 5, count 2 2006.190.08:25:38.10#ibcon#wrote, iclass 5, count 2 2006.190.08:25:38.10#ibcon#about to read 3, iclass 5, count 2 2006.190.08:25:38.12#ibcon#read 3, iclass 5, count 2 2006.190.08:25:38.12#ibcon#about to read 4, iclass 5, count 2 2006.190.08:25:38.12#ibcon#read 4, iclass 5, count 2 2006.190.08:25:38.12#ibcon#about to read 5, iclass 5, count 2 2006.190.08:25:38.12#ibcon#read 5, iclass 5, count 2 2006.190.08:25:38.12#ibcon#about to read 6, iclass 5, count 2 2006.190.08:25:38.12#ibcon#read 6, iclass 5, count 2 2006.190.08:25:38.12#ibcon#end of sib2, iclass 5, count 2 2006.190.08:25:38.12#ibcon#*mode == 0, iclass 5, count 2 2006.190.08:25:38.12#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.08:25:38.12#ibcon#[25=AT01-08\r\n] 2006.190.08:25:38.12#ibcon#*before write, iclass 5, count 2 2006.190.08:25:38.12#ibcon#enter sib2, iclass 5, count 2 2006.190.08:25:38.12#ibcon#flushed, iclass 5, count 2 2006.190.08:25:38.12#ibcon#about to write, iclass 5, count 2 2006.190.08:25:38.12#ibcon#wrote, iclass 5, count 2 2006.190.08:25:38.12#ibcon#about to read 3, iclass 5, count 2 2006.190.08:25:38.15#ibcon#read 3, iclass 5, count 2 2006.190.08:25:38.15#ibcon#about to read 4, iclass 5, count 2 2006.190.08:25:38.15#ibcon#read 4, iclass 5, count 2 2006.190.08:25:38.15#ibcon#about to read 5, iclass 5, count 2 2006.190.08:25:38.15#ibcon#read 5, iclass 5, count 2 2006.190.08:25:38.15#ibcon#about to read 6, iclass 5, count 2 2006.190.08:25:38.15#ibcon#read 6, iclass 5, count 2 2006.190.08:25:38.15#ibcon#end of sib2, iclass 5, count 2 2006.190.08:25:38.15#ibcon#*after write, iclass 5, count 2 2006.190.08:25:38.15#ibcon#*before return 0, iclass 5, count 2 2006.190.08:25:38.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:38.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:38.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.08:25:38.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:38.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:38.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:38.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:38.27#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:25:38.27#ibcon#first serial, iclass 5, count 0 2006.190.08:25:38.27#ibcon#enter sib2, iclass 5, count 0 2006.190.08:25:38.27#ibcon#flushed, iclass 5, count 0 2006.190.08:25:38.27#ibcon#about to write, iclass 5, count 0 2006.190.08:25:38.27#ibcon#wrote, iclass 5, count 0 2006.190.08:25:38.27#ibcon#about to read 3, iclass 5, count 0 2006.190.08:25:38.29#ibcon#read 3, iclass 5, count 0 2006.190.08:25:38.29#ibcon#about to read 4, iclass 5, count 0 2006.190.08:25:38.29#ibcon#read 4, iclass 5, count 0 2006.190.08:25:38.29#ibcon#about to read 5, iclass 5, count 0 2006.190.08:25:38.29#ibcon#read 5, iclass 5, count 0 2006.190.08:25:38.29#ibcon#about to read 6, iclass 5, count 0 2006.190.08:25:38.29#ibcon#read 6, iclass 5, count 0 2006.190.08:25:38.29#ibcon#end of sib2, iclass 5, count 0 2006.190.08:25:38.29#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:25:38.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:25:38.29#ibcon#[25=USB\r\n] 2006.190.08:25:38.29#ibcon#*before write, iclass 5, count 0 2006.190.08:25:38.29#ibcon#enter sib2, iclass 5, count 0 2006.190.08:25:38.29#ibcon#flushed, iclass 5, count 0 2006.190.08:25:38.29#ibcon#about to write, iclass 5, count 0 2006.190.08:25:38.29#ibcon#wrote, iclass 5, count 0 2006.190.08:25:38.29#ibcon#about to read 3, iclass 5, count 0 2006.190.08:25:38.32#ibcon#read 3, iclass 5, count 0 2006.190.08:25:38.32#ibcon#about to read 4, iclass 5, count 0 2006.190.08:25:38.32#ibcon#read 4, iclass 5, count 0 2006.190.08:25:38.32#ibcon#about to read 5, iclass 5, count 0 2006.190.08:25:38.32#ibcon#read 5, iclass 5, count 0 2006.190.08:25:38.32#ibcon#about to read 6, iclass 5, count 0 2006.190.08:25:38.32#ibcon#read 6, iclass 5, count 0 2006.190.08:25:38.32#ibcon#end of sib2, iclass 5, count 0 2006.190.08:25:38.32#ibcon#*after write, iclass 5, count 0 2006.190.08:25:38.32#ibcon#*before return 0, iclass 5, count 0 2006.190.08:25:38.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:38.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:38.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:25:38.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:25:38.32$vc4f8/valo=2,572.99 2006.190.08:25:38.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.08:25:38.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.08:25:38.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:38.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:38.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:38.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:38.32#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:25:38.32#ibcon#first serial, iclass 7, count 0 2006.190.08:25:38.32#ibcon#enter sib2, iclass 7, count 0 2006.190.08:25:38.32#ibcon#flushed, iclass 7, count 0 2006.190.08:25:38.32#ibcon#about to write, iclass 7, count 0 2006.190.08:25:38.32#ibcon#wrote, iclass 7, count 0 2006.190.08:25:38.32#ibcon#about to read 3, iclass 7, count 0 2006.190.08:25:38.34#ibcon#read 3, iclass 7, count 0 2006.190.08:25:38.34#ibcon#about to read 4, iclass 7, count 0 2006.190.08:25:38.34#ibcon#read 4, iclass 7, count 0 2006.190.08:25:38.34#ibcon#about to read 5, iclass 7, count 0 2006.190.08:25:38.34#ibcon#read 5, iclass 7, count 0 2006.190.08:25:38.34#ibcon#about to read 6, iclass 7, count 0 2006.190.08:25:38.34#ibcon#read 6, iclass 7, count 0 2006.190.08:25:38.34#ibcon#end of sib2, iclass 7, count 0 2006.190.08:25:38.34#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:25:38.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:25:38.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.190.08:25:38.34#ibcon#*before write, iclass 7, count 0 2006.190.08:25:38.34#ibcon#enter sib2, iclass 7, count 0 2006.190.08:25:38.34#ibcon#flushed, iclass 7, count 0 2006.190.08:25:38.34#ibcon#about to write, iclass 7, count 0 2006.190.08:25:38.34#ibcon#wrote, iclass 7, count 0 2006.190.08:25:38.34#ibcon#about to read 3, iclass 7, count 0 2006.190.08:25:38.38#ibcon#read 3, iclass 7, count 0 2006.190.08:25:38.38#ibcon#about to read 4, iclass 7, count 0 2006.190.08:25:38.38#ibcon#read 4, iclass 7, count 0 2006.190.08:25:38.38#ibcon#about to read 5, iclass 7, count 0 2006.190.08:25:38.38#ibcon#read 5, iclass 7, count 0 2006.190.08:25:38.38#ibcon#about to read 6, iclass 7, count 0 2006.190.08:25:38.38#ibcon#read 6, iclass 7, count 0 2006.190.08:25:38.38#ibcon#end of sib2, iclass 7, count 0 2006.190.08:25:38.38#ibcon#*after write, iclass 7, count 0 2006.190.08:25:38.38#ibcon#*before return 0, iclass 7, count 0 2006.190.08:25:38.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:38.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:38.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:25:38.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:25:38.38$vc4f8/va=2,7 2006.190.08:25:38.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.08:25:38.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.08:25:38.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:38.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:38.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:38.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:38.44#ibcon#enter wrdev, iclass 11, count 2 2006.190.08:25:38.44#ibcon#first serial, iclass 11, count 2 2006.190.08:25:38.44#ibcon#enter sib2, iclass 11, count 2 2006.190.08:25:38.44#ibcon#flushed, iclass 11, count 2 2006.190.08:25:38.44#ibcon#about to write, iclass 11, count 2 2006.190.08:25:38.44#ibcon#wrote, iclass 11, count 2 2006.190.08:25:38.44#ibcon#about to read 3, iclass 11, count 2 2006.190.08:25:38.46#ibcon#read 3, iclass 11, count 2 2006.190.08:25:38.46#ibcon#about to read 4, iclass 11, count 2 2006.190.08:25:38.46#ibcon#read 4, iclass 11, count 2 2006.190.08:25:38.46#ibcon#about to read 5, iclass 11, count 2 2006.190.08:25:38.46#ibcon#read 5, iclass 11, count 2 2006.190.08:25:38.46#ibcon#about to read 6, iclass 11, count 2 2006.190.08:25:38.46#ibcon#read 6, iclass 11, count 2 2006.190.08:25:38.46#ibcon#end of sib2, iclass 11, count 2 2006.190.08:25:38.46#ibcon#*mode == 0, iclass 11, count 2 2006.190.08:25:38.46#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.08:25:38.46#ibcon#[25=AT02-07\r\n] 2006.190.08:25:38.46#ibcon#*before write, iclass 11, count 2 2006.190.08:25:38.46#ibcon#enter sib2, iclass 11, count 2 2006.190.08:25:38.46#ibcon#flushed, iclass 11, count 2 2006.190.08:25:38.46#ibcon#about to write, iclass 11, count 2 2006.190.08:25:38.46#ibcon#wrote, iclass 11, count 2 2006.190.08:25:38.46#ibcon#about to read 3, iclass 11, count 2 2006.190.08:25:38.49#ibcon#read 3, iclass 11, count 2 2006.190.08:25:38.49#ibcon#about to read 4, iclass 11, count 2 2006.190.08:25:38.49#ibcon#read 4, iclass 11, count 2 2006.190.08:25:38.49#ibcon#about to read 5, iclass 11, count 2 2006.190.08:25:38.49#ibcon#read 5, iclass 11, count 2 2006.190.08:25:38.49#ibcon#about to read 6, iclass 11, count 2 2006.190.08:25:38.49#ibcon#read 6, iclass 11, count 2 2006.190.08:25:38.49#ibcon#end of sib2, iclass 11, count 2 2006.190.08:25:38.49#ibcon#*after write, iclass 11, count 2 2006.190.08:25:38.49#ibcon#*before return 0, iclass 11, count 2 2006.190.08:25:38.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:38.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:38.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.08:25:38.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:38.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:38.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:38.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:38.61#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:25:38.61#ibcon#first serial, iclass 11, count 0 2006.190.08:25:38.61#ibcon#enter sib2, iclass 11, count 0 2006.190.08:25:38.61#ibcon#flushed, iclass 11, count 0 2006.190.08:25:38.61#ibcon#about to write, iclass 11, count 0 2006.190.08:25:38.61#ibcon#wrote, iclass 11, count 0 2006.190.08:25:38.61#ibcon#about to read 3, iclass 11, count 0 2006.190.08:25:38.63#ibcon#read 3, iclass 11, count 0 2006.190.08:25:38.63#ibcon#about to read 4, iclass 11, count 0 2006.190.08:25:38.63#ibcon#read 4, iclass 11, count 0 2006.190.08:25:38.63#ibcon#about to read 5, iclass 11, count 0 2006.190.08:25:38.63#ibcon#read 5, iclass 11, count 0 2006.190.08:25:38.63#ibcon#about to read 6, iclass 11, count 0 2006.190.08:25:38.63#ibcon#read 6, iclass 11, count 0 2006.190.08:25:38.63#ibcon#end of sib2, iclass 11, count 0 2006.190.08:25:38.63#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:25:38.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:25:38.63#ibcon#[25=USB\r\n] 2006.190.08:25:38.63#ibcon#*before write, iclass 11, count 0 2006.190.08:25:38.63#ibcon#enter sib2, iclass 11, count 0 2006.190.08:25:38.63#ibcon#flushed, iclass 11, count 0 2006.190.08:25:38.63#ibcon#about to write, iclass 11, count 0 2006.190.08:25:38.63#ibcon#wrote, iclass 11, count 0 2006.190.08:25:38.63#ibcon#about to read 3, iclass 11, count 0 2006.190.08:25:38.66#ibcon#read 3, iclass 11, count 0 2006.190.08:25:38.66#ibcon#about to read 4, iclass 11, count 0 2006.190.08:25:38.66#ibcon#read 4, iclass 11, count 0 2006.190.08:25:38.66#ibcon#about to read 5, iclass 11, count 0 2006.190.08:25:38.66#ibcon#read 5, iclass 11, count 0 2006.190.08:25:38.66#ibcon#about to read 6, iclass 11, count 0 2006.190.08:25:38.66#ibcon#read 6, iclass 11, count 0 2006.190.08:25:38.66#ibcon#end of sib2, iclass 11, count 0 2006.190.08:25:38.66#ibcon#*after write, iclass 11, count 0 2006.190.08:25:38.66#ibcon#*before return 0, iclass 11, count 0 2006.190.08:25:38.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:38.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:38.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:25:38.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:25:38.66$vc4f8/valo=3,672.99 2006.190.08:25:38.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.08:25:38.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.08:25:38.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:38.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:38.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:38.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:38.66#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:25:38.66#ibcon#first serial, iclass 13, count 0 2006.190.08:25:38.66#ibcon#enter sib2, iclass 13, count 0 2006.190.08:25:38.66#ibcon#flushed, iclass 13, count 0 2006.190.08:25:38.66#ibcon#about to write, iclass 13, count 0 2006.190.08:25:38.66#ibcon#wrote, iclass 13, count 0 2006.190.08:25:38.66#ibcon#about to read 3, iclass 13, count 0 2006.190.08:25:38.68#ibcon#read 3, iclass 13, count 0 2006.190.08:25:38.68#ibcon#about to read 4, iclass 13, count 0 2006.190.08:25:38.68#ibcon#read 4, iclass 13, count 0 2006.190.08:25:38.68#ibcon#about to read 5, iclass 13, count 0 2006.190.08:25:38.68#ibcon#read 5, iclass 13, count 0 2006.190.08:25:38.68#ibcon#about to read 6, iclass 13, count 0 2006.190.08:25:38.68#ibcon#read 6, iclass 13, count 0 2006.190.08:25:38.68#ibcon#end of sib2, iclass 13, count 0 2006.190.08:25:38.68#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:25:38.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:25:38.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.190.08:25:38.68#ibcon#*before write, iclass 13, count 0 2006.190.08:25:38.68#ibcon#enter sib2, iclass 13, count 0 2006.190.08:25:38.68#ibcon#flushed, iclass 13, count 0 2006.190.08:25:38.68#ibcon#about to write, iclass 13, count 0 2006.190.08:25:38.68#ibcon#wrote, iclass 13, count 0 2006.190.08:25:38.68#ibcon#about to read 3, iclass 13, count 0 2006.190.08:25:38.72#ibcon#read 3, iclass 13, count 0 2006.190.08:25:38.72#ibcon#about to read 4, iclass 13, count 0 2006.190.08:25:38.72#ibcon#read 4, iclass 13, count 0 2006.190.08:25:38.72#ibcon#about to read 5, iclass 13, count 0 2006.190.08:25:38.72#ibcon#read 5, iclass 13, count 0 2006.190.08:25:38.72#ibcon#about to read 6, iclass 13, count 0 2006.190.08:25:38.72#ibcon#read 6, iclass 13, count 0 2006.190.08:25:38.72#ibcon#end of sib2, iclass 13, count 0 2006.190.08:25:38.72#ibcon#*after write, iclass 13, count 0 2006.190.08:25:38.72#ibcon#*before return 0, iclass 13, count 0 2006.190.08:25:38.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:38.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:38.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:25:38.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:25:38.72$vc4f8/va=3,6 2006.190.08:25:38.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.08:25:38.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.08:25:38.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:38.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:38.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:38.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:38.78#ibcon#enter wrdev, iclass 15, count 2 2006.190.08:25:38.78#ibcon#first serial, iclass 15, count 2 2006.190.08:25:38.78#ibcon#enter sib2, iclass 15, count 2 2006.190.08:25:38.78#ibcon#flushed, iclass 15, count 2 2006.190.08:25:38.78#ibcon#about to write, iclass 15, count 2 2006.190.08:25:38.78#ibcon#wrote, iclass 15, count 2 2006.190.08:25:38.78#ibcon#about to read 3, iclass 15, count 2 2006.190.08:25:38.80#ibcon#read 3, iclass 15, count 2 2006.190.08:25:38.80#ibcon#about to read 4, iclass 15, count 2 2006.190.08:25:38.80#ibcon#read 4, iclass 15, count 2 2006.190.08:25:38.80#ibcon#about to read 5, iclass 15, count 2 2006.190.08:25:38.80#ibcon#read 5, iclass 15, count 2 2006.190.08:25:38.80#ibcon#about to read 6, iclass 15, count 2 2006.190.08:25:38.80#ibcon#read 6, iclass 15, count 2 2006.190.08:25:38.80#ibcon#end of sib2, iclass 15, count 2 2006.190.08:25:38.80#ibcon#*mode == 0, iclass 15, count 2 2006.190.08:25:38.80#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.08:25:38.80#ibcon#[25=AT03-06\r\n] 2006.190.08:25:38.80#ibcon#*before write, iclass 15, count 2 2006.190.08:25:38.80#ibcon#enter sib2, iclass 15, count 2 2006.190.08:25:38.80#ibcon#flushed, iclass 15, count 2 2006.190.08:25:38.80#ibcon#about to write, iclass 15, count 2 2006.190.08:25:38.80#ibcon#wrote, iclass 15, count 2 2006.190.08:25:38.80#ibcon#about to read 3, iclass 15, count 2 2006.190.08:25:38.83#ibcon#read 3, iclass 15, count 2 2006.190.08:25:38.83#ibcon#about to read 4, iclass 15, count 2 2006.190.08:25:38.83#ibcon#read 4, iclass 15, count 2 2006.190.08:25:38.83#ibcon#about to read 5, iclass 15, count 2 2006.190.08:25:38.83#ibcon#read 5, iclass 15, count 2 2006.190.08:25:38.83#ibcon#about to read 6, iclass 15, count 2 2006.190.08:25:38.83#ibcon#read 6, iclass 15, count 2 2006.190.08:25:38.83#ibcon#end of sib2, iclass 15, count 2 2006.190.08:25:38.83#ibcon#*after write, iclass 15, count 2 2006.190.08:25:38.83#ibcon#*before return 0, iclass 15, count 2 2006.190.08:25:38.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:38.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:38.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.08:25:38.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:38.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:38.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:38.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:38.95#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:25:38.95#ibcon#first serial, iclass 15, count 0 2006.190.08:25:38.95#ibcon#enter sib2, iclass 15, count 0 2006.190.08:25:38.95#ibcon#flushed, iclass 15, count 0 2006.190.08:25:38.95#ibcon#about to write, iclass 15, count 0 2006.190.08:25:38.95#ibcon#wrote, iclass 15, count 0 2006.190.08:25:38.95#ibcon#about to read 3, iclass 15, count 0 2006.190.08:25:38.97#ibcon#read 3, iclass 15, count 0 2006.190.08:25:38.97#ibcon#about to read 4, iclass 15, count 0 2006.190.08:25:38.97#ibcon#read 4, iclass 15, count 0 2006.190.08:25:38.97#ibcon#about to read 5, iclass 15, count 0 2006.190.08:25:38.97#ibcon#read 5, iclass 15, count 0 2006.190.08:25:38.97#ibcon#about to read 6, iclass 15, count 0 2006.190.08:25:38.97#ibcon#read 6, iclass 15, count 0 2006.190.08:25:38.97#ibcon#end of sib2, iclass 15, count 0 2006.190.08:25:38.97#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:25:38.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:25:38.97#ibcon#[25=USB\r\n] 2006.190.08:25:38.97#ibcon#*before write, iclass 15, count 0 2006.190.08:25:38.97#ibcon#enter sib2, iclass 15, count 0 2006.190.08:25:38.97#ibcon#flushed, iclass 15, count 0 2006.190.08:25:38.97#ibcon#about to write, iclass 15, count 0 2006.190.08:25:38.97#ibcon#wrote, iclass 15, count 0 2006.190.08:25:38.97#ibcon#about to read 3, iclass 15, count 0 2006.190.08:25:39.00#ibcon#read 3, iclass 15, count 0 2006.190.08:25:39.00#ibcon#about to read 4, iclass 15, count 0 2006.190.08:25:39.00#ibcon#read 4, iclass 15, count 0 2006.190.08:25:39.00#ibcon#about to read 5, iclass 15, count 0 2006.190.08:25:39.00#ibcon#read 5, iclass 15, count 0 2006.190.08:25:39.00#ibcon#about to read 6, iclass 15, count 0 2006.190.08:25:39.00#ibcon#read 6, iclass 15, count 0 2006.190.08:25:39.00#ibcon#end of sib2, iclass 15, count 0 2006.190.08:25:39.00#ibcon#*after write, iclass 15, count 0 2006.190.08:25:39.00#ibcon#*before return 0, iclass 15, count 0 2006.190.08:25:39.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:39.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:39.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:25:39.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:25:39.00$vc4f8/valo=4,832.99 2006.190.08:25:39.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.08:25:39.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.08:25:39.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:39.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:39.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:39.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:39.00#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:25:39.00#ibcon#first serial, iclass 17, count 0 2006.190.08:25:39.00#ibcon#enter sib2, iclass 17, count 0 2006.190.08:25:39.00#ibcon#flushed, iclass 17, count 0 2006.190.08:25:39.00#ibcon#about to write, iclass 17, count 0 2006.190.08:25:39.00#ibcon#wrote, iclass 17, count 0 2006.190.08:25:39.00#ibcon#about to read 3, iclass 17, count 0 2006.190.08:25:39.02#ibcon#read 3, iclass 17, count 0 2006.190.08:25:39.02#ibcon#about to read 4, iclass 17, count 0 2006.190.08:25:39.02#ibcon#read 4, iclass 17, count 0 2006.190.08:25:39.02#ibcon#about to read 5, iclass 17, count 0 2006.190.08:25:39.02#ibcon#read 5, iclass 17, count 0 2006.190.08:25:39.02#ibcon#about to read 6, iclass 17, count 0 2006.190.08:25:39.02#ibcon#read 6, iclass 17, count 0 2006.190.08:25:39.02#ibcon#end of sib2, iclass 17, count 0 2006.190.08:25:39.02#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:25:39.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:25:39.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.190.08:25:39.02#ibcon#*before write, iclass 17, count 0 2006.190.08:25:39.02#ibcon#enter sib2, iclass 17, count 0 2006.190.08:25:39.02#ibcon#flushed, iclass 17, count 0 2006.190.08:25:39.02#ibcon#about to write, iclass 17, count 0 2006.190.08:25:39.02#ibcon#wrote, iclass 17, count 0 2006.190.08:25:39.02#ibcon#about to read 3, iclass 17, count 0 2006.190.08:25:39.06#ibcon#read 3, iclass 17, count 0 2006.190.08:25:39.06#ibcon#about to read 4, iclass 17, count 0 2006.190.08:25:39.06#ibcon#read 4, iclass 17, count 0 2006.190.08:25:39.06#ibcon#about to read 5, iclass 17, count 0 2006.190.08:25:39.06#ibcon#read 5, iclass 17, count 0 2006.190.08:25:39.06#ibcon#about to read 6, iclass 17, count 0 2006.190.08:25:39.06#ibcon#read 6, iclass 17, count 0 2006.190.08:25:39.06#ibcon#end of sib2, iclass 17, count 0 2006.190.08:25:39.06#ibcon#*after write, iclass 17, count 0 2006.190.08:25:39.06#ibcon#*before return 0, iclass 17, count 0 2006.190.08:25:39.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:39.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:39.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:25:39.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:25:39.06$vc4f8/va=4,7 2006.190.08:25:39.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.08:25:39.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.08:25:39.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:39.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:39.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:39.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:39.12#ibcon#enter wrdev, iclass 19, count 2 2006.190.08:25:39.12#ibcon#first serial, iclass 19, count 2 2006.190.08:25:39.12#ibcon#enter sib2, iclass 19, count 2 2006.190.08:25:39.12#ibcon#flushed, iclass 19, count 2 2006.190.08:25:39.12#ibcon#about to write, iclass 19, count 2 2006.190.08:25:39.12#ibcon#wrote, iclass 19, count 2 2006.190.08:25:39.12#ibcon#about to read 3, iclass 19, count 2 2006.190.08:25:39.14#ibcon#read 3, iclass 19, count 2 2006.190.08:25:39.14#ibcon#about to read 4, iclass 19, count 2 2006.190.08:25:39.14#ibcon#read 4, iclass 19, count 2 2006.190.08:25:39.14#ibcon#about to read 5, iclass 19, count 2 2006.190.08:25:39.14#ibcon#read 5, iclass 19, count 2 2006.190.08:25:39.14#ibcon#about to read 6, iclass 19, count 2 2006.190.08:25:39.14#ibcon#read 6, iclass 19, count 2 2006.190.08:25:39.14#ibcon#end of sib2, iclass 19, count 2 2006.190.08:25:39.14#ibcon#*mode == 0, iclass 19, count 2 2006.190.08:25:39.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.08:25:39.14#ibcon#[25=AT04-07\r\n] 2006.190.08:25:39.14#ibcon#*before write, iclass 19, count 2 2006.190.08:25:39.14#ibcon#enter sib2, iclass 19, count 2 2006.190.08:25:39.14#ibcon#flushed, iclass 19, count 2 2006.190.08:25:39.14#ibcon#about to write, iclass 19, count 2 2006.190.08:25:39.14#ibcon#wrote, iclass 19, count 2 2006.190.08:25:39.14#ibcon#about to read 3, iclass 19, count 2 2006.190.08:25:39.17#ibcon#read 3, iclass 19, count 2 2006.190.08:25:39.17#ibcon#about to read 4, iclass 19, count 2 2006.190.08:25:39.17#ibcon#read 4, iclass 19, count 2 2006.190.08:25:39.17#ibcon#about to read 5, iclass 19, count 2 2006.190.08:25:39.17#ibcon#read 5, iclass 19, count 2 2006.190.08:25:39.17#ibcon#about to read 6, iclass 19, count 2 2006.190.08:25:39.17#ibcon#read 6, iclass 19, count 2 2006.190.08:25:39.17#ibcon#end of sib2, iclass 19, count 2 2006.190.08:25:39.17#ibcon#*after write, iclass 19, count 2 2006.190.08:25:39.17#ibcon#*before return 0, iclass 19, count 2 2006.190.08:25:39.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:39.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:39.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.08:25:39.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:39.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:39.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:39.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:39.29#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:25:39.29#ibcon#first serial, iclass 19, count 0 2006.190.08:25:39.29#ibcon#enter sib2, iclass 19, count 0 2006.190.08:25:39.29#ibcon#flushed, iclass 19, count 0 2006.190.08:25:39.29#ibcon#about to write, iclass 19, count 0 2006.190.08:25:39.29#ibcon#wrote, iclass 19, count 0 2006.190.08:25:39.29#ibcon#about to read 3, iclass 19, count 0 2006.190.08:25:39.31#ibcon#read 3, iclass 19, count 0 2006.190.08:25:39.31#ibcon#about to read 4, iclass 19, count 0 2006.190.08:25:39.31#ibcon#read 4, iclass 19, count 0 2006.190.08:25:39.31#ibcon#about to read 5, iclass 19, count 0 2006.190.08:25:39.31#ibcon#read 5, iclass 19, count 0 2006.190.08:25:39.31#ibcon#about to read 6, iclass 19, count 0 2006.190.08:25:39.31#ibcon#read 6, iclass 19, count 0 2006.190.08:25:39.31#ibcon#end of sib2, iclass 19, count 0 2006.190.08:25:39.31#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:25:39.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:25:39.31#ibcon#[25=USB\r\n] 2006.190.08:25:39.31#ibcon#*before write, iclass 19, count 0 2006.190.08:25:39.31#ibcon#enter sib2, iclass 19, count 0 2006.190.08:25:39.31#ibcon#flushed, iclass 19, count 0 2006.190.08:25:39.31#ibcon#about to write, iclass 19, count 0 2006.190.08:25:39.31#ibcon#wrote, iclass 19, count 0 2006.190.08:25:39.31#ibcon#about to read 3, iclass 19, count 0 2006.190.08:25:39.34#ibcon#read 3, iclass 19, count 0 2006.190.08:25:39.34#ibcon#about to read 4, iclass 19, count 0 2006.190.08:25:39.34#ibcon#read 4, iclass 19, count 0 2006.190.08:25:39.34#ibcon#about to read 5, iclass 19, count 0 2006.190.08:25:39.34#ibcon#read 5, iclass 19, count 0 2006.190.08:25:39.34#ibcon#about to read 6, iclass 19, count 0 2006.190.08:25:39.34#ibcon#read 6, iclass 19, count 0 2006.190.08:25:39.34#ibcon#end of sib2, iclass 19, count 0 2006.190.08:25:39.34#ibcon#*after write, iclass 19, count 0 2006.190.08:25:39.34#ibcon#*before return 0, iclass 19, count 0 2006.190.08:25:39.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:39.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:39.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:25:39.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:25:39.34$vc4f8/valo=5,652.99 2006.190.08:25:39.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.08:25:39.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.08:25:39.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:39.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:39.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:39.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:39.34#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:25:39.34#ibcon#first serial, iclass 21, count 0 2006.190.08:25:39.34#ibcon#enter sib2, iclass 21, count 0 2006.190.08:25:39.34#ibcon#flushed, iclass 21, count 0 2006.190.08:25:39.34#ibcon#about to write, iclass 21, count 0 2006.190.08:25:39.34#ibcon#wrote, iclass 21, count 0 2006.190.08:25:39.34#ibcon#about to read 3, iclass 21, count 0 2006.190.08:25:39.36#ibcon#read 3, iclass 21, count 0 2006.190.08:25:39.36#ibcon#about to read 4, iclass 21, count 0 2006.190.08:25:39.36#ibcon#read 4, iclass 21, count 0 2006.190.08:25:39.36#ibcon#about to read 5, iclass 21, count 0 2006.190.08:25:39.36#ibcon#read 5, iclass 21, count 0 2006.190.08:25:39.36#ibcon#about to read 6, iclass 21, count 0 2006.190.08:25:39.36#ibcon#read 6, iclass 21, count 0 2006.190.08:25:39.36#ibcon#end of sib2, iclass 21, count 0 2006.190.08:25:39.36#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:25:39.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:25:39.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.190.08:25:39.36#ibcon#*before write, iclass 21, count 0 2006.190.08:25:39.36#ibcon#enter sib2, iclass 21, count 0 2006.190.08:25:39.36#ibcon#flushed, iclass 21, count 0 2006.190.08:25:39.36#ibcon#about to write, iclass 21, count 0 2006.190.08:25:39.36#ibcon#wrote, iclass 21, count 0 2006.190.08:25:39.36#ibcon#about to read 3, iclass 21, count 0 2006.190.08:25:39.40#ibcon#read 3, iclass 21, count 0 2006.190.08:25:39.40#ibcon#about to read 4, iclass 21, count 0 2006.190.08:25:39.40#ibcon#read 4, iclass 21, count 0 2006.190.08:25:39.40#ibcon#about to read 5, iclass 21, count 0 2006.190.08:25:39.40#ibcon#read 5, iclass 21, count 0 2006.190.08:25:39.40#ibcon#about to read 6, iclass 21, count 0 2006.190.08:25:39.40#ibcon#read 6, iclass 21, count 0 2006.190.08:25:39.40#ibcon#end of sib2, iclass 21, count 0 2006.190.08:25:39.40#ibcon#*after write, iclass 21, count 0 2006.190.08:25:39.40#ibcon#*before return 0, iclass 21, count 0 2006.190.08:25:39.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:39.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:39.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:25:39.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:25:39.40$vc4f8/va=5,7 2006.190.08:25:39.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.08:25:39.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.08:25:39.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:39.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:39.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:39.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:39.46#ibcon#enter wrdev, iclass 23, count 2 2006.190.08:25:39.46#ibcon#first serial, iclass 23, count 2 2006.190.08:25:39.46#ibcon#enter sib2, iclass 23, count 2 2006.190.08:25:39.46#ibcon#flushed, iclass 23, count 2 2006.190.08:25:39.46#ibcon#about to write, iclass 23, count 2 2006.190.08:25:39.46#ibcon#wrote, iclass 23, count 2 2006.190.08:25:39.46#ibcon#about to read 3, iclass 23, count 2 2006.190.08:25:39.48#ibcon#read 3, iclass 23, count 2 2006.190.08:25:39.48#ibcon#about to read 4, iclass 23, count 2 2006.190.08:25:39.48#ibcon#read 4, iclass 23, count 2 2006.190.08:25:39.48#ibcon#about to read 5, iclass 23, count 2 2006.190.08:25:39.48#ibcon#read 5, iclass 23, count 2 2006.190.08:25:39.48#ibcon#about to read 6, iclass 23, count 2 2006.190.08:25:39.48#ibcon#read 6, iclass 23, count 2 2006.190.08:25:39.48#ibcon#end of sib2, iclass 23, count 2 2006.190.08:25:39.48#ibcon#*mode == 0, iclass 23, count 2 2006.190.08:25:39.48#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.08:25:39.48#ibcon#[25=AT05-07\r\n] 2006.190.08:25:39.48#ibcon#*before write, iclass 23, count 2 2006.190.08:25:39.48#ibcon#enter sib2, iclass 23, count 2 2006.190.08:25:39.48#ibcon#flushed, iclass 23, count 2 2006.190.08:25:39.48#ibcon#about to write, iclass 23, count 2 2006.190.08:25:39.48#ibcon#wrote, iclass 23, count 2 2006.190.08:25:39.48#ibcon#about to read 3, iclass 23, count 2 2006.190.08:25:39.51#ibcon#read 3, iclass 23, count 2 2006.190.08:25:39.51#ibcon#about to read 4, iclass 23, count 2 2006.190.08:25:39.51#ibcon#read 4, iclass 23, count 2 2006.190.08:25:39.51#ibcon#about to read 5, iclass 23, count 2 2006.190.08:25:39.51#ibcon#read 5, iclass 23, count 2 2006.190.08:25:39.51#ibcon#about to read 6, iclass 23, count 2 2006.190.08:25:39.51#ibcon#read 6, iclass 23, count 2 2006.190.08:25:39.51#ibcon#end of sib2, iclass 23, count 2 2006.190.08:25:39.51#ibcon#*after write, iclass 23, count 2 2006.190.08:25:39.51#ibcon#*before return 0, iclass 23, count 2 2006.190.08:25:39.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:39.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:39.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.08:25:39.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:39.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:39.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:39.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:39.63#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:25:39.63#ibcon#first serial, iclass 23, count 0 2006.190.08:25:39.63#ibcon#enter sib2, iclass 23, count 0 2006.190.08:25:39.63#ibcon#flushed, iclass 23, count 0 2006.190.08:25:39.63#ibcon#about to write, iclass 23, count 0 2006.190.08:25:39.63#ibcon#wrote, iclass 23, count 0 2006.190.08:25:39.63#ibcon#about to read 3, iclass 23, count 0 2006.190.08:25:39.65#ibcon#read 3, iclass 23, count 0 2006.190.08:25:39.65#ibcon#about to read 4, iclass 23, count 0 2006.190.08:25:39.65#ibcon#read 4, iclass 23, count 0 2006.190.08:25:39.65#ibcon#about to read 5, iclass 23, count 0 2006.190.08:25:39.65#ibcon#read 5, iclass 23, count 0 2006.190.08:25:39.65#ibcon#about to read 6, iclass 23, count 0 2006.190.08:25:39.65#ibcon#read 6, iclass 23, count 0 2006.190.08:25:39.65#ibcon#end of sib2, iclass 23, count 0 2006.190.08:25:39.65#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:25:39.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:25:39.65#ibcon#[25=USB\r\n] 2006.190.08:25:39.65#ibcon#*before write, iclass 23, count 0 2006.190.08:25:39.65#ibcon#enter sib2, iclass 23, count 0 2006.190.08:25:39.65#ibcon#flushed, iclass 23, count 0 2006.190.08:25:39.65#ibcon#about to write, iclass 23, count 0 2006.190.08:25:39.65#ibcon#wrote, iclass 23, count 0 2006.190.08:25:39.65#ibcon#about to read 3, iclass 23, count 0 2006.190.08:25:39.68#ibcon#read 3, iclass 23, count 0 2006.190.08:25:39.68#ibcon#about to read 4, iclass 23, count 0 2006.190.08:25:39.68#ibcon#read 4, iclass 23, count 0 2006.190.08:25:39.68#ibcon#about to read 5, iclass 23, count 0 2006.190.08:25:39.68#ibcon#read 5, iclass 23, count 0 2006.190.08:25:39.68#ibcon#about to read 6, iclass 23, count 0 2006.190.08:25:39.68#ibcon#read 6, iclass 23, count 0 2006.190.08:25:39.68#ibcon#end of sib2, iclass 23, count 0 2006.190.08:25:39.68#ibcon#*after write, iclass 23, count 0 2006.190.08:25:39.68#ibcon#*before return 0, iclass 23, count 0 2006.190.08:25:39.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:39.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:39.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:25:39.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:25:39.68$vc4f8/valo=6,772.99 2006.190.08:25:39.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.08:25:39.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.08:25:39.68#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:39.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:39.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:39.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:39.68#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:25:39.68#ibcon#first serial, iclass 25, count 0 2006.190.08:25:39.68#ibcon#enter sib2, iclass 25, count 0 2006.190.08:25:39.68#ibcon#flushed, iclass 25, count 0 2006.190.08:25:39.68#ibcon#about to write, iclass 25, count 0 2006.190.08:25:39.68#ibcon#wrote, iclass 25, count 0 2006.190.08:25:39.68#ibcon#about to read 3, iclass 25, count 0 2006.190.08:25:39.70#ibcon#read 3, iclass 25, count 0 2006.190.08:25:39.70#ibcon#about to read 4, iclass 25, count 0 2006.190.08:25:39.70#ibcon#read 4, iclass 25, count 0 2006.190.08:25:39.70#ibcon#about to read 5, iclass 25, count 0 2006.190.08:25:39.70#ibcon#read 5, iclass 25, count 0 2006.190.08:25:39.70#ibcon#about to read 6, iclass 25, count 0 2006.190.08:25:39.70#ibcon#read 6, iclass 25, count 0 2006.190.08:25:39.70#ibcon#end of sib2, iclass 25, count 0 2006.190.08:25:39.70#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:25:39.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:25:39.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.190.08:25:39.70#ibcon#*before write, iclass 25, count 0 2006.190.08:25:39.70#ibcon#enter sib2, iclass 25, count 0 2006.190.08:25:39.70#ibcon#flushed, iclass 25, count 0 2006.190.08:25:39.70#ibcon#about to write, iclass 25, count 0 2006.190.08:25:39.70#ibcon#wrote, iclass 25, count 0 2006.190.08:25:39.70#ibcon#about to read 3, iclass 25, count 0 2006.190.08:25:39.74#ibcon#read 3, iclass 25, count 0 2006.190.08:25:39.74#ibcon#about to read 4, iclass 25, count 0 2006.190.08:25:39.74#ibcon#read 4, iclass 25, count 0 2006.190.08:25:39.74#ibcon#about to read 5, iclass 25, count 0 2006.190.08:25:39.74#ibcon#read 5, iclass 25, count 0 2006.190.08:25:39.74#ibcon#about to read 6, iclass 25, count 0 2006.190.08:25:39.74#ibcon#read 6, iclass 25, count 0 2006.190.08:25:39.74#ibcon#end of sib2, iclass 25, count 0 2006.190.08:25:39.74#ibcon#*after write, iclass 25, count 0 2006.190.08:25:39.74#ibcon#*before return 0, iclass 25, count 0 2006.190.08:25:39.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:39.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:39.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:25:39.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:25:39.74$vc4f8/va=6,6 2006.190.08:25:39.74#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.190.08:25:39.74#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.190.08:25:39.74#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:39.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:25:39.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:25:39.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:25:39.80#ibcon#enter wrdev, iclass 27, count 2 2006.190.08:25:39.80#ibcon#first serial, iclass 27, count 2 2006.190.08:25:39.80#ibcon#enter sib2, iclass 27, count 2 2006.190.08:25:39.80#ibcon#flushed, iclass 27, count 2 2006.190.08:25:39.80#ibcon#about to write, iclass 27, count 2 2006.190.08:25:39.80#ibcon#wrote, iclass 27, count 2 2006.190.08:25:39.80#ibcon#about to read 3, iclass 27, count 2 2006.190.08:25:39.82#ibcon#read 3, iclass 27, count 2 2006.190.08:25:39.82#ibcon#about to read 4, iclass 27, count 2 2006.190.08:25:39.82#ibcon#read 4, iclass 27, count 2 2006.190.08:25:39.82#ibcon#about to read 5, iclass 27, count 2 2006.190.08:25:39.82#ibcon#read 5, iclass 27, count 2 2006.190.08:25:39.82#ibcon#about to read 6, iclass 27, count 2 2006.190.08:25:39.82#ibcon#read 6, iclass 27, count 2 2006.190.08:25:39.82#ibcon#end of sib2, iclass 27, count 2 2006.190.08:25:39.82#ibcon#*mode == 0, iclass 27, count 2 2006.190.08:25:39.82#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.190.08:25:39.82#ibcon#[25=AT06-06\r\n] 2006.190.08:25:39.82#ibcon#*before write, iclass 27, count 2 2006.190.08:25:39.82#ibcon#enter sib2, iclass 27, count 2 2006.190.08:25:39.82#ibcon#flushed, iclass 27, count 2 2006.190.08:25:39.82#ibcon#about to write, iclass 27, count 2 2006.190.08:25:39.82#ibcon#wrote, iclass 27, count 2 2006.190.08:25:39.82#ibcon#about to read 3, iclass 27, count 2 2006.190.08:25:39.85#ibcon#read 3, iclass 27, count 2 2006.190.08:25:39.85#ibcon#about to read 4, iclass 27, count 2 2006.190.08:25:39.85#ibcon#read 4, iclass 27, count 2 2006.190.08:25:39.85#ibcon#about to read 5, iclass 27, count 2 2006.190.08:25:39.85#ibcon#read 5, iclass 27, count 2 2006.190.08:25:39.85#ibcon#about to read 6, iclass 27, count 2 2006.190.08:25:39.85#ibcon#read 6, iclass 27, count 2 2006.190.08:25:39.85#ibcon#end of sib2, iclass 27, count 2 2006.190.08:25:39.85#ibcon#*after write, iclass 27, count 2 2006.190.08:25:39.85#ibcon#*before return 0, iclass 27, count 2 2006.190.08:25:39.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:25:39.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.190.08:25:39.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.190.08:25:39.85#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:39.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:25:39.97#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:25:39.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:25:39.97#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:25:39.97#ibcon#first serial, iclass 27, count 0 2006.190.08:25:39.97#ibcon#enter sib2, iclass 27, count 0 2006.190.08:25:39.97#ibcon#flushed, iclass 27, count 0 2006.190.08:25:39.97#ibcon#about to write, iclass 27, count 0 2006.190.08:25:39.97#ibcon#wrote, iclass 27, count 0 2006.190.08:25:39.97#ibcon#about to read 3, iclass 27, count 0 2006.190.08:25:39.99#ibcon#read 3, iclass 27, count 0 2006.190.08:25:39.99#ibcon#about to read 4, iclass 27, count 0 2006.190.08:25:39.99#ibcon#read 4, iclass 27, count 0 2006.190.08:25:39.99#ibcon#about to read 5, iclass 27, count 0 2006.190.08:25:39.99#ibcon#read 5, iclass 27, count 0 2006.190.08:25:39.99#ibcon#about to read 6, iclass 27, count 0 2006.190.08:25:39.99#ibcon#read 6, iclass 27, count 0 2006.190.08:25:39.99#ibcon#end of sib2, iclass 27, count 0 2006.190.08:25:39.99#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:25:39.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:25:39.99#ibcon#[25=USB\r\n] 2006.190.08:25:39.99#ibcon#*before write, iclass 27, count 0 2006.190.08:25:39.99#ibcon#enter sib2, iclass 27, count 0 2006.190.08:25:39.99#ibcon#flushed, iclass 27, count 0 2006.190.08:25:39.99#ibcon#about to write, iclass 27, count 0 2006.190.08:25:39.99#ibcon#wrote, iclass 27, count 0 2006.190.08:25:39.99#ibcon#about to read 3, iclass 27, count 0 2006.190.08:25:40.02#ibcon#read 3, iclass 27, count 0 2006.190.08:25:40.02#ibcon#about to read 4, iclass 27, count 0 2006.190.08:25:40.02#ibcon#read 4, iclass 27, count 0 2006.190.08:25:40.02#ibcon#about to read 5, iclass 27, count 0 2006.190.08:25:40.02#ibcon#read 5, iclass 27, count 0 2006.190.08:25:40.02#ibcon#about to read 6, iclass 27, count 0 2006.190.08:25:40.02#ibcon#read 6, iclass 27, count 0 2006.190.08:25:40.02#ibcon#end of sib2, iclass 27, count 0 2006.190.08:25:40.02#ibcon#*after write, iclass 27, count 0 2006.190.08:25:40.02#ibcon#*before return 0, iclass 27, count 0 2006.190.08:25:40.02#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:25:40.02#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.190.08:25:40.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:25:40.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:25:40.02$vc4f8/valo=7,832.99 2006.190.08:25:40.02#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.190.08:25:40.02#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.190.08:25:40.02#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:40.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:25:40.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:25:40.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:25:40.02#ibcon#enter wrdev, iclass 29, count 0 2006.190.08:25:40.02#ibcon#first serial, iclass 29, count 0 2006.190.08:25:40.02#ibcon#enter sib2, iclass 29, count 0 2006.190.08:25:40.02#ibcon#flushed, iclass 29, count 0 2006.190.08:25:40.02#ibcon#about to write, iclass 29, count 0 2006.190.08:25:40.02#ibcon#wrote, iclass 29, count 0 2006.190.08:25:40.02#ibcon#about to read 3, iclass 29, count 0 2006.190.08:25:40.04#ibcon#read 3, iclass 29, count 0 2006.190.08:25:40.04#ibcon#about to read 4, iclass 29, count 0 2006.190.08:25:40.04#ibcon#read 4, iclass 29, count 0 2006.190.08:25:40.04#ibcon#about to read 5, iclass 29, count 0 2006.190.08:25:40.04#ibcon#read 5, iclass 29, count 0 2006.190.08:25:40.04#ibcon#about to read 6, iclass 29, count 0 2006.190.08:25:40.04#ibcon#read 6, iclass 29, count 0 2006.190.08:25:40.04#ibcon#end of sib2, iclass 29, count 0 2006.190.08:25:40.04#ibcon#*mode == 0, iclass 29, count 0 2006.190.08:25:40.04#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.190.08:25:40.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.190.08:25:40.04#ibcon#*before write, iclass 29, count 0 2006.190.08:25:40.04#ibcon#enter sib2, iclass 29, count 0 2006.190.08:25:40.04#ibcon#flushed, iclass 29, count 0 2006.190.08:25:40.04#ibcon#about to write, iclass 29, count 0 2006.190.08:25:40.04#ibcon#wrote, iclass 29, count 0 2006.190.08:25:40.04#ibcon#about to read 3, iclass 29, count 0 2006.190.08:25:40.08#ibcon#read 3, iclass 29, count 0 2006.190.08:25:40.08#ibcon#about to read 4, iclass 29, count 0 2006.190.08:25:40.08#ibcon#read 4, iclass 29, count 0 2006.190.08:25:40.08#ibcon#about to read 5, iclass 29, count 0 2006.190.08:25:40.08#ibcon#read 5, iclass 29, count 0 2006.190.08:25:40.08#ibcon#about to read 6, iclass 29, count 0 2006.190.08:25:40.08#ibcon#read 6, iclass 29, count 0 2006.190.08:25:40.08#ibcon#end of sib2, iclass 29, count 0 2006.190.08:25:40.08#ibcon#*after write, iclass 29, count 0 2006.190.08:25:40.08#ibcon#*before return 0, iclass 29, count 0 2006.190.08:25:40.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:25:40.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.190.08:25:40.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.190.08:25:40.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.190.08:25:40.08$vc4f8/va=7,6 2006.190.08:25:40.08#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.190.08:25:40.08#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.190.08:25:40.08#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:40.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:25:40.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:25:40.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:25:40.14#ibcon#enter wrdev, iclass 31, count 2 2006.190.08:25:40.14#ibcon#first serial, iclass 31, count 2 2006.190.08:25:40.14#ibcon#enter sib2, iclass 31, count 2 2006.190.08:25:40.14#ibcon#flushed, iclass 31, count 2 2006.190.08:25:40.14#ibcon#about to write, iclass 31, count 2 2006.190.08:25:40.14#ibcon#wrote, iclass 31, count 2 2006.190.08:25:40.14#ibcon#about to read 3, iclass 31, count 2 2006.190.08:25:40.16#ibcon#read 3, iclass 31, count 2 2006.190.08:25:40.16#ibcon#about to read 4, iclass 31, count 2 2006.190.08:25:40.16#ibcon#read 4, iclass 31, count 2 2006.190.08:25:40.16#ibcon#about to read 5, iclass 31, count 2 2006.190.08:25:40.16#ibcon#read 5, iclass 31, count 2 2006.190.08:25:40.16#ibcon#about to read 6, iclass 31, count 2 2006.190.08:25:40.16#ibcon#read 6, iclass 31, count 2 2006.190.08:25:40.16#ibcon#end of sib2, iclass 31, count 2 2006.190.08:25:40.16#ibcon#*mode == 0, iclass 31, count 2 2006.190.08:25:40.16#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.190.08:25:40.16#ibcon#[25=AT07-06\r\n] 2006.190.08:25:40.16#ibcon#*before write, iclass 31, count 2 2006.190.08:25:40.16#ibcon#enter sib2, iclass 31, count 2 2006.190.08:25:40.16#ibcon#flushed, iclass 31, count 2 2006.190.08:25:40.16#ibcon#about to write, iclass 31, count 2 2006.190.08:25:40.16#ibcon#wrote, iclass 31, count 2 2006.190.08:25:40.16#ibcon#about to read 3, iclass 31, count 2 2006.190.08:25:40.19#ibcon#read 3, iclass 31, count 2 2006.190.08:25:40.19#ibcon#about to read 4, iclass 31, count 2 2006.190.08:25:40.19#ibcon#read 4, iclass 31, count 2 2006.190.08:25:40.19#ibcon#about to read 5, iclass 31, count 2 2006.190.08:25:40.19#ibcon#read 5, iclass 31, count 2 2006.190.08:25:40.19#ibcon#about to read 6, iclass 31, count 2 2006.190.08:25:40.19#ibcon#read 6, iclass 31, count 2 2006.190.08:25:40.19#ibcon#end of sib2, iclass 31, count 2 2006.190.08:25:40.19#ibcon#*after write, iclass 31, count 2 2006.190.08:25:40.19#ibcon#*before return 0, iclass 31, count 2 2006.190.08:25:40.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:25:40.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.190.08:25:40.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.190.08:25:40.19#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:40.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:25:40.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:25:40.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:25:40.31#ibcon#enter wrdev, iclass 31, count 0 2006.190.08:25:40.31#ibcon#first serial, iclass 31, count 0 2006.190.08:25:40.31#ibcon#enter sib2, iclass 31, count 0 2006.190.08:25:40.31#ibcon#flushed, iclass 31, count 0 2006.190.08:25:40.31#ibcon#about to write, iclass 31, count 0 2006.190.08:25:40.31#ibcon#wrote, iclass 31, count 0 2006.190.08:25:40.31#ibcon#about to read 3, iclass 31, count 0 2006.190.08:25:40.33#ibcon#read 3, iclass 31, count 0 2006.190.08:25:40.33#ibcon#about to read 4, iclass 31, count 0 2006.190.08:25:40.33#ibcon#read 4, iclass 31, count 0 2006.190.08:25:40.33#ibcon#about to read 5, iclass 31, count 0 2006.190.08:25:40.33#ibcon#read 5, iclass 31, count 0 2006.190.08:25:40.33#ibcon#about to read 6, iclass 31, count 0 2006.190.08:25:40.33#ibcon#read 6, iclass 31, count 0 2006.190.08:25:40.33#ibcon#end of sib2, iclass 31, count 0 2006.190.08:25:40.33#ibcon#*mode == 0, iclass 31, count 0 2006.190.08:25:40.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.190.08:25:40.33#ibcon#[25=USB\r\n] 2006.190.08:25:40.33#ibcon#*before write, iclass 31, count 0 2006.190.08:25:40.33#ibcon#enter sib2, iclass 31, count 0 2006.190.08:25:40.33#ibcon#flushed, iclass 31, count 0 2006.190.08:25:40.33#ibcon#about to write, iclass 31, count 0 2006.190.08:25:40.33#ibcon#wrote, iclass 31, count 0 2006.190.08:25:40.33#ibcon#about to read 3, iclass 31, count 0 2006.190.08:25:40.36#ibcon#read 3, iclass 31, count 0 2006.190.08:25:40.36#ibcon#about to read 4, iclass 31, count 0 2006.190.08:25:40.36#ibcon#read 4, iclass 31, count 0 2006.190.08:25:40.36#ibcon#about to read 5, iclass 31, count 0 2006.190.08:25:40.36#ibcon#read 5, iclass 31, count 0 2006.190.08:25:40.36#ibcon#about to read 6, iclass 31, count 0 2006.190.08:25:40.36#ibcon#read 6, iclass 31, count 0 2006.190.08:25:40.36#ibcon#end of sib2, iclass 31, count 0 2006.190.08:25:40.36#ibcon#*after write, iclass 31, count 0 2006.190.08:25:40.36#ibcon#*before return 0, iclass 31, count 0 2006.190.08:25:40.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:25:40.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.190.08:25:40.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.190.08:25:40.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.190.08:25:40.36$vc4f8/valo=8,852.99 2006.190.08:25:40.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.190.08:25:40.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.190.08:25:40.36#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:40.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:25:40.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:25:40.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:25:40.36#ibcon#enter wrdev, iclass 33, count 0 2006.190.08:25:40.36#ibcon#first serial, iclass 33, count 0 2006.190.08:25:40.36#ibcon#enter sib2, iclass 33, count 0 2006.190.08:25:40.36#ibcon#flushed, iclass 33, count 0 2006.190.08:25:40.36#ibcon#about to write, iclass 33, count 0 2006.190.08:25:40.36#ibcon#wrote, iclass 33, count 0 2006.190.08:25:40.36#ibcon#about to read 3, iclass 33, count 0 2006.190.08:25:40.38#ibcon#read 3, iclass 33, count 0 2006.190.08:25:40.38#ibcon#about to read 4, iclass 33, count 0 2006.190.08:25:40.38#ibcon#read 4, iclass 33, count 0 2006.190.08:25:40.38#ibcon#about to read 5, iclass 33, count 0 2006.190.08:25:40.38#ibcon#read 5, iclass 33, count 0 2006.190.08:25:40.38#ibcon#about to read 6, iclass 33, count 0 2006.190.08:25:40.38#ibcon#read 6, iclass 33, count 0 2006.190.08:25:40.38#ibcon#end of sib2, iclass 33, count 0 2006.190.08:25:40.38#ibcon#*mode == 0, iclass 33, count 0 2006.190.08:25:40.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.190.08:25:40.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.190.08:25:40.38#ibcon#*before write, iclass 33, count 0 2006.190.08:25:40.38#ibcon#enter sib2, iclass 33, count 0 2006.190.08:25:40.38#ibcon#flushed, iclass 33, count 0 2006.190.08:25:40.38#ibcon#about to write, iclass 33, count 0 2006.190.08:25:40.38#ibcon#wrote, iclass 33, count 0 2006.190.08:25:40.38#ibcon#about to read 3, iclass 33, count 0 2006.190.08:25:40.42#ibcon#read 3, iclass 33, count 0 2006.190.08:25:40.42#ibcon#about to read 4, iclass 33, count 0 2006.190.08:25:40.42#ibcon#read 4, iclass 33, count 0 2006.190.08:25:40.42#ibcon#about to read 5, iclass 33, count 0 2006.190.08:25:40.42#ibcon#read 5, iclass 33, count 0 2006.190.08:25:40.42#ibcon#about to read 6, iclass 33, count 0 2006.190.08:25:40.42#ibcon#read 6, iclass 33, count 0 2006.190.08:25:40.42#ibcon#end of sib2, iclass 33, count 0 2006.190.08:25:40.42#ibcon#*after write, iclass 33, count 0 2006.190.08:25:40.42#ibcon#*before return 0, iclass 33, count 0 2006.190.08:25:40.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:25:40.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.190.08:25:40.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.190.08:25:40.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.190.08:25:40.42$vc4f8/va=8,6 2006.190.08:25:40.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.190.08:25:40.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.190.08:25:40.42#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:40.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:25:40.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:25:40.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:25:40.48#ibcon#enter wrdev, iclass 35, count 2 2006.190.08:25:40.48#ibcon#first serial, iclass 35, count 2 2006.190.08:25:40.48#ibcon#enter sib2, iclass 35, count 2 2006.190.08:25:40.48#ibcon#flushed, iclass 35, count 2 2006.190.08:25:40.48#ibcon#about to write, iclass 35, count 2 2006.190.08:25:40.48#ibcon#wrote, iclass 35, count 2 2006.190.08:25:40.48#ibcon#about to read 3, iclass 35, count 2 2006.190.08:25:40.50#ibcon#read 3, iclass 35, count 2 2006.190.08:25:40.50#ibcon#about to read 4, iclass 35, count 2 2006.190.08:25:40.50#ibcon#read 4, iclass 35, count 2 2006.190.08:25:40.50#ibcon#about to read 5, iclass 35, count 2 2006.190.08:25:40.50#ibcon#read 5, iclass 35, count 2 2006.190.08:25:40.50#ibcon#about to read 6, iclass 35, count 2 2006.190.08:25:40.50#ibcon#read 6, iclass 35, count 2 2006.190.08:25:40.50#ibcon#end of sib2, iclass 35, count 2 2006.190.08:25:40.50#ibcon#*mode == 0, iclass 35, count 2 2006.190.08:25:40.50#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.190.08:25:40.50#ibcon#[25=AT08-06\r\n] 2006.190.08:25:40.50#ibcon#*before write, iclass 35, count 2 2006.190.08:25:40.50#ibcon#enter sib2, iclass 35, count 2 2006.190.08:25:40.50#ibcon#flushed, iclass 35, count 2 2006.190.08:25:40.50#ibcon#about to write, iclass 35, count 2 2006.190.08:25:40.50#ibcon#wrote, iclass 35, count 2 2006.190.08:25:40.50#ibcon#about to read 3, iclass 35, count 2 2006.190.08:25:40.53#ibcon#read 3, iclass 35, count 2 2006.190.08:25:40.53#ibcon#about to read 4, iclass 35, count 2 2006.190.08:25:40.53#ibcon#read 4, iclass 35, count 2 2006.190.08:25:40.53#ibcon#about to read 5, iclass 35, count 2 2006.190.08:25:40.53#ibcon#read 5, iclass 35, count 2 2006.190.08:25:40.53#ibcon#about to read 6, iclass 35, count 2 2006.190.08:25:40.53#ibcon#read 6, iclass 35, count 2 2006.190.08:25:40.53#ibcon#end of sib2, iclass 35, count 2 2006.190.08:25:40.53#ibcon#*after write, iclass 35, count 2 2006.190.08:25:40.53#ibcon#*before return 0, iclass 35, count 2 2006.190.08:25:40.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:25:40.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.190.08:25:40.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.190.08:25:40.53#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:40.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:25:40.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:25:40.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:25:40.65#ibcon#enter wrdev, iclass 35, count 0 2006.190.08:25:40.65#ibcon#first serial, iclass 35, count 0 2006.190.08:25:40.65#ibcon#enter sib2, iclass 35, count 0 2006.190.08:25:40.65#ibcon#flushed, iclass 35, count 0 2006.190.08:25:40.65#ibcon#about to write, iclass 35, count 0 2006.190.08:25:40.65#ibcon#wrote, iclass 35, count 0 2006.190.08:25:40.65#ibcon#about to read 3, iclass 35, count 0 2006.190.08:25:40.67#ibcon#read 3, iclass 35, count 0 2006.190.08:25:40.67#ibcon#about to read 4, iclass 35, count 0 2006.190.08:25:40.67#ibcon#read 4, iclass 35, count 0 2006.190.08:25:40.67#ibcon#about to read 5, iclass 35, count 0 2006.190.08:25:40.67#ibcon#read 5, iclass 35, count 0 2006.190.08:25:40.67#ibcon#about to read 6, iclass 35, count 0 2006.190.08:25:40.67#ibcon#read 6, iclass 35, count 0 2006.190.08:25:40.67#ibcon#end of sib2, iclass 35, count 0 2006.190.08:25:40.67#ibcon#*mode == 0, iclass 35, count 0 2006.190.08:25:40.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.190.08:25:40.67#ibcon#[25=USB\r\n] 2006.190.08:25:40.67#ibcon#*before write, iclass 35, count 0 2006.190.08:25:40.67#ibcon#enter sib2, iclass 35, count 0 2006.190.08:25:40.67#ibcon#flushed, iclass 35, count 0 2006.190.08:25:40.67#ibcon#about to write, iclass 35, count 0 2006.190.08:25:40.67#ibcon#wrote, iclass 35, count 0 2006.190.08:25:40.67#ibcon#about to read 3, iclass 35, count 0 2006.190.08:25:40.70#ibcon#read 3, iclass 35, count 0 2006.190.08:25:40.70#ibcon#about to read 4, iclass 35, count 0 2006.190.08:25:40.70#ibcon#read 4, iclass 35, count 0 2006.190.08:25:40.70#ibcon#about to read 5, iclass 35, count 0 2006.190.08:25:40.70#ibcon#read 5, iclass 35, count 0 2006.190.08:25:40.70#ibcon#about to read 6, iclass 35, count 0 2006.190.08:25:40.70#ibcon#read 6, iclass 35, count 0 2006.190.08:25:40.70#ibcon#end of sib2, iclass 35, count 0 2006.190.08:25:40.70#ibcon#*after write, iclass 35, count 0 2006.190.08:25:40.70#ibcon#*before return 0, iclass 35, count 0 2006.190.08:25:40.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:25:40.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.190.08:25:40.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.190.08:25:40.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.190.08:25:40.70$vc4f8/vblo=1,632.99 2006.190.08:25:40.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.190.08:25:40.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.190.08:25:40.70#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:40.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:25:40.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:25:40.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:25:40.70#ibcon#enter wrdev, iclass 37, count 0 2006.190.08:25:40.70#ibcon#first serial, iclass 37, count 0 2006.190.08:25:40.70#ibcon#enter sib2, iclass 37, count 0 2006.190.08:25:40.70#ibcon#flushed, iclass 37, count 0 2006.190.08:25:40.70#ibcon#about to write, iclass 37, count 0 2006.190.08:25:40.70#ibcon#wrote, iclass 37, count 0 2006.190.08:25:40.70#ibcon#about to read 3, iclass 37, count 0 2006.190.08:25:40.72#ibcon#read 3, iclass 37, count 0 2006.190.08:25:40.72#ibcon#about to read 4, iclass 37, count 0 2006.190.08:25:40.72#ibcon#read 4, iclass 37, count 0 2006.190.08:25:40.72#ibcon#about to read 5, iclass 37, count 0 2006.190.08:25:40.72#ibcon#read 5, iclass 37, count 0 2006.190.08:25:40.72#ibcon#about to read 6, iclass 37, count 0 2006.190.08:25:40.72#ibcon#read 6, iclass 37, count 0 2006.190.08:25:40.72#ibcon#end of sib2, iclass 37, count 0 2006.190.08:25:40.72#ibcon#*mode == 0, iclass 37, count 0 2006.190.08:25:40.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.190.08:25:40.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.190.08:25:40.72#ibcon#*before write, iclass 37, count 0 2006.190.08:25:40.72#ibcon#enter sib2, iclass 37, count 0 2006.190.08:25:40.72#ibcon#flushed, iclass 37, count 0 2006.190.08:25:40.72#ibcon#about to write, iclass 37, count 0 2006.190.08:25:40.72#ibcon#wrote, iclass 37, count 0 2006.190.08:25:40.72#ibcon#about to read 3, iclass 37, count 0 2006.190.08:25:40.76#ibcon#read 3, iclass 37, count 0 2006.190.08:25:40.76#ibcon#about to read 4, iclass 37, count 0 2006.190.08:25:40.76#ibcon#read 4, iclass 37, count 0 2006.190.08:25:40.76#ibcon#about to read 5, iclass 37, count 0 2006.190.08:25:40.76#ibcon#read 5, iclass 37, count 0 2006.190.08:25:40.76#ibcon#about to read 6, iclass 37, count 0 2006.190.08:25:40.76#ibcon#read 6, iclass 37, count 0 2006.190.08:25:40.76#ibcon#end of sib2, iclass 37, count 0 2006.190.08:25:40.76#ibcon#*after write, iclass 37, count 0 2006.190.08:25:40.76#ibcon#*before return 0, iclass 37, count 0 2006.190.08:25:40.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:25:40.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.190.08:25:40.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.190.08:25:40.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.190.08:25:40.76$vc4f8/vb=1,4 2006.190.08:25:40.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.190.08:25:40.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.190.08:25:40.76#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:40.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:25:40.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:25:40.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:25:40.76#ibcon#enter wrdev, iclass 39, count 2 2006.190.08:25:40.76#ibcon#first serial, iclass 39, count 2 2006.190.08:25:40.76#ibcon#enter sib2, iclass 39, count 2 2006.190.08:25:40.76#ibcon#flushed, iclass 39, count 2 2006.190.08:25:40.76#ibcon#about to write, iclass 39, count 2 2006.190.08:25:40.76#ibcon#wrote, iclass 39, count 2 2006.190.08:25:40.76#ibcon#about to read 3, iclass 39, count 2 2006.190.08:25:40.78#ibcon#read 3, iclass 39, count 2 2006.190.08:25:40.78#ibcon#about to read 4, iclass 39, count 2 2006.190.08:25:40.78#ibcon#read 4, iclass 39, count 2 2006.190.08:25:40.78#ibcon#about to read 5, iclass 39, count 2 2006.190.08:25:40.78#ibcon#read 5, iclass 39, count 2 2006.190.08:25:40.78#ibcon#about to read 6, iclass 39, count 2 2006.190.08:25:40.78#ibcon#read 6, iclass 39, count 2 2006.190.08:25:40.78#ibcon#end of sib2, iclass 39, count 2 2006.190.08:25:40.78#ibcon#*mode == 0, iclass 39, count 2 2006.190.08:25:40.78#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.190.08:25:40.78#ibcon#[27=AT01-04\r\n] 2006.190.08:25:40.78#ibcon#*before write, iclass 39, count 2 2006.190.08:25:40.78#ibcon#enter sib2, iclass 39, count 2 2006.190.08:25:40.78#ibcon#flushed, iclass 39, count 2 2006.190.08:25:40.78#ibcon#about to write, iclass 39, count 2 2006.190.08:25:40.78#ibcon#wrote, iclass 39, count 2 2006.190.08:25:40.78#ibcon#about to read 3, iclass 39, count 2 2006.190.08:25:40.81#ibcon#read 3, iclass 39, count 2 2006.190.08:25:40.81#ibcon#about to read 4, iclass 39, count 2 2006.190.08:25:40.81#ibcon#read 4, iclass 39, count 2 2006.190.08:25:40.81#ibcon#about to read 5, iclass 39, count 2 2006.190.08:25:40.81#ibcon#read 5, iclass 39, count 2 2006.190.08:25:40.81#ibcon#about to read 6, iclass 39, count 2 2006.190.08:25:40.81#ibcon#read 6, iclass 39, count 2 2006.190.08:25:40.81#ibcon#end of sib2, iclass 39, count 2 2006.190.08:25:40.81#ibcon#*after write, iclass 39, count 2 2006.190.08:25:40.81#ibcon#*before return 0, iclass 39, count 2 2006.190.08:25:40.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:25:40.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.190.08:25:40.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.190.08:25:40.81#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:40.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:25:40.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:25:40.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:25:40.93#ibcon#enter wrdev, iclass 39, count 0 2006.190.08:25:40.93#ibcon#first serial, iclass 39, count 0 2006.190.08:25:40.93#ibcon#enter sib2, iclass 39, count 0 2006.190.08:25:40.93#ibcon#flushed, iclass 39, count 0 2006.190.08:25:40.93#ibcon#about to write, iclass 39, count 0 2006.190.08:25:40.93#ibcon#wrote, iclass 39, count 0 2006.190.08:25:40.93#ibcon#about to read 3, iclass 39, count 0 2006.190.08:25:40.95#ibcon#read 3, iclass 39, count 0 2006.190.08:25:40.95#ibcon#about to read 4, iclass 39, count 0 2006.190.08:25:40.95#ibcon#read 4, iclass 39, count 0 2006.190.08:25:40.95#ibcon#about to read 5, iclass 39, count 0 2006.190.08:25:40.95#ibcon#read 5, iclass 39, count 0 2006.190.08:25:40.95#ibcon#about to read 6, iclass 39, count 0 2006.190.08:25:40.95#ibcon#read 6, iclass 39, count 0 2006.190.08:25:40.95#ibcon#end of sib2, iclass 39, count 0 2006.190.08:25:40.95#ibcon#*mode == 0, iclass 39, count 0 2006.190.08:25:40.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.190.08:25:40.95#ibcon#[27=USB\r\n] 2006.190.08:25:40.95#ibcon#*before write, iclass 39, count 0 2006.190.08:25:40.95#ibcon#enter sib2, iclass 39, count 0 2006.190.08:25:40.95#ibcon#flushed, iclass 39, count 0 2006.190.08:25:40.95#ibcon#about to write, iclass 39, count 0 2006.190.08:25:40.95#ibcon#wrote, iclass 39, count 0 2006.190.08:25:40.95#ibcon#about to read 3, iclass 39, count 0 2006.190.08:25:40.98#ibcon#read 3, iclass 39, count 0 2006.190.08:25:40.98#ibcon#about to read 4, iclass 39, count 0 2006.190.08:25:40.98#ibcon#read 4, iclass 39, count 0 2006.190.08:25:40.98#ibcon#about to read 5, iclass 39, count 0 2006.190.08:25:40.98#ibcon#read 5, iclass 39, count 0 2006.190.08:25:40.98#ibcon#about to read 6, iclass 39, count 0 2006.190.08:25:40.98#ibcon#read 6, iclass 39, count 0 2006.190.08:25:40.98#ibcon#end of sib2, iclass 39, count 0 2006.190.08:25:40.98#ibcon#*after write, iclass 39, count 0 2006.190.08:25:40.98#ibcon#*before return 0, iclass 39, count 0 2006.190.08:25:40.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:25:40.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.190.08:25:40.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.190.08:25:40.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.190.08:25:40.98$vc4f8/vblo=2,640.99 2006.190.08:25:40.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.190.08:25:40.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.190.08:25:40.98#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:40.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:40.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:40.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:40.98#ibcon#enter wrdev, iclass 3, count 0 2006.190.08:25:40.98#ibcon#first serial, iclass 3, count 0 2006.190.08:25:40.98#ibcon#enter sib2, iclass 3, count 0 2006.190.08:25:40.98#ibcon#flushed, iclass 3, count 0 2006.190.08:25:40.98#ibcon#about to write, iclass 3, count 0 2006.190.08:25:40.98#ibcon#wrote, iclass 3, count 0 2006.190.08:25:40.98#ibcon#about to read 3, iclass 3, count 0 2006.190.08:25:41.00#ibcon#read 3, iclass 3, count 0 2006.190.08:25:41.00#ibcon#about to read 4, iclass 3, count 0 2006.190.08:25:41.00#ibcon#read 4, iclass 3, count 0 2006.190.08:25:41.00#ibcon#about to read 5, iclass 3, count 0 2006.190.08:25:41.00#ibcon#read 5, iclass 3, count 0 2006.190.08:25:41.00#ibcon#about to read 6, iclass 3, count 0 2006.190.08:25:41.00#ibcon#read 6, iclass 3, count 0 2006.190.08:25:41.00#ibcon#end of sib2, iclass 3, count 0 2006.190.08:25:41.00#ibcon#*mode == 0, iclass 3, count 0 2006.190.08:25:41.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.190.08:25:41.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.190.08:25:41.00#ibcon#*before write, iclass 3, count 0 2006.190.08:25:41.00#ibcon#enter sib2, iclass 3, count 0 2006.190.08:25:41.00#ibcon#flushed, iclass 3, count 0 2006.190.08:25:41.00#ibcon#about to write, iclass 3, count 0 2006.190.08:25:41.00#ibcon#wrote, iclass 3, count 0 2006.190.08:25:41.00#ibcon#about to read 3, iclass 3, count 0 2006.190.08:25:41.04#ibcon#read 3, iclass 3, count 0 2006.190.08:25:41.04#ibcon#about to read 4, iclass 3, count 0 2006.190.08:25:41.04#ibcon#read 4, iclass 3, count 0 2006.190.08:25:41.04#ibcon#about to read 5, iclass 3, count 0 2006.190.08:25:41.04#ibcon#read 5, iclass 3, count 0 2006.190.08:25:41.04#ibcon#about to read 6, iclass 3, count 0 2006.190.08:25:41.04#ibcon#read 6, iclass 3, count 0 2006.190.08:25:41.04#ibcon#end of sib2, iclass 3, count 0 2006.190.08:25:41.04#ibcon#*after write, iclass 3, count 0 2006.190.08:25:41.04#ibcon#*before return 0, iclass 3, count 0 2006.190.08:25:41.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:41.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.190.08:25:41.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.190.08:25:41.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.190.08:25:41.04$vc4f8/vb=2,4 2006.190.08:25:41.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.190.08:25:41.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.190.08:25:41.04#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:41.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:41.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:41.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:41.10#ibcon#enter wrdev, iclass 5, count 2 2006.190.08:25:41.10#ibcon#first serial, iclass 5, count 2 2006.190.08:25:41.10#ibcon#enter sib2, iclass 5, count 2 2006.190.08:25:41.10#ibcon#flushed, iclass 5, count 2 2006.190.08:25:41.10#ibcon#about to write, iclass 5, count 2 2006.190.08:25:41.10#ibcon#wrote, iclass 5, count 2 2006.190.08:25:41.10#ibcon#about to read 3, iclass 5, count 2 2006.190.08:25:41.12#ibcon#read 3, iclass 5, count 2 2006.190.08:25:41.12#ibcon#about to read 4, iclass 5, count 2 2006.190.08:25:41.12#ibcon#read 4, iclass 5, count 2 2006.190.08:25:41.12#ibcon#about to read 5, iclass 5, count 2 2006.190.08:25:41.12#ibcon#read 5, iclass 5, count 2 2006.190.08:25:41.12#ibcon#about to read 6, iclass 5, count 2 2006.190.08:25:41.12#ibcon#read 6, iclass 5, count 2 2006.190.08:25:41.12#ibcon#end of sib2, iclass 5, count 2 2006.190.08:25:41.12#ibcon#*mode == 0, iclass 5, count 2 2006.190.08:25:41.12#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.190.08:25:41.12#ibcon#[27=AT02-04\r\n] 2006.190.08:25:41.12#ibcon#*before write, iclass 5, count 2 2006.190.08:25:41.12#ibcon#enter sib2, iclass 5, count 2 2006.190.08:25:41.12#ibcon#flushed, iclass 5, count 2 2006.190.08:25:41.12#ibcon#about to write, iclass 5, count 2 2006.190.08:25:41.12#ibcon#wrote, iclass 5, count 2 2006.190.08:25:41.12#ibcon#about to read 3, iclass 5, count 2 2006.190.08:25:41.15#ibcon#read 3, iclass 5, count 2 2006.190.08:25:41.15#ibcon#about to read 4, iclass 5, count 2 2006.190.08:25:41.15#ibcon#read 4, iclass 5, count 2 2006.190.08:25:41.15#ibcon#about to read 5, iclass 5, count 2 2006.190.08:25:41.15#ibcon#read 5, iclass 5, count 2 2006.190.08:25:41.15#ibcon#about to read 6, iclass 5, count 2 2006.190.08:25:41.15#ibcon#read 6, iclass 5, count 2 2006.190.08:25:41.15#ibcon#end of sib2, iclass 5, count 2 2006.190.08:25:41.15#ibcon#*after write, iclass 5, count 2 2006.190.08:25:41.15#ibcon#*before return 0, iclass 5, count 2 2006.190.08:25:41.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:41.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.190.08:25:41.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.190.08:25:41.15#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:41.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:41.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:41.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:41.27#ibcon#enter wrdev, iclass 5, count 0 2006.190.08:25:41.27#ibcon#first serial, iclass 5, count 0 2006.190.08:25:41.27#ibcon#enter sib2, iclass 5, count 0 2006.190.08:25:41.27#ibcon#flushed, iclass 5, count 0 2006.190.08:25:41.27#ibcon#about to write, iclass 5, count 0 2006.190.08:25:41.27#ibcon#wrote, iclass 5, count 0 2006.190.08:25:41.27#ibcon#about to read 3, iclass 5, count 0 2006.190.08:25:41.29#ibcon#read 3, iclass 5, count 0 2006.190.08:25:41.29#ibcon#about to read 4, iclass 5, count 0 2006.190.08:25:41.29#ibcon#read 4, iclass 5, count 0 2006.190.08:25:41.29#ibcon#about to read 5, iclass 5, count 0 2006.190.08:25:41.29#ibcon#read 5, iclass 5, count 0 2006.190.08:25:41.29#ibcon#about to read 6, iclass 5, count 0 2006.190.08:25:41.29#ibcon#read 6, iclass 5, count 0 2006.190.08:25:41.29#ibcon#end of sib2, iclass 5, count 0 2006.190.08:25:41.29#ibcon#*mode == 0, iclass 5, count 0 2006.190.08:25:41.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.190.08:25:41.29#ibcon#[27=USB\r\n] 2006.190.08:25:41.29#ibcon#*before write, iclass 5, count 0 2006.190.08:25:41.29#ibcon#enter sib2, iclass 5, count 0 2006.190.08:25:41.29#ibcon#flushed, iclass 5, count 0 2006.190.08:25:41.29#ibcon#about to write, iclass 5, count 0 2006.190.08:25:41.29#ibcon#wrote, iclass 5, count 0 2006.190.08:25:41.29#ibcon#about to read 3, iclass 5, count 0 2006.190.08:25:41.32#ibcon#read 3, iclass 5, count 0 2006.190.08:25:41.32#ibcon#about to read 4, iclass 5, count 0 2006.190.08:25:41.32#ibcon#read 4, iclass 5, count 0 2006.190.08:25:41.32#ibcon#about to read 5, iclass 5, count 0 2006.190.08:25:41.32#ibcon#read 5, iclass 5, count 0 2006.190.08:25:41.32#ibcon#about to read 6, iclass 5, count 0 2006.190.08:25:41.32#ibcon#read 6, iclass 5, count 0 2006.190.08:25:41.32#ibcon#end of sib2, iclass 5, count 0 2006.190.08:25:41.32#ibcon#*after write, iclass 5, count 0 2006.190.08:25:41.32#ibcon#*before return 0, iclass 5, count 0 2006.190.08:25:41.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:41.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.190.08:25:41.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.190.08:25:41.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.190.08:25:41.32$vc4f8/vblo=3,656.99 2006.190.08:25:41.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.190.08:25:41.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.190.08:25:41.32#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:41.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:41.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:41.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:41.32#ibcon#enter wrdev, iclass 7, count 0 2006.190.08:25:41.32#ibcon#first serial, iclass 7, count 0 2006.190.08:25:41.32#ibcon#enter sib2, iclass 7, count 0 2006.190.08:25:41.32#ibcon#flushed, iclass 7, count 0 2006.190.08:25:41.32#ibcon#about to write, iclass 7, count 0 2006.190.08:25:41.32#ibcon#wrote, iclass 7, count 0 2006.190.08:25:41.32#ibcon#about to read 3, iclass 7, count 0 2006.190.08:25:41.34#ibcon#read 3, iclass 7, count 0 2006.190.08:25:41.34#ibcon#about to read 4, iclass 7, count 0 2006.190.08:25:41.34#ibcon#read 4, iclass 7, count 0 2006.190.08:25:41.34#ibcon#about to read 5, iclass 7, count 0 2006.190.08:25:41.34#ibcon#read 5, iclass 7, count 0 2006.190.08:25:41.34#ibcon#about to read 6, iclass 7, count 0 2006.190.08:25:41.34#ibcon#read 6, iclass 7, count 0 2006.190.08:25:41.34#ibcon#end of sib2, iclass 7, count 0 2006.190.08:25:41.34#ibcon#*mode == 0, iclass 7, count 0 2006.190.08:25:41.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.190.08:25:41.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.190.08:25:41.34#ibcon#*before write, iclass 7, count 0 2006.190.08:25:41.34#ibcon#enter sib2, iclass 7, count 0 2006.190.08:25:41.34#ibcon#flushed, iclass 7, count 0 2006.190.08:25:41.34#ibcon#about to write, iclass 7, count 0 2006.190.08:25:41.34#ibcon#wrote, iclass 7, count 0 2006.190.08:25:41.34#ibcon#about to read 3, iclass 7, count 0 2006.190.08:25:41.38#ibcon#read 3, iclass 7, count 0 2006.190.08:25:41.38#ibcon#about to read 4, iclass 7, count 0 2006.190.08:25:41.38#ibcon#read 4, iclass 7, count 0 2006.190.08:25:41.38#ibcon#about to read 5, iclass 7, count 0 2006.190.08:25:41.38#ibcon#read 5, iclass 7, count 0 2006.190.08:25:41.38#ibcon#about to read 6, iclass 7, count 0 2006.190.08:25:41.38#ibcon#read 6, iclass 7, count 0 2006.190.08:25:41.38#ibcon#end of sib2, iclass 7, count 0 2006.190.08:25:41.38#ibcon#*after write, iclass 7, count 0 2006.190.08:25:41.38#ibcon#*before return 0, iclass 7, count 0 2006.190.08:25:41.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:41.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.190.08:25:41.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.190.08:25:41.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.190.08:25:41.38$vc4f8/vb=3,4 2006.190.08:25:41.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.190.08:25:41.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.190.08:25:41.38#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:41.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:41.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:41.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:41.44#ibcon#enter wrdev, iclass 11, count 2 2006.190.08:25:41.44#ibcon#first serial, iclass 11, count 2 2006.190.08:25:41.44#ibcon#enter sib2, iclass 11, count 2 2006.190.08:25:41.44#ibcon#flushed, iclass 11, count 2 2006.190.08:25:41.44#ibcon#about to write, iclass 11, count 2 2006.190.08:25:41.44#ibcon#wrote, iclass 11, count 2 2006.190.08:25:41.44#ibcon#about to read 3, iclass 11, count 2 2006.190.08:25:41.46#ibcon#read 3, iclass 11, count 2 2006.190.08:25:41.46#ibcon#about to read 4, iclass 11, count 2 2006.190.08:25:41.46#ibcon#read 4, iclass 11, count 2 2006.190.08:25:41.46#ibcon#about to read 5, iclass 11, count 2 2006.190.08:25:41.46#ibcon#read 5, iclass 11, count 2 2006.190.08:25:41.46#ibcon#about to read 6, iclass 11, count 2 2006.190.08:25:41.46#ibcon#read 6, iclass 11, count 2 2006.190.08:25:41.46#ibcon#end of sib2, iclass 11, count 2 2006.190.08:25:41.46#ibcon#*mode == 0, iclass 11, count 2 2006.190.08:25:41.46#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.190.08:25:41.46#ibcon#[27=AT03-04\r\n] 2006.190.08:25:41.46#ibcon#*before write, iclass 11, count 2 2006.190.08:25:41.46#ibcon#enter sib2, iclass 11, count 2 2006.190.08:25:41.46#ibcon#flushed, iclass 11, count 2 2006.190.08:25:41.46#ibcon#about to write, iclass 11, count 2 2006.190.08:25:41.46#ibcon#wrote, iclass 11, count 2 2006.190.08:25:41.46#ibcon#about to read 3, iclass 11, count 2 2006.190.08:25:41.49#ibcon#read 3, iclass 11, count 2 2006.190.08:25:41.49#ibcon#about to read 4, iclass 11, count 2 2006.190.08:25:41.49#ibcon#read 4, iclass 11, count 2 2006.190.08:25:41.49#ibcon#about to read 5, iclass 11, count 2 2006.190.08:25:41.49#ibcon#read 5, iclass 11, count 2 2006.190.08:25:41.49#ibcon#about to read 6, iclass 11, count 2 2006.190.08:25:41.49#ibcon#read 6, iclass 11, count 2 2006.190.08:25:41.49#ibcon#end of sib2, iclass 11, count 2 2006.190.08:25:41.49#ibcon#*after write, iclass 11, count 2 2006.190.08:25:41.49#ibcon#*before return 0, iclass 11, count 2 2006.190.08:25:41.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:41.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.190.08:25:41.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.190.08:25:41.49#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:41.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:41.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:41.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:41.61#ibcon#enter wrdev, iclass 11, count 0 2006.190.08:25:41.61#ibcon#first serial, iclass 11, count 0 2006.190.08:25:41.61#ibcon#enter sib2, iclass 11, count 0 2006.190.08:25:41.61#ibcon#flushed, iclass 11, count 0 2006.190.08:25:41.61#ibcon#about to write, iclass 11, count 0 2006.190.08:25:41.61#ibcon#wrote, iclass 11, count 0 2006.190.08:25:41.61#ibcon#about to read 3, iclass 11, count 0 2006.190.08:25:41.63#ibcon#read 3, iclass 11, count 0 2006.190.08:25:41.63#ibcon#about to read 4, iclass 11, count 0 2006.190.08:25:41.63#ibcon#read 4, iclass 11, count 0 2006.190.08:25:41.63#ibcon#about to read 5, iclass 11, count 0 2006.190.08:25:41.63#ibcon#read 5, iclass 11, count 0 2006.190.08:25:41.63#ibcon#about to read 6, iclass 11, count 0 2006.190.08:25:41.63#ibcon#read 6, iclass 11, count 0 2006.190.08:25:41.63#ibcon#end of sib2, iclass 11, count 0 2006.190.08:25:41.63#ibcon#*mode == 0, iclass 11, count 0 2006.190.08:25:41.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.190.08:25:41.63#ibcon#[27=USB\r\n] 2006.190.08:25:41.63#ibcon#*before write, iclass 11, count 0 2006.190.08:25:41.63#ibcon#enter sib2, iclass 11, count 0 2006.190.08:25:41.63#ibcon#flushed, iclass 11, count 0 2006.190.08:25:41.63#ibcon#about to write, iclass 11, count 0 2006.190.08:25:41.63#ibcon#wrote, iclass 11, count 0 2006.190.08:25:41.63#ibcon#about to read 3, iclass 11, count 0 2006.190.08:25:41.66#ibcon#read 3, iclass 11, count 0 2006.190.08:25:41.66#ibcon#about to read 4, iclass 11, count 0 2006.190.08:25:41.66#ibcon#read 4, iclass 11, count 0 2006.190.08:25:41.66#ibcon#about to read 5, iclass 11, count 0 2006.190.08:25:41.66#ibcon#read 5, iclass 11, count 0 2006.190.08:25:41.66#ibcon#about to read 6, iclass 11, count 0 2006.190.08:25:41.66#ibcon#read 6, iclass 11, count 0 2006.190.08:25:41.66#ibcon#end of sib2, iclass 11, count 0 2006.190.08:25:41.66#ibcon#*after write, iclass 11, count 0 2006.190.08:25:41.66#ibcon#*before return 0, iclass 11, count 0 2006.190.08:25:41.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:41.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.190.08:25:41.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.190.08:25:41.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.190.08:25:41.66$vc4f8/vblo=4,712.99 2006.190.08:25:41.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.190.08:25:41.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.190.08:25:41.66#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:41.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:41.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:41.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:41.66#ibcon#enter wrdev, iclass 13, count 0 2006.190.08:25:41.66#ibcon#first serial, iclass 13, count 0 2006.190.08:25:41.66#ibcon#enter sib2, iclass 13, count 0 2006.190.08:25:41.66#ibcon#flushed, iclass 13, count 0 2006.190.08:25:41.66#ibcon#about to write, iclass 13, count 0 2006.190.08:25:41.66#ibcon#wrote, iclass 13, count 0 2006.190.08:25:41.66#ibcon#about to read 3, iclass 13, count 0 2006.190.08:25:41.68#ibcon#read 3, iclass 13, count 0 2006.190.08:25:41.68#ibcon#about to read 4, iclass 13, count 0 2006.190.08:25:41.68#ibcon#read 4, iclass 13, count 0 2006.190.08:25:41.68#ibcon#about to read 5, iclass 13, count 0 2006.190.08:25:41.68#ibcon#read 5, iclass 13, count 0 2006.190.08:25:41.68#ibcon#about to read 6, iclass 13, count 0 2006.190.08:25:41.68#ibcon#read 6, iclass 13, count 0 2006.190.08:25:41.68#ibcon#end of sib2, iclass 13, count 0 2006.190.08:25:41.68#ibcon#*mode == 0, iclass 13, count 0 2006.190.08:25:41.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.190.08:25:41.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.190.08:25:41.68#ibcon#*before write, iclass 13, count 0 2006.190.08:25:41.68#ibcon#enter sib2, iclass 13, count 0 2006.190.08:25:41.68#ibcon#flushed, iclass 13, count 0 2006.190.08:25:41.68#ibcon#about to write, iclass 13, count 0 2006.190.08:25:41.68#ibcon#wrote, iclass 13, count 0 2006.190.08:25:41.68#ibcon#about to read 3, iclass 13, count 0 2006.190.08:25:41.72#ibcon#read 3, iclass 13, count 0 2006.190.08:25:41.72#ibcon#about to read 4, iclass 13, count 0 2006.190.08:25:41.72#ibcon#read 4, iclass 13, count 0 2006.190.08:25:41.72#ibcon#about to read 5, iclass 13, count 0 2006.190.08:25:41.72#ibcon#read 5, iclass 13, count 0 2006.190.08:25:41.72#ibcon#about to read 6, iclass 13, count 0 2006.190.08:25:41.72#ibcon#read 6, iclass 13, count 0 2006.190.08:25:41.72#ibcon#end of sib2, iclass 13, count 0 2006.190.08:25:41.72#ibcon#*after write, iclass 13, count 0 2006.190.08:25:41.72#ibcon#*before return 0, iclass 13, count 0 2006.190.08:25:41.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:41.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.190.08:25:41.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.190.08:25:41.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.190.08:25:41.72$vc4f8/vb=4,4 2006.190.08:25:41.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.190.08:25:41.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.190.08:25:41.72#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:41.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:41.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:41.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:41.78#ibcon#enter wrdev, iclass 15, count 2 2006.190.08:25:41.78#ibcon#first serial, iclass 15, count 2 2006.190.08:25:41.78#ibcon#enter sib2, iclass 15, count 2 2006.190.08:25:41.78#ibcon#flushed, iclass 15, count 2 2006.190.08:25:41.78#ibcon#about to write, iclass 15, count 2 2006.190.08:25:41.78#ibcon#wrote, iclass 15, count 2 2006.190.08:25:41.78#ibcon#about to read 3, iclass 15, count 2 2006.190.08:25:41.80#ibcon#read 3, iclass 15, count 2 2006.190.08:25:41.80#ibcon#about to read 4, iclass 15, count 2 2006.190.08:25:41.80#ibcon#read 4, iclass 15, count 2 2006.190.08:25:41.80#ibcon#about to read 5, iclass 15, count 2 2006.190.08:25:41.80#ibcon#read 5, iclass 15, count 2 2006.190.08:25:41.80#ibcon#about to read 6, iclass 15, count 2 2006.190.08:25:41.80#ibcon#read 6, iclass 15, count 2 2006.190.08:25:41.80#ibcon#end of sib2, iclass 15, count 2 2006.190.08:25:41.80#ibcon#*mode == 0, iclass 15, count 2 2006.190.08:25:41.80#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.190.08:25:41.80#ibcon#[27=AT04-04\r\n] 2006.190.08:25:41.80#ibcon#*before write, iclass 15, count 2 2006.190.08:25:41.80#ibcon#enter sib2, iclass 15, count 2 2006.190.08:25:41.80#ibcon#flushed, iclass 15, count 2 2006.190.08:25:41.80#ibcon#about to write, iclass 15, count 2 2006.190.08:25:41.80#ibcon#wrote, iclass 15, count 2 2006.190.08:25:41.80#ibcon#about to read 3, iclass 15, count 2 2006.190.08:25:41.83#ibcon#read 3, iclass 15, count 2 2006.190.08:25:41.83#ibcon#about to read 4, iclass 15, count 2 2006.190.08:25:41.83#ibcon#read 4, iclass 15, count 2 2006.190.08:25:41.83#ibcon#about to read 5, iclass 15, count 2 2006.190.08:25:41.83#ibcon#read 5, iclass 15, count 2 2006.190.08:25:41.83#ibcon#about to read 6, iclass 15, count 2 2006.190.08:25:41.83#ibcon#read 6, iclass 15, count 2 2006.190.08:25:41.83#ibcon#end of sib2, iclass 15, count 2 2006.190.08:25:41.83#ibcon#*after write, iclass 15, count 2 2006.190.08:25:41.83#ibcon#*before return 0, iclass 15, count 2 2006.190.08:25:41.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:41.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.190.08:25:41.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.190.08:25:41.83#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:41.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:41.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:41.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:41.95#ibcon#enter wrdev, iclass 15, count 0 2006.190.08:25:41.95#ibcon#first serial, iclass 15, count 0 2006.190.08:25:41.95#ibcon#enter sib2, iclass 15, count 0 2006.190.08:25:41.95#ibcon#flushed, iclass 15, count 0 2006.190.08:25:41.95#ibcon#about to write, iclass 15, count 0 2006.190.08:25:41.95#ibcon#wrote, iclass 15, count 0 2006.190.08:25:41.95#ibcon#about to read 3, iclass 15, count 0 2006.190.08:25:41.97#ibcon#read 3, iclass 15, count 0 2006.190.08:25:41.97#ibcon#about to read 4, iclass 15, count 0 2006.190.08:25:41.97#ibcon#read 4, iclass 15, count 0 2006.190.08:25:41.97#ibcon#about to read 5, iclass 15, count 0 2006.190.08:25:41.97#ibcon#read 5, iclass 15, count 0 2006.190.08:25:41.97#ibcon#about to read 6, iclass 15, count 0 2006.190.08:25:41.97#ibcon#read 6, iclass 15, count 0 2006.190.08:25:41.97#ibcon#end of sib2, iclass 15, count 0 2006.190.08:25:41.97#ibcon#*mode == 0, iclass 15, count 0 2006.190.08:25:41.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.190.08:25:41.97#ibcon#[27=USB\r\n] 2006.190.08:25:41.97#ibcon#*before write, iclass 15, count 0 2006.190.08:25:41.97#ibcon#enter sib2, iclass 15, count 0 2006.190.08:25:41.97#ibcon#flushed, iclass 15, count 0 2006.190.08:25:41.97#ibcon#about to write, iclass 15, count 0 2006.190.08:25:41.97#ibcon#wrote, iclass 15, count 0 2006.190.08:25:41.97#ibcon#about to read 3, iclass 15, count 0 2006.190.08:25:42.00#ibcon#read 3, iclass 15, count 0 2006.190.08:25:42.00#ibcon#about to read 4, iclass 15, count 0 2006.190.08:25:42.00#ibcon#read 4, iclass 15, count 0 2006.190.08:25:42.00#ibcon#about to read 5, iclass 15, count 0 2006.190.08:25:42.00#ibcon#read 5, iclass 15, count 0 2006.190.08:25:42.00#ibcon#about to read 6, iclass 15, count 0 2006.190.08:25:42.00#ibcon#read 6, iclass 15, count 0 2006.190.08:25:42.00#ibcon#end of sib2, iclass 15, count 0 2006.190.08:25:42.00#ibcon#*after write, iclass 15, count 0 2006.190.08:25:42.00#ibcon#*before return 0, iclass 15, count 0 2006.190.08:25:42.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:42.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.190.08:25:42.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.190.08:25:42.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.190.08:25:42.00$vc4f8/vblo=5,744.99 2006.190.08:25:42.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.190.08:25:42.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.190.08:25:42.00#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:42.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:42.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:42.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:42.00#ibcon#enter wrdev, iclass 17, count 0 2006.190.08:25:42.00#ibcon#first serial, iclass 17, count 0 2006.190.08:25:42.00#ibcon#enter sib2, iclass 17, count 0 2006.190.08:25:42.00#ibcon#flushed, iclass 17, count 0 2006.190.08:25:42.00#ibcon#about to write, iclass 17, count 0 2006.190.08:25:42.00#ibcon#wrote, iclass 17, count 0 2006.190.08:25:42.00#ibcon#about to read 3, iclass 17, count 0 2006.190.08:25:42.02#ibcon#read 3, iclass 17, count 0 2006.190.08:25:42.02#ibcon#about to read 4, iclass 17, count 0 2006.190.08:25:42.02#ibcon#read 4, iclass 17, count 0 2006.190.08:25:42.02#ibcon#about to read 5, iclass 17, count 0 2006.190.08:25:42.02#ibcon#read 5, iclass 17, count 0 2006.190.08:25:42.02#ibcon#about to read 6, iclass 17, count 0 2006.190.08:25:42.02#ibcon#read 6, iclass 17, count 0 2006.190.08:25:42.02#ibcon#end of sib2, iclass 17, count 0 2006.190.08:25:42.02#ibcon#*mode == 0, iclass 17, count 0 2006.190.08:25:42.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.190.08:25:42.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.190.08:25:42.02#ibcon#*before write, iclass 17, count 0 2006.190.08:25:42.02#ibcon#enter sib2, iclass 17, count 0 2006.190.08:25:42.02#ibcon#flushed, iclass 17, count 0 2006.190.08:25:42.02#ibcon#about to write, iclass 17, count 0 2006.190.08:25:42.02#ibcon#wrote, iclass 17, count 0 2006.190.08:25:42.02#ibcon#about to read 3, iclass 17, count 0 2006.190.08:25:42.06#ibcon#read 3, iclass 17, count 0 2006.190.08:25:42.06#ibcon#about to read 4, iclass 17, count 0 2006.190.08:25:42.06#ibcon#read 4, iclass 17, count 0 2006.190.08:25:42.06#ibcon#about to read 5, iclass 17, count 0 2006.190.08:25:42.06#ibcon#read 5, iclass 17, count 0 2006.190.08:25:42.06#ibcon#about to read 6, iclass 17, count 0 2006.190.08:25:42.06#ibcon#read 6, iclass 17, count 0 2006.190.08:25:42.06#ibcon#end of sib2, iclass 17, count 0 2006.190.08:25:42.06#ibcon#*after write, iclass 17, count 0 2006.190.08:25:42.06#ibcon#*before return 0, iclass 17, count 0 2006.190.08:25:42.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:42.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.190.08:25:42.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.190.08:25:42.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.190.08:25:42.06$vc4f8/vb=5,4 2006.190.08:25:42.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.190.08:25:42.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.190.08:25:42.06#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:42.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:42.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:42.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:42.12#ibcon#enter wrdev, iclass 19, count 2 2006.190.08:25:42.12#ibcon#first serial, iclass 19, count 2 2006.190.08:25:42.12#ibcon#enter sib2, iclass 19, count 2 2006.190.08:25:42.12#ibcon#flushed, iclass 19, count 2 2006.190.08:25:42.12#ibcon#about to write, iclass 19, count 2 2006.190.08:25:42.12#ibcon#wrote, iclass 19, count 2 2006.190.08:25:42.12#ibcon#about to read 3, iclass 19, count 2 2006.190.08:25:42.14#ibcon#read 3, iclass 19, count 2 2006.190.08:25:42.14#ibcon#about to read 4, iclass 19, count 2 2006.190.08:25:42.14#ibcon#read 4, iclass 19, count 2 2006.190.08:25:42.14#ibcon#about to read 5, iclass 19, count 2 2006.190.08:25:42.14#ibcon#read 5, iclass 19, count 2 2006.190.08:25:42.14#ibcon#about to read 6, iclass 19, count 2 2006.190.08:25:42.14#ibcon#read 6, iclass 19, count 2 2006.190.08:25:42.14#ibcon#end of sib2, iclass 19, count 2 2006.190.08:25:42.14#ibcon#*mode == 0, iclass 19, count 2 2006.190.08:25:42.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.190.08:25:42.14#ibcon#[27=AT05-04\r\n] 2006.190.08:25:42.14#ibcon#*before write, iclass 19, count 2 2006.190.08:25:42.14#ibcon#enter sib2, iclass 19, count 2 2006.190.08:25:42.14#ibcon#flushed, iclass 19, count 2 2006.190.08:25:42.14#ibcon#about to write, iclass 19, count 2 2006.190.08:25:42.14#ibcon#wrote, iclass 19, count 2 2006.190.08:25:42.14#ibcon#about to read 3, iclass 19, count 2 2006.190.08:25:42.17#ibcon#read 3, iclass 19, count 2 2006.190.08:25:42.17#ibcon#about to read 4, iclass 19, count 2 2006.190.08:25:42.17#ibcon#read 4, iclass 19, count 2 2006.190.08:25:42.17#ibcon#about to read 5, iclass 19, count 2 2006.190.08:25:42.17#ibcon#read 5, iclass 19, count 2 2006.190.08:25:42.17#ibcon#about to read 6, iclass 19, count 2 2006.190.08:25:42.17#ibcon#read 6, iclass 19, count 2 2006.190.08:25:42.17#ibcon#end of sib2, iclass 19, count 2 2006.190.08:25:42.17#ibcon#*after write, iclass 19, count 2 2006.190.08:25:42.17#ibcon#*before return 0, iclass 19, count 2 2006.190.08:25:42.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:42.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.190.08:25:42.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.190.08:25:42.17#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:42.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:42.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:42.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:42.29#ibcon#enter wrdev, iclass 19, count 0 2006.190.08:25:42.29#ibcon#first serial, iclass 19, count 0 2006.190.08:25:42.29#ibcon#enter sib2, iclass 19, count 0 2006.190.08:25:42.29#ibcon#flushed, iclass 19, count 0 2006.190.08:25:42.29#ibcon#about to write, iclass 19, count 0 2006.190.08:25:42.29#ibcon#wrote, iclass 19, count 0 2006.190.08:25:42.29#ibcon#about to read 3, iclass 19, count 0 2006.190.08:25:42.31#ibcon#read 3, iclass 19, count 0 2006.190.08:25:42.31#ibcon#about to read 4, iclass 19, count 0 2006.190.08:25:42.31#ibcon#read 4, iclass 19, count 0 2006.190.08:25:42.31#ibcon#about to read 5, iclass 19, count 0 2006.190.08:25:42.31#ibcon#read 5, iclass 19, count 0 2006.190.08:25:42.31#ibcon#about to read 6, iclass 19, count 0 2006.190.08:25:42.31#ibcon#read 6, iclass 19, count 0 2006.190.08:25:42.31#ibcon#end of sib2, iclass 19, count 0 2006.190.08:25:42.31#ibcon#*mode == 0, iclass 19, count 0 2006.190.08:25:42.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.190.08:25:42.31#ibcon#[27=USB\r\n] 2006.190.08:25:42.31#ibcon#*before write, iclass 19, count 0 2006.190.08:25:42.31#ibcon#enter sib2, iclass 19, count 0 2006.190.08:25:42.31#ibcon#flushed, iclass 19, count 0 2006.190.08:25:42.31#ibcon#about to write, iclass 19, count 0 2006.190.08:25:42.31#ibcon#wrote, iclass 19, count 0 2006.190.08:25:42.31#ibcon#about to read 3, iclass 19, count 0 2006.190.08:25:42.34#ibcon#read 3, iclass 19, count 0 2006.190.08:25:42.34#ibcon#about to read 4, iclass 19, count 0 2006.190.08:25:42.34#ibcon#read 4, iclass 19, count 0 2006.190.08:25:42.34#ibcon#about to read 5, iclass 19, count 0 2006.190.08:25:42.34#ibcon#read 5, iclass 19, count 0 2006.190.08:25:42.34#ibcon#about to read 6, iclass 19, count 0 2006.190.08:25:42.34#ibcon#read 6, iclass 19, count 0 2006.190.08:25:42.34#ibcon#end of sib2, iclass 19, count 0 2006.190.08:25:42.34#ibcon#*after write, iclass 19, count 0 2006.190.08:25:42.34#ibcon#*before return 0, iclass 19, count 0 2006.190.08:25:42.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:42.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.190.08:25:42.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.190.08:25:42.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.190.08:25:42.34$vc4f8/vblo=6,752.99 2006.190.08:25:42.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.190.08:25:42.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.190.08:25:42.34#ibcon#ireg 17 cls_cnt 0 2006.190.08:25:42.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:42.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:42.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:42.34#ibcon#enter wrdev, iclass 21, count 0 2006.190.08:25:42.34#ibcon#first serial, iclass 21, count 0 2006.190.08:25:42.34#ibcon#enter sib2, iclass 21, count 0 2006.190.08:25:42.34#ibcon#flushed, iclass 21, count 0 2006.190.08:25:42.34#ibcon#about to write, iclass 21, count 0 2006.190.08:25:42.34#ibcon#wrote, iclass 21, count 0 2006.190.08:25:42.34#ibcon#about to read 3, iclass 21, count 0 2006.190.08:25:42.36#ibcon#read 3, iclass 21, count 0 2006.190.08:25:42.36#ibcon#about to read 4, iclass 21, count 0 2006.190.08:25:42.36#ibcon#read 4, iclass 21, count 0 2006.190.08:25:42.36#ibcon#about to read 5, iclass 21, count 0 2006.190.08:25:42.36#ibcon#read 5, iclass 21, count 0 2006.190.08:25:42.36#ibcon#about to read 6, iclass 21, count 0 2006.190.08:25:42.36#ibcon#read 6, iclass 21, count 0 2006.190.08:25:42.36#ibcon#end of sib2, iclass 21, count 0 2006.190.08:25:42.36#ibcon#*mode == 0, iclass 21, count 0 2006.190.08:25:42.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.190.08:25:42.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.190.08:25:42.36#ibcon#*before write, iclass 21, count 0 2006.190.08:25:42.36#ibcon#enter sib2, iclass 21, count 0 2006.190.08:25:42.36#ibcon#flushed, iclass 21, count 0 2006.190.08:25:42.36#ibcon#about to write, iclass 21, count 0 2006.190.08:25:42.36#ibcon#wrote, iclass 21, count 0 2006.190.08:25:42.36#ibcon#about to read 3, iclass 21, count 0 2006.190.08:25:42.40#ibcon#read 3, iclass 21, count 0 2006.190.08:25:42.40#ibcon#about to read 4, iclass 21, count 0 2006.190.08:25:42.40#ibcon#read 4, iclass 21, count 0 2006.190.08:25:42.40#ibcon#about to read 5, iclass 21, count 0 2006.190.08:25:42.40#ibcon#read 5, iclass 21, count 0 2006.190.08:25:42.40#ibcon#about to read 6, iclass 21, count 0 2006.190.08:25:42.40#ibcon#read 6, iclass 21, count 0 2006.190.08:25:42.40#ibcon#end of sib2, iclass 21, count 0 2006.190.08:25:42.40#ibcon#*after write, iclass 21, count 0 2006.190.08:25:42.40#ibcon#*before return 0, iclass 21, count 0 2006.190.08:25:42.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:42.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.190.08:25:42.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.190.08:25:42.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.190.08:25:42.40$vc4f8/vb=6,4 2006.190.08:25:42.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.190.08:25:42.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.190.08:25:42.40#ibcon#ireg 11 cls_cnt 2 2006.190.08:25:42.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:42.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:42.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:42.46#ibcon#enter wrdev, iclass 23, count 2 2006.190.08:25:42.46#ibcon#first serial, iclass 23, count 2 2006.190.08:25:42.46#ibcon#enter sib2, iclass 23, count 2 2006.190.08:25:42.46#ibcon#flushed, iclass 23, count 2 2006.190.08:25:42.46#ibcon#about to write, iclass 23, count 2 2006.190.08:25:42.46#ibcon#wrote, iclass 23, count 2 2006.190.08:25:42.46#ibcon#about to read 3, iclass 23, count 2 2006.190.08:25:42.48#ibcon#read 3, iclass 23, count 2 2006.190.08:25:42.48#ibcon#about to read 4, iclass 23, count 2 2006.190.08:25:42.48#ibcon#read 4, iclass 23, count 2 2006.190.08:25:42.48#ibcon#about to read 5, iclass 23, count 2 2006.190.08:25:42.48#ibcon#read 5, iclass 23, count 2 2006.190.08:25:42.48#ibcon#about to read 6, iclass 23, count 2 2006.190.08:25:42.48#ibcon#read 6, iclass 23, count 2 2006.190.08:25:42.48#ibcon#end of sib2, iclass 23, count 2 2006.190.08:25:42.48#ibcon#*mode == 0, iclass 23, count 2 2006.190.08:25:42.48#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.190.08:25:42.48#ibcon#[27=AT06-04\r\n] 2006.190.08:25:42.48#ibcon#*before write, iclass 23, count 2 2006.190.08:25:42.48#ibcon#enter sib2, iclass 23, count 2 2006.190.08:25:42.48#ibcon#flushed, iclass 23, count 2 2006.190.08:25:42.48#ibcon#about to write, iclass 23, count 2 2006.190.08:25:42.48#ibcon#wrote, iclass 23, count 2 2006.190.08:25:42.48#ibcon#about to read 3, iclass 23, count 2 2006.190.08:25:42.51#ibcon#read 3, iclass 23, count 2 2006.190.08:25:42.51#ibcon#about to read 4, iclass 23, count 2 2006.190.08:25:42.51#ibcon#read 4, iclass 23, count 2 2006.190.08:25:42.51#ibcon#about to read 5, iclass 23, count 2 2006.190.08:25:42.51#ibcon#read 5, iclass 23, count 2 2006.190.08:25:42.51#ibcon#about to read 6, iclass 23, count 2 2006.190.08:25:42.51#ibcon#read 6, iclass 23, count 2 2006.190.08:25:42.51#ibcon#end of sib2, iclass 23, count 2 2006.190.08:25:42.51#ibcon#*after write, iclass 23, count 2 2006.190.08:25:42.51#ibcon#*before return 0, iclass 23, count 2 2006.190.08:25:42.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:42.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.190.08:25:42.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.190.08:25:42.51#ibcon#ireg 7 cls_cnt 0 2006.190.08:25:42.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:42.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:42.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:42.63#ibcon#enter wrdev, iclass 23, count 0 2006.190.08:25:42.63#ibcon#first serial, iclass 23, count 0 2006.190.08:25:42.63#ibcon#enter sib2, iclass 23, count 0 2006.190.08:25:42.63#ibcon#flushed, iclass 23, count 0 2006.190.08:25:42.63#ibcon#about to write, iclass 23, count 0 2006.190.08:25:42.63#ibcon#wrote, iclass 23, count 0 2006.190.08:25:42.63#ibcon#about to read 3, iclass 23, count 0 2006.190.08:25:42.65#ibcon#read 3, iclass 23, count 0 2006.190.08:25:42.65#ibcon#about to read 4, iclass 23, count 0 2006.190.08:25:42.65#ibcon#read 4, iclass 23, count 0 2006.190.08:25:42.65#ibcon#about to read 5, iclass 23, count 0 2006.190.08:25:42.65#ibcon#read 5, iclass 23, count 0 2006.190.08:25:42.65#ibcon#about to read 6, iclass 23, count 0 2006.190.08:25:42.65#ibcon#read 6, iclass 23, count 0 2006.190.08:25:42.65#ibcon#end of sib2, iclass 23, count 0 2006.190.08:25:42.65#ibcon#*mode == 0, iclass 23, count 0 2006.190.08:25:42.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.190.08:25:42.65#ibcon#[27=USB\r\n] 2006.190.08:25:42.65#ibcon#*before write, iclass 23, count 0 2006.190.08:25:42.65#ibcon#enter sib2, iclass 23, count 0 2006.190.08:25:42.65#ibcon#flushed, iclass 23, count 0 2006.190.08:25:42.65#ibcon#about to write, iclass 23, count 0 2006.190.08:25:42.65#ibcon#wrote, iclass 23, count 0 2006.190.08:25:42.65#ibcon#about to read 3, iclass 23, count 0 2006.190.08:25:42.68#ibcon#read 3, iclass 23, count 0 2006.190.08:25:42.68#ibcon#about to read 4, iclass 23, count 0 2006.190.08:25:42.68#ibcon#read 4, iclass 23, count 0 2006.190.08:25:42.68#ibcon#about to read 5, iclass 23, count 0 2006.190.08:25:42.68#ibcon#read 5, iclass 23, count 0 2006.190.08:25:42.68#ibcon#about to read 6, iclass 23, count 0 2006.190.08:25:42.68#ibcon#read 6, iclass 23, count 0 2006.190.08:25:42.68#ibcon#end of sib2, iclass 23, count 0 2006.190.08:25:42.68#ibcon#*after write, iclass 23, count 0 2006.190.08:25:42.68#ibcon#*before return 0, iclass 23, count 0 2006.190.08:25:42.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:42.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.190.08:25:42.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.190.08:25:42.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.190.08:25:42.68$vc4f8/vabw=wide 2006.190.08:25:42.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.190.08:25:42.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.190.08:25:42.68#ibcon#ireg 8 cls_cnt 0 2006.190.08:25:42.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:42.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:42.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:42.68#ibcon#enter wrdev, iclass 25, count 0 2006.190.08:25:42.68#ibcon#first serial, iclass 25, count 0 2006.190.08:25:42.68#ibcon#enter sib2, iclass 25, count 0 2006.190.08:25:42.68#ibcon#flushed, iclass 25, count 0 2006.190.08:25:42.68#ibcon#about to write, iclass 25, count 0 2006.190.08:25:42.68#ibcon#wrote, iclass 25, count 0 2006.190.08:25:42.68#ibcon#about to read 3, iclass 25, count 0 2006.190.08:25:42.70#ibcon#read 3, iclass 25, count 0 2006.190.08:25:42.70#ibcon#about to read 4, iclass 25, count 0 2006.190.08:25:42.70#ibcon#read 4, iclass 25, count 0 2006.190.08:25:42.70#ibcon#about to read 5, iclass 25, count 0 2006.190.08:25:42.70#ibcon#read 5, iclass 25, count 0 2006.190.08:25:42.70#ibcon#about to read 6, iclass 25, count 0 2006.190.08:25:42.70#ibcon#read 6, iclass 25, count 0 2006.190.08:25:42.70#ibcon#end of sib2, iclass 25, count 0 2006.190.08:25:42.70#ibcon#*mode == 0, iclass 25, count 0 2006.190.08:25:42.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.190.08:25:42.70#ibcon#[25=BW32\r\n] 2006.190.08:25:42.70#ibcon#*before write, iclass 25, count 0 2006.190.08:25:42.70#ibcon#enter sib2, iclass 25, count 0 2006.190.08:25:42.70#ibcon#flushed, iclass 25, count 0 2006.190.08:25:42.70#ibcon#about to write, iclass 25, count 0 2006.190.08:25:42.70#ibcon#wrote, iclass 25, count 0 2006.190.08:25:42.70#ibcon#about to read 3, iclass 25, count 0 2006.190.08:25:42.73#ibcon#read 3, iclass 25, count 0 2006.190.08:25:42.73#ibcon#about to read 4, iclass 25, count 0 2006.190.08:25:42.73#ibcon#read 4, iclass 25, count 0 2006.190.08:25:42.73#ibcon#about to read 5, iclass 25, count 0 2006.190.08:25:42.73#ibcon#read 5, iclass 25, count 0 2006.190.08:25:42.73#ibcon#about to read 6, iclass 25, count 0 2006.190.08:25:42.73#ibcon#read 6, iclass 25, count 0 2006.190.08:25:42.73#ibcon#end of sib2, iclass 25, count 0 2006.190.08:25:42.73#ibcon#*after write, iclass 25, count 0 2006.190.08:25:42.73#ibcon#*before return 0, iclass 25, count 0 2006.190.08:25:42.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:42.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.190.08:25:42.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.190.08:25:42.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.190.08:25:42.73$vc4f8/vbbw=wide 2006.190.08:25:42.73#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.190.08:25:42.73#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.190.08:25:42.73#ibcon#ireg 8 cls_cnt 0 2006.190.08:25:42.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:25:42.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:25:42.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:25:42.80#ibcon#enter wrdev, iclass 27, count 0 2006.190.08:25:42.80#ibcon#first serial, iclass 27, count 0 2006.190.08:25:42.80#ibcon#enter sib2, iclass 27, count 0 2006.190.08:25:42.80#ibcon#flushed, iclass 27, count 0 2006.190.08:25:42.80#ibcon#about to write, iclass 27, count 0 2006.190.08:25:42.80#ibcon#wrote, iclass 27, count 0 2006.190.08:25:42.80#ibcon#about to read 3, iclass 27, count 0 2006.190.08:25:42.82#ibcon#read 3, iclass 27, count 0 2006.190.08:25:42.82#ibcon#about to read 4, iclass 27, count 0 2006.190.08:25:42.82#ibcon#read 4, iclass 27, count 0 2006.190.08:25:42.82#ibcon#about to read 5, iclass 27, count 0 2006.190.08:25:42.82#ibcon#read 5, iclass 27, count 0 2006.190.08:25:42.82#ibcon#about to read 6, iclass 27, count 0 2006.190.08:25:42.82#ibcon#read 6, iclass 27, count 0 2006.190.08:25:42.82#ibcon#end of sib2, iclass 27, count 0 2006.190.08:25:42.82#ibcon#*mode == 0, iclass 27, count 0 2006.190.08:25:42.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.190.08:25:42.82#ibcon#[27=BW32\r\n] 2006.190.08:25:42.82#ibcon#*before write, iclass 27, count 0 2006.190.08:25:42.82#ibcon#enter sib2, iclass 27, count 0 2006.190.08:25:42.82#ibcon#flushed, iclass 27, count 0 2006.190.08:25:42.82#ibcon#about to write, iclass 27, count 0 2006.190.08:25:42.82#ibcon#wrote, iclass 27, count 0 2006.190.08:25:42.82#ibcon#about to read 3, iclass 27, count 0 2006.190.08:25:42.85#ibcon#read 3, iclass 27, count 0 2006.190.08:25:42.85#ibcon#about to read 4, iclass 27, count 0 2006.190.08:25:42.85#ibcon#read 4, iclass 27, count 0 2006.190.08:25:42.85#ibcon#about to read 5, iclass 27, count 0 2006.190.08:25:42.85#ibcon#read 5, iclass 27, count 0 2006.190.08:25:42.85#ibcon#about to read 6, iclass 27, count 0 2006.190.08:25:42.85#ibcon#read 6, iclass 27, count 0 2006.190.08:25:42.85#ibcon#end of sib2, iclass 27, count 0 2006.190.08:25:42.85#ibcon#*after write, iclass 27, count 0 2006.190.08:25:42.85#ibcon#*before return 0, iclass 27, count 0 2006.190.08:25:42.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:25:42.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.190.08:25:42.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.190.08:25:42.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.190.08:25:42.85$4f8m12a/ifd4f 2006.190.08:25:42.85$ifd4f/lo= 2006.190.08:25:42.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.190.08:25:42.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.190.08:25:42.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.190.08:25:42.85$ifd4f/patch= 2006.190.08:25:42.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.190.08:25:42.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.190.08:25:42.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.190.08:25:42.85$4f8m12a/"form=m,16.000,1:2 2006.190.08:25:42.85$4f8m12a/"tpicd 2006.190.08:25:42.85$4f8m12a/echo=off 2006.190.08:25:42.85$4f8m12a/xlog=off 2006.190.08:25:42.85:!2006.190.08:26:10 2006.190.08:25:52.14#trakl#Source acquired 2006.190.08:25:52.14#flagr#flagr/antenna,acquired 2006.190.08:26:10.00:preob 2006.190.08:26:11.14/onsource/TRACKING 2006.190.08:26:11.14:!2006.190.08:26:20 2006.190.08:26:20.00:data_valid=on 2006.190.08:26:20.00:midob 2006.190.08:26:20.14/onsource/TRACKING 2006.190.08:26:20.14/wx/24.39,1012.2,100 2006.190.08:26:20.28/cable/+6.4718E-03 2006.190.08:26:21.37/va/01,08,usb,yes,34,36 2006.190.08:26:21.37/va/02,07,usb,yes,35,36 2006.190.08:26:21.37/va/03,06,usb,yes,36,36 2006.190.08:26:21.37/va/04,07,usb,yes,35,38 2006.190.08:26:21.37/va/05,07,usb,yes,39,41 2006.190.08:26:21.37/va/06,06,usb,yes,38,38 2006.190.08:26:21.37/va/07,06,usb,yes,39,39 2006.190.08:26:21.37/va/08,06,usb,yes,41,41 2006.190.08:26:21.60/valo/01,532.99,yes,locked 2006.190.08:26:21.60/valo/02,572.99,yes,locked 2006.190.08:26:21.60/valo/03,672.99,yes,locked 2006.190.08:26:21.60/valo/04,832.99,yes,locked 2006.190.08:26:21.60/valo/05,652.99,yes,locked 2006.190.08:26:21.60/valo/06,772.99,yes,locked 2006.190.08:26:21.60/valo/07,832.99,yes,locked 2006.190.08:26:21.60/valo/08,852.99,yes,locked 2006.190.08:26:22.69/vb/01,04,usb,yes,31,30 2006.190.08:26:22.69/vb/02,04,usb,yes,33,34 2006.190.08:26:22.69/vb/03,04,usb,yes,29,33 2006.190.08:26:22.69/vb/04,04,usb,yes,30,30 2006.190.08:26:22.69/vb/05,04,usb,yes,29,33 2006.190.08:26:22.69/vb/06,04,usb,yes,30,33 2006.190.08:26:22.69/vb/07,04,usb,yes,32,32 2006.190.08:26:22.69/vb/08,04,usb,yes,29,33 2006.190.08:26:22.92/vblo/01,632.99,yes,locked 2006.190.08:26:22.92/vblo/02,640.99,yes,locked 2006.190.08:26:22.92/vblo/03,656.99,yes,locked 2006.190.08:26:22.92/vblo/04,712.99,yes,locked 2006.190.08:26:22.92/vblo/05,744.99,yes,locked 2006.190.08:26:22.92/vblo/06,752.99,yes,locked 2006.190.08:26:22.92/vblo/07,734.99,yes,locked 2006.190.08:26:22.92/vblo/08,744.99,yes,locked 2006.190.08:26:23.07/vabw/8 2006.190.08:26:23.22/vbbw/8 2006.190.08:26:23.31/xfe/off,on,14.5 2006.190.08:26:23.69/ifatt/23,28,28,28 2006.190.08:26:24.08/fmout-gps/S +2.90E-07 2006.190.08:26:24.16:!2006.190.08:27:20 2006.190.08:27:20.00:data_valid=off 2006.190.08:27:20.00:postob 2006.190.08:27:20.09/cable/+6.4712E-03 2006.190.08:27:20.09/wx/24.39,1012.2,100 2006.190.08:27:21.08/fmout-gps/S +2.89E-07 2006.190.08:27:21.08:checkk5last 2006.190.08:27:21.08&checkk5last/chk_obsdata=1 2006.190.08:27:21.09&checkk5last/chk_obsdata=2 2006.190.08:27:21.09&checkk5last/chk_obsdata=3 2006.190.08:27:21.10&checkk5last/chk_obsdata=4 2006.190.08:27:21.10&checkk5last/k5log=1 2006.190.08:27:21.10&checkk5last/k5log=2 2006.190.08:27:21.11&checkk5last/k5log=3 2006.190.08:27:21.11&checkk5last/k5log=4 2006.190.08:27:21.12&checkk5last/obsinfo 2006.190.08:27:21.50/chk_obsdata//k5ts1/T1900826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:27:21.88/chk_obsdata//k5ts2/T1900826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:27:22.25/chk_obsdata//k5ts3/T1900826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:27:22.62/chk_obsdata//k5ts4/T1900826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.190.08:27:23.33/k5log//k5ts1_log_newline 2006.190.08:27:24.03/k5log//k5ts2_log_newline 2006.190.08:27:24.73/k5log//k5ts3_log_newline 2006.190.08:27:25.43/k5log//k5ts4_log_newline 2006.190.08:27:25.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.190.08:27:25.46:"sched_end 2006.190.08:27:25.46:sy=cp /usr2/log/k06190ts.log /usr2/log_backup/ 2006.190.08:27:25.56:log=u06190ts