2006.188.08:04:42.50;Log Opened: Mark IV Field System Version 9.7.7 2006.188.08:04:42.50;location,TSUKUB32,-140.09,36.10,61.0 2006.188.08:04:42.50;horizon1,0.,5.,360. 2006.188.08:04:42.50;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.188.08:04:42.50;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.188.08:04:42.50;drivev11,330,270,no 2006.188.08:04:42.50;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.188.08:04:42.50;drivev13,15.000,268,10.000,10.000,10.000 2006.188.08:04:42.50;drivev21,330,270,no 2006.188.08:04:42.50;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.188.08:04:42.50;drivev23,15.000,268,10.000,10.000,10.000 2006.188.08:04:42.50;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.188.08:04:42.50;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.188.08:04:42.50;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.188.08:04:42.50;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.188.08:04:42.50;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.188.08:04:42.50;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.188.08:04:42.50;time,-0.364,101.533,rate 2006.188.08:04:42.50;flagr,200 2006.188.08:04:42.50:" K06189 2006 TSUKUB32 T Ts 2006.188.08:04:42.50:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.188.08:04:42.50:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.188.08:04:42.50:" 108 TSUKUB32 14 17400 2006.188.08:04:42.50:" drudg version 050216 compiled under FS 9.7.07 2006.188.08:04:42.50:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.188.08:04:42.50:exper_initi 2006.188.08:04:42.50&exper_initi/proc_library 2006.188.08:04:42.50&exper_initi/sched_initi 2006.188.08:04:42.50:!2006.189.06:29:50 2006.188.08:04:42.50&proc_library/" k06189 tsukub32 ts 2006.188.08:04:42.50&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.188.08:04:42.50&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.188.08:04:42.50&sched_initi/startcheck 2006.188.08:04:42.50&startcheck/sy=check_fsrun.pl & 2006.188.08:04:42.50&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.188.08:05:00.36;cable 2006.188.08:05:00.52/cable/+6.4522E-03 2006.188.08:05:41.61;cablelong 2006.188.08:05:41.84/cablelong/+7.0058E-03 2006.188.08:05:49.78;cablediff 2006.188.08:05:49.78/cablediff/553.6e-6,+ 2006.188.08:05:56.69;cable 2006.188.08:05:56.88/cable/+7.0071E-03 2006.188.08:06:52.98;cable 2006.188.08:06:53.09/cable/+6.4518E-03 2006.188.08:08:21.33;wx 2006.188.08:08:21.33/wx/27.36,1002.3,89 2006.188.08:08:35.92;"Sky is cloudy. 2006.188.08:09:21.81;xfe 2006.188.08:09:21.92/xfe/off,on,14.5 2006.188.08:09:29.28;clockoff 2006.188.08:09:29.28&clockoff/"gps-fmout=1p 2006.188.08:09:29.28&clockoff/fmout-gps=1p 2006.188.08:09:30.08/fmout-gps/S +3.01E-07 2006.188.20:21:09.86?ERROR st -97 Trouble decoding pressure data 2006.188.20:21:09.86#wxget#03 0.9 2.0 23.261001006.6 2006.189.03:17:59.75?ERROR st -97 Trouble decoding pressure data 2006.189.03:17:59.75#wxget#05 2.8 6.1 28.79 801007.9 2006.189.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.189.06:29:50.03:!2006.189.07:19:50 2006.189.07:19:50.00:unstow 2006.189.07:19:50.00&unstow/antenna=e 2006.189.07:19:50.00&unstow/!+10s 2006.189.07:19:50.00&unstow/antenna=m2 2006.189.07:20:02.01:scan_name=189-0730,k06189,60 2006.189.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.189.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.189.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.189.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.189.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.189.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.189.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.189.07:20:03.13:ready_k5 2006.189.07:20:03.13&ready_k5/obsinfo=st 2006.189.07:20:03.13&ready_k5/autoobs=1 2006.189.07:20:03.13&ready_k5/autoobs=2 2006.189.07:20:03.13&ready_k5/autoobs=3 2006.189.07:20:03.13&ready_k5/autoobs=4 2006.189.07:20:03.13&ready_k5/obsinfo 2006.189.07:20:03.13/obsinfo=st/error_log.tmp was not found (or not removed). 2006.189.07:20:03.13#flagr#flagr/antenna,new-source 2006.189.07:20:06.33/autoobs//k5ts1/ autoobs started! 2006.189.07:20:09.46/autoobs//k5ts2/ autoobs started! 2006.189.07:20:12.59/autoobs//k5ts3/ autoobs started! 2006.189.07:20:15.72/autoobs//k5ts4/ autoobs started! 2006.189.07:20:15.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:20:15.75:4f8m12a=1 2006.189.07:20:15.75&4f8m12a/xlog=on 2006.189.07:20:15.75&4f8m12a/echo=on 2006.189.07:20:15.75&4f8m12a/pcalon 2006.189.07:20:15.75&4f8m12a/"tpicd=stop 2006.189.07:20:15.75&4f8m12a/vc4f8 2006.189.07:20:15.75&4f8m12a/ifd4f 2006.189.07:20:15.75&4f8m12a/"form=m,16.000,1:2 2006.189.07:20:15.75&4f8m12a/"tpicd 2006.189.07:20:15.75&4f8m12a/echo=off 2006.189.07:20:15.75&4f8m12a/xlog=off 2006.189.07:20:15.75$4f8m12a/echo=on 2006.189.07:20:15.75$4f8m12a/pcalon 2006.189.07:20:15.75&pcalon/"no phase cal control is implemented here 2006.189.07:20:15.75$pcalon/"no phase cal control is implemented here 2006.189.07:20:15.75$4f8m12a/"tpicd=stop 2006.189.07:20:15.75$4f8m12a/vc4f8 2006.189.07:20:15.75&vc4f8/valo=1,532.99 2006.189.07:20:15.75&vc4f8/va=1,8 2006.189.07:20:15.75&vc4f8/valo=2,572.99 2006.189.07:20:15.75&vc4f8/va=2,7 2006.189.07:20:15.75&vc4f8/valo=3,672.99 2006.189.07:20:15.75&vc4f8/va=3,6 2006.189.07:20:15.75&vc4f8/valo=4,832.99 2006.189.07:20:15.75&vc4f8/va=4,7 2006.189.07:20:15.75&vc4f8/valo=5,652.99 2006.189.07:20:15.75&vc4f8/va=5,7 2006.189.07:20:15.75&vc4f8/valo=6,772.99 2006.189.07:20:15.75&vc4f8/va=6,6 2006.189.07:20:15.75&vc4f8/valo=7,832.99 2006.189.07:20:15.75&vc4f8/va=7,6 2006.189.07:20:15.75&vc4f8/valo=8,852.99 2006.189.07:20:15.75&vc4f8/va=8,6 2006.189.07:20:15.75&vc4f8/vblo=1,632.99 2006.189.07:20:15.75&vc4f8/vb=1,4 2006.189.07:20:15.75&vc4f8/vblo=2,640.99 2006.189.07:20:15.75&vc4f8/vb=2,4 2006.189.07:20:15.75&vc4f8/vblo=3,656.99 2006.189.07:20:15.75&vc4f8/vb=3,4 2006.189.07:20:15.75&vc4f8/vblo=4,712.99 2006.189.07:20:15.75&vc4f8/vb=4,4 2006.189.07:20:15.75&vc4f8/vblo=5,744.99 2006.189.07:20:15.75&vc4f8/vb=5,4 2006.189.07:20:15.75&vc4f8/vblo=6,752.99 2006.189.07:20:15.75&vc4f8/vb=6,4 2006.189.07:20:15.75&vc4f8/vabw=wide 2006.189.07:20:15.75&vc4f8/vbbw=wide 2006.189.07:20:15.75$vc4f8/valo=1,532.99 2006.189.07:20:15.76#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.07:20:15.76#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.07:20:15.76#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:15.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:15.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:15.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:15.76#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:20:15.76#ibcon#first serial, iclass 31, count 0 2006.189.07:20:15.76#ibcon#enter sib2, iclass 31, count 0 2006.189.07:20:15.76#ibcon#flushed, iclass 31, count 0 2006.189.07:20:15.76#ibcon#about to write, iclass 31, count 0 2006.189.07:20:15.76#ibcon#wrote, iclass 31, count 0 2006.189.07:20:15.76#ibcon#about to read 3, iclass 31, count 0 2006.189.07:20:15.80#ibcon#read 3, iclass 31, count 0 2006.189.07:20:15.80#ibcon#about to read 4, iclass 31, count 0 2006.189.07:20:15.80#ibcon#read 4, iclass 31, count 0 2006.189.07:20:15.80#ibcon#about to read 5, iclass 31, count 0 2006.189.07:20:15.80#ibcon#read 5, iclass 31, count 0 2006.189.07:20:15.80#ibcon#about to read 6, iclass 31, count 0 2006.189.07:20:15.80#ibcon#read 6, iclass 31, count 0 2006.189.07:20:15.80#ibcon#end of sib2, iclass 31, count 0 2006.189.07:20:15.80#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:20:15.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:20:15.80#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:20:15.80#ibcon#*before write, iclass 31, count 0 2006.189.07:20:15.80#ibcon#enter sib2, iclass 31, count 0 2006.189.07:20:15.80#ibcon#flushed, iclass 31, count 0 2006.189.07:20:15.80#ibcon#about to write, iclass 31, count 0 2006.189.07:20:15.80#ibcon#wrote, iclass 31, count 0 2006.189.07:20:15.80#ibcon#about to read 3, iclass 31, count 0 2006.189.07:20:15.86#ibcon#read 3, iclass 31, count 0 2006.189.07:20:15.86#ibcon#about to read 4, iclass 31, count 0 2006.189.07:20:15.86#ibcon#read 4, iclass 31, count 0 2006.189.07:20:15.86#ibcon#about to read 5, iclass 31, count 0 2006.189.07:20:15.86#ibcon#read 5, iclass 31, count 0 2006.189.07:20:15.86#ibcon#about to read 6, iclass 31, count 0 2006.189.07:20:15.86#ibcon#read 6, iclass 31, count 0 2006.189.07:20:15.86#ibcon#end of sib2, iclass 31, count 0 2006.189.07:20:15.86#ibcon#*after write, iclass 31, count 0 2006.189.07:20:15.86#ibcon#*before return 0, iclass 31, count 0 2006.189.07:20:15.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:15.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:15.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:20:15.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:20:15.86$vc4f8/va=1,8 2006.189.07:20:15.86#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.07:20:15.86#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.07:20:15.86#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:15.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:15.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:15.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:15.86#ibcon#enter wrdev, iclass 33, count 2 2006.189.07:20:15.86#ibcon#first serial, iclass 33, count 2 2006.189.07:20:15.86#ibcon#enter sib2, iclass 33, count 2 2006.189.07:20:15.86#ibcon#flushed, iclass 33, count 2 2006.189.07:20:15.86#ibcon#about to write, iclass 33, count 2 2006.189.07:20:15.86#ibcon#wrote, iclass 33, count 2 2006.189.07:20:15.86#ibcon#about to read 3, iclass 33, count 2 2006.189.07:20:15.88#ibcon#read 3, iclass 33, count 2 2006.189.07:20:15.88#ibcon#about to read 4, iclass 33, count 2 2006.189.07:20:15.88#ibcon#read 4, iclass 33, count 2 2006.189.07:20:15.88#ibcon#about to read 5, iclass 33, count 2 2006.189.07:20:15.88#ibcon#read 5, iclass 33, count 2 2006.189.07:20:15.88#ibcon#about to read 6, iclass 33, count 2 2006.189.07:20:15.88#ibcon#read 6, iclass 33, count 2 2006.189.07:20:15.88#ibcon#end of sib2, iclass 33, count 2 2006.189.07:20:15.88#ibcon#*mode == 0, iclass 33, count 2 2006.189.07:20:15.88#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.07:20:15.88#ibcon#[25=AT01-08\r\n] 2006.189.07:20:15.88#ibcon#*before write, iclass 33, count 2 2006.189.07:20:15.88#ibcon#enter sib2, iclass 33, count 2 2006.189.07:20:15.88#ibcon#flushed, iclass 33, count 2 2006.189.07:20:15.88#ibcon#about to write, iclass 33, count 2 2006.189.07:20:15.88#ibcon#wrote, iclass 33, count 2 2006.189.07:20:15.88#ibcon#about to read 3, iclass 33, count 2 2006.189.07:20:15.92#ibcon#read 3, iclass 33, count 2 2006.189.07:20:15.92#ibcon#about to read 4, iclass 33, count 2 2006.189.07:20:15.92#ibcon#read 4, iclass 33, count 2 2006.189.07:20:15.92#ibcon#about to read 5, iclass 33, count 2 2006.189.07:20:15.92#ibcon#read 5, iclass 33, count 2 2006.189.07:20:15.92#ibcon#about to read 6, iclass 33, count 2 2006.189.07:20:15.92#ibcon#read 6, iclass 33, count 2 2006.189.07:20:15.92#ibcon#end of sib2, iclass 33, count 2 2006.189.07:20:15.92#ibcon#*after write, iclass 33, count 2 2006.189.07:20:15.92#ibcon#*before return 0, iclass 33, count 2 2006.189.07:20:15.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:15.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:15.92#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.07:20:15.92#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:15.92#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:16.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:16.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:16.04#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:20:16.04#ibcon#first serial, iclass 33, count 0 2006.189.07:20:16.04#ibcon#enter sib2, iclass 33, count 0 2006.189.07:20:16.04#ibcon#flushed, iclass 33, count 0 2006.189.07:20:16.04#ibcon#about to write, iclass 33, count 0 2006.189.07:20:16.04#ibcon#wrote, iclass 33, count 0 2006.189.07:20:16.04#ibcon#about to read 3, iclass 33, count 0 2006.189.07:20:16.06#ibcon#read 3, iclass 33, count 0 2006.189.07:20:16.06#ibcon#about to read 4, iclass 33, count 0 2006.189.07:20:16.06#ibcon#read 4, iclass 33, count 0 2006.189.07:20:16.06#ibcon#about to read 5, iclass 33, count 0 2006.189.07:20:16.06#ibcon#read 5, iclass 33, count 0 2006.189.07:20:16.06#ibcon#about to read 6, iclass 33, count 0 2006.189.07:20:16.06#ibcon#read 6, iclass 33, count 0 2006.189.07:20:16.06#ibcon#end of sib2, iclass 33, count 0 2006.189.07:20:16.06#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:20:16.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:20:16.06#ibcon#[25=USB\r\n] 2006.189.07:20:16.06#ibcon#*before write, iclass 33, count 0 2006.189.07:20:16.06#ibcon#enter sib2, iclass 33, count 0 2006.189.07:20:16.06#ibcon#flushed, iclass 33, count 0 2006.189.07:20:16.06#ibcon#about to write, iclass 33, count 0 2006.189.07:20:16.06#ibcon#wrote, iclass 33, count 0 2006.189.07:20:16.06#ibcon#about to read 3, iclass 33, count 0 2006.189.07:20:16.09#ibcon#read 3, iclass 33, count 0 2006.189.07:20:16.09#ibcon#about to read 4, iclass 33, count 0 2006.189.07:20:16.09#ibcon#read 4, iclass 33, count 0 2006.189.07:20:16.09#ibcon#about to read 5, iclass 33, count 0 2006.189.07:20:16.09#ibcon#read 5, iclass 33, count 0 2006.189.07:20:16.09#ibcon#about to read 6, iclass 33, count 0 2006.189.07:20:16.09#ibcon#read 6, iclass 33, count 0 2006.189.07:20:16.09#ibcon#end of sib2, iclass 33, count 0 2006.189.07:20:16.09#ibcon#*after write, iclass 33, count 0 2006.189.07:20:16.09#ibcon#*before return 0, iclass 33, count 0 2006.189.07:20:16.09#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:16.09#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:16.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:20:16.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:20:16.09$vc4f8/valo=2,572.99 2006.189.07:20:16.09#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.07:20:16.09#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.07:20:16.09#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:16.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:16.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:16.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:16.09#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:20:16.09#ibcon#first serial, iclass 35, count 0 2006.189.07:20:16.09#ibcon#enter sib2, iclass 35, count 0 2006.189.07:20:16.09#ibcon#flushed, iclass 35, count 0 2006.189.07:20:16.09#ibcon#about to write, iclass 35, count 0 2006.189.07:20:16.09#ibcon#wrote, iclass 35, count 0 2006.189.07:20:16.09#ibcon#about to read 3, iclass 35, count 0 2006.189.07:20:16.11#ibcon#read 3, iclass 35, count 0 2006.189.07:20:16.11#ibcon#about to read 4, iclass 35, count 0 2006.189.07:20:16.11#ibcon#read 4, iclass 35, count 0 2006.189.07:20:16.11#ibcon#about to read 5, iclass 35, count 0 2006.189.07:20:16.11#ibcon#read 5, iclass 35, count 0 2006.189.07:20:16.11#ibcon#about to read 6, iclass 35, count 0 2006.189.07:20:16.11#ibcon#read 6, iclass 35, count 0 2006.189.07:20:16.11#ibcon#end of sib2, iclass 35, count 0 2006.189.07:20:16.11#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:20:16.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:20:16.11#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:20:16.11#ibcon#*before write, iclass 35, count 0 2006.189.07:20:16.11#ibcon#enter sib2, iclass 35, count 0 2006.189.07:20:16.11#ibcon#flushed, iclass 35, count 0 2006.189.07:20:16.11#ibcon#about to write, iclass 35, count 0 2006.189.07:20:16.11#ibcon#wrote, iclass 35, count 0 2006.189.07:20:16.11#ibcon#about to read 3, iclass 35, count 0 2006.189.07:20:16.15#ibcon#read 3, iclass 35, count 0 2006.189.07:20:16.15#ibcon#about to read 4, iclass 35, count 0 2006.189.07:20:16.15#ibcon#read 4, iclass 35, count 0 2006.189.07:20:16.15#ibcon#about to read 5, iclass 35, count 0 2006.189.07:20:16.15#ibcon#read 5, iclass 35, count 0 2006.189.07:20:16.15#ibcon#about to read 6, iclass 35, count 0 2006.189.07:20:16.15#ibcon#read 6, iclass 35, count 0 2006.189.07:20:16.15#ibcon#end of sib2, iclass 35, count 0 2006.189.07:20:16.15#ibcon#*after write, iclass 35, count 0 2006.189.07:20:16.15#ibcon#*before return 0, iclass 35, count 0 2006.189.07:20:16.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:16.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:16.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:20:16.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:20:16.15$vc4f8/va=2,7 2006.189.07:20:16.15#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.07:20:16.15#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.07:20:16.15#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:16.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:16.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:16.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:16.21#ibcon#enter wrdev, iclass 37, count 2 2006.189.07:20:16.21#ibcon#first serial, iclass 37, count 2 2006.189.07:20:16.21#ibcon#enter sib2, iclass 37, count 2 2006.189.07:20:16.21#ibcon#flushed, iclass 37, count 2 2006.189.07:20:16.21#ibcon#about to write, iclass 37, count 2 2006.189.07:20:16.21#ibcon#wrote, iclass 37, count 2 2006.189.07:20:16.21#ibcon#about to read 3, iclass 37, count 2 2006.189.07:20:16.23#ibcon#read 3, iclass 37, count 2 2006.189.07:20:16.23#ibcon#about to read 4, iclass 37, count 2 2006.189.07:20:16.23#ibcon#read 4, iclass 37, count 2 2006.189.07:20:16.23#ibcon#about to read 5, iclass 37, count 2 2006.189.07:20:16.23#ibcon#read 5, iclass 37, count 2 2006.189.07:20:16.23#ibcon#about to read 6, iclass 37, count 2 2006.189.07:20:16.23#ibcon#read 6, iclass 37, count 2 2006.189.07:20:16.23#ibcon#end of sib2, iclass 37, count 2 2006.189.07:20:16.23#ibcon#*mode == 0, iclass 37, count 2 2006.189.07:20:16.23#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.07:20:16.23#ibcon#[25=AT02-07\r\n] 2006.189.07:20:16.23#ibcon#*before write, iclass 37, count 2 2006.189.07:20:16.23#ibcon#enter sib2, iclass 37, count 2 2006.189.07:20:16.23#ibcon#flushed, iclass 37, count 2 2006.189.07:20:16.23#ibcon#about to write, iclass 37, count 2 2006.189.07:20:16.23#ibcon#wrote, iclass 37, count 2 2006.189.07:20:16.23#ibcon#about to read 3, iclass 37, count 2 2006.189.07:20:16.26#ibcon#read 3, iclass 37, count 2 2006.189.07:20:16.26#ibcon#about to read 4, iclass 37, count 2 2006.189.07:20:16.26#ibcon#read 4, iclass 37, count 2 2006.189.07:20:16.26#ibcon#about to read 5, iclass 37, count 2 2006.189.07:20:16.26#ibcon#read 5, iclass 37, count 2 2006.189.07:20:16.26#ibcon#about to read 6, iclass 37, count 2 2006.189.07:20:16.26#ibcon#read 6, iclass 37, count 2 2006.189.07:20:16.26#ibcon#end of sib2, iclass 37, count 2 2006.189.07:20:16.26#ibcon#*after write, iclass 37, count 2 2006.189.07:20:16.26#ibcon#*before return 0, iclass 37, count 2 2006.189.07:20:16.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:16.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:16.26#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.07:20:16.26#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:16.26#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:16.38#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:16.38#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:16.38#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:20:16.38#ibcon#first serial, iclass 37, count 0 2006.189.07:20:16.38#ibcon#enter sib2, iclass 37, count 0 2006.189.07:20:16.38#ibcon#flushed, iclass 37, count 0 2006.189.07:20:16.38#ibcon#about to write, iclass 37, count 0 2006.189.07:20:16.38#ibcon#wrote, iclass 37, count 0 2006.189.07:20:16.38#ibcon#about to read 3, iclass 37, count 0 2006.189.07:20:16.40#ibcon#read 3, iclass 37, count 0 2006.189.07:20:16.40#ibcon#about to read 4, iclass 37, count 0 2006.189.07:20:16.40#ibcon#read 4, iclass 37, count 0 2006.189.07:20:16.40#ibcon#about to read 5, iclass 37, count 0 2006.189.07:20:16.40#ibcon#read 5, iclass 37, count 0 2006.189.07:20:16.40#ibcon#about to read 6, iclass 37, count 0 2006.189.07:20:16.40#ibcon#read 6, iclass 37, count 0 2006.189.07:20:16.40#ibcon#end of sib2, iclass 37, count 0 2006.189.07:20:16.40#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:20:16.40#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:20:16.40#ibcon#[25=USB\r\n] 2006.189.07:20:16.40#ibcon#*before write, iclass 37, count 0 2006.189.07:20:16.40#ibcon#enter sib2, iclass 37, count 0 2006.189.07:20:16.40#ibcon#flushed, iclass 37, count 0 2006.189.07:20:16.40#ibcon#about to write, iclass 37, count 0 2006.189.07:20:16.40#ibcon#wrote, iclass 37, count 0 2006.189.07:20:16.40#ibcon#about to read 3, iclass 37, count 0 2006.189.07:20:16.43#ibcon#read 3, iclass 37, count 0 2006.189.07:20:16.43#ibcon#about to read 4, iclass 37, count 0 2006.189.07:20:16.43#ibcon#read 4, iclass 37, count 0 2006.189.07:20:16.43#ibcon#about to read 5, iclass 37, count 0 2006.189.07:20:16.43#ibcon#read 5, iclass 37, count 0 2006.189.07:20:16.43#ibcon#about to read 6, iclass 37, count 0 2006.189.07:20:16.43#ibcon#read 6, iclass 37, count 0 2006.189.07:20:16.43#ibcon#end of sib2, iclass 37, count 0 2006.189.07:20:16.43#ibcon#*after write, iclass 37, count 0 2006.189.07:20:16.43#ibcon#*before return 0, iclass 37, count 0 2006.189.07:20:16.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:16.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:16.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:20:16.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:20:16.43$vc4f8/valo=3,672.99 2006.189.07:20:16.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.07:20:16.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.07:20:16.43#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:16.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:16.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:16.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:16.43#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:20:16.43#ibcon#first serial, iclass 39, count 0 2006.189.07:20:16.43#ibcon#enter sib2, iclass 39, count 0 2006.189.07:20:16.43#ibcon#flushed, iclass 39, count 0 2006.189.07:20:16.43#ibcon#about to write, iclass 39, count 0 2006.189.07:20:16.43#ibcon#wrote, iclass 39, count 0 2006.189.07:20:16.43#ibcon#about to read 3, iclass 39, count 0 2006.189.07:20:16.45#ibcon#read 3, iclass 39, count 0 2006.189.07:20:16.45#ibcon#about to read 4, iclass 39, count 0 2006.189.07:20:16.45#ibcon#read 4, iclass 39, count 0 2006.189.07:20:16.45#ibcon#about to read 5, iclass 39, count 0 2006.189.07:20:16.45#ibcon#read 5, iclass 39, count 0 2006.189.07:20:16.45#ibcon#about to read 6, iclass 39, count 0 2006.189.07:20:16.45#ibcon#read 6, iclass 39, count 0 2006.189.07:20:16.45#ibcon#end of sib2, iclass 39, count 0 2006.189.07:20:16.45#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:20:16.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:20:16.45#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:20:16.45#ibcon#*before write, iclass 39, count 0 2006.189.07:20:16.45#ibcon#enter sib2, iclass 39, count 0 2006.189.07:20:16.45#ibcon#flushed, iclass 39, count 0 2006.189.07:20:16.45#ibcon#about to write, iclass 39, count 0 2006.189.07:20:16.45#ibcon#wrote, iclass 39, count 0 2006.189.07:20:16.45#ibcon#about to read 3, iclass 39, count 0 2006.189.07:20:16.49#ibcon#read 3, iclass 39, count 0 2006.189.07:20:16.49#ibcon#about to read 4, iclass 39, count 0 2006.189.07:20:16.49#ibcon#read 4, iclass 39, count 0 2006.189.07:20:16.49#ibcon#about to read 5, iclass 39, count 0 2006.189.07:20:16.49#ibcon#read 5, iclass 39, count 0 2006.189.07:20:16.49#ibcon#about to read 6, iclass 39, count 0 2006.189.07:20:16.49#ibcon#read 6, iclass 39, count 0 2006.189.07:20:16.49#ibcon#end of sib2, iclass 39, count 0 2006.189.07:20:16.49#ibcon#*after write, iclass 39, count 0 2006.189.07:20:16.49#ibcon#*before return 0, iclass 39, count 0 2006.189.07:20:16.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:16.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:16.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:20:16.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:20:16.49$vc4f8/va=3,6 2006.189.07:20:16.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.07:20:16.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.07:20:16.49#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:16.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:16.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:16.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:16.55#ibcon#enter wrdev, iclass 3, count 2 2006.189.07:20:16.55#ibcon#first serial, iclass 3, count 2 2006.189.07:20:16.55#ibcon#enter sib2, iclass 3, count 2 2006.189.07:20:16.55#ibcon#flushed, iclass 3, count 2 2006.189.07:20:16.55#ibcon#about to write, iclass 3, count 2 2006.189.07:20:16.55#ibcon#wrote, iclass 3, count 2 2006.189.07:20:16.55#ibcon#about to read 3, iclass 3, count 2 2006.189.07:20:16.57#ibcon#read 3, iclass 3, count 2 2006.189.07:20:16.57#ibcon#about to read 4, iclass 3, count 2 2006.189.07:20:16.57#ibcon#read 4, iclass 3, count 2 2006.189.07:20:16.57#ibcon#about to read 5, iclass 3, count 2 2006.189.07:20:16.57#ibcon#read 5, iclass 3, count 2 2006.189.07:20:16.57#ibcon#about to read 6, iclass 3, count 2 2006.189.07:20:16.57#ibcon#read 6, iclass 3, count 2 2006.189.07:20:16.57#ibcon#end of sib2, iclass 3, count 2 2006.189.07:20:16.57#ibcon#*mode == 0, iclass 3, count 2 2006.189.07:20:16.57#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.07:20:16.57#ibcon#[25=AT03-06\r\n] 2006.189.07:20:16.57#ibcon#*before write, iclass 3, count 2 2006.189.07:20:16.57#ibcon#enter sib2, iclass 3, count 2 2006.189.07:20:16.57#ibcon#flushed, iclass 3, count 2 2006.189.07:20:16.57#ibcon#about to write, iclass 3, count 2 2006.189.07:20:16.57#ibcon#wrote, iclass 3, count 2 2006.189.07:20:16.57#ibcon#about to read 3, iclass 3, count 2 2006.189.07:20:16.60#ibcon#read 3, iclass 3, count 2 2006.189.07:20:16.60#ibcon#about to read 4, iclass 3, count 2 2006.189.07:20:16.60#ibcon#read 4, iclass 3, count 2 2006.189.07:20:16.60#ibcon#about to read 5, iclass 3, count 2 2006.189.07:20:16.60#ibcon#read 5, iclass 3, count 2 2006.189.07:20:16.60#ibcon#about to read 6, iclass 3, count 2 2006.189.07:20:16.60#ibcon#read 6, iclass 3, count 2 2006.189.07:20:16.60#ibcon#end of sib2, iclass 3, count 2 2006.189.07:20:16.60#ibcon#*after write, iclass 3, count 2 2006.189.07:20:16.60#ibcon#*before return 0, iclass 3, count 2 2006.189.07:20:16.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:16.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:16.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.07:20:16.60#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:16.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:16.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:16.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:16.72#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:20:16.72#ibcon#first serial, iclass 3, count 0 2006.189.07:20:16.72#ibcon#enter sib2, iclass 3, count 0 2006.189.07:20:16.72#ibcon#flushed, iclass 3, count 0 2006.189.07:20:16.72#ibcon#about to write, iclass 3, count 0 2006.189.07:20:16.72#ibcon#wrote, iclass 3, count 0 2006.189.07:20:16.72#ibcon#about to read 3, iclass 3, count 0 2006.189.07:20:16.74#ibcon#read 3, iclass 3, count 0 2006.189.07:20:16.74#ibcon#about to read 4, iclass 3, count 0 2006.189.07:20:16.74#ibcon#read 4, iclass 3, count 0 2006.189.07:20:16.74#ibcon#about to read 5, iclass 3, count 0 2006.189.07:20:16.74#ibcon#read 5, iclass 3, count 0 2006.189.07:20:16.74#ibcon#about to read 6, iclass 3, count 0 2006.189.07:20:16.74#ibcon#read 6, iclass 3, count 0 2006.189.07:20:16.74#ibcon#end of sib2, iclass 3, count 0 2006.189.07:20:16.74#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:20:16.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:20:16.74#ibcon#[25=USB\r\n] 2006.189.07:20:16.74#ibcon#*before write, iclass 3, count 0 2006.189.07:20:16.74#ibcon#enter sib2, iclass 3, count 0 2006.189.07:20:16.74#ibcon#flushed, iclass 3, count 0 2006.189.07:20:16.74#ibcon#about to write, iclass 3, count 0 2006.189.07:20:16.74#ibcon#wrote, iclass 3, count 0 2006.189.07:20:16.74#ibcon#about to read 3, iclass 3, count 0 2006.189.07:20:16.77#ibcon#read 3, iclass 3, count 0 2006.189.07:20:16.77#ibcon#about to read 4, iclass 3, count 0 2006.189.07:20:16.77#ibcon#read 4, iclass 3, count 0 2006.189.07:20:16.77#ibcon#about to read 5, iclass 3, count 0 2006.189.07:20:16.77#ibcon#read 5, iclass 3, count 0 2006.189.07:20:16.77#ibcon#about to read 6, iclass 3, count 0 2006.189.07:20:16.77#ibcon#read 6, iclass 3, count 0 2006.189.07:20:16.77#ibcon#end of sib2, iclass 3, count 0 2006.189.07:20:16.77#ibcon#*after write, iclass 3, count 0 2006.189.07:20:16.77#ibcon#*before return 0, iclass 3, count 0 2006.189.07:20:16.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:16.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:16.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:20:16.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:20:16.77$vc4f8/valo=4,832.99 2006.189.07:20:16.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.07:20:16.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.07:20:16.77#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:16.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:16.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:16.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:16.77#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:20:16.77#ibcon#first serial, iclass 5, count 0 2006.189.07:20:16.77#ibcon#enter sib2, iclass 5, count 0 2006.189.07:20:16.77#ibcon#flushed, iclass 5, count 0 2006.189.07:20:16.77#ibcon#about to write, iclass 5, count 0 2006.189.07:20:16.77#ibcon#wrote, iclass 5, count 0 2006.189.07:20:16.77#ibcon#about to read 3, iclass 5, count 0 2006.189.07:20:16.79#ibcon#read 3, iclass 5, count 0 2006.189.07:20:16.79#ibcon#about to read 4, iclass 5, count 0 2006.189.07:20:16.79#ibcon#read 4, iclass 5, count 0 2006.189.07:20:16.79#ibcon#about to read 5, iclass 5, count 0 2006.189.07:20:16.79#ibcon#read 5, iclass 5, count 0 2006.189.07:20:16.79#ibcon#about to read 6, iclass 5, count 0 2006.189.07:20:16.79#ibcon#read 6, iclass 5, count 0 2006.189.07:20:16.79#ibcon#end of sib2, iclass 5, count 0 2006.189.07:20:16.79#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:20:16.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:20:16.79#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:20:16.79#ibcon#*before write, iclass 5, count 0 2006.189.07:20:16.79#ibcon#enter sib2, iclass 5, count 0 2006.189.07:20:16.79#ibcon#flushed, iclass 5, count 0 2006.189.07:20:16.79#ibcon#about to write, iclass 5, count 0 2006.189.07:20:16.79#ibcon#wrote, iclass 5, count 0 2006.189.07:20:16.79#ibcon#about to read 3, iclass 5, count 0 2006.189.07:20:16.83#ibcon#read 3, iclass 5, count 0 2006.189.07:20:16.83#ibcon#about to read 4, iclass 5, count 0 2006.189.07:20:16.83#ibcon#read 4, iclass 5, count 0 2006.189.07:20:16.83#ibcon#about to read 5, iclass 5, count 0 2006.189.07:20:16.83#ibcon#read 5, iclass 5, count 0 2006.189.07:20:16.83#ibcon#about to read 6, iclass 5, count 0 2006.189.07:20:16.83#ibcon#read 6, iclass 5, count 0 2006.189.07:20:16.83#ibcon#end of sib2, iclass 5, count 0 2006.189.07:20:16.83#ibcon#*after write, iclass 5, count 0 2006.189.07:20:16.83#ibcon#*before return 0, iclass 5, count 0 2006.189.07:20:16.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:16.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:16.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:20:16.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:20:16.83$vc4f8/va=4,7 2006.189.07:20:16.83#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.07:20:16.83#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.07:20:16.83#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:16.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:16.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:16.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:16.89#ibcon#enter wrdev, iclass 7, count 2 2006.189.07:20:16.89#ibcon#first serial, iclass 7, count 2 2006.189.07:20:16.89#ibcon#enter sib2, iclass 7, count 2 2006.189.07:20:16.89#ibcon#flushed, iclass 7, count 2 2006.189.07:20:16.89#ibcon#about to write, iclass 7, count 2 2006.189.07:20:16.89#ibcon#wrote, iclass 7, count 2 2006.189.07:20:16.89#ibcon#about to read 3, iclass 7, count 2 2006.189.07:20:16.91#ibcon#read 3, iclass 7, count 2 2006.189.07:20:16.91#ibcon#about to read 4, iclass 7, count 2 2006.189.07:20:16.91#ibcon#read 4, iclass 7, count 2 2006.189.07:20:16.91#ibcon#about to read 5, iclass 7, count 2 2006.189.07:20:16.91#ibcon#read 5, iclass 7, count 2 2006.189.07:20:16.91#ibcon#about to read 6, iclass 7, count 2 2006.189.07:20:16.91#ibcon#read 6, iclass 7, count 2 2006.189.07:20:16.91#ibcon#end of sib2, iclass 7, count 2 2006.189.07:20:16.91#ibcon#*mode == 0, iclass 7, count 2 2006.189.07:20:16.91#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.07:20:16.91#ibcon#[25=AT04-07\r\n] 2006.189.07:20:16.91#ibcon#*before write, iclass 7, count 2 2006.189.07:20:16.91#ibcon#enter sib2, iclass 7, count 2 2006.189.07:20:16.91#ibcon#flushed, iclass 7, count 2 2006.189.07:20:16.91#ibcon#about to write, iclass 7, count 2 2006.189.07:20:16.91#ibcon#wrote, iclass 7, count 2 2006.189.07:20:16.91#ibcon#about to read 3, iclass 7, count 2 2006.189.07:20:16.94#ibcon#read 3, iclass 7, count 2 2006.189.07:20:16.94#ibcon#about to read 4, iclass 7, count 2 2006.189.07:20:16.94#ibcon#read 4, iclass 7, count 2 2006.189.07:20:16.94#ibcon#about to read 5, iclass 7, count 2 2006.189.07:20:16.94#ibcon#read 5, iclass 7, count 2 2006.189.07:20:16.94#ibcon#about to read 6, iclass 7, count 2 2006.189.07:20:16.94#ibcon#read 6, iclass 7, count 2 2006.189.07:20:16.94#ibcon#end of sib2, iclass 7, count 2 2006.189.07:20:16.94#ibcon#*after write, iclass 7, count 2 2006.189.07:20:16.94#ibcon#*before return 0, iclass 7, count 2 2006.189.07:20:16.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:16.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:16.94#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.07:20:16.94#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:16.94#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:17.06#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:17.06#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:17.06#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:20:17.06#ibcon#first serial, iclass 7, count 0 2006.189.07:20:17.06#ibcon#enter sib2, iclass 7, count 0 2006.189.07:20:17.06#ibcon#flushed, iclass 7, count 0 2006.189.07:20:17.06#ibcon#about to write, iclass 7, count 0 2006.189.07:20:17.06#ibcon#wrote, iclass 7, count 0 2006.189.07:20:17.06#ibcon#about to read 3, iclass 7, count 0 2006.189.07:20:17.08#ibcon#read 3, iclass 7, count 0 2006.189.07:20:17.08#ibcon#about to read 4, iclass 7, count 0 2006.189.07:20:17.08#ibcon#read 4, iclass 7, count 0 2006.189.07:20:17.08#ibcon#about to read 5, iclass 7, count 0 2006.189.07:20:17.08#ibcon#read 5, iclass 7, count 0 2006.189.07:20:17.08#ibcon#about to read 6, iclass 7, count 0 2006.189.07:20:17.08#ibcon#read 6, iclass 7, count 0 2006.189.07:20:17.08#ibcon#end of sib2, iclass 7, count 0 2006.189.07:20:17.08#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:20:17.08#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:20:17.08#ibcon#[25=USB\r\n] 2006.189.07:20:17.08#ibcon#*before write, iclass 7, count 0 2006.189.07:20:17.08#ibcon#enter sib2, iclass 7, count 0 2006.189.07:20:17.08#ibcon#flushed, iclass 7, count 0 2006.189.07:20:17.08#ibcon#about to write, iclass 7, count 0 2006.189.07:20:17.08#ibcon#wrote, iclass 7, count 0 2006.189.07:20:17.08#ibcon#about to read 3, iclass 7, count 0 2006.189.07:20:17.11#ibcon#read 3, iclass 7, count 0 2006.189.07:20:17.11#ibcon#about to read 4, iclass 7, count 0 2006.189.07:20:17.11#ibcon#read 4, iclass 7, count 0 2006.189.07:20:17.11#ibcon#about to read 5, iclass 7, count 0 2006.189.07:20:17.11#ibcon#read 5, iclass 7, count 0 2006.189.07:20:17.11#ibcon#about to read 6, iclass 7, count 0 2006.189.07:20:17.11#ibcon#read 6, iclass 7, count 0 2006.189.07:20:17.11#ibcon#end of sib2, iclass 7, count 0 2006.189.07:20:17.11#ibcon#*after write, iclass 7, count 0 2006.189.07:20:17.11#ibcon#*before return 0, iclass 7, count 0 2006.189.07:20:17.11#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:17.11#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:17.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:20:17.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:20:17.11$vc4f8/valo=5,652.99 2006.189.07:20:17.11#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.07:20:17.11#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.07:20:17.11#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:17.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:17.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:17.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:17.11#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:20:17.11#ibcon#first serial, iclass 11, count 0 2006.189.07:20:17.11#ibcon#enter sib2, iclass 11, count 0 2006.189.07:20:17.11#ibcon#flushed, iclass 11, count 0 2006.189.07:20:17.11#ibcon#about to write, iclass 11, count 0 2006.189.07:20:17.11#ibcon#wrote, iclass 11, count 0 2006.189.07:20:17.11#ibcon#about to read 3, iclass 11, count 0 2006.189.07:20:17.13#ibcon#read 3, iclass 11, count 0 2006.189.07:20:17.13#ibcon#about to read 4, iclass 11, count 0 2006.189.07:20:17.13#ibcon#read 4, iclass 11, count 0 2006.189.07:20:17.13#ibcon#about to read 5, iclass 11, count 0 2006.189.07:20:17.13#ibcon#read 5, iclass 11, count 0 2006.189.07:20:17.13#ibcon#about to read 6, iclass 11, count 0 2006.189.07:20:17.13#ibcon#read 6, iclass 11, count 0 2006.189.07:20:17.13#ibcon#end of sib2, iclass 11, count 0 2006.189.07:20:17.13#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:20:17.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:20:17.13#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:20:17.13#ibcon#*before write, iclass 11, count 0 2006.189.07:20:17.13#ibcon#enter sib2, iclass 11, count 0 2006.189.07:20:17.13#ibcon#flushed, iclass 11, count 0 2006.189.07:20:17.13#ibcon#about to write, iclass 11, count 0 2006.189.07:20:17.13#ibcon#wrote, iclass 11, count 0 2006.189.07:20:17.13#ibcon#about to read 3, iclass 11, count 0 2006.189.07:20:17.17#ibcon#read 3, iclass 11, count 0 2006.189.07:20:17.17#ibcon#about to read 4, iclass 11, count 0 2006.189.07:20:17.17#ibcon#read 4, iclass 11, count 0 2006.189.07:20:17.17#ibcon#about to read 5, iclass 11, count 0 2006.189.07:20:17.17#ibcon#read 5, iclass 11, count 0 2006.189.07:20:17.17#ibcon#about to read 6, iclass 11, count 0 2006.189.07:20:17.17#ibcon#read 6, iclass 11, count 0 2006.189.07:20:17.17#ibcon#end of sib2, iclass 11, count 0 2006.189.07:20:17.17#ibcon#*after write, iclass 11, count 0 2006.189.07:20:17.17#ibcon#*before return 0, iclass 11, count 0 2006.189.07:20:17.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:17.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:17.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:20:17.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:20:17.17$vc4f8/va=5,7 2006.189.07:20:17.17#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.07:20:17.17#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.07:20:17.17#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:17.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:17.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:17.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:17.23#ibcon#enter wrdev, iclass 13, count 2 2006.189.07:20:17.23#ibcon#first serial, iclass 13, count 2 2006.189.07:20:17.23#ibcon#enter sib2, iclass 13, count 2 2006.189.07:20:17.23#ibcon#flushed, iclass 13, count 2 2006.189.07:20:17.23#ibcon#about to write, iclass 13, count 2 2006.189.07:20:17.23#ibcon#wrote, iclass 13, count 2 2006.189.07:20:17.23#ibcon#about to read 3, iclass 13, count 2 2006.189.07:20:17.25#ibcon#read 3, iclass 13, count 2 2006.189.07:20:17.25#ibcon#about to read 4, iclass 13, count 2 2006.189.07:20:17.25#ibcon#read 4, iclass 13, count 2 2006.189.07:20:17.25#ibcon#about to read 5, iclass 13, count 2 2006.189.07:20:17.25#ibcon#read 5, iclass 13, count 2 2006.189.07:20:17.25#ibcon#about to read 6, iclass 13, count 2 2006.189.07:20:17.25#ibcon#read 6, iclass 13, count 2 2006.189.07:20:17.25#ibcon#end of sib2, iclass 13, count 2 2006.189.07:20:17.25#ibcon#*mode == 0, iclass 13, count 2 2006.189.07:20:17.25#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.07:20:17.25#ibcon#[25=AT05-07\r\n] 2006.189.07:20:17.25#ibcon#*before write, iclass 13, count 2 2006.189.07:20:17.25#ibcon#enter sib2, iclass 13, count 2 2006.189.07:20:17.25#ibcon#flushed, iclass 13, count 2 2006.189.07:20:17.25#ibcon#about to write, iclass 13, count 2 2006.189.07:20:17.25#ibcon#wrote, iclass 13, count 2 2006.189.07:20:17.25#ibcon#about to read 3, iclass 13, count 2 2006.189.07:20:17.28#ibcon#read 3, iclass 13, count 2 2006.189.07:20:17.28#ibcon#about to read 4, iclass 13, count 2 2006.189.07:20:17.28#ibcon#read 4, iclass 13, count 2 2006.189.07:20:17.28#ibcon#about to read 5, iclass 13, count 2 2006.189.07:20:17.28#ibcon#read 5, iclass 13, count 2 2006.189.07:20:17.28#ibcon#about to read 6, iclass 13, count 2 2006.189.07:20:17.28#ibcon#read 6, iclass 13, count 2 2006.189.07:20:17.28#ibcon#end of sib2, iclass 13, count 2 2006.189.07:20:17.28#ibcon#*after write, iclass 13, count 2 2006.189.07:20:17.28#ibcon#*before return 0, iclass 13, count 2 2006.189.07:20:17.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:17.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:17.28#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.07:20:17.28#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:17.28#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:17.40#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:17.40#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:17.40#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:20:17.40#ibcon#first serial, iclass 13, count 0 2006.189.07:20:17.40#ibcon#enter sib2, iclass 13, count 0 2006.189.07:20:17.40#ibcon#flushed, iclass 13, count 0 2006.189.07:20:17.40#ibcon#about to write, iclass 13, count 0 2006.189.07:20:17.40#ibcon#wrote, iclass 13, count 0 2006.189.07:20:17.40#ibcon#about to read 3, iclass 13, count 0 2006.189.07:20:17.42#ibcon#read 3, iclass 13, count 0 2006.189.07:20:17.42#ibcon#about to read 4, iclass 13, count 0 2006.189.07:20:17.42#ibcon#read 4, iclass 13, count 0 2006.189.07:20:17.42#ibcon#about to read 5, iclass 13, count 0 2006.189.07:20:17.42#ibcon#read 5, iclass 13, count 0 2006.189.07:20:17.42#ibcon#about to read 6, iclass 13, count 0 2006.189.07:20:17.42#ibcon#read 6, iclass 13, count 0 2006.189.07:20:17.42#ibcon#end of sib2, iclass 13, count 0 2006.189.07:20:17.42#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:20:17.42#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:20:17.42#ibcon#[25=USB\r\n] 2006.189.07:20:17.42#ibcon#*before write, iclass 13, count 0 2006.189.07:20:17.42#ibcon#enter sib2, iclass 13, count 0 2006.189.07:20:17.42#ibcon#flushed, iclass 13, count 0 2006.189.07:20:17.42#ibcon#about to write, iclass 13, count 0 2006.189.07:20:17.42#ibcon#wrote, iclass 13, count 0 2006.189.07:20:17.42#ibcon#about to read 3, iclass 13, count 0 2006.189.07:20:17.45#ibcon#read 3, iclass 13, count 0 2006.189.07:20:17.45#ibcon#about to read 4, iclass 13, count 0 2006.189.07:20:17.45#ibcon#read 4, iclass 13, count 0 2006.189.07:20:17.45#ibcon#about to read 5, iclass 13, count 0 2006.189.07:20:17.45#ibcon#read 5, iclass 13, count 0 2006.189.07:20:17.45#ibcon#about to read 6, iclass 13, count 0 2006.189.07:20:17.45#ibcon#read 6, iclass 13, count 0 2006.189.07:20:17.45#ibcon#end of sib2, iclass 13, count 0 2006.189.07:20:17.45#ibcon#*after write, iclass 13, count 0 2006.189.07:20:17.45#ibcon#*before return 0, iclass 13, count 0 2006.189.07:20:17.45#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:17.45#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:17.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:20:17.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:20:17.45$vc4f8/valo=6,772.99 2006.189.07:20:17.45#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.07:20:17.45#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.07:20:17.45#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:17.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:17.45#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:17.45#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:17.45#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:20:17.45#ibcon#first serial, iclass 15, count 0 2006.189.07:20:17.45#ibcon#enter sib2, iclass 15, count 0 2006.189.07:20:17.45#ibcon#flushed, iclass 15, count 0 2006.189.07:20:17.45#ibcon#about to write, iclass 15, count 0 2006.189.07:20:17.45#ibcon#wrote, iclass 15, count 0 2006.189.07:20:17.45#ibcon#about to read 3, iclass 15, count 0 2006.189.07:20:17.47#ibcon#read 3, iclass 15, count 0 2006.189.07:20:17.47#ibcon#about to read 4, iclass 15, count 0 2006.189.07:20:17.47#ibcon#read 4, iclass 15, count 0 2006.189.07:20:17.47#ibcon#about to read 5, iclass 15, count 0 2006.189.07:20:17.47#ibcon#read 5, iclass 15, count 0 2006.189.07:20:17.47#ibcon#about to read 6, iclass 15, count 0 2006.189.07:20:17.47#ibcon#read 6, iclass 15, count 0 2006.189.07:20:17.47#ibcon#end of sib2, iclass 15, count 0 2006.189.07:20:17.47#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:20:17.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:20:17.47#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:20:17.47#ibcon#*before write, iclass 15, count 0 2006.189.07:20:17.47#ibcon#enter sib2, iclass 15, count 0 2006.189.07:20:17.47#ibcon#flushed, iclass 15, count 0 2006.189.07:20:17.47#ibcon#about to write, iclass 15, count 0 2006.189.07:20:17.47#ibcon#wrote, iclass 15, count 0 2006.189.07:20:17.47#ibcon#about to read 3, iclass 15, count 0 2006.189.07:20:17.51#ibcon#read 3, iclass 15, count 0 2006.189.07:20:17.51#ibcon#about to read 4, iclass 15, count 0 2006.189.07:20:17.51#ibcon#read 4, iclass 15, count 0 2006.189.07:20:17.51#ibcon#about to read 5, iclass 15, count 0 2006.189.07:20:17.51#ibcon#read 5, iclass 15, count 0 2006.189.07:20:17.51#ibcon#about to read 6, iclass 15, count 0 2006.189.07:20:17.51#ibcon#read 6, iclass 15, count 0 2006.189.07:20:17.51#ibcon#end of sib2, iclass 15, count 0 2006.189.07:20:17.51#ibcon#*after write, iclass 15, count 0 2006.189.07:20:17.51#ibcon#*before return 0, iclass 15, count 0 2006.189.07:20:17.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:17.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:17.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:20:17.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:20:17.51$vc4f8/va=6,6 2006.189.07:20:17.51#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.07:20:17.51#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.07:20:17.51#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:17.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:20:17.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:20:17.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:20:17.57#ibcon#enter wrdev, iclass 17, count 2 2006.189.07:20:17.57#ibcon#first serial, iclass 17, count 2 2006.189.07:20:17.57#ibcon#enter sib2, iclass 17, count 2 2006.189.07:20:17.57#ibcon#flushed, iclass 17, count 2 2006.189.07:20:17.57#ibcon#about to write, iclass 17, count 2 2006.189.07:20:17.57#ibcon#wrote, iclass 17, count 2 2006.189.07:20:17.57#ibcon#about to read 3, iclass 17, count 2 2006.189.07:20:17.59#ibcon#read 3, iclass 17, count 2 2006.189.07:20:17.59#ibcon#about to read 4, iclass 17, count 2 2006.189.07:20:17.59#ibcon#read 4, iclass 17, count 2 2006.189.07:20:17.59#ibcon#about to read 5, iclass 17, count 2 2006.189.07:20:17.59#ibcon#read 5, iclass 17, count 2 2006.189.07:20:17.59#ibcon#about to read 6, iclass 17, count 2 2006.189.07:20:17.59#ibcon#read 6, iclass 17, count 2 2006.189.07:20:17.59#ibcon#end of sib2, iclass 17, count 2 2006.189.07:20:17.59#ibcon#*mode == 0, iclass 17, count 2 2006.189.07:20:17.59#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.07:20:17.59#ibcon#[25=AT06-06\r\n] 2006.189.07:20:17.59#ibcon#*before write, iclass 17, count 2 2006.189.07:20:17.59#ibcon#enter sib2, iclass 17, count 2 2006.189.07:20:17.59#ibcon#flushed, iclass 17, count 2 2006.189.07:20:17.59#ibcon#about to write, iclass 17, count 2 2006.189.07:20:17.59#ibcon#wrote, iclass 17, count 2 2006.189.07:20:17.59#ibcon#about to read 3, iclass 17, count 2 2006.189.07:20:17.62#ibcon#read 3, iclass 17, count 2 2006.189.07:20:17.62#ibcon#about to read 4, iclass 17, count 2 2006.189.07:20:17.62#ibcon#read 4, iclass 17, count 2 2006.189.07:20:17.62#ibcon#about to read 5, iclass 17, count 2 2006.189.07:20:17.62#ibcon#read 5, iclass 17, count 2 2006.189.07:20:17.62#ibcon#about to read 6, iclass 17, count 2 2006.189.07:20:17.62#ibcon#read 6, iclass 17, count 2 2006.189.07:20:17.62#ibcon#end of sib2, iclass 17, count 2 2006.189.07:20:17.62#ibcon#*after write, iclass 17, count 2 2006.189.07:20:17.62#ibcon#*before return 0, iclass 17, count 2 2006.189.07:20:17.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:20:17.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:20:17.62#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.07:20:17.62#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:17.62#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:20:17.74#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:20:17.74#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:20:17.74#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:20:17.74#ibcon#first serial, iclass 17, count 0 2006.189.07:20:17.74#ibcon#enter sib2, iclass 17, count 0 2006.189.07:20:17.74#ibcon#flushed, iclass 17, count 0 2006.189.07:20:17.74#ibcon#about to write, iclass 17, count 0 2006.189.07:20:17.74#ibcon#wrote, iclass 17, count 0 2006.189.07:20:17.74#ibcon#about to read 3, iclass 17, count 0 2006.189.07:20:17.76#ibcon#read 3, iclass 17, count 0 2006.189.07:20:17.76#ibcon#about to read 4, iclass 17, count 0 2006.189.07:20:17.76#ibcon#read 4, iclass 17, count 0 2006.189.07:20:17.76#ibcon#about to read 5, iclass 17, count 0 2006.189.07:20:17.76#ibcon#read 5, iclass 17, count 0 2006.189.07:20:17.76#ibcon#about to read 6, iclass 17, count 0 2006.189.07:20:17.76#ibcon#read 6, iclass 17, count 0 2006.189.07:20:17.76#ibcon#end of sib2, iclass 17, count 0 2006.189.07:20:17.76#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:20:17.76#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:20:17.76#ibcon#[25=USB\r\n] 2006.189.07:20:17.76#ibcon#*before write, iclass 17, count 0 2006.189.07:20:17.76#ibcon#enter sib2, iclass 17, count 0 2006.189.07:20:17.76#ibcon#flushed, iclass 17, count 0 2006.189.07:20:17.76#ibcon#about to write, iclass 17, count 0 2006.189.07:20:17.76#ibcon#wrote, iclass 17, count 0 2006.189.07:20:17.76#ibcon#about to read 3, iclass 17, count 0 2006.189.07:20:17.79#ibcon#read 3, iclass 17, count 0 2006.189.07:20:17.79#ibcon#about to read 4, iclass 17, count 0 2006.189.07:20:17.79#ibcon#read 4, iclass 17, count 0 2006.189.07:20:17.79#ibcon#about to read 5, iclass 17, count 0 2006.189.07:20:17.79#ibcon#read 5, iclass 17, count 0 2006.189.07:20:17.79#ibcon#about to read 6, iclass 17, count 0 2006.189.07:20:17.79#ibcon#read 6, iclass 17, count 0 2006.189.07:20:17.79#ibcon#end of sib2, iclass 17, count 0 2006.189.07:20:17.79#ibcon#*after write, iclass 17, count 0 2006.189.07:20:17.79#ibcon#*before return 0, iclass 17, count 0 2006.189.07:20:17.79#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:20:17.79#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:20:17.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:20:17.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:20:17.79$vc4f8/valo=7,832.99 2006.189.07:20:17.79#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.07:20:17.79#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.07:20:17.79#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:17.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:20:17.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:20:17.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:20:17.79#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:20:17.79#ibcon#first serial, iclass 19, count 0 2006.189.07:20:17.79#ibcon#enter sib2, iclass 19, count 0 2006.189.07:20:17.79#ibcon#flushed, iclass 19, count 0 2006.189.07:20:17.79#ibcon#about to write, iclass 19, count 0 2006.189.07:20:17.79#ibcon#wrote, iclass 19, count 0 2006.189.07:20:17.79#ibcon#about to read 3, iclass 19, count 0 2006.189.07:20:17.81#ibcon#read 3, iclass 19, count 0 2006.189.07:20:17.81#ibcon#about to read 4, iclass 19, count 0 2006.189.07:20:17.81#ibcon#read 4, iclass 19, count 0 2006.189.07:20:17.81#ibcon#about to read 5, iclass 19, count 0 2006.189.07:20:17.81#ibcon#read 5, iclass 19, count 0 2006.189.07:20:17.81#ibcon#about to read 6, iclass 19, count 0 2006.189.07:20:17.81#ibcon#read 6, iclass 19, count 0 2006.189.07:20:17.81#ibcon#end of sib2, iclass 19, count 0 2006.189.07:20:17.81#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:20:17.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:20:17.81#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:20:17.81#ibcon#*before write, iclass 19, count 0 2006.189.07:20:17.81#ibcon#enter sib2, iclass 19, count 0 2006.189.07:20:17.81#ibcon#flushed, iclass 19, count 0 2006.189.07:20:17.81#ibcon#about to write, iclass 19, count 0 2006.189.07:20:17.81#ibcon#wrote, iclass 19, count 0 2006.189.07:20:17.81#ibcon#about to read 3, iclass 19, count 0 2006.189.07:20:17.85#ibcon#read 3, iclass 19, count 0 2006.189.07:20:17.85#ibcon#about to read 4, iclass 19, count 0 2006.189.07:20:17.85#ibcon#read 4, iclass 19, count 0 2006.189.07:20:17.85#ibcon#about to read 5, iclass 19, count 0 2006.189.07:20:17.85#ibcon#read 5, iclass 19, count 0 2006.189.07:20:17.85#ibcon#about to read 6, iclass 19, count 0 2006.189.07:20:17.85#ibcon#read 6, iclass 19, count 0 2006.189.07:20:17.85#ibcon#end of sib2, iclass 19, count 0 2006.189.07:20:17.85#ibcon#*after write, iclass 19, count 0 2006.189.07:20:17.85#ibcon#*before return 0, iclass 19, count 0 2006.189.07:20:17.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:20:17.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:20:17.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:20:17.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:20:17.85$vc4f8/va=7,6 2006.189.07:20:17.85#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.07:20:17.85#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.07:20:17.85#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:17.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:20:17.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:20:17.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:20:17.91#ibcon#enter wrdev, iclass 21, count 2 2006.189.07:20:17.91#ibcon#first serial, iclass 21, count 2 2006.189.07:20:17.91#ibcon#enter sib2, iclass 21, count 2 2006.189.07:20:17.91#ibcon#flushed, iclass 21, count 2 2006.189.07:20:17.91#ibcon#about to write, iclass 21, count 2 2006.189.07:20:17.91#ibcon#wrote, iclass 21, count 2 2006.189.07:20:17.91#ibcon#about to read 3, iclass 21, count 2 2006.189.07:20:17.93#ibcon#read 3, iclass 21, count 2 2006.189.07:20:17.93#ibcon#about to read 4, iclass 21, count 2 2006.189.07:20:17.93#ibcon#read 4, iclass 21, count 2 2006.189.07:20:17.93#ibcon#about to read 5, iclass 21, count 2 2006.189.07:20:17.93#ibcon#read 5, iclass 21, count 2 2006.189.07:20:17.93#ibcon#about to read 6, iclass 21, count 2 2006.189.07:20:17.93#ibcon#read 6, iclass 21, count 2 2006.189.07:20:17.93#ibcon#end of sib2, iclass 21, count 2 2006.189.07:20:17.93#ibcon#*mode == 0, iclass 21, count 2 2006.189.07:20:17.93#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.07:20:17.93#ibcon#[25=AT07-06\r\n] 2006.189.07:20:17.93#ibcon#*before write, iclass 21, count 2 2006.189.07:20:17.93#ibcon#enter sib2, iclass 21, count 2 2006.189.07:20:17.93#ibcon#flushed, iclass 21, count 2 2006.189.07:20:17.93#ibcon#about to write, iclass 21, count 2 2006.189.07:20:17.93#ibcon#wrote, iclass 21, count 2 2006.189.07:20:17.93#ibcon#about to read 3, iclass 21, count 2 2006.189.07:20:17.96#ibcon#read 3, iclass 21, count 2 2006.189.07:20:17.96#ibcon#about to read 4, iclass 21, count 2 2006.189.07:20:17.96#ibcon#read 4, iclass 21, count 2 2006.189.07:20:17.96#ibcon#about to read 5, iclass 21, count 2 2006.189.07:20:17.96#ibcon#read 5, iclass 21, count 2 2006.189.07:20:17.96#ibcon#about to read 6, iclass 21, count 2 2006.189.07:20:17.96#ibcon#read 6, iclass 21, count 2 2006.189.07:20:17.96#ibcon#end of sib2, iclass 21, count 2 2006.189.07:20:17.96#ibcon#*after write, iclass 21, count 2 2006.189.07:20:17.96#ibcon#*before return 0, iclass 21, count 2 2006.189.07:20:17.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:20:17.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:20:17.96#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.07:20:17.96#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:17.96#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:20:18.08#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:20:18.08#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:20:18.08#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:20:18.08#ibcon#first serial, iclass 21, count 0 2006.189.07:20:18.08#ibcon#enter sib2, iclass 21, count 0 2006.189.07:20:18.08#ibcon#flushed, iclass 21, count 0 2006.189.07:20:18.08#ibcon#about to write, iclass 21, count 0 2006.189.07:20:18.08#ibcon#wrote, iclass 21, count 0 2006.189.07:20:18.08#ibcon#about to read 3, iclass 21, count 0 2006.189.07:20:18.10#ibcon#read 3, iclass 21, count 0 2006.189.07:20:18.10#ibcon#about to read 4, iclass 21, count 0 2006.189.07:20:18.10#ibcon#read 4, iclass 21, count 0 2006.189.07:20:18.10#ibcon#about to read 5, iclass 21, count 0 2006.189.07:20:18.10#ibcon#read 5, iclass 21, count 0 2006.189.07:20:18.10#ibcon#about to read 6, iclass 21, count 0 2006.189.07:20:18.10#ibcon#read 6, iclass 21, count 0 2006.189.07:20:18.10#ibcon#end of sib2, iclass 21, count 0 2006.189.07:20:18.10#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:20:18.10#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:20:18.10#ibcon#[25=USB\r\n] 2006.189.07:20:18.10#ibcon#*before write, iclass 21, count 0 2006.189.07:20:18.10#ibcon#enter sib2, iclass 21, count 0 2006.189.07:20:18.10#ibcon#flushed, iclass 21, count 0 2006.189.07:20:18.10#ibcon#about to write, iclass 21, count 0 2006.189.07:20:18.10#ibcon#wrote, iclass 21, count 0 2006.189.07:20:18.10#ibcon#about to read 3, iclass 21, count 0 2006.189.07:20:18.13#ibcon#read 3, iclass 21, count 0 2006.189.07:20:18.13#ibcon#about to read 4, iclass 21, count 0 2006.189.07:20:18.13#ibcon#read 4, iclass 21, count 0 2006.189.07:20:18.13#ibcon#about to read 5, iclass 21, count 0 2006.189.07:20:18.13#ibcon#read 5, iclass 21, count 0 2006.189.07:20:18.13#ibcon#about to read 6, iclass 21, count 0 2006.189.07:20:18.13#ibcon#read 6, iclass 21, count 0 2006.189.07:20:18.13#ibcon#end of sib2, iclass 21, count 0 2006.189.07:20:18.13#ibcon#*after write, iclass 21, count 0 2006.189.07:20:18.13#ibcon#*before return 0, iclass 21, count 0 2006.189.07:20:18.13#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:20:18.13#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:20:18.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:20:18.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:20:18.13$vc4f8/valo=8,852.99 2006.189.07:20:18.13#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.07:20:18.13#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.07:20:18.13#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:18.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:20:18.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:20:18.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:20:18.13#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:20:18.13#ibcon#first serial, iclass 23, count 0 2006.189.07:20:18.13#ibcon#enter sib2, iclass 23, count 0 2006.189.07:20:18.13#ibcon#flushed, iclass 23, count 0 2006.189.07:20:18.13#ibcon#about to write, iclass 23, count 0 2006.189.07:20:18.13#ibcon#wrote, iclass 23, count 0 2006.189.07:20:18.13#ibcon#about to read 3, iclass 23, count 0 2006.189.07:20:18.15#ibcon#read 3, iclass 23, count 0 2006.189.07:20:18.15#ibcon#about to read 4, iclass 23, count 0 2006.189.07:20:18.15#ibcon#read 4, iclass 23, count 0 2006.189.07:20:18.15#ibcon#about to read 5, iclass 23, count 0 2006.189.07:20:18.15#ibcon#read 5, iclass 23, count 0 2006.189.07:20:18.15#ibcon#about to read 6, iclass 23, count 0 2006.189.07:20:18.15#ibcon#read 6, iclass 23, count 0 2006.189.07:20:18.15#ibcon#end of sib2, iclass 23, count 0 2006.189.07:20:18.15#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:20:18.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:20:18.15#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:20:18.15#ibcon#*before write, iclass 23, count 0 2006.189.07:20:18.15#ibcon#enter sib2, iclass 23, count 0 2006.189.07:20:18.15#ibcon#flushed, iclass 23, count 0 2006.189.07:20:18.15#ibcon#about to write, iclass 23, count 0 2006.189.07:20:18.15#ibcon#wrote, iclass 23, count 0 2006.189.07:20:18.15#ibcon#about to read 3, iclass 23, count 0 2006.189.07:20:18.19#ibcon#read 3, iclass 23, count 0 2006.189.07:20:18.19#ibcon#about to read 4, iclass 23, count 0 2006.189.07:20:18.19#ibcon#read 4, iclass 23, count 0 2006.189.07:20:18.19#ibcon#about to read 5, iclass 23, count 0 2006.189.07:20:18.19#ibcon#read 5, iclass 23, count 0 2006.189.07:20:18.19#ibcon#about to read 6, iclass 23, count 0 2006.189.07:20:18.19#ibcon#read 6, iclass 23, count 0 2006.189.07:20:18.19#ibcon#end of sib2, iclass 23, count 0 2006.189.07:20:18.19#ibcon#*after write, iclass 23, count 0 2006.189.07:20:18.19#ibcon#*before return 0, iclass 23, count 0 2006.189.07:20:18.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:20:18.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:20:18.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:20:18.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:20:18.19$vc4f8/va=8,6 2006.189.07:20:18.19#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.07:20:18.19#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.07:20:18.19#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:18.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:20:18.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:20:18.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:20:18.25#ibcon#enter wrdev, iclass 25, count 2 2006.189.07:20:18.25#ibcon#first serial, iclass 25, count 2 2006.189.07:20:18.25#ibcon#enter sib2, iclass 25, count 2 2006.189.07:20:18.25#ibcon#flushed, iclass 25, count 2 2006.189.07:20:18.25#ibcon#about to write, iclass 25, count 2 2006.189.07:20:18.25#ibcon#wrote, iclass 25, count 2 2006.189.07:20:18.25#ibcon#about to read 3, iclass 25, count 2 2006.189.07:20:18.27#ibcon#read 3, iclass 25, count 2 2006.189.07:20:18.27#ibcon#about to read 4, iclass 25, count 2 2006.189.07:20:18.27#ibcon#read 4, iclass 25, count 2 2006.189.07:20:18.27#ibcon#about to read 5, iclass 25, count 2 2006.189.07:20:18.27#ibcon#read 5, iclass 25, count 2 2006.189.07:20:18.27#ibcon#about to read 6, iclass 25, count 2 2006.189.07:20:18.27#ibcon#read 6, iclass 25, count 2 2006.189.07:20:18.27#ibcon#end of sib2, iclass 25, count 2 2006.189.07:20:18.27#ibcon#*mode == 0, iclass 25, count 2 2006.189.07:20:18.27#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.07:20:18.27#ibcon#[25=AT08-06\r\n] 2006.189.07:20:18.27#ibcon#*before write, iclass 25, count 2 2006.189.07:20:18.27#ibcon#enter sib2, iclass 25, count 2 2006.189.07:20:18.27#ibcon#flushed, iclass 25, count 2 2006.189.07:20:18.27#ibcon#about to write, iclass 25, count 2 2006.189.07:20:18.27#ibcon#wrote, iclass 25, count 2 2006.189.07:20:18.27#ibcon#about to read 3, iclass 25, count 2 2006.189.07:20:18.30#ibcon#read 3, iclass 25, count 2 2006.189.07:20:18.30#ibcon#about to read 4, iclass 25, count 2 2006.189.07:20:18.30#ibcon#read 4, iclass 25, count 2 2006.189.07:20:18.30#ibcon#about to read 5, iclass 25, count 2 2006.189.07:20:18.30#ibcon#read 5, iclass 25, count 2 2006.189.07:20:18.30#ibcon#about to read 6, iclass 25, count 2 2006.189.07:20:18.30#ibcon#read 6, iclass 25, count 2 2006.189.07:20:18.30#ibcon#end of sib2, iclass 25, count 2 2006.189.07:20:18.30#ibcon#*after write, iclass 25, count 2 2006.189.07:20:18.30#ibcon#*before return 0, iclass 25, count 2 2006.189.07:20:18.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:20:18.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:20:18.30#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.07:20:18.30#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:18.30#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:20:18.42#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:20:18.42#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:20:18.42#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:20:18.42#ibcon#first serial, iclass 25, count 0 2006.189.07:20:18.42#ibcon#enter sib2, iclass 25, count 0 2006.189.07:20:18.42#ibcon#flushed, iclass 25, count 0 2006.189.07:20:18.42#ibcon#about to write, iclass 25, count 0 2006.189.07:20:18.42#ibcon#wrote, iclass 25, count 0 2006.189.07:20:18.42#ibcon#about to read 3, iclass 25, count 0 2006.189.07:20:18.44#ibcon#read 3, iclass 25, count 0 2006.189.07:20:18.44#ibcon#about to read 4, iclass 25, count 0 2006.189.07:20:18.44#ibcon#read 4, iclass 25, count 0 2006.189.07:20:18.44#ibcon#about to read 5, iclass 25, count 0 2006.189.07:20:18.44#ibcon#read 5, iclass 25, count 0 2006.189.07:20:18.44#ibcon#about to read 6, iclass 25, count 0 2006.189.07:20:18.44#ibcon#read 6, iclass 25, count 0 2006.189.07:20:18.44#ibcon#end of sib2, iclass 25, count 0 2006.189.07:20:18.44#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:20:18.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:20:18.44#ibcon#[25=USB\r\n] 2006.189.07:20:18.44#ibcon#*before write, iclass 25, count 0 2006.189.07:20:18.44#ibcon#enter sib2, iclass 25, count 0 2006.189.07:20:18.44#ibcon#flushed, iclass 25, count 0 2006.189.07:20:18.44#ibcon#about to write, iclass 25, count 0 2006.189.07:20:18.44#ibcon#wrote, iclass 25, count 0 2006.189.07:20:18.44#ibcon#about to read 3, iclass 25, count 0 2006.189.07:20:18.47#ibcon#read 3, iclass 25, count 0 2006.189.07:20:18.47#ibcon#about to read 4, iclass 25, count 0 2006.189.07:20:18.47#ibcon#read 4, iclass 25, count 0 2006.189.07:20:18.47#ibcon#about to read 5, iclass 25, count 0 2006.189.07:20:18.47#ibcon#read 5, iclass 25, count 0 2006.189.07:20:18.47#ibcon#about to read 6, iclass 25, count 0 2006.189.07:20:18.47#ibcon#read 6, iclass 25, count 0 2006.189.07:20:18.47#ibcon#end of sib2, iclass 25, count 0 2006.189.07:20:18.47#ibcon#*after write, iclass 25, count 0 2006.189.07:20:18.47#ibcon#*before return 0, iclass 25, count 0 2006.189.07:20:18.47#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:20:18.47#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:20:18.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:20:18.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:20:18.47$vc4f8/vblo=1,632.99 2006.189.07:20:18.47#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.07:20:18.47#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.07:20:18.47#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:18.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:20:18.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:20:18.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:20:18.47#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:20:18.47#ibcon#first serial, iclass 27, count 0 2006.189.07:20:18.47#ibcon#enter sib2, iclass 27, count 0 2006.189.07:20:18.47#ibcon#flushed, iclass 27, count 0 2006.189.07:20:18.47#ibcon#about to write, iclass 27, count 0 2006.189.07:20:18.47#ibcon#wrote, iclass 27, count 0 2006.189.07:20:18.47#ibcon#about to read 3, iclass 27, count 0 2006.189.07:20:18.49#ibcon#read 3, iclass 27, count 0 2006.189.07:20:18.49#ibcon#about to read 4, iclass 27, count 0 2006.189.07:20:18.49#ibcon#read 4, iclass 27, count 0 2006.189.07:20:18.49#ibcon#about to read 5, iclass 27, count 0 2006.189.07:20:18.49#ibcon#read 5, iclass 27, count 0 2006.189.07:20:18.49#ibcon#about to read 6, iclass 27, count 0 2006.189.07:20:18.49#ibcon#read 6, iclass 27, count 0 2006.189.07:20:18.49#ibcon#end of sib2, iclass 27, count 0 2006.189.07:20:18.49#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:20:18.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:20:18.49#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:20:18.49#ibcon#*before write, iclass 27, count 0 2006.189.07:20:18.49#ibcon#enter sib2, iclass 27, count 0 2006.189.07:20:18.49#ibcon#flushed, iclass 27, count 0 2006.189.07:20:18.49#ibcon#about to write, iclass 27, count 0 2006.189.07:20:18.49#ibcon#wrote, iclass 27, count 0 2006.189.07:20:18.49#ibcon#about to read 3, iclass 27, count 0 2006.189.07:20:18.55#ibcon#read 3, iclass 27, count 0 2006.189.07:20:18.55#ibcon#about to read 4, iclass 27, count 0 2006.189.07:20:18.55#ibcon#read 4, iclass 27, count 0 2006.189.07:20:18.55#ibcon#about to read 5, iclass 27, count 0 2006.189.07:20:18.55#ibcon#read 5, iclass 27, count 0 2006.189.07:20:18.55#ibcon#about to read 6, iclass 27, count 0 2006.189.07:20:18.55#ibcon#read 6, iclass 27, count 0 2006.189.07:20:18.55#ibcon#end of sib2, iclass 27, count 0 2006.189.07:20:18.55#ibcon#*after write, iclass 27, count 0 2006.189.07:20:18.55#ibcon#*before return 0, iclass 27, count 0 2006.189.07:20:18.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:20:18.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:20:18.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:20:18.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:20:18.55$vc4f8/vb=1,4 2006.189.07:20:18.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.07:20:18.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.07:20:18.55#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:18.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:20:18.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:20:18.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:20:18.55#ibcon#enter wrdev, iclass 29, count 2 2006.189.07:20:18.55#ibcon#first serial, iclass 29, count 2 2006.189.07:20:18.55#ibcon#enter sib2, iclass 29, count 2 2006.189.07:20:18.55#ibcon#flushed, iclass 29, count 2 2006.189.07:20:18.55#ibcon#about to write, iclass 29, count 2 2006.189.07:20:18.55#ibcon#wrote, iclass 29, count 2 2006.189.07:20:18.55#ibcon#about to read 3, iclass 29, count 2 2006.189.07:20:18.57#ibcon#read 3, iclass 29, count 2 2006.189.07:20:18.57#ibcon#about to read 4, iclass 29, count 2 2006.189.07:20:18.57#ibcon#read 4, iclass 29, count 2 2006.189.07:20:18.57#ibcon#about to read 5, iclass 29, count 2 2006.189.07:20:18.57#ibcon#read 5, iclass 29, count 2 2006.189.07:20:18.57#ibcon#about to read 6, iclass 29, count 2 2006.189.07:20:18.57#ibcon#read 6, iclass 29, count 2 2006.189.07:20:18.57#ibcon#end of sib2, iclass 29, count 2 2006.189.07:20:18.57#ibcon#*mode == 0, iclass 29, count 2 2006.189.07:20:18.57#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.07:20:18.57#ibcon#[27=AT01-04\r\n] 2006.189.07:20:18.57#ibcon#*before write, iclass 29, count 2 2006.189.07:20:18.57#ibcon#enter sib2, iclass 29, count 2 2006.189.07:20:18.57#ibcon#flushed, iclass 29, count 2 2006.189.07:20:18.57#ibcon#about to write, iclass 29, count 2 2006.189.07:20:18.57#ibcon#wrote, iclass 29, count 2 2006.189.07:20:18.57#ibcon#about to read 3, iclass 29, count 2 2006.189.07:20:18.61#ibcon#read 3, iclass 29, count 2 2006.189.07:20:18.61#ibcon#about to read 4, iclass 29, count 2 2006.189.07:20:18.61#ibcon#read 4, iclass 29, count 2 2006.189.07:20:18.61#ibcon#about to read 5, iclass 29, count 2 2006.189.07:20:18.61#ibcon#read 5, iclass 29, count 2 2006.189.07:20:18.61#ibcon#about to read 6, iclass 29, count 2 2006.189.07:20:18.61#ibcon#read 6, iclass 29, count 2 2006.189.07:20:18.61#ibcon#end of sib2, iclass 29, count 2 2006.189.07:20:18.61#ibcon#*after write, iclass 29, count 2 2006.189.07:20:18.61#ibcon#*before return 0, iclass 29, count 2 2006.189.07:20:18.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:20:18.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:20:18.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.07:20:18.61#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:18.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:20:18.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:20:18.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:20:18.73#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:20:18.73#ibcon#first serial, iclass 29, count 0 2006.189.07:20:18.73#ibcon#enter sib2, iclass 29, count 0 2006.189.07:20:18.73#ibcon#flushed, iclass 29, count 0 2006.189.07:20:18.73#ibcon#about to write, iclass 29, count 0 2006.189.07:20:18.73#ibcon#wrote, iclass 29, count 0 2006.189.07:20:18.73#ibcon#about to read 3, iclass 29, count 0 2006.189.07:20:18.75#ibcon#read 3, iclass 29, count 0 2006.189.07:20:18.75#ibcon#about to read 4, iclass 29, count 0 2006.189.07:20:18.75#ibcon#read 4, iclass 29, count 0 2006.189.07:20:18.75#ibcon#about to read 5, iclass 29, count 0 2006.189.07:20:18.75#ibcon#read 5, iclass 29, count 0 2006.189.07:20:18.75#ibcon#about to read 6, iclass 29, count 0 2006.189.07:20:18.75#ibcon#read 6, iclass 29, count 0 2006.189.07:20:18.75#ibcon#end of sib2, iclass 29, count 0 2006.189.07:20:18.75#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:20:18.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:20:18.75#ibcon#[27=USB\r\n] 2006.189.07:20:18.75#ibcon#*before write, iclass 29, count 0 2006.189.07:20:18.75#ibcon#enter sib2, iclass 29, count 0 2006.189.07:20:18.75#ibcon#flushed, iclass 29, count 0 2006.189.07:20:18.75#ibcon#about to write, iclass 29, count 0 2006.189.07:20:18.75#ibcon#wrote, iclass 29, count 0 2006.189.07:20:18.75#ibcon#about to read 3, iclass 29, count 0 2006.189.07:20:18.78#ibcon#read 3, iclass 29, count 0 2006.189.07:20:18.78#ibcon#about to read 4, iclass 29, count 0 2006.189.07:20:18.78#ibcon#read 4, iclass 29, count 0 2006.189.07:20:18.78#ibcon#about to read 5, iclass 29, count 0 2006.189.07:20:18.78#ibcon#read 5, iclass 29, count 0 2006.189.07:20:18.78#ibcon#about to read 6, iclass 29, count 0 2006.189.07:20:18.78#ibcon#read 6, iclass 29, count 0 2006.189.07:20:18.78#ibcon#end of sib2, iclass 29, count 0 2006.189.07:20:18.78#ibcon#*after write, iclass 29, count 0 2006.189.07:20:18.78#ibcon#*before return 0, iclass 29, count 0 2006.189.07:20:18.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:20:18.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:20:18.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:20:18.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:20:18.78$vc4f8/vblo=2,640.99 2006.189.07:20:18.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.07:20:18.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.07:20:18.78#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:18.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:18.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:18.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:18.78#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:20:18.78#ibcon#first serial, iclass 31, count 0 2006.189.07:20:18.78#ibcon#enter sib2, iclass 31, count 0 2006.189.07:20:18.78#ibcon#flushed, iclass 31, count 0 2006.189.07:20:18.78#ibcon#about to write, iclass 31, count 0 2006.189.07:20:18.78#ibcon#wrote, iclass 31, count 0 2006.189.07:20:18.78#ibcon#about to read 3, iclass 31, count 0 2006.189.07:20:18.80#ibcon#read 3, iclass 31, count 0 2006.189.07:20:18.80#ibcon#about to read 4, iclass 31, count 0 2006.189.07:20:18.80#ibcon#read 4, iclass 31, count 0 2006.189.07:20:18.80#ibcon#about to read 5, iclass 31, count 0 2006.189.07:20:18.80#ibcon#read 5, iclass 31, count 0 2006.189.07:20:18.80#ibcon#about to read 6, iclass 31, count 0 2006.189.07:20:18.80#ibcon#read 6, iclass 31, count 0 2006.189.07:20:18.80#ibcon#end of sib2, iclass 31, count 0 2006.189.07:20:18.80#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:20:18.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:20:18.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:20:18.80#ibcon#*before write, iclass 31, count 0 2006.189.07:20:18.80#ibcon#enter sib2, iclass 31, count 0 2006.189.07:20:18.80#ibcon#flushed, iclass 31, count 0 2006.189.07:20:18.80#ibcon#about to write, iclass 31, count 0 2006.189.07:20:18.80#ibcon#wrote, iclass 31, count 0 2006.189.07:20:18.80#ibcon#about to read 3, iclass 31, count 0 2006.189.07:20:18.84#ibcon#read 3, iclass 31, count 0 2006.189.07:20:18.84#ibcon#about to read 4, iclass 31, count 0 2006.189.07:20:18.84#ibcon#read 4, iclass 31, count 0 2006.189.07:20:18.84#ibcon#about to read 5, iclass 31, count 0 2006.189.07:20:18.84#ibcon#read 5, iclass 31, count 0 2006.189.07:20:18.84#ibcon#about to read 6, iclass 31, count 0 2006.189.07:20:18.84#ibcon#read 6, iclass 31, count 0 2006.189.07:20:18.84#ibcon#end of sib2, iclass 31, count 0 2006.189.07:20:18.84#ibcon#*after write, iclass 31, count 0 2006.189.07:20:18.84#ibcon#*before return 0, iclass 31, count 0 2006.189.07:20:18.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:18.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:20:18.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:20:18.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:20:18.84$vc4f8/vb=2,4 2006.189.07:20:18.84#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.07:20:18.84#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.07:20:18.84#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:18.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:18.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:18.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:18.90#ibcon#enter wrdev, iclass 33, count 2 2006.189.07:20:18.90#ibcon#first serial, iclass 33, count 2 2006.189.07:20:18.90#ibcon#enter sib2, iclass 33, count 2 2006.189.07:20:18.90#ibcon#flushed, iclass 33, count 2 2006.189.07:20:18.90#ibcon#about to write, iclass 33, count 2 2006.189.07:20:18.90#ibcon#wrote, iclass 33, count 2 2006.189.07:20:18.90#ibcon#about to read 3, iclass 33, count 2 2006.189.07:20:18.92#ibcon#read 3, iclass 33, count 2 2006.189.07:20:18.92#ibcon#about to read 4, iclass 33, count 2 2006.189.07:20:18.92#ibcon#read 4, iclass 33, count 2 2006.189.07:20:18.92#ibcon#about to read 5, iclass 33, count 2 2006.189.07:20:18.92#ibcon#read 5, iclass 33, count 2 2006.189.07:20:18.92#ibcon#about to read 6, iclass 33, count 2 2006.189.07:20:18.92#ibcon#read 6, iclass 33, count 2 2006.189.07:20:18.92#ibcon#end of sib2, iclass 33, count 2 2006.189.07:20:18.92#ibcon#*mode == 0, iclass 33, count 2 2006.189.07:20:18.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.07:20:18.92#ibcon#[27=AT02-04\r\n] 2006.189.07:20:18.92#ibcon#*before write, iclass 33, count 2 2006.189.07:20:18.92#ibcon#enter sib2, iclass 33, count 2 2006.189.07:20:18.92#ibcon#flushed, iclass 33, count 2 2006.189.07:20:18.92#ibcon#about to write, iclass 33, count 2 2006.189.07:20:18.92#ibcon#wrote, iclass 33, count 2 2006.189.07:20:18.92#ibcon#about to read 3, iclass 33, count 2 2006.189.07:20:18.95#ibcon#read 3, iclass 33, count 2 2006.189.07:20:18.95#ibcon#about to read 4, iclass 33, count 2 2006.189.07:20:18.95#ibcon#read 4, iclass 33, count 2 2006.189.07:20:18.95#ibcon#about to read 5, iclass 33, count 2 2006.189.07:20:18.95#ibcon#read 5, iclass 33, count 2 2006.189.07:20:18.95#ibcon#about to read 6, iclass 33, count 2 2006.189.07:20:18.95#ibcon#read 6, iclass 33, count 2 2006.189.07:20:18.95#ibcon#end of sib2, iclass 33, count 2 2006.189.07:20:18.95#ibcon#*after write, iclass 33, count 2 2006.189.07:20:18.95#ibcon#*before return 0, iclass 33, count 2 2006.189.07:20:18.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:18.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:20:18.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.07:20:18.95#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:18.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:19.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:19.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:19.07#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:20:19.07#ibcon#first serial, iclass 33, count 0 2006.189.07:20:19.07#ibcon#enter sib2, iclass 33, count 0 2006.189.07:20:19.07#ibcon#flushed, iclass 33, count 0 2006.189.07:20:19.07#ibcon#about to write, iclass 33, count 0 2006.189.07:20:19.07#ibcon#wrote, iclass 33, count 0 2006.189.07:20:19.07#ibcon#about to read 3, iclass 33, count 0 2006.189.07:20:19.09#ibcon#read 3, iclass 33, count 0 2006.189.07:20:19.09#ibcon#about to read 4, iclass 33, count 0 2006.189.07:20:19.09#ibcon#read 4, iclass 33, count 0 2006.189.07:20:19.09#ibcon#about to read 5, iclass 33, count 0 2006.189.07:20:19.09#ibcon#read 5, iclass 33, count 0 2006.189.07:20:19.09#ibcon#about to read 6, iclass 33, count 0 2006.189.07:20:19.09#ibcon#read 6, iclass 33, count 0 2006.189.07:20:19.09#ibcon#end of sib2, iclass 33, count 0 2006.189.07:20:19.09#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:20:19.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:20:19.09#ibcon#[27=USB\r\n] 2006.189.07:20:19.09#ibcon#*before write, iclass 33, count 0 2006.189.07:20:19.09#ibcon#enter sib2, iclass 33, count 0 2006.189.07:20:19.09#ibcon#flushed, iclass 33, count 0 2006.189.07:20:19.09#ibcon#about to write, iclass 33, count 0 2006.189.07:20:19.09#ibcon#wrote, iclass 33, count 0 2006.189.07:20:19.09#ibcon#about to read 3, iclass 33, count 0 2006.189.07:20:19.12#ibcon#read 3, iclass 33, count 0 2006.189.07:20:19.12#ibcon#about to read 4, iclass 33, count 0 2006.189.07:20:19.12#ibcon#read 4, iclass 33, count 0 2006.189.07:20:19.12#ibcon#about to read 5, iclass 33, count 0 2006.189.07:20:19.12#ibcon#read 5, iclass 33, count 0 2006.189.07:20:19.12#ibcon#about to read 6, iclass 33, count 0 2006.189.07:20:19.12#ibcon#read 6, iclass 33, count 0 2006.189.07:20:19.12#ibcon#end of sib2, iclass 33, count 0 2006.189.07:20:19.12#ibcon#*after write, iclass 33, count 0 2006.189.07:20:19.12#ibcon#*before return 0, iclass 33, count 0 2006.189.07:20:19.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:19.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:20:19.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:20:19.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:20:19.12$vc4f8/vblo=3,656.99 2006.189.07:20:19.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.07:20:19.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.07:20:19.12#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:19.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:19.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:19.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:19.12#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:20:19.12#ibcon#first serial, iclass 35, count 0 2006.189.07:20:19.12#ibcon#enter sib2, iclass 35, count 0 2006.189.07:20:19.12#ibcon#flushed, iclass 35, count 0 2006.189.07:20:19.12#ibcon#about to write, iclass 35, count 0 2006.189.07:20:19.12#ibcon#wrote, iclass 35, count 0 2006.189.07:20:19.12#ibcon#about to read 3, iclass 35, count 0 2006.189.07:20:19.14#ibcon#read 3, iclass 35, count 0 2006.189.07:20:19.14#ibcon#about to read 4, iclass 35, count 0 2006.189.07:20:19.14#ibcon#read 4, iclass 35, count 0 2006.189.07:20:19.14#ibcon#about to read 5, iclass 35, count 0 2006.189.07:20:19.14#ibcon#read 5, iclass 35, count 0 2006.189.07:20:19.14#ibcon#about to read 6, iclass 35, count 0 2006.189.07:20:19.14#ibcon#read 6, iclass 35, count 0 2006.189.07:20:19.14#ibcon#end of sib2, iclass 35, count 0 2006.189.07:20:19.14#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:20:19.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:20:19.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:20:19.14#ibcon#*before write, iclass 35, count 0 2006.189.07:20:19.14#ibcon#enter sib2, iclass 35, count 0 2006.189.07:20:19.14#ibcon#flushed, iclass 35, count 0 2006.189.07:20:19.14#ibcon#about to write, iclass 35, count 0 2006.189.07:20:19.14#ibcon#wrote, iclass 35, count 0 2006.189.07:20:19.14#ibcon#about to read 3, iclass 35, count 0 2006.189.07:20:19.18#ibcon#read 3, iclass 35, count 0 2006.189.07:20:19.18#ibcon#about to read 4, iclass 35, count 0 2006.189.07:20:19.18#ibcon#read 4, iclass 35, count 0 2006.189.07:20:19.18#ibcon#about to read 5, iclass 35, count 0 2006.189.07:20:19.18#ibcon#read 5, iclass 35, count 0 2006.189.07:20:19.18#ibcon#about to read 6, iclass 35, count 0 2006.189.07:20:19.18#ibcon#read 6, iclass 35, count 0 2006.189.07:20:19.18#ibcon#end of sib2, iclass 35, count 0 2006.189.07:20:19.18#ibcon#*after write, iclass 35, count 0 2006.189.07:20:19.18#ibcon#*before return 0, iclass 35, count 0 2006.189.07:20:19.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:19.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:20:19.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:20:19.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:20:19.18$vc4f8/vb=3,4 2006.189.07:20:19.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.07:20:19.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.07:20:19.18#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:19.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:19.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:19.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:19.24#ibcon#enter wrdev, iclass 37, count 2 2006.189.07:20:19.24#ibcon#first serial, iclass 37, count 2 2006.189.07:20:19.24#ibcon#enter sib2, iclass 37, count 2 2006.189.07:20:19.24#ibcon#flushed, iclass 37, count 2 2006.189.07:20:19.24#ibcon#about to write, iclass 37, count 2 2006.189.07:20:19.24#ibcon#wrote, iclass 37, count 2 2006.189.07:20:19.24#ibcon#about to read 3, iclass 37, count 2 2006.189.07:20:19.26#ibcon#read 3, iclass 37, count 2 2006.189.07:20:19.26#ibcon#about to read 4, iclass 37, count 2 2006.189.07:20:19.26#ibcon#read 4, iclass 37, count 2 2006.189.07:20:19.26#ibcon#about to read 5, iclass 37, count 2 2006.189.07:20:19.26#ibcon#read 5, iclass 37, count 2 2006.189.07:20:19.26#ibcon#about to read 6, iclass 37, count 2 2006.189.07:20:19.26#ibcon#read 6, iclass 37, count 2 2006.189.07:20:19.26#ibcon#end of sib2, iclass 37, count 2 2006.189.07:20:19.26#ibcon#*mode == 0, iclass 37, count 2 2006.189.07:20:19.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.07:20:19.26#ibcon#[27=AT03-04\r\n] 2006.189.07:20:19.26#ibcon#*before write, iclass 37, count 2 2006.189.07:20:19.26#ibcon#enter sib2, iclass 37, count 2 2006.189.07:20:19.26#ibcon#flushed, iclass 37, count 2 2006.189.07:20:19.26#ibcon#about to write, iclass 37, count 2 2006.189.07:20:19.26#ibcon#wrote, iclass 37, count 2 2006.189.07:20:19.26#ibcon#about to read 3, iclass 37, count 2 2006.189.07:20:19.29#ibcon#read 3, iclass 37, count 2 2006.189.07:20:19.29#ibcon#about to read 4, iclass 37, count 2 2006.189.07:20:19.29#ibcon#read 4, iclass 37, count 2 2006.189.07:20:19.29#ibcon#about to read 5, iclass 37, count 2 2006.189.07:20:19.29#ibcon#read 5, iclass 37, count 2 2006.189.07:20:19.29#ibcon#about to read 6, iclass 37, count 2 2006.189.07:20:19.29#ibcon#read 6, iclass 37, count 2 2006.189.07:20:19.29#ibcon#end of sib2, iclass 37, count 2 2006.189.07:20:19.29#ibcon#*after write, iclass 37, count 2 2006.189.07:20:19.29#ibcon#*before return 0, iclass 37, count 2 2006.189.07:20:19.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:19.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:20:19.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.07:20:19.29#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:19.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:19.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:19.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:19.41#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:20:19.41#ibcon#first serial, iclass 37, count 0 2006.189.07:20:19.41#ibcon#enter sib2, iclass 37, count 0 2006.189.07:20:19.41#ibcon#flushed, iclass 37, count 0 2006.189.07:20:19.41#ibcon#about to write, iclass 37, count 0 2006.189.07:20:19.41#ibcon#wrote, iclass 37, count 0 2006.189.07:20:19.41#ibcon#about to read 3, iclass 37, count 0 2006.189.07:20:19.43#ibcon#read 3, iclass 37, count 0 2006.189.07:20:19.43#ibcon#about to read 4, iclass 37, count 0 2006.189.07:20:19.43#ibcon#read 4, iclass 37, count 0 2006.189.07:20:19.43#ibcon#about to read 5, iclass 37, count 0 2006.189.07:20:19.43#ibcon#read 5, iclass 37, count 0 2006.189.07:20:19.43#ibcon#about to read 6, iclass 37, count 0 2006.189.07:20:19.43#ibcon#read 6, iclass 37, count 0 2006.189.07:20:19.43#ibcon#end of sib2, iclass 37, count 0 2006.189.07:20:19.43#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:20:19.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:20:19.43#ibcon#[27=USB\r\n] 2006.189.07:20:19.43#ibcon#*before write, iclass 37, count 0 2006.189.07:20:19.43#ibcon#enter sib2, iclass 37, count 0 2006.189.07:20:19.43#ibcon#flushed, iclass 37, count 0 2006.189.07:20:19.43#ibcon#about to write, iclass 37, count 0 2006.189.07:20:19.43#ibcon#wrote, iclass 37, count 0 2006.189.07:20:19.43#ibcon#about to read 3, iclass 37, count 0 2006.189.07:20:19.46#ibcon#read 3, iclass 37, count 0 2006.189.07:20:19.46#ibcon#about to read 4, iclass 37, count 0 2006.189.07:20:19.46#ibcon#read 4, iclass 37, count 0 2006.189.07:20:19.46#ibcon#about to read 5, iclass 37, count 0 2006.189.07:20:19.46#ibcon#read 5, iclass 37, count 0 2006.189.07:20:19.46#ibcon#about to read 6, iclass 37, count 0 2006.189.07:20:19.46#ibcon#read 6, iclass 37, count 0 2006.189.07:20:19.46#ibcon#end of sib2, iclass 37, count 0 2006.189.07:20:19.46#ibcon#*after write, iclass 37, count 0 2006.189.07:20:19.46#ibcon#*before return 0, iclass 37, count 0 2006.189.07:20:19.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:19.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:20:19.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:20:19.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:20:19.46$vc4f8/vblo=4,712.99 2006.189.07:20:19.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.07:20:19.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.07:20:19.46#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:19.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:19.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:19.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:19.46#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:20:19.46#ibcon#first serial, iclass 39, count 0 2006.189.07:20:19.46#ibcon#enter sib2, iclass 39, count 0 2006.189.07:20:19.46#ibcon#flushed, iclass 39, count 0 2006.189.07:20:19.46#ibcon#about to write, iclass 39, count 0 2006.189.07:20:19.46#ibcon#wrote, iclass 39, count 0 2006.189.07:20:19.46#ibcon#about to read 3, iclass 39, count 0 2006.189.07:20:19.48#ibcon#read 3, iclass 39, count 0 2006.189.07:20:19.48#ibcon#about to read 4, iclass 39, count 0 2006.189.07:20:19.48#ibcon#read 4, iclass 39, count 0 2006.189.07:20:19.48#ibcon#about to read 5, iclass 39, count 0 2006.189.07:20:19.48#ibcon#read 5, iclass 39, count 0 2006.189.07:20:19.48#ibcon#about to read 6, iclass 39, count 0 2006.189.07:20:19.48#ibcon#read 6, iclass 39, count 0 2006.189.07:20:19.48#ibcon#end of sib2, iclass 39, count 0 2006.189.07:20:19.48#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:20:19.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:20:19.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:20:19.48#ibcon#*before write, iclass 39, count 0 2006.189.07:20:19.48#ibcon#enter sib2, iclass 39, count 0 2006.189.07:20:19.48#ibcon#flushed, iclass 39, count 0 2006.189.07:20:19.48#ibcon#about to write, iclass 39, count 0 2006.189.07:20:19.48#ibcon#wrote, iclass 39, count 0 2006.189.07:20:19.48#ibcon#about to read 3, iclass 39, count 0 2006.189.07:20:19.52#ibcon#read 3, iclass 39, count 0 2006.189.07:20:19.52#ibcon#about to read 4, iclass 39, count 0 2006.189.07:20:19.52#ibcon#read 4, iclass 39, count 0 2006.189.07:20:19.52#ibcon#about to read 5, iclass 39, count 0 2006.189.07:20:19.52#ibcon#read 5, iclass 39, count 0 2006.189.07:20:19.52#ibcon#about to read 6, iclass 39, count 0 2006.189.07:20:19.52#ibcon#read 6, iclass 39, count 0 2006.189.07:20:19.52#ibcon#end of sib2, iclass 39, count 0 2006.189.07:20:19.52#ibcon#*after write, iclass 39, count 0 2006.189.07:20:19.52#ibcon#*before return 0, iclass 39, count 0 2006.189.07:20:19.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:19.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:20:19.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:20:19.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:20:19.52$vc4f8/vb=4,4 2006.189.07:20:19.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.07:20:19.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.07:20:19.52#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:19.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:19.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:19.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:19.58#ibcon#enter wrdev, iclass 3, count 2 2006.189.07:20:19.58#ibcon#first serial, iclass 3, count 2 2006.189.07:20:19.58#ibcon#enter sib2, iclass 3, count 2 2006.189.07:20:19.58#ibcon#flushed, iclass 3, count 2 2006.189.07:20:19.58#ibcon#about to write, iclass 3, count 2 2006.189.07:20:19.58#ibcon#wrote, iclass 3, count 2 2006.189.07:20:19.58#ibcon#about to read 3, iclass 3, count 2 2006.189.07:20:19.60#ibcon#read 3, iclass 3, count 2 2006.189.07:20:19.60#ibcon#about to read 4, iclass 3, count 2 2006.189.07:20:19.60#ibcon#read 4, iclass 3, count 2 2006.189.07:20:19.60#ibcon#about to read 5, iclass 3, count 2 2006.189.07:20:19.60#ibcon#read 5, iclass 3, count 2 2006.189.07:20:19.60#ibcon#about to read 6, iclass 3, count 2 2006.189.07:20:19.60#ibcon#read 6, iclass 3, count 2 2006.189.07:20:19.60#ibcon#end of sib2, iclass 3, count 2 2006.189.07:20:19.60#ibcon#*mode == 0, iclass 3, count 2 2006.189.07:20:19.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.07:20:19.60#ibcon#[27=AT04-04\r\n] 2006.189.07:20:19.60#ibcon#*before write, iclass 3, count 2 2006.189.07:20:19.60#ibcon#enter sib2, iclass 3, count 2 2006.189.07:20:19.60#ibcon#flushed, iclass 3, count 2 2006.189.07:20:19.60#ibcon#about to write, iclass 3, count 2 2006.189.07:20:19.60#ibcon#wrote, iclass 3, count 2 2006.189.07:20:19.60#ibcon#about to read 3, iclass 3, count 2 2006.189.07:20:19.63#ibcon#read 3, iclass 3, count 2 2006.189.07:20:19.63#ibcon#about to read 4, iclass 3, count 2 2006.189.07:20:19.63#ibcon#read 4, iclass 3, count 2 2006.189.07:20:19.63#ibcon#about to read 5, iclass 3, count 2 2006.189.07:20:19.63#ibcon#read 5, iclass 3, count 2 2006.189.07:20:19.63#ibcon#about to read 6, iclass 3, count 2 2006.189.07:20:19.63#ibcon#read 6, iclass 3, count 2 2006.189.07:20:19.63#ibcon#end of sib2, iclass 3, count 2 2006.189.07:20:19.63#ibcon#*after write, iclass 3, count 2 2006.189.07:20:19.63#ibcon#*before return 0, iclass 3, count 2 2006.189.07:20:19.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:19.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:20:19.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.07:20:19.63#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:19.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:19.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:19.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:19.75#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:20:19.75#ibcon#first serial, iclass 3, count 0 2006.189.07:20:19.75#ibcon#enter sib2, iclass 3, count 0 2006.189.07:20:19.75#ibcon#flushed, iclass 3, count 0 2006.189.07:20:19.75#ibcon#about to write, iclass 3, count 0 2006.189.07:20:19.75#ibcon#wrote, iclass 3, count 0 2006.189.07:20:19.75#ibcon#about to read 3, iclass 3, count 0 2006.189.07:20:19.77#ibcon#read 3, iclass 3, count 0 2006.189.07:20:19.77#ibcon#about to read 4, iclass 3, count 0 2006.189.07:20:19.77#ibcon#read 4, iclass 3, count 0 2006.189.07:20:19.77#ibcon#about to read 5, iclass 3, count 0 2006.189.07:20:19.77#ibcon#read 5, iclass 3, count 0 2006.189.07:20:19.77#ibcon#about to read 6, iclass 3, count 0 2006.189.07:20:19.77#ibcon#read 6, iclass 3, count 0 2006.189.07:20:19.77#ibcon#end of sib2, iclass 3, count 0 2006.189.07:20:19.77#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:20:19.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:20:19.77#ibcon#[27=USB\r\n] 2006.189.07:20:19.77#ibcon#*before write, iclass 3, count 0 2006.189.07:20:19.77#ibcon#enter sib2, iclass 3, count 0 2006.189.07:20:19.77#ibcon#flushed, iclass 3, count 0 2006.189.07:20:19.77#ibcon#about to write, iclass 3, count 0 2006.189.07:20:19.77#ibcon#wrote, iclass 3, count 0 2006.189.07:20:19.77#ibcon#about to read 3, iclass 3, count 0 2006.189.07:20:19.80#ibcon#read 3, iclass 3, count 0 2006.189.07:20:19.80#ibcon#about to read 4, iclass 3, count 0 2006.189.07:20:19.80#ibcon#read 4, iclass 3, count 0 2006.189.07:20:19.80#ibcon#about to read 5, iclass 3, count 0 2006.189.07:20:19.80#ibcon#read 5, iclass 3, count 0 2006.189.07:20:19.80#ibcon#about to read 6, iclass 3, count 0 2006.189.07:20:19.80#ibcon#read 6, iclass 3, count 0 2006.189.07:20:19.80#ibcon#end of sib2, iclass 3, count 0 2006.189.07:20:19.80#ibcon#*after write, iclass 3, count 0 2006.189.07:20:19.80#ibcon#*before return 0, iclass 3, count 0 2006.189.07:20:19.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:19.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:20:19.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:20:19.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:20:19.80$vc4f8/vblo=5,744.99 2006.189.07:20:19.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.07:20:19.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.07:20:19.80#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:19.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:19.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:19.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:19.80#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:20:19.80#ibcon#first serial, iclass 5, count 0 2006.189.07:20:19.80#ibcon#enter sib2, iclass 5, count 0 2006.189.07:20:19.80#ibcon#flushed, iclass 5, count 0 2006.189.07:20:19.80#ibcon#about to write, iclass 5, count 0 2006.189.07:20:19.80#ibcon#wrote, iclass 5, count 0 2006.189.07:20:19.80#ibcon#about to read 3, iclass 5, count 0 2006.189.07:20:19.82#ibcon#read 3, iclass 5, count 0 2006.189.07:20:19.82#ibcon#about to read 4, iclass 5, count 0 2006.189.07:20:19.82#ibcon#read 4, iclass 5, count 0 2006.189.07:20:19.82#ibcon#about to read 5, iclass 5, count 0 2006.189.07:20:19.82#ibcon#read 5, iclass 5, count 0 2006.189.07:20:19.82#ibcon#about to read 6, iclass 5, count 0 2006.189.07:20:19.82#ibcon#read 6, iclass 5, count 0 2006.189.07:20:19.82#ibcon#end of sib2, iclass 5, count 0 2006.189.07:20:19.82#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:20:19.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:20:19.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:20:19.82#ibcon#*before write, iclass 5, count 0 2006.189.07:20:19.82#ibcon#enter sib2, iclass 5, count 0 2006.189.07:20:19.82#ibcon#flushed, iclass 5, count 0 2006.189.07:20:19.82#ibcon#about to write, iclass 5, count 0 2006.189.07:20:19.82#ibcon#wrote, iclass 5, count 0 2006.189.07:20:19.82#ibcon#about to read 3, iclass 5, count 0 2006.189.07:20:19.86#ibcon#read 3, iclass 5, count 0 2006.189.07:20:19.86#ibcon#about to read 4, iclass 5, count 0 2006.189.07:20:19.86#ibcon#read 4, iclass 5, count 0 2006.189.07:20:19.86#ibcon#about to read 5, iclass 5, count 0 2006.189.07:20:19.86#ibcon#read 5, iclass 5, count 0 2006.189.07:20:19.86#ibcon#about to read 6, iclass 5, count 0 2006.189.07:20:19.86#ibcon#read 6, iclass 5, count 0 2006.189.07:20:19.86#ibcon#end of sib2, iclass 5, count 0 2006.189.07:20:19.86#ibcon#*after write, iclass 5, count 0 2006.189.07:20:19.86#ibcon#*before return 0, iclass 5, count 0 2006.189.07:20:19.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:19.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:20:19.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:20:19.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:20:19.86$vc4f8/vb=5,4 2006.189.07:20:19.86#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.07:20:19.86#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.07:20:19.86#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:19.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:19.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:19.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:19.92#ibcon#enter wrdev, iclass 7, count 2 2006.189.07:20:19.92#ibcon#first serial, iclass 7, count 2 2006.189.07:20:19.92#ibcon#enter sib2, iclass 7, count 2 2006.189.07:20:19.92#ibcon#flushed, iclass 7, count 2 2006.189.07:20:19.92#ibcon#about to write, iclass 7, count 2 2006.189.07:20:19.92#ibcon#wrote, iclass 7, count 2 2006.189.07:20:19.92#ibcon#about to read 3, iclass 7, count 2 2006.189.07:20:19.94#ibcon#read 3, iclass 7, count 2 2006.189.07:20:19.94#ibcon#about to read 4, iclass 7, count 2 2006.189.07:20:19.94#ibcon#read 4, iclass 7, count 2 2006.189.07:20:19.94#ibcon#about to read 5, iclass 7, count 2 2006.189.07:20:19.94#ibcon#read 5, iclass 7, count 2 2006.189.07:20:19.94#ibcon#about to read 6, iclass 7, count 2 2006.189.07:20:19.94#ibcon#read 6, iclass 7, count 2 2006.189.07:20:19.94#ibcon#end of sib2, iclass 7, count 2 2006.189.07:20:19.94#ibcon#*mode == 0, iclass 7, count 2 2006.189.07:20:19.94#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.07:20:19.94#ibcon#[27=AT05-04\r\n] 2006.189.07:20:19.94#ibcon#*before write, iclass 7, count 2 2006.189.07:20:19.94#ibcon#enter sib2, iclass 7, count 2 2006.189.07:20:19.94#ibcon#flushed, iclass 7, count 2 2006.189.07:20:19.94#ibcon#about to write, iclass 7, count 2 2006.189.07:20:19.94#ibcon#wrote, iclass 7, count 2 2006.189.07:20:19.94#ibcon#about to read 3, iclass 7, count 2 2006.189.07:20:19.97#ibcon#read 3, iclass 7, count 2 2006.189.07:20:19.97#ibcon#about to read 4, iclass 7, count 2 2006.189.07:20:19.97#ibcon#read 4, iclass 7, count 2 2006.189.07:20:19.97#ibcon#about to read 5, iclass 7, count 2 2006.189.07:20:19.97#ibcon#read 5, iclass 7, count 2 2006.189.07:20:19.97#ibcon#about to read 6, iclass 7, count 2 2006.189.07:20:19.97#ibcon#read 6, iclass 7, count 2 2006.189.07:20:19.97#ibcon#end of sib2, iclass 7, count 2 2006.189.07:20:19.97#ibcon#*after write, iclass 7, count 2 2006.189.07:20:19.97#ibcon#*before return 0, iclass 7, count 2 2006.189.07:20:19.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:19.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:20:19.97#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.07:20:19.97#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:19.97#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:20.09#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:20.09#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:20.09#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:20:20.09#ibcon#first serial, iclass 7, count 0 2006.189.07:20:20.09#ibcon#enter sib2, iclass 7, count 0 2006.189.07:20:20.09#ibcon#flushed, iclass 7, count 0 2006.189.07:20:20.09#ibcon#about to write, iclass 7, count 0 2006.189.07:20:20.09#ibcon#wrote, iclass 7, count 0 2006.189.07:20:20.09#ibcon#about to read 3, iclass 7, count 0 2006.189.07:20:20.11#ibcon#read 3, iclass 7, count 0 2006.189.07:20:20.11#ibcon#about to read 4, iclass 7, count 0 2006.189.07:20:20.11#ibcon#read 4, iclass 7, count 0 2006.189.07:20:20.11#ibcon#about to read 5, iclass 7, count 0 2006.189.07:20:20.11#ibcon#read 5, iclass 7, count 0 2006.189.07:20:20.11#ibcon#about to read 6, iclass 7, count 0 2006.189.07:20:20.11#ibcon#read 6, iclass 7, count 0 2006.189.07:20:20.11#ibcon#end of sib2, iclass 7, count 0 2006.189.07:20:20.11#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:20:20.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:20:20.11#ibcon#[27=USB\r\n] 2006.189.07:20:20.11#ibcon#*before write, iclass 7, count 0 2006.189.07:20:20.11#ibcon#enter sib2, iclass 7, count 0 2006.189.07:20:20.11#ibcon#flushed, iclass 7, count 0 2006.189.07:20:20.11#ibcon#about to write, iclass 7, count 0 2006.189.07:20:20.11#ibcon#wrote, iclass 7, count 0 2006.189.07:20:20.11#ibcon#about to read 3, iclass 7, count 0 2006.189.07:20:20.14#ibcon#read 3, iclass 7, count 0 2006.189.07:20:20.14#ibcon#about to read 4, iclass 7, count 0 2006.189.07:20:20.14#ibcon#read 4, iclass 7, count 0 2006.189.07:20:20.14#ibcon#about to read 5, iclass 7, count 0 2006.189.07:20:20.14#ibcon#read 5, iclass 7, count 0 2006.189.07:20:20.14#ibcon#about to read 6, iclass 7, count 0 2006.189.07:20:20.14#ibcon#read 6, iclass 7, count 0 2006.189.07:20:20.14#ibcon#end of sib2, iclass 7, count 0 2006.189.07:20:20.14#ibcon#*after write, iclass 7, count 0 2006.189.07:20:20.14#ibcon#*before return 0, iclass 7, count 0 2006.189.07:20:20.14#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:20.14#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:20:20.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:20:20.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:20:20.14$vc4f8/vblo=6,752.99 2006.189.07:20:20.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.07:20:20.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.07:20:20.14#ibcon#ireg 17 cls_cnt 0 2006.189.07:20:20.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:20.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:20.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:20.14#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:20:20.14#ibcon#first serial, iclass 11, count 0 2006.189.07:20:20.14#ibcon#enter sib2, iclass 11, count 0 2006.189.07:20:20.14#ibcon#flushed, iclass 11, count 0 2006.189.07:20:20.14#ibcon#about to write, iclass 11, count 0 2006.189.07:20:20.14#ibcon#wrote, iclass 11, count 0 2006.189.07:20:20.14#ibcon#about to read 3, iclass 11, count 0 2006.189.07:20:20.16#ibcon#read 3, iclass 11, count 0 2006.189.07:20:20.16#ibcon#about to read 4, iclass 11, count 0 2006.189.07:20:20.16#ibcon#read 4, iclass 11, count 0 2006.189.07:20:20.16#ibcon#about to read 5, iclass 11, count 0 2006.189.07:20:20.16#ibcon#read 5, iclass 11, count 0 2006.189.07:20:20.16#ibcon#about to read 6, iclass 11, count 0 2006.189.07:20:20.16#ibcon#read 6, iclass 11, count 0 2006.189.07:20:20.16#ibcon#end of sib2, iclass 11, count 0 2006.189.07:20:20.16#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:20:20.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:20:20.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:20:20.16#ibcon#*before write, iclass 11, count 0 2006.189.07:20:20.16#ibcon#enter sib2, iclass 11, count 0 2006.189.07:20:20.16#ibcon#flushed, iclass 11, count 0 2006.189.07:20:20.16#ibcon#about to write, iclass 11, count 0 2006.189.07:20:20.16#ibcon#wrote, iclass 11, count 0 2006.189.07:20:20.16#ibcon#about to read 3, iclass 11, count 0 2006.189.07:20:20.20#ibcon#read 3, iclass 11, count 0 2006.189.07:20:20.20#ibcon#about to read 4, iclass 11, count 0 2006.189.07:20:20.20#ibcon#read 4, iclass 11, count 0 2006.189.07:20:20.20#ibcon#about to read 5, iclass 11, count 0 2006.189.07:20:20.20#ibcon#read 5, iclass 11, count 0 2006.189.07:20:20.20#ibcon#about to read 6, iclass 11, count 0 2006.189.07:20:20.20#ibcon#read 6, iclass 11, count 0 2006.189.07:20:20.20#ibcon#end of sib2, iclass 11, count 0 2006.189.07:20:20.20#ibcon#*after write, iclass 11, count 0 2006.189.07:20:20.20#ibcon#*before return 0, iclass 11, count 0 2006.189.07:20:20.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:20.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:20:20.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:20:20.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:20:20.20$vc4f8/vb=6,4 2006.189.07:20:20.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.07:20:20.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.07:20:20.20#ibcon#ireg 11 cls_cnt 2 2006.189.07:20:20.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:20.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:20.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:20.26#ibcon#enter wrdev, iclass 13, count 2 2006.189.07:20:20.26#ibcon#first serial, iclass 13, count 2 2006.189.07:20:20.26#ibcon#enter sib2, iclass 13, count 2 2006.189.07:20:20.26#ibcon#flushed, iclass 13, count 2 2006.189.07:20:20.26#ibcon#about to write, iclass 13, count 2 2006.189.07:20:20.26#ibcon#wrote, iclass 13, count 2 2006.189.07:20:20.26#ibcon#about to read 3, iclass 13, count 2 2006.189.07:20:20.28#ibcon#read 3, iclass 13, count 2 2006.189.07:20:20.28#ibcon#about to read 4, iclass 13, count 2 2006.189.07:20:20.28#ibcon#read 4, iclass 13, count 2 2006.189.07:20:20.28#ibcon#about to read 5, iclass 13, count 2 2006.189.07:20:20.28#ibcon#read 5, iclass 13, count 2 2006.189.07:20:20.28#ibcon#about to read 6, iclass 13, count 2 2006.189.07:20:20.28#ibcon#read 6, iclass 13, count 2 2006.189.07:20:20.28#ibcon#end of sib2, iclass 13, count 2 2006.189.07:20:20.28#ibcon#*mode == 0, iclass 13, count 2 2006.189.07:20:20.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.07:20:20.28#ibcon#[27=AT06-04\r\n] 2006.189.07:20:20.28#ibcon#*before write, iclass 13, count 2 2006.189.07:20:20.28#ibcon#enter sib2, iclass 13, count 2 2006.189.07:20:20.28#ibcon#flushed, iclass 13, count 2 2006.189.07:20:20.28#ibcon#about to write, iclass 13, count 2 2006.189.07:20:20.28#ibcon#wrote, iclass 13, count 2 2006.189.07:20:20.28#ibcon#about to read 3, iclass 13, count 2 2006.189.07:20:20.31#ibcon#read 3, iclass 13, count 2 2006.189.07:20:20.31#ibcon#about to read 4, iclass 13, count 2 2006.189.07:20:20.31#ibcon#read 4, iclass 13, count 2 2006.189.07:20:20.31#ibcon#about to read 5, iclass 13, count 2 2006.189.07:20:20.31#ibcon#read 5, iclass 13, count 2 2006.189.07:20:20.31#ibcon#about to read 6, iclass 13, count 2 2006.189.07:20:20.31#ibcon#read 6, iclass 13, count 2 2006.189.07:20:20.31#ibcon#end of sib2, iclass 13, count 2 2006.189.07:20:20.31#ibcon#*after write, iclass 13, count 2 2006.189.07:20:20.31#ibcon#*before return 0, iclass 13, count 2 2006.189.07:20:20.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:20.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:20:20.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.07:20:20.31#ibcon#ireg 7 cls_cnt 0 2006.189.07:20:20.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:20.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:20.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:20.43#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:20:20.43#ibcon#first serial, iclass 13, count 0 2006.189.07:20:20.43#ibcon#enter sib2, iclass 13, count 0 2006.189.07:20:20.43#ibcon#flushed, iclass 13, count 0 2006.189.07:20:20.43#ibcon#about to write, iclass 13, count 0 2006.189.07:20:20.43#ibcon#wrote, iclass 13, count 0 2006.189.07:20:20.43#ibcon#about to read 3, iclass 13, count 0 2006.189.07:20:20.45#ibcon#read 3, iclass 13, count 0 2006.189.07:20:20.45#ibcon#about to read 4, iclass 13, count 0 2006.189.07:20:20.45#ibcon#read 4, iclass 13, count 0 2006.189.07:20:20.45#ibcon#about to read 5, iclass 13, count 0 2006.189.07:20:20.45#ibcon#read 5, iclass 13, count 0 2006.189.07:20:20.45#ibcon#about to read 6, iclass 13, count 0 2006.189.07:20:20.45#ibcon#read 6, iclass 13, count 0 2006.189.07:20:20.45#ibcon#end of sib2, iclass 13, count 0 2006.189.07:20:20.45#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:20:20.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:20:20.45#ibcon#[27=USB\r\n] 2006.189.07:20:20.45#ibcon#*before write, iclass 13, count 0 2006.189.07:20:20.45#ibcon#enter sib2, iclass 13, count 0 2006.189.07:20:20.45#ibcon#flushed, iclass 13, count 0 2006.189.07:20:20.45#ibcon#about to write, iclass 13, count 0 2006.189.07:20:20.45#ibcon#wrote, iclass 13, count 0 2006.189.07:20:20.45#ibcon#about to read 3, iclass 13, count 0 2006.189.07:20:20.48#ibcon#read 3, iclass 13, count 0 2006.189.07:20:20.48#ibcon#about to read 4, iclass 13, count 0 2006.189.07:20:20.48#ibcon#read 4, iclass 13, count 0 2006.189.07:20:20.48#ibcon#about to read 5, iclass 13, count 0 2006.189.07:20:20.48#ibcon#read 5, iclass 13, count 0 2006.189.07:20:20.48#ibcon#about to read 6, iclass 13, count 0 2006.189.07:20:20.48#ibcon#read 6, iclass 13, count 0 2006.189.07:20:20.48#ibcon#end of sib2, iclass 13, count 0 2006.189.07:20:20.48#ibcon#*after write, iclass 13, count 0 2006.189.07:20:20.48#ibcon#*before return 0, iclass 13, count 0 2006.189.07:20:20.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:20.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:20:20.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:20:20.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:20:20.48$vc4f8/vabw=wide 2006.189.07:20:20.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.07:20:20.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.07:20:20.48#ibcon#ireg 8 cls_cnt 0 2006.189.07:20:20.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:20.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:20.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:20.48#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:20:20.48#ibcon#first serial, iclass 15, count 0 2006.189.07:20:20.48#ibcon#enter sib2, iclass 15, count 0 2006.189.07:20:20.48#ibcon#flushed, iclass 15, count 0 2006.189.07:20:20.48#ibcon#about to write, iclass 15, count 0 2006.189.07:20:20.48#ibcon#wrote, iclass 15, count 0 2006.189.07:20:20.48#ibcon#about to read 3, iclass 15, count 0 2006.189.07:20:20.50#ibcon#read 3, iclass 15, count 0 2006.189.07:20:20.50#ibcon#about to read 4, iclass 15, count 0 2006.189.07:20:20.50#ibcon#read 4, iclass 15, count 0 2006.189.07:20:20.50#ibcon#about to read 5, iclass 15, count 0 2006.189.07:20:20.50#ibcon#read 5, iclass 15, count 0 2006.189.07:20:20.50#ibcon#about to read 6, iclass 15, count 0 2006.189.07:20:20.50#ibcon#read 6, iclass 15, count 0 2006.189.07:20:20.50#ibcon#end of sib2, iclass 15, count 0 2006.189.07:20:20.50#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:20:20.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:20:20.50#ibcon#[25=BW32\r\n] 2006.189.07:20:20.50#ibcon#*before write, iclass 15, count 0 2006.189.07:20:20.50#ibcon#enter sib2, iclass 15, count 0 2006.189.07:20:20.50#ibcon#flushed, iclass 15, count 0 2006.189.07:20:20.50#ibcon#about to write, iclass 15, count 0 2006.189.07:20:20.50#ibcon#wrote, iclass 15, count 0 2006.189.07:20:20.50#ibcon#about to read 3, iclass 15, count 0 2006.189.07:20:20.53#ibcon#read 3, iclass 15, count 0 2006.189.07:20:20.53#ibcon#about to read 4, iclass 15, count 0 2006.189.07:20:20.53#ibcon#read 4, iclass 15, count 0 2006.189.07:20:20.53#ibcon#about to read 5, iclass 15, count 0 2006.189.07:20:20.53#ibcon#read 5, iclass 15, count 0 2006.189.07:20:20.53#ibcon#about to read 6, iclass 15, count 0 2006.189.07:20:20.53#ibcon#read 6, iclass 15, count 0 2006.189.07:20:20.53#ibcon#end of sib2, iclass 15, count 0 2006.189.07:20:20.53#ibcon#*after write, iclass 15, count 0 2006.189.07:20:20.53#ibcon#*before return 0, iclass 15, count 0 2006.189.07:20:20.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:20.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:20:20.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:20:20.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:20:20.53$vc4f8/vbbw=wide 2006.189.07:20:20.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:20:20.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:20:20.53#ibcon#ireg 8 cls_cnt 0 2006.189.07:20:20.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:20:20.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:20:20.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:20:20.60#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:20:20.60#ibcon#first serial, iclass 17, count 0 2006.189.07:20:20.60#ibcon#enter sib2, iclass 17, count 0 2006.189.07:20:20.60#ibcon#flushed, iclass 17, count 0 2006.189.07:20:20.60#ibcon#about to write, iclass 17, count 0 2006.189.07:20:20.60#ibcon#wrote, iclass 17, count 0 2006.189.07:20:20.60#ibcon#about to read 3, iclass 17, count 0 2006.189.07:20:20.62#ibcon#read 3, iclass 17, count 0 2006.189.07:20:20.62#ibcon#about to read 4, iclass 17, count 0 2006.189.07:20:20.62#ibcon#read 4, iclass 17, count 0 2006.189.07:20:20.62#ibcon#about to read 5, iclass 17, count 0 2006.189.07:20:20.62#ibcon#read 5, iclass 17, count 0 2006.189.07:20:20.62#ibcon#about to read 6, iclass 17, count 0 2006.189.07:20:20.62#ibcon#read 6, iclass 17, count 0 2006.189.07:20:20.62#ibcon#end of sib2, iclass 17, count 0 2006.189.07:20:20.62#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:20:20.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:20:20.62#ibcon#[27=BW32\r\n] 2006.189.07:20:20.62#ibcon#*before write, iclass 17, count 0 2006.189.07:20:20.62#ibcon#enter sib2, iclass 17, count 0 2006.189.07:20:20.62#ibcon#flushed, iclass 17, count 0 2006.189.07:20:20.62#ibcon#about to write, iclass 17, count 0 2006.189.07:20:20.62#ibcon#wrote, iclass 17, count 0 2006.189.07:20:20.62#ibcon#about to read 3, iclass 17, count 0 2006.189.07:20:20.65#ibcon#read 3, iclass 17, count 0 2006.189.07:20:20.65#ibcon#about to read 4, iclass 17, count 0 2006.189.07:20:20.65#ibcon#read 4, iclass 17, count 0 2006.189.07:20:20.65#ibcon#about to read 5, iclass 17, count 0 2006.189.07:20:20.65#ibcon#read 5, iclass 17, count 0 2006.189.07:20:20.65#ibcon#about to read 6, iclass 17, count 0 2006.189.07:20:20.65#ibcon#read 6, iclass 17, count 0 2006.189.07:20:20.65#ibcon#end of sib2, iclass 17, count 0 2006.189.07:20:20.65#ibcon#*after write, iclass 17, count 0 2006.189.07:20:20.65#ibcon#*before return 0, iclass 17, count 0 2006.189.07:20:20.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:20:20.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:20:20.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:20:20.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:20:20.65$4f8m12a/ifd4f 2006.189.07:20:20.65&ifd4f/lo= 2006.189.07:20:20.65&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:20:20.65&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:20:20.65&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:20:20.65&ifd4f/patch= 2006.189.07:20:20.65&ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:20:20.65&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:20:20.65&ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:20:20.65$ifd4f/lo= 2006.189.07:20:20.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:20:20.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:20:20.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:20:20.65$ifd4f/patch= 2006.189.07:20:20.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:20:20.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:20:20.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:20:20.65$4f8m12a/"form=m,16.000,1:2 2006.189.07:20:20.65$4f8m12a/"tpicd 2006.189.07:20:20.65$4f8m12a/echo=off 2006.189.07:20:20.65$4f8m12a/xlog=off 2006.189.07:20:20.65:!2006.189.07:29:50 2006.189.07:20:35.13#trakl#Source acquired 2006.189.07:20:35.13#flagr#flagr/antenna,acquired 2006.189.07:29:50.00:preob 2006.189.07:29:50.00&preob/onsource 2006.189.07:29:51.14/onsource/TRACKING 2006.189.07:29:51.14:!2006.189.07:30:00 2006.189.07:30:00.00:data_valid=on 2006.189.07:30:00.00:midob 2006.189.07:30:00.00&midob/onsource 2006.189.07:30:00.00&midob/wx 2006.189.07:30:00.00&midob/cable 2006.189.07:30:00.00&midob/va 2006.189.07:30:00.00&midob/valo 2006.189.07:30:00.00&midob/vb 2006.189.07:30:00.00&midob/vblo 2006.189.07:30:00.00&midob/vabw 2006.189.07:30:00.00&midob/vbbw 2006.189.07:30:00.00&midob/"form 2006.189.07:30:00.00&midob/xfe 2006.189.07:30:00.00&midob/ifatt 2006.189.07:30:00.00&midob/clockoff 2006.189.07:30:00.00&midob/sy=logmail 2006.189.07:30:00.00&midob/"sy=run setcl adapt & 2006.189.07:30:00.14/onsource/TRACKING 2006.189.07:30:00.14/wx/26.60,1008.9,86 2006.189.07:30:00.29/cable/+6.4509E-03 2006.189.07:30:01.38/va/01,08,usb,yes,29,30 2006.189.07:30:01.38/va/02,07,usb,yes,29,30 2006.189.07:30:01.38/va/03,06,usb,yes,31,31 2006.189.07:30:01.38/va/04,07,usb,yes,30,32 2006.189.07:30:01.38/va/05,07,usb,yes,31,33 2006.189.07:30:01.38/va/06,06,usb,yes,30,30 2006.189.07:30:01.38/va/07,06,usb,yes,31,30 2006.189.07:30:01.38/va/08,06,usb,yes,33,32 2006.189.07:30:01.61/valo/01,532.99,yes,locked 2006.189.07:30:01.61/valo/02,572.99,yes,locked 2006.189.07:30:01.61/valo/03,672.99,yes,locked 2006.189.07:30:01.61/valo/04,832.99,yes,locked 2006.189.07:30:01.61/valo/05,652.99,yes,locked 2006.189.07:30:01.61/valo/06,772.99,yes,locked 2006.189.07:30:01.61/valo/07,832.99,yes,locked 2006.189.07:30:01.61/valo/08,852.99,yes,locked 2006.189.07:30:02.70/vb/01,04,usb,yes,29,28 2006.189.07:30:02.70/vb/02,04,usb,yes,31,32 2006.189.07:30:02.70/vb/03,04,usb,yes,27,31 2006.189.07:30:02.70/vb/04,04,usb,yes,28,28 2006.189.07:30:02.70/vb/05,04,usb,yes,27,30 2006.189.07:30:02.70/vb/06,04,usb,yes,28,30 2006.189.07:30:02.70/vb/07,04,usb,yes,30,29 2006.189.07:30:02.70/vb/08,04,usb,yes,27,30 2006.189.07:30:02.93/vblo/01,632.99,yes,locked 2006.189.07:30:02.93/vblo/02,640.99,yes,locked 2006.189.07:30:02.93/vblo/03,656.99,yes,locked 2006.189.07:30:02.93/vblo/04,712.99,yes,locked 2006.189.07:30:02.93/vblo/05,744.99,yes,locked 2006.189.07:30:02.93/vblo/06,752.99,yes,locked 2006.189.07:30:02.93/vblo/07,734.99,yes,locked 2006.189.07:30:02.93/vblo/08,744.99,yes,locked 2006.189.07:30:03.08/vabw/8 2006.189.07:30:03.23/vbbw/8 2006.189.07:30:03.32/xfe/off,on,15.5 2006.189.07:30:03.70/ifatt/23,28,28,28 2006.189.07:30:04.08/fmout-gps/S +2.96E-07 2006.189.07:30:04.17:!2006.189.07:31:00 2006.189.07:31:00.02:data_valid=off 2006.189.07:31:00.02:postob 2006.189.07:31:00.02&postob/cable 2006.189.07:31:00.03&postob/wx 2006.189.07:31:00.03&postob/clockoff 2006.189.07:31:00.10/cable/+6.4507E-03 2006.189.07:31:00.10/wx/26.57,1008.9,85 2006.189.07:31:00.17/fmout-gps/S +2.96E-07 2006.189.07:31:00.17:scan_name=189-0733,k06189,60 2006.189.07:31:00.17:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.189.07:31:01.14#flagr#flagr/antenna,new-source 2006.189.07:31:01.14:checkk5 2006.189.07:31:01.14&checkk5/chk_autoobs=1 2006.189.07:31:01.15&checkk5/chk_autoobs=2 2006.189.07:31:01.15&checkk5/chk_autoobs=3 2006.189.07:31:01.16&checkk5/chk_autoobs=4 2006.189.07:31:01.16&checkk5/chk_obsdata=1 2006.189.07:31:01.16&checkk5/chk_obsdata=2 2006.189.07:31:01.17&checkk5/chk_obsdata=3 2006.189.07:31:01.17&checkk5/chk_obsdata=4 2006.189.07:31:01.17&checkk5/k5log=1 2006.189.07:31:01.18&checkk5/k5log=2 2006.189.07:31:01.18&checkk5/k5log=3 2006.189.07:31:01.18&checkk5/k5log=4 2006.189.07:31:01.18&checkk5/obsinfo 2006.189.07:31:01.60/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:31:02.01/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:31:02.40/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:31:02.79/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:31:03.17/chk_obsdata//k5ts1/T1890730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:31:03.54/chk_obsdata//k5ts2/T1890730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:31:03.92/chk_obsdata//k5ts3/T1890730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:31:04.30/chk_obsdata//k5ts4/T1890730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:31:05.00/k5log//k5ts1_log_newline 2006.189.07:31:05.70/k5log//k5ts2_log_newline 2006.189.07:31:06.40/k5log//k5ts3_log_newline 2006.189.07:31:07.09/k5log//k5ts4_log_newline 2006.189.07:31:07.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:31:07.12:4f8m12a=1 2006.189.07:31:07.12$4f8m12a/echo=on 2006.189.07:31:07.12$4f8m12a/pcalon 2006.189.07:31:07.12$pcalon/"no phase cal control is implemented here 2006.189.07:31:07.12$4f8m12a/"tpicd=stop 2006.189.07:31:07.12$4f8m12a/vc4f8 2006.189.07:31:07.12$vc4f8/valo=1,532.99 2006.189.07:31:07.12#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.07:31:07.12#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.07:31:07.12#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:07.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:07.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:07.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:07.12#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:31:07.12#ibcon#first serial, iclass 24, count 0 2006.189.07:31:07.12#ibcon#enter sib2, iclass 24, count 0 2006.189.07:31:07.12#ibcon#flushed, iclass 24, count 0 2006.189.07:31:07.12#ibcon#about to write, iclass 24, count 0 2006.189.07:31:07.12#ibcon#wrote, iclass 24, count 0 2006.189.07:31:07.12#ibcon#about to read 3, iclass 24, count 0 2006.189.07:31:07.14#ibcon#read 3, iclass 24, count 0 2006.189.07:31:07.14#ibcon#about to read 4, iclass 24, count 0 2006.189.07:31:07.14#ibcon#read 4, iclass 24, count 0 2006.189.07:31:07.14#ibcon#about to read 5, iclass 24, count 0 2006.189.07:31:07.14#ibcon#read 5, iclass 24, count 0 2006.189.07:31:07.14#ibcon#about to read 6, iclass 24, count 0 2006.189.07:31:07.14#ibcon#read 6, iclass 24, count 0 2006.189.07:31:07.14#ibcon#end of sib2, iclass 24, count 0 2006.189.07:31:07.14#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:31:07.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:31:07.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:31:07.14#ibcon#*before write, iclass 24, count 0 2006.189.07:31:07.14#ibcon#enter sib2, iclass 24, count 0 2006.189.07:31:07.14#ibcon#flushed, iclass 24, count 0 2006.189.07:31:07.14#ibcon#about to write, iclass 24, count 0 2006.189.07:31:07.14#ibcon#wrote, iclass 24, count 0 2006.189.07:31:07.14#ibcon#about to read 3, iclass 24, count 0 2006.189.07:31:07.18#ibcon#read 3, iclass 24, count 0 2006.189.07:31:07.18#ibcon#about to read 4, iclass 24, count 0 2006.189.07:31:07.18#ibcon#read 4, iclass 24, count 0 2006.189.07:31:07.18#ibcon#about to read 5, iclass 24, count 0 2006.189.07:31:07.19#ibcon#read 5, iclass 24, count 0 2006.189.07:31:07.19#ibcon#about to read 6, iclass 24, count 0 2006.189.07:31:07.19#ibcon#read 6, iclass 24, count 0 2006.189.07:31:07.19#ibcon#end of sib2, iclass 24, count 0 2006.189.07:31:07.19#ibcon#*after write, iclass 24, count 0 2006.189.07:31:07.19#ibcon#*before return 0, iclass 24, count 0 2006.189.07:31:07.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:07.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:07.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:31:07.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:31:07.19$vc4f8/va=1,8 2006.189.07:31:07.19#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.07:31:07.19#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.07:31:07.19#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:07.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:07.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:07.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:07.19#ibcon#enter wrdev, iclass 26, count 2 2006.189.07:31:07.19#ibcon#first serial, iclass 26, count 2 2006.189.07:31:07.19#ibcon#enter sib2, iclass 26, count 2 2006.189.07:31:07.19#ibcon#flushed, iclass 26, count 2 2006.189.07:31:07.19#ibcon#about to write, iclass 26, count 2 2006.189.07:31:07.19#ibcon#wrote, iclass 26, count 2 2006.189.07:31:07.19#ibcon#about to read 3, iclass 26, count 2 2006.189.07:31:07.20#ibcon#read 3, iclass 26, count 2 2006.189.07:31:07.20#ibcon#about to read 4, iclass 26, count 2 2006.189.07:31:07.20#ibcon#read 4, iclass 26, count 2 2006.189.07:31:07.21#ibcon#about to read 5, iclass 26, count 2 2006.189.07:31:07.21#ibcon#read 5, iclass 26, count 2 2006.189.07:31:07.21#ibcon#about to read 6, iclass 26, count 2 2006.189.07:31:07.21#ibcon#read 6, iclass 26, count 2 2006.189.07:31:07.21#ibcon#end of sib2, iclass 26, count 2 2006.189.07:31:07.21#ibcon#*mode == 0, iclass 26, count 2 2006.189.07:31:07.21#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.07:31:07.21#ibcon#[25=AT01-08\r\n] 2006.189.07:31:07.21#ibcon#*before write, iclass 26, count 2 2006.189.07:31:07.21#ibcon#enter sib2, iclass 26, count 2 2006.189.07:31:07.21#ibcon#flushed, iclass 26, count 2 2006.189.07:31:07.21#ibcon#about to write, iclass 26, count 2 2006.189.07:31:07.21#ibcon#wrote, iclass 26, count 2 2006.189.07:31:07.21#ibcon#about to read 3, iclass 26, count 2 2006.189.07:31:07.24#ibcon#read 3, iclass 26, count 2 2006.189.07:31:07.24#ibcon#about to read 4, iclass 26, count 2 2006.189.07:31:07.24#ibcon#read 4, iclass 26, count 2 2006.189.07:31:07.24#ibcon#about to read 5, iclass 26, count 2 2006.189.07:31:07.24#ibcon#read 5, iclass 26, count 2 2006.189.07:31:07.24#ibcon#about to read 6, iclass 26, count 2 2006.189.07:31:07.24#ibcon#read 6, iclass 26, count 2 2006.189.07:31:07.24#ibcon#end of sib2, iclass 26, count 2 2006.189.07:31:07.24#ibcon#*after write, iclass 26, count 2 2006.189.07:31:07.24#ibcon#*before return 0, iclass 26, count 2 2006.189.07:31:07.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:07.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:07.24#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.07:31:07.24#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:07.24#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:07.36#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:07.36#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:07.36#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:31:07.36#ibcon#first serial, iclass 26, count 0 2006.189.07:31:07.36#ibcon#enter sib2, iclass 26, count 0 2006.189.07:31:07.36#ibcon#flushed, iclass 26, count 0 2006.189.07:31:07.36#ibcon#about to write, iclass 26, count 0 2006.189.07:31:07.36#ibcon#wrote, iclass 26, count 0 2006.189.07:31:07.36#ibcon#about to read 3, iclass 26, count 0 2006.189.07:31:07.38#ibcon#read 3, iclass 26, count 0 2006.189.07:31:07.38#ibcon#about to read 4, iclass 26, count 0 2006.189.07:31:07.38#ibcon#read 4, iclass 26, count 0 2006.189.07:31:07.38#ibcon#about to read 5, iclass 26, count 0 2006.189.07:31:07.38#ibcon#read 5, iclass 26, count 0 2006.189.07:31:07.38#ibcon#about to read 6, iclass 26, count 0 2006.189.07:31:07.38#ibcon#read 6, iclass 26, count 0 2006.189.07:31:07.38#ibcon#end of sib2, iclass 26, count 0 2006.189.07:31:07.38#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:31:07.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:31:07.38#ibcon#[25=USB\r\n] 2006.189.07:31:07.38#ibcon#*before write, iclass 26, count 0 2006.189.07:31:07.38#ibcon#enter sib2, iclass 26, count 0 2006.189.07:31:07.38#ibcon#flushed, iclass 26, count 0 2006.189.07:31:07.38#ibcon#about to write, iclass 26, count 0 2006.189.07:31:07.38#ibcon#wrote, iclass 26, count 0 2006.189.07:31:07.38#ibcon#about to read 3, iclass 26, count 0 2006.189.07:31:07.40#ibcon#read 3, iclass 26, count 0 2006.189.07:31:07.41#ibcon#about to read 4, iclass 26, count 0 2006.189.07:31:07.41#ibcon#read 4, iclass 26, count 0 2006.189.07:31:07.41#ibcon#about to read 5, iclass 26, count 0 2006.189.07:31:07.41#ibcon#read 5, iclass 26, count 0 2006.189.07:31:07.41#ibcon#about to read 6, iclass 26, count 0 2006.189.07:31:07.41#ibcon#read 6, iclass 26, count 0 2006.189.07:31:07.41#ibcon#end of sib2, iclass 26, count 0 2006.189.07:31:07.41#ibcon#*after write, iclass 26, count 0 2006.189.07:31:07.41#ibcon#*before return 0, iclass 26, count 0 2006.189.07:31:07.41#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:07.41#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:07.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:31:07.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:31:07.41$vc4f8/valo=2,572.99 2006.189.07:31:07.41#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.07:31:07.41#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.07:31:07.41#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:07.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:07.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:07.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:07.41#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:31:07.41#ibcon#first serial, iclass 28, count 0 2006.189.07:31:07.41#ibcon#enter sib2, iclass 28, count 0 2006.189.07:31:07.41#ibcon#flushed, iclass 28, count 0 2006.189.07:31:07.41#ibcon#about to write, iclass 28, count 0 2006.189.07:31:07.41#ibcon#wrote, iclass 28, count 0 2006.189.07:31:07.41#ibcon#about to read 3, iclass 28, count 0 2006.189.07:31:07.42#ibcon#read 3, iclass 28, count 0 2006.189.07:31:07.42#ibcon#about to read 4, iclass 28, count 0 2006.189.07:31:07.42#ibcon#read 4, iclass 28, count 0 2006.189.07:31:07.43#ibcon#about to read 5, iclass 28, count 0 2006.189.07:31:07.43#ibcon#read 5, iclass 28, count 0 2006.189.07:31:07.43#ibcon#about to read 6, iclass 28, count 0 2006.189.07:31:07.43#ibcon#read 6, iclass 28, count 0 2006.189.07:31:07.43#ibcon#end of sib2, iclass 28, count 0 2006.189.07:31:07.43#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:31:07.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:31:07.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:31:07.43#ibcon#*before write, iclass 28, count 0 2006.189.07:31:07.43#ibcon#enter sib2, iclass 28, count 0 2006.189.07:31:07.43#ibcon#flushed, iclass 28, count 0 2006.189.07:31:07.43#ibcon#about to write, iclass 28, count 0 2006.189.07:31:07.43#ibcon#wrote, iclass 28, count 0 2006.189.07:31:07.43#ibcon#about to read 3, iclass 28, count 0 2006.189.07:31:07.47#ibcon#read 3, iclass 28, count 0 2006.189.07:31:07.47#ibcon#about to read 4, iclass 28, count 0 2006.189.07:31:07.47#ibcon#read 4, iclass 28, count 0 2006.189.07:31:07.47#ibcon#about to read 5, iclass 28, count 0 2006.189.07:31:07.47#ibcon#read 5, iclass 28, count 0 2006.189.07:31:07.47#ibcon#about to read 6, iclass 28, count 0 2006.189.07:31:07.47#ibcon#read 6, iclass 28, count 0 2006.189.07:31:07.47#ibcon#end of sib2, iclass 28, count 0 2006.189.07:31:07.47#ibcon#*after write, iclass 28, count 0 2006.189.07:31:07.47#ibcon#*before return 0, iclass 28, count 0 2006.189.07:31:07.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:07.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:07.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:31:07.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:31:07.47$vc4f8/va=2,7 2006.189.07:31:07.47#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.07:31:07.47#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.07:31:07.47#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:07.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:07.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:07.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:07.52#ibcon#enter wrdev, iclass 30, count 2 2006.189.07:31:07.52#ibcon#first serial, iclass 30, count 2 2006.189.07:31:07.52#ibcon#enter sib2, iclass 30, count 2 2006.189.07:31:07.53#ibcon#flushed, iclass 30, count 2 2006.189.07:31:07.53#ibcon#about to write, iclass 30, count 2 2006.189.07:31:07.53#ibcon#wrote, iclass 30, count 2 2006.189.07:31:07.53#ibcon#about to read 3, iclass 30, count 2 2006.189.07:31:07.54#ibcon#read 3, iclass 30, count 2 2006.189.07:31:07.54#ibcon#about to read 4, iclass 30, count 2 2006.189.07:31:07.54#ibcon#read 4, iclass 30, count 2 2006.189.07:31:07.55#ibcon#about to read 5, iclass 30, count 2 2006.189.07:31:07.55#ibcon#read 5, iclass 30, count 2 2006.189.07:31:07.55#ibcon#about to read 6, iclass 30, count 2 2006.189.07:31:07.55#ibcon#read 6, iclass 30, count 2 2006.189.07:31:07.55#ibcon#end of sib2, iclass 30, count 2 2006.189.07:31:07.55#ibcon#*mode == 0, iclass 30, count 2 2006.189.07:31:07.55#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.07:31:07.55#ibcon#[25=AT02-07\r\n] 2006.189.07:31:07.55#ibcon#*before write, iclass 30, count 2 2006.189.07:31:07.55#ibcon#enter sib2, iclass 30, count 2 2006.189.07:31:07.55#ibcon#flushed, iclass 30, count 2 2006.189.07:31:07.55#ibcon#about to write, iclass 30, count 2 2006.189.07:31:07.55#ibcon#wrote, iclass 30, count 2 2006.189.07:31:07.55#ibcon#about to read 3, iclass 30, count 2 2006.189.07:31:07.58#ibcon#read 3, iclass 30, count 2 2006.189.07:31:07.58#ibcon#about to read 4, iclass 30, count 2 2006.189.07:31:07.58#ibcon#read 4, iclass 30, count 2 2006.189.07:31:07.58#ibcon#about to read 5, iclass 30, count 2 2006.189.07:31:07.58#ibcon#read 5, iclass 30, count 2 2006.189.07:31:07.58#ibcon#about to read 6, iclass 30, count 2 2006.189.07:31:07.58#ibcon#read 6, iclass 30, count 2 2006.189.07:31:07.58#ibcon#end of sib2, iclass 30, count 2 2006.189.07:31:07.58#ibcon#*after write, iclass 30, count 2 2006.189.07:31:07.58#ibcon#*before return 0, iclass 30, count 2 2006.189.07:31:07.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:07.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:07.58#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.07:31:07.58#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:07.58#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:07.69#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:07.69#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:07.70#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:31:07.70#ibcon#first serial, iclass 30, count 0 2006.189.07:31:07.70#ibcon#enter sib2, iclass 30, count 0 2006.189.07:31:07.70#ibcon#flushed, iclass 30, count 0 2006.189.07:31:07.70#ibcon#about to write, iclass 30, count 0 2006.189.07:31:07.70#ibcon#wrote, iclass 30, count 0 2006.189.07:31:07.70#ibcon#about to read 3, iclass 30, count 0 2006.189.07:31:07.72#ibcon#read 3, iclass 30, count 0 2006.189.07:31:07.72#ibcon#about to read 4, iclass 30, count 0 2006.189.07:31:07.72#ibcon#read 4, iclass 30, count 0 2006.189.07:31:07.72#ibcon#about to read 5, iclass 30, count 0 2006.189.07:31:07.72#ibcon#read 5, iclass 30, count 0 2006.189.07:31:07.72#ibcon#about to read 6, iclass 30, count 0 2006.189.07:31:07.72#ibcon#read 6, iclass 30, count 0 2006.189.07:31:07.72#ibcon#end of sib2, iclass 30, count 0 2006.189.07:31:07.72#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:31:07.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:31:07.72#ibcon#[25=USB\r\n] 2006.189.07:31:07.72#ibcon#*before write, iclass 30, count 0 2006.189.07:31:07.72#ibcon#enter sib2, iclass 30, count 0 2006.189.07:31:07.72#ibcon#flushed, iclass 30, count 0 2006.189.07:31:07.72#ibcon#about to write, iclass 30, count 0 2006.189.07:31:07.72#ibcon#wrote, iclass 30, count 0 2006.189.07:31:07.72#ibcon#about to read 3, iclass 30, count 0 2006.189.07:31:07.74#ibcon#read 3, iclass 30, count 0 2006.189.07:31:07.74#ibcon#about to read 4, iclass 30, count 0 2006.189.07:31:07.74#ibcon#read 4, iclass 30, count 0 2006.189.07:31:07.75#ibcon#about to read 5, iclass 30, count 0 2006.189.07:31:07.75#ibcon#read 5, iclass 30, count 0 2006.189.07:31:07.75#ibcon#about to read 6, iclass 30, count 0 2006.189.07:31:07.75#ibcon#read 6, iclass 30, count 0 2006.189.07:31:07.75#ibcon#end of sib2, iclass 30, count 0 2006.189.07:31:07.75#ibcon#*after write, iclass 30, count 0 2006.189.07:31:07.75#ibcon#*before return 0, iclass 30, count 0 2006.189.07:31:07.75#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:07.75#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:07.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:31:07.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:31:07.75$vc4f8/valo=3,672.99 2006.189.07:31:07.75#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.07:31:07.75#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.07:31:07.75#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:07.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:07.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:07.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:07.75#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:31:07.75#ibcon#first serial, iclass 32, count 0 2006.189.07:31:07.75#ibcon#enter sib2, iclass 32, count 0 2006.189.07:31:07.75#ibcon#flushed, iclass 32, count 0 2006.189.07:31:07.75#ibcon#about to write, iclass 32, count 0 2006.189.07:31:07.75#ibcon#wrote, iclass 32, count 0 2006.189.07:31:07.75#ibcon#about to read 3, iclass 32, count 0 2006.189.07:31:07.77#ibcon#read 3, iclass 32, count 0 2006.189.07:31:07.77#ibcon#about to read 4, iclass 32, count 0 2006.189.07:31:07.77#ibcon#read 4, iclass 32, count 0 2006.189.07:31:07.77#ibcon#about to read 5, iclass 32, count 0 2006.189.07:31:07.77#ibcon#read 5, iclass 32, count 0 2006.189.07:31:07.77#ibcon#about to read 6, iclass 32, count 0 2006.189.07:31:07.77#ibcon#read 6, iclass 32, count 0 2006.189.07:31:07.77#ibcon#end of sib2, iclass 32, count 0 2006.189.07:31:07.77#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:31:07.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:31:07.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:31:07.77#ibcon#*before write, iclass 32, count 0 2006.189.07:31:07.77#ibcon#enter sib2, iclass 32, count 0 2006.189.07:31:07.77#ibcon#flushed, iclass 32, count 0 2006.189.07:31:07.77#ibcon#about to write, iclass 32, count 0 2006.189.07:31:07.77#ibcon#wrote, iclass 32, count 0 2006.189.07:31:07.77#ibcon#about to read 3, iclass 32, count 0 2006.189.07:31:07.81#ibcon#read 3, iclass 32, count 0 2006.189.07:31:07.81#ibcon#about to read 4, iclass 32, count 0 2006.189.07:31:07.81#ibcon#read 4, iclass 32, count 0 2006.189.07:31:07.81#ibcon#about to read 5, iclass 32, count 0 2006.189.07:31:07.81#ibcon#read 5, iclass 32, count 0 2006.189.07:31:07.81#ibcon#about to read 6, iclass 32, count 0 2006.189.07:31:07.81#ibcon#read 6, iclass 32, count 0 2006.189.07:31:07.81#ibcon#end of sib2, iclass 32, count 0 2006.189.07:31:07.81#ibcon#*after write, iclass 32, count 0 2006.189.07:31:07.81#ibcon#*before return 0, iclass 32, count 0 2006.189.07:31:07.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:07.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:07.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:31:07.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:31:07.81$vc4f8/va=3,6 2006.189.07:31:07.81#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.07:31:07.81#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.07:31:07.81#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:07.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:07.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:07.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:07.87#ibcon#enter wrdev, iclass 34, count 2 2006.189.07:31:07.87#ibcon#first serial, iclass 34, count 2 2006.189.07:31:07.87#ibcon#enter sib2, iclass 34, count 2 2006.189.07:31:07.87#ibcon#flushed, iclass 34, count 2 2006.189.07:31:07.87#ibcon#about to write, iclass 34, count 2 2006.189.07:31:07.87#ibcon#wrote, iclass 34, count 2 2006.189.07:31:07.87#ibcon#about to read 3, iclass 34, count 2 2006.189.07:31:07.88#ibcon#read 3, iclass 34, count 2 2006.189.07:31:07.88#ibcon#about to read 4, iclass 34, count 2 2006.189.07:31:07.88#ibcon#read 4, iclass 34, count 2 2006.189.07:31:07.89#ibcon#about to read 5, iclass 34, count 2 2006.189.07:31:07.89#ibcon#read 5, iclass 34, count 2 2006.189.07:31:07.89#ibcon#about to read 6, iclass 34, count 2 2006.189.07:31:07.89#ibcon#read 6, iclass 34, count 2 2006.189.07:31:07.89#ibcon#end of sib2, iclass 34, count 2 2006.189.07:31:07.89#ibcon#*mode == 0, iclass 34, count 2 2006.189.07:31:07.89#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.07:31:07.89#ibcon#[25=AT03-06\r\n] 2006.189.07:31:07.89#ibcon#*before write, iclass 34, count 2 2006.189.07:31:07.89#ibcon#enter sib2, iclass 34, count 2 2006.189.07:31:07.89#ibcon#flushed, iclass 34, count 2 2006.189.07:31:07.89#ibcon#about to write, iclass 34, count 2 2006.189.07:31:07.89#ibcon#wrote, iclass 34, count 2 2006.189.07:31:07.89#ibcon#about to read 3, iclass 34, count 2 2006.189.07:31:07.91#ibcon#read 3, iclass 34, count 2 2006.189.07:31:07.91#ibcon#about to read 4, iclass 34, count 2 2006.189.07:31:07.91#ibcon#read 4, iclass 34, count 2 2006.189.07:31:07.91#ibcon#about to read 5, iclass 34, count 2 2006.189.07:31:07.92#ibcon#read 5, iclass 34, count 2 2006.189.07:31:07.92#ibcon#about to read 6, iclass 34, count 2 2006.189.07:31:07.92#ibcon#read 6, iclass 34, count 2 2006.189.07:31:07.92#ibcon#end of sib2, iclass 34, count 2 2006.189.07:31:07.92#ibcon#*after write, iclass 34, count 2 2006.189.07:31:07.92#ibcon#*before return 0, iclass 34, count 2 2006.189.07:31:07.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:07.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:07.92#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.07:31:07.92#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:07.92#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:08.03#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:08.03#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:08.03#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:31:08.03#ibcon#first serial, iclass 34, count 0 2006.189.07:31:08.03#ibcon#enter sib2, iclass 34, count 0 2006.189.07:31:08.04#ibcon#flushed, iclass 34, count 0 2006.189.07:31:08.04#ibcon#about to write, iclass 34, count 0 2006.189.07:31:08.04#ibcon#wrote, iclass 34, count 0 2006.189.07:31:08.04#ibcon#about to read 3, iclass 34, count 0 2006.189.07:31:08.05#ibcon#read 3, iclass 34, count 0 2006.189.07:31:08.06#ibcon#about to read 4, iclass 34, count 0 2006.189.07:31:08.06#ibcon#read 4, iclass 34, count 0 2006.189.07:31:08.06#ibcon#about to read 5, iclass 34, count 0 2006.189.07:31:08.06#ibcon#read 5, iclass 34, count 0 2006.189.07:31:08.06#ibcon#about to read 6, iclass 34, count 0 2006.189.07:31:08.06#ibcon#read 6, iclass 34, count 0 2006.189.07:31:08.06#ibcon#end of sib2, iclass 34, count 0 2006.189.07:31:08.06#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:31:08.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:31:08.06#ibcon#[25=USB\r\n] 2006.189.07:31:08.06#ibcon#*before write, iclass 34, count 0 2006.189.07:31:08.06#ibcon#enter sib2, iclass 34, count 0 2006.189.07:31:08.06#ibcon#flushed, iclass 34, count 0 2006.189.07:31:08.06#ibcon#about to write, iclass 34, count 0 2006.189.07:31:08.06#ibcon#wrote, iclass 34, count 0 2006.189.07:31:08.06#ibcon#about to read 3, iclass 34, count 0 2006.189.07:31:08.08#ibcon#read 3, iclass 34, count 0 2006.189.07:31:08.08#ibcon#about to read 4, iclass 34, count 0 2006.189.07:31:08.08#ibcon#read 4, iclass 34, count 0 2006.189.07:31:08.09#ibcon#about to read 5, iclass 34, count 0 2006.189.07:31:08.09#ibcon#read 5, iclass 34, count 0 2006.189.07:31:08.09#ibcon#about to read 6, iclass 34, count 0 2006.189.07:31:08.09#ibcon#read 6, iclass 34, count 0 2006.189.07:31:08.09#ibcon#end of sib2, iclass 34, count 0 2006.189.07:31:08.09#ibcon#*after write, iclass 34, count 0 2006.189.07:31:08.09#ibcon#*before return 0, iclass 34, count 0 2006.189.07:31:08.09#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:08.09#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:08.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:31:08.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:31:08.09$vc4f8/valo=4,832.99 2006.189.07:31:08.09#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.07:31:08.09#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.07:31:08.09#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:08.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:08.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:08.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:08.09#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:31:08.09#ibcon#first serial, iclass 36, count 0 2006.189.07:31:08.09#ibcon#enter sib2, iclass 36, count 0 2006.189.07:31:08.09#ibcon#flushed, iclass 36, count 0 2006.189.07:31:08.09#ibcon#about to write, iclass 36, count 0 2006.189.07:31:08.09#ibcon#wrote, iclass 36, count 0 2006.189.07:31:08.09#ibcon#about to read 3, iclass 36, count 0 2006.189.07:31:08.10#ibcon#read 3, iclass 36, count 0 2006.189.07:31:08.10#ibcon#about to read 4, iclass 36, count 0 2006.189.07:31:08.10#ibcon#read 4, iclass 36, count 0 2006.189.07:31:08.11#ibcon#about to read 5, iclass 36, count 0 2006.189.07:31:08.11#ibcon#read 5, iclass 36, count 0 2006.189.07:31:08.11#ibcon#about to read 6, iclass 36, count 0 2006.189.07:31:08.11#ibcon#read 6, iclass 36, count 0 2006.189.07:31:08.11#ibcon#end of sib2, iclass 36, count 0 2006.189.07:31:08.11#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:31:08.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:31:08.11#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:31:08.11#ibcon#*before write, iclass 36, count 0 2006.189.07:31:08.11#ibcon#enter sib2, iclass 36, count 0 2006.189.07:31:08.11#ibcon#flushed, iclass 36, count 0 2006.189.07:31:08.11#ibcon#about to write, iclass 36, count 0 2006.189.07:31:08.11#ibcon#wrote, iclass 36, count 0 2006.189.07:31:08.11#ibcon#about to read 3, iclass 36, count 0 2006.189.07:31:08.14#ibcon#read 3, iclass 36, count 0 2006.189.07:31:08.14#ibcon#about to read 4, iclass 36, count 0 2006.189.07:31:08.14#ibcon#read 4, iclass 36, count 0 2006.189.07:31:08.15#ibcon#about to read 5, iclass 36, count 0 2006.189.07:31:08.15#ibcon#read 5, iclass 36, count 0 2006.189.07:31:08.15#ibcon#about to read 6, iclass 36, count 0 2006.189.07:31:08.15#ibcon#read 6, iclass 36, count 0 2006.189.07:31:08.15#ibcon#end of sib2, iclass 36, count 0 2006.189.07:31:08.15#ibcon#*after write, iclass 36, count 0 2006.189.07:31:08.15#ibcon#*before return 0, iclass 36, count 0 2006.189.07:31:08.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:08.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:08.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:31:08.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:31:08.15$vc4f8/va=4,7 2006.189.07:31:08.15#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.07:31:08.15#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.07:31:08.15#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:08.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:08.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:08.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:08.20#ibcon#enter wrdev, iclass 38, count 2 2006.189.07:31:08.20#ibcon#first serial, iclass 38, count 2 2006.189.07:31:08.20#ibcon#enter sib2, iclass 38, count 2 2006.189.07:31:08.21#ibcon#flushed, iclass 38, count 2 2006.189.07:31:08.21#ibcon#about to write, iclass 38, count 2 2006.189.07:31:08.21#ibcon#wrote, iclass 38, count 2 2006.189.07:31:08.21#ibcon#about to read 3, iclass 38, count 2 2006.189.07:31:08.22#ibcon#read 3, iclass 38, count 2 2006.189.07:31:08.22#ibcon#about to read 4, iclass 38, count 2 2006.189.07:31:08.22#ibcon#read 4, iclass 38, count 2 2006.189.07:31:08.23#ibcon#about to read 5, iclass 38, count 2 2006.189.07:31:08.23#ibcon#read 5, iclass 38, count 2 2006.189.07:31:08.23#ibcon#about to read 6, iclass 38, count 2 2006.189.07:31:08.23#ibcon#read 6, iclass 38, count 2 2006.189.07:31:08.23#ibcon#end of sib2, iclass 38, count 2 2006.189.07:31:08.23#ibcon#*mode == 0, iclass 38, count 2 2006.189.07:31:08.23#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.07:31:08.23#ibcon#[25=AT04-07\r\n] 2006.189.07:31:08.23#ibcon#*before write, iclass 38, count 2 2006.189.07:31:08.23#ibcon#enter sib2, iclass 38, count 2 2006.189.07:31:08.23#ibcon#flushed, iclass 38, count 2 2006.189.07:31:08.23#ibcon#about to write, iclass 38, count 2 2006.189.07:31:08.23#ibcon#wrote, iclass 38, count 2 2006.189.07:31:08.23#ibcon#about to read 3, iclass 38, count 2 2006.189.07:31:08.25#ibcon#read 3, iclass 38, count 2 2006.189.07:31:08.25#ibcon#about to read 4, iclass 38, count 2 2006.189.07:31:08.25#ibcon#read 4, iclass 38, count 2 2006.189.07:31:08.26#ibcon#about to read 5, iclass 38, count 2 2006.189.07:31:08.26#ibcon#read 5, iclass 38, count 2 2006.189.07:31:08.26#ibcon#about to read 6, iclass 38, count 2 2006.189.07:31:08.26#ibcon#read 6, iclass 38, count 2 2006.189.07:31:08.26#ibcon#end of sib2, iclass 38, count 2 2006.189.07:31:08.26#ibcon#*after write, iclass 38, count 2 2006.189.07:31:08.26#ibcon#*before return 0, iclass 38, count 2 2006.189.07:31:08.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:08.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:08.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.07:31:08.26#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:08.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:08.37#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:08.37#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:08.37#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:31:08.37#ibcon#first serial, iclass 38, count 0 2006.189.07:31:08.37#ibcon#enter sib2, iclass 38, count 0 2006.189.07:31:08.38#ibcon#flushed, iclass 38, count 0 2006.189.07:31:08.38#ibcon#about to write, iclass 38, count 0 2006.189.07:31:08.38#ibcon#wrote, iclass 38, count 0 2006.189.07:31:08.38#ibcon#about to read 3, iclass 38, count 0 2006.189.07:31:08.39#ibcon#read 3, iclass 38, count 0 2006.189.07:31:08.39#ibcon#about to read 4, iclass 38, count 0 2006.189.07:31:08.39#ibcon#read 4, iclass 38, count 0 2006.189.07:31:08.40#ibcon#about to read 5, iclass 38, count 0 2006.189.07:31:08.40#ibcon#read 5, iclass 38, count 0 2006.189.07:31:08.40#ibcon#about to read 6, iclass 38, count 0 2006.189.07:31:08.40#ibcon#read 6, iclass 38, count 0 2006.189.07:31:08.40#ibcon#end of sib2, iclass 38, count 0 2006.189.07:31:08.40#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:31:08.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:31:08.40#ibcon#[25=USB\r\n] 2006.189.07:31:08.40#ibcon#*before write, iclass 38, count 0 2006.189.07:31:08.40#ibcon#enter sib2, iclass 38, count 0 2006.189.07:31:08.40#ibcon#flushed, iclass 38, count 0 2006.189.07:31:08.40#ibcon#about to write, iclass 38, count 0 2006.189.07:31:08.40#ibcon#wrote, iclass 38, count 0 2006.189.07:31:08.40#ibcon#about to read 3, iclass 38, count 0 2006.189.07:31:08.42#ibcon#read 3, iclass 38, count 0 2006.189.07:31:08.42#ibcon#about to read 4, iclass 38, count 0 2006.189.07:31:08.42#ibcon#read 4, iclass 38, count 0 2006.189.07:31:08.43#ibcon#about to read 5, iclass 38, count 0 2006.189.07:31:08.43#ibcon#read 5, iclass 38, count 0 2006.189.07:31:08.43#ibcon#about to read 6, iclass 38, count 0 2006.189.07:31:08.43#ibcon#read 6, iclass 38, count 0 2006.189.07:31:08.43#ibcon#end of sib2, iclass 38, count 0 2006.189.07:31:08.43#ibcon#*after write, iclass 38, count 0 2006.189.07:31:08.43#ibcon#*before return 0, iclass 38, count 0 2006.189.07:31:08.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:08.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:08.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:31:08.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:31:08.43$vc4f8/valo=5,652.99 2006.189.07:31:08.43#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.07:31:08.43#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.07:31:08.43#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:08.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:08.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:08.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:08.43#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:31:08.43#ibcon#first serial, iclass 40, count 0 2006.189.07:31:08.43#ibcon#enter sib2, iclass 40, count 0 2006.189.07:31:08.43#ibcon#flushed, iclass 40, count 0 2006.189.07:31:08.43#ibcon#about to write, iclass 40, count 0 2006.189.07:31:08.43#ibcon#wrote, iclass 40, count 0 2006.189.07:31:08.43#ibcon#about to read 3, iclass 40, count 0 2006.189.07:31:08.44#ibcon#read 3, iclass 40, count 0 2006.189.07:31:08.44#ibcon#about to read 4, iclass 40, count 0 2006.189.07:31:08.44#ibcon#read 4, iclass 40, count 0 2006.189.07:31:08.45#ibcon#about to read 5, iclass 40, count 0 2006.189.07:31:08.45#ibcon#read 5, iclass 40, count 0 2006.189.07:31:08.45#ibcon#about to read 6, iclass 40, count 0 2006.189.07:31:08.45#ibcon#read 6, iclass 40, count 0 2006.189.07:31:08.45#ibcon#end of sib2, iclass 40, count 0 2006.189.07:31:08.45#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:31:08.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:31:08.45#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:31:08.45#ibcon#*before write, iclass 40, count 0 2006.189.07:31:08.45#ibcon#enter sib2, iclass 40, count 0 2006.189.07:31:08.45#ibcon#flushed, iclass 40, count 0 2006.189.07:31:08.45#ibcon#about to write, iclass 40, count 0 2006.189.07:31:08.45#ibcon#wrote, iclass 40, count 0 2006.189.07:31:08.45#ibcon#about to read 3, iclass 40, count 0 2006.189.07:31:08.48#ibcon#read 3, iclass 40, count 0 2006.189.07:31:08.48#ibcon#about to read 4, iclass 40, count 0 2006.189.07:31:08.48#ibcon#read 4, iclass 40, count 0 2006.189.07:31:08.48#ibcon#about to read 5, iclass 40, count 0 2006.189.07:31:08.49#ibcon#read 5, iclass 40, count 0 2006.189.07:31:08.49#ibcon#about to read 6, iclass 40, count 0 2006.189.07:31:08.49#ibcon#read 6, iclass 40, count 0 2006.189.07:31:08.49#ibcon#end of sib2, iclass 40, count 0 2006.189.07:31:08.49#ibcon#*after write, iclass 40, count 0 2006.189.07:31:08.49#ibcon#*before return 0, iclass 40, count 0 2006.189.07:31:08.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:08.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:08.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:31:08.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:31:08.49$vc4f8/va=5,7 2006.189.07:31:08.49#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.07:31:08.49#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.07:31:08.49#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:08.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:08.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:08.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:08.54#ibcon#enter wrdev, iclass 4, count 2 2006.189.07:31:08.54#ibcon#first serial, iclass 4, count 2 2006.189.07:31:08.54#ibcon#enter sib2, iclass 4, count 2 2006.189.07:31:08.55#ibcon#flushed, iclass 4, count 2 2006.189.07:31:08.55#ibcon#about to write, iclass 4, count 2 2006.189.07:31:08.55#ibcon#wrote, iclass 4, count 2 2006.189.07:31:08.55#ibcon#about to read 3, iclass 4, count 2 2006.189.07:31:08.56#ibcon#read 3, iclass 4, count 2 2006.189.07:31:08.56#ibcon#about to read 4, iclass 4, count 2 2006.189.07:31:08.57#ibcon#read 4, iclass 4, count 2 2006.189.07:31:08.57#ibcon#about to read 5, iclass 4, count 2 2006.189.07:31:08.57#ibcon#read 5, iclass 4, count 2 2006.189.07:31:08.57#ibcon#about to read 6, iclass 4, count 2 2006.189.07:31:08.57#ibcon#read 6, iclass 4, count 2 2006.189.07:31:08.57#ibcon#end of sib2, iclass 4, count 2 2006.189.07:31:08.57#ibcon#*mode == 0, iclass 4, count 2 2006.189.07:31:08.57#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.07:31:08.57#ibcon#[25=AT05-07\r\n] 2006.189.07:31:08.57#ibcon#*before write, iclass 4, count 2 2006.189.07:31:08.57#ibcon#enter sib2, iclass 4, count 2 2006.189.07:31:08.57#ibcon#flushed, iclass 4, count 2 2006.189.07:31:08.57#ibcon#about to write, iclass 4, count 2 2006.189.07:31:08.57#ibcon#wrote, iclass 4, count 2 2006.189.07:31:08.57#ibcon#about to read 3, iclass 4, count 2 2006.189.07:31:08.59#ibcon#read 3, iclass 4, count 2 2006.189.07:31:08.59#ibcon#about to read 4, iclass 4, count 2 2006.189.07:31:08.59#ibcon#read 4, iclass 4, count 2 2006.189.07:31:08.59#ibcon#about to read 5, iclass 4, count 2 2006.189.07:31:08.60#ibcon#read 5, iclass 4, count 2 2006.189.07:31:08.60#ibcon#about to read 6, iclass 4, count 2 2006.189.07:31:08.60#ibcon#read 6, iclass 4, count 2 2006.189.07:31:08.60#ibcon#end of sib2, iclass 4, count 2 2006.189.07:31:08.60#ibcon#*after write, iclass 4, count 2 2006.189.07:31:08.60#ibcon#*before return 0, iclass 4, count 2 2006.189.07:31:08.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:08.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:08.60#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.07:31:08.60#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:08.60#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:08.71#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:08.71#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:08.71#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:31:08.71#ibcon#first serial, iclass 4, count 0 2006.189.07:31:08.71#ibcon#enter sib2, iclass 4, count 0 2006.189.07:31:08.72#ibcon#flushed, iclass 4, count 0 2006.189.07:31:08.72#ibcon#about to write, iclass 4, count 0 2006.189.07:31:08.72#ibcon#wrote, iclass 4, count 0 2006.189.07:31:08.72#ibcon#about to read 3, iclass 4, count 0 2006.189.07:31:08.73#ibcon#read 3, iclass 4, count 0 2006.189.07:31:08.73#ibcon#about to read 4, iclass 4, count 0 2006.189.07:31:08.74#ibcon#read 4, iclass 4, count 0 2006.189.07:31:08.74#ibcon#about to read 5, iclass 4, count 0 2006.189.07:31:08.74#ibcon#read 5, iclass 4, count 0 2006.189.07:31:08.74#ibcon#about to read 6, iclass 4, count 0 2006.189.07:31:08.74#ibcon#read 6, iclass 4, count 0 2006.189.07:31:08.74#ibcon#end of sib2, iclass 4, count 0 2006.189.07:31:08.74#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:31:08.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:31:08.74#ibcon#[25=USB\r\n] 2006.189.07:31:08.74#ibcon#*before write, iclass 4, count 0 2006.189.07:31:08.74#ibcon#enter sib2, iclass 4, count 0 2006.189.07:31:08.74#ibcon#flushed, iclass 4, count 0 2006.189.07:31:08.74#ibcon#about to write, iclass 4, count 0 2006.189.07:31:08.74#ibcon#wrote, iclass 4, count 0 2006.189.07:31:08.74#ibcon#about to read 3, iclass 4, count 0 2006.189.07:31:08.76#ibcon#read 3, iclass 4, count 0 2006.189.07:31:08.76#ibcon#about to read 4, iclass 4, count 0 2006.189.07:31:08.76#ibcon#read 4, iclass 4, count 0 2006.189.07:31:08.77#ibcon#about to read 5, iclass 4, count 0 2006.189.07:31:08.77#ibcon#read 5, iclass 4, count 0 2006.189.07:31:08.77#ibcon#about to read 6, iclass 4, count 0 2006.189.07:31:08.77#ibcon#read 6, iclass 4, count 0 2006.189.07:31:08.77#ibcon#end of sib2, iclass 4, count 0 2006.189.07:31:08.77#ibcon#*after write, iclass 4, count 0 2006.189.07:31:08.77#ibcon#*before return 0, iclass 4, count 0 2006.189.07:31:08.77#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:08.77#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:08.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:31:08.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:31:08.77$vc4f8/valo=6,772.99 2006.189.07:31:08.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:31:08.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:31:08.77#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:08.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:08.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:08.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:08.77#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:31:08.77#ibcon#first serial, iclass 6, count 0 2006.189.07:31:08.77#ibcon#enter sib2, iclass 6, count 0 2006.189.07:31:08.77#ibcon#flushed, iclass 6, count 0 2006.189.07:31:08.77#ibcon#about to write, iclass 6, count 0 2006.189.07:31:08.77#ibcon#wrote, iclass 6, count 0 2006.189.07:31:08.77#ibcon#about to read 3, iclass 6, count 0 2006.189.07:31:08.78#ibcon#read 3, iclass 6, count 0 2006.189.07:31:08.78#ibcon#about to read 4, iclass 6, count 0 2006.189.07:31:08.78#ibcon#read 4, iclass 6, count 0 2006.189.07:31:08.78#ibcon#about to read 5, iclass 6, count 0 2006.189.07:31:08.79#ibcon#read 5, iclass 6, count 0 2006.189.07:31:08.79#ibcon#about to read 6, iclass 6, count 0 2006.189.07:31:08.79#ibcon#read 6, iclass 6, count 0 2006.189.07:31:08.79#ibcon#end of sib2, iclass 6, count 0 2006.189.07:31:08.79#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:31:08.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:31:08.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:31:08.79#ibcon#*before write, iclass 6, count 0 2006.189.07:31:08.79#ibcon#enter sib2, iclass 6, count 0 2006.189.07:31:08.79#ibcon#flushed, iclass 6, count 0 2006.189.07:31:08.79#ibcon#about to write, iclass 6, count 0 2006.189.07:31:08.79#ibcon#wrote, iclass 6, count 0 2006.189.07:31:08.79#ibcon#about to read 3, iclass 6, count 0 2006.189.07:31:08.82#ibcon#read 3, iclass 6, count 0 2006.189.07:31:08.82#ibcon#about to read 4, iclass 6, count 0 2006.189.07:31:08.82#ibcon#read 4, iclass 6, count 0 2006.189.07:31:08.83#ibcon#about to read 5, iclass 6, count 0 2006.189.07:31:08.83#ibcon#read 5, iclass 6, count 0 2006.189.07:31:08.83#ibcon#about to read 6, iclass 6, count 0 2006.189.07:31:08.83#ibcon#read 6, iclass 6, count 0 2006.189.07:31:08.83#ibcon#end of sib2, iclass 6, count 0 2006.189.07:31:08.83#ibcon#*after write, iclass 6, count 0 2006.189.07:31:08.83#ibcon#*before return 0, iclass 6, count 0 2006.189.07:31:08.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:08.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:08.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:31:08.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:31:08.83$vc4f8/va=6,6 2006.189.07:31:08.83#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.07:31:08.83#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.07:31:08.83#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:08.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:31:08.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:31:08.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:31:08.88#ibcon#enter wrdev, iclass 10, count 2 2006.189.07:31:08.88#ibcon#first serial, iclass 10, count 2 2006.189.07:31:08.88#ibcon#enter sib2, iclass 10, count 2 2006.189.07:31:08.89#ibcon#flushed, iclass 10, count 2 2006.189.07:31:08.89#ibcon#about to write, iclass 10, count 2 2006.189.07:31:08.89#ibcon#wrote, iclass 10, count 2 2006.189.07:31:08.89#ibcon#about to read 3, iclass 10, count 2 2006.189.07:31:08.90#ibcon#read 3, iclass 10, count 2 2006.189.07:31:08.90#ibcon#about to read 4, iclass 10, count 2 2006.189.07:31:08.90#ibcon#read 4, iclass 10, count 2 2006.189.07:31:08.91#ibcon#about to read 5, iclass 10, count 2 2006.189.07:31:08.91#ibcon#read 5, iclass 10, count 2 2006.189.07:31:08.91#ibcon#about to read 6, iclass 10, count 2 2006.189.07:31:08.91#ibcon#read 6, iclass 10, count 2 2006.189.07:31:08.91#ibcon#end of sib2, iclass 10, count 2 2006.189.07:31:08.91#ibcon#*mode == 0, iclass 10, count 2 2006.189.07:31:08.91#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.07:31:08.91#ibcon#[25=AT06-06\r\n] 2006.189.07:31:08.91#ibcon#*before write, iclass 10, count 2 2006.189.07:31:08.91#ibcon#enter sib2, iclass 10, count 2 2006.189.07:31:08.91#ibcon#flushed, iclass 10, count 2 2006.189.07:31:08.91#ibcon#about to write, iclass 10, count 2 2006.189.07:31:08.91#ibcon#wrote, iclass 10, count 2 2006.189.07:31:08.91#ibcon#about to read 3, iclass 10, count 2 2006.189.07:31:08.93#ibcon#read 3, iclass 10, count 2 2006.189.07:31:08.93#ibcon#about to read 4, iclass 10, count 2 2006.189.07:31:08.93#ibcon#read 4, iclass 10, count 2 2006.189.07:31:08.94#ibcon#about to read 5, iclass 10, count 2 2006.189.07:31:08.94#ibcon#read 5, iclass 10, count 2 2006.189.07:31:08.94#ibcon#about to read 6, iclass 10, count 2 2006.189.07:31:08.94#ibcon#read 6, iclass 10, count 2 2006.189.07:31:08.94#ibcon#end of sib2, iclass 10, count 2 2006.189.07:31:08.94#ibcon#*after write, iclass 10, count 2 2006.189.07:31:08.94#ibcon#*before return 0, iclass 10, count 2 2006.189.07:31:08.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:31:08.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:31:08.94#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.07:31:08.94#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:08.94#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:31:09.05#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:31:09.05#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:31:09.05#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:31:09.05#ibcon#first serial, iclass 10, count 0 2006.189.07:31:09.05#ibcon#enter sib2, iclass 10, count 0 2006.189.07:31:09.06#ibcon#flushed, iclass 10, count 0 2006.189.07:31:09.06#ibcon#about to write, iclass 10, count 0 2006.189.07:31:09.06#ibcon#wrote, iclass 10, count 0 2006.189.07:31:09.06#ibcon#about to read 3, iclass 10, count 0 2006.189.07:31:09.07#ibcon#read 3, iclass 10, count 0 2006.189.07:31:09.07#ibcon#about to read 4, iclass 10, count 0 2006.189.07:31:09.07#ibcon#read 4, iclass 10, count 0 2006.189.07:31:09.08#ibcon#about to read 5, iclass 10, count 0 2006.189.07:31:09.08#ibcon#read 5, iclass 10, count 0 2006.189.07:31:09.08#ibcon#about to read 6, iclass 10, count 0 2006.189.07:31:09.08#ibcon#read 6, iclass 10, count 0 2006.189.07:31:09.08#ibcon#end of sib2, iclass 10, count 0 2006.189.07:31:09.08#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:31:09.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:31:09.08#ibcon#[25=USB\r\n] 2006.189.07:31:09.08#ibcon#*before write, iclass 10, count 0 2006.189.07:31:09.08#ibcon#enter sib2, iclass 10, count 0 2006.189.07:31:09.08#ibcon#flushed, iclass 10, count 0 2006.189.07:31:09.08#ibcon#about to write, iclass 10, count 0 2006.189.07:31:09.08#ibcon#wrote, iclass 10, count 0 2006.189.07:31:09.08#ibcon#about to read 3, iclass 10, count 0 2006.189.07:31:09.10#ibcon#read 3, iclass 10, count 0 2006.189.07:31:09.10#ibcon#about to read 4, iclass 10, count 0 2006.189.07:31:09.10#ibcon#read 4, iclass 10, count 0 2006.189.07:31:09.11#ibcon#about to read 5, iclass 10, count 0 2006.189.07:31:09.11#ibcon#read 5, iclass 10, count 0 2006.189.07:31:09.11#ibcon#about to read 6, iclass 10, count 0 2006.189.07:31:09.11#ibcon#read 6, iclass 10, count 0 2006.189.07:31:09.11#ibcon#end of sib2, iclass 10, count 0 2006.189.07:31:09.11#ibcon#*after write, iclass 10, count 0 2006.189.07:31:09.11#ibcon#*before return 0, iclass 10, count 0 2006.189.07:31:09.11#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:31:09.11#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:31:09.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:31:09.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:31:09.11$vc4f8/valo=7,832.99 2006.189.07:31:09.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.07:31:09.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.07:31:09.11#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:09.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:31:09.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:31:09.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:31:09.11#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:31:09.11#ibcon#first serial, iclass 12, count 0 2006.189.07:31:09.11#ibcon#enter sib2, iclass 12, count 0 2006.189.07:31:09.11#ibcon#flushed, iclass 12, count 0 2006.189.07:31:09.11#ibcon#about to write, iclass 12, count 0 2006.189.07:31:09.11#ibcon#wrote, iclass 12, count 0 2006.189.07:31:09.11#ibcon#about to read 3, iclass 12, count 0 2006.189.07:31:09.12#ibcon#read 3, iclass 12, count 0 2006.189.07:31:09.12#ibcon#about to read 4, iclass 12, count 0 2006.189.07:31:09.12#ibcon#read 4, iclass 12, count 0 2006.189.07:31:09.13#ibcon#about to read 5, iclass 12, count 0 2006.189.07:31:09.13#ibcon#read 5, iclass 12, count 0 2006.189.07:31:09.13#ibcon#about to read 6, iclass 12, count 0 2006.189.07:31:09.13#ibcon#read 6, iclass 12, count 0 2006.189.07:31:09.13#ibcon#end of sib2, iclass 12, count 0 2006.189.07:31:09.13#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:31:09.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:31:09.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:31:09.13#ibcon#*before write, iclass 12, count 0 2006.189.07:31:09.13#ibcon#enter sib2, iclass 12, count 0 2006.189.07:31:09.13#ibcon#flushed, iclass 12, count 0 2006.189.07:31:09.13#ibcon#about to write, iclass 12, count 0 2006.189.07:31:09.13#ibcon#wrote, iclass 12, count 0 2006.189.07:31:09.13#ibcon#about to read 3, iclass 12, count 0 2006.189.07:31:09.16#ibcon#read 3, iclass 12, count 0 2006.189.07:31:09.16#ibcon#about to read 4, iclass 12, count 0 2006.189.07:31:09.16#ibcon#read 4, iclass 12, count 0 2006.189.07:31:09.17#ibcon#about to read 5, iclass 12, count 0 2006.189.07:31:09.17#ibcon#read 5, iclass 12, count 0 2006.189.07:31:09.17#ibcon#about to read 6, iclass 12, count 0 2006.189.07:31:09.17#ibcon#read 6, iclass 12, count 0 2006.189.07:31:09.17#ibcon#end of sib2, iclass 12, count 0 2006.189.07:31:09.17#ibcon#*after write, iclass 12, count 0 2006.189.07:31:09.17#ibcon#*before return 0, iclass 12, count 0 2006.189.07:31:09.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:31:09.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:31:09.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:31:09.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:31:09.17$vc4f8/va=7,6 2006.189.07:31:09.17#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.07:31:09.17#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.07:31:09.17#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:09.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:31:09.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:31:09.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:31:09.23#ibcon#enter wrdev, iclass 14, count 2 2006.189.07:31:09.23#ibcon#first serial, iclass 14, count 2 2006.189.07:31:09.23#ibcon#enter sib2, iclass 14, count 2 2006.189.07:31:09.23#ibcon#flushed, iclass 14, count 2 2006.189.07:31:09.23#ibcon#about to write, iclass 14, count 2 2006.189.07:31:09.23#ibcon#wrote, iclass 14, count 2 2006.189.07:31:09.23#ibcon#about to read 3, iclass 14, count 2 2006.189.07:31:09.24#ibcon#read 3, iclass 14, count 2 2006.189.07:31:09.24#ibcon#about to read 4, iclass 14, count 2 2006.189.07:31:09.24#ibcon#read 4, iclass 14, count 2 2006.189.07:31:09.25#ibcon#about to read 5, iclass 14, count 2 2006.189.07:31:09.25#ibcon#read 5, iclass 14, count 2 2006.189.07:31:09.25#ibcon#about to read 6, iclass 14, count 2 2006.189.07:31:09.25#ibcon#read 6, iclass 14, count 2 2006.189.07:31:09.25#ibcon#end of sib2, iclass 14, count 2 2006.189.07:31:09.25#ibcon#*mode == 0, iclass 14, count 2 2006.189.07:31:09.25#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.07:31:09.25#ibcon#[25=AT07-06\r\n] 2006.189.07:31:09.25#ibcon#*before write, iclass 14, count 2 2006.189.07:31:09.25#ibcon#enter sib2, iclass 14, count 2 2006.189.07:31:09.25#ibcon#flushed, iclass 14, count 2 2006.189.07:31:09.25#ibcon#about to write, iclass 14, count 2 2006.189.07:31:09.25#ibcon#wrote, iclass 14, count 2 2006.189.07:31:09.25#ibcon#about to read 3, iclass 14, count 2 2006.189.07:31:09.27#ibcon#read 3, iclass 14, count 2 2006.189.07:31:09.28#ibcon#about to read 4, iclass 14, count 2 2006.189.07:31:09.28#ibcon#read 4, iclass 14, count 2 2006.189.07:31:09.28#ibcon#about to read 5, iclass 14, count 2 2006.189.07:31:09.28#ibcon#read 5, iclass 14, count 2 2006.189.07:31:09.28#ibcon#about to read 6, iclass 14, count 2 2006.189.07:31:09.28#ibcon#read 6, iclass 14, count 2 2006.189.07:31:09.28#ibcon#end of sib2, iclass 14, count 2 2006.189.07:31:09.28#ibcon#*after write, iclass 14, count 2 2006.189.07:31:09.28#ibcon#*before return 0, iclass 14, count 2 2006.189.07:31:09.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:31:09.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:31:09.28#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.07:31:09.28#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:09.28#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:31:09.39#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:31:09.39#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:31:09.39#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:31:09.39#ibcon#first serial, iclass 14, count 0 2006.189.07:31:09.39#ibcon#enter sib2, iclass 14, count 0 2006.189.07:31:09.40#ibcon#flushed, iclass 14, count 0 2006.189.07:31:09.40#ibcon#about to write, iclass 14, count 0 2006.189.07:31:09.40#ibcon#wrote, iclass 14, count 0 2006.189.07:31:09.40#ibcon#about to read 3, iclass 14, count 0 2006.189.07:31:09.41#ibcon#read 3, iclass 14, count 0 2006.189.07:31:09.41#ibcon#about to read 4, iclass 14, count 0 2006.189.07:31:09.41#ibcon#read 4, iclass 14, count 0 2006.189.07:31:09.42#ibcon#about to read 5, iclass 14, count 0 2006.189.07:31:09.42#ibcon#read 5, iclass 14, count 0 2006.189.07:31:09.42#ibcon#about to read 6, iclass 14, count 0 2006.189.07:31:09.42#ibcon#read 6, iclass 14, count 0 2006.189.07:31:09.42#ibcon#end of sib2, iclass 14, count 0 2006.189.07:31:09.42#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:31:09.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:31:09.42#ibcon#[25=USB\r\n] 2006.189.07:31:09.42#ibcon#*before write, iclass 14, count 0 2006.189.07:31:09.42#ibcon#enter sib2, iclass 14, count 0 2006.189.07:31:09.42#ibcon#flushed, iclass 14, count 0 2006.189.07:31:09.42#ibcon#about to write, iclass 14, count 0 2006.189.07:31:09.42#ibcon#wrote, iclass 14, count 0 2006.189.07:31:09.42#ibcon#about to read 3, iclass 14, count 0 2006.189.07:31:09.44#ibcon#read 3, iclass 14, count 0 2006.189.07:31:09.44#ibcon#about to read 4, iclass 14, count 0 2006.189.07:31:09.44#ibcon#read 4, iclass 14, count 0 2006.189.07:31:09.45#ibcon#about to read 5, iclass 14, count 0 2006.189.07:31:09.45#ibcon#read 5, iclass 14, count 0 2006.189.07:31:09.45#ibcon#about to read 6, iclass 14, count 0 2006.189.07:31:09.45#ibcon#read 6, iclass 14, count 0 2006.189.07:31:09.45#ibcon#end of sib2, iclass 14, count 0 2006.189.07:31:09.45#ibcon#*after write, iclass 14, count 0 2006.189.07:31:09.45#ibcon#*before return 0, iclass 14, count 0 2006.189.07:31:09.45#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:31:09.45#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:31:09.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:31:09.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:31:09.45$vc4f8/valo=8,852.99 2006.189.07:31:09.45#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.07:31:09.45#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.07:31:09.45#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:09.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:31:09.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:31:09.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:31:09.45#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:31:09.45#ibcon#first serial, iclass 16, count 0 2006.189.07:31:09.45#ibcon#enter sib2, iclass 16, count 0 2006.189.07:31:09.45#ibcon#flushed, iclass 16, count 0 2006.189.07:31:09.45#ibcon#about to write, iclass 16, count 0 2006.189.07:31:09.45#ibcon#wrote, iclass 16, count 0 2006.189.07:31:09.45#ibcon#about to read 3, iclass 16, count 0 2006.189.07:31:09.46#ibcon#read 3, iclass 16, count 0 2006.189.07:31:09.46#ibcon#about to read 4, iclass 16, count 0 2006.189.07:31:09.46#ibcon#read 4, iclass 16, count 0 2006.189.07:31:09.46#ibcon#about to read 5, iclass 16, count 0 2006.189.07:31:09.47#ibcon#read 5, iclass 16, count 0 2006.189.07:31:09.47#ibcon#about to read 6, iclass 16, count 0 2006.189.07:31:09.47#ibcon#read 6, iclass 16, count 0 2006.189.07:31:09.47#ibcon#end of sib2, iclass 16, count 0 2006.189.07:31:09.47#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:31:09.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:31:09.47#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:31:09.47#ibcon#*before write, iclass 16, count 0 2006.189.07:31:09.47#ibcon#enter sib2, iclass 16, count 0 2006.189.07:31:09.47#ibcon#flushed, iclass 16, count 0 2006.189.07:31:09.47#ibcon#about to write, iclass 16, count 0 2006.189.07:31:09.47#ibcon#wrote, iclass 16, count 0 2006.189.07:31:09.47#ibcon#about to read 3, iclass 16, count 0 2006.189.07:31:09.51#ibcon#read 3, iclass 16, count 0 2006.189.07:31:09.51#ibcon#about to read 4, iclass 16, count 0 2006.189.07:31:09.51#ibcon#read 4, iclass 16, count 0 2006.189.07:31:09.51#ibcon#about to read 5, iclass 16, count 0 2006.189.07:31:09.51#ibcon#read 5, iclass 16, count 0 2006.189.07:31:09.51#ibcon#about to read 6, iclass 16, count 0 2006.189.07:31:09.51#ibcon#read 6, iclass 16, count 0 2006.189.07:31:09.51#ibcon#end of sib2, iclass 16, count 0 2006.189.07:31:09.51#ibcon#*after write, iclass 16, count 0 2006.189.07:31:09.51#ibcon#*before return 0, iclass 16, count 0 2006.189.07:31:09.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:31:09.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:31:09.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:31:09.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:31:09.51$vc4f8/va=8,6 2006.189.07:31:09.51#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.07:31:09.51#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.07:31:09.51#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:09.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:31:09.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:31:09.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:31:09.56#ibcon#enter wrdev, iclass 18, count 2 2006.189.07:31:09.56#ibcon#first serial, iclass 18, count 2 2006.189.07:31:09.56#ibcon#enter sib2, iclass 18, count 2 2006.189.07:31:09.57#ibcon#flushed, iclass 18, count 2 2006.189.07:31:09.57#ibcon#about to write, iclass 18, count 2 2006.189.07:31:09.57#ibcon#wrote, iclass 18, count 2 2006.189.07:31:09.57#ibcon#about to read 3, iclass 18, count 2 2006.189.07:31:09.58#ibcon#read 3, iclass 18, count 2 2006.189.07:31:09.58#ibcon#about to read 4, iclass 18, count 2 2006.189.07:31:09.58#ibcon#read 4, iclass 18, count 2 2006.189.07:31:09.59#ibcon#about to read 5, iclass 18, count 2 2006.189.07:31:09.59#ibcon#read 5, iclass 18, count 2 2006.189.07:31:09.59#ibcon#about to read 6, iclass 18, count 2 2006.189.07:31:09.59#ibcon#read 6, iclass 18, count 2 2006.189.07:31:09.59#ibcon#end of sib2, iclass 18, count 2 2006.189.07:31:09.59#ibcon#*mode == 0, iclass 18, count 2 2006.189.07:31:09.59#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.07:31:09.59#ibcon#[25=AT08-06\r\n] 2006.189.07:31:09.59#ibcon#*before write, iclass 18, count 2 2006.189.07:31:09.59#ibcon#enter sib2, iclass 18, count 2 2006.189.07:31:09.59#ibcon#flushed, iclass 18, count 2 2006.189.07:31:09.59#ibcon#about to write, iclass 18, count 2 2006.189.07:31:09.59#ibcon#wrote, iclass 18, count 2 2006.189.07:31:09.59#ibcon#about to read 3, iclass 18, count 2 2006.189.07:31:09.61#ibcon#read 3, iclass 18, count 2 2006.189.07:31:09.61#ibcon#about to read 4, iclass 18, count 2 2006.189.07:31:09.61#ibcon#read 4, iclass 18, count 2 2006.189.07:31:09.61#ibcon#about to read 5, iclass 18, count 2 2006.189.07:31:09.62#ibcon#read 5, iclass 18, count 2 2006.189.07:31:09.62#ibcon#about to read 6, iclass 18, count 2 2006.189.07:31:09.62#ibcon#read 6, iclass 18, count 2 2006.189.07:31:09.62#ibcon#end of sib2, iclass 18, count 2 2006.189.07:31:09.62#ibcon#*after write, iclass 18, count 2 2006.189.07:31:09.62#ibcon#*before return 0, iclass 18, count 2 2006.189.07:31:09.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:31:09.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:31:09.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.07:31:09.62#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:09.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:31:09.73#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:31:09.73#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:31:09.73#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:31:09.73#ibcon#first serial, iclass 18, count 0 2006.189.07:31:09.73#ibcon#enter sib2, iclass 18, count 0 2006.189.07:31:09.74#ibcon#flushed, iclass 18, count 0 2006.189.07:31:09.74#ibcon#about to write, iclass 18, count 0 2006.189.07:31:09.74#ibcon#wrote, iclass 18, count 0 2006.189.07:31:09.74#ibcon#about to read 3, iclass 18, count 0 2006.189.07:31:09.75#ibcon#read 3, iclass 18, count 0 2006.189.07:31:09.75#ibcon#about to read 4, iclass 18, count 0 2006.189.07:31:09.75#ibcon#read 4, iclass 18, count 0 2006.189.07:31:09.76#ibcon#about to read 5, iclass 18, count 0 2006.189.07:31:09.76#ibcon#read 5, iclass 18, count 0 2006.189.07:31:09.76#ibcon#about to read 6, iclass 18, count 0 2006.189.07:31:09.76#ibcon#read 6, iclass 18, count 0 2006.189.07:31:09.76#ibcon#end of sib2, iclass 18, count 0 2006.189.07:31:09.76#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:31:09.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:31:09.76#ibcon#[25=USB\r\n] 2006.189.07:31:09.76#ibcon#*before write, iclass 18, count 0 2006.189.07:31:09.76#ibcon#enter sib2, iclass 18, count 0 2006.189.07:31:09.76#ibcon#flushed, iclass 18, count 0 2006.189.07:31:09.76#ibcon#about to write, iclass 18, count 0 2006.189.07:31:09.76#ibcon#wrote, iclass 18, count 0 2006.189.07:31:09.76#ibcon#about to read 3, iclass 18, count 0 2006.189.07:31:09.78#ibcon#read 3, iclass 18, count 0 2006.189.07:31:09.78#ibcon#about to read 4, iclass 18, count 0 2006.189.07:31:09.78#ibcon#read 4, iclass 18, count 0 2006.189.07:31:09.79#ibcon#about to read 5, iclass 18, count 0 2006.189.07:31:09.79#ibcon#read 5, iclass 18, count 0 2006.189.07:31:09.79#ibcon#about to read 6, iclass 18, count 0 2006.189.07:31:09.79#ibcon#read 6, iclass 18, count 0 2006.189.07:31:09.79#ibcon#end of sib2, iclass 18, count 0 2006.189.07:31:09.79#ibcon#*after write, iclass 18, count 0 2006.189.07:31:09.79#ibcon#*before return 0, iclass 18, count 0 2006.189.07:31:09.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:31:09.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:31:09.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:31:09.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:31:09.79$vc4f8/vblo=1,632.99 2006.189.07:31:09.79#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.07:31:09.79#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.07:31:09.79#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:09.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:31:09.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:31:09.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:31:09.79#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:31:09.79#ibcon#first serial, iclass 20, count 0 2006.189.07:31:09.79#ibcon#enter sib2, iclass 20, count 0 2006.189.07:31:09.79#ibcon#flushed, iclass 20, count 0 2006.189.07:31:09.79#ibcon#about to write, iclass 20, count 0 2006.189.07:31:09.79#ibcon#wrote, iclass 20, count 0 2006.189.07:31:09.79#ibcon#about to read 3, iclass 20, count 0 2006.189.07:31:09.80#ibcon#read 3, iclass 20, count 0 2006.189.07:31:09.80#ibcon#about to read 4, iclass 20, count 0 2006.189.07:31:09.80#ibcon#read 4, iclass 20, count 0 2006.189.07:31:09.80#ibcon#about to read 5, iclass 20, count 0 2006.189.07:31:09.81#ibcon#read 5, iclass 20, count 0 2006.189.07:31:09.81#ibcon#about to read 6, iclass 20, count 0 2006.189.07:31:09.81#ibcon#read 6, iclass 20, count 0 2006.189.07:31:09.81#ibcon#end of sib2, iclass 20, count 0 2006.189.07:31:09.81#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:31:09.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:31:09.81#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:31:09.81#ibcon#*before write, iclass 20, count 0 2006.189.07:31:09.81#ibcon#enter sib2, iclass 20, count 0 2006.189.07:31:09.81#ibcon#flushed, iclass 20, count 0 2006.189.07:31:09.81#ibcon#about to write, iclass 20, count 0 2006.189.07:31:09.81#ibcon#wrote, iclass 20, count 0 2006.189.07:31:09.81#ibcon#about to read 3, iclass 20, count 0 2006.189.07:31:09.84#ibcon#read 3, iclass 20, count 0 2006.189.07:31:09.84#ibcon#about to read 4, iclass 20, count 0 2006.189.07:31:09.84#ibcon#read 4, iclass 20, count 0 2006.189.07:31:09.84#ibcon#about to read 5, iclass 20, count 0 2006.189.07:31:09.85#ibcon#read 5, iclass 20, count 0 2006.189.07:31:09.85#ibcon#about to read 6, iclass 20, count 0 2006.189.07:31:09.85#ibcon#read 6, iclass 20, count 0 2006.189.07:31:09.85#ibcon#end of sib2, iclass 20, count 0 2006.189.07:31:09.85#ibcon#*after write, iclass 20, count 0 2006.189.07:31:09.85#ibcon#*before return 0, iclass 20, count 0 2006.189.07:31:09.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:31:09.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:31:09.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:31:09.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:31:09.85$vc4f8/vb=1,4 2006.189.07:31:09.85#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.07:31:09.85#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.07:31:09.85#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:09.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:31:09.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:31:09.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:31:09.85#ibcon#enter wrdev, iclass 22, count 2 2006.189.07:31:09.85#ibcon#first serial, iclass 22, count 2 2006.189.07:31:09.85#ibcon#enter sib2, iclass 22, count 2 2006.189.07:31:09.85#ibcon#flushed, iclass 22, count 2 2006.189.07:31:09.85#ibcon#about to write, iclass 22, count 2 2006.189.07:31:09.85#ibcon#wrote, iclass 22, count 2 2006.189.07:31:09.85#ibcon#about to read 3, iclass 22, count 2 2006.189.07:31:09.86#ibcon#read 3, iclass 22, count 2 2006.189.07:31:09.87#ibcon#about to read 4, iclass 22, count 2 2006.189.07:31:09.87#ibcon#read 4, iclass 22, count 2 2006.189.07:31:09.87#ibcon#about to read 5, iclass 22, count 2 2006.189.07:31:09.87#ibcon#read 5, iclass 22, count 2 2006.189.07:31:09.87#ibcon#about to read 6, iclass 22, count 2 2006.189.07:31:09.87#ibcon#read 6, iclass 22, count 2 2006.189.07:31:09.87#ibcon#end of sib2, iclass 22, count 2 2006.189.07:31:09.87#ibcon#*mode == 0, iclass 22, count 2 2006.189.07:31:09.87#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.07:31:09.87#ibcon#[27=AT01-04\r\n] 2006.189.07:31:09.87#ibcon#*before write, iclass 22, count 2 2006.189.07:31:09.87#ibcon#enter sib2, iclass 22, count 2 2006.189.07:31:09.87#ibcon#flushed, iclass 22, count 2 2006.189.07:31:09.87#ibcon#about to write, iclass 22, count 2 2006.189.07:31:09.87#ibcon#wrote, iclass 22, count 2 2006.189.07:31:09.87#ibcon#about to read 3, iclass 22, count 2 2006.189.07:31:09.89#ibcon#read 3, iclass 22, count 2 2006.189.07:31:09.89#ibcon#about to read 4, iclass 22, count 2 2006.189.07:31:09.89#ibcon#read 4, iclass 22, count 2 2006.189.07:31:09.89#ibcon#about to read 5, iclass 22, count 2 2006.189.07:31:09.90#ibcon#read 5, iclass 22, count 2 2006.189.07:31:09.90#ibcon#about to read 6, iclass 22, count 2 2006.189.07:31:09.90#ibcon#read 6, iclass 22, count 2 2006.189.07:31:09.90#ibcon#end of sib2, iclass 22, count 2 2006.189.07:31:09.90#ibcon#*after write, iclass 22, count 2 2006.189.07:31:09.90#ibcon#*before return 0, iclass 22, count 2 2006.189.07:31:09.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:31:09.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:31:09.90#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.07:31:09.90#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:09.90#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:31:10.01#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:31:10.01#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:31:10.01#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:31:10.01#ibcon#first serial, iclass 22, count 0 2006.189.07:31:10.01#ibcon#enter sib2, iclass 22, count 0 2006.189.07:31:10.02#ibcon#flushed, iclass 22, count 0 2006.189.07:31:10.02#ibcon#about to write, iclass 22, count 0 2006.189.07:31:10.02#ibcon#wrote, iclass 22, count 0 2006.189.07:31:10.02#ibcon#about to read 3, iclass 22, count 0 2006.189.07:31:10.03#ibcon#read 3, iclass 22, count 0 2006.189.07:31:10.03#ibcon#about to read 4, iclass 22, count 0 2006.189.07:31:10.03#ibcon#read 4, iclass 22, count 0 2006.189.07:31:10.03#ibcon#about to read 5, iclass 22, count 0 2006.189.07:31:10.04#ibcon#read 5, iclass 22, count 0 2006.189.07:31:10.04#ibcon#about to read 6, iclass 22, count 0 2006.189.07:31:10.04#ibcon#read 6, iclass 22, count 0 2006.189.07:31:10.04#ibcon#end of sib2, iclass 22, count 0 2006.189.07:31:10.04#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:31:10.04#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:31:10.04#ibcon#[27=USB\r\n] 2006.189.07:31:10.04#ibcon#*before write, iclass 22, count 0 2006.189.07:31:10.04#ibcon#enter sib2, iclass 22, count 0 2006.189.07:31:10.04#ibcon#flushed, iclass 22, count 0 2006.189.07:31:10.04#ibcon#about to write, iclass 22, count 0 2006.189.07:31:10.04#ibcon#wrote, iclass 22, count 0 2006.189.07:31:10.04#ibcon#about to read 3, iclass 22, count 0 2006.189.07:31:10.06#ibcon#read 3, iclass 22, count 0 2006.189.07:31:10.06#ibcon#about to read 4, iclass 22, count 0 2006.189.07:31:10.07#ibcon#read 4, iclass 22, count 0 2006.189.07:31:10.07#ibcon#about to read 5, iclass 22, count 0 2006.189.07:31:10.07#ibcon#read 5, iclass 22, count 0 2006.189.07:31:10.07#ibcon#about to read 6, iclass 22, count 0 2006.189.07:31:10.07#ibcon#read 6, iclass 22, count 0 2006.189.07:31:10.07#ibcon#end of sib2, iclass 22, count 0 2006.189.07:31:10.07#ibcon#*after write, iclass 22, count 0 2006.189.07:31:10.07#ibcon#*before return 0, iclass 22, count 0 2006.189.07:31:10.07#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:31:10.07#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:31:10.07#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:31:10.07#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:31:10.07$vc4f8/vblo=2,640.99 2006.189.07:31:10.07#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.07:31:10.07#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.07:31:10.07#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:10.07#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:10.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:10.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:10.07#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:31:10.07#ibcon#first serial, iclass 24, count 0 2006.189.07:31:10.07#ibcon#enter sib2, iclass 24, count 0 2006.189.07:31:10.07#ibcon#flushed, iclass 24, count 0 2006.189.07:31:10.07#ibcon#about to write, iclass 24, count 0 2006.189.07:31:10.07#ibcon#wrote, iclass 24, count 0 2006.189.07:31:10.07#ibcon#about to read 3, iclass 24, count 0 2006.189.07:31:10.08#ibcon#read 3, iclass 24, count 0 2006.189.07:31:10.08#ibcon#about to read 4, iclass 24, count 0 2006.189.07:31:10.08#ibcon#read 4, iclass 24, count 0 2006.189.07:31:10.09#ibcon#about to read 5, iclass 24, count 0 2006.189.07:31:10.09#ibcon#read 5, iclass 24, count 0 2006.189.07:31:10.09#ibcon#about to read 6, iclass 24, count 0 2006.189.07:31:10.09#ibcon#read 6, iclass 24, count 0 2006.189.07:31:10.09#ibcon#end of sib2, iclass 24, count 0 2006.189.07:31:10.09#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:31:10.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:31:10.09#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:31:10.09#ibcon#*before write, iclass 24, count 0 2006.189.07:31:10.09#ibcon#enter sib2, iclass 24, count 0 2006.189.07:31:10.09#ibcon#flushed, iclass 24, count 0 2006.189.07:31:10.09#ibcon#about to write, iclass 24, count 0 2006.189.07:31:10.09#ibcon#wrote, iclass 24, count 0 2006.189.07:31:10.09#ibcon#about to read 3, iclass 24, count 0 2006.189.07:31:10.12#ibcon#read 3, iclass 24, count 0 2006.189.07:31:10.12#ibcon#about to read 4, iclass 24, count 0 2006.189.07:31:10.12#ibcon#read 4, iclass 24, count 0 2006.189.07:31:10.12#ibcon#about to read 5, iclass 24, count 0 2006.189.07:31:10.13#ibcon#read 5, iclass 24, count 0 2006.189.07:31:10.13#ibcon#about to read 6, iclass 24, count 0 2006.189.07:31:10.13#ibcon#read 6, iclass 24, count 0 2006.189.07:31:10.13#ibcon#end of sib2, iclass 24, count 0 2006.189.07:31:10.13#ibcon#*after write, iclass 24, count 0 2006.189.07:31:10.13#ibcon#*before return 0, iclass 24, count 0 2006.189.07:31:10.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:10.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:31:10.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:31:10.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:31:10.13$vc4f8/vb=2,4 2006.189.07:31:10.13#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.07:31:10.13#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.07:31:10.13#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:10.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:10.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:10.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:10.18#ibcon#enter wrdev, iclass 26, count 2 2006.189.07:31:10.18#ibcon#first serial, iclass 26, count 2 2006.189.07:31:10.18#ibcon#enter sib2, iclass 26, count 2 2006.189.07:31:10.19#ibcon#flushed, iclass 26, count 2 2006.189.07:31:10.19#ibcon#about to write, iclass 26, count 2 2006.189.07:31:10.19#ibcon#wrote, iclass 26, count 2 2006.189.07:31:10.19#ibcon#about to read 3, iclass 26, count 2 2006.189.07:31:10.20#ibcon#read 3, iclass 26, count 2 2006.189.07:31:10.20#ibcon#about to read 4, iclass 26, count 2 2006.189.07:31:10.20#ibcon#read 4, iclass 26, count 2 2006.189.07:31:10.21#ibcon#about to read 5, iclass 26, count 2 2006.189.07:31:10.21#ibcon#read 5, iclass 26, count 2 2006.189.07:31:10.21#ibcon#about to read 6, iclass 26, count 2 2006.189.07:31:10.21#ibcon#read 6, iclass 26, count 2 2006.189.07:31:10.21#ibcon#end of sib2, iclass 26, count 2 2006.189.07:31:10.21#ibcon#*mode == 0, iclass 26, count 2 2006.189.07:31:10.21#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.07:31:10.21#ibcon#[27=AT02-04\r\n] 2006.189.07:31:10.21#ibcon#*before write, iclass 26, count 2 2006.189.07:31:10.21#ibcon#enter sib2, iclass 26, count 2 2006.189.07:31:10.21#ibcon#flushed, iclass 26, count 2 2006.189.07:31:10.21#ibcon#about to write, iclass 26, count 2 2006.189.07:31:10.21#ibcon#wrote, iclass 26, count 2 2006.189.07:31:10.21#ibcon#about to read 3, iclass 26, count 2 2006.189.07:31:10.24#ibcon#read 3, iclass 26, count 2 2006.189.07:31:10.24#ibcon#about to read 4, iclass 26, count 2 2006.189.07:31:10.24#ibcon#read 4, iclass 26, count 2 2006.189.07:31:10.24#ibcon#about to read 5, iclass 26, count 2 2006.189.07:31:10.24#ibcon#read 5, iclass 26, count 2 2006.189.07:31:10.24#ibcon#about to read 6, iclass 26, count 2 2006.189.07:31:10.24#ibcon#read 6, iclass 26, count 2 2006.189.07:31:10.24#ibcon#end of sib2, iclass 26, count 2 2006.189.07:31:10.24#ibcon#*after write, iclass 26, count 2 2006.189.07:31:10.24#ibcon#*before return 0, iclass 26, count 2 2006.189.07:31:10.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:10.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:31:10.24#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.07:31:10.24#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:10.24#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:10.35#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:10.35#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:10.35#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:31:10.35#ibcon#first serial, iclass 26, count 0 2006.189.07:31:10.35#ibcon#enter sib2, iclass 26, count 0 2006.189.07:31:10.36#ibcon#flushed, iclass 26, count 0 2006.189.07:31:10.36#ibcon#about to write, iclass 26, count 0 2006.189.07:31:10.36#ibcon#wrote, iclass 26, count 0 2006.189.07:31:10.36#ibcon#about to read 3, iclass 26, count 0 2006.189.07:31:10.37#ibcon#read 3, iclass 26, count 0 2006.189.07:31:10.37#ibcon#about to read 4, iclass 26, count 0 2006.189.07:31:10.37#ibcon#read 4, iclass 26, count 0 2006.189.07:31:10.37#ibcon#about to read 5, iclass 26, count 0 2006.189.07:31:10.38#ibcon#read 5, iclass 26, count 0 2006.189.07:31:10.38#ibcon#about to read 6, iclass 26, count 0 2006.189.07:31:10.38#ibcon#read 6, iclass 26, count 0 2006.189.07:31:10.38#ibcon#end of sib2, iclass 26, count 0 2006.189.07:31:10.38#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:31:10.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:31:10.38#ibcon#[27=USB\r\n] 2006.189.07:31:10.38#ibcon#*before write, iclass 26, count 0 2006.189.07:31:10.38#ibcon#enter sib2, iclass 26, count 0 2006.189.07:31:10.38#ibcon#flushed, iclass 26, count 0 2006.189.07:31:10.38#ibcon#about to write, iclass 26, count 0 2006.189.07:31:10.38#ibcon#wrote, iclass 26, count 0 2006.189.07:31:10.38#ibcon#about to read 3, iclass 26, count 0 2006.189.07:31:10.40#ibcon#read 3, iclass 26, count 0 2006.189.07:31:10.40#ibcon#about to read 4, iclass 26, count 0 2006.189.07:31:10.40#ibcon#read 4, iclass 26, count 0 2006.189.07:31:10.40#ibcon#about to read 5, iclass 26, count 0 2006.189.07:31:10.41#ibcon#read 5, iclass 26, count 0 2006.189.07:31:10.41#ibcon#about to read 6, iclass 26, count 0 2006.189.07:31:10.41#ibcon#read 6, iclass 26, count 0 2006.189.07:31:10.41#ibcon#end of sib2, iclass 26, count 0 2006.189.07:31:10.41#ibcon#*after write, iclass 26, count 0 2006.189.07:31:10.41#ibcon#*before return 0, iclass 26, count 0 2006.189.07:31:10.41#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:10.41#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:31:10.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:31:10.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:31:10.41$vc4f8/vblo=3,656.99 2006.189.07:31:10.41#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.07:31:10.41#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.07:31:10.41#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:10.41#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:10.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:10.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:10.41#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:31:10.41#ibcon#first serial, iclass 28, count 0 2006.189.07:31:10.41#ibcon#enter sib2, iclass 28, count 0 2006.189.07:31:10.41#ibcon#flushed, iclass 28, count 0 2006.189.07:31:10.41#ibcon#about to write, iclass 28, count 0 2006.189.07:31:10.41#ibcon#wrote, iclass 28, count 0 2006.189.07:31:10.41#ibcon#about to read 3, iclass 28, count 0 2006.189.07:31:10.42#ibcon#read 3, iclass 28, count 0 2006.189.07:31:10.42#ibcon#about to read 4, iclass 28, count 0 2006.189.07:31:10.43#ibcon#read 4, iclass 28, count 0 2006.189.07:31:10.43#ibcon#about to read 5, iclass 28, count 0 2006.189.07:31:10.43#ibcon#read 5, iclass 28, count 0 2006.189.07:31:10.43#ibcon#about to read 6, iclass 28, count 0 2006.189.07:31:10.43#ibcon#read 6, iclass 28, count 0 2006.189.07:31:10.43#ibcon#end of sib2, iclass 28, count 0 2006.189.07:31:10.43#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:31:10.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:31:10.43#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:31:10.43#ibcon#*before write, iclass 28, count 0 2006.189.07:31:10.43#ibcon#enter sib2, iclass 28, count 0 2006.189.07:31:10.43#ibcon#flushed, iclass 28, count 0 2006.189.07:31:10.43#ibcon#about to write, iclass 28, count 0 2006.189.07:31:10.43#ibcon#wrote, iclass 28, count 0 2006.189.07:31:10.43#ibcon#about to read 3, iclass 28, count 0 2006.189.07:31:10.46#ibcon#read 3, iclass 28, count 0 2006.189.07:31:10.46#ibcon#about to read 4, iclass 28, count 0 2006.189.07:31:10.46#ibcon#read 4, iclass 28, count 0 2006.189.07:31:10.46#ibcon#about to read 5, iclass 28, count 0 2006.189.07:31:10.47#ibcon#read 5, iclass 28, count 0 2006.189.07:31:10.47#ibcon#about to read 6, iclass 28, count 0 2006.189.07:31:10.47#ibcon#read 6, iclass 28, count 0 2006.189.07:31:10.47#ibcon#end of sib2, iclass 28, count 0 2006.189.07:31:10.47#ibcon#*after write, iclass 28, count 0 2006.189.07:31:10.47#ibcon#*before return 0, iclass 28, count 0 2006.189.07:31:10.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:10.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:31:10.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:31:10.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:31:10.47$vc4f8/vb=3,4 2006.189.07:31:10.47#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.07:31:10.47#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.07:31:10.47#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:10.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:10.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:10.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:10.52#ibcon#enter wrdev, iclass 30, count 2 2006.189.07:31:10.52#ibcon#first serial, iclass 30, count 2 2006.189.07:31:10.52#ibcon#enter sib2, iclass 30, count 2 2006.189.07:31:10.53#ibcon#flushed, iclass 30, count 2 2006.189.07:31:10.53#ibcon#about to write, iclass 30, count 2 2006.189.07:31:10.53#ibcon#wrote, iclass 30, count 2 2006.189.07:31:10.53#ibcon#about to read 3, iclass 30, count 2 2006.189.07:31:10.54#ibcon#read 3, iclass 30, count 2 2006.189.07:31:10.54#ibcon#about to read 4, iclass 30, count 2 2006.189.07:31:10.54#ibcon#read 4, iclass 30, count 2 2006.189.07:31:10.54#ibcon#about to read 5, iclass 30, count 2 2006.189.07:31:10.55#ibcon#read 5, iclass 30, count 2 2006.189.07:31:10.55#ibcon#about to read 6, iclass 30, count 2 2006.189.07:31:10.55#ibcon#read 6, iclass 30, count 2 2006.189.07:31:10.55#ibcon#end of sib2, iclass 30, count 2 2006.189.07:31:10.55#ibcon#*mode == 0, iclass 30, count 2 2006.189.07:31:10.55#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.07:31:10.55#ibcon#[27=AT03-04\r\n] 2006.189.07:31:10.55#ibcon#*before write, iclass 30, count 2 2006.189.07:31:10.55#ibcon#enter sib2, iclass 30, count 2 2006.189.07:31:10.55#ibcon#flushed, iclass 30, count 2 2006.189.07:31:10.55#ibcon#about to write, iclass 30, count 2 2006.189.07:31:10.55#ibcon#wrote, iclass 30, count 2 2006.189.07:31:10.55#ibcon#about to read 3, iclass 30, count 2 2006.189.07:31:10.57#ibcon#read 3, iclass 30, count 2 2006.189.07:31:10.57#ibcon#about to read 4, iclass 30, count 2 2006.189.07:31:10.57#ibcon#read 4, iclass 30, count 2 2006.189.07:31:10.57#ibcon#about to read 5, iclass 30, count 2 2006.189.07:31:10.57#ibcon#read 5, iclass 30, count 2 2006.189.07:31:10.58#ibcon#about to read 6, iclass 30, count 2 2006.189.07:31:10.58#ibcon#read 6, iclass 30, count 2 2006.189.07:31:10.58#ibcon#end of sib2, iclass 30, count 2 2006.189.07:31:10.58#ibcon#*after write, iclass 30, count 2 2006.189.07:31:10.58#ibcon#*before return 0, iclass 30, count 2 2006.189.07:31:10.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:10.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:31:10.58#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.07:31:10.58#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:10.58#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:10.69#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:10.69#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:10.69#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:31:10.69#ibcon#first serial, iclass 30, count 0 2006.189.07:31:10.69#ibcon#enter sib2, iclass 30, count 0 2006.189.07:31:10.70#ibcon#flushed, iclass 30, count 0 2006.189.07:31:10.70#ibcon#about to write, iclass 30, count 0 2006.189.07:31:10.70#ibcon#wrote, iclass 30, count 0 2006.189.07:31:10.70#ibcon#about to read 3, iclass 30, count 0 2006.189.07:31:10.71#ibcon#read 3, iclass 30, count 0 2006.189.07:31:10.71#ibcon#about to read 4, iclass 30, count 0 2006.189.07:31:10.72#ibcon#read 4, iclass 30, count 0 2006.189.07:31:10.72#ibcon#about to read 5, iclass 30, count 0 2006.189.07:31:10.72#ibcon#read 5, iclass 30, count 0 2006.189.07:31:10.72#ibcon#about to read 6, iclass 30, count 0 2006.189.07:31:10.72#ibcon#read 6, iclass 30, count 0 2006.189.07:31:10.72#ibcon#end of sib2, iclass 30, count 0 2006.189.07:31:10.72#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:31:10.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:31:10.72#ibcon#[27=USB\r\n] 2006.189.07:31:10.72#ibcon#*before write, iclass 30, count 0 2006.189.07:31:10.72#ibcon#enter sib2, iclass 30, count 0 2006.189.07:31:10.72#ibcon#flushed, iclass 30, count 0 2006.189.07:31:10.72#ibcon#about to write, iclass 30, count 0 2006.189.07:31:10.72#ibcon#wrote, iclass 30, count 0 2006.189.07:31:10.72#ibcon#about to read 3, iclass 30, count 0 2006.189.07:31:10.74#ibcon#read 3, iclass 30, count 0 2006.189.07:31:10.74#ibcon#about to read 4, iclass 30, count 0 2006.189.07:31:10.74#ibcon#read 4, iclass 30, count 0 2006.189.07:31:10.75#ibcon#about to read 5, iclass 30, count 0 2006.189.07:31:10.75#ibcon#read 5, iclass 30, count 0 2006.189.07:31:10.75#ibcon#about to read 6, iclass 30, count 0 2006.189.07:31:10.75#ibcon#read 6, iclass 30, count 0 2006.189.07:31:10.75#ibcon#end of sib2, iclass 30, count 0 2006.189.07:31:10.75#ibcon#*after write, iclass 30, count 0 2006.189.07:31:10.75#ibcon#*before return 0, iclass 30, count 0 2006.189.07:31:10.75#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:10.75#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:31:10.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:31:10.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:31:10.75$vc4f8/vblo=4,712.99 2006.189.07:31:10.75#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.07:31:10.75#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.07:31:10.75#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:10.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:10.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:10.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:10.75#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:31:10.75#ibcon#first serial, iclass 32, count 0 2006.189.07:31:10.75#ibcon#enter sib2, iclass 32, count 0 2006.189.07:31:10.75#ibcon#flushed, iclass 32, count 0 2006.189.07:31:10.75#ibcon#about to write, iclass 32, count 0 2006.189.07:31:10.75#ibcon#wrote, iclass 32, count 0 2006.189.07:31:10.75#ibcon#about to read 3, iclass 32, count 0 2006.189.07:31:10.76#ibcon#read 3, iclass 32, count 0 2006.189.07:31:10.76#ibcon#about to read 4, iclass 32, count 0 2006.189.07:31:10.76#ibcon#read 4, iclass 32, count 0 2006.189.07:31:10.76#ibcon#about to read 5, iclass 32, count 0 2006.189.07:31:10.77#ibcon#read 5, iclass 32, count 0 2006.189.07:31:10.77#ibcon#about to read 6, iclass 32, count 0 2006.189.07:31:10.77#ibcon#read 6, iclass 32, count 0 2006.189.07:31:10.77#ibcon#end of sib2, iclass 32, count 0 2006.189.07:31:10.77#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:31:10.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:31:10.77#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:31:10.77#ibcon#*before write, iclass 32, count 0 2006.189.07:31:10.77#ibcon#enter sib2, iclass 32, count 0 2006.189.07:31:10.77#ibcon#flushed, iclass 32, count 0 2006.189.07:31:10.77#ibcon#about to write, iclass 32, count 0 2006.189.07:31:10.77#ibcon#wrote, iclass 32, count 0 2006.189.07:31:10.77#ibcon#about to read 3, iclass 32, count 0 2006.189.07:31:10.80#ibcon#read 3, iclass 32, count 0 2006.189.07:31:10.80#ibcon#about to read 4, iclass 32, count 0 2006.189.07:31:10.80#ibcon#read 4, iclass 32, count 0 2006.189.07:31:10.80#ibcon#about to read 5, iclass 32, count 0 2006.189.07:31:10.81#ibcon#read 5, iclass 32, count 0 2006.189.07:31:10.81#ibcon#about to read 6, iclass 32, count 0 2006.189.07:31:10.81#ibcon#read 6, iclass 32, count 0 2006.189.07:31:10.81#ibcon#end of sib2, iclass 32, count 0 2006.189.07:31:10.81#ibcon#*after write, iclass 32, count 0 2006.189.07:31:10.81#ibcon#*before return 0, iclass 32, count 0 2006.189.07:31:10.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:10.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:31:10.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:31:10.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:31:10.81$vc4f8/vb=4,4 2006.189.07:31:10.81#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.07:31:10.81#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.07:31:10.81#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:10.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:10.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:10.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:10.86#ibcon#enter wrdev, iclass 34, count 2 2006.189.07:31:10.87#ibcon#first serial, iclass 34, count 2 2006.189.07:31:10.87#ibcon#enter sib2, iclass 34, count 2 2006.189.07:31:10.87#ibcon#flushed, iclass 34, count 2 2006.189.07:31:10.87#ibcon#about to write, iclass 34, count 2 2006.189.07:31:10.87#ibcon#wrote, iclass 34, count 2 2006.189.07:31:10.87#ibcon#about to read 3, iclass 34, count 2 2006.189.07:31:10.88#ibcon#read 3, iclass 34, count 2 2006.189.07:31:10.88#ibcon#about to read 4, iclass 34, count 2 2006.189.07:31:10.88#ibcon#read 4, iclass 34, count 2 2006.189.07:31:10.88#ibcon#about to read 5, iclass 34, count 2 2006.189.07:31:10.89#ibcon#read 5, iclass 34, count 2 2006.189.07:31:10.89#ibcon#about to read 6, iclass 34, count 2 2006.189.07:31:10.89#ibcon#read 6, iclass 34, count 2 2006.189.07:31:10.89#ibcon#end of sib2, iclass 34, count 2 2006.189.07:31:10.89#ibcon#*mode == 0, iclass 34, count 2 2006.189.07:31:10.89#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.07:31:10.89#ibcon#[27=AT04-04\r\n] 2006.189.07:31:10.89#ibcon#*before write, iclass 34, count 2 2006.189.07:31:10.89#ibcon#enter sib2, iclass 34, count 2 2006.189.07:31:10.89#ibcon#flushed, iclass 34, count 2 2006.189.07:31:10.89#ibcon#about to write, iclass 34, count 2 2006.189.07:31:10.89#ibcon#wrote, iclass 34, count 2 2006.189.07:31:10.89#ibcon#about to read 3, iclass 34, count 2 2006.189.07:31:10.91#ibcon#read 3, iclass 34, count 2 2006.189.07:31:10.91#ibcon#about to read 4, iclass 34, count 2 2006.189.07:31:10.91#ibcon#read 4, iclass 34, count 2 2006.189.07:31:10.91#ibcon#about to read 5, iclass 34, count 2 2006.189.07:31:10.92#ibcon#read 5, iclass 34, count 2 2006.189.07:31:10.92#ibcon#about to read 6, iclass 34, count 2 2006.189.07:31:10.92#ibcon#read 6, iclass 34, count 2 2006.189.07:31:10.92#ibcon#end of sib2, iclass 34, count 2 2006.189.07:31:10.92#ibcon#*after write, iclass 34, count 2 2006.189.07:31:10.92#ibcon#*before return 0, iclass 34, count 2 2006.189.07:31:10.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:10.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:31:10.92#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.07:31:10.92#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:10.92#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:11.03#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:11.03#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:11.03#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:31:11.03#ibcon#first serial, iclass 34, count 0 2006.189.07:31:11.03#ibcon#enter sib2, iclass 34, count 0 2006.189.07:31:11.04#ibcon#flushed, iclass 34, count 0 2006.189.07:31:11.04#ibcon#about to write, iclass 34, count 0 2006.189.07:31:11.04#ibcon#wrote, iclass 34, count 0 2006.189.07:31:11.04#ibcon#about to read 3, iclass 34, count 0 2006.189.07:31:11.05#ibcon#read 3, iclass 34, count 0 2006.189.07:31:11.05#ibcon#about to read 4, iclass 34, count 0 2006.189.07:31:11.05#ibcon#read 4, iclass 34, count 0 2006.189.07:31:11.06#ibcon#about to read 5, iclass 34, count 0 2006.189.07:31:11.06#ibcon#read 5, iclass 34, count 0 2006.189.07:31:11.06#ibcon#about to read 6, iclass 34, count 0 2006.189.07:31:11.06#ibcon#read 6, iclass 34, count 0 2006.189.07:31:11.06#ibcon#end of sib2, iclass 34, count 0 2006.189.07:31:11.06#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:31:11.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:31:11.06#ibcon#[27=USB\r\n] 2006.189.07:31:11.06#ibcon#*before write, iclass 34, count 0 2006.189.07:31:11.06#ibcon#enter sib2, iclass 34, count 0 2006.189.07:31:11.06#ibcon#flushed, iclass 34, count 0 2006.189.07:31:11.06#ibcon#about to write, iclass 34, count 0 2006.189.07:31:11.06#ibcon#wrote, iclass 34, count 0 2006.189.07:31:11.06#ibcon#about to read 3, iclass 34, count 0 2006.189.07:31:11.08#ibcon#read 3, iclass 34, count 0 2006.189.07:31:11.08#ibcon#about to read 4, iclass 34, count 0 2006.189.07:31:11.08#ibcon#read 4, iclass 34, count 0 2006.189.07:31:11.08#ibcon#about to read 5, iclass 34, count 0 2006.189.07:31:11.09#ibcon#read 5, iclass 34, count 0 2006.189.07:31:11.09#ibcon#about to read 6, iclass 34, count 0 2006.189.07:31:11.09#ibcon#read 6, iclass 34, count 0 2006.189.07:31:11.09#ibcon#end of sib2, iclass 34, count 0 2006.189.07:31:11.09#ibcon#*after write, iclass 34, count 0 2006.189.07:31:11.09#ibcon#*before return 0, iclass 34, count 0 2006.189.07:31:11.09#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:11.09#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:31:11.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:31:11.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:31:11.09$vc4f8/vblo=5,744.99 2006.189.07:31:11.09#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.07:31:11.09#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.07:31:11.09#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:11.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:11.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:11.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:11.09#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:31:11.09#ibcon#first serial, iclass 36, count 0 2006.189.07:31:11.09#ibcon#enter sib2, iclass 36, count 0 2006.189.07:31:11.09#ibcon#flushed, iclass 36, count 0 2006.189.07:31:11.09#ibcon#about to write, iclass 36, count 0 2006.189.07:31:11.09#ibcon#wrote, iclass 36, count 0 2006.189.07:31:11.09#ibcon#about to read 3, iclass 36, count 0 2006.189.07:31:11.10#ibcon#read 3, iclass 36, count 0 2006.189.07:31:11.10#ibcon#about to read 4, iclass 36, count 0 2006.189.07:31:11.10#ibcon#read 4, iclass 36, count 0 2006.189.07:31:11.10#ibcon#about to read 5, iclass 36, count 0 2006.189.07:31:11.11#ibcon#read 5, iclass 36, count 0 2006.189.07:31:11.11#ibcon#about to read 6, iclass 36, count 0 2006.189.07:31:11.11#ibcon#read 6, iclass 36, count 0 2006.189.07:31:11.11#ibcon#end of sib2, iclass 36, count 0 2006.189.07:31:11.11#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:31:11.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:31:11.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:31:11.11#ibcon#*before write, iclass 36, count 0 2006.189.07:31:11.11#ibcon#enter sib2, iclass 36, count 0 2006.189.07:31:11.11#ibcon#flushed, iclass 36, count 0 2006.189.07:31:11.11#ibcon#about to write, iclass 36, count 0 2006.189.07:31:11.11#ibcon#wrote, iclass 36, count 0 2006.189.07:31:11.11#ibcon#about to read 3, iclass 36, count 0 2006.189.07:31:11.14#ibcon#read 3, iclass 36, count 0 2006.189.07:31:11.14#ibcon#about to read 4, iclass 36, count 0 2006.189.07:31:11.14#ibcon#read 4, iclass 36, count 0 2006.189.07:31:11.14#ibcon#about to read 5, iclass 36, count 0 2006.189.07:31:11.15#ibcon#read 5, iclass 36, count 0 2006.189.07:31:11.15#ibcon#about to read 6, iclass 36, count 0 2006.189.07:31:11.15#ibcon#read 6, iclass 36, count 0 2006.189.07:31:11.15#ibcon#end of sib2, iclass 36, count 0 2006.189.07:31:11.15#ibcon#*after write, iclass 36, count 0 2006.189.07:31:11.15#ibcon#*before return 0, iclass 36, count 0 2006.189.07:31:11.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:11.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:31:11.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:31:11.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:31:11.15$vc4f8/vb=5,4 2006.189.07:31:11.15#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.07:31:11.15#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.07:31:11.15#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:11.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:11.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:11.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:11.20#ibcon#enter wrdev, iclass 38, count 2 2006.189.07:31:11.20#ibcon#first serial, iclass 38, count 2 2006.189.07:31:11.20#ibcon#enter sib2, iclass 38, count 2 2006.189.07:31:11.21#ibcon#flushed, iclass 38, count 2 2006.189.07:31:11.21#ibcon#about to write, iclass 38, count 2 2006.189.07:31:11.21#ibcon#wrote, iclass 38, count 2 2006.189.07:31:11.21#ibcon#about to read 3, iclass 38, count 2 2006.189.07:31:11.22#ibcon#read 3, iclass 38, count 2 2006.189.07:31:11.22#ibcon#about to read 4, iclass 38, count 2 2006.189.07:31:11.22#ibcon#read 4, iclass 38, count 2 2006.189.07:31:11.23#ibcon#about to read 5, iclass 38, count 2 2006.189.07:31:11.23#ibcon#read 5, iclass 38, count 2 2006.189.07:31:11.23#ibcon#about to read 6, iclass 38, count 2 2006.189.07:31:11.23#ibcon#read 6, iclass 38, count 2 2006.189.07:31:11.23#ibcon#end of sib2, iclass 38, count 2 2006.189.07:31:11.23#ibcon#*mode == 0, iclass 38, count 2 2006.189.07:31:11.23#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.07:31:11.23#ibcon#[27=AT05-04\r\n] 2006.189.07:31:11.23#ibcon#*before write, iclass 38, count 2 2006.189.07:31:11.23#ibcon#enter sib2, iclass 38, count 2 2006.189.07:31:11.23#ibcon#flushed, iclass 38, count 2 2006.189.07:31:11.23#ibcon#about to write, iclass 38, count 2 2006.189.07:31:11.23#ibcon#wrote, iclass 38, count 2 2006.189.07:31:11.23#ibcon#about to read 3, iclass 38, count 2 2006.189.07:31:11.25#ibcon#read 3, iclass 38, count 2 2006.189.07:31:11.25#ibcon#about to read 4, iclass 38, count 2 2006.189.07:31:11.25#ibcon#read 4, iclass 38, count 2 2006.189.07:31:11.25#ibcon#about to read 5, iclass 38, count 2 2006.189.07:31:11.26#ibcon#read 5, iclass 38, count 2 2006.189.07:31:11.26#ibcon#about to read 6, iclass 38, count 2 2006.189.07:31:11.26#ibcon#read 6, iclass 38, count 2 2006.189.07:31:11.26#ibcon#end of sib2, iclass 38, count 2 2006.189.07:31:11.26#ibcon#*after write, iclass 38, count 2 2006.189.07:31:11.26#ibcon#*before return 0, iclass 38, count 2 2006.189.07:31:11.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:11.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:31:11.26#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.07:31:11.26#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:11.26#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:11.37#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:11.37#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:11.37#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:31:11.37#ibcon#first serial, iclass 38, count 0 2006.189.07:31:11.37#ibcon#enter sib2, iclass 38, count 0 2006.189.07:31:11.38#ibcon#flushed, iclass 38, count 0 2006.189.07:31:11.38#ibcon#about to write, iclass 38, count 0 2006.189.07:31:11.38#ibcon#wrote, iclass 38, count 0 2006.189.07:31:11.38#ibcon#about to read 3, iclass 38, count 0 2006.189.07:31:11.39#ibcon#read 3, iclass 38, count 0 2006.189.07:31:11.39#ibcon#about to read 4, iclass 38, count 0 2006.189.07:31:11.39#ibcon#read 4, iclass 38, count 0 2006.189.07:31:11.39#ibcon#about to read 5, iclass 38, count 0 2006.189.07:31:11.40#ibcon#read 5, iclass 38, count 0 2006.189.07:31:11.40#ibcon#about to read 6, iclass 38, count 0 2006.189.07:31:11.40#ibcon#read 6, iclass 38, count 0 2006.189.07:31:11.40#ibcon#end of sib2, iclass 38, count 0 2006.189.07:31:11.40#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:31:11.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:31:11.40#ibcon#[27=USB\r\n] 2006.189.07:31:11.40#ibcon#*before write, iclass 38, count 0 2006.189.07:31:11.40#ibcon#enter sib2, iclass 38, count 0 2006.189.07:31:11.40#ibcon#flushed, iclass 38, count 0 2006.189.07:31:11.40#ibcon#about to write, iclass 38, count 0 2006.189.07:31:11.40#ibcon#wrote, iclass 38, count 0 2006.189.07:31:11.40#ibcon#about to read 3, iclass 38, count 0 2006.189.07:31:11.42#ibcon#read 3, iclass 38, count 0 2006.189.07:31:11.42#ibcon#about to read 4, iclass 38, count 0 2006.189.07:31:11.42#ibcon#read 4, iclass 38, count 0 2006.189.07:31:11.42#ibcon#about to read 5, iclass 38, count 0 2006.189.07:31:11.43#ibcon#read 5, iclass 38, count 0 2006.189.07:31:11.43#ibcon#about to read 6, iclass 38, count 0 2006.189.07:31:11.43#ibcon#read 6, iclass 38, count 0 2006.189.07:31:11.43#ibcon#end of sib2, iclass 38, count 0 2006.189.07:31:11.43#ibcon#*after write, iclass 38, count 0 2006.189.07:31:11.43#ibcon#*before return 0, iclass 38, count 0 2006.189.07:31:11.43#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:11.43#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:31:11.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:31:11.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:31:11.43$vc4f8/vblo=6,752.99 2006.189.07:31:11.43#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.07:31:11.43#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.07:31:11.43#ibcon#ireg 17 cls_cnt 0 2006.189.07:31:11.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:11.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:11.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:11.43#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:31:11.43#ibcon#first serial, iclass 40, count 0 2006.189.07:31:11.43#ibcon#enter sib2, iclass 40, count 0 2006.189.07:31:11.43#ibcon#flushed, iclass 40, count 0 2006.189.07:31:11.43#ibcon#about to write, iclass 40, count 0 2006.189.07:31:11.43#ibcon#wrote, iclass 40, count 0 2006.189.07:31:11.43#ibcon#about to read 3, iclass 40, count 0 2006.189.07:31:11.44#ibcon#read 3, iclass 40, count 0 2006.189.07:31:11.44#ibcon#about to read 4, iclass 40, count 0 2006.189.07:31:11.44#ibcon#read 4, iclass 40, count 0 2006.189.07:31:11.44#ibcon#about to read 5, iclass 40, count 0 2006.189.07:31:11.45#ibcon#read 5, iclass 40, count 0 2006.189.07:31:11.45#ibcon#about to read 6, iclass 40, count 0 2006.189.07:31:11.45#ibcon#read 6, iclass 40, count 0 2006.189.07:31:11.45#ibcon#end of sib2, iclass 40, count 0 2006.189.07:31:11.45#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:31:11.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:31:11.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:31:11.45#ibcon#*before write, iclass 40, count 0 2006.189.07:31:11.45#ibcon#enter sib2, iclass 40, count 0 2006.189.07:31:11.45#ibcon#flushed, iclass 40, count 0 2006.189.07:31:11.45#ibcon#about to write, iclass 40, count 0 2006.189.07:31:11.45#ibcon#wrote, iclass 40, count 0 2006.189.07:31:11.45#ibcon#about to read 3, iclass 40, count 0 2006.189.07:31:11.48#ibcon#read 3, iclass 40, count 0 2006.189.07:31:11.48#ibcon#about to read 4, iclass 40, count 0 2006.189.07:31:11.48#ibcon#read 4, iclass 40, count 0 2006.189.07:31:11.48#ibcon#about to read 5, iclass 40, count 0 2006.189.07:31:11.49#ibcon#read 5, iclass 40, count 0 2006.189.07:31:11.49#ibcon#about to read 6, iclass 40, count 0 2006.189.07:31:11.49#ibcon#read 6, iclass 40, count 0 2006.189.07:31:11.49#ibcon#end of sib2, iclass 40, count 0 2006.189.07:31:11.49#ibcon#*after write, iclass 40, count 0 2006.189.07:31:11.49#ibcon#*before return 0, iclass 40, count 0 2006.189.07:31:11.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:11.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:31:11.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:31:11.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:31:11.49$vc4f8/vb=6,4 2006.189.07:31:11.49#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.07:31:11.49#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.07:31:11.49#ibcon#ireg 11 cls_cnt 2 2006.189.07:31:11.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:11.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:11.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:11.54#ibcon#enter wrdev, iclass 4, count 2 2006.189.07:31:11.54#ibcon#first serial, iclass 4, count 2 2006.189.07:31:11.54#ibcon#enter sib2, iclass 4, count 2 2006.189.07:31:11.54#ibcon#flushed, iclass 4, count 2 2006.189.07:31:11.55#ibcon#about to write, iclass 4, count 2 2006.189.07:31:11.55#ibcon#wrote, iclass 4, count 2 2006.189.07:31:11.55#ibcon#about to read 3, iclass 4, count 2 2006.189.07:31:11.56#ibcon#read 3, iclass 4, count 2 2006.189.07:31:11.56#ibcon#about to read 4, iclass 4, count 2 2006.189.07:31:11.56#ibcon#read 4, iclass 4, count 2 2006.189.07:31:11.56#ibcon#about to read 5, iclass 4, count 2 2006.189.07:31:11.57#ibcon#read 5, iclass 4, count 2 2006.189.07:31:11.57#ibcon#about to read 6, iclass 4, count 2 2006.189.07:31:11.57#ibcon#read 6, iclass 4, count 2 2006.189.07:31:11.57#ibcon#end of sib2, iclass 4, count 2 2006.189.07:31:11.57#ibcon#*mode == 0, iclass 4, count 2 2006.189.07:31:11.57#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.07:31:11.57#ibcon#[27=AT06-04\r\n] 2006.189.07:31:11.57#ibcon#*before write, iclass 4, count 2 2006.189.07:31:11.57#ibcon#enter sib2, iclass 4, count 2 2006.189.07:31:11.57#ibcon#flushed, iclass 4, count 2 2006.189.07:31:11.57#ibcon#about to write, iclass 4, count 2 2006.189.07:31:11.57#ibcon#wrote, iclass 4, count 2 2006.189.07:31:11.57#ibcon#about to read 3, iclass 4, count 2 2006.189.07:31:11.59#ibcon#read 3, iclass 4, count 2 2006.189.07:31:11.59#ibcon#about to read 4, iclass 4, count 2 2006.189.07:31:11.59#ibcon#read 4, iclass 4, count 2 2006.189.07:31:11.59#ibcon#about to read 5, iclass 4, count 2 2006.189.07:31:11.60#ibcon#read 5, iclass 4, count 2 2006.189.07:31:11.60#ibcon#about to read 6, iclass 4, count 2 2006.189.07:31:11.60#ibcon#read 6, iclass 4, count 2 2006.189.07:31:11.60#ibcon#end of sib2, iclass 4, count 2 2006.189.07:31:11.60#ibcon#*after write, iclass 4, count 2 2006.189.07:31:11.60#ibcon#*before return 0, iclass 4, count 2 2006.189.07:31:11.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:11.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:31:11.60#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.07:31:11.60#ibcon#ireg 7 cls_cnt 0 2006.189.07:31:11.60#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:11.71#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:11.71#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:11.71#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:31:11.71#ibcon#first serial, iclass 4, count 0 2006.189.07:31:11.71#ibcon#enter sib2, iclass 4, count 0 2006.189.07:31:11.72#ibcon#flushed, iclass 4, count 0 2006.189.07:31:11.72#ibcon#about to write, iclass 4, count 0 2006.189.07:31:11.72#ibcon#wrote, iclass 4, count 0 2006.189.07:31:11.72#ibcon#about to read 3, iclass 4, count 0 2006.189.07:31:11.73#ibcon#read 3, iclass 4, count 0 2006.189.07:31:11.73#ibcon#about to read 4, iclass 4, count 0 2006.189.07:31:11.73#ibcon#read 4, iclass 4, count 0 2006.189.07:31:11.73#ibcon#about to read 5, iclass 4, count 0 2006.189.07:31:11.74#ibcon#read 5, iclass 4, count 0 2006.189.07:31:11.74#ibcon#about to read 6, iclass 4, count 0 2006.189.07:31:11.74#ibcon#read 6, iclass 4, count 0 2006.189.07:31:11.74#ibcon#end of sib2, iclass 4, count 0 2006.189.07:31:11.74#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:31:11.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:31:11.74#ibcon#[27=USB\r\n] 2006.189.07:31:11.74#ibcon#*before write, iclass 4, count 0 2006.189.07:31:11.74#ibcon#enter sib2, iclass 4, count 0 2006.189.07:31:11.74#ibcon#flushed, iclass 4, count 0 2006.189.07:31:11.74#ibcon#about to write, iclass 4, count 0 2006.189.07:31:11.74#ibcon#wrote, iclass 4, count 0 2006.189.07:31:11.74#ibcon#about to read 3, iclass 4, count 0 2006.189.07:31:11.76#ibcon#read 3, iclass 4, count 0 2006.189.07:31:11.76#ibcon#about to read 4, iclass 4, count 0 2006.189.07:31:11.76#ibcon#read 4, iclass 4, count 0 2006.189.07:31:11.76#ibcon#about to read 5, iclass 4, count 0 2006.189.07:31:11.77#ibcon#read 5, iclass 4, count 0 2006.189.07:31:11.77#ibcon#about to read 6, iclass 4, count 0 2006.189.07:31:11.77#ibcon#read 6, iclass 4, count 0 2006.189.07:31:11.77#ibcon#end of sib2, iclass 4, count 0 2006.189.07:31:11.77#ibcon#*after write, iclass 4, count 0 2006.189.07:31:11.77#ibcon#*before return 0, iclass 4, count 0 2006.189.07:31:11.77#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:11.77#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:31:11.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:31:11.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:31:11.77$vc4f8/vabw=wide 2006.189.07:31:11.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:31:11.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:31:11.77#ibcon#ireg 8 cls_cnt 0 2006.189.07:31:11.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:11.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:11.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:11.77#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:31:11.77#ibcon#first serial, iclass 6, count 0 2006.189.07:31:11.77#ibcon#enter sib2, iclass 6, count 0 2006.189.07:31:11.77#ibcon#flushed, iclass 6, count 0 2006.189.07:31:11.77#ibcon#about to write, iclass 6, count 0 2006.189.07:31:11.77#ibcon#wrote, iclass 6, count 0 2006.189.07:31:11.77#ibcon#about to read 3, iclass 6, count 0 2006.189.07:31:11.78#ibcon#read 3, iclass 6, count 0 2006.189.07:31:11.78#ibcon#about to read 4, iclass 6, count 0 2006.189.07:31:11.78#ibcon#read 4, iclass 6, count 0 2006.189.07:31:11.78#ibcon#about to read 5, iclass 6, count 0 2006.189.07:31:11.79#ibcon#read 5, iclass 6, count 0 2006.189.07:31:11.79#ibcon#about to read 6, iclass 6, count 0 2006.189.07:31:11.79#ibcon#read 6, iclass 6, count 0 2006.189.07:31:11.79#ibcon#end of sib2, iclass 6, count 0 2006.189.07:31:11.79#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:31:11.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:31:11.79#ibcon#[25=BW32\r\n] 2006.189.07:31:11.79#ibcon#*before write, iclass 6, count 0 2006.189.07:31:11.79#ibcon#enter sib2, iclass 6, count 0 2006.189.07:31:11.79#ibcon#flushed, iclass 6, count 0 2006.189.07:31:11.79#ibcon#about to write, iclass 6, count 0 2006.189.07:31:11.79#ibcon#wrote, iclass 6, count 0 2006.189.07:31:11.79#ibcon#about to read 3, iclass 6, count 0 2006.189.07:31:11.81#ibcon#read 3, iclass 6, count 0 2006.189.07:31:11.81#ibcon#about to read 4, iclass 6, count 0 2006.189.07:31:11.82#ibcon#read 4, iclass 6, count 0 2006.189.07:31:11.82#ibcon#about to read 5, iclass 6, count 0 2006.189.07:31:11.82#ibcon#read 5, iclass 6, count 0 2006.189.07:31:11.82#ibcon#about to read 6, iclass 6, count 0 2006.189.07:31:11.82#ibcon#read 6, iclass 6, count 0 2006.189.07:31:11.82#ibcon#end of sib2, iclass 6, count 0 2006.189.07:31:11.82#ibcon#*after write, iclass 6, count 0 2006.189.07:31:11.82#ibcon#*before return 0, iclass 6, count 0 2006.189.07:31:11.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:11.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:31:11.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:31:11.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:31:11.82$vc4f8/vbbw=wide 2006.189.07:31:11.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.07:31:11.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.07:31:11.82#ibcon#ireg 8 cls_cnt 0 2006.189.07:31:11.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:31:11.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:31:11.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:31:11.88#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:31:11.88#ibcon#first serial, iclass 10, count 0 2006.189.07:31:11.88#ibcon#enter sib2, iclass 10, count 0 2006.189.07:31:11.89#ibcon#flushed, iclass 10, count 0 2006.189.07:31:11.89#ibcon#about to write, iclass 10, count 0 2006.189.07:31:11.89#ibcon#wrote, iclass 10, count 0 2006.189.07:31:11.89#ibcon#about to read 3, iclass 10, count 0 2006.189.07:31:11.90#ibcon#read 3, iclass 10, count 0 2006.189.07:31:11.90#ibcon#about to read 4, iclass 10, count 0 2006.189.07:31:11.90#ibcon#read 4, iclass 10, count 0 2006.189.07:31:11.91#ibcon#about to read 5, iclass 10, count 0 2006.189.07:31:11.91#ibcon#read 5, iclass 10, count 0 2006.189.07:31:11.91#ibcon#about to read 6, iclass 10, count 0 2006.189.07:31:11.91#ibcon#read 6, iclass 10, count 0 2006.189.07:31:11.91#ibcon#end of sib2, iclass 10, count 0 2006.189.07:31:11.91#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:31:11.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:31:11.91#ibcon#[27=BW32\r\n] 2006.189.07:31:11.91#ibcon#*before write, iclass 10, count 0 2006.189.07:31:11.91#ibcon#enter sib2, iclass 10, count 0 2006.189.07:31:11.91#ibcon#flushed, iclass 10, count 0 2006.189.07:31:11.91#ibcon#about to write, iclass 10, count 0 2006.189.07:31:11.91#ibcon#wrote, iclass 10, count 0 2006.189.07:31:11.91#ibcon#about to read 3, iclass 10, count 0 2006.189.07:31:11.93#ibcon#read 3, iclass 10, count 0 2006.189.07:31:11.93#ibcon#about to read 4, iclass 10, count 0 2006.189.07:31:11.93#ibcon#read 4, iclass 10, count 0 2006.189.07:31:11.94#ibcon#about to read 5, iclass 10, count 0 2006.189.07:31:11.94#ibcon#read 5, iclass 10, count 0 2006.189.07:31:11.94#ibcon#about to read 6, iclass 10, count 0 2006.189.07:31:11.94#ibcon#read 6, iclass 10, count 0 2006.189.07:31:11.94#ibcon#end of sib2, iclass 10, count 0 2006.189.07:31:11.94#ibcon#*after write, iclass 10, count 0 2006.189.07:31:11.94#ibcon#*before return 0, iclass 10, count 0 2006.189.07:31:11.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:31:11.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:31:11.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:31:11.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:31:11.94$4f8m12a/ifd4f 2006.189.07:31:11.94$ifd4f/lo= 2006.189.07:31:11.94$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:31:11.94$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:31:11.94$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:31:11.94$ifd4f/patch= 2006.189.07:31:11.94$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:31:11.94$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:31:11.94$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:31:11.94$4f8m12a/"form=m,16.000,1:2 2006.189.07:31:11.94$4f8m12a/"tpicd 2006.189.07:31:11.94$4f8m12a/echo=off 2006.189.07:31:11.94$4f8m12a/xlog=off 2006.189.07:31:11.94:!2006.189.07:33:20 2006.189.07:31:53.14#trakl#Source acquired 2006.189.07:31:54.15#flagr#flagr/antenna,acquired 2006.189.07:33:20.02:preob 2006.189.07:33:21.15/onsource/TRACKING 2006.189.07:33:21.15:!2006.189.07:33:30 2006.189.07:33:30.01:data_valid=on 2006.189.07:33:30.02:midob 2006.189.07:33:31.14/onsource/TRACKING 2006.189.07:33:31.15/wx/26.50,1008.9,86 2006.189.07:33:31.21/cable/+6.4546E-03 2006.189.07:33:32.30/va/01,08,usb,yes,33,35 2006.189.07:33:32.30/va/02,07,usb,yes,34,35 2006.189.07:33:32.30/va/03,06,usb,yes,36,36 2006.189.07:33:32.30/va/04,07,usb,yes,35,37 2006.189.07:33:32.30/va/05,07,usb,yes,36,38 2006.189.07:33:32.30/va/06,06,usb,yes,36,35 2006.189.07:33:32.30/va/07,06,usb,yes,36,36 2006.189.07:33:32.30/va/08,06,usb,yes,38,38 2006.189.07:33:32.53/valo/01,532.99,yes,locked 2006.189.07:33:32.53/valo/02,572.99,yes,locked 2006.189.07:33:32.53/valo/03,672.99,yes,locked 2006.189.07:33:32.53/valo/04,832.99,yes,locked 2006.189.07:33:32.53/valo/05,652.99,yes,locked 2006.189.07:33:32.53/valo/06,772.99,yes,locked 2006.189.07:33:32.53/valo/07,832.99,yes,locked 2006.189.07:33:32.53/valo/08,852.99,yes,locked 2006.189.07:33:33.62/vb/01,04,usb,yes,31,30 2006.189.07:33:33.62/vb/02,04,usb,yes,33,35 2006.189.07:33:33.62/vb/03,04,usb,yes,29,33 2006.189.07:33:33.62/vb/04,04,usb,yes,30,31 2006.189.07:33:33.62/vb/05,04,usb,yes,29,33 2006.189.07:33:33.62/vb/06,04,usb,yes,30,33 2006.189.07:33:33.62/vb/07,04,usb,yes,32,32 2006.189.07:33:33.62/vb/08,04,usb,yes,29,33 2006.189.07:33:33.85/vblo/01,632.99,yes,locked 2006.189.07:33:33.85/vblo/02,640.99,yes,locked 2006.189.07:33:33.85/vblo/03,656.99,yes,locked 2006.189.07:33:33.85/vblo/04,712.99,yes,locked 2006.189.07:33:33.85/vblo/05,744.99,yes,locked 2006.189.07:33:33.85/vblo/06,752.99,yes,locked 2006.189.07:33:33.85/vblo/07,734.99,yes,locked 2006.189.07:33:33.85/vblo/08,744.99,yes,locked 2006.189.07:33:34.00/vabw/8 2006.189.07:33:34.15/vbbw/8 2006.189.07:33:34.24/xfe/off,on,14.7 2006.189.07:33:34.61/ifatt/23,28,28,28 2006.189.07:33:35.07/fmout-gps/S +2.97E-07 2006.189.07:33:35.16:!2006.189.07:34:30 2006.189.07:34:30.01:data_valid=off 2006.189.07:34:30.02:postob 2006.189.07:34:30.17/cable/+6.4536E-03 2006.189.07:34:30.18/wx/26.48,1008.9,87 2006.189.07:34:31.07/fmout-gps/S +2.97E-07 2006.189.07:34:31.08:scan_name=189-0735,k06189,60 2006.189.07:34:31.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.189.07:34:32.14#flagr#flagr/antenna,new-source 2006.189.07:34:32.15:checkk5 2006.189.07:34:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:34:32.92/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:34:33.30/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:34:33.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:34:34.06/chk_obsdata//k5ts1/T1890733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:34:34.43/chk_obsdata//k5ts2/T1890733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:34:34.88/chk_obsdata//k5ts3/T1890733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:34:35.26/chk_obsdata//k5ts4/T1890733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:34:35.95/k5log//k5ts1_log_newline 2006.189.07:34:36.65/k5log//k5ts2_log_newline 2006.189.07:34:37.35/k5log//k5ts3_log_newline 2006.189.07:34:38.04/k5log//k5ts4_log_newline 2006.189.07:34:38.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:34:38.11:4f8m12a=1 2006.189.07:34:38.11$4f8m12a/echo=on 2006.189.07:34:38.11$4f8m12a/pcalon 2006.189.07:34:38.11$pcalon/"no phase cal control is implemented here 2006.189.07:34:38.11$4f8m12a/"tpicd=stop 2006.189.07:34:38.11$4f8m12a/vc4f8 2006.189.07:34:38.11$vc4f8/valo=1,532.99 2006.189.07:34:38.11#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:34:38.11#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:34:38.11#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:38.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:38.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:38.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:38.11#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:34:38.11#ibcon#first serial, iclass 21, count 0 2006.189.07:34:38.11#ibcon#enter sib2, iclass 21, count 0 2006.189.07:34:38.11#ibcon#flushed, iclass 21, count 0 2006.189.07:34:38.11#ibcon#about to write, iclass 21, count 0 2006.189.07:34:38.11#ibcon#wrote, iclass 21, count 0 2006.189.07:34:38.11#ibcon#about to read 3, iclass 21, count 0 2006.189.07:34:38.12#ibcon#read 3, iclass 21, count 0 2006.189.07:34:38.12#ibcon#about to read 4, iclass 21, count 0 2006.189.07:34:38.12#ibcon#read 4, iclass 21, count 0 2006.189.07:34:38.12#ibcon#about to read 5, iclass 21, count 0 2006.189.07:34:38.12#ibcon#read 5, iclass 21, count 0 2006.189.07:34:38.12#ibcon#about to read 6, iclass 21, count 0 2006.189.07:34:38.12#ibcon#read 6, iclass 21, count 0 2006.189.07:34:38.12#ibcon#end of sib2, iclass 21, count 0 2006.189.07:34:38.12#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:34:38.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:34:38.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:34:38.12#ibcon#*before write, iclass 21, count 0 2006.189.07:34:38.12#ibcon#enter sib2, iclass 21, count 0 2006.189.07:34:38.12#ibcon#flushed, iclass 21, count 0 2006.189.07:34:38.12#ibcon#about to write, iclass 21, count 0 2006.189.07:34:38.12#ibcon#wrote, iclass 21, count 0 2006.189.07:34:38.12#ibcon#about to read 3, iclass 21, count 0 2006.189.07:34:38.17#ibcon#read 3, iclass 21, count 0 2006.189.07:34:38.17#ibcon#about to read 4, iclass 21, count 0 2006.189.07:34:38.17#ibcon#read 4, iclass 21, count 0 2006.189.07:34:38.17#ibcon#about to read 5, iclass 21, count 0 2006.189.07:34:38.17#ibcon#read 5, iclass 21, count 0 2006.189.07:34:38.17#ibcon#about to read 6, iclass 21, count 0 2006.189.07:34:38.17#ibcon#read 6, iclass 21, count 0 2006.189.07:34:38.17#ibcon#end of sib2, iclass 21, count 0 2006.189.07:34:38.17#ibcon#*after write, iclass 21, count 0 2006.189.07:34:38.17#ibcon#*before return 0, iclass 21, count 0 2006.189.07:34:38.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:38.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:38.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:34:38.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:34:38.17$vc4f8/va=1,8 2006.189.07:34:38.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:34:38.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:34:38.17#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:38.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:38.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:38.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:38.17#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:34:38.17#ibcon#first serial, iclass 23, count 2 2006.189.07:34:38.17#ibcon#enter sib2, iclass 23, count 2 2006.189.07:34:38.18#ibcon#flushed, iclass 23, count 2 2006.189.07:34:38.18#ibcon#about to write, iclass 23, count 2 2006.189.07:34:38.18#ibcon#wrote, iclass 23, count 2 2006.189.07:34:38.18#ibcon#about to read 3, iclass 23, count 2 2006.189.07:34:38.19#ibcon#read 3, iclass 23, count 2 2006.189.07:34:38.19#ibcon#about to read 4, iclass 23, count 2 2006.189.07:34:38.19#ibcon#read 4, iclass 23, count 2 2006.189.07:34:38.19#ibcon#about to read 5, iclass 23, count 2 2006.189.07:34:38.19#ibcon#read 5, iclass 23, count 2 2006.189.07:34:38.19#ibcon#about to read 6, iclass 23, count 2 2006.189.07:34:38.19#ibcon#read 6, iclass 23, count 2 2006.189.07:34:38.19#ibcon#end of sib2, iclass 23, count 2 2006.189.07:34:38.19#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:34:38.19#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:34:38.19#ibcon#[25=AT01-08\r\n] 2006.189.07:34:38.19#ibcon#*before write, iclass 23, count 2 2006.189.07:34:38.19#ibcon#enter sib2, iclass 23, count 2 2006.189.07:34:38.19#ibcon#flushed, iclass 23, count 2 2006.189.07:34:38.19#ibcon#about to write, iclass 23, count 2 2006.189.07:34:38.19#ibcon#wrote, iclass 23, count 2 2006.189.07:34:38.19#ibcon#about to read 3, iclass 23, count 2 2006.189.07:34:38.22#ibcon#read 3, iclass 23, count 2 2006.189.07:34:38.22#ibcon#about to read 4, iclass 23, count 2 2006.189.07:34:38.22#ibcon#read 4, iclass 23, count 2 2006.189.07:34:38.22#ibcon#about to read 5, iclass 23, count 2 2006.189.07:34:38.22#ibcon#read 5, iclass 23, count 2 2006.189.07:34:38.22#ibcon#about to read 6, iclass 23, count 2 2006.189.07:34:38.22#ibcon#read 6, iclass 23, count 2 2006.189.07:34:38.22#ibcon#end of sib2, iclass 23, count 2 2006.189.07:34:38.22#ibcon#*after write, iclass 23, count 2 2006.189.07:34:38.22#ibcon#*before return 0, iclass 23, count 2 2006.189.07:34:38.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:38.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:38.22#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:34:38.22#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:38.22#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:38.34#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:38.34#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:38.34#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:34:38.34#ibcon#first serial, iclass 23, count 0 2006.189.07:34:38.34#ibcon#enter sib2, iclass 23, count 0 2006.189.07:34:38.34#ibcon#flushed, iclass 23, count 0 2006.189.07:34:38.34#ibcon#about to write, iclass 23, count 0 2006.189.07:34:38.34#ibcon#wrote, iclass 23, count 0 2006.189.07:34:38.34#ibcon#about to read 3, iclass 23, count 0 2006.189.07:34:38.36#ibcon#read 3, iclass 23, count 0 2006.189.07:34:38.36#ibcon#about to read 4, iclass 23, count 0 2006.189.07:34:38.36#ibcon#read 4, iclass 23, count 0 2006.189.07:34:38.36#ibcon#about to read 5, iclass 23, count 0 2006.189.07:34:38.36#ibcon#read 5, iclass 23, count 0 2006.189.07:34:38.36#ibcon#about to read 6, iclass 23, count 0 2006.189.07:34:38.36#ibcon#read 6, iclass 23, count 0 2006.189.07:34:38.36#ibcon#end of sib2, iclass 23, count 0 2006.189.07:34:38.36#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:34:38.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:34:38.36#ibcon#[25=USB\r\n] 2006.189.07:34:38.36#ibcon#*before write, iclass 23, count 0 2006.189.07:34:38.36#ibcon#enter sib2, iclass 23, count 0 2006.189.07:34:38.36#ibcon#flushed, iclass 23, count 0 2006.189.07:34:38.36#ibcon#about to write, iclass 23, count 0 2006.189.07:34:38.36#ibcon#wrote, iclass 23, count 0 2006.189.07:34:38.36#ibcon#about to read 3, iclass 23, count 0 2006.189.07:34:38.39#ibcon#read 3, iclass 23, count 0 2006.189.07:34:38.39#ibcon#about to read 4, iclass 23, count 0 2006.189.07:34:38.39#ibcon#read 4, iclass 23, count 0 2006.189.07:34:38.39#ibcon#about to read 5, iclass 23, count 0 2006.189.07:34:38.39#ibcon#read 5, iclass 23, count 0 2006.189.07:34:38.39#ibcon#about to read 6, iclass 23, count 0 2006.189.07:34:38.39#ibcon#read 6, iclass 23, count 0 2006.189.07:34:38.39#ibcon#end of sib2, iclass 23, count 0 2006.189.07:34:38.39#ibcon#*after write, iclass 23, count 0 2006.189.07:34:38.39#ibcon#*before return 0, iclass 23, count 0 2006.189.07:34:38.39#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:38.39#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:38.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:34:38.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:34:38.39$vc4f8/valo=2,572.99 2006.189.07:34:38.39#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:34:38.39#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:34:38.39#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:38.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:38.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:38.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:38.39#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:34:38.39#ibcon#first serial, iclass 25, count 0 2006.189.07:34:38.39#ibcon#enter sib2, iclass 25, count 0 2006.189.07:34:38.39#ibcon#flushed, iclass 25, count 0 2006.189.07:34:38.39#ibcon#about to write, iclass 25, count 0 2006.189.07:34:38.39#ibcon#wrote, iclass 25, count 0 2006.189.07:34:38.39#ibcon#about to read 3, iclass 25, count 0 2006.189.07:34:38.41#ibcon#read 3, iclass 25, count 0 2006.189.07:34:38.41#ibcon#about to read 4, iclass 25, count 0 2006.189.07:34:38.41#ibcon#read 4, iclass 25, count 0 2006.189.07:34:38.41#ibcon#about to read 5, iclass 25, count 0 2006.189.07:34:38.41#ibcon#read 5, iclass 25, count 0 2006.189.07:34:38.41#ibcon#about to read 6, iclass 25, count 0 2006.189.07:34:38.41#ibcon#read 6, iclass 25, count 0 2006.189.07:34:38.41#ibcon#end of sib2, iclass 25, count 0 2006.189.07:34:38.41#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:34:38.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:34:38.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:34:38.41#ibcon#*before write, iclass 25, count 0 2006.189.07:34:38.41#ibcon#enter sib2, iclass 25, count 0 2006.189.07:34:38.41#ibcon#flushed, iclass 25, count 0 2006.189.07:34:38.41#ibcon#about to write, iclass 25, count 0 2006.189.07:34:38.41#ibcon#wrote, iclass 25, count 0 2006.189.07:34:38.41#ibcon#about to read 3, iclass 25, count 0 2006.189.07:34:38.46#ibcon#read 3, iclass 25, count 0 2006.189.07:34:38.46#ibcon#about to read 4, iclass 25, count 0 2006.189.07:34:38.46#ibcon#read 4, iclass 25, count 0 2006.189.07:34:38.46#ibcon#about to read 5, iclass 25, count 0 2006.189.07:34:38.46#ibcon#read 5, iclass 25, count 0 2006.189.07:34:38.46#ibcon#about to read 6, iclass 25, count 0 2006.189.07:34:38.46#ibcon#read 6, iclass 25, count 0 2006.189.07:34:38.46#ibcon#end of sib2, iclass 25, count 0 2006.189.07:34:38.46#ibcon#*after write, iclass 25, count 0 2006.189.07:34:38.46#ibcon#*before return 0, iclass 25, count 0 2006.189.07:34:38.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:38.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:38.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:34:38.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:34:38.46$vc4f8/va=2,7 2006.189.07:34:38.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:34:38.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:34:38.46#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:38.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:38.50#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:38.50#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:38.50#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:34:38.50#ibcon#first serial, iclass 27, count 2 2006.189.07:34:38.50#ibcon#enter sib2, iclass 27, count 2 2006.189.07:34:38.50#ibcon#flushed, iclass 27, count 2 2006.189.07:34:38.50#ibcon#about to write, iclass 27, count 2 2006.189.07:34:38.50#ibcon#wrote, iclass 27, count 2 2006.189.07:34:38.50#ibcon#about to read 3, iclass 27, count 2 2006.189.07:34:38.52#ibcon#read 3, iclass 27, count 2 2006.189.07:34:38.52#ibcon#about to read 4, iclass 27, count 2 2006.189.07:34:38.52#ibcon#read 4, iclass 27, count 2 2006.189.07:34:38.52#ibcon#about to read 5, iclass 27, count 2 2006.189.07:34:38.52#ibcon#read 5, iclass 27, count 2 2006.189.07:34:38.52#ibcon#about to read 6, iclass 27, count 2 2006.189.07:34:38.52#ibcon#read 6, iclass 27, count 2 2006.189.07:34:38.52#ibcon#end of sib2, iclass 27, count 2 2006.189.07:34:38.52#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:34:38.52#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:34:38.52#ibcon#[25=AT02-07\r\n] 2006.189.07:34:38.52#ibcon#*before write, iclass 27, count 2 2006.189.07:34:38.52#ibcon#enter sib2, iclass 27, count 2 2006.189.07:34:38.52#ibcon#flushed, iclass 27, count 2 2006.189.07:34:38.52#ibcon#about to write, iclass 27, count 2 2006.189.07:34:38.52#ibcon#wrote, iclass 27, count 2 2006.189.07:34:38.52#ibcon#about to read 3, iclass 27, count 2 2006.189.07:34:38.55#ibcon#read 3, iclass 27, count 2 2006.189.07:34:38.55#ibcon#about to read 4, iclass 27, count 2 2006.189.07:34:38.55#ibcon#read 4, iclass 27, count 2 2006.189.07:34:38.55#ibcon#about to read 5, iclass 27, count 2 2006.189.07:34:38.55#ibcon#read 5, iclass 27, count 2 2006.189.07:34:38.55#ibcon#about to read 6, iclass 27, count 2 2006.189.07:34:38.55#ibcon#read 6, iclass 27, count 2 2006.189.07:34:38.55#ibcon#end of sib2, iclass 27, count 2 2006.189.07:34:38.55#ibcon#*after write, iclass 27, count 2 2006.189.07:34:38.55#ibcon#*before return 0, iclass 27, count 2 2006.189.07:34:38.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:38.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:38.55#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:34:38.55#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:38.55#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:38.67#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:38.67#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:38.67#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:34:38.67#ibcon#first serial, iclass 27, count 0 2006.189.07:34:38.67#ibcon#enter sib2, iclass 27, count 0 2006.189.07:34:38.67#ibcon#flushed, iclass 27, count 0 2006.189.07:34:38.67#ibcon#about to write, iclass 27, count 0 2006.189.07:34:38.67#ibcon#wrote, iclass 27, count 0 2006.189.07:34:38.67#ibcon#about to read 3, iclass 27, count 0 2006.189.07:34:38.69#ibcon#read 3, iclass 27, count 0 2006.189.07:34:38.69#ibcon#about to read 4, iclass 27, count 0 2006.189.07:34:38.69#ibcon#read 4, iclass 27, count 0 2006.189.07:34:38.69#ibcon#about to read 5, iclass 27, count 0 2006.189.07:34:38.69#ibcon#read 5, iclass 27, count 0 2006.189.07:34:38.69#ibcon#about to read 6, iclass 27, count 0 2006.189.07:34:38.69#ibcon#read 6, iclass 27, count 0 2006.189.07:34:38.69#ibcon#end of sib2, iclass 27, count 0 2006.189.07:34:38.69#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:34:38.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:34:38.69#ibcon#[25=USB\r\n] 2006.189.07:34:38.69#ibcon#*before write, iclass 27, count 0 2006.189.07:34:38.69#ibcon#enter sib2, iclass 27, count 0 2006.189.07:34:38.69#ibcon#flushed, iclass 27, count 0 2006.189.07:34:38.69#ibcon#about to write, iclass 27, count 0 2006.189.07:34:38.69#ibcon#wrote, iclass 27, count 0 2006.189.07:34:38.69#ibcon#about to read 3, iclass 27, count 0 2006.189.07:34:38.72#ibcon#read 3, iclass 27, count 0 2006.189.07:34:38.72#ibcon#about to read 4, iclass 27, count 0 2006.189.07:34:38.72#ibcon#read 4, iclass 27, count 0 2006.189.07:34:38.72#ibcon#about to read 5, iclass 27, count 0 2006.189.07:34:38.72#ibcon#read 5, iclass 27, count 0 2006.189.07:34:38.72#ibcon#about to read 6, iclass 27, count 0 2006.189.07:34:38.72#ibcon#read 6, iclass 27, count 0 2006.189.07:34:38.72#ibcon#end of sib2, iclass 27, count 0 2006.189.07:34:38.72#ibcon#*after write, iclass 27, count 0 2006.189.07:34:38.72#ibcon#*before return 0, iclass 27, count 0 2006.189.07:34:38.72#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:38.72#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:38.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:34:38.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:34:38.72$vc4f8/valo=3,672.99 2006.189.07:34:38.72#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:34:38.72#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:34:38.72#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:38.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:38.72#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:38.72#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:38.72#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:34:38.72#ibcon#first serial, iclass 29, count 0 2006.189.07:34:38.72#ibcon#enter sib2, iclass 29, count 0 2006.189.07:34:38.72#ibcon#flushed, iclass 29, count 0 2006.189.07:34:38.72#ibcon#about to write, iclass 29, count 0 2006.189.07:34:38.72#ibcon#wrote, iclass 29, count 0 2006.189.07:34:38.72#ibcon#about to read 3, iclass 29, count 0 2006.189.07:34:38.74#ibcon#read 3, iclass 29, count 0 2006.189.07:34:38.74#ibcon#about to read 4, iclass 29, count 0 2006.189.07:34:38.74#ibcon#read 4, iclass 29, count 0 2006.189.07:34:38.74#ibcon#about to read 5, iclass 29, count 0 2006.189.07:34:38.74#ibcon#read 5, iclass 29, count 0 2006.189.07:34:38.74#ibcon#about to read 6, iclass 29, count 0 2006.189.07:34:38.74#ibcon#read 6, iclass 29, count 0 2006.189.07:34:38.74#ibcon#end of sib2, iclass 29, count 0 2006.189.07:34:38.74#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:34:38.74#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:34:38.74#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:34:38.74#ibcon#*before write, iclass 29, count 0 2006.189.07:34:38.74#ibcon#enter sib2, iclass 29, count 0 2006.189.07:34:38.74#ibcon#flushed, iclass 29, count 0 2006.189.07:34:38.74#ibcon#about to write, iclass 29, count 0 2006.189.07:34:38.74#ibcon#wrote, iclass 29, count 0 2006.189.07:34:38.74#ibcon#about to read 3, iclass 29, count 0 2006.189.07:34:38.79#ibcon#read 3, iclass 29, count 0 2006.189.07:34:38.79#ibcon#about to read 4, iclass 29, count 0 2006.189.07:34:38.79#ibcon#read 4, iclass 29, count 0 2006.189.07:34:38.79#ibcon#about to read 5, iclass 29, count 0 2006.189.07:34:38.79#ibcon#read 5, iclass 29, count 0 2006.189.07:34:38.79#ibcon#about to read 6, iclass 29, count 0 2006.189.07:34:38.79#ibcon#read 6, iclass 29, count 0 2006.189.07:34:38.79#ibcon#end of sib2, iclass 29, count 0 2006.189.07:34:38.79#ibcon#*after write, iclass 29, count 0 2006.189.07:34:38.79#ibcon#*before return 0, iclass 29, count 0 2006.189.07:34:38.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:38.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:38.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:34:38.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:34:38.79$vc4f8/va=3,6 2006.189.07:34:38.79#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.07:34:38.79#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.07:34:38.79#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:38.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:38.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:38.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:38.83#ibcon#enter wrdev, iclass 31, count 2 2006.189.07:34:38.83#ibcon#first serial, iclass 31, count 2 2006.189.07:34:38.83#ibcon#enter sib2, iclass 31, count 2 2006.189.07:34:38.83#ibcon#flushed, iclass 31, count 2 2006.189.07:34:38.83#ibcon#about to write, iclass 31, count 2 2006.189.07:34:38.83#ibcon#wrote, iclass 31, count 2 2006.189.07:34:38.83#ibcon#about to read 3, iclass 31, count 2 2006.189.07:34:38.85#ibcon#read 3, iclass 31, count 2 2006.189.07:34:38.85#ibcon#about to read 4, iclass 31, count 2 2006.189.07:34:38.85#ibcon#read 4, iclass 31, count 2 2006.189.07:34:38.85#ibcon#about to read 5, iclass 31, count 2 2006.189.07:34:38.85#ibcon#read 5, iclass 31, count 2 2006.189.07:34:38.85#ibcon#about to read 6, iclass 31, count 2 2006.189.07:34:38.85#ibcon#read 6, iclass 31, count 2 2006.189.07:34:38.85#ibcon#end of sib2, iclass 31, count 2 2006.189.07:34:38.85#ibcon#*mode == 0, iclass 31, count 2 2006.189.07:34:38.85#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.07:34:38.85#ibcon#[25=AT03-06\r\n] 2006.189.07:34:38.85#ibcon#*before write, iclass 31, count 2 2006.189.07:34:38.85#ibcon#enter sib2, iclass 31, count 2 2006.189.07:34:38.85#ibcon#flushed, iclass 31, count 2 2006.189.07:34:38.85#ibcon#about to write, iclass 31, count 2 2006.189.07:34:38.85#ibcon#wrote, iclass 31, count 2 2006.189.07:34:38.85#ibcon#about to read 3, iclass 31, count 2 2006.189.07:34:38.88#ibcon#read 3, iclass 31, count 2 2006.189.07:34:38.88#ibcon#about to read 4, iclass 31, count 2 2006.189.07:34:38.88#ibcon#read 4, iclass 31, count 2 2006.189.07:34:38.88#ibcon#about to read 5, iclass 31, count 2 2006.189.07:34:38.88#ibcon#read 5, iclass 31, count 2 2006.189.07:34:38.88#ibcon#about to read 6, iclass 31, count 2 2006.189.07:34:38.88#ibcon#read 6, iclass 31, count 2 2006.189.07:34:38.88#ibcon#end of sib2, iclass 31, count 2 2006.189.07:34:38.88#ibcon#*after write, iclass 31, count 2 2006.189.07:34:38.88#ibcon#*before return 0, iclass 31, count 2 2006.189.07:34:38.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:38.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:38.88#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.07:34:38.88#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:38.88#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:39.00#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:39.00#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:39.00#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:34:39.00#ibcon#first serial, iclass 31, count 0 2006.189.07:34:39.00#ibcon#enter sib2, iclass 31, count 0 2006.189.07:34:39.00#ibcon#flushed, iclass 31, count 0 2006.189.07:34:39.00#ibcon#about to write, iclass 31, count 0 2006.189.07:34:39.00#ibcon#wrote, iclass 31, count 0 2006.189.07:34:39.00#ibcon#about to read 3, iclass 31, count 0 2006.189.07:34:39.02#ibcon#read 3, iclass 31, count 0 2006.189.07:34:39.02#ibcon#about to read 4, iclass 31, count 0 2006.189.07:34:39.02#ibcon#read 4, iclass 31, count 0 2006.189.07:34:39.02#ibcon#about to read 5, iclass 31, count 0 2006.189.07:34:39.02#ibcon#read 5, iclass 31, count 0 2006.189.07:34:39.02#ibcon#about to read 6, iclass 31, count 0 2006.189.07:34:39.02#ibcon#read 6, iclass 31, count 0 2006.189.07:34:39.02#ibcon#end of sib2, iclass 31, count 0 2006.189.07:34:39.02#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:34:39.02#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:34:39.02#ibcon#[25=USB\r\n] 2006.189.07:34:39.02#ibcon#*before write, iclass 31, count 0 2006.189.07:34:39.02#ibcon#enter sib2, iclass 31, count 0 2006.189.07:34:39.02#ibcon#flushed, iclass 31, count 0 2006.189.07:34:39.02#ibcon#about to write, iclass 31, count 0 2006.189.07:34:39.02#ibcon#wrote, iclass 31, count 0 2006.189.07:34:39.02#ibcon#about to read 3, iclass 31, count 0 2006.189.07:34:39.05#ibcon#read 3, iclass 31, count 0 2006.189.07:34:39.05#ibcon#about to read 4, iclass 31, count 0 2006.189.07:34:39.05#ibcon#read 4, iclass 31, count 0 2006.189.07:34:39.05#ibcon#about to read 5, iclass 31, count 0 2006.189.07:34:39.05#ibcon#read 5, iclass 31, count 0 2006.189.07:34:39.05#ibcon#about to read 6, iclass 31, count 0 2006.189.07:34:39.05#ibcon#read 6, iclass 31, count 0 2006.189.07:34:39.05#ibcon#end of sib2, iclass 31, count 0 2006.189.07:34:39.05#ibcon#*after write, iclass 31, count 0 2006.189.07:34:39.05#ibcon#*before return 0, iclass 31, count 0 2006.189.07:34:39.05#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:39.05#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:39.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:34:39.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:34:39.05$vc4f8/valo=4,832.99 2006.189.07:34:39.05#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:34:39.05#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:34:39.05#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:39.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:39.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:39.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:39.05#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:34:39.05#ibcon#first serial, iclass 33, count 0 2006.189.07:34:39.05#ibcon#enter sib2, iclass 33, count 0 2006.189.07:34:39.05#ibcon#flushed, iclass 33, count 0 2006.189.07:34:39.05#ibcon#about to write, iclass 33, count 0 2006.189.07:34:39.05#ibcon#wrote, iclass 33, count 0 2006.189.07:34:39.05#ibcon#about to read 3, iclass 33, count 0 2006.189.07:34:39.07#ibcon#read 3, iclass 33, count 0 2006.189.07:34:39.07#ibcon#about to read 4, iclass 33, count 0 2006.189.07:34:39.07#ibcon#read 4, iclass 33, count 0 2006.189.07:34:39.07#ibcon#about to read 5, iclass 33, count 0 2006.189.07:34:39.07#ibcon#read 5, iclass 33, count 0 2006.189.07:34:39.07#ibcon#about to read 6, iclass 33, count 0 2006.189.07:34:39.07#ibcon#read 6, iclass 33, count 0 2006.189.07:34:39.07#ibcon#end of sib2, iclass 33, count 0 2006.189.07:34:39.07#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:34:39.07#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:34:39.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:34:39.07#ibcon#*before write, iclass 33, count 0 2006.189.07:34:39.07#ibcon#enter sib2, iclass 33, count 0 2006.189.07:34:39.07#ibcon#flushed, iclass 33, count 0 2006.189.07:34:39.07#ibcon#about to write, iclass 33, count 0 2006.189.07:34:39.07#ibcon#wrote, iclass 33, count 0 2006.189.07:34:39.07#ibcon#about to read 3, iclass 33, count 0 2006.189.07:34:39.11#ibcon#read 3, iclass 33, count 0 2006.189.07:34:39.11#ibcon#about to read 4, iclass 33, count 0 2006.189.07:34:39.11#ibcon#read 4, iclass 33, count 0 2006.189.07:34:39.11#ibcon#about to read 5, iclass 33, count 0 2006.189.07:34:39.11#ibcon#read 5, iclass 33, count 0 2006.189.07:34:39.11#ibcon#about to read 6, iclass 33, count 0 2006.189.07:34:39.11#ibcon#read 6, iclass 33, count 0 2006.189.07:34:39.11#ibcon#end of sib2, iclass 33, count 0 2006.189.07:34:39.11#ibcon#*after write, iclass 33, count 0 2006.189.07:34:39.11#ibcon#*before return 0, iclass 33, count 0 2006.189.07:34:39.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:39.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:39.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:34:39.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:34:39.11$vc4f8/va=4,7 2006.189.07:34:39.11#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:34:39.11#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:34:39.11#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:39.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:39.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:39.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:39.17#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:34:39.17#ibcon#first serial, iclass 35, count 2 2006.189.07:34:39.17#ibcon#enter sib2, iclass 35, count 2 2006.189.07:34:39.17#ibcon#flushed, iclass 35, count 2 2006.189.07:34:39.17#ibcon#about to write, iclass 35, count 2 2006.189.07:34:39.17#ibcon#wrote, iclass 35, count 2 2006.189.07:34:39.17#ibcon#about to read 3, iclass 35, count 2 2006.189.07:34:39.19#ibcon#read 3, iclass 35, count 2 2006.189.07:34:39.19#ibcon#about to read 4, iclass 35, count 2 2006.189.07:34:39.19#ibcon#read 4, iclass 35, count 2 2006.189.07:34:39.19#ibcon#about to read 5, iclass 35, count 2 2006.189.07:34:39.19#ibcon#read 5, iclass 35, count 2 2006.189.07:34:39.19#ibcon#about to read 6, iclass 35, count 2 2006.189.07:34:39.19#ibcon#read 6, iclass 35, count 2 2006.189.07:34:39.19#ibcon#end of sib2, iclass 35, count 2 2006.189.07:34:39.19#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:34:39.19#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:34:39.19#ibcon#[25=AT04-07\r\n] 2006.189.07:34:39.19#ibcon#*before write, iclass 35, count 2 2006.189.07:34:39.19#ibcon#enter sib2, iclass 35, count 2 2006.189.07:34:39.19#ibcon#flushed, iclass 35, count 2 2006.189.07:34:39.19#ibcon#about to write, iclass 35, count 2 2006.189.07:34:39.19#ibcon#wrote, iclass 35, count 2 2006.189.07:34:39.19#ibcon#about to read 3, iclass 35, count 2 2006.189.07:34:39.22#ibcon#read 3, iclass 35, count 2 2006.189.07:34:39.22#ibcon#about to read 4, iclass 35, count 2 2006.189.07:34:39.22#ibcon#read 4, iclass 35, count 2 2006.189.07:34:39.22#ibcon#about to read 5, iclass 35, count 2 2006.189.07:34:39.22#ibcon#read 5, iclass 35, count 2 2006.189.07:34:39.22#ibcon#about to read 6, iclass 35, count 2 2006.189.07:34:39.22#ibcon#read 6, iclass 35, count 2 2006.189.07:34:39.22#ibcon#end of sib2, iclass 35, count 2 2006.189.07:34:39.22#ibcon#*after write, iclass 35, count 2 2006.189.07:34:39.22#ibcon#*before return 0, iclass 35, count 2 2006.189.07:34:39.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:39.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:39.22#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:34:39.22#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:39.22#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:39.34#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:39.34#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:39.34#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:34:39.34#ibcon#first serial, iclass 35, count 0 2006.189.07:34:39.34#ibcon#enter sib2, iclass 35, count 0 2006.189.07:34:39.34#ibcon#flushed, iclass 35, count 0 2006.189.07:34:39.34#ibcon#about to write, iclass 35, count 0 2006.189.07:34:39.34#ibcon#wrote, iclass 35, count 0 2006.189.07:34:39.34#ibcon#about to read 3, iclass 35, count 0 2006.189.07:34:39.36#ibcon#read 3, iclass 35, count 0 2006.189.07:34:39.36#ibcon#about to read 4, iclass 35, count 0 2006.189.07:34:39.36#ibcon#read 4, iclass 35, count 0 2006.189.07:34:39.36#ibcon#about to read 5, iclass 35, count 0 2006.189.07:34:39.36#ibcon#read 5, iclass 35, count 0 2006.189.07:34:39.36#ibcon#about to read 6, iclass 35, count 0 2006.189.07:34:39.36#ibcon#read 6, iclass 35, count 0 2006.189.07:34:39.36#ibcon#end of sib2, iclass 35, count 0 2006.189.07:34:39.36#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:34:39.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:34:39.36#ibcon#[25=USB\r\n] 2006.189.07:34:39.36#ibcon#*before write, iclass 35, count 0 2006.189.07:34:39.36#ibcon#enter sib2, iclass 35, count 0 2006.189.07:34:39.36#ibcon#flushed, iclass 35, count 0 2006.189.07:34:39.36#ibcon#about to write, iclass 35, count 0 2006.189.07:34:39.36#ibcon#wrote, iclass 35, count 0 2006.189.07:34:39.36#ibcon#about to read 3, iclass 35, count 0 2006.189.07:34:39.39#ibcon#read 3, iclass 35, count 0 2006.189.07:34:39.39#ibcon#about to read 4, iclass 35, count 0 2006.189.07:34:39.39#ibcon#read 4, iclass 35, count 0 2006.189.07:34:39.39#ibcon#about to read 5, iclass 35, count 0 2006.189.07:34:39.39#ibcon#read 5, iclass 35, count 0 2006.189.07:34:39.39#ibcon#about to read 6, iclass 35, count 0 2006.189.07:34:39.39#ibcon#read 6, iclass 35, count 0 2006.189.07:34:39.39#ibcon#end of sib2, iclass 35, count 0 2006.189.07:34:39.39#ibcon#*after write, iclass 35, count 0 2006.189.07:34:39.39#ibcon#*before return 0, iclass 35, count 0 2006.189.07:34:39.39#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:39.39#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:39.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:34:39.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:34:39.39$vc4f8/valo=5,652.99 2006.189.07:34:39.39#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:34:39.39#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:34:39.39#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:39.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:39.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:39.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:39.39#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:34:39.39#ibcon#first serial, iclass 37, count 0 2006.189.07:34:39.39#ibcon#enter sib2, iclass 37, count 0 2006.189.07:34:39.39#ibcon#flushed, iclass 37, count 0 2006.189.07:34:39.39#ibcon#about to write, iclass 37, count 0 2006.189.07:34:39.39#ibcon#wrote, iclass 37, count 0 2006.189.07:34:39.39#ibcon#about to read 3, iclass 37, count 0 2006.189.07:34:39.41#ibcon#read 3, iclass 37, count 0 2006.189.07:34:39.41#ibcon#about to read 4, iclass 37, count 0 2006.189.07:34:39.41#ibcon#read 4, iclass 37, count 0 2006.189.07:34:39.41#ibcon#about to read 5, iclass 37, count 0 2006.189.07:34:39.41#ibcon#read 5, iclass 37, count 0 2006.189.07:34:39.41#ibcon#about to read 6, iclass 37, count 0 2006.189.07:34:39.41#ibcon#read 6, iclass 37, count 0 2006.189.07:34:39.41#ibcon#end of sib2, iclass 37, count 0 2006.189.07:34:39.41#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:34:39.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:34:39.41#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:34:39.41#ibcon#*before write, iclass 37, count 0 2006.189.07:34:39.41#ibcon#enter sib2, iclass 37, count 0 2006.189.07:34:39.41#ibcon#flushed, iclass 37, count 0 2006.189.07:34:39.41#ibcon#about to write, iclass 37, count 0 2006.189.07:34:39.41#ibcon#wrote, iclass 37, count 0 2006.189.07:34:39.41#ibcon#about to read 3, iclass 37, count 0 2006.189.07:34:39.45#ibcon#read 3, iclass 37, count 0 2006.189.07:34:39.45#ibcon#about to read 4, iclass 37, count 0 2006.189.07:34:39.45#ibcon#read 4, iclass 37, count 0 2006.189.07:34:39.45#ibcon#about to read 5, iclass 37, count 0 2006.189.07:34:39.45#ibcon#read 5, iclass 37, count 0 2006.189.07:34:39.45#ibcon#about to read 6, iclass 37, count 0 2006.189.07:34:39.45#ibcon#read 6, iclass 37, count 0 2006.189.07:34:39.45#ibcon#end of sib2, iclass 37, count 0 2006.189.07:34:39.45#ibcon#*after write, iclass 37, count 0 2006.189.07:34:39.45#ibcon#*before return 0, iclass 37, count 0 2006.189.07:34:39.45#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:39.45#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:39.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:34:39.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:34:39.45$vc4f8/va=5,7 2006.189.07:34:39.45#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:34:39.45#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:34:39.45#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:39.45#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:39.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:39.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:39.51#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:34:39.51#ibcon#first serial, iclass 39, count 2 2006.189.07:34:39.51#ibcon#enter sib2, iclass 39, count 2 2006.189.07:34:39.51#ibcon#flushed, iclass 39, count 2 2006.189.07:34:39.51#ibcon#about to write, iclass 39, count 2 2006.189.07:34:39.51#ibcon#wrote, iclass 39, count 2 2006.189.07:34:39.51#ibcon#about to read 3, iclass 39, count 2 2006.189.07:34:39.53#ibcon#read 3, iclass 39, count 2 2006.189.07:34:39.53#ibcon#about to read 4, iclass 39, count 2 2006.189.07:34:39.53#ibcon#read 4, iclass 39, count 2 2006.189.07:34:39.53#ibcon#about to read 5, iclass 39, count 2 2006.189.07:34:39.53#ibcon#read 5, iclass 39, count 2 2006.189.07:34:39.53#ibcon#about to read 6, iclass 39, count 2 2006.189.07:34:39.53#ibcon#read 6, iclass 39, count 2 2006.189.07:34:39.53#ibcon#end of sib2, iclass 39, count 2 2006.189.07:34:39.53#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:34:39.53#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:34:39.53#ibcon#[25=AT05-07\r\n] 2006.189.07:34:39.53#ibcon#*before write, iclass 39, count 2 2006.189.07:34:39.53#ibcon#enter sib2, iclass 39, count 2 2006.189.07:34:39.53#ibcon#flushed, iclass 39, count 2 2006.189.07:34:39.53#ibcon#about to write, iclass 39, count 2 2006.189.07:34:39.53#ibcon#wrote, iclass 39, count 2 2006.189.07:34:39.53#ibcon#about to read 3, iclass 39, count 2 2006.189.07:34:39.56#ibcon#read 3, iclass 39, count 2 2006.189.07:34:39.56#ibcon#about to read 4, iclass 39, count 2 2006.189.07:34:39.56#ibcon#read 4, iclass 39, count 2 2006.189.07:34:39.56#ibcon#about to read 5, iclass 39, count 2 2006.189.07:34:39.56#ibcon#read 5, iclass 39, count 2 2006.189.07:34:39.56#ibcon#about to read 6, iclass 39, count 2 2006.189.07:34:39.56#ibcon#read 6, iclass 39, count 2 2006.189.07:34:39.56#ibcon#end of sib2, iclass 39, count 2 2006.189.07:34:39.56#ibcon#*after write, iclass 39, count 2 2006.189.07:34:39.56#ibcon#*before return 0, iclass 39, count 2 2006.189.07:34:39.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:39.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:39.56#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:34:39.56#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:39.56#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:39.68#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:39.68#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:39.68#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:34:39.68#ibcon#first serial, iclass 39, count 0 2006.189.07:34:39.68#ibcon#enter sib2, iclass 39, count 0 2006.189.07:34:39.68#ibcon#flushed, iclass 39, count 0 2006.189.07:34:39.68#ibcon#about to write, iclass 39, count 0 2006.189.07:34:39.68#ibcon#wrote, iclass 39, count 0 2006.189.07:34:39.68#ibcon#about to read 3, iclass 39, count 0 2006.189.07:34:39.70#ibcon#read 3, iclass 39, count 0 2006.189.07:34:39.70#ibcon#about to read 4, iclass 39, count 0 2006.189.07:34:39.70#ibcon#read 4, iclass 39, count 0 2006.189.07:34:39.70#ibcon#about to read 5, iclass 39, count 0 2006.189.07:34:39.70#ibcon#read 5, iclass 39, count 0 2006.189.07:34:39.70#ibcon#about to read 6, iclass 39, count 0 2006.189.07:34:39.70#ibcon#read 6, iclass 39, count 0 2006.189.07:34:39.70#ibcon#end of sib2, iclass 39, count 0 2006.189.07:34:39.70#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:34:39.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:34:39.70#ibcon#[25=USB\r\n] 2006.189.07:34:39.70#ibcon#*before write, iclass 39, count 0 2006.189.07:34:39.70#ibcon#enter sib2, iclass 39, count 0 2006.189.07:34:39.70#ibcon#flushed, iclass 39, count 0 2006.189.07:34:39.70#ibcon#about to write, iclass 39, count 0 2006.189.07:34:39.70#ibcon#wrote, iclass 39, count 0 2006.189.07:34:39.70#ibcon#about to read 3, iclass 39, count 0 2006.189.07:34:39.73#ibcon#read 3, iclass 39, count 0 2006.189.07:34:39.73#ibcon#about to read 4, iclass 39, count 0 2006.189.07:34:39.73#ibcon#read 4, iclass 39, count 0 2006.189.07:34:39.73#ibcon#about to read 5, iclass 39, count 0 2006.189.07:34:39.73#ibcon#read 5, iclass 39, count 0 2006.189.07:34:39.73#ibcon#about to read 6, iclass 39, count 0 2006.189.07:34:39.73#ibcon#read 6, iclass 39, count 0 2006.189.07:34:39.73#ibcon#end of sib2, iclass 39, count 0 2006.189.07:34:39.73#ibcon#*after write, iclass 39, count 0 2006.189.07:34:39.73#ibcon#*before return 0, iclass 39, count 0 2006.189.07:34:39.73#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:39.73#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:39.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:34:39.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:34:39.73$vc4f8/valo=6,772.99 2006.189.07:34:39.73#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:34:39.73#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:34:39.73#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:39.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:39.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:39.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:39.73#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:34:39.73#ibcon#first serial, iclass 3, count 0 2006.189.07:34:39.73#ibcon#enter sib2, iclass 3, count 0 2006.189.07:34:39.73#ibcon#flushed, iclass 3, count 0 2006.189.07:34:39.73#ibcon#about to write, iclass 3, count 0 2006.189.07:34:39.73#ibcon#wrote, iclass 3, count 0 2006.189.07:34:39.73#ibcon#about to read 3, iclass 3, count 0 2006.189.07:34:39.75#ibcon#read 3, iclass 3, count 0 2006.189.07:34:39.75#ibcon#about to read 4, iclass 3, count 0 2006.189.07:34:39.75#ibcon#read 4, iclass 3, count 0 2006.189.07:34:39.75#ibcon#about to read 5, iclass 3, count 0 2006.189.07:34:39.75#ibcon#read 5, iclass 3, count 0 2006.189.07:34:39.75#ibcon#about to read 6, iclass 3, count 0 2006.189.07:34:39.75#ibcon#read 6, iclass 3, count 0 2006.189.07:34:39.75#ibcon#end of sib2, iclass 3, count 0 2006.189.07:34:39.75#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:34:39.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:34:39.75#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:34:39.75#ibcon#*before write, iclass 3, count 0 2006.189.07:34:39.75#ibcon#enter sib2, iclass 3, count 0 2006.189.07:34:39.75#ibcon#flushed, iclass 3, count 0 2006.189.07:34:39.75#ibcon#about to write, iclass 3, count 0 2006.189.07:34:39.75#ibcon#wrote, iclass 3, count 0 2006.189.07:34:39.75#ibcon#about to read 3, iclass 3, count 0 2006.189.07:34:39.79#ibcon#read 3, iclass 3, count 0 2006.189.07:34:39.79#ibcon#about to read 4, iclass 3, count 0 2006.189.07:34:39.79#ibcon#read 4, iclass 3, count 0 2006.189.07:34:39.79#ibcon#about to read 5, iclass 3, count 0 2006.189.07:34:39.79#ibcon#read 5, iclass 3, count 0 2006.189.07:34:39.79#ibcon#about to read 6, iclass 3, count 0 2006.189.07:34:39.79#ibcon#read 6, iclass 3, count 0 2006.189.07:34:39.79#ibcon#end of sib2, iclass 3, count 0 2006.189.07:34:39.79#ibcon#*after write, iclass 3, count 0 2006.189.07:34:39.79#ibcon#*before return 0, iclass 3, count 0 2006.189.07:34:39.79#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:39.79#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:39.79#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:34:39.79#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:34:39.79$vc4f8/va=6,6 2006.189.07:34:39.79#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:34:39.79#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:34:39.79#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:39.79#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:39.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:39.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:39.85#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:34:39.85#ibcon#first serial, iclass 5, count 2 2006.189.07:34:39.85#ibcon#enter sib2, iclass 5, count 2 2006.189.07:34:39.85#ibcon#flushed, iclass 5, count 2 2006.189.07:34:39.85#ibcon#about to write, iclass 5, count 2 2006.189.07:34:39.85#ibcon#wrote, iclass 5, count 2 2006.189.07:34:39.85#ibcon#about to read 3, iclass 5, count 2 2006.189.07:34:39.87#ibcon#read 3, iclass 5, count 2 2006.189.07:34:39.87#ibcon#about to read 4, iclass 5, count 2 2006.189.07:34:39.87#ibcon#read 4, iclass 5, count 2 2006.189.07:34:39.87#ibcon#about to read 5, iclass 5, count 2 2006.189.07:34:39.87#ibcon#read 5, iclass 5, count 2 2006.189.07:34:39.87#ibcon#about to read 6, iclass 5, count 2 2006.189.07:34:39.87#ibcon#read 6, iclass 5, count 2 2006.189.07:34:39.87#ibcon#end of sib2, iclass 5, count 2 2006.189.07:34:39.87#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:34:39.87#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:34:39.87#ibcon#[25=AT06-06\r\n] 2006.189.07:34:39.87#ibcon#*before write, iclass 5, count 2 2006.189.07:34:39.87#ibcon#enter sib2, iclass 5, count 2 2006.189.07:34:39.87#ibcon#flushed, iclass 5, count 2 2006.189.07:34:39.87#ibcon#about to write, iclass 5, count 2 2006.189.07:34:39.87#ibcon#wrote, iclass 5, count 2 2006.189.07:34:39.87#ibcon#about to read 3, iclass 5, count 2 2006.189.07:34:39.90#ibcon#read 3, iclass 5, count 2 2006.189.07:34:39.90#ibcon#about to read 4, iclass 5, count 2 2006.189.07:34:39.90#ibcon#read 4, iclass 5, count 2 2006.189.07:34:39.90#ibcon#about to read 5, iclass 5, count 2 2006.189.07:34:39.90#ibcon#read 5, iclass 5, count 2 2006.189.07:34:39.90#ibcon#about to read 6, iclass 5, count 2 2006.189.07:34:39.90#ibcon#read 6, iclass 5, count 2 2006.189.07:34:39.90#ibcon#end of sib2, iclass 5, count 2 2006.189.07:34:39.90#ibcon#*after write, iclass 5, count 2 2006.189.07:34:39.90#ibcon#*before return 0, iclass 5, count 2 2006.189.07:34:39.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:39.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:39.90#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:34:39.90#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:39.90#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:40.02#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:40.02#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:40.02#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:34:40.02#ibcon#first serial, iclass 5, count 0 2006.189.07:34:40.02#ibcon#enter sib2, iclass 5, count 0 2006.189.07:34:40.02#ibcon#flushed, iclass 5, count 0 2006.189.07:34:40.02#ibcon#about to write, iclass 5, count 0 2006.189.07:34:40.02#ibcon#wrote, iclass 5, count 0 2006.189.07:34:40.02#ibcon#about to read 3, iclass 5, count 0 2006.189.07:34:40.04#ibcon#read 3, iclass 5, count 0 2006.189.07:34:40.04#ibcon#about to read 4, iclass 5, count 0 2006.189.07:34:40.04#ibcon#read 4, iclass 5, count 0 2006.189.07:34:40.04#ibcon#about to read 5, iclass 5, count 0 2006.189.07:34:40.04#ibcon#read 5, iclass 5, count 0 2006.189.07:34:40.04#ibcon#about to read 6, iclass 5, count 0 2006.189.07:34:40.04#ibcon#read 6, iclass 5, count 0 2006.189.07:34:40.04#ibcon#end of sib2, iclass 5, count 0 2006.189.07:34:40.04#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:34:40.04#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:34:40.04#ibcon#[25=USB\r\n] 2006.189.07:34:40.04#ibcon#*before write, iclass 5, count 0 2006.189.07:34:40.04#ibcon#enter sib2, iclass 5, count 0 2006.189.07:34:40.04#ibcon#flushed, iclass 5, count 0 2006.189.07:34:40.04#ibcon#about to write, iclass 5, count 0 2006.189.07:34:40.04#ibcon#wrote, iclass 5, count 0 2006.189.07:34:40.04#ibcon#about to read 3, iclass 5, count 0 2006.189.07:34:40.07#ibcon#read 3, iclass 5, count 0 2006.189.07:34:40.07#ibcon#about to read 4, iclass 5, count 0 2006.189.07:34:40.07#ibcon#read 4, iclass 5, count 0 2006.189.07:34:40.07#ibcon#about to read 5, iclass 5, count 0 2006.189.07:34:40.07#ibcon#read 5, iclass 5, count 0 2006.189.07:34:40.07#ibcon#about to read 6, iclass 5, count 0 2006.189.07:34:40.07#ibcon#read 6, iclass 5, count 0 2006.189.07:34:40.07#ibcon#end of sib2, iclass 5, count 0 2006.189.07:34:40.07#ibcon#*after write, iclass 5, count 0 2006.189.07:34:40.07#ibcon#*before return 0, iclass 5, count 0 2006.189.07:34:40.07#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:40.07#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:40.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:34:40.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:34:40.07$vc4f8/valo=7,832.99 2006.189.07:34:40.07#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:34:40.07#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:34:40.07#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:40.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:40.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:40.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:40.07#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:34:40.07#ibcon#first serial, iclass 7, count 0 2006.189.07:34:40.07#ibcon#enter sib2, iclass 7, count 0 2006.189.07:34:40.07#ibcon#flushed, iclass 7, count 0 2006.189.07:34:40.07#ibcon#about to write, iclass 7, count 0 2006.189.07:34:40.07#ibcon#wrote, iclass 7, count 0 2006.189.07:34:40.07#ibcon#about to read 3, iclass 7, count 0 2006.189.07:34:40.09#ibcon#read 3, iclass 7, count 0 2006.189.07:34:40.09#ibcon#about to read 4, iclass 7, count 0 2006.189.07:34:40.09#ibcon#read 4, iclass 7, count 0 2006.189.07:34:40.09#ibcon#about to read 5, iclass 7, count 0 2006.189.07:34:40.09#ibcon#read 5, iclass 7, count 0 2006.189.07:34:40.09#ibcon#about to read 6, iclass 7, count 0 2006.189.07:34:40.09#ibcon#read 6, iclass 7, count 0 2006.189.07:34:40.09#ibcon#end of sib2, iclass 7, count 0 2006.189.07:34:40.09#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:34:40.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:34:40.09#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:34:40.09#ibcon#*before write, iclass 7, count 0 2006.189.07:34:40.09#ibcon#enter sib2, iclass 7, count 0 2006.189.07:34:40.09#ibcon#flushed, iclass 7, count 0 2006.189.07:34:40.09#ibcon#about to write, iclass 7, count 0 2006.189.07:34:40.09#ibcon#wrote, iclass 7, count 0 2006.189.07:34:40.09#ibcon#about to read 3, iclass 7, count 0 2006.189.07:34:40.13#ibcon#read 3, iclass 7, count 0 2006.189.07:34:40.13#ibcon#about to read 4, iclass 7, count 0 2006.189.07:34:40.13#ibcon#read 4, iclass 7, count 0 2006.189.07:34:40.13#ibcon#about to read 5, iclass 7, count 0 2006.189.07:34:40.13#ibcon#read 5, iclass 7, count 0 2006.189.07:34:40.13#ibcon#about to read 6, iclass 7, count 0 2006.189.07:34:40.13#ibcon#read 6, iclass 7, count 0 2006.189.07:34:40.13#ibcon#end of sib2, iclass 7, count 0 2006.189.07:34:40.13#ibcon#*after write, iclass 7, count 0 2006.189.07:34:40.13#ibcon#*before return 0, iclass 7, count 0 2006.189.07:34:40.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:40.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:40.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:34:40.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:34:40.13$vc4f8/va=7,6 2006.189.07:34:40.13#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:34:40.13#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:34:40.13#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:40.13#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:34:40.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:34:40.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:34:40.19#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:34:40.19#ibcon#first serial, iclass 11, count 2 2006.189.07:34:40.19#ibcon#enter sib2, iclass 11, count 2 2006.189.07:34:40.19#ibcon#flushed, iclass 11, count 2 2006.189.07:34:40.19#ibcon#about to write, iclass 11, count 2 2006.189.07:34:40.19#ibcon#wrote, iclass 11, count 2 2006.189.07:34:40.19#ibcon#about to read 3, iclass 11, count 2 2006.189.07:34:40.21#ibcon#read 3, iclass 11, count 2 2006.189.07:34:40.21#ibcon#about to read 4, iclass 11, count 2 2006.189.07:34:40.21#ibcon#read 4, iclass 11, count 2 2006.189.07:34:40.21#ibcon#about to read 5, iclass 11, count 2 2006.189.07:34:40.21#ibcon#read 5, iclass 11, count 2 2006.189.07:34:40.21#ibcon#about to read 6, iclass 11, count 2 2006.189.07:34:40.21#ibcon#read 6, iclass 11, count 2 2006.189.07:34:40.21#ibcon#end of sib2, iclass 11, count 2 2006.189.07:34:40.21#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:34:40.21#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:34:40.21#ibcon#[25=AT07-06\r\n] 2006.189.07:34:40.21#ibcon#*before write, iclass 11, count 2 2006.189.07:34:40.21#ibcon#enter sib2, iclass 11, count 2 2006.189.07:34:40.21#ibcon#flushed, iclass 11, count 2 2006.189.07:34:40.21#ibcon#about to write, iclass 11, count 2 2006.189.07:34:40.21#ibcon#wrote, iclass 11, count 2 2006.189.07:34:40.21#ibcon#about to read 3, iclass 11, count 2 2006.189.07:34:40.24#ibcon#read 3, iclass 11, count 2 2006.189.07:34:40.24#ibcon#about to read 4, iclass 11, count 2 2006.189.07:34:40.24#ibcon#read 4, iclass 11, count 2 2006.189.07:34:40.24#ibcon#about to read 5, iclass 11, count 2 2006.189.07:34:40.24#ibcon#read 5, iclass 11, count 2 2006.189.07:34:40.24#ibcon#about to read 6, iclass 11, count 2 2006.189.07:34:40.24#ibcon#read 6, iclass 11, count 2 2006.189.07:34:40.24#ibcon#end of sib2, iclass 11, count 2 2006.189.07:34:40.24#ibcon#*after write, iclass 11, count 2 2006.189.07:34:40.24#ibcon#*before return 0, iclass 11, count 2 2006.189.07:34:40.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:34:40.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:34:40.24#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:34:40.24#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:40.24#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:34:40.36#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:34:40.36#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:34:40.36#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:34:40.36#ibcon#first serial, iclass 11, count 0 2006.189.07:34:40.36#ibcon#enter sib2, iclass 11, count 0 2006.189.07:34:40.36#ibcon#flushed, iclass 11, count 0 2006.189.07:34:40.36#ibcon#about to write, iclass 11, count 0 2006.189.07:34:40.36#ibcon#wrote, iclass 11, count 0 2006.189.07:34:40.36#ibcon#about to read 3, iclass 11, count 0 2006.189.07:34:40.38#ibcon#read 3, iclass 11, count 0 2006.189.07:34:40.38#ibcon#about to read 4, iclass 11, count 0 2006.189.07:34:40.38#ibcon#read 4, iclass 11, count 0 2006.189.07:34:40.38#ibcon#about to read 5, iclass 11, count 0 2006.189.07:34:40.38#ibcon#read 5, iclass 11, count 0 2006.189.07:34:40.38#ibcon#about to read 6, iclass 11, count 0 2006.189.07:34:40.38#ibcon#read 6, iclass 11, count 0 2006.189.07:34:40.38#ibcon#end of sib2, iclass 11, count 0 2006.189.07:34:40.38#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:34:40.38#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:34:40.38#ibcon#[25=USB\r\n] 2006.189.07:34:40.38#ibcon#*before write, iclass 11, count 0 2006.189.07:34:40.38#ibcon#enter sib2, iclass 11, count 0 2006.189.07:34:40.38#ibcon#flushed, iclass 11, count 0 2006.189.07:34:40.38#ibcon#about to write, iclass 11, count 0 2006.189.07:34:40.38#ibcon#wrote, iclass 11, count 0 2006.189.07:34:40.38#ibcon#about to read 3, iclass 11, count 0 2006.189.07:34:40.41#ibcon#read 3, iclass 11, count 0 2006.189.07:34:40.41#ibcon#about to read 4, iclass 11, count 0 2006.189.07:34:40.41#ibcon#read 4, iclass 11, count 0 2006.189.07:34:40.41#ibcon#about to read 5, iclass 11, count 0 2006.189.07:34:40.41#ibcon#read 5, iclass 11, count 0 2006.189.07:34:40.41#ibcon#about to read 6, iclass 11, count 0 2006.189.07:34:40.41#ibcon#read 6, iclass 11, count 0 2006.189.07:34:40.41#ibcon#end of sib2, iclass 11, count 0 2006.189.07:34:40.41#ibcon#*after write, iclass 11, count 0 2006.189.07:34:40.41#ibcon#*before return 0, iclass 11, count 0 2006.189.07:34:40.41#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:34:40.41#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:34:40.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:34:40.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:34:40.41$vc4f8/valo=8,852.99 2006.189.07:34:40.41#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.07:34:40.41#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.07:34:40.41#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:40.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:34:40.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:34:40.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:34:40.41#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:34:40.41#ibcon#first serial, iclass 14, count 0 2006.189.07:34:40.41#ibcon#enter sib2, iclass 14, count 0 2006.189.07:34:40.41#ibcon#flushed, iclass 14, count 0 2006.189.07:34:40.41#ibcon#about to write, iclass 14, count 0 2006.189.07:34:40.41#ibcon#wrote, iclass 14, count 0 2006.189.07:34:40.41#ibcon#about to read 3, iclass 14, count 0 2006.189.07:34:40.42#abcon#<5=/04 4.3 7.3 26.47 871008.9\r\n> 2006.189.07:34:40.43#ibcon#read 3, iclass 14, count 0 2006.189.07:34:40.43#ibcon#about to read 4, iclass 14, count 0 2006.189.07:34:40.43#ibcon#read 4, iclass 14, count 0 2006.189.07:34:40.43#ibcon#about to read 5, iclass 14, count 0 2006.189.07:34:40.43#ibcon#read 5, iclass 14, count 0 2006.189.07:34:40.43#ibcon#about to read 6, iclass 14, count 0 2006.189.07:34:40.43#ibcon#read 6, iclass 14, count 0 2006.189.07:34:40.43#ibcon#end of sib2, iclass 14, count 0 2006.189.07:34:40.43#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:34:40.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:34:40.43#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:34:40.43#ibcon#*before write, iclass 14, count 0 2006.189.07:34:40.43#ibcon#enter sib2, iclass 14, count 0 2006.189.07:34:40.43#ibcon#flushed, iclass 14, count 0 2006.189.07:34:40.43#ibcon#about to write, iclass 14, count 0 2006.189.07:34:40.43#ibcon#wrote, iclass 14, count 0 2006.189.07:34:40.43#ibcon#about to read 3, iclass 14, count 0 2006.189.07:34:40.44#abcon#{5=INTERFACE CLEAR} 2006.189.07:34:40.47#ibcon#read 3, iclass 14, count 0 2006.189.07:34:40.47#ibcon#about to read 4, iclass 14, count 0 2006.189.07:34:40.47#ibcon#read 4, iclass 14, count 0 2006.189.07:34:40.47#ibcon#about to read 5, iclass 14, count 0 2006.189.07:34:40.47#ibcon#read 5, iclass 14, count 0 2006.189.07:34:40.47#ibcon#about to read 6, iclass 14, count 0 2006.189.07:34:40.47#ibcon#read 6, iclass 14, count 0 2006.189.07:34:40.47#ibcon#end of sib2, iclass 14, count 0 2006.189.07:34:40.47#ibcon#*after write, iclass 14, count 0 2006.189.07:34:40.47#ibcon#*before return 0, iclass 14, count 0 2006.189.07:34:40.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:34:40.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:34:40.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:34:40.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:34:40.47$vc4f8/va=8,6 2006.189.07:34:40.47#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.07:34:40.47#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.07:34:40.47#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:40.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:34:40.50#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:34:40.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:34:40.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:34:40.54#ibcon#enter wrdev, iclass 18, count 2 2006.189.07:34:40.54#ibcon#first serial, iclass 18, count 2 2006.189.07:34:40.54#ibcon#enter sib2, iclass 18, count 2 2006.189.07:34:40.54#ibcon#flushed, iclass 18, count 2 2006.189.07:34:40.54#ibcon#about to write, iclass 18, count 2 2006.189.07:34:40.54#ibcon#wrote, iclass 18, count 2 2006.189.07:34:40.54#ibcon#about to read 3, iclass 18, count 2 2006.189.07:34:40.55#ibcon#read 3, iclass 18, count 2 2006.189.07:34:40.55#ibcon#about to read 4, iclass 18, count 2 2006.189.07:34:40.55#ibcon#read 4, iclass 18, count 2 2006.189.07:34:40.55#ibcon#about to read 5, iclass 18, count 2 2006.189.07:34:40.55#ibcon#read 5, iclass 18, count 2 2006.189.07:34:40.55#ibcon#about to read 6, iclass 18, count 2 2006.189.07:34:40.55#ibcon#read 6, iclass 18, count 2 2006.189.07:34:40.55#ibcon#end of sib2, iclass 18, count 2 2006.189.07:34:40.55#ibcon#*mode == 0, iclass 18, count 2 2006.189.07:34:40.55#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.07:34:40.55#ibcon#[25=AT08-06\r\n] 2006.189.07:34:40.55#ibcon#*before write, iclass 18, count 2 2006.189.07:34:40.55#ibcon#enter sib2, iclass 18, count 2 2006.189.07:34:40.55#ibcon#flushed, iclass 18, count 2 2006.189.07:34:40.55#ibcon#about to write, iclass 18, count 2 2006.189.07:34:40.56#ibcon#wrote, iclass 18, count 2 2006.189.07:34:40.56#ibcon#about to read 3, iclass 18, count 2 2006.189.07:34:40.58#ibcon#read 3, iclass 18, count 2 2006.189.07:34:40.58#ibcon#about to read 4, iclass 18, count 2 2006.189.07:34:40.58#ibcon#read 4, iclass 18, count 2 2006.189.07:34:40.58#ibcon#about to read 5, iclass 18, count 2 2006.189.07:34:40.58#ibcon#read 5, iclass 18, count 2 2006.189.07:34:40.58#ibcon#about to read 6, iclass 18, count 2 2006.189.07:34:40.58#ibcon#read 6, iclass 18, count 2 2006.189.07:34:40.58#ibcon#end of sib2, iclass 18, count 2 2006.189.07:34:40.58#ibcon#*after write, iclass 18, count 2 2006.189.07:34:40.58#ibcon#*before return 0, iclass 18, count 2 2006.189.07:34:40.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:34:40.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:34:40.58#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.07:34:40.58#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:40.58#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:34:40.70#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:34:40.70#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:34:40.70#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:34:40.70#ibcon#first serial, iclass 18, count 0 2006.189.07:34:40.70#ibcon#enter sib2, iclass 18, count 0 2006.189.07:34:40.70#ibcon#flushed, iclass 18, count 0 2006.189.07:34:40.70#ibcon#about to write, iclass 18, count 0 2006.189.07:34:40.70#ibcon#wrote, iclass 18, count 0 2006.189.07:34:40.70#ibcon#about to read 3, iclass 18, count 0 2006.189.07:34:40.72#ibcon#read 3, iclass 18, count 0 2006.189.07:34:40.72#ibcon#about to read 4, iclass 18, count 0 2006.189.07:34:40.72#ibcon#read 4, iclass 18, count 0 2006.189.07:34:40.72#ibcon#about to read 5, iclass 18, count 0 2006.189.07:34:40.72#ibcon#read 5, iclass 18, count 0 2006.189.07:34:40.72#ibcon#about to read 6, iclass 18, count 0 2006.189.07:34:40.72#ibcon#read 6, iclass 18, count 0 2006.189.07:34:40.72#ibcon#end of sib2, iclass 18, count 0 2006.189.07:34:40.72#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:34:40.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:34:40.72#ibcon#[25=USB\r\n] 2006.189.07:34:40.72#ibcon#*before write, iclass 18, count 0 2006.189.07:34:40.72#ibcon#enter sib2, iclass 18, count 0 2006.189.07:34:40.72#ibcon#flushed, iclass 18, count 0 2006.189.07:34:40.72#ibcon#about to write, iclass 18, count 0 2006.189.07:34:40.72#ibcon#wrote, iclass 18, count 0 2006.189.07:34:40.72#ibcon#about to read 3, iclass 18, count 0 2006.189.07:34:40.75#ibcon#read 3, iclass 18, count 0 2006.189.07:34:40.75#ibcon#about to read 4, iclass 18, count 0 2006.189.07:34:40.75#ibcon#read 4, iclass 18, count 0 2006.189.07:34:40.75#ibcon#about to read 5, iclass 18, count 0 2006.189.07:34:40.75#ibcon#read 5, iclass 18, count 0 2006.189.07:34:40.75#ibcon#about to read 6, iclass 18, count 0 2006.189.07:34:40.75#ibcon#read 6, iclass 18, count 0 2006.189.07:34:40.75#ibcon#end of sib2, iclass 18, count 0 2006.189.07:34:40.75#ibcon#*after write, iclass 18, count 0 2006.189.07:34:40.75#ibcon#*before return 0, iclass 18, count 0 2006.189.07:34:40.75#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:34:40.75#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:34:40.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:34:40.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:34:40.75$vc4f8/vblo=1,632.99 2006.189.07:34:40.75#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:34:40.75#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:34:40.75#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:40.75#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:40.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:40.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:40.75#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:34:40.75#ibcon#first serial, iclass 21, count 0 2006.189.07:34:40.75#ibcon#enter sib2, iclass 21, count 0 2006.189.07:34:40.75#ibcon#flushed, iclass 21, count 0 2006.189.07:34:40.75#ibcon#about to write, iclass 21, count 0 2006.189.07:34:40.75#ibcon#wrote, iclass 21, count 0 2006.189.07:34:40.75#ibcon#about to read 3, iclass 21, count 0 2006.189.07:34:40.77#ibcon#read 3, iclass 21, count 0 2006.189.07:34:40.77#ibcon#about to read 4, iclass 21, count 0 2006.189.07:34:40.77#ibcon#read 4, iclass 21, count 0 2006.189.07:34:40.77#ibcon#about to read 5, iclass 21, count 0 2006.189.07:34:40.77#ibcon#read 5, iclass 21, count 0 2006.189.07:34:40.77#ibcon#about to read 6, iclass 21, count 0 2006.189.07:34:40.77#ibcon#read 6, iclass 21, count 0 2006.189.07:34:40.77#ibcon#end of sib2, iclass 21, count 0 2006.189.07:34:40.77#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:34:40.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:34:40.77#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:34:40.77#ibcon#*before write, iclass 21, count 0 2006.189.07:34:40.77#ibcon#enter sib2, iclass 21, count 0 2006.189.07:34:40.77#ibcon#flushed, iclass 21, count 0 2006.189.07:34:40.77#ibcon#about to write, iclass 21, count 0 2006.189.07:34:40.77#ibcon#wrote, iclass 21, count 0 2006.189.07:34:40.77#ibcon#about to read 3, iclass 21, count 0 2006.189.07:34:40.81#ibcon#read 3, iclass 21, count 0 2006.189.07:34:40.81#ibcon#about to read 4, iclass 21, count 0 2006.189.07:34:40.81#ibcon#read 4, iclass 21, count 0 2006.189.07:34:40.81#ibcon#about to read 5, iclass 21, count 0 2006.189.07:34:40.81#ibcon#read 5, iclass 21, count 0 2006.189.07:34:40.81#ibcon#about to read 6, iclass 21, count 0 2006.189.07:34:40.81#ibcon#read 6, iclass 21, count 0 2006.189.07:34:40.81#ibcon#end of sib2, iclass 21, count 0 2006.189.07:34:40.81#ibcon#*after write, iclass 21, count 0 2006.189.07:34:40.81#ibcon#*before return 0, iclass 21, count 0 2006.189.07:34:40.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:40.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:34:40.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:34:40.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:34:40.81$vc4f8/vb=1,4 2006.189.07:34:40.81#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:34:40.81#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:34:40.81#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:40.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:40.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:40.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:40.81#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:34:40.81#ibcon#first serial, iclass 23, count 2 2006.189.07:34:40.81#ibcon#enter sib2, iclass 23, count 2 2006.189.07:34:40.81#ibcon#flushed, iclass 23, count 2 2006.189.07:34:40.81#ibcon#about to write, iclass 23, count 2 2006.189.07:34:40.81#ibcon#wrote, iclass 23, count 2 2006.189.07:34:40.81#ibcon#about to read 3, iclass 23, count 2 2006.189.07:34:40.83#ibcon#read 3, iclass 23, count 2 2006.189.07:34:40.83#ibcon#about to read 4, iclass 23, count 2 2006.189.07:34:40.83#ibcon#read 4, iclass 23, count 2 2006.189.07:34:40.83#ibcon#about to read 5, iclass 23, count 2 2006.189.07:34:40.83#ibcon#read 5, iclass 23, count 2 2006.189.07:34:40.83#ibcon#about to read 6, iclass 23, count 2 2006.189.07:34:40.83#ibcon#read 6, iclass 23, count 2 2006.189.07:34:40.83#ibcon#end of sib2, iclass 23, count 2 2006.189.07:34:40.83#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:34:40.83#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:34:40.83#ibcon#[27=AT01-04\r\n] 2006.189.07:34:40.83#ibcon#*before write, iclass 23, count 2 2006.189.07:34:40.83#ibcon#enter sib2, iclass 23, count 2 2006.189.07:34:40.83#ibcon#flushed, iclass 23, count 2 2006.189.07:34:40.83#ibcon#about to write, iclass 23, count 2 2006.189.07:34:40.83#ibcon#wrote, iclass 23, count 2 2006.189.07:34:40.83#ibcon#about to read 3, iclass 23, count 2 2006.189.07:34:40.86#ibcon#read 3, iclass 23, count 2 2006.189.07:34:40.86#ibcon#about to read 4, iclass 23, count 2 2006.189.07:34:40.86#ibcon#read 4, iclass 23, count 2 2006.189.07:34:40.86#ibcon#about to read 5, iclass 23, count 2 2006.189.07:34:40.86#ibcon#read 5, iclass 23, count 2 2006.189.07:34:40.86#ibcon#about to read 6, iclass 23, count 2 2006.189.07:34:40.86#ibcon#read 6, iclass 23, count 2 2006.189.07:34:40.86#ibcon#end of sib2, iclass 23, count 2 2006.189.07:34:40.86#ibcon#*after write, iclass 23, count 2 2006.189.07:34:40.86#ibcon#*before return 0, iclass 23, count 2 2006.189.07:34:40.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:40.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:34:40.86#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:34:40.86#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:40.86#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:40.98#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:40.98#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:40.98#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:34:40.98#ibcon#first serial, iclass 23, count 0 2006.189.07:34:40.98#ibcon#enter sib2, iclass 23, count 0 2006.189.07:34:40.98#ibcon#flushed, iclass 23, count 0 2006.189.07:34:40.98#ibcon#about to write, iclass 23, count 0 2006.189.07:34:40.98#ibcon#wrote, iclass 23, count 0 2006.189.07:34:40.98#ibcon#about to read 3, iclass 23, count 0 2006.189.07:34:41.00#ibcon#read 3, iclass 23, count 0 2006.189.07:34:41.00#ibcon#about to read 4, iclass 23, count 0 2006.189.07:34:41.00#ibcon#read 4, iclass 23, count 0 2006.189.07:34:41.00#ibcon#about to read 5, iclass 23, count 0 2006.189.07:34:41.00#ibcon#read 5, iclass 23, count 0 2006.189.07:34:41.00#ibcon#about to read 6, iclass 23, count 0 2006.189.07:34:41.00#ibcon#read 6, iclass 23, count 0 2006.189.07:34:41.00#ibcon#end of sib2, iclass 23, count 0 2006.189.07:34:41.00#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:34:41.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:34:41.00#ibcon#[27=USB\r\n] 2006.189.07:34:41.00#ibcon#*before write, iclass 23, count 0 2006.189.07:34:41.00#ibcon#enter sib2, iclass 23, count 0 2006.189.07:34:41.00#ibcon#flushed, iclass 23, count 0 2006.189.07:34:41.00#ibcon#about to write, iclass 23, count 0 2006.189.07:34:41.00#ibcon#wrote, iclass 23, count 0 2006.189.07:34:41.00#ibcon#about to read 3, iclass 23, count 0 2006.189.07:34:41.03#ibcon#read 3, iclass 23, count 0 2006.189.07:34:41.03#ibcon#about to read 4, iclass 23, count 0 2006.189.07:34:41.03#ibcon#read 4, iclass 23, count 0 2006.189.07:34:41.03#ibcon#about to read 5, iclass 23, count 0 2006.189.07:34:41.03#ibcon#read 5, iclass 23, count 0 2006.189.07:34:41.03#ibcon#about to read 6, iclass 23, count 0 2006.189.07:34:41.03#ibcon#read 6, iclass 23, count 0 2006.189.07:34:41.03#ibcon#end of sib2, iclass 23, count 0 2006.189.07:34:41.03#ibcon#*after write, iclass 23, count 0 2006.189.07:34:41.03#ibcon#*before return 0, iclass 23, count 0 2006.189.07:34:41.03#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:41.03#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:34:41.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:34:41.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:34:41.03$vc4f8/vblo=2,640.99 2006.189.07:34:41.03#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:34:41.03#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:34:41.03#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:41.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:41.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:41.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:41.03#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:34:41.03#ibcon#first serial, iclass 25, count 0 2006.189.07:34:41.03#ibcon#enter sib2, iclass 25, count 0 2006.189.07:34:41.03#ibcon#flushed, iclass 25, count 0 2006.189.07:34:41.03#ibcon#about to write, iclass 25, count 0 2006.189.07:34:41.03#ibcon#wrote, iclass 25, count 0 2006.189.07:34:41.03#ibcon#about to read 3, iclass 25, count 0 2006.189.07:34:41.05#ibcon#read 3, iclass 25, count 0 2006.189.07:34:41.05#ibcon#about to read 4, iclass 25, count 0 2006.189.07:34:41.05#ibcon#read 4, iclass 25, count 0 2006.189.07:34:41.05#ibcon#about to read 5, iclass 25, count 0 2006.189.07:34:41.05#ibcon#read 5, iclass 25, count 0 2006.189.07:34:41.05#ibcon#about to read 6, iclass 25, count 0 2006.189.07:34:41.05#ibcon#read 6, iclass 25, count 0 2006.189.07:34:41.05#ibcon#end of sib2, iclass 25, count 0 2006.189.07:34:41.05#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:34:41.05#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:34:41.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:34:41.05#ibcon#*before write, iclass 25, count 0 2006.189.07:34:41.05#ibcon#enter sib2, iclass 25, count 0 2006.189.07:34:41.05#ibcon#flushed, iclass 25, count 0 2006.189.07:34:41.05#ibcon#about to write, iclass 25, count 0 2006.189.07:34:41.05#ibcon#wrote, iclass 25, count 0 2006.189.07:34:41.05#ibcon#about to read 3, iclass 25, count 0 2006.189.07:34:41.09#ibcon#read 3, iclass 25, count 0 2006.189.07:34:41.09#ibcon#about to read 4, iclass 25, count 0 2006.189.07:34:41.09#ibcon#read 4, iclass 25, count 0 2006.189.07:34:41.09#ibcon#about to read 5, iclass 25, count 0 2006.189.07:34:41.09#ibcon#read 5, iclass 25, count 0 2006.189.07:34:41.09#ibcon#about to read 6, iclass 25, count 0 2006.189.07:34:41.09#ibcon#read 6, iclass 25, count 0 2006.189.07:34:41.09#ibcon#end of sib2, iclass 25, count 0 2006.189.07:34:41.09#ibcon#*after write, iclass 25, count 0 2006.189.07:34:41.09#ibcon#*before return 0, iclass 25, count 0 2006.189.07:34:41.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:41.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:34:41.09#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:34:41.09#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:34:41.09$vc4f8/vb=2,4 2006.189.07:34:41.09#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:34:41.09#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:34:41.09#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:41.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:41.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:41.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:41.15#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:34:41.15#ibcon#first serial, iclass 27, count 2 2006.189.07:34:41.15#ibcon#enter sib2, iclass 27, count 2 2006.189.07:34:41.15#ibcon#flushed, iclass 27, count 2 2006.189.07:34:41.15#ibcon#about to write, iclass 27, count 2 2006.189.07:34:41.15#ibcon#wrote, iclass 27, count 2 2006.189.07:34:41.15#ibcon#about to read 3, iclass 27, count 2 2006.189.07:34:41.17#ibcon#read 3, iclass 27, count 2 2006.189.07:34:41.17#ibcon#about to read 4, iclass 27, count 2 2006.189.07:34:41.17#ibcon#read 4, iclass 27, count 2 2006.189.07:34:41.17#ibcon#about to read 5, iclass 27, count 2 2006.189.07:34:41.17#ibcon#read 5, iclass 27, count 2 2006.189.07:34:41.17#ibcon#about to read 6, iclass 27, count 2 2006.189.07:34:41.17#ibcon#read 6, iclass 27, count 2 2006.189.07:34:41.17#ibcon#end of sib2, iclass 27, count 2 2006.189.07:34:41.17#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:34:41.17#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:34:41.17#ibcon#[27=AT02-04\r\n] 2006.189.07:34:41.17#ibcon#*before write, iclass 27, count 2 2006.189.07:34:41.17#ibcon#enter sib2, iclass 27, count 2 2006.189.07:34:41.17#ibcon#flushed, iclass 27, count 2 2006.189.07:34:41.17#ibcon#about to write, iclass 27, count 2 2006.189.07:34:41.17#ibcon#wrote, iclass 27, count 2 2006.189.07:34:41.17#ibcon#about to read 3, iclass 27, count 2 2006.189.07:34:41.20#ibcon#read 3, iclass 27, count 2 2006.189.07:34:41.20#ibcon#about to read 4, iclass 27, count 2 2006.189.07:34:41.20#ibcon#read 4, iclass 27, count 2 2006.189.07:34:41.20#ibcon#about to read 5, iclass 27, count 2 2006.189.07:34:41.20#ibcon#read 5, iclass 27, count 2 2006.189.07:34:41.20#ibcon#about to read 6, iclass 27, count 2 2006.189.07:34:41.20#ibcon#read 6, iclass 27, count 2 2006.189.07:34:41.20#ibcon#end of sib2, iclass 27, count 2 2006.189.07:34:41.20#ibcon#*after write, iclass 27, count 2 2006.189.07:34:41.20#ibcon#*before return 0, iclass 27, count 2 2006.189.07:34:41.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:41.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:34:41.20#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:34:41.21#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:41.21#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:41.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:41.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:41.31#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:34:41.31#ibcon#first serial, iclass 27, count 0 2006.189.07:34:41.31#ibcon#enter sib2, iclass 27, count 0 2006.189.07:34:41.31#ibcon#flushed, iclass 27, count 0 2006.189.07:34:41.31#ibcon#about to write, iclass 27, count 0 2006.189.07:34:41.31#ibcon#wrote, iclass 27, count 0 2006.189.07:34:41.31#ibcon#about to read 3, iclass 27, count 0 2006.189.07:34:41.33#ibcon#read 3, iclass 27, count 0 2006.189.07:34:41.33#ibcon#about to read 4, iclass 27, count 0 2006.189.07:34:41.33#ibcon#read 4, iclass 27, count 0 2006.189.07:34:41.33#ibcon#about to read 5, iclass 27, count 0 2006.189.07:34:41.33#ibcon#read 5, iclass 27, count 0 2006.189.07:34:41.33#ibcon#about to read 6, iclass 27, count 0 2006.189.07:34:41.33#ibcon#read 6, iclass 27, count 0 2006.189.07:34:41.33#ibcon#end of sib2, iclass 27, count 0 2006.189.07:34:41.33#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:34:41.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:34:41.33#ibcon#[27=USB\r\n] 2006.189.07:34:41.33#ibcon#*before write, iclass 27, count 0 2006.189.07:34:41.33#ibcon#enter sib2, iclass 27, count 0 2006.189.07:34:41.33#ibcon#flushed, iclass 27, count 0 2006.189.07:34:41.33#ibcon#about to write, iclass 27, count 0 2006.189.07:34:41.33#ibcon#wrote, iclass 27, count 0 2006.189.07:34:41.33#ibcon#about to read 3, iclass 27, count 0 2006.189.07:34:41.36#ibcon#read 3, iclass 27, count 0 2006.189.07:34:41.36#ibcon#about to read 4, iclass 27, count 0 2006.189.07:34:41.36#ibcon#read 4, iclass 27, count 0 2006.189.07:34:41.36#ibcon#about to read 5, iclass 27, count 0 2006.189.07:34:41.36#ibcon#read 5, iclass 27, count 0 2006.189.07:34:41.36#ibcon#about to read 6, iclass 27, count 0 2006.189.07:34:41.36#ibcon#read 6, iclass 27, count 0 2006.189.07:34:41.36#ibcon#end of sib2, iclass 27, count 0 2006.189.07:34:41.36#ibcon#*after write, iclass 27, count 0 2006.189.07:34:41.36#ibcon#*before return 0, iclass 27, count 0 2006.189.07:34:41.36#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:41.36#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:34:41.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:34:41.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:34:41.36$vc4f8/vblo=3,656.99 2006.189.07:34:41.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:34:41.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:34:41.36#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:41.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:41.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:41.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:41.36#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:34:41.36#ibcon#first serial, iclass 29, count 0 2006.189.07:34:41.36#ibcon#enter sib2, iclass 29, count 0 2006.189.07:34:41.36#ibcon#flushed, iclass 29, count 0 2006.189.07:34:41.36#ibcon#about to write, iclass 29, count 0 2006.189.07:34:41.36#ibcon#wrote, iclass 29, count 0 2006.189.07:34:41.36#ibcon#about to read 3, iclass 29, count 0 2006.189.07:34:41.38#ibcon#read 3, iclass 29, count 0 2006.189.07:34:41.38#ibcon#about to read 4, iclass 29, count 0 2006.189.07:34:41.38#ibcon#read 4, iclass 29, count 0 2006.189.07:34:41.38#ibcon#about to read 5, iclass 29, count 0 2006.189.07:34:41.38#ibcon#read 5, iclass 29, count 0 2006.189.07:34:41.38#ibcon#about to read 6, iclass 29, count 0 2006.189.07:34:41.38#ibcon#read 6, iclass 29, count 0 2006.189.07:34:41.38#ibcon#end of sib2, iclass 29, count 0 2006.189.07:34:41.38#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:34:41.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:34:41.38#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:34:41.38#ibcon#*before write, iclass 29, count 0 2006.189.07:34:41.38#ibcon#enter sib2, iclass 29, count 0 2006.189.07:34:41.38#ibcon#flushed, iclass 29, count 0 2006.189.07:34:41.38#ibcon#about to write, iclass 29, count 0 2006.189.07:34:41.38#ibcon#wrote, iclass 29, count 0 2006.189.07:34:41.38#ibcon#about to read 3, iclass 29, count 0 2006.189.07:34:41.42#ibcon#read 3, iclass 29, count 0 2006.189.07:34:41.42#ibcon#about to read 4, iclass 29, count 0 2006.189.07:34:41.42#ibcon#read 4, iclass 29, count 0 2006.189.07:34:41.42#ibcon#about to read 5, iclass 29, count 0 2006.189.07:34:41.42#ibcon#read 5, iclass 29, count 0 2006.189.07:34:41.42#ibcon#about to read 6, iclass 29, count 0 2006.189.07:34:41.42#ibcon#read 6, iclass 29, count 0 2006.189.07:34:41.42#ibcon#end of sib2, iclass 29, count 0 2006.189.07:34:41.42#ibcon#*after write, iclass 29, count 0 2006.189.07:34:41.42#ibcon#*before return 0, iclass 29, count 0 2006.189.07:34:41.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:41.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:34:41.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:34:41.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:34:41.42$vc4f8/vb=3,4 2006.189.07:34:41.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.07:34:41.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.07:34:41.42#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:41.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:41.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:41.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:41.48#ibcon#enter wrdev, iclass 31, count 2 2006.189.07:34:41.48#ibcon#first serial, iclass 31, count 2 2006.189.07:34:41.48#ibcon#enter sib2, iclass 31, count 2 2006.189.07:34:41.48#ibcon#flushed, iclass 31, count 2 2006.189.07:34:41.48#ibcon#about to write, iclass 31, count 2 2006.189.07:34:41.48#ibcon#wrote, iclass 31, count 2 2006.189.07:34:41.48#ibcon#about to read 3, iclass 31, count 2 2006.189.07:34:41.50#ibcon#read 3, iclass 31, count 2 2006.189.07:34:41.50#ibcon#about to read 4, iclass 31, count 2 2006.189.07:34:41.50#ibcon#read 4, iclass 31, count 2 2006.189.07:34:41.50#ibcon#about to read 5, iclass 31, count 2 2006.189.07:34:41.50#ibcon#read 5, iclass 31, count 2 2006.189.07:34:41.50#ibcon#about to read 6, iclass 31, count 2 2006.189.07:34:41.50#ibcon#read 6, iclass 31, count 2 2006.189.07:34:41.50#ibcon#end of sib2, iclass 31, count 2 2006.189.07:34:41.50#ibcon#*mode == 0, iclass 31, count 2 2006.189.07:34:41.50#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.07:34:41.50#ibcon#[27=AT03-04\r\n] 2006.189.07:34:41.50#ibcon#*before write, iclass 31, count 2 2006.189.07:34:41.50#ibcon#enter sib2, iclass 31, count 2 2006.189.07:34:41.50#ibcon#flushed, iclass 31, count 2 2006.189.07:34:41.50#ibcon#about to write, iclass 31, count 2 2006.189.07:34:41.50#ibcon#wrote, iclass 31, count 2 2006.189.07:34:41.50#ibcon#about to read 3, iclass 31, count 2 2006.189.07:34:41.53#ibcon#read 3, iclass 31, count 2 2006.189.07:34:41.53#ibcon#about to read 4, iclass 31, count 2 2006.189.07:34:41.53#ibcon#read 4, iclass 31, count 2 2006.189.07:34:41.53#ibcon#about to read 5, iclass 31, count 2 2006.189.07:34:41.53#ibcon#read 5, iclass 31, count 2 2006.189.07:34:41.53#ibcon#about to read 6, iclass 31, count 2 2006.189.07:34:41.53#ibcon#read 6, iclass 31, count 2 2006.189.07:34:41.53#ibcon#end of sib2, iclass 31, count 2 2006.189.07:34:41.53#ibcon#*after write, iclass 31, count 2 2006.189.07:34:41.53#ibcon#*before return 0, iclass 31, count 2 2006.189.07:34:41.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:41.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:34:41.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.07:34:41.53#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:41.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:41.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:41.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:41.65#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:34:41.65#ibcon#first serial, iclass 31, count 0 2006.189.07:34:41.65#ibcon#enter sib2, iclass 31, count 0 2006.189.07:34:41.65#ibcon#flushed, iclass 31, count 0 2006.189.07:34:41.65#ibcon#about to write, iclass 31, count 0 2006.189.07:34:41.65#ibcon#wrote, iclass 31, count 0 2006.189.07:34:41.65#ibcon#about to read 3, iclass 31, count 0 2006.189.07:34:41.67#ibcon#read 3, iclass 31, count 0 2006.189.07:34:41.67#ibcon#about to read 4, iclass 31, count 0 2006.189.07:34:41.67#ibcon#read 4, iclass 31, count 0 2006.189.07:34:41.67#ibcon#about to read 5, iclass 31, count 0 2006.189.07:34:41.67#ibcon#read 5, iclass 31, count 0 2006.189.07:34:41.67#ibcon#about to read 6, iclass 31, count 0 2006.189.07:34:41.67#ibcon#read 6, iclass 31, count 0 2006.189.07:34:41.67#ibcon#end of sib2, iclass 31, count 0 2006.189.07:34:41.67#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:34:41.67#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:34:41.67#ibcon#[27=USB\r\n] 2006.189.07:34:41.67#ibcon#*before write, iclass 31, count 0 2006.189.07:34:41.67#ibcon#enter sib2, iclass 31, count 0 2006.189.07:34:41.67#ibcon#flushed, iclass 31, count 0 2006.189.07:34:41.67#ibcon#about to write, iclass 31, count 0 2006.189.07:34:41.67#ibcon#wrote, iclass 31, count 0 2006.189.07:34:41.67#ibcon#about to read 3, iclass 31, count 0 2006.189.07:34:41.70#ibcon#read 3, iclass 31, count 0 2006.189.07:34:41.70#ibcon#about to read 4, iclass 31, count 0 2006.189.07:34:41.70#ibcon#read 4, iclass 31, count 0 2006.189.07:34:41.70#ibcon#about to read 5, iclass 31, count 0 2006.189.07:34:41.70#ibcon#read 5, iclass 31, count 0 2006.189.07:34:41.70#ibcon#about to read 6, iclass 31, count 0 2006.189.07:34:41.70#ibcon#read 6, iclass 31, count 0 2006.189.07:34:41.70#ibcon#end of sib2, iclass 31, count 0 2006.189.07:34:41.70#ibcon#*after write, iclass 31, count 0 2006.189.07:34:41.70#ibcon#*before return 0, iclass 31, count 0 2006.189.07:34:41.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:41.70#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:34:41.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:34:41.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:34:41.70$vc4f8/vblo=4,712.99 2006.189.07:34:41.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:34:41.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:34:41.70#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:41.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:41.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:41.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:41.70#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:34:41.70#ibcon#first serial, iclass 33, count 0 2006.189.07:34:41.70#ibcon#enter sib2, iclass 33, count 0 2006.189.07:34:41.70#ibcon#flushed, iclass 33, count 0 2006.189.07:34:41.70#ibcon#about to write, iclass 33, count 0 2006.189.07:34:41.70#ibcon#wrote, iclass 33, count 0 2006.189.07:34:41.70#ibcon#about to read 3, iclass 33, count 0 2006.189.07:34:41.72#ibcon#read 3, iclass 33, count 0 2006.189.07:34:41.72#ibcon#about to read 4, iclass 33, count 0 2006.189.07:34:41.72#ibcon#read 4, iclass 33, count 0 2006.189.07:34:41.72#ibcon#about to read 5, iclass 33, count 0 2006.189.07:34:41.72#ibcon#read 5, iclass 33, count 0 2006.189.07:34:41.72#ibcon#about to read 6, iclass 33, count 0 2006.189.07:34:41.72#ibcon#read 6, iclass 33, count 0 2006.189.07:34:41.72#ibcon#end of sib2, iclass 33, count 0 2006.189.07:34:41.72#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:34:41.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:34:41.72#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:34:41.72#ibcon#*before write, iclass 33, count 0 2006.189.07:34:41.72#ibcon#enter sib2, iclass 33, count 0 2006.189.07:34:41.72#ibcon#flushed, iclass 33, count 0 2006.189.07:34:41.72#ibcon#about to write, iclass 33, count 0 2006.189.07:34:41.72#ibcon#wrote, iclass 33, count 0 2006.189.07:34:41.72#ibcon#about to read 3, iclass 33, count 0 2006.189.07:34:41.76#ibcon#read 3, iclass 33, count 0 2006.189.07:34:41.76#ibcon#about to read 4, iclass 33, count 0 2006.189.07:34:41.76#ibcon#read 4, iclass 33, count 0 2006.189.07:34:41.76#ibcon#about to read 5, iclass 33, count 0 2006.189.07:34:41.76#ibcon#read 5, iclass 33, count 0 2006.189.07:34:41.76#ibcon#about to read 6, iclass 33, count 0 2006.189.07:34:41.76#ibcon#read 6, iclass 33, count 0 2006.189.07:34:41.76#ibcon#end of sib2, iclass 33, count 0 2006.189.07:34:41.76#ibcon#*after write, iclass 33, count 0 2006.189.07:34:41.76#ibcon#*before return 0, iclass 33, count 0 2006.189.07:34:41.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:41.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:34:41.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:34:41.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:34:41.76$vc4f8/vb=4,4 2006.189.07:34:41.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:34:41.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:34:41.76#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:41.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:41.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:41.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:41.82#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:34:41.82#ibcon#first serial, iclass 35, count 2 2006.189.07:34:41.82#ibcon#enter sib2, iclass 35, count 2 2006.189.07:34:41.82#ibcon#flushed, iclass 35, count 2 2006.189.07:34:41.82#ibcon#about to write, iclass 35, count 2 2006.189.07:34:41.82#ibcon#wrote, iclass 35, count 2 2006.189.07:34:41.82#ibcon#about to read 3, iclass 35, count 2 2006.189.07:34:41.84#ibcon#read 3, iclass 35, count 2 2006.189.07:34:41.84#ibcon#about to read 4, iclass 35, count 2 2006.189.07:34:41.84#ibcon#read 4, iclass 35, count 2 2006.189.07:34:41.84#ibcon#about to read 5, iclass 35, count 2 2006.189.07:34:41.84#ibcon#read 5, iclass 35, count 2 2006.189.07:34:41.84#ibcon#about to read 6, iclass 35, count 2 2006.189.07:34:41.84#ibcon#read 6, iclass 35, count 2 2006.189.07:34:41.84#ibcon#end of sib2, iclass 35, count 2 2006.189.07:34:41.84#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:34:41.84#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:34:41.84#ibcon#[27=AT04-04\r\n] 2006.189.07:34:41.84#ibcon#*before write, iclass 35, count 2 2006.189.07:34:41.84#ibcon#enter sib2, iclass 35, count 2 2006.189.07:34:41.84#ibcon#flushed, iclass 35, count 2 2006.189.07:34:41.84#ibcon#about to write, iclass 35, count 2 2006.189.07:34:41.84#ibcon#wrote, iclass 35, count 2 2006.189.07:34:41.84#ibcon#about to read 3, iclass 35, count 2 2006.189.07:34:41.87#ibcon#read 3, iclass 35, count 2 2006.189.07:34:41.87#ibcon#about to read 4, iclass 35, count 2 2006.189.07:34:41.87#ibcon#read 4, iclass 35, count 2 2006.189.07:34:41.87#ibcon#about to read 5, iclass 35, count 2 2006.189.07:34:41.87#ibcon#read 5, iclass 35, count 2 2006.189.07:34:41.87#ibcon#about to read 6, iclass 35, count 2 2006.189.07:34:41.87#ibcon#read 6, iclass 35, count 2 2006.189.07:34:41.87#ibcon#end of sib2, iclass 35, count 2 2006.189.07:34:41.87#ibcon#*after write, iclass 35, count 2 2006.189.07:34:41.87#ibcon#*before return 0, iclass 35, count 2 2006.189.07:34:41.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:41.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:34:41.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:34:41.87#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:41.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:41.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:41.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:41.99#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:34:41.99#ibcon#first serial, iclass 35, count 0 2006.189.07:34:41.99#ibcon#enter sib2, iclass 35, count 0 2006.189.07:34:41.99#ibcon#flushed, iclass 35, count 0 2006.189.07:34:41.99#ibcon#about to write, iclass 35, count 0 2006.189.07:34:41.99#ibcon#wrote, iclass 35, count 0 2006.189.07:34:41.99#ibcon#about to read 3, iclass 35, count 0 2006.189.07:34:42.01#ibcon#read 3, iclass 35, count 0 2006.189.07:34:42.01#ibcon#about to read 4, iclass 35, count 0 2006.189.07:34:42.01#ibcon#read 4, iclass 35, count 0 2006.189.07:34:42.01#ibcon#about to read 5, iclass 35, count 0 2006.189.07:34:42.01#ibcon#read 5, iclass 35, count 0 2006.189.07:34:42.01#ibcon#about to read 6, iclass 35, count 0 2006.189.07:34:42.01#ibcon#read 6, iclass 35, count 0 2006.189.07:34:42.01#ibcon#end of sib2, iclass 35, count 0 2006.189.07:34:42.01#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:34:42.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:34:42.01#ibcon#[27=USB\r\n] 2006.189.07:34:42.01#ibcon#*before write, iclass 35, count 0 2006.189.07:34:42.01#ibcon#enter sib2, iclass 35, count 0 2006.189.07:34:42.01#ibcon#flushed, iclass 35, count 0 2006.189.07:34:42.01#ibcon#about to write, iclass 35, count 0 2006.189.07:34:42.01#ibcon#wrote, iclass 35, count 0 2006.189.07:34:42.01#ibcon#about to read 3, iclass 35, count 0 2006.189.07:34:42.04#ibcon#read 3, iclass 35, count 0 2006.189.07:34:42.04#ibcon#about to read 4, iclass 35, count 0 2006.189.07:34:42.04#ibcon#read 4, iclass 35, count 0 2006.189.07:34:42.04#ibcon#about to read 5, iclass 35, count 0 2006.189.07:34:42.04#ibcon#read 5, iclass 35, count 0 2006.189.07:34:42.04#ibcon#about to read 6, iclass 35, count 0 2006.189.07:34:42.04#ibcon#read 6, iclass 35, count 0 2006.189.07:34:42.04#ibcon#end of sib2, iclass 35, count 0 2006.189.07:34:42.04#ibcon#*after write, iclass 35, count 0 2006.189.07:34:42.04#ibcon#*before return 0, iclass 35, count 0 2006.189.07:34:42.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:42.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:34:42.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:34:42.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:34:42.04$vc4f8/vblo=5,744.99 2006.189.07:34:42.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:34:42.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:34:42.04#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:42.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:42.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:42.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:42.04#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:34:42.04#ibcon#first serial, iclass 37, count 0 2006.189.07:34:42.04#ibcon#enter sib2, iclass 37, count 0 2006.189.07:34:42.04#ibcon#flushed, iclass 37, count 0 2006.189.07:34:42.04#ibcon#about to write, iclass 37, count 0 2006.189.07:34:42.04#ibcon#wrote, iclass 37, count 0 2006.189.07:34:42.04#ibcon#about to read 3, iclass 37, count 0 2006.189.07:34:42.06#ibcon#read 3, iclass 37, count 0 2006.189.07:34:42.06#ibcon#about to read 4, iclass 37, count 0 2006.189.07:34:42.06#ibcon#read 4, iclass 37, count 0 2006.189.07:34:42.06#ibcon#about to read 5, iclass 37, count 0 2006.189.07:34:42.06#ibcon#read 5, iclass 37, count 0 2006.189.07:34:42.06#ibcon#about to read 6, iclass 37, count 0 2006.189.07:34:42.06#ibcon#read 6, iclass 37, count 0 2006.189.07:34:42.06#ibcon#end of sib2, iclass 37, count 0 2006.189.07:34:42.06#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:34:42.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:34:42.06#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:34:42.06#ibcon#*before write, iclass 37, count 0 2006.189.07:34:42.06#ibcon#enter sib2, iclass 37, count 0 2006.189.07:34:42.06#ibcon#flushed, iclass 37, count 0 2006.189.07:34:42.06#ibcon#about to write, iclass 37, count 0 2006.189.07:34:42.06#ibcon#wrote, iclass 37, count 0 2006.189.07:34:42.06#ibcon#about to read 3, iclass 37, count 0 2006.189.07:34:42.10#ibcon#read 3, iclass 37, count 0 2006.189.07:34:42.10#ibcon#about to read 4, iclass 37, count 0 2006.189.07:34:42.10#ibcon#read 4, iclass 37, count 0 2006.189.07:34:42.10#ibcon#about to read 5, iclass 37, count 0 2006.189.07:34:42.10#ibcon#read 5, iclass 37, count 0 2006.189.07:34:42.10#ibcon#about to read 6, iclass 37, count 0 2006.189.07:34:42.10#ibcon#read 6, iclass 37, count 0 2006.189.07:34:42.10#ibcon#end of sib2, iclass 37, count 0 2006.189.07:34:42.10#ibcon#*after write, iclass 37, count 0 2006.189.07:34:42.10#ibcon#*before return 0, iclass 37, count 0 2006.189.07:34:42.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:42.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:34:42.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:34:42.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:34:42.10$vc4f8/vb=5,4 2006.189.07:34:42.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:34:42.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:34:42.10#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:42.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:42.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:42.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:42.16#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:34:42.16#ibcon#first serial, iclass 39, count 2 2006.189.07:34:42.16#ibcon#enter sib2, iclass 39, count 2 2006.189.07:34:42.16#ibcon#flushed, iclass 39, count 2 2006.189.07:34:42.16#ibcon#about to write, iclass 39, count 2 2006.189.07:34:42.16#ibcon#wrote, iclass 39, count 2 2006.189.07:34:42.16#ibcon#about to read 3, iclass 39, count 2 2006.189.07:34:42.18#ibcon#read 3, iclass 39, count 2 2006.189.07:34:42.18#ibcon#about to read 4, iclass 39, count 2 2006.189.07:34:42.18#ibcon#read 4, iclass 39, count 2 2006.189.07:34:42.18#ibcon#about to read 5, iclass 39, count 2 2006.189.07:34:42.18#ibcon#read 5, iclass 39, count 2 2006.189.07:34:42.18#ibcon#about to read 6, iclass 39, count 2 2006.189.07:34:42.18#ibcon#read 6, iclass 39, count 2 2006.189.07:34:42.18#ibcon#end of sib2, iclass 39, count 2 2006.189.07:34:42.18#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:34:42.18#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:34:42.18#ibcon#[27=AT05-04\r\n] 2006.189.07:34:42.18#ibcon#*before write, iclass 39, count 2 2006.189.07:34:42.18#ibcon#enter sib2, iclass 39, count 2 2006.189.07:34:42.18#ibcon#flushed, iclass 39, count 2 2006.189.07:34:42.18#ibcon#about to write, iclass 39, count 2 2006.189.07:34:42.18#ibcon#wrote, iclass 39, count 2 2006.189.07:34:42.18#ibcon#about to read 3, iclass 39, count 2 2006.189.07:34:42.21#ibcon#read 3, iclass 39, count 2 2006.189.07:34:42.21#ibcon#about to read 4, iclass 39, count 2 2006.189.07:34:42.21#ibcon#read 4, iclass 39, count 2 2006.189.07:34:42.21#ibcon#about to read 5, iclass 39, count 2 2006.189.07:34:42.21#ibcon#read 5, iclass 39, count 2 2006.189.07:34:42.21#ibcon#about to read 6, iclass 39, count 2 2006.189.07:34:42.21#ibcon#read 6, iclass 39, count 2 2006.189.07:34:42.21#ibcon#end of sib2, iclass 39, count 2 2006.189.07:34:42.21#ibcon#*after write, iclass 39, count 2 2006.189.07:34:42.21#ibcon#*before return 0, iclass 39, count 2 2006.189.07:34:42.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:42.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:34:42.21#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:34:42.21#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:42.21#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:42.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:42.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:42.33#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:34:42.33#ibcon#first serial, iclass 39, count 0 2006.189.07:34:42.33#ibcon#enter sib2, iclass 39, count 0 2006.189.07:34:42.33#ibcon#flushed, iclass 39, count 0 2006.189.07:34:42.33#ibcon#about to write, iclass 39, count 0 2006.189.07:34:42.33#ibcon#wrote, iclass 39, count 0 2006.189.07:34:42.33#ibcon#about to read 3, iclass 39, count 0 2006.189.07:34:42.35#ibcon#read 3, iclass 39, count 0 2006.189.07:34:42.35#ibcon#about to read 4, iclass 39, count 0 2006.189.07:34:42.35#ibcon#read 4, iclass 39, count 0 2006.189.07:34:42.35#ibcon#about to read 5, iclass 39, count 0 2006.189.07:34:42.35#ibcon#read 5, iclass 39, count 0 2006.189.07:34:42.35#ibcon#about to read 6, iclass 39, count 0 2006.189.07:34:42.35#ibcon#read 6, iclass 39, count 0 2006.189.07:34:42.35#ibcon#end of sib2, iclass 39, count 0 2006.189.07:34:42.35#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:34:42.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:34:42.35#ibcon#[27=USB\r\n] 2006.189.07:34:42.35#ibcon#*before write, iclass 39, count 0 2006.189.07:34:42.35#ibcon#enter sib2, iclass 39, count 0 2006.189.07:34:42.35#ibcon#flushed, iclass 39, count 0 2006.189.07:34:42.35#ibcon#about to write, iclass 39, count 0 2006.189.07:34:42.35#ibcon#wrote, iclass 39, count 0 2006.189.07:34:42.35#ibcon#about to read 3, iclass 39, count 0 2006.189.07:34:42.38#ibcon#read 3, iclass 39, count 0 2006.189.07:34:42.38#ibcon#about to read 4, iclass 39, count 0 2006.189.07:34:42.38#ibcon#read 4, iclass 39, count 0 2006.189.07:34:42.38#ibcon#about to read 5, iclass 39, count 0 2006.189.07:34:42.38#ibcon#read 5, iclass 39, count 0 2006.189.07:34:42.38#ibcon#about to read 6, iclass 39, count 0 2006.189.07:34:42.38#ibcon#read 6, iclass 39, count 0 2006.189.07:34:42.38#ibcon#end of sib2, iclass 39, count 0 2006.189.07:34:42.38#ibcon#*after write, iclass 39, count 0 2006.189.07:34:42.38#ibcon#*before return 0, iclass 39, count 0 2006.189.07:34:42.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:42.38#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:34:42.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:34:42.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:34:42.38$vc4f8/vblo=6,752.99 2006.189.07:34:42.38#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:34:42.38#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:34:42.38#ibcon#ireg 17 cls_cnt 0 2006.189.07:34:42.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:42.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:42.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:42.38#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:34:42.38#ibcon#first serial, iclass 3, count 0 2006.189.07:34:42.38#ibcon#enter sib2, iclass 3, count 0 2006.189.07:34:42.38#ibcon#flushed, iclass 3, count 0 2006.189.07:34:42.38#ibcon#about to write, iclass 3, count 0 2006.189.07:34:42.38#ibcon#wrote, iclass 3, count 0 2006.189.07:34:42.38#ibcon#about to read 3, iclass 3, count 0 2006.189.07:34:42.40#ibcon#read 3, iclass 3, count 0 2006.189.07:34:42.40#ibcon#about to read 4, iclass 3, count 0 2006.189.07:34:42.40#ibcon#read 4, iclass 3, count 0 2006.189.07:34:42.40#ibcon#about to read 5, iclass 3, count 0 2006.189.07:34:42.40#ibcon#read 5, iclass 3, count 0 2006.189.07:34:42.40#ibcon#about to read 6, iclass 3, count 0 2006.189.07:34:42.40#ibcon#read 6, iclass 3, count 0 2006.189.07:34:42.40#ibcon#end of sib2, iclass 3, count 0 2006.189.07:34:42.40#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:34:42.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:34:42.40#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:34:42.40#ibcon#*before write, iclass 3, count 0 2006.189.07:34:42.40#ibcon#enter sib2, iclass 3, count 0 2006.189.07:34:42.40#ibcon#flushed, iclass 3, count 0 2006.189.07:34:42.40#ibcon#about to write, iclass 3, count 0 2006.189.07:34:42.40#ibcon#wrote, iclass 3, count 0 2006.189.07:34:42.40#ibcon#about to read 3, iclass 3, count 0 2006.189.07:34:42.44#ibcon#read 3, iclass 3, count 0 2006.189.07:34:42.44#ibcon#about to read 4, iclass 3, count 0 2006.189.07:34:42.44#ibcon#read 4, iclass 3, count 0 2006.189.07:34:42.44#ibcon#about to read 5, iclass 3, count 0 2006.189.07:34:42.44#ibcon#read 5, iclass 3, count 0 2006.189.07:34:42.44#ibcon#about to read 6, iclass 3, count 0 2006.189.07:34:42.44#ibcon#read 6, iclass 3, count 0 2006.189.07:34:42.44#ibcon#end of sib2, iclass 3, count 0 2006.189.07:34:42.44#ibcon#*after write, iclass 3, count 0 2006.189.07:34:42.44#ibcon#*before return 0, iclass 3, count 0 2006.189.07:34:42.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:42.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:34:42.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:34:42.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:34:42.44$vc4f8/vb=6,4 2006.189.07:34:42.44#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:34:42.44#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:34:42.44#ibcon#ireg 11 cls_cnt 2 2006.189.07:34:42.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:42.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:42.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:42.50#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:34:42.50#ibcon#first serial, iclass 5, count 2 2006.189.07:34:42.50#ibcon#enter sib2, iclass 5, count 2 2006.189.07:34:42.50#ibcon#flushed, iclass 5, count 2 2006.189.07:34:42.50#ibcon#about to write, iclass 5, count 2 2006.189.07:34:42.50#ibcon#wrote, iclass 5, count 2 2006.189.07:34:42.50#ibcon#about to read 3, iclass 5, count 2 2006.189.07:34:42.52#ibcon#read 3, iclass 5, count 2 2006.189.07:34:42.52#ibcon#about to read 4, iclass 5, count 2 2006.189.07:34:42.52#ibcon#read 4, iclass 5, count 2 2006.189.07:34:42.52#ibcon#about to read 5, iclass 5, count 2 2006.189.07:34:42.52#ibcon#read 5, iclass 5, count 2 2006.189.07:34:42.52#ibcon#about to read 6, iclass 5, count 2 2006.189.07:34:42.52#ibcon#read 6, iclass 5, count 2 2006.189.07:34:42.52#ibcon#end of sib2, iclass 5, count 2 2006.189.07:34:42.52#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:34:42.52#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:34:42.52#ibcon#[27=AT06-04\r\n] 2006.189.07:34:42.52#ibcon#*before write, iclass 5, count 2 2006.189.07:34:42.52#ibcon#enter sib2, iclass 5, count 2 2006.189.07:34:42.52#ibcon#flushed, iclass 5, count 2 2006.189.07:34:42.52#ibcon#about to write, iclass 5, count 2 2006.189.07:34:42.52#ibcon#wrote, iclass 5, count 2 2006.189.07:34:42.52#ibcon#about to read 3, iclass 5, count 2 2006.189.07:34:42.55#ibcon#read 3, iclass 5, count 2 2006.189.07:34:42.55#ibcon#about to read 4, iclass 5, count 2 2006.189.07:34:42.55#ibcon#read 4, iclass 5, count 2 2006.189.07:34:42.55#ibcon#about to read 5, iclass 5, count 2 2006.189.07:34:42.55#ibcon#read 5, iclass 5, count 2 2006.189.07:34:42.55#ibcon#about to read 6, iclass 5, count 2 2006.189.07:34:42.55#ibcon#read 6, iclass 5, count 2 2006.189.07:34:42.55#ibcon#end of sib2, iclass 5, count 2 2006.189.07:34:42.55#ibcon#*after write, iclass 5, count 2 2006.189.07:34:42.55#ibcon#*before return 0, iclass 5, count 2 2006.189.07:34:42.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:42.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:34:42.55#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:34:42.55#ibcon#ireg 7 cls_cnt 0 2006.189.07:34:42.55#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:42.67#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:42.67#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:42.67#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:34:42.67#ibcon#first serial, iclass 5, count 0 2006.189.07:34:42.67#ibcon#enter sib2, iclass 5, count 0 2006.189.07:34:42.67#ibcon#flushed, iclass 5, count 0 2006.189.07:34:42.67#ibcon#about to write, iclass 5, count 0 2006.189.07:34:42.67#ibcon#wrote, iclass 5, count 0 2006.189.07:34:42.67#ibcon#about to read 3, iclass 5, count 0 2006.189.07:34:42.69#ibcon#read 3, iclass 5, count 0 2006.189.07:34:42.69#ibcon#about to read 4, iclass 5, count 0 2006.189.07:34:42.69#ibcon#read 4, iclass 5, count 0 2006.189.07:34:42.69#ibcon#about to read 5, iclass 5, count 0 2006.189.07:34:42.69#ibcon#read 5, iclass 5, count 0 2006.189.07:34:42.69#ibcon#about to read 6, iclass 5, count 0 2006.189.07:34:42.69#ibcon#read 6, iclass 5, count 0 2006.189.07:34:42.69#ibcon#end of sib2, iclass 5, count 0 2006.189.07:34:42.69#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:34:42.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:34:42.69#ibcon#[27=USB\r\n] 2006.189.07:34:42.69#ibcon#*before write, iclass 5, count 0 2006.189.07:34:42.69#ibcon#enter sib2, iclass 5, count 0 2006.189.07:34:42.69#ibcon#flushed, iclass 5, count 0 2006.189.07:34:42.69#ibcon#about to write, iclass 5, count 0 2006.189.07:34:42.69#ibcon#wrote, iclass 5, count 0 2006.189.07:34:42.69#ibcon#about to read 3, iclass 5, count 0 2006.189.07:34:42.72#ibcon#read 3, iclass 5, count 0 2006.189.07:34:42.72#ibcon#about to read 4, iclass 5, count 0 2006.189.07:34:42.72#ibcon#read 4, iclass 5, count 0 2006.189.07:34:42.72#ibcon#about to read 5, iclass 5, count 0 2006.189.07:34:42.72#ibcon#read 5, iclass 5, count 0 2006.189.07:34:42.72#ibcon#about to read 6, iclass 5, count 0 2006.189.07:34:42.72#ibcon#read 6, iclass 5, count 0 2006.189.07:34:42.72#ibcon#end of sib2, iclass 5, count 0 2006.189.07:34:42.72#ibcon#*after write, iclass 5, count 0 2006.189.07:34:42.72#ibcon#*before return 0, iclass 5, count 0 2006.189.07:34:42.72#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:42.72#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:34:42.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:34:42.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:34:42.72$vc4f8/vabw=wide 2006.189.07:34:42.72#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:34:42.72#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:34:42.72#ibcon#ireg 8 cls_cnt 0 2006.189.07:34:42.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:42.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:42.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:42.72#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:34:42.72#ibcon#first serial, iclass 7, count 0 2006.189.07:34:42.72#ibcon#enter sib2, iclass 7, count 0 2006.189.07:34:42.72#ibcon#flushed, iclass 7, count 0 2006.189.07:34:42.72#ibcon#about to write, iclass 7, count 0 2006.189.07:34:42.72#ibcon#wrote, iclass 7, count 0 2006.189.07:34:42.72#ibcon#about to read 3, iclass 7, count 0 2006.189.07:34:42.74#ibcon#read 3, iclass 7, count 0 2006.189.07:34:42.74#ibcon#about to read 4, iclass 7, count 0 2006.189.07:34:42.74#ibcon#read 4, iclass 7, count 0 2006.189.07:34:42.74#ibcon#about to read 5, iclass 7, count 0 2006.189.07:34:42.74#ibcon#read 5, iclass 7, count 0 2006.189.07:34:42.74#ibcon#about to read 6, iclass 7, count 0 2006.189.07:34:42.74#ibcon#read 6, iclass 7, count 0 2006.189.07:34:42.74#ibcon#end of sib2, iclass 7, count 0 2006.189.07:34:42.74#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:34:42.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:34:42.74#ibcon#[25=BW32\r\n] 2006.189.07:34:42.74#ibcon#*before write, iclass 7, count 0 2006.189.07:34:42.74#ibcon#enter sib2, iclass 7, count 0 2006.189.07:34:42.74#ibcon#flushed, iclass 7, count 0 2006.189.07:34:42.74#ibcon#about to write, iclass 7, count 0 2006.189.07:34:42.74#ibcon#wrote, iclass 7, count 0 2006.189.07:34:42.74#ibcon#about to read 3, iclass 7, count 0 2006.189.07:34:42.77#ibcon#read 3, iclass 7, count 0 2006.189.07:34:42.77#ibcon#about to read 4, iclass 7, count 0 2006.189.07:34:42.77#ibcon#read 4, iclass 7, count 0 2006.189.07:34:42.77#ibcon#about to read 5, iclass 7, count 0 2006.189.07:34:42.77#ibcon#read 5, iclass 7, count 0 2006.189.07:34:42.77#ibcon#about to read 6, iclass 7, count 0 2006.189.07:34:42.77#ibcon#read 6, iclass 7, count 0 2006.189.07:34:42.77#ibcon#end of sib2, iclass 7, count 0 2006.189.07:34:42.77#ibcon#*after write, iclass 7, count 0 2006.189.07:34:42.77#ibcon#*before return 0, iclass 7, count 0 2006.189.07:34:42.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:42.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:34:42.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:34:42.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:34:42.77$vc4f8/vbbw=wide 2006.189.07:34:42.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.07:34:42.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.07:34:42.77#ibcon#ireg 8 cls_cnt 0 2006.189.07:34:42.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:34:42.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:34:42.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:34:42.84#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:34:42.84#ibcon#first serial, iclass 11, count 0 2006.189.07:34:42.84#ibcon#enter sib2, iclass 11, count 0 2006.189.07:34:42.84#ibcon#flushed, iclass 11, count 0 2006.189.07:34:42.84#ibcon#about to write, iclass 11, count 0 2006.189.07:34:42.84#ibcon#wrote, iclass 11, count 0 2006.189.07:34:42.84#ibcon#about to read 3, iclass 11, count 0 2006.189.07:34:42.86#ibcon#read 3, iclass 11, count 0 2006.189.07:34:42.86#ibcon#about to read 4, iclass 11, count 0 2006.189.07:34:42.86#ibcon#read 4, iclass 11, count 0 2006.189.07:34:42.86#ibcon#about to read 5, iclass 11, count 0 2006.189.07:34:42.86#ibcon#read 5, iclass 11, count 0 2006.189.07:34:42.86#ibcon#about to read 6, iclass 11, count 0 2006.189.07:34:42.86#ibcon#read 6, iclass 11, count 0 2006.189.07:34:42.86#ibcon#end of sib2, iclass 11, count 0 2006.189.07:34:42.86#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:34:42.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:34:42.86#ibcon#[27=BW32\r\n] 2006.189.07:34:42.86#ibcon#*before write, iclass 11, count 0 2006.189.07:34:42.86#ibcon#enter sib2, iclass 11, count 0 2006.189.07:34:42.86#ibcon#flushed, iclass 11, count 0 2006.189.07:34:42.86#ibcon#about to write, iclass 11, count 0 2006.189.07:34:42.86#ibcon#wrote, iclass 11, count 0 2006.189.07:34:42.86#ibcon#about to read 3, iclass 11, count 0 2006.189.07:34:42.89#ibcon#read 3, iclass 11, count 0 2006.189.07:34:42.89#ibcon#about to read 4, iclass 11, count 0 2006.189.07:34:42.89#ibcon#read 4, iclass 11, count 0 2006.189.07:34:42.89#ibcon#about to read 5, iclass 11, count 0 2006.189.07:34:42.89#ibcon#read 5, iclass 11, count 0 2006.189.07:34:42.89#ibcon#about to read 6, iclass 11, count 0 2006.189.07:34:42.89#ibcon#read 6, iclass 11, count 0 2006.189.07:34:42.89#ibcon#end of sib2, iclass 11, count 0 2006.189.07:34:42.89#ibcon#*after write, iclass 11, count 0 2006.189.07:34:42.89#ibcon#*before return 0, iclass 11, count 0 2006.189.07:34:42.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:34:42.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:34:42.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:34:42.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:34:42.89$4f8m12a/ifd4f 2006.189.07:34:42.89$ifd4f/lo= 2006.189.07:34:42.89$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:34:42.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:34:42.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:34:42.90$ifd4f/patch= 2006.189.07:34:42.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:34:42.90$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:34:42.90$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:34:42.90$4f8m12a/"form=m,16.000,1:2 2006.189.07:34:42.90$4f8m12a/"tpicd 2006.189.07:34:42.90$4f8m12a/echo=off 2006.189.07:34:42.90$4f8m12a/xlog=off 2006.189.07:34:42.90:!2006.189.07:35:10 2006.189.07:34:55.14#trakl#Source acquired 2006.189.07:34:55.14#flagr#flagr/antenna,acquired 2006.189.07:35:10.01:preob 2006.189.07:35:11.14/onsource/TRACKING 2006.189.07:35:11.14:!2006.189.07:35:20 2006.189.07:35:20.00:data_valid=on 2006.189.07:35:20.00:midob 2006.189.07:35:20.14/onsource/TRACKING 2006.189.07:35:20.14/wx/26.46,1008.9,86 2006.189.07:35:20.25/cable/+6.4533E-03 2006.189.07:35:21.34/va/01,08,usb,yes,28,30 2006.189.07:35:21.34/va/02,07,usb,yes,28,30 2006.189.07:35:21.34/va/03,06,usb,yes,30,30 2006.189.07:35:21.34/va/04,07,usb,yes,29,31 2006.189.07:35:21.34/va/05,07,usb,yes,30,32 2006.189.07:35:21.34/va/06,06,usb,yes,29,29 2006.189.07:35:21.34/va/07,06,usb,yes,30,30 2006.189.07:35:21.34/va/08,06,usb,yes,32,31 2006.189.07:35:21.57/valo/01,532.99,yes,locked 2006.189.07:35:21.57/valo/02,572.99,yes,locked 2006.189.07:35:21.57/valo/03,672.99,yes,locked 2006.189.07:35:21.57/valo/04,832.99,yes,locked 2006.189.07:35:21.57/valo/05,652.99,yes,locked 2006.189.07:35:21.57/valo/06,772.99,yes,locked 2006.189.07:35:21.57/valo/07,832.99,yes,locked 2006.189.07:35:21.57/valo/08,852.99,yes,locked 2006.189.07:35:22.66/vb/01,04,usb,yes,28,27 2006.189.07:35:22.66/vb/02,04,usb,yes,30,32 2006.189.07:35:22.66/vb/03,04,usb,yes,27,30 2006.189.07:35:22.66/vb/04,04,usb,yes,27,28 2006.189.07:35:22.66/vb/05,04,usb,yes,26,30 2006.189.07:35:22.66/vb/06,04,usb,yes,27,30 2006.189.07:35:22.66/vb/07,04,usb,yes,29,29 2006.189.07:35:22.66/vb/08,04,usb,yes,27,30 2006.189.07:35:22.89/vblo/01,632.99,yes,locked 2006.189.07:35:22.89/vblo/02,640.99,yes,locked 2006.189.07:35:22.89/vblo/03,656.99,yes,locked 2006.189.07:35:22.89/vblo/04,712.99,yes,locked 2006.189.07:35:22.89/vblo/05,744.99,yes,locked 2006.189.07:35:22.89/vblo/06,752.99,yes,locked 2006.189.07:35:22.89/vblo/07,734.99,yes,locked 2006.189.07:35:22.89/vblo/08,744.99,yes,locked 2006.189.07:35:23.04/vabw/8 2006.189.07:35:23.19/vbbw/8 2006.189.07:35:23.28/xfe/off,on,14.5 2006.189.07:35:23.65/ifatt/23,28,28,28 2006.189.07:35:24.07/fmout-gps/S +2.97E-07 2006.189.07:35:24.13:!2006.189.07:36:20 2006.189.07:36:20.01:data_valid=off 2006.189.07:36:20.02:postob 2006.189.07:36:20.15/cable/+6.4535E-03 2006.189.07:36:20.16/wx/26.44,1008.9,86 2006.189.07:36:21.07/fmout-gps/S +2.97E-07 2006.189.07:36:21.08:scan_name=189-0737,k06189,60 2006.189.07:36:21.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.189.07:36:21.13#flagr#flagr/antenna,new-source 2006.189.07:36:22.13:checkk5 2006.189.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:36:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:36:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:36:23.67/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:36:24.07/chk_obsdata//k5ts1/T1890735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:36:24.44/chk_obsdata//k5ts2/T1890735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:36:24.82/chk_obsdata//k5ts3/T1890735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:36:25.20/chk_obsdata//k5ts4/T1890735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:36:25.89/k5log//k5ts1_log_newline 2006.189.07:36:26.59/k5log//k5ts2_log_newline 2006.189.07:36:27.29/k5log//k5ts3_log_newline 2006.189.07:36:27.98/k5log//k5ts4_log_newline 2006.189.07:36:28.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:36:28.01:4f8m12a=1 2006.189.07:36:28.01$4f8m12a/echo=on 2006.189.07:36:28.01$4f8m12a/pcalon 2006.189.07:36:28.01$pcalon/"no phase cal control is implemented here 2006.189.07:36:28.01$4f8m12a/"tpicd=stop 2006.189.07:36:28.01$4f8m12a/vc4f8 2006.189.07:36:28.01$vc4f8/valo=1,532.99 2006.189.07:36:28.02#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.07:36:28.02#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.07:36:28.02#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:28.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:28.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:28.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:28.02#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:36:28.02#ibcon#first serial, iclass 18, count 0 2006.189.07:36:28.02#ibcon#enter sib2, iclass 18, count 0 2006.189.07:36:28.02#ibcon#flushed, iclass 18, count 0 2006.189.07:36:28.02#ibcon#about to write, iclass 18, count 0 2006.189.07:36:28.02#ibcon#wrote, iclass 18, count 0 2006.189.07:36:28.02#ibcon#about to read 3, iclass 18, count 0 2006.189.07:36:28.06#ibcon#read 3, iclass 18, count 0 2006.189.07:36:28.06#ibcon#about to read 4, iclass 18, count 0 2006.189.07:36:28.06#ibcon#read 4, iclass 18, count 0 2006.189.07:36:28.06#ibcon#about to read 5, iclass 18, count 0 2006.189.07:36:28.06#ibcon#read 5, iclass 18, count 0 2006.189.07:36:28.06#ibcon#about to read 6, iclass 18, count 0 2006.189.07:36:28.06#ibcon#read 6, iclass 18, count 0 2006.189.07:36:28.06#ibcon#end of sib2, iclass 18, count 0 2006.189.07:36:28.06#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:36:28.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:36:28.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:36:28.06#ibcon#*before write, iclass 18, count 0 2006.189.07:36:28.06#ibcon#enter sib2, iclass 18, count 0 2006.189.07:36:28.06#ibcon#flushed, iclass 18, count 0 2006.189.07:36:28.06#ibcon#about to write, iclass 18, count 0 2006.189.07:36:28.06#ibcon#wrote, iclass 18, count 0 2006.189.07:36:28.06#ibcon#about to read 3, iclass 18, count 0 2006.189.07:36:28.11#ibcon#read 3, iclass 18, count 0 2006.189.07:36:28.11#ibcon#about to read 4, iclass 18, count 0 2006.189.07:36:28.11#ibcon#read 4, iclass 18, count 0 2006.189.07:36:28.11#ibcon#about to read 5, iclass 18, count 0 2006.189.07:36:28.11#ibcon#read 5, iclass 18, count 0 2006.189.07:36:28.11#ibcon#about to read 6, iclass 18, count 0 2006.189.07:36:28.11#ibcon#read 6, iclass 18, count 0 2006.189.07:36:28.11#ibcon#end of sib2, iclass 18, count 0 2006.189.07:36:28.11#ibcon#*after write, iclass 18, count 0 2006.189.07:36:28.11#ibcon#*before return 0, iclass 18, count 0 2006.189.07:36:28.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:28.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:28.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:36:28.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:36:28.11$vc4f8/va=1,8 2006.189.07:36:28.11#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:36:28.11#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:36:28.11#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:28.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:28.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:28.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:28.11#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:36:28.11#ibcon#first serial, iclass 20, count 2 2006.189.07:36:28.11#ibcon#enter sib2, iclass 20, count 2 2006.189.07:36:28.11#ibcon#flushed, iclass 20, count 2 2006.189.07:36:28.11#ibcon#about to write, iclass 20, count 2 2006.189.07:36:28.11#ibcon#wrote, iclass 20, count 2 2006.189.07:36:28.11#ibcon#about to read 3, iclass 20, count 2 2006.189.07:36:28.13#ibcon#read 3, iclass 20, count 2 2006.189.07:36:28.13#ibcon#about to read 4, iclass 20, count 2 2006.189.07:36:28.13#ibcon#read 4, iclass 20, count 2 2006.189.07:36:28.13#ibcon#about to read 5, iclass 20, count 2 2006.189.07:36:28.13#ibcon#read 5, iclass 20, count 2 2006.189.07:36:28.13#ibcon#about to read 6, iclass 20, count 2 2006.189.07:36:28.13#ibcon#read 6, iclass 20, count 2 2006.189.07:36:28.13#ibcon#end of sib2, iclass 20, count 2 2006.189.07:36:28.13#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:36:28.13#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:36:28.13#ibcon#[25=AT01-08\r\n] 2006.189.07:36:28.13#ibcon#*before write, iclass 20, count 2 2006.189.07:36:28.13#ibcon#enter sib2, iclass 20, count 2 2006.189.07:36:28.13#ibcon#flushed, iclass 20, count 2 2006.189.07:36:28.13#ibcon#about to write, iclass 20, count 2 2006.189.07:36:28.13#ibcon#wrote, iclass 20, count 2 2006.189.07:36:28.13#ibcon#about to read 3, iclass 20, count 2 2006.189.07:36:28.16#ibcon#read 3, iclass 20, count 2 2006.189.07:36:28.16#ibcon#about to read 4, iclass 20, count 2 2006.189.07:36:28.16#ibcon#read 4, iclass 20, count 2 2006.189.07:36:28.16#ibcon#about to read 5, iclass 20, count 2 2006.189.07:36:28.16#ibcon#read 5, iclass 20, count 2 2006.189.07:36:28.16#ibcon#about to read 6, iclass 20, count 2 2006.189.07:36:28.16#ibcon#read 6, iclass 20, count 2 2006.189.07:36:28.16#ibcon#end of sib2, iclass 20, count 2 2006.189.07:36:28.16#ibcon#*after write, iclass 20, count 2 2006.189.07:36:28.16#ibcon#*before return 0, iclass 20, count 2 2006.189.07:36:28.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:28.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:28.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:36:28.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:28.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:28.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:28.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:28.28#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:36:28.28#ibcon#first serial, iclass 20, count 0 2006.189.07:36:28.28#ibcon#enter sib2, iclass 20, count 0 2006.189.07:36:28.28#ibcon#flushed, iclass 20, count 0 2006.189.07:36:28.28#ibcon#about to write, iclass 20, count 0 2006.189.07:36:28.28#ibcon#wrote, iclass 20, count 0 2006.189.07:36:28.28#ibcon#about to read 3, iclass 20, count 0 2006.189.07:36:28.30#ibcon#read 3, iclass 20, count 0 2006.189.07:36:28.30#ibcon#about to read 4, iclass 20, count 0 2006.189.07:36:28.30#ibcon#read 4, iclass 20, count 0 2006.189.07:36:28.30#ibcon#about to read 5, iclass 20, count 0 2006.189.07:36:28.30#ibcon#read 5, iclass 20, count 0 2006.189.07:36:28.30#ibcon#about to read 6, iclass 20, count 0 2006.189.07:36:28.30#ibcon#read 6, iclass 20, count 0 2006.189.07:36:28.30#ibcon#end of sib2, iclass 20, count 0 2006.189.07:36:28.30#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:36:28.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:36:28.30#ibcon#[25=USB\r\n] 2006.189.07:36:28.30#ibcon#*before write, iclass 20, count 0 2006.189.07:36:28.30#ibcon#enter sib2, iclass 20, count 0 2006.189.07:36:28.30#ibcon#flushed, iclass 20, count 0 2006.189.07:36:28.30#ibcon#about to write, iclass 20, count 0 2006.189.07:36:28.30#ibcon#wrote, iclass 20, count 0 2006.189.07:36:28.30#ibcon#about to read 3, iclass 20, count 0 2006.189.07:36:28.33#ibcon#read 3, iclass 20, count 0 2006.189.07:36:28.33#ibcon#about to read 4, iclass 20, count 0 2006.189.07:36:28.33#ibcon#read 4, iclass 20, count 0 2006.189.07:36:28.33#ibcon#about to read 5, iclass 20, count 0 2006.189.07:36:28.33#ibcon#read 5, iclass 20, count 0 2006.189.07:36:28.33#ibcon#about to read 6, iclass 20, count 0 2006.189.07:36:28.33#ibcon#read 6, iclass 20, count 0 2006.189.07:36:28.33#ibcon#end of sib2, iclass 20, count 0 2006.189.07:36:28.33#ibcon#*after write, iclass 20, count 0 2006.189.07:36:28.33#ibcon#*before return 0, iclass 20, count 0 2006.189.07:36:28.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:28.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:28.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:36:28.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:36:28.33$vc4f8/valo=2,572.99 2006.189.07:36:28.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:36:28.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:36:28.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:28.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:28.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:28.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:28.33#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:36:28.33#ibcon#first serial, iclass 22, count 0 2006.189.07:36:28.33#ibcon#enter sib2, iclass 22, count 0 2006.189.07:36:28.33#ibcon#flushed, iclass 22, count 0 2006.189.07:36:28.33#ibcon#about to write, iclass 22, count 0 2006.189.07:36:28.33#ibcon#wrote, iclass 22, count 0 2006.189.07:36:28.33#ibcon#about to read 3, iclass 22, count 0 2006.189.07:36:28.35#ibcon#read 3, iclass 22, count 0 2006.189.07:36:28.35#ibcon#about to read 4, iclass 22, count 0 2006.189.07:36:28.35#ibcon#read 4, iclass 22, count 0 2006.189.07:36:28.35#ibcon#about to read 5, iclass 22, count 0 2006.189.07:36:28.35#ibcon#read 5, iclass 22, count 0 2006.189.07:36:28.35#ibcon#about to read 6, iclass 22, count 0 2006.189.07:36:28.35#ibcon#read 6, iclass 22, count 0 2006.189.07:36:28.35#ibcon#end of sib2, iclass 22, count 0 2006.189.07:36:28.35#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:36:28.35#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:36:28.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:36:28.35#ibcon#*before write, iclass 22, count 0 2006.189.07:36:28.35#ibcon#enter sib2, iclass 22, count 0 2006.189.07:36:28.35#ibcon#flushed, iclass 22, count 0 2006.189.07:36:28.35#ibcon#about to write, iclass 22, count 0 2006.189.07:36:28.35#ibcon#wrote, iclass 22, count 0 2006.189.07:36:28.35#ibcon#about to read 3, iclass 22, count 0 2006.189.07:36:28.40#ibcon#read 3, iclass 22, count 0 2006.189.07:36:28.40#ibcon#about to read 4, iclass 22, count 0 2006.189.07:36:28.40#ibcon#read 4, iclass 22, count 0 2006.189.07:36:28.40#ibcon#about to read 5, iclass 22, count 0 2006.189.07:36:28.40#ibcon#read 5, iclass 22, count 0 2006.189.07:36:28.40#ibcon#about to read 6, iclass 22, count 0 2006.189.07:36:28.40#ibcon#read 6, iclass 22, count 0 2006.189.07:36:28.40#ibcon#end of sib2, iclass 22, count 0 2006.189.07:36:28.40#ibcon#*after write, iclass 22, count 0 2006.189.07:36:28.40#ibcon#*before return 0, iclass 22, count 0 2006.189.07:36:28.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:28.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:28.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:36:28.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:36:28.40$vc4f8/va=2,7 2006.189.07:36:28.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:36:28.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:36:28.40#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:28.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:28.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:28.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:28.44#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:36:28.44#ibcon#first serial, iclass 24, count 2 2006.189.07:36:28.44#ibcon#enter sib2, iclass 24, count 2 2006.189.07:36:28.44#ibcon#flushed, iclass 24, count 2 2006.189.07:36:28.44#ibcon#about to write, iclass 24, count 2 2006.189.07:36:28.44#ibcon#wrote, iclass 24, count 2 2006.189.07:36:28.44#ibcon#about to read 3, iclass 24, count 2 2006.189.07:36:28.46#ibcon#read 3, iclass 24, count 2 2006.189.07:36:28.46#ibcon#about to read 4, iclass 24, count 2 2006.189.07:36:28.46#ibcon#read 4, iclass 24, count 2 2006.189.07:36:28.46#ibcon#about to read 5, iclass 24, count 2 2006.189.07:36:28.46#ibcon#read 5, iclass 24, count 2 2006.189.07:36:28.46#ibcon#about to read 6, iclass 24, count 2 2006.189.07:36:28.46#ibcon#read 6, iclass 24, count 2 2006.189.07:36:28.46#ibcon#end of sib2, iclass 24, count 2 2006.189.07:36:28.46#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:36:28.46#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:36:28.46#ibcon#[25=AT02-07\r\n] 2006.189.07:36:28.46#ibcon#*before write, iclass 24, count 2 2006.189.07:36:28.46#ibcon#enter sib2, iclass 24, count 2 2006.189.07:36:28.46#ibcon#flushed, iclass 24, count 2 2006.189.07:36:28.46#ibcon#about to write, iclass 24, count 2 2006.189.07:36:28.46#ibcon#wrote, iclass 24, count 2 2006.189.07:36:28.46#ibcon#about to read 3, iclass 24, count 2 2006.189.07:36:28.49#ibcon#read 3, iclass 24, count 2 2006.189.07:36:28.49#ibcon#about to read 4, iclass 24, count 2 2006.189.07:36:28.49#ibcon#read 4, iclass 24, count 2 2006.189.07:36:28.49#ibcon#about to read 5, iclass 24, count 2 2006.189.07:36:28.49#ibcon#read 5, iclass 24, count 2 2006.189.07:36:28.49#ibcon#about to read 6, iclass 24, count 2 2006.189.07:36:28.49#ibcon#read 6, iclass 24, count 2 2006.189.07:36:28.49#ibcon#end of sib2, iclass 24, count 2 2006.189.07:36:28.49#ibcon#*after write, iclass 24, count 2 2006.189.07:36:28.49#ibcon#*before return 0, iclass 24, count 2 2006.189.07:36:28.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:28.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:28.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:36:28.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:28.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:28.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:28.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:28.61#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:36:28.61#ibcon#first serial, iclass 24, count 0 2006.189.07:36:28.61#ibcon#enter sib2, iclass 24, count 0 2006.189.07:36:28.61#ibcon#flushed, iclass 24, count 0 2006.189.07:36:28.61#ibcon#about to write, iclass 24, count 0 2006.189.07:36:28.61#ibcon#wrote, iclass 24, count 0 2006.189.07:36:28.61#ibcon#about to read 3, iclass 24, count 0 2006.189.07:36:28.63#ibcon#read 3, iclass 24, count 0 2006.189.07:36:28.63#ibcon#about to read 4, iclass 24, count 0 2006.189.07:36:28.63#ibcon#read 4, iclass 24, count 0 2006.189.07:36:28.63#ibcon#about to read 5, iclass 24, count 0 2006.189.07:36:28.63#ibcon#read 5, iclass 24, count 0 2006.189.07:36:28.63#ibcon#about to read 6, iclass 24, count 0 2006.189.07:36:28.63#ibcon#read 6, iclass 24, count 0 2006.189.07:36:28.63#ibcon#end of sib2, iclass 24, count 0 2006.189.07:36:28.63#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:36:28.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:36:28.63#ibcon#[25=USB\r\n] 2006.189.07:36:28.63#ibcon#*before write, iclass 24, count 0 2006.189.07:36:28.63#ibcon#enter sib2, iclass 24, count 0 2006.189.07:36:28.63#ibcon#flushed, iclass 24, count 0 2006.189.07:36:28.63#ibcon#about to write, iclass 24, count 0 2006.189.07:36:28.63#ibcon#wrote, iclass 24, count 0 2006.189.07:36:28.63#ibcon#about to read 3, iclass 24, count 0 2006.189.07:36:28.66#ibcon#read 3, iclass 24, count 0 2006.189.07:36:28.66#ibcon#about to read 4, iclass 24, count 0 2006.189.07:36:28.66#ibcon#read 4, iclass 24, count 0 2006.189.07:36:28.66#ibcon#about to read 5, iclass 24, count 0 2006.189.07:36:28.66#ibcon#read 5, iclass 24, count 0 2006.189.07:36:28.66#ibcon#about to read 6, iclass 24, count 0 2006.189.07:36:28.66#ibcon#read 6, iclass 24, count 0 2006.189.07:36:28.66#ibcon#end of sib2, iclass 24, count 0 2006.189.07:36:28.66#ibcon#*after write, iclass 24, count 0 2006.189.07:36:28.66#ibcon#*before return 0, iclass 24, count 0 2006.189.07:36:28.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:28.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:28.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:36:28.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:36:28.66$vc4f8/valo=3,672.99 2006.189.07:36:28.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.07:36:28.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.07:36:28.66#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:28.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:28.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:28.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:28.66#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:36:28.66#ibcon#first serial, iclass 26, count 0 2006.189.07:36:28.66#ibcon#enter sib2, iclass 26, count 0 2006.189.07:36:28.66#ibcon#flushed, iclass 26, count 0 2006.189.07:36:28.66#ibcon#about to write, iclass 26, count 0 2006.189.07:36:28.66#ibcon#wrote, iclass 26, count 0 2006.189.07:36:28.66#ibcon#about to read 3, iclass 26, count 0 2006.189.07:36:28.68#ibcon#read 3, iclass 26, count 0 2006.189.07:36:28.68#ibcon#about to read 4, iclass 26, count 0 2006.189.07:36:28.68#ibcon#read 4, iclass 26, count 0 2006.189.07:36:28.68#ibcon#about to read 5, iclass 26, count 0 2006.189.07:36:28.68#ibcon#read 5, iclass 26, count 0 2006.189.07:36:28.68#ibcon#about to read 6, iclass 26, count 0 2006.189.07:36:28.68#ibcon#read 6, iclass 26, count 0 2006.189.07:36:28.68#ibcon#end of sib2, iclass 26, count 0 2006.189.07:36:28.68#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:36:28.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:36:28.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:36:28.68#ibcon#*before write, iclass 26, count 0 2006.189.07:36:28.68#ibcon#enter sib2, iclass 26, count 0 2006.189.07:36:28.68#ibcon#flushed, iclass 26, count 0 2006.189.07:36:28.68#ibcon#about to write, iclass 26, count 0 2006.189.07:36:28.68#ibcon#wrote, iclass 26, count 0 2006.189.07:36:28.68#ibcon#about to read 3, iclass 26, count 0 2006.189.07:36:28.73#ibcon#read 3, iclass 26, count 0 2006.189.07:36:28.73#ibcon#about to read 4, iclass 26, count 0 2006.189.07:36:28.73#ibcon#read 4, iclass 26, count 0 2006.189.07:36:28.73#ibcon#about to read 5, iclass 26, count 0 2006.189.07:36:28.73#ibcon#read 5, iclass 26, count 0 2006.189.07:36:28.73#ibcon#about to read 6, iclass 26, count 0 2006.189.07:36:28.73#ibcon#read 6, iclass 26, count 0 2006.189.07:36:28.73#ibcon#end of sib2, iclass 26, count 0 2006.189.07:36:28.73#ibcon#*after write, iclass 26, count 0 2006.189.07:36:28.73#ibcon#*before return 0, iclass 26, count 0 2006.189.07:36:28.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:28.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:28.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:36:28.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:36:28.73$vc4f8/va=3,6 2006.189.07:36:28.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.07:36:28.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.07:36:28.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:28.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:28.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:28.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:28.77#ibcon#enter wrdev, iclass 28, count 2 2006.189.07:36:28.77#ibcon#first serial, iclass 28, count 2 2006.189.07:36:28.77#ibcon#enter sib2, iclass 28, count 2 2006.189.07:36:28.77#ibcon#flushed, iclass 28, count 2 2006.189.07:36:28.77#ibcon#about to write, iclass 28, count 2 2006.189.07:36:28.77#ibcon#wrote, iclass 28, count 2 2006.189.07:36:28.77#ibcon#about to read 3, iclass 28, count 2 2006.189.07:36:28.79#ibcon#read 3, iclass 28, count 2 2006.189.07:36:28.79#ibcon#about to read 4, iclass 28, count 2 2006.189.07:36:28.79#ibcon#read 4, iclass 28, count 2 2006.189.07:36:28.79#ibcon#about to read 5, iclass 28, count 2 2006.189.07:36:28.79#ibcon#read 5, iclass 28, count 2 2006.189.07:36:28.79#ibcon#about to read 6, iclass 28, count 2 2006.189.07:36:28.79#ibcon#read 6, iclass 28, count 2 2006.189.07:36:28.79#ibcon#end of sib2, iclass 28, count 2 2006.189.07:36:28.79#ibcon#*mode == 0, iclass 28, count 2 2006.189.07:36:28.79#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.07:36:28.79#ibcon#[25=AT03-06\r\n] 2006.189.07:36:28.79#ibcon#*before write, iclass 28, count 2 2006.189.07:36:28.79#ibcon#enter sib2, iclass 28, count 2 2006.189.07:36:28.79#ibcon#flushed, iclass 28, count 2 2006.189.07:36:28.79#ibcon#about to write, iclass 28, count 2 2006.189.07:36:28.79#ibcon#wrote, iclass 28, count 2 2006.189.07:36:28.79#ibcon#about to read 3, iclass 28, count 2 2006.189.07:36:28.82#ibcon#read 3, iclass 28, count 2 2006.189.07:36:28.82#ibcon#about to read 4, iclass 28, count 2 2006.189.07:36:28.82#ibcon#read 4, iclass 28, count 2 2006.189.07:36:28.82#ibcon#about to read 5, iclass 28, count 2 2006.189.07:36:28.82#ibcon#read 5, iclass 28, count 2 2006.189.07:36:28.82#ibcon#about to read 6, iclass 28, count 2 2006.189.07:36:28.82#ibcon#read 6, iclass 28, count 2 2006.189.07:36:28.82#ibcon#end of sib2, iclass 28, count 2 2006.189.07:36:28.82#ibcon#*after write, iclass 28, count 2 2006.189.07:36:28.82#ibcon#*before return 0, iclass 28, count 2 2006.189.07:36:28.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:28.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:28.82#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.07:36:28.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:28.82#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:28.94#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:28.94#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:28.94#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:36:28.94#ibcon#first serial, iclass 28, count 0 2006.189.07:36:28.94#ibcon#enter sib2, iclass 28, count 0 2006.189.07:36:28.94#ibcon#flushed, iclass 28, count 0 2006.189.07:36:28.94#ibcon#about to write, iclass 28, count 0 2006.189.07:36:28.94#ibcon#wrote, iclass 28, count 0 2006.189.07:36:28.94#ibcon#about to read 3, iclass 28, count 0 2006.189.07:36:28.96#ibcon#read 3, iclass 28, count 0 2006.189.07:36:28.96#ibcon#about to read 4, iclass 28, count 0 2006.189.07:36:28.96#ibcon#read 4, iclass 28, count 0 2006.189.07:36:28.96#ibcon#about to read 5, iclass 28, count 0 2006.189.07:36:28.96#ibcon#read 5, iclass 28, count 0 2006.189.07:36:28.96#ibcon#about to read 6, iclass 28, count 0 2006.189.07:36:28.96#ibcon#read 6, iclass 28, count 0 2006.189.07:36:28.96#ibcon#end of sib2, iclass 28, count 0 2006.189.07:36:28.96#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:36:28.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:36:28.96#ibcon#[25=USB\r\n] 2006.189.07:36:28.96#ibcon#*before write, iclass 28, count 0 2006.189.07:36:28.96#ibcon#enter sib2, iclass 28, count 0 2006.189.07:36:28.96#ibcon#flushed, iclass 28, count 0 2006.189.07:36:28.96#ibcon#about to write, iclass 28, count 0 2006.189.07:36:28.96#ibcon#wrote, iclass 28, count 0 2006.189.07:36:28.96#ibcon#about to read 3, iclass 28, count 0 2006.189.07:36:28.99#ibcon#read 3, iclass 28, count 0 2006.189.07:36:28.99#ibcon#about to read 4, iclass 28, count 0 2006.189.07:36:28.99#ibcon#read 4, iclass 28, count 0 2006.189.07:36:28.99#ibcon#about to read 5, iclass 28, count 0 2006.189.07:36:28.99#ibcon#read 5, iclass 28, count 0 2006.189.07:36:28.99#ibcon#about to read 6, iclass 28, count 0 2006.189.07:36:28.99#ibcon#read 6, iclass 28, count 0 2006.189.07:36:28.99#ibcon#end of sib2, iclass 28, count 0 2006.189.07:36:28.99#ibcon#*after write, iclass 28, count 0 2006.189.07:36:28.99#ibcon#*before return 0, iclass 28, count 0 2006.189.07:36:28.99#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:28.99#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:28.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:36:28.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:36:28.99$vc4f8/valo=4,832.99 2006.189.07:36:28.99#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.07:36:28.99#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.07:36:28.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:28.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:28.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:28.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:28.99#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:36:28.99#ibcon#first serial, iclass 30, count 0 2006.189.07:36:28.99#ibcon#enter sib2, iclass 30, count 0 2006.189.07:36:28.99#ibcon#flushed, iclass 30, count 0 2006.189.07:36:28.99#ibcon#about to write, iclass 30, count 0 2006.189.07:36:28.99#ibcon#wrote, iclass 30, count 0 2006.189.07:36:28.99#ibcon#about to read 3, iclass 30, count 0 2006.189.07:36:29.01#ibcon#read 3, iclass 30, count 0 2006.189.07:36:29.01#ibcon#about to read 4, iclass 30, count 0 2006.189.07:36:29.01#ibcon#read 4, iclass 30, count 0 2006.189.07:36:29.01#ibcon#about to read 5, iclass 30, count 0 2006.189.07:36:29.01#ibcon#read 5, iclass 30, count 0 2006.189.07:36:29.01#ibcon#about to read 6, iclass 30, count 0 2006.189.07:36:29.01#ibcon#read 6, iclass 30, count 0 2006.189.07:36:29.01#ibcon#end of sib2, iclass 30, count 0 2006.189.07:36:29.01#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:36:29.01#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:36:29.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:36:29.01#ibcon#*before write, iclass 30, count 0 2006.189.07:36:29.01#ibcon#enter sib2, iclass 30, count 0 2006.189.07:36:29.01#ibcon#flushed, iclass 30, count 0 2006.189.07:36:29.01#ibcon#about to write, iclass 30, count 0 2006.189.07:36:29.01#ibcon#wrote, iclass 30, count 0 2006.189.07:36:29.01#ibcon#about to read 3, iclass 30, count 0 2006.189.07:36:29.05#ibcon#read 3, iclass 30, count 0 2006.189.07:36:29.05#ibcon#about to read 4, iclass 30, count 0 2006.189.07:36:29.05#ibcon#read 4, iclass 30, count 0 2006.189.07:36:29.05#ibcon#about to read 5, iclass 30, count 0 2006.189.07:36:29.05#ibcon#read 5, iclass 30, count 0 2006.189.07:36:29.05#ibcon#about to read 6, iclass 30, count 0 2006.189.07:36:29.05#ibcon#read 6, iclass 30, count 0 2006.189.07:36:29.05#ibcon#end of sib2, iclass 30, count 0 2006.189.07:36:29.05#ibcon#*after write, iclass 30, count 0 2006.189.07:36:29.05#ibcon#*before return 0, iclass 30, count 0 2006.189.07:36:29.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:29.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:29.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:36:29.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:36:29.05$vc4f8/va=4,7 2006.189.07:36:29.05#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.07:36:29.05#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.07:36:29.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:29.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:29.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:29.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:29.11#ibcon#enter wrdev, iclass 32, count 2 2006.189.07:36:29.11#ibcon#first serial, iclass 32, count 2 2006.189.07:36:29.11#ibcon#enter sib2, iclass 32, count 2 2006.189.07:36:29.11#ibcon#flushed, iclass 32, count 2 2006.189.07:36:29.11#ibcon#about to write, iclass 32, count 2 2006.189.07:36:29.11#ibcon#wrote, iclass 32, count 2 2006.189.07:36:29.11#ibcon#about to read 3, iclass 32, count 2 2006.189.07:36:29.13#ibcon#read 3, iclass 32, count 2 2006.189.07:36:29.13#ibcon#about to read 4, iclass 32, count 2 2006.189.07:36:29.13#ibcon#read 4, iclass 32, count 2 2006.189.07:36:29.13#ibcon#about to read 5, iclass 32, count 2 2006.189.07:36:29.13#ibcon#read 5, iclass 32, count 2 2006.189.07:36:29.13#ibcon#about to read 6, iclass 32, count 2 2006.189.07:36:29.13#ibcon#read 6, iclass 32, count 2 2006.189.07:36:29.13#ibcon#end of sib2, iclass 32, count 2 2006.189.07:36:29.13#ibcon#*mode == 0, iclass 32, count 2 2006.189.07:36:29.13#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.07:36:29.13#ibcon#[25=AT04-07\r\n] 2006.189.07:36:29.13#ibcon#*before write, iclass 32, count 2 2006.189.07:36:29.13#ibcon#enter sib2, iclass 32, count 2 2006.189.07:36:29.13#ibcon#flushed, iclass 32, count 2 2006.189.07:36:29.13#ibcon#about to write, iclass 32, count 2 2006.189.07:36:29.13#ibcon#wrote, iclass 32, count 2 2006.189.07:36:29.13#ibcon#about to read 3, iclass 32, count 2 2006.189.07:36:29.16#ibcon#read 3, iclass 32, count 2 2006.189.07:36:29.16#ibcon#about to read 4, iclass 32, count 2 2006.189.07:36:29.16#ibcon#read 4, iclass 32, count 2 2006.189.07:36:29.16#ibcon#about to read 5, iclass 32, count 2 2006.189.07:36:29.16#ibcon#read 5, iclass 32, count 2 2006.189.07:36:29.16#ibcon#about to read 6, iclass 32, count 2 2006.189.07:36:29.16#ibcon#read 6, iclass 32, count 2 2006.189.07:36:29.16#ibcon#end of sib2, iclass 32, count 2 2006.189.07:36:29.16#ibcon#*after write, iclass 32, count 2 2006.189.07:36:29.16#ibcon#*before return 0, iclass 32, count 2 2006.189.07:36:29.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:29.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:29.16#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.07:36:29.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:29.16#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:29.28#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:29.28#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:29.28#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:36:29.28#ibcon#first serial, iclass 32, count 0 2006.189.07:36:29.28#ibcon#enter sib2, iclass 32, count 0 2006.189.07:36:29.28#ibcon#flushed, iclass 32, count 0 2006.189.07:36:29.28#ibcon#about to write, iclass 32, count 0 2006.189.07:36:29.28#ibcon#wrote, iclass 32, count 0 2006.189.07:36:29.28#ibcon#about to read 3, iclass 32, count 0 2006.189.07:36:29.30#ibcon#read 3, iclass 32, count 0 2006.189.07:36:29.30#ibcon#about to read 4, iclass 32, count 0 2006.189.07:36:29.30#ibcon#read 4, iclass 32, count 0 2006.189.07:36:29.30#ibcon#about to read 5, iclass 32, count 0 2006.189.07:36:29.30#ibcon#read 5, iclass 32, count 0 2006.189.07:36:29.30#ibcon#about to read 6, iclass 32, count 0 2006.189.07:36:29.30#ibcon#read 6, iclass 32, count 0 2006.189.07:36:29.30#ibcon#end of sib2, iclass 32, count 0 2006.189.07:36:29.30#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:36:29.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:36:29.30#ibcon#[25=USB\r\n] 2006.189.07:36:29.30#ibcon#*before write, iclass 32, count 0 2006.189.07:36:29.30#ibcon#enter sib2, iclass 32, count 0 2006.189.07:36:29.30#ibcon#flushed, iclass 32, count 0 2006.189.07:36:29.30#ibcon#about to write, iclass 32, count 0 2006.189.07:36:29.30#ibcon#wrote, iclass 32, count 0 2006.189.07:36:29.30#ibcon#about to read 3, iclass 32, count 0 2006.189.07:36:29.33#ibcon#read 3, iclass 32, count 0 2006.189.07:36:29.33#ibcon#about to read 4, iclass 32, count 0 2006.189.07:36:29.33#ibcon#read 4, iclass 32, count 0 2006.189.07:36:29.33#ibcon#about to read 5, iclass 32, count 0 2006.189.07:36:29.33#ibcon#read 5, iclass 32, count 0 2006.189.07:36:29.33#ibcon#about to read 6, iclass 32, count 0 2006.189.07:36:29.33#ibcon#read 6, iclass 32, count 0 2006.189.07:36:29.33#ibcon#end of sib2, iclass 32, count 0 2006.189.07:36:29.33#ibcon#*after write, iclass 32, count 0 2006.189.07:36:29.33#ibcon#*before return 0, iclass 32, count 0 2006.189.07:36:29.33#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:29.33#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:29.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:36:29.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:36:29.33$vc4f8/valo=5,652.99 2006.189.07:36:29.33#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.07:36:29.33#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.07:36:29.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:29.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:36:29.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:36:29.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:36:29.33#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:36:29.33#ibcon#first serial, iclass 34, count 0 2006.189.07:36:29.33#ibcon#enter sib2, iclass 34, count 0 2006.189.07:36:29.33#ibcon#flushed, iclass 34, count 0 2006.189.07:36:29.33#ibcon#about to write, iclass 34, count 0 2006.189.07:36:29.33#ibcon#wrote, iclass 34, count 0 2006.189.07:36:29.33#ibcon#about to read 3, iclass 34, count 0 2006.189.07:36:29.35#ibcon#read 3, iclass 34, count 0 2006.189.07:36:29.35#ibcon#about to read 4, iclass 34, count 0 2006.189.07:36:29.35#ibcon#read 4, iclass 34, count 0 2006.189.07:36:29.35#ibcon#about to read 5, iclass 34, count 0 2006.189.07:36:29.35#ibcon#read 5, iclass 34, count 0 2006.189.07:36:29.35#ibcon#about to read 6, iclass 34, count 0 2006.189.07:36:29.35#ibcon#read 6, iclass 34, count 0 2006.189.07:36:29.35#ibcon#end of sib2, iclass 34, count 0 2006.189.07:36:29.35#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:36:29.35#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:36:29.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:36:29.35#ibcon#*before write, iclass 34, count 0 2006.189.07:36:29.35#ibcon#enter sib2, iclass 34, count 0 2006.189.07:36:29.35#ibcon#flushed, iclass 34, count 0 2006.189.07:36:29.35#ibcon#about to write, iclass 34, count 0 2006.189.07:36:29.35#ibcon#wrote, iclass 34, count 0 2006.189.07:36:29.35#ibcon#about to read 3, iclass 34, count 0 2006.189.07:36:29.39#ibcon#read 3, iclass 34, count 0 2006.189.07:36:29.39#ibcon#about to read 4, iclass 34, count 0 2006.189.07:36:29.39#ibcon#read 4, iclass 34, count 0 2006.189.07:36:29.39#ibcon#about to read 5, iclass 34, count 0 2006.189.07:36:29.39#ibcon#read 5, iclass 34, count 0 2006.189.07:36:29.39#ibcon#about to read 6, iclass 34, count 0 2006.189.07:36:29.39#ibcon#read 6, iclass 34, count 0 2006.189.07:36:29.39#ibcon#end of sib2, iclass 34, count 0 2006.189.07:36:29.39#ibcon#*after write, iclass 34, count 0 2006.189.07:36:29.39#ibcon#*before return 0, iclass 34, count 0 2006.189.07:36:29.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:36:29.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:36:29.39#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:36:29.39#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:36:29.39$vc4f8/va=5,7 2006.189.07:36:29.39#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.07:36:29.39#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.07:36:29.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:29.39#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:36:29.45#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:36:29.45#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:36:29.45#ibcon#enter wrdev, iclass 36, count 2 2006.189.07:36:29.45#ibcon#first serial, iclass 36, count 2 2006.189.07:36:29.45#ibcon#enter sib2, iclass 36, count 2 2006.189.07:36:29.45#ibcon#flushed, iclass 36, count 2 2006.189.07:36:29.45#ibcon#about to write, iclass 36, count 2 2006.189.07:36:29.45#ibcon#wrote, iclass 36, count 2 2006.189.07:36:29.45#ibcon#about to read 3, iclass 36, count 2 2006.189.07:36:29.47#ibcon#read 3, iclass 36, count 2 2006.189.07:36:29.47#ibcon#about to read 4, iclass 36, count 2 2006.189.07:36:29.47#ibcon#read 4, iclass 36, count 2 2006.189.07:36:29.47#ibcon#about to read 5, iclass 36, count 2 2006.189.07:36:29.47#ibcon#read 5, iclass 36, count 2 2006.189.07:36:29.47#ibcon#about to read 6, iclass 36, count 2 2006.189.07:36:29.47#ibcon#read 6, iclass 36, count 2 2006.189.07:36:29.47#ibcon#end of sib2, iclass 36, count 2 2006.189.07:36:29.47#ibcon#*mode == 0, iclass 36, count 2 2006.189.07:36:29.47#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.07:36:29.47#ibcon#[25=AT05-07\r\n] 2006.189.07:36:29.47#ibcon#*before write, iclass 36, count 2 2006.189.07:36:29.47#ibcon#enter sib2, iclass 36, count 2 2006.189.07:36:29.47#ibcon#flushed, iclass 36, count 2 2006.189.07:36:29.47#ibcon#about to write, iclass 36, count 2 2006.189.07:36:29.47#ibcon#wrote, iclass 36, count 2 2006.189.07:36:29.47#ibcon#about to read 3, iclass 36, count 2 2006.189.07:36:29.50#ibcon#read 3, iclass 36, count 2 2006.189.07:36:29.50#ibcon#about to read 4, iclass 36, count 2 2006.189.07:36:29.50#ibcon#read 4, iclass 36, count 2 2006.189.07:36:29.50#ibcon#about to read 5, iclass 36, count 2 2006.189.07:36:29.50#ibcon#read 5, iclass 36, count 2 2006.189.07:36:29.50#ibcon#about to read 6, iclass 36, count 2 2006.189.07:36:29.50#ibcon#read 6, iclass 36, count 2 2006.189.07:36:29.50#ibcon#end of sib2, iclass 36, count 2 2006.189.07:36:29.50#ibcon#*after write, iclass 36, count 2 2006.189.07:36:29.50#ibcon#*before return 0, iclass 36, count 2 2006.189.07:36:29.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:36:29.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:36:29.50#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.07:36:29.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:29.50#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:36:29.62#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:36:29.62#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:36:29.62#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:36:29.62#ibcon#first serial, iclass 36, count 0 2006.189.07:36:29.62#ibcon#enter sib2, iclass 36, count 0 2006.189.07:36:29.62#ibcon#flushed, iclass 36, count 0 2006.189.07:36:29.62#ibcon#about to write, iclass 36, count 0 2006.189.07:36:29.62#ibcon#wrote, iclass 36, count 0 2006.189.07:36:29.62#ibcon#about to read 3, iclass 36, count 0 2006.189.07:36:29.64#ibcon#read 3, iclass 36, count 0 2006.189.07:36:29.64#ibcon#about to read 4, iclass 36, count 0 2006.189.07:36:29.64#ibcon#read 4, iclass 36, count 0 2006.189.07:36:29.64#ibcon#about to read 5, iclass 36, count 0 2006.189.07:36:29.64#ibcon#read 5, iclass 36, count 0 2006.189.07:36:29.64#ibcon#about to read 6, iclass 36, count 0 2006.189.07:36:29.64#ibcon#read 6, iclass 36, count 0 2006.189.07:36:29.64#ibcon#end of sib2, iclass 36, count 0 2006.189.07:36:29.64#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:36:29.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:36:29.64#ibcon#[25=USB\r\n] 2006.189.07:36:29.64#ibcon#*before write, iclass 36, count 0 2006.189.07:36:29.64#ibcon#enter sib2, iclass 36, count 0 2006.189.07:36:29.64#ibcon#flushed, iclass 36, count 0 2006.189.07:36:29.64#ibcon#about to write, iclass 36, count 0 2006.189.07:36:29.64#ibcon#wrote, iclass 36, count 0 2006.189.07:36:29.64#ibcon#about to read 3, iclass 36, count 0 2006.189.07:36:29.67#ibcon#read 3, iclass 36, count 0 2006.189.07:36:29.67#ibcon#about to read 4, iclass 36, count 0 2006.189.07:36:29.67#ibcon#read 4, iclass 36, count 0 2006.189.07:36:29.67#ibcon#about to read 5, iclass 36, count 0 2006.189.07:36:29.67#ibcon#read 5, iclass 36, count 0 2006.189.07:36:29.67#ibcon#about to read 6, iclass 36, count 0 2006.189.07:36:29.67#ibcon#read 6, iclass 36, count 0 2006.189.07:36:29.67#ibcon#end of sib2, iclass 36, count 0 2006.189.07:36:29.67#ibcon#*after write, iclass 36, count 0 2006.189.07:36:29.67#ibcon#*before return 0, iclass 36, count 0 2006.189.07:36:29.67#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:36:29.67#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:36:29.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:36:29.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:36:29.67$vc4f8/valo=6,772.99 2006.189.07:36:29.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.07:36:29.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.07:36:29.67#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:29.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:36:29.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:36:29.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:36:29.67#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:36:29.67#ibcon#first serial, iclass 38, count 0 2006.189.07:36:29.67#ibcon#enter sib2, iclass 38, count 0 2006.189.07:36:29.67#ibcon#flushed, iclass 38, count 0 2006.189.07:36:29.67#ibcon#about to write, iclass 38, count 0 2006.189.07:36:29.67#ibcon#wrote, iclass 38, count 0 2006.189.07:36:29.67#ibcon#about to read 3, iclass 38, count 0 2006.189.07:36:29.69#ibcon#read 3, iclass 38, count 0 2006.189.07:36:29.69#ibcon#about to read 4, iclass 38, count 0 2006.189.07:36:29.69#ibcon#read 4, iclass 38, count 0 2006.189.07:36:29.69#ibcon#about to read 5, iclass 38, count 0 2006.189.07:36:29.69#ibcon#read 5, iclass 38, count 0 2006.189.07:36:29.69#ibcon#about to read 6, iclass 38, count 0 2006.189.07:36:29.69#ibcon#read 6, iclass 38, count 0 2006.189.07:36:29.69#ibcon#end of sib2, iclass 38, count 0 2006.189.07:36:29.69#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:36:29.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:36:29.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:36:29.69#ibcon#*before write, iclass 38, count 0 2006.189.07:36:29.69#ibcon#enter sib2, iclass 38, count 0 2006.189.07:36:29.69#ibcon#flushed, iclass 38, count 0 2006.189.07:36:29.69#ibcon#about to write, iclass 38, count 0 2006.189.07:36:29.69#ibcon#wrote, iclass 38, count 0 2006.189.07:36:29.69#ibcon#about to read 3, iclass 38, count 0 2006.189.07:36:29.73#ibcon#read 3, iclass 38, count 0 2006.189.07:36:29.73#ibcon#about to read 4, iclass 38, count 0 2006.189.07:36:29.73#ibcon#read 4, iclass 38, count 0 2006.189.07:36:29.73#ibcon#about to read 5, iclass 38, count 0 2006.189.07:36:29.73#ibcon#read 5, iclass 38, count 0 2006.189.07:36:29.73#ibcon#about to read 6, iclass 38, count 0 2006.189.07:36:29.73#ibcon#read 6, iclass 38, count 0 2006.189.07:36:29.73#ibcon#end of sib2, iclass 38, count 0 2006.189.07:36:29.73#ibcon#*after write, iclass 38, count 0 2006.189.07:36:29.73#ibcon#*before return 0, iclass 38, count 0 2006.189.07:36:29.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:36:29.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:36:29.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:36:29.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:36:29.73$vc4f8/va=6,6 2006.189.07:36:29.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.07:36:29.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.07:36:29.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:29.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:29.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:29.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:29.79#ibcon#enter wrdev, iclass 40, count 2 2006.189.07:36:29.79#ibcon#first serial, iclass 40, count 2 2006.189.07:36:29.79#ibcon#enter sib2, iclass 40, count 2 2006.189.07:36:29.79#ibcon#flushed, iclass 40, count 2 2006.189.07:36:29.79#ibcon#about to write, iclass 40, count 2 2006.189.07:36:29.79#ibcon#wrote, iclass 40, count 2 2006.189.07:36:29.79#ibcon#about to read 3, iclass 40, count 2 2006.189.07:36:29.81#ibcon#read 3, iclass 40, count 2 2006.189.07:36:29.81#ibcon#about to read 4, iclass 40, count 2 2006.189.07:36:29.81#ibcon#read 4, iclass 40, count 2 2006.189.07:36:29.81#ibcon#about to read 5, iclass 40, count 2 2006.189.07:36:29.81#ibcon#read 5, iclass 40, count 2 2006.189.07:36:29.81#ibcon#about to read 6, iclass 40, count 2 2006.189.07:36:29.81#ibcon#read 6, iclass 40, count 2 2006.189.07:36:29.81#ibcon#end of sib2, iclass 40, count 2 2006.189.07:36:29.81#ibcon#*mode == 0, iclass 40, count 2 2006.189.07:36:29.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.07:36:29.81#ibcon#[25=AT06-06\r\n] 2006.189.07:36:29.81#ibcon#*before write, iclass 40, count 2 2006.189.07:36:29.81#ibcon#enter sib2, iclass 40, count 2 2006.189.07:36:29.81#ibcon#flushed, iclass 40, count 2 2006.189.07:36:29.81#ibcon#about to write, iclass 40, count 2 2006.189.07:36:29.81#ibcon#wrote, iclass 40, count 2 2006.189.07:36:29.81#ibcon#about to read 3, iclass 40, count 2 2006.189.07:36:29.84#ibcon#read 3, iclass 40, count 2 2006.189.07:36:29.84#ibcon#about to read 4, iclass 40, count 2 2006.189.07:36:29.84#ibcon#read 4, iclass 40, count 2 2006.189.07:36:29.84#ibcon#about to read 5, iclass 40, count 2 2006.189.07:36:29.84#ibcon#read 5, iclass 40, count 2 2006.189.07:36:29.84#ibcon#about to read 6, iclass 40, count 2 2006.189.07:36:29.84#ibcon#read 6, iclass 40, count 2 2006.189.07:36:29.84#ibcon#end of sib2, iclass 40, count 2 2006.189.07:36:29.84#ibcon#*after write, iclass 40, count 2 2006.189.07:36:29.84#ibcon#*before return 0, iclass 40, count 2 2006.189.07:36:29.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:29.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:29.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.07:36:29.84#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:29.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:29.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:29.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:29.96#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:36:29.96#ibcon#first serial, iclass 40, count 0 2006.189.07:36:29.96#ibcon#enter sib2, iclass 40, count 0 2006.189.07:36:29.96#ibcon#flushed, iclass 40, count 0 2006.189.07:36:29.96#ibcon#about to write, iclass 40, count 0 2006.189.07:36:29.96#ibcon#wrote, iclass 40, count 0 2006.189.07:36:29.96#ibcon#about to read 3, iclass 40, count 0 2006.189.07:36:29.98#ibcon#read 3, iclass 40, count 0 2006.189.07:36:29.98#ibcon#about to read 4, iclass 40, count 0 2006.189.07:36:29.98#ibcon#read 4, iclass 40, count 0 2006.189.07:36:29.98#ibcon#about to read 5, iclass 40, count 0 2006.189.07:36:29.98#ibcon#read 5, iclass 40, count 0 2006.189.07:36:29.98#ibcon#about to read 6, iclass 40, count 0 2006.189.07:36:29.98#ibcon#read 6, iclass 40, count 0 2006.189.07:36:29.98#ibcon#end of sib2, iclass 40, count 0 2006.189.07:36:29.98#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:36:29.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:36:29.98#ibcon#[25=USB\r\n] 2006.189.07:36:29.98#ibcon#*before write, iclass 40, count 0 2006.189.07:36:29.98#ibcon#enter sib2, iclass 40, count 0 2006.189.07:36:29.98#ibcon#flushed, iclass 40, count 0 2006.189.07:36:29.98#ibcon#about to write, iclass 40, count 0 2006.189.07:36:29.98#ibcon#wrote, iclass 40, count 0 2006.189.07:36:29.98#ibcon#about to read 3, iclass 40, count 0 2006.189.07:36:30.01#ibcon#read 3, iclass 40, count 0 2006.189.07:36:30.01#ibcon#about to read 4, iclass 40, count 0 2006.189.07:36:30.01#ibcon#read 4, iclass 40, count 0 2006.189.07:36:30.01#ibcon#about to read 5, iclass 40, count 0 2006.189.07:36:30.01#ibcon#read 5, iclass 40, count 0 2006.189.07:36:30.01#ibcon#about to read 6, iclass 40, count 0 2006.189.07:36:30.01#ibcon#read 6, iclass 40, count 0 2006.189.07:36:30.01#ibcon#end of sib2, iclass 40, count 0 2006.189.07:36:30.01#ibcon#*after write, iclass 40, count 0 2006.189.07:36:30.01#ibcon#*before return 0, iclass 40, count 0 2006.189.07:36:30.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:30.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:30.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:36:30.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:36:30.01$vc4f8/valo=7,832.99 2006.189.07:36:30.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:36:30.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:36:30.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:30.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:30.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:30.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:30.01#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:36:30.01#ibcon#first serial, iclass 4, count 0 2006.189.07:36:30.01#ibcon#enter sib2, iclass 4, count 0 2006.189.07:36:30.01#ibcon#flushed, iclass 4, count 0 2006.189.07:36:30.01#ibcon#about to write, iclass 4, count 0 2006.189.07:36:30.01#ibcon#wrote, iclass 4, count 0 2006.189.07:36:30.01#ibcon#about to read 3, iclass 4, count 0 2006.189.07:36:30.03#ibcon#read 3, iclass 4, count 0 2006.189.07:36:30.03#ibcon#about to read 4, iclass 4, count 0 2006.189.07:36:30.03#ibcon#read 4, iclass 4, count 0 2006.189.07:36:30.03#ibcon#about to read 5, iclass 4, count 0 2006.189.07:36:30.03#ibcon#read 5, iclass 4, count 0 2006.189.07:36:30.03#ibcon#about to read 6, iclass 4, count 0 2006.189.07:36:30.03#ibcon#read 6, iclass 4, count 0 2006.189.07:36:30.03#ibcon#end of sib2, iclass 4, count 0 2006.189.07:36:30.03#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:36:30.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:36:30.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:36:30.03#ibcon#*before write, iclass 4, count 0 2006.189.07:36:30.03#ibcon#enter sib2, iclass 4, count 0 2006.189.07:36:30.03#ibcon#flushed, iclass 4, count 0 2006.189.07:36:30.03#ibcon#about to write, iclass 4, count 0 2006.189.07:36:30.03#ibcon#wrote, iclass 4, count 0 2006.189.07:36:30.03#ibcon#about to read 3, iclass 4, count 0 2006.189.07:36:30.07#ibcon#read 3, iclass 4, count 0 2006.189.07:36:30.07#ibcon#about to read 4, iclass 4, count 0 2006.189.07:36:30.07#ibcon#read 4, iclass 4, count 0 2006.189.07:36:30.07#ibcon#about to read 5, iclass 4, count 0 2006.189.07:36:30.07#ibcon#read 5, iclass 4, count 0 2006.189.07:36:30.07#ibcon#about to read 6, iclass 4, count 0 2006.189.07:36:30.07#ibcon#read 6, iclass 4, count 0 2006.189.07:36:30.07#ibcon#end of sib2, iclass 4, count 0 2006.189.07:36:30.07#ibcon#*after write, iclass 4, count 0 2006.189.07:36:30.07#ibcon#*before return 0, iclass 4, count 0 2006.189.07:36:30.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:30.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:30.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:36:30.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:36:30.07$vc4f8/va=7,6 2006.189.07:36:30.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.07:36:30.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.07:36:30.07#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:30.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:36:30.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:36:30.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:36:30.13#ibcon#enter wrdev, iclass 6, count 2 2006.189.07:36:30.13#ibcon#first serial, iclass 6, count 2 2006.189.07:36:30.13#ibcon#enter sib2, iclass 6, count 2 2006.189.07:36:30.13#ibcon#flushed, iclass 6, count 2 2006.189.07:36:30.13#ibcon#about to write, iclass 6, count 2 2006.189.07:36:30.13#ibcon#wrote, iclass 6, count 2 2006.189.07:36:30.13#ibcon#about to read 3, iclass 6, count 2 2006.189.07:36:30.15#ibcon#read 3, iclass 6, count 2 2006.189.07:36:30.15#ibcon#about to read 4, iclass 6, count 2 2006.189.07:36:30.15#ibcon#read 4, iclass 6, count 2 2006.189.07:36:30.15#ibcon#about to read 5, iclass 6, count 2 2006.189.07:36:30.15#ibcon#read 5, iclass 6, count 2 2006.189.07:36:30.15#ibcon#about to read 6, iclass 6, count 2 2006.189.07:36:30.15#ibcon#read 6, iclass 6, count 2 2006.189.07:36:30.15#ibcon#end of sib2, iclass 6, count 2 2006.189.07:36:30.15#ibcon#*mode == 0, iclass 6, count 2 2006.189.07:36:30.15#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.07:36:30.15#ibcon#[25=AT07-06\r\n] 2006.189.07:36:30.15#ibcon#*before write, iclass 6, count 2 2006.189.07:36:30.15#ibcon#enter sib2, iclass 6, count 2 2006.189.07:36:30.15#ibcon#flushed, iclass 6, count 2 2006.189.07:36:30.15#ibcon#about to write, iclass 6, count 2 2006.189.07:36:30.15#ibcon#wrote, iclass 6, count 2 2006.189.07:36:30.15#ibcon#about to read 3, iclass 6, count 2 2006.189.07:36:30.18#ibcon#read 3, iclass 6, count 2 2006.189.07:36:30.18#ibcon#about to read 4, iclass 6, count 2 2006.189.07:36:30.18#ibcon#read 4, iclass 6, count 2 2006.189.07:36:30.18#ibcon#about to read 5, iclass 6, count 2 2006.189.07:36:30.18#ibcon#read 5, iclass 6, count 2 2006.189.07:36:30.18#ibcon#about to read 6, iclass 6, count 2 2006.189.07:36:30.18#ibcon#read 6, iclass 6, count 2 2006.189.07:36:30.18#ibcon#end of sib2, iclass 6, count 2 2006.189.07:36:30.18#ibcon#*after write, iclass 6, count 2 2006.189.07:36:30.18#ibcon#*before return 0, iclass 6, count 2 2006.189.07:36:30.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:36:30.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:36:30.18#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.07:36:30.18#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:30.18#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:36:30.30#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:36:30.30#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:36:30.30#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:36:30.30#ibcon#first serial, iclass 6, count 0 2006.189.07:36:30.30#ibcon#enter sib2, iclass 6, count 0 2006.189.07:36:30.30#ibcon#flushed, iclass 6, count 0 2006.189.07:36:30.30#ibcon#about to write, iclass 6, count 0 2006.189.07:36:30.30#ibcon#wrote, iclass 6, count 0 2006.189.07:36:30.30#ibcon#about to read 3, iclass 6, count 0 2006.189.07:36:30.32#ibcon#read 3, iclass 6, count 0 2006.189.07:36:30.32#ibcon#about to read 4, iclass 6, count 0 2006.189.07:36:30.32#ibcon#read 4, iclass 6, count 0 2006.189.07:36:30.32#ibcon#about to read 5, iclass 6, count 0 2006.189.07:36:30.32#ibcon#read 5, iclass 6, count 0 2006.189.07:36:30.32#ibcon#about to read 6, iclass 6, count 0 2006.189.07:36:30.32#ibcon#read 6, iclass 6, count 0 2006.189.07:36:30.32#ibcon#end of sib2, iclass 6, count 0 2006.189.07:36:30.32#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:36:30.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:36:30.32#ibcon#[25=USB\r\n] 2006.189.07:36:30.32#ibcon#*before write, iclass 6, count 0 2006.189.07:36:30.32#ibcon#enter sib2, iclass 6, count 0 2006.189.07:36:30.32#ibcon#flushed, iclass 6, count 0 2006.189.07:36:30.32#ibcon#about to write, iclass 6, count 0 2006.189.07:36:30.32#ibcon#wrote, iclass 6, count 0 2006.189.07:36:30.32#ibcon#about to read 3, iclass 6, count 0 2006.189.07:36:30.35#ibcon#read 3, iclass 6, count 0 2006.189.07:36:30.35#ibcon#about to read 4, iclass 6, count 0 2006.189.07:36:30.35#ibcon#read 4, iclass 6, count 0 2006.189.07:36:30.35#ibcon#about to read 5, iclass 6, count 0 2006.189.07:36:30.35#ibcon#read 5, iclass 6, count 0 2006.189.07:36:30.35#ibcon#about to read 6, iclass 6, count 0 2006.189.07:36:30.35#ibcon#read 6, iclass 6, count 0 2006.189.07:36:30.35#ibcon#end of sib2, iclass 6, count 0 2006.189.07:36:30.35#ibcon#*after write, iclass 6, count 0 2006.189.07:36:30.35#ibcon#*before return 0, iclass 6, count 0 2006.189.07:36:30.35#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:36:30.35#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:36:30.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:36:30.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:36:30.35$vc4f8/valo=8,852.99 2006.189.07:36:30.35#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.07:36:30.35#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.07:36:30.35#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:30.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:36:30.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:36:30.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:36:30.35#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:36:30.35#ibcon#first serial, iclass 10, count 0 2006.189.07:36:30.35#ibcon#enter sib2, iclass 10, count 0 2006.189.07:36:30.35#ibcon#flushed, iclass 10, count 0 2006.189.07:36:30.35#ibcon#about to write, iclass 10, count 0 2006.189.07:36:30.35#ibcon#wrote, iclass 10, count 0 2006.189.07:36:30.35#ibcon#about to read 3, iclass 10, count 0 2006.189.07:36:30.37#ibcon#read 3, iclass 10, count 0 2006.189.07:36:30.37#ibcon#about to read 4, iclass 10, count 0 2006.189.07:36:30.37#ibcon#read 4, iclass 10, count 0 2006.189.07:36:30.37#ibcon#about to read 5, iclass 10, count 0 2006.189.07:36:30.37#ibcon#read 5, iclass 10, count 0 2006.189.07:36:30.37#ibcon#about to read 6, iclass 10, count 0 2006.189.07:36:30.37#ibcon#read 6, iclass 10, count 0 2006.189.07:36:30.37#ibcon#end of sib2, iclass 10, count 0 2006.189.07:36:30.37#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:36:30.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:36:30.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:36:30.37#ibcon#*before write, iclass 10, count 0 2006.189.07:36:30.37#ibcon#enter sib2, iclass 10, count 0 2006.189.07:36:30.37#ibcon#flushed, iclass 10, count 0 2006.189.07:36:30.37#ibcon#about to write, iclass 10, count 0 2006.189.07:36:30.37#ibcon#wrote, iclass 10, count 0 2006.189.07:36:30.37#ibcon#about to read 3, iclass 10, count 0 2006.189.07:36:30.41#ibcon#read 3, iclass 10, count 0 2006.189.07:36:30.41#ibcon#about to read 4, iclass 10, count 0 2006.189.07:36:30.41#ibcon#read 4, iclass 10, count 0 2006.189.07:36:30.41#ibcon#about to read 5, iclass 10, count 0 2006.189.07:36:30.41#ibcon#read 5, iclass 10, count 0 2006.189.07:36:30.41#ibcon#about to read 6, iclass 10, count 0 2006.189.07:36:30.41#ibcon#read 6, iclass 10, count 0 2006.189.07:36:30.41#ibcon#end of sib2, iclass 10, count 0 2006.189.07:36:30.41#ibcon#*after write, iclass 10, count 0 2006.189.07:36:30.41#ibcon#*before return 0, iclass 10, count 0 2006.189.07:36:30.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:36:30.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:36:30.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:36:30.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:36:30.41$vc4f8/va=8,6 2006.189.07:36:30.41#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.07:36:30.41#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.07:36:30.41#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:30.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:36:30.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:36:30.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:36:30.47#ibcon#enter wrdev, iclass 12, count 2 2006.189.07:36:30.47#ibcon#first serial, iclass 12, count 2 2006.189.07:36:30.47#ibcon#enter sib2, iclass 12, count 2 2006.189.07:36:30.47#ibcon#flushed, iclass 12, count 2 2006.189.07:36:30.47#ibcon#about to write, iclass 12, count 2 2006.189.07:36:30.47#ibcon#wrote, iclass 12, count 2 2006.189.07:36:30.47#ibcon#about to read 3, iclass 12, count 2 2006.189.07:36:30.49#ibcon#read 3, iclass 12, count 2 2006.189.07:36:30.49#ibcon#about to read 4, iclass 12, count 2 2006.189.07:36:30.49#ibcon#read 4, iclass 12, count 2 2006.189.07:36:30.49#ibcon#about to read 5, iclass 12, count 2 2006.189.07:36:30.49#ibcon#read 5, iclass 12, count 2 2006.189.07:36:30.49#ibcon#about to read 6, iclass 12, count 2 2006.189.07:36:30.49#ibcon#read 6, iclass 12, count 2 2006.189.07:36:30.49#ibcon#end of sib2, iclass 12, count 2 2006.189.07:36:30.49#ibcon#*mode == 0, iclass 12, count 2 2006.189.07:36:30.49#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.07:36:30.49#ibcon#[25=AT08-06\r\n] 2006.189.07:36:30.49#ibcon#*before write, iclass 12, count 2 2006.189.07:36:30.49#ibcon#enter sib2, iclass 12, count 2 2006.189.07:36:30.49#ibcon#flushed, iclass 12, count 2 2006.189.07:36:30.49#ibcon#about to write, iclass 12, count 2 2006.189.07:36:30.49#ibcon#wrote, iclass 12, count 2 2006.189.07:36:30.49#ibcon#about to read 3, iclass 12, count 2 2006.189.07:36:30.52#ibcon#read 3, iclass 12, count 2 2006.189.07:36:30.52#ibcon#about to read 4, iclass 12, count 2 2006.189.07:36:30.52#ibcon#read 4, iclass 12, count 2 2006.189.07:36:30.52#ibcon#about to read 5, iclass 12, count 2 2006.189.07:36:30.52#ibcon#read 5, iclass 12, count 2 2006.189.07:36:30.52#ibcon#about to read 6, iclass 12, count 2 2006.189.07:36:30.52#ibcon#read 6, iclass 12, count 2 2006.189.07:36:30.52#ibcon#end of sib2, iclass 12, count 2 2006.189.07:36:30.52#ibcon#*after write, iclass 12, count 2 2006.189.07:36:30.52#ibcon#*before return 0, iclass 12, count 2 2006.189.07:36:30.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:36:30.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:36:30.52#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.07:36:30.52#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:30.52#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:36:30.64#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:36:30.64#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:36:30.64#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:36:30.64#ibcon#first serial, iclass 12, count 0 2006.189.07:36:30.64#ibcon#enter sib2, iclass 12, count 0 2006.189.07:36:30.64#ibcon#flushed, iclass 12, count 0 2006.189.07:36:30.64#ibcon#about to write, iclass 12, count 0 2006.189.07:36:30.64#ibcon#wrote, iclass 12, count 0 2006.189.07:36:30.64#ibcon#about to read 3, iclass 12, count 0 2006.189.07:36:30.66#ibcon#read 3, iclass 12, count 0 2006.189.07:36:30.66#ibcon#about to read 4, iclass 12, count 0 2006.189.07:36:30.66#ibcon#read 4, iclass 12, count 0 2006.189.07:36:30.66#ibcon#about to read 5, iclass 12, count 0 2006.189.07:36:30.66#ibcon#read 5, iclass 12, count 0 2006.189.07:36:30.66#ibcon#about to read 6, iclass 12, count 0 2006.189.07:36:30.66#ibcon#read 6, iclass 12, count 0 2006.189.07:36:30.66#ibcon#end of sib2, iclass 12, count 0 2006.189.07:36:30.66#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:36:30.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:36:30.66#ibcon#[25=USB\r\n] 2006.189.07:36:30.66#ibcon#*before write, iclass 12, count 0 2006.189.07:36:30.66#ibcon#enter sib2, iclass 12, count 0 2006.189.07:36:30.66#ibcon#flushed, iclass 12, count 0 2006.189.07:36:30.66#ibcon#about to write, iclass 12, count 0 2006.189.07:36:30.66#ibcon#wrote, iclass 12, count 0 2006.189.07:36:30.66#ibcon#about to read 3, iclass 12, count 0 2006.189.07:36:30.69#ibcon#read 3, iclass 12, count 0 2006.189.07:36:30.69#ibcon#about to read 4, iclass 12, count 0 2006.189.07:36:30.69#ibcon#read 4, iclass 12, count 0 2006.189.07:36:30.69#ibcon#about to read 5, iclass 12, count 0 2006.189.07:36:30.69#ibcon#read 5, iclass 12, count 0 2006.189.07:36:30.69#ibcon#about to read 6, iclass 12, count 0 2006.189.07:36:30.69#ibcon#read 6, iclass 12, count 0 2006.189.07:36:30.69#ibcon#end of sib2, iclass 12, count 0 2006.189.07:36:30.69#ibcon#*after write, iclass 12, count 0 2006.189.07:36:30.69#ibcon#*before return 0, iclass 12, count 0 2006.189.07:36:30.69#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:36:30.69#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:36:30.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:36:30.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:36:30.69$vc4f8/vblo=1,632.99 2006.189.07:36:30.69#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.07:36:30.69#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.07:36:30.69#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:30.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:36:30.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:36:30.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:36:30.69#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:36:30.69#ibcon#first serial, iclass 14, count 0 2006.189.07:36:30.69#ibcon#enter sib2, iclass 14, count 0 2006.189.07:36:30.69#ibcon#flushed, iclass 14, count 0 2006.189.07:36:30.69#ibcon#about to write, iclass 14, count 0 2006.189.07:36:30.69#ibcon#wrote, iclass 14, count 0 2006.189.07:36:30.69#ibcon#about to read 3, iclass 14, count 0 2006.189.07:36:30.71#ibcon#read 3, iclass 14, count 0 2006.189.07:36:30.71#ibcon#about to read 4, iclass 14, count 0 2006.189.07:36:30.71#ibcon#read 4, iclass 14, count 0 2006.189.07:36:30.71#ibcon#about to read 5, iclass 14, count 0 2006.189.07:36:30.71#ibcon#read 5, iclass 14, count 0 2006.189.07:36:30.71#ibcon#about to read 6, iclass 14, count 0 2006.189.07:36:30.71#ibcon#read 6, iclass 14, count 0 2006.189.07:36:30.71#ibcon#end of sib2, iclass 14, count 0 2006.189.07:36:30.71#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:36:30.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:36:30.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:36:30.71#ibcon#*before write, iclass 14, count 0 2006.189.07:36:30.71#ibcon#enter sib2, iclass 14, count 0 2006.189.07:36:30.71#ibcon#flushed, iclass 14, count 0 2006.189.07:36:30.71#ibcon#about to write, iclass 14, count 0 2006.189.07:36:30.71#ibcon#wrote, iclass 14, count 0 2006.189.07:36:30.71#ibcon#about to read 3, iclass 14, count 0 2006.189.07:36:30.75#ibcon#read 3, iclass 14, count 0 2006.189.07:36:30.75#ibcon#about to read 4, iclass 14, count 0 2006.189.07:36:30.75#ibcon#read 4, iclass 14, count 0 2006.189.07:36:30.75#ibcon#about to read 5, iclass 14, count 0 2006.189.07:36:30.75#ibcon#read 5, iclass 14, count 0 2006.189.07:36:30.75#ibcon#about to read 6, iclass 14, count 0 2006.189.07:36:30.75#ibcon#read 6, iclass 14, count 0 2006.189.07:36:30.75#ibcon#end of sib2, iclass 14, count 0 2006.189.07:36:30.75#ibcon#*after write, iclass 14, count 0 2006.189.07:36:30.75#ibcon#*before return 0, iclass 14, count 0 2006.189.07:36:30.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:36:30.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:36:30.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:36:30.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:36:30.75$vc4f8/vb=1,4 2006.189.07:36:30.75#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.07:36:30.75#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.07:36:30.75#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:30.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:36:30.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:36:30.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:36:30.75#ibcon#enter wrdev, iclass 16, count 2 2006.189.07:36:30.75#ibcon#first serial, iclass 16, count 2 2006.189.07:36:30.75#ibcon#enter sib2, iclass 16, count 2 2006.189.07:36:30.75#ibcon#flushed, iclass 16, count 2 2006.189.07:36:30.75#ibcon#about to write, iclass 16, count 2 2006.189.07:36:30.75#ibcon#wrote, iclass 16, count 2 2006.189.07:36:30.75#ibcon#about to read 3, iclass 16, count 2 2006.189.07:36:30.77#ibcon#read 3, iclass 16, count 2 2006.189.07:36:30.77#ibcon#about to read 4, iclass 16, count 2 2006.189.07:36:30.77#ibcon#read 4, iclass 16, count 2 2006.189.07:36:30.77#ibcon#about to read 5, iclass 16, count 2 2006.189.07:36:30.77#ibcon#read 5, iclass 16, count 2 2006.189.07:36:30.77#ibcon#about to read 6, iclass 16, count 2 2006.189.07:36:30.77#ibcon#read 6, iclass 16, count 2 2006.189.07:36:30.77#ibcon#end of sib2, iclass 16, count 2 2006.189.07:36:30.77#ibcon#*mode == 0, iclass 16, count 2 2006.189.07:36:30.77#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.07:36:30.77#ibcon#[27=AT01-04\r\n] 2006.189.07:36:30.77#ibcon#*before write, iclass 16, count 2 2006.189.07:36:30.77#ibcon#enter sib2, iclass 16, count 2 2006.189.07:36:30.77#ibcon#flushed, iclass 16, count 2 2006.189.07:36:30.77#ibcon#about to write, iclass 16, count 2 2006.189.07:36:30.77#ibcon#wrote, iclass 16, count 2 2006.189.07:36:30.77#ibcon#about to read 3, iclass 16, count 2 2006.189.07:36:30.80#ibcon#read 3, iclass 16, count 2 2006.189.07:36:30.80#ibcon#about to read 4, iclass 16, count 2 2006.189.07:36:30.80#ibcon#read 4, iclass 16, count 2 2006.189.07:36:30.80#ibcon#about to read 5, iclass 16, count 2 2006.189.07:36:30.80#ibcon#read 5, iclass 16, count 2 2006.189.07:36:30.80#ibcon#about to read 6, iclass 16, count 2 2006.189.07:36:30.80#ibcon#read 6, iclass 16, count 2 2006.189.07:36:30.80#ibcon#end of sib2, iclass 16, count 2 2006.189.07:36:30.80#ibcon#*after write, iclass 16, count 2 2006.189.07:36:30.80#ibcon#*before return 0, iclass 16, count 2 2006.189.07:36:30.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:36:30.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:36:30.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.07:36:30.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:30.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:36:30.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:36:30.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:36:30.92#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:36:30.92#ibcon#first serial, iclass 16, count 0 2006.189.07:36:30.92#ibcon#enter sib2, iclass 16, count 0 2006.189.07:36:30.92#ibcon#flushed, iclass 16, count 0 2006.189.07:36:30.92#ibcon#about to write, iclass 16, count 0 2006.189.07:36:30.92#ibcon#wrote, iclass 16, count 0 2006.189.07:36:30.92#ibcon#about to read 3, iclass 16, count 0 2006.189.07:36:30.94#ibcon#read 3, iclass 16, count 0 2006.189.07:36:30.94#ibcon#about to read 4, iclass 16, count 0 2006.189.07:36:30.94#ibcon#read 4, iclass 16, count 0 2006.189.07:36:30.94#ibcon#about to read 5, iclass 16, count 0 2006.189.07:36:30.94#ibcon#read 5, iclass 16, count 0 2006.189.07:36:30.94#ibcon#about to read 6, iclass 16, count 0 2006.189.07:36:30.94#ibcon#read 6, iclass 16, count 0 2006.189.07:36:30.94#ibcon#end of sib2, iclass 16, count 0 2006.189.07:36:30.94#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:36:30.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:36:30.94#ibcon#[27=USB\r\n] 2006.189.07:36:30.94#ibcon#*before write, iclass 16, count 0 2006.189.07:36:30.94#ibcon#enter sib2, iclass 16, count 0 2006.189.07:36:30.94#ibcon#flushed, iclass 16, count 0 2006.189.07:36:30.94#ibcon#about to write, iclass 16, count 0 2006.189.07:36:30.94#ibcon#wrote, iclass 16, count 0 2006.189.07:36:30.94#ibcon#about to read 3, iclass 16, count 0 2006.189.07:36:30.97#ibcon#read 3, iclass 16, count 0 2006.189.07:36:30.97#ibcon#about to read 4, iclass 16, count 0 2006.189.07:36:30.97#ibcon#read 4, iclass 16, count 0 2006.189.07:36:30.97#ibcon#about to read 5, iclass 16, count 0 2006.189.07:36:30.97#ibcon#read 5, iclass 16, count 0 2006.189.07:36:30.97#ibcon#about to read 6, iclass 16, count 0 2006.189.07:36:30.97#ibcon#read 6, iclass 16, count 0 2006.189.07:36:30.97#ibcon#end of sib2, iclass 16, count 0 2006.189.07:36:30.97#ibcon#*after write, iclass 16, count 0 2006.189.07:36:30.97#ibcon#*before return 0, iclass 16, count 0 2006.189.07:36:30.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:36:30.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:36:30.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:36:30.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:36:30.97$vc4f8/vblo=2,640.99 2006.189.07:36:30.97#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.07:36:30.97#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.07:36:30.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:30.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:30.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:30.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:30.97#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:36:30.97#ibcon#first serial, iclass 18, count 0 2006.189.07:36:30.97#ibcon#enter sib2, iclass 18, count 0 2006.189.07:36:30.97#ibcon#flushed, iclass 18, count 0 2006.189.07:36:30.97#ibcon#about to write, iclass 18, count 0 2006.189.07:36:30.97#ibcon#wrote, iclass 18, count 0 2006.189.07:36:30.97#ibcon#about to read 3, iclass 18, count 0 2006.189.07:36:30.99#ibcon#read 3, iclass 18, count 0 2006.189.07:36:30.99#ibcon#about to read 4, iclass 18, count 0 2006.189.07:36:30.99#ibcon#read 4, iclass 18, count 0 2006.189.07:36:30.99#ibcon#about to read 5, iclass 18, count 0 2006.189.07:36:30.99#ibcon#read 5, iclass 18, count 0 2006.189.07:36:30.99#ibcon#about to read 6, iclass 18, count 0 2006.189.07:36:30.99#ibcon#read 6, iclass 18, count 0 2006.189.07:36:30.99#ibcon#end of sib2, iclass 18, count 0 2006.189.07:36:30.99#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:36:30.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:36:30.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:36:30.99#ibcon#*before write, iclass 18, count 0 2006.189.07:36:30.99#ibcon#enter sib2, iclass 18, count 0 2006.189.07:36:30.99#ibcon#flushed, iclass 18, count 0 2006.189.07:36:30.99#ibcon#about to write, iclass 18, count 0 2006.189.07:36:30.99#ibcon#wrote, iclass 18, count 0 2006.189.07:36:30.99#ibcon#about to read 3, iclass 18, count 0 2006.189.07:36:31.03#ibcon#read 3, iclass 18, count 0 2006.189.07:36:31.03#ibcon#about to read 4, iclass 18, count 0 2006.189.07:36:31.03#ibcon#read 4, iclass 18, count 0 2006.189.07:36:31.03#ibcon#about to read 5, iclass 18, count 0 2006.189.07:36:31.03#ibcon#read 5, iclass 18, count 0 2006.189.07:36:31.03#ibcon#about to read 6, iclass 18, count 0 2006.189.07:36:31.03#ibcon#read 6, iclass 18, count 0 2006.189.07:36:31.03#ibcon#end of sib2, iclass 18, count 0 2006.189.07:36:31.03#ibcon#*after write, iclass 18, count 0 2006.189.07:36:31.03#ibcon#*before return 0, iclass 18, count 0 2006.189.07:36:31.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:31.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:36:31.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:36:31.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:36:31.03$vc4f8/vb=2,4 2006.189.07:36:31.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:36:31.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:36:31.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:31.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:31.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:31.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:31.09#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:36:31.09#ibcon#first serial, iclass 20, count 2 2006.189.07:36:31.09#ibcon#enter sib2, iclass 20, count 2 2006.189.07:36:31.09#ibcon#flushed, iclass 20, count 2 2006.189.07:36:31.09#ibcon#about to write, iclass 20, count 2 2006.189.07:36:31.09#ibcon#wrote, iclass 20, count 2 2006.189.07:36:31.09#ibcon#about to read 3, iclass 20, count 2 2006.189.07:36:31.11#ibcon#read 3, iclass 20, count 2 2006.189.07:36:31.11#ibcon#about to read 4, iclass 20, count 2 2006.189.07:36:31.11#ibcon#read 4, iclass 20, count 2 2006.189.07:36:31.11#ibcon#about to read 5, iclass 20, count 2 2006.189.07:36:31.11#ibcon#read 5, iclass 20, count 2 2006.189.07:36:31.11#ibcon#about to read 6, iclass 20, count 2 2006.189.07:36:31.11#ibcon#read 6, iclass 20, count 2 2006.189.07:36:31.11#ibcon#end of sib2, iclass 20, count 2 2006.189.07:36:31.11#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:36:31.11#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:36:31.11#ibcon#[27=AT02-04\r\n] 2006.189.07:36:31.11#ibcon#*before write, iclass 20, count 2 2006.189.07:36:31.11#ibcon#enter sib2, iclass 20, count 2 2006.189.07:36:31.11#ibcon#flushed, iclass 20, count 2 2006.189.07:36:31.11#ibcon#about to write, iclass 20, count 2 2006.189.07:36:31.11#ibcon#wrote, iclass 20, count 2 2006.189.07:36:31.11#ibcon#about to read 3, iclass 20, count 2 2006.189.07:36:31.14#ibcon#read 3, iclass 20, count 2 2006.189.07:36:31.14#ibcon#about to read 4, iclass 20, count 2 2006.189.07:36:31.14#ibcon#read 4, iclass 20, count 2 2006.189.07:36:31.14#ibcon#about to read 5, iclass 20, count 2 2006.189.07:36:31.14#ibcon#read 5, iclass 20, count 2 2006.189.07:36:31.14#ibcon#about to read 6, iclass 20, count 2 2006.189.07:36:31.14#ibcon#read 6, iclass 20, count 2 2006.189.07:36:31.14#ibcon#end of sib2, iclass 20, count 2 2006.189.07:36:31.14#ibcon#*after write, iclass 20, count 2 2006.189.07:36:31.14#ibcon#*before return 0, iclass 20, count 2 2006.189.07:36:31.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:31.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:36:31.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:36:31.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:31.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:31.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:31.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:31.26#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:36:31.26#ibcon#first serial, iclass 20, count 0 2006.189.07:36:31.26#ibcon#enter sib2, iclass 20, count 0 2006.189.07:36:31.26#ibcon#flushed, iclass 20, count 0 2006.189.07:36:31.26#ibcon#about to write, iclass 20, count 0 2006.189.07:36:31.26#ibcon#wrote, iclass 20, count 0 2006.189.07:36:31.26#ibcon#about to read 3, iclass 20, count 0 2006.189.07:36:31.28#ibcon#read 3, iclass 20, count 0 2006.189.07:36:31.28#ibcon#about to read 4, iclass 20, count 0 2006.189.07:36:31.28#ibcon#read 4, iclass 20, count 0 2006.189.07:36:31.28#ibcon#about to read 5, iclass 20, count 0 2006.189.07:36:31.28#ibcon#read 5, iclass 20, count 0 2006.189.07:36:31.28#ibcon#about to read 6, iclass 20, count 0 2006.189.07:36:31.28#ibcon#read 6, iclass 20, count 0 2006.189.07:36:31.28#ibcon#end of sib2, iclass 20, count 0 2006.189.07:36:31.28#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:36:31.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:36:31.28#ibcon#[27=USB\r\n] 2006.189.07:36:31.28#ibcon#*before write, iclass 20, count 0 2006.189.07:36:31.28#ibcon#enter sib2, iclass 20, count 0 2006.189.07:36:31.28#ibcon#flushed, iclass 20, count 0 2006.189.07:36:31.28#ibcon#about to write, iclass 20, count 0 2006.189.07:36:31.28#ibcon#wrote, iclass 20, count 0 2006.189.07:36:31.28#ibcon#about to read 3, iclass 20, count 0 2006.189.07:36:31.31#ibcon#read 3, iclass 20, count 0 2006.189.07:36:31.31#ibcon#about to read 4, iclass 20, count 0 2006.189.07:36:31.31#ibcon#read 4, iclass 20, count 0 2006.189.07:36:31.31#ibcon#about to read 5, iclass 20, count 0 2006.189.07:36:31.31#ibcon#read 5, iclass 20, count 0 2006.189.07:36:31.31#ibcon#about to read 6, iclass 20, count 0 2006.189.07:36:31.31#ibcon#read 6, iclass 20, count 0 2006.189.07:36:31.31#ibcon#end of sib2, iclass 20, count 0 2006.189.07:36:31.31#ibcon#*after write, iclass 20, count 0 2006.189.07:36:31.31#ibcon#*before return 0, iclass 20, count 0 2006.189.07:36:31.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:31.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:36:31.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:36:31.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:36:31.31$vc4f8/vblo=3,656.99 2006.189.07:36:31.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:36:31.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:36:31.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:31.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:31.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:31.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:31.31#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:36:31.31#ibcon#first serial, iclass 22, count 0 2006.189.07:36:31.31#ibcon#enter sib2, iclass 22, count 0 2006.189.07:36:31.31#ibcon#flushed, iclass 22, count 0 2006.189.07:36:31.31#ibcon#about to write, iclass 22, count 0 2006.189.07:36:31.31#ibcon#wrote, iclass 22, count 0 2006.189.07:36:31.31#ibcon#about to read 3, iclass 22, count 0 2006.189.07:36:31.33#ibcon#read 3, iclass 22, count 0 2006.189.07:36:31.33#ibcon#about to read 4, iclass 22, count 0 2006.189.07:36:31.33#ibcon#read 4, iclass 22, count 0 2006.189.07:36:31.33#ibcon#about to read 5, iclass 22, count 0 2006.189.07:36:31.33#ibcon#read 5, iclass 22, count 0 2006.189.07:36:31.33#ibcon#about to read 6, iclass 22, count 0 2006.189.07:36:31.33#ibcon#read 6, iclass 22, count 0 2006.189.07:36:31.33#ibcon#end of sib2, iclass 22, count 0 2006.189.07:36:31.33#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:36:31.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:36:31.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:36:31.33#ibcon#*before write, iclass 22, count 0 2006.189.07:36:31.33#ibcon#enter sib2, iclass 22, count 0 2006.189.07:36:31.33#ibcon#flushed, iclass 22, count 0 2006.189.07:36:31.33#ibcon#about to write, iclass 22, count 0 2006.189.07:36:31.33#ibcon#wrote, iclass 22, count 0 2006.189.07:36:31.33#ibcon#about to read 3, iclass 22, count 0 2006.189.07:36:31.37#ibcon#read 3, iclass 22, count 0 2006.189.07:36:31.37#ibcon#about to read 4, iclass 22, count 0 2006.189.07:36:31.37#ibcon#read 4, iclass 22, count 0 2006.189.07:36:31.37#ibcon#about to read 5, iclass 22, count 0 2006.189.07:36:31.37#ibcon#read 5, iclass 22, count 0 2006.189.07:36:31.37#ibcon#about to read 6, iclass 22, count 0 2006.189.07:36:31.37#ibcon#read 6, iclass 22, count 0 2006.189.07:36:31.37#ibcon#end of sib2, iclass 22, count 0 2006.189.07:36:31.37#ibcon#*after write, iclass 22, count 0 2006.189.07:36:31.37#ibcon#*before return 0, iclass 22, count 0 2006.189.07:36:31.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:31.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:36:31.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:36:31.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:36:31.37$vc4f8/vb=3,4 2006.189.07:36:31.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:36:31.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:36:31.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:31.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:31.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:31.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:31.43#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:36:31.43#ibcon#first serial, iclass 24, count 2 2006.189.07:36:31.43#ibcon#enter sib2, iclass 24, count 2 2006.189.07:36:31.43#ibcon#flushed, iclass 24, count 2 2006.189.07:36:31.43#ibcon#about to write, iclass 24, count 2 2006.189.07:36:31.43#ibcon#wrote, iclass 24, count 2 2006.189.07:36:31.43#ibcon#about to read 3, iclass 24, count 2 2006.189.07:36:31.45#ibcon#read 3, iclass 24, count 2 2006.189.07:36:31.45#ibcon#about to read 4, iclass 24, count 2 2006.189.07:36:31.45#ibcon#read 4, iclass 24, count 2 2006.189.07:36:31.45#ibcon#about to read 5, iclass 24, count 2 2006.189.07:36:31.45#ibcon#read 5, iclass 24, count 2 2006.189.07:36:31.45#ibcon#about to read 6, iclass 24, count 2 2006.189.07:36:31.45#ibcon#read 6, iclass 24, count 2 2006.189.07:36:31.45#ibcon#end of sib2, iclass 24, count 2 2006.189.07:36:31.45#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:36:31.45#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:36:31.45#ibcon#[27=AT03-04\r\n] 2006.189.07:36:31.45#ibcon#*before write, iclass 24, count 2 2006.189.07:36:31.45#ibcon#enter sib2, iclass 24, count 2 2006.189.07:36:31.45#ibcon#flushed, iclass 24, count 2 2006.189.07:36:31.45#ibcon#about to write, iclass 24, count 2 2006.189.07:36:31.45#ibcon#wrote, iclass 24, count 2 2006.189.07:36:31.45#ibcon#about to read 3, iclass 24, count 2 2006.189.07:36:31.48#ibcon#read 3, iclass 24, count 2 2006.189.07:36:31.48#ibcon#about to read 4, iclass 24, count 2 2006.189.07:36:31.48#ibcon#read 4, iclass 24, count 2 2006.189.07:36:31.48#ibcon#about to read 5, iclass 24, count 2 2006.189.07:36:31.48#ibcon#read 5, iclass 24, count 2 2006.189.07:36:31.48#ibcon#about to read 6, iclass 24, count 2 2006.189.07:36:31.48#ibcon#read 6, iclass 24, count 2 2006.189.07:36:31.48#ibcon#end of sib2, iclass 24, count 2 2006.189.07:36:31.48#ibcon#*after write, iclass 24, count 2 2006.189.07:36:31.48#ibcon#*before return 0, iclass 24, count 2 2006.189.07:36:31.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:31.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:36:31.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:36:31.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:31.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:31.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:31.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:31.60#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:36:31.60#ibcon#first serial, iclass 24, count 0 2006.189.07:36:31.60#ibcon#enter sib2, iclass 24, count 0 2006.189.07:36:31.60#ibcon#flushed, iclass 24, count 0 2006.189.07:36:31.60#ibcon#about to write, iclass 24, count 0 2006.189.07:36:31.60#ibcon#wrote, iclass 24, count 0 2006.189.07:36:31.60#ibcon#about to read 3, iclass 24, count 0 2006.189.07:36:31.62#ibcon#read 3, iclass 24, count 0 2006.189.07:36:31.62#ibcon#about to read 4, iclass 24, count 0 2006.189.07:36:31.62#ibcon#read 4, iclass 24, count 0 2006.189.07:36:31.62#ibcon#about to read 5, iclass 24, count 0 2006.189.07:36:31.62#ibcon#read 5, iclass 24, count 0 2006.189.07:36:31.62#ibcon#about to read 6, iclass 24, count 0 2006.189.07:36:31.62#ibcon#read 6, iclass 24, count 0 2006.189.07:36:31.62#ibcon#end of sib2, iclass 24, count 0 2006.189.07:36:31.62#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:36:31.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:36:31.62#ibcon#[27=USB\r\n] 2006.189.07:36:31.62#ibcon#*before write, iclass 24, count 0 2006.189.07:36:31.62#ibcon#enter sib2, iclass 24, count 0 2006.189.07:36:31.62#ibcon#flushed, iclass 24, count 0 2006.189.07:36:31.62#ibcon#about to write, iclass 24, count 0 2006.189.07:36:31.62#ibcon#wrote, iclass 24, count 0 2006.189.07:36:31.62#ibcon#about to read 3, iclass 24, count 0 2006.189.07:36:31.65#ibcon#read 3, iclass 24, count 0 2006.189.07:36:31.65#ibcon#about to read 4, iclass 24, count 0 2006.189.07:36:31.65#ibcon#read 4, iclass 24, count 0 2006.189.07:36:31.65#ibcon#about to read 5, iclass 24, count 0 2006.189.07:36:31.65#ibcon#read 5, iclass 24, count 0 2006.189.07:36:31.65#ibcon#about to read 6, iclass 24, count 0 2006.189.07:36:31.65#ibcon#read 6, iclass 24, count 0 2006.189.07:36:31.65#ibcon#end of sib2, iclass 24, count 0 2006.189.07:36:31.65#ibcon#*after write, iclass 24, count 0 2006.189.07:36:31.65#ibcon#*before return 0, iclass 24, count 0 2006.189.07:36:31.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:31.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:36:31.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:36:31.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:36:31.65$vc4f8/vblo=4,712.99 2006.189.07:36:31.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.07:36:31.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.07:36:31.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:31.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:31.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:31.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:31.65#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:36:31.65#ibcon#first serial, iclass 26, count 0 2006.189.07:36:31.65#ibcon#enter sib2, iclass 26, count 0 2006.189.07:36:31.65#ibcon#flushed, iclass 26, count 0 2006.189.07:36:31.65#ibcon#about to write, iclass 26, count 0 2006.189.07:36:31.65#ibcon#wrote, iclass 26, count 0 2006.189.07:36:31.65#ibcon#about to read 3, iclass 26, count 0 2006.189.07:36:31.67#ibcon#read 3, iclass 26, count 0 2006.189.07:36:31.67#ibcon#about to read 4, iclass 26, count 0 2006.189.07:36:31.67#ibcon#read 4, iclass 26, count 0 2006.189.07:36:31.67#ibcon#about to read 5, iclass 26, count 0 2006.189.07:36:31.67#ibcon#read 5, iclass 26, count 0 2006.189.07:36:31.67#ibcon#about to read 6, iclass 26, count 0 2006.189.07:36:31.67#ibcon#read 6, iclass 26, count 0 2006.189.07:36:31.67#ibcon#end of sib2, iclass 26, count 0 2006.189.07:36:31.67#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:36:31.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:36:31.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:36:31.67#ibcon#*before write, iclass 26, count 0 2006.189.07:36:31.67#ibcon#enter sib2, iclass 26, count 0 2006.189.07:36:31.67#ibcon#flushed, iclass 26, count 0 2006.189.07:36:31.67#ibcon#about to write, iclass 26, count 0 2006.189.07:36:31.67#ibcon#wrote, iclass 26, count 0 2006.189.07:36:31.67#ibcon#about to read 3, iclass 26, count 0 2006.189.07:36:31.71#ibcon#read 3, iclass 26, count 0 2006.189.07:36:31.71#ibcon#about to read 4, iclass 26, count 0 2006.189.07:36:31.71#ibcon#read 4, iclass 26, count 0 2006.189.07:36:31.71#ibcon#about to read 5, iclass 26, count 0 2006.189.07:36:31.71#ibcon#read 5, iclass 26, count 0 2006.189.07:36:31.71#ibcon#about to read 6, iclass 26, count 0 2006.189.07:36:31.71#ibcon#read 6, iclass 26, count 0 2006.189.07:36:31.71#ibcon#end of sib2, iclass 26, count 0 2006.189.07:36:31.71#ibcon#*after write, iclass 26, count 0 2006.189.07:36:31.71#ibcon#*before return 0, iclass 26, count 0 2006.189.07:36:31.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:31.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:36:31.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:36:31.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:36:31.71$vc4f8/vb=4,4 2006.189.07:36:31.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.07:36:31.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.07:36:31.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:31.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:31.77#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:31.77#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:31.77#ibcon#enter wrdev, iclass 28, count 2 2006.189.07:36:31.77#ibcon#first serial, iclass 28, count 2 2006.189.07:36:31.77#ibcon#enter sib2, iclass 28, count 2 2006.189.07:36:31.77#ibcon#flushed, iclass 28, count 2 2006.189.07:36:31.77#ibcon#about to write, iclass 28, count 2 2006.189.07:36:31.77#ibcon#wrote, iclass 28, count 2 2006.189.07:36:31.77#ibcon#about to read 3, iclass 28, count 2 2006.189.07:36:31.79#ibcon#read 3, iclass 28, count 2 2006.189.07:36:31.79#ibcon#about to read 4, iclass 28, count 2 2006.189.07:36:31.79#ibcon#read 4, iclass 28, count 2 2006.189.07:36:31.79#ibcon#about to read 5, iclass 28, count 2 2006.189.07:36:31.79#ibcon#read 5, iclass 28, count 2 2006.189.07:36:31.79#ibcon#about to read 6, iclass 28, count 2 2006.189.07:36:31.79#ibcon#read 6, iclass 28, count 2 2006.189.07:36:31.79#ibcon#end of sib2, iclass 28, count 2 2006.189.07:36:31.79#ibcon#*mode == 0, iclass 28, count 2 2006.189.07:36:31.79#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.07:36:31.79#ibcon#[27=AT04-04\r\n] 2006.189.07:36:31.79#ibcon#*before write, iclass 28, count 2 2006.189.07:36:31.79#ibcon#enter sib2, iclass 28, count 2 2006.189.07:36:31.79#ibcon#flushed, iclass 28, count 2 2006.189.07:36:31.79#ibcon#about to write, iclass 28, count 2 2006.189.07:36:31.79#ibcon#wrote, iclass 28, count 2 2006.189.07:36:31.79#ibcon#about to read 3, iclass 28, count 2 2006.189.07:36:31.82#ibcon#read 3, iclass 28, count 2 2006.189.07:36:31.82#ibcon#about to read 4, iclass 28, count 2 2006.189.07:36:31.82#ibcon#read 4, iclass 28, count 2 2006.189.07:36:31.82#ibcon#about to read 5, iclass 28, count 2 2006.189.07:36:31.82#ibcon#read 5, iclass 28, count 2 2006.189.07:36:31.82#ibcon#about to read 6, iclass 28, count 2 2006.189.07:36:31.82#ibcon#read 6, iclass 28, count 2 2006.189.07:36:31.82#ibcon#end of sib2, iclass 28, count 2 2006.189.07:36:31.82#ibcon#*after write, iclass 28, count 2 2006.189.07:36:31.82#ibcon#*before return 0, iclass 28, count 2 2006.189.07:36:31.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:31.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:36:31.82#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.07:36:31.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:31.82#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:31.94#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:31.94#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:31.94#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:36:31.94#ibcon#first serial, iclass 28, count 0 2006.189.07:36:31.94#ibcon#enter sib2, iclass 28, count 0 2006.189.07:36:31.94#ibcon#flushed, iclass 28, count 0 2006.189.07:36:31.94#ibcon#about to write, iclass 28, count 0 2006.189.07:36:31.94#ibcon#wrote, iclass 28, count 0 2006.189.07:36:31.94#ibcon#about to read 3, iclass 28, count 0 2006.189.07:36:31.96#ibcon#read 3, iclass 28, count 0 2006.189.07:36:31.96#ibcon#about to read 4, iclass 28, count 0 2006.189.07:36:31.96#ibcon#read 4, iclass 28, count 0 2006.189.07:36:31.96#ibcon#about to read 5, iclass 28, count 0 2006.189.07:36:31.96#ibcon#read 5, iclass 28, count 0 2006.189.07:36:31.96#ibcon#about to read 6, iclass 28, count 0 2006.189.07:36:31.96#ibcon#read 6, iclass 28, count 0 2006.189.07:36:31.96#ibcon#end of sib2, iclass 28, count 0 2006.189.07:36:31.96#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:36:31.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:36:31.96#ibcon#[27=USB\r\n] 2006.189.07:36:31.96#ibcon#*before write, iclass 28, count 0 2006.189.07:36:31.96#ibcon#enter sib2, iclass 28, count 0 2006.189.07:36:31.96#ibcon#flushed, iclass 28, count 0 2006.189.07:36:31.96#ibcon#about to write, iclass 28, count 0 2006.189.07:36:31.96#ibcon#wrote, iclass 28, count 0 2006.189.07:36:31.96#ibcon#about to read 3, iclass 28, count 0 2006.189.07:36:31.99#ibcon#read 3, iclass 28, count 0 2006.189.07:36:31.99#ibcon#about to read 4, iclass 28, count 0 2006.189.07:36:31.99#ibcon#read 4, iclass 28, count 0 2006.189.07:36:31.99#ibcon#about to read 5, iclass 28, count 0 2006.189.07:36:31.99#ibcon#read 5, iclass 28, count 0 2006.189.07:36:31.99#ibcon#about to read 6, iclass 28, count 0 2006.189.07:36:31.99#ibcon#read 6, iclass 28, count 0 2006.189.07:36:31.99#ibcon#end of sib2, iclass 28, count 0 2006.189.07:36:31.99#ibcon#*after write, iclass 28, count 0 2006.189.07:36:31.99#ibcon#*before return 0, iclass 28, count 0 2006.189.07:36:31.99#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:31.99#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:36:31.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:36:31.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:36:31.99$vc4f8/vblo=5,744.99 2006.189.07:36:31.99#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.07:36:31.99#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.07:36:31.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:31.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:31.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:31.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:31.99#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:36:31.99#ibcon#first serial, iclass 30, count 0 2006.189.07:36:31.99#ibcon#enter sib2, iclass 30, count 0 2006.189.07:36:31.99#ibcon#flushed, iclass 30, count 0 2006.189.07:36:31.99#ibcon#about to write, iclass 30, count 0 2006.189.07:36:31.99#ibcon#wrote, iclass 30, count 0 2006.189.07:36:31.99#ibcon#about to read 3, iclass 30, count 0 2006.189.07:36:32.01#ibcon#read 3, iclass 30, count 0 2006.189.07:36:32.01#ibcon#about to read 4, iclass 30, count 0 2006.189.07:36:32.01#ibcon#read 4, iclass 30, count 0 2006.189.07:36:32.01#ibcon#about to read 5, iclass 30, count 0 2006.189.07:36:32.01#ibcon#read 5, iclass 30, count 0 2006.189.07:36:32.01#ibcon#about to read 6, iclass 30, count 0 2006.189.07:36:32.01#ibcon#read 6, iclass 30, count 0 2006.189.07:36:32.01#ibcon#end of sib2, iclass 30, count 0 2006.189.07:36:32.01#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:36:32.01#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:36:32.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:36:32.01#ibcon#*before write, iclass 30, count 0 2006.189.07:36:32.01#ibcon#enter sib2, iclass 30, count 0 2006.189.07:36:32.01#ibcon#flushed, iclass 30, count 0 2006.189.07:36:32.01#ibcon#about to write, iclass 30, count 0 2006.189.07:36:32.01#ibcon#wrote, iclass 30, count 0 2006.189.07:36:32.01#ibcon#about to read 3, iclass 30, count 0 2006.189.07:36:32.05#ibcon#read 3, iclass 30, count 0 2006.189.07:36:32.05#ibcon#about to read 4, iclass 30, count 0 2006.189.07:36:32.05#ibcon#read 4, iclass 30, count 0 2006.189.07:36:32.05#ibcon#about to read 5, iclass 30, count 0 2006.189.07:36:32.05#ibcon#read 5, iclass 30, count 0 2006.189.07:36:32.05#ibcon#about to read 6, iclass 30, count 0 2006.189.07:36:32.05#ibcon#read 6, iclass 30, count 0 2006.189.07:36:32.05#ibcon#end of sib2, iclass 30, count 0 2006.189.07:36:32.05#ibcon#*after write, iclass 30, count 0 2006.189.07:36:32.05#ibcon#*before return 0, iclass 30, count 0 2006.189.07:36:32.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:32.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:36:32.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:36:32.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:36:32.05$vc4f8/vb=5,4 2006.189.07:36:32.05#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.07:36:32.05#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.07:36:32.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:32.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:32.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:32.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:32.12#ibcon#enter wrdev, iclass 32, count 2 2006.189.07:36:32.12#ibcon#first serial, iclass 32, count 2 2006.189.07:36:32.12#ibcon#enter sib2, iclass 32, count 2 2006.189.07:36:32.12#ibcon#flushed, iclass 32, count 2 2006.189.07:36:32.12#ibcon#about to write, iclass 32, count 2 2006.189.07:36:32.12#ibcon#wrote, iclass 32, count 2 2006.189.07:36:32.12#ibcon#about to read 3, iclass 32, count 2 2006.189.07:36:32.13#ibcon#read 3, iclass 32, count 2 2006.189.07:36:32.13#ibcon#about to read 4, iclass 32, count 2 2006.189.07:36:32.13#ibcon#read 4, iclass 32, count 2 2006.189.07:36:32.13#ibcon#about to read 5, iclass 32, count 2 2006.189.07:36:32.13#ibcon#read 5, iclass 32, count 2 2006.189.07:36:32.13#ibcon#about to read 6, iclass 32, count 2 2006.189.07:36:32.13#ibcon#read 6, iclass 32, count 2 2006.189.07:36:32.13#ibcon#end of sib2, iclass 32, count 2 2006.189.07:36:32.13#ibcon#*mode == 0, iclass 32, count 2 2006.189.07:36:32.13#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.07:36:32.13#ibcon#[27=AT05-04\r\n] 2006.189.07:36:32.13#ibcon#*before write, iclass 32, count 2 2006.189.07:36:32.13#ibcon#enter sib2, iclass 32, count 2 2006.189.07:36:32.13#ibcon#flushed, iclass 32, count 2 2006.189.07:36:32.13#ibcon#about to write, iclass 32, count 2 2006.189.07:36:32.13#ibcon#wrote, iclass 32, count 2 2006.189.07:36:32.13#ibcon#about to read 3, iclass 32, count 2 2006.189.07:36:32.16#ibcon#read 3, iclass 32, count 2 2006.189.07:36:32.16#ibcon#about to read 4, iclass 32, count 2 2006.189.07:36:32.16#ibcon#read 4, iclass 32, count 2 2006.189.07:36:32.16#ibcon#about to read 5, iclass 32, count 2 2006.189.07:36:32.16#ibcon#read 5, iclass 32, count 2 2006.189.07:36:32.16#ibcon#about to read 6, iclass 32, count 2 2006.189.07:36:32.16#ibcon#read 6, iclass 32, count 2 2006.189.07:36:32.16#ibcon#end of sib2, iclass 32, count 2 2006.189.07:36:32.16#ibcon#*after write, iclass 32, count 2 2006.189.07:36:32.16#ibcon#*before return 0, iclass 32, count 2 2006.189.07:36:32.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:32.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:36:32.16#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.07:36:32.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:32.16#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:32.28#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:32.28#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:32.28#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:36:32.28#ibcon#first serial, iclass 32, count 0 2006.189.07:36:32.28#ibcon#enter sib2, iclass 32, count 0 2006.189.07:36:32.28#ibcon#flushed, iclass 32, count 0 2006.189.07:36:32.28#ibcon#about to write, iclass 32, count 0 2006.189.07:36:32.28#ibcon#wrote, iclass 32, count 0 2006.189.07:36:32.28#ibcon#about to read 3, iclass 32, count 0 2006.189.07:36:32.30#ibcon#read 3, iclass 32, count 0 2006.189.07:36:32.30#ibcon#about to read 4, iclass 32, count 0 2006.189.07:36:32.30#ibcon#read 4, iclass 32, count 0 2006.189.07:36:32.30#ibcon#about to read 5, iclass 32, count 0 2006.189.07:36:32.30#ibcon#read 5, iclass 32, count 0 2006.189.07:36:32.30#ibcon#about to read 6, iclass 32, count 0 2006.189.07:36:32.30#ibcon#read 6, iclass 32, count 0 2006.189.07:36:32.30#ibcon#end of sib2, iclass 32, count 0 2006.189.07:36:32.30#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:36:32.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:36:32.30#ibcon#[27=USB\r\n] 2006.189.07:36:32.30#ibcon#*before write, iclass 32, count 0 2006.189.07:36:32.30#ibcon#enter sib2, iclass 32, count 0 2006.189.07:36:32.30#ibcon#flushed, iclass 32, count 0 2006.189.07:36:32.30#ibcon#about to write, iclass 32, count 0 2006.189.07:36:32.30#ibcon#wrote, iclass 32, count 0 2006.189.07:36:32.30#ibcon#about to read 3, iclass 32, count 0 2006.189.07:36:32.30#abcon#<5=/04 4.3 7.3 26.43 861008.9\r\n> 2006.189.07:36:32.32#abcon#{5=INTERFACE CLEAR} 2006.189.07:36:32.33#ibcon#read 3, iclass 32, count 0 2006.189.07:36:32.33#ibcon#about to read 4, iclass 32, count 0 2006.189.07:36:32.33#ibcon#read 4, iclass 32, count 0 2006.189.07:36:32.33#ibcon#about to read 5, iclass 32, count 0 2006.189.07:36:32.33#ibcon#read 5, iclass 32, count 0 2006.189.07:36:32.33#ibcon#about to read 6, iclass 32, count 0 2006.189.07:36:32.33#ibcon#read 6, iclass 32, count 0 2006.189.07:36:32.33#ibcon#end of sib2, iclass 32, count 0 2006.189.07:36:32.33#ibcon#*after write, iclass 32, count 0 2006.189.07:36:32.33#ibcon#*before return 0, iclass 32, count 0 2006.189.07:36:32.33#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:32.33#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:36:32.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:36:32.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:36:32.33$vc4f8/vblo=6,752.99 2006.189.07:36:32.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:36:32.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:36:32.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:36:32.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:36:32.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:36:32.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:36:32.33#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:36:32.33#ibcon#first serial, iclass 37, count 0 2006.189.07:36:32.33#ibcon#enter sib2, iclass 37, count 0 2006.189.07:36:32.33#ibcon#flushed, iclass 37, count 0 2006.189.07:36:32.33#ibcon#about to write, iclass 37, count 0 2006.189.07:36:32.33#ibcon#wrote, iclass 37, count 0 2006.189.07:36:32.33#ibcon#about to read 3, iclass 37, count 0 2006.189.07:36:32.35#ibcon#read 3, iclass 37, count 0 2006.189.07:36:32.35#ibcon#about to read 4, iclass 37, count 0 2006.189.07:36:32.35#ibcon#read 4, iclass 37, count 0 2006.189.07:36:32.35#ibcon#about to read 5, iclass 37, count 0 2006.189.07:36:32.35#ibcon#read 5, iclass 37, count 0 2006.189.07:36:32.35#ibcon#about to read 6, iclass 37, count 0 2006.189.07:36:32.35#ibcon#read 6, iclass 37, count 0 2006.189.07:36:32.35#ibcon#end of sib2, iclass 37, count 0 2006.189.07:36:32.35#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:36:32.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:36:32.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:36:32.35#ibcon#*before write, iclass 37, count 0 2006.189.07:36:32.35#ibcon#enter sib2, iclass 37, count 0 2006.189.07:36:32.35#ibcon#flushed, iclass 37, count 0 2006.189.07:36:32.35#ibcon#about to write, iclass 37, count 0 2006.189.07:36:32.35#ibcon#wrote, iclass 37, count 0 2006.189.07:36:32.35#ibcon#about to read 3, iclass 37, count 0 2006.189.07:36:32.38#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:36:32.39#ibcon#read 3, iclass 37, count 0 2006.189.07:36:32.39#ibcon#about to read 4, iclass 37, count 0 2006.189.07:36:32.39#ibcon#read 4, iclass 37, count 0 2006.189.07:36:32.39#ibcon#about to read 5, iclass 37, count 0 2006.189.07:36:32.39#ibcon#read 5, iclass 37, count 0 2006.189.07:36:32.39#ibcon#about to read 6, iclass 37, count 0 2006.189.07:36:32.39#ibcon#read 6, iclass 37, count 0 2006.189.07:36:32.39#ibcon#end of sib2, iclass 37, count 0 2006.189.07:36:32.39#ibcon#*after write, iclass 37, count 0 2006.189.07:36:32.39#ibcon#*before return 0, iclass 37, count 0 2006.189.07:36:32.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:36:32.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:36:32.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:36:32.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:36:32.39$vc4f8/vb=6,4 2006.189.07:36:32.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.07:36:32.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.07:36:32.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:36:32.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:32.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:32.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:32.45#ibcon#enter wrdev, iclass 40, count 2 2006.189.07:36:32.45#ibcon#first serial, iclass 40, count 2 2006.189.07:36:32.45#ibcon#enter sib2, iclass 40, count 2 2006.189.07:36:32.45#ibcon#flushed, iclass 40, count 2 2006.189.07:36:32.45#ibcon#about to write, iclass 40, count 2 2006.189.07:36:32.45#ibcon#wrote, iclass 40, count 2 2006.189.07:36:32.45#ibcon#about to read 3, iclass 40, count 2 2006.189.07:36:32.47#ibcon#read 3, iclass 40, count 2 2006.189.07:36:32.47#ibcon#about to read 4, iclass 40, count 2 2006.189.07:36:32.47#ibcon#read 4, iclass 40, count 2 2006.189.07:36:32.47#ibcon#about to read 5, iclass 40, count 2 2006.189.07:36:32.47#ibcon#read 5, iclass 40, count 2 2006.189.07:36:32.47#ibcon#about to read 6, iclass 40, count 2 2006.189.07:36:32.47#ibcon#read 6, iclass 40, count 2 2006.189.07:36:32.47#ibcon#end of sib2, iclass 40, count 2 2006.189.07:36:32.47#ibcon#*mode == 0, iclass 40, count 2 2006.189.07:36:32.47#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.07:36:32.47#ibcon#[27=AT06-04\r\n] 2006.189.07:36:32.47#ibcon#*before write, iclass 40, count 2 2006.189.07:36:32.47#ibcon#enter sib2, iclass 40, count 2 2006.189.07:36:32.47#ibcon#flushed, iclass 40, count 2 2006.189.07:36:32.47#ibcon#about to write, iclass 40, count 2 2006.189.07:36:32.47#ibcon#wrote, iclass 40, count 2 2006.189.07:36:32.47#ibcon#about to read 3, iclass 40, count 2 2006.189.07:36:32.50#ibcon#read 3, iclass 40, count 2 2006.189.07:36:32.50#ibcon#about to read 4, iclass 40, count 2 2006.189.07:36:32.50#ibcon#read 4, iclass 40, count 2 2006.189.07:36:32.50#ibcon#about to read 5, iclass 40, count 2 2006.189.07:36:32.50#ibcon#read 5, iclass 40, count 2 2006.189.07:36:32.50#ibcon#about to read 6, iclass 40, count 2 2006.189.07:36:32.50#ibcon#read 6, iclass 40, count 2 2006.189.07:36:32.50#ibcon#end of sib2, iclass 40, count 2 2006.189.07:36:32.50#ibcon#*after write, iclass 40, count 2 2006.189.07:36:32.50#ibcon#*before return 0, iclass 40, count 2 2006.189.07:36:32.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:32.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:36:32.50#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.07:36:32.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:36:32.50#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:32.62#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:32.62#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:32.62#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:36:32.62#ibcon#first serial, iclass 40, count 0 2006.189.07:36:32.62#ibcon#enter sib2, iclass 40, count 0 2006.189.07:36:32.62#ibcon#flushed, iclass 40, count 0 2006.189.07:36:32.62#ibcon#about to write, iclass 40, count 0 2006.189.07:36:32.62#ibcon#wrote, iclass 40, count 0 2006.189.07:36:32.62#ibcon#about to read 3, iclass 40, count 0 2006.189.07:36:32.64#ibcon#read 3, iclass 40, count 0 2006.189.07:36:32.64#ibcon#about to read 4, iclass 40, count 0 2006.189.07:36:32.64#ibcon#read 4, iclass 40, count 0 2006.189.07:36:32.64#ibcon#about to read 5, iclass 40, count 0 2006.189.07:36:32.64#ibcon#read 5, iclass 40, count 0 2006.189.07:36:32.64#ibcon#about to read 6, iclass 40, count 0 2006.189.07:36:32.64#ibcon#read 6, iclass 40, count 0 2006.189.07:36:32.64#ibcon#end of sib2, iclass 40, count 0 2006.189.07:36:32.64#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:36:32.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:36:32.64#ibcon#[27=USB\r\n] 2006.189.07:36:32.64#ibcon#*before write, iclass 40, count 0 2006.189.07:36:32.64#ibcon#enter sib2, iclass 40, count 0 2006.189.07:36:32.64#ibcon#flushed, iclass 40, count 0 2006.189.07:36:32.64#ibcon#about to write, iclass 40, count 0 2006.189.07:36:32.64#ibcon#wrote, iclass 40, count 0 2006.189.07:36:32.64#ibcon#about to read 3, iclass 40, count 0 2006.189.07:36:32.67#ibcon#read 3, iclass 40, count 0 2006.189.07:36:32.67#ibcon#about to read 4, iclass 40, count 0 2006.189.07:36:32.67#ibcon#read 4, iclass 40, count 0 2006.189.07:36:32.67#ibcon#about to read 5, iclass 40, count 0 2006.189.07:36:32.67#ibcon#read 5, iclass 40, count 0 2006.189.07:36:32.67#ibcon#about to read 6, iclass 40, count 0 2006.189.07:36:32.67#ibcon#read 6, iclass 40, count 0 2006.189.07:36:32.67#ibcon#end of sib2, iclass 40, count 0 2006.189.07:36:32.67#ibcon#*after write, iclass 40, count 0 2006.189.07:36:32.67#ibcon#*before return 0, iclass 40, count 0 2006.189.07:36:32.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:32.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:36:32.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:36:32.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:36:32.67$vc4f8/vabw=wide 2006.189.07:36:32.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:36:32.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:36:32.67#ibcon#ireg 8 cls_cnt 0 2006.189.07:36:32.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:32.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:32.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:32.67#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:36:32.67#ibcon#first serial, iclass 4, count 0 2006.189.07:36:32.67#ibcon#enter sib2, iclass 4, count 0 2006.189.07:36:32.67#ibcon#flushed, iclass 4, count 0 2006.189.07:36:32.67#ibcon#about to write, iclass 4, count 0 2006.189.07:36:32.67#ibcon#wrote, iclass 4, count 0 2006.189.07:36:32.67#ibcon#about to read 3, iclass 4, count 0 2006.189.07:36:32.69#ibcon#read 3, iclass 4, count 0 2006.189.07:36:32.69#ibcon#about to read 4, iclass 4, count 0 2006.189.07:36:32.69#ibcon#read 4, iclass 4, count 0 2006.189.07:36:32.69#ibcon#about to read 5, iclass 4, count 0 2006.189.07:36:32.69#ibcon#read 5, iclass 4, count 0 2006.189.07:36:32.69#ibcon#about to read 6, iclass 4, count 0 2006.189.07:36:32.69#ibcon#read 6, iclass 4, count 0 2006.189.07:36:32.69#ibcon#end of sib2, iclass 4, count 0 2006.189.07:36:32.69#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:36:32.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:36:32.69#ibcon#[25=BW32\r\n] 2006.189.07:36:32.69#ibcon#*before write, iclass 4, count 0 2006.189.07:36:32.69#ibcon#enter sib2, iclass 4, count 0 2006.189.07:36:32.69#ibcon#flushed, iclass 4, count 0 2006.189.07:36:32.69#ibcon#about to write, iclass 4, count 0 2006.189.07:36:32.69#ibcon#wrote, iclass 4, count 0 2006.189.07:36:32.69#ibcon#about to read 3, iclass 4, count 0 2006.189.07:36:32.72#ibcon#read 3, iclass 4, count 0 2006.189.07:36:32.72#ibcon#about to read 4, iclass 4, count 0 2006.189.07:36:32.72#ibcon#read 4, iclass 4, count 0 2006.189.07:36:32.72#ibcon#about to read 5, iclass 4, count 0 2006.189.07:36:32.72#ibcon#read 5, iclass 4, count 0 2006.189.07:36:32.72#ibcon#about to read 6, iclass 4, count 0 2006.189.07:36:32.72#ibcon#read 6, iclass 4, count 0 2006.189.07:36:32.72#ibcon#end of sib2, iclass 4, count 0 2006.189.07:36:32.72#ibcon#*after write, iclass 4, count 0 2006.189.07:36:32.72#ibcon#*before return 0, iclass 4, count 0 2006.189.07:36:32.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:32.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:36:32.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:36:32.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:36:32.72$vc4f8/vbbw=wide 2006.189.07:36:32.72#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:36:32.72#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:36:32.72#ibcon#ireg 8 cls_cnt 0 2006.189.07:36:32.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:36:32.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:36:32.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:36:32.79#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:36:32.79#ibcon#first serial, iclass 6, count 0 2006.189.07:36:32.79#ibcon#enter sib2, iclass 6, count 0 2006.189.07:36:32.79#ibcon#flushed, iclass 6, count 0 2006.189.07:36:32.79#ibcon#about to write, iclass 6, count 0 2006.189.07:36:32.79#ibcon#wrote, iclass 6, count 0 2006.189.07:36:32.79#ibcon#about to read 3, iclass 6, count 0 2006.189.07:36:32.81#ibcon#read 3, iclass 6, count 0 2006.189.07:36:32.81#ibcon#about to read 4, iclass 6, count 0 2006.189.07:36:32.81#ibcon#read 4, iclass 6, count 0 2006.189.07:36:32.81#ibcon#about to read 5, iclass 6, count 0 2006.189.07:36:32.81#ibcon#read 5, iclass 6, count 0 2006.189.07:36:32.81#ibcon#about to read 6, iclass 6, count 0 2006.189.07:36:32.81#ibcon#read 6, iclass 6, count 0 2006.189.07:36:32.81#ibcon#end of sib2, iclass 6, count 0 2006.189.07:36:32.81#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:36:32.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:36:32.81#ibcon#[27=BW32\r\n] 2006.189.07:36:32.81#ibcon#*before write, iclass 6, count 0 2006.189.07:36:32.81#ibcon#enter sib2, iclass 6, count 0 2006.189.07:36:32.81#ibcon#flushed, iclass 6, count 0 2006.189.07:36:32.81#ibcon#about to write, iclass 6, count 0 2006.189.07:36:32.81#ibcon#wrote, iclass 6, count 0 2006.189.07:36:32.81#ibcon#about to read 3, iclass 6, count 0 2006.189.07:36:32.84#ibcon#read 3, iclass 6, count 0 2006.189.07:36:32.84#ibcon#about to read 4, iclass 6, count 0 2006.189.07:36:32.84#ibcon#read 4, iclass 6, count 0 2006.189.07:36:32.84#ibcon#about to read 5, iclass 6, count 0 2006.189.07:36:32.84#ibcon#read 5, iclass 6, count 0 2006.189.07:36:32.84#ibcon#about to read 6, iclass 6, count 0 2006.189.07:36:32.84#ibcon#read 6, iclass 6, count 0 2006.189.07:36:32.84#ibcon#end of sib2, iclass 6, count 0 2006.189.07:36:32.84#ibcon#*after write, iclass 6, count 0 2006.189.07:36:32.84#ibcon#*before return 0, iclass 6, count 0 2006.189.07:36:32.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:36:32.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:36:32.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:36:32.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:36:32.84$4f8m12a/ifd4f 2006.189.07:36:32.84$ifd4f/lo= 2006.189.07:36:32.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:36:32.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:36:32.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:36:32.84$ifd4f/patch= 2006.189.07:36:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:36:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:36:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:36:32.85$4f8m12a/"form=m,16.000,1:2 2006.189.07:36:32.85$4f8m12a/"tpicd 2006.189.07:36:32.85$4f8m12a/echo=off 2006.189.07:36:32.85$4f8m12a/xlog=off 2006.189.07:36:32.85:!2006.189.07:37:00 2006.189.07:36:45.13#trakl#Source acquired 2006.189.07:36:45.13#flagr#flagr/antenna,acquired 2006.189.07:37:00.01:preob 2006.189.07:37:01.13/onsource/TRACKING 2006.189.07:37:01.13:!2006.189.07:37:10 2006.189.07:37:10.00:data_valid=on 2006.189.07:37:10.00:midob 2006.189.07:37:10.13/onsource/TRACKING 2006.189.07:37:10.13/wx/26.41,1008.9,86 2006.189.07:37:10.25/cable/+6.4536E-03 2006.189.07:37:11.34/va/01,08,usb,yes,28,29 2006.189.07:37:11.34/va/02,07,usb,yes,28,29 2006.189.07:37:11.34/va/03,06,usb,yes,29,29 2006.189.07:37:11.34/va/04,07,usb,yes,29,31 2006.189.07:37:11.34/va/05,07,usb,yes,30,32 2006.189.07:37:11.34/va/06,06,usb,yes,29,29 2006.189.07:37:11.34/va/07,06,usb,yes,29,29 2006.189.07:37:11.34/va/08,06,usb,yes,32,31 2006.189.07:37:11.57/valo/01,532.99,yes,locked 2006.189.07:37:11.57/valo/02,572.99,yes,locked 2006.189.07:37:11.57/valo/03,672.99,yes,locked 2006.189.07:37:11.57/valo/04,832.99,yes,locked 2006.189.07:37:11.57/valo/05,652.99,yes,locked 2006.189.07:37:11.57/valo/06,772.99,yes,locked 2006.189.07:37:11.57/valo/07,832.99,yes,locked 2006.189.07:37:11.57/valo/08,852.99,yes,locked 2006.189.07:37:12.66/vb/01,04,usb,yes,28,27 2006.189.07:37:12.66/vb/02,04,usb,yes,30,31 2006.189.07:37:12.66/vb/03,04,usb,yes,27,30 2006.189.07:37:12.66/vb/04,04,usb,yes,27,27 2006.189.07:37:12.66/vb/05,04,usb,yes,26,30 2006.189.07:37:12.66/vb/06,04,usb,yes,27,29 2006.189.07:37:12.66/vb/07,04,usb,yes,29,29 2006.189.07:37:12.66/vb/08,04,usb,yes,26,30 2006.189.07:37:12.90/vblo/01,632.99,yes,locked 2006.189.07:37:12.90/vblo/02,640.99,yes,locked 2006.189.07:37:12.90/vblo/03,656.99,yes,locked 2006.189.07:37:12.90/vblo/04,712.99,yes,locked 2006.189.07:37:12.90/vblo/05,744.99,yes,locked 2006.189.07:37:12.90/vblo/06,752.99,yes,locked 2006.189.07:37:12.90/vblo/07,734.99,yes,locked 2006.189.07:37:12.90/vblo/08,744.99,yes,locked 2006.189.07:37:13.05/vabw/8 2006.189.07:37:13.20/vbbw/8 2006.189.07:37:13.29/xfe/off,on,14.5 2006.189.07:37:13.67/ifatt/23,28,28,28 2006.189.07:37:14.07/fmout-gps/S +2.96E-07 2006.189.07:37:14.16:!2006.189.07:38:10 2006.189.07:38:10.01:data_valid=off 2006.189.07:38:10.02:postob 2006.189.07:38:10.19/cable/+6.4520E-03 2006.189.07:38:10.20/wx/26.38,1008.9,86 2006.189.07:38:11.07/fmout-gps/S +2.96E-07 2006.189.07:38:11.08:scan_name=189-0739,k06189,60 2006.189.07:38:11.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.189.07:38:11.16#flagr#flagr/antenna,new-source 2006.189.07:38:12.13:checkk5 2006.189.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:38:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:38:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:38:14.02/chk_obsdata//k5ts1/T1890737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:38:14.40/chk_obsdata//k5ts2/T1890737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:38:14.78/chk_obsdata//k5ts3/T1890737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:38:15.16/chk_obsdata//k5ts4/T1890737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:38:15.85/k5log//k5ts1_log_newline 2006.189.07:38:16.56/k5log//k5ts2_log_newline 2006.189.07:38:17.27/k5log//k5ts3_log_newline 2006.189.07:38:17.96/k5log//k5ts4_log_newline 2006.189.07:38:17.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:38:17.99:4f8m12a=1 2006.189.07:38:17.99$4f8m12a/echo=on 2006.189.07:38:17.99$4f8m12a/pcalon 2006.189.07:38:17.99$pcalon/"no phase cal control is implemented here 2006.189.07:38:17.99$4f8m12a/"tpicd=stop 2006.189.07:38:17.99$4f8m12a/vc4f8 2006.189.07:38:17.99$vc4f8/valo=1,532.99 2006.189.07:38:17.99#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.07:38:17.99#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.07:38:17.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:17.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:17.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:17.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:17.99#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:38:17.99#ibcon#first serial, iclass 15, count 0 2006.189.07:38:17.99#ibcon#enter sib2, iclass 15, count 0 2006.189.07:38:17.99#ibcon#flushed, iclass 15, count 0 2006.189.07:38:17.99#ibcon#about to write, iclass 15, count 0 2006.189.07:38:18.00#ibcon#wrote, iclass 15, count 0 2006.189.07:38:18.00#ibcon#about to read 3, iclass 15, count 0 2006.189.07:38:18.04#ibcon#read 3, iclass 15, count 0 2006.189.07:38:18.04#ibcon#about to read 4, iclass 15, count 0 2006.189.07:38:18.04#ibcon#read 4, iclass 15, count 0 2006.189.07:38:18.04#ibcon#about to read 5, iclass 15, count 0 2006.189.07:38:18.04#ibcon#read 5, iclass 15, count 0 2006.189.07:38:18.04#ibcon#about to read 6, iclass 15, count 0 2006.189.07:38:18.04#ibcon#read 6, iclass 15, count 0 2006.189.07:38:18.04#ibcon#end of sib2, iclass 15, count 0 2006.189.07:38:18.04#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:38:18.04#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:38:18.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:38:18.04#ibcon#*before write, iclass 15, count 0 2006.189.07:38:18.04#ibcon#enter sib2, iclass 15, count 0 2006.189.07:38:18.04#ibcon#flushed, iclass 15, count 0 2006.189.07:38:18.04#ibcon#about to write, iclass 15, count 0 2006.189.07:38:18.04#ibcon#wrote, iclass 15, count 0 2006.189.07:38:18.04#ibcon#about to read 3, iclass 15, count 0 2006.189.07:38:18.09#ibcon#read 3, iclass 15, count 0 2006.189.07:38:18.09#ibcon#about to read 4, iclass 15, count 0 2006.189.07:38:18.09#ibcon#read 4, iclass 15, count 0 2006.189.07:38:18.09#ibcon#about to read 5, iclass 15, count 0 2006.189.07:38:18.09#ibcon#read 5, iclass 15, count 0 2006.189.07:38:18.09#ibcon#about to read 6, iclass 15, count 0 2006.189.07:38:18.09#ibcon#read 6, iclass 15, count 0 2006.189.07:38:18.09#ibcon#end of sib2, iclass 15, count 0 2006.189.07:38:18.09#ibcon#*after write, iclass 15, count 0 2006.189.07:38:18.09#ibcon#*before return 0, iclass 15, count 0 2006.189.07:38:18.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:18.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:18.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:38:18.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:38:18.09$vc4f8/va=1,8 2006.189.07:38:18.09#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.07:38:18.09#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.07:38:18.09#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:18.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:18.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:18.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:18.09#ibcon#enter wrdev, iclass 17, count 2 2006.189.07:38:18.09#ibcon#first serial, iclass 17, count 2 2006.189.07:38:18.09#ibcon#enter sib2, iclass 17, count 2 2006.189.07:38:18.09#ibcon#flushed, iclass 17, count 2 2006.189.07:38:18.09#ibcon#about to write, iclass 17, count 2 2006.189.07:38:18.09#ibcon#wrote, iclass 17, count 2 2006.189.07:38:18.09#ibcon#about to read 3, iclass 17, count 2 2006.189.07:38:18.11#ibcon#read 3, iclass 17, count 2 2006.189.07:38:18.11#ibcon#about to read 4, iclass 17, count 2 2006.189.07:38:18.11#ibcon#read 4, iclass 17, count 2 2006.189.07:38:18.11#ibcon#about to read 5, iclass 17, count 2 2006.189.07:38:18.11#ibcon#read 5, iclass 17, count 2 2006.189.07:38:18.11#ibcon#about to read 6, iclass 17, count 2 2006.189.07:38:18.11#ibcon#read 6, iclass 17, count 2 2006.189.07:38:18.11#ibcon#end of sib2, iclass 17, count 2 2006.189.07:38:18.11#ibcon#*mode == 0, iclass 17, count 2 2006.189.07:38:18.11#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.07:38:18.11#ibcon#[25=AT01-08\r\n] 2006.189.07:38:18.11#ibcon#*before write, iclass 17, count 2 2006.189.07:38:18.11#ibcon#enter sib2, iclass 17, count 2 2006.189.07:38:18.11#ibcon#flushed, iclass 17, count 2 2006.189.07:38:18.11#ibcon#about to write, iclass 17, count 2 2006.189.07:38:18.11#ibcon#wrote, iclass 17, count 2 2006.189.07:38:18.11#ibcon#about to read 3, iclass 17, count 2 2006.189.07:38:18.14#ibcon#read 3, iclass 17, count 2 2006.189.07:38:18.14#ibcon#about to read 4, iclass 17, count 2 2006.189.07:38:18.14#ibcon#read 4, iclass 17, count 2 2006.189.07:38:18.14#ibcon#about to read 5, iclass 17, count 2 2006.189.07:38:18.14#ibcon#read 5, iclass 17, count 2 2006.189.07:38:18.14#ibcon#about to read 6, iclass 17, count 2 2006.189.07:38:18.14#ibcon#read 6, iclass 17, count 2 2006.189.07:38:18.14#ibcon#end of sib2, iclass 17, count 2 2006.189.07:38:18.14#ibcon#*after write, iclass 17, count 2 2006.189.07:38:18.14#ibcon#*before return 0, iclass 17, count 2 2006.189.07:38:18.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:18.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:18.14#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.07:38:18.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:18.14#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:18.26#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:18.26#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:18.26#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:38:18.26#ibcon#first serial, iclass 17, count 0 2006.189.07:38:18.26#ibcon#enter sib2, iclass 17, count 0 2006.189.07:38:18.26#ibcon#flushed, iclass 17, count 0 2006.189.07:38:18.26#ibcon#about to write, iclass 17, count 0 2006.189.07:38:18.26#ibcon#wrote, iclass 17, count 0 2006.189.07:38:18.26#ibcon#about to read 3, iclass 17, count 0 2006.189.07:38:18.28#ibcon#read 3, iclass 17, count 0 2006.189.07:38:18.28#ibcon#about to read 4, iclass 17, count 0 2006.189.07:38:18.28#ibcon#read 4, iclass 17, count 0 2006.189.07:38:18.28#ibcon#about to read 5, iclass 17, count 0 2006.189.07:38:18.28#ibcon#read 5, iclass 17, count 0 2006.189.07:38:18.28#ibcon#about to read 6, iclass 17, count 0 2006.189.07:38:18.28#ibcon#read 6, iclass 17, count 0 2006.189.07:38:18.28#ibcon#end of sib2, iclass 17, count 0 2006.189.07:38:18.28#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:38:18.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:38:18.28#ibcon#[25=USB\r\n] 2006.189.07:38:18.28#ibcon#*before write, iclass 17, count 0 2006.189.07:38:18.28#ibcon#enter sib2, iclass 17, count 0 2006.189.07:38:18.28#ibcon#flushed, iclass 17, count 0 2006.189.07:38:18.28#ibcon#about to write, iclass 17, count 0 2006.189.07:38:18.28#ibcon#wrote, iclass 17, count 0 2006.189.07:38:18.28#ibcon#about to read 3, iclass 17, count 0 2006.189.07:38:18.31#ibcon#read 3, iclass 17, count 0 2006.189.07:38:18.31#ibcon#about to read 4, iclass 17, count 0 2006.189.07:38:18.31#ibcon#read 4, iclass 17, count 0 2006.189.07:38:18.31#ibcon#about to read 5, iclass 17, count 0 2006.189.07:38:18.31#ibcon#read 5, iclass 17, count 0 2006.189.07:38:18.31#ibcon#about to read 6, iclass 17, count 0 2006.189.07:38:18.31#ibcon#read 6, iclass 17, count 0 2006.189.07:38:18.31#ibcon#end of sib2, iclass 17, count 0 2006.189.07:38:18.31#ibcon#*after write, iclass 17, count 0 2006.189.07:38:18.31#ibcon#*before return 0, iclass 17, count 0 2006.189.07:38:18.31#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:18.31#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:18.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:38:18.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:38:18.31$vc4f8/valo=2,572.99 2006.189.07:38:18.31#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.07:38:18.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.07:38:18.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:18.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:18.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:18.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:18.31#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:38:18.31#ibcon#first serial, iclass 19, count 0 2006.189.07:38:18.31#ibcon#enter sib2, iclass 19, count 0 2006.189.07:38:18.31#ibcon#flushed, iclass 19, count 0 2006.189.07:38:18.31#ibcon#about to write, iclass 19, count 0 2006.189.07:38:18.31#ibcon#wrote, iclass 19, count 0 2006.189.07:38:18.31#ibcon#about to read 3, iclass 19, count 0 2006.189.07:38:18.33#ibcon#read 3, iclass 19, count 0 2006.189.07:38:18.33#ibcon#about to read 4, iclass 19, count 0 2006.189.07:38:18.33#ibcon#read 4, iclass 19, count 0 2006.189.07:38:18.33#ibcon#about to read 5, iclass 19, count 0 2006.189.07:38:18.33#ibcon#read 5, iclass 19, count 0 2006.189.07:38:18.33#ibcon#about to read 6, iclass 19, count 0 2006.189.07:38:18.33#ibcon#read 6, iclass 19, count 0 2006.189.07:38:18.33#ibcon#end of sib2, iclass 19, count 0 2006.189.07:38:18.33#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:38:18.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:38:18.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:38:18.33#ibcon#*before write, iclass 19, count 0 2006.189.07:38:18.33#ibcon#enter sib2, iclass 19, count 0 2006.189.07:38:18.33#ibcon#flushed, iclass 19, count 0 2006.189.07:38:18.33#ibcon#about to write, iclass 19, count 0 2006.189.07:38:18.33#ibcon#wrote, iclass 19, count 0 2006.189.07:38:18.33#ibcon#about to read 3, iclass 19, count 0 2006.189.07:38:18.38#ibcon#read 3, iclass 19, count 0 2006.189.07:38:18.38#ibcon#about to read 4, iclass 19, count 0 2006.189.07:38:18.38#ibcon#read 4, iclass 19, count 0 2006.189.07:38:18.38#ibcon#about to read 5, iclass 19, count 0 2006.189.07:38:18.38#ibcon#read 5, iclass 19, count 0 2006.189.07:38:18.38#ibcon#about to read 6, iclass 19, count 0 2006.189.07:38:18.38#ibcon#read 6, iclass 19, count 0 2006.189.07:38:18.38#ibcon#end of sib2, iclass 19, count 0 2006.189.07:38:18.38#ibcon#*after write, iclass 19, count 0 2006.189.07:38:18.38#ibcon#*before return 0, iclass 19, count 0 2006.189.07:38:18.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:18.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:18.38#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:38:18.38#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:38:18.38$vc4f8/va=2,7 2006.189.07:38:18.38#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.07:38:18.38#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.07:38:18.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:18.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:18.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:18.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:18.42#ibcon#enter wrdev, iclass 21, count 2 2006.189.07:38:18.42#ibcon#first serial, iclass 21, count 2 2006.189.07:38:18.42#ibcon#enter sib2, iclass 21, count 2 2006.189.07:38:18.42#ibcon#flushed, iclass 21, count 2 2006.189.07:38:18.42#ibcon#about to write, iclass 21, count 2 2006.189.07:38:18.42#ibcon#wrote, iclass 21, count 2 2006.189.07:38:18.42#ibcon#about to read 3, iclass 21, count 2 2006.189.07:38:18.44#ibcon#read 3, iclass 21, count 2 2006.189.07:38:18.44#ibcon#about to read 4, iclass 21, count 2 2006.189.07:38:18.44#ibcon#read 4, iclass 21, count 2 2006.189.07:38:18.44#ibcon#about to read 5, iclass 21, count 2 2006.189.07:38:18.44#ibcon#read 5, iclass 21, count 2 2006.189.07:38:18.44#ibcon#about to read 6, iclass 21, count 2 2006.189.07:38:18.44#ibcon#read 6, iclass 21, count 2 2006.189.07:38:18.44#ibcon#end of sib2, iclass 21, count 2 2006.189.07:38:18.44#ibcon#*mode == 0, iclass 21, count 2 2006.189.07:38:18.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.07:38:18.44#ibcon#[25=AT02-07\r\n] 2006.189.07:38:18.44#ibcon#*before write, iclass 21, count 2 2006.189.07:38:18.44#ibcon#enter sib2, iclass 21, count 2 2006.189.07:38:18.44#ibcon#flushed, iclass 21, count 2 2006.189.07:38:18.44#ibcon#about to write, iclass 21, count 2 2006.189.07:38:18.44#ibcon#wrote, iclass 21, count 2 2006.189.07:38:18.44#ibcon#about to read 3, iclass 21, count 2 2006.189.07:38:18.47#ibcon#read 3, iclass 21, count 2 2006.189.07:38:18.47#ibcon#about to read 4, iclass 21, count 2 2006.189.07:38:18.47#ibcon#read 4, iclass 21, count 2 2006.189.07:38:18.47#ibcon#about to read 5, iclass 21, count 2 2006.189.07:38:18.47#ibcon#read 5, iclass 21, count 2 2006.189.07:38:18.47#ibcon#about to read 6, iclass 21, count 2 2006.189.07:38:18.47#ibcon#read 6, iclass 21, count 2 2006.189.07:38:18.47#ibcon#end of sib2, iclass 21, count 2 2006.189.07:38:18.47#ibcon#*after write, iclass 21, count 2 2006.189.07:38:18.47#ibcon#*before return 0, iclass 21, count 2 2006.189.07:38:18.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:18.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:18.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.07:38:18.47#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:18.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:18.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:18.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:18.59#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:38:18.59#ibcon#first serial, iclass 21, count 0 2006.189.07:38:18.59#ibcon#enter sib2, iclass 21, count 0 2006.189.07:38:18.59#ibcon#flushed, iclass 21, count 0 2006.189.07:38:18.59#ibcon#about to write, iclass 21, count 0 2006.189.07:38:18.59#ibcon#wrote, iclass 21, count 0 2006.189.07:38:18.59#ibcon#about to read 3, iclass 21, count 0 2006.189.07:38:18.61#ibcon#read 3, iclass 21, count 0 2006.189.07:38:18.61#ibcon#about to read 4, iclass 21, count 0 2006.189.07:38:18.61#ibcon#read 4, iclass 21, count 0 2006.189.07:38:18.61#ibcon#about to read 5, iclass 21, count 0 2006.189.07:38:18.61#ibcon#read 5, iclass 21, count 0 2006.189.07:38:18.61#ibcon#about to read 6, iclass 21, count 0 2006.189.07:38:18.61#ibcon#read 6, iclass 21, count 0 2006.189.07:38:18.61#ibcon#end of sib2, iclass 21, count 0 2006.189.07:38:18.61#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:38:18.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:38:18.61#ibcon#[25=USB\r\n] 2006.189.07:38:18.61#ibcon#*before write, iclass 21, count 0 2006.189.07:38:18.61#ibcon#enter sib2, iclass 21, count 0 2006.189.07:38:18.61#ibcon#flushed, iclass 21, count 0 2006.189.07:38:18.61#ibcon#about to write, iclass 21, count 0 2006.189.07:38:18.61#ibcon#wrote, iclass 21, count 0 2006.189.07:38:18.61#ibcon#about to read 3, iclass 21, count 0 2006.189.07:38:18.64#ibcon#read 3, iclass 21, count 0 2006.189.07:38:18.64#ibcon#about to read 4, iclass 21, count 0 2006.189.07:38:18.64#ibcon#read 4, iclass 21, count 0 2006.189.07:38:18.64#ibcon#about to read 5, iclass 21, count 0 2006.189.07:38:18.64#ibcon#read 5, iclass 21, count 0 2006.189.07:38:18.64#ibcon#about to read 6, iclass 21, count 0 2006.189.07:38:18.64#ibcon#read 6, iclass 21, count 0 2006.189.07:38:18.64#ibcon#end of sib2, iclass 21, count 0 2006.189.07:38:18.64#ibcon#*after write, iclass 21, count 0 2006.189.07:38:18.64#ibcon#*before return 0, iclass 21, count 0 2006.189.07:38:18.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:18.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:18.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:38:18.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:38:18.64$vc4f8/valo=3,672.99 2006.189.07:38:18.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.07:38:18.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.07:38:18.64#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:18.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:18.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:18.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:18.64#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:38:18.64#ibcon#first serial, iclass 23, count 0 2006.189.07:38:18.64#ibcon#enter sib2, iclass 23, count 0 2006.189.07:38:18.64#ibcon#flushed, iclass 23, count 0 2006.189.07:38:18.64#ibcon#about to write, iclass 23, count 0 2006.189.07:38:18.64#ibcon#wrote, iclass 23, count 0 2006.189.07:38:18.64#ibcon#about to read 3, iclass 23, count 0 2006.189.07:38:18.66#ibcon#read 3, iclass 23, count 0 2006.189.07:38:18.66#ibcon#about to read 4, iclass 23, count 0 2006.189.07:38:18.66#ibcon#read 4, iclass 23, count 0 2006.189.07:38:18.66#ibcon#about to read 5, iclass 23, count 0 2006.189.07:38:18.66#ibcon#read 5, iclass 23, count 0 2006.189.07:38:18.66#ibcon#about to read 6, iclass 23, count 0 2006.189.07:38:18.66#ibcon#read 6, iclass 23, count 0 2006.189.07:38:18.66#ibcon#end of sib2, iclass 23, count 0 2006.189.07:38:18.66#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:38:18.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:38:18.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:38:18.66#ibcon#*before write, iclass 23, count 0 2006.189.07:38:18.66#ibcon#enter sib2, iclass 23, count 0 2006.189.07:38:18.66#ibcon#flushed, iclass 23, count 0 2006.189.07:38:18.66#ibcon#about to write, iclass 23, count 0 2006.189.07:38:18.66#ibcon#wrote, iclass 23, count 0 2006.189.07:38:18.66#ibcon#about to read 3, iclass 23, count 0 2006.189.07:38:18.71#ibcon#read 3, iclass 23, count 0 2006.189.07:38:18.71#ibcon#about to read 4, iclass 23, count 0 2006.189.07:38:18.71#ibcon#read 4, iclass 23, count 0 2006.189.07:38:18.71#ibcon#about to read 5, iclass 23, count 0 2006.189.07:38:18.71#ibcon#read 5, iclass 23, count 0 2006.189.07:38:18.71#ibcon#about to read 6, iclass 23, count 0 2006.189.07:38:18.71#ibcon#read 6, iclass 23, count 0 2006.189.07:38:18.71#ibcon#end of sib2, iclass 23, count 0 2006.189.07:38:18.71#ibcon#*after write, iclass 23, count 0 2006.189.07:38:18.71#ibcon#*before return 0, iclass 23, count 0 2006.189.07:38:18.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:18.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:18.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:38:18.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:38:18.71$vc4f8/va=3,6 2006.189.07:38:18.71#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.07:38:18.71#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.07:38:18.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:18.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:18.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:18.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:18.75#ibcon#enter wrdev, iclass 25, count 2 2006.189.07:38:18.75#ibcon#first serial, iclass 25, count 2 2006.189.07:38:18.75#ibcon#enter sib2, iclass 25, count 2 2006.189.07:38:18.75#ibcon#flushed, iclass 25, count 2 2006.189.07:38:18.75#ibcon#about to write, iclass 25, count 2 2006.189.07:38:18.75#ibcon#wrote, iclass 25, count 2 2006.189.07:38:18.75#ibcon#about to read 3, iclass 25, count 2 2006.189.07:38:18.77#ibcon#read 3, iclass 25, count 2 2006.189.07:38:18.77#ibcon#about to read 4, iclass 25, count 2 2006.189.07:38:18.77#ibcon#read 4, iclass 25, count 2 2006.189.07:38:18.77#ibcon#about to read 5, iclass 25, count 2 2006.189.07:38:18.77#ibcon#read 5, iclass 25, count 2 2006.189.07:38:18.77#ibcon#about to read 6, iclass 25, count 2 2006.189.07:38:18.77#ibcon#read 6, iclass 25, count 2 2006.189.07:38:18.77#ibcon#end of sib2, iclass 25, count 2 2006.189.07:38:18.77#ibcon#*mode == 0, iclass 25, count 2 2006.189.07:38:18.77#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.07:38:18.77#ibcon#[25=AT03-06\r\n] 2006.189.07:38:18.77#ibcon#*before write, iclass 25, count 2 2006.189.07:38:18.77#ibcon#enter sib2, iclass 25, count 2 2006.189.07:38:18.77#ibcon#flushed, iclass 25, count 2 2006.189.07:38:18.77#ibcon#about to write, iclass 25, count 2 2006.189.07:38:18.77#ibcon#wrote, iclass 25, count 2 2006.189.07:38:18.77#ibcon#about to read 3, iclass 25, count 2 2006.189.07:38:18.80#ibcon#read 3, iclass 25, count 2 2006.189.07:38:18.80#ibcon#about to read 4, iclass 25, count 2 2006.189.07:38:18.80#ibcon#read 4, iclass 25, count 2 2006.189.07:38:18.80#ibcon#about to read 5, iclass 25, count 2 2006.189.07:38:18.80#ibcon#read 5, iclass 25, count 2 2006.189.07:38:18.80#ibcon#about to read 6, iclass 25, count 2 2006.189.07:38:18.80#ibcon#read 6, iclass 25, count 2 2006.189.07:38:18.80#ibcon#end of sib2, iclass 25, count 2 2006.189.07:38:18.80#ibcon#*after write, iclass 25, count 2 2006.189.07:38:18.80#ibcon#*before return 0, iclass 25, count 2 2006.189.07:38:18.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:18.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:18.80#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.07:38:18.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:18.80#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:18.92#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:18.92#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:18.92#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:38:18.92#ibcon#first serial, iclass 25, count 0 2006.189.07:38:18.92#ibcon#enter sib2, iclass 25, count 0 2006.189.07:38:18.92#ibcon#flushed, iclass 25, count 0 2006.189.07:38:18.92#ibcon#about to write, iclass 25, count 0 2006.189.07:38:18.92#ibcon#wrote, iclass 25, count 0 2006.189.07:38:18.92#ibcon#about to read 3, iclass 25, count 0 2006.189.07:38:18.94#ibcon#read 3, iclass 25, count 0 2006.189.07:38:18.94#ibcon#about to read 4, iclass 25, count 0 2006.189.07:38:18.94#ibcon#read 4, iclass 25, count 0 2006.189.07:38:18.94#ibcon#about to read 5, iclass 25, count 0 2006.189.07:38:18.94#ibcon#read 5, iclass 25, count 0 2006.189.07:38:18.94#ibcon#about to read 6, iclass 25, count 0 2006.189.07:38:18.94#ibcon#read 6, iclass 25, count 0 2006.189.07:38:18.94#ibcon#end of sib2, iclass 25, count 0 2006.189.07:38:18.94#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:38:18.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:38:18.94#ibcon#[25=USB\r\n] 2006.189.07:38:18.94#ibcon#*before write, iclass 25, count 0 2006.189.07:38:18.94#ibcon#enter sib2, iclass 25, count 0 2006.189.07:38:18.94#ibcon#flushed, iclass 25, count 0 2006.189.07:38:18.94#ibcon#about to write, iclass 25, count 0 2006.189.07:38:18.94#ibcon#wrote, iclass 25, count 0 2006.189.07:38:18.94#ibcon#about to read 3, iclass 25, count 0 2006.189.07:38:18.97#ibcon#read 3, iclass 25, count 0 2006.189.07:38:18.97#ibcon#about to read 4, iclass 25, count 0 2006.189.07:38:18.97#ibcon#read 4, iclass 25, count 0 2006.189.07:38:18.97#ibcon#about to read 5, iclass 25, count 0 2006.189.07:38:18.97#ibcon#read 5, iclass 25, count 0 2006.189.07:38:18.97#ibcon#about to read 6, iclass 25, count 0 2006.189.07:38:18.97#ibcon#read 6, iclass 25, count 0 2006.189.07:38:18.97#ibcon#end of sib2, iclass 25, count 0 2006.189.07:38:18.97#ibcon#*after write, iclass 25, count 0 2006.189.07:38:18.97#ibcon#*before return 0, iclass 25, count 0 2006.189.07:38:18.97#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:18.97#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:18.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:38:18.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:38:18.97$vc4f8/valo=4,832.99 2006.189.07:38:18.97#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.07:38:18.97#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.07:38:18.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:18.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:18.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:18.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:18.97#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:38:18.97#ibcon#first serial, iclass 27, count 0 2006.189.07:38:18.97#ibcon#enter sib2, iclass 27, count 0 2006.189.07:38:18.97#ibcon#flushed, iclass 27, count 0 2006.189.07:38:18.97#ibcon#about to write, iclass 27, count 0 2006.189.07:38:18.97#ibcon#wrote, iclass 27, count 0 2006.189.07:38:18.97#ibcon#about to read 3, iclass 27, count 0 2006.189.07:38:18.99#ibcon#read 3, iclass 27, count 0 2006.189.07:38:18.99#ibcon#about to read 4, iclass 27, count 0 2006.189.07:38:18.99#ibcon#read 4, iclass 27, count 0 2006.189.07:38:18.99#ibcon#about to read 5, iclass 27, count 0 2006.189.07:38:18.99#ibcon#read 5, iclass 27, count 0 2006.189.07:38:18.99#ibcon#about to read 6, iclass 27, count 0 2006.189.07:38:18.99#ibcon#read 6, iclass 27, count 0 2006.189.07:38:18.99#ibcon#end of sib2, iclass 27, count 0 2006.189.07:38:18.99#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:38:18.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:38:18.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:38:18.99#ibcon#*before write, iclass 27, count 0 2006.189.07:38:18.99#ibcon#enter sib2, iclass 27, count 0 2006.189.07:38:18.99#ibcon#flushed, iclass 27, count 0 2006.189.07:38:18.99#ibcon#about to write, iclass 27, count 0 2006.189.07:38:18.99#ibcon#wrote, iclass 27, count 0 2006.189.07:38:18.99#ibcon#about to read 3, iclass 27, count 0 2006.189.07:38:19.03#ibcon#read 3, iclass 27, count 0 2006.189.07:38:19.03#ibcon#about to read 4, iclass 27, count 0 2006.189.07:38:19.03#ibcon#read 4, iclass 27, count 0 2006.189.07:38:19.03#ibcon#about to read 5, iclass 27, count 0 2006.189.07:38:19.03#ibcon#read 5, iclass 27, count 0 2006.189.07:38:19.03#ibcon#about to read 6, iclass 27, count 0 2006.189.07:38:19.03#ibcon#read 6, iclass 27, count 0 2006.189.07:38:19.03#ibcon#end of sib2, iclass 27, count 0 2006.189.07:38:19.03#ibcon#*after write, iclass 27, count 0 2006.189.07:38:19.03#ibcon#*before return 0, iclass 27, count 0 2006.189.07:38:19.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:19.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:19.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:38:19.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:38:19.03$vc4f8/va=4,7 2006.189.07:38:19.03#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.07:38:19.03#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.07:38:19.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:19.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:19.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:19.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:19.09#ibcon#enter wrdev, iclass 29, count 2 2006.189.07:38:19.09#ibcon#first serial, iclass 29, count 2 2006.189.07:38:19.09#ibcon#enter sib2, iclass 29, count 2 2006.189.07:38:19.09#ibcon#flushed, iclass 29, count 2 2006.189.07:38:19.09#ibcon#about to write, iclass 29, count 2 2006.189.07:38:19.09#ibcon#wrote, iclass 29, count 2 2006.189.07:38:19.09#ibcon#about to read 3, iclass 29, count 2 2006.189.07:38:19.11#ibcon#read 3, iclass 29, count 2 2006.189.07:38:19.11#ibcon#about to read 4, iclass 29, count 2 2006.189.07:38:19.11#ibcon#read 4, iclass 29, count 2 2006.189.07:38:19.11#ibcon#about to read 5, iclass 29, count 2 2006.189.07:38:19.11#ibcon#read 5, iclass 29, count 2 2006.189.07:38:19.11#ibcon#about to read 6, iclass 29, count 2 2006.189.07:38:19.11#ibcon#read 6, iclass 29, count 2 2006.189.07:38:19.11#ibcon#end of sib2, iclass 29, count 2 2006.189.07:38:19.11#ibcon#*mode == 0, iclass 29, count 2 2006.189.07:38:19.11#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.07:38:19.11#ibcon#[25=AT04-07\r\n] 2006.189.07:38:19.11#ibcon#*before write, iclass 29, count 2 2006.189.07:38:19.11#ibcon#enter sib2, iclass 29, count 2 2006.189.07:38:19.11#ibcon#flushed, iclass 29, count 2 2006.189.07:38:19.11#ibcon#about to write, iclass 29, count 2 2006.189.07:38:19.11#ibcon#wrote, iclass 29, count 2 2006.189.07:38:19.11#ibcon#about to read 3, iclass 29, count 2 2006.189.07:38:19.14#ibcon#read 3, iclass 29, count 2 2006.189.07:38:19.14#ibcon#about to read 4, iclass 29, count 2 2006.189.07:38:19.14#ibcon#read 4, iclass 29, count 2 2006.189.07:38:19.14#ibcon#about to read 5, iclass 29, count 2 2006.189.07:38:19.14#ibcon#read 5, iclass 29, count 2 2006.189.07:38:19.14#ibcon#about to read 6, iclass 29, count 2 2006.189.07:38:19.14#ibcon#read 6, iclass 29, count 2 2006.189.07:38:19.14#ibcon#end of sib2, iclass 29, count 2 2006.189.07:38:19.14#ibcon#*after write, iclass 29, count 2 2006.189.07:38:19.14#ibcon#*before return 0, iclass 29, count 2 2006.189.07:38:19.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:19.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:19.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.07:38:19.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:19.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:19.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:19.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:19.26#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:38:19.26#ibcon#first serial, iclass 29, count 0 2006.189.07:38:19.26#ibcon#enter sib2, iclass 29, count 0 2006.189.07:38:19.26#ibcon#flushed, iclass 29, count 0 2006.189.07:38:19.26#ibcon#about to write, iclass 29, count 0 2006.189.07:38:19.26#ibcon#wrote, iclass 29, count 0 2006.189.07:38:19.26#ibcon#about to read 3, iclass 29, count 0 2006.189.07:38:19.28#ibcon#read 3, iclass 29, count 0 2006.189.07:38:19.28#ibcon#about to read 4, iclass 29, count 0 2006.189.07:38:19.28#ibcon#read 4, iclass 29, count 0 2006.189.07:38:19.28#ibcon#about to read 5, iclass 29, count 0 2006.189.07:38:19.28#ibcon#read 5, iclass 29, count 0 2006.189.07:38:19.28#ibcon#about to read 6, iclass 29, count 0 2006.189.07:38:19.28#ibcon#read 6, iclass 29, count 0 2006.189.07:38:19.28#ibcon#end of sib2, iclass 29, count 0 2006.189.07:38:19.28#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:38:19.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:38:19.28#ibcon#[25=USB\r\n] 2006.189.07:38:19.28#ibcon#*before write, iclass 29, count 0 2006.189.07:38:19.28#ibcon#enter sib2, iclass 29, count 0 2006.189.07:38:19.28#ibcon#flushed, iclass 29, count 0 2006.189.07:38:19.28#ibcon#about to write, iclass 29, count 0 2006.189.07:38:19.28#ibcon#wrote, iclass 29, count 0 2006.189.07:38:19.28#ibcon#about to read 3, iclass 29, count 0 2006.189.07:38:19.31#ibcon#read 3, iclass 29, count 0 2006.189.07:38:19.31#ibcon#about to read 4, iclass 29, count 0 2006.189.07:38:19.31#ibcon#read 4, iclass 29, count 0 2006.189.07:38:19.31#ibcon#about to read 5, iclass 29, count 0 2006.189.07:38:19.31#ibcon#read 5, iclass 29, count 0 2006.189.07:38:19.31#ibcon#about to read 6, iclass 29, count 0 2006.189.07:38:19.31#ibcon#read 6, iclass 29, count 0 2006.189.07:38:19.31#ibcon#end of sib2, iclass 29, count 0 2006.189.07:38:19.31#ibcon#*after write, iclass 29, count 0 2006.189.07:38:19.31#ibcon#*before return 0, iclass 29, count 0 2006.189.07:38:19.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:19.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:19.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:38:19.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:38:19.31$vc4f8/valo=5,652.99 2006.189.07:38:19.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.07:38:19.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.07:38:19.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:19.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:19.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:19.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:19.31#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:38:19.31#ibcon#first serial, iclass 31, count 0 2006.189.07:38:19.31#ibcon#enter sib2, iclass 31, count 0 2006.189.07:38:19.31#ibcon#flushed, iclass 31, count 0 2006.189.07:38:19.31#ibcon#about to write, iclass 31, count 0 2006.189.07:38:19.31#ibcon#wrote, iclass 31, count 0 2006.189.07:38:19.31#ibcon#about to read 3, iclass 31, count 0 2006.189.07:38:19.33#ibcon#read 3, iclass 31, count 0 2006.189.07:38:19.33#ibcon#about to read 4, iclass 31, count 0 2006.189.07:38:19.33#ibcon#read 4, iclass 31, count 0 2006.189.07:38:19.33#ibcon#about to read 5, iclass 31, count 0 2006.189.07:38:19.33#ibcon#read 5, iclass 31, count 0 2006.189.07:38:19.33#ibcon#about to read 6, iclass 31, count 0 2006.189.07:38:19.33#ibcon#read 6, iclass 31, count 0 2006.189.07:38:19.33#ibcon#end of sib2, iclass 31, count 0 2006.189.07:38:19.33#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:38:19.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:38:19.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:38:19.33#ibcon#*before write, iclass 31, count 0 2006.189.07:38:19.33#ibcon#enter sib2, iclass 31, count 0 2006.189.07:38:19.33#ibcon#flushed, iclass 31, count 0 2006.189.07:38:19.33#ibcon#about to write, iclass 31, count 0 2006.189.07:38:19.33#ibcon#wrote, iclass 31, count 0 2006.189.07:38:19.33#ibcon#about to read 3, iclass 31, count 0 2006.189.07:38:19.37#ibcon#read 3, iclass 31, count 0 2006.189.07:38:19.37#ibcon#about to read 4, iclass 31, count 0 2006.189.07:38:19.37#ibcon#read 4, iclass 31, count 0 2006.189.07:38:19.37#ibcon#about to read 5, iclass 31, count 0 2006.189.07:38:19.37#ibcon#read 5, iclass 31, count 0 2006.189.07:38:19.37#ibcon#about to read 6, iclass 31, count 0 2006.189.07:38:19.37#ibcon#read 6, iclass 31, count 0 2006.189.07:38:19.37#ibcon#end of sib2, iclass 31, count 0 2006.189.07:38:19.37#ibcon#*after write, iclass 31, count 0 2006.189.07:38:19.37#ibcon#*before return 0, iclass 31, count 0 2006.189.07:38:19.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:19.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:19.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:38:19.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:38:19.37$vc4f8/va=5,7 2006.189.07:38:19.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.07:38:19.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.07:38:19.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:19.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:19.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:19.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:19.43#ibcon#enter wrdev, iclass 33, count 2 2006.189.07:38:19.43#ibcon#first serial, iclass 33, count 2 2006.189.07:38:19.43#ibcon#enter sib2, iclass 33, count 2 2006.189.07:38:19.43#ibcon#flushed, iclass 33, count 2 2006.189.07:38:19.43#ibcon#about to write, iclass 33, count 2 2006.189.07:38:19.43#ibcon#wrote, iclass 33, count 2 2006.189.07:38:19.43#ibcon#about to read 3, iclass 33, count 2 2006.189.07:38:19.45#ibcon#read 3, iclass 33, count 2 2006.189.07:38:19.45#ibcon#about to read 4, iclass 33, count 2 2006.189.07:38:19.45#ibcon#read 4, iclass 33, count 2 2006.189.07:38:19.45#ibcon#about to read 5, iclass 33, count 2 2006.189.07:38:19.45#ibcon#read 5, iclass 33, count 2 2006.189.07:38:19.45#ibcon#about to read 6, iclass 33, count 2 2006.189.07:38:19.45#ibcon#read 6, iclass 33, count 2 2006.189.07:38:19.45#ibcon#end of sib2, iclass 33, count 2 2006.189.07:38:19.45#ibcon#*mode == 0, iclass 33, count 2 2006.189.07:38:19.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.07:38:19.45#ibcon#[25=AT05-07\r\n] 2006.189.07:38:19.45#ibcon#*before write, iclass 33, count 2 2006.189.07:38:19.45#ibcon#enter sib2, iclass 33, count 2 2006.189.07:38:19.45#ibcon#flushed, iclass 33, count 2 2006.189.07:38:19.45#ibcon#about to write, iclass 33, count 2 2006.189.07:38:19.45#ibcon#wrote, iclass 33, count 2 2006.189.07:38:19.45#ibcon#about to read 3, iclass 33, count 2 2006.189.07:38:19.48#ibcon#read 3, iclass 33, count 2 2006.189.07:38:19.48#ibcon#about to read 4, iclass 33, count 2 2006.189.07:38:19.48#ibcon#read 4, iclass 33, count 2 2006.189.07:38:19.48#ibcon#about to read 5, iclass 33, count 2 2006.189.07:38:19.48#ibcon#read 5, iclass 33, count 2 2006.189.07:38:19.48#ibcon#about to read 6, iclass 33, count 2 2006.189.07:38:19.48#ibcon#read 6, iclass 33, count 2 2006.189.07:38:19.48#ibcon#end of sib2, iclass 33, count 2 2006.189.07:38:19.48#ibcon#*after write, iclass 33, count 2 2006.189.07:38:19.48#ibcon#*before return 0, iclass 33, count 2 2006.189.07:38:19.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:19.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:19.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.07:38:19.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:19.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:19.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:19.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:19.60#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:38:19.60#ibcon#first serial, iclass 33, count 0 2006.189.07:38:19.60#ibcon#enter sib2, iclass 33, count 0 2006.189.07:38:19.60#ibcon#flushed, iclass 33, count 0 2006.189.07:38:19.60#ibcon#about to write, iclass 33, count 0 2006.189.07:38:19.60#ibcon#wrote, iclass 33, count 0 2006.189.07:38:19.60#ibcon#about to read 3, iclass 33, count 0 2006.189.07:38:19.62#ibcon#read 3, iclass 33, count 0 2006.189.07:38:19.62#ibcon#about to read 4, iclass 33, count 0 2006.189.07:38:19.62#ibcon#read 4, iclass 33, count 0 2006.189.07:38:19.62#ibcon#about to read 5, iclass 33, count 0 2006.189.07:38:19.62#ibcon#read 5, iclass 33, count 0 2006.189.07:38:19.62#ibcon#about to read 6, iclass 33, count 0 2006.189.07:38:19.62#ibcon#read 6, iclass 33, count 0 2006.189.07:38:19.62#ibcon#end of sib2, iclass 33, count 0 2006.189.07:38:19.62#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:38:19.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:38:19.62#ibcon#[25=USB\r\n] 2006.189.07:38:19.62#ibcon#*before write, iclass 33, count 0 2006.189.07:38:19.62#ibcon#enter sib2, iclass 33, count 0 2006.189.07:38:19.62#ibcon#flushed, iclass 33, count 0 2006.189.07:38:19.62#ibcon#about to write, iclass 33, count 0 2006.189.07:38:19.62#ibcon#wrote, iclass 33, count 0 2006.189.07:38:19.62#ibcon#about to read 3, iclass 33, count 0 2006.189.07:38:19.65#ibcon#read 3, iclass 33, count 0 2006.189.07:38:19.65#ibcon#about to read 4, iclass 33, count 0 2006.189.07:38:19.65#ibcon#read 4, iclass 33, count 0 2006.189.07:38:19.65#ibcon#about to read 5, iclass 33, count 0 2006.189.07:38:19.65#ibcon#read 5, iclass 33, count 0 2006.189.07:38:19.65#ibcon#about to read 6, iclass 33, count 0 2006.189.07:38:19.65#ibcon#read 6, iclass 33, count 0 2006.189.07:38:19.65#ibcon#end of sib2, iclass 33, count 0 2006.189.07:38:19.65#ibcon#*after write, iclass 33, count 0 2006.189.07:38:19.65#ibcon#*before return 0, iclass 33, count 0 2006.189.07:38:19.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:19.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:19.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:38:19.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:38:19.65$vc4f8/valo=6,772.99 2006.189.07:38:19.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.07:38:19.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.07:38:19.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:19.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:19.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:19.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:19.65#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:38:19.65#ibcon#first serial, iclass 35, count 0 2006.189.07:38:19.65#ibcon#enter sib2, iclass 35, count 0 2006.189.07:38:19.65#ibcon#flushed, iclass 35, count 0 2006.189.07:38:19.65#ibcon#about to write, iclass 35, count 0 2006.189.07:38:19.65#ibcon#wrote, iclass 35, count 0 2006.189.07:38:19.65#ibcon#about to read 3, iclass 35, count 0 2006.189.07:38:19.67#ibcon#read 3, iclass 35, count 0 2006.189.07:38:19.67#ibcon#about to read 4, iclass 35, count 0 2006.189.07:38:19.67#ibcon#read 4, iclass 35, count 0 2006.189.07:38:19.67#ibcon#about to read 5, iclass 35, count 0 2006.189.07:38:19.67#ibcon#read 5, iclass 35, count 0 2006.189.07:38:19.67#ibcon#about to read 6, iclass 35, count 0 2006.189.07:38:19.67#ibcon#read 6, iclass 35, count 0 2006.189.07:38:19.67#ibcon#end of sib2, iclass 35, count 0 2006.189.07:38:19.67#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:38:19.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:38:19.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:38:19.67#ibcon#*before write, iclass 35, count 0 2006.189.07:38:19.67#ibcon#enter sib2, iclass 35, count 0 2006.189.07:38:19.67#ibcon#flushed, iclass 35, count 0 2006.189.07:38:19.67#ibcon#about to write, iclass 35, count 0 2006.189.07:38:19.67#ibcon#wrote, iclass 35, count 0 2006.189.07:38:19.67#ibcon#about to read 3, iclass 35, count 0 2006.189.07:38:19.71#ibcon#read 3, iclass 35, count 0 2006.189.07:38:19.71#ibcon#about to read 4, iclass 35, count 0 2006.189.07:38:19.71#ibcon#read 4, iclass 35, count 0 2006.189.07:38:19.71#ibcon#about to read 5, iclass 35, count 0 2006.189.07:38:19.71#ibcon#read 5, iclass 35, count 0 2006.189.07:38:19.71#ibcon#about to read 6, iclass 35, count 0 2006.189.07:38:19.71#ibcon#read 6, iclass 35, count 0 2006.189.07:38:19.71#ibcon#end of sib2, iclass 35, count 0 2006.189.07:38:19.71#ibcon#*after write, iclass 35, count 0 2006.189.07:38:19.71#ibcon#*before return 0, iclass 35, count 0 2006.189.07:38:19.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:19.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:19.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:38:19.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:38:19.71$vc4f8/va=6,6 2006.189.07:38:19.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.07:38:19.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.07:38:19.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:19.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:38:19.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:38:19.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:38:19.77#ibcon#enter wrdev, iclass 37, count 2 2006.189.07:38:19.77#ibcon#first serial, iclass 37, count 2 2006.189.07:38:19.77#ibcon#enter sib2, iclass 37, count 2 2006.189.07:38:19.77#ibcon#flushed, iclass 37, count 2 2006.189.07:38:19.77#ibcon#about to write, iclass 37, count 2 2006.189.07:38:19.77#ibcon#wrote, iclass 37, count 2 2006.189.07:38:19.77#ibcon#about to read 3, iclass 37, count 2 2006.189.07:38:19.79#ibcon#read 3, iclass 37, count 2 2006.189.07:38:19.79#ibcon#about to read 4, iclass 37, count 2 2006.189.07:38:19.79#ibcon#read 4, iclass 37, count 2 2006.189.07:38:19.79#ibcon#about to read 5, iclass 37, count 2 2006.189.07:38:19.79#ibcon#read 5, iclass 37, count 2 2006.189.07:38:19.79#ibcon#about to read 6, iclass 37, count 2 2006.189.07:38:19.79#ibcon#read 6, iclass 37, count 2 2006.189.07:38:19.79#ibcon#end of sib2, iclass 37, count 2 2006.189.07:38:19.79#ibcon#*mode == 0, iclass 37, count 2 2006.189.07:38:19.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.07:38:19.79#ibcon#[25=AT06-06\r\n] 2006.189.07:38:19.79#ibcon#*before write, iclass 37, count 2 2006.189.07:38:19.79#ibcon#enter sib2, iclass 37, count 2 2006.189.07:38:19.79#ibcon#flushed, iclass 37, count 2 2006.189.07:38:19.79#ibcon#about to write, iclass 37, count 2 2006.189.07:38:19.79#ibcon#wrote, iclass 37, count 2 2006.189.07:38:19.79#ibcon#about to read 3, iclass 37, count 2 2006.189.07:38:19.82#ibcon#read 3, iclass 37, count 2 2006.189.07:38:19.82#ibcon#about to read 4, iclass 37, count 2 2006.189.07:38:19.82#ibcon#read 4, iclass 37, count 2 2006.189.07:38:19.82#ibcon#about to read 5, iclass 37, count 2 2006.189.07:38:19.82#ibcon#read 5, iclass 37, count 2 2006.189.07:38:19.82#ibcon#about to read 6, iclass 37, count 2 2006.189.07:38:19.82#ibcon#read 6, iclass 37, count 2 2006.189.07:38:19.82#ibcon#end of sib2, iclass 37, count 2 2006.189.07:38:19.82#ibcon#*after write, iclass 37, count 2 2006.189.07:38:19.82#ibcon#*before return 0, iclass 37, count 2 2006.189.07:38:19.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:38:19.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:38:19.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.07:38:19.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:19.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:38:19.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:38:19.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:38:19.94#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:38:19.94#ibcon#first serial, iclass 37, count 0 2006.189.07:38:19.94#ibcon#enter sib2, iclass 37, count 0 2006.189.07:38:19.94#ibcon#flushed, iclass 37, count 0 2006.189.07:38:19.94#ibcon#about to write, iclass 37, count 0 2006.189.07:38:19.94#ibcon#wrote, iclass 37, count 0 2006.189.07:38:19.94#ibcon#about to read 3, iclass 37, count 0 2006.189.07:38:19.96#ibcon#read 3, iclass 37, count 0 2006.189.07:38:19.96#ibcon#about to read 4, iclass 37, count 0 2006.189.07:38:19.96#ibcon#read 4, iclass 37, count 0 2006.189.07:38:19.96#ibcon#about to read 5, iclass 37, count 0 2006.189.07:38:19.96#ibcon#read 5, iclass 37, count 0 2006.189.07:38:19.96#ibcon#about to read 6, iclass 37, count 0 2006.189.07:38:19.96#ibcon#read 6, iclass 37, count 0 2006.189.07:38:19.96#ibcon#end of sib2, iclass 37, count 0 2006.189.07:38:19.96#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:38:19.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:38:19.96#ibcon#[25=USB\r\n] 2006.189.07:38:19.96#ibcon#*before write, iclass 37, count 0 2006.189.07:38:19.96#ibcon#enter sib2, iclass 37, count 0 2006.189.07:38:19.96#ibcon#flushed, iclass 37, count 0 2006.189.07:38:19.96#ibcon#about to write, iclass 37, count 0 2006.189.07:38:19.96#ibcon#wrote, iclass 37, count 0 2006.189.07:38:19.96#ibcon#about to read 3, iclass 37, count 0 2006.189.07:38:19.99#ibcon#read 3, iclass 37, count 0 2006.189.07:38:19.99#ibcon#about to read 4, iclass 37, count 0 2006.189.07:38:19.99#ibcon#read 4, iclass 37, count 0 2006.189.07:38:19.99#ibcon#about to read 5, iclass 37, count 0 2006.189.07:38:19.99#ibcon#read 5, iclass 37, count 0 2006.189.07:38:19.99#ibcon#about to read 6, iclass 37, count 0 2006.189.07:38:19.99#ibcon#read 6, iclass 37, count 0 2006.189.07:38:19.99#ibcon#end of sib2, iclass 37, count 0 2006.189.07:38:19.99#ibcon#*after write, iclass 37, count 0 2006.189.07:38:19.99#ibcon#*before return 0, iclass 37, count 0 2006.189.07:38:19.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:38:19.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:38:19.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:38:19.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:38:19.99$vc4f8/valo=7,832.99 2006.189.07:38:19.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.07:38:19.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.07:38:19.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:19.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:38:19.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:38:19.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:38:19.99#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:38:19.99#ibcon#first serial, iclass 39, count 0 2006.189.07:38:19.99#ibcon#enter sib2, iclass 39, count 0 2006.189.07:38:19.99#ibcon#flushed, iclass 39, count 0 2006.189.07:38:19.99#ibcon#about to write, iclass 39, count 0 2006.189.07:38:19.99#ibcon#wrote, iclass 39, count 0 2006.189.07:38:19.99#ibcon#about to read 3, iclass 39, count 0 2006.189.07:38:20.01#ibcon#read 3, iclass 39, count 0 2006.189.07:38:20.01#ibcon#about to read 4, iclass 39, count 0 2006.189.07:38:20.01#ibcon#read 4, iclass 39, count 0 2006.189.07:38:20.01#ibcon#about to read 5, iclass 39, count 0 2006.189.07:38:20.01#ibcon#read 5, iclass 39, count 0 2006.189.07:38:20.01#ibcon#about to read 6, iclass 39, count 0 2006.189.07:38:20.01#ibcon#read 6, iclass 39, count 0 2006.189.07:38:20.01#ibcon#end of sib2, iclass 39, count 0 2006.189.07:38:20.01#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:38:20.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:38:20.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:38:20.01#ibcon#*before write, iclass 39, count 0 2006.189.07:38:20.01#ibcon#enter sib2, iclass 39, count 0 2006.189.07:38:20.01#ibcon#flushed, iclass 39, count 0 2006.189.07:38:20.01#ibcon#about to write, iclass 39, count 0 2006.189.07:38:20.01#ibcon#wrote, iclass 39, count 0 2006.189.07:38:20.01#ibcon#about to read 3, iclass 39, count 0 2006.189.07:38:20.05#ibcon#read 3, iclass 39, count 0 2006.189.07:38:20.05#ibcon#about to read 4, iclass 39, count 0 2006.189.07:38:20.05#ibcon#read 4, iclass 39, count 0 2006.189.07:38:20.05#ibcon#about to read 5, iclass 39, count 0 2006.189.07:38:20.05#ibcon#read 5, iclass 39, count 0 2006.189.07:38:20.05#ibcon#about to read 6, iclass 39, count 0 2006.189.07:38:20.05#ibcon#read 6, iclass 39, count 0 2006.189.07:38:20.05#ibcon#end of sib2, iclass 39, count 0 2006.189.07:38:20.05#ibcon#*after write, iclass 39, count 0 2006.189.07:38:20.05#ibcon#*before return 0, iclass 39, count 0 2006.189.07:38:20.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:38:20.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:38:20.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:38:20.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:38:20.05$vc4f8/va=7,6 2006.189.07:38:20.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.07:38:20.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.07:38:20.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:20.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:38:20.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:38:20.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:38:20.11#ibcon#enter wrdev, iclass 3, count 2 2006.189.07:38:20.11#ibcon#first serial, iclass 3, count 2 2006.189.07:38:20.11#ibcon#enter sib2, iclass 3, count 2 2006.189.07:38:20.11#ibcon#flushed, iclass 3, count 2 2006.189.07:38:20.11#ibcon#about to write, iclass 3, count 2 2006.189.07:38:20.11#ibcon#wrote, iclass 3, count 2 2006.189.07:38:20.11#ibcon#about to read 3, iclass 3, count 2 2006.189.07:38:20.13#ibcon#read 3, iclass 3, count 2 2006.189.07:38:20.13#ibcon#about to read 4, iclass 3, count 2 2006.189.07:38:20.13#ibcon#read 4, iclass 3, count 2 2006.189.07:38:20.13#ibcon#about to read 5, iclass 3, count 2 2006.189.07:38:20.13#ibcon#read 5, iclass 3, count 2 2006.189.07:38:20.13#ibcon#about to read 6, iclass 3, count 2 2006.189.07:38:20.13#ibcon#read 6, iclass 3, count 2 2006.189.07:38:20.13#ibcon#end of sib2, iclass 3, count 2 2006.189.07:38:20.13#ibcon#*mode == 0, iclass 3, count 2 2006.189.07:38:20.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.07:38:20.13#ibcon#[25=AT07-06\r\n] 2006.189.07:38:20.13#ibcon#*before write, iclass 3, count 2 2006.189.07:38:20.13#ibcon#enter sib2, iclass 3, count 2 2006.189.07:38:20.13#ibcon#flushed, iclass 3, count 2 2006.189.07:38:20.13#ibcon#about to write, iclass 3, count 2 2006.189.07:38:20.13#ibcon#wrote, iclass 3, count 2 2006.189.07:38:20.13#ibcon#about to read 3, iclass 3, count 2 2006.189.07:38:20.16#ibcon#read 3, iclass 3, count 2 2006.189.07:38:20.16#ibcon#about to read 4, iclass 3, count 2 2006.189.07:38:20.16#ibcon#read 4, iclass 3, count 2 2006.189.07:38:20.16#ibcon#about to read 5, iclass 3, count 2 2006.189.07:38:20.16#ibcon#read 5, iclass 3, count 2 2006.189.07:38:20.16#ibcon#about to read 6, iclass 3, count 2 2006.189.07:38:20.16#ibcon#read 6, iclass 3, count 2 2006.189.07:38:20.16#ibcon#end of sib2, iclass 3, count 2 2006.189.07:38:20.16#ibcon#*after write, iclass 3, count 2 2006.189.07:38:20.16#ibcon#*before return 0, iclass 3, count 2 2006.189.07:38:20.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:38:20.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:38:20.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.07:38:20.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:20.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:38:20.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:38:20.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:38:20.28#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:38:20.28#ibcon#first serial, iclass 3, count 0 2006.189.07:38:20.28#ibcon#enter sib2, iclass 3, count 0 2006.189.07:38:20.28#ibcon#flushed, iclass 3, count 0 2006.189.07:38:20.28#ibcon#about to write, iclass 3, count 0 2006.189.07:38:20.28#ibcon#wrote, iclass 3, count 0 2006.189.07:38:20.28#ibcon#about to read 3, iclass 3, count 0 2006.189.07:38:20.30#ibcon#read 3, iclass 3, count 0 2006.189.07:38:20.30#ibcon#about to read 4, iclass 3, count 0 2006.189.07:38:20.30#ibcon#read 4, iclass 3, count 0 2006.189.07:38:20.30#ibcon#about to read 5, iclass 3, count 0 2006.189.07:38:20.30#ibcon#read 5, iclass 3, count 0 2006.189.07:38:20.30#ibcon#about to read 6, iclass 3, count 0 2006.189.07:38:20.30#ibcon#read 6, iclass 3, count 0 2006.189.07:38:20.30#ibcon#end of sib2, iclass 3, count 0 2006.189.07:38:20.30#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:38:20.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:38:20.30#ibcon#[25=USB\r\n] 2006.189.07:38:20.30#ibcon#*before write, iclass 3, count 0 2006.189.07:38:20.30#ibcon#enter sib2, iclass 3, count 0 2006.189.07:38:20.30#ibcon#flushed, iclass 3, count 0 2006.189.07:38:20.30#ibcon#about to write, iclass 3, count 0 2006.189.07:38:20.30#ibcon#wrote, iclass 3, count 0 2006.189.07:38:20.30#ibcon#about to read 3, iclass 3, count 0 2006.189.07:38:20.33#ibcon#read 3, iclass 3, count 0 2006.189.07:38:20.33#ibcon#about to read 4, iclass 3, count 0 2006.189.07:38:20.33#ibcon#read 4, iclass 3, count 0 2006.189.07:38:20.33#ibcon#about to read 5, iclass 3, count 0 2006.189.07:38:20.33#ibcon#read 5, iclass 3, count 0 2006.189.07:38:20.33#ibcon#about to read 6, iclass 3, count 0 2006.189.07:38:20.33#ibcon#read 6, iclass 3, count 0 2006.189.07:38:20.33#ibcon#end of sib2, iclass 3, count 0 2006.189.07:38:20.33#ibcon#*after write, iclass 3, count 0 2006.189.07:38:20.33#ibcon#*before return 0, iclass 3, count 0 2006.189.07:38:20.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:38:20.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:38:20.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:38:20.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:38:20.33$vc4f8/valo=8,852.99 2006.189.07:38:20.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.07:38:20.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.07:38:20.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:20.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:38:20.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:38:20.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:38:20.33#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:38:20.33#ibcon#first serial, iclass 5, count 0 2006.189.07:38:20.33#ibcon#enter sib2, iclass 5, count 0 2006.189.07:38:20.33#ibcon#flushed, iclass 5, count 0 2006.189.07:38:20.33#ibcon#about to write, iclass 5, count 0 2006.189.07:38:20.33#ibcon#wrote, iclass 5, count 0 2006.189.07:38:20.33#ibcon#about to read 3, iclass 5, count 0 2006.189.07:38:20.35#ibcon#read 3, iclass 5, count 0 2006.189.07:38:20.35#ibcon#about to read 4, iclass 5, count 0 2006.189.07:38:20.35#ibcon#read 4, iclass 5, count 0 2006.189.07:38:20.35#ibcon#about to read 5, iclass 5, count 0 2006.189.07:38:20.35#ibcon#read 5, iclass 5, count 0 2006.189.07:38:20.35#ibcon#about to read 6, iclass 5, count 0 2006.189.07:38:20.35#ibcon#read 6, iclass 5, count 0 2006.189.07:38:20.35#ibcon#end of sib2, iclass 5, count 0 2006.189.07:38:20.35#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:38:20.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:38:20.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:38:20.35#ibcon#*before write, iclass 5, count 0 2006.189.07:38:20.35#ibcon#enter sib2, iclass 5, count 0 2006.189.07:38:20.35#ibcon#flushed, iclass 5, count 0 2006.189.07:38:20.35#ibcon#about to write, iclass 5, count 0 2006.189.07:38:20.35#ibcon#wrote, iclass 5, count 0 2006.189.07:38:20.35#ibcon#about to read 3, iclass 5, count 0 2006.189.07:38:20.39#ibcon#read 3, iclass 5, count 0 2006.189.07:38:20.39#ibcon#about to read 4, iclass 5, count 0 2006.189.07:38:20.39#ibcon#read 4, iclass 5, count 0 2006.189.07:38:20.39#ibcon#about to read 5, iclass 5, count 0 2006.189.07:38:20.39#ibcon#read 5, iclass 5, count 0 2006.189.07:38:20.39#ibcon#about to read 6, iclass 5, count 0 2006.189.07:38:20.39#ibcon#read 6, iclass 5, count 0 2006.189.07:38:20.39#ibcon#end of sib2, iclass 5, count 0 2006.189.07:38:20.39#ibcon#*after write, iclass 5, count 0 2006.189.07:38:20.39#ibcon#*before return 0, iclass 5, count 0 2006.189.07:38:20.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:38:20.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:38:20.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:38:20.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:38:20.39$vc4f8/va=8,6 2006.189.07:38:20.39#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.07:38:20.39#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.07:38:20.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:20.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:38:20.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:38:20.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:38:20.45#ibcon#enter wrdev, iclass 7, count 2 2006.189.07:38:20.45#ibcon#first serial, iclass 7, count 2 2006.189.07:38:20.45#ibcon#enter sib2, iclass 7, count 2 2006.189.07:38:20.45#ibcon#flushed, iclass 7, count 2 2006.189.07:38:20.45#ibcon#about to write, iclass 7, count 2 2006.189.07:38:20.45#ibcon#wrote, iclass 7, count 2 2006.189.07:38:20.45#ibcon#about to read 3, iclass 7, count 2 2006.189.07:38:20.47#ibcon#read 3, iclass 7, count 2 2006.189.07:38:20.47#ibcon#about to read 4, iclass 7, count 2 2006.189.07:38:20.47#ibcon#read 4, iclass 7, count 2 2006.189.07:38:20.47#ibcon#about to read 5, iclass 7, count 2 2006.189.07:38:20.47#ibcon#read 5, iclass 7, count 2 2006.189.07:38:20.47#ibcon#about to read 6, iclass 7, count 2 2006.189.07:38:20.47#ibcon#read 6, iclass 7, count 2 2006.189.07:38:20.47#ibcon#end of sib2, iclass 7, count 2 2006.189.07:38:20.47#ibcon#*mode == 0, iclass 7, count 2 2006.189.07:38:20.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.07:38:20.47#ibcon#[25=AT08-06\r\n] 2006.189.07:38:20.47#ibcon#*before write, iclass 7, count 2 2006.189.07:38:20.47#ibcon#enter sib2, iclass 7, count 2 2006.189.07:38:20.47#ibcon#flushed, iclass 7, count 2 2006.189.07:38:20.47#ibcon#about to write, iclass 7, count 2 2006.189.07:38:20.47#ibcon#wrote, iclass 7, count 2 2006.189.07:38:20.47#ibcon#about to read 3, iclass 7, count 2 2006.189.07:38:20.50#ibcon#read 3, iclass 7, count 2 2006.189.07:38:20.50#ibcon#about to read 4, iclass 7, count 2 2006.189.07:38:20.50#ibcon#read 4, iclass 7, count 2 2006.189.07:38:20.50#ibcon#about to read 5, iclass 7, count 2 2006.189.07:38:20.50#ibcon#read 5, iclass 7, count 2 2006.189.07:38:20.50#ibcon#about to read 6, iclass 7, count 2 2006.189.07:38:20.50#ibcon#read 6, iclass 7, count 2 2006.189.07:38:20.50#ibcon#end of sib2, iclass 7, count 2 2006.189.07:38:20.50#ibcon#*after write, iclass 7, count 2 2006.189.07:38:20.50#ibcon#*before return 0, iclass 7, count 2 2006.189.07:38:20.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:38:20.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:38:20.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.07:38:20.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:20.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:38:20.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:38:20.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:38:20.62#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:38:20.62#ibcon#first serial, iclass 7, count 0 2006.189.07:38:20.62#ibcon#enter sib2, iclass 7, count 0 2006.189.07:38:20.62#ibcon#flushed, iclass 7, count 0 2006.189.07:38:20.62#ibcon#about to write, iclass 7, count 0 2006.189.07:38:20.62#ibcon#wrote, iclass 7, count 0 2006.189.07:38:20.62#ibcon#about to read 3, iclass 7, count 0 2006.189.07:38:20.64#ibcon#read 3, iclass 7, count 0 2006.189.07:38:20.64#ibcon#about to read 4, iclass 7, count 0 2006.189.07:38:20.64#ibcon#read 4, iclass 7, count 0 2006.189.07:38:20.64#ibcon#about to read 5, iclass 7, count 0 2006.189.07:38:20.64#ibcon#read 5, iclass 7, count 0 2006.189.07:38:20.64#ibcon#about to read 6, iclass 7, count 0 2006.189.07:38:20.64#ibcon#read 6, iclass 7, count 0 2006.189.07:38:20.64#ibcon#end of sib2, iclass 7, count 0 2006.189.07:38:20.64#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:38:20.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:38:20.64#ibcon#[25=USB\r\n] 2006.189.07:38:20.64#ibcon#*before write, iclass 7, count 0 2006.189.07:38:20.64#ibcon#enter sib2, iclass 7, count 0 2006.189.07:38:20.64#ibcon#flushed, iclass 7, count 0 2006.189.07:38:20.64#ibcon#about to write, iclass 7, count 0 2006.189.07:38:20.64#ibcon#wrote, iclass 7, count 0 2006.189.07:38:20.64#ibcon#about to read 3, iclass 7, count 0 2006.189.07:38:20.67#ibcon#read 3, iclass 7, count 0 2006.189.07:38:20.67#ibcon#about to read 4, iclass 7, count 0 2006.189.07:38:20.67#ibcon#read 4, iclass 7, count 0 2006.189.07:38:20.67#ibcon#about to read 5, iclass 7, count 0 2006.189.07:38:20.67#ibcon#read 5, iclass 7, count 0 2006.189.07:38:20.67#ibcon#about to read 6, iclass 7, count 0 2006.189.07:38:20.67#ibcon#read 6, iclass 7, count 0 2006.189.07:38:20.67#ibcon#end of sib2, iclass 7, count 0 2006.189.07:38:20.67#ibcon#*after write, iclass 7, count 0 2006.189.07:38:20.67#ibcon#*before return 0, iclass 7, count 0 2006.189.07:38:20.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:38:20.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:38:20.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:38:20.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:38:20.67$vc4f8/vblo=1,632.99 2006.189.07:38:20.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.07:38:20.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.07:38:20.67#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:20.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:38:20.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:38:20.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:38:20.67#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:38:20.67#ibcon#first serial, iclass 11, count 0 2006.189.07:38:20.67#ibcon#enter sib2, iclass 11, count 0 2006.189.07:38:20.67#ibcon#flushed, iclass 11, count 0 2006.189.07:38:20.67#ibcon#about to write, iclass 11, count 0 2006.189.07:38:20.67#ibcon#wrote, iclass 11, count 0 2006.189.07:38:20.67#ibcon#about to read 3, iclass 11, count 0 2006.189.07:38:20.69#ibcon#read 3, iclass 11, count 0 2006.189.07:38:20.69#ibcon#about to read 4, iclass 11, count 0 2006.189.07:38:20.69#ibcon#read 4, iclass 11, count 0 2006.189.07:38:20.69#ibcon#about to read 5, iclass 11, count 0 2006.189.07:38:20.69#ibcon#read 5, iclass 11, count 0 2006.189.07:38:20.69#ibcon#about to read 6, iclass 11, count 0 2006.189.07:38:20.69#ibcon#read 6, iclass 11, count 0 2006.189.07:38:20.69#ibcon#end of sib2, iclass 11, count 0 2006.189.07:38:20.69#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:38:20.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:38:20.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:38:20.69#ibcon#*before write, iclass 11, count 0 2006.189.07:38:20.69#ibcon#enter sib2, iclass 11, count 0 2006.189.07:38:20.69#ibcon#flushed, iclass 11, count 0 2006.189.07:38:20.69#ibcon#about to write, iclass 11, count 0 2006.189.07:38:20.69#ibcon#wrote, iclass 11, count 0 2006.189.07:38:20.69#ibcon#about to read 3, iclass 11, count 0 2006.189.07:38:20.73#ibcon#read 3, iclass 11, count 0 2006.189.07:38:20.73#ibcon#about to read 4, iclass 11, count 0 2006.189.07:38:20.73#ibcon#read 4, iclass 11, count 0 2006.189.07:38:20.73#ibcon#about to read 5, iclass 11, count 0 2006.189.07:38:20.73#ibcon#read 5, iclass 11, count 0 2006.189.07:38:20.73#ibcon#about to read 6, iclass 11, count 0 2006.189.07:38:20.73#ibcon#read 6, iclass 11, count 0 2006.189.07:38:20.73#ibcon#end of sib2, iclass 11, count 0 2006.189.07:38:20.73#ibcon#*after write, iclass 11, count 0 2006.189.07:38:20.73#ibcon#*before return 0, iclass 11, count 0 2006.189.07:38:20.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:38:20.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:38:20.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:38:20.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:38:20.73$vc4f8/vb=1,4 2006.189.07:38:20.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.07:38:20.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.07:38:20.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:20.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:38:20.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:38:20.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:38:20.73#ibcon#enter wrdev, iclass 13, count 2 2006.189.07:38:20.73#ibcon#first serial, iclass 13, count 2 2006.189.07:38:20.73#ibcon#enter sib2, iclass 13, count 2 2006.189.07:38:20.73#ibcon#flushed, iclass 13, count 2 2006.189.07:38:20.73#ibcon#about to write, iclass 13, count 2 2006.189.07:38:20.73#ibcon#wrote, iclass 13, count 2 2006.189.07:38:20.73#ibcon#about to read 3, iclass 13, count 2 2006.189.07:38:20.75#ibcon#read 3, iclass 13, count 2 2006.189.07:38:20.75#ibcon#about to read 4, iclass 13, count 2 2006.189.07:38:20.75#ibcon#read 4, iclass 13, count 2 2006.189.07:38:20.75#ibcon#about to read 5, iclass 13, count 2 2006.189.07:38:20.75#ibcon#read 5, iclass 13, count 2 2006.189.07:38:20.75#ibcon#about to read 6, iclass 13, count 2 2006.189.07:38:20.75#ibcon#read 6, iclass 13, count 2 2006.189.07:38:20.75#ibcon#end of sib2, iclass 13, count 2 2006.189.07:38:20.75#ibcon#*mode == 0, iclass 13, count 2 2006.189.07:38:20.75#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.07:38:20.75#ibcon#[27=AT01-04\r\n] 2006.189.07:38:20.75#ibcon#*before write, iclass 13, count 2 2006.189.07:38:20.75#ibcon#enter sib2, iclass 13, count 2 2006.189.07:38:20.75#ibcon#flushed, iclass 13, count 2 2006.189.07:38:20.75#ibcon#about to write, iclass 13, count 2 2006.189.07:38:20.75#ibcon#wrote, iclass 13, count 2 2006.189.07:38:20.75#ibcon#about to read 3, iclass 13, count 2 2006.189.07:38:20.78#ibcon#read 3, iclass 13, count 2 2006.189.07:38:20.78#ibcon#about to read 4, iclass 13, count 2 2006.189.07:38:20.78#ibcon#read 4, iclass 13, count 2 2006.189.07:38:20.78#ibcon#about to read 5, iclass 13, count 2 2006.189.07:38:20.78#ibcon#read 5, iclass 13, count 2 2006.189.07:38:20.78#ibcon#about to read 6, iclass 13, count 2 2006.189.07:38:20.78#ibcon#read 6, iclass 13, count 2 2006.189.07:38:20.78#ibcon#end of sib2, iclass 13, count 2 2006.189.07:38:20.78#ibcon#*after write, iclass 13, count 2 2006.189.07:38:20.78#ibcon#*before return 0, iclass 13, count 2 2006.189.07:38:20.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:38:20.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:38:20.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.07:38:20.78#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:20.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:38:20.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:38:20.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:38:20.90#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:38:20.90#ibcon#first serial, iclass 13, count 0 2006.189.07:38:20.90#ibcon#enter sib2, iclass 13, count 0 2006.189.07:38:20.90#ibcon#flushed, iclass 13, count 0 2006.189.07:38:20.90#ibcon#about to write, iclass 13, count 0 2006.189.07:38:20.90#ibcon#wrote, iclass 13, count 0 2006.189.07:38:20.90#ibcon#about to read 3, iclass 13, count 0 2006.189.07:38:20.92#ibcon#read 3, iclass 13, count 0 2006.189.07:38:20.92#ibcon#about to read 4, iclass 13, count 0 2006.189.07:38:20.92#ibcon#read 4, iclass 13, count 0 2006.189.07:38:20.92#ibcon#about to read 5, iclass 13, count 0 2006.189.07:38:20.92#ibcon#read 5, iclass 13, count 0 2006.189.07:38:20.92#ibcon#about to read 6, iclass 13, count 0 2006.189.07:38:20.92#ibcon#read 6, iclass 13, count 0 2006.189.07:38:20.92#ibcon#end of sib2, iclass 13, count 0 2006.189.07:38:20.92#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:38:20.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:38:20.92#ibcon#[27=USB\r\n] 2006.189.07:38:20.92#ibcon#*before write, iclass 13, count 0 2006.189.07:38:20.92#ibcon#enter sib2, iclass 13, count 0 2006.189.07:38:20.92#ibcon#flushed, iclass 13, count 0 2006.189.07:38:20.92#ibcon#about to write, iclass 13, count 0 2006.189.07:38:20.92#ibcon#wrote, iclass 13, count 0 2006.189.07:38:20.92#ibcon#about to read 3, iclass 13, count 0 2006.189.07:38:20.95#ibcon#read 3, iclass 13, count 0 2006.189.07:38:20.95#ibcon#about to read 4, iclass 13, count 0 2006.189.07:38:20.95#ibcon#read 4, iclass 13, count 0 2006.189.07:38:20.95#ibcon#about to read 5, iclass 13, count 0 2006.189.07:38:20.95#ibcon#read 5, iclass 13, count 0 2006.189.07:38:20.95#ibcon#about to read 6, iclass 13, count 0 2006.189.07:38:20.95#ibcon#read 6, iclass 13, count 0 2006.189.07:38:20.95#ibcon#end of sib2, iclass 13, count 0 2006.189.07:38:20.95#ibcon#*after write, iclass 13, count 0 2006.189.07:38:20.95#ibcon#*before return 0, iclass 13, count 0 2006.189.07:38:20.95#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:38:20.95#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:38:20.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:38:20.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:38:20.95$vc4f8/vblo=2,640.99 2006.189.07:38:20.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.07:38:20.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.07:38:20.95#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:20.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:20.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:20.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:20.95#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:38:20.95#ibcon#first serial, iclass 15, count 0 2006.189.07:38:20.95#ibcon#enter sib2, iclass 15, count 0 2006.189.07:38:20.95#ibcon#flushed, iclass 15, count 0 2006.189.07:38:20.95#ibcon#about to write, iclass 15, count 0 2006.189.07:38:20.95#ibcon#wrote, iclass 15, count 0 2006.189.07:38:20.95#ibcon#about to read 3, iclass 15, count 0 2006.189.07:38:20.97#ibcon#read 3, iclass 15, count 0 2006.189.07:38:20.97#ibcon#about to read 4, iclass 15, count 0 2006.189.07:38:20.97#ibcon#read 4, iclass 15, count 0 2006.189.07:38:20.97#ibcon#about to read 5, iclass 15, count 0 2006.189.07:38:20.97#ibcon#read 5, iclass 15, count 0 2006.189.07:38:20.97#ibcon#about to read 6, iclass 15, count 0 2006.189.07:38:20.97#ibcon#read 6, iclass 15, count 0 2006.189.07:38:20.97#ibcon#end of sib2, iclass 15, count 0 2006.189.07:38:20.97#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:38:20.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:38:20.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:38:20.97#ibcon#*before write, iclass 15, count 0 2006.189.07:38:20.97#ibcon#enter sib2, iclass 15, count 0 2006.189.07:38:20.97#ibcon#flushed, iclass 15, count 0 2006.189.07:38:20.97#ibcon#about to write, iclass 15, count 0 2006.189.07:38:20.97#ibcon#wrote, iclass 15, count 0 2006.189.07:38:20.97#ibcon#about to read 3, iclass 15, count 0 2006.189.07:38:21.01#ibcon#read 3, iclass 15, count 0 2006.189.07:38:21.01#ibcon#about to read 4, iclass 15, count 0 2006.189.07:38:21.01#ibcon#read 4, iclass 15, count 0 2006.189.07:38:21.01#ibcon#about to read 5, iclass 15, count 0 2006.189.07:38:21.01#ibcon#read 5, iclass 15, count 0 2006.189.07:38:21.01#ibcon#about to read 6, iclass 15, count 0 2006.189.07:38:21.01#ibcon#read 6, iclass 15, count 0 2006.189.07:38:21.01#ibcon#end of sib2, iclass 15, count 0 2006.189.07:38:21.01#ibcon#*after write, iclass 15, count 0 2006.189.07:38:21.01#ibcon#*before return 0, iclass 15, count 0 2006.189.07:38:21.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:21.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:38:21.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:38:21.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:38:21.01$vc4f8/vb=2,4 2006.189.07:38:21.01#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.07:38:21.01#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.07:38:21.01#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:21.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:21.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:21.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:21.07#ibcon#enter wrdev, iclass 17, count 2 2006.189.07:38:21.07#ibcon#first serial, iclass 17, count 2 2006.189.07:38:21.07#ibcon#enter sib2, iclass 17, count 2 2006.189.07:38:21.07#ibcon#flushed, iclass 17, count 2 2006.189.07:38:21.07#ibcon#about to write, iclass 17, count 2 2006.189.07:38:21.07#ibcon#wrote, iclass 17, count 2 2006.189.07:38:21.07#ibcon#about to read 3, iclass 17, count 2 2006.189.07:38:21.09#ibcon#read 3, iclass 17, count 2 2006.189.07:38:21.09#ibcon#about to read 4, iclass 17, count 2 2006.189.07:38:21.09#ibcon#read 4, iclass 17, count 2 2006.189.07:38:21.09#ibcon#about to read 5, iclass 17, count 2 2006.189.07:38:21.09#ibcon#read 5, iclass 17, count 2 2006.189.07:38:21.09#ibcon#about to read 6, iclass 17, count 2 2006.189.07:38:21.09#ibcon#read 6, iclass 17, count 2 2006.189.07:38:21.09#ibcon#end of sib2, iclass 17, count 2 2006.189.07:38:21.09#ibcon#*mode == 0, iclass 17, count 2 2006.189.07:38:21.09#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.07:38:21.09#ibcon#[27=AT02-04\r\n] 2006.189.07:38:21.09#ibcon#*before write, iclass 17, count 2 2006.189.07:38:21.09#ibcon#enter sib2, iclass 17, count 2 2006.189.07:38:21.09#ibcon#flushed, iclass 17, count 2 2006.189.07:38:21.09#ibcon#about to write, iclass 17, count 2 2006.189.07:38:21.09#ibcon#wrote, iclass 17, count 2 2006.189.07:38:21.09#ibcon#about to read 3, iclass 17, count 2 2006.189.07:38:21.12#ibcon#read 3, iclass 17, count 2 2006.189.07:38:21.12#ibcon#about to read 4, iclass 17, count 2 2006.189.07:38:21.12#ibcon#read 4, iclass 17, count 2 2006.189.07:38:21.12#ibcon#about to read 5, iclass 17, count 2 2006.189.07:38:21.12#ibcon#read 5, iclass 17, count 2 2006.189.07:38:21.12#ibcon#about to read 6, iclass 17, count 2 2006.189.07:38:21.12#ibcon#read 6, iclass 17, count 2 2006.189.07:38:21.12#ibcon#end of sib2, iclass 17, count 2 2006.189.07:38:21.12#ibcon#*after write, iclass 17, count 2 2006.189.07:38:21.12#ibcon#*before return 0, iclass 17, count 2 2006.189.07:38:21.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:21.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:38:21.12#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.07:38:21.12#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:21.12#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:21.24#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:21.24#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:21.24#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:38:21.24#ibcon#first serial, iclass 17, count 0 2006.189.07:38:21.24#ibcon#enter sib2, iclass 17, count 0 2006.189.07:38:21.24#ibcon#flushed, iclass 17, count 0 2006.189.07:38:21.24#ibcon#about to write, iclass 17, count 0 2006.189.07:38:21.24#ibcon#wrote, iclass 17, count 0 2006.189.07:38:21.24#ibcon#about to read 3, iclass 17, count 0 2006.189.07:38:21.26#ibcon#read 3, iclass 17, count 0 2006.189.07:38:21.26#ibcon#about to read 4, iclass 17, count 0 2006.189.07:38:21.26#ibcon#read 4, iclass 17, count 0 2006.189.07:38:21.26#ibcon#about to read 5, iclass 17, count 0 2006.189.07:38:21.26#ibcon#read 5, iclass 17, count 0 2006.189.07:38:21.26#ibcon#about to read 6, iclass 17, count 0 2006.189.07:38:21.26#ibcon#read 6, iclass 17, count 0 2006.189.07:38:21.26#ibcon#end of sib2, iclass 17, count 0 2006.189.07:38:21.26#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:38:21.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:38:21.26#ibcon#[27=USB\r\n] 2006.189.07:38:21.26#ibcon#*before write, iclass 17, count 0 2006.189.07:38:21.26#ibcon#enter sib2, iclass 17, count 0 2006.189.07:38:21.26#ibcon#flushed, iclass 17, count 0 2006.189.07:38:21.26#ibcon#about to write, iclass 17, count 0 2006.189.07:38:21.26#ibcon#wrote, iclass 17, count 0 2006.189.07:38:21.26#ibcon#about to read 3, iclass 17, count 0 2006.189.07:38:21.29#ibcon#read 3, iclass 17, count 0 2006.189.07:38:21.29#ibcon#about to read 4, iclass 17, count 0 2006.189.07:38:21.29#ibcon#read 4, iclass 17, count 0 2006.189.07:38:21.29#ibcon#about to read 5, iclass 17, count 0 2006.189.07:38:21.29#ibcon#read 5, iclass 17, count 0 2006.189.07:38:21.29#ibcon#about to read 6, iclass 17, count 0 2006.189.07:38:21.29#ibcon#read 6, iclass 17, count 0 2006.189.07:38:21.29#ibcon#end of sib2, iclass 17, count 0 2006.189.07:38:21.29#ibcon#*after write, iclass 17, count 0 2006.189.07:38:21.29#ibcon#*before return 0, iclass 17, count 0 2006.189.07:38:21.29#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:21.29#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:38:21.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:38:21.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:38:21.29$vc4f8/vblo=3,656.99 2006.189.07:38:21.29#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.07:38:21.29#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.07:38:21.29#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:21.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:21.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:21.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:21.29#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:38:21.29#ibcon#first serial, iclass 19, count 0 2006.189.07:38:21.29#ibcon#enter sib2, iclass 19, count 0 2006.189.07:38:21.29#ibcon#flushed, iclass 19, count 0 2006.189.07:38:21.29#ibcon#about to write, iclass 19, count 0 2006.189.07:38:21.29#ibcon#wrote, iclass 19, count 0 2006.189.07:38:21.29#ibcon#about to read 3, iclass 19, count 0 2006.189.07:38:21.31#ibcon#read 3, iclass 19, count 0 2006.189.07:38:21.31#ibcon#about to read 4, iclass 19, count 0 2006.189.07:38:21.31#ibcon#read 4, iclass 19, count 0 2006.189.07:38:21.31#ibcon#about to read 5, iclass 19, count 0 2006.189.07:38:21.31#ibcon#read 5, iclass 19, count 0 2006.189.07:38:21.31#ibcon#about to read 6, iclass 19, count 0 2006.189.07:38:21.31#ibcon#read 6, iclass 19, count 0 2006.189.07:38:21.31#ibcon#end of sib2, iclass 19, count 0 2006.189.07:38:21.31#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:38:21.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:38:21.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:38:21.31#ibcon#*before write, iclass 19, count 0 2006.189.07:38:21.31#ibcon#enter sib2, iclass 19, count 0 2006.189.07:38:21.31#ibcon#flushed, iclass 19, count 0 2006.189.07:38:21.31#ibcon#about to write, iclass 19, count 0 2006.189.07:38:21.31#ibcon#wrote, iclass 19, count 0 2006.189.07:38:21.31#ibcon#about to read 3, iclass 19, count 0 2006.189.07:38:21.35#ibcon#read 3, iclass 19, count 0 2006.189.07:38:21.35#ibcon#about to read 4, iclass 19, count 0 2006.189.07:38:21.35#ibcon#read 4, iclass 19, count 0 2006.189.07:38:21.35#ibcon#about to read 5, iclass 19, count 0 2006.189.07:38:21.35#ibcon#read 5, iclass 19, count 0 2006.189.07:38:21.35#ibcon#about to read 6, iclass 19, count 0 2006.189.07:38:21.35#ibcon#read 6, iclass 19, count 0 2006.189.07:38:21.35#ibcon#end of sib2, iclass 19, count 0 2006.189.07:38:21.35#ibcon#*after write, iclass 19, count 0 2006.189.07:38:21.35#ibcon#*before return 0, iclass 19, count 0 2006.189.07:38:21.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:21.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:38:21.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:38:21.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:38:21.35$vc4f8/vb=3,4 2006.189.07:38:21.35#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.07:38:21.35#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.07:38:21.35#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:21.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:21.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:21.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:21.41#ibcon#enter wrdev, iclass 21, count 2 2006.189.07:38:21.41#ibcon#first serial, iclass 21, count 2 2006.189.07:38:21.41#ibcon#enter sib2, iclass 21, count 2 2006.189.07:38:21.41#ibcon#flushed, iclass 21, count 2 2006.189.07:38:21.41#ibcon#about to write, iclass 21, count 2 2006.189.07:38:21.41#ibcon#wrote, iclass 21, count 2 2006.189.07:38:21.41#ibcon#about to read 3, iclass 21, count 2 2006.189.07:38:21.43#ibcon#read 3, iclass 21, count 2 2006.189.07:38:21.43#ibcon#about to read 4, iclass 21, count 2 2006.189.07:38:21.43#ibcon#read 4, iclass 21, count 2 2006.189.07:38:21.43#ibcon#about to read 5, iclass 21, count 2 2006.189.07:38:21.43#ibcon#read 5, iclass 21, count 2 2006.189.07:38:21.43#ibcon#about to read 6, iclass 21, count 2 2006.189.07:38:21.43#ibcon#read 6, iclass 21, count 2 2006.189.07:38:21.43#ibcon#end of sib2, iclass 21, count 2 2006.189.07:38:21.43#ibcon#*mode == 0, iclass 21, count 2 2006.189.07:38:21.43#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.07:38:21.43#ibcon#[27=AT03-04\r\n] 2006.189.07:38:21.43#ibcon#*before write, iclass 21, count 2 2006.189.07:38:21.43#ibcon#enter sib2, iclass 21, count 2 2006.189.07:38:21.43#ibcon#flushed, iclass 21, count 2 2006.189.07:38:21.43#ibcon#about to write, iclass 21, count 2 2006.189.07:38:21.43#ibcon#wrote, iclass 21, count 2 2006.189.07:38:21.43#ibcon#about to read 3, iclass 21, count 2 2006.189.07:38:21.46#ibcon#read 3, iclass 21, count 2 2006.189.07:38:21.46#ibcon#about to read 4, iclass 21, count 2 2006.189.07:38:21.46#ibcon#read 4, iclass 21, count 2 2006.189.07:38:21.46#ibcon#about to read 5, iclass 21, count 2 2006.189.07:38:21.46#ibcon#read 5, iclass 21, count 2 2006.189.07:38:21.46#ibcon#about to read 6, iclass 21, count 2 2006.189.07:38:21.46#ibcon#read 6, iclass 21, count 2 2006.189.07:38:21.46#ibcon#end of sib2, iclass 21, count 2 2006.189.07:38:21.46#ibcon#*after write, iclass 21, count 2 2006.189.07:38:21.46#ibcon#*before return 0, iclass 21, count 2 2006.189.07:38:21.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:21.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:38:21.46#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.07:38:21.46#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:21.46#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:21.58#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:21.58#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:21.58#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:38:21.58#ibcon#first serial, iclass 21, count 0 2006.189.07:38:21.58#ibcon#enter sib2, iclass 21, count 0 2006.189.07:38:21.58#ibcon#flushed, iclass 21, count 0 2006.189.07:38:21.58#ibcon#about to write, iclass 21, count 0 2006.189.07:38:21.58#ibcon#wrote, iclass 21, count 0 2006.189.07:38:21.58#ibcon#about to read 3, iclass 21, count 0 2006.189.07:38:21.60#ibcon#read 3, iclass 21, count 0 2006.189.07:38:21.60#ibcon#about to read 4, iclass 21, count 0 2006.189.07:38:21.60#ibcon#read 4, iclass 21, count 0 2006.189.07:38:21.60#ibcon#about to read 5, iclass 21, count 0 2006.189.07:38:21.60#ibcon#read 5, iclass 21, count 0 2006.189.07:38:21.60#ibcon#about to read 6, iclass 21, count 0 2006.189.07:38:21.60#ibcon#read 6, iclass 21, count 0 2006.189.07:38:21.60#ibcon#end of sib2, iclass 21, count 0 2006.189.07:38:21.60#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:38:21.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:38:21.60#ibcon#[27=USB\r\n] 2006.189.07:38:21.60#ibcon#*before write, iclass 21, count 0 2006.189.07:38:21.60#ibcon#enter sib2, iclass 21, count 0 2006.189.07:38:21.60#ibcon#flushed, iclass 21, count 0 2006.189.07:38:21.60#ibcon#about to write, iclass 21, count 0 2006.189.07:38:21.60#ibcon#wrote, iclass 21, count 0 2006.189.07:38:21.60#ibcon#about to read 3, iclass 21, count 0 2006.189.07:38:21.63#ibcon#read 3, iclass 21, count 0 2006.189.07:38:21.63#ibcon#about to read 4, iclass 21, count 0 2006.189.07:38:21.63#ibcon#read 4, iclass 21, count 0 2006.189.07:38:21.63#ibcon#about to read 5, iclass 21, count 0 2006.189.07:38:21.63#ibcon#read 5, iclass 21, count 0 2006.189.07:38:21.63#ibcon#about to read 6, iclass 21, count 0 2006.189.07:38:21.63#ibcon#read 6, iclass 21, count 0 2006.189.07:38:21.63#ibcon#end of sib2, iclass 21, count 0 2006.189.07:38:21.63#ibcon#*after write, iclass 21, count 0 2006.189.07:38:21.63#ibcon#*before return 0, iclass 21, count 0 2006.189.07:38:21.63#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:21.63#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:38:21.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:38:21.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:38:21.63$vc4f8/vblo=4,712.99 2006.189.07:38:21.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.07:38:21.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.07:38:21.63#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:21.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:21.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:21.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:21.63#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:38:21.63#ibcon#first serial, iclass 23, count 0 2006.189.07:38:21.63#ibcon#enter sib2, iclass 23, count 0 2006.189.07:38:21.63#ibcon#flushed, iclass 23, count 0 2006.189.07:38:21.63#ibcon#about to write, iclass 23, count 0 2006.189.07:38:21.63#ibcon#wrote, iclass 23, count 0 2006.189.07:38:21.63#ibcon#about to read 3, iclass 23, count 0 2006.189.07:38:21.65#ibcon#read 3, iclass 23, count 0 2006.189.07:38:21.65#ibcon#about to read 4, iclass 23, count 0 2006.189.07:38:21.65#ibcon#read 4, iclass 23, count 0 2006.189.07:38:21.65#ibcon#about to read 5, iclass 23, count 0 2006.189.07:38:21.65#ibcon#read 5, iclass 23, count 0 2006.189.07:38:21.65#ibcon#about to read 6, iclass 23, count 0 2006.189.07:38:21.65#ibcon#read 6, iclass 23, count 0 2006.189.07:38:21.65#ibcon#end of sib2, iclass 23, count 0 2006.189.07:38:21.65#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:38:21.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:38:21.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:38:21.65#ibcon#*before write, iclass 23, count 0 2006.189.07:38:21.65#ibcon#enter sib2, iclass 23, count 0 2006.189.07:38:21.65#ibcon#flushed, iclass 23, count 0 2006.189.07:38:21.65#ibcon#about to write, iclass 23, count 0 2006.189.07:38:21.65#ibcon#wrote, iclass 23, count 0 2006.189.07:38:21.65#ibcon#about to read 3, iclass 23, count 0 2006.189.07:38:21.69#ibcon#read 3, iclass 23, count 0 2006.189.07:38:21.69#ibcon#about to read 4, iclass 23, count 0 2006.189.07:38:21.69#ibcon#read 4, iclass 23, count 0 2006.189.07:38:21.69#ibcon#about to read 5, iclass 23, count 0 2006.189.07:38:21.69#ibcon#read 5, iclass 23, count 0 2006.189.07:38:21.69#ibcon#about to read 6, iclass 23, count 0 2006.189.07:38:21.69#ibcon#read 6, iclass 23, count 0 2006.189.07:38:21.69#ibcon#end of sib2, iclass 23, count 0 2006.189.07:38:21.69#ibcon#*after write, iclass 23, count 0 2006.189.07:38:21.69#ibcon#*before return 0, iclass 23, count 0 2006.189.07:38:21.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:21.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:38:21.69#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:38:21.69#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:38:21.69$vc4f8/vb=4,4 2006.189.07:38:21.69#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.07:38:21.69#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.07:38:21.69#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:21.69#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:21.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:21.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:21.75#ibcon#enter wrdev, iclass 25, count 2 2006.189.07:38:21.75#ibcon#first serial, iclass 25, count 2 2006.189.07:38:21.75#ibcon#enter sib2, iclass 25, count 2 2006.189.07:38:21.75#ibcon#flushed, iclass 25, count 2 2006.189.07:38:21.75#ibcon#about to write, iclass 25, count 2 2006.189.07:38:21.75#ibcon#wrote, iclass 25, count 2 2006.189.07:38:21.75#ibcon#about to read 3, iclass 25, count 2 2006.189.07:38:21.77#ibcon#read 3, iclass 25, count 2 2006.189.07:38:21.77#ibcon#about to read 4, iclass 25, count 2 2006.189.07:38:21.77#ibcon#read 4, iclass 25, count 2 2006.189.07:38:21.77#ibcon#about to read 5, iclass 25, count 2 2006.189.07:38:21.77#ibcon#read 5, iclass 25, count 2 2006.189.07:38:21.77#ibcon#about to read 6, iclass 25, count 2 2006.189.07:38:21.77#ibcon#read 6, iclass 25, count 2 2006.189.07:38:21.77#ibcon#end of sib2, iclass 25, count 2 2006.189.07:38:21.77#ibcon#*mode == 0, iclass 25, count 2 2006.189.07:38:21.77#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.07:38:21.77#ibcon#[27=AT04-04\r\n] 2006.189.07:38:21.77#ibcon#*before write, iclass 25, count 2 2006.189.07:38:21.77#ibcon#enter sib2, iclass 25, count 2 2006.189.07:38:21.77#ibcon#flushed, iclass 25, count 2 2006.189.07:38:21.77#ibcon#about to write, iclass 25, count 2 2006.189.07:38:21.77#ibcon#wrote, iclass 25, count 2 2006.189.07:38:21.77#ibcon#about to read 3, iclass 25, count 2 2006.189.07:38:21.80#ibcon#read 3, iclass 25, count 2 2006.189.07:38:21.80#ibcon#about to read 4, iclass 25, count 2 2006.189.07:38:21.80#ibcon#read 4, iclass 25, count 2 2006.189.07:38:21.80#ibcon#about to read 5, iclass 25, count 2 2006.189.07:38:21.80#ibcon#read 5, iclass 25, count 2 2006.189.07:38:21.80#ibcon#about to read 6, iclass 25, count 2 2006.189.07:38:21.80#ibcon#read 6, iclass 25, count 2 2006.189.07:38:21.80#ibcon#end of sib2, iclass 25, count 2 2006.189.07:38:21.80#ibcon#*after write, iclass 25, count 2 2006.189.07:38:21.80#ibcon#*before return 0, iclass 25, count 2 2006.189.07:38:21.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:21.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:38:21.80#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.07:38:21.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:21.80#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:21.92#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:21.92#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:21.92#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:38:21.92#ibcon#first serial, iclass 25, count 0 2006.189.07:38:21.92#ibcon#enter sib2, iclass 25, count 0 2006.189.07:38:21.92#ibcon#flushed, iclass 25, count 0 2006.189.07:38:21.92#ibcon#about to write, iclass 25, count 0 2006.189.07:38:21.92#ibcon#wrote, iclass 25, count 0 2006.189.07:38:21.92#ibcon#about to read 3, iclass 25, count 0 2006.189.07:38:21.94#ibcon#read 3, iclass 25, count 0 2006.189.07:38:21.94#ibcon#about to read 4, iclass 25, count 0 2006.189.07:38:21.94#ibcon#read 4, iclass 25, count 0 2006.189.07:38:21.94#ibcon#about to read 5, iclass 25, count 0 2006.189.07:38:21.94#ibcon#read 5, iclass 25, count 0 2006.189.07:38:21.94#ibcon#about to read 6, iclass 25, count 0 2006.189.07:38:21.94#ibcon#read 6, iclass 25, count 0 2006.189.07:38:21.94#ibcon#end of sib2, iclass 25, count 0 2006.189.07:38:21.94#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:38:21.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:38:21.94#ibcon#[27=USB\r\n] 2006.189.07:38:21.94#ibcon#*before write, iclass 25, count 0 2006.189.07:38:21.94#ibcon#enter sib2, iclass 25, count 0 2006.189.07:38:21.94#ibcon#flushed, iclass 25, count 0 2006.189.07:38:21.94#ibcon#about to write, iclass 25, count 0 2006.189.07:38:21.94#ibcon#wrote, iclass 25, count 0 2006.189.07:38:21.94#ibcon#about to read 3, iclass 25, count 0 2006.189.07:38:21.97#ibcon#read 3, iclass 25, count 0 2006.189.07:38:21.97#ibcon#about to read 4, iclass 25, count 0 2006.189.07:38:21.97#ibcon#read 4, iclass 25, count 0 2006.189.07:38:21.97#ibcon#about to read 5, iclass 25, count 0 2006.189.07:38:21.97#ibcon#read 5, iclass 25, count 0 2006.189.07:38:21.97#ibcon#about to read 6, iclass 25, count 0 2006.189.07:38:21.97#ibcon#read 6, iclass 25, count 0 2006.189.07:38:21.97#ibcon#end of sib2, iclass 25, count 0 2006.189.07:38:21.97#ibcon#*after write, iclass 25, count 0 2006.189.07:38:21.97#ibcon#*before return 0, iclass 25, count 0 2006.189.07:38:21.97#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:21.97#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:38:21.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:38:21.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:38:21.97$vc4f8/vblo=5,744.99 2006.189.07:38:21.97#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.07:38:21.97#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.07:38:21.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:21.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:21.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:21.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:21.97#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:38:21.97#ibcon#first serial, iclass 27, count 0 2006.189.07:38:21.97#ibcon#enter sib2, iclass 27, count 0 2006.189.07:38:21.97#ibcon#flushed, iclass 27, count 0 2006.189.07:38:21.97#ibcon#about to write, iclass 27, count 0 2006.189.07:38:21.97#ibcon#wrote, iclass 27, count 0 2006.189.07:38:21.97#ibcon#about to read 3, iclass 27, count 0 2006.189.07:38:21.99#ibcon#read 3, iclass 27, count 0 2006.189.07:38:21.99#ibcon#about to read 4, iclass 27, count 0 2006.189.07:38:21.99#ibcon#read 4, iclass 27, count 0 2006.189.07:38:21.99#ibcon#about to read 5, iclass 27, count 0 2006.189.07:38:21.99#ibcon#read 5, iclass 27, count 0 2006.189.07:38:21.99#ibcon#about to read 6, iclass 27, count 0 2006.189.07:38:21.99#ibcon#read 6, iclass 27, count 0 2006.189.07:38:21.99#ibcon#end of sib2, iclass 27, count 0 2006.189.07:38:21.99#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:38:21.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:38:21.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:38:21.99#ibcon#*before write, iclass 27, count 0 2006.189.07:38:21.99#ibcon#enter sib2, iclass 27, count 0 2006.189.07:38:21.99#ibcon#flushed, iclass 27, count 0 2006.189.07:38:21.99#ibcon#about to write, iclass 27, count 0 2006.189.07:38:21.99#ibcon#wrote, iclass 27, count 0 2006.189.07:38:21.99#ibcon#about to read 3, iclass 27, count 0 2006.189.07:38:22.03#ibcon#read 3, iclass 27, count 0 2006.189.07:38:22.03#ibcon#about to read 4, iclass 27, count 0 2006.189.07:38:22.03#ibcon#read 4, iclass 27, count 0 2006.189.07:38:22.03#ibcon#about to read 5, iclass 27, count 0 2006.189.07:38:22.03#ibcon#read 5, iclass 27, count 0 2006.189.07:38:22.03#ibcon#about to read 6, iclass 27, count 0 2006.189.07:38:22.03#ibcon#read 6, iclass 27, count 0 2006.189.07:38:22.03#ibcon#end of sib2, iclass 27, count 0 2006.189.07:38:22.03#ibcon#*after write, iclass 27, count 0 2006.189.07:38:22.03#ibcon#*before return 0, iclass 27, count 0 2006.189.07:38:22.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:22.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:38:22.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:38:22.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:38:22.03$vc4f8/vb=5,4 2006.189.07:38:22.03#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.07:38:22.03#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.07:38:22.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:22.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:22.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:22.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:22.09#ibcon#enter wrdev, iclass 29, count 2 2006.189.07:38:22.09#ibcon#first serial, iclass 29, count 2 2006.189.07:38:22.09#ibcon#enter sib2, iclass 29, count 2 2006.189.07:38:22.09#ibcon#flushed, iclass 29, count 2 2006.189.07:38:22.09#ibcon#about to write, iclass 29, count 2 2006.189.07:38:22.09#ibcon#wrote, iclass 29, count 2 2006.189.07:38:22.09#ibcon#about to read 3, iclass 29, count 2 2006.189.07:38:22.11#ibcon#read 3, iclass 29, count 2 2006.189.07:38:22.11#ibcon#about to read 4, iclass 29, count 2 2006.189.07:38:22.11#ibcon#read 4, iclass 29, count 2 2006.189.07:38:22.11#ibcon#about to read 5, iclass 29, count 2 2006.189.07:38:22.11#ibcon#read 5, iclass 29, count 2 2006.189.07:38:22.11#ibcon#about to read 6, iclass 29, count 2 2006.189.07:38:22.11#ibcon#read 6, iclass 29, count 2 2006.189.07:38:22.11#ibcon#end of sib2, iclass 29, count 2 2006.189.07:38:22.11#ibcon#*mode == 0, iclass 29, count 2 2006.189.07:38:22.11#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.07:38:22.11#ibcon#[27=AT05-04\r\n] 2006.189.07:38:22.11#ibcon#*before write, iclass 29, count 2 2006.189.07:38:22.11#ibcon#enter sib2, iclass 29, count 2 2006.189.07:38:22.11#ibcon#flushed, iclass 29, count 2 2006.189.07:38:22.11#ibcon#about to write, iclass 29, count 2 2006.189.07:38:22.11#ibcon#wrote, iclass 29, count 2 2006.189.07:38:22.11#ibcon#about to read 3, iclass 29, count 2 2006.189.07:38:22.14#ibcon#read 3, iclass 29, count 2 2006.189.07:38:22.14#ibcon#about to read 4, iclass 29, count 2 2006.189.07:38:22.14#ibcon#read 4, iclass 29, count 2 2006.189.07:38:22.14#ibcon#about to read 5, iclass 29, count 2 2006.189.07:38:22.14#ibcon#read 5, iclass 29, count 2 2006.189.07:38:22.14#ibcon#about to read 6, iclass 29, count 2 2006.189.07:38:22.14#ibcon#read 6, iclass 29, count 2 2006.189.07:38:22.14#ibcon#end of sib2, iclass 29, count 2 2006.189.07:38:22.14#ibcon#*after write, iclass 29, count 2 2006.189.07:38:22.14#ibcon#*before return 0, iclass 29, count 2 2006.189.07:38:22.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:22.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:38:22.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.07:38:22.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:22.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:22.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:22.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:22.26#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:38:22.26#ibcon#first serial, iclass 29, count 0 2006.189.07:38:22.26#ibcon#enter sib2, iclass 29, count 0 2006.189.07:38:22.26#ibcon#flushed, iclass 29, count 0 2006.189.07:38:22.26#ibcon#about to write, iclass 29, count 0 2006.189.07:38:22.26#ibcon#wrote, iclass 29, count 0 2006.189.07:38:22.26#ibcon#about to read 3, iclass 29, count 0 2006.189.07:38:22.28#ibcon#read 3, iclass 29, count 0 2006.189.07:38:22.28#ibcon#about to read 4, iclass 29, count 0 2006.189.07:38:22.28#ibcon#read 4, iclass 29, count 0 2006.189.07:38:22.28#ibcon#about to read 5, iclass 29, count 0 2006.189.07:38:22.28#ibcon#read 5, iclass 29, count 0 2006.189.07:38:22.28#ibcon#about to read 6, iclass 29, count 0 2006.189.07:38:22.28#ibcon#read 6, iclass 29, count 0 2006.189.07:38:22.28#ibcon#end of sib2, iclass 29, count 0 2006.189.07:38:22.28#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:38:22.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:38:22.28#ibcon#[27=USB\r\n] 2006.189.07:38:22.28#ibcon#*before write, iclass 29, count 0 2006.189.07:38:22.28#ibcon#enter sib2, iclass 29, count 0 2006.189.07:38:22.28#ibcon#flushed, iclass 29, count 0 2006.189.07:38:22.28#ibcon#about to write, iclass 29, count 0 2006.189.07:38:22.28#ibcon#wrote, iclass 29, count 0 2006.189.07:38:22.28#ibcon#about to read 3, iclass 29, count 0 2006.189.07:38:22.31#ibcon#read 3, iclass 29, count 0 2006.189.07:38:22.31#ibcon#about to read 4, iclass 29, count 0 2006.189.07:38:22.31#ibcon#read 4, iclass 29, count 0 2006.189.07:38:22.31#ibcon#about to read 5, iclass 29, count 0 2006.189.07:38:22.31#ibcon#read 5, iclass 29, count 0 2006.189.07:38:22.31#ibcon#about to read 6, iclass 29, count 0 2006.189.07:38:22.31#ibcon#read 6, iclass 29, count 0 2006.189.07:38:22.31#ibcon#end of sib2, iclass 29, count 0 2006.189.07:38:22.31#ibcon#*after write, iclass 29, count 0 2006.189.07:38:22.31#ibcon#*before return 0, iclass 29, count 0 2006.189.07:38:22.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:22.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:38:22.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:38:22.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:38:22.31$vc4f8/vblo=6,752.99 2006.189.07:38:22.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.07:38:22.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.07:38:22.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:38:22.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:22.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:22.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:22.31#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:38:22.31#ibcon#first serial, iclass 31, count 0 2006.189.07:38:22.31#ibcon#enter sib2, iclass 31, count 0 2006.189.07:38:22.31#ibcon#flushed, iclass 31, count 0 2006.189.07:38:22.31#ibcon#about to write, iclass 31, count 0 2006.189.07:38:22.31#ibcon#wrote, iclass 31, count 0 2006.189.07:38:22.31#ibcon#about to read 3, iclass 31, count 0 2006.189.07:38:22.33#ibcon#read 3, iclass 31, count 0 2006.189.07:38:22.33#ibcon#about to read 4, iclass 31, count 0 2006.189.07:38:22.33#ibcon#read 4, iclass 31, count 0 2006.189.07:38:22.33#ibcon#about to read 5, iclass 31, count 0 2006.189.07:38:22.33#ibcon#read 5, iclass 31, count 0 2006.189.07:38:22.33#ibcon#about to read 6, iclass 31, count 0 2006.189.07:38:22.33#ibcon#read 6, iclass 31, count 0 2006.189.07:38:22.33#ibcon#end of sib2, iclass 31, count 0 2006.189.07:38:22.33#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:38:22.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:38:22.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:38:22.33#ibcon#*before write, iclass 31, count 0 2006.189.07:38:22.33#ibcon#enter sib2, iclass 31, count 0 2006.189.07:38:22.33#ibcon#flushed, iclass 31, count 0 2006.189.07:38:22.33#ibcon#about to write, iclass 31, count 0 2006.189.07:38:22.33#ibcon#wrote, iclass 31, count 0 2006.189.07:38:22.33#ibcon#about to read 3, iclass 31, count 0 2006.189.07:38:22.37#ibcon#read 3, iclass 31, count 0 2006.189.07:38:22.37#ibcon#about to read 4, iclass 31, count 0 2006.189.07:38:22.37#ibcon#read 4, iclass 31, count 0 2006.189.07:38:22.37#ibcon#about to read 5, iclass 31, count 0 2006.189.07:38:22.37#ibcon#read 5, iclass 31, count 0 2006.189.07:38:22.37#ibcon#about to read 6, iclass 31, count 0 2006.189.07:38:22.37#ibcon#read 6, iclass 31, count 0 2006.189.07:38:22.37#ibcon#end of sib2, iclass 31, count 0 2006.189.07:38:22.37#ibcon#*after write, iclass 31, count 0 2006.189.07:38:22.37#ibcon#*before return 0, iclass 31, count 0 2006.189.07:38:22.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:22.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:38:22.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:38:22.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:38:22.37$vc4f8/vb=6,4 2006.189.07:38:22.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.07:38:22.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.07:38:22.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:38:22.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:22.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:22.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:22.43#ibcon#enter wrdev, iclass 33, count 2 2006.189.07:38:22.43#ibcon#first serial, iclass 33, count 2 2006.189.07:38:22.43#ibcon#enter sib2, iclass 33, count 2 2006.189.07:38:22.43#ibcon#flushed, iclass 33, count 2 2006.189.07:38:22.43#ibcon#about to write, iclass 33, count 2 2006.189.07:38:22.43#ibcon#wrote, iclass 33, count 2 2006.189.07:38:22.43#ibcon#about to read 3, iclass 33, count 2 2006.189.07:38:22.45#ibcon#read 3, iclass 33, count 2 2006.189.07:38:22.45#ibcon#about to read 4, iclass 33, count 2 2006.189.07:38:22.45#ibcon#read 4, iclass 33, count 2 2006.189.07:38:22.45#ibcon#about to read 5, iclass 33, count 2 2006.189.07:38:22.45#ibcon#read 5, iclass 33, count 2 2006.189.07:38:22.45#ibcon#about to read 6, iclass 33, count 2 2006.189.07:38:22.45#ibcon#read 6, iclass 33, count 2 2006.189.07:38:22.45#ibcon#end of sib2, iclass 33, count 2 2006.189.07:38:22.45#ibcon#*mode == 0, iclass 33, count 2 2006.189.07:38:22.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.07:38:22.45#ibcon#[27=AT06-04\r\n] 2006.189.07:38:22.45#ibcon#*before write, iclass 33, count 2 2006.189.07:38:22.45#ibcon#enter sib2, iclass 33, count 2 2006.189.07:38:22.45#ibcon#flushed, iclass 33, count 2 2006.189.07:38:22.45#ibcon#about to write, iclass 33, count 2 2006.189.07:38:22.45#ibcon#wrote, iclass 33, count 2 2006.189.07:38:22.45#ibcon#about to read 3, iclass 33, count 2 2006.189.07:38:22.48#ibcon#read 3, iclass 33, count 2 2006.189.07:38:22.48#ibcon#about to read 4, iclass 33, count 2 2006.189.07:38:22.48#ibcon#read 4, iclass 33, count 2 2006.189.07:38:22.48#ibcon#about to read 5, iclass 33, count 2 2006.189.07:38:22.48#ibcon#read 5, iclass 33, count 2 2006.189.07:38:22.48#ibcon#about to read 6, iclass 33, count 2 2006.189.07:38:22.48#ibcon#read 6, iclass 33, count 2 2006.189.07:38:22.48#ibcon#end of sib2, iclass 33, count 2 2006.189.07:38:22.48#ibcon#*after write, iclass 33, count 2 2006.189.07:38:22.48#ibcon#*before return 0, iclass 33, count 2 2006.189.07:38:22.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:22.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:38:22.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.07:38:22.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:38:22.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:22.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:22.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:22.60#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:38:22.60#ibcon#first serial, iclass 33, count 0 2006.189.07:38:22.60#ibcon#enter sib2, iclass 33, count 0 2006.189.07:38:22.60#ibcon#flushed, iclass 33, count 0 2006.189.07:38:22.60#ibcon#about to write, iclass 33, count 0 2006.189.07:38:22.60#ibcon#wrote, iclass 33, count 0 2006.189.07:38:22.60#ibcon#about to read 3, iclass 33, count 0 2006.189.07:38:22.62#ibcon#read 3, iclass 33, count 0 2006.189.07:38:22.62#ibcon#about to read 4, iclass 33, count 0 2006.189.07:38:22.62#ibcon#read 4, iclass 33, count 0 2006.189.07:38:22.62#ibcon#about to read 5, iclass 33, count 0 2006.189.07:38:22.62#ibcon#read 5, iclass 33, count 0 2006.189.07:38:22.62#ibcon#about to read 6, iclass 33, count 0 2006.189.07:38:22.62#ibcon#read 6, iclass 33, count 0 2006.189.07:38:22.62#ibcon#end of sib2, iclass 33, count 0 2006.189.07:38:22.62#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:38:22.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:38:22.62#ibcon#[27=USB\r\n] 2006.189.07:38:22.62#ibcon#*before write, iclass 33, count 0 2006.189.07:38:22.62#ibcon#enter sib2, iclass 33, count 0 2006.189.07:38:22.62#ibcon#flushed, iclass 33, count 0 2006.189.07:38:22.62#ibcon#about to write, iclass 33, count 0 2006.189.07:38:22.62#ibcon#wrote, iclass 33, count 0 2006.189.07:38:22.62#ibcon#about to read 3, iclass 33, count 0 2006.189.07:38:22.65#ibcon#read 3, iclass 33, count 0 2006.189.07:38:22.65#ibcon#about to read 4, iclass 33, count 0 2006.189.07:38:22.65#ibcon#read 4, iclass 33, count 0 2006.189.07:38:22.65#ibcon#about to read 5, iclass 33, count 0 2006.189.07:38:22.65#ibcon#read 5, iclass 33, count 0 2006.189.07:38:22.65#ibcon#about to read 6, iclass 33, count 0 2006.189.07:38:22.65#ibcon#read 6, iclass 33, count 0 2006.189.07:38:22.65#ibcon#end of sib2, iclass 33, count 0 2006.189.07:38:22.65#ibcon#*after write, iclass 33, count 0 2006.189.07:38:22.65#ibcon#*before return 0, iclass 33, count 0 2006.189.07:38:22.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:22.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:38:22.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:38:22.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:38:22.65$vc4f8/vabw=wide 2006.189.07:38:22.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.07:38:22.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.07:38:22.65#ibcon#ireg 8 cls_cnt 0 2006.189.07:38:22.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:22.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:22.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:22.65#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:38:22.65#ibcon#first serial, iclass 35, count 0 2006.189.07:38:22.65#ibcon#enter sib2, iclass 35, count 0 2006.189.07:38:22.65#ibcon#flushed, iclass 35, count 0 2006.189.07:38:22.65#ibcon#about to write, iclass 35, count 0 2006.189.07:38:22.65#ibcon#wrote, iclass 35, count 0 2006.189.07:38:22.65#ibcon#about to read 3, iclass 35, count 0 2006.189.07:38:22.67#ibcon#read 3, iclass 35, count 0 2006.189.07:38:22.67#ibcon#about to read 4, iclass 35, count 0 2006.189.07:38:22.67#ibcon#read 4, iclass 35, count 0 2006.189.07:38:22.67#ibcon#about to read 5, iclass 35, count 0 2006.189.07:38:22.67#ibcon#read 5, iclass 35, count 0 2006.189.07:38:22.67#ibcon#about to read 6, iclass 35, count 0 2006.189.07:38:22.67#ibcon#read 6, iclass 35, count 0 2006.189.07:38:22.67#ibcon#end of sib2, iclass 35, count 0 2006.189.07:38:22.67#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:38:22.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:38:22.67#ibcon#[25=BW32\r\n] 2006.189.07:38:22.67#ibcon#*before write, iclass 35, count 0 2006.189.07:38:22.67#ibcon#enter sib2, iclass 35, count 0 2006.189.07:38:22.67#ibcon#flushed, iclass 35, count 0 2006.189.07:38:22.67#ibcon#about to write, iclass 35, count 0 2006.189.07:38:22.67#ibcon#wrote, iclass 35, count 0 2006.189.07:38:22.67#ibcon#about to read 3, iclass 35, count 0 2006.189.07:38:22.70#ibcon#read 3, iclass 35, count 0 2006.189.07:38:22.70#ibcon#about to read 4, iclass 35, count 0 2006.189.07:38:22.70#ibcon#read 4, iclass 35, count 0 2006.189.07:38:22.70#ibcon#about to read 5, iclass 35, count 0 2006.189.07:38:22.70#ibcon#read 5, iclass 35, count 0 2006.189.07:38:22.70#ibcon#about to read 6, iclass 35, count 0 2006.189.07:38:22.70#ibcon#read 6, iclass 35, count 0 2006.189.07:38:22.70#ibcon#end of sib2, iclass 35, count 0 2006.189.07:38:22.70#ibcon#*after write, iclass 35, count 0 2006.189.07:38:22.70#ibcon#*before return 0, iclass 35, count 0 2006.189.07:38:22.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:22.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:38:22.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:38:22.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:38:22.70$vc4f8/vbbw=wide 2006.189.07:38:22.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:38:22.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:38:22.70#ibcon#ireg 8 cls_cnt 0 2006.189.07:38:22.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:38:22.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:38:22.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:38:22.78#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:38:22.78#ibcon#first serial, iclass 37, count 0 2006.189.07:38:22.78#ibcon#enter sib2, iclass 37, count 0 2006.189.07:38:22.78#ibcon#flushed, iclass 37, count 0 2006.189.07:38:22.78#ibcon#about to write, iclass 37, count 0 2006.189.07:38:22.78#ibcon#wrote, iclass 37, count 0 2006.189.07:38:22.78#ibcon#about to read 3, iclass 37, count 0 2006.189.07:38:22.79#ibcon#read 3, iclass 37, count 0 2006.189.07:38:22.79#ibcon#about to read 4, iclass 37, count 0 2006.189.07:38:22.79#ibcon#read 4, iclass 37, count 0 2006.189.07:38:22.79#ibcon#about to read 5, iclass 37, count 0 2006.189.07:38:22.79#ibcon#read 5, iclass 37, count 0 2006.189.07:38:22.79#ibcon#about to read 6, iclass 37, count 0 2006.189.07:38:22.79#ibcon#read 6, iclass 37, count 0 2006.189.07:38:22.79#ibcon#end of sib2, iclass 37, count 0 2006.189.07:38:22.79#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:38:22.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:38:22.79#ibcon#[27=BW32\r\n] 2006.189.07:38:22.79#ibcon#*before write, iclass 37, count 0 2006.189.07:38:22.79#ibcon#enter sib2, iclass 37, count 0 2006.189.07:38:22.79#ibcon#flushed, iclass 37, count 0 2006.189.07:38:22.79#ibcon#about to write, iclass 37, count 0 2006.189.07:38:22.79#ibcon#wrote, iclass 37, count 0 2006.189.07:38:22.79#ibcon#about to read 3, iclass 37, count 0 2006.189.07:38:22.82#ibcon#read 3, iclass 37, count 0 2006.189.07:38:22.82#ibcon#about to read 4, iclass 37, count 0 2006.189.07:38:22.82#ibcon#read 4, iclass 37, count 0 2006.189.07:38:22.82#ibcon#about to read 5, iclass 37, count 0 2006.189.07:38:22.82#ibcon#read 5, iclass 37, count 0 2006.189.07:38:22.82#ibcon#about to read 6, iclass 37, count 0 2006.189.07:38:22.82#ibcon#read 6, iclass 37, count 0 2006.189.07:38:22.82#ibcon#end of sib2, iclass 37, count 0 2006.189.07:38:22.82#ibcon#*after write, iclass 37, count 0 2006.189.07:38:22.82#ibcon#*before return 0, iclass 37, count 0 2006.189.07:38:22.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:38:22.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:38:22.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:38:22.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:38:22.82$4f8m12a/ifd4f 2006.189.07:38:22.82$ifd4f/lo= 2006.189.07:38:22.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:38:22.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:38:22.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:38:22.82$ifd4f/patch= 2006.189.07:38:22.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:38:22.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:38:22.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:38:22.83$4f8m12a/"form=m,16.000,1:2 2006.189.07:38:22.83$4f8m12a/"tpicd 2006.189.07:38:22.83$4f8m12a/echo=off 2006.189.07:38:22.83$4f8m12a/xlog=off 2006.189.07:38:22.83:!2006.189.07:38:50 2006.189.07:38:36.14#trakl#Source acquired 2006.189.07:38:38.14#flagr#flagr/antenna,acquired 2006.189.07:38:50.01:preob 2006.189.07:38:51.14/onsource/TRACKING 2006.189.07:38:51.14:!2006.189.07:39:00 2006.189.07:39:00.00:data_valid=on 2006.189.07:39:00.00:midob 2006.189.07:39:00.14/onsource/TRACKING 2006.189.07:39:00.14/wx/26.36,1008.9,87 2006.189.07:39:00.25/cable/+6.4535E-03 2006.189.07:39:01.34/va/01,08,usb,yes,28,30 2006.189.07:39:01.34/va/02,07,usb,yes,28,30 2006.189.07:39:01.34/va/03,06,usb,yes,30,30 2006.189.07:39:01.34/va/04,07,usb,yes,29,31 2006.189.07:39:01.34/va/05,07,usb,yes,31,32 2006.189.07:39:01.34/va/06,06,usb,yes,30,30 2006.189.07:39:01.34/va/07,06,usb,yes,30,30 2006.189.07:39:01.34/va/08,06,usb,yes,32,32 2006.189.07:39:01.57/valo/01,532.99,yes,locked 2006.189.07:39:01.57/valo/02,572.99,yes,locked 2006.189.07:39:01.57/valo/03,672.99,yes,locked 2006.189.07:39:01.57/valo/04,832.99,yes,locked 2006.189.07:39:01.57/valo/05,652.99,yes,locked 2006.189.07:39:01.57/valo/06,772.99,yes,locked 2006.189.07:39:01.57/valo/07,832.99,yes,locked 2006.189.07:39:01.57/valo/08,852.99,yes,locked 2006.189.07:39:02.66/vb/01,04,usb,yes,28,27 2006.189.07:39:02.66/vb/02,04,usb,yes,30,32 2006.189.07:39:02.66/vb/03,04,usb,yes,27,30 2006.189.07:39:02.66/vb/04,04,usb,yes,27,28 2006.189.07:39:02.66/vb/05,04,usb,yes,26,30 2006.189.07:39:02.66/vb/06,04,usb,yes,27,30 2006.189.07:39:02.66/vb/07,04,usb,yes,29,29 2006.189.07:39:02.66/vb/08,04,usb,yes,27,30 2006.189.07:39:02.89/vblo/01,632.99,yes,locked 2006.189.07:39:02.89/vblo/02,640.99,yes,locked 2006.189.07:39:02.89/vblo/03,656.99,yes,locked 2006.189.07:39:02.89/vblo/04,712.99,yes,locked 2006.189.07:39:02.89/vblo/05,744.99,yes,locked 2006.189.07:39:02.89/vblo/06,752.99,yes,locked 2006.189.07:39:02.89/vblo/07,734.99,yes,locked 2006.189.07:39:02.89/vblo/08,744.99,yes,locked 2006.189.07:39:03.04/vabw/8 2006.189.07:39:03.19/vbbw/8 2006.189.07:39:03.28/xfe/off,on,15.0 2006.189.07:39:03.66/ifatt/23,28,28,28 2006.189.07:39:04.07/fmout-gps/S +2.97E-07 2006.189.07:39:04.16:!2006.189.07:40:00 2006.189.07:40:00.01:data_valid=off 2006.189.07:40:00.02:postob 2006.189.07:40:00.12/cable/+6.4540E-03 2006.189.07:40:00.13/wx/26.33,1008.9,86 2006.189.07:40:01.07/fmout-gps/S +2.98E-07 2006.189.07:40:01.08:scan_name=189-0740,k06189,60 2006.189.07:40:01.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.189.07:40:01.14#flagr#flagr/antenna,new-source 2006.189.07:40:02.14:checkk5 2006.189.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:40:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:40:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:40:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:40:04.03/chk_obsdata//k5ts1/T1890739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:40:04.41/chk_obsdata//k5ts2/T1890739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:40:04.78/chk_obsdata//k5ts3/T1890739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:40:05.16/chk_obsdata//k5ts4/T1890739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:40:05.85/k5log//k5ts1_log_newline 2006.189.07:40:06.55/k5log//k5ts2_log_newline 2006.189.07:40:07.25/k5log//k5ts3_log_newline 2006.189.07:40:07.94/k5log//k5ts4_log_newline 2006.189.07:40:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:40:07.97:4f8m12a=1 2006.189.07:40:07.97$4f8m12a/echo=on 2006.189.07:40:07.97$4f8m12a/pcalon 2006.189.07:40:07.97$pcalon/"no phase cal control is implemented here 2006.189.07:40:07.97$4f8m12a/"tpicd=stop 2006.189.07:40:07.97$4f8m12a/vc4f8 2006.189.07:40:07.97$vc4f8/valo=1,532.99 2006.189.07:40:07.97#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.07:40:07.97#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.07:40:07.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:07.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:07.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:07.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:07.97#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:40:07.97#ibcon#first serial, iclass 12, count 0 2006.189.07:40:07.97#ibcon#enter sib2, iclass 12, count 0 2006.189.07:40:07.97#ibcon#flushed, iclass 12, count 0 2006.189.07:40:07.97#ibcon#about to write, iclass 12, count 0 2006.189.07:40:07.97#ibcon#wrote, iclass 12, count 0 2006.189.07:40:07.97#ibcon#about to read 3, iclass 12, count 0 2006.189.07:40:08.02#ibcon#read 3, iclass 12, count 0 2006.189.07:40:08.02#ibcon#about to read 4, iclass 12, count 0 2006.189.07:40:08.02#ibcon#read 4, iclass 12, count 0 2006.189.07:40:08.02#ibcon#about to read 5, iclass 12, count 0 2006.189.07:40:08.02#ibcon#read 5, iclass 12, count 0 2006.189.07:40:08.02#ibcon#about to read 6, iclass 12, count 0 2006.189.07:40:08.02#ibcon#read 6, iclass 12, count 0 2006.189.07:40:08.02#ibcon#end of sib2, iclass 12, count 0 2006.189.07:40:08.02#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:40:08.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:40:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:40:08.02#ibcon#*before write, iclass 12, count 0 2006.189.07:40:08.02#ibcon#enter sib2, iclass 12, count 0 2006.189.07:40:08.02#ibcon#flushed, iclass 12, count 0 2006.189.07:40:08.02#ibcon#about to write, iclass 12, count 0 2006.189.07:40:08.02#ibcon#wrote, iclass 12, count 0 2006.189.07:40:08.02#ibcon#about to read 3, iclass 12, count 0 2006.189.07:40:08.07#ibcon#read 3, iclass 12, count 0 2006.189.07:40:08.07#ibcon#about to read 4, iclass 12, count 0 2006.189.07:40:08.07#ibcon#read 4, iclass 12, count 0 2006.189.07:40:08.07#ibcon#about to read 5, iclass 12, count 0 2006.189.07:40:08.07#ibcon#read 5, iclass 12, count 0 2006.189.07:40:08.07#ibcon#about to read 6, iclass 12, count 0 2006.189.07:40:08.07#ibcon#read 6, iclass 12, count 0 2006.189.07:40:08.07#ibcon#end of sib2, iclass 12, count 0 2006.189.07:40:08.07#ibcon#*after write, iclass 12, count 0 2006.189.07:40:08.07#ibcon#*before return 0, iclass 12, count 0 2006.189.07:40:08.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:08.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:08.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:40:08.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:40:08.07$vc4f8/va=1,8 2006.189.07:40:08.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.07:40:08.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.07:40:08.07#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:08.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:08.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:08.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:08.07#ibcon#enter wrdev, iclass 14, count 2 2006.189.07:40:08.07#ibcon#first serial, iclass 14, count 2 2006.189.07:40:08.07#ibcon#enter sib2, iclass 14, count 2 2006.189.07:40:08.07#ibcon#flushed, iclass 14, count 2 2006.189.07:40:08.07#ibcon#about to write, iclass 14, count 2 2006.189.07:40:08.07#ibcon#wrote, iclass 14, count 2 2006.189.07:40:08.07#ibcon#about to read 3, iclass 14, count 2 2006.189.07:40:08.09#ibcon#read 3, iclass 14, count 2 2006.189.07:40:08.09#ibcon#about to read 4, iclass 14, count 2 2006.189.07:40:08.09#ibcon#read 4, iclass 14, count 2 2006.189.07:40:08.09#ibcon#about to read 5, iclass 14, count 2 2006.189.07:40:08.09#ibcon#read 5, iclass 14, count 2 2006.189.07:40:08.09#ibcon#about to read 6, iclass 14, count 2 2006.189.07:40:08.09#ibcon#read 6, iclass 14, count 2 2006.189.07:40:08.09#ibcon#end of sib2, iclass 14, count 2 2006.189.07:40:08.09#ibcon#*mode == 0, iclass 14, count 2 2006.189.07:40:08.09#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.07:40:08.09#ibcon#[25=AT01-08\r\n] 2006.189.07:40:08.09#ibcon#*before write, iclass 14, count 2 2006.189.07:40:08.09#ibcon#enter sib2, iclass 14, count 2 2006.189.07:40:08.09#ibcon#flushed, iclass 14, count 2 2006.189.07:40:08.09#ibcon#about to write, iclass 14, count 2 2006.189.07:40:08.09#ibcon#wrote, iclass 14, count 2 2006.189.07:40:08.09#ibcon#about to read 3, iclass 14, count 2 2006.189.07:40:08.12#ibcon#read 3, iclass 14, count 2 2006.189.07:40:08.12#ibcon#about to read 4, iclass 14, count 2 2006.189.07:40:08.12#ibcon#read 4, iclass 14, count 2 2006.189.07:40:08.12#ibcon#about to read 5, iclass 14, count 2 2006.189.07:40:08.12#ibcon#read 5, iclass 14, count 2 2006.189.07:40:08.12#ibcon#about to read 6, iclass 14, count 2 2006.189.07:40:08.12#ibcon#read 6, iclass 14, count 2 2006.189.07:40:08.12#ibcon#end of sib2, iclass 14, count 2 2006.189.07:40:08.12#ibcon#*after write, iclass 14, count 2 2006.189.07:40:08.12#ibcon#*before return 0, iclass 14, count 2 2006.189.07:40:08.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:08.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:08.12#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.07:40:08.12#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:08.12#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:08.24#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:08.24#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:08.24#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:40:08.24#ibcon#first serial, iclass 14, count 0 2006.189.07:40:08.24#ibcon#enter sib2, iclass 14, count 0 2006.189.07:40:08.24#ibcon#flushed, iclass 14, count 0 2006.189.07:40:08.24#ibcon#about to write, iclass 14, count 0 2006.189.07:40:08.24#ibcon#wrote, iclass 14, count 0 2006.189.07:40:08.24#ibcon#about to read 3, iclass 14, count 0 2006.189.07:40:08.26#ibcon#read 3, iclass 14, count 0 2006.189.07:40:08.26#ibcon#about to read 4, iclass 14, count 0 2006.189.07:40:08.26#ibcon#read 4, iclass 14, count 0 2006.189.07:40:08.26#ibcon#about to read 5, iclass 14, count 0 2006.189.07:40:08.26#ibcon#read 5, iclass 14, count 0 2006.189.07:40:08.26#ibcon#about to read 6, iclass 14, count 0 2006.189.07:40:08.26#ibcon#read 6, iclass 14, count 0 2006.189.07:40:08.26#ibcon#end of sib2, iclass 14, count 0 2006.189.07:40:08.26#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:40:08.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:40:08.26#ibcon#[25=USB\r\n] 2006.189.07:40:08.26#ibcon#*before write, iclass 14, count 0 2006.189.07:40:08.26#ibcon#enter sib2, iclass 14, count 0 2006.189.07:40:08.26#ibcon#flushed, iclass 14, count 0 2006.189.07:40:08.26#ibcon#about to write, iclass 14, count 0 2006.189.07:40:08.26#ibcon#wrote, iclass 14, count 0 2006.189.07:40:08.26#ibcon#about to read 3, iclass 14, count 0 2006.189.07:40:08.29#ibcon#read 3, iclass 14, count 0 2006.189.07:40:08.29#ibcon#about to read 4, iclass 14, count 0 2006.189.07:40:08.29#ibcon#read 4, iclass 14, count 0 2006.189.07:40:08.29#ibcon#about to read 5, iclass 14, count 0 2006.189.07:40:08.29#ibcon#read 5, iclass 14, count 0 2006.189.07:40:08.29#ibcon#about to read 6, iclass 14, count 0 2006.189.07:40:08.29#ibcon#read 6, iclass 14, count 0 2006.189.07:40:08.29#ibcon#end of sib2, iclass 14, count 0 2006.189.07:40:08.29#ibcon#*after write, iclass 14, count 0 2006.189.07:40:08.29#ibcon#*before return 0, iclass 14, count 0 2006.189.07:40:08.29#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:08.29#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:08.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:40:08.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:40:08.29$vc4f8/valo=2,572.99 2006.189.07:40:08.29#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.07:40:08.29#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.07:40:08.29#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:08.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:08.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:08.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:08.29#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:40:08.29#ibcon#first serial, iclass 16, count 0 2006.189.07:40:08.29#ibcon#enter sib2, iclass 16, count 0 2006.189.07:40:08.29#ibcon#flushed, iclass 16, count 0 2006.189.07:40:08.29#ibcon#about to write, iclass 16, count 0 2006.189.07:40:08.29#ibcon#wrote, iclass 16, count 0 2006.189.07:40:08.29#ibcon#about to read 3, iclass 16, count 0 2006.189.07:40:08.31#ibcon#read 3, iclass 16, count 0 2006.189.07:40:08.31#ibcon#about to read 4, iclass 16, count 0 2006.189.07:40:08.31#ibcon#read 4, iclass 16, count 0 2006.189.07:40:08.31#ibcon#about to read 5, iclass 16, count 0 2006.189.07:40:08.31#ibcon#read 5, iclass 16, count 0 2006.189.07:40:08.31#ibcon#about to read 6, iclass 16, count 0 2006.189.07:40:08.31#ibcon#read 6, iclass 16, count 0 2006.189.07:40:08.31#ibcon#end of sib2, iclass 16, count 0 2006.189.07:40:08.31#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:40:08.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:40:08.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:40:08.31#ibcon#*before write, iclass 16, count 0 2006.189.07:40:08.31#ibcon#enter sib2, iclass 16, count 0 2006.189.07:40:08.31#ibcon#flushed, iclass 16, count 0 2006.189.07:40:08.31#ibcon#about to write, iclass 16, count 0 2006.189.07:40:08.31#ibcon#wrote, iclass 16, count 0 2006.189.07:40:08.31#ibcon#about to read 3, iclass 16, count 0 2006.189.07:40:08.36#ibcon#read 3, iclass 16, count 0 2006.189.07:40:08.36#ibcon#about to read 4, iclass 16, count 0 2006.189.07:40:08.36#ibcon#read 4, iclass 16, count 0 2006.189.07:40:08.36#ibcon#about to read 5, iclass 16, count 0 2006.189.07:40:08.36#ibcon#read 5, iclass 16, count 0 2006.189.07:40:08.36#ibcon#about to read 6, iclass 16, count 0 2006.189.07:40:08.36#ibcon#read 6, iclass 16, count 0 2006.189.07:40:08.36#ibcon#end of sib2, iclass 16, count 0 2006.189.07:40:08.36#ibcon#*after write, iclass 16, count 0 2006.189.07:40:08.36#ibcon#*before return 0, iclass 16, count 0 2006.189.07:40:08.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:08.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:08.36#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:40:08.36#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:40:08.36$vc4f8/va=2,7 2006.189.07:40:08.36#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.07:40:08.36#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.07:40:08.36#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:08.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:08.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:08.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:08.40#ibcon#enter wrdev, iclass 18, count 2 2006.189.07:40:08.40#ibcon#first serial, iclass 18, count 2 2006.189.07:40:08.40#ibcon#enter sib2, iclass 18, count 2 2006.189.07:40:08.40#ibcon#flushed, iclass 18, count 2 2006.189.07:40:08.40#ibcon#about to write, iclass 18, count 2 2006.189.07:40:08.40#ibcon#wrote, iclass 18, count 2 2006.189.07:40:08.40#ibcon#about to read 3, iclass 18, count 2 2006.189.07:40:08.42#ibcon#read 3, iclass 18, count 2 2006.189.07:40:08.42#ibcon#about to read 4, iclass 18, count 2 2006.189.07:40:08.42#ibcon#read 4, iclass 18, count 2 2006.189.07:40:08.42#ibcon#about to read 5, iclass 18, count 2 2006.189.07:40:08.42#ibcon#read 5, iclass 18, count 2 2006.189.07:40:08.42#ibcon#about to read 6, iclass 18, count 2 2006.189.07:40:08.42#ibcon#read 6, iclass 18, count 2 2006.189.07:40:08.42#ibcon#end of sib2, iclass 18, count 2 2006.189.07:40:08.42#ibcon#*mode == 0, iclass 18, count 2 2006.189.07:40:08.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.07:40:08.42#ibcon#[25=AT02-07\r\n] 2006.189.07:40:08.42#ibcon#*before write, iclass 18, count 2 2006.189.07:40:08.42#ibcon#enter sib2, iclass 18, count 2 2006.189.07:40:08.42#ibcon#flushed, iclass 18, count 2 2006.189.07:40:08.42#ibcon#about to write, iclass 18, count 2 2006.189.07:40:08.42#ibcon#wrote, iclass 18, count 2 2006.189.07:40:08.42#ibcon#about to read 3, iclass 18, count 2 2006.189.07:40:08.45#ibcon#read 3, iclass 18, count 2 2006.189.07:40:08.45#ibcon#about to read 4, iclass 18, count 2 2006.189.07:40:08.45#ibcon#read 4, iclass 18, count 2 2006.189.07:40:08.45#ibcon#about to read 5, iclass 18, count 2 2006.189.07:40:08.45#ibcon#read 5, iclass 18, count 2 2006.189.07:40:08.45#ibcon#about to read 6, iclass 18, count 2 2006.189.07:40:08.45#ibcon#read 6, iclass 18, count 2 2006.189.07:40:08.45#ibcon#end of sib2, iclass 18, count 2 2006.189.07:40:08.45#ibcon#*after write, iclass 18, count 2 2006.189.07:40:08.45#ibcon#*before return 0, iclass 18, count 2 2006.189.07:40:08.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:08.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:08.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.07:40:08.45#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:08.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:08.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:08.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:08.57#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:40:08.57#ibcon#first serial, iclass 18, count 0 2006.189.07:40:08.57#ibcon#enter sib2, iclass 18, count 0 2006.189.07:40:08.57#ibcon#flushed, iclass 18, count 0 2006.189.07:40:08.57#ibcon#about to write, iclass 18, count 0 2006.189.07:40:08.57#ibcon#wrote, iclass 18, count 0 2006.189.07:40:08.57#ibcon#about to read 3, iclass 18, count 0 2006.189.07:40:08.59#ibcon#read 3, iclass 18, count 0 2006.189.07:40:08.59#ibcon#about to read 4, iclass 18, count 0 2006.189.07:40:08.59#ibcon#read 4, iclass 18, count 0 2006.189.07:40:08.59#ibcon#about to read 5, iclass 18, count 0 2006.189.07:40:08.59#ibcon#read 5, iclass 18, count 0 2006.189.07:40:08.59#ibcon#about to read 6, iclass 18, count 0 2006.189.07:40:08.59#ibcon#read 6, iclass 18, count 0 2006.189.07:40:08.59#ibcon#end of sib2, iclass 18, count 0 2006.189.07:40:08.59#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:40:08.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:40:08.59#ibcon#[25=USB\r\n] 2006.189.07:40:08.59#ibcon#*before write, iclass 18, count 0 2006.189.07:40:08.59#ibcon#enter sib2, iclass 18, count 0 2006.189.07:40:08.59#ibcon#flushed, iclass 18, count 0 2006.189.07:40:08.59#ibcon#about to write, iclass 18, count 0 2006.189.07:40:08.59#ibcon#wrote, iclass 18, count 0 2006.189.07:40:08.59#ibcon#about to read 3, iclass 18, count 0 2006.189.07:40:08.62#ibcon#read 3, iclass 18, count 0 2006.189.07:40:08.62#ibcon#about to read 4, iclass 18, count 0 2006.189.07:40:08.62#ibcon#read 4, iclass 18, count 0 2006.189.07:40:08.62#ibcon#about to read 5, iclass 18, count 0 2006.189.07:40:08.62#ibcon#read 5, iclass 18, count 0 2006.189.07:40:08.62#ibcon#about to read 6, iclass 18, count 0 2006.189.07:40:08.62#ibcon#read 6, iclass 18, count 0 2006.189.07:40:08.62#ibcon#end of sib2, iclass 18, count 0 2006.189.07:40:08.62#ibcon#*after write, iclass 18, count 0 2006.189.07:40:08.62#ibcon#*before return 0, iclass 18, count 0 2006.189.07:40:08.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:08.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:08.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:40:08.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:40:08.62$vc4f8/valo=3,672.99 2006.189.07:40:08.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.07:40:08.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.07:40:08.62#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:08.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:08.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:08.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:08.62#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:40:08.62#ibcon#first serial, iclass 20, count 0 2006.189.07:40:08.62#ibcon#enter sib2, iclass 20, count 0 2006.189.07:40:08.62#ibcon#flushed, iclass 20, count 0 2006.189.07:40:08.62#ibcon#about to write, iclass 20, count 0 2006.189.07:40:08.62#ibcon#wrote, iclass 20, count 0 2006.189.07:40:08.62#ibcon#about to read 3, iclass 20, count 0 2006.189.07:40:08.64#ibcon#read 3, iclass 20, count 0 2006.189.07:40:08.64#ibcon#about to read 4, iclass 20, count 0 2006.189.07:40:08.64#ibcon#read 4, iclass 20, count 0 2006.189.07:40:08.64#ibcon#about to read 5, iclass 20, count 0 2006.189.07:40:08.64#ibcon#read 5, iclass 20, count 0 2006.189.07:40:08.64#ibcon#about to read 6, iclass 20, count 0 2006.189.07:40:08.64#ibcon#read 6, iclass 20, count 0 2006.189.07:40:08.64#ibcon#end of sib2, iclass 20, count 0 2006.189.07:40:08.64#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:40:08.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:40:08.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:40:08.64#ibcon#*before write, iclass 20, count 0 2006.189.07:40:08.64#ibcon#enter sib2, iclass 20, count 0 2006.189.07:40:08.64#ibcon#flushed, iclass 20, count 0 2006.189.07:40:08.64#ibcon#about to write, iclass 20, count 0 2006.189.07:40:08.64#ibcon#wrote, iclass 20, count 0 2006.189.07:40:08.64#ibcon#about to read 3, iclass 20, count 0 2006.189.07:40:08.69#ibcon#read 3, iclass 20, count 0 2006.189.07:40:08.69#ibcon#about to read 4, iclass 20, count 0 2006.189.07:40:08.69#ibcon#read 4, iclass 20, count 0 2006.189.07:40:08.69#ibcon#about to read 5, iclass 20, count 0 2006.189.07:40:08.69#ibcon#read 5, iclass 20, count 0 2006.189.07:40:08.69#ibcon#about to read 6, iclass 20, count 0 2006.189.07:40:08.69#ibcon#read 6, iclass 20, count 0 2006.189.07:40:08.69#ibcon#end of sib2, iclass 20, count 0 2006.189.07:40:08.69#ibcon#*after write, iclass 20, count 0 2006.189.07:40:08.69#ibcon#*before return 0, iclass 20, count 0 2006.189.07:40:08.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:08.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:08.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:40:08.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:40:08.69$vc4f8/va=3,6 2006.189.07:40:08.69#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.07:40:08.69#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.07:40:08.69#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:08.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:08.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:08.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:08.73#ibcon#enter wrdev, iclass 22, count 2 2006.189.07:40:08.73#ibcon#first serial, iclass 22, count 2 2006.189.07:40:08.73#ibcon#enter sib2, iclass 22, count 2 2006.189.07:40:08.73#ibcon#flushed, iclass 22, count 2 2006.189.07:40:08.73#ibcon#about to write, iclass 22, count 2 2006.189.07:40:08.73#ibcon#wrote, iclass 22, count 2 2006.189.07:40:08.73#ibcon#about to read 3, iclass 22, count 2 2006.189.07:40:08.75#ibcon#read 3, iclass 22, count 2 2006.189.07:40:08.75#ibcon#about to read 4, iclass 22, count 2 2006.189.07:40:08.75#ibcon#read 4, iclass 22, count 2 2006.189.07:40:08.75#ibcon#about to read 5, iclass 22, count 2 2006.189.07:40:08.75#ibcon#read 5, iclass 22, count 2 2006.189.07:40:08.75#ibcon#about to read 6, iclass 22, count 2 2006.189.07:40:08.75#ibcon#read 6, iclass 22, count 2 2006.189.07:40:08.75#ibcon#end of sib2, iclass 22, count 2 2006.189.07:40:08.75#ibcon#*mode == 0, iclass 22, count 2 2006.189.07:40:08.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.07:40:08.75#ibcon#[25=AT03-06\r\n] 2006.189.07:40:08.75#ibcon#*before write, iclass 22, count 2 2006.189.07:40:08.75#ibcon#enter sib2, iclass 22, count 2 2006.189.07:40:08.75#ibcon#flushed, iclass 22, count 2 2006.189.07:40:08.75#ibcon#about to write, iclass 22, count 2 2006.189.07:40:08.75#ibcon#wrote, iclass 22, count 2 2006.189.07:40:08.75#ibcon#about to read 3, iclass 22, count 2 2006.189.07:40:08.78#ibcon#read 3, iclass 22, count 2 2006.189.07:40:08.78#ibcon#about to read 4, iclass 22, count 2 2006.189.07:40:08.78#ibcon#read 4, iclass 22, count 2 2006.189.07:40:08.78#ibcon#about to read 5, iclass 22, count 2 2006.189.07:40:08.78#ibcon#read 5, iclass 22, count 2 2006.189.07:40:08.78#ibcon#about to read 6, iclass 22, count 2 2006.189.07:40:08.78#ibcon#read 6, iclass 22, count 2 2006.189.07:40:08.78#ibcon#end of sib2, iclass 22, count 2 2006.189.07:40:08.78#ibcon#*after write, iclass 22, count 2 2006.189.07:40:08.78#ibcon#*before return 0, iclass 22, count 2 2006.189.07:40:08.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:08.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:08.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.07:40:08.78#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:08.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:08.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:08.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:08.90#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:40:08.90#ibcon#first serial, iclass 22, count 0 2006.189.07:40:08.90#ibcon#enter sib2, iclass 22, count 0 2006.189.07:40:08.90#ibcon#flushed, iclass 22, count 0 2006.189.07:40:08.90#ibcon#about to write, iclass 22, count 0 2006.189.07:40:08.90#ibcon#wrote, iclass 22, count 0 2006.189.07:40:08.90#ibcon#about to read 3, iclass 22, count 0 2006.189.07:40:08.92#ibcon#read 3, iclass 22, count 0 2006.189.07:40:08.92#ibcon#about to read 4, iclass 22, count 0 2006.189.07:40:08.92#ibcon#read 4, iclass 22, count 0 2006.189.07:40:08.92#ibcon#about to read 5, iclass 22, count 0 2006.189.07:40:08.92#ibcon#read 5, iclass 22, count 0 2006.189.07:40:08.92#ibcon#about to read 6, iclass 22, count 0 2006.189.07:40:08.92#ibcon#read 6, iclass 22, count 0 2006.189.07:40:08.92#ibcon#end of sib2, iclass 22, count 0 2006.189.07:40:08.92#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:40:08.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:40:08.92#ibcon#[25=USB\r\n] 2006.189.07:40:08.92#ibcon#*before write, iclass 22, count 0 2006.189.07:40:08.92#ibcon#enter sib2, iclass 22, count 0 2006.189.07:40:08.92#ibcon#flushed, iclass 22, count 0 2006.189.07:40:08.92#ibcon#about to write, iclass 22, count 0 2006.189.07:40:08.92#ibcon#wrote, iclass 22, count 0 2006.189.07:40:08.92#ibcon#about to read 3, iclass 22, count 0 2006.189.07:40:08.95#ibcon#read 3, iclass 22, count 0 2006.189.07:40:08.95#ibcon#about to read 4, iclass 22, count 0 2006.189.07:40:08.95#ibcon#read 4, iclass 22, count 0 2006.189.07:40:08.95#ibcon#about to read 5, iclass 22, count 0 2006.189.07:40:08.95#ibcon#read 5, iclass 22, count 0 2006.189.07:40:08.95#ibcon#about to read 6, iclass 22, count 0 2006.189.07:40:08.95#ibcon#read 6, iclass 22, count 0 2006.189.07:40:08.95#ibcon#end of sib2, iclass 22, count 0 2006.189.07:40:08.95#ibcon#*after write, iclass 22, count 0 2006.189.07:40:08.95#ibcon#*before return 0, iclass 22, count 0 2006.189.07:40:08.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:08.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:08.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:40:08.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:40:08.95$vc4f8/valo=4,832.99 2006.189.07:40:08.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.07:40:08.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.07:40:08.95#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:08.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:08.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:08.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:08.95#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:40:08.95#ibcon#first serial, iclass 24, count 0 2006.189.07:40:08.95#ibcon#enter sib2, iclass 24, count 0 2006.189.07:40:08.95#ibcon#flushed, iclass 24, count 0 2006.189.07:40:08.95#ibcon#about to write, iclass 24, count 0 2006.189.07:40:08.95#ibcon#wrote, iclass 24, count 0 2006.189.07:40:08.95#ibcon#about to read 3, iclass 24, count 0 2006.189.07:40:08.97#ibcon#read 3, iclass 24, count 0 2006.189.07:40:08.97#ibcon#about to read 4, iclass 24, count 0 2006.189.07:40:08.97#ibcon#read 4, iclass 24, count 0 2006.189.07:40:08.97#ibcon#about to read 5, iclass 24, count 0 2006.189.07:40:08.97#ibcon#read 5, iclass 24, count 0 2006.189.07:40:08.97#ibcon#about to read 6, iclass 24, count 0 2006.189.07:40:08.97#ibcon#read 6, iclass 24, count 0 2006.189.07:40:08.97#ibcon#end of sib2, iclass 24, count 0 2006.189.07:40:08.97#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:40:08.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:40:08.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:40:08.97#ibcon#*before write, iclass 24, count 0 2006.189.07:40:08.97#ibcon#enter sib2, iclass 24, count 0 2006.189.07:40:08.97#ibcon#flushed, iclass 24, count 0 2006.189.07:40:08.97#ibcon#about to write, iclass 24, count 0 2006.189.07:40:08.97#ibcon#wrote, iclass 24, count 0 2006.189.07:40:08.97#ibcon#about to read 3, iclass 24, count 0 2006.189.07:40:09.01#ibcon#read 3, iclass 24, count 0 2006.189.07:40:09.01#ibcon#about to read 4, iclass 24, count 0 2006.189.07:40:09.01#ibcon#read 4, iclass 24, count 0 2006.189.07:40:09.01#ibcon#about to read 5, iclass 24, count 0 2006.189.07:40:09.01#ibcon#read 5, iclass 24, count 0 2006.189.07:40:09.01#ibcon#about to read 6, iclass 24, count 0 2006.189.07:40:09.01#ibcon#read 6, iclass 24, count 0 2006.189.07:40:09.01#ibcon#end of sib2, iclass 24, count 0 2006.189.07:40:09.01#ibcon#*after write, iclass 24, count 0 2006.189.07:40:09.01#ibcon#*before return 0, iclass 24, count 0 2006.189.07:40:09.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:09.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:09.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:40:09.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:40:09.01$vc4f8/va=4,7 2006.189.07:40:09.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.07:40:09.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.07:40:09.01#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:09.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:09.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:09.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:09.07#ibcon#enter wrdev, iclass 26, count 2 2006.189.07:40:09.07#ibcon#first serial, iclass 26, count 2 2006.189.07:40:09.07#ibcon#enter sib2, iclass 26, count 2 2006.189.07:40:09.07#ibcon#flushed, iclass 26, count 2 2006.189.07:40:09.07#ibcon#about to write, iclass 26, count 2 2006.189.07:40:09.07#ibcon#wrote, iclass 26, count 2 2006.189.07:40:09.07#ibcon#about to read 3, iclass 26, count 2 2006.189.07:40:09.09#ibcon#read 3, iclass 26, count 2 2006.189.07:40:09.09#ibcon#about to read 4, iclass 26, count 2 2006.189.07:40:09.09#ibcon#read 4, iclass 26, count 2 2006.189.07:40:09.09#ibcon#about to read 5, iclass 26, count 2 2006.189.07:40:09.09#ibcon#read 5, iclass 26, count 2 2006.189.07:40:09.09#ibcon#about to read 6, iclass 26, count 2 2006.189.07:40:09.09#ibcon#read 6, iclass 26, count 2 2006.189.07:40:09.09#ibcon#end of sib2, iclass 26, count 2 2006.189.07:40:09.09#ibcon#*mode == 0, iclass 26, count 2 2006.189.07:40:09.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.07:40:09.09#ibcon#[25=AT04-07\r\n] 2006.189.07:40:09.09#ibcon#*before write, iclass 26, count 2 2006.189.07:40:09.09#ibcon#enter sib2, iclass 26, count 2 2006.189.07:40:09.09#ibcon#flushed, iclass 26, count 2 2006.189.07:40:09.09#ibcon#about to write, iclass 26, count 2 2006.189.07:40:09.09#ibcon#wrote, iclass 26, count 2 2006.189.07:40:09.09#ibcon#about to read 3, iclass 26, count 2 2006.189.07:40:09.12#ibcon#read 3, iclass 26, count 2 2006.189.07:40:09.12#ibcon#about to read 4, iclass 26, count 2 2006.189.07:40:09.12#ibcon#read 4, iclass 26, count 2 2006.189.07:40:09.12#ibcon#about to read 5, iclass 26, count 2 2006.189.07:40:09.12#ibcon#read 5, iclass 26, count 2 2006.189.07:40:09.12#ibcon#about to read 6, iclass 26, count 2 2006.189.07:40:09.12#ibcon#read 6, iclass 26, count 2 2006.189.07:40:09.12#ibcon#end of sib2, iclass 26, count 2 2006.189.07:40:09.12#ibcon#*after write, iclass 26, count 2 2006.189.07:40:09.12#ibcon#*before return 0, iclass 26, count 2 2006.189.07:40:09.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:09.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:09.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.07:40:09.12#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:09.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:09.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:09.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:09.24#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:40:09.24#ibcon#first serial, iclass 26, count 0 2006.189.07:40:09.24#ibcon#enter sib2, iclass 26, count 0 2006.189.07:40:09.24#ibcon#flushed, iclass 26, count 0 2006.189.07:40:09.24#ibcon#about to write, iclass 26, count 0 2006.189.07:40:09.24#ibcon#wrote, iclass 26, count 0 2006.189.07:40:09.24#ibcon#about to read 3, iclass 26, count 0 2006.189.07:40:09.26#ibcon#read 3, iclass 26, count 0 2006.189.07:40:09.26#ibcon#about to read 4, iclass 26, count 0 2006.189.07:40:09.26#ibcon#read 4, iclass 26, count 0 2006.189.07:40:09.26#ibcon#about to read 5, iclass 26, count 0 2006.189.07:40:09.26#ibcon#read 5, iclass 26, count 0 2006.189.07:40:09.26#ibcon#about to read 6, iclass 26, count 0 2006.189.07:40:09.26#ibcon#read 6, iclass 26, count 0 2006.189.07:40:09.26#ibcon#end of sib2, iclass 26, count 0 2006.189.07:40:09.26#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:40:09.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:40:09.26#ibcon#[25=USB\r\n] 2006.189.07:40:09.26#ibcon#*before write, iclass 26, count 0 2006.189.07:40:09.26#ibcon#enter sib2, iclass 26, count 0 2006.189.07:40:09.26#ibcon#flushed, iclass 26, count 0 2006.189.07:40:09.26#ibcon#about to write, iclass 26, count 0 2006.189.07:40:09.26#ibcon#wrote, iclass 26, count 0 2006.189.07:40:09.26#ibcon#about to read 3, iclass 26, count 0 2006.189.07:40:09.29#ibcon#read 3, iclass 26, count 0 2006.189.07:40:09.29#ibcon#about to read 4, iclass 26, count 0 2006.189.07:40:09.29#ibcon#read 4, iclass 26, count 0 2006.189.07:40:09.29#ibcon#about to read 5, iclass 26, count 0 2006.189.07:40:09.29#ibcon#read 5, iclass 26, count 0 2006.189.07:40:09.29#ibcon#about to read 6, iclass 26, count 0 2006.189.07:40:09.29#ibcon#read 6, iclass 26, count 0 2006.189.07:40:09.29#ibcon#end of sib2, iclass 26, count 0 2006.189.07:40:09.29#ibcon#*after write, iclass 26, count 0 2006.189.07:40:09.29#ibcon#*before return 0, iclass 26, count 0 2006.189.07:40:09.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:09.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:09.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:40:09.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:40:09.29$vc4f8/valo=5,652.99 2006.189.07:40:09.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.07:40:09.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.07:40:09.29#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:09.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:09.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:09.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:09.29#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:40:09.29#ibcon#first serial, iclass 28, count 0 2006.189.07:40:09.29#ibcon#enter sib2, iclass 28, count 0 2006.189.07:40:09.29#ibcon#flushed, iclass 28, count 0 2006.189.07:40:09.29#ibcon#about to write, iclass 28, count 0 2006.189.07:40:09.29#ibcon#wrote, iclass 28, count 0 2006.189.07:40:09.29#ibcon#about to read 3, iclass 28, count 0 2006.189.07:40:09.31#ibcon#read 3, iclass 28, count 0 2006.189.07:40:09.31#ibcon#about to read 4, iclass 28, count 0 2006.189.07:40:09.31#ibcon#read 4, iclass 28, count 0 2006.189.07:40:09.31#ibcon#about to read 5, iclass 28, count 0 2006.189.07:40:09.31#ibcon#read 5, iclass 28, count 0 2006.189.07:40:09.31#ibcon#about to read 6, iclass 28, count 0 2006.189.07:40:09.31#ibcon#read 6, iclass 28, count 0 2006.189.07:40:09.31#ibcon#end of sib2, iclass 28, count 0 2006.189.07:40:09.31#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:40:09.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:40:09.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:40:09.31#ibcon#*before write, iclass 28, count 0 2006.189.07:40:09.31#ibcon#enter sib2, iclass 28, count 0 2006.189.07:40:09.31#ibcon#flushed, iclass 28, count 0 2006.189.07:40:09.31#ibcon#about to write, iclass 28, count 0 2006.189.07:40:09.31#ibcon#wrote, iclass 28, count 0 2006.189.07:40:09.31#ibcon#about to read 3, iclass 28, count 0 2006.189.07:40:09.35#ibcon#read 3, iclass 28, count 0 2006.189.07:40:09.35#ibcon#about to read 4, iclass 28, count 0 2006.189.07:40:09.35#ibcon#read 4, iclass 28, count 0 2006.189.07:40:09.35#ibcon#about to read 5, iclass 28, count 0 2006.189.07:40:09.35#ibcon#read 5, iclass 28, count 0 2006.189.07:40:09.35#ibcon#about to read 6, iclass 28, count 0 2006.189.07:40:09.35#ibcon#read 6, iclass 28, count 0 2006.189.07:40:09.35#ibcon#end of sib2, iclass 28, count 0 2006.189.07:40:09.35#ibcon#*after write, iclass 28, count 0 2006.189.07:40:09.35#ibcon#*before return 0, iclass 28, count 0 2006.189.07:40:09.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:09.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:09.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:40:09.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:40:09.35$vc4f8/va=5,7 2006.189.07:40:09.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.07:40:09.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.07:40:09.35#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:09.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:09.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:09.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:09.41#ibcon#enter wrdev, iclass 30, count 2 2006.189.07:40:09.41#ibcon#first serial, iclass 30, count 2 2006.189.07:40:09.41#ibcon#enter sib2, iclass 30, count 2 2006.189.07:40:09.41#ibcon#flushed, iclass 30, count 2 2006.189.07:40:09.41#ibcon#about to write, iclass 30, count 2 2006.189.07:40:09.41#ibcon#wrote, iclass 30, count 2 2006.189.07:40:09.41#ibcon#about to read 3, iclass 30, count 2 2006.189.07:40:09.43#ibcon#read 3, iclass 30, count 2 2006.189.07:40:09.43#ibcon#about to read 4, iclass 30, count 2 2006.189.07:40:09.43#ibcon#read 4, iclass 30, count 2 2006.189.07:40:09.43#ibcon#about to read 5, iclass 30, count 2 2006.189.07:40:09.43#ibcon#read 5, iclass 30, count 2 2006.189.07:40:09.43#ibcon#about to read 6, iclass 30, count 2 2006.189.07:40:09.43#ibcon#read 6, iclass 30, count 2 2006.189.07:40:09.43#ibcon#end of sib2, iclass 30, count 2 2006.189.07:40:09.43#ibcon#*mode == 0, iclass 30, count 2 2006.189.07:40:09.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.07:40:09.43#ibcon#[25=AT05-07\r\n] 2006.189.07:40:09.43#ibcon#*before write, iclass 30, count 2 2006.189.07:40:09.43#ibcon#enter sib2, iclass 30, count 2 2006.189.07:40:09.43#ibcon#flushed, iclass 30, count 2 2006.189.07:40:09.43#ibcon#about to write, iclass 30, count 2 2006.189.07:40:09.43#ibcon#wrote, iclass 30, count 2 2006.189.07:40:09.43#ibcon#about to read 3, iclass 30, count 2 2006.189.07:40:09.46#ibcon#read 3, iclass 30, count 2 2006.189.07:40:09.46#ibcon#about to read 4, iclass 30, count 2 2006.189.07:40:09.46#ibcon#read 4, iclass 30, count 2 2006.189.07:40:09.46#ibcon#about to read 5, iclass 30, count 2 2006.189.07:40:09.46#ibcon#read 5, iclass 30, count 2 2006.189.07:40:09.46#ibcon#about to read 6, iclass 30, count 2 2006.189.07:40:09.46#ibcon#read 6, iclass 30, count 2 2006.189.07:40:09.46#ibcon#end of sib2, iclass 30, count 2 2006.189.07:40:09.46#ibcon#*after write, iclass 30, count 2 2006.189.07:40:09.46#ibcon#*before return 0, iclass 30, count 2 2006.189.07:40:09.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:09.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:09.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.07:40:09.46#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:09.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:09.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:09.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:09.58#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:40:09.58#ibcon#first serial, iclass 30, count 0 2006.189.07:40:09.58#ibcon#enter sib2, iclass 30, count 0 2006.189.07:40:09.58#ibcon#flushed, iclass 30, count 0 2006.189.07:40:09.58#ibcon#about to write, iclass 30, count 0 2006.189.07:40:09.58#ibcon#wrote, iclass 30, count 0 2006.189.07:40:09.58#ibcon#about to read 3, iclass 30, count 0 2006.189.07:40:09.60#ibcon#read 3, iclass 30, count 0 2006.189.07:40:09.60#ibcon#about to read 4, iclass 30, count 0 2006.189.07:40:09.60#ibcon#read 4, iclass 30, count 0 2006.189.07:40:09.60#ibcon#about to read 5, iclass 30, count 0 2006.189.07:40:09.60#ibcon#read 5, iclass 30, count 0 2006.189.07:40:09.60#ibcon#about to read 6, iclass 30, count 0 2006.189.07:40:09.60#ibcon#read 6, iclass 30, count 0 2006.189.07:40:09.60#ibcon#end of sib2, iclass 30, count 0 2006.189.07:40:09.60#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:40:09.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:40:09.60#ibcon#[25=USB\r\n] 2006.189.07:40:09.60#ibcon#*before write, iclass 30, count 0 2006.189.07:40:09.60#ibcon#enter sib2, iclass 30, count 0 2006.189.07:40:09.60#ibcon#flushed, iclass 30, count 0 2006.189.07:40:09.60#ibcon#about to write, iclass 30, count 0 2006.189.07:40:09.60#ibcon#wrote, iclass 30, count 0 2006.189.07:40:09.60#ibcon#about to read 3, iclass 30, count 0 2006.189.07:40:09.63#ibcon#read 3, iclass 30, count 0 2006.189.07:40:09.63#ibcon#about to read 4, iclass 30, count 0 2006.189.07:40:09.63#ibcon#read 4, iclass 30, count 0 2006.189.07:40:09.63#ibcon#about to read 5, iclass 30, count 0 2006.189.07:40:09.63#ibcon#read 5, iclass 30, count 0 2006.189.07:40:09.63#ibcon#about to read 6, iclass 30, count 0 2006.189.07:40:09.63#ibcon#read 6, iclass 30, count 0 2006.189.07:40:09.63#ibcon#end of sib2, iclass 30, count 0 2006.189.07:40:09.63#ibcon#*after write, iclass 30, count 0 2006.189.07:40:09.63#ibcon#*before return 0, iclass 30, count 0 2006.189.07:40:09.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:09.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:09.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:40:09.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:40:09.63$vc4f8/valo=6,772.99 2006.189.07:40:09.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.07:40:09.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.07:40:09.63#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:09.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:09.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:09.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:09.63#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:40:09.63#ibcon#first serial, iclass 32, count 0 2006.189.07:40:09.63#ibcon#enter sib2, iclass 32, count 0 2006.189.07:40:09.63#ibcon#flushed, iclass 32, count 0 2006.189.07:40:09.63#ibcon#about to write, iclass 32, count 0 2006.189.07:40:09.63#ibcon#wrote, iclass 32, count 0 2006.189.07:40:09.63#ibcon#about to read 3, iclass 32, count 0 2006.189.07:40:09.65#ibcon#read 3, iclass 32, count 0 2006.189.07:40:09.65#ibcon#about to read 4, iclass 32, count 0 2006.189.07:40:09.65#ibcon#read 4, iclass 32, count 0 2006.189.07:40:09.65#ibcon#about to read 5, iclass 32, count 0 2006.189.07:40:09.65#ibcon#read 5, iclass 32, count 0 2006.189.07:40:09.65#ibcon#about to read 6, iclass 32, count 0 2006.189.07:40:09.65#ibcon#read 6, iclass 32, count 0 2006.189.07:40:09.65#ibcon#end of sib2, iclass 32, count 0 2006.189.07:40:09.65#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:40:09.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:40:09.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:40:09.65#ibcon#*before write, iclass 32, count 0 2006.189.07:40:09.65#ibcon#enter sib2, iclass 32, count 0 2006.189.07:40:09.65#ibcon#flushed, iclass 32, count 0 2006.189.07:40:09.65#ibcon#about to write, iclass 32, count 0 2006.189.07:40:09.65#ibcon#wrote, iclass 32, count 0 2006.189.07:40:09.65#ibcon#about to read 3, iclass 32, count 0 2006.189.07:40:09.69#ibcon#read 3, iclass 32, count 0 2006.189.07:40:09.69#ibcon#about to read 4, iclass 32, count 0 2006.189.07:40:09.69#ibcon#read 4, iclass 32, count 0 2006.189.07:40:09.69#ibcon#about to read 5, iclass 32, count 0 2006.189.07:40:09.69#ibcon#read 5, iclass 32, count 0 2006.189.07:40:09.69#ibcon#about to read 6, iclass 32, count 0 2006.189.07:40:09.69#ibcon#read 6, iclass 32, count 0 2006.189.07:40:09.69#ibcon#end of sib2, iclass 32, count 0 2006.189.07:40:09.69#ibcon#*after write, iclass 32, count 0 2006.189.07:40:09.69#ibcon#*before return 0, iclass 32, count 0 2006.189.07:40:09.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:09.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:09.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:40:09.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:40:09.69$vc4f8/va=6,6 2006.189.07:40:09.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.07:40:09.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.07:40:09.69#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:09.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:40:09.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:40:09.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:40:09.75#ibcon#enter wrdev, iclass 34, count 2 2006.189.07:40:09.75#ibcon#first serial, iclass 34, count 2 2006.189.07:40:09.75#ibcon#enter sib2, iclass 34, count 2 2006.189.07:40:09.75#ibcon#flushed, iclass 34, count 2 2006.189.07:40:09.75#ibcon#about to write, iclass 34, count 2 2006.189.07:40:09.75#ibcon#wrote, iclass 34, count 2 2006.189.07:40:09.75#ibcon#about to read 3, iclass 34, count 2 2006.189.07:40:09.77#ibcon#read 3, iclass 34, count 2 2006.189.07:40:09.77#ibcon#about to read 4, iclass 34, count 2 2006.189.07:40:09.77#ibcon#read 4, iclass 34, count 2 2006.189.07:40:09.77#ibcon#about to read 5, iclass 34, count 2 2006.189.07:40:09.77#ibcon#read 5, iclass 34, count 2 2006.189.07:40:09.77#ibcon#about to read 6, iclass 34, count 2 2006.189.07:40:09.77#ibcon#read 6, iclass 34, count 2 2006.189.07:40:09.77#ibcon#end of sib2, iclass 34, count 2 2006.189.07:40:09.77#ibcon#*mode == 0, iclass 34, count 2 2006.189.07:40:09.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.07:40:09.77#ibcon#[25=AT06-06\r\n] 2006.189.07:40:09.77#ibcon#*before write, iclass 34, count 2 2006.189.07:40:09.77#ibcon#enter sib2, iclass 34, count 2 2006.189.07:40:09.77#ibcon#flushed, iclass 34, count 2 2006.189.07:40:09.77#ibcon#about to write, iclass 34, count 2 2006.189.07:40:09.77#ibcon#wrote, iclass 34, count 2 2006.189.07:40:09.77#ibcon#about to read 3, iclass 34, count 2 2006.189.07:40:09.80#ibcon#read 3, iclass 34, count 2 2006.189.07:40:09.80#ibcon#about to read 4, iclass 34, count 2 2006.189.07:40:09.80#ibcon#read 4, iclass 34, count 2 2006.189.07:40:09.80#ibcon#about to read 5, iclass 34, count 2 2006.189.07:40:09.80#ibcon#read 5, iclass 34, count 2 2006.189.07:40:09.80#ibcon#about to read 6, iclass 34, count 2 2006.189.07:40:09.80#ibcon#read 6, iclass 34, count 2 2006.189.07:40:09.80#ibcon#end of sib2, iclass 34, count 2 2006.189.07:40:09.80#ibcon#*after write, iclass 34, count 2 2006.189.07:40:09.80#ibcon#*before return 0, iclass 34, count 2 2006.189.07:40:09.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:40:09.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:40:09.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.07:40:09.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:09.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:40:09.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:40:09.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:40:09.92#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:40:09.92#ibcon#first serial, iclass 34, count 0 2006.189.07:40:09.92#ibcon#enter sib2, iclass 34, count 0 2006.189.07:40:09.92#ibcon#flushed, iclass 34, count 0 2006.189.07:40:09.92#ibcon#about to write, iclass 34, count 0 2006.189.07:40:09.92#ibcon#wrote, iclass 34, count 0 2006.189.07:40:09.92#ibcon#about to read 3, iclass 34, count 0 2006.189.07:40:09.94#ibcon#read 3, iclass 34, count 0 2006.189.07:40:09.94#ibcon#about to read 4, iclass 34, count 0 2006.189.07:40:09.94#ibcon#read 4, iclass 34, count 0 2006.189.07:40:09.94#ibcon#about to read 5, iclass 34, count 0 2006.189.07:40:09.94#ibcon#read 5, iclass 34, count 0 2006.189.07:40:09.94#ibcon#about to read 6, iclass 34, count 0 2006.189.07:40:09.94#ibcon#read 6, iclass 34, count 0 2006.189.07:40:09.94#ibcon#end of sib2, iclass 34, count 0 2006.189.07:40:09.94#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:40:09.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:40:09.94#ibcon#[25=USB\r\n] 2006.189.07:40:09.94#ibcon#*before write, iclass 34, count 0 2006.189.07:40:09.94#ibcon#enter sib2, iclass 34, count 0 2006.189.07:40:09.94#ibcon#flushed, iclass 34, count 0 2006.189.07:40:09.94#ibcon#about to write, iclass 34, count 0 2006.189.07:40:09.94#ibcon#wrote, iclass 34, count 0 2006.189.07:40:09.94#ibcon#about to read 3, iclass 34, count 0 2006.189.07:40:09.97#ibcon#read 3, iclass 34, count 0 2006.189.07:40:09.97#ibcon#about to read 4, iclass 34, count 0 2006.189.07:40:09.97#ibcon#read 4, iclass 34, count 0 2006.189.07:40:09.97#ibcon#about to read 5, iclass 34, count 0 2006.189.07:40:09.97#ibcon#read 5, iclass 34, count 0 2006.189.07:40:09.97#ibcon#about to read 6, iclass 34, count 0 2006.189.07:40:09.97#ibcon#read 6, iclass 34, count 0 2006.189.07:40:09.97#ibcon#end of sib2, iclass 34, count 0 2006.189.07:40:09.97#ibcon#*after write, iclass 34, count 0 2006.189.07:40:09.97#ibcon#*before return 0, iclass 34, count 0 2006.189.07:40:09.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:40:09.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:40:09.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:40:09.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:40:09.97$vc4f8/valo=7,832.99 2006.189.07:40:09.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.07:40:09.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.07:40:09.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:09.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:40:09.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:40:09.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:40:09.97#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:40:09.97#ibcon#first serial, iclass 36, count 0 2006.189.07:40:09.97#ibcon#enter sib2, iclass 36, count 0 2006.189.07:40:09.97#ibcon#flushed, iclass 36, count 0 2006.189.07:40:09.97#ibcon#about to write, iclass 36, count 0 2006.189.07:40:09.97#ibcon#wrote, iclass 36, count 0 2006.189.07:40:09.97#ibcon#about to read 3, iclass 36, count 0 2006.189.07:40:09.99#ibcon#read 3, iclass 36, count 0 2006.189.07:40:09.99#ibcon#about to read 4, iclass 36, count 0 2006.189.07:40:09.99#ibcon#read 4, iclass 36, count 0 2006.189.07:40:09.99#ibcon#about to read 5, iclass 36, count 0 2006.189.07:40:09.99#ibcon#read 5, iclass 36, count 0 2006.189.07:40:09.99#ibcon#about to read 6, iclass 36, count 0 2006.189.07:40:09.99#ibcon#read 6, iclass 36, count 0 2006.189.07:40:09.99#ibcon#end of sib2, iclass 36, count 0 2006.189.07:40:09.99#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:40:09.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:40:09.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:40:09.99#ibcon#*before write, iclass 36, count 0 2006.189.07:40:09.99#ibcon#enter sib2, iclass 36, count 0 2006.189.07:40:09.99#ibcon#flushed, iclass 36, count 0 2006.189.07:40:09.99#ibcon#about to write, iclass 36, count 0 2006.189.07:40:09.99#ibcon#wrote, iclass 36, count 0 2006.189.07:40:09.99#ibcon#about to read 3, iclass 36, count 0 2006.189.07:40:10.03#ibcon#read 3, iclass 36, count 0 2006.189.07:40:10.03#ibcon#about to read 4, iclass 36, count 0 2006.189.07:40:10.03#ibcon#read 4, iclass 36, count 0 2006.189.07:40:10.03#ibcon#about to read 5, iclass 36, count 0 2006.189.07:40:10.03#ibcon#read 5, iclass 36, count 0 2006.189.07:40:10.03#ibcon#about to read 6, iclass 36, count 0 2006.189.07:40:10.03#ibcon#read 6, iclass 36, count 0 2006.189.07:40:10.03#ibcon#end of sib2, iclass 36, count 0 2006.189.07:40:10.03#ibcon#*after write, iclass 36, count 0 2006.189.07:40:10.03#ibcon#*before return 0, iclass 36, count 0 2006.189.07:40:10.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:40:10.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:40:10.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:40:10.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:40:10.03$vc4f8/va=7,6 2006.189.07:40:10.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.07:40:10.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.07:40:10.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:10.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:40:10.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:40:10.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:40:10.09#ibcon#enter wrdev, iclass 38, count 2 2006.189.07:40:10.09#ibcon#first serial, iclass 38, count 2 2006.189.07:40:10.09#ibcon#enter sib2, iclass 38, count 2 2006.189.07:40:10.09#ibcon#flushed, iclass 38, count 2 2006.189.07:40:10.09#ibcon#about to write, iclass 38, count 2 2006.189.07:40:10.09#ibcon#wrote, iclass 38, count 2 2006.189.07:40:10.09#ibcon#about to read 3, iclass 38, count 2 2006.189.07:40:10.11#ibcon#read 3, iclass 38, count 2 2006.189.07:40:10.11#ibcon#about to read 4, iclass 38, count 2 2006.189.07:40:10.11#ibcon#read 4, iclass 38, count 2 2006.189.07:40:10.11#ibcon#about to read 5, iclass 38, count 2 2006.189.07:40:10.11#ibcon#read 5, iclass 38, count 2 2006.189.07:40:10.11#ibcon#about to read 6, iclass 38, count 2 2006.189.07:40:10.11#ibcon#read 6, iclass 38, count 2 2006.189.07:40:10.11#ibcon#end of sib2, iclass 38, count 2 2006.189.07:40:10.11#ibcon#*mode == 0, iclass 38, count 2 2006.189.07:40:10.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.07:40:10.11#ibcon#[25=AT07-06\r\n] 2006.189.07:40:10.11#ibcon#*before write, iclass 38, count 2 2006.189.07:40:10.11#ibcon#enter sib2, iclass 38, count 2 2006.189.07:40:10.11#ibcon#flushed, iclass 38, count 2 2006.189.07:40:10.11#ibcon#about to write, iclass 38, count 2 2006.189.07:40:10.11#ibcon#wrote, iclass 38, count 2 2006.189.07:40:10.11#ibcon#about to read 3, iclass 38, count 2 2006.189.07:40:10.14#ibcon#read 3, iclass 38, count 2 2006.189.07:40:10.14#ibcon#about to read 4, iclass 38, count 2 2006.189.07:40:10.14#ibcon#read 4, iclass 38, count 2 2006.189.07:40:10.14#ibcon#about to read 5, iclass 38, count 2 2006.189.07:40:10.14#ibcon#read 5, iclass 38, count 2 2006.189.07:40:10.14#ibcon#about to read 6, iclass 38, count 2 2006.189.07:40:10.14#ibcon#read 6, iclass 38, count 2 2006.189.07:40:10.14#ibcon#end of sib2, iclass 38, count 2 2006.189.07:40:10.14#ibcon#*after write, iclass 38, count 2 2006.189.07:40:10.14#ibcon#*before return 0, iclass 38, count 2 2006.189.07:40:10.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:40:10.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:40:10.14#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.07:40:10.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:10.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:40:10.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:40:10.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:40:10.26#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:40:10.26#ibcon#first serial, iclass 38, count 0 2006.189.07:40:10.26#ibcon#enter sib2, iclass 38, count 0 2006.189.07:40:10.26#ibcon#flushed, iclass 38, count 0 2006.189.07:40:10.26#ibcon#about to write, iclass 38, count 0 2006.189.07:40:10.26#ibcon#wrote, iclass 38, count 0 2006.189.07:40:10.26#ibcon#about to read 3, iclass 38, count 0 2006.189.07:40:10.28#ibcon#read 3, iclass 38, count 0 2006.189.07:40:10.28#ibcon#about to read 4, iclass 38, count 0 2006.189.07:40:10.28#ibcon#read 4, iclass 38, count 0 2006.189.07:40:10.28#ibcon#about to read 5, iclass 38, count 0 2006.189.07:40:10.28#ibcon#read 5, iclass 38, count 0 2006.189.07:40:10.28#ibcon#about to read 6, iclass 38, count 0 2006.189.07:40:10.28#ibcon#read 6, iclass 38, count 0 2006.189.07:40:10.28#ibcon#end of sib2, iclass 38, count 0 2006.189.07:40:10.28#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:40:10.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:40:10.28#ibcon#[25=USB\r\n] 2006.189.07:40:10.28#ibcon#*before write, iclass 38, count 0 2006.189.07:40:10.28#ibcon#enter sib2, iclass 38, count 0 2006.189.07:40:10.28#ibcon#flushed, iclass 38, count 0 2006.189.07:40:10.28#ibcon#about to write, iclass 38, count 0 2006.189.07:40:10.28#ibcon#wrote, iclass 38, count 0 2006.189.07:40:10.28#ibcon#about to read 3, iclass 38, count 0 2006.189.07:40:10.31#ibcon#read 3, iclass 38, count 0 2006.189.07:40:10.31#ibcon#about to read 4, iclass 38, count 0 2006.189.07:40:10.31#ibcon#read 4, iclass 38, count 0 2006.189.07:40:10.31#ibcon#about to read 5, iclass 38, count 0 2006.189.07:40:10.31#ibcon#read 5, iclass 38, count 0 2006.189.07:40:10.31#ibcon#about to read 6, iclass 38, count 0 2006.189.07:40:10.31#ibcon#read 6, iclass 38, count 0 2006.189.07:40:10.31#ibcon#end of sib2, iclass 38, count 0 2006.189.07:40:10.31#ibcon#*after write, iclass 38, count 0 2006.189.07:40:10.31#ibcon#*before return 0, iclass 38, count 0 2006.189.07:40:10.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:40:10.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:40:10.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:40:10.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:40:10.31$vc4f8/valo=8,852.99 2006.189.07:40:10.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.07:40:10.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.07:40:10.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:10.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:40:10.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:40:10.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:40:10.31#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:40:10.31#ibcon#first serial, iclass 40, count 0 2006.189.07:40:10.31#ibcon#enter sib2, iclass 40, count 0 2006.189.07:40:10.31#ibcon#flushed, iclass 40, count 0 2006.189.07:40:10.31#ibcon#about to write, iclass 40, count 0 2006.189.07:40:10.31#ibcon#wrote, iclass 40, count 0 2006.189.07:40:10.31#ibcon#about to read 3, iclass 40, count 0 2006.189.07:40:10.33#ibcon#read 3, iclass 40, count 0 2006.189.07:40:10.33#ibcon#about to read 4, iclass 40, count 0 2006.189.07:40:10.33#ibcon#read 4, iclass 40, count 0 2006.189.07:40:10.33#ibcon#about to read 5, iclass 40, count 0 2006.189.07:40:10.33#ibcon#read 5, iclass 40, count 0 2006.189.07:40:10.33#ibcon#about to read 6, iclass 40, count 0 2006.189.07:40:10.33#ibcon#read 6, iclass 40, count 0 2006.189.07:40:10.33#ibcon#end of sib2, iclass 40, count 0 2006.189.07:40:10.33#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:40:10.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:40:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:40:10.33#ibcon#*before write, iclass 40, count 0 2006.189.07:40:10.33#ibcon#enter sib2, iclass 40, count 0 2006.189.07:40:10.33#ibcon#flushed, iclass 40, count 0 2006.189.07:40:10.33#ibcon#about to write, iclass 40, count 0 2006.189.07:40:10.33#ibcon#wrote, iclass 40, count 0 2006.189.07:40:10.33#ibcon#about to read 3, iclass 40, count 0 2006.189.07:40:10.37#ibcon#read 3, iclass 40, count 0 2006.189.07:40:10.37#ibcon#about to read 4, iclass 40, count 0 2006.189.07:40:10.37#ibcon#read 4, iclass 40, count 0 2006.189.07:40:10.37#ibcon#about to read 5, iclass 40, count 0 2006.189.07:40:10.37#ibcon#read 5, iclass 40, count 0 2006.189.07:40:10.37#ibcon#about to read 6, iclass 40, count 0 2006.189.07:40:10.37#ibcon#read 6, iclass 40, count 0 2006.189.07:40:10.37#ibcon#end of sib2, iclass 40, count 0 2006.189.07:40:10.37#ibcon#*after write, iclass 40, count 0 2006.189.07:40:10.37#ibcon#*before return 0, iclass 40, count 0 2006.189.07:40:10.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:40:10.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:40:10.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:40:10.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:40:10.37$vc4f8/va=8,6 2006.189.07:40:10.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.07:40:10.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.07:40:10.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:10.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:40:10.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:40:10.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:40:10.43#ibcon#enter wrdev, iclass 4, count 2 2006.189.07:40:10.43#ibcon#first serial, iclass 4, count 2 2006.189.07:40:10.43#ibcon#enter sib2, iclass 4, count 2 2006.189.07:40:10.43#ibcon#flushed, iclass 4, count 2 2006.189.07:40:10.43#ibcon#about to write, iclass 4, count 2 2006.189.07:40:10.43#ibcon#wrote, iclass 4, count 2 2006.189.07:40:10.43#ibcon#about to read 3, iclass 4, count 2 2006.189.07:40:10.45#ibcon#read 3, iclass 4, count 2 2006.189.07:40:10.45#ibcon#about to read 4, iclass 4, count 2 2006.189.07:40:10.45#ibcon#read 4, iclass 4, count 2 2006.189.07:40:10.45#ibcon#about to read 5, iclass 4, count 2 2006.189.07:40:10.45#ibcon#read 5, iclass 4, count 2 2006.189.07:40:10.45#ibcon#about to read 6, iclass 4, count 2 2006.189.07:40:10.45#ibcon#read 6, iclass 4, count 2 2006.189.07:40:10.45#ibcon#end of sib2, iclass 4, count 2 2006.189.07:40:10.45#ibcon#*mode == 0, iclass 4, count 2 2006.189.07:40:10.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.07:40:10.45#ibcon#[25=AT08-06\r\n] 2006.189.07:40:10.45#ibcon#*before write, iclass 4, count 2 2006.189.07:40:10.45#ibcon#enter sib2, iclass 4, count 2 2006.189.07:40:10.45#ibcon#flushed, iclass 4, count 2 2006.189.07:40:10.45#ibcon#about to write, iclass 4, count 2 2006.189.07:40:10.45#ibcon#wrote, iclass 4, count 2 2006.189.07:40:10.45#ibcon#about to read 3, iclass 4, count 2 2006.189.07:40:10.48#ibcon#read 3, iclass 4, count 2 2006.189.07:40:10.48#ibcon#about to read 4, iclass 4, count 2 2006.189.07:40:10.48#ibcon#read 4, iclass 4, count 2 2006.189.07:40:10.48#ibcon#about to read 5, iclass 4, count 2 2006.189.07:40:10.48#ibcon#read 5, iclass 4, count 2 2006.189.07:40:10.48#ibcon#about to read 6, iclass 4, count 2 2006.189.07:40:10.48#ibcon#read 6, iclass 4, count 2 2006.189.07:40:10.48#ibcon#end of sib2, iclass 4, count 2 2006.189.07:40:10.48#ibcon#*after write, iclass 4, count 2 2006.189.07:40:10.48#ibcon#*before return 0, iclass 4, count 2 2006.189.07:40:10.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:40:10.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:40:10.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.07:40:10.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:10.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:40:10.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:40:10.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:40:10.60#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:40:10.60#ibcon#first serial, iclass 4, count 0 2006.189.07:40:10.60#ibcon#enter sib2, iclass 4, count 0 2006.189.07:40:10.60#ibcon#flushed, iclass 4, count 0 2006.189.07:40:10.60#ibcon#about to write, iclass 4, count 0 2006.189.07:40:10.60#ibcon#wrote, iclass 4, count 0 2006.189.07:40:10.60#ibcon#about to read 3, iclass 4, count 0 2006.189.07:40:10.62#ibcon#read 3, iclass 4, count 0 2006.189.07:40:10.62#ibcon#about to read 4, iclass 4, count 0 2006.189.07:40:10.62#ibcon#read 4, iclass 4, count 0 2006.189.07:40:10.62#ibcon#about to read 5, iclass 4, count 0 2006.189.07:40:10.62#ibcon#read 5, iclass 4, count 0 2006.189.07:40:10.62#ibcon#about to read 6, iclass 4, count 0 2006.189.07:40:10.62#ibcon#read 6, iclass 4, count 0 2006.189.07:40:10.62#ibcon#end of sib2, iclass 4, count 0 2006.189.07:40:10.62#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:40:10.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:40:10.62#ibcon#[25=USB\r\n] 2006.189.07:40:10.62#ibcon#*before write, iclass 4, count 0 2006.189.07:40:10.62#ibcon#enter sib2, iclass 4, count 0 2006.189.07:40:10.62#ibcon#flushed, iclass 4, count 0 2006.189.07:40:10.62#ibcon#about to write, iclass 4, count 0 2006.189.07:40:10.62#ibcon#wrote, iclass 4, count 0 2006.189.07:40:10.62#ibcon#about to read 3, iclass 4, count 0 2006.189.07:40:10.65#ibcon#read 3, iclass 4, count 0 2006.189.07:40:10.65#ibcon#about to read 4, iclass 4, count 0 2006.189.07:40:10.65#ibcon#read 4, iclass 4, count 0 2006.189.07:40:10.65#ibcon#about to read 5, iclass 4, count 0 2006.189.07:40:10.65#ibcon#read 5, iclass 4, count 0 2006.189.07:40:10.65#ibcon#about to read 6, iclass 4, count 0 2006.189.07:40:10.65#ibcon#read 6, iclass 4, count 0 2006.189.07:40:10.65#ibcon#end of sib2, iclass 4, count 0 2006.189.07:40:10.65#ibcon#*after write, iclass 4, count 0 2006.189.07:40:10.65#ibcon#*before return 0, iclass 4, count 0 2006.189.07:40:10.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:40:10.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:40:10.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:40:10.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:40:10.65$vc4f8/vblo=1,632.99 2006.189.07:40:10.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:40:10.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:40:10.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:10.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:40:10.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:40:10.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:40:10.65#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:40:10.65#ibcon#first serial, iclass 6, count 0 2006.189.07:40:10.65#ibcon#enter sib2, iclass 6, count 0 2006.189.07:40:10.65#ibcon#flushed, iclass 6, count 0 2006.189.07:40:10.65#ibcon#about to write, iclass 6, count 0 2006.189.07:40:10.65#ibcon#wrote, iclass 6, count 0 2006.189.07:40:10.65#ibcon#about to read 3, iclass 6, count 0 2006.189.07:40:10.67#ibcon#read 3, iclass 6, count 0 2006.189.07:40:10.67#ibcon#about to read 4, iclass 6, count 0 2006.189.07:40:10.67#ibcon#read 4, iclass 6, count 0 2006.189.07:40:10.67#ibcon#about to read 5, iclass 6, count 0 2006.189.07:40:10.67#ibcon#read 5, iclass 6, count 0 2006.189.07:40:10.67#ibcon#about to read 6, iclass 6, count 0 2006.189.07:40:10.67#ibcon#read 6, iclass 6, count 0 2006.189.07:40:10.67#ibcon#end of sib2, iclass 6, count 0 2006.189.07:40:10.67#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:40:10.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:40:10.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:40:10.67#ibcon#*before write, iclass 6, count 0 2006.189.07:40:10.67#ibcon#enter sib2, iclass 6, count 0 2006.189.07:40:10.67#ibcon#flushed, iclass 6, count 0 2006.189.07:40:10.67#ibcon#about to write, iclass 6, count 0 2006.189.07:40:10.67#ibcon#wrote, iclass 6, count 0 2006.189.07:40:10.67#ibcon#about to read 3, iclass 6, count 0 2006.189.07:40:10.71#ibcon#read 3, iclass 6, count 0 2006.189.07:40:10.71#ibcon#about to read 4, iclass 6, count 0 2006.189.07:40:10.71#ibcon#read 4, iclass 6, count 0 2006.189.07:40:10.71#ibcon#about to read 5, iclass 6, count 0 2006.189.07:40:10.71#ibcon#read 5, iclass 6, count 0 2006.189.07:40:10.71#ibcon#about to read 6, iclass 6, count 0 2006.189.07:40:10.71#ibcon#read 6, iclass 6, count 0 2006.189.07:40:10.71#ibcon#end of sib2, iclass 6, count 0 2006.189.07:40:10.71#ibcon#*after write, iclass 6, count 0 2006.189.07:40:10.71#ibcon#*before return 0, iclass 6, count 0 2006.189.07:40:10.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:40:10.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:40:10.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:40:10.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:40:10.71$vc4f8/vb=1,4 2006.189.07:40:10.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.07:40:10.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.07:40:10.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:10.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:40:10.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:40:10.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:40:10.71#ibcon#enter wrdev, iclass 10, count 2 2006.189.07:40:10.71#ibcon#first serial, iclass 10, count 2 2006.189.07:40:10.71#ibcon#enter sib2, iclass 10, count 2 2006.189.07:40:10.71#ibcon#flushed, iclass 10, count 2 2006.189.07:40:10.71#ibcon#about to write, iclass 10, count 2 2006.189.07:40:10.71#ibcon#wrote, iclass 10, count 2 2006.189.07:40:10.71#ibcon#about to read 3, iclass 10, count 2 2006.189.07:40:10.73#ibcon#read 3, iclass 10, count 2 2006.189.07:40:10.73#ibcon#about to read 4, iclass 10, count 2 2006.189.07:40:10.73#ibcon#read 4, iclass 10, count 2 2006.189.07:40:10.73#ibcon#about to read 5, iclass 10, count 2 2006.189.07:40:10.73#ibcon#read 5, iclass 10, count 2 2006.189.07:40:10.73#ibcon#about to read 6, iclass 10, count 2 2006.189.07:40:10.73#ibcon#read 6, iclass 10, count 2 2006.189.07:40:10.73#ibcon#end of sib2, iclass 10, count 2 2006.189.07:40:10.73#ibcon#*mode == 0, iclass 10, count 2 2006.189.07:40:10.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.07:40:10.73#ibcon#[27=AT01-04\r\n] 2006.189.07:40:10.73#ibcon#*before write, iclass 10, count 2 2006.189.07:40:10.73#ibcon#enter sib2, iclass 10, count 2 2006.189.07:40:10.73#ibcon#flushed, iclass 10, count 2 2006.189.07:40:10.73#ibcon#about to write, iclass 10, count 2 2006.189.07:40:10.73#ibcon#wrote, iclass 10, count 2 2006.189.07:40:10.73#ibcon#about to read 3, iclass 10, count 2 2006.189.07:40:10.76#ibcon#read 3, iclass 10, count 2 2006.189.07:40:10.76#ibcon#about to read 4, iclass 10, count 2 2006.189.07:40:10.76#ibcon#read 4, iclass 10, count 2 2006.189.07:40:10.76#ibcon#about to read 5, iclass 10, count 2 2006.189.07:40:10.76#ibcon#read 5, iclass 10, count 2 2006.189.07:40:10.76#ibcon#about to read 6, iclass 10, count 2 2006.189.07:40:10.76#ibcon#read 6, iclass 10, count 2 2006.189.07:40:10.76#ibcon#end of sib2, iclass 10, count 2 2006.189.07:40:10.76#ibcon#*after write, iclass 10, count 2 2006.189.07:40:10.76#ibcon#*before return 0, iclass 10, count 2 2006.189.07:40:10.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:40:10.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:40:10.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.07:40:10.76#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:10.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:40:10.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:40:10.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:40:10.88#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:40:10.88#ibcon#first serial, iclass 10, count 0 2006.189.07:40:10.88#ibcon#enter sib2, iclass 10, count 0 2006.189.07:40:10.88#ibcon#flushed, iclass 10, count 0 2006.189.07:40:10.88#ibcon#about to write, iclass 10, count 0 2006.189.07:40:10.88#ibcon#wrote, iclass 10, count 0 2006.189.07:40:10.88#ibcon#about to read 3, iclass 10, count 0 2006.189.07:40:10.90#ibcon#read 3, iclass 10, count 0 2006.189.07:40:10.90#ibcon#about to read 4, iclass 10, count 0 2006.189.07:40:10.90#ibcon#read 4, iclass 10, count 0 2006.189.07:40:10.90#ibcon#about to read 5, iclass 10, count 0 2006.189.07:40:10.90#ibcon#read 5, iclass 10, count 0 2006.189.07:40:10.90#ibcon#about to read 6, iclass 10, count 0 2006.189.07:40:10.90#ibcon#read 6, iclass 10, count 0 2006.189.07:40:10.90#ibcon#end of sib2, iclass 10, count 0 2006.189.07:40:10.90#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:40:10.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:40:10.90#ibcon#[27=USB\r\n] 2006.189.07:40:10.90#ibcon#*before write, iclass 10, count 0 2006.189.07:40:10.90#ibcon#enter sib2, iclass 10, count 0 2006.189.07:40:10.90#ibcon#flushed, iclass 10, count 0 2006.189.07:40:10.90#ibcon#about to write, iclass 10, count 0 2006.189.07:40:10.90#ibcon#wrote, iclass 10, count 0 2006.189.07:40:10.90#ibcon#about to read 3, iclass 10, count 0 2006.189.07:40:10.93#ibcon#read 3, iclass 10, count 0 2006.189.07:40:10.93#ibcon#about to read 4, iclass 10, count 0 2006.189.07:40:10.93#ibcon#read 4, iclass 10, count 0 2006.189.07:40:10.93#ibcon#about to read 5, iclass 10, count 0 2006.189.07:40:10.93#ibcon#read 5, iclass 10, count 0 2006.189.07:40:10.93#ibcon#about to read 6, iclass 10, count 0 2006.189.07:40:10.93#ibcon#read 6, iclass 10, count 0 2006.189.07:40:10.93#ibcon#end of sib2, iclass 10, count 0 2006.189.07:40:10.93#ibcon#*after write, iclass 10, count 0 2006.189.07:40:10.93#ibcon#*before return 0, iclass 10, count 0 2006.189.07:40:10.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:40:10.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:40:10.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:40:10.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:40:10.93$vc4f8/vblo=2,640.99 2006.189.07:40:10.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.07:40:10.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.07:40:10.93#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:10.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:10.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:10.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:10.93#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:40:10.93#ibcon#first serial, iclass 12, count 0 2006.189.07:40:10.93#ibcon#enter sib2, iclass 12, count 0 2006.189.07:40:10.93#ibcon#flushed, iclass 12, count 0 2006.189.07:40:10.93#ibcon#about to write, iclass 12, count 0 2006.189.07:40:10.93#ibcon#wrote, iclass 12, count 0 2006.189.07:40:10.93#ibcon#about to read 3, iclass 12, count 0 2006.189.07:40:10.95#ibcon#read 3, iclass 12, count 0 2006.189.07:40:10.95#ibcon#about to read 4, iclass 12, count 0 2006.189.07:40:10.95#ibcon#read 4, iclass 12, count 0 2006.189.07:40:10.95#ibcon#about to read 5, iclass 12, count 0 2006.189.07:40:10.95#ibcon#read 5, iclass 12, count 0 2006.189.07:40:10.95#ibcon#about to read 6, iclass 12, count 0 2006.189.07:40:10.95#ibcon#read 6, iclass 12, count 0 2006.189.07:40:10.95#ibcon#end of sib2, iclass 12, count 0 2006.189.07:40:10.95#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:40:10.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:40:10.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:40:10.95#ibcon#*before write, iclass 12, count 0 2006.189.07:40:10.95#ibcon#enter sib2, iclass 12, count 0 2006.189.07:40:10.95#ibcon#flushed, iclass 12, count 0 2006.189.07:40:10.95#ibcon#about to write, iclass 12, count 0 2006.189.07:40:10.95#ibcon#wrote, iclass 12, count 0 2006.189.07:40:10.95#ibcon#about to read 3, iclass 12, count 0 2006.189.07:40:10.99#ibcon#read 3, iclass 12, count 0 2006.189.07:40:10.99#ibcon#about to read 4, iclass 12, count 0 2006.189.07:40:10.99#ibcon#read 4, iclass 12, count 0 2006.189.07:40:10.99#ibcon#about to read 5, iclass 12, count 0 2006.189.07:40:10.99#ibcon#read 5, iclass 12, count 0 2006.189.07:40:10.99#ibcon#about to read 6, iclass 12, count 0 2006.189.07:40:10.99#ibcon#read 6, iclass 12, count 0 2006.189.07:40:10.99#ibcon#end of sib2, iclass 12, count 0 2006.189.07:40:10.99#ibcon#*after write, iclass 12, count 0 2006.189.07:40:10.99#ibcon#*before return 0, iclass 12, count 0 2006.189.07:40:10.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:10.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:40:10.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:40:10.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:40:10.99$vc4f8/vb=2,4 2006.189.07:40:10.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.07:40:10.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.07:40:10.99#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:10.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:11.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:11.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:11.05#ibcon#enter wrdev, iclass 14, count 2 2006.189.07:40:11.05#ibcon#first serial, iclass 14, count 2 2006.189.07:40:11.05#ibcon#enter sib2, iclass 14, count 2 2006.189.07:40:11.05#ibcon#flushed, iclass 14, count 2 2006.189.07:40:11.05#ibcon#about to write, iclass 14, count 2 2006.189.07:40:11.05#ibcon#wrote, iclass 14, count 2 2006.189.07:40:11.05#ibcon#about to read 3, iclass 14, count 2 2006.189.07:40:11.07#ibcon#read 3, iclass 14, count 2 2006.189.07:40:11.07#ibcon#about to read 4, iclass 14, count 2 2006.189.07:40:11.07#ibcon#read 4, iclass 14, count 2 2006.189.07:40:11.07#ibcon#about to read 5, iclass 14, count 2 2006.189.07:40:11.07#ibcon#read 5, iclass 14, count 2 2006.189.07:40:11.07#ibcon#about to read 6, iclass 14, count 2 2006.189.07:40:11.07#ibcon#read 6, iclass 14, count 2 2006.189.07:40:11.07#ibcon#end of sib2, iclass 14, count 2 2006.189.07:40:11.07#ibcon#*mode == 0, iclass 14, count 2 2006.189.07:40:11.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.07:40:11.07#ibcon#[27=AT02-04\r\n] 2006.189.07:40:11.07#ibcon#*before write, iclass 14, count 2 2006.189.07:40:11.07#ibcon#enter sib2, iclass 14, count 2 2006.189.07:40:11.07#ibcon#flushed, iclass 14, count 2 2006.189.07:40:11.07#ibcon#about to write, iclass 14, count 2 2006.189.07:40:11.07#ibcon#wrote, iclass 14, count 2 2006.189.07:40:11.07#ibcon#about to read 3, iclass 14, count 2 2006.189.07:40:11.10#ibcon#read 3, iclass 14, count 2 2006.189.07:40:11.10#ibcon#about to read 4, iclass 14, count 2 2006.189.07:40:11.10#ibcon#read 4, iclass 14, count 2 2006.189.07:40:11.10#ibcon#about to read 5, iclass 14, count 2 2006.189.07:40:11.10#ibcon#read 5, iclass 14, count 2 2006.189.07:40:11.10#ibcon#about to read 6, iclass 14, count 2 2006.189.07:40:11.10#ibcon#read 6, iclass 14, count 2 2006.189.07:40:11.10#ibcon#end of sib2, iclass 14, count 2 2006.189.07:40:11.10#ibcon#*after write, iclass 14, count 2 2006.189.07:40:11.10#ibcon#*before return 0, iclass 14, count 2 2006.189.07:40:11.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:11.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:40:11.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.07:40:11.10#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:11.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:11.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:11.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:11.22#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:40:11.22#ibcon#first serial, iclass 14, count 0 2006.189.07:40:11.22#ibcon#enter sib2, iclass 14, count 0 2006.189.07:40:11.22#ibcon#flushed, iclass 14, count 0 2006.189.07:40:11.22#ibcon#about to write, iclass 14, count 0 2006.189.07:40:11.22#ibcon#wrote, iclass 14, count 0 2006.189.07:40:11.22#ibcon#about to read 3, iclass 14, count 0 2006.189.07:40:11.24#ibcon#read 3, iclass 14, count 0 2006.189.07:40:11.24#ibcon#about to read 4, iclass 14, count 0 2006.189.07:40:11.24#ibcon#read 4, iclass 14, count 0 2006.189.07:40:11.24#ibcon#about to read 5, iclass 14, count 0 2006.189.07:40:11.24#ibcon#read 5, iclass 14, count 0 2006.189.07:40:11.24#ibcon#about to read 6, iclass 14, count 0 2006.189.07:40:11.24#ibcon#read 6, iclass 14, count 0 2006.189.07:40:11.24#ibcon#end of sib2, iclass 14, count 0 2006.189.07:40:11.24#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:40:11.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:40:11.24#ibcon#[27=USB\r\n] 2006.189.07:40:11.24#ibcon#*before write, iclass 14, count 0 2006.189.07:40:11.24#ibcon#enter sib2, iclass 14, count 0 2006.189.07:40:11.24#ibcon#flushed, iclass 14, count 0 2006.189.07:40:11.24#ibcon#about to write, iclass 14, count 0 2006.189.07:40:11.24#ibcon#wrote, iclass 14, count 0 2006.189.07:40:11.24#ibcon#about to read 3, iclass 14, count 0 2006.189.07:40:11.27#ibcon#read 3, iclass 14, count 0 2006.189.07:40:11.27#ibcon#about to read 4, iclass 14, count 0 2006.189.07:40:11.27#ibcon#read 4, iclass 14, count 0 2006.189.07:40:11.27#ibcon#about to read 5, iclass 14, count 0 2006.189.07:40:11.27#ibcon#read 5, iclass 14, count 0 2006.189.07:40:11.27#ibcon#about to read 6, iclass 14, count 0 2006.189.07:40:11.27#ibcon#read 6, iclass 14, count 0 2006.189.07:40:11.27#ibcon#end of sib2, iclass 14, count 0 2006.189.07:40:11.27#ibcon#*after write, iclass 14, count 0 2006.189.07:40:11.27#ibcon#*before return 0, iclass 14, count 0 2006.189.07:40:11.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:11.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:40:11.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:40:11.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:40:11.27$vc4f8/vblo=3,656.99 2006.189.07:40:11.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.07:40:11.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.07:40:11.27#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:11.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:11.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:11.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:11.27#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:40:11.27#ibcon#first serial, iclass 16, count 0 2006.189.07:40:11.27#ibcon#enter sib2, iclass 16, count 0 2006.189.07:40:11.27#ibcon#flushed, iclass 16, count 0 2006.189.07:40:11.27#ibcon#about to write, iclass 16, count 0 2006.189.07:40:11.27#ibcon#wrote, iclass 16, count 0 2006.189.07:40:11.27#ibcon#about to read 3, iclass 16, count 0 2006.189.07:40:11.29#ibcon#read 3, iclass 16, count 0 2006.189.07:40:11.29#ibcon#about to read 4, iclass 16, count 0 2006.189.07:40:11.29#ibcon#read 4, iclass 16, count 0 2006.189.07:40:11.29#ibcon#about to read 5, iclass 16, count 0 2006.189.07:40:11.29#ibcon#read 5, iclass 16, count 0 2006.189.07:40:11.29#ibcon#about to read 6, iclass 16, count 0 2006.189.07:40:11.29#ibcon#read 6, iclass 16, count 0 2006.189.07:40:11.29#ibcon#end of sib2, iclass 16, count 0 2006.189.07:40:11.29#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:40:11.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:40:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:40:11.29#ibcon#*before write, iclass 16, count 0 2006.189.07:40:11.29#ibcon#enter sib2, iclass 16, count 0 2006.189.07:40:11.29#ibcon#flushed, iclass 16, count 0 2006.189.07:40:11.29#ibcon#about to write, iclass 16, count 0 2006.189.07:40:11.29#ibcon#wrote, iclass 16, count 0 2006.189.07:40:11.29#ibcon#about to read 3, iclass 16, count 0 2006.189.07:40:11.33#ibcon#read 3, iclass 16, count 0 2006.189.07:40:11.33#ibcon#about to read 4, iclass 16, count 0 2006.189.07:40:11.33#ibcon#read 4, iclass 16, count 0 2006.189.07:40:11.33#ibcon#about to read 5, iclass 16, count 0 2006.189.07:40:11.33#ibcon#read 5, iclass 16, count 0 2006.189.07:40:11.33#ibcon#about to read 6, iclass 16, count 0 2006.189.07:40:11.33#ibcon#read 6, iclass 16, count 0 2006.189.07:40:11.33#ibcon#end of sib2, iclass 16, count 0 2006.189.07:40:11.33#ibcon#*after write, iclass 16, count 0 2006.189.07:40:11.33#ibcon#*before return 0, iclass 16, count 0 2006.189.07:40:11.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:11.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:40:11.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:40:11.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:40:11.33$vc4f8/vb=3,4 2006.189.07:40:11.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.07:40:11.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.07:40:11.33#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:11.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:11.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:11.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:11.39#ibcon#enter wrdev, iclass 18, count 2 2006.189.07:40:11.39#ibcon#first serial, iclass 18, count 2 2006.189.07:40:11.39#ibcon#enter sib2, iclass 18, count 2 2006.189.07:40:11.39#ibcon#flushed, iclass 18, count 2 2006.189.07:40:11.39#ibcon#about to write, iclass 18, count 2 2006.189.07:40:11.39#ibcon#wrote, iclass 18, count 2 2006.189.07:40:11.39#ibcon#about to read 3, iclass 18, count 2 2006.189.07:40:11.41#ibcon#read 3, iclass 18, count 2 2006.189.07:40:11.41#ibcon#about to read 4, iclass 18, count 2 2006.189.07:40:11.41#ibcon#read 4, iclass 18, count 2 2006.189.07:40:11.41#ibcon#about to read 5, iclass 18, count 2 2006.189.07:40:11.41#ibcon#read 5, iclass 18, count 2 2006.189.07:40:11.41#ibcon#about to read 6, iclass 18, count 2 2006.189.07:40:11.41#ibcon#read 6, iclass 18, count 2 2006.189.07:40:11.41#ibcon#end of sib2, iclass 18, count 2 2006.189.07:40:11.41#ibcon#*mode == 0, iclass 18, count 2 2006.189.07:40:11.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.07:40:11.41#ibcon#[27=AT03-04\r\n] 2006.189.07:40:11.41#ibcon#*before write, iclass 18, count 2 2006.189.07:40:11.41#ibcon#enter sib2, iclass 18, count 2 2006.189.07:40:11.41#ibcon#flushed, iclass 18, count 2 2006.189.07:40:11.41#ibcon#about to write, iclass 18, count 2 2006.189.07:40:11.41#ibcon#wrote, iclass 18, count 2 2006.189.07:40:11.41#ibcon#about to read 3, iclass 18, count 2 2006.189.07:40:11.44#ibcon#read 3, iclass 18, count 2 2006.189.07:40:11.44#ibcon#about to read 4, iclass 18, count 2 2006.189.07:40:11.44#ibcon#read 4, iclass 18, count 2 2006.189.07:40:11.44#ibcon#about to read 5, iclass 18, count 2 2006.189.07:40:11.44#ibcon#read 5, iclass 18, count 2 2006.189.07:40:11.44#ibcon#about to read 6, iclass 18, count 2 2006.189.07:40:11.44#ibcon#read 6, iclass 18, count 2 2006.189.07:40:11.44#ibcon#end of sib2, iclass 18, count 2 2006.189.07:40:11.44#ibcon#*after write, iclass 18, count 2 2006.189.07:40:11.44#ibcon#*before return 0, iclass 18, count 2 2006.189.07:40:11.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:11.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:40:11.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.07:40:11.44#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:11.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:11.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:11.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:11.56#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:40:11.56#ibcon#first serial, iclass 18, count 0 2006.189.07:40:11.56#ibcon#enter sib2, iclass 18, count 0 2006.189.07:40:11.56#ibcon#flushed, iclass 18, count 0 2006.189.07:40:11.56#ibcon#about to write, iclass 18, count 0 2006.189.07:40:11.56#ibcon#wrote, iclass 18, count 0 2006.189.07:40:11.56#ibcon#about to read 3, iclass 18, count 0 2006.189.07:40:11.58#ibcon#read 3, iclass 18, count 0 2006.189.07:40:11.58#ibcon#about to read 4, iclass 18, count 0 2006.189.07:40:11.58#ibcon#read 4, iclass 18, count 0 2006.189.07:40:11.58#ibcon#about to read 5, iclass 18, count 0 2006.189.07:40:11.58#ibcon#read 5, iclass 18, count 0 2006.189.07:40:11.58#ibcon#about to read 6, iclass 18, count 0 2006.189.07:40:11.58#ibcon#read 6, iclass 18, count 0 2006.189.07:40:11.58#ibcon#end of sib2, iclass 18, count 0 2006.189.07:40:11.58#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:40:11.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:40:11.58#ibcon#[27=USB\r\n] 2006.189.07:40:11.58#ibcon#*before write, iclass 18, count 0 2006.189.07:40:11.58#ibcon#enter sib2, iclass 18, count 0 2006.189.07:40:11.58#ibcon#flushed, iclass 18, count 0 2006.189.07:40:11.58#ibcon#about to write, iclass 18, count 0 2006.189.07:40:11.58#ibcon#wrote, iclass 18, count 0 2006.189.07:40:11.58#ibcon#about to read 3, iclass 18, count 0 2006.189.07:40:11.61#ibcon#read 3, iclass 18, count 0 2006.189.07:40:11.61#ibcon#about to read 4, iclass 18, count 0 2006.189.07:40:11.61#ibcon#read 4, iclass 18, count 0 2006.189.07:40:11.61#ibcon#about to read 5, iclass 18, count 0 2006.189.07:40:11.61#ibcon#read 5, iclass 18, count 0 2006.189.07:40:11.61#ibcon#about to read 6, iclass 18, count 0 2006.189.07:40:11.61#ibcon#read 6, iclass 18, count 0 2006.189.07:40:11.61#ibcon#end of sib2, iclass 18, count 0 2006.189.07:40:11.61#ibcon#*after write, iclass 18, count 0 2006.189.07:40:11.61#ibcon#*before return 0, iclass 18, count 0 2006.189.07:40:11.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:11.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:40:11.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:40:11.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:40:11.61$vc4f8/vblo=4,712.99 2006.189.07:40:11.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.07:40:11.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.07:40:11.61#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:11.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:11.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:11.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:11.61#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:40:11.61#ibcon#first serial, iclass 20, count 0 2006.189.07:40:11.61#ibcon#enter sib2, iclass 20, count 0 2006.189.07:40:11.61#ibcon#flushed, iclass 20, count 0 2006.189.07:40:11.61#ibcon#about to write, iclass 20, count 0 2006.189.07:40:11.61#ibcon#wrote, iclass 20, count 0 2006.189.07:40:11.61#ibcon#about to read 3, iclass 20, count 0 2006.189.07:40:11.63#ibcon#read 3, iclass 20, count 0 2006.189.07:40:11.63#ibcon#about to read 4, iclass 20, count 0 2006.189.07:40:11.63#ibcon#read 4, iclass 20, count 0 2006.189.07:40:11.63#ibcon#about to read 5, iclass 20, count 0 2006.189.07:40:11.63#ibcon#read 5, iclass 20, count 0 2006.189.07:40:11.63#ibcon#about to read 6, iclass 20, count 0 2006.189.07:40:11.63#ibcon#read 6, iclass 20, count 0 2006.189.07:40:11.63#ibcon#end of sib2, iclass 20, count 0 2006.189.07:40:11.63#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:40:11.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:40:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:40:11.63#ibcon#*before write, iclass 20, count 0 2006.189.07:40:11.63#ibcon#enter sib2, iclass 20, count 0 2006.189.07:40:11.63#ibcon#flushed, iclass 20, count 0 2006.189.07:40:11.63#ibcon#about to write, iclass 20, count 0 2006.189.07:40:11.63#ibcon#wrote, iclass 20, count 0 2006.189.07:40:11.63#ibcon#about to read 3, iclass 20, count 0 2006.189.07:40:11.67#ibcon#read 3, iclass 20, count 0 2006.189.07:40:11.67#ibcon#about to read 4, iclass 20, count 0 2006.189.07:40:11.67#ibcon#read 4, iclass 20, count 0 2006.189.07:40:11.67#ibcon#about to read 5, iclass 20, count 0 2006.189.07:40:11.67#ibcon#read 5, iclass 20, count 0 2006.189.07:40:11.67#ibcon#about to read 6, iclass 20, count 0 2006.189.07:40:11.67#ibcon#read 6, iclass 20, count 0 2006.189.07:40:11.67#ibcon#end of sib2, iclass 20, count 0 2006.189.07:40:11.67#ibcon#*after write, iclass 20, count 0 2006.189.07:40:11.67#ibcon#*before return 0, iclass 20, count 0 2006.189.07:40:11.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:11.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:40:11.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:40:11.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:40:11.67$vc4f8/vb=4,4 2006.189.07:40:11.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.07:40:11.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.07:40:11.67#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:11.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:11.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:11.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:11.73#ibcon#enter wrdev, iclass 22, count 2 2006.189.07:40:11.73#ibcon#first serial, iclass 22, count 2 2006.189.07:40:11.73#ibcon#enter sib2, iclass 22, count 2 2006.189.07:40:11.73#ibcon#flushed, iclass 22, count 2 2006.189.07:40:11.73#ibcon#about to write, iclass 22, count 2 2006.189.07:40:11.73#ibcon#wrote, iclass 22, count 2 2006.189.07:40:11.73#ibcon#about to read 3, iclass 22, count 2 2006.189.07:40:11.75#ibcon#read 3, iclass 22, count 2 2006.189.07:40:11.75#ibcon#about to read 4, iclass 22, count 2 2006.189.07:40:11.75#ibcon#read 4, iclass 22, count 2 2006.189.07:40:11.75#ibcon#about to read 5, iclass 22, count 2 2006.189.07:40:11.75#ibcon#read 5, iclass 22, count 2 2006.189.07:40:11.75#ibcon#about to read 6, iclass 22, count 2 2006.189.07:40:11.75#ibcon#read 6, iclass 22, count 2 2006.189.07:40:11.75#ibcon#end of sib2, iclass 22, count 2 2006.189.07:40:11.75#ibcon#*mode == 0, iclass 22, count 2 2006.189.07:40:11.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.07:40:11.75#ibcon#[27=AT04-04\r\n] 2006.189.07:40:11.75#ibcon#*before write, iclass 22, count 2 2006.189.07:40:11.75#ibcon#enter sib2, iclass 22, count 2 2006.189.07:40:11.75#ibcon#flushed, iclass 22, count 2 2006.189.07:40:11.75#ibcon#about to write, iclass 22, count 2 2006.189.07:40:11.75#ibcon#wrote, iclass 22, count 2 2006.189.07:40:11.75#ibcon#about to read 3, iclass 22, count 2 2006.189.07:40:11.78#ibcon#read 3, iclass 22, count 2 2006.189.07:40:11.78#ibcon#about to read 4, iclass 22, count 2 2006.189.07:40:11.78#ibcon#read 4, iclass 22, count 2 2006.189.07:40:11.78#ibcon#about to read 5, iclass 22, count 2 2006.189.07:40:11.78#ibcon#read 5, iclass 22, count 2 2006.189.07:40:11.78#ibcon#about to read 6, iclass 22, count 2 2006.189.07:40:11.78#ibcon#read 6, iclass 22, count 2 2006.189.07:40:11.78#ibcon#end of sib2, iclass 22, count 2 2006.189.07:40:11.78#ibcon#*after write, iclass 22, count 2 2006.189.07:40:11.78#ibcon#*before return 0, iclass 22, count 2 2006.189.07:40:11.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:11.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:40:11.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.07:40:11.78#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:11.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:11.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:11.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:11.90#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:40:11.90#ibcon#first serial, iclass 22, count 0 2006.189.07:40:11.90#ibcon#enter sib2, iclass 22, count 0 2006.189.07:40:11.90#ibcon#flushed, iclass 22, count 0 2006.189.07:40:11.90#ibcon#about to write, iclass 22, count 0 2006.189.07:40:11.90#ibcon#wrote, iclass 22, count 0 2006.189.07:40:11.90#ibcon#about to read 3, iclass 22, count 0 2006.189.07:40:11.92#ibcon#read 3, iclass 22, count 0 2006.189.07:40:11.92#ibcon#about to read 4, iclass 22, count 0 2006.189.07:40:11.92#ibcon#read 4, iclass 22, count 0 2006.189.07:40:11.92#ibcon#about to read 5, iclass 22, count 0 2006.189.07:40:11.92#ibcon#read 5, iclass 22, count 0 2006.189.07:40:11.92#ibcon#about to read 6, iclass 22, count 0 2006.189.07:40:11.92#ibcon#read 6, iclass 22, count 0 2006.189.07:40:11.92#ibcon#end of sib2, iclass 22, count 0 2006.189.07:40:11.92#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:40:11.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:40:11.92#ibcon#[27=USB\r\n] 2006.189.07:40:11.92#ibcon#*before write, iclass 22, count 0 2006.189.07:40:11.92#ibcon#enter sib2, iclass 22, count 0 2006.189.07:40:11.92#ibcon#flushed, iclass 22, count 0 2006.189.07:40:11.92#ibcon#about to write, iclass 22, count 0 2006.189.07:40:11.92#ibcon#wrote, iclass 22, count 0 2006.189.07:40:11.92#ibcon#about to read 3, iclass 22, count 0 2006.189.07:40:11.95#ibcon#read 3, iclass 22, count 0 2006.189.07:40:11.95#ibcon#about to read 4, iclass 22, count 0 2006.189.07:40:11.95#ibcon#read 4, iclass 22, count 0 2006.189.07:40:11.95#ibcon#about to read 5, iclass 22, count 0 2006.189.07:40:11.95#ibcon#read 5, iclass 22, count 0 2006.189.07:40:11.95#ibcon#about to read 6, iclass 22, count 0 2006.189.07:40:11.95#ibcon#read 6, iclass 22, count 0 2006.189.07:40:11.95#ibcon#end of sib2, iclass 22, count 0 2006.189.07:40:11.95#ibcon#*after write, iclass 22, count 0 2006.189.07:40:11.95#ibcon#*before return 0, iclass 22, count 0 2006.189.07:40:11.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:11.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:40:11.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:40:11.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:40:11.95$vc4f8/vblo=5,744.99 2006.189.07:40:11.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.07:40:11.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.07:40:11.95#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:11.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:11.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:11.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:11.95#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:40:11.95#ibcon#first serial, iclass 24, count 0 2006.189.07:40:11.95#ibcon#enter sib2, iclass 24, count 0 2006.189.07:40:11.95#ibcon#flushed, iclass 24, count 0 2006.189.07:40:11.95#ibcon#about to write, iclass 24, count 0 2006.189.07:40:11.95#ibcon#wrote, iclass 24, count 0 2006.189.07:40:11.95#ibcon#about to read 3, iclass 24, count 0 2006.189.07:40:11.97#ibcon#read 3, iclass 24, count 0 2006.189.07:40:11.97#ibcon#about to read 4, iclass 24, count 0 2006.189.07:40:11.97#ibcon#read 4, iclass 24, count 0 2006.189.07:40:11.97#ibcon#about to read 5, iclass 24, count 0 2006.189.07:40:11.97#ibcon#read 5, iclass 24, count 0 2006.189.07:40:11.97#ibcon#about to read 6, iclass 24, count 0 2006.189.07:40:11.97#ibcon#read 6, iclass 24, count 0 2006.189.07:40:11.97#ibcon#end of sib2, iclass 24, count 0 2006.189.07:40:11.97#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:40:11.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:40:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:40:11.97#ibcon#*before write, iclass 24, count 0 2006.189.07:40:11.97#ibcon#enter sib2, iclass 24, count 0 2006.189.07:40:11.97#ibcon#flushed, iclass 24, count 0 2006.189.07:40:11.97#ibcon#about to write, iclass 24, count 0 2006.189.07:40:11.97#ibcon#wrote, iclass 24, count 0 2006.189.07:40:11.97#ibcon#about to read 3, iclass 24, count 0 2006.189.07:40:12.01#ibcon#read 3, iclass 24, count 0 2006.189.07:40:12.01#ibcon#about to read 4, iclass 24, count 0 2006.189.07:40:12.01#ibcon#read 4, iclass 24, count 0 2006.189.07:40:12.01#ibcon#about to read 5, iclass 24, count 0 2006.189.07:40:12.01#ibcon#read 5, iclass 24, count 0 2006.189.07:40:12.01#ibcon#about to read 6, iclass 24, count 0 2006.189.07:40:12.01#ibcon#read 6, iclass 24, count 0 2006.189.07:40:12.01#ibcon#end of sib2, iclass 24, count 0 2006.189.07:40:12.01#ibcon#*after write, iclass 24, count 0 2006.189.07:40:12.01#ibcon#*before return 0, iclass 24, count 0 2006.189.07:40:12.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:12.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:40:12.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:40:12.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:40:12.01$vc4f8/vb=5,4 2006.189.07:40:12.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.07:40:12.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.07:40:12.01#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:12.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:12.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:12.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:12.07#ibcon#enter wrdev, iclass 26, count 2 2006.189.07:40:12.07#ibcon#first serial, iclass 26, count 2 2006.189.07:40:12.07#ibcon#enter sib2, iclass 26, count 2 2006.189.07:40:12.07#ibcon#flushed, iclass 26, count 2 2006.189.07:40:12.07#ibcon#about to write, iclass 26, count 2 2006.189.07:40:12.07#ibcon#wrote, iclass 26, count 2 2006.189.07:40:12.07#ibcon#about to read 3, iclass 26, count 2 2006.189.07:40:12.09#ibcon#read 3, iclass 26, count 2 2006.189.07:40:12.09#ibcon#about to read 4, iclass 26, count 2 2006.189.07:40:12.09#ibcon#read 4, iclass 26, count 2 2006.189.07:40:12.09#ibcon#about to read 5, iclass 26, count 2 2006.189.07:40:12.09#ibcon#read 5, iclass 26, count 2 2006.189.07:40:12.09#ibcon#about to read 6, iclass 26, count 2 2006.189.07:40:12.09#ibcon#read 6, iclass 26, count 2 2006.189.07:40:12.09#ibcon#end of sib2, iclass 26, count 2 2006.189.07:40:12.09#ibcon#*mode == 0, iclass 26, count 2 2006.189.07:40:12.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.07:40:12.09#ibcon#[27=AT05-04\r\n] 2006.189.07:40:12.09#ibcon#*before write, iclass 26, count 2 2006.189.07:40:12.09#ibcon#enter sib2, iclass 26, count 2 2006.189.07:40:12.09#ibcon#flushed, iclass 26, count 2 2006.189.07:40:12.09#ibcon#about to write, iclass 26, count 2 2006.189.07:40:12.09#ibcon#wrote, iclass 26, count 2 2006.189.07:40:12.09#ibcon#about to read 3, iclass 26, count 2 2006.189.07:40:12.12#ibcon#read 3, iclass 26, count 2 2006.189.07:40:12.12#ibcon#about to read 4, iclass 26, count 2 2006.189.07:40:12.12#ibcon#read 4, iclass 26, count 2 2006.189.07:40:12.12#ibcon#about to read 5, iclass 26, count 2 2006.189.07:40:12.12#ibcon#read 5, iclass 26, count 2 2006.189.07:40:12.12#ibcon#about to read 6, iclass 26, count 2 2006.189.07:40:12.12#ibcon#read 6, iclass 26, count 2 2006.189.07:40:12.12#ibcon#end of sib2, iclass 26, count 2 2006.189.07:40:12.12#ibcon#*after write, iclass 26, count 2 2006.189.07:40:12.12#ibcon#*before return 0, iclass 26, count 2 2006.189.07:40:12.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:12.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:40:12.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.07:40:12.12#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:12.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:12.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:12.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:12.24#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:40:12.24#ibcon#first serial, iclass 26, count 0 2006.189.07:40:12.24#ibcon#enter sib2, iclass 26, count 0 2006.189.07:40:12.24#ibcon#flushed, iclass 26, count 0 2006.189.07:40:12.24#ibcon#about to write, iclass 26, count 0 2006.189.07:40:12.24#ibcon#wrote, iclass 26, count 0 2006.189.07:40:12.24#ibcon#about to read 3, iclass 26, count 0 2006.189.07:40:12.26#ibcon#read 3, iclass 26, count 0 2006.189.07:40:12.26#ibcon#about to read 4, iclass 26, count 0 2006.189.07:40:12.26#ibcon#read 4, iclass 26, count 0 2006.189.07:40:12.26#ibcon#about to read 5, iclass 26, count 0 2006.189.07:40:12.26#ibcon#read 5, iclass 26, count 0 2006.189.07:40:12.26#ibcon#about to read 6, iclass 26, count 0 2006.189.07:40:12.26#ibcon#read 6, iclass 26, count 0 2006.189.07:40:12.26#ibcon#end of sib2, iclass 26, count 0 2006.189.07:40:12.26#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:40:12.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:40:12.26#ibcon#[27=USB\r\n] 2006.189.07:40:12.26#ibcon#*before write, iclass 26, count 0 2006.189.07:40:12.26#ibcon#enter sib2, iclass 26, count 0 2006.189.07:40:12.26#ibcon#flushed, iclass 26, count 0 2006.189.07:40:12.26#ibcon#about to write, iclass 26, count 0 2006.189.07:40:12.26#ibcon#wrote, iclass 26, count 0 2006.189.07:40:12.26#ibcon#about to read 3, iclass 26, count 0 2006.189.07:40:12.29#ibcon#read 3, iclass 26, count 0 2006.189.07:40:12.29#ibcon#about to read 4, iclass 26, count 0 2006.189.07:40:12.29#ibcon#read 4, iclass 26, count 0 2006.189.07:40:12.29#ibcon#about to read 5, iclass 26, count 0 2006.189.07:40:12.29#ibcon#read 5, iclass 26, count 0 2006.189.07:40:12.29#ibcon#about to read 6, iclass 26, count 0 2006.189.07:40:12.29#ibcon#read 6, iclass 26, count 0 2006.189.07:40:12.29#ibcon#end of sib2, iclass 26, count 0 2006.189.07:40:12.29#ibcon#*after write, iclass 26, count 0 2006.189.07:40:12.29#ibcon#*before return 0, iclass 26, count 0 2006.189.07:40:12.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:12.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:40:12.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:40:12.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:40:12.29$vc4f8/vblo=6,752.99 2006.189.07:40:12.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.07:40:12.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.07:40:12.29#ibcon#ireg 17 cls_cnt 0 2006.189.07:40:12.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:12.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:12.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:12.29#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:40:12.29#ibcon#first serial, iclass 28, count 0 2006.189.07:40:12.29#ibcon#enter sib2, iclass 28, count 0 2006.189.07:40:12.29#ibcon#flushed, iclass 28, count 0 2006.189.07:40:12.29#ibcon#about to write, iclass 28, count 0 2006.189.07:40:12.29#ibcon#wrote, iclass 28, count 0 2006.189.07:40:12.29#ibcon#about to read 3, iclass 28, count 0 2006.189.07:40:12.31#ibcon#read 3, iclass 28, count 0 2006.189.07:40:12.31#ibcon#about to read 4, iclass 28, count 0 2006.189.07:40:12.31#ibcon#read 4, iclass 28, count 0 2006.189.07:40:12.31#ibcon#about to read 5, iclass 28, count 0 2006.189.07:40:12.31#ibcon#read 5, iclass 28, count 0 2006.189.07:40:12.31#ibcon#about to read 6, iclass 28, count 0 2006.189.07:40:12.31#ibcon#read 6, iclass 28, count 0 2006.189.07:40:12.31#ibcon#end of sib2, iclass 28, count 0 2006.189.07:40:12.31#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:40:12.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:40:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:40:12.31#ibcon#*before write, iclass 28, count 0 2006.189.07:40:12.31#ibcon#enter sib2, iclass 28, count 0 2006.189.07:40:12.31#ibcon#flushed, iclass 28, count 0 2006.189.07:40:12.31#ibcon#about to write, iclass 28, count 0 2006.189.07:40:12.31#ibcon#wrote, iclass 28, count 0 2006.189.07:40:12.31#ibcon#about to read 3, iclass 28, count 0 2006.189.07:40:12.35#ibcon#read 3, iclass 28, count 0 2006.189.07:40:12.35#ibcon#about to read 4, iclass 28, count 0 2006.189.07:40:12.35#ibcon#read 4, iclass 28, count 0 2006.189.07:40:12.35#ibcon#about to read 5, iclass 28, count 0 2006.189.07:40:12.35#ibcon#read 5, iclass 28, count 0 2006.189.07:40:12.35#ibcon#about to read 6, iclass 28, count 0 2006.189.07:40:12.35#ibcon#read 6, iclass 28, count 0 2006.189.07:40:12.35#ibcon#end of sib2, iclass 28, count 0 2006.189.07:40:12.35#ibcon#*after write, iclass 28, count 0 2006.189.07:40:12.35#ibcon#*before return 0, iclass 28, count 0 2006.189.07:40:12.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:12.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:40:12.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:40:12.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:40:12.35$vc4f8/vb=6,4 2006.189.07:40:12.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.07:40:12.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.07:40:12.35#ibcon#ireg 11 cls_cnt 2 2006.189.07:40:12.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:12.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:12.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:12.41#ibcon#enter wrdev, iclass 30, count 2 2006.189.07:40:12.41#ibcon#first serial, iclass 30, count 2 2006.189.07:40:12.41#ibcon#enter sib2, iclass 30, count 2 2006.189.07:40:12.41#ibcon#flushed, iclass 30, count 2 2006.189.07:40:12.41#ibcon#about to write, iclass 30, count 2 2006.189.07:40:12.41#ibcon#wrote, iclass 30, count 2 2006.189.07:40:12.41#ibcon#about to read 3, iclass 30, count 2 2006.189.07:40:12.43#ibcon#read 3, iclass 30, count 2 2006.189.07:40:12.43#ibcon#about to read 4, iclass 30, count 2 2006.189.07:40:12.43#ibcon#read 4, iclass 30, count 2 2006.189.07:40:12.43#ibcon#about to read 5, iclass 30, count 2 2006.189.07:40:12.43#ibcon#read 5, iclass 30, count 2 2006.189.07:40:12.43#ibcon#about to read 6, iclass 30, count 2 2006.189.07:40:12.43#ibcon#read 6, iclass 30, count 2 2006.189.07:40:12.43#ibcon#end of sib2, iclass 30, count 2 2006.189.07:40:12.43#ibcon#*mode == 0, iclass 30, count 2 2006.189.07:40:12.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.07:40:12.43#ibcon#[27=AT06-04\r\n] 2006.189.07:40:12.43#ibcon#*before write, iclass 30, count 2 2006.189.07:40:12.43#ibcon#enter sib2, iclass 30, count 2 2006.189.07:40:12.43#ibcon#flushed, iclass 30, count 2 2006.189.07:40:12.43#ibcon#about to write, iclass 30, count 2 2006.189.07:40:12.43#ibcon#wrote, iclass 30, count 2 2006.189.07:40:12.43#ibcon#about to read 3, iclass 30, count 2 2006.189.07:40:12.46#ibcon#read 3, iclass 30, count 2 2006.189.07:40:12.46#ibcon#about to read 4, iclass 30, count 2 2006.189.07:40:12.46#ibcon#read 4, iclass 30, count 2 2006.189.07:40:12.46#ibcon#about to read 5, iclass 30, count 2 2006.189.07:40:12.46#ibcon#read 5, iclass 30, count 2 2006.189.07:40:12.46#ibcon#about to read 6, iclass 30, count 2 2006.189.07:40:12.46#ibcon#read 6, iclass 30, count 2 2006.189.07:40:12.46#ibcon#end of sib2, iclass 30, count 2 2006.189.07:40:12.46#ibcon#*after write, iclass 30, count 2 2006.189.07:40:12.46#ibcon#*before return 0, iclass 30, count 2 2006.189.07:40:12.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:12.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:40:12.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.07:40:12.46#ibcon#ireg 7 cls_cnt 0 2006.189.07:40:12.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:12.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:12.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:12.58#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:40:12.58#ibcon#first serial, iclass 30, count 0 2006.189.07:40:12.58#ibcon#enter sib2, iclass 30, count 0 2006.189.07:40:12.58#ibcon#flushed, iclass 30, count 0 2006.189.07:40:12.58#ibcon#about to write, iclass 30, count 0 2006.189.07:40:12.58#ibcon#wrote, iclass 30, count 0 2006.189.07:40:12.58#ibcon#about to read 3, iclass 30, count 0 2006.189.07:40:12.60#ibcon#read 3, iclass 30, count 0 2006.189.07:40:12.60#ibcon#about to read 4, iclass 30, count 0 2006.189.07:40:12.60#ibcon#read 4, iclass 30, count 0 2006.189.07:40:12.60#ibcon#about to read 5, iclass 30, count 0 2006.189.07:40:12.60#ibcon#read 5, iclass 30, count 0 2006.189.07:40:12.60#ibcon#about to read 6, iclass 30, count 0 2006.189.07:40:12.60#ibcon#read 6, iclass 30, count 0 2006.189.07:40:12.60#ibcon#end of sib2, iclass 30, count 0 2006.189.07:40:12.60#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:40:12.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:40:12.60#ibcon#[27=USB\r\n] 2006.189.07:40:12.60#ibcon#*before write, iclass 30, count 0 2006.189.07:40:12.60#ibcon#enter sib2, iclass 30, count 0 2006.189.07:40:12.60#ibcon#flushed, iclass 30, count 0 2006.189.07:40:12.60#ibcon#about to write, iclass 30, count 0 2006.189.07:40:12.60#ibcon#wrote, iclass 30, count 0 2006.189.07:40:12.60#ibcon#about to read 3, iclass 30, count 0 2006.189.07:40:12.63#ibcon#read 3, iclass 30, count 0 2006.189.07:40:12.63#ibcon#about to read 4, iclass 30, count 0 2006.189.07:40:12.63#ibcon#read 4, iclass 30, count 0 2006.189.07:40:12.63#ibcon#about to read 5, iclass 30, count 0 2006.189.07:40:12.63#ibcon#read 5, iclass 30, count 0 2006.189.07:40:12.63#ibcon#about to read 6, iclass 30, count 0 2006.189.07:40:12.63#ibcon#read 6, iclass 30, count 0 2006.189.07:40:12.63#ibcon#end of sib2, iclass 30, count 0 2006.189.07:40:12.63#ibcon#*after write, iclass 30, count 0 2006.189.07:40:12.63#ibcon#*before return 0, iclass 30, count 0 2006.189.07:40:12.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:12.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:40:12.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:40:12.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:40:12.63$vc4f8/vabw=wide 2006.189.07:40:12.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.07:40:12.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.07:40:12.63#ibcon#ireg 8 cls_cnt 0 2006.189.07:40:12.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:12.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:12.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:12.63#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:40:12.63#ibcon#first serial, iclass 32, count 0 2006.189.07:40:12.63#ibcon#enter sib2, iclass 32, count 0 2006.189.07:40:12.63#ibcon#flushed, iclass 32, count 0 2006.189.07:40:12.63#ibcon#about to write, iclass 32, count 0 2006.189.07:40:12.63#ibcon#wrote, iclass 32, count 0 2006.189.07:40:12.63#ibcon#about to read 3, iclass 32, count 0 2006.189.07:40:12.65#ibcon#read 3, iclass 32, count 0 2006.189.07:40:12.65#ibcon#about to read 4, iclass 32, count 0 2006.189.07:40:12.65#ibcon#read 4, iclass 32, count 0 2006.189.07:40:12.65#ibcon#about to read 5, iclass 32, count 0 2006.189.07:40:12.65#ibcon#read 5, iclass 32, count 0 2006.189.07:40:12.65#ibcon#about to read 6, iclass 32, count 0 2006.189.07:40:12.65#ibcon#read 6, iclass 32, count 0 2006.189.07:40:12.65#ibcon#end of sib2, iclass 32, count 0 2006.189.07:40:12.65#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:40:12.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:40:12.65#ibcon#[25=BW32\r\n] 2006.189.07:40:12.65#ibcon#*before write, iclass 32, count 0 2006.189.07:40:12.65#ibcon#enter sib2, iclass 32, count 0 2006.189.07:40:12.65#ibcon#flushed, iclass 32, count 0 2006.189.07:40:12.65#ibcon#about to write, iclass 32, count 0 2006.189.07:40:12.65#ibcon#wrote, iclass 32, count 0 2006.189.07:40:12.65#ibcon#about to read 3, iclass 32, count 0 2006.189.07:40:12.68#ibcon#read 3, iclass 32, count 0 2006.189.07:40:12.68#ibcon#about to read 4, iclass 32, count 0 2006.189.07:40:12.68#ibcon#read 4, iclass 32, count 0 2006.189.07:40:12.68#ibcon#about to read 5, iclass 32, count 0 2006.189.07:40:12.68#ibcon#read 5, iclass 32, count 0 2006.189.07:40:12.68#ibcon#about to read 6, iclass 32, count 0 2006.189.07:40:12.68#ibcon#read 6, iclass 32, count 0 2006.189.07:40:12.68#ibcon#end of sib2, iclass 32, count 0 2006.189.07:40:12.68#ibcon#*after write, iclass 32, count 0 2006.189.07:40:12.68#ibcon#*before return 0, iclass 32, count 0 2006.189.07:40:12.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:12.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:40:12.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:40:12.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:40:12.68$vc4f8/vbbw=wide 2006.189.07:40:12.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.07:40:12.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.07:40:12.68#ibcon#ireg 8 cls_cnt 0 2006.189.07:40:12.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:40:12.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:40:12.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:40:12.75#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:40:12.75#ibcon#first serial, iclass 34, count 0 2006.189.07:40:12.75#ibcon#enter sib2, iclass 34, count 0 2006.189.07:40:12.75#ibcon#flushed, iclass 34, count 0 2006.189.07:40:12.75#ibcon#about to write, iclass 34, count 0 2006.189.07:40:12.75#ibcon#wrote, iclass 34, count 0 2006.189.07:40:12.75#ibcon#about to read 3, iclass 34, count 0 2006.189.07:40:12.77#ibcon#read 3, iclass 34, count 0 2006.189.07:40:12.77#ibcon#about to read 4, iclass 34, count 0 2006.189.07:40:12.77#ibcon#read 4, iclass 34, count 0 2006.189.07:40:12.77#ibcon#about to read 5, iclass 34, count 0 2006.189.07:40:12.77#ibcon#read 5, iclass 34, count 0 2006.189.07:40:12.77#ibcon#about to read 6, iclass 34, count 0 2006.189.07:40:12.77#ibcon#read 6, iclass 34, count 0 2006.189.07:40:12.77#ibcon#end of sib2, iclass 34, count 0 2006.189.07:40:12.77#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:40:12.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:40:12.77#ibcon#[27=BW32\r\n] 2006.189.07:40:12.77#ibcon#*before write, iclass 34, count 0 2006.189.07:40:12.77#ibcon#enter sib2, iclass 34, count 0 2006.189.07:40:12.77#ibcon#flushed, iclass 34, count 0 2006.189.07:40:12.77#ibcon#about to write, iclass 34, count 0 2006.189.07:40:12.77#ibcon#wrote, iclass 34, count 0 2006.189.07:40:12.77#ibcon#about to read 3, iclass 34, count 0 2006.189.07:40:12.80#ibcon#read 3, iclass 34, count 0 2006.189.07:40:12.80#ibcon#about to read 4, iclass 34, count 0 2006.189.07:40:12.80#ibcon#read 4, iclass 34, count 0 2006.189.07:40:12.80#ibcon#about to read 5, iclass 34, count 0 2006.189.07:40:12.80#ibcon#read 5, iclass 34, count 0 2006.189.07:40:12.80#ibcon#about to read 6, iclass 34, count 0 2006.189.07:40:12.80#ibcon#read 6, iclass 34, count 0 2006.189.07:40:12.80#ibcon#end of sib2, iclass 34, count 0 2006.189.07:40:12.80#ibcon#*after write, iclass 34, count 0 2006.189.07:40:12.80#ibcon#*before return 0, iclass 34, count 0 2006.189.07:40:12.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:40:12.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:40:12.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:40:12.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:40:12.80$4f8m12a/ifd4f 2006.189.07:40:12.80$ifd4f/lo= 2006.189.07:40:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:40:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:40:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:40:12.80$ifd4f/patch= 2006.189.07:40:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:40:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:40:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:40:12.80$4f8m12a/"form=m,16.000,1:2 2006.189.07:40:12.80$4f8m12a/"tpicd 2006.189.07:40:12.80$4f8m12a/echo=off 2006.189.07:40:12.80$4f8m12a/xlog=off 2006.189.07:40:12.81:!2006.189.07:40:40 2006.189.07:40:22.14#trakl#Source acquired 2006.189.07:40:22.14#flagr#flagr/antenna,acquired 2006.189.07:40:40.01:preob 2006.189.07:40:41.14/onsource/TRACKING 2006.189.07:40:41.14:!2006.189.07:40:50 2006.189.07:40:50.00:data_valid=on 2006.189.07:40:50.00:midob 2006.189.07:40:50.14/onsource/TRACKING 2006.189.07:40:50.14/wx/26.29,1008.9,87 2006.189.07:40:50.32/cable/+6.4517E-03 2006.189.07:40:51.41/va/01,08,usb,yes,30,32 2006.189.07:40:51.41/va/02,07,usb,yes,31,32 2006.189.07:40:51.41/va/03,06,usb,yes,32,32 2006.189.07:40:51.41/va/04,07,usb,yes,32,34 2006.189.07:40:51.41/va/05,07,usb,yes,33,35 2006.189.07:40:51.41/va/06,06,usb,yes,32,32 2006.189.07:40:51.41/va/07,06,usb,yes,33,33 2006.189.07:40:51.41/va/08,06,usb,yes,35,35 2006.189.07:40:51.64/valo/01,532.99,yes,locked 2006.189.07:40:51.64/valo/02,572.99,yes,locked 2006.189.07:40:51.64/valo/03,672.99,yes,locked 2006.189.07:40:51.64/valo/04,832.99,yes,locked 2006.189.07:40:51.64/valo/05,652.99,yes,locked 2006.189.07:40:51.64/valo/06,772.99,yes,locked 2006.189.07:40:51.64/valo/07,832.99,yes,locked 2006.189.07:40:51.64/valo/08,852.99,yes,locked 2006.189.07:40:52.73/vb/01,04,usb,yes,30,28 2006.189.07:40:52.73/vb/02,04,usb,yes,32,33 2006.189.07:40:52.73/vb/03,04,usb,yes,28,32 2006.189.07:40:52.73/vb/04,04,usb,yes,29,29 2006.189.07:40:52.73/vb/05,04,usb,yes,28,31 2006.189.07:40:52.73/vb/06,04,usb,yes,28,31 2006.189.07:40:52.73/vb/07,04,usb,yes,31,30 2006.189.07:40:52.73/vb/08,04,usb,yes,28,31 2006.189.07:40:52.96/vblo/01,632.99,yes,locked 2006.189.07:40:52.96/vblo/02,640.99,yes,locked 2006.189.07:40:52.96/vblo/03,656.99,yes,locked 2006.189.07:40:52.96/vblo/04,712.99,yes,locked 2006.189.07:40:52.96/vblo/05,744.99,yes,locked 2006.189.07:40:52.96/vblo/06,752.99,yes,locked 2006.189.07:40:52.96/vblo/07,734.99,yes,locked 2006.189.07:40:52.96/vblo/08,744.99,yes,locked 2006.189.07:40:53.11/vabw/8 2006.189.07:40:53.26/vbbw/8 2006.189.07:40:53.35/xfe/off,on,15.5 2006.189.07:40:53.72/ifatt/23,28,28,28 2006.189.07:40:54.08/fmout-gps/S +2.98E-07 2006.189.07:40:54.15:!2006.189.07:41:50 2006.189.07:41:50.01:data_valid=off 2006.189.07:41:50.02:postob 2006.189.07:41:50.16/cable/+6.4524E-03 2006.189.07:41:50.17/wx/26.25,1008.9,88 2006.189.07:41:51.07/fmout-gps/S +2.99E-07 2006.189.07:41:51.08:scan_name=189-0742,k06189,60 2006.189.07:41:51.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.189.07:41:51.14#flagr#flagr/antenna,new-source 2006.189.07:41:52.14:checkk5 2006.189.07:41:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:41:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:41:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:41:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:41:54.05/chk_obsdata//k5ts1/T1890740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:41:54.43/chk_obsdata//k5ts2/T1890740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:41:54.80/chk_obsdata//k5ts3/T1890740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:41:55.18/chk_obsdata//k5ts4/T1890740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:41:55.87/k5log//k5ts1_log_newline 2006.189.07:41:56.57/k5log//k5ts2_log_newline 2006.189.07:41:57.27/k5log//k5ts3_log_newline 2006.189.07:41:57.96/k5log//k5ts4_log_newline 2006.189.07:41:57.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:41:57.99:4f8m12a=1 2006.189.07:41:57.99$4f8m12a/echo=on 2006.189.07:41:57.99$4f8m12a/pcalon 2006.189.07:41:57.99$pcalon/"no phase cal control is implemented here 2006.189.07:41:57.99$4f8m12a/"tpicd=stop 2006.189.07:41:57.99$4f8m12a/vc4f8 2006.189.07:41:57.99$vc4f8/valo=1,532.99 2006.189.07:41:58.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:41:58.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:41:58.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:41:58.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:41:58.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:41:58.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:41:58.00#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:41:58.00#ibcon#first serial, iclass 6, count 0 2006.189.07:41:58.00#ibcon#enter sib2, iclass 6, count 0 2006.189.07:41:58.00#ibcon#flushed, iclass 6, count 0 2006.189.07:41:58.00#ibcon#about to write, iclass 6, count 0 2006.189.07:41:58.00#ibcon#wrote, iclass 6, count 0 2006.189.07:41:58.00#ibcon#about to read 3, iclass 6, count 0 2006.189.07:41:58.04#ibcon#read 3, iclass 6, count 0 2006.189.07:41:58.04#ibcon#about to read 4, iclass 6, count 0 2006.189.07:41:58.04#ibcon#read 4, iclass 6, count 0 2006.189.07:41:58.04#ibcon#about to read 5, iclass 6, count 0 2006.189.07:41:58.04#ibcon#read 5, iclass 6, count 0 2006.189.07:41:58.04#ibcon#about to read 6, iclass 6, count 0 2006.189.07:41:58.04#ibcon#read 6, iclass 6, count 0 2006.189.07:41:58.04#ibcon#end of sib2, iclass 6, count 0 2006.189.07:41:58.04#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:41:58.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:41:58.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:41:58.04#ibcon#*before write, iclass 6, count 0 2006.189.07:41:58.04#ibcon#enter sib2, iclass 6, count 0 2006.189.07:41:58.04#ibcon#flushed, iclass 6, count 0 2006.189.07:41:58.04#ibcon#about to write, iclass 6, count 0 2006.189.07:41:58.04#ibcon#wrote, iclass 6, count 0 2006.189.07:41:58.04#ibcon#about to read 3, iclass 6, count 0 2006.189.07:41:58.06#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:41:58.09#ibcon#read 3, iclass 6, count 0 2006.189.07:41:58.09#ibcon#about to read 4, iclass 6, count 0 2006.189.07:41:58.09#ibcon#read 4, iclass 6, count 0 2006.189.07:41:58.09#ibcon#about to read 5, iclass 6, count 0 2006.189.07:41:58.09#ibcon#read 5, iclass 6, count 0 2006.189.07:41:58.09#ibcon#about to read 6, iclass 6, count 0 2006.189.07:41:58.09#ibcon#read 6, iclass 6, count 0 2006.189.07:41:58.09#ibcon#end of sib2, iclass 6, count 0 2006.189.07:41:58.09#ibcon#*after write, iclass 6, count 0 2006.189.07:41:58.09#ibcon#*before return 0, iclass 6, count 0 2006.189.07:41:58.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:41:58.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:41:58.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:41:58.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:41:58.09$vc4f8/va=1,8 2006.189.07:41:58.09#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:41:58.09#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:41:58.09#ibcon#ireg 11 cls_cnt 2 2006.189.07:41:58.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:41:58.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:41:58.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:41:58.09#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:41:58.09#ibcon#first serial, iclass 11, count 2 2006.189.07:41:58.09#ibcon#enter sib2, iclass 11, count 2 2006.189.07:41:58.09#ibcon#flushed, iclass 11, count 2 2006.189.07:41:58.09#ibcon#about to write, iclass 11, count 2 2006.189.07:41:58.09#ibcon#wrote, iclass 11, count 2 2006.189.07:41:58.09#ibcon#about to read 3, iclass 11, count 2 2006.189.07:41:58.11#ibcon#read 3, iclass 11, count 2 2006.189.07:41:58.11#ibcon#about to read 4, iclass 11, count 2 2006.189.07:41:58.11#ibcon#read 4, iclass 11, count 2 2006.189.07:41:58.11#ibcon#about to read 5, iclass 11, count 2 2006.189.07:41:58.11#ibcon#read 5, iclass 11, count 2 2006.189.07:41:58.11#ibcon#about to read 6, iclass 11, count 2 2006.189.07:41:58.11#ibcon#read 6, iclass 11, count 2 2006.189.07:41:58.11#ibcon#end of sib2, iclass 11, count 2 2006.189.07:41:58.11#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:41:58.11#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:41:58.11#ibcon#[25=AT01-08\r\n] 2006.189.07:41:58.11#ibcon#*before write, iclass 11, count 2 2006.189.07:41:58.11#ibcon#enter sib2, iclass 11, count 2 2006.189.07:41:58.11#ibcon#flushed, iclass 11, count 2 2006.189.07:41:58.11#ibcon#about to write, iclass 11, count 2 2006.189.07:41:58.11#ibcon#wrote, iclass 11, count 2 2006.189.07:41:58.11#ibcon#about to read 3, iclass 11, count 2 2006.189.07:41:58.14#ibcon#read 3, iclass 11, count 2 2006.189.07:41:58.14#ibcon#about to read 4, iclass 11, count 2 2006.189.07:41:58.14#ibcon#read 4, iclass 11, count 2 2006.189.07:41:58.14#ibcon#about to read 5, iclass 11, count 2 2006.189.07:41:58.14#ibcon#read 5, iclass 11, count 2 2006.189.07:41:58.14#ibcon#about to read 6, iclass 11, count 2 2006.189.07:41:58.14#ibcon#read 6, iclass 11, count 2 2006.189.07:41:58.14#ibcon#end of sib2, iclass 11, count 2 2006.189.07:41:58.14#ibcon#*after write, iclass 11, count 2 2006.189.07:41:58.14#ibcon#*before return 0, iclass 11, count 2 2006.189.07:41:58.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:41:58.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:41:58.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:41:58.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:41:58.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:41:58.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:41:58.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:41:58.26#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:41:58.26#ibcon#first serial, iclass 11, count 0 2006.189.07:41:58.26#ibcon#enter sib2, iclass 11, count 0 2006.189.07:41:58.26#ibcon#flushed, iclass 11, count 0 2006.189.07:41:58.26#ibcon#about to write, iclass 11, count 0 2006.189.07:41:58.26#ibcon#wrote, iclass 11, count 0 2006.189.07:41:58.26#ibcon#about to read 3, iclass 11, count 0 2006.189.07:41:58.28#ibcon#read 3, iclass 11, count 0 2006.189.07:41:58.28#ibcon#about to read 4, iclass 11, count 0 2006.189.07:41:58.28#ibcon#read 4, iclass 11, count 0 2006.189.07:41:58.28#ibcon#about to read 5, iclass 11, count 0 2006.189.07:41:58.28#ibcon#read 5, iclass 11, count 0 2006.189.07:41:58.28#ibcon#about to read 6, iclass 11, count 0 2006.189.07:41:58.28#ibcon#read 6, iclass 11, count 0 2006.189.07:41:58.28#ibcon#end of sib2, iclass 11, count 0 2006.189.07:41:58.28#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:41:58.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:41:58.28#ibcon#[25=USB\r\n] 2006.189.07:41:58.28#ibcon#*before write, iclass 11, count 0 2006.189.07:41:58.28#ibcon#enter sib2, iclass 11, count 0 2006.189.07:41:58.28#ibcon#flushed, iclass 11, count 0 2006.189.07:41:58.28#ibcon#about to write, iclass 11, count 0 2006.189.07:41:58.28#ibcon#wrote, iclass 11, count 0 2006.189.07:41:58.28#ibcon#about to read 3, iclass 11, count 0 2006.189.07:41:58.31#ibcon#read 3, iclass 11, count 0 2006.189.07:41:58.31#ibcon#about to read 4, iclass 11, count 0 2006.189.07:41:58.31#ibcon#read 4, iclass 11, count 0 2006.189.07:41:58.31#ibcon#about to read 5, iclass 11, count 0 2006.189.07:41:58.31#ibcon#read 5, iclass 11, count 0 2006.189.07:41:58.31#ibcon#about to read 6, iclass 11, count 0 2006.189.07:41:58.31#ibcon#read 6, iclass 11, count 0 2006.189.07:41:58.31#ibcon#end of sib2, iclass 11, count 0 2006.189.07:41:58.31#ibcon#*after write, iclass 11, count 0 2006.189.07:41:58.31#ibcon#*before return 0, iclass 11, count 0 2006.189.07:41:58.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:41:58.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:41:58.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:41:58.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:41:58.31$vc4f8/valo=2,572.99 2006.189.07:41:58.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.07:41:58.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.07:41:58.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:41:58.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:41:58.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:41:58.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:41:58.31#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:41:58.31#ibcon#first serial, iclass 13, count 0 2006.189.07:41:58.31#ibcon#enter sib2, iclass 13, count 0 2006.189.07:41:58.31#ibcon#flushed, iclass 13, count 0 2006.189.07:41:58.31#ibcon#about to write, iclass 13, count 0 2006.189.07:41:58.31#ibcon#wrote, iclass 13, count 0 2006.189.07:41:58.31#ibcon#about to read 3, iclass 13, count 0 2006.189.07:41:58.33#ibcon#read 3, iclass 13, count 0 2006.189.07:41:58.33#ibcon#about to read 4, iclass 13, count 0 2006.189.07:41:58.33#ibcon#read 4, iclass 13, count 0 2006.189.07:41:58.33#ibcon#about to read 5, iclass 13, count 0 2006.189.07:41:58.33#ibcon#read 5, iclass 13, count 0 2006.189.07:41:58.33#ibcon#about to read 6, iclass 13, count 0 2006.189.07:41:58.33#ibcon#read 6, iclass 13, count 0 2006.189.07:41:58.33#ibcon#end of sib2, iclass 13, count 0 2006.189.07:41:58.33#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:41:58.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:41:58.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:41:58.33#ibcon#*before write, iclass 13, count 0 2006.189.07:41:58.33#ibcon#enter sib2, iclass 13, count 0 2006.189.07:41:58.33#ibcon#flushed, iclass 13, count 0 2006.189.07:41:58.33#ibcon#about to write, iclass 13, count 0 2006.189.07:41:58.33#ibcon#wrote, iclass 13, count 0 2006.189.07:41:58.33#ibcon#about to read 3, iclass 13, count 0 2006.189.07:41:58.37#ibcon#read 3, iclass 13, count 0 2006.189.07:41:58.37#ibcon#about to read 4, iclass 13, count 0 2006.189.07:41:58.37#ibcon#read 4, iclass 13, count 0 2006.189.07:41:58.37#ibcon#about to read 5, iclass 13, count 0 2006.189.07:41:58.38#ibcon#read 5, iclass 13, count 0 2006.189.07:41:58.38#ibcon#about to read 6, iclass 13, count 0 2006.189.07:41:58.38#ibcon#read 6, iclass 13, count 0 2006.189.07:41:58.38#ibcon#end of sib2, iclass 13, count 0 2006.189.07:41:58.38#ibcon#*after write, iclass 13, count 0 2006.189.07:41:58.38#ibcon#*before return 0, iclass 13, count 0 2006.189.07:41:58.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:41:58.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:41:58.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:41:58.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:41:58.38$vc4f8/va=2,7 2006.189.07:41:58.38#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.07:41:58.38#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.07:41:58.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:41:58.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:41:58.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:41:58.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:41:58.42#ibcon#enter wrdev, iclass 15, count 2 2006.189.07:41:58.42#ibcon#first serial, iclass 15, count 2 2006.189.07:41:58.42#ibcon#enter sib2, iclass 15, count 2 2006.189.07:41:58.42#ibcon#flushed, iclass 15, count 2 2006.189.07:41:58.42#ibcon#about to write, iclass 15, count 2 2006.189.07:41:58.42#ibcon#wrote, iclass 15, count 2 2006.189.07:41:58.42#ibcon#about to read 3, iclass 15, count 2 2006.189.07:41:58.44#ibcon#read 3, iclass 15, count 2 2006.189.07:41:58.44#ibcon#about to read 4, iclass 15, count 2 2006.189.07:41:58.44#ibcon#read 4, iclass 15, count 2 2006.189.07:41:58.44#ibcon#about to read 5, iclass 15, count 2 2006.189.07:41:58.44#ibcon#read 5, iclass 15, count 2 2006.189.07:41:58.44#ibcon#about to read 6, iclass 15, count 2 2006.189.07:41:58.44#ibcon#read 6, iclass 15, count 2 2006.189.07:41:58.44#ibcon#end of sib2, iclass 15, count 2 2006.189.07:41:58.44#ibcon#*mode == 0, iclass 15, count 2 2006.189.07:41:58.44#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.07:41:58.44#ibcon#[25=AT02-07\r\n] 2006.189.07:41:58.44#ibcon#*before write, iclass 15, count 2 2006.189.07:41:58.44#ibcon#enter sib2, iclass 15, count 2 2006.189.07:41:58.44#ibcon#flushed, iclass 15, count 2 2006.189.07:41:58.44#ibcon#about to write, iclass 15, count 2 2006.189.07:41:58.44#ibcon#wrote, iclass 15, count 2 2006.189.07:41:58.44#ibcon#about to read 3, iclass 15, count 2 2006.189.07:41:58.47#ibcon#read 3, iclass 15, count 2 2006.189.07:41:58.47#ibcon#about to read 4, iclass 15, count 2 2006.189.07:41:58.47#ibcon#read 4, iclass 15, count 2 2006.189.07:41:58.47#ibcon#about to read 5, iclass 15, count 2 2006.189.07:41:58.47#ibcon#read 5, iclass 15, count 2 2006.189.07:41:58.47#ibcon#about to read 6, iclass 15, count 2 2006.189.07:41:58.47#ibcon#read 6, iclass 15, count 2 2006.189.07:41:58.47#ibcon#end of sib2, iclass 15, count 2 2006.189.07:41:58.47#ibcon#*after write, iclass 15, count 2 2006.189.07:41:58.47#ibcon#*before return 0, iclass 15, count 2 2006.189.07:41:58.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:41:58.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:41:58.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.07:41:58.47#ibcon#ireg 7 cls_cnt 0 2006.189.07:41:58.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:41:58.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:41:58.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:41:58.59#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:41:58.59#ibcon#first serial, iclass 15, count 0 2006.189.07:41:58.59#ibcon#enter sib2, iclass 15, count 0 2006.189.07:41:58.59#ibcon#flushed, iclass 15, count 0 2006.189.07:41:58.59#ibcon#about to write, iclass 15, count 0 2006.189.07:41:58.59#ibcon#wrote, iclass 15, count 0 2006.189.07:41:58.59#ibcon#about to read 3, iclass 15, count 0 2006.189.07:41:58.61#ibcon#read 3, iclass 15, count 0 2006.189.07:41:58.61#ibcon#about to read 4, iclass 15, count 0 2006.189.07:41:58.61#ibcon#read 4, iclass 15, count 0 2006.189.07:41:58.61#ibcon#about to read 5, iclass 15, count 0 2006.189.07:41:58.61#ibcon#read 5, iclass 15, count 0 2006.189.07:41:58.61#ibcon#about to read 6, iclass 15, count 0 2006.189.07:41:58.61#ibcon#read 6, iclass 15, count 0 2006.189.07:41:58.61#ibcon#end of sib2, iclass 15, count 0 2006.189.07:41:58.61#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:41:58.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:41:58.61#ibcon#[25=USB\r\n] 2006.189.07:41:58.61#ibcon#*before write, iclass 15, count 0 2006.189.07:41:58.61#ibcon#enter sib2, iclass 15, count 0 2006.189.07:41:58.61#ibcon#flushed, iclass 15, count 0 2006.189.07:41:58.61#ibcon#about to write, iclass 15, count 0 2006.189.07:41:58.61#ibcon#wrote, iclass 15, count 0 2006.189.07:41:58.61#ibcon#about to read 3, iclass 15, count 0 2006.189.07:41:58.64#ibcon#read 3, iclass 15, count 0 2006.189.07:41:58.64#ibcon#about to read 4, iclass 15, count 0 2006.189.07:41:58.64#ibcon#read 4, iclass 15, count 0 2006.189.07:41:58.64#ibcon#about to read 5, iclass 15, count 0 2006.189.07:41:58.64#ibcon#read 5, iclass 15, count 0 2006.189.07:41:58.64#ibcon#about to read 6, iclass 15, count 0 2006.189.07:41:58.64#ibcon#read 6, iclass 15, count 0 2006.189.07:41:58.64#ibcon#end of sib2, iclass 15, count 0 2006.189.07:41:58.64#ibcon#*after write, iclass 15, count 0 2006.189.07:41:58.64#ibcon#*before return 0, iclass 15, count 0 2006.189.07:41:58.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:41:58.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:41:58.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:41:58.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:41:58.64$vc4f8/valo=3,672.99 2006.189.07:41:58.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:41:58.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:41:58.64#ibcon#ireg 17 cls_cnt 0 2006.189.07:41:58.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:41:58.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:41:58.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:41:58.64#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:41:58.64#ibcon#first serial, iclass 17, count 0 2006.189.07:41:58.64#ibcon#enter sib2, iclass 17, count 0 2006.189.07:41:58.64#ibcon#flushed, iclass 17, count 0 2006.189.07:41:58.64#ibcon#about to write, iclass 17, count 0 2006.189.07:41:58.64#ibcon#wrote, iclass 17, count 0 2006.189.07:41:58.64#ibcon#about to read 3, iclass 17, count 0 2006.189.07:41:58.66#ibcon#read 3, iclass 17, count 0 2006.189.07:41:58.66#ibcon#about to read 4, iclass 17, count 0 2006.189.07:41:58.66#ibcon#read 4, iclass 17, count 0 2006.189.07:41:58.66#ibcon#about to read 5, iclass 17, count 0 2006.189.07:41:58.66#ibcon#read 5, iclass 17, count 0 2006.189.07:41:58.66#ibcon#about to read 6, iclass 17, count 0 2006.189.07:41:58.66#ibcon#read 6, iclass 17, count 0 2006.189.07:41:58.66#ibcon#end of sib2, iclass 17, count 0 2006.189.07:41:58.66#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:41:58.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:41:58.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:41:58.66#ibcon#*before write, iclass 17, count 0 2006.189.07:41:58.66#ibcon#enter sib2, iclass 17, count 0 2006.189.07:41:58.66#ibcon#flushed, iclass 17, count 0 2006.189.07:41:58.66#ibcon#about to write, iclass 17, count 0 2006.189.07:41:58.66#ibcon#wrote, iclass 17, count 0 2006.189.07:41:58.66#ibcon#about to read 3, iclass 17, count 0 2006.189.07:41:58.70#ibcon#read 3, iclass 17, count 0 2006.189.07:41:58.70#ibcon#about to read 4, iclass 17, count 0 2006.189.07:41:58.70#ibcon#read 4, iclass 17, count 0 2006.189.07:41:58.70#ibcon#about to read 5, iclass 17, count 0 2006.189.07:41:58.71#ibcon#read 5, iclass 17, count 0 2006.189.07:41:58.71#ibcon#about to read 6, iclass 17, count 0 2006.189.07:41:58.71#ibcon#read 6, iclass 17, count 0 2006.189.07:41:58.71#ibcon#end of sib2, iclass 17, count 0 2006.189.07:41:58.71#ibcon#*after write, iclass 17, count 0 2006.189.07:41:58.71#ibcon#*before return 0, iclass 17, count 0 2006.189.07:41:58.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:41:58.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:41:58.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:41:58.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:41:58.71$vc4f8/va=3,6 2006.189.07:41:58.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.07:41:58.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.07:41:58.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:41:58.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:41:58.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:41:58.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:41:58.75#ibcon#enter wrdev, iclass 19, count 2 2006.189.07:41:58.75#ibcon#first serial, iclass 19, count 2 2006.189.07:41:58.75#ibcon#enter sib2, iclass 19, count 2 2006.189.07:41:58.75#ibcon#flushed, iclass 19, count 2 2006.189.07:41:58.75#ibcon#about to write, iclass 19, count 2 2006.189.07:41:58.75#ibcon#wrote, iclass 19, count 2 2006.189.07:41:58.75#ibcon#about to read 3, iclass 19, count 2 2006.189.07:41:58.77#ibcon#read 3, iclass 19, count 2 2006.189.07:41:58.77#ibcon#about to read 4, iclass 19, count 2 2006.189.07:41:58.77#ibcon#read 4, iclass 19, count 2 2006.189.07:41:58.77#ibcon#about to read 5, iclass 19, count 2 2006.189.07:41:58.77#ibcon#read 5, iclass 19, count 2 2006.189.07:41:58.77#ibcon#about to read 6, iclass 19, count 2 2006.189.07:41:58.77#ibcon#read 6, iclass 19, count 2 2006.189.07:41:58.77#ibcon#end of sib2, iclass 19, count 2 2006.189.07:41:58.77#ibcon#*mode == 0, iclass 19, count 2 2006.189.07:41:58.77#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.07:41:58.77#ibcon#[25=AT03-06\r\n] 2006.189.07:41:58.77#ibcon#*before write, iclass 19, count 2 2006.189.07:41:58.77#ibcon#enter sib2, iclass 19, count 2 2006.189.07:41:58.77#ibcon#flushed, iclass 19, count 2 2006.189.07:41:58.77#ibcon#about to write, iclass 19, count 2 2006.189.07:41:58.77#ibcon#wrote, iclass 19, count 2 2006.189.07:41:58.77#ibcon#about to read 3, iclass 19, count 2 2006.189.07:41:58.80#ibcon#read 3, iclass 19, count 2 2006.189.07:41:58.80#ibcon#about to read 4, iclass 19, count 2 2006.189.07:41:58.80#ibcon#read 4, iclass 19, count 2 2006.189.07:41:58.80#ibcon#about to read 5, iclass 19, count 2 2006.189.07:41:58.80#ibcon#read 5, iclass 19, count 2 2006.189.07:41:58.80#ibcon#about to read 6, iclass 19, count 2 2006.189.07:41:58.80#ibcon#read 6, iclass 19, count 2 2006.189.07:41:58.80#ibcon#end of sib2, iclass 19, count 2 2006.189.07:41:58.80#ibcon#*after write, iclass 19, count 2 2006.189.07:41:58.80#ibcon#*before return 0, iclass 19, count 2 2006.189.07:41:58.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:41:58.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:41:58.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.07:41:58.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:41:58.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:41:58.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:41:58.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:41:58.92#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:41:58.92#ibcon#first serial, iclass 19, count 0 2006.189.07:41:58.92#ibcon#enter sib2, iclass 19, count 0 2006.189.07:41:58.92#ibcon#flushed, iclass 19, count 0 2006.189.07:41:58.92#ibcon#about to write, iclass 19, count 0 2006.189.07:41:58.92#ibcon#wrote, iclass 19, count 0 2006.189.07:41:58.92#ibcon#about to read 3, iclass 19, count 0 2006.189.07:41:58.94#ibcon#read 3, iclass 19, count 0 2006.189.07:41:58.94#ibcon#about to read 4, iclass 19, count 0 2006.189.07:41:58.94#ibcon#read 4, iclass 19, count 0 2006.189.07:41:58.94#ibcon#about to read 5, iclass 19, count 0 2006.189.07:41:58.94#ibcon#read 5, iclass 19, count 0 2006.189.07:41:58.94#ibcon#about to read 6, iclass 19, count 0 2006.189.07:41:58.94#ibcon#read 6, iclass 19, count 0 2006.189.07:41:58.94#ibcon#end of sib2, iclass 19, count 0 2006.189.07:41:58.94#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:41:58.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:41:58.94#ibcon#[25=USB\r\n] 2006.189.07:41:58.94#ibcon#*before write, iclass 19, count 0 2006.189.07:41:58.94#ibcon#enter sib2, iclass 19, count 0 2006.189.07:41:58.94#ibcon#flushed, iclass 19, count 0 2006.189.07:41:58.94#ibcon#about to write, iclass 19, count 0 2006.189.07:41:58.94#ibcon#wrote, iclass 19, count 0 2006.189.07:41:58.94#ibcon#about to read 3, iclass 19, count 0 2006.189.07:41:58.97#ibcon#read 3, iclass 19, count 0 2006.189.07:41:58.97#ibcon#about to read 4, iclass 19, count 0 2006.189.07:41:58.97#ibcon#read 4, iclass 19, count 0 2006.189.07:41:58.97#ibcon#about to read 5, iclass 19, count 0 2006.189.07:41:58.97#ibcon#read 5, iclass 19, count 0 2006.189.07:41:58.97#ibcon#about to read 6, iclass 19, count 0 2006.189.07:41:58.97#ibcon#read 6, iclass 19, count 0 2006.189.07:41:58.97#ibcon#end of sib2, iclass 19, count 0 2006.189.07:41:58.97#ibcon#*after write, iclass 19, count 0 2006.189.07:41:58.97#ibcon#*before return 0, iclass 19, count 0 2006.189.07:41:58.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:41:58.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:41:58.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:41:58.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:41:58.97$vc4f8/valo=4,832.99 2006.189.07:41:58.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:41:58.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:41:58.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:41:58.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:41:58.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:41:58.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:41:58.97#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:41:58.97#ibcon#first serial, iclass 21, count 0 2006.189.07:41:58.97#ibcon#enter sib2, iclass 21, count 0 2006.189.07:41:58.97#ibcon#flushed, iclass 21, count 0 2006.189.07:41:58.97#ibcon#about to write, iclass 21, count 0 2006.189.07:41:58.97#ibcon#wrote, iclass 21, count 0 2006.189.07:41:58.97#ibcon#about to read 3, iclass 21, count 0 2006.189.07:41:58.99#ibcon#read 3, iclass 21, count 0 2006.189.07:41:58.99#ibcon#about to read 4, iclass 21, count 0 2006.189.07:41:58.99#ibcon#read 4, iclass 21, count 0 2006.189.07:41:58.99#ibcon#about to read 5, iclass 21, count 0 2006.189.07:41:58.99#ibcon#read 5, iclass 21, count 0 2006.189.07:41:58.99#ibcon#about to read 6, iclass 21, count 0 2006.189.07:41:58.99#ibcon#read 6, iclass 21, count 0 2006.189.07:41:58.99#ibcon#end of sib2, iclass 21, count 0 2006.189.07:41:58.99#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:41:58.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:41:58.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:41:58.99#ibcon#*before write, iclass 21, count 0 2006.189.07:41:58.99#ibcon#enter sib2, iclass 21, count 0 2006.189.07:41:58.99#ibcon#flushed, iclass 21, count 0 2006.189.07:41:58.99#ibcon#about to write, iclass 21, count 0 2006.189.07:41:58.99#ibcon#wrote, iclass 21, count 0 2006.189.07:41:58.99#ibcon#about to read 3, iclass 21, count 0 2006.189.07:41:59.03#ibcon#read 3, iclass 21, count 0 2006.189.07:41:59.03#ibcon#about to read 4, iclass 21, count 0 2006.189.07:41:59.03#ibcon#read 4, iclass 21, count 0 2006.189.07:41:59.03#ibcon#about to read 5, iclass 21, count 0 2006.189.07:41:59.03#ibcon#read 5, iclass 21, count 0 2006.189.07:41:59.03#ibcon#about to read 6, iclass 21, count 0 2006.189.07:41:59.03#ibcon#read 6, iclass 21, count 0 2006.189.07:41:59.03#ibcon#end of sib2, iclass 21, count 0 2006.189.07:41:59.03#ibcon#*after write, iclass 21, count 0 2006.189.07:41:59.03#ibcon#*before return 0, iclass 21, count 0 2006.189.07:41:59.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:41:59.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:41:59.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:41:59.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:41:59.03$vc4f8/va=4,7 2006.189.07:41:59.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:41:59.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:41:59.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:41:59.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:41:59.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:41:59.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:41:59.09#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:41:59.09#ibcon#first serial, iclass 23, count 2 2006.189.07:41:59.09#ibcon#enter sib2, iclass 23, count 2 2006.189.07:41:59.09#ibcon#flushed, iclass 23, count 2 2006.189.07:41:59.09#ibcon#about to write, iclass 23, count 2 2006.189.07:41:59.09#ibcon#wrote, iclass 23, count 2 2006.189.07:41:59.09#ibcon#about to read 3, iclass 23, count 2 2006.189.07:41:59.11#ibcon#read 3, iclass 23, count 2 2006.189.07:41:59.11#ibcon#about to read 4, iclass 23, count 2 2006.189.07:41:59.11#ibcon#read 4, iclass 23, count 2 2006.189.07:41:59.11#ibcon#about to read 5, iclass 23, count 2 2006.189.07:41:59.11#ibcon#read 5, iclass 23, count 2 2006.189.07:41:59.11#ibcon#about to read 6, iclass 23, count 2 2006.189.07:41:59.11#ibcon#read 6, iclass 23, count 2 2006.189.07:41:59.11#ibcon#end of sib2, iclass 23, count 2 2006.189.07:41:59.11#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:41:59.11#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:41:59.11#ibcon#[25=AT04-07\r\n] 2006.189.07:41:59.11#ibcon#*before write, iclass 23, count 2 2006.189.07:41:59.11#ibcon#enter sib2, iclass 23, count 2 2006.189.07:41:59.11#ibcon#flushed, iclass 23, count 2 2006.189.07:41:59.11#ibcon#about to write, iclass 23, count 2 2006.189.07:41:59.11#ibcon#wrote, iclass 23, count 2 2006.189.07:41:59.11#ibcon#about to read 3, iclass 23, count 2 2006.189.07:41:59.14#ibcon#read 3, iclass 23, count 2 2006.189.07:41:59.14#ibcon#about to read 4, iclass 23, count 2 2006.189.07:41:59.14#ibcon#read 4, iclass 23, count 2 2006.189.07:41:59.14#ibcon#about to read 5, iclass 23, count 2 2006.189.07:41:59.14#ibcon#read 5, iclass 23, count 2 2006.189.07:41:59.14#ibcon#about to read 6, iclass 23, count 2 2006.189.07:41:59.14#ibcon#read 6, iclass 23, count 2 2006.189.07:41:59.14#ibcon#end of sib2, iclass 23, count 2 2006.189.07:41:59.14#ibcon#*after write, iclass 23, count 2 2006.189.07:41:59.14#ibcon#*before return 0, iclass 23, count 2 2006.189.07:41:59.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:41:59.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:41:59.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:41:59.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:41:59.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:41:59.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:41:59.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:41:59.26#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:41:59.26#ibcon#first serial, iclass 23, count 0 2006.189.07:41:59.26#ibcon#enter sib2, iclass 23, count 0 2006.189.07:41:59.26#ibcon#flushed, iclass 23, count 0 2006.189.07:41:59.26#ibcon#about to write, iclass 23, count 0 2006.189.07:41:59.26#ibcon#wrote, iclass 23, count 0 2006.189.07:41:59.26#ibcon#about to read 3, iclass 23, count 0 2006.189.07:41:59.28#ibcon#read 3, iclass 23, count 0 2006.189.07:41:59.28#ibcon#about to read 4, iclass 23, count 0 2006.189.07:41:59.28#ibcon#read 4, iclass 23, count 0 2006.189.07:41:59.28#ibcon#about to read 5, iclass 23, count 0 2006.189.07:41:59.28#ibcon#read 5, iclass 23, count 0 2006.189.07:41:59.28#ibcon#about to read 6, iclass 23, count 0 2006.189.07:41:59.28#ibcon#read 6, iclass 23, count 0 2006.189.07:41:59.28#ibcon#end of sib2, iclass 23, count 0 2006.189.07:41:59.28#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:41:59.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:41:59.28#ibcon#[25=USB\r\n] 2006.189.07:41:59.28#ibcon#*before write, iclass 23, count 0 2006.189.07:41:59.28#ibcon#enter sib2, iclass 23, count 0 2006.189.07:41:59.28#ibcon#flushed, iclass 23, count 0 2006.189.07:41:59.28#ibcon#about to write, iclass 23, count 0 2006.189.07:41:59.28#ibcon#wrote, iclass 23, count 0 2006.189.07:41:59.28#ibcon#about to read 3, iclass 23, count 0 2006.189.07:41:59.31#ibcon#read 3, iclass 23, count 0 2006.189.07:41:59.31#ibcon#about to read 4, iclass 23, count 0 2006.189.07:41:59.31#ibcon#read 4, iclass 23, count 0 2006.189.07:41:59.31#ibcon#about to read 5, iclass 23, count 0 2006.189.07:41:59.31#ibcon#read 5, iclass 23, count 0 2006.189.07:41:59.31#ibcon#about to read 6, iclass 23, count 0 2006.189.07:41:59.31#ibcon#read 6, iclass 23, count 0 2006.189.07:41:59.31#ibcon#end of sib2, iclass 23, count 0 2006.189.07:41:59.31#ibcon#*after write, iclass 23, count 0 2006.189.07:41:59.31#ibcon#*before return 0, iclass 23, count 0 2006.189.07:41:59.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:41:59.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:41:59.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:41:59.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:41:59.31$vc4f8/valo=5,652.99 2006.189.07:41:59.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:41:59.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:41:59.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:41:59.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:41:59.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:41:59.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:41:59.31#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:41:59.31#ibcon#first serial, iclass 25, count 0 2006.189.07:41:59.31#ibcon#enter sib2, iclass 25, count 0 2006.189.07:41:59.31#ibcon#flushed, iclass 25, count 0 2006.189.07:41:59.31#ibcon#about to write, iclass 25, count 0 2006.189.07:41:59.31#ibcon#wrote, iclass 25, count 0 2006.189.07:41:59.31#ibcon#about to read 3, iclass 25, count 0 2006.189.07:41:59.33#ibcon#read 3, iclass 25, count 0 2006.189.07:41:59.33#ibcon#about to read 4, iclass 25, count 0 2006.189.07:41:59.33#ibcon#read 4, iclass 25, count 0 2006.189.07:41:59.33#ibcon#about to read 5, iclass 25, count 0 2006.189.07:41:59.33#ibcon#read 5, iclass 25, count 0 2006.189.07:41:59.33#ibcon#about to read 6, iclass 25, count 0 2006.189.07:41:59.33#ibcon#read 6, iclass 25, count 0 2006.189.07:41:59.33#ibcon#end of sib2, iclass 25, count 0 2006.189.07:41:59.33#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:41:59.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:41:59.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:41:59.33#ibcon#*before write, iclass 25, count 0 2006.189.07:41:59.33#ibcon#enter sib2, iclass 25, count 0 2006.189.07:41:59.33#ibcon#flushed, iclass 25, count 0 2006.189.07:41:59.33#ibcon#about to write, iclass 25, count 0 2006.189.07:41:59.33#ibcon#wrote, iclass 25, count 0 2006.189.07:41:59.33#ibcon#about to read 3, iclass 25, count 0 2006.189.07:41:59.37#ibcon#read 3, iclass 25, count 0 2006.189.07:41:59.37#ibcon#about to read 4, iclass 25, count 0 2006.189.07:41:59.37#ibcon#read 4, iclass 25, count 0 2006.189.07:41:59.37#ibcon#about to read 5, iclass 25, count 0 2006.189.07:41:59.37#ibcon#read 5, iclass 25, count 0 2006.189.07:41:59.37#ibcon#about to read 6, iclass 25, count 0 2006.189.07:41:59.37#ibcon#read 6, iclass 25, count 0 2006.189.07:41:59.37#ibcon#end of sib2, iclass 25, count 0 2006.189.07:41:59.37#ibcon#*after write, iclass 25, count 0 2006.189.07:41:59.37#ibcon#*before return 0, iclass 25, count 0 2006.189.07:41:59.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:41:59.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:41:59.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:41:59.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:41:59.37$vc4f8/va=5,7 2006.189.07:41:59.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:41:59.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:41:59.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:41:59.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:41:59.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:41:59.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:41:59.43#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:41:59.43#ibcon#first serial, iclass 27, count 2 2006.189.07:41:59.43#ibcon#enter sib2, iclass 27, count 2 2006.189.07:41:59.43#ibcon#flushed, iclass 27, count 2 2006.189.07:41:59.43#ibcon#about to write, iclass 27, count 2 2006.189.07:41:59.43#ibcon#wrote, iclass 27, count 2 2006.189.07:41:59.43#ibcon#about to read 3, iclass 27, count 2 2006.189.07:41:59.45#ibcon#read 3, iclass 27, count 2 2006.189.07:41:59.45#ibcon#about to read 4, iclass 27, count 2 2006.189.07:41:59.45#ibcon#read 4, iclass 27, count 2 2006.189.07:41:59.45#ibcon#about to read 5, iclass 27, count 2 2006.189.07:41:59.45#ibcon#read 5, iclass 27, count 2 2006.189.07:41:59.45#ibcon#about to read 6, iclass 27, count 2 2006.189.07:41:59.45#ibcon#read 6, iclass 27, count 2 2006.189.07:41:59.45#ibcon#end of sib2, iclass 27, count 2 2006.189.07:41:59.45#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:41:59.45#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:41:59.45#ibcon#[25=AT05-07\r\n] 2006.189.07:41:59.45#ibcon#*before write, iclass 27, count 2 2006.189.07:41:59.45#ibcon#enter sib2, iclass 27, count 2 2006.189.07:41:59.45#ibcon#flushed, iclass 27, count 2 2006.189.07:41:59.45#ibcon#about to write, iclass 27, count 2 2006.189.07:41:59.45#ibcon#wrote, iclass 27, count 2 2006.189.07:41:59.45#ibcon#about to read 3, iclass 27, count 2 2006.189.07:41:59.48#ibcon#read 3, iclass 27, count 2 2006.189.07:41:59.48#ibcon#about to read 4, iclass 27, count 2 2006.189.07:41:59.48#ibcon#read 4, iclass 27, count 2 2006.189.07:41:59.48#ibcon#about to read 5, iclass 27, count 2 2006.189.07:41:59.48#ibcon#read 5, iclass 27, count 2 2006.189.07:41:59.48#ibcon#about to read 6, iclass 27, count 2 2006.189.07:41:59.48#ibcon#read 6, iclass 27, count 2 2006.189.07:41:59.48#ibcon#end of sib2, iclass 27, count 2 2006.189.07:41:59.48#ibcon#*after write, iclass 27, count 2 2006.189.07:41:59.48#ibcon#*before return 0, iclass 27, count 2 2006.189.07:41:59.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:41:59.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:41:59.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:41:59.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:41:59.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:41:59.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:41:59.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:41:59.60#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:41:59.60#ibcon#first serial, iclass 27, count 0 2006.189.07:41:59.60#ibcon#enter sib2, iclass 27, count 0 2006.189.07:41:59.60#ibcon#flushed, iclass 27, count 0 2006.189.07:41:59.60#ibcon#about to write, iclass 27, count 0 2006.189.07:41:59.60#ibcon#wrote, iclass 27, count 0 2006.189.07:41:59.60#ibcon#about to read 3, iclass 27, count 0 2006.189.07:41:59.62#ibcon#read 3, iclass 27, count 0 2006.189.07:41:59.62#ibcon#about to read 4, iclass 27, count 0 2006.189.07:41:59.62#ibcon#read 4, iclass 27, count 0 2006.189.07:41:59.62#ibcon#about to read 5, iclass 27, count 0 2006.189.07:41:59.62#ibcon#read 5, iclass 27, count 0 2006.189.07:41:59.62#ibcon#about to read 6, iclass 27, count 0 2006.189.07:41:59.62#ibcon#read 6, iclass 27, count 0 2006.189.07:41:59.62#ibcon#end of sib2, iclass 27, count 0 2006.189.07:41:59.62#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:41:59.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:41:59.62#ibcon#[25=USB\r\n] 2006.189.07:41:59.62#ibcon#*before write, iclass 27, count 0 2006.189.07:41:59.62#ibcon#enter sib2, iclass 27, count 0 2006.189.07:41:59.62#ibcon#flushed, iclass 27, count 0 2006.189.07:41:59.62#ibcon#about to write, iclass 27, count 0 2006.189.07:41:59.62#ibcon#wrote, iclass 27, count 0 2006.189.07:41:59.62#ibcon#about to read 3, iclass 27, count 0 2006.189.07:41:59.65#ibcon#read 3, iclass 27, count 0 2006.189.07:41:59.65#ibcon#about to read 4, iclass 27, count 0 2006.189.07:41:59.65#ibcon#read 4, iclass 27, count 0 2006.189.07:41:59.65#ibcon#about to read 5, iclass 27, count 0 2006.189.07:41:59.65#ibcon#read 5, iclass 27, count 0 2006.189.07:41:59.65#ibcon#about to read 6, iclass 27, count 0 2006.189.07:41:59.65#ibcon#read 6, iclass 27, count 0 2006.189.07:41:59.65#ibcon#end of sib2, iclass 27, count 0 2006.189.07:41:59.65#ibcon#*after write, iclass 27, count 0 2006.189.07:41:59.65#ibcon#*before return 0, iclass 27, count 0 2006.189.07:41:59.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:41:59.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:41:59.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:41:59.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:41:59.65$vc4f8/valo=6,772.99 2006.189.07:41:59.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:41:59.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:41:59.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:41:59.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:41:59.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:41:59.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:41:59.65#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:41:59.65#ibcon#first serial, iclass 29, count 0 2006.189.07:41:59.65#ibcon#enter sib2, iclass 29, count 0 2006.189.07:41:59.65#ibcon#flushed, iclass 29, count 0 2006.189.07:41:59.65#ibcon#about to write, iclass 29, count 0 2006.189.07:41:59.65#ibcon#wrote, iclass 29, count 0 2006.189.07:41:59.65#ibcon#about to read 3, iclass 29, count 0 2006.189.07:41:59.67#ibcon#read 3, iclass 29, count 0 2006.189.07:41:59.67#ibcon#about to read 4, iclass 29, count 0 2006.189.07:41:59.67#ibcon#read 4, iclass 29, count 0 2006.189.07:41:59.67#ibcon#about to read 5, iclass 29, count 0 2006.189.07:41:59.67#ibcon#read 5, iclass 29, count 0 2006.189.07:41:59.67#ibcon#about to read 6, iclass 29, count 0 2006.189.07:41:59.67#ibcon#read 6, iclass 29, count 0 2006.189.07:41:59.67#ibcon#end of sib2, iclass 29, count 0 2006.189.07:41:59.67#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:41:59.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:41:59.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:41:59.67#ibcon#*before write, iclass 29, count 0 2006.189.07:41:59.67#ibcon#enter sib2, iclass 29, count 0 2006.189.07:41:59.67#ibcon#flushed, iclass 29, count 0 2006.189.07:41:59.67#ibcon#about to write, iclass 29, count 0 2006.189.07:41:59.67#ibcon#wrote, iclass 29, count 0 2006.189.07:41:59.67#ibcon#about to read 3, iclass 29, count 0 2006.189.07:41:59.71#ibcon#read 3, iclass 29, count 0 2006.189.07:41:59.71#ibcon#about to read 4, iclass 29, count 0 2006.189.07:41:59.71#ibcon#read 4, iclass 29, count 0 2006.189.07:41:59.71#ibcon#about to read 5, iclass 29, count 0 2006.189.07:41:59.71#ibcon#read 5, iclass 29, count 0 2006.189.07:41:59.71#ibcon#about to read 6, iclass 29, count 0 2006.189.07:41:59.71#ibcon#read 6, iclass 29, count 0 2006.189.07:41:59.71#ibcon#end of sib2, iclass 29, count 0 2006.189.07:41:59.71#ibcon#*after write, iclass 29, count 0 2006.189.07:41:59.71#ibcon#*before return 0, iclass 29, count 0 2006.189.07:41:59.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:41:59.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:41:59.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:41:59.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:41:59.71$vc4f8/va=6,6 2006.189.07:41:59.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.07:41:59.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.07:41:59.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:41:59.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:41:59.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:41:59.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:41:59.77#ibcon#enter wrdev, iclass 31, count 2 2006.189.07:41:59.77#ibcon#first serial, iclass 31, count 2 2006.189.07:41:59.77#ibcon#enter sib2, iclass 31, count 2 2006.189.07:41:59.77#ibcon#flushed, iclass 31, count 2 2006.189.07:41:59.77#ibcon#about to write, iclass 31, count 2 2006.189.07:41:59.77#ibcon#wrote, iclass 31, count 2 2006.189.07:41:59.77#ibcon#about to read 3, iclass 31, count 2 2006.189.07:41:59.79#ibcon#read 3, iclass 31, count 2 2006.189.07:41:59.79#ibcon#about to read 4, iclass 31, count 2 2006.189.07:41:59.79#ibcon#read 4, iclass 31, count 2 2006.189.07:41:59.79#ibcon#about to read 5, iclass 31, count 2 2006.189.07:41:59.79#ibcon#read 5, iclass 31, count 2 2006.189.07:41:59.79#ibcon#about to read 6, iclass 31, count 2 2006.189.07:41:59.79#ibcon#read 6, iclass 31, count 2 2006.189.07:41:59.79#ibcon#end of sib2, iclass 31, count 2 2006.189.07:41:59.79#ibcon#*mode == 0, iclass 31, count 2 2006.189.07:41:59.79#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.07:41:59.79#ibcon#[25=AT06-06\r\n] 2006.189.07:41:59.79#ibcon#*before write, iclass 31, count 2 2006.189.07:41:59.79#ibcon#enter sib2, iclass 31, count 2 2006.189.07:41:59.79#ibcon#flushed, iclass 31, count 2 2006.189.07:41:59.79#ibcon#about to write, iclass 31, count 2 2006.189.07:41:59.79#ibcon#wrote, iclass 31, count 2 2006.189.07:41:59.79#ibcon#about to read 3, iclass 31, count 2 2006.189.07:41:59.82#ibcon#read 3, iclass 31, count 2 2006.189.07:41:59.82#ibcon#about to read 4, iclass 31, count 2 2006.189.07:41:59.82#ibcon#read 4, iclass 31, count 2 2006.189.07:41:59.82#ibcon#about to read 5, iclass 31, count 2 2006.189.07:41:59.82#ibcon#read 5, iclass 31, count 2 2006.189.07:41:59.82#ibcon#about to read 6, iclass 31, count 2 2006.189.07:41:59.82#ibcon#read 6, iclass 31, count 2 2006.189.07:41:59.82#ibcon#end of sib2, iclass 31, count 2 2006.189.07:41:59.82#ibcon#*after write, iclass 31, count 2 2006.189.07:41:59.82#ibcon#*before return 0, iclass 31, count 2 2006.189.07:41:59.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:41:59.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:41:59.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.07:41:59.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:41:59.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:41:59.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:41:59.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:41:59.94#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:41:59.94#ibcon#first serial, iclass 31, count 0 2006.189.07:41:59.94#ibcon#enter sib2, iclass 31, count 0 2006.189.07:41:59.94#ibcon#flushed, iclass 31, count 0 2006.189.07:41:59.94#ibcon#about to write, iclass 31, count 0 2006.189.07:41:59.94#ibcon#wrote, iclass 31, count 0 2006.189.07:41:59.94#ibcon#about to read 3, iclass 31, count 0 2006.189.07:41:59.96#ibcon#read 3, iclass 31, count 0 2006.189.07:41:59.96#ibcon#about to read 4, iclass 31, count 0 2006.189.07:41:59.96#ibcon#read 4, iclass 31, count 0 2006.189.07:41:59.96#ibcon#about to read 5, iclass 31, count 0 2006.189.07:41:59.96#ibcon#read 5, iclass 31, count 0 2006.189.07:41:59.96#ibcon#about to read 6, iclass 31, count 0 2006.189.07:41:59.96#ibcon#read 6, iclass 31, count 0 2006.189.07:41:59.96#ibcon#end of sib2, iclass 31, count 0 2006.189.07:41:59.96#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:41:59.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:41:59.96#ibcon#[25=USB\r\n] 2006.189.07:41:59.96#ibcon#*before write, iclass 31, count 0 2006.189.07:41:59.96#ibcon#enter sib2, iclass 31, count 0 2006.189.07:41:59.96#ibcon#flushed, iclass 31, count 0 2006.189.07:41:59.96#ibcon#about to write, iclass 31, count 0 2006.189.07:41:59.96#ibcon#wrote, iclass 31, count 0 2006.189.07:41:59.96#ibcon#about to read 3, iclass 31, count 0 2006.189.07:41:59.99#ibcon#read 3, iclass 31, count 0 2006.189.07:41:59.99#ibcon#about to read 4, iclass 31, count 0 2006.189.07:41:59.99#ibcon#read 4, iclass 31, count 0 2006.189.07:41:59.99#ibcon#about to read 5, iclass 31, count 0 2006.189.07:41:59.99#ibcon#read 5, iclass 31, count 0 2006.189.07:41:59.99#ibcon#about to read 6, iclass 31, count 0 2006.189.07:41:59.99#ibcon#read 6, iclass 31, count 0 2006.189.07:41:59.99#ibcon#end of sib2, iclass 31, count 0 2006.189.07:41:59.99#ibcon#*after write, iclass 31, count 0 2006.189.07:41:59.99#ibcon#*before return 0, iclass 31, count 0 2006.189.07:41:59.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:41:59.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:41:59.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:41:59.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:41:59.99$vc4f8/valo=7,832.99 2006.189.07:41:59.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:41:59.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:41:59.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:41:59.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:41:59.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:41:59.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:41:59.99#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:41:59.99#ibcon#first serial, iclass 33, count 0 2006.189.07:41:59.99#ibcon#enter sib2, iclass 33, count 0 2006.189.07:41:59.99#ibcon#flushed, iclass 33, count 0 2006.189.07:41:59.99#ibcon#about to write, iclass 33, count 0 2006.189.07:41:59.99#ibcon#wrote, iclass 33, count 0 2006.189.07:41:59.99#ibcon#about to read 3, iclass 33, count 0 2006.189.07:42:00.01#ibcon#read 3, iclass 33, count 0 2006.189.07:42:00.01#ibcon#about to read 4, iclass 33, count 0 2006.189.07:42:00.01#ibcon#read 4, iclass 33, count 0 2006.189.07:42:00.01#ibcon#about to read 5, iclass 33, count 0 2006.189.07:42:00.01#ibcon#read 5, iclass 33, count 0 2006.189.07:42:00.01#ibcon#about to read 6, iclass 33, count 0 2006.189.07:42:00.01#ibcon#read 6, iclass 33, count 0 2006.189.07:42:00.01#ibcon#end of sib2, iclass 33, count 0 2006.189.07:42:00.01#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:42:00.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:42:00.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:42:00.01#ibcon#*before write, iclass 33, count 0 2006.189.07:42:00.01#ibcon#enter sib2, iclass 33, count 0 2006.189.07:42:00.01#ibcon#flushed, iclass 33, count 0 2006.189.07:42:00.01#ibcon#about to write, iclass 33, count 0 2006.189.07:42:00.01#ibcon#wrote, iclass 33, count 0 2006.189.07:42:00.01#ibcon#about to read 3, iclass 33, count 0 2006.189.07:42:00.05#ibcon#read 3, iclass 33, count 0 2006.189.07:42:00.05#ibcon#about to read 4, iclass 33, count 0 2006.189.07:42:00.05#ibcon#read 4, iclass 33, count 0 2006.189.07:42:00.05#ibcon#about to read 5, iclass 33, count 0 2006.189.07:42:00.05#ibcon#read 5, iclass 33, count 0 2006.189.07:42:00.05#ibcon#about to read 6, iclass 33, count 0 2006.189.07:42:00.05#ibcon#read 6, iclass 33, count 0 2006.189.07:42:00.05#ibcon#end of sib2, iclass 33, count 0 2006.189.07:42:00.05#ibcon#*after write, iclass 33, count 0 2006.189.07:42:00.05#ibcon#*before return 0, iclass 33, count 0 2006.189.07:42:00.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:42:00.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:42:00.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:42:00.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:42:00.05$vc4f8/va=7,6 2006.189.07:42:00.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:42:00.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:42:00.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:00.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:42:00.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:42:00.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:42:00.11#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:42:00.11#ibcon#first serial, iclass 35, count 2 2006.189.07:42:00.11#ibcon#enter sib2, iclass 35, count 2 2006.189.07:42:00.11#ibcon#flushed, iclass 35, count 2 2006.189.07:42:00.11#ibcon#about to write, iclass 35, count 2 2006.189.07:42:00.11#ibcon#wrote, iclass 35, count 2 2006.189.07:42:00.11#ibcon#about to read 3, iclass 35, count 2 2006.189.07:42:00.13#ibcon#read 3, iclass 35, count 2 2006.189.07:42:00.13#ibcon#about to read 4, iclass 35, count 2 2006.189.07:42:00.13#ibcon#read 4, iclass 35, count 2 2006.189.07:42:00.13#ibcon#about to read 5, iclass 35, count 2 2006.189.07:42:00.13#ibcon#read 5, iclass 35, count 2 2006.189.07:42:00.13#ibcon#about to read 6, iclass 35, count 2 2006.189.07:42:00.13#ibcon#read 6, iclass 35, count 2 2006.189.07:42:00.13#ibcon#end of sib2, iclass 35, count 2 2006.189.07:42:00.13#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:42:00.13#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:42:00.13#ibcon#[25=AT07-06\r\n] 2006.189.07:42:00.13#ibcon#*before write, iclass 35, count 2 2006.189.07:42:00.13#ibcon#enter sib2, iclass 35, count 2 2006.189.07:42:00.13#ibcon#flushed, iclass 35, count 2 2006.189.07:42:00.13#ibcon#about to write, iclass 35, count 2 2006.189.07:42:00.13#ibcon#wrote, iclass 35, count 2 2006.189.07:42:00.13#ibcon#about to read 3, iclass 35, count 2 2006.189.07:42:00.16#ibcon#read 3, iclass 35, count 2 2006.189.07:42:00.16#ibcon#about to read 4, iclass 35, count 2 2006.189.07:42:00.16#ibcon#read 4, iclass 35, count 2 2006.189.07:42:00.16#ibcon#about to read 5, iclass 35, count 2 2006.189.07:42:00.16#ibcon#read 5, iclass 35, count 2 2006.189.07:42:00.16#ibcon#about to read 6, iclass 35, count 2 2006.189.07:42:00.16#ibcon#read 6, iclass 35, count 2 2006.189.07:42:00.16#ibcon#end of sib2, iclass 35, count 2 2006.189.07:42:00.16#ibcon#*after write, iclass 35, count 2 2006.189.07:42:00.16#ibcon#*before return 0, iclass 35, count 2 2006.189.07:42:00.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:42:00.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:42:00.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:42:00.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:00.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:42:00.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:42:00.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:42:00.28#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:42:00.28#ibcon#first serial, iclass 35, count 0 2006.189.07:42:00.28#ibcon#enter sib2, iclass 35, count 0 2006.189.07:42:00.28#ibcon#flushed, iclass 35, count 0 2006.189.07:42:00.28#ibcon#about to write, iclass 35, count 0 2006.189.07:42:00.28#ibcon#wrote, iclass 35, count 0 2006.189.07:42:00.28#ibcon#about to read 3, iclass 35, count 0 2006.189.07:42:00.30#ibcon#read 3, iclass 35, count 0 2006.189.07:42:00.30#ibcon#about to read 4, iclass 35, count 0 2006.189.07:42:00.30#ibcon#read 4, iclass 35, count 0 2006.189.07:42:00.30#ibcon#about to read 5, iclass 35, count 0 2006.189.07:42:00.30#ibcon#read 5, iclass 35, count 0 2006.189.07:42:00.30#ibcon#about to read 6, iclass 35, count 0 2006.189.07:42:00.30#ibcon#read 6, iclass 35, count 0 2006.189.07:42:00.30#ibcon#end of sib2, iclass 35, count 0 2006.189.07:42:00.30#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:42:00.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:42:00.30#ibcon#[25=USB\r\n] 2006.189.07:42:00.30#ibcon#*before write, iclass 35, count 0 2006.189.07:42:00.30#ibcon#enter sib2, iclass 35, count 0 2006.189.07:42:00.30#ibcon#flushed, iclass 35, count 0 2006.189.07:42:00.30#ibcon#about to write, iclass 35, count 0 2006.189.07:42:00.30#ibcon#wrote, iclass 35, count 0 2006.189.07:42:00.30#ibcon#about to read 3, iclass 35, count 0 2006.189.07:42:00.33#ibcon#read 3, iclass 35, count 0 2006.189.07:42:00.33#ibcon#about to read 4, iclass 35, count 0 2006.189.07:42:00.33#ibcon#read 4, iclass 35, count 0 2006.189.07:42:00.33#ibcon#about to read 5, iclass 35, count 0 2006.189.07:42:00.33#ibcon#read 5, iclass 35, count 0 2006.189.07:42:00.33#ibcon#about to read 6, iclass 35, count 0 2006.189.07:42:00.33#ibcon#read 6, iclass 35, count 0 2006.189.07:42:00.33#ibcon#end of sib2, iclass 35, count 0 2006.189.07:42:00.33#ibcon#*after write, iclass 35, count 0 2006.189.07:42:00.33#ibcon#*before return 0, iclass 35, count 0 2006.189.07:42:00.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:42:00.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:42:00.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:42:00.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:42:00.33$vc4f8/valo=8,852.99 2006.189.07:42:00.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:42:00.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:42:00.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:42:00.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:42:00.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:42:00.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:42:00.33#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:42:00.33#ibcon#first serial, iclass 37, count 0 2006.189.07:42:00.33#ibcon#enter sib2, iclass 37, count 0 2006.189.07:42:00.33#ibcon#flushed, iclass 37, count 0 2006.189.07:42:00.33#ibcon#about to write, iclass 37, count 0 2006.189.07:42:00.33#ibcon#wrote, iclass 37, count 0 2006.189.07:42:00.33#ibcon#about to read 3, iclass 37, count 0 2006.189.07:42:00.35#ibcon#read 3, iclass 37, count 0 2006.189.07:42:00.35#ibcon#about to read 4, iclass 37, count 0 2006.189.07:42:00.35#ibcon#read 4, iclass 37, count 0 2006.189.07:42:00.35#ibcon#about to read 5, iclass 37, count 0 2006.189.07:42:00.35#ibcon#read 5, iclass 37, count 0 2006.189.07:42:00.35#ibcon#about to read 6, iclass 37, count 0 2006.189.07:42:00.35#ibcon#read 6, iclass 37, count 0 2006.189.07:42:00.35#ibcon#end of sib2, iclass 37, count 0 2006.189.07:42:00.35#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:42:00.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:42:00.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:42:00.35#ibcon#*before write, iclass 37, count 0 2006.189.07:42:00.35#ibcon#enter sib2, iclass 37, count 0 2006.189.07:42:00.35#ibcon#flushed, iclass 37, count 0 2006.189.07:42:00.35#ibcon#about to write, iclass 37, count 0 2006.189.07:42:00.35#ibcon#wrote, iclass 37, count 0 2006.189.07:42:00.35#ibcon#about to read 3, iclass 37, count 0 2006.189.07:42:00.39#ibcon#read 3, iclass 37, count 0 2006.189.07:42:00.39#ibcon#about to read 4, iclass 37, count 0 2006.189.07:42:00.39#ibcon#read 4, iclass 37, count 0 2006.189.07:42:00.39#ibcon#about to read 5, iclass 37, count 0 2006.189.07:42:00.39#ibcon#read 5, iclass 37, count 0 2006.189.07:42:00.39#ibcon#about to read 6, iclass 37, count 0 2006.189.07:42:00.39#ibcon#read 6, iclass 37, count 0 2006.189.07:42:00.39#ibcon#end of sib2, iclass 37, count 0 2006.189.07:42:00.39#ibcon#*after write, iclass 37, count 0 2006.189.07:42:00.39#ibcon#*before return 0, iclass 37, count 0 2006.189.07:42:00.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:42:00.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:42:00.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:42:00.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:42:00.39$vc4f8/va=8,6 2006.189.07:42:00.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:42:00.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:42:00.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:00.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:42:00.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:42:00.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:42:00.46#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:42:00.46#ibcon#first serial, iclass 39, count 2 2006.189.07:42:00.46#ibcon#enter sib2, iclass 39, count 2 2006.189.07:42:00.46#ibcon#flushed, iclass 39, count 2 2006.189.07:42:00.46#ibcon#about to write, iclass 39, count 2 2006.189.07:42:00.46#ibcon#wrote, iclass 39, count 2 2006.189.07:42:00.46#ibcon#about to read 3, iclass 39, count 2 2006.189.07:42:00.47#ibcon#read 3, iclass 39, count 2 2006.189.07:42:00.47#ibcon#about to read 4, iclass 39, count 2 2006.189.07:42:00.47#ibcon#read 4, iclass 39, count 2 2006.189.07:42:00.47#ibcon#about to read 5, iclass 39, count 2 2006.189.07:42:00.47#ibcon#read 5, iclass 39, count 2 2006.189.07:42:00.47#ibcon#about to read 6, iclass 39, count 2 2006.189.07:42:00.47#ibcon#read 6, iclass 39, count 2 2006.189.07:42:00.47#ibcon#end of sib2, iclass 39, count 2 2006.189.07:42:00.47#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:42:00.47#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:42:00.47#ibcon#[25=AT08-06\r\n] 2006.189.07:42:00.47#ibcon#*before write, iclass 39, count 2 2006.189.07:42:00.47#ibcon#enter sib2, iclass 39, count 2 2006.189.07:42:00.47#ibcon#flushed, iclass 39, count 2 2006.189.07:42:00.47#ibcon#about to write, iclass 39, count 2 2006.189.07:42:00.47#ibcon#wrote, iclass 39, count 2 2006.189.07:42:00.47#ibcon#about to read 3, iclass 39, count 2 2006.189.07:42:00.50#ibcon#read 3, iclass 39, count 2 2006.189.07:42:00.50#ibcon#about to read 4, iclass 39, count 2 2006.189.07:42:00.50#ibcon#read 4, iclass 39, count 2 2006.189.07:42:00.50#ibcon#about to read 5, iclass 39, count 2 2006.189.07:42:00.50#ibcon#read 5, iclass 39, count 2 2006.189.07:42:00.50#ibcon#about to read 6, iclass 39, count 2 2006.189.07:42:00.50#ibcon#read 6, iclass 39, count 2 2006.189.07:42:00.50#ibcon#end of sib2, iclass 39, count 2 2006.189.07:42:00.50#ibcon#*after write, iclass 39, count 2 2006.189.07:42:00.50#ibcon#*before return 0, iclass 39, count 2 2006.189.07:42:00.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:42:00.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:42:00.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:42:00.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:00.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:42:00.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:42:00.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:42:00.62#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:42:00.62#ibcon#first serial, iclass 39, count 0 2006.189.07:42:00.62#ibcon#enter sib2, iclass 39, count 0 2006.189.07:42:00.62#ibcon#flushed, iclass 39, count 0 2006.189.07:42:00.62#ibcon#about to write, iclass 39, count 0 2006.189.07:42:00.62#ibcon#wrote, iclass 39, count 0 2006.189.07:42:00.62#ibcon#about to read 3, iclass 39, count 0 2006.189.07:42:00.64#ibcon#read 3, iclass 39, count 0 2006.189.07:42:00.64#ibcon#about to read 4, iclass 39, count 0 2006.189.07:42:00.64#ibcon#read 4, iclass 39, count 0 2006.189.07:42:00.64#ibcon#about to read 5, iclass 39, count 0 2006.189.07:42:00.64#ibcon#read 5, iclass 39, count 0 2006.189.07:42:00.64#ibcon#about to read 6, iclass 39, count 0 2006.189.07:42:00.64#ibcon#read 6, iclass 39, count 0 2006.189.07:42:00.64#ibcon#end of sib2, iclass 39, count 0 2006.189.07:42:00.64#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:42:00.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:42:00.64#ibcon#[25=USB\r\n] 2006.189.07:42:00.64#ibcon#*before write, iclass 39, count 0 2006.189.07:42:00.64#ibcon#enter sib2, iclass 39, count 0 2006.189.07:42:00.64#ibcon#flushed, iclass 39, count 0 2006.189.07:42:00.64#ibcon#about to write, iclass 39, count 0 2006.189.07:42:00.64#ibcon#wrote, iclass 39, count 0 2006.189.07:42:00.64#ibcon#about to read 3, iclass 39, count 0 2006.189.07:42:00.67#ibcon#read 3, iclass 39, count 0 2006.189.07:42:00.67#ibcon#about to read 4, iclass 39, count 0 2006.189.07:42:00.67#ibcon#read 4, iclass 39, count 0 2006.189.07:42:00.67#ibcon#about to read 5, iclass 39, count 0 2006.189.07:42:00.67#ibcon#read 5, iclass 39, count 0 2006.189.07:42:00.67#ibcon#about to read 6, iclass 39, count 0 2006.189.07:42:00.67#ibcon#read 6, iclass 39, count 0 2006.189.07:42:00.67#ibcon#end of sib2, iclass 39, count 0 2006.189.07:42:00.67#ibcon#*after write, iclass 39, count 0 2006.189.07:42:00.67#ibcon#*before return 0, iclass 39, count 0 2006.189.07:42:00.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:42:00.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:42:00.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:42:00.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:42:00.67$vc4f8/vblo=1,632.99 2006.189.07:42:00.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:42:00.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:42:00.67#ibcon#ireg 17 cls_cnt 0 2006.189.07:42:00.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:42:00.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:42:00.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:42:00.67#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:42:00.67#ibcon#first serial, iclass 3, count 0 2006.189.07:42:00.67#ibcon#enter sib2, iclass 3, count 0 2006.189.07:42:00.67#ibcon#flushed, iclass 3, count 0 2006.189.07:42:00.67#ibcon#about to write, iclass 3, count 0 2006.189.07:42:00.67#ibcon#wrote, iclass 3, count 0 2006.189.07:42:00.67#ibcon#about to read 3, iclass 3, count 0 2006.189.07:42:00.69#ibcon#read 3, iclass 3, count 0 2006.189.07:42:00.69#ibcon#about to read 4, iclass 3, count 0 2006.189.07:42:00.69#ibcon#read 4, iclass 3, count 0 2006.189.07:42:00.69#ibcon#about to read 5, iclass 3, count 0 2006.189.07:42:00.69#ibcon#read 5, iclass 3, count 0 2006.189.07:42:00.69#ibcon#about to read 6, iclass 3, count 0 2006.189.07:42:00.69#ibcon#read 6, iclass 3, count 0 2006.189.07:42:00.69#ibcon#end of sib2, iclass 3, count 0 2006.189.07:42:00.69#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:42:00.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:42:00.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:42:00.69#ibcon#*before write, iclass 3, count 0 2006.189.07:42:00.69#ibcon#enter sib2, iclass 3, count 0 2006.189.07:42:00.69#ibcon#flushed, iclass 3, count 0 2006.189.07:42:00.69#ibcon#about to write, iclass 3, count 0 2006.189.07:42:00.69#ibcon#wrote, iclass 3, count 0 2006.189.07:42:00.69#ibcon#about to read 3, iclass 3, count 0 2006.189.07:42:00.73#ibcon#read 3, iclass 3, count 0 2006.189.07:42:00.73#ibcon#about to read 4, iclass 3, count 0 2006.189.07:42:00.73#ibcon#read 4, iclass 3, count 0 2006.189.07:42:00.73#ibcon#about to read 5, iclass 3, count 0 2006.189.07:42:00.73#ibcon#read 5, iclass 3, count 0 2006.189.07:42:00.73#ibcon#about to read 6, iclass 3, count 0 2006.189.07:42:00.73#ibcon#read 6, iclass 3, count 0 2006.189.07:42:00.73#ibcon#end of sib2, iclass 3, count 0 2006.189.07:42:00.73#ibcon#*after write, iclass 3, count 0 2006.189.07:42:00.73#ibcon#*before return 0, iclass 3, count 0 2006.189.07:42:00.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:42:00.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:42:00.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:42:00.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:42:00.73$vc4f8/vb=1,4 2006.189.07:42:00.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:42:00.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:42:00.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:00.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:42:00.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:42:00.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:42:00.73#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:42:00.73#ibcon#first serial, iclass 5, count 2 2006.189.07:42:00.73#ibcon#enter sib2, iclass 5, count 2 2006.189.07:42:00.73#ibcon#flushed, iclass 5, count 2 2006.189.07:42:00.73#ibcon#about to write, iclass 5, count 2 2006.189.07:42:00.73#ibcon#wrote, iclass 5, count 2 2006.189.07:42:00.73#ibcon#about to read 3, iclass 5, count 2 2006.189.07:42:00.75#ibcon#read 3, iclass 5, count 2 2006.189.07:42:00.75#ibcon#about to read 4, iclass 5, count 2 2006.189.07:42:00.75#ibcon#read 4, iclass 5, count 2 2006.189.07:42:00.75#ibcon#about to read 5, iclass 5, count 2 2006.189.07:42:00.75#ibcon#read 5, iclass 5, count 2 2006.189.07:42:00.75#ibcon#about to read 6, iclass 5, count 2 2006.189.07:42:00.75#ibcon#read 6, iclass 5, count 2 2006.189.07:42:00.75#ibcon#end of sib2, iclass 5, count 2 2006.189.07:42:00.75#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:42:00.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:42:00.75#ibcon#[27=AT01-04\r\n] 2006.189.07:42:00.75#ibcon#*before write, iclass 5, count 2 2006.189.07:42:00.75#ibcon#enter sib2, iclass 5, count 2 2006.189.07:42:00.75#ibcon#flushed, iclass 5, count 2 2006.189.07:42:00.75#ibcon#about to write, iclass 5, count 2 2006.189.07:42:00.75#ibcon#wrote, iclass 5, count 2 2006.189.07:42:00.75#ibcon#about to read 3, iclass 5, count 2 2006.189.07:42:00.78#ibcon#read 3, iclass 5, count 2 2006.189.07:42:00.78#ibcon#about to read 4, iclass 5, count 2 2006.189.07:42:00.78#ibcon#read 4, iclass 5, count 2 2006.189.07:42:00.78#ibcon#about to read 5, iclass 5, count 2 2006.189.07:42:00.78#ibcon#read 5, iclass 5, count 2 2006.189.07:42:00.78#ibcon#about to read 6, iclass 5, count 2 2006.189.07:42:00.78#ibcon#read 6, iclass 5, count 2 2006.189.07:42:00.78#ibcon#end of sib2, iclass 5, count 2 2006.189.07:42:00.78#ibcon#*after write, iclass 5, count 2 2006.189.07:42:00.78#ibcon#*before return 0, iclass 5, count 2 2006.189.07:42:00.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:42:00.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:42:00.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:42:00.78#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:00.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:42:00.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:42:00.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:42:00.90#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:42:00.90#ibcon#first serial, iclass 5, count 0 2006.189.07:42:00.90#ibcon#enter sib2, iclass 5, count 0 2006.189.07:42:00.90#ibcon#flushed, iclass 5, count 0 2006.189.07:42:00.90#ibcon#about to write, iclass 5, count 0 2006.189.07:42:00.90#ibcon#wrote, iclass 5, count 0 2006.189.07:42:00.90#ibcon#about to read 3, iclass 5, count 0 2006.189.07:42:00.92#ibcon#read 3, iclass 5, count 0 2006.189.07:42:00.92#ibcon#about to read 4, iclass 5, count 0 2006.189.07:42:00.92#ibcon#read 4, iclass 5, count 0 2006.189.07:42:00.92#ibcon#about to read 5, iclass 5, count 0 2006.189.07:42:00.92#ibcon#read 5, iclass 5, count 0 2006.189.07:42:00.92#ibcon#about to read 6, iclass 5, count 0 2006.189.07:42:00.92#ibcon#read 6, iclass 5, count 0 2006.189.07:42:00.92#ibcon#end of sib2, iclass 5, count 0 2006.189.07:42:00.92#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:42:00.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:42:00.92#ibcon#[27=USB\r\n] 2006.189.07:42:00.92#ibcon#*before write, iclass 5, count 0 2006.189.07:42:00.92#ibcon#enter sib2, iclass 5, count 0 2006.189.07:42:00.92#ibcon#flushed, iclass 5, count 0 2006.189.07:42:00.92#ibcon#about to write, iclass 5, count 0 2006.189.07:42:00.92#ibcon#wrote, iclass 5, count 0 2006.189.07:42:00.92#ibcon#about to read 3, iclass 5, count 0 2006.189.07:42:00.95#ibcon#read 3, iclass 5, count 0 2006.189.07:42:00.95#ibcon#about to read 4, iclass 5, count 0 2006.189.07:42:00.95#ibcon#read 4, iclass 5, count 0 2006.189.07:42:00.95#ibcon#about to read 5, iclass 5, count 0 2006.189.07:42:00.95#ibcon#read 5, iclass 5, count 0 2006.189.07:42:00.95#ibcon#about to read 6, iclass 5, count 0 2006.189.07:42:00.95#ibcon#read 6, iclass 5, count 0 2006.189.07:42:00.95#ibcon#end of sib2, iclass 5, count 0 2006.189.07:42:00.95#ibcon#*after write, iclass 5, count 0 2006.189.07:42:00.95#ibcon#*before return 0, iclass 5, count 0 2006.189.07:42:00.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:42:00.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:42:00.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:42:00.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:42:00.95$vc4f8/vblo=2,640.99 2006.189.07:42:00.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:42:00.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:42:00.95#ibcon#ireg 17 cls_cnt 0 2006.189.07:42:00.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:42:00.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:42:00.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:42:00.95#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:42:00.95#ibcon#first serial, iclass 7, count 0 2006.189.07:42:00.95#ibcon#enter sib2, iclass 7, count 0 2006.189.07:42:00.95#ibcon#flushed, iclass 7, count 0 2006.189.07:42:00.95#ibcon#about to write, iclass 7, count 0 2006.189.07:42:00.95#ibcon#wrote, iclass 7, count 0 2006.189.07:42:00.95#ibcon#about to read 3, iclass 7, count 0 2006.189.07:42:00.97#ibcon#read 3, iclass 7, count 0 2006.189.07:42:00.97#ibcon#about to read 4, iclass 7, count 0 2006.189.07:42:00.97#ibcon#read 4, iclass 7, count 0 2006.189.07:42:00.97#ibcon#about to read 5, iclass 7, count 0 2006.189.07:42:00.97#ibcon#read 5, iclass 7, count 0 2006.189.07:42:00.97#ibcon#about to read 6, iclass 7, count 0 2006.189.07:42:00.97#ibcon#read 6, iclass 7, count 0 2006.189.07:42:00.97#ibcon#end of sib2, iclass 7, count 0 2006.189.07:42:00.97#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:42:00.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:42:00.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:42:00.97#ibcon#*before write, iclass 7, count 0 2006.189.07:42:00.97#ibcon#enter sib2, iclass 7, count 0 2006.189.07:42:00.97#ibcon#flushed, iclass 7, count 0 2006.189.07:42:00.97#ibcon#about to write, iclass 7, count 0 2006.189.07:42:00.97#ibcon#wrote, iclass 7, count 0 2006.189.07:42:00.97#ibcon#about to read 3, iclass 7, count 0 2006.189.07:42:01.01#ibcon#read 3, iclass 7, count 0 2006.189.07:42:01.01#ibcon#about to read 4, iclass 7, count 0 2006.189.07:42:01.01#ibcon#read 4, iclass 7, count 0 2006.189.07:42:01.01#ibcon#about to read 5, iclass 7, count 0 2006.189.07:42:01.01#ibcon#read 5, iclass 7, count 0 2006.189.07:42:01.01#ibcon#about to read 6, iclass 7, count 0 2006.189.07:42:01.01#ibcon#read 6, iclass 7, count 0 2006.189.07:42:01.01#ibcon#end of sib2, iclass 7, count 0 2006.189.07:42:01.01#ibcon#*after write, iclass 7, count 0 2006.189.07:42:01.01#ibcon#*before return 0, iclass 7, count 0 2006.189.07:42:01.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:42:01.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:42:01.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:42:01.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:42:01.01$vc4f8/vb=2,4 2006.189.07:42:01.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:42:01.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:42:01.01#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:01.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:42:01.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:42:01.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:42:01.07#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:42:01.07#ibcon#first serial, iclass 11, count 2 2006.189.07:42:01.07#ibcon#enter sib2, iclass 11, count 2 2006.189.07:42:01.07#ibcon#flushed, iclass 11, count 2 2006.189.07:42:01.07#ibcon#about to write, iclass 11, count 2 2006.189.07:42:01.07#ibcon#wrote, iclass 11, count 2 2006.189.07:42:01.07#ibcon#about to read 3, iclass 11, count 2 2006.189.07:42:01.09#ibcon#read 3, iclass 11, count 2 2006.189.07:42:01.09#ibcon#about to read 4, iclass 11, count 2 2006.189.07:42:01.09#ibcon#read 4, iclass 11, count 2 2006.189.07:42:01.09#ibcon#about to read 5, iclass 11, count 2 2006.189.07:42:01.09#ibcon#read 5, iclass 11, count 2 2006.189.07:42:01.09#ibcon#about to read 6, iclass 11, count 2 2006.189.07:42:01.09#ibcon#read 6, iclass 11, count 2 2006.189.07:42:01.09#ibcon#end of sib2, iclass 11, count 2 2006.189.07:42:01.09#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:42:01.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:42:01.09#ibcon#[27=AT02-04\r\n] 2006.189.07:42:01.09#ibcon#*before write, iclass 11, count 2 2006.189.07:42:01.09#ibcon#enter sib2, iclass 11, count 2 2006.189.07:42:01.09#ibcon#flushed, iclass 11, count 2 2006.189.07:42:01.09#ibcon#about to write, iclass 11, count 2 2006.189.07:42:01.09#ibcon#wrote, iclass 11, count 2 2006.189.07:42:01.09#ibcon#about to read 3, iclass 11, count 2 2006.189.07:42:01.12#ibcon#read 3, iclass 11, count 2 2006.189.07:42:01.12#ibcon#about to read 4, iclass 11, count 2 2006.189.07:42:01.12#ibcon#read 4, iclass 11, count 2 2006.189.07:42:01.12#ibcon#about to read 5, iclass 11, count 2 2006.189.07:42:01.12#ibcon#read 5, iclass 11, count 2 2006.189.07:42:01.12#ibcon#about to read 6, iclass 11, count 2 2006.189.07:42:01.12#ibcon#read 6, iclass 11, count 2 2006.189.07:42:01.12#ibcon#end of sib2, iclass 11, count 2 2006.189.07:42:01.12#ibcon#*after write, iclass 11, count 2 2006.189.07:42:01.12#ibcon#*before return 0, iclass 11, count 2 2006.189.07:42:01.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:42:01.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:42:01.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:42:01.12#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:01.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:42:01.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:42:01.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:42:01.24#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:42:01.24#ibcon#first serial, iclass 11, count 0 2006.189.07:42:01.24#ibcon#enter sib2, iclass 11, count 0 2006.189.07:42:01.24#ibcon#flushed, iclass 11, count 0 2006.189.07:42:01.24#ibcon#about to write, iclass 11, count 0 2006.189.07:42:01.24#ibcon#wrote, iclass 11, count 0 2006.189.07:42:01.24#ibcon#about to read 3, iclass 11, count 0 2006.189.07:42:01.26#ibcon#read 3, iclass 11, count 0 2006.189.07:42:01.26#ibcon#about to read 4, iclass 11, count 0 2006.189.07:42:01.26#ibcon#read 4, iclass 11, count 0 2006.189.07:42:01.26#ibcon#about to read 5, iclass 11, count 0 2006.189.07:42:01.26#ibcon#read 5, iclass 11, count 0 2006.189.07:42:01.26#ibcon#about to read 6, iclass 11, count 0 2006.189.07:42:01.26#ibcon#read 6, iclass 11, count 0 2006.189.07:42:01.26#ibcon#end of sib2, iclass 11, count 0 2006.189.07:42:01.26#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:42:01.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:42:01.26#ibcon#[27=USB\r\n] 2006.189.07:42:01.26#ibcon#*before write, iclass 11, count 0 2006.189.07:42:01.26#ibcon#enter sib2, iclass 11, count 0 2006.189.07:42:01.26#ibcon#flushed, iclass 11, count 0 2006.189.07:42:01.26#ibcon#about to write, iclass 11, count 0 2006.189.07:42:01.26#ibcon#wrote, iclass 11, count 0 2006.189.07:42:01.26#ibcon#about to read 3, iclass 11, count 0 2006.189.07:42:01.29#ibcon#read 3, iclass 11, count 0 2006.189.07:42:01.29#ibcon#about to read 4, iclass 11, count 0 2006.189.07:42:01.29#ibcon#read 4, iclass 11, count 0 2006.189.07:42:01.29#ibcon#about to read 5, iclass 11, count 0 2006.189.07:42:01.29#ibcon#read 5, iclass 11, count 0 2006.189.07:42:01.29#ibcon#about to read 6, iclass 11, count 0 2006.189.07:42:01.29#ibcon#read 6, iclass 11, count 0 2006.189.07:42:01.29#ibcon#end of sib2, iclass 11, count 0 2006.189.07:42:01.29#ibcon#*after write, iclass 11, count 0 2006.189.07:42:01.29#ibcon#*before return 0, iclass 11, count 0 2006.189.07:42:01.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:42:01.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:42:01.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:42:01.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:42:01.29$vc4f8/vblo=3,656.99 2006.189.07:42:01.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.07:42:01.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.07:42:01.29#ibcon#ireg 17 cls_cnt 0 2006.189.07:42:01.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:42:01.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:42:01.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:42:01.29#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:42:01.29#ibcon#first serial, iclass 13, count 0 2006.189.07:42:01.29#ibcon#enter sib2, iclass 13, count 0 2006.189.07:42:01.29#ibcon#flushed, iclass 13, count 0 2006.189.07:42:01.29#ibcon#about to write, iclass 13, count 0 2006.189.07:42:01.29#ibcon#wrote, iclass 13, count 0 2006.189.07:42:01.29#ibcon#about to read 3, iclass 13, count 0 2006.189.07:42:01.31#ibcon#read 3, iclass 13, count 0 2006.189.07:42:01.31#ibcon#about to read 4, iclass 13, count 0 2006.189.07:42:01.31#ibcon#read 4, iclass 13, count 0 2006.189.07:42:01.31#ibcon#about to read 5, iclass 13, count 0 2006.189.07:42:01.31#ibcon#read 5, iclass 13, count 0 2006.189.07:42:01.31#ibcon#about to read 6, iclass 13, count 0 2006.189.07:42:01.31#ibcon#read 6, iclass 13, count 0 2006.189.07:42:01.31#ibcon#end of sib2, iclass 13, count 0 2006.189.07:42:01.31#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:42:01.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:42:01.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:42:01.31#ibcon#*before write, iclass 13, count 0 2006.189.07:42:01.31#ibcon#enter sib2, iclass 13, count 0 2006.189.07:42:01.31#ibcon#flushed, iclass 13, count 0 2006.189.07:42:01.31#ibcon#about to write, iclass 13, count 0 2006.189.07:42:01.31#ibcon#wrote, iclass 13, count 0 2006.189.07:42:01.31#ibcon#about to read 3, iclass 13, count 0 2006.189.07:42:01.35#ibcon#read 3, iclass 13, count 0 2006.189.07:42:01.35#ibcon#about to read 4, iclass 13, count 0 2006.189.07:42:01.35#ibcon#read 4, iclass 13, count 0 2006.189.07:42:01.35#ibcon#about to read 5, iclass 13, count 0 2006.189.07:42:01.35#ibcon#read 5, iclass 13, count 0 2006.189.07:42:01.35#ibcon#about to read 6, iclass 13, count 0 2006.189.07:42:01.35#ibcon#read 6, iclass 13, count 0 2006.189.07:42:01.35#ibcon#end of sib2, iclass 13, count 0 2006.189.07:42:01.35#ibcon#*after write, iclass 13, count 0 2006.189.07:42:01.35#ibcon#*before return 0, iclass 13, count 0 2006.189.07:42:01.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:42:01.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:42:01.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:42:01.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:42:01.35$vc4f8/vb=3,4 2006.189.07:42:01.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.07:42:01.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.07:42:01.35#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:01.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:42:01.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:42:01.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:42:01.41#ibcon#enter wrdev, iclass 15, count 2 2006.189.07:42:01.41#ibcon#first serial, iclass 15, count 2 2006.189.07:42:01.41#ibcon#enter sib2, iclass 15, count 2 2006.189.07:42:01.41#ibcon#flushed, iclass 15, count 2 2006.189.07:42:01.41#ibcon#about to write, iclass 15, count 2 2006.189.07:42:01.41#ibcon#wrote, iclass 15, count 2 2006.189.07:42:01.41#ibcon#about to read 3, iclass 15, count 2 2006.189.07:42:01.43#ibcon#read 3, iclass 15, count 2 2006.189.07:42:01.43#ibcon#about to read 4, iclass 15, count 2 2006.189.07:42:01.43#ibcon#read 4, iclass 15, count 2 2006.189.07:42:01.43#ibcon#about to read 5, iclass 15, count 2 2006.189.07:42:01.43#ibcon#read 5, iclass 15, count 2 2006.189.07:42:01.43#ibcon#about to read 6, iclass 15, count 2 2006.189.07:42:01.43#ibcon#read 6, iclass 15, count 2 2006.189.07:42:01.43#ibcon#end of sib2, iclass 15, count 2 2006.189.07:42:01.43#ibcon#*mode == 0, iclass 15, count 2 2006.189.07:42:01.43#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.07:42:01.43#ibcon#[27=AT03-04\r\n] 2006.189.07:42:01.43#ibcon#*before write, iclass 15, count 2 2006.189.07:42:01.43#ibcon#enter sib2, iclass 15, count 2 2006.189.07:42:01.43#ibcon#flushed, iclass 15, count 2 2006.189.07:42:01.43#ibcon#about to write, iclass 15, count 2 2006.189.07:42:01.43#ibcon#wrote, iclass 15, count 2 2006.189.07:42:01.43#ibcon#about to read 3, iclass 15, count 2 2006.189.07:42:01.46#ibcon#read 3, iclass 15, count 2 2006.189.07:42:01.46#ibcon#about to read 4, iclass 15, count 2 2006.189.07:42:01.46#ibcon#read 4, iclass 15, count 2 2006.189.07:42:01.46#ibcon#about to read 5, iclass 15, count 2 2006.189.07:42:01.46#ibcon#read 5, iclass 15, count 2 2006.189.07:42:01.46#ibcon#about to read 6, iclass 15, count 2 2006.189.07:42:01.46#ibcon#read 6, iclass 15, count 2 2006.189.07:42:01.46#ibcon#end of sib2, iclass 15, count 2 2006.189.07:42:01.46#ibcon#*after write, iclass 15, count 2 2006.189.07:42:01.46#ibcon#*before return 0, iclass 15, count 2 2006.189.07:42:01.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:42:01.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:42:01.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.07:42:01.46#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:01.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:42:01.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:42:01.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:42:01.58#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:42:01.58#ibcon#first serial, iclass 15, count 0 2006.189.07:42:01.58#ibcon#enter sib2, iclass 15, count 0 2006.189.07:42:01.58#ibcon#flushed, iclass 15, count 0 2006.189.07:42:01.58#ibcon#about to write, iclass 15, count 0 2006.189.07:42:01.58#ibcon#wrote, iclass 15, count 0 2006.189.07:42:01.58#ibcon#about to read 3, iclass 15, count 0 2006.189.07:42:01.60#ibcon#read 3, iclass 15, count 0 2006.189.07:42:01.60#ibcon#about to read 4, iclass 15, count 0 2006.189.07:42:01.60#ibcon#read 4, iclass 15, count 0 2006.189.07:42:01.60#ibcon#about to read 5, iclass 15, count 0 2006.189.07:42:01.60#ibcon#read 5, iclass 15, count 0 2006.189.07:42:01.60#ibcon#about to read 6, iclass 15, count 0 2006.189.07:42:01.60#ibcon#read 6, iclass 15, count 0 2006.189.07:42:01.60#ibcon#end of sib2, iclass 15, count 0 2006.189.07:42:01.60#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:42:01.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:42:01.60#ibcon#[27=USB\r\n] 2006.189.07:42:01.60#ibcon#*before write, iclass 15, count 0 2006.189.07:42:01.60#ibcon#enter sib2, iclass 15, count 0 2006.189.07:42:01.60#ibcon#flushed, iclass 15, count 0 2006.189.07:42:01.60#ibcon#about to write, iclass 15, count 0 2006.189.07:42:01.60#ibcon#wrote, iclass 15, count 0 2006.189.07:42:01.60#ibcon#about to read 3, iclass 15, count 0 2006.189.07:42:01.63#ibcon#read 3, iclass 15, count 0 2006.189.07:42:01.63#ibcon#about to read 4, iclass 15, count 0 2006.189.07:42:01.63#ibcon#read 4, iclass 15, count 0 2006.189.07:42:01.63#ibcon#about to read 5, iclass 15, count 0 2006.189.07:42:01.63#ibcon#read 5, iclass 15, count 0 2006.189.07:42:01.63#ibcon#about to read 6, iclass 15, count 0 2006.189.07:42:01.63#ibcon#read 6, iclass 15, count 0 2006.189.07:42:01.63#ibcon#end of sib2, iclass 15, count 0 2006.189.07:42:01.63#ibcon#*after write, iclass 15, count 0 2006.189.07:42:01.63#ibcon#*before return 0, iclass 15, count 0 2006.189.07:42:01.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:42:01.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:42:01.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:42:01.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:42:01.63$vc4f8/vblo=4,712.99 2006.189.07:42:01.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:42:01.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:42:01.63#ibcon#ireg 17 cls_cnt 0 2006.189.07:42:01.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:42:01.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:42:01.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:42:01.63#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:42:01.63#ibcon#first serial, iclass 17, count 0 2006.189.07:42:01.63#ibcon#enter sib2, iclass 17, count 0 2006.189.07:42:01.63#ibcon#flushed, iclass 17, count 0 2006.189.07:42:01.63#ibcon#about to write, iclass 17, count 0 2006.189.07:42:01.63#ibcon#wrote, iclass 17, count 0 2006.189.07:42:01.63#ibcon#about to read 3, iclass 17, count 0 2006.189.07:42:01.65#ibcon#read 3, iclass 17, count 0 2006.189.07:42:01.65#ibcon#about to read 4, iclass 17, count 0 2006.189.07:42:01.65#ibcon#read 4, iclass 17, count 0 2006.189.07:42:01.65#ibcon#about to read 5, iclass 17, count 0 2006.189.07:42:01.65#ibcon#read 5, iclass 17, count 0 2006.189.07:42:01.65#ibcon#about to read 6, iclass 17, count 0 2006.189.07:42:01.65#ibcon#read 6, iclass 17, count 0 2006.189.07:42:01.65#ibcon#end of sib2, iclass 17, count 0 2006.189.07:42:01.65#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:42:01.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:42:01.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:42:01.65#ibcon#*before write, iclass 17, count 0 2006.189.07:42:01.65#ibcon#enter sib2, iclass 17, count 0 2006.189.07:42:01.65#ibcon#flushed, iclass 17, count 0 2006.189.07:42:01.65#ibcon#about to write, iclass 17, count 0 2006.189.07:42:01.65#ibcon#wrote, iclass 17, count 0 2006.189.07:42:01.65#ibcon#about to read 3, iclass 17, count 0 2006.189.07:42:01.69#ibcon#read 3, iclass 17, count 0 2006.189.07:42:01.69#ibcon#about to read 4, iclass 17, count 0 2006.189.07:42:01.69#ibcon#read 4, iclass 17, count 0 2006.189.07:42:01.69#ibcon#about to read 5, iclass 17, count 0 2006.189.07:42:01.69#ibcon#read 5, iclass 17, count 0 2006.189.07:42:01.69#ibcon#about to read 6, iclass 17, count 0 2006.189.07:42:01.69#ibcon#read 6, iclass 17, count 0 2006.189.07:42:01.69#ibcon#end of sib2, iclass 17, count 0 2006.189.07:42:01.69#ibcon#*after write, iclass 17, count 0 2006.189.07:42:01.69#ibcon#*before return 0, iclass 17, count 0 2006.189.07:42:01.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:42:01.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:42:01.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:42:01.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:42:01.69$vc4f8/vb=4,4 2006.189.07:42:01.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.07:42:01.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.07:42:01.69#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:01.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:42:01.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:42:01.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:42:01.75#ibcon#enter wrdev, iclass 19, count 2 2006.189.07:42:01.75#ibcon#first serial, iclass 19, count 2 2006.189.07:42:01.75#ibcon#enter sib2, iclass 19, count 2 2006.189.07:42:01.75#ibcon#flushed, iclass 19, count 2 2006.189.07:42:01.75#ibcon#about to write, iclass 19, count 2 2006.189.07:42:01.75#ibcon#wrote, iclass 19, count 2 2006.189.07:42:01.75#ibcon#about to read 3, iclass 19, count 2 2006.189.07:42:01.77#ibcon#read 3, iclass 19, count 2 2006.189.07:42:01.77#ibcon#about to read 4, iclass 19, count 2 2006.189.07:42:01.77#ibcon#read 4, iclass 19, count 2 2006.189.07:42:01.77#ibcon#about to read 5, iclass 19, count 2 2006.189.07:42:01.77#ibcon#read 5, iclass 19, count 2 2006.189.07:42:01.77#ibcon#about to read 6, iclass 19, count 2 2006.189.07:42:01.77#ibcon#read 6, iclass 19, count 2 2006.189.07:42:01.77#ibcon#end of sib2, iclass 19, count 2 2006.189.07:42:01.77#ibcon#*mode == 0, iclass 19, count 2 2006.189.07:42:01.77#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.07:42:01.77#ibcon#[27=AT04-04\r\n] 2006.189.07:42:01.77#ibcon#*before write, iclass 19, count 2 2006.189.07:42:01.77#ibcon#enter sib2, iclass 19, count 2 2006.189.07:42:01.77#ibcon#flushed, iclass 19, count 2 2006.189.07:42:01.77#ibcon#about to write, iclass 19, count 2 2006.189.07:42:01.77#ibcon#wrote, iclass 19, count 2 2006.189.07:42:01.77#ibcon#about to read 3, iclass 19, count 2 2006.189.07:42:01.80#ibcon#read 3, iclass 19, count 2 2006.189.07:42:01.80#ibcon#about to read 4, iclass 19, count 2 2006.189.07:42:01.80#ibcon#read 4, iclass 19, count 2 2006.189.07:42:01.80#ibcon#about to read 5, iclass 19, count 2 2006.189.07:42:01.80#ibcon#read 5, iclass 19, count 2 2006.189.07:42:01.80#ibcon#about to read 6, iclass 19, count 2 2006.189.07:42:01.80#ibcon#read 6, iclass 19, count 2 2006.189.07:42:01.80#ibcon#end of sib2, iclass 19, count 2 2006.189.07:42:01.80#ibcon#*after write, iclass 19, count 2 2006.189.07:42:01.80#ibcon#*before return 0, iclass 19, count 2 2006.189.07:42:01.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:42:01.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:42:01.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.07:42:01.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:01.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:42:01.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:42:01.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:42:01.92#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:42:01.92#ibcon#first serial, iclass 19, count 0 2006.189.07:42:01.92#ibcon#enter sib2, iclass 19, count 0 2006.189.07:42:01.92#ibcon#flushed, iclass 19, count 0 2006.189.07:42:01.92#ibcon#about to write, iclass 19, count 0 2006.189.07:42:01.92#ibcon#wrote, iclass 19, count 0 2006.189.07:42:01.92#ibcon#about to read 3, iclass 19, count 0 2006.189.07:42:01.94#ibcon#read 3, iclass 19, count 0 2006.189.07:42:01.94#ibcon#about to read 4, iclass 19, count 0 2006.189.07:42:01.94#ibcon#read 4, iclass 19, count 0 2006.189.07:42:01.94#ibcon#about to read 5, iclass 19, count 0 2006.189.07:42:01.94#ibcon#read 5, iclass 19, count 0 2006.189.07:42:01.94#ibcon#about to read 6, iclass 19, count 0 2006.189.07:42:01.94#ibcon#read 6, iclass 19, count 0 2006.189.07:42:01.94#ibcon#end of sib2, iclass 19, count 0 2006.189.07:42:01.94#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:42:01.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:42:01.94#ibcon#[27=USB\r\n] 2006.189.07:42:01.94#ibcon#*before write, iclass 19, count 0 2006.189.07:42:01.94#ibcon#enter sib2, iclass 19, count 0 2006.189.07:42:01.94#ibcon#flushed, iclass 19, count 0 2006.189.07:42:01.94#ibcon#about to write, iclass 19, count 0 2006.189.07:42:01.94#ibcon#wrote, iclass 19, count 0 2006.189.07:42:01.94#ibcon#about to read 3, iclass 19, count 0 2006.189.07:42:01.97#ibcon#read 3, iclass 19, count 0 2006.189.07:42:01.97#ibcon#about to read 4, iclass 19, count 0 2006.189.07:42:01.97#ibcon#read 4, iclass 19, count 0 2006.189.07:42:01.97#ibcon#about to read 5, iclass 19, count 0 2006.189.07:42:01.97#ibcon#read 5, iclass 19, count 0 2006.189.07:42:01.97#ibcon#about to read 6, iclass 19, count 0 2006.189.07:42:01.97#ibcon#read 6, iclass 19, count 0 2006.189.07:42:01.97#ibcon#end of sib2, iclass 19, count 0 2006.189.07:42:01.97#ibcon#*after write, iclass 19, count 0 2006.189.07:42:01.97#ibcon#*before return 0, iclass 19, count 0 2006.189.07:42:01.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:42:01.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:42:01.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:42:01.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:42:01.97$vc4f8/vblo=5,744.99 2006.189.07:42:01.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:42:01.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:42:01.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:42:01.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:42:01.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:42:01.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:42:01.97#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:42:01.97#ibcon#first serial, iclass 21, count 0 2006.189.07:42:01.97#ibcon#enter sib2, iclass 21, count 0 2006.189.07:42:01.97#ibcon#flushed, iclass 21, count 0 2006.189.07:42:01.97#ibcon#about to write, iclass 21, count 0 2006.189.07:42:01.97#ibcon#wrote, iclass 21, count 0 2006.189.07:42:01.97#ibcon#about to read 3, iclass 21, count 0 2006.189.07:42:01.99#ibcon#read 3, iclass 21, count 0 2006.189.07:42:01.99#ibcon#about to read 4, iclass 21, count 0 2006.189.07:42:01.99#ibcon#read 4, iclass 21, count 0 2006.189.07:42:01.99#ibcon#about to read 5, iclass 21, count 0 2006.189.07:42:01.99#ibcon#read 5, iclass 21, count 0 2006.189.07:42:01.99#ibcon#about to read 6, iclass 21, count 0 2006.189.07:42:01.99#ibcon#read 6, iclass 21, count 0 2006.189.07:42:01.99#ibcon#end of sib2, iclass 21, count 0 2006.189.07:42:01.99#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:42:01.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:42:01.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:42:01.99#ibcon#*before write, iclass 21, count 0 2006.189.07:42:01.99#ibcon#enter sib2, iclass 21, count 0 2006.189.07:42:01.99#ibcon#flushed, iclass 21, count 0 2006.189.07:42:01.99#ibcon#about to write, iclass 21, count 0 2006.189.07:42:01.99#ibcon#wrote, iclass 21, count 0 2006.189.07:42:01.99#ibcon#about to read 3, iclass 21, count 0 2006.189.07:42:02.03#ibcon#read 3, iclass 21, count 0 2006.189.07:42:02.03#ibcon#about to read 4, iclass 21, count 0 2006.189.07:42:02.03#ibcon#read 4, iclass 21, count 0 2006.189.07:42:02.03#ibcon#about to read 5, iclass 21, count 0 2006.189.07:42:02.03#ibcon#read 5, iclass 21, count 0 2006.189.07:42:02.03#ibcon#about to read 6, iclass 21, count 0 2006.189.07:42:02.03#ibcon#read 6, iclass 21, count 0 2006.189.07:42:02.03#ibcon#end of sib2, iclass 21, count 0 2006.189.07:42:02.03#ibcon#*after write, iclass 21, count 0 2006.189.07:42:02.03#ibcon#*before return 0, iclass 21, count 0 2006.189.07:42:02.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:42:02.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:42:02.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:42:02.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:42:02.03$vc4f8/vb=5,4 2006.189.07:42:02.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:42:02.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:42:02.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:02.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:42:02.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:42:02.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:42:02.09#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:42:02.09#ibcon#first serial, iclass 23, count 2 2006.189.07:42:02.09#ibcon#enter sib2, iclass 23, count 2 2006.189.07:42:02.09#ibcon#flushed, iclass 23, count 2 2006.189.07:42:02.09#ibcon#about to write, iclass 23, count 2 2006.189.07:42:02.09#ibcon#wrote, iclass 23, count 2 2006.189.07:42:02.09#ibcon#about to read 3, iclass 23, count 2 2006.189.07:42:02.11#ibcon#read 3, iclass 23, count 2 2006.189.07:42:02.11#ibcon#about to read 4, iclass 23, count 2 2006.189.07:42:02.11#ibcon#read 4, iclass 23, count 2 2006.189.07:42:02.11#ibcon#about to read 5, iclass 23, count 2 2006.189.07:42:02.11#ibcon#read 5, iclass 23, count 2 2006.189.07:42:02.11#ibcon#about to read 6, iclass 23, count 2 2006.189.07:42:02.11#ibcon#read 6, iclass 23, count 2 2006.189.07:42:02.11#ibcon#end of sib2, iclass 23, count 2 2006.189.07:42:02.11#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:42:02.11#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:42:02.11#ibcon#[27=AT05-04\r\n] 2006.189.07:42:02.11#ibcon#*before write, iclass 23, count 2 2006.189.07:42:02.11#ibcon#enter sib2, iclass 23, count 2 2006.189.07:42:02.11#ibcon#flushed, iclass 23, count 2 2006.189.07:42:02.11#ibcon#about to write, iclass 23, count 2 2006.189.07:42:02.11#ibcon#wrote, iclass 23, count 2 2006.189.07:42:02.11#ibcon#about to read 3, iclass 23, count 2 2006.189.07:42:02.14#ibcon#read 3, iclass 23, count 2 2006.189.07:42:02.14#ibcon#about to read 4, iclass 23, count 2 2006.189.07:42:02.14#ibcon#read 4, iclass 23, count 2 2006.189.07:42:02.14#ibcon#about to read 5, iclass 23, count 2 2006.189.07:42:02.14#ibcon#read 5, iclass 23, count 2 2006.189.07:42:02.14#ibcon#about to read 6, iclass 23, count 2 2006.189.07:42:02.14#ibcon#read 6, iclass 23, count 2 2006.189.07:42:02.14#ibcon#end of sib2, iclass 23, count 2 2006.189.07:42:02.14#ibcon#*after write, iclass 23, count 2 2006.189.07:42:02.14#ibcon#*before return 0, iclass 23, count 2 2006.189.07:42:02.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:42:02.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:42:02.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:42:02.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:02.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:42:02.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:42:02.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:42:02.26#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:42:02.26#ibcon#first serial, iclass 23, count 0 2006.189.07:42:02.26#ibcon#enter sib2, iclass 23, count 0 2006.189.07:42:02.26#ibcon#flushed, iclass 23, count 0 2006.189.07:42:02.26#ibcon#about to write, iclass 23, count 0 2006.189.07:42:02.26#ibcon#wrote, iclass 23, count 0 2006.189.07:42:02.26#ibcon#about to read 3, iclass 23, count 0 2006.189.07:42:02.28#ibcon#read 3, iclass 23, count 0 2006.189.07:42:02.28#ibcon#about to read 4, iclass 23, count 0 2006.189.07:42:02.28#ibcon#read 4, iclass 23, count 0 2006.189.07:42:02.28#ibcon#about to read 5, iclass 23, count 0 2006.189.07:42:02.28#ibcon#read 5, iclass 23, count 0 2006.189.07:42:02.28#ibcon#about to read 6, iclass 23, count 0 2006.189.07:42:02.28#ibcon#read 6, iclass 23, count 0 2006.189.07:42:02.28#ibcon#end of sib2, iclass 23, count 0 2006.189.07:42:02.28#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:42:02.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:42:02.28#ibcon#[27=USB\r\n] 2006.189.07:42:02.28#ibcon#*before write, iclass 23, count 0 2006.189.07:42:02.28#ibcon#enter sib2, iclass 23, count 0 2006.189.07:42:02.28#ibcon#flushed, iclass 23, count 0 2006.189.07:42:02.28#ibcon#about to write, iclass 23, count 0 2006.189.07:42:02.28#ibcon#wrote, iclass 23, count 0 2006.189.07:42:02.28#ibcon#about to read 3, iclass 23, count 0 2006.189.07:42:02.31#ibcon#read 3, iclass 23, count 0 2006.189.07:42:02.31#ibcon#about to read 4, iclass 23, count 0 2006.189.07:42:02.31#ibcon#read 4, iclass 23, count 0 2006.189.07:42:02.31#ibcon#about to read 5, iclass 23, count 0 2006.189.07:42:02.31#ibcon#read 5, iclass 23, count 0 2006.189.07:42:02.31#ibcon#about to read 6, iclass 23, count 0 2006.189.07:42:02.31#ibcon#read 6, iclass 23, count 0 2006.189.07:42:02.31#ibcon#end of sib2, iclass 23, count 0 2006.189.07:42:02.31#ibcon#*after write, iclass 23, count 0 2006.189.07:42:02.31#ibcon#*before return 0, iclass 23, count 0 2006.189.07:42:02.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:42:02.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:42:02.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:42:02.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:42:02.31$vc4f8/vblo=6,752.99 2006.189.07:42:02.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:42:02.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:42:02.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:42:02.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:42:02.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:42:02.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:42:02.31#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:42:02.31#ibcon#first serial, iclass 25, count 0 2006.189.07:42:02.31#ibcon#enter sib2, iclass 25, count 0 2006.189.07:42:02.31#ibcon#flushed, iclass 25, count 0 2006.189.07:42:02.31#ibcon#about to write, iclass 25, count 0 2006.189.07:42:02.31#ibcon#wrote, iclass 25, count 0 2006.189.07:42:02.31#ibcon#about to read 3, iclass 25, count 0 2006.189.07:42:02.33#ibcon#read 3, iclass 25, count 0 2006.189.07:42:02.33#ibcon#about to read 4, iclass 25, count 0 2006.189.07:42:02.33#ibcon#read 4, iclass 25, count 0 2006.189.07:42:02.33#ibcon#about to read 5, iclass 25, count 0 2006.189.07:42:02.33#ibcon#read 5, iclass 25, count 0 2006.189.07:42:02.33#ibcon#about to read 6, iclass 25, count 0 2006.189.07:42:02.33#ibcon#read 6, iclass 25, count 0 2006.189.07:42:02.33#ibcon#end of sib2, iclass 25, count 0 2006.189.07:42:02.33#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:42:02.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:42:02.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:42:02.33#ibcon#*before write, iclass 25, count 0 2006.189.07:42:02.33#ibcon#enter sib2, iclass 25, count 0 2006.189.07:42:02.33#ibcon#flushed, iclass 25, count 0 2006.189.07:42:02.33#ibcon#about to write, iclass 25, count 0 2006.189.07:42:02.33#ibcon#wrote, iclass 25, count 0 2006.189.07:42:02.33#ibcon#about to read 3, iclass 25, count 0 2006.189.07:42:02.37#ibcon#read 3, iclass 25, count 0 2006.189.07:42:02.37#ibcon#about to read 4, iclass 25, count 0 2006.189.07:42:02.37#ibcon#read 4, iclass 25, count 0 2006.189.07:42:02.37#ibcon#about to read 5, iclass 25, count 0 2006.189.07:42:02.37#ibcon#read 5, iclass 25, count 0 2006.189.07:42:02.37#ibcon#about to read 6, iclass 25, count 0 2006.189.07:42:02.37#ibcon#read 6, iclass 25, count 0 2006.189.07:42:02.37#ibcon#end of sib2, iclass 25, count 0 2006.189.07:42:02.37#ibcon#*after write, iclass 25, count 0 2006.189.07:42:02.37#ibcon#*before return 0, iclass 25, count 0 2006.189.07:42:02.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:42:02.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:42:02.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:42:02.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:42:02.37$vc4f8/vb=6,4 2006.189.07:42:02.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:42:02.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:42:02.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:42:02.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:42:02.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:42:02.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:42:02.43#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:42:02.43#ibcon#first serial, iclass 27, count 2 2006.189.07:42:02.43#ibcon#enter sib2, iclass 27, count 2 2006.189.07:42:02.43#ibcon#flushed, iclass 27, count 2 2006.189.07:42:02.43#ibcon#about to write, iclass 27, count 2 2006.189.07:42:02.43#ibcon#wrote, iclass 27, count 2 2006.189.07:42:02.43#ibcon#about to read 3, iclass 27, count 2 2006.189.07:42:02.45#ibcon#read 3, iclass 27, count 2 2006.189.07:42:02.45#ibcon#about to read 4, iclass 27, count 2 2006.189.07:42:02.45#ibcon#read 4, iclass 27, count 2 2006.189.07:42:02.45#ibcon#about to read 5, iclass 27, count 2 2006.189.07:42:02.45#ibcon#read 5, iclass 27, count 2 2006.189.07:42:02.45#ibcon#about to read 6, iclass 27, count 2 2006.189.07:42:02.45#ibcon#read 6, iclass 27, count 2 2006.189.07:42:02.45#ibcon#end of sib2, iclass 27, count 2 2006.189.07:42:02.45#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:42:02.45#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:42:02.45#ibcon#[27=AT06-04\r\n] 2006.189.07:42:02.45#ibcon#*before write, iclass 27, count 2 2006.189.07:42:02.45#ibcon#enter sib2, iclass 27, count 2 2006.189.07:42:02.45#ibcon#flushed, iclass 27, count 2 2006.189.07:42:02.45#ibcon#about to write, iclass 27, count 2 2006.189.07:42:02.45#ibcon#wrote, iclass 27, count 2 2006.189.07:42:02.45#ibcon#about to read 3, iclass 27, count 2 2006.189.07:42:02.48#ibcon#read 3, iclass 27, count 2 2006.189.07:42:02.48#ibcon#about to read 4, iclass 27, count 2 2006.189.07:42:02.48#ibcon#read 4, iclass 27, count 2 2006.189.07:42:02.48#ibcon#about to read 5, iclass 27, count 2 2006.189.07:42:02.48#ibcon#read 5, iclass 27, count 2 2006.189.07:42:02.48#ibcon#about to read 6, iclass 27, count 2 2006.189.07:42:02.48#ibcon#read 6, iclass 27, count 2 2006.189.07:42:02.48#ibcon#end of sib2, iclass 27, count 2 2006.189.07:42:02.48#ibcon#*after write, iclass 27, count 2 2006.189.07:42:02.48#ibcon#*before return 0, iclass 27, count 2 2006.189.07:42:02.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:42:02.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:42:02.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:42:02.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:42:02.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:42:02.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:42:02.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:42:02.60#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:42:02.60#ibcon#first serial, iclass 27, count 0 2006.189.07:42:02.60#ibcon#enter sib2, iclass 27, count 0 2006.189.07:42:02.60#ibcon#flushed, iclass 27, count 0 2006.189.07:42:02.60#ibcon#about to write, iclass 27, count 0 2006.189.07:42:02.60#ibcon#wrote, iclass 27, count 0 2006.189.07:42:02.60#ibcon#about to read 3, iclass 27, count 0 2006.189.07:42:02.62#ibcon#read 3, iclass 27, count 0 2006.189.07:42:02.62#ibcon#about to read 4, iclass 27, count 0 2006.189.07:42:02.62#ibcon#read 4, iclass 27, count 0 2006.189.07:42:02.62#ibcon#about to read 5, iclass 27, count 0 2006.189.07:42:02.62#ibcon#read 5, iclass 27, count 0 2006.189.07:42:02.62#ibcon#about to read 6, iclass 27, count 0 2006.189.07:42:02.62#ibcon#read 6, iclass 27, count 0 2006.189.07:42:02.62#ibcon#end of sib2, iclass 27, count 0 2006.189.07:42:02.62#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:42:02.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:42:02.62#ibcon#[27=USB\r\n] 2006.189.07:42:02.62#ibcon#*before write, iclass 27, count 0 2006.189.07:42:02.62#ibcon#enter sib2, iclass 27, count 0 2006.189.07:42:02.62#ibcon#flushed, iclass 27, count 0 2006.189.07:42:02.62#ibcon#about to write, iclass 27, count 0 2006.189.07:42:02.62#ibcon#wrote, iclass 27, count 0 2006.189.07:42:02.62#ibcon#about to read 3, iclass 27, count 0 2006.189.07:42:02.65#ibcon#read 3, iclass 27, count 0 2006.189.07:42:02.65#ibcon#about to read 4, iclass 27, count 0 2006.189.07:42:02.65#ibcon#read 4, iclass 27, count 0 2006.189.07:42:02.65#ibcon#about to read 5, iclass 27, count 0 2006.189.07:42:02.65#ibcon#read 5, iclass 27, count 0 2006.189.07:42:02.65#ibcon#about to read 6, iclass 27, count 0 2006.189.07:42:02.65#ibcon#read 6, iclass 27, count 0 2006.189.07:42:02.65#ibcon#end of sib2, iclass 27, count 0 2006.189.07:42:02.65#ibcon#*after write, iclass 27, count 0 2006.189.07:42:02.65#ibcon#*before return 0, iclass 27, count 0 2006.189.07:42:02.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:42:02.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:42:02.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:42:02.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:42:02.65$vc4f8/vabw=wide 2006.189.07:42:02.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:42:02.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:42:02.65#ibcon#ireg 8 cls_cnt 0 2006.189.07:42:02.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:42:02.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:42:02.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:42:02.65#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:42:02.65#ibcon#first serial, iclass 29, count 0 2006.189.07:42:02.65#ibcon#enter sib2, iclass 29, count 0 2006.189.07:42:02.65#ibcon#flushed, iclass 29, count 0 2006.189.07:42:02.65#ibcon#about to write, iclass 29, count 0 2006.189.07:42:02.65#ibcon#wrote, iclass 29, count 0 2006.189.07:42:02.65#ibcon#about to read 3, iclass 29, count 0 2006.189.07:42:02.67#ibcon#read 3, iclass 29, count 0 2006.189.07:42:02.67#ibcon#about to read 4, iclass 29, count 0 2006.189.07:42:02.67#ibcon#read 4, iclass 29, count 0 2006.189.07:42:02.67#ibcon#about to read 5, iclass 29, count 0 2006.189.07:42:02.67#ibcon#read 5, iclass 29, count 0 2006.189.07:42:02.67#ibcon#about to read 6, iclass 29, count 0 2006.189.07:42:02.67#ibcon#read 6, iclass 29, count 0 2006.189.07:42:02.67#ibcon#end of sib2, iclass 29, count 0 2006.189.07:42:02.67#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:42:02.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:42:02.67#ibcon#[25=BW32\r\n] 2006.189.07:42:02.67#ibcon#*before write, iclass 29, count 0 2006.189.07:42:02.67#ibcon#enter sib2, iclass 29, count 0 2006.189.07:42:02.67#ibcon#flushed, iclass 29, count 0 2006.189.07:42:02.67#ibcon#about to write, iclass 29, count 0 2006.189.07:42:02.67#ibcon#wrote, iclass 29, count 0 2006.189.07:42:02.67#ibcon#about to read 3, iclass 29, count 0 2006.189.07:42:02.70#ibcon#read 3, iclass 29, count 0 2006.189.07:42:02.70#ibcon#about to read 4, iclass 29, count 0 2006.189.07:42:02.70#ibcon#read 4, iclass 29, count 0 2006.189.07:42:02.70#ibcon#about to read 5, iclass 29, count 0 2006.189.07:42:02.70#ibcon#read 5, iclass 29, count 0 2006.189.07:42:02.70#ibcon#about to read 6, iclass 29, count 0 2006.189.07:42:02.70#ibcon#read 6, iclass 29, count 0 2006.189.07:42:02.70#ibcon#end of sib2, iclass 29, count 0 2006.189.07:42:02.70#ibcon#*after write, iclass 29, count 0 2006.189.07:42:02.70#ibcon#*before return 0, iclass 29, count 0 2006.189.07:42:02.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:42:02.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:42:02.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:42:02.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:42:02.70$vc4f8/vbbw=wide 2006.189.07:42:02.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.07:42:02.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.07:42:02.70#ibcon#ireg 8 cls_cnt 0 2006.189.07:42:02.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:42:02.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:42:02.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:42:02.78#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:42:02.78#ibcon#first serial, iclass 31, count 0 2006.189.07:42:02.78#ibcon#enter sib2, iclass 31, count 0 2006.189.07:42:02.78#ibcon#flushed, iclass 31, count 0 2006.189.07:42:02.78#ibcon#about to write, iclass 31, count 0 2006.189.07:42:02.78#ibcon#wrote, iclass 31, count 0 2006.189.07:42:02.78#ibcon#about to read 3, iclass 31, count 0 2006.189.07:42:02.79#ibcon#read 3, iclass 31, count 0 2006.189.07:42:02.79#ibcon#about to read 4, iclass 31, count 0 2006.189.07:42:02.79#ibcon#read 4, iclass 31, count 0 2006.189.07:42:02.79#ibcon#about to read 5, iclass 31, count 0 2006.189.07:42:02.79#ibcon#read 5, iclass 31, count 0 2006.189.07:42:02.79#ibcon#about to read 6, iclass 31, count 0 2006.189.07:42:02.79#ibcon#read 6, iclass 31, count 0 2006.189.07:42:02.79#ibcon#end of sib2, iclass 31, count 0 2006.189.07:42:02.79#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:42:02.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:42:02.79#ibcon#[27=BW32\r\n] 2006.189.07:42:02.79#ibcon#*before write, iclass 31, count 0 2006.189.07:42:02.79#ibcon#enter sib2, iclass 31, count 0 2006.189.07:42:02.79#ibcon#flushed, iclass 31, count 0 2006.189.07:42:02.79#ibcon#about to write, iclass 31, count 0 2006.189.07:42:02.79#ibcon#wrote, iclass 31, count 0 2006.189.07:42:02.79#ibcon#about to read 3, iclass 31, count 0 2006.189.07:42:02.82#ibcon#read 3, iclass 31, count 0 2006.189.07:42:02.82#ibcon#about to read 4, iclass 31, count 0 2006.189.07:42:02.82#ibcon#read 4, iclass 31, count 0 2006.189.07:42:02.82#ibcon#about to read 5, iclass 31, count 0 2006.189.07:42:02.82#ibcon#read 5, iclass 31, count 0 2006.189.07:42:02.82#ibcon#about to read 6, iclass 31, count 0 2006.189.07:42:02.82#ibcon#read 6, iclass 31, count 0 2006.189.07:42:02.82#ibcon#end of sib2, iclass 31, count 0 2006.189.07:42:02.82#ibcon#*after write, iclass 31, count 0 2006.189.07:42:02.82#ibcon#*before return 0, iclass 31, count 0 2006.189.07:42:02.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:42:02.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:42:02.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:42:02.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:42:02.82$4f8m12a/ifd4f 2006.189.07:42:02.82$ifd4f/lo= 2006.189.07:42:02.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:42:02.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:42:02.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:42:02.82$ifd4f/patch= 2006.189.07:42:02.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:42:02.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:42:02.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:42:02.82$4f8m12a/"form=m,16.000,1:2 2006.189.07:42:02.82$4f8m12a/"tpicd 2006.189.07:42:02.82$4f8m12a/echo=off 2006.189.07:42:02.82$4f8m12a/xlog=off 2006.189.07:42:02.82:!2006.189.07:42:30 2006.189.07:42:16.14#trakl#Source acquired 2006.189.07:42:18.14#flagr#flagr/antenna,acquired 2006.189.07:42:30.00:preob 2006.189.07:42:31.14/onsource/TRACKING 2006.189.07:42:31.14:!2006.189.07:42:40 2006.189.07:42:40.00:data_valid=on 2006.189.07:42:40.00:midob 2006.189.07:42:40.14/onsource/TRACKING 2006.189.07:42:40.14/wx/26.22,1008.9,88 2006.189.07:42:40.21/cable/+6.4535E-03 2006.189.07:42:41.30/va/01,08,usb,yes,28,30 2006.189.07:42:41.30/va/02,07,usb,yes,29,30 2006.189.07:42:41.30/va/03,06,usb,yes,30,30 2006.189.07:42:41.30/va/04,07,usb,yes,30,32 2006.189.07:42:41.30/va/05,07,usb,yes,31,33 2006.189.07:42:41.30/va/06,06,usb,yes,30,30 2006.189.07:42:41.30/va/07,06,usb,yes,30,30 2006.189.07:42:41.30/va/08,06,usb,yes,33,32 2006.189.07:42:41.53/valo/01,532.99,yes,locked 2006.189.07:42:41.53/valo/02,572.99,yes,locked 2006.189.07:42:41.53/valo/03,672.99,yes,locked 2006.189.07:42:41.53/valo/04,832.99,yes,locked 2006.189.07:42:41.53/valo/05,652.99,yes,locked 2006.189.07:42:41.53/valo/06,772.99,yes,locked 2006.189.07:42:41.53/valo/07,832.99,yes,locked 2006.189.07:42:41.53/valo/08,852.99,yes,locked 2006.189.07:42:42.62/vb/01,04,usb,yes,28,27 2006.189.07:42:42.62/vb/02,04,usb,yes,30,32 2006.189.07:42:42.62/vb/03,04,usb,yes,27,30 2006.189.07:42:42.62/vb/04,04,usb,yes,27,28 2006.189.07:42:42.62/vb/05,04,usb,yes,26,30 2006.189.07:42:42.62/vb/06,04,usb,yes,27,30 2006.189.07:42:42.62/vb/07,04,usb,yes,29,29 2006.189.07:42:42.62/vb/08,04,usb,yes,27,30 2006.189.07:42:42.86/vblo/01,632.99,yes,locked 2006.189.07:42:42.86/vblo/02,640.99,yes,locked 2006.189.07:42:42.86/vblo/03,656.99,yes,locked 2006.189.07:42:42.86/vblo/04,712.99,yes,locked 2006.189.07:42:42.86/vblo/05,744.99,yes,locked 2006.189.07:42:42.86/vblo/06,752.99,yes,locked 2006.189.07:42:42.86/vblo/07,734.99,yes,locked 2006.189.07:42:42.86/vblo/08,744.99,yes,locked 2006.189.07:42:43.01/vabw/8 2006.189.07:42:43.16/vbbw/8 2006.189.07:42:43.25/xfe/off,on,14.7 2006.189.07:42:43.62/ifatt/23,28,28,28 2006.189.07:42:44.07/fmout-gps/S +2.98E-07 2006.189.07:42:44.16:!2006.189.07:43:40 2006.189.07:43:40.01:data_valid=off 2006.189.07:43:40.02:postob 2006.189.07:43:40.10/cable/+6.4531E-03 2006.189.07:43:40.11/wx/26.18,1008.9,88 2006.189.07:43:41.07/fmout-gps/S +2.99E-07 2006.189.07:43:41.08:scan_name=189-0744,k06189,60 2006.189.07:43:41.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.189.07:43:41.14#flagr#flagr/antenna,new-source 2006.189.07:43:42.13:checkk5 2006.189.07:43:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:43:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:43:43.30/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:43:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:43:44.05/chk_obsdata//k5ts1/T1890742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:43:44.43/chk_obsdata//k5ts2/T1890742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:43:44.81/chk_obsdata//k5ts3/T1890742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:43:45.19/chk_obsdata//k5ts4/T1890742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:43:45.88/k5log//k5ts1_log_newline 2006.189.07:43:46.58/k5log//k5ts2_log_newline 2006.189.07:43:47.28/k5log//k5ts3_log_newline 2006.189.07:43:47.98/k5log//k5ts4_log_newline 2006.189.07:43:48.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:43:48.00:4f8m12a=1 2006.189.07:43:48.00$4f8m12a/echo=on 2006.189.07:43:48.00$4f8m12a/pcalon 2006.189.07:43:48.00$pcalon/"no phase cal control is implemented here 2006.189.07:43:48.00$4f8m12a/"tpicd=stop 2006.189.07:43:48.00$4f8m12a/vc4f8 2006.189.07:43:48.00$vc4f8/valo=1,532.99 2006.189.07:43:48.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.07:43:48.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.07:43:48.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:48.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:48.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:48.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:48.01#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:43:48.01#ibcon#first serial, iclass 38, count 0 2006.189.07:43:48.01#ibcon#enter sib2, iclass 38, count 0 2006.189.07:43:48.01#ibcon#flushed, iclass 38, count 0 2006.189.07:43:48.01#ibcon#about to write, iclass 38, count 0 2006.189.07:43:48.01#ibcon#wrote, iclass 38, count 0 2006.189.07:43:48.01#ibcon#about to read 3, iclass 38, count 0 2006.189.07:43:48.05#ibcon#read 3, iclass 38, count 0 2006.189.07:43:48.05#ibcon#about to read 4, iclass 38, count 0 2006.189.07:43:48.05#ibcon#read 4, iclass 38, count 0 2006.189.07:43:48.05#ibcon#about to read 5, iclass 38, count 0 2006.189.07:43:48.05#ibcon#read 5, iclass 38, count 0 2006.189.07:43:48.05#ibcon#about to read 6, iclass 38, count 0 2006.189.07:43:48.05#ibcon#read 6, iclass 38, count 0 2006.189.07:43:48.05#ibcon#end of sib2, iclass 38, count 0 2006.189.07:43:48.05#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:43:48.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:43:48.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:43:48.05#ibcon#*before write, iclass 38, count 0 2006.189.07:43:48.05#ibcon#enter sib2, iclass 38, count 0 2006.189.07:43:48.05#ibcon#flushed, iclass 38, count 0 2006.189.07:43:48.05#ibcon#about to write, iclass 38, count 0 2006.189.07:43:48.05#ibcon#wrote, iclass 38, count 0 2006.189.07:43:48.05#ibcon#about to read 3, iclass 38, count 0 2006.189.07:43:48.10#ibcon#read 3, iclass 38, count 0 2006.189.07:43:48.10#ibcon#about to read 4, iclass 38, count 0 2006.189.07:43:48.10#ibcon#read 4, iclass 38, count 0 2006.189.07:43:48.10#ibcon#about to read 5, iclass 38, count 0 2006.189.07:43:48.10#ibcon#read 5, iclass 38, count 0 2006.189.07:43:48.10#ibcon#about to read 6, iclass 38, count 0 2006.189.07:43:48.10#ibcon#read 6, iclass 38, count 0 2006.189.07:43:48.10#ibcon#end of sib2, iclass 38, count 0 2006.189.07:43:48.10#ibcon#*after write, iclass 38, count 0 2006.189.07:43:48.10#ibcon#*before return 0, iclass 38, count 0 2006.189.07:43:48.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:48.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:48.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:43:48.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:43:48.10$vc4f8/va=1,8 2006.189.07:43:48.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.07:43:48.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.07:43:48.10#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:48.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:48.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:48.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:48.10#ibcon#enter wrdev, iclass 40, count 2 2006.189.07:43:48.10#ibcon#first serial, iclass 40, count 2 2006.189.07:43:48.10#ibcon#enter sib2, iclass 40, count 2 2006.189.07:43:48.10#ibcon#flushed, iclass 40, count 2 2006.189.07:43:48.10#ibcon#about to write, iclass 40, count 2 2006.189.07:43:48.10#ibcon#wrote, iclass 40, count 2 2006.189.07:43:48.10#ibcon#about to read 3, iclass 40, count 2 2006.189.07:43:48.12#ibcon#read 3, iclass 40, count 2 2006.189.07:43:48.12#ibcon#about to read 4, iclass 40, count 2 2006.189.07:43:48.12#ibcon#read 4, iclass 40, count 2 2006.189.07:43:48.12#ibcon#about to read 5, iclass 40, count 2 2006.189.07:43:48.12#ibcon#read 5, iclass 40, count 2 2006.189.07:43:48.12#ibcon#about to read 6, iclass 40, count 2 2006.189.07:43:48.12#ibcon#read 6, iclass 40, count 2 2006.189.07:43:48.12#ibcon#end of sib2, iclass 40, count 2 2006.189.07:43:48.12#ibcon#*mode == 0, iclass 40, count 2 2006.189.07:43:48.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.07:43:48.12#ibcon#[25=AT01-08\r\n] 2006.189.07:43:48.12#ibcon#*before write, iclass 40, count 2 2006.189.07:43:48.12#ibcon#enter sib2, iclass 40, count 2 2006.189.07:43:48.12#ibcon#flushed, iclass 40, count 2 2006.189.07:43:48.12#ibcon#about to write, iclass 40, count 2 2006.189.07:43:48.12#ibcon#wrote, iclass 40, count 2 2006.189.07:43:48.12#ibcon#about to read 3, iclass 40, count 2 2006.189.07:43:48.15#ibcon#read 3, iclass 40, count 2 2006.189.07:43:48.15#ibcon#about to read 4, iclass 40, count 2 2006.189.07:43:48.15#ibcon#read 4, iclass 40, count 2 2006.189.07:43:48.15#ibcon#about to read 5, iclass 40, count 2 2006.189.07:43:48.15#ibcon#read 5, iclass 40, count 2 2006.189.07:43:48.15#ibcon#about to read 6, iclass 40, count 2 2006.189.07:43:48.15#ibcon#read 6, iclass 40, count 2 2006.189.07:43:48.15#ibcon#end of sib2, iclass 40, count 2 2006.189.07:43:48.15#ibcon#*after write, iclass 40, count 2 2006.189.07:43:48.15#ibcon#*before return 0, iclass 40, count 2 2006.189.07:43:48.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:48.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:48.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.07:43:48.15#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:48.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:48.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:48.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:48.27#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:43:48.27#ibcon#first serial, iclass 40, count 0 2006.189.07:43:48.27#ibcon#enter sib2, iclass 40, count 0 2006.189.07:43:48.27#ibcon#flushed, iclass 40, count 0 2006.189.07:43:48.27#ibcon#about to write, iclass 40, count 0 2006.189.07:43:48.27#ibcon#wrote, iclass 40, count 0 2006.189.07:43:48.27#ibcon#about to read 3, iclass 40, count 0 2006.189.07:43:48.29#ibcon#read 3, iclass 40, count 0 2006.189.07:43:48.29#ibcon#about to read 4, iclass 40, count 0 2006.189.07:43:48.29#ibcon#read 4, iclass 40, count 0 2006.189.07:43:48.29#ibcon#about to read 5, iclass 40, count 0 2006.189.07:43:48.29#ibcon#read 5, iclass 40, count 0 2006.189.07:43:48.29#ibcon#about to read 6, iclass 40, count 0 2006.189.07:43:48.29#ibcon#read 6, iclass 40, count 0 2006.189.07:43:48.29#ibcon#end of sib2, iclass 40, count 0 2006.189.07:43:48.29#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:43:48.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:43:48.29#ibcon#[25=USB\r\n] 2006.189.07:43:48.29#ibcon#*before write, iclass 40, count 0 2006.189.07:43:48.29#ibcon#enter sib2, iclass 40, count 0 2006.189.07:43:48.29#ibcon#flushed, iclass 40, count 0 2006.189.07:43:48.29#ibcon#about to write, iclass 40, count 0 2006.189.07:43:48.29#ibcon#wrote, iclass 40, count 0 2006.189.07:43:48.29#ibcon#about to read 3, iclass 40, count 0 2006.189.07:43:48.32#ibcon#read 3, iclass 40, count 0 2006.189.07:43:48.32#ibcon#about to read 4, iclass 40, count 0 2006.189.07:43:48.32#ibcon#read 4, iclass 40, count 0 2006.189.07:43:48.32#ibcon#about to read 5, iclass 40, count 0 2006.189.07:43:48.32#ibcon#read 5, iclass 40, count 0 2006.189.07:43:48.32#ibcon#about to read 6, iclass 40, count 0 2006.189.07:43:48.32#ibcon#read 6, iclass 40, count 0 2006.189.07:43:48.32#ibcon#end of sib2, iclass 40, count 0 2006.189.07:43:48.32#ibcon#*after write, iclass 40, count 0 2006.189.07:43:48.32#ibcon#*before return 0, iclass 40, count 0 2006.189.07:43:48.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:48.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:48.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:43:48.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:43:48.32$vc4f8/valo=2,572.99 2006.189.07:43:48.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:43:48.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:43:48.32#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:48.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:48.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:48.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:48.32#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:43:48.32#ibcon#first serial, iclass 4, count 0 2006.189.07:43:48.32#ibcon#enter sib2, iclass 4, count 0 2006.189.07:43:48.32#ibcon#flushed, iclass 4, count 0 2006.189.07:43:48.32#ibcon#about to write, iclass 4, count 0 2006.189.07:43:48.32#ibcon#wrote, iclass 4, count 0 2006.189.07:43:48.32#ibcon#about to read 3, iclass 4, count 0 2006.189.07:43:48.34#ibcon#read 3, iclass 4, count 0 2006.189.07:43:48.34#ibcon#about to read 4, iclass 4, count 0 2006.189.07:43:48.34#ibcon#read 4, iclass 4, count 0 2006.189.07:43:48.34#ibcon#about to read 5, iclass 4, count 0 2006.189.07:43:48.34#ibcon#read 5, iclass 4, count 0 2006.189.07:43:48.34#ibcon#about to read 6, iclass 4, count 0 2006.189.07:43:48.34#ibcon#read 6, iclass 4, count 0 2006.189.07:43:48.34#ibcon#end of sib2, iclass 4, count 0 2006.189.07:43:48.34#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:43:48.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:43:48.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:43:48.34#ibcon#*before write, iclass 4, count 0 2006.189.07:43:48.34#ibcon#enter sib2, iclass 4, count 0 2006.189.07:43:48.34#ibcon#flushed, iclass 4, count 0 2006.189.07:43:48.34#ibcon#about to write, iclass 4, count 0 2006.189.07:43:48.34#ibcon#wrote, iclass 4, count 0 2006.189.07:43:48.34#ibcon#about to read 3, iclass 4, count 0 2006.189.07:43:48.38#ibcon#read 3, iclass 4, count 0 2006.189.07:43:48.38#ibcon#about to read 4, iclass 4, count 0 2006.189.07:43:48.38#ibcon#read 4, iclass 4, count 0 2006.189.07:43:48.38#ibcon#about to read 5, iclass 4, count 0 2006.189.07:43:48.38#ibcon#read 5, iclass 4, count 0 2006.189.07:43:48.38#ibcon#about to read 6, iclass 4, count 0 2006.189.07:43:48.38#ibcon#read 6, iclass 4, count 0 2006.189.07:43:48.38#ibcon#end of sib2, iclass 4, count 0 2006.189.07:43:48.38#ibcon#*after write, iclass 4, count 0 2006.189.07:43:48.38#ibcon#*before return 0, iclass 4, count 0 2006.189.07:43:48.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:48.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:48.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:43:48.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:43:48.39$vc4f8/va=2,7 2006.189.07:43:48.39#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.07:43:48.39#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.07:43:48.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:48.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:48.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:48.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:48.43#ibcon#enter wrdev, iclass 6, count 2 2006.189.07:43:48.43#ibcon#first serial, iclass 6, count 2 2006.189.07:43:48.43#ibcon#enter sib2, iclass 6, count 2 2006.189.07:43:48.43#ibcon#flushed, iclass 6, count 2 2006.189.07:43:48.43#ibcon#about to write, iclass 6, count 2 2006.189.07:43:48.43#ibcon#wrote, iclass 6, count 2 2006.189.07:43:48.43#ibcon#about to read 3, iclass 6, count 2 2006.189.07:43:48.45#ibcon#read 3, iclass 6, count 2 2006.189.07:43:48.45#ibcon#about to read 4, iclass 6, count 2 2006.189.07:43:48.45#ibcon#read 4, iclass 6, count 2 2006.189.07:43:48.45#ibcon#about to read 5, iclass 6, count 2 2006.189.07:43:48.45#ibcon#read 5, iclass 6, count 2 2006.189.07:43:48.45#ibcon#about to read 6, iclass 6, count 2 2006.189.07:43:48.45#ibcon#read 6, iclass 6, count 2 2006.189.07:43:48.45#ibcon#end of sib2, iclass 6, count 2 2006.189.07:43:48.45#ibcon#*mode == 0, iclass 6, count 2 2006.189.07:43:48.45#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.07:43:48.45#ibcon#[25=AT02-07\r\n] 2006.189.07:43:48.45#ibcon#*before write, iclass 6, count 2 2006.189.07:43:48.45#ibcon#enter sib2, iclass 6, count 2 2006.189.07:43:48.45#ibcon#flushed, iclass 6, count 2 2006.189.07:43:48.45#ibcon#about to write, iclass 6, count 2 2006.189.07:43:48.45#ibcon#wrote, iclass 6, count 2 2006.189.07:43:48.45#ibcon#about to read 3, iclass 6, count 2 2006.189.07:43:48.48#ibcon#read 3, iclass 6, count 2 2006.189.07:43:48.48#ibcon#about to read 4, iclass 6, count 2 2006.189.07:43:48.48#ibcon#read 4, iclass 6, count 2 2006.189.07:43:48.48#ibcon#about to read 5, iclass 6, count 2 2006.189.07:43:48.48#ibcon#read 5, iclass 6, count 2 2006.189.07:43:48.48#ibcon#about to read 6, iclass 6, count 2 2006.189.07:43:48.48#ibcon#read 6, iclass 6, count 2 2006.189.07:43:48.48#ibcon#end of sib2, iclass 6, count 2 2006.189.07:43:48.48#ibcon#*after write, iclass 6, count 2 2006.189.07:43:48.48#ibcon#*before return 0, iclass 6, count 2 2006.189.07:43:48.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:48.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:48.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.07:43:48.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:48.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:48.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:48.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:48.60#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:43:48.60#ibcon#first serial, iclass 6, count 0 2006.189.07:43:48.60#ibcon#enter sib2, iclass 6, count 0 2006.189.07:43:48.60#ibcon#flushed, iclass 6, count 0 2006.189.07:43:48.60#ibcon#about to write, iclass 6, count 0 2006.189.07:43:48.60#ibcon#wrote, iclass 6, count 0 2006.189.07:43:48.60#ibcon#about to read 3, iclass 6, count 0 2006.189.07:43:48.62#ibcon#read 3, iclass 6, count 0 2006.189.07:43:48.62#ibcon#about to read 4, iclass 6, count 0 2006.189.07:43:48.62#ibcon#read 4, iclass 6, count 0 2006.189.07:43:48.62#ibcon#about to read 5, iclass 6, count 0 2006.189.07:43:48.62#ibcon#read 5, iclass 6, count 0 2006.189.07:43:48.62#ibcon#about to read 6, iclass 6, count 0 2006.189.07:43:48.62#ibcon#read 6, iclass 6, count 0 2006.189.07:43:48.62#ibcon#end of sib2, iclass 6, count 0 2006.189.07:43:48.62#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:43:48.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:43:48.62#ibcon#[25=USB\r\n] 2006.189.07:43:48.62#ibcon#*before write, iclass 6, count 0 2006.189.07:43:48.62#ibcon#enter sib2, iclass 6, count 0 2006.189.07:43:48.62#ibcon#flushed, iclass 6, count 0 2006.189.07:43:48.62#ibcon#about to write, iclass 6, count 0 2006.189.07:43:48.62#ibcon#wrote, iclass 6, count 0 2006.189.07:43:48.62#ibcon#about to read 3, iclass 6, count 0 2006.189.07:43:48.65#ibcon#read 3, iclass 6, count 0 2006.189.07:43:48.65#ibcon#about to read 4, iclass 6, count 0 2006.189.07:43:48.65#ibcon#read 4, iclass 6, count 0 2006.189.07:43:48.65#ibcon#about to read 5, iclass 6, count 0 2006.189.07:43:48.65#ibcon#read 5, iclass 6, count 0 2006.189.07:43:48.65#ibcon#about to read 6, iclass 6, count 0 2006.189.07:43:48.65#ibcon#read 6, iclass 6, count 0 2006.189.07:43:48.65#ibcon#end of sib2, iclass 6, count 0 2006.189.07:43:48.65#ibcon#*after write, iclass 6, count 0 2006.189.07:43:48.65#ibcon#*before return 0, iclass 6, count 0 2006.189.07:43:48.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:48.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:48.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:43:48.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:43:48.65$vc4f8/valo=3,672.99 2006.189.07:43:48.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.07:43:48.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.07:43:48.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:48.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:48.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:48.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:48.65#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:43:48.65#ibcon#first serial, iclass 10, count 0 2006.189.07:43:48.65#ibcon#enter sib2, iclass 10, count 0 2006.189.07:43:48.65#ibcon#flushed, iclass 10, count 0 2006.189.07:43:48.65#ibcon#about to write, iclass 10, count 0 2006.189.07:43:48.65#ibcon#wrote, iclass 10, count 0 2006.189.07:43:48.65#ibcon#about to read 3, iclass 10, count 0 2006.189.07:43:48.67#ibcon#read 3, iclass 10, count 0 2006.189.07:43:48.67#ibcon#about to read 4, iclass 10, count 0 2006.189.07:43:48.67#ibcon#read 4, iclass 10, count 0 2006.189.07:43:48.67#ibcon#about to read 5, iclass 10, count 0 2006.189.07:43:48.67#ibcon#read 5, iclass 10, count 0 2006.189.07:43:48.67#ibcon#about to read 6, iclass 10, count 0 2006.189.07:43:48.67#ibcon#read 6, iclass 10, count 0 2006.189.07:43:48.67#ibcon#end of sib2, iclass 10, count 0 2006.189.07:43:48.67#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:43:48.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:43:48.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:43:48.67#ibcon#*before write, iclass 10, count 0 2006.189.07:43:48.67#ibcon#enter sib2, iclass 10, count 0 2006.189.07:43:48.67#ibcon#flushed, iclass 10, count 0 2006.189.07:43:48.67#ibcon#about to write, iclass 10, count 0 2006.189.07:43:48.67#ibcon#wrote, iclass 10, count 0 2006.189.07:43:48.67#ibcon#about to read 3, iclass 10, count 0 2006.189.07:43:48.71#ibcon#read 3, iclass 10, count 0 2006.189.07:43:48.71#ibcon#about to read 4, iclass 10, count 0 2006.189.07:43:48.71#ibcon#read 4, iclass 10, count 0 2006.189.07:43:48.71#ibcon#about to read 5, iclass 10, count 0 2006.189.07:43:48.71#ibcon#read 5, iclass 10, count 0 2006.189.07:43:48.71#ibcon#about to read 6, iclass 10, count 0 2006.189.07:43:48.71#ibcon#read 6, iclass 10, count 0 2006.189.07:43:48.71#ibcon#end of sib2, iclass 10, count 0 2006.189.07:43:48.71#ibcon#*after write, iclass 10, count 0 2006.189.07:43:48.71#ibcon#*before return 0, iclass 10, count 0 2006.189.07:43:48.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:48.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:48.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:43:48.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:43:48.71$vc4f8/va=3,6 2006.189.07:43:48.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.07:43:48.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.07:43:48.72#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:48.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:48.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:48.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:48.76#ibcon#enter wrdev, iclass 12, count 2 2006.189.07:43:48.76#ibcon#first serial, iclass 12, count 2 2006.189.07:43:48.76#ibcon#enter sib2, iclass 12, count 2 2006.189.07:43:48.76#ibcon#flushed, iclass 12, count 2 2006.189.07:43:48.76#ibcon#about to write, iclass 12, count 2 2006.189.07:43:48.76#ibcon#wrote, iclass 12, count 2 2006.189.07:43:48.76#ibcon#about to read 3, iclass 12, count 2 2006.189.07:43:48.78#ibcon#read 3, iclass 12, count 2 2006.189.07:43:48.78#ibcon#about to read 4, iclass 12, count 2 2006.189.07:43:48.78#ibcon#read 4, iclass 12, count 2 2006.189.07:43:48.78#ibcon#about to read 5, iclass 12, count 2 2006.189.07:43:48.78#ibcon#read 5, iclass 12, count 2 2006.189.07:43:48.78#ibcon#about to read 6, iclass 12, count 2 2006.189.07:43:48.78#ibcon#read 6, iclass 12, count 2 2006.189.07:43:48.78#ibcon#end of sib2, iclass 12, count 2 2006.189.07:43:48.78#ibcon#*mode == 0, iclass 12, count 2 2006.189.07:43:48.78#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.07:43:48.78#ibcon#[25=AT03-06\r\n] 2006.189.07:43:48.78#ibcon#*before write, iclass 12, count 2 2006.189.07:43:48.78#ibcon#enter sib2, iclass 12, count 2 2006.189.07:43:48.78#ibcon#flushed, iclass 12, count 2 2006.189.07:43:48.78#ibcon#about to write, iclass 12, count 2 2006.189.07:43:48.78#ibcon#wrote, iclass 12, count 2 2006.189.07:43:48.78#ibcon#about to read 3, iclass 12, count 2 2006.189.07:43:48.81#ibcon#read 3, iclass 12, count 2 2006.189.07:43:48.81#ibcon#about to read 4, iclass 12, count 2 2006.189.07:43:48.81#ibcon#read 4, iclass 12, count 2 2006.189.07:43:48.81#ibcon#about to read 5, iclass 12, count 2 2006.189.07:43:48.81#ibcon#read 5, iclass 12, count 2 2006.189.07:43:48.81#ibcon#about to read 6, iclass 12, count 2 2006.189.07:43:48.81#ibcon#read 6, iclass 12, count 2 2006.189.07:43:48.81#ibcon#end of sib2, iclass 12, count 2 2006.189.07:43:48.81#ibcon#*after write, iclass 12, count 2 2006.189.07:43:48.81#ibcon#*before return 0, iclass 12, count 2 2006.189.07:43:48.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:48.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:48.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.07:43:48.81#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:48.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:48.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:48.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:48.93#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:43:48.93#ibcon#first serial, iclass 12, count 0 2006.189.07:43:48.93#ibcon#enter sib2, iclass 12, count 0 2006.189.07:43:48.93#ibcon#flushed, iclass 12, count 0 2006.189.07:43:48.93#ibcon#about to write, iclass 12, count 0 2006.189.07:43:48.93#ibcon#wrote, iclass 12, count 0 2006.189.07:43:48.93#ibcon#about to read 3, iclass 12, count 0 2006.189.07:43:48.95#ibcon#read 3, iclass 12, count 0 2006.189.07:43:48.95#ibcon#about to read 4, iclass 12, count 0 2006.189.07:43:48.95#ibcon#read 4, iclass 12, count 0 2006.189.07:43:48.95#ibcon#about to read 5, iclass 12, count 0 2006.189.07:43:48.95#ibcon#read 5, iclass 12, count 0 2006.189.07:43:48.95#ibcon#about to read 6, iclass 12, count 0 2006.189.07:43:48.95#ibcon#read 6, iclass 12, count 0 2006.189.07:43:48.95#ibcon#end of sib2, iclass 12, count 0 2006.189.07:43:48.95#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:43:48.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:43:48.95#ibcon#[25=USB\r\n] 2006.189.07:43:48.95#ibcon#*before write, iclass 12, count 0 2006.189.07:43:48.95#ibcon#enter sib2, iclass 12, count 0 2006.189.07:43:48.95#ibcon#flushed, iclass 12, count 0 2006.189.07:43:48.95#ibcon#about to write, iclass 12, count 0 2006.189.07:43:48.95#ibcon#wrote, iclass 12, count 0 2006.189.07:43:48.95#ibcon#about to read 3, iclass 12, count 0 2006.189.07:43:48.98#ibcon#read 3, iclass 12, count 0 2006.189.07:43:48.98#ibcon#about to read 4, iclass 12, count 0 2006.189.07:43:48.98#ibcon#read 4, iclass 12, count 0 2006.189.07:43:48.98#ibcon#about to read 5, iclass 12, count 0 2006.189.07:43:48.98#ibcon#read 5, iclass 12, count 0 2006.189.07:43:48.98#ibcon#about to read 6, iclass 12, count 0 2006.189.07:43:48.98#ibcon#read 6, iclass 12, count 0 2006.189.07:43:48.98#ibcon#end of sib2, iclass 12, count 0 2006.189.07:43:48.98#ibcon#*after write, iclass 12, count 0 2006.189.07:43:48.98#ibcon#*before return 0, iclass 12, count 0 2006.189.07:43:48.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:48.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:48.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:43:48.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:43:48.98$vc4f8/valo=4,832.99 2006.189.07:43:48.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.07:43:48.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.07:43:48.98#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:48.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:48.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:48.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:48.98#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:43:48.98#ibcon#first serial, iclass 14, count 0 2006.189.07:43:48.98#ibcon#enter sib2, iclass 14, count 0 2006.189.07:43:48.98#ibcon#flushed, iclass 14, count 0 2006.189.07:43:48.98#ibcon#about to write, iclass 14, count 0 2006.189.07:43:48.98#ibcon#wrote, iclass 14, count 0 2006.189.07:43:48.98#ibcon#about to read 3, iclass 14, count 0 2006.189.07:43:49.00#ibcon#read 3, iclass 14, count 0 2006.189.07:43:49.00#ibcon#about to read 4, iclass 14, count 0 2006.189.07:43:49.00#ibcon#read 4, iclass 14, count 0 2006.189.07:43:49.00#ibcon#about to read 5, iclass 14, count 0 2006.189.07:43:49.00#ibcon#read 5, iclass 14, count 0 2006.189.07:43:49.00#ibcon#about to read 6, iclass 14, count 0 2006.189.07:43:49.00#ibcon#read 6, iclass 14, count 0 2006.189.07:43:49.00#ibcon#end of sib2, iclass 14, count 0 2006.189.07:43:49.00#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:43:49.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:43:49.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:43:49.00#ibcon#*before write, iclass 14, count 0 2006.189.07:43:49.00#ibcon#enter sib2, iclass 14, count 0 2006.189.07:43:49.00#ibcon#flushed, iclass 14, count 0 2006.189.07:43:49.00#ibcon#about to write, iclass 14, count 0 2006.189.07:43:49.00#ibcon#wrote, iclass 14, count 0 2006.189.07:43:49.00#ibcon#about to read 3, iclass 14, count 0 2006.189.07:43:49.04#ibcon#read 3, iclass 14, count 0 2006.189.07:43:49.04#ibcon#about to read 4, iclass 14, count 0 2006.189.07:43:49.04#ibcon#read 4, iclass 14, count 0 2006.189.07:43:49.04#ibcon#about to read 5, iclass 14, count 0 2006.189.07:43:49.04#ibcon#read 5, iclass 14, count 0 2006.189.07:43:49.04#ibcon#about to read 6, iclass 14, count 0 2006.189.07:43:49.04#ibcon#read 6, iclass 14, count 0 2006.189.07:43:49.04#ibcon#end of sib2, iclass 14, count 0 2006.189.07:43:49.04#ibcon#*after write, iclass 14, count 0 2006.189.07:43:49.04#ibcon#*before return 0, iclass 14, count 0 2006.189.07:43:49.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:49.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:49.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:43:49.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:43:49.04$vc4f8/va=4,7 2006.189.07:43:49.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.07:43:49.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.07:43:49.04#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:49.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:49.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:49.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:49.10#ibcon#enter wrdev, iclass 16, count 2 2006.189.07:43:49.10#ibcon#first serial, iclass 16, count 2 2006.189.07:43:49.10#ibcon#enter sib2, iclass 16, count 2 2006.189.07:43:49.10#ibcon#flushed, iclass 16, count 2 2006.189.07:43:49.10#ibcon#about to write, iclass 16, count 2 2006.189.07:43:49.10#ibcon#wrote, iclass 16, count 2 2006.189.07:43:49.10#ibcon#about to read 3, iclass 16, count 2 2006.189.07:43:49.12#ibcon#read 3, iclass 16, count 2 2006.189.07:43:49.12#ibcon#about to read 4, iclass 16, count 2 2006.189.07:43:49.12#ibcon#read 4, iclass 16, count 2 2006.189.07:43:49.12#ibcon#about to read 5, iclass 16, count 2 2006.189.07:43:49.12#ibcon#read 5, iclass 16, count 2 2006.189.07:43:49.12#ibcon#about to read 6, iclass 16, count 2 2006.189.07:43:49.12#ibcon#read 6, iclass 16, count 2 2006.189.07:43:49.12#ibcon#end of sib2, iclass 16, count 2 2006.189.07:43:49.12#ibcon#*mode == 0, iclass 16, count 2 2006.189.07:43:49.12#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.07:43:49.12#ibcon#[25=AT04-07\r\n] 2006.189.07:43:49.12#ibcon#*before write, iclass 16, count 2 2006.189.07:43:49.12#ibcon#enter sib2, iclass 16, count 2 2006.189.07:43:49.12#ibcon#flushed, iclass 16, count 2 2006.189.07:43:49.12#ibcon#about to write, iclass 16, count 2 2006.189.07:43:49.12#ibcon#wrote, iclass 16, count 2 2006.189.07:43:49.12#ibcon#about to read 3, iclass 16, count 2 2006.189.07:43:49.15#ibcon#read 3, iclass 16, count 2 2006.189.07:43:49.15#ibcon#about to read 4, iclass 16, count 2 2006.189.07:43:49.15#ibcon#read 4, iclass 16, count 2 2006.189.07:43:49.15#ibcon#about to read 5, iclass 16, count 2 2006.189.07:43:49.15#ibcon#read 5, iclass 16, count 2 2006.189.07:43:49.15#ibcon#about to read 6, iclass 16, count 2 2006.189.07:43:49.15#ibcon#read 6, iclass 16, count 2 2006.189.07:43:49.15#ibcon#end of sib2, iclass 16, count 2 2006.189.07:43:49.15#ibcon#*after write, iclass 16, count 2 2006.189.07:43:49.15#ibcon#*before return 0, iclass 16, count 2 2006.189.07:43:49.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:49.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:49.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.07:43:49.15#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:49.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:49.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:49.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:49.27#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:43:49.27#ibcon#first serial, iclass 16, count 0 2006.189.07:43:49.27#ibcon#enter sib2, iclass 16, count 0 2006.189.07:43:49.27#ibcon#flushed, iclass 16, count 0 2006.189.07:43:49.27#ibcon#about to write, iclass 16, count 0 2006.189.07:43:49.27#ibcon#wrote, iclass 16, count 0 2006.189.07:43:49.27#ibcon#about to read 3, iclass 16, count 0 2006.189.07:43:49.29#ibcon#read 3, iclass 16, count 0 2006.189.07:43:49.29#ibcon#about to read 4, iclass 16, count 0 2006.189.07:43:49.29#ibcon#read 4, iclass 16, count 0 2006.189.07:43:49.29#ibcon#about to read 5, iclass 16, count 0 2006.189.07:43:49.29#ibcon#read 5, iclass 16, count 0 2006.189.07:43:49.29#ibcon#about to read 6, iclass 16, count 0 2006.189.07:43:49.29#ibcon#read 6, iclass 16, count 0 2006.189.07:43:49.29#ibcon#end of sib2, iclass 16, count 0 2006.189.07:43:49.29#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:43:49.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:43:49.29#ibcon#[25=USB\r\n] 2006.189.07:43:49.29#ibcon#*before write, iclass 16, count 0 2006.189.07:43:49.29#ibcon#enter sib2, iclass 16, count 0 2006.189.07:43:49.29#ibcon#flushed, iclass 16, count 0 2006.189.07:43:49.29#ibcon#about to write, iclass 16, count 0 2006.189.07:43:49.29#ibcon#wrote, iclass 16, count 0 2006.189.07:43:49.29#ibcon#about to read 3, iclass 16, count 0 2006.189.07:43:49.32#ibcon#read 3, iclass 16, count 0 2006.189.07:43:49.32#ibcon#about to read 4, iclass 16, count 0 2006.189.07:43:49.32#ibcon#read 4, iclass 16, count 0 2006.189.07:43:49.32#ibcon#about to read 5, iclass 16, count 0 2006.189.07:43:49.32#ibcon#read 5, iclass 16, count 0 2006.189.07:43:49.32#ibcon#about to read 6, iclass 16, count 0 2006.189.07:43:49.32#ibcon#read 6, iclass 16, count 0 2006.189.07:43:49.32#ibcon#end of sib2, iclass 16, count 0 2006.189.07:43:49.32#ibcon#*after write, iclass 16, count 0 2006.189.07:43:49.32#ibcon#*before return 0, iclass 16, count 0 2006.189.07:43:49.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:49.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:49.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:43:49.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:43:49.32$vc4f8/valo=5,652.99 2006.189.07:43:49.32#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.07:43:49.32#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.07:43:49.32#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:49.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:49.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:49.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:49.32#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:43:49.32#ibcon#first serial, iclass 18, count 0 2006.189.07:43:49.32#ibcon#enter sib2, iclass 18, count 0 2006.189.07:43:49.32#ibcon#flushed, iclass 18, count 0 2006.189.07:43:49.32#ibcon#about to write, iclass 18, count 0 2006.189.07:43:49.32#ibcon#wrote, iclass 18, count 0 2006.189.07:43:49.32#ibcon#about to read 3, iclass 18, count 0 2006.189.07:43:49.34#ibcon#read 3, iclass 18, count 0 2006.189.07:43:49.34#ibcon#about to read 4, iclass 18, count 0 2006.189.07:43:49.34#ibcon#read 4, iclass 18, count 0 2006.189.07:43:49.34#ibcon#about to read 5, iclass 18, count 0 2006.189.07:43:49.34#ibcon#read 5, iclass 18, count 0 2006.189.07:43:49.34#ibcon#about to read 6, iclass 18, count 0 2006.189.07:43:49.34#ibcon#read 6, iclass 18, count 0 2006.189.07:43:49.34#ibcon#end of sib2, iclass 18, count 0 2006.189.07:43:49.34#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:43:49.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:43:49.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:43:49.34#ibcon#*before write, iclass 18, count 0 2006.189.07:43:49.34#ibcon#enter sib2, iclass 18, count 0 2006.189.07:43:49.34#ibcon#flushed, iclass 18, count 0 2006.189.07:43:49.34#ibcon#about to write, iclass 18, count 0 2006.189.07:43:49.34#ibcon#wrote, iclass 18, count 0 2006.189.07:43:49.34#ibcon#about to read 3, iclass 18, count 0 2006.189.07:43:49.38#ibcon#read 3, iclass 18, count 0 2006.189.07:43:49.38#ibcon#about to read 4, iclass 18, count 0 2006.189.07:43:49.38#ibcon#read 4, iclass 18, count 0 2006.189.07:43:49.38#ibcon#about to read 5, iclass 18, count 0 2006.189.07:43:49.38#ibcon#read 5, iclass 18, count 0 2006.189.07:43:49.38#ibcon#about to read 6, iclass 18, count 0 2006.189.07:43:49.38#ibcon#read 6, iclass 18, count 0 2006.189.07:43:49.38#ibcon#end of sib2, iclass 18, count 0 2006.189.07:43:49.38#ibcon#*after write, iclass 18, count 0 2006.189.07:43:49.38#ibcon#*before return 0, iclass 18, count 0 2006.189.07:43:49.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:49.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:49.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:43:49.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:43:49.38$vc4f8/va=5,7 2006.189.07:43:49.38#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:43:49.38#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:43:49.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:49.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:49.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:49.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:49.44#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:43:49.44#ibcon#first serial, iclass 20, count 2 2006.189.07:43:49.44#ibcon#enter sib2, iclass 20, count 2 2006.189.07:43:49.44#ibcon#flushed, iclass 20, count 2 2006.189.07:43:49.44#ibcon#about to write, iclass 20, count 2 2006.189.07:43:49.44#ibcon#wrote, iclass 20, count 2 2006.189.07:43:49.44#ibcon#about to read 3, iclass 20, count 2 2006.189.07:43:49.46#ibcon#read 3, iclass 20, count 2 2006.189.07:43:49.46#ibcon#about to read 4, iclass 20, count 2 2006.189.07:43:49.46#ibcon#read 4, iclass 20, count 2 2006.189.07:43:49.46#ibcon#about to read 5, iclass 20, count 2 2006.189.07:43:49.46#ibcon#read 5, iclass 20, count 2 2006.189.07:43:49.46#ibcon#about to read 6, iclass 20, count 2 2006.189.07:43:49.46#ibcon#read 6, iclass 20, count 2 2006.189.07:43:49.46#ibcon#end of sib2, iclass 20, count 2 2006.189.07:43:49.46#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:43:49.46#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:43:49.46#ibcon#[25=AT05-07\r\n] 2006.189.07:43:49.46#ibcon#*before write, iclass 20, count 2 2006.189.07:43:49.46#ibcon#enter sib2, iclass 20, count 2 2006.189.07:43:49.46#ibcon#flushed, iclass 20, count 2 2006.189.07:43:49.46#ibcon#about to write, iclass 20, count 2 2006.189.07:43:49.46#ibcon#wrote, iclass 20, count 2 2006.189.07:43:49.46#ibcon#about to read 3, iclass 20, count 2 2006.189.07:43:49.49#ibcon#read 3, iclass 20, count 2 2006.189.07:43:49.49#ibcon#about to read 4, iclass 20, count 2 2006.189.07:43:49.49#ibcon#read 4, iclass 20, count 2 2006.189.07:43:49.49#ibcon#about to read 5, iclass 20, count 2 2006.189.07:43:49.49#ibcon#read 5, iclass 20, count 2 2006.189.07:43:49.49#ibcon#about to read 6, iclass 20, count 2 2006.189.07:43:49.49#ibcon#read 6, iclass 20, count 2 2006.189.07:43:49.49#ibcon#end of sib2, iclass 20, count 2 2006.189.07:43:49.49#ibcon#*after write, iclass 20, count 2 2006.189.07:43:49.49#ibcon#*before return 0, iclass 20, count 2 2006.189.07:43:49.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:49.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:49.49#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:43:49.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:49.49#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:49.61#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:49.61#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:49.61#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:43:49.61#ibcon#first serial, iclass 20, count 0 2006.189.07:43:49.61#ibcon#enter sib2, iclass 20, count 0 2006.189.07:43:49.61#ibcon#flushed, iclass 20, count 0 2006.189.07:43:49.61#ibcon#about to write, iclass 20, count 0 2006.189.07:43:49.61#ibcon#wrote, iclass 20, count 0 2006.189.07:43:49.61#ibcon#about to read 3, iclass 20, count 0 2006.189.07:43:49.63#ibcon#read 3, iclass 20, count 0 2006.189.07:43:49.63#ibcon#about to read 4, iclass 20, count 0 2006.189.07:43:49.63#ibcon#read 4, iclass 20, count 0 2006.189.07:43:49.63#ibcon#about to read 5, iclass 20, count 0 2006.189.07:43:49.63#ibcon#read 5, iclass 20, count 0 2006.189.07:43:49.63#ibcon#about to read 6, iclass 20, count 0 2006.189.07:43:49.63#ibcon#read 6, iclass 20, count 0 2006.189.07:43:49.63#ibcon#end of sib2, iclass 20, count 0 2006.189.07:43:49.63#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:43:49.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:43:49.63#ibcon#[25=USB\r\n] 2006.189.07:43:49.63#ibcon#*before write, iclass 20, count 0 2006.189.07:43:49.63#ibcon#enter sib2, iclass 20, count 0 2006.189.07:43:49.63#ibcon#flushed, iclass 20, count 0 2006.189.07:43:49.63#ibcon#about to write, iclass 20, count 0 2006.189.07:43:49.63#ibcon#wrote, iclass 20, count 0 2006.189.07:43:49.63#ibcon#about to read 3, iclass 20, count 0 2006.189.07:43:49.66#ibcon#read 3, iclass 20, count 0 2006.189.07:43:49.66#ibcon#about to read 4, iclass 20, count 0 2006.189.07:43:49.66#ibcon#read 4, iclass 20, count 0 2006.189.07:43:49.66#ibcon#about to read 5, iclass 20, count 0 2006.189.07:43:49.66#ibcon#read 5, iclass 20, count 0 2006.189.07:43:49.66#ibcon#about to read 6, iclass 20, count 0 2006.189.07:43:49.66#ibcon#read 6, iclass 20, count 0 2006.189.07:43:49.66#ibcon#end of sib2, iclass 20, count 0 2006.189.07:43:49.66#ibcon#*after write, iclass 20, count 0 2006.189.07:43:49.66#ibcon#*before return 0, iclass 20, count 0 2006.189.07:43:49.66#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:49.66#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:49.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:43:49.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:43:49.66$vc4f8/valo=6,772.99 2006.189.07:43:49.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:43:49.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:43:49.66#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:49.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:49.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:49.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:49.66#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:43:49.66#ibcon#first serial, iclass 22, count 0 2006.189.07:43:49.66#ibcon#enter sib2, iclass 22, count 0 2006.189.07:43:49.66#ibcon#flushed, iclass 22, count 0 2006.189.07:43:49.66#ibcon#about to write, iclass 22, count 0 2006.189.07:43:49.66#ibcon#wrote, iclass 22, count 0 2006.189.07:43:49.66#ibcon#about to read 3, iclass 22, count 0 2006.189.07:43:49.68#ibcon#read 3, iclass 22, count 0 2006.189.07:43:49.68#ibcon#about to read 4, iclass 22, count 0 2006.189.07:43:49.68#ibcon#read 4, iclass 22, count 0 2006.189.07:43:49.68#ibcon#about to read 5, iclass 22, count 0 2006.189.07:43:49.68#ibcon#read 5, iclass 22, count 0 2006.189.07:43:49.68#ibcon#about to read 6, iclass 22, count 0 2006.189.07:43:49.68#ibcon#read 6, iclass 22, count 0 2006.189.07:43:49.68#ibcon#end of sib2, iclass 22, count 0 2006.189.07:43:49.68#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:43:49.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:43:49.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:43:49.68#ibcon#*before write, iclass 22, count 0 2006.189.07:43:49.68#ibcon#enter sib2, iclass 22, count 0 2006.189.07:43:49.68#ibcon#flushed, iclass 22, count 0 2006.189.07:43:49.68#ibcon#about to write, iclass 22, count 0 2006.189.07:43:49.68#ibcon#wrote, iclass 22, count 0 2006.189.07:43:49.68#ibcon#about to read 3, iclass 22, count 0 2006.189.07:43:49.72#ibcon#read 3, iclass 22, count 0 2006.189.07:43:49.72#ibcon#about to read 4, iclass 22, count 0 2006.189.07:43:49.72#ibcon#read 4, iclass 22, count 0 2006.189.07:43:49.72#ibcon#about to read 5, iclass 22, count 0 2006.189.07:43:49.72#ibcon#read 5, iclass 22, count 0 2006.189.07:43:49.72#ibcon#about to read 6, iclass 22, count 0 2006.189.07:43:49.72#ibcon#read 6, iclass 22, count 0 2006.189.07:43:49.72#ibcon#end of sib2, iclass 22, count 0 2006.189.07:43:49.72#ibcon#*after write, iclass 22, count 0 2006.189.07:43:49.72#ibcon#*before return 0, iclass 22, count 0 2006.189.07:43:49.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:49.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:49.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:43:49.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:43:49.72$vc4f8/va=6,6 2006.189.07:43:49.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:43:49.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:43:49.72#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:49.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:49.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:49.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:49.78#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:43:49.78#ibcon#first serial, iclass 24, count 2 2006.189.07:43:49.78#ibcon#enter sib2, iclass 24, count 2 2006.189.07:43:49.78#ibcon#flushed, iclass 24, count 2 2006.189.07:43:49.78#ibcon#about to write, iclass 24, count 2 2006.189.07:43:49.78#ibcon#wrote, iclass 24, count 2 2006.189.07:43:49.78#ibcon#about to read 3, iclass 24, count 2 2006.189.07:43:49.80#ibcon#read 3, iclass 24, count 2 2006.189.07:43:49.80#ibcon#about to read 4, iclass 24, count 2 2006.189.07:43:49.80#ibcon#read 4, iclass 24, count 2 2006.189.07:43:49.80#ibcon#about to read 5, iclass 24, count 2 2006.189.07:43:49.80#ibcon#read 5, iclass 24, count 2 2006.189.07:43:49.80#ibcon#about to read 6, iclass 24, count 2 2006.189.07:43:49.80#ibcon#read 6, iclass 24, count 2 2006.189.07:43:49.80#ibcon#end of sib2, iclass 24, count 2 2006.189.07:43:49.80#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:43:49.80#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:43:49.80#ibcon#[25=AT06-06\r\n] 2006.189.07:43:49.80#ibcon#*before write, iclass 24, count 2 2006.189.07:43:49.80#ibcon#enter sib2, iclass 24, count 2 2006.189.07:43:49.80#ibcon#flushed, iclass 24, count 2 2006.189.07:43:49.80#ibcon#about to write, iclass 24, count 2 2006.189.07:43:49.80#ibcon#wrote, iclass 24, count 2 2006.189.07:43:49.80#ibcon#about to read 3, iclass 24, count 2 2006.189.07:43:49.83#ibcon#read 3, iclass 24, count 2 2006.189.07:43:49.83#ibcon#about to read 4, iclass 24, count 2 2006.189.07:43:49.83#ibcon#read 4, iclass 24, count 2 2006.189.07:43:49.83#ibcon#about to read 5, iclass 24, count 2 2006.189.07:43:49.83#ibcon#read 5, iclass 24, count 2 2006.189.07:43:49.83#ibcon#about to read 6, iclass 24, count 2 2006.189.07:43:49.83#ibcon#read 6, iclass 24, count 2 2006.189.07:43:49.83#ibcon#end of sib2, iclass 24, count 2 2006.189.07:43:49.83#ibcon#*after write, iclass 24, count 2 2006.189.07:43:49.83#ibcon#*before return 0, iclass 24, count 2 2006.189.07:43:49.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:49.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:49.83#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:43:49.83#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:49.83#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:49.85#abcon#<5=/04 4.3 8.1 26.17 881008.9\r\n> 2006.189.07:43:49.87#abcon#{5=INTERFACE CLEAR} 2006.189.07:43:49.93#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:43:49.95#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:49.95#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:49.95#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:43:49.95#ibcon#first serial, iclass 24, count 0 2006.189.07:43:49.95#ibcon#enter sib2, iclass 24, count 0 2006.189.07:43:49.95#ibcon#flushed, iclass 24, count 0 2006.189.07:43:49.95#ibcon#about to write, iclass 24, count 0 2006.189.07:43:49.95#ibcon#wrote, iclass 24, count 0 2006.189.07:43:49.95#ibcon#about to read 3, iclass 24, count 0 2006.189.07:43:49.97#ibcon#read 3, iclass 24, count 0 2006.189.07:43:49.97#ibcon#about to read 4, iclass 24, count 0 2006.189.07:43:49.97#ibcon#read 4, iclass 24, count 0 2006.189.07:43:49.97#ibcon#about to read 5, iclass 24, count 0 2006.189.07:43:49.97#ibcon#read 5, iclass 24, count 0 2006.189.07:43:49.97#ibcon#about to read 6, iclass 24, count 0 2006.189.07:43:49.97#ibcon#read 6, iclass 24, count 0 2006.189.07:43:49.97#ibcon#end of sib2, iclass 24, count 0 2006.189.07:43:49.97#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:43:49.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:43:49.97#ibcon#[25=USB\r\n] 2006.189.07:43:49.97#ibcon#*before write, iclass 24, count 0 2006.189.07:43:49.97#ibcon#enter sib2, iclass 24, count 0 2006.189.07:43:49.97#ibcon#flushed, iclass 24, count 0 2006.189.07:43:49.97#ibcon#about to write, iclass 24, count 0 2006.189.07:43:49.97#ibcon#wrote, iclass 24, count 0 2006.189.07:43:49.97#ibcon#about to read 3, iclass 24, count 0 2006.189.07:43:50.00#ibcon#read 3, iclass 24, count 0 2006.189.07:43:50.00#ibcon#about to read 4, iclass 24, count 0 2006.189.07:43:50.00#ibcon#read 4, iclass 24, count 0 2006.189.07:43:50.00#ibcon#about to read 5, iclass 24, count 0 2006.189.07:43:50.00#ibcon#read 5, iclass 24, count 0 2006.189.07:43:50.00#ibcon#about to read 6, iclass 24, count 0 2006.189.07:43:50.00#ibcon#read 6, iclass 24, count 0 2006.189.07:43:50.00#ibcon#end of sib2, iclass 24, count 0 2006.189.07:43:50.00#ibcon#*after write, iclass 24, count 0 2006.189.07:43:50.00#ibcon#*before return 0, iclass 24, count 0 2006.189.07:43:50.00#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:50.00#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:50.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:43:50.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:43:50.00$vc4f8/valo=7,832.99 2006.189.07:43:50.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.07:43:50.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.07:43:50.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:50.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:43:50.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:43:50.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:43:50.00#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:43:50.00#ibcon#first serial, iclass 30, count 0 2006.189.07:43:50.00#ibcon#enter sib2, iclass 30, count 0 2006.189.07:43:50.00#ibcon#flushed, iclass 30, count 0 2006.189.07:43:50.00#ibcon#about to write, iclass 30, count 0 2006.189.07:43:50.00#ibcon#wrote, iclass 30, count 0 2006.189.07:43:50.00#ibcon#about to read 3, iclass 30, count 0 2006.189.07:43:50.02#ibcon#read 3, iclass 30, count 0 2006.189.07:43:50.02#ibcon#about to read 4, iclass 30, count 0 2006.189.07:43:50.02#ibcon#read 4, iclass 30, count 0 2006.189.07:43:50.02#ibcon#about to read 5, iclass 30, count 0 2006.189.07:43:50.02#ibcon#read 5, iclass 30, count 0 2006.189.07:43:50.02#ibcon#about to read 6, iclass 30, count 0 2006.189.07:43:50.02#ibcon#read 6, iclass 30, count 0 2006.189.07:43:50.02#ibcon#end of sib2, iclass 30, count 0 2006.189.07:43:50.02#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:43:50.02#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:43:50.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:43:50.02#ibcon#*before write, iclass 30, count 0 2006.189.07:43:50.02#ibcon#enter sib2, iclass 30, count 0 2006.189.07:43:50.02#ibcon#flushed, iclass 30, count 0 2006.189.07:43:50.02#ibcon#about to write, iclass 30, count 0 2006.189.07:43:50.02#ibcon#wrote, iclass 30, count 0 2006.189.07:43:50.02#ibcon#about to read 3, iclass 30, count 0 2006.189.07:43:50.06#ibcon#read 3, iclass 30, count 0 2006.189.07:43:50.06#ibcon#about to read 4, iclass 30, count 0 2006.189.07:43:50.06#ibcon#read 4, iclass 30, count 0 2006.189.07:43:50.06#ibcon#about to read 5, iclass 30, count 0 2006.189.07:43:50.06#ibcon#read 5, iclass 30, count 0 2006.189.07:43:50.06#ibcon#about to read 6, iclass 30, count 0 2006.189.07:43:50.06#ibcon#read 6, iclass 30, count 0 2006.189.07:43:50.06#ibcon#end of sib2, iclass 30, count 0 2006.189.07:43:50.06#ibcon#*after write, iclass 30, count 0 2006.189.07:43:50.06#ibcon#*before return 0, iclass 30, count 0 2006.189.07:43:50.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:43:50.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:43:50.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:43:50.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:43:50.06$vc4f8/va=7,6 2006.189.07:43:50.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.07:43:50.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.07:43:50.06#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:50.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:43:50.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:43:50.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:43:50.12#ibcon#enter wrdev, iclass 32, count 2 2006.189.07:43:50.12#ibcon#first serial, iclass 32, count 2 2006.189.07:43:50.12#ibcon#enter sib2, iclass 32, count 2 2006.189.07:43:50.12#ibcon#flushed, iclass 32, count 2 2006.189.07:43:50.12#ibcon#about to write, iclass 32, count 2 2006.189.07:43:50.12#ibcon#wrote, iclass 32, count 2 2006.189.07:43:50.12#ibcon#about to read 3, iclass 32, count 2 2006.189.07:43:50.14#ibcon#read 3, iclass 32, count 2 2006.189.07:43:50.14#ibcon#about to read 4, iclass 32, count 2 2006.189.07:43:50.14#ibcon#read 4, iclass 32, count 2 2006.189.07:43:50.14#ibcon#about to read 5, iclass 32, count 2 2006.189.07:43:50.14#ibcon#read 5, iclass 32, count 2 2006.189.07:43:50.14#ibcon#about to read 6, iclass 32, count 2 2006.189.07:43:50.14#ibcon#read 6, iclass 32, count 2 2006.189.07:43:50.14#ibcon#end of sib2, iclass 32, count 2 2006.189.07:43:50.14#ibcon#*mode == 0, iclass 32, count 2 2006.189.07:43:50.14#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.07:43:50.14#ibcon#[25=AT07-06\r\n] 2006.189.07:43:50.14#ibcon#*before write, iclass 32, count 2 2006.189.07:43:50.14#ibcon#enter sib2, iclass 32, count 2 2006.189.07:43:50.14#ibcon#flushed, iclass 32, count 2 2006.189.07:43:50.14#ibcon#about to write, iclass 32, count 2 2006.189.07:43:50.14#ibcon#wrote, iclass 32, count 2 2006.189.07:43:50.14#ibcon#about to read 3, iclass 32, count 2 2006.189.07:43:50.17#ibcon#read 3, iclass 32, count 2 2006.189.07:43:50.17#ibcon#about to read 4, iclass 32, count 2 2006.189.07:43:50.17#ibcon#read 4, iclass 32, count 2 2006.189.07:43:50.17#ibcon#about to read 5, iclass 32, count 2 2006.189.07:43:50.17#ibcon#read 5, iclass 32, count 2 2006.189.07:43:50.17#ibcon#about to read 6, iclass 32, count 2 2006.189.07:43:50.17#ibcon#read 6, iclass 32, count 2 2006.189.07:43:50.17#ibcon#end of sib2, iclass 32, count 2 2006.189.07:43:50.17#ibcon#*after write, iclass 32, count 2 2006.189.07:43:50.17#ibcon#*before return 0, iclass 32, count 2 2006.189.07:43:50.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:43:50.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:43:50.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.07:43:50.17#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:50.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:43:50.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:43:50.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:43:50.29#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:43:50.29#ibcon#first serial, iclass 32, count 0 2006.189.07:43:50.29#ibcon#enter sib2, iclass 32, count 0 2006.189.07:43:50.29#ibcon#flushed, iclass 32, count 0 2006.189.07:43:50.29#ibcon#about to write, iclass 32, count 0 2006.189.07:43:50.29#ibcon#wrote, iclass 32, count 0 2006.189.07:43:50.29#ibcon#about to read 3, iclass 32, count 0 2006.189.07:43:50.31#ibcon#read 3, iclass 32, count 0 2006.189.07:43:50.31#ibcon#about to read 4, iclass 32, count 0 2006.189.07:43:50.31#ibcon#read 4, iclass 32, count 0 2006.189.07:43:50.31#ibcon#about to read 5, iclass 32, count 0 2006.189.07:43:50.31#ibcon#read 5, iclass 32, count 0 2006.189.07:43:50.31#ibcon#about to read 6, iclass 32, count 0 2006.189.07:43:50.31#ibcon#read 6, iclass 32, count 0 2006.189.07:43:50.31#ibcon#end of sib2, iclass 32, count 0 2006.189.07:43:50.31#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:43:50.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:43:50.31#ibcon#[25=USB\r\n] 2006.189.07:43:50.31#ibcon#*before write, iclass 32, count 0 2006.189.07:43:50.31#ibcon#enter sib2, iclass 32, count 0 2006.189.07:43:50.31#ibcon#flushed, iclass 32, count 0 2006.189.07:43:50.31#ibcon#about to write, iclass 32, count 0 2006.189.07:43:50.31#ibcon#wrote, iclass 32, count 0 2006.189.07:43:50.31#ibcon#about to read 3, iclass 32, count 0 2006.189.07:43:50.34#ibcon#read 3, iclass 32, count 0 2006.189.07:43:50.34#ibcon#about to read 4, iclass 32, count 0 2006.189.07:43:50.34#ibcon#read 4, iclass 32, count 0 2006.189.07:43:50.34#ibcon#about to read 5, iclass 32, count 0 2006.189.07:43:50.34#ibcon#read 5, iclass 32, count 0 2006.189.07:43:50.34#ibcon#about to read 6, iclass 32, count 0 2006.189.07:43:50.34#ibcon#read 6, iclass 32, count 0 2006.189.07:43:50.34#ibcon#end of sib2, iclass 32, count 0 2006.189.07:43:50.34#ibcon#*after write, iclass 32, count 0 2006.189.07:43:50.34#ibcon#*before return 0, iclass 32, count 0 2006.189.07:43:50.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:43:50.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:43:50.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:43:50.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:43:50.34$vc4f8/valo=8,852.99 2006.189.07:43:50.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.07:43:50.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.07:43:50.34#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:50.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:43:50.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:43:50.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:43:50.34#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:43:50.34#ibcon#first serial, iclass 34, count 0 2006.189.07:43:50.34#ibcon#enter sib2, iclass 34, count 0 2006.189.07:43:50.34#ibcon#flushed, iclass 34, count 0 2006.189.07:43:50.34#ibcon#about to write, iclass 34, count 0 2006.189.07:43:50.34#ibcon#wrote, iclass 34, count 0 2006.189.07:43:50.34#ibcon#about to read 3, iclass 34, count 0 2006.189.07:43:50.36#ibcon#read 3, iclass 34, count 0 2006.189.07:43:50.36#ibcon#about to read 4, iclass 34, count 0 2006.189.07:43:50.36#ibcon#read 4, iclass 34, count 0 2006.189.07:43:50.36#ibcon#about to read 5, iclass 34, count 0 2006.189.07:43:50.36#ibcon#read 5, iclass 34, count 0 2006.189.07:43:50.36#ibcon#about to read 6, iclass 34, count 0 2006.189.07:43:50.36#ibcon#read 6, iclass 34, count 0 2006.189.07:43:50.36#ibcon#end of sib2, iclass 34, count 0 2006.189.07:43:50.36#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:43:50.36#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:43:50.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:43:50.36#ibcon#*before write, iclass 34, count 0 2006.189.07:43:50.36#ibcon#enter sib2, iclass 34, count 0 2006.189.07:43:50.36#ibcon#flushed, iclass 34, count 0 2006.189.07:43:50.36#ibcon#about to write, iclass 34, count 0 2006.189.07:43:50.36#ibcon#wrote, iclass 34, count 0 2006.189.07:43:50.36#ibcon#about to read 3, iclass 34, count 0 2006.189.07:43:50.40#ibcon#read 3, iclass 34, count 0 2006.189.07:43:50.40#ibcon#about to read 4, iclass 34, count 0 2006.189.07:43:50.40#ibcon#read 4, iclass 34, count 0 2006.189.07:43:50.40#ibcon#about to read 5, iclass 34, count 0 2006.189.07:43:50.40#ibcon#read 5, iclass 34, count 0 2006.189.07:43:50.40#ibcon#about to read 6, iclass 34, count 0 2006.189.07:43:50.40#ibcon#read 6, iclass 34, count 0 2006.189.07:43:50.40#ibcon#end of sib2, iclass 34, count 0 2006.189.07:43:50.40#ibcon#*after write, iclass 34, count 0 2006.189.07:43:50.40#ibcon#*before return 0, iclass 34, count 0 2006.189.07:43:50.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:43:50.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:43:50.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:43:50.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:43:50.40$vc4f8/va=8,6 2006.189.07:43:50.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.07:43:50.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.07:43:50.40#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:50.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:43:50.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:43:50.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:43:50.46#ibcon#enter wrdev, iclass 36, count 2 2006.189.07:43:50.46#ibcon#first serial, iclass 36, count 2 2006.189.07:43:50.46#ibcon#enter sib2, iclass 36, count 2 2006.189.07:43:50.46#ibcon#flushed, iclass 36, count 2 2006.189.07:43:50.46#ibcon#about to write, iclass 36, count 2 2006.189.07:43:50.46#ibcon#wrote, iclass 36, count 2 2006.189.07:43:50.46#ibcon#about to read 3, iclass 36, count 2 2006.189.07:43:50.48#ibcon#read 3, iclass 36, count 2 2006.189.07:43:50.48#ibcon#about to read 4, iclass 36, count 2 2006.189.07:43:50.48#ibcon#read 4, iclass 36, count 2 2006.189.07:43:50.48#ibcon#about to read 5, iclass 36, count 2 2006.189.07:43:50.48#ibcon#read 5, iclass 36, count 2 2006.189.07:43:50.48#ibcon#about to read 6, iclass 36, count 2 2006.189.07:43:50.48#ibcon#read 6, iclass 36, count 2 2006.189.07:43:50.48#ibcon#end of sib2, iclass 36, count 2 2006.189.07:43:50.48#ibcon#*mode == 0, iclass 36, count 2 2006.189.07:43:50.48#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.07:43:50.48#ibcon#[25=AT08-06\r\n] 2006.189.07:43:50.48#ibcon#*before write, iclass 36, count 2 2006.189.07:43:50.48#ibcon#enter sib2, iclass 36, count 2 2006.189.07:43:50.48#ibcon#flushed, iclass 36, count 2 2006.189.07:43:50.48#ibcon#about to write, iclass 36, count 2 2006.189.07:43:50.48#ibcon#wrote, iclass 36, count 2 2006.189.07:43:50.48#ibcon#about to read 3, iclass 36, count 2 2006.189.07:43:50.51#ibcon#read 3, iclass 36, count 2 2006.189.07:43:50.51#ibcon#about to read 4, iclass 36, count 2 2006.189.07:43:50.51#ibcon#read 4, iclass 36, count 2 2006.189.07:43:50.51#ibcon#about to read 5, iclass 36, count 2 2006.189.07:43:50.51#ibcon#read 5, iclass 36, count 2 2006.189.07:43:50.51#ibcon#about to read 6, iclass 36, count 2 2006.189.07:43:50.51#ibcon#read 6, iclass 36, count 2 2006.189.07:43:50.51#ibcon#end of sib2, iclass 36, count 2 2006.189.07:43:50.51#ibcon#*after write, iclass 36, count 2 2006.189.07:43:50.51#ibcon#*before return 0, iclass 36, count 2 2006.189.07:43:50.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:43:50.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:43:50.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.07:43:50.51#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:50.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:43:50.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:43:50.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:43:50.63#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:43:50.63#ibcon#first serial, iclass 36, count 0 2006.189.07:43:50.63#ibcon#enter sib2, iclass 36, count 0 2006.189.07:43:50.63#ibcon#flushed, iclass 36, count 0 2006.189.07:43:50.63#ibcon#about to write, iclass 36, count 0 2006.189.07:43:50.63#ibcon#wrote, iclass 36, count 0 2006.189.07:43:50.63#ibcon#about to read 3, iclass 36, count 0 2006.189.07:43:50.65#ibcon#read 3, iclass 36, count 0 2006.189.07:43:50.65#ibcon#about to read 4, iclass 36, count 0 2006.189.07:43:50.65#ibcon#read 4, iclass 36, count 0 2006.189.07:43:50.65#ibcon#about to read 5, iclass 36, count 0 2006.189.07:43:50.65#ibcon#read 5, iclass 36, count 0 2006.189.07:43:50.65#ibcon#about to read 6, iclass 36, count 0 2006.189.07:43:50.65#ibcon#read 6, iclass 36, count 0 2006.189.07:43:50.65#ibcon#end of sib2, iclass 36, count 0 2006.189.07:43:50.65#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:43:50.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:43:50.65#ibcon#[25=USB\r\n] 2006.189.07:43:50.65#ibcon#*before write, iclass 36, count 0 2006.189.07:43:50.65#ibcon#enter sib2, iclass 36, count 0 2006.189.07:43:50.65#ibcon#flushed, iclass 36, count 0 2006.189.07:43:50.65#ibcon#about to write, iclass 36, count 0 2006.189.07:43:50.65#ibcon#wrote, iclass 36, count 0 2006.189.07:43:50.65#ibcon#about to read 3, iclass 36, count 0 2006.189.07:43:50.68#ibcon#read 3, iclass 36, count 0 2006.189.07:43:50.68#ibcon#about to read 4, iclass 36, count 0 2006.189.07:43:50.68#ibcon#read 4, iclass 36, count 0 2006.189.07:43:50.68#ibcon#about to read 5, iclass 36, count 0 2006.189.07:43:50.68#ibcon#read 5, iclass 36, count 0 2006.189.07:43:50.68#ibcon#about to read 6, iclass 36, count 0 2006.189.07:43:50.68#ibcon#read 6, iclass 36, count 0 2006.189.07:43:50.68#ibcon#end of sib2, iclass 36, count 0 2006.189.07:43:50.68#ibcon#*after write, iclass 36, count 0 2006.189.07:43:50.68#ibcon#*before return 0, iclass 36, count 0 2006.189.07:43:50.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:43:50.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:43:50.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:43:50.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:43:50.68$vc4f8/vblo=1,632.99 2006.189.07:43:50.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.07:43:50.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.07:43:50.68#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:50.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:50.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:50.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:50.68#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:43:50.68#ibcon#first serial, iclass 38, count 0 2006.189.07:43:50.68#ibcon#enter sib2, iclass 38, count 0 2006.189.07:43:50.68#ibcon#flushed, iclass 38, count 0 2006.189.07:43:50.68#ibcon#about to write, iclass 38, count 0 2006.189.07:43:50.68#ibcon#wrote, iclass 38, count 0 2006.189.07:43:50.68#ibcon#about to read 3, iclass 38, count 0 2006.189.07:43:50.70#ibcon#read 3, iclass 38, count 0 2006.189.07:43:50.70#ibcon#about to read 4, iclass 38, count 0 2006.189.07:43:50.70#ibcon#read 4, iclass 38, count 0 2006.189.07:43:50.70#ibcon#about to read 5, iclass 38, count 0 2006.189.07:43:50.70#ibcon#read 5, iclass 38, count 0 2006.189.07:43:50.70#ibcon#about to read 6, iclass 38, count 0 2006.189.07:43:50.70#ibcon#read 6, iclass 38, count 0 2006.189.07:43:50.70#ibcon#end of sib2, iclass 38, count 0 2006.189.07:43:50.70#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:43:50.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:43:50.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:43:50.70#ibcon#*before write, iclass 38, count 0 2006.189.07:43:50.70#ibcon#enter sib2, iclass 38, count 0 2006.189.07:43:50.70#ibcon#flushed, iclass 38, count 0 2006.189.07:43:50.70#ibcon#about to write, iclass 38, count 0 2006.189.07:43:50.70#ibcon#wrote, iclass 38, count 0 2006.189.07:43:50.70#ibcon#about to read 3, iclass 38, count 0 2006.189.07:43:50.74#ibcon#read 3, iclass 38, count 0 2006.189.07:43:50.74#ibcon#about to read 4, iclass 38, count 0 2006.189.07:43:50.74#ibcon#read 4, iclass 38, count 0 2006.189.07:43:50.74#ibcon#about to read 5, iclass 38, count 0 2006.189.07:43:50.74#ibcon#read 5, iclass 38, count 0 2006.189.07:43:50.74#ibcon#about to read 6, iclass 38, count 0 2006.189.07:43:50.74#ibcon#read 6, iclass 38, count 0 2006.189.07:43:50.74#ibcon#end of sib2, iclass 38, count 0 2006.189.07:43:50.74#ibcon#*after write, iclass 38, count 0 2006.189.07:43:50.74#ibcon#*before return 0, iclass 38, count 0 2006.189.07:43:50.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:50.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:43:50.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:43:50.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:43:50.74$vc4f8/vb=1,4 2006.189.07:43:50.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.07:43:50.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.07:43:50.74#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:50.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:50.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:50.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:50.74#ibcon#enter wrdev, iclass 40, count 2 2006.189.07:43:50.74#ibcon#first serial, iclass 40, count 2 2006.189.07:43:50.74#ibcon#enter sib2, iclass 40, count 2 2006.189.07:43:50.74#ibcon#flushed, iclass 40, count 2 2006.189.07:43:50.74#ibcon#about to write, iclass 40, count 2 2006.189.07:43:50.74#ibcon#wrote, iclass 40, count 2 2006.189.07:43:50.74#ibcon#about to read 3, iclass 40, count 2 2006.189.07:43:50.76#ibcon#read 3, iclass 40, count 2 2006.189.07:43:50.76#ibcon#about to read 4, iclass 40, count 2 2006.189.07:43:50.76#ibcon#read 4, iclass 40, count 2 2006.189.07:43:50.76#ibcon#about to read 5, iclass 40, count 2 2006.189.07:43:50.76#ibcon#read 5, iclass 40, count 2 2006.189.07:43:50.76#ibcon#about to read 6, iclass 40, count 2 2006.189.07:43:50.76#ibcon#read 6, iclass 40, count 2 2006.189.07:43:50.76#ibcon#end of sib2, iclass 40, count 2 2006.189.07:43:50.76#ibcon#*mode == 0, iclass 40, count 2 2006.189.07:43:50.76#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.07:43:50.76#ibcon#[27=AT01-04\r\n] 2006.189.07:43:50.76#ibcon#*before write, iclass 40, count 2 2006.189.07:43:50.76#ibcon#enter sib2, iclass 40, count 2 2006.189.07:43:50.76#ibcon#flushed, iclass 40, count 2 2006.189.07:43:50.76#ibcon#about to write, iclass 40, count 2 2006.189.07:43:50.76#ibcon#wrote, iclass 40, count 2 2006.189.07:43:50.76#ibcon#about to read 3, iclass 40, count 2 2006.189.07:43:50.79#ibcon#read 3, iclass 40, count 2 2006.189.07:43:50.79#ibcon#about to read 4, iclass 40, count 2 2006.189.07:43:50.79#ibcon#read 4, iclass 40, count 2 2006.189.07:43:50.79#ibcon#about to read 5, iclass 40, count 2 2006.189.07:43:50.79#ibcon#read 5, iclass 40, count 2 2006.189.07:43:50.79#ibcon#about to read 6, iclass 40, count 2 2006.189.07:43:50.79#ibcon#read 6, iclass 40, count 2 2006.189.07:43:50.79#ibcon#end of sib2, iclass 40, count 2 2006.189.07:43:50.79#ibcon#*after write, iclass 40, count 2 2006.189.07:43:50.79#ibcon#*before return 0, iclass 40, count 2 2006.189.07:43:50.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:50.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:43:50.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.07:43:50.79#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:50.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:50.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:50.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:50.91#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:43:50.91#ibcon#first serial, iclass 40, count 0 2006.189.07:43:50.91#ibcon#enter sib2, iclass 40, count 0 2006.189.07:43:50.91#ibcon#flushed, iclass 40, count 0 2006.189.07:43:50.91#ibcon#about to write, iclass 40, count 0 2006.189.07:43:50.91#ibcon#wrote, iclass 40, count 0 2006.189.07:43:50.91#ibcon#about to read 3, iclass 40, count 0 2006.189.07:43:50.93#ibcon#read 3, iclass 40, count 0 2006.189.07:43:50.93#ibcon#about to read 4, iclass 40, count 0 2006.189.07:43:50.93#ibcon#read 4, iclass 40, count 0 2006.189.07:43:50.93#ibcon#about to read 5, iclass 40, count 0 2006.189.07:43:50.93#ibcon#read 5, iclass 40, count 0 2006.189.07:43:50.93#ibcon#about to read 6, iclass 40, count 0 2006.189.07:43:50.93#ibcon#read 6, iclass 40, count 0 2006.189.07:43:50.93#ibcon#end of sib2, iclass 40, count 0 2006.189.07:43:50.93#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:43:50.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:43:50.93#ibcon#[27=USB\r\n] 2006.189.07:43:50.93#ibcon#*before write, iclass 40, count 0 2006.189.07:43:50.93#ibcon#enter sib2, iclass 40, count 0 2006.189.07:43:50.93#ibcon#flushed, iclass 40, count 0 2006.189.07:43:50.93#ibcon#about to write, iclass 40, count 0 2006.189.07:43:50.93#ibcon#wrote, iclass 40, count 0 2006.189.07:43:50.93#ibcon#about to read 3, iclass 40, count 0 2006.189.07:43:50.96#ibcon#read 3, iclass 40, count 0 2006.189.07:43:50.96#ibcon#about to read 4, iclass 40, count 0 2006.189.07:43:50.96#ibcon#read 4, iclass 40, count 0 2006.189.07:43:50.96#ibcon#about to read 5, iclass 40, count 0 2006.189.07:43:50.96#ibcon#read 5, iclass 40, count 0 2006.189.07:43:50.96#ibcon#about to read 6, iclass 40, count 0 2006.189.07:43:50.96#ibcon#read 6, iclass 40, count 0 2006.189.07:43:50.96#ibcon#end of sib2, iclass 40, count 0 2006.189.07:43:50.96#ibcon#*after write, iclass 40, count 0 2006.189.07:43:50.96#ibcon#*before return 0, iclass 40, count 0 2006.189.07:43:50.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:50.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:43:50.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:43:50.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:43:50.96$vc4f8/vblo=2,640.99 2006.189.07:43:50.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:43:50.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:43:50.96#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:50.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:50.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:50.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:50.96#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:43:50.96#ibcon#first serial, iclass 4, count 0 2006.189.07:43:50.96#ibcon#enter sib2, iclass 4, count 0 2006.189.07:43:50.96#ibcon#flushed, iclass 4, count 0 2006.189.07:43:50.96#ibcon#about to write, iclass 4, count 0 2006.189.07:43:50.96#ibcon#wrote, iclass 4, count 0 2006.189.07:43:50.96#ibcon#about to read 3, iclass 4, count 0 2006.189.07:43:50.98#ibcon#read 3, iclass 4, count 0 2006.189.07:43:50.98#ibcon#about to read 4, iclass 4, count 0 2006.189.07:43:50.98#ibcon#read 4, iclass 4, count 0 2006.189.07:43:50.98#ibcon#about to read 5, iclass 4, count 0 2006.189.07:43:50.98#ibcon#read 5, iclass 4, count 0 2006.189.07:43:50.98#ibcon#about to read 6, iclass 4, count 0 2006.189.07:43:50.98#ibcon#read 6, iclass 4, count 0 2006.189.07:43:50.98#ibcon#end of sib2, iclass 4, count 0 2006.189.07:43:50.98#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:43:50.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:43:50.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:43:50.98#ibcon#*before write, iclass 4, count 0 2006.189.07:43:50.98#ibcon#enter sib2, iclass 4, count 0 2006.189.07:43:50.98#ibcon#flushed, iclass 4, count 0 2006.189.07:43:50.98#ibcon#about to write, iclass 4, count 0 2006.189.07:43:50.98#ibcon#wrote, iclass 4, count 0 2006.189.07:43:50.98#ibcon#about to read 3, iclass 4, count 0 2006.189.07:43:51.02#ibcon#read 3, iclass 4, count 0 2006.189.07:43:51.02#ibcon#about to read 4, iclass 4, count 0 2006.189.07:43:51.02#ibcon#read 4, iclass 4, count 0 2006.189.07:43:51.02#ibcon#about to read 5, iclass 4, count 0 2006.189.07:43:51.02#ibcon#read 5, iclass 4, count 0 2006.189.07:43:51.02#ibcon#about to read 6, iclass 4, count 0 2006.189.07:43:51.02#ibcon#read 6, iclass 4, count 0 2006.189.07:43:51.02#ibcon#end of sib2, iclass 4, count 0 2006.189.07:43:51.02#ibcon#*after write, iclass 4, count 0 2006.189.07:43:51.02#ibcon#*before return 0, iclass 4, count 0 2006.189.07:43:51.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:51.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:43:51.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:43:51.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:43:51.02$vc4f8/vb=2,4 2006.189.07:43:51.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.07:43:51.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.07:43:51.02#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:51.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:51.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:51.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:51.08#ibcon#enter wrdev, iclass 6, count 2 2006.189.07:43:51.08#ibcon#first serial, iclass 6, count 2 2006.189.07:43:51.08#ibcon#enter sib2, iclass 6, count 2 2006.189.07:43:51.08#ibcon#flushed, iclass 6, count 2 2006.189.07:43:51.08#ibcon#about to write, iclass 6, count 2 2006.189.07:43:51.08#ibcon#wrote, iclass 6, count 2 2006.189.07:43:51.08#ibcon#about to read 3, iclass 6, count 2 2006.189.07:43:51.10#ibcon#read 3, iclass 6, count 2 2006.189.07:43:51.10#ibcon#about to read 4, iclass 6, count 2 2006.189.07:43:51.10#ibcon#read 4, iclass 6, count 2 2006.189.07:43:51.10#ibcon#about to read 5, iclass 6, count 2 2006.189.07:43:51.10#ibcon#read 5, iclass 6, count 2 2006.189.07:43:51.10#ibcon#about to read 6, iclass 6, count 2 2006.189.07:43:51.10#ibcon#read 6, iclass 6, count 2 2006.189.07:43:51.10#ibcon#end of sib2, iclass 6, count 2 2006.189.07:43:51.10#ibcon#*mode == 0, iclass 6, count 2 2006.189.07:43:51.10#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.07:43:51.10#ibcon#[27=AT02-04\r\n] 2006.189.07:43:51.10#ibcon#*before write, iclass 6, count 2 2006.189.07:43:51.10#ibcon#enter sib2, iclass 6, count 2 2006.189.07:43:51.10#ibcon#flushed, iclass 6, count 2 2006.189.07:43:51.10#ibcon#about to write, iclass 6, count 2 2006.189.07:43:51.10#ibcon#wrote, iclass 6, count 2 2006.189.07:43:51.10#ibcon#about to read 3, iclass 6, count 2 2006.189.07:43:51.13#ibcon#read 3, iclass 6, count 2 2006.189.07:43:51.13#ibcon#about to read 4, iclass 6, count 2 2006.189.07:43:51.13#ibcon#read 4, iclass 6, count 2 2006.189.07:43:51.13#ibcon#about to read 5, iclass 6, count 2 2006.189.07:43:51.13#ibcon#read 5, iclass 6, count 2 2006.189.07:43:51.13#ibcon#about to read 6, iclass 6, count 2 2006.189.07:43:51.13#ibcon#read 6, iclass 6, count 2 2006.189.07:43:51.13#ibcon#end of sib2, iclass 6, count 2 2006.189.07:43:51.13#ibcon#*after write, iclass 6, count 2 2006.189.07:43:51.13#ibcon#*before return 0, iclass 6, count 2 2006.189.07:43:51.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:51.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:43:51.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.07:43:51.13#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:51.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:51.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:51.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:51.25#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:43:51.25#ibcon#first serial, iclass 6, count 0 2006.189.07:43:51.25#ibcon#enter sib2, iclass 6, count 0 2006.189.07:43:51.25#ibcon#flushed, iclass 6, count 0 2006.189.07:43:51.25#ibcon#about to write, iclass 6, count 0 2006.189.07:43:51.25#ibcon#wrote, iclass 6, count 0 2006.189.07:43:51.25#ibcon#about to read 3, iclass 6, count 0 2006.189.07:43:51.27#ibcon#read 3, iclass 6, count 0 2006.189.07:43:51.27#ibcon#about to read 4, iclass 6, count 0 2006.189.07:43:51.27#ibcon#read 4, iclass 6, count 0 2006.189.07:43:51.27#ibcon#about to read 5, iclass 6, count 0 2006.189.07:43:51.27#ibcon#read 5, iclass 6, count 0 2006.189.07:43:51.27#ibcon#about to read 6, iclass 6, count 0 2006.189.07:43:51.27#ibcon#read 6, iclass 6, count 0 2006.189.07:43:51.27#ibcon#end of sib2, iclass 6, count 0 2006.189.07:43:51.27#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:43:51.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:43:51.27#ibcon#[27=USB\r\n] 2006.189.07:43:51.27#ibcon#*before write, iclass 6, count 0 2006.189.07:43:51.27#ibcon#enter sib2, iclass 6, count 0 2006.189.07:43:51.27#ibcon#flushed, iclass 6, count 0 2006.189.07:43:51.27#ibcon#about to write, iclass 6, count 0 2006.189.07:43:51.27#ibcon#wrote, iclass 6, count 0 2006.189.07:43:51.27#ibcon#about to read 3, iclass 6, count 0 2006.189.07:43:51.30#ibcon#read 3, iclass 6, count 0 2006.189.07:43:51.30#ibcon#about to read 4, iclass 6, count 0 2006.189.07:43:51.30#ibcon#read 4, iclass 6, count 0 2006.189.07:43:51.30#ibcon#about to read 5, iclass 6, count 0 2006.189.07:43:51.30#ibcon#read 5, iclass 6, count 0 2006.189.07:43:51.30#ibcon#about to read 6, iclass 6, count 0 2006.189.07:43:51.30#ibcon#read 6, iclass 6, count 0 2006.189.07:43:51.30#ibcon#end of sib2, iclass 6, count 0 2006.189.07:43:51.30#ibcon#*after write, iclass 6, count 0 2006.189.07:43:51.30#ibcon#*before return 0, iclass 6, count 0 2006.189.07:43:51.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:51.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:43:51.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:43:51.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:43:51.30$vc4f8/vblo=3,656.99 2006.189.07:43:51.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.07:43:51.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.07:43:51.30#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:51.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:51.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:51.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:51.30#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:43:51.30#ibcon#first serial, iclass 10, count 0 2006.189.07:43:51.30#ibcon#enter sib2, iclass 10, count 0 2006.189.07:43:51.30#ibcon#flushed, iclass 10, count 0 2006.189.07:43:51.30#ibcon#about to write, iclass 10, count 0 2006.189.07:43:51.30#ibcon#wrote, iclass 10, count 0 2006.189.07:43:51.30#ibcon#about to read 3, iclass 10, count 0 2006.189.07:43:51.32#ibcon#read 3, iclass 10, count 0 2006.189.07:43:51.32#ibcon#about to read 4, iclass 10, count 0 2006.189.07:43:51.32#ibcon#read 4, iclass 10, count 0 2006.189.07:43:51.32#ibcon#about to read 5, iclass 10, count 0 2006.189.07:43:51.32#ibcon#read 5, iclass 10, count 0 2006.189.07:43:51.32#ibcon#about to read 6, iclass 10, count 0 2006.189.07:43:51.32#ibcon#read 6, iclass 10, count 0 2006.189.07:43:51.32#ibcon#end of sib2, iclass 10, count 0 2006.189.07:43:51.32#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:43:51.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:43:51.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:43:51.32#ibcon#*before write, iclass 10, count 0 2006.189.07:43:51.32#ibcon#enter sib2, iclass 10, count 0 2006.189.07:43:51.32#ibcon#flushed, iclass 10, count 0 2006.189.07:43:51.32#ibcon#about to write, iclass 10, count 0 2006.189.07:43:51.32#ibcon#wrote, iclass 10, count 0 2006.189.07:43:51.32#ibcon#about to read 3, iclass 10, count 0 2006.189.07:43:51.36#ibcon#read 3, iclass 10, count 0 2006.189.07:43:51.36#ibcon#about to read 4, iclass 10, count 0 2006.189.07:43:51.36#ibcon#read 4, iclass 10, count 0 2006.189.07:43:51.36#ibcon#about to read 5, iclass 10, count 0 2006.189.07:43:51.36#ibcon#read 5, iclass 10, count 0 2006.189.07:43:51.36#ibcon#about to read 6, iclass 10, count 0 2006.189.07:43:51.36#ibcon#read 6, iclass 10, count 0 2006.189.07:43:51.36#ibcon#end of sib2, iclass 10, count 0 2006.189.07:43:51.36#ibcon#*after write, iclass 10, count 0 2006.189.07:43:51.36#ibcon#*before return 0, iclass 10, count 0 2006.189.07:43:51.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:51.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:43:51.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:43:51.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:43:51.36$vc4f8/vb=3,4 2006.189.07:43:51.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.07:43:51.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.07:43:51.36#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:51.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:51.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:51.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:51.42#ibcon#enter wrdev, iclass 12, count 2 2006.189.07:43:51.42#ibcon#first serial, iclass 12, count 2 2006.189.07:43:51.42#ibcon#enter sib2, iclass 12, count 2 2006.189.07:43:51.42#ibcon#flushed, iclass 12, count 2 2006.189.07:43:51.42#ibcon#about to write, iclass 12, count 2 2006.189.07:43:51.42#ibcon#wrote, iclass 12, count 2 2006.189.07:43:51.42#ibcon#about to read 3, iclass 12, count 2 2006.189.07:43:51.44#ibcon#read 3, iclass 12, count 2 2006.189.07:43:51.44#ibcon#about to read 4, iclass 12, count 2 2006.189.07:43:51.44#ibcon#read 4, iclass 12, count 2 2006.189.07:43:51.44#ibcon#about to read 5, iclass 12, count 2 2006.189.07:43:51.44#ibcon#read 5, iclass 12, count 2 2006.189.07:43:51.44#ibcon#about to read 6, iclass 12, count 2 2006.189.07:43:51.44#ibcon#read 6, iclass 12, count 2 2006.189.07:43:51.44#ibcon#end of sib2, iclass 12, count 2 2006.189.07:43:51.44#ibcon#*mode == 0, iclass 12, count 2 2006.189.07:43:51.44#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.07:43:51.44#ibcon#[27=AT03-04\r\n] 2006.189.07:43:51.44#ibcon#*before write, iclass 12, count 2 2006.189.07:43:51.44#ibcon#enter sib2, iclass 12, count 2 2006.189.07:43:51.44#ibcon#flushed, iclass 12, count 2 2006.189.07:43:51.44#ibcon#about to write, iclass 12, count 2 2006.189.07:43:51.44#ibcon#wrote, iclass 12, count 2 2006.189.07:43:51.44#ibcon#about to read 3, iclass 12, count 2 2006.189.07:43:51.47#ibcon#read 3, iclass 12, count 2 2006.189.07:43:51.47#ibcon#about to read 4, iclass 12, count 2 2006.189.07:43:51.47#ibcon#read 4, iclass 12, count 2 2006.189.07:43:51.47#ibcon#about to read 5, iclass 12, count 2 2006.189.07:43:51.47#ibcon#read 5, iclass 12, count 2 2006.189.07:43:51.47#ibcon#about to read 6, iclass 12, count 2 2006.189.07:43:51.47#ibcon#read 6, iclass 12, count 2 2006.189.07:43:51.47#ibcon#end of sib2, iclass 12, count 2 2006.189.07:43:51.47#ibcon#*after write, iclass 12, count 2 2006.189.07:43:51.47#ibcon#*before return 0, iclass 12, count 2 2006.189.07:43:51.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:51.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:43:51.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.07:43:51.47#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:51.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:51.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:51.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:51.59#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:43:51.59#ibcon#first serial, iclass 12, count 0 2006.189.07:43:51.59#ibcon#enter sib2, iclass 12, count 0 2006.189.07:43:51.59#ibcon#flushed, iclass 12, count 0 2006.189.07:43:51.59#ibcon#about to write, iclass 12, count 0 2006.189.07:43:51.59#ibcon#wrote, iclass 12, count 0 2006.189.07:43:51.59#ibcon#about to read 3, iclass 12, count 0 2006.189.07:43:51.61#ibcon#read 3, iclass 12, count 0 2006.189.07:43:51.61#ibcon#about to read 4, iclass 12, count 0 2006.189.07:43:51.61#ibcon#read 4, iclass 12, count 0 2006.189.07:43:51.61#ibcon#about to read 5, iclass 12, count 0 2006.189.07:43:51.61#ibcon#read 5, iclass 12, count 0 2006.189.07:43:51.61#ibcon#about to read 6, iclass 12, count 0 2006.189.07:43:51.61#ibcon#read 6, iclass 12, count 0 2006.189.07:43:51.61#ibcon#end of sib2, iclass 12, count 0 2006.189.07:43:51.61#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:43:51.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:43:51.61#ibcon#[27=USB\r\n] 2006.189.07:43:51.61#ibcon#*before write, iclass 12, count 0 2006.189.07:43:51.61#ibcon#enter sib2, iclass 12, count 0 2006.189.07:43:51.61#ibcon#flushed, iclass 12, count 0 2006.189.07:43:51.61#ibcon#about to write, iclass 12, count 0 2006.189.07:43:51.61#ibcon#wrote, iclass 12, count 0 2006.189.07:43:51.61#ibcon#about to read 3, iclass 12, count 0 2006.189.07:43:51.64#ibcon#read 3, iclass 12, count 0 2006.189.07:43:51.64#ibcon#about to read 4, iclass 12, count 0 2006.189.07:43:51.64#ibcon#read 4, iclass 12, count 0 2006.189.07:43:51.64#ibcon#about to read 5, iclass 12, count 0 2006.189.07:43:51.64#ibcon#read 5, iclass 12, count 0 2006.189.07:43:51.64#ibcon#about to read 6, iclass 12, count 0 2006.189.07:43:51.64#ibcon#read 6, iclass 12, count 0 2006.189.07:43:51.64#ibcon#end of sib2, iclass 12, count 0 2006.189.07:43:51.64#ibcon#*after write, iclass 12, count 0 2006.189.07:43:51.64#ibcon#*before return 0, iclass 12, count 0 2006.189.07:43:51.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:51.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:43:51.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:43:51.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:43:51.64$vc4f8/vblo=4,712.99 2006.189.07:43:51.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.07:43:51.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.07:43:51.64#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:51.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:51.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:51.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:51.64#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:43:51.64#ibcon#first serial, iclass 14, count 0 2006.189.07:43:51.64#ibcon#enter sib2, iclass 14, count 0 2006.189.07:43:51.64#ibcon#flushed, iclass 14, count 0 2006.189.07:43:51.64#ibcon#about to write, iclass 14, count 0 2006.189.07:43:51.64#ibcon#wrote, iclass 14, count 0 2006.189.07:43:51.64#ibcon#about to read 3, iclass 14, count 0 2006.189.07:43:51.66#ibcon#read 3, iclass 14, count 0 2006.189.07:43:51.66#ibcon#about to read 4, iclass 14, count 0 2006.189.07:43:51.66#ibcon#read 4, iclass 14, count 0 2006.189.07:43:51.66#ibcon#about to read 5, iclass 14, count 0 2006.189.07:43:51.66#ibcon#read 5, iclass 14, count 0 2006.189.07:43:51.66#ibcon#about to read 6, iclass 14, count 0 2006.189.07:43:51.66#ibcon#read 6, iclass 14, count 0 2006.189.07:43:51.66#ibcon#end of sib2, iclass 14, count 0 2006.189.07:43:51.66#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:43:51.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:43:51.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:43:51.66#ibcon#*before write, iclass 14, count 0 2006.189.07:43:51.66#ibcon#enter sib2, iclass 14, count 0 2006.189.07:43:51.66#ibcon#flushed, iclass 14, count 0 2006.189.07:43:51.66#ibcon#about to write, iclass 14, count 0 2006.189.07:43:51.66#ibcon#wrote, iclass 14, count 0 2006.189.07:43:51.66#ibcon#about to read 3, iclass 14, count 0 2006.189.07:43:51.70#ibcon#read 3, iclass 14, count 0 2006.189.07:43:51.70#ibcon#about to read 4, iclass 14, count 0 2006.189.07:43:51.70#ibcon#read 4, iclass 14, count 0 2006.189.07:43:51.70#ibcon#about to read 5, iclass 14, count 0 2006.189.07:43:51.70#ibcon#read 5, iclass 14, count 0 2006.189.07:43:51.70#ibcon#about to read 6, iclass 14, count 0 2006.189.07:43:51.70#ibcon#read 6, iclass 14, count 0 2006.189.07:43:51.70#ibcon#end of sib2, iclass 14, count 0 2006.189.07:43:51.70#ibcon#*after write, iclass 14, count 0 2006.189.07:43:51.70#ibcon#*before return 0, iclass 14, count 0 2006.189.07:43:51.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:51.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:43:51.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:43:51.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:43:51.70$vc4f8/vb=4,4 2006.189.07:43:51.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.07:43:51.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.07:43:51.70#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:51.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:51.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:51.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:51.76#ibcon#enter wrdev, iclass 16, count 2 2006.189.07:43:51.76#ibcon#first serial, iclass 16, count 2 2006.189.07:43:51.76#ibcon#enter sib2, iclass 16, count 2 2006.189.07:43:51.76#ibcon#flushed, iclass 16, count 2 2006.189.07:43:51.76#ibcon#about to write, iclass 16, count 2 2006.189.07:43:51.76#ibcon#wrote, iclass 16, count 2 2006.189.07:43:51.76#ibcon#about to read 3, iclass 16, count 2 2006.189.07:43:51.78#ibcon#read 3, iclass 16, count 2 2006.189.07:43:51.78#ibcon#about to read 4, iclass 16, count 2 2006.189.07:43:51.78#ibcon#read 4, iclass 16, count 2 2006.189.07:43:51.78#ibcon#about to read 5, iclass 16, count 2 2006.189.07:43:51.78#ibcon#read 5, iclass 16, count 2 2006.189.07:43:51.78#ibcon#about to read 6, iclass 16, count 2 2006.189.07:43:51.78#ibcon#read 6, iclass 16, count 2 2006.189.07:43:51.78#ibcon#end of sib2, iclass 16, count 2 2006.189.07:43:51.78#ibcon#*mode == 0, iclass 16, count 2 2006.189.07:43:51.78#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.07:43:51.78#ibcon#[27=AT04-04\r\n] 2006.189.07:43:51.78#ibcon#*before write, iclass 16, count 2 2006.189.07:43:51.78#ibcon#enter sib2, iclass 16, count 2 2006.189.07:43:51.78#ibcon#flushed, iclass 16, count 2 2006.189.07:43:51.78#ibcon#about to write, iclass 16, count 2 2006.189.07:43:51.78#ibcon#wrote, iclass 16, count 2 2006.189.07:43:51.78#ibcon#about to read 3, iclass 16, count 2 2006.189.07:43:51.81#ibcon#read 3, iclass 16, count 2 2006.189.07:43:51.81#ibcon#about to read 4, iclass 16, count 2 2006.189.07:43:51.81#ibcon#read 4, iclass 16, count 2 2006.189.07:43:51.81#ibcon#about to read 5, iclass 16, count 2 2006.189.07:43:51.81#ibcon#read 5, iclass 16, count 2 2006.189.07:43:51.81#ibcon#about to read 6, iclass 16, count 2 2006.189.07:43:51.81#ibcon#read 6, iclass 16, count 2 2006.189.07:43:51.81#ibcon#end of sib2, iclass 16, count 2 2006.189.07:43:51.81#ibcon#*after write, iclass 16, count 2 2006.189.07:43:51.81#ibcon#*before return 0, iclass 16, count 2 2006.189.07:43:51.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:51.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:43:51.81#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.07:43:51.81#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:51.81#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:51.93#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:51.93#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:51.93#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:43:51.93#ibcon#first serial, iclass 16, count 0 2006.189.07:43:51.93#ibcon#enter sib2, iclass 16, count 0 2006.189.07:43:51.93#ibcon#flushed, iclass 16, count 0 2006.189.07:43:51.93#ibcon#about to write, iclass 16, count 0 2006.189.07:43:51.93#ibcon#wrote, iclass 16, count 0 2006.189.07:43:51.93#ibcon#about to read 3, iclass 16, count 0 2006.189.07:43:51.95#ibcon#read 3, iclass 16, count 0 2006.189.07:43:51.95#ibcon#about to read 4, iclass 16, count 0 2006.189.07:43:51.95#ibcon#read 4, iclass 16, count 0 2006.189.07:43:51.95#ibcon#about to read 5, iclass 16, count 0 2006.189.07:43:51.95#ibcon#read 5, iclass 16, count 0 2006.189.07:43:51.95#ibcon#about to read 6, iclass 16, count 0 2006.189.07:43:51.95#ibcon#read 6, iclass 16, count 0 2006.189.07:43:51.95#ibcon#end of sib2, iclass 16, count 0 2006.189.07:43:51.95#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:43:51.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:43:51.95#ibcon#[27=USB\r\n] 2006.189.07:43:51.95#ibcon#*before write, iclass 16, count 0 2006.189.07:43:51.95#ibcon#enter sib2, iclass 16, count 0 2006.189.07:43:51.95#ibcon#flushed, iclass 16, count 0 2006.189.07:43:51.95#ibcon#about to write, iclass 16, count 0 2006.189.07:43:51.95#ibcon#wrote, iclass 16, count 0 2006.189.07:43:51.95#ibcon#about to read 3, iclass 16, count 0 2006.189.07:43:51.98#ibcon#read 3, iclass 16, count 0 2006.189.07:43:51.98#ibcon#about to read 4, iclass 16, count 0 2006.189.07:43:51.98#ibcon#read 4, iclass 16, count 0 2006.189.07:43:51.98#ibcon#about to read 5, iclass 16, count 0 2006.189.07:43:51.98#ibcon#read 5, iclass 16, count 0 2006.189.07:43:51.98#ibcon#about to read 6, iclass 16, count 0 2006.189.07:43:51.98#ibcon#read 6, iclass 16, count 0 2006.189.07:43:51.98#ibcon#end of sib2, iclass 16, count 0 2006.189.07:43:51.98#ibcon#*after write, iclass 16, count 0 2006.189.07:43:51.98#ibcon#*before return 0, iclass 16, count 0 2006.189.07:43:51.98#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:51.98#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:43:51.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:43:51.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:43:51.98$vc4f8/vblo=5,744.99 2006.189.07:43:51.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.07:43:51.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.07:43:51.98#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:51.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:51.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:51.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:51.98#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:43:51.98#ibcon#first serial, iclass 18, count 0 2006.189.07:43:51.98#ibcon#enter sib2, iclass 18, count 0 2006.189.07:43:51.98#ibcon#flushed, iclass 18, count 0 2006.189.07:43:51.98#ibcon#about to write, iclass 18, count 0 2006.189.07:43:51.98#ibcon#wrote, iclass 18, count 0 2006.189.07:43:51.98#ibcon#about to read 3, iclass 18, count 0 2006.189.07:43:52.00#ibcon#read 3, iclass 18, count 0 2006.189.07:43:52.00#ibcon#about to read 4, iclass 18, count 0 2006.189.07:43:52.00#ibcon#read 4, iclass 18, count 0 2006.189.07:43:52.00#ibcon#about to read 5, iclass 18, count 0 2006.189.07:43:52.00#ibcon#read 5, iclass 18, count 0 2006.189.07:43:52.00#ibcon#about to read 6, iclass 18, count 0 2006.189.07:43:52.00#ibcon#read 6, iclass 18, count 0 2006.189.07:43:52.00#ibcon#end of sib2, iclass 18, count 0 2006.189.07:43:52.00#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:43:52.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:43:52.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:43:52.00#ibcon#*before write, iclass 18, count 0 2006.189.07:43:52.00#ibcon#enter sib2, iclass 18, count 0 2006.189.07:43:52.00#ibcon#flushed, iclass 18, count 0 2006.189.07:43:52.00#ibcon#about to write, iclass 18, count 0 2006.189.07:43:52.00#ibcon#wrote, iclass 18, count 0 2006.189.07:43:52.00#ibcon#about to read 3, iclass 18, count 0 2006.189.07:43:52.04#ibcon#read 3, iclass 18, count 0 2006.189.07:43:52.04#ibcon#about to read 4, iclass 18, count 0 2006.189.07:43:52.04#ibcon#read 4, iclass 18, count 0 2006.189.07:43:52.04#ibcon#about to read 5, iclass 18, count 0 2006.189.07:43:52.04#ibcon#read 5, iclass 18, count 0 2006.189.07:43:52.04#ibcon#about to read 6, iclass 18, count 0 2006.189.07:43:52.04#ibcon#read 6, iclass 18, count 0 2006.189.07:43:52.04#ibcon#end of sib2, iclass 18, count 0 2006.189.07:43:52.04#ibcon#*after write, iclass 18, count 0 2006.189.07:43:52.04#ibcon#*before return 0, iclass 18, count 0 2006.189.07:43:52.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:52.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:43:52.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:43:52.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:43:52.04$vc4f8/vb=5,4 2006.189.07:43:52.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:43:52.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:43:52.04#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:52.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:52.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:52.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:52.10#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:43:52.10#ibcon#first serial, iclass 20, count 2 2006.189.07:43:52.10#ibcon#enter sib2, iclass 20, count 2 2006.189.07:43:52.10#ibcon#flushed, iclass 20, count 2 2006.189.07:43:52.10#ibcon#about to write, iclass 20, count 2 2006.189.07:43:52.10#ibcon#wrote, iclass 20, count 2 2006.189.07:43:52.10#ibcon#about to read 3, iclass 20, count 2 2006.189.07:43:52.12#ibcon#read 3, iclass 20, count 2 2006.189.07:43:52.12#ibcon#about to read 4, iclass 20, count 2 2006.189.07:43:52.12#ibcon#read 4, iclass 20, count 2 2006.189.07:43:52.12#ibcon#about to read 5, iclass 20, count 2 2006.189.07:43:52.12#ibcon#read 5, iclass 20, count 2 2006.189.07:43:52.12#ibcon#about to read 6, iclass 20, count 2 2006.189.07:43:52.12#ibcon#read 6, iclass 20, count 2 2006.189.07:43:52.12#ibcon#end of sib2, iclass 20, count 2 2006.189.07:43:52.12#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:43:52.12#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:43:52.12#ibcon#[27=AT05-04\r\n] 2006.189.07:43:52.12#ibcon#*before write, iclass 20, count 2 2006.189.07:43:52.12#ibcon#enter sib2, iclass 20, count 2 2006.189.07:43:52.12#ibcon#flushed, iclass 20, count 2 2006.189.07:43:52.12#ibcon#about to write, iclass 20, count 2 2006.189.07:43:52.12#ibcon#wrote, iclass 20, count 2 2006.189.07:43:52.12#ibcon#about to read 3, iclass 20, count 2 2006.189.07:43:52.15#ibcon#read 3, iclass 20, count 2 2006.189.07:43:52.15#ibcon#about to read 4, iclass 20, count 2 2006.189.07:43:52.15#ibcon#read 4, iclass 20, count 2 2006.189.07:43:52.15#ibcon#about to read 5, iclass 20, count 2 2006.189.07:43:52.15#ibcon#read 5, iclass 20, count 2 2006.189.07:43:52.15#ibcon#about to read 6, iclass 20, count 2 2006.189.07:43:52.15#ibcon#read 6, iclass 20, count 2 2006.189.07:43:52.15#ibcon#end of sib2, iclass 20, count 2 2006.189.07:43:52.15#ibcon#*after write, iclass 20, count 2 2006.189.07:43:52.15#ibcon#*before return 0, iclass 20, count 2 2006.189.07:43:52.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:52.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:43:52.15#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:43:52.15#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:52.15#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:52.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:52.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:52.27#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:43:52.27#ibcon#first serial, iclass 20, count 0 2006.189.07:43:52.27#ibcon#enter sib2, iclass 20, count 0 2006.189.07:43:52.27#ibcon#flushed, iclass 20, count 0 2006.189.07:43:52.27#ibcon#about to write, iclass 20, count 0 2006.189.07:43:52.27#ibcon#wrote, iclass 20, count 0 2006.189.07:43:52.27#ibcon#about to read 3, iclass 20, count 0 2006.189.07:43:52.29#ibcon#read 3, iclass 20, count 0 2006.189.07:43:52.29#ibcon#about to read 4, iclass 20, count 0 2006.189.07:43:52.29#ibcon#read 4, iclass 20, count 0 2006.189.07:43:52.29#ibcon#about to read 5, iclass 20, count 0 2006.189.07:43:52.29#ibcon#read 5, iclass 20, count 0 2006.189.07:43:52.29#ibcon#about to read 6, iclass 20, count 0 2006.189.07:43:52.29#ibcon#read 6, iclass 20, count 0 2006.189.07:43:52.29#ibcon#end of sib2, iclass 20, count 0 2006.189.07:43:52.29#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:43:52.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:43:52.29#ibcon#[27=USB\r\n] 2006.189.07:43:52.29#ibcon#*before write, iclass 20, count 0 2006.189.07:43:52.29#ibcon#enter sib2, iclass 20, count 0 2006.189.07:43:52.29#ibcon#flushed, iclass 20, count 0 2006.189.07:43:52.29#ibcon#about to write, iclass 20, count 0 2006.189.07:43:52.29#ibcon#wrote, iclass 20, count 0 2006.189.07:43:52.29#ibcon#about to read 3, iclass 20, count 0 2006.189.07:43:52.32#ibcon#read 3, iclass 20, count 0 2006.189.07:43:52.32#ibcon#about to read 4, iclass 20, count 0 2006.189.07:43:52.32#ibcon#read 4, iclass 20, count 0 2006.189.07:43:52.32#ibcon#about to read 5, iclass 20, count 0 2006.189.07:43:52.32#ibcon#read 5, iclass 20, count 0 2006.189.07:43:52.32#ibcon#about to read 6, iclass 20, count 0 2006.189.07:43:52.32#ibcon#read 6, iclass 20, count 0 2006.189.07:43:52.32#ibcon#end of sib2, iclass 20, count 0 2006.189.07:43:52.32#ibcon#*after write, iclass 20, count 0 2006.189.07:43:52.32#ibcon#*before return 0, iclass 20, count 0 2006.189.07:43:52.32#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:52.32#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:43:52.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:43:52.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:43:52.32$vc4f8/vblo=6,752.99 2006.189.07:43:52.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:43:52.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:43:52.32#ibcon#ireg 17 cls_cnt 0 2006.189.07:43:52.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:52.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:52.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:52.32#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:43:52.32#ibcon#first serial, iclass 22, count 0 2006.189.07:43:52.32#ibcon#enter sib2, iclass 22, count 0 2006.189.07:43:52.32#ibcon#flushed, iclass 22, count 0 2006.189.07:43:52.32#ibcon#about to write, iclass 22, count 0 2006.189.07:43:52.32#ibcon#wrote, iclass 22, count 0 2006.189.07:43:52.32#ibcon#about to read 3, iclass 22, count 0 2006.189.07:43:52.34#ibcon#read 3, iclass 22, count 0 2006.189.07:43:52.34#ibcon#about to read 4, iclass 22, count 0 2006.189.07:43:52.34#ibcon#read 4, iclass 22, count 0 2006.189.07:43:52.34#ibcon#about to read 5, iclass 22, count 0 2006.189.07:43:52.34#ibcon#read 5, iclass 22, count 0 2006.189.07:43:52.34#ibcon#about to read 6, iclass 22, count 0 2006.189.07:43:52.34#ibcon#read 6, iclass 22, count 0 2006.189.07:43:52.34#ibcon#end of sib2, iclass 22, count 0 2006.189.07:43:52.34#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:43:52.34#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:43:52.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:43:52.34#ibcon#*before write, iclass 22, count 0 2006.189.07:43:52.34#ibcon#enter sib2, iclass 22, count 0 2006.189.07:43:52.34#ibcon#flushed, iclass 22, count 0 2006.189.07:43:52.34#ibcon#about to write, iclass 22, count 0 2006.189.07:43:52.34#ibcon#wrote, iclass 22, count 0 2006.189.07:43:52.34#ibcon#about to read 3, iclass 22, count 0 2006.189.07:43:52.38#ibcon#read 3, iclass 22, count 0 2006.189.07:43:52.38#ibcon#about to read 4, iclass 22, count 0 2006.189.07:43:52.38#ibcon#read 4, iclass 22, count 0 2006.189.07:43:52.38#ibcon#about to read 5, iclass 22, count 0 2006.189.07:43:52.38#ibcon#read 5, iclass 22, count 0 2006.189.07:43:52.38#ibcon#about to read 6, iclass 22, count 0 2006.189.07:43:52.38#ibcon#read 6, iclass 22, count 0 2006.189.07:43:52.38#ibcon#end of sib2, iclass 22, count 0 2006.189.07:43:52.38#ibcon#*after write, iclass 22, count 0 2006.189.07:43:52.38#ibcon#*before return 0, iclass 22, count 0 2006.189.07:43:52.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:52.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:43:52.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:43:52.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:43:52.38$vc4f8/vb=6,4 2006.189.07:43:52.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:43:52.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:43:52.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:43:52.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:52.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:52.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:52.44#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:43:52.44#ibcon#first serial, iclass 24, count 2 2006.189.07:43:52.44#ibcon#enter sib2, iclass 24, count 2 2006.189.07:43:52.44#ibcon#flushed, iclass 24, count 2 2006.189.07:43:52.44#ibcon#about to write, iclass 24, count 2 2006.189.07:43:52.44#ibcon#wrote, iclass 24, count 2 2006.189.07:43:52.44#ibcon#about to read 3, iclass 24, count 2 2006.189.07:43:52.46#ibcon#read 3, iclass 24, count 2 2006.189.07:43:52.46#ibcon#about to read 4, iclass 24, count 2 2006.189.07:43:52.46#ibcon#read 4, iclass 24, count 2 2006.189.07:43:52.46#ibcon#about to read 5, iclass 24, count 2 2006.189.07:43:52.46#ibcon#read 5, iclass 24, count 2 2006.189.07:43:52.46#ibcon#about to read 6, iclass 24, count 2 2006.189.07:43:52.46#ibcon#read 6, iclass 24, count 2 2006.189.07:43:52.46#ibcon#end of sib2, iclass 24, count 2 2006.189.07:43:52.46#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:43:52.46#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:43:52.46#ibcon#[27=AT06-04\r\n] 2006.189.07:43:52.46#ibcon#*before write, iclass 24, count 2 2006.189.07:43:52.46#ibcon#enter sib2, iclass 24, count 2 2006.189.07:43:52.46#ibcon#flushed, iclass 24, count 2 2006.189.07:43:52.46#ibcon#about to write, iclass 24, count 2 2006.189.07:43:52.46#ibcon#wrote, iclass 24, count 2 2006.189.07:43:52.46#ibcon#about to read 3, iclass 24, count 2 2006.189.07:43:52.49#ibcon#read 3, iclass 24, count 2 2006.189.07:43:52.49#ibcon#about to read 4, iclass 24, count 2 2006.189.07:43:52.49#ibcon#read 4, iclass 24, count 2 2006.189.07:43:52.49#ibcon#about to read 5, iclass 24, count 2 2006.189.07:43:52.49#ibcon#read 5, iclass 24, count 2 2006.189.07:43:52.49#ibcon#about to read 6, iclass 24, count 2 2006.189.07:43:52.49#ibcon#read 6, iclass 24, count 2 2006.189.07:43:52.49#ibcon#end of sib2, iclass 24, count 2 2006.189.07:43:52.49#ibcon#*after write, iclass 24, count 2 2006.189.07:43:52.49#ibcon#*before return 0, iclass 24, count 2 2006.189.07:43:52.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:52.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:43:52.49#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:43:52.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:43:52.49#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:52.61#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:52.61#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:52.61#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:43:52.61#ibcon#first serial, iclass 24, count 0 2006.189.07:43:52.61#ibcon#enter sib2, iclass 24, count 0 2006.189.07:43:52.61#ibcon#flushed, iclass 24, count 0 2006.189.07:43:52.61#ibcon#about to write, iclass 24, count 0 2006.189.07:43:52.61#ibcon#wrote, iclass 24, count 0 2006.189.07:43:52.61#ibcon#about to read 3, iclass 24, count 0 2006.189.07:43:52.63#ibcon#read 3, iclass 24, count 0 2006.189.07:43:52.63#ibcon#about to read 4, iclass 24, count 0 2006.189.07:43:52.63#ibcon#read 4, iclass 24, count 0 2006.189.07:43:52.63#ibcon#about to read 5, iclass 24, count 0 2006.189.07:43:52.63#ibcon#read 5, iclass 24, count 0 2006.189.07:43:52.63#ibcon#about to read 6, iclass 24, count 0 2006.189.07:43:52.63#ibcon#read 6, iclass 24, count 0 2006.189.07:43:52.63#ibcon#end of sib2, iclass 24, count 0 2006.189.07:43:52.63#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:43:52.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:43:52.63#ibcon#[27=USB\r\n] 2006.189.07:43:52.63#ibcon#*before write, iclass 24, count 0 2006.189.07:43:52.63#ibcon#enter sib2, iclass 24, count 0 2006.189.07:43:52.63#ibcon#flushed, iclass 24, count 0 2006.189.07:43:52.63#ibcon#about to write, iclass 24, count 0 2006.189.07:43:52.63#ibcon#wrote, iclass 24, count 0 2006.189.07:43:52.63#ibcon#about to read 3, iclass 24, count 0 2006.189.07:43:52.66#ibcon#read 3, iclass 24, count 0 2006.189.07:43:52.66#ibcon#about to read 4, iclass 24, count 0 2006.189.07:43:52.66#ibcon#read 4, iclass 24, count 0 2006.189.07:43:52.66#ibcon#about to read 5, iclass 24, count 0 2006.189.07:43:52.66#ibcon#read 5, iclass 24, count 0 2006.189.07:43:52.66#ibcon#about to read 6, iclass 24, count 0 2006.189.07:43:52.66#ibcon#read 6, iclass 24, count 0 2006.189.07:43:52.66#ibcon#end of sib2, iclass 24, count 0 2006.189.07:43:52.66#ibcon#*after write, iclass 24, count 0 2006.189.07:43:52.66#ibcon#*before return 0, iclass 24, count 0 2006.189.07:43:52.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:52.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:43:52.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:43:52.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:43:52.66$vc4f8/vabw=wide 2006.189.07:43:52.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.07:43:52.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.07:43:52.66#ibcon#ireg 8 cls_cnt 0 2006.189.07:43:52.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:43:52.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:43:52.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:43:52.66#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:43:52.66#ibcon#first serial, iclass 26, count 0 2006.189.07:43:52.66#ibcon#enter sib2, iclass 26, count 0 2006.189.07:43:52.66#ibcon#flushed, iclass 26, count 0 2006.189.07:43:52.66#ibcon#about to write, iclass 26, count 0 2006.189.07:43:52.66#ibcon#wrote, iclass 26, count 0 2006.189.07:43:52.66#ibcon#about to read 3, iclass 26, count 0 2006.189.07:43:52.68#ibcon#read 3, iclass 26, count 0 2006.189.07:43:52.68#ibcon#about to read 4, iclass 26, count 0 2006.189.07:43:52.68#ibcon#read 4, iclass 26, count 0 2006.189.07:43:52.68#ibcon#about to read 5, iclass 26, count 0 2006.189.07:43:52.68#ibcon#read 5, iclass 26, count 0 2006.189.07:43:52.68#ibcon#about to read 6, iclass 26, count 0 2006.189.07:43:52.68#ibcon#read 6, iclass 26, count 0 2006.189.07:43:52.68#ibcon#end of sib2, iclass 26, count 0 2006.189.07:43:52.68#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:43:52.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:43:52.68#ibcon#[25=BW32\r\n] 2006.189.07:43:52.68#ibcon#*before write, iclass 26, count 0 2006.189.07:43:52.68#ibcon#enter sib2, iclass 26, count 0 2006.189.07:43:52.68#ibcon#flushed, iclass 26, count 0 2006.189.07:43:52.68#ibcon#about to write, iclass 26, count 0 2006.189.07:43:52.68#ibcon#wrote, iclass 26, count 0 2006.189.07:43:52.68#ibcon#about to read 3, iclass 26, count 0 2006.189.07:43:52.71#ibcon#read 3, iclass 26, count 0 2006.189.07:43:52.71#ibcon#about to read 4, iclass 26, count 0 2006.189.07:43:52.71#ibcon#read 4, iclass 26, count 0 2006.189.07:43:52.71#ibcon#about to read 5, iclass 26, count 0 2006.189.07:43:52.71#ibcon#read 5, iclass 26, count 0 2006.189.07:43:52.71#ibcon#about to read 6, iclass 26, count 0 2006.189.07:43:52.71#ibcon#read 6, iclass 26, count 0 2006.189.07:43:52.71#ibcon#end of sib2, iclass 26, count 0 2006.189.07:43:52.71#ibcon#*after write, iclass 26, count 0 2006.189.07:43:52.71#ibcon#*before return 0, iclass 26, count 0 2006.189.07:43:52.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:43:52.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:43:52.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:43:52.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:43:52.71$vc4f8/vbbw=wide 2006.189.07:43:52.71#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.07:43:52.71#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.07:43:52.71#ibcon#ireg 8 cls_cnt 0 2006.189.07:43:52.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:43:52.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:43:52.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:43:52.78#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:43:52.78#ibcon#first serial, iclass 28, count 0 2006.189.07:43:52.78#ibcon#enter sib2, iclass 28, count 0 2006.189.07:43:52.78#ibcon#flushed, iclass 28, count 0 2006.189.07:43:52.78#ibcon#about to write, iclass 28, count 0 2006.189.07:43:52.78#ibcon#wrote, iclass 28, count 0 2006.189.07:43:52.78#ibcon#about to read 3, iclass 28, count 0 2006.189.07:43:52.80#ibcon#read 3, iclass 28, count 0 2006.189.07:43:52.80#ibcon#about to read 4, iclass 28, count 0 2006.189.07:43:52.80#ibcon#read 4, iclass 28, count 0 2006.189.07:43:52.80#ibcon#about to read 5, iclass 28, count 0 2006.189.07:43:52.80#ibcon#read 5, iclass 28, count 0 2006.189.07:43:52.80#ibcon#about to read 6, iclass 28, count 0 2006.189.07:43:52.80#ibcon#read 6, iclass 28, count 0 2006.189.07:43:52.80#ibcon#end of sib2, iclass 28, count 0 2006.189.07:43:52.80#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:43:52.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:43:52.80#ibcon#[27=BW32\r\n] 2006.189.07:43:52.80#ibcon#*before write, iclass 28, count 0 2006.189.07:43:52.80#ibcon#enter sib2, iclass 28, count 0 2006.189.07:43:52.80#ibcon#flushed, iclass 28, count 0 2006.189.07:43:52.80#ibcon#about to write, iclass 28, count 0 2006.189.07:43:52.80#ibcon#wrote, iclass 28, count 0 2006.189.07:43:52.80#ibcon#about to read 3, iclass 28, count 0 2006.189.07:43:52.83#ibcon#read 3, iclass 28, count 0 2006.189.07:43:52.83#ibcon#about to read 4, iclass 28, count 0 2006.189.07:43:52.83#ibcon#read 4, iclass 28, count 0 2006.189.07:43:52.83#ibcon#about to read 5, iclass 28, count 0 2006.189.07:43:52.83#ibcon#read 5, iclass 28, count 0 2006.189.07:43:52.83#ibcon#about to read 6, iclass 28, count 0 2006.189.07:43:52.83#ibcon#read 6, iclass 28, count 0 2006.189.07:43:52.83#ibcon#end of sib2, iclass 28, count 0 2006.189.07:43:52.83#ibcon#*after write, iclass 28, count 0 2006.189.07:43:52.83#ibcon#*before return 0, iclass 28, count 0 2006.189.07:43:52.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:43:52.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:43:52.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:43:52.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:43:52.83$4f8m12a/ifd4f 2006.189.07:43:52.83$ifd4f/lo= 2006.189.07:43:52.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:43:52.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:43:52.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:43:52.83$ifd4f/patch= 2006.189.07:43:52.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:43:52.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:43:52.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:43:52.83$4f8m12a/"form=m,16.000,1:2 2006.189.07:43:52.83$4f8m12a/"tpicd 2006.189.07:43:52.83$4f8m12a/echo=off 2006.189.07:43:52.83$4f8m12a/xlog=off 2006.189.07:43:52.83:!2006.189.07:44:20 2006.189.07:44:03.13#trakl#Source acquired 2006.189.07:44:05.13#flagr#flagr/antenna,acquired 2006.189.07:44:20.00:preob 2006.189.07:44:21.13/onsource/TRACKING 2006.189.07:44:21.13:!2006.189.07:44:30 2006.189.07:44:30.00:data_valid=on 2006.189.07:44:30.00:midob 2006.189.07:44:30.13/onsource/TRACKING 2006.189.07:44:30.13/wx/26.15,1008.9,88 2006.189.07:44:30.22/cable/+6.4547E-03 2006.189.07:44:31.30/va/01,08,usb,yes,29,31 2006.189.07:44:31.30/va/02,07,usb,yes,29,31 2006.189.07:44:31.30/va/03,06,usb,yes,31,31 2006.189.07:44:31.30/va/04,07,usb,yes,30,32 2006.189.07:44:31.30/va/05,07,usb,yes,32,33 2006.189.07:44:31.30/va/06,06,usb,yes,31,30 2006.189.07:44:31.30/va/07,06,usb,yes,31,31 2006.189.07:44:31.30/va/08,06,usb,yes,33,33 2006.189.07:44:31.53/valo/01,532.99,yes,locked 2006.189.07:44:31.53/valo/02,572.99,yes,locked 2006.189.07:44:31.53/valo/03,672.99,yes,locked 2006.189.07:44:31.53/valo/04,832.99,yes,locked 2006.189.07:44:31.53/valo/05,652.99,yes,locked 2006.189.07:44:31.53/valo/06,772.99,yes,locked 2006.189.07:44:31.53/valo/07,832.99,yes,locked 2006.189.07:44:31.53/valo/08,852.99,yes,locked 2006.189.07:44:32.62/vb/01,04,usb,yes,29,28 2006.189.07:44:32.62/vb/02,04,usb,yes,31,32 2006.189.07:44:32.62/vb/03,04,usb,yes,27,31 2006.189.07:44:32.62/vb/04,04,usb,yes,28,28 2006.189.07:44:32.62/vb/05,04,usb,yes,27,30 2006.189.07:44:32.62/vb/06,04,usb,yes,28,30 2006.189.07:44:32.62/vb/07,04,usb,yes,30,29 2006.189.07:44:32.62/vb/08,04,usb,yes,27,30 2006.189.07:44:32.85/vblo/01,632.99,yes,locked 2006.189.07:44:32.85/vblo/02,640.99,yes,locked 2006.189.07:44:32.85/vblo/03,656.99,yes,locked 2006.189.07:44:32.85/vblo/04,712.99,yes,locked 2006.189.07:44:32.85/vblo/05,744.99,yes,locked 2006.189.07:44:32.85/vblo/06,752.99,yes,locked 2006.189.07:44:32.85/vblo/07,734.99,yes,locked 2006.189.07:44:32.85/vblo/08,744.99,yes,locked 2006.189.07:44:33.00/vabw/8 2006.189.07:44:33.15/vbbw/8 2006.189.07:44:33.24/xfe/off,on,15.5 2006.189.07:44:33.61/ifatt/23,28,28,28 2006.189.07:44:34.07/fmout-gps/S +2.98E-07 2006.189.07:44:34.16:!2006.189.07:45:30 2006.189.07:45:30.01:data_valid=off 2006.189.07:45:30.02:postob 2006.189.07:45:30.16/cable/+6.4536E-03 2006.189.07:45:30.17/wx/26.12,1008.9,88 2006.189.07:45:31.08/fmout-gps/S +2.98E-07 2006.189.07:45:31.09:scan_name=189-0746,k06189,60 2006.189.07:45:31.09:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.189.07:45:31.13#flagr#flagr/antenna,new-source 2006.189.07:45:32.13:checkk5 2006.189.07:45:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:45:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:45:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:45:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:45:34.04/chk_obsdata//k5ts1/T1890744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:45:34.43/chk_obsdata//k5ts2/T1890744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:45:34.80/chk_obsdata//k5ts3/T1890744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:45:35.18/chk_obsdata//k5ts4/T1890744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:45:35.88/k5log//k5ts1_log_newline 2006.189.07:45:36.57/k5log//k5ts2_log_newline 2006.189.07:45:37.27/k5log//k5ts3_log_newline 2006.189.07:45:37.96/k5log//k5ts4_log_newline 2006.189.07:45:37.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:45:37.99:4f8m12a=1 2006.189.07:45:37.99$4f8m12a/echo=on 2006.189.07:45:37.99$4f8m12a/pcalon 2006.189.07:45:37.99$pcalon/"no phase cal control is implemented here 2006.189.07:45:37.99$4f8m12a/"tpicd=stop 2006.189.07:45:37.99$4f8m12a/vc4f8 2006.189.07:45:37.99$vc4f8/valo=1,532.99 2006.189.07:45:38.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.07:45:38.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.07:45:38.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:38.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:38.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:38.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:38.00#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:45:38.00#ibcon#first serial, iclass 35, count 0 2006.189.07:45:38.00#ibcon#enter sib2, iclass 35, count 0 2006.189.07:45:38.00#ibcon#flushed, iclass 35, count 0 2006.189.07:45:38.00#ibcon#about to write, iclass 35, count 0 2006.189.07:45:38.00#ibcon#wrote, iclass 35, count 0 2006.189.07:45:38.00#ibcon#about to read 3, iclass 35, count 0 2006.189.07:45:38.04#ibcon#read 3, iclass 35, count 0 2006.189.07:45:38.04#ibcon#about to read 4, iclass 35, count 0 2006.189.07:45:38.04#ibcon#read 4, iclass 35, count 0 2006.189.07:45:38.04#ibcon#about to read 5, iclass 35, count 0 2006.189.07:45:38.04#ibcon#read 5, iclass 35, count 0 2006.189.07:45:38.04#ibcon#about to read 6, iclass 35, count 0 2006.189.07:45:38.04#ibcon#read 6, iclass 35, count 0 2006.189.07:45:38.04#ibcon#end of sib2, iclass 35, count 0 2006.189.07:45:38.04#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:45:38.04#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:45:38.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:45:38.04#ibcon#*before write, iclass 35, count 0 2006.189.07:45:38.04#ibcon#enter sib2, iclass 35, count 0 2006.189.07:45:38.04#ibcon#flushed, iclass 35, count 0 2006.189.07:45:38.04#ibcon#about to write, iclass 35, count 0 2006.189.07:45:38.04#ibcon#wrote, iclass 35, count 0 2006.189.07:45:38.04#ibcon#about to read 3, iclass 35, count 0 2006.189.07:45:38.09#ibcon#read 3, iclass 35, count 0 2006.189.07:45:38.09#ibcon#about to read 4, iclass 35, count 0 2006.189.07:45:38.09#ibcon#read 4, iclass 35, count 0 2006.189.07:45:38.09#ibcon#about to read 5, iclass 35, count 0 2006.189.07:45:38.09#ibcon#read 5, iclass 35, count 0 2006.189.07:45:38.09#ibcon#about to read 6, iclass 35, count 0 2006.189.07:45:38.09#ibcon#read 6, iclass 35, count 0 2006.189.07:45:38.09#ibcon#end of sib2, iclass 35, count 0 2006.189.07:45:38.09#ibcon#*after write, iclass 35, count 0 2006.189.07:45:38.09#ibcon#*before return 0, iclass 35, count 0 2006.189.07:45:38.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:38.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:38.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:45:38.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:45:38.09$vc4f8/va=1,8 2006.189.07:45:38.09#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.07:45:38.09#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.07:45:38.09#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:38.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:38.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:38.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:38.09#ibcon#enter wrdev, iclass 37, count 2 2006.189.07:45:38.09#ibcon#first serial, iclass 37, count 2 2006.189.07:45:38.09#ibcon#enter sib2, iclass 37, count 2 2006.189.07:45:38.09#ibcon#flushed, iclass 37, count 2 2006.189.07:45:38.09#ibcon#about to write, iclass 37, count 2 2006.189.07:45:38.09#ibcon#wrote, iclass 37, count 2 2006.189.07:45:38.09#ibcon#about to read 3, iclass 37, count 2 2006.189.07:45:38.11#ibcon#read 3, iclass 37, count 2 2006.189.07:45:38.11#ibcon#about to read 4, iclass 37, count 2 2006.189.07:45:38.11#ibcon#read 4, iclass 37, count 2 2006.189.07:45:38.11#ibcon#about to read 5, iclass 37, count 2 2006.189.07:45:38.11#ibcon#read 5, iclass 37, count 2 2006.189.07:45:38.11#ibcon#about to read 6, iclass 37, count 2 2006.189.07:45:38.11#ibcon#read 6, iclass 37, count 2 2006.189.07:45:38.11#ibcon#end of sib2, iclass 37, count 2 2006.189.07:45:38.11#ibcon#*mode == 0, iclass 37, count 2 2006.189.07:45:38.11#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.07:45:38.11#ibcon#[25=AT01-08\r\n] 2006.189.07:45:38.11#ibcon#*before write, iclass 37, count 2 2006.189.07:45:38.11#ibcon#enter sib2, iclass 37, count 2 2006.189.07:45:38.11#ibcon#flushed, iclass 37, count 2 2006.189.07:45:38.11#ibcon#about to write, iclass 37, count 2 2006.189.07:45:38.11#ibcon#wrote, iclass 37, count 2 2006.189.07:45:38.11#ibcon#about to read 3, iclass 37, count 2 2006.189.07:45:38.14#ibcon#read 3, iclass 37, count 2 2006.189.07:45:38.14#ibcon#about to read 4, iclass 37, count 2 2006.189.07:45:38.14#ibcon#read 4, iclass 37, count 2 2006.189.07:45:38.14#ibcon#about to read 5, iclass 37, count 2 2006.189.07:45:38.14#ibcon#read 5, iclass 37, count 2 2006.189.07:45:38.14#ibcon#about to read 6, iclass 37, count 2 2006.189.07:45:38.14#ibcon#read 6, iclass 37, count 2 2006.189.07:45:38.14#ibcon#end of sib2, iclass 37, count 2 2006.189.07:45:38.14#ibcon#*after write, iclass 37, count 2 2006.189.07:45:38.14#ibcon#*before return 0, iclass 37, count 2 2006.189.07:45:38.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:38.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:38.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.07:45:38.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:38.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:38.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:38.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:38.26#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:45:38.26#ibcon#first serial, iclass 37, count 0 2006.189.07:45:38.26#ibcon#enter sib2, iclass 37, count 0 2006.189.07:45:38.26#ibcon#flushed, iclass 37, count 0 2006.189.07:45:38.26#ibcon#about to write, iclass 37, count 0 2006.189.07:45:38.26#ibcon#wrote, iclass 37, count 0 2006.189.07:45:38.26#ibcon#about to read 3, iclass 37, count 0 2006.189.07:45:38.28#ibcon#read 3, iclass 37, count 0 2006.189.07:45:38.28#ibcon#about to read 4, iclass 37, count 0 2006.189.07:45:38.28#ibcon#read 4, iclass 37, count 0 2006.189.07:45:38.28#ibcon#about to read 5, iclass 37, count 0 2006.189.07:45:38.28#ibcon#read 5, iclass 37, count 0 2006.189.07:45:38.28#ibcon#about to read 6, iclass 37, count 0 2006.189.07:45:38.28#ibcon#read 6, iclass 37, count 0 2006.189.07:45:38.28#ibcon#end of sib2, iclass 37, count 0 2006.189.07:45:38.28#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:45:38.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:45:38.28#ibcon#[25=USB\r\n] 2006.189.07:45:38.28#ibcon#*before write, iclass 37, count 0 2006.189.07:45:38.28#ibcon#enter sib2, iclass 37, count 0 2006.189.07:45:38.28#ibcon#flushed, iclass 37, count 0 2006.189.07:45:38.28#ibcon#about to write, iclass 37, count 0 2006.189.07:45:38.28#ibcon#wrote, iclass 37, count 0 2006.189.07:45:38.28#ibcon#about to read 3, iclass 37, count 0 2006.189.07:45:38.31#ibcon#read 3, iclass 37, count 0 2006.189.07:45:38.31#ibcon#about to read 4, iclass 37, count 0 2006.189.07:45:38.31#ibcon#read 4, iclass 37, count 0 2006.189.07:45:38.31#ibcon#about to read 5, iclass 37, count 0 2006.189.07:45:38.31#ibcon#read 5, iclass 37, count 0 2006.189.07:45:38.31#ibcon#about to read 6, iclass 37, count 0 2006.189.07:45:38.31#ibcon#read 6, iclass 37, count 0 2006.189.07:45:38.31#ibcon#end of sib2, iclass 37, count 0 2006.189.07:45:38.31#ibcon#*after write, iclass 37, count 0 2006.189.07:45:38.31#ibcon#*before return 0, iclass 37, count 0 2006.189.07:45:38.31#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:38.31#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:38.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:45:38.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:45:38.31$vc4f8/valo=2,572.99 2006.189.07:45:38.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.07:45:38.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.07:45:38.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:38.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:38.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:38.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:38.31#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:45:38.31#ibcon#first serial, iclass 39, count 0 2006.189.07:45:38.31#ibcon#enter sib2, iclass 39, count 0 2006.189.07:45:38.31#ibcon#flushed, iclass 39, count 0 2006.189.07:45:38.31#ibcon#about to write, iclass 39, count 0 2006.189.07:45:38.31#ibcon#wrote, iclass 39, count 0 2006.189.07:45:38.31#ibcon#about to read 3, iclass 39, count 0 2006.189.07:45:38.33#ibcon#read 3, iclass 39, count 0 2006.189.07:45:38.33#ibcon#about to read 4, iclass 39, count 0 2006.189.07:45:38.33#ibcon#read 4, iclass 39, count 0 2006.189.07:45:38.33#ibcon#about to read 5, iclass 39, count 0 2006.189.07:45:38.33#ibcon#read 5, iclass 39, count 0 2006.189.07:45:38.33#ibcon#about to read 6, iclass 39, count 0 2006.189.07:45:38.33#ibcon#read 6, iclass 39, count 0 2006.189.07:45:38.33#ibcon#end of sib2, iclass 39, count 0 2006.189.07:45:38.33#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:45:38.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:45:38.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:45:38.33#ibcon#*before write, iclass 39, count 0 2006.189.07:45:38.33#ibcon#enter sib2, iclass 39, count 0 2006.189.07:45:38.33#ibcon#flushed, iclass 39, count 0 2006.189.07:45:38.33#ibcon#about to write, iclass 39, count 0 2006.189.07:45:38.33#ibcon#wrote, iclass 39, count 0 2006.189.07:45:38.33#ibcon#about to read 3, iclass 39, count 0 2006.189.07:45:38.37#ibcon#read 3, iclass 39, count 0 2006.189.07:45:38.37#ibcon#about to read 4, iclass 39, count 0 2006.189.07:45:38.37#ibcon#read 4, iclass 39, count 0 2006.189.07:45:38.37#ibcon#about to read 5, iclass 39, count 0 2006.189.07:45:38.37#ibcon#read 5, iclass 39, count 0 2006.189.07:45:38.37#ibcon#about to read 6, iclass 39, count 0 2006.189.07:45:38.37#ibcon#read 6, iclass 39, count 0 2006.189.07:45:38.37#ibcon#end of sib2, iclass 39, count 0 2006.189.07:45:38.37#ibcon#*after write, iclass 39, count 0 2006.189.07:45:38.37#ibcon#*before return 0, iclass 39, count 0 2006.189.07:45:38.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:38.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:38.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:45:38.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:45:38.37$vc4f8/va=2,7 2006.189.07:45:38.37#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.07:45:38.37#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.07:45:38.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:38.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:38.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:38.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:38.43#ibcon#enter wrdev, iclass 3, count 2 2006.189.07:45:38.43#ibcon#first serial, iclass 3, count 2 2006.189.07:45:38.43#ibcon#enter sib2, iclass 3, count 2 2006.189.07:45:38.43#ibcon#flushed, iclass 3, count 2 2006.189.07:45:38.43#ibcon#about to write, iclass 3, count 2 2006.189.07:45:38.43#ibcon#wrote, iclass 3, count 2 2006.189.07:45:38.43#ibcon#about to read 3, iclass 3, count 2 2006.189.07:45:38.45#ibcon#read 3, iclass 3, count 2 2006.189.07:45:38.45#ibcon#about to read 4, iclass 3, count 2 2006.189.07:45:38.45#ibcon#read 4, iclass 3, count 2 2006.189.07:45:38.45#ibcon#about to read 5, iclass 3, count 2 2006.189.07:45:38.45#ibcon#read 5, iclass 3, count 2 2006.189.07:45:38.45#ibcon#about to read 6, iclass 3, count 2 2006.189.07:45:38.45#ibcon#read 6, iclass 3, count 2 2006.189.07:45:38.45#ibcon#end of sib2, iclass 3, count 2 2006.189.07:45:38.45#ibcon#*mode == 0, iclass 3, count 2 2006.189.07:45:38.45#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.07:45:38.45#ibcon#[25=AT02-07\r\n] 2006.189.07:45:38.45#ibcon#*before write, iclass 3, count 2 2006.189.07:45:38.45#ibcon#enter sib2, iclass 3, count 2 2006.189.07:45:38.45#ibcon#flushed, iclass 3, count 2 2006.189.07:45:38.45#ibcon#about to write, iclass 3, count 2 2006.189.07:45:38.45#ibcon#wrote, iclass 3, count 2 2006.189.07:45:38.45#ibcon#about to read 3, iclass 3, count 2 2006.189.07:45:38.48#ibcon#read 3, iclass 3, count 2 2006.189.07:45:38.48#ibcon#about to read 4, iclass 3, count 2 2006.189.07:45:38.48#ibcon#read 4, iclass 3, count 2 2006.189.07:45:38.48#ibcon#about to read 5, iclass 3, count 2 2006.189.07:45:38.48#ibcon#read 5, iclass 3, count 2 2006.189.07:45:38.48#ibcon#about to read 6, iclass 3, count 2 2006.189.07:45:38.48#ibcon#read 6, iclass 3, count 2 2006.189.07:45:38.48#ibcon#end of sib2, iclass 3, count 2 2006.189.07:45:38.48#ibcon#*after write, iclass 3, count 2 2006.189.07:45:38.48#ibcon#*before return 0, iclass 3, count 2 2006.189.07:45:38.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:38.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:38.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.07:45:38.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:38.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:38.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:38.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:38.60#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:45:38.60#ibcon#first serial, iclass 3, count 0 2006.189.07:45:38.60#ibcon#enter sib2, iclass 3, count 0 2006.189.07:45:38.60#ibcon#flushed, iclass 3, count 0 2006.189.07:45:38.60#ibcon#about to write, iclass 3, count 0 2006.189.07:45:38.60#ibcon#wrote, iclass 3, count 0 2006.189.07:45:38.60#ibcon#about to read 3, iclass 3, count 0 2006.189.07:45:38.62#ibcon#read 3, iclass 3, count 0 2006.189.07:45:38.62#ibcon#about to read 4, iclass 3, count 0 2006.189.07:45:38.62#ibcon#read 4, iclass 3, count 0 2006.189.07:45:38.62#ibcon#about to read 5, iclass 3, count 0 2006.189.07:45:38.62#ibcon#read 5, iclass 3, count 0 2006.189.07:45:38.62#ibcon#about to read 6, iclass 3, count 0 2006.189.07:45:38.62#ibcon#read 6, iclass 3, count 0 2006.189.07:45:38.62#ibcon#end of sib2, iclass 3, count 0 2006.189.07:45:38.62#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:45:38.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:45:38.62#ibcon#[25=USB\r\n] 2006.189.07:45:38.62#ibcon#*before write, iclass 3, count 0 2006.189.07:45:38.62#ibcon#enter sib2, iclass 3, count 0 2006.189.07:45:38.62#ibcon#flushed, iclass 3, count 0 2006.189.07:45:38.62#ibcon#about to write, iclass 3, count 0 2006.189.07:45:38.62#ibcon#wrote, iclass 3, count 0 2006.189.07:45:38.62#ibcon#about to read 3, iclass 3, count 0 2006.189.07:45:38.65#ibcon#read 3, iclass 3, count 0 2006.189.07:45:38.65#ibcon#about to read 4, iclass 3, count 0 2006.189.07:45:38.65#ibcon#read 4, iclass 3, count 0 2006.189.07:45:38.65#ibcon#about to read 5, iclass 3, count 0 2006.189.07:45:38.65#ibcon#read 5, iclass 3, count 0 2006.189.07:45:38.65#ibcon#about to read 6, iclass 3, count 0 2006.189.07:45:38.65#ibcon#read 6, iclass 3, count 0 2006.189.07:45:38.65#ibcon#end of sib2, iclass 3, count 0 2006.189.07:45:38.65#ibcon#*after write, iclass 3, count 0 2006.189.07:45:38.65#ibcon#*before return 0, iclass 3, count 0 2006.189.07:45:38.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:38.65#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:38.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:45:38.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:45:38.65$vc4f8/valo=3,672.99 2006.189.07:45:38.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.07:45:38.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.07:45:38.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:38.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:38.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:38.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:38.65#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:45:38.65#ibcon#first serial, iclass 5, count 0 2006.189.07:45:38.65#ibcon#enter sib2, iclass 5, count 0 2006.189.07:45:38.65#ibcon#flushed, iclass 5, count 0 2006.189.07:45:38.65#ibcon#about to write, iclass 5, count 0 2006.189.07:45:38.65#ibcon#wrote, iclass 5, count 0 2006.189.07:45:38.65#ibcon#about to read 3, iclass 5, count 0 2006.189.07:45:38.67#ibcon#read 3, iclass 5, count 0 2006.189.07:45:38.67#ibcon#about to read 4, iclass 5, count 0 2006.189.07:45:38.67#ibcon#read 4, iclass 5, count 0 2006.189.07:45:38.67#ibcon#about to read 5, iclass 5, count 0 2006.189.07:45:38.67#ibcon#read 5, iclass 5, count 0 2006.189.07:45:38.67#ibcon#about to read 6, iclass 5, count 0 2006.189.07:45:38.67#ibcon#read 6, iclass 5, count 0 2006.189.07:45:38.67#ibcon#end of sib2, iclass 5, count 0 2006.189.07:45:38.67#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:45:38.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:45:38.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:45:38.67#ibcon#*before write, iclass 5, count 0 2006.189.07:45:38.67#ibcon#enter sib2, iclass 5, count 0 2006.189.07:45:38.67#ibcon#flushed, iclass 5, count 0 2006.189.07:45:38.67#ibcon#about to write, iclass 5, count 0 2006.189.07:45:38.67#ibcon#wrote, iclass 5, count 0 2006.189.07:45:38.67#ibcon#about to read 3, iclass 5, count 0 2006.189.07:45:38.71#ibcon#read 3, iclass 5, count 0 2006.189.07:45:38.71#ibcon#about to read 4, iclass 5, count 0 2006.189.07:45:38.71#ibcon#read 4, iclass 5, count 0 2006.189.07:45:38.71#ibcon#about to read 5, iclass 5, count 0 2006.189.07:45:38.71#ibcon#read 5, iclass 5, count 0 2006.189.07:45:38.71#ibcon#about to read 6, iclass 5, count 0 2006.189.07:45:38.71#ibcon#read 6, iclass 5, count 0 2006.189.07:45:38.71#ibcon#end of sib2, iclass 5, count 0 2006.189.07:45:38.71#ibcon#*after write, iclass 5, count 0 2006.189.07:45:38.71#ibcon#*before return 0, iclass 5, count 0 2006.189.07:45:38.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:38.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:38.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:45:38.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:45:38.71$vc4f8/va=3,6 2006.189.07:45:38.71#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.07:45:38.71#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.07:45:38.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:38.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:45:38.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:45:38.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:45:38.77#ibcon#enter wrdev, iclass 7, count 2 2006.189.07:45:38.77#ibcon#first serial, iclass 7, count 2 2006.189.07:45:38.77#ibcon#enter sib2, iclass 7, count 2 2006.189.07:45:38.77#ibcon#flushed, iclass 7, count 2 2006.189.07:45:38.77#ibcon#about to write, iclass 7, count 2 2006.189.07:45:38.77#ibcon#wrote, iclass 7, count 2 2006.189.07:45:38.77#ibcon#about to read 3, iclass 7, count 2 2006.189.07:45:38.79#ibcon#read 3, iclass 7, count 2 2006.189.07:45:38.79#ibcon#about to read 4, iclass 7, count 2 2006.189.07:45:38.79#ibcon#read 4, iclass 7, count 2 2006.189.07:45:38.79#ibcon#about to read 5, iclass 7, count 2 2006.189.07:45:38.79#ibcon#read 5, iclass 7, count 2 2006.189.07:45:38.79#ibcon#about to read 6, iclass 7, count 2 2006.189.07:45:38.79#ibcon#read 6, iclass 7, count 2 2006.189.07:45:38.79#ibcon#end of sib2, iclass 7, count 2 2006.189.07:45:38.79#ibcon#*mode == 0, iclass 7, count 2 2006.189.07:45:38.79#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.07:45:38.79#ibcon#[25=AT03-06\r\n] 2006.189.07:45:38.79#ibcon#*before write, iclass 7, count 2 2006.189.07:45:38.79#ibcon#enter sib2, iclass 7, count 2 2006.189.07:45:38.79#ibcon#flushed, iclass 7, count 2 2006.189.07:45:38.79#ibcon#about to write, iclass 7, count 2 2006.189.07:45:38.79#ibcon#wrote, iclass 7, count 2 2006.189.07:45:38.79#ibcon#about to read 3, iclass 7, count 2 2006.189.07:45:38.82#ibcon#read 3, iclass 7, count 2 2006.189.07:45:38.82#ibcon#about to read 4, iclass 7, count 2 2006.189.07:45:38.82#ibcon#read 4, iclass 7, count 2 2006.189.07:45:38.82#ibcon#about to read 5, iclass 7, count 2 2006.189.07:45:38.82#ibcon#read 5, iclass 7, count 2 2006.189.07:45:38.82#ibcon#about to read 6, iclass 7, count 2 2006.189.07:45:38.82#ibcon#read 6, iclass 7, count 2 2006.189.07:45:38.82#ibcon#end of sib2, iclass 7, count 2 2006.189.07:45:38.82#ibcon#*after write, iclass 7, count 2 2006.189.07:45:38.82#ibcon#*before return 0, iclass 7, count 2 2006.189.07:45:38.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:45:38.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.07:45:38.82#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.07:45:38.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:38.82#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:45:38.94#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:45:38.94#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:45:38.94#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:45:38.94#ibcon#first serial, iclass 7, count 0 2006.189.07:45:38.94#ibcon#enter sib2, iclass 7, count 0 2006.189.07:45:38.94#ibcon#flushed, iclass 7, count 0 2006.189.07:45:38.94#ibcon#about to write, iclass 7, count 0 2006.189.07:45:38.94#ibcon#wrote, iclass 7, count 0 2006.189.07:45:38.94#ibcon#about to read 3, iclass 7, count 0 2006.189.07:45:38.96#ibcon#read 3, iclass 7, count 0 2006.189.07:45:38.96#ibcon#about to read 4, iclass 7, count 0 2006.189.07:45:38.96#ibcon#read 4, iclass 7, count 0 2006.189.07:45:38.96#ibcon#about to read 5, iclass 7, count 0 2006.189.07:45:38.96#ibcon#read 5, iclass 7, count 0 2006.189.07:45:38.96#ibcon#about to read 6, iclass 7, count 0 2006.189.07:45:38.96#ibcon#read 6, iclass 7, count 0 2006.189.07:45:38.96#ibcon#end of sib2, iclass 7, count 0 2006.189.07:45:38.96#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:45:38.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:45:38.96#ibcon#[25=USB\r\n] 2006.189.07:45:38.96#ibcon#*before write, iclass 7, count 0 2006.189.07:45:38.96#ibcon#enter sib2, iclass 7, count 0 2006.189.07:45:38.96#ibcon#flushed, iclass 7, count 0 2006.189.07:45:38.96#ibcon#about to write, iclass 7, count 0 2006.189.07:45:38.96#ibcon#wrote, iclass 7, count 0 2006.189.07:45:38.96#ibcon#about to read 3, iclass 7, count 0 2006.189.07:45:38.99#ibcon#read 3, iclass 7, count 0 2006.189.07:45:38.99#ibcon#about to read 4, iclass 7, count 0 2006.189.07:45:38.99#ibcon#read 4, iclass 7, count 0 2006.189.07:45:38.99#ibcon#about to read 5, iclass 7, count 0 2006.189.07:45:38.99#ibcon#read 5, iclass 7, count 0 2006.189.07:45:38.99#ibcon#about to read 6, iclass 7, count 0 2006.189.07:45:38.99#ibcon#read 6, iclass 7, count 0 2006.189.07:45:38.99#ibcon#end of sib2, iclass 7, count 0 2006.189.07:45:38.99#ibcon#*after write, iclass 7, count 0 2006.189.07:45:38.99#ibcon#*before return 0, iclass 7, count 0 2006.189.07:45:38.99#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:45:38.99#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.07:45:38.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:45:38.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:45:38.99$vc4f8/valo=4,832.99 2006.189.07:45:38.99#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.07:45:38.99#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.07:45:38.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:38.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:45:38.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:45:38.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:45:38.99#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:45:38.99#ibcon#first serial, iclass 11, count 0 2006.189.07:45:38.99#ibcon#enter sib2, iclass 11, count 0 2006.189.07:45:38.99#ibcon#flushed, iclass 11, count 0 2006.189.07:45:38.99#ibcon#about to write, iclass 11, count 0 2006.189.07:45:38.99#ibcon#wrote, iclass 11, count 0 2006.189.07:45:38.99#ibcon#about to read 3, iclass 11, count 0 2006.189.07:45:39.01#ibcon#read 3, iclass 11, count 0 2006.189.07:45:39.01#ibcon#about to read 4, iclass 11, count 0 2006.189.07:45:39.01#ibcon#read 4, iclass 11, count 0 2006.189.07:45:39.01#ibcon#about to read 5, iclass 11, count 0 2006.189.07:45:39.01#ibcon#read 5, iclass 11, count 0 2006.189.07:45:39.01#ibcon#about to read 6, iclass 11, count 0 2006.189.07:45:39.01#ibcon#read 6, iclass 11, count 0 2006.189.07:45:39.01#ibcon#end of sib2, iclass 11, count 0 2006.189.07:45:39.01#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:45:39.01#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:45:39.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:45:39.01#ibcon#*before write, iclass 11, count 0 2006.189.07:45:39.01#ibcon#enter sib2, iclass 11, count 0 2006.189.07:45:39.01#ibcon#flushed, iclass 11, count 0 2006.189.07:45:39.01#ibcon#about to write, iclass 11, count 0 2006.189.07:45:39.01#ibcon#wrote, iclass 11, count 0 2006.189.07:45:39.01#ibcon#about to read 3, iclass 11, count 0 2006.189.07:45:39.05#ibcon#read 3, iclass 11, count 0 2006.189.07:45:39.05#ibcon#about to read 4, iclass 11, count 0 2006.189.07:45:39.05#ibcon#read 4, iclass 11, count 0 2006.189.07:45:39.05#ibcon#about to read 5, iclass 11, count 0 2006.189.07:45:39.05#ibcon#read 5, iclass 11, count 0 2006.189.07:45:39.05#ibcon#about to read 6, iclass 11, count 0 2006.189.07:45:39.05#ibcon#read 6, iclass 11, count 0 2006.189.07:45:39.05#ibcon#end of sib2, iclass 11, count 0 2006.189.07:45:39.05#ibcon#*after write, iclass 11, count 0 2006.189.07:45:39.05#ibcon#*before return 0, iclass 11, count 0 2006.189.07:45:39.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:45:39.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:45:39.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:45:39.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:45:39.05$vc4f8/va=4,7 2006.189.07:45:39.05#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.07:45:39.05#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.07:45:39.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:39.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:45:39.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:45:39.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:45:39.11#ibcon#enter wrdev, iclass 13, count 2 2006.189.07:45:39.11#ibcon#first serial, iclass 13, count 2 2006.189.07:45:39.11#ibcon#enter sib2, iclass 13, count 2 2006.189.07:45:39.11#ibcon#flushed, iclass 13, count 2 2006.189.07:45:39.11#ibcon#about to write, iclass 13, count 2 2006.189.07:45:39.11#ibcon#wrote, iclass 13, count 2 2006.189.07:45:39.11#ibcon#about to read 3, iclass 13, count 2 2006.189.07:45:39.13#ibcon#read 3, iclass 13, count 2 2006.189.07:45:39.13#ibcon#about to read 4, iclass 13, count 2 2006.189.07:45:39.13#ibcon#read 4, iclass 13, count 2 2006.189.07:45:39.13#ibcon#about to read 5, iclass 13, count 2 2006.189.07:45:39.13#ibcon#read 5, iclass 13, count 2 2006.189.07:45:39.13#ibcon#about to read 6, iclass 13, count 2 2006.189.07:45:39.13#ibcon#read 6, iclass 13, count 2 2006.189.07:45:39.13#ibcon#end of sib2, iclass 13, count 2 2006.189.07:45:39.13#ibcon#*mode == 0, iclass 13, count 2 2006.189.07:45:39.13#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.07:45:39.13#ibcon#[25=AT04-07\r\n] 2006.189.07:45:39.13#ibcon#*before write, iclass 13, count 2 2006.189.07:45:39.13#ibcon#enter sib2, iclass 13, count 2 2006.189.07:45:39.13#ibcon#flushed, iclass 13, count 2 2006.189.07:45:39.13#ibcon#about to write, iclass 13, count 2 2006.189.07:45:39.13#ibcon#wrote, iclass 13, count 2 2006.189.07:45:39.13#ibcon#about to read 3, iclass 13, count 2 2006.189.07:45:39.16#ibcon#read 3, iclass 13, count 2 2006.189.07:45:39.16#ibcon#about to read 4, iclass 13, count 2 2006.189.07:45:39.16#ibcon#read 4, iclass 13, count 2 2006.189.07:45:39.16#ibcon#about to read 5, iclass 13, count 2 2006.189.07:45:39.16#ibcon#read 5, iclass 13, count 2 2006.189.07:45:39.16#ibcon#about to read 6, iclass 13, count 2 2006.189.07:45:39.16#ibcon#read 6, iclass 13, count 2 2006.189.07:45:39.16#ibcon#end of sib2, iclass 13, count 2 2006.189.07:45:39.16#ibcon#*after write, iclass 13, count 2 2006.189.07:45:39.16#ibcon#*before return 0, iclass 13, count 2 2006.189.07:45:39.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:45:39.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.07:45:39.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.07:45:39.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:39.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:45:39.28#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:45:39.28#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:45:39.28#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:45:39.28#ibcon#first serial, iclass 13, count 0 2006.189.07:45:39.28#ibcon#enter sib2, iclass 13, count 0 2006.189.07:45:39.28#ibcon#flushed, iclass 13, count 0 2006.189.07:45:39.28#ibcon#about to write, iclass 13, count 0 2006.189.07:45:39.28#ibcon#wrote, iclass 13, count 0 2006.189.07:45:39.28#ibcon#about to read 3, iclass 13, count 0 2006.189.07:45:39.30#ibcon#read 3, iclass 13, count 0 2006.189.07:45:39.30#ibcon#about to read 4, iclass 13, count 0 2006.189.07:45:39.30#ibcon#read 4, iclass 13, count 0 2006.189.07:45:39.30#ibcon#about to read 5, iclass 13, count 0 2006.189.07:45:39.30#ibcon#read 5, iclass 13, count 0 2006.189.07:45:39.30#ibcon#about to read 6, iclass 13, count 0 2006.189.07:45:39.30#ibcon#read 6, iclass 13, count 0 2006.189.07:45:39.30#ibcon#end of sib2, iclass 13, count 0 2006.189.07:45:39.30#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:45:39.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:45:39.30#ibcon#[25=USB\r\n] 2006.189.07:45:39.30#ibcon#*before write, iclass 13, count 0 2006.189.07:45:39.30#ibcon#enter sib2, iclass 13, count 0 2006.189.07:45:39.30#ibcon#flushed, iclass 13, count 0 2006.189.07:45:39.30#ibcon#about to write, iclass 13, count 0 2006.189.07:45:39.30#ibcon#wrote, iclass 13, count 0 2006.189.07:45:39.30#ibcon#about to read 3, iclass 13, count 0 2006.189.07:45:39.33#ibcon#read 3, iclass 13, count 0 2006.189.07:45:39.33#ibcon#about to read 4, iclass 13, count 0 2006.189.07:45:39.33#ibcon#read 4, iclass 13, count 0 2006.189.07:45:39.33#ibcon#about to read 5, iclass 13, count 0 2006.189.07:45:39.33#ibcon#read 5, iclass 13, count 0 2006.189.07:45:39.33#ibcon#about to read 6, iclass 13, count 0 2006.189.07:45:39.33#ibcon#read 6, iclass 13, count 0 2006.189.07:45:39.33#ibcon#end of sib2, iclass 13, count 0 2006.189.07:45:39.33#ibcon#*after write, iclass 13, count 0 2006.189.07:45:39.33#ibcon#*before return 0, iclass 13, count 0 2006.189.07:45:39.33#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:45:39.33#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.07:45:39.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:45:39.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:45:39.33$vc4f8/valo=5,652.99 2006.189.07:45:39.33#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.07:45:39.33#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.07:45:39.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:39.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:39.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:39.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:39.33#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:45:39.33#ibcon#first serial, iclass 15, count 0 2006.189.07:45:39.33#ibcon#enter sib2, iclass 15, count 0 2006.189.07:45:39.33#ibcon#flushed, iclass 15, count 0 2006.189.07:45:39.33#ibcon#about to write, iclass 15, count 0 2006.189.07:45:39.33#ibcon#wrote, iclass 15, count 0 2006.189.07:45:39.33#ibcon#about to read 3, iclass 15, count 0 2006.189.07:45:39.35#ibcon#read 3, iclass 15, count 0 2006.189.07:45:39.35#ibcon#about to read 4, iclass 15, count 0 2006.189.07:45:39.35#ibcon#read 4, iclass 15, count 0 2006.189.07:45:39.35#ibcon#about to read 5, iclass 15, count 0 2006.189.07:45:39.35#ibcon#read 5, iclass 15, count 0 2006.189.07:45:39.35#ibcon#about to read 6, iclass 15, count 0 2006.189.07:45:39.35#ibcon#read 6, iclass 15, count 0 2006.189.07:45:39.35#ibcon#end of sib2, iclass 15, count 0 2006.189.07:45:39.35#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:45:39.35#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:45:39.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:45:39.35#ibcon#*before write, iclass 15, count 0 2006.189.07:45:39.35#ibcon#enter sib2, iclass 15, count 0 2006.189.07:45:39.35#ibcon#flushed, iclass 15, count 0 2006.189.07:45:39.35#ibcon#about to write, iclass 15, count 0 2006.189.07:45:39.35#ibcon#wrote, iclass 15, count 0 2006.189.07:45:39.35#ibcon#about to read 3, iclass 15, count 0 2006.189.07:45:39.39#ibcon#read 3, iclass 15, count 0 2006.189.07:45:39.39#ibcon#about to read 4, iclass 15, count 0 2006.189.07:45:39.39#ibcon#read 4, iclass 15, count 0 2006.189.07:45:39.39#ibcon#about to read 5, iclass 15, count 0 2006.189.07:45:39.39#ibcon#read 5, iclass 15, count 0 2006.189.07:45:39.39#ibcon#about to read 6, iclass 15, count 0 2006.189.07:45:39.39#ibcon#read 6, iclass 15, count 0 2006.189.07:45:39.39#ibcon#end of sib2, iclass 15, count 0 2006.189.07:45:39.39#ibcon#*after write, iclass 15, count 0 2006.189.07:45:39.39#ibcon#*before return 0, iclass 15, count 0 2006.189.07:45:39.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:39.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:39.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:45:39.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:45:39.39$vc4f8/va=5,7 2006.189.07:45:39.39#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.07:45:39.39#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.07:45:39.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:39.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:39.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:39.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:39.45#ibcon#enter wrdev, iclass 17, count 2 2006.189.07:45:39.45#ibcon#first serial, iclass 17, count 2 2006.189.07:45:39.45#ibcon#enter sib2, iclass 17, count 2 2006.189.07:45:39.45#ibcon#flushed, iclass 17, count 2 2006.189.07:45:39.45#ibcon#about to write, iclass 17, count 2 2006.189.07:45:39.45#ibcon#wrote, iclass 17, count 2 2006.189.07:45:39.45#ibcon#about to read 3, iclass 17, count 2 2006.189.07:45:39.47#ibcon#read 3, iclass 17, count 2 2006.189.07:45:39.47#ibcon#about to read 4, iclass 17, count 2 2006.189.07:45:39.47#ibcon#read 4, iclass 17, count 2 2006.189.07:45:39.47#ibcon#about to read 5, iclass 17, count 2 2006.189.07:45:39.47#ibcon#read 5, iclass 17, count 2 2006.189.07:45:39.47#ibcon#about to read 6, iclass 17, count 2 2006.189.07:45:39.47#ibcon#read 6, iclass 17, count 2 2006.189.07:45:39.47#ibcon#end of sib2, iclass 17, count 2 2006.189.07:45:39.47#ibcon#*mode == 0, iclass 17, count 2 2006.189.07:45:39.47#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.07:45:39.47#ibcon#[25=AT05-07\r\n] 2006.189.07:45:39.47#ibcon#*before write, iclass 17, count 2 2006.189.07:45:39.47#ibcon#enter sib2, iclass 17, count 2 2006.189.07:45:39.47#ibcon#flushed, iclass 17, count 2 2006.189.07:45:39.47#ibcon#about to write, iclass 17, count 2 2006.189.07:45:39.47#ibcon#wrote, iclass 17, count 2 2006.189.07:45:39.47#ibcon#about to read 3, iclass 17, count 2 2006.189.07:45:39.50#ibcon#read 3, iclass 17, count 2 2006.189.07:45:39.50#ibcon#about to read 4, iclass 17, count 2 2006.189.07:45:39.50#ibcon#read 4, iclass 17, count 2 2006.189.07:45:39.50#ibcon#about to read 5, iclass 17, count 2 2006.189.07:45:39.50#ibcon#read 5, iclass 17, count 2 2006.189.07:45:39.50#ibcon#about to read 6, iclass 17, count 2 2006.189.07:45:39.50#ibcon#read 6, iclass 17, count 2 2006.189.07:45:39.50#ibcon#end of sib2, iclass 17, count 2 2006.189.07:45:39.50#ibcon#*after write, iclass 17, count 2 2006.189.07:45:39.50#ibcon#*before return 0, iclass 17, count 2 2006.189.07:45:39.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:39.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:39.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.07:45:39.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:39.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:39.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:39.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:39.62#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:45:39.62#ibcon#first serial, iclass 17, count 0 2006.189.07:45:39.62#ibcon#enter sib2, iclass 17, count 0 2006.189.07:45:39.62#ibcon#flushed, iclass 17, count 0 2006.189.07:45:39.62#ibcon#about to write, iclass 17, count 0 2006.189.07:45:39.62#ibcon#wrote, iclass 17, count 0 2006.189.07:45:39.62#ibcon#about to read 3, iclass 17, count 0 2006.189.07:45:39.64#ibcon#read 3, iclass 17, count 0 2006.189.07:45:39.64#ibcon#about to read 4, iclass 17, count 0 2006.189.07:45:39.64#ibcon#read 4, iclass 17, count 0 2006.189.07:45:39.64#ibcon#about to read 5, iclass 17, count 0 2006.189.07:45:39.64#ibcon#read 5, iclass 17, count 0 2006.189.07:45:39.64#ibcon#about to read 6, iclass 17, count 0 2006.189.07:45:39.64#ibcon#read 6, iclass 17, count 0 2006.189.07:45:39.64#ibcon#end of sib2, iclass 17, count 0 2006.189.07:45:39.64#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:45:39.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:45:39.64#ibcon#[25=USB\r\n] 2006.189.07:45:39.64#ibcon#*before write, iclass 17, count 0 2006.189.07:45:39.64#ibcon#enter sib2, iclass 17, count 0 2006.189.07:45:39.64#ibcon#flushed, iclass 17, count 0 2006.189.07:45:39.64#ibcon#about to write, iclass 17, count 0 2006.189.07:45:39.64#ibcon#wrote, iclass 17, count 0 2006.189.07:45:39.64#ibcon#about to read 3, iclass 17, count 0 2006.189.07:45:39.67#ibcon#read 3, iclass 17, count 0 2006.189.07:45:39.67#ibcon#about to read 4, iclass 17, count 0 2006.189.07:45:39.67#ibcon#read 4, iclass 17, count 0 2006.189.07:45:39.67#ibcon#about to read 5, iclass 17, count 0 2006.189.07:45:39.67#ibcon#read 5, iclass 17, count 0 2006.189.07:45:39.67#ibcon#about to read 6, iclass 17, count 0 2006.189.07:45:39.67#ibcon#read 6, iclass 17, count 0 2006.189.07:45:39.67#ibcon#end of sib2, iclass 17, count 0 2006.189.07:45:39.67#ibcon#*after write, iclass 17, count 0 2006.189.07:45:39.67#ibcon#*before return 0, iclass 17, count 0 2006.189.07:45:39.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:39.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:39.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:45:39.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:45:39.67$vc4f8/valo=6,772.99 2006.189.07:45:39.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.07:45:39.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.07:45:39.67#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:39.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:39.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:39.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:39.67#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:45:39.67#ibcon#first serial, iclass 19, count 0 2006.189.07:45:39.67#ibcon#enter sib2, iclass 19, count 0 2006.189.07:45:39.67#ibcon#flushed, iclass 19, count 0 2006.189.07:45:39.67#ibcon#about to write, iclass 19, count 0 2006.189.07:45:39.67#ibcon#wrote, iclass 19, count 0 2006.189.07:45:39.67#ibcon#about to read 3, iclass 19, count 0 2006.189.07:45:39.69#ibcon#read 3, iclass 19, count 0 2006.189.07:45:39.69#ibcon#about to read 4, iclass 19, count 0 2006.189.07:45:39.69#ibcon#read 4, iclass 19, count 0 2006.189.07:45:39.69#ibcon#about to read 5, iclass 19, count 0 2006.189.07:45:39.69#ibcon#read 5, iclass 19, count 0 2006.189.07:45:39.69#ibcon#about to read 6, iclass 19, count 0 2006.189.07:45:39.69#ibcon#read 6, iclass 19, count 0 2006.189.07:45:39.69#ibcon#end of sib2, iclass 19, count 0 2006.189.07:45:39.69#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:45:39.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:45:39.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:45:39.69#ibcon#*before write, iclass 19, count 0 2006.189.07:45:39.69#ibcon#enter sib2, iclass 19, count 0 2006.189.07:45:39.69#ibcon#flushed, iclass 19, count 0 2006.189.07:45:39.69#ibcon#about to write, iclass 19, count 0 2006.189.07:45:39.69#ibcon#wrote, iclass 19, count 0 2006.189.07:45:39.69#ibcon#about to read 3, iclass 19, count 0 2006.189.07:45:39.73#ibcon#read 3, iclass 19, count 0 2006.189.07:45:39.73#ibcon#about to read 4, iclass 19, count 0 2006.189.07:45:39.73#ibcon#read 4, iclass 19, count 0 2006.189.07:45:39.73#ibcon#about to read 5, iclass 19, count 0 2006.189.07:45:39.73#ibcon#read 5, iclass 19, count 0 2006.189.07:45:39.73#ibcon#about to read 6, iclass 19, count 0 2006.189.07:45:39.73#ibcon#read 6, iclass 19, count 0 2006.189.07:45:39.73#ibcon#end of sib2, iclass 19, count 0 2006.189.07:45:39.73#ibcon#*after write, iclass 19, count 0 2006.189.07:45:39.73#ibcon#*before return 0, iclass 19, count 0 2006.189.07:45:39.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:39.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:39.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:45:39.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:45:39.73$vc4f8/va=6,6 2006.189.07:45:39.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.07:45:39.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.07:45:39.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:39.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:39.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:39.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:39.79#ibcon#enter wrdev, iclass 21, count 2 2006.189.07:45:39.79#ibcon#first serial, iclass 21, count 2 2006.189.07:45:39.79#ibcon#enter sib2, iclass 21, count 2 2006.189.07:45:39.79#ibcon#flushed, iclass 21, count 2 2006.189.07:45:39.79#ibcon#about to write, iclass 21, count 2 2006.189.07:45:39.79#ibcon#wrote, iclass 21, count 2 2006.189.07:45:39.79#ibcon#about to read 3, iclass 21, count 2 2006.189.07:45:39.81#ibcon#read 3, iclass 21, count 2 2006.189.07:45:39.81#ibcon#about to read 4, iclass 21, count 2 2006.189.07:45:39.81#ibcon#read 4, iclass 21, count 2 2006.189.07:45:39.81#ibcon#about to read 5, iclass 21, count 2 2006.189.07:45:39.81#ibcon#read 5, iclass 21, count 2 2006.189.07:45:39.81#ibcon#about to read 6, iclass 21, count 2 2006.189.07:45:39.81#ibcon#read 6, iclass 21, count 2 2006.189.07:45:39.81#ibcon#end of sib2, iclass 21, count 2 2006.189.07:45:39.81#ibcon#*mode == 0, iclass 21, count 2 2006.189.07:45:39.81#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.07:45:39.81#ibcon#[25=AT06-06\r\n] 2006.189.07:45:39.81#ibcon#*before write, iclass 21, count 2 2006.189.07:45:39.81#ibcon#enter sib2, iclass 21, count 2 2006.189.07:45:39.81#ibcon#flushed, iclass 21, count 2 2006.189.07:45:39.81#ibcon#about to write, iclass 21, count 2 2006.189.07:45:39.81#ibcon#wrote, iclass 21, count 2 2006.189.07:45:39.81#ibcon#about to read 3, iclass 21, count 2 2006.189.07:45:39.84#ibcon#read 3, iclass 21, count 2 2006.189.07:45:39.84#ibcon#about to read 4, iclass 21, count 2 2006.189.07:45:39.84#ibcon#read 4, iclass 21, count 2 2006.189.07:45:39.84#ibcon#about to read 5, iclass 21, count 2 2006.189.07:45:39.84#ibcon#read 5, iclass 21, count 2 2006.189.07:45:39.84#ibcon#about to read 6, iclass 21, count 2 2006.189.07:45:39.84#ibcon#read 6, iclass 21, count 2 2006.189.07:45:39.84#ibcon#end of sib2, iclass 21, count 2 2006.189.07:45:39.84#ibcon#*after write, iclass 21, count 2 2006.189.07:45:39.84#ibcon#*before return 0, iclass 21, count 2 2006.189.07:45:39.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:39.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:39.84#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.07:45:39.84#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:39.84#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:39.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:39.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:39.96#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:45:39.96#ibcon#first serial, iclass 21, count 0 2006.189.07:45:39.96#ibcon#enter sib2, iclass 21, count 0 2006.189.07:45:39.96#ibcon#flushed, iclass 21, count 0 2006.189.07:45:39.96#ibcon#about to write, iclass 21, count 0 2006.189.07:45:39.96#ibcon#wrote, iclass 21, count 0 2006.189.07:45:39.96#ibcon#about to read 3, iclass 21, count 0 2006.189.07:45:39.98#ibcon#read 3, iclass 21, count 0 2006.189.07:45:39.98#ibcon#about to read 4, iclass 21, count 0 2006.189.07:45:39.98#ibcon#read 4, iclass 21, count 0 2006.189.07:45:39.98#ibcon#about to read 5, iclass 21, count 0 2006.189.07:45:39.98#ibcon#read 5, iclass 21, count 0 2006.189.07:45:39.98#ibcon#about to read 6, iclass 21, count 0 2006.189.07:45:39.98#ibcon#read 6, iclass 21, count 0 2006.189.07:45:39.98#ibcon#end of sib2, iclass 21, count 0 2006.189.07:45:39.98#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:45:39.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:45:39.98#ibcon#[25=USB\r\n] 2006.189.07:45:39.98#ibcon#*before write, iclass 21, count 0 2006.189.07:45:39.98#ibcon#enter sib2, iclass 21, count 0 2006.189.07:45:39.98#ibcon#flushed, iclass 21, count 0 2006.189.07:45:39.98#ibcon#about to write, iclass 21, count 0 2006.189.07:45:39.98#ibcon#wrote, iclass 21, count 0 2006.189.07:45:39.98#ibcon#about to read 3, iclass 21, count 0 2006.189.07:45:40.01#ibcon#read 3, iclass 21, count 0 2006.189.07:45:40.01#ibcon#about to read 4, iclass 21, count 0 2006.189.07:45:40.01#ibcon#read 4, iclass 21, count 0 2006.189.07:45:40.01#ibcon#about to read 5, iclass 21, count 0 2006.189.07:45:40.01#ibcon#read 5, iclass 21, count 0 2006.189.07:45:40.01#ibcon#about to read 6, iclass 21, count 0 2006.189.07:45:40.01#ibcon#read 6, iclass 21, count 0 2006.189.07:45:40.01#ibcon#end of sib2, iclass 21, count 0 2006.189.07:45:40.01#ibcon#*after write, iclass 21, count 0 2006.189.07:45:40.01#ibcon#*before return 0, iclass 21, count 0 2006.189.07:45:40.01#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:40.01#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:40.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:45:40.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:45:40.01$vc4f8/valo=7,832.99 2006.189.07:45:40.01#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.07:45:40.01#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.07:45:40.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:40.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:40.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:40.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:40.01#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:45:40.01#ibcon#first serial, iclass 23, count 0 2006.189.07:45:40.01#ibcon#enter sib2, iclass 23, count 0 2006.189.07:45:40.01#ibcon#flushed, iclass 23, count 0 2006.189.07:45:40.01#ibcon#about to write, iclass 23, count 0 2006.189.07:45:40.01#ibcon#wrote, iclass 23, count 0 2006.189.07:45:40.01#ibcon#about to read 3, iclass 23, count 0 2006.189.07:45:40.03#ibcon#read 3, iclass 23, count 0 2006.189.07:45:40.03#ibcon#about to read 4, iclass 23, count 0 2006.189.07:45:40.03#ibcon#read 4, iclass 23, count 0 2006.189.07:45:40.03#ibcon#about to read 5, iclass 23, count 0 2006.189.07:45:40.03#ibcon#read 5, iclass 23, count 0 2006.189.07:45:40.03#ibcon#about to read 6, iclass 23, count 0 2006.189.07:45:40.03#ibcon#read 6, iclass 23, count 0 2006.189.07:45:40.03#ibcon#end of sib2, iclass 23, count 0 2006.189.07:45:40.03#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:45:40.03#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:45:40.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:45:40.03#ibcon#*before write, iclass 23, count 0 2006.189.07:45:40.03#ibcon#enter sib2, iclass 23, count 0 2006.189.07:45:40.03#ibcon#flushed, iclass 23, count 0 2006.189.07:45:40.03#ibcon#about to write, iclass 23, count 0 2006.189.07:45:40.03#ibcon#wrote, iclass 23, count 0 2006.189.07:45:40.03#ibcon#about to read 3, iclass 23, count 0 2006.189.07:45:40.07#ibcon#read 3, iclass 23, count 0 2006.189.07:45:40.07#ibcon#about to read 4, iclass 23, count 0 2006.189.07:45:40.07#ibcon#read 4, iclass 23, count 0 2006.189.07:45:40.07#ibcon#about to read 5, iclass 23, count 0 2006.189.07:45:40.07#ibcon#read 5, iclass 23, count 0 2006.189.07:45:40.07#ibcon#about to read 6, iclass 23, count 0 2006.189.07:45:40.07#ibcon#read 6, iclass 23, count 0 2006.189.07:45:40.07#ibcon#end of sib2, iclass 23, count 0 2006.189.07:45:40.07#ibcon#*after write, iclass 23, count 0 2006.189.07:45:40.07#ibcon#*before return 0, iclass 23, count 0 2006.189.07:45:40.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:40.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:40.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:45:40.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:45:40.07$vc4f8/va=7,6 2006.189.07:45:40.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.07:45:40.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.07:45:40.07#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:40.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:45:40.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:45:40.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:45:40.13#ibcon#enter wrdev, iclass 25, count 2 2006.189.07:45:40.13#ibcon#first serial, iclass 25, count 2 2006.189.07:45:40.13#ibcon#enter sib2, iclass 25, count 2 2006.189.07:45:40.13#ibcon#flushed, iclass 25, count 2 2006.189.07:45:40.13#ibcon#about to write, iclass 25, count 2 2006.189.07:45:40.13#ibcon#wrote, iclass 25, count 2 2006.189.07:45:40.13#ibcon#about to read 3, iclass 25, count 2 2006.189.07:45:40.15#ibcon#read 3, iclass 25, count 2 2006.189.07:45:40.15#ibcon#about to read 4, iclass 25, count 2 2006.189.07:45:40.15#ibcon#read 4, iclass 25, count 2 2006.189.07:45:40.15#ibcon#about to read 5, iclass 25, count 2 2006.189.07:45:40.15#ibcon#read 5, iclass 25, count 2 2006.189.07:45:40.15#ibcon#about to read 6, iclass 25, count 2 2006.189.07:45:40.15#ibcon#read 6, iclass 25, count 2 2006.189.07:45:40.15#ibcon#end of sib2, iclass 25, count 2 2006.189.07:45:40.15#ibcon#*mode == 0, iclass 25, count 2 2006.189.07:45:40.15#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.07:45:40.15#ibcon#[25=AT07-06\r\n] 2006.189.07:45:40.15#ibcon#*before write, iclass 25, count 2 2006.189.07:45:40.15#ibcon#enter sib2, iclass 25, count 2 2006.189.07:45:40.15#ibcon#flushed, iclass 25, count 2 2006.189.07:45:40.15#ibcon#about to write, iclass 25, count 2 2006.189.07:45:40.15#ibcon#wrote, iclass 25, count 2 2006.189.07:45:40.15#ibcon#about to read 3, iclass 25, count 2 2006.189.07:45:40.18#ibcon#read 3, iclass 25, count 2 2006.189.07:45:40.18#ibcon#about to read 4, iclass 25, count 2 2006.189.07:45:40.18#ibcon#read 4, iclass 25, count 2 2006.189.07:45:40.18#ibcon#about to read 5, iclass 25, count 2 2006.189.07:45:40.18#ibcon#read 5, iclass 25, count 2 2006.189.07:45:40.18#ibcon#about to read 6, iclass 25, count 2 2006.189.07:45:40.18#ibcon#read 6, iclass 25, count 2 2006.189.07:45:40.18#ibcon#end of sib2, iclass 25, count 2 2006.189.07:45:40.18#ibcon#*after write, iclass 25, count 2 2006.189.07:45:40.18#ibcon#*before return 0, iclass 25, count 2 2006.189.07:45:40.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:45:40.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.07:45:40.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.07:45:40.18#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:40.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:45:40.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:45:40.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:45:40.30#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:45:40.30#ibcon#first serial, iclass 25, count 0 2006.189.07:45:40.30#ibcon#enter sib2, iclass 25, count 0 2006.189.07:45:40.30#ibcon#flushed, iclass 25, count 0 2006.189.07:45:40.30#ibcon#about to write, iclass 25, count 0 2006.189.07:45:40.30#ibcon#wrote, iclass 25, count 0 2006.189.07:45:40.30#ibcon#about to read 3, iclass 25, count 0 2006.189.07:45:40.32#ibcon#read 3, iclass 25, count 0 2006.189.07:45:40.32#ibcon#about to read 4, iclass 25, count 0 2006.189.07:45:40.32#ibcon#read 4, iclass 25, count 0 2006.189.07:45:40.32#ibcon#about to read 5, iclass 25, count 0 2006.189.07:45:40.32#ibcon#read 5, iclass 25, count 0 2006.189.07:45:40.32#ibcon#about to read 6, iclass 25, count 0 2006.189.07:45:40.32#ibcon#read 6, iclass 25, count 0 2006.189.07:45:40.32#ibcon#end of sib2, iclass 25, count 0 2006.189.07:45:40.32#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:45:40.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:45:40.32#ibcon#[25=USB\r\n] 2006.189.07:45:40.32#ibcon#*before write, iclass 25, count 0 2006.189.07:45:40.32#ibcon#enter sib2, iclass 25, count 0 2006.189.07:45:40.32#ibcon#flushed, iclass 25, count 0 2006.189.07:45:40.32#ibcon#about to write, iclass 25, count 0 2006.189.07:45:40.32#ibcon#wrote, iclass 25, count 0 2006.189.07:45:40.32#ibcon#about to read 3, iclass 25, count 0 2006.189.07:45:40.35#ibcon#read 3, iclass 25, count 0 2006.189.07:45:40.35#ibcon#about to read 4, iclass 25, count 0 2006.189.07:45:40.35#ibcon#read 4, iclass 25, count 0 2006.189.07:45:40.35#ibcon#about to read 5, iclass 25, count 0 2006.189.07:45:40.35#ibcon#read 5, iclass 25, count 0 2006.189.07:45:40.35#ibcon#about to read 6, iclass 25, count 0 2006.189.07:45:40.35#ibcon#read 6, iclass 25, count 0 2006.189.07:45:40.35#ibcon#end of sib2, iclass 25, count 0 2006.189.07:45:40.35#ibcon#*after write, iclass 25, count 0 2006.189.07:45:40.35#ibcon#*before return 0, iclass 25, count 0 2006.189.07:45:40.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:45:40.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.07:45:40.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:45:40.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:45:40.35$vc4f8/valo=8,852.99 2006.189.07:45:40.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.07:45:40.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.07:45:40.35#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:40.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:45:40.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:45:40.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:45:40.35#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:45:40.35#ibcon#first serial, iclass 27, count 0 2006.189.07:45:40.35#ibcon#enter sib2, iclass 27, count 0 2006.189.07:45:40.35#ibcon#flushed, iclass 27, count 0 2006.189.07:45:40.35#ibcon#about to write, iclass 27, count 0 2006.189.07:45:40.35#ibcon#wrote, iclass 27, count 0 2006.189.07:45:40.35#ibcon#about to read 3, iclass 27, count 0 2006.189.07:45:40.37#ibcon#read 3, iclass 27, count 0 2006.189.07:45:40.37#ibcon#about to read 4, iclass 27, count 0 2006.189.07:45:40.37#ibcon#read 4, iclass 27, count 0 2006.189.07:45:40.37#ibcon#about to read 5, iclass 27, count 0 2006.189.07:45:40.37#ibcon#read 5, iclass 27, count 0 2006.189.07:45:40.37#ibcon#about to read 6, iclass 27, count 0 2006.189.07:45:40.37#ibcon#read 6, iclass 27, count 0 2006.189.07:45:40.37#ibcon#end of sib2, iclass 27, count 0 2006.189.07:45:40.37#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:45:40.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:45:40.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:45:40.37#ibcon#*before write, iclass 27, count 0 2006.189.07:45:40.37#ibcon#enter sib2, iclass 27, count 0 2006.189.07:45:40.37#ibcon#flushed, iclass 27, count 0 2006.189.07:45:40.37#ibcon#about to write, iclass 27, count 0 2006.189.07:45:40.37#ibcon#wrote, iclass 27, count 0 2006.189.07:45:40.37#ibcon#about to read 3, iclass 27, count 0 2006.189.07:45:40.41#ibcon#read 3, iclass 27, count 0 2006.189.07:45:40.41#ibcon#about to read 4, iclass 27, count 0 2006.189.07:45:40.41#ibcon#read 4, iclass 27, count 0 2006.189.07:45:40.41#ibcon#about to read 5, iclass 27, count 0 2006.189.07:45:40.41#ibcon#read 5, iclass 27, count 0 2006.189.07:45:40.41#ibcon#about to read 6, iclass 27, count 0 2006.189.07:45:40.41#ibcon#read 6, iclass 27, count 0 2006.189.07:45:40.41#ibcon#end of sib2, iclass 27, count 0 2006.189.07:45:40.41#ibcon#*after write, iclass 27, count 0 2006.189.07:45:40.41#ibcon#*before return 0, iclass 27, count 0 2006.189.07:45:40.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:45:40.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.07:45:40.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:45:40.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:45:40.41$vc4f8/va=8,6 2006.189.07:45:40.41#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.07:45:40.41#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.07:45:40.41#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:40.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:45:40.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:45:40.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:45:40.47#ibcon#enter wrdev, iclass 29, count 2 2006.189.07:45:40.47#ibcon#first serial, iclass 29, count 2 2006.189.07:45:40.47#ibcon#enter sib2, iclass 29, count 2 2006.189.07:45:40.47#ibcon#flushed, iclass 29, count 2 2006.189.07:45:40.47#ibcon#about to write, iclass 29, count 2 2006.189.07:45:40.47#ibcon#wrote, iclass 29, count 2 2006.189.07:45:40.47#ibcon#about to read 3, iclass 29, count 2 2006.189.07:45:40.49#ibcon#read 3, iclass 29, count 2 2006.189.07:45:40.49#ibcon#about to read 4, iclass 29, count 2 2006.189.07:45:40.49#ibcon#read 4, iclass 29, count 2 2006.189.07:45:40.49#ibcon#about to read 5, iclass 29, count 2 2006.189.07:45:40.49#ibcon#read 5, iclass 29, count 2 2006.189.07:45:40.49#ibcon#about to read 6, iclass 29, count 2 2006.189.07:45:40.49#ibcon#read 6, iclass 29, count 2 2006.189.07:45:40.49#ibcon#end of sib2, iclass 29, count 2 2006.189.07:45:40.49#ibcon#*mode == 0, iclass 29, count 2 2006.189.07:45:40.49#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.07:45:40.49#ibcon#[25=AT08-06\r\n] 2006.189.07:45:40.49#ibcon#*before write, iclass 29, count 2 2006.189.07:45:40.49#ibcon#enter sib2, iclass 29, count 2 2006.189.07:45:40.49#ibcon#flushed, iclass 29, count 2 2006.189.07:45:40.49#ibcon#about to write, iclass 29, count 2 2006.189.07:45:40.49#ibcon#wrote, iclass 29, count 2 2006.189.07:45:40.49#ibcon#about to read 3, iclass 29, count 2 2006.189.07:45:40.52#ibcon#read 3, iclass 29, count 2 2006.189.07:45:40.52#ibcon#about to read 4, iclass 29, count 2 2006.189.07:45:40.52#ibcon#read 4, iclass 29, count 2 2006.189.07:45:40.52#ibcon#about to read 5, iclass 29, count 2 2006.189.07:45:40.52#ibcon#read 5, iclass 29, count 2 2006.189.07:45:40.52#ibcon#about to read 6, iclass 29, count 2 2006.189.07:45:40.52#ibcon#read 6, iclass 29, count 2 2006.189.07:45:40.52#ibcon#end of sib2, iclass 29, count 2 2006.189.07:45:40.52#ibcon#*after write, iclass 29, count 2 2006.189.07:45:40.52#ibcon#*before return 0, iclass 29, count 2 2006.189.07:45:40.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:45:40.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.07:45:40.52#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.07:45:40.52#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:40.52#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:45:40.64#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:45:40.64#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:45:40.64#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:45:40.64#ibcon#first serial, iclass 29, count 0 2006.189.07:45:40.64#ibcon#enter sib2, iclass 29, count 0 2006.189.07:45:40.64#ibcon#flushed, iclass 29, count 0 2006.189.07:45:40.64#ibcon#about to write, iclass 29, count 0 2006.189.07:45:40.64#ibcon#wrote, iclass 29, count 0 2006.189.07:45:40.64#ibcon#about to read 3, iclass 29, count 0 2006.189.07:45:40.66#ibcon#read 3, iclass 29, count 0 2006.189.07:45:40.66#ibcon#about to read 4, iclass 29, count 0 2006.189.07:45:40.66#ibcon#read 4, iclass 29, count 0 2006.189.07:45:40.66#ibcon#about to read 5, iclass 29, count 0 2006.189.07:45:40.66#ibcon#read 5, iclass 29, count 0 2006.189.07:45:40.66#ibcon#about to read 6, iclass 29, count 0 2006.189.07:45:40.66#ibcon#read 6, iclass 29, count 0 2006.189.07:45:40.66#ibcon#end of sib2, iclass 29, count 0 2006.189.07:45:40.66#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:45:40.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:45:40.66#ibcon#[25=USB\r\n] 2006.189.07:45:40.66#ibcon#*before write, iclass 29, count 0 2006.189.07:45:40.66#ibcon#enter sib2, iclass 29, count 0 2006.189.07:45:40.66#ibcon#flushed, iclass 29, count 0 2006.189.07:45:40.66#ibcon#about to write, iclass 29, count 0 2006.189.07:45:40.66#ibcon#wrote, iclass 29, count 0 2006.189.07:45:40.66#ibcon#about to read 3, iclass 29, count 0 2006.189.07:45:40.69#ibcon#read 3, iclass 29, count 0 2006.189.07:45:40.69#ibcon#about to read 4, iclass 29, count 0 2006.189.07:45:40.69#ibcon#read 4, iclass 29, count 0 2006.189.07:45:40.69#ibcon#about to read 5, iclass 29, count 0 2006.189.07:45:40.69#ibcon#read 5, iclass 29, count 0 2006.189.07:45:40.69#ibcon#about to read 6, iclass 29, count 0 2006.189.07:45:40.69#ibcon#read 6, iclass 29, count 0 2006.189.07:45:40.69#ibcon#end of sib2, iclass 29, count 0 2006.189.07:45:40.69#ibcon#*after write, iclass 29, count 0 2006.189.07:45:40.69#ibcon#*before return 0, iclass 29, count 0 2006.189.07:45:40.69#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:45:40.69#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.07:45:40.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:45:40.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:45:40.69$vc4f8/vblo=1,632.99 2006.189.07:45:40.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.07:45:40.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.07:45:40.69#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:40.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:45:40.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:45:40.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:45:40.69#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:45:40.69#ibcon#first serial, iclass 31, count 0 2006.189.07:45:40.69#ibcon#enter sib2, iclass 31, count 0 2006.189.07:45:40.69#ibcon#flushed, iclass 31, count 0 2006.189.07:45:40.69#ibcon#about to write, iclass 31, count 0 2006.189.07:45:40.69#ibcon#wrote, iclass 31, count 0 2006.189.07:45:40.69#ibcon#about to read 3, iclass 31, count 0 2006.189.07:45:40.71#ibcon#read 3, iclass 31, count 0 2006.189.07:45:40.71#ibcon#about to read 4, iclass 31, count 0 2006.189.07:45:40.71#ibcon#read 4, iclass 31, count 0 2006.189.07:45:40.71#ibcon#about to read 5, iclass 31, count 0 2006.189.07:45:40.71#ibcon#read 5, iclass 31, count 0 2006.189.07:45:40.71#ibcon#about to read 6, iclass 31, count 0 2006.189.07:45:40.71#ibcon#read 6, iclass 31, count 0 2006.189.07:45:40.71#ibcon#end of sib2, iclass 31, count 0 2006.189.07:45:40.71#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:45:40.71#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:45:40.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:45:40.71#ibcon#*before write, iclass 31, count 0 2006.189.07:45:40.71#ibcon#enter sib2, iclass 31, count 0 2006.189.07:45:40.71#ibcon#flushed, iclass 31, count 0 2006.189.07:45:40.71#ibcon#about to write, iclass 31, count 0 2006.189.07:45:40.71#ibcon#wrote, iclass 31, count 0 2006.189.07:45:40.71#ibcon#about to read 3, iclass 31, count 0 2006.189.07:45:40.75#ibcon#read 3, iclass 31, count 0 2006.189.07:45:40.75#ibcon#about to read 4, iclass 31, count 0 2006.189.07:45:40.75#ibcon#read 4, iclass 31, count 0 2006.189.07:45:40.75#ibcon#about to read 5, iclass 31, count 0 2006.189.07:45:40.75#ibcon#read 5, iclass 31, count 0 2006.189.07:45:40.75#ibcon#about to read 6, iclass 31, count 0 2006.189.07:45:40.75#ibcon#read 6, iclass 31, count 0 2006.189.07:45:40.75#ibcon#end of sib2, iclass 31, count 0 2006.189.07:45:40.75#ibcon#*after write, iclass 31, count 0 2006.189.07:45:40.75#ibcon#*before return 0, iclass 31, count 0 2006.189.07:45:40.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:45:40.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:45:40.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:45:40.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:45:40.75$vc4f8/vb=1,4 2006.189.07:45:40.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.07:45:40.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.07:45:40.75#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:40.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:45:40.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:45:40.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:45:40.75#ibcon#enter wrdev, iclass 33, count 2 2006.189.07:45:40.75#ibcon#first serial, iclass 33, count 2 2006.189.07:45:40.75#ibcon#enter sib2, iclass 33, count 2 2006.189.07:45:40.75#ibcon#flushed, iclass 33, count 2 2006.189.07:45:40.75#ibcon#about to write, iclass 33, count 2 2006.189.07:45:40.75#ibcon#wrote, iclass 33, count 2 2006.189.07:45:40.75#ibcon#about to read 3, iclass 33, count 2 2006.189.07:45:40.77#ibcon#read 3, iclass 33, count 2 2006.189.07:45:40.77#ibcon#about to read 4, iclass 33, count 2 2006.189.07:45:40.77#ibcon#read 4, iclass 33, count 2 2006.189.07:45:40.77#ibcon#about to read 5, iclass 33, count 2 2006.189.07:45:40.77#ibcon#read 5, iclass 33, count 2 2006.189.07:45:40.77#ibcon#about to read 6, iclass 33, count 2 2006.189.07:45:40.77#ibcon#read 6, iclass 33, count 2 2006.189.07:45:40.77#ibcon#end of sib2, iclass 33, count 2 2006.189.07:45:40.77#ibcon#*mode == 0, iclass 33, count 2 2006.189.07:45:40.77#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.07:45:40.77#ibcon#[27=AT01-04\r\n] 2006.189.07:45:40.77#ibcon#*before write, iclass 33, count 2 2006.189.07:45:40.77#ibcon#enter sib2, iclass 33, count 2 2006.189.07:45:40.77#ibcon#flushed, iclass 33, count 2 2006.189.07:45:40.77#ibcon#about to write, iclass 33, count 2 2006.189.07:45:40.77#ibcon#wrote, iclass 33, count 2 2006.189.07:45:40.77#ibcon#about to read 3, iclass 33, count 2 2006.189.07:45:40.80#ibcon#read 3, iclass 33, count 2 2006.189.07:45:40.80#ibcon#about to read 4, iclass 33, count 2 2006.189.07:45:40.80#ibcon#read 4, iclass 33, count 2 2006.189.07:45:40.80#ibcon#about to read 5, iclass 33, count 2 2006.189.07:45:40.80#ibcon#read 5, iclass 33, count 2 2006.189.07:45:40.80#ibcon#about to read 6, iclass 33, count 2 2006.189.07:45:40.80#ibcon#read 6, iclass 33, count 2 2006.189.07:45:40.80#ibcon#end of sib2, iclass 33, count 2 2006.189.07:45:40.80#ibcon#*after write, iclass 33, count 2 2006.189.07:45:40.80#ibcon#*before return 0, iclass 33, count 2 2006.189.07:45:40.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:45:40.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:45:40.80#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.07:45:40.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:40.80#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:45:40.92#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:45:40.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:45:40.92#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:45:40.92#ibcon#first serial, iclass 33, count 0 2006.189.07:45:40.92#ibcon#enter sib2, iclass 33, count 0 2006.189.07:45:40.92#ibcon#flushed, iclass 33, count 0 2006.189.07:45:40.92#ibcon#about to write, iclass 33, count 0 2006.189.07:45:40.92#ibcon#wrote, iclass 33, count 0 2006.189.07:45:40.92#ibcon#about to read 3, iclass 33, count 0 2006.189.07:45:40.94#ibcon#read 3, iclass 33, count 0 2006.189.07:45:40.94#ibcon#about to read 4, iclass 33, count 0 2006.189.07:45:40.94#ibcon#read 4, iclass 33, count 0 2006.189.07:45:40.94#ibcon#about to read 5, iclass 33, count 0 2006.189.07:45:40.94#ibcon#read 5, iclass 33, count 0 2006.189.07:45:40.94#ibcon#about to read 6, iclass 33, count 0 2006.189.07:45:40.94#ibcon#read 6, iclass 33, count 0 2006.189.07:45:40.94#ibcon#end of sib2, iclass 33, count 0 2006.189.07:45:40.94#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:45:40.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:45:40.94#ibcon#[27=USB\r\n] 2006.189.07:45:40.94#ibcon#*before write, iclass 33, count 0 2006.189.07:45:40.94#ibcon#enter sib2, iclass 33, count 0 2006.189.07:45:40.94#ibcon#flushed, iclass 33, count 0 2006.189.07:45:40.94#ibcon#about to write, iclass 33, count 0 2006.189.07:45:40.94#ibcon#wrote, iclass 33, count 0 2006.189.07:45:40.94#ibcon#about to read 3, iclass 33, count 0 2006.189.07:45:40.97#ibcon#read 3, iclass 33, count 0 2006.189.07:45:40.97#ibcon#about to read 4, iclass 33, count 0 2006.189.07:45:40.97#ibcon#read 4, iclass 33, count 0 2006.189.07:45:40.97#ibcon#about to read 5, iclass 33, count 0 2006.189.07:45:40.97#ibcon#read 5, iclass 33, count 0 2006.189.07:45:40.97#ibcon#about to read 6, iclass 33, count 0 2006.189.07:45:40.97#ibcon#read 6, iclass 33, count 0 2006.189.07:45:40.97#ibcon#end of sib2, iclass 33, count 0 2006.189.07:45:40.97#ibcon#*after write, iclass 33, count 0 2006.189.07:45:40.97#ibcon#*before return 0, iclass 33, count 0 2006.189.07:45:40.97#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:45:40.97#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:45:40.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:45:40.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:45:40.97$vc4f8/vblo=2,640.99 2006.189.07:45:40.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.07:45:40.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.07:45:40.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:40.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:40.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:40.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:40.97#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:45:40.97#ibcon#first serial, iclass 35, count 0 2006.189.07:45:40.97#ibcon#enter sib2, iclass 35, count 0 2006.189.07:45:40.97#ibcon#flushed, iclass 35, count 0 2006.189.07:45:40.97#ibcon#about to write, iclass 35, count 0 2006.189.07:45:40.97#ibcon#wrote, iclass 35, count 0 2006.189.07:45:40.97#ibcon#about to read 3, iclass 35, count 0 2006.189.07:45:40.99#ibcon#read 3, iclass 35, count 0 2006.189.07:45:40.99#ibcon#about to read 4, iclass 35, count 0 2006.189.07:45:40.99#ibcon#read 4, iclass 35, count 0 2006.189.07:45:40.99#ibcon#about to read 5, iclass 35, count 0 2006.189.07:45:40.99#ibcon#read 5, iclass 35, count 0 2006.189.07:45:40.99#ibcon#about to read 6, iclass 35, count 0 2006.189.07:45:40.99#ibcon#read 6, iclass 35, count 0 2006.189.07:45:40.99#ibcon#end of sib2, iclass 35, count 0 2006.189.07:45:40.99#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:45:40.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:45:40.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:45:40.99#ibcon#*before write, iclass 35, count 0 2006.189.07:45:40.99#ibcon#enter sib2, iclass 35, count 0 2006.189.07:45:40.99#ibcon#flushed, iclass 35, count 0 2006.189.07:45:40.99#ibcon#about to write, iclass 35, count 0 2006.189.07:45:40.99#ibcon#wrote, iclass 35, count 0 2006.189.07:45:40.99#ibcon#about to read 3, iclass 35, count 0 2006.189.07:45:41.03#ibcon#read 3, iclass 35, count 0 2006.189.07:45:41.03#ibcon#about to read 4, iclass 35, count 0 2006.189.07:45:41.03#ibcon#read 4, iclass 35, count 0 2006.189.07:45:41.03#ibcon#about to read 5, iclass 35, count 0 2006.189.07:45:41.03#ibcon#read 5, iclass 35, count 0 2006.189.07:45:41.03#ibcon#about to read 6, iclass 35, count 0 2006.189.07:45:41.03#ibcon#read 6, iclass 35, count 0 2006.189.07:45:41.03#ibcon#end of sib2, iclass 35, count 0 2006.189.07:45:41.03#ibcon#*after write, iclass 35, count 0 2006.189.07:45:41.03#ibcon#*before return 0, iclass 35, count 0 2006.189.07:45:41.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:41.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.07:45:41.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:45:41.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:45:41.03$vc4f8/vb=2,4 2006.189.07:45:41.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.07:45:41.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.07:45:41.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:41.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:41.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:41.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:41.09#ibcon#enter wrdev, iclass 37, count 2 2006.189.07:45:41.09#ibcon#first serial, iclass 37, count 2 2006.189.07:45:41.09#ibcon#enter sib2, iclass 37, count 2 2006.189.07:45:41.09#ibcon#flushed, iclass 37, count 2 2006.189.07:45:41.09#ibcon#about to write, iclass 37, count 2 2006.189.07:45:41.09#ibcon#wrote, iclass 37, count 2 2006.189.07:45:41.09#ibcon#about to read 3, iclass 37, count 2 2006.189.07:45:41.11#ibcon#read 3, iclass 37, count 2 2006.189.07:45:41.11#ibcon#about to read 4, iclass 37, count 2 2006.189.07:45:41.11#ibcon#read 4, iclass 37, count 2 2006.189.07:45:41.11#ibcon#about to read 5, iclass 37, count 2 2006.189.07:45:41.11#ibcon#read 5, iclass 37, count 2 2006.189.07:45:41.11#ibcon#about to read 6, iclass 37, count 2 2006.189.07:45:41.11#ibcon#read 6, iclass 37, count 2 2006.189.07:45:41.11#ibcon#end of sib2, iclass 37, count 2 2006.189.07:45:41.11#ibcon#*mode == 0, iclass 37, count 2 2006.189.07:45:41.11#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.07:45:41.11#ibcon#[27=AT02-04\r\n] 2006.189.07:45:41.11#ibcon#*before write, iclass 37, count 2 2006.189.07:45:41.11#ibcon#enter sib2, iclass 37, count 2 2006.189.07:45:41.11#ibcon#flushed, iclass 37, count 2 2006.189.07:45:41.11#ibcon#about to write, iclass 37, count 2 2006.189.07:45:41.11#ibcon#wrote, iclass 37, count 2 2006.189.07:45:41.11#ibcon#about to read 3, iclass 37, count 2 2006.189.07:45:41.14#ibcon#read 3, iclass 37, count 2 2006.189.07:45:41.14#ibcon#about to read 4, iclass 37, count 2 2006.189.07:45:41.14#ibcon#read 4, iclass 37, count 2 2006.189.07:45:41.14#ibcon#about to read 5, iclass 37, count 2 2006.189.07:45:41.14#ibcon#read 5, iclass 37, count 2 2006.189.07:45:41.14#ibcon#about to read 6, iclass 37, count 2 2006.189.07:45:41.14#ibcon#read 6, iclass 37, count 2 2006.189.07:45:41.14#ibcon#end of sib2, iclass 37, count 2 2006.189.07:45:41.14#ibcon#*after write, iclass 37, count 2 2006.189.07:45:41.14#ibcon#*before return 0, iclass 37, count 2 2006.189.07:45:41.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:41.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.07:45:41.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.07:45:41.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:41.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:41.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:41.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:41.26#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:45:41.26#ibcon#first serial, iclass 37, count 0 2006.189.07:45:41.26#ibcon#enter sib2, iclass 37, count 0 2006.189.07:45:41.26#ibcon#flushed, iclass 37, count 0 2006.189.07:45:41.26#ibcon#about to write, iclass 37, count 0 2006.189.07:45:41.26#ibcon#wrote, iclass 37, count 0 2006.189.07:45:41.26#ibcon#about to read 3, iclass 37, count 0 2006.189.07:45:41.28#ibcon#read 3, iclass 37, count 0 2006.189.07:45:41.28#ibcon#about to read 4, iclass 37, count 0 2006.189.07:45:41.28#ibcon#read 4, iclass 37, count 0 2006.189.07:45:41.28#ibcon#about to read 5, iclass 37, count 0 2006.189.07:45:41.28#ibcon#read 5, iclass 37, count 0 2006.189.07:45:41.28#ibcon#about to read 6, iclass 37, count 0 2006.189.07:45:41.28#ibcon#read 6, iclass 37, count 0 2006.189.07:45:41.28#ibcon#end of sib2, iclass 37, count 0 2006.189.07:45:41.28#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:45:41.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:45:41.28#ibcon#[27=USB\r\n] 2006.189.07:45:41.28#ibcon#*before write, iclass 37, count 0 2006.189.07:45:41.28#ibcon#enter sib2, iclass 37, count 0 2006.189.07:45:41.28#ibcon#flushed, iclass 37, count 0 2006.189.07:45:41.28#ibcon#about to write, iclass 37, count 0 2006.189.07:45:41.28#ibcon#wrote, iclass 37, count 0 2006.189.07:45:41.28#ibcon#about to read 3, iclass 37, count 0 2006.189.07:45:41.31#ibcon#read 3, iclass 37, count 0 2006.189.07:45:41.31#ibcon#about to read 4, iclass 37, count 0 2006.189.07:45:41.31#ibcon#read 4, iclass 37, count 0 2006.189.07:45:41.31#ibcon#about to read 5, iclass 37, count 0 2006.189.07:45:41.31#ibcon#read 5, iclass 37, count 0 2006.189.07:45:41.31#ibcon#about to read 6, iclass 37, count 0 2006.189.07:45:41.31#ibcon#read 6, iclass 37, count 0 2006.189.07:45:41.31#ibcon#end of sib2, iclass 37, count 0 2006.189.07:45:41.31#ibcon#*after write, iclass 37, count 0 2006.189.07:45:41.31#ibcon#*before return 0, iclass 37, count 0 2006.189.07:45:41.31#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:41.31#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.07:45:41.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:45:41.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:45:41.31$vc4f8/vblo=3,656.99 2006.189.07:45:41.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.07:45:41.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.07:45:41.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:41.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:41.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:41.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:41.31#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:45:41.31#ibcon#first serial, iclass 39, count 0 2006.189.07:45:41.31#ibcon#enter sib2, iclass 39, count 0 2006.189.07:45:41.31#ibcon#flushed, iclass 39, count 0 2006.189.07:45:41.31#ibcon#about to write, iclass 39, count 0 2006.189.07:45:41.31#ibcon#wrote, iclass 39, count 0 2006.189.07:45:41.31#ibcon#about to read 3, iclass 39, count 0 2006.189.07:45:41.33#ibcon#read 3, iclass 39, count 0 2006.189.07:45:41.33#ibcon#about to read 4, iclass 39, count 0 2006.189.07:45:41.33#ibcon#read 4, iclass 39, count 0 2006.189.07:45:41.33#ibcon#about to read 5, iclass 39, count 0 2006.189.07:45:41.33#ibcon#read 5, iclass 39, count 0 2006.189.07:45:41.33#ibcon#about to read 6, iclass 39, count 0 2006.189.07:45:41.33#ibcon#read 6, iclass 39, count 0 2006.189.07:45:41.33#ibcon#end of sib2, iclass 39, count 0 2006.189.07:45:41.33#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:45:41.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:45:41.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:45:41.33#ibcon#*before write, iclass 39, count 0 2006.189.07:45:41.33#ibcon#enter sib2, iclass 39, count 0 2006.189.07:45:41.33#ibcon#flushed, iclass 39, count 0 2006.189.07:45:41.33#ibcon#about to write, iclass 39, count 0 2006.189.07:45:41.33#ibcon#wrote, iclass 39, count 0 2006.189.07:45:41.33#ibcon#about to read 3, iclass 39, count 0 2006.189.07:45:41.37#ibcon#read 3, iclass 39, count 0 2006.189.07:45:41.37#ibcon#about to read 4, iclass 39, count 0 2006.189.07:45:41.37#ibcon#read 4, iclass 39, count 0 2006.189.07:45:41.37#ibcon#about to read 5, iclass 39, count 0 2006.189.07:45:41.37#ibcon#read 5, iclass 39, count 0 2006.189.07:45:41.37#ibcon#about to read 6, iclass 39, count 0 2006.189.07:45:41.37#ibcon#read 6, iclass 39, count 0 2006.189.07:45:41.37#ibcon#end of sib2, iclass 39, count 0 2006.189.07:45:41.37#ibcon#*after write, iclass 39, count 0 2006.189.07:45:41.37#ibcon#*before return 0, iclass 39, count 0 2006.189.07:45:41.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:41.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.07:45:41.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:45:41.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:45:41.37$vc4f8/vb=3,4 2006.189.07:45:41.37#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.07:45:41.37#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.07:45:41.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:41.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:41.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:41.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:41.43#ibcon#enter wrdev, iclass 3, count 2 2006.189.07:45:41.43#ibcon#first serial, iclass 3, count 2 2006.189.07:45:41.43#ibcon#enter sib2, iclass 3, count 2 2006.189.07:45:41.43#ibcon#flushed, iclass 3, count 2 2006.189.07:45:41.43#ibcon#about to write, iclass 3, count 2 2006.189.07:45:41.43#ibcon#wrote, iclass 3, count 2 2006.189.07:45:41.43#ibcon#about to read 3, iclass 3, count 2 2006.189.07:45:41.45#ibcon#read 3, iclass 3, count 2 2006.189.07:45:41.45#ibcon#about to read 4, iclass 3, count 2 2006.189.07:45:41.45#ibcon#read 4, iclass 3, count 2 2006.189.07:45:41.45#ibcon#about to read 5, iclass 3, count 2 2006.189.07:45:41.45#ibcon#read 5, iclass 3, count 2 2006.189.07:45:41.45#ibcon#about to read 6, iclass 3, count 2 2006.189.07:45:41.45#ibcon#read 6, iclass 3, count 2 2006.189.07:45:41.45#ibcon#end of sib2, iclass 3, count 2 2006.189.07:45:41.45#ibcon#*mode == 0, iclass 3, count 2 2006.189.07:45:41.45#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.07:45:41.45#ibcon#[27=AT03-04\r\n] 2006.189.07:45:41.45#ibcon#*before write, iclass 3, count 2 2006.189.07:45:41.45#ibcon#enter sib2, iclass 3, count 2 2006.189.07:45:41.45#ibcon#flushed, iclass 3, count 2 2006.189.07:45:41.45#ibcon#about to write, iclass 3, count 2 2006.189.07:45:41.45#ibcon#wrote, iclass 3, count 2 2006.189.07:45:41.45#ibcon#about to read 3, iclass 3, count 2 2006.189.07:45:41.48#ibcon#read 3, iclass 3, count 2 2006.189.07:45:41.48#ibcon#about to read 4, iclass 3, count 2 2006.189.07:45:41.48#ibcon#read 4, iclass 3, count 2 2006.189.07:45:41.48#ibcon#about to read 5, iclass 3, count 2 2006.189.07:45:41.48#ibcon#read 5, iclass 3, count 2 2006.189.07:45:41.48#ibcon#about to read 6, iclass 3, count 2 2006.189.07:45:41.48#ibcon#read 6, iclass 3, count 2 2006.189.07:45:41.48#ibcon#end of sib2, iclass 3, count 2 2006.189.07:45:41.48#ibcon#*after write, iclass 3, count 2 2006.189.07:45:41.48#ibcon#*before return 0, iclass 3, count 2 2006.189.07:45:41.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:41.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.07:45:41.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.07:45:41.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:41.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:41.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:41.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:41.60#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:45:41.60#ibcon#first serial, iclass 3, count 0 2006.189.07:45:41.60#ibcon#enter sib2, iclass 3, count 0 2006.189.07:45:41.60#ibcon#flushed, iclass 3, count 0 2006.189.07:45:41.60#ibcon#about to write, iclass 3, count 0 2006.189.07:45:41.60#ibcon#wrote, iclass 3, count 0 2006.189.07:45:41.60#ibcon#about to read 3, iclass 3, count 0 2006.189.07:45:41.62#ibcon#read 3, iclass 3, count 0 2006.189.07:45:41.62#ibcon#about to read 4, iclass 3, count 0 2006.189.07:45:41.62#ibcon#read 4, iclass 3, count 0 2006.189.07:45:41.62#ibcon#about to read 5, iclass 3, count 0 2006.189.07:45:41.62#ibcon#read 5, iclass 3, count 0 2006.189.07:45:41.62#ibcon#about to read 6, iclass 3, count 0 2006.189.07:45:41.62#ibcon#read 6, iclass 3, count 0 2006.189.07:45:41.62#ibcon#end of sib2, iclass 3, count 0 2006.189.07:45:41.62#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:45:41.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:45:41.62#ibcon#[27=USB\r\n] 2006.189.07:45:41.62#ibcon#*before write, iclass 3, count 0 2006.189.07:45:41.62#ibcon#enter sib2, iclass 3, count 0 2006.189.07:45:41.62#ibcon#flushed, iclass 3, count 0 2006.189.07:45:41.62#ibcon#about to write, iclass 3, count 0 2006.189.07:45:41.62#ibcon#wrote, iclass 3, count 0 2006.189.07:45:41.62#ibcon#about to read 3, iclass 3, count 0 2006.189.07:45:41.65#ibcon#read 3, iclass 3, count 0 2006.189.07:45:41.65#ibcon#about to read 4, iclass 3, count 0 2006.189.07:45:41.65#ibcon#read 4, iclass 3, count 0 2006.189.07:45:41.65#ibcon#about to read 5, iclass 3, count 0 2006.189.07:45:41.65#ibcon#read 5, iclass 3, count 0 2006.189.07:45:41.65#ibcon#about to read 6, iclass 3, count 0 2006.189.07:45:41.65#ibcon#read 6, iclass 3, count 0 2006.189.07:45:41.65#ibcon#end of sib2, iclass 3, count 0 2006.189.07:45:41.65#ibcon#*after write, iclass 3, count 0 2006.189.07:45:41.65#ibcon#*before return 0, iclass 3, count 0 2006.189.07:45:41.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:41.65#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.07:45:41.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:45:41.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:45:41.65$vc4f8/vblo=4,712.99 2006.189.07:45:41.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.07:45:41.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.07:45:41.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:41.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:41.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:41.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:41.65#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:45:41.65#ibcon#first serial, iclass 5, count 0 2006.189.07:45:41.65#ibcon#enter sib2, iclass 5, count 0 2006.189.07:45:41.65#ibcon#flushed, iclass 5, count 0 2006.189.07:45:41.65#ibcon#about to write, iclass 5, count 0 2006.189.07:45:41.65#ibcon#wrote, iclass 5, count 0 2006.189.07:45:41.65#ibcon#about to read 3, iclass 5, count 0 2006.189.07:45:41.67#ibcon#read 3, iclass 5, count 0 2006.189.07:45:41.67#ibcon#about to read 4, iclass 5, count 0 2006.189.07:45:41.67#ibcon#read 4, iclass 5, count 0 2006.189.07:45:41.67#ibcon#about to read 5, iclass 5, count 0 2006.189.07:45:41.67#ibcon#read 5, iclass 5, count 0 2006.189.07:45:41.67#ibcon#about to read 6, iclass 5, count 0 2006.189.07:45:41.67#ibcon#read 6, iclass 5, count 0 2006.189.07:45:41.67#ibcon#end of sib2, iclass 5, count 0 2006.189.07:45:41.67#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:45:41.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:45:41.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:45:41.67#ibcon#*before write, iclass 5, count 0 2006.189.07:45:41.67#ibcon#enter sib2, iclass 5, count 0 2006.189.07:45:41.67#ibcon#flushed, iclass 5, count 0 2006.189.07:45:41.67#ibcon#about to write, iclass 5, count 0 2006.189.07:45:41.67#ibcon#wrote, iclass 5, count 0 2006.189.07:45:41.67#ibcon#about to read 3, iclass 5, count 0 2006.189.07:45:41.71#ibcon#read 3, iclass 5, count 0 2006.189.07:45:41.71#ibcon#about to read 4, iclass 5, count 0 2006.189.07:45:41.71#ibcon#read 4, iclass 5, count 0 2006.189.07:45:41.71#ibcon#about to read 5, iclass 5, count 0 2006.189.07:45:41.71#ibcon#read 5, iclass 5, count 0 2006.189.07:45:41.71#ibcon#about to read 6, iclass 5, count 0 2006.189.07:45:41.71#ibcon#read 6, iclass 5, count 0 2006.189.07:45:41.71#ibcon#end of sib2, iclass 5, count 0 2006.189.07:45:41.71#ibcon#*after write, iclass 5, count 0 2006.189.07:45:41.71#ibcon#*before return 0, iclass 5, count 0 2006.189.07:45:41.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:41.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.07:45:41.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:45:41.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:45:41.71$vc4f8/vb=4,4 2006.189.07:45:41.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.07:45:41.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.07:45:41.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:41.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:45:41.72#abcon#<5=/04 4.4 8.1 26.11 891008.9\r\n> 2006.189.07:45:41.74#abcon#{5=INTERFACE CLEAR} 2006.189.07:45:41.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:45:41.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:45:41.77#ibcon#enter wrdev, iclass 10, count 2 2006.189.07:45:41.77#ibcon#first serial, iclass 10, count 2 2006.189.07:45:41.77#ibcon#enter sib2, iclass 10, count 2 2006.189.07:45:41.77#ibcon#flushed, iclass 10, count 2 2006.189.07:45:41.77#ibcon#about to write, iclass 10, count 2 2006.189.07:45:41.77#ibcon#wrote, iclass 10, count 2 2006.189.07:45:41.77#ibcon#about to read 3, iclass 10, count 2 2006.189.07:45:41.79#ibcon#read 3, iclass 10, count 2 2006.189.07:45:41.79#ibcon#about to read 4, iclass 10, count 2 2006.189.07:45:41.79#ibcon#read 4, iclass 10, count 2 2006.189.07:45:41.79#ibcon#about to read 5, iclass 10, count 2 2006.189.07:45:41.79#ibcon#read 5, iclass 10, count 2 2006.189.07:45:41.79#ibcon#about to read 6, iclass 10, count 2 2006.189.07:45:41.79#ibcon#read 6, iclass 10, count 2 2006.189.07:45:41.79#ibcon#end of sib2, iclass 10, count 2 2006.189.07:45:41.79#ibcon#*mode == 0, iclass 10, count 2 2006.189.07:45:41.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.07:45:41.79#ibcon#[27=AT04-04\r\n] 2006.189.07:45:41.79#ibcon#*before write, iclass 10, count 2 2006.189.07:45:41.79#ibcon#enter sib2, iclass 10, count 2 2006.189.07:45:41.79#ibcon#flushed, iclass 10, count 2 2006.189.07:45:41.79#ibcon#about to write, iclass 10, count 2 2006.189.07:45:41.79#ibcon#wrote, iclass 10, count 2 2006.189.07:45:41.79#ibcon#about to read 3, iclass 10, count 2 2006.189.07:45:41.80#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:45:41.82#ibcon#read 3, iclass 10, count 2 2006.189.07:45:41.82#ibcon#about to read 4, iclass 10, count 2 2006.189.07:45:41.82#ibcon#read 4, iclass 10, count 2 2006.189.07:45:41.82#ibcon#about to read 5, iclass 10, count 2 2006.189.07:45:41.82#ibcon#read 5, iclass 10, count 2 2006.189.07:45:41.82#ibcon#about to read 6, iclass 10, count 2 2006.189.07:45:41.82#ibcon#read 6, iclass 10, count 2 2006.189.07:45:41.82#ibcon#end of sib2, iclass 10, count 2 2006.189.07:45:41.82#ibcon#*after write, iclass 10, count 2 2006.189.07:45:41.82#ibcon#*before return 0, iclass 10, count 2 2006.189.07:45:41.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:45:41.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:45:41.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.07:45:41.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:41.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:45:41.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:45:41.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:45:41.94#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:45:41.94#ibcon#first serial, iclass 10, count 0 2006.189.07:45:41.94#ibcon#enter sib2, iclass 10, count 0 2006.189.07:45:41.94#ibcon#flushed, iclass 10, count 0 2006.189.07:45:41.94#ibcon#about to write, iclass 10, count 0 2006.189.07:45:41.94#ibcon#wrote, iclass 10, count 0 2006.189.07:45:41.94#ibcon#about to read 3, iclass 10, count 0 2006.189.07:45:41.96#ibcon#read 3, iclass 10, count 0 2006.189.07:45:41.96#ibcon#about to read 4, iclass 10, count 0 2006.189.07:45:41.96#ibcon#read 4, iclass 10, count 0 2006.189.07:45:41.96#ibcon#about to read 5, iclass 10, count 0 2006.189.07:45:41.96#ibcon#read 5, iclass 10, count 0 2006.189.07:45:41.96#ibcon#about to read 6, iclass 10, count 0 2006.189.07:45:41.96#ibcon#read 6, iclass 10, count 0 2006.189.07:45:41.96#ibcon#end of sib2, iclass 10, count 0 2006.189.07:45:41.96#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:45:41.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:45:41.96#ibcon#[27=USB\r\n] 2006.189.07:45:41.96#ibcon#*before write, iclass 10, count 0 2006.189.07:45:41.96#ibcon#enter sib2, iclass 10, count 0 2006.189.07:45:41.96#ibcon#flushed, iclass 10, count 0 2006.189.07:45:41.96#ibcon#about to write, iclass 10, count 0 2006.189.07:45:41.96#ibcon#wrote, iclass 10, count 0 2006.189.07:45:41.96#ibcon#about to read 3, iclass 10, count 0 2006.189.07:45:41.99#ibcon#read 3, iclass 10, count 0 2006.189.07:45:41.99#ibcon#about to read 4, iclass 10, count 0 2006.189.07:45:41.99#ibcon#read 4, iclass 10, count 0 2006.189.07:45:41.99#ibcon#about to read 5, iclass 10, count 0 2006.189.07:45:41.99#ibcon#read 5, iclass 10, count 0 2006.189.07:45:41.99#ibcon#about to read 6, iclass 10, count 0 2006.189.07:45:41.99#ibcon#read 6, iclass 10, count 0 2006.189.07:45:41.99#ibcon#end of sib2, iclass 10, count 0 2006.189.07:45:41.99#ibcon#*after write, iclass 10, count 0 2006.189.07:45:41.99#ibcon#*before return 0, iclass 10, count 0 2006.189.07:45:41.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:45:41.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:45:41.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:45:41.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:45:41.99$vc4f8/vblo=5,744.99 2006.189.07:45:41.99#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.07:45:41.99#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.07:45:41.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:41.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:41.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:41.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:41.99#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:45:41.99#ibcon#first serial, iclass 15, count 0 2006.189.07:45:41.99#ibcon#enter sib2, iclass 15, count 0 2006.189.07:45:41.99#ibcon#flushed, iclass 15, count 0 2006.189.07:45:41.99#ibcon#about to write, iclass 15, count 0 2006.189.07:45:41.99#ibcon#wrote, iclass 15, count 0 2006.189.07:45:41.99#ibcon#about to read 3, iclass 15, count 0 2006.189.07:45:42.01#ibcon#read 3, iclass 15, count 0 2006.189.07:45:42.01#ibcon#about to read 4, iclass 15, count 0 2006.189.07:45:42.01#ibcon#read 4, iclass 15, count 0 2006.189.07:45:42.01#ibcon#about to read 5, iclass 15, count 0 2006.189.07:45:42.01#ibcon#read 5, iclass 15, count 0 2006.189.07:45:42.01#ibcon#about to read 6, iclass 15, count 0 2006.189.07:45:42.01#ibcon#read 6, iclass 15, count 0 2006.189.07:45:42.01#ibcon#end of sib2, iclass 15, count 0 2006.189.07:45:42.01#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:45:42.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:45:42.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:45:42.01#ibcon#*before write, iclass 15, count 0 2006.189.07:45:42.01#ibcon#enter sib2, iclass 15, count 0 2006.189.07:45:42.01#ibcon#flushed, iclass 15, count 0 2006.189.07:45:42.01#ibcon#about to write, iclass 15, count 0 2006.189.07:45:42.01#ibcon#wrote, iclass 15, count 0 2006.189.07:45:42.01#ibcon#about to read 3, iclass 15, count 0 2006.189.07:45:42.05#ibcon#read 3, iclass 15, count 0 2006.189.07:45:42.05#ibcon#about to read 4, iclass 15, count 0 2006.189.07:45:42.05#ibcon#read 4, iclass 15, count 0 2006.189.07:45:42.05#ibcon#about to read 5, iclass 15, count 0 2006.189.07:45:42.05#ibcon#read 5, iclass 15, count 0 2006.189.07:45:42.05#ibcon#about to read 6, iclass 15, count 0 2006.189.07:45:42.05#ibcon#read 6, iclass 15, count 0 2006.189.07:45:42.05#ibcon#end of sib2, iclass 15, count 0 2006.189.07:45:42.05#ibcon#*after write, iclass 15, count 0 2006.189.07:45:42.05#ibcon#*before return 0, iclass 15, count 0 2006.189.07:45:42.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:42.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.07:45:42.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:45:42.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:45:42.05$vc4f8/vb=5,4 2006.189.07:45:42.05#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.07:45:42.05#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.07:45:42.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:42.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:42.11#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:42.11#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:42.11#ibcon#enter wrdev, iclass 17, count 2 2006.189.07:45:42.11#ibcon#first serial, iclass 17, count 2 2006.189.07:45:42.11#ibcon#enter sib2, iclass 17, count 2 2006.189.07:45:42.11#ibcon#flushed, iclass 17, count 2 2006.189.07:45:42.11#ibcon#about to write, iclass 17, count 2 2006.189.07:45:42.11#ibcon#wrote, iclass 17, count 2 2006.189.07:45:42.11#ibcon#about to read 3, iclass 17, count 2 2006.189.07:45:42.13#ibcon#read 3, iclass 17, count 2 2006.189.07:45:42.13#ibcon#about to read 4, iclass 17, count 2 2006.189.07:45:42.13#ibcon#read 4, iclass 17, count 2 2006.189.07:45:42.13#ibcon#about to read 5, iclass 17, count 2 2006.189.07:45:42.13#ibcon#read 5, iclass 17, count 2 2006.189.07:45:42.13#ibcon#about to read 6, iclass 17, count 2 2006.189.07:45:42.13#ibcon#read 6, iclass 17, count 2 2006.189.07:45:42.13#ibcon#end of sib2, iclass 17, count 2 2006.189.07:45:42.13#ibcon#*mode == 0, iclass 17, count 2 2006.189.07:45:42.13#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.07:45:42.13#ibcon#[27=AT05-04\r\n] 2006.189.07:45:42.13#ibcon#*before write, iclass 17, count 2 2006.189.07:45:42.13#ibcon#enter sib2, iclass 17, count 2 2006.189.07:45:42.13#ibcon#flushed, iclass 17, count 2 2006.189.07:45:42.13#ibcon#about to write, iclass 17, count 2 2006.189.07:45:42.13#ibcon#wrote, iclass 17, count 2 2006.189.07:45:42.13#ibcon#about to read 3, iclass 17, count 2 2006.189.07:45:42.16#ibcon#read 3, iclass 17, count 2 2006.189.07:45:42.16#ibcon#about to read 4, iclass 17, count 2 2006.189.07:45:42.16#ibcon#read 4, iclass 17, count 2 2006.189.07:45:42.16#ibcon#about to read 5, iclass 17, count 2 2006.189.07:45:42.16#ibcon#read 5, iclass 17, count 2 2006.189.07:45:42.16#ibcon#about to read 6, iclass 17, count 2 2006.189.07:45:42.16#ibcon#read 6, iclass 17, count 2 2006.189.07:45:42.16#ibcon#end of sib2, iclass 17, count 2 2006.189.07:45:42.16#ibcon#*after write, iclass 17, count 2 2006.189.07:45:42.16#ibcon#*before return 0, iclass 17, count 2 2006.189.07:45:42.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:42.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.07:45:42.16#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.07:45:42.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:42.16#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:42.28#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:42.28#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:42.28#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:45:42.28#ibcon#first serial, iclass 17, count 0 2006.189.07:45:42.28#ibcon#enter sib2, iclass 17, count 0 2006.189.07:45:42.28#ibcon#flushed, iclass 17, count 0 2006.189.07:45:42.28#ibcon#about to write, iclass 17, count 0 2006.189.07:45:42.28#ibcon#wrote, iclass 17, count 0 2006.189.07:45:42.28#ibcon#about to read 3, iclass 17, count 0 2006.189.07:45:42.30#ibcon#read 3, iclass 17, count 0 2006.189.07:45:42.30#ibcon#about to read 4, iclass 17, count 0 2006.189.07:45:42.30#ibcon#read 4, iclass 17, count 0 2006.189.07:45:42.30#ibcon#about to read 5, iclass 17, count 0 2006.189.07:45:42.30#ibcon#read 5, iclass 17, count 0 2006.189.07:45:42.30#ibcon#about to read 6, iclass 17, count 0 2006.189.07:45:42.30#ibcon#read 6, iclass 17, count 0 2006.189.07:45:42.30#ibcon#end of sib2, iclass 17, count 0 2006.189.07:45:42.30#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:45:42.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:45:42.30#ibcon#[27=USB\r\n] 2006.189.07:45:42.30#ibcon#*before write, iclass 17, count 0 2006.189.07:45:42.30#ibcon#enter sib2, iclass 17, count 0 2006.189.07:45:42.30#ibcon#flushed, iclass 17, count 0 2006.189.07:45:42.30#ibcon#about to write, iclass 17, count 0 2006.189.07:45:42.30#ibcon#wrote, iclass 17, count 0 2006.189.07:45:42.30#ibcon#about to read 3, iclass 17, count 0 2006.189.07:45:42.33#ibcon#read 3, iclass 17, count 0 2006.189.07:45:42.33#ibcon#about to read 4, iclass 17, count 0 2006.189.07:45:42.33#ibcon#read 4, iclass 17, count 0 2006.189.07:45:42.33#ibcon#about to read 5, iclass 17, count 0 2006.189.07:45:42.33#ibcon#read 5, iclass 17, count 0 2006.189.07:45:42.33#ibcon#about to read 6, iclass 17, count 0 2006.189.07:45:42.33#ibcon#read 6, iclass 17, count 0 2006.189.07:45:42.33#ibcon#end of sib2, iclass 17, count 0 2006.189.07:45:42.33#ibcon#*after write, iclass 17, count 0 2006.189.07:45:42.33#ibcon#*before return 0, iclass 17, count 0 2006.189.07:45:42.33#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:42.33#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.07:45:42.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:45:42.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:45:42.33$vc4f8/vblo=6,752.99 2006.189.07:45:42.33#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.07:45:42.33#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.07:45:42.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:45:42.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:42.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:42.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:42.33#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:45:42.33#ibcon#first serial, iclass 19, count 0 2006.189.07:45:42.33#ibcon#enter sib2, iclass 19, count 0 2006.189.07:45:42.33#ibcon#flushed, iclass 19, count 0 2006.189.07:45:42.33#ibcon#about to write, iclass 19, count 0 2006.189.07:45:42.33#ibcon#wrote, iclass 19, count 0 2006.189.07:45:42.33#ibcon#about to read 3, iclass 19, count 0 2006.189.07:45:42.35#ibcon#read 3, iclass 19, count 0 2006.189.07:45:42.35#ibcon#about to read 4, iclass 19, count 0 2006.189.07:45:42.35#ibcon#read 4, iclass 19, count 0 2006.189.07:45:42.35#ibcon#about to read 5, iclass 19, count 0 2006.189.07:45:42.35#ibcon#read 5, iclass 19, count 0 2006.189.07:45:42.35#ibcon#about to read 6, iclass 19, count 0 2006.189.07:45:42.35#ibcon#read 6, iclass 19, count 0 2006.189.07:45:42.35#ibcon#end of sib2, iclass 19, count 0 2006.189.07:45:42.35#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:45:42.35#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:45:42.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:45:42.35#ibcon#*before write, iclass 19, count 0 2006.189.07:45:42.35#ibcon#enter sib2, iclass 19, count 0 2006.189.07:45:42.35#ibcon#flushed, iclass 19, count 0 2006.189.07:45:42.35#ibcon#about to write, iclass 19, count 0 2006.189.07:45:42.35#ibcon#wrote, iclass 19, count 0 2006.189.07:45:42.35#ibcon#about to read 3, iclass 19, count 0 2006.189.07:45:42.39#ibcon#read 3, iclass 19, count 0 2006.189.07:45:42.39#ibcon#about to read 4, iclass 19, count 0 2006.189.07:45:42.39#ibcon#read 4, iclass 19, count 0 2006.189.07:45:42.39#ibcon#about to read 5, iclass 19, count 0 2006.189.07:45:42.39#ibcon#read 5, iclass 19, count 0 2006.189.07:45:42.39#ibcon#about to read 6, iclass 19, count 0 2006.189.07:45:42.39#ibcon#read 6, iclass 19, count 0 2006.189.07:45:42.39#ibcon#end of sib2, iclass 19, count 0 2006.189.07:45:42.39#ibcon#*after write, iclass 19, count 0 2006.189.07:45:42.39#ibcon#*before return 0, iclass 19, count 0 2006.189.07:45:42.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:42.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:45:42.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:45:42.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:45:42.39$vc4f8/vb=6,4 2006.189.07:45:42.39#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.07:45:42.39#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.07:45:42.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:45:42.39#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:42.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:42.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:42.45#ibcon#enter wrdev, iclass 21, count 2 2006.189.07:45:42.45#ibcon#first serial, iclass 21, count 2 2006.189.07:45:42.45#ibcon#enter sib2, iclass 21, count 2 2006.189.07:45:42.45#ibcon#flushed, iclass 21, count 2 2006.189.07:45:42.45#ibcon#about to write, iclass 21, count 2 2006.189.07:45:42.45#ibcon#wrote, iclass 21, count 2 2006.189.07:45:42.45#ibcon#about to read 3, iclass 21, count 2 2006.189.07:45:42.47#ibcon#read 3, iclass 21, count 2 2006.189.07:45:42.47#ibcon#about to read 4, iclass 21, count 2 2006.189.07:45:42.47#ibcon#read 4, iclass 21, count 2 2006.189.07:45:42.47#ibcon#about to read 5, iclass 21, count 2 2006.189.07:45:42.47#ibcon#read 5, iclass 21, count 2 2006.189.07:45:42.47#ibcon#about to read 6, iclass 21, count 2 2006.189.07:45:42.47#ibcon#read 6, iclass 21, count 2 2006.189.07:45:42.47#ibcon#end of sib2, iclass 21, count 2 2006.189.07:45:42.47#ibcon#*mode == 0, iclass 21, count 2 2006.189.07:45:42.47#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.07:45:42.47#ibcon#[27=AT06-04\r\n] 2006.189.07:45:42.47#ibcon#*before write, iclass 21, count 2 2006.189.07:45:42.47#ibcon#enter sib2, iclass 21, count 2 2006.189.07:45:42.47#ibcon#flushed, iclass 21, count 2 2006.189.07:45:42.47#ibcon#about to write, iclass 21, count 2 2006.189.07:45:42.47#ibcon#wrote, iclass 21, count 2 2006.189.07:45:42.47#ibcon#about to read 3, iclass 21, count 2 2006.189.07:45:42.50#ibcon#read 3, iclass 21, count 2 2006.189.07:45:42.50#ibcon#about to read 4, iclass 21, count 2 2006.189.07:45:42.50#ibcon#read 4, iclass 21, count 2 2006.189.07:45:42.50#ibcon#about to read 5, iclass 21, count 2 2006.189.07:45:42.50#ibcon#read 5, iclass 21, count 2 2006.189.07:45:42.50#ibcon#about to read 6, iclass 21, count 2 2006.189.07:45:42.50#ibcon#read 6, iclass 21, count 2 2006.189.07:45:42.50#ibcon#end of sib2, iclass 21, count 2 2006.189.07:45:42.50#ibcon#*after write, iclass 21, count 2 2006.189.07:45:42.50#ibcon#*before return 0, iclass 21, count 2 2006.189.07:45:42.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:42.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.07:45:42.50#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.07:45:42.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:45:42.50#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:42.62#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:42.62#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:42.62#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:45:42.62#ibcon#first serial, iclass 21, count 0 2006.189.07:45:42.62#ibcon#enter sib2, iclass 21, count 0 2006.189.07:45:42.62#ibcon#flushed, iclass 21, count 0 2006.189.07:45:42.62#ibcon#about to write, iclass 21, count 0 2006.189.07:45:42.62#ibcon#wrote, iclass 21, count 0 2006.189.07:45:42.62#ibcon#about to read 3, iclass 21, count 0 2006.189.07:45:42.64#ibcon#read 3, iclass 21, count 0 2006.189.07:45:42.64#ibcon#about to read 4, iclass 21, count 0 2006.189.07:45:42.64#ibcon#read 4, iclass 21, count 0 2006.189.07:45:42.64#ibcon#about to read 5, iclass 21, count 0 2006.189.07:45:42.64#ibcon#read 5, iclass 21, count 0 2006.189.07:45:42.64#ibcon#about to read 6, iclass 21, count 0 2006.189.07:45:42.64#ibcon#read 6, iclass 21, count 0 2006.189.07:45:42.64#ibcon#end of sib2, iclass 21, count 0 2006.189.07:45:42.64#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:45:42.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:45:42.64#ibcon#[27=USB\r\n] 2006.189.07:45:42.64#ibcon#*before write, iclass 21, count 0 2006.189.07:45:42.64#ibcon#enter sib2, iclass 21, count 0 2006.189.07:45:42.64#ibcon#flushed, iclass 21, count 0 2006.189.07:45:42.64#ibcon#about to write, iclass 21, count 0 2006.189.07:45:42.64#ibcon#wrote, iclass 21, count 0 2006.189.07:45:42.64#ibcon#about to read 3, iclass 21, count 0 2006.189.07:45:42.67#ibcon#read 3, iclass 21, count 0 2006.189.07:45:42.67#ibcon#about to read 4, iclass 21, count 0 2006.189.07:45:42.67#ibcon#read 4, iclass 21, count 0 2006.189.07:45:42.67#ibcon#about to read 5, iclass 21, count 0 2006.189.07:45:42.67#ibcon#read 5, iclass 21, count 0 2006.189.07:45:42.67#ibcon#about to read 6, iclass 21, count 0 2006.189.07:45:42.67#ibcon#read 6, iclass 21, count 0 2006.189.07:45:42.67#ibcon#end of sib2, iclass 21, count 0 2006.189.07:45:42.67#ibcon#*after write, iclass 21, count 0 2006.189.07:45:42.67#ibcon#*before return 0, iclass 21, count 0 2006.189.07:45:42.67#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:42.67#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.07:45:42.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:45:42.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:45:42.67$vc4f8/vabw=wide 2006.189.07:45:42.67#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.07:45:42.67#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.07:45:42.67#ibcon#ireg 8 cls_cnt 0 2006.189.07:45:42.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:42.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:42.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:42.67#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:45:42.67#ibcon#first serial, iclass 23, count 0 2006.189.07:45:42.67#ibcon#enter sib2, iclass 23, count 0 2006.189.07:45:42.67#ibcon#flushed, iclass 23, count 0 2006.189.07:45:42.67#ibcon#about to write, iclass 23, count 0 2006.189.07:45:42.67#ibcon#wrote, iclass 23, count 0 2006.189.07:45:42.67#ibcon#about to read 3, iclass 23, count 0 2006.189.07:45:42.69#ibcon#read 3, iclass 23, count 0 2006.189.07:45:42.69#ibcon#about to read 4, iclass 23, count 0 2006.189.07:45:42.69#ibcon#read 4, iclass 23, count 0 2006.189.07:45:42.69#ibcon#about to read 5, iclass 23, count 0 2006.189.07:45:42.69#ibcon#read 5, iclass 23, count 0 2006.189.07:45:42.69#ibcon#about to read 6, iclass 23, count 0 2006.189.07:45:42.69#ibcon#read 6, iclass 23, count 0 2006.189.07:45:42.69#ibcon#end of sib2, iclass 23, count 0 2006.189.07:45:42.69#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:45:42.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:45:42.69#ibcon#[25=BW32\r\n] 2006.189.07:45:42.69#ibcon#*before write, iclass 23, count 0 2006.189.07:45:42.69#ibcon#enter sib2, iclass 23, count 0 2006.189.07:45:42.69#ibcon#flushed, iclass 23, count 0 2006.189.07:45:42.69#ibcon#about to write, iclass 23, count 0 2006.189.07:45:42.69#ibcon#wrote, iclass 23, count 0 2006.189.07:45:42.69#ibcon#about to read 3, iclass 23, count 0 2006.189.07:45:42.72#ibcon#read 3, iclass 23, count 0 2006.189.07:45:42.72#ibcon#about to read 4, iclass 23, count 0 2006.189.07:45:42.72#ibcon#read 4, iclass 23, count 0 2006.189.07:45:42.72#ibcon#about to read 5, iclass 23, count 0 2006.189.07:45:42.72#ibcon#read 5, iclass 23, count 0 2006.189.07:45:42.72#ibcon#about to read 6, iclass 23, count 0 2006.189.07:45:42.72#ibcon#read 6, iclass 23, count 0 2006.189.07:45:42.72#ibcon#end of sib2, iclass 23, count 0 2006.189.07:45:42.72#ibcon#*after write, iclass 23, count 0 2006.189.07:45:42.72#ibcon#*before return 0, iclass 23, count 0 2006.189.07:45:42.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:42.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.07:45:42.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:45:42.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:45:42.72$vc4f8/vbbw=wide 2006.189.07:45:42.72#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:45:42.72#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:45:42.72#ibcon#ireg 8 cls_cnt 0 2006.189.07:45:42.72#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:45:42.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:45:42.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:45:42.79#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:45:42.79#ibcon#first serial, iclass 25, count 0 2006.189.07:45:42.79#ibcon#enter sib2, iclass 25, count 0 2006.189.07:45:42.79#ibcon#flushed, iclass 25, count 0 2006.189.07:45:42.79#ibcon#about to write, iclass 25, count 0 2006.189.07:45:42.79#ibcon#wrote, iclass 25, count 0 2006.189.07:45:42.79#ibcon#about to read 3, iclass 25, count 0 2006.189.07:45:42.81#ibcon#read 3, iclass 25, count 0 2006.189.07:45:42.81#ibcon#about to read 4, iclass 25, count 0 2006.189.07:45:42.81#ibcon#read 4, iclass 25, count 0 2006.189.07:45:42.81#ibcon#about to read 5, iclass 25, count 0 2006.189.07:45:42.81#ibcon#read 5, iclass 25, count 0 2006.189.07:45:42.81#ibcon#about to read 6, iclass 25, count 0 2006.189.07:45:42.81#ibcon#read 6, iclass 25, count 0 2006.189.07:45:42.81#ibcon#end of sib2, iclass 25, count 0 2006.189.07:45:42.81#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:45:42.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:45:42.81#ibcon#[27=BW32\r\n] 2006.189.07:45:42.81#ibcon#*before write, iclass 25, count 0 2006.189.07:45:42.81#ibcon#enter sib2, iclass 25, count 0 2006.189.07:45:42.81#ibcon#flushed, iclass 25, count 0 2006.189.07:45:42.81#ibcon#about to write, iclass 25, count 0 2006.189.07:45:42.81#ibcon#wrote, iclass 25, count 0 2006.189.07:45:42.81#ibcon#about to read 3, iclass 25, count 0 2006.189.07:45:42.84#ibcon#read 3, iclass 25, count 0 2006.189.07:45:42.84#ibcon#about to read 4, iclass 25, count 0 2006.189.07:45:42.84#ibcon#read 4, iclass 25, count 0 2006.189.07:45:42.84#ibcon#about to read 5, iclass 25, count 0 2006.189.07:45:42.84#ibcon#read 5, iclass 25, count 0 2006.189.07:45:42.84#ibcon#about to read 6, iclass 25, count 0 2006.189.07:45:42.84#ibcon#read 6, iclass 25, count 0 2006.189.07:45:42.84#ibcon#end of sib2, iclass 25, count 0 2006.189.07:45:42.84#ibcon#*after write, iclass 25, count 0 2006.189.07:45:42.84#ibcon#*before return 0, iclass 25, count 0 2006.189.07:45:42.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:45:42.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:45:42.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:45:42.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:45:42.84$4f8m12a/ifd4f 2006.189.07:45:42.84$ifd4f/lo= 2006.189.07:45:42.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:45:42.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:45:42.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:45:42.84$ifd4f/patch= 2006.189.07:45:42.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:45:42.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:45:42.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:45:42.84$4f8m12a/"form=m,16.000,1:2 2006.189.07:45:42.84$4f8m12a/"tpicd 2006.189.07:45:42.84$4f8m12a/echo=off 2006.189.07:45:42.84$4f8m12a/xlog=off 2006.189.07:45:42.84:!2006.189.07:46:20 2006.189.07:45:59.14#trakl#Source acquired 2006.189.07:46:01.14#flagr#flagr/antenna,acquired 2006.189.07:46:20.00:preob 2006.189.07:46:20.14/onsource/TRACKING 2006.189.07:46:20.14:!2006.189.07:46:30 2006.189.07:46:30.00:data_valid=on 2006.189.07:46:30.00:midob 2006.189.07:46:31.14/onsource/TRACKING 2006.189.07:46:31.14/wx/26.09,1008.9,88 2006.189.07:46:31.32/cable/+6.4543E-03 2006.189.07:46:32.41/va/01,08,usb,yes,29,31 2006.189.07:46:32.41/va/02,07,usb,yes,29,31 2006.189.07:46:32.41/va/03,06,usb,yes,31,31 2006.189.07:46:32.41/va/04,07,usb,yes,30,33 2006.189.07:46:32.41/va/05,07,usb,yes,32,34 2006.189.07:46:32.41/va/06,06,usb,yes,31,31 2006.189.07:46:32.41/va/07,06,usb,yes,32,31 2006.189.07:46:32.41/va/08,06,usb,yes,34,33 2006.189.07:46:32.64/valo/01,532.99,yes,locked 2006.189.07:46:32.64/valo/02,572.99,yes,locked 2006.189.07:46:32.64/valo/03,672.99,yes,locked 2006.189.07:46:32.64/valo/04,832.99,yes,locked 2006.189.07:46:32.64/valo/05,652.99,yes,locked 2006.189.07:46:32.64/valo/06,772.99,yes,locked 2006.189.07:46:32.64/valo/07,832.99,yes,locked 2006.189.07:46:32.64/valo/08,852.99,yes,locked 2006.189.07:46:33.73/vb/01,04,usb,yes,29,28 2006.189.07:46:33.73/vb/02,04,usb,yes,31,32 2006.189.07:46:33.73/vb/03,04,usb,yes,27,31 2006.189.07:46:33.73/vb/04,04,usb,yes,28,28 2006.189.07:46:33.73/vb/05,04,usb,yes,27,31 2006.189.07:46:33.73/vb/06,04,usb,yes,28,30 2006.189.07:46:33.73/vb/07,04,usb,yes,30,29 2006.189.07:46:33.73/vb/08,04,usb,yes,27,30 2006.189.07:46:33.96/vblo/01,632.99,yes,locked 2006.189.07:46:33.96/vblo/02,640.99,yes,locked 2006.189.07:46:33.96/vblo/03,656.99,yes,locked 2006.189.07:46:33.96/vblo/04,712.99,yes,locked 2006.189.07:46:33.96/vblo/05,744.99,yes,locked 2006.189.07:46:33.96/vblo/06,752.99,yes,locked 2006.189.07:46:33.96/vblo/07,734.99,yes,locked 2006.189.07:46:33.96/vblo/08,744.99,yes,locked 2006.189.07:46:34.11/vabw/8 2006.189.07:46:34.26/vbbw/8 2006.189.07:46:34.35/xfe/off,on,15.2 2006.189.07:46:34.73/ifatt/23,28,28,28 2006.189.07:46:35.07/fmout-gps/S +2.97E-07 2006.189.07:46:35.16:!2006.189.07:47:30 2006.189.07:47:30.01:data_valid=off 2006.189.07:47:30.02:postob 2006.189.07:47:30.12/cable/+6.4524E-03 2006.189.07:47:30.13/wx/26.06,1009.0,88 2006.189.07:47:31.08/fmout-gps/S +2.98E-07 2006.189.07:47:31.08:scan_name=189-0748,k06189,60 2006.189.07:47:31.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.189.07:47:31.14#flagr#flagr/antenna,new-source 2006.189.07:47:32.14:checkk5 2006.189.07:47:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:47:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:47:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:47:33.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:47:34.05/chk_obsdata//k5ts1/T1890746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:47:34.43/chk_obsdata//k5ts2/T1890746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:47:34.81/chk_obsdata//k5ts3/T1890746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:47:35.18/chk_obsdata//k5ts4/T1890746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:47:35.88/k5log//k5ts1_log_newline 2006.189.07:47:36.58/k5log//k5ts2_log_newline 2006.189.07:47:37.28/k5log//k5ts3_log_newline 2006.189.07:47:37.98/k5log//k5ts4_log_newline 2006.189.07:47:38.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:47:38.00:4f8m12a=1 2006.189.07:47:38.00$4f8m12a/echo=on 2006.189.07:47:38.00$4f8m12a/pcalon 2006.189.07:47:38.00$pcalon/"no phase cal control is implemented here 2006.189.07:47:38.00$4f8m12a/"tpicd=stop 2006.189.07:47:38.00$4f8m12a/vc4f8 2006.189.07:47:38.00$vc4f8/valo=1,532.99 2006.189.07:47:38.00#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.07:47:38.00#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.07:47:38.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:38.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:38.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:38.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:38.00#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:47:38.00#ibcon#first serial, iclass 36, count 0 2006.189.07:47:38.00#ibcon#enter sib2, iclass 36, count 0 2006.189.07:47:38.00#ibcon#flushed, iclass 36, count 0 2006.189.07:47:38.00#ibcon#about to write, iclass 36, count 0 2006.189.07:47:38.00#ibcon#wrote, iclass 36, count 0 2006.189.07:47:38.00#ibcon#about to read 3, iclass 36, count 0 2006.189.07:47:38.05#ibcon#read 3, iclass 36, count 0 2006.189.07:47:38.05#ibcon#about to read 4, iclass 36, count 0 2006.189.07:47:38.05#ibcon#read 4, iclass 36, count 0 2006.189.07:47:38.05#ibcon#about to read 5, iclass 36, count 0 2006.189.07:47:38.05#ibcon#read 5, iclass 36, count 0 2006.189.07:47:38.05#ibcon#about to read 6, iclass 36, count 0 2006.189.07:47:38.05#ibcon#read 6, iclass 36, count 0 2006.189.07:47:38.05#ibcon#end of sib2, iclass 36, count 0 2006.189.07:47:38.05#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:47:38.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:47:38.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:47:38.05#ibcon#*before write, iclass 36, count 0 2006.189.07:47:38.05#ibcon#enter sib2, iclass 36, count 0 2006.189.07:47:38.05#ibcon#flushed, iclass 36, count 0 2006.189.07:47:38.05#ibcon#about to write, iclass 36, count 0 2006.189.07:47:38.05#ibcon#wrote, iclass 36, count 0 2006.189.07:47:38.05#ibcon#about to read 3, iclass 36, count 0 2006.189.07:47:38.10#ibcon#read 3, iclass 36, count 0 2006.189.07:47:38.10#ibcon#about to read 4, iclass 36, count 0 2006.189.07:47:38.10#ibcon#read 4, iclass 36, count 0 2006.189.07:47:38.10#ibcon#about to read 5, iclass 36, count 0 2006.189.07:47:38.10#ibcon#read 5, iclass 36, count 0 2006.189.07:47:38.10#ibcon#about to read 6, iclass 36, count 0 2006.189.07:47:38.10#ibcon#read 6, iclass 36, count 0 2006.189.07:47:38.10#ibcon#end of sib2, iclass 36, count 0 2006.189.07:47:38.10#ibcon#*after write, iclass 36, count 0 2006.189.07:47:38.10#ibcon#*before return 0, iclass 36, count 0 2006.189.07:47:38.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:38.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:38.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:47:38.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:47:38.10$vc4f8/va=1,8 2006.189.07:47:38.10#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.07:47:38.10#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.07:47:38.10#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:38.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:38.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:38.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:38.10#ibcon#enter wrdev, iclass 38, count 2 2006.189.07:47:38.10#ibcon#first serial, iclass 38, count 2 2006.189.07:47:38.10#ibcon#enter sib2, iclass 38, count 2 2006.189.07:47:38.10#ibcon#flushed, iclass 38, count 2 2006.189.07:47:38.10#ibcon#about to write, iclass 38, count 2 2006.189.07:47:38.10#ibcon#wrote, iclass 38, count 2 2006.189.07:47:38.10#ibcon#about to read 3, iclass 38, count 2 2006.189.07:47:38.12#ibcon#read 3, iclass 38, count 2 2006.189.07:47:38.12#ibcon#about to read 4, iclass 38, count 2 2006.189.07:47:38.12#ibcon#read 4, iclass 38, count 2 2006.189.07:47:38.12#ibcon#about to read 5, iclass 38, count 2 2006.189.07:47:38.12#ibcon#read 5, iclass 38, count 2 2006.189.07:47:38.12#ibcon#about to read 6, iclass 38, count 2 2006.189.07:47:38.12#ibcon#read 6, iclass 38, count 2 2006.189.07:47:38.12#ibcon#end of sib2, iclass 38, count 2 2006.189.07:47:38.12#ibcon#*mode == 0, iclass 38, count 2 2006.189.07:47:38.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.07:47:38.12#ibcon#[25=AT01-08\r\n] 2006.189.07:47:38.12#ibcon#*before write, iclass 38, count 2 2006.189.07:47:38.12#ibcon#enter sib2, iclass 38, count 2 2006.189.07:47:38.12#ibcon#flushed, iclass 38, count 2 2006.189.07:47:38.12#ibcon#about to write, iclass 38, count 2 2006.189.07:47:38.12#ibcon#wrote, iclass 38, count 2 2006.189.07:47:38.12#ibcon#about to read 3, iclass 38, count 2 2006.189.07:47:38.15#ibcon#read 3, iclass 38, count 2 2006.189.07:47:38.15#ibcon#about to read 4, iclass 38, count 2 2006.189.07:47:38.15#ibcon#read 4, iclass 38, count 2 2006.189.07:47:38.15#ibcon#about to read 5, iclass 38, count 2 2006.189.07:47:38.15#ibcon#read 5, iclass 38, count 2 2006.189.07:47:38.15#ibcon#about to read 6, iclass 38, count 2 2006.189.07:47:38.15#ibcon#read 6, iclass 38, count 2 2006.189.07:47:38.15#ibcon#end of sib2, iclass 38, count 2 2006.189.07:47:38.15#ibcon#*after write, iclass 38, count 2 2006.189.07:47:38.15#ibcon#*before return 0, iclass 38, count 2 2006.189.07:47:38.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:38.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:38.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.07:47:38.15#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:38.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:38.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:38.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:38.27#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:47:38.27#ibcon#first serial, iclass 38, count 0 2006.189.07:47:38.27#ibcon#enter sib2, iclass 38, count 0 2006.189.07:47:38.27#ibcon#flushed, iclass 38, count 0 2006.189.07:47:38.27#ibcon#about to write, iclass 38, count 0 2006.189.07:47:38.27#ibcon#wrote, iclass 38, count 0 2006.189.07:47:38.27#ibcon#about to read 3, iclass 38, count 0 2006.189.07:47:38.29#ibcon#read 3, iclass 38, count 0 2006.189.07:47:38.29#ibcon#about to read 4, iclass 38, count 0 2006.189.07:47:38.29#ibcon#read 4, iclass 38, count 0 2006.189.07:47:38.29#ibcon#about to read 5, iclass 38, count 0 2006.189.07:47:38.29#ibcon#read 5, iclass 38, count 0 2006.189.07:47:38.29#ibcon#about to read 6, iclass 38, count 0 2006.189.07:47:38.29#ibcon#read 6, iclass 38, count 0 2006.189.07:47:38.29#ibcon#end of sib2, iclass 38, count 0 2006.189.07:47:38.29#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:47:38.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:47:38.29#ibcon#[25=USB\r\n] 2006.189.07:47:38.29#ibcon#*before write, iclass 38, count 0 2006.189.07:47:38.29#ibcon#enter sib2, iclass 38, count 0 2006.189.07:47:38.29#ibcon#flushed, iclass 38, count 0 2006.189.07:47:38.29#ibcon#about to write, iclass 38, count 0 2006.189.07:47:38.29#ibcon#wrote, iclass 38, count 0 2006.189.07:47:38.29#ibcon#about to read 3, iclass 38, count 0 2006.189.07:47:38.32#ibcon#read 3, iclass 38, count 0 2006.189.07:47:38.32#ibcon#about to read 4, iclass 38, count 0 2006.189.07:47:38.32#ibcon#read 4, iclass 38, count 0 2006.189.07:47:38.32#ibcon#about to read 5, iclass 38, count 0 2006.189.07:47:38.32#ibcon#read 5, iclass 38, count 0 2006.189.07:47:38.32#ibcon#about to read 6, iclass 38, count 0 2006.189.07:47:38.32#ibcon#read 6, iclass 38, count 0 2006.189.07:47:38.32#ibcon#end of sib2, iclass 38, count 0 2006.189.07:47:38.32#ibcon#*after write, iclass 38, count 0 2006.189.07:47:38.32#ibcon#*before return 0, iclass 38, count 0 2006.189.07:47:38.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:38.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:38.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:47:38.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:47:38.32$vc4f8/valo=2,572.99 2006.189.07:47:38.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.07:47:38.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.07:47:38.32#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:38.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:38.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:38.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:38.32#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:47:38.32#ibcon#first serial, iclass 40, count 0 2006.189.07:47:38.32#ibcon#enter sib2, iclass 40, count 0 2006.189.07:47:38.32#ibcon#flushed, iclass 40, count 0 2006.189.07:47:38.32#ibcon#about to write, iclass 40, count 0 2006.189.07:47:38.32#ibcon#wrote, iclass 40, count 0 2006.189.07:47:38.32#ibcon#about to read 3, iclass 40, count 0 2006.189.07:47:38.34#ibcon#read 3, iclass 40, count 0 2006.189.07:47:38.34#ibcon#about to read 4, iclass 40, count 0 2006.189.07:47:38.34#ibcon#read 4, iclass 40, count 0 2006.189.07:47:38.34#ibcon#about to read 5, iclass 40, count 0 2006.189.07:47:38.34#ibcon#read 5, iclass 40, count 0 2006.189.07:47:38.34#ibcon#about to read 6, iclass 40, count 0 2006.189.07:47:38.34#ibcon#read 6, iclass 40, count 0 2006.189.07:47:38.34#ibcon#end of sib2, iclass 40, count 0 2006.189.07:47:38.34#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:47:38.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:47:38.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:47:38.34#ibcon#*before write, iclass 40, count 0 2006.189.07:47:38.34#ibcon#enter sib2, iclass 40, count 0 2006.189.07:47:38.34#ibcon#flushed, iclass 40, count 0 2006.189.07:47:38.34#ibcon#about to write, iclass 40, count 0 2006.189.07:47:38.34#ibcon#wrote, iclass 40, count 0 2006.189.07:47:38.34#ibcon#about to read 3, iclass 40, count 0 2006.189.07:47:38.38#ibcon#read 3, iclass 40, count 0 2006.189.07:47:38.38#ibcon#about to read 4, iclass 40, count 0 2006.189.07:47:38.38#ibcon#read 4, iclass 40, count 0 2006.189.07:47:38.38#ibcon#about to read 5, iclass 40, count 0 2006.189.07:47:38.38#ibcon#read 5, iclass 40, count 0 2006.189.07:47:38.38#ibcon#about to read 6, iclass 40, count 0 2006.189.07:47:38.38#ibcon#read 6, iclass 40, count 0 2006.189.07:47:38.38#ibcon#end of sib2, iclass 40, count 0 2006.189.07:47:38.38#ibcon#*after write, iclass 40, count 0 2006.189.07:47:38.38#ibcon#*before return 0, iclass 40, count 0 2006.189.07:47:38.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:38.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:38.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:47:38.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:47:38.38$vc4f8/va=2,7 2006.189.07:47:38.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.07:47:38.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.07:47:38.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:38.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:38.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:38.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:38.44#ibcon#enter wrdev, iclass 4, count 2 2006.189.07:47:38.44#ibcon#first serial, iclass 4, count 2 2006.189.07:47:38.44#ibcon#enter sib2, iclass 4, count 2 2006.189.07:47:38.44#ibcon#flushed, iclass 4, count 2 2006.189.07:47:38.44#ibcon#about to write, iclass 4, count 2 2006.189.07:47:38.44#ibcon#wrote, iclass 4, count 2 2006.189.07:47:38.44#ibcon#about to read 3, iclass 4, count 2 2006.189.07:47:38.46#ibcon#read 3, iclass 4, count 2 2006.189.07:47:38.46#ibcon#about to read 4, iclass 4, count 2 2006.189.07:47:38.46#ibcon#read 4, iclass 4, count 2 2006.189.07:47:38.46#ibcon#about to read 5, iclass 4, count 2 2006.189.07:47:38.46#ibcon#read 5, iclass 4, count 2 2006.189.07:47:38.46#ibcon#about to read 6, iclass 4, count 2 2006.189.07:47:38.46#ibcon#read 6, iclass 4, count 2 2006.189.07:47:38.46#ibcon#end of sib2, iclass 4, count 2 2006.189.07:47:38.46#ibcon#*mode == 0, iclass 4, count 2 2006.189.07:47:38.46#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.07:47:38.46#ibcon#[25=AT02-07\r\n] 2006.189.07:47:38.46#ibcon#*before write, iclass 4, count 2 2006.189.07:47:38.46#ibcon#enter sib2, iclass 4, count 2 2006.189.07:47:38.46#ibcon#flushed, iclass 4, count 2 2006.189.07:47:38.46#ibcon#about to write, iclass 4, count 2 2006.189.07:47:38.46#ibcon#wrote, iclass 4, count 2 2006.189.07:47:38.46#ibcon#about to read 3, iclass 4, count 2 2006.189.07:47:38.49#ibcon#read 3, iclass 4, count 2 2006.189.07:47:38.49#ibcon#about to read 4, iclass 4, count 2 2006.189.07:47:38.49#ibcon#read 4, iclass 4, count 2 2006.189.07:47:38.49#ibcon#about to read 5, iclass 4, count 2 2006.189.07:47:38.49#ibcon#read 5, iclass 4, count 2 2006.189.07:47:38.49#ibcon#about to read 6, iclass 4, count 2 2006.189.07:47:38.49#ibcon#read 6, iclass 4, count 2 2006.189.07:47:38.49#ibcon#end of sib2, iclass 4, count 2 2006.189.07:47:38.49#ibcon#*after write, iclass 4, count 2 2006.189.07:47:38.49#ibcon#*before return 0, iclass 4, count 2 2006.189.07:47:38.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:38.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:38.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.07:47:38.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:38.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:38.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:38.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:38.61#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:47:38.61#ibcon#first serial, iclass 4, count 0 2006.189.07:47:38.61#ibcon#enter sib2, iclass 4, count 0 2006.189.07:47:38.61#ibcon#flushed, iclass 4, count 0 2006.189.07:47:38.61#ibcon#about to write, iclass 4, count 0 2006.189.07:47:38.61#ibcon#wrote, iclass 4, count 0 2006.189.07:47:38.61#ibcon#about to read 3, iclass 4, count 0 2006.189.07:47:38.63#ibcon#read 3, iclass 4, count 0 2006.189.07:47:38.63#ibcon#about to read 4, iclass 4, count 0 2006.189.07:47:38.63#ibcon#read 4, iclass 4, count 0 2006.189.07:47:38.63#ibcon#about to read 5, iclass 4, count 0 2006.189.07:47:38.63#ibcon#read 5, iclass 4, count 0 2006.189.07:47:38.63#ibcon#about to read 6, iclass 4, count 0 2006.189.07:47:38.63#ibcon#read 6, iclass 4, count 0 2006.189.07:47:38.63#ibcon#end of sib2, iclass 4, count 0 2006.189.07:47:38.63#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:47:38.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:47:38.63#ibcon#[25=USB\r\n] 2006.189.07:47:38.63#ibcon#*before write, iclass 4, count 0 2006.189.07:47:38.63#ibcon#enter sib2, iclass 4, count 0 2006.189.07:47:38.63#ibcon#flushed, iclass 4, count 0 2006.189.07:47:38.63#ibcon#about to write, iclass 4, count 0 2006.189.07:47:38.63#ibcon#wrote, iclass 4, count 0 2006.189.07:47:38.63#ibcon#about to read 3, iclass 4, count 0 2006.189.07:47:38.66#ibcon#read 3, iclass 4, count 0 2006.189.07:47:38.66#ibcon#about to read 4, iclass 4, count 0 2006.189.07:47:38.66#ibcon#read 4, iclass 4, count 0 2006.189.07:47:38.66#ibcon#about to read 5, iclass 4, count 0 2006.189.07:47:38.66#ibcon#read 5, iclass 4, count 0 2006.189.07:47:38.66#ibcon#about to read 6, iclass 4, count 0 2006.189.07:47:38.66#ibcon#read 6, iclass 4, count 0 2006.189.07:47:38.66#ibcon#end of sib2, iclass 4, count 0 2006.189.07:47:38.66#ibcon#*after write, iclass 4, count 0 2006.189.07:47:38.66#ibcon#*before return 0, iclass 4, count 0 2006.189.07:47:38.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:38.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:38.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:47:38.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:47:38.66$vc4f8/valo=3,672.99 2006.189.07:47:38.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:47:38.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:47:38.66#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:38.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:38.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:38.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:38.66#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:47:38.66#ibcon#first serial, iclass 6, count 0 2006.189.07:47:38.66#ibcon#enter sib2, iclass 6, count 0 2006.189.07:47:38.66#ibcon#flushed, iclass 6, count 0 2006.189.07:47:38.66#ibcon#about to write, iclass 6, count 0 2006.189.07:47:38.66#ibcon#wrote, iclass 6, count 0 2006.189.07:47:38.66#ibcon#about to read 3, iclass 6, count 0 2006.189.07:47:38.68#ibcon#read 3, iclass 6, count 0 2006.189.07:47:38.68#ibcon#about to read 4, iclass 6, count 0 2006.189.07:47:38.68#ibcon#read 4, iclass 6, count 0 2006.189.07:47:38.68#ibcon#about to read 5, iclass 6, count 0 2006.189.07:47:38.68#ibcon#read 5, iclass 6, count 0 2006.189.07:47:38.68#ibcon#about to read 6, iclass 6, count 0 2006.189.07:47:38.68#ibcon#read 6, iclass 6, count 0 2006.189.07:47:38.68#ibcon#end of sib2, iclass 6, count 0 2006.189.07:47:38.68#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:47:38.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:47:38.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:47:38.68#ibcon#*before write, iclass 6, count 0 2006.189.07:47:38.68#ibcon#enter sib2, iclass 6, count 0 2006.189.07:47:38.68#ibcon#flushed, iclass 6, count 0 2006.189.07:47:38.68#ibcon#about to write, iclass 6, count 0 2006.189.07:47:38.68#ibcon#wrote, iclass 6, count 0 2006.189.07:47:38.68#ibcon#about to read 3, iclass 6, count 0 2006.189.07:47:38.72#ibcon#read 3, iclass 6, count 0 2006.189.07:47:38.72#ibcon#about to read 4, iclass 6, count 0 2006.189.07:47:38.72#ibcon#read 4, iclass 6, count 0 2006.189.07:47:38.72#ibcon#about to read 5, iclass 6, count 0 2006.189.07:47:38.72#ibcon#read 5, iclass 6, count 0 2006.189.07:47:38.72#ibcon#about to read 6, iclass 6, count 0 2006.189.07:47:38.72#ibcon#read 6, iclass 6, count 0 2006.189.07:47:38.72#ibcon#end of sib2, iclass 6, count 0 2006.189.07:47:38.72#ibcon#*after write, iclass 6, count 0 2006.189.07:47:38.72#ibcon#*before return 0, iclass 6, count 0 2006.189.07:47:38.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:38.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:38.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:47:38.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:47:38.72$vc4f8/va=3,6 2006.189.07:47:38.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.07:47:38.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.07:47:38.72#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:38.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:38.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:38.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:38.78#ibcon#enter wrdev, iclass 10, count 2 2006.189.07:47:38.78#ibcon#first serial, iclass 10, count 2 2006.189.07:47:38.78#ibcon#enter sib2, iclass 10, count 2 2006.189.07:47:38.78#ibcon#flushed, iclass 10, count 2 2006.189.07:47:38.78#ibcon#about to write, iclass 10, count 2 2006.189.07:47:38.78#ibcon#wrote, iclass 10, count 2 2006.189.07:47:38.78#ibcon#about to read 3, iclass 10, count 2 2006.189.07:47:38.80#ibcon#read 3, iclass 10, count 2 2006.189.07:47:38.80#ibcon#about to read 4, iclass 10, count 2 2006.189.07:47:38.80#ibcon#read 4, iclass 10, count 2 2006.189.07:47:38.80#ibcon#about to read 5, iclass 10, count 2 2006.189.07:47:38.80#ibcon#read 5, iclass 10, count 2 2006.189.07:47:38.80#ibcon#about to read 6, iclass 10, count 2 2006.189.07:47:38.80#ibcon#read 6, iclass 10, count 2 2006.189.07:47:38.80#ibcon#end of sib2, iclass 10, count 2 2006.189.07:47:38.80#ibcon#*mode == 0, iclass 10, count 2 2006.189.07:47:38.80#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.07:47:38.80#ibcon#[25=AT03-06\r\n] 2006.189.07:47:38.80#ibcon#*before write, iclass 10, count 2 2006.189.07:47:38.80#ibcon#enter sib2, iclass 10, count 2 2006.189.07:47:38.80#ibcon#flushed, iclass 10, count 2 2006.189.07:47:38.80#ibcon#about to write, iclass 10, count 2 2006.189.07:47:38.80#ibcon#wrote, iclass 10, count 2 2006.189.07:47:38.80#ibcon#about to read 3, iclass 10, count 2 2006.189.07:47:38.83#ibcon#read 3, iclass 10, count 2 2006.189.07:47:38.83#ibcon#about to read 4, iclass 10, count 2 2006.189.07:47:38.83#ibcon#read 4, iclass 10, count 2 2006.189.07:47:38.83#ibcon#about to read 5, iclass 10, count 2 2006.189.07:47:38.83#ibcon#read 5, iclass 10, count 2 2006.189.07:47:38.83#ibcon#about to read 6, iclass 10, count 2 2006.189.07:47:38.83#ibcon#read 6, iclass 10, count 2 2006.189.07:47:38.83#ibcon#end of sib2, iclass 10, count 2 2006.189.07:47:38.83#ibcon#*after write, iclass 10, count 2 2006.189.07:47:38.83#ibcon#*before return 0, iclass 10, count 2 2006.189.07:47:38.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:38.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:38.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.07:47:38.83#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:38.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:38.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:38.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:38.95#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:47:38.95#ibcon#first serial, iclass 10, count 0 2006.189.07:47:38.95#ibcon#enter sib2, iclass 10, count 0 2006.189.07:47:38.95#ibcon#flushed, iclass 10, count 0 2006.189.07:47:38.95#ibcon#about to write, iclass 10, count 0 2006.189.07:47:38.95#ibcon#wrote, iclass 10, count 0 2006.189.07:47:38.95#ibcon#about to read 3, iclass 10, count 0 2006.189.07:47:38.97#ibcon#read 3, iclass 10, count 0 2006.189.07:47:38.97#ibcon#about to read 4, iclass 10, count 0 2006.189.07:47:38.97#ibcon#read 4, iclass 10, count 0 2006.189.07:47:38.97#ibcon#about to read 5, iclass 10, count 0 2006.189.07:47:38.97#ibcon#read 5, iclass 10, count 0 2006.189.07:47:38.97#ibcon#about to read 6, iclass 10, count 0 2006.189.07:47:38.97#ibcon#read 6, iclass 10, count 0 2006.189.07:47:38.97#ibcon#end of sib2, iclass 10, count 0 2006.189.07:47:38.97#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:47:38.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:47:38.97#ibcon#[25=USB\r\n] 2006.189.07:47:38.97#ibcon#*before write, iclass 10, count 0 2006.189.07:47:38.97#ibcon#enter sib2, iclass 10, count 0 2006.189.07:47:38.97#ibcon#flushed, iclass 10, count 0 2006.189.07:47:38.97#ibcon#about to write, iclass 10, count 0 2006.189.07:47:38.97#ibcon#wrote, iclass 10, count 0 2006.189.07:47:38.97#ibcon#about to read 3, iclass 10, count 0 2006.189.07:47:39.00#ibcon#read 3, iclass 10, count 0 2006.189.07:47:39.00#ibcon#about to read 4, iclass 10, count 0 2006.189.07:47:39.00#ibcon#read 4, iclass 10, count 0 2006.189.07:47:39.00#ibcon#about to read 5, iclass 10, count 0 2006.189.07:47:39.00#ibcon#read 5, iclass 10, count 0 2006.189.07:47:39.00#ibcon#about to read 6, iclass 10, count 0 2006.189.07:47:39.00#ibcon#read 6, iclass 10, count 0 2006.189.07:47:39.00#ibcon#end of sib2, iclass 10, count 0 2006.189.07:47:39.00#ibcon#*after write, iclass 10, count 0 2006.189.07:47:39.00#ibcon#*before return 0, iclass 10, count 0 2006.189.07:47:39.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:39.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:39.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:47:39.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:47:39.00$vc4f8/valo=4,832.99 2006.189.07:47:39.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.07:47:39.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.07:47:39.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:39.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:39.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:39.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:39.00#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:47:39.00#ibcon#first serial, iclass 12, count 0 2006.189.07:47:39.00#ibcon#enter sib2, iclass 12, count 0 2006.189.07:47:39.00#ibcon#flushed, iclass 12, count 0 2006.189.07:47:39.00#ibcon#about to write, iclass 12, count 0 2006.189.07:47:39.00#ibcon#wrote, iclass 12, count 0 2006.189.07:47:39.00#ibcon#about to read 3, iclass 12, count 0 2006.189.07:47:39.02#ibcon#read 3, iclass 12, count 0 2006.189.07:47:39.02#ibcon#about to read 4, iclass 12, count 0 2006.189.07:47:39.02#ibcon#read 4, iclass 12, count 0 2006.189.07:47:39.02#ibcon#about to read 5, iclass 12, count 0 2006.189.07:47:39.02#ibcon#read 5, iclass 12, count 0 2006.189.07:47:39.02#ibcon#about to read 6, iclass 12, count 0 2006.189.07:47:39.02#ibcon#read 6, iclass 12, count 0 2006.189.07:47:39.02#ibcon#end of sib2, iclass 12, count 0 2006.189.07:47:39.02#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:47:39.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:47:39.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:47:39.02#ibcon#*before write, iclass 12, count 0 2006.189.07:47:39.02#ibcon#enter sib2, iclass 12, count 0 2006.189.07:47:39.02#ibcon#flushed, iclass 12, count 0 2006.189.07:47:39.02#ibcon#about to write, iclass 12, count 0 2006.189.07:47:39.02#ibcon#wrote, iclass 12, count 0 2006.189.07:47:39.02#ibcon#about to read 3, iclass 12, count 0 2006.189.07:47:39.06#ibcon#read 3, iclass 12, count 0 2006.189.07:47:39.06#ibcon#about to read 4, iclass 12, count 0 2006.189.07:47:39.06#ibcon#read 4, iclass 12, count 0 2006.189.07:47:39.06#ibcon#about to read 5, iclass 12, count 0 2006.189.07:47:39.06#ibcon#read 5, iclass 12, count 0 2006.189.07:47:39.06#ibcon#about to read 6, iclass 12, count 0 2006.189.07:47:39.06#ibcon#read 6, iclass 12, count 0 2006.189.07:47:39.06#ibcon#end of sib2, iclass 12, count 0 2006.189.07:47:39.06#ibcon#*after write, iclass 12, count 0 2006.189.07:47:39.06#ibcon#*before return 0, iclass 12, count 0 2006.189.07:47:39.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:39.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:39.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:47:39.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:47:39.06$vc4f8/va=4,7 2006.189.07:47:39.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.07:47:39.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.07:47:39.06#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:39.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:39.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:39.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:39.12#ibcon#enter wrdev, iclass 14, count 2 2006.189.07:47:39.12#ibcon#first serial, iclass 14, count 2 2006.189.07:47:39.12#ibcon#enter sib2, iclass 14, count 2 2006.189.07:47:39.12#ibcon#flushed, iclass 14, count 2 2006.189.07:47:39.12#ibcon#about to write, iclass 14, count 2 2006.189.07:47:39.12#ibcon#wrote, iclass 14, count 2 2006.189.07:47:39.12#ibcon#about to read 3, iclass 14, count 2 2006.189.07:47:39.14#ibcon#read 3, iclass 14, count 2 2006.189.07:47:39.14#ibcon#about to read 4, iclass 14, count 2 2006.189.07:47:39.14#ibcon#read 4, iclass 14, count 2 2006.189.07:47:39.14#ibcon#about to read 5, iclass 14, count 2 2006.189.07:47:39.14#ibcon#read 5, iclass 14, count 2 2006.189.07:47:39.14#ibcon#about to read 6, iclass 14, count 2 2006.189.07:47:39.14#ibcon#read 6, iclass 14, count 2 2006.189.07:47:39.14#ibcon#end of sib2, iclass 14, count 2 2006.189.07:47:39.14#ibcon#*mode == 0, iclass 14, count 2 2006.189.07:47:39.14#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.07:47:39.14#ibcon#[25=AT04-07\r\n] 2006.189.07:47:39.14#ibcon#*before write, iclass 14, count 2 2006.189.07:47:39.14#ibcon#enter sib2, iclass 14, count 2 2006.189.07:47:39.14#ibcon#flushed, iclass 14, count 2 2006.189.07:47:39.14#ibcon#about to write, iclass 14, count 2 2006.189.07:47:39.14#ibcon#wrote, iclass 14, count 2 2006.189.07:47:39.14#ibcon#about to read 3, iclass 14, count 2 2006.189.07:47:39.17#ibcon#read 3, iclass 14, count 2 2006.189.07:47:39.17#ibcon#about to read 4, iclass 14, count 2 2006.189.07:47:39.17#ibcon#read 4, iclass 14, count 2 2006.189.07:47:39.17#ibcon#about to read 5, iclass 14, count 2 2006.189.07:47:39.17#ibcon#read 5, iclass 14, count 2 2006.189.07:47:39.17#ibcon#about to read 6, iclass 14, count 2 2006.189.07:47:39.17#ibcon#read 6, iclass 14, count 2 2006.189.07:47:39.17#ibcon#end of sib2, iclass 14, count 2 2006.189.07:47:39.17#ibcon#*after write, iclass 14, count 2 2006.189.07:47:39.17#ibcon#*before return 0, iclass 14, count 2 2006.189.07:47:39.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:39.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:39.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.07:47:39.17#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:39.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:39.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:39.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:39.29#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:47:39.29#ibcon#first serial, iclass 14, count 0 2006.189.07:47:39.29#ibcon#enter sib2, iclass 14, count 0 2006.189.07:47:39.29#ibcon#flushed, iclass 14, count 0 2006.189.07:47:39.29#ibcon#about to write, iclass 14, count 0 2006.189.07:47:39.29#ibcon#wrote, iclass 14, count 0 2006.189.07:47:39.29#ibcon#about to read 3, iclass 14, count 0 2006.189.07:47:39.31#ibcon#read 3, iclass 14, count 0 2006.189.07:47:39.31#ibcon#about to read 4, iclass 14, count 0 2006.189.07:47:39.31#ibcon#read 4, iclass 14, count 0 2006.189.07:47:39.31#ibcon#about to read 5, iclass 14, count 0 2006.189.07:47:39.31#ibcon#read 5, iclass 14, count 0 2006.189.07:47:39.31#ibcon#about to read 6, iclass 14, count 0 2006.189.07:47:39.31#ibcon#read 6, iclass 14, count 0 2006.189.07:47:39.31#ibcon#end of sib2, iclass 14, count 0 2006.189.07:47:39.31#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:47:39.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:47:39.31#ibcon#[25=USB\r\n] 2006.189.07:47:39.31#ibcon#*before write, iclass 14, count 0 2006.189.07:47:39.31#ibcon#enter sib2, iclass 14, count 0 2006.189.07:47:39.31#ibcon#flushed, iclass 14, count 0 2006.189.07:47:39.31#ibcon#about to write, iclass 14, count 0 2006.189.07:47:39.31#ibcon#wrote, iclass 14, count 0 2006.189.07:47:39.31#ibcon#about to read 3, iclass 14, count 0 2006.189.07:47:39.34#ibcon#read 3, iclass 14, count 0 2006.189.07:47:39.34#ibcon#about to read 4, iclass 14, count 0 2006.189.07:47:39.34#ibcon#read 4, iclass 14, count 0 2006.189.07:47:39.34#ibcon#about to read 5, iclass 14, count 0 2006.189.07:47:39.34#ibcon#read 5, iclass 14, count 0 2006.189.07:47:39.34#ibcon#about to read 6, iclass 14, count 0 2006.189.07:47:39.34#ibcon#read 6, iclass 14, count 0 2006.189.07:47:39.34#ibcon#end of sib2, iclass 14, count 0 2006.189.07:47:39.34#ibcon#*after write, iclass 14, count 0 2006.189.07:47:39.34#ibcon#*before return 0, iclass 14, count 0 2006.189.07:47:39.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:39.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:39.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:47:39.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:47:39.34$vc4f8/valo=5,652.99 2006.189.07:47:39.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.07:47:39.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.07:47:39.34#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:39.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:39.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:39.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:39.34#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:47:39.34#ibcon#first serial, iclass 16, count 0 2006.189.07:47:39.34#ibcon#enter sib2, iclass 16, count 0 2006.189.07:47:39.34#ibcon#flushed, iclass 16, count 0 2006.189.07:47:39.34#ibcon#about to write, iclass 16, count 0 2006.189.07:47:39.34#ibcon#wrote, iclass 16, count 0 2006.189.07:47:39.34#ibcon#about to read 3, iclass 16, count 0 2006.189.07:47:39.36#ibcon#read 3, iclass 16, count 0 2006.189.07:47:39.36#ibcon#about to read 4, iclass 16, count 0 2006.189.07:47:39.36#ibcon#read 4, iclass 16, count 0 2006.189.07:47:39.36#ibcon#about to read 5, iclass 16, count 0 2006.189.07:47:39.36#ibcon#read 5, iclass 16, count 0 2006.189.07:47:39.36#ibcon#about to read 6, iclass 16, count 0 2006.189.07:47:39.36#ibcon#read 6, iclass 16, count 0 2006.189.07:47:39.36#ibcon#end of sib2, iclass 16, count 0 2006.189.07:47:39.36#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:47:39.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:47:39.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:47:39.36#ibcon#*before write, iclass 16, count 0 2006.189.07:47:39.36#ibcon#enter sib2, iclass 16, count 0 2006.189.07:47:39.36#ibcon#flushed, iclass 16, count 0 2006.189.07:47:39.36#ibcon#about to write, iclass 16, count 0 2006.189.07:47:39.36#ibcon#wrote, iclass 16, count 0 2006.189.07:47:39.36#ibcon#about to read 3, iclass 16, count 0 2006.189.07:47:39.40#ibcon#read 3, iclass 16, count 0 2006.189.07:47:39.40#ibcon#about to read 4, iclass 16, count 0 2006.189.07:47:39.40#ibcon#read 4, iclass 16, count 0 2006.189.07:47:39.40#ibcon#about to read 5, iclass 16, count 0 2006.189.07:47:39.40#ibcon#read 5, iclass 16, count 0 2006.189.07:47:39.40#ibcon#about to read 6, iclass 16, count 0 2006.189.07:47:39.40#ibcon#read 6, iclass 16, count 0 2006.189.07:47:39.40#ibcon#end of sib2, iclass 16, count 0 2006.189.07:47:39.40#ibcon#*after write, iclass 16, count 0 2006.189.07:47:39.40#ibcon#*before return 0, iclass 16, count 0 2006.189.07:47:39.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:39.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:39.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:47:39.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:47:39.40$vc4f8/va=5,7 2006.189.07:47:39.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.07:47:39.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.07:47:39.40#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:39.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:39.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:39.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:39.46#ibcon#enter wrdev, iclass 18, count 2 2006.189.07:47:39.46#ibcon#first serial, iclass 18, count 2 2006.189.07:47:39.46#ibcon#enter sib2, iclass 18, count 2 2006.189.07:47:39.46#ibcon#flushed, iclass 18, count 2 2006.189.07:47:39.46#ibcon#about to write, iclass 18, count 2 2006.189.07:47:39.46#ibcon#wrote, iclass 18, count 2 2006.189.07:47:39.46#ibcon#about to read 3, iclass 18, count 2 2006.189.07:47:39.48#ibcon#read 3, iclass 18, count 2 2006.189.07:47:39.48#ibcon#about to read 4, iclass 18, count 2 2006.189.07:47:39.48#ibcon#read 4, iclass 18, count 2 2006.189.07:47:39.48#ibcon#about to read 5, iclass 18, count 2 2006.189.07:47:39.48#ibcon#read 5, iclass 18, count 2 2006.189.07:47:39.48#ibcon#about to read 6, iclass 18, count 2 2006.189.07:47:39.48#ibcon#read 6, iclass 18, count 2 2006.189.07:47:39.48#ibcon#end of sib2, iclass 18, count 2 2006.189.07:47:39.48#ibcon#*mode == 0, iclass 18, count 2 2006.189.07:47:39.48#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.07:47:39.48#ibcon#[25=AT05-07\r\n] 2006.189.07:47:39.48#ibcon#*before write, iclass 18, count 2 2006.189.07:47:39.48#ibcon#enter sib2, iclass 18, count 2 2006.189.07:47:39.48#ibcon#flushed, iclass 18, count 2 2006.189.07:47:39.48#ibcon#about to write, iclass 18, count 2 2006.189.07:47:39.48#ibcon#wrote, iclass 18, count 2 2006.189.07:47:39.48#ibcon#about to read 3, iclass 18, count 2 2006.189.07:47:39.51#ibcon#read 3, iclass 18, count 2 2006.189.07:47:39.51#ibcon#about to read 4, iclass 18, count 2 2006.189.07:47:39.51#ibcon#read 4, iclass 18, count 2 2006.189.07:47:39.51#ibcon#about to read 5, iclass 18, count 2 2006.189.07:47:39.51#ibcon#read 5, iclass 18, count 2 2006.189.07:47:39.51#ibcon#about to read 6, iclass 18, count 2 2006.189.07:47:39.51#ibcon#read 6, iclass 18, count 2 2006.189.07:47:39.51#ibcon#end of sib2, iclass 18, count 2 2006.189.07:47:39.51#ibcon#*after write, iclass 18, count 2 2006.189.07:47:39.51#ibcon#*before return 0, iclass 18, count 2 2006.189.07:47:39.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:39.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:39.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.07:47:39.51#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:39.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:39.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:39.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:39.63#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:47:39.63#ibcon#first serial, iclass 18, count 0 2006.189.07:47:39.63#ibcon#enter sib2, iclass 18, count 0 2006.189.07:47:39.63#ibcon#flushed, iclass 18, count 0 2006.189.07:47:39.63#ibcon#about to write, iclass 18, count 0 2006.189.07:47:39.63#ibcon#wrote, iclass 18, count 0 2006.189.07:47:39.63#ibcon#about to read 3, iclass 18, count 0 2006.189.07:47:39.65#ibcon#read 3, iclass 18, count 0 2006.189.07:47:39.65#ibcon#about to read 4, iclass 18, count 0 2006.189.07:47:39.65#ibcon#read 4, iclass 18, count 0 2006.189.07:47:39.65#ibcon#about to read 5, iclass 18, count 0 2006.189.07:47:39.65#ibcon#read 5, iclass 18, count 0 2006.189.07:47:39.65#ibcon#about to read 6, iclass 18, count 0 2006.189.07:47:39.65#ibcon#read 6, iclass 18, count 0 2006.189.07:47:39.65#ibcon#end of sib2, iclass 18, count 0 2006.189.07:47:39.65#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:47:39.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:47:39.65#ibcon#[25=USB\r\n] 2006.189.07:47:39.65#ibcon#*before write, iclass 18, count 0 2006.189.07:47:39.65#ibcon#enter sib2, iclass 18, count 0 2006.189.07:47:39.65#ibcon#flushed, iclass 18, count 0 2006.189.07:47:39.65#ibcon#about to write, iclass 18, count 0 2006.189.07:47:39.65#ibcon#wrote, iclass 18, count 0 2006.189.07:47:39.65#ibcon#about to read 3, iclass 18, count 0 2006.189.07:47:39.68#ibcon#read 3, iclass 18, count 0 2006.189.07:47:39.68#ibcon#about to read 4, iclass 18, count 0 2006.189.07:47:39.68#ibcon#read 4, iclass 18, count 0 2006.189.07:47:39.68#ibcon#about to read 5, iclass 18, count 0 2006.189.07:47:39.68#ibcon#read 5, iclass 18, count 0 2006.189.07:47:39.68#ibcon#about to read 6, iclass 18, count 0 2006.189.07:47:39.68#ibcon#read 6, iclass 18, count 0 2006.189.07:47:39.68#ibcon#end of sib2, iclass 18, count 0 2006.189.07:47:39.68#ibcon#*after write, iclass 18, count 0 2006.189.07:47:39.68#ibcon#*before return 0, iclass 18, count 0 2006.189.07:47:39.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:39.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:39.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:47:39.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:47:39.68$vc4f8/valo=6,772.99 2006.189.07:47:39.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.07:47:39.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.07:47:39.68#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:39.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:39.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:39.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:39.68#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:47:39.68#ibcon#first serial, iclass 20, count 0 2006.189.07:47:39.68#ibcon#enter sib2, iclass 20, count 0 2006.189.07:47:39.68#ibcon#flushed, iclass 20, count 0 2006.189.07:47:39.68#ibcon#about to write, iclass 20, count 0 2006.189.07:47:39.68#ibcon#wrote, iclass 20, count 0 2006.189.07:47:39.68#ibcon#about to read 3, iclass 20, count 0 2006.189.07:47:39.70#ibcon#read 3, iclass 20, count 0 2006.189.07:47:39.70#ibcon#about to read 4, iclass 20, count 0 2006.189.07:47:39.70#ibcon#read 4, iclass 20, count 0 2006.189.07:47:39.70#ibcon#about to read 5, iclass 20, count 0 2006.189.07:47:39.70#ibcon#read 5, iclass 20, count 0 2006.189.07:47:39.70#ibcon#about to read 6, iclass 20, count 0 2006.189.07:47:39.70#ibcon#read 6, iclass 20, count 0 2006.189.07:47:39.70#ibcon#end of sib2, iclass 20, count 0 2006.189.07:47:39.70#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:47:39.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:47:39.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:47:39.70#ibcon#*before write, iclass 20, count 0 2006.189.07:47:39.70#ibcon#enter sib2, iclass 20, count 0 2006.189.07:47:39.70#ibcon#flushed, iclass 20, count 0 2006.189.07:47:39.70#ibcon#about to write, iclass 20, count 0 2006.189.07:47:39.70#ibcon#wrote, iclass 20, count 0 2006.189.07:47:39.70#ibcon#about to read 3, iclass 20, count 0 2006.189.07:47:39.74#ibcon#read 3, iclass 20, count 0 2006.189.07:47:39.74#ibcon#about to read 4, iclass 20, count 0 2006.189.07:47:39.74#ibcon#read 4, iclass 20, count 0 2006.189.07:47:39.74#ibcon#about to read 5, iclass 20, count 0 2006.189.07:47:39.74#ibcon#read 5, iclass 20, count 0 2006.189.07:47:39.74#ibcon#about to read 6, iclass 20, count 0 2006.189.07:47:39.74#ibcon#read 6, iclass 20, count 0 2006.189.07:47:39.74#ibcon#end of sib2, iclass 20, count 0 2006.189.07:47:39.74#ibcon#*after write, iclass 20, count 0 2006.189.07:47:39.74#ibcon#*before return 0, iclass 20, count 0 2006.189.07:47:39.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:39.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:39.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:47:39.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:47:39.74$vc4f8/va=6,6 2006.189.07:47:39.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.07:47:39.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.07:47:39.74#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:39.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:47:39.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:47:39.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:47:39.80#ibcon#enter wrdev, iclass 22, count 2 2006.189.07:47:39.80#ibcon#first serial, iclass 22, count 2 2006.189.07:47:39.80#ibcon#enter sib2, iclass 22, count 2 2006.189.07:47:39.80#ibcon#flushed, iclass 22, count 2 2006.189.07:47:39.80#ibcon#about to write, iclass 22, count 2 2006.189.07:47:39.80#ibcon#wrote, iclass 22, count 2 2006.189.07:47:39.80#ibcon#about to read 3, iclass 22, count 2 2006.189.07:47:39.82#ibcon#read 3, iclass 22, count 2 2006.189.07:47:39.82#ibcon#about to read 4, iclass 22, count 2 2006.189.07:47:39.82#ibcon#read 4, iclass 22, count 2 2006.189.07:47:39.82#ibcon#about to read 5, iclass 22, count 2 2006.189.07:47:39.82#ibcon#read 5, iclass 22, count 2 2006.189.07:47:39.82#ibcon#about to read 6, iclass 22, count 2 2006.189.07:47:39.82#ibcon#read 6, iclass 22, count 2 2006.189.07:47:39.82#ibcon#end of sib2, iclass 22, count 2 2006.189.07:47:39.82#ibcon#*mode == 0, iclass 22, count 2 2006.189.07:47:39.82#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.07:47:39.82#ibcon#[25=AT06-06\r\n] 2006.189.07:47:39.82#ibcon#*before write, iclass 22, count 2 2006.189.07:47:39.82#ibcon#enter sib2, iclass 22, count 2 2006.189.07:47:39.82#ibcon#flushed, iclass 22, count 2 2006.189.07:47:39.82#ibcon#about to write, iclass 22, count 2 2006.189.07:47:39.82#ibcon#wrote, iclass 22, count 2 2006.189.07:47:39.82#ibcon#about to read 3, iclass 22, count 2 2006.189.07:47:39.85#ibcon#read 3, iclass 22, count 2 2006.189.07:47:39.85#ibcon#about to read 4, iclass 22, count 2 2006.189.07:47:39.85#ibcon#read 4, iclass 22, count 2 2006.189.07:47:39.85#ibcon#about to read 5, iclass 22, count 2 2006.189.07:47:39.85#ibcon#read 5, iclass 22, count 2 2006.189.07:47:39.85#ibcon#about to read 6, iclass 22, count 2 2006.189.07:47:39.85#ibcon#read 6, iclass 22, count 2 2006.189.07:47:39.85#ibcon#end of sib2, iclass 22, count 2 2006.189.07:47:39.85#ibcon#*after write, iclass 22, count 2 2006.189.07:47:39.85#ibcon#*before return 0, iclass 22, count 2 2006.189.07:47:39.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:47:39.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.07:47:39.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.07:47:39.85#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:39.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:47:39.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:47:39.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:47:39.97#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:47:39.97#ibcon#first serial, iclass 22, count 0 2006.189.07:47:39.97#ibcon#enter sib2, iclass 22, count 0 2006.189.07:47:39.97#ibcon#flushed, iclass 22, count 0 2006.189.07:47:39.97#ibcon#about to write, iclass 22, count 0 2006.189.07:47:39.97#ibcon#wrote, iclass 22, count 0 2006.189.07:47:39.97#ibcon#about to read 3, iclass 22, count 0 2006.189.07:47:39.99#ibcon#read 3, iclass 22, count 0 2006.189.07:47:39.99#ibcon#about to read 4, iclass 22, count 0 2006.189.07:47:39.99#ibcon#read 4, iclass 22, count 0 2006.189.07:47:39.99#ibcon#about to read 5, iclass 22, count 0 2006.189.07:47:39.99#ibcon#read 5, iclass 22, count 0 2006.189.07:47:39.99#ibcon#about to read 6, iclass 22, count 0 2006.189.07:47:39.99#ibcon#read 6, iclass 22, count 0 2006.189.07:47:39.99#ibcon#end of sib2, iclass 22, count 0 2006.189.07:47:39.99#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:47:39.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:47:39.99#ibcon#[25=USB\r\n] 2006.189.07:47:39.99#ibcon#*before write, iclass 22, count 0 2006.189.07:47:39.99#ibcon#enter sib2, iclass 22, count 0 2006.189.07:47:39.99#ibcon#flushed, iclass 22, count 0 2006.189.07:47:39.99#ibcon#about to write, iclass 22, count 0 2006.189.07:47:39.99#ibcon#wrote, iclass 22, count 0 2006.189.07:47:39.99#ibcon#about to read 3, iclass 22, count 0 2006.189.07:47:40.02#ibcon#read 3, iclass 22, count 0 2006.189.07:47:40.02#ibcon#about to read 4, iclass 22, count 0 2006.189.07:47:40.02#ibcon#read 4, iclass 22, count 0 2006.189.07:47:40.02#ibcon#about to read 5, iclass 22, count 0 2006.189.07:47:40.02#ibcon#read 5, iclass 22, count 0 2006.189.07:47:40.02#ibcon#about to read 6, iclass 22, count 0 2006.189.07:47:40.02#ibcon#read 6, iclass 22, count 0 2006.189.07:47:40.02#ibcon#end of sib2, iclass 22, count 0 2006.189.07:47:40.02#ibcon#*after write, iclass 22, count 0 2006.189.07:47:40.02#ibcon#*before return 0, iclass 22, count 0 2006.189.07:47:40.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:47:40.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.07:47:40.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:47:40.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:47:40.02$vc4f8/valo=7,832.99 2006.189.07:47:40.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.07:47:40.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.07:47:40.02#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:40.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:47:40.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:47:40.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:47:40.02#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:47:40.02#ibcon#first serial, iclass 24, count 0 2006.189.07:47:40.02#ibcon#enter sib2, iclass 24, count 0 2006.189.07:47:40.02#ibcon#flushed, iclass 24, count 0 2006.189.07:47:40.02#ibcon#about to write, iclass 24, count 0 2006.189.07:47:40.02#ibcon#wrote, iclass 24, count 0 2006.189.07:47:40.02#ibcon#about to read 3, iclass 24, count 0 2006.189.07:47:40.04#ibcon#read 3, iclass 24, count 0 2006.189.07:47:40.04#ibcon#about to read 4, iclass 24, count 0 2006.189.07:47:40.04#ibcon#read 4, iclass 24, count 0 2006.189.07:47:40.04#ibcon#about to read 5, iclass 24, count 0 2006.189.07:47:40.04#ibcon#read 5, iclass 24, count 0 2006.189.07:47:40.04#ibcon#about to read 6, iclass 24, count 0 2006.189.07:47:40.04#ibcon#read 6, iclass 24, count 0 2006.189.07:47:40.04#ibcon#end of sib2, iclass 24, count 0 2006.189.07:47:40.04#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:47:40.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:47:40.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:47:40.04#ibcon#*before write, iclass 24, count 0 2006.189.07:47:40.04#ibcon#enter sib2, iclass 24, count 0 2006.189.07:47:40.04#ibcon#flushed, iclass 24, count 0 2006.189.07:47:40.04#ibcon#about to write, iclass 24, count 0 2006.189.07:47:40.04#ibcon#wrote, iclass 24, count 0 2006.189.07:47:40.04#ibcon#about to read 3, iclass 24, count 0 2006.189.07:47:40.08#ibcon#read 3, iclass 24, count 0 2006.189.07:47:40.08#ibcon#about to read 4, iclass 24, count 0 2006.189.07:47:40.08#ibcon#read 4, iclass 24, count 0 2006.189.07:47:40.08#ibcon#about to read 5, iclass 24, count 0 2006.189.07:47:40.08#ibcon#read 5, iclass 24, count 0 2006.189.07:47:40.08#ibcon#about to read 6, iclass 24, count 0 2006.189.07:47:40.08#ibcon#read 6, iclass 24, count 0 2006.189.07:47:40.08#ibcon#end of sib2, iclass 24, count 0 2006.189.07:47:40.08#ibcon#*after write, iclass 24, count 0 2006.189.07:47:40.08#ibcon#*before return 0, iclass 24, count 0 2006.189.07:47:40.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:47:40.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.07:47:40.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:47:40.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:47:40.08$vc4f8/va=7,6 2006.189.07:47:40.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.07:47:40.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.07:47:40.08#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:40.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:47:40.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:47:40.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:47:40.14#ibcon#enter wrdev, iclass 26, count 2 2006.189.07:47:40.14#ibcon#first serial, iclass 26, count 2 2006.189.07:47:40.14#ibcon#enter sib2, iclass 26, count 2 2006.189.07:47:40.14#ibcon#flushed, iclass 26, count 2 2006.189.07:47:40.14#ibcon#about to write, iclass 26, count 2 2006.189.07:47:40.14#ibcon#wrote, iclass 26, count 2 2006.189.07:47:40.14#ibcon#about to read 3, iclass 26, count 2 2006.189.07:47:40.16#ibcon#read 3, iclass 26, count 2 2006.189.07:47:40.16#ibcon#about to read 4, iclass 26, count 2 2006.189.07:47:40.16#ibcon#read 4, iclass 26, count 2 2006.189.07:47:40.16#ibcon#about to read 5, iclass 26, count 2 2006.189.07:47:40.16#ibcon#read 5, iclass 26, count 2 2006.189.07:47:40.16#ibcon#about to read 6, iclass 26, count 2 2006.189.07:47:40.16#ibcon#read 6, iclass 26, count 2 2006.189.07:47:40.16#ibcon#end of sib2, iclass 26, count 2 2006.189.07:47:40.16#ibcon#*mode == 0, iclass 26, count 2 2006.189.07:47:40.16#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.07:47:40.16#ibcon#[25=AT07-06\r\n] 2006.189.07:47:40.16#ibcon#*before write, iclass 26, count 2 2006.189.07:47:40.16#ibcon#enter sib2, iclass 26, count 2 2006.189.07:47:40.16#ibcon#flushed, iclass 26, count 2 2006.189.07:47:40.16#ibcon#about to write, iclass 26, count 2 2006.189.07:47:40.16#ibcon#wrote, iclass 26, count 2 2006.189.07:47:40.16#ibcon#about to read 3, iclass 26, count 2 2006.189.07:47:40.19#ibcon#read 3, iclass 26, count 2 2006.189.07:47:40.19#ibcon#about to read 4, iclass 26, count 2 2006.189.07:47:40.19#ibcon#read 4, iclass 26, count 2 2006.189.07:47:40.19#ibcon#about to read 5, iclass 26, count 2 2006.189.07:47:40.19#ibcon#read 5, iclass 26, count 2 2006.189.07:47:40.19#ibcon#about to read 6, iclass 26, count 2 2006.189.07:47:40.19#ibcon#read 6, iclass 26, count 2 2006.189.07:47:40.19#ibcon#end of sib2, iclass 26, count 2 2006.189.07:47:40.19#ibcon#*after write, iclass 26, count 2 2006.189.07:47:40.19#ibcon#*before return 0, iclass 26, count 2 2006.189.07:47:40.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:47:40.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.07:47:40.19#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.07:47:40.19#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:40.19#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:47:40.31#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:47:40.31#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:47:40.31#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:47:40.31#ibcon#first serial, iclass 26, count 0 2006.189.07:47:40.31#ibcon#enter sib2, iclass 26, count 0 2006.189.07:47:40.31#ibcon#flushed, iclass 26, count 0 2006.189.07:47:40.31#ibcon#about to write, iclass 26, count 0 2006.189.07:47:40.31#ibcon#wrote, iclass 26, count 0 2006.189.07:47:40.31#ibcon#about to read 3, iclass 26, count 0 2006.189.07:47:40.33#ibcon#read 3, iclass 26, count 0 2006.189.07:47:40.33#ibcon#about to read 4, iclass 26, count 0 2006.189.07:47:40.33#ibcon#read 4, iclass 26, count 0 2006.189.07:47:40.33#ibcon#about to read 5, iclass 26, count 0 2006.189.07:47:40.33#ibcon#read 5, iclass 26, count 0 2006.189.07:47:40.33#ibcon#about to read 6, iclass 26, count 0 2006.189.07:47:40.33#ibcon#read 6, iclass 26, count 0 2006.189.07:47:40.33#ibcon#end of sib2, iclass 26, count 0 2006.189.07:47:40.33#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:47:40.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:47:40.33#ibcon#[25=USB\r\n] 2006.189.07:47:40.33#ibcon#*before write, iclass 26, count 0 2006.189.07:47:40.33#ibcon#enter sib2, iclass 26, count 0 2006.189.07:47:40.33#ibcon#flushed, iclass 26, count 0 2006.189.07:47:40.33#ibcon#about to write, iclass 26, count 0 2006.189.07:47:40.33#ibcon#wrote, iclass 26, count 0 2006.189.07:47:40.33#ibcon#about to read 3, iclass 26, count 0 2006.189.07:47:40.36#ibcon#read 3, iclass 26, count 0 2006.189.07:47:40.36#ibcon#about to read 4, iclass 26, count 0 2006.189.07:47:40.36#ibcon#read 4, iclass 26, count 0 2006.189.07:47:40.36#ibcon#about to read 5, iclass 26, count 0 2006.189.07:47:40.36#ibcon#read 5, iclass 26, count 0 2006.189.07:47:40.36#ibcon#about to read 6, iclass 26, count 0 2006.189.07:47:40.36#ibcon#read 6, iclass 26, count 0 2006.189.07:47:40.36#ibcon#end of sib2, iclass 26, count 0 2006.189.07:47:40.36#ibcon#*after write, iclass 26, count 0 2006.189.07:47:40.36#ibcon#*before return 0, iclass 26, count 0 2006.189.07:47:40.36#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:47:40.36#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.07:47:40.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:47:40.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:47:40.36$vc4f8/valo=8,852.99 2006.189.07:47:40.36#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.07:47:40.36#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.07:47:40.36#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:40.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:47:40.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:47:40.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:47:40.36#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:47:40.36#ibcon#first serial, iclass 28, count 0 2006.189.07:47:40.36#ibcon#enter sib2, iclass 28, count 0 2006.189.07:47:40.36#ibcon#flushed, iclass 28, count 0 2006.189.07:47:40.36#ibcon#about to write, iclass 28, count 0 2006.189.07:47:40.36#ibcon#wrote, iclass 28, count 0 2006.189.07:47:40.36#ibcon#about to read 3, iclass 28, count 0 2006.189.07:47:40.38#ibcon#read 3, iclass 28, count 0 2006.189.07:47:40.38#ibcon#about to read 4, iclass 28, count 0 2006.189.07:47:40.38#ibcon#read 4, iclass 28, count 0 2006.189.07:47:40.38#ibcon#about to read 5, iclass 28, count 0 2006.189.07:47:40.38#ibcon#read 5, iclass 28, count 0 2006.189.07:47:40.38#ibcon#about to read 6, iclass 28, count 0 2006.189.07:47:40.38#ibcon#read 6, iclass 28, count 0 2006.189.07:47:40.38#ibcon#end of sib2, iclass 28, count 0 2006.189.07:47:40.38#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:47:40.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:47:40.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:47:40.38#ibcon#*before write, iclass 28, count 0 2006.189.07:47:40.38#ibcon#enter sib2, iclass 28, count 0 2006.189.07:47:40.38#ibcon#flushed, iclass 28, count 0 2006.189.07:47:40.38#ibcon#about to write, iclass 28, count 0 2006.189.07:47:40.38#ibcon#wrote, iclass 28, count 0 2006.189.07:47:40.38#ibcon#about to read 3, iclass 28, count 0 2006.189.07:47:40.42#ibcon#read 3, iclass 28, count 0 2006.189.07:47:40.42#ibcon#about to read 4, iclass 28, count 0 2006.189.07:47:40.42#ibcon#read 4, iclass 28, count 0 2006.189.07:47:40.42#ibcon#about to read 5, iclass 28, count 0 2006.189.07:47:40.42#ibcon#read 5, iclass 28, count 0 2006.189.07:47:40.42#ibcon#about to read 6, iclass 28, count 0 2006.189.07:47:40.42#ibcon#read 6, iclass 28, count 0 2006.189.07:47:40.42#ibcon#end of sib2, iclass 28, count 0 2006.189.07:47:40.42#ibcon#*after write, iclass 28, count 0 2006.189.07:47:40.42#ibcon#*before return 0, iclass 28, count 0 2006.189.07:47:40.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:47:40.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.07:47:40.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:47:40.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:47:40.42$vc4f8/va=8,6 2006.189.07:47:40.42#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.07:47:40.42#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.07:47:40.42#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:40.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:47:40.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:47:40.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:47:40.48#ibcon#enter wrdev, iclass 30, count 2 2006.189.07:47:40.48#ibcon#first serial, iclass 30, count 2 2006.189.07:47:40.48#ibcon#enter sib2, iclass 30, count 2 2006.189.07:47:40.48#ibcon#flushed, iclass 30, count 2 2006.189.07:47:40.48#ibcon#about to write, iclass 30, count 2 2006.189.07:47:40.48#ibcon#wrote, iclass 30, count 2 2006.189.07:47:40.48#ibcon#about to read 3, iclass 30, count 2 2006.189.07:47:40.50#ibcon#read 3, iclass 30, count 2 2006.189.07:47:40.50#ibcon#about to read 4, iclass 30, count 2 2006.189.07:47:40.50#ibcon#read 4, iclass 30, count 2 2006.189.07:47:40.50#ibcon#about to read 5, iclass 30, count 2 2006.189.07:47:40.50#ibcon#read 5, iclass 30, count 2 2006.189.07:47:40.50#ibcon#about to read 6, iclass 30, count 2 2006.189.07:47:40.50#ibcon#read 6, iclass 30, count 2 2006.189.07:47:40.50#ibcon#end of sib2, iclass 30, count 2 2006.189.07:47:40.50#ibcon#*mode == 0, iclass 30, count 2 2006.189.07:47:40.50#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.07:47:40.50#ibcon#[25=AT08-06\r\n] 2006.189.07:47:40.50#ibcon#*before write, iclass 30, count 2 2006.189.07:47:40.50#ibcon#enter sib2, iclass 30, count 2 2006.189.07:47:40.50#ibcon#flushed, iclass 30, count 2 2006.189.07:47:40.50#ibcon#about to write, iclass 30, count 2 2006.189.07:47:40.50#ibcon#wrote, iclass 30, count 2 2006.189.07:47:40.50#ibcon#about to read 3, iclass 30, count 2 2006.189.07:47:40.53#ibcon#read 3, iclass 30, count 2 2006.189.07:47:40.53#ibcon#about to read 4, iclass 30, count 2 2006.189.07:47:40.53#ibcon#read 4, iclass 30, count 2 2006.189.07:47:40.53#ibcon#about to read 5, iclass 30, count 2 2006.189.07:47:40.53#ibcon#read 5, iclass 30, count 2 2006.189.07:47:40.53#ibcon#about to read 6, iclass 30, count 2 2006.189.07:47:40.53#ibcon#read 6, iclass 30, count 2 2006.189.07:47:40.53#ibcon#end of sib2, iclass 30, count 2 2006.189.07:47:40.53#ibcon#*after write, iclass 30, count 2 2006.189.07:47:40.53#ibcon#*before return 0, iclass 30, count 2 2006.189.07:47:40.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:47:40.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.07:47:40.53#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.07:47:40.53#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:40.53#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:47:40.65#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:47:40.65#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:47:40.65#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:47:40.65#ibcon#first serial, iclass 30, count 0 2006.189.07:47:40.65#ibcon#enter sib2, iclass 30, count 0 2006.189.07:47:40.65#ibcon#flushed, iclass 30, count 0 2006.189.07:47:40.65#ibcon#about to write, iclass 30, count 0 2006.189.07:47:40.65#ibcon#wrote, iclass 30, count 0 2006.189.07:47:40.65#ibcon#about to read 3, iclass 30, count 0 2006.189.07:47:40.67#ibcon#read 3, iclass 30, count 0 2006.189.07:47:40.67#ibcon#about to read 4, iclass 30, count 0 2006.189.07:47:40.67#ibcon#read 4, iclass 30, count 0 2006.189.07:47:40.67#ibcon#about to read 5, iclass 30, count 0 2006.189.07:47:40.67#ibcon#read 5, iclass 30, count 0 2006.189.07:47:40.67#ibcon#about to read 6, iclass 30, count 0 2006.189.07:47:40.67#ibcon#read 6, iclass 30, count 0 2006.189.07:47:40.67#ibcon#end of sib2, iclass 30, count 0 2006.189.07:47:40.67#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:47:40.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:47:40.67#ibcon#[25=USB\r\n] 2006.189.07:47:40.67#ibcon#*before write, iclass 30, count 0 2006.189.07:47:40.67#ibcon#enter sib2, iclass 30, count 0 2006.189.07:47:40.67#ibcon#flushed, iclass 30, count 0 2006.189.07:47:40.67#ibcon#about to write, iclass 30, count 0 2006.189.07:47:40.67#ibcon#wrote, iclass 30, count 0 2006.189.07:47:40.67#ibcon#about to read 3, iclass 30, count 0 2006.189.07:47:40.70#ibcon#read 3, iclass 30, count 0 2006.189.07:47:40.70#ibcon#about to read 4, iclass 30, count 0 2006.189.07:47:40.70#ibcon#read 4, iclass 30, count 0 2006.189.07:47:40.70#ibcon#about to read 5, iclass 30, count 0 2006.189.07:47:40.70#ibcon#read 5, iclass 30, count 0 2006.189.07:47:40.70#ibcon#about to read 6, iclass 30, count 0 2006.189.07:47:40.70#ibcon#read 6, iclass 30, count 0 2006.189.07:47:40.70#ibcon#end of sib2, iclass 30, count 0 2006.189.07:47:40.70#ibcon#*after write, iclass 30, count 0 2006.189.07:47:40.70#ibcon#*before return 0, iclass 30, count 0 2006.189.07:47:40.70#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:47:40.70#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.07:47:40.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:47:40.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:47:40.70$vc4f8/vblo=1,632.99 2006.189.07:47:40.70#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.07:47:40.70#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.07:47:40.70#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:40.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:47:40.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:47:40.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:47:40.70#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:47:40.70#ibcon#first serial, iclass 32, count 0 2006.189.07:47:40.70#ibcon#enter sib2, iclass 32, count 0 2006.189.07:47:40.70#ibcon#flushed, iclass 32, count 0 2006.189.07:47:40.70#ibcon#about to write, iclass 32, count 0 2006.189.07:47:40.70#ibcon#wrote, iclass 32, count 0 2006.189.07:47:40.70#ibcon#about to read 3, iclass 32, count 0 2006.189.07:47:40.72#ibcon#read 3, iclass 32, count 0 2006.189.07:47:40.72#ibcon#about to read 4, iclass 32, count 0 2006.189.07:47:40.72#ibcon#read 4, iclass 32, count 0 2006.189.07:47:40.72#ibcon#about to read 5, iclass 32, count 0 2006.189.07:47:40.72#ibcon#read 5, iclass 32, count 0 2006.189.07:47:40.72#ibcon#about to read 6, iclass 32, count 0 2006.189.07:47:40.72#ibcon#read 6, iclass 32, count 0 2006.189.07:47:40.72#ibcon#end of sib2, iclass 32, count 0 2006.189.07:47:40.72#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:47:40.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:47:40.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:47:40.72#ibcon#*before write, iclass 32, count 0 2006.189.07:47:40.72#ibcon#enter sib2, iclass 32, count 0 2006.189.07:47:40.72#ibcon#flushed, iclass 32, count 0 2006.189.07:47:40.72#ibcon#about to write, iclass 32, count 0 2006.189.07:47:40.72#ibcon#wrote, iclass 32, count 0 2006.189.07:47:40.72#ibcon#about to read 3, iclass 32, count 0 2006.189.07:47:40.76#ibcon#read 3, iclass 32, count 0 2006.189.07:47:40.76#ibcon#about to read 4, iclass 32, count 0 2006.189.07:47:40.76#ibcon#read 4, iclass 32, count 0 2006.189.07:47:40.76#ibcon#about to read 5, iclass 32, count 0 2006.189.07:47:40.76#ibcon#read 5, iclass 32, count 0 2006.189.07:47:40.76#ibcon#about to read 6, iclass 32, count 0 2006.189.07:47:40.76#ibcon#read 6, iclass 32, count 0 2006.189.07:47:40.76#ibcon#end of sib2, iclass 32, count 0 2006.189.07:47:40.76#ibcon#*after write, iclass 32, count 0 2006.189.07:47:40.76#ibcon#*before return 0, iclass 32, count 0 2006.189.07:47:40.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:47:40.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:47:40.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:47:40.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:47:40.76$vc4f8/vb=1,4 2006.189.07:47:40.76#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.07:47:40.76#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.07:47:40.76#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:40.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:47:40.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:47:40.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:47:40.76#ibcon#enter wrdev, iclass 34, count 2 2006.189.07:47:40.76#ibcon#first serial, iclass 34, count 2 2006.189.07:47:40.76#ibcon#enter sib2, iclass 34, count 2 2006.189.07:47:40.76#ibcon#flushed, iclass 34, count 2 2006.189.07:47:40.76#ibcon#about to write, iclass 34, count 2 2006.189.07:47:40.76#ibcon#wrote, iclass 34, count 2 2006.189.07:47:40.76#ibcon#about to read 3, iclass 34, count 2 2006.189.07:47:40.78#ibcon#read 3, iclass 34, count 2 2006.189.07:47:40.78#ibcon#about to read 4, iclass 34, count 2 2006.189.07:47:40.78#ibcon#read 4, iclass 34, count 2 2006.189.07:47:40.78#ibcon#about to read 5, iclass 34, count 2 2006.189.07:47:40.78#ibcon#read 5, iclass 34, count 2 2006.189.07:47:40.78#ibcon#about to read 6, iclass 34, count 2 2006.189.07:47:40.78#ibcon#read 6, iclass 34, count 2 2006.189.07:47:40.78#ibcon#end of sib2, iclass 34, count 2 2006.189.07:47:40.78#ibcon#*mode == 0, iclass 34, count 2 2006.189.07:47:40.78#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.07:47:40.78#ibcon#[27=AT01-04\r\n] 2006.189.07:47:40.78#ibcon#*before write, iclass 34, count 2 2006.189.07:47:40.78#ibcon#enter sib2, iclass 34, count 2 2006.189.07:47:40.78#ibcon#flushed, iclass 34, count 2 2006.189.07:47:40.78#ibcon#about to write, iclass 34, count 2 2006.189.07:47:40.78#ibcon#wrote, iclass 34, count 2 2006.189.07:47:40.78#ibcon#about to read 3, iclass 34, count 2 2006.189.07:47:40.81#ibcon#read 3, iclass 34, count 2 2006.189.07:47:40.81#ibcon#about to read 4, iclass 34, count 2 2006.189.07:47:40.81#ibcon#read 4, iclass 34, count 2 2006.189.07:47:40.81#ibcon#about to read 5, iclass 34, count 2 2006.189.07:47:40.81#ibcon#read 5, iclass 34, count 2 2006.189.07:47:40.81#ibcon#about to read 6, iclass 34, count 2 2006.189.07:47:40.81#ibcon#read 6, iclass 34, count 2 2006.189.07:47:40.81#ibcon#end of sib2, iclass 34, count 2 2006.189.07:47:40.81#ibcon#*after write, iclass 34, count 2 2006.189.07:47:40.81#ibcon#*before return 0, iclass 34, count 2 2006.189.07:47:40.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:47:40.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.07:47:40.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.07:47:40.81#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:40.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:47:40.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:47:40.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:47:40.93#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:47:40.93#ibcon#first serial, iclass 34, count 0 2006.189.07:47:40.93#ibcon#enter sib2, iclass 34, count 0 2006.189.07:47:40.93#ibcon#flushed, iclass 34, count 0 2006.189.07:47:40.93#ibcon#about to write, iclass 34, count 0 2006.189.07:47:40.93#ibcon#wrote, iclass 34, count 0 2006.189.07:47:40.93#ibcon#about to read 3, iclass 34, count 0 2006.189.07:47:40.95#ibcon#read 3, iclass 34, count 0 2006.189.07:47:40.95#ibcon#about to read 4, iclass 34, count 0 2006.189.07:47:40.95#ibcon#read 4, iclass 34, count 0 2006.189.07:47:40.95#ibcon#about to read 5, iclass 34, count 0 2006.189.07:47:40.95#ibcon#read 5, iclass 34, count 0 2006.189.07:47:40.95#ibcon#about to read 6, iclass 34, count 0 2006.189.07:47:40.95#ibcon#read 6, iclass 34, count 0 2006.189.07:47:40.95#ibcon#end of sib2, iclass 34, count 0 2006.189.07:47:40.95#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:47:40.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:47:40.95#ibcon#[27=USB\r\n] 2006.189.07:47:40.95#ibcon#*before write, iclass 34, count 0 2006.189.07:47:40.95#ibcon#enter sib2, iclass 34, count 0 2006.189.07:47:40.95#ibcon#flushed, iclass 34, count 0 2006.189.07:47:40.95#ibcon#about to write, iclass 34, count 0 2006.189.07:47:40.95#ibcon#wrote, iclass 34, count 0 2006.189.07:47:40.95#ibcon#about to read 3, iclass 34, count 0 2006.189.07:47:40.98#ibcon#read 3, iclass 34, count 0 2006.189.07:47:40.98#ibcon#about to read 4, iclass 34, count 0 2006.189.07:47:40.98#ibcon#read 4, iclass 34, count 0 2006.189.07:47:40.98#ibcon#about to read 5, iclass 34, count 0 2006.189.07:47:40.98#ibcon#read 5, iclass 34, count 0 2006.189.07:47:40.98#ibcon#about to read 6, iclass 34, count 0 2006.189.07:47:40.98#ibcon#read 6, iclass 34, count 0 2006.189.07:47:40.98#ibcon#end of sib2, iclass 34, count 0 2006.189.07:47:40.98#ibcon#*after write, iclass 34, count 0 2006.189.07:47:40.98#ibcon#*before return 0, iclass 34, count 0 2006.189.07:47:40.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:47:40.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.07:47:40.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:47:40.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:47:40.98$vc4f8/vblo=2,640.99 2006.189.07:47:40.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.07:47:40.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.07:47:40.98#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:40.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:40.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:40.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:40.98#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:47:40.98#ibcon#first serial, iclass 36, count 0 2006.189.07:47:40.98#ibcon#enter sib2, iclass 36, count 0 2006.189.07:47:40.98#ibcon#flushed, iclass 36, count 0 2006.189.07:47:40.98#ibcon#about to write, iclass 36, count 0 2006.189.07:47:40.98#ibcon#wrote, iclass 36, count 0 2006.189.07:47:40.98#ibcon#about to read 3, iclass 36, count 0 2006.189.07:47:41.00#ibcon#read 3, iclass 36, count 0 2006.189.07:47:41.00#ibcon#about to read 4, iclass 36, count 0 2006.189.07:47:41.00#ibcon#read 4, iclass 36, count 0 2006.189.07:47:41.00#ibcon#about to read 5, iclass 36, count 0 2006.189.07:47:41.00#ibcon#read 5, iclass 36, count 0 2006.189.07:47:41.00#ibcon#about to read 6, iclass 36, count 0 2006.189.07:47:41.00#ibcon#read 6, iclass 36, count 0 2006.189.07:47:41.00#ibcon#end of sib2, iclass 36, count 0 2006.189.07:47:41.00#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:47:41.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:47:41.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:47:41.00#ibcon#*before write, iclass 36, count 0 2006.189.07:47:41.00#ibcon#enter sib2, iclass 36, count 0 2006.189.07:47:41.00#ibcon#flushed, iclass 36, count 0 2006.189.07:47:41.00#ibcon#about to write, iclass 36, count 0 2006.189.07:47:41.00#ibcon#wrote, iclass 36, count 0 2006.189.07:47:41.00#ibcon#about to read 3, iclass 36, count 0 2006.189.07:47:41.04#ibcon#read 3, iclass 36, count 0 2006.189.07:47:41.04#ibcon#about to read 4, iclass 36, count 0 2006.189.07:47:41.04#ibcon#read 4, iclass 36, count 0 2006.189.07:47:41.04#ibcon#about to read 5, iclass 36, count 0 2006.189.07:47:41.04#ibcon#read 5, iclass 36, count 0 2006.189.07:47:41.04#ibcon#about to read 6, iclass 36, count 0 2006.189.07:47:41.04#ibcon#read 6, iclass 36, count 0 2006.189.07:47:41.04#ibcon#end of sib2, iclass 36, count 0 2006.189.07:47:41.04#ibcon#*after write, iclass 36, count 0 2006.189.07:47:41.04#ibcon#*before return 0, iclass 36, count 0 2006.189.07:47:41.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:41.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.07:47:41.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:47:41.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:47:41.04$vc4f8/vb=2,4 2006.189.07:47:41.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.07:47:41.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.07:47:41.04#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:41.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:41.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:41.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:41.10#ibcon#enter wrdev, iclass 38, count 2 2006.189.07:47:41.10#ibcon#first serial, iclass 38, count 2 2006.189.07:47:41.10#ibcon#enter sib2, iclass 38, count 2 2006.189.07:47:41.10#ibcon#flushed, iclass 38, count 2 2006.189.07:47:41.10#ibcon#about to write, iclass 38, count 2 2006.189.07:47:41.10#ibcon#wrote, iclass 38, count 2 2006.189.07:47:41.10#ibcon#about to read 3, iclass 38, count 2 2006.189.07:47:41.12#ibcon#read 3, iclass 38, count 2 2006.189.07:47:41.12#ibcon#about to read 4, iclass 38, count 2 2006.189.07:47:41.12#ibcon#read 4, iclass 38, count 2 2006.189.07:47:41.12#ibcon#about to read 5, iclass 38, count 2 2006.189.07:47:41.12#ibcon#read 5, iclass 38, count 2 2006.189.07:47:41.12#ibcon#about to read 6, iclass 38, count 2 2006.189.07:47:41.12#ibcon#read 6, iclass 38, count 2 2006.189.07:47:41.12#ibcon#end of sib2, iclass 38, count 2 2006.189.07:47:41.12#ibcon#*mode == 0, iclass 38, count 2 2006.189.07:47:41.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.07:47:41.12#ibcon#[27=AT02-04\r\n] 2006.189.07:47:41.12#ibcon#*before write, iclass 38, count 2 2006.189.07:47:41.12#ibcon#enter sib2, iclass 38, count 2 2006.189.07:47:41.12#ibcon#flushed, iclass 38, count 2 2006.189.07:47:41.12#ibcon#about to write, iclass 38, count 2 2006.189.07:47:41.12#ibcon#wrote, iclass 38, count 2 2006.189.07:47:41.12#ibcon#about to read 3, iclass 38, count 2 2006.189.07:47:41.15#ibcon#read 3, iclass 38, count 2 2006.189.07:47:41.15#ibcon#about to read 4, iclass 38, count 2 2006.189.07:47:41.15#ibcon#read 4, iclass 38, count 2 2006.189.07:47:41.15#ibcon#about to read 5, iclass 38, count 2 2006.189.07:47:41.15#ibcon#read 5, iclass 38, count 2 2006.189.07:47:41.15#ibcon#about to read 6, iclass 38, count 2 2006.189.07:47:41.15#ibcon#read 6, iclass 38, count 2 2006.189.07:47:41.15#ibcon#end of sib2, iclass 38, count 2 2006.189.07:47:41.15#ibcon#*after write, iclass 38, count 2 2006.189.07:47:41.15#ibcon#*before return 0, iclass 38, count 2 2006.189.07:47:41.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:41.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.07:47:41.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.07:47:41.15#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:41.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:41.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:41.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:41.27#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:47:41.27#ibcon#first serial, iclass 38, count 0 2006.189.07:47:41.27#ibcon#enter sib2, iclass 38, count 0 2006.189.07:47:41.27#ibcon#flushed, iclass 38, count 0 2006.189.07:47:41.27#ibcon#about to write, iclass 38, count 0 2006.189.07:47:41.27#ibcon#wrote, iclass 38, count 0 2006.189.07:47:41.27#ibcon#about to read 3, iclass 38, count 0 2006.189.07:47:41.29#ibcon#read 3, iclass 38, count 0 2006.189.07:47:41.29#ibcon#about to read 4, iclass 38, count 0 2006.189.07:47:41.29#ibcon#read 4, iclass 38, count 0 2006.189.07:47:41.29#ibcon#about to read 5, iclass 38, count 0 2006.189.07:47:41.29#ibcon#read 5, iclass 38, count 0 2006.189.07:47:41.29#ibcon#about to read 6, iclass 38, count 0 2006.189.07:47:41.29#ibcon#read 6, iclass 38, count 0 2006.189.07:47:41.29#ibcon#end of sib2, iclass 38, count 0 2006.189.07:47:41.29#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:47:41.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:47:41.29#ibcon#[27=USB\r\n] 2006.189.07:47:41.29#ibcon#*before write, iclass 38, count 0 2006.189.07:47:41.29#ibcon#enter sib2, iclass 38, count 0 2006.189.07:47:41.29#ibcon#flushed, iclass 38, count 0 2006.189.07:47:41.29#ibcon#about to write, iclass 38, count 0 2006.189.07:47:41.29#ibcon#wrote, iclass 38, count 0 2006.189.07:47:41.29#ibcon#about to read 3, iclass 38, count 0 2006.189.07:47:41.32#ibcon#read 3, iclass 38, count 0 2006.189.07:47:41.32#ibcon#about to read 4, iclass 38, count 0 2006.189.07:47:41.32#ibcon#read 4, iclass 38, count 0 2006.189.07:47:41.32#ibcon#about to read 5, iclass 38, count 0 2006.189.07:47:41.32#ibcon#read 5, iclass 38, count 0 2006.189.07:47:41.32#ibcon#about to read 6, iclass 38, count 0 2006.189.07:47:41.32#ibcon#read 6, iclass 38, count 0 2006.189.07:47:41.32#ibcon#end of sib2, iclass 38, count 0 2006.189.07:47:41.32#ibcon#*after write, iclass 38, count 0 2006.189.07:47:41.32#ibcon#*before return 0, iclass 38, count 0 2006.189.07:47:41.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:41.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.07:47:41.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:47:41.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:47:41.32$vc4f8/vblo=3,656.99 2006.189.07:47:41.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.07:47:41.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.07:47:41.32#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:41.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:41.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:41.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:41.32#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:47:41.32#ibcon#first serial, iclass 40, count 0 2006.189.07:47:41.32#ibcon#enter sib2, iclass 40, count 0 2006.189.07:47:41.32#ibcon#flushed, iclass 40, count 0 2006.189.07:47:41.32#ibcon#about to write, iclass 40, count 0 2006.189.07:47:41.32#ibcon#wrote, iclass 40, count 0 2006.189.07:47:41.32#ibcon#about to read 3, iclass 40, count 0 2006.189.07:47:41.34#ibcon#read 3, iclass 40, count 0 2006.189.07:47:41.34#ibcon#about to read 4, iclass 40, count 0 2006.189.07:47:41.34#ibcon#read 4, iclass 40, count 0 2006.189.07:47:41.34#ibcon#about to read 5, iclass 40, count 0 2006.189.07:47:41.34#ibcon#read 5, iclass 40, count 0 2006.189.07:47:41.34#ibcon#about to read 6, iclass 40, count 0 2006.189.07:47:41.34#ibcon#read 6, iclass 40, count 0 2006.189.07:47:41.34#ibcon#end of sib2, iclass 40, count 0 2006.189.07:47:41.34#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:47:41.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:47:41.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:47:41.34#ibcon#*before write, iclass 40, count 0 2006.189.07:47:41.34#ibcon#enter sib2, iclass 40, count 0 2006.189.07:47:41.34#ibcon#flushed, iclass 40, count 0 2006.189.07:47:41.34#ibcon#about to write, iclass 40, count 0 2006.189.07:47:41.34#ibcon#wrote, iclass 40, count 0 2006.189.07:47:41.34#ibcon#about to read 3, iclass 40, count 0 2006.189.07:47:41.38#ibcon#read 3, iclass 40, count 0 2006.189.07:47:41.38#ibcon#about to read 4, iclass 40, count 0 2006.189.07:47:41.38#ibcon#read 4, iclass 40, count 0 2006.189.07:47:41.38#ibcon#about to read 5, iclass 40, count 0 2006.189.07:47:41.38#ibcon#read 5, iclass 40, count 0 2006.189.07:47:41.38#ibcon#about to read 6, iclass 40, count 0 2006.189.07:47:41.38#ibcon#read 6, iclass 40, count 0 2006.189.07:47:41.38#ibcon#end of sib2, iclass 40, count 0 2006.189.07:47:41.38#ibcon#*after write, iclass 40, count 0 2006.189.07:47:41.38#ibcon#*before return 0, iclass 40, count 0 2006.189.07:47:41.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:41.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.07:47:41.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:47:41.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:47:41.38$vc4f8/vb=3,4 2006.189.07:47:41.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.07:47:41.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.07:47:41.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:41.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:41.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:41.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:41.44#ibcon#enter wrdev, iclass 4, count 2 2006.189.07:47:41.44#ibcon#first serial, iclass 4, count 2 2006.189.07:47:41.44#ibcon#enter sib2, iclass 4, count 2 2006.189.07:47:41.44#ibcon#flushed, iclass 4, count 2 2006.189.07:47:41.44#ibcon#about to write, iclass 4, count 2 2006.189.07:47:41.44#ibcon#wrote, iclass 4, count 2 2006.189.07:47:41.44#ibcon#about to read 3, iclass 4, count 2 2006.189.07:47:41.46#ibcon#read 3, iclass 4, count 2 2006.189.07:47:41.46#ibcon#about to read 4, iclass 4, count 2 2006.189.07:47:41.46#ibcon#read 4, iclass 4, count 2 2006.189.07:47:41.46#ibcon#about to read 5, iclass 4, count 2 2006.189.07:47:41.46#ibcon#read 5, iclass 4, count 2 2006.189.07:47:41.46#ibcon#about to read 6, iclass 4, count 2 2006.189.07:47:41.46#ibcon#read 6, iclass 4, count 2 2006.189.07:47:41.46#ibcon#end of sib2, iclass 4, count 2 2006.189.07:47:41.46#ibcon#*mode == 0, iclass 4, count 2 2006.189.07:47:41.46#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.07:47:41.46#ibcon#[27=AT03-04\r\n] 2006.189.07:47:41.46#ibcon#*before write, iclass 4, count 2 2006.189.07:47:41.46#ibcon#enter sib2, iclass 4, count 2 2006.189.07:47:41.46#ibcon#flushed, iclass 4, count 2 2006.189.07:47:41.46#ibcon#about to write, iclass 4, count 2 2006.189.07:47:41.46#ibcon#wrote, iclass 4, count 2 2006.189.07:47:41.46#ibcon#about to read 3, iclass 4, count 2 2006.189.07:47:41.49#ibcon#read 3, iclass 4, count 2 2006.189.07:47:41.49#ibcon#about to read 4, iclass 4, count 2 2006.189.07:47:41.49#ibcon#read 4, iclass 4, count 2 2006.189.07:47:41.49#ibcon#about to read 5, iclass 4, count 2 2006.189.07:47:41.49#ibcon#read 5, iclass 4, count 2 2006.189.07:47:41.49#ibcon#about to read 6, iclass 4, count 2 2006.189.07:47:41.49#ibcon#read 6, iclass 4, count 2 2006.189.07:47:41.49#ibcon#end of sib2, iclass 4, count 2 2006.189.07:47:41.49#ibcon#*after write, iclass 4, count 2 2006.189.07:47:41.49#ibcon#*before return 0, iclass 4, count 2 2006.189.07:47:41.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:41.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.07:47:41.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.07:47:41.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:41.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:41.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:41.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:41.61#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:47:41.61#ibcon#first serial, iclass 4, count 0 2006.189.07:47:41.61#ibcon#enter sib2, iclass 4, count 0 2006.189.07:47:41.61#ibcon#flushed, iclass 4, count 0 2006.189.07:47:41.61#ibcon#about to write, iclass 4, count 0 2006.189.07:47:41.61#ibcon#wrote, iclass 4, count 0 2006.189.07:47:41.61#ibcon#about to read 3, iclass 4, count 0 2006.189.07:47:41.63#ibcon#read 3, iclass 4, count 0 2006.189.07:47:41.63#ibcon#about to read 4, iclass 4, count 0 2006.189.07:47:41.63#ibcon#read 4, iclass 4, count 0 2006.189.07:47:41.63#ibcon#about to read 5, iclass 4, count 0 2006.189.07:47:41.63#ibcon#read 5, iclass 4, count 0 2006.189.07:47:41.63#ibcon#about to read 6, iclass 4, count 0 2006.189.07:47:41.63#ibcon#read 6, iclass 4, count 0 2006.189.07:47:41.63#ibcon#end of sib2, iclass 4, count 0 2006.189.07:47:41.63#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:47:41.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:47:41.63#ibcon#[27=USB\r\n] 2006.189.07:47:41.63#ibcon#*before write, iclass 4, count 0 2006.189.07:47:41.63#ibcon#enter sib2, iclass 4, count 0 2006.189.07:47:41.63#ibcon#flushed, iclass 4, count 0 2006.189.07:47:41.63#ibcon#about to write, iclass 4, count 0 2006.189.07:47:41.63#ibcon#wrote, iclass 4, count 0 2006.189.07:47:41.63#ibcon#about to read 3, iclass 4, count 0 2006.189.07:47:41.66#ibcon#read 3, iclass 4, count 0 2006.189.07:47:41.66#ibcon#about to read 4, iclass 4, count 0 2006.189.07:47:41.66#ibcon#read 4, iclass 4, count 0 2006.189.07:47:41.66#ibcon#about to read 5, iclass 4, count 0 2006.189.07:47:41.66#ibcon#read 5, iclass 4, count 0 2006.189.07:47:41.66#ibcon#about to read 6, iclass 4, count 0 2006.189.07:47:41.66#ibcon#read 6, iclass 4, count 0 2006.189.07:47:41.66#ibcon#end of sib2, iclass 4, count 0 2006.189.07:47:41.66#ibcon#*after write, iclass 4, count 0 2006.189.07:47:41.66#ibcon#*before return 0, iclass 4, count 0 2006.189.07:47:41.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:41.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.07:47:41.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:47:41.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:47:41.66$vc4f8/vblo=4,712.99 2006.189.07:47:41.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:47:41.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:47:41.66#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:41.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:41.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:41.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:41.66#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:47:41.66#ibcon#first serial, iclass 6, count 0 2006.189.07:47:41.66#ibcon#enter sib2, iclass 6, count 0 2006.189.07:47:41.66#ibcon#flushed, iclass 6, count 0 2006.189.07:47:41.66#ibcon#about to write, iclass 6, count 0 2006.189.07:47:41.66#ibcon#wrote, iclass 6, count 0 2006.189.07:47:41.66#ibcon#about to read 3, iclass 6, count 0 2006.189.07:47:41.68#ibcon#read 3, iclass 6, count 0 2006.189.07:47:41.68#ibcon#about to read 4, iclass 6, count 0 2006.189.07:47:41.68#ibcon#read 4, iclass 6, count 0 2006.189.07:47:41.68#ibcon#about to read 5, iclass 6, count 0 2006.189.07:47:41.68#ibcon#read 5, iclass 6, count 0 2006.189.07:47:41.68#ibcon#about to read 6, iclass 6, count 0 2006.189.07:47:41.68#ibcon#read 6, iclass 6, count 0 2006.189.07:47:41.68#ibcon#end of sib2, iclass 6, count 0 2006.189.07:47:41.68#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:47:41.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:47:41.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:47:41.68#ibcon#*before write, iclass 6, count 0 2006.189.07:47:41.68#ibcon#enter sib2, iclass 6, count 0 2006.189.07:47:41.68#ibcon#flushed, iclass 6, count 0 2006.189.07:47:41.68#ibcon#about to write, iclass 6, count 0 2006.189.07:47:41.68#ibcon#wrote, iclass 6, count 0 2006.189.07:47:41.68#ibcon#about to read 3, iclass 6, count 0 2006.189.07:47:41.72#ibcon#read 3, iclass 6, count 0 2006.189.07:47:41.72#ibcon#about to read 4, iclass 6, count 0 2006.189.07:47:41.72#ibcon#read 4, iclass 6, count 0 2006.189.07:47:41.72#ibcon#about to read 5, iclass 6, count 0 2006.189.07:47:41.72#ibcon#read 5, iclass 6, count 0 2006.189.07:47:41.72#ibcon#about to read 6, iclass 6, count 0 2006.189.07:47:41.72#ibcon#read 6, iclass 6, count 0 2006.189.07:47:41.72#ibcon#end of sib2, iclass 6, count 0 2006.189.07:47:41.72#ibcon#*after write, iclass 6, count 0 2006.189.07:47:41.72#ibcon#*before return 0, iclass 6, count 0 2006.189.07:47:41.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:41.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:47:41.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:47:41.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:47:41.72$vc4f8/vb=4,4 2006.189.07:47:41.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.07:47:41.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.07:47:41.72#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:41.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:41.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:41.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:41.78#ibcon#enter wrdev, iclass 10, count 2 2006.189.07:47:41.78#ibcon#first serial, iclass 10, count 2 2006.189.07:47:41.78#ibcon#enter sib2, iclass 10, count 2 2006.189.07:47:41.78#ibcon#flushed, iclass 10, count 2 2006.189.07:47:41.78#ibcon#about to write, iclass 10, count 2 2006.189.07:47:41.78#ibcon#wrote, iclass 10, count 2 2006.189.07:47:41.78#ibcon#about to read 3, iclass 10, count 2 2006.189.07:47:41.80#ibcon#read 3, iclass 10, count 2 2006.189.07:47:41.80#ibcon#about to read 4, iclass 10, count 2 2006.189.07:47:41.80#ibcon#read 4, iclass 10, count 2 2006.189.07:47:41.80#ibcon#about to read 5, iclass 10, count 2 2006.189.07:47:41.80#ibcon#read 5, iclass 10, count 2 2006.189.07:47:41.80#ibcon#about to read 6, iclass 10, count 2 2006.189.07:47:41.80#ibcon#read 6, iclass 10, count 2 2006.189.07:47:41.80#ibcon#end of sib2, iclass 10, count 2 2006.189.07:47:41.80#ibcon#*mode == 0, iclass 10, count 2 2006.189.07:47:41.80#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.07:47:41.80#ibcon#[27=AT04-04\r\n] 2006.189.07:47:41.80#ibcon#*before write, iclass 10, count 2 2006.189.07:47:41.80#ibcon#enter sib2, iclass 10, count 2 2006.189.07:47:41.80#ibcon#flushed, iclass 10, count 2 2006.189.07:47:41.80#ibcon#about to write, iclass 10, count 2 2006.189.07:47:41.80#ibcon#wrote, iclass 10, count 2 2006.189.07:47:41.80#ibcon#about to read 3, iclass 10, count 2 2006.189.07:47:41.83#ibcon#read 3, iclass 10, count 2 2006.189.07:47:41.83#ibcon#about to read 4, iclass 10, count 2 2006.189.07:47:41.83#ibcon#read 4, iclass 10, count 2 2006.189.07:47:41.83#ibcon#about to read 5, iclass 10, count 2 2006.189.07:47:41.83#ibcon#read 5, iclass 10, count 2 2006.189.07:47:41.83#ibcon#about to read 6, iclass 10, count 2 2006.189.07:47:41.83#ibcon#read 6, iclass 10, count 2 2006.189.07:47:41.83#ibcon#end of sib2, iclass 10, count 2 2006.189.07:47:41.83#ibcon#*after write, iclass 10, count 2 2006.189.07:47:41.83#ibcon#*before return 0, iclass 10, count 2 2006.189.07:47:41.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:41.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.07:47:41.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.07:47:41.83#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:41.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:41.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:41.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:41.95#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:47:41.95#ibcon#first serial, iclass 10, count 0 2006.189.07:47:41.95#ibcon#enter sib2, iclass 10, count 0 2006.189.07:47:41.95#ibcon#flushed, iclass 10, count 0 2006.189.07:47:41.95#ibcon#about to write, iclass 10, count 0 2006.189.07:47:41.95#ibcon#wrote, iclass 10, count 0 2006.189.07:47:41.95#ibcon#about to read 3, iclass 10, count 0 2006.189.07:47:41.97#ibcon#read 3, iclass 10, count 0 2006.189.07:47:41.97#ibcon#about to read 4, iclass 10, count 0 2006.189.07:47:41.97#ibcon#read 4, iclass 10, count 0 2006.189.07:47:41.97#ibcon#about to read 5, iclass 10, count 0 2006.189.07:47:41.97#ibcon#read 5, iclass 10, count 0 2006.189.07:47:41.97#ibcon#about to read 6, iclass 10, count 0 2006.189.07:47:41.97#ibcon#read 6, iclass 10, count 0 2006.189.07:47:41.97#ibcon#end of sib2, iclass 10, count 0 2006.189.07:47:41.97#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:47:41.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:47:41.97#ibcon#[27=USB\r\n] 2006.189.07:47:41.97#ibcon#*before write, iclass 10, count 0 2006.189.07:47:41.97#ibcon#enter sib2, iclass 10, count 0 2006.189.07:47:41.97#ibcon#flushed, iclass 10, count 0 2006.189.07:47:41.97#ibcon#about to write, iclass 10, count 0 2006.189.07:47:41.97#ibcon#wrote, iclass 10, count 0 2006.189.07:47:41.97#ibcon#about to read 3, iclass 10, count 0 2006.189.07:47:42.00#ibcon#read 3, iclass 10, count 0 2006.189.07:47:42.00#ibcon#about to read 4, iclass 10, count 0 2006.189.07:47:42.00#ibcon#read 4, iclass 10, count 0 2006.189.07:47:42.00#ibcon#about to read 5, iclass 10, count 0 2006.189.07:47:42.00#ibcon#read 5, iclass 10, count 0 2006.189.07:47:42.00#ibcon#about to read 6, iclass 10, count 0 2006.189.07:47:42.00#ibcon#read 6, iclass 10, count 0 2006.189.07:47:42.00#ibcon#end of sib2, iclass 10, count 0 2006.189.07:47:42.00#ibcon#*after write, iclass 10, count 0 2006.189.07:47:42.00#ibcon#*before return 0, iclass 10, count 0 2006.189.07:47:42.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:42.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.07:47:42.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:47:42.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:47:42.00$vc4f8/vblo=5,744.99 2006.189.07:47:42.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.07:47:42.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.07:47:42.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:42.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:42.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:42.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:42.00#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:47:42.00#ibcon#first serial, iclass 12, count 0 2006.189.07:47:42.00#ibcon#enter sib2, iclass 12, count 0 2006.189.07:47:42.00#ibcon#flushed, iclass 12, count 0 2006.189.07:47:42.00#ibcon#about to write, iclass 12, count 0 2006.189.07:47:42.00#ibcon#wrote, iclass 12, count 0 2006.189.07:47:42.00#ibcon#about to read 3, iclass 12, count 0 2006.189.07:47:42.02#ibcon#read 3, iclass 12, count 0 2006.189.07:47:42.02#ibcon#about to read 4, iclass 12, count 0 2006.189.07:47:42.02#ibcon#read 4, iclass 12, count 0 2006.189.07:47:42.02#ibcon#about to read 5, iclass 12, count 0 2006.189.07:47:42.02#ibcon#read 5, iclass 12, count 0 2006.189.07:47:42.02#ibcon#about to read 6, iclass 12, count 0 2006.189.07:47:42.02#ibcon#read 6, iclass 12, count 0 2006.189.07:47:42.02#ibcon#end of sib2, iclass 12, count 0 2006.189.07:47:42.02#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:47:42.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:47:42.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:47:42.02#ibcon#*before write, iclass 12, count 0 2006.189.07:47:42.02#ibcon#enter sib2, iclass 12, count 0 2006.189.07:47:42.02#ibcon#flushed, iclass 12, count 0 2006.189.07:47:42.02#ibcon#about to write, iclass 12, count 0 2006.189.07:47:42.02#ibcon#wrote, iclass 12, count 0 2006.189.07:47:42.02#ibcon#about to read 3, iclass 12, count 0 2006.189.07:47:42.06#ibcon#read 3, iclass 12, count 0 2006.189.07:47:42.06#ibcon#about to read 4, iclass 12, count 0 2006.189.07:47:42.06#ibcon#read 4, iclass 12, count 0 2006.189.07:47:42.06#ibcon#about to read 5, iclass 12, count 0 2006.189.07:47:42.06#ibcon#read 5, iclass 12, count 0 2006.189.07:47:42.06#ibcon#about to read 6, iclass 12, count 0 2006.189.07:47:42.06#ibcon#read 6, iclass 12, count 0 2006.189.07:47:42.06#ibcon#end of sib2, iclass 12, count 0 2006.189.07:47:42.06#ibcon#*after write, iclass 12, count 0 2006.189.07:47:42.06#ibcon#*before return 0, iclass 12, count 0 2006.189.07:47:42.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:42.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.07:47:42.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:47:42.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:47:42.06$vc4f8/vb=5,4 2006.189.07:47:42.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.07:47:42.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.07:47:42.06#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:42.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:42.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:42.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:42.12#ibcon#enter wrdev, iclass 14, count 2 2006.189.07:47:42.12#ibcon#first serial, iclass 14, count 2 2006.189.07:47:42.12#ibcon#enter sib2, iclass 14, count 2 2006.189.07:47:42.12#ibcon#flushed, iclass 14, count 2 2006.189.07:47:42.12#ibcon#about to write, iclass 14, count 2 2006.189.07:47:42.12#ibcon#wrote, iclass 14, count 2 2006.189.07:47:42.12#ibcon#about to read 3, iclass 14, count 2 2006.189.07:47:42.14#ibcon#read 3, iclass 14, count 2 2006.189.07:47:42.14#ibcon#about to read 4, iclass 14, count 2 2006.189.07:47:42.14#ibcon#read 4, iclass 14, count 2 2006.189.07:47:42.14#ibcon#about to read 5, iclass 14, count 2 2006.189.07:47:42.14#ibcon#read 5, iclass 14, count 2 2006.189.07:47:42.14#ibcon#about to read 6, iclass 14, count 2 2006.189.07:47:42.14#ibcon#read 6, iclass 14, count 2 2006.189.07:47:42.14#ibcon#end of sib2, iclass 14, count 2 2006.189.07:47:42.14#ibcon#*mode == 0, iclass 14, count 2 2006.189.07:47:42.14#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.07:47:42.14#ibcon#[27=AT05-04\r\n] 2006.189.07:47:42.14#ibcon#*before write, iclass 14, count 2 2006.189.07:47:42.14#ibcon#enter sib2, iclass 14, count 2 2006.189.07:47:42.14#ibcon#flushed, iclass 14, count 2 2006.189.07:47:42.14#ibcon#about to write, iclass 14, count 2 2006.189.07:47:42.14#ibcon#wrote, iclass 14, count 2 2006.189.07:47:42.14#ibcon#about to read 3, iclass 14, count 2 2006.189.07:47:42.17#ibcon#read 3, iclass 14, count 2 2006.189.07:47:42.17#ibcon#about to read 4, iclass 14, count 2 2006.189.07:47:42.17#ibcon#read 4, iclass 14, count 2 2006.189.07:47:42.17#ibcon#about to read 5, iclass 14, count 2 2006.189.07:47:42.17#ibcon#read 5, iclass 14, count 2 2006.189.07:47:42.17#ibcon#about to read 6, iclass 14, count 2 2006.189.07:47:42.17#ibcon#read 6, iclass 14, count 2 2006.189.07:47:42.17#ibcon#end of sib2, iclass 14, count 2 2006.189.07:47:42.17#ibcon#*after write, iclass 14, count 2 2006.189.07:47:42.17#ibcon#*before return 0, iclass 14, count 2 2006.189.07:47:42.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:42.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.07:47:42.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.07:47:42.17#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:42.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:42.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:42.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:42.29#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:47:42.29#ibcon#first serial, iclass 14, count 0 2006.189.07:47:42.29#ibcon#enter sib2, iclass 14, count 0 2006.189.07:47:42.29#ibcon#flushed, iclass 14, count 0 2006.189.07:47:42.29#ibcon#about to write, iclass 14, count 0 2006.189.07:47:42.29#ibcon#wrote, iclass 14, count 0 2006.189.07:47:42.29#ibcon#about to read 3, iclass 14, count 0 2006.189.07:47:42.31#ibcon#read 3, iclass 14, count 0 2006.189.07:47:42.31#ibcon#about to read 4, iclass 14, count 0 2006.189.07:47:42.31#ibcon#read 4, iclass 14, count 0 2006.189.07:47:42.31#ibcon#about to read 5, iclass 14, count 0 2006.189.07:47:42.31#ibcon#read 5, iclass 14, count 0 2006.189.07:47:42.31#ibcon#about to read 6, iclass 14, count 0 2006.189.07:47:42.31#ibcon#read 6, iclass 14, count 0 2006.189.07:47:42.31#ibcon#end of sib2, iclass 14, count 0 2006.189.07:47:42.31#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:47:42.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:47:42.31#ibcon#[27=USB\r\n] 2006.189.07:47:42.31#ibcon#*before write, iclass 14, count 0 2006.189.07:47:42.31#ibcon#enter sib2, iclass 14, count 0 2006.189.07:47:42.31#ibcon#flushed, iclass 14, count 0 2006.189.07:47:42.31#ibcon#about to write, iclass 14, count 0 2006.189.07:47:42.31#ibcon#wrote, iclass 14, count 0 2006.189.07:47:42.31#ibcon#about to read 3, iclass 14, count 0 2006.189.07:47:42.34#ibcon#read 3, iclass 14, count 0 2006.189.07:47:42.34#ibcon#about to read 4, iclass 14, count 0 2006.189.07:47:42.34#ibcon#read 4, iclass 14, count 0 2006.189.07:47:42.34#ibcon#about to read 5, iclass 14, count 0 2006.189.07:47:42.34#ibcon#read 5, iclass 14, count 0 2006.189.07:47:42.34#ibcon#about to read 6, iclass 14, count 0 2006.189.07:47:42.34#ibcon#read 6, iclass 14, count 0 2006.189.07:47:42.34#ibcon#end of sib2, iclass 14, count 0 2006.189.07:47:42.34#ibcon#*after write, iclass 14, count 0 2006.189.07:47:42.34#ibcon#*before return 0, iclass 14, count 0 2006.189.07:47:42.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:42.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.07:47:42.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:47:42.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:47:42.34$vc4f8/vblo=6,752.99 2006.189.07:47:42.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.07:47:42.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.07:47:42.34#ibcon#ireg 17 cls_cnt 0 2006.189.07:47:42.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:42.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:42.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:42.34#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:47:42.34#ibcon#first serial, iclass 16, count 0 2006.189.07:47:42.34#ibcon#enter sib2, iclass 16, count 0 2006.189.07:47:42.34#ibcon#flushed, iclass 16, count 0 2006.189.07:47:42.34#ibcon#about to write, iclass 16, count 0 2006.189.07:47:42.34#ibcon#wrote, iclass 16, count 0 2006.189.07:47:42.34#ibcon#about to read 3, iclass 16, count 0 2006.189.07:47:42.36#ibcon#read 3, iclass 16, count 0 2006.189.07:47:42.36#ibcon#about to read 4, iclass 16, count 0 2006.189.07:47:42.36#ibcon#read 4, iclass 16, count 0 2006.189.07:47:42.36#ibcon#about to read 5, iclass 16, count 0 2006.189.07:47:42.36#ibcon#read 5, iclass 16, count 0 2006.189.07:47:42.36#ibcon#about to read 6, iclass 16, count 0 2006.189.07:47:42.36#ibcon#read 6, iclass 16, count 0 2006.189.07:47:42.36#ibcon#end of sib2, iclass 16, count 0 2006.189.07:47:42.36#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:47:42.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:47:42.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:47:42.36#ibcon#*before write, iclass 16, count 0 2006.189.07:47:42.36#ibcon#enter sib2, iclass 16, count 0 2006.189.07:47:42.36#ibcon#flushed, iclass 16, count 0 2006.189.07:47:42.36#ibcon#about to write, iclass 16, count 0 2006.189.07:47:42.36#ibcon#wrote, iclass 16, count 0 2006.189.07:47:42.36#ibcon#about to read 3, iclass 16, count 0 2006.189.07:47:42.40#ibcon#read 3, iclass 16, count 0 2006.189.07:47:42.40#ibcon#about to read 4, iclass 16, count 0 2006.189.07:47:42.40#ibcon#read 4, iclass 16, count 0 2006.189.07:47:42.40#ibcon#about to read 5, iclass 16, count 0 2006.189.07:47:42.40#ibcon#read 5, iclass 16, count 0 2006.189.07:47:42.40#ibcon#about to read 6, iclass 16, count 0 2006.189.07:47:42.40#ibcon#read 6, iclass 16, count 0 2006.189.07:47:42.40#ibcon#end of sib2, iclass 16, count 0 2006.189.07:47:42.40#ibcon#*after write, iclass 16, count 0 2006.189.07:47:42.40#ibcon#*before return 0, iclass 16, count 0 2006.189.07:47:42.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:42.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.07:47:42.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:47:42.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:47:42.40$vc4f8/vb=6,4 2006.189.07:47:42.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.07:47:42.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.07:47:42.40#ibcon#ireg 11 cls_cnt 2 2006.189.07:47:42.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:42.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:42.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:42.46#ibcon#enter wrdev, iclass 18, count 2 2006.189.07:47:42.46#ibcon#first serial, iclass 18, count 2 2006.189.07:47:42.46#ibcon#enter sib2, iclass 18, count 2 2006.189.07:47:42.46#ibcon#flushed, iclass 18, count 2 2006.189.07:47:42.46#ibcon#about to write, iclass 18, count 2 2006.189.07:47:42.46#ibcon#wrote, iclass 18, count 2 2006.189.07:47:42.46#ibcon#about to read 3, iclass 18, count 2 2006.189.07:47:42.48#ibcon#read 3, iclass 18, count 2 2006.189.07:47:42.48#ibcon#about to read 4, iclass 18, count 2 2006.189.07:47:42.48#ibcon#read 4, iclass 18, count 2 2006.189.07:47:42.48#ibcon#about to read 5, iclass 18, count 2 2006.189.07:47:42.48#ibcon#read 5, iclass 18, count 2 2006.189.07:47:42.48#ibcon#about to read 6, iclass 18, count 2 2006.189.07:47:42.48#ibcon#read 6, iclass 18, count 2 2006.189.07:47:42.48#ibcon#end of sib2, iclass 18, count 2 2006.189.07:47:42.48#ibcon#*mode == 0, iclass 18, count 2 2006.189.07:47:42.48#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.07:47:42.48#ibcon#[27=AT06-04\r\n] 2006.189.07:47:42.48#ibcon#*before write, iclass 18, count 2 2006.189.07:47:42.48#ibcon#enter sib2, iclass 18, count 2 2006.189.07:47:42.48#ibcon#flushed, iclass 18, count 2 2006.189.07:47:42.48#ibcon#about to write, iclass 18, count 2 2006.189.07:47:42.48#ibcon#wrote, iclass 18, count 2 2006.189.07:47:42.48#ibcon#about to read 3, iclass 18, count 2 2006.189.07:47:42.51#ibcon#read 3, iclass 18, count 2 2006.189.07:47:42.51#ibcon#about to read 4, iclass 18, count 2 2006.189.07:47:42.51#ibcon#read 4, iclass 18, count 2 2006.189.07:47:42.51#ibcon#about to read 5, iclass 18, count 2 2006.189.07:47:42.51#ibcon#read 5, iclass 18, count 2 2006.189.07:47:42.51#ibcon#about to read 6, iclass 18, count 2 2006.189.07:47:42.51#ibcon#read 6, iclass 18, count 2 2006.189.07:47:42.51#ibcon#end of sib2, iclass 18, count 2 2006.189.07:47:42.51#ibcon#*after write, iclass 18, count 2 2006.189.07:47:42.51#ibcon#*before return 0, iclass 18, count 2 2006.189.07:47:42.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:42.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.07:47:42.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.07:47:42.51#ibcon#ireg 7 cls_cnt 0 2006.189.07:47:42.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:42.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:42.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:42.63#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:47:42.63#ibcon#first serial, iclass 18, count 0 2006.189.07:47:42.63#ibcon#enter sib2, iclass 18, count 0 2006.189.07:47:42.63#ibcon#flushed, iclass 18, count 0 2006.189.07:47:42.63#ibcon#about to write, iclass 18, count 0 2006.189.07:47:42.63#ibcon#wrote, iclass 18, count 0 2006.189.07:47:42.63#ibcon#about to read 3, iclass 18, count 0 2006.189.07:47:42.65#ibcon#read 3, iclass 18, count 0 2006.189.07:47:42.65#ibcon#about to read 4, iclass 18, count 0 2006.189.07:47:42.65#ibcon#read 4, iclass 18, count 0 2006.189.07:47:42.65#ibcon#about to read 5, iclass 18, count 0 2006.189.07:47:42.65#ibcon#read 5, iclass 18, count 0 2006.189.07:47:42.65#ibcon#about to read 6, iclass 18, count 0 2006.189.07:47:42.65#ibcon#read 6, iclass 18, count 0 2006.189.07:47:42.65#ibcon#end of sib2, iclass 18, count 0 2006.189.07:47:42.65#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:47:42.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:47:42.65#ibcon#[27=USB\r\n] 2006.189.07:47:42.65#ibcon#*before write, iclass 18, count 0 2006.189.07:47:42.65#ibcon#enter sib2, iclass 18, count 0 2006.189.07:47:42.65#ibcon#flushed, iclass 18, count 0 2006.189.07:47:42.65#ibcon#about to write, iclass 18, count 0 2006.189.07:47:42.65#ibcon#wrote, iclass 18, count 0 2006.189.07:47:42.65#ibcon#about to read 3, iclass 18, count 0 2006.189.07:47:42.68#ibcon#read 3, iclass 18, count 0 2006.189.07:47:42.68#ibcon#about to read 4, iclass 18, count 0 2006.189.07:47:42.68#ibcon#read 4, iclass 18, count 0 2006.189.07:47:42.68#ibcon#about to read 5, iclass 18, count 0 2006.189.07:47:42.68#ibcon#read 5, iclass 18, count 0 2006.189.07:47:42.68#ibcon#about to read 6, iclass 18, count 0 2006.189.07:47:42.68#ibcon#read 6, iclass 18, count 0 2006.189.07:47:42.68#ibcon#end of sib2, iclass 18, count 0 2006.189.07:47:42.68#ibcon#*after write, iclass 18, count 0 2006.189.07:47:42.68#ibcon#*before return 0, iclass 18, count 0 2006.189.07:47:42.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:42.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.07:47:42.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:47:42.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:47:42.68$vc4f8/vabw=wide 2006.189.07:47:42.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.07:47:42.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.07:47:42.68#ibcon#ireg 8 cls_cnt 0 2006.189.07:47:42.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:42.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:42.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:42.68#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:47:42.68#ibcon#first serial, iclass 20, count 0 2006.189.07:47:42.68#ibcon#enter sib2, iclass 20, count 0 2006.189.07:47:42.68#ibcon#flushed, iclass 20, count 0 2006.189.07:47:42.68#ibcon#about to write, iclass 20, count 0 2006.189.07:47:42.68#ibcon#wrote, iclass 20, count 0 2006.189.07:47:42.68#ibcon#about to read 3, iclass 20, count 0 2006.189.07:47:42.70#ibcon#read 3, iclass 20, count 0 2006.189.07:47:42.70#ibcon#about to read 4, iclass 20, count 0 2006.189.07:47:42.70#ibcon#read 4, iclass 20, count 0 2006.189.07:47:42.70#ibcon#about to read 5, iclass 20, count 0 2006.189.07:47:42.70#ibcon#read 5, iclass 20, count 0 2006.189.07:47:42.70#ibcon#about to read 6, iclass 20, count 0 2006.189.07:47:42.70#ibcon#read 6, iclass 20, count 0 2006.189.07:47:42.70#ibcon#end of sib2, iclass 20, count 0 2006.189.07:47:42.70#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:47:42.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:47:42.70#ibcon#[25=BW32\r\n] 2006.189.07:47:42.70#ibcon#*before write, iclass 20, count 0 2006.189.07:47:42.70#ibcon#enter sib2, iclass 20, count 0 2006.189.07:47:42.70#ibcon#flushed, iclass 20, count 0 2006.189.07:47:42.70#ibcon#about to write, iclass 20, count 0 2006.189.07:47:42.70#ibcon#wrote, iclass 20, count 0 2006.189.07:47:42.70#ibcon#about to read 3, iclass 20, count 0 2006.189.07:47:42.73#ibcon#read 3, iclass 20, count 0 2006.189.07:47:42.73#ibcon#about to read 4, iclass 20, count 0 2006.189.07:47:42.73#ibcon#read 4, iclass 20, count 0 2006.189.07:47:42.73#ibcon#about to read 5, iclass 20, count 0 2006.189.07:47:42.73#ibcon#read 5, iclass 20, count 0 2006.189.07:47:42.73#ibcon#about to read 6, iclass 20, count 0 2006.189.07:47:42.73#ibcon#read 6, iclass 20, count 0 2006.189.07:47:42.73#ibcon#end of sib2, iclass 20, count 0 2006.189.07:47:42.73#ibcon#*after write, iclass 20, count 0 2006.189.07:47:42.73#ibcon#*before return 0, iclass 20, count 0 2006.189.07:47:42.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:42.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.07:47:42.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:47:42.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:47:42.73$vc4f8/vbbw=wide 2006.189.07:47:42.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:47:42.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:47:42.73#ibcon#ireg 8 cls_cnt 0 2006.189.07:47:42.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:47:42.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:47:42.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:47:42.80#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:47:42.80#ibcon#first serial, iclass 22, count 0 2006.189.07:47:42.80#ibcon#enter sib2, iclass 22, count 0 2006.189.07:47:42.80#ibcon#flushed, iclass 22, count 0 2006.189.07:47:42.80#ibcon#about to write, iclass 22, count 0 2006.189.07:47:42.80#ibcon#wrote, iclass 22, count 0 2006.189.07:47:42.80#ibcon#about to read 3, iclass 22, count 0 2006.189.07:47:42.82#ibcon#read 3, iclass 22, count 0 2006.189.07:47:42.82#ibcon#about to read 4, iclass 22, count 0 2006.189.07:47:42.82#ibcon#read 4, iclass 22, count 0 2006.189.07:47:42.82#ibcon#about to read 5, iclass 22, count 0 2006.189.07:47:42.82#ibcon#read 5, iclass 22, count 0 2006.189.07:47:42.82#ibcon#about to read 6, iclass 22, count 0 2006.189.07:47:42.82#ibcon#read 6, iclass 22, count 0 2006.189.07:47:42.82#ibcon#end of sib2, iclass 22, count 0 2006.189.07:47:42.82#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:47:42.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:47:42.82#ibcon#[27=BW32\r\n] 2006.189.07:47:42.82#ibcon#*before write, iclass 22, count 0 2006.189.07:47:42.82#ibcon#enter sib2, iclass 22, count 0 2006.189.07:47:42.82#ibcon#flushed, iclass 22, count 0 2006.189.07:47:42.82#ibcon#about to write, iclass 22, count 0 2006.189.07:47:42.82#ibcon#wrote, iclass 22, count 0 2006.189.07:47:42.82#ibcon#about to read 3, iclass 22, count 0 2006.189.07:47:42.85#ibcon#read 3, iclass 22, count 0 2006.189.07:47:42.85#ibcon#about to read 4, iclass 22, count 0 2006.189.07:47:42.85#ibcon#read 4, iclass 22, count 0 2006.189.07:47:42.85#ibcon#about to read 5, iclass 22, count 0 2006.189.07:47:42.85#ibcon#read 5, iclass 22, count 0 2006.189.07:47:42.85#ibcon#about to read 6, iclass 22, count 0 2006.189.07:47:42.85#ibcon#read 6, iclass 22, count 0 2006.189.07:47:42.85#ibcon#end of sib2, iclass 22, count 0 2006.189.07:47:42.85#ibcon#*after write, iclass 22, count 0 2006.189.07:47:42.85#ibcon#*before return 0, iclass 22, count 0 2006.189.07:47:42.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:47:42.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:47:42.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:47:42.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:47:42.85$4f8m12a/ifd4f 2006.189.07:47:42.85$ifd4f/lo= 2006.189.07:47:42.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:47:42.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:47:42.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:47:42.85$ifd4f/patch= 2006.189.07:47:42.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:47:42.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:47:42.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:47:42.85$4f8m12a/"form=m,16.000,1:2 2006.189.07:47:42.85$4f8m12a/"tpicd 2006.189.07:47:42.85$4f8m12a/echo=off 2006.189.07:47:42.85$4f8m12a/xlog=off 2006.189.07:47:42.85:!2006.189.07:48:10 2006.189.07:47:50.14#trakl#Source acquired 2006.189.07:47:52.14#flagr#flagr/antenna,acquired 2006.189.07:48:10.00:preob 2006.189.07:48:11.14/onsource/TRACKING 2006.189.07:48:11.14:!2006.189.07:48:20 2006.189.07:48:20.00:data_valid=on 2006.189.07:48:20.00:midob 2006.189.07:48:20.14/onsource/TRACKING 2006.189.07:48:20.14/wx/26.03,1009.0,88 2006.189.07:48:20.33/cable/+6.4545E-03 2006.189.07:48:21.42/va/01,08,usb,yes,29,31 2006.189.07:48:21.42/va/02,07,usb,yes,29,30 2006.189.07:48:21.42/va/03,06,usb,yes,31,31 2006.189.07:48:21.42/va/04,07,usb,yes,30,32 2006.189.07:48:21.42/va/05,07,usb,yes,32,33 2006.189.07:48:21.42/va/06,06,usb,yes,31,30 2006.189.07:48:21.42/va/07,06,usb,yes,31,31 2006.189.07:48:21.42/va/08,06,usb,yes,33,33 2006.189.07:48:21.65/valo/01,532.99,yes,locked 2006.189.07:48:21.65/valo/02,572.99,yes,locked 2006.189.07:48:21.65/valo/03,672.99,yes,locked 2006.189.07:48:21.65/valo/04,832.99,yes,locked 2006.189.07:48:21.65/valo/05,652.99,yes,locked 2006.189.07:48:21.65/valo/06,772.99,yes,locked 2006.189.07:48:21.65/valo/07,832.99,yes,locked 2006.189.07:48:21.65/valo/08,852.99,yes,locked 2006.189.07:48:22.74/vb/01,04,usb,yes,29,28 2006.189.07:48:22.74/vb/02,04,usb,yes,31,32 2006.189.07:48:22.74/vb/03,04,usb,yes,27,31 2006.189.07:48:22.74/vb/04,04,usb,yes,28,28 2006.189.07:48:22.74/vb/05,04,usb,yes,27,30 2006.189.07:48:22.74/vb/06,04,usb,yes,28,30 2006.189.07:48:22.74/vb/07,04,usb,yes,30,29 2006.189.07:48:22.74/vb/08,04,usb,yes,27,30 2006.189.07:48:22.97/vblo/01,632.99,yes,locked 2006.189.07:48:22.97/vblo/02,640.99,yes,locked 2006.189.07:48:22.97/vblo/03,656.99,yes,locked 2006.189.07:48:22.97/vblo/04,712.99,yes,locked 2006.189.07:48:22.97/vblo/05,744.99,yes,locked 2006.189.07:48:22.97/vblo/06,752.99,yes,locked 2006.189.07:48:22.97/vblo/07,734.99,yes,locked 2006.189.07:48:22.97/vblo/08,744.99,yes,locked 2006.189.07:48:23.12/vabw/8 2006.189.07:48:23.27/vbbw/8 2006.189.07:48:23.36/xfe/off,on,15.0 2006.189.07:48:23.73/ifatt/23,28,28,28 2006.189.07:48:24.08/fmout-gps/S +2.97E-07 2006.189.07:48:24.16:!2006.189.07:49:20 2006.189.07:49:20.01:data_valid=off 2006.189.07:49:20.02:postob 2006.189.07:49:20.10/cable/+6.4543E-03 2006.189.07:49:20.11/wx/26.00,1009.0,89 2006.189.07:49:21.07/fmout-gps/S +2.97E-07 2006.189.07:49:21.07:scan_name=189-0750,k06189,60 2006.189.07:49:21.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.189.07:49:21.14#flagr#flagr/antenna,new-source 2006.189.07:49:22.14:checkk5 2006.189.07:49:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:49:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:49:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:49:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:49:24.06/chk_obsdata//k5ts1/T1890748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:49:24.44/chk_obsdata//k5ts2/T1890748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:49:24.82/chk_obsdata//k5ts3/T1890748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:49:25.20/chk_obsdata//k5ts4/T1890748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:49:25.89/k5log//k5ts1_log_newline 2006.189.07:49:26.59/k5log//k5ts2_log_newline 2006.189.07:49:27.29/k5log//k5ts3_log_newline 2006.189.07:49:27.99/k5log//k5ts4_log_newline 2006.189.07:49:28.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:49:28.01:4f8m12a=1 2006.189.07:49:28.01$4f8m12a/echo=on 2006.189.07:49:28.01$4f8m12a/pcalon 2006.189.07:49:28.01$pcalon/"no phase cal control is implemented here 2006.189.07:49:28.01$4f8m12a/"tpicd=stop 2006.189.07:49:28.01$4f8m12a/vc4f8 2006.189.07:49:28.01$vc4f8/valo=1,532.99 2006.189.07:49:28.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:49:28.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:49:28.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:28.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:28.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:28.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:28.01#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:49:28.01#ibcon#first serial, iclass 33, count 0 2006.189.07:49:28.01#ibcon#enter sib2, iclass 33, count 0 2006.189.07:49:28.01#ibcon#flushed, iclass 33, count 0 2006.189.07:49:28.01#ibcon#about to write, iclass 33, count 0 2006.189.07:49:28.01#ibcon#wrote, iclass 33, count 0 2006.189.07:49:28.01#ibcon#about to read 3, iclass 33, count 0 2006.189.07:49:28.06#ibcon#read 3, iclass 33, count 0 2006.189.07:49:28.06#ibcon#about to read 4, iclass 33, count 0 2006.189.07:49:28.06#ibcon#read 4, iclass 33, count 0 2006.189.07:49:28.06#ibcon#about to read 5, iclass 33, count 0 2006.189.07:49:28.06#ibcon#read 5, iclass 33, count 0 2006.189.07:49:28.06#ibcon#about to read 6, iclass 33, count 0 2006.189.07:49:28.06#ibcon#read 6, iclass 33, count 0 2006.189.07:49:28.06#ibcon#end of sib2, iclass 33, count 0 2006.189.07:49:28.06#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:49:28.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:49:28.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:49:28.06#ibcon#*before write, iclass 33, count 0 2006.189.07:49:28.06#ibcon#enter sib2, iclass 33, count 0 2006.189.07:49:28.06#ibcon#flushed, iclass 33, count 0 2006.189.07:49:28.06#ibcon#about to write, iclass 33, count 0 2006.189.07:49:28.06#ibcon#wrote, iclass 33, count 0 2006.189.07:49:28.06#ibcon#about to read 3, iclass 33, count 0 2006.189.07:49:28.11#ibcon#read 3, iclass 33, count 0 2006.189.07:49:28.11#ibcon#about to read 4, iclass 33, count 0 2006.189.07:49:28.11#ibcon#read 4, iclass 33, count 0 2006.189.07:49:28.11#ibcon#about to read 5, iclass 33, count 0 2006.189.07:49:28.11#ibcon#read 5, iclass 33, count 0 2006.189.07:49:28.11#ibcon#about to read 6, iclass 33, count 0 2006.189.07:49:28.11#ibcon#read 6, iclass 33, count 0 2006.189.07:49:28.11#ibcon#end of sib2, iclass 33, count 0 2006.189.07:49:28.11#ibcon#*after write, iclass 33, count 0 2006.189.07:49:28.11#ibcon#*before return 0, iclass 33, count 0 2006.189.07:49:28.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:28.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:28.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:49:28.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:49:28.11$vc4f8/va=1,8 2006.189.07:49:28.11#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:49:28.11#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:49:28.11#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:28.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:28.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:28.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:28.11#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:49:28.11#ibcon#first serial, iclass 35, count 2 2006.189.07:49:28.11#ibcon#enter sib2, iclass 35, count 2 2006.189.07:49:28.11#ibcon#flushed, iclass 35, count 2 2006.189.07:49:28.11#ibcon#about to write, iclass 35, count 2 2006.189.07:49:28.11#ibcon#wrote, iclass 35, count 2 2006.189.07:49:28.11#ibcon#about to read 3, iclass 35, count 2 2006.189.07:49:28.13#ibcon#read 3, iclass 35, count 2 2006.189.07:49:28.13#ibcon#about to read 4, iclass 35, count 2 2006.189.07:49:28.13#ibcon#read 4, iclass 35, count 2 2006.189.07:49:28.13#ibcon#about to read 5, iclass 35, count 2 2006.189.07:49:28.13#ibcon#read 5, iclass 35, count 2 2006.189.07:49:28.13#ibcon#about to read 6, iclass 35, count 2 2006.189.07:49:28.13#ibcon#read 6, iclass 35, count 2 2006.189.07:49:28.13#ibcon#end of sib2, iclass 35, count 2 2006.189.07:49:28.13#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:49:28.13#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:49:28.13#ibcon#[25=AT01-08\r\n] 2006.189.07:49:28.13#ibcon#*before write, iclass 35, count 2 2006.189.07:49:28.13#ibcon#enter sib2, iclass 35, count 2 2006.189.07:49:28.13#ibcon#flushed, iclass 35, count 2 2006.189.07:49:28.13#ibcon#about to write, iclass 35, count 2 2006.189.07:49:28.13#ibcon#wrote, iclass 35, count 2 2006.189.07:49:28.13#ibcon#about to read 3, iclass 35, count 2 2006.189.07:49:28.16#ibcon#read 3, iclass 35, count 2 2006.189.07:49:28.16#ibcon#about to read 4, iclass 35, count 2 2006.189.07:49:28.16#ibcon#read 4, iclass 35, count 2 2006.189.07:49:28.16#ibcon#about to read 5, iclass 35, count 2 2006.189.07:49:28.16#ibcon#read 5, iclass 35, count 2 2006.189.07:49:28.16#ibcon#about to read 6, iclass 35, count 2 2006.189.07:49:28.16#ibcon#read 6, iclass 35, count 2 2006.189.07:49:28.16#ibcon#end of sib2, iclass 35, count 2 2006.189.07:49:28.16#ibcon#*after write, iclass 35, count 2 2006.189.07:49:28.16#ibcon#*before return 0, iclass 35, count 2 2006.189.07:49:28.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:28.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:28.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:49:28.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:28.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:28.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:28.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:28.28#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:49:28.28#ibcon#first serial, iclass 35, count 0 2006.189.07:49:28.28#ibcon#enter sib2, iclass 35, count 0 2006.189.07:49:28.28#ibcon#flushed, iclass 35, count 0 2006.189.07:49:28.28#ibcon#about to write, iclass 35, count 0 2006.189.07:49:28.28#ibcon#wrote, iclass 35, count 0 2006.189.07:49:28.28#ibcon#about to read 3, iclass 35, count 0 2006.189.07:49:28.30#ibcon#read 3, iclass 35, count 0 2006.189.07:49:28.30#ibcon#about to read 4, iclass 35, count 0 2006.189.07:49:28.30#ibcon#read 4, iclass 35, count 0 2006.189.07:49:28.30#ibcon#about to read 5, iclass 35, count 0 2006.189.07:49:28.30#ibcon#read 5, iclass 35, count 0 2006.189.07:49:28.30#ibcon#about to read 6, iclass 35, count 0 2006.189.07:49:28.30#ibcon#read 6, iclass 35, count 0 2006.189.07:49:28.30#ibcon#end of sib2, iclass 35, count 0 2006.189.07:49:28.30#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:49:28.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:49:28.30#ibcon#[25=USB\r\n] 2006.189.07:49:28.30#ibcon#*before write, iclass 35, count 0 2006.189.07:49:28.30#ibcon#enter sib2, iclass 35, count 0 2006.189.07:49:28.30#ibcon#flushed, iclass 35, count 0 2006.189.07:49:28.30#ibcon#about to write, iclass 35, count 0 2006.189.07:49:28.30#ibcon#wrote, iclass 35, count 0 2006.189.07:49:28.30#ibcon#about to read 3, iclass 35, count 0 2006.189.07:49:28.33#ibcon#read 3, iclass 35, count 0 2006.189.07:49:28.33#ibcon#about to read 4, iclass 35, count 0 2006.189.07:49:28.33#ibcon#read 4, iclass 35, count 0 2006.189.07:49:28.33#ibcon#about to read 5, iclass 35, count 0 2006.189.07:49:28.33#ibcon#read 5, iclass 35, count 0 2006.189.07:49:28.33#ibcon#about to read 6, iclass 35, count 0 2006.189.07:49:28.33#ibcon#read 6, iclass 35, count 0 2006.189.07:49:28.33#ibcon#end of sib2, iclass 35, count 0 2006.189.07:49:28.33#ibcon#*after write, iclass 35, count 0 2006.189.07:49:28.33#ibcon#*before return 0, iclass 35, count 0 2006.189.07:49:28.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:28.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:28.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:49:28.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:49:28.33$vc4f8/valo=2,572.99 2006.189.07:49:28.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:49:28.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:49:28.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:28.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:28.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:28.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:28.33#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:49:28.33#ibcon#first serial, iclass 37, count 0 2006.189.07:49:28.33#ibcon#enter sib2, iclass 37, count 0 2006.189.07:49:28.33#ibcon#flushed, iclass 37, count 0 2006.189.07:49:28.33#ibcon#about to write, iclass 37, count 0 2006.189.07:49:28.33#ibcon#wrote, iclass 37, count 0 2006.189.07:49:28.33#ibcon#about to read 3, iclass 37, count 0 2006.189.07:49:28.35#ibcon#read 3, iclass 37, count 0 2006.189.07:49:28.35#ibcon#about to read 4, iclass 37, count 0 2006.189.07:49:28.35#ibcon#read 4, iclass 37, count 0 2006.189.07:49:28.35#ibcon#about to read 5, iclass 37, count 0 2006.189.07:49:28.35#ibcon#read 5, iclass 37, count 0 2006.189.07:49:28.35#ibcon#about to read 6, iclass 37, count 0 2006.189.07:49:28.35#ibcon#read 6, iclass 37, count 0 2006.189.07:49:28.35#ibcon#end of sib2, iclass 37, count 0 2006.189.07:49:28.35#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:49:28.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:49:28.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:49:28.35#ibcon#*before write, iclass 37, count 0 2006.189.07:49:28.35#ibcon#enter sib2, iclass 37, count 0 2006.189.07:49:28.35#ibcon#flushed, iclass 37, count 0 2006.189.07:49:28.35#ibcon#about to write, iclass 37, count 0 2006.189.07:49:28.35#ibcon#wrote, iclass 37, count 0 2006.189.07:49:28.35#ibcon#about to read 3, iclass 37, count 0 2006.189.07:49:28.40#ibcon#read 3, iclass 37, count 0 2006.189.07:49:28.40#ibcon#about to read 4, iclass 37, count 0 2006.189.07:49:28.40#ibcon#read 4, iclass 37, count 0 2006.189.07:49:28.40#ibcon#about to read 5, iclass 37, count 0 2006.189.07:49:28.40#ibcon#read 5, iclass 37, count 0 2006.189.07:49:28.40#ibcon#about to read 6, iclass 37, count 0 2006.189.07:49:28.40#ibcon#read 6, iclass 37, count 0 2006.189.07:49:28.40#ibcon#end of sib2, iclass 37, count 0 2006.189.07:49:28.40#ibcon#*after write, iclass 37, count 0 2006.189.07:49:28.40#ibcon#*before return 0, iclass 37, count 0 2006.189.07:49:28.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:28.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:28.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:49:28.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:49:28.40$vc4f8/va=2,7 2006.189.07:49:28.40#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:49:28.40#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:49:28.40#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:28.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:28.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:28.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:28.44#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:49:28.44#ibcon#first serial, iclass 39, count 2 2006.189.07:49:28.44#ibcon#enter sib2, iclass 39, count 2 2006.189.07:49:28.44#ibcon#flushed, iclass 39, count 2 2006.189.07:49:28.44#ibcon#about to write, iclass 39, count 2 2006.189.07:49:28.44#ibcon#wrote, iclass 39, count 2 2006.189.07:49:28.44#ibcon#about to read 3, iclass 39, count 2 2006.189.07:49:28.46#ibcon#read 3, iclass 39, count 2 2006.189.07:49:28.46#ibcon#about to read 4, iclass 39, count 2 2006.189.07:49:28.46#ibcon#read 4, iclass 39, count 2 2006.189.07:49:28.46#ibcon#about to read 5, iclass 39, count 2 2006.189.07:49:28.46#ibcon#read 5, iclass 39, count 2 2006.189.07:49:28.46#ibcon#about to read 6, iclass 39, count 2 2006.189.07:49:28.46#ibcon#read 6, iclass 39, count 2 2006.189.07:49:28.46#ibcon#end of sib2, iclass 39, count 2 2006.189.07:49:28.46#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:49:28.46#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:49:28.46#ibcon#[25=AT02-07\r\n] 2006.189.07:49:28.46#ibcon#*before write, iclass 39, count 2 2006.189.07:49:28.46#ibcon#enter sib2, iclass 39, count 2 2006.189.07:49:28.46#ibcon#flushed, iclass 39, count 2 2006.189.07:49:28.46#ibcon#about to write, iclass 39, count 2 2006.189.07:49:28.46#ibcon#wrote, iclass 39, count 2 2006.189.07:49:28.46#ibcon#about to read 3, iclass 39, count 2 2006.189.07:49:28.49#ibcon#read 3, iclass 39, count 2 2006.189.07:49:28.49#ibcon#about to read 4, iclass 39, count 2 2006.189.07:49:28.49#ibcon#read 4, iclass 39, count 2 2006.189.07:49:28.49#ibcon#about to read 5, iclass 39, count 2 2006.189.07:49:28.49#ibcon#read 5, iclass 39, count 2 2006.189.07:49:28.49#ibcon#about to read 6, iclass 39, count 2 2006.189.07:49:28.49#ibcon#read 6, iclass 39, count 2 2006.189.07:49:28.49#ibcon#end of sib2, iclass 39, count 2 2006.189.07:49:28.49#ibcon#*after write, iclass 39, count 2 2006.189.07:49:28.49#ibcon#*before return 0, iclass 39, count 2 2006.189.07:49:28.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:28.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:28.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:49:28.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:28.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:28.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:28.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:28.61#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:49:28.61#ibcon#first serial, iclass 39, count 0 2006.189.07:49:28.61#ibcon#enter sib2, iclass 39, count 0 2006.189.07:49:28.61#ibcon#flushed, iclass 39, count 0 2006.189.07:49:28.61#ibcon#about to write, iclass 39, count 0 2006.189.07:49:28.61#ibcon#wrote, iclass 39, count 0 2006.189.07:49:28.61#ibcon#about to read 3, iclass 39, count 0 2006.189.07:49:28.63#ibcon#read 3, iclass 39, count 0 2006.189.07:49:28.63#ibcon#about to read 4, iclass 39, count 0 2006.189.07:49:28.63#ibcon#read 4, iclass 39, count 0 2006.189.07:49:28.63#ibcon#about to read 5, iclass 39, count 0 2006.189.07:49:28.63#ibcon#read 5, iclass 39, count 0 2006.189.07:49:28.63#ibcon#about to read 6, iclass 39, count 0 2006.189.07:49:28.63#ibcon#read 6, iclass 39, count 0 2006.189.07:49:28.63#ibcon#end of sib2, iclass 39, count 0 2006.189.07:49:28.63#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:49:28.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:49:28.63#ibcon#[25=USB\r\n] 2006.189.07:49:28.63#ibcon#*before write, iclass 39, count 0 2006.189.07:49:28.63#ibcon#enter sib2, iclass 39, count 0 2006.189.07:49:28.63#ibcon#flushed, iclass 39, count 0 2006.189.07:49:28.63#ibcon#about to write, iclass 39, count 0 2006.189.07:49:28.63#ibcon#wrote, iclass 39, count 0 2006.189.07:49:28.63#ibcon#about to read 3, iclass 39, count 0 2006.189.07:49:28.66#ibcon#read 3, iclass 39, count 0 2006.189.07:49:28.66#ibcon#about to read 4, iclass 39, count 0 2006.189.07:49:28.66#ibcon#read 4, iclass 39, count 0 2006.189.07:49:28.66#ibcon#about to read 5, iclass 39, count 0 2006.189.07:49:28.66#ibcon#read 5, iclass 39, count 0 2006.189.07:49:28.66#ibcon#about to read 6, iclass 39, count 0 2006.189.07:49:28.66#ibcon#read 6, iclass 39, count 0 2006.189.07:49:28.66#ibcon#end of sib2, iclass 39, count 0 2006.189.07:49:28.66#ibcon#*after write, iclass 39, count 0 2006.189.07:49:28.66#ibcon#*before return 0, iclass 39, count 0 2006.189.07:49:28.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:28.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:28.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:49:28.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:49:28.66$vc4f8/valo=3,672.99 2006.189.07:49:28.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:49:28.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:49:28.66#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:28.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:28.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:28.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:28.66#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:49:28.66#ibcon#first serial, iclass 3, count 0 2006.189.07:49:28.66#ibcon#enter sib2, iclass 3, count 0 2006.189.07:49:28.66#ibcon#flushed, iclass 3, count 0 2006.189.07:49:28.66#ibcon#about to write, iclass 3, count 0 2006.189.07:49:28.66#ibcon#wrote, iclass 3, count 0 2006.189.07:49:28.66#ibcon#about to read 3, iclass 3, count 0 2006.189.07:49:28.68#ibcon#read 3, iclass 3, count 0 2006.189.07:49:28.68#ibcon#about to read 4, iclass 3, count 0 2006.189.07:49:28.68#ibcon#read 4, iclass 3, count 0 2006.189.07:49:28.68#ibcon#about to read 5, iclass 3, count 0 2006.189.07:49:28.68#ibcon#read 5, iclass 3, count 0 2006.189.07:49:28.68#ibcon#about to read 6, iclass 3, count 0 2006.189.07:49:28.68#ibcon#read 6, iclass 3, count 0 2006.189.07:49:28.68#ibcon#end of sib2, iclass 3, count 0 2006.189.07:49:28.68#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:49:28.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:49:28.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:49:28.68#ibcon#*before write, iclass 3, count 0 2006.189.07:49:28.68#ibcon#enter sib2, iclass 3, count 0 2006.189.07:49:28.68#ibcon#flushed, iclass 3, count 0 2006.189.07:49:28.68#ibcon#about to write, iclass 3, count 0 2006.189.07:49:28.68#ibcon#wrote, iclass 3, count 0 2006.189.07:49:28.68#ibcon#about to read 3, iclass 3, count 0 2006.189.07:49:28.72#ibcon#read 3, iclass 3, count 0 2006.189.07:49:28.72#ibcon#about to read 4, iclass 3, count 0 2006.189.07:49:28.72#ibcon#read 4, iclass 3, count 0 2006.189.07:49:28.72#ibcon#about to read 5, iclass 3, count 0 2006.189.07:49:28.72#ibcon#read 5, iclass 3, count 0 2006.189.07:49:28.72#ibcon#about to read 6, iclass 3, count 0 2006.189.07:49:28.72#ibcon#read 6, iclass 3, count 0 2006.189.07:49:28.72#ibcon#end of sib2, iclass 3, count 0 2006.189.07:49:28.72#ibcon#*after write, iclass 3, count 0 2006.189.07:49:28.72#ibcon#*before return 0, iclass 3, count 0 2006.189.07:49:28.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:28.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:28.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:49:28.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:49:28.72$vc4f8/va=3,6 2006.189.07:49:28.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:49:28.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:49:28.72#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:28.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:28.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:28.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:28.78#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:49:28.78#ibcon#first serial, iclass 5, count 2 2006.189.07:49:28.78#ibcon#enter sib2, iclass 5, count 2 2006.189.07:49:28.78#ibcon#flushed, iclass 5, count 2 2006.189.07:49:28.78#ibcon#about to write, iclass 5, count 2 2006.189.07:49:28.78#ibcon#wrote, iclass 5, count 2 2006.189.07:49:28.78#ibcon#about to read 3, iclass 5, count 2 2006.189.07:49:28.80#ibcon#read 3, iclass 5, count 2 2006.189.07:49:28.80#ibcon#about to read 4, iclass 5, count 2 2006.189.07:49:28.80#ibcon#read 4, iclass 5, count 2 2006.189.07:49:28.80#ibcon#about to read 5, iclass 5, count 2 2006.189.07:49:28.80#ibcon#read 5, iclass 5, count 2 2006.189.07:49:28.80#ibcon#about to read 6, iclass 5, count 2 2006.189.07:49:28.80#ibcon#read 6, iclass 5, count 2 2006.189.07:49:28.80#ibcon#end of sib2, iclass 5, count 2 2006.189.07:49:28.80#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:49:28.80#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:49:28.80#ibcon#[25=AT03-06\r\n] 2006.189.07:49:28.80#ibcon#*before write, iclass 5, count 2 2006.189.07:49:28.80#ibcon#enter sib2, iclass 5, count 2 2006.189.07:49:28.80#ibcon#flushed, iclass 5, count 2 2006.189.07:49:28.80#ibcon#about to write, iclass 5, count 2 2006.189.07:49:28.80#ibcon#wrote, iclass 5, count 2 2006.189.07:49:28.80#ibcon#about to read 3, iclass 5, count 2 2006.189.07:49:28.83#ibcon#read 3, iclass 5, count 2 2006.189.07:49:28.83#ibcon#about to read 4, iclass 5, count 2 2006.189.07:49:28.83#ibcon#read 4, iclass 5, count 2 2006.189.07:49:28.83#ibcon#about to read 5, iclass 5, count 2 2006.189.07:49:28.83#ibcon#read 5, iclass 5, count 2 2006.189.07:49:28.83#ibcon#about to read 6, iclass 5, count 2 2006.189.07:49:28.83#ibcon#read 6, iclass 5, count 2 2006.189.07:49:28.83#ibcon#end of sib2, iclass 5, count 2 2006.189.07:49:28.83#ibcon#*after write, iclass 5, count 2 2006.189.07:49:28.83#ibcon#*before return 0, iclass 5, count 2 2006.189.07:49:28.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:28.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:28.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:49:28.83#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:28.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:28.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:28.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:28.95#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:49:28.95#ibcon#first serial, iclass 5, count 0 2006.189.07:49:28.95#ibcon#enter sib2, iclass 5, count 0 2006.189.07:49:28.95#ibcon#flushed, iclass 5, count 0 2006.189.07:49:28.95#ibcon#about to write, iclass 5, count 0 2006.189.07:49:28.95#ibcon#wrote, iclass 5, count 0 2006.189.07:49:28.95#ibcon#about to read 3, iclass 5, count 0 2006.189.07:49:28.97#ibcon#read 3, iclass 5, count 0 2006.189.07:49:28.97#ibcon#about to read 4, iclass 5, count 0 2006.189.07:49:28.97#ibcon#read 4, iclass 5, count 0 2006.189.07:49:28.97#ibcon#about to read 5, iclass 5, count 0 2006.189.07:49:28.97#ibcon#read 5, iclass 5, count 0 2006.189.07:49:28.97#ibcon#about to read 6, iclass 5, count 0 2006.189.07:49:28.97#ibcon#read 6, iclass 5, count 0 2006.189.07:49:28.97#ibcon#end of sib2, iclass 5, count 0 2006.189.07:49:28.97#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:49:28.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:49:28.97#ibcon#[25=USB\r\n] 2006.189.07:49:28.97#ibcon#*before write, iclass 5, count 0 2006.189.07:49:28.97#ibcon#enter sib2, iclass 5, count 0 2006.189.07:49:28.97#ibcon#flushed, iclass 5, count 0 2006.189.07:49:28.97#ibcon#about to write, iclass 5, count 0 2006.189.07:49:28.97#ibcon#wrote, iclass 5, count 0 2006.189.07:49:28.97#ibcon#about to read 3, iclass 5, count 0 2006.189.07:49:29.00#ibcon#read 3, iclass 5, count 0 2006.189.07:49:29.00#ibcon#about to read 4, iclass 5, count 0 2006.189.07:49:29.00#ibcon#read 4, iclass 5, count 0 2006.189.07:49:29.00#ibcon#about to read 5, iclass 5, count 0 2006.189.07:49:29.00#ibcon#read 5, iclass 5, count 0 2006.189.07:49:29.00#ibcon#about to read 6, iclass 5, count 0 2006.189.07:49:29.00#ibcon#read 6, iclass 5, count 0 2006.189.07:49:29.00#ibcon#end of sib2, iclass 5, count 0 2006.189.07:49:29.00#ibcon#*after write, iclass 5, count 0 2006.189.07:49:29.00#ibcon#*before return 0, iclass 5, count 0 2006.189.07:49:29.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:29.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:29.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:49:29.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:49:29.00$vc4f8/valo=4,832.99 2006.189.07:49:29.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:49:29.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:49:29.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:29.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:29.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:29.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:29.00#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:49:29.00#ibcon#first serial, iclass 7, count 0 2006.189.07:49:29.00#ibcon#enter sib2, iclass 7, count 0 2006.189.07:49:29.00#ibcon#flushed, iclass 7, count 0 2006.189.07:49:29.00#ibcon#about to write, iclass 7, count 0 2006.189.07:49:29.00#ibcon#wrote, iclass 7, count 0 2006.189.07:49:29.00#ibcon#about to read 3, iclass 7, count 0 2006.189.07:49:29.02#ibcon#read 3, iclass 7, count 0 2006.189.07:49:29.02#ibcon#about to read 4, iclass 7, count 0 2006.189.07:49:29.02#ibcon#read 4, iclass 7, count 0 2006.189.07:49:29.02#ibcon#about to read 5, iclass 7, count 0 2006.189.07:49:29.02#ibcon#read 5, iclass 7, count 0 2006.189.07:49:29.02#ibcon#about to read 6, iclass 7, count 0 2006.189.07:49:29.02#ibcon#read 6, iclass 7, count 0 2006.189.07:49:29.02#ibcon#end of sib2, iclass 7, count 0 2006.189.07:49:29.02#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:49:29.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:49:29.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:49:29.02#ibcon#*before write, iclass 7, count 0 2006.189.07:49:29.02#ibcon#enter sib2, iclass 7, count 0 2006.189.07:49:29.02#ibcon#flushed, iclass 7, count 0 2006.189.07:49:29.02#ibcon#about to write, iclass 7, count 0 2006.189.07:49:29.02#ibcon#wrote, iclass 7, count 0 2006.189.07:49:29.02#ibcon#about to read 3, iclass 7, count 0 2006.189.07:49:29.06#ibcon#read 3, iclass 7, count 0 2006.189.07:49:29.06#ibcon#about to read 4, iclass 7, count 0 2006.189.07:49:29.06#ibcon#read 4, iclass 7, count 0 2006.189.07:49:29.06#ibcon#about to read 5, iclass 7, count 0 2006.189.07:49:29.06#ibcon#read 5, iclass 7, count 0 2006.189.07:49:29.06#ibcon#about to read 6, iclass 7, count 0 2006.189.07:49:29.06#ibcon#read 6, iclass 7, count 0 2006.189.07:49:29.06#ibcon#end of sib2, iclass 7, count 0 2006.189.07:49:29.06#ibcon#*after write, iclass 7, count 0 2006.189.07:49:29.06#ibcon#*before return 0, iclass 7, count 0 2006.189.07:49:29.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:29.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:29.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:49:29.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:49:29.06$vc4f8/va=4,7 2006.189.07:49:29.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:49:29.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:49:29.06#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:29.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:29.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:29.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:29.12#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:49:29.12#ibcon#first serial, iclass 11, count 2 2006.189.07:49:29.12#ibcon#enter sib2, iclass 11, count 2 2006.189.07:49:29.12#ibcon#flushed, iclass 11, count 2 2006.189.07:49:29.12#ibcon#about to write, iclass 11, count 2 2006.189.07:49:29.12#ibcon#wrote, iclass 11, count 2 2006.189.07:49:29.12#ibcon#about to read 3, iclass 11, count 2 2006.189.07:49:29.14#ibcon#read 3, iclass 11, count 2 2006.189.07:49:29.14#ibcon#about to read 4, iclass 11, count 2 2006.189.07:49:29.14#ibcon#read 4, iclass 11, count 2 2006.189.07:49:29.14#ibcon#about to read 5, iclass 11, count 2 2006.189.07:49:29.14#ibcon#read 5, iclass 11, count 2 2006.189.07:49:29.14#ibcon#about to read 6, iclass 11, count 2 2006.189.07:49:29.14#ibcon#read 6, iclass 11, count 2 2006.189.07:49:29.14#ibcon#end of sib2, iclass 11, count 2 2006.189.07:49:29.14#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:49:29.14#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:49:29.14#ibcon#[25=AT04-07\r\n] 2006.189.07:49:29.14#ibcon#*before write, iclass 11, count 2 2006.189.07:49:29.14#ibcon#enter sib2, iclass 11, count 2 2006.189.07:49:29.14#ibcon#flushed, iclass 11, count 2 2006.189.07:49:29.14#ibcon#about to write, iclass 11, count 2 2006.189.07:49:29.14#ibcon#wrote, iclass 11, count 2 2006.189.07:49:29.14#ibcon#about to read 3, iclass 11, count 2 2006.189.07:49:29.17#ibcon#read 3, iclass 11, count 2 2006.189.07:49:29.17#ibcon#about to read 4, iclass 11, count 2 2006.189.07:49:29.17#ibcon#read 4, iclass 11, count 2 2006.189.07:49:29.17#ibcon#about to read 5, iclass 11, count 2 2006.189.07:49:29.17#ibcon#read 5, iclass 11, count 2 2006.189.07:49:29.17#ibcon#about to read 6, iclass 11, count 2 2006.189.07:49:29.17#ibcon#read 6, iclass 11, count 2 2006.189.07:49:29.17#ibcon#end of sib2, iclass 11, count 2 2006.189.07:49:29.17#ibcon#*after write, iclass 11, count 2 2006.189.07:49:29.17#ibcon#*before return 0, iclass 11, count 2 2006.189.07:49:29.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:29.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:29.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:49:29.17#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:29.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:29.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:29.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:29.29#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:49:29.29#ibcon#first serial, iclass 11, count 0 2006.189.07:49:29.29#ibcon#enter sib2, iclass 11, count 0 2006.189.07:49:29.29#ibcon#flushed, iclass 11, count 0 2006.189.07:49:29.29#ibcon#about to write, iclass 11, count 0 2006.189.07:49:29.29#ibcon#wrote, iclass 11, count 0 2006.189.07:49:29.29#ibcon#about to read 3, iclass 11, count 0 2006.189.07:49:29.31#ibcon#read 3, iclass 11, count 0 2006.189.07:49:29.31#ibcon#about to read 4, iclass 11, count 0 2006.189.07:49:29.31#ibcon#read 4, iclass 11, count 0 2006.189.07:49:29.31#ibcon#about to read 5, iclass 11, count 0 2006.189.07:49:29.31#ibcon#read 5, iclass 11, count 0 2006.189.07:49:29.31#ibcon#about to read 6, iclass 11, count 0 2006.189.07:49:29.31#ibcon#read 6, iclass 11, count 0 2006.189.07:49:29.31#ibcon#end of sib2, iclass 11, count 0 2006.189.07:49:29.31#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:49:29.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:49:29.31#ibcon#[25=USB\r\n] 2006.189.07:49:29.31#ibcon#*before write, iclass 11, count 0 2006.189.07:49:29.31#ibcon#enter sib2, iclass 11, count 0 2006.189.07:49:29.31#ibcon#flushed, iclass 11, count 0 2006.189.07:49:29.31#ibcon#about to write, iclass 11, count 0 2006.189.07:49:29.31#ibcon#wrote, iclass 11, count 0 2006.189.07:49:29.31#ibcon#about to read 3, iclass 11, count 0 2006.189.07:49:29.34#ibcon#read 3, iclass 11, count 0 2006.189.07:49:29.34#ibcon#about to read 4, iclass 11, count 0 2006.189.07:49:29.34#ibcon#read 4, iclass 11, count 0 2006.189.07:49:29.34#ibcon#about to read 5, iclass 11, count 0 2006.189.07:49:29.34#ibcon#read 5, iclass 11, count 0 2006.189.07:49:29.34#ibcon#about to read 6, iclass 11, count 0 2006.189.07:49:29.34#ibcon#read 6, iclass 11, count 0 2006.189.07:49:29.34#ibcon#end of sib2, iclass 11, count 0 2006.189.07:49:29.34#ibcon#*after write, iclass 11, count 0 2006.189.07:49:29.34#ibcon#*before return 0, iclass 11, count 0 2006.189.07:49:29.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:29.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:29.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:49:29.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:49:29.34$vc4f8/valo=5,652.99 2006.189.07:49:29.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.07:49:29.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.07:49:29.34#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:29.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:29.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:29.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:29.34#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:49:29.34#ibcon#first serial, iclass 13, count 0 2006.189.07:49:29.34#ibcon#enter sib2, iclass 13, count 0 2006.189.07:49:29.34#ibcon#flushed, iclass 13, count 0 2006.189.07:49:29.34#ibcon#about to write, iclass 13, count 0 2006.189.07:49:29.34#ibcon#wrote, iclass 13, count 0 2006.189.07:49:29.34#ibcon#about to read 3, iclass 13, count 0 2006.189.07:49:29.36#ibcon#read 3, iclass 13, count 0 2006.189.07:49:29.36#ibcon#about to read 4, iclass 13, count 0 2006.189.07:49:29.36#ibcon#read 4, iclass 13, count 0 2006.189.07:49:29.36#ibcon#about to read 5, iclass 13, count 0 2006.189.07:49:29.36#ibcon#read 5, iclass 13, count 0 2006.189.07:49:29.36#ibcon#about to read 6, iclass 13, count 0 2006.189.07:49:29.36#ibcon#read 6, iclass 13, count 0 2006.189.07:49:29.36#ibcon#end of sib2, iclass 13, count 0 2006.189.07:49:29.36#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:49:29.36#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:49:29.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:49:29.36#ibcon#*before write, iclass 13, count 0 2006.189.07:49:29.36#ibcon#enter sib2, iclass 13, count 0 2006.189.07:49:29.36#ibcon#flushed, iclass 13, count 0 2006.189.07:49:29.36#ibcon#about to write, iclass 13, count 0 2006.189.07:49:29.36#ibcon#wrote, iclass 13, count 0 2006.189.07:49:29.36#ibcon#about to read 3, iclass 13, count 0 2006.189.07:49:29.40#ibcon#read 3, iclass 13, count 0 2006.189.07:49:29.40#ibcon#about to read 4, iclass 13, count 0 2006.189.07:49:29.40#ibcon#read 4, iclass 13, count 0 2006.189.07:49:29.40#ibcon#about to read 5, iclass 13, count 0 2006.189.07:49:29.40#ibcon#read 5, iclass 13, count 0 2006.189.07:49:29.40#ibcon#about to read 6, iclass 13, count 0 2006.189.07:49:29.40#ibcon#read 6, iclass 13, count 0 2006.189.07:49:29.40#ibcon#end of sib2, iclass 13, count 0 2006.189.07:49:29.40#ibcon#*after write, iclass 13, count 0 2006.189.07:49:29.40#ibcon#*before return 0, iclass 13, count 0 2006.189.07:49:29.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:29.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:29.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:49:29.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:49:29.40$vc4f8/va=5,7 2006.189.07:49:29.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.07:49:29.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.07:49:29.40#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:29.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:29.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:29.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:29.46#ibcon#enter wrdev, iclass 15, count 2 2006.189.07:49:29.46#ibcon#first serial, iclass 15, count 2 2006.189.07:49:29.46#ibcon#enter sib2, iclass 15, count 2 2006.189.07:49:29.46#ibcon#flushed, iclass 15, count 2 2006.189.07:49:29.46#ibcon#about to write, iclass 15, count 2 2006.189.07:49:29.46#ibcon#wrote, iclass 15, count 2 2006.189.07:49:29.46#ibcon#about to read 3, iclass 15, count 2 2006.189.07:49:29.48#ibcon#read 3, iclass 15, count 2 2006.189.07:49:29.48#ibcon#about to read 4, iclass 15, count 2 2006.189.07:49:29.48#ibcon#read 4, iclass 15, count 2 2006.189.07:49:29.48#ibcon#about to read 5, iclass 15, count 2 2006.189.07:49:29.48#ibcon#read 5, iclass 15, count 2 2006.189.07:49:29.48#ibcon#about to read 6, iclass 15, count 2 2006.189.07:49:29.48#ibcon#read 6, iclass 15, count 2 2006.189.07:49:29.48#ibcon#end of sib2, iclass 15, count 2 2006.189.07:49:29.48#ibcon#*mode == 0, iclass 15, count 2 2006.189.07:49:29.48#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.07:49:29.48#ibcon#[25=AT05-07\r\n] 2006.189.07:49:29.48#ibcon#*before write, iclass 15, count 2 2006.189.07:49:29.48#ibcon#enter sib2, iclass 15, count 2 2006.189.07:49:29.48#ibcon#flushed, iclass 15, count 2 2006.189.07:49:29.48#ibcon#about to write, iclass 15, count 2 2006.189.07:49:29.48#ibcon#wrote, iclass 15, count 2 2006.189.07:49:29.48#ibcon#about to read 3, iclass 15, count 2 2006.189.07:49:29.51#ibcon#read 3, iclass 15, count 2 2006.189.07:49:29.51#ibcon#about to read 4, iclass 15, count 2 2006.189.07:49:29.51#ibcon#read 4, iclass 15, count 2 2006.189.07:49:29.51#ibcon#about to read 5, iclass 15, count 2 2006.189.07:49:29.51#ibcon#read 5, iclass 15, count 2 2006.189.07:49:29.51#ibcon#about to read 6, iclass 15, count 2 2006.189.07:49:29.51#ibcon#read 6, iclass 15, count 2 2006.189.07:49:29.51#ibcon#end of sib2, iclass 15, count 2 2006.189.07:49:29.51#ibcon#*after write, iclass 15, count 2 2006.189.07:49:29.51#ibcon#*before return 0, iclass 15, count 2 2006.189.07:49:29.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:29.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:29.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.07:49:29.51#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:29.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:29.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:29.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:29.63#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:49:29.63#ibcon#first serial, iclass 15, count 0 2006.189.07:49:29.63#ibcon#enter sib2, iclass 15, count 0 2006.189.07:49:29.63#ibcon#flushed, iclass 15, count 0 2006.189.07:49:29.63#ibcon#about to write, iclass 15, count 0 2006.189.07:49:29.63#ibcon#wrote, iclass 15, count 0 2006.189.07:49:29.63#ibcon#about to read 3, iclass 15, count 0 2006.189.07:49:29.65#ibcon#read 3, iclass 15, count 0 2006.189.07:49:29.65#ibcon#about to read 4, iclass 15, count 0 2006.189.07:49:29.65#ibcon#read 4, iclass 15, count 0 2006.189.07:49:29.65#ibcon#about to read 5, iclass 15, count 0 2006.189.07:49:29.65#ibcon#read 5, iclass 15, count 0 2006.189.07:49:29.65#ibcon#about to read 6, iclass 15, count 0 2006.189.07:49:29.65#ibcon#read 6, iclass 15, count 0 2006.189.07:49:29.65#ibcon#end of sib2, iclass 15, count 0 2006.189.07:49:29.65#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:49:29.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:49:29.65#ibcon#[25=USB\r\n] 2006.189.07:49:29.65#ibcon#*before write, iclass 15, count 0 2006.189.07:49:29.65#ibcon#enter sib2, iclass 15, count 0 2006.189.07:49:29.65#ibcon#flushed, iclass 15, count 0 2006.189.07:49:29.65#ibcon#about to write, iclass 15, count 0 2006.189.07:49:29.65#ibcon#wrote, iclass 15, count 0 2006.189.07:49:29.65#ibcon#about to read 3, iclass 15, count 0 2006.189.07:49:29.68#ibcon#read 3, iclass 15, count 0 2006.189.07:49:29.68#ibcon#about to read 4, iclass 15, count 0 2006.189.07:49:29.68#ibcon#read 4, iclass 15, count 0 2006.189.07:49:29.68#ibcon#about to read 5, iclass 15, count 0 2006.189.07:49:29.68#ibcon#read 5, iclass 15, count 0 2006.189.07:49:29.68#ibcon#about to read 6, iclass 15, count 0 2006.189.07:49:29.68#ibcon#read 6, iclass 15, count 0 2006.189.07:49:29.68#ibcon#end of sib2, iclass 15, count 0 2006.189.07:49:29.68#ibcon#*after write, iclass 15, count 0 2006.189.07:49:29.68#ibcon#*before return 0, iclass 15, count 0 2006.189.07:49:29.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:29.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:29.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:49:29.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:49:29.68$vc4f8/valo=6,772.99 2006.189.07:49:29.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:49:29.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:49:29.68#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:29.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:29.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:29.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:29.68#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:49:29.68#ibcon#first serial, iclass 17, count 0 2006.189.07:49:29.68#ibcon#enter sib2, iclass 17, count 0 2006.189.07:49:29.68#ibcon#flushed, iclass 17, count 0 2006.189.07:49:29.68#ibcon#about to write, iclass 17, count 0 2006.189.07:49:29.68#ibcon#wrote, iclass 17, count 0 2006.189.07:49:29.68#ibcon#about to read 3, iclass 17, count 0 2006.189.07:49:29.70#ibcon#read 3, iclass 17, count 0 2006.189.07:49:29.70#ibcon#about to read 4, iclass 17, count 0 2006.189.07:49:29.70#ibcon#read 4, iclass 17, count 0 2006.189.07:49:29.70#ibcon#about to read 5, iclass 17, count 0 2006.189.07:49:29.70#ibcon#read 5, iclass 17, count 0 2006.189.07:49:29.70#ibcon#about to read 6, iclass 17, count 0 2006.189.07:49:29.70#ibcon#read 6, iclass 17, count 0 2006.189.07:49:29.70#ibcon#end of sib2, iclass 17, count 0 2006.189.07:49:29.70#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:49:29.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:49:29.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:49:29.70#ibcon#*before write, iclass 17, count 0 2006.189.07:49:29.70#ibcon#enter sib2, iclass 17, count 0 2006.189.07:49:29.70#ibcon#flushed, iclass 17, count 0 2006.189.07:49:29.70#ibcon#about to write, iclass 17, count 0 2006.189.07:49:29.70#ibcon#wrote, iclass 17, count 0 2006.189.07:49:29.70#ibcon#about to read 3, iclass 17, count 0 2006.189.07:49:29.74#ibcon#read 3, iclass 17, count 0 2006.189.07:49:29.74#ibcon#about to read 4, iclass 17, count 0 2006.189.07:49:29.74#ibcon#read 4, iclass 17, count 0 2006.189.07:49:29.74#ibcon#about to read 5, iclass 17, count 0 2006.189.07:49:29.74#ibcon#read 5, iclass 17, count 0 2006.189.07:49:29.74#ibcon#about to read 6, iclass 17, count 0 2006.189.07:49:29.74#ibcon#read 6, iclass 17, count 0 2006.189.07:49:29.74#ibcon#end of sib2, iclass 17, count 0 2006.189.07:49:29.74#ibcon#*after write, iclass 17, count 0 2006.189.07:49:29.74#ibcon#*before return 0, iclass 17, count 0 2006.189.07:49:29.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:29.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:29.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:49:29.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:49:29.74$vc4f8/va=6,6 2006.189.07:49:29.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.07:49:29.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.07:49:29.74#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:29.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:49:29.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:49:29.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:49:29.80#ibcon#enter wrdev, iclass 19, count 2 2006.189.07:49:29.80#ibcon#first serial, iclass 19, count 2 2006.189.07:49:29.80#ibcon#enter sib2, iclass 19, count 2 2006.189.07:49:29.80#ibcon#flushed, iclass 19, count 2 2006.189.07:49:29.80#ibcon#about to write, iclass 19, count 2 2006.189.07:49:29.80#ibcon#wrote, iclass 19, count 2 2006.189.07:49:29.80#ibcon#about to read 3, iclass 19, count 2 2006.189.07:49:29.82#ibcon#read 3, iclass 19, count 2 2006.189.07:49:29.82#ibcon#about to read 4, iclass 19, count 2 2006.189.07:49:29.82#ibcon#read 4, iclass 19, count 2 2006.189.07:49:29.82#ibcon#about to read 5, iclass 19, count 2 2006.189.07:49:29.82#ibcon#read 5, iclass 19, count 2 2006.189.07:49:29.82#ibcon#about to read 6, iclass 19, count 2 2006.189.07:49:29.82#ibcon#read 6, iclass 19, count 2 2006.189.07:49:29.82#ibcon#end of sib2, iclass 19, count 2 2006.189.07:49:29.82#ibcon#*mode == 0, iclass 19, count 2 2006.189.07:49:29.82#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.07:49:29.82#ibcon#[25=AT06-06\r\n] 2006.189.07:49:29.82#ibcon#*before write, iclass 19, count 2 2006.189.07:49:29.82#ibcon#enter sib2, iclass 19, count 2 2006.189.07:49:29.82#ibcon#flushed, iclass 19, count 2 2006.189.07:49:29.82#ibcon#about to write, iclass 19, count 2 2006.189.07:49:29.82#ibcon#wrote, iclass 19, count 2 2006.189.07:49:29.82#ibcon#about to read 3, iclass 19, count 2 2006.189.07:49:29.85#ibcon#read 3, iclass 19, count 2 2006.189.07:49:29.85#ibcon#about to read 4, iclass 19, count 2 2006.189.07:49:29.85#ibcon#read 4, iclass 19, count 2 2006.189.07:49:29.85#ibcon#about to read 5, iclass 19, count 2 2006.189.07:49:29.85#ibcon#read 5, iclass 19, count 2 2006.189.07:49:29.85#ibcon#about to read 6, iclass 19, count 2 2006.189.07:49:29.85#ibcon#read 6, iclass 19, count 2 2006.189.07:49:29.85#ibcon#end of sib2, iclass 19, count 2 2006.189.07:49:29.85#ibcon#*after write, iclass 19, count 2 2006.189.07:49:29.85#ibcon#*before return 0, iclass 19, count 2 2006.189.07:49:29.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:49:29.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:49:29.85#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.07:49:29.85#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:29.85#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:49:29.97#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:49:29.97#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:49:29.97#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:49:29.97#ibcon#first serial, iclass 19, count 0 2006.189.07:49:29.97#ibcon#enter sib2, iclass 19, count 0 2006.189.07:49:29.97#ibcon#flushed, iclass 19, count 0 2006.189.07:49:29.97#ibcon#about to write, iclass 19, count 0 2006.189.07:49:29.97#ibcon#wrote, iclass 19, count 0 2006.189.07:49:29.97#ibcon#about to read 3, iclass 19, count 0 2006.189.07:49:29.99#ibcon#read 3, iclass 19, count 0 2006.189.07:49:29.99#ibcon#about to read 4, iclass 19, count 0 2006.189.07:49:29.99#ibcon#read 4, iclass 19, count 0 2006.189.07:49:29.99#ibcon#about to read 5, iclass 19, count 0 2006.189.07:49:29.99#ibcon#read 5, iclass 19, count 0 2006.189.07:49:29.99#ibcon#about to read 6, iclass 19, count 0 2006.189.07:49:29.99#ibcon#read 6, iclass 19, count 0 2006.189.07:49:29.99#ibcon#end of sib2, iclass 19, count 0 2006.189.07:49:29.99#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:49:29.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:49:29.99#ibcon#[25=USB\r\n] 2006.189.07:49:29.99#ibcon#*before write, iclass 19, count 0 2006.189.07:49:29.99#ibcon#enter sib2, iclass 19, count 0 2006.189.07:49:29.99#ibcon#flushed, iclass 19, count 0 2006.189.07:49:29.99#ibcon#about to write, iclass 19, count 0 2006.189.07:49:29.99#ibcon#wrote, iclass 19, count 0 2006.189.07:49:29.99#ibcon#about to read 3, iclass 19, count 0 2006.189.07:49:30.02#ibcon#read 3, iclass 19, count 0 2006.189.07:49:30.02#ibcon#about to read 4, iclass 19, count 0 2006.189.07:49:30.02#ibcon#read 4, iclass 19, count 0 2006.189.07:49:30.02#ibcon#about to read 5, iclass 19, count 0 2006.189.07:49:30.02#ibcon#read 5, iclass 19, count 0 2006.189.07:49:30.02#ibcon#about to read 6, iclass 19, count 0 2006.189.07:49:30.02#ibcon#read 6, iclass 19, count 0 2006.189.07:49:30.02#ibcon#end of sib2, iclass 19, count 0 2006.189.07:49:30.02#ibcon#*after write, iclass 19, count 0 2006.189.07:49:30.02#ibcon#*before return 0, iclass 19, count 0 2006.189.07:49:30.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:49:30.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:49:30.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:49:30.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:49:30.02$vc4f8/valo=7,832.99 2006.189.07:49:30.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:49:30.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:49:30.02#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:30.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:49:30.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:49:30.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:49:30.02#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:49:30.02#ibcon#first serial, iclass 21, count 0 2006.189.07:49:30.02#ibcon#enter sib2, iclass 21, count 0 2006.189.07:49:30.02#ibcon#flushed, iclass 21, count 0 2006.189.07:49:30.02#ibcon#about to write, iclass 21, count 0 2006.189.07:49:30.02#ibcon#wrote, iclass 21, count 0 2006.189.07:49:30.02#ibcon#about to read 3, iclass 21, count 0 2006.189.07:49:30.04#ibcon#read 3, iclass 21, count 0 2006.189.07:49:30.04#ibcon#about to read 4, iclass 21, count 0 2006.189.07:49:30.04#ibcon#read 4, iclass 21, count 0 2006.189.07:49:30.04#ibcon#about to read 5, iclass 21, count 0 2006.189.07:49:30.04#ibcon#read 5, iclass 21, count 0 2006.189.07:49:30.04#ibcon#about to read 6, iclass 21, count 0 2006.189.07:49:30.04#ibcon#read 6, iclass 21, count 0 2006.189.07:49:30.04#ibcon#end of sib2, iclass 21, count 0 2006.189.07:49:30.04#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:49:30.04#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:49:30.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:49:30.04#ibcon#*before write, iclass 21, count 0 2006.189.07:49:30.04#ibcon#enter sib2, iclass 21, count 0 2006.189.07:49:30.04#ibcon#flushed, iclass 21, count 0 2006.189.07:49:30.04#ibcon#about to write, iclass 21, count 0 2006.189.07:49:30.04#ibcon#wrote, iclass 21, count 0 2006.189.07:49:30.04#ibcon#about to read 3, iclass 21, count 0 2006.189.07:49:30.08#ibcon#read 3, iclass 21, count 0 2006.189.07:49:30.08#ibcon#about to read 4, iclass 21, count 0 2006.189.07:49:30.08#ibcon#read 4, iclass 21, count 0 2006.189.07:49:30.08#ibcon#about to read 5, iclass 21, count 0 2006.189.07:49:30.08#ibcon#read 5, iclass 21, count 0 2006.189.07:49:30.08#ibcon#about to read 6, iclass 21, count 0 2006.189.07:49:30.08#ibcon#read 6, iclass 21, count 0 2006.189.07:49:30.08#ibcon#end of sib2, iclass 21, count 0 2006.189.07:49:30.08#ibcon#*after write, iclass 21, count 0 2006.189.07:49:30.08#ibcon#*before return 0, iclass 21, count 0 2006.189.07:49:30.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:49:30.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:49:30.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:49:30.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:49:30.08$vc4f8/va=7,6 2006.189.07:49:30.08#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:49:30.08#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:49:30.08#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:30.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:49:30.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:49:30.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:49:30.14#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:49:30.14#ibcon#first serial, iclass 23, count 2 2006.189.07:49:30.14#ibcon#enter sib2, iclass 23, count 2 2006.189.07:49:30.14#ibcon#flushed, iclass 23, count 2 2006.189.07:49:30.14#ibcon#about to write, iclass 23, count 2 2006.189.07:49:30.14#ibcon#wrote, iclass 23, count 2 2006.189.07:49:30.14#ibcon#about to read 3, iclass 23, count 2 2006.189.07:49:30.16#ibcon#read 3, iclass 23, count 2 2006.189.07:49:30.16#ibcon#about to read 4, iclass 23, count 2 2006.189.07:49:30.16#ibcon#read 4, iclass 23, count 2 2006.189.07:49:30.16#ibcon#about to read 5, iclass 23, count 2 2006.189.07:49:30.16#ibcon#read 5, iclass 23, count 2 2006.189.07:49:30.16#ibcon#about to read 6, iclass 23, count 2 2006.189.07:49:30.16#ibcon#read 6, iclass 23, count 2 2006.189.07:49:30.16#ibcon#end of sib2, iclass 23, count 2 2006.189.07:49:30.16#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:49:30.16#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:49:30.16#ibcon#[25=AT07-06\r\n] 2006.189.07:49:30.16#ibcon#*before write, iclass 23, count 2 2006.189.07:49:30.16#ibcon#enter sib2, iclass 23, count 2 2006.189.07:49:30.16#ibcon#flushed, iclass 23, count 2 2006.189.07:49:30.16#ibcon#about to write, iclass 23, count 2 2006.189.07:49:30.16#ibcon#wrote, iclass 23, count 2 2006.189.07:49:30.16#ibcon#about to read 3, iclass 23, count 2 2006.189.07:49:30.19#ibcon#read 3, iclass 23, count 2 2006.189.07:49:30.19#ibcon#about to read 4, iclass 23, count 2 2006.189.07:49:30.19#ibcon#read 4, iclass 23, count 2 2006.189.07:49:30.19#ibcon#about to read 5, iclass 23, count 2 2006.189.07:49:30.19#ibcon#read 5, iclass 23, count 2 2006.189.07:49:30.19#ibcon#about to read 6, iclass 23, count 2 2006.189.07:49:30.19#ibcon#read 6, iclass 23, count 2 2006.189.07:49:30.19#ibcon#end of sib2, iclass 23, count 2 2006.189.07:49:30.19#ibcon#*after write, iclass 23, count 2 2006.189.07:49:30.19#ibcon#*before return 0, iclass 23, count 2 2006.189.07:49:30.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:49:30.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:49:30.19#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:49:30.19#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:30.19#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:49:30.31#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:49:30.31#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:49:30.31#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:49:30.31#ibcon#first serial, iclass 23, count 0 2006.189.07:49:30.31#ibcon#enter sib2, iclass 23, count 0 2006.189.07:49:30.31#ibcon#flushed, iclass 23, count 0 2006.189.07:49:30.31#ibcon#about to write, iclass 23, count 0 2006.189.07:49:30.31#ibcon#wrote, iclass 23, count 0 2006.189.07:49:30.31#ibcon#about to read 3, iclass 23, count 0 2006.189.07:49:30.33#ibcon#read 3, iclass 23, count 0 2006.189.07:49:30.33#ibcon#about to read 4, iclass 23, count 0 2006.189.07:49:30.33#ibcon#read 4, iclass 23, count 0 2006.189.07:49:30.33#ibcon#about to read 5, iclass 23, count 0 2006.189.07:49:30.33#ibcon#read 5, iclass 23, count 0 2006.189.07:49:30.33#ibcon#about to read 6, iclass 23, count 0 2006.189.07:49:30.33#ibcon#read 6, iclass 23, count 0 2006.189.07:49:30.33#ibcon#end of sib2, iclass 23, count 0 2006.189.07:49:30.33#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:49:30.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:49:30.33#ibcon#[25=USB\r\n] 2006.189.07:49:30.33#ibcon#*before write, iclass 23, count 0 2006.189.07:49:30.33#ibcon#enter sib2, iclass 23, count 0 2006.189.07:49:30.33#ibcon#flushed, iclass 23, count 0 2006.189.07:49:30.33#ibcon#about to write, iclass 23, count 0 2006.189.07:49:30.33#ibcon#wrote, iclass 23, count 0 2006.189.07:49:30.33#ibcon#about to read 3, iclass 23, count 0 2006.189.07:49:30.36#ibcon#read 3, iclass 23, count 0 2006.189.07:49:30.36#ibcon#about to read 4, iclass 23, count 0 2006.189.07:49:30.36#ibcon#read 4, iclass 23, count 0 2006.189.07:49:30.36#ibcon#about to read 5, iclass 23, count 0 2006.189.07:49:30.36#ibcon#read 5, iclass 23, count 0 2006.189.07:49:30.36#ibcon#about to read 6, iclass 23, count 0 2006.189.07:49:30.36#ibcon#read 6, iclass 23, count 0 2006.189.07:49:30.36#ibcon#end of sib2, iclass 23, count 0 2006.189.07:49:30.36#ibcon#*after write, iclass 23, count 0 2006.189.07:49:30.36#ibcon#*before return 0, iclass 23, count 0 2006.189.07:49:30.36#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:49:30.36#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:49:30.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:49:30.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:49:30.36$vc4f8/valo=8,852.99 2006.189.07:49:30.36#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:49:30.36#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:49:30.36#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:30.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:49:30.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:49:30.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:49:30.36#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:49:30.36#ibcon#first serial, iclass 25, count 0 2006.189.07:49:30.36#ibcon#enter sib2, iclass 25, count 0 2006.189.07:49:30.36#ibcon#flushed, iclass 25, count 0 2006.189.07:49:30.36#ibcon#about to write, iclass 25, count 0 2006.189.07:49:30.36#ibcon#wrote, iclass 25, count 0 2006.189.07:49:30.36#ibcon#about to read 3, iclass 25, count 0 2006.189.07:49:30.38#ibcon#read 3, iclass 25, count 0 2006.189.07:49:30.38#ibcon#about to read 4, iclass 25, count 0 2006.189.07:49:30.38#ibcon#read 4, iclass 25, count 0 2006.189.07:49:30.38#ibcon#about to read 5, iclass 25, count 0 2006.189.07:49:30.38#ibcon#read 5, iclass 25, count 0 2006.189.07:49:30.38#ibcon#about to read 6, iclass 25, count 0 2006.189.07:49:30.38#ibcon#read 6, iclass 25, count 0 2006.189.07:49:30.38#ibcon#end of sib2, iclass 25, count 0 2006.189.07:49:30.38#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:49:30.38#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:49:30.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:49:30.38#ibcon#*before write, iclass 25, count 0 2006.189.07:49:30.38#ibcon#enter sib2, iclass 25, count 0 2006.189.07:49:30.38#ibcon#flushed, iclass 25, count 0 2006.189.07:49:30.38#ibcon#about to write, iclass 25, count 0 2006.189.07:49:30.38#ibcon#wrote, iclass 25, count 0 2006.189.07:49:30.38#ibcon#about to read 3, iclass 25, count 0 2006.189.07:49:30.42#ibcon#read 3, iclass 25, count 0 2006.189.07:49:30.42#ibcon#about to read 4, iclass 25, count 0 2006.189.07:49:30.42#ibcon#read 4, iclass 25, count 0 2006.189.07:49:30.42#ibcon#about to read 5, iclass 25, count 0 2006.189.07:49:30.42#ibcon#read 5, iclass 25, count 0 2006.189.07:49:30.42#ibcon#about to read 6, iclass 25, count 0 2006.189.07:49:30.42#ibcon#read 6, iclass 25, count 0 2006.189.07:49:30.42#ibcon#end of sib2, iclass 25, count 0 2006.189.07:49:30.42#ibcon#*after write, iclass 25, count 0 2006.189.07:49:30.42#ibcon#*before return 0, iclass 25, count 0 2006.189.07:49:30.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:49:30.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:49:30.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:49:30.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:49:30.42$vc4f8/va=8,6 2006.189.07:49:30.42#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:49:30.42#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:49:30.42#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:30.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:49:30.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:49:30.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:49:30.48#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:49:30.48#ibcon#first serial, iclass 27, count 2 2006.189.07:49:30.48#ibcon#enter sib2, iclass 27, count 2 2006.189.07:49:30.48#ibcon#flushed, iclass 27, count 2 2006.189.07:49:30.48#ibcon#about to write, iclass 27, count 2 2006.189.07:49:30.48#ibcon#wrote, iclass 27, count 2 2006.189.07:49:30.48#ibcon#about to read 3, iclass 27, count 2 2006.189.07:49:30.50#ibcon#read 3, iclass 27, count 2 2006.189.07:49:30.50#ibcon#about to read 4, iclass 27, count 2 2006.189.07:49:30.50#ibcon#read 4, iclass 27, count 2 2006.189.07:49:30.50#ibcon#about to read 5, iclass 27, count 2 2006.189.07:49:30.50#ibcon#read 5, iclass 27, count 2 2006.189.07:49:30.50#ibcon#about to read 6, iclass 27, count 2 2006.189.07:49:30.50#ibcon#read 6, iclass 27, count 2 2006.189.07:49:30.50#ibcon#end of sib2, iclass 27, count 2 2006.189.07:49:30.50#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:49:30.50#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:49:30.50#ibcon#[25=AT08-06\r\n] 2006.189.07:49:30.50#ibcon#*before write, iclass 27, count 2 2006.189.07:49:30.50#ibcon#enter sib2, iclass 27, count 2 2006.189.07:49:30.50#ibcon#flushed, iclass 27, count 2 2006.189.07:49:30.50#ibcon#about to write, iclass 27, count 2 2006.189.07:49:30.50#ibcon#wrote, iclass 27, count 2 2006.189.07:49:30.50#ibcon#about to read 3, iclass 27, count 2 2006.189.07:49:30.53#ibcon#read 3, iclass 27, count 2 2006.189.07:49:30.53#ibcon#about to read 4, iclass 27, count 2 2006.189.07:49:30.53#ibcon#read 4, iclass 27, count 2 2006.189.07:49:30.53#ibcon#about to read 5, iclass 27, count 2 2006.189.07:49:30.53#ibcon#read 5, iclass 27, count 2 2006.189.07:49:30.53#ibcon#about to read 6, iclass 27, count 2 2006.189.07:49:30.53#ibcon#read 6, iclass 27, count 2 2006.189.07:49:30.53#ibcon#end of sib2, iclass 27, count 2 2006.189.07:49:30.53#ibcon#*after write, iclass 27, count 2 2006.189.07:49:30.53#ibcon#*before return 0, iclass 27, count 2 2006.189.07:49:30.53#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:49:30.53#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:49:30.53#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:49:30.53#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:30.53#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:49:30.65#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:49:30.65#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:49:30.65#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:49:30.65#ibcon#first serial, iclass 27, count 0 2006.189.07:49:30.65#ibcon#enter sib2, iclass 27, count 0 2006.189.07:49:30.65#ibcon#flushed, iclass 27, count 0 2006.189.07:49:30.65#ibcon#about to write, iclass 27, count 0 2006.189.07:49:30.65#ibcon#wrote, iclass 27, count 0 2006.189.07:49:30.65#ibcon#about to read 3, iclass 27, count 0 2006.189.07:49:30.67#ibcon#read 3, iclass 27, count 0 2006.189.07:49:30.67#ibcon#about to read 4, iclass 27, count 0 2006.189.07:49:30.67#ibcon#read 4, iclass 27, count 0 2006.189.07:49:30.67#ibcon#about to read 5, iclass 27, count 0 2006.189.07:49:30.67#ibcon#read 5, iclass 27, count 0 2006.189.07:49:30.67#ibcon#about to read 6, iclass 27, count 0 2006.189.07:49:30.67#ibcon#read 6, iclass 27, count 0 2006.189.07:49:30.67#ibcon#end of sib2, iclass 27, count 0 2006.189.07:49:30.67#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:49:30.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:49:30.67#ibcon#[25=USB\r\n] 2006.189.07:49:30.67#ibcon#*before write, iclass 27, count 0 2006.189.07:49:30.67#ibcon#enter sib2, iclass 27, count 0 2006.189.07:49:30.67#ibcon#flushed, iclass 27, count 0 2006.189.07:49:30.67#ibcon#about to write, iclass 27, count 0 2006.189.07:49:30.67#ibcon#wrote, iclass 27, count 0 2006.189.07:49:30.67#ibcon#about to read 3, iclass 27, count 0 2006.189.07:49:30.70#ibcon#read 3, iclass 27, count 0 2006.189.07:49:30.70#ibcon#about to read 4, iclass 27, count 0 2006.189.07:49:30.70#ibcon#read 4, iclass 27, count 0 2006.189.07:49:30.70#ibcon#about to read 5, iclass 27, count 0 2006.189.07:49:30.70#ibcon#read 5, iclass 27, count 0 2006.189.07:49:30.70#ibcon#about to read 6, iclass 27, count 0 2006.189.07:49:30.70#ibcon#read 6, iclass 27, count 0 2006.189.07:49:30.70#ibcon#end of sib2, iclass 27, count 0 2006.189.07:49:30.70#ibcon#*after write, iclass 27, count 0 2006.189.07:49:30.70#ibcon#*before return 0, iclass 27, count 0 2006.189.07:49:30.70#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:49:30.70#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:49:30.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:49:30.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:49:30.70$vc4f8/vblo=1,632.99 2006.189.07:49:30.70#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:49:30.70#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:49:30.70#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:30.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:49:30.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:49:30.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:49:30.70#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:49:30.70#ibcon#first serial, iclass 29, count 0 2006.189.07:49:30.70#ibcon#enter sib2, iclass 29, count 0 2006.189.07:49:30.70#ibcon#flushed, iclass 29, count 0 2006.189.07:49:30.70#ibcon#about to write, iclass 29, count 0 2006.189.07:49:30.70#ibcon#wrote, iclass 29, count 0 2006.189.07:49:30.70#ibcon#about to read 3, iclass 29, count 0 2006.189.07:49:30.72#ibcon#read 3, iclass 29, count 0 2006.189.07:49:30.72#ibcon#about to read 4, iclass 29, count 0 2006.189.07:49:30.72#ibcon#read 4, iclass 29, count 0 2006.189.07:49:30.72#ibcon#about to read 5, iclass 29, count 0 2006.189.07:49:30.72#ibcon#read 5, iclass 29, count 0 2006.189.07:49:30.72#ibcon#about to read 6, iclass 29, count 0 2006.189.07:49:30.72#ibcon#read 6, iclass 29, count 0 2006.189.07:49:30.72#ibcon#end of sib2, iclass 29, count 0 2006.189.07:49:30.72#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:49:30.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:49:30.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:49:30.72#ibcon#*before write, iclass 29, count 0 2006.189.07:49:30.72#ibcon#enter sib2, iclass 29, count 0 2006.189.07:49:30.72#ibcon#flushed, iclass 29, count 0 2006.189.07:49:30.72#ibcon#about to write, iclass 29, count 0 2006.189.07:49:30.72#ibcon#wrote, iclass 29, count 0 2006.189.07:49:30.72#ibcon#about to read 3, iclass 29, count 0 2006.189.07:49:30.76#ibcon#read 3, iclass 29, count 0 2006.189.07:49:30.76#ibcon#about to read 4, iclass 29, count 0 2006.189.07:49:30.76#ibcon#read 4, iclass 29, count 0 2006.189.07:49:30.76#ibcon#about to read 5, iclass 29, count 0 2006.189.07:49:30.76#ibcon#read 5, iclass 29, count 0 2006.189.07:49:30.76#ibcon#about to read 6, iclass 29, count 0 2006.189.07:49:30.76#ibcon#read 6, iclass 29, count 0 2006.189.07:49:30.76#ibcon#end of sib2, iclass 29, count 0 2006.189.07:49:30.76#ibcon#*after write, iclass 29, count 0 2006.189.07:49:30.76#ibcon#*before return 0, iclass 29, count 0 2006.189.07:49:30.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:49:30.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:49:30.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:49:30.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:49:30.76$vc4f8/vb=1,4 2006.189.07:49:30.76#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.07:49:30.76#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.07:49:30.76#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:30.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:49:30.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:49:30.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:49:30.76#ibcon#enter wrdev, iclass 31, count 2 2006.189.07:49:30.76#ibcon#first serial, iclass 31, count 2 2006.189.07:49:30.76#ibcon#enter sib2, iclass 31, count 2 2006.189.07:49:30.76#ibcon#flushed, iclass 31, count 2 2006.189.07:49:30.76#ibcon#about to write, iclass 31, count 2 2006.189.07:49:30.76#ibcon#wrote, iclass 31, count 2 2006.189.07:49:30.76#ibcon#about to read 3, iclass 31, count 2 2006.189.07:49:30.78#ibcon#read 3, iclass 31, count 2 2006.189.07:49:30.78#ibcon#about to read 4, iclass 31, count 2 2006.189.07:49:30.78#ibcon#read 4, iclass 31, count 2 2006.189.07:49:30.78#ibcon#about to read 5, iclass 31, count 2 2006.189.07:49:30.78#ibcon#read 5, iclass 31, count 2 2006.189.07:49:30.78#ibcon#about to read 6, iclass 31, count 2 2006.189.07:49:30.78#ibcon#read 6, iclass 31, count 2 2006.189.07:49:30.78#ibcon#end of sib2, iclass 31, count 2 2006.189.07:49:30.78#ibcon#*mode == 0, iclass 31, count 2 2006.189.07:49:30.78#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.07:49:30.78#ibcon#[27=AT01-04\r\n] 2006.189.07:49:30.78#ibcon#*before write, iclass 31, count 2 2006.189.07:49:30.78#ibcon#enter sib2, iclass 31, count 2 2006.189.07:49:30.78#ibcon#flushed, iclass 31, count 2 2006.189.07:49:30.78#ibcon#about to write, iclass 31, count 2 2006.189.07:49:30.78#ibcon#wrote, iclass 31, count 2 2006.189.07:49:30.78#ibcon#about to read 3, iclass 31, count 2 2006.189.07:49:30.81#ibcon#read 3, iclass 31, count 2 2006.189.07:49:30.81#ibcon#about to read 4, iclass 31, count 2 2006.189.07:49:30.81#ibcon#read 4, iclass 31, count 2 2006.189.07:49:30.81#ibcon#about to read 5, iclass 31, count 2 2006.189.07:49:30.81#ibcon#read 5, iclass 31, count 2 2006.189.07:49:30.81#ibcon#about to read 6, iclass 31, count 2 2006.189.07:49:30.81#ibcon#read 6, iclass 31, count 2 2006.189.07:49:30.81#ibcon#end of sib2, iclass 31, count 2 2006.189.07:49:30.81#ibcon#*after write, iclass 31, count 2 2006.189.07:49:30.81#ibcon#*before return 0, iclass 31, count 2 2006.189.07:49:30.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:49:30.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:49:30.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.07:49:30.81#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:30.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:49:30.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:49:30.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:49:30.93#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:49:30.93#ibcon#first serial, iclass 31, count 0 2006.189.07:49:30.93#ibcon#enter sib2, iclass 31, count 0 2006.189.07:49:30.93#ibcon#flushed, iclass 31, count 0 2006.189.07:49:30.93#ibcon#about to write, iclass 31, count 0 2006.189.07:49:30.93#ibcon#wrote, iclass 31, count 0 2006.189.07:49:30.93#ibcon#about to read 3, iclass 31, count 0 2006.189.07:49:30.95#ibcon#read 3, iclass 31, count 0 2006.189.07:49:30.95#ibcon#about to read 4, iclass 31, count 0 2006.189.07:49:30.95#ibcon#read 4, iclass 31, count 0 2006.189.07:49:30.95#ibcon#about to read 5, iclass 31, count 0 2006.189.07:49:30.95#ibcon#read 5, iclass 31, count 0 2006.189.07:49:30.95#ibcon#about to read 6, iclass 31, count 0 2006.189.07:49:30.95#ibcon#read 6, iclass 31, count 0 2006.189.07:49:30.95#ibcon#end of sib2, iclass 31, count 0 2006.189.07:49:30.95#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:49:30.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:49:30.95#ibcon#[27=USB\r\n] 2006.189.07:49:30.95#ibcon#*before write, iclass 31, count 0 2006.189.07:49:30.95#ibcon#enter sib2, iclass 31, count 0 2006.189.07:49:30.95#ibcon#flushed, iclass 31, count 0 2006.189.07:49:30.95#ibcon#about to write, iclass 31, count 0 2006.189.07:49:30.95#ibcon#wrote, iclass 31, count 0 2006.189.07:49:30.95#ibcon#about to read 3, iclass 31, count 0 2006.189.07:49:30.98#ibcon#read 3, iclass 31, count 0 2006.189.07:49:30.98#ibcon#about to read 4, iclass 31, count 0 2006.189.07:49:30.98#ibcon#read 4, iclass 31, count 0 2006.189.07:49:30.98#ibcon#about to read 5, iclass 31, count 0 2006.189.07:49:30.98#ibcon#read 5, iclass 31, count 0 2006.189.07:49:30.98#ibcon#about to read 6, iclass 31, count 0 2006.189.07:49:30.98#ibcon#read 6, iclass 31, count 0 2006.189.07:49:30.98#ibcon#end of sib2, iclass 31, count 0 2006.189.07:49:30.98#ibcon#*after write, iclass 31, count 0 2006.189.07:49:30.98#ibcon#*before return 0, iclass 31, count 0 2006.189.07:49:30.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:49:30.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:49:30.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:49:30.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:49:30.98$vc4f8/vblo=2,640.99 2006.189.07:49:30.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:49:30.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:49:30.98#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:30.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:30.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:30.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:30.98#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:49:30.98#ibcon#first serial, iclass 33, count 0 2006.189.07:49:30.98#ibcon#enter sib2, iclass 33, count 0 2006.189.07:49:30.98#ibcon#flushed, iclass 33, count 0 2006.189.07:49:30.98#ibcon#about to write, iclass 33, count 0 2006.189.07:49:30.98#ibcon#wrote, iclass 33, count 0 2006.189.07:49:30.98#ibcon#about to read 3, iclass 33, count 0 2006.189.07:49:31.00#ibcon#read 3, iclass 33, count 0 2006.189.07:49:31.00#ibcon#about to read 4, iclass 33, count 0 2006.189.07:49:31.00#ibcon#read 4, iclass 33, count 0 2006.189.07:49:31.00#ibcon#about to read 5, iclass 33, count 0 2006.189.07:49:31.00#ibcon#read 5, iclass 33, count 0 2006.189.07:49:31.00#ibcon#about to read 6, iclass 33, count 0 2006.189.07:49:31.00#ibcon#read 6, iclass 33, count 0 2006.189.07:49:31.00#ibcon#end of sib2, iclass 33, count 0 2006.189.07:49:31.00#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:49:31.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:49:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:49:31.00#ibcon#*before write, iclass 33, count 0 2006.189.07:49:31.00#ibcon#enter sib2, iclass 33, count 0 2006.189.07:49:31.00#ibcon#flushed, iclass 33, count 0 2006.189.07:49:31.00#ibcon#about to write, iclass 33, count 0 2006.189.07:49:31.00#ibcon#wrote, iclass 33, count 0 2006.189.07:49:31.00#ibcon#about to read 3, iclass 33, count 0 2006.189.07:49:31.04#ibcon#read 3, iclass 33, count 0 2006.189.07:49:31.04#ibcon#about to read 4, iclass 33, count 0 2006.189.07:49:31.04#ibcon#read 4, iclass 33, count 0 2006.189.07:49:31.04#ibcon#about to read 5, iclass 33, count 0 2006.189.07:49:31.04#ibcon#read 5, iclass 33, count 0 2006.189.07:49:31.04#ibcon#about to read 6, iclass 33, count 0 2006.189.07:49:31.04#ibcon#read 6, iclass 33, count 0 2006.189.07:49:31.04#ibcon#end of sib2, iclass 33, count 0 2006.189.07:49:31.04#ibcon#*after write, iclass 33, count 0 2006.189.07:49:31.04#ibcon#*before return 0, iclass 33, count 0 2006.189.07:49:31.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:31.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:49:31.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:49:31.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:49:31.04$vc4f8/vb=2,4 2006.189.07:49:31.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:49:31.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:49:31.04#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:31.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:31.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:31.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:31.10#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:49:31.10#ibcon#first serial, iclass 35, count 2 2006.189.07:49:31.10#ibcon#enter sib2, iclass 35, count 2 2006.189.07:49:31.10#ibcon#flushed, iclass 35, count 2 2006.189.07:49:31.10#ibcon#about to write, iclass 35, count 2 2006.189.07:49:31.10#ibcon#wrote, iclass 35, count 2 2006.189.07:49:31.10#ibcon#about to read 3, iclass 35, count 2 2006.189.07:49:31.12#ibcon#read 3, iclass 35, count 2 2006.189.07:49:31.12#ibcon#about to read 4, iclass 35, count 2 2006.189.07:49:31.12#ibcon#read 4, iclass 35, count 2 2006.189.07:49:31.12#ibcon#about to read 5, iclass 35, count 2 2006.189.07:49:31.12#ibcon#read 5, iclass 35, count 2 2006.189.07:49:31.12#ibcon#about to read 6, iclass 35, count 2 2006.189.07:49:31.12#ibcon#read 6, iclass 35, count 2 2006.189.07:49:31.12#ibcon#end of sib2, iclass 35, count 2 2006.189.07:49:31.12#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:49:31.12#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:49:31.12#ibcon#[27=AT02-04\r\n] 2006.189.07:49:31.12#ibcon#*before write, iclass 35, count 2 2006.189.07:49:31.12#ibcon#enter sib2, iclass 35, count 2 2006.189.07:49:31.12#ibcon#flushed, iclass 35, count 2 2006.189.07:49:31.12#ibcon#about to write, iclass 35, count 2 2006.189.07:49:31.12#ibcon#wrote, iclass 35, count 2 2006.189.07:49:31.12#ibcon#about to read 3, iclass 35, count 2 2006.189.07:49:31.15#ibcon#read 3, iclass 35, count 2 2006.189.07:49:31.15#ibcon#about to read 4, iclass 35, count 2 2006.189.07:49:31.15#ibcon#read 4, iclass 35, count 2 2006.189.07:49:31.15#ibcon#about to read 5, iclass 35, count 2 2006.189.07:49:31.15#ibcon#read 5, iclass 35, count 2 2006.189.07:49:31.15#ibcon#about to read 6, iclass 35, count 2 2006.189.07:49:31.15#ibcon#read 6, iclass 35, count 2 2006.189.07:49:31.15#ibcon#end of sib2, iclass 35, count 2 2006.189.07:49:31.15#ibcon#*after write, iclass 35, count 2 2006.189.07:49:31.15#ibcon#*before return 0, iclass 35, count 2 2006.189.07:49:31.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:31.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:49:31.15#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:49:31.15#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:31.15#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:31.27#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:31.27#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:31.27#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:49:31.27#ibcon#first serial, iclass 35, count 0 2006.189.07:49:31.27#ibcon#enter sib2, iclass 35, count 0 2006.189.07:49:31.27#ibcon#flushed, iclass 35, count 0 2006.189.07:49:31.27#ibcon#about to write, iclass 35, count 0 2006.189.07:49:31.27#ibcon#wrote, iclass 35, count 0 2006.189.07:49:31.27#ibcon#about to read 3, iclass 35, count 0 2006.189.07:49:31.29#ibcon#read 3, iclass 35, count 0 2006.189.07:49:31.29#ibcon#about to read 4, iclass 35, count 0 2006.189.07:49:31.29#ibcon#read 4, iclass 35, count 0 2006.189.07:49:31.29#ibcon#about to read 5, iclass 35, count 0 2006.189.07:49:31.29#ibcon#read 5, iclass 35, count 0 2006.189.07:49:31.29#ibcon#about to read 6, iclass 35, count 0 2006.189.07:49:31.29#ibcon#read 6, iclass 35, count 0 2006.189.07:49:31.29#ibcon#end of sib2, iclass 35, count 0 2006.189.07:49:31.29#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:49:31.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:49:31.29#ibcon#[27=USB\r\n] 2006.189.07:49:31.29#ibcon#*before write, iclass 35, count 0 2006.189.07:49:31.29#ibcon#enter sib2, iclass 35, count 0 2006.189.07:49:31.29#ibcon#flushed, iclass 35, count 0 2006.189.07:49:31.29#ibcon#about to write, iclass 35, count 0 2006.189.07:49:31.29#ibcon#wrote, iclass 35, count 0 2006.189.07:49:31.29#ibcon#about to read 3, iclass 35, count 0 2006.189.07:49:31.32#ibcon#read 3, iclass 35, count 0 2006.189.07:49:31.32#ibcon#about to read 4, iclass 35, count 0 2006.189.07:49:31.32#ibcon#read 4, iclass 35, count 0 2006.189.07:49:31.32#ibcon#about to read 5, iclass 35, count 0 2006.189.07:49:31.32#ibcon#read 5, iclass 35, count 0 2006.189.07:49:31.32#ibcon#about to read 6, iclass 35, count 0 2006.189.07:49:31.32#ibcon#read 6, iclass 35, count 0 2006.189.07:49:31.32#ibcon#end of sib2, iclass 35, count 0 2006.189.07:49:31.32#ibcon#*after write, iclass 35, count 0 2006.189.07:49:31.32#ibcon#*before return 0, iclass 35, count 0 2006.189.07:49:31.32#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:31.32#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:49:31.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:49:31.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:49:31.32$vc4f8/vblo=3,656.99 2006.189.07:49:31.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:49:31.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:49:31.32#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:31.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:31.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:31.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:31.32#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:49:31.32#ibcon#first serial, iclass 37, count 0 2006.189.07:49:31.32#ibcon#enter sib2, iclass 37, count 0 2006.189.07:49:31.32#ibcon#flushed, iclass 37, count 0 2006.189.07:49:31.32#ibcon#about to write, iclass 37, count 0 2006.189.07:49:31.32#ibcon#wrote, iclass 37, count 0 2006.189.07:49:31.32#ibcon#about to read 3, iclass 37, count 0 2006.189.07:49:31.34#ibcon#read 3, iclass 37, count 0 2006.189.07:49:31.34#ibcon#about to read 4, iclass 37, count 0 2006.189.07:49:31.34#ibcon#read 4, iclass 37, count 0 2006.189.07:49:31.34#ibcon#about to read 5, iclass 37, count 0 2006.189.07:49:31.34#ibcon#read 5, iclass 37, count 0 2006.189.07:49:31.34#ibcon#about to read 6, iclass 37, count 0 2006.189.07:49:31.34#ibcon#read 6, iclass 37, count 0 2006.189.07:49:31.34#ibcon#end of sib2, iclass 37, count 0 2006.189.07:49:31.34#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:49:31.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:49:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:49:31.34#ibcon#*before write, iclass 37, count 0 2006.189.07:49:31.34#ibcon#enter sib2, iclass 37, count 0 2006.189.07:49:31.34#ibcon#flushed, iclass 37, count 0 2006.189.07:49:31.34#ibcon#about to write, iclass 37, count 0 2006.189.07:49:31.34#ibcon#wrote, iclass 37, count 0 2006.189.07:49:31.34#ibcon#about to read 3, iclass 37, count 0 2006.189.07:49:31.38#ibcon#read 3, iclass 37, count 0 2006.189.07:49:31.38#ibcon#about to read 4, iclass 37, count 0 2006.189.07:49:31.38#ibcon#read 4, iclass 37, count 0 2006.189.07:49:31.38#ibcon#about to read 5, iclass 37, count 0 2006.189.07:49:31.38#ibcon#read 5, iclass 37, count 0 2006.189.07:49:31.38#ibcon#about to read 6, iclass 37, count 0 2006.189.07:49:31.38#ibcon#read 6, iclass 37, count 0 2006.189.07:49:31.38#ibcon#end of sib2, iclass 37, count 0 2006.189.07:49:31.38#ibcon#*after write, iclass 37, count 0 2006.189.07:49:31.38#ibcon#*before return 0, iclass 37, count 0 2006.189.07:49:31.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:31.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:49:31.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:49:31.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:49:31.38$vc4f8/vb=3,4 2006.189.07:49:31.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:49:31.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:49:31.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:31.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:31.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:31.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:31.44#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:49:31.44#ibcon#first serial, iclass 39, count 2 2006.189.07:49:31.44#ibcon#enter sib2, iclass 39, count 2 2006.189.07:49:31.44#ibcon#flushed, iclass 39, count 2 2006.189.07:49:31.44#ibcon#about to write, iclass 39, count 2 2006.189.07:49:31.44#ibcon#wrote, iclass 39, count 2 2006.189.07:49:31.44#ibcon#about to read 3, iclass 39, count 2 2006.189.07:49:31.46#ibcon#read 3, iclass 39, count 2 2006.189.07:49:31.46#ibcon#about to read 4, iclass 39, count 2 2006.189.07:49:31.46#ibcon#read 4, iclass 39, count 2 2006.189.07:49:31.46#ibcon#about to read 5, iclass 39, count 2 2006.189.07:49:31.46#ibcon#read 5, iclass 39, count 2 2006.189.07:49:31.46#ibcon#about to read 6, iclass 39, count 2 2006.189.07:49:31.46#ibcon#read 6, iclass 39, count 2 2006.189.07:49:31.46#ibcon#end of sib2, iclass 39, count 2 2006.189.07:49:31.46#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:49:31.46#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:49:31.46#ibcon#[27=AT03-04\r\n] 2006.189.07:49:31.46#ibcon#*before write, iclass 39, count 2 2006.189.07:49:31.46#ibcon#enter sib2, iclass 39, count 2 2006.189.07:49:31.46#ibcon#flushed, iclass 39, count 2 2006.189.07:49:31.46#ibcon#about to write, iclass 39, count 2 2006.189.07:49:31.46#ibcon#wrote, iclass 39, count 2 2006.189.07:49:31.46#ibcon#about to read 3, iclass 39, count 2 2006.189.07:49:31.49#ibcon#read 3, iclass 39, count 2 2006.189.07:49:31.49#ibcon#about to read 4, iclass 39, count 2 2006.189.07:49:31.49#ibcon#read 4, iclass 39, count 2 2006.189.07:49:31.49#ibcon#about to read 5, iclass 39, count 2 2006.189.07:49:31.49#ibcon#read 5, iclass 39, count 2 2006.189.07:49:31.49#ibcon#about to read 6, iclass 39, count 2 2006.189.07:49:31.49#ibcon#read 6, iclass 39, count 2 2006.189.07:49:31.49#ibcon#end of sib2, iclass 39, count 2 2006.189.07:49:31.49#ibcon#*after write, iclass 39, count 2 2006.189.07:49:31.49#ibcon#*before return 0, iclass 39, count 2 2006.189.07:49:31.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:31.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:49:31.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:49:31.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:31.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:31.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:31.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:31.61#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:49:31.61#ibcon#first serial, iclass 39, count 0 2006.189.07:49:31.61#ibcon#enter sib2, iclass 39, count 0 2006.189.07:49:31.61#ibcon#flushed, iclass 39, count 0 2006.189.07:49:31.61#ibcon#about to write, iclass 39, count 0 2006.189.07:49:31.61#ibcon#wrote, iclass 39, count 0 2006.189.07:49:31.61#ibcon#about to read 3, iclass 39, count 0 2006.189.07:49:31.63#ibcon#read 3, iclass 39, count 0 2006.189.07:49:31.63#ibcon#about to read 4, iclass 39, count 0 2006.189.07:49:31.63#ibcon#read 4, iclass 39, count 0 2006.189.07:49:31.63#ibcon#about to read 5, iclass 39, count 0 2006.189.07:49:31.63#ibcon#read 5, iclass 39, count 0 2006.189.07:49:31.63#ibcon#about to read 6, iclass 39, count 0 2006.189.07:49:31.63#ibcon#read 6, iclass 39, count 0 2006.189.07:49:31.63#ibcon#end of sib2, iclass 39, count 0 2006.189.07:49:31.63#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:49:31.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:49:31.63#ibcon#[27=USB\r\n] 2006.189.07:49:31.63#ibcon#*before write, iclass 39, count 0 2006.189.07:49:31.63#ibcon#enter sib2, iclass 39, count 0 2006.189.07:49:31.63#ibcon#flushed, iclass 39, count 0 2006.189.07:49:31.63#ibcon#about to write, iclass 39, count 0 2006.189.07:49:31.63#ibcon#wrote, iclass 39, count 0 2006.189.07:49:31.63#ibcon#about to read 3, iclass 39, count 0 2006.189.07:49:31.66#ibcon#read 3, iclass 39, count 0 2006.189.07:49:31.66#ibcon#about to read 4, iclass 39, count 0 2006.189.07:49:31.66#ibcon#read 4, iclass 39, count 0 2006.189.07:49:31.66#ibcon#about to read 5, iclass 39, count 0 2006.189.07:49:31.66#ibcon#read 5, iclass 39, count 0 2006.189.07:49:31.66#ibcon#about to read 6, iclass 39, count 0 2006.189.07:49:31.66#ibcon#read 6, iclass 39, count 0 2006.189.07:49:31.66#ibcon#end of sib2, iclass 39, count 0 2006.189.07:49:31.66#ibcon#*after write, iclass 39, count 0 2006.189.07:49:31.66#ibcon#*before return 0, iclass 39, count 0 2006.189.07:49:31.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:31.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:49:31.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:49:31.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:49:31.66$vc4f8/vblo=4,712.99 2006.189.07:49:31.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:49:31.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:49:31.66#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:31.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:31.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:31.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:31.66#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:49:31.66#ibcon#first serial, iclass 3, count 0 2006.189.07:49:31.66#ibcon#enter sib2, iclass 3, count 0 2006.189.07:49:31.66#ibcon#flushed, iclass 3, count 0 2006.189.07:49:31.66#ibcon#about to write, iclass 3, count 0 2006.189.07:49:31.66#ibcon#wrote, iclass 3, count 0 2006.189.07:49:31.66#ibcon#about to read 3, iclass 3, count 0 2006.189.07:49:31.68#ibcon#read 3, iclass 3, count 0 2006.189.07:49:31.68#ibcon#about to read 4, iclass 3, count 0 2006.189.07:49:31.68#ibcon#read 4, iclass 3, count 0 2006.189.07:49:31.68#ibcon#about to read 5, iclass 3, count 0 2006.189.07:49:31.68#ibcon#read 5, iclass 3, count 0 2006.189.07:49:31.68#ibcon#about to read 6, iclass 3, count 0 2006.189.07:49:31.68#ibcon#read 6, iclass 3, count 0 2006.189.07:49:31.68#ibcon#end of sib2, iclass 3, count 0 2006.189.07:49:31.68#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:49:31.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:49:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:49:31.68#ibcon#*before write, iclass 3, count 0 2006.189.07:49:31.68#ibcon#enter sib2, iclass 3, count 0 2006.189.07:49:31.68#ibcon#flushed, iclass 3, count 0 2006.189.07:49:31.68#ibcon#about to write, iclass 3, count 0 2006.189.07:49:31.68#ibcon#wrote, iclass 3, count 0 2006.189.07:49:31.68#ibcon#about to read 3, iclass 3, count 0 2006.189.07:49:31.72#ibcon#read 3, iclass 3, count 0 2006.189.07:49:31.72#ibcon#about to read 4, iclass 3, count 0 2006.189.07:49:31.72#ibcon#read 4, iclass 3, count 0 2006.189.07:49:31.72#ibcon#about to read 5, iclass 3, count 0 2006.189.07:49:31.72#ibcon#read 5, iclass 3, count 0 2006.189.07:49:31.72#ibcon#about to read 6, iclass 3, count 0 2006.189.07:49:31.72#ibcon#read 6, iclass 3, count 0 2006.189.07:49:31.72#ibcon#end of sib2, iclass 3, count 0 2006.189.07:49:31.72#ibcon#*after write, iclass 3, count 0 2006.189.07:49:31.72#ibcon#*before return 0, iclass 3, count 0 2006.189.07:49:31.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:31.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:49:31.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:49:31.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:49:31.72$vc4f8/vb=4,4 2006.189.07:49:31.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:49:31.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:49:31.72#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:31.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:31.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:31.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:31.78#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:49:31.78#ibcon#first serial, iclass 5, count 2 2006.189.07:49:31.78#ibcon#enter sib2, iclass 5, count 2 2006.189.07:49:31.78#ibcon#flushed, iclass 5, count 2 2006.189.07:49:31.78#ibcon#about to write, iclass 5, count 2 2006.189.07:49:31.78#ibcon#wrote, iclass 5, count 2 2006.189.07:49:31.78#ibcon#about to read 3, iclass 5, count 2 2006.189.07:49:31.80#ibcon#read 3, iclass 5, count 2 2006.189.07:49:31.80#ibcon#about to read 4, iclass 5, count 2 2006.189.07:49:31.80#ibcon#read 4, iclass 5, count 2 2006.189.07:49:31.80#ibcon#about to read 5, iclass 5, count 2 2006.189.07:49:31.80#ibcon#read 5, iclass 5, count 2 2006.189.07:49:31.80#ibcon#about to read 6, iclass 5, count 2 2006.189.07:49:31.80#ibcon#read 6, iclass 5, count 2 2006.189.07:49:31.80#ibcon#end of sib2, iclass 5, count 2 2006.189.07:49:31.80#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:49:31.80#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:49:31.80#ibcon#[27=AT04-04\r\n] 2006.189.07:49:31.80#ibcon#*before write, iclass 5, count 2 2006.189.07:49:31.80#ibcon#enter sib2, iclass 5, count 2 2006.189.07:49:31.80#ibcon#flushed, iclass 5, count 2 2006.189.07:49:31.80#ibcon#about to write, iclass 5, count 2 2006.189.07:49:31.80#ibcon#wrote, iclass 5, count 2 2006.189.07:49:31.80#ibcon#about to read 3, iclass 5, count 2 2006.189.07:49:31.83#ibcon#read 3, iclass 5, count 2 2006.189.07:49:31.83#ibcon#about to read 4, iclass 5, count 2 2006.189.07:49:31.83#ibcon#read 4, iclass 5, count 2 2006.189.07:49:31.83#ibcon#about to read 5, iclass 5, count 2 2006.189.07:49:31.83#ibcon#read 5, iclass 5, count 2 2006.189.07:49:31.83#ibcon#about to read 6, iclass 5, count 2 2006.189.07:49:31.83#ibcon#read 6, iclass 5, count 2 2006.189.07:49:31.83#ibcon#end of sib2, iclass 5, count 2 2006.189.07:49:31.83#ibcon#*after write, iclass 5, count 2 2006.189.07:49:31.83#ibcon#*before return 0, iclass 5, count 2 2006.189.07:49:31.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:31.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:49:31.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:49:31.83#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:31.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:31.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:31.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:31.95#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:49:31.95#ibcon#first serial, iclass 5, count 0 2006.189.07:49:31.95#ibcon#enter sib2, iclass 5, count 0 2006.189.07:49:31.95#ibcon#flushed, iclass 5, count 0 2006.189.07:49:31.95#ibcon#about to write, iclass 5, count 0 2006.189.07:49:31.95#ibcon#wrote, iclass 5, count 0 2006.189.07:49:31.95#ibcon#about to read 3, iclass 5, count 0 2006.189.07:49:31.97#ibcon#read 3, iclass 5, count 0 2006.189.07:49:31.97#ibcon#about to read 4, iclass 5, count 0 2006.189.07:49:31.97#ibcon#read 4, iclass 5, count 0 2006.189.07:49:31.97#ibcon#about to read 5, iclass 5, count 0 2006.189.07:49:31.97#ibcon#read 5, iclass 5, count 0 2006.189.07:49:31.97#ibcon#about to read 6, iclass 5, count 0 2006.189.07:49:31.97#ibcon#read 6, iclass 5, count 0 2006.189.07:49:31.97#ibcon#end of sib2, iclass 5, count 0 2006.189.07:49:31.97#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:49:31.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:49:31.97#ibcon#[27=USB\r\n] 2006.189.07:49:31.97#ibcon#*before write, iclass 5, count 0 2006.189.07:49:31.97#ibcon#enter sib2, iclass 5, count 0 2006.189.07:49:31.97#ibcon#flushed, iclass 5, count 0 2006.189.07:49:31.97#ibcon#about to write, iclass 5, count 0 2006.189.07:49:31.97#ibcon#wrote, iclass 5, count 0 2006.189.07:49:31.97#ibcon#about to read 3, iclass 5, count 0 2006.189.07:49:32.00#ibcon#read 3, iclass 5, count 0 2006.189.07:49:32.00#ibcon#about to read 4, iclass 5, count 0 2006.189.07:49:32.00#ibcon#read 4, iclass 5, count 0 2006.189.07:49:32.00#ibcon#about to read 5, iclass 5, count 0 2006.189.07:49:32.00#ibcon#read 5, iclass 5, count 0 2006.189.07:49:32.00#ibcon#about to read 6, iclass 5, count 0 2006.189.07:49:32.00#ibcon#read 6, iclass 5, count 0 2006.189.07:49:32.00#ibcon#end of sib2, iclass 5, count 0 2006.189.07:49:32.00#ibcon#*after write, iclass 5, count 0 2006.189.07:49:32.00#ibcon#*before return 0, iclass 5, count 0 2006.189.07:49:32.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:32.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:49:32.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:49:32.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:49:32.00$vc4f8/vblo=5,744.99 2006.189.07:49:32.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:49:32.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:49:32.00#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:32.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:32.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:32.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:32.00#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:49:32.00#ibcon#first serial, iclass 7, count 0 2006.189.07:49:32.00#ibcon#enter sib2, iclass 7, count 0 2006.189.07:49:32.00#ibcon#flushed, iclass 7, count 0 2006.189.07:49:32.00#ibcon#about to write, iclass 7, count 0 2006.189.07:49:32.00#ibcon#wrote, iclass 7, count 0 2006.189.07:49:32.00#ibcon#about to read 3, iclass 7, count 0 2006.189.07:49:32.02#ibcon#read 3, iclass 7, count 0 2006.189.07:49:32.02#ibcon#about to read 4, iclass 7, count 0 2006.189.07:49:32.02#ibcon#read 4, iclass 7, count 0 2006.189.07:49:32.02#ibcon#about to read 5, iclass 7, count 0 2006.189.07:49:32.02#ibcon#read 5, iclass 7, count 0 2006.189.07:49:32.02#ibcon#about to read 6, iclass 7, count 0 2006.189.07:49:32.02#ibcon#read 6, iclass 7, count 0 2006.189.07:49:32.02#ibcon#end of sib2, iclass 7, count 0 2006.189.07:49:32.02#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:49:32.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:49:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:49:32.02#ibcon#*before write, iclass 7, count 0 2006.189.07:49:32.02#ibcon#enter sib2, iclass 7, count 0 2006.189.07:49:32.02#ibcon#flushed, iclass 7, count 0 2006.189.07:49:32.02#ibcon#about to write, iclass 7, count 0 2006.189.07:49:32.02#ibcon#wrote, iclass 7, count 0 2006.189.07:49:32.02#ibcon#about to read 3, iclass 7, count 0 2006.189.07:49:32.06#ibcon#read 3, iclass 7, count 0 2006.189.07:49:32.06#ibcon#about to read 4, iclass 7, count 0 2006.189.07:49:32.06#ibcon#read 4, iclass 7, count 0 2006.189.07:49:32.06#ibcon#about to read 5, iclass 7, count 0 2006.189.07:49:32.06#ibcon#read 5, iclass 7, count 0 2006.189.07:49:32.06#ibcon#about to read 6, iclass 7, count 0 2006.189.07:49:32.06#ibcon#read 6, iclass 7, count 0 2006.189.07:49:32.06#ibcon#end of sib2, iclass 7, count 0 2006.189.07:49:32.06#ibcon#*after write, iclass 7, count 0 2006.189.07:49:32.06#ibcon#*before return 0, iclass 7, count 0 2006.189.07:49:32.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:32.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:49:32.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:49:32.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:49:32.06$vc4f8/vb=5,4 2006.189.07:49:32.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:49:32.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:49:32.06#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:32.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:32.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:32.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:32.12#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:49:32.12#ibcon#first serial, iclass 11, count 2 2006.189.07:49:32.12#ibcon#enter sib2, iclass 11, count 2 2006.189.07:49:32.12#ibcon#flushed, iclass 11, count 2 2006.189.07:49:32.12#ibcon#about to write, iclass 11, count 2 2006.189.07:49:32.12#ibcon#wrote, iclass 11, count 2 2006.189.07:49:32.12#ibcon#about to read 3, iclass 11, count 2 2006.189.07:49:32.14#ibcon#read 3, iclass 11, count 2 2006.189.07:49:32.14#ibcon#about to read 4, iclass 11, count 2 2006.189.07:49:32.14#ibcon#read 4, iclass 11, count 2 2006.189.07:49:32.14#ibcon#about to read 5, iclass 11, count 2 2006.189.07:49:32.14#ibcon#read 5, iclass 11, count 2 2006.189.07:49:32.14#ibcon#about to read 6, iclass 11, count 2 2006.189.07:49:32.14#ibcon#read 6, iclass 11, count 2 2006.189.07:49:32.14#ibcon#end of sib2, iclass 11, count 2 2006.189.07:49:32.14#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:49:32.14#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:49:32.14#ibcon#[27=AT05-04\r\n] 2006.189.07:49:32.14#ibcon#*before write, iclass 11, count 2 2006.189.07:49:32.14#ibcon#enter sib2, iclass 11, count 2 2006.189.07:49:32.14#ibcon#flushed, iclass 11, count 2 2006.189.07:49:32.14#ibcon#about to write, iclass 11, count 2 2006.189.07:49:32.14#ibcon#wrote, iclass 11, count 2 2006.189.07:49:32.14#ibcon#about to read 3, iclass 11, count 2 2006.189.07:49:32.17#ibcon#read 3, iclass 11, count 2 2006.189.07:49:32.17#ibcon#about to read 4, iclass 11, count 2 2006.189.07:49:32.17#ibcon#read 4, iclass 11, count 2 2006.189.07:49:32.17#ibcon#about to read 5, iclass 11, count 2 2006.189.07:49:32.17#ibcon#read 5, iclass 11, count 2 2006.189.07:49:32.17#ibcon#about to read 6, iclass 11, count 2 2006.189.07:49:32.17#ibcon#read 6, iclass 11, count 2 2006.189.07:49:32.17#ibcon#end of sib2, iclass 11, count 2 2006.189.07:49:32.17#ibcon#*after write, iclass 11, count 2 2006.189.07:49:32.17#ibcon#*before return 0, iclass 11, count 2 2006.189.07:49:32.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:32.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:49:32.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:49:32.17#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:32.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:32.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:32.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:32.29#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:49:32.29#ibcon#first serial, iclass 11, count 0 2006.189.07:49:32.29#ibcon#enter sib2, iclass 11, count 0 2006.189.07:49:32.29#ibcon#flushed, iclass 11, count 0 2006.189.07:49:32.29#ibcon#about to write, iclass 11, count 0 2006.189.07:49:32.29#ibcon#wrote, iclass 11, count 0 2006.189.07:49:32.29#ibcon#about to read 3, iclass 11, count 0 2006.189.07:49:32.31#ibcon#read 3, iclass 11, count 0 2006.189.07:49:32.31#ibcon#about to read 4, iclass 11, count 0 2006.189.07:49:32.31#ibcon#read 4, iclass 11, count 0 2006.189.07:49:32.31#ibcon#about to read 5, iclass 11, count 0 2006.189.07:49:32.31#ibcon#read 5, iclass 11, count 0 2006.189.07:49:32.31#ibcon#about to read 6, iclass 11, count 0 2006.189.07:49:32.31#ibcon#read 6, iclass 11, count 0 2006.189.07:49:32.31#ibcon#end of sib2, iclass 11, count 0 2006.189.07:49:32.31#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:49:32.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:49:32.31#ibcon#[27=USB\r\n] 2006.189.07:49:32.31#ibcon#*before write, iclass 11, count 0 2006.189.07:49:32.31#ibcon#enter sib2, iclass 11, count 0 2006.189.07:49:32.31#ibcon#flushed, iclass 11, count 0 2006.189.07:49:32.31#ibcon#about to write, iclass 11, count 0 2006.189.07:49:32.31#ibcon#wrote, iclass 11, count 0 2006.189.07:49:32.31#ibcon#about to read 3, iclass 11, count 0 2006.189.07:49:32.34#ibcon#read 3, iclass 11, count 0 2006.189.07:49:32.34#ibcon#about to read 4, iclass 11, count 0 2006.189.07:49:32.34#ibcon#read 4, iclass 11, count 0 2006.189.07:49:32.34#ibcon#about to read 5, iclass 11, count 0 2006.189.07:49:32.34#ibcon#read 5, iclass 11, count 0 2006.189.07:49:32.34#ibcon#about to read 6, iclass 11, count 0 2006.189.07:49:32.34#ibcon#read 6, iclass 11, count 0 2006.189.07:49:32.34#ibcon#end of sib2, iclass 11, count 0 2006.189.07:49:32.34#ibcon#*after write, iclass 11, count 0 2006.189.07:49:32.34#ibcon#*before return 0, iclass 11, count 0 2006.189.07:49:32.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:32.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:49:32.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:49:32.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:49:32.34$vc4f8/vblo=6,752.99 2006.189.07:49:32.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.07:49:32.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.07:49:32.34#ibcon#ireg 17 cls_cnt 0 2006.189.07:49:32.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:32.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:32.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:32.34#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:49:32.34#ibcon#first serial, iclass 13, count 0 2006.189.07:49:32.34#ibcon#enter sib2, iclass 13, count 0 2006.189.07:49:32.34#ibcon#flushed, iclass 13, count 0 2006.189.07:49:32.34#ibcon#about to write, iclass 13, count 0 2006.189.07:49:32.34#ibcon#wrote, iclass 13, count 0 2006.189.07:49:32.34#ibcon#about to read 3, iclass 13, count 0 2006.189.07:49:32.36#ibcon#read 3, iclass 13, count 0 2006.189.07:49:32.36#ibcon#about to read 4, iclass 13, count 0 2006.189.07:49:32.36#ibcon#read 4, iclass 13, count 0 2006.189.07:49:32.36#ibcon#about to read 5, iclass 13, count 0 2006.189.07:49:32.36#ibcon#read 5, iclass 13, count 0 2006.189.07:49:32.36#ibcon#about to read 6, iclass 13, count 0 2006.189.07:49:32.36#ibcon#read 6, iclass 13, count 0 2006.189.07:49:32.36#ibcon#end of sib2, iclass 13, count 0 2006.189.07:49:32.36#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:49:32.36#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:49:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:49:32.36#ibcon#*before write, iclass 13, count 0 2006.189.07:49:32.36#ibcon#enter sib2, iclass 13, count 0 2006.189.07:49:32.36#ibcon#flushed, iclass 13, count 0 2006.189.07:49:32.36#ibcon#about to write, iclass 13, count 0 2006.189.07:49:32.36#ibcon#wrote, iclass 13, count 0 2006.189.07:49:32.36#ibcon#about to read 3, iclass 13, count 0 2006.189.07:49:32.40#ibcon#read 3, iclass 13, count 0 2006.189.07:49:32.40#ibcon#about to read 4, iclass 13, count 0 2006.189.07:49:32.40#ibcon#read 4, iclass 13, count 0 2006.189.07:49:32.40#ibcon#about to read 5, iclass 13, count 0 2006.189.07:49:32.40#ibcon#read 5, iclass 13, count 0 2006.189.07:49:32.40#ibcon#about to read 6, iclass 13, count 0 2006.189.07:49:32.40#ibcon#read 6, iclass 13, count 0 2006.189.07:49:32.40#ibcon#end of sib2, iclass 13, count 0 2006.189.07:49:32.40#ibcon#*after write, iclass 13, count 0 2006.189.07:49:32.40#ibcon#*before return 0, iclass 13, count 0 2006.189.07:49:32.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:32.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:49:32.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:49:32.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:49:32.40$vc4f8/vb=6,4 2006.189.07:49:32.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.07:49:32.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.07:49:32.40#ibcon#ireg 11 cls_cnt 2 2006.189.07:49:32.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:32.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:32.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:32.46#ibcon#enter wrdev, iclass 15, count 2 2006.189.07:49:32.46#ibcon#first serial, iclass 15, count 2 2006.189.07:49:32.46#ibcon#enter sib2, iclass 15, count 2 2006.189.07:49:32.46#ibcon#flushed, iclass 15, count 2 2006.189.07:49:32.46#ibcon#about to write, iclass 15, count 2 2006.189.07:49:32.46#ibcon#wrote, iclass 15, count 2 2006.189.07:49:32.46#ibcon#about to read 3, iclass 15, count 2 2006.189.07:49:32.48#ibcon#read 3, iclass 15, count 2 2006.189.07:49:32.48#ibcon#about to read 4, iclass 15, count 2 2006.189.07:49:32.48#ibcon#read 4, iclass 15, count 2 2006.189.07:49:32.48#ibcon#about to read 5, iclass 15, count 2 2006.189.07:49:32.48#ibcon#read 5, iclass 15, count 2 2006.189.07:49:32.48#ibcon#about to read 6, iclass 15, count 2 2006.189.07:49:32.48#ibcon#read 6, iclass 15, count 2 2006.189.07:49:32.48#ibcon#end of sib2, iclass 15, count 2 2006.189.07:49:32.48#ibcon#*mode == 0, iclass 15, count 2 2006.189.07:49:32.48#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.07:49:32.48#ibcon#[27=AT06-04\r\n] 2006.189.07:49:32.48#ibcon#*before write, iclass 15, count 2 2006.189.07:49:32.48#ibcon#enter sib2, iclass 15, count 2 2006.189.07:49:32.48#ibcon#flushed, iclass 15, count 2 2006.189.07:49:32.48#ibcon#about to write, iclass 15, count 2 2006.189.07:49:32.48#ibcon#wrote, iclass 15, count 2 2006.189.07:49:32.48#ibcon#about to read 3, iclass 15, count 2 2006.189.07:49:32.51#ibcon#read 3, iclass 15, count 2 2006.189.07:49:32.51#ibcon#about to read 4, iclass 15, count 2 2006.189.07:49:32.51#ibcon#read 4, iclass 15, count 2 2006.189.07:49:32.51#ibcon#about to read 5, iclass 15, count 2 2006.189.07:49:32.51#ibcon#read 5, iclass 15, count 2 2006.189.07:49:32.51#ibcon#about to read 6, iclass 15, count 2 2006.189.07:49:32.51#ibcon#read 6, iclass 15, count 2 2006.189.07:49:32.51#ibcon#end of sib2, iclass 15, count 2 2006.189.07:49:32.51#ibcon#*after write, iclass 15, count 2 2006.189.07:49:32.51#ibcon#*before return 0, iclass 15, count 2 2006.189.07:49:32.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:32.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:49:32.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.07:49:32.51#ibcon#ireg 7 cls_cnt 0 2006.189.07:49:32.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:32.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:32.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:32.63#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:49:32.63#ibcon#first serial, iclass 15, count 0 2006.189.07:49:32.63#ibcon#enter sib2, iclass 15, count 0 2006.189.07:49:32.63#ibcon#flushed, iclass 15, count 0 2006.189.07:49:32.63#ibcon#about to write, iclass 15, count 0 2006.189.07:49:32.63#ibcon#wrote, iclass 15, count 0 2006.189.07:49:32.63#ibcon#about to read 3, iclass 15, count 0 2006.189.07:49:32.65#ibcon#read 3, iclass 15, count 0 2006.189.07:49:32.65#ibcon#about to read 4, iclass 15, count 0 2006.189.07:49:32.65#ibcon#read 4, iclass 15, count 0 2006.189.07:49:32.65#ibcon#about to read 5, iclass 15, count 0 2006.189.07:49:32.65#ibcon#read 5, iclass 15, count 0 2006.189.07:49:32.65#ibcon#about to read 6, iclass 15, count 0 2006.189.07:49:32.65#ibcon#read 6, iclass 15, count 0 2006.189.07:49:32.65#ibcon#end of sib2, iclass 15, count 0 2006.189.07:49:32.65#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:49:32.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:49:32.65#ibcon#[27=USB\r\n] 2006.189.07:49:32.65#ibcon#*before write, iclass 15, count 0 2006.189.07:49:32.65#ibcon#enter sib2, iclass 15, count 0 2006.189.07:49:32.65#ibcon#flushed, iclass 15, count 0 2006.189.07:49:32.65#ibcon#about to write, iclass 15, count 0 2006.189.07:49:32.65#ibcon#wrote, iclass 15, count 0 2006.189.07:49:32.65#ibcon#about to read 3, iclass 15, count 0 2006.189.07:49:32.68#ibcon#read 3, iclass 15, count 0 2006.189.07:49:32.68#ibcon#about to read 4, iclass 15, count 0 2006.189.07:49:32.68#ibcon#read 4, iclass 15, count 0 2006.189.07:49:32.68#ibcon#about to read 5, iclass 15, count 0 2006.189.07:49:32.68#ibcon#read 5, iclass 15, count 0 2006.189.07:49:32.68#ibcon#about to read 6, iclass 15, count 0 2006.189.07:49:32.68#ibcon#read 6, iclass 15, count 0 2006.189.07:49:32.68#ibcon#end of sib2, iclass 15, count 0 2006.189.07:49:32.68#ibcon#*after write, iclass 15, count 0 2006.189.07:49:32.68#ibcon#*before return 0, iclass 15, count 0 2006.189.07:49:32.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:32.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:49:32.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:49:32.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:49:32.68$vc4f8/vabw=wide 2006.189.07:49:32.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:49:32.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:49:32.68#ibcon#ireg 8 cls_cnt 0 2006.189.07:49:32.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:32.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:32.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:32.68#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:49:32.68#ibcon#first serial, iclass 17, count 0 2006.189.07:49:32.68#ibcon#enter sib2, iclass 17, count 0 2006.189.07:49:32.68#ibcon#flushed, iclass 17, count 0 2006.189.07:49:32.68#ibcon#about to write, iclass 17, count 0 2006.189.07:49:32.68#ibcon#wrote, iclass 17, count 0 2006.189.07:49:32.68#ibcon#about to read 3, iclass 17, count 0 2006.189.07:49:32.70#ibcon#read 3, iclass 17, count 0 2006.189.07:49:32.70#ibcon#about to read 4, iclass 17, count 0 2006.189.07:49:32.70#ibcon#read 4, iclass 17, count 0 2006.189.07:49:32.70#ibcon#about to read 5, iclass 17, count 0 2006.189.07:49:32.70#ibcon#read 5, iclass 17, count 0 2006.189.07:49:32.70#ibcon#about to read 6, iclass 17, count 0 2006.189.07:49:32.70#ibcon#read 6, iclass 17, count 0 2006.189.07:49:32.70#ibcon#end of sib2, iclass 17, count 0 2006.189.07:49:32.70#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:49:32.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:49:32.70#ibcon#[25=BW32\r\n] 2006.189.07:49:32.70#ibcon#*before write, iclass 17, count 0 2006.189.07:49:32.70#ibcon#enter sib2, iclass 17, count 0 2006.189.07:49:32.70#ibcon#flushed, iclass 17, count 0 2006.189.07:49:32.70#ibcon#about to write, iclass 17, count 0 2006.189.07:49:32.70#ibcon#wrote, iclass 17, count 0 2006.189.07:49:32.70#ibcon#about to read 3, iclass 17, count 0 2006.189.07:49:32.73#ibcon#read 3, iclass 17, count 0 2006.189.07:49:32.73#ibcon#about to read 4, iclass 17, count 0 2006.189.07:49:32.73#ibcon#read 4, iclass 17, count 0 2006.189.07:49:32.73#ibcon#about to read 5, iclass 17, count 0 2006.189.07:49:32.73#ibcon#read 5, iclass 17, count 0 2006.189.07:49:32.73#ibcon#about to read 6, iclass 17, count 0 2006.189.07:49:32.73#ibcon#read 6, iclass 17, count 0 2006.189.07:49:32.73#ibcon#end of sib2, iclass 17, count 0 2006.189.07:49:32.73#ibcon#*after write, iclass 17, count 0 2006.189.07:49:32.73#ibcon#*before return 0, iclass 17, count 0 2006.189.07:49:32.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:32.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:49:32.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:49:32.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:49:32.73$vc4f8/vbbw=wide 2006.189.07:49:32.73#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.07:49:32.73#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.07:49:32.73#ibcon#ireg 8 cls_cnt 0 2006.189.07:49:32.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:49:32.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:49:32.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:49:32.80#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:49:32.80#ibcon#first serial, iclass 19, count 0 2006.189.07:49:32.80#ibcon#enter sib2, iclass 19, count 0 2006.189.07:49:32.80#ibcon#flushed, iclass 19, count 0 2006.189.07:49:32.80#ibcon#about to write, iclass 19, count 0 2006.189.07:49:32.80#ibcon#wrote, iclass 19, count 0 2006.189.07:49:32.80#ibcon#about to read 3, iclass 19, count 0 2006.189.07:49:32.82#ibcon#read 3, iclass 19, count 0 2006.189.07:49:32.82#ibcon#about to read 4, iclass 19, count 0 2006.189.07:49:32.82#ibcon#read 4, iclass 19, count 0 2006.189.07:49:32.82#ibcon#about to read 5, iclass 19, count 0 2006.189.07:49:32.82#ibcon#read 5, iclass 19, count 0 2006.189.07:49:32.82#ibcon#about to read 6, iclass 19, count 0 2006.189.07:49:32.82#ibcon#read 6, iclass 19, count 0 2006.189.07:49:32.82#ibcon#end of sib2, iclass 19, count 0 2006.189.07:49:32.82#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:49:32.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:49:32.82#ibcon#[27=BW32\r\n] 2006.189.07:49:32.82#ibcon#*before write, iclass 19, count 0 2006.189.07:49:32.82#ibcon#enter sib2, iclass 19, count 0 2006.189.07:49:32.82#ibcon#flushed, iclass 19, count 0 2006.189.07:49:32.82#ibcon#about to write, iclass 19, count 0 2006.189.07:49:32.82#ibcon#wrote, iclass 19, count 0 2006.189.07:49:32.82#ibcon#about to read 3, iclass 19, count 0 2006.189.07:49:32.85#ibcon#read 3, iclass 19, count 0 2006.189.07:49:32.85#ibcon#about to read 4, iclass 19, count 0 2006.189.07:49:32.85#ibcon#read 4, iclass 19, count 0 2006.189.07:49:32.85#ibcon#about to read 5, iclass 19, count 0 2006.189.07:49:32.85#ibcon#read 5, iclass 19, count 0 2006.189.07:49:32.85#ibcon#about to read 6, iclass 19, count 0 2006.189.07:49:32.85#ibcon#read 6, iclass 19, count 0 2006.189.07:49:32.85#ibcon#end of sib2, iclass 19, count 0 2006.189.07:49:32.85#ibcon#*after write, iclass 19, count 0 2006.189.07:49:32.85#ibcon#*before return 0, iclass 19, count 0 2006.189.07:49:32.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:49:32.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.07:49:32.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:49:32.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:49:32.85$4f8m12a/ifd4f 2006.189.07:49:32.85$ifd4f/lo= 2006.189.07:49:32.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:49:32.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:49:32.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:49:32.85$ifd4f/patch= 2006.189.07:49:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:49:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:49:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:49:32.85$4f8m12a/"form=m,16.000,1:2 2006.189.07:49:32.85$4f8m12a/"tpicd 2006.189.07:49:32.85$4f8m12a/echo=off 2006.189.07:49:32.85$4f8m12a/xlog=off 2006.189.07:49:32.85:!2006.189.07:50:00 2006.189.07:49:43.14#trakl#Source acquired 2006.189.07:49:45.14#flagr#flagr/antenna,acquired 2006.189.07:50:00.00:preob 2006.189.07:50:01.14/onsource/TRACKING 2006.189.07:50:01.14:!2006.189.07:50:10 2006.189.07:50:10.00:data_valid=on 2006.189.07:50:10.00:midob 2006.189.07:50:10.14/onsource/TRACKING 2006.189.07:50:10.14/wx/25.97,1009.1,89 2006.189.07:50:10.21/cable/+6.4541E-03 2006.189.07:50:11.30/va/01,08,usb,yes,28,30 2006.189.07:50:11.30/va/02,07,usb,yes,28,30 2006.189.07:50:11.30/va/03,06,usb,yes,30,30 2006.189.07:50:11.30/va/04,07,usb,yes,29,31 2006.189.07:50:11.30/va/05,07,usb,yes,31,32 2006.189.07:50:11.30/va/06,06,usb,yes,30,29 2006.189.07:50:11.30/va/07,06,usb,yes,30,30 2006.189.07:50:11.30/va/08,06,usb,yes,32,32 2006.189.07:50:11.53/valo/01,532.99,yes,locked 2006.189.07:50:11.53/valo/02,572.99,yes,locked 2006.189.07:50:11.53/valo/03,672.99,yes,locked 2006.189.07:50:11.53/valo/04,832.99,yes,locked 2006.189.07:50:11.53/valo/05,652.99,yes,locked 2006.189.07:50:11.53/valo/06,772.99,yes,locked 2006.189.07:50:11.53/valo/07,832.99,yes,locked 2006.189.07:50:11.53/valo/08,852.99,yes,locked 2006.189.07:50:12.62/vb/01,04,usb,yes,28,27 2006.189.07:50:12.62/vb/02,04,usb,yes,30,31 2006.189.07:50:12.62/vb/03,04,usb,yes,26,30 2006.189.07:50:12.62/vb/04,04,usb,yes,27,27 2006.189.07:50:12.62/vb/05,04,usb,yes,26,30 2006.189.07:50:12.62/vb/06,04,usb,yes,27,30 2006.189.07:50:12.62/vb/07,04,usb,yes,29,29 2006.189.07:50:12.62/vb/08,04,usb,yes,27,30 2006.189.07:50:12.85/vblo/01,632.99,yes,locked 2006.189.07:50:12.85/vblo/02,640.99,yes,locked 2006.189.07:50:12.85/vblo/03,656.99,yes,locked 2006.189.07:50:12.85/vblo/04,712.99,yes,locked 2006.189.07:50:12.85/vblo/05,744.99,yes,locked 2006.189.07:50:12.85/vblo/06,752.99,yes,locked 2006.189.07:50:12.85/vblo/07,734.99,yes,locked 2006.189.07:50:12.85/vblo/08,744.99,yes,locked 2006.189.07:50:13.00/vabw/8 2006.189.07:50:13.15/vbbw/8 2006.189.07:50:13.24/xfe/off,on,14.7 2006.189.07:50:13.62/ifatt/23,28,28,28 2006.189.07:50:14.07/fmout-gps/S +2.98E-07 2006.189.07:50:14.15:!2006.189.07:51:10 2006.189.07:51:10.01:data_valid=off 2006.189.07:51:10.01:postob 2006.189.07:51:10.10/cable/+6.4527E-03 2006.189.07:51:10.11/wx/25.93,1009.1,89 2006.189.07:51:11.08/fmout-gps/S +2.98E-07 2006.189.07:51:11.08:scan_name=189-0752,k06189,60 2006.189.07:51:11.09:source=3c418,203837.03,511912.7,2000.0,cw 2006.189.07:51:11.14#flagr#flagr/antenna,new-source 2006.189.07:51:12.14:checkk5 2006.189.07:51:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:51:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:51:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:51:13.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:51:14.06/chk_obsdata//k5ts1/T1890750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:51:14.43/chk_obsdata//k5ts2/T1890750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:51:14.81/chk_obsdata//k5ts3/T1890750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:51:15.19/chk_obsdata//k5ts4/T1890750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:51:15.88/k5log//k5ts1_log_newline 2006.189.07:51:16.59/k5log//k5ts2_log_newline 2006.189.07:51:17.29/k5log//k5ts3_log_newline 2006.189.07:51:17.99/k5log//k5ts4_log_newline 2006.189.07:51:18.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:51:18.01:4f8m12a=1 2006.189.07:51:18.01$4f8m12a/echo=on 2006.189.07:51:18.01$4f8m12a/pcalon 2006.189.07:51:18.01$pcalon/"no phase cal control is implemented here 2006.189.07:51:18.01$4f8m12a/"tpicd=stop 2006.189.07:51:18.01$4f8m12a/vc4f8 2006.189.07:51:18.01$vc4f8/valo=1,532.99 2006.189.07:51:18.01#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:51:18.01#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:51:18.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:18.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:18.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:18.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:18.01#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:51:18.01#ibcon#first serial, iclass 21, count 0 2006.189.07:51:18.01#ibcon#enter sib2, iclass 21, count 0 2006.189.07:51:18.01#ibcon#flushed, iclass 21, count 0 2006.189.07:51:18.01#ibcon#about to write, iclass 21, count 0 2006.189.07:51:18.01#ibcon#wrote, iclass 21, count 0 2006.189.07:51:18.01#ibcon#about to read 3, iclass 21, count 0 2006.189.07:51:18.06#ibcon#read 3, iclass 21, count 0 2006.189.07:51:18.06#ibcon#about to read 4, iclass 21, count 0 2006.189.07:51:18.06#ibcon#read 4, iclass 21, count 0 2006.189.07:51:18.06#ibcon#about to read 5, iclass 21, count 0 2006.189.07:51:18.06#ibcon#read 5, iclass 21, count 0 2006.189.07:51:18.06#ibcon#about to read 6, iclass 21, count 0 2006.189.07:51:18.06#ibcon#read 6, iclass 21, count 0 2006.189.07:51:18.06#ibcon#end of sib2, iclass 21, count 0 2006.189.07:51:18.06#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:51:18.06#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:51:18.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:51:18.06#ibcon#*before write, iclass 21, count 0 2006.189.07:51:18.06#ibcon#enter sib2, iclass 21, count 0 2006.189.07:51:18.06#ibcon#flushed, iclass 21, count 0 2006.189.07:51:18.06#ibcon#about to write, iclass 21, count 0 2006.189.07:51:18.06#ibcon#wrote, iclass 21, count 0 2006.189.07:51:18.06#ibcon#about to read 3, iclass 21, count 0 2006.189.07:51:18.11#ibcon#read 3, iclass 21, count 0 2006.189.07:51:18.11#ibcon#about to read 4, iclass 21, count 0 2006.189.07:51:18.11#ibcon#read 4, iclass 21, count 0 2006.189.07:51:18.11#ibcon#about to read 5, iclass 21, count 0 2006.189.07:51:18.11#ibcon#read 5, iclass 21, count 0 2006.189.07:51:18.11#ibcon#about to read 6, iclass 21, count 0 2006.189.07:51:18.11#ibcon#read 6, iclass 21, count 0 2006.189.07:51:18.11#ibcon#end of sib2, iclass 21, count 0 2006.189.07:51:18.11#ibcon#*after write, iclass 21, count 0 2006.189.07:51:18.11#ibcon#*before return 0, iclass 21, count 0 2006.189.07:51:18.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:18.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:18.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:51:18.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:51:18.11$vc4f8/va=1,8 2006.189.07:51:18.11#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:51:18.11#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:51:18.11#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:18.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:18.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:18.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:18.11#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:51:18.11#ibcon#first serial, iclass 23, count 2 2006.189.07:51:18.11#ibcon#enter sib2, iclass 23, count 2 2006.189.07:51:18.11#ibcon#flushed, iclass 23, count 2 2006.189.07:51:18.11#ibcon#about to write, iclass 23, count 2 2006.189.07:51:18.11#ibcon#wrote, iclass 23, count 2 2006.189.07:51:18.11#ibcon#about to read 3, iclass 23, count 2 2006.189.07:51:18.13#ibcon#read 3, iclass 23, count 2 2006.189.07:51:18.13#ibcon#about to read 4, iclass 23, count 2 2006.189.07:51:18.13#ibcon#read 4, iclass 23, count 2 2006.189.07:51:18.13#ibcon#about to read 5, iclass 23, count 2 2006.189.07:51:18.13#ibcon#read 5, iclass 23, count 2 2006.189.07:51:18.13#ibcon#about to read 6, iclass 23, count 2 2006.189.07:51:18.13#ibcon#read 6, iclass 23, count 2 2006.189.07:51:18.13#ibcon#end of sib2, iclass 23, count 2 2006.189.07:51:18.13#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:51:18.13#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:51:18.13#ibcon#[25=AT01-08\r\n] 2006.189.07:51:18.13#ibcon#*before write, iclass 23, count 2 2006.189.07:51:18.13#ibcon#enter sib2, iclass 23, count 2 2006.189.07:51:18.13#ibcon#flushed, iclass 23, count 2 2006.189.07:51:18.13#ibcon#about to write, iclass 23, count 2 2006.189.07:51:18.13#ibcon#wrote, iclass 23, count 2 2006.189.07:51:18.13#ibcon#about to read 3, iclass 23, count 2 2006.189.07:51:18.16#ibcon#read 3, iclass 23, count 2 2006.189.07:51:18.16#ibcon#about to read 4, iclass 23, count 2 2006.189.07:51:18.16#ibcon#read 4, iclass 23, count 2 2006.189.07:51:18.16#ibcon#about to read 5, iclass 23, count 2 2006.189.07:51:18.16#ibcon#read 5, iclass 23, count 2 2006.189.07:51:18.16#ibcon#about to read 6, iclass 23, count 2 2006.189.07:51:18.16#ibcon#read 6, iclass 23, count 2 2006.189.07:51:18.16#ibcon#end of sib2, iclass 23, count 2 2006.189.07:51:18.16#ibcon#*after write, iclass 23, count 2 2006.189.07:51:18.16#ibcon#*before return 0, iclass 23, count 2 2006.189.07:51:18.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:18.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:18.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:51:18.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:18.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:18.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:18.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:18.28#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:51:18.28#ibcon#first serial, iclass 23, count 0 2006.189.07:51:18.28#ibcon#enter sib2, iclass 23, count 0 2006.189.07:51:18.28#ibcon#flushed, iclass 23, count 0 2006.189.07:51:18.28#ibcon#about to write, iclass 23, count 0 2006.189.07:51:18.28#ibcon#wrote, iclass 23, count 0 2006.189.07:51:18.28#ibcon#about to read 3, iclass 23, count 0 2006.189.07:51:18.30#ibcon#read 3, iclass 23, count 0 2006.189.07:51:18.30#ibcon#about to read 4, iclass 23, count 0 2006.189.07:51:18.30#ibcon#read 4, iclass 23, count 0 2006.189.07:51:18.30#ibcon#about to read 5, iclass 23, count 0 2006.189.07:51:18.30#ibcon#read 5, iclass 23, count 0 2006.189.07:51:18.30#ibcon#about to read 6, iclass 23, count 0 2006.189.07:51:18.30#ibcon#read 6, iclass 23, count 0 2006.189.07:51:18.30#ibcon#end of sib2, iclass 23, count 0 2006.189.07:51:18.30#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:51:18.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:51:18.30#ibcon#[25=USB\r\n] 2006.189.07:51:18.30#ibcon#*before write, iclass 23, count 0 2006.189.07:51:18.30#ibcon#enter sib2, iclass 23, count 0 2006.189.07:51:18.30#ibcon#flushed, iclass 23, count 0 2006.189.07:51:18.30#ibcon#about to write, iclass 23, count 0 2006.189.07:51:18.30#ibcon#wrote, iclass 23, count 0 2006.189.07:51:18.30#ibcon#about to read 3, iclass 23, count 0 2006.189.07:51:18.33#ibcon#read 3, iclass 23, count 0 2006.189.07:51:18.33#ibcon#about to read 4, iclass 23, count 0 2006.189.07:51:18.33#ibcon#read 4, iclass 23, count 0 2006.189.07:51:18.33#ibcon#about to read 5, iclass 23, count 0 2006.189.07:51:18.33#ibcon#read 5, iclass 23, count 0 2006.189.07:51:18.33#ibcon#about to read 6, iclass 23, count 0 2006.189.07:51:18.33#ibcon#read 6, iclass 23, count 0 2006.189.07:51:18.33#ibcon#end of sib2, iclass 23, count 0 2006.189.07:51:18.33#ibcon#*after write, iclass 23, count 0 2006.189.07:51:18.33#ibcon#*before return 0, iclass 23, count 0 2006.189.07:51:18.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:18.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:18.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:51:18.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:51:18.33$vc4f8/valo=2,572.99 2006.189.07:51:18.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:51:18.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:51:18.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:18.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:18.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:18.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:18.33#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:51:18.33#ibcon#first serial, iclass 25, count 0 2006.189.07:51:18.33#ibcon#enter sib2, iclass 25, count 0 2006.189.07:51:18.33#ibcon#flushed, iclass 25, count 0 2006.189.07:51:18.33#ibcon#about to write, iclass 25, count 0 2006.189.07:51:18.33#ibcon#wrote, iclass 25, count 0 2006.189.07:51:18.33#ibcon#about to read 3, iclass 25, count 0 2006.189.07:51:18.35#ibcon#read 3, iclass 25, count 0 2006.189.07:51:18.35#ibcon#about to read 4, iclass 25, count 0 2006.189.07:51:18.35#ibcon#read 4, iclass 25, count 0 2006.189.07:51:18.35#ibcon#about to read 5, iclass 25, count 0 2006.189.07:51:18.35#ibcon#read 5, iclass 25, count 0 2006.189.07:51:18.35#ibcon#about to read 6, iclass 25, count 0 2006.189.07:51:18.35#ibcon#read 6, iclass 25, count 0 2006.189.07:51:18.35#ibcon#end of sib2, iclass 25, count 0 2006.189.07:51:18.35#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:51:18.35#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:51:18.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:51:18.35#ibcon#*before write, iclass 25, count 0 2006.189.07:51:18.35#ibcon#enter sib2, iclass 25, count 0 2006.189.07:51:18.35#ibcon#flushed, iclass 25, count 0 2006.189.07:51:18.35#ibcon#about to write, iclass 25, count 0 2006.189.07:51:18.35#ibcon#wrote, iclass 25, count 0 2006.189.07:51:18.35#ibcon#about to read 3, iclass 25, count 0 2006.189.07:51:18.39#ibcon#read 3, iclass 25, count 0 2006.189.07:51:18.39#ibcon#about to read 4, iclass 25, count 0 2006.189.07:51:18.39#ibcon#read 4, iclass 25, count 0 2006.189.07:51:18.39#ibcon#about to read 5, iclass 25, count 0 2006.189.07:51:18.39#ibcon#read 5, iclass 25, count 0 2006.189.07:51:18.39#ibcon#about to read 6, iclass 25, count 0 2006.189.07:51:18.39#ibcon#read 6, iclass 25, count 0 2006.189.07:51:18.39#ibcon#end of sib2, iclass 25, count 0 2006.189.07:51:18.39#ibcon#*after write, iclass 25, count 0 2006.189.07:51:18.39#ibcon#*before return 0, iclass 25, count 0 2006.189.07:51:18.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:18.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:18.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:51:18.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:51:18.39$vc4f8/va=2,7 2006.189.07:51:18.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:51:18.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:51:18.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:18.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:18.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:18.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:18.45#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:51:18.45#ibcon#first serial, iclass 27, count 2 2006.189.07:51:18.45#ibcon#enter sib2, iclass 27, count 2 2006.189.07:51:18.45#ibcon#flushed, iclass 27, count 2 2006.189.07:51:18.45#ibcon#about to write, iclass 27, count 2 2006.189.07:51:18.45#ibcon#wrote, iclass 27, count 2 2006.189.07:51:18.45#ibcon#about to read 3, iclass 27, count 2 2006.189.07:51:18.47#ibcon#read 3, iclass 27, count 2 2006.189.07:51:18.47#ibcon#about to read 4, iclass 27, count 2 2006.189.07:51:18.47#ibcon#read 4, iclass 27, count 2 2006.189.07:51:18.47#ibcon#about to read 5, iclass 27, count 2 2006.189.07:51:18.47#ibcon#read 5, iclass 27, count 2 2006.189.07:51:18.47#ibcon#about to read 6, iclass 27, count 2 2006.189.07:51:18.47#ibcon#read 6, iclass 27, count 2 2006.189.07:51:18.47#ibcon#end of sib2, iclass 27, count 2 2006.189.07:51:18.47#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:51:18.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:51:18.47#ibcon#[25=AT02-07\r\n] 2006.189.07:51:18.47#ibcon#*before write, iclass 27, count 2 2006.189.07:51:18.47#ibcon#enter sib2, iclass 27, count 2 2006.189.07:51:18.47#ibcon#flushed, iclass 27, count 2 2006.189.07:51:18.47#ibcon#about to write, iclass 27, count 2 2006.189.07:51:18.47#ibcon#wrote, iclass 27, count 2 2006.189.07:51:18.47#ibcon#about to read 3, iclass 27, count 2 2006.189.07:51:18.50#ibcon#read 3, iclass 27, count 2 2006.189.07:51:18.50#ibcon#about to read 4, iclass 27, count 2 2006.189.07:51:18.50#ibcon#read 4, iclass 27, count 2 2006.189.07:51:18.50#ibcon#about to read 5, iclass 27, count 2 2006.189.07:51:18.50#ibcon#read 5, iclass 27, count 2 2006.189.07:51:18.50#ibcon#about to read 6, iclass 27, count 2 2006.189.07:51:18.50#ibcon#read 6, iclass 27, count 2 2006.189.07:51:18.50#ibcon#end of sib2, iclass 27, count 2 2006.189.07:51:18.50#ibcon#*after write, iclass 27, count 2 2006.189.07:51:18.50#ibcon#*before return 0, iclass 27, count 2 2006.189.07:51:18.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:18.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:18.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:51:18.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:18.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:18.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:18.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:18.62#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:51:18.62#ibcon#first serial, iclass 27, count 0 2006.189.07:51:18.62#ibcon#enter sib2, iclass 27, count 0 2006.189.07:51:18.62#ibcon#flushed, iclass 27, count 0 2006.189.07:51:18.62#ibcon#about to write, iclass 27, count 0 2006.189.07:51:18.62#ibcon#wrote, iclass 27, count 0 2006.189.07:51:18.62#ibcon#about to read 3, iclass 27, count 0 2006.189.07:51:18.64#ibcon#read 3, iclass 27, count 0 2006.189.07:51:18.64#ibcon#about to read 4, iclass 27, count 0 2006.189.07:51:18.64#ibcon#read 4, iclass 27, count 0 2006.189.07:51:18.64#ibcon#about to read 5, iclass 27, count 0 2006.189.07:51:18.64#ibcon#read 5, iclass 27, count 0 2006.189.07:51:18.64#ibcon#about to read 6, iclass 27, count 0 2006.189.07:51:18.64#ibcon#read 6, iclass 27, count 0 2006.189.07:51:18.64#ibcon#end of sib2, iclass 27, count 0 2006.189.07:51:18.64#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:51:18.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:51:18.64#ibcon#[25=USB\r\n] 2006.189.07:51:18.64#ibcon#*before write, iclass 27, count 0 2006.189.07:51:18.64#ibcon#enter sib2, iclass 27, count 0 2006.189.07:51:18.64#ibcon#flushed, iclass 27, count 0 2006.189.07:51:18.64#ibcon#about to write, iclass 27, count 0 2006.189.07:51:18.64#ibcon#wrote, iclass 27, count 0 2006.189.07:51:18.64#ibcon#about to read 3, iclass 27, count 0 2006.189.07:51:18.67#ibcon#read 3, iclass 27, count 0 2006.189.07:51:18.67#ibcon#about to read 4, iclass 27, count 0 2006.189.07:51:18.67#ibcon#read 4, iclass 27, count 0 2006.189.07:51:18.67#ibcon#about to read 5, iclass 27, count 0 2006.189.07:51:18.67#ibcon#read 5, iclass 27, count 0 2006.189.07:51:18.67#ibcon#about to read 6, iclass 27, count 0 2006.189.07:51:18.67#ibcon#read 6, iclass 27, count 0 2006.189.07:51:18.67#ibcon#end of sib2, iclass 27, count 0 2006.189.07:51:18.67#ibcon#*after write, iclass 27, count 0 2006.189.07:51:18.67#ibcon#*before return 0, iclass 27, count 0 2006.189.07:51:18.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:18.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:18.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:51:18.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:51:18.67$vc4f8/valo=3,672.99 2006.189.07:51:18.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:51:18.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:51:18.67#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:18.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:18.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:18.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:18.67#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:51:18.67#ibcon#first serial, iclass 29, count 0 2006.189.07:51:18.67#ibcon#enter sib2, iclass 29, count 0 2006.189.07:51:18.67#ibcon#flushed, iclass 29, count 0 2006.189.07:51:18.67#ibcon#about to write, iclass 29, count 0 2006.189.07:51:18.67#ibcon#wrote, iclass 29, count 0 2006.189.07:51:18.67#ibcon#about to read 3, iclass 29, count 0 2006.189.07:51:18.69#ibcon#read 3, iclass 29, count 0 2006.189.07:51:18.69#ibcon#about to read 4, iclass 29, count 0 2006.189.07:51:18.69#ibcon#read 4, iclass 29, count 0 2006.189.07:51:18.69#ibcon#about to read 5, iclass 29, count 0 2006.189.07:51:18.69#ibcon#read 5, iclass 29, count 0 2006.189.07:51:18.69#ibcon#about to read 6, iclass 29, count 0 2006.189.07:51:18.69#ibcon#read 6, iclass 29, count 0 2006.189.07:51:18.69#ibcon#end of sib2, iclass 29, count 0 2006.189.07:51:18.69#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:51:18.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:51:18.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:51:18.69#ibcon#*before write, iclass 29, count 0 2006.189.07:51:18.69#ibcon#enter sib2, iclass 29, count 0 2006.189.07:51:18.69#ibcon#flushed, iclass 29, count 0 2006.189.07:51:18.69#ibcon#about to write, iclass 29, count 0 2006.189.07:51:18.69#ibcon#wrote, iclass 29, count 0 2006.189.07:51:18.69#ibcon#about to read 3, iclass 29, count 0 2006.189.07:51:18.73#ibcon#read 3, iclass 29, count 0 2006.189.07:51:18.73#ibcon#about to read 4, iclass 29, count 0 2006.189.07:51:18.73#ibcon#read 4, iclass 29, count 0 2006.189.07:51:18.73#ibcon#about to read 5, iclass 29, count 0 2006.189.07:51:18.73#ibcon#read 5, iclass 29, count 0 2006.189.07:51:18.73#ibcon#about to read 6, iclass 29, count 0 2006.189.07:51:18.73#ibcon#read 6, iclass 29, count 0 2006.189.07:51:18.73#ibcon#end of sib2, iclass 29, count 0 2006.189.07:51:18.73#ibcon#*after write, iclass 29, count 0 2006.189.07:51:18.73#ibcon#*before return 0, iclass 29, count 0 2006.189.07:51:18.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:18.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:18.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:51:18.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:51:18.73$vc4f8/va=3,6 2006.189.07:51:18.73#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.07:51:18.73#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.07:51:18.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:18.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:18.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:18.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:18.79#ibcon#enter wrdev, iclass 31, count 2 2006.189.07:51:18.79#ibcon#first serial, iclass 31, count 2 2006.189.07:51:18.79#ibcon#enter sib2, iclass 31, count 2 2006.189.07:51:18.79#ibcon#flushed, iclass 31, count 2 2006.189.07:51:18.79#ibcon#about to write, iclass 31, count 2 2006.189.07:51:18.79#ibcon#wrote, iclass 31, count 2 2006.189.07:51:18.79#ibcon#about to read 3, iclass 31, count 2 2006.189.07:51:18.81#ibcon#read 3, iclass 31, count 2 2006.189.07:51:18.81#ibcon#about to read 4, iclass 31, count 2 2006.189.07:51:18.81#ibcon#read 4, iclass 31, count 2 2006.189.07:51:18.81#ibcon#about to read 5, iclass 31, count 2 2006.189.07:51:18.81#ibcon#read 5, iclass 31, count 2 2006.189.07:51:18.81#ibcon#about to read 6, iclass 31, count 2 2006.189.07:51:18.81#ibcon#read 6, iclass 31, count 2 2006.189.07:51:18.81#ibcon#end of sib2, iclass 31, count 2 2006.189.07:51:18.81#ibcon#*mode == 0, iclass 31, count 2 2006.189.07:51:18.81#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.07:51:18.81#ibcon#[25=AT03-06\r\n] 2006.189.07:51:18.81#ibcon#*before write, iclass 31, count 2 2006.189.07:51:18.81#ibcon#enter sib2, iclass 31, count 2 2006.189.07:51:18.81#ibcon#flushed, iclass 31, count 2 2006.189.07:51:18.81#ibcon#about to write, iclass 31, count 2 2006.189.07:51:18.81#ibcon#wrote, iclass 31, count 2 2006.189.07:51:18.81#ibcon#about to read 3, iclass 31, count 2 2006.189.07:51:18.84#ibcon#read 3, iclass 31, count 2 2006.189.07:51:18.84#ibcon#about to read 4, iclass 31, count 2 2006.189.07:51:18.84#ibcon#read 4, iclass 31, count 2 2006.189.07:51:18.84#ibcon#about to read 5, iclass 31, count 2 2006.189.07:51:18.84#ibcon#read 5, iclass 31, count 2 2006.189.07:51:18.84#ibcon#about to read 6, iclass 31, count 2 2006.189.07:51:18.84#ibcon#read 6, iclass 31, count 2 2006.189.07:51:18.84#ibcon#end of sib2, iclass 31, count 2 2006.189.07:51:18.84#ibcon#*after write, iclass 31, count 2 2006.189.07:51:18.84#ibcon#*before return 0, iclass 31, count 2 2006.189.07:51:18.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:18.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:18.84#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.07:51:18.84#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:18.84#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:18.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:18.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:18.96#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:51:18.96#ibcon#first serial, iclass 31, count 0 2006.189.07:51:18.96#ibcon#enter sib2, iclass 31, count 0 2006.189.07:51:18.96#ibcon#flushed, iclass 31, count 0 2006.189.07:51:18.96#ibcon#about to write, iclass 31, count 0 2006.189.07:51:18.96#ibcon#wrote, iclass 31, count 0 2006.189.07:51:18.96#ibcon#about to read 3, iclass 31, count 0 2006.189.07:51:18.98#ibcon#read 3, iclass 31, count 0 2006.189.07:51:18.98#ibcon#about to read 4, iclass 31, count 0 2006.189.07:51:18.98#ibcon#read 4, iclass 31, count 0 2006.189.07:51:18.98#ibcon#about to read 5, iclass 31, count 0 2006.189.07:51:18.98#ibcon#read 5, iclass 31, count 0 2006.189.07:51:18.98#ibcon#about to read 6, iclass 31, count 0 2006.189.07:51:18.98#ibcon#read 6, iclass 31, count 0 2006.189.07:51:18.98#ibcon#end of sib2, iclass 31, count 0 2006.189.07:51:18.98#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:51:18.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:51:18.98#ibcon#[25=USB\r\n] 2006.189.07:51:18.98#ibcon#*before write, iclass 31, count 0 2006.189.07:51:18.98#ibcon#enter sib2, iclass 31, count 0 2006.189.07:51:18.98#ibcon#flushed, iclass 31, count 0 2006.189.07:51:18.98#ibcon#about to write, iclass 31, count 0 2006.189.07:51:18.98#ibcon#wrote, iclass 31, count 0 2006.189.07:51:18.98#ibcon#about to read 3, iclass 31, count 0 2006.189.07:51:19.01#ibcon#read 3, iclass 31, count 0 2006.189.07:51:19.01#ibcon#about to read 4, iclass 31, count 0 2006.189.07:51:19.01#ibcon#read 4, iclass 31, count 0 2006.189.07:51:19.01#ibcon#about to read 5, iclass 31, count 0 2006.189.07:51:19.01#ibcon#read 5, iclass 31, count 0 2006.189.07:51:19.01#ibcon#about to read 6, iclass 31, count 0 2006.189.07:51:19.01#ibcon#read 6, iclass 31, count 0 2006.189.07:51:19.01#ibcon#end of sib2, iclass 31, count 0 2006.189.07:51:19.01#ibcon#*after write, iclass 31, count 0 2006.189.07:51:19.01#ibcon#*before return 0, iclass 31, count 0 2006.189.07:51:19.01#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:19.01#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:19.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:51:19.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:51:19.01$vc4f8/valo=4,832.99 2006.189.07:51:19.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:51:19.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:51:19.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:19.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:19.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:19.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:19.01#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:51:19.01#ibcon#first serial, iclass 33, count 0 2006.189.07:51:19.01#ibcon#enter sib2, iclass 33, count 0 2006.189.07:51:19.01#ibcon#flushed, iclass 33, count 0 2006.189.07:51:19.01#ibcon#about to write, iclass 33, count 0 2006.189.07:51:19.01#ibcon#wrote, iclass 33, count 0 2006.189.07:51:19.01#ibcon#about to read 3, iclass 33, count 0 2006.189.07:51:19.03#ibcon#read 3, iclass 33, count 0 2006.189.07:51:19.03#ibcon#about to read 4, iclass 33, count 0 2006.189.07:51:19.03#ibcon#read 4, iclass 33, count 0 2006.189.07:51:19.03#ibcon#about to read 5, iclass 33, count 0 2006.189.07:51:19.03#ibcon#read 5, iclass 33, count 0 2006.189.07:51:19.03#ibcon#about to read 6, iclass 33, count 0 2006.189.07:51:19.03#ibcon#read 6, iclass 33, count 0 2006.189.07:51:19.03#ibcon#end of sib2, iclass 33, count 0 2006.189.07:51:19.03#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:51:19.03#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:51:19.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:51:19.03#ibcon#*before write, iclass 33, count 0 2006.189.07:51:19.03#ibcon#enter sib2, iclass 33, count 0 2006.189.07:51:19.03#ibcon#flushed, iclass 33, count 0 2006.189.07:51:19.03#ibcon#about to write, iclass 33, count 0 2006.189.07:51:19.03#ibcon#wrote, iclass 33, count 0 2006.189.07:51:19.03#ibcon#about to read 3, iclass 33, count 0 2006.189.07:51:19.07#ibcon#read 3, iclass 33, count 0 2006.189.07:51:19.07#ibcon#about to read 4, iclass 33, count 0 2006.189.07:51:19.07#ibcon#read 4, iclass 33, count 0 2006.189.07:51:19.07#ibcon#about to read 5, iclass 33, count 0 2006.189.07:51:19.07#ibcon#read 5, iclass 33, count 0 2006.189.07:51:19.07#ibcon#about to read 6, iclass 33, count 0 2006.189.07:51:19.07#ibcon#read 6, iclass 33, count 0 2006.189.07:51:19.07#ibcon#end of sib2, iclass 33, count 0 2006.189.07:51:19.07#ibcon#*after write, iclass 33, count 0 2006.189.07:51:19.07#ibcon#*before return 0, iclass 33, count 0 2006.189.07:51:19.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:19.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:19.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:51:19.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:51:19.07$vc4f8/va=4,7 2006.189.07:51:19.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:51:19.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:51:19.07#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:19.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:19.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:19.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:19.13#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:51:19.13#ibcon#first serial, iclass 35, count 2 2006.189.07:51:19.13#ibcon#enter sib2, iclass 35, count 2 2006.189.07:51:19.13#ibcon#flushed, iclass 35, count 2 2006.189.07:51:19.13#ibcon#about to write, iclass 35, count 2 2006.189.07:51:19.13#ibcon#wrote, iclass 35, count 2 2006.189.07:51:19.13#ibcon#about to read 3, iclass 35, count 2 2006.189.07:51:19.15#ibcon#read 3, iclass 35, count 2 2006.189.07:51:19.15#ibcon#about to read 4, iclass 35, count 2 2006.189.07:51:19.15#ibcon#read 4, iclass 35, count 2 2006.189.07:51:19.15#ibcon#about to read 5, iclass 35, count 2 2006.189.07:51:19.15#ibcon#read 5, iclass 35, count 2 2006.189.07:51:19.15#ibcon#about to read 6, iclass 35, count 2 2006.189.07:51:19.15#ibcon#read 6, iclass 35, count 2 2006.189.07:51:19.15#ibcon#end of sib2, iclass 35, count 2 2006.189.07:51:19.15#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:51:19.15#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:51:19.15#ibcon#[25=AT04-07\r\n] 2006.189.07:51:19.15#ibcon#*before write, iclass 35, count 2 2006.189.07:51:19.15#ibcon#enter sib2, iclass 35, count 2 2006.189.07:51:19.15#ibcon#flushed, iclass 35, count 2 2006.189.07:51:19.15#ibcon#about to write, iclass 35, count 2 2006.189.07:51:19.15#ibcon#wrote, iclass 35, count 2 2006.189.07:51:19.15#ibcon#about to read 3, iclass 35, count 2 2006.189.07:51:19.18#ibcon#read 3, iclass 35, count 2 2006.189.07:51:19.18#ibcon#about to read 4, iclass 35, count 2 2006.189.07:51:19.18#ibcon#read 4, iclass 35, count 2 2006.189.07:51:19.18#ibcon#about to read 5, iclass 35, count 2 2006.189.07:51:19.18#ibcon#read 5, iclass 35, count 2 2006.189.07:51:19.18#ibcon#about to read 6, iclass 35, count 2 2006.189.07:51:19.18#ibcon#read 6, iclass 35, count 2 2006.189.07:51:19.18#ibcon#end of sib2, iclass 35, count 2 2006.189.07:51:19.18#ibcon#*after write, iclass 35, count 2 2006.189.07:51:19.18#ibcon#*before return 0, iclass 35, count 2 2006.189.07:51:19.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:19.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:19.18#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:51:19.18#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:19.18#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:19.30#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:19.30#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:19.30#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:51:19.30#ibcon#first serial, iclass 35, count 0 2006.189.07:51:19.30#ibcon#enter sib2, iclass 35, count 0 2006.189.07:51:19.30#ibcon#flushed, iclass 35, count 0 2006.189.07:51:19.30#ibcon#about to write, iclass 35, count 0 2006.189.07:51:19.30#ibcon#wrote, iclass 35, count 0 2006.189.07:51:19.30#ibcon#about to read 3, iclass 35, count 0 2006.189.07:51:19.32#ibcon#read 3, iclass 35, count 0 2006.189.07:51:19.32#ibcon#about to read 4, iclass 35, count 0 2006.189.07:51:19.32#ibcon#read 4, iclass 35, count 0 2006.189.07:51:19.32#ibcon#about to read 5, iclass 35, count 0 2006.189.07:51:19.32#ibcon#read 5, iclass 35, count 0 2006.189.07:51:19.32#ibcon#about to read 6, iclass 35, count 0 2006.189.07:51:19.32#ibcon#read 6, iclass 35, count 0 2006.189.07:51:19.32#ibcon#end of sib2, iclass 35, count 0 2006.189.07:51:19.32#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:51:19.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:51:19.32#ibcon#[25=USB\r\n] 2006.189.07:51:19.32#ibcon#*before write, iclass 35, count 0 2006.189.07:51:19.32#ibcon#enter sib2, iclass 35, count 0 2006.189.07:51:19.32#ibcon#flushed, iclass 35, count 0 2006.189.07:51:19.32#ibcon#about to write, iclass 35, count 0 2006.189.07:51:19.32#ibcon#wrote, iclass 35, count 0 2006.189.07:51:19.32#ibcon#about to read 3, iclass 35, count 0 2006.189.07:51:19.35#ibcon#read 3, iclass 35, count 0 2006.189.07:51:19.35#ibcon#about to read 4, iclass 35, count 0 2006.189.07:51:19.35#ibcon#read 4, iclass 35, count 0 2006.189.07:51:19.35#ibcon#about to read 5, iclass 35, count 0 2006.189.07:51:19.35#ibcon#read 5, iclass 35, count 0 2006.189.07:51:19.35#ibcon#about to read 6, iclass 35, count 0 2006.189.07:51:19.35#ibcon#read 6, iclass 35, count 0 2006.189.07:51:19.35#ibcon#end of sib2, iclass 35, count 0 2006.189.07:51:19.35#ibcon#*after write, iclass 35, count 0 2006.189.07:51:19.35#ibcon#*before return 0, iclass 35, count 0 2006.189.07:51:19.35#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:19.35#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:19.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:51:19.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:51:19.35$vc4f8/valo=5,652.99 2006.189.07:51:19.35#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:51:19.35#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:51:19.35#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:19.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:19.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:19.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:19.35#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:51:19.35#ibcon#first serial, iclass 37, count 0 2006.189.07:51:19.35#ibcon#enter sib2, iclass 37, count 0 2006.189.07:51:19.35#ibcon#flushed, iclass 37, count 0 2006.189.07:51:19.35#ibcon#about to write, iclass 37, count 0 2006.189.07:51:19.35#ibcon#wrote, iclass 37, count 0 2006.189.07:51:19.35#ibcon#about to read 3, iclass 37, count 0 2006.189.07:51:19.37#ibcon#read 3, iclass 37, count 0 2006.189.07:51:19.37#ibcon#about to read 4, iclass 37, count 0 2006.189.07:51:19.37#ibcon#read 4, iclass 37, count 0 2006.189.07:51:19.37#ibcon#about to read 5, iclass 37, count 0 2006.189.07:51:19.37#ibcon#read 5, iclass 37, count 0 2006.189.07:51:19.37#ibcon#about to read 6, iclass 37, count 0 2006.189.07:51:19.37#ibcon#read 6, iclass 37, count 0 2006.189.07:51:19.37#ibcon#end of sib2, iclass 37, count 0 2006.189.07:51:19.37#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:51:19.37#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:51:19.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:51:19.37#ibcon#*before write, iclass 37, count 0 2006.189.07:51:19.37#ibcon#enter sib2, iclass 37, count 0 2006.189.07:51:19.37#ibcon#flushed, iclass 37, count 0 2006.189.07:51:19.37#ibcon#about to write, iclass 37, count 0 2006.189.07:51:19.37#ibcon#wrote, iclass 37, count 0 2006.189.07:51:19.37#ibcon#about to read 3, iclass 37, count 0 2006.189.07:51:19.41#ibcon#read 3, iclass 37, count 0 2006.189.07:51:19.41#ibcon#about to read 4, iclass 37, count 0 2006.189.07:51:19.41#ibcon#read 4, iclass 37, count 0 2006.189.07:51:19.41#ibcon#about to read 5, iclass 37, count 0 2006.189.07:51:19.41#ibcon#read 5, iclass 37, count 0 2006.189.07:51:19.41#ibcon#about to read 6, iclass 37, count 0 2006.189.07:51:19.41#ibcon#read 6, iclass 37, count 0 2006.189.07:51:19.41#ibcon#end of sib2, iclass 37, count 0 2006.189.07:51:19.41#ibcon#*after write, iclass 37, count 0 2006.189.07:51:19.41#ibcon#*before return 0, iclass 37, count 0 2006.189.07:51:19.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:19.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:19.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:51:19.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:51:19.41$vc4f8/va=5,7 2006.189.07:51:19.41#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:51:19.41#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:51:19.41#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:19.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:19.47#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:19.47#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:19.47#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:51:19.47#ibcon#first serial, iclass 39, count 2 2006.189.07:51:19.47#ibcon#enter sib2, iclass 39, count 2 2006.189.07:51:19.47#ibcon#flushed, iclass 39, count 2 2006.189.07:51:19.47#ibcon#about to write, iclass 39, count 2 2006.189.07:51:19.47#ibcon#wrote, iclass 39, count 2 2006.189.07:51:19.47#ibcon#about to read 3, iclass 39, count 2 2006.189.07:51:19.49#ibcon#read 3, iclass 39, count 2 2006.189.07:51:19.49#ibcon#about to read 4, iclass 39, count 2 2006.189.07:51:19.49#ibcon#read 4, iclass 39, count 2 2006.189.07:51:19.49#ibcon#about to read 5, iclass 39, count 2 2006.189.07:51:19.49#ibcon#read 5, iclass 39, count 2 2006.189.07:51:19.49#ibcon#about to read 6, iclass 39, count 2 2006.189.07:51:19.49#ibcon#read 6, iclass 39, count 2 2006.189.07:51:19.49#ibcon#end of sib2, iclass 39, count 2 2006.189.07:51:19.49#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:51:19.49#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:51:19.49#ibcon#[25=AT05-07\r\n] 2006.189.07:51:19.49#ibcon#*before write, iclass 39, count 2 2006.189.07:51:19.49#ibcon#enter sib2, iclass 39, count 2 2006.189.07:51:19.49#ibcon#flushed, iclass 39, count 2 2006.189.07:51:19.49#ibcon#about to write, iclass 39, count 2 2006.189.07:51:19.49#ibcon#wrote, iclass 39, count 2 2006.189.07:51:19.49#ibcon#about to read 3, iclass 39, count 2 2006.189.07:51:19.52#ibcon#read 3, iclass 39, count 2 2006.189.07:51:19.52#ibcon#about to read 4, iclass 39, count 2 2006.189.07:51:19.52#ibcon#read 4, iclass 39, count 2 2006.189.07:51:19.52#ibcon#about to read 5, iclass 39, count 2 2006.189.07:51:19.52#ibcon#read 5, iclass 39, count 2 2006.189.07:51:19.52#ibcon#about to read 6, iclass 39, count 2 2006.189.07:51:19.52#ibcon#read 6, iclass 39, count 2 2006.189.07:51:19.52#ibcon#end of sib2, iclass 39, count 2 2006.189.07:51:19.52#ibcon#*after write, iclass 39, count 2 2006.189.07:51:19.52#ibcon#*before return 0, iclass 39, count 2 2006.189.07:51:19.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:19.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:19.52#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:51:19.52#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:19.52#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:19.64#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:19.64#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:19.64#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:51:19.64#ibcon#first serial, iclass 39, count 0 2006.189.07:51:19.64#ibcon#enter sib2, iclass 39, count 0 2006.189.07:51:19.64#ibcon#flushed, iclass 39, count 0 2006.189.07:51:19.64#ibcon#about to write, iclass 39, count 0 2006.189.07:51:19.64#ibcon#wrote, iclass 39, count 0 2006.189.07:51:19.64#ibcon#about to read 3, iclass 39, count 0 2006.189.07:51:19.66#ibcon#read 3, iclass 39, count 0 2006.189.07:51:19.66#ibcon#about to read 4, iclass 39, count 0 2006.189.07:51:19.66#ibcon#read 4, iclass 39, count 0 2006.189.07:51:19.66#ibcon#about to read 5, iclass 39, count 0 2006.189.07:51:19.66#ibcon#read 5, iclass 39, count 0 2006.189.07:51:19.66#ibcon#about to read 6, iclass 39, count 0 2006.189.07:51:19.66#ibcon#read 6, iclass 39, count 0 2006.189.07:51:19.66#ibcon#end of sib2, iclass 39, count 0 2006.189.07:51:19.66#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:51:19.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:51:19.66#ibcon#[25=USB\r\n] 2006.189.07:51:19.66#ibcon#*before write, iclass 39, count 0 2006.189.07:51:19.66#ibcon#enter sib2, iclass 39, count 0 2006.189.07:51:19.66#ibcon#flushed, iclass 39, count 0 2006.189.07:51:19.66#ibcon#about to write, iclass 39, count 0 2006.189.07:51:19.66#ibcon#wrote, iclass 39, count 0 2006.189.07:51:19.66#ibcon#about to read 3, iclass 39, count 0 2006.189.07:51:19.69#ibcon#read 3, iclass 39, count 0 2006.189.07:51:19.69#ibcon#about to read 4, iclass 39, count 0 2006.189.07:51:19.69#ibcon#read 4, iclass 39, count 0 2006.189.07:51:19.69#ibcon#about to read 5, iclass 39, count 0 2006.189.07:51:19.69#ibcon#read 5, iclass 39, count 0 2006.189.07:51:19.69#ibcon#about to read 6, iclass 39, count 0 2006.189.07:51:19.69#ibcon#read 6, iclass 39, count 0 2006.189.07:51:19.69#ibcon#end of sib2, iclass 39, count 0 2006.189.07:51:19.69#ibcon#*after write, iclass 39, count 0 2006.189.07:51:19.69#ibcon#*before return 0, iclass 39, count 0 2006.189.07:51:19.69#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:19.69#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:19.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:51:19.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:51:19.69$vc4f8/valo=6,772.99 2006.189.07:51:19.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:51:19.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:51:19.69#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:19.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:19.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:19.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:19.69#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:51:19.69#ibcon#first serial, iclass 3, count 0 2006.189.07:51:19.69#ibcon#enter sib2, iclass 3, count 0 2006.189.07:51:19.69#ibcon#flushed, iclass 3, count 0 2006.189.07:51:19.69#ibcon#about to write, iclass 3, count 0 2006.189.07:51:19.69#ibcon#wrote, iclass 3, count 0 2006.189.07:51:19.69#ibcon#about to read 3, iclass 3, count 0 2006.189.07:51:19.71#ibcon#read 3, iclass 3, count 0 2006.189.07:51:19.71#ibcon#about to read 4, iclass 3, count 0 2006.189.07:51:19.71#ibcon#read 4, iclass 3, count 0 2006.189.07:51:19.71#ibcon#about to read 5, iclass 3, count 0 2006.189.07:51:19.71#ibcon#read 5, iclass 3, count 0 2006.189.07:51:19.71#ibcon#about to read 6, iclass 3, count 0 2006.189.07:51:19.71#ibcon#read 6, iclass 3, count 0 2006.189.07:51:19.71#ibcon#end of sib2, iclass 3, count 0 2006.189.07:51:19.71#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:51:19.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:51:19.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:51:19.71#ibcon#*before write, iclass 3, count 0 2006.189.07:51:19.71#ibcon#enter sib2, iclass 3, count 0 2006.189.07:51:19.71#ibcon#flushed, iclass 3, count 0 2006.189.07:51:19.71#ibcon#about to write, iclass 3, count 0 2006.189.07:51:19.71#ibcon#wrote, iclass 3, count 0 2006.189.07:51:19.71#ibcon#about to read 3, iclass 3, count 0 2006.189.07:51:19.75#ibcon#read 3, iclass 3, count 0 2006.189.07:51:19.75#ibcon#about to read 4, iclass 3, count 0 2006.189.07:51:19.75#ibcon#read 4, iclass 3, count 0 2006.189.07:51:19.75#ibcon#about to read 5, iclass 3, count 0 2006.189.07:51:19.75#ibcon#read 5, iclass 3, count 0 2006.189.07:51:19.75#ibcon#about to read 6, iclass 3, count 0 2006.189.07:51:19.75#ibcon#read 6, iclass 3, count 0 2006.189.07:51:19.75#ibcon#end of sib2, iclass 3, count 0 2006.189.07:51:19.75#ibcon#*after write, iclass 3, count 0 2006.189.07:51:19.75#ibcon#*before return 0, iclass 3, count 0 2006.189.07:51:19.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:19.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:19.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:51:19.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:51:19.75$vc4f8/va=6,6 2006.189.07:51:19.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:51:19.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:51:19.75#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:19.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:19.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:19.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:19.81#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:51:19.81#ibcon#first serial, iclass 5, count 2 2006.189.07:51:19.81#ibcon#enter sib2, iclass 5, count 2 2006.189.07:51:19.81#ibcon#flushed, iclass 5, count 2 2006.189.07:51:19.81#ibcon#about to write, iclass 5, count 2 2006.189.07:51:19.81#ibcon#wrote, iclass 5, count 2 2006.189.07:51:19.81#ibcon#about to read 3, iclass 5, count 2 2006.189.07:51:19.83#ibcon#read 3, iclass 5, count 2 2006.189.07:51:19.83#ibcon#about to read 4, iclass 5, count 2 2006.189.07:51:19.83#ibcon#read 4, iclass 5, count 2 2006.189.07:51:19.83#ibcon#about to read 5, iclass 5, count 2 2006.189.07:51:19.83#ibcon#read 5, iclass 5, count 2 2006.189.07:51:19.83#ibcon#about to read 6, iclass 5, count 2 2006.189.07:51:19.83#ibcon#read 6, iclass 5, count 2 2006.189.07:51:19.83#ibcon#end of sib2, iclass 5, count 2 2006.189.07:51:19.83#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:51:19.83#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:51:19.83#ibcon#[25=AT06-06\r\n] 2006.189.07:51:19.83#ibcon#*before write, iclass 5, count 2 2006.189.07:51:19.83#ibcon#enter sib2, iclass 5, count 2 2006.189.07:51:19.83#ibcon#flushed, iclass 5, count 2 2006.189.07:51:19.83#ibcon#about to write, iclass 5, count 2 2006.189.07:51:19.83#ibcon#wrote, iclass 5, count 2 2006.189.07:51:19.83#ibcon#about to read 3, iclass 5, count 2 2006.189.07:51:19.86#ibcon#read 3, iclass 5, count 2 2006.189.07:51:19.86#ibcon#about to read 4, iclass 5, count 2 2006.189.07:51:19.86#ibcon#read 4, iclass 5, count 2 2006.189.07:51:19.86#ibcon#about to read 5, iclass 5, count 2 2006.189.07:51:19.86#ibcon#read 5, iclass 5, count 2 2006.189.07:51:19.86#ibcon#about to read 6, iclass 5, count 2 2006.189.07:51:19.86#ibcon#read 6, iclass 5, count 2 2006.189.07:51:19.86#ibcon#end of sib2, iclass 5, count 2 2006.189.07:51:19.86#ibcon#*after write, iclass 5, count 2 2006.189.07:51:19.86#ibcon#*before return 0, iclass 5, count 2 2006.189.07:51:19.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:19.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:19.86#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:51:19.86#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:19.86#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:19.98#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:19.98#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:19.98#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:51:19.98#ibcon#first serial, iclass 5, count 0 2006.189.07:51:19.98#ibcon#enter sib2, iclass 5, count 0 2006.189.07:51:19.98#ibcon#flushed, iclass 5, count 0 2006.189.07:51:19.98#ibcon#about to write, iclass 5, count 0 2006.189.07:51:19.98#ibcon#wrote, iclass 5, count 0 2006.189.07:51:19.98#ibcon#about to read 3, iclass 5, count 0 2006.189.07:51:20.00#ibcon#read 3, iclass 5, count 0 2006.189.07:51:20.00#ibcon#about to read 4, iclass 5, count 0 2006.189.07:51:20.00#ibcon#read 4, iclass 5, count 0 2006.189.07:51:20.00#ibcon#about to read 5, iclass 5, count 0 2006.189.07:51:20.00#ibcon#read 5, iclass 5, count 0 2006.189.07:51:20.00#ibcon#about to read 6, iclass 5, count 0 2006.189.07:51:20.00#ibcon#read 6, iclass 5, count 0 2006.189.07:51:20.00#ibcon#end of sib2, iclass 5, count 0 2006.189.07:51:20.00#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:51:20.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:51:20.00#ibcon#[25=USB\r\n] 2006.189.07:51:20.00#ibcon#*before write, iclass 5, count 0 2006.189.07:51:20.00#ibcon#enter sib2, iclass 5, count 0 2006.189.07:51:20.00#ibcon#flushed, iclass 5, count 0 2006.189.07:51:20.00#ibcon#about to write, iclass 5, count 0 2006.189.07:51:20.00#ibcon#wrote, iclass 5, count 0 2006.189.07:51:20.00#ibcon#about to read 3, iclass 5, count 0 2006.189.07:51:20.03#ibcon#read 3, iclass 5, count 0 2006.189.07:51:20.03#ibcon#about to read 4, iclass 5, count 0 2006.189.07:51:20.03#ibcon#read 4, iclass 5, count 0 2006.189.07:51:20.03#ibcon#about to read 5, iclass 5, count 0 2006.189.07:51:20.03#ibcon#read 5, iclass 5, count 0 2006.189.07:51:20.03#ibcon#about to read 6, iclass 5, count 0 2006.189.07:51:20.03#ibcon#read 6, iclass 5, count 0 2006.189.07:51:20.03#ibcon#end of sib2, iclass 5, count 0 2006.189.07:51:20.03#ibcon#*after write, iclass 5, count 0 2006.189.07:51:20.03#ibcon#*before return 0, iclass 5, count 0 2006.189.07:51:20.03#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:20.03#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:20.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:51:20.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:51:20.03$vc4f8/valo=7,832.99 2006.189.07:51:20.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:51:20.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:51:20.03#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:20.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:20.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:20.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:20.03#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:51:20.03#ibcon#first serial, iclass 7, count 0 2006.189.07:51:20.03#ibcon#enter sib2, iclass 7, count 0 2006.189.07:51:20.03#ibcon#flushed, iclass 7, count 0 2006.189.07:51:20.03#ibcon#about to write, iclass 7, count 0 2006.189.07:51:20.03#ibcon#wrote, iclass 7, count 0 2006.189.07:51:20.03#ibcon#about to read 3, iclass 7, count 0 2006.189.07:51:20.05#ibcon#read 3, iclass 7, count 0 2006.189.07:51:20.05#ibcon#about to read 4, iclass 7, count 0 2006.189.07:51:20.05#ibcon#read 4, iclass 7, count 0 2006.189.07:51:20.05#ibcon#about to read 5, iclass 7, count 0 2006.189.07:51:20.05#ibcon#read 5, iclass 7, count 0 2006.189.07:51:20.05#ibcon#about to read 6, iclass 7, count 0 2006.189.07:51:20.05#ibcon#read 6, iclass 7, count 0 2006.189.07:51:20.05#ibcon#end of sib2, iclass 7, count 0 2006.189.07:51:20.05#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:51:20.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:51:20.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:51:20.05#ibcon#*before write, iclass 7, count 0 2006.189.07:51:20.05#ibcon#enter sib2, iclass 7, count 0 2006.189.07:51:20.05#ibcon#flushed, iclass 7, count 0 2006.189.07:51:20.05#ibcon#about to write, iclass 7, count 0 2006.189.07:51:20.05#ibcon#wrote, iclass 7, count 0 2006.189.07:51:20.05#ibcon#about to read 3, iclass 7, count 0 2006.189.07:51:20.09#ibcon#read 3, iclass 7, count 0 2006.189.07:51:20.09#ibcon#about to read 4, iclass 7, count 0 2006.189.07:51:20.09#ibcon#read 4, iclass 7, count 0 2006.189.07:51:20.09#ibcon#about to read 5, iclass 7, count 0 2006.189.07:51:20.09#ibcon#read 5, iclass 7, count 0 2006.189.07:51:20.09#ibcon#about to read 6, iclass 7, count 0 2006.189.07:51:20.09#ibcon#read 6, iclass 7, count 0 2006.189.07:51:20.09#ibcon#end of sib2, iclass 7, count 0 2006.189.07:51:20.09#ibcon#*after write, iclass 7, count 0 2006.189.07:51:20.09#ibcon#*before return 0, iclass 7, count 0 2006.189.07:51:20.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:20.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:20.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:51:20.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:51:20.09$vc4f8/va=7,6 2006.189.07:51:20.09#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:51:20.09#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:51:20.09#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:20.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:51:20.15#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:51:20.15#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:51:20.15#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:51:20.15#ibcon#first serial, iclass 11, count 2 2006.189.07:51:20.15#ibcon#enter sib2, iclass 11, count 2 2006.189.07:51:20.15#ibcon#flushed, iclass 11, count 2 2006.189.07:51:20.15#ibcon#about to write, iclass 11, count 2 2006.189.07:51:20.15#ibcon#wrote, iclass 11, count 2 2006.189.07:51:20.15#ibcon#about to read 3, iclass 11, count 2 2006.189.07:51:20.17#ibcon#read 3, iclass 11, count 2 2006.189.07:51:20.17#ibcon#about to read 4, iclass 11, count 2 2006.189.07:51:20.17#ibcon#read 4, iclass 11, count 2 2006.189.07:51:20.17#ibcon#about to read 5, iclass 11, count 2 2006.189.07:51:20.17#ibcon#read 5, iclass 11, count 2 2006.189.07:51:20.17#ibcon#about to read 6, iclass 11, count 2 2006.189.07:51:20.17#ibcon#read 6, iclass 11, count 2 2006.189.07:51:20.17#ibcon#end of sib2, iclass 11, count 2 2006.189.07:51:20.17#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:51:20.17#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:51:20.17#ibcon#[25=AT07-06\r\n] 2006.189.07:51:20.17#ibcon#*before write, iclass 11, count 2 2006.189.07:51:20.17#ibcon#enter sib2, iclass 11, count 2 2006.189.07:51:20.17#ibcon#flushed, iclass 11, count 2 2006.189.07:51:20.17#ibcon#about to write, iclass 11, count 2 2006.189.07:51:20.17#ibcon#wrote, iclass 11, count 2 2006.189.07:51:20.17#ibcon#about to read 3, iclass 11, count 2 2006.189.07:51:20.17#abcon#<5=/05 4.4 8.4 25.93 901009.1\r\n> 2006.189.07:51:20.19#abcon#{5=INTERFACE CLEAR} 2006.189.07:51:20.20#ibcon#read 3, iclass 11, count 2 2006.189.07:51:20.20#ibcon#about to read 4, iclass 11, count 2 2006.189.07:51:20.20#ibcon#read 4, iclass 11, count 2 2006.189.07:51:20.20#ibcon#about to read 5, iclass 11, count 2 2006.189.07:51:20.20#ibcon#read 5, iclass 11, count 2 2006.189.07:51:20.20#ibcon#about to read 6, iclass 11, count 2 2006.189.07:51:20.20#ibcon#read 6, iclass 11, count 2 2006.189.07:51:20.20#ibcon#end of sib2, iclass 11, count 2 2006.189.07:51:20.20#ibcon#*after write, iclass 11, count 2 2006.189.07:51:20.20#ibcon#*before return 0, iclass 11, count 2 2006.189.07:51:20.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:51:20.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:51:20.20#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:51:20.20#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:20.20#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:51:20.25#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:51:20.32#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:51:20.32#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:51:20.32#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:51:20.32#ibcon#first serial, iclass 11, count 0 2006.189.07:51:20.32#ibcon#enter sib2, iclass 11, count 0 2006.189.07:51:20.32#ibcon#flushed, iclass 11, count 0 2006.189.07:51:20.32#ibcon#about to write, iclass 11, count 0 2006.189.07:51:20.32#ibcon#wrote, iclass 11, count 0 2006.189.07:51:20.32#ibcon#about to read 3, iclass 11, count 0 2006.189.07:51:20.34#ibcon#read 3, iclass 11, count 0 2006.189.07:51:20.34#ibcon#about to read 4, iclass 11, count 0 2006.189.07:51:20.34#ibcon#read 4, iclass 11, count 0 2006.189.07:51:20.34#ibcon#about to read 5, iclass 11, count 0 2006.189.07:51:20.34#ibcon#read 5, iclass 11, count 0 2006.189.07:51:20.34#ibcon#about to read 6, iclass 11, count 0 2006.189.07:51:20.34#ibcon#read 6, iclass 11, count 0 2006.189.07:51:20.34#ibcon#end of sib2, iclass 11, count 0 2006.189.07:51:20.34#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:51:20.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:51:20.34#ibcon#[25=USB\r\n] 2006.189.07:51:20.34#ibcon#*before write, iclass 11, count 0 2006.189.07:51:20.34#ibcon#enter sib2, iclass 11, count 0 2006.189.07:51:20.34#ibcon#flushed, iclass 11, count 0 2006.189.07:51:20.34#ibcon#about to write, iclass 11, count 0 2006.189.07:51:20.34#ibcon#wrote, iclass 11, count 0 2006.189.07:51:20.34#ibcon#about to read 3, iclass 11, count 0 2006.189.07:51:20.37#ibcon#read 3, iclass 11, count 0 2006.189.07:51:20.37#ibcon#about to read 4, iclass 11, count 0 2006.189.07:51:20.37#ibcon#read 4, iclass 11, count 0 2006.189.07:51:20.37#ibcon#about to read 5, iclass 11, count 0 2006.189.07:51:20.37#ibcon#read 5, iclass 11, count 0 2006.189.07:51:20.37#ibcon#about to read 6, iclass 11, count 0 2006.189.07:51:20.37#ibcon#read 6, iclass 11, count 0 2006.189.07:51:20.37#ibcon#end of sib2, iclass 11, count 0 2006.189.07:51:20.37#ibcon#*after write, iclass 11, count 0 2006.189.07:51:20.37#ibcon#*before return 0, iclass 11, count 0 2006.189.07:51:20.37#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:51:20.37#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:51:20.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:51:20.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:51:20.37$vc4f8/valo=8,852.99 2006.189.07:51:20.37#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:51:20.37#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:51:20.37#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:20.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:51:20.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:51:20.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:51:20.37#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:51:20.37#ibcon#first serial, iclass 17, count 0 2006.189.07:51:20.37#ibcon#enter sib2, iclass 17, count 0 2006.189.07:51:20.37#ibcon#flushed, iclass 17, count 0 2006.189.07:51:20.37#ibcon#about to write, iclass 17, count 0 2006.189.07:51:20.37#ibcon#wrote, iclass 17, count 0 2006.189.07:51:20.37#ibcon#about to read 3, iclass 17, count 0 2006.189.07:51:20.39#ibcon#read 3, iclass 17, count 0 2006.189.07:51:20.39#ibcon#about to read 4, iclass 17, count 0 2006.189.07:51:20.39#ibcon#read 4, iclass 17, count 0 2006.189.07:51:20.39#ibcon#about to read 5, iclass 17, count 0 2006.189.07:51:20.39#ibcon#read 5, iclass 17, count 0 2006.189.07:51:20.39#ibcon#about to read 6, iclass 17, count 0 2006.189.07:51:20.39#ibcon#read 6, iclass 17, count 0 2006.189.07:51:20.39#ibcon#end of sib2, iclass 17, count 0 2006.189.07:51:20.39#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:51:20.39#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:51:20.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:51:20.39#ibcon#*before write, iclass 17, count 0 2006.189.07:51:20.39#ibcon#enter sib2, iclass 17, count 0 2006.189.07:51:20.39#ibcon#flushed, iclass 17, count 0 2006.189.07:51:20.39#ibcon#about to write, iclass 17, count 0 2006.189.07:51:20.39#ibcon#wrote, iclass 17, count 0 2006.189.07:51:20.39#ibcon#about to read 3, iclass 17, count 0 2006.189.07:51:20.43#ibcon#read 3, iclass 17, count 0 2006.189.07:51:20.43#ibcon#about to read 4, iclass 17, count 0 2006.189.07:51:20.43#ibcon#read 4, iclass 17, count 0 2006.189.07:51:20.43#ibcon#about to read 5, iclass 17, count 0 2006.189.07:51:20.43#ibcon#read 5, iclass 17, count 0 2006.189.07:51:20.43#ibcon#about to read 6, iclass 17, count 0 2006.189.07:51:20.43#ibcon#read 6, iclass 17, count 0 2006.189.07:51:20.43#ibcon#end of sib2, iclass 17, count 0 2006.189.07:51:20.43#ibcon#*after write, iclass 17, count 0 2006.189.07:51:20.43#ibcon#*before return 0, iclass 17, count 0 2006.189.07:51:20.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:51:20.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:51:20.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:51:20.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:51:20.43$vc4f8/va=8,6 2006.189.07:51:20.43#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.07:51:20.43#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.07:51:20.43#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:20.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:51:20.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:51:20.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:51:20.49#ibcon#enter wrdev, iclass 19, count 2 2006.189.07:51:20.49#ibcon#first serial, iclass 19, count 2 2006.189.07:51:20.49#ibcon#enter sib2, iclass 19, count 2 2006.189.07:51:20.49#ibcon#flushed, iclass 19, count 2 2006.189.07:51:20.49#ibcon#about to write, iclass 19, count 2 2006.189.07:51:20.49#ibcon#wrote, iclass 19, count 2 2006.189.07:51:20.49#ibcon#about to read 3, iclass 19, count 2 2006.189.07:51:20.51#ibcon#read 3, iclass 19, count 2 2006.189.07:51:20.51#ibcon#about to read 4, iclass 19, count 2 2006.189.07:51:20.51#ibcon#read 4, iclass 19, count 2 2006.189.07:51:20.51#ibcon#about to read 5, iclass 19, count 2 2006.189.07:51:20.51#ibcon#read 5, iclass 19, count 2 2006.189.07:51:20.51#ibcon#about to read 6, iclass 19, count 2 2006.189.07:51:20.51#ibcon#read 6, iclass 19, count 2 2006.189.07:51:20.51#ibcon#end of sib2, iclass 19, count 2 2006.189.07:51:20.51#ibcon#*mode == 0, iclass 19, count 2 2006.189.07:51:20.51#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.07:51:20.51#ibcon#[25=AT08-06\r\n] 2006.189.07:51:20.51#ibcon#*before write, iclass 19, count 2 2006.189.07:51:20.51#ibcon#enter sib2, iclass 19, count 2 2006.189.07:51:20.51#ibcon#flushed, iclass 19, count 2 2006.189.07:51:20.51#ibcon#about to write, iclass 19, count 2 2006.189.07:51:20.51#ibcon#wrote, iclass 19, count 2 2006.189.07:51:20.51#ibcon#about to read 3, iclass 19, count 2 2006.189.07:51:20.54#ibcon#read 3, iclass 19, count 2 2006.189.07:51:20.54#ibcon#about to read 4, iclass 19, count 2 2006.189.07:51:20.54#ibcon#read 4, iclass 19, count 2 2006.189.07:51:20.54#ibcon#about to read 5, iclass 19, count 2 2006.189.07:51:20.54#ibcon#read 5, iclass 19, count 2 2006.189.07:51:20.54#ibcon#about to read 6, iclass 19, count 2 2006.189.07:51:20.54#ibcon#read 6, iclass 19, count 2 2006.189.07:51:20.54#ibcon#end of sib2, iclass 19, count 2 2006.189.07:51:20.54#ibcon#*after write, iclass 19, count 2 2006.189.07:51:20.54#ibcon#*before return 0, iclass 19, count 2 2006.189.07:51:20.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:51:20.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:51:20.54#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.07:51:20.54#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:20.54#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:51:20.66#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:51:20.66#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:51:20.66#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:51:20.66#ibcon#first serial, iclass 19, count 0 2006.189.07:51:20.66#ibcon#enter sib2, iclass 19, count 0 2006.189.07:51:20.66#ibcon#flushed, iclass 19, count 0 2006.189.07:51:20.66#ibcon#about to write, iclass 19, count 0 2006.189.07:51:20.66#ibcon#wrote, iclass 19, count 0 2006.189.07:51:20.66#ibcon#about to read 3, iclass 19, count 0 2006.189.07:51:20.68#ibcon#read 3, iclass 19, count 0 2006.189.07:51:20.68#ibcon#about to read 4, iclass 19, count 0 2006.189.07:51:20.68#ibcon#read 4, iclass 19, count 0 2006.189.07:51:20.68#ibcon#about to read 5, iclass 19, count 0 2006.189.07:51:20.68#ibcon#read 5, iclass 19, count 0 2006.189.07:51:20.68#ibcon#about to read 6, iclass 19, count 0 2006.189.07:51:20.68#ibcon#read 6, iclass 19, count 0 2006.189.07:51:20.68#ibcon#end of sib2, iclass 19, count 0 2006.189.07:51:20.68#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:51:20.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:51:20.68#ibcon#[25=USB\r\n] 2006.189.07:51:20.68#ibcon#*before write, iclass 19, count 0 2006.189.07:51:20.68#ibcon#enter sib2, iclass 19, count 0 2006.189.07:51:20.68#ibcon#flushed, iclass 19, count 0 2006.189.07:51:20.68#ibcon#about to write, iclass 19, count 0 2006.189.07:51:20.68#ibcon#wrote, iclass 19, count 0 2006.189.07:51:20.68#ibcon#about to read 3, iclass 19, count 0 2006.189.07:51:20.71#ibcon#read 3, iclass 19, count 0 2006.189.07:51:20.71#ibcon#about to read 4, iclass 19, count 0 2006.189.07:51:20.71#ibcon#read 4, iclass 19, count 0 2006.189.07:51:20.71#ibcon#about to read 5, iclass 19, count 0 2006.189.07:51:20.71#ibcon#read 5, iclass 19, count 0 2006.189.07:51:20.71#ibcon#about to read 6, iclass 19, count 0 2006.189.07:51:20.71#ibcon#read 6, iclass 19, count 0 2006.189.07:51:20.71#ibcon#end of sib2, iclass 19, count 0 2006.189.07:51:20.71#ibcon#*after write, iclass 19, count 0 2006.189.07:51:20.71#ibcon#*before return 0, iclass 19, count 0 2006.189.07:51:20.71#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:51:20.71#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:51:20.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:51:20.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:51:20.71$vc4f8/vblo=1,632.99 2006.189.07:51:20.71#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:51:20.71#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:51:20.71#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:20.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:20.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:20.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:20.71#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:51:20.71#ibcon#first serial, iclass 21, count 0 2006.189.07:51:20.71#ibcon#enter sib2, iclass 21, count 0 2006.189.07:51:20.71#ibcon#flushed, iclass 21, count 0 2006.189.07:51:20.71#ibcon#about to write, iclass 21, count 0 2006.189.07:51:20.71#ibcon#wrote, iclass 21, count 0 2006.189.07:51:20.71#ibcon#about to read 3, iclass 21, count 0 2006.189.07:51:20.73#ibcon#read 3, iclass 21, count 0 2006.189.07:51:20.73#ibcon#about to read 4, iclass 21, count 0 2006.189.07:51:20.73#ibcon#read 4, iclass 21, count 0 2006.189.07:51:20.73#ibcon#about to read 5, iclass 21, count 0 2006.189.07:51:20.73#ibcon#read 5, iclass 21, count 0 2006.189.07:51:20.73#ibcon#about to read 6, iclass 21, count 0 2006.189.07:51:20.73#ibcon#read 6, iclass 21, count 0 2006.189.07:51:20.73#ibcon#end of sib2, iclass 21, count 0 2006.189.07:51:20.73#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:51:20.73#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:51:20.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:51:20.73#ibcon#*before write, iclass 21, count 0 2006.189.07:51:20.73#ibcon#enter sib2, iclass 21, count 0 2006.189.07:51:20.73#ibcon#flushed, iclass 21, count 0 2006.189.07:51:20.73#ibcon#about to write, iclass 21, count 0 2006.189.07:51:20.73#ibcon#wrote, iclass 21, count 0 2006.189.07:51:20.73#ibcon#about to read 3, iclass 21, count 0 2006.189.07:51:20.77#ibcon#read 3, iclass 21, count 0 2006.189.07:51:20.77#ibcon#about to read 4, iclass 21, count 0 2006.189.07:51:20.77#ibcon#read 4, iclass 21, count 0 2006.189.07:51:20.77#ibcon#about to read 5, iclass 21, count 0 2006.189.07:51:20.77#ibcon#read 5, iclass 21, count 0 2006.189.07:51:20.77#ibcon#about to read 6, iclass 21, count 0 2006.189.07:51:20.77#ibcon#read 6, iclass 21, count 0 2006.189.07:51:20.77#ibcon#end of sib2, iclass 21, count 0 2006.189.07:51:20.77#ibcon#*after write, iclass 21, count 0 2006.189.07:51:20.77#ibcon#*before return 0, iclass 21, count 0 2006.189.07:51:20.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:20.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:51:20.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:51:20.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:51:20.77$vc4f8/vb=1,4 2006.189.07:51:20.77#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:51:20.77#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:51:20.77#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:20.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:20.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:20.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:20.77#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:51:20.77#ibcon#first serial, iclass 23, count 2 2006.189.07:51:20.77#ibcon#enter sib2, iclass 23, count 2 2006.189.07:51:20.77#ibcon#flushed, iclass 23, count 2 2006.189.07:51:20.77#ibcon#about to write, iclass 23, count 2 2006.189.07:51:20.77#ibcon#wrote, iclass 23, count 2 2006.189.07:51:20.77#ibcon#about to read 3, iclass 23, count 2 2006.189.07:51:20.79#ibcon#read 3, iclass 23, count 2 2006.189.07:51:20.79#ibcon#about to read 4, iclass 23, count 2 2006.189.07:51:20.79#ibcon#read 4, iclass 23, count 2 2006.189.07:51:20.79#ibcon#about to read 5, iclass 23, count 2 2006.189.07:51:20.79#ibcon#read 5, iclass 23, count 2 2006.189.07:51:20.79#ibcon#about to read 6, iclass 23, count 2 2006.189.07:51:20.79#ibcon#read 6, iclass 23, count 2 2006.189.07:51:20.79#ibcon#end of sib2, iclass 23, count 2 2006.189.07:51:20.79#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:51:20.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:51:20.79#ibcon#[27=AT01-04\r\n] 2006.189.07:51:20.79#ibcon#*before write, iclass 23, count 2 2006.189.07:51:20.79#ibcon#enter sib2, iclass 23, count 2 2006.189.07:51:20.79#ibcon#flushed, iclass 23, count 2 2006.189.07:51:20.79#ibcon#about to write, iclass 23, count 2 2006.189.07:51:20.79#ibcon#wrote, iclass 23, count 2 2006.189.07:51:20.79#ibcon#about to read 3, iclass 23, count 2 2006.189.07:51:20.82#ibcon#read 3, iclass 23, count 2 2006.189.07:51:20.82#ibcon#about to read 4, iclass 23, count 2 2006.189.07:51:20.82#ibcon#read 4, iclass 23, count 2 2006.189.07:51:20.82#ibcon#about to read 5, iclass 23, count 2 2006.189.07:51:20.82#ibcon#read 5, iclass 23, count 2 2006.189.07:51:20.82#ibcon#about to read 6, iclass 23, count 2 2006.189.07:51:20.82#ibcon#read 6, iclass 23, count 2 2006.189.07:51:20.82#ibcon#end of sib2, iclass 23, count 2 2006.189.07:51:20.82#ibcon#*after write, iclass 23, count 2 2006.189.07:51:20.82#ibcon#*before return 0, iclass 23, count 2 2006.189.07:51:20.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:20.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:51:20.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:51:20.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:20.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:20.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:20.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:20.94#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:51:20.94#ibcon#first serial, iclass 23, count 0 2006.189.07:51:20.94#ibcon#enter sib2, iclass 23, count 0 2006.189.07:51:20.94#ibcon#flushed, iclass 23, count 0 2006.189.07:51:20.94#ibcon#about to write, iclass 23, count 0 2006.189.07:51:20.94#ibcon#wrote, iclass 23, count 0 2006.189.07:51:20.94#ibcon#about to read 3, iclass 23, count 0 2006.189.07:51:20.96#ibcon#read 3, iclass 23, count 0 2006.189.07:51:20.96#ibcon#about to read 4, iclass 23, count 0 2006.189.07:51:20.96#ibcon#read 4, iclass 23, count 0 2006.189.07:51:20.96#ibcon#about to read 5, iclass 23, count 0 2006.189.07:51:20.96#ibcon#read 5, iclass 23, count 0 2006.189.07:51:20.96#ibcon#about to read 6, iclass 23, count 0 2006.189.07:51:20.96#ibcon#read 6, iclass 23, count 0 2006.189.07:51:20.96#ibcon#end of sib2, iclass 23, count 0 2006.189.07:51:20.96#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:51:20.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:51:20.96#ibcon#[27=USB\r\n] 2006.189.07:51:20.96#ibcon#*before write, iclass 23, count 0 2006.189.07:51:20.96#ibcon#enter sib2, iclass 23, count 0 2006.189.07:51:20.96#ibcon#flushed, iclass 23, count 0 2006.189.07:51:20.96#ibcon#about to write, iclass 23, count 0 2006.189.07:51:20.96#ibcon#wrote, iclass 23, count 0 2006.189.07:51:20.96#ibcon#about to read 3, iclass 23, count 0 2006.189.07:51:20.99#ibcon#read 3, iclass 23, count 0 2006.189.07:51:20.99#ibcon#about to read 4, iclass 23, count 0 2006.189.07:51:20.99#ibcon#read 4, iclass 23, count 0 2006.189.07:51:20.99#ibcon#about to read 5, iclass 23, count 0 2006.189.07:51:20.99#ibcon#read 5, iclass 23, count 0 2006.189.07:51:20.99#ibcon#about to read 6, iclass 23, count 0 2006.189.07:51:20.99#ibcon#read 6, iclass 23, count 0 2006.189.07:51:20.99#ibcon#end of sib2, iclass 23, count 0 2006.189.07:51:20.99#ibcon#*after write, iclass 23, count 0 2006.189.07:51:20.99#ibcon#*before return 0, iclass 23, count 0 2006.189.07:51:20.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:20.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:51:20.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:51:20.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:51:20.99$vc4f8/vblo=2,640.99 2006.189.07:51:20.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:51:20.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:51:20.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:20.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:20.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:20.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:20.99#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:51:20.99#ibcon#first serial, iclass 25, count 0 2006.189.07:51:20.99#ibcon#enter sib2, iclass 25, count 0 2006.189.07:51:20.99#ibcon#flushed, iclass 25, count 0 2006.189.07:51:20.99#ibcon#about to write, iclass 25, count 0 2006.189.07:51:20.99#ibcon#wrote, iclass 25, count 0 2006.189.07:51:20.99#ibcon#about to read 3, iclass 25, count 0 2006.189.07:51:21.01#ibcon#read 3, iclass 25, count 0 2006.189.07:51:21.01#ibcon#about to read 4, iclass 25, count 0 2006.189.07:51:21.01#ibcon#read 4, iclass 25, count 0 2006.189.07:51:21.01#ibcon#about to read 5, iclass 25, count 0 2006.189.07:51:21.01#ibcon#read 5, iclass 25, count 0 2006.189.07:51:21.01#ibcon#about to read 6, iclass 25, count 0 2006.189.07:51:21.01#ibcon#read 6, iclass 25, count 0 2006.189.07:51:21.01#ibcon#end of sib2, iclass 25, count 0 2006.189.07:51:21.01#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:51:21.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:51:21.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:51:21.01#ibcon#*before write, iclass 25, count 0 2006.189.07:51:21.01#ibcon#enter sib2, iclass 25, count 0 2006.189.07:51:21.01#ibcon#flushed, iclass 25, count 0 2006.189.07:51:21.01#ibcon#about to write, iclass 25, count 0 2006.189.07:51:21.01#ibcon#wrote, iclass 25, count 0 2006.189.07:51:21.01#ibcon#about to read 3, iclass 25, count 0 2006.189.07:51:21.05#ibcon#read 3, iclass 25, count 0 2006.189.07:51:21.05#ibcon#about to read 4, iclass 25, count 0 2006.189.07:51:21.05#ibcon#read 4, iclass 25, count 0 2006.189.07:51:21.05#ibcon#about to read 5, iclass 25, count 0 2006.189.07:51:21.05#ibcon#read 5, iclass 25, count 0 2006.189.07:51:21.05#ibcon#about to read 6, iclass 25, count 0 2006.189.07:51:21.05#ibcon#read 6, iclass 25, count 0 2006.189.07:51:21.05#ibcon#end of sib2, iclass 25, count 0 2006.189.07:51:21.05#ibcon#*after write, iclass 25, count 0 2006.189.07:51:21.05#ibcon#*before return 0, iclass 25, count 0 2006.189.07:51:21.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:21.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:51:21.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:51:21.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:51:21.05$vc4f8/vb=2,4 2006.189.07:51:21.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:51:21.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:51:21.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:21.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:21.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:21.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:21.11#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:51:21.11#ibcon#first serial, iclass 27, count 2 2006.189.07:51:21.11#ibcon#enter sib2, iclass 27, count 2 2006.189.07:51:21.11#ibcon#flushed, iclass 27, count 2 2006.189.07:51:21.11#ibcon#about to write, iclass 27, count 2 2006.189.07:51:21.11#ibcon#wrote, iclass 27, count 2 2006.189.07:51:21.11#ibcon#about to read 3, iclass 27, count 2 2006.189.07:51:21.13#ibcon#read 3, iclass 27, count 2 2006.189.07:51:21.13#ibcon#about to read 4, iclass 27, count 2 2006.189.07:51:21.13#ibcon#read 4, iclass 27, count 2 2006.189.07:51:21.13#ibcon#about to read 5, iclass 27, count 2 2006.189.07:51:21.13#ibcon#read 5, iclass 27, count 2 2006.189.07:51:21.13#ibcon#about to read 6, iclass 27, count 2 2006.189.07:51:21.13#ibcon#read 6, iclass 27, count 2 2006.189.07:51:21.13#ibcon#end of sib2, iclass 27, count 2 2006.189.07:51:21.13#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:51:21.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:51:21.13#ibcon#[27=AT02-04\r\n] 2006.189.07:51:21.13#ibcon#*before write, iclass 27, count 2 2006.189.07:51:21.13#ibcon#enter sib2, iclass 27, count 2 2006.189.07:51:21.13#ibcon#flushed, iclass 27, count 2 2006.189.07:51:21.13#ibcon#about to write, iclass 27, count 2 2006.189.07:51:21.13#ibcon#wrote, iclass 27, count 2 2006.189.07:51:21.13#ibcon#about to read 3, iclass 27, count 2 2006.189.07:51:21.16#ibcon#read 3, iclass 27, count 2 2006.189.07:51:21.16#ibcon#about to read 4, iclass 27, count 2 2006.189.07:51:21.16#ibcon#read 4, iclass 27, count 2 2006.189.07:51:21.16#ibcon#about to read 5, iclass 27, count 2 2006.189.07:51:21.16#ibcon#read 5, iclass 27, count 2 2006.189.07:51:21.16#ibcon#about to read 6, iclass 27, count 2 2006.189.07:51:21.16#ibcon#read 6, iclass 27, count 2 2006.189.07:51:21.16#ibcon#end of sib2, iclass 27, count 2 2006.189.07:51:21.16#ibcon#*after write, iclass 27, count 2 2006.189.07:51:21.16#ibcon#*before return 0, iclass 27, count 2 2006.189.07:51:21.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:21.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:51:21.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:51:21.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:21.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:21.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:21.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:21.28#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:51:21.28#ibcon#first serial, iclass 27, count 0 2006.189.07:51:21.28#ibcon#enter sib2, iclass 27, count 0 2006.189.07:51:21.28#ibcon#flushed, iclass 27, count 0 2006.189.07:51:21.28#ibcon#about to write, iclass 27, count 0 2006.189.07:51:21.28#ibcon#wrote, iclass 27, count 0 2006.189.07:51:21.28#ibcon#about to read 3, iclass 27, count 0 2006.189.07:51:21.30#ibcon#read 3, iclass 27, count 0 2006.189.07:51:21.30#ibcon#about to read 4, iclass 27, count 0 2006.189.07:51:21.30#ibcon#read 4, iclass 27, count 0 2006.189.07:51:21.30#ibcon#about to read 5, iclass 27, count 0 2006.189.07:51:21.30#ibcon#read 5, iclass 27, count 0 2006.189.07:51:21.30#ibcon#about to read 6, iclass 27, count 0 2006.189.07:51:21.30#ibcon#read 6, iclass 27, count 0 2006.189.07:51:21.30#ibcon#end of sib2, iclass 27, count 0 2006.189.07:51:21.30#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:51:21.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:51:21.30#ibcon#[27=USB\r\n] 2006.189.07:51:21.30#ibcon#*before write, iclass 27, count 0 2006.189.07:51:21.30#ibcon#enter sib2, iclass 27, count 0 2006.189.07:51:21.30#ibcon#flushed, iclass 27, count 0 2006.189.07:51:21.30#ibcon#about to write, iclass 27, count 0 2006.189.07:51:21.30#ibcon#wrote, iclass 27, count 0 2006.189.07:51:21.30#ibcon#about to read 3, iclass 27, count 0 2006.189.07:51:21.33#ibcon#read 3, iclass 27, count 0 2006.189.07:51:21.33#ibcon#about to read 4, iclass 27, count 0 2006.189.07:51:21.33#ibcon#read 4, iclass 27, count 0 2006.189.07:51:21.33#ibcon#about to read 5, iclass 27, count 0 2006.189.07:51:21.33#ibcon#read 5, iclass 27, count 0 2006.189.07:51:21.33#ibcon#about to read 6, iclass 27, count 0 2006.189.07:51:21.33#ibcon#read 6, iclass 27, count 0 2006.189.07:51:21.33#ibcon#end of sib2, iclass 27, count 0 2006.189.07:51:21.33#ibcon#*after write, iclass 27, count 0 2006.189.07:51:21.33#ibcon#*before return 0, iclass 27, count 0 2006.189.07:51:21.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:21.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:51:21.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:51:21.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:51:21.33$vc4f8/vblo=3,656.99 2006.189.07:51:21.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:51:21.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:51:21.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:21.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:21.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:21.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:21.33#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:51:21.33#ibcon#first serial, iclass 29, count 0 2006.189.07:51:21.33#ibcon#enter sib2, iclass 29, count 0 2006.189.07:51:21.33#ibcon#flushed, iclass 29, count 0 2006.189.07:51:21.33#ibcon#about to write, iclass 29, count 0 2006.189.07:51:21.33#ibcon#wrote, iclass 29, count 0 2006.189.07:51:21.33#ibcon#about to read 3, iclass 29, count 0 2006.189.07:51:21.35#ibcon#read 3, iclass 29, count 0 2006.189.07:51:21.35#ibcon#about to read 4, iclass 29, count 0 2006.189.07:51:21.35#ibcon#read 4, iclass 29, count 0 2006.189.07:51:21.35#ibcon#about to read 5, iclass 29, count 0 2006.189.07:51:21.35#ibcon#read 5, iclass 29, count 0 2006.189.07:51:21.35#ibcon#about to read 6, iclass 29, count 0 2006.189.07:51:21.35#ibcon#read 6, iclass 29, count 0 2006.189.07:51:21.35#ibcon#end of sib2, iclass 29, count 0 2006.189.07:51:21.35#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:51:21.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:51:21.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:51:21.35#ibcon#*before write, iclass 29, count 0 2006.189.07:51:21.35#ibcon#enter sib2, iclass 29, count 0 2006.189.07:51:21.35#ibcon#flushed, iclass 29, count 0 2006.189.07:51:21.35#ibcon#about to write, iclass 29, count 0 2006.189.07:51:21.35#ibcon#wrote, iclass 29, count 0 2006.189.07:51:21.35#ibcon#about to read 3, iclass 29, count 0 2006.189.07:51:21.39#ibcon#read 3, iclass 29, count 0 2006.189.07:51:21.39#ibcon#about to read 4, iclass 29, count 0 2006.189.07:51:21.39#ibcon#read 4, iclass 29, count 0 2006.189.07:51:21.39#ibcon#about to read 5, iclass 29, count 0 2006.189.07:51:21.39#ibcon#read 5, iclass 29, count 0 2006.189.07:51:21.39#ibcon#about to read 6, iclass 29, count 0 2006.189.07:51:21.39#ibcon#read 6, iclass 29, count 0 2006.189.07:51:21.39#ibcon#end of sib2, iclass 29, count 0 2006.189.07:51:21.39#ibcon#*after write, iclass 29, count 0 2006.189.07:51:21.39#ibcon#*before return 0, iclass 29, count 0 2006.189.07:51:21.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:21.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:51:21.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:51:21.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:51:21.39$vc4f8/vb=3,4 2006.189.07:51:21.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.07:51:21.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.07:51:21.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:21.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:21.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:21.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:21.45#ibcon#enter wrdev, iclass 31, count 2 2006.189.07:51:21.45#ibcon#first serial, iclass 31, count 2 2006.189.07:51:21.45#ibcon#enter sib2, iclass 31, count 2 2006.189.07:51:21.45#ibcon#flushed, iclass 31, count 2 2006.189.07:51:21.45#ibcon#about to write, iclass 31, count 2 2006.189.07:51:21.45#ibcon#wrote, iclass 31, count 2 2006.189.07:51:21.45#ibcon#about to read 3, iclass 31, count 2 2006.189.07:51:21.47#ibcon#read 3, iclass 31, count 2 2006.189.07:51:21.47#ibcon#about to read 4, iclass 31, count 2 2006.189.07:51:21.47#ibcon#read 4, iclass 31, count 2 2006.189.07:51:21.47#ibcon#about to read 5, iclass 31, count 2 2006.189.07:51:21.47#ibcon#read 5, iclass 31, count 2 2006.189.07:51:21.47#ibcon#about to read 6, iclass 31, count 2 2006.189.07:51:21.47#ibcon#read 6, iclass 31, count 2 2006.189.07:51:21.47#ibcon#end of sib2, iclass 31, count 2 2006.189.07:51:21.47#ibcon#*mode == 0, iclass 31, count 2 2006.189.07:51:21.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.07:51:21.47#ibcon#[27=AT03-04\r\n] 2006.189.07:51:21.47#ibcon#*before write, iclass 31, count 2 2006.189.07:51:21.47#ibcon#enter sib2, iclass 31, count 2 2006.189.07:51:21.47#ibcon#flushed, iclass 31, count 2 2006.189.07:51:21.47#ibcon#about to write, iclass 31, count 2 2006.189.07:51:21.47#ibcon#wrote, iclass 31, count 2 2006.189.07:51:21.47#ibcon#about to read 3, iclass 31, count 2 2006.189.07:51:21.50#ibcon#read 3, iclass 31, count 2 2006.189.07:51:21.50#ibcon#about to read 4, iclass 31, count 2 2006.189.07:51:21.50#ibcon#read 4, iclass 31, count 2 2006.189.07:51:21.50#ibcon#about to read 5, iclass 31, count 2 2006.189.07:51:21.50#ibcon#read 5, iclass 31, count 2 2006.189.07:51:21.50#ibcon#about to read 6, iclass 31, count 2 2006.189.07:51:21.50#ibcon#read 6, iclass 31, count 2 2006.189.07:51:21.50#ibcon#end of sib2, iclass 31, count 2 2006.189.07:51:21.50#ibcon#*after write, iclass 31, count 2 2006.189.07:51:21.50#ibcon#*before return 0, iclass 31, count 2 2006.189.07:51:21.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:21.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:51:21.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.07:51:21.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:21.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:21.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:21.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:21.62#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:51:21.62#ibcon#first serial, iclass 31, count 0 2006.189.07:51:21.62#ibcon#enter sib2, iclass 31, count 0 2006.189.07:51:21.62#ibcon#flushed, iclass 31, count 0 2006.189.07:51:21.62#ibcon#about to write, iclass 31, count 0 2006.189.07:51:21.62#ibcon#wrote, iclass 31, count 0 2006.189.07:51:21.62#ibcon#about to read 3, iclass 31, count 0 2006.189.07:51:21.64#ibcon#read 3, iclass 31, count 0 2006.189.07:51:21.64#ibcon#about to read 4, iclass 31, count 0 2006.189.07:51:21.64#ibcon#read 4, iclass 31, count 0 2006.189.07:51:21.64#ibcon#about to read 5, iclass 31, count 0 2006.189.07:51:21.64#ibcon#read 5, iclass 31, count 0 2006.189.07:51:21.64#ibcon#about to read 6, iclass 31, count 0 2006.189.07:51:21.64#ibcon#read 6, iclass 31, count 0 2006.189.07:51:21.64#ibcon#end of sib2, iclass 31, count 0 2006.189.07:51:21.64#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:51:21.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:51:21.64#ibcon#[27=USB\r\n] 2006.189.07:51:21.64#ibcon#*before write, iclass 31, count 0 2006.189.07:51:21.64#ibcon#enter sib2, iclass 31, count 0 2006.189.07:51:21.64#ibcon#flushed, iclass 31, count 0 2006.189.07:51:21.64#ibcon#about to write, iclass 31, count 0 2006.189.07:51:21.64#ibcon#wrote, iclass 31, count 0 2006.189.07:51:21.64#ibcon#about to read 3, iclass 31, count 0 2006.189.07:51:21.67#ibcon#read 3, iclass 31, count 0 2006.189.07:51:21.67#ibcon#about to read 4, iclass 31, count 0 2006.189.07:51:21.67#ibcon#read 4, iclass 31, count 0 2006.189.07:51:21.67#ibcon#about to read 5, iclass 31, count 0 2006.189.07:51:21.67#ibcon#read 5, iclass 31, count 0 2006.189.07:51:21.67#ibcon#about to read 6, iclass 31, count 0 2006.189.07:51:21.67#ibcon#read 6, iclass 31, count 0 2006.189.07:51:21.67#ibcon#end of sib2, iclass 31, count 0 2006.189.07:51:21.67#ibcon#*after write, iclass 31, count 0 2006.189.07:51:21.67#ibcon#*before return 0, iclass 31, count 0 2006.189.07:51:21.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:21.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:51:21.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:51:21.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:51:21.67$vc4f8/vblo=4,712.99 2006.189.07:51:21.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:51:21.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:51:21.67#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:21.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:21.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:21.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:21.67#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:51:21.67#ibcon#first serial, iclass 33, count 0 2006.189.07:51:21.67#ibcon#enter sib2, iclass 33, count 0 2006.189.07:51:21.67#ibcon#flushed, iclass 33, count 0 2006.189.07:51:21.67#ibcon#about to write, iclass 33, count 0 2006.189.07:51:21.67#ibcon#wrote, iclass 33, count 0 2006.189.07:51:21.67#ibcon#about to read 3, iclass 33, count 0 2006.189.07:51:21.69#ibcon#read 3, iclass 33, count 0 2006.189.07:51:21.69#ibcon#about to read 4, iclass 33, count 0 2006.189.07:51:21.69#ibcon#read 4, iclass 33, count 0 2006.189.07:51:21.69#ibcon#about to read 5, iclass 33, count 0 2006.189.07:51:21.69#ibcon#read 5, iclass 33, count 0 2006.189.07:51:21.69#ibcon#about to read 6, iclass 33, count 0 2006.189.07:51:21.69#ibcon#read 6, iclass 33, count 0 2006.189.07:51:21.69#ibcon#end of sib2, iclass 33, count 0 2006.189.07:51:21.69#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:51:21.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:51:21.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:51:21.69#ibcon#*before write, iclass 33, count 0 2006.189.07:51:21.69#ibcon#enter sib2, iclass 33, count 0 2006.189.07:51:21.69#ibcon#flushed, iclass 33, count 0 2006.189.07:51:21.69#ibcon#about to write, iclass 33, count 0 2006.189.07:51:21.69#ibcon#wrote, iclass 33, count 0 2006.189.07:51:21.69#ibcon#about to read 3, iclass 33, count 0 2006.189.07:51:21.73#ibcon#read 3, iclass 33, count 0 2006.189.07:51:21.73#ibcon#about to read 4, iclass 33, count 0 2006.189.07:51:21.73#ibcon#read 4, iclass 33, count 0 2006.189.07:51:21.73#ibcon#about to read 5, iclass 33, count 0 2006.189.07:51:21.73#ibcon#read 5, iclass 33, count 0 2006.189.07:51:21.73#ibcon#about to read 6, iclass 33, count 0 2006.189.07:51:21.73#ibcon#read 6, iclass 33, count 0 2006.189.07:51:21.73#ibcon#end of sib2, iclass 33, count 0 2006.189.07:51:21.73#ibcon#*after write, iclass 33, count 0 2006.189.07:51:21.73#ibcon#*before return 0, iclass 33, count 0 2006.189.07:51:21.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:21.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:51:21.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:51:21.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:51:21.73$vc4f8/vb=4,4 2006.189.07:51:21.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:51:21.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:51:21.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:21.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:21.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:21.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:21.79#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:51:21.79#ibcon#first serial, iclass 35, count 2 2006.189.07:51:21.79#ibcon#enter sib2, iclass 35, count 2 2006.189.07:51:21.79#ibcon#flushed, iclass 35, count 2 2006.189.07:51:21.79#ibcon#about to write, iclass 35, count 2 2006.189.07:51:21.79#ibcon#wrote, iclass 35, count 2 2006.189.07:51:21.79#ibcon#about to read 3, iclass 35, count 2 2006.189.07:51:21.81#ibcon#read 3, iclass 35, count 2 2006.189.07:51:21.81#ibcon#about to read 4, iclass 35, count 2 2006.189.07:51:21.81#ibcon#read 4, iclass 35, count 2 2006.189.07:51:21.81#ibcon#about to read 5, iclass 35, count 2 2006.189.07:51:21.81#ibcon#read 5, iclass 35, count 2 2006.189.07:51:21.81#ibcon#about to read 6, iclass 35, count 2 2006.189.07:51:21.81#ibcon#read 6, iclass 35, count 2 2006.189.07:51:21.81#ibcon#end of sib2, iclass 35, count 2 2006.189.07:51:21.81#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:51:21.81#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:51:21.81#ibcon#[27=AT04-04\r\n] 2006.189.07:51:21.81#ibcon#*before write, iclass 35, count 2 2006.189.07:51:21.81#ibcon#enter sib2, iclass 35, count 2 2006.189.07:51:21.81#ibcon#flushed, iclass 35, count 2 2006.189.07:51:21.81#ibcon#about to write, iclass 35, count 2 2006.189.07:51:21.81#ibcon#wrote, iclass 35, count 2 2006.189.07:51:21.81#ibcon#about to read 3, iclass 35, count 2 2006.189.07:51:21.84#ibcon#read 3, iclass 35, count 2 2006.189.07:51:21.84#ibcon#about to read 4, iclass 35, count 2 2006.189.07:51:21.84#ibcon#read 4, iclass 35, count 2 2006.189.07:51:21.84#ibcon#about to read 5, iclass 35, count 2 2006.189.07:51:21.84#ibcon#read 5, iclass 35, count 2 2006.189.07:51:21.84#ibcon#about to read 6, iclass 35, count 2 2006.189.07:51:21.84#ibcon#read 6, iclass 35, count 2 2006.189.07:51:21.84#ibcon#end of sib2, iclass 35, count 2 2006.189.07:51:21.84#ibcon#*after write, iclass 35, count 2 2006.189.07:51:21.84#ibcon#*before return 0, iclass 35, count 2 2006.189.07:51:21.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:21.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:51:21.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:51:21.84#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:21.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:21.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:21.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:21.96#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:51:21.96#ibcon#first serial, iclass 35, count 0 2006.189.07:51:21.96#ibcon#enter sib2, iclass 35, count 0 2006.189.07:51:21.96#ibcon#flushed, iclass 35, count 0 2006.189.07:51:21.96#ibcon#about to write, iclass 35, count 0 2006.189.07:51:21.96#ibcon#wrote, iclass 35, count 0 2006.189.07:51:21.96#ibcon#about to read 3, iclass 35, count 0 2006.189.07:51:21.98#ibcon#read 3, iclass 35, count 0 2006.189.07:51:21.98#ibcon#about to read 4, iclass 35, count 0 2006.189.07:51:21.98#ibcon#read 4, iclass 35, count 0 2006.189.07:51:21.98#ibcon#about to read 5, iclass 35, count 0 2006.189.07:51:21.98#ibcon#read 5, iclass 35, count 0 2006.189.07:51:21.98#ibcon#about to read 6, iclass 35, count 0 2006.189.07:51:21.98#ibcon#read 6, iclass 35, count 0 2006.189.07:51:21.98#ibcon#end of sib2, iclass 35, count 0 2006.189.07:51:21.98#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:51:21.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:51:21.98#ibcon#[27=USB\r\n] 2006.189.07:51:21.98#ibcon#*before write, iclass 35, count 0 2006.189.07:51:21.98#ibcon#enter sib2, iclass 35, count 0 2006.189.07:51:21.98#ibcon#flushed, iclass 35, count 0 2006.189.07:51:21.98#ibcon#about to write, iclass 35, count 0 2006.189.07:51:21.98#ibcon#wrote, iclass 35, count 0 2006.189.07:51:21.98#ibcon#about to read 3, iclass 35, count 0 2006.189.07:51:22.01#ibcon#read 3, iclass 35, count 0 2006.189.07:51:22.01#ibcon#about to read 4, iclass 35, count 0 2006.189.07:51:22.01#ibcon#read 4, iclass 35, count 0 2006.189.07:51:22.01#ibcon#about to read 5, iclass 35, count 0 2006.189.07:51:22.01#ibcon#read 5, iclass 35, count 0 2006.189.07:51:22.01#ibcon#about to read 6, iclass 35, count 0 2006.189.07:51:22.01#ibcon#read 6, iclass 35, count 0 2006.189.07:51:22.01#ibcon#end of sib2, iclass 35, count 0 2006.189.07:51:22.01#ibcon#*after write, iclass 35, count 0 2006.189.07:51:22.01#ibcon#*before return 0, iclass 35, count 0 2006.189.07:51:22.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:22.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:51:22.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:51:22.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:51:22.01$vc4f8/vblo=5,744.99 2006.189.07:51:22.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:51:22.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:51:22.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:22.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:22.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:22.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:22.01#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:51:22.01#ibcon#first serial, iclass 37, count 0 2006.189.07:51:22.01#ibcon#enter sib2, iclass 37, count 0 2006.189.07:51:22.01#ibcon#flushed, iclass 37, count 0 2006.189.07:51:22.01#ibcon#about to write, iclass 37, count 0 2006.189.07:51:22.01#ibcon#wrote, iclass 37, count 0 2006.189.07:51:22.01#ibcon#about to read 3, iclass 37, count 0 2006.189.07:51:22.03#ibcon#read 3, iclass 37, count 0 2006.189.07:51:22.03#ibcon#about to read 4, iclass 37, count 0 2006.189.07:51:22.03#ibcon#read 4, iclass 37, count 0 2006.189.07:51:22.03#ibcon#about to read 5, iclass 37, count 0 2006.189.07:51:22.03#ibcon#read 5, iclass 37, count 0 2006.189.07:51:22.03#ibcon#about to read 6, iclass 37, count 0 2006.189.07:51:22.03#ibcon#read 6, iclass 37, count 0 2006.189.07:51:22.03#ibcon#end of sib2, iclass 37, count 0 2006.189.07:51:22.03#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:51:22.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:51:22.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:51:22.03#ibcon#*before write, iclass 37, count 0 2006.189.07:51:22.03#ibcon#enter sib2, iclass 37, count 0 2006.189.07:51:22.03#ibcon#flushed, iclass 37, count 0 2006.189.07:51:22.03#ibcon#about to write, iclass 37, count 0 2006.189.07:51:22.03#ibcon#wrote, iclass 37, count 0 2006.189.07:51:22.03#ibcon#about to read 3, iclass 37, count 0 2006.189.07:51:22.07#ibcon#read 3, iclass 37, count 0 2006.189.07:51:22.07#ibcon#about to read 4, iclass 37, count 0 2006.189.07:51:22.07#ibcon#read 4, iclass 37, count 0 2006.189.07:51:22.07#ibcon#about to read 5, iclass 37, count 0 2006.189.07:51:22.07#ibcon#read 5, iclass 37, count 0 2006.189.07:51:22.07#ibcon#about to read 6, iclass 37, count 0 2006.189.07:51:22.07#ibcon#read 6, iclass 37, count 0 2006.189.07:51:22.07#ibcon#end of sib2, iclass 37, count 0 2006.189.07:51:22.07#ibcon#*after write, iclass 37, count 0 2006.189.07:51:22.07#ibcon#*before return 0, iclass 37, count 0 2006.189.07:51:22.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:22.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:51:22.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:51:22.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:51:22.07$vc4f8/vb=5,4 2006.189.07:51:22.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:51:22.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:51:22.07#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:22.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:22.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:22.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:22.13#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:51:22.13#ibcon#first serial, iclass 39, count 2 2006.189.07:51:22.13#ibcon#enter sib2, iclass 39, count 2 2006.189.07:51:22.13#ibcon#flushed, iclass 39, count 2 2006.189.07:51:22.13#ibcon#about to write, iclass 39, count 2 2006.189.07:51:22.13#ibcon#wrote, iclass 39, count 2 2006.189.07:51:22.13#ibcon#about to read 3, iclass 39, count 2 2006.189.07:51:22.15#ibcon#read 3, iclass 39, count 2 2006.189.07:51:22.15#ibcon#about to read 4, iclass 39, count 2 2006.189.07:51:22.15#ibcon#read 4, iclass 39, count 2 2006.189.07:51:22.15#ibcon#about to read 5, iclass 39, count 2 2006.189.07:51:22.15#ibcon#read 5, iclass 39, count 2 2006.189.07:51:22.15#ibcon#about to read 6, iclass 39, count 2 2006.189.07:51:22.15#ibcon#read 6, iclass 39, count 2 2006.189.07:51:22.15#ibcon#end of sib2, iclass 39, count 2 2006.189.07:51:22.15#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:51:22.15#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:51:22.15#ibcon#[27=AT05-04\r\n] 2006.189.07:51:22.15#ibcon#*before write, iclass 39, count 2 2006.189.07:51:22.15#ibcon#enter sib2, iclass 39, count 2 2006.189.07:51:22.15#ibcon#flushed, iclass 39, count 2 2006.189.07:51:22.15#ibcon#about to write, iclass 39, count 2 2006.189.07:51:22.15#ibcon#wrote, iclass 39, count 2 2006.189.07:51:22.15#ibcon#about to read 3, iclass 39, count 2 2006.189.07:51:22.18#ibcon#read 3, iclass 39, count 2 2006.189.07:51:22.18#ibcon#about to read 4, iclass 39, count 2 2006.189.07:51:22.18#ibcon#read 4, iclass 39, count 2 2006.189.07:51:22.18#ibcon#about to read 5, iclass 39, count 2 2006.189.07:51:22.18#ibcon#read 5, iclass 39, count 2 2006.189.07:51:22.18#ibcon#about to read 6, iclass 39, count 2 2006.189.07:51:22.18#ibcon#read 6, iclass 39, count 2 2006.189.07:51:22.18#ibcon#end of sib2, iclass 39, count 2 2006.189.07:51:22.18#ibcon#*after write, iclass 39, count 2 2006.189.07:51:22.18#ibcon#*before return 0, iclass 39, count 2 2006.189.07:51:22.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:22.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:51:22.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:51:22.18#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:22.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:22.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:22.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:22.30#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:51:22.30#ibcon#first serial, iclass 39, count 0 2006.189.07:51:22.30#ibcon#enter sib2, iclass 39, count 0 2006.189.07:51:22.30#ibcon#flushed, iclass 39, count 0 2006.189.07:51:22.30#ibcon#about to write, iclass 39, count 0 2006.189.07:51:22.30#ibcon#wrote, iclass 39, count 0 2006.189.07:51:22.30#ibcon#about to read 3, iclass 39, count 0 2006.189.07:51:22.32#ibcon#read 3, iclass 39, count 0 2006.189.07:51:22.32#ibcon#about to read 4, iclass 39, count 0 2006.189.07:51:22.32#ibcon#read 4, iclass 39, count 0 2006.189.07:51:22.32#ibcon#about to read 5, iclass 39, count 0 2006.189.07:51:22.32#ibcon#read 5, iclass 39, count 0 2006.189.07:51:22.32#ibcon#about to read 6, iclass 39, count 0 2006.189.07:51:22.32#ibcon#read 6, iclass 39, count 0 2006.189.07:51:22.32#ibcon#end of sib2, iclass 39, count 0 2006.189.07:51:22.32#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:51:22.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:51:22.32#ibcon#[27=USB\r\n] 2006.189.07:51:22.32#ibcon#*before write, iclass 39, count 0 2006.189.07:51:22.32#ibcon#enter sib2, iclass 39, count 0 2006.189.07:51:22.32#ibcon#flushed, iclass 39, count 0 2006.189.07:51:22.32#ibcon#about to write, iclass 39, count 0 2006.189.07:51:22.32#ibcon#wrote, iclass 39, count 0 2006.189.07:51:22.32#ibcon#about to read 3, iclass 39, count 0 2006.189.07:51:22.35#ibcon#read 3, iclass 39, count 0 2006.189.07:51:22.35#ibcon#about to read 4, iclass 39, count 0 2006.189.07:51:22.35#ibcon#read 4, iclass 39, count 0 2006.189.07:51:22.35#ibcon#about to read 5, iclass 39, count 0 2006.189.07:51:22.35#ibcon#read 5, iclass 39, count 0 2006.189.07:51:22.35#ibcon#about to read 6, iclass 39, count 0 2006.189.07:51:22.35#ibcon#read 6, iclass 39, count 0 2006.189.07:51:22.35#ibcon#end of sib2, iclass 39, count 0 2006.189.07:51:22.35#ibcon#*after write, iclass 39, count 0 2006.189.07:51:22.35#ibcon#*before return 0, iclass 39, count 0 2006.189.07:51:22.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:22.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:51:22.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:51:22.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:51:22.35$vc4f8/vblo=6,752.99 2006.189.07:51:22.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:51:22.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:51:22.35#ibcon#ireg 17 cls_cnt 0 2006.189.07:51:22.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:22.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:22.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:22.35#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:51:22.35#ibcon#first serial, iclass 3, count 0 2006.189.07:51:22.35#ibcon#enter sib2, iclass 3, count 0 2006.189.07:51:22.35#ibcon#flushed, iclass 3, count 0 2006.189.07:51:22.35#ibcon#about to write, iclass 3, count 0 2006.189.07:51:22.35#ibcon#wrote, iclass 3, count 0 2006.189.07:51:22.35#ibcon#about to read 3, iclass 3, count 0 2006.189.07:51:22.37#ibcon#read 3, iclass 3, count 0 2006.189.07:51:22.37#ibcon#about to read 4, iclass 3, count 0 2006.189.07:51:22.37#ibcon#read 4, iclass 3, count 0 2006.189.07:51:22.37#ibcon#about to read 5, iclass 3, count 0 2006.189.07:51:22.37#ibcon#read 5, iclass 3, count 0 2006.189.07:51:22.37#ibcon#about to read 6, iclass 3, count 0 2006.189.07:51:22.37#ibcon#read 6, iclass 3, count 0 2006.189.07:51:22.37#ibcon#end of sib2, iclass 3, count 0 2006.189.07:51:22.37#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:51:22.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:51:22.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:51:22.37#ibcon#*before write, iclass 3, count 0 2006.189.07:51:22.37#ibcon#enter sib2, iclass 3, count 0 2006.189.07:51:22.37#ibcon#flushed, iclass 3, count 0 2006.189.07:51:22.37#ibcon#about to write, iclass 3, count 0 2006.189.07:51:22.37#ibcon#wrote, iclass 3, count 0 2006.189.07:51:22.37#ibcon#about to read 3, iclass 3, count 0 2006.189.07:51:22.41#ibcon#read 3, iclass 3, count 0 2006.189.07:51:22.41#ibcon#about to read 4, iclass 3, count 0 2006.189.07:51:22.41#ibcon#read 4, iclass 3, count 0 2006.189.07:51:22.41#ibcon#about to read 5, iclass 3, count 0 2006.189.07:51:22.41#ibcon#read 5, iclass 3, count 0 2006.189.07:51:22.41#ibcon#about to read 6, iclass 3, count 0 2006.189.07:51:22.41#ibcon#read 6, iclass 3, count 0 2006.189.07:51:22.41#ibcon#end of sib2, iclass 3, count 0 2006.189.07:51:22.41#ibcon#*after write, iclass 3, count 0 2006.189.07:51:22.41#ibcon#*before return 0, iclass 3, count 0 2006.189.07:51:22.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:22.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:51:22.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:51:22.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:51:22.41$vc4f8/vb=6,4 2006.189.07:51:22.41#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:51:22.41#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:51:22.41#ibcon#ireg 11 cls_cnt 2 2006.189.07:51:22.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:22.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:22.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:22.47#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:51:22.47#ibcon#first serial, iclass 5, count 2 2006.189.07:51:22.47#ibcon#enter sib2, iclass 5, count 2 2006.189.07:51:22.47#ibcon#flushed, iclass 5, count 2 2006.189.07:51:22.47#ibcon#about to write, iclass 5, count 2 2006.189.07:51:22.47#ibcon#wrote, iclass 5, count 2 2006.189.07:51:22.47#ibcon#about to read 3, iclass 5, count 2 2006.189.07:51:22.49#ibcon#read 3, iclass 5, count 2 2006.189.07:51:22.49#ibcon#about to read 4, iclass 5, count 2 2006.189.07:51:22.49#ibcon#read 4, iclass 5, count 2 2006.189.07:51:22.49#ibcon#about to read 5, iclass 5, count 2 2006.189.07:51:22.49#ibcon#read 5, iclass 5, count 2 2006.189.07:51:22.49#ibcon#about to read 6, iclass 5, count 2 2006.189.07:51:22.49#ibcon#read 6, iclass 5, count 2 2006.189.07:51:22.49#ibcon#end of sib2, iclass 5, count 2 2006.189.07:51:22.49#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:51:22.49#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:51:22.49#ibcon#[27=AT06-04\r\n] 2006.189.07:51:22.49#ibcon#*before write, iclass 5, count 2 2006.189.07:51:22.49#ibcon#enter sib2, iclass 5, count 2 2006.189.07:51:22.49#ibcon#flushed, iclass 5, count 2 2006.189.07:51:22.49#ibcon#about to write, iclass 5, count 2 2006.189.07:51:22.49#ibcon#wrote, iclass 5, count 2 2006.189.07:51:22.49#ibcon#about to read 3, iclass 5, count 2 2006.189.07:51:22.52#ibcon#read 3, iclass 5, count 2 2006.189.07:51:22.52#ibcon#about to read 4, iclass 5, count 2 2006.189.07:51:22.52#ibcon#read 4, iclass 5, count 2 2006.189.07:51:22.52#ibcon#about to read 5, iclass 5, count 2 2006.189.07:51:22.52#ibcon#read 5, iclass 5, count 2 2006.189.07:51:22.52#ibcon#about to read 6, iclass 5, count 2 2006.189.07:51:22.52#ibcon#read 6, iclass 5, count 2 2006.189.07:51:22.52#ibcon#end of sib2, iclass 5, count 2 2006.189.07:51:22.52#ibcon#*after write, iclass 5, count 2 2006.189.07:51:22.52#ibcon#*before return 0, iclass 5, count 2 2006.189.07:51:22.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:22.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:51:22.52#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:51:22.52#ibcon#ireg 7 cls_cnt 0 2006.189.07:51:22.52#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:22.64#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:22.64#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:22.64#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:51:22.64#ibcon#first serial, iclass 5, count 0 2006.189.07:51:22.64#ibcon#enter sib2, iclass 5, count 0 2006.189.07:51:22.64#ibcon#flushed, iclass 5, count 0 2006.189.07:51:22.64#ibcon#about to write, iclass 5, count 0 2006.189.07:51:22.64#ibcon#wrote, iclass 5, count 0 2006.189.07:51:22.64#ibcon#about to read 3, iclass 5, count 0 2006.189.07:51:22.66#ibcon#read 3, iclass 5, count 0 2006.189.07:51:22.66#ibcon#about to read 4, iclass 5, count 0 2006.189.07:51:22.66#ibcon#read 4, iclass 5, count 0 2006.189.07:51:22.66#ibcon#about to read 5, iclass 5, count 0 2006.189.07:51:22.66#ibcon#read 5, iclass 5, count 0 2006.189.07:51:22.66#ibcon#about to read 6, iclass 5, count 0 2006.189.07:51:22.66#ibcon#read 6, iclass 5, count 0 2006.189.07:51:22.66#ibcon#end of sib2, iclass 5, count 0 2006.189.07:51:22.66#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:51:22.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:51:22.66#ibcon#[27=USB\r\n] 2006.189.07:51:22.66#ibcon#*before write, iclass 5, count 0 2006.189.07:51:22.66#ibcon#enter sib2, iclass 5, count 0 2006.189.07:51:22.66#ibcon#flushed, iclass 5, count 0 2006.189.07:51:22.66#ibcon#about to write, iclass 5, count 0 2006.189.07:51:22.66#ibcon#wrote, iclass 5, count 0 2006.189.07:51:22.66#ibcon#about to read 3, iclass 5, count 0 2006.189.07:51:22.69#ibcon#read 3, iclass 5, count 0 2006.189.07:51:22.69#ibcon#about to read 4, iclass 5, count 0 2006.189.07:51:22.69#ibcon#read 4, iclass 5, count 0 2006.189.07:51:22.69#ibcon#about to read 5, iclass 5, count 0 2006.189.07:51:22.69#ibcon#read 5, iclass 5, count 0 2006.189.07:51:22.69#ibcon#about to read 6, iclass 5, count 0 2006.189.07:51:22.69#ibcon#read 6, iclass 5, count 0 2006.189.07:51:22.69#ibcon#end of sib2, iclass 5, count 0 2006.189.07:51:22.69#ibcon#*after write, iclass 5, count 0 2006.189.07:51:22.69#ibcon#*before return 0, iclass 5, count 0 2006.189.07:51:22.69#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:22.69#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:51:22.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:51:22.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:51:22.69$vc4f8/vabw=wide 2006.189.07:51:22.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:51:22.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:51:22.69#ibcon#ireg 8 cls_cnt 0 2006.189.07:51:22.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:22.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:22.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:22.69#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:51:22.69#ibcon#first serial, iclass 7, count 0 2006.189.07:51:22.69#ibcon#enter sib2, iclass 7, count 0 2006.189.07:51:22.69#ibcon#flushed, iclass 7, count 0 2006.189.07:51:22.69#ibcon#about to write, iclass 7, count 0 2006.189.07:51:22.69#ibcon#wrote, iclass 7, count 0 2006.189.07:51:22.69#ibcon#about to read 3, iclass 7, count 0 2006.189.07:51:22.71#ibcon#read 3, iclass 7, count 0 2006.189.07:51:22.71#ibcon#about to read 4, iclass 7, count 0 2006.189.07:51:22.71#ibcon#read 4, iclass 7, count 0 2006.189.07:51:22.71#ibcon#about to read 5, iclass 7, count 0 2006.189.07:51:22.71#ibcon#read 5, iclass 7, count 0 2006.189.07:51:22.71#ibcon#about to read 6, iclass 7, count 0 2006.189.07:51:22.71#ibcon#read 6, iclass 7, count 0 2006.189.07:51:22.71#ibcon#end of sib2, iclass 7, count 0 2006.189.07:51:22.71#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:51:22.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:51:22.71#ibcon#[25=BW32\r\n] 2006.189.07:51:22.71#ibcon#*before write, iclass 7, count 0 2006.189.07:51:22.71#ibcon#enter sib2, iclass 7, count 0 2006.189.07:51:22.71#ibcon#flushed, iclass 7, count 0 2006.189.07:51:22.71#ibcon#about to write, iclass 7, count 0 2006.189.07:51:22.71#ibcon#wrote, iclass 7, count 0 2006.189.07:51:22.71#ibcon#about to read 3, iclass 7, count 0 2006.189.07:51:22.74#ibcon#read 3, iclass 7, count 0 2006.189.07:51:22.74#ibcon#about to read 4, iclass 7, count 0 2006.189.07:51:22.74#ibcon#read 4, iclass 7, count 0 2006.189.07:51:22.74#ibcon#about to read 5, iclass 7, count 0 2006.189.07:51:22.74#ibcon#read 5, iclass 7, count 0 2006.189.07:51:22.74#ibcon#about to read 6, iclass 7, count 0 2006.189.07:51:22.74#ibcon#read 6, iclass 7, count 0 2006.189.07:51:22.74#ibcon#end of sib2, iclass 7, count 0 2006.189.07:51:22.74#ibcon#*after write, iclass 7, count 0 2006.189.07:51:22.74#ibcon#*before return 0, iclass 7, count 0 2006.189.07:51:22.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:22.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:51:22.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:51:22.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:51:22.74$vc4f8/vbbw=wide 2006.189.07:51:22.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.07:51:22.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.07:51:22.74#ibcon#ireg 8 cls_cnt 0 2006.189.07:51:22.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:51:22.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:51:22.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:51:22.81#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:51:22.81#ibcon#first serial, iclass 11, count 0 2006.189.07:51:22.81#ibcon#enter sib2, iclass 11, count 0 2006.189.07:51:22.81#ibcon#flushed, iclass 11, count 0 2006.189.07:51:22.81#ibcon#about to write, iclass 11, count 0 2006.189.07:51:22.81#ibcon#wrote, iclass 11, count 0 2006.189.07:51:22.81#ibcon#about to read 3, iclass 11, count 0 2006.189.07:51:22.83#ibcon#read 3, iclass 11, count 0 2006.189.07:51:22.83#ibcon#about to read 4, iclass 11, count 0 2006.189.07:51:22.83#ibcon#read 4, iclass 11, count 0 2006.189.07:51:22.83#ibcon#about to read 5, iclass 11, count 0 2006.189.07:51:22.83#ibcon#read 5, iclass 11, count 0 2006.189.07:51:22.83#ibcon#about to read 6, iclass 11, count 0 2006.189.07:51:22.83#ibcon#read 6, iclass 11, count 0 2006.189.07:51:22.83#ibcon#end of sib2, iclass 11, count 0 2006.189.07:51:22.83#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:51:22.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:51:22.83#ibcon#[27=BW32\r\n] 2006.189.07:51:22.83#ibcon#*before write, iclass 11, count 0 2006.189.07:51:22.83#ibcon#enter sib2, iclass 11, count 0 2006.189.07:51:22.83#ibcon#flushed, iclass 11, count 0 2006.189.07:51:22.83#ibcon#about to write, iclass 11, count 0 2006.189.07:51:22.83#ibcon#wrote, iclass 11, count 0 2006.189.07:51:22.83#ibcon#about to read 3, iclass 11, count 0 2006.189.07:51:22.86#ibcon#read 3, iclass 11, count 0 2006.189.07:51:22.86#ibcon#about to read 4, iclass 11, count 0 2006.189.07:51:22.86#ibcon#read 4, iclass 11, count 0 2006.189.07:51:22.86#ibcon#about to read 5, iclass 11, count 0 2006.189.07:51:22.86#ibcon#read 5, iclass 11, count 0 2006.189.07:51:22.86#ibcon#about to read 6, iclass 11, count 0 2006.189.07:51:22.86#ibcon#read 6, iclass 11, count 0 2006.189.07:51:22.86#ibcon#end of sib2, iclass 11, count 0 2006.189.07:51:22.86#ibcon#*after write, iclass 11, count 0 2006.189.07:51:22.86#ibcon#*before return 0, iclass 11, count 0 2006.189.07:51:22.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:51:22.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.07:51:22.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:51:22.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:51:22.86$4f8m12a/ifd4f 2006.189.07:51:22.86$ifd4f/lo= 2006.189.07:51:22.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:51:22.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:51:22.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:51:22.86$ifd4f/patch= 2006.189.07:51:22.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:51:22.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:51:22.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:51:22.86$4f8m12a/"form=m,16.000,1:2 2006.189.07:51:22.86$4f8m12a/"tpicd 2006.189.07:51:22.86$4f8m12a/echo=off 2006.189.07:51:22.86$4f8m12a/xlog=off 2006.189.07:51:22.86:!2006.189.07:51:50 2006.189.07:51:36.14#trakl#Source acquired 2006.189.07:51:38.14#flagr#flagr/antenna,acquired 2006.189.07:51:50.00:preob 2006.189.07:51:51.14/onsource/TRACKING 2006.189.07:51:51.14:!2006.189.07:52:00 2006.189.07:52:00.00:data_valid=on 2006.189.07:52:00.00:midob 2006.189.07:52:00.14/onsource/TRACKING 2006.189.07:52:00.14/wx/25.91,1009.1,89 2006.189.07:52:00.34/cable/+6.4532E-03 2006.189.07:52:01.43/va/01,08,usb,yes,36,38 2006.189.07:52:01.43/va/02,07,usb,yes,37,38 2006.189.07:52:01.43/va/03,06,usb,yes,38,39 2006.189.07:52:01.43/va/04,07,usb,yes,37,40 2006.189.07:52:01.43/va/05,07,usb,yes,40,43 2006.189.07:52:01.43/va/06,06,usb,yes,40,39 2006.189.07:52:01.43/va/07,06,usb,yes,40,40 2006.189.07:52:01.43/va/08,06,usb,yes,43,42 2006.189.07:52:01.66/valo/01,532.99,yes,locked 2006.189.07:52:01.66/valo/02,572.99,yes,locked 2006.189.07:52:01.66/valo/03,672.99,yes,locked 2006.189.07:52:01.66/valo/04,832.99,yes,locked 2006.189.07:52:01.66/valo/05,652.99,yes,locked 2006.189.07:52:01.66/valo/06,772.99,yes,locked 2006.189.07:52:01.66/valo/07,832.99,yes,locked 2006.189.07:52:01.66/valo/08,852.99,yes,locked 2006.189.07:52:02.75/vb/01,04,usb,yes,32,33 2006.189.07:52:02.75/vb/02,04,usb,yes,33,37 2006.189.07:52:02.75/vb/03,04,usb,yes,30,34 2006.189.07:52:02.75/vb/04,04,usb,yes,31,31 2006.189.07:52:02.75/vb/05,04,usb,yes,29,34 2006.189.07:52:02.75/vb/06,04,usb,yes,31,34 2006.189.07:52:02.75/vb/07,04,usb,yes,33,33 2006.189.07:52:02.75/vb/08,04,usb,yes,30,33 2006.189.07:52:02.99/vblo/01,632.99,yes,locked 2006.189.07:52:02.99/vblo/02,640.99,yes,locked 2006.189.07:52:02.99/vblo/03,656.99,yes,locked 2006.189.07:52:02.99/vblo/04,712.99,yes,locked 2006.189.07:52:02.99/vblo/05,744.99,yes,locked 2006.189.07:52:02.99/vblo/06,752.99,yes,locked 2006.189.07:52:02.99/vblo/07,734.99,yes,locked 2006.189.07:52:02.99/vblo/08,744.99,yes,locked 2006.189.07:52:03.14/vabw/8 2006.189.07:52:03.29/vbbw/8 2006.189.07:52:03.47/xfe/off,on,14.5 2006.189.07:52:03.84/ifatt/23,28,28,28 2006.189.07:52:04.07/fmout-gps/S +2.97E-07 2006.189.07:52:04.15:!2006.189.07:53:00 2006.189.07:53:00.01:data_valid=off 2006.189.07:53:00.01:postob 2006.189.07:53:00.10/cable/+6.4545E-03 2006.189.07:53:00.10/wx/25.88,1009.1,89 2006.189.07:53:01.07/fmout-gps/S +2.97E-07 2006.189.07:53:01.07:scan_name=189-0755,k06189,60 2006.189.07:53:01.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.189.07:53:01.13#flagr#flagr/antenna,new-source 2006.189.07:53:02.13:checkk5 2006.189.07:53:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:53:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:53:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:53:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:53:04.03/chk_obsdata//k5ts1/T1890752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:53:04.41/chk_obsdata//k5ts2/T1890752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:53:04.78/chk_obsdata//k5ts3/T1890752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:53:05.16/chk_obsdata//k5ts4/T1890752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:53:05.85/k5log//k5ts1_log_newline 2006.189.07:53:06.56/k5log//k5ts2_log_newline 2006.189.07:53:07.26/k5log//k5ts3_log_newline 2006.189.07:53:07.96/k5log//k5ts4_log_newline 2006.189.07:53:07.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:53:07.98:4f8m12a=2 2006.189.07:53:07.98$4f8m12a/echo=on 2006.189.07:53:07.98$4f8m12a/pcalon 2006.189.07:53:07.98$pcalon/"no phase cal control is implemented here 2006.189.07:53:07.98$4f8m12a/"tpicd=stop 2006.189.07:53:07.98$4f8m12a/vc4f8 2006.189.07:53:07.98$vc4f8/valo=1,532.99 2006.189.07:53:07.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.07:53:07.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.07:53:07.98#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:07.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:07.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:07.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:07.98#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:53:07.98#ibcon#first serial, iclass 18, count 0 2006.189.07:53:07.98#ibcon#enter sib2, iclass 18, count 0 2006.189.07:53:07.98#ibcon#flushed, iclass 18, count 0 2006.189.07:53:07.98#ibcon#about to write, iclass 18, count 0 2006.189.07:53:07.98#ibcon#wrote, iclass 18, count 0 2006.189.07:53:07.98#ibcon#about to read 3, iclass 18, count 0 2006.189.07:53:08.00#ibcon#read 3, iclass 18, count 0 2006.189.07:53:08.00#ibcon#about to read 4, iclass 18, count 0 2006.189.07:53:08.00#ibcon#read 4, iclass 18, count 0 2006.189.07:53:08.00#ibcon#about to read 5, iclass 18, count 0 2006.189.07:53:08.00#ibcon#read 5, iclass 18, count 0 2006.189.07:53:08.00#ibcon#about to read 6, iclass 18, count 0 2006.189.07:53:08.00#ibcon#read 6, iclass 18, count 0 2006.189.07:53:08.00#ibcon#end of sib2, iclass 18, count 0 2006.189.07:53:08.00#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:53:08.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:53:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:53:08.00#ibcon#*before write, iclass 18, count 0 2006.189.07:53:08.00#ibcon#enter sib2, iclass 18, count 0 2006.189.07:53:08.00#ibcon#flushed, iclass 18, count 0 2006.189.07:53:08.00#ibcon#about to write, iclass 18, count 0 2006.189.07:53:08.00#ibcon#wrote, iclass 18, count 0 2006.189.07:53:08.00#ibcon#about to read 3, iclass 18, count 0 2006.189.07:53:08.05#ibcon#read 3, iclass 18, count 0 2006.189.07:53:08.05#ibcon#about to read 4, iclass 18, count 0 2006.189.07:53:08.05#ibcon#read 4, iclass 18, count 0 2006.189.07:53:08.05#ibcon#about to read 5, iclass 18, count 0 2006.189.07:53:08.05#ibcon#read 5, iclass 18, count 0 2006.189.07:53:08.05#ibcon#about to read 6, iclass 18, count 0 2006.189.07:53:08.05#ibcon#read 6, iclass 18, count 0 2006.189.07:53:08.05#ibcon#end of sib2, iclass 18, count 0 2006.189.07:53:08.05#ibcon#*after write, iclass 18, count 0 2006.189.07:53:08.05#ibcon#*before return 0, iclass 18, count 0 2006.189.07:53:08.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:08.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:08.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:53:08.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:53:08.05$vc4f8/va=1,8 2006.189.07:53:08.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:53:08.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:53:08.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:08.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:08.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:08.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:08.05#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:53:08.05#ibcon#first serial, iclass 20, count 2 2006.189.07:53:08.05#ibcon#enter sib2, iclass 20, count 2 2006.189.07:53:08.05#ibcon#flushed, iclass 20, count 2 2006.189.07:53:08.05#ibcon#about to write, iclass 20, count 2 2006.189.07:53:08.05#ibcon#wrote, iclass 20, count 2 2006.189.07:53:08.05#ibcon#about to read 3, iclass 20, count 2 2006.189.07:53:08.07#ibcon#read 3, iclass 20, count 2 2006.189.07:53:08.07#ibcon#about to read 4, iclass 20, count 2 2006.189.07:53:08.07#ibcon#read 4, iclass 20, count 2 2006.189.07:53:08.07#ibcon#about to read 5, iclass 20, count 2 2006.189.07:53:08.07#ibcon#read 5, iclass 20, count 2 2006.189.07:53:08.07#ibcon#about to read 6, iclass 20, count 2 2006.189.07:53:08.07#ibcon#read 6, iclass 20, count 2 2006.189.07:53:08.07#ibcon#end of sib2, iclass 20, count 2 2006.189.07:53:08.07#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:53:08.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:53:08.07#ibcon#[25=AT01-08\r\n] 2006.189.07:53:08.07#ibcon#*before write, iclass 20, count 2 2006.189.07:53:08.07#ibcon#enter sib2, iclass 20, count 2 2006.189.07:53:08.07#ibcon#flushed, iclass 20, count 2 2006.189.07:53:08.07#ibcon#about to write, iclass 20, count 2 2006.189.07:53:08.07#ibcon#wrote, iclass 20, count 2 2006.189.07:53:08.07#ibcon#about to read 3, iclass 20, count 2 2006.189.07:53:08.10#ibcon#read 3, iclass 20, count 2 2006.189.07:53:08.10#ibcon#about to read 4, iclass 20, count 2 2006.189.07:53:08.10#ibcon#read 4, iclass 20, count 2 2006.189.07:53:08.10#ibcon#about to read 5, iclass 20, count 2 2006.189.07:53:08.10#ibcon#read 5, iclass 20, count 2 2006.189.07:53:08.10#ibcon#about to read 6, iclass 20, count 2 2006.189.07:53:08.10#ibcon#read 6, iclass 20, count 2 2006.189.07:53:08.10#ibcon#end of sib2, iclass 20, count 2 2006.189.07:53:08.10#ibcon#*after write, iclass 20, count 2 2006.189.07:53:08.10#ibcon#*before return 0, iclass 20, count 2 2006.189.07:53:08.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:08.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:08.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:53:08.10#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:08.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:08.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:08.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:08.22#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:53:08.22#ibcon#first serial, iclass 20, count 0 2006.189.07:53:08.22#ibcon#enter sib2, iclass 20, count 0 2006.189.07:53:08.22#ibcon#flushed, iclass 20, count 0 2006.189.07:53:08.22#ibcon#about to write, iclass 20, count 0 2006.189.07:53:08.22#ibcon#wrote, iclass 20, count 0 2006.189.07:53:08.22#ibcon#about to read 3, iclass 20, count 0 2006.189.07:53:08.25#ibcon#read 3, iclass 20, count 0 2006.189.07:53:08.25#ibcon#about to read 4, iclass 20, count 0 2006.189.07:53:08.25#ibcon#read 4, iclass 20, count 0 2006.189.07:53:08.25#ibcon#about to read 5, iclass 20, count 0 2006.189.07:53:08.25#ibcon#read 5, iclass 20, count 0 2006.189.07:53:08.25#ibcon#about to read 6, iclass 20, count 0 2006.189.07:53:08.25#ibcon#read 6, iclass 20, count 0 2006.189.07:53:08.25#ibcon#end of sib2, iclass 20, count 0 2006.189.07:53:08.25#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:53:08.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:53:08.25#ibcon#[25=USB\r\n] 2006.189.07:53:08.25#ibcon#*before write, iclass 20, count 0 2006.189.07:53:08.25#ibcon#enter sib2, iclass 20, count 0 2006.189.07:53:08.25#ibcon#flushed, iclass 20, count 0 2006.189.07:53:08.25#ibcon#about to write, iclass 20, count 0 2006.189.07:53:08.25#ibcon#wrote, iclass 20, count 0 2006.189.07:53:08.25#ibcon#about to read 3, iclass 20, count 0 2006.189.07:53:08.28#ibcon#read 3, iclass 20, count 0 2006.189.07:53:08.28#ibcon#about to read 4, iclass 20, count 0 2006.189.07:53:08.28#ibcon#read 4, iclass 20, count 0 2006.189.07:53:08.28#ibcon#about to read 5, iclass 20, count 0 2006.189.07:53:08.28#ibcon#read 5, iclass 20, count 0 2006.189.07:53:08.28#ibcon#about to read 6, iclass 20, count 0 2006.189.07:53:08.28#ibcon#read 6, iclass 20, count 0 2006.189.07:53:08.28#ibcon#end of sib2, iclass 20, count 0 2006.189.07:53:08.28#ibcon#*after write, iclass 20, count 0 2006.189.07:53:08.28#ibcon#*before return 0, iclass 20, count 0 2006.189.07:53:08.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:08.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:08.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:53:08.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:53:08.28$vc4f8/valo=2,572.99 2006.189.07:53:08.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:53:08.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:53:08.28#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:08.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:08.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:08.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:08.28#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:53:08.28#ibcon#first serial, iclass 22, count 0 2006.189.07:53:08.28#ibcon#enter sib2, iclass 22, count 0 2006.189.07:53:08.28#ibcon#flushed, iclass 22, count 0 2006.189.07:53:08.28#ibcon#about to write, iclass 22, count 0 2006.189.07:53:08.28#ibcon#wrote, iclass 22, count 0 2006.189.07:53:08.28#ibcon#about to read 3, iclass 22, count 0 2006.189.07:53:08.30#ibcon#read 3, iclass 22, count 0 2006.189.07:53:08.30#ibcon#about to read 4, iclass 22, count 0 2006.189.07:53:08.30#ibcon#read 4, iclass 22, count 0 2006.189.07:53:08.30#ibcon#about to read 5, iclass 22, count 0 2006.189.07:53:08.30#ibcon#read 5, iclass 22, count 0 2006.189.07:53:08.30#ibcon#about to read 6, iclass 22, count 0 2006.189.07:53:08.30#ibcon#read 6, iclass 22, count 0 2006.189.07:53:08.30#ibcon#end of sib2, iclass 22, count 0 2006.189.07:53:08.30#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:53:08.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:53:08.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:53:08.30#ibcon#*before write, iclass 22, count 0 2006.189.07:53:08.30#ibcon#enter sib2, iclass 22, count 0 2006.189.07:53:08.30#ibcon#flushed, iclass 22, count 0 2006.189.07:53:08.30#ibcon#about to write, iclass 22, count 0 2006.189.07:53:08.30#ibcon#wrote, iclass 22, count 0 2006.189.07:53:08.30#ibcon#about to read 3, iclass 22, count 0 2006.189.07:53:08.34#ibcon#read 3, iclass 22, count 0 2006.189.07:53:08.34#ibcon#about to read 4, iclass 22, count 0 2006.189.07:53:08.34#ibcon#read 4, iclass 22, count 0 2006.189.07:53:08.34#ibcon#about to read 5, iclass 22, count 0 2006.189.07:53:08.34#ibcon#read 5, iclass 22, count 0 2006.189.07:53:08.34#ibcon#about to read 6, iclass 22, count 0 2006.189.07:53:08.34#ibcon#read 6, iclass 22, count 0 2006.189.07:53:08.34#ibcon#end of sib2, iclass 22, count 0 2006.189.07:53:08.34#ibcon#*after write, iclass 22, count 0 2006.189.07:53:08.34#ibcon#*before return 0, iclass 22, count 0 2006.189.07:53:08.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:08.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:08.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:53:08.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:53:08.34$vc4f8/va=2,7 2006.189.07:53:08.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:53:08.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:53:08.34#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:08.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:08.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:08.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:08.40#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:53:08.40#ibcon#first serial, iclass 24, count 2 2006.189.07:53:08.40#ibcon#enter sib2, iclass 24, count 2 2006.189.07:53:08.40#ibcon#flushed, iclass 24, count 2 2006.189.07:53:08.40#ibcon#about to write, iclass 24, count 2 2006.189.07:53:08.40#ibcon#wrote, iclass 24, count 2 2006.189.07:53:08.40#ibcon#about to read 3, iclass 24, count 2 2006.189.07:53:08.42#ibcon#read 3, iclass 24, count 2 2006.189.07:53:08.42#ibcon#about to read 4, iclass 24, count 2 2006.189.07:53:08.42#ibcon#read 4, iclass 24, count 2 2006.189.07:53:08.42#ibcon#about to read 5, iclass 24, count 2 2006.189.07:53:08.42#ibcon#read 5, iclass 24, count 2 2006.189.07:53:08.42#ibcon#about to read 6, iclass 24, count 2 2006.189.07:53:08.42#ibcon#read 6, iclass 24, count 2 2006.189.07:53:08.42#ibcon#end of sib2, iclass 24, count 2 2006.189.07:53:08.42#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:53:08.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:53:08.42#ibcon#[25=AT02-07\r\n] 2006.189.07:53:08.42#ibcon#*before write, iclass 24, count 2 2006.189.07:53:08.42#ibcon#enter sib2, iclass 24, count 2 2006.189.07:53:08.42#ibcon#flushed, iclass 24, count 2 2006.189.07:53:08.42#ibcon#about to write, iclass 24, count 2 2006.189.07:53:08.42#ibcon#wrote, iclass 24, count 2 2006.189.07:53:08.42#ibcon#about to read 3, iclass 24, count 2 2006.189.07:53:08.45#ibcon#read 3, iclass 24, count 2 2006.189.07:53:08.45#ibcon#about to read 4, iclass 24, count 2 2006.189.07:53:08.45#ibcon#read 4, iclass 24, count 2 2006.189.07:53:08.45#ibcon#about to read 5, iclass 24, count 2 2006.189.07:53:08.45#ibcon#read 5, iclass 24, count 2 2006.189.07:53:08.45#ibcon#about to read 6, iclass 24, count 2 2006.189.07:53:08.45#ibcon#read 6, iclass 24, count 2 2006.189.07:53:08.45#ibcon#end of sib2, iclass 24, count 2 2006.189.07:53:08.45#ibcon#*after write, iclass 24, count 2 2006.189.07:53:08.45#ibcon#*before return 0, iclass 24, count 2 2006.189.07:53:08.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:08.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:08.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:53:08.45#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:08.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:08.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:08.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:08.58#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:53:08.58#ibcon#first serial, iclass 24, count 0 2006.189.07:53:08.58#ibcon#enter sib2, iclass 24, count 0 2006.189.07:53:08.58#ibcon#flushed, iclass 24, count 0 2006.189.07:53:08.58#ibcon#about to write, iclass 24, count 0 2006.189.07:53:08.58#ibcon#wrote, iclass 24, count 0 2006.189.07:53:08.58#ibcon#about to read 3, iclass 24, count 0 2006.189.07:53:08.59#ibcon#read 3, iclass 24, count 0 2006.189.07:53:08.59#ibcon#about to read 4, iclass 24, count 0 2006.189.07:53:08.59#ibcon#read 4, iclass 24, count 0 2006.189.07:53:08.59#ibcon#about to read 5, iclass 24, count 0 2006.189.07:53:08.59#ibcon#read 5, iclass 24, count 0 2006.189.07:53:08.59#ibcon#about to read 6, iclass 24, count 0 2006.189.07:53:08.59#ibcon#read 6, iclass 24, count 0 2006.189.07:53:08.59#ibcon#end of sib2, iclass 24, count 0 2006.189.07:53:08.59#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:53:08.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:53:08.59#ibcon#[25=USB\r\n] 2006.189.07:53:08.59#ibcon#*before write, iclass 24, count 0 2006.189.07:53:08.59#ibcon#enter sib2, iclass 24, count 0 2006.189.07:53:08.59#ibcon#flushed, iclass 24, count 0 2006.189.07:53:08.59#ibcon#about to write, iclass 24, count 0 2006.189.07:53:08.59#ibcon#wrote, iclass 24, count 0 2006.189.07:53:08.59#ibcon#about to read 3, iclass 24, count 0 2006.189.07:53:08.62#ibcon#read 3, iclass 24, count 0 2006.189.07:53:08.62#ibcon#about to read 4, iclass 24, count 0 2006.189.07:53:08.62#ibcon#read 4, iclass 24, count 0 2006.189.07:53:08.62#ibcon#about to read 5, iclass 24, count 0 2006.189.07:53:08.62#ibcon#read 5, iclass 24, count 0 2006.189.07:53:08.62#ibcon#about to read 6, iclass 24, count 0 2006.189.07:53:08.62#ibcon#read 6, iclass 24, count 0 2006.189.07:53:08.62#ibcon#end of sib2, iclass 24, count 0 2006.189.07:53:08.62#ibcon#*after write, iclass 24, count 0 2006.189.07:53:08.62#ibcon#*before return 0, iclass 24, count 0 2006.189.07:53:08.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:08.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:08.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:53:08.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:53:08.62$vc4f8/valo=3,672.99 2006.189.07:53:08.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.07:53:08.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.07:53:08.62#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:08.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:08.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:08.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:08.62#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:53:08.62#ibcon#first serial, iclass 26, count 0 2006.189.07:53:08.62#ibcon#enter sib2, iclass 26, count 0 2006.189.07:53:08.62#ibcon#flushed, iclass 26, count 0 2006.189.07:53:08.62#ibcon#about to write, iclass 26, count 0 2006.189.07:53:08.62#ibcon#wrote, iclass 26, count 0 2006.189.07:53:08.62#ibcon#about to read 3, iclass 26, count 0 2006.189.07:53:08.64#ibcon#read 3, iclass 26, count 0 2006.189.07:53:08.64#ibcon#about to read 4, iclass 26, count 0 2006.189.07:53:08.64#ibcon#read 4, iclass 26, count 0 2006.189.07:53:08.64#ibcon#about to read 5, iclass 26, count 0 2006.189.07:53:08.64#ibcon#read 5, iclass 26, count 0 2006.189.07:53:08.64#ibcon#about to read 6, iclass 26, count 0 2006.189.07:53:08.64#ibcon#read 6, iclass 26, count 0 2006.189.07:53:08.64#ibcon#end of sib2, iclass 26, count 0 2006.189.07:53:08.64#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:53:08.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:53:08.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:53:08.64#ibcon#*before write, iclass 26, count 0 2006.189.07:53:08.64#ibcon#enter sib2, iclass 26, count 0 2006.189.07:53:08.64#ibcon#flushed, iclass 26, count 0 2006.189.07:53:08.64#ibcon#about to write, iclass 26, count 0 2006.189.07:53:08.64#ibcon#wrote, iclass 26, count 0 2006.189.07:53:08.64#ibcon#about to read 3, iclass 26, count 0 2006.189.07:53:08.68#ibcon#read 3, iclass 26, count 0 2006.189.07:53:08.68#ibcon#about to read 4, iclass 26, count 0 2006.189.07:53:08.68#ibcon#read 4, iclass 26, count 0 2006.189.07:53:08.68#ibcon#about to read 5, iclass 26, count 0 2006.189.07:53:08.68#ibcon#read 5, iclass 26, count 0 2006.189.07:53:08.68#ibcon#about to read 6, iclass 26, count 0 2006.189.07:53:08.68#ibcon#read 6, iclass 26, count 0 2006.189.07:53:08.68#ibcon#end of sib2, iclass 26, count 0 2006.189.07:53:08.68#ibcon#*after write, iclass 26, count 0 2006.189.07:53:08.68#ibcon#*before return 0, iclass 26, count 0 2006.189.07:53:08.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:08.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:08.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:53:08.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:53:08.68$vc4f8/va=3,6 2006.189.07:53:08.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.07:53:08.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.07:53:08.68#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:08.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:08.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:08.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:08.74#ibcon#enter wrdev, iclass 28, count 2 2006.189.07:53:08.74#ibcon#first serial, iclass 28, count 2 2006.189.07:53:08.74#ibcon#enter sib2, iclass 28, count 2 2006.189.07:53:08.74#ibcon#flushed, iclass 28, count 2 2006.189.07:53:08.74#ibcon#about to write, iclass 28, count 2 2006.189.07:53:08.74#ibcon#wrote, iclass 28, count 2 2006.189.07:53:08.74#ibcon#about to read 3, iclass 28, count 2 2006.189.07:53:08.76#ibcon#read 3, iclass 28, count 2 2006.189.07:53:08.76#ibcon#about to read 4, iclass 28, count 2 2006.189.07:53:08.76#ibcon#read 4, iclass 28, count 2 2006.189.07:53:08.76#ibcon#about to read 5, iclass 28, count 2 2006.189.07:53:08.76#ibcon#read 5, iclass 28, count 2 2006.189.07:53:08.76#ibcon#about to read 6, iclass 28, count 2 2006.189.07:53:08.76#ibcon#read 6, iclass 28, count 2 2006.189.07:53:08.76#ibcon#end of sib2, iclass 28, count 2 2006.189.07:53:08.76#ibcon#*mode == 0, iclass 28, count 2 2006.189.07:53:08.76#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.07:53:08.76#ibcon#[25=AT03-06\r\n] 2006.189.07:53:08.76#ibcon#*before write, iclass 28, count 2 2006.189.07:53:08.76#ibcon#enter sib2, iclass 28, count 2 2006.189.07:53:08.76#ibcon#flushed, iclass 28, count 2 2006.189.07:53:08.76#ibcon#about to write, iclass 28, count 2 2006.189.07:53:08.76#ibcon#wrote, iclass 28, count 2 2006.189.07:53:08.76#ibcon#about to read 3, iclass 28, count 2 2006.189.07:53:08.79#ibcon#read 3, iclass 28, count 2 2006.189.07:53:08.79#ibcon#about to read 4, iclass 28, count 2 2006.189.07:53:08.79#ibcon#read 4, iclass 28, count 2 2006.189.07:53:08.79#ibcon#about to read 5, iclass 28, count 2 2006.189.07:53:08.79#ibcon#read 5, iclass 28, count 2 2006.189.07:53:08.79#ibcon#about to read 6, iclass 28, count 2 2006.189.07:53:08.79#ibcon#read 6, iclass 28, count 2 2006.189.07:53:08.79#ibcon#end of sib2, iclass 28, count 2 2006.189.07:53:08.79#ibcon#*after write, iclass 28, count 2 2006.189.07:53:08.79#ibcon#*before return 0, iclass 28, count 2 2006.189.07:53:08.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:08.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:08.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.07:53:08.79#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:08.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:08.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:08.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:08.91#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:53:08.91#ibcon#first serial, iclass 28, count 0 2006.189.07:53:08.91#ibcon#enter sib2, iclass 28, count 0 2006.189.07:53:08.91#ibcon#flushed, iclass 28, count 0 2006.189.07:53:08.91#ibcon#about to write, iclass 28, count 0 2006.189.07:53:08.91#ibcon#wrote, iclass 28, count 0 2006.189.07:53:08.91#ibcon#about to read 3, iclass 28, count 0 2006.189.07:53:08.93#ibcon#read 3, iclass 28, count 0 2006.189.07:53:08.93#ibcon#about to read 4, iclass 28, count 0 2006.189.07:53:08.93#ibcon#read 4, iclass 28, count 0 2006.189.07:53:08.93#ibcon#about to read 5, iclass 28, count 0 2006.189.07:53:08.93#ibcon#read 5, iclass 28, count 0 2006.189.07:53:08.93#ibcon#about to read 6, iclass 28, count 0 2006.189.07:53:08.93#ibcon#read 6, iclass 28, count 0 2006.189.07:53:08.93#ibcon#end of sib2, iclass 28, count 0 2006.189.07:53:08.93#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:53:08.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:53:08.93#ibcon#[25=USB\r\n] 2006.189.07:53:08.93#ibcon#*before write, iclass 28, count 0 2006.189.07:53:08.93#ibcon#enter sib2, iclass 28, count 0 2006.189.07:53:08.93#ibcon#flushed, iclass 28, count 0 2006.189.07:53:08.93#ibcon#about to write, iclass 28, count 0 2006.189.07:53:08.93#ibcon#wrote, iclass 28, count 0 2006.189.07:53:08.93#ibcon#about to read 3, iclass 28, count 0 2006.189.07:53:08.96#ibcon#read 3, iclass 28, count 0 2006.189.07:53:08.96#ibcon#about to read 4, iclass 28, count 0 2006.189.07:53:08.96#ibcon#read 4, iclass 28, count 0 2006.189.07:53:08.96#ibcon#about to read 5, iclass 28, count 0 2006.189.07:53:08.96#ibcon#read 5, iclass 28, count 0 2006.189.07:53:08.96#ibcon#about to read 6, iclass 28, count 0 2006.189.07:53:08.96#ibcon#read 6, iclass 28, count 0 2006.189.07:53:08.96#ibcon#end of sib2, iclass 28, count 0 2006.189.07:53:08.96#ibcon#*after write, iclass 28, count 0 2006.189.07:53:08.96#ibcon#*before return 0, iclass 28, count 0 2006.189.07:53:08.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:08.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:08.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:53:08.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:53:08.96$vc4f8/valo=4,832.99 2006.189.07:53:08.96#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.07:53:08.96#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.07:53:08.96#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:08.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:08.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:08.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:08.96#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:53:08.96#ibcon#first serial, iclass 30, count 0 2006.189.07:53:08.96#ibcon#enter sib2, iclass 30, count 0 2006.189.07:53:08.96#ibcon#flushed, iclass 30, count 0 2006.189.07:53:08.96#ibcon#about to write, iclass 30, count 0 2006.189.07:53:08.96#ibcon#wrote, iclass 30, count 0 2006.189.07:53:08.96#ibcon#about to read 3, iclass 30, count 0 2006.189.07:53:08.98#ibcon#read 3, iclass 30, count 0 2006.189.07:53:08.98#ibcon#about to read 4, iclass 30, count 0 2006.189.07:53:08.98#ibcon#read 4, iclass 30, count 0 2006.189.07:53:08.98#ibcon#about to read 5, iclass 30, count 0 2006.189.07:53:08.98#ibcon#read 5, iclass 30, count 0 2006.189.07:53:08.98#ibcon#about to read 6, iclass 30, count 0 2006.189.07:53:08.98#ibcon#read 6, iclass 30, count 0 2006.189.07:53:08.98#ibcon#end of sib2, iclass 30, count 0 2006.189.07:53:08.98#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:53:08.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:53:08.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:53:08.98#ibcon#*before write, iclass 30, count 0 2006.189.07:53:08.98#ibcon#enter sib2, iclass 30, count 0 2006.189.07:53:08.98#ibcon#flushed, iclass 30, count 0 2006.189.07:53:08.98#ibcon#about to write, iclass 30, count 0 2006.189.07:53:08.98#ibcon#wrote, iclass 30, count 0 2006.189.07:53:08.98#ibcon#about to read 3, iclass 30, count 0 2006.189.07:53:09.02#ibcon#read 3, iclass 30, count 0 2006.189.07:53:09.02#ibcon#about to read 4, iclass 30, count 0 2006.189.07:53:09.02#ibcon#read 4, iclass 30, count 0 2006.189.07:53:09.02#ibcon#about to read 5, iclass 30, count 0 2006.189.07:53:09.02#ibcon#read 5, iclass 30, count 0 2006.189.07:53:09.02#ibcon#about to read 6, iclass 30, count 0 2006.189.07:53:09.02#ibcon#read 6, iclass 30, count 0 2006.189.07:53:09.02#ibcon#end of sib2, iclass 30, count 0 2006.189.07:53:09.02#ibcon#*after write, iclass 30, count 0 2006.189.07:53:09.02#ibcon#*before return 0, iclass 30, count 0 2006.189.07:53:09.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:09.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:09.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:53:09.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:53:09.02$vc4f8/va=4,7 2006.189.07:53:09.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.07:53:09.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.07:53:09.02#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:09.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:53:09.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:53:09.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:53:09.08#ibcon#enter wrdev, iclass 32, count 2 2006.189.07:53:09.08#ibcon#first serial, iclass 32, count 2 2006.189.07:53:09.08#ibcon#enter sib2, iclass 32, count 2 2006.189.07:53:09.08#ibcon#flushed, iclass 32, count 2 2006.189.07:53:09.08#ibcon#about to write, iclass 32, count 2 2006.189.07:53:09.08#ibcon#wrote, iclass 32, count 2 2006.189.07:53:09.08#ibcon#about to read 3, iclass 32, count 2 2006.189.07:53:09.10#ibcon#read 3, iclass 32, count 2 2006.189.07:53:09.10#ibcon#about to read 4, iclass 32, count 2 2006.189.07:53:09.10#ibcon#read 4, iclass 32, count 2 2006.189.07:53:09.10#ibcon#about to read 5, iclass 32, count 2 2006.189.07:53:09.10#ibcon#read 5, iclass 32, count 2 2006.189.07:53:09.10#ibcon#about to read 6, iclass 32, count 2 2006.189.07:53:09.10#ibcon#read 6, iclass 32, count 2 2006.189.07:53:09.10#ibcon#end of sib2, iclass 32, count 2 2006.189.07:53:09.10#ibcon#*mode == 0, iclass 32, count 2 2006.189.07:53:09.10#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.07:53:09.10#ibcon#[25=AT04-07\r\n] 2006.189.07:53:09.10#ibcon#*before write, iclass 32, count 2 2006.189.07:53:09.10#ibcon#enter sib2, iclass 32, count 2 2006.189.07:53:09.10#ibcon#flushed, iclass 32, count 2 2006.189.07:53:09.10#ibcon#about to write, iclass 32, count 2 2006.189.07:53:09.10#ibcon#wrote, iclass 32, count 2 2006.189.07:53:09.10#ibcon#about to read 3, iclass 32, count 2 2006.189.07:53:09.13#ibcon#read 3, iclass 32, count 2 2006.189.07:53:09.13#ibcon#about to read 4, iclass 32, count 2 2006.189.07:53:09.13#ibcon#read 4, iclass 32, count 2 2006.189.07:53:09.13#ibcon#about to read 5, iclass 32, count 2 2006.189.07:53:09.13#ibcon#read 5, iclass 32, count 2 2006.189.07:53:09.13#ibcon#about to read 6, iclass 32, count 2 2006.189.07:53:09.13#ibcon#read 6, iclass 32, count 2 2006.189.07:53:09.13#ibcon#end of sib2, iclass 32, count 2 2006.189.07:53:09.13#ibcon#*after write, iclass 32, count 2 2006.189.07:53:09.13#ibcon#*before return 0, iclass 32, count 2 2006.189.07:53:09.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:53:09.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:53:09.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.07:53:09.13#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:09.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:53:09.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:53:09.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:53:09.25#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:53:09.25#ibcon#first serial, iclass 32, count 0 2006.189.07:53:09.25#ibcon#enter sib2, iclass 32, count 0 2006.189.07:53:09.25#ibcon#flushed, iclass 32, count 0 2006.189.07:53:09.25#ibcon#about to write, iclass 32, count 0 2006.189.07:53:09.25#ibcon#wrote, iclass 32, count 0 2006.189.07:53:09.25#ibcon#about to read 3, iclass 32, count 0 2006.189.07:53:09.27#ibcon#read 3, iclass 32, count 0 2006.189.07:53:09.27#ibcon#about to read 4, iclass 32, count 0 2006.189.07:53:09.27#ibcon#read 4, iclass 32, count 0 2006.189.07:53:09.27#ibcon#about to read 5, iclass 32, count 0 2006.189.07:53:09.27#ibcon#read 5, iclass 32, count 0 2006.189.07:53:09.27#ibcon#about to read 6, iclass 32, count 0 2006.189.07:53:09.27#ibcon#read 6, iclass 32, count 0 2006.189.07:53:09.27#ibcon#end of sib2, iclass 32, count 0 2006.189.07:53:09.27#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:53:09.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:53:09.27#ibcon#[25=USB\r\n] 2006.189.07:53:09.27#ibcon#*before write, iclass 32, count 0 2006.189.07:53:09.27#ibcon#enter sib2, iclass 32, count 0 2006.189.07:53:09.27#ibcon#flushed, iclass 32, count 0 2006.189.07:53:09.27#ibcon#about to write, iclass 32, count 0 2006.189.07:53:09.27#ibcon#wrote, iclass 32, count 0 2006.189.07:53:09.27#ibcon#about to read 3, iclass 32, count 0 2006.189.07:53:09.30#ibcon#read 3, iclass 32, count 0 2006.189.07:53:09.30#ibcon#about to read 4, iclass 32, count 0 2006.189.07:53:09.30#ibcon#read 4, iclass 32, count 0 2006.189.07:53:09.30#ibcon#about to read 5, iclass 32, count 0 2006.189.07:53:09.30#ibcon#read 5, iclass 32, count 0 2006.189.07:53:09.30#ibcon#about to read 6, iclass 32, count 0 2006.189.07:53:09.30#ibcon#read 6, iclass 32, count 0 2006.189.07:53:09.30#ibcon#end of sib2, iclass 32, count 0 2006.189.07:53:09.30#ibcon#*after write, iclass 32, count 0 2006.189.07:53:09.30#ibcon#*before return 0, iclass 32, count 0 2006.189.07:53:09.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:53:09.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:53:09.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:53:09.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:53:09.30$vc4f8/valo=5,652.99 2006.189.07:53:09.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.07:53:09.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.07:53:09.30#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:09.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:53:09.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:53:09.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:53:09.30#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:53:09.30#ibcon#first serial, iclass 34, count 0 2006.189.07:53:09.30#ibcon#enter sib2, iclass 34, count 0 2006.189.07:53:09.30#ibcon#flushed, iclass 34, count 0 2006.189.07:53:09.30#ibcon#about to write, iclass 34, count 0 2006.189.07:53:09.30#ibcon#wrote, iclass 34, count 0 2006.189.07:53:09.30#ibcon#about to read 3, iclass 34, count 0 2006.189.07:53:09.32#ibcon#read 3, iclass 34, count 0 2006.189.07:53:09.32#ibcon#about to read 4, iclass 34, count 0 2006.189.07:53:09.32#ibcon#read 4, iclass 34, count 0 2006.189.07:53:09.32#ibcon#about to read 5, iclass 34, count 0 2006.189.07:53:09.32#ibcon#read 5, iclass 34, count 0 2006.189.07:53:09.32#ibcon#about to read 6, iclass 34, count 0 2006.189.07:53:09.32#ibcon#read 6, iclass 34, count 0 2006.189.07:53:09.32#ibcon#end of sib2, iclass 34, count 0 2006.189.07:53:09.32#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:53:09.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:53:09.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:53:09.32#ibcon#*before write, iclass 34, count 0 2006.189.07:53:09.32#ibcon#enter sib2, iclass 34, count 0 2006.189.07:53:09.32#ibcon#flushed, iclass 34, count 0 2006.189.07:53:09.32#ibcon#about to write, iclass 34, count 0 2006.189.07:53:09.32#ibcon#wrote, iclass 34, count 0 2006.189.07:53:09.32#ibcon#about to read 3, iclass 34, count 0 2006.189.07:53:09.36#ibcon#read 3, iclass 34, count 0 2006.189.07:53:09.36#ibcon#about to read 4, iclass 34, count 0 2006.189.07:53:09.36#ibcon#read 4, iclass 34, count 0 2006.189.07:53:09.36#ibcon#about to read 5, iclass 34, count 0 2006.189.07:53:09.36#ibcon#read 5, iclass 34, count 0 2006.189.07:53:09.36#ibcon#about to read 6, iclass 34, count 0 2006.189.07:53:09.36#ibcon#read 6, iclass 34, count 0 2006.189.07:53:09.36#ibcon#end of sib2, iclass 34, count 0 2006.189.07:53:09.36#ibcon#*after write, iclass 34, count 0 2006.189.07:53:09.36#ibcon#*before return 0, iclass 34, count 0 2006.189.07:53:09.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:53:09.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:53:09.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:53:09.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:53:09.36$vc4f8/va=5,7 2006.189.07:53:09.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.07:53:09.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.07:53:09.36#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:09.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:53:09.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:53:09.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:53:09.42#ibcon#enter wrdev, iclass 36, count 2 2006.189.07:53:09.42#ibcon#first serial, iclass 36, count 2 2006.189.07:53:09.42#ibcon#enter sib2, iclass 36, count 2 2006.189.07:53:09.42#ibcon#flushed, iclass 36, count 2 2006.189.07:53:09.42#ibcon#about to write, iclass 36, count 2 2006.189.07:53:09.42#ibcon#wrote, iclass 36, count 2 2006.189.07:53:09.42#ibcon#about to read 3, iclass 36, count 2 2006.189.07:53:09.44#ibcon#read 3, iclass 36, count 2 2006.189.07:53:09.44#ibcon#about to read 4, iclass 36, count 2 2006.189.07:53:09.44#ibcon#read 4, iclass 36, count 2 2006.189.07:53:09.44#ibcon#about to read 5, iclass 36, count 2 2006.189.07:53:09.44#ibcon#read 5, iclass 36, count 2 2006.189.07:53:09.44#ibcon#about to read 6, iclass 36, count 2 2006.189.07:53:09.44#ibcon#read 6, iclass 36, count 2 2006.189.07:53:09.44#ibcon#end of sib2, iclass 36, count 2 2006.189.07:53:09.44#ibcon#*mode == 0, iclass 36, count 2 2006.189.07:53:09.44#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.07:53:09.44#ibcon#[25=AT05-07\r\n] 2006.189.07:53:09.44#ibcon#*before write, iclass 36, count 2 2006.189.07:53:09.44#ibcon#enter sib2, iclass 36, count 2 2006.189.07:53:09.44#ibcon#flushed, iclass 36, count 2 2006.189.07:53:09.44#ibcon#about to write, iclass 36, count 2 2006.189.07:53:09.44#ibcon#wrote, iclass 36, count 2 2006.189.07:53:09.44#ibcon#about to read 3, iclass 36, count 2 2006.189.07:53:09.47#ibcon#read 3, iclass 36, count 2 2006.189.07:53:09.47#ibcon#about to read 4, iclass 36, count 2 2006.189.07:53:09.47#ibcon#read 4, iclass 36, count 2 2006.189.07:53:09.47#ibcon#about to read 5, iclass 36, count 2 2006.189.07:53:09.47#ibcon#read 5, iclass 36, count 2 2006.189.07:53:09.47#ibcon#about to read 6, iclass 36, count 2 2006.189.07:53:09.47#ibcon#read 6, iclass 36, count 2 2006.189.07:53:09.47#ibcon#end of sib2, iclass 36, count 2 2006.189.07:53:09.47#ibcon#*after write, iclass 36, count 2 2006.189.07:53:09.47#ibcon#*before return 0, iclass 36, count 2 2006.189.07:53:09.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:53:09.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:53:09.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.07:53:09.47#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:09.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:53:09.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:53:09.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:53:09.59#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:53:09.59#ibcon#first serial, iclass 36, count 0 2006.189.07:53:09.59#ibcon#enter sib2, iclass 36, count 0 2006.189.07:53:09.59#ibcon#flushed, iclass 36, count 0 2006.189.07:53:09.59#ibcon#about to write, iclass 36, count 0 2006.189.07:53:09.59#ibcon#wrote, iclass 36, count 0 2006.189.07:53:09.59#ibcon#about to read 3, iclass 36, count 0 2006.189.07:53:09.61#ibcon#read 3, iclass 36, count 0 2006.189.07:53:09.61#ibcon#about to read 4, iclass 36, count 0 2006.189.07:53:09.61#ibcon#read 4, iclass 36, count 0 2006.189.07:53:09.61#ibcon#about to read 5, iclass 36, count 0 2006.189.07:53:09.61#ibcon#read 5, iclass 36, count 0 2006.189.07:53:09.61#ibcon#about to read 6, iclass 36, count 0 2006.189.07:53:09.61#ibcon#read 6, iclass 36, count 0 2006.189.07:53:09.61#ibcon#end of sib2, iclass 36, count 0 2006.189.07:53:09.61#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:53:09.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:53:09.61#ibcon#[25=USB\r\n] 2006.189.07:53:09.61#ibcon#*before write, iclass 36, count 0 2006.189.07:53:09.61#ibcon#enter sib2, iclass 36, count 0 2006.189.07:53:09.61#ibcon#flushed, iclass 36, count 0 2006.189.07:53:09.61#ibcon#about to write, iclass 36, count 0 2006.189.07:53:09.61#ibcon#wrote, iclass 36, count 0 2006.189.07:53:09.61#ibcon#about to read 3, iclass 36, count 0 2006.189.07:53:09.64#ibcon#read 3, iclass 36, count 0 2006.189.07:53:09.64#ibcon#about to read 4, iclass 36, count 0 2006.189.07:53:09.64#ibcon#read 4, iclass 36, count 0 2006.189.07:53:09.64#ibcon#about to read 5, iclass 36, count 0 2006.189.07:53:09.64#ibcon#read 5, iclass 36, count 0 2006.189.07:53:09.64#ibcon#about to read 6, iclass 36, count 0 2006.189.07:53:09.64#ibcon#read 6, iclass 36, count 0 2006.189.07:53:09.64#ibcon#end of sib2, iclass 36, count 0 2006.189.07:53:09.64#ibcon#*after write, iclass 36, count 0 2006.189.07:53:09.64#ibcon#*before return 0, iclass 36, count 0 2006.189.07:53:09.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:53:09.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:53:09.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:53:09.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:53:09.64$vc4f8/valo=6,772.99 2006.189.07:53:09.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.07:53:09.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.07:53:09.64#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:09.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:09.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:09.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:09.64#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:53:09.64#ibcon#first serial, iclass 38, count 0 2006.189.07:53:09.64#ibcon#enter sib2, iclass 38, count 0 2006.189.07:53:09.64#ibcon#flushed, iclass 38, count 0 2006.189.07:53:09.64#ibcon#about to write, iclass 38, count 0 2006.189.07:53:09.64#ibcon#wrote, iclass 38, count 0 2006.189.07:53:09.64#ibcon#about to read 3, iclass 38, count 0 2006.189.07:53:09.66#ibcon#read 3, iclass 38, count 0 2006.189.07:53:09.66#ibcon#about to read 4, iclass 38, count 0 2006.189.07:53:09.66#ibcon#read 4, iclass 38, count 0 2006.189.07:53:09.66#ibcon#about to read 5, iclass 38, count 0 2006.189.07:53:09.66#ibcon#read 5, iclass 38, count 0 2006.189.07:53:09.66#ibcon#about to read 6, iclass 38, count 0 2006.189.07:53:09.66#ibcon#read 6, iclass 38, count 0 2006.189.07:53:09.66#ibcon#end of sib2, iclass 38, count 0 2006.189.07:53:09.66#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:53:09.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:53:09.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:53:09.66#ibcon#*before write, iclass 38, count 0 2006.189.07:53:09.66#ibcon#enter sib2, iclass 38, count 0 2006.189.07:53:09.66#ibcon#flushed, iclass 38, count 0 2006.189.07:53:09.66#ibcon#about to write, iclass 38, count 0 2006.189.07:53:09.66#ibcon#wrote, iclass 38, count 0 2006.189.07:53:09.66#ibcon#about to read 3, iclass 38, count 0 2006.189.07:53:09.70#ibcon#read 3, iclass 38, count 0 2006.189.07:53:09.70#ibcon#about to read 4, iclass 38, count 0 2006.189.07:53:09.70#ibcon#read 4, iclass 38, count 0 2006.189.07:53:09.70#ibcon#about to read 5, iclass 38, count 0 2006.189.07:53:09.70#ibcon#read 5, iclass 38, count 0 2006.189.07:53:09.70#ibcon#about to read 6, iclass 38, count 0 2006.189.07:53:09.70#ibcon#read 6, iclass 38, count 0 2006.189.07:53:09.70#ibcon#end of sib2, iclass 38, count 0 2006.189.07:53:09.70#ibcon#*after write, iclass 38, count 0 2006.189.07:53:09.70#ibcon#*before return 0, iclass 38, count 0 2006.189.07:53:09.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:09.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:09.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:53:09.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:53:09.70$vc4f8/va=6,6 2006.189.07:53:09.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.07:53:09.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.07:53:09.70#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:09.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:09.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:09.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:09.76#ibcon#enter wrdev, iclass 40, count 2 2006.189.07:53:09.76#ibcon#first serial, iclass 40, count 2 2006.189.07:53:09.76#ibcon#enter sib2, iclass 40, count 2 2006.189.07:53:09.76#ibcon#flushed, iclass 40, count 2 2006.189.07:53:09.76#ibcon#about to write, iclass 40, count 2 2006.189.07:53:09.76#ibcon#wrote, iclass 40, count 2 2006.189.07:53:09.76#ibcon#about to read 3, iclass 40, count 2 2006.189.07:53:09.78#ibcon#read 3, iclass 40, count 2 2006.189.07:53:09.78#ibcon#about to read 4, iclass 40, count 2 2006.189.07:53:09.78#ibcon#read 4, iclass 40, count 2 2006.189.07:53:09.78#ibcon#about to read 5, iclass 40, count 2 2006.189.07:53:09.78#ibcon#read 5, iclass 40, count 2 2006.189.07:53:09.78#ibcon#about to read 6, iclass 40, count 2 2006.189.07:53:09.78#ibcon#read 6, iclass 40, count 2 2006.189.07:53:09.78#ibcon#end of sib2, iclass 40, count 2 2006.189.07:53:09.78#ibcon#*mode == 0, iclass 40, count 2 2006.189.07:53:09.78#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.07:53:09.78#ibcon#[25=AT06-06\r\n] 2006.189.07:53:09.78#ibcon#*before write, iclass 40, count 2 2006.189.07:53:09.78#ibcon#enter sib2, iclass 40, count 2 2006.189.07:53:09.78#ibcon#flushed, iclass 40, count 2 2006.189.07:53:09.78#ibcon#about to write, iclass 40, count 2 2006.189.07:53:09.78#ibcon#wrote, iclass 40, count 2 2006.189.07:53:09.78#ibcon#about to read 3, iclass 40, count 2 2006.189.07:53:09.81#ibcon#read 3, iclass 40, count 2 2006.189.07:53:09.81#ibcon#about to read 4, iclass 40, count 2 2006.189.07:53:09.81#ibcon#read 4, iclass 40, count 2 2006.189.07:53:09.81#ibcon#about to read 5, iclass 40, count 2 2006.189.07:53:09.81#ibcon#read 5, iclass 40, count 2 2006.189.07:53:09.81#ibcon#about to read 6, iclass 40, count 2 2006.189.07:53:09.81#ibcon#read 6, iclass 40, count 2 2006.189.07:53:09.81#ibcon#end of sib2, iclass 40, count 2 2006.189.07:53:09.81#ibcon#*after write, iclass 40, count 2 2006.189.07:53:09.81#ibcon#*before return 0, iclass 40, count 2 2006.189.07:53:09.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:09.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:09.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.07:53:09.81#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:09.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:09.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:09.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:09.93#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:53:09.93#ibcon#first serial, iclass 40, count 0 2006.189.07:53:09.93#ibcon#enter sib2, iclass 40, count 0 2006.189.07:53:09.93#ibcon#flushed, iclass 40, count 0 2006.189.07:53:09.93#ibcon#about to write, iclass 40, count 0 2006.189.07:53:09.93#ibcon#wrote, iclass 40, count 0 2006.189.07:53:09.93#ibcon#about to read 3, iclass 40, count 0 2006.189.07:53:09.95#ibcon#read 3, iclass 40, count 0 2006.189.07:53:09.95#ibcon#about to read 4, iclass 40, count 0 2006.189.07:53:09.95#ibcon#read 4, iclass 40, count 0 2006.189.07:53:09.95#ibcon#about to read 5, iclass 40, count 0 2006.189.07:53:09.95#ibcon#read 5, iclass 40, count 0 2006.189.07:53:09.95#ibcon#about to read 6, iclass 40, count 0 2006.189.07:53:09.95#ibcon#read 6, iclass 40, count 0 2006.189.07:53:09.95#ibcon#end of sib2, iclass 40, count 0 2006.189.07:53:09.95#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:53:09.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:53:09.95#ibcon#[25=USB\r\n] 2006.189.07:53:09.95#ibcon#*before write, iclass 40, count 0 2006.189.07:53:09.95#ibcon#enter sib2, iclass 40, count 0 2006.189.07:53:09.95#ibcon#flushed, iclass 40, count 0 2006.189.07:53:09.95#ibcon#about to write, iclass 40, count 0 2006.189.07:53:09.95#ibcon#wrote, iclass 40, count 0 2006.189.07:53:09.95#ibcon#about to read 3, iclass 40, count 0 2006.189.07:53:09.98#ibcon#read 3, iclass 40, count 0 2006.189.07:53:09.98#ibcon#about to read 4, iclass 40, count 0 2006.189.07:53:09.98#ibcon#read 4, iclass 40, count 0 2006.189.07:53:09.98#ibcon#about to read 5, iclass 40, count 0 2006.189.07:53:09.98#ibcon#read 5, iclass 40, count 0 2006.189.07:53:09.98#ibcon#about to read 6, iclass 40, count 0 2006.189.07:53:09.98#ibcon#read 6, iclass 40, count 0 2006.189.07:53:09.98#ibcon#end of sib2, iclass 40, count 0 2006.189.07:53:09.98#ibcon#*after write, iclass 40, count 0 2006.189.07:53:09.98#ibcon#*before return 0, iclass 40, count 0 2006.189.07:53:09.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:09.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:09.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:53:09.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:53:09.98$vc4f8/valo=7,832.99 2006.189.07:53:09.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:53:09.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:53:09.98#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:09.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:09.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:09.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:09.98#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:53:09.98#ibcon#first serial, iclass 4, count 0 2006.189.07:53:09.98#ibcon#enter sib2, iclass 4, count 0 2006.189.07:53:09.98#ibcon#flushed, iclass 4, count 0 2006.189.07:53:09.98#ibcon#about to write, iclass 4, count 0 2006.189.07:53:09.98#ibcon#wrote, iclass 4, count 0 2006.189.07:53:09.98#ibcon#about to read 3, iclass 4, count 0 2006.189.07:53:10.00#ibcon#read 3, iclass 4, count 0 2006.189.07:53:10.00#ibcon#about to read 4, iclass 4, count 0 2006.189.07:53:10.00#ibcon#read 4, iclass 4, count 0 2006.189.07:53:10.00#ibcon#about to read 5, iclass 4, count 0 2006.189.07:53:10.00#ibcon#read 5, iclass 4, count 0 2006.189.07:53:10.00#ibcon#about to read 6, iclass 4, count 0 2006.189.07:53:10.00#ibcon#read 6, iclass 4, count 0 2006.189.07:53:10.00#ibcon#end of sib2, iclass 4, count 0 2006.189.07:53:10.00#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:53:10.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:53:10.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:53:10.00#ibcon#*before write, iclass 4, count 0 2006.189.07:53:10.00#ibcon#enter sib2, iclass 4, count 0 2006.189.07:53:10.00#ibcon#flushed, iclass 4, count 0 2006.189.07:53:10.00#ibcon#about to write, iclass 4, count 0 2006.189.07:53:10.00#ibcon#wrote, iclass 4, count 0 2006.189.07:53:10.00#ibcon#about to read 3, iclass 4, count 0 2006.189.07:53:10.04#ibcon#read 3, iclass 4, count 0 2006.189.07:53:10.04#ibcon#about to read 4, iclass 4, count 0 2006.189.07:53:10.04#ibcon#read 4, iclass 4, count 0 2006.189.07:53:10.04#ibcon#about to read 5, iclass 4, count 0 2006.189.07:53:10.04#ibcon#read 5, iclass 4, count 0 2006.189.07:53:10.04#ibcon#about to read 6, iclass 4, count 0 2006.189.07:53:10.04#ibcon#read 6, iclass 4, count 0 2006.189.07:53:10.04#ibcon#end of sib2, iclass 4, count 0 2006.189.07:53:10.04#ibcon#*after write, iclass 4, count 0 2006.189.07:53:10.04#ibcon#*before return 0, iclass 4, count 0 2006.189.07:53:10.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:10.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:10.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:53:10.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:53:10.04$vc4f8/va=7,6 2006.189.07:53:10.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.07:53:10.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.07:53:10.04#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:10.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:53:10.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:53:10.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:53:10.10#ibcon#enter wrdev, iclass 6, count 2 2006.189.07:53:10.10#ibcon#first serial, iclass 6, count 2 2006.189.07:53:10.10#ibcon#enter sib2, iclass 6, count 2 2006.189.07:53:10.10#ibcon#flushed, iclass 6, count 2 2006.189.07:53:10.10#ibcon#about to write, iclass 6, count 2 2006.189.07:53:10.10#ibcon#wrote, iclass 6, count 2 2006.189.07:53:10.10#ibcon#about to read 3, iclass 6, count 2 2006.189.07:53:10.12#ibcon#read 3, iclass 6, count 2 2006.189.07:53:10.12#ibcon#about to read 4, iclass 6, count 2 2006.189.07:53:10.12#ibcon#read 4, iclass 6, count 2 2006.189.07:53:10.12#ibcon#about to read 5, iclass 6, count 2 2006.189.07:53:10.12#ibcon#read 5, iclass 6, count 2 2006.189.07:53:10.12#ibcon#about to read 6, iclass 6, count 2 2006.189.07:53:10.12#ibcon#read 6, iclass 6, count 2 2006.189.07:53:10.12#ibcon#end of sib2, iclass 6, count 2 2006.189.07:53:10.12#ibcon#*mode == 0, iclass 6, count 2 2006.189.07:53:10.12#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.07:53:10.12#ibcon#[25=AT07-06\r\n] 2006.189.07:53:10.12#ibcon#*before write, iclass 6, count 2 2006.189.07:53:10.12#ibcon#enter sib2, iclass 6, count 2 2006.189.07:53:10.12#ibcon#flushed, iclass 6, count 2 2006.189.07:53:10.12#ibcon#about to write, iclass 6, count 2 2006.189.07:53:10.12#ibcon#wrote, iclass 6, count 2 2006.189.07:53:10.12#ibcon#about to read 3, iclass 6, count 2 2006.189.07:53:10.15#ibcon#read 3, iclass 6, count 2 2006.189.07:53:10.15#ibcon#about to read 4, iclass 6, count 2 2006.189.07:53:10.15#ibcon#read 4, iclass 6, count 2 2006.189.07:53:10.15#ibcon#about to read 5, iclass 6, count 2 2006.189.07:53:10.15#ibcon#read 5, iclass 6, count 2 2006.189.07:53:10.15#ibcon#about to read 6, iclass 6, count 2 2006.189.07:53:10.15#ibcon#read 6, iclass 6, count 2 2006.189.07:53:10.15#ibcon#end of sib2, iclass 6, count 2 2006.189.07:53:10.15#ibcon#*after write, iclass 6, count 2 2006.189.07:53:10.15#ibcon#*before return 0, iclass 6, count 2 2006.189.07:53:10.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:53:10.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:53:10.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.07:53:10.15#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:10.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:53:10.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:53:10.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:53:10.27#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:53:10.27#ibcon#first serial, iclass 6, count 0 2006.189.07:53:10.27#ibcon#enter sib2, iclass 6, count 0 2006.189.07:53:10.27#ibcon#flushed, iclass 6, count 0 2006.189.07:53:10.27#ibcon#about to write, iclass 6, count 0 2006.189.07:53:10.27#ibcon#wrote, iclass 6, count 0 2006.189.07:53:10.27#ibcon#about to read 3, iclass 6, count 0 2006.189.07:53:10.29#ibcon#read 3, iclass 6, count 0 2006.189.07:53:10.29#ibcon#about to read 4, iclass 6, count 0 2006.189.07:53:10.29#ibcon#read 4, iclass 6, count 0 2006.189.07:53:10.29#ibcon#about to read 5, iclass 6, count 0 2006.189.07:53:10.29#ibcon#read 5, iclass 6, count 0 2006.189.07:53:10.29#ibcon#about to read 6, iclass 6, count 0 2006.189.07:53:10.29#ibcon#read 6, iclass 6, count 0 2006.189.07:53:10.29#ibcon#end of sib2, iclass 6, count 0 2006.189.07:53:10.29#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:53:10.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:53:10.29#ibcon#[25=USB\r\n] 2006.189.07:53:10.29#ibcon#*before write, iclass 6, count 0 2006.189.07:53:10.29#ibcon#enter sib2, iclass 6, count 0 2006.189.07:53:10.29#ibcon#flushed, iclass 6, count 0 2006.189.07:53:10.29#ibcon#about to write, iclass 6, count 0 2006.189.07:53:10.29#ibcon#wrote, iclass 6, count 0 2006.189.07:53:10.29#ibcon#about to read 3, iclass 6, count 0 2006.189.07:53:10.32#ibcon#read 3, iclass 6, count 0 2006.189.07:53:10.32#ibcon#about to read 4, iclass 6, count 0 2006.189.07:53:10.32#ibcon#read 4, iclass 6, count 0 2006.189.07:53:10.32#ibcon#about to read 5, iclass 6, count 0 2006.189.07:53:10.32#ibcon#read 5, iclass 6, count 0 2006.189.07:53:10.32#ibcon#about to read 6, iclass 6, count 0 2006.189.07:53:10.32#ibcon#read 6, iclass 6, count 0 2006.189.07:53:10.32#ibcon#end of sib2, iclass 6, count 0 2006.189.07:53:10.32#ibcon#*after write, iclass 6, count 0 2006.189.07:53:10.32#ibcon#*before return 0, iclass 6, count 0 2006.189.07:53:10.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:53:10.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:53:10.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:53:10.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:53:10.32$vc4f8/valo=8,852.99 2006.189.07:53:10.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.07:53:10.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.07:53:10.32#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:10.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:53:10.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:53:10.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:53:10.32#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:53:10.32#ibcon#first serial, iclass 10, count 0 2006.189.07:53:10.32#ibcon#enter sib2, iclass 10, count 0 2006.189.07:53:10.32#ibcon#flushed, iclass 10, count 0 2006.189.07:53:10.32#ibcon#about to write, iclass 10, count 0 2006.189.07:53:10.32#ibcon#wrote, iclass 10, count 0 2006.189.07:53:10.32#ibcon#about to read 3, iclass 10, count 0 2006.189.07:53:10.34#ibcon#read 3, iclass 10, count 0 2006.189.07:53:10.34#ibcon#about to read 4, iclass 10, count 0 2006.189.07:53:10.34#ibcon#read 4, iclass 10, count 0 2006.189.07:53:10.34#ibcon#about to read 5, iclass 10, count 0 2006.189.07:53:10.34#ibcon#read 5, iclass 10, count 0 2006.189.07:53:10.34#ibcon#about to read 6, iclass 10, count 0 2006.189.07:53:10.34#ibcon#read 6, iclass 10, count 0 2006.189.07:53:10.34#ibcon#end of sib2, iclass 10, count 0 2006.189.07:53:10.34#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:53:10.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:53:10.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:53:10.34#ibcon#*before write, iclass 10, count 0 2006.189.07:53:10.34#ibcon#enter sib2, iclass 10, count 0 2006.189.07:53:10.34#ibcon#flushed, iclass 10, count 0 2006.189.07:53:10.34#ibcon#about to write, iclass 10, count 0 2006.189.07:53:10.34#ibcon#wrote, iclass 10, count 0 2006.189.07:53:10.34#ibcon#about to read 3, iclass 10, count 0 2006.189.07:53:10.38#ibcon#read 3, iclass 10, count 0 2006.189.07:53:10.38#ibcon#about to read 4, iclass 10, count 0 2006.189.07:53:10.38#ibcon#read 4, iclass 10, count 0 2006.189.07:53:10.38#ibcon#about to read 5, iclass 10, count 0 2006.189.07:53:10.38#ibcon#read 5, iclass 10, count 0 2006.189.07:53:10.38#ibcon#about to read 6, iclass 10, count 0 2006.189.07:53:10.38#ibcon#read 6, iclass 10, count 0 2006.189.07:53:10.38#ibcon#end of sib2, iclass 10, count 0 2006.189.07:53:10.38#ibcon#*after write, iclass 10, count 0 2006.189.07:53:10.38#ibcon#*before return 0, iclass 10, count 0 2006.189.07:53:10.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:53:10.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:53:10.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:53:10.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:53:10.38$vc4f8/va=8,6 2006.189.07:53:10.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.07:53:10.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.07:53:10.38#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:10.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:53:10.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:53:10.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:53:10.44#ibcon#enter wrdev, iclass 12, count 2 2006.189.07:53:10.44#ibcon#first serial, iclass 12, count 2 2006.189.07:53:10.44#ibcon#enter sib2, iclass 12, count 2 2006.189.07:53:10.44#ibcon#flushed, iclass 12, count 2 2006.189.07:53:10.44#ibcon#about to write, iclass 12, count 2 2006.189.07:53:10.44#ibcon#wrote, iclass 12, count 2 2006.189.07:53:10.44#ibcon#about to read 3, iclass 12, count 2 2006.189.07:53:10.46#ibcon#read 3, iclass 12, count 2 2006.189.07:53:10.46#ibcon#about to read 4, iclass 12, count 2 2006.189.07:53:10.46#ibcon#read 4, iclass 12, count 2 2006.189.07:53:10.46#ibcon#about to read 5, iclass 12, count 2 2006.189.07:53:10.46#ibcon#read 5, iclass 12, count 2 2006.189.07:53:10.46#ibcon#about to read 6, iclass 12, count 2 2006.189.07:53:10.46#ibcon#read 6, iclass 12, count 2 2006.189.07:53:10.46#ibcon#end of sib2, iclass 12, count 2 2006.189.07:53:10.46#ibcon#*mode == 0, iclass 12, count 2 2006.189.07:53:10.46#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.07:53:10.46#ibcon#[25=AT08-06\r\n] 2006.189.07:53:10.46#ibcon#*before write, iclass 12, count 2 2006.189.07:53:10.46#ibcon#enter sib2, iclass 12, count 2 2006.189.07:53:10.46#ibcon#flushed, iclass 12, count 2 2006.189.07:53:10.46#ibcon#about to write, iclass 12, count 2 2006.189.07:53:10.46#ibcon#wrote, iclass 12, count 2 2006.189.07:53:10.46#ibcon#about to read 3, iclass 12, count 2 2006.189.07:53:10.49#ibcon#read 3, iclass 12, count 2 2006.189.07:53:10.49#ibcon#about to read 4, iclass 12, count 2 2006.189.07:53:10.49#ibcon#read 4, iclass 12, count 2 2006.189.07:53:10.49#ibcon#about to read 5, iclass 12, count 2 2006.189.07:53:10.49#ibcon#read 5, iclass 12, count 2 2006.189.07:53:10.49#ibcon#about to read 6, iclass 12, count 2 2006.189.07:53:10.49#ibcon#read 6, iclass 12, count 2 2006.189.07:53:10.49#ibcon#end of sib2, iclass 12, count 2 2006.189.07:53:10.49#ibcon#*after write, iclass 12, count 2 2006.189.07:53:10.49#ibcon#*before return 0, iclass 12, count 2 2006.189.07:53:10.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:53:10.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:53:10.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.07:53:10.49#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:10.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:53:10.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:53:10.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:53:10.61#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:53:10.61#ibcon#first serial, iclass 12, count 0 2006.189.07:53:10.61#ibcon#enter sib2, iclass 12, count 0 2006.189.07:53:10.61#ibcon#flushed, iclass 12, count 0 2006.189.07:53:10.61#ibcon#about to write, iclass 12, count 0 2006.189.07:53:10.61#ibcon#wrote, iclass 12, count 0 2006.189.07:53:10.61#ibcon#about to read 3, iclass 12, count 0 2006.189.07:53:10.63#ibcon#read 3, iclass 12, count 0 2006.189.07:53:10.63#ibcon#about to read 4, iclass 12, count 0 2006.189.07:53:10.63#ibcon#read 4, iclass 12, count 0 2006.189.07:53:10.63#ibcon#about to read 5, iclass 12, count 0 2006.189.07:53:10.63#ibcon#read 5, iclass 12, count 0 2006.189.07:53:10.63#ibcon#about to read 6, iclass 12, count 0 2006.189.07:53:10.63#ibcon#read 6, iclass 12, count 0 2006.189.07:53:10.63#ibcon#end of sib2, iclass 12, count 0 2006.189.07:53:10.63#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:53:10.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:53:10.63#ibcon#[25=USB\r\n] 2006.189.07:53:10.63#ibcon#*before write, iclass 12, count 0 2006.189.07:53:10.63#ibcon#enter sib2, iclass 12, count 0 2006.189.07:53:10.63#ibcon#flushed, iclass 12, count 0 2006.189.07:53:10.63#ibcon#about to write, iclass 12, count 0 2006.189.07:53:10.63#ibcon#wrote, iclass 12, count 0 2006.189.07:53:10.63#ibcon#about to read 3, iclass 12, count 0 2006.189.07:53:10.66#ibcon#read 3, iclass 12, count 0 2006.189.07:53:10.66#ibcon#about to read 4, iclass 12, count 0 2006.189.07:53:10.66#ibcon#read 4, iclass 12, count 0 2006.189.07:53:10.66#ibcon#about to read 5, iclass 12, count 0 2006.189.07:53:10.66#ibcon#read 5, iclass 12, count 0 2006.189.07:53:10.66#ibcon#about to read 6, iclass 12, count 0 2006.189.07:53:10.66#ibcon#read 6, iclass 12, count 0 2006.189.07:53:10.66#ibcon#end of sib2, iclass 12, count 0 2006.189.07:53:10.66#ibcon#*after write, iclass 12, count 0 2006.189.07:53:10.66#ibcon#*before return 0, iclass 12, count 0 2006.189.07:53:10.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:53:10.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:53:10.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:53:10.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:53:10.66$vc4f8/vblo=1,632.99 2006.189.07:53:10.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.07:53:10.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.07:53:10.66#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:10.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:53:10.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:53:10.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:53:10.66#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:53:10.66#ibcon#first serial, iclass 14, count 0 2006.189.07:53:10.66#ibcon#enter sib2, iclass 14, count 0 2006.189.07:53:10.66#ibcon#flushed, iclass 14, count 0 2006.189.07:53:10.66#ibcon#about to write, iclass 14, count 0 2006.189.07:53:10.66#ibcon#wrote, iclass 14, count 0 2006.189.07:53:10.66#ibcon#about to read 3, iclass 14, count 0 2006.189.07:53:10.68#ibcon#read 3, iclass 14, count 0 2006.189.07:53:10.68#ibcon#about to read 4, iclass 14, count 0 2006.189.07:53:10.68#ibcon#read 4, iclass 14, count 0 2006.189.07:53:10.68#ibcon#about to read 5, iclass 14, count 0 2006.189.07:53:10.68#ibcon#read 5, iclass 14, count 0 2006.189.07:53:10.68#ibcon#about to read 6, iclass 14, count 0 2006.189.07:53:10.68#ibcon#read 6, iclass 14, count 0 2006.189.07:53:10.68#ibcon#end of sib2, iclass 14, count 0 2006.189.07:53:10.68#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:53:10.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:53:10.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:53:10.68#ibcon#*before write, iclass 14, count 0 2006.189.07:53:10.68#ibcon#enter sib2, iclass 14, count 0 2006.189.07:53:10.68#ibcon#flushed, iclass 14, count 0 2006.189.07:53:10.68#ibcon#about to write, iclass 14, count 0 2006.189.07:53:10.68#ibcon#wrote, iclass 14, count 0 2006.189.07:53:10.68#ibcon#about to read 3, iclass 14, count 0 2006.189.07:53:10.72#ibcon#read 3, iclass 14, count 0 2006.189.07:53:10.72#ibcon#about to read 4, iclass 14, count 0 2006.189.07:53:10.72#ibcon#read 4, iclass 14, count 0 2006.189.07:53:10.72#ibcon#about to read 5, iclass 14, count 0 2006.189.07:53:10.72#ibcon#read 5, iclass 14, count 0 2006.189.07:53:10.72#ibcon#about to read 6, iclass 14, count 0 2006.189.07:53:10.72#ibcon#read 6, iclass 14, count 0 2006.189.07:53:10.72#ibcon#end of sib2, iclass 14, count 0 2006.189.07:53:10.72#ibcon#*after write, iclass 14, count 0 2006.189.07:53:10.72#ibcon#*before return 0, iclass 14, count 0 2006.189.07:53:10.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:53:10.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:53:10.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:53:10.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:53:10.72$vc4f8/vb=1,4 2006.189.07:53:10.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.07:53:10.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.07:53:10.72#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:10.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:53:10.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:53:10.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:53:10.72#ibcon#enter wrdev, iclass 16, count 2 2006.189.07:53:10.72#ibcon#first serial, iclass 16, count 2 2006.189.07:53:10.72#ibcon#enter sib2, iclass 16, count 2 2006.189.07:53:10.72#ibcon#flushed, iclass 16, count 2 2006.189.07:53:10.72#ibcon#about to write, iclass 16, count 2 2006.189.07:53:10.72#ibcon#wrote, iclass 16, count 2 2006.189.07:53:10.72#ibcon#about to read 3, iclass 16, count 2 2006.189.07:53:10.74#ibcon#read 3, iclass 16, count 2 2006.189.07:53:10.74#ibcon#about to read 4, iclass 16, count 2 2006.189.07:53:10.74#ibcon#read 4, iclass 16, count 2 2006.189.07:53:10.74#ibcon#about to read 5, iclass 16, count 2 2006.189.07:53:10.74#ibcon#read 5, iclass 16, count 2 2006.189.07:53:10.74#ibcon#about to read 6, iclass 16, count 2 2006.189.07:53:10.74#ibcon#read 6, iclass 16, count 2 2006.189.07:53:10.74#ibcon#end of sib2, iclass 16, count 2 2006.189.07:53:10.74#ibcon#*mode == 0, iclass 16, count 2 2006.189.07:53:10.74#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.07:53:10.74#ibcon#[27=AT01-04\r\n] 2006.189.07:53:10.74#ibcon#*before write, iclass 16, count 2 2006.189.07:53:10.74#ibcon#enter sib2, iclass 16, count 2 2006.189.07:53:10.74#ibcon#flushed, iclass 16, count 2 2006.189.07:53:10.74#ibcon#about to write, iclass 16, count 2 2006.189.07:53:10.74#ibcon#wrote, iclass 16, count 2 2006.189.07:53:10.74#ibcon#about to read 3, iclass 16, count 2 2006.189.07:53:10.77#ibcon#read 3, iclass 16, count 2 2006.189.07:53:10.77#ibcon#about to read 4, iclass 16, count 2 2006.189.07:53:10.77#ibcon#read 4, iclass 16, count 2 2006.189.07:53:10.77#ibcon#about to read 5, iclass 16, count 2 2006.189.07:53:10.77#ibcon#read 5, iclass 16, count 2 2006.189.07:53:10.77#ibcon#about to read 6, iclass 16, count 2 2006.189.07:53:10.77#ibcon#read 6, iclass 16, count 2 2006.189.07:53:10.77#ibcon#end of sib2, iclass 16, count 2 2006.189.07:53:10.77#ibcon#*after write, iclass 16, count 2 2006.189.07:53:10.77#ibcon#*before return 0, iclass 16, count 2 2006.189.07:53:10.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:53:10.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:53:10.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.07:53:10.77#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:10.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:53:10.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:53:10.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:53:10.89#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:53:10.89#ibcon#first serial, iclass 16, count 0 2006.189.07:53:10.89#ibcon#enter sib2, iclass 16, count 0 2006.189.07:53:10.89#ibcon#flushed, iclass 16, count 0 2006.189.07:53:10.89#ibcon#about to write, iclass 16, count 0 2006.189.07:53:10.89#ibcon#wrote, iclass 16, count 0 2006.189.07:53:10.89#ibcon#about to read 3, iclass 16, count 0 2006.189.07:53:10.91#ibcon#read 3, iclass 16, count 0 2006.189.07:53:10.91#ibcon#about to read 4, iclass 16, count 0 2006.189.07:53:10.91#ibcon#read 4, iclass 16, count 0 2006.189.07:53:10.91#ibcon#about to read 5, iclass 16, count 0 2006.189.07:53:10.91#ibcon#read 5, iclass 16, count 0 2006.189.07:53:10.91#ibcon#about to read 6, iclass 16, count 0 2006.189.07:53:10.91#ibcon#read 6, iclass 16, count 0 2006.189.07:53:10.91#ibcon#end of sib2, iclass 16, count 0 2006.189.07:53:10.91#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:53:10.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:53:10.91#ibcon#[27=USB\r\n] 2006.189.07:53:10.91#ibcon#*before write, iclass 16, count 0 2006.189.07:53:10.91#ibcon#enter sib2, iclass 16, count 0 2006.189.07:53:10.91#ibcon#flushed, iclass 16, count 0 2006.189.07:53:10.91#ibcon#about to write, iclass 16, count 0 2006.189.07:53:10.91#ibcon#wrote, iclass 16, count 0 2006.189.07:53:10.91#ibcon#about to read 3, iclass 16, count 0 2006.189.07:53:10.94#ibcon#read 3, iclass 16, count 0 2006.189.07:53:10.94#ibcon#about to read 4, iclass 16, count 0 2006.189.07:53:10.94#ibcon#read 4, iclass 16, count 0 2006.189.07:53:10.94#ibcon#about to read 5, iclass 16, count 0 2006.189.07:53:10.94#ibcon#read 5, iclass 16, count 0 2006.189.07:53:10.94#ibcon#about to read 6, iclass 16, count 0 2006.189.07:53:10.94#ibcon#read 6, iclass 16, count 0 2006.189.07:53:10.94#ibcon#end of sib2, iclass 16, count 0 2006.189.07:53:10.94#ibcon#*after write, iclass 16, count 0 2006.189.07:53:10.94#ibcon#*before return 0, iclass 16, count 0 2006.189.07:53:10.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:53:10.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:53:10.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:53:10.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:53:10.94$vc4f8/vblo=2,640.99 2006.189.07:53:10.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.07:53:10.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.07:53:10.94#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:10.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:10.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:10.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:10.94#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:53:10.94#ibcon#first serial, iclass 18, count 0 2006.189.07:53:10.94#ibcon#enter sib2, iclass 18, count 0 2006.189.07:53:10.94#ibcon#flushed, iclass 18, count 0 2006.189.07:53:10.94#ibcon#about to write, iclass 18, count 0 2006.189.07:53:10.94#ibcon#wrote, iclass 18, count 0 2006.189.07:53:10.94#ibcon#about to read 3, iclass 18, count 0 2006.189.07:53:10.96#ibcon#read 3, iclass 18, count 0 2006.189.07:53:10.96#ibcon#about to read 4, iclass 18, count 0 2006.189.07:53:10.96#ibcon#read 4, iclass 18, count 0 2006.189.07:53:10.96#ibcon#about to read 5, iclass 18, count 0 2006.189.07:53:10.96#ibcon#read 5, iclass 18, count 0 2006.189.07:53:10.96#ibcon#about to read 6, iclass 18, count 0 2006.189.07:53:10.96#ibcon#read 6, iclass 18, count 0 2006.189.07:53:10.96#ibcon#end of sib2, iclass 18, count 0 2006.189.07:53:10.96#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:53:10.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:53:10.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:53:10.96#ibcon#*before write, iclass 18, count 0 2006.189.07:53:10.96#ibcon#enter sib2, iclass 18, count 0 2006.189.07:53:10.96#ibcon#flushed, iclass 18, count 0 2006.189.07:53:10.96#ibcon#about to write, iclass 18, count 0 2006.189.07:53:10.96#ibcon#wrote, iclass 18, count 0 2006.189.07:53:10.96#ibcon#about to read 3, iclass 18, count 0 2006.189.07:53:11.00#ibcon#read 3, iclass 18, count 0 2006.189.07:53:11.00#ibcon#about to read 4, iclass 18, count 0 2006.189.07:53:11.00#ibcon#read 4, iclass 18, count 0 2006.189.07:53:11.00#ibcon#about to read 5, iclass 18, count 0 2006.189.07:53:11.00#ibcon#read 5, iclass 18, count 0 2006.189.07:53:11.00#ibcon#about to read 6, iclass 18, count 0 2006.189.07:53:11.00#ibcon#read 6, iclass 18, count 0 2006.189.07:53:11.00#ibcon#end of sib2, iclass 18, count 0 2006.189.07:53:11.00#ibcon#*after write, iclass 18, count 0 2006.189.07:53:11.00#ibcon#*before return 0, iclass 18, count 0 2006.189.07:53:11.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:11.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:53:11.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:53:11.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:53:11.00$vc4f8/vb=2,4 2006.189.07:53:11.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:53:11.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:53:11.00#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:11.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:11.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:11.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:11.06#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:53:11.06#ibcon#first serial, iclass 20, count 2 2006.189.07:53:11.06#ibcon#enter sib2, iclass 20, count 2 2006.189.07:53:11.06#ibcon#flushed, iclass 20, count 2 2006.189.07:53:11.06#ibcon#about to write, iclass 20, count 2 2006.189.07:53:11.06#ibcon#wrote, iclass 20, count 2 2006.189.07:53:11.06#ibcon#about to read 3, iclass 20, count 2 2006.189.07:53:11.08#ibcon#read 3, iclass 20, count 2 2006.189.07:53:11.08#ibcon#about to read 4, iclass 20, count 2 2006.189.07:53:11.08#ibcon#read 4, iclass 20, count 2 2006.189.07:53:11.08#ibcon#about to read 5, iclass 20, count 2 2006.189.07:53:11.08#ibcon#read 5, iclass 20, count 2 2006.189.07:53:11.08#ibcon#about to read 6, iclass 20, count 2 2006.189.07:53:11.08#ibcon#read 6, iclass 20, count 2 2006.189.07:53:11.08#ibcon#end of sib2, iclass 20, count 2 2006.189.07:53:11.08#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:53:11.08#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:53:11.08#ibcon#[27=AT02-04\r\n] 2006.189.07:53:11.08#ibcon#*before write, iclass 20, count 2 2006.189.07:53:11.08#ibcon#enter sib2, iclass 20, count 2 2006.189.07:53:11.08#ibcon#flushed, iclass 20, count 2 2006.189.07:53:11.08#ibcon#about to write, iclass 20, count 2 2006.189.07:53:11.08#ibcon#wrote, iclass 20, count 2 2006.189.07:53:11.08#ibcon#about to read 3, iclass 20, count 2 2006.189.07:53:11.11#ibcon#read 3, iclass 20, count 2 2006.189.07:53:11.11#ibcon#about to read 4, iclass 20, count 2 2006.189.07:53:11.11#ibcon#read 4, iclass 20, count 2 2006.189.07:53:11.11#ibcon#about to read 5, iclass 20, count 2 2006.189.07:53:11.11#ibcon#read 5, iclass 20, count 2 2006.189.07:53:11.11#ibcon#about to read 6, iclass 20, count 2 2006.189.07:53:11.11#ibcon#read 6, iclass 20, count 2 2006.189.07:53:11.11#ibcon#end of sib2, iclass 20, count 2 2006.189.07:53:11.11#ibcon#*after write, iclass 20, count 2 2006.189.07:53:11.11#ibcon#*before return 0, iclass 20, count 2 2006.189.07:53:11.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:11.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:53:11.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:53:11.11#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:11.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:11.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:11.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:11.23#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:53:11.23#ibcon#first serial, iclass 20, count 0 2006.189.07:53:11.23#ibcon#enter sib2, iclass 20, count 0 2006.189.07:53:11.23#ibcon#flushed, iclass 20, count 0 2006.189.07:53:11.23#ibcon#about to write, iclass 20, count 0 2006.189.07:53:11.23#ibcon#wrote, iclass 20, count 0 2006.189.07:53:11.23#ibcon#about to read 3, iclass 20, count 0 2006.189.07:53:11.25#ibcon#read 3, iclass 20, count 0 2006.189.07:53:11.25#ibcon#about to read 4, iclass 20, count 0 2006.189.07:53:11.25#ibcon#read 4, iclass 20, count 0 2006.189.07:53:11.25#ibcon#about to read 5, iclass 20, count 0 2006.189.07:53:11.25#ibcon#read 5, iclass 20, count 0 2006.189.07:53:11.25#ibcon#about to read 6, iclass 20, count 0 2006.189.07:53:11.25#ibcon#read 6, iclass 20, count 0 2006.189.07:53:11.25#ibcon#end of sib2, iclass 20, count 0 2006.189.07:53:11.25#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:53:11.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:53:11.25#ibcon#[27=USB\r\n] 2006.189.07:53:11.25#ibcon#*before write, iclass 20, count 0 2006.189.07:53:11.25#ibcon#enter sib2, iclass 20, count 0 2006.189.07:53:11.25#ibcon#flushed, iclass 20, count 0 2006.189.07:53:11.25#ibcon#about to write, iclass 20, count 0 2006.189.07:53:11.25#ibcon#wrote, iclass 20, count 0 2006.189.07:53:11.25#ibcon#about to read 3, iclass 20, count 0 2006.189.07:53:11.28#ibcon#read 3, iclass 20, count 0 2006.189.07:53:11.28#ibcon#about to read 4, iclass 20, count 0 2006.189.07:53:11.28#ibcon#read 4, iclass 20, count 0 2006.189.07:53:11.28#ibcon#about to read 5, iclass 20, count 0 2006.189.07:53:11.28#ibcon#read 5, iclass 20, count 0 2006.189.07:53:11.28#ibcon#about to read 6, iclass 20, count 0 2006.189.07:53:11.28#ibcon#read 6, iclass 20, count 0 2006.189.07:53:11.28#ibcon#end of sib2, iclass 20, count 0 2006.189.07:53:11.28#ibcon#*after write, iclass 20, count 0 2006.189.07:53:11.28#ibcon#*before return 0, iclass 20, count 0 2006.189.07:53:11.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:11.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:53:11.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:53:11.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:53:11.28$vc4f8/vblo=3,656.99 2006.189.07:53:11.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:53:11.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:53:11.28#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:11.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:11.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:11.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:11.28#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:53:11.28#ibcon#first serial, iclass 22, count 0 2006.189.07:53:11.28#ibcon#enter sib2, iclass 22, count 0 2006.189.07:53:11.28#ibcon#flushed, iclass 22, count 0 2006.189.07:53:11.28#ibcon#about to write, iclass 22, count 0 2006.189.07:53:11.28#ibcon#wrote, iclass 22, count 0 2006.189.07:53:11.28#ibcon#about to read 3, iclass 22, count 0 2006.189.07:53:11.30#ibcon#read 3, iclass 22, count 0 2006.189.07:53:11.30#ibcon#about to read 4, iclass 22, count 0 2006.189.07:53:11.30#ibcon#read 4, iclass 22, count 0 2006.189.07:53:11.30#ibcon#about to read 5, iclass 22, count 0 2006.189.07:53:11.30#ibcon#read 5, iclass 22, count 0 2006.189.07:53:11.30#ibcon#about to read 6, iclass 22, count 0 2006.189.07:53:11.30#ibcon#read 6, iclass 22, count 0 2006.189.07:53:11.30#ibcon#end of sib2, iclass 22, count 0 2006.189.07:53:11.30#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:53:11.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:53:11.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:53:11.30#ibcon#*before write, iclass 22, count 0 2006.189.07:53:11.30#ibcon#enter sib2, iclass 22, count 0 2006.189.07:53:11.30#ibcon#flushed, iclass 22, count 0 2006.189.07:53:11.30#ibcon#about to write, iclass 22, count 0 2006.189.07:53:11.30#ibcon#wrote, iclass 22, count 0 2006.189.07:53:11.30#ibcon#about to read 3, iclass 22, count 0 2006.189.07:53:11.34#ibcon#read 3, iclass 22, count 0 2006.189.07:53:11.34#ibcon#about to read 4, iclass 22, count 0 2006.189.07:53:11.34#ibcon#read 4, iclass 22, count 0 2006.189.07:53:11.34#ibcon#about to read 5, iclass 22, count 0 2006.189.07:53:11.34#ibcon#read 5, iclass 22, count 0 2006.189.07:53:11.34#ibcon#about to read 6, iclass 22, count 0 2006.189.07:53:11.34#ibcon#read 6, iclass 22, count 0 2006.189.07:53:11.34#ibcon#end of sib2, iclass 22, count 0 2006.189.07:53:11.34#ibcon#*after write, iclass 22, count 0 2006.189.07:53:11.34#ibcon#*before return 0, iclass 22, count 0 2006.189.07:53:11.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:11.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:53:11.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:53:11.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:53:11.34$vc4f8/vb=3,4 2006.189.07:53:11.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:53:11.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:53:11.34#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:11.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:11.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:11.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:11.40#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:53:11.40#ibcon#first serial, iclass 24, count 2 2006.189.07:53:11.40#ibcon#enter sib2, iclass 24, count 2 2006.189.07:53:11.40#ibcon#flushed, iclass 24, count 2 2006.189.07:53:11.40#ibcon#about to write, iclass 24, count 2 2006.189.07:53:11.40#ibcon#wrote, iclass 24, count 2 2006.189.07:53:11.40#ibcon#about to read 3, iclass 24, count 2 2006.189.07:53:11.42#ibcon#read 3, iclass 24, count 2 2006.189.07:53:11.42#ibcon#about to read 4, iclass 24, count 2 2006.189.07:53:11.42#ibcon#read 4, iclass 24, count 2 2006.189.07:53:11.42#ibcon#about to read 5, iclass 24, count 2 2006.189.07:53:11.42#ibcon#read 5, iclass 24, count 2 2006.189.07:53:11.42#ibcon#about to read 6, iclass 24, count 2 2006.189.07:53:11.42#ibcon#read 6, iclass 24, count 2 2006.189.07:53:11.42#ibcon#end of sib2, iclass 24, count 2 2006.189.07:53:11.42#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:53:11.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:53:11.42#ibcon#[27=AT03-04\r\n] 2006.189.07:53:11.42#ibcon#*before write, iclass 24, count 2 2006.189.07:53:11.42#ibcon#enter sib2, iclass 24, count 2 2006.189.07:53:11.42#ibcon#flushed, iclass 24, count 2 2006.189.07:53:11.42#ibcon#about to write, iclass 24, count 2 2006.189.07:53:11.42#ibcon#wrote, iclass 24, count 2 2006.189.07:53:11.42#ibcon#about to read 3, iclass 24, count 2 2006.189.07:53:11.45#ibcon#read 3, iclass 24, count 2 2006.189.07:53:11.45#ibcon#about to read 4, iclass 24, count 2 2006.189.07:53:11.45#ibcon#read 4, iclass 24, count 2 2006.189.07:53:11.45#ibcon#about to read 5, iclass 24, count 2 2006.189.07:53:11.45#ibcon#read 5, iclass 24, count 2 2006.189.07:53:11.45#ibcon#about to read 6, iclass 24, count 2 2006.189.07:53:11.45#ibcon#read 6, iclass 24, count 2 2006.189.07:53:11.45#ibcon#end of sib2, iclass 24, count 2 2006.189.07:53:11.45#ibcon#*after write, iclass 24, count 2 2006.189.07:53:11.45#ibcon#*before return 0, iclass 24, count 2 2006.189.07:53:11.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:11.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:53:11.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:53:11.45#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:11.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:11.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:11.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:11.57#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:53:11.57#ibcon#first serial, iclass 24, count 0 2006.189.07:53:11.57#ibcon#enter sib2, iclass 24, count 0 2006.189.07:53:11.57#ibcon#flushed, iclass 24, count 0 2006.189.07:53:11.57#ibcon#about to write, iclass 24, count 0 2006.189.07:53:11.57#ibcon#wrote, iclass 24, count 0 2006.189.07:53:11.57#ibcon#about to read 3, iclass 24, count 0 2006.189.07:53:11.59#ibcon#read 3, iclass 24, count 0 2006.189.07:53:11.59#ibcon#about to read 4, iclass 24, count 0 2006.189.07:53:11.59#ibcon#read 4, iclass 24, count 0 2006.189.07:53:11.59#ibcon#about to read 5, iclass 24, count 0 2006.189.07:53:11.59#ibcon#read 5, iclass 24, count 0 2006.189.07:53:11.59#ibcon#about to read 6, iclass 24, count 0 2006.189.07:53:11.59#ibcon#read 6, iclass 24, count 0 2006.189.07:53:11.59#ibcon#end of sib2, iclass 24, count 0 2006.189.07:53:11.59#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:53:11.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:53:11.59#ibcon#[27=USB\r\n] 2006.189.07:53:11.59#ibcon#*before write, iclass 24, count 0 2006.189.07:53:11.59#ibcon#enter sib2, iclass 24, count 0 2006.189.07:53:11.59#ibcon#flushed, iclass 24, count 0 2006.189.07:53:11.59#ibcon#about to write, iclass 24, count 0 2006.189.07:53:11.59#ibcon#wrote, iclass 24, count 0 2006.189.07:53:11.59#ibcon#about to read 3, iclass 24, count 0 2006.189.07:53:11.62#ibcon#read 3, iclass 24, count 0 2006.189.07:53:11.62#ibcon#about to read 4, iclass 24, count 0 2006.189.07:53:11.62#ibcon#read 4, iclass 24, count 0 2006.189.07:53:11.62#ibcon#about to read 5, iclass 24, count 0 2006.189.07:53:11.62#ibcon#read 5, iclass 24, count 0 2006.189.07:53:11.62#ibcon#about to read 6, iclass 24, count 0 2006.189.07:53:11.62#ibcon#read 6, iclass 24, count 0 2006.189.07:53:11.62#ibcon#end of sib2, iclass 24, count 0 2006.189.07:53:11.62#ibcon#*after write, iclass 24, count 0 2006.189.07:53:11.62#ibcon#*before return 0, iclass 24, count 0 2006.189.07:53:11.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:11.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:53:11.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:53:11.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:53:11.62$vc4f8/vblo=4,712.99 2006.189.07:53:11.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.07:53:11.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.07:53:11.62#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:11.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:11.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:11.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:11.62#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:53:11.62#ibcon#first serial, iclass 26, count 0 2006.189.07:53:11.62#ibcon#enter sib2, iclass 26, count 0 2006.189.07:53:11.62#ibcon#flushed, iclass 26, count 0 2006.189.07:53:11.62#ibcon#about to write, iclass 26, count 0 2006.189.07:53:11.62#ibcon#wrote, iclass 26, count 0 2006.189.07:53:11.62#ibcon#about to read 3, iclass 26, count 0 2006.189.07:53:11.64#ibcon#read 3, iclass 26, count 0 2006.189.07:53:11.64#ibcon#about to read 4, iclass 26, count 0 2006.189.07:53:11.64#ibcon#read 4, iclass 26, count 0 2006.189.07:53:11.64#ibcon#about to read 5, iclass 26, count 0 2006.189.07:53:11.64#ibcon#read 5, iclass 26, count 0 2006.189.07:53:11.64#ibcon#about to read 6, iclass 26, count 0 2006.189.07:53:11.64#ibcon#read 6, iclass 26, count 0 2006.189.07:53:11.64#ibcon#end of sib2, iclass 26, count 0 2006.189.07:53:11.64#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:53:11.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:53:11.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:53:11.64#ibcon#*before write, iclass 26, count 0 2006.189.07:53:11.64#ibcon#enter sib2, iclass 26, count 0 2006.189.07:53:11.64#ibcon#flushed, iclass 26, count 0 2006.189.07:53:11.64#ibcon#about to write, iclass 26, count 0 2006.189.07:53:11.64#ibcon#wrote, iclass 26, count 0 2006.189.07:53:11.64#ibcon#about to read 3, iclass 26, count 0 2006.189.07:53:11.68#ibcon#read 3, iclass 26, count 0 2006.189.07:53:11.68#ibcon#about to read 4, iclass 26, count 0 2006.189.07:53:11.68#ibcon#read 4, iclass 26, count 0 2006.189.07:53:11.68#ibcon#about to read 5, iclass 26, count 0 2006.189.07:53:11.68#ibcon#read 5, iclass 26, count 0 2006.189.07:53:11.68#ibcon#about to read 6, iclass 26, count 0 2006.189.07:53:11.68#ibcon#read 6, iclass 26, count 0 2006.189.07:53:11.68#ibcon#end of sib2, iclass 26, count 0 2006.189.07:53:11.68#ibcon#*after write, iclass 26, count 0 2006.189.07:53:11.68#ibcon#*before return 0, iclass 26, count 0 2006.189.07:53:11.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:11.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:53:11.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:53:11.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:53:11.68$vc4f8/vb=4,4 2006.189.07:53:11.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.07:53:11.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.07:53:11.68#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:11.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:11.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:11.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:11.74#ibcon#enter wrdev, iclass 28, count 2 2006.189.07:53:11.74#ibcon#first serial, iclass 28, count 2 2006.189.07:53:11.74#ibcon#enter sib2, iclass 28, count 2 2006.189.07:53:11.74#ibcon#flushed, iclass 28, count 2 2006.189.07:53:11.74#ibcon#about to write, iclass 28, count 2 2006.189.07:53:11.74#ibcon#wrote, iclass 28, count 2 2006.189.07:53:11.74#ibcon#about to read 3, iclass 28, count 2 2006.189.07:53:11.76#ibcon#read 3, iclass 28, count 2 2006.189.07:53:11.76#ibcon#about to read 4, iclass 28, count 2 2006.189.07:53:11.76#ibcon#read 4, iclass 28, count 2 2006.189.07:53:11.76#ibcon#about to read 5, iclass 28, count 2 2006.189.07:53:11.76#ibcon#read 5, iclass 28, count 2 2006.189.07:53:11.76#ibcon#about to read 6, iclass 28, count 2 2006.189.07:53:11.76#ibcon#read 6, iclass 28, count 2 2006.189.07:53:11.76#ibcon#end of sib2, iclass 28, count 2 2006.189.07:53:11.76#ibcon#*mode == 0, iclass 28, count 2 2006.189.07:53:11.76#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.07:53:11.76#ibcon#[27=AT04-04\r\n] 2006.189.07:53:11.76#ibcon#*before write, iclass 28, count 2 2006.189.07:53:11.76#ibcon#enter sib2, iclass 28, count 2 2006.189.07:53:11.76#ibcon#flushed, iclass 28, count 2 2006.189.07:53:11.76#ibcon#about to write, iclass 28, count 2 2006.189.07:53:11.76#ibcon#wrote, iclass 28, count 2 2006.189.07:53:11.76#ibcon#about to read 3, iclass 28, count 2 2006.189.07:53:11.79#ibcon#read 3, iclass 28, count 2 2006.189.07:53:11.79#ibcon#about to read 4, iclass 28, count 2 2006.189.07:53:11.79#ibcon#read 4, iclass 28, count 2 2006.189.07:53:11.79#ibcon#about to read 5, iclass 28, count 2 2006.189.07:53:11.79#ibcon#read 5, iclass 28, count 2 2006.189.07:53:11.79#ibcon#about to read 6, iclass 28, count 2 2006.189.07:53:11.79#ibcon#read 6, iclass 28, count 2 2006.189.07:53:11.79#ibcon#end of sib2, iclass 28, count 2 2006.189.07:53:11.79#ibcon#*after write, iclass 28, count 2 2006.189.07:53:11.79#ibcon#*before return 0, iclass 28, count 2 2006.189.07:53:11.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:11.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:53:11.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.07:53:11.79#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:11.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:11.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:11.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:11.91#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:53:11.91#ibcon#first serial, iclass 28, count 0 2006.189.07:53:11.91#ibcon#enter sib2, iclass 28, count 0 2006.189.07:53:11.91#ibcon#flushed, iclass 28, count 0 2006.189.07:53:11.91#ibcon#about to write, iclass 28, count 0 2006.189.07:53:11.91#ibcon#wrote, iclass 28, count 0 2006.189.07:53:11.91#ibcon#about to read 3, iclass 28, count 0 2006.189.07:53:11.93#ibcon#read 3, iclass 28, count 0 2006.189.07:53:11.93#ibcon#about to read 4, iclass 28, count 0 2006.189.07:53:11.93#ibcon#read 4, iclass 28, count 0 2006.189.07:53:11.93#ibcon#about to read 5, iclass 28, count 0 2006.189.07:53:11.93#ibcon#read 5, iclass 28, count 0 2006.189.07:53:11.93#ibcon#about to read 6, iclass 28, count 0 2006.189.07:53:11.93#ibcon#read 6, iclass 28, count 0 2006.189.07:53:11.93#ibcon#end of sib2, iclass 28, count 0 2006.189.07:53:11.93#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:53:11.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:53:11.93#ibcon#[27=USB\r\n] 2006.189.07:53:11.93#ibcon#*before write, iclass 28, count 0 2006.189.07:53:11.93#ibcon#enter sib2, iclass 28, count 0 2006.189.07:53:11.93#ibcon#flushed, iclass 28, count 0 2006.189.07:53:11.93#ibcon#about to write, iclass 28, count 0 2006.189.07:53:11.93#ibcon#wrote, iclass 28, count 0 2006.189.07:53:11.93#ibcon#about to read 3, iclass 28, count 0 2006.189.07:53:11.96#ibcon#read 3, iclass 28, count 0 2006.189.07:53:11.96#ibcon#about to read 4, iclass 28, count 0 2006.189.07:53:11.96#ibcon#read 4, iclass 28, count 0 2006.189.07:53:11.96#ibcon#about to read 5, iclass 28, count 0 2006.189.07:53:11.96#ibcon#read 5, iclass 28, count 0 2006.189.07:53:11.96#ibcon#about to read 6, iclass 28, count 0 2006.189.07:53:11.96#ibcon#read 6, iclass 28, count 0 2006.189.07:53:11.96#ibcon#end of sib2, iclass 28, count 0 2006.189.07:53:11.96#ibcon#*after write, iclass 28, count 0 2006.189.07:53:11.96#ibcon#*before return 0, iclass 28, count 0 2006.189.07:53:11.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:11.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:53:11.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:53:11.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:53:11.96$vc4f8/vblo=5,744.99 2006.189.07:53:11.96#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.07:53:11.96#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.07:53:11.96#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:11.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:11.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:11.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:11.96#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:53:11.96#ibcon#first serial, iclass 30, count 0 2006.189.07:53:11.96#ibcon#enter sib2, iclass 30, count 0 2006.189.07:53:11.96#ibcon#flushed, iclass 30, count 0 2006.189.07:53:11.96#ibcon#about to write, iclass 30, count 0 2006.189.07:53:11.96#ibcon#wrote, iclass 30, count 0 2006.189.07:53:11.96#ibcon#about to read 3, iclass 30, count 0 2006.189.07:53:11.98#ibcon#read 3, iclass 30, count 0 2006.189.07:53:11.98#ibcon#about to read 4, iclass 30, count 0 2006.189.07:53:11.98#ibcon#read 4, iclass 30, count 0 2006.189.07:53:11.98#ibcon#about to read 5, iclass 30, count 0 2006.189.07:53:11.98#ibcon#read 5, iclass 30, count 0 2006.189.07:53:11.98#ibcon#about to read 6, iclass 30, count 0 2006.189.07:53:11.98#ibcon#read 6, iclass 30, count 0 2006.189.07:53:11.98#ibcon#end of sib2, iclass 30, count 0 2006.189.07:53:11.98#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:53:11.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:53:11.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:53:11.98#ibcon#*before write, iclass 30, count 0 2006.189.07:53:11.98#ibcon#enter sib2, iclass 30, count 0 2006.189.07:53:11.98#ibcon#flushed, iclass 30, count 0 2006.189.07:53:11.98#ibcon#about to write, iclass 30, count 0 2006.189.07:53:11.98#ibcon#wrote, iclass 30, count 0 2006.189.07:53:11.98#ibcon#about to read 3, iclass 30, count 0 2006.189.07:53:12.02#ibcon#read 3, iclass 30, count 0 2006.189.07:53:12.02#ibcon#about to read 4, iclass 30, count 0 2006.189.07:53:12.02#ibcon#read 4, iclass 30, count 0 2006.189.07:53:12.02#ibcon#about to read 5, iclass 30, count 0 2006.189.07:53:12.02#ibcon#read 5, iclass 30, count 0 2006.189.07:53:12.02#ibcon#about to read 6, iclass 30, count 0 2006.189.07:53:12.02#ibcon#read 6, iclass 30, count 0 2006.189.07:53:12.02#ibcon#end of sib2, iclass 30, count 0 2006.189.07:53:12.02#ibcon#*after write, iclass 30, count 0 2006.189.07:53:12.02#ibcon#*before return 0, iclass 30, count 0 2006.189.07:53:12.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:12.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:53:12.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:53:12.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:53:12.02$vc4f8/vb=5,4 2006.189.07:53:12.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.07:53:12.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.07:53:12.02#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:12.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:53:12.04#abcon#<5=/04 4.4 8.4 25.88 901009.1\r\n> 2006.189.07:53:12.06#abcon#{5=INTERFACE CLEAR} 2006.189.07:53:12.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:53:12.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:53:12.08#ibcon#enter wrdev, iclass 33, count 2 2006.189.07:53:12.08#ibcon#first serial, iclass 33, count 2 2006.189.07:53:12.08#ibcon#enter sib2, iclass 33, count 2 2006.189.07:53:12.08#ibcon#flushed, iclass 33, count 2 2006.189.07:53:12.08#ibcon#about to write, iclass 33, count 2 2006.189.07:53:12.08#ibcon#wrote, iclass 33, count 2 2006.189.07:53:12.08#ibcon#about to read 3, iclass 33, count 2 2006.189.07:53:12.10#ibcon#read 3, iclass 33, count 2 2006.189.07:53:12.10#ibcon#about to read 4, iclass 33, count 2 2006.189.07:53:12.10#ibcon#read 4, iclass 33, count 2 2006.189.07:53:12.10#ibcon#about to read 5, iclass 33, count 2 2006.189.07:53:12.10#ibcon#read 5, iclass 33, count 2 2006.189.07:53:12.10#ibcon#about to read 6, iclass 33, count 2 2006.189.07:53:12.10#ibcon#read 6, iclass 33, count 2 2006.189.07:53:12.10#ibcon#end of sib2, iclass 33, count 2 2006.189.07:53:12.10#ibcon#*mode == 0, iclass 33, count 2 2006.189.07:53:12.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.07:53:12.10#ibcon#[27=AT05-04\r\n] 2006.189.07:53:12.10#ibcon#*before write, iclass 33, count 2 2006.189.07:53:12.10#ibcon#enter sib2, iclass 33, count 2 2006.189.07:53:12.10#ibcon#flushed, iclass 33, count 2 2006.189.07:53:12.10#ibcon#about to write, iclass 33, count 2 2006.189.07:53:12.10#ibcon#wrote, iclass 33, count 2 2006.189.07:53:12.10#ibcon#about to read 3, iclass 33, count 2 2006.189.07:53:12.12#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:53:12.13#ibcon#read 3, iclass 33, count 2 2006.189.07:53:12.13#ibcon#about to read 4, iclass 33, count 2 2006.189.07:53:12.13#ibcon#read 4, iclass 33, count 2 2006.189.07:53:12.13#ibcon#about to read 5, iclass 33, count 2 2006.189.07:53:12.13#ibcon#read 5, iclass 33, count 2 2006.189.07:53:12.13#ibcon#about to read 6, iclass 33, count 2 2006.189.07:53:12.13#ibcon#read 6, iclass 33, count 2 2006.189.07:53:12.13#ibcon#end of sib2, iclass 33, count 2 2006.189.07:53:12.13#ibcon#*after write, iclass 33, count 2 2006.189.07:53:12.13#ibcon#*before return 0, iclass 33, count 2 2006.189.07:53:12.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:53:12.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.07:53:12.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.07:53:12.13#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:12.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:53:12.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:53:12.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:53:12.25#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:53:12.25#ibcon#first serial, iclass 33, count 0 2006.189.07:53:12.25#ibcon#enter sib2, iclass 33, count 0 2006.189.07:53:12.25#ibcon#flushed, iclass 33, count 0 2006.189.07:53:12.25#ibcon#about to write, iclass 33, count 0 2006.189.07:53:12.25#ibcon#wrote, iclass 33, count 0 2006.189.07:53:12.25#ibcon#about to read 3, iclass 33, count 0 2006.189.07:53:12.27#ibcon#read 3, iclass 33, count 0 2006.189.07:53:12.27#ibcon#about to read 4, iclass 33, count 0 2006.189.07:53:12.27#ibcon#read 4, iclass 33, count 0 2006.189.07:53:12.27#ibcon#about to read 5, iclass 33, count 0 2006.189.07:53:12.27#ibcon#read 5, iclass 33, count 0 2006.189.07:53:12.27#ibcon#about to read 6, iclass 33, count 0 2006.189.07:53:12.27#ibcon#read 6, iclass 33, count 0 2006.189.07:53:12.27#ibcon#end of sib2, iclass 33, count 0 2006.189.07:53:12.27#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:53:12.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:53:12.27#ibcon#[27=USB\r\n] 2006.189.07:53:12.27#ibcon#*before write, iclass 33, count 0 2006.189.07:53:12.27#ibcon#enter sib2, iclass 33, count 0 2006.189.07:53:12.27#ibcon#flushed, iclass 33, count 0 2006.189.07:53:12.27#ibcon#about to write, iclass 33, count 0 2006.189.07:53:12.27#ibcon#wrote, iclass 33, count 0 2006.189.07:53:12.27#ibcon#about to read 3, iclass 33, count 0 2006.189.07:53:12.30#ibcon#read 3, iclass 33, count 0 2006.189.07:53:12.30#ibcon#about to read 4, iclass 33, count 0 2006.189.07:53:12.30#ibcon#read 4, iclass 33, count 0 2006.189.07:53:12.30#ibcon#about to read 5, iclass 33, count 0 2006.189.07:53:12.30#ibcon#read 5, iclass 33, count 0 2006.189.07:53:12.30#ibcon#about to read 6, iclass 33, count 0 2006.189.07:53:12.30#ibcon#read 6, iclass 33, count 0 2006.189.07:53:12.30#ibcon#end of sib2, iclass 33, count 0 2006.189.07:53:12.30#ibcon#*after write, iclass 33, count 0 2006.189.07:53:12.30#ibcon#*before return 0, iclass 33, count 0 2006.189.07:53:12.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:53:12.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.07:53:12.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:53:12.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:53:12.30$vc4f8/vblo=6,752.99 2006.189.07:53:12.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.07:53:12.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.07:53:12.30#ibcon#ireg 17 cls_cnt 0 2006.189.07:53:12.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:12.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:12.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:12.30#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:53:12.30#ibcon#first serial, iclass 38, count 0 2006.189.07:53:12.30#ibcon#enter sib2, iclass 38, count 0 2006.189.07:53:12.30#ibcon#flushed, iclass 38, count 0 2006.189.07:53:12.30#ibcon#about to write, iclass 38, count 0 2006.189.07:53:12.30#ibcon#wrote, iclass 38, count 0 2006.189.07:53:12.30#ibcon#about to read 3, iclass 38, count 0 2006.189.07:53:12.32#ibcon#read 3, iclass 38, count 0 2006.189.07:53:12.32#ibcon#about to read 4, iclass 38, count 0 2006.189.07:53:12.32#ibcon#read 4, iclass 38, count 0 2006.189.07:53:12.32#ibcon#about to read 5, iclass 38, count 0 2006.189.07:53:12.32#ibcon#read 5, iclass 38, count 0 2006.189.07:53:12.32#ibcon#about to read 6, iclass 38, count 0 2006.189.07:53:12.32#ibcon#read 6, iclass 38, count 0 2006.189.07:53:12.32#ibcon#end of sib2, iclass 38, count 0 2006.189.07:53:12.32#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:53:12.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:53:12.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:53:12.32#ibcon#*before write, iclass 38, count 0 2006.189.07:53:12.32#ibcon#enter sib2, iclass 38, count 0 2006.189.07:53:12.32#ibcon#flushed, iclass 38, count 0 2006.189.07:53:12.32#ibcon#about to write, iclass 38, count 0 2006.189.07:53:12.32#ibcon#wrote, iclass 38, count 0 2006.189.07:53:12.32#ibcon#about to read 3, iclass 38, count 0 2006.189.07:53:12.36#ibcon#read 3, iclass 38, count 0 2006.189.07:53:12.36#ibcon#about to read 4, iclass 38, count 0 2006.189.07:53:12.36#ibcon#read 4, iclass 38, count 0 2006.189.07:53:12.36#ibcon#about to read 5, iclass 38, count 0 2006.189.07:53:12.36#ibcon#read 5, iclass 38, count 0 2006.189.07:53:12.36#ibcon#about to read 6, iclass 38, count 0 2006.189.07:53:12.36#ibcon#read 6, iclass 38, count 0 2006.189.07:53:12.36#ibcon#end of sib2, iclass 38, count 0 2006.189.07:53:12.36#ibcon#*after write, iclass 38, count 0 2006.189.07:53:12.36#ibcon#*before return 0, iclass 38, count 0 2006.189.07:53:12.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:12.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:53:12.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:53:12.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:53:12.36$vc4f8/vb=6,4 2006.189.07:53:12.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.07:53:12.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.07:53:12.36#ibcon#ireg 11 cls_cnt 2 2006.189.07:53:12.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:12.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:12.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:12.42#ibcon#enter wrdev, iclass 40, count 2 2006.189.07:53:12.42#ibcon#first serial, iclass 40, count 2 2006.189.07:53:12.42#ibcon#enter sib2, iclass 40, count 2 2006.189.07:53:12.42#ibcon#flushed, iclass 40, count 2 2006.189.07:53:12.42#ibcon#about to write, iclass 40, count 2 2006.189.07:53:12.42#ibcon#wrote, iclass 40, count 2 2006.189.07:53:12.42#ibcon#about to read 3, iclass 40, count 2 2006.189.07:53:12.44#ibcon#read 3, iclass 40, count 2 2006.189.07:53:12.44#ibcon#about to read 4, iclass 40, count 2 2006.189.07:53:12.44#ibcon#read 4, iclass 40, count 2 2006.189.07:53:12.44#ibcon#about to read 5, iclass 40, count 2 2006.189.07:53:12.44#ibcon#read 5, iclass 40, count 2 2006.189.07:53:12.44#ibcon#about to read 6, iclass 40, count 2 2006.189.07:53:12.44#ibcon#read 6, iclass 40, count 2 2006.189.07:53:12.44#ibcon#end of sib2, iclass 40, count 2 2006.189.07:53:12.44#ibcon#*mode == 0, iclass 40, count 2 2006.189.07:53:12.44#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.07:53:12.44#ibcon#[27=AT06-04\r\n] 2006.189.07:53:12.44#ibcon#*before write, iclass 40, count 2 2006.189.07:53:12.44#ibcon#enter sib2, iclass 40, count 2 2006.189.07:53:12.44#ibcon#flushed, iclass 40, count 2 2006.189.07:53:12.44#ibcon#about to write, iclass 40, count 2 2006.189.07:53:12.44#ibcon#wrote, iclass 40, count 2 2006.189.07:53:12.44#ibcon#about to read 3, iclass 40, count 2 2006.189.07:53:12.47#ibcon#read 3, iclass 40, count 2 2006.189.07:53:12.47#ibcon#about to read 4, iclass 40, count 2 2006.189.07:53:12.47#ibcon#read 4, iclass 40, count 2 2006.189.07:53:12.47#ibcon#about to read 5, iclass 40, count 2 2006.189.07:53:12.47#ibcon#read 5, iclass 40, count 2 2006.189.07:53:12.47#ibcon#about to read 6, iclass 40, count 2 2006.189.07:53:12.47#ibcon#read 6, iclass 40, count 2 2006.189.07:53:12.47#ibcon#end of sib2, iclass 40, count 2 2006.189.07:53:12.47#ibcon#*after write, iclass 40, count 2 2006.189.07:53:12.47#ibcon#*before return 0, iclass 40, count 2 2006.189.07:53:12.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:12.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:53:12.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.07:53:12.47#ibcon#ireg 7 cls_cnt 0 2006.189.07:53:12.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:12.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:12.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:12.59#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:53:12.59#ibcon#first serial, iclass 40, count 0 2006.189.07:53:12.59#ibcon#enter sib2, iclass 40, count 0 2006.189.07:53:12.59#ibcon#flushed, iclass 40, count 0 2006.189.07:53:12.59#ibcon#about to write, iclass 40, count 0 2006.189.07:53:12.59#ibcon#wrote, iclass 40, count 0 2006.189.07:53:12.59#ibcon#about to read 3, iclass 40, count 0 2006.189.07:53:12.61#ibcon#read 3, iclass 40, count 0 2006.189.07:53:12.61#ibcon#about to read 4, iclass 40, count 0 2006.189.07:53:12.61#ibcon#read 4, iclass 40, count 0 2006.189.07:53:12.61#ibcon#about to read 5, iclass 40, count 0 2006.189.07:53:12.61#ibcon#read 5, iclass 40, count 0 2006.189.07:53:12.61#ibcon#about to read 6, iclass 40, count 0 2006.189.07:53:12.61#ibcon#read 6, iclass 40, count 0 2006.189.07:53:12.61#ibcon#end of sib2, iclass 40, count 0 2006.189.07:53:12.61#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:53:12.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:53:12.61#ibcon#[27=USB\r\n] 2006.189.07:53:12.61#ibcon#*before write, iclass 40, count 0 2006.189.07:53:12.61#ibcon#enter sib2, iclass 40, count 0 2006.189.07:53:12.61#ibcon#flushed, iclass 40, count 0 2006.189.07:53:12.61#ibcon#about to write, iclass 40, count 0 2006.189.07:53:12.61#ibcon#wrote, iclass 40, count 0 2006.189.07:53:12.61#ibcon#about to read 3, iclass 40, count 0 2006.189.07:53:12.64#ibcon#read 3, iclass 40, count 0 2006.189.07:53:12.64#ibcon#about to read 4, iclass 40, count 0 2006.189.07:53:12.64#ibcon#read 4, iclass 40, count 0 2006.189.07:53:12.64#ibcon#about to read 5, iclass 40, count 0 2006.189.07:53:12.64#ibcon#read 5, iclass 40, count 0 2006.189.07:53:12.64#ibcon#about to read 6, iclass 40, count 0 2006.189.07:53:12.64#ibcon#read 6, iclass 40, count 0 2006.189.07:53:12.64#ibcon#end of sib2, iclass 40, count 0 2006.189.07:53:12.64#ibcon#*after write, iclass 40, count 0 2006.189.07:53:12.64#ibcon#*before return 0, iclass 40, count 0 2006.189.07:53:12.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:12.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:53:12.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:53:12.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:53:12.64$vc4f8/vabw=wide 2006.189.07:53:12.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:53:12.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:53:12.64#ibcon#ireg 8 cls_cnt 0 2006.189.07:53:12.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:12.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:12.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:12.64#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:53:12.64#ibcon#first serial, iclass 4, count 0 2006.189.07:53:12.64#ibcon#enter sib2, iclass 4, count 0 2006.189.07:53:12.64#ibcon#flushed, iclass 4, count 0 2006.189.07:53:12.64#ibcon#about to write, iclass 4, count 0 2006.189.07:53:12.64#ibcon#wrote, iclass 4, count 0 2006.189.07:53:12.64#ibcon#about to read 3, iclass 4, count 0 2006.189.07:53:12.66#ibcon#read 3, iclass 4, count 0 2006.189.07:53:12.66#ibcon#about to read 4, iclass 4, count 0 2006.189.07:53:12.66#ibcon#read 4, iclass 4, count 0 2006.189.07:53:12.66#ibcon#about to read 5, iclass 4, count 0 2006.189.07:53:12.66#ibcon#read 5, iclass 4, count 0 2006.189.07:53:12.66#ibcon#about to read 6, iclass 4, count 0 2006.189.07:53:12.66#ibcon#read 6, iclass 4, count 0 2006.189.07:53:12.66#ibcon#end of sib2, iclass 4, count 0 2006.189.07:53:12.66#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:53:12.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:53:12.66#ibcon#[25=BW32\r\n] 2006.189.07:53:12.66#ibcon#*before write, iclass 4, count 0 2006.189.07:53:12.66#ibcon#enter sib2, iclass 4, count 0 2006.189.07:53:12.66#ibcon#flushed, iclass 4, count 0 2006.189.07:53:12.66#ibcon#about to write, iclass 4, count 0 2006.189.07:53:12.66#ibcon#wrote, iclass 4, count 0 2006.189.07:53:12.66#ibcon#about to read 3, iclass 4, count 0 2006.189.07:53:12.69#ibcon#read 3, iclass 4, count 0 2006.189.07:53:12.69#ibcon#about to read 4, iclass 4, count 0 2006.189.07:53:12.69#ibcon#read 4, iclass 4, count 0 2006.189.07:53:12.69#ibcon#about to read 5, iclass 4, count 0 2006.189.07:53:12.69#ibcon#read 5, iclass 4, count 0 2006.189.07:53:12.69#ibcon#about to read 6, iclass 4, count 0 2006.189.07:53:12.69#ibcon#read 6, iclass 4, count 0 2006.189.07:53:12.69#ibcon#end of sib2, iclass 4, count 0 2006.189.07:53:12.69#ibcon#*after write, iclass 4, count 0 2006.189.07:53:12.69#ibcon#*before return 0, iclass 4, count 0 2006.189.07:53:12.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:12.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:53:12.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:53:12.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:53:12.69$vc4f8/vbbw=wide 2006.189.07:53:12.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.07:53:12.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.07:53:12.69#ibcon#ireg 8 cls_cnt 0 2006.189.07:53:12.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:53:12.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:53:12.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:53:12.76#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:53:12.76#ibcon#first serial, iclass 6, count 0 2006.189.07:53:12.76#ibcon#enter sib2, iclass 6, count 0 2006.189.07:53:12.76#ibcon#flushed, iclass 6, count 0 2006.189.07:53:12.76#ibcon#about to write, iclass 6, count 0 2006.189.07:53:12.76#ibcon#wrote, iclass 6, count 0 2006.189.07:53:12.76#ibcon#about to read 3, iclass 6, count 0 2006.189.07:53:12.78#ibcon#read 3, iclass 6, count 0 2006.189.07:53:12.78#ibcon#about to read 4, iclass 6, count 0 2006.189.07:53:12.78#ibcon#read 4, iclass 6, count 0 2006.189.07:53:12.78#ibcon#about to read 5, iclass 6, count 0 2006.189.07:53:12.78#ibcon#read 5, iclass 6, count 0 2006.189.07:53:12.78#ibcon#about to read 6, iclass 6, count 0 2006.189.07:53:12.78#ibcon#read 6, iclass 6, count 0 2006.189.07:53:12.78#ibcon#end of sib2, iclass 6, count 0 2006.189.07:53:12.78#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:53:12.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:53:12.78#ibcon#[27=BW32\r\n] 2006.189.07:53:12.78#ibcon#*before write, iclass 6, count 0 2006.189.07:53:12.78#ibcon#enter sib2, iclass 6, count 0 2006.189.07:53:12.78#ibcon#flushed, iclass 6, count 0 2006.189.07:53:12.78#ibcon#about to write, iclass 6, count 0 2006.189.07:53:12.78#ibcon#wrote, iclass 6, count 0 2006.189.07:53:12.78#ibcon#about to read 3, iclass 6, count 0 2006.189.07:53:12.81#ibcon#read 3, iclass 6, count 0 2006.189.07:53:12.81#ibcon#about to read 4, iclass 6, count 0 2006.189.07:53:12.81#ibcon#read 4, iclass 6, count 0 2006.189.07:53:12.81#ibcon#about to read 5, iclass 6, count 0 2006.189.07:53:12.81#ibcon#read 5, iclass 6, count 0 2006.189.07:53:12.81#ibcon#about to read 6, iclass 6, count 0 2006.189.07:53:12.81#ibcon#read 6, iclass 6, count 0 2006.189.07:53:12.81#ibcon#end of sib2, iclass 6, count 0 2006.189.07:53:12.81#ibcon#*after write, iclass 6, count 0 2006.189.07:53:12.81#ibcon#*before return 0, iclass 6, count 0 2006.189.07:53:12.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:53:12.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.07:53:12.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:53:12.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:53:12.81$4f8m12a/ifd4f 2006.189.07:53:12.81$ifd4f/lo= 2006.189.07:53:12.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:53:12.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:53:12.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:53:12.81$ifd4f/patch= 2006.189.07:53:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:53:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:53:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:53:12.81$4f8m12a/"form=m,16.000,1:2 2006.189.07:53:12.81$4f8m12a/"tpicd 2006.189.07:53:12.81$4f8m12a/echo=off 2006.189.07:53:12.81$4f8m12a/xlog=off 2006.189.07:53:12.81:!2006.189.07:54:50 2006.189.07:53:30.13#trakl#Source acquired 2006.189.07:53:31.13#flagr#flagr/antenna,acquired 2006.189.07:54:34.14#trakl#Off source 2006.189.07:54:34.14?ERROR st -7 Antenna off-source! 2006.189.07:54:34.14#trakl#az 39.101 el 62.356 azerr*cos(el) 0.0003 elerr 0.0214 2006.189.07:54:34.14#flagr#flagr/antenna,off-source 2006.189.07:54:40.14#trakl#Source re-acquired 2006.189.07:54:40.14#flagr#flagr/antenna,re-acquired 2006.189.07:54:50.00:preob 2006.189.07:54:50.14/onsource/TRACKING 2006.189.07:54:50.14:!2006.189.07:55:00 2006.189.07:55:00.00:data_valid=on 2006.189.07:55:00.00:midob 2006.189.07:55:01.14/onsource/TRACKING 2006.189.07:55:01.14/wx/25.83,1009.1,90 2006.189.07:55:01.33/cable/+6.4538E-03 2006.189.07:55:02.42/va/01,08,usb,yes,28,29 2006.189.07:55:02.42/va/02,07,usb,yes,28,29 2006.189.07:55:02.42/va/03,06,usb,yes,29,29 2006.189.07:55:02.42/va/04,07,usb,yes,29,31 2006.189.07:55:02.42/va/05,07,usb,yes,31,32 2006.189.07:55:02.42/va/06,06,usb,yes,30,29 2006.189.07:55:02.42/va/07,06,usb,yes,30,30 2006.189.07:55:02.42/va/08,06,usb,yes,32,32 2006.189.07:55:02.65/valo/01,532.99,yes,locked 2006.189.07:55:02.65/valo/02,572.99,yes,locked 2006.189.07:55:02.65/valo/03,672.99,yes,locked 2006.189.07:55:02.65/valo/04,832.99,yes,locked 2006.189.07:55:02.65/valo/05,652.99,yes,locked 2006.189.07:55:02.65/valo/06,772.99,yes,locked 2006.189.07:55:02.65/valo/07,832.99,yes,locked 2006.189.07:55:02.65/valo/08,852.99,yes,locked 2006.189.07:55:03.74/vb/01,04,usb,yes,28,27 2006.189.07:55:03.74/vb/02,04,usb,yes,30,31 2006.189.07:55:03.74/vb/03,04,usb,yes,26,30 2006.189.07:55:03.74/vb/04,04,usb,yes,27,27 2006.189.07:55:03.74/vb/05,04,usb,yes,26,30 2006.189.07:55:03.74/vb/06,04,usb,yes,27,29 2006.189.07:55:03.74/vb/07,04,usb,yes,29,29 2006.189.07:55:03.74/vb/08,04,usb,yes,26,30 2006.189.07:55:03.97/vblo/01,632.99,yes,locked 2006.189.07:55:03.97/vblo/02,640.99,yes,locked 2006.189.07:55:03.97/vblo/03,656.99,yes,locked 2006.189.07:55:03.97/vblo/04,712.99,yes,locked 2006.189.07:55:03.97/vblo/05,744.99,yes,locked 2006.189.07:55:03.97/vblo/06,752.99,yes,locked 2006.189.07:55:03.97/vblo/07,734.99,yes,locked 2006.189.07:55:03.97/vblo/08,744.99,yes,locked 2006.189.07:55:04.12/vabw/8 2006.189.07:55:04.27/vbbw/8 2006.189.07:55:04.36/xfe/off,on,14.7 2006.189.07:55:04.73/ifatt/23,28,28,28 2006.189.07:55:05.08/fmout-gps/S +2.96E-07 2006.189.07:55:05.16:!2006.189.07:56:00 2006.189.07:56:00.01:data_valid=off 2006.189.07:56:00.01:postob 2006.189.07:56:00.21/cable/+6.4518E-03 2006.189.07:56:00.21/wx/25.80,1009.1,90 2006.189.07:56:01.08/fmout-gps/S +2.97E-07 2006.189.07:56:01.08:scan_name=189-0758,k06189,60 2006.189.07:56:01.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.189.07:56:01.14#flagr#flagr/antenna,new-source 2006.189.07:56:02.14:checkk5 2006.189.07:56:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:56:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:56:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:56:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:56:04.04/chk_obsdata//k5ts1/T1890755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:56:04.41/chk_obsdata//k5ts2/T1890755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:56:04.78/chk_obsdata//k5ts3/T1890755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:56:05.16/chk_obsdata//k5ts4/T1890755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:56:05.86/k5log//k5ts1_log_newline 2006.189.07:56:06.56/k5log//k5ts2_log_newline 2006.189.07:56:07.26/k5log//k5ts3_log_newline 2006.189.07:56:07.95/k5log//k5ts4_log_newline 2006.189.07:56:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:56:07.97:4f8m12a=2 2006.189.07:56:07.97$4f8m12a/echo=on 2006.189.07:56:07.97$4f8m12a/pcalon 2006.189.07:56:07.97$pcalon/"no phase cal control is implemented here 2006.189.07:56:07.97$4f8m12a/"tpicd=stop 2006.189.07:56:07.97$4f8m12a/vc4f8 2006.189.07:56:07.97$vc4f8/valo=1,532.99 2006.189.07:56:07.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:56:07.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:56:07.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:07.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:07.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:07.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:07.97#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:56:07.97#ibcon#first serial, iclass 7, count 0 2006.189.07:56:07.97#ibcon#enter sib2, iclass 7, count 0 2006.189.07:56:07.97#ibcon#flushed, iclass 7, count 0 2006.189.07:56:07.97#ibcon#about to write, iclass 7, count 0 2006.189.07:56:07.97#ibcon#wrote, iclass 7, count 0 2006.189.07:56:07.97#ibcon#about to read 3, iclass 7, count 0 2006.189.07:56:07.99#ibcon#read 3, iclass 7, count 0 2006.189.07:56:07.99#ibcon#about to read 4, iclass 7, count 0 2006.189.07:56:07.99#ibcon#read 4, iclass 7, count 0 2006.189.07:56:07.99#ibcon#about to read 5, iclass 7, count 0 2006.189.07:56:07.99#ibcon#read 5, iclass 7, count 0 2006.189.07:56:07.99#ibcon#about to read 6, iclass 7, count 0 2006.189.07:56:07.99#ibcon#read 6, iclass 7, count 0 2006.189.07:56:07.99#ibcon#end of sib2, iclass 7, count 0 2006.189.07:56:07.99#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:56:07.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:56:07.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:56:07.99#ibcon#*before write, iclass 7, count 0 2006.189.07:56:07.99#ibcon#enter sib2, iclass 7, count 0 2006.189.07:56:07.99#ibcon#flushed, iclass 7, count 0 2006.189.07:56:07.99#ibcon#about to write, iclass 7, count 0 2006.189.07:56:07.99#ibcon#wrote, iclass 7, count 0 2006.189.07:56:07.99#ibcon#about to read 3, iclass 7, count 0 2006.189.07:56:08.04#ibcon#read 3, iclass 7, count 0 2006.189.07:56:08.04#ibcon#about to read 4, iclass 7, count 0 2006.189.07:56:08.04#ibcon#read 4, iclass 7, count 0 2006.189.07:56:08.04#ibcon#about to read 5, iclass 7, count 0 2006.189.07:56:08.04#ibcon#read 5, iclass 7, count 0 2006.189.07:56:08.04#ibcon#about to read 6, iclass 7, count 0 2006.189.07:56:08.04#ibcon#read 6, iclass 7, count 0 2006.189.07:56:08.04#ibcon#end of sib2, iclass 7, count 0 2006.189.07:56:08.04#ibcon#*after write, iclass 7, count 0 2006.189.07:56:08.04#ibcon#*before return 0, iclass 7, count 0 2006.189.07:56:08.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:08.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:08.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:56:08.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:56:08.04$vc4f8/va=1,8 2006.189.07:56:08.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:56:08.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:56:08.04#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:08.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:08.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:08.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:08.04#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:56:08.04#ibcon#first serial, iclass 11, count 2 2006.189.07:56:08.04#ibcon#enter sib2, iclass 11, count 2 2006.189.07:56:08.04#ibcon#flushed, iclass 11, count 2 2006.189.07:56:08.04#ibcon#about to write, iclass 11, count 2 2006.189.07:56:08.04#ibcon#wrote, iclass 11, count 2 2006.189.07:56:08.04#ibcon#about to read 3, iclass 11, count 2 2006.189.07:56:08.06#ibcon#read 3, iclass 11, count 2 2006.189.07:56:08.06#ibcon#about to read 4, iclass 11, count 2 2006.189.07:56:08.06#ibcon#read 4, iclass 11, count 2 2006.189.07:56:08.06#ibcon#about to read 5, iclass 11, count 2 2006.189.07:56:08.06#ibcon#read 5, iclass 11, count 2 2006.189.07:56:08.06#ibcon#about to read 6, iclass 11, count 2 2006.189.07:56:08.06#ibcon#read 6, iclass 11, count 2 2006.189.07:56:08.06#ibcon#end of sib2, iclass 11, count 2 2006.189.07:56:08.06#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:56:08.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:56:08.06#ibcon#[25=AT01-08\r\n] 2006.189.07:56:08.06#ibcon#*before write, iclass 11, count 2 2006.189.07:56:08.06#ibcon#enter sib2, iclass 11, count 2 2006.189.07:56:08.06#ibcon#flushed, iclass 11, count 2 2006.189.07:56:08.06#ibcon#about to write, iclass 11, count 2 2006.189.07:56:08.06#ibcon#wrote, iclass 11, count 2 2006.189.07:56:08.06#ibcon#about to read 3, iclass 11, count 2 2006.189.07:56:08.09#ibcon#read 3, iclass 11, count 2 2006.189.07:56:08.09#ibcon#about to read 4, iclass 11, count 2 2006.189.07:56:08.09#ibcon#read 4, iclass 11, count 2 2006.189.07:56:08.09#ibcon#about to read 5, iclass 11, count 2 2006.189.07:56:08.09#ibcon#read 5, iclass 11, count 2 2006.189.07:56:08.09#ibcon#about to read 6, iclass 11, count 2 2006.189.07:56:08.09#ibcon#read 6, iclass 11, count 2 2006.189.07:56:08.09#ibcon#end of sib2, iclass 11, count 2 2006.189.07:56:08.09#ibcon#*after write, iclass 11, count 2 2006.189.07:56:08.09#ibcon#*before return 0, iclass 11, count 2 2006.189.07:56:08.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:08.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:08.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:56:08.09#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:08.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:08.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:08.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:08.21#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:56:08.21#ibcon#first serial, iclass 11, count 0 2006.189.07:56:08.21#ibcon#enter sib2, iclass 11, count 0 2006.189.07:56:08.21#ibcon#flushed, iclass 11, count 0 2006.189.07:56:08.21#ibcon#about to write, iclass 11, count 0 2006.189.07:56:08.21#ibcon#wrote, iclass 11, count 0 2006.189.07:56:08.21#ibcon#about to read 3, iclass 11, count 0 2006.189.07:56:08.23#ibcon#read 3, iclass 11, count 0 2006.189.07:56:08.23#ibcon#about to read 4, iclass 11, count 0 2006.189.07:56:08.23#ibcon#read 4, iclass 11, count 0 2006.189.07:56:08.23#ibcon#about to read 5, iclass 11, count 0 2006.189.07:56:08.23#ibcon#read 5, iclass 11, count 0 2006.189.07:56:08.23#ibcon#about to read 6, iclass 11, count 0 2006.189.07:56:08.23#ibcon#read 6, iclass 11, count 0 2006.189.07:56:08.23#ibcon#end of sib2, iclass 11, count 0 2006.189.07:56:08.23#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:56:08.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:56:08.23#ibcon#[25=USB\r\n] 2006.189.07:56:08.23#ibcon#*before write, iclass 11, count 0 2006.189.07:56:08.23#ibcon#enter sib2, iclass 11, count 0 2006.189.07:56:08.23#ibcon#flushed, iclass 11, count 0 2006.189.07:56:08.23#ibcon#about to write, iclass 11, count 0 2006.189.07:56:08.24#ibcon#wrote, iclass 11, count 0 2006.189.07:56:08.24#ibcon#about to read 3, iclass 11, count 0 2006.189.07:56:08.26#ibcon#read 3, iclass 11, count 0 2006.189.07:56:08.26#ibcon#about to read 4, iclass 11, count 0 2006.189.07:56:08.26#ibcon#read 4, iclass 11, count 0 2006.189.07:56:08.26#ibcon#about to read 5, iclass 11, count 0 2006.189.07:56:08.26#ibcon#read 5, iclass 11, count 0 2006.189.07:56:08.26#ibcon#about to read 6, iclass 11, count 0 2006.189.07:56:08.26#ibcon#read 6, iclass 11, count 0 2006.189.07:56:08.26#ibcon#end of sib2, iclass 11, count 0 2006.189.07:56:08.26#ibcon#*after write, iclass 11, count 0 2006.189.07:56:08.26#ibcon#*before return 0, iclass 11, count 0 2006.189.07:56:08.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:08.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:08.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:56:08.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:56:08.26$vc4f8/valo=2,572.99 2006.189.07:56:08.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.07:56:08.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.07:56:08.26#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:08.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:08.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:08.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:08.26#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:56:08.26#ibcon#first serial, iclass 13, count 0 2006.189.07:56:08.26#ibcon#enter sib2, iclass 13, count 0 2006.189.07:56:08.26#ibcon#flushed, iclass 13, count 0 2006.189.07:56:08.26#ibcon#about to write, iclass 13, count 0 2006.189.07:56:08.26#ibcon#wrote, iclass 13, count 0 2006.189.07:56:08.26#ibcon#about to read 3, iclass 13, count 0 2006.189.07:56:08.28#ibcon#read 3, iclass 13, count 0 2006.189.07:56:08.28#ibcon#about to read 4, iclass 13, count 0 2006.189.07:56:08.28#ibcon#read 4, iclass 13, count 0 2006.189.07:56:08.28#ibcon#about to read 5, iclass 13, count 0 2006.189.07:56:08.28#ibcon#read 5, iclass 13, count 0 2006.189.07:56:08.28#ibcon#about to read 6, iclass 13, count 0 2006.189.07:56:08.28#ibcon#read 6, iclass 13, count 0 2006.189.07:56:08.28#ibcon#end of sib2, iclass 13, count 0 2006.189.07:56:08.28#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:56:08.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:56:08.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:56:08.28#ibcon#*before write, iclass 13, count 0 2006.189.07:56:08.28#ibcon#enter sib2, iclass 13, count 0 2006.189.07:56:08.28#ibcon#flushed, iclass 13, count 0 2006.189.07:56:08.28#ibcon#about to write, iclass 13, count 0 2006.189.07:56:08.28#ibcon#wrote, iclass 13, count 0 2006.189.07:56:08.28#ibcon#about to read 3, iclass 13, count 0 2006.189.07:56:08.33#ibcon#read 3, iclass 13, count 0 2006.189.07:56:08.33#ibcon#about to read 4, iclass 13, count 0 2006.189.07:56:08.33#ibcon#read 4, iclass 13, count 0 2006.189.07:56:08.33#ibcon#about to read 5, iclass 13, count 0 2006.189.07:56:08.33#ibcon#read 5, iclass 13, count 0 2006.189.07:56:08.33#ibcon#about to read 6, iclass 13, count 0 2006.189.07:56:08.33#ibcon#read 6, iclass 13, count 0 2006.189.07:56:08.33#ibcon#end of sib2, iclass 13, count 0 2006.189.07:56:08.33#ibcon#*after write, iclass 13, count 0 2006.189.07:56:08.33#ibcon#*before return 0, iclass 13, count 0 2006.189.07:56:08.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:08.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:08.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:56:08.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:56:08.33$vc4f8/va=2,7 2006.189.07:56:08.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.07:56:08.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.07:56:08.33#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:08.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:08.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:08.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:08.37#ibcon#enter wrdev, iclass 15, count 2 2006.189.07:56:08.37#ibcon#first serial, iclass 15, count 2 2006.189.07:56:08.37#ibcon#enter sib2, iclass 15, count 2 2006.189.07:56:08.37#ibcon#flushed, iclass 15, count 2 2006.189.07:56:08.37#ibcon#about to write, iclass 15, count 2 2006.189.07:56:08.37#ibcon#wrote, iclass 15, count 2 2006.189.07:56:08.37#ibcon#about to read 3, iclass 15, count 2 2006.189.07:56:08.39#ibcon#read 3, iclass 15, count 2 2006.189.07:56:08.39#ibcon#about to read 4, iclass 15, count 2 2006.189.07:56:08.39#ibcon#read 4, iclass 15, count 2 2006.189.07:56:08.39#ibcon#about to read 5, iclass 15, count 2 2006.189.07:56:08.39#ibcon#read 5, iclass 15, count 2 2006.189.07:56:08.39#ibcon#about to read 6, iclass 15, count 2 2006.189.07:56:08.39#ibcon#read 6, iclass 15, count 2 2006.189.07:56:08.39#ibcon#end of sib2, iclass 15, count 2 2006.189.07:56:08.39#ibcon#*mode == 0, iclass 15, count 2 2006.189.07:56:08.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.07:56:08.39#ibcon#[25=AT02-07\r\n] 2006.189.07:56:08.39#ibcon#*before write, iclass 15, count 2 2006.189.07:56:08.39#ibcon#enter sib2, iclass 15, count 2 2006.189.07:56:08.39#ibcon#flushed, iclass 15, count 2 2006.189.07:56:08.39#ibcon#about to write, iclass 15, count 2 2006.189.07:56:08.39#ibcon#wrote, iclass 15, count 2 2006.189.07:56:08.39#ibcon#about to read 3, iclass 15, count 2 2006.189.07:56:08.42#ibcon#read 3, iclass 15, count 2 2006.189.07:56:08.42#ibcon#about to read 4, iclass 15, count 2 2006.189.07:56:08.42#ibcon#read 4, iclass 15, count 2 2006.189.07:56:08.42#ibcon#about to read 5, iclass 15, count 2 2006.189.07:56:08.42#ibcon#read 5, iclass 15, count 2 2006.189.07:56:08.42#ibcon#about to read 6, iclass 15, count 2 2006.189.07:56:08.42#ibcon#read 6, iclass 15, count 2 2006.189.07:56:08.42#ibcon#end of sib2, iclass 15, count 2 2006.189.07:56:08.42#ibcon#*after write, iclass 15, count 2 2006.189.07:56:08.42#ibcon#*before return 0, iclass 15, count 2 2006.189.07:56:08.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:08.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:08.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.07:56:08.42#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:08.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:08.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:08.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:08.54#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:56:08.54#ibcon#first serial, iclass 15, count 0 2006.189.07:56:08.54#ibcon#enter sib2, iclass 15, count 0 2006.189.07:56:08.54#ibcon#flushed, iclass 15, count 0 2006.189.07:56:08.54#ibcon#about to write, iclass 15, count 0 2006.189.07:56:08.54#ibcon#wrote, iclass 15, count 0 2006.189.07:56:08.54#ibcon#about to read 3, iclass 15, count 0 2006.189.07:56:08.56#ibcon#read 3, iclass 15, count 0 2006.189.07:56:08.56#ibcon#about to read 4, iclass 15, count 0 2006.189.07:56:08.56#ibcon#read 4, iclass 15, count 0 2006.189.07:56:08.56#ibcon#about to read 5, iclass 15, count 0 2006.189.07:56:08.56#ibcon#read 5, iclass 15, count 0 2006.189.07:56:08.56#ibcon#about to read 6, iclass 15, count 0 2006.189.07:56:08.56#ibcon#read 6, iclass 15, count 0 2006.189.07:56:08.56#ibcon#end of sib2, iclass 15, count 0 2006.189.07:56:08.56#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:56:08.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:56:08.56#ibcon#[25=USB\r\n] 2006.189.07:56:08.56#ibcon#*before write, iclass 15, count 0 2006.189.07:56:08.56#ibcon#enter sib2, iclass 15, count 0 2006.189.07:56:08.56#ibcon#flushed, iclass 15, count 0 2006.189.07:56:08.56#ibcon#about to write, iclass 15, count 0 2006.189.07:56:08.56#ibcon#wrote, iclass 15, count 0 2006.189.07:56:08.56#ibcon#about to read 3, iclass 15, count 0 2006.189.07:56:08.59#ibcon#read 3, iclass 15, count 0 2006.189.07:56:08.59#ibcon#about to read 4, iclass 15, count 0 2006.189.07:56:08.59#ibcon#read 4, iclass 15, count 0 2006.189.07:56:08.59#ibcon#about to read 5, iclass 15, count 0 2006.189.07:56:08.59#ibcon#read 5, iclass 15, count 0 2006.189.07:56:08.59#ibcon#about to read 6, iclass 15, count 0 2006.189.07:56:08.59#ibcon#read 6, iclass 15, count 0 2006.189.07:56:08.59#ibcon#end of sib2, iclass 15, count 0 2006.189.07:56:08.59#ibcon#*after write, iclass 15, count 0 2006.189.07:56:08.59#ibcon#*before return 0, iclass 15, count 0 2006.189.07:56:08.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:08.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:08.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:56:08.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:56:08.59$vc4f8/valo=3,672.99 2006.189.07:56:08.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:56:08.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:56:08.59#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:08.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:08.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:08.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:08.59#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:56:08.59#ibcon#first serial, iclass 17, count 0 2006.189.07:56:08.59#ibcon#enter sib2, iclass 17, count 0 2006.189.07:56:08.59#ibcon#flushed, iclass 17, count 0 2006.189.07:56:08.59#ibcon#about to write, iclass 17, count 0 2006.189.07:56:08.59#ibcon#wrote, iclass 17, count 0 2006.189.07:56:08.59#ibcon#about to read 3, iclass 17, count 0 2006.189.07:56:08.61#ibcon#read 3, iclass 17, count 0 2006.189.07:56:08.61#ibcon#about to read 4, iclass 17, count 0 2006.189.07:56:08.61#ibcon#read 4, iclass 17, count 0 2006.189.07:56:08.61#ibcon#about to read 5, iclass 17, count 0 2006.189.07:56:08.61#ibcon#read 5, iclass 17, count 0 2006.189.07:56:08.61#ibcon#about to read 6, iclass 17, count 0 2006.189.07:56:08.61#ibcon#read 6, iclass 17, count 0 2006.189.07:56:08.61#ibcon#end of sib2, iclass 17, count 0 2006.189.07:56:08.61#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:56:08.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:56:08.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:56:08.61#ibcon#*before write, iclass 17, count 0 2006.189.07:56:08.61#ibcon#enter sib2, iclass 17, count 0 2006.189.07:56:08.61#ibcon#flushed, iclass 17, count 0 2006.189.07:56:08.61#ibcon#about to write, iclass 17, count 0 2006.189.07:56:08.61#ibcon#wrote, iclass 17, count 0 2006.189.07:56:08.61#ibcon#about to read 3, iclass 17, count 0 2006.189.07:56:08.65#ibcon#read 3, iclass 17, count 0 2006.189.07:56:08.65#ibcon#about to read 4, iclass 17, count 0 2006.189.07:56:08.65#ibcon#read 4, iclass 17, count 0 2006.189.07:56:08.65#ibcon#about to read 5, iclass 17, count 0 2006.189.07:56:08.65#ibcon#read 5, iclass 17, count 0 2006.189.07:56:08.65#ibcon#about to read 6, iclass 17, count 0 2006.189.07:56:08.65#ibcon#read 6, iclass 17, count 0 2006.189.07:56:08.65#ibcon#end of sib2, iclass 17, count 0 2006.189.07:56:08.65#ibcon#*after write, iclass 17, count 0 2006.189.07:56:08.65#ibcon#*before return 0, iclass 17, count 0 2006.189.07:56:08.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:08.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:08.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:56:08.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:56:08.65$vc4f8/va=3,6 2006.189.07:56:08.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.07:56:08.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.07:56:08.65#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:08.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:08.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:08.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:08.71#ibcon#enter wrdev, iclass 19, count 2 2006.189.07:56:08.71#ibcon#first serial, iclass 19, count 2 2006.189.07:56:08.71#ibcon#enter sib2, iclass 19, count 2 2006.189.07:56:08.71#ibcon#flushed, iclass 19, count 2 2006.189.07:56:08.71#ibcon#about to write, iclass 19, count 2 2006.189.07:56:08.71#ibcon#wrote, iclass 19, count 2 2006.189.07:56:08.71#ibcon#about to read 3, iclass 19, count 2 2006.189.07:56:08.73#ibcon#read 3, iclass 19, count 2 2006.189.07:56:08.73#ibcon#about to read 4, iclass 19, count 2 2006.189.07:56:08.73#ibcon#read 4, iclass 19, count 2 2006.189.07:56:08.73#ibcon#about to read 5, iclass 19, count 2 2006.189.07:56:08.73#ibcon#read 5, iclass 19, count 2 2006.189.07:56:08.73#ibcon#about to read 6, iclass 19, count 2 2006.189.07:56:08.73#ibcon#read 6, iclass 19, count 2 2006.189.07:56:08.73#ibcon#end of sib2, iclass 19, count 2 2006.189.07:56:08.73#ibcon#*mode == 0, iclass 19, count 2 2006.189.07:56:08.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.07:56:08.73#ibcon#[25=AT03-06\r\n] 2006.189.07:56:08.73#ibcon#*before write, iclass 19, count 2 2006.189.07:56:08.73#ibcon#enter sib2, iclass 19, count 2 2006.189.07:56:08.73#ibcon#flushed, iclass 19, count 2 2006.189.07:56:08.73#ibcon#about to write, iclass 19, count 2 2006.189.07:56:08.73#ibcon#wrote, iclass 19, count 2 2006.189.07:56:08.73#ibcon#about to read 3, iclass 19, count 2 2006.189.07:56:08.76#ibcon#read 3, iclass 19, count 2 2006.189.07:56:08.76#ibcon#about to read 4, iclass 19, count 2 2006.189.07:56:08.76#ibcon#read 4, iclass 19, count 2 2006.189.07:56:08.76#ibcon#about to read 5, iclass 19, count 2 2006.189.07:56:08.76#ibcon#read 5, iclass 19, count 2 2006.189.07:56:08.76#ibcon#about to read 6, iclass 19, count 2 2006.189.07:56:08.76#ibcon#read 6, iclass 19, count 2 2006.189.07:56:08.76#ibcon#end of sib2, iclass 19, count 2 2006.189.07:56:08.76#ibcon#*after write, iclass 19, count 2 2006.189.07:56:08.76#ibcon#*before return 0, iclass 19, count 2 2006.189.07:56:08.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:08.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:08.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.07:56:08.76#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:08.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:08.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:08.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:08.88#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:56:08.88#ibcon#first serial, iclass 19, count 0 2006.189.07:56:08.88#ibcon#enter sib2, iclass 19, count 0 2006.189.07:56:08.88#ibcon#flushed, iclass 19, count 0 2006.189.07:56:08.88#ibcon#about to write, iclass 19, count 0 2006.189.07:56:08.88#ibcon#wrote, iclass 19, count 0 2006.189.07:56:08.88#ibcon#about to read 3, iclass 19, count 0 2006.189.07:56:08.90#ibcon#read 3, iclass 19, count 0 2006.189.07:56:08.90#ibcon#about to read 4, iclass 19, count 0 2006.189.07:56:08.90#ibcon#read 4, iclass 19, count 0 2006.189.07:56:08.90#ibcon#about to read 5, iclass 19, count 0 2006.189.07:56:08.90#ibcon#read 5, iclass 19, count 0 2006.189.07:56:08.90#ibcon#about to read 6, iclass 19, count 0 2006.189.07:56:08.90#ibcon#read 6, iclass 19, count 0 2006.189.07:56:08.90#ibcon#end of sib2, iclass 19, count 0 2006.189.07:56:08.90#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:56:08.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:56:08.90#ibcon#[25=USB\r\n] 2006.189.07:56:08.90#ibcon#*before write, iclass 19, count 0 2006.189.07:56:08.90#ibcon#enter sib2, iclass 19, count 0 2006.189.07:56:08.90#ibcon#flushed, iclass 19, count 0 2006.189.07:56:08.90#ibcon#about to write, iclass 19, count 0 2006.189.07:56:08.90#ibcon#wrote, iclass 19, count 0 2006.189.07:56:08.90#ibcon#about to read 3, iclass 19, count 0 2006.189.07:56:08.93#ibcon#read 3, iclass 19, count 0 2006.189.07:56:08.93#ibcon#about to read 4, iclass 19, count 0 2006.189.07:56:08.93#ibcon#read 4, iclass 19, count 0 2006.189.07:56:08.93#ibcon#about to read 5, iclass 19, count 0 2006.189.07:56:08.93#ibcon#read 5, iclass 19, count 0 2006.189.07:56:08.93#ibcon#about to read 6, iclass 19, count 0 2006.189.07:56:08.93#ibcon#read 6, iclass 19, count 0 2006.189.07:56:08.93#ibcon#end of sib2, iclass 19, count 0 2006.189.07:56:08.93#ibcon#*after write, iclass 19, count 0 2006.189.07:56:08.93#ibcon#*before return 0, iclass 19, count 0 2006.189.07:56:08.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:08.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:08.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:56:08.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:56:08.93$vc4f8/valo=4,832.99 2006.189.07:56:08.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:56:08.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:56:08.93#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:08.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:08.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:08.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:08.93#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:56:08.93#ibcon#first serial, iclass 21, count 0 2006.189.07:56:08.93#ibcon#enter sib2, iclass 21, count 0 2006.189.07:56:08.93#ibcon#flushed, iclass 21, count 0 2006.189.07:56:08.93#ibcon#about to write, iclass 21, count 0 2006.189.07:56:08.93#ibcon#wrote, iclass 21, count 0 2006.189.07:56:08.93#ibcon#about to read 3, iclass 21, count 0 2006.189.07:56:08.95#ibcon#read 3, iclass 21, count 0 2006.189.07:56:08.95#ibcon#about to read 4, iclass 21, count 0 2006.189.07:56:08.95#ibcon#read 4, iclass 21, count 0 2006.189.07:56:08.95#ibcon#about to read 5, iclass 21, count 0 2006.189.07:56:08.95#ibcon#read 5, iclass 21, count 0 2006.189.07:56:08.95#ibcon#about to read 6, iclass 21, count 0 2006.189.07:56:08.95#ibcon#read 6, iclass 21, count 0 2006.189.07:56:08.95#ibcon#end of sib2, iclass 21, count 0 2006.189.07:56:08.95#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:56:08.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:56:08.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:56:08.95#ibcon#*before write, iclass 21, count 0 2006.189.07:56:08.95#ibcon#enter sib2, iclass 21, count 0 2006.189.07:56:08.95#ibcon#flushed, iclass 21, count 0 2006.189.07:56:08.95#ibcon#about to write, iclass 21, count 0 2006.189.07:56:08.95#ibcon#wrote, iclass 21, count 0 2006.189.07:56:08.95#ibcon#about to read 3, iclass 21, count 0 2006.189.07:56:08.99#ibcon#read 3, iclass 21, count 0 2006.189.07:56:08.99#ibcon#about to read 4, iclass 21, count 0 2006.189.07:56:08.99#ibcon#read 4, iclass 21, count 0 2006.189.07:56:08.99#ibcon#about to read 5, iclass 21, count 0 2006.189.07:56:08.99#ibcon#read 5, iclass 21, count 0 2006.189.07:56:08.99#ibcon#about to read 6, iclass 21, count 0 2006.189.07:56:08.99#ibcon#read 6, iclass 21, count 0 2006.189.07:56:08.99#ibcon#end of sib2, iclass 21, count 0 2006.189.07:56:08.99#ibcon#*after write, iclass 21, count 0 2006.189.07:56:08.99#ibcon#*before return 0, iclass 21, count 0 2006.189.07:56:08.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:08.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:08.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:56:08.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:56:08.99$vc4f8/va=4,7 2006.189.07:56:08.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:56:08.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:56:08.99#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:08.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:09.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:09.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:09.05#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:56:09.05#ibcon#first serial, iclass 23, count 2 2006.189.07:56:09.05#ibcon#enter sib2, iclass 23, count 2 2006.189.07:56:09.05#ibcon#flushed, iclass 23, count 2 2006.189.07:56:09.05#ibcon#about to write, iclass 23, count 2 2006.189.07:56:09.05#ibcon#wrote, iclass 23, count 2 2006.189.07:56:09.05#ibcon#about to read 3, iclass 23, count 2 2006.189.07:56:09.07#ibcon#read 3, iclass 23, count 2 2006.189.07:56:09.07#ibcon#about to read 4, iclass 23, count 2 2006.189.07:56:09.07#ibcon#read 4, iclass 23, count 2 2006.189.07:56:09.07#ibcon#about to read 5, iclass 23, count 2 2006.189.07:56:09.07#ibcon#read 5, iclass 23, count 2 2006.189.07:56:09.07#ibcon#about to read 6, iclass 23, count 2 2006.189.07:56:09.07#ibcon#read 6, iclass 23, count 2 2006.189.07:56:09.07#ibcon#end of sib2, iclass 23, count 2 2006.189.07:56:09.07#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:56:09.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:56:09.07#ibcon#[25=AT04-07\r\n] 2006.189.07:56:09.07#ibcon#*before write, iclass 23, count 2 2006.189.07:56:09.07#ibcon#enter sib2, iclass 23, count 2 2006.189.07:56:09.07#ibcon#flushed, iclass 23, count 2 2006.189.07:56:09.07#ibcon#about to write, iclass 23, count 2 2006.189.07:56:09.07#ibcon#wrote, iclass 23, count 2 2006.189.07:56:09.07#ibcon#about to read 3, iclass 23, count 2 2006.189.07:56:09.10#ibcon#read 3, iclass 23, count 2 2006.189.07:56:09.10#ibcon#about to read 4, iclass 23, count 2 2006.189.07:56:09.10#ibcon#read 4, iclass 23, count 2 2006.189.07:56:09.10#ibcon#about to read 5, iclass 23, count 2 2006.189.07:56:09.10#ibcon#read 5, iclass 23, count 2 2006.189.07:56:09.10#ibcon#about to read 6, iclass 23, count 2 2006.189.07:56:09.10#ibcon#read 6, iclass 23, count 2 2006.189.07:56:09.10#ibcon#end of sib2, iclass 23, count 2 2006.189.07:56:09.10#ibcon#*after write, iclass 23, count 2 2006.189.07:56:09.10#ibcon#*before return 0, iclass 23, count 2 2006.189.07:56:09.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:09.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:09.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:56:09.10#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:09.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:09.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:09.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:09.22#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:56:09.22#ibcon#first serial, iclass 23, count 0 2006.189.07:56:09.22#ibcon#enter sib2, iclass 23, count 0 2006.189.07:56:09.22#ibcon#flushed, iclass 23, count 0 2006.189.07:56:09.22#ibcon#about to write, iclass 23, count 0 2006.189.07:56:09.22#ibcon#wrote, iclass 23, count 0 2006.189.07:56:09.22#ibcon#about to read 3, iclass 23, count 0 2006.189.07:56:09.24#ibcon#read 3, iclass 23, count 0 2006.189.07:56:09.24#ibcon#about to read 4, iclass 23, count 0 2006.189.07:56:09.24#ibcon#read 4, iclass 23, count 0 2006.189.07:56:09.24#ibcon#about to read 5, iclass 23, count 0 2006.189.07:56:09.24#ibcon#read 5, iclass 23, count 0 2006.189.07:56:09.24#ibcon#about to read 6, iclass 23, count 0 2006.189.07:56:09.24#ibcon#read 6, iclass 23, count 0 2006.189.07:56:09.24#ibcon#end of sib2, iclass 23, count 0 2006.189.07:56:09.24#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:56:09.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:56:09.24#ibcon#[25=USB\r\n] 2006.189.07:56:09.24#ibcon#*before write, iclass 23, count 0 2006.189.07:56:09.24#ibcon#enter sib2, iclass 23, count 0 2006.189.07:56:09.24#ibcon#flushed, iclass 23, count 0 2006.189.07:56:09.24#ibcon#about to write, iclass 23, count 0 2006.189.07:56:09.24#ibcon#wrote, iclass 23, count 0 2006.189.07:56:09.24#ibcon#about to read 3, iclass 23, count 0 2006.189.07:56:09.27#ibcon#read 3, iclass 23, count 0 2006.189.07:56:09.27#ibcon#about to read 4, iclass 23, count 0 2006.189.07:56:09.27#ibcon#read 4, iclass 23, count 0 2006.189.07:56:09.27#ibcon#about to read 5, iclass 23, count 0 2006.189.07:56:09.27#ibcon#read 5, iclass 23, count 0 2006.189.07:56:09.27#ibcon#about to read 6, iclass 23, count 0 2006.189.07:56:09.27#ibcon#read 6, iclass 23, count 0 2006.189.07:56:09.27#ibcon#end of sib2, iclass 23, count 0 2006.189.07:56:09.27#ibcon#*after write, iclass 23, count 0 2006.189.07:56:09.27#ibcon#*before return 0, iclass 23, count 0 2006.189.07:56:09.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:09.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:09.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:56:09.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:56:09.27$vc4f8/valo=5,652.99 2006.189.07:56:09.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:56:09.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:56:09.27#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:09.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:09.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:09.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:09.27#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:56:09.27#ibcon#first serial, iclass 25, count 0 2006.189.07:56:09.27#ibcon#enter sib2, iclass 25, count 0 2006.189.07:56:09.27#ibcon#flushed, iclass 25, count 0 2006.189.07:56:09.27#ibcon#about to write, iclass 25, count 0 2006.189.07:56:09.27#ibcon#wrote, iclass 25, count 0 2006.189.07:56:09.27#ibcon#about to read 3, iclass 25, count 0 2006.189.07:56:09.29#ibcon#read 3, iclass 25, count 0 2006.189.07:56:09.29#ibcon#about to read 4, iclass 25, count 0 2006.189.07:56:09.29#ibcon#read 4, iclass 25, count 0 2006.189.07:56:09.29#ibcon#about to read 5, iclass 25, count 0 2006.189.07:56:09.29#ibcon#read 5, iclass 25, count 0 2006.189.07:56:09.29#ibcon#about to read 6, iclass 25, count 0 2006.189.07:56:09.29#ibcon#read 6, iclass 25, count 0 2006.189.07:56:09.29#ibcon#end of sib2, iclass 25, count 0 2006.189.07:56:09.29#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:56:09.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:56:09.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:56:09.29#ibcon#*before write, iclass 25, count 0 2006.189.07:56:09.29#ibcon#enter sib2, iclass 25, count 0 2006.189.07:56:09.29#ibcon#flushed, iclass 25, count 0 2006.189.07:56:09.29#ibcon#about to write, iclass 25, count 0 2006.189.07:56:09.29#ibcon#wrote, iclass 25, count 0 2006.189.07:56:09.29#ibcon#about to read 3, iclass 25, count 0 2006.189.07:56:09.33#ibcon#read 3, iclass 25, count 0 2006.189.07:56:09.33#ibcon#about to read 4, iclass 25, count 0 2006.189.07:56:09.33#ibcon#read 4, iclass 25, count 0 2006.189.07:56:09.33#ibcon#about to read 5, iclass 25, count 0 2006.189.07:56:09.33#ibcon#read 5, iclass 25, count 0 2006.189.07:56:09.33#ibcon#about to read 6, iclass 25, count 0 2006.189.07:56:09.33#ibcon#read 6, iclass 25, count 0 2006.189.07:56:09.33#ibcon#end of sib2, iclass 25, count 0 2006.189.07:56:09.33#ibcon#*after write, iclass 25, count 0 2006.189.07:56:09.33#ibcon#*before return 0, iclass 25, count 0 2006.189.07:56:09.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:09.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:09.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:56:09.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:56:09.33$vc4f8/va=5,7 2006.189.07:56:09.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:56:09.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:56:09.33#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:09.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:09.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:09.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:09.39#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:56:09.39#ibcon#first serial, iclass 27, count 2 2006.189.07:56:09.39#ibcon#enter sib2, iclass 27, count 2 2006.189.07:56:09.39#ibcon#flushed, iclass 27, count 2 2006.189.07:56:09.39#ibcon#about to write, iclass 27, count 2 2006.189.07:56:09.39#ibcon#wrote, iclass 27, count 2 2006.189.07:56:09.39#ibcon#about to read 3, iclass 27, count 2 2006.189.07:56:09.41#ibcon#read 3, iclass 27, count 2 2006.189.07:56:09.41#ibcon#about to read 4, iclass 27, count 2 2006.189.07:56:09.41#ibcon#read 4, iclass 27, count 2 2006.189.07:56:09.41#ibcon#about to read 5, iclass 27, count 2 2006.189.07:56:09.41#ibcon#read 5, iclass 27, count 2 2006.189.07:56:09.41#ibcon#about to read 6, iclass 27, count 2 2006.189.07:56:09.41#ibcon#read 6, iclass 27, count 2 2006.189.07:56:09.41#ibcon#end of sib2, iclass 27, count 2 2006.189.07:56:09.41#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:56:09.41#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:56:09.41#ibcon#[25=AT05-07\r\n] 2006.189.07:56:09.41#ibcon#*before write, iclass 27, count 2 2006.189.07:56:09.41#ibcon#enter sib2, iclass 27, count 2 2006.189.07:56:09.41#ibcon#flushed, iclass 27, count 2 2006.189.07:56:09.41#ibcon#about to write, iclass 27, count 2 2006.189.07:56:09.41#ibcon#wrote, iclass 27, count 2 2006.189.07:56:09.41#ibcon#about to read 3, iclass 27, count 2 2006.189.07:56:09.44#ibcon#read 3, iclass 27, count 2 2006.189.07:56:09.44#ibcon#about to read 4, iclass 27, count 2 2006.189.07:56:09.44#ibcon#read 4, iclass 27, count 2 2006.189.07:56:09.44#ibcon#about to read 5, iclass 27, count 2 2006.189.07:56:09.44#ibcon#read 5, iclass 27, count 2 2006.189.07:56:09.44#ibcon#about to read 6, iclass 27, count 2 2006.189.07:56:09.44#ibcon#read 6, iclass 27, count 2 2006.189.07:56:09.44#ibcon#end of sib2, iclass 27, count 2 2006.189.07:56:09.44#ibcon#*after write, iclass 27, count 2 2006.189.07:56:09.44#ibcon#*before return 0, iclass 27, count 2 2006.189.07:56:09.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:09.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:09.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:56:09.44#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:09.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:09.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:09.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:09.56#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:56:09.56#ibcon#first serial, iclass 27, count 0 2006.189.07:56:09.56#ibcon#enter sib2, iclass 27, count 0 2006.189.07:56:09.56#ibcon#flushed, iclass 27, count 0 2006.189.07:56:09.56#ibcon#about to write, iclass 27, count 0 2006.189.07:56:09.56#ibcon#wrote, iclass 27, count 0 2006.189.07:56:09.56#ibcon#about to read 3, iclass 27, count 0 2006.189.07:56:09.58#ibcon#read 3, iclass 27, count 0 2006.189.07:56:09.58#ibcon#about to read 4, iclass 27, count 0 2006.189.07:56:09.58#ibcon#read 4, iclass 27, count 0 2006.189.07:56:09.58#ibcon#about to read 5, iclass 27, count 0 2006.189.07:56:09.58#ibcon#read 5, iclass 27, count 0 2006.189.07:56:09.58#ibcon#about to read 6, iclass 27, count 0 2006.189.07:56:09.58#ibcon#read 6, iclass 27, count 0 2006.189.07:56:09.58#ibcon#end of sib2, iclass 27, count 0 2006.189.07:56:09.58#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:56:09.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:56:09.58#ibcon#[25=USB\r\n] 2006.189.07:56:09.58#ibcon#*before write, iclass 27, count 0 2006.189.07:56:09.58#ibcon#enter sib2, iclass 27, count 0 2006.189.07:56:09.58#ibcon#flushed, iclass 27, count 0 2006.189.07:56:09.58#ibcon#about to write, iclass 27, count 0 2006.189.07:56:09.58#ibcon#wrote, iclass 27, count 0 2006.189.07:56:09.58#ibcon#about to read 3, iclass 27, count 0 2006.189.07:56:09.61#ibcon#read 3, iclass 27, count 0 2006.189.07:56:09.61#ibcon#about to read 4, iclass 27, count 0 2006.189.07:56:09.61#ibcon#read 4, iclass 27, count 0 2006.189.07:56:09.61#ibcon#about to read 5, iclass 27, count 0 2006.189.07:56:09.61#ibcon#read 5, iclass 27, count 0 2006.189.07:56:09.61#ibcon#about to read 6, iclass 27, count 0 2006.189.07:56:09.61#ibcon#read 6, iclass 27, count 0 2006.189.07:56:09.61#ibcon#end of sib2, iclass 27, count 0 2006.189.07:56:09.61#ibcon#*after write, iclass 27, count 0 2006.189.07:56:09.61#ibcon#*before return 0, iclass 27, count 0 2006.189.07:56:09.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:09.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:09.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:56:09.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:56:09.61$vc4f8/valo=6,772.99 2006.189.07:56:09.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:56:09.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:56:09.61#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:09.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:09.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:09.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:09.61#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:56:09.61#ibcon#first serial, iclass 29, count 0 2006.189.07:56:09.61#ibcon#enter sib2, iclass 29, count 0 2006.189.07:56:09.61#ibcon#flushed, iclass 29, count 0 2006.189.07:56:09.61#ibcon#about to write, iclass 29, count 0 2006.189.07:56:09.61#ibcon#wrote, iclass 29, count 0 2006.189.07:56:09.61#ibcon#about to read 3, iclass 29, count 0 2006.189.07:56:09.63#ibcon#read 3, iclass 29, count 0 2006.189.07:56:09.63#ibcon#about to read 4, iclass 29, count 0 2006.189.07:56:09.63#ibcon#read 4, iclass 29, count 0 2006.189.07:56:09.63#ibcon#about to read 5, iclass 29, count 0 2006.189.07:56:09.63#ibcon#read 5, iclass 29, count 0 2006.189.07:56:09.63#ibcon#about to read 6, iclass 29, count 0 2006.189.07:56:09.63#ibcon#read 6, iclass 29, count 0 2006.189.07:56:09.63#ibcon#end of sib2, iclass 29, count 0 2006.189.07:56:09.63#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:56:09.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:56:09.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:56:09.63#ibcon#*before write, iclass 29, count 0 2006.189.07:56:09.63#ibcon#enter sib2, iclass 29, count 0 2006.189.07:56:09.63#ibcon#flushed, iclass 29, count 0 2006.189.07:56:09.63#ibcon#about to write, iclass 29, count 0 2006.189.07:56:09.63#ibcon#wrote, iclass 29, count 0 2006.189.07:56:09.63#ibcon#about to read 3, iclass 29, count 0 2006.189.07:56:09.67#ibcon#read 3, iclass 29, count 0 2006.189.07:56:09.67#ibcon#about to read 4, iclass 29, count 0 2006.189.07:56:09.67#ibcon#read 4, iclass 29, count 0 2006.189.07:56:09.67#ibcon#about to read 5, iclass 29, count 0 2006.189.07:56:09.67#ibcon#read 5, iclass 29, count 0 2006.189.07:56:09.67#ibcon#about to read 6, iclass 29, count 0 2006.189.07:56:09.67#ibcon#read 6, iclass 29, count 0 2006.189.07:56:09.67#ibcon#end of sib2, iclass 29, count 0 2006.189.07:56:09.67#ibcon#*after write, iclass 29, count 0 2006.189.07:56:09.67#ibcon#*before return 0, iclass 29, count 0 2006.189.07:56:09.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:09.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:09.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:56:09.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:56:09.67$vc4f8/va=6,6 2006.189.07:56:09.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.07:56:09.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.07:56:09.67#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:09.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:56:09.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:56:09.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:56:09.73#ibcon#enter wrdev, iclass 31, count 2 2006.189.07:56:09.73#ibcon#first serial, iclass 31, count 2 2006.189.07:56:09.73#ibcon#enter sib2, iclass 31, count 2 2006.189.07:56:09.73#ibcon#flushed, iclass 31, count 2 2006.189.07:56:09.73#ibcon#about to write, iclass 31, count 2 2006.189.07:56:09.73#ibcon#wrote, iclass 31, count 2 2006.189.07:56:09.73#ibcon#about to read 3, iclass 31, count 2 2006.189.07:56:09.75#ibcon#read 3, iclass 31, count 2 2006.189.07:56:09.75#ibcon#about to read 4, iclass 31, count 2 2006.189.07:56:09.75#ibcon#read 4, iclass 31, count 2 2006.189.07:56:09.75#ibcon#about to read 5, iclass 31, count 2 2006.189.07:56:09.75#ibcon#read 5, iclass 31, count 2 2006.189.07:56:09.75#ibcon#about to read 6, iclass 31, count 2 2006.189.07:56:09.75#ibcon#read 6, iclass 31, count 2 2006.189.07:56:09.75#ibcon#end of sib2, iclass 31, count 2 2006.189.07:56:09.75#ibcon#*mode == 0, iclass 31, count 2 2006.189.07:56:09.75#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.07:56:09.75#ibcon#[25=AT06-06\r\n] 2006.189.07:56:09.75#ibcon#*before write, iclass 31, count 2 2006.189.07:56:09.75#ibcon#enter sib2, iclass 31, count 2 2006.189.07:56:09.75#ibcon#flushed, iclass 31, count 2 2006.189.07:56:09.75#ibcon#about to write, iclass 31, count 2 2006.189.07:56:09.75#ibcon#wrote, iclass 31, count 2 2006.189.07:56:09.75#ibcon#about to read 3, iclass 31, count 2 2006.189.07:56:09.78#ibcon#read 3, iclass 31, count 2 2006.189.07:56:09.78#ibcon#about to read 4, iclass 31, count 2 2006.189.07:56:09.78#ibcon#read 4, iclass 31, count 2 2006.189.07:56:09.78#ibcon#about to read 5, iclass 31, count 2 2006.189.07:56:09.78#ibcon#read 5, iclass 31, count 2 2006.189.07:56:09.78#ibcon#about to read 6, iclass 31, count 2 2006.189.07:56:09.78#ibcon#read 6, iclass 31, count 2 2006.189.07:56:09.78#ibcon#end of sib2, iclass 31, count 2 2006.189.07:56:09.78#ibcon#*after write, iclass 31, count 2 2006.189.07:56:09.78#ibcon#*before return 0, iclass 31, count 2 2006.189.07:56:09.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:56:09.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.07:56:09.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.07:56:09.78#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:09.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:56:09.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:56:09.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:56:09.90#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:56:09.90#ibcon#first serial, iclass 31, count 0 2006.189.07:56:09.90#ibcon#enter sib2, iclass 31, count 0 2006.189.07:56:09.90#ibcon#flushed, iclass 31, count 0 2006.189.07:56:09.90#ibcon#about to write, iclass 31, count 0 2006.189.07:56:09.90#ibcon#wrote, iclass 31, count 0 2006.189.07:56:09.90#ibcon#about to read 3, iclass 31, count 0 2006.189.07:56:09.92#ibcon#read 3, iclass 31, count 0 2006.189.07:56:09.92#ibcon#about to read 4, iclass 31, count 0 2006.189.07:56:09.92#ibcon#read 4, iclass 31, count 0 2006.189.07:56:09.92#ibcon#about to read 5, iclass 31, count 0 2006.189.07:56:09.92#ibcon#read 5, iclass 31, count 0 2006.189.07:56:09.92#ibcon#about to read 6, iclass 31, count 0 2006.189.07:56:09.92#ibcon#read 6, iclass 31, count 0 2006.189.07:56:09.92#ibcon#end of sib2, iclass 31, count 0 2006.189.07:56:09.92#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:56:09.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:56:09.92#ibcon#[25=USB\r\n] 2006.189.07:56:09.92#ibcon#*before write, iclass 31, count 0 2006.189.07:56:09.92#ibcon#enter sib2, iclass 31, count 0 2006.189.07:56:09.92#ibcon#flushed, iclass 31, count 0 2006.189.07:56:09.92#ibcon#about to write, iclass 31, count 0 2006.189.07:56:09.92#ibcon#wrote, iclass 31, count 0 2006.189.07:56:09.92#ibcon#about to read 3, iclass 31, count 0 2006.189.07:56:09.95#ibcon#read 3, iclass 31, count 0 2006.189.07:56:09.95#ibcon#about to read 4, iclass 31, count 0 2006.189.07:56:09.95#ibcon#read 4, iclass 31, count 0 2006.189.07:56:09.95#ibcon#about to read 5, iclass 31, count 0 2006.189.07:56:09.95#ibcon#read 5, iclass 31, count 0 2006.189.07:56:09.95#ibcon#about to read 6, iclass 31, count 0 2006.189.07:56:09.95#ibcon#read 6, iclass 31, count 0 2006.189.07:56:09.95#ibcon#end of sib2, iclass 31, count 0 2006.189.07:56:09.95#ibcon#*after write, iclass 31, count 0 2006.189.07:56:09.95#ibcon#*before return 0, iclass 31, count 0 2006.189.07:56:09.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:56:09.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.07:56:09.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:56:09.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:56:09.95$vc4f8/valo=7,832.99 2006.189.07:56:09.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.07:56:09.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.07:56:09.95#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:09.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:56:09.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:56:09.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:56:09.95#ibcon#enter wrdev, iclass 33, count 0 2006.189.07:56:09.95#ibcon#first serial, iclass 33, count 0 2006.189.07:56:09.95#ibcon#enter sib2, iclass 33, count 0 2006.189.07:56:09.95#ibcon#flushed, iclass 33, count 0 2006.189.07:56:09.95#ibcon#about to write, iclass 33, count 0 2006.189.07:56:09.95#ibcon#wrote, iclass 33, count 0 2006.189.07:56:09.95#ibcon#about to read 3, iclass 33, count 0 2006.189.07:56:09.97#ibcon#read 3, iclass 33, count 0 2006.189.07:56:09.97#ibcon#about to read 4, iclass 33, count 0 2006.189.07:56:09.97#ibcon#read 4, iclass 33, count 0 2006.189.07:56:09.97#ibcon#about to read 5, iclass 33, count 0 2006.189.07:56:09.97#ibcon#read 5, iclass 33, count 0 2006.189.07:56:09.97#ibcon#about to read 6, iclass 33, count 0 2006.189.07:56:09.97#ibcon#read 6, iclass 33, count 0 2006.189.07:56:09.97#ibcon#end of sib2, iclass 33, count 0 2006.189.07:56:09.97#ibcon#*mode == 0, iclass 33, count 0 2006.189.07:56:09.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.07:56:09.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:56:09.97#ibcon#*before write, iclass 33, count 0 2006.189.07:56:09.97#ibcon#enter sib2, iclass 33, count 0 2006.189.07:56:09.97#ibcon#flushed, iclass 33, count 0 2006.189.07:56:09.97#ibcon#about to write, iclass 33, count 0 2006.189.07:56:09.97#ibcon#wrote, iclass 33, count 0 2006.189.07:56:09.97#ibcon#about to read 3, iclass 33, count 0 2006.189.07:56:10.01#ibcon#read 3, iclass 33, count 0 2006.189.07:56:10.01#ibcon#about to read 4, iclass 33, count 0 2006.189.07:56:10.01#ibcon#read 4, iclass 33, count 0 2006.189.07:56:10.01#ibcon#about to read 5, iclass 33, count 0 2006.189.07:56:10.01#ibcon#read 5, iclass 33, count 0 2006.189.07:56:10.01#ibcon#about to read 6, iclass 33, count 0 2006.189.07:56:10.01#ibcon#read 6, iclass 33, count 0 2006.189.07:56:10.01#ibcon#end of sib2, iclass 33, count 0 2006.189.07:56:10.01#ibcon#*after write, iclass 33, count 0 2006.189.07:56:10.01#ibcon#*before return 0, iclass 33, count 0 2006.189.07:56:10.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:56:10.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.07:56:10.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.07:56:10.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.07:56:10.01$vc4f8/va=7,6 2006.189.07:56:10.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.07:56:10.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.07:56:10.01#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:10.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:56:10.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:56:10.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:56:10.07#ibcon#enter wrdev, iclass 35, count 2 2006.189.07:56:10.07#ibcon#first serial, iclass 35, count 2 2006.189.07:56:10.07#ibcon#enter sib2, iclass 35, count 2 2006.189.07:56:10.07#ibcon#flushed, iclass 35, count 2 2006.189.07:56:10.07#ibcon#about to write, iclass 35, count 2 2006.189.07:56:10.07#ibcon#wrote, iclass 35, count 2 2006.189.07:56:10.07#ibcon#about to read 3, iclass 35, count 2 2006.189.07:56:10.09#ibcon#read 3, iclass 35, count 2 2006.189.07:56:10.09#ibcon#about to read 4, iclass 35, count 2 2006.189.07:56:10.09#ibcon#read 4, iclass 35, count 2 2006.189.07:56:10.09#ibcon#about to read 5, iclass 35, count 2 2006.189.07:56:10.09#ibcon#read 5, iclass 35, count 2 2006.189.07:56:10.09#ibcon#about to read 6, iclass 35, count 2 2006.189.07:56:10.09#ibcon#read 6, iclass 35, count 2 2006.189.07:56:10.09#ibcon#end of sib2, iclass 35, count 2 2006.189.07:56:10.09#ibcon#*mode == 0, iclass 35, count 2 2006.189.07:56:10.09#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.07:56:10.09#ibcon#[25=AT07-06\r\n] 2006.189.07:56:10.09#ibcon#*before write, iclass 35, count 2 2006.189.07:56:10.09#ibcon#enter sib2, iclass 35, count 2 2006.189.07:56:10.09#ibcon#flushed, iclass 35, count 2 2006.189.07:56:10.09#ibcon#about to write, iclass 35, count 2 2006.189.07:56:10.09#ibcon#wrote, iclass 35, count 2 2006.189.07:56:10.09#ibcon#about to read 3, iclass 35, count 2 2006.189.07:56:10.12#ibcon#read 3, iclass 35, count 2 2006.189.07:56:10.12#ibcon#about to read 4, iclass 35, count 2 2006.189.07:56:10.12#ibcon#read 4, iclass 35, count 2 2006.189.07:56:10.12#ibcon#about to read 5, iclass 35, count 2 2006.189.07:56:10.12#ibcon#read 5, iclass 35, count 2 2006.189.07:56:10.12#ibcon#about to read 6, iclass 35, count 2 2006.189.07:56:10.12#ibcon#read 6, iclass 35, count 2 2006.189.07:56:10.12#ibcon#end of sib2, iclass 35, count 2 2006.189.07:56:10.12#ibcon#*after write, iclass 35, count 2 2006.189.07:56:10.12#ibcon#*before return 0, iclass 35, count 2 2006.189.07:56:10.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:56:10.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.07:56:10.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.07:56:10.12#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:10.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:56:10.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:56:10.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:56:10.24#ibcon#enter wrdev, iclass 35, count 0 2006.189.07:56:10.24#ibcon#first serial, iclass 35, count 0 2006.189.07:56:10.24#ibcon#enter sib2, iclass 35, count 0 2006.189.07:56:10.24#ibcon#flushed, iclass 35, count 0 2006.189.07:56:10.24#ibcon#about to write, iclass 35, count 0 2006.189.07:56:10.24#ibcon#wrote, iclass 35, count 0 2006.189.07:56:10.24#ibcon#about to read 3, iclass 35, count 0 2006.189.07:56:10.26#ibcon#read 3, iclass 35, count 0 2006.189.07:56:10.26#ibcon#about to read 4, iclass 35, count 0 2006.189.07:56:10.26#ibcon#read 4, iclass 35, count 0 2006.189.07:56:10.26#ibcon#about to read 5, iclass 35, count 0 2006.189.07:56:10.26#ibcon#read 5, iclass 35, count 0 2006.189.07:56:10.26#ibcon#about to read 6, iclass 35, count 0 2006.189.07:56:10.26#ibcon#read 6, iclass 35, count 0 2006.189.07:56:10.26#ibcon#end of sib2, iclass 35, count 0 2006.189.07:56:10.26#ibcon#*mode == 0, iclass 35, count 0 2006.189.07:56:10.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.07:56:10.26#ibcon#[25=USB\r\n] 2006.189.07:56:10.26#ibcon#*before write, iclass 35, count 0 2006.189.07:56:10.26#ibcon#enter sib2, iclass 35, count 0 2006.189.07:56:10.26#ibcon#flushed, iclass 35, count 0 2006.189.07:56:10.26#ibcon#about to write, iclass 35, count 0 2006.189.07:56:10.26#ibcon#wrote, iclass 35, count 0 2006.189.07:56:10.26#ibcon#about to read 3, iclass 35, count 0 2006.189.07:56:10.29#ibcon#read 3, iclass 35, count 0 2006.189.07:56:10.29#ibcon#about to read 4, iclass 35, count 0 2006.189.07:56:10.29#ibcon#read 4, iclass 35, count 0 2006.189.07:56:10.29#ibcon#about to read 5, iclass 35, count 0 2006.189.07:56:10.29#ibcon#read 5, iclass 35, count 0 2006.189.07:56:10.29#ibcon#about to read 6, iclass 35, count 0 2006.189.07:56:10.29#ibcon#read 6, iclass 35, count 0 2006.189.07:56:10.29#ibcon#end of sib2, iclass 35, count 0 2006.189.07:56:10.29#ibcon#*after write, iclass 35, count 0 2006.189.07:56:10.29#ibcon#*before return 0, iclass 35, count 0 2006.189.07:56:10.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:56:10.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.07:56:10.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.07:56:10.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.07:56:10.29$vc4f8/valo=8,852.99 2006.189.07:56:10.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.07:56:10.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.07:56:10.29#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:10.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:56:10.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:56:10.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:56:10.29#ibcon#enter wrdev, iclass 37, count 0 2006.189.07:56:10.29#ibcon#first serial, iclass 37, count 0 2006.189.07:56:10.29#ibcon#enter sib2, iclass 37, count 0 2006.189.07:56:10.29#ibcon#flushed, iclass 37, count 0 2006.189.07:56:10.29#ibcon#about to write, iclass 37, count 0 2006.189.07:56:10.29#ibcon#wrote, iclass 37, count 0 2006.189.07:56:10.29#ibcon#about to read 3, iclass 37, count 0 2006.189.07:56:10.31#ibcon#read 3, iclass 37, count 0 2006.189.07:56:10.31#ibcon#about to read 4, iclass 37, count 0 2006.189.07:56:10.31#ibcon#read 4, iclass 37, count 0 2006.189.07:56:10.31#ibcon#about to read 5, iclass 37, count 0 2006.189.07:56:10.31#ibcon#read 5, iclass 37, count 0 2006.189.07:56:10.31#ibcon#about to read 6, iclass 37, count 0 2006.189.07:56:10.31#ibcon#read 6, iclass 37, count 0 2006.189.07:56:10.31#ibcon#end of sib2, iclass 37, count 0 2006.189.07:56:10.31#ibcon#*mode == 0, iclass 37, count 0 2006.189.07:56:10.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.07:56:10.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:56:10.31#ibcon#*before write, iclass 37, count 0 2006.189.07:56:10.31#ibcon#enter sib2, iclass 37, count 0 2006.189.07:56:10.31#ibcon#flushed, iclass 37, count 0 2006.189.07:56:10.31#ibcon#about to write, iclass 37, count 0 2006.189.07:56:10.31#ibcon#wrote, iclass 37, count 0 2006.189.07:56:10.31#ibcon#about to read 3, iclass 37, count 0 2006.189.07:56:10.35#ibcon#read 3, iclass 37, count 0 2006.189.07:56:10.35#ibcon#about to read 4, iclass 37, count 0 2006.189.07:56:10.35#ibcon#read 4, iclass 37, count 0 2006.189.07:56:10.35#ibcon#about to read 5, iclass 37, count 0 2006.189.07:56:10.35#ibcon#read 5, iclass 37, count 0 2006.189.07:56:10.35#ibcon#about to read 6, iclass 37, count 0 2006.189.07:56:10.35#ibcon#read 6, iclass 37, count 0 2006.189.07:56:10.35#ibcon#end of sib2, iclass 37, count 0 2006.189.07:56:10.35#ibcon#*after write, iclass 37, count 0 2006.189.07:56:10.35#ibcon#*before return 0, iclass 37, count 0 2006.189.07:56:10.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:56:10.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.07:56:10.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.07:56:10.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.07:56:10.35$vc4f8/va=8,6 2006.189.07:56:10.35#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.07:56:10.35#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.07:56:10.35#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:10.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:56:10.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:56:10.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:56:10.41#ibcon#enter wrdev, iclass 39, count 2 2006.189.07:56:10.41#ibcon#first serial, iclass 39, count 2 2006.189.07:56:10.41#ibcon#enter sib2, iclass 39, count 2 2006.189.07:56:10.41#ibcon#flushed, iclass 39, count 2 2006.189.07:56:10.41#ibcon#about to write, iclass 39, count 2 2006.189.07:56:10.41#ibcon#wrote, iclass 39, count 2 2006.189.07:56:10.41#ibcon#about to read 3, iclass 39, count 2 2006.189.07:56:10.43#ibcon#read 3, iclass 39, count 2 2006.189.07:56:10.43#ibcon#about to read 4, iclass 39, count 2 2006.189.07:56:10.43#ibcon#read 4, iclass 39, count 2 2006.189.07:56:10.43#ibcon#about to read 5, iclass 39, count 2 2006.189.07:56:10.43#ibcon#read 5, iclass 39, count 2 2006.189.07:56:10.43#ibcon#about to read 6, iclass 39, count 2 2006.189.07:56:10.43#ibcon#read 6, iclass 39, count 2 2006.189.07:56:10.43#ibcon#end of sib2, iclass 39, count 2 2006.189.07:56:10.43#ibcon#*mode == 0, iclass 39, count 2 2006.189.07:56:10.43#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.07:56:10.43#ibcon#[25=AT08-06\r\n] 2006.189.07:56:10.43#ibcon#*before write, iclass 39, count 2 2006.189.07:56:10.43#ibcon#enter sib2, iclass 39, count 2 2006.189.07:56:10.43#ibcon#flushed, iclass 39, count 2 2006.189.07:56:10.43#ibcon#about to write, iclass 39, count 2 2006.189.07:56:10.43#ibcon#wrote, iclass 39, count 2 2006.189.07:56:10.43#ibcon#about to read 3, iclass 39, count 2 2006.189.07:56:10.46#ibcon#read 3, iclass 39, count 2 2006.189.07:56:10.46#ibcon#about to read 4, iclass 39, count 2 2006.189.07:56:10.46#ibcon#read 4, iclass 39, count 2 2006.189.07:56:10.46#ibcon#about to read 5, iclass 39, count 2 2006.189.07:56:10.46#ibcon#read 5, iclass 39, count 2 2006.189.07:56:10.46#ibcon#about to read 6, iclass 39, count 2 2006.189.07:56:10.46#ibcon#read 6, iclass 39, count 2 2006.189.07:56:10.46#ibcon#end of sib2, iclass 39, count 2 2006.189.07:56:10.46#ibcon#*after write, iclass 39, count 2 2006.189.07:56:10.46#ibcon#*before return 0, iclass 39, count 2 2006.189.07:56:10.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:56:10.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.07:56:10.46#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.07:56:10.46#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:10.46#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:56:10.58#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:56:10.58#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:56:10.58#ibcon#enter wrdev, iclass 39, count 0 2006.189.07:56:10.58#ibcon#first serial, iclass 39, count 0 2006.189.07:56:10.58#ibcon#enter sib2, iclass 39, count 0 2006.189.07:56:10.58#ibcon#flushed, iclass 39, count 0 2006.189.07:56:10.58#ibcon#about to write, iclass 39, count 0 2006.189.07:56:10.58#ibcon#wrote, iclass 39, count 0 2006.189.07:56:10.58#ibcon#about to read 3, iclass 39, count 0 2006.189.07:56:10.60#ibcon#read 3, iclass 39, count 0 2006.189.07:56:10.60#ibcon#about to read 4, iclass 39, count 0 2006.189.07:56:10.60#ibcon#read 4, iclass 39, count 0 2006.189.07:56:10.60#ibcon#about to read 5, iclass 39, count 0 2006.189.07:56:10.60#ibcon#read 5, iclass 39, count 0 2006.189.07:56:10.60#ibcon#about to read 6, iclass 39, count 0 2006.189.07:56:10.60#ibcon#read 6, iclass 39, count 0 2006.189.07:56:10.60#ibcon#end of sib2, iclass 39, count 0 2006.189.07:56:10.60#ibcon#*mode == 0, iclass 39, count 0 2006.189.07:56:10.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.07:56:10.60#ibcon#[25=USB\r\n] 2006.189.07:56:10.60#ibcon#*before write, iclass 39, count 0 2006.189.07:56:10.60#ibcon#enter sib2, iclass 39, count 0 2006.189.07:56:10.60#ibcon#flushed, iclass 39, count 0 2006.189.07:56:10.60#ibcon#about to write, iclass 39, count 0 2006.189.07:56:10.60#ibcon#wrote, iclass 39, count 0 2006.189.07:56:10.60#ibcon#about to read 3, iclass 39, count 0 2006.189.07:56:10.63#ibcon#read 3, iclass 39, count 0 2006.189.07:56:10.63#ibcon#about to read 4, iclass 39, count 0 2006.189.07:56:10.63#ibcon#read 4, iclass 39, count 0 2006.189.07:56:10.63#ibcon#about to read 5, iclass 39, count 0 2006.189.07:56:10.63#ibcon#read 5, iclass 39, count 0 2006.189.07:56:10.63#ibcon#about to read 6, iclass 39, count 0 2006.189.07:56:10.63#ibcon#read 6, iclass 39, count 0 2006.189.07:56:10.63#ibcon#end of sib2, iclass 39, count 0 2006.189.07:56:10.63#ibcon#*after write, iclass 39, count 0 2006.189.07:56:10.63#ibcon#*before return 0, iclass 39, count 0 2006.189.07:56:10.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:56:10.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.07:56:10.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.07:56:10.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.07:56:10.63$vc4f8/vblo=1,632.99 2006.189.07:56:10.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.07:56:10.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.07:56:10.63#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:10.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:56:10.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:56:10.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:56:10.63#ibcon#enter wrdev, iclass 3, count 0 2006.189.07:56:10.63#ibcon#first serial, iclass 3, count 0 2006.189.07:56:10.63#ibcon#enter sib2, iclass 3, count 0 2006.189.07:56:10.63#ibcon#flushed, iclass 3, count 0 2006.189.07:56:10.63#ibcon#about to write, iclass 3, count 0 2006.189.07:56:10.63#ibcon#wrote, iclass 3, count 0 2006.189.07:56:10.63#ibcon#about to read 3, iclass 3, count 0 2006.189.07:56:10.65#ibcon#read 3, iclass 3, count 0 2006.189.07:56:10.65#ibcon#about to read 4, iclass 3, count 0 2006.189.07:56:10.65#ibcon#read 4, iclass 3, count 0 2006.189.07:56:10.65#ibcon#about to read 5, iclass 3, count 0 2006.189.07:56:10.65#ibcon#read 5, iclass 3, count 0 2006.189.07:56:10.65#ibcon#about to read 6, iclass 3, count 0 2006.189.07:56:10.65#ibcon#read 6, iclass 3, count 0 2006.189.07:56:10.65#ibcon#end of sib2, iclass 3, count 0 2006.189.07:56:10.65#ibcon#*mode == 0, iclass 3, count 0 2006.189.07:56:10.65#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.07:56:10.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:56:10.65#ibcon#*before write, iclass 3, count 0 2006.189.07:56:10.65#ibcon#enter sib2, iclass 3, count 0 2006.189.07:56:10.65#ibcon#flushed, iclass 3, count 0 2006.189.07:56:10.65#ibcon#about to write, iclass 3, count 0 2006.189.07:56:10.65#ibcon#wrote, iclass 3, count 0 2006.189.07:56:10.65#ibcon#about to read 3, iclass 3, count 0 2006.189.07:56:10.69#ibcon#read 3, iclass 3, count 0 2006.189.07:56:10.69#ibcon#about to read 4, iclass 3, count 0 2006.189.07:56:10.69#ibcon#read 4, iclass 3, count 0 2006.189.07:56:10.69#ibcon#about to read 5, iclass 3, count 0 2006.189.07:56:10.69#ibcon#read 5, iclass 3, count 0 2006.189.07:56:10.69#ibcon#about to read 6, iclass 3, count 0 2006.189.07:56:10.69#ibcon#read 6, iclass 3, count 0 2006.189.07:56:10.69#ibcon#end of sib2, iclass 3, count 0 2006.189.07:56:10.69#ibcon#*after write, iclass 3, count 0 2006.189.07:56:10.69#ibcon#*before return 0, iclass 3, count 0 2006.189.07:56:10.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:56:10.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.07:56:10.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.07:56:10.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.07:56:10.69$vc4f8/vb=1,4 2006.189.07:56:10.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.07:56:10.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.07:56:10.69#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:10.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:56:10.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:56:10.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:56:10.69#ibcon#enter wrdev, iclass 5, count 2 2006.189.07:56:10.69#ibcon#first serial, iclass 5, count 2 2006.189.07:56:10.69#ibcon#enter sib2, iclass 5, count 2 2006.189.07:56:10.69#ibcon#flushed, iclass 5, count 2 2006.189.07:56:10.69#ibcon#about to write, iclass 5, count 2 2006.189.07:56:10.69#ibcon#wrote, iclass 5, count 2 2006.189.07:56:10.69#ibcon#about to read 3, iclass 5, count 2 2006.189.07:56:10.71#ibcon#read 3, iclass 5, count 2 2006.189.07:56:10.71#ibcon#about to read 4, iclass 5, count 2 2006.189.07:56:10.71#ibcon#read 4, iclass 5, count 2 2006.189.07:56:10.71#ibcon#about to read 5, iclass 5, count 2 2006.189.07:56:10.71#ibcon#read 5, iclass 5, count 2 2006.189.07:56:10.71#ibcon#about to read 6, iclass 5, count 2 2006.189.07:56:10.71#ibcon#read 6, iclass 5, count 2 2006.189.07:56:10.71#ibcon#end of sib2, iclass 5, count 2 2006.189.07:56:10.71#ibcon#*mode == 0, iclass 5, count 2 2006.189.07:56:10.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.07:56:10.71#ibcon#[27=AT01-04\r\n] 2006.189.07:56:10.71#ibcon#*before write, iclass 5, count 2 2006.189.07:56:10.71#ibcon#enter sib2, iclass 5, count 2 2006.189.07:56:10.71#ibcon#flushed, iclass 5, count 2 2006.189.07:56:10.71#ibcon#about to write, iclass 5, count 2 2006.189.07:56:10.71#ibcon#wrote, iclass 5, count 2 2006.189.07:56:10.71#ibcon#about to read 3, iclass 5, count 2 2006.189.07:56:10.74#ibcon#read 3, iclass 5, count 2 2006.189.07:56:10.74#ibcon#about to read 4, iclass 5, count 2 2006.189.07:56:10.74#ibcon#read 4, iclass 5, count 2 2006.189.07:56:10.74#ibcon#about to read 5, iclass 5, count 2 2006.189.07:56:10.74#ibcon#read 5, iclass 5, count 2 2006.189.07:56:10.74#ibcon#about to read 6, iclass 5, count 2 2006.189.07:56:10.74#ibcon#read 6, iclass 5, count 2 2006.189.07:56:10.74#ibcon#end of sib2, iclass 5, count 2 2006.189.07:56:10.74#ibcon#*after write, iclass 5, count 2 2006.189.07:56:10.74#ibcon#*before return 0, iclass 5, count 2 2006.189.07:56:10.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:56:10.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.07:56:10.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.07:56:10.74#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:10.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:56:10.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:56:10.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:56:10.86#ibcon#enter wrdev, iclass 5, count 0 2006.189.07:56:10.86#ibcon#first serial, iclass 5, count 0 2006.189.07:56:10.86#ibcon#enter sib2, iclass 5, count 0 2006.189.07:56:10.86#ibcon#flushed, iclass 5, count 0 2006.189.07:56:10.86#ibcon#about to write, iclass 5, count 0 2006.189.07:56:10.86#ibcon#wrote, iclass 5, count 0 2006.189.07:56:10.86#ibcon#about to read 3, iclass 5, count 0 2006.189.07:56:10.88#ibcon#read 3, iclass 5, count 0 2006.189.07:56:10.88#ibcon#about to read 4, iclass 5, count 0 2006.189.07:56:10.88#ibcon#read 4, iclass 5, count 0 2006.189.07:56:10.88#ibcon#about to read 5, iclass 5, count 0 2006.189.07:56:10.88#ibcon#read 5, iclass 5, count 0 2006.189.07:56:10.88#ibcon#about to read 6, iclass 5, count 0 2006.189.07:56:10.88#ibcon#read 6, iclass 5, count 0 2006.189.07:56:10.88#ibcon#end of sib2, iclass 5, count 0 2006.189.07:56:10.88#ibcon#*mode == 0, iclass 5, count 0 2006.189.07:56:10.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.07:56:10.88#ibcon#[27=USB\r\n] 2006.189.07:56:10.88#ibcon#*before write, iclass 5, count 0 2006.189.07:56:10.88#ibcon#enter sib2, iclass 5, count 0 2006.189.07:56:10.88#ibcon#flushed, iclass 5, count 0 2006.189.07:56:10.88#ibcon#about to write, iclass 5, count 0 2006.189.07:56:10.88#ibcon#wrote, iclass 5, count 0 2006.189.07:56:10.88#ibcon#about to read 3, iclass 5, count 0 2006.189.07:56:10.91#ibcon#read 3, iclass 5, count 0 2006.189.07:56:10.91#ibcon#about to read 4, iclass 5, count 0 2006.189.07:56:10.91#ibcon#read 4, iclass 5, count 0 2006.189.07:56:10.91#ibcon#about to read 5, iclass 5, count 0 2006.189.07:56:10.91#ibcon#read 5, iclass 5, count 0 2006.189.07:56:10.91#ibcon#about to read 6, iclass 5, count 0 2006.189.07:56:10.91#ibcon#read 6, iclass 5, count 0 2006.189.07:56:10.91#ibcon#end of sib2, iclass 5, count 0 2006.189.07:56:10.91#ibcon#*after write, iclass 5, count 0 2006.189.07:56:10.91#ibcon#*before return 0, iclass 5, count 0 2006.189.07:56:10.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:56:10.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.07:56:10.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.07:56:10.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.07:56:10.91$vc4f8/vblo=2,640.99 2006.189.07:56:10.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.07:56:10.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.07:56:10.91#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:10.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:10.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:10.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:10.91#ibcon#enter wrdev, iclass 7, count 0 2006.189.07:56:10.91#ibcon#first serial, iclass 7, count 0 2006.189.07:56:10.91#ibcon#enter sib2, iclass 7, count 0 2006.189.07:56:10.91#ibcon#flushed, iclass 7, count 0 2006.189.07:56:10.91#ibcon#about to write, iclass 7, count 0 2006.189.07:56:10.91#ibcon#wrote, iclass 7, count 0 2006.189.07:56:10.91#ibcon#about to read 3, iclass 7, count 0 2006.189.07:56:10.93#ibcon#read 3, iclass 7, count 0 2006.189.07:56:10.93#ibcon#about to read 4, iclass 7, count 0 2006.189.07:56:10.93#ibcon#read 4, iclass 7, count 0 2006.189.07:56:10.93#ibcon#about to read 5, iclass 7, count 0 2006.189.07:56:10.93#ibcon#read 5, iclass 7, count 0 2006.189.07:56:10.93#ibcon#about to read 6, iclass 7, count 0 2006.189.07:56:10.93#ibcon#read 6, iclass 7, count 0 2006.189.07:56:10.93#ibcon#end of sib2, iclass 7, count 0 2006.189.07:56:10.93#ibcon#*mode == 0, iclass 7, count 0 2006.189.07:56:10.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.07:56:10.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:56:10.93#ibcon#*before write, iclass 7, count 0 2006.189.07:56:10.93#ibcon#enter sib2, iclass 7, count 0 2006.189.07:56:10.93#ibcon#flushed, iclass 7, count 0 2006.189.07:56:10.93#ibcon#about to write, iclass 7, count 0 2006.189.07:56:10.93#ibcon#wrote, iclass 7, count 0 2006.189.07:56:10.93#ibcon#about to read 3, iclass 7, count 0 2006.189.07:56:10.97#ibcon#read 3, iclass 7, count 0 2006.189.07:56:10.97#ibcon#about to read 4, iclass 7, count 0 2006.189.07:56:10.97#ibcon#read 4, iclass 7, count 0 2006.189.07:56:10.97#ibcon#about to read 5, iclass 7, count 0 2006.189.07:56:10.97#ibcon#read 5, iclass 7, count 0 2006.189.07:56:10.97#ibcon#about to read 6, iclass 7, count 0 2006.189.07:56:10.97#ibcon#read 6, iclass 7, count 0 2006.189.07:56:10.97#ibcon#end of sib2, iclass 7, count 0 2006.189.07:56:10.97#ibcon#*after write, iclass 7, count 0 2006.189.07:56:10.97#ibcon#*before return 0, iclass 7, count 0 2006.189.07:56:10.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:10.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.07:56:10.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.07:56:10.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.07:56:10.97$vc4f8/vb=2,4 2006.189.07:56:10.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.07:56:10.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.07:56:10.97#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:10.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:11.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:11.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:11.03#ibcon#enter wrdev, iclass 11, count 2 2006.189.07:56:11.03#ibcon#first serial, iclass 11, count 2 2006.189.07:56:11.03#ibcon#enter sib2, iclass 11, count 2 2006.189.07:56:11.03#ibcon#flushed, iclass 11, count 2 2006.189.07:56:11.03#ibcon#about to write, iclass 11, count 2 2006.189.07:56:11.03#ibcon#wrote, iclass 11, count 2 2006.189.07:56:11.03#ibcon#about to read 3, iclass 11, count 2 2006.189.07:56:11.05#ibcon#read 3, iclass 11, count 2 2006.189.07:56:11.05#ibcon#about to read 4, iclass 11, count 2 2006.189.07:56:11.05#ibcon#read 4, iclass 11, count 2 2006.189.07:56:11.05#ibcon#about to read 5, iclass 11, count 2 2006.189.07:56:11.05#ibcon#read 5, iclass 11, count 2 2006.189.07:56:11.05#ibcon#about to read 6, iclass 11, count 2 2006.189.07:56:11.05#ibcon#read 6, iclass 11, count 2 2006.189.07:56:11.05#ibcon#end of sib2, iclass 11, count 2 2006.189.07:56:11.05#ibcon#*mode == 0, iclass 11, count 2 2006.189.07:56:11.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.07:56:11.05#ibcon#[27=AT02-04\r\n] 2006.189.07:56:11.05#ibcon#*before write, iclass 11, count 2 2006.189.07:56:11.05#ibcon#enter sib2, iclass 11, count 2 2006.189.07:56:11.05#ibcon#flushed, iclass 11, count 2 2006.189.07:56:11.05#ibcon#about to write, iclass 11, count 2 2006.189.07:56:11.05#ibcon#wrote, iclass 11, count 2 2006.189.07:56:11.05#ibcon#about to read 3, iclass 11, count 2 2006.189.07:56:11.08#ibcon#read 3, iclass 11, count 2 2006.189.07:56:11.08#ibcon#about to read 4, iclass 11, count 2 2006.189.07:56:11.08#ibcon#read 4, iclass 11, count 2 2006.189.07:56:11.08#ibcon#about to read 5, iclass 11, count 2 2006.189.07:56:11.08#ibcon#read 5, iclass 11, count 2 2006.189.07:56:11.08#ibcon#about to read 6, iclass 11, count 2 2006.189.07:56:11.08#ibcon#read 6, iclass 11, count 2 2006.189.07:56:11.08#ibcon#end of sib2, iclass 11, count 2 2006.189.07:56:11.08#ibcon#*after write, iclass 11, count 2 2006.189.07:56:11.08#ibcon#*before return 0, iclass 11, count 2 2006.189.07:56:11.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:11.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.07:56:11.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.07:56:11.08#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:11.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:11.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:11.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:11.20#ibcon#enter wrdev, iclass 11, count 0 2006.189.07:56:11.20#ibcon#first serial, iclass 11, count 0 2006.189.07:56:11.20#ibcon#enter sib2, iclass 11, count 0 2006.189.07:56:11.20#ibcon#flushed, iclass 11, count 0 2006.189.07:56:11.20#ibcon#about to write, iclass 11, count 0 2006.189.07:56:11.20#ibcon#wrote, iclass 11, count 0 2006.189.07:56:11.20#ibcon#about to read 3, iclass 11, count 0 2006.189.07:56:11.22#ibcon#read 3, iclass 11, count 0 2006.189.07:56:11.22#ibcon#about to read 4, iclass 11, count 0 2006.189.07:56:11.22#ibcon#read 4, iclass 11, count 0 2006.189.07:56:11.22#ibcon#about to read 5, iclass 11, count 0 2006.189.07:56:11.22#ibcon#read 5, iclass 11, count 0 2006.189.07:56:11.22#ibcon#about to read 6, iclass 11, count 0 2006.189.07:56:11.22#ibcon#read 6, iclass 11, count 0 2006.189.07:56:11.22#ibcon#end of sib2, iclass 11, count 0 2006.189.07:56:11.22#ibcon#*mode == 0, iclass 11, count 0 2006.189.07:56:11.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.07:56:11.22#ibcon#[27=USB\r\n] 2006.189.07:56:11.22#ibcon#*before write, iclass 11, count 0 2006.189.07:56:11.22#ibcon#enter sib2, iclass 11, count 0 2006.189.07:56:11.22#ibcon#flushed, iclass 11, count 0 2006.189.07:56:11.22#ibcon#about to write, iclass 11, count 0 2006.189.07:56:11.22#ibcon#wrote, iclass 11, count 0 2006.189.07:56:11.22#ibcon#about to read 3, iclass 11, count 0 2006.189.07:56:11.25#ibcon#read 3, iclass 11, count 0 2006.189.07:56:11.25#ibcon#about to read 4, iclass 11, count 0 2006.189.07:56:11.25#ibcon#read 4, iclass 11, count 0 2006.189.07:56:11.25#ibcon#about to read 5, iclass 11, count 0 2006.189.07:56:11.25#ibcon#read 5, iclass 11, count 0 2006.189.07:56:11.25#ibcon#about to read 6, iclass 11, count 0 2006.189.07:56:11.25#ibcon#read 6, iclass 11, count 0 2006.189.07:56:11.25#ibcon#end of sib2, iclass 11, count 0 2006.189.07:56:11.25#ibcon#*after write, iclass 11, count 0 2006.189.07:56:11.25#ibcon#*before return 0, iclass 11, count 0 2006.189.07:56:11.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:11.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.07:56:11.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.07:56:11.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.07:56:11.25$vc4f8/vblo=3,656.99 2006.189.07:56:11.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.07:56:11.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.07:56:11.25#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:11.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:11.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:11.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:11.25#ibcon#enter wrdev, iclass 13, count 0 2006.189.07:56:11.25#ibcon#first serial, iclass 13, count 0 2006.189.07:56:11.25#ibcon#enter sib2, iclass 13, count 0 2006.189.07:56:11.25#ibcon#flushed, iclass 13, count 0 2006.189.07:56:11.25#ibcon#about to write, iclass 13, count 0 2006.189.07:56:11.25#ibcon#wrote, iclass 13, count 0 2006.189.07:56:11.25#ibcon#about to read 3, iclass 13, count 0 2006.189.07:56:11.27#ibcon#read 3, iclass 13, count 0 2006.189.07:56:11.27#ibcon#about to read 4, iclass 13, count 0 2006.189.07:56:11.27#ibcon#read 4, iclass 13, count 0 2006.189.07:56:11.27#ibcon#about to read 5, iclass 13, count 0 2006.189.07:56:11.27#ibcon#read 5, iclass 13, count 0 2006.189.07:56:11.27#ibcon#about to read 6, iclass 13, count 0 2006.189.07:56:11.27#ibcon#read 6, iclass 13, count 0 2006.189.07:56:11.27#ibcon#end of sib2, iclass 13, count 0 2006.189.07:56:11.27#ibcon#*mode == 0, iclass 13, count 0 2006.189.07:56:11.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.07:56:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:56:11.27#ibcon#*before write, iclass 13, count 0 2006.189.07:56:11.27#ibcon#enter sib2, iclass 13, count 0 2006.189.07:56:11.27#ibcon#flushed, iclass 13, count 0 2006.189.07:56:11.27#ibcon#about to write, iclass 13, count 0 2006.189.07:56:11.27#ibcon#wrote, iclass 13, count 0 2006.189.07:56:11.27#ibcon#about to read 3, iclass 13, count 0 2006.189.07:56:11.31#ibcon#read 3, iclass 13, count 0 2006.189.07:56:11.31#ibcon#about to read 4, iclass 13, count 0 2006.189.07:56:11.31#ibcon#read 4, iclass 13, count 0 2006.189.07:56:11.31#ibcon#about to read 5, iclass 13, count 0 2006.189.07:56:11.31#ibcon#read 5, iclass 13, count 0 2006.189.07:56:11.31#ibcon#about to read 6, iclass 13, count 0 2006.189.07:56:11.31#ibcon#read 6, iclass 13, count 0 2006.189.07:56:11.31#ibcon#end of sib2, iclass 13, count 0 2006.189.07:56:11.31#ibcon#*after write, iclass 13, count 0 2006.189.07:56:11.31#ibcon#*before return 0, iclass 13, count 0 2006.189.07:56:11.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:11.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.07:56:11.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.07:56:11.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.07:56:11.31$vc4f8/vb=3,4 2006.189.07:56:11.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.07:56:11.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.07:56:11.31#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:11.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:11.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:11.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:11.37#ibcon#enter wrdev, iclass 15, count 2 2006.189.07:56:11.37#ibcon#first serial, iclass 15, count 2 2006.189.07:56:11.37#ibcon#enter sib2, iclass 15, count 2 2006.189.07:56:11.37#ibcon#flushed, iclass 15, count 2 2006.189.07:56:11.37#ibcon#about to write, iclass 15, count 2 2006.189.07:56:11.37#ibcon#wrote, iclass 15, count 2 2006.189.07:56:11.37#ibcon#about to read 3, iclass 15, count 2 2006.189.07:56:11.39#ibcon#read 3, iclass 15, count 2 2006.189.07:56:11.39#ibcon#about to read 4, iclass 15, count 2 2006.189.07:56:11.39#ibcon#read 4, iclass 15, count 2 2006.189.07:56:11.39#ibcon#about to read 5, iclass 15, count 2 2006.189.07:56:11.39#ibcon#read 5, iclass 15, count 2 2006.189.07:56:11.39#ibcon#about to read 6, iclass 15, count 2 2006.189.07:56:11.39#ibcon#read 6, iclass 15, count 2 2006.189.07:56:11.39#ibcon#end of sib2, iclass 15, count 2 2006.189.07:56:11.39#ibcon#*mode == 0, iclass 15, count 2 2006.189.07:56:11.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.07:56:11.39#ibcon#[27=AT03-04\r\n] 2006.189.07:56:11.39#ibcon#*before write, iclass 15, count 2 2006.189.07:56:11.39#ibcon#enter sib2, iclass 15, count 2 2006.189.07:56:11.39#ibcon#flushed, iclass 15, count 2 2006.189.07:56:11.39#ibcon#about to write, iclass 15, count 2 2006.189.07:56:11.39#ibcon#wrote, iclass 15, count 2 2006.189.07:56:11.39#ibcon#about to read 3, iclass 15, count 2 2006.189.07:56:11.42#ibcon#read 3, iclass 15, count 2 2006.189.07:56:11.42#ibcon#about to read 4, iclass 15, count 2 2006.189.07:56:11.42#ibcon#read 4, iclass 15, count 2 2006.189.07:56:11.42#ibcon#about to read 5, iclass 15, count 2 2006.189.07:56:11.42#ibcon#read 5, iclass 15, count 2 2006.189.07:56:11.42#ibcon#about to read 6, iclass 15, count 2 2006.189.07:56:11.42#ibcon#read 6, iclass 15, count 2 2006.189.07:56:11.42#ibcon#end of sib2, iclass 15, count 2 2006.189.07:56:11.42#ibcon#*after write, iclass 15, count 2 2006.189.07:56:11.42#ibcon#*before return 0, iclass 15, count 2 2006.189.07:56:11.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:11.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.07:56:11.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.07:56:11.42#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:11.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:11.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:11.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:11.54#ibcon#enter wrdev, iclass 15, count 0 2006.189.07:56:11.54#ibcon#first serial, iclass 15, count 0 2006.189.07:56:11.54#ibcon#enter sib2, iclass 15, count 0 2006.189.07:56:11.54#ibcon#flushed, iclass 15, count 0 2006.189.07:56:11.54#ibcon#about to write, iclass 15, count 0 2006.189.07:56:11.54#ibcon#wrote, iclass 15, count 0 2006.189.07:56:11.54#ibcon#about to read 3, iclass 15, count 0 2006.189.07:56:11.56#ibcon#read 3, iclass 15, count 0 2006.189.07:56:11.56#ibcon#about to read 4, iclass 15, count 0 2006.189.07:56:11.56#ibcon#read 4, iclass 15, count 0 2006.189.07:56:11.56#ibcon#about to read 5, iclass 15, count 0 2006.189.07:56:11.56#ibcon#read 5, iclass 15, count 0 2006.189.07:56:11.56#ibcon#about to read 6, iclass 15, count 0 2006.189.07:56:11.56#ibcon#read 6, iclass 15, count 0 2006.189.07:56:11.56#ibcon#end of sib2, iclass 15, count 0 2006.189.07:56:11.56#ibcon#*mode == 0, iclass 15, count 0 2006.189.07:56:11.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.07:56:11.56#ibcon#[27=USB\r\n] 2006.189.07:56:11.56#ibcon#*before write, iclass 15, count 0 2006.189.07:56:11.56#ibcon#enter sib2, iclass 15, count 0 2006.189.07:56:11.56#ibcon#flushed, iclass 15, count 0 2006.189.07:56:11.56#ibcon#about to write, iclass 15, count 0 2006.189.07:56:11.56#ibcon#wrote, iclass 15, count 0 2006.189.07:56:11.56#ibcon#about to read 3, iclass 15, count 0 2006.189.07:56:11.59#ibcon#read 3, iclass 15, count 0 2006.189.07:56:11.59#ibcon#about to read 4, iclass 15, count 0 2006.189.07:56:11.59#ibcon#read 4, iclass 15, count 0 2006.189.07:56:11.59#ibcon#about to read 5, iclass 15, count 0 2006.189.07:56:11.59#ibcon#read 5, iclass 15, count 0 2006.189.07:56:11.59#ibcon#about to read 6, iclass 15, count 0 2006.189.07:56:11.59#ibcon#read 6, iclass 15, count 0 2006.189.07:56:11.59#ibcon#end of sib2, iclass 15, count 0 2006.189.07:56:11.59#ibcon#*after write, iclass 15, count 0 2006.189.07:56:11.59#ibcon#*before return 0, iclass 15, count 0 2006.189.07:56:11.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:11.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.07:56:11.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.07:56:11.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.07:56:11.59$vc4f8/vblo=4,712.99 2006.189.07:56:11.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:56:11.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:56:11.59#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:11.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:11.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:11.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:11.59#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:56:11.59#ibcon#first serial, iclass 17, count 0 2006.189.07:56:11.59#ibcon#enter sib2, iclass 17, count 0 2006.189.07:56:11.59#ibcon#flushed, iclass 17, count 0 2006.189.07:56:11.59#ibcon#about to write, iclass 17, count 0 2006.189.07:56:11.59#ibcon#wrote, iclass 17, count 0 2006.189.07:56:11.59#ibcon#about to read 3, iclass 17, count 0 2006.189.07:56:11.61#ibcon#read 3, iclass 17, count 0 2006.189.07:56:11.61#ibcon#about to read 4, iclass 17, count 0 2006.189.07:56:11.61#ibcon#read 4, iclass 17, count 0 2006.189.07:56:11.61#ibcon#about to read 5, iclass 17, count 0 2006.189.07:56:11.61#ibcon#read 5, iclass 17, count 0 2006.189.07:56:11.61#ibcon#about to read 6, iclass 17, count 0 2006.189.07:56:11.61#ibcon#read 6, iclass 17, count 0 2006.189.07:56:11.61#ibcon#end of sib2, iclass 17, count 0 2006.189.07:56:11.61#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:56:11.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:56:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:56:11.61#ibcon#*before write, iclass 17, count 0 2006.189.07:56:11.61#ibcon#enter sib2, iclass 17, count 0 2006.189.07:56:11.61#ibcon#flushed, iclass 17, count 0 2006.189.07:56:11.61#ibcon#about to write, iclass 17, count 0 2006.189.07:56:11.61#ibcon#wrote, iclass 17, count 0 2006.189.07:56:11.61#ibcon#about to read 3, iclass 17, count 0 2006.189.07:56:11.65#ibcon#read 3, iclass 17, count 0 2006.189.07:56:11.65#ibcon#about to read 4, iclass 17, count 0 2006.189.07:56:11.65#ibcon#read 4, iclass 17, count 0 2006.189.07:56:11.65#ibcon#about to read 5, iclass 17, count 0 2006.189.07:56:11.65#ibcon#read 5, iclass 17, count 0 2006.189.07:56:11.65#ibcon#about to read 6, iclass 17, count 0 2006.189.07:56:11.65#ibcon#read 6, iclass 17, count 0 2006.189.07:56:11.65#ibcon#end of sib2, iclass 17, count 0 2006.189.07:56:11.65#ibcon#*after write, iclass 17, count 0 2006.189.07:56:11.65#ibcon#*before return 0, iclass 17, count 0 2006.189.07:56:11.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:11.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:56:11.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:56:11.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:56:11.65$vc4f8/vb=4,4 2006.189.07:56:11.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.07:56:11.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.07:56:11.65#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:11.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:11.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:11.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:11.71#ibcon#enter wrdev, iclass 19, count 2 2006.189.07:56:11.71#ibcon#first serial, iclass 19, count 2 2006.189.07:56:11.71#ibcon#enter sib2, iclass 19, count 2 2006.189.07:56:11.71#ibcon#flushed, iclass 19, count 2 2006.189.07:56:11.71#ibcon#about to write, iclass 19, count 2 2006.189.07:56:11.71#ibcon#wrote, iclass 19, count 2 2006.189.07:56:11.71#ibcon#about to read 3, iclass 19, count 2 2006.189.07:56:11.73#ibcon#read 3, iclass 19, count 2 2006.189.07:56:11.73#ibcon#about to read 4, iclass 19, count 2 2006.189.07:56:11.73#ibcon#read 4, iclass 19, count 2 2006.189.07:56:11.73#ibcon#about to read 5, iclass 19, count 2 2006.189.07:56:11.73#ibcon#read 5, iclass 19, count 2 2006.189.07:56:11.73#ibcon#about to read 6, iclass 19, count 2 2006.189.07:56:11.73#ibcon#read 6, iclass 19, count 2 2006.189.07:56:11.73#ibcon#end of sib2, iclass 19, count 2 2006.189.07:56:11.73#ibcon#*mode == 0, iclass 19, count 2 2006.189.07:56:11.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.07:56:11.73#ibcon#[27=AT04-04\r\n] 2006.189.07:56:11.73#ibcon#*before write, iclass 19, count 2 2006.189.07:56:11.73#ibcon#enter sib2, iclass 19, count 2 2006.189.07:56:11.73#ibcon#flushed, iclass 19, count 2 2006.189.07:56:11.73#ibcon#about to write, iclass 19, count 2 2006.189.07:56:11.73#ibcon#wrote, iclass 19, count 2 2006.189.07:56:11.73#ibcon#about to read 3, iclass 19, count 2 2006.189.07:56:11.76#ibcon#read 3, iclass 19, count 2 2006.189.07:56:11.76#ibcon#about to read 4, iclass 19, count 2 2006.189.07:56:11.76#ibcon#read 4, iclass 19, count 2 2006.189.07:56:11.76#ibcon#about to read 5, iclass 19, count 2 2006.189.07:56:11.76#ibcon#read 5, iclass 19, count 2 2006.189.07:56:11.76#ibcon#about to read 6, iclass 19, count 2 2006.189.07:56:11.76#ibcon#read 6, iclass 19, count 2 2006.189.07:56:11.76#ibcon#end of sib2, iclass 19, count 2 2006.189.07:56:11.76#ibcon#*after write, iclass 19, count 2 2006.189.07:56:11.76#ibcon#*before return 0, iclass 19, count 2 2006.189.07:56:11.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:11.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.07:56:11.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.07:56:11.76#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:11.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:11.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:11.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:11.88#ibcon#enter wrdev, iclass 19, count 0 2006.189.07:56:11.88#ibcon#first serial, iclass 19, count 0 2006.189.07:56:11.88#ibcon#enter sib2, iclass 19, count 0 2006.189.07:56:11.88#ibcon#flushed, iclass 19, count 0 2006.189.07:56:11.88#ibcon#about to write, iclass 19, count 0 2006.189.07:56:11.88#ibcon#wrote, iclass 19, count 0 2006.189.07:56:11.88#ibcon#about to read 3, iclass 19, count 0 2006.189.07:56:11.90#ibcon#read 3, iclass 19, count 0 2006.189.07:56:11.90#ibcon#about to read 4, iclass 19, count 0 2006.189.07:56:11.90#ibcon#read 4, iclass 19, count 0 2006.189.07:56:11.90#ibcon#about to read 5, iclass 19, count 0 2006.189.07:56:11.90#ibcon#read 5, iclass 19, count 0 2006.189.07:56:11.90#ibcon#about to read 6, iclass 19, count 0 2006.189.07:56:11.90#ibcon#read 6, iclass 19, count 0 2006.189.07:56:11.90#ibcon#end of sib2, iclass 19, count 0 2006.189.07:56:11.90#ibcon#*mode == 0, iclass 19, count 0 2006.189.07:56:11.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.07:56:11.90#ibcon#[27=USB\r\n] 2006.189.07:56:11.90#ibcon#*before write, iclass 19, count 0 2006.189.07:56:11.90#ibcon#enter sib2, iclass 19, count 0 2006.189.07:56:11.90#ibcon#flushed, iclass 19, count 0 2006.189.07:56:11.90#ibcon#about to write, iclass 19, count 0 2006.189.07:56:11.90#ibcon#wrote, iclass 19, count 0 2006.189.07:56:11.90#ibcon#about to read 3, iclass 19, count 0 2006.189.07:56:11.93#ibcon#read 3, iclass 19, count 0 2006.189.07:56:11.93#ibcon#about to read 4, iclass 19, count 0 2006.189.07:56:11.93#ibcon#read 4, iclass 19, count 0 2006.189.07:56:11.93#ibcon#about to read 5, iclass 19, count 0 2006.189.07:56:11.93#ibcon#read 5, iclass 19, count 0 2006.189.07:56:11.93#ibcon#about to read 6, iclass 19, count 0 2006.189.07:56:11.93#ibcon#read 6, iclass 19, count 0 2006.189.07:56:11.93#ibcon#end of sib2, iclass 19, count 0 2006.189.07:56:11.93#ibcon#*after write, iclass 19, count 0 2006.189.07:56:11.93#ibcon#*before return 0, iclass 19, count 0 2006.189.07:56:11.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:11.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.07:56:11.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.07:56:11.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.07:56:11.93$vc4f8/vblo=5,744.99 2006.189.07:56:11.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.07:56:11.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.07:56:11.93#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:11.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:11.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:11.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:11.93#ibcon#enter wrdev, iclass 21, count 0 2006.189.07:56:11.93#ibcon#first serial, iclass 21, count 0 2006.189.07:56:11.93#ibcon#enter sib2, iclass 21, count 0 2006.189.07:56:11.93#ibcon#flushed, iclass 21, count 0 2006.189.07:56:11.93#ibcon#about to write, iclass 21, count 0 2006.189.07:56:11.93#ibcon#wrote, iclass 21, count 0 2006.189.07:56:11.93#ibcon#about to read 3, iclass 21, count 0 2006.189.07:56:11.95#ibcon#read 3, iclass 21, count 0 2006.189.07:56:11.95#ibcon#about to read 4, iclass 21, count 0 2006.189.07:56:11.95#ibcon#read 4, iclass 21, count 0 2006.189.07:56:11.95#ibcon#about to read 5, iclass 21, count 0 2006.189.07:56:11.95#ibcon#read 5, iclass 21, count 0 2006.189.07:56:11.95#ibcon#about to read 6, iclass 21, count 0 2006.189.07:56:11.95#ibcon#read 6, iclass 21, count 0 2006.189.07:56:11.95#ibcon#end of sib2, iclass 21, count 0 2006.189.07:56:11.95#ibcon#*mode == 0, iclass 21, count 0 2006.189.07:56:11.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.07:56:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:56:11.95#ibcon#*before write, iclass 21, count 0 2006.189.07:56:11.95#ibcon#enter sib2, iclass 21, count 0 2006.189.07:56:11.95#ibcon#flushed, iclass 21, count 0 2006.189.07:56:11.95#ibcon#about to write, iclass 21, count 0 2006.189.07:56:11.95#ibcon#wrote, iclass 21, count 0 2006.189.07:56:11.95#ibcon#about to read 3, iclass 21, count 0 2006.189.07:56:12.00#ibcon#read 3, iclass 21, count 0 2006.189.07:56:12.00#ibcon#about to read 4, iclass 21, count 0 2006.189.07:56:12.00#ibcon#read 4, iclass 21, count 0 2006.189.07:56:12.00#ibcon#about to read 5, iclass 21, count 0 2006.189.07:56:12.00#ibcon#read 5, iclass 21, count 0 2006.189.07:56:12.00#ibcon#about to read 6, iclass 21, count 0 2006.189.07:56:12.00#ibcon#read 6, iclass 21, count 0 2006.189.07:56:12.00#ibcon#end of sib2, iclass 21, count 0 2006.189.07:56:12.00#ibcon#*after write, iclass 21, count 0 2006.189.07:56:12.00#ibcon#*before return 0, iclass 21, count 0 2006.189.07:56:12.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:12.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.07:56:12.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.07:56:12.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.07:56:12.00$vc4f8/vb=5,4 2006.189.07:56:12.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.07:56:12.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.07:56:12.00#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:12.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:12.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:12.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:12.04#ibcon#enter wrdev, iclass 23, count 2 2006.189.07:56:12.04#ibcon#first serial, iclass 23, count 2 2006.189.07:56:12.04#ibcon#enter sib2, iclass 23, count 2 2006.189.07:56:12.04#ibcon#flushed, iclass 23, count 2 2006.189.07:56:12.04#ibcon#about to write, iclass 23, count 2 2006.189.07:56:12.04#ibcon#wrote, iclass 23, count 2 2006.189.07:56:12.04#ibcon#about to read 3, iclass 23, count 2 2006.189.07:56:12.06#ibcon#read 3, iclass 23, count 2 2006.189.07:56:12.06#ibcon#about to read 4, iclass 23, count 2 2006.189.07:56:12.06#ibcon#read 4, iclass 23, count 2 2006.189.07:56:12.06#ibcon#about to read 5, iclass 23, count 2 2006.189.07:56:12.06#ibcon#read 5, iclass 23, count 2 2006.189.07:56:12.06#ibcon#about to read 6, iclass 23, count 2 2006.189.07:56:12.06#ibcon#read 6, iclass 23, count 2 2006.189.07:56:12.06#ibcon#end of sib2, iclass 23, count 2 2006.189.07:56:12.06#ibcon#*mode == 0, iclass 23, count 2 2006.189.07:56:12.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.07:56:12.06#ibcon#[27=AT05-04\r\n] 2006.189.07:56:12.06#ibcon#*before write, iclass 23, count 2 2006.189.07:56:12.06#ibcon#enter sib2, iclass 23, count 2 2006.189.07:56:12.06#ibcon#flushed, iclass 23, count 2 2006.189.07:56:12.06#ibcon#about to write, iclass 23, count 2 2006.189.07:56:12.06#ibcon#wrote, iclass 23, count 2 2006.189.07:56:12.06#ibcon#about to read 3, iclass 23, count 2 2006.189.07:56:12.09#ibcon#read 3, iclass 23, count 2 2006.189.07:56:12.09#ibcon#about to read 4, iclass 23, count 2 2006.189.07:56:12.09#ibcon#read 4, iclass 23, count 2 2006.189.07:56:12.09#ibcon#about to read 5, iclass 23, count 2 2006.189.07:56:12.09#ibcon#read 5, iclass 23, count 2 2006.189.07:56:12.09#ibcon#about to read 6, iclass 23, count 2 2006.189.07:56:12.09#ibcon#read 6, iclass 23, count 2 2006.189.07:56:12.09#ibcon#end of sib2, iclass 23, count 2 2006.189.07:56:12.09#ibcon#*after write, iclass 23, count 2 2006.189.07:56:12.09#ibcon#*before return 0, iclass 23, count 2 2006.189.07:56:12.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:12.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.07:56:12.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.07:56:12.09#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:12.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:12.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:12.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:12.21#ibcon#enter wrdev, iclass 23, count 0 2006.189.07:56:12.21#ibcon#first serial, iclass 23, count 0 2006.189.07:56:12.21#ibcon#enter sib2, iclass 23, count 0 2006.189.07:56:12.21#ibcon#flushed, iclass 23, count 0 2006.189.07:56:12.21#ibcon#about to write, iclass 23, count 0 2006.189.07:56:12.21#ibcon#wrote, iclass 23, count 0 2006.189.07:56:12.21#ibcon#about to read 3, iclass 23, count 0 2006.189.07:56:12.23#ibcon#read 3, iclass 23, count 0 2006.189.07:56:12.23#ibcon#about to read 4, iclass 23, count 0 2006.189.07:56:12.23#ibcon#read 4, iclass 23, count 0 2006.189.07:56:12.23#ibcon#about to read 5, iclass 23, count 0 2006.189.07:56:12.23#ibcon#read 5, iclass 23, count 0 2006.189.07:56:12.23#ibcon#about to read 6, iclass 23, count 0 2006.189.07:56:12.23#ibcon#read 6, iclass 23, count 0 2006.189.07:56:12.23#ibcon#end of sib2, iclass 23, count 0 2006.189.07:56:12.23#ibcon#*mode == 0, iclass 23, count 0 2006.189.07:56:12.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.07:56:12.23#ibcon#[27=USB\r\n] 2006.189.07:56:12.23#ibcon#*before write, iclass 23, count 0 2006.189.07:56:12.23#ibcon#enter sib2, iclass 23, count 0 2006.189.07:56:12.23#ibcon#flushed, iclass 23, count 0 2006.189.07:56:12.23#ibcon#about to write, iclass 23, count 0 2006.189.07:56:12.23#ibcon#wrote, iclass 23, count 0 2006.189.07:56:12.23#ibcon#about to read 3, iclass 23, count 0 2006.189.07:56:12.26#ibcon#read 3, iclass 23, count 0 2006.189.07:56:12.26#ibcon#about to read 4, iclass 23, count 0 2006.189.07:56:12.26#ibcon#read 4, iclass 23, count 0 2006.189.07:56:12.26#ibcon#about to read 5, iclass 23, count 0 2006.189.07:56:12.26#ibcon#read 5, iclass 23, count 0 2006.189.07:56:12.26#ibcon#about to read 6, iclass 23, count 0 2006.189.07:56:12.26#ibcon#read 6, iclass 23, count 0 2006.189.07:56:12.26#ibcon#end of sib2, iclass 23, count 0 2006.189.07:56:12.26#ibcon#*after write, iclass 23, count 0 2006.189.07:56:12.26#ibcon#*before return 0, iclass 23, count 0 2006.189.07:56:12.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:12.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.07:56:12.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.07:56:12.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.07:56:12.26$vc4f8/vblo=6,752.99 2006.189.07:56:12.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.07:56:12.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.07:56:12.26#ibcon#ireg 17 cls_cnt 0 2006.189.07:56:12.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:12.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:12.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:12.26#ibcon#enter wrdev, iclass 25, count 0 2006.189.07:56:12.26#ibcon#first serial, iclass 25, count 0 2006.189.07:56:12.26#ibcon#enter sib2, iclass 25, count 0 2006.189.07:56:12.26#ibcon#flushed, iclass 25, count 0 2006.189.07:56:12.26#ibcon#about to write, iclass 25, count 0 2006.189.07:56:12.26#ibcon#wrote, iclass 25, count 0 2006.189.07:56:12.26#ibcon#about to read 3, iclass 25, count 0 2006.189.07:56:12.28#ibcon#read 3, iclass 25, count 0 2006.189.07:56:12.28#ibcon#about to read 4, iclass 25, count 0 2006.189.07:56:12.28#ibcon#read 4, iclass 25, count 0 2006.189.07:56:12.28#ibcon#about to read 5, iclass 25, count 0 2006.189.07:56:12.28#ibcon#read 5, iclass 25, count 0 2006.189.07:56:12.28#ibcon#about to read 6, iclass 25, count 0 2006.189.07:56:12.28#ibcon#read 6, iclass 25, count 0 2006.189.07:56:12.28#ibcon#end of sib2, iclass 25, count 0 2006.189.07:56:12.28#ibcon#*mode == 0, iclass 25, count 0 2006.189.07:56:12.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.07:56:12.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:56:12.28#ibcon#*before write, iclass 25, count 0 2006.189.07:56:12.28#ibcon#enter sib2, iclass 25, count 0 2006.189.07:56:12.28#ibcon#flushed, iclass 25, count 0 2006.189.07:56:12.28#ibcon#about to write, iclass 25, count 0 2006.189.07:56:12.28#ibcon#wrote, iclass 25, count 0 2006.189.07:56:12.28#ibcon#about to read 3, iclass 25, count 0 2006.189.07:56:12.32#ibcon#read 3, iclass 25, count 0 2006.189.07:56:12.32#ibcon#about to read 4, iclass 25, count 0 2006.189.07:56:12.32#ibcon#read 4, iclass 25, count 0 2006.189.07:56:12.32#ibcon#about to read 5, iclass 25, count 0 2006.189.07:56:12.32#ibcon#read 5, iclass 25, count 0 2006.189.07:56:12.32#ibcon#about to read 6, iclass 25, count 0 2006.189.07:56:12.32#ibcon#read 6, iclass 25, count 0 2006.189.07:56:12.32#ibcon#end of sib2, iclass 25, count 0 2006.189.07:56:12.32#ibcon#*after write, iclass 25, count 0 2006.189.07:56:12.32#ibcon#*before return 0, iclass 25, count 0 2006.189.07:56:12.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:12.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.07:56:12.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.07:56:12.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.07:56:12.32$vc4f8/vb=6,4 2006.189.07:56:12.32#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.07:56:12.32#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.07:56:12.32#ibcon#ireg 11 cls_cnt 2 2006.189.07:56:12.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:12.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:12.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:12.38#ibcon#enter wrdev, iclass 27, count 2 2006.189.07:56:12.38#ibcon#first serial, iclass 27, count 2 2006.189.07:56:12.38#ibcon#enter sib2, iclass 27, count 2 2006.189.07:56:12.38#ibcon#flushed, iclass 27, count 2 2006.189.07:56:12.38#ibcon#about to write, iclass 27, count 2 2006.189.07:56:12.38#ibcon#wrote, iclass 27, count 2 2006.189.07:56:12.38#ibcon#about to read 3, iclass 27, count 2 2006.189.07:56:12.40#ibcon#read 3, iclass 27, count 2 2006.189.07:56:12.40#ibcon#about to read 4, iclass 27, count 2 2006.189.07:56:12.40#ibcon#read 4, iclass 27, count 2 2006.189.07:56:12.40#ibcon#about to read 5, iclass 27, count 2 2006.189.07:56:12.40#ibcon#read 5, iclass 27, count 2 2006.189.07:56:12.40#ibcon#about to read 6, iclass 27, count 2 2006.189.07:56:12.40#ibcon#read 6, iclass 27, count 2 2006.189.07:56:12.40#ibcon#end of sib2, iclass 27, count 2 2006.189.07:56:12.40#ibcon#*mode == 0, iclass 27, count 2 2006.189.07:56:12.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.07:56:12.40#ibcon#[27=AT06-04\r\n] 2006.189.07:56:12.40#ibcon#*before write, iclass 27, count 2 2006.189.07:56:12.40#ibcon#enter sib2, iclass 27, count 2 2006.189.07:56:12.40#ibcon#flushed, iclass 27, count 2 2006.189.07:56:12.40#ibcon#about to write, iclass 27, count 2 2006.189.07:56:12.40#ibcon#wrote, iclass 27, count 2 2006.189.07:56:12.40#ibcon#about to read 3, iclass 27, count 2 2006.189.07:56:12.43#ibcon#read 3, iclass 27, count 2 2006.189.07:56:12.43#ibcon#about to read 4, iclass 27, count 2 2006.189.07:56:12.43#ibcon#read 4, iclass 27, count 2 2006.189.07:56:12.43#ibcon#about to read 5, iclass 27, count 2 2006.189.07:56:12.43#ibcon#read 5, iclass 27, count 2 2006.189.07:56:12.43#ibcon#about to read 6, iclass 27, count 2 2006.189.07:56:12.43#ibcon#read 6, iclass 27, count 2 2006.189.07:56:12.43#ibcon#end of sib2, iclass 27, count 2 2006.189.07:56:12.43#ibcon#*after write, iclass 27, count 2 2006.189.07:56:12.43#ibcon#*before return 0, iclass 27, count 2 2006.189.07:56:12.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:12.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.07:56:12.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.07:56:12.43#ibcon#ireg 7 cls_cnt 0 2006.189.07:56:12.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:12.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:12.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:12.55#ibcon#enter wrdev, iclass 27, count 0 2006.189.07:56:12.55#ibcon#first serial, iclass 27, count 0 2006.189.07:56:12.55#ibcon#enter sib2, iclass 27, count 0 2006.189.07:56:12.55#ibcon#flushed, iclass 27, count 0 2006.189.07:56:12.55#ibcon#about to write, iclass 27, count 0 2006.189.07:56:12.55#ibcon#wrote, iclass 27, count 0 2006.189.07:56:12.55#ibcon#about to read 3, iclass 27, count 0 2006.189.07:56:12.57#ibcon#read 3, iclass 27, count 0 2006.189.07:56:12.57#ibcon#about to read 4, iclass 27, count 0 2006.189.07:56:12.57#ibcon#read 4, iclass 27, count 0 2006.189.07:56:12.57#ibcon#about to read 5, iclass 27, count 0 2006.189.07:56:12.57#ibcon#read 5, iclass 27, count 0 2006.189.07:56:12.57#ibcon#about to read 6, iclass 27, count 0 2006.189.07:56:12.57#ibcon#read 6, iclass 27, count 0 2006.189.07:56:12.57#ibcon#end of sib2, iclass 27, count 0 2006.189.07:56:12.57#ibcon#*mode == 0, iclass 27, count 0 2006.189.07:56:12.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.07:56:12.57#ibcon#[27=USB\r\n] 2006.189.07:56:12.57#ibcon#*before write, iclass 27, count 0 2006.189.07:56:12.57#ibcon#enter sib2, iclass 27, count 0 2006.189.07:56:12.57#ibcon#flushed, iclass 27, count 0 2006.189.07:56:12.57#ibcon#about to write, iclass 27, count 0 2006.189.07:56:12.57#ibcon#wrote, iclass 27, count 0 2006.189.07:56:12.57#ibcon#about to read 3, iclass 27, count 0 2006.189.07:56:12.60#ibcon#read 3, iclass 27, count 0 2006.189.07:56:12.60#ibcon#about to read 4, iclass 27, count 0 2006.189.07:56:12.60#ibcon#read 4, iclass 27, count 0 2006.189.07:56:12.60#ibcon#about to read 5, iclass 27, count 0 2006.189.07:56:12.60#ibcon#read 5, iclass 27, count 0 2006.189.07:56:12.60#ibcon#about to read 6, iclass 27, count 0 2006.189.07:56:12.60#ibcon#read 6, iclass 27, count 0 2006.189.07:56:12.60#ibcon#end of sib2, iclass 27, count 0 2006.189.07:56:12.60#ibcon#*after write, iclass 27, count 0 2006.189.07:56:12.60#ibcon#*before return 0, iclass 27, count 0 2006.189.07:56:12.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:12.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.07:56:12.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.07:56:12.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.07:56:12.60$vc4f8/vabw=wide 2006.189.07:56:12.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.07:56:12.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.07:56:12.60#ibcon#ireg 8 cls_cnt 0 2006.189.07:56:12.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:12.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:12.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:12.60#ibcon#enter wrdev, iclass 29, count 0 2006.189.07:56:12.60#ibcon#first serial, iclass 29, count 0 2006.189.07:56:12.60#ibcon#enter sib2, iclass 29, count 0 2006.189.07:56:12.60#ibcon#flushed, iclass 29, count 0 2006.189.07:56:12.60#ibcon#about to write, iclass 29, count 0 2006.189.07:56:12.60#ibcon#wrote, iclass 29, count 0 2006.189.07:56:12.60#ibcon#about to read 3, iclass 29, count 0 2006.189.07:56:12.62#ibcon#read 3, iclass 29, count 0 2006.189.07:56:12.62#ibcon#about to read 4, iclass 29, count 0 2006.189.07:56:12.62#ibcon#read 4, iclass 29, count 0 2006.189.07:56:12.62#ibcon#about to read 5, iclass 29, count 0 2006.189.07:56:12.62#ibcon#read 5, iclass 29, count 0 2006.189.07:56:12.62#ibcon#about to read 6, iclass 29, count 0 2006.189.07:56:12.62#ibcon#read 6, iclass 29, count 0 2006.189.07:56:12.62#ibcon#end of sib2, iclass 29, count 0 2006.189.07:56:12.62#ibcon#*mode == 0, iclass 29, count 0 2006.189.07:56:12.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.07:56:12.62#ibcon#[25=BW32\r\n] 2006.189.07:56:12.62#ibcon#*before write, iclass 29, count 0 2006.189.07:56:12.62#ibcon#enter sib2, iclass 29, count 0 2006.189.07:56:12.62#ibcon#flushed, iclass 29, count 0 2006.189.07:56:12.62#ibcon#about to write, iclass 29, count 0 2006.189.07:56:12.62#ibcon#wrote, iclass 29, count 0 2006.189.07:56:12.62#ibcon#about to read 3, iclass 29, count 0 2006.189.07:56:12.65#ibcon#read 3, iclass 29, count 0 2006.189.07:56:12.65#ibcon#about to read 4, iclass 29, count 0 2006.189.07:56:12.65#ibcon#read 4, iclass 29, count 0 2006.189.07:56:12.65#ibcon#about to read 5, iclass 29, count 0 2006.189.07:56:12.65#ibcon#read 5, iclass 29, count 0 2006.189.07:56:12.65#ibcon#about to read 6, iclass 29, count 0 2006.189.07:56:12.65#ibcon#read 6, iclass 29, count 0 2006.189.07:56:12.65#ibcon#end of sib2, iclass 29, count 0 2006.189.07:56:12.65#ibcon#*after write, iclass 29, count 0 2006.189.07:56:12.65#ibcon#*before return 0, iclass 29, count 0 2006.189.07:56:12.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:12.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.07:56:12.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.07:56:12.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.07:56:12.65$vc4f8/vbbw=wide 2006.189.07:56:12.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.07:56:12.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.07:56:12.65#ibcon#ireg 8 cls_cnt 0 2006.189.07:56:12.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:56:12.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:56:12.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:56:12.72#ibcon#enter wrdev, iclass 31, count 0 2006.189.07:56:12.72#ibcon#first serial, iclass 31, count 0 2006.189.07:56:12.72#ibcon#enter sib2, iclass 31, count 0 2006.189.07:56:12.72#ibcon#flushed, iclass 31, count 0 2006.189.07:56:12.72#ibcon#about to write, iclass 31, count 0 2006.189.07:56:12.72#ibcon#wrote, iclass 31, count 0 2006.189.07:56:12.72#ibcon#about to read 3, iclass 31, count 0 2006.189.07:56:12.74#ibcon#read 3, iclass 31, count 0 2006.189.07:56:12.74#ibcon#about to read 4, iclass 31, count 0 2006.189.07:56:12.74#ibcon#read 4, iclass 31, count 0 2006.189.07:56:12.74#ibcon#about to read 5, iclass 31, count 0 2006.189.07:56:12.74#ibcon#read 5, iclass 31, count 0 2006.189.07:56:12.74#ibcon#about to read 6, iclass 31, count 0 2006.189.07:56:12.74#ibcon#read 6, iclass 31, count 0 2006.189.07:56:12.74#ibcon#end of sib2, iclass 31, count 0 2006.189.07:56:12.74#ibcon#*mode == 0, iclass 31, count 0 2006.189.07:56:12.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.07:56:12.74#ibcon#[27=BW32\r\n] 2006.189.07:56:12.74#ibcon#*before write, iclass 31, count 0 2006.189.07:56:12.74#ibcon#enter sib2, iclass 31, count 0 2006.189.07:56:12.74#ibcon#flushed, iclass 31, count 0 2006.189.07:56:12.74#ibcon#about to write, iclass 31, count 0 2006.189.07:56:12.74#ibcon#wrote, iclass 31, count 0 2006.189.07:56:12.74#ibcon#about to read 3, iclass 31, count 0 2006.189.07:56:12.77#ibcon#read 3, iclass 31, count 0 2006.189.07:56:12.77#ibcon#about to read 4, iclass 31, count 0 2006.189.07:56:12.77#ibcon#read 4, iclass 31, count 0 2006.189.07:56:12.77#ibcon#about to read 5, iclass 31, count 0 2006.189.07:56:12.77#ibcon#read 5, iclass 31, count 0 2006.189.07:56:12.77#ibcon#about to read 6, iclass 31, count 0 2006.189.07:56:12.77#ibcon#read 6, iclass 31, count 0 2006.189.07:56:12.77#ibcon#end of sib2, iclass 31, count 0 2006.189.07:56:12.77#ibcon#*after write, iclass 31, count 0 2006.189.07:56:12.77#ibcon#*before return 0, iclass 31, count 0 2006.189.07:56:12.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:56:12.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.07:56:12.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.07:56:12.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.07:56:12.77$4f8m12a/ifd4f 2006.189.07:56:12.77$ifd4f/lo= 2006.189.07:56:12.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:56:12.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:56:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:56:12.77$ifd4f/patch= 2006.189.07:56:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:56:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:56:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:56:12.77$4f8m12a/"form=m,16.000,1:2 2006.189.07:56:12.77$4f8m12a/"tpicd 2006.189.07:56:12.77$4f8m12a/echo=off 2006.189.07:56:12.77$4f8m12a/xlog=off 2006.189.07:56:12.77:!2006.189.07:58:20 2006.189.07:56:40.14#trakl#Source acquired 2006.189.07:56:40.14#flagr#flagr/antenna,acquired 2006.189.07:58:20.00:preob 2006.189.07:58:20.14/onsource/TRACKING 2006.189.07:58:20.14:!2006.189.07:58:30 2006.189.07:58:30.00:data_valid=on 2006.189.07:58:30.00:midob 2006.189.07:58:31.14/onsource/TRACKING 2006.189.07:58:31.14/wx/25.75,1009.1,90 2006.189.07:58:31.25/cable/+6.4546E-03 2006.189.07:58:32.34/va/01,08,usb,yes,32,34 2006.189.07:58:32.34/va/02,07,usb,yes,32,34 2006.189.07:58:32.34/va/03,06,usb,yes,34,34 2006.189.07:58:32.34/va/04,07,usb,yes,33,35 2006.189.07:58:32.34/va/05,07,usb,yes,35,38 2006.189.07:58:32.34/va/06,06,usb,yes,35,34 2006.189.07:58:32.34/va/07,06,usb,yes,35,35 2006.189.07:58:32.34/va/08,06,usb,yes,37,37 2006.189.07:58:32.57/valo/01,532.99,yes,locked 2006.189.07:58:32.57/valo/02,572.99,yes,locked 2006.189.07:58:32.57/valo/03,672.99,yes,locked 2006.189.07:58:32.57/valo/04,832.99,yes,locked 2006.189.07:58:32.57/valo/05,652.99,yes,locked 2006.189.07:58:32.57/valo/06,772.99,yes,locked 2006.189.07:58:32.57/valo/07,832.99,yes,locked 2006.189.07:58:32.57/valo/08,852.99,yes,locked 2006.189.07:58:33.66/vb/01,04,usb,yes,30,29 2006.189.07:58:33.66/vb/02,04,usb,yes,32,34 2006.189.07:58:33.66/vb/03,04,usb,yes,29,32 2006.189.07:58:33.66/vb/04,04,usb,yes,30,30 2006.189.07:58:33.66/vb/05,04,usb,yes,28,32 2006.189.07:58:33.66/vb/06,04,usb,yes,29,32 2006.189.07:58:33.66/vb/07,04,usb,yes,31,31 2006.189.07:58:33.66/vb/08,04,usb,yes,29,32 2006.189.07:58:33.89/vblo/01,632.99,yes,locked 2006.189.07:58:33.89/vblo/02,640.99,yes,locked 2006.189.07:58:33.89/vblo/03,656.99,yes,locked 2006.189.07:58:33.89/vblo/04,712.99,yes,locked 2006.189.07:58:33.89/vblo/05,744.99,yes,locked 2006.189.07:58:33.89/vblo/06,752.99,yes,locked 2006.189.07:58:33.89/vblo/07,734.99,yes,locked 2006.189.07:58:33.89/vblo/08,744.99,yes,locked 2006.189.07:58:34.04/vabw/8 2006.189.07:58:34.19/vbbw/8 2006.189.07:58:34.31/xfe/off,on,15.5 2006.189.07:58:34.71/ifatt/23,28,28,28 2006.189.07:58:35.08/fmout-gps/S +2.97E-07 2006.189.07:58:35.16:!2006.189.07:59:30 2006.189.07:59:30.00:data_valid=off 2006.189.07:59:30.00:postob 2006.189.07:59:30.16/cable/+6.4543E-03 2006.189.07:59:30.16/wx/25.72,1009.1,90 2006.189.07:59:31.08/fmout-gps/S +2.97E-07 2006.189.07:59:31.08:scan_name=189-0800,k06189,60 2006.189.07:59:31.09:source=oj287,085448.87,200630.6,2000.0,ccw 2006.189.07:59:31.14#flagr#flagr/antenna,new-source 2006.189.07:59:32.14:checkk5 2006.189.07:59:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.189.07:59:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.189.07:59:33.30/chk_autoobs//k5ts3/ autoobs is running! 2006.189.07:59:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.189.07:59:34.04/chk_obsdata//k5ts1/T1890758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:59:34.42/chk_obsdata//k5ts2/T1890758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:59:34.80/chk_obsdata//k5ts3/T1890758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:59:35.17/chk_obsdata//k5ts4/T1890758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.07:59:35.87/k5log//k5ts1_log_newline 2006.189.07:59:36.57/k5log//k5ts2_log_newline 2006.189.07:59:37.27/k5log//k5ts3_log_newline 2006.189.07:59:37.96/k5log//k5ts4_log_newline 2006.189.07:59:37.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.07:59:37.98:4f8m12a=2 2006.189.07:59:37.98$4f8m12a/echo=on 2006.189.07:59:37.98$4f8m12a/pcalon 2006.189.07:59:37.98$pcalon/"no phase cal control is implemented here 2006.189.07:59:37.98$4f8m12a/"tpicd=stop 2006.189.07:59:37.98$4f8m12a/vc4f8 2006.189.07:59:37.98$vc4f8/valo=1,532.99 2006.189.07:59:37.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:59:37.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:59:37.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:37.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:37.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:37.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:37.99#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:59:37.99#ibcon#first serial, iclass 4, count 0 2006.189.07:59:37.99#ibcon#enter sib2, iclass 4, count 0 2006.189.07:59:37.99#ibcon#flushed, iclass 4, count 0 2006.189.07:59:37.99#ibcon#about to write, iclass 4, count 0 2006.189.07:59:37.99#ibcon#wrote, iclass 4, count 0 2006.189.07:59:37.99#ibcon#about to read 3, iclass 4, count 0 2006.189.07:59:38.04#ibcon#read 3, iclass 4, count 0 2006.189.07:59:38.04#ibcon#about to read 4, iclass 4, count 0 2006.189.07:59:38.04#ibcon#read 4, iclass 4, count 0 2006.189.07:59:38.04#ibcon#about to read 5, iclass 4, count 0 2006.189.07:59:38.04#ibcon#read 5, iclass 4, count 0 2006.189.07:59:38.04#ibcon#about to read 6, iclass 4, count 0 2006.189.07:59:38.04#ibcon#read 6, iclass 4, count 0 2006.189.07:59:38.04#ibcon#end of sib2, iclass 4, count 0 2006.189.07:59:38.04#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:59:38.04#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:59:38.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.07:59:38.04#ibcon#*before write, iclass 4, count 0 2006.189.07:59:38.04#ibcon#enter sib2, iclass 4, count 0 2006.189.07:59:38.04#ibcon#flushed, iclass 4, count 0 2006.189.07:59:38.04#ibcon#about to write, iclass 4, count 0 2006.189.07:59:38.04#ibcon#wrote, iclass 4, count 0 2006.189.07:59:38.04#ibcon#about to read 3, iclass 4, count 0 2006.189.07:59:38.09#ibcon#read 3, iclass 4, count 0 2006.189.07:59:38.09#ibcon#about to read 4, iclass 4, count 0 2006.189.07:59:38.09#ibcon#read 4, iclass 4, count 0 2006.189.07:59:38.09#ibcon#about to read 5, iclass 4, count 0 2006.189.07:59:38.09#ibcon#read 5, iclass 4, count 0 2006.189.07:59:38.09#ibcon#about to read 6, iclass 4, count 0 2006.189.07:59:38.09#ibcon#read 6, iclass 4, count 0 2006.189.07:59:38.09#ibcon#end of sib2, iclass 4, count 0 2006.189.07:59:38.09#ibcon#*after write, iclass 4, count 0 2006.189.07:59:38.09#ibcon#*before return 0, iclass 4, count 0 2006.189.07:59:38.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:38.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:38.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:59:38.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:59:38.09$vc4f8/va=1,8 2006.189.07:59:38.09#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.07:59:38.09#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.07:59:38.09#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:38.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:38.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:38.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:38.09#ibcon#enter wrdev, iclass 6, count 2 2006.189.07:59:38.09#ibcon#first serial, iclass 6, count 2 2006.189.07:59:38.09#ibcon#enter sib2, iclass 6, count 2 2006.189.07:59:38.09#ibcon#flushed, iclass 6, count 2 2006.189.07:59:38.09#ibcon#about to write, iclass 6, count 2 2006.189.07:59:38.09#ibcon#wrote, iclass 6, count 2 2006.189.07:59:38.09#ibcon#about to read 3, iclass 6, count 2 2006.189.07:59:38.11#ibcon#read 3, iclass 6, count 2 2006.189.07:59:38.11#ibcon#about to read 4, iclass 6, count 2 2006.189.07:59:38.11#ibcon#read 4, iclass 6, count 2 2006.189.07:59:38.11#ibcon#about to read 5, iclass 6, count 2 2006.189.07:59:38.11#ibcon#read 5, iclass 6, count 2 2006.189.07:59:38.11#ibcon#about to read 6, iclass 6, count 2 2006.189.07:59:38.11#ibcon#read 6, iclass 6, count 2 2006.189.07:59:38.11#ibcon#end of sib2, iclass 6, count 2 2006.189.07:59:38.11#ibcon#*mode == 0, iclass 6, count 2 2006.189.07:59:38.11#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.07:59:38.11#ibcon#[25=AT01-08\r\n] 2006.189.07:59:38.11#ibcon#*before write, iclass 6, count 2 2006.189.07:59:38.11#ibcon#enter sib2, iclass 6, count 2 2006.189.07:59:38.11#ibcon#flushed, iclass 6, count 2 2006.189.07:59:38.11#ibcon#about to write, iclass 6, count 2 2006.189.07:59:38.11#ibcon#wrote, iclass 6, count 2 2006.189.07:59:38.11#ibcon#about to read 3, iclass 6, count 2 2006.189.07:59:38.14#ibcon#read 3, iclass 6, count 2 2006.189.07:59:38.14#ibcon#about to read 4, iclass 6, count 2 2006.189.07:59:38.14#ibcon#read 4, iclass 6, count 2 2006.189.07:59:38.14#ibcon#about to read 5, iclass 6, count 2 2006.189.07:59:38.14#ibcon#read 5, iclass 6, count 2 2006.189.07:59:38.14#ibcon#about to read 6, iclass 6, count 2 2006.189.07:59:38.14#ibcon#read 6, iclass 6, count 2 2006.189.07:59:38.14#ibcon#end of sib2, iclass 6, count 2 2006.189.07:59:38.14#ibcon#*after write, iclass 6, count 2 2006.189.07:59:38.14#ibcon#*before return 0, iclass 6, count 2 2006.189.07:59:38.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:38.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:38.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.07:59:38.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:38.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:38.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:38.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:38.26#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:59:38.26#ibcon#first serial, iclass 6, count 0 2006.189.07:59:38.26#ibcon#enter sib2, iclass 6, count 0 2006.189.07:59:38.26#ibcon#flushed, iclass 6, count 0 2006.189.07:59:38.26#ibcon#about to write, iclass 6, count 0 2006.189.07:59:38.26#ibcon#wrote, iclass 6, count 0 2006.189.07:59:38.26#ibcon#about to read 3, iclass 6, count 0 2006.189.07:59:38.28#ibcon#read 3, iclass 6, count 0 2006.189.07:59:38.28#ibcon#about to read 4, iclass 6, count 0 2006.189.07:59:38.28#ibcon#read 4, iclass 6, count 0 2006.189.07:59:38.28#ibcon#about to read 5, iclass 6, count 0 2006.189.07:59:38.28#ibcon#read 5, iclass 6, count 0 2006.189.07:59:38.28#ibcon#about to read 6, iclass 6, count 0 2006.189.07:59:38.28#ibcon#read 6, iclass 6, count 0 2006.189.07:59:38.28#ibcon#end of sib2, iclass 6, count 0 2006.189.07:59:38.28#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:59:38.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:59:38.28#ibcon#[25=USB\r\n] 2006.189.07:59:38.28#ibcon#*before write, iclass 6, count 0 2006.189.07:59:38.28#ibcon#enter sib2, iclass 6, count 0 2006.189.07:59:38.28#ibcon#flushed, iclass 6, count 0 2006.189.07:59:38.28#ibcon#about to write, iclass 6, count 0 2006.189.07:59:38.28#ibcon#wrote, iclass 6, count 0 2006.189.07:59:38.28#ibcon#about to read 3, iclass 6, count 0 2006.189.07:59:38.31#ibcon#read 3, iclass 6, count 0 2006.189.07:59:38.31#ibcon#about to read 4, iclass 6, count 0 2006.189.07:59:38.31#ibcon#read 4, iclass 6, count 0 2006.189.07:59:38.31#ibcon#about to read 5, iclass 6, count 0 2006.189.07:59:38.31#ibcon#read 5, iclass 6, count 0 2006.189.07:59:38.31#ibcon#about to read 6, iclass 6, count 0 2006.189.07:59:38.31#ibcon#read 6, iclass 6, count 0 2006.189.07:59:38.31#ibcon#end of sib2, iclass 6, count 0 2006.189.07:59:38.31#ibcon#*after write, iclass 6, count 0 2006.189.07:59:38.31#ibcon#*before return 0, iclass 6, count 0 2006.189.07:59:38.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:38.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:38.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:59:38.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:59:38.31$vc4f8/valo=2,572.99 2006.189.07:59:38.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.07:59:38.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.07:59:38.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:38.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:38.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:38.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:38.31#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:59:38.31#ibcon#first serial, iclass 10, count 0 2006.189.07:59:38.31#ibcon#enter sib2, iclass 10, count 0 2006.189.07:59:38.31#ibcon#flushed, iclass 10, count 0 2006.189.07:59:38.31#ibcon#about to write, iclass 10, count 0 2006.189.07:59:38.31#ibcon#wrote, iclass 10, count 0 2006.189.07:59:38.31#ibcon#about to read 3, iclass 10, count 0 2006.189.07:59:38.33#ibcon#read 3, iclass 10, count 0 2006.189.07:59:38.33#ibcon#about to read 4, iclass 10, count 0 2006.189.07:59:38.33#ibcon#read 4, iclass 10, count 0 2006.189.07:59:38.33#ibcon#about to read 5, iclass 10, count 0 2006.189.07:59:38.33#ibcon#read 5, iclass 10, count 0 2006.189.07:59:38.33#ibcon#about to read 6, iclass 10, count 0 2006.189.07:59:38.33#ibcon#read 6, iclass 10, count 0 2006.189.07:59:38.33#ibcon#end of sib2, iclass 10, count 0 2006.189.07:59:38.33#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:59:38.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:59:38.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.07:59:38.33#ibcon#*before write, iclass 10, count 0 2006.189.07:59:38.33#ibcon#enter sib2, iclass 10, count 0 2006.189.07:59:38.33#ibcon#flushed, iclass 10, count 0 2006.189.07:59:38.33#ibcon#about to write, iclass 10, count 0 2006.189.07:59:38.33#ibcon#wrote, iclass 10, count 0 2006.189.07:59:38.33#ibcon#about to read 3, iclass 10, count 0 2006.189.07:59:38.37#ibcon#read 3, iclass 10, count 0 2006.189.07:59:38.37#ibcon#about to read 4, iclass 10, count 0 2006.189.07:59:38.37#ibcon#read 4, iclass 10, count 0 2006.189.07:59:38.37#ibcon#about to read 5, iclass 10, count 0 2006.189.07:59:38.37#ibcon#read 5, iclass 10, count 0 2006.189.07:59:38.37#ibcon#about to read 6, iclass 10, count 0 2006.189.07:59:38.37#ibcon#read 6, iclass 10, count 0 2006.189.07:59:38.37#ibcon#end of sib2, iclass 10, count 0 2006.189.07:59:38.37#ibcon#*after write, iclass 10, count 0 2006.189.07:59:38.37#ibcon#*before return 0, iclass 10, count 0 2006.189.07:59:38.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:38.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:38.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:59:38.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:59:38.37$vc4f8/va=2,7 2006.189.07:59:38.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.07:59:38.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.07:59:38.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:38.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:38.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:38.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:38.43#ibcon#enter wrdev, iclass 12, count 2 2006.189.07:59:38.43#ibcon#first serial, iclass 12, count 2 2006.189.07:59:38.43#ibcon#enter sib2, iclass 12, count 2 2006.189.07:59:38.43#ibcon#flushed, iclass 12, count 2 2006.189.07:59:38.43#ibcon#about to write, iclass 12, count 2 2006.189.07:59:38.43#ibcon#wrote, iclass 12, count 2 2006.189.07:59:38.43#ibcon#about to read 3, iclass 12, count 2 2006.189.07:59:38.45#ibcon#read 3, iclass 12, count 2 2006.189.07:59:38.45#ibcon#about to read 4, iclass 12, count 2 2006.189.07:59:38.45#ibcon#read 4, iclass 12, count 2 2006.189.07:59:38.45#ibcon#about to read 5, iclass 12, count 2 2006.189.07:59:38.45#ibcon#read 5, iclass 12, count 2 2006.189.07:59:38.45#ibcon#about to read 6, iclass 12, count 2 2006.189.07:59:38.45#ibcon#read 6, iclass 12, count 2 2006.189.07:59:38.45#ibcon#end of sib2, iclass 12, count 2 2006.189.07:59:38.45#ibcon#*mode == 0, iclass 12, count 2 2006.189.07:59:38.45#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.07:59:38.45#ibcon#[25=AT02-07\r\n] 2006.189.07:59:38.45#ibcon#*before write, iclass 12, count 2 2006.189.07:59:38.45#ibcon#enter sib2, iclass 12, count 2 2006.189.07:59:38.45#ibcon#flushed, iclass 12, count 2 2006.189.07:59:38.45#ibcon#about to write, iclass 12, count 2 2006.189.07:59:38.45#ibcon#wrote, iclass 12, count 2 2006.189.07:59:38.45#ibcon#about to read 3, iclass 12, count 2 2006.189.07:59:38.48#ibcon#read 3, iclass 12, count 2 2006.189.07:59:38.48#ibcon#about to read 4, iclass 12, count 2 2006.189.07:59:38.48#ibcon#read 4, iclass 12, count 2 2006.189.07:59:38.48#ibcon#about to read 5, iclass 12, count 2 2006.189.07:59:38.48#ibcon#read 5, iclass 12, count 2 2006.189.07:59:38.48#ibcon#about to read 6, iclass 12, count 2 2006.189.07:59:38.48#ibcon#read 6, iclass 12, count 2 2006.189.07:59:38.48#ibcon#end of sib2, iclass 12, count 2 2006.189.07:59:38.48#ibcon#*after write, iclass 12, count 2 2006.189.07:59:38.48#ibcon#*before return 0, iclass 12, count 2 2006.189.07:59:38.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:38.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:38.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.07:59:38.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:38.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:38.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:38.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:38.60#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:59:38.60#ibcon#first serial, iclass 12, count 0 2006.189.07:59:38.60#ibcon#enter sib2, iclass 12, count 0 2006.189.07:59:38.60#ibcon#flushed, iclass 12, count 0 2006.189.07:59:38.60#ibcon#about to write, iclass 12, count 0 2006.189.07:59:38.60#ibcon#wrote, iclass 12, count 0 2006.189.07:59:38.60#ibcon#about to read 3, iclass 12, count 0 2006.189.07:59:38.62#ibcon#read 3, iclass 12, count 0 2006.189.07:59:38.62#ibcon#about to read 4, iclass 12, count 0 2006.189.07:59:38.62#ibcon#read 4, iclass 12, count 0 2006.189.07:59:38.62#ibcon#about to read 5, iclass 12, count 0 2006.189.07:59:38.62#ibcon#read 5, iclass 12, count 0 2006.189.07:59:38.62#ibcon#about to read 6, iclass 12, count 0 2006.189.07:59:38.62#ibcon#read 6, iclass 12, count 0 2006.189.07:59:38.62#ibcon#end of sib2, iclass 12, count 0 2006.189.07:59:38.62#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:59:38.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:59:38.62#ibcon#[25=USB\r\n] 2006.189.07:59:38.62#ibcon#*before write, iclass 12, count 0 2006.189.07:59:38.62#ibcon#enter sib2, iclass 12, count 0 2006.189.07:59:38.62#ibcon#flushed, iclass 12, count 0 2006.189.07:59:38.62#ibcon#about to write, iclass 12, count 0 2006.189.07:59:38.62#ibcon#wrote, iclass 12, count 0 2006.189.07:59:38.62#ibcon#about to read 3, iclass 12, count 0 2006.189.07:59:38.63#abcon#<5=/04 4.1 7.7 25.72 901009.1\r\n> 2006.189.07:59:38.65#abcon#{5=INTERFACE CLEAR} 2006.189.07:59:38.65#ibcon#read 3, iclass 12, count 0 2006.189.07:59:38.65#ibcon#about to read 4, iclass 12, count 0 2006.189.07:59:38.65#ibcon#read 4, iclass 12, count 0 2006.189.07:59:38.65#ibcon#about to read 5, iclass 12, count 0 2006.189.07:59:38.65#ibcon#read 5, iclass 12, count 0 2006.189.07:59:38.65#ibcon#about to read 6, iclass 12, count 0 2006.189.07:59:38.65#ibcon#read 6, iclass 12, count 0 2006.189.07:59:38.65#ibcon#end of sib2, iclass 12, count 0 2006.189.07:59:38.65#ibcon#*after write, iclass 12, count 0 2006.189.07:59:38.65#ibcon#*before return 0, iclass 12, count 0 2006.189.07:59:38.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:38.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:38.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:59:38.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:59:38.65$vc4f8/valo=3,672.99 2006.189.07:59:38.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.07:59:38.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.07:59:38.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:38.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:59:38.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:59:38.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:59:38.65#ibcon#enter wrdev, iclass 17, count 0 2006.189.07:59:38.65#ibcon#first serial, iclass 17, count 0 2006.189.07:59:38.65#ibcon#enter sib2, iclass 17, count 0 2006.189.07:59:38.65#ibcon#flushed, iclass 17, count 0 2006.189.07:59:38.65#ibcon#about to write, iclass 17, count 0 2006.189.07:59:38.65#ibcon#wrote, iclass 17, count 0 2006.189.07:59:38.65#ibcon#about to read 3, iclass 17, count 0 2006.189.07:59:38.67#ibcon#read 3, iclass 17, count 0 2006.189.07:59:38.67#ibcon#about to read 4, iclass 17, count 0 2006.189.07:59:38.67#ibcon#read 4, iclass 17, count 0 2006.189.07:59:38.67#ibcon#about to read 5, iclass 17, count 0 2006.189.07:59:38.67#ibcon#read 5, iclass 17, count 0 2006.189.07:59:38.67#ibcon#about to read 6, iclass 17, count 0 2006.189.07:59:38.67#ibcon#read 6, iclass 17, count 0 2006.189.07:59:38.67#ibcon#end of sib2, iclass 17, count 0 2006.189.07:59:38.67#ibcon#*mode == 0, iclass 17, count 0 2006.189.07:59:38.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.07:59:38.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.07:59:38.67#ibcon#*before write, iclass 17, count 0 2006.189.07:59:38.67#ibcon#enter sib2, iclass 17, count 0 2006.189.07:59:38.67#ibcon#flushed, iclass 17, count 0 2006.189.07:59:38.67#ibcon#about to write, iclass 17, count 0 2006.189.07:59:38.67#ibcon#wrote, iclass 17, count 0 2006.189.07:59:38.67#ibcon#about to read 3, iclass 17, count 0 2006.189.07:59:38.71#abcon#[5=S1D000X0/0*\r\n] 2006.189.07:59:38.71#ibcon#read 3, iclass 17, count 0 2006.189.07:59:38.71#ibcon#about to read 4, iclass 17, count 0 2006.189.07:59:38.71#ibcon#read 4, iclass 17, count 0 2006.189.07:59:38.71#ibcon#about to read 5, iclass 17, count 0 2006.189.07:59:38.71#ibcon#read 5, iclass 17, count 0 2006.189.07:59:38.71#ibcon#about to read 6, iclass 17, count 0 2006.189.07:59:38.71#ibcon#read 6, iclass 17, count 0 2006.189.07:59:38.71#ibcon#end of sib2, iclass 17, count 0 2006.189.07:59:38.71#ibcon#*after write, iclass 17, count 0 2006.189.07:59:38.71#ibcon#*before return 0, iclass 17, count 0 2006.189.07:59:38.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:59:38.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.07:59:38.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.07:59:38.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.07:59:38.71$vc4f8/va=3,6 2006.189.07:59:38.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:59:38.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:59:38.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:38.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:38.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:38.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:38.77#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:59:38.77#ibcon#first serial, iclass 20, count 2 2006.189.07:59:38.77#ibcon#enter sib2, iclass 20, count 2 2006.189.07:59:38.77#ibcon#flushed, iclass 20, count 2 2006.189.07:59:38.77#ibcon#about to write, iclass 20, count 2 2006.189.07:59:38.77#ibcon#wrote, iclass 20, count 2 2006.189.07:59:38.77#ibcon#about to read 3, iclass 20, count 2 2006.189.07:59:38.79#ibcon#read 3, iclass 20, count 2 2006.189.07:59:38.79#ibcon#about to read 4, iclass 20, count 2 2006.189.07:59:38.79#ibcon#read 4, iclass 20, count 2 2006.189.07:59:38.79#ibcon#about to read 5, iclass 20, count 2 2006.189.07:59:38.79#ibcon#read 5, iclass 20, count 2 2006.189.07:59:38.79#ibcon#about to read 6, iclass 20, count 2 2006.189.07:59:38.79#ibcon#read 6, iclass 20, count 2 2006.189.07:59:38.79#ibcon#end of sib2, iclass 20, count 2 2006.189.07:59:38.79#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:59:38.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:59:38.79#ibcon#[25=AT03-06\r\n] 2006.189.07:59:38.79#ibcon#*before write, iclass 20, count 2 2006.189.07:59:38.79#ibcon#enter sib2, iclass 20, count 2 2006.189.07:59:38.79#ibcon#flushed, iclass 20, count 2 2006.189.07:59:38.79#ibcon#about to write, iclass 20, count 2 2006.189.07:59:38.79#ibcon#wrote, iclass 20, count 2 2006.189.07:59:38.79#ibcon#about to read 3, iclass 20, count 2 2006.189.07:59:38.82#ibcon#read 3, iclass 20, count 2 2006.189.07:59:38.82#ibcon#about to read 4, iclass 20, count 2 2006.189.07:59:38.82#ibcon#read 4, iclass 20, count 2 2006.189.07:59:38.82#ibcon#about to read 5, iclass 20, count 2 2006.189.07:59:38.82#ibcon#read 5, iclass 20, count 2 2006.189.07:59:38.82#ibcon#about to read 6, iclass 20, count 2 2006.189.07:59:38.82#ibcon#read 6, iclass 20, count 2 2006.189.07:59:38.82#ibcon#end of sib2, iclass 20, count 2 2006.189.07:59:38.82#ibcon#*after write, iclass 20, count 2 2006.189.07:59:38.82#ibcon#*before return 0, iclass 20, count 2 2006.189.07:59:38.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:38.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:38.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:59:38.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:38.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:38.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:38.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:38.94#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:59:38.94#ibcon#first serial, iclass 20, count 0 2006.189.07:59:38.94#ibcon#enter sib2, iclass 20, count 0 2006.189.07:59:38.94#ibcon#flushed, iclass 20, count 0 2006.189.07:59:38.94#ibcon#about to write, iclass 20, count 0 2006.189.07:59:38.94#ibcon#wrote, iclass 20, count 0 2006.189.07:59:38.94#ibcon#about to read 3, iclass 20, count 0 2006.189.07:59:38.96#ibcon#read 3, iclass 20, count 0 2006.189.07:59:38.96#ibcon#about to read 4, iclass 20, count 0 2006.189.07:59:38.96#ibcon#read 4, iclass 20, count 0 2006.189.07:59:38.96#ibcon#about to read 5, iclass 20, count 0 2006.189.07:59:38.96#ibcon#read 5, iclass 20, count 0 2006.189.07:59:38.96#ibcon#about to read 6, iclass 20, count 0 2006.189.07:59:38.96#ibcon#read 6, iclass 20, count 0 2006.189.07:59:38.96#ibcon#end of sib2, iclass 20, count 0 2006.189.07:59:38.96#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:59:38.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:59:38.96#ibcon#[25=USB\r\n] 2006.189.07:59:38.96#ibcon#*before write, iclass 20, count 0 2006.189.07:59:38.96#ibcon#enter sib2, iclass 20, count 0 2006.189.07:59:38.96#ibcon#flushed, iclass 20, count 0 2006.189.07:59:38.96#ibcon#about to write, iclass 20, count 0 2006.189.07:59:38.96#ibcon#wrote, iclass 20, count 0 2006.189.07:59:38.96#ibcon#about to read 3, iclass 20, count 0 2006.189.07:59:38.99#ibcon#read 3, iclass 20, count 0 2006.189.07:59:38.99#ibcon#about to read 4, iclass 20, count 0 2006.189.07:59:38.99#ibcon#read 4, iclass 20, count 0 2006.189.07:59:38.99#ibcon#about to read 5, iclass 20, count 0 2006.189.07:59:38.99#ibcon#read 5, iclass 20, count 0 2006.189.07:59:38.99#ibcon#about to read 6, iclass 20, count 0 2006.189.07:59:38.99#ibcon#read 6, iclass 20, count 0 2006.189.07:59:38.99#ibcon#end of sib2, iclass 20, count 0 2006.189.07:59:38.99#ibcon#*after write, iclass 20, count 0 2006.189.07:59:38.99#ibcon#*before return 0, iclass 20, count 0 2006.189.07:59:38.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:38.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:38.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:59:38.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:59:38.99$vc4f8/valo=4,832.99 2006.189.07:59:38.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:59:38.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:59:38.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:38.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:38.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:38.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:38.99#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:59:38.99#ibcon#first serial, iclass 22, count 0 2006.189.07:59:38.99#ibcon#enter sib2, iclass 22, count 0 2006.189.07:59:38.99#ibcon#flushed, iclass 22, count 0 2006.189.07:59:38.99#ibcon#about to write, iclass 22, count 0 2006.189.07:59:38.99#ibcon#wrote, iclass 22, count 0 2006.189.07:59:38.99#ibcon#about to read 3, iclass 22, count 0 2006.189.07:59:39.01#ibcon#read 3, iclass 22, count 0 2006.189.07:59:39.01#ibcon#about to read 4, iclass 22, count 0 2006.189.07:59:39.01#ibcon#read 4, iclass 22, count 0 2006.189.07:59:39.01#ibcon#about to read 5, iclass 22, count 0 2006.189.07:59:39.01#ibcon#read 5, iclass 22, count 0 2006.189.07:59:39.01#ibcon#about to read 6, iclass 22, count 0 2006.189.07:59:39.01#ibcon#read 6, iclass 22, count 0 2006.189.07:59:39.01#ibcon#end of sib2, iclass 22, count 0 2006.189.07:59:39.01#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:59:39.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:59:39.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.07:59:39.01#ibcon#*before write, iclass 22, count 0 2006.189.07:59:39.01#ibcon#enter sib2, iclass 22, count 0 2006.189.07:59:39.01#ibcon#flushed, iclass 22, count 0 2006.189.07:59:39.01#ibcon#about to write, iclass 22, count 0 2006.189.07:59:39.01#ibcon#wrote, iclass 22, count 0 2006.189.07:59:39.01#ibcon#about to read 3, iclass 22, count 0 2006.189.07:59:39.05#ibcon#read 3, iclass 22, count 0 2006.189.07:59:39.05#ibcon#about to read 4, iclass 22, count 0 2006.189.07:59:39.05#ibcon#read 4, iclass 22, count 0 2006.189.07:59:39.05#ibcon#about to read 5, iclass 22, count 0 2006.189.07:59:39.05#ibcon#read 5, iclass 22, count 0 2006.189.07:59:39.05#ibcon#about to read 6, iclass 22, count 0 2006.189.07:59:39.05#ibcon#read 6, iclass 22, count 0 2006.189.07:59:39.05#ibcon#end of sib2, iclass 22, count 0 2006.189.07:59:39.05#ibcon#*after write, iclass 22, count 0 2006.189.07:59:39.05#ibcon#*before return 0, iclass 22, count 0 2006.189.07:59:39.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:39.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:39.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:59:39.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:59:39.05$vc4f8/va=4,7 2006.189.07:59:39.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:59:39.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:59:39.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:39.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:39.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:39.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:39.11#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:59:39.11#ibcon#first serial, iclass 24, count 2 2006.189.07:59:39.11#ibcon#enter sib2, iclass 24, count 2 2006.189.07:59:39.11#ibcon#flushed, iclass 24, count 2 2006.189.07:59:39.11#ibcon#about to write, iclass 24, count 2 2006.189.07:59:39.11#ibcon#wrote, iclass 24, count 2 2006.189.07:59:39.11#ibcon#about to read 3, iclass 24, count 2 2006.189.07:59:39.13#ibcon#read 3, iclass 24, count 2 2006.189.07:59:39.13#ibcon#about to read 4, iclass 24, count 2 2006.189.07:59:39.13#ibcon#read 4, iclass 24, count 2 2006.189.07:59:39.13#ibcon#about to read 5, iclass 24, count 2 2006.189.07:59:39.13#ibcon#read 5, iclass 24, count 2 2006.189.07:59:39.13#ibcon#about to read 6, iclass 24, count 2 2006.189.07:59:39.13#ibcon#read 6, iclass 24, count 2 2006.189.07:59:39.13#ibcon#end of sib2, iclass 24, count 2 2006.189.07:59:39.13#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:59:39.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:59:39.13#ibcon#[25=AT04-07\r\n] 2006.189.07:59:39.13#ibcon#*before write, iclass 24, count 2 2006.189.07:59:39.13#ibcon#enter sib2, iclass 24, count 2 2006.189.07:59:39.13#ibcon#flushed, iclass 24, count 2 2006.189.07:59:39.13#ibcon#about to write, iclass 24, count 2 2006.189.07:59:39.13#ibcon#wrote, iclass 24, count 2 2006.189.07:59:39.13#ibcon#about to read 3, iclass 24, count 2 2006.189.07:59:39.16#ibcon#read 3, iclass 24, count 2 2006.189.07:59:39.16#ibcon#about to read 4, iclass 24, count 2 2006.189.07:59:39.16#ibcon#read 4, iclass 24, count 2 2006.189.07:59:39.16#ibcon#about to read 5, iclass 24, count 2 2006.189.07:59:39.16#ibcon#read 5, iclass 24, count 2 2006.189.07:59:39.16#ibcon#about to read 6, iclass 24, count 2 2006.189.07:59:39.16#ibcon#read 6, iclass 24, count 2 2006.189.07:59:39.16#ibcon#end of sib2, iclass 24, count 2 2006.189.07:59:39.16#ibcon#*after write, iclass 24, count 2 2006.189.07:59:39.16#ibcon#*before return 0, iclass 24, count 2 2006.189.07:59:39.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:39.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:39.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:59:39.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:39.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:39.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:39.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:39.28#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:59:39.28#ibcon#first serial, iclass 24, count 0 2006.189.07:59:39.28#ibcon#enter sib2, iclass 24, count 0 2006.189.07:59:39.28#ibcon#flushed, iclass 24, count 0 2006.189.07:59:39.28#ibcon#about to write, iclass 24, count 0 2006.189.07:59:39.28#ibcon#wrote, iclass 24, count 0 2006.189.07:59:39.28#ibcon#about to read 3, iclass 24, count 0 2006.189.07:59:39.30#ibcon#read 3, iclass 24, count 0 2006.189.07:59:39.30#ibcon#about to read 4, iclass 24, count 0 2006.189.07:59:39.30#ibcon#read 4, iclass 24, count 0 2006.189.07:59:39.30#ibcon#about to read 5, iclass 24, count 0 2006.189.07:59:39.30#ibcon#read 5, iclass 24, count 0 2006.189.07:59:39.30#ibcon#about to read 6, iclass 24, count 0 2006.189.07:59:39.30#ibcon#read 6, iclass 24, count 0 2006.189.07:59:39.30#ibcon#end of sib2, iclass 24, count 0 2006.189.07:59:39.30#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:59:39.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:59:39.30#ibcon#[25=USB\r\n] 2006.189.07:59:39.30#ibcon#*before write, iclass 24, count 0 2006.189.07:59:39.30#ibcon#enter sib2, iclass 24, count 0 2006.189.07:59:39.30#ibcon#flushed, iclass 24, count 0 2006.189.07:59:39.30#ibcon#about to write, iclass 24, count 0 2006.189.07:59:39.30#ibcon#wrote, iclass 24, count 0 2006.189.07:59:39.30#ibcon#about to read 3, iclass 24, count 0 2006.189.07:59:39.33#ibcon#read 3, iclass 24, count 0 2006.189.07:59:39.33#ibcon#about to read 4, iclass 24, count 0 2006.189.07:59:39.33#ibcon#read 4, iclass 24, count 0 2006.189.07:59:39.33#ibcon#about to read 5, iclass 24, count 0 2006.189.07:59:39.33#ibcon#read 5, iclass 24, count 0 2006.189.07:59:39.33#ibcon#about to read 6, iclass 24, count 0 2006.189.07:59:39.33#ibcon#read 6, iclass 24, count 0 2006.189.07:59:39.33#ibcon#end of sib2, iclass 24, count 0 2006.189.07:59:39.33#ibcon#*after write, iclass 24, count 0 2006.189.07:59:39.33#ibcon#*before return 0, iclass 24, count 0 2006.189.07:59:39.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:39.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:39.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:59:39.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:59:39.33$vc4f8/valo=5,652.99 2006.189.07:59:39.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.07:59:39.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.07:59:39.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:39.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:39.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:39.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:39.33#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:59:39.33#ibcon#first serial, iclass 26, count 0 2006.189.07:59:39.33#ibcon#enter sib2, iclass 26, count 0 2006.189.07:59:39.33#ibcon#flushed, iclass 26, count 0 2006.189.07:59:39.33#ibcon#about to write, iclass 26, count 0 2006.189.07:59:39.33#ibcon#wrote, iclass 26, count 0 2006.189.07:59:39.33#ibcon#about to read 3, iclass 26, count 0 2006.189.07:59:39.35#ibcon#read 3, iclass 26, count 0 2006.189.07:59:39.35#ibcon#about to read 4, iclass 26, count 0 2006.189.07:59:39.35#ibcon#read 4, iclass 26, count 0 2006.189.07:59:39.35#ibcon#about to read 5, iclass 26, count 0 2006.189.07:59:39.35#ibcon#read 5, iclass 26, count 0 2006.189.07:59:39.35#ibcon#about to read 6, iclass 26, count 0 2006.189.07:59:39.35#ibcon#read 6, iclass 26, count 0 2006.189.07:59:39.35#ibcon#end of sib2, iclass 26, count 0 2006.189.07:59:39.35#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:59:39.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:59:39.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.07:59:39.35#ibcon#*before write, iclass 26, count 0 2006.189.07:59:39.35#ibcon#enter sib2, iclass 26, count 0 2006.189.07:59:39.35#ibcon#flushed, iclass 26, count 0 2006.189.07:59:39.35#ibcon#about to write, iclass 26, count 0 2006.189.07:59:39.35#ibcon#wrote, iclass 26, count 0 2006.189.07:59:39.35#ibcon#about to read 3, iclass 26, count 0 2006.189.07:59:39.39#ibcon#read 3, iclass 26, count 0 2006.189.07:59:39.39#ibcon#about to read 4, iclass 26, count 0 2006.189.07:59:39.39#ibcon#read 4, iclass 26, count 0 2006.189.07:59:39.39#ibcon#about to read 5, iclass 26, count 0 2006.189.07:59:39.39#ibcon#read 5, iclass 26, count 0 2006.189.07:59:39.39#ibcon#about to read 6, iclass 26, count 0 2006.189.07:59:39.39#ibcon#read 6, iclass 26, count 0 2006.189.07:59:39.39#ibcon#end of sib2, iclass 26, count 0 2006.189.07:59:39.39#ibcon#*after write, iclass 26, count 0 2006.189.07:59:39.39#ibcon#*before return 0, iclass 26, count 0 2006.189.07:59:39.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:39.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:39.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:59:39.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:59:39.39$vc4f8/va=5,7 2006.189.07:59:39.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.07:59:39.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.07:59:39.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:39.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:39.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:39.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:39.45#ibcon#enter wrdev, iclass 28, count 2 2006.189.07:59:39.45#ibcon#first serial, iclass 28, count 2 2006.189.07:59:39.45#ibcon#enter sib2, iclass 28, count 2 2006.189.07:59:39.45#ibcon#flushed, iclass 28, count 2 2006.189.07:59:39.45#ibcon#about to write, iclass 28, count 2 2006.189.07:59:39.45#ibcon#wrote, iclass 28, count 2 2006.189.07:59:39.45#ibcon#about to read 3, iclass 28, count 2 2006.189.07:59:39.47#ibcon#read 3, iclass 28, count 2 2006.189.07:59:39.47#ibcon#about to read 4, iclass 28, count 2 2006.189.07:59:39.47#ibcon#read 4, iclass 28, count 2 2006.189.07:59:39.47#ibcon#about to read 5, iclass 28, count 2 2006.189.07:59:39.47#ibcon#read 5, iclass 28, count 2 2006.189.07:59:39.47#ibcon#about to read 6, iclass 28, count 2 2006.189.07:59:39.47#ibcon#read 6, iclass 28, count 2 2006.189.07:59:39.47#ibcon#end of sib2, iclass 28, count 2 2006.189.07:59:39.47#ibcon#*mode == 0, iclass 28, count 2 2006.189.07:59:39.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.07:59:39.47#ibcon#[25=AT05-07\r\n] 2006.189.07:59:39.47#ibcon#*before write, iclass 28, count 2 2006.189.07:59:39.47#ibcon#enter sib2, iclass 28, count 2 2006.189.07:59:39.47#ibcon#flushed, iclass 28, count 2 2006.189.07:59:39.47#ibcon#about to write, iclass 28, count 2 2006.189.07:59:39.47#ibcon#wrote, iclass 28, count 2 2006.189.07:59:39.47#ibcon#about to read 3, iclass 28, count 2 2006.189.07:59:39.50#ibcon#read 3, iclass 28, count 2 2006.189.07:59:39.50#ibcon#about to read 4, iclass 28, count 2 2006.189.07:59:39.50#ibcon#read 4, iclass 28, count 2 2006.189.07:59:39.50#ibcon#about to read 5, iclass 28, count 2 2006.189.07:59:39.50#ibcon#read 5, iclass 28, count 2 2006.189.07:59:39.50#ibcon#about to read 6, iclass 28, count 2 2006.189.07:59:39.50#ibcon#read 6, iclass 28, count 2 2006.189.07:59:39.50#ibcon#end of sib2, iclass 28, count 2 2006.189.07:59:39.50#ibcon#*after write, iclass 28, count 2 2006.189.07:59:39.50#ibcon#*before return 0, iclass 28, count 2 2006.189.07:59:39.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:39.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:39.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.07:59:39.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:39.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:39.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:39.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:39.62#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:59:39.62#ibcon#first serial, iclass 28, count 0 2006.189.07:59:39.62#ibcon#enter sib2, iclass 28, count 0 2006.189.07:59:39.62#ibcon#flushed, iclass 28, count 0 2006.189.07:59:39.62#ibcon#about to write, iclass 28, count 0 2006.189.07:59:39.62#ibcon#wrote, iclass 28, count 0 2006.189.07:59:39.62#ibcon#about to read 3, iclass 28, count 0 2006.189.07:59:39.64#ibcon#read 3, iclass 28, count 0 2006.189.07:59:39.64#ibcon#about to read 4, iclass 28, count 0 2006.189.07:59:39.64#ibcon#read 4, iclass 28, count 0 2006.189.07:59:39.64#ibcon#about to read 5, iclass 28, count 0 2006.189.07:59:39.64#ibcon#read 5, iclass 28, count 0 2006.189.07:59:39.64#ibcon#about to read 6, iclass 28, count 0 2006.189.07:59:39.64#ibcon#read 6, iclass 28, count 0 2006.189.07:59:39.64#ibcon#end of sib2, iclass 28, count 0 2006.189.07:59:39.64#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:59:39.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:59:39.64#ibcon#[25=USB\r\n] 2006.189.07:59:39.64#ibcon#*before write, iclass 28, count 0 2006.189.07:59:39.64#ibcon#enter sib2, iclass 28, count 0 2006.189.07:59:39.64#ibcon#flushed, iclass 28, count 0 2006.189.07:59:39.64#ibcon#about to write, iclass 28, count 0 2006.189.07:59:39.64#ibcon#wrote, iclass 28, count 0 2006.189.07:59:39.64#ibcon#about to read 3, iclass 28, count 0 2006.189.07:59:39.67#ibcon#read 3, iclass 28, count 0 2006.189.07:59:39.67#ibcon#about to read 4, iclass 28, count 0 2006.189.07:59:39.67#ibcon#read 4, iclass 28, count 0 2006.189.07:59:39.67#ibcon#about to read 5, iclass 28, count 0 2006.189.07:59:39.67#ibcon#read 5, iclass 28, count 0 2006.189.07:59:39.67#ibcon#about to read 6, iclass 28, count 0 2006.189.07:59:39.67#ibcon#read 6, iclass 28, count 0 2006.189.07:59:39.67#ibcon#end of sib2, iclass 28, count 0 2006.189.07:59:39.67#ibcon#*after write, iclass 28, count 0 2006.189.07:59:39.67#ibcon#*before return 0, iclass 28, count 0 2006.189.07:59:39.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:39.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:39.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:59:39.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:59:39.67$vc4f8/valo=6,772.99 2006.189.07:59:39.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.07:59:39.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.07:59:39.67#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:39.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:39.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:39.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:39.67#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:59:39.67#ibcon#first serial, iclass 30, count 0 2006.189.07:59:39.67#ibcon#enter sib2, iclass 30, count 0 2006.189.07:59:39.67#ibcon#flushed, iclass 30, count 0 2006.189.07:59:39.67#ibcon#about to write, iclass 30, count 0 2006.189.07:59:39.67#ibcon#wrote, iclass 30, count 0 2006.189.07:59:39.67#ibcon#about to read 3, iclass 30, count 0 2006.189.07:59:39.69#ibcon#read 3, iclass 30, count 0 2006.189.07:59:39.69#ibcon#about to read 4, iclass 30, count 0 2006.189.07:59:39.69#ibcon#read 4, iclass 30, count 0 2006.189.07:59:39.69#ibcon#about to read 5, iclass 30, count 0 2006.189.07:59:39.69#ibcon#read 5, iclass 30, count 0 2006.189.07:59:39.69#ibcon#about to read 6, iclass 30, count 0 2006.189.07:59:39.69#ibcon#read 6, iclass 30, count 0 2006.189.07:59:39.69#ibcon#end of sib2, iclass 30, count 0 2006.189.07:59:39.69#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:59:39.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:59:39.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.07:59:39.69#ibcon#*before write, iclass 30, count 0 2006.189.07:59:39.69#ibcon#enter sib2, iclass 30, count 0 2006.189.07:59:39.69#ibcon#flushed, iclass 30, count 0 2006.189.07:59:39.69#ibcon#about to write, iclass 30, count 0 2006.189.07:59:39.69#ibcon#wrote, iclass 30, count 0 2006.189.07:59:39.69#ibcon#about to read 3, iclass 30, count 0 2006.189.07:59:39.73#ibcon#read 3, iclass 30, count 0 2006.189.07:59:39.73#ibcon#about to read 4, iclass 30, count 0 2006.189.07:59:39.73#ibcon#read 4, iclass 30, count 0 2006.189.07:59:39.73#ibcon#about to read 5, iclass 30, count 0 2006.189.07:59:39.73#ibcon#read 5, iclass 30, count 0 2006.189.07:59:39.73#ibcon#about to read 6, iclass 30, count 0 2006.189.07:59:39.73#ibcon#read 6, iclass 30, count 0 2006.189.07:59:39.73#ibcon#end of sib2, iclass 30, count 0 2006.189.07:59:39.73#ibcon#*after write, iclass 30, count 0 2006.189.07:59:39.73#ibcon#*before return 0, iclass 30, count 0 2006.189.07:59:39.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:39.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:39.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:59:39.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:59:39.73$vc4f8/va=6,6 2006.189.07:59:39.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.07:59:39.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.07:59:39.73#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:39.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:59:39.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:59:39.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:59:39.79#ibcon#enter wrdev, iclass 32, count 2 2006.189.07:59:39.79#ibcon#first serial, iclass 32, count 2 2006.189.07:59:39.79#ibcon#enter sib2, iclass 32, count 2 2006.189.07:59:39.79#ibcon#flushed, iclass 32, count 2 2006.189.07:59:39.79#ibcon#about to write, iclass 32, count 2 2006.189.07:59:39.79#ibcon#wrote, iclass 32, count 2 2006.189.07:59:39.79#ibcon#about to read 3, iclass 32, count 2 2006.189.07:59:39.81#ibcon#read 3, iclass 32, count 2 2006.189.07:59:39.81#ibcon#about to read 4, iclass 32, count 2 2006.189.07:59:39.81#ibcon#read 4, iclass 32, count 2 2006.189.07:59:39.81#ibcon#about to read 5, iclass 32, count 2 2006.189.07:59:39.81#ibcon#read 5, iclass 32, count 2 2006.189.07:59:39.81#ibcon#about to read 6, iclass 32, count 2 2006.189.07:59:39.81#ibcon#read 6, iclass 32, count 2 2006.189.07:59:39.81#ibcon#end of sib2, iclass 32, count 2 2006.189.07:59:39.81#ibcon#*mode == 0, iclass 32, count 2 2006.189.07:59:39.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.07:59:39.81#ibcon#[25=AT06-06\r\n] 2006.189.07:59:39.81#ibcon#*before write, iclass 32, count 2 2006.189.07:59:39.81#ibcon#enter sib2, iclass 32, count 2 2006.189.07:59:39.81#ibcon#flushed, iclass 32, count 2 2006.189.07:59:39.81#ibcon#about to write, iclass 32, count 2 2006.189.07:59:39.81#ibcon#wrote, iclass 32, count 2 2006.189.07:59:39.81#ibcon#about to read 3, iclass 32, count 2 2006.189.07:59:39.84#ibcon#read 3, iclass 32, count 2 2006.189.07:59:39.84#ibcon#about to read 4, iclass 32, count 2 2006.189.07:59:39.84#ibcon#read 4, iclass 32, count 2 2006.189.07:59:39.84#ibcon#about to read 5, iclass 32, count 2 2006.189.07:59:39.84#ibcon#read 5, iclass 32, count 2 2006.189.07:59:39.84#ibcon#about to read 6, iclass 32, count 2 2006.189.07:59:39.84#ibcon#read 6, iclass 32, count 2 2006.189.07:59:39.84#ibcon#end of sib2, iclass 32, count 2 2006.189.07:59:39.84#ibcon#*after write, iclass 32, count 2 2006.189.07:59:39.84#ibcon#*before return 0, iclass 32, count 2 2006.189.07:59:39.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:59:39.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.07:59:39.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.07:59:39.84#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:39.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:59:39.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:59:39.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:59:39.96#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:59:39.96#ibcon#first serial, iclass 32, count 0 2006.189.07:59:39.96#ibcon#enter sib2, iclass 32, count 0 2006.189.07:59:39.96#ibcon#flushed, iclass 32, count 0 2006.189.07:59:39.96#ibcon#about to write, iclass 32, count 0 2006.189.07:59:39.96#ibcon#wrote, iclass 32, count 0 2006.189.07:59:39.96#ibcon#about to read 3, iclass 32, count 0 2006.189.07:59:39.98#ibcon#read 3, iclass 32, count 0 2006.189.07:59:39.98#ibcon#about to read 4, iclass 32, count 0 2006.189.07:59:39.98#ibcon#read 4, iclass 32, count 0 2006.189.07:59:39.98#ibcon#about to read 5, iclass 32, count 0 2006.189.07:59:39.98#ibcon#read 5, iclass 32, count 0 2006.189.07:59:39.98#ibcon#about to read 6, iclass 32, count 0 2006.189.07:59:39.98#ibcon#read 6, iclass 32, count 0 2006.189.07:59:39.98#ibcon#end of sib2, iclass 32, count 0 2006.189.07:59:39.98#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:59:39.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:59:39.98#ibcon#[25=USB\r\n] 2006.189.07:59:39.98#ibcon#*before write, iclass 32, count 0 2006.189.07:59:39.98#ibcon#enter sib2, iclass 32, count 0 2006.189.07:59:39.98#ibcon#flushed, iclass 32, count 0 2006.189.07:59:39.98#ibcon#about to write, iclass 32, count 0 2006.189.07:59:39.98#ibcon#wrote, iclass 32, count 0 2006.189.07:59:39.98#ibcon#about to read 3, iclass 32, count 0 2006.189.07:59:40.01#ibcon#read 3, iclass 32, count 0 2006.189.07:59:40.01#ibcon#about to read 4, iclass 32, count 0 2006.189.07:59:40.01#ibcon#read 4, iclass 32, count 0 2006.189.07:59:40.01#ibcon#about to read 5, iclass 32, count 0 2006.189.07:59:40.01#ibcon#read 5, iclass 32, count 0 2006.189.07:59:40.01#ibcon#about to read 6, iclass 32, count 0 2006.189.07:59:40.01#ibcon#read 6, iclass 32, count 0 2006.189.07:59:40.01#ibcon#end of sib2, iclass 32, count 0 2006.189.07:59:40.01#ibcon#*after write, iclass 32, count 0 2006.189.07:59:40.01#ibcon#*before return 0, iclass 32, count 0 2006.189.07:59:40.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:59:40.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.07:59:40.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:59:40.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:59:40.01$vc4f8/valo=7,832.99 2006.189.07:59:40.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.07:59:40.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.07:59:40.01#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:40.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:59:40.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:59:40.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:59:40.01#ibcon#enter wrdev, iclass 34, count 0 2006.189.07:59:40.01#ibcon#first serial, iclass 34, count 0 2006.189.07:59:40.01#ibcon#enter sib2, iclass 34, count 0 2006.189.07:59:40.01#ibcon#flushed, iclass 34, count 0 2006.189.07:59:40.01#ibcon#about to write, iclass 34, count 0 2006.189.07:59:40.01#ibcon#wrote, iclass 34, count 0 2006.189.07:59:40.01#ibcon#about to read 3, iclass 34, count 0 2006.189.07:59:40.03#ibcon#read 3, iclass 34, count 0 2006.189.07:59:40.03#ibcon#about to read 4, iclass 34, count 0 2006.189.07:59:40.03#ibcon#read 4, iclass 34, count 0 2006.189.07:59:40.03#ibcon#about to read 5, iclass 34, count 0 2006.189.07:59:40.03#ibcon#read 5, iclass 34, count 0 2006.189.07:59:40.03#ibcon#about to read 6, iclass 34, count 0 2006.189.07:59:40.03#ibcon#read 6, iclass 34, count 0 2006.189.07:59:40.03#ibcon#end of sib2, iclass 34, count 0 2006.189.07:59:40.03#ibcon#*mode == 0, iclass 34, count 0 2006.189.07:59:40.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.07:59:40.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.07:59:40.03#ibcon#*before write, iclass 34, count 0 2006.189.07:59:40.03#ibcon#enter sib2, iclass 34, count 0 2006.189.07:59:40.03#ibcon#flushed, iclass 34, count 0 2006.189.07:59:40.03#ibcon#about to write, iclass 34, count 0 2006.189.07:59:40.03#ibcon#wrote, iclass 34, count 0 2006.189.07:59:40.03#ibcon#about to read 3, iclass 34, count 0 2006.189.07:59:40.07#ibcon#read 3, iclass 34, count 0 2006.189.07:59:40.07#ibcon#about to read 4, iclass 34, count 0 2006.189.07:59:40.07#ibcon#read 4, iclass 34, count 0 2006.189.07:59:40.07#ibcon#about to read 5, iclass 34, count 0 2006.189.07:59:40.07#ibcon#read 5, iclass 34, count 0 2006.189.07:59:40.07#ibcon#about to read 6, iclass 34, count 0 2006.189.07:59:40.07#ibcon#read 6, iclass 34, count 0 2006.189.07:59:40.07#ibcon#end of sib2, iclass 34, count 0 2006.189.07:59:40.07#ibcon#*after write, iclass 34, count 0 2006.189.07:59:40.07#ibcon#*before return 0, iclass 34, count 0 2006.189.07:59:40.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:59:40.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.07:59:40.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.07:59:40.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.07:59:40.07$vc4f8/va=7,6 2006.189.07:59:40.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.07:59:40.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.07:59:40.07#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:40.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:59:40.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:59:40.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:59:40.13#ibcon#enter wrdev, iclass 36, count 2 2006.189.07:59:40.13#ibcon#first serial, iclass 36, count 2 2006.189.07:59:40.13#ibcon#enter sib2, iclass 36, count 2 2006.189.07:59:40.13#ibcon#flushed, iclass 36, count 2 2006.189.07:59:40.13#ibcon#about to write, iclass 36, count 2 2006.189.07:59:40.13#ibcon#wrote, iclass 36, count 2 2006.189.07:59:40.13#ibcon#about to read 3, iclass 36, count 2 2006.189.07:59:40.15#ibcon#read 3, iclass 36, count 2 2006.189.07:59:40.15#ibcon#about to read 4, iclass 36, count 2 2006.189.07:59:40.15#ibcon#read 4, iclass 36, count 2 2006.189.07:59:40.15#ibcon#about to read 5, iclass 36, count 2 2006.189.07:59:40.15#ibcon#read 5, iclass 36, count 2 2006.189.07:59:40.15#ibcon#about to read 6, iclass 36, count 2 2006.189.07:59:40.15#ibcon#read 6, iclass 36, count 2 2006.189.07:59:40.15#ibcon#end of sib2, iclass 36, count 2 2006.189.07:59:40.15#ibcon#*mode == 0, iclass 36, count 2 2006.189.07:59:40.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.07:59:40.15#ibcon#[25=AT07-06\r\n] 2006.189.07:59:40.15#ibcon#*before write, iclass 36, count 2 2006.189.07:59:40.15#ibcon#enter sib2, iclass 36, count 2 2006.189.07:59:40.15#ibcon#flushed, iclass 36, count 2 2006.189.07:59:40.15#ibcon#about to write, iclass 36, count 2 2006.189.07:59:40.15#ibcon#wrote, iclass 36, count 2 2006.189.07:59:40.15#ibcon#about to read 3, iclass 36, count 2 2006.189.07:59:40.18#ibcon#read 3, iclass 36, count 2 2006.189.07:59:40.18#ibcon#about to read 4, iclass 36, count 2 2006.189.07:59:40.18#ibcon#read 4, iclass 36, count 2 2006.189.07:59:40.18#ibcon#about to read 5, iclass 36, count 2 2006.189.07:59:40.18#ibcon#read 5, iclass 36, count 2 2006.189.07:59:40.18#ibcon#about to read 6, iclass 36, count 2 2006.189.07:59:40.18#ibcon#read 6, iclass 36, count 2 2006.189.07:59:40.18#ibcon#end of sib2, iclass 36, count 2 2006.189.07:59:40.18#ibcon#*after write, iclass 36, count 2 2006.189.07:59:40.18#ibcon#*before return 0, iclass 36, count 2 2006.189.07:59:40.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:59:40.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.07:59:40.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.07:59:40.18#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:40.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:59:40.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:59:40.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:59:40.30#ibcon#enter wrdev, iclass 36, count 0 2006.189.07:59:40.30#ibcon#first serial, iclass 36, count 0 2006.189.07:59:40.30#ibcon#enter sib2, iclass 36, count 0 2006.189.07:59:40.30#ibcon#flushed, iclass 36, count 0 2006.189.07:59:40.30#ibcon#about to write, iclass 36, count 0 2006.189.07:59:40.30#ibcon#wrote, iclass 36, count 0 2006.189.07:59:40.30#ibcon#about to read 3, iclass 36, count 0 2006.189.07:59:40.32#ibcon#read 3, iclass 36, count 0 2006.189.07:59:40.32#ibcon#about to read 4, iclass 36, count 0 2006.189.07:59:40.32#ibcon#read 4, iclass 36, count 0 2006.189.07:59:40.32#ibcon#about to read 5, iclass 36, count 0 2006.189.07:59:40.32#ibcon#read 5, iclass 36, count 0 2006.189.07:59:40.32#ibcon#about to read 6, iclass 36, count 0 2006.189.07:59:40.32#ibcon#read 6, iclass 36, count 0 2006.189.07:59:40.32#ibcon#end of sib2, iclass 36, count 0 2006.189.07:59:40.32#ibcon#*mode == 0, iclass 36, count 0 2006.189.07:59:40.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.07:59:40.32#ibcon#[25=USB\r\n] 2006.189.07:59:40.32#ibcon#*before write, iclass 36, count 0 2006.189.07:59:40.32#ibcon#enter sib2, iclass 36, count 0 2006.189.07:59:40.32#ibcon#flushed, iclass 36, count 0 2006.189.07:59:40.32#ibcon#about to write, iclass 36, count 0 2006.189.07:59:40.32#ibcon#wrote, iclass 36, count 0 2006.189.07:59:40.32#ibcon#about to read 3, iclass 36, count 0 2006.189.07:59:40.35#ibcon#read 3, iclass 36, count 0 2006.189.07:59:40.35#ibcon#about to read 4, iclass 36, count 0 2006.189.07:59:40.35#ibcon#read 4, iclass 36, count 0 2006.189.07:59:40.35#ibcon#about to read 5, iclass 36, count 0 2006.189.07:59:40.35#ibcon#read 5, iclass 36, count 0 2006.189.07:59:40.35#ibcon#about to read 6, iclass 36, count 0 2006.189.07:59:40.35#ibcon#read 6, iclass 36, count 0 2006.189.07:59:40.35#ibcon#end of sib2, iclass 36, count 0 2006.189.07:59:40.35#ibcon#*after write, iclass 36, count 0 2006.189.07:59:40.35#ibcon#*before return 0, iclass 36, count 0 2006.189.07:59:40.35#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:59:40.35#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.07:59:40.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.07:59:40.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.07:59:40.35$vc4f8/valo=8,852.99 2006.189.07:59:40.35#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.07:59:40.35#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.07:59:40.35#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:40.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:59:40.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:59:40.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:59:40.35#ibcon#enter wrdev, iclass 38, count 0 2006.189.07:59:40.35#ibcon#first serial, iclass 38, count 0 2006.189.07:59:40.35#ibcon#enter sib2, iclass 38, count 0 2006.189.07:59:40.35#ibcon#flushed, iclass 38, count 0 2006.189.07:59:40.35#ibcon#about to write, iclass 38, count 0 2006.189.07:59:40.35#ibcon#wrote, iclass 38, count 0 2006.189.07:59:40.35#ibcon#about to read 3, iclass 38, count 0 2006.189.07:59:40.37#ibcon#read 3, iclass 38, count 0 2006.189.07:59:40.37#ibcon#about to read 4, iclass 38, count 0 2006.189.07:59:40.37#ibcon#read 4, iclass 38, count 0 2006.189.07:59:40.37#ibcon#about to read 5, iclass 38, count 0 2006.189.07:59:40.37#ibcon#read 5, iclass 38, count 0 2006.189.07:59:40.37#ibcon#about to read 6, iclass 38, count 0 2006.189.07:59:40.37#ibcon#read 6, iclass 38, count 0 2006.189.07:59:40.37#ibcon#end of sib2, iclass 38, count 0 2006.189.07:59:40.37#ibcon#*mode == 0, iclass 38, count 0 2006.189.07:59:40.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.07:59:40.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.07:59:40.37#ibcon#*before write, iclass 38, count 0 2006.189.07:59:40.37#ibcon#enter sib2, iclass 38, count 0 2006.189.07:59:40.37#ibcon#flushed, iclass 38, count 0 2006.189.07:59:40.37#ibcon#about to write, iclass 38, count 0 2006.189.07:59:40.37#ibcon#wrote, iclass 38, count 0 2006.189.07:59:40.37#ibcon#about to read 3, iclass 38, count 0 2006.189.07:59:40.41#ibcon#read 3, iclass 38, count 0 2006.189.07:59:40.41#ibcon#about to read 4, iclass 38, count 0 2006.189.07:59:40.41#ibcon#read 4, iclass 38, count 0 2006.189.07:59:40.41#ibcon#about to read 5, iclass 38, count 0 2006.189.07:59:40.41#ibcon#read 5, iclass 38, count 0 2006.189.07:59:40.41#ibcon#about to read 6, iclass 38, count 0 2006.189.07:59:40.41#ibcon#read 6, iclass 38, count 0 2006.189.07:59:40.41#ibcon#end of sib2, iclass 38, count 0 2006.189.07:59:40.41#ibcon#*after write, iclass 38, count 0 2006.189.07:59:40.41#ibcon#*before return 0, iclass 38, count 0 2006.189.07:59:40.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:59:40.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.07:59:40.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.07:59:40.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.07:59:40.41$vc4f8/va=8,6 2006.189.07:59:40.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.07:59:40.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.07:59:40.41#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:40.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:59:40.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:59:40.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:59:40.47#ibcon#enter wrdev, iclass 40, count 2 2006.189.07:59:40.47#ibcon#first serial, iclass 40, count 2 2006.189.07:59:40.47#ibcon#enter sib2, iclass 40, count 2 2006.189.07:59:40.47#ibcon#flushed, iclass 40, count 2 2006.189.07:59:40.47#ibcon#about to write, iclass 40, count 2 2006.189.07:59:40.47#ibcon#wrote, iclass 40, count 2 2006.189.07:59:40.47#ibcon#about to read 3, iclass 40, count 2 2006.189.07:59:40.49#ibcon#read 3, iclass 40, count 2 2006.189.07:59:40.49#ibcon#about to read 4, iclass 40, count 2 2006.189.07:59:40.49#ibcon#read 4, iclass 40, count 2 2006.189.07:59:40.49#ibcon#about to read 5, iclass 40, count 2 2006.189.07:59:40.49#ibcon#read 5, iclass 40, count 2 2006.189.07:59:40.49#ibcon#about to read 6, iclass 40, count 2 2006.189.07:59:40.49#ibcon#read 6, iclass 40, count 2 2006.189.07:59:40.49#ibcon#end of sib2, iclass 40, count 2 2006.189.07:59:40.49#ibcon#*mode == 0, iclass 40, count 2 2006.189.07:59:40.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.07:59:40.49#ibcon#[25=AT08-06\r\n] 2006.189.07:59:40.49#ibcon#*before write, iclass 40, count 2 2006.189.07:59:40.49#ibcon#enter sib2, iclass 40, count 2 2006.189.07:59:40.49#ibcon#flushed, iclass 40, count 2 2006.189.07:59:40.49#ibcon#about to write, iclass 40, count 2 2006.189.07:59:40.49#ibcon#wrote, iclass 40, count 2 2006.189.07:59:40.49#ibcon#about to read 3, iclass 40, count 2 2006.189.07:59:40.52#ibcon#read 3, iclass 40, count 2 2006.189.07:59:40.52#ibcon#about to read 4, iclass 40, count 2 2006.189.07:59:40.52#ibcon#read 4, iclass 40, count 2 2006.189.07:59:40.52#ibcon#about to read 5, iclass 40, count 2 2006.189.07:59:40.52#ibcon#read 5, iclass 40, count 2 2006.189.07:59:40.52#ibcon#about to read 6, iclass 40, count 2 2006.189.07:59:40.52#ibcon#read 6, iclass 40, count 2 2006.189.07:59:40.52#ibcon#end of sib2, iclass 40, count 2 2006.189.07:59:40.52#ibcon#*after write, iclass 40, count 2 2006.189.07:59:40.52#ibcon#*before return 0, iclass 40, count 2 2006.189.07:59:40.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:59:40.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.07:59:40.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.07:59:40.52#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:40.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:59:40.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:59:40.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:59:40.64#ibcon#enter wrdev, iclass 40, count 0 2006.189.07:59:40.64#ibcon#first serial, iclass 40, count 0 2006.189.07:59:40.64#ibcon#enter sib2, iclass 40, count 0 2006.189.07:59:40.64#ibcon#flushed, iclass 40, count 0 2006.189.07:59:40.64#ibcon#about to write, iclass 40, count 0 2006.189.07:59:40.64#ibcon#wrote, iclass 40, count 0 2006.189.07:59:40.64#ibcon#about to read 3, iclass 40, count 0 2006.189.07:59:40.66#ibcon#read 3, iclass 40, count 0 2006.189.07:59:40.66#ibcon#about to read 4, iclass 40, count 0 2006.189.07:59:40.66#ibcon#read 4, iclass 40, count 0 2006.189.07:59:40.66#ibcon#about to read 5, iclass 40, count 0 2006.189.07:59:40.66#ibcon#read 5, iclass 40, count 0 2006.189.07:59:40.66#ibcon#about to read 6, iclass 40, count 0 2006.189.07:59:40.66#ibcon#read 6, iclass 40, count 0 2006.189.07:59:40.66#ibcon#end of sib2, iclass 40, count 0 2006.189.07:59:40.66#ibcon#*mode == 0, iclass 40, count 0 2006.189.07:59:40.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.07:59:40.66#ibcon#[25=USB\r\n] 2006.189.07:59:40.66#ibcon#*before write, iclass 40, count 0 2006.189.07:59:40.66#ibcon#enter sib2, iclass 40, count 0 2006.189.07:59:40.66#ibcon#flushed, iclass 40, count 0 2006.189.07:59:40.66#ibcon#about to write, iclass 40, count 0 2006.189.07:59:40.66#ibcon#wrote, iclass 40, count 0 2006.189.07:59:40.66#ibcon#about to read 3, iclass 40, count 0 2006.189.07:59:40.69#ibcon#read 3, iclass 40, count 0 2006.189.07:59:40.69#ibcon#about to read 4, iclass 40, count 0 2006.189.07:59:40.69#ibcon#read 4, iclass 40, count 0 2006.189.07:59:40.69#ibcon#about to read 5, iclass 40, count 0 2006.189.07:59:40.69#ibcon#read 5, iclass 40, count 0 2006.189.07:59:40.69#ibcon#about to read 6, iclass 40, count 0 2006.189.07:59:40.69#ibcon#read 6, iclass 40, count 0 2006.189.07:59:40.69#ibcon#end of sib2, iclass 40, count 0 2006.189.07:59:40.69#ibcon#*after write, iclass 40, count 0 2006.189.07:59:40.69#ibcon#*before return 0, iclass 40, count 0 2006.189.07:59:40.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:59:40.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.07:59:40.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.07:59:40.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.07:59:40.69$vc4f8/vblo=1,632.99 2006.189.07:59:40.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.07:59:40.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.07:59:40.69#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:40.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:40.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:40.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:40.69#ibcon#enter wrdev, iclass 4, count 0 2006.189.07:59:40.69#ibcon#first serial, iclass 4, count 0 2006.189.07:59:40.69#ibcon#enter sib2, iclass 4, count 0 2006.189.07:59:40.69#ibcon#flushed, iclass 4, count 0 2006.189.07:59:40.69#ibcon#about to write, iclass 4, count 0 2006.189.07:59:40.69#ibcon#wrote, iclass 4, count 0 2006.189.07:59:40.69#ibcon#about to read 3, iclass 4, count 0 2006.189.07:59:40.71#ibcon#read 3, iclass 4, count 0 2006.189.07:59:40.71#ibcon#about to read 4, iclass 4, count 0 2006.189.07:59:40.71#ibcon#read 4, iclass 4, count 0 2006.189.07:59:40.71#ibcon#about to read 5, iclass 4, count 0 2006.189.07:59:40.71#ibcon#read 5, iclass 4, count 0 2006.189.07:59:40.71#ibcon#about to read 6, iclass 4, count 0 2006.189.07:59:40.71#ibcon#read 6, iclass 4, count 0 2006.189.07:59:40.71#ibcon#end of sib2, iclass 4, count 0 2006.189.07:59:40.71#ibcon#*mode == 0, iclass 4, count 0 2006.189.07:59:40.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.07:59:40.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.07:59:40.71#ibcon#*before write, iclass 4, count 0 2006.189.07:59:40.71#ibcon#enter sib2, iclass 4, count 0 2006.189.07:59:40.71#ibcon#flushed, iclass 4, count 0 2006.189.07:59:40.71#ibcon#about to write, iclass 4, count 0 2006.189.07:59:40.71#ibcon#wrote, iclass 4, count 0 2006.189.07:59:40.71#ibcon#about to read 3, iclass 4, count 0 2006.189.07:59:40.75#ibcon#read 3, iclass 4, count 0 2006.189.07:59:40.75#ibcon#about to read 4, iclass 4, count 0 2006.189.07:59:40.75#ibcon#read 4, iclass 4, count 0 2006.189.07:59:40.75#ibcon#about to read 5, iclass 4, count 0 2006.189.07:59:40.75#ibcon#read 5, iclass 4, count 0 2006.189.07:59:40.75#ibcon#about to read 6, iclass 4, count 0 2006.189.07:59:40.75#ibcon#read 6, iclass 4, count 0 2006.189.07:59:40.75#ibcon#end of sib2, iclass 4, count 0 2006.189.07:59:40.75#ibcon#*after write, iclass 4, count 0 2006.189.07:59:40.75#ibcon#*before return 0, iclass 4, count 0 2006.189.07:59:40.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:40.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.07:59:40.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.07:59:40.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.07:59:40.75$vc4f8/vb=1,4 2006.189.07:59:40.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.07:59:40.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.07:59:40.75#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:40.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:40.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:40.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:40.75#ibcon#enter wrdev, iclass 6, count 2 2006.189.07:59:40.75#ibcon#first serial, iclass 6, count 2 2006.189.07:59:40.75#ibcon#enter sib2, iclass 6, count 2 2006.189.07:59:40.75#ibcon#flushed, iclass 6, count 2 2006.189.07:59:40.75#ibcon#about to write, iclass 6, count 2 2006.189.07:59:40.75#ibcon#wrote, iclass 6, count 2 2006.189.07:59:40.75#ibcon#about to read 3, iclass 6, count 2 2006.189.07:59:40.77#ibcon#read 3, iclass 6, count 2 2006.189.07:59:40.77#ibcon#about to read 4, iclass 6, count 2 2006.189.07:59:40.77#ibcon#read 4, iclass 6, count 2 2006.189.07:59:40.77#ibcon#about to read 5, iclass 6, count 2 2006.189.07:59:40.77#ibcon#read 5, iclass 6, count 2 2006.189.07:59:40.77#ibcon#about to read 6, iclass 6, count 2 2006.189.07:59:40.77#ibcon#read 6, iclass 6, count 2 2006.189.07:59:40.77#ibcon#end of sib2, iclass 6, count 2 2006.189.07:59:40.77#ibcon#*mode == 0, iclass 6, count 2 2006.189.07:59:40.77#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.07:59:40.77#ibcon#[27=AT01-04\r\n] 2006.189.07:59:40.77#ibcon#*before write, iclass 6, count 2 2006.189.07:59:40.77#ibcon#enter sib2, iclass 6, count 2 2006.189.07:59:40.77#ibcon#flushed, iclass 6, count 2 2006.189.07:59:40.77#ibcon#about to write, iclass 6, count 2 2006.189.07:59:40.77#ibcon#wrote, iclass 6, count 2 2006.189.07:59:40.77#ibcon#about to read 3, iclass 6, count 2 2006.189.07:59:40.80#ibcon#read 3, iclass 6, count 2 2006.189.07:59:40.80#ibcon#about to read 4, iclass 6, count 2 2006.189.07:59:40.80#ibcon#read 4, iclass 6, count 2 2006.189.07:59:40.80#ibcon#about to read 5, iclass 6, count 2 2006.189.07:59:40.80#ibcon#read 5, iclass 6, count 2 2006.189.07:59:40.80#ibcon#about to read 6, iclass 6, count 2 2006.189.07:59:40.80#ibcon#read 6, iclass 6, count 2 2006.189.07:59:40.80#ibcon#end of sib2, iclass 6, count 2 2006.189.07:59:40.80#ibcon#*after write, iclass 6, count 2 2006.189.07:59:40.80#ibcon#*before return 0, iclass 6, count 2 2006.189.07:59:40.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:40.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.07:59:40.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.07:59:40.80#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:40.80#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:40.92#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:40.92#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:40.92#ibcon#enter wrdev, iclass 6, count 0 2006.189.07:59:40.92#ibcon#first serial, iclass 6, count 0 2006.189.07:59:40.92#ibcon#enter sib2, iclass 6, count 0 2006.189.07:59:40.92#ibcon#flushed, iclass 6, count 0 2006.189.07:59:40.92#ibcon#about to write, iclass 6, count 0 2006.189.07:59:40.92#ibcon#wrote, iclass 6, count 0 2006.189.07:59:40.92#ibcon#about to read 3, iclass 6, count 0 2006.189.07:59:40.94#ibcon#read 3, iclass 6, count 0 2006.189.07:59:40.94#ibcon#about to read 4, iclass 6, count 0 2006.189.07:59:40.94#ibcon#read 4, iclass 6, count 0 2006.189.07:59:40.94#ibcon#about to read 5, iclass 6, count 0 2006.189.07:59:40.94#ibcon#read 5, iclass 6, count 0 2006.189.07:59:40.94#ibcon#about to read 6, iclass 6, count 0 2006.189.07:59:40.94#ibcon#read 6, iclass 6, count 0 2006.189.07:59:40.94#ibcon#end of sib2, iclass 6, count 0 2006.189.07:59:40.94#ibcon#*mode == 0, iclass 6, count 0 2006.189.07:59:40.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.07:59:40.94#ibcon#[27=USB\r\n] 2006.189.07:59:40.94#ibcon#*before write, iclass 6, count 0 2006.189.07:59:40.94#ibcon#enter sib2, iclass 6, count 0 2006.189.07:59:40.94#ibcon#flushed, iclass 6, count 0 2006.189.07:59:40.94#ibcon#about to write, iclass 6, count 0 2006.189.07:59:40.94#ibcon#wrote, iclass 6, count 0 2006.189.07:59:40.94#ibcon#about to read 3, iclass 6, count 0 2006.189.07:59:40.97#ibcon#read 3, iclass 6, count 0 2006.189.07:59:40.97#ibcon#about to read 4, iclass 6, count 0 2006.189.07:59:40.97#ibcon#read 4, iclass 6, count 0 2006.189.07:59:40.97#ibcon#about to read 5, iclass 6, count 0 2006.189.07:59:40.97#ibcon#read 5, iclass 6, count 0 2006.189.07:59:40.97#ibcon#about to read 6, iclass 6, count 0 2006.189.07:59:40.97#ibcon#read 6, iclass 6, count 0 2006.189.07:59:40.97#ibcon#end of sib2, iclass 6, count 0 2006.189.07:59:40.97#ibcon#*after write, iclass 6, count 0 2006.189.07:59:40.97#ibcon#*before return 0, iclass 6, count 0 2006.189.07:59:40.97#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:40.97#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.07:59:40.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.07:59:40.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.07:59:40.97$vc4f8/vblo=2,640.99 2006.189.07:59:40.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.07:59:40.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.07:59:40.97#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:40.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:40.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:40.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:40.97#ibcon#enter wrdev, iclass 10, count 0 2006.189.07:59:40.97#ibcon#first serial, iclass 10, count 0 2006.189.07:59:40.97#ibcon#enter sib2, iclass 10, count 0 2006.189.07:59:40.97#ibcon#flushed, iclass 10, count 0 2006.189.07:59:40.97#ibcon#about to write, iclass 10, count 0 2006.189.07:59:40.97#ibcon#wrote, iclass 10, count 0 2006.189.07:59:40.97#ibcon#about to read 3, iclass 10, count 0 2006.189.07:59:40.99#ibcon#read 3, iclass 10, count 0 2006.189.07:59:40.99#ibcon#about to read 4, iclass 10, count 0 2006.189.07:59:40.99#ibcon#read 4, iclass 10, count 0 2006.189.07:59:40.99#ibcon#about to read 5, iclass 10, count 0 2006.189.07:59:40.99#ibcon#read 5, iclass 10, count 0 2006.189.07:59:40.99#ibcon#about to read 6, iclass 10, count 0 2006.189.07:59:40.99#ibcon#read 6, iclass 10, count 0 2006.189.07:59:40.99#ibcon#end of sib2, iclass 10, count 0 2006.189.07:59:40.99#ibcon#*mode == 0, iclass 10, count 0 2006.189.07:59:40.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.07:59:40.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.07:59:40.99#ibcon#*before write, iclass 10, count 0 2006.189.07:59:40.99#ibcon#enter sib2, iclass 10, count 0 2006.189.07:59:40.99#ibcon#flushed, iclass 10, count 0 2006.189.07:59:40.99#ibcon#about to write, iclass 10, count 0 2006.189.07:59:40.99#ibcon#wrote, iclass 10, count 0 2006.189.07:59:40.99#ibcon#about to read 3, iclass 10, count 0 2006.189.07:59:41.03#ibcon#read 3, iclass 10, count 0 2006.189.07:59:41.03#ibcon#about to read 4, iclass 10, count 0 2006.189.07:59:41.03#ibcon#read 4, iclass 10, count 0 2006.189.07:59:41.03#ibcon#about to read 5, iclass 10, count 0 2006.189.07:59:41.03#ibcon#read 5, iclass 10, count 0 2006.189.07:59:41.03#ibcon#about to read 6, iclass 10, count 0 2006.189.07:59:41.03#ibcon#read 6, iclass 10, count 0 2006.189.07:59:41.03#ibcon#end of sib2, iclass 10, count 0 2006.189.07:59:41.03#ibcon#*after write, iclass 10, count 0 2006.189.07:59:41.03#ibcon#*before return 0, iclass 10, count 0 2006.189.07:59:41.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:41.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.07:59:41.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.07:59:41.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.07:59:41.03$vc4f8/vb=2,4 2006.189.07:59:41.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.07:59:41.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.07:59:41.03#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:41.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:41.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:41.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:41.09#ibcon#enter wrdev, iclass 12, count 2 2006.189.07:59:41.09#ibcon#first serial, iclass 12, count 2 2006.189.07:59:41.09#ibcon#enter sib2, iclass 12, count 2 2006.189.07:59:41.09#ibcon#flushed, iclass 12, count 2 2006.189.07:59:41.09#ibcon#about to write, iclass 12, count 2 2006.189.07:59:41.09#ibcon#wrote, iclass 12, count 2 2006.189.07:59:41.09#ibcon#about to read 3, iclass 12, count 2 2006.189.07:59:41.11#ibcon#read 3, iclass 12, count 2 2006.189.07:59:41.11#ibcon#about to read 4, iclass 12, count 2 2006.189.07:59:41.11#ibcon#read 4, iclass 12, count 2 2006.189.07:59:41.11#ibcon#about to read 5, iclass 12, count 2 2006.189.07:59:41.11#ibcon#read 5, iclass 12, count 2 2006.189.07:59:41.11#ibcon#about to read 6, iclass 12, count 2 2006.189.07:59:41.11#ibcon#read 6, iclass 12, count 2 2006.189.07:59:41.11#ibcon#end of sib2, iclass 12, count 2 2006.189.07:59:41.11#ibcon#*mode == 0, iclass 12, count 2 2006.189.07:59:41.11#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.07:59:41.11#ibcon#[27=AT02-04\r\n] 2006.189.07:59:41.11#ibcon#*before write, iclass 12, count 2 2006.189.07:59:41.11#ibcon#enter sib2, iclass 12, count 2 2006.189.07:59:41.11#ibcon#flushed, iclass 12, count 2 2006.189.07:59:41.11#ibcon#about to write, iclass 12, count 2 2006.189.07:59:41.11#ibcon#wrote, iclass 12, count 2 2006.189.07:59:41.11#ibcon#about to read 3, iclass 12, count 2 2006.189.07:59:41.14#ibcon#read 3, iclass 12, count 2 2006.189.07:59:41.14#ibcon#about to read 4, iclass 12, count 2 2006.189.07:59:41.14#ibcon#read 4, iclass 12, count 2 2006.189.07:59:41.14#ibcon#about to read 5, iclass 12, count 2 2006.189.07:59:41.14#ibcon#read 5, iclass 12, count 2 2006.189.07:59:41.14#ibcon#about to read 6, iclass 12, count 2 2006.189.07:59:41.14#ibcon#read 6, iclass 12, count 2 2006.189.07:59:41.14#ibcon#end of sib2, iclass 12, count 2 2006.189.07:59:41.14#ibcon#*after write, iclass 12, count 2 2006.189.07:59:41.14#ibcon#*before return 0, iclass 12, count 2 2006.189.07:59:41.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:41.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.07:59:41.14#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.07:59:41.14#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:41.14#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:41.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:41.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:41.26#ibcon#enter wrdev, iclass 12, count 0 2006.189.07:59:41.26#ibcon#first serial, iclass 12, count 0 2006.189.07:59:41.26#ibcon#enter sib2, iclass 12, count 0 2006.189.07:59:41.26#ibcon#flushed, iclass 12, count 0 2006.189.07:59:41.26#ibcon#about to write, iclass 12, count 0 2006.189.07:59:41.26#ibcon#wrote, iclass 12, count 0 2006.189.07:59:41.26#ibcon#about to read 3, iclass 12, count 0 2006.189.07:59:41.28#ibcon#read 3, iclass 12, count 0 2006.189.07:59:41.28#ibcon#about to read 4, iclass 12, count 0 2006.189.07:59:41.28#ibcon#read 4, iclass 12, count 0 2006.189.07:59:41.28#ibcon#about to read 5, iclass 12, count 0 2006.189.07:59:41.28#ibcon#read 5, iclass 12, count 0 2006.189.07:59:41.28#ibcon#about to read 6, iclass 12, count 0 2006.189.07:59:41.28#ibcon#read 6, iclass 12, count 0 2006.189.07:59:41.28#ibcon#end of sib2, iclass 12, count 0 2006.189.07:59:41.28#ibcon#*mode == 0, iclass 12, count 0 2006.189.07:59:41.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.07:59:41.28#ibcon#[27=USB\r\n] 2006.189.07:59:41.28#ibcon#*before write, iclass 12, count 0 2006.189.07:59:41.28#ibcon#enter sib2, iclass 12, count 0 2006.189.07:59:41.28#ibcon#flushed, iclass 12, count 0 2006.189.07:59:41.28#ibcon#about to write, iclass 12, count 0 2006.189.07:59:41.28#ibcon#wrote, iclass 12, count 0 2006.189.07:59:41.28#ibcon#about to read 3, iclass 12, count 0 2006.189.07:59:41.31#ibcon#read 3, iclass 12, count 0 2006.189.07:59:41.31#ibcon#about to read 4, iclass 12, count 0 2006.189.07:59:41.31#ibcon#read 4, iclass 12, count 0 2006.189.07:59:41.31#ibcon#about to read 5, iclass 12, count 0 2006.189.07:59:41.31#ibcon#read 5, iclass 12, count 0 2006.189.07:59:41.31#ibcon#about to read 6, iclass 12, count 0 2006.189.07:59:41.31#ibcon#read 6, iclass 12, count 0 2006.189.07:59:41.31#ibcon#end of sib2, iclass 12, count 0 2006.189.07:59:41.31#ibcon#*after write, iclass 12, count 0 2006.189.07:59:41.31#ibcon#*before return 0, iclass 12, count 0 2006.189.07:59:41.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:41.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.07:59:41.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.07:59:41.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.07:59:41.31$vc4f8/vblo=3,656.99 2006.189.07:59:41.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.07:59:41.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.07:59:41.31#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:41.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:59:41.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:59:41.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:59:41.31#ibcon#enter wrdev, iclass 14, count 0 2006.189.07:59:41.31#ibcon#first serial, iclass 14, count 0 2006.189.07:59:41.31#ibcon#enter sib2, iclass 14, count 0 2006.189.07:59:41.31#ibcon#flushed, iclass 14, count 0 2006.189.07:59:41.31#ibcon#about to write, iclass 14, count 0 2006.189.07:59:41.31#ibcon#wrote, iclass 14, count 0 2006.189.07:59:41.31#ibcon#about to read 3, iclass 14, count 0 2006.189.07:59:41.33#ibcon#read 3, iclass 14, count 0 2006.189.07:59:41.33#ibcon#about to read 4, iclass 14, count 0 2006.189.07:59:41.33#ibcon#read 4, iclass 14, count 0 2006.189.07:59:41.33#ibcon#about to read 5, iclass 14, count 0 2006.189.07:59:41.33#ibcon#read 5, iclass 14, count 0 2006.189.07:59:41.33#ibcon#about to read 6, iclass 14, count 0 2006.189.07:59:41.33#ibcon#read 6, iclass 14, count 0 2006.189.07:59:41.33#ibcon#end of sib2, iclass 14, count 0 2006.189.07:59:41.33#ibcon#*mode == 0, iclass 14, count 0 2006.189.07:59:41.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.07:59:41.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.07:59:41.33#ibcon#*before write, iclass 14, count 0 2006.189.07:59:41.33#ibcon#enter sib2, iclass 14, count 0 2006.189.07:59:41.33#ibcon#flushed, iclass 14, count 0 2006.189.07:59:41.33#ibcon#about to write, iclass 14, count 0 2006.189.07:59:41.33#ibcon#wrote, iclass 14, count 0 2006.189.07:59:41.33#ibcon#about to read 3, iclass 14, count 0 2006.189.07:59:41.37#ibcon#read 3, iclass 14, count 0 2006.189.07:59:41.37#ibcon#about to read 4, iclass 14, count 0 2006.189.07:59:41.37#ibcon#read 4, iclass 14, count 0 2006.189.07:59:41.37#ibcon#about to read 5, iclass 14, count 0 2006.189.07:59:41.37#ibcon#read 5, iclass 14, count 0 2006.189.07:59:41.37#ibcon#about to read 6, iclass 14, count 0 2006.189.07:59:41.37#ibcon#read 6, iclass 14, count 0 2006.189.07:59:41.37#ibcon#end of sib2, iclass 14, count 0 2006.189.07:59:41.37#ibcon#*after write, iclass 14, count 0 2006.189.07:59:41.37#ibcon#*before return 0, iclass 14, count 0 2006.189.07:59:41.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:59:41.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.07:59:41.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.07:59:41.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.07:59:41.37$vc4f8/vb=3,4 2006.189.07:59:41.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.07:59:41.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.07:59:41.37#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:41.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:59:41.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:59:41.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:59:41.43#ibcon#enter wrdev, iclass 16, count 2 2006.189.07:59:41.43#ibcon#first serial, iclass 16, count 2 2006.189.07:59:41.43#ibcon#enter sib2, iclass 16, count 2 2006.189.07:59:41.43#ibcon#flushed, iclass 16, count 2 2006.189.07:59:41.43#ibcon#about to write, iclass 16, count 2 2006.189.07:59:41.43#ibcon#wrote, iclass 16, count 2 2006.189.07:59:41.43#ibcon#about to read 3, iclass 16, count 2 2006.189.07:59:41.45#ibcon#read 3, iclass 16, count 2 2006.189.07:59:41.45#ibcon#about to read 4, iclass 16, count 2 2006.189.07:59:41.45#ibcon#read 4, iclass 16, count 2 2006.189.07:59:41.45#ibcon#about to read 5, iclass 16, count 2 2006.189.07:59:41.45#ibcon#read 5, iclass 16, count 2 2006.189.07:59:41.45#ibcon#about to read 6, iclass 16, count 2 2006.189.07:59:41.45#ibcon#read 6, iclass 16, count 2 2006.189.07:59:41.45#ibcon#end of sib2, iclass 16, count 2 2006.189.07:59:41.45#ibcon#*mode == 0, iclass 16, count 2 2006.189.07:59:41.45#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.07:59:41.45#ibcon#[27=AT03-04\r\n] 2006.189.07:59:41.45#ibcon#*before write, iclass 16, count 2 2006.189.07:59:41.45#ibcon#enter sib2, iclass 16, count 2 2006.189.07:59:41.45#ibcon#flushed, iclass 16, count 2 2006.189.07:59:41.45#ibcon#about to write, iclass 16, count 2 2006.189.07:59:41.45#ibcon#wrote, iclass 16, count 2 2006.189.07:59:41.45#ibcon#about to read 3, iclass 16, count 2 2006.189.07:59:41.48#ibcon#read 3, iclass 16, count 2 2006.189.07:59:41.48#ibcon#about to read 4, iclass 16, count 2 2006.189.07:59:41.48#ibcon#read 4, iclass 16, count 2 2006.189.07:59:41.48#ibcon#about to read 5, iclass 16, count 2 2006.189.07:59:41.48#ibcon#read 5, iclass 16, count 2 2006.189.07:59:41.48#ibcon#about to read 6, iclass 16, count 2 2006.189.07:59:41.48#ibcon#read 6, iclass 16, count 2 2006.189.07:59:41.48#ibcon#end of sib2, iclass 16, count 2 2006.189.07:59:41.48#ibcon#*after write, iclass 16, count 2 2006.189.07:59:41.48#ibcon#*before return 0, iclass 16, count 2 2006.189.07:59:41.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:59:41.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.07:59:41.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.07:59:41.48#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:41.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:59:41.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:59:41.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:59:41.60#ibcon#enter wrdev, iclass 16, count 0 2006.189.07:59:41.60#ibcon#first serial, iclass 16, count 0 2006.189.07:59:41.60#ibcon#enter sib2, iclass 16, count 0 2006.189.07:59:41.60#ibcon#flushed, iclass 16, count 0 2006.189.07:59:41.60#ibcon#about to write, iclass 16, count 0 2006.189.07:59:41.60#ibcon#wrote, iclass 16, count 0 2006.189.07:59:41.60#ibcon#about to read 3, iclass 16, count 0 2006.189.07:59:41.62#ibcon#read 3, iclass 16, count 0 2006.189.07:59:41.62#ibcon#about to read 4, iclass 16, count 0 2006.189.07:59:41.62#ibcon#read 4, iclass 16, count 0 2006.189.07:59:41.62#ibcon#about to read 5, iclass 16, count 0 2006.189.07:59:41.62#ibcon#read 5, iclass 16, count 0 2006.189.07:59:41.62#ibcon#about to read 6, iclass 16, count 0 2006.189.07:59:41.62#ibcon#read 6, iclass 16, count 0 2006.189.07:59:41.62#ibcon#end of sib2, iclass 16, count 0 2006.189.07:59:41.62#ibcon#*mode == 0, iclass 16, count 0 2006.189.07:59:41.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.07:59:41.62#ibcon#[27=USB\r\n] 2006.189.07:59:41.62#ibcon#*before write, iclass 16, count 0 2006.189.07:59:41.62#ibcon#enter sib2, iclass 16, count 0 2006.189.07:59:41.62#ibcon#flushed, iclass 16, count 0 2006.189.07:59:41.62#ibcon#about to write, iclass 16, count 0 2006.189.07:59:41.62#ibcon#wrote, iclass 16, count 0 2006.189.07:59:41.62#ibcon#about to read 3, iclass 16, count 0 2006.189.07:59:41.65#ibcon#read 3, iclass 16, count 0 2006.189.07:59:41.65#ibcon#about to read 4, iclass 16, count 0 2006.189.07:59:41.65#ibcon#read 4, iclass 16, count 0 2006.189.07:59:41.65#ibcon#about to read 5, iclass 16, count 0 2006.189.07:59:41.65#ibcon#read 5, iclass 16, count 0 2006.189.07:59:41.65#ibcon#about to read 6, iclass 16, count 0 2006.189.07:59:41.65#ibcon#read 6, iclass 16, count 0 2006.189.07:59:41.65#ibcon#end of sib2, iclass 16, count 0 2006.189.07:59:41.65#ibcon#*after write, iclass 16, count 0 2006.189.07:59:41.65#ibcon#*before return 0, iclass 16, count 0 2006.189.07:59:41.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:59:41.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.07:59:41.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.07:59:41.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.07:59:41.65$vc4f8/vblo=4,712.99 2006.189.07:59:41.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.07:59:41.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.07:59:41.65#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:41.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:59:41.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:59:41.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:59:41.65#ibcon#enter wrdev, iclass 18, count 0 2006.189.07:59:41.65#ibcon#first serial, iclass 18, count 0 2006.189.07:59:41.65#ibcon#enter sib2, iclass 18, count 0 2006.189.07:59:41.65#ibcon#flushed, iclass 18, count 0 2006.189.07:59:41.65#ibcon#about to write, iclass 18, count 0 2006.189.07:59:41.65#ibcon#wrote, iclass 18, count 0 2006.189.07:59:41.65#ibcon#about to read 3, iclass 18, count 0 2006.189.07:59:41.67#ibcon#read 3, iclass 18, count 0 2006.189.07:59:41.67#ibcon#about to read 4, iclass 18, count 0 2006.189.07:59:41.67#ibcon#read 4, iclass 18, count 0 2006.189.07:59:41.67#ibcon#about to read 5, iclass 18, count 0 2006.189.07:59:41.67#ibcon#read 5, iclass 18, count 0 2006.189.07:59:41.67#ibcon#about to read 6, iclass 18, count 0 2006.189.07:59:41.67#ibcon#read 6, iclass 18, count 0 2006.189.07:59:41.67#ibcon#end of sib2, iclass 18, count 0 2006.189.07:59:41.67#ibcon#*mode == 0, iclass 18, count 0 2006.189.07:59:41.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.07:59:41.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.07:59:41.67#ibcon#*before write, iclass 18, count 0 2006.189.07:59:41.67#ibcon#enter sib2, iclass 18, count 0 2006.189.07:59:41.67#ibcon#flushed, iclass 18, count 0 2006.189.07:59:41.67#ibcon#about to write, iclass 18, count 0 2006.189.07:59:41.67#ibcon#wrote, iclass 18, count 0 2006.189.07:59:41.67#ibcon#about to read 3, iclass 18, count 0 2006.189.07:59:41.71#ibcon#read 3, iclass 18, count 0 2006.189.07:59:41.71#ibcon#about to read 4, iclass 18, count 0 2006.189.07:59:41.71#ibcon#read 4, iclass 18, count 0 2006.189.07:59:41.71#ibcon#about to read 5, iclass 18, count 0 2006.189.07:59:41.71#ibcon#read 5, iclass 18, count 0 2006.189.07:59:41.71#ibcon#about to read 6, iclass 18, count 0 2006.189.07:59:41.71#ibcon#read 6, iclass 18, count 0 2006.189.07:59:41.71#ibcon#end of sib2, iclass 18, count 0 2006.189.07:59:41.71#ibcon#*after write, iclass 18, count 0 2006.189.07:59:41.71#ibcon#*before return 0, iclass 18, count 0 2006.189.07:59:41.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:59:41.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.07:59:41.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.07:59:41.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.07:59:41.71$vc4f8/vb=4,4 2006.189.07:59:41.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.07:59:41.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.07:59:41.71#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:41.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:41.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:41.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:41.77#ibcon#enter wrdev, iclass 20, count 2 2006.189.07:59:41.77#ibcon#first serial, iclass 20, count 2 2006.189.07:59:41.77#ibcon#enter sib2, iclass 20, count 2 2006.189.07:59:41.77#ibcon#flushed, iclass 20, count 2 2006.189.07:59:41.77#ibcon#about to write, iclass 20, count 2 2006.189.07:59:41.77#ibcon#wrote, iclass 20, count 2 2006.189.07:59:41.77#ibcon#about to read 3, iclass 20, count 2 2006.189.07:59:41.79#ibcon#read 3, iclass 20, count 2 2006.189.07:59:41.79#ibcon#about to read 4, iclass 20, count 2 2006.189.07:59:41.79#ibcon#read 4, iclass 20, count 2 2006.189.07:59:41.79#ibcon#about to read 5, iclass 20, count 2 2006.189.07:59:41.79#ibcon#read 5, iclass 20, count 2 2006.189.07:59:41.79#ibcon#about to read 6, iclass 20, count 2 2006.189.07:59:41.79#ibcon#read 6, iclass 20, count 2 2006.189.07:59:41.79#ibcon#end of sib2, iclass 20, count 2 2006.189.07:59:41.79#ibcon#*mode == 0, iclass 20, count 2 2006.189.07:59:41.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.07:59:41.79#ibcon#[27=AT04-04\r\n] 2006.189.07:59:41.79#ibcon#*before write, iclass 20, count 2 2006.189.07:59:41.79#ibcon#enter sib2, iclass 20, count 2 2006.189.07:59:41.79#ibcon#flushed, iclass 20, count 2 2006.189.07:59:41.79#ibcon#about to write, iclass 20, count 2 2006.189.07:59:41.79#ibcon#wrote, iclass 20, count 2 2006.189.07:59:41.79#ibcon#about to read 3, iclass 20, count 2 2006.189.07:59:41.82#ibcon#read 3, iclass 20, count 2 2006.189.07:59:41.82#ibcon#about to read 4, iclass 20, count 2 2006.189.07:59:41.82#ibcon#read 4, iclass 20, count 2 2006.189.07:59:41.82#ibcon#about to read 5, iclass 20, count 2 2006.189.07:59:41.82#ibcon#read 5, iclass 20, count 2 2006.189.07:59:41.82#ibcon#about to read 6, iclass 20, count 2 2006.189.07:59:41.82#ibcon#read 6, iclass 20, count 2 2006.189.07:59:41.82#ibcon#end of sib2, iclass 20, count 2 2006.189.07:59:41.82#ibcon#*after write, iclass 20, count 2 2006.189.07:59:41.82#ibcon#*before return 0, iclass 20, count 2 2006.189.07:59:41.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:41.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.07:59:41.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.07:59:41.82#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:41.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:41.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:41.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:41.94#ibcon#enter wrdev, iclass 20, count 0 2006.189.07:59:41.94#ibcon#first serial, iclass 20, count 0 2006.189.07:59:41.94#ibcon#enter sib2, iclass 20, count 0 2006.189.07:59:41.94#ibcon#flushed, iclass 20, count 0 2006.189.07:59:41.94#ibcon#about to write, iclass 20, count 0 2006.189.07:59:41.94#ibcon#wrote, iclass 20, count 0 2006.189.07:59:41.94#ibcon#about to read 3, iclass 20, count 0 2006.189.07:59:41.96#ibcon#read 3, iclass 20, count 0 2006.189.07:59:41.96#ibcon#about to read 4, iclass 20, count 0 2006.189.07:59:41.96#ibcon#read 4, iclass 20, count 0 2006.189.07:59:41.96#ibcon#about to read 5, iclass 20, count 0 2006.189.07:59:41.96#ibcon#read 5, iclass 20, count 0 2006.189.07:59:41.96#ibcon#about to read 6, iclass 20, count 0 2006.189.07:59:41.96#ibcon#read 6, iclass 20, count 0 2006.189.07:59:41.96#ibcon#end of sib2, iclass 20, count 0 2006.189.07:59:41.96#ibcon#*mode == 0, iclass 20, count 0 2006.189.07:59:41.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.07:59:41.96#ibcon#[27=USB\r\n] 2006.189.07:59:41.96#ibcon#*before write, iclass 20, count 0 2006.189.07:59:41.96#ibcon#enter sib2, iclass 20, count 0 2006.189.07:59:41.96#ibcon#flushed, iclass 20, count 0 2006.189.07:59:41.96#ibcon#about to write, iclass 20, count 0 2006.189.07:59:41.96#ibcon#wrote, iclass 20, count 0 2006.189.07:59:41.96#ibcon#about to read 3, iclass 20, count 0 2006.189.07:59:41.99#ibcon#read 3, iclass 20, count 0 2006.189.07:59:41.99#ibcon#about to read 4, iclass 20, count 0 2006.189.07:59:41.99#ibcon#read 4, iclass 20, count 0 2006.189.07:59:41.99#ibcon#about to read 5, iclass 20, count 0 2006.189.07:59:41.99#ibcon#read 5, iclass 20, count 0 2006.189.07:59:41.99#ibcon#about to read 6, iclass 20, count 0 2006.189.07:59:41.99#ibcon#read 6, iclass 20, count 0 2006.189.07:59:41.99#ibcon#end of sib2, iclass 20, count 0 2006.189.07:59:41.99#ibcon#*after write, iclass 20, count 0 2006.189.07:59:41.99#ibcon#*before return 0, iclass 20, count 0 2006.189.07:59:41.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:41.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.07:59:41.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.07:59:41.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.07:59:41.99$vc4f8/vblo=5,744.99 2006.189.07:59:41.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.07:59:41.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.07:59:41.99#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:41.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:41.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:41.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:41.99#ibcon#enter wrdev, iclass 22, count 0 2006.189.07:59:41.99#ibcon#first serial, iclass 22, count 0 2006.189.07:59:41.99#ibcon#enter sib2, iclass 22, count 0 2006.189.07:59:41.99#ibcon#flushed, iclass 22, count 0 2006.189.07:59:41.99#ibcon#about to write, iclass 22, count 0 2006.189.07:59:41.99#ibcon#wrote, iclass 22, count 0 2006.189.07:59:41.99#ibcon#about to read 3, iclass 22, count 0 2006.189.07:59:42.01#ibcon#read 3, iclass 22, count 0 2006.189.07:59:42.01#ibcon#about to read 4, iclass 22, count 0 2006.189.07:59:42.01#ibcon#read 4, iclass 22, count 0 2006.189.07:59:42.01#ibcon#about to read 5, iclass 22, count 0 2006.189.07:59:42.01#ibcon#read 5, iclass 22, count 0 2006.189.07:59:42.01#ibcon#about to read 6, iclass 22, count 0 2006.189.07:59:42.01#ibcon#read 6, iclass 22, count 0 2006.189.07:59:42.01#ibcon#end of sib2, iclass 22, count 0 2006.189.07:59:42.01#ibcon#*mode == 0, iclass 22, count 0 2006.189.07:59:42.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.07:59:42.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.07:59:42.01#ibcon#*before write, iclass 22, count 0 2006.189.07:59:42.01#ibcon#enter sib2, iclass 22, count 0 2006.189.07:59:42.01#ibcon#flushed, iclass 22, count 0 2006.189.07:59:42.01#ibcon#about to write, iclass 22, count 0 2006.189.07:59:42.01#ibcon#wrote, iclass 22, count 0 2006.189.07:59:42.01#ibcon#about to read 3, iclass 22, count 0 2006.189.07:59:42.05#ibcon#read 3, iclass 22, count 0 2006.189.07:59:42.05#ibcon#about to read 4, iclass 22, count 0 2006.189.07:59:42.05#ibcon#read 4, iclass 22, count 0 2006.189.07:59:42.05#ibcon#about to read 5, iclass 22, count 0 2006.189.07:59:42.05#ibcon#read 5, iclass 22, count 0 2006.189.07:59:42.05#ibcon#about to read 6, iclass 22, count 0 2006.189.07:59:42.05#ibcon#read 6, iclass 22, count 0 2006.189.07:59:42.05#ibcon#end of sib2, iclass 22, count 0 2006.189.07:59:42.05#ibcon#*after write, iclass 22, count 0 2006.189.07:59:42.05#ibcon#*before return 0, iclass 22, count 0 2006.189.07:59:42.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:42.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.07:59:42.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.07:59:42.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.07:59:42.05$vc4f8/vb=5,4 2006.189.07:59:42.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.07:59:42.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.07:59:42.05#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:42.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:42.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:42.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:42.11#ibcon#enter wrdev, iclass 24, count 2 2006.189.07:59:42.11#ibcon#first serial, iclass 24, count 2 2006.189.07:59:42.11#ibcon#enter sib2, iclass 24, count 2 2006.189.07:59:42.11#ibcon#flushed, iclass 24, count 2 2006.189.07:59:42.11#ibcon#about to write, iclass 24, count 2 2006.189.07:59:42.11#ibcon#wrote, iclass 24, count 2 2006.189.07:59:42.11#ibcon#about to read 3, iclass 24, count 2 2006.189.07:59:42.13#ibcon#read 3, iclass 24, count 2 2006.189.07:59:42.13#ibcon#about to read 4, iclass 24, count 2 2006.189.07:59:42.13#ibcon#read 4, iclass 24, count 2 2006.189.07:59:42.13#ibcon#about to read 5, iclass 24, count 2 2006.189.07:59:42.13#ibcon#read 5, iclass 24, count 2 2006.189.07:59:42.13#ibcon#about to read 6, iclass 24, count 2 2006.189.07:59:42.13#ibcon#read 6, iclass 24, count 2 2006.189.07:59:42.13#ibcon#end of sib2, iclass 24, count 2 2006.189.07:59:42.13#ibcon#*mode == 0, iclass 24, count 2 2006.189.07:59:42.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.07:59:42.13#ibcon#[27=AT05-04\r\n] 2006.189.07:59:42.13#ibcon#*before write, iclass 24, count 2 2006.189.07:59:42.13#ibcon#enter sib2, iclass 24, count 2 2006.189.07:59:42.13#ibcon#flushed, iclass 24, count 2 2006.189.07:59:42.13#ibcon#about to write, iclass 24, count 2 2006.189.07:59:42.13#ibcon#wrote, iclass 24, count 2 2006.189.07:59:42.13#ibcon#about to read 3, iclass 24, count 2 2006.189.07:59:42.16#ibcon#read 3, iclass 24, count 2 2006.189.07:59:42.16#ibcon#about to read 4, iclass 24, count 2 2006.189.07:59:42.16#ibcon#read 4, iclass 24, count 2 2006.189.07:59:42.16#ibcon#about to read 5, iclass 24, count 2 2006.189.07:59:42.16#ibcon#read 5, iclass 24, count 2 2006.189.07:59:42.16#ibcon#about to read 6, iclass 24, count 2 2006.189.07:59:42.16#ibcon#read 6, iclass 24, count 2 2006.189.07:59:42.16#ibcon#end of sib2, iclass 24, count 2 2006.189.07:59:42.16#ibcon#*after write, iclass 24, count 2 2006.189.07:59:42.16#ibcon#*before return 0, iclass 24, count 2 2006.189.07:59:42.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:42.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.07:59:42.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.07:59:42.16#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:42.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:42.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:42.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:42.28#ibcon#enter wrdev, iclass 24, count 0 2006.189.07:59:42.28#ibcon#first serial, iclass 24, count 0 2006.189.07:59:42.28#ibcon#enter sib2, iclass 24, count 0 2006.189.07:59:42.28#ibcon#flushed, iclass 24, count 0 2006.189.07:59:42.28#ibcon#about to write, iclass 24, count 0 2006.189.07:59:42.28#ibcon#wrote, iclass 24, count 0 2006.189.07:59:42.28#ibcon#about to read 3, iclass 24, count 0 2006.189.07:59:42.30#ibcon#read 3, iclass 24, count 0 2006.189.07:59:42.30#ibcon#about to read 4, iclass 24, count 0 2006.189.07:59:42.30#ibcon#read 4, iclass 24, count 0 2006.189.07:59:42.30#ibcon#about to read 5, iclass 24, count 0 2006.189.07:59:42.30#ibcon#read 5, iclass 24, count 0 2006.189.07:59:42.30#ibcon#about to read 6, iclass 24, count 0 2006.189.07:59:42.30#ibcon#read 6, iclass 24, count 0 2006.189.07:59:42.30#ibcon#end of sib2, iclass 24, count 0 2006.189.07:59:42.30#ibcon#*mode == 0, iclass 24, count 0 2006.189.07:59:42.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.07:59:42.30#ibcon#[27=USB\r\n] 2006.189.07:59:42.30#ibcon#*before write, iclass 24, count 0 2006.189.07:59:42.30#ibcon#enter sib2, iclass 24, count 0 2006.189.07:59:42.30#ibcon#flushed, iclass 24, count 0 2006.189.07:59:42.30#ibcon#about to write, iclass 24, count 0 2006.189.07:59:42.30#ibcon#wrote, iclass 24, count 0 2006.189.07:59:42.30#ibcon#about to read 3, iclass 24, count 0 2006.189.07:59:42.33#ibcon#read 3, iclass 24, count 0 2006.189.07:59:42.33#ibcon#about to read 4, iclass 24, count 0 2006.189.07:59:42.33#ibcon#read 4, iclass 24, count 0 2006.189.07:59:42.33#ibcon#about to read 5, iclass 24, count 0 2006.189.07:59:42.33#ibcon#read 5, iclass 24, count 0 2006.189.07:59:42.33#ibcon#about to read 6, iclass 24, count 0 2006.189.07:59:42.33#ibcon#read 6, iclass 24, count 0 2006.189.07:59:42.33#ibcon#end of sib2, iclass 24, count 0 2006.189.07:59:42.33#ibcon#*after write, iclass 24, count 0 2006.189.07:59:42.33#ibcon#*before return 0, iclass 24, count 0 2006.189.07:59:42.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:42.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.07:59:42.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.07:59:42.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.07:59:42.33$vc4f8/vblo=6,752.99 2006.189.07:59:42.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.07:59:42.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.07:59:42.33#ibcon#ireg 17 cls_cnt 0 2006.189.07:59:42.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:42.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:42.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:42.33#ibcon#enter wrdev, iclass 26, count 0 2006.189.07:59:42.33#ibcon#first serial, iclass 26, count 0 2006.189.07:59:42.33#ibcon#enter sib2, iclass 26, count 0 2006.189.07:59:42.33#ibcon#flushed, iclass 26, count 0 2006.189.07:59:42.33#ibcon#about to write, iclass 26, count 0 2006.189.07:59:42.33#ibcon#wrote, iclass 26, count 0 2006.189.07:59:42.33#ibcon#about to read 3, iclass 26, count 0 2006.189.07:59:42.35#ibcon#read 3, iclass 26, count 0 2006.189.07:59:42.35#ibcon#about to read 4, iclass 26, count 0 2006.189.07:59:42.35#ibcon#read 4, iclass 26, count 0 2006.189.07:59:42.35#ibcon#about to read 5, iclass 26, count 0 2006.189.07:59:42.35#ibcon#read 5, iclass 26, count 0 2006.189.07:59:42.35#ibcon#about to read 6, iclass 26, count 0 2006.189.07:59:42.35#ibcon#read 6, iclass 26, count 0 2006.189.07:59:42.35#ibcon#end of sib2, iclass 26, count 0 2006.189.07:59:42.35#ibcon#*mode == 0, iclass 26, count 0 2006.189.07:59:42.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.07:59:42.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.07:59:42.35#ibcon#*before write, iclass 26, count 0 2006.189.07:59:42.35#ibcon#enter sib2, iclass 26, count 0 2006.189.07:59:42.35#ibcon#flushed, iclass 26, count 0 2006.189.07:59:42.35#ibcon#about to write, iclass 26, count 0 2006.189.07:59:42.35#ibcon#wrote, iclass 26, count 0 2006.189.07:59:42.35#ibcon#about to read 3, iclass 26, count 0 2006.189.07:59:42.39#ibcon#read 3, iclass 26, count 0 2006.189.07:59:42.39#ibcon#about to read 4, iclass 26, count 0 2006.189.07:59:42.39#ibcon#read 4, iclass 26, count 0 2006.189.07:59:42.39#ibcon#about to read 5, iclass 26, count 0 2006.189.07:59:42.39#ibcon#read 5, iclass 26, count 0 2006.189.07:59:42.39#ibcon#about to read 6, iclass 26, count 0 2006.189.07:59:42.39#ibcon#read 6, iclass 26, count 0 2006.189.07:59:42.39#ibcon#end of sib2, iclass 26, count 0 2006.189.07:59:42.39#ibcon#*after write, iclass 26, count 0 2006.189.07:59:42.39#ibcon#*before return 0, iclass 26, count 0 2006.189.07:59:42.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:42.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.07:59:42.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.07:59:42.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.07:59:42.39$vc4f8/vb=6,4 2006.189.07:59:42.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.07:59:42.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.07:59:42.39#ibcon#ireg 11 cls_cnt 2 2006.189.07:59:42.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:42.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:42.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:42.45#ibcon#enter wrdev, iclass 28, count 2 2006.189.07:59:42.45#ibcon#first serial, iclass 28, count 2 2006.189.07:59:42.45#ibcon#enter sib2, iclass 28, count 2 2006.189.07:59:42.45#ibcon#flushed, iclass 28, count 2 2006.189.07:59:42.45#ibcon#about to write, iclass 28, count 2 2006.189.07:59:42.45#ibcon#wrote, iclass 28, count 2 2006.189.07:59:42.45#ibcon#about to read 3, iclass 28, count 2 2006.189.07:59:42.47#ibcon#read 3, iclass 28, count 2 2006.189.07:59:42.47#ibcon#about to read 4, iclass 28, count 2 2006.189.07:59:42.47#ibcon#read 4, iclass 28, count 2 2006.189.07:59:42.47#ibcon#about to read 5, iclass 28, count 2 2006.189.07:59:42.47#ibcon#read 5, iclass 28, count 2 2006.189.07:59:42.47#ibcon#about to read 6, iclass 28, count 2 2006.189.07:59:42.47#ibcon#read 6, iclass 28, count 2 2006.189.07:59:42.47#ibcon#end of sib2, iclass 28, count 2 2006.189.07:59:42.47#ibcon#*mode == 0, iclass 28, count 2 2006.189.07:59:42.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.07:59:42.47#ibcon#[27=AT06-04\r\n] 2006.189.07:59:42.47#ibcon#*before write, iclass 28, count 2 2006.189.07:59:42.47#ibcon#enter sib2, iclass 28, count 2 2006.189.07:59:42.47#ibcon#flushed, iclass 28, count 2 2006.189.07:59:42.47#ibcon#about to write, iclass 28, count 2 2006.189.07:59:42.47#ibcon#wrote, iclass 28, count 2 2006.189.07:59:42.47#ibcon#about to read 3, iclass 28, count 2 2006.189.07:59:42.50#ibcon#read 3, iclass 28, count 2 2006.189.07:59:42.50#ibcon#about to read 4, iclass 28, count 2 2006.189.07:59:42.50#ibcon#read 4, iclass 28, count 2 2006.189.07:59:42.50#ibcon#about to read 5, iclass 28, count 2 2006.189.07:59:42.50#ibcon#read 5, iclass 28, count 2 2006.189.07:59:42.50#ibcon#about to read 6, iclass 28, count 2 2006.189.07:59:42.50#ibcon#read 6, iclass 28, count 2 2006.189.07:59:42.50#ibcon#end of sib2, iclass 28, count 2 2006.189.07:59:42.50#ibcon#*after write, iclass 28, count 2 2006.189.07:59:42.50#ibcon#*before return 0, iclass 28, count 2 2006.189.07:59:42.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:42.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.07:59:42.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.07:59:42.50#ibcon#ireg 7 cls_cnt 0 2006.189.07:59:42.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:42.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:42.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:42.62#ibcon#enter wrdev, iclass 28, count 0 2006.189.07:59:42.62#ibcon#first serial, iclass 28, count 0 2006.189.07:59:42.62#ibcon#enter sib2, iclass 28, count 0 2006.189.07:59:42.62#ibcon#flushed, iclass 28, count 0 2006.189.07:59:42.62#ibcon#about to write, iclass 28, count 0 2006.189.07:59:42.62#ibcon#wrote, iclass 28, count 0 2006.189.07:59:42.62#ibcon#about to read 3, iclass 28, count 0 2006.189.07:59:42.64#ibcon#read 3, iclass 28, count 0 2006.189.07:59:42.64#ibcon#about to read 4, iclass 28, count 0 2006.189.07:59:42.64#ibcon#read 4, iclass 28, count 0 2006.189.07:59:42.64#ibcon#about to read 5, iclass 28, count 0 2006.189.07:59:42.64#ibcon#read 5, iclass 28, count 0 2006.189.07:59:42.64#ibcon#about to read 6, iclass 28, count 0 2006.189.07:59:42.64#ibcon#read 6, iclass 28, count 0 2006.189.07:59:42.64#ibcon#end of sib2, iclass 28, count 0 2006.189.07:59:42.64#ibcon#*mode == 0, iclass 28, count 0 2006.189.07:59:42.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.07:59:42.64#ibcon#[27=USB\r\n] 2006.189.07:59:42.64#ibcon#*before write, iclass 28, count 0 2006.189.07:59:42.64#ibcon#enter sib2, iclass 28, count 0 2006.189.07:59:42.64#ibcon#flushed, iclass 28, count 0 2006.189.07:59:42.64#ibcon#about to write, iclass 28, count 0 2006.189.07:59:42.64#ibcon#wrote, iclass 28, count 0 2006.189.07:59:42.64#ibcon#about to read 3, iclass 28, count 0 2006.189.07:59:42.67#ibcon#read 3, iclass 28, count 0 2006.189.07:59:42.67#ibcon#about to read 4, iclass 28, count 0 2006.189.07:59:42.67#ibcon#read 4, iclass 28, count 0 2006.189.07:59:42.67#ibcon#about to read 5, iclass 28, count 0 2006.189.07:59:42.67#ibcon#read 5, iclass 28, count 0 2006.189.07:59:42.67#ibcon#about to read 6, iclass 28, count 0 2006.189.07:59:42.67#ibcon#read 6, iclass 28, count 0 2006.189.07:59:42.67#ibcon#end of sib2, iclass 28, count 0 2006.189.07:59:42.67#ibcon#*after write, iclass 28, count 0 2006.189.07:59:42.67#ibcon#*before return 0, iclass 28, count 0 2006.189.07:59:42.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:42.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.07:59:42.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.07:59:42.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.07:59:42.67$vc4f8/vabw=wide 2006.189.07:59:42.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.07:59:42.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.07:59:42.67#ibcon#ireg 8 cls_cnt 0 2006.189.07:59:42.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:42.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:42.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:42.67#ibcon#enter wrdev, iclass 30, count 0 2006.189.07:59:42.67#ibcon#first serial, iclass 30, count 0 2006.189.07:59:42.67#ibcon#enter sib2, iclass 30, count 0 2006.189.07:59:42.67#ibcon#flushed, iclass 30, count 0 2006.189.07:59:42.67#ibcon#about to write, iclass 30, count 0 2006.189.07:59:42.67#ibcon#wrote, iclass 30, count 0 2006.189.07:59:42.67#ibcon#about to read 3, iclass 30, count 0 2006.189.07:59:42.69#ibcon#read 3, iclass 30, count 0 2006.189.07:59:42.69#ibcon#about to read 4, iclass 30, count 0 2006.189.07:59:42.69#ibcon#read 4, iclass 30, count 0 2006.189.07:59:42.69#ibcon#about to read 5, iclass 30, count 0 2006.189.07:59:42.69#ibcon#read 5, iclass 30, count 0 2006.189.07:59:42.69#ibcon#about to read 6, iclass 30, count 0 2006.189.07:59:42.69#ibcon#read 6, iclass 30, count 0 2006.189.07:59:42.69#ibcon#end of sib2, iclass 30, count 0 2006.189.07:59:42.69#ibcon#*mode == 0, iclass 30, count 0 2006.189.07:59:42.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.07:59:42.69#ibcon#[25=BW32\r\n] 2006.189.07:59:42.69#ibcon#*before write, iclass 30, count 0 2006.189.07:59:42.69#ibcon#enter sib2, iclass 30, count 0 2006.189.07:59:42.69#ibcon#flushed, iclass 30, count 0 2006.189.07:59:42.69#ibcon#about to write, iclass 30, count 0 2006.189.07:59:42.69#ibcon#wrote, iclass 30, count 0 2006.189.07:59:42.69#ibcon#about to read 3, iclass 30, count 0 2006.189.07:59:42.72#ibcon#read 3, iclass 30, count 0 2006.189.07:59:42.72#ibcon#about to read 4, iclass 30, count 0 2006.189.07:59:42.72#ibcon#read 4, iclass 30, count 0 2006.189.07:59:42.72#ibcon#about to read 5, iclass 30, count 0 2006.189.07:59:42.72#ibcon#read 5, iclass 30, count 0 2006.189.07:59:42.72#ibcon#about to read 6, iclass 30, count 0 2006.189.07:59:42.72#ibcon#read 6, iclass 30, count 0 2006.189.07:59:42.72#ibcon#end of sib2, iclass 30, count 0 2006.189.07:59:42.72#ibcon#*after write, iclass 30, count 0 2006.189.07:59:42.72#ibcon#*before return 0, iclass 30, count 0 2006.189.07:59:42.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:42.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.07:59:42.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.07:59:42.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.07:59:42.72$vc4f8/vbbw=wide 2006.189.07:59:42.72#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.07:59:42.72#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.07:59:42.72#ibcon#ireg 8 cls_cnt 0 2006.189.07:59:42.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:59:42.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:59:42.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:59:42.79#ibcon#enter wrdev, iclass 32, count 0 2006.189.07:59:42.79#ibcon#first serial, iclass 32, count 0 2006.189.07:59:42.79#ibcon#enter sib2, iclass 32, count 0 2006.189.07:59:42.79#ibcon#flushed, iclass 32, count 0 2006.189.07:59:42.79#ibcon#about to write, iclass 32, count 0 2006.189.07:59:42.79#ibcon#wrote, iclass 32, count 0 2006.189.07:59:42.79#ibcon#about to read 3, iclass 32, count 0 2006.189.07:59:42.81#ibcon#read 3, iclass 32, count 0 2006.189.07:59:42.81#ibcon#about to read 4, iclass 32, count 0 2006.189.07:59:42.81#ibcon#read 4, iclass 32, count 0 2006.189.07:59:42.81#ibcon#about to read 5, iclass 32, count 0 2006.189.07:59:42.81#ibcon#read 5, iclass 32, count 0 2006.189.07:59:42.81#ibcon#about to read 6, iclass 32, count 0 2006.189.07:59:42.81#ibcon#read 6, iclass 32, count 0 2006.189.07:59:42.81#ibcon#end of sib2, iclass 32, count 0 2006.189.07:59:42.81#ibcon#*mode == 0, iclass 32, count 0 2006.189.07:59:42.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.07:59:42.81#ibcon#[27=BW32\r\n] 2006.189.07:59:42.81#ibcon#*before write, iclass 32, count 0 2006.189.07:59:42.81#ibcon#enter sib2, iclass 32, count 0 2006.189.07:59:42.81#ibcon#flushed, iclass 32, count 0 2006.189.07:59:42.81#ibcon#about to write, iclass 32, count 0 2006.189.07:59:42.81#ibcon#wrote, iclass 32, count 0 2006.189.07:59:42.81#ibcon#about to read 3, iclass 32, count 0 2006.189.07:59:42.84#ibcon#read 3, iclass 32, count 0 2006.189.07:59:42.84#ibcon#about to read 4, iclass 32, count 0 2006.189.07:59:42.84#ibcon#read 4, iclass 32, count 0 2006.189.07:59:42.84#ibcon#about to read 5, iclass 32, count 0 2006.189.07:59:42.84#ibcon#read 5, iclass 32, count 0 2006.189.07:59:42.84#ibcon#about to read 6, iclass 32, count 0 2006.189.07:59:42.84#ibcon#read 6, iclass 32, count 0 2006.189.07:59:42.84#ibcon#end of sib2, iclass 32, count 0 2006.189.07:59:42.84#ibcon#*after write, iclass 32, count 0 2006.189.07:59:42.84#ibcon#*before return 0, iclass 32, count 0 2006.189.07:59:42.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:59:42.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.07:59:42.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.07:59:42.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.07:59:42.84$4f8m12a/ifd4f 2006.189.07:59:42.84$ifd4f/lo= 2006.189.07:59:42.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.07:59:42.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.07:59:42.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.07:59:42.84$ifd4f/patch= 2006.189.07:59:42.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.07:59:42.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.07:59:42.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.07:59:42.84$4f8m12a/"form=m,16.000,1:2 2006.189.07:59:42.84$4f8m12a/"tpicd 2006.189.07:59:42.84$4f8m12a/echo=off 2006.189.07:59:42.84$4f8m12a/xlog=off 2006.189.07:59:42.84:!2006.189.08:00:10 2006.189.07:59:55.14#trakl#Source acquired 2006.189.07:59:55.14#flagr#flagr/antenna,acquired 2006.189.08:00:10.00:preob 2006.189.08:00:11.14/onsource/TRACKING 2006.189.08:00:11.14:!2006.189.08:00:20 2006.189.08:00:20.00:data_valid=on 2006.189.08:00:20.00:midob 2006.189.08:00:20.14/onsource/TRACKING 2006.189.08:00:20.14/wx/25.71,1009.1,91 2006.189.08:00:20.34/cable/+6.4547E-03 2006.189.08:00:21.43/va/01,08,usb,yes,28,30 2006.189.08:00:21.43/va/02,07,usb,yes,29,30 2006.189.08:00:21.43/va/03,06,usb,yes,30,30 2006.189.08:00:21.43/va/04,07,usb,yes,29,32 2006.189.08:00:21.43/va/05,07,usb,yes,31,33 2006.189.08:00:21.43/va/06,06,usb,yes,30,30 2006.189.08:00:21.43/va/07,06,usb,yes,30,30 2006.189.08:00:21.43/va/08,06,usb,yes,33,32 2006.189.08:00:21.66/valo/01,532.99,yes,locked 2006.189.08:00:21.66/valo/02,572.99,yes,locked 2006.189.08:00:21.66/valo/03,672.99,yes,locked 2006.189.08:00:21.66/valo/04,832.99,yes,locked 2006.189.08:00:21.66/valo/05,652.99,yes,locked 2006.189.08:00:21.66/valo/06,772.99,yes,locked 2006.189.08:00:21.66/valo/07,832.99,yes,locked 2006.189.08:00:21.66/valo/08,852.99,yes,locked 2006.189.08:00:22.75/vb/01,04,usb,yes,28,27 2006.189.08:00:22.75/vb/02,04,usb,yes,30,32 2006.189.08:00:22.75/vb/03,04,usb,yes,27,30 2006.189.08:00:22.75/vb/04,04,usb,yes,27,28 2006.189.08:00:22.75/vb/05,04,usb,yes,26,30 2006.189.08:00:22.75/vb/06,04,usb,yes,27,30 2006.189.08:00:22.75/vb/07,04,usb,yes,29,29 2006.189.08:00:22.75/vb/08,04,usb,yes,27,30 2006.189.08:00:22.98/vblo/01,632.99,yes,locked 2006.189.08:00:22.98/vblo/02,640.99,yes,locked 2006.189.08:00:22.98/vblo/03,656.99,yes,locked 2006.189.08:00:22.98/vblo/04,712.99,yes,locked 2006.189.08:00:22.98/vblo/05,744.99,yes,locked 2006.189.08:00:22.98/vblo/06,752.99,yes,locked 2006.189.08:00:22.98/vblo/07,734.99,yes,locked 2006.189.08:00:22.98/vblo/08,744.99,yes,locked 2006.189.08:00:23.13/vabw/8 2006.189.08:00:23.28/vbbw/8 2006.189.08:00:23.40/xfe/off,on,15.2 2006.189.08:00:23.77/ifatt/23,28,28,28 2006.189.08:00:24.08/fmout-gps/S +2.97E-07 2006.189.08:00:24.16:!2006.189.08:01:20 2006.189.08:01:20.01:data_valid=off 2006.189.08:01:20.01:postob 2006.189.08:01:20.21/cable/+6.4554E-03 2006.189.08:01:20.21/wx/25.70,1009.1,90 2006.189.08:01:21.08/fmout-gps/S +2.97E-07 2006.189.08:01:21.08:scan_name=189-0802,k06189,60 2006.189.08:01:21.09:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.189.08:01:21.13#flagr#flagr/antenna,new-source 2006.189.08:01:22.13:checkk5 2006.189.08:01:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:01:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:01:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:01:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:01:24.02/chk_obsdata//k5ts1/T1890800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:01:24.41/chk_obsdata//k5ts2/T1890800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:01:24.78/chk_obsdata//k5ts3/T1890800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:01:25.15/chk_obsdata//k5ts4/T1890800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:01:25.84/k5log//k5ts1_log_newline 2006.189.08:01:26.54/k5log//k5ts2_log_newline 2006.189.08:01:27.24/k5log//k5ts3_log_newline 2006.189.08:01:27.93/k5log//k5ts4_log_newline 2006.189.08:01:27.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:01:27.95:4f8m12a=2 2006.189.08:01:27.95$4f8m12a/echo=on 2006.189.08:01:27.95$4f8m12a/pcalon 2006.189.08:01:27.95$pcalon/"no phase cal control is implemented here 2006.189.08:01:27.96$4f8m12a/"tpicd=stop 2006.189.08:01:27.96$4f8m12a/vc4f8 2006.189.08:01:27.96$vc4f8/valo=1,532.99 2006.189.08:01:27.96#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.08:01:27.96#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.08:01:27.96#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:27.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:27.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:27.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:27.96#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:01:27.96#ibcon#first serial, iclass 39, count 0 2006.189.08:01:27.96#ibcon#enter sib2, iclass 39, count 0 2006.189.08:01:27.96#ibcon#flushed, iclass 39, count 0 2006.189.08:01:27.96#ibcon#about to write, iclass 39, count 0 2006.189.08:01:27.96#ibcon#wrote, iclass 39, count 0 2006.189.08:01:27.96#ibcon#about to read 3, iclass 39, count 0 2006.189.08:01:28.01#ibcon#read 3, iclass 39, count 0 2006.189.08:01:28.01#ibcon#about to read 4, iclass 39, count 0 2006.189.08:01:28.01#ibcon#read 4, iclass 39, count 0 2006.189.08:01:28.01#ibcon#about to read 5, iclass 39, count 0 2006.189.08:01:28.01#ibcon#read 5, iclass 39, count 0 2006.189.08:01:28.01#ibcon#about to read 6, iclass 39, count 0 2006.189.08:01:28.01#ibcon#read 6, iclass 39, count 0 2006.189.08:01:28.01#ibcon#end of sib2, iclass 39, count 0 2006.189.08:01:28.01#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:01:28.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:01:28.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:01:28.01#ibcon#*before write, iclass 39, count 0 2006.189.08:01:28.01#ibcon#enter sib2, iclass 39, count 0 2006.189.08:01:28.01#ibcon#flushed, iclass 39, count 0 2006.189.08:01:28.01#ibcon#about to write, iclass 39, count 0 2006.189.08:01:28.01#ibcon#wrote, iclass 39, count 0 2006.189.08:01:28.01#ibcon#about to read 3, iclass 39, count 0 2006.189.08:01:28.06#ibcon#read 3, iclass 39, count 0 2006.189.08:01:28.06#ibcon#about to read 4, iclass 39, count 0 2006.189.08:01:28.06#ibcon#read 4, iclass 39, count 0 2006.189.08:01:28.06#ibcon#about to read 5, iclass 39, count 0 2006.189.08:01:28.06#ibcon#read 5, iclass 39, count 0 2006.189.08:01:28.06#ibcon#about to read 6, iclass 39, count 0 2006.189.08:01:28.06#ibcon#read 6, iclass 39, count 0 2006.189.08:01:28.06#ibcon#end of sib2, iclass 39, count 0 2006.189.08:01:28.06#ibcon#*after write, iclass 39, count 0 2006.189.08:01:28.06#ibcon#*before return 0, iclass 39, count 0 2006.189.08:01:28.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:28.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:28.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:01:28.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:01:28.06$vc4f8/va=1,8 2006.189.08:01:28.06#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.08:01:28.06#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.08:01:28.06#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:28.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:28.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:28.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:28.06#ibcon#enter wrdev, iclass 3, count 2 2006.189.08:01:28.06#ibcon#first serial, iclass 3, count 2 2006.189.08:01:28.06#ibcon#enter sib2, iclass 3, count 2 2006.189.08:01:28.06#ibcon#flushed, iclass 3, count 2 2006.189.08:01:28.06#ibcon#about to write, iclass 3, count 2 2006.189.08:01:28.06#ibcon#wrote, iclass 3, count 2 2006.189.08:01:28.06#ibcon#about to read 3, iclass 3, count 2 2006.189.08:01:28.08#ibcon#read 3, iclass 3, count 2 2006.189.08:01:28.08#ibcon#about to read 4, iclass 3, count 2 2006.189.08:01:28.08#ibcon#read 4, iclass 3, count 2 2006.189.08:01:28.08#ibcon#about to read 5, iclass 3, count 2 2006.189.08:01:28.08#ibcon#read 5, iclass 3, count 2 2006.189.08:01:28.08#ibcon#about to read 6, iclass 3, count 2 2006.189.08:01:28.08#ibcon#read 6, iclass 3, count 2 2006.189.08:01:28.08#ibcon#end of sib2, iclass 3, count 2 2006.189.08:01:28.08#ibcon#*mode == 0, iclass 3, count 2 2006.189.08:01:28.08#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.08:01:28.08#ibcon#[25=AT01-08\r\n] 2006.189.08:01:28.08#ibcon#*before write, iclass 3, count 2 2006.189.08:01:28.08#ibcon#enter sib2, iclass 3, count 2 2006.189.08:01:28.08#ibcon#flushed, iclass 3, count 2 2006.189.08:01:28.08#ibcon#about to write, iclass 3, count 2 2006.189.08:01:28.08#ibcon#wrote, iclass 3, count 2 2006.189.08:01:28.08#ibcon#about to read 3, iclass 3, count 2 2006.189.08:01:28.11#ibcon#read 3, iclass 3, count 2 2006.189.08:01:28.11#ibcon#about to read 4, iclass 3, count 2 2006.189.08:01:28.11#ibcon#read 4, iclass 3, count 2 2006.189.08:01:28.11#ibcon#about to read 5, iclass 3, count 2 2006.189.08:01:28.11#ibcon#read 5, iclass 3, count 2 2006.189.08:01:28.11#ibcon#about to read 6, iclass 3, count 2 2006.189.08:01:28.11#ibcon#read 6, iclass 3, count 2 2006.189.08:01:28.11#ibcon#end of sib2, iclass 3, count 2 2006.189.08:01:28.11#ibcon#*after write, iclass 3, count 2 2006.189.08:01:28.11#ibcon#*before return 0, iclass 3, count 2 2006.189.08:01:28.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:28.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:28.11#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.08:01:28.11#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:28.11#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:28.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:28.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:28.23#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:01:28.23#ibcon#first serial, iclass 3, count 0 2006.189.08:01:28.23#ibcon#enter sib2, iclass 3, count 0 2006.189.08:01:28.23#ibcon#flushed, iclass 3, count 0 2006.189.08:01:28.23#ibcon#about to write, iclass 3, count 0 2006.189.08:01:28.23#ibcon#wrote, iclass 3, count 0 2006.189.08:01:28.23#ibcon#about to read 3, iclass 3, count 0 2006.189.08:01:28.25#ibcon#read 3, iclass 3, count 0 2006.189.08:01:28.25#ibcon#about to read 4, iclass 3, count 0 2006.189.08:01:28.25#ibcon#read 4, iclass 3, count 0 2006.189.08:01:28.25#ibcon#about to read 5, iclass 3, count 0 2006.189.08:01:28.25#ibcon#read 5, iclass 3, count 0 2006.189.08:01:28.25#ibcon#about to read 6, iclass 3, count 0 2006.189.08:01:28.25#ibcon#read 6, iclass 3, count 0 2006.189.08:01:28.25#ibcon#end of sib2, iclass 3, count 0 2006.189.08:01:28.25#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:01:28.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:01:28.25#ibcon#[25=USB\r\n] 2006.189.08:01:28.25#ibcon#*before write, iclass 3, count 0 2006.189.08:01:28.25#ibcon#enter sib2, iclass 3, count 0 2006.189.08:01:28.25#ibcon#flushed, iclass 3, count 0 2006.189.08:01:28.25#ibcon#about to write, iclass 3, count 0 2006.189.08:01:28.25#ibcon#wrote, iclass 3, count 0 2006.189.08:01:28.25#ibcon#about to read 3, iclass 3, count 0 2006.189.08:01:28.28#ibcon#read 3, iclass 3, count 0 2006.189.08:01:28.28#ibcon#about to read 4, iclass 3, count 0 2006.189.08:01:28.28#ibcon#read 4, iclass 3, count 0 2006.189.08:01:28.28#ibcon#about to read 5, iclass 3, count 0 2006.189.08:01:28.28#ibcon#read 5, iclass 3, count 0 2006.189.08:01:28.28#ibcon#about to read 6, iclass 3, count 0 2006.189.08:01:28.28#ibcon#read 6, iclass 3, count 0 2006.189.08:01:28.28#ibcon#end of sib2, iclass 3, count 0 2006.189.08:01:28.28#ibcon#*after write, iclass 3, count 0 2006.189.08:01:28.28#ibcon#*before return 0, iclass 3, count 0 2006.189.08:01:28.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:28.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:28.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:01:28.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:01:28.28$vc4f8/valo=2,572.99 2006.189.08:01:28.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.08:01:28.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.08:01:28.28#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:28.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:28.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:28.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:28.28#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:01:28.28#ibcon#first serial, iclass 5, count 0 2006.189.08:01:28.28#ibcon#enter sib2, iclass 5, count 0 2006.189.08:01:28.28#ibcon#flushed, iclass 5, count 0 2006.189.08:01:28.28#ibcon#about to write, iclass 5, count 0 2006.189.08:01:28.28#ibcon#wrote, iclass 5, count 0 2006.189.08:01:28.28#ibcon#about to read 3, iclass 5, count 0 2006.189.08:01:28.30#ibcon#read 3, iclass 5, count 0 2006.189.08:01:28.30#ibcon#about to read 4, iclass 5, count 0 2006.189.08:01:28.30#ibcon#read 4, iclass 5, count 0 2006.189.08:01:28.30#ibcon#about to read 5, iclass 5, count 0 2006.189.08:01:28.30#ibcon#read 5, iclass 5, count 0 2006.189.08:01:28.30#ibcon#about to read 6, iclass 5, count 0 2006.189.08:01:28.30#ibcon#read 6, iclass 5, count 0 2006.189.08:01:28.30#ibcon#end of sib2, iclass 5, count 0 2006.189.08:01:28.30#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:01:28.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:01:28.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:01:28.30#ibcon#*before write, iclass 5, count 0 2006.189.08:01:28.30#ibcon#enter sib2, iclass 5, count 0 2006.189.08:01:28.30#ibcon#flushed, iclass 5, count 0 2006.189.08:01:28.30#ibcon#about to write, iclass 5, count 0 2006.189.08:01:28.30#ibcon#wrote, iclass 5, count 0 2006.189.08:01:28.30#ibcon#about to read 3, iclass 5, count 0 2006.189.08:01:28.34#ibcon#read 3, iclass 5, count 0 2006.189.08:01:28.34#ibcon#about to read 4, iclass 5, count 0 2006.189.08:01:28.34#ibcon#read 4, iclass 5, count 0 2006.189.08:01:28.34#ibcon#about to read 5, iclass 5, count 0 2006.189.08:01:28.34#ibcon#read 5, iclass 5, count 0 2006.189.08:01:28.34#ibcon#about to read 6, iclass 5, count 0 2006.189.08:01:28.34#ibcon#read 6, iclass 5, count 0 2006.189.08:01:28.34#ibcon#end of sib2, iclass 5, count 0 2006.189.08:01:28.34#ibcon#*after write, iclass 5, count 0 2006.189.08:01:28.34#ibcon#*before return 0, iclass 5, count 0 2006.189.08:01:28.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:28.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:28.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:01:28.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:01:28.34$vc4f8/va=2,7 2006.189.08:01:28.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.08:01:28.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.08:01:28.34#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:28.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:28.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:28.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:28.40#ibcon#enter wrdev, iclass 7, count 2 2006.189.08:01:28.40#ibcon#first serial, iclass 7, count 2 2006.189.08:01:28.40#ibcon#enter sib2, iclass 7, count 2 2006.189.08:01:28.40#ibcon#flushed, iclass 7, count 2 2006.189.08:01:28.40#ibcon#about to write, iclass 7, count 2 2006.189.08:01:28.40#ibcon#wrote, iclass 7, count 2 2006.189.08:01:28.40#ibcon#about to read 3, iclass 7, count 2 2006.189.08:01:28.42#ibcon#read 3, iclass 7, count 2 2006.189.08:01:28.42#ibcon#about to read 4, iclass 7, count 2 2006.189.08:01:28.42#ibcon#read 4, iclass 7, count 2 2006.189.08:01:28.42#ibcon#about to read 5, iclass 7, count 2 2006.189.08:01:28.42#ibcon#read 5, iclass 7, count 2 2006.189.08:01:28.42#ibcon#about to read 6, iclass 7, count 2 2006.189.08:01:28.42#ibcon#read 6, iclass 7, count 2 2006.189.08:01:28.42#ibcon#end of sib2, iclass 7, count 2 2006.189.08:01:28.42#ibcon#*mode == 0, iclass 7, count 2 2006.189.08:01:28.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.08:01:28.42#ibcon#[25=AT02-07\r\n] 2006.189.08:01:28.42#ibcon#*before write, iclass 7, count 2 2006.189.08:01:28.42#ibcon#enter sib2, iclass 7, count 2 2006.189.08:01:28.42#ibcon#flushed, iclass 7, count 2 2006.189.08:01:28.42#ibcon#about to write, iclass 7, count 2 2006.189.08:01:28.42#ibcon#wrote, iclass 7, count 2 2006.189.08:01:28.42#ibcon#about to read 3, iclass 7, count 2 2006.189.08:01:28.45#ibcon#read 3, iclass 7, count 2 2006.189.08:01:28.45#ibcon#about to read 4, iclass 7, count 2 2006.189.08:01:28.45#ibcon#read 4, iclass 7, count 2 2006.189.08:01:28.45#ibcon#about to read 5, iclass 7, count 2 2006.189.08:01:28.45#ibcon#read 5, iclass 7, count 2 2006.189.08:01:28.45#ibcon#about to read 6, iclass 7, count 2 2006.189.08:01:28.45#ibcon#read 6, iclass 7, count 2 2006.189.08:01:28.45#ibcon#end of sib2, iclass 7, count 2 2006.189.08:01:28.45#ibcon#*after write, iclass 7, count 2 2006.189.08:01:28.45#ibcon#*before return 0, iclass 7, count 2 2006.189.08:01:28.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:28.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:28.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.08:01:28.45#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:28.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:28.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:28.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:28.57#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:01:28.57#ibcon#first serial, iclass 7, count 0 2006.189.08:01:28.57#ibcon#enter sib2, iclass 7, count 0 2006.189.08:01:28.57#ibcon#flushed, iclass 7, count 0 2006.189.08:01:28.57#ibcon#about to write, iclass 7, count 0 2006.189.08:01:28.57#ibcon#wrote, iclass 7, count 0 2006.189.08:01:28.57#ibcon#about to read 3, iclass 7, count 0 2006.189.08:01:28.59#ibcon#read 3, iclass 7, count 0 2006.189.08:01:28.59#ibcon#about to read 4, iclass 7, count 0 2006.189.08:01:28.59#ibcon#read 4, iclass 7, count 0 2006.189.08:01:28.59#ibcon#about to read 5, iclass 7, count 0 2006.189.08:01:28.59#ibcon#read 5, iclass 7, count 0 2006.189.08:01:28.59#ibcon#about to read 6, iclass 7, count 0 2006.189.08:01:28.59#ibcon#read 6, iclass 7, count 0 2006.189.08:01:28.59#ibcon#end of sib2, iclass 7, count 0 2006.189.08:01:28.59#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:01:28.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:01:28.59#ibcon#[25=USB\r\n] 2006.189.08:01:28.59#ibcon#*before write, iclass 7, count 0 2006.189.08:01:28.59#ibcon#enter sib2, iclass 7, count 0 2006.189.08:01:28.59#ibcon#flushed, iclass 7, count 0 2006.189.08:01:28.59#ibcon#about to write, iclass 7, count 0 2006.189.08:01:28.59#ibcon#wrote, iclass 7, count 0 2006.189.08:01:28.59#ibcon#about to read 3, iclass 7, count 0 2006.189.08:01:28.62#ibcon#read 3, iclass 7, count 0 2006.189.08:01:28.62#ibcon#about to read 4, iclass 7, count 0 2006.189.08:01:28.62#ibcon#read 4, iclass 7, count 0 2006.189.08:01:28.62#ibcon#about to read 5, iclass 7, count 0 2006.189.08:01:28.62#ibcon#read 5, iclass 7, count 0 2006.189.08:01:28.62#ibcon#about to read 6, iclass 7, count 0 2006.189.08:01:28.62#ibcon#read 6, iclass 7, count 0 2006.189.08:01:28.62#ibcon#end of sib2, iclass 7, count 0 2006.189.08:01:28.62#ibcon#*after write, iclass 7, count 0 2006.189.08:01:28.62#ibcon#*before return 0, iclass 7, count 0 2006.189.08:01:28.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:28.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:28.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:01:28.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:01:28.62$vc4f8/valo=3,672.99 2006.189.08:01:28.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.08:01:28.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.08:01:28.62#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:28.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:28.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:28.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:28.62#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:01:28.62#ibcon#first serial, iclass 11, count 0 2006.189.08:01:28.62#ibcon#enter sib2, iclass 11, count 0 2006.189.08:01:28.62#ibcon#flushed, iclass 11, count 0 2006.189.08:01:28.62#ibcon#about to write, iclass 11, count 0 2006.189.08:01:28.62#ibcon#wrote, iclass 11, count 0 2006.189.08:01:28.62#ibcon#about to read 3, iclass 11, count 0 2006.189.08:01:28.64#ibcon#read 3, iclass 11, count 0 2006.189.08:01:28.64#ibcon#about to read 4, iclass 11, count 0 2006.189.08:01:28.64#ibcon#read 4, iclass 11, count 0 2006.189.08:01:28.64#ibcon#about to read 5, iclass 11, count 0 2006.189.08:01:28.64#ibcon#read 5, iclass 11, count 0 2006.189.08:01:28.64#ibcon#about to read 6, iclass 11, count 0 2006.189.08:01:28.64#ibcon#read 6, iclass 11, count 0 2006.189.08:01:28.64#ibcon#end of sib2, iclass 11, count 0 2006.189.08:01:28.64#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:01:28.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:01:28.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:01:28.64#ibcon#*before write, iclass 11, count 0 2006.189.08:01:28.64#ibcon#enter sib2, iclass 11, count 0 2006.189.08:01:28.64#ibcon#flushed, iclass 11, count 0 2006.189.08:01:28.64#ibcon#about to write, iclass 11, count 0 2006.189.08:01:28.64#ibcon#wrote, iclass 11, count 0 2006.189.08:01:28.64#ibcon#about to read 3, iclass 11, count 0 2006.189.08:01:28.68#ibcon#read 3, iclass 11, count 0 2006.189.08:01:28.68#ibcon#about to read 4, iclass 11, count 0 2006.189.08:01:28.68#ibcon#read 4, iclass 11, count 0 2006.189.08:01:28.68#ibcon#about to read 5, iclass 11, count 0 2006.189.08:01:28.68#ibcon#read 5, iclass 11, count 0 2006.189.08:01:28.68#ibcon#about to read 6, iclass 11, count 0 2006.189.08:01:28.68#ibcon#read 6, iclass 11, count 0 2006.189.08:01:28.68#ibcon#end of sib2, iclass 11, count 0 2006.189.08:01:28.68#ibcon#*after write, iclass 11, count 0 2006.189.08:01:28.68#ibcon#*before return 0, iclass 11, count 0 2006.189.08:01:28.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:28.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:28.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:01:28.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:01:28.68$vc4f8/va=3,6 2006.189.08:01:28.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.08:01:28.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.08:01:28.68#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:28.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:28.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:28.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:28.74#ibcon#enter wrdev, iclass 13, count 2 2006.189.08:01:28.74#ibcon#first serial, iclass 13, count 2 2006.189.08:01:28.74#ibcon#enter sib2, iclass 13, count 2 2006.189.08:01:28.74#ibcon#flushed, iclass 13, count 2 2006.189.08:01:28.74#ibcon#about to write, iclass 13, count 2 2006.189.08:01:28.74#ibcon#wrote, iclass 13, count 2 2006.189.08:01:28.74#ibcon#about to read 3, iclass 13, count 2 2006.189.08:01:28.76#ibcon#read 3, iclass 13, count 2 2006.189.08:01:28.76#ibcon#about to read 4, iclass 13, count 2 2006.189.08:01:28.76#ibcon#read 4, iclass 13, count 2 2006.189.08:01:28.76#ibcon#about to read 5, iclass 13, count 2 2006.189.08:01:28.76#ibcon#read 5, iclass 13, count 2 2006.189.08:01:28.76#ibcon#about to read 6, iclass 13, count 2 2006.189.08:01:28.76#ibcon#read 6, iclass 13, count 2 2006.189.08:01:28.76#ibcon#end of sib2, iclass 13, count 2 2006.189.08:01:28.76#ibcon#*mode == 0, iclass 13, count 2 2006.189.08:01:28.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.08:01:28.76#ibcon#[25=AT03-06\r\n] 2006.189.08:01:28.76#ibcon#*before write, iclass 13, count 2 2006.189.08:01:28.76#ibcon#enter sib2, iclass 13, count 2 2006.189.08:01:28.76#ibcon#flushed, iclass 13, count 2 2006.189.08:01:28.76#ibcon#about to write, iclass 13, count 2 2006.189.08:01:28.76#ibcon#wrote, iclass 13, count 2 2006.189.08:01:28.76#ibcon#about to read 3, iclass 13, count 2 2006.189.08:01:28.79#ibcon#read 3, iclass 13, count 2 2006.189.08:01:28.79#ibcon#about to read 4, iclass 13, count 2 2006.189.08:01:28.79#ibcon#read 4, iclass 13, count 2 2006.189.08:01:28.79#ibcon#about to read 5, iclass 13, count 2 2006.189.08:01:28.79#ibcon#read 5, iclass 13, count 2 2006.189.08:01:28.79#ibcon#about to read 6, iclass 13, count 2 2006.189.08:01:28.79#ibcon#read 6, iclass 13, count 2 2006.189.08:01:28.79#ibcon#end of sib2, iclass 13, count 2 2006.189.08:01:28.79#ibcon#*after write, iclass 13, count 2 2006.189.08:01:28.79#ibcon#*before return 0, iclass 13, count 2 2006.189.08:01:28.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:28.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:28.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.08:01:28.79#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:28.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:28.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:28.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:28.91#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:01:28.91#ibcon#first serial, iclass 13, count 0 2006.189.08:01:28.91#ibcon#enter sib2, iclass 13, count 0 2006.189.08:01:28.91#ibcon#flushed, iclass 13, count 0 2006.189.08:01:28.91#ibcon#about to write, iclass 13, count 0 2006.189.08:01:28.91#ibcon#wrote, iclass 13, count 0 2006.189.08:01:28.91#ibcon#about to read 3, iclass 13, count 0 2006.189.08:01:28.93#ibcon#read 3, iclass 13, count 0 2006.189.08:01:28.93#ibcon#about to read 4, iclass 13, count 0 2006.189.08:01:28.93#ibcon#read 4, iclass 13, count 0 2006.189.08:01:28.93#ibcon#about to read 5, iclass 13, count 0 2006.189.08:01:28.93#ibcon#read 5, iclass 13, count 0 2006.189.08:01:28.93#ibcon#about to read 6, iclass 13, count 0 2006.189.08:01:28.93#ibcon#read 6, iclass 13, count 0 2006.189.08:01:28.93#ibcon#end of sib2, iclass 13, count 0 2006.189.08:01:28.93#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:01:28.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:01:28.93#ibcon#[25=USB\r\n] 2006.189.08:01:28.93#ibcon#*before write, iclass 13, count 0 2006.189.08:01:28.93#ibcon#enter sib2, iclass 13, count 0 2006.189.08:01:28.93#ibcon#flushed, iclass 13, count 0 2006.189.08:01:28.93#ibcon#about to write, iclass 13, count 0 2006.189.08:01:28.93#ibcon#wrote, iclass 13, count 0 2006.189.08:01:28.93#ibcon#about to read 3, iclass 13, count 0 2006.189.08:01:28.96#ibcon#read 3, iclass 13, count 0 2006.189.08:01:28.96#ibcon#about to read 4, iclass 13, count 0 2006.189.08:01:28.96#ibcon#read 4, iclass 13, count 0 2006.189.08:01:28.96#ibcon#about to read 5, iclass 13, count 0 2006.189.08:01:28.96#ibcon#read 5, iclass 13, count 0 2006.189.08:01:28.96#ibcon#about to read 6, iclass 13, count 0 2006.189.08:01:28.96#ibcon#read 6, iclass 13, count 0 2006.189.08:01:28.96#ibcon#end of sib2, iclass 13, count 0 2006.189.08:01:28.96#ibcon#*after write, iclass 13, count 0 2006.189.08:01:28.96#ibcon#*before return 0, iclass 13, count 0 2006.189.08:01:28.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:28.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:28.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:01:28.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:01:28.96$vc4f8/valo=4,832.99 2006.189.08:01:28.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.08:01:28.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.08:01:28.96#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:28.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:28.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:28.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:28.96#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:01:28.96#ibcon#first serial, iclass 15, count 0 2006.189.08:01:28.96#ibcon#enter sib2, iclass 15, count 0 2006.189.08:01:28.96#ibcon#flushed, iclass 15, count 0 2006.189.08:01:28.96#ibcon#about to write, iclass 15, count 0 2006.189.08:01:28.96#ibcon#wrote, iclass 15, count 0 2006.189.08:01:28.96#ibcon#about to read 3, iclass 15, count 0 2006.189.08:01:28.98#ibcon#read 3, iclass 15, count 0 2006.189.08:01:28.98#ibcon#about to read 4, iclass 15, count 0 2006.189.08:01:28.98#ibcon#read 4, iclass 15, count 0 2006.189.08:01:28.98#ibcon#about to read 5, iclass 15, count 0 2006.189.08:01:28.98#ibcon#read 5, iclass 15, count 0 2006.189.08:01:28.98#ibcon#about to read 6, iclass 15, count 0 2006.189.08:01:28.98#ibcon#read 6, iclass 15, count 0 2006.189.08:01:28.98#ibcon#end of sib2, iclass 15, count 0 2006.189.08:01:28.98#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:01:28.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:01:28.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:01:28.98#ibcon#*before write, iclass 15, count 0 2006.189.08:01:28.98#ibcon#enter sib2, iclass 15, count 0 2006.189.08:01:28.98#ibcon#flushed, iclass 15, count 0 2006.189.08:01:28.98#ibcon#about to write, iclass 15, count 0 2006.189.08:01:28.98#ibcon#wrote, iclass 15, count 0 2006.189.08:01:28.98#ibcon#about to read 3, iclass 15, count 0 2006.189.08:01:29.02#ibcon#read 3, iclass 15, count 0 2006.189.08:01:29.02#ibcon#about to read 4, iclass 15, count 0 2006.189.08:01:29.02#ibcon#read 4, iclass 15, count 0 2006.189.08:01:29.02#ibcon#about to read 5, iclass 15, count 0 2006.189.08:01:29.02#ibcon#read 5, iclass 15, count 0 2006.189.08:01:29.02#ibcon#about to read 6, iclass 15, count 0 2006.189.08:01:29.02#ibcon#read 6, iclass 15, count 0 2006.189.08:01:29.02#ibcon#end of sib2, iclass 15, count 0 2006.189.08:01:29.02#ibcon#*after write, iclass 15, count 0 2006.189.08:01:29.02#ibcon#*before return 0, iclass 15, count 0 2006.189.08:01:29.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:29.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:29.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:01:29.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:01:29.02$vc4f8/va=4,7 2006.189.08:01:29.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.08:01:29.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.08:01:29.02#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:29.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:29.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:29.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:29.08#ibcon#enter wrdev, iclass 17, count 2 2006.189.08:01:29.08#ibcon#first serial, iclass 17, count 2 2006.189.08:01:29.08#ibcon#enter sib2, iclass 17, count 2 2006.189.08:01:29.08#ibcon#flushed, iclass 17, count 2 2006.189.08:01:29.08#ibcon#about to write, iclass 17, count 2 2006.189.08:01:29.08#ibcon#wrote, iclass 17, count 2 2006.189.08:01:29.08#ibcon#about to read 3, iclass 17, count 2 2006.189.08:01:29.10#ibcon#read 3, iclass 17, count 2 2006.189.08:01:29.10#ibcon#about to read 4, iclass 17, count 2 2006.189.08:01:29.10#ibcon#read 4, iclass 17, count 2 2006.189.08:01:29.10#ibcon#about to read 5, iclass 17, count 2 2006.189.08:01:29.10#ibcon#read 5, iclass 17, count 2 2006.189.08:01:29.10#ibcon#about to read 6, iclass 17, count 2 2006.189.08:01:29.10#ibcon#read 6, iclass 17, count 2 2006.189.08:01:29.10#ibcon#end of sib2, iclass 17, count 2 2006.189.08:01:29.10#ibcon#*mode == 0, iclass 17, count 2 2006.189.08:01:29.10#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.08:01:29.10#ibcon#[25=AT04-07\r\n] 2006.189.08:01:29.10#ibcon#*before write, iclass 17, count 2 2006.189.08:01:29.10#ibcon#enter sib2, iclass 17, count 2 2006.189.08:01:29.10#ibcon#flushed, iclass 17, count 2 2006.189.08:01:29.10#ibcon#about to write, iclass 17, count 2 2006.189.08:01:29.10#ibcon#wrote, iclass 17, count 2 2006.189.08:01:29.10#ibcon#about to read 3, iclass 17, count 2 2006.189.08:01:29.13#ibcon#read 3, iclass 17, count 2 2006.189.08:01:29.13#ibcon#about to read 4, iclass 17, count 2 2006.189.08:01:29.13#ibcon#read 4, iclass 17, count 2 2006.189.08:01:29.13#ibcon#about to read 5, iclass 17, count 2 2006.189.08:01:29.13#ibcon#read 5, iclass 17, count 2 2006.189.08:01:29.13#ibcon#about to read 6, iclass 17, count 2 2006.189.08:01:29.13#ibcon#read 6, iclass 17, count 2 2006.189.08:01:29.13#ibcon#end of sib2, iclass 17, count 2 2006.189.08:01:29.13#ibcon#*after write, iclass 17, count 2 2006.189.08:01:29.13#ibcon#*before return 0, iclass 17, count 2 2006.189.08:01:29.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:29.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:29.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.08:01:29.13#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:29.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:29.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:29.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:29.25#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:01:29.25#ibcon#first serial, iclass 17, count 0 2006.189.08:01:29.25#ibcon#enter sib2, iclass 17, count 0 2006.189.08:01:29.25#ibcon#flushed, iclass 17, count 0 2006.189.08:01:29.25#ibcon#about to write, iclass 17, count 0 2006.189.08:01:29.25#ibcon#wrote, iclass 17, count 0 2006.189.08:01:29.25#ibcon#about to read 3, iclass 17, count 0 2006.189.08:01:29.27#ibcon#read 3, iclass 17, count 0 2006.189.08:01:29.27#ibcon#about to read 4, iclass 17, count 0 2006.189.08:01:29.27#ibcon#read 4, iclass 17, count 0 2006.189.08:01:29.27#ibcon#about to read 5, iclass 17, count 0 2006.189.08:01:29.27#ibcon#read 5, iclass 17, count 0 2006.189.08:01:29.27#ibcon#about to read 6, iclass 17, count 0 2006.189.08:01:29.27#ibcon#read 6, iclass 17, count 0 2006.189.08:01:29.27#ibcon#end of sib2, iclass 17, count 0 2006.189.08:01:29.27#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:01:29.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:01:29.27#ibcon#[25=USB\r\n] 2006.189.08:01:29.27#ibcon#*before write, iclass 17, count 0 2006.189.08:01:29.27#ibcon#enter sib2, iclass 17, count 0 2006.189.08:01:29.27#ibcon#flushed, iclass 17, count 0 2006.189.08:01:29.27#ibcon#about to write, iclass 17, count 0 2006.189.08:01:29.27#ibcon#wrote, iclass 17, count 0 2006.189.08:01:29.27#ibcon#about to read 3, iclass 17, count 0 2006.189.08:01:29.30#ibcon#read 3, iclass 17, count 0 2006.189.08:01:29.30#ibcon#about to read 4, iclass 17, count 0 2006.189.08:01:29.30#ibcon#read 4, iclass 17, count 0 2006.189.08:01:29.30#ibcon#about to read 5, iclass 17, count 0 2006.189.08:01:29.30#ibcon#read 5, iclass 17, count 0 2006.189.08:01:29.30#ibcon#about to read 6, iclass 17, count 0 2006.189.08:01:29.30#ibcon#read 6, iclass 17, count 0 2006.189.08:01:29.30#ibcon#end of sib2, iclass 17, count 0 2006.189.08:01:29.30#ibcon#*after write, iclass 17, count 0 2006.189.08:01:29.30#ibcon#*before return 0, iclass 17, count 0 2006.189.08:01:29.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:29.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:29.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:01:29.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:01:29.30$vc4f8/valo=5,652.99 2006.189.08:01:29.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.08:01:29.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.08:01:29.30#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:29.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:29.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:29.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:29.30#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:01:29.30#ibcon#first serial, iclass 19, count 0 2006.189.08:01:29.30#ibcon#enter sib2, iclass 19, count 0 2006.189.08:01:29.30#ibcon#flushed, iclass 19, count 0 2006.189.08:01:29.30#ibcon#about to write, iclass 19, count 0 2006.189.08:01:29.30#ibcon#wrote, iclass 19, count 0 2006.189.08:01:29.30#ibcon#about to read 3, iclass 19, count 0 2006.189.08:01:29.32#ibcon#read 3, iclass 19, count 0 2006.189.08:01:29.32#ibcon#about to read 4, iclass 19, count 0 2006.189.08:01:29.32#ibcon#read 4, iclass 19, count 0 2006.189.08:01:29.32#ibcon#about to read 5, iclass 19, count 0 2006.189.08:01:29.32#ibcon#read 5, iclass 19, count 0 2006.189.08:01:29.32#ibcon#about to read 6, iclass 19, count 0 2006.189.08:01:29.32#ibcon#read 6, iclass 19, count 0 2006.189.08:01:29.32#ibcon#end of sib2, iclass 19, count 0 2006.189.08:01:29.32#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:01:29.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:01:29.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:01:29.32#ibcon#*before write, iclass 19, count 0 2006.189.08:01:29.32#ibcon#enter sib2, iclass 19, count 0 2006.189.08:01:29.32#ibcon#flushed, iclass 19, count 0 2006.189.08:01:29.32#ibcon#about to write, iclass 19, count 0 2006.189.08:01:29.32#ibcon#wrote, iclass 19, count 0 2006.189.08:01:29.32#ibcon#about to read 3, iclass 19, count 0 2006.189.08:01:29.36#ibcon#read 3, iclass 19, count 0 2006.189.08:01:29.36#ibcon#about to read 4, iclass 19, count 0 2006.189.08:01:29.36#ibcon#read 4, iclass 19, count 0 2006.189.08:01:29.36#ibcon#about to read 5, iclass 19, count 0 2006.189.08:01:29.36#ibcon#read 5, iclass 19, count 0 2006.189.08:01:29.36#ibcon#about to read 6, iclass 19, count 0 2006.189.08:01:29.36#ibcon#read 6, iclass 19, count 0 2006.189.08:01:29.36#ibcon#end of sib2, iclass 19, count 0 2006.189.08:01:29.36#ibcon#*after write, iclass 19, count 0 2006.189.08:01:29.36#ibcon#*before return 0, iclass 19, count 0 2006.189.08:01:29.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:29.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:29.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:01:29.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:01:29.36$vc4f8/va=5,7 2006.189.08:01:29.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.08:01:29.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.08:01:29.36#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:29.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:29.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:29.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:29.42#ibcon#enter wrdev, iclass 21, count 2 2006.189.08:01:29.42#ibcon#first serial, iclass 21, count 2 2006.189.08:01:29.42#ibcon#enter sib2, iclass 21, count 2 2006.189.08:01:29.42#ibcon#flushed, iclass 21, count 2 2006.189.08:01:29.42#ibcon#about to write, iclass 21, count 2 2006.189.08:01:29.42#ibcon#wrote, iclass 21, count 2 2006.189.08:01:29.42#ibcon#about to read 3, iclass 21, count 2 2006.189.08:01:29.44#ibcon#read 3, iclass 21, count 2 2006.189.08:01:29.44#ibcon#about to read 4, iclass 21, count 2 2006.189.08:01:29.44#ibcon#read 4, iclass 21, count 2 2006.189.08:01:29.44#ibcon#about to read 5, iclass 21, count 2 2006.189.08:01:29.44#ibcon#read 5, iclass 21, count 2 2006.189.08:01:29.44#ibcon#about to read 6, iclass 21, count 2 2006.189.08:01:29.44#ibcon#read 6, iclass 21, count 2 2006.189.08:01:29.44#ibcon#end of sib2, iclass 21, count 2 2006.189.08:01:29.44#ibcon#*mode == 0, iclass 21, count 2 2006.189.08:01:29.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.08:01:29.44#ibcon#[25=AT05-07\r\n] 2006.189.08:01:29.44#ibcon#*before write, iclass 21, count 2 2006.189.08:01:29.44#ibcon#enter sib2, iclass 21, count 2 2006.189.08:01:29.44#ibcon#flushed, iclass 21, count 2 2006.189.08:01:29.44#ibcon#about to write, iclass 21, count 2 2006.189.08:01:29.44#ibcon#wrote, iclass 21, count 2 2006.189.08:01:29.44#ibcon#about to read 3, iclass 21, count 2 2006.189.08:01:29.47#ibcon#read 3, iclass 21, count 2 2006.189.08:01:29.47#ibcon#about to read 4, iclass 21, count 2 2006.189.08:01:29.47#ibcon#read 4, iclass 21, count 2 2006.189.08:01:29.47#ibcon#about to read 5, iclass 21, count 2 2006.189.08:01:29.47#ibcon#read 5, iclass 21, count 2 2006.189.08:01:29.47#ibcon#about to read 6, iclass 21, count 2 2006.189.08:01:29.47#ibcon#read 6, iclass 21, count 2 2006.189.08:01:29.47#ibcon#end of sib2, iclass 21, count 2 2006.189.08:01:29.47#ibcon#*after write, iclass 21, count 2 2006.189.08:01:29.47#ibcon#*before return 0, iclass 21, count 2 2006.189.08:01:29.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:29.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:29.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.08:01:29.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:29.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:29.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:29.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:29.59#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:01:29.59#ibcon#first serial, iclass 21, count 0 2006.189.08:01:29.59#ibcon#enter sib2, iclass 21, count 0 2006.189.08:01:29.59#ibcon#flushed, iclass 21, count 0 2006.189.08:01:29.59#ibcon#about to write, iclass 21, count 0 2006.189.08:01:29.59#ibcon#wrote, iclass 21, count 0 2006.189.08:01:29.59#ibcon#about to read 3, iclass 21, count 0 2006.189.08:01:29.61#ibcon#read 3, iclass 21, count 0 2006.189.08:01:29.61#ibcon#about to read 4, iclass 21, count 0 2006.189.08:01:29.61#ibcon#read 4, iclass 21, count 0 2006.189.08:01:29.61#ibcon#about to read 5, iclass 21, count 0 2006.189.08:01:29.61#ibcon#read 5, iclass 21, count 0 2006.189.08:01:29.61#ibcon#about to read 6, iclass 21, count 0 2006.189.08:01:29.61#ibcon#read 6, iclass 21, count 0 2006.189.08:01:29.61#ibcon#end of sib2, iclass 21, count 0 2006.189.08:01:29.61#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:01:29.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:01:29.61#ibcon#[25=USB\r\n] 2006.189.08:01:29.61#ibcon#*before write, iclass 21, count 0 2006.189.08:01:29.61#ibcon#enter sib2, iclass 21, count 0 2006.189.08:01:29.61#ibcon#flushed, iclass 21, count 0 2006.189.08:01:29.61#ibcon#about to write, iclass 21, count 0 2006.189.08:01:29.61#ibcon#wrote, iclass 21, count 0 2006.189.08:01:29.61#ibcon#about to read 3, iclass 21, count 0 2006.189.08:01:29.64#ibcon#read 3, iclass 21, count 0 2006.189.08:01:29.64#ibcon#about to read 4, iclass 21, count 0 2006.189.08:01:29.64#ibcon#read 4, iclass 21, count 0 2006.189.08:01:29.64#ibcon#about to read 5, iclass 21, count 0 2006.189.08:01:29.64#ibcon#read 5, iclass 21, count 0 2006.189.08:01:29.64#ibcon#about to read 6, iclass 21, count 0 2006.189.08:01:29.64#ibcon#read 6, iclass 21, count 0 2006.189.08:01:29.64#ibcon#end of sib2, iclass 21, count 0 2006.189.08:01:29.64#ibcon#*after write, iclass 21, count 0 2006.189.08:01:29.64#ibcon#*before return 0, iclass 21, count 0 2006.189.08:01:29.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:29.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:29.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:01:29.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:01:29.64$vc4f8/valo=6,772.99 2006.189.08:01:29.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.08:01:29.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.08:01:29.64#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:29.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:29.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:29.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:29.64#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:01:29.64#ibcon#first serial, iclass 23, count 0 2006.189.08:01:29.64#ibcon#enter sib2, iclass 23, count 0 2006.189.08:01:29.64#ibcon#flushed, iclass 23, count 0 2006.189.08:01:29.64#ibcon#about to write, iclass 23, count 0 2006.189.08:01:29.64#ibcon#wrote, iclass 23, count 0 2006.189.08:01:29.64#ibcon#about to read 3, iclass 23, count 0 2006.189.08:01:29.66#ibcon#read 3, iclass 23, count 0 2006.189.08:01:29.66#ibcon#about to read 4, iclass 23, count 0 2006.189.08:01:29.66#ibcon#read 4, iclass 23, count 0 2006.189.08:01:29.66#ibcon#about to read 5, iclass 23, count 0 2006.189.08:01:29.66#ibcon#read 5, iclass 23, count 0 2006.189.08:01:29.66#ibcon#about to read 6, iclass 23, count 0 2006.189.08:01:29.66#ibcon#read 6, iclass 23, count 0 2006.189.08:01:29.66#ibcon#end of sib2, iclass 23, count 0 2006.189.08:01:29.66#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:01:29.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:01:29.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:01:29.66#ibcon#*before write, iclass 23, count 0 2006.189.08:01:29.66#ibcon#enter sib2, iclass 23, count 0 2006.189.08:01:29.66#ibcon#flushed, iclass 23, count 0 2006.189.08:01:29.66#ibcon#about to write, iclass 23, count 0 2006.189.08:01:29.66#ibcon#wrote, iclass 23, count 0 2006.189.08:01:29.66#ibcon#about to read 3, iclass 23, count 0 2006.189.08:01:29.70#ibcon#read 3, iclass 23, count 0 2006.189.08:01:29.70#ibcon#about to read 4, iclass 23, count 0 2006.189.08:01:29.70#ibcon#read 4, iclass 23, count 0 2006.189.08:01:29.70#ibcon#about to read 5, iclass 23, count 0 2006.189.08:01:29.70#ibcon#read 5, iclass 23, count 0 2006.189.08:01:29.70#ibcon#about to read 6, iclass 23, count 0 2006.189.08:01:29.70#ibcon#read 6, iclass 23, count 0 2006.189.08:01:29.70#ibcon#end of sib2, iclass 23, count 0 2006.189.08:01:29.70#ibcon#*after write, iclass 23, count 0 2006.189.08:01:29.70#ibcon#*before return 0, iclass 23, count 0 2006.189.08:01:29.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:29.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:29.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:01:29.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:01:29.70$vc4f8/va=6,6 2006.189.08:01:29.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.08:01:29.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.08:01:29.70#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:29.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:29.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:29.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:29.76#ibcon#enter wrdev, iclass 25, count 2 2006.189.08:01:29.76#ibcon#first serial, iclass 25, count 2 2006.189.08:01:29.76#ibcon#enter sib2, iclass 25, count 2 2006.189.08:01:29.76#ibcon#flushed, iclass 25, count 2 2006.189.08:01:29.76#ibcon#about to write, iclass 25, count 2 2006.189.08:01:29.76#ibcon#wrote, iclass 25, count 2 2006.189.08:01:29.76#ibcon#about to read 3, iclass 25, count 2 2006.189.08:01:29.78#ibcon#read 3, iclass 25, count 2 2006.189.08:01:29.78#ibcon#about to read 4, iclass 25, count 2 2006.189.08:01:29.78#ibcon#read 4, iclass 25, count 2 2006.189.08:01:29.78#ibcon#about to read 5, iclass 25, count 2 2006.189.08:01:29.78#ibcon#read 5, iclass 25, count 2 2006.189.08:01:29.78#ibcon#about to read 6, iclass 25, count 2 2006.189.08:01:29.78#ibcon#read 6, iclass 25, count 2 2006.189.08:01:29.78#ibcon#end of sib2, iclass 25, count 2 2006.189.08:01:29.78#ibcon#*mode == 0, iclass 25, count 2 2006.189.08:01:29.78#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.08:01:29.78#ibcon#[25=AT06-06\r\n] 2006.189.08:01:29.78#ibcon#*before write, iclass 25, count 2 2006.189.08:01:29.78#ibcon#enter sib2, iclass 25, count 2 2006.189.08:01:29.78#ibcon#flushed, iclass 25, count 2 2006.189.08:01:29.78#ibcon#about to write, iclass 25, count 2 2006.189.08:01:29.78#ibcon#wrote, iclass 25, count 2 2006.189.08:01:29.78#ibcon#about to read 3, iclass 25, count 2 2006.189.08:01:29.81#ibcon#read 3, iclass 25, count 2 2006.189.08:01:29.81#ibcon#about to read 4, iclass 25, count 2 2006.189.08:01:29.81#ibcon#read 4, iclass 25, count 2 2006.189.08:01:29.81#ibcon#about to read 5, iclass 25, count 2 2006.189.08:01:29.81#ibcon#read 5, iclass 25, count 2 2006.189.08:01:29.81#ibcon#about to read 6, iclass 25, count 2 2006.189.08:01:29.81#ibcon#read 6, iclass 25, count 2 2006.189.08:01:29.81#ibcon#end of sib2, iclass 25, count 2 2006.189.08:01:29.81#ibcon#*after write, iclass 25, count 2 2006.189.08:01:29.81#ibcon#*before return 0, iclass 25, count 2 2006.189.08:01:29.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:29.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:29.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.08:01:29.81#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:29.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:29.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:29.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:29.93#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:01:29.93#ibcon#first serial, iclass 25, count 0 2006.189.08:01:29.93#ibcon#enter sib2, iclass 25, count 0 2006.189.08:01:29.93#ibcon#flushed, iclass 25, count 0 2006.189.08:01:29.93#ibcon#about to write, iclass 25, count 0 2006.189.08:01:29.93#ibcon#wrote, iclass 25, count 0 2006.189.08:01:29.93#ibcon#about to read 3, iclass 25, count 0 2006.189.08:01:29.95#ibcon#read 3, iclass 25, count 0 2006.189.08:01:29.95#ibcon#about to read 4, iclass 25, count 0 2006.189.08:01:29.95#ibcon#read 4, iclass 25, count 0 2006.189.08:01:29.95#ibcon#about to read 5, iclass 25, count 0 2006.189.08:01:29.95#ibcon#read 5, iclass 25, count 0 2006.189.08:01:29.95#ibcon#about to read 6, iclass 25, count 0 2006.189.08:01:29.95#ibcon#read 6, iclass 25, count 0 2006.189.08:01:29.95#ibcon#end of sib2, iclass 25, count 0 2006.189.08:01:29.95#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:01:29.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:01:29.95#ibcon#[25=USB\r\n] 2006.189.08:01:29.95#ibcon#*before write, iclass 25, count 0 2006.189.08:01:29.95#ibcon#enter sib2, iclass 25, count 0 2006.189.08:01:29.95#ibcon#flushed, iclass 25, count 0 2006.189.08:01:29.95#ibcon#about to write, iclass 25, count 0 2006.189.08:01:29.95#ibcon#wrote, iclass 25, count 0 2006.189.08:01:29.95#ibcon#about to read 3, iclass 25, count 0 2006.189.08:01:29.98#ibcon#read 3, iclass 25, count 0 2006.189.08:01:29.98#ibcon#about to read 4, iclass 25, count 0 2006.189.08:01:29.98#ibcon#read 4, iclass 25, count 0 2006.189.08:01:29.98#ibcon#about to read 5, iclass 25, count 0 2006.189.08:01:29.98#ibcon#read 5, iclass 25, count 0 2006.189.08:01:29.98#ibcon#about to read 6, iclass 25, count 0 2006.189.08:01:29.98#ibcon#read 6, iclass 25, count 0 2006.189.08:01:29.98#ibcon#end of sib2, iclass 25, count 0 2006.189.08:01:29.98#ibcon#*after write, iclass 25, count 0 2006.189.08:01:29.98#ibcon#*before return 0, iclass 25, count 0 2006.189.08:01:29.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:29.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:29.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:01:29.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:01:29.98$vc4f8/valo=7,832.99 2006.189.08:01:29.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.08:01:29.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.08:01:29.98#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:29.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:29.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:29.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:29.98#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:01:29.98#ibcon#first serial, iclass 27, count 0 2006.189.08:01:29.98#ibcon#enter sib2, iclass 27, count 0 2006.189.08:01:29.98#ibcon#flushed, iclass 27, count 0 2006.189.08:01:29.98#ibcon#about to write, iclass 27, count 0 2006.189.08:01:29.98#ibcon#wrote, iclass 27, count 0 2006.189.08:01:29.98#ibcon#about to read 3, iclass 27, count 0 2006.189.08:01:30.00#ibcon#read 3, iclass 27, count 0 2006.189.08:01:30.00#ibcon#about to read 4, iclass 27, count 0 2006.189.08:01:30.00#ibcon#read 4, iclass 27, count 0 2006.189.08:01:30.00#ibcon#about to read 5, iclass 27, count 0 2006.189.08:01:30.00#ibcon#read 5, iclass 27, count 0 2006.189.08:01:30.00#ibcon#about to read 6, iclass 27, count 0 2006.189.08:01:30.00#ibcon#read 6, iclass 27, count 0 2006.189.08:01:30.00#ibcon#end of sib2, iclass 27, count 0 2006.189.08:01:30.00#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:01:30.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:01:30.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:01:30.00#ibcon#*before write, iclass 27, count 0 2006.189.08:01:30.00#ibcon#enter sib2, iclass 27, count 0 2006.189.08:01:30.00#ibcon#flushed, iclass 27, count 0 2006.189.08:01:30.00#ibcon#about to write, iclass 27, count 0 2006.189.08:01:30.00#ibcon#wrote, iclass 27, count 0 2006.189.08:01:30.00#ibcon#about to read 3, iclass 27, count 0 2006.189.08:01:30.04#ibcon#read 3, iclass 27, count 0 2006.189.08:01:30.04#ibcon#about to read 4, iclass 27, count 0 2006.189.08:01:30.04#ibcon#read 4, iclass 27, count 0 2006.189.08:01:30.04#ibcon#about to read 5, iclass 27, count 0 2006.189.08:01:30.04#ibcon#read 5, iclass 27, count 0 2006.189.08:01:30.04#ibcon#about to read 6, iclass 27, count 0 2006.189.08:01:30.04#ibcon#read 6, iclass 27, count 0 2006.189.08:01:30.04#ibcon#end of sib2, iclass 27, count 0 2006.189.08:01:30.04#ibcon#*after write, iclass 27, count 0 2006.189.08:01:30.04#ibcon#*before return 0, iclass 27, count 0 2006.189.08:01:30.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:30.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:30.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:01:30.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:01:30.04$vc4f8/va=7,6 2006.189.08:01:30.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.08:01:30.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.08:01:30.04#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:30.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:01:30.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:01:30.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:01:30.10#ibcon#enter wrdev, iclass 29, count 2 2006.189.08:01:30.10#ibcon#first serial, iclass 29, count 2 2006.189.08:01:30.10#ibcon#enter sib2, iclass 29, count 2 2006.189.08:01:30.10#ibcon#flushed, iclass 29, count 2 2006.189.08:01:30.10#ibcon#about to write, iclass 29, count 2 2006.189.08:01:30.10#ibcon#wrote, iclass 29, count 2 2006.189.08:01:30.10#ibcon#about to read 3, iclass 29, count 2 2006.189.08:01:30.12#ibcon#read 3, iclass 29, count 2 2006.189.08:01:30.12#ibcon#about to read 4, iclass 29, count 2 2006.189.08:01:30.12#ibcon#read 4, iclass 29, count 2 2006.189.08:01:30.12#ibcon#about to read 5, iclass 29, count 2 2006.189.08:01:30.12#ibcon#read 5, iclass 29, count 2 2006.189.08:01:30.12#ibcon#about to read 6, iclass 29, count 2 2006.189.08:01:30.12#ibcon#read 6, iclass 29, count 2 2006.189.08:01:30.12#ibcon#end of sib2, iclass 29, count 2 2006.189.08:01:30.12#ibcon#*mode == 0, iclass 29, count 2 2006.189.08:01:30.12#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.08:01:30.12#ibcon#[25=AT07-06\r\n] 2006.189.08:01:30.12#ibcon#*before write, iclass 29, count 2 2006.189.08:01:30.12#ibcon#enter sib2, iclass 29, count 2 2006.189.08:01:30.12#ibcon#flushed, iclass 29, count 2 2006.189.08:01:30.12#ibcon#about to write, iclass 29, count 2 2006.189.08:01:30.12#ibcon#wrote, iclass 29, count 2 2006.189.08:01:30.12#ibcon#about to read 3, iclass 29, count 2 2006.189.08:01:30.15#ibcon#read 3, iclass 29, count 2 2006.189.08:01:30.15#ibcon#about to read 4, iclass 29, count 2 2006.189.08:01:30.15#ibcon#read 4, iclass 29, count 2 2006.189.08:01:30.15#ibcon#about to read 5, iclass 29, count 2 2006.189.08:01:30.15#ibcon#read 5, iclass 29, count 2 2006.189.08:01:30.15#ibcon#about to read 6, iclass 29, count 2 2006.189.08:01:30.15#ibcon#read 6, iclass 29, count 2 2006.189.08:01:30.15#ibcon#end of sib2, iclass 29, count 2 2006.189.08:01:30.15#ibcon#*after write, iclass 29, count 2 2006.189.08:01:30.15#ibcon#*before return 0, iclass 29, count 2 2006.189.08:01:30.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:01:30.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:01:30.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.08:01:30.15#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:30.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:01:30.27#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:01:30.27#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:01:30.27#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:01:30.27#ibcon#first serial, iclass 29, count 0 2006.189.08:01:30.27#ibcon#enter sib2, iclass 29, count 0 2006.189.08:01:30.27#ibcon#flushed, iclass 29, count 0 2006.189.08:01:30.27#ibcon#about to write, iclass 29, count 0 2006.189.08:01:30.27#ibcon#wrote, iclass 29, count 0 2006.189.08:01:30.27#ibcon#about to read 3, iclass 29, count 0 2006.189.08:01:30.29#ibcon#read 3, iclass 29, count 0 2006.189.08:01:30.29#ibcon#about to read 4, iclass 29, count 0 2006.189.08:01:30.29#ibcon#read 4, iclass 29, count 0 2006.189.08:01:30.29#ibcon#about to read 5, iclass 29, count 0 2006.189.08:01:30.29#ibcon#read 5, iclass 29, count 0 2006.189.08:01:30.29#ibcon#about to read 6, iclass 29, count 0 2006.189.08:01:30.29#ibcon#read 6, iclass 29, count 0 2006.189.08:01:30.29#ibcon#end of sib2, iclass 29, count 0 2006.189.08:01:30.29#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:01:30.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:01:30.29#ibcon#[25=USB\r\n] 2006.189.08:01:30.29#ibcon#*before write, iclass 29, count 0 2006.189.08:01:30.29#ibcon#enter sib2, iclass 29, count 0 2006.189.08:01:30.29#ibcon#flushed, iclass 29, count 0 2006.189.08:01:30.29#ibcon#about to write, iclass 29, count 0 2006.189.08:01:30.29#ibcon#wrote, iclass 29, count 0 2006.189.08:01:30.29#ibcon#about to read 3, iclass 29, count 0 2006.189.08:01:30.32#ibcon#read 3, iclass 29, count 0 2006.189.08:01:30.32#ibcon#about to read 4, iclass 29, count 0 2006.189.08:01:30.32#ibcon#read 4, iclass 29, count 0 2006.189.08:01:30.32#ibcon#about to read 5, iclass 29, count 0 2006.189.08:01:30.32#ibcon#read 5, iclass 29, count 0 2006.189.08:01:30.32#ibcon#about to read 6, iclass 29, count 0 2006.189.08:01:30.32#ibcon#read 6, iclass 29, count 0 2006.189.08:01:30.32#ibcon#end of sib2, iclass 29, count 0 2006.189.08:01:30.32#ibcon#*after write, iclass 29, count 0 2006.189.08:01:30.32#ibcon#*before return 0, iclass 29, count 0 2006.189.08:01:30.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:01:30.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:01:30.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:01:30.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:01:30.32$vc4f8/valo=8,852.99 2006.189.08:01:30.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.08:01:30.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.08:01:30.32#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:30.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:01:30.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:01:30.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:01:30.32#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:01:30.32#ibcon#first serial, iclass 31, count 0 2006.189.08:01:30.32#ibcon#enter sib2, iclass 31, count 0 2006.189.08:01:30.32#ibcon#flushed, iclass 31, count 0 2006.189.08:01:30.32#ibcon#about to write, iclass 31, count 0 2006.189.08:01:30.32#ibcon#wrote, iclass 31, count 0 2006.189.08:01:30.32#ibcon#about to read 3, iclass 31, count 0 2006.189.08:01:30.34#ibcon#read 3, iclass 31, count 0 2006.189.08:01:30.34#ibcon#about to read 4, iclass 31, count 0 2006.189.08:01:30.34#ibcon#read 4, iclass 31, count 0 2006.189.08:01:30.34#ibcon#about to read 5, iclass 31, count 0 2006.189.08:01:30.34#ibcon#read 5, iclass 31, count 0 2006.189.08:01:30.34#ibcon#about to read 6, iclass 31, count 0 2006.189.08:01:30.34#ibcon#read 6, iclass 31, count 0 2006.189.08:01:30.34#ibcon#end of sib2, iclass 31, count 0 2006.189.08:01:30.34#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:01:30.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:01:30.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:01:30.34#ibcon#*before write, iclass 31, count 0 2006.189.08:01:30.34#ibcon#enter sib2, iclass 31, count 0 2006.189.08:01:30.34#ibcon#flushed, iclass 31, count 0 2006.189.08:01:30.34#ibcon#about to write, iclass 31, count 0 2006.189.08:01:30.34#ibcon#wrote, iclass 31, count 0 2006.189.08:01:30.34#ibcon#about to read 3, iclass 31, count 0 2006.189.08:01:30.38#ibcon#read 3, iclass 31, count 0 2006.189.08:01:30.38#ibcon#about to read 4, iclass 31, count 0 2006.189.08:01:30.38#ibcon#read 4, iclass 31, count 0 2006.189.08:01:30.38#ibcon#about to read 5, iclass 31, count 0 2006.189.08:01:30.38#ibcon#read 5, iclass 31, count 0 2006.189.08:01:30.38#ibcon#about to read 6, iclass 31, count 0 2006.189.08:01:30.38#ibcon#read 6, iclass 31, count 0 2006.189.08:01:30.38#ibcon#end of sib2, iclass 31, count 0 2006.189.08:01:30.38#ibcon#*after write, iclass 31, count 0 2006.189.08:01:30.38#ibcon#*before return 0, iclass 31, count 0 2006.189.08:01:30.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:01:30.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:01:30.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:01:30.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:01:30.38$vc4f8/va=8,6 2006.189.08:01:30.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.08:01:30.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.08:01:30.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:30.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:01:30.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:01:30.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:01:30.44#ibcon#enter wrdev, iclass 33, count 2 2006.189.08:01:30.44#ibcon#first serial, iclass 33, count 2 2006.189.08:01:30.44#ibcon#enter sib2, iclass 33, count 2 2006.189.08:01:30.44#ibcon#flushed, iclass 33, count 2 2006.189.08:01:30.44#ibcon#about to write, iclass 33, count 2 2006.189.08:01:30.44#ibcon#wrote, iclass 33, count 2 2006.189.08:01:30.44#ibcon#about to read 3, iclass 33, count 2 2006.189.08:01:30.46#ibcon#read 3, iclass 33, count 2 2006.189.08:01:30.46#ibcon#about to read 4, iclass 33, count 2 2006.189.08:01:30.46#ibcon#read 4, iclass 33, count 2 2006.189.08:01:30.46#ibcon#about to read 5, iclass 33, count 2 2006.189.08:01:30.46#ibcon#read 5, iclass 33, count 2 2006.189.08:01:30.46#ibcon#about to read 6, iclass 33, count 2 2006.189.08:01:30.46#ibcon#read 6, iclass 33, count 2 2006.189.08:01:30.46#ibcon#end of sib2, iclass 33, count 2 2006.189.08:01:30.46#ibcon#*mode == 0, iclass 33, count 2 2006.189.08:01:30.46#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.08:01:30.46#ibcon#[25=AT08-06\r\n] 2006.189.08:01:30.46#ibcon#*before write, iclass 33, count 2 2006.189.08:01:30.46#ibcon#enter sib2, iclass 33, count 2 2006.189.08:01:30.46#ibcon#flushed, iclass 33, count 2 2006.189.08:01:30.46#ibcon#about to write, iclass 33, count 2 2006.189.08:01:30.46#ibcon#wrote, iclass 33, count 2 2006.189.08:01:30.46#ibcon#about to read 3, iclass 33, count 2 2006.189.08:01:30.49#ibcon#read 3, iclass 33, count 2 2006.189.08:01:30.49#ibcon#about to read 4, iclass 33, count 2 2006.189.08:01:30.49#ibcon#read 4, iclass 33, count 2 2006.189.08:01:30.49#ibcon#about to read 5, iclass 33, count 2 2006.189.08:01:30.49#ibcon#read 5, iclass 33, count 2 2006.189.08:01:30.49#ibcon#about to read 6, iclass 33, count 2 2006.189.08:01:30.49#ibcon#read 6, iclass 33, count 2 2006.189.08:01:30.49#ibcon#end of sib2, iclass 33, count 2 2006.189.08:01:30.49#ibcon#*after write, iclass 33, count 2 2006.189.08:01:30.49#ibcon#*before return 0, iclass 33, count 2 2006.189.08:01:30.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:01:30.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:01:30.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.08:01:30.49#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:30.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:01:30.51#abcon#<5=/04 4.0 7.5 25.69 901009.1\r\n> 2006.189.08:01:30.53#abcon#{5=INTERFACE CLEAR} 2006.189.08:01:30.59#abcon#[5=S1D000X0/0*\r\n] 2006.189.08:01:30.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:01:30.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:01:30.61#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:01:30.61#ibcon#first serial, iclass 33, count 0 2006.189.08:01:30.61#ibcon#enter sib2, iclass 33, count 0 2006.189.08:01:30.61#ibcon#flushed, iclass 33, count 0 2006.189.08:01:30.61#ibcon#about to write, iclass 33, count 0 2006.189.08:01:30.61#ibcon#wrote, iclass 33, count 0 2006.189.08:01:30.61#ibcon#about to read 3, iclass 33, count 0 2006.189.08:01:30.63#ibcon#read 3, iclass 33, count 0 2006.189.08:01:30.63#ibcon#about to read 4, iclass 33, count 0 2006.189.08:01:30.63#ibcon#read 4, iclass 33, count 0 2006.189.08:01:30.63#ibcon#about to read 5, iclass 33, count 0 2006.189.08:01:30.63#ibcon#read 5, iclass 33, count 0 2006.189.08:01:30.63#ibcon#about to read 6, iclass 33, count 0 2006.189.08:01:30.63#ibcon#read 6, iclass 33, count 0 2006.189.08:01:30.63#ibcon#end of sib2, iclass 33, count 0 2006.189.08:01:30.63#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:01:30.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:01:30.63#ibcon#[25=USB\r\n] 2006.189.08:01:30.63#ibcon#*before write, iclass 33, count 0 2006.189.08:01:30.63#ibcon#enter sib2, iclass 33, count 0 2006.189.08:01:30.63#ibcon#flushed, iclass 33, count 0 2006.189.08:01:30.63#ibcon#about to write, iclass 33, count 0 2006.189.08:01:30.63#ibcon#wrote, iclass 33, count 0 2006.189.08:01:30.63#ibcon#about to read 3, iclass 33, count 0 2006.189.08:01:30.66#ibcon#read 3, iclass 33, count 0 2006.189.08:01:30.66#ibcon#about to read 4, iclass 33, count 0 2006.189.08:01:30.66#ibcon#read 4, iclass 33, count 0 2006.189.08:01:30.66#ibcon#about to read 5, iclass 33, count 0 2006.189.08:01:30.66#ibcon#read 5, iclass 33, count 0 2006.189.08:01:30.66#ibcon#about to read 6, iclass 33, count 0 2006.189.08:01:30.66#ibcon#read 6, iclass 33, count 0 2006.189.08:01:30.66#ibcon#end of sib2, iclass 33, count 0 2006.189.08:01:30.66#ibcon#*after write, iclass 33, count 0 2006.189.08:01:30.66#ibcon#*before return 0, iclass 33, count 0 2006.189.08:01:30.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:01:30.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:01:30.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:01:30.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:01:30.66$vc4f8/vblo=1,632.99 2006.189.08:01:30.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.08:01:30.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.08:01:30.66#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:30.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:30.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:30.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:30.66#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:01:30.66#ibcon#first serial, iclass 39, count 0 2006.189.08:01:30.66#ibcon#enter sib2, iclass 39, count 0 2006.189.08:01:30.66#ibcon#flushed, iclass 39, count 0 2006.189.08:01:30.66#ibcon#about to write, iclass 39, count 0 2006.189.08:01:30.66#ibcon#wrote, iclass 39, count 0 2006.189.08:01:30.66#ibcon#about to read 3, iclass 39, count 0 2006.189.08:01:30.68#ibcon#read 3, iclass 39, count 0 2006.189.08:01:30.68#ibcon#about to read 4, iclass 39, count 0 2006.189.08:01:30.68#ibcon#read 4, iclass 39, count 0 2006.189.08:01:30.68#ibcon#about to read 5, iclass 39, count 0 2006.189.08:01:30.68#ibcon#read 5, iclass 39, count 0 2006.189.08:01:30.68#ibcon#about to read 6, iclass 39, count 0 2006.189.08:01:30.68#ibcon#read 6, iclass 39, count 0 2006.189.08:01:30.68#ibcon#end of sib2, iclass 39, count 0 2006.189.08:01:30.68#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:01:30.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:01:30.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:01:30.68#ibcon#*before write, iclass 39, count 0 2006.189.08:01:30.68#ibcon#enter sib2, iclass 39, count 0 2006.189.08:01:30.68#ibcon#flushed, iclass 39, count 0 2006.189.08:01:30.68#ibcon#about to write, iclass 39, count 0 2006.189.08:01:30.68#ibcon#wrote, iclass 39, count 0 2006.189.08:01:30.68#ibcon#about to read 3, iclass 39, count 0 2006.189.08:01:30.72#ibcon#read 3, iclass 39, count 0 2006.189.08:01:30.72#ibcon#about to read 4, iclass 39, count 0 2006.189.08:01:30.72#ibcon#read 4, iclass 39, count 0 2006.189.08:01:30.72#ibcon#about to read 5, iclass 39, count 0 2006.189.08:01:30.72#ibcon#read 5, iclass 39, count 0 2006.189.08:01:30.72#ibcon#about to read 6, iclass 39, count 0 2006.189.08:01:30.72#ibcon#read 6, iclass 39, count 0 2006.189.08:01:30.72#ibcon#end of sib2, iclass 39, count 0 2006.189.08:01:30.72#ibcon#*after write, iclass 39, count 0 2006.189.08:01:30.72#ibcon#*before return 0, iclass 39, count 0 2006.189.08:01:30.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:30.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:01:30.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:01:30.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:01:30.72$vc4f8/vb=1,4 2006.189.08:01:30.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.08:01:30.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.08:01:30.72#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:30.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:30.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:30.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:30.72#ibcon#enter wrdev, iclass 3, count 2 2006.189.08:01:30.72#ibcon#first serial, iclass 3, count 2 2006.189.08:01:30.72#ibcon#enter sib2, iclass 3, count 2 2006.189.08:01:30.72#ibcon#flushed, iclass 3, count 2 2006.189.08:01:30.72#ibcon#about to write, iclass 3, count 2 2006.189.08:01:30.72#ibcon#wrote, iclass 3, count 2 2006.189.08:01:30.72#ibcon#about to read 3, iclass 3, count 2 2006.189.08:01:30.74#ibcon#read 3, iclass 3, count 2 2006.189.08:01:30.74#ibcon#about to read 4, iclass 3, count 2 2006.189.08:01:30.74#ibcon#read 4, iclass 3, count 2 2006.189.08:01:30.74#ibcon#about to read 5, iclass 3, count 2 2006.189.08:01:30.74#ibcon#read 5, iclass 3, count 2 2006.189.08:01:30.74#ibcon#about to read 6, iclass 3, count 2 2006.189.08:01:30.74#ibcon#read 6, iclass 3, count 2 2006.189.08:01:30.74#ibcon#end of sib2, iclass 3, count 2 2006.189.08:01:30.74#ibcon#*mode == 0, iclass 3, count 2 2006.189.08:01:30.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.08:01:30.74#ibcon#[27=AT01-04\r\n] 2006.189.08:01:30.74#ibcon#*before write, iclass 3, count 2 2006.189.08:01:30.74#ibcon#enter sib2, iclass 3, count 2 2006.189.08:01:30.74#ibcon#flushed, iclass 3, count 2 2006.189.08:01:30.74#ibcon#about to write, iclass 3, count 2 2006.189.08:01:30.74#ibcon#wrote, iclass 3, count 2 2006.189.08:01:30.74#ibcon#about to read 3, iclass 3, count 2 2006.189.08:01:30.77#ibcon#read 3, iclass 3, count 2 2006.189.08:01:30.77#ibcon#about to read 4, iclass 3, count 2 2006.189.08:01:30.77#ibcon#read 4, iclass 3, count 2 2006.189.08:01:30.77#ibcon#about to read 5, iclass 3, count 2 2006.189.08:01:30.77#ibcon#read 5, iclass 3, count 2 2006.189.08:01:30.77#ibcon#about to read 6, iclass 3, count 2 2006.189.08:01:30.77#ibcon#read 6, iclass 3, count 2 2006.189.08:01:30.77#ibcon#end of sib2, iclass 3, count 2 2006.189.08:01:30.77#ibcon#*after write, iclass 3, count 2 2006.189.08:01:30.77#ibcon#*before return 0, iclass 3, count 2 2006.189.08:01:30.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:30.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:01:30.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.08:01:30.77#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:30.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:30.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:30.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:30.89#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:01:30.89#ibcon#first serial, iclass 3, count 0 2006.189.08:01:30.89#ibcon#enter sib2, iclass 3, count 0 2006.189.08:01:30.89#ibcon#flushed, iclass 3, count 0 2006.189.08:01:30.89#ibcon#about to write, iclass 3, count 0 2006.189.08:01:30.89#ibcon#wrote, iclass 3, count 0 2006.189.08:01:30.89#ibcon#about to read 3, iclass 3, count 0 2006.189.08:01:30.91#ibcon#read 3, iclass 3, count 0 2006.189.08:01:30.91#ibcon#about to read 4, iclass 3, count 0 2006.189.08:01:30.91#ibcon#read 4, iclass 3, count 0 2006.189.08:01:30.91#ibcon#about to read 5, iclass 3, count 0 2006.189.08:01:30.91#ibcon#read 5, iclass 3, count 0 2006.189.08:01:30.91#ibcon#about to read 6, iclass 3, count 0 2006.189.08:01:30.91#ibcon#read 6, iclass 3, count 0 2006.189.08:01:30.91#ibcon#end of sib2, iclass 3, count 0 2006.189.08:01:30.91#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:01:30.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:01:30.91#ibcon#[27=USB\r\n] 2006.189.08:01:30.91#ibcon#*before write, iclass 3, count 0 2006.189.08:01:30.91#ibcon#enter sib2, iclass 3, count 0 2006.189.08:01:30.91#ibcon#flushed, iclass 3, count 0 2006.189.08:01:30.91#ibcon#about to write, iclass 3, count 0 2006.189.08:01:30.91#ibcon#wrote, iclass 3, count 0 2006.189.08:01:30.91#ibcon#about to read 3, iclass 3, count 0 2006.189.08:01:30.94#ibcon#read 3, iclass 3, count 0 2006.189.08:01:30.94#ibcon#about to read 4, iclass 3, count 0 2006.189.08:01:30.94#ibcon#read 4, iclass 3, count 0 2006.189.08:01:30.94#ibcon#about to read 5, iclass 3, count 0 2006.189.08:01:30.94#ibcon#read 5, iclass 3, count 0 2006.189.08:01:30.94#ibcon#about to read 6, iclass 3, count 0 2006.189.08:01:30.94#ibcon#read 6, iclass 3, count 0 2006.189.08:01:30.94#ibcon#end of sib2, iclass 3, count 0 2006.189.08:01:30.94#ibcon#*after write, iclass 3, count 0 2006.189.08:01:30.94#ibcon#*before return 0, iclass 3, count 0 2006.189.08:01:30.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:30.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:01:30.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:01:30.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:01:30.94$vc4f8/vblo=2,640.99 2006.189.08:01:30.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.08:01:30.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.08:01:30.94#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:30.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:30.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:30.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:30.94#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:01:30.94#ibcon#first serial, iclass 5, count 0 2006.189.08:01:30.94#ibcon#enter sib2, iclass 5, count 0 2006.189.08:01:30.94#ibcon#flushed, iclass 5, count 0 2006.189.08:01:30.94#ibcon#about to write, iclass 5, count 0 2006.189.08:01:30.94#ibcon#wrote, iclass 5, count 0 2006.189.08:01:30.94#ibcon#about to read 3, iclass 5, count 0 2006.189.08:01:30.96#ibcon#read 3, iclass 5, count 0 2006.189.08:01:30.96#ibcon#about to read 4, iclass 5, count 0 2006.189.08:01:30.96#ibcon#read 4, iclass 5, count 0 2006.189.08:01:30.96#ibcon#about to read 5, iclass 5, count 0 2006.189.08:01:30.96#ibcon#read 5, iclass 5, count 0 2006.189.08:01:30.96#ibcon#about to read 6, iclass 5, count 0 2006.189.08:01:30.96#ibcon#read 6, iclass 5, count 0 2006.189.08:01:30.96#ibcon#end of sib2, iclass 5, count 0 2006.189.08:01:30.96#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:01:30.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:01:30.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:01:30.96#ibcon#*before write, iclass 5, count 0 2006.189.08:01:30.96#ibcon#enter sib2, iclass 5, count 0 2006.189.08:01:30.96#ibcon#flushed, iclass 5, count 0 2006.189.08:01:30.96#ibcon#about to write, iclass 5, count 0 2006.189.08:01:30.96#ibcon#wrote, iclass 5, count 0 2006.189.08:01:30.96#ibcon#about to read 3, iclass 5, count 0 2006.189.08:01:31.00#ibcon#read 3, iclass 5, count 0 2006.189.08:01:31.00#ibcon#about to read 4, iclass 5, count 0 2006.189.08:01:31.00#ibcon#read 4, iclass 5, count 0 2006.189.08:01:31.00#ibcon#about to read 5, iclass 5, count 0 2006.189.08:01:31.00#ibcon#read 5, iclass 5, count 0 2006.189.08:01:31.00#ibcon#about to read 6, iclass 5, count 0 2006.189.08:01:31.00#ibcon#read 6, iclass 5, count 0 2006.189.08:01:31.00#ibcon#end of sib2, iclass 5, count 0 2006.189.08:01:31.00#ibcon#*after write, iclass 5, count 0 2006.189.08:01:31.00#ibcon#*before return 0, iclass 5, count 0 2006.189.08:01:31.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:31.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:01:31.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:01:31.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:01:31.00$vc4f8/vb=2,4 2006.189.08:01:31.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.08:01:31.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.08:01:31.00#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:31.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:31.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:31.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:31.06#ibcon#enter wrdev, iclass 7, count 2 2006.189.08:01:31.06#ibcon#first serial, iclass 7, count 2 2006.189.08:01:31.06#ibcon#enter sib2, iclass 7, count 2 2006.189.08:01:31.06#ibcon#flushed, iclass 7, count 2 2006.189.08:01:31.06#ibcon#about to write, iclass 7, count 2 2006.189.08:01:31.06#ibcon#wrote, iclass 7, count 2 2006.189.08:01:31.06#ibcon#about to read 3, iclass 7, count 2 2006.189.08:01:31.08#ibcon#read 3, iclass 7, count 2 2006.189.08:01:31.08#ibcon#about to read 4, iclass 7, count 2 2006.189.08:01:31.08#ibcon#read 4, iclass 7, count 2 2006.189.08:01:31.08#ibcon#about to read 5, iclass 7, count 2 2006.189.08:01:31.08#ibcon#read 5, iclass 7, count 2 2006.189.08:01:31.08#ibcon#about to read 6, iclass 7, count 2 2006.189.08:01:31.08#ibcon#read 6, iclass 7, count 2 2006.189.08:01:31.08#ibcon#end of sib2, iclass 7, count 2 2006.189.08:01:31.08#ibcon#*mode == 0, iclass 7, count 2 2006.189.08:01:31.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.08:01:31.08#ibcon#[27=AT02-04\r\n] 2006.189.08:01:31.08#ibcon#*before write, iclass 7, count 2 2006.189.08:01:31.08#ibcon#enter sib2, iclass 7, count 2 2006.189.08:01:31.08#ibcon#flushed, iclass 7, count 2 2006.189.08:01:31.08#ibcon#about to write, iclass 7, count 2 2006.189.08:01:31.08#ibcon#wrote, iclass 7, count 2 2006.189.08:01:31.08#ibcon#about to read 3, iclass 7, count 2 2006.189.08:01:31.11#ibcon#read 3, iclass 7, count 2 2006.189.08:01:31.11#ibcon#about to read 4, iclass 7, count 2 2006.189.08:01:31.11#ibcon#read 4, iclass 7, count 2 2006.189.08:01:31.11#ibcon#about to read 5, iclass 7, count 2 2006.189.08:01:31.11#ibcon#read 5, iclass 7, count 2 2006.189.08:01:31.11#ibcon#about to read 6, iclass 7, count 2 2006.189.08:01:31.11#ibcon#read 6, iclass 7, count 2 2006.189.08:01:31.11#ibcon#end of sib2, iclass 7, count 2 2006.189.08:01:31.11#ibcon#*after write, iclass 7, count 2 2006.189.08:01:31.11#ibcon#*before return 0, iclass 7, count 2 2006.189.08:01:31.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:31.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:01:31.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.08:01:31.11#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:31.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:31.23#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:31.23#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:31.23#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:01:31.23#ibcon#first serial, iclass 7, count 0 2006.189.08:01:31.23#ibcon#enter sib2, iclass 7, count 0 2006.189.08:01:31.23#ibcon#flushed, iclass 7, count 0 2006.189.08:01:31.23#ibcon#about to write, iclass 7, count 0 2006.189.08:01:31.23#ibcon#wrote, iclass 7, count 0 2006.189.08:01:31.23#ibcon#about to read 3, iclass 7, count 0 2006.189.08:01:31.25#ibcon#read 3, iclass 7, count 0 2006.189.08:01:31.25#ibcon#about to read 4, iclass 7, count 0 2006.189.08:01:31.25#ibcon#read 4, iclass 7, count 0 2006.189.08:01:31.25#ibcon#about to read 5, iclass 7, count 0 2006.189.08:01:31.25#ibcon#read 5, iclass 7, count 0 2006.189.08:01:31.25#ibcon#about to read 6, iclass 7, count 0 2006.189.08:01:31.25#ibcon#read 6, iclass 7, count 0 2006.189.08:01:31.25#ibcon#end of sib2, iclass 7, count 0 2006.189.08:01:31.25#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:01:31.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:01:31.25#ibcon#[27=USB\r\n] 2006.189.08:01:31.25#ibcon#*before write, iclass 7, count 0 2006.189.08:01:31.25#ibcon#enter sib2, iclass 7, count 0 2006.189.08:01:31.25#ibcon#flushed, iclass 7, count 0 2006.189.08:01:31.25#ibcon#about to write, iclass 7, count 0 2006.189.08:01:31.25#ibcon#wrote, iclass 7, count 0 2006.189.08:01:31.25#ibcon#about to read 3, iclass 7, count 0 2006.189.08:01:31.28#ibcon#read 3, iclass 7, count 0 2006.189.08:01:31.28#ibcon#about to read 4, iclass 7, count 0 2006.189.08:01:31.28#ibcon#read 4, iclass 7, count 0 2006.189.08:01:31.28#ibcon#about to read 5, iclass 7, count 0 2006.189.08:01:31.28#ibcon#read 5, iclass 7, count 0 2006.189.08:01:31.28#ibcon#about to read 6, iclass 7, count 0 2006.189.08:01:31.28#ibcon#read 6, iclass 7, count 0 2006.189.08:01:31.28#ibcon#end of sib2, iclass 7, count 0 2006.189.08:01:31.28#ibcon#*after write, iclass 7, count 0 2006.189.08:01:31.28#ibcon#*before return 0, iclass 7, count 0 2006.189.08:01:31.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:31.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:01:31.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:01:31.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:01:31.28$vc4f8/vblo=3,656.99 2006.189.08:01:31.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.08:01:31.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.08:01:31.28#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:31.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:31.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:31.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:31.28#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:01:31.28#ibcon#first serial, iclass 11, count 0 2006.189.08:01:31.28#ibcon#enter sib2, iclass 11, count 0 2006.189.08:01:31.28#ibcon#flushed, iclass 11, count 0 2006.189.08:01:31.28#ibcon#about to write, iclass 11, count 0 2006.189.08:01:31.28#ibcon#wrote, iclass 11, count 0 2006.189.08:01:31.28#ibcon#about to read 3, iclass 11, count 0 2006.189.08:01:31.30#ibcon#read 3, iclass 11, count 0 2006.189.08:01:31.30#ibcon#about to read 4, iclass 11, count 0 2006.189.08:01:31.30#ibcon#read 4, iclass 11, count 0 2006.189.08:01:31.30#ibcon#about to read 5, iclass 11, count 0 2006.189.08:01:31.30#ibcon#read 5, iclass 11, count 0 2006.189.08:01:31.30#ibcon#about to read 6, iclass 11, count 0 2006.189.08:01:31.30#ibcon#read 6, iclass 11, count 0 2006.189.08:01:31.30#ibcon#end of sib2, iclass 11, count 0 2006.189.08:01:31.30#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:01:31.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:01:31.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:01:31.30#ibcon#*before write, iclass 11, count 0 2006.189.08:01:31.30#ibcon#enter sib2, iclass 11, count 0 2006.189.08:01:31.30#ibcon#flushed, iclass 11, count 0 2006.189.08:01:31.30#ibcon#about to write, iclass 11, count 0 2006.189.08:01:31.30#ibcon#wrote, iclass 11, count 0 2006.189.08:01:31.30#ibcon#about to read 3, iclass 11, count 0 2006.189.08:01:31.34#ibcon#read 3, iclass 11, count 0 2006.189.08:01:31.34#ibcon#about to read 4, iclass 11, count 0 2006.189.08:01:31.34#ibcon#read 4, iclass 11, count 0 2006.189.08:01:31.34#ibcon#about to read 5, iclass 11, count 0 2006.189.08:01:31.34#ibcon#read 5, iclass 11, count 0 2006.189.08:01:31.34#ibcon#about to read 6, iclass 11, count 0 2006.189.08:01:31.34#ibcon#read 6, iclass 11, count 0 2006.189.08:01:31.34#ibcon#end of sib2, iclass 11, count 0 2006.189.08:01:31.34#ibcon#*after write, iclass 11, count 0 2006.189.08:01:31.34#ibcon#*before return 0, iclass 11, count 0 2006.189.08:01:31.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:31.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:01:31.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:01:31.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:01:31.34$vc4f8/vb=3,4 2006.189.08:01:31.34#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.08:01:31.34#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.08:01:31.34#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:31.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:31.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:31.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:31.40#ibcon#enter wrdev, iclass 13, count 2 2006.189.08:01:31.40#ibcon#first serial, iclass 13, count 2 2006.189.08:01:31.40#ibcon#enter sib2, iclass 13, count 2 2006.189.08:01:31.40#ibcon#flushed, iclass 13, count 2 2006.189.08:01:31.40#ibcon#about to write, iclass 13, count 2 2006.189.08:01:31.40#ibcon#wrote, iclass 13, count 2 2006.189.08:01:31.40#ibcon#about to read 3, iclass 13, count 2 2006.189.08:01:31.42#ibcon#read 3, iclass 13, count 2 2006.189.08:01:31.42#ibcon#about to read 4, iclass 13, count 2 2006.189.08:01:31.42#ibcon#read 4, iclass 13, count 2 2006.189.08:01:31.42#ibcon#about to read 5, iclass 13, count 2 2006.189.08:01:31.42#ibcon#read 5, iclass 13, count 2 2006.189.08:01:31.42#ibcon#about to read 6, iclass 13, count 2 2006.189.08:01:31.42#ibcon#read 6, iclass 13, count 2 2006.189.08:01:31.42#ibcon#end of sib2, iclass 13, count 2 2006.189.08:01:31.42#ibcon#*mode == 0, iclass 13, count 2 2006.189.08:01:31.42#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.08:01:31.42#ibcon#[27=AT03-04\r\n] 2006.189.08:01:31.42#ibcon#*before write, iclass 13, count 2 2006.189.08:01:31.42#ibcon#enter sib2, iclass 13, count 2 2006.189.08:01:31.42#ibcon#flushed, iclass 13, count 2 2006.189.08:01:31.42#ibcon#about to write, iclass 13, count 2 2006.189.08:01:31.42#ibcon#wrote, iclass 13, count 2 2006.189.08:01:31.42#ibcon#about to read 3, iclass 13, count 2 2006.189.08:01:31.45#ibcon#read 3, iclass 13, count 2 2006.189.08:01:31.45#ibcon#about to read 4, iclass 13, count 2 2006.189.08:01:31.45#ibcon#read 4, iclass 13, count 2 2006.189.08:01:31.45#ibcon#about to read 5, iclass 13, count 2 2006.189.08:01:31.45#ibcon#read 5, iclass 13, count 2 2006.189.08:01:31.45#ibcon#about to read 6, iclass 13, count 2 2006.189.08:01:31.45#ibcon#read 6, iclass 13, count 2 2006.189.08:01:31.45#ibcon#end of sib2, iclass 13, count 2 2006.189.08:01:31.45#ibcon#*after write, iclass 13, count 2 2006.189.08:01:31.45#ibcon#*before return 0, iclass 13, count 2 2006.189.08:01:31.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:31.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:01:31.45#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.08:01:31.45#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:31.45#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:31.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:31.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:31.57#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:01:31.57#ibcon#first serial, iclass 13, count 0 2006.189.08:01:31.57#ibcon#enter sib2, iclass 13, count 0 2006.189.08:01:31.57#ibcon#flushed, iclass 13, count 0 2006.189.08:01:31.57#ibcon#about to write, iclass 13, count 0 2006.189.08:01:31.57#ibcon#wrote, iclass 13, count 0 2006.189.08:01:31.57#ibcon#about to read 3, iclass 13, count 0 2006.189.08:01:31.59#ibcon#read 3, iclass 13, count 0 2006.189.08:01:31.59#ibcon#about to read 4, iclass 13, count 0 2006.189.08:01:31.59#ibcon#read 4, iclass 13, count 0 2006.189.08:01:31.59#ibcon#about to read 5, iclass 13, count 0 2006.189.08:01:31.59#ibcon#read 5, iclass 13, count 0 2006.189.08:01:31.59#ibcon#about to read 6, iclass 13, count 0 2006.189.08:01:31.59#ibcon#read 6, iclass 13, count 0 2006.189.08:01:31.59#ibcon#end of sib2, iclass 13, count 0 2006.189.08:01:31.59#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:01:31.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:01:31.59#ibcon#[27=USB\r\n] 2006.189.08:01:31.59#ibcon#*before write, iclass 13, count 0 2006.189.08:01:31.59#ibcon#enter sib2, iclass 13, count 0 2006.189.08:01:31.59#ibcon#flushed, iclass 13, count 0 2006.189.08:01:31.59#ibcon#about to write, iclass 13, count 0 2006.189.08:01:31.59#ibcon#wrote, iclass 13, count 0 2006.189.08:01:31.59#ibcon#about to read 3, iclass 13, count 0 2006.189.08:01:31.62#ibcon#read 3, iclass 13, count 0 2006.189.08:01:31.62#ibcon#about to read 4, iclass 13, count 0 2006.189.08:01:31.62#ibcon#read 4, iclass 13, count 0 2006.189.08:01:31.62#ibcon#about to read 5, iclass 13, count 0 2006.189.08:01:31.62#ibcon#read 5, iclass 13, count 0 2006.189.08:01:31.62#ibcon#about to read 6, iclass 13, count 0 2006.189.08:01:31.62#ibcon#read 6, iclass 13, count 0 2006.189.08:01:31.62#ibcon#end of sib2, iclass 13, count 0 2006.189.08:01:31.62#ibcon#*after write, iclass 13, count 0 2006.189.08:01:31.62#ibcon#*before return 0, iclass 13, count 0 2006.189.08:01:31.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:31.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:01:31.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:01:31.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:01:31.62$vc4f8/vblo=4,712.99 2006.189.08:01:31.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.08:01:31.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.08:01:31.62#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:31.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:31.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:31.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:31.62#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:01:31.62#ibcon#first serial, iclass 15, count 0 2006.189.08:01:31.62#ibcon#enter sib2, iclass 15, count 0 2006.189.08:01:31.62#ibcon#flushed, iclass 15, count 0 2006.189.08:01:31.62#ibcon#about to write, iclass 15, count 0 2006.189.08:01:31.62#ibcon#wrote, iclass 15, count 0 2006.189.08:01:31.62#ibcon#about to read 3, iclass 15, count 0 2006.189.08:01:31.64#ibcon#read 3, iclass 15, count 0 2006.189.08:01:31.64#ibcon#about to read 4, iclass 15, count 0 2006.189.08:01:31.64#ibcon#read 4, iclass 15, count 0 2006.189.08:01:31.64#ibcon#about to read 5, iclass 15, count 0 2006.189.08:01:31.64#ibcon#read 5, iclass 15, count 0 2006.189.08:01:31.64#ibcon#about to read 6, iclass 15, count 0 2006.189.08:01:31.64#ibcon#read 6, iclass 15, count 0 2006.189.08:01:31.64#ibcon#end of sib2, iclass 15, count 0 2006.189.08:01:31.64#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:01:31.64#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:01:31.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:01:31.64#ibcon#*before write, iclass 15, count 0 2006.189.08:01:31.64#ibcon#enter sib2, iclass 15, count 0 2006.189.08:01:31.64#ibcon#flushed, iclass 15, count 0 2006.189.08:01:31.64#ibcon#about to write, iclass 15, count 0 2006.189.08:01:31.64#ibcon#wrote, iclass 15, count 0 2006.189.08:01:31.64#ibcon#about to read 3, iclass 15, count 0 2006.189.08:01:31.68#ibcon#read 3, iclass 15, count 0 2006.189.08:01:31.68#ibcon#about to read 4, iclass 15, count 0 2006.189.08:01:31.68#ibcon#read 4, iclass 15, count 0 2006.189.08:01:31.68#ibcon#about to read 5, iclass 15, count 0 2006.189.08:01:31.68#ibcon#read 5, iclass 15, count 0 2006.189.08:01:31.68#ibcon#about to read 6, iclass 15, count 0 2006.189.08:01:31.68#ibcon#read 6, iclass 15, count 0 2006.189.08:01:31.68#ibcon#end of sib2, iclass 15, count 0 2006.189.08:01:31.68#ibcon#*after write, iclass 15, count 0 2006.189.08:01:31.68#ibcon#*before return 0, iclass 15, count 0 2006.189.08:01:31.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:31.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:01:31.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:01:31.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:01:31.68$vc4f8/vb=4,4 2006.189.08:01:31.68#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.08:01:31.68#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.08:01:31.68#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:31.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:31.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:31.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:31.74#ibcon#enter wrdev, iclass 17, count 2 2006.189.08:01:31.74#ibcon#first serial, iclass 17, count 2 2006.189.08:01:31.74#ibcon#enter sib2, iclass 17, count 2 2006.189.08:01:31.74#ibcon#flushed, iclass 17, count 2 2006.189.08:01:31.74#ibcon#about to write, iclass 17, count 2 2006.189.08:01:31.74#ibcon#wrote, iclass 17, count 2 2006.189.08:01:31.74#ibcon#about to read 3, iclass 17, count 2 2006.189.08:01:31.76#ibcon#read 3, iclass 17, count 2 2006.189.08:01:31.76#ibcon#about to read 4, iclass 17, count 2 2006.189.08:01:31.76#ibcon#read 4, iclass 17, count 2 2006.189.08:01:31.76#ibcon#about to read 5, iclass 17, count 2 2006.189.08:01:31.76#ibcon#read 5, iclass 17, count 2 2006.189.08:01:31.76#ibcon#about to read 6, iclass 17, count 2 2006.189.08:01:31.76#ibcon#read 6, iclass 17, count 2 2006.189.08:01:31.76#ibcon#end of sib2, iclass 17, count 2 2006.189.08:01:31.76#ibcon#*mode == 0, iclass 17, count 2 2006.189.08:01:31.76#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.08:01:31.76#ibcon#[27=AT04-04\r\n] 2006.189.08:01:31.76#ibcon#*before write, iclass 17, count 2 2006.189.08:01:31.76#ibcon#enter sib2, iclass 17, count 2 2006.189.08:01:31.76#ibcon#flushed, iclass 17, count 2 2006.189.08:01:31.76#ibcon#about to write, iclass 17, count 2 2006.189.08:01:31.76#ibcon#wrote, iclass 17, count 2 2006.189.08:01:31.76#ibcon#about to read 3, iclass 17, count 2 2006.189.08:01:31.79#ibcon#read 3, iclass 17, count 2 2006.189.08:01:31.79#ibcon#about to read 4, iclass 17, count 2 2006.189.08:01:31.79#ibcon#read 4, iclass 17, count 2 2006.189.08:01:31.79#ibcon#about to read 5, iclass 17, count 2 2006.189.08:01:31.79#ibcon#read 5, iclass 17, count 2 2006.189.08:01:31.79#ibcon#about to read 6, iclass 17, count 2 2006.189.08:01:31.79#ibcon#read 6, iclass 17, count 2 2006.189.08:01:31.79#ibcon#end of sib2, iclass 17, count 2 2006.189.08:01:31.79#ibcon#*after write, iclass 17, count 2 2006.189.08:01:31.79#ibcon#*before return 0, iclass 17, count 2 2006.189.08:01:31.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:31.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:01:31.79#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.08:01:31.79#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:31.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:31.91#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:31.91#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:31.91#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:01:31.91#ibcon#first serial, iclass 17, count 0 2006.189.08:01:31.91#ibcon#enter sib2, iclass 17, count 0 2006.189.08:01:31.91#ibcon#flushed, iclass 17, count 0 2006.189.08:01:31.91#ibcon#about to write, iclass 17, count 0 2006.189.08:01:31.91#ibcon#wrote, iclass 17, count 0 2006.189.08:01:31.91#ibcon#about to read 3, iclass 17, count 0 2006.189.08:01:31.93#ibcon#read 3, iclass 17, count 0 2006.189.08:01:31.93#ibcon#about to read 4, iclass 17, count 0 2006.189.08:01:31.93#ibcon#read 4, iclass 17, count 0 2006.189.08:01:31.93#ibcon#about to read 5, iclass 17, count 0 2006.189.08:01:31.93#ibcon#read 5, iclass 17, count 0 2006.189.08:01:31.93#ibcon#about to read 6, iclass 17, count 0 2006.189.08:01:31.93#ibcon#read 6, iclass 17, count 0 2006.189.08:01:31.93#ibcon#end of sib2, iclass 17, count 0 2006.189.08:01:31.93#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:01:31.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:01:31.93#ibcon#[27=USB\r\n] 2006.189.08:01:31.93#ibcon#*before write, iclass 17, count 0 2006.189.08:01:31.93#ibcon#enter sib2, iclass 17, count 0 2006.189.08:01:31.93#ibcon#flushed, iclass 17, count 0 2006.189.08:01:31.93#ibcon#about to write, iclass 17, count 0 2006.189.08:01:31.93#ibcon#wrote, iclass 17, count 0 2006.189.08:01:31.93#ibcon#about to read 3, iclass 17, count 0 2006.189.08:01:31.96#ibcon#read 3, iclass 17, count 0 2006.189.08:01:31.96#ibcon#about to read 4, iclass 17, count 0 2006.189.08:01:31.96#ibcon#read 4, iclass 17, count 0 2006.189.08:01:31.96#ibcon#about to read 5, iclass 17, count 0 2006.189.08:01:31.96#ibcon#read 5, iclass 17, count 0 2006.189.08:01:31.96#ibcon#about to read 6, iclass 17, count 0 2006.189.08:01:31.96#ibcon#read 6, iclass 17, count 0 2006.189.08:01:31.96#ibcon#end of sib2, iclass 17, count 0 2006.189.08:01:31.96#ibcon#*after write, iclass 17, count 0 2006.189.08:01:31.96#ibcon#*before return 0, iclass 17, count 0 2006.189.08:01:31.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:31.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:01:31.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:01:31.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:01:31.96$vc4f8/vblo=5,744.99 2006.189.08:01:31.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.08:01:31.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.08:01:31.96#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:31.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:31.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:31.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:31.96#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:01:31.96#ibcon#first serial, iclass 19, count 0 2006.189.08:01:31.96#ibcon#enter sib2, iclass 19, count 0 2006.189.08:01:31.96#ibcon#flushed, iclass 19, count 0 2006.189.08:01:31.96#ibcon#about to write, iclass 19, count 0 2006.189.08:01:31.96#ibcon#wrote, iclass 19, count 0 2006.189.08:01:31.96#ibcon#about to read 3, iclass 19, count 0 2006.189.08:01:31.98#ibcon#read 3, iclass 19, count 0 2006.189.08:01:31.98#ibcon#about to read 4, iclass 19, count 0 2006.189.08:01:31.98#ibcon#read 4, iclass 19, count 0 2006.189.08:01:31.98#ibcon#about to read 5, iclass 19, count 0 2006.189.08:01:31.98#ibcon#read 5, iclass 19, count 0 2006.189.08:01:31.98#ibcon#about to read 6, iclass 19, count 0 2006.189.08:01:31.98#ibcon#read 6, iclass 19, count 0 2006.189.08:01:31.98#ibcon#end of sib2, iclass 19, count 0 2006.189.08:01:31.98#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:01:31.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:01:31.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:01:31.98#ibcon#*before write, iclass 19, count 0 2006.189.08:01:31.98#ibcon#enter sib2, iclass 19, count 0 2006.189.08:01:31.98#ibcon#flushed, iclass 19, count 0 2006.189.08:01:31.98#ibcon#about to write, iclass 19, count 0 2006.189.08:01:31.98#ibcon#wrote, iclass 19, count 0 2006.189.08:01:31.98#ibcon#about to read 3, iclass 19, count 0 2006.189.08:01:32.02#ibcon#read 3, iclass 19, count 0 2006.189.08:01:32.02#ibcon#about to read 4, iclass 19, count 0 2006.189.08:01:32.02#ibcon#read 4, iclass 19, count 0 2006.189.08:01:32.02#ibcon#about to read 5, iclass 19, count 0 2006.189.08:01:32.02#ibcon#read 5, iclass 19, count 0 2006.189.08:01:32.02#ibcon#about to read 6, iclass 19, count 0 2006.189.08:01:32.02#ibcon#read 6, iclass 19, count 0 2006.189.08:01:32.02#ibcon#end of sib2, iclass 19, count 0 2006.189.08:01:32.02#ibcon#*after write, iclass 19, count 0 2006.189.08:01:32.02#ibcon#*before return 0, iclass 19, count 0 2006.189.08:01:32.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:32.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:01:32.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:01:32.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:01:32.02$vc4f8/vb=5,4 2006.189.08:01:32.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.08:01:32.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.08:01:32.02#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:32.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:32.08#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:32.08#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:32.08#ibcon#enter wrdev, iclass 21, count 2 2006.189.08:01:32.08#ibcon#first serial, iclass 21, count 2 2006.189.08:01:32.08#ibcon#enter sib2, iclass 21, count 2 2006.189.08:01:32.08#ibcon#flushed, iclass 21, count 2 2006.189.08:01:32.08#ibcon#about to write, iclass 21, count 2 2006.189.08:01:32.08#ibcon#wrote, iclass 21, count 2 2006.189.08:01:32.08#ibcon#about to read 3, iclass 21, count 2 2006.189.08:01:32.10#ibcon#read 3, iclass 21, count 2 2006.189.08:01:32.10#ibcon#about to read 4, iclass 21, count 2 2006.189.08:01:32.10#ibcon#read 4, iclass 21, count 2 2006.189.08:01:32.10#ibcon#about to read 5, iclass 21, count 2 2006.189.08:01:32.10#ibcon#read 5, iclass 21, count 2 2006.189.08:01:32.10#ibcon#about to read 6, iclass 21, count 2 2006.189.08:01:32.10#ibcon#read 6, iclass 21, count 2 2006.189.08:01:32.10#ibcon#end of sib2, iclass 21, count 2 2006.189.08:01:32.10#ibcon#*mode == 0, iclass 21, count 2 2006.189.08:01:32.10#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.08:01:32.10#ibcon#[27=AT05-04\r\n] 2006.189.08:01:32.10#ibcon#*before write, iclass 21, count 2 2006.189.08:01:32.10#ibcon#enter sib2, iclass 21, count 2 2006.189.08:01:32.10#ibcon#flushed, iclass 21, count 2 2006.189.08:01:32.10#ibcon#about to write, iclass 21, count 2 2006.189.08:01:32.10#ibcon#wrote, iclass 21, count 2 2006.189.08:01:32.10#ibcon#about to read 3, iclass 21, count 2 2006.189.08:01:32.13#ibcon#read 3, iclass 21, count 2 2006.189.08:01:32.13#ibcon#about to read 4, iclass 21, count 2 2006.189.08:01:32.13#ibcon#read 4, iclass 21, count 2 2006.189.08:01:32.13#ibcon#about to read 5, iclass 21, count 2 2006.189.08:01:32.13#ibcon#read 5, iclass 21, count 2 2006.189.08:01:32.13#ibcon#about to read 6, iclass 21, count 2 2006.189.08:01:32.13#ibcon#read 6, iclass 21, count 2 2006.189.08:01:32.13#ibcon#end of sib2, iclass 21, count 2 2006.189.08:01:32.13#ibcon#*after write, iclass 21, count 2 2006.189.08:01:32.13#ibcon#*before return 0, iclass 21, count 2 2006.189.08:01:32.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:32.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:01:32.13#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.08:01:32.13#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:32.13#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:32.25#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:32.25#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:32.25#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:01:32.25#ibcon#first serial, iclass 21, count 0 2006.189.08:01:32.25#ibcon#enter sib2, iclass 21, count 0 2006.189.08:01:32.25#ibcon#flushed, iclass 21, count 0 2006.189.08:01:32.25#ibcon#about to write, iclass 21, count 0 2006.189.08:01:32.25#ibcon#wrote, iclass 21, count 0 2006.189.08:01:32.25#ibcon#about to read 3, iclass 21, count 0 2006.189.08:01:32.27#ibcon#read 3, iclass 21, count 0 2006.189.08:01:32.27#ibcon#about to read 4, iclass 21, count 0 2006.189.08:01:32.27#ibcon#read 4, iclass 21, count 0 2006.189.08:01:32.27#ibcon#about to read 5, iclass 21, count 0 2006.189.08:01:32.27#ibcon#read 5, iclass 21, count 0 2006.189.08:01:32.27#ibcon#about to read 6, iclass 21, count 0 2006.189.08:01:32.27#ibcon#read 6, iclass 21, count 0 2006.189.08:01:32.27#ibcon#end of sib2, iclass 21, count 0 2006.189.08:01:32.27#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:01:32.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:01:32.27#ibcon#[27=USB\r\n] 2006.189.08:01:32.27#ibcon#*before write, iclass 21, count 0 2006.189.08:01:32.27#ibcon#enter sib2, iclass 21, count 0 2006.189.08:01:32.27#ibcon#flushed, iclass 21, count 0 2006.189.08:01:32.27#ibcon#about to write, iclass 21, count 0 2006.189.08:01:32.27#ibcon#wrote, iclass 21, count 0 2006.189.08:01:32.27#ibcon#about to read 3, iclass 21, count 0 2006.189.08:01:32.30#ibcon#read 3, iclass 21, count 0 2006.189.08:01:32.30#ibcon#about to read 4, iclass 21, count 0 2006.189.08:01:32.30#ibcon#read 4, iclass 21, count 0 2006.189.08:01:32.30#ibcon#about to read 5, iclass 21, count 0 2006.189.08:01:32.30#ibcon#read 5, iclass 21, count 0 2006.189.08:01:32.30#ibcon#about to read 6, iclass 21, count 0 2006.189.08:01:32.30#ibcon#read 6, iclass 21, count 0 2006.189.08:01:32.30#ibcon#end of sib2, iclass 21, count 0 2006.189.08:01:32.30#ibcon#*after write, iclass 21, count 0 2006.189.08:01:32.30#ibcon#*before return 0, iclass 21, count 0 2006.189.08:01:32.30#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:32.30#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:01:32.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:01:32.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:01:32.30$vc4f8/vblo=6,752.99 2006.189.08:01:32.30#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.08:01:32.30#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.08:01:32.30#ibcon#ireg 17 cls_cnt 0 2006.189.08:01:32.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:32.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:32.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:32.30#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:01:32.30#ibcon#first serial, iclass 23, count 0 2006.189.08:01:32.30#ibcon#enter sib2, iclass 23, count 0 2006.189.08:01:32.30#ibcon#flushed, iclass 23, count 0 2006.189.08:01:32.30#ibcon#about to write, iclass 23, count 0 2006.189.08:01:32.30#ibcon#wrote, iclass 23, count 0 2006.189.08:01:32.30#ibcon#about to read 3, iclass 23, count 0 2006.189.08:01:32.32#ibcon#read 3, iclass 23, count 0 2006.189.08:01:32.32#ibcon#about to read 4, iclass 23, count 0 2006.189.08:01:32.32#ibcon#read 4, iclass 23, count 0 2006.189.08:01:32.32#ibcon#about to read 5, iclass 23, count 0 2006.189.08:01:32.32#ibcon#read 5, iclass 23, count 0 2006.189.08:01:32.32#ibcon#about to read 6, iclass 23, count 0 2006.189.08:01:32.32#ibcon#read 6, iclass 23, count 0 2006.189.08:01:32.32#ibcon#end of sib2, iclass 23, count 0 2006.189.08:01:32.32#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:01:32.32#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:01:32.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:01:32.32#ibcon#*before write, iclass 23, count 0 2006.189.08:01:32.32#ibcon#enter sib2, iclass 23, count 0 2006.189.08:01:32.32#ibcon#flushed, iclass 23, count 0 2006.189.08:01:32.32#ibcon#about to write, iclass 23, count 0 2006.189.08:01:32.32#ibcon#wrote, iclass 23, count 0 2006.189.08:01:32.32#ibcon#about to read 3, iclass 23, count 0 2006.189.08:01:32.36#ibcon#read 3, iclass 23, count 0 2006.189.08:01:32.36#ibcon#about to read 4, iclass 23, count 0 2006.189.08:01:32.36#ibcon#read 4, iclass 23, count 0 2006.189.08:01:32.36#ibcon#about to read 5, iclass 23, count 0 2006.189.08:01:32.36#ibcon#read 5, iclass 23, count 0 2006.189.08:01:32.36#ibcon#about to read 6, iclass 23, count 0 2006.189.08:01:32.36#ibcon#read 6, iclass 23, count 0 2006.189.08:01:32.36#ibcon#end of sib2, iclass 23, count 0 2006.189.08:01:32.36#ibcon#*after write, iclass 23, count 0 2006.189.08:01:32.36#ibcon#*before return 0, iclass 23, count 0 2006.189.08:01:32.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:32.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:01:32.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:01:32.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:01:32.36$vc4f8/vb=6,4 2006.189.08:01:32.36#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.08:01:32.36#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.08:01:32.36#ibcon#ireg 11 cls_cnt 2 2006.189.08:01:32.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:32.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:32.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:32.42#ibcon#enter wrdev, iclass 25, count 2 2006.189.08:01:32.42#ibcon#first serial, iclass 25, count 2 2006.189.08:01:32.42#ibcon#enter sib2, iclass 25, count 2 2006.189.08:01:32.42#ibcon#flushed, iclass 25, count 2 2006.189.08:01:32.42#ibcon#about to write, iclass 25, count 2 2006.189.08:01:32.42#ibcon#wrote, iclass 25, count 2 2006.189.08:01:32.42#ibcon#about to read 3, iclass 25, count 2 2006.189.08:01:32.44#ibcon#read 3, iclass 25, count 2 2006.189.08:01:32.44#ibcon#about to read 4, iclass 25, count 2 2006.189.08:01:32.44#ibcon#read 4, iclass 25, count 2 2006.189.08:01:32.44#ibcon#about to read 5, iclass 25, count 2 2006.189.08:01:32.44#ibcon#read 5, iclass 25, count 2 2006.189.08:01:32.44#ibcon#about to read 6, iclass 25, count 2 2006.189.08:01:32.44#ibcon#read 6, iclass 25, count 2 2006.189.08:01:32.44#ibcon#end of sib2, iclass 25, count 2 2006.189.08:01:32.44#ibcon#*mode == 0, iclass 25, count 2 2006.189.08:01:32.44#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.08:01:32.44#ibcon#[27=AT06-04\r\n] 2006.189.08:01:32.44#ibcon#*before write, iclass 25, count 2 2006.189.08:01:32.44#ibcon#enter sib2, iclass 25, count 2 2006.189.08:01:32.44#ibcon#flushed, iclass 25, count 2 2006.189.08:01:32.44#ibcon#about to write, iclass 25, count 2 2006.189.08:01:32.44#ibcon#wrote, iclass 25, count 2 2006.189.08:01:32.44#ibcon#about to read 3, iclass 25, count 2 2006.189.08:01:32.47#ibcon#read 3, iclass 25, count 2 2006.189.08:01:32.47#ibcon#about to read 4, iclass 25, count 2 2006.189.08:01:32.47#ibcon#read 4, iclass 25, count 2 2006.189.08:01:32.47#ibcon#about to read 5, iclass 25, count 2 2006.189.08:01:32.47#ibcon#read 5, iclass 25, count 2 2006.189.08:01:32.47#ibcon#about to read 6, iclass 25, count 2 2006.189.08:01:32.47#ibcon#read 6, iclass 25, count 2 2006.189.08:01:32.47#ibcon#end of sib2, iclass 25, count 2 2006.189.08:01:32.47#ibcon#*after write, iclass 25, count 2 2006.189.08:01:32.47#ibcon#*before return 0, iclass 25, count 2 2006.189.08:01:32.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:32.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:01:32.47#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.08:01:32.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:01:32.47#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:32.59#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:32.59#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:32.59#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:01:32.59#ibcon#first serial, iclass 25, count 0 2006.189.08:01:32.59#ibcon#enter sib2, iclass 25, count 0 2006.189.08:01:32.59#ibcon#flushed, iclass 25, count 0 2006.189.08:01:32.59#ibcon#about to write, iclass 25, count 0 2006.189.08:01:32.59#ibcon#wrote, iclass 25, count 0 2006.189.08:01:32.59#ibcon#about to read 3, iclass 25, count 0 2006.189.08:01:32.61#ibcon#read 3, iclass 25, count 0 2006.189.08:01:32.61#ibcon#about to read 4, iclass 25, count 0 2006.189.08:01:32.61#ibcon#read 4, iclass 25, count 0 2006.189.08:01:32.61#ibcon#about to read 5, iclass 25, count 0 2006.189.08:01:32.61#ibcon#read 5, iclass 25, count 0 2006.189.08:01:32.61#ibcon#about to read 6, iclass 25, count 0 2006.189.08:01:32.61#ibcon#read 6, iclass 25, count 0 2006.189.08:01:32.61#ibcon#end of sib2, iclass 25, count 0 2006.189.08:01:32.61#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:01:32.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:01:32.61#ibcon#[27=USB\r\n] 2006.189.08:01:32.61#ibcon#*before write, iclass 25, count 0 2006.189.08:01:32.61#ibcon#enter sib2, iclass 25, count 0 2006.189.08:01:32.61#ibcon#flushed, iclass 25, count 0 2006.189.08:01:32.61#ibcon#about to write, iclass 25, count 0 2006.189.08:01:32.61#ibcon#wrote, iclass 25, count 0 2006.189.08:01:32.61#ibcon#about to read 3, iclass 25, count 0 2006.189.08:01:32.64#ibcon#read 3, iclass 25, count 0 2006.189.08:01:32.64#ibcon#about to read 4, iclass 25, count 0 2006.189.08:01:32.64#ibcon#read 4, iclass 25, count 0 2006.189.08:01:32.64#ibcon#about to read 5, iclass 25, count 0 2006.189.08:01:32.64#ibcon#read 5, iclass 25, count 0 2006.189.08:01:32.64#ibcon#about to read 6, iclass 25, count 0 2006.189.08:01:32.64#ibcon#read 6, iclass 25, count 0 2006.189.08:01:32.64#ibcon#end of sib2, iclass 25, count 0 2006.189.08:01:32.64#ibcon#*after write, iclass 25, count 0 2006.189.08:01:32.64#ibcon#*before return 0, iclass 25, count 0 2006.189.08:01:32.64#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:32.64#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:01:32.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:01:32.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:01:32.64$vc4f8/vabw=wide 2006.189.08:01:32.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.08:01:32.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.08:01:32.64#ibcon#ireg 8 cls_cnt 0 2006.189.08:01:32.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:32.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:32.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:32.64#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:01:32.64#ibcon#first serial, iclass 27, count 0 2006.189.08:01:32.64#ibcon#enter sib2, iclass 27, count 0 2006.189.08:01:32.64#ibcon#flushed, iclass 27, count 0 2006.189.08:01:32.64#ibcon#about to write, iclass 27, count 0 2006.189.08:01:32.64#ibcon#wrote, iclass 27, count 0 2006.189.08:01:32.64#ibcon#about to read 3, iclass 27, count 0 2006.189.08:01:32.66#ibcon#read 3, iclass 27, count 0 2006.189.08:01:32.66#ibcon#about to read 4, iclass 27, count 0 2006.189.08:01:32.66#ibcon#read 4, iclass 27, count 0 2006.189.08:01:32.66#ibcon#about to read 5, iclass 27, count 0 2006.189.08:01:32.66#ibcon#read 5, iclass 27, count 0 2006.189.08:01:32.66#ibcon#about to read 6, iclass 27, count 0 2006.189.08:01:32.66#ibcon#read 6, iclass 27, count 0 2006.189.08:01:32.66#ibcon#end of sib2, iclass 27, count 0 2006.189.08:01:32.66#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:01:32.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:01:32.66#ibcon#[25=BW32\r\n] 2006.189.08:01:32.66#ibcon#*before write, iclass 27, count 0 2006.189.08:01:32.66#ibcon#enter sib2, iclass 27, count 0 2006.189.08:01:32.66#ibcon#flushed, iclass 27, count 0 2006.189.08:01:32.66#ibcon#about to write, iclass 27, count 0 2006.189.08:01:32.66#ibcon#wrote, iclass 27, count 0 2006.189.08:01:32.66#ibcon#about to read 3, iclass 27, count 0 2006.189.08:01:32.69#ibcon#read 3, iclass 27, count 0 2006.189.08:01:32.69#ibcon#about to read 4, iclass 27, count 0 2006.189.08:01:32.69#ibcon#read 4, iclass 27, count 0 2006.189.08:01:32.69#ibcon#about to read 5, iclass 27, count 0 2006.189.08:01:32.69#ibcon#read 5, iclass 27, count 0 2006.189.08:01:32.69#ibcon#about to read 6, iclass 27, count 0 2006.189.08:01:32.69#ibcon#read 6, iclass 27, count 0 2006.189.08:01:32.69#ibcon#end of sib2, iclass 27, count 0 2006.189.08:01:32.69#ibcon#*after write, iclass 27, count 0 2006.189.08:01:32.69#ibcon#*before return 0, iclass 27, count 0 2006.189.08:01:32.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:32.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:01:32.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:01:32.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:01:32.69$vc4f8/vbbw=wide 2006.189.08:01:32.69#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.08:01:32.69#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.08:01:32.69#ibcon#ireg 8 cls_cnt 0 2006.189.08:01:32.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:01:32.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:01:32.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:01:32.76#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:01:32.76#ibcon#first serial, iclass 29, count 0 2006.189.08:01:32.76#ibcon#enter sib2, iclass 29, count 0 2006.189.08:01:32.76#ibcon#flushed, iclass 29, count 0 2006.189.08:01:32.76#ibcon#about to write, iclass 29, count 0 2006.189.08:01:32.76#ibcon#wrote, iclass 29, count 0 2006.189.08:01:32.76#ibcon#about to read 3, iclass 29, count 0 2006.189.08:01:32.78#ibcon#read 3, iclass 29, count 0 2006.189.08:01:32.78#ibcon#about to read 4, iclass 29, count 0 2006.189.08:01:32.78#ibcon#read 4, iclass 29, count 0 2006.189.08:01:32.78#ibcon#about to read 5, iclass 29, count 0 2006.189.08:01:32.78#ibcon#read 5, iclass 29, count 0 2006.189.08:01:32.78#ibcon#about to read 6, iclass 29, count 0 2006.189.08:01:32.78#ibcon#read 6, iclass 29, count 0 2006.189.08:01:32.78#ibcon#end of sib2, iclass 29, count 0 2006.189.08:01:32.78#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:01:32.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:01:32.78#ibcon#[27=BW32\r\n] 2006.189.08:01:32.78#ibcon#*before write, iclass 29, count 0 2006.189.08:01:32.78#ibcon#enter sib2, iclass 29, count 0 2006.189.08:01:32.78#ibcon#flushed, iclass 29, count 0 2006.189.08:01:32.78#ibcon#about to write, iclass 29, count 0 2006.189.08:01:32.78#ibcon#wrote, iclass 29, count 0 2006.189.08:01:32.78#ibcon#about to read 3, iclass 29, count 0 2006.189.08:01:32.81#ibcon#read 3, iclass 29, count 0 2006.189.08:01:32.81#ibcon#about to read 4, iclass 29, count 0 2006.189.08:01:32.81#ibcon#read 4, iclass 29, count 0 2006.189.08:01:32.81#ibcon#about to read 5, iclass 29, count 0 2006.189.08:01:32.81#ibcon#read 5, iclass 29, count 0 2006.189.08:01:32.81#ibcon#about to read 6, iclass 29, count 0 2006.189.08:01:32.81#ibcon#read 6, iclass 29, count 0 2006.189.08:01:32.81#ibcon#end of sib2, iclass 29, count 0 2006.189.08:01:32.81#ibcon#*after write, iclass 29, count 0 2006.189.08:01:32.81#ibcon#*before return 0, iclass 29, count 0 2006.189.08:01:32.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:01:32.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:01:32.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:01:32.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:01:32.81$4f8m12a/ifd4f 2006.189.08:01:32.81$ifd4f/lo= 2006.189.08:01:32.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:01:32.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:01:32.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:01:32.81$ifd4f/patch= 2006.189.08:01:32.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:01:32.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:01:32.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:01:32.81$4f8m12a/"form=m,16.000,1:2 2006.189.08:01:32.81$4f8m12a/"tpicd 2006.189.08:01:32.81$4f8m12a/echo=off 2006.189.08:01:32.81$4f8m12a/xlog=off 2006.189.08:01:32.81:!2006.189.08:02:00 2006.189.08:01:39.13#trakl#Source acquired 2006.189.08:01:39.13#flagr#flagr/antenna,acquired 2006.189.08:02:00.00:preob 2006.189.08:02:01.13/onsource/TRACKING 2006.189.08:02:01.13:!2006.189.08:02:10 2006.189.08:02:10.00:data_valid=on 2006.189.08:02:10.00:midob 2006.189.08:02:10.13/onsource/TRACKING 2006.189.08:02:10.13/wx/25.68,1009.2,90 2006.189.08:02:10.20/cable/+6.4562E-03 2006.189.08:02:11.30/va/01,08,usb,yes,29,31 2006.189.08:02:11.30/va/02,07,usb,yes,30,31 2006.189.08:02:11.30/va/03,06,usb,yes,31,31 2006.189.08:02:11.30/va/04,07,usb,yes,30,33 2006.189.08:02:11.30/va/05,07,usb,yes,32,34 2006.189.08:02:11.30/va/06,06,usb,yes,31,31 2006.189.08:02:11.30/va/07,06,usb,yes,32,32 2006.189.08:02:11.30/va/08,06,usb,yes,34,33 2006.189.08:02:11.53/valo/01,532.99,yes,locked 2006.189.08:02:11.53/valo/02,572.99,yes,locked 2006.189.08:02:11.53/valo/03,672.99,yes,locked 2006.189.08:02:11.53/valo/04,832.99,yes,locked 2006.189.08:02:11.53/valo/05,652.99,yes,locked 2006.189.08:02:11.53/valo/06,772.99,yes,locked 2006.189.08:02:11.53/valo/07,832.99,yes,locked 2006.189.08:02:11.53/valo/08,852.99,yes,locked 2006.189.08:02:12.62/vb/01,04,usb,yes,29,28 2006.189.08:02:12.62/vb/02,04,usb,yes,31,32 2006.189.08:02:12.62/vb/03,04,usb,yes,27,31 2006.189.08:02:12.62/vb/04,04,usb,yes,28,28 2006.189.08:02:12.62/vb/05,04,usb,yes,27,31 2006.189.08:02:12.62/vb/06,04,usb,yes,28,30 2006.189.08:02:12.62/vb/07,04,usb,yes,30,30 2006.189.08:02:12.62/vb/08,04,usb,yes,27,31 2006.189.08:02:12.86/vblo/01,632.99,yes,locked 2006.189.08:02:12.86/vblo/02,640.99,yes,locked 2006.189.08:02:12.86/vblo/03,656.99,yes,locked 2006.189.08:02:12.86/vblo/04,712.99,yes,locked 2006.189.08:02:12.86/vblo/05,744.99,yes,locked 2006.189.08:02:12.86/vblo/06,752.99,yes,locked 2006.189.08:02:12.86/vblo/07,734.99,yes,locked 2006.189.08:02:12.86/vblo/08,744.99,yes,locked 2006.189.08:02:13.01/vabw/8 2006.189.08:02:13.16/vbbw/8 2006.189.08:02:13.25/xfe/off,on,15.2 2006.189.08:02:13.64/ifatt/23,28,28,28 2006.189.08:02:14.08/fmout-gps/S +2.98E-07 2006.189.08:02:14.16:!2006.189.08:03:10 2006.189.08:03:10.00:data_valid=off 2006.189.08:03:10.00:postob 2006.189.08:03:10.22/cable/+6.4574E-03 2006.189.08:03:10.22/wx/25.67,1009.1,91 2006.189.08:03:11.08/fmout-gps/S +2.96E-07 2006.189.08:03:11.08:scan_name=189-0804,k06189,60 2006.189.08:03:11.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.189.08:03:11.14#flagr#flagr/antenna,new-source 2006.189.08:03:12.14:checkk5 2006.189.08:03:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:03:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:03:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:03:13.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:03:14.05/chk_obsdata//k5ts1/T1890802??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:03:14.44/chk_obsdata//k5ts2/T1890802??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:03:14.81/chk_obsdata//k5ts3/T1890802??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:03:15.18/chk_obsdata//k5ts4/T1890802??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:03:15.87/k5log//k5ts1_log_newline 2006.189.08:03:16.56/k5log//k5ts2_log_newline 2006.189.08:03:17.26/k5log//k5ts3_log_newline 2006.189.08:03:17.96/k5log//k5ts4_log_newline 2006.189.08:03:17.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:03:17.98:4f8m12a=2 2006.189.08:03:17.98$4f8m12a/echo=on 2006.189.08:03:17.98$4f8m12a/pcalon 2006.189.08:03:17.98$pcalon/"no phase cal control is implemented here 2006.189.08:03:17.98$4f8m12a/"tpicd=stop 2006.189.08:03:17.98$4f8m12a/vc4f8 2006.189.08:03:17.98$vc4f8/valo=1,532.99 2006.189.08:03:17.99#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.08:03:17.99#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.08:03:17.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:17.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:17.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:17.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:17.99#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:03:17.99#ibcon#first serial, iclass 36, count 0 2006.189.08:03:17.99#ibcon#enter sib2, iclass 36, count 0 2006.189.08:03:17.99#ibcon#flushed, iclass 36, count 0 2006.189.08:03:17.99#ibcon#about to write, iclass 36, count 0 2006.189.08:03:17.99#ibcon#wrote, iclass 36, count 0 2006.189.08:03:17.99#ibcon#about to read 3, iclass 36, count 0 2006.189.08:03:18.04#ibcon#read 3, iclass 36, count 0 2006.189.08:03:18.04#ibcon#about to read 4, iclass 36, count 0 2006.189.08:03:18.04#ibcon#read 4, iclass 36, count 0 2006.189.08:03:18.04#ibcon#about to read 5, iclass 36, count 0 2006.189.08:03:18.04#ibcon#read 5, iclass 36, count 0 2006.189.08:03:18.04#ibcon#about to read 6, iclass 36, count 0 2006.189.08:03:18.04#ibcon#read 6, iclass 36, count 0 2006.189.08:03:18.04#ibcon#end of sib2, iclass 36, count 0 2006.189.08:03:18.04#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:03:18.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:03:18.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:03:18.04#ibcon#*before write, iclass 36, count 0 2006.189.08:03:18.04#ibcon#enter sib2, iclass 36, count 0 2006.189.08:03:18.04#ibcon#flushed, iclass 36, count 0 2006.189.08:03:18.04#ibcon#about to write, iclass 36, count 0 2006.189.08:03:18.04#ibcon#wrote, iclass 36, count 0 2006.189.08:03:18.04#ibcon#about to read 3, iclass 36, count 0 2006.189.08:03:18.09#ibcon#read 3, iclass 36, count 0 2006.189.08:03:18.09#ibcon#about to read 4, iclass 36, count 0 2006.189.08:03:18.09#ibcon#read 4, iclass 36, count 0 2006.189.08:03:18.09#ibcon#about to read 5, iclass 36, count 0 2006.189.08:03:18.09#ibcon#read 5, iclass 36, count 0 2006.189.08:03:18.09#ibcon#about to read 6, iclass 36, count 0 2006.189.08:03:18.09#ibcon#read 6, iclass 36, count 0 2006.189.08:03:18.09#ibcon#end of sib2, iclass 36, count 0 2006.189.08:03:18.09#ibcon#*after write, iclass 36, count 0 2006.189.08:03:18.09#ibcon#*before return 0, iclass 36, count 0 2006.189.08:03:18.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:18.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:18.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:03:18.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:03:18.09$vc4f8/va=1,8 2006.189.08:03:18.09#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.08:03:18.09#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.08:03:18.09#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:18.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:18.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:18.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:18.09#ibcon#enter wrdev, iclass 38, count 2 2006.189.08:03:18.09#ibcon#first serial, iclass 38, count 2 2006.189.08:03:18.09#ibcon#enter sib2, iclass 38, count 2 2006.189.08:03:18.09#ibcon#flushed, iclass 38, count 2 2006.189.08:03:18.09#ibcon#about to write, iclass 38, count 2 2006.189.08:03:18.09#ibcon#wrote, iclass 38, count 2 2006.189.08:03:18.09#ibcon#about to read 3, iclass 38, count 2 2006.189.08:03:18.11#ibcon#read 3, iclass 38, count 2 2006.189.08:03:18.11#ibcon#about to read 4, iclass 38, count 2 2006.189.08:03:18.11#ibcon#read 4, iclass 38, count 2 2006.189.08:03:18.11#ibcon#about to read 5, iclass 38, count 2 2006.189.08:03:18.11#ibcon#read 5, iclass 38, count 2 2006.189.08:03:18.11#ibcon#about to read 6, iclass 38, count 2 2006.189.08:03:18.11#ibcon#read 6, iclass 38, count 2 2006.189.08:03:18.11#ibcon#end of sib2, iclass 38, count 2 2006.189.08:03:18.11#ibcon#*mode == 0, iclass 38, count 2 2006.189.08:03:18.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.08:03:18.11#ibcon#[25=AT01-08\r\n] 2006.189.08:03:18.11#ibcon#*before write, iclass 38, count 2 2006.189.08:03:18.11#ibcon#enter sib2, iclass 38, count 2 2006.189.08:03:18.11#ibcon#flushed, iclass 38, count 2 2006.189.08:03:18.11#ibcon#about to write, iclass 38, count 2 2006.189.08:03:18.11#ibcon#wrote, iclass 38, count 2 2006.189.08:03:18.11#ibcon#about to read 3, iclass 38, count 2 2006.189.08:03:18.14#ibcon#read 3, iclass 38, count 2 2006.189.08:03:18.14#ibcon#about to read 4, iclass 38, count 2 2006.189.08:03:18.14#ibcon#read 4, iclass 38, count 2 2006.189.08:03:18.14#ibcon#about to read 5, iclass 38, count 2 2006.189.08:03:18.14#ibcon#read 5, iclass 38, count 2 2006.189.08:03:18.14#ibcon#about to read 6, iclass 38, count 2 2006.189.08:03:18.14#ibcon#read 6, iclass 38, count 2 2006.189.08:03:18.14#ibcon#end of sib2, iclass 38, count 2 2006.189.08:03:18.14#ibcon#*after write, iclass 38, count 2 2006.189.08:03:18.14#ibcon#*before return 0, iclass 38, count 2 2006.189.08:03:18.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:18.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:18.14#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.08:03:18.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:18.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:18.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:18.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:18.26#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:03:18.26#ibcon#first serial, iclass 38, count 0 2006.189.08:03:18.26#ibcon#enter sib2, iclass 38, count 0 2006.189.08:03:18.26#ibcon#flushed, iclass 38, count 0 2006.189.08:03:18.26#ibcon#about to write, iclass 38, count 0 2006.189.08:03:18.26#ibcon#wrote, iclass 38, count 0 2006.189.08:03:18.26#ibcon#about to read 3, iclass 38, count 0 2006.189.08:03:18.28#ibcon#read 3, iclass 38, count 0 2006.189.08:03:18.28#ibcon#about to read 4, iclass 38, count 0 2006.189.08:03:18.28#ibcon#read 4, iclass 38, count 0 2006.189.08:03:18.28#ibcon#about to read 5, iclass 38, count 0 2006.189.08:03:18.28#ibcon#read 5, iclass 38, count 0 2006.189.08:03:18.28#ibcon#about to read 6, iclass 38, count 0 2006.189.08:03:18.28#ibcon#read 6, iclass 38, count 0 2006.189.08:03:18.28#ibcon#end of sib2, iclass 38, count 0 2006.189.08:03:18.28#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:03:18.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:03:18.28#ibcon#[25=USB\r\n] 2006.189.08:03:18.28#ibcon#*before write, iclass 38, count 0 2006.189.08:03:18.28#ibcon#enter sib2, iclass 38, count 0 2006.189.08:03:18.28#ibcon#flushed, iclass 38, count 0 2006.189.08:03:18.28#ibcon#about to write, iclass 38, count 0 2006.189.08:03:18.28#ibcon#wrote, iclass 38, count 0 2006.189.08:03:18.28#ibcon#about to read 3, iclass 38, count 0 2006.189.08:03:18.31#ibcon#read 3, iclass 38, count 0 2006.189.08:03:18.31#ibcon#about to read 4, iclass 38, count 0 2006.189.08:03:18.31#ibcon#read 4, iclass 38, count 0 2006.189.08:03:18.31#ibcon#about to read 5, iclass 38, count 0 2006.189.08:03:18.31#ibcon#read 5, iclass 38, count 0 2006.189.08:03:18.31#ibcon#about to read 6, iclass 38, count 0 2006.189.08:03:18.31#ibcon#read 6, iclass 38, count 0 2006.189.08:03:18.31#ibcon#end of sib2, iclass 38, count 0 2006.189.08:03:18.31#ibcon#*after write, iclass 38, count 0 2006.189.08:03:18.31#ibcon#*before return 0, iclass 38, count 0 2006.189.08:03:18.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:18.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:18.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:03:18.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:03:18.31$vc4f8/valo=2,572.99 2006.189.08:03:18.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.08:03:18.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.08:03:18.31#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:18.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:18.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:18.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:18.31#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:03:18.31#ibcon#first serial, iclass 40, count 0 2006.189.08:03:18.31#ibcon#enter sib2, iclass 40, count 0 2006.189.08:03:18.31#ibcon#flushed, iclass 40, count 0 2006.189.08:03:18.31#ibcon#about to write, iclass 40, count 0 2006.189.08:03:18.31#ibcon#wrote, iclass 40, count 0 2006.189.08:03:18.31#ibcon#about to read 3, iclass 40, count 0 2006.189.08:03:18.33#ibcon#read 3, iclass 40, count 0 2006.189.08:03:18.33#ibcon#about to read 4, iclass 40, count 0 2006.189.08:03:18.33#ibcon#read 4, iclass 40, count 0 2006.189.08:03:18.33#ibcon#about to read 5, iclass 40, count 0 2006.189.08:03:18.33#ibcon#read 5, iclass 40, count 0 2006.189.08:03:18.33#ibcon#about to read 6, iclass 40, count 0 2006.189.08:03:18.33#ibcon#read 6, iclass 40, count 0 2006.189.08:03:18.33#ibcon#end of sib2, iclass 40, count 0 2006.189.08:03:18.33#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:03:18.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:03:18.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:03:18.33#ibcon#*before write, iclass 40, count 0 2006.189.08:03:18.33#ibcon#enter sib2, iclass 40, count 0 2006.189.08:03:18.33#ibcon#flushed, iclass 40, count 0 2006.189.08:03:18.33#ibcon#about to write, iclass 40, count 0 2006.189.08:03:18.33#ibcon#wrote, iclass 40, count 0 2006.189.08:03:18.33#ibcon#about to read 3, iclass 40, count 0 2006.189.08:03:18.37#ibcon#read 3, iclass 40, count 0 2006.189.08:03:18.37#ibcon#about to read 4, iclass 40, count 0 2006.189.08:03:18.37#ibcon#read 4, iclass 40, count 0 2006.189.08:03:18.37#ibcon#about to read 5, iclass 40, count 0 2006.189.08:03:18.37#ibcon#read 5, iclass 40, count 0 2006.189.08:03:18.37#ibcon#about to read 6, iclass 40, count 0 2006.189.08:03:18.37#ibcon#read 6, iclass 40, count 0 2006.189.08:03:18.37#ibcon#end of sib2, iclass 40, count 0 2006.189.08:03:18.37#ibcon#*after write, iclass 40, count 0 2006.189.08:03:18.37#ibcon#*before return 0, iclass 40, count 0 2006.189.08:03:18.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:18.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:18.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:03:18.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:03:18.37$vc4f8/va=2,7 2006.189.08:03:18.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.08:03:18.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.08:03:18.37#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:18.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:18.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:18.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:18.43#ibcon#enter wrdev, iclass 4, count 2 2006.189.08:03:18.43#ibcon#first serial, iclass 4, count 2 2006.189.08:03:18.43#ibcon#enter sib2, iclass 4, count 2 2006.189.08:03:18.43#ibcon#flushed, iclass 4, count 2 2006.189.08:03:18.43#ibcon#about to write, iclass 4, count 2 2006.189.08:03:18.43#ibcon#wrote, iclass 4, count 2 2006.189.08:03:18.43#ibcon#about to read 3, iclass 4, count 2 2006.189.08:03:18.45#ibcon#read 3, iclass 4, count 2 2006.189.08:03:18.45#ibcon#about to read 4, iclass 4, count 2 2006.189.08:03:18.45#ibcon#read 4, iclass 4, count 2 2006.189.08:03:18.45#ibcon#about to read 5, iclass 4, count 2 2006.189.08:03:18.45#ibcon#read 5, iclass 4, count 2 2006.189.08:03:18.45#ibcon#about to read 6, iclass 4, count 2 2006.189.08:03:18.45#ibcon#read 6, iclass 4, count 2 2006.189.08:03:18.45#ibcon#end of sib2, iclass 4, count 2 2006.189.08:03:18.45#ibcon#*mode == 0, iclass 4, count 2 2006.189.08:03:18.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.08:03:18.45#ibcon#[25=AT02-07\r\n] 2006.189.08:03:18.45#ibcon#*before write, iclass 4, count 2 2006.189.08:03:18.45#ibcon#enter sib2, iclass 4, count 2 2006.189.08:03:18.45#ibcon#flushed, iclass 4, count 2 2006.189.08:03:18.45#ibcon#about to write, iclass 4, count 2 2006.189.08:03:18.45#ibcon#wrote, iclass 4, count 2 2006.189.08:03:18.45#ibcon#about to read 3, iclass 4, count 2 2006.189.08:03:18.48#ibcon#read 3, iclass 4, count 2 2006.189.08:03:18.48#ibcon#about to read 4, iclass 4, count 2 2006.189.08:03:18.48#ibcon#read 4, iclass 4, count 2 2006.189.08:03:18.48#ibcon#about to read 5, iclass 4, count 2 2006.189.08:03:18.48#ibcon#read 5, iclass 4, count 2 2006.189.08:03:18.48#ibcon#about to read 6, iclass 4, count 2 2006.189.08:03:18.48#ibcon#read 6, iclass 4, count 2 2006.189.08:03:18.48#ibcon#end of sib2, iclass 4, count 2 2006.189.08:03:18.48#ibcon#*after write, iclass 4, count 2 2006.189.08:03:18.48#ibcon#*before return 0, iclass 4, count 2 2006.189.08:03:18.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:18.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:18.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.08:03:18.48#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:18.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:18.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:18.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:18.60#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:03:18.60#ibcon#first serial, iclass 4, count 0 2006.189.08:03:18.60#ibcon#enter sib2, iclass 4, count 0 2006.189.08:03:18.60#ibcon#flushed, iclass 4, count 0 2006.189.08:03:18.60#ibcon#about to write, iclass 4, count 0 2006.189.08:03:18.60#ibcon#wrote, iclass 4, count 0 2006.189.08:03:18.60#ibcon#about to read 3, iclass 4, count 0 2006.189.08:03:18.62#ibcon#read 3, iclass 4, count 0 2006.189.08:03:18.62#ibcon#about to read 4, iclass 4, count 0 2006.189.08:03:18.62#ibcon#read 4, iclass 4, count 0 2006.189.08:03:18.62#ibcon#about to read 5, iclass 4, count 0 2006.189.08:03:18.62#ibcon#read 5, iclass 4, count 0 2006.189.08:03:18.62#ibcon#about to read 6, iclass 4, count 0 2006.189.08:03:18.62#ibcon#read 6, iclass 4, count 0 2006.189.08:03:18.62#ibcon#end of sib2, iclass 4, count 0 2006.189.08:03:18.62#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:03:18.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:03:18.62#ibcon#[25=USB\r\n] 2006.189.08:03:18.62#ibcon#*before write, iclass 4, count 0 2006.189.08:03:18.62#ibcon#enter sib2, iclass 4, count 0 2006.189.08:03:18.62#ibcon#flushed, iclass 4, count 0 2006.189.08:03:18.62#ibcon#about to write, iclass 4, count 0 2006.189.08:03:18.62#ibcon#wrote, iclass 4, count 0 2006.189.08:03:18.62#ibcon#about to read 3, iclass 4, count 0 2006.189.08:03:18.65#ibcon#read 3, iclass 4, count 0 2006.189.08:03:18.65#ibcon#about to read 4, iclass 4, count 0 2006.189.08:03:18.65#ibcon#read 4, iclass 4, count 0 2006.189.08:03:18.65#ibcon#about to read 5, iclass 4, count 0 2006.189.08:03:18.65#ibcon#read 5, iclass 4, count 0 2006.189.08:03:18.65#ibcon#about to read 6, iclass 4, count 0 2006.189.08:03:18.65#ibcon#read 6, iclass 4, count 0 2006.189.08:03:18.65#ibcon#end of sib2, iclass 4, count 0 2006.189.08:03:18.65#ibcon#*after write, iclass 4, count 0 2006.189.08:03:18.65#ibcon#*before return 0, iclass 4, count 0 2006.189.08:03:18.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:18.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:18.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:03:18.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:03:18.65$vc4f8/valo=3,672.99 2006.189.08:03:18.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.08:03:18.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.08:03:18.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:18.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:18.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:18.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:18.65#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:03:18.65#ibcon#first serial, iclass 6, count 0 2006.189.08:03:18.65#ibcon#enter sib2, iclass 6, count 0 2006.189.08:03:18.65#ibcon#flushed, iclass 6, count 0 2006.189.08:03:18.65#ibcon#about to write, iclass 6, count 0 2006.189.08:03:18.65#ibcon#wrote, iclass 6, count 0 2006.189.08:03:18.65#ibcon#about to read 3, iclass 6, count 0 2006.189.08:03:18.67#ibcon#read 3, iclass 6, count 0 2006.189.08:03:18.67#ibcon#about to read 4, iclass 6, count 0 2006.189.08:03:18.67#ibcon#read 4, iclass 6, count 0 2006.189.08:03:18.67#ibcon#about to read 5, iclass 6, count 0 2006.189.08:03:18.67#ibcon#read 5, iclass 6, count 0 2006.189.08:03:18.67#ibcon#about to read 6, iclass 6, count 0 2006.189.08:03:18.67#ibcon#read 6, iclass 6, count 0 2006.189.08:03:18.67#ibcon#end of sib2, iclass 6, count 0 2006.189.08:03:18.67#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:03:18.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:03:18.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:03:18.67#ibcon#*before write, iclass 6, count 0 2006.189.08:03:18.67#ibcon#enter sib2, iclass 6, count 0 2006.189.08:03:18.67#ibcon#flushed, iclass 6, count 0 2006.189.08:03:18.67#ibcon#about to write, iclass 6, count 0 2006.189.08:03:18.67#ibcon#wrote, iclass 6, count 0 2006.189.08:03:18.67#ibcon#about to read 3, iclass 6, count 0 2006.189.08:03:18.71#ibcon#read 3, iclass 6, count 0 2006.189.08:03:18.71#ibcon#about to read 4, iclass 6, count 0 2006.189.08:03:18.71#ibcon#read 4, iclass 6, count 0 2006.189.08:03:18.71#ibcon#about to read 5, iclass 6, count 0 2006.189.08:03:18.71#ibcon#read 5, iclass 6, count 0 2006.189.08:03:18.71#ibcon#about to read 6, iclass 6, count 0 2006.189.08:03:18.71#ibcon#read 6, iclass 6, count 0 2006.189.08:03:18.71#ibcon#end of sib2, iclass 6, count 0 2006.189.08:03:18.71#ibcon#*after write, iclass 6, count 0 2006.189.08:03:18.71#ibcon#*before return 0, iclass 6, count 0 2006.189.08:03:18.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:18.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:18.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:03:18.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:03:18.71$vc4f8/va=3,6 2006.189.08:03:18.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.08:03:18.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.08:03:18.71#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:18.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:18.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:18.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:18.77#ibcon#enter wrdev, iclass 10, count 2 2006.189.08:03:18.77#ibcon#first serial, iclass 10, count 2 2006.189.08:03:18.77#ibcon#enter sib2, iclass 10, count 2 2006.189.08:03:18.77#ibcon#flushed, iclass 10, count 2 2006.189.08:03:18.77#ibcon#about to write, iclass 10, count 2 2006.189.08:03:18.77#ibcon#wrote, iclass 10, count 2 2006.189.08:03:18.77#ibcon#about to read 3, iclass 10, count 2 2006.189.08:03:18.79#ibcon#read 3, iclass 10, count 2 2006.189.08:03:18.79#ibcon#about to read 4, iclass 10, count 2 2006.189.08:03:18.79#ibcon#read 4, iclass 10, count 2 2006.189.08:03:18.79#ibcon#about to read 5, iclass 10, count 2 2006.189.08:03:18.79#ibcon#read 5, iclass 10, count 2 2006.189.08:03:18.79#ibcon#about to read 6, iclass 10, count 2 2006.189.08:03:18.79#ibcon#read 6, iclass 10, count 2 2006.189.08:03:18.79#ibcon#end of sib2, iclass 10, count 2 2006.189.08:03:18.79#ibcon#*mode == 0, iclass 10, count 2 2006.189.08:03:18.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.08:03:18.79#ibcon#[25=AT03-06\r\n] 2006.189.08:03:18.79#ibcon#*before write, iclass 10, count 2 2006.189.08:03:18.79#ibcon#enter sib2, iclass 10, count 2 2006.189.08:03:18.79#ibcon#flushed, iclass 10, count 2 2006.189.08:03:18.79#ibcon#about to write, iclass 10, count 2 2006.189.08:03:18.79#ibcon#wrote, iclass 10, count 2 2006.189.08:03:18.79#ibcon#about to read 3, iclass 10, count 2 2006.189.08:03:18.82#ibcon#read 3, iclass 10, count 2 2006.189.08:03:18.82#ibcon#about to read 4, iclass 10, count 2 2006.189.08:03:18.82#ibcon#read 4, iclass 10, count 2 2006.189.08:03:18.82#ibcon#about to read 5, iclass 10, count 2 2006.189.08:03:18.82#ibcon#read 5, iclass 10, count 2 2006.189.08:03:18.82#ibcon#about to read 6, iclass 10, count 2 2006.189.08:03:18.82#ibcon#read 6, iclass 10, count 2 2006.189.08:03:18.82#ibcon#end of sib2, iclass 10, count 2 2006.189.08:03:18.82#ibcon#*after write, iclass 10, count 2 2006.189.08:03:18.82#ibcon#*before return 0, iclass 10, count 2 2006.189.08:03:18.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:18.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:18.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.08:03:18.82#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:18.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:18.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:18.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:18.94#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:03:18.94#ibcon#first serial, iclass 10, count 0 2006.189.08:03:18.94#ibcon#enter sib2, iclass 10, count 0 2006.189.08:03:18.94#ibcon#flushed, iclass 10, count 0 2006.189.08:03:18.94#ibcon#about to write, iclass 10, count 0 2006.189.08:03:18.94#ibcon#wrote, iclass 10, count 0 2006.189.08:03:18.94#ibcon#about to read 3, iclass 10, count 0 2006.189.08:03:18.96#ibcon#read 3, iclass 10, count 0 2006.189.08:03:18.96#ibcon#about to read 4, iclass 10, count 0 2006.189.08:03:18.96#ibcon#read 4, iclass 10, count 0 2006.189.08:03:18.96#ibcon#about to read 5, iclass 10, count 0 2006.189.08:03:18.96#ibcon#read 5, iclass 10, count 0 2006.189.08:03:18.96#ibcon#about to read 6, iclass 10, count 0 2006.189.08:03:18.96#ibcon#read 6, iclass 10, count 0 2006.189.08:03:18.96#ibcon#end of sib2, iclass 10, count 0 2006.189.08:03:18.96#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:03:18.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:03:18.96#ibcon#[25=USB\r\n] 2006.189.08:03:18.96#ibcon#*before write, iclass 10, count 0 2006.189.08:03:18.96#ibcon#enter sib2, iclass 10, count 0 2006.189.08:03:18.96#ibcon#flushed, iclass 10, count 0 2006.189.08:03:18.96#ibcon#about to write, iclass 10, count 0 2006.189.08:03:18.96#ibcon#wrote, iclass 10, count 0 2006.189.08:03:18.96#ibcon#about to read 3, iclass 10, count 0 2006.189.08:03:18.99#ibcon#read 3, iclass 10, count 0 2006.189.08:03:18.99#ibcon#about to read 4, iclass 10, count 0 2006.189.08:03:18.99#ibcon#read 4, iclass 10, count 0 2006.189.08:03:18.99#ibcon#about to read 5, iclass 10, count 0 2006.189.08:03:18.99#ibcon#read 5, iclass 10, count 0 2006.189.08:03:18.99#ibcon#about to read 6, iclass 10, count 0 2006.189.08:03:18.99#ibcon#read 6, iclass 10, count 0 2006.189.08:03:18.99#ibcon#end of sib2, iclass 10, count 0 2006.189.08:03:18.99#ibcon#*after write, iclass 10, count 0 2006.189.08:03:18.99#ibcon#*before return 0, iclass 10, count 0 2006.189.08:03:18.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:18.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:18.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:03:18.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:03:18.99$vc4f8/valo=4,832.99 2006.189.08:03:18.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.08:03:18.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.08:03:18.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:18.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:18.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:18.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:18.99#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:03:18.99#ibcon#first serial, iclass 12, count 0 2006.189.08:03:18.99#ibcon#enter sib2, iclass 12, count 0 2006.189.08:03:18.99#ibcon#flushed, iclass 12, count 0 2006.189.08:03:18.99#ibcon#about to write, iclass 12, count 0 2006.189.08:03:18.99#ibcon#wrote, iclass 12, count 0 2006.189.08:03:18.99#ibcon#about to read 3, iclass 12, count 0 2006.189.08:03:19.01#ibcon#read 3, iclass 12, count 0 2006.189.08:03:19.01#ibcon#about to read 4, iclass 12, count 0 2006.189.08:03:19.01#ibcon#read 4, iclass 12, count 0 2006.189.08:03:19.01#ibcon#about to read 5, iclass 12, count 0 2006.189.08:03:19.01#ibcon#read 5, iclass 12, count 0 2006.189.08:03:19.01#ibcon#about to read 6, iclass 12, count 0 2006.189.08:03:19.01#ibcon#read 6, iclass 12, count 0 2006.189.08:03:19.01#ibcon#end of sib2, iclass 12, count 0 2006.189.08:03:19.01#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:03:19.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:03:19.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:03:19.01#ibcon#*before write, iclass 12, count 0 2006.189.08:03:19.01#ibcon#enter sib2, iclass 12, count 0 2006.189.08:03:19.01#ibcon#flushed, iclass 12, count 0 2006.189.08:03:19.01#ibcon#about to write, iclass 12, count 0 2006.189.08:03:19.01#ibcon#wrote, iclass 12, count 0 2006.189.08:03:19.01#ibcon#about to read 3, iclass 12, count 0 2006.189.08:03:19.05#ibcon#read 3, iclass 12, count 0 2006.189.08:03:19.05#ibcon#about to read 4, iclass 12, count 0 2006.189.08:03:19.05#ibcon#read 4, iclass 12, count 0 2006.189.08:03:19.05#ibcon#about to read 5, iclass 12, count 0 2006.189.08:03:19.05#ibcon#read 5, iclass 12, count 0 2006.189.08:03:19.05#ibcon#about to read 6, iclass 12, count 0 2006.189.08:03:19.05#ibcon#read 6, iclass 12, count 0 2006.189.08:03:19.05#ibcon#end of sib2, iclass 12, count 0 2006.189.08:03:19.05#ibcon#*after write, iclass 12, count 0 2006.189.08:03:19.05#ibcon#*before return 0, iclass 12, count 0 2006.189.08:03:19.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:19.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:19.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:03:19.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:03:19.05$vc4f8/va=4,7 2006.189.08:03:19.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.08:03:19.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.08:03:19.05#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:19.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:19.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:19.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:19.11#ibcon#enter wrdev, iclass 14, count 2 2006.189.08:03:19.11#ibcon#first serial, iclass 14, count 2 2006.189.08:03:19.11#ibcon#enter sib2, iclass 14, count 2 2006.189.08:03:19.11#ibcon#flushed, iclass 14, count 2 2006.189.08:03:19.11#ibcon#about to write, iclass 14, count 2 2006.189.08:03:19.11#ibcon#wrote, iclass 14, count 2 2006.189.08:03:19.11#ibcon#about to read 3, iclass 14, count 2 2006.189.08:03:19.13#ibcon#read 3, iclass 14, count 2 2006.189.08:03:19.13#ibcon#about to read 4, iclass 14, count 2 2006.189.08:03:19.13#ibcon#read 4, iclass 14, count 2 2006.189.08:03:19.13#ibcon#about to read 5, iclass 14, count 2 2006.189.08:03:19.13#ibcon#read 5, iclass 14, count 2 2006.189.08:03:19.13#ibcon#about to read 6, iclass 14, count 2 2006.189.08:03:19.13#ibcon#read 6, iclass 14, count 2 2006.189.08:03:19.13#ibcon#end of sib2, iclass 14, count 2 2006.189.08:03:19.13#ibcon#*mode == 0, iclass 14, count 2 2006.189.08:03:19.13#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.08:03:19.13#ibcon#[25=AT04-07\r\n] 2006.189.08:03:19.13#ibcon#*before write, iclass 14, count 2 2006.189.08:03:19.13#ibcon#enter sib2, iclass 14, count 2 2006.189.08:03:19.13#ibcon#flushed, iclass 14, count 2 2006.189.08:03:19.13#ibcon#about to write, iclass 14, count 2 2006.189.08:03:19.13#ibcon#wrote, iclass 14, count 2 2006.189.08:03:19.13#ibcon#about to read 3, iclass 14, count 2 2006.189.08:03:19.16#ibcon#read 3, iclass 14, count 2 2006.189.08:03:19.16#ibcon#about to read 4, iclass 14, count 2 2006.189.08:03:19.16#ibcon#read 4, iclass 14, count 2 2006.189.08:03:19.16#ibcon#about to read 5, iclass 14, count 2 2006.189.08:03:19.16#ibcon#read 5, iclass 14, count 2 2006.189.08:03:19.16#ibcon#about to read 6, iclass 14, count 2 2006.189.08:03:19.16#ibcon#read 6, iclass 14, count 2 2006.189.08:03:19.16#ibcon#end of sib2, iclass 14, count 2 2006.189.08:03:19.16#ibcon#*after write, iclass 14, count 2 2006.189.08:03:19.16#ibcon#*before return 0, iclass 14, count 2 2006.189.08:03:19.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:19.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:19.16#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.08:03:19.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:19.16#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:19.28#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:19.28#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:19.28#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:03:19.28#ibcon#first serial, iclass 14, count 0 2006.189.08:03:19.28#ibcon#enter sib2, iclass 14, count 0 2006.189.08:03:19.28#ibcon#flushed, iclass 14, count 0 2006.189.08:03:19.28#ibcon#about to write, iclass 14, count 0 2006.189.08:03:19.28#ibcon#wrote, iclass 14, count 0 2006.189.08:03:19.28#ibcon#about to read 3, iclass 14, count 0 2006.189.08:03:19.30#ibcon#read 3, iclass 14, count 0 2006.189.08:03:19.30#ibcon#about to read 4, iclass 14, count 0 2006.189.08:03:19.30#ibcon#read 4, iclass 14, count 0 2006.189.08:03:19.30#ibcon#about to read 5, iclass 14, count 0 2006.189.08:03:19.30#ibcon#read 5, iclass 14, count 0 2006.189.08:03:19.30#ibcon#about to read 6, iclass 14, count 0 2006.189.08:03:19.30#ibcon#read 6, iclass 14, count 0 2006.189.08:03:19.30#ibcon#end of sib2, iclass 14, count 0 2006.189.08:03:19.30#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:03:19.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:03:19.30#ibcon#[25=USB\r\n] 2006.189.08:03:19.30#ibcon#*before write, iclass 14, count 0 2006.189.08:03:19.30#ibcon#enter sib2, iclass 14, count 0 2006.189.08:03:19.30#ibcon#flushed, iclass 14, count 0 2006.189.08:03:19.30#ibcon#about to write, iclass 14, count 0 2006.189.08:03:19.30#ibcon#wrote, iclass 14, count 0 2006.189.08:03:19.30#ibcon#about to read 3, iclass 14, count 0 2006.189.08:03:19.33#ibcon#read 3, iclass 14, count 0 2006.189.08:03:19.33#ibcon#about to read 4, iclass 14, count 0 2006.189.08:03:19.33#ibcon#read 4, iclass 14, count 0 2006.189.08:03:19.33#ibcon#about to read 5, iclass 14, count 0 2006.189.08:03:19.33#ibcon#read 5, iclass 14, count 0 2006.189.08:03:19.33#ibcon#about to read 6, iclass 14, count 0 2006.189.08:03:19.33#ibcon#read 6, iclass 14, count 0 2006.189.08:03:19.33#ibcon#end of sib2, iclass 14, count 0 2006.189.08:03:19.33#ibcon#*after write, iclass 14, count 0 2006.189.08:03:19.33#ibcon#*before return 0, iclass 14, count 0 2006.189.08:03:19.33#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:19.33#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:19.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:03:19.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:03:19.33$vc4f8/valo=5,652.99 2006.189.08:03:19.33#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.08:03:19.33#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.08:03:19.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:19.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:19.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:19.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:19.33#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:03:19.33#ibcon#first serial, iclass 16, count 0 2006.189.08:03:19.33#ibcon#enter sib2, iclass 16, count 0 2006.189.08:03:19.33#ibcon#flushed, iclass 16, count 0 2006.189.08:03:19.33#ibcon#about to write, iclass 16, count 0 2006.189.08:03:19.33#ibcon#wrote, iclass 16, count 0 2006.189.08:03:19.33#ibcon#about to read 3, iclass 16, count 0 2006.189.08:03:19.35#ibcon#read 3, iclass 16, count 0 2006.189.08:03:19.35#ibcon#about to read 4, iclass 16, count 0 2006.189.08:03:19.35#ibcon#read 4, iclass 16, count 0 2006.189.08:03:19.35#ibcon#about to read 5, iclass 16, count 0 2006.189.08:03:19.35#ibcon#read 5, iclass 16, count 0 2006.189.08:03:19.35#ibcon#about to read 6, iclass 16, count 0 2006.189.08:03:19.35#ibcon#read 6, iclass 16, count 0 2006.189.08:03:19.35#ibcon#end of sib2, iclass 16, count 0 2006.189.08:03:19.35#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:03:19.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:03:19.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:03:19.35#ibcon#*before write, iclass 16, count 0 2006.189.08:03:19.35#ibcon#enter sib2, iclass 16, count 0 2006.189.08:03:19.35#ibcon#flushed, iclass 16, count 0 2006.189.08:03:19.35#ibcon#about to write, iclass 16, count 0 2006.189.08:03:19.35#ibcon#wrote, iclass 16, count 0 2006.189.08:03:19.35#ibcon#about to read 3, iclass 16, count 0 2006.189.08:03:19.39#ibcon#read 3, iclass 16, count 0 2006.189.08:03:19.39#ibcon#about to read 4, iclass 16, count 0 2006.189.08:03:19.39#ibcon#read 4, iclass 16, count 0 2006.189.08:03:19.39#ibcon#about to read 5, iclass 16, count 0 2006.189.08:03:19.39#ibcon#read 5, iclass 16, count 0 2006.189.08:03:19.39#ibcon#about to read 6, iclass 16, count 0 2006.189.08:03:19.39#ibcon#read 6, iclass 16, count 0 2006.189.08:03:19.39#ibcon#end of sib2, iclass 16, count 0 2006.189.08:03:19.39#ibcon#*after write, iclass 16, count 0 2006.189.08:03:19.39#ibcon#*before return 0, iclass 16, count 0 2006.189.08:03:19.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:19.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:19.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:03:19.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:03:19.39$vc4f8/va=5,7 2006.189.08:03:19.39#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.08:03:19.39#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.08:03:19.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:19.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:03:19.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:03:19.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:03:19.45#ibcon#enter wrdev, iclass 18, count 2 2006.189.08:03:19.45#ibcon#first serial, iclass 18, count 2 2006.189.08:03:19.45#ibcon#enter sib2, iclass 18, count 2 2006.189.08:03:19.45#ibcon#flushed, iclass 18, count 2 2006.189.08:03:19.45#ibcon#about to write, iclass 18, count 2 2006.189.08:03:19.45#ibcon#wrote, iclass 18, count 2 2006.189.08:03:19.45#ibcon#about to read 3, iclass 18, count 2 2006.189.08:03:19.47#ibcon#read 3, iclass 18, count 2 2006.189.08:03:19.47#ibcon#about to read 4, iclass 18, count 2 2006.189.08:03:19.47#ibcon#read 4, iclass 18, count 2 2006.189.08:03:19.47#ibcon#about to read 5, iclass 18, count 2 2006.189.08:03:19.47#ibcon#read 5, iclass 18, count 2 2006.189.08:03:19.47#ibcon#about to read 6, iclass 18, count 2 2006.189.08:03:19.47#ibcon#read 6, iclass 18, count 2 2006.189.08:03:19.47#ibcon#end of sib2, iclass 18, count 2 2006.189.08:03:19.47#ibcon#*mode == 0, iclass 18, count 2 2006.189.08:03:19.47#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.08:03:19.47#ibcon#[25=AT05-07\r\n] 2006.189.08:03:19.47#ibcon#*before write, iclass 18, count 2 2006.189.08:03:19.47#ibcon#enter sib2, iclass 18, count 2 2006.189.08:03:19.47#ibcon#flushed, iclass 18, count 2 2006.189.08:03:19.47#ibcon#about to write, iclass 18, count 2 2006.189.08:03:19.47#ibcon#wrote, iclass 18, count 2 2006.189.08:03:19.47#ibcon#about to read 3, iclass 18, count 2 2006.189.08:03:19.50#ibcon#read 3, iclass 18, count 2 2006.189.08:03:19.50#ibcon#about to read 4, iclass 18, count 2 2006.189.08:03:19.50#ibcon#read 4, iclass 18, count 2 2006.189.08:03:19.50#ibcon#about to read 5, iclass 18, count 2 2006.189.08:03:19.50#ibcon#read 5, iclass 18, count 2 2006.189.08:03:19.50#ibcon#about to read 6, iclass 18, count 2 2006.189.08:03:19.50#ibcon#read 6, iclass 18, count 2 2006.189.08:03:19.50#ibcon#end of sib2, iclass 18, count 2 2006.189.08:03:19.50#ibcon#*after write, iclass 18, count 2 2006.189.08:03:19.50#ibcon#*before return 0, iclass 18, count 2 2006.189.08:03:19.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:03:19.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:03:19.50#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.08:03:19.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:19.50#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:03:19.62#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:03:19.62#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:03:19.62#ibcon#enter wrdev, iclass 18, count 0 2006.189.08:03:19.62#ibcon#first serial, iclass 18, count 0 2006.189.08:03:19.62#ibcon#enter sib2, iclass 18, count 0 2006.189.08:03:19.62#ibcon#flushed, iclass 18, count 0 2006.189.08:03:19.62#ibcon#about to write, iclass 18, count 0 2006.189.08:03:19.62#ibcon#wrote, iclass 18, count 0 2006.189.08:03:19.62#ibcon#about to read 3, iclass 18, count 0 2006.189.08:03:19.64#ibcon#read 3, iclass 18, count 0 2006.189.08:03:19.64#ibcon#about to read 4, iclass 18, count 0 2006.189.08:03:19.64#ibcon#read 4, iclass 18, count 0 2006.189.08:03:19.64#ibcon#about to read 5, iclass 18, count 0 2006.189.08:03:19.64#ibcon#read 5, iclass 18, count 0 2006.189.08:03:19.64#ibcon#about to read 6, iclass 18, count 0 2006.189.08:03:19.64#ibcon#read 6, iclass 18, count 0 2006.189.08:03:19.64#ibcon#end of sib2, iclass 18, count 0 2006.189.08:03:19.64#ibcon#*mode == 0, iclass 18, count 0 2006.189.08:03:19.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.08:03:19.64#ibcon#[25=USB\r\n] 2006.189.08:03:19.64#ibcon#*before write, iclass 18, count 0 2006.189.08:03:19.64#ibcon#enter sib2, iclass 18, count 0 2006.189.08:03:19.64#ibcon#flushed, iclass 18, count 0 2006.189.08:03:19.64#ibcon#about to write, iclass 18, count 0 2006.189.08:03:19.64#ibcon#wrote, iclass 18, count 0 2006.189.08:03:19.64#ibcon#about to read 3, iclass 18, count 0 2006.189.08:03:19.67#ibcon#read 3, iclass 18, count 0 2006.189.08:03:19.67#ibcon#about to read 4, iclass 18, count 0 2006.189.08:03:19.67#ibcon#read 4, iclass 18, count 0 2006.189.08:03:19.67#ibcon#about to read 5, iclass 18, count 0 2006.189.08:03:19.67#ibcon#read 5, iclass 18, count 0 2006.189.08:03:19.67#ibcon#about to read 6, iclass 18, count 0 2006.189.08:03:19.67#ibcon#read 6, iclass 18, count 0 2006.189.08:03:19.67#ibcon#end of sib2, iclass 18, count 0 2006.189.08:03:19.67#ibcon#*after write, iclass 18, count 0 2006.189.08:03:19.67#ibcon#*before return 0, iclass 18, count 0 2006.189.08:03:19.67#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:03:19.67#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:03:19.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.08:03:19.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.08:03:19.67$vc4f8/valo=6,772.99 2006.189.08:03:19.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.08:03:19.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.08:03:19.67#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:19.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:03:19.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:03:19.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:03:19.67#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:03:19.67#ibcon#first serial, iclass 20, count 0 2006.189.08:03:19.67#ibcon#enter sib2, iclass 20, count 0 2006.189.08:03:19.67#ibcon#flushed, iclass 20, count 0 2006.189.08:03:19.67#ibcon#about to write, iclass 20, count 0 2006.189.08:03:19.67#ibcon#wrote, iclass 20, count 0 2006.189.08:03:19.67#ibcon#about to read 3, iclass 20, count 0 2006.189.08:03:19.69#ibcon#read 3, iclass 20, count 0 2006.189.08:03:19.69#ibcon#about to read 4, iclass 20, count 0 2006.189.08:03:19.69#ibcon#read 4, iclass 20, count 0 2006.189.08:03:19.69#ibcon#about to read 5, iclass 20, count 0 2006.189.08:03:19.69#ibcon#read 5, iclass 20, count 0 2006.189.08:03:19.69#ibcon#about to read 6, iclass 20, count 0 2006.189.08:03:19.69#ibcon#read 6, iclass 20, count 0 2006.189.08:03:19.69#ibcon#end of sib2, iclass 20, count 0 2006.189.08:03:19.69#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:03:19.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:03:19.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:03:19.69#ibcon#*before write, iclass 20, count 0 2006.189.08:03:19.69#ibcon#enter sib2, iclass 20, count 0 2006.189.08:03:19.69#ibcon#flushed, iclass 20, count 0 2006.189.08:03:19.69#ibcon#about to write, iclass 20, count 0 2006.189.08:03:19.69#ibcon#wrote, iclass 20, count 0 2006.189.08:03:19.69#ibcon#about to read 3, iclass 20, count 0 2006.189.08:03:19.73#ibcon#read 3, iclass 20, count 0 2006.189.08:03:19.73#ibcon#about to read 4, iclass 20, count 0 2006.189.08:03:19.73#ibcon#read 4, iclass 20, count 0 2006.189.08:03:19.73#ibcon#about to read 5, iclass 20, count 0 2006.189.08:03:19.73#ibcon#read 5, iclass 20, count 0 2006.189.08:03:19.73#ibcon#about to read 6, iclass 20, count 0 2006.189.08:03:19.73#ibcon#read 6, iclass 20, count 0 2006.189.08:03:19.73#ibcon#end of sib2, iclass 20, count 0 2006.189.08:03:19.73#ibcon#*after write, iclass 20, count 0 2006.189.08:03:19.73#ibcon#*before return 0, iclass 20, count 0 2006.189.08:03:19.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:03:19.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:03:19.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:03:19.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:03:19.73$vc4f8/va=6,6 2006.189.08:03:19.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.08:03:19.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.08:03:19.73#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:19.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:03:19.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:03:19.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:03:19.79#ibcon#enter wrdev, iclass 22, count 2 2006.189.08:03:19.79#ibcon#first serial, iclass 22, count 2 2006.189.08:03:19.79#ibcon#enter sib2, iclass 22, count 2 2006.189.08:03:19.79#ibcon#flushed, iclass 22, count 2 2006.189.08:03:19.79#ibcon#about to write, iclass 22, count 2 2006.189.08:03:19.79#ibcon#wrote, iclass 22, count 2 2006.189.08:03:19.79#ibcon#about to read 3, iclass 22, count 2 2006.189.08:03:19.81#ibcon#read 3, iclass 22, count 2 2006.189.08:03:19.81#ibcon#about to read 4, iclass 22, count 2 2006.189.08:03:19.81#ibcon#read 4, iclass 22, count 2 2006.189.08:03:19.81#ibcon#about to read 5, iclass 22, count 2 2006.189.08:03:19.81#ibcon#read 5, iclass 22, count 2 2006.189.08:03:19.81#ibcon#about to read 6, iclass 22, count 2 2006.189.08:03:19.81#ibcon#read 6, iclass 22, count 2 2006.189.08:03:19.81#ibcon#end of sib2, iclass 22, count 2 2006.189.08:03:19.81#ibcon#*mode == 0, iclass 22, count 2 2006.189.08:03:19.81#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.08:03:19.81#ibcon#[25=AT06-06\r\n] 2006.189.08:03:19.81#ibcon#*before write, iclass 22, count 2 2006.189.08:03:19.81#ibcon#enter sib2, iclass 22, count 2 2006.189.08:03:19.81#ibcon#flushed, iclass 22, count 2 2006.189.08:03:19.81#ibcon#about to write, iclass 22, count 2 2006.189.08:03:19.81#ibcon#wrote, iclass 22, count 2 2006.189.08:03:19.81#ibcon#about to read 3, iclass 22, count 2 2006.189.08:03:19.84#ibcon#read 3, iclass 22, count 2 2006.189.08:03:19.84#ibcon#about to read 4, iclass 22, count 2 2006.189.08:03:19.84#ibcon#read 4, iclass 22, count 2 2006.189.08:03:19.84#ibcon#about to read 5, iclass 22, count 2 2006.189.08:03:19.84#ibcon#read 5, iclass 22, count 2 2006.189.08:03:19.84#ibcon#about to read 6, iclass 22, count 2 2006.189.08:03:19.84#ibcon#read 6, iclass 22, count 2 2006.189.08:03:19.84#ibcon#end of sib2, iclass 22, count 2 2006.189.08:03:19.84#ibcon#*after write, iclass 22, count 2 2006.189.08:03:19.84#ibcon#*before return 0, iclass 22, count 2 2006.189.08:03:19.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:03:19.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:03:19.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.08:03:19.84#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:19.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:03:19.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:03:19.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:03:19.96#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:03:19.96#ibcon#first serial, iclass 22, count 0 2006.189.08:03:19.96#ibcon#enter sib2, iclass 22, count 0 2006.189.08:03:19.96#ibcon#flushed, iclass 22, count 0 2006.189.08:03:19.96#ibcon#about to write, iclass 22, count 0 2006.189.08:03:19.96#ibcon#wrote, iclass 22, count 0 2006.189.08:03:19.96#ibcon#about to read 3, iclass 22, count 0 2006.189.08:03:19.98#ibcon#read 3, iclass 22, count 0 2006.189.08:03:19.98#ibcon#about to read 4, iclass 22, count 0 2006.189.08:03:19.98#ibcon#read 4, iclass 22, count 0 2006.189.08:03:19.98#ibcon#about to read 5, iclass 22, count 0 2006.189.08:03:19.98#ibcon#read 5, iclass 22, count 0 2006.189.08:03:19.98#ibcon#about to read 6, iclass 22, count 0 2006.189.08:03:19.98#ibcon#read 6, iclass 22, count 0 2006.189.08:03:19.98#ibcon#end of sib2, iclass 22, count 0 2006.189.08:03:19.98#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:03:19.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:03:19.98#ibcon#[25=USB\r\n] 2006.189.08:03:19.98#ibcon#*before write, iclass 22, count 0 2006.189.08:03:19.98#ibcon#enter sib2, iclass 22, count 0 2006.189.08:03:19.98#ibcon#flushed, iclass 22, count 0 2006.189.08:03:19.98#ibcon#about to write, iclass 22, count 0 2006.189.08:03:19.98#ibcon#wrote, iclass 22, count 0 2006.189.08:03:19.98#ibcon#about to read 3, iclass 22, count 0 2006.189.08:03:20.01#ibcon#read 3, iclass 22, count 0 2006.189.08:03:20.01#ibcon#about to read 4, iclass 22, count 0 2006.189.08:03:20.01#ibcon#read 4, iclass 22, count 0 2006.189.08:03:20.01#ibcon#about to read 5, iclass 22, count 0 2006.189.08:03:20.01#ibcon#read 5, iclass 22, count 0 2006.189.08:03:20.01#ibcon#about to read 6, iclass 22, count 0 2006.189.08:03:20.01#ibcon#read 6, iclass 22, count 0 2006.189.08:03:20.01#ibcon#end of sib2, iclass 22, count 0 2006.189.08:03:20.01#ibcon#*after write, iclass 22, count 0 2006.189.08:03:20.01#ibcon#*before return 0, iclass 22, count 0 2006.189.08:03:20.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:03:20.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:03:20.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:03:20.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:03:20.01$vc4f8/valo=7,832.99 2006.189.08:03:20.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.08:03:20.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.08:03:20.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:20.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:20.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:20.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:20.01#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:03:20.01#ibcon#first serial, iclass 24, count 0 2006.189.08:03:20.01#ibcon#enter sib2, iclass 24, count 0 2006.189.08:03:20.01#ibcon#flushed, iclass 24, count 0 2006.189.08:03:20.01#ibcon#about to write, iclass 24, count 0 2006.189.08:03:20.01#ibcon#wrote, iclass 24, count 0 2006.189.08:03:20.01#ibcon#about to read 3, iclass 24, count 0 2006.189.08:03:20.03#ibcon#read 3, iclass 24, count 0 2006.189.08:03:20.03#ibcon#about to read 4, iclass 24, count 0 2006.189.08:03:20.03#ibcon#read 4, iclass 24, count 0 2006.189.08:03:20.03#ibcon#about to read 5, iclass 24, count 0 2006.189.08:03:20.03#ibcon#read 5, iclass 24, count 0 2006.189.08:03:20.03#ibcon#about to read 6, iclass 24, count 0 2006.189.08:03:20.03#ibcon#read 6, iclass 24, count 0 2006.189.08:03:20.03#ibcon#end of sib2, iclass 24, count 0 2006.189.08:03:20.03#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:03:20.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:03:20.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:03:20.03#ibcon#*before write, iclass 24, count 0 2006.189.08:03:20.03#ibcon#enter sib2, iclass 24, count 0 2006.189.08:03:20.03#ibcon#flushed, iclass 24, count 0 2006.189.08:03:20.03#ibcon#about to write, iclass 24, count 0 2006.189.08:03:20.03#ibcon#wrote, iclass 24, count 0 2006.189.08:03:20.03#ibcon#about to read 3, iclass 24, count 0 2006.189.08:03:20.07#ibcon#read 3, iclass 24, count 0 2006.189.08:03:20.07#ibcon#about to read 4, iclass 24, count 0 2006.189.08:03:20.07#ibcon#read 4, iclass 24, count 0 2006.189.08:03:20.07#ibcon#about to read 5, iclass 24, count 0 2006.189.08:03:20.07#ibcon#read 5, iclass 24, count 0 2006.189.08:03:20.07#ibcon#about to read 6, iclass 24, count 0 2006.189.08:03:20.07#ibcon#read 6, iclass 24, count 0 2006.189.08:03:20.07#ibcon#end of sib2, iclass 24, count 0 2006.189.08:03:20.07#ibcon#*after write, iclass 24, count 0 2006.189.08:03:20.07#ibcon#*before return 0, iclass 24, count 0 2006.189.08:03:20.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:20.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:20.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:03:20.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:03:20.07$vc4f8/va=7,6 2006.189.08:03:20.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.08:03:20.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.08:03:20.07#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:20.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:03:20.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:03:20.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:03:20.13#ibcon#enter wrdev, iclass 26, count 2 2006.189.08:03:20.13#ibcon#first serial, iclass 26, count 2 2006.189.08:03:20.13#ibcon#enter sib2, iclass 26, count 2 2006.189.08:03:20.13#ibcon#flushed, iclass 26, count 2 2006.189.08:03:20.13#ibcon#about to write, iclass 26, count 2 2006.189.08:03:20.13#ibcon#wrote, iclass 26, count 2 2006.189.08:03:20.13#ibcon#about to read 3, iclass 26, count 2 2006.189.08:03:20.15#ibcon#read 3, iclass 26, count 2 2006.189.08:03:20.15#ibcon#about to read 4, iclass 26, count 2 2006.189.08:03:20.15#ibcon#read 4, iclass 26, count 2 2006.189.08:03:20.15#ibcon#about to read 5, iclass 26, count 2 2006.189.08:03:20.15#ibcon#read 5, iclass 26, count 2 2006.189.08:03:20.15#ibcon#about to read 6, iclass 26, count 2 2006.189.08:03:20.15#ibcon#read 6, iclass 26, count 2 2006.189.08:03:20.15#ibcon#end of sib2, iclass 26, count 2 2006.189.08:03:20.15#ibcon#*mode == 0, iclass 26, count 2 2006.189.08:03:20.15#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.08:03:20.15#ibcon#[25=AT07-06\r\n] 2006.189.08:03:20.15#ibcon#*before write, iclass 26, count 2 2006.189.08:03:20.15#ibcon#enter sib2, iclass 26, count 2 2006.189.08:03:20.15#ibcon#flushed, iclass 26, count 2 2006.189.08:03:20.15#ibcon#about to write, iclass 26, count 2 2006.189.08:03:20.15#ibcon#wrote, iclass 26, count 2 2006.189.08:03:20.15#ibcon#about to read 3, iclass 26, count 2 2006.189.08:03:20.18#ibcon#read 3, iclass 26, count 2 2006.189.08:03:20.18#ibcon#about to read 4, iclass 26, count 2 2006.189.08:03:20.18#ibcon#read 4, iclass 26, count 2 2006.189.08:03:20.18#ibcon#about to read 5, iclass 26, count 2 2006.189.08:03:20.18#ibcon#read 5, iclass 26, count 2 2006.189.08:03:20.18#ibcon#about to read 6, iclass 26, count 2 2006.189.08:03:20.18#ibcon#read 6, iclass 26, count 2 2006.189.08:03:20.18#ibcon#end of sib2, iclass 26, count 2 2006.189.08:03:20.18#ibcon#*after write, iclass 26, count 2 2006.189.08:03:20.18#ibcon#*before return 0, iclass 26, count 2 2006.189.08:03:20.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:03:20.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:03:20.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.08:03:20.18#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:20.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:03:20.30#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:03:20.30#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:03:20.30#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:03:20.30#ibcon#first serial, iclass 26, count 0 2006.189.08:03:20.30#ibcon#enter sib2, iclass 26, count 0 2006.189.08:03:20.30#ibcon#flushed, iclass 26, count 0 2006.189.08:03:20.30#ibcon#about to write, iclass 26, count 0 2006.189.08:03:20.30#ibcon#wrote, iclass 26, count 0 2006.189.08:03:20.30#ibcon#about to read 3, iclass 26, count 0 2006.189.08:03:20.32#ibcon#read 3, iclass 26, count 0 2006.189.08:03:20.32#ibcon#about to read 4, iclass 26, count 0 2006.189.08:03:20.32#ibcon#read 4, iclass 26, count 0 2006.189.08:03:20.32#ibcon#about to read 5, iclass 26, count 0 2006.189.08:03:20.32#ibcon#read 5, iclass 26, count 0 2006.189.08:03:20.32#ibcon#about to read 6, iclass 26, count 0 2006.189.08:03:20.32#ibcon#read 6, iclass 26, count 0 2006.189.08:03:20.32#ibcon#end of sib2, iclass 26, count 0 2006.189.08:03:20.32#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:03:20.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:03:20.32#ibcon#[25=USB\r\n] 2006.189.08:03:20.32#ibcon#*before write, iclass 26, count 0 2006.189.08:03:20.32#ibcon#enter sib2, iclass 26, count 0 2006.189.08:03:20.32#ibcon#flushed, iclass 26, count 0 2006.189.08:03:20.32#ibcon#about to write, iclass 26, count 0 2006.189.08:03:20.32#ibcon#wrote, iclass 26, count 0 2006.189.08:03:20.32#ibcon#about to read 3, iclass 26, count 0 2006.189.08:03:20.35#ibcon#read 3, iclass 26, count 0 2006.189.08:03:20.35#ibcon#about to read 4, iclass 26, count 0 2006.189.08:03:20.35#ibcon#read 4, iclass 26, count 0 2006.189.08:03:20.35#ibcon#about to read 5, iclass 26, count 0 2006.189.08:03:20.35#ibcon#read 5, iclass 26, count 0 2006.189.08:03:20.35#ibcon#about to read 6, iclass 26, count 0 2006.189.08:03:20.35#ibcon#read 6, iclass 26, count 0 2006.189.08:03:20.35#ibcon#end of sib2, iclass 26, count 0 2006.189.08:03:20.35#ibcon#*after write, iclass 26, count 0 2006.189.08:03:20.35#ibcon#*before return 0, iclass 26, count 0 2006.189.08:03:20.35#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:03:20.35#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:03:20.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:03:20.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:03:20.35$vc4f8/valo=8,852.99 2006.189.08:03:20.35#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.08:03:20.35#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.08:03:20.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:20.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:03:20.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:03:20.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:03:20.35#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:03:20.35#ibcon#first serial, iclass 28, count 0 2006.189.08:03:20.35#ibcon#enter sib2, iclass 28, count 0 2006.189.08:03:20.35#ibcon#flushed, iclass 28, count 0 2006.189.08:03:20.35#ibcon#about to write, iclass 28, count 0 2006.189.08:03:20.35#ibcon#wrote, iclass 28, count 0 2006.189.08:03:20.35#ibcon#about to read 3, iclass 28, count 0 2006.189.08:03:20.37#ibcon#read 3, iclass 28, count 0 2006.189.08:03:20.37#ibcon#about to read 4, iclass 28, count 0 2006.189.08:03:20.37#ibcon#read 4, iclass 28, count 0 2006.189.08:03:20.37#ibcon#about to read 5, iclass 28, count 0 2006.189.08:03:20.37#ibcon#read 5, iclass 28, count 0 2006.189.08:03:20.37#ibcon#about to read 6, iclass 28, count 0 2006.189.08:03:20.37#ibcon#read 6, iclass 28, count 0 2006.189.08:03:20.37#ibcon#end of sib2, iclass 28, count 0 2006.189.08:03:20.37#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:03:20.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:03:20.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:03:20.37#ibcon#*before write, iclass 28, count 0 2006.189.08:03:20.37#ibcon#enter sib2, iclass 28, count 0 2006.189.08:03:20.37#ibcon#flushed, iclass 28, count 0 2006.189.08:03:20.37#ibcon#about to write, iclass 28, count 0 2006.189.08:03:20.37#ibcon#wrote, iclass 28, count 0 2006.189.08:03:20.37#ibcon#about to read 3, iclass 28, count 0 2006.189.08:03:20.41#ibcon#read 3, iclass 28, count 0 2006.189.08:03:20.41#ibcon#about to read 4, iclass 28, count 0 2006.189.08:03:20.41#ibcon#read 4, iclass 28, count 0 2006.189.08:03:20.41#ibcon#about to read 5, iclass 28, count 0 2006.189.08:03:20.41#ibcon#read 5, iclass 28, count 0 2006.189.08:03:20.41#ibcon#about to read 6, iclass 28, count 0 2006.189.08:03:20.41#ibcon#read 6, iclass 28, count 0 2006.189.08:03:20.41#ibcon#end of sib2, iclass 28, count 0 2006.189.08:03:20.41#ibcon#*after write, iclass 28, count 0 2006.189.08:03:20.41#ibcon#*before return 0, iclass 28, count 0 2006.189.08:03:20.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:03:20.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:03:20.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:03:20.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:03:20.41$vc4f8/va=8,6 2006.189.08:03:20.41#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.08:03:20.41#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.08:03:20.41#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:20.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:03:20.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:03:20.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:03:20.47#ibcon#enter wrdev, iclass 30, count 2 2006.189.08:03:20.47#ibcon#first serial, iclass 30, count 2 2006.189.08:03:20.47#ibcon#enter sib2, iclass 30, count 2 2006.189.08:03:20.47#ibcon#flushed, iclass 30, count 2 2006.189.08:03:20.47#ibcon#about to write, iclass 30, count 2 2006.189.08:03:20.47#ibcon#wrote, iclass 30, count 2 2006.189.08:03:20.47#ibcon#about to read 3, iclass 30, count 2 2006.189.08:03:20.49#ibcon#read 3, iclass 30, count 2 2006.189.08:03:20.49#ibcon#about to read 4, iclass 30, count 2 2006.189.08:03:20.49#ibcon#read 4, iclass 30, count 2 2006.189.08:03:20.49#ibcon#about to read 5, iclass 30, count 2 2006.189.08:03:20.49#ibcon#read 5, iclass 30, count 2 2006.189.08:03:20.49#ibcon#about to read 6, iclass 30, count 2 2006.189.08:03:20.49#ibcon#read 6, iclass 30, count 2 2006.189.08:03:20.49#ibcon#end of sib2, iclass 30, count 2 2006.189.08:03:20.49#ibcon#*mode == 0, iclass 30, count 2 2006.189.08:03:20.49#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.08:03:20.49#ibcon#[25=AT08-06\r\n] 2006.189.08:03:20.49#ibcon#*before write, iclass 30, count 2 2006.189.08:03:20.49#ibcon#enter sib2, iclass 30, count 2 2006.189.08:03:20.49#ibcon#flushed, iclass 30, count 2 2006.189.08:03:20.49#ibcon#about to write, iclass 30, count 2 2006.189.08:03:20.49#ibcon#wrote, iclass 30, count 2 2006.189.08:03:20.49#ibcon#about to read 3, iclass 30, count 2 2006.189.08:03:20.52#ibcon#read 3, iclass 30, count 2 2006.189.08:03:20.52#ibcon#about to read 4, iclass 30, count 2 2006.189.08:03:20.52#ibcon#read 4, iclass 30, count 2 2006.189.08:03:20.52#ibcon#about to read 5, iclass 30, count 2 2006.189.08:03:20.52#ibcon#read 5, iclass 30, count 2 2006.189.08:03:20.52#ibcon#about to read 6, iclass 30, count 2 2006.189.08:03:20.52#ibcon#read 6, iclass 30, count 2 2006.189.08:03:20.52#ibcon#end of sib2, iclass 30, count 2 2006.189.08:03:20.52#ibcon#*after write, iclass 30, count 2 2006.189.08:03:20.52#ibcon#*before return 0, iclass 30, count 2 2006.189.08:03:20.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:03:20.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:03:20.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.08:03:20.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:20.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:03:20.64#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:03:20.64#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:03:20.64#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:03:20.64#ibcon#first serial, iclass 30, count 0 2006.189.08:03:20.64#ibcon#enter sib2, iclass 30, count 0 2006.189.08:03:20.64#ibcon#flushed, iclass 30, count 0 2006.189.08:03:20.64#ibcon#about to write, iclass 30, count 0 2006.189.08:03:20.64#ibcon#wrote, iclass 30, count 0 2006.189.08:03:20.64#ibcon#about to read 3, iclass 30, count 0 2006.189.08:03:20.66#ibcon#read 3, iclass 30, count 0 2006.189.08:03:20.66#ibcon#about to read 4, iclass 30, count 0 2006.189.08:03:20.66#ibcon#read 4, iclass 30, count 0 2006.189.08:03:20.66#ibcon#about to read 5, iclass 30, count 0 2006.189.08:03:20.66#ibcon#read 5, iclass 30, count 0 2006.189.08:03:20.66#ibcon#about to read 6, iclass 30, count 0 2006.189.08:03:20.66#ibcon#read 6, iclass 30, count 0 2006.189.08:03:20.66#ibcon#end of sib2, iclass 30, count 0 2006.189.08:03:20.66#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:03:20.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:03:20.66#ibcon#[25=USB\r\n] 2006.189.08:03:20.66#ibcon#*before write, iclass 30, count 0 2006.189.08:03:20.66#ibcon#enter sib2, iclass 30, count 0 2006.189.08:03:20.66#ibcon#flushed, iclass 30, count 0 2006.189.08:03:20.66#ibcon#about to write, iclass 30, count 0 2006.189.08:03:20.66#ibcon#wrote, iclass 30, count 0 2006.189.08:03:20.66#ibcon#about to read 3, iclass 30, count 0 2006.189.08:03:20.69#ibcon#read 3, iclass 30, count 0 2006.189.08:03:20.69#ibcon#about to read 4, iclass 30, count 0 2006.189.08:03:20.69#ibcon#read 4, iclass 30, count 0 2006.189.08:03:20.69#ibcon#about to read 5, iclass 30, count 0 2006.189.08:03:20.69#ibcon#read 5, iclass 30, count 0 2006.189.08:03:20.69#ibcon#about to read 6, iclass 30, count 0 2006.189.08:03:20.69#ibcon#read 6, iclass 30, count 0 2006.189.08:03:20.69#ibcon#end of sib2, iclass 30, count 0 2006.189.08:03:20.69#ibcon#*after write, iclass 30, count 0 2006.189.08:03:20.69#ibcon#*before return 0, iclass 30, count 0 2006.189.08:03:20.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:03:20.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:03:20.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:03:20.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:03:20.69$vc4f8/vblo=1,632.99 2006.189.08:03:20.69#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.08:03:20.69#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.08:03:20.69#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:20.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:03:20.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:03:20.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:03:20.69#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:03:20.69#ibcon#first serial, iclass 32, count 0 2006.189.08:03:20.69#ibcon#enter sib2, iclass 32, count 0 2006.189.08:03:20.69#ibcon#flushed, iclass 32, count 0 2006.189.08:03:20.69#ibcon#about to write, iclass 32, count 0 2006.189.08:03:20.69#ibcon#wrote, iclass 32, count 0 2006.189.08:03:20.69#ibcon#about to read 3, iclass 32, count 0 2006.189.08:03:20.71#ibcon#read 3, iclass 32, count 0 2006.189.08:03:20.71#ibcon#about to read 4, iclass 32, count 0 2006.189.08:03:20.71#ibcon#read 4, iclass 32, count 0 2006.189.08:03:20.71#ibcon#about to read 5, iclass 32, count 0 2006.189.08:03:20.71#ibcon#read 5, iclass 32, count 0 2006.189.08:03:20.71#ibcon#about to read 6, iclass 32, count 0 2006.189.08:03:20.71#ibcon#read 6, iclass 32, count 0 2006.189.08:03:20.71#ibcon#end of sib2, iclass 32, count 0 2006.189.08:03:20.71#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:03:20.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:03:20.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:03:20.71#ibcon#*before write, iclass 32, count 0 2006.189.08:03:20.71#ibcon#enter sib2, iclass 32, count 0 2006.189.08:03:20.71#ibcon#flushed, iclass 32, count 0 2006.189.08:03:20.71#ibcon#about to write, iclass 32, count 0 2006.189.08:03:20.71#ibcon#wrote, iclass 32, count 0 2006.189.08:03:20.71#ibcon#about to read 3, iclass 32, count 0 2006.189.08:03:20.75#ibcon#read 3, iclass 32, count 0 2006.189.08:03:20.75#ibcon#about to read 4, iclass 32, count 0 2006.189.08:03:20.75#ibcon#read 4, iclass 32, count 0 2006.189.08:03:20.75#ibcon#about to read 5, iclass 32, count 0 2006.189.08:03:20.75#ibcon#read 5, iclass 32, count 0 2006.189.08:03:20.75#ibcon#about to read 6, iclass 32, count 0 2006.189.08:03:20.75#ibcon#read 6, iclass 32, count 0 2006.189.08:03:20.75#ibcon#end of sib2, iclass 32, count 0 2006.189.08:03:20.75#ibcon#*after write, iclass 32, count 0 2006.189.08:03:20.75#ibcon#*before return 0, iclass 32, count 0 2006.189.08:03:20.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:03:20.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:03:20.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:03:20.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:03:20.75$vc4f8/vb=1,4 2006.189.08:03:20.75#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.08:03:20.75#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.08:03:20.75#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:20.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:03:20.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:03:20.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:03:20.75#ibcon#enter wrdev, iclass 34, count 2 2006.189.08:03:20.75#ibcon#first serial, iclass 34, count 2 2006.189.08:03:20.75#ibcon#enter sib2, iclass 34, count 2 2006.189.08:03:20.75#ibcon#flushed, iclass 34, count 2 2006.189.08:03:20.75#ibcon#about to write, iclass 34, count 2 2006.189.08:03:20.75#ibcon#wrote, iclass 34, count 2 2006.189.08:03:20.75#ibcon#about to read 3, iclass 34, count 2 2006.189.08:03:20.77#ibcon#read 3, iclass 34, count 2 2006.189.08:03:20.77#ibcon#about to read 4, iclass 34, count 2 2006.189.08:03:20.77#ibcon#read 4, iclass 34, count 2 2006.189.08:03:20.77#ibcon#about to read 5, iclass 34, count 2 2006.189.08:03:20.77#ibcon#read 5, iclass 34, count 2 2006.189.08:03:20.77#ibcon#about to read 6, iclass 34, count 2 2006.189.08:03:20.77#ibcon#read 6, iclass 34, count 2 2006.189.08:03:20.77#ibcon#end of sib2, iclass 34, count 2 2006.189.08:03:20.77#ibcon#*mode == 0, iclass 34, count 2 2006.189.08:03:20.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.08:03:20.77#ibcon#[27=AT01-04\r\n] 2006.189.08:03:20.77#ibcon#*before write, iclass 34, count 2 2006.189.08:03:20.77#ibcon#enter sib2, iclass 34, count 2 2006.189.08:03:20.77#ibcon#flushed, iclass 34, count 2 2006.189.08:03:20.77#ibcon#about to write, iclass 34, count 2 2006.189.08:03:20.77#ibcon#wrote, iclass 34, count 2 2006.189.08:03:20.77#ibcon#about to read 3, iclass 34, count 2 2006.189.08:03:20.80#ibcon#read 3, iclass 34, count 2 2006.189.08:03:20.80#ibcon#about to read 4, iclass 34, count 2 2006.189.08:03:20.80#ibcon#read 4, iclass 34, count 2 2006.189.08:03:20.80#ibcon#about to read 5, iclass 34, count 2 2006.189.08:03:20.80#ibcon#read 5, iclass 34, count 2 2006.189.08:03:20.80#ibcon#about to read 6, iclass 34, count 2 2006.189.08:03:20.80#ibcon#read 6, iclass 34, count 2 2006.189.08:03:20.80#ibcon#end of sib2, iclass 34, count 2 2006.189.08:03:20.80#ibcon#*after write, iclass 34, count 2 2006.189.08:03:20.80#ibcon#*before return 0, iclass 34, count 2 2006.189.08:03:20.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:03:20.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:03:20.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.08:03:20.80#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:20.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:03:20.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:03:20.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:03:20.92#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:03:20.92#ibcon#first serial, iclass 34, count 0 2006.189.08:03:20.92#ibcon#enter sib2, iclass 34, count 0 2006.189.08:03:20.92#ibcon#flushed, iclass 34, count 0 2006.189.08:03:20.92#ibcon#about to write, iclass 34, count 0 2006.189.08:03:20.92#ibcon#wrote, iclass 34, count 0 2006.189.08:03:20.92#ibcon#about to read 3, iclass 34, count 0 2006.189.08:03:20.94#ibcon#read 3, iclass 34, count 0 2006.189.08:03:20.94#ibcon#about to read 4, iclass 34, count 0 2006.189.08:03:20.94#ibcon#read 4, iclass 34, count 0 2006.189.08:03:20.94#ibcon#about to read 5, iclass 34, count 0 2006.189.08:03:20.94#ibcon#read 5, iclass 34, count 0 2006.189.08:03:20.94#ibcon#about to read 6, iclass 34, count 0 2006.189.08:03:20.94#ibcon#read 6, iclass 34, count 0 2006.189.08:03:20.94#ibcon#end of sib2, iclass 34, count 0 2006.189.08:03:20.94#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:03:20.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:03:20.94#ibcon#[27=USB\r\n] 2006.189.08:03:20.94#ibcon#*before write, iclass 34, count 0 2006.189.08:03:20.94#ibcon#enter sib2, iclass 34, count 0 2006.189.08:03:20.94#ibcon#flushed, iclass 34, count 0 2006.189.08:03:20.94#ibcon#about to write, iclass 34, count 0 2006.189.08:03:20.94#ibcon#wrote, iclass 34, count 0 2006.189.08:03:20.94#ibcon#about to read 3, iclass 34, count 0 2006.189.08:03:20.97#ibcon#read 3, iclass 34, count 0 2006.189.08:03:20.97#ibcon#about to read 4, iclass 34, count 0 2006.189.08:03:20.97#ibcon#read 4, iclass 34, count 0 2006.189.08:03:20.97#ibcon#about to read 5, iclass 34, count 0 2006.189.08:03:20.97#ibcon#read 5, iclass 34, count 0 2006.189.08:03:20.97#ibcon#about to read 6, iclass 34, count 0 2006.189.08:03:20.97#ibcon#read 6, iclass 34, count 0 2006.189.08:03:20.97#ibcon#end of sib2, iclass 34, count 0 2006.189.08:03:20.97#ibcon#*after write, iclass 34, count 0 2006.189.08:03:20.97#ibcon#*before return 0, iclass 34, count 0 2006.189.08:03:20.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:03:20.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:03:20.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:03:20.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:03:20.97$vc4f8/vblo=2,640.99 2006.189.08:03:20.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.08:03:20.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.08:03:20.97#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:20.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:20.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:20.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:20.97#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:03:20.97#ibcon#first serial, iclass 36, count 0 2006.189.08:03:20.97#ibcon#enter sib2, iclass 36, count 0 2006.189.08:03:20.97#ibcon#flushed, iclass 36, count 0 2006.189.08:03:20.97#ibcon#about to write, iclass 36, count 0 2006.189.08:03:20.97#ibcon#wrote, iclass 36, count 0 2006.189.08:03:20.97#ibcon#about to read 3, iclass 36, count 0 2006.189.08:03:20.99#ibcon#read 3, iclass 36, count 0 2006.189.08:03:20.99#ibcon#about to read 4, iclass 36, count 0 2006.189.08:03:20.99#ibcon#read 4, iclass 36, count 0 2006.189.08:03:20.99#ibcon#about to read 5, iclass 36, count 0 2006.189.08:03:20.99#ibcon#read 5, iclass 36, count 0 2006.189.08:03:20.99#ibcon#about to read 6, iclass 36, count 0 2006.189.08:03:20.99#ibcon#read 6, iclass 36, count 0 2006.189.08:03:20.99#ibcon#end of sib2, iclass 36, count 0 2006.189.08:03:20.99#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:03:20.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:03:20.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:03:20.99#ibcon#*before write, iclass 36, count 0 2006.189.08:03:20.99#ibcon#enter sib2, iclass 36, count 0 2006.189.08:03:20.99#ibcon#flushed, iclass 36, count 0 2006.189.08:03:20.99#ibcon#about to write, iclass 36, count 0 2006.189.08:03:20.99#ibcon#wrote, iclass 36, count 0 2006.189.08:03:20.99#ibcon#about to read 3, iclass 36, count 0 2006.189.08:03:21.03#ibcon#read 3, iclass 36, count 0 2006.189.08:03:21.03#ibcon#about to read 4, iclass 36, count 0 2006.189.08:03:21.03#ibcon#read 4, iclass 36, count 0 2006.189.08:03:21.03#ibcon#about to read 5, iclass 36, count 0 2006.189.08:03:21.03#ibcon#read 5, iclass 36, count 0 2006.189.08:03:21.03#ibcon#about to read 6, iclass 36, count 0 2006.189.08:03:21.03#ibcon#read 6, iclass 36, count 0 2006.189.08:03:21.03#ibcon#end of sib2, iclass 36, count 0 2006.189.08:03:21.03#ibcon#*after write, iclass 36, count 0 2006.189.08:03:21.03#ibcon#*before return 0, iclass 36, count 0 2006.189.08:03:21.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:21.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:03:21.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:03:21.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:03:21.03$vc4f8/vb=2,4 2006.189.08:03:21.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.08:03:21.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.08:03:21.03#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:21.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:21.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:21.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:21.09#ibcon#enter wrdev, iclass 38, count 2 2006.189.08:03:21.09#ibcon#first serial, iclass 38, count 2 2006.189.08:03:21.09#ibcon#enter sib2, iclass 38, count 2 2006.189.08:03:21.09#ibcon#flushed, iclass 38, count 2 2006.189.08:03:21.09#ibcon#about to write, iclass 38, count 2 2006.189.08:03:21.09#ibcon#wrote, iclass 38, count 2 2006.189.08:03:21.09#ibcon#about to read 3, iclass 38, count 2 2006.189.08:03:21.11#ibcon#read 3, iclass 38, count 2 2006.189.08:03:21.11#ibcon#about to read 4, iclass 38, count 2 2006.189.08:03:21.11#ibcon#read 4, iclass 38, count 2 2006.189.08:03:21.11#ibcon#about to read 5, iclass 38, count 2 2006.189.08:03:21.11#ibcon#read 5, iclass 38, count 2 2006.189.08:03:21.11#ibcon#about to read 6, iclass 38, count 2 2006.189.08:03:21.11#ibcon#read 6, iclass 38, count 2 2006.189.08:03:21.11#ibcon#end of sib2, iclass 38, count 2 2006.189.08:03:21.11#ibcon#*mode == 0, iclass 38, count 2 2006.189.08:03:21.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.08:03:21.11#ibcon#[27=AT02-04\r\n] 2006.189.08:03:21.11#ibcon#*before write, iclass 38, count 2 2006.189.08:03:21.11#ibcon#enter sib2, iclass 38, count 2 2006.189.08:03:21.11#ibcon#flushed, iclass 38, count 2 2006.189.08:03:21.11#ibcon#about to write, iclass 38, count 2 2006.189.08:03:21.11#ibcon#wrote, iclass 38, count 2 2006.189.08:03:21.11#ibcon#about to read 3, iclass 38, count 2 2006.189.08:03:21.14#ibcon#read 3, iclass 38, count 2 2006.189.08:03:21.14#ibcon#about to read 4, iclass 38, count 2 2006.189.08:03:21.14#ibcon#read 4, iclass 38, count 2 2006.189.08:03:21.14#ibcon#about to read 5, iclass 38, count 2 2006.189.08:03:21.14#ibcon#read 5, iclass 38, count 2 2006.189.08:03:21.14#ibcon#about to read 6, iclass 38, count 2 2006.189.08:03:21.14#ibcon#read 6, iclass 38, count 2 2006.189.08:03:21.14#ibcon#end of sib2, iclass 38, count 2 2006.189.08:03:21.14#ibcon#*after write, iclass 38, count 2 2006.189.08:03:21.14#ibcon#*before return 0, iclass 38, count 2 2006.189.08:03:21.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:21.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:03:21.14#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.08:03:21.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:21.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:21.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:21.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:21.26#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:03:21.26#ibcon#first serial, iclass 38, count 0 2006.189.08:03:21.26#ibcon#enter sib2, iclass 38, count 0 2006.189.08:03:21.26#ibcon#flushed, iclass 38, count 0 2006.189.08:03:21.26#ibcon#about to write, iclass 38, count 0 2006.189.08:03:21.26#ibcon#wrote, iclass 38, count 0 2006.189.08:03:21.26#ibcon#about to read 3, iclass 38, count 0 2006.189.08:03:21.28#ibcon#read 3, iclass 38, count 0 2006.189.08:03:21.28#ibcon#about to read 4, iclass 38, count 0 2006.189.08:03:21.28#ibcon#read 4, iclass 38, count 0 2006.189.08:03:21.28#ibcon#about to read 5, iclass 38, count 0 2006.189.08:03:21.28#ibcon#read 5, iclass 38, count 0 2006.189.08:03:21.28#ibcon#about to read 6, iclass 38, count 0 2006.189.08:03:21.28#ibcon#read 6, iclass 38, count 0 2006.189.08:03:21.28#ibcon#end of sib2, iclass 38, count 0 2006.189.08:03:21.28#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:03:21.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:03:21.28#ibcon#[27=USB\r\n] 2006.189.08:03:21.28#ibcon#*before write, iclass 38, count 0 2006.189.08:03:21.28#ibcon#enter sib2, iclass 38, count 0 2006.189.08:03:21.28#ibcon#flushed, iclass 38, count 0 2006.189.08:03:21.28#ibcon#about to write, iclass 38, count 0 2006.189.08:03:21.28#ibcon#wrote, iclass 38, count 0 2006.189.08:03:21.28#ibcon#about to read 3, iclass 38, count 0 2006.189.08:03:21.31#ibcon#read 3, iclass 38, count 0 2006.189.08:03:21.31#ibcon#about to read 4, iclass 38, count 0 2006.189.08:03:21.31#ibcon#read 4, iclass 38, count 0 2006.189.08:03:21.31#ibcon#about to read 5, iclass 38, count 0 2006.189.08:03:21.31#ibcon#read 5, iclass 38, count 0 2006.189.08:03:21.31#ibcon#about to read 6, iclass 38, count 0 2006.189.08:03:21.31#ibcon#read 6, iclass 38, count 0 2006.189.08:03:21.31#ibcon#end of sib2, iclass 38, count 0 2006.189.08:03:21.31#ibcon#*after write, iclass 38, count 0 2006.189.08:03:21.31#ibcon#*before return 0, iclass 38, count 0 2006.189.08:03:21.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:21.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:03:21.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:03:21.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:03:21.31$vc4f8/vblo=3,656.99 2006.189.08:03:21.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.08:03:21.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.08:03:21.31#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:21.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:21.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:21.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:21.31#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:03:21.31#ibcon#first serial, iclass 40, count 0 2006.189.08:03:21.31#ibcon#enter sib2, iclass 40, count 0 2006.189.08:03:21.31#ibcon#flushed, iclass 40, count 0 2006.189.08:03:21.31#ibcon#about to write, iclass 40, count 0 2006.189.08:03:21.31#ibcon#wrote, iclass 40, count 0 2006.189.08:03:21.31#ibcon#about to read 3, iclass 40, count 0 2006.189.08:03:21.33#ibcon#read 3, iclass 40, count 0 2006.189.08:03:21.33#ibcon#about to read 4, iclass 40, count 0 2006.189.08:03:21.33#ibcon#read 4, iclass 40, count 0 2006.189.08:03:21.33#ibcon#about to read 5, iclass 40, count 0 2006.189.08:03:21.33#ibcon#read 5, iclass 40, count 0 2006.189.08:03:21.33#ibcon#about to read 6, iclass 40, count 0 2006.189.08:03:21.33#ibcon#read 6, iclass 40, count 0 2006.189.08:03:21.33#ibcon#end of sib2, iclass 40, count 0 2006.189.08:03:21.33#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:03:21.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:03:21.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:03:21.33#ibcon#*before write, iclass 40, count 0 2006.189.08:03:21.33#ibcon#enter sib2, iclass 40, count 0 2006.189.08:03:21.33#ibcon#flushed, iclass 40, count 0 2006.189.08:03:21.33#ibcon#about to write, iclass 40, count 0 2006.189.08:03:21.33#ibcon#wrote, iclass 40, count 0 2006.189.08:03:21.33#ibcon#about to read 3, iclass 40, count 0 2006.189.08:03:21.37#ibcon#read 3, iclass 40, count 0 2006.189.08:03:21.37#ibcon#about to read 4, iclass 40, count 0 2006.189.08:03:21.37#ibcon#read 4, iclass 40, count 0 2006.189.08:03:21.37#ibcon#about to read 5, iclass 40, count 0 2006.189.08:03:21.37#ibcon#read 5, iclass 40, count 0 2006.189.08:03:21.37#ibcon#about to read 6, iclass 40, count 0 2006.189.08:03:21.37#ibcon#read 6, iclass 40, count 0 2006.189.08:03:21.37#ibcon#end of sib2, iclass 40, count 0 2006.189.08:03:21.37#ibcon#*after write, iclass 40, count 0 2006.189.08:03:21.37#ibcon#*before return 0, iclass 40, count 0 2006.189.08:03:21.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:21.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:03:21.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:03:21.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:03:21.37$vc4f8/vb=3,4 2006.189.08:03:21.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.08:03:21.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.08:03:21.37#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:21.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:21.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:21.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:21.43#ibcon#enter wrdev, iclass 4, count 2 2006.189.08:03:21.43#ibcon#first serial, iclass 4, count 2 2006.189.08:03:21.43#ibcon#enter sib2, iclass 4, count 2 2006.189.08:03:21.43#ibcon#flushed, iclass 4, count 2 2006.189.08:03:21.43#ibcon#about to write, iclass 4, count 2 2006.189.08:03:21.43#ibcon#wrote, iclass 4, count 2 2006.189.08:03:21.43#ibcon#about to read 3, iclass 4, count 2 2006.189.08:03:21.45#ibcon#read 3, iclass 4, count 2 2006.189.08:03:21.45#ibcon#about to read 4, iclass 4, count 2 2006.189.08:03:21.45#ibcon#read 4, iclass 4, count 2 2006.189.08:03:21.45#ibcon#about to read 5, iclass 4, count 2 2006.189.08:03:21.45#ibcon#read 5, iclass 4, count 2 2006.189.08:03:21.45#ibcon#about to read 6, iclass 4, count 2 2006.189.08:03:21.45#ibcon#read 6, iclass 4, count 2 2006.189.08:03:21.45#ibcon#end of sib2, iclass 4, count 2 2006.189.08:03:21.45#ibcon#*mode == 0, iclass 4, count 2 2006.189.08:03:21.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.08:03:21.45#ibcon#[27=AT03-04\r\n] 2006.189.08:03:21.45#ibcon#*before write, iclass 4, count 2 2006.189.08:03:21.45#ibcon#enter sib2, iclass 4, count 2 2006.189.08:03:21.45#ibcon#flushed, iclass 4, count 2 2006.189.08:03:21.45#ibcon#about to write, iclass 4, count 2 2006.189.08:03:21.45#ibcon#wrote, iclass 4, count 2 2006.189.08:03:21.45#ibcon#about to read 3, iclass 4, count 2 2006.189.08:03:21.48#ibcon#read 3, iclass 4, count 2 2006.189.08:03:21.48#ibcon#about to read 4, iclass 4, count 2 2006.189.08:03:21.48#ibcon#read 4, iclass 4, count 2 2006.189.08:03:21.48#ibcon#about to read 5, iclass 4, count 2 2006.189.08:03:21.48#ibcon#read 5, iclass 4, count 2 2006.189.08:03:21.48#ibcon#about to read 6, iclass 4, count 2 2006.189.08:03:21.48#ibcon#read 6, iclass 4, count 2 2006.189.08:03:21.48#ibcon#end of sib2, iclass 4, count 2 2006.189.08:03:21.48#ibcon#*after write, iclass 4, count 2 2006.189.08:03:21.48#ibcon#*before return 0, iclass 4, count 2 2006.189.08:03:21.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:21.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:03:21.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.08:03:21.48#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:21.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:21.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:21.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:21.60#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:03:21.60#ibcon#first serial, iclass 4, count 0 2006.189.08:03:21.60#ibcon#enter sib2, iclass 4, count 0 2006.189.08:03:21.60#ibcon#flushed, iclass 4, count 0 2006.189.08:03:21.60#ibcon#about to write, iclass 4, count 0 2006.189.08:03:21.60#ibcon#wrote, iclass 4, count 0 2006.189.08:03:21.60#ibcon#about to read 3, iclass 4, count 0 2006.189.08:03:21.62#ibcon#read 3, iclass 4, count 0 2006.189.08:03:21.62#ibcon#about to read 4, iclass 4, count 0 2006.189.08:03:21.62#ibcon#read 4, iclass 4, count 0 2006.189.08:03:21.62#ibcon#about to read 5, iclass 4, count 0 2006.189.08:03:21.62#ibcon#read 5, iclass 4, count 0 2006.189.08:03:21.62#ibcon#about to read 6, iclass 4, count 0 2006.189.08:03:21.62#ibcon#read 6, iclass 4, count 0 2006.189.08:03:21.62#ibcon#end of sib2, iclass 4, count 0 2006.189.08:03:21.62#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:03:21.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:03:21.62#ibcon#[27=USB\r\n] 2006.189.08:03:21.62#ibcon#*before write, iclass 4, count 0 2006.189.08:03:21.62#ibcon#enter sib2, iclass 4, count 0 2006.189.08:03:21.62#ibcon#flushed, iclass 4, count 0 2006.189.08:03:21.62#ibcon#about to write, iclass 4, count 0 2006.189.08:03:21.62#ibcon#wrote, iclass 4, count 0 2006.189.08:03:21.62#ibcon#about to read 3, iclass 4, count 0 2006.189.08:03:21.65#ibcon#read 3, iclass 4, count 0 2006.189.08:03:21.65#ibcon#about to read 4, iclass 4, count 0 2006.189.08:03:21.65#ibcon#read 4, iclass 4, count 0 2006.189.08:03:21.65#ibcon#about to read 5, iclass 4, count 0 2006.189.08:03:21.65#ibcon#read 5, iclass 4, count 0 2006.189.08:03:21.65#ibcon#about to read 6, iclass 4, count 0 2006.189.08:03:21.65#ibcon#read 6, iclass 4, count 0 2006.189.08:03:21.65#ibcon#end of sib2, iclass 4, count 0 2006.189.08:03:21.65#ibcon#*after write, iclass 4, count 0 2006.189.08:03:21.65#ibcon#*before return 0, iclass 4, count 0 2006.189.08:03:21.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:21.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:03:21.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:03:21.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:03:21.65$vc4f8/vblo=4,712.99 2006.189.08:03:21.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.08:03:21.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.08:03:21.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:21.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:21.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:21.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:21.65#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:03:21.65#ibcon#first serial, iclass 6, count 0 2006.189.08:03:21.65#ibcon#enter sib2, iclass 6, count 0 2006.189.08:03:21.65#ibcon#flushed, iclass 6, count 0 2006.189.08:03:21.65#ibcon#about to write, iclass 6, count 0 2006.189.08:03:21.65#ibcon#wrote, iclass 6, count 0 2006.189.08:03:21.65#ibcon#about to read 3, iclass 6, count 0 2006.189.08:03:21.67#ibcon#read 3, iclass 6, count 0 2006.189.08:03:21.67#ibcon#about to read 4, iclass 6, count 0 2006.189.08:03:21.67#ibcon#read 4, iclass 6, count 0 2006.189.08:03:21.67#ibcon#about to read 5, iclass 6, count 0 2006.189.08:03:21.67#ibcon#read 5, iclass 6, count 0 2006.189.08:03:21.67#ibcon#about to read 6, iclass 6, count 0 2006.189.08:03:21.67#ibcon#read 6, iclass 6, count 0 2006.189.08:03:21.67#ibcon#end of sib2, iclass 6, count 0 2006.189.08:03:21.67#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:03:21.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:03:21.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:03:21.67#ibcon#*before write, iclass 6, count 0 2006.189.08:03:21.67#ibcon#enter sib2, iclass 6, count 0 2006.189.08:03:21.67#ibcon#flushed, iclass 6, count 0 2006.189.08:03:21.67#ibcon#about to write, iclass 6, count 0 2006.189.08:03:21.67#ibcon#wrote, iclass 6, count 0 2006.189.08:03:21.67#ibcon#about to read 3, iclass 6, count 0 2006.189.08:03:21.71#ibcon#read 3, iclass 6, count 0 2006.189.08:03:21.71#ibcon#about to read 4, iclass 6, count 0 2006.189.08:03:21.71#ibcon#read 4, iclass 6, count 0 2006.189.08:03:21.71#ibcon#about to read 5, iclass 6, count 0 2006.189.08:03:21.71#ibcon#read 5, iclass 6, count 0 2006.189.08:03:21.71#ibcon#about to read 6, iclass 6, count 0 2006.189.08:03:21.71#ibcon#read 6, iclass 6, count 0 2006.189.08:03:21.71#ibcon#end of sib2, iclass 6, count 0 2006.189.08:03:21.71#ibcon#*after write, iclass 6, count 0 2006.189.08:03:21.71#ibcon#*before return 0, iclass 6, count 0 2006.189.08:03:21.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:21.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:03:21.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:03:21.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:03:21.71$vc4f8/vb=4,4 2006.189.08:03:21.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.08:03:21.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.08:03:21.71#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:21.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:21.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:21.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:21.77#ibcon#enter wrdev, iclass 10, count 2 2006.189.08:03:21.77#ibcon#first serial, iclass 10, count 2 2006.189.08:03:21.77#ibcon#enter sib2, iclass 10, count 2 2006.189.08:03:21.77#ibcon#flushed, iclass 10, count 2 2006.189.08:03:21.77#ibcon#about to write, iclass 10, count 2 2006.189.08:03:21.77#ibcon#wrote, iclass 10, count 2 2006.189.08:03:21.77#ibcon#about to read 3, iclass 10, count 2 2006.189.08:03:21.79#ibcon#read 3, iclass 10, count 2 2006.189.08:03:21.79#ibcon#about to read 4, iclass 10, count 2 2006.189.08:03:21.79#ibcon#read 4, iclass 10, count 2 2006.189.08:03:21.79#ibcon#about to read 5, iclass 10, count 2 2006.189.08:03:21.79#ibcon#read 5, iclass 10, count 2 2006.189.08:03:21.79#ibcon#about to read 6, iclass 10, count 2 2006.189.08:03:21.79#ibcon#read 6, iclass 10, count 2 2006.189.08:03:21.79#ibcon#end of sib2, iclass 10, count 2 2006.189.08:03:21.79#ibcon#*mode == 0, iclass 10, count 2 2006.189.08:03:21.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.08:03:21.79#ibcon#[27=AT04-04\r\n] 2006.189.08:03:21.79#ibcon#*before write, iclass 10, count 2 2006.189.08:03:21.79#ibcon#enter sib2, iclass 10, count 2 2006.189.08:03:21.79#ibcon#flushed, iclass 10, count 2 2006.189.08:03:21.79#ibcon#about to write, iclass 10, count 2 2006.189.08:03:21.79#ibcon#wrote, iclass 10, count 2 2006.189.08:03:21.79#ibcon#about to read 3, iclass 10, count 2 2006.189.08:03:21.82#ibcon#read 3, iclass 10, count 2 2006.189.08:03:21.82#ibcon#about to read 4, iclass 10, count 2 2006.189.08:03:21.82#ibcon#read 4, iclass 10, count 2 2006.189.08:03:21.82#ibcon#about to read 5, iclass 10, count 2 2006.189.08:03:21.82#ibcon#read 5, iclass 10, count 2 2006.189.08:03:21.82#ibcon#about to read 6, iclass 10, count 2 2006.189.08:03:21.82#ibcon#read 6, iclass 10, count 2 2006.189.08:03:21.82#ibcon#end of sib2, iclass 10, count 2 2006.189.08:03:21.82#ibcon#*after write, iclass 10, count 2 2006.189.08:03:21.82#ibcon#*before return 0, iclass 10, count 2 2006.189.08:03:21.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:21.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:03:21.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.08:03:21.82#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:21.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:21.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:21.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:21.94#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:03:21.94#ibcon#first serial, iclass 10, count 0 2006.189.08:03:21.94#ibcon#enter sib2, iclass 10, count 0 2006.189.08:03:21.94#ibcon#flushed, iclass 10, count 0 2006.189.08:03:21.94#ibcon#about to write, iclass 10, count 0 2006.189.08:03:21.94#ibcon#wrote, iclass 10, count 0 2006.189.08:03:21.94#ibcon#about to read 3, iclass 10, count 0 2006.189.08:03:21.96#ibcon#read 3, iclass 10, count 0 2006.189.08:03:21.96#ibcon#about to read 4, iclass 10, count 0 2006.189.08:03:21.96#ibcon#read 4, iclass 10, count 0 2006.189.08:03:21.96#ibcon#about to read 5, iclass 10, count 0 2006.189.08:03:21.96#ibcon#read 5, iclass 10, count 0 2006.189.08:03:21.96#ibcon#about to read 6, iclass 10, count 0 2006.189.08:03:21.96#ibcon#read 6, iclass 10, count 0 2006.189.08:03:21.96#ibcon#end of sib2, iclass 10, count 0 2006.189.08:03:21.96#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:03:21.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:03:21.96#ibcon#[27=USB\r\n] 2006.189.08:03:21.96#ibcon#*before write, iclass 10, count 0 2006.189.08:03:21.96#ibcon#enter sib2, iclass 10, count 0 2006.189.08:03:21.96#ibcon#flushed, iclass 10, count 0 2006.189.08:03:21.96#ibcon#about to write, iclass 10, count 0 2006.189.08:03:21.96#ibcon#wrote, iclass 10, count 0 2006.189.08:03:21.96#ibcon#about to read 3, iclass 10, count 0 2006.189.08:03:21.99#ibcon#read 3, iclass 10, count 0 2006.189.08:03:21.99#ibcon#about to read 4, iclass 10, count 0 2006.189.08:03:21.99#ibcon#read 4, iclass 10, count 0 2006.189.08:03:21.99#ibcon#about to read 5, iclass 10, count 0 2006.189.08:03:21.99#ibcon#read 5, iclass 10, count 0 2006.189.08:03:21.99#ibcon#about to read 6, iclass 10, count 0 2006.189.08:03:21.99#ibcon#read 6, iclass 10, count 0 2006.189.08:03:21.99#ibcon#end of sib2, iclass 10, count 0 2006.189.08:03:21.99#ibcon#*after write, iclass 10, count 0 2006.189.08:03:21.99#ibcon#*before return 0, iclass 10, count 0 2006.189.08:03:21.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:21.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:03:21.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:03:21.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:03:21.99$vc4f8/vblo=5,744.99 2006.189.08:03:21.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.08:03:21.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.08:03:21.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:21.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:21.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:21.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:21.99#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:03:21.99#ibcon#first serial, iclass 12, count 0 2006.189.08:03:21.99#ibcon#enter sib2, iclass 12, count 0 2006.189.08:03:21.99#ibcon#flushed, iclass 12, count 0 2006.189.08:03:21.99#ibcon#about to write, iclass 12, count 0 2006.189.08:03:21.99#ibcon#wrote, iclass 12, count 0 2006.189.08:03:21.99#ibcon#about to read 3, iclass 12, count 0 2006.189.08:03:22.01#ibcon#read 3, iclass 12, count 0 2006.189.08:03:22.01#ibcon#about to read 4, iclass 12, count 0 2006.189.08:03:22.01#ibcon#read 4, iclass 12, count 0 2006.189.08:03:22.01#ibcon#about to read 5, iclass 12, count 0 2006.189.08:03:22.01#ibcon#read 5, iclass 12, count 0 2006.189.08:03:22.01#ibcon#about to read 6, iclass 12, count 0 2006.189.08:03:22.01#ibcon#read 6, iclass 12, count 0 2006.189.08:03:22.01#ibcon#end of sib2, iclass 12, count 0 2006.189.08:03:22.01#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:03:22.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:03:22.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:03:22.01#ibcon#*before write, iclass 12, count 0 2006.189.08:03:22.01#ibcon#enter sib2, iclass 12, count 0 2006.189.08:03:22.01#ibcon#flushed, iclass 12, count 0 2006.189.08:03:22.01#ibcon#about to write, iclass 12, count 0 2006.189.08:03:22.01#ibcon#wrote, iclass 12, count 0 2006.189.08:03:22.01#ibcon#about to read 3, iclass 12, count 0 2006.189.08:03:22.05#ibcon#read 3, iclass 12, count 0 2006.189.08:03:22.05#ibcon#about to read 4, iclass 12, count 0 2006.189.08:03:22.05#ibcon#read 4, iclass 12, count 0 2006.189.08:03:22.05#ibcon#about to read 5, iclass 12, count 0 2006.189.08:03:22.05#ibcon#read 5, iclass 12, count 0 2006.189.08:03:22.05#ibcon#about to read 6, iclass 12, count 0 2006.189.08:03:22.05#ibcon#read 6, iclass 12, count 0 2006.189.08:03:22.05#ibcon#end of sib2, iclass 12, count 0 2006.189.08:03:22.05#ibcon#*after write, iclass 12, count 0 2006.189.08:03:22.05#ibcon#*before return 0, iclass 12, count 0 2006.189.08:03:22.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:22.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:03:22.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:03:22.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:03:22.05$vc4f8/vb=5,4 2006.189.08:03:22.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.08:03:22.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.08:03:22.05#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:22.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:22.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:22.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:22.11#ibcon#enter wrdev, iclass 14, count 2 2006.189.08:03:22.11#ibcon#first serial, iclass 14, count 2 2006.189.08:03:22.11#ibcon#enter sib2, iclass 14, count 2 2006.189.08:03:22.11#ibcon#flushed, iclass 14, count 2 2006.189.08:03:22.11#ibcon#about to write, iclass 14, count 2 2006.189.08:03:22.11#ibcon#wrote, iclass 14, count 2 2006.189.08:03:22.11#ibcon#about to read 3, iclass 14, count 2 2006.189.08:03:22.13#ibcon#read 3, iclass 14, count 2 2006.189.08:03:22.13#ibcon#about to read 4, iclass 14, count 2 2006.189.08:03:22.13#ibcon#read 4, iclass 14, count 2 2006.189.08:03:22.13#ibcon#about to read 5, iclass 14, count 2 2006.189.08:03:22.13#ibcon#read 5, iclass 14, count 2 2006.189.08:03:22.13#ibcon#about to read 6, iclass 14, count 2 2006.189.08:03:22.13#ibcon#read 6, iclass 14, count 2 2006.189.08:03:22.13#ibcon#end of sib2, iclass 14, count 2 2006.189.08:03:22.13#ibcon#*mode == 0, iclass 14, count 2 2006.189.08:03:22.13#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.08:03:22.13#ibcon#[27=AT05-04\r\n] 2006.189.08:03:22.13#ibcon#*before write, iclass 14, count 2 2006.189.08:03:22.13#ibcon#enter sib2, iclass 14, count 2 2006.189.08:03:22.13#ibcon#flushed, iclass 14, count 2 2006.189.08:03:22.13#ibcon#about to write, iclass 14, count 2 2006.189.08:03:22.13#ibcon#wrote, iclass 14, count 2 2006.189.08:03:22.13#ibcon#about to read 3, iclass 14, count 2 2006.189.08:03:22.16#ibcon#read 3, iclass 14, count 2 2006.189.08:03:22.16#ibcon#about to read 4, iclass 14, count 2 2006.189.08:03:22.16#ibcon#read 4, iclass 14, count 2 2006.189.08:03:22.16#ibcon#about to read 5, iclass 14, count 2 2006.189.08:03:22.16#ibcon#read 5, iclass 14, count 2 2006.189.08:03:22.16#ibcon#about to read 6, iclass 14, count 2 2006.189.08:03:22.16#ibcon#read 6, iclass 14, count 2 2006.189.08:03:22.16#ibcon#end of sib2, iclass 14, count 2 2006.189.08:03:22.16#ibcon#*after write, iclass 14, count 2 2006.189.08:03:22.16#ibcon#*before return 0, iclass 14, count 2 2006.189.08:03:22.16#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:22.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:03:22.16#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.08:03:22.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:22.16#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:22.28#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:22.28#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:22.28#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:03:22.28#ibcon#first serial, iclass 14, count 0 2006.189.08:03:22.28#ibcon#enter sib2, iclass 14, count 0 2006.189.08:03:22.28#ibcon#flushed, iclass 14, count 0 2006.189.08:03:22.28#ibcon#about to write, iclass 14, count 0 2006.189.08:03:22.28#ibcon#wrote, iclass 14, count 0 2006.189.08:03:22.28#ibcon#about to read 3, iclass 14, count 0 2006.189.08:03:22.30#ibcon#read 3, iclass 14, count 0 2006.189.08:03:22.30#ibcon#about to read 4, iclass 14, count 0 2006.189.08:03:22.30#ibcon#read 4, iclass 14, count 0 2006.189.08:03:22.30#ibcon#about to read 5, iclass 14, count 0 2006.189.08:03:22.30#ibcon#read 5, iclass 14, count 0 2006.189.08:03:22.30#ibcon#about to read 6, iclass 14, count 0 2006.189.08:03:22.30#ibcon#read 6, iclass 14, count 0 2006.189.08:03:22.30#ibcon#end of sib2, iclass 14, count 0 2006.189.08:03:22.30#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:03:22.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:03:22.30#ibcon#[27=USB\r\n] 2006.189.08:03:22.30#ibcon#*before write, iclass 14, count 0 2006.189.08:03:22.30#ibcon#enter sib2, iclass 14, count 0 2006.189.08:03:22.30#ibcon#flushed, iclass 14, count 0 2006.189.08:03:22.30#ibcon#about to write, iclass 14, count 0 2006.189.08:03:22.30#ibcon#wrote, iclass 14, count 0 2006.189.08:03:22.30#ibcon#about to read 3, iclass 14, count 0 2006.189.08:03:22.33#ibcon#read 3, iclass 14, count 0 2006.189.08:03:22.33#ibcon#about to read 4, iclass 14, count 0 2006.189.08:03:22.33#ibcon#read 4, iclass 14, count 0 2006.189.08:03:22.33#ibcon#about to read 5, iclass 14, count 0 2006.189.08:03:22.33#ibcon#read 5, iclass 14, count 0 2006.189.08:03:22.33#ibcon#about to read 6, iclass 14, count 0 2006.189.08:03:22.33#ibcon#read 6, iclass 14, count 0 2006.189.08:03:22.33#ibcon#end of sib2, iclass 14, count 0 2006.189.08:03:22.33#ibcon#*after write, iclass 14, count 0 2006.189.08:03:22.33#ibcon#*before return 0, iclass 14, count 0 2006.189.08:03:22.33#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:22.33#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:03:22.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:03:22.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:03:22.33$vc4f8/vblo=6,752.99 2006.189.08:03:22.33#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.08:03:22.33#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.08:03:22.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:03:22.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:22.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:22.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:22.33#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:03:22.33#ibcon#first serial, iclass 16, count 0 2006.189.08:03:22.33#ibcon#enter sib2, iclass 16, count 0 2006.189.08:03:22.33#ibcon#flushed, iclass 16, count 0 2006.189.08:03:22.33#ibcon#about to write, iclass 16, count 0 2006.189.08:03:22.33#ibcon#wrote, iclass 16, count 0 2006.189.08:03:22.33#ibcon#about to read 3, iclass 16, count 0 2006.189.08:03:22.35#ibcon#read 3, iclass 16, count 0 2006.189.08:03:22.35#ibcon#about to read 4, iclass 16, count 0 2006.189.08:03:22.35#ibcon#read 4, iclass 16, count 0 2006.189.08:03:22.35#ibcon#about to read 5, iclass 16, count 0 2006.189.08:03:22.35#ibcon#read 5, iclass 16, count 0 2006.189.08:03:22.35#ibcon#about to read 6, iclass 16, count 0 2006.189.08:03:22.35#ibcon#read 6, iclass 16, count 0 2006.189.08:03:22.35#ibcon#end of sib2, iclass 16, count 0 2006.189.08:03:22.35#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:03:22.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:03:22.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:03:22.35#ibcon#*before write, iclass 16, count 0 2006.189.08:03:22.35#ibcon#enter sib2, iclass 16, count 0 2006.189.08:03:22.35#ibcon#flushed, iclass 16, count 0 2006.189.08:03:22.35#ibcon#about to write, iclass 16, count 0 2006.189.08:03:22.35#ibcon#wrote, iclass 16, count 0 2006.189.08:03:22.35#ibcon#about to read 3, iclass 16, count 0 2006.189.08:03:22.39#ibcon#read 3, iclass 16, count 0 2006.189.08:03:22.39#ibcon#about to read 4, iclass 16, count 0 2006.189.08:03:22.39#ibcon#read 4, iclass 16, count 0 2006.189.08:03:22.39#ibcon#about to read 5, iclass 16, count 0 2006.189.08:03:22.39#ibcon#read 5, iclass 16, count 0 2006.189.08:03:22.39#ibcon#about to read 6, iclass 16, count 0 2006.189.08:03:22.39#ibcon#read 6, iclass 16, count 0 2006.189.08:03:22.39#ibcon#end of sib2, iclass 16, count 0 2006.189.08:03:22.39#ibcon#*after write, iclass 16, count 0 2006.189.08:03:22.39#ibcon#*before return 0, iclass 16, count 0 2006.189.08:03:22.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:22.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:03:22.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:03:22.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:03:22.39$vc4f8/vb=6,4 2006.189.08:03:22.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.08:03:22.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.08:03:22.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:03:22.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:03:22.40#abcon#<5=/04 3.8 7.3 25.67 911009.2\r\n> 2006.189.08:03:22.42#abcon#{5=INTERFACE CLEAR} 2006.189.08:03:22.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:03:22.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:03:22.45#ibcon#enter wrdev, iclass 19, count 2 2006.189.08:03:22.45#ibcon#first serial, iclass 19, count 2 2006.189.08:03:22.45#ibcon#enter sib2, iclass 19, count 2 2006.189.08:03:22.45#ibcon#flushed, iclass 19, count 2 2006.189.08:03:22.45#ibcon#about to write, iclass 19, count 2 2006.189.08:03:22.45#ibcon#wrote, iclass 19, count 2 2006.189.08:03:22.45#ibcon#about to read 3, iclass 19, count 2 2006.189.08:03:22.47#ibcon#read 3, iclass 19, count 2 2006.189.08:03:22.47#ibcon#about to read 4, iclass 19, count 2 2006.189.08:03:22.47#ibcon#read 4, iclass 19, count 2 2006.189.08:03:22.47#ibcon#about to read 5, iclass 19, count 2 2006.189.08:03:22.47#ibcon#read 5, iclass 19, count 2 2006.189.08:03:22.47#ibcon#about to read 6, iclass 19, count 2 2006.189.08:03:22.47#ibcon#read 6, iclass 19, count 2 2006.189.08:03:22.47#ibcon#end of sib2, iclass 19, count 2 2006.189.08:03:22.47#ibcon#*mode == 0, iclass 19, count 2 2006.189.08:03:22.47#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.08:03:22.47#ibcon#[27=AT06-04\r\n] 2006.189.08:03:22.47#ibcon#*before write, iclass 19, count 2 2006.189.08:03:22.47#ibcon#enter sib2, iclass 19, count 2 2006.189.08:03:22.47#ibcon#flushed, iclass 19, count 2 2006.189.08:03:22.47#ibcon#about to write, iclass 19, count 2 2006.189.08:03:22.47#ibcon#wrote, iclass 19, count 2 2006.189.08:03:22.47#ibcon#about to read 3, iclass 19, count 2 2006.189.08:03:22.48#abcon#[5=S1D000X0/0*\r\n] 2006.189.08:03:22.50#ibcon#read 3, iclass 19, count 2 2006.189.08:03:22.50#ibcon#about to read 4, iclass 19, count 2 2006.189.08:03:22.50#ibcon#read 4, iclass 19, count 2 2006.189.08:03:22.50#ibcon#about to read 5, iclass 19, count 2 2006.189.08:03:22.50#ibcon#read 5, iclass 19, count 2 2006.189.08:03:22.50#ibcon#about to read 6, iclass 19, count 2 2006.189.08:03:22.50#ibcon#read 6, iclass 19, count 2 2006.189.08:03:22.50#ibcon#end of sib2, iclass 19, count 2 2006.189.08:03:22.50#ibcon#*after write, iclass 19, count 2 2006.189.08:03:22.50#ibcon#*before return 0, iclass 19, count 2 2006.189.08:03:22.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:03:22.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:03:22.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.08:03:22.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:03:22.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:03:22.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:03:22.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:03:22.62#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:03:22.62#ibcon#first serial, iclass 19, count 0 2006.189.08:03:22.62#ibcon#enter sib2, iclass 19, count 0 2006.189.08:03:22.62#ibcon#flushed, iclass 19, count 0 2006.189.08:03:22.62#ibcon#about to write, iclass 19, count 0 2006.189.08:03:22.62#ibcon#wrote, iclass 19, count 0 2006.189.08:03:22.62#ibcon#about to read 3, iclass 19, count 0 2006.189.08:03:22.64#ibcon#read 3, iclass 19, count 0 2006.189.08:03:22.64#ibcon#about to read 4, iclass 19, count 0 2006.189.08:03:22.64#ibcon#read 4, iclass 19, count 0 2006.189.08:03:22.64#ibcon#about to read 5, iclass 19, count 0 2006.189.08:03:22.64#ibcon#read 5, iclass 19, count 0 2006.189.08:03:22.64#ibcon#about to read 6, iclass 19, count 0 2006.189.08:03:22.64#ibcon#read 6, iclass 19, count 0 2006.189.08:03:22.64#ibcon#end of sib2, iclass 19, count 0 2006.189.08:03:22.64#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:03:22.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:03:22.64#ibcon#[27=USB\r\n] 2006.189.08:03:22.64#ibcon#*before write, iclass 19, count 0 2006.189.08:03:22.64#ibcon#enter sib2, iclass 19, count 0 2006.189.08:03:22.64#ibcon#flushed, iclass 19, count 0 2006.189.08:03:22.64#ibcon#about to write, iclass 19, count 0 2006.189.08:03:22.64#ibcon#wrote, iclass 19, count 0 2006.189.08:03:22.64#ibcon#about to read 3, iclass 19, count 0 2006.189.08:03:22.67#ibcon#read 3, iclass 19, count 0 2006.189.08:03:22.67#ibcon#about to read 4, iclass 19, count 0 2006.189.08:03:22.67#ibcon#read 4, iclass 19, count 0 2006.189.08:03:22.67#ibcon#about to read 5, iclass 19, count 0 2006.189.08:03:22.67#ibcon#read 5, iclass 19, count 0 2006.189.08:03:22.67#ibcon#about to read 6, iclass 19, count 0 2006.189.08:03:22.67#ibcon#read 6, iclass 19, count 0 2006.189.08:03:22.67#ibcon#end of sib2, iclass 19, count 0 2006.189.08:03:22.67#ibcon#*after write, iclass 19, count 0 2006.189.08:03:22.67#ibcon#*before return 0, iclass 19, count 0 2006.189.08:03:22.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:03:22.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:03:22.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:03:22.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:03:22.67$vc4f8/vabw=wide 2006.189.08:03:22.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.08:03:22.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.08:03:22.67#ibcon#ireg 8 cls_cnt 0 2006.189.08:03:22.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:22.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:22.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:22.67#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:03:22.67#ibcon#first serial, iclass 24, count 0 2006.189.08:03:22.67#ibcon#enter sib2, iclass 24, count 0 2006.189.08:03:22.67#ibcon#flushed, iclass 24, count 0 2006.189.08:03:22.67#ibcon#about to write, iclass 24, count 0 2006.189.08:03:22.67#ibcon#wrote, iclass 24, count 0 2006.189.08:03:22.67#ibcon#about to read 3, iclass 24, count 0 2006.189.08:03:22.69#ibcon#read 3, iclass 24, count 0 2006.189.08:03:22.69#ibcon#about to read 4, iclass 24, count 0 2006.189.08:03:22.69#ibcon#read 4, iclass 24, count 0 2006.189.08:03:22.69#ibcon#about to read 5, iclass 24, count 0 2006.189.08:03:22.69#ibcon#read 5, iclass 24, count 0 2006.189.08:03:22.69#ibcon#about to read 6, iclass 24, count 0 2006.189.08:03:22.69#ibcon#read 6, iclass 24, count 0 2006.189.08:03:22.69#ibcon#end of sib2, iclass 24, count 0 2006.189.08:03:22.69#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:03:22.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:03:22.69#ibcon#[25=BW32\r\n] 2006.189.08:03:22.69#ibcon#*before write, iclass 24, count 0 2006.189.08:03:22.69#ibcon#enter sib2, iclass 24, count 0 2006.189.08:03:22.69#ibcon#flushed, iclass 24, count 0 2006.189.08:03:22.69#ibcon#about to write, iclass 24, count 0 2006.189.08:03:22.69#ibcon#wrote, iclass 24, count 0 2006.189.08:03:22.69#ibcon#about to read 3, iclass 24, count 0 2006.189.08:03:22.72#ibcon#read 3, iclass 24, count 0 2006.189.08:03:22.72#ibcon#about to read 4, iclass 24, count 0 2006.189.08:03:22.72#ibcon#read 4, iclass 24, count 0 2006.189.08:03:22.72#ibcon#about to read 5, iclass 24, count 0 2006.189.08:03:22.72#ibcon#read 5, iclass 24, count 0 2006.189.08:03:22.72#ibcon#about to read 6, iclass 24, count 0 2006.189.08:03:22.72#ibcon#read 6, iclass 24, count 0 2006.189.08:03:22.72#ibcon#end of sib2, iclass 24, count 0 2006.189.08:03:22.72#ibcon#*after write, iclass 24, count 0 2006.189.08:03:22.72#ibcon#*before return 0, iclass 24, count 0 2006.189.08:03:22.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:22.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:03:22.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:03:22.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:03:22.72$vc4f8/vbbw=wide 2006.189.08:03:22.72#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.08:03:22.72#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.08:03:22.72#ibcon#ireg 8 cls_cnt 0 2006.189.08:03:22.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:03:22.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:03:22.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:03:22.79#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:03:22.79#ibcon#first serial, iclass 26, count 0 2006.189.08:03:22.79#ibcon#enter sib2, iclass 26, count 0 2006.189.08:03:22.79#ibcon#flushed, iclass 26, count 0 2006.189.08:03:22.79#ibcon#about to write, iclass 26, count 0 2006.189.08:03:22.79#ibcon#wrote, iclass 26, count 0 2006.189.08:03:22.79#ibcon#about to read 3, iclass 26, count 0 2006.189.08:03:22.81#ibcon#read 3, iclass 26, count 0 2006.189.08:03:22.81#ibcon#about to read 4, iclass 26, count 0 2006.189.08:03:22.81#ibcon#read 4, iclass 26, count 0 2006.189.08:03:22.81#ibcon#about to read 5, iclass 26, count 0 2006.189.08:03:22.81#ibcon#read 5, iclass 26, count 0 2006.189.08:03:22.81#ibcon#about to read 6, iclass 26, count 0 2006.189.08:03:22.81#ibcon#read 6, iclass 26, count 0 2006.189.08:03:22.81#ibcon#end of sib2, iclass 26, count 0 2006.189.08:03:22.81#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:03:22.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:03:22.81#ibcon#[27=BW32\r\n] 2006.189.08:03:22.81#ibcon#*before write, iclass 26, count 0 2006.189.08:03:22.81#ibcon#enter sib2, iclass 26, count 0 2006.189.08:03:22.81#ibcon#flushed, iclass 26, count 0 2006.189.08:03:22.81#ibcon#about to write, iclass 26, count 0 2006.189.08:03:22.81#ibcon#wrote, iclass 26, count 0 2006.189.08:03:22.81#ibcon#about to read 3, iclass 26, count 0 2006.189.08:03:22.84#ibcon#read 3, iclass 26, count 0 2006.189.08:03:22.84#ibcon#about to read 4, iclass 26, count 0 2006.189.08:03:22.84#ibcon#read 4, iclass 26, count 0 2006.189.08:03:22.84#ibcon#about to read 5, iclass 26, count 0 2006.189.08:03:22.84#ibcon#read 5, iclass 26, count 0 2006.189.08:03:22.84#ibcon#about to read 6, iclass 26, count 0 2006.189.08:03:22.84#ibcon#read 6, iclass 26, count 0 2006.189.08:03:22.84#ibcon#end of sib2, iclass 26, count 0 2006.189.08:03:22.84#ibcon#*after write, iclass 26, count 0 2006.189.08:03:22.84#ibcon#*before return 0, iclass 26, count 0 2006.189.08:03:22.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:03:22.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:03:22.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:03:22.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:03:22.84$4f8m12a/ifd4f 2006.189.08:03:22.84$ifd4f/lo= 2006.189.08:03:22.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:03:22.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:03:22.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:03:22.84$ifd4f/patch= 2006.189.08:03:22.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:03:22.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:03:22.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:03:22.84$4f8m12a/"form=m,16.000,1:2 2006.189.08:03:22.84$4f8m12a/"tpicd 2006.189.08:03:22.84$4f8m12a/echo=off 2006.189.08:03:22.84$4f8m12a/xlog=off 2006.189.08:03:22.84:!2006.189.08:04:00 2006.189.08:03:39.14#trakl#Source acquired 2006.189.08:03:41.14#flagr#flagr/antenna,acquired 2006.189.08:04:00.00:preob 2006.189.08:04:00.14/onsource/TRACKING 2006.189.08:04:00.14:!2006.189.08:04:10 2006.189.08:04:10.00:data_valid=on 2006.189.08:04:10.00:midob 2006.189.08:04:11.14/onsource/TRACKING 2006.189.08:04:11.14/wx/25.66,1009.2,90 2006.189.08:04:11.29/cable/+6.4549E-03 2006.189.08:04:12.38/va/01,08,usb,yes,28,29 2006.189.08:04:12.38/va/02,07,usb,yes,28,29 2006.189.08:04:12.38/va/03,06,usb,yes,29,29 2006.189.08:04:12.38/va/04,07,usb,yes,29,31 2006.189.08:04:12.38/va/05,07,usb,yes,30,32 2006.189.08:04:12.38/va/06,06,usb,yes,30,29 2006.189.08:04:12.38/va/07,06,usb,yes,30,30 2006.189.08:04:12.38/va/08,06,usb,yes,32,32 2006.189.08:04:12.61/valo/01,532.99,yes,locked 2006.189.08:04:12.61/valo/02,572.99,yes,locked 2006.189.08:04:12.61/valo/03,672.99,yes,locked 2006.189.08:04:12.61/valo/04,832.99,yes,locked 2006.189.08:04:12.61/valo/05,652.99,yes,locked 2006.189.08:04:12.61/valo/06,772.99,yes,locked 2006.189.08:04:12.61/valo/07,832.99,yes,locked 2006.189.08:04:12.61/valo/08,852.99,yes,locked 2006.189.08:04:13.70/vb/01,04,usb,yes,28,27 2006.189.08:04:13.70/vb/02,04,usb,yes,30,31 2006.189.08:04:13.70/vb/03,04,usb,yes,26,30 2006.189.08:04:13.70/vb/04,04,usb,yes,27,27 2006.189.08:04:13.70/vb/05,04,usb,yes,26,30 2006.189.08:04:13.70/vb/06,04,usb,yes,27,29 2006.189.08:04:13.70/vb/07,04,usb,yes,29,29 2006.189.08:04:13.70/vb/08,04,usb,yes,26,30 2006.189.08:04:13.93/vblo/01,632.99,yes,locked 2006.189.08:04:13.93/vblo/02,640.99,yes,locked 2006.189.08:04:13.93/vblo/03,656.99,yes,locked 2006.189.08:04:13.93/vblo/04,712.99,yes,locked 2006.189.08:04:13.93/vblo/05,744.99,yes,locked 2006.189.08:04:13.93/vblo/06,752.99,yes,locked 2006.189.08:04:13.93/vblo/07,734.99,yes,locked 2006.189.08:04:13.93/vblo/08,744.99,yes,locked 2006.189.08:04:14.08/vabw/8 2006.189.08:04:14.23/vbbw/8 2006.189.08:04:14.32/xfe/off,on,14.7 2006.189.08:04:14.70/ifatt/23,28,28,28 2006.189.08:04:15.08/fmout-gps/S +2.96E-07 2006.189.08:04:15.16:!2006.189.08:05:10 2006.189.08:05:10.00:data_valid=off 2006.189.08:05:10.00:postob 2006.189.08:05:10.20/cable/+6.4554E-03 2006.189.08:05:10.20/wx/25.65,1009.2,90 2006.189.08:05:11.08/fmout-gps/S +2.96E-07 2006.189.08:05:11.08:scan_name=189-0806,k06189,60 2006.189.08:05:11.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.189.08:05:11.14#flagr#flagr/antenna,new-source 2006.189.08:05:12.14:checkk5 2006.189.08:05:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:05:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:05:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:05:13.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:05:14.05/chk_obsdata//k5ts1/T1890804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:05:14.43/chk_obsdata//k5ts2/T1890804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:05:14.80/chk_obsdata//k5ts3/T1890804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:05:15.18/chk_obsdata//k5ts4/T1890804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:05:15.87/k5log//k5ts1_log_newline 2006.189.08:05:16.56/k5log//k5ts2_log_newline 2006.189.08:05:17.26/k5log//k5ts3_log_newline 2006.189.08:05:17.96/k5log//k5ts4_log_newline 2006.189.08:05:17.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:05:17.99:4f8m12a=2 2006.189.08:05:17.99$4f8m12a/echo=on 2006.189.08:05:17.99$4f8m12a/pcalon 2006.189.08:05:17.99$pcalon/"no phase cal control is implemented here 2006.189.08:05:17.99$4f8m12a/"tpicd=stop 2006.189.08:05:17.99$4f8m12a/vc4f8 2006.189.08:05:17.99$vc4f8/valo=1,532.99 2006.189.08:05:17.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.08:05:17.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.08:05:17.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:17.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:17.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:17.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:17.99#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:05:17.99#ibcon#first serial, iclass 37, count 0 2006.189.08:05:17.99#ibcon#enter sib2, iclass 37, count 0 2006.189.08:05:17.99#ibcon#flushed, iclass 37, count 0 2006.189.08:05:17.99#ibcon#about to write, iclass 37, count 0 2006.189.08:05:17.99#ibcon#wrote, iclass 37, count 0 2006.189.08:05:17.99#ibcon#about to read 3, iclass 37, count 0 2006.189.08:05:18.04#ibcon#read 3, iclass 37, count 0 2006.189.08:05:18.04#ibcon#about to read 4, iclass 37, count 0 2006.189.08:05:18.04#ibcon#read 4, iclass 37, count 0 2006.189.08:05:18.04#ibcon#about to read 5, iclass 37, count 0 2006.189.08:05:18.04#ibcon#read 5, iclass 37, count 0 2006.189.08:05:18.04#ibcon#about to read 6, iclass 37, count 0 2006.189.08:05:18.04#ibcon#read 6, iclass 37, count 0 2006.189.08:05:18.04#ibcon#end of sib2, iclass 37, count 0 2006.189.08:05:18.04#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:05:18.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:05:18.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:05:18.04#ibcon#*before write, iclass 37, count 0 2006.189.08:05:18.04#ibcon#enter sib2, iclass 37, count 0 2006.189.08:05:18.04#ibcon#flushed, iclass 37, count 0 2006.189.08:05:18.04#ibcon#about to write, iclass 37, count 0 2006.189.08:05:18.04#ibcon#wrote, iclass 37, count 0 2006.189.08:05:18.04#ibcon#about to read 3, iclass 37, count 0 2006.189.08:05:18.09#ibcon#read 3, iclass 37, count 0 2006.189.08:05:18.09#ibcon#about to read 4, iclass 37, count 0 2006.189.08:05:18.09#ibcon#read 4, iclass 37, count 0 2006.189.08:05:18.09#ibcon#about to read 5, iclass 37, count 0 2006.189.08:05:18.09#ibcon#read 5, iclass 37, count 0 2006.189.08:05:18.09#ibcon#about to read 6, iclass 37, count 0 2006.189.08:05:18.09#ibcon#read 6, iclass 37, count 0 2006.189.08:05:18.09#ibcon#end of sib2, iclass 37, count 0 2006.189.08:05:18.09#ibcon#*after write, iclass 37, count 0 2006.189.08:05:18.09#ibcon#*before return 0, iclass 37, count 0 2006.189.08:05:18.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:18.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:18.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:05:18.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:05:18.09$vc4f8/va=1,8 2006.189.08:05:18.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.08:05:18.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.08:05:18.09#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:18.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:18.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:18.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:18.09#ibcon#enter wrdev, iclass 39, count 2 2006.189.08:05:18.09#ibcon#first serial, iclass 39, count 2 2006.189.08:05:18.09#ibcon#enter sib2, iclass 39, count 2 2006.189.08:05:18.09#ibcon#flushed, iclass 39, count 2 2006.189.08:05:18.09#ibcon#about to write, iclass 39, count 2 2006.189.08:05:18.09#ibcon#wrote, iclass 39, count 2 2006.189.08:05:18.09#ibcon#about to read 3, iclass 39, count 2 2006.189.08:05:18.12#ibcon#read 3, iclass 39, count 2 2006.189.08:05:18.12#ibcon#about to read 4, iclass 39, count 2 2006.189.08:05:18.12#ibcon#read 4, iclass 39, count 2 2006.189.08:05:18.12#ibcon#about to read 5, iclass 39, count 2 2006.189.08:05:18.12#ibcon#read 5, iclass 39, count 2 2006.189.08:05:18.12#ibcon#about to read 6, iclass 39, count 2 2006.189.08:05:18.12#ibcon#read 6, iclass 39, count 2 2006.189.08:05:18.12#ibcon#end of sib2, iclass 39, count 2 2006.189.08:05:18.12#ibcon#*mode == 0, iclass 39, count 2 2006.189.08:05:18.12#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.08:05:18.12#ibcon#[25=AT01-08\r\n] 2006.189.08:05:18.12#ibcon#*before write, iclass 39, count 2 2006.189.08:05:18.12#ibcon#enter sib2, iclass 39, count 2 2006.189.08:05:18.12#ibcon#flushed, iclass 39, count 2 2006.189.08:05:18.12#ibcon#about to write, iclass 39, count 2 2006.189.08:05:18.12#ibcon#wrote, iclass 39, count 2 2006.189.08:05:18.12#ibcon#about to read 3, iclass 39, count 2 2006.189.08:05:18.16#ibcon#read 3, iclass 39, count 2 2006.189.08:05:18.16#ibcon#about to read 4, iclass 39, count 2 2006.189.08:05:18.16#ibcon#read 4, iclass 39, count 2 2006.189.08:05:18.16#ibcon#about to read 5, iclass 39, count 2 2006.189.08:05:18.16#ibcon#read 5, iclass 39, count 2 2006.189.08:05:18.16#ibcon#about to read 6, iclass 39, count 2 2006.189.08:05:18.16#ibcon#read 6, iclass 39, count 2 2006.189.08:05:18.16#ibcon#end of sib2, iclass 39, count 2 2006.189.08:05:18.16#ibcon#*after write, iclass 39, count 2 2006.189.08:05:18.16#ibcon#*before return 0, iclass 39, count 2 2006.189.08:05:18.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:18.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:18.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.08:05:18.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:18.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:18.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:18.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:18.28#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:05:18.28#ibcon#first serial, iclass 39, count 0 2006.189.08:05:18.28#ibcon#enter sib2, iclass 39, count 0 2006.189.08:05:18.28#ibcon#flushed, iclass 39, count 0 2006.189.08:05:18.28#ibcon#about to write, iclass 39, count 0 2006.189.08:05:18.28#ibcon#wrote, iclass 39, count 0 2006.189.08:05:18.28#ibcon#about to read 3, iclass 39, count 0 2006.189.08:05:18.30#ibcon#read 3, iclass 39, count 0 2006.189.08:05:18.30#ibcon#about to read 4, iclass 39, count 0 2006.189.08:05:18.30#ibcon#read 4, iclass 39, count 0 2006.189.08:05:18.30#ibcon#about to read 5, iclass 39, count 0 2006.189.08:05:18.30#ibcon#read 5, iclass 39, count 0 2006.189.08:05:18.30#ibcon#about to read 6, iclass 39, count 0 2006.189.08:05:18.30#ibcon#read 6, iclass 39, count 0 2006.189.08:05:18.30#ibcon#end of sib2, iclass 39, count 0 2006.189.08:05:18.30#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:05:18.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:05:18.30#ibcon#[25=USB\r\n] 2006.189.08:05:18.30#ibcon#*before write, iclass 39, count 0 2006.189.08:05:18.30#ibcon#enter sib2, iclass 39, count 0 2006.189.08:05:18.30#ibcon#flushed, iclass 39, count 0 2006.189.08:05:18.30#ibcon#about to write, iclass 39, count 0 2006.189.08:05:18.30#ibcon#wrote, iclass 39, count 0 2006.189.08:05:18.30#ibcon#about to read 3, iclass 39, count 0 2006.189.08:05:18.33#ibcon#read 3, iclass 39, count 0 2006.189.08:05:18.33#ibcon#about to read 4, iclass 39, count 0 2006.189.08:05:18.33#ibcon#read 4, iclass 39, count 0 2006.189.08:05:18.33#ibcon#about to read 5, iclass 39, count 0 2006.189.08:05:18.33#ibcon#read 5, iclass 39, count 0 2006.189.08:05:18.33#ibcon#about to read 6, iclass 39, count 0 2006.189.08:05:18.33#ibcon#read 6, iclass 39, count 0 2006.189.08:05:18.33#ibcon#end of sib2, iclass 39, count 0 2006.189.08:05:18.33#ibcon#*after write, iclass 39, count 0 2006.189.08:05:18.33#ibcon#*before return 0, iclass 39, count 0 2006.189.08:05:18.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:18.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:18.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:05:18.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:05:18.33$vc4f8/valo=2,572.99 2006.189.08:05:18.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.08:05:18.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.08:05:18.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:18.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:18.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:18.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:18.33#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:05:18.33#ibcon#first serial, iclass 3, count 0 2006.189.08:05:18.33#ibcon#enter sib2, iclass 3, count 0 2006.189.08:05:18.33#ibcon#flushed, iclass 3, count 0 2006.189.08:05:18.33#ibcon#about to write, iclass 3, count 0 2006.189.08:05:18.33#ibcon#wrote, iclass 3, count 0 2006.189.08:05:18.33#ibcon#about to read 3, iclass 3, count 0 2006.189.08:05:18.35#ibcon#read 3, iclass 3, count 0 2006.189.08:05:18.35#ibcon#about to read 4, iclass 3, count 0 2006.189.08:05:18.35#ibcon#read 4, iclass 3, count 0 2006.189.08:05:18.35#ibcon#about to read 5, iclass 3, count 0 2006.189.08:05:18.35#ibcon#read 5, iclass 3, count 0 2006.189.08:05:18.35#ibcon#about to read 6, iclass 3, count 0 2006.189.08:05:18.35#ibcon#read 6, iclass 3, count 0 2006.189.08:05:18.35#ibcon#end of sib2, iclass 3, count 0 2006.189.08:05:18.35#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:05:18.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:05:18.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:05:18.35#ibcon#*before write, iclass 3, count 0 2006.189.08:05:18.35#ibcon#enter sib2, iclass 3, count 0 2006.189.08:05:18.35#ibcon#flushed, iclass 3, count 0 2006.189.08:05:18.35#ibcon#about to write, iclass 3, count 0 2006.189.08:05:18.35#ibcon#wrote, iclass 3, count 0 2006.189.08:05:18.35#ibcon#about to read 3, iclass 3, count 0 2006.189.08:05:18.39#ibcon#read 3, iclass 3, count 0 2006.189.08:05:18.39#ibcon#about to read 4, iclass 3, count 0 2006.189.08:05:18.39#ibcon#read 4, iclass 3, count 0 2006.189.08:05:18.39#ibcon#about to read 5, iclass 3, count 0 2006.189.08:05:18.39#ibcon#read 5, iclass 3, count 0 2006.189.08:05:18.39#ibcon#about to read 6, iclass 3, count 0 2006.189.08:05:18.39#ibcon#read 6, iclass 3, count 0 2006.189.08:05:18.39#ibcon#end of sib2, iclass 3, count 0 2006.189.08:05:18.39#ibcon#*after write, iclass 3, count 0 2006.189.08:05:18.39#ibcon#*before return 0, iclass 3, count 0 2006.189.08:05:18.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:18.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:18.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:05:18.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:05:18.39$vc4f8/va=2,7 2006.189.08:05:18.39#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.08:05:18.39#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.08:05:18.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:18.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:18.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:18.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:18.45#ibcon#enter wrdev, iclass 5, count 2 2006.189.08:05:18.45#ibcon#first serial, iclass 5, count 2 2006.189.08:05:18.45#ibcon#enter sib2, iclass 5, count 2 2006.189.08:05:18.45#ibcon#flushed, iclass 5, count 2 2006.189.08:05:18.45#ibcon#about to write, iclass 5, count 2 2006.189.08:05:18.45#ibcon#wrote, iclass 5, count 2 2006.189.08:05:18.45#ibcon#about to read 3, iclass 5, count 2 2006.189.08:05:18.47#ibcon#read 3, iclass 5, count 2 2006.189.08:05:18.47#ibcon#about to read 4, iclass 5, count 2 2006.189.08:05:18.47#ibcon#read 4, iclass 5, count 2 2006.189.08:05:18.47#ibcon#about to read 5, iclass 5, count 2 2006.189.08:05:18.47#ibcon#read 5, iclass 5, count 2 2006.189.08:05:18.47#ibcon#about to read 6, iclass 5, count 2 2006.189.08:05:18.47#ibcon#read 6, iclass 5, count 2 2006.189.08:05:18.47#ibcon#end of sib2, iclass 5, count 2 2006.189.08:05:18.47#ibcon#*mode == 0, iclass 5, count 2 2006.189.08:05:18.47#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.08:05:18.47#ibcon#[25=AT02-07\r\n] 2006.189.08:05:18.47#ibcon#*before write, iclass 5, count 2 2006.189.08:05:18.47#ibcon#enter sib2, iclass 5, count 2 2006.189.08:05:18.47#ibcon#flushed, iclass 5, count 2 2006.189.08:05:18.47#ibcon#about to write, iclass 5, count 2 2006.189.08:05:18.47#ibcon#wrote, iclass 5, count 2 2006.189.08:05:18.47#ibcon#about to read 3, iclass 5, count 2 2006.189.08:05:18.50#ibcon#read 3, iclass 5, count 2 2006.189.08:05:18.50#ibcon#about to read 4, iclass 5, count 2 2006.189.08:05:18.50#ibcon#read 4, iclass 5, count 2 2006.189.08:05:18.50#ibcon#about to read 5, iclass 5, count 2 2006.189.08:05:18.50#ibcon#read 5, iclass 5, count 2 2006.189.08:05:18.50#ibcon#about to read 6, iclass 5, count 2 2006.189.08:05:18.50#ibcon#read 6, iclass 5, count 2 2006.189.08:05:18.50#ibcon#end of sib2, iclass 5, count 2 2006.189.08:05:18.50#ibcon#*after write, iclass 5, count 2 2006.189.08:05:18.50#ibcon#*before return 0, iclass 5, count 2 2006.189.08:05:18.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:18.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:18.50#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.08:05:18.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:18.50#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:18.62#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:18.62#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:18.62#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:05:18.62#ibcon#first serial, iclass 5, count 0 2006.189.08:05:18.62#ibcon#enter sib2, iclass 5, count 0 2006.189.08:05:18.62#ibcon#flushed, iclass 5, count 0 2006.189.08:05:18.62#ibcon#about to write, iclass 5, count 0 2006.189.08:05:18.62#ibcon#wrote, iclass 5, count 0 2006.189.08:05:18.62#ibcon#about to read 3, iclass 5, count 0 2006.189.08:05:18.64#ibcon#read 3, iclass 5, count 0 2006.189.08:05:18.64#ibcon#about to read 4, iclass 5, count 0 2006.189.08:05:18.64#ibcon#read 4, iclass 5, count 0 2006.189.08:05:18.64#ibcon#about to read 5, iclass 5, count 0 2006.189.08:05:18.64#ibcon#read 5, iclass 5, count 0 2006.189.08:05:18.64#ibcon#about to read 6, iclass 5, count 0 2006.189.08:05:18.64#ibcon#read 6, iclass 5, count 0 2006.189.08:05:18.64#ibcon#end of sib2, iclass 5, count 0 2006.189.08:05:18.64#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:05:18.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:05:18.64#ibcon#[25=USB\r\n] 2006.189.08:05:18.64#ibcon#*before write, iclass 5, count 0 2006.189.08:05:18.64#ibcon#enter sib2, iclass 5, count 0 2006.189.08:05:18.64#ibcon#flushed, iclass 5, count 0 2006.189.08:05:18.64#ibcon#about to write, iclass 5, count 0 2006.189.08:05:18.64#ibcon#wrote, iclass 5, count 0 2006.189.08:05:18.64#ibcon#about to read 3, iclass 5, count 0 2006.189.08:05:18.67#ibcon#read 3, iclass 5, count 0 2006.189.08:05:18.67#ibcon#about to read 4, iclass 5, count 0 2006.189.08:05:18.67#ibcon#read 4, iclass 5, count 0 2006.189.08:05:18.67#ibcon#about to read 5, iclass 5, count 0 2006.189.08:05:18.67#ibcon#read 5, iclass 5, count 0 2006.189.08:05:18.67#ibcon#about to read 6, iclass 5, count 0 2006.189.08:05:18.67#ibcon#read 6, iclass 5, count 0 2006.189.08:05:18.67#ibcon#end of sib2, iclass 5, count 0 2006.189.08:05:18.67#ibcon#*after write, iclass 5, count 0 2006.189.08:05:18.67#ibcon#*before return 0, iclass 5, count 0 2006.189.08:05:18.67#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:18.67#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:18.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:05:18.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:05:18.67$vc4f8/valo=3,672.99 2006.189.08:05:18.67#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.08:05:18.67#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.08:05:18.67#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:18.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:18.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:18.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:18.67#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:05:18.67#ibcon#first serial, iclass 7, count 0 2006.189.08:05:18.67#ibcon#enter sib2, iclass 7, count 0 2006.189.08:05:18.67#ibcon#flushed, iclass 7, count 0 2006.189.08:05:18.67#ibcon#about to write, iclass 7, count 0 2006.189.08:05:18.67#ibcon#wrote, iclass 7, count 0 2006.189.08:05:18.67#ibcon#about to read 3, iclass 7, count 0 2006.189.08:05:18.69#ibcon#read 3, iclass 7, count 0 2006.189.08:05:18.69#ibcon#about to read 4, iclass 7, count 0 2006.189.08:05:18.69#ibcon#read 4, iclass 7, count 0 2006.189.08:05:18.69#ibcon#about to read 5, iclass 7, count 0 2006.189.08:05:18.69#ibcon#read 5, iclass 7, count 0 2006.189.08:05:18.69#ibcon#about to read 6, iclass 7, count 0 2006.189.08:05:18.69#ibcon#read 6, iclass 7, count 0 2006.189.08:05:18.69#ibcon#end of sib2, iclass 7, count 0 2006.189.08:05:18.69#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:05:18.69#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:05:18.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:05:18.69#ibcon#*before write, iclass 7, count 0 2006.189.08:05:18.69#ibcon#enter sib2, iclass 7, count 0 2006.189.08:05:18.69#ibcon#flushed, iclass 7, count 0 2006.189.08:05:18.69#ibcon#about to write, iclass 7, count 0 2006.189.08:05:18.69#ibcon#wrote, iclass 7, count 0 2006.189.08:05:18.69#ibcon#about to read 3, iclass 7, count 0 2006.189.08:05:18.73#ibcon#read 3, iclass 7, count 0 2006.189.08:05:18.73#ibcon#about to read 4, iclass 7, count 0 2006.189.08:05:18.73#ibcon#read 4, iclass 7, count 0 2006.189.08:05:18.73#ibcon#about to read 5, iclass 7, count 0 2006.189.08:05:18.73#ibcon#read 5, iclass 7, count 0 2006.189.08:05:18.73#ibcon#about to read 6, iclass 7, count 0 2006.189.08:05:18.73#ibcon#read 6, iclass 7, count 0 2006.189.08:05:18.73#ibcon#end of sib2, iclass 7, count 0 2006.189.08:05:18.73#ibcon#*after write, iclass 7, count 0 2006.189.08:05:18.73#ibcon#*before return 0, iclass 7, count 0 2006.189.08:05:18.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:18.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:18.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:05:18.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:05:18.73$vc4f8/va=3,6 2006.189.08:05:18.73#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.08:05:18.73#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.08:05:18.73#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:18.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:18.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:18.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:18.79#ibcon#enter wrdev, iclass 11, count 2 2006.189.08:05:18.79#ibcon#first serial, iclass 11, count 2 2006.189.08:05:18.79#ibcon#enter sib2, iclass 11, count 2 2006.189.08:05:18.79#ibcon#flushed, iclass 11, count 2 2006.189.08:05:18.79#ibcon#about to write, iclass 11, count 2 2006.189.08:05:18.79#ibcon#wrote, iclass 11, count 2 2006.189.08:05:18.79#ibcon#about to read 3, iclass 11, count 2 2006.189.08:05:18.81#ibcon#read 3, iclass 11, count 2 2006.189.08:05:18.81#ibcon#about to read 4, iclass 11, count 2 2006.189.08:05:18.81#ibcon#read 4, iclass 11, count 2 2006.189.08:05:18.81#ibcon#about to read 5, iclass 11, count 2 2006.189.08:05:18.81#ibcon#read 5, iclass 11, count 2 2006.189.08:05:18.81#ibcon#about to read 6, iclass 11, count 2 2006.189.08:05:18.81#ibcon#read 6, iclass 11, count 2 2006.189.08:05:18.81#ibcon#end of sib2, iclass 11, count 2 2006.189.08:05:18.81#ibcon#*mode == 0, iclass 11, count 2 2006.189.08:05:18.81#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.08:05:18.81#ibcon#[25=AT03-06\r\n] 2006.189.08:05:18.81#ibcon#*before write, iclass 11, count 2 2006.189.08:05:18.81#ibcon#enter sib2, iclass 11, count 2 2006.189.08:05:18.81#ibcon#flushed, iclass 11, count 2 2006.189.08:05:18.81#ibcon#about to write, iclass 11, count 2 2006.189.08:05:18.81#ibcon#wrote, iclass 11, count 2 2006.189.08:05:18.81#ibcon#about to read 3, iclass 11, count 2 2006.189.08:05:18.84#ibcon#read 3, iclass 11, count 2 2006.189.08:05:18.84#ibcon#about to read 4, iclass 11, count 2 2006.189.08:05:18.84#ibcon#read 4, iclass 11, count 2 2006.189.08:05:18.84#ibcon#about to read 5, iclass 11, count 2 2006.189.08:05:18.84#ibcon#read 5, iclass 11, count 2 2006.189.08:05:18.84#ibcon#about to read 6, iclass 11, count 2 2006.189.08:05:18.84#ibcon#read 6, iclass 11, count 2 2006.189.08:05:18.84#ibcon#end of sib2, iclass 11, count 2 2006.189.08:05:18.84#ibcon#*after write, iclass 11, count 2 2006.189.08:05:18.84#ibcon#*before return 0, iclass 11, count 2 2006.189.08:05:18.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:18.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:18.84#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.08:05:18.84#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:18.84#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:18.96#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:18.96#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:18.96#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:05:18.96#ibcon#first serial, iclass 11, count 0 2006.189.08:05:18.96#ibcon#enter sib2, iclass 11, count 0 2006.189.08:05:18.96#ibcon#flushed, iclass 11, count 0 2006.189.08:05:18.96#ibcon#about to write, iclass 11, count 0 2006.189.08:05:18.96#ibcon#wrote, iclass 11, count 0 2006.189.08:05:18.96#ibcon#about to read 3, iclass 11, count 0 2006.189.08:05:18.98#ibcon#read 3, iclass 11, count 0 2006.189.08:05:18.98#ibcon#about to read 4, iclass 11, count 0 2006.189.08:05:18.98#ibcon#read 4, iclass 11, count 0 2006.189.08:05:18.98#ibcon#about to read 5, iclass 11, count 0 2006.189.08:05:18.98#ibcon#read 5, iclass 11, count 0 2006.189.08:05:18.98#ibcon#about to read 6, iclass 11, count 0 2006.189.08:05:18.98#ibcon#read 6, iclass 11, count 0 2006.189.08:05:18.98#ibcon#end of sib2, iclass 11, count 0 2006.189.08:05:18.98#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:05:18.98#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:05:18.98#ibcon#[25=USB\r\n] 2006.189.08:05:18.98#ibcon#*before write, iclass 11, count 0 2006.189.08:05:18.98#ibcon#enter sib2, iclass 11, count 0 2006.189.08:05:18.98#ibcon#flushed, iclass 11, count 0 2006.189.08:05:18.98#ibcon#about to write, iclass 11, count 0 2006.189.08:05:18.98#ibcon#wrote, iclass 11, count 0 2006.189.08:05:18.98#ibcon#about to read 3, iclass 11, count 0 2006.189.08:05:19.01#ibcon#read 3, iclass 11, count 0 2006.189.08:05:19.01#ibcon#about to read 4, iclass 11, count 0 2006.189.08:05:19.01#ibcon#read 4, iclass 11, count 0 2006.189.08:05:19.01#ibcon#about to read 5, iclass 11, count 0 2006.189.08:05:19.01#ibcon#read 5, iclass 11, count 0 2006.189.08:05:19.01#ibcon#about to read 6, iclass 11, count 0 2006.189.08:05:19.01#ibcon#read 6, iclass 11, count 0 2006.189.08:05:19.01#ibcon#end of sib2, iclass 11, count 0 2006.189.08:05:19.01#ibcon#*after write, iclass 11, count 0 2006.189.08:05:19.01#ibcon#*before return 0, iclass 11, count 0 2006.189.08:05:19.01#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:19.01#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:19.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:05:19.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:05:19.01$vc4f8/valo=4,832.99 2006.189.08:05:19.01#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.08:05:19.01#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.08:05:19.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:19.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:19.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:19.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:19.01#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:05:19.01#ibcon#first serial, iclass 13, count 0 2006.189.08:05:19.01#ibcon#enter sib2, iclass 13, count 0 2006.189.08:05:19.01#ibcon#flushed, iclass 13, count 0 2006.189.08:05:19.01#ibcon#about to write, iclass 13, count 0 2006.189.08:05:19.01#ibcon#wrote, iclass 13, count 0 2006.189.08:05:19.01#ibcon#about to read 3, iclass 13, count 0 2006.189.08:05:19.03#ibcon#read 3, iclass 13, count 0 2006.189.08:05:19.03#ibcon#about to read 4, iclass 13, count 0 2006.189.08:05:19.03#ibcon#read 4, iclass 13, count 0 2006.189.08:05:19.03#ibcon#about to read 5, iclass 13, count 0 2006.189.08:05:19.03#ibcon#read 5, iclass 13, count 0 2006.189.08:05:19.03#ibcon#about to read 6, iclass 13, count 0 2006.189.08:05:19.03#ibcon#read 6, iclass 13, count 0 2006.189.08:05:19.03#ibcon#end of sib2, iclass 13, count 0 2006.189.08:05:19.03#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:05:19.03#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:05:19.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:05:19.03#ibcon#*before write, iclass 13, count 0 2006.189.08:05:19.03#ibcon#enter sib2, iclass 13, count 0 2006.189.08:05:19.03#ibcon#flushed, iclass 13, count 0 2006.189.08:05:19.03#ibcon#about to write, iclass 13, count 0 2006.189.08:05:19.03#ibcon#wrote, iclass 13, count 0 2006.189.08:05:19.03#ibcon#about to read 3, iclass 13, count 0 2006.189.08:05:19.07#ibcon#read 3, iclass 13, count 0 2006.189.08:05:19.07#ibcon#about to read 4, iclass 13, count 0 2006.189.08:05:19.07#ibcon#read 4, iclass 13, count 0 2006.189.08:05:19.07#ibcon#about to read 5, iclass 13, count 0 2006.189.08:05:19.07#ibcon#read 5, iclass 13, count 0 2006.189.08:05:19.07#ibcon#about to read 6, iclass 13, count 0 2006.189.08:05:19.07#ibcon#read 6, iclass 13, count 0 2006.189.08:05:19.07#ibcon#end of sib2, iclass 13, count 0 2006.189.08:05:19.07#ibcon#*after write, iclass 13, count 0 2006.189.08:05:19.07#ibcon#*before return 0, iclass 13, count 0 2006.189.08:05:19.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:19.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:19.07#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:05:19.07#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:05:19.07$vc4f8/va=4,7 2006.189.08:05:19.07#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.08:05:19.07#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.08:05:19.07#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:19.07#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:19.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:19.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:19.13#ibcon#enter wrdev, iclass 15, count 2 2006.189.08:05:19.13#ibcon#first serial, iclass 15, count 2 2006.189.08:05:19.13#ibcon#enter sib2, iclass 15, count 2 2006.189.08:05:19.13#ibcon#flushed, iclass 15, count 2 2006.189.08:05:19.13#ibcon#about to write, iclass 15, count 2 2006.189.08:05:19.13#ibcon#wrote, iclass 15, count 2 2006.189.08:05:19.13#ibcon#about to read 3, iclass 15, count 2 2006.189.08:05:19.15#ibcon#read 3, iclass 15, count 2 2006.189.08:05:19.15#ibcon#about to read 4, iclass 15, count 2 2006.189.08:05:19.15#ibcon#read 4, iclass 15, count 2 2006.189.08:05:19.15#ibcon#about to read 5, iclass 15, count 2 2006.189.08:05:19.15#ibcon#read 5, iclass 15, count 2 2006.189.08:05:19.15#ibcon#about to read 6, iclass 15, count 2 2006.189.08:05:19.15#ibcon#read 6, iclass 15, count 2 2006.189.08:05:19.15#ibcon#end of sib2, iclass 15, count 2 2006.189.08:05:19.15#ibcon#*mode == 0, iclass 15, count 2 2006.189.08:05:19.15#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.08:05:19.15#ibcon#[25=AT04-07\r\n] 2006.189.08:05:19.15#ibcon#*before write, iclass 15, count 2 2006.189.08:05:19.15#ibcon#enter sib2, iclass 15, count 2 2006.189.08:05:19.15#ibcon#flushed, iclass 15, count 2 2006.189.08:05:19.15#ibcon#about to write, iclass 15, count 2 2006.189.08:05:19.15#ibcon#wrote, iclass 15, count 2 2006.189.08:05:19.15#ibcon#about to read 3, iclass 15, count 2 2006.189.08:05:19.18#ibcon#read 3, iclass 15, count 2 2006.189.08:05:19.18#ibcon#about to read 4, iclass 15, count 2 2006.189.08:05:19.18#ibcon#read 4, iclass 15, count 2 2006.189.08:05:19.18#ibcon#about to read 5, iclass 15, count 2 2006.189.08:05:19.18#ibcon#read 5, iclass 15, count 2 2006.189.08:05:19.18#ibcon#about to read 6, iclass 15, count 2 2006.189.08:05:19.18#ibcon#read 6, iclass 15, count 2 2006.189.08:05:19.18#ibcon#end of sib2, iclass 15, count 2 2006.189.08:05:19.18#ibcon#*after write, iclass 15, count 2 2006.189.08:05:19.18#ibcon#*before return 0, iclass 15, count 2 2006.189.08:05:19.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:19.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:19.18#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.08:05:19.18#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:19.18#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:19.30#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:19.30#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:19.30#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:05:19.30#ibcon#first serial, iclass 15, count 0 2006.189.08:05:19.30#ibcon#enter sib2, iclass 15, count 0 2006.189.08:05:19.30#ibcon#flushed, iclass 15, count 0 2006.189.08:05:19.30#ibcon#about to write, iclass 15, count 0 2006.189.08:05:19.30#ibcon#wrote, iclass 15, count 0 2006.189.08:05:19.30#ibcon#about to read 3, iclass 15, count 0 2006.189.08:05:19.32#ibcon#read 3, iclass 15, count 0 2006.189.08:05:19.32#ibcon#about to read 4, iclass 15, count 0 2006.189.08:05:19.32#ibcon#read 4, iclass 15, count 0 2006.189.08:05:19.32#ibcon#about to read 5, iclass 15, count 0 2006.189.08:05:19.32#ibcon#read 5, iclass 15, count 0 2006.189.08:05:19.32#ibcon#about to read 6, iclass 15, count 0 2006.189.08:05:19.32#ibcon#read 6, iclass 15, count 0 2006.189.08:05:19.32#ibcon#end of sib2, iclass 15, count 0 2006.189.08:05:19.32#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:05:19.32#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:05:19.32#ibcon#[25=USB\r\n] 2006.189.08:05:19.32#ibcon#*before write, iclass 15, count 0 2006.189.08:05:19.32#ibcon#enter sib2, iclass 15, count 0 2006.189.08:05:19.32#ibcon#flushed, iclass 15, count 0 2006.189.08:05:19.32#ibcon#about to write, iclass 15, count 0 2006.189.08:05:19.32#ibcon#wrote, iclass 15, count 0 2006.189.08:05:19.32#ibcon#about to read 3, iclass 15, count 0 2006.189.08:05:19.35#ibcon#read 3, iclass 15, count 0 2006.189.08:05:19.35#ibcon#about to read 4, iclass 15, count 0 2006.189.08:05:19.35#ibcon#read 4, iclass 15, count 0 2006.189.08:05:19.35#ibcon#about to read 5, iclass 15, count 0 2006.189.08:05:19.35#ibcon#read 5, iclass 15, count 0 2006.189.08:05:19.35#ibcon#about to read 6, iclass 15, count 0 2006.189.08:05:19.35#ibcon#read 6, iclass 15, count 0 2006.189.08:05:19.35#ibcon#end of sib2, iclass 15, count 0 2006.189.08:05:19.35#ibcon#*after write, iclass 15, count 0 2006.189.08:05:19.35#ibcon#*before return 0, iclass 15, count 0 2006.189.08:05:19.35#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:19.35#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:19.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:05:19.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:05:19.35$vc4f8/valo=5,652.99 2006.189.08:05:19.35#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.08:05:19.35#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.08:05:19.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:19.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:19.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:19.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:19.35#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:05:19.35#ibcon#first serial, iclass 17, count 0 2006.189.08:05:19.35#ibcon#enter sib2, iclass 17, count 0 2006.189.08:05:19.35#ibcon#flushed, iclass 17, count 0 2006.189.08:05:19.35#ibcon#about to write, iclass 17, count 0 2006.189.08:05:19.35#ibcon#wrote, iclass 17, count 0 2006.189.08:05:19.35#ibcon#about to read 3, iclass 17, count 0 2006.189.08:05:19.37#ibcon#read 3, iclass 17, count 0 2006.189.08:05:19.37#ibcon#about to read 4, iclass 17, count 0 2006.189.08:05:19.37#ibcon#read 4, iclass 17, count 0 2006.189.08:05:19.37#ibcon#about to read 5, iclass 17, count 0 2006.189.08:05:19.37#ibcon#read 5, iclass 17, count 0 2006.189.08:05:19.37#ibcon#about to read 6, iclass 17, count 0 2006.189.08:05:19.37#ibcon#read 6, iclass 17, count 0 2006.189.08:05:19.37#ibcon#end of sib2, iclass 17, count 0 2006.189.08:05:19.37#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:05:19.37#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:05:19.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:05:19.37#ibcon#*before write, iclass 17, count 0 2006.189.08:05:19.37#ibcon#enter sib2, iclass 17, count 0 2006.189.08:05:19.37#ibcon#flushed, iclass 17, count 0 2006.189.08:05:19.37#ibcon#about to write, iclass 17, count 0 2006.189.08:05:19.37#ibcon#wrote, iclass 17, count 0 2006.189.08:05:19.37#ibcon#about to read 3, iclass 17, count 0 2006.189.08:05:19.41#ibcon#read 3, iclass 17, count 0 2006.189.08:05:19.41#ibcon#about to read 4, iclass 17, count 0 2006.189.08:05:19.41#ibcon#read 4, iclass 17, count 0 2006.189.08:05:19.41#ibcon#about to read 5, iclass 17, count 0 2006.189.08:05:19.41#ibcon#read 5, iclass 17, count 0 2006.189.08:05:19.41#ibcon#about to read 6, iclass 17, count 0 2006.189.08:05:19.41#ibcon#read 6, iclass 17, count 0 2006.189.08:05:19.41#ibcon#end of sib2, iclass 17, count 0 2006.189.08:05:19.41#ibcon#*after write, iclass 17, count 0 2006.189.08:05:19.41#ibcon#*before return 0, iclass 17, count 0 2006.189.08:05:19.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:19.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:19.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:05:19.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:05:19.41$vc4f8/va=5,7 2006.189.08:05:19.41#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.08:05:19.41#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.08:05:19.41#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:19.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:19.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:19.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:19.47#ibcon#enter wrdev, iclass 19, count 2 2006.189.08:05:19.47#ibcon#first serial, iclass 19, count 2 2006.189.08:05:19.47#ibcon#enter sib2, iclass 19, count 2 2006.189.08:05:19.47#ibcon#flushed, iclass 19, count 2 2006.189.08:05:19.47#ibcon#about to write, iclass 19, count 2 2006.189.08:05:19.47#ibcon#wrote, iclass 19, count 2 2006.189.08:05:19.47#ibcon#about to read 3, iclass 19, count 2 2006.189.08:05:19.49#ibcon#read 3, iclass 19, count 2 2006.189.08:05:19.49#ibcon#about to read 4, iclass 19, count 2 2006.189.08:05:19.49#ibcon#read 4, iclass 19, count 2 2006.189.08:05:19.49#ibcon#about to read 5, iclass 19, count 2 2006.189.08:05:19.49#ibcon#read 5, iclass 19, count 2 2006.189.08:05:19.49#ibcon#about to read 6, iclass 19, count 2 2006.189.08:05:19.49#ibcon#read 6, iclass 19, count 2 2006.189.08:05:19.49#ibcon#end of sib2, iclass 19, count 2 2006.189.08:05:19.49#ibcon#*mode == 0, iclass 19, count 2 2006.189.08:05:19.49#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.08:05:19.49#ibcon#[25=AT05-07\r\n] 2006.189.08:05:19.49#ibcon#*before write, iclass 19, count 2 2006.189.08:05:19.49#ibcon#enter sib2, iclass 19, count 2 2006.189.08:05:19.49#ibcon#flushed, iclass 19, count 2 2006.189.08:05:19.49#ibcon#about to write, iclass 19, count 2 2006.189.08:05:19.49#ibcon#wrote, iclass 19, count 2 2006.189.08:05:19.49#ibcon#about to read 3, iclass 19, count 2 2006.189.08:05:19.52#ibcon#read 3, iclass 19, count 2 2006.189.08:05:19.52#ibcon#about to read 4, iclass 19, count 2 2006.189.08:05:19.52#ibcon#read 4, iclass 19, count 2 2006.189.08:05:19.52#ibcon#about to read 5, iclass 19, count 2 2006.189.08:05:19.52#ibcon#read 5, iclass 19, count 2 2006.189.08:05:19.52#ibcon#about to read 6, iclass 19, count 2 2006.189.08:05:19.52#ibcon#read 6, iclass 19, count 2 2006.189.08:05:19.52#ibcon#end of sib2, iclass 19, count 2 2006.189.08:05:19.52#ibcon#*after write, iclass 19, count 2 2006.189.08:05:19.52#ibcon#*before return 0, iclass 19, count 2 2006.189.08:05:19.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:19.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:19.52#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.08:05:19.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:19.52#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:19.64#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:19.64#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:19.64#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:05:19.64#ibcon#first serial, iclass 19, count 0 2006.189.08:05:19.64#ibcon#enter sib2, iclass 19, count 0 2006.189.08:05:19.64#ibcon#flushed, iclass 19, count 0 2006.189.08:05:19.64#ibcon#about to write, iclass 19, count 0 2006.189.08:05:19.64#ibcon#wrote, iclass 19, count 0 2006.189.08:05:19.64#ibcon#about to read 3, iclass 19, count 0 2006.189.08:05:19.66#ibcon#read 3, iclass 19, count 0 2006.189.08:05:19.66#ibcon#about to read 4, iclass 19, count 0 2006.189.08:05:19.66#ibcon#read 4, iclass 19, count 0 2006.189.08:05:19.66#ibcon#about to read 5, iclass 19, count 0 2006.189.08:05:19.66#ibcon#read 5, iclass 19, count 0 2006.189.08:05:19.66#ibcon#about to read 6, iclass 19, count 0 2006.189.08:05:19.66#ibcon#read 6, iclass 19, count 0 2006.189.08:05:19.66#ibcon#end of sib2, iclass 19, count 0 2006.189.08:05:19.66#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:05:19.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:05:19.66#ibcon#[25=USB\r\n] 2006.189.08:05:19.66#ibcon#*before write, iclass 19, count 0 2006.189.08:05:19.66#ibcon#enter sib2, iclass 19, count 0 2006.189.08:05:19.66#ibcon#flushed, iclass 19, count 0 2006.189.08:05:19.66#ibcon#about to write, iclass 19, count 0 2006.189.08:05:19.66#ibcon#wrote, iclass 19, count 0 2006.189.08:05:19.66#ibcon#about to read 3, iclass 19, count 0 2006.189.08:05:19.69#ibcon#read 3, iclass 19, count 0 2006.189.08:05:19.69#ibcon#about to read 4, iclass 19, count 0 2006.189.08:05:19.69#ibcon#read 4, iclass 19, count 0 2006.189.08:05:19.69#ibcon#about to read 5, iclass 19, count 0 2006.189.08:05:19.69#ibcon#read 5, iclass 19, count 0 2006.189.08:05:19.69#ibcon#about to read 6, iclass 19, count 0 2006.189.08:05:19.69#ibcon#read 6, iclass 19, count 0 2006.189.08:05:19.69#ibcon#end of sib2, iclass 19, count 0 2006.189.08:05:19.69#ibcon#*after write, iclass 19, count 0 2006.189.08:05:19.69#ibcon#*before return 0, iclass 19, count 0 2006.189.08:05:19.69#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:19.69#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:19.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:05:19.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:05:19.69$vc4f8/valo=6,772.99 2006.189.08:05:19.69#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.08:05:19.69#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.08:05:19.69#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:19.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:19.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:19.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:19.69#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:05:19.69#ibcon#first serial, iclass 21, count 0 2006.189.08:05:19.69#ibcon#enter sib2, iclass 21, count 0 2006.189.08:05:19.69#ibcon#flushed, iclass 21, count 0 2006.189.08:05:19.69#ibcon#about to write, iclass 21, count 0 2006.189.08:05:19.69#ibcon#wrote, iclass 21, count 0 2006.189.08:05:19.69#ibcon#about to read 3, iclass 21, count 0 2006.189.08:05:19.71#ibcon#read 3, iclass 21, count 0 2006.189.08:05:19.71#ibcon#about to read 4, iclass 21, count 0 2006.189.08:05:19.71#ibcon#read 4, iclass 21, count 0 2006.189.08:05:19.71#ibcon#about to read 5, iclass 21, count 0 2006.189.08:05:19.71#ibcon#read 5, iclass 21, count 0 2006.189.08:05:19.71#ibcon#about to read 6, iclass 21, count 0 2006.189.08:05:19.71#ibcon#read 6, iclass 21, count 0 2006.189.08:05:19.71#ibcon#end of sib2, iclass 21, count 0 2006.189.08:05:19.71#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:05:19.71#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:05:19.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:05:19.71#ibcon#*before write, iclass 21, count 0 2006.189.08:05:19.71#ibcon#enter sib2, iclass 21, count 0 2006.189.08:05:19.71#ibcon#flushed, iclass 21, count 0 2006.189.08:05:19.71#ibcon#about to write, iclass 21, count 0 2006.189.08:05:19.71#ibcon#wrote, iclass 21, count 0 2006.189.08:05:19.71#ibcon#about to read 3, iclass 21, count 0 2006.189.08:05:19.75#ibcon#read 3, iclass 21, count 0 2006.189.08:05:19.75#ibcon#about to read 4, iclass 21, count 0 2006.189.08:05:19.75#ibcon#read 4, iclass 21, count 0 2006.189.08:05:19.75#ibcon#about to read 5, iclass 21, count 0 2006.189.08:05:19.75#ibcon#read 5, iclass 21, count 0 2006.189.08:05:19.75#ibcon#about to read 6, iclass 21, count 0 2006.189.08:05:19.75#ibcon#read 6, iclass 21, count 0 2006.189.08:05:19.75#ibcon#end of sib2, iclass 21, count 0 2006.189.08:05:19.75#ibcon#*after write, iclass 21, count 0 2006.189.08:05:19.75#ibcon#*before return 0, iclass 21, count 0 2006.189.08:05:19.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:19.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:19.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:05:19.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:05:19.75$vc4f8/va=6,6 2006.189.08:05:19.75#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.08:05:19.75#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.08:05:19.75#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:19.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:05:19.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:05:19.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:05:19.81#ibcon#enter wrdev, iclass 23, count 2 2006.189.08:05:19.81#ibcon#first serial, iclass 23, count 2 2006.189.08:05:19.81#ibcon#enter sib2, iclass 23, count 2 2006.189.08:05:19.81#ibcon#flushed, iclass 23, count 2 2006.189.08:05:19.81#ibcon#about to write, iclass 23, count 2 2006.189.08:05:19.81#ibcon#wrote, iclass 23, count 2 2006.189.08:05:19.81#ibcon#about to read 3, iclass 23, count 2 2006.189.08:05:19.83#ibcon#read 3, iclass 23, count 2 2006.189.08:05:19.83#ibcon#about to read 4, iclass 23, count 2 2006.189.08:05:19.83#ibcon#read 4, iclass 23, count 2 2006.189.08:05:19.83#ibcon#about to read 5, iclass 23, count 2 2006.189.08:05:19.83#ibcon#read 5, iclass 23, count 2 2006.189.08:05:19.83#ibcon#about to read 6, iclass 23, count 2 2006.189.08:05:19.83#ibcon#read 6, iclass 23, count 2 2006.189.08:05:19.83#ibcon#end of sib2, iclass 23, count 2 2006.189.08:05:19.83#ibcon#*mode == 0, iclass 23, count 2 2006.189.08:05:19.83#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.08:05:19.83#ibcon#[25=AT06-06\r\n] 2006.189.08:05:19.83#ibcon#*before write, iclass 23, count 2 2006.189.08:05:19.83#ibcon#enter sib2, iclass 23, count 2 2006.189.08:05:19.83#ibcon#flushed, iclass 23, count 2 2006.189.08:05:19.83#ibcon#about to write, iclass 23, count 2 2006.189.08:05:19.83#ibcon#wrote, iclass 23, count 2 2006.189.08:05:19.83#ibcon#about to read 3, iclass 23, count 2 2006.189.08:05:19.86#ibcon#read 3, iclass 23, count 2 2006.189.08:05:19.86#ibcon#about to read 4, iclass 23, count 2 2006.189.08:05:19.86#ibcon#read 4, iclass 23, count 2 2006.189.08:05:19.86#ibcon#about to read 5, iclass 23, count 2 2006.189.08:05:19.86#ibcon#read 5, iclass 23, count 2 2006.189.08:05:19.86#ibcon#about to read 6, iclass 23, count 2 2006.189.08:05:19.86#ibcon#read 6, iclass 23, count 2 2006.189.08:05:19.86#ibcon#end of sib2, iclass 23, count 2 2006.189.08:05:19.86#ibcon#*after write, iclass 23, count 2 2006.189.08:05:19.86#ibcon#*before return 0, iclass 23, count 2 2006.189.08:05:19.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:05:19.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:05:19.86#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.08:05:19.86#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:19.86#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:05:19.98#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:05:19.98#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:05:19.98#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:05:19.98#ibcon#first serial, iclass 23, count 0 2006.189.08:05:19.98#ibcon#enter sib2, iclass 23, count 0 2006.189.08:05:19.98#ibcon#flushed, iclass 23, count 0 2006.189.08:05:19.98#ibcon#about to write, iclass 23, count 0 2006.189.08:05:19.98#ibcon#wrote, iclass 23, count 0 2006.189.08:05:19.98#ibcon#about to read 3, iclass 23, count 0 2006.189.08:05:20.00#ibcon#read 3, iclass 23, count 0 2006.189.08:05:20.00#ibcon#about to read 4, iclass 23, count 0 2006.189.08:05:20.00#ibcon#read 4, iclass 23, count 0 2006.189.08:05:20.00#ibcon#about to read 5, iclass 23, count 0 2006.189.08:05:20.00#ibcon#read 5, iclass 23, count 0 2006.189.08:05:20.00#ibcon#about to read 6, iclass 23, count 0 2006.189.08:05:20.00#ibcon#read 6, iclass 23, count 0 2006.189.08:05:20.00#ibcon#end of sib2, iclass 23, count 0 2006.189.08:05:20.00#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:05:20.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:05:20.00#ibcon#[25=USB\r\n] 2006.189.08:05:20.00#ibcon#*before write, iclass 23, count 0 2006.189.08:05:20.00#ibcon#enter sib2, iclass 23, count 0 2006.189.08:05:20.00#ibcon#flushed, iclass 23, count 0 2006.189.08:05:20.00#ibcon#about to write, iclass 23, count 0 2006.189.08:05:20.00#ibcon#wrote, iclass 23, count 0 2006.189.08:05:20.00#ibcon#about to read 3, iclass 23, count 0 2006.189.08:05:20.03#ibcon#read 3, iclass 23, count 0 2006.189.08:05:20.03#ibcon#about to read 4, iclass 23, count 0 2006.189.08:05:20.03#ibcon#read 4, iclass 23, count 0 2006.189.08:05:20.03#ibcon#about to read 5, iclass 23, count 0 2006.189.08:05:20.03#ibcon#read 5, iclass 23, count 0 2006.189.08:05:20.03#ibcon#about to read 6, iclass 23, count 0 2006.189.08:05:20.03#ibcon#read 6, iclass 23, count 0 2006.189.08:05:20.03#ibcon#end of sib2, iclass 23, count 0 2006.189.08:05:20.03#ibcon#*after write, iclass 23, count 0 2006.189.08:05:20.03#ibcon#*before return 0, iclass 23, count 0 2006.189.08:05:20.03#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:05:20.03#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:05:20.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:05:20.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:05:20.03$vc4f8/valo=7,832.99 2006.189.08:05:20.03#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.08:05:20.03#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.08:05:20.03#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:20.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:05:20.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:05:20.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:05:20.03#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:05:20.03#ibcon#first serial, iclass 25, count 0 2006.189.08:05:20.03#ibcon#enter sib2, iclass 25, count 0 2006.189.08:05:20.03#ibcon#flushed, iclass 25, count 0 2006.189.08:05:20.03#ibcon#about to write, iclass 25, count 0 2006.189.08:05:20.03#ibcon#wrote, iclass 25, count 0 2006.189.08:05:20.03#ibcon#about to read 3, iclass 25, count 0 2006.189.08:05:20.05#ibcon#read 3, iclass 25, count 0 2006.189.08:05:20.05#ibcon#about to read 4, iclass 25, count 0 2006.189.08:05:20.05#ibcon#read 4, iclass 25, count 0 2006.189.08:05:20.05#ibcon#about to read 5, iclass 25, count 0 2006.189.08:05:20.05#ibcon#read 5, iclass 25, count 0 2006.189.08:05:20.05#ibcon#about to read 6, iclass 25, count 0 2006.189.08:05:20.05#ibcon#read 6, iclass 25, count 0 2006.189.08:05:20.05#ibcon#end of sib2, iclass 25, count 0 2006.189.08:05:20.05#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:05:20.05#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:05:20.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:05:20.05#ibcon#*before write, iclass 25, count 0 2006.189.08:05:20.05#ibcon#enter sib2, iclass 25, count 0 2006.189.08:05:20.05#ibcon#flushed, iclass 25, count 0 2006.189.08:05:20.05#ibcon#about to write, iclass 25, count 0 2006.189.08:05:20.05#ibcon#wrote, iclass 25, count 0 2006.189.08:05:20.05#ibcon#about to read 3, iclass 25, count 0 2006.189.08:05:20.09#ibcon#read 3, iclass 25, count 0 2006.189.08:05:20.09#ibcon#about to read 4, iclass 25, count 0 2006.189.08:05:20.09#ibcon#read 4, iclass 25, count 0 2006.189.08:05:20.09#ibcon#about to read 5, iclass 25, count 0 2006.189.08:05:20.09#ibcon#read 5, iclass 25, count 0 2006.189.08:05:20.09#ibcon#about to read 6, iclass 25, count 0 2006.189.08:05:20.09#ibcon#read 6, iclass 25, count 0 2006.189.08:05:20.09#ibcon#end of sib2, iclass 25, count 0 2006.189.08:05:20.09#ibcon#*after write, iclass 25, count 0 2006.189.08:05:20.09#ibcon#*before return 0, iclass 25, count 0 2006.189.08:05:20.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:05:20.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:05:20.09#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:05:20.09#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:05:20.09$vc4f8/va=7,6 2006.189.08:05:20.09#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.08:05:20.09#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.08:05:20.09#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:20.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:05:20.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:05:20.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:05:20.15#ibcon#enter wrdev, iclass 27, count 2 2006.189.08:05:20.15#ibcon#first serial, iclass 27, count 2 2006.189.08:05:20.15#ibcon#enter sib2, iclass 27, count 2 2006.189.08:05:20.15#ibcon#flushed, iclass 27, count 2 2006.189.08:05:20.15#ibcon#about to write, iclass 27, count 2 2006.189.08:05:20.15#ibcon#wrote, iclass 27, count 2 2006.189.08:05:20.15#ibcon#about to read 3, iclass 27, count 2 2006.189.08:05:20.17#ibcon#read 3, iclass 27, count 2 2006.189.08:05:20.17#ibcon#about to read 4, iclass 27, count 2 2006.189.08:05:20.17#ibcon#read 4, iclass 27, count 2 2006.189.08:05:20.17#ibcon#about to read 5, iclass 27, count 2 2006.189.08:05:20.17#ibcon#read 5, iclass 27, count 2 2006.189.08:05:20.17#ibcon#about to read 6, iclass 27, count 2 2006.189.08:05:20.17#ibcon#read 6, iclass 27, count 2 2006.189.08:05:20.17#ibcon#end of sib2, iclass 27, count 2 2006.189.08:05:20.17#ibcon#*mode == 0, iclass 27, count 2 2006.189.08:05:20.17#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.08:05:20.17#ibcon#[25=AT07-06\r\n] 2006.189.08:05:20.17#ibcon#*before write, iclass 27, count 2 2006.189.08:05:20.17#ibcon#enter sib2, iclass 27, count 2 2006.189.08:05:20.17#ibcon#flushed, iclass 27, count 2 2006.189.08:05:20.17#ibcon#about to write, iclass 27, count 2 2006.189.08:05:20.17#ibcon#wrote, iclass 27, count 2 2006.189.08:05:20.17#ibcon#about to read 3, iclass 27, count 2 2006.189.08:05:20.20#ibcon#read 3, iclass 27, count 2 2006.189.08:05:20.20#ibcon#about to read 4, iclass 27, count 2 2006.189.08:05:20.20#ibcon#read 4, iclass 27, count 2 2006.189.08:05:20.20#ibcon#about to read 5, iclass 27, count 2 2006.189.08:05:20.20#ibcon#read 5, iclass 27, count 2 2006.189.08:05:20.20#ibcon#about to read 6, iclass 27, count 2 2006.189.08:05:20.20#ibcon#read 6, iclass 27, count 2 2006.189.08:05:20.20#ibcon#end of sib2, iclass 27, count 2 2006.189.08:05:20.20#ibcon#*after write, iclass 27, count 2 2006.189.08:05:20.20#ibcon#*before return 0, iclass 27, count 2 2006.189.08:05:20.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:05:20.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:05:20.20#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.08:05:20.20#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:20.20#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:05:20.32#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:05:20.32#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:05:20.32#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:05:20.32#ibcon#first serial, iclass 27, count 0 2006.189.08:05:20.32#ibcon#enter sib2, iclass 27, count 0 2006.189.08:05:20.32#ibcon#flushed, iclass 27, count 0 2006.189.08:05:20.32#ibcon#about to write, iclass 27, count 0 2006.189.08:05:20.32#ibcon#wrote, iclass 27, count 0 2006.189.08:05:20.32#ibcon#about to read 3, iclass 27, count 0 2006.189.08:05:20.34#ibcon#read 3, iclass 27, count 0 2006.189.08:05:20.34#ibcon#about to read 4, iclass 27, count 0 2006.189.08:05:20.34#ibcon#read 4, iclass 27, count 0 2006.189.08:05:20.34#ibcon#about to read 5, iclass 27, count 0 2006.189.08:05:20.34#ibcon#read 5, iclass 27, count 0 2006.189.08:05:20.34#ibcon#about to read 6, iclass 27, count 0 2006.189.08:05:20.34#ibcon#read 6, iclass 27, count 0 2006.189.08:05:20.34#ibcon#end of sib2, iclass 27, count 0 2006.189.08:05:20.34#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:05:20.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:05:20.34#ibcon#[25=USB\r\n] 2006.189.08:05:20.34#ibcon#*before write, iclass 27, count 0 2006.189.08:05:20.34#ibcon#enter sib2, iclass 27, count 0 2006.189.08:05:20.34#ibcon#flushed, iclass 27, count 0 2006.189.08:05:20.34#ibcon#about to write, iclass 27, count 0 2006.189.08:05:20.34#ibcon#wrote, iclass 27, count 0 2006.189.08:05:20.34#ibcon#about to read 3, iclass 27, count 0 2006.189.08:05:20.37#ibcon#read 3, iclass 27, count 0 2006.189.08:05:20.37#ibcon#about to read 4, iclass 27, count 0 2006.189.08:05:20.37#ibcon#read 4, iclass 27, count 0 2006.189.08:05:20.37#ibcon#about to read 5, iclass 27, count 0 2006.189.08:05:20.37#ibcon#read 5, iclass 27, count 0 2006.189.08:05:20.37#ibcon#about to read 6, iclass 27, count 0 2006.189.08:05:20.37#ibcon#read 6, iclass 27, count 0 2006.189.08:05:20.37#ibcon#end of sib2, iclass 27, count 0 2006.189.08:05:20.37#ibcon#*after write, iclass 27, count 0 2006.189.08:05:20.37#ibcon#*before return 0, iclass 27, count 0 2006.189.08:05:20.37#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:05:20.37#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:05:20.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:05:20.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:05:20.37$vc4f8/valo=8,852.99 2006.189.08:05:20.37#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.08:05:20.37#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.08:05:20.37#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:20.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:05:20.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:05:20.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:05:20.37#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:05:20.37#ibcon#first serial, iclass 29, count 0 2006.189.08:05:20.37#ibcon#enter sib2, iclass 29, count 0 2006.189.08:05:20.37#ibcon#flushed, iclass 29, count 0 2006.189.08:05:20.37#ibcon#about to write, iclass 29, count 0 2006.189.08:05:20.37#ibcon#wrote, iclass 29, count 0 2006.189.08:05:20.37#ibcon#about to read 3, iclass 29, count 0 2006.189.08:05:20.39#ibcon#read 3, iclass 29, count 0 2006.189.08:05:20.39#ibcon#about to read 4, iclass 29, count 0 2006.189.08:05:20.39#ibcon#read 4, iclass 29, count 0 2006.189.08:05:20.39#ibcon#about to read 5, iclass 29, count 0 2006.189.08:05:20.39#ibcon#read 5, iclass 29, count 0 2006.189.08:05:20.39#ibcon#about to read 6, iclass 29, count 0 2006.189.08:05:20.39#ibcon#read 6, iclass 29, count 0 2006.189.08:05:20.39#ibcon#end of sib2, iclass 29, count 0 2006.189.08:05:20.39#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:05:20.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:05:20.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:05:20.39#ibcon#*before write, iclass 29, count 0 2006.189.08:05:20.39#ibcon#enter sib2, iclass 29, count 0 2006.189.08:05:20.39#ibcon#flushed, iclass 29, count 0 2006.189.08:05:20.39#ibcon#about to write, iclass 29, count 0 2006.189.08:05:20.39#ibcon#wrote, iclass 29, count 0 2006.189.08:05:20.39#ibcon#about to read 3, iclass 29, count 0 2006.189.08:05:20.43#ibcon#read 3, iclass 29, count 0 2006.189.08:05:20.43#ibcon#about to read 4, iclass 29, count 0 2006.189.08:05:20.43#ibcon#read 4, iclass 29, count 0 2006.189.08:05:20.43#ibcon#about to read 5, iclass 29, count 0 2006.189.08:05:20.43#ibcon#read 5, iclass 29, count 0 2006.189.08:05:20.43#ibcon#about to read 6, iclass 29, count 0 2006.189.08:05:20.43#ibcon#read 6, iclass 29, count 0 2006.189.08:05:20.43#ibcon#end of sib2, iclass 29, count 0 2006.189.08:05:20.43#ibcon#*after write, iclass 29, count 0 2006.189.08:05:20.43#ibcon#*before return 0, iclass 29, count 0 2006.189.08:05:20.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:05:20.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:05:20.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:05:20.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:05:20.43$vc4f8/va=8,6 2006.189.08:05:20.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.08:05:20.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.08:05:20.43#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:20.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:05:20.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:05:20.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:05:20.49#ibcon#enter wrdev, iclass 31, count 2 2006.189.08:05:20.49#ibcon#first serial, iclass 31, count 2 2006.189.08:05:20.49#ibcon#enter sib2, iclass 31, count 2 2006.189.08:05:20.49#ibcon#flushed, iclass 31, count 2 2006.189.08:05:20.49#ibcon#about to write, iclass 31, count 2 2006.189.08:05:20.49#ibcon#wrote, iclass 31, count 2 2006.189.08:05:20.49#ibcon#about to read 3, iclass 31, count 2 2006.189.08:05:20.51#ibcon#read 3, iclass 31, count 2 2006.189.08:05:20.51#ibcon#about to read 4, iclass 31, count 2 2006.189.08:05:20.51#ibcon#read 4, iclass 31, count 2 2006.189.08:05:20.51#ibcon#about to read 5, iclass 31, count 2 2006.189.08:05:20.51#ibcon#read 5, iclass 31, count 2 2006.189.08:05:20.51#ibcon#about to read 6, iclass 31, count 2 2006.189.08:05:20.51#ibcon#read 6, iclass 31, count 2 2006.189.08:05:20.51#ibcon#end of sib2, iclass 31, count 2 2006.189.08:05:20.51#ibcon#*mode == 0, iclass 31, count 2 2006.189.08:05:20.51#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.08:05:20.51#ibcon#[25=AT08-06\r\n] 2006.189.08:05:20.51#ibcon#*before write, iclass 31, count 2 2006.189.08:05:20.51#ibcon#enter sib2, iclass 31, count 2 2006.189.08:05:20.51#ibcon#flushed, iclass 31, count 2 2006.189.08:05:20.51#ibcon#about to write, iclass 31, count 2 2006.189.08:05:20.51#ibcon#wrote, iclass 31, count 2 2006.189.08:05:20.51#ibcon#about to read 3, iclass 31, count 2 2006.189.08:05:20.54#ibcon#read 3, iclass 31, count 2 2006.189.08:05:20.54#ibcon#about to read 4, iclass 31, count 2 2006.189.08:05:20.54#ibcon#read 4, iclass 31, count 2 2006.189.08:05:20.54#ibcon#about to read 5, iclass 31, count 2 2006.189.08:05:20.54#ibcon#read 5, iclass 31, count 2 2006.189.08:05:20.54#ibcon#about to read 6, iclass 31, count 2 2006.189.08:05:20.54#ibcon#read 6, iclass 31, count 2 2006.189.08:05:20.54#ibcon#end of sib2, iclass 31, count 2 2006.189.08:05:20.54#ibcon#*after write, iclass 31, count 2 2006.189.08:05:20.54#ibcon#*before return 0, iclass 31, count 2 2006.189.08:05:20.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:05:20.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:05:20.54#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.08:05:20.54#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:20.54#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:05:20.66#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:05:20.66#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:05:20.66#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:05:20.66#ibcon#first serial, iclass 31, count 0 2006.189.08:05:20.66#ibcon#enter sib2, iclass 31, count 0 2006.189.08:05:20.66#ibcon#flushed, iclass 31, count 0 2006.189.08:05:20.66#ibcon#about to write, iclass 31, count 0 2006.189.08:05:20.66#ibcon#wrote, iclass 31, count 0 2006.189.08:05:20.66#ibcon#about to read 3, iclass 31, count 0 2006.189.08:05:20.68#ibcon#read 3, iclass 31, count 0 2006.189.08:05:20.68#ibcon#about to read 4, iclass 31, count 0 2006.189.08:05:20.68#ibcon#read 4, iclass 31, count 0 2006.189.08:05:20.68#ibcon#about to read 5, iclass 31, count 0 2006.189.08:05:20.68#ibcon#read 5, iclass 31, count 0 2006.189.08:05:20.68#ibcon#about to read 6, iclass 31, count 0 2006.189.08:05:20.68#ibcon#read 6, iclass 31, count 0 2006.189.08:05:20.68#ibcon#end of sib2, iclass 31, count 0 2006.189.08:05:20.68#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:05:20.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:05:20.68#ibcon#[25=USB\r\n] 2006.189.08:05:20.68#ibcon#*before write, iclass 31, count 0 2006.189.08:05:20.68#ibcon#enter sib2, iclass 31, count 0 2006.189.08:05:20.68#ibcon#flushed, iclass 31, count 0 2006.189.08:05:20.68#ibcon#about to write, iclass 31, count 0 2006.189.08:05:20.68#ibcon#wrote, iclass 31, count 0 2006.189.08:05:20.68#ibcon#about to read 3, iclass 31, count 0 2006.189.08:05:20.71#ibcon#read 3, iclass 31, count 0 2006.189.08:05:20.71#ibcon#about to read 4, iclass 31, count 0 2006.189.08:05:20.71#ibcon#read 4, iclass 31, count 0 2006.189.08:05:20.71#ibcon#about to read 5, iclass 31, count 0 2006.189.08:05:20.71#ibcon#read 5, iclass 31, count 0 2006.189.08:05:20.71#ibcon#about to read 6, iclass 31, count 0 2006.189.08:05:20.71#ibcon#read 6, iclass 31, count 0 2006.189.08:05:20.71#ibcon#end of sib2, iclass 31, count 0 2006.189.08:05:20.71#ibcon#*after write, iclass 31, count 0 2006.189.08:05:20.71#ibcon#*before return 0, iclass 31, count 0 2006.189.08:05:20.71#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:05:20.71#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:05:20.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:05:20.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:05:20.71$vc4f8/vblo=1,632.99 2006.189.08:05:20.71#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.08:05:20.71#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.08:05:20.71#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:20.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:05:20.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:05:20.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:05:20.71#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:05:20.71#ibcon#first serial, iclass 33, count 0 2006.189.08:05:20.71#ibcon#enter sib2, iclass 33, count 0 2006.189.08:05:20.71#ibcon#flushed, iclass 33, count 0 2006.189.08:05:20.71#ibcon#about to write, iclass 33, count 0 2006.189.08:05:20.71#ibcon#wrote, iclass 33, count 0 2006.189.08:05:20.71#ibcon#about to read 3, iclass 33, count 0 2006.189.08:05:20.73#ibcon#read 3, iclass 33, count 0 2006.189.08:05:20.73#ibcon#about to read 4, iclass 33, count 0 2006.189.08:05:20.73#ibcon#read 4, iclass 33, count 0 2006.189.08:05:20.73#ibcon#about to read 5, iclass 33, count 0 2006.189.08:05:20.73#ibcon#read 5, iclass 33, count 0 2006.189.08:05:20.73#ibcon#about to read 6, iclass 33, count 0 2006.189.08:05:20.73#ibcon#read 6, iclass 33, count 0 2006.189.08:05:20.73#ibcon#end of sib2, iclass 33, count 0 2006.189.08:05:20.73#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:05:20.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:05:20.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:05:20.73#ibcon#*before write, iclass 33, count 0 2006.189.08:05:20.73#ibcon#enter sib2, iclass 33, count 0 2006.189.08:05:20.73#ibcon#flushed, iclass 33, count 0 2006.189.08:05:20.73#ibcon#about to write, iclass 33, count 0 2006.189.08:05:20.73#ibcon#wrote, iclass 33, count 0 2006.189.08:05:20.73#ibcon#about to read 3, iclass 33, count 0 2006.189.08:05:20.77#ibcon#read 3, iclass 33, count 0 2006.189.08:05:20.77#ibcon#about to read 4, iclass 33, count 0 2006.189.08:05:20.77#ibcon#read 4, iclass 33, count 0 2006.189.08:05:20.77#ibcon#about to read 5, iclass 33, count 0 2006.189.08:05:20.77#ibcon#read 5, iclass 33, count 0 2006.189.08:05:20.77#ibcon#about to read 6, iclass 33, count 0 2006.189.08:05:20.77#ibcon#read 6, iclass 33, count 0 2006.189.08:05:20.77#ibcon#end of sib2, iclass 33, count 0 2006.189.08:05:20.77#ibcon#*after write, iclass 33, count 0 2006.189.08:05:20.77#ibcon#*before return 0, iclass 33, count 0 2006.189.08:05:20.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:05:20.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:05:20.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:05:20.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:05:20.77$vc4f8/vb=1,4 2006.189.08:05:20.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.08:05:20.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.08:05:20.77#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:20.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:05:20.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:05:20.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:05:20.77#ibcon#enter wrdev, iclass 35, count 2 2006.189.08:05:20.77#ibcon#first serial, iclass 35, count 2 2006.189.08:05:20.77#ibcon#enter sib2, iclass 35, count 2 2006.189.08:05:20.77#ibcon#flushed, iclass 35, count 2 2006.189.08:05:20.77#ibcon#about to write, iclass 35, count 2 2006.189.08:05:20.77#ibcon#wrote, iclass 35, count 2 2006.189.08:05:20.77#ibcon#about to read 3, iclass 35, count 2 2006.189.08:05:20.79#ibcon#read 3, iclass 35, count 2 2006.189.08:05:20.79#ibcon#about to read 4, iclass 35, count 2 2006.189.08:05:20.79#ibcon#read 4, iclass 35, count 2 2006.189.08:05:20.79#ibcon#about to read 5, iclass 35, count 2 2006.189.08:05:20.79#ibcon#read 5, iclass 35, count 2 2006.189.08:05:20.79#ibcon#about to read 6, iclass 35, count 2 2006.189.08:05:20.79#ibcon#read 6, iclass 35, count 2 2006.189.08:05:20.79#ibcon#end of sib2, iclass 35, count 2 2006.189.08:05:20.79#ibcon#*mode == 0, iclass 35, count 2 2006.189.08:05:20.79#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.08:05:20.79#ibcon#[27=AT01-04\r\n] 2006.189.08:05:20.79#ibcon#*before write, iclass 35, count 2 2006.189.08:05:20.79#ibcon#enter sib2, iclass 35, count 2 2006.189.08:05:20.79#ibcon#flushed, iclass 35, count 2 2006.189.08:05:20.79#ibcon#about to write, iclass 35, count 2 2006.189.08:05:20.79#ibcon#wrote, iclass 35, count 2 2006.189.08:05:20.79#ibcon#about to read 3, iclass 35, count 2 2006.189.08:05:20.82#ibcon#read 3, iclass 35, count 2 2006.189.08:05:20.82#ibcon#about to read 4, iclass 35, count 2 2006.189.08:05:20.82#ibcon#read 4, iclass 35, count 2 2006.189.08:05:20.82#ibcon#about to read 5, iclass 35, count 2 2006.189.08:05:20.82#ibcon#read 5, iclass 35, count 2 2006.189.08:05:20.82#ibcon#about to read 6, iclass 35, count 2 2006.189.08:05:20.82#ibcon#read 6, iclass 35, count 2 2006.189.08:05:20.82#ibcon#end of sib2, iclass 35, count 2 2006.189.08:05:20.82#ibcon#*after write, iclass 35, count 2 2006.189.08:05:20.82#ibcon#*before return 0, iclass 35, count 2 2006.189.08:05:20.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:05:20.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:05:20.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.08:05:20.82#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:20.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:05:20.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:05:20.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:05:20.94#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:05:20.94#ibcon#first serial, iclass 35, count 0 2006.189.08:05:20.94#ibcon#enter sib2, iclass 35, count 0 2006.189.08:05:20.94#ibcon#flushed, iclass 35, count 0 2006.189.08:05:20.94#ibcon#about to write, iclass 35, count 0 2006.189.08:05:20.94#ibcon#wrote, iclass 35, count 0 2006.189.08:05:20.94#ibcon#about to read 3, iclass 35, count 0 2006.189.08:05:20.96#ibcon#read 3, iclass 35, count 0 2006.189.08:05:20.96#ibcon#about to read 4, iclass 35, count 0 2006.189.08:05:20.96#ibcon#read 4, iclass 35, count 0 2006.189.08:05:20.96#ibcon#about to read 5, iclass 35, count 0 2006.189.08:05:20.96#ibcon#read 5, iclass 35, count 0 2006.189.08:05:20.96#ibcon#about to read 6, iclass 35, count 0 2006.189.08:05:20.96#ibcon#read 6, iclass 35, count 0 2006.189.08:05:20.96#ibcon#end of sib2, iclass 35, count 0 2006.189.08:05:20.96#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:05:20.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:05:20.96#ibcon#[27=USB\r\n] 2006.189.08:05:20.96#ibcon#*before write, iclass 35, count 0 2006.189.08:05:20.96#ibcon#enter sib2, iclass 35, count 0 2006.189.08:05:20.96#ibcon#flushed, iclass 35, count 0 2006.189.08:05:20.96#ibcon#about to write, iclass 35, count 0 2006.189.08:05:20.96#ibcon#wrote, iclass 35, count 0 2006.189.08:05:20.96#ibcon#about to read 3, iclass 35, count 0 2006.189.08:05:20.99#ibcon#read 3, iclass 35, count 0 2006.189.08:05:20.99#ibcon#about to read 4, iclass 35, count 0 2006.189.08:05:20.99#ibcon#read 4, iclass 35, count 0 2006.189.08:05:20.99#ibcon#about to read 5, iclass 35, count 0 2006.189.08:05:20.99#ibcon#read 5, iclass 35, count 0 2006.189.08:05:20.99#ibcon#about to read 6, iclass 35, count 0 2006.189.08:05:20.99#ibcon#read 6, iclass 35, count 0 2006.189.08:05:20.99#ibcon#end of sib2, iclass 35, count 0 2006.189.08:05:20.99#ibcon#*after write, iclass 35, count 0 2006.189.08:05:20.99#ibcon#*before return 0, iclass 35, count 0 2006.189.08:05:20.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:05:20.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:05:20.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:05:20.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:05:20.99$vc4f8/vblo=2,640.99 2006.189.08:05:20.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.08:05:20.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.08:05:20.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:20.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:20.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:20.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:20.99#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:05:20.99#ibcon#first serial, iclass 37, count 0 2006.189.08:05:20.99#ibcon#enter sib2, iclass 37, count 0 2006.189.08:05:20.99#ibcon#flushed, iclass 37, count 0 2006.189.08:05:20.99#ibcon#about to write, iclass 37, count 0 2006.189.08:05:20.99#ibcon#wrote, iclass 37, count 0 2006.189.08:05:20.99#ibcon#about to read 3, iclass 37, count 0 2006.189.08:05:21.01#ibcon#read 3, iclass 37, count 0 2006.189.08:05:21.01#ibcon#about to read 4, iclass 37, count 0 2006.189.08:05:21.01#ibcon#read 4, iclass 37, count 0 2006.189.08:05:21.01#ibcon#about to read 5, iclass 37, count 0 2006.189.08:05:21.01#ibcon#read 5, iclass 37, count 0 2006.189.08:05:21.01#ibcon#about to read 6, iclass 37, count 0 2006.189.08:05:21.01#ibcon#read 6, iclass 37, count 0 2006.189.08:05:21.01#ibcon#end of sib2, iclass 37, count 0 2006.189.08:05:21.01#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:05:21.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:05:21.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:05:21.01#ibcon#*before write, iclass 37, count 0 2006.189.08:05:21.01#ibcon#enter sib2, iclass 37, count 0 2006.189.08:05:21.01#ibcon#flushed, iclass 37, count 0 2006.189.08:05:21.01#ibcon#about to write, iclass 37, count 0 2006.189.08:05:21.01#ibcon#wrote, iclass 37, count 0 2006.189.08:05:21.01#ibcon#about to read 3, iclass 37, count 0 2006.189.08:05:21.05#ibcon#read 3, iclass 37, count 0 2006.189.08:05:21.05#ibcon#about to read 4, iclass 37, count 0 2006.189.08:05:21.05#ibcon#read 4, iclass 37, count 0 2006.189.08:05:21.05#ibcon#about to read 5, iclass 37, count 0 2006.189.08:05:21.05#ibcon#read 5, iclass 37, count 0 2006.189.08:05:21.05#ibcon#about to read 6, iclass 37, count 0 2006.189.08:05:21.05#ibcon#read 6, iclass 37, count 0 2006.189.08:05:21.05#ibcon#end of sib2, iclass 37, count 0 2006.189.08:05:21.05#ibcon#*after write, iclass 37, count 0 2006.189.08:05:21.05#ibcon#*before return 0, iclass 37, count 0 2006.189.08:05:21.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:21.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:05:21.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:05:21.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:05:21.05$vc4f8/vb=2,4 2006.189.08:05:21.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.08:05:21.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.08:05:21.05#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:21.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:21.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:21.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:21.11#ibcon#enter wrdev, iclass 39, count 2 2006.189.08:05:21.11#ibcon#first serial, iclass 39, count 2 2006.189.08:05:21.11#ibcon#enter sib2, iclass 39, count 2 2006.189.08:05:21.11#ibcon#flushed, iclass 39, count 2 2006.189.08:05:21.11#ibcon#about to write, iclass 39, count 2 2006.189.08:05:21.11#ibcon#wrote, iclass 39, count 2 2006.189.08:05:21.11#ibcon#about to read 3, iclass 39, count 2 2006.189.08:05:21.13#ibcon#read 3, iclass 39, count 2 2006.189.08:05:21.13#ibcon#about to read 4, iclass 39, count 2 2006.189.08:05:21.13#ibcon#read 4, iclass 39, count 2 2006.189.08:05:21.13#ibcon#about to read 5, iclass 39, count 2 2006.189.08:05:21.13#ibcon#read 5, iclass 39, count 2 2006.189.08:05:21.13#ibcon#about to read 6, iclass 39, count 2 2006.189.08:05:21.13#ibcon#read 6, iclass 39, count 2 2006.189.08:05:21.13#ibcon#end of sib2, iclass 39, count 2 2006.189.08:05:21.13#ibcon#*mode == 0, iclass 39, count 2 2006.189.08:05:21.13#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.08:05:21.13#ibcon#[27=AT02-04\r\n] 2006.189.08:05:21.13#ibcon#*before write, iclass 39, count 2 2006.189.08:05:21.13#ibcon#enter sib2, iclass 39, count 2 2006.189.08:05:21.13#ibcon#flushed, iclass 39, count 2 2006.189.08:05:21.13#ibcon#about to write, iclass 39, count 2 2006.189.08:05:21.13#ibcon#wrote, iclass 39, count 2 2006.189.08:05:21.13#ibcon#about to read 3, iclass 39, count 2 2006.189.08:05:21.16#ibcon#read 3, iclass 39, count 2 2006.189.08:05:21.16#ibcon#about to read 4, iclass 39, count 2 2006.189.08:05:21.16#ibcon#read 4, iclass 39, count 2 2006.189.08:05:21.16#ibcon#about to read 5, iclass 39, count 2 2006.189.08:05:21.16#ibcon#read 5, iclass 39, count 2 2006.189.08:05:21.16#ibcon#about to read 6, iclass 39, count 2 2006.189.08:05:21.16#ibcon#read 6, iclass 39, count 2 2006.189.08:05:21.16#ibcon#end of sib2, iclass 39, count 2 2006.189.08:05:21.16#ibcon#*after write, iclass 39, count 2 2006.189.08:05:21.16#ibcon#*before return 0, iclass 39, count 2 2006.189.08:05:21.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:21.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:05:21.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.08:05:21.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:21.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:21.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:21.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:21.28#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:05:21.28#ibcon#first serial, iclass 39, count 0 2006.189.08:05:21.28#ibcon#enter sib2, iclass 39, count 0 2006.189.08:05:21.28#ibcon#flushed, iclass 39, count 0 2006.189.08:05:21.28#ibcon#about to write, iclass 39, count 0 2006.189.08:05:21.28#ibcon#wrote, iclass 39, count 0 2006.189.08:05:21.28#ibcon#about to read 3, iclass 39, count 0 2006.189.08:05:21.30#ibcon#read 3, iclass 39, count 0 2006.189.08:05:21.30#ibcon#about to read 4, iclass 39, count 0 2006.189.08:05:21.30#ibcon#read 4, iclass 39, count 0 2006.189.08:05:21.30#ibcon#about to read 5, iclass 39, count 0 2006.189.08:05:21.30#ibcon#read 5, iclass 39, count 0 2006.189.08:05:21.30#ibcon#about to read 6, iclass 39, count 0 2006.189.08:05:21.30#ibcon#read 6, iclass 39, count 0 2006.189.08:05:21.30#ibcon#end of sib2, iclass 39, count 0 2006.189.08:05:21.30#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:05:21.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:05:21.30#ibcon#[27=USB\r\n] 2006.189.08:05:21.30#ibcon#*before write, iclass 39, count 0 2006.189.08:05:21.30#ibcon#enter sib2, iclass 39, count 0 2006.189.08:05:21.30#ibcon#flushed, iclass 39, count 0 2006.189.08:05:21.30#ibcon#about to write, iclass 39, count 0 2006.189.08:05:21.30#ibcon#wrote, iclass 39, count 0 2006.189.08:05:21.30#ibcon#about to read 3, iclass 39, count 0 2006.189.08:05:21.33#ibcon#read 3, iclass 39, count 0 2006.189.08:05:21.33#ibcon#about to read 4, iclass 39, count 0 2006.189.08:05:21.33#ibcon#read 4, iclass 39, count 0 2006.189.08:05:21.33#ibcon#about to read 5, iclass 39, count 0 2006.189.08:05:21.33#ibcon#read 5, iclass 39, count 0 2006.189.08:05:21.33#ibcon#about to read 6, iclass 39, count 0 2006.189.08:05:21.33#ibcon#read 6, iclass 39, count 0 2006.189.08:05:21.33#ibcon#end of sib2, iclass 39, count 0 2006.189.08:05:21.33#ibcon#*after write, iclass 39, count 0 2006.189.08:05:21.33#ibcon#*before return 0, iclass 39, count 0 2006.189.08:05:21.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:21.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:05:21.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:05:21.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:05:21.33$vc4f8/vblo=3,656.99 2006.189.08:05:21.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.08:05:21.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.08:05:21.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:21.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:21.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:21.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:21.33#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:05:21.33#ibcon#first serial, iclass 3, count 0 2006.189.08:05:21.33#ibcon#enter sib2, iclass 3, count 0 2006.189.08:05:21.33#ibcon#flushed, iclass 3, count 0 2006.189.08:05:21.33#ibcon#about to write, iclass 3, count 0 2006.189.08:05:21.33#ibcon#wrote, iclass 3, count 0 2006.189.08:05:21.33#ibcon#about to read 3, iclass 3, count 0 2006.189.08:05:21.35#ibcon#read 3, iclass 3, count 0 2006.189.08:05:21.35#ibcon#about to read 4, iclass 3, count 0 2006.189.08:05:21.35#ibcon#read 4, iclass 3, count 0 2006.189.08:05:21.35#ibcon#about to read 5, iclass 3, count 0 2006.189.08:05:21.35#ibcon#read 5, iclass 3, count 0 2006.189.08:05:21.35#ibcon#about to read 6, iclass 3, count 0 2006.189.08:05:21.35#ibcon#read 6, iclass 3, count 0 2006.189.08:05:21.35#ibcon#end of sib2, iclass 3, count 0 2006.189.08:05:21.35#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:05:21.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:05:21.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:05:21.35#ibcon#*before write, iclass 3, count 0 2006.189.08:05:21.35#ibcon#enter sib2, iclass 3, count 0 2006.189.08:05:21.35#ibcon#flushed, iclass 3, count 0 2006.189.08:05:21.35#ibcon#about to write, iclass 3, count 0 2006.189.08:05:21.35#ibcon#wrote, iclass 3, count 0 2006.189.08:05:21.35#ibcon#about to read 3, iclass 3, count 0 2006.189.08:05:21.39#ibcon#read 3, iclass 3, count 0 2006.189.08:05:21.39#ibcon#about to read 4, iclass 3, count 0 2006.189.08:05:21.39#ibcon#read 4, iclass 3, count 0 2006.189.08:05:21.39#ibcon#about to read 5, iclass 3, count 0 2006.189.08:05:21.39#ibcon#read 5, iclass 3, count 0 2006.189.08:05:21.39#ibcon#about to read 6, iclass 3, count 0 2006.189.08:05:21.39#ibcon#read 6, iclass 3, count 0 2006.189.08:05:21.39#ibcon#end of sib2, iclass 3, count 0 2006.189.08:05:21.39#ibcon#*after write, iclass 3, count 0 2006.189.08:05:21.39#ibcon#*before return 0, iclass 3, count 0 2006.189.08:05:21.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:21.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:05:21.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:05:21.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:05:21.39$vc4f8/vb=3,4 2006.189.08:05:21.39#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.08:05:21.39#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.08:05:21.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:21.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:21.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:21.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:21.45#ibcon#enter wrdev, iclass 5, count 2 2006.189.08:05:21.45#ibcon#first serial, iclass 5, count 2 2006.189.08:05:21.45#ibcon#enter sib2, iclass 5, count 2 2006.189.08:05:21.45#ibcon#flushed, iclass 5, count 2 2006.189.08:05:21.45#ibcon#about to write, iclass 5, count 2 2006.189.08:05:21.45#ibcon#wrote, iclass 5, count 2 2006.189.08:05:21.45#ibcon#about to read 3, iclass 5, count 2 2006.189.08:05:21.47#ibcon#read 3, iclass 5, count 2 2006.189.08:05:21.47#ibcon#about to read 4, iclass 5, count 2 2006.189.08:05:21.47#ibcon#read 4, iclass 5, count 2 2006.189.08:05:21.47#ibcon#about to read 5, iclass 5, count 2 2006.189.08:05:21.47#ibcon#read 5, iclass 5, count 2 2006.189.08:05:21.47#ibcon#about to read 6, iclass 5, count 2 2006.189.08:05:21.47#ibcon#read 6, iclass 5, count 2 2006.189.08:05:21.47#ibcon#end of sib2, iclass 5, count 2 2006.189.08:05:21.47#ibcon#*mode == 0, iclass 5, count 2 2006.189.08:05:21.47#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.08:05:21.47#ibcon#[27=AT03-04\r\n] 2006.189.08:05:21.47#ibcon#*before write, iclass 5, count 2 2006.189.08:05:21.47#ibcon#enter sib2, iclass 5, count 2 2006.189.08:05:21.47#ibcon#flushed, iclass 5, count 2 2006.189.08:05:21.47#ibcon#about to write, iclass 5, count 2 2006.189.08:05:21.47#ibcon#wrote, iclass 5, count 2 2006.189.08:05:21.47#ibcon#about to read 3, iclass 5, count 2 2006.189.08:05:21.50#ibcon#read 3, iclass 5, count 2 2006.189.08:05:21.50#ibcon#about to read 4, iclass 5, count 2 2006.189.08:05:21.50#ibcon#read 4, iclass 5, count 2 2006.189.08:05:21.50#ibcon#about to read 5, iclass 5, count 2 2006.189.08:05:21.50#ibcon#read 5, iclass 5, count 2 2006.189.08:05:21.50#ibcon#about to read 6, iclass 5, count 2 2006.189.08:05:21.50#ibcon#read 6, iclass 5, count 2 2006.189.08:05:21.50#ibcon#end of sib2, iclass 5, count 2 2006.189.08:05:21.50#ibcon#*after write, iclass 5, count 2 2006.189.08:05:21.50#ibcon#*before return 0, iclass 5, count 2 2006.189.08:05:21.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:21.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:05:21.50#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.08:05:21.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:21.50#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:21.62#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:21.62#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:21.62#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:05:21.62#ibcon#first serial, iclass 5, count 0 2006.189.08:05:21.62#ibcon#enter sib2, iclass 5, count 0 2006.189.08:05:21.62#ibcon#flushed, iclass 5, count 0 2006.189.08:05:21.62#ibcon#about to write, iclass 5, count 0 2006.189.08:05:21.62#ibcon#wrote, iclass 5, count 0 2006.189.08:05:21.62#ibcon#about to read 3, iclass 5, count 0 2006.189.08:05:21.64#ibcon#read 3, iclass 5, count 0 2006.189.08:05:21.64#ibcon#about to read 4, iclass 5, count 0 2006.189.08:05:21.64#ibcon#read 4, iclass 5, count 0 2006.189.08:05:21.64#ibcon#about to read 5, iclass 5, count 0 2006.189.08:05:21.64#ibcon#read 5, iclass 5, count 0 2006.189.08:05:21.64#ibcon#about to read 6, iclass 5, count 0 2006.189.08:05:21.64#ibcon#read 6, iclass 5, count 0 2006.189.08:05:21.64#ibcon#end of sib2, iclass 5, count 0 2006.189.08:05:21.64#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:05:21.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:05:21.64#ibcon#[27=USB\r\n] 2006.189.08:05:21.64#ibcon#*before write, iclass 5, count 0 2006.189.08:05:21.64#ibcon#enter sib2, iclass 5, count 0 2006.189.08:05:21.64#ibcon#flushed, iclass 5, count 0 2006.189.08:05:21.64#ibcon#about to write, iclass 5, count 0 2006.189.08:05:21.64#ibcon#wrote, iclass 5, count 0 2006.189.08:05:21.64#ibcon#about to read 3, iclass 5, count 0 2006.189.08:05:21.67#ibcon#read 3, iclass 5, count 0 2006.189.08:05:21.67#ibcon#about to read 4, iclass 5, count 0 2006.189.08:05:21.67#ibcon#read 4, iclass 5, count 0 2006.189.08:05:21.67#ibcon#about to read 5, iclass 5, count 0 2006.189.08:05:21.67#ibcon#read 5, iclass 5, count 0 2006.189.08:05:21.67#ibcon#about to read 6, iclass 5, count 0 2006.189.08:05:21.67#ibcon#read 6, iclass 5, count 0 2006.189.08:05:21.67#ibcon#end of sib2, iclass 5, count 0 2006.189.08:05:21.67#ibcon#*after write, iclass 5, count 0 2006.189.08:05:21.67#ibcon#*before return 0, iclass 5, count 0 2006.189.08:05:21.67#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:21.67#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:05:21.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:05:21.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:05:21.67$vc4f8/vblo=4,712.99 2006.189.08:05:21.67#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.08:05:21.67#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.08:05:21.67#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:21.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:21.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:21.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:21.67#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:05:21.67#ibcon#first serial, iclass 7, count 0 2006.189.08:05:21.67#ibcon#enter sib2, iclass 7, count 0 2006.189.08:05:21.67#ibcon#flushed, iclass 7, count 0 2006.189.08:05:21.67#ibcon#about to write, iclass 7, count 0 2006.189.08:05:21.67#ibcon#wrote, iclass 7, count 0 2006.189.08:05:21.67#ibcon#about to read 3, iclass 7, count 0 2006.189.08:05:21.69#ibcon#read 3, iclass 7, count 0 2006.189.08:05:21.69#ibcon#about to read 4, iclass 7, count 0 2006.189.08:05:21.69#ibcon#read 4, iclass 7, count 0 2006.189.08:05:21.69#ibcon#about to read 5, iclass 7, count 0 2006.189.08:05:21.69#ibcon#read 5, iclass 7, count 0 2006.189.08:05:21.69#ibcon#about to read 6, iclass 7, count 0 2006.189.08:05:21.69#ibcon#read 6, iclass 7, count 0 2006.189.08:05:21.69#ibcon#end of sib2, iclass 7, count 0 2006.189.08:05:21.69#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:05:21.69#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:05:21.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:05:21.69#ibcon#*before write, iclass 7, count 0 2006.189.08:05:21.69#ibcon#enter sib2, iclass 7, count 0 2006.189.08:05:21.69#ibcon#flushed, iclass 7, count 0 2006.189.08:05:21.69#ibcon#about to write, iclass 7, count 0 2006.189.08:05:21.69#ibcon#wrote, iclass 7, count 0 2006.189.08:05:21.69#ibcon#about to read 3, iclass 7, count 0 2006.189.08:05:21.73#ibcon#read 3, iclass 7, count 0 2006.189.08:05:21.73#ibcon#about to read 4, iclass 7, count 0 2006.189.08:05:21.73#ibcon#read 4, iclass 7, count 0 2006.189.08:05:21.73#ibcon#about to read 5, iclass 7, count 0 2006.189.08:05:21.73#ibcon#read 5, iclass 7, count 0 2006.189.08:05:21.73#ibcon#about to read 6, iclass 7, count 0 2006.189.08:05:21.73#ibcon#read 6, iclass 7, count 0 2006.189.08:05:21.73#ibcon#end of sib2, iclass 7, count 0 2006.189.08:05:21.73#ibcon#*after write, iclass 7, count 0 2006.189.08:05:21.73#ibcon#*before return 0, iclass 7, count 0 2006.189.08:05:21.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:21.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:05:21.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:05:21.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:05:21.73$vc4f8/vb=4,4 2006.189.08:05:21.73#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.08:05:21.73#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.08:05:21.73#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:21.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:21.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:21.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:21.79#ibcon#enter wrdev, iclass 11, count 2 2006.189.08:05:21.79#ibcon#first serial, iclass 11, count 2 2006.189.08:05:21.79#ibcon#enter sib2, iclass 11, count 2 2006.189.08:05:21.79#ibcon#flushed, iclass 11, count 2 2006.189.08:05:21.79#ibcon#about to write, iclass 11, count 2 2006.189.08:05:21.79#ibcon#wrote, iclass 11, count 2 2006.189.08:05:21.79#ibcon#about to read 3, iclass 11, count 2 2006.189.08:05:21.81#ibcon#read 3, iclass 11, count 2 2006.189.08:05:21.81#ibcon#about to read 4, iclass 11, count 2 2006.189.08:05:21.81#ibcon#read 4, iclass 11, count 2 2006.189.08:05:21.81#ibcon#about to read 5, iclass 11, count 2 2006.189.08:05:21.81#ibcon#read 5, iclass 11, count 2 2006.189.08:05:21.81#ibcon#about to read 6, iclass 11, count 2 2006.189.08:05:21.81#ibcon#read 6, iclass 11, count 2 2006.189.08:05:21.81#ibcon#end of sib2, iclass 11, count 2 2006.189.08:05:21.81#ibcon#*mode == 0, iclass 11, count 2 2006.189.08:05:21.81#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.08:05:21.81#ibcon#[27=AT04-04\r\n] 2006.189.08:05:21.81#ibcon#*before write, iclass 11, count 2 2006.189.08:05:21.81#ibcon#enter sib2, iclass 11, count 2 2006.189.08:05:21.81#ibcon#flushed, iclass 11, count 2 2006.189.08:05:21.81#ibcon#about to write, iclass 11, count 2 2006.189.08:05:21.81#ibcon#wrote, iclass 11, count 2 2006.189.08:05:21.81#ibcon#about to read 3, iclass 11, count 2 2006.189.08:05:21.84#ibcon#read 3, iclass 11, count 2 2006.189.08:05:21.84#ibcon#about to read 4, iclass 11, count 2 2006.189.08:05:21.84#ibcon#read 4, iclass 11, count 2 2006.189.08:05:21.84#ibcon#about to read 5, iclass 11, count 2 2006.189.08:05:21.84#ibcon#read 5, iclass 11, count 2 2006.189.08:05:21.84#ibcon#about to read 6, iclass 11, count 2 2006.189.08:05:21.84#ibcon#read 6, iclass 11, count 2 2006.189.08:05:21.84#ibcon#end of sib2, iclass 11, count 2 2006.189.08:05:21.84#ibcon#*after write, iclass 11, count 2 2006.189.08:05:21.84#ibcon#*before return 0, iclass 11, count 2 2006.189.08:05:21.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:21.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:05:21.84#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.08:05:21.84#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:21.84#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:21.96#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:21.96#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:21.96#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:05:21.96#ibcon#first serial, iclass 11, count 0 2006.189.08:05:21.96#ibcon#enter sib2, iclass 11, count 0 2006.189.08:05:21.96#ibcon#flushed, iclass 11, count 0 2006.189.08:05:21.96#ibcon#about to write, iclass 11, count 0 2006.189.08:05:21.96#ibcon#wrote, iclass 11, count 0 2006.189.08:05:21.96#ibcon#about to read 3, iclass 11, count 0 2006.189.08:05:21.98#ibcon#read 3, iclass 11, count 0 2006.189.08:05:21.98#ibcon#about to read 4, iclass 11, count 0 2006.189.08:05:21.98#ibcon#read 4, iclass 11, count 0 2006.189.08:05:21.98#ibcon#about to read 5, iclass 11, count 0 2006.189.08:05:21.98#ibcon#read 5, iclass 11, count 0 2006.189.08:05:21.98#ibcon#about to read 6, iclass 11, count 0 2006.189.08:05:21.98#ibcon#read 6, iclass 11, count 0 2006.189.08:05:21.98#ibcon#end of sib2, iclass 11, count 0 2006.189.08:05:21.98#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:05:21.98#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:05:21.98#ibcon#[27=USB\r\n] 2006.189.08:05:21.98#ibcon#*before write, iclass 11, count 0 2006.189.08:05:21.98#ibcon#enter sib2, iclass 11, count 0 2006.189.08:05:21.98#ibcon#flushed, iclass 11, count 0 2006.189.08:05:21.98#ibcon#about to write, iclass 11, count 0 2006.189.08:05:21.98#ibcon#wrote, iclass 11, count 0 2006.189.08:05:21.98#ibcon#about to read 3, iclass 11, count 0 2006.189.08:05:22.01#ibcon#read 3, iclass 11, count 0 2006.189.08:05:22.01#ibcon#about to read 4, iclass 11, count 0 2006.189.08:05:22.01#ibcon#read 4, iclass 11, count 0 2006.189.08:05:22.01#ibcon#about to read 5, iclass 11, count 0 2006.189.08:05:22.01#ibcon#read 5, iclass 11, count 0 2006.189.08:05:22.01#ibcon#about to read 6, iclass 11, count 0 2006.189.08:05:22.01#ibcon#read 6, iclass 11, count 0 2006.189.08:05:22.01#ibcon#end of sib2, iclass 11, count 0 2006.189.08:05:22.01#ibcon#*after write, iclass 11, count 0 2006.189.08:05:22.01#ibcon#*before return 0, iclass 11, count 0 2006.189.08:05:22.01#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:22.01#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:05:22.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:05:22.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:05:22.01$vc4f8/vblo=5,744.99 2006.189.08:05:22.01#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.08:05:22.01#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.08:05:22.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:22.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:22.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:22.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:22.01#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:05:22.01#ibcon#first serial, iclass 13, count 0 2006.189.08:05:22.01#ibcon#enter sib2, iclass 13, count 0 2006.189.08:05:22.01#ibcon#flushed, iclass 13, count 0 2006.189.08:05:22.01#ibcon#about to write, iclass 13, count 0 2006.189.08:05:22.01#ibcon#wrote, iclass 13, count 0 2006.189.08:05:22.01#ibcon#about to read 3, iclass 13, count 0 2006.189.08:05:22.03#ibcon#read 3, iclass 13, count 0 2006.189.08:05:22.03#ibcon#about to read 4, iclass 13, count 0 2006.189.08:05:22.03#ibcon#read 4, iclass 13, count 0 2006.189.08:05:22.03#ibcon#about to read 5, iclass 13, count 0 2006.189.08:05:22.03#ibcon#read 5, iclass 13, count 0 2006.189.08:05:22.03#ibcon#about to read 6, iclass 13, count 0 2006.189.08:05:22.03#ibcon#read 6, iclass 13, count 0 2006.189.08:05:22.03#ibcon#end of sib2, iclass 13, count 0 2006.189.08:05:22.03#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:05:22.03#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:05:22.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:05:22.03#ibcon#*before write, iclass 13, count 0 2006.189.08:05:22.03#ibcon#enter sib2, iclass 13, count 0 2006.189.08:05:22.03#ibcon#flushed, iclass 13, count 0 2006.189.08:05:22.03#ibcon#about to write, iclass 13, count 0 2006.189.08:05:22.03#ibcon#wrote, iclass 13, count 0 2006.189.08:05:22.03#ibcon#about to read 3, iclass 13, count 0 2006.189.08:05:22.07#ibcon#read 3, iclass 13, count 0 2006.189.08:05:22.07#ibcon#about to read 4, iclass 13, count 0 2006.189.08:05:22.07#ibcon#read 4, iclass 13, count 0 2006.189.08:05:22.07#ibcon#about to read 5, iclass 13, count 0 2006.189.08:05:22.07#ibcon#read 5, iclass 13, count 0 2006.189.08:05:22.07#ibcon#about to read 6, iclass 13, count 0 2006.189.08:05:22.07#ibcon#read 6, iclass 13, count 0 2006.189.08:05:22.07#ibcon#end of sib2, iclass 13, count 0 2006.189.08:05:22.07#ibcon#*after write, iclass 13, count 0 2006.189.08:05:22.07#ibcon#*before return 0, iclass 13, count 0 2006.189.08:05:22.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:22.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:05:22.07#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:05:22.07#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:05:22.07$vc4f8/vb=5,4 2006.189.08:05:22.07#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.08:05:22.07#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.08:05:22.07#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:22.07#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:22.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:22.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:22.13#ibcon#enter wrdev, iclass 15, count 2 2006.189.08:05:22.13#ibcon#first serial, iclass 15, count 2 2006.189.08:05:22.13#ibcon#enter sib2, iclass 15, count 2 2006.189.08:05:22.13#ibcon#flushed, iclass 15, count 2 2006.189.08:05:22.13#ibcon#about to write, iclass 15, count 2 2006.189.08:05:22.13#ibcon#wrote, iclass 15, count 2 2006.189.08:05:22.13#ibcon#about to read 3, iclass 15, count 2 2006.189.08:05:22.15#ibcon#read 3, iclass 15, count 2 2006.189.08:05:22.15#ibcon#about to read 4, iclass 15, count 2 2006.189.08:05:22.15#ibcon#read 4, iclass 15, count 2 2006.189.08:05:22.15#ibcon#about to read 5, iclass 15, count 2 2006.189.08:05:22.15#ibcon#read 5, iclass 15, count 2 2006.189.08:05:22.15#ibcon#about to read 6, iclass 15, count 2 2006.189.08:05:22.15#ibcon#read 6, iclass 15, count 2 2006.189.08:05:22.15#ibcon#end of sib2, iclass 15, count 2 2006.189.08:05:22.15#ibcon#*mode == 0, iclass 15, count 2 2006.189.08:05:22.15#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.08:05:22.15#ibcon#[27=AT05-04\r\n] 2006.189.08:05:22.15#ibcon#*before write, iclass 15, count 2 2006.189.08:05:22.15#ibcon#enter sib2, iclass 15, count 2 2006.189.08:05:22.15#ibcon#flushed, iclass 15, count 2 2006.189.08:05:22.15#ibcon#about to write, iclass 15, count 2 2006.189.08:05:22.15#ibcon#wrote, iclass 15, count 2 2006.189.08:05:22.15#ibcon#about to read 3, iclass 15, count 2 2006.189.08:05:22.18#ibcon#read 3, iclass 15, count 2 2006.189.08:05:22.18#ibcon#about to read 4, iclass 15, count 2 2006.189.08:05:22.18#ibcon#read 4, iclass 15, count 2 2006.189.08:05:22.18#ibcon#about to read 5, iclass 15, count 2 2006.189.08:05:22.18#ibcon#read 5, iclass 15, count 2 2006.189.08:05:22.18#ibcon#about to read 6, iclass 15, count 2 2006.189.08:05:22.18#ibcon#read 6, iclass 15, count 2 2006.189.08:05:22.18#ibcon#end of sib2, iclass 15, count 2 2006.189.08:05:22.18#ibcon#*after write, iclass 15, count 2 2006.189.08:05:22.18#ibcon#*before return 0, iclass 15, count 2 2006.189.08:05:22.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:22.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:05:22.18#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.08:05:22.18#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:22.18#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:22.30#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:22.30#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:22.30#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:05:22.30#ibcon#first serial, iclass 15, count 0 2006.189.08:05:22.30#ibcon#enter sib2, iclass 15, count 0 2006.189.08:05:22.30#ibcon#flushed, iclass 15, count 0 2006.189.08:05:22.30#ibcon#about to write, iclass 15, count 0 2006.189.08:05:22.30#ibcon#wrote, iclass 15, count 0 2006.189.08:05:22.30#ibcon#about to read 3, iclass 15, count 0 2006.189.08:05:22.32#ibcon#read 3, iclass 15, count 0 2006.189.08:05:22.32#ibcon#about to read 4, iclass 15, count 0 2006.189.08:05:22.32#ibcon#read 4, iclass 15, count 0 2006.189.08:05:22.32#ibcon#about to read 5, iclass 15, count 0 2006.189.08:05:22.32#ibcon#read 5, iclass 15, count 0 2006.189.08:05:22.32#ibcon#about to read 6, iclass 15, count 0 2006.189.08:05:22.32#ibcon#read 6, iclass 15, count 0 2006.189.08:05:22.32#ibcon#end of sib2, iclass 15, count 0 2006.189.08:05:22.32#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:05:22.32#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:05:22.32#ibcon#[27=USB\r\n] 2006.189.08:05:22.32#ibcon#*before write, iclass 15, count 0 2006.189.08:05:22.32#ibcon#enter sib2, iclass 15, count 0 2006.189.08:05:22.32#ibcon#flushed, iclass 15, count 0 2006.189.08:05:22.32#ibcon#about to write, iclass 15, count 0 2006.189.08:05:22.32#ibcon#wrote, iclass 15, count 0 2006.189.08:05:22.32#ibcon#about to read 3, iclass 15, count 0 2006.189.08:05:22.35#ibcon#read 3, iclass 15, count 0 2006.189.08:05:22.35#ibcon#about to read 4, iclass 15, count 0 2006.189.08:05:22.35#ibcon#read 4, iclass 15, count 0 2006.189.08:05:22.35#ibcon#about to read 5, iclass 15, count 0 2006.189.08:05:22.35#ibcon#read 5, iclass 15, count 0 2006.189.08:05:22.35#ibcon#about to read 6, iclass 15, count 0 2006.189.08:05:22.35#ibcon#read 6, iclass 15, count 0 2006.189.08:05:22.35#ibcon#end of sib2, iclass 15, count 0 2006.189.08:05:22.35#ibcon#*after write, iclass 15, count 0 2006.189.08:05:22.35#ibcon#*before return 0, iclass 15, count 0 2006.189.08:05:22.35#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:22.35#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:05:22.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:05:22.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:05:22.35$vc4f8/vblo=6,752.99 2006.189.08:05:22.35#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.08:05:22.35#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.08:05:22.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:05:22.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:22.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:22.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:22.35#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:05:22.35#ibcon#first serial, iclass 17, count 0 2006.189.08:05:22.35#ibcon#enter sib2, iclass 17, count 0 2006.189.08:05:22.35#ibcon#flushed, iclass 17, count 0 2006.189.08:05:22.35#ibcon#about to write, iclass 17, count 0 2006.189.08:05:22.35#ibcon#wrote, iclass 17, count 0 2006.189.08:05:22.35#ibcon#about to read 3, iclass 17, count 0 2006.189.08:05:22.37#ibcon#read 3, iclass 17, count 0 2006.189.08:05:22.37#ibcon#about to read 4, iclass 17, count 0 2006.189.08:05:22.37#ibcon#read 4, iclass 17, count 0 2006.189.08:05:22.37#ibcon#about to read 5, iclass 17, count 0 2006.189.08:05:22.37#ibcon#read 5, iclass 17, count 0 2006.189.08:05:22.37#ibcon#about to read 6, iclass 17, count 0 2006.189.08:05:22.37#ibcon#read 6, iclass 17, count 0 2006.189.08:05:22.37#ibcon#end of sib2, iclass 17, count 0 2006.189.08:05:22.37#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:05:22.37#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:05:22.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:05:22.37#ibcon#*before write, iclass 17, count 0 2006.189.08:05:22.37#ibcon#enter sib2, iclass 17, count 0 2006.189.08:05:22.37#ibcon#flushed, iclass 17, count 0 2006.189.08:05:22.37#ibcon#about to write, iclass 17, count 0 2006.189.08:05:22.37#ibcon#wrote, iclass 17, count 0 2006.189.08:05:22.37#ibcon#about to read 3, iclass 17, count 0 2006.189.08:05:22.41#ibcon#read 3, iclass 17, count 0 2006.189.08:05:22.41#ibcon#about to read 4, iclass 17, count 0 2006.189.08:05:22.41#ibcon#read 4, iclass 17, count 0 2006.189.08:05:22.41#ibcon#about to read 5, iclass 17, count 0 2006.189.08:05:22.41#ibcon#read 5, iclass 17, count 0 2006.189.08:05:22.41#ibcon#about to read 6, iclass 17, count 0 2006.189.08:05:22.41#ibcon#read 6, iclass 17, count 0 2006.189.08:05:22.41#ibcon#end of sib2, iclass 17, count 0 2006.189.08:05:22.41#ibcon#*after write, iclass 17, count 0 2006.189.08:05:22.41#ibcon#*before return 0, iclass 17, count 0 2006.189.08:05:22.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:22.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:05:22.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:05:22.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:05:22.41$vc4f8/vb=6,4 2006.189.08:05:22.41#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.08:05:22.41#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.08:05:22.41#ibcon#ireg 11 cls_cnt 2 2006.189.08:05:22.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:22.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:22.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:22.47#ibcon#enter wrdev, iclass 19, count 2 2006.189.08:05:22.47#ibcon#first serial, iclass 19, count 2 2006.189.08:05:22.47#ibcon#enter sib2, iclass 19, count 2 2006.189.08:05:22.47#ibcon#flushed, iclass 19, count 2 2006.189.08:05:22.47#ibcon#about to write, iclass 19, count 2 2006.189.08:05:22.47#ibcon#wrote, iclass 19, count 2 2006.189.08:05:22.47#ibcon#about to read 3, iclass 19, count 2 2006.189.08:05:22.49#ibcon#read 3, iclass 19, count 2 2006.189.08:05:22.49#ibcon#about to read 4, iclass 19, count 2 2006.189.08:05:22.49#ibcon#read 4, iclass 19, count 2 2006.189.08:05:22.49#ibcon#about to read 5, iclass 19, count 2 2006.189.08:05:22.49#ibcon#read 5, iclass 19, count 2 2006.189.08:05:22.49#ibcon#about to read 6, iclass 19, count 2 2006.189.08:05:22.49#ibcon#read 6, iclass 19, count 2 2006.189.08:05:22.49#ibcon#end of sib2, iclass 19, count 2 2006.189.08:05:22.49#ibcon#*mode == 0, iclass 19, count 2 2006.189.08:05:22.49#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.08:05:22.49#ibcon#[27=AT06-04\r\n] 2006.189.08:05:22.49#ibcon#*before write, iclass 19, count 2 2006.189.08:05:22.49#ibcon#enter sib2, iclass 19, count 2 2006.189.08:05:22.49#ibcon#flushed, iclass 19, count 2 2006.189.08:05:22.49#ibcon#about to write, iclass 19, count 2 2006.189.08:05:22.49#ibcon#wrote, iclass 19, count 2 2006.189.08:05:22.49#ibcon#about to read 3, iclass 19, count 2 2006.189.08:05:22.52#ibcon#read 3, iclass 19, count 2 2006.189.08:05:22.52#ibcon#about to read 4, iclass 19, count 2 2006.189.08:05:22.52#ibcon#read 4, iclass 19, count 2 2006.189.08:05:22.52#ibcon#about to read 5, iclass 19, count 2 2006.189.08:05:22.52#ibcon#read 5, iclass 19, count 2 2006.189.08:05:22.52#ibcon#about to read 6, iclass 19, count 2 2006.189.08:05:22.52#ibcon#read 6, iclass 19, count 2 2006.189.08:05:22.52#ibcon#end of sib2, iclass 19, count 2 2006.189.08:05:22.52#ibcon#*after write, iclass 19, count 2 2006.189.08:05:22.52#ibcon#*before return 0, iclass 19, count 2 2006.189.08:05:22.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:22.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:05:22.52#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.08:05:22.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:05:22.52#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:22.64#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:22.64#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:22.64#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:05:22.64#ibcon#first serial, iclass 19, count 0 2006.189.08:05:22.64#ibcon#enter sib2, iclass 19, count 0 2006.189.08:05:22.64#ibcon#flushed, iclass 19, count 0 2006.189.08:05:22.64#ibcon#about to write, iclass 19, count 0 2006.189.08:05:22.64#ibcon#wrote, iclass 19, count 0 2006.189.08:05:22.64#ibcon#about to read 3, iclass 19, count 0 2006.189.08:05:22.66#ibcon#read 3, iclass 19, count 0 2006.189.08:05:22.66#ibcon#about to read 4, iclass 19, count 0 2006.189.08:05:22.66#ibcon#read 4, iclass 19, count 0 2006.189.08:05:22.66#ibcon#about to read 5, iclass 19, count 0 2006.189.08:05:22.66#ibcon#read 5, iclass 19, count 0 2006.189.08:05:22.66#ibcon#about to read 6, iclass 19, count 0 2006.189.08:05:22.66#ibcon#read 6, iclass 19, count 0 2006.189.08:05:22.66#ibcon#end of sib2, iclass 19, count 0 2006.189.08:05:22.66#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:05:22.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:05:22.66#ibcon#[27=USB\r\n] 2006.189.08:05:22.66#ibcon#*before write, iclass 19, count 0 2006.189.08:05:22.66#ibcon#enter sib2, iclass 19, count 0 2006.189.08:05:22.66#ibcon#flushed, iclass 19, count 0 2006.189.08:05:22.66#ibcon#about to write, iclass 19, count 0 2006.189.08:05:22.66#ibcon#wrote, iclass 19, count 0 2006.189.08:05:22.66#ibcon#about to read 3, iclass 19, count 0 2006.189.08:05:22.69#ibcon#read 3, iclass 19, count 0 2006.189.08:05:22.69#ibcon#about to read 4, iclass 19, count 0 2006.189.08:05:22.69#ibcon#read 4, iclass 19, count 0 2006.189.08:05:22.69#ibcon#about to read 5, iclass 19, count 0 2006.189.08:05:22.69#ibcon#read 5, iclass 19, count 0 2006.189.08:05:22.69#ibcon#about to read 6, iclass 19, count 0 2006.189.08:05:22.69#ibcon#read 6, iclass 19, count 0 2006.189.08:05:22.69#ibcon#end of sib2, iclass 19, count 0 2006.189.08:05:22.69#ibcon#*after write, iclass 19, count 0 2006.189.08:05:22.69#ibcon#*before return 0, iclass 19, count 0 2006.189.08:05:22.69#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:22.69#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:05:22.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:05:22.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:05:22.69$vc4f8/vabw=wide 2006.189.08:05:22.69#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.08:05:22.69#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.08:05:22.69#ibcon#ireg 8 cls_cnt 0 2006.189.08:05:22.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:22.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:22.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:22.69#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:05:22.69#ibcon#first serial, iclass 21, count 0 2006.189.08:05:22.69#ibcon#enter sib2, iclass 21, count 0 2006.189.08:05:22.69#ibcon#flushed, iclass 21, count 0 2006.189.08:05:22.69#ibcon#about to write, iclass 21, count 0 2006.189.08:05:22.69#ibcon#wrote, iclass 21, count 0 2006.189.08:05:22.69#ibcon#about to read 3, iclass 21, count 0 2006.189.08:05:22.71#ibcon#read 3, iclass 21, count 0 2006.189.08:05:22.71#ibcon#about to read 4, iclass 21, count 0 2006.189.08:05:22.71#ibcon#read 4, iclass 21, count 0 2006.189.08:05:22.71#ibcon#about to read 5, iclass 21, count 0 2006.189.08:05:22.71#ibcon#read 5, iclass 21, count 0 2006.189.08:05:22.71#ibcon#about to read 6, iclass 21, count 0 2006.189.08:05:22.71#ibcon#read 6, iclass 21, count 0 2006.189.08:05:22.71#ibcon#end of sib2, iclass 21, count 0 2006.189.08:05:22.71#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:05:22.71#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:05:22.71#ibcon#[25=BW32\r\n] 2006.189.08:05:22.71#ibcon#*before write, iclass 21, count 0 2006.189.08:05:22.71#ibcon#enter sib2, iclass 21, count 0 2006.189.08:05:22.71#ibcon#flushed, iclass 21, count 0 2006.189.08:05:22.71#ibcon#about to write, iclass 21, count 0 2006.189.08:05:22.71#ibcon#wrote, iclass 21, count 0 2006.189.08:05:22.71#ibcon#about to read 3, iclass 21, count 0 2006.189.08:05:22.74#ibcon#read 3, iclass 21, count 0 2006.189.08:05:22.74#ibcon#about to read 4, iclass 21, count 0 2006.189.08:05:22.74#ibcon#read 4, iclass 21, count 0 2006.189.08:05:22.74#ibcon#about to read 5, iclass 21, count 0 2006.189.08:05:22.74#ibcon#read 5, iclass 21, count 0 2006.189.08:05:22.74#ibcon#about to read 6, iclass 21, count 0 2006.189.08:05:22.74#ibcon#read 6, iclass 21, count 0 2006.189.08:05:22.74#ibcon#end of sib2, iclass 21, count 0 2006.189.08:05:22.74#ibcon#*after write, iclass 21, count 0 2006.189.08:05:22.74#ibcon#*before return 0, iclass 21, count 0 2006.189.08:05:22.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:22.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:05:22.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:05:22.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:05:22.74$vc4f8/vbbw=wide 2006.189.08:05:22.74#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.08:05:22.74#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.08:05:22.74#ibcon#ireg 8 cls_cnt 0 2006.189.08:05:22.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:05:22.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:05:22.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:05:22.81#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:05:22.81#ibcon#first serial, iclass 23, count 0 2006.189.08:05:22.81#ibcon#enter sib2, iclass 23, count 0 2006.189.08:05:22.81#ibcon#flushed, iclass 23, count 0 2006.189.08:05:22.81#ibcon#about to write, iclass 23, count 0 2006.189.08:05:22.81#ibcon#wrote, iclass 23, count 0 2006.189.08:05:22.81#ibcon#about to read 3, iclass 23, count 0 2006.189.08:05:22.83#ibcon#read 3, iclass 23, count 0 2006.189.08:05:22.83#ibcon#about to read 4, iclass 23, count 0 2006.189.08:05:22.83#ibcon#read 4, iclass 23, count 0 2006.189.08:05:22.83#ibcon#about to read 5, iclass 23, count 0 2006.189.08:05:22.83#ibcon#read 5, iclass 23, count 0 2006.189.08:05:22.83#ibcon#about to read 6, iclass 23, count 0 2006.189.08:05:22.83#ibcon#read 6, iclass 23, count 0 2006.189.08:05:22.83#ibcon#end of sib2, iclass 23, count 0 2006.189.08:05:22.83#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:05:22.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:05:22.83#ibcon#[27=BW32\r\n] 2006.189.08:05:22.83#ibcon#*before write, iclass 23, count 0 2006.189.08:05:22.83#ibcon#enter sib2, iclass 23, count 0 2006.189.08:05:22.83#ibcon#flushed, iclass 23, count 0 2006.189.08:05:22.83#ibcon#about to write, iclass 23, count 0 2006.189.08:05:22.83#ibcon#wrote, iclass 23, count 0 2006.189.08:05:22.83#ibcon#about to read 3, iclass 23, count 0 2006.189.08:05:22.86#ibcon#read 3, iclass 23, count 0 2006.189.08:05:22.86#ibcon#about to read 4, iclass 23, count 0 2006.189.08:05:22.86#ibcon#read 4, iclass 23, count 0 2006.189.08:05:22.86#ibcon#about to read 5, iclass 23, count 0 2006.189.08:05:22.86#ibcon#read 5, iclass 23, count 0 2006.189.08:05:22.86#ibcon#about to read 6, iclass 23, count 0 2006.189.08:05:22.86#ibcon#read 6, iclass 23, count 0 2006.189.08:05:22.86#ibcon#end of sib2, iclass 23, count 0 2006.189.08:05:22.86#ibcon#*after write, iclass 23, count 0 2006.189.08:05:22.86#ibcon#*before return 0, iclass 23, count 0 2006.189.08:05:22.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:05:22.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:05:22.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:05:22.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:05:22.86$4f8m12a/ifd4f 2006.189.08:05:22.86$ifd4f/lo= 2006.189.08:05:22.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:05:22.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:05:22.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:05:22.86$ifd4f/patch= 2006.189.08:05:22.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:05:22.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:05:22.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:05:22.86$4f8m12a/"form=m,16.000,1:2 2006.189.08:05:22.86$4f8m12a/"tpicd 2006.189.08:05:22.86$4f8m12a/echo=off 2006.189.08:05:22.86$4f8m12a/xlog=off 2006.189.08:05:22.86:!2006.189.08:05:50 2006.189.08:05:32.14#trakl#Source acquired 2006.189.08:05:32.14#flagr#flagr/antenna,acquired 2006.189.08:05:50.00:preob 2006.189.08:05:51.14/onsource/TRACKING 2006.189.08:05:51.14:!2006.189.08:06:00 2006.189.08:06:00.00:data_valid=on 2006.189.08:06:00.00:midob 2006.189.08:06:00.14/onsource/TRACKING 2006.189.08:06:00.14/wx/25.63,1009.2,91 2006.189.08:06:00.33/cable/+6.4564E-03 2006.189.08:06:01.42/va/01,08,usb,yes,29,30 2006.189.08:06:01.42/va/02,07,usb,yes,29,30 2006.189.08:06:01.42/va/03,06,usb,yes,30,30 2006.189.08:06:01.42/va/04,07,usb,yes,30,32 2006.189.08:06:01.42/va/05,07,usb,yes,32,33 2006.189.08:06:01.42/va/06,06,usb,yes,31,30 2006.189.08:06:01.42/va/07,06,usb,yes,31,31 2006.189.08:06:01.42/va/08,06,usb,yes,33,33 2006.189.08:06:01.65/valo/01,532.99,yes,locked 2006.189.08:06:01.65/valo/02,572.99,yes,locked 2006.189.08:06:01.65/valo/03,672.99,yes,locked 2006.189.08:06:01.65/valo/04,832.99,yes,locked 2006.189.08:06:01.65/valo/05,652.99,yes,locked 2006.189.08:06:01.65/valo/06,772.99,yes,locked 2006.189.08:06:01.65/valo/07,832.99,yes,locked 2006.189.08:06:01.65/valo/08,852.99,yes,locked 2006.189.08:06:02.74/vb/01,04,usb,yes,28,27 2006.189.08:06:02.74/vb/02,04,usb,yes,30,32 2006.189.08:06:02.74/vb/03,04,usb,yes,27,30 2006.189.08:06:02.74/vb/04,04,usb,yes,27,28 2006.189.08:06:02.74/vb/05,04,usb,yes,26,30 2006.189.08:06:02.74/vb/06,04,usb,yes,27,30 2006.189.08:06:02.74/vb/07,04,usb,yes,29,29 2006.189.08:06:02.74/vb/08,04,usb,yes,27,30 2006.189.08:06:02.97/vblo/01,632.99,yes,locked 2006.189.08:06:02.97/vblo/02,640.99,yes,locked 2006.189.08:06:02.97/vblo/03,656.99,yes,locked 2006.189.08:06:02.97/vblo/04,712.99,yes,locked 2006.189.08:06:02.97/vblo/05,744.99,yes,locked 2006.189.08:06:02.97/vblo/06,752.99,yes,locked 2006.189.08:06:02.97/vblo/07,734.99,yes,locked 2006.189.08:06:02.97/vblo/08,744.99,yes,locked 2006.189.08:06:03.12/vabw/8 2006.189.08:06:03.27/vbbw/8 2006.189.08:06:03.40/xfe/off,on,14.5 2006.189.08:06:03.79/ifatt/23,28,28,28 2006.189.08:06:04.08/fmout-gps/S +2.97E-07 2006.189.08:06:04.16:!2006.189.08:07:00 2006.189.08:07:00.00:data_valid=off 2006.189.08:07:00.00:postob 2006.189.08:07:00.17/cable/+6.4566E-03 2006.189.08:07:00.17/wx/25.61,1009.2,91 2006.189.08:07:01.08/fmout-gps/S +2.96E-07 2006.189.08:07:01.08:scan_name=189-0807,k06189,60 2006.189.08:07:01.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.189.08:07:01.14#flagr#flagr/antenna,new-source 2006.189.08:07:02.14:checkk5 2006.189.08:07:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:07:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:07:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:07:03.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:07:04.05/chk_obsdata//k5ts1/T1890806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:07:04.43/chk_obsdata//k5ts2/T1890806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:07:04.80/chk_obsdata//k5ts3/T1890806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:07:05.18/chk_obsdata//k5ts4/T1890806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:07:05.89/k5log//k5ts1_log_newline 2006.189.08:07:06.59/k5log//k5ts2_log_newline 2006.189.08:07:07.28/k5log//k5ts3_log_newline 2006.189.08:07:07.98/k5log//k5ts4_log_newline 2006.189.08:07:08.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:07:08.00:4f8m12a=2 2006.189.08:07:08.00$4f8m12a/echo=on 2006.189.08:07:08.00$4f8m12a/pcalon 2006.189.08:07:08.00$pcalon/"no phase cal control is implemented here 2006.189.08:07:08.01$4f8m12a/"tpicd=stop 2006.189.08:07:08.01$4f8m12a/vc4f8 2006.189.08:07:08.01$vc4f8/valo=1,532.99 2006.189.08:07:08.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.08:07:08.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.08:07:08.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:08.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:08.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:08.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:08.01#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:07:08.01#ibcon#first serial, iclass 34, count 0 2006.189.08:07:08.01#ibcon#enter sib2, iclass 34, count 0 2006.189.08:07:08.01#ibcon#flushed, iclass 34, count 0 2006.189.08:07:08.01#ibcon#about to write, iclass 34, count 0 2006.189.08:07:08.01#ibcon#wrote, iclass 34, count 0 2006.189.08:07:08.01#ibcon#about to read 3, iclass 34, count 0 2006.189.08:07:08.06#ibcon#read 3, iclass 34, count 0 2006.189.08:07:08.06#ibcon#about to read 4, iclass 34, count 0 2006.189.08:07:08.06#ibcon#read 4, iclass 34, count 0 2006.189.08:07:08.06#ibcon#about to read 5, iclass 34, count 0 2006.189.08:07:08.06#ibcon#read 5, iclass 34, count 0 2006.189.08:07:08.06#ibcon#about to read 6, iclass 34, count 0 2006.189.08:07:08.06#ibcon#read 6, iclass 34, count 0 2006.189.08:07:08.06#ibcon#end of sib2, iclass 34, count 0 2006.189.08:07:08.06#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:07:08.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:07:08.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:07:08.06#ibcon#*before write, iclass 34, count 0 2006.189.08:07:08.06#ibcon#enter sib2, iclass 34, count 0 2006.189.08:07:08.06#ibcon#flushed, iclass 34, count 0 2006.189.08:07:08.06#ibcon#about to write, iclass 34, count 0 2006.189.08:07:08.06#ibcon#wrote, iclass 34, count 0 2006.189.08:07:08.06#ibcon#about to read 3, iclass 34, count 0 2006.189.08:07:08.11#ibcon#read 3, iclass 34, count 0 2006.189.08:07:08.11#ibcon#about to read 4, iclass 34, count 0 2006.189.08:07:08.11#ibcon#read 4, iclass 34, count 0 2006.189.08:07:08.11#ibcon#about to read 5, iclass 34, count 0 2006.189.08:07:08.11#ibcon#read 5, iclass 34, count 0 2006.189.08:07:08.11#ibcon#about to read 6, iclass 34, count 0 2006.189.08:07:08.11#ibcon#read 6, iclass 34, count 0 2006.189.08:07:08.11#ibcon#end of sib2, iclass 34, count 0 2006.189.08:07:08.11#ibcon#*after write, iclass 34, count 0 2006.189.08:07:08.11#ibcon#*before return 0, iclass 34, count 0 2006.189.08:07:08.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:08.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:08.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:07:08.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:07:08.11$vc4f8/va=1,8 2006.189.08:07:08.11#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.08:07:08.11#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.08:07:08.11#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:08.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:08.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:08.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:08.11#ibcon#enter wrdev, iclass 36, count 2 2006.189.08:07:08.11#ibcon#first serial, iclass 36, count 2 2006.189.08:07:08.11#ibcon#enter sib2, iclass 36, count 2 2006.189.08:07:08.11#ibcon#flushed, iclass 36, count 2 2006.189.08:07:08.11#ibcon#about to write, iclass 36, count 2 2006.189.08:07:08.11#ibcon#wrote, iclass 36, count 2 2006.189.08:07:08.11#ibcon#about to read 3, iclass 36, count 2 2006.189.08:07:08.13#ibcon#read 3, iclass 36, count 2 2006.189.08:07:08.13#ibcon#about to read 4, iclass 36, count 2 2006.189.08:07:08.13#ibcon#read 4, iclass 36, count 2 2006.189.08:07:08.13#ibcon#about to read 5, iclass 36, count 2 2006.189.08:07:08.13#ibcon#read 5, iclass 36, count 2 2006.189.08:07:08.13#ibcon#about to read 6, iclass 36, count 2 2006.189.08:07:08.13#ibcon#read 6, iclass 36, count 2 2006.189.08:07:08.13#ibcon#end of sib2, iclass 36, count 2 2006.189.08:07:08.13#ibcon#*mode == 0, iclass 36, count 2 2006.189.08:07:08.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.08:07:08.13#ibcon#[25=AT01-08\r\n] 2006.189.08:07:08.13#ibcon#*before write, iclass 36, count 2 2006.189.08:07:08.13#ibcon#enter sib2, iclass 36, count 2 2006.189.08:07:08.13#ibcon#flushed, iclass 36, count 2 2006.189.08:07:08.13#ibcon#about to write, iclass 36, count 2 2006.189.08:07:08.13#ibcon#wrote, iclass 36, count 2 2006.189.08:07:08.13#ibcon#about to read 3, iclass 36, count 2 2006.189.08:07:08.16#ibcon#read 3, iclass 36, count 2 2006.189.08:07:08.16#ibcon#about to read 4, iclass 36, count 2 2006.189.08:07:08.16#ibcon#read 4, iclass 36, count 2 2006.189.08:07:08.16#ibcon#about to read 5, iclass 36, count 2 2006.189.08:07:08.16#ibcon#read 5, iclass 36, count 2 2006.189.08:07:08.16#ibcon#about to read 6, iclass 36, count 2 2006.189.08:07:08.16#ibcon#read 6, iclass 36, count 2 2006.189.08:07:08.16#ibcon#end of sib2, iclass 36, count 2 2006.189.08:07:08.16#ibcon#*after write, iclass 36, count 2 2006.189.08:07:08.16#ibcon#*before return 0, iclass 36, count 2 2006.189.08:07:08.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:08.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:08.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.08:07:08.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:08.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:08.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:08.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:08.28#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:07:08.28#ibcon#first serial, iclass 36, count 0 2006.189.08:07:08.28#ibcon#enter sib2, iclass 36, count 0 2006.189.08:07:08.28#ibcon#flushed, iclass 36, count 0 2006.189.08:07:08.28#ibcon#about to write, iclass 36, count 0 2006.189.08:07:08.28#ibcon#wrote, iclass 36, count 0 2006.189.08:07:08.28#ibcon#about to read 3, iclass 36, count 0 2006.189.08:07:08.30#ibcon#read 3, iclass 36, count 0 2006.189.08:07:08.30#ibcon#about to read 4, iclass 36, count 0 2006.189.08:07:08.30#ibcon#read 4, iclass 36, count 0 2006.189.08:07:08.30#ibcon#about to read 5, iclass 36, count 0 2006.189.08:07:08.30#ibcon#read 5, iclass 36, count 0 2006.189.08:07:08.30#ibcon#about to read 6, iclass 36, count 0 2006.189.08:07:08.30#ibcon#read 6, iclass 36, count 0 2006.189.08:07:08.30#ibcon#end of sib2, iclass 36, count 0 2006.189.08:07:08.30#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:07:08.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:07:08.30#ibcon#[25=USB\r\n] 2006.189.08:07:08.30#ibcon#*before write, iclass 36, count 0 2006.189.08:07:08.30#ibcon#enter sib2, iclass 36, count 0 2006.189.08:07:08.30#ibcon#flushed, iclass 36, count 0 2006.189.08:07:08.30#ibcon#about to write, iclass 36, count 0 2006.189.08:07:08.30#ibcon#wrote, iclass 36, count 0 2006.189.08:07:08.30#ibcon#about to read 3, iclass 36, count 0 2006.189.08:07:08.33#ibcon#read 3, iclass 36, count 0 2006.189.08:07:08.33#ibcon#about to read 4, iclass 36, count 0 2006.189.08:07:08.33#ibcon#read 4, iclass 36, count 0 2006.189.08:07:08.33#ibcon#about to read 5, iclass 36, count 0 2006.189.08:07:08.33#ibcon#read 5, iclass 36, count 0 2006.189.08:07:08.33#ibcon#about to read 6, iclass 36, count 0 2006.189.08:07:08.33#ibcon#read 6, iclass 36, count 0 2006.189.08:07:08.33#ibcon#end of sib2, iclass 36, count 0 2006.189.08:07:08.33#ibcon#*after write, iclass 36, count 0 2006.189.08:07:08.33#ibcon#*before return 0, iclass 36, count 0 2006.189.08:07:08.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:08.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:08.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:07:08.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:07:08.33$vc4f8/valo=2,572.99 2006.189.08:07:08.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.08:07:08.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.08:07:08.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:08.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:08.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:08.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:08.33#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:07:08.33#ibcon#first serial, iclass 38, count 0 2006.189.08:07:08.33#ibcon#enter sib2, iclass 38, count 0 2006.189.08:07:08.33#ibcon#flushed, iclass 38, count 0 2006.189.08:07:08.33#ibcon#about to write, iclass 38, count 0 2006.189.08:07:08.33#ibcon#wrote, iclass 38, count 0 2006.189.08:07:08.33#ibcon#about to read 3, iclass 38, count 0 2006.189.08:07:08.35#ibcon#read 3, iclass 38, count 0 2006.189.08:07:08.35#ibcon#about to read 4, iclass 38, count 0 2006.189.08:07:08.35#ibcon#read 4, iclass 38, count 0 2006.189.08:07:08.35#ibcon#about to read 5, iclass 38, count 0 2006.189.08:07:08.35#ibcon#read 5, iclass 38, count 0 2006.189.08:07:08.35#ibcon#about to read 6, iclass 38, count 0 2006.189.08:07:08.35#ibcon#read 6, iclass 38, count 0 2006.189.08:07:08.35#ibcon#end of sib2, iclass 38, count 0 2006.189.08:07:08.35#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:07:08.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:07:08.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:07:08.35#ibcon#*before write, iclass 38, count 0 2006.189.08:07:08.35#ibcon#enter sib2, iclass 38, count 0 2006.189.08:07:08.35#ibcon#flushed, iclass 38, count 0 2006.189.08:07:08.35#ibcon#about to write, iclass 38, count 0 2006.189.08:07:08.35#ibcon#wrote, iclass 38, count 0 2006.189.08:07:08.35#ibcon#about to read 3, iclass 38, count 0 2006.189.08:07:08.39#ibcon#read 3, iclass 38, count 0 2006.189.08:07:08.39#ibcon#about to read 4, iclass 38, count 0 2006.189.08:07:08.39#ibcon#read 4, iclass 38, count 0 2006.189.08:07:08.39#ibcon#about to read 5, iclass 38, count 0 2006.189.08:07:08.39#ibcon#read 5, iclass 38, count 0 2006.189.08:07:08.39#ibcon#about to read 6, iclass 38, count 0 2006.189.08:07:08.39#ibcon#read 6, iclass 38, count 0 2006.189.08:07:08.39#ibcon#end of sib2, iclass 38, count 0 2006.189.08:07:08.39#ibcon#*after write, iclass 38, count 0 2006.189.08:07:08.39#ibcon#*before return 0, iclass 38, count 0 2006.189.08:07:08.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:08.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:08.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:07:08.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:07:08.39$vc4f8/va=2,7 2006.189.08:07:08.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.08:07:08.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.08:07:08.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:08.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:08.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:08.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:08.45#ibcon#enter wrdev, iclass 40, count 2 2006.189.08:07:08.45#ibcon#first serial, iclass 40, count 2 2006.189.08:07:08.45#ibcon#enter sib2, iclass 40, count 2 2006.189.08:07:08.45#ibcon#flushed, iclass 40, count 2 2006.189.08:07:08.45#ibcon#about to write, iclass 40, count 2 2006.189.08:07:08.45#ibcon#wrote, iclass 40, count 2 2006.189.08:07:08.45#ibcon#about to read 3, iclass 40, count 2 2006.189.08:07:08.47#ibcon#read 3, iclass 40, count 2 2006.189.08:07:08.47#ibcon#about to read 4, iclass 40, count 2 2006.189.08:07:08.47#ibcon#read 4, iclass 40, count 2 2006.189.08:07:08.47#ibcon#about to read 5, iclass 40, count 2 2006.189.08:07:08.47#ibcon#read 5, iclass 40, count 2 2006.189.08:07:08.47#ibcon#about to read 6, iclass 40, count 2 2006.189.08:07:08.47#ibcon#read 6, iclass 40, count 2 2006.189.08:07:08.47#ibcon#end of sib2, iclass 40, count 2 2006.189.08:07:08.47#ibcon#*mode == 0, iclass 40, count 2 2006.189.08:07:08.47#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.08:07:08.47#ibcon#[25=AT02-07\r\n] 2006.189.08:07:08.47#ibcon#*before write, iclass 40, count 2 2006.189.08:07:08.47#ibcon#enter sib2, iclass 40, count 2 2006.189.08:07:08.47#ibcon#flushed, iclass 40, count 2 2006.189.08:07:08.47#ibcon#about to write, iclass 40, count 2 2006.189.08:07:08.47#ibcon#wrote, iclass 40, count 2 2006.189.08:07:08.47#ibcon#about to read 3, iclass 40, count 2 2006.189.08:07:08.50#ibcon#read 3, iclass 40, count 2 2006.189.08:07:08.50#ibcon#about to read 4, iclass 40, count 2 2006.189.08:07:08.50#ibcon#read 4, iclass 40, count 2 2006.189.08:07:08.50#ibcon#about to read 5, iclass 40, count 2 2006.189.08:07:08.50#ibcon#read 5, iclass 40, count 2 2006.189.08:07:08.50#ibcon#about to read 6, iclass 40, count 2 2006.189.08:07:08.50#ibcon#read 6, iclass 40, count 2 2006.189.08:07:08.50#ibcon#end of sib2, iclass 40, count 2 2006.189.08:07:08.50#ibcon#*after write, iclass 40, count 2 2006.189.08:07:08.50#ibcon#*before return 0, iclass 40, count 2 2006.189.08:07:08.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:08.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:08.50#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.08:07:08.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:08.50#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:08.62#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:08.62#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:08.62#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:07:08.62#ibcon#first serial, iclass 40, count 0 2006.189.08:07:08.62#ibcon#enter sib2, iclass 40, count 0 2006.189.08:07:08.62#ibcon#flushed, iclass 40, count 0 2006.189.08:07:08.62#ibcon#about to write, iclass 40, count 0 2006.189.08:07:08.62#ibcon#wrote, iclass 40, count 0 2006.189.08:07:08.62#ibcon#about to read 3, iclass 40, count 0 2006.189.08:07:08.64#ibcon#read 3, iclass 40, count 0 2006.189.08:07:08.64#ibcon#about to read 4, iclass 40, count 0 2006.189.08:07:08.64#ibcon#read 4, iclass 40, count 0 2006.189.08:07:08.64#ibcon#about to read 5, iclass 40, count 0 2006.189.08:07:08.64#ibcon#read 5, iclass 40, count 0 2006.189.08:07:08.64#ibcon#about to read 6, iclass 40, count 0 2006.189.08:07:08.64#ibcon#read 6, iclass 40, count 0 2006.189.08:07:08.64#ibcon#end of sib2, iclass 40, count 0 2006.189.08:07:08.64#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:07:08.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:07:08.64#ibcon#[25=USB\r\n] 2006.189.08:07:08.64#ibcon#*before write, iclass 40, count 0 2006.189.08:07:08.64#ibcon#enter sib2, iclass 40, count 0 2006.189.08:07:08.64#ibcon#flushed, iclass 40, count 0 2006.189.08:07:08.64#ibcon#about to write, iclass 40, count 0 2006.189.08:07:08.64#ibcon#wrote, iclass 40, count 0 2006.189.08:07:08.64#ibcon#about to read 3, iclass 40, count 0 2006.189.08:07:08.67#ibcon#read 3, iclass 40, count 0 2006.189.08:07:08.67#ibcon#about to read 4, iclass 40, count 0 2006.189.08:07:08.67#ibcon#read 4, iclass 40, count 0 2006.189.08:07:08.67#ibcon#about to read 5, iclass 40, count 0 2006.189.08:07:08.67#ibcon#read 5, iclass 40, count 0 2006.189.08:07:08.67#ibcon#about to read 6, iclass 40, count 0 2006.189.08:07:08.67#ibcon#read 6, iclass 40, count 0 2006.189.08:07:08.67#ibcon#end of sib2, iclass 40, count 0 2006.189.08:07:08.67#ibcon#*after write, iclass 40, count 0 2006.189.08:07:08.67#ibcon#*before return 0, iclass 40, count 0 2006.189.08:07:08.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:08.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:08.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:07:08.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:07:08.67$vc4f8/valo=3,672.99 2006.189.08:07:08.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.08:07:08.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.08:07:08.67#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:08.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:08.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:08.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:08.67#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:07:08.67#ibcon#first serial, iclass 4, count 0 2006.189.08:07:08.67#ibcon#enter sib2, iclass 4, count 0 2006.189.08:07:08.67#ibcon#flushed, iclass 4, count 0 2006.189.08:07:08.67#ibcon#about to write, iclass 4, count 0 2006.189.08:07:08.67#ibcon#wrote, iclass 4, count 0 2006.189.08:07:08.67#ibcon#about to read 3, iclass 4, count 0 2006.189.08:07:08.69#ibcon#read 3, iclass 4, count 0 2006.189.08:07:08.69#ibcon#about to read 4, iclass 4, count 0 2006.189.08:07:08.69#ibcon#read 4, iclass 4, count 0 2006.189.08:07:08.69#ibcon#about to read 5, iclass 4, count 0 2006.189.08:07:08.69#ibcon#read 5, iclass 4, count 0 2006.189.08:07:08.69#ibcon#about to read 6, iclass 4, count 0 2006.189.08:07:08.69#ibcon#read 6, iclass 4, count 0 2006.189.08:07:08.69#ibcon#end of sib2, iclass 4, count 0 2006.189.08:07:08.69#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:07:08.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:07:08.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:07:08.69#ibcon#*before write, iclass 4, count 0 2006.189.08:07:08.69#ibcon#enter sib2, iclass 4, count 0 2006.189.08:07:08.69#ibcon#flushed, iclass 4, count 0 2006.189.08:07:08.69#ibcon#about to write, iclass 4, count 0 2006.189.08:07:08.69#ibcon#wrote, iclass 4, count 0 2006.189.08:07:08.69#ibcon#about to read 3, iclass 4, count 0 2006.189.08:07:08.73#ibcon#read 3, iclass 4, count 0 2006.189.08:07:08.73#ibcon#about to read 4, iclass 4, count 0 2006.189.08:07:08.73#ibcon#read 4, iclass 4, count 0 2006.189.08:07:08.73#ibcon#about to read 5, iclass 4, count 0 2006.189.08:07:08.73#ibcon#read 5, iclass 4, count 0 2006.189.08:07:08.73#ibcon#about to read 6, iclass 4, count 0 2006.189.08:07:08.73#ibcon#read 6, iclass 4, count 0 2006.189.08:07:08.73#ibcon#end of sib2, iclass 4, count 0 2006.189.08:07:08.73#ibcon#*after write, iclass 4, count 0 2006.189.08:07:08.73#ibcon#*before return 0, iclass 4, count 0 2006.189.08:07:08.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:08.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:08.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:07:08.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:07:08.73$vc4f8/va=3,6 2006.189.08:07:08.73#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.08:07:08.73#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.08:07:08.73#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:08.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:08.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:08.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:08.79#ibcon#enter wrdev, iclass 6, count 2 2006.189.08:07:08.79#ibcon#first serial, iclass 6, count 2 2006.189.08:07:08.79#ibcon#enter sib2, iclass 6, count 2 2006.189.08:07:08.79#ibcon#flushed, iclass 6, count 2 2006.189.08:07:08.79#ibcon#about to write, iclass 6, count 2 2006.189.08:07:08.79#ibcon#wrote, iclass 6, count 2 2006.189.08:07:08.79#ibcon#about to read 3, iclass 6, count 2 2006.189.08:07:08.81#ibcon#read 3, iclass 6, count 2 2006.189.08:07:08.81#ibcon#about to read 4, iclass 6, count 2 2006.189.08:07:08.81#ibcon#read 4, iclass 6, count 2 2006.189.08:07:08.81#ibcon#about to read 5, iclass 6, count 2 2006.189.08:07:08.81#ibcon#read 5, iclass 6, count 2 2006.189.08:07:08.81#ibcon#about to read 6, iclass 6, count 2 2006.189.08:07:08.81#ibcon#read 6, iclass 6, count 2 2006.189.08:07:08.81#ibcon#end of sib2, iclass 6, count 2 2006.189.08:07:08.81#ibcon#*mode == 0, iclass 6, count 2 2006.189.08:07:08.81#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.08:07:08.81#ibcon#[25=AT03-06\r\n] 2006.189.08:07:08.81#ibcon#*before write, iclass 6, count 2 2006.189.08:07:08.81#ibcon#enter sib2, iclass 6, count 2 2006.189.08:07:08.81#ibcon#flushed, iclass 6, count 2 2006.189.08:07:08.81#ibcon#about to write, iclass 6, count 2 2006.189.08:07:08.81#ibcon#wrote, iclass 6, count 2 2006.189.08:07:08.81#ibcon#about to read 3, iclass 6, count 2 2006.189.08:07:08.84#ibcon#read 3, iclass 6, count 2 2006.189.08:07:08.84#ibcon#about to read 4, iclass 6, count 2 2006.189.08:07:08.84#ibcon#read 4, iclass 6, count 2 2006.189.08:07:08.84#ibcon#about to read 5, iclass 6, count 2 2006.189.08:07:08.84#ibcon#read 5, iclass 6, count 2 2006.189.08:07:08.84#ibcon#about to read 6, iclass 6, count 2 2006.189.08:07:08.84#ibcon#read 6, iclass 6, count 2 2006.189.08:07:08.84#ibcon#end of sib2, iclass 6, count 2 2006.189.08:07:08.84#ibcon#*after write, iclass 6, count 2 2006.189.08:07:08.84#ibcon#*before return 0, iclass 6, count 2 2006.189.08:07:08.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:08.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:08.84#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.08:07:08.84#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:08.84#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:08.96#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:08.96#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:08.96#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:07:08.96#ibcon#first serial, iclass 6, count 0 2006.189.08:07:08.96#ibcon#enter sib2, iclass 6, count 0 2006.189.08:07:08.96#ibcon#flushed, iclass 6, count 0 2006.189.08:07:08.96#ibcon#about to write, iclass 6, count 0 2006.189.08:07:08.96#ibcon#wrote, iclass 6, count 0 2006.189.08:07:08.96#ibcon#about to read 3, iclass 6, count 0 2006.189.08:07:08.98#ibcon#read 3, iclass 6, count 0 2006.189.08:07:08.98#ibcon#about to read 4, iclass 6, count 0 2006.189.08:07:08.98#ibcon#read 4, iclass 6, count 0 2006.189.08:07:08.98#ibcon#about to read 5, iclass 6, count 0 2006.189.08:07:08.98#ibcon#read 5, iclass 6, count 0 2006.189.08:07:08.98#ibcon#about to read 6, iclass 6, count 0 2006.189.08:07:08.98#ibcon#read 6, iclass 6, count 0 2006.189.08:07:08.98#ibcon#end of sib2, iclass 6, count 0 2006.189.08:07:08.98#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:07:08.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:07:08.98#ibcon#[25=USB\r\n] 2006.189.08:07:08.98#ibcon#*before write, iclass 6, count 0 2006.189.08:07:08.98#ibcon#enter sib2, iclass 6, count 0 2006.189.08:07:08.98#ibcon#flushed, iclass 6, count 0 2006.189.08:07:08.98#ibcon#about to write, iclass 6, count 0 2006.189.08:07:08.98#ibcon#wrote, iclass 6, count 0 2006.189.08:07:08.98#ibcon#about to read 3, iclass 6, count 0 2006.189.08:07:09.01#ibcon#read 3, iclass 6, count 0 2006.189.08:07:09.01#ibcon#about to read 4, iclass 6, count 0 2006.189.08:07:09.01#ibcon#read 4, iclass 6, count 0 2006.189.08:07:09.01#ibcon#about to read 5, iclass 6, count 0 2006.189.08:07:09.01#ibcon#read 5, iclass 6, count 0 2006.189.08:07:09.01#ibcon#about to read 6, iclass 6, count 0 2006.189.08:07:09.01#ibcon#read 6, iclass 6, count 0 2006.189.08:07:09.01#ibcon#end of sib2, iclass 6, count 0 2006.189.08:07:09.01#ibcon#*after write, iclass 6, count 0 2006.189.08:07:09.01#ibcon#*before return 0, iclass 6, count 0 2006.189.08:07:09.01#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:09.01#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:09.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:07:09.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:07:09.01$vc4f8/valo=4,832.99 2006.189.08:07:09.01#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.08:07:09.01#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.08:07:09.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:09.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:09.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:09.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:09.01#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:07:09.01#ibcon#first serial, iclass 10, count 0 2006.189.08:07:09.01#ibcon#enter sib2, iclass 10, count 0 2006.189.08:07:09.01#ibcon#flushed, iclass 10, count 0 2006.189.08:07:09.01#ibcon#about to write, iclass 10, count 0 2006.189.08:07:09.01#ibcon#wrote, iclass 10, count 0 2006.189.08:07:09.01#ibcon#about to read 3, iclass 10, count 0 2006.189.08:07:09.03#ibcon#read 3, iclass 10, count 0 2006.189.08:07:09.03#ibcon#about to read 4, iclass 10, count 0 2006.189.08:07:09.03#ibcon#read 4, iclass 10, count 0 2006.189.08:07:09.03#ibcon#about to read 5, iclass 10, count 0 2006.189.08:07:09.03#ibcon#read 5, iclass 10, count 0 2006.189.08:07:09.03#ibcon#about to read 6, iclass 10, count 0 2006.189.08:07:09.03#ibcon#read 6, iclass 10, count 0 2006.189.08:07:09.03#ibcon#end of sib2, iclass 10, count 0 2006.189.08:07:09.03#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:07:09.03#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:07:09.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:07:09.03#ibcon#*before write, iclass 10, count 0 2006.189.08:07:09.03#ibcon#enter sib2, iclass 10, count 0 2006.189.08:07:09.03#ibcon#flushed, iclass 10, count 0 2006.189.08:07:09.03#ibcon#about to write, iclass 10, count 0 2006.189.08:07:09.03#ibcon#wrote, iclass 10, count 0 2006.189.08:07:09.03#ibcon#about to read 3, iclass 10, count 0 2006.189.08:07:09.07#ibcon#read 3, iclass 10, count 0 2006.189.08:07:09.07#ibcon#about to read 4, iclass 10, count 0 2006.189.08:07:09.07#ibcon#read 4, iclass 10, count 0 2006.189.08:07:09.07#ibcon#about to read 5, iclass 10, count 0 2006.189.08:07:09.07#ibcon#read 5, iclass 10, count 0 2006.189.08:07:09.07#ibcon#about to read 6, iclass 10, count 0 2006.189.08:07:09.07#ibcon#read 6, iclass 10, count 0 2006.189.08:07:09.07#ibcon#end of sib2, iclass 10, count 0 2006.189.08:07:09.07#ibcon#*after write, iclass 10, count 0 2006.189.08:07:09.07#ibcon#*before return 0, iclass 10, count 0 2006.189.08:07:09.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:09.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:09.07#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:07:09.07#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:07:09.07$vc4f8/va=4,7 2006.189.08:07:09.07#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.08:07:09.07#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.08:07:09.07#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:09.07#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:09.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:09.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:09.13#ibcon#enter wrdev, iclass 12, count 2 2006.189.08:07:09.13#ibcon#first serial, iclass 12, count 2 2006.189.08:07:09.13#ibcon#enter sib2, iclass 12, count 2 2006.189.08:07:09.13#ibcon#flushed, iclass 12, count 2 2006.189.08:07:09.13#ibcon#about to write, iclass 12, count 2 2006.189.08:07:09.13#ibcon#wrote, iclass 12, count 2 2006.189.08:07:09.13#ibcon#about to read 3, iclass 12, count 2 2006.189.08:07:09.15#ibcon#read 3, iclass 12, count 2 2006.189.08:07:09.15#ibcon#about to read 4, iclass 12, count 2 2006.189.08:07:09.15#ibcon#read 4, iclass 12, count 2 2006.189.08:07:09.15#ibcon#about to read 5, iclass 12, count 2 2006.189.08:07:09.15#ibcon#read 5, iclass 12, count 2 2006.189.08:07:09.15#ibcon#about to read 6, iclass 12, count 2 2006.189.08:07:09.15#ibcon#read 6, iclass 12, count 2 2006.189.08:07:09.15#ibcon#end of sib2, iclass 12, count 2 2006.189.08:07:09.15#ibcon#*mode == 0, iclass 12, count 2 2006.189.08:07:09.15#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.08:07:09.15#ibcon#[25=AT04-07\r\n] 2006.189.08:07:09.15#ibcon#*before write, iclass 12, count 2 2006.189.08:07:09.15#ibcon#enter sib2, iclass 12, count 2 2006.189.08:07:09.15#ibcon#flushed, iclass 12, count 2 2006.189.08:07:09.15#ibcon#about to write, iclass 12, count 2 2006.189.08:07:09.15#ibcon#wrote, iclass 12, count 2 2006.189.08:07:09.15#ibcon#about to read 3, iclass 12, count 2 2006.189.08:07:09.18#ibcon#read 3, iclass 12, count 2 2006.189.08:07:09.18#ibcon#about to read 4, iclass 12, count 2 2006.189.08:07:09.18#ibcon#read 4, iclass 12, count 2 2006.189.08:07:09.18#ibcon#about to read 5, iclass 12, count 2 2006.189.08:07:09.18#ibcon#read 5, iclass 12, count 2 2006.189.08:07:09.18#ibcon#about to read 6, iclass 12, count 2 2006.189.08:07:09.18#ibcon#read 6, iclass 12, count 2 2006.189.08:07:09.18#ibcon#end of sib2, iclass 12, count 2 2006.189.08:07:09.18#ibcon#*after write, iclass 12, count 2 2006.189.08:07:09.18#ibcon#*before return 0, iclass 12, count 2 2006.189.08:07:09.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:09.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:09.18#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.08:07:09.18#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:09.18#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:09.30#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:09.30#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:09.30#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:07:09.30#ibcon#first serial, iclass 12, count 0 2006.189.08:07:09.30#ibcon#enter sib2, iclass 12, count 0 2006.189.08:07:09.30#ibcon#flushed, iclass 12, count 0 2006.189.08:07:09.30#ibcon#about to write, iclass 12, count 0 2006.189.08:07:09.30#ibcon#wrote, iclass 12, count 0 2006.189.08:07:09.30#ibcon#about to read 3, iclass 12, count 0 2006.189.08:07:09.32#ibcon#read 3, iclass 12, count 0 2006.189.08:07:09.32#ibcon#about to read 4, iclass 12, count 0 2006.189.08:07:09.32#ibcon#read 4, iclass 12, count 0 2006.189.08:07:09.32#ibcon#about to read 5, iclass 12, count 0 2006.189.08:07:09.32#ibcon#read 5, iclass 12, count 0 2006.189.08:07:09.32#ibcon#about to read 6, iclass 12, count 0 2006.189.08:07:09.32#ibcon#read 6, iclass 12, count 0 2006.189.08:07:09.32#ibcon#end of sib2, iclass 12, count 0 2006.189.08:07:09.32#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:07:09.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:07:09.32#ibcon#[25=USB\r\n] 2006.189.08:07:09.32#ibcon#*before write, iclass 12, count 0 2006.189.08:07:09.32#ibcon#enter sib2, iclass 12, count 0 2006.189.08:07:09.32#ibcon#flushed, iclass 12, count 0 2006.189.08:07:09.32#ibcon#about to write, iclass 12, count 0 2006.189.08:07:09.32#ibcon#wrote, iclass 12, count 0 2006.189.08:07:09.32#ibcon#about to read 3, iclass 12, count 0 2006.189.08:07:09.35#ibcon#read 3, iclass 12, count 0 2006.189.08:07:09.35#ibcon#about to read 4, iclass 12, count 0 2006.189.08:07:09.35#ibcon#read 4, iclass 12, count 0 2006.189.08:07:09.35#ibcon#about to read 5, iclass 12, count 0 2006.189.08:07:09.35#ibcon#read 5, iclass 12, count 0 2006.189.08:07:09.35#ibcon#about to read 6, iclass 12, count 0 2006.189.08:07:09.35#ibcon#read 6, iclass 12, count 0 2006.189.08:07:09.35#ibcon#end of sib2, iclass 12, count 0 2006.189.08:07:09.35#ibcon#*after write, iclass 12, count 0 2006.189.08:07:09.35#ibcon#*before return 0, iclass 12, count 0 2006.189.08:07:09.35#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:09.35#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:09.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:07:09.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:07:09.35$vc4f8/valo=5,652.99 2006.189.08:07:09.35#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.08:07:09.35#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.08:07:09.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:09.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:09.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:09.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:09.35#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:07:09.35#ibcon#first serial, iclass 14, count 0 2006.189.08:07:09.35#ibcon#enter sib2, iclass 14, count 0 2006.189.08:07:09.35#ibcon#flushed, iclass 14, count 0 2006.189.08:07:09.35#ibcon#about to write, iclass 14, count 0 2006.189.08:07:09.35#ibcon#wrote, iclass 14, count 0 2006.189.08:07:09.35#ibcon#about to read 3, iclass 14, count 0 2006.189.08:07:09.37#ibcon#read 3, iclass 14, count 0 2006.189.08:07:09.37#ibcon#about to read 4, iclass 14, count 0 2006.189.08:07:09.37#ibcon#read 4, iclass 14, count 0 2006.189.08:07:09.37#ibcon#about to read 5, iclass 14, count 0 2006.189.08:07:09.37#ibcon#read 5, iclass 14, count 0 2006.189.08:07:09.37#ibcon#about to read 6, iclass 14, count 0 2006.189.08:07:09.37#ibcon#read 6, iclass 14, count 0 2006.189.08:07:09.37#ibcon#end of sib2, iclass 14, count 0 2006.189.08:07:09.37#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:07:09.37#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:07:09.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:07:09.37#ibcon#*before write, iclass 14, count 0 2006.189.08:07:09.37#ibcon#enter sib2, iclass 14, count 0 2006.189.08:07:09.37#ibcon#flushed, iclass 14, count 0 2006.189.08:07:09.37#ibcon#about to write, iclass 14, count 0 2006.189.08:07:09.37#ibcon#wrote, iclass 14, count 0 2006.189.08:07:09.37#ibcon#about to read 3, iclass 14, count 0 2006.189.08:07:09.41#ibcon#read 3, iclass 14, count 0 2006.189.08:07:09.41#ibcon#about to read 4, iclass 14, count 0 2006.189.08:07:09.41#ibcon#read 4, iclass 14, count 0 2006.189.08:07:09.41#ibcon#about to read 5, iclass 14, count 0 2006.189.08:07:09.41#ibcon#read 5, iclass 14, count 0 2006.189.08:07:09.41#ibcon#about to read 6, iclass 14, count 0 2006.189.08:07:09.41#ibcon#read 6, iclass 14, count 0 2006.189.08:07:09.41#ibcon#end of sib2, iclass 14, count 0 2006.189.08:07:09.41#ibcon#*after write, iclass 14, count 0 2006.189.08:07:09.41#ibcon#*before return 0, iclass 14, count 0 2006.189.08:07:09.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:09.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:09.41#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:07:09.41#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:07:09.41$vc4f8/va=5,7 2006.189.08:07:09.41#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.08:07:09.41#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.08:07:09.41#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:09.41#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:09.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:09.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:09.47#ibcon#enter wrdev, iclass 16, count 2 2006.189.08:07:09.47#ibcon#first serial, iclass 16, count 2 2006.189.08:07:09.47#ibcon#enter sib2, iclass 16, count 2 2006.189.08:07:09.47#ibcon#flushed, iclass 16, count 2 2006.189.08:07:09.47#ibcon#about to write, iclass 16, count 2 2006.189.08:07:09.47#ibcon#wrote, iclass 16, count 2 2006.189.08:07:09.47#ibcon#about to read 3, iclass 16, count 2 2006.189.08:07:09.49#ibcon#read 3, iclass 16, count 2 2006.189.08:07:09.49#ibcon#about to read 4, iclass 16, count 2 2006.189.08:07:09.49#ibcon#read 4, iclass 16, count 2 2006.189.08:07:09.49#ibcon#about to read 5, iclass 16, count 2 2006.189.08:07:09.49#ibcon#read 5, iclass 16, count 2 2006.189.08:07:09.49#ibcon#about to read 6, iclass 16, count 2 2006.189.08:07:09.49#ibcon#read 6, iclass 16, count 2 2006.189.08:07:09.49#ibcon#end of sib2, iclass 16, count 2 2006.189.08:07:09.49#ibcon#*mode == 0, iclass 16, count 2 2006.189.08:07:09.49#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.08:07:09.49#ibcon#[25=AT05-07\r\n] 2006.189.08:07:09.49#ibcon#*before write, iclass 16, count 2 2006.189.08:07:09.49#ibcon#enter sib2, iclass 16, count 2 2006.189.08:07:09.49#ibcon#flushed, iclass 16, count 2 2006.189.08:07:09.49#ibcon#about to write, iclass 16, count 2 2006.189.08:07:09.49#ibcon#wrote, iclass 16, count 2 2006.189.08:07:09.49#ibcon#about to read 3, iclass 16, count 2 2006.189.08:07:09.52#ibcon#read 3, iclass 16, count 2 2006.189.08:07:09.52#ibcon#about to read 4, iclass 16, count 2 2006.189.08:07:09.52#ibcon#read 4, iclass 16, count 2 2006.189.08:07:09.52#ibcon#about to read 5, iclass 16, count 2 2006.189.08:07:09.52#ibcon#read 5, iclass 16, count 2 2006.189.08:07:09.52#ibcon#about to read 6, iclass 16, count 2 2006.189.08:07:09.52#ibcon#read 6, iclass 16, count 2 2006.189.08:07:09.52#ibcon#end of sib2, iclass 16, count 2 2006.189.08:07:09.52#ibcon#*after write, iclass 16, count 2 2006.189.08:07:09.52#ibcon#*before return 0, iclass 16, count 2 2006.189.08:07:09.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:09.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:09.52#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.08:07:09.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:09.52#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:09.64#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:09.64#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:09.64#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:07:09.64#ibcon#first serial, iclass 16, count 0 2006.189.08:07:09.64#ibcon#enter sib2, iclass 16, count 0 2006.189.08:07:09.64#ibcon#flushed, iclass 16, count 0 2006.189.08:07:09.64#ibcon#about to write, iclass 16, count 0 2006.189.08:07:09.64#ibcon#wrote, iclass 16, count 0 2006.189.08:07:09.64#ibcon#about to read 3, iclass 16, count 0 2006.189.08:07:09.66#ibcon#read 3, iclass 16, count 0 2006.189.08:07:09.66#ibcon#about to read 4, iclass 16, count 0 2006.189.08:07:09.66#ibcon#read 4, iclass 16, count 0 2006.189.08:07:09.66#ibcon#about to read 5, iclass 16, count 0 2006.189.08:07:09.66#ibcon#read 5, iclass 16, count 0 2006.189.08:07:09.66#ibcon#about to read 6, iclass 16, count 0 2006.189.08:07:09.66#ibcon#read 6, iclass 16, count 0 2006.189.08:07:09.66#ibcon#end of sib2, iclass 16, count 0 2006.189.08:07:09.66#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:07:09.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:07:09.66#ibcon#[25=USB\r\n] 2006.189.08:07:09.66#ibcon#*before write, iclass 16, count 0 2006.189.08:07:09.66#ibcon#enter sib2, iclass 16, count 0 2006.189.08:07:09.66#ibcon#flushed, iclass 16, count 0 2006.189.08:07:09.66#ibcon#about to write, iclass 16, count 0 2006.189.08:07:09.66#ibcon#wrote, iclass 16, count 0 2006.189.08:07:09.66#ibcon#about to read 3, iclass 16, count 0 2006.189.08:07:09.69#ibcon#read 3, iclass 16, count 0 2006.189.08:07:09.69#ibcon#about to read 4, iclass 16, count 0 2006.189.08:07:09.69#ibcon#read 4, iclass 16, count 0 2006.189.08:07:09.69#ibcon#about to read 5, iclass 16, count 0 2006.189.08:07:09.69#ibcon#read 5, iclass 16, count 0 2006.189.08:07:09.69#ibcon#about to read 6, iclass 16, count 0 2006.189.08:07:09.69#ibcon#read 6, iclass 16, count 0 2006.189.08:07:09.69#ibcon#end of sib2, iclass 16, count 0 2006.189.08:07:09.69#ibcon#*after write, iclass 16, count 0 2006.189.08:07:09.69#ibcon#*before return 0, iclass 16, count 0 2006.189.08:07:09.69#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:09.69#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:09.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:07:09.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:07:09.69$vc4f8/valo=6,772.99 2006.189.08:07:09.69#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.08:07:09.69#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.08:07:09.69#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:09.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:09.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:09.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:09.69#ibcon#enter wrdev, iclass 18, count 0 2006.189.08:07:09.69#ibcon#first serial, iclass 18, count 0 2006.189.08:07:09.69#ibcon#enter sib2, iclass 18, count 0 2006.189.08:07:09.69#ibcon#flushed, iclass 18, count 0 2006.189.08:07:09.69#ibcon#about to write, iclass 18, count 0 2006.189.08:07:09.69#ibcon#wrote, iclass 18, count 0 2006.189.08:07:09.69#ibcon#about to read 3, iclass 18, count 0 2006.189.08:07:09.71#ibcon#read 3, iclass 18, count 0 2006.189.08:07:09.71#ibcon#about to read 4, iclass 18, count 0 2006.189.08:07:09.71#ibcon#read 4, iclass 18, count 0 2006.189.08:07:09.71#ibcon#about to read 5, iclass 18, count 0 2006.189.08:07:09.71#ibcon#read 5, iclass 18, count 0 2006.189.08:07:09.71#ibcon#about to read 6, iclass 18, count 0 2006.189.08:07:09.71#ibcon#read 6, iclass 18, count 0 2006.189.08:07:09.71#ibcon#end of sib2, iclass 18, count 0 2006.189.08:07:09.71#ibcon#*mode == 0, iclass 18, count 0 2006.189.08:07:09.71#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.08:07:09.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:07:09.71#ibcon#*before write, iclass 18, count 0 2006.189.08:07:09.71#ibcon#enter sib2, iclass 18, count 0 2006.189.08:07:09.71#ibcon#flushed, iclass 18, count 0 2006.189.08:07:09.71#ibcon#about to write, iclass 18, count 0 2006.189.08:07:09.71#ibcon#wrote, iclass 18, count 0 2006.189.08:07:09.71#ibcon#about to read 3, iclass 18, count 0 2006.189.08:07:09.75#ibcon#read 3, iclass 18, count 0 2006.189.08:07:09.75#ibcon#about to read 4, iclass 18, count 0 2006.189.08:07:09.75#ibcon#read 4, iclass 18, count 0 2006.189.08:07:09.75#ibcon#about to read 5, iclass 18, count 0 2006.189.08:07:09.75#ibcon#read 5, iclass 18, count 0 2006.189.08:07:09.75#ibcon#about to read 6, iclass 18, count 0 2006.189.08:07:09.75#ibcon#read 6, iclass 18, count 0 2006.189.08:07:09.75#ibcon#end of sib2, iclass 18, count 0 2006.189.08:07:09.75#ibcon#*after write, iclass 18, count 0 2006.189.08:07:09.75#ibcon#*before return 0, iclass 18, count 0 2006.189.08:07:09.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:09.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:09.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.08:07:09.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.08:07:09.75$vc4f8/va=6,6 2006.189.08:07:09.75#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.08:07:09.75#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.08:07:09.75#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:09.75#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:07:09.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:07:09.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:07:09.81#ibcon#enter wrdev, iclass 20, count 2 2006.189.08:07:09.81#ibcon#first serial, iclass 20, count 2 2006.189.08:07:09.81#ibcon#enter sib2, iclass 20, count 2 2006.189.08:07:09.81#ibcon#flushed, iclass 20, count 2 2006.189.08:07:09.81#ibcon#about to write, iclass 20, count 2 2006.189.08:07:09.81#ibcon#wrote, iclass 20, count 2 2006.189.08:07:09.81#ibcon#about to read 3, iclass 20, count 2 2006.189.08:07:09.83#ibcon#read 3, iclass 20, count 2 2006.189.08:07:09.83#ibcon#about to read 4, iclass 20, count 2 2006.189.08:07:09.83#ibcon#read 4, iclass 20, count 2 2006.189.08:07:09.83#ibcon#about to read 5, iclass 20, count 2 2006.189.08:07:09.83#ibcon#read 5, iclass 20, count 2 2006.189.08:07:09.83#ibcon#about to read 6, iclass 20, count 2 2006.189.08:07:09.83#ibcon#read 6, iclass 20, count 2 2006.189.08:07:09.83#ibcon#end of sib2, iclass 20, count 2 2006.189.08:07:09.83#ibcon#*mode == 0, iclass 20, count 2 2006.189.08:07:09.83#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.08:07:09.83#ibcon#[25=AT06-06\r\n] 2006.189.08:07:09.83#ibcon#*before write, iclass 20, count 2 2006.189.08:07:09.83#ibcon#enter sib2, iclass 20, count 2 2006.189.08:07:09.83#ibcon#flushed, iclass 20, count 2 2006.189.08:07:09.83#ibcon#about to write, iclass 20, count 2 2006.189.08:07:09.83#ibcon#wrote, iclass 20, count 2 2006.189.08:07:09.83#ibcon#about to read 3, iclass 20, count 2 2006.189.08:07:09.86#ibcon#read 3, iclass 20, count 2 2006.189.08:07:09.86#ibcon#about to read 4, iclass 20, count 2 2006.189.08:07:09.86#ibcon#read 4, iclass 20, count 2 2006.189.08:07:09.86#ibcon#about to read 5, iclass 20, count 2 2006.189.08:07:09.86#ibcon#read 5, iclass 20, count 2 2006.189.08:07:09.86#ibcon#about to read 6, iclass 20, count 2 2006.189.08:07:09.86#ibcon#read 6, iclass 20, count 2 2006.189.08:07:09.86#ibcon#end of sib2, iclass 20, count 2 2006.189.08:07:09.86#ibcon#*after write, iclass 20, count 2 2006.189.08:07:09.86#ibcon#*before return 0, iclass 20, count 2 2006.189.08:07:09.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:07:09.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:07:09.86#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.08:07:09.86#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:09.86#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:07:09.98#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:07:09.98#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:07:09.98#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:07:09.98#ibcon#first serial, iclass 20, count 0 2006.189.08:07:09.98#ibcon#enter sib2, iclass 20, count 0 2006.189.08:07:09.98#ibcon#flushed, iclass 20, count 0 2006.189.08:07:09.98#ibcon#about to write, iclass 20, count 0 2006.189.08:07:09.98#ibcon#wrote, iclass 20, count 0 2006.189.08:07:09.98#ibcon#about to read 3, iclass 20, count 0 2006.189.08:07:10.00#ibcon#read 3, iclass 20, count 0 2006.189.08:07:10.00#ibcon#about to read 4, iclass 20, count 0 2006.189.08:07:10.00#ibcon#read 4, iclass 20, count 0 2006.189.08:07:10.00#ibcon#about to read 5, iclass 20, count 0 2006.189.08:07:10.00#ibcon#read 5, iclass 20, count 0 2006.189.08:07:10.00#ibcon#about to read 6, iclass 20, count 0 2006.189.08:07:10.00#ibcon#read 6, iclass 20, count 0 2006.189.08:07:10.00#ibcon#end of sib2, iclass 20, count 0 2006.189.08:07:10.00#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:07:10.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:07:10.00#ibcon#[25=USB\r\n] 2006.189.08:07:10.00#ibcon#*before write, iclass 20, count 0 2006.189.08:07:10.00#ibcon#enter sib2, iclass 20, count 0 2006.189.08:07:10.00#ibcon#flushed, iclass 20, count 0 2006.189.08:07:10.00#ibcon#about to write, iclass 20, count 0 2006.189.08:07:10.00#ibcon#wrote, iclass 20, count 0 2006.189.08:07:10.00#ibcon#about to read 3, iclass 20, count 0 2006.189.08:07:10.03#ibcon#read 3, iclass 20, count 0 2006.189.08:07:10.03#ibcon#about to read 4, iclass 20, count 0 2006.189.08:07:10.03#ibcon#read 4, iclass 20, count 0 2006.189.08:07:10.03#ibcon#about to read 5, iclass 20, count 0 2006.189.08:07:10.03#ibcon#read 5, iclass 20, count 0 2006.189.08:07:10.03#ibcon#about to read 6, iclass 20, count 0 2006.189.08:07:10.03#ibcon#read 6, iclass 20, count 0 2006.189.08:07:10.03#ibcon#end of sib2, iclass 20, count 0 2006.189.08:07:10.03#ibcon#*after write, iclass 20, count 0 2006.189.08:07:10.03#ibcon#*before return 0, iclass 20, count 0 2006.189.08:07:10.03#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:07:10.03#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:07:10.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:07:10.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:07:10.03$vc4f8/valo=7,832.99 2006.189.08:07:10.03#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.08:07:10.03#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.08:07:10.03#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:10.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:07:10.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:07:10.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:07:10.03#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:07:10.03#ibcon#first serial, iclass 22, count 0 2006.189.08:07:10.03#ibcon#enter sib2, iclass 22, count 0 2006.189.08:07:10.03#ibcon#flushed, iclass 22, count 0 2006.189.08:07:10.03#ibcon#about to write, iclass 22, count 0 2006.189.08:07:10.03#ibcon#wrote, iclass 22, count 0 2006.189.08:07:10.03#ibcon#about to read 3, iclass 22, count 0 2006.189.08:07:10.05#ibcon#read 3, iclass 22, count 0 2006.189.08:07:10.05#ibcon#about to read 4, iclass 22, count 0 2006.189.08:07:10.05#ibcon#read 4, iclass 22, count 0 2006.189.08:07:10.05#ibcon#about to read 5, iclass 22, count 0 2006.189.08:07:10.05#ibcon#read 5, iclass 22, count 0 2006.189.08:07:10.05#ibcon#about to read 6, iclass 22, count 0 2006.189.08:07:10.05#ibcon#read 6, iclass 22, count 0 2006.189.08:07:10.05#ibcon#end of sib2, iclass 22, count 0 2006.189.08:07:10.05#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:07:10.05#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:07:10.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:07:10.05#ibcon#*before write, iclass 22, count 0 2006.189.08:07:10.05#ibcon#enter sib2, iclass 22, count 0 2006.189.08:07:10.05#ibcon#flushed, iclass 22, count 0 2006.189.08:07:10.05#ibcon#about to write, iclass 22, count 0 2006.189.08:07:10.05#ibcon#wrote, iclass 22, count 0 2006.189.08:07:10.05#ibcon#about to read 3, iclass 22, count 0 2006.189.08:07:10.09#ibcon#read 3, iclass 22, count 0 2006.189.08:07:10.09#ibcon#about to read 4, iclass 22, count 0 2006.189.08:07:10.09#ibcon#read 4, iclass 22, count 0 2006.189.08:07:10.09#ibcon#about to read 5, iclass 22, count 0 2006.189.08:07:10.09#ibcon#read 5, iclass 22, count 0 2006.189.08:07:10.09#ibcon#about to read 6, iclass 22, count 0 2006.189.08:07:10.09#ibcon#read 6, iclass 22, count 0 2006.189.08:07:10.09#ibcon#end of sib2, iclass 22, count 0 2006.189.08:07:10.09#ibcon#*after write, iclass 22, count 0 2006.189.08:07:10.09#ibcon#*before return 0, iclass 22, count 0 2006.189.08:07:10.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:07:10.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:07:10.09#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:07:10.09#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:07:10.09$vc4f8/va=7,6 2006.189.08:07:10.09#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.08:07:10.09#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.08:07:10.09#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:10.09#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:07:10.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:07:10.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:07:10.15#ibcon#enter wrdev, iclass 24, count 2 2006.189.08:07:10.15#ibcon#first serial, iclass 24, count 2 2006.189.08:07:10.15#ibcon#enter sib2, iclass 24, count 2 2006.189.08:07:10.15#ibcon#flushed, iclass 24, count 2 2006.189.08:07:10.15#ibcon#about to write, iclass 24, count 2 2006.189.08:07:10.15#ibcon#wrote, iclass 24, count 2 2006.189.08:07:10.15#ibcon#about to read 3, iclass 24, count 2 2006.189.08:07:10.17#ibcon#read 3, iclass 24, count 2 2006.189.08:07:10.17#ibcon#about to read 4, iclass 24, count 2 2006.189.08:07:10.17#ibcon#read 4, iclass 24, count 2 2006.189.08:07:10.17#ibcon#about to read 5, iclass 24, count 2 2006.189.08:07:10.17#ibcon#read 5, iclass 24, count 2 2006.189.08:07:10.17#ibcon#about to read 6, iclass 24, count 2 2006.189.08:07:10.17#ibcon#read 6, iclass 24, count 2 2006.189.08:07:10.17#ibcon#end of sib2, iclass 24, count 2 2006.189.08:07:10.17#ibcon#*mode == 0, iclass 24, count 2 2006.189.08:07:10.17#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.08:07:10.17#ibcon#[25=AT07-06\r\n] 2006.189.08:07:10.17#ibcon#*before write, iclass 24, count 2 2006.189.08:07:10.17#ibcon#enter sib2, iclass 24, count 2 2006.189.08:07:10.17#ibcon#flushed, iclass 24, count 2 2006.189.08:07:10.17#ibcon#about to write, iclass 24, count 2 2006.189.08:07:10.17#ibcon#wrote, iclass 24, count 2 2006.189.08:07:10.17#ibcon#about to read 3, iclass 24, count 2 2006.189.08:07:10.20#ibcon#read 3, iclass 24, count 2 2006.189.08:07:10.20#ibcon#about to read 4, iclass 24, count 2 2006.189.08:07:10.20#ibcon#read 4, iclass 24, count 2 2006.189.08:07:10.20#ibcon#about to read 5, iclass 24, count 2 2006.189.08:07:10.20#ibcon#read 5, iclass 24, count 2 2006.189.08:07:10.20#ibcon#about to read 6, iclass 24, count 2 2006.189.08:07:10.20#ibcon#read 6, iclass 24, count 2 2006.189.08:07:10.20#ibcon#end of sib2, iclass 24, count 2 2006.189.08:07:10.20#ibcon#*after write, iclass 24, count 2 2006.189.08:07:10.20#ibcon#*before return 0, iclass 24, count 2 2006.189.08:07:10.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:07:10.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:07:10.20#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.08:07:10.20#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:10.20#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:07:10.32#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:07:10.32#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:07:10.32#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:07:10.32#ibcon#first serial, iclass 24, count 0 2006.189.08:07:10.32#ibcon#enter sib2, iclass 24, count 0 2006.189.08:07:10.32#ibcon#flushed, iclass 24, count 0 2006.189.08:07:10.32#ibcon#about to write, iclass 24, count 0 2006.189.08:07:10.32#ibcon#wrote, iclass 24, count 0 2006.189.08:07:10.32#ibcon#about to read 3, iclass 24, count 0 2006.189.08:07:10.34#ibcon#read 3, iclass 24, count 0 2006.189.08:07:10.34#ibcon#about to read 4, iclass 24, count 0 2006.189.08:07:10.34#ibcon#read 4, iclass 24, count 0 2006.189.08:07:10.34#ibcon#about to read 5, iclass 24, count 0 2006.189.08:07:10.34#ibcon#read 5, iclass 24, count 0 2006.189.08:07:10.34#ibcon#about to read 6, iclass 24, count 0 2006.189.08:07:10.34#ibcon#read 6, iclass 24, count 0 2006.189.08:07:10.34#ibcon#end of sib2, iclass 24, count 0 2006.189.08:07:10.34#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:07:10.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:07:10.34#ibcon#[25=USB\r\n] 2006.189.08:07:10.34#ibcon#*before write, iclass 24, count 0 2006.189.08:07:10.34#ibcon#enter sib2, iclass 24, count 0 2006.189.08:07:10.34#ibcon#flushed, iclass 24, count 0 2006.189.08:07:10.34#ibcon#about to write, iclass 24, count 0 2006.189.08:07:10.34#ibcon#wrote, iclass 24, count 0 2006.189.08:07:10.34#ibcon#about to read 3, iclass 24, count 0 2006.189.08:07:10.37#ibcon#read 3, iclass 24, count 0 2006.189.08:07:10.37#ibcon#about to read 4, iclass 24, count 0 2006.189.08:07:10.37#ibcon#read 4, iclass 24, count 0 2006.189.08:07:10.37#ibcon#about to read 5, iclass 24, count 0 2006.189.08:07:10.37#ibcon#read 5, iclass 24, count 0 2006.189.08:07:10.37#ibcon#about to read 6, iclass 24, count 0 2006.189.08:07:10.37#ibcon#read 6, iclass 24, count 0 2006.189.08:07:10.37#ibcon#end of sib2, iclass 24, count 0 2006.189.08:07:10.37#ibcon#*after write, iclass 24, count 0 2006.189.08:07:10.37#ibcon#*before return 0, iclass 24, count 0 2006.189.08:07:10.37#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:07:10.37#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:07:10.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:07:10.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:07:10.37$vc4f8/valo=8,852.99 2006.189.08:07:10.37#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.08:07:10.37#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.08:07:10.37#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:10.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:07:10.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:07:10.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:07:10.37#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:07:10.37#ibcon#first serial, iclass 26, count 0 2006.189.08:07:10.37#ibcon#enter sib2, iclass 26, count 0 2006.189.08:07:10.37#ibcon#flushed, iclass 26, count 0 2006.189.08:07:10.37#ibcon#about to write, iclass 26, count 0 2006.189.08:07:10.37#ibcon#wrote, iclass 26, count 0 2006.189.08:07:10.37#ibcon#about to read 3, iclass 26, count 0 2006.189.08:07:10.39#ibcon#read 3, iclass 26, count 0 2006.189.08:07:10.39#ibcon#about to read 4, iclass 26, count 0 2006.189.08:07:10.39#ibcon#read 4, iclass 26, count 0 2006.189.08:07:10.39#ibcon#about to read 5, iclass 26, count 0 2006.189.08:07:10.39#ibcon#read 5, iclass 26, count 0 2006.189.08:07:10.39#ibcon#about to read 6, iclass 26, count 0 2006.189.08:07:10.39#ibcon#read 6, iclass 26, count 0 2006.189.08:07:10.39#ibcon#end of sib2, iclass 26, count 0 2006.189.08:07:10.39#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:07:10.39#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:07:10.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:07:10.39#ibcon#*before write, iclass 26, count 0 2006.189.08:07:10.39#ibcon#enter sib2, iclass 26, count 0 2006.189.08:07:10.39#ibcon#flushed, iclass 26, count 0 2006.189.08:07:10.39#ibcon#about to write, iclass 26, count 0 2006.189.08:07:10.39#ibcon#wrote, iclass 26, count 0 2006.189.08:07:10.39#ibcon#about to read 3, iclass 26, count 0 2006.189.08:07:10.43#ibcon#read 3, iclass 26, count 0 2006.189.08:07:10.43#ibcon#about to read 4, iclass 26, count 0 2006.189.08:07:10.43#ibcon#read 4, iclass 26, count 0 2006.189.08:07:10.43#ibcon#about to read 5, iclass 26, count 0 2006.189.08:07:10.43#ibcon#read 5, iclass 26, count 0 2006.189.08:07:10.43#ibcon#about to read 6, iclass 26, count 0 2006.189.08:07:10.43#ibcon#read 6, iclass 26, count 0 2006.189.08:07:10.43#ibcon#end of sib2, iclass 26, count 0 2006.189.08:07:10.43#ibcon#*after write, iclass 26, count 0 2006.189.08:07:10.43#ibcon#*before return 0, iclass 26, count 0 2006.189.08:07:10.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:07:10.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:07:10.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:07:10.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:07:10.43$vc4f8/va=8,6 2006.189.08:07:10.43#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.08:07:10.43#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.08:07:10.43#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:10.43#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:07:10.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:07:10.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:07:10.49#ibcon#enter wrdev, iclass 28, count 2 2006.189.08:07:10.49#ibcon#first serial, iclass 28, count 2 2006.189.08:07:10.49#ibcon#enter sib2, iclass 28, count 2 2006.189.08:07:10.49#ibcon#flushed, iclass 28, count 2 2006.189.08:07:10.49#ibcon#about to write, iclass 28, count 2 2006.189.08:07:10.49#ibcon#wrote, iclass 28, count 2 2006.189.08:07:10.49#ibcon#about to read 3, iclass 28, count 2 2006.189.08:07:10.51#ibcon#read 3, iclass 28, count 2 2006.189.08:07:10.51#ibcon#about to read 4, iclass 28, count 2 2006.189.08:07:10.51#ibcon#read 4, iclass 28, count 2 2006.189.08:07:10.51#ibcon#about to read 5, iclass 28, count 2 2006.189.08:07:10.51#ibcon#read 5, iclass 28, count 2 2006.189.08:07:10.51#ibcon#about to read 6, iclass 28, count 2 2006.189.08:07:10.51#ibcon#read 6, iclass 28, count 2 2006.189.08:07:10.51#ibcon#end of sib2, iclass 28, count 2 2006.189.08:07:10.51#ibcon#*mode == 0, iclass 28, count 2 2006.189.08:07:10.51#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.08:07:10.51#ibcon#[25=AT08-06\r\n] 2006.189.08:07:10.51#ibcon#*before write, iclass 28, count 2 2006.189.08:07:10.51#ibcon#enter sib2, iclass 28, count 2 2006.189.08:07:10.51#ibcon#flushed, iclass 28, count 2 2006.189.08:07:10.51#ibcon#about to write, iclass 28, count 2 2006.189.08:07:10.51#ibcon#wrote, iclass 28, count 2 2006.189.08:07:10.51#ibcon#about to read 3, iclass 28, count 2 2006.189.08:07:10.54#ibcon#read 3, iclass 28, count 2 2006.189.08:07:10.54#ibcon#about to read 4, iclass 28, count 2 2006.189.08:07:10.54#ibcon#read 4, iclass 28, count 2 2006.189.08:07:10.54#ibcon#about to read 5, iclass 28, count 2 2006.189.08:07:10.54#ibcon#read 5, iclass 28, count 2 2006.189.08:07:10.54#ibcon#about to read 6, iclass 28, count 2 2006.189.08:07:10.54#ibcon#read 6, iclass 28, count 2 2006.189.08:07:10.54#ibcon#end of sib2, iclass 28, count 2 2006.189.08:07:10.54#ibcon#*after write, iclass 28, count 2 2006.189.08:07:10.54#ibcon#*before return 0, iclass 28, count 2 2006.189.08:07:10.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:07:10.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:07:10.54#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.08:07:10.54#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:10.54#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:07:10.66#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:07:10.66#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:07:10.66#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:07:10.66#ibcon#first serial, iclass 28, count 0 2006.189.08:07:10.66#ibcon#enter sib2, iclass 28, count 0 2006.189.08:07:10.66#ibcon#flushed, iclass 28, count 0 2006.189.08:07:10.66#ibcon#about to write, iclass 28, count 0 2006.189.08:07:10.66#ibcon#wrote, iclass 28, count 0 2006.189.08:07:10.66#ibcon#about to read 3, iclass 28, count 0 2006.189.08:07:10.68#ibcon#read 3, iclass 28, count 0 2006.189.08:07:10.68#ibcon#about to read 4, iclass 28, count 0 2006.189.08:07:10.68#ibcon#read 4, iclass 28, count 0 2006.189.08:07:10.68#ibcon#about to read 5, iclass 28, count 0 2006.189.08:07:10.68#ibcon#read 5, iclass 28, count 0 2006.189.08:07:10.68#ibcon#about to read 6, iclass 28, count 0 2006.189.08:07:10.68#ibcon#read 6, iclass 28, count 0 2006.189.08:07:10.68#ibcon#end of sib2, iclass 28, count 0 2006.189.08:07:10.68#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:07:10.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:07:10.68#ibcon#[25=USB\r\n] 2006.189.08:07:10.68#ibcon#*before write, iclass 28, count 0 2006.189.08:07:10.68#ibcon#enter sib2, iclass 28, count 0 2006.189.08:07:10.68#ibcon#flushed, iclass 28, count 0 2006.189.08:07:10.68#ibcon#about to write, iclass 28, count 0 2006.189.08:07:10.68#ibcon#wrote, iclass 28, count 0 2006.189.08:07:10.68#ibcon#about to read 3, iclass 28, count 0 2006.189.08:07:10.71#ibcon#read 3, iclass 28, count 0 2006.189.08:07:10.71#ibcon#about to read 4, iclass 28, count 0 2006.189.08:07:10.71#ibcon#read 4, iclass 28, count 0 2006.189.08:07:10.71#ibcon#about to read 5, iclass 28, count 0 2006.189.08:07:10.71#ibcon#read 5, iclass 28, count 0 2006.189.08:07:10.71#ibcon#about to read 6, iclass 28, count 0 2006.189.08:07:10.71#ibcon#read 6, iclass 28, count 0 2006.189.08:07:10.71#ibcon#end of sib2, iclass 28, count 0 2006.189.08:07:10.71#ibcon#*after write, iclass 28, count 0 2006.189.08:07:10.71#ibcon#*before return 0, iclass 28, count 0 2006.189.08:07:10.71#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:07:10.71#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:07:10.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:07:10.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:07:10.71$vc4f8/vblo=1,632.99 2006.189.08:07:10.71#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.08:07:10.71#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.08:07:10.71#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:10.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:07:10.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:07:10.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:07:10.71#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:07:10.71#ibcon#first serial, iclass 30, count 0 2006.189.08:07:10.71#ibcon#enter sib2, iclass 30, count 0 2006.189.08:07:10.71#ibcon#flushed, iclass 30, count 0 2006.189.08:07:10.71#ibcon#about to write, iclass 30, count 0 2006.189.08:07:10.71#ibcon#wrote, iclass 30, count 0 2006.189.08:07:10.71#ibcon#about to read 3, iclass 30, count 0 2006.189.08:07:10.73#ibcon#read 3, iclass 30, count 0 2006.189.08:07:10.73#ibcon#about to read 4, iclass 30, count 0 2006.189.08:07:10.73#ibcon#read 4, iclass 30, count 0 2006.189.08:07:10.73#ibcon#about to read 5, iclass 30, count 0 2006.189.08:07:10.73#ibcon#read 5, iclass 30, count 0 2006.189.08:07:10.73#ibcon#about to read 6, iclass 30, count 0 2006.189.08:07:10.73#ibcon#read 6, iclass 30, count 0 2006.189.08:07:10.73#ibcon#end of sib2, iclass 30, count 0 2006.189.08:07:10.73#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:07:10.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:07:10.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:07:10.73#ibcon#*before write, iclass 30, count 0 2006.189.08:07:10.73#ibcon#enter sib2, iclass 30, count 0 2006.189.08:07:10.73#ibcon#flushed, iclass 30, count 0 2006.189.08:07:10.73#ibcon#about to write, iclass 30, count 0 2006.189.08:07:10.73#ibcon#wrote, iclass 30, count 0 2006.189.08:07:10.73#ibcon#about to read 3, iclass 30, count 0 2006.189.08:07:10.77#ibcon#read 3, iclass 30, count 0 2006.189.08:07:10.77#ibcon#about to read 4, iclass 30, count 0 2006.189.08:07:10.77#ibcon#read 4, iclass 30, count 0 2006.189.08:07:10.77#ibcon#about to read 5, iclass 30, count 0 2006.189.08:07:10.77#ibcon#read 5, iclass 30, count 0 2006.189.08:07:10.77#ibcon#about to read 6, iclass 30, count 0 2006.189.08:07:10.77#ibcon#read 6, iclass 30, count 0 2006.189.08:07:10.77#ibcon#end of sib2, iclass 30, count 0 2006.189.08:07:10.77#ibcon#*after write, iclass 30, count 0 2006.189.08:07:10.77#ibcon#*before return 0, iclass 30, count 0 2006.189.08:07:10.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:07:10.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:07:10.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:07:10.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:07:10.77$vc4f8/vb=1,4 2006.189.08:07:10.77#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.08:07:10.77#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.08:07:10.77#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:10.77#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:07:10.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:07:10.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:07:10.77#ibcon#enter wrdev, iclass 32, count 2 2006.189.08:07:10.77#ibcon#first serial, iclass 32, count 2 2006.189.08:07:10.77#ibcon#enter sib2, iclass 32, count 2 2006.189.08:07:10.77#ibcon#flushed, iclass 32, count 2 2006.189.08:07:10.77#ibcon#about to write, iclass 32, count 2 2006.189.08:07:10.77#ibcon#wrote, iclass 32, count 2 2006.189.08:07:10.77#ibcon#about to read 3, iclass 32, count 2 2006.189.08:07:10.79#ibcon#read 3, iclass 32, count 2 2006.189.08:07:10.79#ibcon#about to read 4, iclass 32, count 2 2006.189.08:07:10.79#ibcon#read 4, iclass 32, count 2 2006.189.08:07:10.79#ibcon#about to read 5, iclass 32, count 2 2006.189.08:07:10.79#ibcon#read 5, iclass 32, count 2 2006.189.08:07:10.79#ibcon#about to read 6, iclass 32, count 2 2006.189.08:07:10.79#ibcon#read 6, iclass 32, count 2 2006.189.08:07:10.79#ibcon#end of sib2, iclass 32, count 2 2006.189.08:07:10.79#ibcon#*mode == 0, iclass 32, count 2 2006.189.08:07:10.79#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.08:07:10.79#ibcon#[27=AT01-04\r\n] 2006.189.08:07:10.79#ibcon#*before write, iclass 32, count 2 2006.189.08:07:10.79#ibcon#enter sib2, iclass 32, count 2 2006.189.08:07:10.79#ibcon#flushed, iclass 32, count 2 2006.189.08:07:10.79#ibcon#about to write, iclass 32, count 2 2006.189.08:07:10.79#ibcon#wrote, iclass 32, count 2 2006.189.08:07:10.79#ibcon#about to read 3, iclass 32, count 2 2006.189.08:07:10.82#ibcon#read 3, iclass 32, count 2 2006.189.08:07:10.82#ibcon#about to read 4, iclass 32, count 2 2006.189.08:07:10.82#ibcon#read 4, iclass 32, count 2 2006.189.08:07:10.82#ibcon#about to read 5, iclass 32, count 2 2006.189.08:07:10.82#ibcon#read 5, iclass 32, count 2 2006.189.08:07:10.82#ibcon#about to read 6, iclass 32, count 2 2006.189.08:07:10.82#ibcon#read 6, iclass 32, count 2 2006.189.08:07:10.82#ibcon#end of sib2, iclass 32, count 2 2006.189.08:07:10.82#ibcon#*after write, iclass 32, count 2 2006.189.08:07:10.82#ibcon#*before return 0, iclass 32, count 2 2006.189.08:07:10.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:07:10.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:07:10.82#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.08:07:10.82#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:10.82#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:07:10.94#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:07:10.94#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:07:10.94#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:07:10.94#ibcon#first serial, iclass 32, count 0 2006.189.08:07:10.94#ibcon#enter sib2, iclass 32, count 0 2006.189.08:07:10.94#ibcon#flushed, iclass 32, count 0 2006.189.08:07:10.94#ibcon#about to write, iclass 32, count 0 2006.189.08:07:10.94#ibcon#wrote, iclass 32, count 0 2006.189.08:07:10.94#ibcon#about to read 3, iclass 32, count 0 2006.189.08:07:10.96#ibcon#read 3, iclass 32, count 0 2006.189.08:07:10.96#ibcon#about to read 4, iclass 32, count 0 2006.189.08:07:10.96#ibcon#read 4, iclass 32, count 0 2006.189.08:07:10.96#ibcon#about to read 5, iclass 32, count 0 2006.189.08:07:10.96#ibcon#read 5, iclass 32, count 0 2006.189.08:07:10.96#ibcon#about to read 6, iclass 32, count 0 2006.189.08:07:10.96#ibcon#read 6, iclass 32, count 0 2006.189.08:07:10.96#ibcon#end of sib2, iclass 32, count 0 2006.189.08:07:10.96#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:07:10.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:07:10.96#ibcon#[27=USB\r\n] 2006.189.08:07:10.96#ibcon#*before write, iclass 32, count 0 2006.189.08:07:10.96#ibcon#enter sib2, iclass 32, count 0 2006.189.08:07:10.96#ibcon#flushed, iclass 32, count 0 2006.189.08:07:10.96#ibcon#about to write, iclass 32, count 0 2006.189.08:07:10.96#ibcon#wrote, iclass 32, count 0 2006.189.08:07:10.96#ibcon#about to read 3, iclass 32, count 0 2006.189.08:07:10.99#ibcon#read 3, iclass 32, count 0 2006.189.08:07:10.99#ibcon#about to read 4, iclass 32, count 0 2006.189.08:07:10.99#ibcon#read 4, iclass 32, count 0 2006.189.08:07:10.99#ibcon#about to read 5, iclass 32, count 0 2006.189.08:07:10.99#ibcon#read 5, iclass 32, count 0 2006.189.08:07:10.99#ibcon#about to read 6, iclass 32, count 0 2006.189.08:07:10.99#ibcon#read 6, iclass 32, count 0 2006.189.08:07:10.99#ibcon#end of sib2, iclass 32, count 0 2006.189.08:07:10.99#ibcon#*after write, iclass 32, count 0 2006.189.08:07:10.99#ibcon#*before return 0, iclass 32, count 0 2006.189.08:07:10.99#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:07:10.99#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:07:10.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:07:10.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:07:10.99$vc4f8/vblo=2,640.99 2006.189.08:07:10.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.08:07:10.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.08:07:10.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:10.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:10.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:10.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:10.99#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:07:10.99#ibcon#first serial, iclass 34, count 0 2006.189.08:07:10.99#ibcon#enter sib2, iclass 34, count 0 2006.189.08:07:10.99#ibcon#flushed, iclass 34, count 0 2006.189.08:07:10.99#ibcon#about to write, iclass 34, count 0 2006.189.08:07:10.99#ibcon#wrote, iclass 34, count 0 2006.189.08:07:10.99#ibcon#about to read 3, iclass 34, count 0 2006.189.08:07:11.01#ibcon#read 3, iclass 34, count 0 2006.189.08:07:11.01#ibcon#about to read 4, iclass 34, count 0 2006.189.08:07:11.01#ibcon#read 4, iclass 34, count 0 2006.189.08:07:11.01#ibcon#about to read 5, iclass 34, count 0 2006.189.08:07:11.01#ibcon#read 5, iclass 34, count 0 2006.189.08:07:11.01#ibcon#about to read 6, iclass 34, count 0 2006.189.08:07:11.01#ibcon#read 6, iclass 34, count 0 2006.189.08:07:11.01#ibcon#end of sib2, iclass 34, count 0 2006.189.08:07:11.01#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:07:11.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:07:11.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:07:11.01#ibcon#*before write, iclass 34, count 0 2006.189.08:07:11.01#ibcon#enter sib2, iclass 34, count 0 2006.189.08:07:11.01#ibcon#flushed, iclass 34, count 0 2006.189.08:07:11.01#ibcon#about to write, iclass 34, count 0 2006.189.08:07:11.01#ibcon#wrote, iclass 34, count 0 2006.189.08:07:11.01#ibcon#about to read 3, iclass 34, count 0 2006.189.08:07:11.05#ibcon#read 3, iclass 34, count 0 2006.189.08:07:11.05#ibcon#about to read 4, iclass 34, count 0 2006.189.08:07:11.05#ibcon#read 4, iclass 34, count 0 2006.189.08:07:11.05#ibcon#about to read 5, iclass 34, count 0 2006.189.08:07:11.05#ibcon#read 5, iclass 34, count 0 2006.189.08:07:11.05#ibcon#about to read 6, iclass 34, count 0 2006.189.08:07:11.05#ibcon#read 6, iclass 34, count 0 2006.189.08:07:11.05#ibcon#end of sib2, iclass 34, count 0 2006.189.08:07:11.05#ibcon#*after write, iclass 34, count 0 2006.189.08:07:11.05#ibcon#*before return 0, iclass 34, count 0 2006.189.08:07:11.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:11.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:07:11.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:07:11.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:07:11.05$vc4f8/vb=2,4 2006.189.08:07:11.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.08:07:11.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.08:07:11.05#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:11.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:11.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:11.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:11.11#ibcon#enter wrdev, iclass 36, count 2 2006.189.08:07:11.11#ibcon#first serial, iclass 36, count 2 2006.189.08:07:11.11#ibcon#enter sib2, iclass 36, count 2 2006.189.08:07:11.11#ibcon#flushed, iclass 36, count 2 2006.189.08:07:11.11#ibcon#about to write, iclass 36, count 2 2006.189.08:07:11.11#ibcon#wrote, iclass 36, count 2 2006.189.08:07:11.11#ibcon#about to read 3, iclass 36, count 2 2006.189.08:07:11.13#ibcon#read 3, iclass 36, count 2 2006.189.08:07:11.13#ibcon#about to read 4, iclass 36, count 2 2006.189.08:07:11.13#ibcon#read 4, iclass 36, count 2 2006.189.08:07:11.13#ibcon#about to read 5, iclass 36, count 2 2006.189.08:07:11.13#ibcon#read 5, iclass 36, count 2 2006.189.08:07:11.13#ibcon#about to read 6, iclass 36, count 2 2006.189.08:07:11.13#ibcon#read 6, iclass 36, count 2 2006.189.08:07:11.13#ibcon#end of sib2, iclass 36, count 2 2006.189.08:07:11.13#ibcon#*mode == 0, iclass 36, count 2 2006.189.08:07:11.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.08:07:11.13#ibcon#[27=AT02-04\r\n] 2006.189.08:07:11.13#ibcon#*before write, iclass 36, count 2 2006.189.08:07:11.13#ibcon#enter sib2, iclass 36, count 2 2006.189.08:07:11.13#ibcon#flushed, iclass 36, count 2 2006.189.08:07:11.13#ibcon#about to write, iclass 36, count 2 2006.189.08:07:11.13#ibcon#wrote, iclass 36, count 2 2006.189.08:07:11.13#ibcon#about to read 3, iclass 36, count 2 2006.189.08:07:11.16#ibcon#read 3, iclass 36, count 2 2006.189.08:07:11.16#ibcon#about to read 4, iclass 36, count 2 2006.189.08:07:11.16#ibcon#read 4, iclass 36, count 2 2006.189.08:07:11.16#ibcon#about to read 5, iclass 36, count 2 2006.189.08:07:11.16#ibcon#read 5, iclass 36, count 2 2006.189.08:07:11.16#ibcon#about to read 6, iclass 36, count 2 2006.189.08:07:11.16#ibcon#read 6, iclass 36, count 2 2006.189.08:07:11.16#ibcon#end of sib2, iclass 36, count 2 2006.189.08:07:11.16#ibcon#*after write, iclass 36, count 2 2006.189.08:07:11.16#ibcon#*before return 0, iclass 36, count 2 2006.189.08:07:11.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:11.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:07:11.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.08:07:11.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:11.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:11.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:11.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:11.28#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:07:11.28#ibcon#first serial, iclass 36, count 0 2006.189.08:07:11.28#ibcon#enter sib2, iclass 36, count 0 2006.189.08:07:11.28#ibcon#flushed, iclass 36, count 0 2006.189.08:07:11.28#ibcon#about to write, iclass 36, count 0 2006.189.08:07:11.28#ibcon#wrote, iclass 36, count 0 2006.189.08:07:11.28#ibcon#about to read 3, iclass 36, count 0 2006.189.08:07:11.30#ibcon#read 3, iclass 36, count 0 2006.189.08:07:11.30#ibcon#about to read 4, iclass 36, count 0 2006.189.08:07:11.30#ibcon#read 4, iclass 36, count 0 2006.189.08:07:11.30#ibcon#about to read 5, iclass 36, count 0 2006.189.08:07:11.30#ibcon#read 5, iclass 36, count 0 2006.189.08:07:11.30#ibcon#about to read 6, iclass 36, count 0 2006.189.08:07:11.30#ibcon#read 6, iclass 36, count 0 2006.189.08:07:11.30#ibcon#end of sib2, iclass 36, count 0 2006.189.08:07:11.30#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:07:11.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:07:11.30#ibcon#[27=USB\r\n] 2006.189.08:07:11.30#ibcon#*before write, iclass 36, count 0 2006.189.08:07:11.30#ibcon#enter sib2, iclass 36, count 0 2006.189.08:07:11.30#ibcon#flushed, iclass 36, count 0 2006.189.08:07:11.30#ibcon#about to write, iclass 36, count 0 2006.189.08:07:11.30#ibcon#wrote, iclass 36, count 0 2006.189.08:07:11.30#ibcon#about to read 3, iclass 36, count 0 2006.189.08:07:11.33#ibcon#read 3, iclass 36, count 0 2006.189.08:07:11.33#ibcon#about to read 4, iclass 36, count 0 2006.189.08:07:11.33#ibcon#read 4, iclass 36, count 0 2006.189.08:07:11.33#ibcon#about to read 5, iclass 36, count 0 2006.189.08:07:11.33#ibcon#read 5, iclass 36, count 0 2006.189.08:07:11.33#ibcon#about to read 6, iclass 36, count 0 2006.189.08:07:11.33#ibcon#read 6, iclass 36, count 0 2006.189.08:07:11.33#ibcon#end of sib2, iclass 36, count 0 2006.189.08:07:11.33#ibcon#*after write, iclass 36, count 0 2006.189.08:07:11.33#ibcon#*before return 0, iclass 36, count 0 2006.189.08:07:11.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:11.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:07:11.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:07:11.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:07:11.33$vc4f8/vblo=3,656.99 2006.189.08:07:11.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.08:07:11.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.08:07:11.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:11.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:11.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:11.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:11.33#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:07:11.33#ibcon#first serial, iclass 38, count 0 2006.189.08:07:11.33#ibcon#enter sib2, iclass 38, count 0 2006.189.08:07:11.33#ibcon#flushed, iclass 38, count 0 2006.189.08:07:11.33#ibcon#about to write, iclass 38, count 0 2006.189.08:07:11.33#ibcon#wrote, iclass 38, count 0 2006.189.08:07:11.33#ibcon#about to read 3, iclass 38, count 0 2006.189.08:07:11.35#ibcon#read 3, iclass 38, count 0 2006.189.08:07:11.35#ibcon#about to read 4, iclass 38, count 0 2006.189.08:07:11.35#ibcon#read 4, iclass 38, count 0 2006.189.08:07:11.35#ibcon#about to read 5, iclass 38, count 0 2006.189.08:07:11.35#ibcon#read 5, iclass 38, count 0 2006.189.08:07:11.35#ibcon#about to read 6, iclass 38, count 0 2006.189.08:07:11.35#ibcon#read 6, iclass 38, count 0 2006.189.08:07:11.35#ibcon#end of sib2, iclass 38, count 0 2006.189.08:07:11.35#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:07:11.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:07:11.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:07:11.35#ibcon#*before write, iclass 38, count 0 2006.189.08:07:11.35#ibcon#enter sib2, iclass 38, count 0 2006.189.08:07:11.35#ibcon#flushed, iclass 38, count 0 2006.189.08:07:11.35#ibcon#about to write, iclass 38, count 0 2006.189.08:07:11.35#ibcon#wrote, iclass 38, count 0 2006.189.08:07:11.35#ibcon#about to read 3, iclass 38, count 0 2006.189.08:07:11.39#ibcon#read 3, iclass 38, count 0 2006.189.08:07:11.39#ibcon#about to read 4, iclass 38, count 0 2006.189.08:07:11.39#ibcon#read 4, iclass 38, count 0 2006.189.08:07:11.39#ibcon#about to read 5, iclass 38, count 0 2006.189.08:07:11.39#ibcon#read 5, iclass 38, count 0 2006.189.08:07:11.39#ibcon#about to read 6, iclass 38, count 0 2006.189.08:07:11.39#ibcon#read 6, iclass 38, count 0 2006.189.08:07:11.39#ibcon#end of sib2, iclass 38, count 0 2006.189.08:07:11.39#ibcon#*after write, iclass 38, count 0 2006.189.08:07:11.39#ibcon#*before return 0, iclass 38, count 0 2006.189.08:07:11.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:11.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:07:11.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:07:11.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:07:11.39$vc4f8/vb=3,4 2006.189.08:07:11.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.08:07:11.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.08:07:11.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:11.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:11.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:11.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:11.45#ibcon#enter wrdev, iclass 40, count 2 2006.189.08:07:11.45#ibcon#first serial, iclass 40, count 2 2006.189.08:07:11.45#ibcon#enter sib2, iclass 40, count 2 2006.189.08:07:11.45#ibcon#flushed, iclass 40, count 2 2006.189.08:07:11.45#ibcon#about to write, iclass 40, count 2 2006.189.08:07:11.45#ibcon#wrote, iclass 40, count 2 2006.189.08:07:11.45#ibcon#about to read 3, iclass 40, count 2 2006.189.08:07:11.47#ibcon#read 3, iclass 40, count 2 2006.189.08:07:11.47#ibcon#about to read 4, iclass 40, count 2 2006.189.08:07:11.47#ibcon#read 4, iclass 40, count 2 2006.189.08:07:11.47#ibcon#about to read 5, iclass 40, count 2 2006.189.08:07:11.47#ibcon#read 5, iclass 40, count 2 2006.189.08:07:11.47#ibcon#about to read 6, iclass 40, count 2 2006.189.08:07:11.47#ibcon#read 6, iclass 40, count 2 2006.189.08:07:11.47#ibcon#end of sib2, iclass 40, count 2 2006.189.08:07:11.47#ibcon#*mode == 0, iclass 40, count 2 2006.189.08:07:11.47#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.08:07:11.47#ibcon#[27=AT03-04\r\n] 2006.189.08:07:11.47#ibcon#*before write, iclass 40, count 2 2006.189.08:07:11.47#ibcon#enter sib2, iclass 40, count 2 2006.189.08:07:11.47#ibcon#flushed, iclass 40, count 2 2006.189.08:07:11.47#ibcon#about to write, iclass 40, count 2 2006.189.08:07:11.47#ibcon#wrote, iclass 40, count 2 2006.189.08:07:11.47#ibcon#about to read 3, iclass 40, count 2 2006.189.08:07:11.50#ibcon#read 3, iclass 40, count 2 2006.189.08:07:11.50#ibcon#about to read 4, iclass 40, count 2 2006.189.08:07:11.50#ibcon#read 4, iclass 40, count 2 2006.189.08:07:11.50#ibcon#about to read 5, iclass 40, count 2 2006.189.08:07:11.50#ibcon#read 5, iclass 40, count 2 2006.189.08:07:11.50#ibcon#about to read 6, iclass 40, count 2 2006.189.08:07:11.50#ibcon#read 6, iclass 40, count 2 2006.189.08:07:11.50#ibcon#end of sib2, iclass 40, count 2 2006.189.08:07:11.50#ibcon#*after write, iclass 40, count 2 2006.189.08:07:11.50#ibcon#*before return 0, iclass 40, count 2 2006.189.08:07:11.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:11.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:07:11.50#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.08:07:11.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:11.50#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:11.62#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:11.62#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:11.62#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:07:11.62#ibcon#first serial, iclass 40, count 0 2006.189.08:07:11.62#ibcon#enter sib2, iclass 40, count 0 2006.189.08:07:11.62#ibcon#flushed, iclass 40, count 0 2006.189.08:07:11.62#ibcon#about to write, iclass 40, count 0 2006.189.08:07:11.62#ibcon#wrote, iclass 40, count 0 2006.189.08:07:11.62#ibcon#about to read 3, iclass 40, count 0 2006.189.08:07:11.64#ibcon#read 3, iclass 40, count 0 2006.189.08:07:11.64#ibcon#about to read 4, iclass 40, count 0 2006.189.08:07:11.64#ibcon#read 4, iclass 40, count 0 2006.189.08:07:11.64#ibcon#about to read 5, iclass 40, count 0 2006.189.08:07:11.64#ibcon#read 5, iclass 40, count 0 2006.189.08:07:11.64#ibcon#about to read 6, iclass 40, count 0 2006.189.08:07:11.64#ibcon#read 6, iclass 40, count 0 2006.189.08:07:11.64#ibcon#end of sib2, iclass 40, count 0 2006.189.08:07:11.64#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:07:11.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:07:11.64#ibcon#[27=USB\r\n] 2006.189.08:07:11.64#ibcon#*before write, iclass 40, count 0 2006.189.08:07:11.64#ibcon#enter sib2, iclass 40, count 0 2006.189.08:07:11.64#ibcon#flushed, iclass 40, count 0 2006.189.08:07:11.64#ibcon#about to write, iclass 40, count 0 2006.189.08:07:11.64#ibcon#wrote, iclass 40, count 0 2006.189.08:07:11.64#ibcon#about to read 3, iclass 40, count 0 2006.189.08:07:11.67#ibcon#read 3, iclass 40, count 0 2006.189.08:07:11.67#ibcon#about to read 4, iclass 40, count 0 2006.189.08:07:11.67#ibcon#read 4, iclass 40, count 0 2006.189.08:07:11.67#ibcon#about to read 5, iclass 40, count 0 2006.189.08:07:11.67#ibcon#read 5, iclass 40, count 0 2006.189.08:07:11.67#ibcon#about to read 6, iclass 40, count 0 2006.189.08:07:11.67#ibcon#read 6, iclass 40, count 0 2006.189.08:07:11.67#ibcon#end of sib2, iclass 40, count 0 2006.189.08:07:11.67#ibcon#*after write, iclass 40, count 0 2006.189.08:07:11.67#ibcon#*before return 0, iclass 40, count 0 2006.189.08:07:11.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:11.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:07:11.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:07:11.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:07:11.67$vc4f8/vblo=4,712.99 2006.189.08:07:11.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.08:07:11.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.08:07:11.67#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:11.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:11.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:11.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:11.67#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:07:11.67#ibcon#first serial, iclass 4, count 0 2006.189.08:07:11.67#ibcon#enter sib2, iclass 4, count 0 2006.189.08:07:11.67#ibcon#flushed, iclass 4, count 0 2006.189.08:07:11.67#ibcon#about to write, iclass 4, count 0 2006.189.08:07:11.67#ibcon#wrote, iclass 4, count 0 2006.189.08:07:11.67#ibcon#about to read 3, iclass 4, count 0 2006.189.08:07:11.69#ibcon#read 3, iclass 4, count 0 2006.189.08:07:11.69#ibcon#about to read 4, iclass 4, count 0 2006.189.08:07:11.69#ibcon#read 4, iclass 4, count 0 2006.189.08:07:11.69#ibcon#about to read 5, iclass 4, count 0 2006.189.08:07:11.69#ibcon#read 5, iclass 4, count 0 2006.189.08:07:11.69#ibcon#about to read 6, iclass 4, count 0 2006.189.08:07:11.69#ibcon#read 6, iclass 4, count 0 2006.189.08:07:11.69#ibcon#end of sib2, iclass 4, count 0 2006.189.08:07:11.69#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:07:11.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:07:11.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:07:11.69#ibcon#*before write, iclass 4, count 0 2006.189.08:07:11.69#ibcon#enter sib2, iclass 4, count 0 2006.189.08:07:11.69#ibcon#flushed, iclass 4, count 0 2006.189.08:07:11.69#ibcon#about to write, iclass 4, count 0 2006.189.08:07:11.69#ibcon#wrote, iclass 4, count 0 2006.189.08:07:11.69#ibcon#about to read 3, iclass 4, count 0 2006.189.08:07:11.73#ibcon#read 3, iclass 4, count 0 2006.189.08:07:11.73#ibcon#about to read 4, iclass 4, count 0 2006.189.08:07:11.73#ibcon#read 4, iclass 4, count 0 2006.189.08:07:11.73#ibcon#about to read 5, iclass 4, count 0 2006.189.08:07:11.73#ibcon#read 5, iclass 4, count 0 2006.189.08:07:11.73#ibcon#about to read 6, iclass 4, count 0 2006.189.08:07:11.73#ibcon#read 6, iclass 4, count 0 2006.189.08:07:11.73#ibcon#end of sib2, iclass 4, count 0 2006.189.08:07:11.73#ibcon#*after write, iclass 4, count 0 2006.189.08:07:11.73#ibcon#*before return 0, iclass 4, count 0 2006.189.08:07:11.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:11.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:07:11.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:07:11.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:07:11.73$vc4f8/vb=4,4 2006.189.08:07:11.73#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.08:07:11.73#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.08:07:11.73#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:11.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:11.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:11.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:11.79#ibcon#enter wrdev, iclass 6, count 2 2006.189.08:07:11.79#ibcon#first serial, iclass 6, count 2 2006.189.08:07:11.79#ibcon#enter sib2, iclass 6, count 2 2006.189.08:07:11.79#ibcon#flushed, iclass 6, count 2 2006.189.08:07:11.79#ibcon#about to write, iclass 6, count 2 2006.189.08:07:11.79#ibcon#wrote, iclass 6, count 2 2006.189.08:07:11.79#ibcon#about to read 3, iclass 6, count 2 2006.189.08:07:11.81#ibcon#read 3, iclass 6, count 2 2006.189.08:07:11.81#ibcon#about to read 4, iclass 6, count 2 2006.189.08:07:11.81#ibcon#read 4, iclass 6, count 2 2006.189.08:07:11.81#ibcon#about to read 5, iclass 6, count 2 2006.189.08:07:11.81#ibcon#read 5, iclass 6, count 2 2006.189.08:07:11.81#ibcon#about to read 6, iclass 6, count 2 2006.189.08:07:11.81#ibcon#read 6, iclass 6, count 2 2006.189.08:07:11.81#ibcon#end of sib2, iclass 6, count 2 2006.189.08:07:11.81#ibcon#*mode == 0, iclass 6, count 2 2006.189.08:07:11.81#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.08:07:11.81#ibcon#[27=AT04-04\r\n] 2006.189.08:07:11.81#ibcon#*before write, iclass 6, count 2 2006.189.08:07:11.81#ibcon#enter sib2, iclass 6, count 2 2006.189.08:07:11.81#ibcon#flushed, iclass 6, count 2 2006.189.08:07:11.81#ibcon#about to write, iclass 6, count 2 2006.189.08:07:11.81#ibcon#wrote, iclass 6, count 2 2006.189.08:07:11.81#ibcon#about to read 3, iclass 6, count 2 2006.189.08:07:11.84#ibcon#read 3, iclass 6, count 2 2006.189.08:07:11.84#ibcon#about to read 4, iclass 6, count 2 2006.189.08:07:11.84#ibcon#read 4, iclass 6, count 2 2006.189.08:07:11.84#ibcon#about to read 5, iclass 6, count 2 2006.189.08:07:11.84#ibcon#read 5, iclass 6, count 2 2006.189.08:07:11.84#ibcon#about to read 6, iclass 6, count 2 2006.189.08:07:11.84#ibcon#read 6, iclass 6, count 2 2006.189.08:07:11.84#ibcon#end of sib2, iclass 6, count 2 2006.189.08:07:11.84#ibcon#*after write, iclass 6, count 2 2006.189.08:07:11.84#ibcon#*before return 0, iclass 6, count 2 2006.189.08:07:11.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:11.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:07:11.84#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.08:07:11.84#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:11.84#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:11.96#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:11.96#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:11.96#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:07:11.96#ibcon#first serial, iclass 6, count 0 2006.189.08:07:11.96#ibcon#enter sib2, iclass 6, count 0 2006.189.08:07:11.96#ibcon#flushed, iclass 6, count 0 2006.189.08:07:11.96#ibcon#about to write, iclass 6, count 0 2006.189.08:07:11.96#ibcon#wrote, iclass 6, count 0 2006.189.08:07:11.96#ibcon#about to read 3, iclass 6, count 0 2006.189.08:07:11.98#ibcon#read 3, iclass 6, count 0 2006.189.08:07:11.98#ibcon#about to read 4, iclass 6, count 0 2006.189.08:07:11.98#ibcon#read 4, iclass 6, count 0 2006.189.08:07:11.98#ibcon#about to read 5, iclass 6, count 0 2006.189.08:07:11.98#ibcon#read 5, iclass 6, count 0 2006.189.08:07:11.98#ibcon#about to read 6, iclass 6, count 0 2006.189.08:07:11.98#ibcon#read 6, iclass 6, count 0 2006.189.08:07:11.98#ibcon#end of sib2, iclass 6, count 0 2006.189.08:07:11.98#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:07:11.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:07:11.98#ibcon#[27=USB\r\n] 2006.189.08:07:11.98#ibcon#*before write, iclass 6, count 0 2006.189.08:07:11.98#ibcon#enter sib2, iclass 6, count 0 2006.189.08:07:11.98#ibcon#flushed, iclass 6, count 0 2006.189.08:07:11.98#ibcon#about to write, iclass 6, count 0 2006.189.08:07:11.98#ibcon#wrote, iclass 6, count 0 2006.189.08:07:11.98#ibcon#about to read 3, iclass 6, count 0 2006.189.08:07:12.01#ibcon#read 3, iclass 6, count 0 2006.189.08:07:12.01#ibcon#about to read 4, iclass 6, count 0 2006.189.08:07:12.01#ibcon#read 4, iclass 6, count 0 2006.189.08:07:12.01#ibcon#about to read 5, iclass 6, count 0 2006.189.08:07:12.01#ibcon#read 5, iclass 6, count 0 2006.189.08:07:12.01#ibcon#about to read 6, iclass 6, count 0 2006.189.08:07:12.01#ibcon#read 6, iclass 6, count 0 2006.189.08:07:12.01#ibcon#end of sib2, iclass 6, count 0 2006.189.08:07:12.01#ibcon#*after write, iclass 6, count 0 2006.189.08:07:12.01#ibcon#*before return 0, iclass 6, count 0 2006.189.08:07:12.01#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:12.01#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:07:12.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:07:12.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:07:12.01$vc4f8/vblo=5,744.99 2006.189.08:07:12.01#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.08:07:12.01#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.08:07:12.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:12.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:12.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:12.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:12.01#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:07:12.01#ibcon#first serial, iclass 10, count 0 2006.189.08:07:12.01#ibcon#enter sib2, iclass 10, count 0 2006.189.08:07:12.01#ibcon#flushed, iclass 10, count 0 2006.189.08:07:12.01#ibcon#about to write, iclass 10, count 0 2006.189.08:07:12.01#ibcon#wrote, iclass 10, count 0 2006.189.08:07:12.01#ibcon#about to read 3, iclass 10, count 0 2006.189.08:07:12.03#ibcon#read 3, iclass 10, count 0 2006.189.08:07:12.03#ibcon#about to read 4, iclass 10, count 0 2006.189.08:07:12.03#ibcon#read 4, iclass 10, count 0 2006.189.08:07:12.03#ibcon#about to read 5, iclass 10, count 0 2006.189.08:07:12.03#ibcon#read 5, iclass 10, count 0 2006.189.08:07:12.03#ibcon#about to read 6, iclass 10, count 0 2006.189.08:07:12.03#ibcon#read 6, iclass 10, count 0 2006.189.08:07:12.03#ibcon#end of sib2, iclass 10, count 0 2006.189.08:07:12.03#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:07:12.03#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:07:12.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:07:12.03#ibcon#*before write, iclass 10, count 0 2006.189.08:07:12.03#ibcon#enter sib2, iclass 10, count 0 2006.189.08:07:12.03#ibcon#flushed, iclass 10, count 0 2006.189.08:07:12.03#ibcon#about to write, iclass 10, count 0 2006.189.08:07:12.03#ibcon#wrote, iclass 10, count 0 2006.189.08:07:12.03#ibcon#about to read 3, iclass 10, count 0 2006.189.08:07:12.07#ibcon#read 3, iclass 10, count 0 2006.189.08:07:12.07#ibcon#about to read 4, iclass 10, count 0 2006.189.08:07:12.07#ibcon#read 4, iclass 10, count 0 2006.189.08:07:12.07#ibcon#about to read 5, iclass 10, count 0 2006.189.08:07:12.07#ibcon#read 5, iclass 10, count 0 2006.189.08:07:12.07#ibcon#about to read 6, iclass 10, count 0 2006.189.08:07:12.07#ibcon#read 6, iclass 10, count 0 2006.189.08:07:12.07#ibcon#end of sib2, iclass 10, count 0 2006.189.08:07:12.07#ibcon#*after write, iclass 10, count 0 2006.189.08:07:12.07#ibcon#*before return 0, iclass 10, count 0 2006.189.08:07:12.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:12.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:07:12.07#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:07:12.07#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:07:12.07$vc4f8/vb=5,4 2006.189.08:07:12.07#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.08:07:12.07#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.08:07:12.07#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:12.07#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:12.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:12.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:12.13#ibcon#enter wrdev, iclass 12, count 2 2006.189.08:07:12.13#ibcon#first serial, iclass 12, count 2 2006.189.08:07:12.13#ibcon#enter sib2, iclass 12, count 2 2006.189.08:07:12.13#ibcon#flushed, iclass 12, count 2 2006.189.08:07:12.13#ibcon#about to write, iclass 12, count 2 2006.189.08:07:12.13#ibcon#wrote, iclass 12, count 2 2006.189.08:07:12.13#ibcon#about to read 3, iclass 12, count 2 2006.189.08:07:12.15#ibcon#read 3, iclass 12, count 2 2006.189.08:07:12.15#ibcon#about to read 4, iclass 12, count 2 2006.189.08:07:12.15#ibcon#read 4, iclass 12, count 2 2006.189.08:07:12.15#ibcon#about to read 5, iclass 12, count 2 2006.189.08:07:12.15#ibcon#read 5, iclass 12, count 2 2006.189.08:07:12.15#ibcon#about to read 6, iclass 12, count 2 2006.189.08:07:12.15#ibcon#read 6, iclass 12, count 2 2006.189.08:07:12.15#ibcon#end of sib2, iclass 12, count 2 2006.189.08:07:12.15#ibcon#*mode == 0, iclass 12, count 2 2006.189.08:07:12.15#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.08:07:12.15#ibcon#[27=AT05-04\r\n] 2006.189.08:07:12.15#ibcon#*before write, iclass 12, count 2 2006.189.08:07:12.15#ibcon#enter sib2, iclass 12, count 2 2006.189.08:07:12.15#ibcon#flushed, iclass 12, count 2 2006.189.08:07:12.15#ibcon#about to write, iclass 12, count 2 2006.189.08:07:12.15#ibcon#wrote, iclass 12, count 2 2006.189.08:07:12.15#ibcon#about to read 3, iclass 12, count 2 2006.189.08:07:12.18#ibcon#read 3, iclass 12, count 2 2006.189.08:07:12.18#ibcon#about to read 4, iclass 12, count 2 2006.189.08:07:12.18#ibcon#read 4, iclass 12, count 2 2006.189.08:07:12.18#ibcon#about to read 5, iclass 12, count 2 2006.189.08:07:12.18#ibcon#read 5, iclass 12, count 2 2006.189.08:07:12.18#ibcon#about to read 6, iclass 12, count 2 2006.189.08:07:12.18#ibcon#read 6, iclass 12, count 2 2006.189.08:07:12.18#ibcon#end of sib2, iclass 12, count 2 2006.189.08:07:12.18#ibcon#*after write, iclass 12, count 2 2006.189.08:07:12.18#ibcon#*before return 0, iclass 12, count 2 2006.189.08:07:12.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:12.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:07:12.18#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.08:07:12.18#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:12.18#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:12.30#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:12.30#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:12.30#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:07:12.30#ibcon#first serial, iclass 12, count 0 2006.189.08:07:12.30#ibcon#enter sib2, iclass 12, count 0 2006.189.08:07:12.30#ibcon#flushed, iclass 12, count 0 2006.189.08:07:12.30#ibcon#about to write, iclass 12, count 0 2006.189.08:07:12.30#ibcon#wrote, iclass 12, count 0 2006.189.08:07:12.30#ibcon#about to read 3, iclass 12, count 0 2006.189.08:07:12.32#ibcon#read 3, iclass 12, count 0 2006.189.08:07:12.32#ibcon#about to read 4, iclass 12, count 0 2006.189.08:07:12.32#ibcon#read 4, iclass 12, count 0 2006.189.08:07:12.32#ibcon#about to read 5, iclass 12, count 0 2006.189.08:07:12.32#ibcon#read 5, iclass 12, count 0 2006.189.08:07:12.32#ibcon#about to read 6, iclass 12, count 0 2006.189.08:07:12.32#ibcon#read 6, iclass 12, count 0 2006.189.08:07:12.32#ibcon#end of sib2, iclass 12, count 0 2006.189.08:07:12.32#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:07:12.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:07:12.32#ibcon#[27=USB\r\n] 2006.189.08:07:12.32#ibcon#*before write, iclass 12, count 0 2006.189.08:07:12.32#ibcon#enter sib2, iclass 12, count 0 2006.189.08:07:12.32#ibcon#flushed, iclass 12, count 0 2006.189.08:07:12.32#ibcon#about to write, iclass 12, count 0 2006.189.08:07:12.32#ibcon#wrote, iclass 12, count 0 2006.189.08:07:12.32#ibcon#about to read 3, iclass 12, count 0 2006.189.08:07:12.35#ibcon#read 3, iclass 12, count 0 2006.189.08:07:12.35#ibcon#about to read 4, iclass 12, count 0 2006.189.08:07:12.35#ibcon#read 4, iclass 12, count 0 2006.189.08:07:12.35#ibcon#about to read 5, iclass 12, count 0 2006.189.08:07:12.35#ibcon#read 5, iclass 12, count 0 2006.189.08:07:12.35#ibcon#about to read 6, iclass 12, count 0 2006.189.08:07:12.35#ibcon#read 6, iclass 12, count 0 2006.189.08:07:12.35#ibcon#end of sib2, iclass 12, count 0 2006.189.08:07:12.35#ibcon#*after write, iclass 12, count 0 2006.189.08:07:12.35#ibcon#*before return 0, iclass 12, count 0 2006.189.08:07:12.35#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:12.35#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:07:12.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:07:12.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:07:12.35$vc4f8/vblo=6,752.99 2006.189.08:07:12.35#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.08:07:12.35#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.08:07:12.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:07:12.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:12.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:12.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:12.35#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:07:12.35#ibcon#first serial, iclass 14, count 0 2006.189.08:07:12.35#ibcon#enter sib2, iclass 14, count 0 2006.189.08:07:12.35#ibcon#flushed, iclass 14, count 0 2006.189.08:07:12.35#ibcon#about to write, iclass 14, count 0 2006.189.08:07:12.35#ibcon#wrote, iclass 14, count 0 2006.189.08:07:12.35#ibcon#about to read 3, iclass 14, count 0 2006.189.08:07:12.37#ibcon#read 3, iclass 14, count 0 2006.189.08:07:12.37#ibcon#about to read 4, iclass 14, count 0 2006.189.08:07:12.37#ibcon#read 4, iclass 14, count 0 2006.189.08:07:12.37#ibcon#about to read 5, iclass 14, count 0 2006.189.08:07:12.37#ibcon#read 5, iclass 14, count 0 2006.189.08:07:12.37#ibcon#about to read 6, iclass 14, count 0 2006.189.08:07:12.37#ibcon#read 6, iclass 14, count 0 2006.189.08:07:12.37#ibcon#end of sib2, iclass 14, count 0 2006.189.08:07:12.37#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:07:12.37#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:07:12.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:07:12.37#ibcon#*before write, iclass 14, count 0 2006.189.08:07:12.37#ibcon#enter sib2, iclass 14, count 0 2006.189.08:07:12.37#ibcon#flushed, iclass 14, count 0 2006.189.08:07:12.37#ibcon#about to write, iclass 14, count 0 2006.189.08:07:12.37#ibcon#wrote, iclass 14, count 0 2006.189.08:07:12.37#ibcon#about to read 3, iclass 14, count 0 2006.189.08:07:12.41#ibcon#read 3, iclass 14, count 0 2006.189.08:07:12.41#ibcon#about to read 4, iclass 14, count 0 2006.189.08:07:12.41#ibcon#read 4, iclass 14, count 0 2006.189.08:07:12.41#ibcon#about to read 5, iclass 14, count 0 2006.189.08:07:12.41#ibcon#read 5, iclass 14, count 0 2006.189.08:07:12.41#ibcon#about to read 6, iclass 14, count 0 2006.189.08:07:12.41#ibcon#read 6, iclass 14, count 0 2006.189.08:07:12.41#ibcon#end of sib2, iclass 14, count 0 2006.189.08:07:12.41#ibcon#*after write, iclass 14, count 0 2006.189.08:07:12.41#ibcon#*before return 0, iclass 14, count 0 2006.189.08:07:12.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:12.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:07:12.41#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:07:12.41#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:07:12.41$vc4f8/vb=6,4 2006.189.08:07:12.41#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.08:07:12.41#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.08:07:12.41#ibcon#ireg 11 cls_cnt 2 2006.189.08:07:12.41#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:12.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:12.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:12.47#ibcon#enter wrdev, iclass 16, count 2 2006.189.08:07:12.47#ibcon#first serial, iclass 16, count 2 2006.189.08:07:12.47#ibcon#enter sib2, iclass 16, count 2 2006.189.08:07:12.47#ibcon#flushed, iclass 16, count 2 2006.189.08:07:12.47#ibcon#about to write, iclass 16, count 2 2006.189.08:07:12.47#ibcon#wrote, iclass 16, count 2 2006.189.08:07:12.47#ibcon#about to read 3, iclass 16, count 2 2006.189.08:07:12.49#ibcon#read 3, iclass 16, count 2 2006.189.08:07:12.49#ibcon#about to read 4, iclass 16, count 2 2006.189.08:07:12.49#ibcon#read 4, iclass 16, count 2 2006.189.08:07:12.49#ibcon#about to read 5, iclass 16, count 2 2006.189.08:07:12.49#ibcon#read 5, iclass 16, count 2 2006.189.08:07:12.49#ibcon#about to read 6, iclass 16, count 2 2006.189.08:07:12.49#ibcon#read 6, iclass 16, count 2 2006.189.08:07:12.49#ibcon#end of sib2, iclass 16, count 2 2006.189.08:07:12.49#ibcon#*mode == 0, iclass 16, count 2 2006.189.08:07:12.49#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.08:07:12.49#ibcon#[27=AT06-04\r\n] 2006.189.08:07:12.49#ibcon#*before write, iclass 16, count 2 2006.189.08:07:12.49#ibcon#enter sib2, iclass 16, count 2 2006.189.08:07:12.49#ibcon#flushed, iclass 16, count 2 2006.189.08:07:12.49#ibcon#about to write, iclass 16, count 2 2006.189.08:07:12.49#ibcon#wrote, iclass 16, count 2 2006.189.08:07:12.49#ibcon#about to read 3, iclass 16, count 2 2006.189.08:07:12.52#ibcon#read 3, iclass 16, count 2 2006.189.08:07:12.52#ibcon#about to read 4, iclass 16, count 2 2006.189.08:07:12.52#ibcon#read 4, iclass 16, count 2 2006.189.08:07:12.52#ibcon#about to read 5, iclass 16, count 2 2006.189.08:07:12.52#ibcon#read 5, iclass 16, count 2 2006.189.08:07:12.52#ibcon#about to read 6, iclass 16, count 2 2006.189.08:07:12.52#ibcon#read 6, iclass 16, count 2 2006.189.08:07:12.52#ibcon#end of sib2, iclass 16, count 2 2006.189.08:07:12.52#ibcon#*after write, iclass 16, count 2 2006.189.08:07:12.52#ibcon#*before return 0, iclass 16, count 2 2006.189.08:07:12.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:12.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:07:12.52#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.08:07:12.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:07:12.52#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:12.64#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:12.64#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:12.64#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:07:12.64#ibcon#first serial, iclass 16, count 0 2006.189.08:07:12.64#ibcon#enter sib2, iclass 16, count 0 2006.189.08:07:12.64#ibcon#flushed, iclass 16, count 0 2006.189.08:07:12.64#ibcon#about to write, iclass 16, count 0 2006.189.08:07:12.64#ibcon#wrote, iclass 16, count 0 2006.189.08:07:12.64#ibcon#about to read 3, iclass 16, count 0 2006.189.08:07:12.66#ibcon#read 3, iclass 16, count 0 2006.189.08:07:12.66#ibcon#about to read 4, iclass 16, count 0 2006.189.08:07:12.66#ibcon#read 4, iclass 16, count 0 2006.189.08:07:12.66#ibcon#about to read 5, iclass 16, count 0 2006.189.08:07:12.66#ibcon#read 5, iclass 16, count 0 2006.189.08:07:12.66#ibcon#about to read 6, iclass 16, count 0 2006.189.08:07:12.66#ibcon#read 6, iclass 16, count 0 2006.189.08:07:12.66#ibcon#end of sib2, iclass 16, count 0 2006.189.08:07:12.66#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:07:12.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:07:12.66#ibcon#[27=USB\r\n] 2006.189.08:07:12.66#ibcon#*before write, iclass 16, count 0 2006.189.08:07:12.66#ibcon#enter sib2, iclass 16, count 0 2006.189.08:07:12.66#ibcon#flushed, iclass 16, count 0 2006.189.08:07:12.66#ibcon#about to write, iclass 16, count 0 2006.189.08:07:12.66#ibcon#wrote, iclass 16, count 0 2006.189.08:07:12.66#ibcon#about to read 3, iclass 16, count 0 2006.189.08:07:12.69#ibcon#read 3, iclass 16, count 0 2006.189.08:07:12.69#ibcon#about to read 4, iclass 16, count 0 2006.189.08:07:12.69#ibcon#read 4, iclass 16, count 0 2006.189.08:07:12.69#ibcon#about to read 5, iclass 16, count 0 2006.189.08:07:12.69#ibcon#read 5, iclass 16, count 0 2006.189.08:07:12.69#ibcon#about to read 6, iclass 16, count 0 2006.189.08:07:12.69#ibcon#read 6, iclass 16, count 0 2006.189.08:07:12.69#ibcon#end of sib2, iclass 16, count 0 2006.189.08:07:12.69#ibcon#*after write, iclass 16, count 0 2006.189.08:07:12.69#ibcon#*before return 0, iclass 16, count 0 2006.189.08:07:12.69#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:12.69#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:07:12.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:07:12.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:07:12.69$vc4f8/vabw=wide 2006.189.08:07:12.69#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.08:07:12.69#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.08:07:12.69#ibcon#ireg 8 cls_cnt 0 2006.189.08:07:12.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:12.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:12.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:12.69#ibcon#enter wrdev, iclass 18, count 0 2006.189.08:07:12.69#ibcon#first serial, iclass 18, count 0 2006.189.08:07:12.69#ibcon#enter sib2, iclass 18, count 0 2006.189.08:07:12.69#ibcon#flushed, iclass 18, count 0 2006.189.08:07:12.69#ibcon#about to write, iclass 18, count 0 2006.189.08:07:12.69#ibcon#wrote, iclass 18, count 0 2006.189.08:07:12.69#ibcon#about to read 3, iclass 18, count 0 2006.189.08:07:12.71#ibcon#read 3, iclass 18, count 0 2006.189.08:07:12.71#ibcon#about to read 4, iclass 18, count 0 2006.189.08:07:12.71#ibcon#read 4, iclass 18, count 0 2006.189.08:07:12.71#ibcon#about to read 5, iclass 18, count 0 2006.189.08:07:12.71#ibcon#read 5, iclass 18, count 0 2006.189.08:07:12.71#ibcon#about to read 6, iclass 18, count 0 2006.189.08:07:12.71#ibcon#read 6, iclass 18, count 0 2006.189.08:07:12.71#ibcon#end of sib2, iclass 18, count 0 2006.189.08:07:12.71#ibcon#*mode == 0, iclass 18, count 0 2006.189.08:07:12.71#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.08:07:12.71#ibcon#[25=BW32\r\n] 2006.189.08:07:12.71#ibcon#*before write, iclass 18, count 0 2006.189.08:07:12.71#ibcon#enter sib2, iclass 18, count 0 2006.189.08:07:12.71#ibcon#flushed, iclass 18, count 0 2006.189.08:07:12.71#ibcon#about to write, iclass 18, count 0 2006.189.08:07:12.71#ibcon#wrote, iclass 18, count 0 2006.189.08:07:12.71#ibcon#about to read 3, iclass 18, count 0 2006.189.08:07:12.74#ibcon#read 3, iclass 18, count 0 2006.189.08:07:12.74#ibcon#about to read 4, iclass 18, count 0 2006.189.08:07:12.74#ibcon#read 4, iclass 18, count 0 2006.189.08:07:12.74#ibcon#about to read 5, iclass 18, count 0 2006.189.08:07:12.74#ibcon#read 5, iclass 18, count 0 2006.189.08:07:12.74#ibcon#about to read 6, iclass 18, count 0 2006.189.08:07:12.74#ibcon#read 6, iclass 18, count 0 2006.189.08:07:12.74#ibcon#end of sib2, iclass 18, count 0 2006.189.08:07:12.74#ibcon#*after write, iclass 18, count 0 2006.189.08:07:12.74#ibcon#*before return 0, iclass 18, count 0 2006.189.08:07:12.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:12.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:07:12.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.08:07:12.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.08:07:12.74$vc4f8/vbbw=wide 2006.189.08:07:12.74#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.08:07:12.74#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.08:07:12.74#ibcon#ireg 8 cls_cnt 0 2006.189.08:07:12.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:07:12.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:07:12.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:07:12.81#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:07:12.81#ibcon#first serial, iclass 20, count 0 2006.189.08:07:12.81#ibcon#enter sib2, iclass 20, count 0 2006.189.08:07:12.81#ibcon#flushed, iclass 20, count 0 2006.189.08:07:12.81#ibcon#about to write, iclass 20, count 0 2006.189.08:07:12.81#ibcon#wrote, iclass 20, count 0 2006.189.08:07:12.81#ibcon#about to read 3, iclass 20, count 0 2006.189.08:07:12.83#ibcon#read 3, iclass 20, count 0 2006.189.08:07:12.83#ibcon#about to read 4, iclass 20, count 0 2006.189.08:07:12.83#ibcon#read 4, iclass 20, count 0 2006.189.08:07:12.83#ibcon#about to read 5, iclass 20, count 0 2006.189.08:07:12.83#ibcon#read 5, iclass 20, count 0 2006.189.08:07:12.83#ibcon#about to read 6, iclass 20, count 0 2006.189.08:07:12.83#ibcon#read 6, iclass 20, count 0 2006.189.08:07:12.83#ibcon#end of sib2, iclass 20, count 0 2006.189.08:07:12.83#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:07:12.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:07:12.83#ibcon#[27=BW32\r\n] 2006.189.08:07:12.83#ibcon#*before write, iclass 20, count 0 2006.189.08:07:12.83#ibcon#enter sib2, iclass 20, count 0 2006.189.08:07:12.83#ibcon#flushed, iclass 20, count 0 2006.189.08:07:12.83#ibcon#about to write, iclass 20, count 0 2006.189.08:07:12.83#ibcon#wrote, iclass 20, count 0 2006.189.08:07:12.83#ibcon#about to read 3, iclass 20, count 0 2006.189.08:07:12.86#ibcon#read 3, iclass 20, count 0 2006.189.08:07:12.86#ibcon#about to read 4, iclass 20, count 0 2006.189.08:07:12.86#ibcon#read 4, iclass 20, count 0 2006.189.08:07:12.86#ibcon#about to read 5, iclass 20, count 0 2006.189.08:07:12.86#ibcon#read 5, iclass 20, count 0 2006.189.08:07:12.86#ibcon#about to read 6, iclass 20, count 0 2006.189.08:07:12.86#ibcon#read 6, iclass 20, count 0 2006.189.08:07:12.86#ibcon#end of sib2, iclass 20, count 0 2006.189.08:07:12.86#ibcon#*after write, iclass 20, count 0 2006.189.08:07:12.86#ibcon#*before return 0, iclass 20, count 0 2006.189.08:07:12.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:07:12.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:07:12.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:07:12.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:07:12.86$4f8m12a/ifd4f 2006.189.08:07:12.86$ifd4f/lo= 2006.189.08:07:12.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:07:12.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:07:12.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:07:12.86$ifd4f/patch= 2006.189.08:07:12.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:07:12.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:07:12.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:07:12.86$4f8m12a/"form=m,16.000,1:2 2006.189.08:07:12.86$4f8m12a/"tpicd 2006.189.08:07:12.86$4f8m12a/echo=off 2006.189.08:07:12.86$4f8m12a/xlog=off 2006.189.08:07:12.86:!2006.189.08:07:40 2006.189.08:07:23.14#trakl#Source acquired 2006.189.08:07:25.14#flagr#flagr/antenna,acquired 2006.189.08:07:40.00:preob 2006.189.08:07:41.14/onsource/TRACKING 2006.189.08:07:41.14:!2006.189.08:07:50 2006.189.08:07:50.00:data_valid=on 2006.189.08:07:50.00:midob 2006.189.08:07:50.14/onsource/TRACKING 2006.189.08:07:50.14/wx/25.59,1009.2,91 2006.189.08:07:50.33/cable/+6.4557E-03 2006.189.08:07:51.42/va/01,08,usb,yes,29,31 2006.189.08:07:51.42/va/02,07,usb,yes,30,31 2006.189.08:07:51.42/va/03,06,usb,yes,31,32 2006.189.08:07:51.42/va/04,07,usb,yes,31,33 2006.189.08:07:51.42/va/05,07,usb,yes,33,35 2006.189.08:07:51.42/va/06,06,usb,yes,32,32 2006.189.08:07:51.42/va/07,06,usb,yes,32,32 2006.189.08:07:51.42/va/08,06,usb,yes,35,34 2006.189.08:07:51.65/valo/01,532.99,yes,locked 2006.189.08:07:51.65/valo/02,572.99,yes,locked 2006.189.08:07:51.65/valo/03,672.99,yes,locked 2006.189.08:07:51.65/valo/04,832.99,yes,locked 2006.189.08:07:51.65/valo/05,652.99,yes,locked 2006.189.08:07:51.65/valo/06,772.99,yes,locked 2006.189.08:07:51.65/valo/07,832.99,yes,locked 2006.189.08:07:51.65/valo/08,852.99,yes,locked 2006.189.08:07:52.74/vb/01,04,usb,yes,29,28 2006.189.08:07:52.74/vb/02,04,usb,yes,31,32 2006.189.08:07:52.74/vb/03,04,usb,yes,27,31 2006.189.08:07:52.74/vb/04,04,usb,yes,28,28 2006.189.08:07:52.74/vb/05,04,usb,yes,27,31 2006.189.08:07:52.74/vb/06,04,usb,yes,28,30 2006.189.08:07:52.74/vb/07,04,usb,yes,30,30 2006.189.08:07:52.74/vb/08,04,usb,yes,27,31 2006.189.08:07:52.97/vblo/01,632.99,yes,locked 2006.189.08:07:52.97/vblo/02,640.99,yes,locked 2006.189.08:07:52.97/vblo/03,656.99,yes,locked 2006.189.08:07:52.97/vblo/04,712.99,yes,locked 2006.189.08:07:52.97/vblo/05,744.99,yes,locked 2006.189.08:07:52.97/vblo/06,752.99,yes,locked 2006.189.08:07:52.97/vblo/07,734.99,yes,locked 2006.189.08:07:52.97/vblo/08,744.99,yes,locked 2006.189.08:07:53.12/vabw/8 2006.189.08:07:53.27/vbbw/8 2006.189.08:07:53.36/xfe/off,on,16.0 2006.189.08:07:53.74/ifatt/23,28,28,28 2006.189.08:07:54.08/fmout-gps/S +2.96E-07 2006.189.08:07:54.16:!2006.189.08:08:50 2006.189.08:08:50.02:data_valid=off 2006.189.08:08:50.02:postob 2006.189.08:08:50.10/cable/+6.4573E-03 2006.189.08:08:50.10/wx/25.56,1009.2,91 2006.189.08:08:51.07/fmout-gps/S +2.96E-07 2006.189.08:08:51.07:scan_name=189-0809,k06189,60 2006.189.08:08:51.07:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.189.08:08:51.15#flagr#flagr/antenna,new-source 2006.189.08:08:52.14:checkk5 2006.189.08:08:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:08:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:08:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:08:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:08:54.05/chk_obsdata//k5ts1/T1890807??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:08:54.43/chk_obsdata//k5ts2/T1890807??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:08:54.80/chk_obsdata//k5ts3/T1890807??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:08:55.18/chk_obsdata//k5ts4/T1890807??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:08:55.88/k5log//k5ts1_log_newline 2006.189.08:08:56.58/k5log//k5ts2_log_newline 2006.189.08:08:57.27/k5log//k5ts3_log_newline 2006.189.08:08:57.97/k5log//k5ts4_log_newline 2006.189.08:08:57.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:08:57.99:4f8m12a=2 2006.189.08:08:57.99$4f8m12a/echo=on 2006.189.08:08:57.99$4f8m12a/pcalon 2006.189.08:08:57.99$pcalon/"no phase cal control is implemented here 2006.189.08:08:58.00$4f8m12a/"tpicd=stop 2006.189.08:08:58.00$4f8m12a/vc4f8 2006.189.08:08:58.00$vc4f8/valo=1,532.99 2006.189.08:08:58.00#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.08:08:58.00#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.08:08:58.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:08:58.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:08:58.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:08:58.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:08:58.00#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:08:58.00#ibcon#first serial, iclass 27, count 0 2006.189.08:08:58.00#ibcon#enter sib2, iclass 27, count 0 2006.189.08:08:58.00#ibcon#flushed, iclass 27, count 0 2006.189.08:08:58.00#ibcon#about to write, iclass 27, count 0 2006.189.08:08:58.00#ibcon#wrote, iclass 27, count 0 2006.189.08:08:58.00#ibcon#about to read 3, iclass 27, count 0 2006.189.08:08:58.05#ibcon#read 3, iclass 27, count 0 2006.189.08:08:58.05#ibcon#about to read 4, iclass 27, count 0 2006.189.08:08:58.05#ibcon#read 4, iclass 27, count 0 2006.189.08:08:58.05#ibcon#about to read 5, iclass 27, count 0 2006.189.08:08:58.05#ibcon#read 5, iclass 27, count 0 2006.189.08:08:58.05#ibcon#about to read 6, iclass 27, count 0 2006.189.08:08:58.05#ibcon#read 6, iclass 27, count 0 2006.189.08:08:58.05#ibcon#end of sib2, iclass 27, count 0 2006.189.08:08:58.05#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:08:58.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:08:58.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:08:58.05#ibcon#*before write, iclass 27, count 0 2006.189.08:08:58.05#ibcon#enter sib2, iclass 27, count 0 2006.189.08:08:58.05#ibcon#flushed, iclass 27, count 0 2006.189.08:08:58.05#ibcon#about to write, iclass 27, count 0 2006.189.08:08:58.05#ibcon#wrote, iclass 27, count 0 2006.189.08:08:58.05#ibcon#about to read 3, iclass 27, count 0 2006.189.08:08:58.09#ibcon#read 3, iclass 27, count 0 2006.189.08:08:58.09#ibcon#about to read 4, iclass 27, count 0 2006.189.08:08:58.09#ibcon#read 4, iclass 27, count 0 2006.189.08:08:58.09#ibcon#about to read 5, iclass 27, count 0 2006.189.08:08:58.09#ibcon#read 5, iclass 27, count 0 2006.189.08:08:58.09#ibcon#about to read 6, iclass 27, count 0 2006.189.08:08:58.09#ibcon#read 6, iclass 27, count 0 2006.189.08:08:58.09#ibcon#end of sib2, iclass 27, count 0 2006.189.08:08:58.09#ibcon#*after write, iclass 27, count 0 2006.189.08:08:58.10#ibcon#*before return 0, iclass 27, count 0 2006.189.08:08:58.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:08:58.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:08:58.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:08:58.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:08:58.10$vc4f8/va=1,8 2006.189.08:08:58.10#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.08:08:58.10#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.08:08:58.10#ibcon#ireg 11 cls_cnt 2 2006.189.08:08:58.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:08:58.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:08:58.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:08:58.10#ibcon#enter wrdev, iclass 30, count 2 2006.189.08:08:58.10#ibcon#first serial, iclass 30, count 2 2006.189.08:08:58.10#ibcon#enter sib2, iclass 30, count 2 2006.189.08:08:58.10#ibcon#flushed, iclass 30, count 2 2006.189.08:08:58.10#ibcon#about to write, iclass 30, count 2 2006.189.08:08:58.10#ibcon#wrote, iclass 30, count 2 2006.189.08:08:58.10#ibcon#about to read 3, iclass 30, count 2 2006.189.08:08:58.11#ibcon#read 3, iclass 30, count 2 2006.189.08:08:58.11#ibcon#about to read 4, iclass 30, count 2 2006.189.08:08:58.11#ibcon#read 4, iclass 30, count 2 2006.189.08:08:58.11#ibcon#about to read 5, iclass 30, count 2 2006.189.08:08:58.11#ibcon#read 5, iclass 30, count 2 2006.189.08:08:58.11#ibcon#about to read 6, iclass 30, count 2 2006.189.08:08:58.11#ibcon#read 6, iclass 30, count 2 2006.189.08:08:58.11#ibcon#end of sib2, iclass 30, count 2 2006.189.08:08:58.11#ibcon#*mode == 0, iclass 30, count 2 2006.189.08:08:58.11#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.08:08:58.11#ibcon#[25=AT01-08\r\n] 2006.189.08:08:58.11#ibcon#*before write, iclass 30, count 2 2006.189.08:08:58.12#ibcon#enter sib2, iclass 30, count 2 2006.189.08:08:58.12#ibcon#flushed, iclass 30, count 2 2006.189.08:08:58.12#ibcon#about to write, iclass 30, count 2 2006.189.08:08:58.12#ibcon#wrote, iclass 30, count 2 2006.189.08:08:58.12#ibcon#about to read 3, iclass 30, count 2 2006.189.08:08:58.13#abcon#<5=/04 3.7 6.7 25.55 911009.2\r\n> 2006.189.08:08:58.14#abcon#{5=INTERFACE CLEAR} 2006.189.08:08:58.15#ibcon#read 3, iclass 30, count 2 2006.189.08:08:58.15#ibcon#about to read 4, iclass 30, count 2 2006.189.08:08:58.15#ibcon#read 4, iclass 30, count 2 2006.189.08:08:58.15#ibcon#about to read 5, iclass 30, count 2 2006.189.08:08:58.15#ibcon#read 5, iclass 30, count 2 2006.189.08:08:58.15#ibcon#about to read 6, iclass 30, count 2 2006.189.08:08:58.15#ibcon#read 6, iclass 30, count 2 2006.189.08:08:58.15#ibcon#end of sib2, iclass 30, count 2 2006.189.08:08:58.15#ibcon#*after write, iclass 30, count 2 2006.189.08:08:58.15#ibcon#*before return 0, iclass 30, count 2 2006.189.08:08:58.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:08:58.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:08:58.15#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.08:08:58.15#ibcon#ireg 7 cls_cnt 0 2006.189.08:08:58.15#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:08:58.20#abcon#[5=S1D000X0/0*\r\n] 2006.189.08:08:58.27#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:08:58.27#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:08:58.27#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:08:58.27#ibcon#first serial, iclass 30, count 0 2006.189.08:08:58.27#ibcon#enter sib2, iclass 30, count 0 2006.189.08:08:58.27#ibcon#flushed, iclass 30, count 0 2006.189.08:08:58.27#ibcon#about to write, iclass 30, count 0 2006.189.08:08:58.27#ibcon#wrote, iclass 30, count 0 2006.189.08:08:58.27#ibcon#about to read 3, iclass 30, count 0 2006.189.08:08:58.28#ibcon#read 3, iclass 30, count 0 2006.189.08:08:58.28#ibcon#about to read 4, iclass 30, count 0 2006.189.08:08:58.28#ibcon#read 4, iclass 30, count 0 2006.189.08:08:58.28#ibcon#about to read 5, iclass 30, count 0 2006.189.08:08:58.28#ibcon#read 5, iclass 30, count 0 2006.189.08:08:58.28#ibcon#about to read 6, iclass 30, count 0 2006.189.08:08:58.28#ibcon#read 6, iclass 30, count 0 2006.189.08:08:58.28#ibcon#end of sib2, iclass 30, count 0 2006.189.08:08:58.29#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:08:58.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:08:58.29#ibcon#[25=USB\r\n] 2006.189.08:08:58.29#ibcon#*before write, iclass 30, count 0 2006.189.08:08:58.29#ibcon#enter sib2, iclass 30, count 0 2006.189.08:08:58.29#ibcon#flushed, iclass 30, count 0 2006.189.08:08:58.29#ibcon#about to write, iclass 30, count 0 2006.189.08:08:58.29#ibcon#wrote, iclass 30, count 0 2006.189.08:08:58.29#ibcon#about to read 3, iclass 30, count 0 2006.189.08:08:58.31#ibcon#read 3, iclass 30, count 0 2006.189.08:08:58.31#ibcon#about to read 4, iclass 30, count 0 2006.189.08:08:58.31#ibcon#read 4, iclass 30, count 0 2006.189.08:08:58.31#ibcon#about to read 5, iclass 30, count 0 2006.189.08:08:58.31#ibcon#read 5, iclass 30, count 0 2006.189.08:08:58.31#ibcon#about to read 6, iclass 30, count 0 2006.189.08:08:58.31#ibcon#read 6, iclass 30, count 0 2006.189.08:08:58.31#ibcon#end of sib2, iclass 30, count 0 2006.189.08:08:58.31#ibcon#*after write, iclass 30, count 0 2006.189.08:08:58.31#ibcon#*before return 0, iclass 30, count 0 2006.189.08:08:58.31#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:08:58.31#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:08:58.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:08:58.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:08:58.32$vc4f8/valo=2,572.99 2006.189.08:08:58.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.08:08:58.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.08:08:58.32#ibcon#ireg 17 cls_cnt 0 2006.189.08:08:58.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:08:58.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:08:58.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:08:58.32#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:08:58.32#ibcon#first serial, iclass 35, count 0 2006.189.08:08:58.32#ibcon#enter sib2, iclass 35, count 0 2006.189.08:08:58.32#ibcon#flushed, iclass 35, count 0 2006.189.08:08:58.32#ibcon#about to write, iclass 35, count 0 2006.189.08:08:58.32#ibcon#wrote, iclass 35, count 0 2006.189.08:08:58.32#ibcon#about to read 3, iclass 35, count 0 2006.189.08:08:58.33#ibcon#read 3, iclass 35, count 0 2006.189.08:08:58.33#ibcon#about to read 4, iclass 35, count 0 2006.189.08:08:58.33#ibcon#read 4, iclass 35, count 0 2006.189.08:08:58.33#ibcon#about to read 5, iclass 35, count 0 2006.189.08:08:58.33#ibcon#read 5, iclass 35, count 0 2006.189.08:08:58.33#ibcon#about to read 6, iclass 35, count 0 2006.189.08:08:58.33#ibcon#read 6, iclass 35, count 0 2006.189.08:08:58.33#ibcon#end of sib2, iclass 35, count 0 2006.189.08:08:58.33#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:08:58.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:08:58.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:08:58.33#ibcon#*before write, iclass 35, count 0 2006.189.08:08:58.33#ibcon#enter sib2, iclass 35, count 0 2006.189.08:08:58.34#ibcon#flushed, iclass 35, count 0 2006.189.08:08:58.34#ibcon#about to write, iclass 35, count 0 2006.189.08:08:58.34#ibcon#wrote, iclass 35, count 0 2006.189.08:08:58.34#ibcon#about to read 3, iclass 35, count 0 2006.189.08:08:58.38#ibcon#read 3, iclass 35, count 0 2006.189.08:08:58.38#ibcon#about to read 4, iclass 35, count 0 2006.189.08:08:58.38#ibcon#read 4, iclass 35, count 0 2006.189.08:08:58.38#ibcon#about to read 5, iclass 35, count 0 2006.189.08:08:58.38#ibcon#read 5, iclass 35, count 0 2006.189.08:08:58.38#ibcon#about to read 6, iclass 35, count 0 2006.189.08:08:58.38#ibcon#read 6, iclass 35, count 0 2006.189.08:08:58.38#ibcon#end of sib2, iclass 35, count 0 2006.189.08:08:58.38#ibcon#*after write, iclass 35, count 0 2006.189.08:08:58.38#ibcon#*before return 0, iclass 35, count 0 2006.189.08:08:58.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:08:58.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:08:58.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:08:58.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:08:58.38$vc4f8/va=2,7 2006.189.08:08:58.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.08:08:58.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.08:08:58.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:08:58.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:08:58.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:08:58.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:08:58.42#ibcon#enter wrdev, iclass 37, count 2 2006.189.08:08:58.42#ibcon#first serial, iclass 37, count 2 2006.189.08:08:58.42#ibcon#enter sib2, iclass 37, count 2 2006.189.08:08:58.42#ibcon#flushed, iclass 37, count 2 2006.189.08:08:58.42#ibcon#about to write, iclass 37, count 2 2006.189.08:08:58.42#ibcon#wrote, iclass 37, count 2 2006.189.08:08:58.42#ibcon#about to read 3, iclass 37, count 2 2006.189.08:08:58.44#ibcon#read 3, iclass 37, count 2 2006.189.08:08:58.44#ibcon#about to read 4, iclass 37, count 2 2006.189.08:08:58.44#ibcon#read 4, iclass 37, count 2 2006.189.08:08:58.44#ibcon#about to read 5, iclass 37, count 2 2006.189.08:08:58.44#ibcon#read 5, iclass 37, count 2 2006.189.08:08:58.44#ibcon#about to read 6, iclass 37, count 2 2006.189.08:08:58.44#ibcon#read 6, iclass 37, count 2 2006.189.08:08:58.44#ibcon#end of sib2, iclass 37, count 2 2006.189.08:08:58.44#ibcon#*mode == 0, iclass 37, count 2 2006.189.08:08:58.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.08:08:58.44#ibcon#[25=AT02-07\r\n] 2006.189.08:08:58.44#ibcon#*before write, iclass 37, count 2 2006.189.08:08:58.45#ibcon#enter sib2, iclass 37, count 2 2006.189.08:08:58.45#ibcon#flushed, iclass 37, count 2 2006.189.08:08:58.45#ibcon#about to write, iclass 37, count 2 2006.189.08:08:58.45#ibcon#wrote, iclass 37, count 2 2006.189.08:08:58.45#ibcon#about to read 3, iclass 37, count 2 2006.189.08:08:58.47#ibcon#read 3, iclass 37, count 2 2006.189.08:08:58.47#ibcon#about to read 4, iclass 37, count 2 2006.189.08:08:58.47#ibcon#read 4, iclass 37, count 2 2006.189.08:08:58.47#ibcon#about to read 5, iclass 37, count 2 2006.189.08:08:58.47#ibcon#read 5, iclass 37, count 2 2006.189.08:08:58.47#ibcon#about to read 6, iclass 37, count 2 2006.189.08:08:58.48#ibcon#read 6, iclass 37, count 2 2006.189.08:08:58.48#ibcon#end of sib2, iclass 37, count 2 2006.189.08:08:58.48#ibcon#*after write, iclass 37, count 2 2006.189.08:08:58.48#ibcon#*before return 0, iclass 37, count 2 2006.189.08:08:58.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:08:58.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:08:58.48#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.08:08:58.48#ibcon#ireg 7 cls_cnt 0 2006.189.08:08:58.48#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:08:58.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:08:58.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:08:58.59#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:08:58.59#ibcon#first serial, iclass 37, count 0 2006.189.08:08:58.59#ibcon#enter sib2, iclass 37, count 0 2006.189.08:08:58.59#ibcon#flushed, iclass 37, count 0 2006.189.08:08:58.59#ibcon#about to write, iclass 37, count 0 2006.189.08:08:58.60#ibcon#wrote, iclass 37, count 0 2006.189.08:08:58.60#ibcon#about to read 3, iclass 37, count 0 2006.189.08:08:58.61#ibcon#read 3, iclass 37, count 0 2006.189.08:08:58.61#ibcon#about to read 4, iclass 37, count 0 2006.189.08:08:58.61#ibcon#read 4, iclass 37, count 0 2006.189.08:08:58.61#ibcon#about to read 5, iclass 37, count 0 2006.189.08:08:58.61#ibcon#read 5, iclass 37, count 0 2006.189.08:08:58.61#ibcon#about to read 6, iclass 37, count 0 2006.189.08:08:58.61#ibcon#read 6, iclass 37, count 0 2006.189.08:08:58.61#ibcon#end of sib2, iclass 37, count 0 2006.189.08:08:58.62#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:08:58.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:08:58.62#ibcon#[25=USB\r\n] 2006.189.08:08:58.62#ibcon#*before write, iclass 37, count 0 2006.189.08:08:58.62#ibcon#enter sib2, iclass 37, count 0 2006.189.08:08:58.62#ibcon#flushed, iclass 37, count 0 2006.189.08:08:58.62#ibcon#about to write, iclass 37, count 0 2006.189.08:08:58.62#ibcon#wrote, iclass 37, count 0 2006.189.08:08:58.62#ibcon#about to read 3, iclass 37, count 0 2006.189.08:08:58.64#ibcon#read 3, iclass 37, count 0 2006.189.08:08:58.64#ibcon#about to read 4, iclass 37, count 0 2006.189.08:08:58.64#ibcon#read 4, iclass 37, count 0 2006.189.08:08:58.64#ibcon#about to read 5, iclass 37, count 0 2006.189.08:08:58.64#ibcon#read 5, iclass 37, count 0 2006.189.08:08:58.64#ibcon#about to read 6, iclass 37, count 0 2006.189.08:08:58.64#ibcon#read 6, iclass 37, count 0 2006.189.08:08:58.64#ibcon#end of sib2, iclass 37, count 0 2006.189.08:08:58.64#ibcon#*after write, iclass 37, count 0 2006.189.08:08:58.64#ibcon#*before return 0, iclass 37, count 0 2006.189.08:08:58.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:08:58.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:08:58.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:08:58.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:08:58.65$vc4f8/valo=3,672.99 2006.189.08:08:58.65#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.08:08:58.65#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.08:08:58.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:08:58.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:08:58.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:08:58.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:08:58.65#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:08:58.65#ibcon#first serial, iclass 39, count 0 2006.189.08:08:58.65#ibcon#enter sib2, iclass 39, count 0 2006.189.08:08:58.65#ibcon#flushed, iclass 39, count 0 2006.189.08:08:58.65#ibcon#about to write, iclass 39, count 0 2006.189.08:08:58.65#ibcon#wrote, iclass 39, count 0 2006.189.08:08:58.65#ibcon#about to read 3, iclass 39, count 0 2006.189.08:08:58.66#ibcon#read 3, iclass 39, count 0 2006.189.08:08:58.66#ibcon#about to read 4, iclass 39, count 0 2006.189.08:08:58.66#ibcon#read 4, iclass 39, count 0 2006.189.08:08:58.66#ibcon#about to read 5, iclass 39, count 0 2006.189.08:08:58.66#ibcon#read 5, iclass 39, count 0 2006.189.08:08:58.66#ibcon#about to read 6, iclass 39, count 0 2006.189.08:08:58.66#ibcon#read 6, iclass 39, count 0 2006.189.08:08:58.66#ibcon#end of sib2, iclass 39, count 0 2006.189.08:08:58.66#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:08:58.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:08:58.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:08:58.66#ibcon#*before write, iclass 39, count 0 2006.189.08:08:58.66#ibcon#enter sib2, iclass 39, count 0 2006.189.08:08:58.66#ibcon#flushed, iclass 39, count 0 2006.189.08:08:58.66#ibcon#about to write, iclass 39, count 0 2006.189.08:08:58.67#ibcon#wrote, iclass 39, count 0 2006.189.08:08:58.67#ibcon#about to read 3, iclass 39, count 0 2006.189.08:08:58.70#ibcon#read 3, iclass 39, count 0 2006.189.08:08:58.70#ibcon#about to read 4, iclass 39, count 0 2006.189.08:08:58.70#ibcon#read 4, iclass 39, count 0 2006.189.08:08:58.70#ibcon#about to read 5, iclass 39, count 0 2006.189.08:08:58.70#ibcon#read 5, iclass 39, count 0 2006.189.08:08:58.70#ibcon#about to read 6, iclass 39, count 0 2006.189.08:08:58.70#ibcon#read 6, iclass 39, count 0 2006.189.08:08:58.70#ibcon#end of sib2, iclass 39, count 0 2006.189.08:08:58.70#ibcon#*after write, iclass 39, count 0 2006.189.08:08:58.70#ibcon#*before return 0, iclass 39, count 0 2006.189.08:08:58.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:08:58.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:08:58.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:08:58.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:08:58.71$vc4f8/va=3,6 2006.189.08:08:58.71#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.08:08:58.71#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.08:08:58.71#ibcon#ireg 11 cls_cnt 2 2006.189.08:08:58.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:08:58.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:08:58.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:08:58.75#ibcon#enter wrdev, iclass 3, count 2 2006.189.08:08:58.75#ibcon#first serial, iclass 3, count 2 2006.189.08:08:58.75#ibcon#enter sib2, iclass 3, count 2 2006.189.08:08:58.75#ibcon#flushed, iclass 3, count 2 2006.189.08:08:58.75#ibcon#about to write, iclass 3, count 2 2006.189.08:08:58.75#ibcon#wrote, iclass 3, count 2 2006.189.08:08:58.75#ibcon#about to read 3, iclass 3, count 2 2006.189.08:08:58.77#ibcon#read 3, iclass 3, count 2 2006.189.08:08:58.77#ibcon#about to read 4, iclass 3, count 2 2006.189.08:08:58.77#ibcon#read 4, iclass 3, count 2 2006.189.08:08:58.77#ibcon#about to read 5, iclass 3, count 2 2006.189.08:08:58.77#ibcon#read 5, iclass 3, count 2 2006.189.08:08:58.77#ibcon#about to read 6, iclass 3, count 2 2006.189.08:08:58.77#ibcon#read 6, iclass 3, count 2 2006.189.08:08:58.77#ibcon#end of sib2, iclass 3, count 2 2006.189.08:08:58.77#ibcon#*mode == 0, iclass 3, count 2 2006.189.08:08:58.77#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.08:08:58.77#ibcon#[25=AT03-06\r\n] 2006.189.08:08:58.77#ibcon#*before write, iclass 3, count 2 2006.189.08:08:58.77#ibcon#enter sib2, iclass 3, count 2 2006.189.08:08:58.77#ibcon#flushed, iclass 3, count 2 2006.189.08:08:58.77#ibcon#about to write, iclass 3, count 2 2006.189.08:08:58.78#ibcon#wrote, iclass 3, count 2 2006.189.08:08:58.78#ibcon#about to read 3, iclass 3, count 2 2006.189.08:08:58.80#ibcon#read 3, iclass 3, count 2 2006.189.08:08:58.80#ibcon#about to read 4, iclass 3, count 2 2006.189.08:08:58.80#ibcon#read 4, iclass 3, count 2 2006.189.08:08:58.80#ibcon#about to read 5, iclass 3, count 2 2006.189.08:08:58.80#ibcon#read 5, iclass 3, count 2 2006.189.08:08:58.80#ibcon#about to read 6, iclass 3, count 2 2006.189.08:08:58.80#ibcon#read 6, iclass 3, count 2 2006.189.08:08:58.80#ibcon#end of sib2, iclass 3, count 2 2006.189.08:08:58.80#ibcon#*after write, iclass 3, count 2 2006.189.08:08:58.80#ibcon#*before return 0, iclass 3, count 2 2006.189.08:08:58.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:08:58.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:08:58.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.08:08:58.80#ibcon#ireg 7 cls_cnt 0 2006.189.08:08:58.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:08:58.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:08:58.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:08:58.92#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:08:58.92#ibcon#first serial, iclass 3, count 0 2006.189.08:08:58.92#ibcon#enter sib2, iclass 3, count 0 2006.189.08:08:58.92#ibcon#flushed, iclass 3, count 0 2006.189.08:08:58.92#ibcon#about to write, iclass 3, count 0 2006.189.08:08:58.92#ibcon#wrote, iclass 3, count 0 2006.189.08:08:58.92#ibcon#about to read 3, iclass 3, count 0 2006.189.08:08:58.94#ibcon#read 3, iclass 3, count 0 2006.189.08:08:58.94#ibcon#about to read 4, iclass 3, count 0 2006.189.08:08:58.94#ibcon#read 4, iclass 3, count 0 2006.189.08:08:58.94#ibcon#about to read 5, iclass 3, count 0 2006.189.08:08:58.94#ibcon#read 5, iclass 3, count 0 2006.189.08:08:58.94#ibcon#about to read 6, iclass 3, count 0 2006.189.08:08:58.94#ibcon#read 6, iclass 3, count 0 2006.189.08:08:58.94#ibcon#end of sib2, iclass 3, count 0 2006.189.08:08:58.94#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:08:58.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:08:58.94#ibcon#[25=USB\r\n] 2006.189.08:08:58.94#ibcon#*before write, iclass 3, count 0 2006.189.08:08:58.95#ibcon#enter sib2, iclass 3, count 0 2006.189.08:08:58.95#ibcon#flushed, iclass 3, count 0 2006.189.08:08:58.95#ibcon#about to write, iclass 3, count 0 2006.189.08:08:58.95#ibcon#wrote, iclass 3, count 0 2006.189.08:08:58.95#ibcon#about to read 3, iclass 3, count 0 2006.189.08:08:58.97#ibcon#read 3, iclass 3, count 0 2006.189.08:08:58.97#ibcon#about to read 4, iclass 3, count 0 2006.189.08:08:58.97#ibcon#read 4, iclass 3, count 0 2006.189.08:08:58.97#ibcon#about to read 5, iclass 3, count 0 2006.189.08:08:58.97#ibcon#read 5, iclass 3, count 0 2006.189.08:08:58.97#ibcon#about to read 6, iclass 3, count 0 2006.189.08:08:58.97#ibcon#read 6, iclass 3, count 0 2006.189.08:08:58.97#ibcon#end of sib2, iclass 3, count 0 2006.189.08:08:58.97#ibcon#*after write, iclass 3, count 0 2006.189.08:08:58.97#ibcon#*before return 0, iclass 3, count 0 2006.189.08:08:58.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:08:58.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:08:58.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:08:58.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:08:58.98$vc4f8/valo=4,832.99 2006.189.08:08:58.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.08:08:58.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.08:08:58.98#ibcon#ireg 17 cls_cnt 0 2006.189.08:08:58.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:08:58.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:08:58.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:08:58.98#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:08:58.98#ibcon#first serial, iclass 5, count 0 2006.189.08:08:58.98#ibcon#enter sib2, iclass 5, count 0 2006.189.08:08:58.98#ibcon#flushed, iclass 5, count 0 2006.189.08:08:58.98#ibcon#about to write, iclass 5, count 0 2006.189.08:08:58.98#ibcon#wrote, iclass 5, count 0 2006.189.08:08:58.98#ibcon#about to read 3, iclass 5, count 0 2006.189.08:08:58.99#ibcon#read 3, iclass 5, count 0 2006.189.08:08:58.99#ibcon#about to read 4, iclass 5, count 0 2006.189.08:08:58.99#ibcon#read 4, iclass 5, count 0 2006.189.08:08:58.99#ibcon#about to read 5, iclass 5, count 0 2006.189.08:08:58.99#ibcon#read 5, iclass 5, count 0 2006.189.08:08:58.99#ibcon#about to read 6, iclass 5, count 0 2006.189.08:08:58.99#ibcon#read 6, iclass 5, count 0 2006.189.08:08:58.99#ibcon#end of sib2, iclass 5, count 0 2006.189.08:08:58.99#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:08:58.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:08:58.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:08:58.99#ibcon#*before write, iclass 5, count 0 2006.189.08:08:58.99#ibcon#enter sib2, iclass 5, count 0 2006.189.08:08:58.99#ibcon#flushed, iclass 5, count 0 2006.189.08:08:58.99#ibcon#about to write, iclass 5, count 0 2006.189.08:08:59.00#ibcon#wrote, iclass 5, count 0 2006.189.08:08:59.00#ibcon#about to read 3, iclass 5, count 0 2006.189.08:08:59.03#ibcon#read 3, iclass 5, count 0 2006.189.08:08:59.03#ibcon#about to read 4, iclass 5, count 0 2006.189.08:08:59.03#ibcon#read 4, iclass 5, count 0 2006.189.08:08:59.03#ibcon#about to read 5, iclass 5, count 0 2006.189.08:08:59.03#ibcon#read 5, iclass 5, count 0 2006.189.08:08:59.03#ibcon#about to read 6, iclass 5, count 0 2006.189.08:08:59.03#ibcon#read 6, iclass 5, count 0 2006.189.08:08:59.03#ibcon#end of sib2, iclass 5, count 0 2006.189.08:08:59.03#ibcon#*after write, iclass 5, count 0 2006.189.08:08:59.03#ibcon#*before return 0, iclass 5, count 0 2006.189.08:08:59.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:08:59.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:08:59.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:08:59.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:08:59.04$vc4f8/va=4,7 2006.189.08:08:59.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.08:08:59.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.08:08:59.04#ibcon#ireg 11 cls_cnt 2 2006.189.08:08:59.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:08:59.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:08:59.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:08:59.08#ibcon#enter wrdev, iclass 7, count 2 2006.189.08:08:59.08#ibcon#first serial, iclass 7, count 2 2006.189.08:08:59.08#ibcon#enter sib2, iclass 7, count 2 2006.189.08:08:59.08#ibcon#flushed, iclass 7, count 2 2006.189.08:08:59.08#ibcon#about to write, iclass 7, count 2 2006.189.08:08:59.08#ibcon#wrote, iclass 7, count 2 2006.189.08:08:59.08#ibcon#about to read 3, iclass 7, count 2 2006.189.08:08:59.10#ibcon#read 3, iclass 7, count 2 2006.189.08:08:59.10#ibcon#about to read 4, iclass 7, count 2 2006.189.08:08:59.10#ibcon#read 4, iclass 7, count 2 2006.189.08:08:59.10#ibcon#about to read 5, iclass 7, count 2 2006.189.08:08:59.10#ibcon#read 5, iclass 7, count 2 2006.189.08:08:59.10#ibcon#about to read 6, iclass 7, count 2 2006.189.08:08:59.10#ibcon#read 6, iclass 7, count 2 2006.189.08:08:59.10#ibcon#end of sib2, iclass 7, count 2 2006.189.08:08:59.10#ibcon#*mode == 0, iclass 7, count 2 2006.189.08:08:59.10#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.08:08:59.10#ibcon#[25=AT04-07\r\n] 2006.189.08:08:59.10#ibcon#*before write, iclass 7, count 2 2006.189.08:08:59.10#ibcon#enter sib2, iclass 7, count 2 2006.189.08:08:59.10#ibcon#flushed, iclass 7, count 2 2006.189.08:08:59.10#ibcon#about to write, iclass 7, count 2 2006.189.08:08:59.11#ibcon#wrote, iclass 7, count 2 2006.189.08:08:59.11#ibcon#about to read 3, iclass 7, count 2 2006.189.08:08:59.13#ibcon#read 3, iclass 7, count 2 2006.189.08:08:59.13#ibcon#about to read 4, iclass 7, count 2 2006.189.08:08:59.13#ibcon#read 4, iclass 7, count 2 2006.189.08:08:59.13#ibcon#about to read 5, iclass 7, count 2 2006.189.08:08:59.13#ibcon#read 5, iclass 7, count 2 2006.189.08:08:59.13#ibcon#about to read 6, iclass 7, count 2 2006.189.08:08:59.13#ibcon#read 6, iclass 7, count 2 2006.189.08:08:59.13#ibcon#end of sib2, iclass 7, count 2 2006.189.08:08:59.13#ibcon#*after write, iclass 7, count 2 2006.189.08:08:59.13#ibcon#*before return 0, iclass 7, count 2 2006.189.08:08:59.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:08:59.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:08:59.13#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.08:08:59.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:08:59.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:08:59.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:08:59.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:08:59.24#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:08:59.24#ibcon#first serial, iclass 7, count 0 2006.189.08:08:59.24#ibcon#enter sib2, iclass 7, count 0 2006.189.08:08:59.24#ibcon#flushed, iclass 7, count 0 2006.189.08:08:59.24#ibcon#about to write, iclass 7, count 0 2006.189.08:08:59.24#ibcon#wrote, iclass 7, count 0 2006.189.08:08:59.24#ibcon#about to read 3, iclass 7, count 0 2006.189.08:08:59.26#ibcon#read 3, iclass 7, count 0 2006.189.08:08:59.26#ibcon#about to read 4, iclass 7, count 0 2006.189.08:08:59.26#ibcon#read 4, iclass 7, count 0 2006.189.08:08:59.26#ibcon#about to read 5, iclass 7, count 0 2006.189.08:08:59.26#ibcon#read 5, iclass 7, count 0 2006.189.08:08:59.26#ibcon#about to read 6, iclass 7, count 0 2006.189.08:08:59.26#ibcon#read 6, iclass 7, count 0 2006.189.08:08:59.26#ibcon#end of sib2, iclass 7, count 0 2006.189.08:08:59.26#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:08:59.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:08:59.26#ibcon#[25=USB\r\n] 2006.189.08:08:59.26#ibcon#*before write, iclass 7, count 0 2006.189.08:08:59.26#ibcon#enter sib2, iclass 7, count 0 2006.189.08:08:59.26#ibcon#flushed, iclass 7, count 0 2006.189.08:08:59.26#ibcon#about to write, iclass 7, count 0 2006.189.08:08:59.27#ibcon#wrote, iclass 7, count 0 2006.189.08:08:59.27#ibcon#about to read 3, iclass 7, count 0 2006.189.08:08:59.29#ibcon#read 3, iclass 7, count 0 2006.189.08:08:59.29#ibcon#about to read 4, iclass 7, count 0 2006.189.08:08:59.29#ibcon#read 4, iclass 7, count 0 2006.189.08:08:59.29#ibcon#about to read 5, iclass 7, count 0 2006.189.08:08:59.29#ibcon#read 5, iclass 7, count 0 2006.189.08:08:59.29#ibcon#about to read 6, iclass 7, count 0 2006.189.08:08:59.29#ibcon#read 6, iclass 7, count 0 2006.189.08:08:59.29#ibcon#end of sib2, iclass 7, count 0 2006.189.08:08:59.29#ibcon#*after write, iclass 7, count 0 2006.189.08:08:59.29#ibcon#*before return 0, iclass 7, count 0 2006.189.08:08:59.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:08:59.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:08:59.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:08:59.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:08:59.30$vc4f8/valo=5,652.99 2006.189.08:08:59.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.08:08:59.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.08:08:59.30#ibcon#ireg 17 cls_cnt 0 2006.189.08:08:59.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:08:59.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:08:59.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:08:59.30#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:08:59.30#ibcon#first serial, iclass 11, count 0 2006.189.08:08:59.30#ibcon#enter sib2, iclass 11, count 0 2006.189.08:08:59.30#ibcon#flushed, iclass 11, count 0 2006.189.08:08:59.30#ibcon#about to write, iclass 11, count 0 2006.189.08:08:59.30#ibcon#wrote, iclass 11, count 0 2006.189.08:08:59.30#ibcon#about to read 3, iclass 11, count 0 2006.189.08:08:59.31#ibcon#read 3, iclass 11, count 0 2006.189.08:08:59.31#ibcon#about to read 4, iclass 11, count 0 2006.189.08:08:59.31#ibcon#read 4, iclass 11, count 0 2006.189.08:08:59.31#ibcon#about to read 5, iclass 11, count 0 2006.189.08:08:59.31#ibcon#read 5, iclass 11, count 0 2006.189.08:08:59.31#ibcon#about to read 6, iclass 11, count 0 2006.189.08:08:59.31#ibcon#read 6, iclass 11, count 0 2006.189.08:08:59.31#ibcon#end of sib2, iclass 11, count 0 2006.189.08:08:59.31#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:08:59.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:08:59.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:08:59.31#ibcon#*before write, iclass 11, count 0 2006.189.08:08:59.31#ibcon#enter sib2, iclass 11, count 0 2006.189.08:08:59.31#ibcon#flushed, iclass 11, count 0 2006.189.08:08:59.32#ibcon#about to write, iclass 11, count 0 2006.189.08:08:59.32#ibcon#wrote, iclass 11, count 0 2006.189.08:08:59.32#ibcon#about to read 3, iclass 11, count 0 2006.189.08:08:59.35#ibcon#read 3, iclass 11, count 0 2006.189.08:08:59.35#ibcon#about to read 4, iclass 11, count 0 2006.189.08:08:59.35#ibcon#read 4, iclass 11, count 0 2006.189.08:08:59.35#ibcon#about to read 5, iclass 11, count 0 2006.189.08:08:59.35#ibcon#read 5, iclass 11, count 0 2006.189.08:08:59.35#ibcon#about to read 6, iclass 11, count 0 2006.189.08:08:59.35#ibcon#read 6, iclass 11, count 0 2006.189.08:08:59.35#ibcon#end of sib2, iclass 11, count 0 2006.189.08:08:59.35#ibcon#*after write, iclass 11, count 0 2006.189.08:08:59.35#ibcon#*before return 0, iclass 11, count 0 2006.189.08:08:59.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:08:59.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:08:59.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:08:59.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:08:59.36$vc4f8/va=5,7 2006.189.08:08:59.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.08:08:59.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.08:08:59.36#ibcon#ireg 11 cls_cnt 2 2006.189.08:08:59.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:08:59.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:08:59.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:08:59.40#ibcon#enter wrdev, iclass 13, count 2 2006.189.08:08:59.40#ibcon#first serial, iclass 13, count 2 2006.189.08:08:59.40#ibcon#enter sib2, iclass 13, count 2 2006.189.08:08:59.40#ibcon#flushed, iclass 13, count 2 2006.189.08:08:59.40#ibcon#about to write, iclass 13, count 2 2006.189.08:08:59.40#ibcon#wrote, iclass 13, count 2 2006.189.08:08:59.40#ibcon#about to read 3, iclass 13, count 2 2006.189.08:08:59.42#ibcon#read 3, iclass 13, count 2 2006.189.08:08:59.42#ibcon#about to read 4, iclass 13, count 2 2006.189.08:08:59.42#ibcon#read 4, iclass 13, count 2 2006.189.08:08:59.42#ibcon#about to read 5, iclass 13, count 2 2006.189.08:08:59.42#ibcon#read 5, iclass 13, count 2 2006.189.08:08:59.42#ibcon#about to read 6, iclass 13, count 2 2006.189.08:08:59.42#ibcon#read 6, iclass 13, count 2 2006.189.08:08:59.42#ibcon#end of sib2, iclass 13, count 2 2006.189.08:08:59.42#ibcon#*mode == 0, iclass 13, count 2 2006.189.08:08:59.42#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.08:08:59.42#ibcon#[25=AT05-07\r\n] 2006.189.08:08:59.42#ibcon#*before write, iclass 13, count 2 2006.189.08:08:59.42#ibcon#enter sib2, iclass 13, count 2 2006.189.08:08:59.42#ibcon#flushed, iclass 13, count 2 2006.189.08:08:59.43#ibcon#about to write, iclass 13, count 2 2006.189.08:08:59.43#ibcon#wrote, iclass 13, count 2 2006.189.08:08:59.43#ibcon#about to read 3, iclass 13, count 2 2006.189.08:08:59.46#ibcon#read 3, iclass 13, count 2 2006.189.08:08:59.46#ibcon#about to read 4, iclass 13, count 2 2006.189.08:08:59.46#ibcon#read 4, iclass 13, count 2 2006.189.08:08:59.46#ibcon#about to read 5, iclass 13, count 2 2006.189.08:08:59.46#ibcon#read 5, iclass 13, count 2 2006.189.08:08:59.46#ibcon#about to read 6, iclass 13, count 2 2006.189.08:08:59.46#ibcon#read 6, iclass 13, count 2 2006.189.08:08:59.46#ibcon#end of sib2, iclass 13, count 2 2006.189.08:08:59.46#ibcon#*after write, iclass 13, count 2 2006.189.08:08:59.46#ibcon#*before return 0, iclass 13, count 2 2006.189.08:08:59.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:08:59.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:08:59.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.08:08:59.46#ibcon#ireg 7 cls_cnt 0 2006.189.08:08:59.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:08:59.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:08:59.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:08:59.57#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:08:59.57#ibcon#first serial, iclass 13, count 0 2006.189.08:08:59.57#ibcon#enter sib2, iclass 13, count 0 2006.189.08:08:59.57#ibcon#flushed, iclass 13, count 0 2006.189.08:08:59.57#ibcon#about to write, iclass 13, count 0 2006.189.08:08:59.57#ibcon#wrote, iclass 13, count 0 2006.189.08:08:59.57#ibcon#about to read 3, iclass 13, count 0 2006.189.08:08:59.59#ibcon#read 3, iclass 13, count 0 2006.189.08:08:59.59#ibcon#about to read 4, iclass 13, count 0 2006.189.08:08:59.59#ibcon#read 4, iclass 13, count 0 2006.189.08:08:59.59#ibcon#about to read 5, iclass 13, count 0 2006.189.08:08:59.59#ibcon#read 5, iclass 13, count 0 2006.189.08:08:59.59#ibcon#about to read 6, iclass 13, count 0 2006.189.08:08:59.59#ibcon#read 6, iclass 13, count 0 2006.189.08:08:59.59#ibcon#end of sib2, iclass 13, count 0 2006.189.08:08:59.59#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:08:59.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:08:59.59#ibcon#[25=USB\r\n] 2006.189.08:08:59.59#ibcon#*before write, iclass 13, count 0 2006.189.08:08:59.59#ibcon#enter sib2, iclass 13, count 0 2006.189.08:08:59.59#ibcon#flushed, iclass 13, count 0 2006.189.08:08:59.59#ibcon#about to write, iclass 13, count 0 2006.189.08:08:59.60#ibcon#wrote, iclass 13, count 0 2006.189.08:08:59.60#ibcon#about to read 3, iclass 13, count 0 2006.189.08:08:59.62#ibcon#read 3, iclass 13, count 0 2006.189.08:08:59.62#ibcon#about to read 4, iclass 13, count 0 2006.189.08:08:59.62#ibcon#read 4, iclass 13, count 0 2006.189.08:08:59.62#ibcon#about to read 5, iclass 13, count 0 2006.189.08:08:59.62#ibcon#read 5, iclass 13, count 0 2006.189.08:08:59.62#ibcon#about to read 6, iclass 13, count 0 2006.189.08:08:59.62#ibcon#read 6, iclass 13, count 0 2006.189.08:08:59.62#ibcon#end of sib2, iclass 13, count 0 2006.189.08:08:59.62#ibcon#*after write, iclass 13, count 0 2006.189.08:08:59.62#ibcon#*before return 0, iclass 13, count 0 2006.189.08:08:59.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:08:59.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:08:59.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:08:59.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:08:59.63$vc4f8/valo=6,772.99 2006.189.08:08:59.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.08:08:59.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.08:08:59.63#ibcon#ireg 17 cls_cnt 0 2006.189.08:08:59.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:08:59.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:08:59.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:08:59.63#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:08:59.63#ibcon#first serial, iclass 15, count 0 2006.189.08:08:59.63#ibcon#enter sib2, iclass 15, count 0 2006.189.08:08:59.63#ibcon#flushed, iclass 15, count 0 2006.189.08:08:59.63#ibcon#about to write, iclass 15, count 0 2006.189.08:08:59.63#ibcon#wrote, iclass 15, count 0 2006.189.08:08:59.63#ibcon#about to read 3, iclass 15, count 0 2006.189.08:08:59.64#ibcon#read 3, iclass 15, count 0 2006.189.08:08:59.64#ibcon#about to read 4, iclass 15, count 0 2006.189.08:08:59.64#ibcon#read 4, iclass 15, count 0 2006.189.08:08:59.64#ibcon#about to read 5, iclass 15, count 0 2006.189.08:08:59.64#ibcon#read 5, iclass 15, count 0 2006.189.08:08:59.64#ibcon#about to read 6, iclass 15, count 0 2006.189.08:08:59.64#ibcon#read 6, iclass 15, count 0 2006.189.08:08:59.64#ibcon#end of sib2, iclass 15, count 0 2006.189.08:08:59.64#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:08:59.64#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:08:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:08:59.65#ibcon#*before write, iclass 15, count 0 2006.189.08:08:59.65#ibcon#enter sib2, iclass 15, count 0 2006.189.08:08:59.65#ibcon#flushed, iclass 15, count 0 2006.189.08:08:59.65#ibcon#about to write, iclass 15, count 0 2006.189.08:08:59.65#ibcon#wrote, iclass 15, count 0 2006.189.08:08:59.65#ibcon#about to read 3, iclass 15, count 0 2006.189.08:08:59.68#ibcon#read 3, iclass 15, count 0 2006.189.08:08:59.68#ibcon#about to read 4, iclass 15, count 0 2006.189.08:08:59.68#ibcon#read 4, iclass 15, count 0 2006.189.08:08:59.68#ibcon#about to read 5, iclass 15, count 0 2006.189.08:08:59.68#ibcon#read 5, iclass 15, count 0 2006.189.08:08:59.68#ibcon#about to read 6, iclass 15, count 0 2006.189.08:08:59.68#ibcon#read 6, iclass 15, count 0 2006.189.08:08:59.68#ibcon#end of sib2, iclass 15, count 0 2006.189.08:08:59.68#ibcon#*after write, iclass 15, count 0 2006.189.08:08:59.68#ibcon#*before return 0, iclass 15, count 0 2006.189.08:08:59.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:08:59.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:08:59.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:08:59.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:08:59.69$vc4f8/va=6,6 2006.189.08:08:59.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.08:08:59.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.08:08:59.69#ibcon#ireg 11 cls_cnt 2 2006.189.08:08:59.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:08:59.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:08:59.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:08:59.73#ibcon#enter wrdev, iclass 17, count 2 2006.189.08:08:59.73#ibcon#first serial, iclass 17, count 2 2006.189.08:08:59.73#ibcon#enter sib2, iclass 17, count 2 2006.189.08:08:59.73#ibcon#flushed, iclass 17, count 2 2006.189.08:08:59.73#ibcon#about to write, iclass 17, count 2 2006.189.08:08:59.73#ibcon#wrote, iclass 17, count 2 2006.189.08:08:59.73#ibcon#about to read 3, iclass 17, count 2 2006.189.08:08:59.75#ibcon#read 3, iclass 17, count 2 2006.189.08:08:59.75#ibcon#about to read 4, iclass 17, count 2 2006.189.08:08:59.75#ibcon#read 4, iclass 17, count 2 2006.189.08:08:59.75#ibcon#about to read 5, iclass 17, count 2 2006.189.08:08:59.75#ibcon#read 5, iclass 17, count 2 2006.189.08:08:59.75#ibcon#about to read 6, iclass 17, count 2 2006.189.08:08:59.75#ibcon#read 6, iclass 17, count 2 2006.189.08:08:59.75#ibcon#end of sib2, iclass 17, count 2 2006.189.08:08:59.75#ibcon#*mode == 0, iclass 17, count 2 2006.189.08:08:59.75#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.08:08:59.75#ibcon#[25=AT06-06\r\n] 2006.189.08:08:59.75#ibcon#*before write, iclass 17, count 2 2006.189.08:08:59.75#ibcon#enter sib2, iclass 17, count 2 2006.189.08:08:59.75#ibcon#flushed, iclass 17, count 2 2006.189.08:08:59.75#ibcon#about to write, iclass 17, count 2 2006.189.08:08:59.76#ibcon#wrote, iclass 17, count 2 2006.189.08:08:59.76#ibcon#about to read 3, iclass 17, count 2 2006.189.08:08:59.78#ibcon#read 3, iclass 17, count 2 2006.189.08:08:59.78#ibcon#about to read 4, iclass 17, count 2 2006.189.08:08:59.78#ibcon#read 4, iclass 17, count 2 2006.189.08:08:59.78#ibcon#about to read 5, iclass 17, count 2 2006.189.08:08:59.78#ibcon#read 5, iclass 17, count 2 2006.189.08:08:59.78#ibcon#about to read 6, iclass 17, count 2 2006.189.08:08:59.78#ibcon#read 6, iclass 17, count 2 2006.189.08:08:59.78#ibcon#end of sib2, iclass 17, count 2 2006.189.08:08:59.78#ibcon#*after write, iclass 17, count 2 2006.189.08:08:59.78#ibcon#*before return 0, iclass 17, count 2 2006.189.08:08:59.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:08:59.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:08:59.78#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.08:08:59.78#ibcon#ireg 7 cls_cnt 0 2006.189.08:08:59.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:08:59.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:08:59.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:08:59.89#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:08:59.89#ibcon#first serial, iclass 17, count 0 2006.189.08:08:59.89#ibcon#enter sib2, iclass 17, count 0 2006.189.08:08:59.89#ibcon#flushed, iclass 17, count 0 2006.189.08:08:59.89#ibcon#about to write, iclass 17, count 0 2006.189.08:08:59.89#ibcon#wrote, iclass 17, count 0 2006.189.08:08:59.89#ibcon#about to read 3, iclass 17, count 0 2006.189.08:08:59.91#ibcon#read 3, iclass 17, count 0 2006.189.08:08:59.91#ibcon#about to read 4, iclass 17, count 0 2006.189.08:08:59.91#ibcon#read 4, iclass 17, count 0 2006.189.08:08:59.91#ibcon#about to read 5, iclass 17, count 0 2006.189.08:08:59.91#ibcon#read 5, iclass 17, count 0 2006.189.08:08:59.91#ibcon#about to read 6, iclass 17, count 0 2006.189.08:08:59.91#ibcon#read 6, iclass 17, count 0 2006.189.08:08:59.91#ibcon#end of sib2, iclass 17, count 0 2006.189.08:08:59.91#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:08:59.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:08:59.91#ibcon#[25=USB\r\n] 2006.189.08:08:59.91#ibcon#*before write, iclass 17, count 0 2006.189.08:08:59.91#ibcon#enter sib2, iclass 17, count 0 2006.189.08:08:59.91#ibcon#flushed, iclass 17, count 0 2006.189.08:08:59.91#ibcon#about to write, iclass 17, count 0 2006.189.08:08:59.92#ibcon#wrote, iclass 17, count 0 2006.189.08:08:59.92#ibcon#about to read 3, iclass 17, count 0 2006.189.08:08:59.94#ibcon#read 3, iclass 17, count 0 2006.189.08:08:59.94#ibcon#about to read 4, iclass 17, count 0 2006.189.08:08:59.94#ibcon#read 4, iclass 17, count 0 2006.189.08:08:59.94#ibcon#about to read 5, iclass 17, count 0 2006.189.08:08:59.94#ibcon#read 5, iclass 17, count 0 2006.189.08:08:59.94#ibcon#about to read 6, iclass 17, count 0 2006.189.08:08:59.94#ibcon#read 6, iclass 17, count 0 2006.189.08:08:59.94#ibcon#end of sib2, iclass 17, count 0 2006.189.08:08:59.94#ibcon#*after write, iclass 17, count 0 2006.189.08:08:59.94#ibcon#*before return 0, iclass 17, count 0 2006.189.08:08:59.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:08:59.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:08:59.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:08:59.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:08:59.95$vc4f8/valo=7,832.99 2006.189.08:08:59.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.08:08:59.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.08:08:59.95#ibcon#ireg 17 cls_cnt 0 2006.189.08:08:59.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:08:59.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:08:59.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:08:59.95#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:08:59.95#ibcon#first serial, iclass 19, count 0 2006.189.08:08:59.95#ibcon#enter sib2, iclass 19, count 0 2006.189.08:08:59.95#ibcon#flushed, iclass 19, count 0 2006.189.08:08:59.95#ibcon#about to write, iclass 19, count 0 2006.189.08:08:59.95#ibcon#wrote, iclass 19, count 0 2006.189.08:08:59.95#ibcon#about to read 3, iclass 19, count 0 2006.189.08:08:59.96#ibcon#read 3, iclass 19, count 0 2006.189.08:08:59.96#ibcon#about to read 4, iclass 19, count 0 2006.189.08:08:59.96#ibcon#read 4, iclass 19, count 0 2006.189.08:08:59.96#ibcon#about to read 5, iclass 19, count 0 2006.189.08:08:59.96#ibcon#read 5, iclass 19, count 0 2006.189.08:08:59.96#ibcon#about to read 6, iclass 19, count 0 2006.189.08:08:59.96#ibcon#read 6, iclass 19, count 0 2006.189.08:08:59.96#ibcon#end of sib2, iclass 19, count 0 2006.189.08:08:59.96#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:08:59.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:08:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:08:59.96#ibcon#*before write, iclass 19, count 0 2006.189.08:08:59.96#ibcon#enter sib2, iclass 19, count 0 2006.189.08:08:59.96#ibcon#flushed, iclass 19, count 0 2006.189.08:08:59.97#ibcon#about to write, iclass 19, count 0 2006.189.08:08:59.97#ibcon#wrote, iclass 19, count 0 2006.189.08:08:59.97#ibcon#about to read 3, iclass 19, count 0 2006.189.08:09:00.00#ibcon#read 3, iclass 19, count 0 2006.189.08:09:00.00#ibcon#about to read 4, iclass 19, count 0 2006.189.08:09:00.00#ibcon#read 4, iclass 19, count 0 2006.189.08:09:00.00#ibcon#about to read 5, iclass 19, count 0 2006.189.08:09:00.00#ibcon#read 5, iclass 19, count 0 2006.189.08:09:00.00#ibcon#about to read 6, iclass 19, count 0 2006.189.08:09:00.00#ibcon#read 6, iclass 19, count 0 2006.189.08:09:00.00#ibcon#end of sib2, iclass 19, count 0 2006.189.08:09:00.00#ibcon#*after write, iclass 19, count 0 2006.189.08:09:00.00#ibcon#*before return 0, iclass 19, count 0 2006.189.08:09:00.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:09:00.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:09:00.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:09:00.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:09:00.01$vc4f8/va=7,6 2006.189.08:09:00.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.08:09:00.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.08:09:00.01#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:00.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:09:00.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:09:00.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:09:00.05#ibcon#enter wrdev, iclass 21, count 2 2006.189.08:09:00.05#ibcon#first serial, iclass 21, count 2 2006.189.08:09:00.05#ibcon#enter sib2, iclass 21, count 2 2006.189.08:09:00.05#ibcon#flushed, iclass 21, count 2 2006.189.08:09:00.05#ibcon#about to write, iclass 21, count 2 2006.189.08:09:00.05#ibcon#wrote, iclass 21, count 2 2006.189.08:09:00.05#ibcon#about to read 3, iclass 21, count 2 2006.189.08:09:00.07#ibcon#read 3, iclass 21, count 2 2006.189.08:09:00.07#ibcon#about to read 4, iclass 21, count 2 2006.189.08:09:00.07#ibcon#read 4, iclass 21, count 2 2006.189.08:09:00.07#ibcon#about to read 5, iclass 21, count 2 2006.189.08:09:00.07#ibcon#read 5, iclass 21, count 2 2006.189.08:09:00.07#ibcon#about to read 6, iclass 21, count 2 2006.189.08:09:00.07#ibcon#read 6, iclass 21, count 2 2006.189.08:09:00.07#ibcon#end of sib2, iclass 21, count 2 2006.189.08:09:00.07#ibcon#*mode == 0, iclass 21, count 2 2006.189.08:09:00.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.08:09:00.07#ibcon#[25=AT07-06\r\n] 2006.189.08:09:00.07#ibcon#*before write, iclass 21, count 2 2006.189.08:09:00.07#ibcon#enter sib2, iclass 21, count 2 2006.189.08:09:00.07#ibcon#flushed, iclass 21, count 2 2006.189.08:09:00.08#ibcon#about to write, iclass 21, count 2 2006.189.08:09:00.08#ibcon#wrote, iclass 21, count 2 2006.189.08:09:00.08#ibcon#about to read 3, iclass 21, count 2 2006.189.08:09:00.10#ibcon#read 3, iclass 21, count 2 2006.189.08:09:00.10#ibcon#about to read 4, iclass 21, count 2 2006.189.08:09:00.10#ibcon#read 4, iclass 21, count 2 2006.189.08:09:00.10#ibcon#about to read 5, iclass 21, count 2 2006.189.08:09:00.10#ibcon#read 5, iclass 21, count 2 2006.189.08:09:00.10#ibcon#about to read 6, iclass 21, count 2 2006.189.08:09:00.10#ibcon#read 6, iclass 21, count 2 2006.189.08:09:00.10#ibcon#end of sib2, iclass 21, count 2 2006.189.08:09:00.10#ibcon#*after write, iclass 21, count 2 2006.189.08:09:00.10#ibcon#*before return 0, iclass 21, count 2 2006.189.08:09:00.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:09:00.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:09:00.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.08:09:00.10#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:00.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:09:00.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:09:00.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:09:00.22#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:09:00.22#ibcon#first serial, iclass 21, count 0 2006.189.08:09:00.22#ibcon#enter sib2, iclass 21, count 0 2006.189.08:09:00.22#ibcon#flushed, iclass 21, count 0 2006.189.08:09:00.22#ibcon#about to write, iclass 21, count 0 2006.189.08:09:00.22#ibcon#wrote, iclass 21, count 0 2006.189.08:09:00.22#ibcon#about to read 3, iclass 21, count 0 2006.189.08:09:00.25#ibcon#read 3, iclass 21, count 0 2006.189.08:09:00.25#ibcon#about to read 4, iclass 21, count 0 2006.189.08:09:00.25#ibcon#read 4, iclass 21, count 0 2006.189.08:09:00.25#ibcon#about to read 5, iclass 21, count 0 2006.189.08:09:00.25#ibcon#read 5, iclass 21, count 0 2006.189.08:09:00.25#ibcon#about to read 6, iclass 21, count 0 2006.189.08:09:00.25#ibcon#read 6, iclass 21, count 0 2006.189.08:09:00.25#ibcon#end of sib2, iclass 21, count 0 2006.189.08:09:00.25#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:09:00.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:09:00.25#ibcon#[25=USB\r\n] 2006.189.08:09:00.25#ibcon#*before write, iclass 21, count 0 2006.189.08:09:00.25#ibcon#enter sib2, iclass 21, count 0 2006.189.08:09:00.25#ibcon#flushed, iclass 21, count 0 2006.189.08:09:00.25#ibcon#about to write, iclass 21, count 0 2006.189.08:09:00.25#ibcon#wrote, iclass 21, count 0 2006.189.08:09:00.25#ibcon#about to read 3, iclass 21, count 0 2006.189.08:09:00.28#ibcon#read 3, iclass 21, count 0 2006.189.08:09:00.28#ibcon#about to read 4, iclass 21, count 0 2006.189.08:09:00.28#ibcon#read 4, iclass 21, count 0 2006.189.08:09:00.28#ibcon#about to read 5, iclass 21, count 0 2006.189.08:09:00.28#ibcon#read 5, iclass 21, count 0 2006.189.08:09:00.28#ibcon#about to read 6, iclass 21, count 0 2006.189.08:09:00.28#ibcon#read 6, iclass 21, count 0 2006.189.08:09:00.28#ibcon#end of sib2, iclass 21, count 0 2006.189.08:09:00.28#ibcon#*after write, iclass 21, count 0 2006.189.08:09:00.28#ibcon#*before return 0, iclass 21, count 0 2006.189.08:09:00.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:09:00.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:09:00.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:09:00.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:09:00.29$vc4f8/valo=8,852.99 2006.189.08:09:00.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.08:09:00.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.08:09:00.29#ibcon#ireg 17 cls_cnt 0 2006.189.08:09:00.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:09:00.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:09:00.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:09:00.29#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:09:00.29#ibcon#first serial, iclass 23, count 0 2006.189.08:09:00.29#ibcon#enter sib2, iclass 23, count 0 2006.189.08:09:00.29#ibcon#flushed, iclass 23, count 0 2006.189.08:09:00.29#ibcon#about to write, iclass 23, count 0 2006.189.08:09:00.29#ibcon#wrote, iclass 23, count 0 2006.189.08:09:00.29#ibcon#about to read 3, iclass 23, count 0 2006.189.08:09:00.30#ibcon#read 3, iclass 23, count 0 2006.189.08:09:00.30#ibcon#about to read 4, iclass 23, count 0 2006.189.08:09:00.30#ibcon#read 4, iclass 23, count 0 2006.189.08:09:00.30#ibcon#about to read 5, iclass 23, count 0 2006.189.08:09:00.30#ibcon#read 5, iclass 23, count 0 2006.189.08:09:00.30#ibcon#about to read 6, iclass 23, count 0 2006.189.08:09:00.30#ibcon#read 6, iclass 23, count 0 2006.189.08:09:00.30#ibcon#end of sib2, iclass 23, count 0 2006.189.08:09:00.30#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:09:00.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:09:00.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:09:00.30#ibcon#*before write, iclass 23, count 0 2006.189.08:09:00.30#ibcon#enter sib2, iclass 23, count 0 2006.189.08:09:00.30#ibcon#flushed, iclass 23, count 0 2006.189.08:09:00.31#ibcon#about to write, iclass 23, count 0 2006.189.08:09:00.31#ibcon#wrote, iclass 23, count 0 2006.189.08:09:00.31#ibcon#about to read 3, iclass 23, count 0 2006.189.08:09:00.34#ibcon#read 3, iclass 23, count 0 2006.189.08:09:00.34#ibcon#about to read 4, iclass 23, count 0 2006.189.08:09:00.34#ibcon#read 4, iclass 23, count 0 2006.189.08:09:00.34#ibcon#about to read 5, iclass 23, count 0 2006.189.08:09:00.34#ibcon#read 5, iclass 23, count 0 2006.189.08:09:00.34#ibcon#about to read 6, iclass 23, count 0 2006.189.08:09:00.34#ibcon#read 6, iclass 23, count 0 2006.189.08:09:00.34#ibcon#end of sib2, iclass 23, count 0 2006.189.08:09:00.34#ibcon#*after write, iclass 23, count 0 2006.189.08:09:00.34#ibcon#*before return 0, iclass 23, count 0 2006.189.08:09:00.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:09:00.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:09:00.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:09:00.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:09:00.35$vc4f8/va=8,6 2006.189.08:09:00.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.08:09:00.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.08:09:00.35#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:00.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:09:00.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:09:00.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:09:00.39#ibcon#enter wrdev, iclass 25, count 2 2006.189.08:09:00.39#ibcon#first serial, iclass 25, count 2 2006.189.08:09:00.39#ibcon#enter sib2, iclass 25, count 2 2006.189.08:09:00.39#ibcon#flushed, iclass 25, count 2 2006.189.08:09:00.39#ibcon#about to write, iclass 25, count 2 2006.189.08:09:00.39#ibcon#wrote, iclass 25, count 2 2006.189.08:09:00.39#ibcon#about to read 3, iclass 25, count 2 2006.189.08:09:00.41#ibcon#read 3, iclass 25, count 2 2006.189.08:09:00.41#ibcon#about to read 4, iclass 25, count 2 2006.189.08:09:00.41#ibcon#read 4, iclass 25, count 2 2006.189.08:09:00.41#ibcon#about to read 5, iclass 25, count 2 2006.189.08:09:00.41#ibcon#read 5, iclass 25, count 2 2006.189.08:09:00.41#ibcon#about to read 6, iclass 25, count 2 2006.189.08:09:00.41#ibcon#read 6, iclass 25, count 2 2006.189.08:09:00.41#ibcon#end of sib2, iclass 25, count 2 2006.189.08:09:00.41#ibcon#*mode == 0, iclass 25, count 2 2006.189.08:09:00.41#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.08:09:00.41#ibcon#[25=AT08-06\r\n] 2006.189.08:09:00.41#ibcon#*before write, iclass 25, count 2 2006.189.08:09:00.41#ibcon#enter sib2, iclass 25, count 2 2006.189.08:09:00.41#ibcon#flushed, iclass 25, count 2 2006.189.08:09:00.41#ibcon#about to write, iclass 25, count 2 2006.189.08:09:00.42#ibcon#wrote, iclass 25, count 2 2006.189.08:09:00.42#ibcon#about to read 3, iclass 25, count 2 2006.189.08:09:00.44#ibcon#read 3, iclass 25, count 2 2006.189.08:09:00.44#ibcon#about to read 4, iclass 25, count 2 2006.189.08:09:00.44#ibcon#read 4, iclass 25, count 2 2006.189.08:09:00.44#ibcon#about to read 5, iclass 25, count 2 2006.189.08:09:00.44#ibcon#read 5, iclass 25, count 2 2006.189.08:09:00.44#ibcon#about to read 6, iclass 25, count 2 2006.189.08:09:00.44#ibcon#read 6, iclass 25, count 2 2006.189.08:09:00.44#ibcon#end of sib2, iclass 25, count 2 2006.189.08:09:00.44#ibcon#*after write, iclass 25, count 2 2006.189.08:09:00.44#ibcon#*before return 0, iclass 25, count 2 2006.189.08:09:00.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:09:00.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:09:00.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.08:09:00.44#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:00.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:09:00.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:09:00.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:09:00.55#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:09:00.55#ibcon#first serial, iclass 25, count 0 2006.189.08:09:00.55#ibcon#enter sib2, iclass 25, count 0 2006.189.08:09:00.55#ibcon#flushed, iclass 25, count 0 2006.189.08:09:00.55#ibcon#about to write, iclass 25, count 0 2006.189.08:09:00.55#ibcon#wrote, iclass 25, count 0 2006.189.08:09:00.55#ibcon#about to read 3, iclass 25, count 0 2006.189.08:09:00.57#ibcon#read 3, iclass 25, count 0 2006.189.08:09:00.57#ibcon#about to read 4, iclass 25, count 0 2006.189.08:09:00.57#ibcon#read 4, iclass 25, count 0 2006.189.08:09:00.57#ibcon#about to read 5, iclass 25, count 0 2006.189.08:09:00.57#ibcon#read 5, iclass 25, count 0 2006.189.08:09:00.57#ibcon#about to read 6, iclass 25, count 0 2006.189.08:09:00.57#ibcon#read 6, iclass 25, count 0 2006.189.08:09:00.57#ibcon#end of sib2, iclass 25, count 0 2006.189.08:09:00.57#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:09:00.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:09:00.57#ibcon#[25=USB\r\n] 2006.189.08:09:00.57#ibcon#*before write, iclass 25, count 0 2006.189.08:09:00.57#ibcon#enter sib2, iclass 25, count 0 2006.189.08:09:00.57#ibcon#flushed, iclass 25, count 0 2006.189.08:09:00.57#ibcon#about to write, iclass 25, count 0 2006.189.08:09:00.58#ibcon#wrote, iclass 25, count 0 2006.189.08:09:00.58#ibcon#about to read 3, iclass 25, count 0 2006.189.08:09:00.60#ibcon#read 3, iclass 25, count 0 2006.189.08:09:00.60#ibcon#about to read 4, iclass 25, count 0 2006.189.08:09:00.60#ibcon#read 4, iclass 25, count 0 2006.189.08:09:00.60#ibcon#about to read 5, iclass 25, count 0 2006.189.08:09:00.60#ibcon#read 5, iclass 25, count 0 2006.189.08:09:00.60#ibcon#about to read 6, iclass 25, count 0 2006.189.08:09:00.60#ibcon#read 6, iclass 25, count 0 2006.189.08:09:00.60#ibcon#end of sib2, iclass 25, count 0 2006.189.08:09:00.60#ibcon#*after write, iclass 25, count 0 2006.189.08:09:00.60#ibcon#*before return 0, iclass 25, count 0 2006.189.08:09:00.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:09:00.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:09:00.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:09:00.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:09:00.61$vc4f8/vblo=1,632.99 2006.189.08:09:00.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.08:09:00.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.08:09:00.61#ibcon#ireg 17 cls_cnt 0 2006.189.08:09:00.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:09:00.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:09:00.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:09:00.61#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:09:00.61#ibcon#first serial, iclass 27, count 0 2006.189.08:09:00.61#ibcon#enter sib2, iclass 27, count 0 2006.189.08:09:00.61#ibcon#flushed, iclass 27, count 0 2006.189.08:09:00.61#ibcon#about to write, iclass 27, count 0 2006.189.08:09:00.61#ibcon#wrote, iclass 27, count 0 2006.189.08:09:00.61#ibcon#about to read 3, iclass 27, count 0 2006.189.08:09:00.62#ibcon#read 3, iclass 27, count 0 2006.189.08:09:00.62#ibcon#about to read 4, iclass 27, count 0 2006.189.08:09:00.62#ibcon#read 4, iclass 27, count 0 2006.189.08:09:00.62#ibcon#about to read 5, iclass 27, count 0 2006.189.08:09:00.62#ibcon#read 5, iclass 27, count 0 2006.189.08:09:00.62#ibcon#about to read 6, iclass 27, count 0 2006.189.08:09:00.62#ibcon#read 6, iclass 27, count 0 2006.189.08:09:00.62#ibcon#end of sib2, iclass 27, count 0 2006.189.08:09:00.62#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:09:00.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:09:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:09:00.62#ibcon#*before write, iclass 27, count 0 2006.189.08:09:00.62#ibcon#enter sib2, iclass 27, count 0 2006.189.08:09:00.62#ibcon#flushed, iclass 27, count 0 2006.189.08:09:00.62#ibcon#about to write, iclass 27, count 0 2006.189.08:09:00.63#ibcon#wrote, iclass 27, count 0 2006.189.08:09:00.63#ibcon#about to read 3, iclass 27, count 0 2006.189.08:09:00.66#ibcon#read 3, iclass 27, count 0 2006.189.08:09:00.66#ibcon#about to read 4, iclass 27, count 0 2006.189.08:09:00.66#ibcon#read 4, iclass 27, count 0 2006.189.08:09:00.66#ibcon#about to read 5, iclass 27, count 0 2006.189.08:09:00.66#ibcon#read 5, iclass 27, count 0 2006.189.08:09:00.66#ibcon#about to read 6, iclass 27, count 0 2006.189.08:09:00.66#ibcon#read 6, iclass 27, count 0 2006.189.08:09:00.66#ibcon#end of sib2, iclass 27, count 0 2006.189.08:09:00.66#ibcon#*after write, iclass 27, count 0 2006.189.08:09:00.66#ibcon#*before return 0, iclass 27, count 0 2006.189.08:09:00.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:09:00.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:09:00.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:09:00.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:09:00.67$vc4f8/vb=1,4 2006.189.08:09:00.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.08:09:00.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.08:09:00.67#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:00.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:09:00.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:09:00.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:09:00.67#ibcon#enter wrdev, iclass 29, count 2 2006.189.08:09:00.67#ibcon#first serial, iclass 29, count 2 2006.189.08:09:00.67#ibcon#enter sib2, iclass 29, count 2 2006.189.08:09:00.67#ibcon#flushed, iclass 29, count 2 2006.189.08:09:00.67#ibcon#about to write, iclass 29, count 2 2006.189.08:09:00.67#ibcon#wrote, iclass 29, count 2 2006.189.08:09:00.67#ibcon#about to read 3, iclass 29, count 2 2006.189.08:09:00.68#ibcon#read 3, iclass 29, count 2 2006.189.08:09:00.68#ibcon#about to read 4, iclass 29, count 2 2006.189.08:09:00.68#ibcon#read 4, iclass 29, count 2 2006.189.08:09:00.68#ibcon#about to read 5, iclass 29, count 2 2006.189.08:09:00.68#ibcon#read 5, iclass 29, count 2 2006.189.08:09:00.68#ibcon#about to read 6, iclass 29, count 2 2006.189.08:09:00.68#ibcon#read 6, iclass 29, count 2 2006.189.08:09:00.68#ibcon#end of sib2, iclass 29, count 2 2006.189.08:09:00.68#ibcon#*mode == 0, iclass 29, count 2 2006.189.08:09:00.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.08:09:00.68#ibcon#[27=AT01-04\r\n] 2006.189.08:09:00.68#ibcon#*before write, iclass 29, count 2 2006.189.08:09:00.68#ibcon#enter sib2, iclass 29, count 2 2006.189.08:09:00.68#ibcon#flushed, iclass 29, count 2 2006.189.08:09:00.68#ibcon#about to write, iclass 29, count 2 2006.189.08:09:00.69#ibcon#wrote, iclass 29, count 2 2006.189.08:09:00.69#ibcon#about to read 3, iclass 29, count 2 2006.189.08:09:00.71#ibcon#read 3, iclass 29, count 2 2006.189.08:09:00.71#ibcon#about to read 4, iclass 29, count 2 2006.189.08:09:00.71#ibcon#read 4, iclass 29, count 2 2006.189.08:09:00.71#ibcon#about to read 5, iclass 29, count 2 2006.189.08:09:00.71#ibcon#read 5, iclass 29, count 2 2006.189.08:09:00.71#ibcon#about to read 6, iclass 29, count 2 2006.189.08:09:00.71#ibcon#read 6, iclass 29, count 2 2006.189.08:09:00.71#ibcon#end of sib2, iclass 29, count 2 2006.189.08:09:00.71#ibcon#*after write, iclass 29, count 2 2006.189.08:09:00.71#ibcon#*before return 0, iclass 29, count 2 2006.189.08:09:00.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:09:00.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:09:00.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.08:09:00.71#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:00.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:09:00.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:09:00.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:09:00.82#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:09:00.82#ibcon#first serial, iclass 29, count 0 2006.189.08:09:00.82#ibcon#enter sib2, iclass 29, count 0 2006.189.08:09:00.82#ibcon#flushed, iclass 29, count 0 2006.189.08:09:00.82#ibcon#about to write, iclass 29, count 0 2006.189.08:09:00.82#ibcon#wrote, iclass 29, count 0 2006.189.08:09:00.82#ibcon#about to read 3, iclass 29, count 0 2006.189.08:09:00.84#ibcon#read 3, iclass 29, count 0 2006.189.08:09:00.84#ibcon#about to read 4, iclass 29, count 0 2006.189.08:09:00.84#ibcon#read 4, iclass 29, count 0 2006.189.08:09:00.84#ibcon#about to read 5, iclass 29, count 0 2006.189.08:09:00.84#ibcon#read 5, iclass 29, count 0 2006.189.08:09:00.84#ibcon#about to read 6, iclass 29, count 0 2006.189.08:09:00.84#ibcon#read 6, iclass 29, count 0 2006.189.08:09:00.84#ibcon#end of sib2, iclass 29, count 0 2006.189.08:09:00.84#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:09:00.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:09:00.84#ibcon#[27=USB\r\n] 2006.189.08:09:00.84#ibcon#*before write, iclass 29, count 0 2006.189.08:09:00.84#ibcon#enter sib2, iclass 29, count 0 2006.189.08:09:00.84#ibcon#flushed, iclass 29, count 0 2006.189.08:09:00.84#ibcon#about to write, iclass 29, count 0 2006.189.08:09:00.85#ibcon#wrote, iclass 29, count 0 2006.189.08:09:00.85#ibcon#about to read 3, iclass 29, count 0 2006.189.08:09:00.87#ibcon#read 3, iclass 29, count 0 2006.189.08:09:00.87#ibcon#about to read 4, iclass 29, count 0 2006.189.08:09:00.87#ibcon#read 4, iclass 29, count 0 2006.189.08:09:00.87#ibcon#about to read 5, iclass 29, count 0 2006.189.08:09:00.87#ibcon#read 5, iclass 29, count 0 2006.189.08:09:00.87#ibcon#about to read 6, iclass 29, count 0 2006.189.08:09:00.87#ibcon#read 6, iclass 29, count 0 2006.189.08:09:00.87#ibcon#end of sib2, iclass 29, count 0 2006.189.08:09:00.87#ibcon#*after write, iclass 29, count 0 2006.189.08:09:00.87#ibcon#*before return 0, iclass 29, count 0 2006.189.08:09:00.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:09:00.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:09:00.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:09:00.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:09:00.88$vc4f8/vblo=2,640.99 2006.189.08:09:00.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.08:09:00.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.08:09:00.88#ibcon#ireg 17 cls_cnt 0 2006.189.08:09:00.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:09:00.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:09:00.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:09:00.88#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:09:00.88#ibcon#first serial, iclass 31, count 0 2006.189.08:09:00.88#ibcon#enter sib2, iclass 31, count 0 2006.189.08:09:00.88#ibcon#flushed, iclass 31, count 0 2006.189.08:09:00.88#ibcon#about to write, iclass 31, count 0 2006.189.08:09:00.88#ibcon#wrote, iclass 31, count 0 2006.189.08:09:00.88#ibcon#about to read 3, iclass 31, count 0 2006.189.08:09:00.89#ibcon#read 3, iclass 31, count 0 2006.189.08:09:00.89#ibcon#about to read 4, iclass 31, count 0 2006.189.08:09:00.89#ibcon#read 4, iclass 31, count 0 2006.189.08:09:00.89#ibcon#about to read 5, iclass 31, count 0 2006.189.08:09:00.89#ibcon#read 5, iclass 31, count 0 2006.189.08:09:00.89#ibcon#about to read 6, iclass 31, count 0 2006.189.08:09:00.89#ibcon#read 6, iclass 31, count 0 2006.189.08:09:00.89#ibcon#end of sib2, iclass 31, count 0 2006.189.08:09:00.89#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:09:00.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:09:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:09:00.89#ibcon#*before write, iclass 31, count 0 2006.189.08:09:00.89#ibcon#enter sib2, iclass 31, count 0 2006.189.08:09:00.90#ibcon#flushed, iclass 31, count 0 2006.189.08:09:00.90#ibcon#about to write, iclass 31, count 0 2006.189.08:09:00.90#ibcon#wrote, iclass 31, count 0 2006.189.08:09:00.90#ibcon#about to read 3, iclass 31, count 0 2006.189.08:09:00.93#ibcon#read 3, iclass 31, count 0 2006.189.08:09:00.93#ibcon#about to read 4, iclass 31, count 0 2006.189.08:09:00.93#ibcon#read 4, iclass 31, count 0 2006.189.08:09:00.93#ibcon#about to read 5, iclass 31, count 0 2006.189.08:09:00.93#ibcon#read 5, iclass 31, count 0 2006.189.08:09:00.93#ibcon#about to read 6, iclass 31, count 0 2006.189.08:09:00.93#ibcon#read 6, iclass 31, count 0 2006.189.08:09:00.93#ibcon#end of sib2, iclass 31, count 0 2006.189.08:09:00.93#ibcon#*after write, iclass 31, count 0 2006.189.08:09:00.93#ibcon#*before return 0, iclass 31, count 0 2006.189.08:09:00.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:09:00.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:09:00.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:09:00.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:09:00.94$vc4f8/vb=2,4 2006.189.08:09:00.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.08:09:00.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.08:09:00.94#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:00.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:09:00.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:09:00.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:09:00.98#ibcon#enter wrdev, iclass 33, count 2 2006.189.08:09:00.98#ibcon#first serial, iclass 33, count 2 2006.189.08:09:00.98#ibcon#enter sib2, iclass 33, count 2 2006.189.08:09:00.98#ibcon#flushed, iclass 33, count 2 2006.189.08:09:00.98#ibcon#about to write, iclass 33, count 2 2006.189.08:09:00.98#ibcon#wrote, iclass 33, count 2 2006.189.08:09:00.98#ibcon#about to read 3, iclass 33, count 2 2006.189.08:09:01.01#ibcon#read 3, iclass 33, count 2 2006.189.08:09:01.01#ibcon#about to read 4, iclass 33, count 2 2006.189.08:09:01.01#ibcon#read 4, iclass 33, count 2 2006.189.08:09:01.01#ibcon#about to read 5, iclass 33, count 2 2006.189.08:09:01.01#ibcon#read 5, iclass 33, count 2 2006.189.08:09:01.01#ibcon#about to read 6, iclass 33, count 2 2006.189.08:09:01.01#ibcon#read 6, iclass 33, count 2 2006.189.08:09:01.01#ibcon#end of sib2, iclass 33, count 2 2006.189.08:09:01.01#ibcon#*mode == 0, iclass 33, count 2 2006.189.08:09:01.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.08:09:01.01#ibcon#[27=AT02-04\r\n] 2006.189.08:09:01.01#ibcon#*before write, iclass 33, count 2 2006.189.08:09:01.01#ibcon#enter sib2, iclass 33, count 2 2006.189.08:09:01.01#ibcon#flushed, iclass 33, count 2 2006.189.08:09:01.01#ibcon#about to write, iclass 33, count 2 2006.189.08:09:01.01#ibcon#wrote, iclass 33, count 2 2006.189.08:09:01.01#ibcon#about to read 3, iclass 33, count 2 2006.189.08:09:01.03#ibcon#read 3, iclass 33, count 2 2006.189.08:09:01.03#ibcon#about to read 4, iclass 33, count 2 2006.189.08:09:01.03#ibcon#read 4, iclass 33, count 2 2006.189.08:09:01.03#ibcon#about to read 5, iclass 33, count 2 2006.189.08:09:01.03#ibcon#read 5, iclass 33, count 2 2006.189.08:09:01.03#ibcon#about to read 6, iclass 33, count 2 2006.189.08:09:01.03#ibcon#read 6, iclass 33, count 2 2006.189.08:09:01.03#ibcon#end of sib2, iclass 33, count 2 2006.189.08:09:01.03#ibcon#*after write, iclass 33, count 2 2006.189.08:09:01.03#ibcon#*before return 0, iclass 33, count 2 2006.189.08:09:01.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:09:01.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:09:01.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.08:09:01.04#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:01.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:09:01.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:09:01.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:09:01.15#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:09:01.15#ibcon#first serial, iclass 33, count 0 2006.189.08:09:01.15#ibcon#enter sib2, iclass 33, count 0 2006.189.08:09:01.15#ibcon#flushed, iclass 33, count 0 2006.189.08:09:01.15#ibcon#about to write, iclass 33, count 0 2006.189.08:09:01.15#ibcon#wrote, iclass 33, count 0 2006.189.08:09:01.15#ibcon#about to read 3, iclass 33, count 0 2006.189.08:09:01.16#ibcon#read 3, iclass 33, count 0 2006.189.08:09:01.16#ibcon#about to read 4, iclass 33, count 0 2006.189.08:09:01.16#ibcon#read 4, iclass 33, count 0 2006.189.08:09:01.16#ibcon#about to read 5, iclass 33, count 0 2006.189.08:09:01.16#ibcon#read 5, iclass 33, count 0 2006.189.08:09:01.16#ibcon#about to read 6, iclass 33, count 0 2006.189.08:09:01.16#ibcon#read 6, iclass 33, count 0 2006.189.08:09:01.16#ibcon#end of sib2, iclass 33, count 0 2006.189.08:09:01.16#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:09:01.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:09:01.16#ibcon#[27=USB\r\n] 2006.189.08:09:01.16#ibcon#*before write, iclass 33, count 0 2006.189.08:09:01.16#ibcon#enter sib2, iclass 33, count 0 2006.189.08:09:01.16#ibcon#flushed, iclass 33, count 0 2006.189.08:09:01.17#ibcon#about to write, iclass 33, count 0 2006.189.08:09:01.17#ibcon#wrote, iclass 33, count 0 2006.189.08:09:01.17#ibcon#about to read 3, iclass 33, count 0 2006.189.08:09:01.19#ibcon#read 3, iclass 33, count 0 2006.189.08:09:01.19#ibcon#about to read 4, iclass 33, count 0 2006.189.08:09:01.19#ibcon#read 4, iclass 33, count 0 2006.189.08:09:01.19#ibcon#about to read 5, iclass 33, count 0 2006.189.08:09:01.19#ibcon#read 5, iclass 33, count 0 2006.189.08:09:01.19#ibcon#about to read 6, iclass 33, count 0 2006.189.08:09:01.19#ibcon#read 6, iclass 33, count 0 2006.189.08:09:01.19#ibcon#end of sib2, iclass 33, count 0 2006.189.08:09:01.19#ibcon#*after write, iclass 33, count 0 2006.189.08:09:01.19#ibcon#*before return 0, iclass 33, count 0 2006.189.08:09:01.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:09:01.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:09:01.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:09:01.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:09:01.20$vc4f8/vblo=3,656.99 2006.189.08:09:01.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.08:09:01.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.08:09:01.20#ibcon#ireg 17 cls_cnt 0 2006.189.08:09:01.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:09:01.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:09:01.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:09:01.20#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:09:01.20#ibcon#first serial, iclass 35, count 0 2006.189.08:09:01.20#ibcon#enter sib2, iclass 35, count 0 2006.189.08:09:01.20#ibcon#flushed, iclass 35, count 0 2006.189.08:09:01.20#ibcon#about to write, iclass 35, count 0 2006.189.08:09:01.20#ibcon#wrote, iclass 35, count 0 2006.189.08:09:01.20#ibcon#about to read 3, iclass 35, count 0 2006.189.08:09:01.21#ibcon#read 3, iclass 35, count 0 2006.189.08:09:01.21#ibcon#about to read 4, iclass 35, count 0 2006.189.08:09:01.21#ibcon#read 4, iclass 35, count 0 2006.189.08:09:01.21#ibcon#about to read 5, iclass 35, count 0 2006.189.08:09:01.21#ibcon#read 5, iclass 35, count 0 2006.189.08:09:01.21#ibcon#about to read 6, iclass 35, count 0 2006.189.08:09:01.21#ibcon#read 6, iclass 35, count 0 2006.189.08:09:01.21#ibcon#end of sib2, iclass 35, count 0 2006.189.08:09:01.21#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:09:01.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:09:01.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:09:01.21#ibcon#*before write, iclass 35, count 0 2006.189.08:09:01.21#ibcon#enter sib2, iclass 35, count 0 2006.189.08:09:01.21#ibcon#flushed, iclass 35, count 0 2006.189.08:09:01.22#ibcon#about to write, iclass 35, count 0 2006.189.08:09:01.22#ibcon#wrote, iclass 35, count 0 2006.189.08:09:01.22#ibcon#about to read 3, iclass 35, count 0 2006.189.08:09:01.25#ibcon#read 3, iclass 35, count 0 2006.189.08:09:01.25#ibcon#about to read 4, iclass 35, count 0 2006.189.08:09:01.25#ibcon#read 4, iclass 35, count 0 2006.189.08:09:01.25#ibcon#about to read 5, iclass 35, count 0 2006.189.08:09:01.25#ibcon#read 5, iclass 35, count 0 2006.189.08:09:01.25#ibcon#about to read 6, iclass 35, count 0 2006.189.08:09:01.25#ibcon#read 6, iclass 35, count 0 2006.189.08:09:01.25#ibcon#end of sib2, iclass 35, count 0 2006.189.08:09:01.25#ibcon#*after write, iclass 35, count 0 2006.189.08:09:01.25#ibcon#*before return 0, iclass 35, count 0 2006.189.08:09:01.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:09:01.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:09:01.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:09:01.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:09:01.26$vc4f8/vb=3,4 2006.189.08:09:01.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.08:09:01.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.08:09:01.26#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:01.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:09:01.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:09:01.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:09:01.30#ibcon#enter wrdev, iclass 37, count 2 2006.189.08:09:01.30#ibcon#first serial, iclass 37, count 2 2006.189.08:09:01.30#ibcon#enter sib2, iclass 37, count 2 2006.189.08:09:01.30#ibcon#flushed, iclass 37, count 2 2006.189.08:09:01.30#ibcon#about to write, iclass 37, count 2 2006.189.08:09:01.30#ibcon#wrote, iclass 37, count 2 2006.189.08:09:01.30#ibcon#about to read 3, iclass 37, count 2 2006.189.08:09:01.32#ibcon#read 3, iclass 37, count 2 2006.189.08:09:01.32#ibcon#about to read 4, iclass 37, count 2 2006.189.08:09:01.32#ibcon#read 4, iclass 37, count 2 2006.189.08:09:01.32#ibcon#about to read 5, iclass 37, count 2 2006.189.08:09:01.32#ibcon#read 5, iclass 37, count 2 2006.189.08:09:01.32#ibcon#about to read 6, iclass 37, count 2 2006.189.08:09:01.32#ibcon#read 6, iclass 37, count 2 2006.189.08:09:01.32#ibcon#end of sib2, iclass 37, count 2 2006.189.08:09:01.32#ibcon#*mode == 0, iclass 37, count 2 2006.189.08:09:01.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.08:09:01.32#ibcon#[27=AT03-04\r\n] 2006.189.08:09:01.32#ibcon#*before write, iclass 37, count 2 2006.189.08:09:01.32#ibcon#enter sib2, iclass 37, count 2 2006.189.08:09:01.32#ibcon#flushed, iclass 37, count 2 2006.189.08:09:01.32#ibcon#about to write, iclass 37, count 2 2006.189.08:09:01.33#ibcon#wrote, iclass 37, count 2 2006.189.08:09:01.33#ibcon#about to read 3, iclass 37, count 2 2006.189.08:09:01.35#ibcon#read 3, iclass 37, count 2 2006.189.08:09:01.35#ibcon#about to read 4, iclass 37, count 2 2006.189.08:09:01.35#ibcon#read 4, iclass 37, count 2 2006.189.08:09:01.35#ibcon#about to read 5, iclass 37, count 2 2006.189.08:09:01.35#ibcon#read 5, iclass 37, count 2 2006.189.08:09:01.35#ibcon#about to read 6, iclass 37, count 2 2006.189.08:09:01.35#ibcon#read 6, iclass 37, count 2 2006.189.08:09:01.35#ibcon#end of sib2, iclass 37, count 2 2006.189.08:09:01.35#ibcon#*after write, iclass 37, count 2 2006.189.08:09:01.35#ibcon#*before return 0, iclass 37, count 2 2006.189.08:09:01.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:09:01.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:09:01.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.08:09:01.35#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:01.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:09:01.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:09:01.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:09:01.47#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:09:01.47#ibcon#first serial, iclass 37, count 0 2006.189.08:09:01.47#ibcon#enter sib2, iclass 37, count 0 2006.189.08:09:01.47#ibcon#flushed, iclass 37, count 0 2006.189.08:09:01.47#ibcon#about to write, iclass 37, count 0 2006.189.08:09:01.47#ibcon#wrote, iclass 37, count 0 2006.189.08:09:01.47#ibcon#about to read 3, iclass 37, count 0 2006.189.08:09:01.49#ibcon#read 3, iclass 37, count 0 2006.189.08:09:01.49#ibcon#about to read 4, iclass 37, count 0 2006.189.08:09:01.49#ibcon#read 4, iclass 37, count 0 2006.189.08:09:01.49#ibcon#about to read 5, iclass 37, count 0 2006.189.08:09:01.49#ibcon#read 5, iclass 37, count 0 2006.189.08:09:01.49#ibcon#about to read 6, iclass 37, count 0 2006.189.08:09:01.49#ibcon#read 6, iclass 37, count 0 2006.189.08:09:01.49#ibcon#end of sib2, iclass 37, count 0 2006.189.08:09:01.49#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:09:01.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:09:01.49#ibcon#[27=USB\r\n] 2006.189.08:09:01.49#ibcon#*before write, iclass 37, count 0 2006.189.08:09:01.49#ibcon#enter sib2, iclass 37, count 0 2006.189.08:09:01.49#ibcon#flushed, iclass 37, count 0 2006.189.08:09:01.49#ibcon#about to write, iclass 37, count 0 2006.189.08:09:01.50#ibcon#wrote, iclass 37, count 0 2006.189.08:09:01.50#ibcon#about to read 3, iclass 37, count 0 2006.189.08:09:01.52#ibcon#read 3, iclass 37, count 0 2006.189.08:09:01.52#ibcon#about to read 4, iclass 37, count 0 2006.189.08:09:01.52#ibcon#read 4, iclass 37, count 0 2006.189.08:09:01.52#ibcon#about to read 5, iclass 37, count 0 2006.189.08:09:01.52#ibcon#read 5, iclass 37, count 0 2006.189.08:09:01.52#ibcon#about to read 6, iclass 37, count 0 2006.189.08:09:01.52#ibcon#read 6, iclass 37, count 0 2006.189.08:09:01.52#ibcon#end of sib2, iclass 37, count 0 2006.189.08:09:01.52#ibcon#*after write, iclass 37, count 0 2006.189.08:09:01.52#ibcon#*before return 0, iclass 37, count 0 2006.189.08:09:01.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:09:01.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:09:01.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:09:01.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:09:01.53$vc4f8/vblo=4,712.99 2006.189.08:09:01.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.08:09:01.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.08:09:01.53#ibcon#ireg 17 cls_cnt 0 2006.189.08:09:01.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:09:01.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:09:01.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:09:01.53#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:09:01.53#ibcon#first serial, iclass 39, count 0 2006.189.08:09:01.53#ibcon#enter sib2, iclass 39, count 0 2006.189.08:09:01.53#ibcon#flushed, iclass 39, count 0 2006.189.08:09:01.53#ibcon#about to write, iclass 39, count 0 2006.189.08:09:01.53#ibcon#wrote, iclass 39, count 0 2006.189.08:09:01.53#ibcon#about to read 3, iclass 39, count 0 2006.189.08:09:01.54#ibcon#read 3, iclass 39, count 0 2006.189.08:09:01.54#ibcon#about to read 4, iclass 39, count 0 2006.189.08:09:01.54#ibcon#read 4, iclass 39, count 0 2006.189.08:09:01.54#ibcon#about to read 5, iclass 39, count 0 2006.189.08:09:01.54#ibcon#read 5, iclass 39, count 0 2006.189.08:09:01.54#ibcon#about to read 6, iclass 39, count 0 2006.189.08:09:01.54#ibcon#read 6, iclass 39, count 0 2006.189.08:09:01.54#ibcon#end of sib2, iclass 39, count 0 2006.189.08:09:01.54#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:09:01.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:09:01.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:09:01.54#ibcon#*before write, iclass 39, count 0 2006.189.08:09:01.54#ibcon#enter sib2, iclass 39, count 0 2006.189.08:09:01.54#ibcon#flushed, iclass 39, count 0 2006.189.08:09:01.55#ibcon#about to write, iclass 39, count 0 2006.189.08:09:01.55#ibcon#wrote, iclass 39, count 0 2006.189.08:09:01.55#ibcon#about to read 3, iclass 39, count 0 2006.189.08:09:01.58#ibcon#read 3, iclass 39, count 0 2006.189.08:09:01.58#ibcon#about to read 4, iclass 39, count 0 2006.189.08:09:01.58#ibcon#read 4, iclass 39, count 0 2006.189.08:09:01.58#ibcon#about to read 5, iclass 39, count 0 2006.189.08:09:01.58#ibcon#read 5, iclass 39, count 0 2006.189.08:09:01.58#ibcon#about to read 6, iclass 39, count 0 2006.189.08:09:01.58#ibcon#read 6, iclass 39, count 0 2006.189.08:09:01.58#ibcon#end of sib2, iclass 39, count 0 2006.189.08:09:01.58#ibcon#*after write, iclass 39, count 0 2006.189.08:09:01.58#ibcon#*before return 0, iclass 39, count 0 2006.189.08:09:01.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:09:01.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:09:01.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:09:01.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:09:01.59$vc4f8/vb=4,4 2006.189.08:09:01.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.08:09:01.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.08:09:01.59#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:01.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:09:01.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:09:01.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:09:01.63#ibcon#enter wrdev, iclass 3, count 2 2006.189.08:09:01.63#ibcon#first serial, iclass 3, count 2 2006.189.08:09:01.63#ibcon#enter sib2, iclass 3, count 2 2006.189.08:09:01.63#ibcon#flushed, iclass 3, count 2 2006.189.08:09:01.63#ibcon#about to write, iclass 3, count 2 2006.189.08:09:01.63#ibcon#wrote, iclass 3, count 2 2006.189.08:09:01.63#ibcon#about to read 3, iclass 3, count 2 2006.189.08:09:01.65#ibcon#read 3, iclass 3, count 2 2006.189.08:09:01.65#ibcon#about to read 4, iclass 3, count 2 2006.189.08:09:01.65#ibcon#read 4, iclass 3, count 2 2006.189.08:09:01.65#ibcon#about to read 5, iclass 3, count 2 2006.189.08:09:01.65#ibcon#read 5, iclass 3, count 2 2006.189.08:09:01.65#ibcon#about to read 6, iclass 3, count 2 2006.189.08:09:01.65#ibcon#read 6, iclass 3, count 2 2006.189.08:09:01.65#ibcon#end of sib2, iclass 3, count 2 2006.189.08:09:01.65#ibcon#*mode == 0, iclass 3, count 2 2006.189.08:09:01.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.08:09:01.65#ibcon#[27=AT04-04\r\n] 2006.189.08:09:01.65#ibcon#*before write, iclass 3, count 2 2006.189.08:09:01.65#ibcon#enter sib2, iclass 3, count 2 2006.189.08:09:01.65#ibcon#flushed, iclass 3, count 2 2006.189.08:09:01.65#ibcon#about to write, iclass 3, count 2 2006.189.08:09:01.66#ibcon#wrote, iclass 3, count 2 2006.189.08:09:01.66#ibcon#about to read 3, iclass 3, count 2 2006.189.08:09:01.68#ibcon#read 3, iclass 3, count 2 2006.189.08:09:01.68#ibcon#about to read 4, iclass 3, count 2 2006.189.08:09:01.68#ibcon#read 4, iclass 3, count 2 2006.189.08:09:01.68#ibcon#about to read 5, iclass 3, count 2 2006.189.08:09:01.68#ibcon#read 5, iclass 3, count 2 2006.189.08:09:01.68#ibcon#about to read 6, iclass 3, count 2 2006.189.08:09:01.68#ibcon#read 6, iclass 3, count 2 2006.189.08:09:01.68#ibcon#end of sib2, iclass 3, count 2 2006.189.08:09:01.68#ibcon#*after write, iclass 3, count 2 2006.189.08:09:01.68#ibcon#*before return 0, iclass 3, count 2 2006.189.08:09:01.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:09:01.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:09:01.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.08:09:01.68#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:01.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:09:01.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:09:01.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:09:01.80#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:09:01.80#ibcon#first serial, iclass 3, count 0 2006.189.08:09:01.80#ibcon#enter sib2, iclass 3, count 0 2006.189.08:09:01.80#ibcon#flushed, iclass 3, count 0 2006.189.08:09:01.80#ibcon#about to write, iclass 3, count 0 2006.189.08:09:01.80#ibcon#wrote, iclass 3, count 0 2006.189.08:09:01.80#ibcon#about to read 3, iclass 3, count 0 2006.189.08:09:01.82#ibcon#read 3, iclass 3, count 0 2006.189.08:09:01.82#ibcon#about to read 4, iclass 3, count 0 2006.189.08:09:01.82#ibcon#read 4, iclass 3, count 0 2006.189.08:09:01.82#ibcon#about to read 5, iclass 3, count 0 2006.189.08:09:01.82#ibcon#read 5, iclass 3, count 0 2006.189.08:09:01.82#ibcon#about to read 6, iclass 3, count 0 2006.189.08:09:01.82#ibcon#read 6, iclass 3, count 0 2006.189.08:09:01.82#ibcon#end of sib2, iclass 3, count 0 2006.189.08:09:01.82#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:09:01.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:09:01.82#ibcon#[27=USB\r\n] 2006.189.08:09:01.82#ibcon#*before write, iclass 3, count 0 2006.189.08:09:01.82#ibcon#enter sib2, iclass 3, count 0 2006.189.08:09:01.82#ibcon#flushed, iclass 3, count 0 2006.189.08:09:01.82#ibcon#about to write, iclass 3, count 0 2006.189.08:09:01.83#ibcon#wrote, iclass 3, count 0 2006.189.08:09:01.83#ibcon#about to read 3, iclass 3, count 0 2006.189.08:09:01.85#ibcon#read 3, iclass 3, count 0 2006.189.08:09:01.85#ibcon#about to read 4, iclass 3, count 0 2006.189.08:09:01.85#ibcon#read 4, iclass 3, count 0 2006.189.08:09:01.85#ibcon#about to read 5, iclass 3, count 0 2006.189.08:09:01.85#ibcon#read 5, iclass 3, count 0 2006.189.08:09:01.85#ibcon#about to read 6, iclass 3, count 0 2006.189.08:09:01.85#ibcon#read 6, iclass 3, count 0 2006.189.08:09:01.85#ibcon#end of sib2, iclass 3, count 0 2006.189.08:09:01.85#ibcon#*after write, iclass 3, count 0 2006.189.08:09:01.85#ibcon#*before return 0, iclass 3, count 0 2006.189.08:09:01.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:09:01.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:09:01.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:09:01.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:09:01.86$vc4f8/vblo=5,744.99 2006.189.08:09:01.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.08:09:01.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.08:09:01.86#ibcon#ireg 17 cls_cnt 0 2006.189.08:09:01.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:09:01.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:09:01.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:09:01.86#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:09:01.86#ibcon#first serial, iclass 5, count 0 2006.189.08:09:01.86#ibcon#enter sib2, iclass 5, count 0 2006.189.08:09:01.86#ibcon#flushed, iclass 5, count 0 2006.189.08:09:01.86#ibcon#about to write, iclass 5, count 0 2006.189.08:09:01.86#ibcon#wrote, iclass 5, count 0 2006.189.08:09:01.86#ibcon#about to read 3, iclass 5, count 0 2006.189.08:09:01.87#ibcon#read 3, iclass 5, count 0 2006.189.08:09:01.87#ibcon#about to read 4, iclass 5, count 0 2006.189.08:09:01.87#ibcon#read 4, iclass 5, count 0 2006.189.08:09:01.87#ibcon#about to read 5, iclass 5, count 0 2006.189.08:09:01.87#ibcon#read 5, iclass 5, count 0 2006.189.08:09:01.87#ibcon#about to read 6, iclass 5, count 0 2006.189.08:09:01.87#ibcon#read 6, iclass 5, count 0 2006.189.08:09:01.87#ibcon#end of sib2, iclass 5, count 0 2006.189.08:09:01.87#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:09:01.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:09:01.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:09:01.87#ibcon#*before write, iclass 5, count 0 2006.189.08:09:01.87#ibcon#enter sib2, iclass 5, count 0 2006.189.08:09:01.87#ibcon#flushed, iclass 5, count 0 2006.189.08:09:01.87#ibcon#about to write, iclass 5, count 0 2006.189.08:09:01.88#ibcon#wrote, iclass 5, count 0 2006.189.08:09:01.88#ibcon#about to read 3, iclass 5, count 0 2006.189.08:09:01.91#ibcon#read 3, iclass 5, count 0 2006.189.08:09:01.91#ibcon#about to read 4, iclass 5, count 0 2006.189.08:09:01.91#ibcon#read 4, iclass 5, count 0 2006.189.08:09:01.91#ibcon#about to read 5, iclass 5, count 0 2006.189.08:09:01.91#ibcon#read 5, iclass 5, count 0 2006.189.08:09:01.91#ibcon#about to read 6, iclass 5, count 0 2006.189.08:09:01.91#ibcon#read 6, iclass 5, count 0 2006.189.08:09:01.91#ibcon#end of sib2, iclass 5, count 0 2006.189.08:09:01.91#ibcon#*after write, iclass 5, count 0 2006.189.08:09:01.91#ibcon#*before return 0, iclass 5, count 0 2006.189.08:09:01.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:09:01.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:09:01.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:09:01.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:09:01.92$vc4f8/vb=5,4 2006.189.08:09:01.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.08:09:01.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.08:09:01.92#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:01.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:09:01.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:09:01.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:09:01.96#ibcon#enter wrdev, iclass 7, count 2 2006.189.08:09:01.96#ibcon#first serial, iclass 7, count 2 2006.189.08:09:01.96#ibcon#enter sib2, iclass 7, count 2 2006.189.08:09:01.96#ibcon#flushed, iclass 7, count 2 2006.189.08:09:01.96#ibcon#about to write, iclass 7, count 2 2006.189.08:09:01.96#ibcon#wrote, iclass 7, count 2 2006.189.08:09:01.96#ibcon#about to read 3, iclass 7, count 2 2006.189.08:09:01.98#ibcon#read 3, iclass 7, count 2 2006.189.08:09:01.98#ibcon#about to read 4, iclass 7, count 2 2006.189.08:09:01.98#ibcon#read 4, iclass 7, count 2 2006.189.08:09:01.98#ibcon#about to read 5, iclass 7, count 2 2006.189.08:09:01.98#ibcon#read 5, iclass 7, count 2 2006.189.08:09:01.98#ibcon#about to read 6, iclass 7, count 2 2006.189.08:09:01.98#ibcon#read 6, iclass 7, count 2 2006.189.08:09:01.98#ibcon#end of sib2, iclass 7, count 2 2006.189.08:09:01.98#ibcon#*mode == 0, iclass 7, count 2 2006.189.08:09:01.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.08:09:01.98#ibcon#[27=AT05-04\r\n] 2006.189.08:09:01.98#ibcon#*before write, iclass 7, count 2 2006.189.08:09:01.98#ibcon#enter sib2, iclass 7, count 2 2006.189.08:09:01.98#ibcon#flushed, iclass 7, count 2 2006.189.08:09:01.98#ibcon#about to write, iclass 7, count 2 2006.189.08:09:01.99#ibcon#wrote, iclass 7, count 2 2006.189.08:09:01.99#ibcon#about to read 3, iclass 7, count 2 2006.189.08:09:02.01#ibcon#read 3, iclass 7, count 2 2006.189.08:09:02.01#ibcon#about to read 4, iclass 7, count 2 2006.189.08:09:02.01#ibcon#read 4, iclass 7, count 2 2006.189.08:09:02.01#ibcon#about to read 5, iclass 7, count 2 2006.189.08:09:02.01#ibcon#read 5, iclass 7, count 2 2006.189.08:09:02.01#ibcon#about to read 6, iclass 7, count 2 2006.189.08:09:02.01#ibcon#read 6, iclass 7, count 2 2006.189.08:09:02.01#ibcon#end of sib2, iclass 7, count 2 2006.189.08:09:02.01#ibcon#*after write, iclass 7, count 2 2006.189.08:09:02.01#ibcon#*before return 0, iclass 7, count 2 2006.189.08:09:02.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:09:02.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:09:02.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.08:09:02.01#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:02.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:09:02.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:09:02.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:09:02.14#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:09:02.14#ibcon#first serial, iclass 7, count 0 2006.189.08:09:02.14#ibcon#enter sib2, iclass 7, count 0 2006.189.08:09:02.14#ibcon#flushed, iclass 7, count 0 2006.189.08:09:02.14#ibcon#about to write, iclass 7, count 0 2006.189.08:09:02.14#ibcon#wrote, iclass 7, count 0 2006.189.08:09:02.14#ibcon#about to read 3, iclass 7, count 0 2006.189.08:09:02.15#ibcon#read 3, iclass 7, count 0 2006.189.08:09:02.15#ibcon#about to read 4, iclass 7, count 0 2006.189.08:09:02.15#ibcon#read 4, iclass 7, count 0 2006.189.08:09:02.15#ibcon#about to read 5, iclass 7, count 0 2006.189.08:09:02.15#ibcon#read 5, iclass 7, count 0 2006.189.08:09:02.15#ibcon#about to read 6, iclass 7, count 0 2006.189.08:09:02.15#ibcon#read 6, iclass 7, count 0 2006.189.08:09:02.15#ibcon#end of sib2, iclass 7, count 0 2006.189.08:09:02.15#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:09:02.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:09:02.15#ibcon#[27=USB\r\n] 2006.189.08:09:02.15#ibcon#*before write, iclass 7, count 0 2006.189.08:09:02.15#ibcon#enter sib2, iclass 7, count 0 2006.189.08:09:02.15#ibcon#flushed, iclass 7, count 0 2006.189.08:09:02.15#ibcon#about to write, iclass 7, count 0 2006.189.08:09:02.16#ibcon#wrote, iclass 7, count 0 2006.189.08:09:02.16#ibcon#about to read 3, iclass 7, count 0 2006.189.08:09:02.18#ibcon#read 3, iclass 7, count 0 2006.189.08:09:02.18#ibcon#about to read 4, iclass 7, count 0 2006.189.08:09:02.18#ibcon#read 4, iclass 7, count 0 2006.189.08:09:02.18#ibcon#about to read 5, iclass 7, count 0 2006.189.08:09:02.18#ibcon#read 5, iclass 7, count 0 2006.189.08:09:02.18#ibcon#about to read 6, iclass 7, count 0 2006.189.08:09:02.18#ibcon#read 6, iclass 7, count 0 2006.189.08:09:02.18#ibcon#end of sib2, iclass 7, count 0 2006.189.08:09:02.18#ibcon#*after write, iclass 7, count 0 2006.189.08:09:02.18#ibcon#*before return 0, iclass 7, count 0 2006.189.08:09:02.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:09:02.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:09:02.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:09:02.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:09:02.19$vc4f8/vblo=6,752.99 2006.189.08:09:02.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.08:09:02.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.08:09:02.19#ibcon#ireg 17 cls_cnt 0 2006.189.08:09:02.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:09:02.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:09:02.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:09:02.19#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:09:02.19#ibcon#first serial, iclass 11, count 0 2006.189.08:09:02.19#ibcon#enter sib2, iclass 11, count 0 2006.189.08:09:02.19#ibcon#flushed, iclass 11, count 0 2006.189.08:09:02.19#ibcon#about to write, iclass 11, count 0 2006.189.08:09:02.19#ibcon#wrote, iclass 11, count 0 2006.189.08:09:02.19#ibcon#about to read 3, iclass 11, count 0 2006.189.08:09:02.20#ibcon#read 3, iclass 11, count 0 2006.189.08:09:02.20#ibcon#about to read 4, iclass 11, count 0 2006.189.08:09:02.20#ibcon#read 4, iclass 11, count 0 2006.189.08:09:02.20#ibcon#about to read 5, iclass 11, count 0 2006.189.08:09:02.20#ibcon#read 5, iclass 11, count 0 2006.189.08:09:02.20#ibcon#about to read 6, iclass 11, count 0 2006.189.08:09:02.20#ibcon#read 6, iclass 11, count 0 2006.189.08:09:02.20#ibcon#end of sib2, iclass 11, count 0 2006.189.08:09:02.20#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:09:02.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:09:02.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:09:02.20#ibcon#*before write, iclass 11, count 0 2006.189.08:09:02.21#ibcon#enter sib2, iclass 11, count 0 2006.189.08:09:02.21#ibcon#flushed, iclass 11, count 0 2006.189.08:09:02.21#ibcon#about to write, iclass 11, count 0 2006.189.08:09:02.21#ibcon#wrote, iclass 11, count 0 2006.189.08:09:02.21#ibcon#about to read 3, iclass 11, count 0 2006.189.08:09:02.24#ibcon#read 3, iclass 11, count 0 2006.189.08:09:02.24#ibcon#about to read 4, iclass 11, count 0 2006.189.08:09:02.24#ibcon#read 4, iclass 11, count 0 2006.189.08:09:02.24#ibcon#about to read 5, iclass 11, count 0 2006.189.08:09:02.24#ibcon#read 5, iclass 11, count 0 2006.189.08:09:02.24#ibcon#about to read 6, iclass 11, count 0 2006.189.08:09:02.24#ibcon#read 6, iclass 11, count 0 2006.189.08:09:02.24#ibcon#end of sib2, iclass 11, count 0 2006.189.08:09:02.24#ibcon#*after write, iclass 11, count 0 2006.189.08:09:02.24#ibcon#*before return 0, iclass 11, count 0 2006.189.08:09:02.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:09:02.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:09:02.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:09:02.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:09:02.25$vc4f8/vb=6,4 2006.189.08:09:02.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.08:09:02.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.08:09:02.25#ibcon#ireg 11 cls_cnt 2 2006.189.08:09:02.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:09:02.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:09:02.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:09:02.29#ibcon#enter wrdev, iclass 13, count 2 2006.189.08:09:02.29#ibcon#first serial, iclass 13, count 2 2006.189.08:09:02.29#ibcon#enter sib2, iclass 13, count 2 2006.189.08:09:02.29#ibcon#flushed, iclass 13, count 2 2006.189.08:09:02.29#ibcon#about to write, iclass 13, count 2 2006.189.08:09:02.29#ibcon#wrote, iclass 13, count 2 2006.189.08:09:02.29#ibcon#about to read 3, iclass 13, count 2 2006.189.08:09:02.31#ibcon#read 3, iclass 13, count 2 2006.189.08:09:02.31#ibcon#about to read 4, iclass 13, count 2 2006.189.08:09:02.31#ibcon#read 4, iclass 13, count 2 2006.189.08:09:02.31#ibcon#about to read 5, iclass 13, count 2 2006.189.08:09:02.31#ibcon#read 5, iclass 13, count 2 2006.189.08:09:02.31#ibcon#about to read 6, iclass 13, count 2 2006.189.08:09:02.31#ibcon#read 6, iclass 13, count 2 2006.189.08:09:02.31#ibcon#end of sib2, iclass 13, count 2 2006.189.08:09:02.31#ibcon#*mode == 0, iclass 13, count 2 2006.189.08:09:02.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.08:09:02.31#ibcon#[27=AT06-04\r\n] 2006.189.08:09:02.31#ibcon#*before write, iclass 13, count 2 2006.189.08:09:02.31#ibcon#enter sib2, iclass 13, count 2 2006.189.08:09:02.31#ibcon#flushed, iclass 13, count 2 2006.189.08:09:02.31#ibcon#about to write, iclass 13, count 2 2006.189.08:09:02.32#ibcon#wrote, iclass 13, count 2 2006.189.08:09:02.32#ibcon#about to read 3, iclass 13, count 2 2006.189.08:09:02.34#ibcon#read 3, iclass 13, count 2 2006.189.08:09:02.34#ibcon#about to read 4, iclass 13, count 2 2006.189.08:09:02.34#ibcon#read 4, iclass 13, count 2 2006.189.08:09:02.34#ibcon#about to read 5, iclass 13, count 2 2006.189.08:09:02.34#ibcon#read 5, iclass 13, count 2 2006.189.08:09:02.34#ibcon#about to read 6, iclass 13, count 2 2006.189.08:09:02.34#ibcon#read 6, iclass 13, count 2 2006.189.08:09:02.34#ibcon#end of sib2, iclass 13, count 2 2006.189.08:09:02.34#ibcon#*after write, iclass 13, count 2 2006.189.08:09:02.34#ibcon#*before return 0, iclass 13, count 2 2006.189.08:09:02.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:09:02.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:09:02.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.08:09:02.34#ibcon#ireg 7 cls_cnt 0 2006.189.08:09:02.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:09:02.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:09:02.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:09:02.46#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:09:02.46#ibcon#first serial, iclass 13, count 0 2006.189.08:09:02.46#ibcon#enter sib2, iclass 13, count 0 2006.189.08:09:02.46#ibcon#flushed, iclass 13, count 0 2006.189.08:09:02.46#ibcon#about to write, iclass 13, count 0 2006.189.08:09:02.46#ibcon#wrote, iclass 13, count 0 2006.189.08:09:02.46#ibcon#about to read 3, iclass 13, count 0 2006.189.08:09:02.48#ibcon#read 3, iclass 13, count 0 2006.189.08:09:02.48#ibcon#about to read 4, iclass 13, count 0 2006.189.08:09:02.48#ibcon#read 4, iclass 13, count 0 2006.189.08:09:02.48#ibcon#about to read 5, iclass 13, count 0 2006.189.08:09:02.48#ibcon#read 5, iclass 13, count 0 2006.189.08:09:02.48#ibcon#about to read 6, iclass 13, count 0 2006.189.08:09:02.48#ibcon#read 6, iclass 13, count 0 2006.189.08:09:02.48#ibcon#end of sib2, iclass 13, count 0 2006.189.08:09:02.48#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:09:02.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:09:02.48#ibcon#[27=USB\r\n] 2006.189.08:09:02.48#ibcon#*before write, iclass 13, count 0 2006.189.08:09:02.48#ibcon#enter sib2, iclass 13, count 0 2006.189.08:09:02.48#ibcon#flushed, iclass 13, count 0 2006.189.08:09:02.48#ibcon#about to write, iclass 13, count 0 2006.189.08:09:02.49#ibcon#wrote, iclass 13, count 0 2006.189.08:09:02.49#ibcon#about to read 3, iclass 13, count 0 2006.189.08:09:02.51#ibcon#read 3, iclass 13, count 0 2006.189.08:09:02.51#ibcon#about to read 4, iclass 13, count 0 2006.189.08:09:02.51#ibcon#read 4, iclass 13, count 0 2006.189.08:09:02.51#ibcon#about to read 5, iclass 13, count 0 2006.189.08:09:02.51#ibcon#read 5, iclass 13, count 0 2006.189.08:09:02.51#ibcon#about to read 6, iclass 13, count 0 2006.189.08:09:02.51#ibcon#read 6, iclass 13, count 0 2006.189.08:09:02.51#ibcon#end of sib2, iclass 13, count 0 2006.189.08:09:02.51#ibcon#*after write, iclass 13, count 0 2006.189.08:09:02.51#ibcon#*before return 0, iclass 13, count 0 2006.189.08:09:02.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:09:02.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:09:02.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:09:02.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:09:02.52$vc4f8/vabw=wide 2006.189.08:09:02.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.08:09:02.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.08:09:02.52#ibcon#ireg 8 cls_cnt 0 2006.189.08:09:02.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:09:02.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:09:02.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:09:02.52#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:09:02.52#ibcon#first serial, iclass 15, count 0 2006.189.08:09:02.52#ibcon#enter sib2, iclass 15, count 0 2006.189.08:09:02.52#ibcon#flushed, iclass 15, count 0 2006.189.08:09:02.52#ibcon#about to write, iclass 15, count 0 2006.189.08:09:02.52#ibcon#wrote, iclass 15, count 0 2006.189.08:09:02.52#ibcon#about to read 3, iclass 15, count 0 2006.189.08:09:02.53#ibcon#read 3, iclass 15, count 0 2006.189.08:09:02.53#ibcon#about to read 4, iclass 15, count 0 2006.189.08:09:02.53#ibcon#read 4, iclass 15, count 0 2006.189.08:09:02.53#ibcon#about to read 5, iclass 15, count 0 2006.189.08:09:02.53#ibcon#read 5, iclass 15, count 0 2006.189.08:09:02.53#ibcon#about to read 6, iclass 15, count 0 2006.189.08:09:02.53#ibcon#read 6, iclass 15, count 0 2006.189.08:09:02.53#ibcon#end of sib2, iclass 15, count 0 2006.189.08:09:02.53#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:09:02.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:09:02.53#ibcon#[25=BW32\r\n] 2006.189.08:09:02.53#ibcon#*before write, iclass 15, count 0 2006.189.08:09:02.53#ibcon#enter sib2, iclass 15, count 0 2006.189.08:09:02.53#ibcon#flushed, iclass 15, count 0 2006.189.08:09:02.53#ibcon#about to write, iclass 15, count 0 2006.189.08:09:02.54#ibcon#wrote, iclass 15, count 0 2006.189.08:09:02.54#ibcon#about to read 3, iclass 15, count 0 2006.189.08:09:02.56#ibcon#read 3, iclass 15, count 0 2006.189.08:09:02.56#ibcon#about to read 4, iclass 15, count 0 2006.189.08:09:02.56#ibcon#read 4, iclass 15, count 0 2006.189.08:09:02.56#ibcon#about to read 5, iclass 15, count 0 2006.189.08:09:02.56#ibcon#read 5, iclass 15, count 0 2006.189.08:09:02.56#ibcon#about to read 6, iclass 15, count 0 2006.189.08:09:02.56#ibcon#read 6, iclass 15, count 0 2006.189.08:09:02.56#ibcon#end of sib2, iclass 15, count 0 2006.189.08:09:02.56#ibcon#*after write, iclass 15, count 0 2006.189.08:09:02.56#ibcon#*before return 0, iclass 15, count 0 2006.189.08:09:02.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:09:02.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:09:02.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:09:02.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:09:02.57$vc4f8/vbbw=wide 2006.189.08:09:02.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.08:09:02.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.08:09:02.57#ibcon#ireg 8 cls_cnt 0 2006.189.08:09:02.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:09:02.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:09:02.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:09:02.62#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:09:02.62#ibcon#first serial, iclass 17, count 0 2006.189.08:09:02.62#ibcon#enter sib2, iclass 17, count 0 2006.189.08:09:02.62#ibcon#flushed, iclass 17, count 0 2006.189.08:09:02.62#ibcon#about to write, iclass 17, count 0 2006.189.08:09:02.62#ibcon#wrote, iclass 17, count 0 2006.189.08:09:02.62#ibcon#about to read 3, iclass 17, count 0 2006.189.08:09:02.64#ibcon#read 3, iclass 17, count 0 2006.189.08:09:02.64#ibcon#about to read 4, iclass 17, count 0 2006.189.08:09:02.64#ibcon#read 4, iclass 17, count 0 2006.189.08:09:02.64#ibcon#about to read 5, iclass 17, count 0 2006.189.08:09:02.64#ibcon#read 5, iclass 17, count 0 2006.189.08:09:02.64#ibcon#about to read 6, iclass 17, count 0 2006.189.08:09:02.64#ibcon#read 6, iclass 17, count 0 2006.189.08:09:02.64#ibcon#end of sib2, iclass 17, count 0 2006.189.08:09:02.64#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:09:02.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:09:02.64#ibcon#[27=BW32\r\n] 2006.189.08:09:02.64#ibcon#*before write, iclass 17, count 0 2006.189.08:09:02.64#ibcon#enter sib2, iclass 17, count 0 2006.189.08:09:02.64#ibcon#flushed, iclass 17, count 0 2006.189.08:09:02.64#ibcon#about to write, iclass 17, count 0 2006.189.08:09:02.65#ibcon#wrote, iclass 17, count 0 2006.189.08:09:02.65#ibcon#about to read 3, iclass 17, count 0 2006.189.08:09:02.67#ibcon#read 3, iclass 17, count 0 2006.189.08:09:02.67#ibcon#about to read 4, iclass 17, count 0 2006.189.08:09:02.67#ibcon#read 4, iclass 17, count 0 2006.189.08:09:02.67#ibcon#about to read 5, iclass 17, count 0 2006.189.08:09:02.67#ibcon#read 5, iclass 17, count 0 2006.189.08:09:02.67#ibcon#about to read 6, iclass 17, count 0 2006.189.08:09:02.67#ibcon#read 6, iclass 17, count 0 2006.189.08:09:02.67#ibcon#end of sib2, iclass 17, count 0 2006.189.08:09:02.67#ibcon#*after write, iclass 17, count 0 2006.189.08:09:02.67#ibcon#*before return 0, iclass 17, count 0 2006.189.08:09:02.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:09:02.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:09:02.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:09:02.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:09:02.68$4f8m12a/ifd4f 2006.189.08:09:02.68$ifd4f/lo= 2006.189.08:09:02.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:09:02.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:09:02.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:09:02.68$ifd4f/patch= 2006.189.08:09:02.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:09:02.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:09:02.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:09:02.68$4f8m12a/"form=m,16.000,1:2 2006.189.08:09:02.68$4f8m12a/"tpicd 2006.189.08:09:02.68$4f8m12a/echo=off 2006.189.08:09:02.68$4f8m12a/xlog=off 2006.189.08:09:02.68:!2006.189.08:09:30 2006.189.08:09:10.13#trakl#Source acquired 2006.189.08:09:12.14#flagr#flagr/antenna,acquired 2006.189.08:09:30.02:preob 2006.189.08:09:31.14/onsource/TRACKING 2006.189.08:09:31.14:!2006.189.08:09:40 2006.189.08:09:40.02:data_valid=on 2006.189.08:09:40.02:midob 2006.189.08:09:41.14/onsource/TRACKING 2006.189.08:09:41.14/wx/25.54,1009.3,91 2006.189.08:09:41.28/cable/+6.4556E-03 2006.189.08:09:42.37/va/01,08,usb,yes,29,31 2006.189.08:09:42.37/va/02,07,usb,yes,29,31 2006.189.08:09:42.37/va/03,06,usb,yes,31,31 2006.189.08:09:42.37/va/04,07,usb,yes,30,32 2006.189.08:09:42.37/va/05,07,usb,yes,32,34 2006.189.08:09:42.37/va/06,06,usb,yes,31,31 2006.189.08:09:42.37/va/07,06,usb,yes,32,32 2006.189.08:09:42.37/va/08,06,usb,yes,34,33 2006.189.08:09:42.60/valo/01,532.99,yes,locked 2006.189.08:09:42.60/valo/02,572.99,yes,locked 2006.189.08:09:42.60/valo/03,672.99,yes,locked 2006.189.08:09:42.60/valo/04,832.99,yes,locked 2006.189.08:09:42.60/valo/05,652.99,yes,locked 2006.189.08:09:42.60/valo/06,772.99,yes,locked 2006.189.08:09:42.60/valo/07,832.99,yes,locked 2006.189.08:09:42.60/valo/08,852.99,yes,locked 2006.189.08:09:43.69/vb/01,04,usb,yes,29,28 2006.189.08:09:43.69/vb/02,04,usb,yes,31,32 2006.189.08:09:43.69/vb/03,04,usb,yes,27,31 2006.189.08:09:43.69/vb/04,04,usb,yes,28,28 2006.189.08:09:43.69/vb/05,04,usb,yes,27,31 2006.189.08:09:43.69/vb/06,04,usb,yes,28,30 2006.189.08:09:43.69/vb/07,04,usb,yes,30,29 2006.189.08:09:43.69/vb/08,04,usb,yes,27,31 2006.189.08:09:43.92/vblo/01,632.99,yes,locked 2006.189.08:09:43.92/vblo/02,640.99,yes,locked 2006.189.08:09:43.92/vblo/03,656.99,yes,locked 2006.189.08:09:43.92/vblo/04,712.99,yes,locked 2006.189.08:09:43.92/vblo/05,744.99,yes,locked 2006.189.08:09:43.92/vblo/06,752.99,yes,locked 2006.189.08:09:43.92/vblo/07,734.99,yes,locked 2006.189.08:09:43.92/vblo/08,744.99,yes,locked 2006.189.08:09:44.07/vabw/8 2006.189.08:09:44.22/vbbw/8 2006.189.08:09:44.31/xfe/off,on,15.5 2006.189.08:09:44.70/ifatt/23,28,28,28 2006.189.08:09:45.07/fmout-gps/S +2.97E-07 2006.189.08:09:45.16:!2006.189.08:10:40 2006.189.08:10:40.02:data_valid=off 2006.189.08:10:40.02:postob 2006.189.08:10:40.24/cable/+6.4559E-03 2006.189.08:10:40.25/wx/25.52,1009.3,91 2006.189.08:10:41.07/fmout-gps/S +2.96E-07 2006.189.08:10:41.08:scan_name=189-0811,k06189,110 2006.189.08:10:41.08:source=1004+141,100741.50,135629.6,2000.0,ccw 2006.189.08:10:42.14#flagr#flagr/antenna,new-source 2006.189.08:10:42.14:checkk5 2006.189.08:10:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:10:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:10:43.29/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:10:43.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:10:44.06/chk_obsdata//k5ts1/T1890809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:10:44.44/chk_obsdata//k5ts2/T1890809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:10:44.81/chk_obsdata//k5ts3/T1890809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:10:45.19/chk_obsdata//k5ts4/T1890809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:10:45.89/k5log//k5ts1_log_newline 2006.189.08:10:46.58/k5log//k5ts2_log_newline 2006.189.08:10:47.27/k5log//k5ts3_log_newline 2006.189.08:10:47.97/k5log//k5ts4_log_newline 2006.189.08:10:47.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:10:47.99:4f8m12a=2 2006.189.08:10:47.99$4f8m12a/echo=on 2006.189.08:10:47.99$4f8m12a/pcalon 2006.189.08:10:47.99$pcalon/"no phase cal control is implemented here 2006.189.08:10:47.99$4f8m12a/"tpicd=stop 2006.189.08:10:47.99$4f8m12a/vc4f8 2006.189.08:10:47.99$vc4f8/valo=1,532.99 2006.189.08:10:48.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.08:10:48.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.08:10:48.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:48.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:48.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:48.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:48.00#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:10:48.00#ibcon#first serial, iclass 24, count 0 2006.189.08:10:48.00#ibcon#enter sib2, iclass 24, count 0 2006.189.08:10:48.00#ibcon#flushed, iclass 24, count 0 2006.189.08:10:48.00#ibcon#about to write, iclass 24, count 0 2006.189.08:10:48.00#ibcon#wrote, iclass 24, count 0 2006.189.08:10:48.00#ibcon#about to read 3, iclass 24, count 0 2006.189.08:10:48.05#ibcon#read 3, iclass 24, count 0 2006.189.08:10:48.05#ibcon#about to read 4, iclass 24, count 0 2006.189.08:10:48.05#ibcon#read 4, iclass 24, count 0 2006.189.08:10:48.05#ibcon#about to read 5, iclass 24, count 0 2006.189.08:10:48.05#ibcon#read 5, iclass 24, count 0 2006.189.08:10:48.05#ibcon#about to read 6, iclass 24, count 0 2006.189.08:10:48.05#ibcon#read 6, iclass 24, count 0 2006.189.08:10:48.05#ibcon#end of sib2, iclass 24, count 0 2006.189.08:10:48.05#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:10:48.05#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:10:48.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:10:48.05#ibcon#*before write, iclass 24, count 0 2006.189.08:10:48.05#ibcon#enter sib2, iclass 24, count 0 2006.189.08:10:48.05#ibcon#flushed, iclass 24, count 0 2006.189.08:10:48.05#ibcon#about to write, iclass 24, count 0 2006.189.08:10:48.05#ibcon#wrote, iclass 24, count 0 2006.189.08:10:48.05#ibcon#about to read 3, iclass 24, count 0 2006.189.08:10:48.09#ibcon#read 3, iclass 24, count 0 2006.189.08:10:48.09#ibcon#about to read 4, iclass 24, count 0 2006.189.08:10:48.09#ibcon#read 4, iclass 24, count 0 2006.189.08:10:48.09#ibcon#about to read 5, iclass 24, count 0 2006.189.08:10:48.09#ibcon#read 5, iclass 24, count 0 2006.189.08:10:48.09#ibcon#about to read 6, iclass 24, count 0 2006.189.08:10:48.09#ibcon#read 6, iclass 24, count 0 2006.189.08:10:48.09#ibcon#end of sib2, iclass 24, count 0 2006.189.08:10:48.09#ibcon#*after write, iclass 24, count 0 2006.189.08:10:48.09#ibcon#*before return 0, iclass 24, count 0 2006.189.08:10:48.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:48.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:48.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:10:48.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:10:48.09$vc4f8/va=1,8 2006.189.08:10:48.09#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.08:10:48.09#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.08:10:48.09#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:48.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:48.09#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:48.09#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:48.09#ibcon#enter wrdev, iclass 26, count 2 2006.189.08:10:48.10#ibcon#first serial, iclass 26, count 2 2006.189.08:10:48.10#ibcon#enter sib2, iclass 26, count 2 2006.189.08:10:48.10#ibcon#flushed, iclass 26, count 2 2006.189.08:10:48.10#ibcon#about to write, iclass 26, count 2 2006.189.08:10:48.10#ibcon#wrote, iclass 26, count 2 2006.189.08:10:48.10#ibcon#about to read 3, iclass 26, count 2 2006.189.08:10:48.11#ibcon#read 3, iclass 26, count 2 2006.189.08:10:48.11#ibcon#about to read 4, iclass 26, count 2 2006.189.08:10:48.11#ibcon#read 4, iclass 26, count 2 2006.189.08:10:48.11#ibcon#about to read 5, iclass 26, count 2 2006.189.08:10:48.11#ibcon#read 5, iclass 26, count 2 2006.189.08:10:48.11#ibcon#about to read 6, iclass 26, count 2 2006.189.08:10:48.11#ibcon#read 6, iclass 26, count 2 2006.189.08:10:48.11#ibcon#end of sib2, iclass 26, count 2 2006.189.08:10:48.11#ibcon#*mode == 0, iclass 26, count 2 2006.189.08:10:48.11#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.08:10:48.11#ibcon#[25=AT01-08\r\n] 2006.189.08:10:48.11#ibcon#*before write, iclass 26, count 2 2006.189.08:10:48.11#ibcon#enter sib2, iclass 26, count 2 2006.189.08:10:48.11#ibcon#flushed, iclass 26, count 2 2006.189.08:10:48.11#ibcon#about to write, iclass 26, count 2 2006.189.08:10:48.11#ibcon#wrote, iclass 26, count 2 2006.189.08:10:48.11#ibcon#about to read 3, iclass 26, count 2 2006.189.08:10:48.14#ibcon#read 3, iclass 26, count 2 2006.189.08:10:48.14#ibcon#about to read 4, iclass 26, count 2 2006.189.08:10:48.14#ibcon#read 4, iclass 26, count 2 2006.189.08:10:48.14#ibcon#about to read 5, iclass 26, count 2 2006.189.08:10:48.14#ibcon#read 5, iclass 26, count 2 2006.189.08:10:48.14#ibcon#about to read 6, iclass 26, count 2 2006.189.08:10:48.14#ibcon#read 6, iclass 26, count 2 2006.189.08:10:48.14#ibcon#end of sib2, iclass 26, count 2 2006.189.08:10:48.14#ibcon#*after write, iclass 26, count 2 2006.189.08:10:48.14#ibcon#*before return 0, iclass 26, count 2 2006.189.08:10:48.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:48.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:48.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.08:10:48.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:48.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:48.26#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:48.26#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:48.26#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:10:48.26#ibcon#first serial, iclass 26, count 0 2006.189.08:10:48.26#ibcon#enter sib2, iclass 26, count 0 2006.189.08:10:48.26#ibcon#flushed, iclass 26, count 0 2006.189.08:10:48.26#ibcon#about to write, iclass 26, count 0 2006.189.08:10:48.26#ibcon#wrote, iclass 26, count 0 2006.189.08:10:48.26#ibcon#about to read 3, iclass 26, count 0 2006.189.08:10:48.28#ibcon#read 3, iclass 26, count 0 2006.189.08:10:48.28#ibcon#about to read 4, iclass 26, count 0 2006.189.08:10:48.28#ibcon#read 4, iclass 26, count 0 2006.189.08:10:48.28#ibcon#about to read 5, iclass 26, count 0 2006.189.08:10:48.28#ibcon#read 5, iclass 26, count 0 2006.189.08:10:48.28#ibcon#about to read 6, iclass 26, count 0 2006.189.08:10:48.28#ibcon#read 6, iclass 26, count 0 2006.189.08:10:48.28#ibcon#end of sib2, iclass 26, count 0 2006.189.08:10:48.28#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:10:48.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:10:48.28#ibcon#[25=USB\r\n] 2006.189.08:10:48.28#ibcon#*before write, iclass 26, count 0 2006.189.08:10:48.28#ibcon#enter sib2, iclass 26, count 0 2006.189.08:10:48.28#ibcon#flushed, iclass 26, count 0 2006.189.08:10:48.28#ibcon#about to write, iclass 26, count 0 2006.189.08:10:48.28#ibcon#wrote, iclass 26, count 0 2006.189.08:10:48.28#ibcon#about to read 3, iclass 26, count 0 2006.189.08:10:48.31#ibcon#read 3, iclass 26, count 0 2006.189.08:10:48.31#ibcon#about to read 4, iclass 26, count 0 2006.189.08:10:48.31#ibcon#read 4, iclass 26, count 0 2006.189.08:10:48.31#ibcon#about to read 5, iclass 26, count 0 2006.189.08:10:48.31#ibcon#read 5, iclass 26, count 0 2006.189.08:10:48.31#ibcon#about to read 6, iclass 26, count 0 2006.189.08:10:48.31#ibcon#read 6, iclass 26, count 0 2006.189.08:10:48.31#ibcon#end of sib2, iclass 26, count 0 2006.189.08:10:48.31#ibcon#*after write, iclass 26, count 0 2006.189.08:10:48.31#ibcon#*before return 0, iclass 26, count 0 2006.189.08:10:48.31#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:48.31#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:48.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:10:48.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:10:48.31$vc4f8/valo=2,572.99 2006.189.08:10:48.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.08:10:48.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.08:10:48.31#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:48.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:48.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:48.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:48.32#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:10:48.32#ibcon#first serial, iclass 28, count 0 2006.189.08:10:48.32#ibcon#enter sib2, iclass 28, count 0 2006.189.08:10:48.32#ibcon#flushed, iclass 28, count 0 2006.189.08:10:48.32#ibcon#about to write, iclass 28, count 0 2006.189.08:10:48.32#ibcon#wrote, iclass 28, count 0 2006.189.08:10:48.32#ibcon#about to read 3, iclass 28, count 0 2006.189.08:10:48.33#ibcon#read 3, iclass 28, count 0 2006.189.08:10:48.33#ibcon#about to read 4, iclass 28, count 0 2006.189.08:10:48.33#ibcon#read 4, iclass 28, count 0 2006.189.08:10:48.33#ibcon#about to read 5, iclass 28, count 0 2006.189.08:10:48.33#ibcon#read 5, iclass 28, count 0 2006.189.08:10:48.33#ibcon#about to read 6, iclass 28, count 0 2006.189.08:10:48.33#ibcon#read 6, iclass 28, count 0 2006.189.08:10:48.33#ibcon#end of sib2, iclass 28, count 0 2006.189.08:10:48.33#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:10:48.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:10:48.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:10:48.33#ibcon#*before write, iclass 28, count 0 2006.189.08:10:48.33#ibcon#enter sib2, iclass 28, count 0 2006.189.08:10:48.33#ibcon#flushed, iclass 28, count 0 2006.189.08:10:48.33#ibcon#about to write, iclass 28, count 0 2006.189.08:10:48.33#ibcon#wrote, iclass 28, count 0 2006.189.08:10:48.33#ibcon#about to read 3, iclass 28, count 0 2006.189.08:10:48.38#ibcon#read 3, iclass 28, count 0 2006.189.08:10:48.38#ibcon#about to read 4, iclass 28, count 0 2006.189.08:10:48.38#ibcon#read 4, iclass 28, count 0 2006.189.08:10:48.38#ibcon#about to read 5, iclass 28, count 0 2006.189.08:10:48.38#ibcon#read 5, iclass 28, count 0 2006.189.08:10:48.38#ibcon#about to read 6, iclass 28, count 0 2006.189.08:10:48.38#ibcon#read 6, iclass 28, count 0 2006.189.08:10:48.38#ibcon#end of sib2, iclass 28, count 0 2006.189.08:10:48.38#ibcon#*after write, iclass 28, count 0 2006.189.08:10:48.38#ibcon#*before return 0, iclass 28, count 0 2006.189.08:10:48.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:48.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:48.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:10:48.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:10:48.38$vc4f8/va=2,7 2006.189.08:10:48.38#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.08:10:48.38#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.08:10:48.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:48.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:48.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:48.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:48.42#ibcon#enter wrdev, iclass 30, count 2 2006.189.08:10:48.42#ibcon#first serial, iclass 30, count 2 2006.189.08:10:48.42#ibcon#enter sib2, iclass 30, count 2 2006.189.08:10:48.42#ibcon#flushed, iclass 30, count 2 2006.189.08:10:48.42#ibcon#about to write, iclass 30, count 2 2006.189.08:10:48.42#ibcon#wrote, iclass 30, count 2 2006.189.08:10:48.42#ibcon#about to read 3, iclass 30, count 2 2006.189.08:10:48.44#ibcon#read 3, iclass 30, count 2 2006.189.08:10:48.44#ibcon#about to read 4, iclass 30, count 2 2006.189.08:10:48.44#ibcon#read 4, iclass 30, count 2 2006.189.08:10:48.44#ibcon#about to read 5, iclass 30, count 2 2006.189.08:10:48.44#ibcon#read 5, iclass 30, count 2 2006.189.08:10:48.44#ibcon#about to read 6, iclass 30, count 2 2006.189.08:10:48.44#ibcon#read 6, iclass 30, count 2 2006.189.08:10:48.44#ibcon#end of sib2, iclass 30, count 2 2006.189.08:10:48.44#ibcon#*mode == 0, iclass 30, count 2 2006.189.08:10:48.44#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.08:10:48.44#ibcon#[25=AT02-07\r\n] 2006.189.08:10:48.44#ibcon#*before write, iclass 30, count 2 2006.189.08:10:48.44#ibcon#enter sib2, iclass 30, count 2 2006.189.08:10:48.44#ibcon#flushed, iclass 30, count 2 2006.189.08:10:48.44#ibcon#about to write, iclass 30, count 2 2006.189.08:10:48.44#ibcon#wrote, iclass 30, count 2 2006.189.08:10:48.44#ibcon#about to read 3, iclass 30, count 2 2006.189.08:10:48.47#ibcon#read 3, iclass 30, count 2 2006.189.08:10:48.47#ibcon#about to read 4, iclass 30, count 2 2006.189.08:10:48.47#ibcon#read 4, iclass 30, count 2 2006.189.08:10:48.47#ibcon#about to read 5, iclass 30, count 2 2006.189.08:10:48.47#ibcon#read 5, iclass 30, count 2 2006.189.08:10:48.47#ibcon#about to read 6, iclass 30, count 2 2006.189.08:10:48.47#ibcon#read 6, iclass 30, count 2 2006.189.08:10:48.47#ibcon#end of sib2, iclass 30, count 2 2006.189.08:10:48.47#ibcon#*after write, iclass 30, count 2 2006.189.08:10:48.47#ibcon#*before return 0, iclass 30, count 2 2006.189.08:10:48.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:48.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:48.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.08:10:48.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:48.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:48.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:48.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:48.59#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:10:48.59#ibcon#first serial, iclass 30, count 0 2006.189.08:10:48.59#ibcon#enter sib2, iclass 30, count 0 2006.189.08:10:48.59#ibcon#flushed, iclass 30, count 0 2006.189.08:10:48.59#ibcon#about to write, iclass 30, count 0 2006.189.08:10:48.59#ibcon#wrote, iclass 30, count 0 2006.189.08:10:48.59#ibcon#about to read 3, iclass 30, count 0 2006.189.08:10:48.61#ibcon#read 3, iclass 30, count 0 2006.189.08:10:48.61#ibcon#about to read 4, iclass 30, count 0 2006.189.08:10:48.61#ibcon#read 4, iclass 30, count 0 2006.189.08:10:48.61#ibcon#about to read 5, iclass 30, count 0 2006.189.08:10:48.61#ibcon#read 5, iclass 30, count 0 2006.189.08:10:48.61#ibcon#about to read 6, iclass 30, count 0 2006.189.08:10:48.61#ibcon#read 6, iclass 30, count 0 2006.189.08:10:48.61#ibcon#end of sib2, iclass 30, count 0 2006.189.08:10:48.61#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:10:48.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:10:48.61#ibcon#[25=USB\r\n] 2006.189.08:10:48.61#ibcon#*before write, iclass 30, count 0 2006.189.08:10:48.61#ibcon#enter sib2, iclass 30, count 0 2006.189.08:10:48.61#ibcon#flushed, iclass 30, count 0 2006.189.08:10:48.61#ibcon#about to write, iclass 30, count 0 2006.189.08:10:48.61#ibcon#wrote, iclass 30, count 0 2006.189.08:10:48.61#ibcon#about to read 3, iclass 30, count 0 2006.189.08:10:48.64#ibcon#read 3, iclass 30, count 0 2006.189.08:10:48.64#ibcon#about to read 4, iclass 30, count 0 2006.189.08:10:48.64#ibcon#read 4, iclass 30, count 0 2006.189.08:10:48.64#ibcon#about to read 5, iclass 30, count 0 2006.189.08:10:48.64#ibcon#read 5, iclass 30, count 0 2006.189.08:10:48.64#ibcon#about to read 6, iclass 30, count 0 2006.189.08:10:48.64#ibcon#read 6, iclass 30, count 0 2006.189.08:10:48.64#ibcon#end of sib2, iclass 30, count 0 2006.189.08:10:48.64#ibcon#*after write, iclass 30, count 0 2006.189.08:10:48.64#ibcon#*before return 0, iclass 30, count 0 2006.189.08:10:48.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:48.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:48.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:10:48.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:10:48.64$vc4f8/valo=3,672.99 2006.189.08:10:48.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.08:10:48.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.08:10:48.64#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:48.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:48.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:48.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:48.65#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:10:48.65#ibcon#first serial, iclass 32, count 0 2006.189.08:10:48.65#ibcon#enter sib2, iclass 32, count 0 2006.189.08:10:48.65#ibcon#flushed, iclass 32, count 0 2006.189.08:10:48.65#ibcon#about to write, iclass 32, count 0 2006.189.08:10:48.65#ibcon#wrote, iclass 32, count 0 2006.189.08:10:48.65#ibcon#about to read 3, iclass 32, count 0 2006.189.08:10:48.66#ibcon#read 3, iclass 32, count 0 2006.189.08:10:48.66#ibcon#about to read 4, iclass 32, count 0 2006.189.08:10:48.66#ibcon#read 4, iclass 32, count 0 2006.189.08:10:48.66#ibcon#about to read 5, iclass 32, count 0 2006.189.08:10:48.66#ibcon#read 5, iclass 32, count 0 2006.189.08:10:48.66#ibcon#about to read 6, iclass 32, count 0 2006.189.08:10:48.66#ibcon#read 6, iclass 32, count 0 2006.189.08:10:48.66#ibcon#end of sib2, iclass 32, count 0 2006.189.08:10:48.66#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:10:48.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:10:48.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:10:48.66#ibcon#*before write, iclass 32, count 0 2006.189.08:10:48.66#ibcon#enter sib2, iclass 32, count 0 2006.189.08:10:48.66#ibcon#flushed, iclass 32, count 0 2006.189.08:10:48.66#ibcon#about to write, iclass 32, count 0 2006.189.08:10:48.66#ibcon#wrote, iclass 32, count 0 2006.189.08:10:48.66#ibcon#about to read 3, iclass 32, count 0 2006.189.08:10:48.70#ibcon#read 3, iclass 32, count 0 2006.189.08:10:48.70#ibcon#about to read 4, iclass 32, count 0 2006.189.08:10:48.70#ibcon#read 4, iclass 32, count 0 2006.189.08:10:48.70#ibcon#about to read 5, iclass 32, count 0 2006.189.08:10:48.70#ibcon#read 5, iclass 32, count 0 2006.189.08:10:48.70#ibcon#about to read 6, iclass 32, count 0 2006.189.08:10:48.70#ibcon#read 6, iclass 32, count 0 2006.189.08:10:48.70#ibcon#end of sib2, iclass 32, count 0 2006.189.08:10:48.70#ibcon#*after write, iclass 32, count 0 2006.189.08:10:48.70#ibcon#*before return 0, iclass 32, count 0 2006.189.08:10:48.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:48.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:48.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:10:48.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:10:48.70$vc4f8/va=3,6 2006.189.08:10:48.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.08:10:48.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.08:10:48.70#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:48.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:48.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:48.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:48.76#ibcon#enter wrdev, iclass 34, count 2 2006.189.08:10:48.76#ibcon#first serial, iclass 34, count 2 2006.189.08:10:48.76#ibcon#enter sib2, iclass 34, count 2 2006.189.08:10:48.76#ibcon#flushed, iclass 34, count 2 2006.189.08:10:48.76#ibcon#about to write, iclass 34, count 2 2006.189.08:10:48.76#ibcon#wrote, iclass 34, count 2 2006.189.08:10:48.76#ibcon#about to read 3, iclass 34, count 2 2006.189.08:10:48.78#ibcon#read 3, iclass 34, count 2 2006.189.08:10:48.78#ibcon#about to read 4, iclass 34, count 2 2006.189.08:10:48.78#ibcon#read 4, iclass 34, count 2 2006.189.08:10:48.78#ibcon#about to read 5, iclass 34, count 2 2006.189.08:10:48.78#ibcon#read 5, iclass 34, count 2 2006.189.08:10:48.78#ibcon#about to read 6, iclass 34, count 2 2006.189.08:10:48.78#ibcon#read 6, iclass 34, count 2 2006.189.08:10:48.78#ibcon#end of sib2, iclass 34, count 2 2006.189.08:10:48.78#ibcon#*mode == 0, iclass 34, count 2 2006.189.08:10:48.78#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.08:10:48.78#ibcon#[25=AT03-06\r\n] 2006.189.08:10:48.78#ibcon#*before write, iclass 34, count 2 2006.189.08:10:48.78#ibcon#enter sib2, iclass 34, count 2 2006.189.08:10:48.78#ibcon#flushed, iclass 34, count 2 2006.189.08:10:48.78#ibcon#about to write, iclass 34, count 2 2006.189.08:10:48.78#ibcon#wrote, iclass 34, count 2 2006.189.08:10:48.78#ibcon#about to read 3, iclass 34, count 2 2006.189.08:10:48.81#ibcon#read 3, iclass 34, count 2 2006.189.08:10:48.81#ibcon#about to read 4, iclass 34, count 2 2006.189.08:10:48.81#ibcon#read 4, iclass 34, count 2 2006.189.08:10:48.81#ibcon#about to read 5, iclass 34, count 2 2006.189.08:10:48.81#ibcon#read 5, iclass 34, count 2 2006.189.08:10:48.81#ibcon#about to read 6, iclass 34, count 2 2006.189.08:10:48.81#ibcon#read 6, iclass 34, count 2 2006.189.08:10:48.81#ibcon#end of sib2, iclass 34, count 2 2006.189.08:10:48.81#ibcon#*after write, iclass 34, count 2 2006.189.08:10:48.81#ibcon#*before return 0, iclass 34, count 2 2006.189.08:10:48.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:48.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:48.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.08:10:48.81#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:48.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:48.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:48.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:48.93#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:10:48.93#ibcon#first serial, iclass 34, count 0 2006.189.08:10:48.93#ibcon#enter sib2, iclass 34, count 0 2006.189.08:10:48.93#ibcon#flushed, iclass 34, count 0 2006.189.08:10:48.93#ibcon#about to write, iclass 34, count 0 2006.189.08:10:48.93#ibcon#wrote, iclass 34, count 0 2006.189.08:10:48.93#ibcon#about to read 3, iclass 34, count 0 2006.189.08:10:48.95#ibcon#read 3, iclass 34, count 0 2006.189.08:10:48.95#ibcon#about to read 4, iclass 34, count 0 2006.189.08:10:48.95#ibcon#read 4, iclass 34, count 0 2006.189.08:10:48.95#ibcon#about to read 5, iclass 34, count 0 2006.189.08:10:48.95#ibcon#read 5, iclass 34, count 0 2006.189.08:10:48.95#ibcon#about to read 6, iclass 34, count 0 2006.189.08:10:48.95#ibcon#read 6, iclass 34, count 0 2006.189.08:10:48.95#ibcon#end of sib2, iclass 34, count 0 2006.189.08:10:48.95#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:10:48.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:10:48.95#ibcon#[25=USB\r\n] 2006.189.08:10:48.95#ibcon#*before write, iclass 34, count 0 2006.189.08:10:48.95#ibcon#enter sib2, iclass 34, count 0 2006.189.08:10:48.95#ibcon#flushed, iclass 34, count 0 2006.189.08:10:48.95#ibcon#about to write, iclass 34, count 0 2006.189.08:10:48.95#ibcon#wrote, iclass 34, count 0 2006.189.08:10:48.95#ibcon#about to read 3, iclass 34, count 0 2006.189.08:10:48.98#ibcon#read 3, iclass 34, count 0 2006.189.08:10:48.98#ibcon#about to read 4, iclass 34, count 0 2006.189.08:10:48.98#ibcon#read 4, iclass 34, count 0 2006.189.08:10:48.98#ibcon#about to read 5, iclass 34, count 0 2006.189.08:10:48.98#ibcon#read 5, iclass 34, count 0 2006.189.08:10:48.98#ibcon#about to read 6, iclass 34, count 0 2006.189.08:10:48.98#ibcon#read 6, iclass 34, count 0 2006.189.08:10:48.98#ibcon#end of sib2, iclass 34, count 0 2006.189.08:10:48.98#ibcon#*after write, iclass 34, count 0 2006.189.08:10:48.98#ibcon#*before return 0, iclass 34, count 0 2006.189.08:10:48.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:48.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:48.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:10:48.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:10:48.98$vc4f8/valo=4,832.99 2006.189.08:10:48.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.08:10:48.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.08:10:48.98#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:48.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:48.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:48.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:48.98#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:10:48.98#ibcon#first serial, iclass 36, count 0 2006.189.08:10:48.98#ibcon#enter sib2, iclass 36, count 0 2006.189.08:10:48.99#ibcon#flushed, iclass 36, count 0 2006.189.08:10:48.99#ibcon#about to write, iclass 36, count 0 2006.189.08:10:48.99#ibcon#wrote, iclass 36, count 0 2006.189.08:10:48.99#ibcon#about to read 3, iclass 36, count 0 2006.189.08:10:49.00#ibcon#read 3, iclass 36, count 0 2006.189.08:10:49.00#ibcon#about to read 4, iclass 36, count 0 2006.189.08:10:49.00#ibcon#read 4, iclass 36, count 0 2006.189.08:10:49.00#ibcon#about to read 5, iclass 36, count 0 2006.189.08:10:49.00#ibcon#read 5, iclass 36, count 0 2006.189.08:10:49.00#ibcon#about to read 6, iclass 36, count 0 2006.189.08:10:49.00#ibcon#read 6, iclass 36, count 0 2006.189.08:10:49.00#ibcon#end of sib2, iclass 36, count 0 2006.189.08:10:49.00#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:10:49.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:10:49.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:10:49.00#ibcon#*before write, iclass 36, count 0 2006.189.08:10:49.00#ibcon#enter sib2, iclass 36, count 0 2006.189.08:10:49.00#ibcon#flushed, iclass 36, count 0 2006.189.08:10:49.00#ibcon#about to write, iclass 36, count 0 2006.189.08:10:49.00#ibcon#wrote, iclass 36, count 0 2006.189.08:10:49.00#ibcon#about to read 3, iclass 36, count 0 2006.189.08:10:49.04#ibcon#read 3, iclass 36, count 0 2006.189.08:10:49.04#ibcon#about to read 4, iclass 36, count 0 2006.189.08:10:49.04#ibcon#read 4, iclass 36, count 0 2006.189.08:10:49.04#ibcon#about to read 5, iclass 36, count 0 2006.189.08:10:49.04#ibcon#read 5, iclass 36, count 0 2006.189.08:10:49.04#ibcon#about to read 6, iclass 36, count 0 2006.189.08:10:49.04#ibcon#read 6, iclass 36, count 0 2006.189.08:10:49.04#ibcon#end of sib2, iclass 36, count 0 2006.189.08:10:49.04#ibcon#*after write, iclass 36, count 0 2006.189.08:10:49.04#ibcon#*before return 0, iclass 36, count 0 2006.189.08:10:49.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:49.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:49.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:10:49.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:10:49.04$vc4f8/va=4,7 2006.189.08:10:49.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.08:10:49.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.08:10:49.04#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:49.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:49.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:49.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:49.10#ibcon#enter wrdev, iclass 38, count 2 2006.189.08:10:49.10#ibcon#first serial, iclass 38, count 2 2006.189.08:10:49.10#ibcon#enter sib2, iclass 38, count 2 2006.189.08:10:49.10#ibcon#flushed, iclass 38, count 2 2006.189.08:10:49.10#ibcon#about to write, iclass 38, count 2 2006.189.08:10:49.10#ibcon#wrote, iclass 38, count 2 2006.189.08:10:49.10#ibcon#about to read 3, iclass 38, count 2 2006.189.08:10:49.12#ibcon#read 3, iclass 38, count 2 2006.189.08:10:49.12#ibcon#about to read 4, iclass 38, count 2 2006.189.08:10:49.12#ibcon#read 4, iclass 38, count 2 2006.189.08:10:49.12#ibcon#about to read 5, iclass 38, count 2 2006.189.08:10:49.12#ibcon#read 5, iclass 38, count 2 2006.189.08:10:49.12#ibcon#about to read 6, iclass 38, count 2 2006.189.08:10:49.12#ibcon#read 6, iclass 38, count 2 2006.189.08:10:49.12#ibcon#end of sib2, iclass 38, count 2 2006.189.08:10:49.12#ibcon#*mode == 0, iclass 38, count 2 2006.189.08:10:49.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.08:10:49.12#ibcon#[25=AT04-07\r\n] 2006.189.08:10:49.12#ibcon#*before write, iclass 38, count 2 2006.189.08:10:49.12#ibcon#enter sib2, iclass 38, count 2 2006.189.08:10:49.12#ibcon#flushed, iclass 38, count 2 2006.189.08:10:49.12#ibcon#about to write, iclass 38, count 2 2006.189.08:10:49.12#ibcon#wrote, iclass 38, count 2 2006.189.08:10:49.12#ibcon#about to read 3, iclass 38, count 2 2006.189.08:10:49.15#ibcon#read 3, iclass 38, count 2 2006.189.08:10:49.15#ibcon#about to read 4, iclass 38, count 2 2006.189.08:10:49.15#ibcon#read 4, iclass 38, count 2 2006.189.08:10:49.15#ibcon#about to read 5, iclass 38, count 2 2006.189.08:10:49.15#ibcon#read 5, iclass 38, count 2 2006.189.08:10:49.15#ibcon#about to read 6, iclass 38, count 2 2006.189.08:10:49.15#ibcon#read 6, iclass 38, count 2 2006.189.08:10:49.15#ibcon#end of sib2, iclass 38, count 2 2006.189.08:10:49.15#ibcon#*after write, iclass 38, count 2 2006.189.08:10:49.15#ibcon#*before return 0, iclass 38, count 2 2006.189.08:10:49.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:49.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:49.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.08:10:49.15#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:49.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:49.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:49.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:49.27#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:10:49.27#ibcon#first serial, iclass 38, count 0 2006.189.08:10:49.27#ibcon#enter sib2, iclass 38, count 0 2006.189.08:10:49.27#ibcon#flushed, iclass 38, count 0 2006.189.08:10:49.27#ibcon#about to write, iclass 38, count 0 2006.189.08:10:49.27#ibcon#wrote, iclass 38, count 0 2006.189.08:10:49.27#ibcon#about to read 3, iclass 38, count 0 2006.189.08:10:49.29#ibcon#read 3, iclass 38, count 0 2006.189.08:10:49.29#ibcon#about to read 4, iclass 38, count 0 2006.189.08:10:49.29#ibcon#read 4, iclass 38, count 0 2006.189.08:10:49.29#ibcon#about to read 5, iclass 38, count 0 2006.189.08:10:49.29#ibcon#read 5, iclass 38, count 0 2006.189.08:10:49.29#ibcon#about to read 6, iclass 38, count 0 2006.189.08:10:49.29#ibcon#read 6, iclass 38, count 0 2006.189.08:10:49.29#ibcon#end of sib2, iclass 38, count 0 2006.189.08:10:49.29#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:10:49.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:10:49.29#ibcon#[25=USB\r\n] 2006.189.08:10:49.29#ibcon#*before write, iclass 38, count 0 2006.189.08:10:49.29#ibcon#enter sib2, iclass 38, count 0 2006.189.08:10:49.29#ibcon#flushed, iclass 38, count 0 2006.189.08:10:49.29#ibcon#about to write, iclass 38, count 0 2006.189.08:10:49.29#ibcon#wrote, iclass 38, count 0 2006.189.08:10:49.29#ibcon#about to read 3, iclass 38, count 0 2006.189.08:10:49.32#ibcon#read 3, iclass 38, count 0 2006.189.08:10:49.32#ibcon#about to read 4, iclass 38, count 0 2006.189.08:10:49.32#ibcon#read 4, iclass 38, count 0 2006.189.08:10:49.32#ibcon#about to read 5, iclass 38, count 0 2006.189.08:10:49.32#ibcon#read 5, iclass 38, count 0 2006.189.08:10:49.32#ibcon#about to read 6, iclass 38, count 0 2006.189.08:10:49.32#ibcon#read 6, iclass 38, count 0 2006.189.08:10:49.32#ibcon#end of sib2, iclass 38, count 0 2006.189.08:10:49.32#ibcon#*after write, iclass 38, count 0 2006.189.08:10:49.32#ibcon#*before return 0, iclass 38, count 0 2006.189.08:10:49.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:49.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:49.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:10:49.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:10:49.32$vc4f8/valo=5,652.99 2006.189.08:10:49.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.08:10:49.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.08:10:49.32#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:49.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:49.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:49.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:49.32#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:10:49.32#ibcon#first serial, iclass 40, count 0 2006.189.08:10:49.32#ibcon#enter sib2, iclass 40, count 0 2006.189.08:10:49.33#ibcon#flushed, iclass 40, count 0 2006.189.08:10:49.33#ibcon#about to write, iclass 40, count 0 2006.189.08:10:49.33#ibcon#wrote, iclass 40, count 0 2006.189.08:10:49.33#ibcon#about to read 3, iclass 40, count 0 2006.189.08:10:49.34#ibcon#read 3, iclass 40, count 0 2006.189.08:10:49.34#ibcon#about to read 4, iclass 40, count 0 2006.189.08:10:49.34#ibcon#read 4, iclass 40, count 0 2006.189.08:10:49.34#ibcon#about to read 5, iclass 40, count 0 2006.189.08:10:49.34#ibcon#read 5, iclass 40, count 0 2006.189.08:10:49.34#ibcon#about to read 6, iclass 40, count 0 2006.189.08:10:49.34#ibcon#read 6, iclass 40, count 0 2006.189.08:10:49.34#ibcon#end of sib2, iclass 40, count 0 2006.189.08:10:49.34#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:10:49.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:10:49.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:10:49.34#ibcon#*before write, iclass 40, count 0 2006.189.08:10:49.34#ibcon#enter sib2, iclass 40, count 0 2006.189.08:10:49.34#ibcon#flushed, iclass 40, count 0 2006.189.08:10:49.34#ibcon#about to write, iclass 40, count 0 2006.189.08:10:49.34#ibcon#wrote, iclass 40, count 0 2006.189.08:10:49.34#ibcon#about to read 3, iclass 40, count 0 2006.189.08:10:49.38#ibcon#read 3, iclass 40, count 0 2006.189.08:10:49.38#ibcon#about to read 4, iclass 40, count 0 2006.189.08:10:49.38#ibcon#read 4, iclass 40, count 0 2006.189.08:10:49.38#ibcon#about to read 5, iclass 40, count 0 2006.189.08:10:49.38#ibcon#read 5, iclass 40, count 0 2006.189.08:10:49.38#ibcon#about to read 6, iclass 40, count 0 2006.189.08:10:49.38#ibcon#read 6, iclass 40, count 0 2006.189.08:10:49.38#ibcon#end of sib2, iclass 40, count 0 2006.189.08:10:49.38#ibcon#*after write, iclass 40, count 0 2006.189.08:10:49.38#ibcon#*before return 0, iclass 40, count 0 2006.189.08:10:49.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:49.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:49.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:10:49.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:10:49.38$vc4f8/va=5,7 2006.189.08:10:49.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.08:10:49.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.08:10:49.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:49.39#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:49.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:49.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:49.43#ibcon#enter wrdev, iclass 4, count 2 2006.189.08:10:49.43#ibcon#first serial, iclass 4, count 2 2006.189.08:10:49.43#ibcon#enter sib2, iclass 4, count 2 2006.189.08:10:49.43#ibcon#flushed, iclass 4, count 2 2006.189.08:10:49.43#ibcon#about to write, iclass 4, count 2 2006.189.08:10:49.43#ibcon#wrote, iclass 4, count 2 2006.189.08:10:49.43#ibcon#about to read 3, iclass 4, count 2 2006.189.08:10:49.45#ibcon#read 3, iclass 4, count 2 2006.189.08:10:49.45#ibcon#about to read 4, iclass 4, count 2 2006.189.08:10:49.45#ibcon#read 4, iclass 4, count 2 2006.189.08:10:49.45#ibcon#about to read 5, iclass 4, count 2 2006.189.08:10:49.45#ibcon#read 5, iclass 4, count 2 2006.189.08:10:49.45#ibcon#about to read 6, iclass 4, count 2 2006.189.08:10:49.45#ibcon#read 6, iclass 4, count 2 2006.189.08:10:49.45#ibcon#end of sib2, iclass 4, count 2 2006.189.08:10:49.45#ibcon#*mode == 0, iclass 4, count 2 2006.189.08:10:49.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.08:10:49.45#ibcon#[25=AT05-07\r\n] 2006.189.08:10:49.45#ibcon#*before write, iclass 4, count 2 2006.189.08:10:49.45#ibcon#enter sib2, iclass 4, count 2 2006.189.08:10:49.45#ibcon#flushed, iclass 4, count 2 2006.189.08:10:49.45#ibcon#about to write, iclass 4, count 2 2006.189.08:10:49.45#ibcon#wrote, iclass 4, count 2 2006.189.08:10:49.45#ibcon#about to read 3, iclass 4, count 2 2006.189.08:10:49.48#ibcon#read 3, iclass 4, count 2 2006.189.08:10:49.48#ibcon#about to read 4, iclass 4, count 2 2006.189.08:10:49.48#ibcon#read 4, iclass 4, count 2 2006.189.08:10:49.48#ibcon#about to read 5, iclass 4, count 2 2006.189.08:10:49.48#ibcon#read 5, iclass 4, count 2 2006.189.08:10:49.48#ibcon#about to read 6, iclass 4, count 2 2006.189.08:10:49.48#ibcon#read 6, iclass 4, count 2 2006.189.08:10:49.48#ibcon#end of sib2, iclass 4, count 2 2006.189.08:10:49.48#ibcon#*after write, iclass 4, count 2 2006.189.08:10:49.48#ibcon#*before return 0, iclass 4, count 2 2006.189.08:10:49.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:49.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:49.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.08:10:49.48#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:49.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:49.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:49.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:49.60#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:10:49.60#ibcon#first serial, iclass 4, count 0 2006.189.08:10:49.60#ibcon#enter sib2, iclass 4, count 0 2006.189.08:10:49.60#ibcon#flushed, iclass 4, count 0 2006.189.08:10:49.60#ibcon#about to write, iclass 4, count 0 2006.189.08:10:49.60#ibcon#wrote, iclass 4, count 0 2006.189.08:10:49.60#ibcon#about to read 3, iclass 4, count 0 2006.189.08:10:49.62#ibcon#read 3, iclass 4, count 0 2006.189.08:10:49.62#ibcon#about to read 4, iclass 4, count 0 2006.189.08:10:49.62#ibcon#read 4, iclass 4, count 0 2006.189.08:10:49.62#ibcon#about to read 5, iclass 4, count 0 2006.189.08:10:49.62#ibcon#read 5, iclass 4, count 0 2006.189.08:10:49.62#ibcon#about to read 6, iclass 4, count 0 2006.189.08:10:49.62#ibcon#read 6, iclass 4, count 0 2006.189.08:10:49.62#ibcon#end of sib2, iclass 4, count 0 2006.189.08:10:49.62#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:10:49.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:10:49.62#ibcon#[25=USB\r\n] 2006.189.08:10:49.62#ibcon#*before write, iclass 4, count 0 2006.189.08:10:49.62#ibcon#enter sib2, iclass 4, count 0 2006.189.08:10:49.62#ibcon#flushed, iclass 4, count 0 2006.189.08:10:49.62#ibcon#about to write, iclass 4, count 0 2006.189.08:10:49.62#ibcon#wrote, iclass 4, count 0 2006.189.08:10:49.62#ibcon#about to read 3, iclass 4, count 0 2006.189.08:10:49.65#ibcon#read 3, iclass 4, count 0 2006.189.08:10:49.65#ibcon#about to read 4, iclass 4, count 0 2006.189.08:10:49.65#ibcon#read 4, iclass 4, count 0 2006.189.08:10:49.65#ibcon#about to read 5, iclass 4, count 0 2006.189.08:10:49.65#ibcon#read 5, iclass 4, count 0 2006.189.08:10:49.65#ibcon#about to read 6, iclass 4, count 0 2006.189.08:10:49.65#ibcon#read 6, iclass 4, count 0 2006.189.08:10:49.65#ibcon#end of sib2, iclass 4, count 0 2006.189.08:10:49.65#ibcon#*after write, iclass 4, count 0 2006.189.08:10:49.65#ibcon#*before return 0, iclass 4, count 0 2006.189.08:10:49.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:49.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:49.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:10:49.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:10:49.65$vc4f8/valo=6,772.99 2006.189.08:10:49.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.08:10:49.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.08:10:49.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:49.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:49.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:49.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:49.65#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:10:49.65#ibcon#first serial, iclass 6, count 0 2006.189.08:10:49.65#ibcon#enter sib2, iclass 6, count 0 2006.189.08:10:49.65#ibcon#flushed, iclass 6, count 0 2006.189.08:10:49.66#ibcon#about to write, iclass 6, count 0 2006.189.08:10:49.66#ibcon#wrote, iclass 6, count 0 2006.189.08:10:49.66#ibcon#about to read 3, iclass 6, count 0 2006.189.08:10:49.67#ibcon#read 3, iclass 6, count 0 2006.189.08:10:49.67#ibcon#about to read 4, iclass 6, count 0 2006.189.08:10:49.67#ibcon#read 4, iclass 6, count 0 2006.189.08:10:49.67#ibcon#about to read 5, iclass 6, count 0 2006.189.08:10:49.67#ibcon#read 5, iclass 6, count 0 2006.189.08:10:49.67#ibcon#about to read 6, iclass 6, count 0 2006.189.08:10:49.67#ibcon#read 6, iclass 6, count 0 2006.189.08:10:49.67#ibcon#end of sib2, iclass 6, count 0 2006.189.08:10:49.67#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:10:49.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:10:49.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:10:49.67#ibcon#*before write, iclass 6, count 0 2006.189.08:10:49.67#ibcon#enter sib2, iclass 6, count 0 2006.189.08:10:49.67#ibcon#flushed, iclass 6, count 0 2006.189.08:10:49.67#ibcon#about to write, iclass 6, count 0 2006.189.08:10:49.67#ibcon#wrote, iclass 6, count 0 2006.189.08:10:49.67#ibcon#about to read 3, iclass 6, count 0 2006.189.08:10:49.71#ibcon#read 3, iclass 6, count 0 2006.189.08:10:49.71#ibcon#about to read 4, iclass 6, count 0 2006.189.08:10:49.71#ibcon#read 4, iclass 6, count 0 2006.189.08:10:49.71#ibcon#about to read 5, iclass 6, count 0 2006.189.08:10:49.71#ibcon#read 5, iclass 6, count 0 2006.189.08:10:49.71#ibcon#about to read 6, iclass 6, count 0 2006.189.08:10:49.71#ibcon#read 6, iclass 6, count 0 2006.189.08:10:49.71#ibcon#end of sib2, iclass 6, count 0 2006.189.08:10:49.71#ibcon#*after write, iclass 6, count 0 2006.189.08:10:49.71#ibcon#*before return 0, iclass 6, count 0 2006.189.08:10:49.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:49.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:49.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:10:49.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:10:49.71$vc4f8/va=6,6 2006.189.08:10:49.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.08:10:49.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.08:10:49.71#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:49.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:49.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:49.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:49.77#ibcon#enter wrdev, iclass 10, count 2 2006.189.08:10:49.77#ibcon#first serial, iclass 10, count 2 2006.189.08:10:49.77#ibcon#enter sib2, iclass 10, count 2 2006.189.08:10:49.77#ibcon#flushed, iclass 10, count 2 2006.189.08:10:49.77#ibcon#about to write, iclass 10, count 2 2006.189.08:10:49.77#ibcon#wrote, iclass 10, count 2 2006.189.08:10:49.77#ibcon#about to read 3, iclass 10, count 2 2006.189.08:10:49.79#ibcon#read 3, iclass 10, count 2 2006.189.08:10:49.79#ibcon#about to read 4, iclass 10, count 2 2006.189.08:10:49.79#ibcon#read 4, iclass 10, count 2 2006.189.08:10:49.79#ibcon#about to read 5, iclass 10, count 2 2006.189.08:10:49.79#ibcon#read 5, iclass 10, count 2 2006.189.08:10:49.79#ibcon#about to read 6, iclass 10, count 2 2006.189.08:10:49.79#ibcon#read 6, iclass 10, count 2 2006.189.08:10:49.79#ibcon#end of sib2, iclass 10, count 2 2006.189.08:10:49.79#ibcon#*mode == 0, iclass 10, count 2 2006.189.08:10:49.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.08:10:49.79#ibcon#[25=AT06-06\r\n] 2006.189.08:10:49.79#ibcon#*before write, iclass 10, count 2 2006.189.08:10:49.79#ibcon#enter sib2, iclass 10, count 2 2006.189.08:10:49.79#ibcon#flushed, iclass 10, count 2 2006.189.08:10:49.79#ibcon#about to write, iclass 10, count 2 2006.189.08:10:49.79#ibcon#wrote, iclass 10, count 2 2006.189.08:10:49.79#ibcon#about to read 3, iclass 10, count 2 2006.189.08:10:49.82#ibcon#read 3, iclass 10, count 2 2006.189.08:10:49.82#ibcon#about to read 4, iclass 10, count 2 2006.189.08:10:49.82#ibcon#read 4, iclass 10, count 2 2006.189.08:10:49.82#ibcon#about to read 5, iclass 10, count 2 2006.189.08:10:49.82#ibcon#read 5, iclass 10, count 2 2006.189.08:10:49.82#ibcon#about to read 6, iclass 10, count 2 2006.189.08:10:49.82#ibcon#read 6, iclass 10, count 2 2006.189.08:10:49.82#ibcon#end of sib2, iclass 10, count 2 2006.189.08:10:49.82#ibcon#*after write, iclass 10, count 2 2006.189.08:10:49.82#ibcon#*before return 0, iclass 10, count 2 2006.189.08:10:49.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:49.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:49.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.08:10:49.82#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:49.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:49.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:49.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:49.94#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:10:49.94#ibcon#first serial, iclass 10, count 0 2006.189.08:10:49.94#ibcon#enter sib2, iclass 10, count 0 2006.189.08:10:49.94#ibcon#flushed, iclass 10, count 0 2006.189.08:10:49.94#ibcon#about to write, iclass 10, count 0 2006.189.08:10:49.94#ibcon#wrote, iclass 10, count 0 2006.189.08:10:49.94#ibcon#about to read 3, iclass 10, count 0 2006.189.08:10:49.96#ibcon#read 3, iclass 10, count 0 2006.189.08:10:49.96#ibcon#about to read 4, iclass 10, count 0 2006.189.08:10:49.96#ibcon#read 4, iclass 10, count 0 2006.189.08:10:49.96#ibcon#about to read 5, iclass 10, count 0 2006.189.08:10:49.96#ibcon#read 5, iclass 10, count 0 2006.189.08:10:49.96#ibcon#about to read 6, iclass 10, count 0 2006.189.08:10:49.96#ibcon#read 6, iclass 10, count 0 2006.189.08:10:49.96#ibcon#end of sib2, iclass 10, count 0 2006.189.08:10:49.96#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:10:49.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:10:49.96#ibcon#[25=USB\r\n] 2006.189.08:10:49.96#ibcon#*before write, iclass 10, count 0 2006.189.08:10:49.96#ibcon#enter sib2, iclass 10, count 0 2006.189.08:10:49.96#ibcon#flushed, iclass 10, count 0 2006.189.08:10:49.96#ibcon#about to write, iclass 10, count 0 2006.189.08:10:49.96#ibcon#wrote, iclass 10, count 0 2006.189.08:10:49.96#ibcon#about to read 3, iclass 10, count 0 2006.189.08:10:49.99#abcon#<5=/04 3.6 6.7 25.51 911009.3\r\n> 2006.189.08:10:49.99#ibcon#read 3, iclass 10, count 0 2006.189.08:10:49.99#ibcon#about to read 4, iclass 10, count 0 2006.189.08:10:49.99#ibcon#read 4, iclass 10, count 0 2006.189.08:10:49.99#ibcon#about to read 5, iclass 10, count 0 2006.189.08:10:49.99#ibcon#read 5, iclass 10, count 0 2006.189.08:10:49.99#ibcon#about to read 6, iclass 10, count 0 2006.189.08:10:49.99#ibcon#read 6, iclass 10, count 0 2006.189.08:10:49.99#ibcon#end of sib2, iclass 10, count 0 2006.189.08:10:49.99#ibcon#*after write, iclass 10, count 0 2006.189.08:10:49.99#ibcon#*before return 0, iclass 10, count 0 2006.189.08:10:50.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:50.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:50.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:10:50.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:10:50.00$vc4f8/valo=7,832.99 2006.189.08:10:50.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.08:10:50.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.08:10:50.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:50.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:10:50.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:10:50.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:10:50.00#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:10:50.00#ibcon#first serial, iclass 15, count 0 2006.189.08:10:50.00#ibcon#enter sib2, iclass 15, count 0 2006.189.08:10:50.00#ibcon#flushed, iclass 15, count 0 2006.189.08:10:50.00#ibcon#about to write, iclass 15, count 0 2006.189.08:10:50.00#ibcon#wrote, iclass 15, count 0 2006.189.08:10:50.00#ibcon#about to read 3, iclass 15, count 0 2006.189.08:10:50.01#abcon#{5=INTERFACE CLEAR} 2006.189.08:10:50.01#ibcon#read 3, iclass 15, count 0 2006.189.08:10:50.01#ibcon#about to read 4, iclass 15, count 0 2006.189.08:10:50.01#ibcon#read 4, iclass 15, count 0 2006.189.08:10:50.01#ibcon#about to read 5, iclass 15, count 0 2006.189.08:10:50.01#ibcon#read 5, iclass 15, count 0 2006.189.08:10:50.01#ibcon#about to read 6, iclass 15, count 0 2006.189.08:10:50.01#ibcon#read 6, iclass 15, count 0 2006.189.08:10:50.01#ibcon#end of sib2, iclass 15, count 0 2006.189.08:10:50.01#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:10:50.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:10:50.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:10:50.01#ibcon#*before write, iclass 15, count 0 2006.189.08:10:50.01#ibcon#enter sib2, iclass 15, count 0 2006.189.08:10:50.01#ibcon#flushed, iclass 15, count 0 2006.189.08:10:50.01#ibcon#about to write, iclass 15, count 0 2006.189.08:10:50.01#ibcon#wrote, iclass 15, count 0 2006.189.08:10:50.01#ibcon#about to read 3, iclass 15, count 0 2006.189.08:10:50.05#ibcon#read 3, iclass 15, count 0 2006.189.08:10:50.05#ibcon#about to read 4, iclass 15, count 0 2006.189.08:10:50.05#ibcon#read 4, iclass 15, count 0 2006.189.08:10:50.05#ibcon#about to read 5, iclass 15, count 0 2006.189.08:10:50.05#ibcon#read 5, iclass 15, count 0 2006.189.08:10:50.05#ibcon#about to read 6, iclass 15, count 0 2006.189.08:10:50.05#ibcon#read 6, iclass 15, count 0 2006.189.08:10:50.05#ibcon#end of sib2, iclass 15, count 0 2006.189.08:10:50.05#ibcon#*after write, iclass 15, count 0 2006.189.08:10:50.05#ibcon#*before return 0, iclass 15, count 0 2006.189.08:10:50.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:10:50.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:10:50.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:10:50.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:10:50.05$vc4f8/va=7,6 2006.189.08:10:50.05#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.08:10:50.05#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.08:10:50.05#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:50.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:10:50.07#abcon#[5=S1D000X0/0*\r\n] 2006.189.08:10:50.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:10:50.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:10:50.12#ibcon#enter wrdev, iclass 17, count 2 2006.189.08:10:50.12#ibcon#first serial, iclass 17, count 2 2006.189.08:10:50.12#ibcon#enter sib2, iclass 17, count 2 2006.189.08:10:50.12#ibcon#flushed, iclass 17, count 2 2006.189.08:10:50.12#ibcon#about to write, iclass 17, count 2 2006.189.08:10:50.12#ibcon#wrote, iclass 17, count 2 2006.189.08:10:50.12#ibcon#about to read 3, iclass 17, count 2 2006.189.08:10:50.14#ibcon#read 3, iclass 17, count 2 2006.189.08:10:50.14#ibcon#about to read 4, iclass 17, count 2 2006.189.08:10:50.14#ibcon#read 4, iclass 17, count 2 2006.189.08:10:50.14#ibcon#about to read 5, iclass 17, count 2 2006.189.08:10:50.14#ibcon#read 5, iclass 17, count 2 2006.189.08:10:50.14#ibcon#about to read 6, iclass 17, count 2 2006.189.08:10:50.14#ibcon#read 6, iclass 17, count 2 2006.189.08:10:50.14#ibcon#end of sib2, iclass 17, count 2 2006.189.08:10:50.14#ibcon#*mode == 0, iclass 17, count 2 2006.189.08:10:50.14#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.08:10:50.14#ibcon#[25=AT07-06\r\n] 2006.189.08:10:50.14#ibcon#*before write, iclass 17, count 2 2006.189.08:10:50.14#ibcon#enter sib2, iclass 17, count 2 2006.189.08:10:50.14#ibcon#flushed, iclass 17, count 2 2006.189.08:10:50.14#ibcon#about to write, iclass 17, count 2 2006.189.08:10:50.14#ibcon#wrote, iclass 17, count 2 2006.189.08:10:50.14#ibcon#about to read 3, iclass 17, count 2 2006.189.08:10:50.17#ibcon#read 3, iclass 17, count 2 2006.189.08:10:50.17#ibcon#about to read 4, iclass 17, count 2 2006.189.08:10:50.17#ibcon#read 4, iclass 17, count 2 2006.189.08:10:50.17#ibcon#about to read 5, iclass 17, count 2 2006.189.08:10:50.17#ibcon#read 5, iclass 17, count 2 2006.189.08:10:50.17#ibcon#about to read 6, iclass 17, count 2 2006.189.08:10:50.17#ibcon#read 6, iclass 17, count 2 2006.189.08:10:50.17#ibcon#end of sib2, iclass 17, count 2 2006.189.08:10:50.17#ibcon#*after write, iclass 17, count 2 2006.189.08:10:50.17#ibcon#*before return 0, iclass 17, count 2 2006.189.08:10:50.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:10:50.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:10:50.17#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.08:10:50.17#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:50.17#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:10:50.29#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:10:50.29#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:10:50.29#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:10:50.29#ibcon#first serial, iclass 17, count 0 2006.189.08:10:50.29#ibcon#enter sib2, iclass 17, count 0 2006.189.08:10:50.29#ibcon#flushed, iclass 17, count 0 2006.189.08:10:50.29#ibcon#about to write, iclass 17, count 0 2006.189.08:10:50.29#ibcon#wrote, iclass 17, count 0 2006.189.08:10:50.29#ibcon#about to read 3, iclass 17, count 0 2006.189.08:10:50.31#ibcon#read 3, iclass 17, count 0 2006.189.08:10:50.31#ibcon#about to read 4, iclass 17, count 0 2006.189.08:10:50.31#ibcon#read 4, iclass 17, count 0 2006.189.08:10:50.31#ibcon#about to read 5, iclass 17, count 0 2006.189.08:10:50.31#ibcon#read 5, iclass 17, count 0 2006.189.08:10:50.31#ibcon#about to read 6, iclass 17, count 0 2006.189.08:10:50.31#ibcon#read 6, iclass 17, count 0 2006.189.08:10:50.31#ibcon#end of sib2, iclass 17, count 0 2006.189.08:10:50.31#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:10:50.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:10:50.31#ibcon#[25=USB\r\n] 2006.189.08:10:50.31#ibcon#*before write, iclass 17, count 0 2006.189.08:10:50.31#ibcon#enter sib2, iclass 17, count 0 2006.189.08:10:50.31#ibcon#flushed, iclass 17, count 0 2006.189.08:10:50.31#ibcon#about to write, iclass 17, count 0 2006.189.08:10:50.31#ibcon#wrote, iclass 17, count 0 2006.189.08:10:50.31#ibcon#about to read 3, iclass 17, count 0 2006.189.08:10:50.35#ibcon#read 3, iclass 17, count 0 2006.189.08:10:50.35#ibcon#about to read 4, iclass 17, count 0 2006.189.08:10:50.35#ibcon#read 4, iclass 17, count 0 2006.189.08:10:50.35#ibcon#about to read 5, iclass 17, count 0 2006.189.08:10:50.35#ibcon#read 5, iclass 17, count 0 2006.189.08:10:50.35#ibcon#about to read 6, iclass 17, count 0 2006.189.08:10:50.35#ibcon#read 6, iclass 17, count 0 2006.189.08:10:50.35#ibcon#end of sib2, iclass 17, count 0 2006.189.08:10:50.35#ibcon#*after write, iclass 17, count 0 2006.189.08:10:50.35#ibcon#*before return 0, iclass 17, count 0 2006.189.08:10:50.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:10:50.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:10:50.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:10:50.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:10:50.35$vc4f8/valo=8,852.99 2006.189.08:10:50.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.08:10:50.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.08:10:50.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:50.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:10:50.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:10:50.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:10:50.35#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:10:50.35#ibcon#first serial, iclass 20, count 0 2006.189.08:10:50.35#ibcon#enter sib2, iclass 20, count 0 2006.189.08:10:50.35#ibcon#flushed, iclass 20, count 0 2006.189.08:10:50.35#ibcon#about to write, iclass 20, count 0 2006.189.08:10:50.35#ibcon#wrote, iclass 20, count 0 2006.189.08:10:50.35#ibcon#about to read 3, iclass 20, count 0 2006.189.08:10:50.37#ibcon#read 3, iclass 20, count 0 2006.189.08:10:50.37#ibcon#about to read 4, iclass 20, count 0 2006.189.08:10:50.37#ibcon#read 4, iclass 20, count 0 2006.189.08:10:50.37#ibcon#about to read 5, iclass 20, count 0 2006.189.08:10:50.37#ibcon#read 5, iclass 20, count 0 2006.189.08:10:50.37#ibcon#about to read 6, iclass 20, count 0 2006.189.08:10:50.37#ibcon#read 6, iclass 20, count 0 2006.189.08:10:50.37#ibcon#end of sib2, iclass 20, count 0 2006.189.08:10:50.37#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:10:50.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:10:50.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:10:50.37#ibcon#*before write, iclass 20, count 0 2006.189.08:10:50.37#ibcon#enter sib2, iclass 20, count 0 2006.189.08:10:50.37#ibcon#flushed, iclass 20, count 0 2006.189.08:10:50.37#ibcon#about to write, iclass 20, count 0 2006.189.08:10:50.37#ibcon#wrote, iclass 20, count 0 2006.189.08:10:50.37#ibcon#about to read 3, iclass 20, count 0 2006.189.08:10:50.40#ibcon#read 3, iclass 20, count 0 2006.189.08:10:50.40#ibcon#about to read 4, iclass 20, count 0 2006.189.08:10:50.40#ibcon#read 4, iclass 20, count 0 2006.189.08:10:50.40#ibcon#about to read 5, iclass 20, count 0 2006.189.08:10:50.40#ibcon#read 5, iclass 20, count 0 2006.189.08:10:50.40#ibcon#about to read 6, iclass 20, count 0 2006.189.08:10:50.40#ibcon#read 6, iclass 20, count 0 2006.189.08:10:50.40#ibcon#end of sib2, iclass 20, count 0 2006.189.08:10:50.40#ibcon#*after write, iclass 20, count 0 2006.189.08:10:50.40#ibcon#*before return 0, iclass 20, count 0 2006.189.08:10:50.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:10:50.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:10:50.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:10:50.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:10:50.40$vc4f8/va=8,6 2006.189.08:10:50.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.08:10:50.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.08:10:50.40#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:50.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:10:50.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:10:50.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:10:50.47#ibcon#enter wrdev, iclass 22, count 2 2006.189.08:10:50.47#ibcon#first serial, iclass 22, count 2 2006.189.08:10:50.47#ibcon#enter sib2, iclass 22, count 2 2006.189.08:10:50.47#ibcon#flushed, iclass 22, count 2 2006.189.08:10:50.47#ibcon#about to write, iclass 22, count 2 2006.189.08:10:50.47#ibcon#wrote, iclass 22, count 2 2006.189.08:10:50.47#ibcon#about to read 3, iclass 22, count 2 2006.189.08:10:50.49#ibcon#read 3, iclass 22, count 2 2006.189.08:10:50.49#ibcon#about to read 4, iclass 22, count 2 2006.189.08:10:50.49#ibcon#read 4, iclass 22, count 2 2006.189.08:10:50.49#ibcon#about to read 5, iclass 22, count 2 2006.189.08:10:50.49#ibcon#read 5, iclass 22, count 2 2006.189.08:10:50.49#ibcon#about to read 6, iclass 22, count 2 2006.189.08:10:50.49#ibcon#read 6, iclass 22, count 2 2006.189.08:10:50.49#ibcon#end of sib2, iclass 22, count 2 2006.189.08:10:50.49#ibcon#*mode == 0, iclass 22, count 2 2006.189.08:10:50.49#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.08:10:50.49#ibcon#[25=AT08-06\r\n] 2006.189.08:10:50.49#ibcon#*before write, iclass 22, count 2 2006.189.08:10:50.49#ibcon#enter sib2, iclass 22, count 2 2006.189.08:10:50.49#ibcon#flushed, iclass 22, count 2 2006.189.08:10:50.49#ibcon#about to write, iclass 22, count 2 2006.189.08:10:50.49#ibcon#wrote, iclass 22, count 2 2006.189.08:10:50.49#ibcon#about to read 3, iclass 22, count 2 2006.189.08:10:50.52#ibcon#read 3, iclass 22, count 2 2006.189.08:10:50.52#ibcon#about to read 4, iclass 22, count 2 2006.189.08:10:50.52#ibcon#read 4, iclass 22, count 2 2006.189.08:10:50.52#ibcon#about to read 5, iclass 22, count 2 2006.189.08:10:50.52#ibcon#read 5, iclass 22, count 2 2006.189.08:10:50.52#ibcon#about to read 6, iclass 22, count 2 2006.189.08:10:50.52#ibcon#read 6, iclass 22, count 2 2006.189.08:10:50.52#ibcon#end of sib2, iclass 22, count 2 2006.189.08:10:50.52#ibcon#*after write, iclass 22, count 2 2006.189.08:10:50.52#ibcon#*before return 0, iclass 22, count 2 2006.189.08:10:50.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:10:50.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:10:50.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.08:10:50.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:50.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:10:50.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:10:50.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:10:50.64#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:10:50.64#ibcon#first serial, iclass 22, count 0 2006.189.08:10:50.64#ibcon#enter sib2, iclass 22, count 0 2006.189.08:10:50.64#ibcon#flushed, iclass 22, count 0 2006.189.08:10:50.64#ibcon#about to write, iclass 22, count 0 2006.189.08:10:50.64#ibcon#wrote, iclass 22, count 0 2006.189.08:10:50.64#ibcon#about to read 3, iclass 22, count 0 2006.189.08:10:50.66#ibcon#read 3, iclass 22, count 0 2006.189.08:10:50.66#ibcon#about to read 4, iclass 22, count 0 2006.189.08:10:50.66#ibcon#read 4, iclass 22, count 0 2006.189.08:10:50.66#ibcon#about to read 5, iclass 22, count 0 2006.189.08:10:50.66#ibcon#read 5, iclass 22, count 0 2006.189.08:10:50.66#ibcon#about to read 6, iclass 22, count 0 2006.189.08:10:50.66#ibcon#read 6, iclass 22, count 0 2006.189.08:10:50.66#ibcon#end of sib2, iclass 22, count 0 2006.189.08:10:50.66#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:10:50.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:10:50.66#ibcon#[25=USB\r\n] 2006.189.08:10:50.66#ibcon#*before write, iclass 22, count 0 2006.189.08:10:50.66#ibcon#enter sib2, iclass 22, count 0 2006.189.08:10:50.66#ibcon#flushed, iclass 22, count 0 2006.189.08:10:50.66#ibcon#about to write, iclass 22, count 0 2006.189.08:10:50.66#ibcon#wrote, iclass 22, count 0 2006.189.08:10:50.66#ibcon#about to read 3, iclass 22, count 0 2006.189.08:10:50.69#ibcon#read 3, iclass 22, count 0 2006.189.08:10:50.69#ibcon#about to read 4, iclass 22, count 0 2006.189.08:10:50.69#ibcon#read 4, iclass 22, count 0 2006.189.08:10:50.69#ibcon#about to read 5, iclass 22, count 0 2006.189.08:10:50.69#ibcon#read 5, iclass 22, count 0 2006.189.08:10:50.69#ibcon#about to read 6, iclass 22, count 0 2006.189.08:10:50.69#ibcon#read 6, iclass 22, count 0 2006.189.08:10:50.69#ibcon#end of sib2, iclass 22, count 0 2006.189.08:10:50.69#ibcon#*after write, iclass 22, count 0 2006.189.08:10:50.69#ibcon#*before return 0, iclass 22, count 0 2006.189.08:10:50.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:10:50.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:10:50.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:10:50.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:10:50.69$vc4f8/vblo=1,632.99 2006.189.08:10:50.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.08:10:50.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.08:10:50.69#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:50.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:50.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:50.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:50.69#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:10:50.69#ibcon#first serial, iclass 24, count 0 2006.189.08:10:50.69#ibcon#enter sib2, iclass 24, count 0 2006.189.08:10:50.70#ibcon#flushed, iclass 24, count 0 2006.189.08:10:50.70#ibcon#about to write, iclass 24, count 0 2006.189.08:10:50.70#ibcon#wrote, iclass 24, count 0 2006.189.08:10:50.70#ibcon#about to read 3, iclass 24, count 0 2006.189.08:10:50.71#ibcon#read 3, iclass 24, count 0 2006.189.08:10:50.71#ibcon#about to read 4, iclass 24, count 0 2006.189.08:10:50.71#ibcon#read 4, iclass 24, count 0 2006.189.08:10:50.71#ibcon#about to read 5, iclass 24, count 0 2006.189.08:10:50.71#ibcon#read 5, iclass 24, count 0 2006.189.08:10:50.71#ibcon#about to read 6, iclass 24, count 0 2006.189.08:10:50.71#ibcon#read 6, iclass 24, count 0 2006.189.08:10:50.71#ibcon#end of sib2, iclass 24, count 0 2006.189.08:10:50.71#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:10:50.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:10:50.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:10:50.71#ibcon#*before write, iclass 24, count 0 2006.189.08:10:50.71#ibcon#enter sib2, iclass 24, count 0 2006.189.08:10:50.71#ibcon#flushed, iclass 24, count 0 2006.189.08:10:50.71#ibcon#about to write, iclass 24, count 0 2006.189.08:10:50.71#ibcon#wrote, iclass 24, count 0 2006.189.08:10:50.71#ibcon#about to read 3, iclass 24, count 0 2006.189.08:10:50.75#ibcon#read 3, iclass 24, count 0 2006.189.08:10:50.75#ibcon#about to read 4, iclass 24, count 0 2006.189.08:10:50.75#ibcon#read 4, iclass 24, count 0 2006.189.08:10:50.75#ibcon#about to read 5, iclass 24, count 0 2006.189.08:10:50.75#ibcon#read 5, iclass 24, count 0 2006.189.08:10:50.75#ibcon#about to read 6, iclass 24, count 0 2006.189.08:10:50.75#ibcon#read 6, iclass 24, count 0 2006.189.08:10:50.75#ibcon#end of sib2, iclass 24, count 0 2006.189.08:10:50.75#ibcon#*after write, iclass 24, count 0 2006.189.08:10:50.75#ibcon#*before return 0, iclass 24, count 0 2006.189.08:10:50.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:50.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:10:50.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:10:50.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:10:50.75$vc4f8/vb=1,4 2006.189.08:10:50.75#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.08:10:50.75#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.08:10:50.75#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:50.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:50.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:50.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:50.76#ibcon#enter wrdev, iclass 26, count 2 2006.189.08:10:50.76#ibcon#first serial, iclass 26, count 2 2006.189.08:10:50.76#ibcon#enter sib2, iclass 26, count 2 2006.189.08:10:50.76#ibcon#flushed, iclass 26, count 2 2006.189.08:10:50.76#ibcon#about to write, iclass 26, count 2 2006.189.08:10:50.76#ibcon#wrote, iclass 26, count 2 2006.189.08:10:50.76#ibcon#about to read 3, iclass 26, count 2 2006.189.08:10:50.77#ibcon#read 3, iclass 26, count 2 2006.189.08:10:50.77#ibcon#about to read 4, iclass 26, count 2 2006.189.08:10:50.77#ibcon#read 4, iclass 26, count 2 2006.189.08:10:50.77#ibcon#about to read 5, iclass 26, count 2 2006.189.08:10:50.77#ibcon#read 5, iclass 26, count 2 2006.189.08:10:50.77#ibcon#about to read 6, iclass 26, count 2 2006.189.08:10:50.77#ibcon#read 6, iclass 26, count 2 2006.189.08:10:50.77#ibcon#end of sib2, iclass 26, count 2 2006.189.08:10:50.77#ibcon#*mode == 0, iclass 26, count 2 2006.189.08:10:50.77#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.08:10:50.77#ibcon#[27=AT01-04\r\n] 2006.189.08:10:50.77#ibcon#*before write, iclass 26, count 2 2006.189.08:10:50.77#ibcon#enter sib2, iclass 26, count 2 2006.189.08:10:50.77#ibcon#flushed, iclass 26, count 2 2006.189.08:10:50.77#ibcon#about to write, iclass 26, count 2 2006.189.08:10:50.77#ibcon#wrote, iclass 26, count 2 2006.189.08:10:50.77#ibcon#about to read 3, iclass 26, count 2 2006.189.08:10:50.80#ibcon#read 3, iclass 26, count 2 2006.189.08:10:50.80#ibcon#about to read 4, iclass 26, count 2 2006.189.08:10:50.80#ibcon#read 4, iclass 26, count 2 2006.189.08:10:50.80#ibcon#about to read 5, iclass 26, count 2 2006.189.08:10:50.80#ibcon#read 5, iclass 26, count 2 2006.189.08:10:50.80#ibcon#about to read 6, iclass 26, count 2 2006.189.08:10:50.80#ibcon#read 6, iclass 26, count 2 2006.189.08:10:50.80#ibcon#end of sib2, iclass 26, count 2 2006.189.08:10:50.80#ibcon#*after write, iclass 26, count 2 2006.189.08:10:50.80#ibcon#*before return 0, iclass 26, count 2 2006.189.08:10:50.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:50.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:10:50.80#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.08:10:50.80#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:50.80#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:50.92#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:50.92#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:50.92#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:10:50.92#ibcon#first serial, iclass 26, count 0 2006.189.08:10:50.92#ibcon#enter sib2, iclass 26, count 0 2006.189.08:10:50.92#ibcon#flushed, iclass 26, count 0 2006.189.08:10:50.92#ibcon#about to write, iclass 26, count 0 2006.189.08:10:50.92#ibcon#wrote, iclass 26, count 0 2006.189.08:10:50.92#ibcon#about to read 3, iclass 26, count 0 2006.189.08:10:50.94#ibcon#read 3, iclass 26, count 0 2006.189.08:10:50.94#ibcon#about to read 4, iclass 26, count 0 2006.189.08:10:50.94#ibcon#read 4, iclass 26, count 0 2006.189.08:10:50.94#ibcon#about to read 5, iclass 26, count 0 2006.189.08:10:50.94#ibcon#read 5, iclass 26, count 0 2006.189.08:10:50.94#ibcon#about to read 6, iclass 26, count 0 2006.189.08:10:50.94#ibcon#read 6, iclass 26, count 0 2006.189.08:10:50.94#ibcon#end of sib2, iclass 26, count 0 2006.189.08:10:50.94#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:10:50.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:10:50.94#ibcon#[27=USB\r\n] 2006.189.08:10:50.94#ibcon#*before write, iclass 26, count 0 2006.189.08:10:50.94#ibcon#enter sib2, iclass 26, count 0 2006.189.08:10:50.94#ibcon#flushed, iclass 26, count 0 2006.189.08:10:50.94#ibcon#about to write, iclass 26, count 0 2006.189.08:10:50.94#ibcon#wrote, iclass 26, count 0 2006.189.08:10:50.94#ibcon#about to read 3, iclass 26, count 0 2006.189.08:10:50.97#ibcon#read 3, iclass 26, count 0 2006.189.08:10:50.97#ibcon#about to read 4, iclass 26, count 0 2006.189.08:10:50.97#ibcon#read 4, iclass 26, count 0 2006.189.08:10:50.97#ibcon#about to read 5, iclass 26, count 0 2006.189.08:10:50.97#ibcon#read 5, iclass 26, count 0 2006.189.08:10:50.97#ibcon#about to read 6, iclass 26, count 0 2006.189.08:10:50.97#ibcon#read 6, iclass 26, count 0 2006.189.08:10:50.97#ibcon#end of sib2, iclass 26, count 0 2006.189.08:10:50.97#ibcon#*after write, iclass 26, count 0 2006.189.08:10:50.97#ibcon#*before return 0, iclass 26, count 0 2006.189.08:10:50.97#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:50.97#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:10:50.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:10:50.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:10:50.97$vc4f8/vblo=2,640.99 2006.189.08:10:50.97#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.08:10:50.97#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.08:10:50.97#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:50.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:50.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:50.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:50.97#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:10:50.98#ibcon#first serial, iclass 28, count 0 2006.189.08:10:50.98#ibcon#enter sib2, iclass 28, count 0 2006.189.08:10:50.98#ibcon#flushed, iclass 28, count 0 2006.189.08:10:50.98#ibcon#about to write, iclass 28, count 0 2006.189.08:10:50.98#ibcon#wrote, iclass 28, count 0 2006.189.08:10:50.98#ibcon#about to read 3, iclass 28, count 0 2006.189.08:10:50.99#ibcon#read 3, iclass 28, count 0 2006.189.08:10:50.99#ibcon#about to read 4, iclass 28, count 0 2006.189.08:10:50.99#ibcon#read 4, iclass 28, count 0 2006.189.08:10:50.99#ibcon#about to read 5, iclass 28, count 0 2006.189.08:10:50.99#ibcon#read 5, iclass 28, count 0 2006.189.08:10:50.99#ibcon#about to read 6, iclass 28, count 0 2006.189.08:10:50.99#ibcon#read 6, iclass 28, count 0 2006.189.08:10:50.99#ibcon#end of sib2, iclass 28, count 0 2006.189.08:10:50.99#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:10:50.99#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:10:50.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:10:50.99#ibcon#*before write, iclass 28, count 0 2006.189.08:10:50.99#ibcon#enter sib2, iclass 28, count 0 2006.189.08:10:50.99#ibcon#flushed, iclass 28, count 0 2006.189.08:10:50.99#ibcon#about to write, iclass 28, count 0 2006.189.08:10:50.99#ibcon#wrote, iclass 28, count 0 2006.189.08:10:50.99#ibcon#about to read 3, iclass 28, count 0 2006.189.08:10:51.03#ibcon#read 3, iclass 28, count 0 2006.189.08:10:51.03#ibcon#about to read 4, iclass 28, count 0 2006.189.08:10:51.03#ibcon#read 4, iclass 28, count 0 2006.189.08:10:51.03#ibcon#about to read 5, iclass 28, count 0 2006.189.08:10:51.03#ibcon#read 5, iclass 28, count 0 2006.189.08:10:51.03#ibcon#about to read 6, iclass 28, count 0 2006.189.08:10:51.03#ibcon#read 6, iclass 28, count 0 2006.189.08:10:51.03#ibcon#end of sib2, iclass 28, count 0 2006.189.08:10:51.03#ibcon#*after write, iclass 28, count 0 2006.189.08:10:51.03#ibcon#*before return 0, iclass 28, count 0 2006.189.08:10:51.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:51.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:10:51.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:10:51.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:10:51.03$vc4f8/vb=2,4 2006.189.08:10:51.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.08:10:51.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.08:10:51.03#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:51.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:51.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:51.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:51.09#ibcon#enter wrdev, iclass 30, count 2 2006.189.08:10:51.09#ibcon#first serial, iclass 30, count 2 2006.189.08:10:51.09#ibcon#enter sib2, iclass 30, count 2 2006.189.08:10:51.09#ibcon#flushed, iclass 30, count 2 2006.189.08:10:51.09#ibcon#about to write, iclass 30, count 2 2006.189.08:10:51.09#ibcon#wrote, iclass 30, count 2 2006.189.08:10:51.09#ibcon#about to read 3, iclass 30, count 2 2006.189.08:10:51.11#ibcon#read 3, iclass 30, count 2 2006.189.08:10:51.11#ibcon#about to read 4, iclass 30, count 2 2006.189.08:10:51.11#ibcon#read 4, iclass 30, count 2 2006.189.08:10:51.11#ibcon#about to read 5, iclass 30, count 2 2006.189.08:10:51.11#ibcon#read 5, iclass 30, count 2 2006.189.08:10:51.11#ibcon#about to read 6, iclass 30, count 2 2006.189.08:10:51.11#ibcon#read 6, iclass 30, count 2 2006.189.08:10:51.11#ibcon#end of sib2, iclass 30, count 2 2006.189.08:10:51.11#ibcon#*mode == 0, iclass 30, count 2 2006.189.08:10:51.11#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.08:10:51.11#ibcon#[27=AT02-04\r\n] 2006.189.08:10:51.11#ibcon#*before write, iclass 30, count 2 2006.189.08:10:51.11#ibcon#enter sib2, iclass 30, count 2 2006.189.08:10:51.11#ibcon#flushed, iclass 30, count 2 2006.189.08:10:51.11#ibcon#about to write, iclass 30, count 2 2006.189.08:10:51.11#ibcon#wrote, iclass 30, count 2 2006.189.08:10:51.11#ibcon#about to read 3, iclass 30, count 2 2006.189.08:10:51.14#ibcon#read 3, iclass 30, count 2 2006.189.08:10:51.14#ibcon#about to read 4, iclass 30, count 2 2006.189.08:10:51.14#ibcon#read 4, iclass 30, count 2 2006.189.08:10:51.14#ibcon#about to read 5, iclass 30, count 2 2006.189.08:10:51.14#ibcon#read 5, iclass 30, count 2 2006.189.08:10:51.14#ibcon#about to read 6, iclass 30, count 2 2006.189.08:10:51.14#ibcon#read 6, iclass 30, count 2 2006.189.08:10:51.14#ibcon#end of sib2, iclass 30, count 2 2006.189.08:10:51.14#ibcon#*after write, iclass 30, count 2 2006.189.08:10:51.14#ibcon#*before return 0, iclass 30, count 2 2006.189.08:10:51.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:51.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:10:51.14#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.08:10:51.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:51.14#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:51.26#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:51.26#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:51.26#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:10:51.26#ibcon#first serial, iclass 30, count 0 2006.189.08:10:51.26#ibcon#enter sib2, iclass 30, count 0 2006.189.08:10:51.26#ibcon#flushed, iclass 30, count 0 2006.189.08:10:51.26#ibcon#about to write, iclass 30, count 0 2006.189.08:10:51.26#ibcon#wrote, iclass 30, count 0 2006.189.08:10:51.26#ibcon#about to read 3, iclass 30, count 0 2006.189.08:10:51.28#ibcon#read 3, iclass 30, count 0 2006.189.08:10:51.28#ibcon#about to read 4, iclass 30, count 0 2006.189.08:10:51.28#ibcon#read 4, iclass 30, count 0 2006.189.08:10:51.28#ibcon#about to read 5, iclass 30, count 0 2006.189.08:10:51.28#ibcon#read 5, iclass 30, count 0 2006.189.08:10:51.28#ibcon#about to read 6, iclass 30, count 0 2006.189.08:10:51.28#ibcon#read 6, iclass 30, count 0 2006.189.08:10:51.28#ibcon#end of sib2, iclass 30, count 0 2006.189.08:10:51.28#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:10:51.28#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:10:51.28#ibcon#[27=USB\r\n] 2006.189.08:10:51.28#ibcon#*before write, iclass 30, count 0 2006.189.08:10:51.28#ibcon#enter sib2, iclass 30, count 0 2006.189.08:10:51.28#ibcon#flushed, iclass 30, count 0 2006.189.08:10:51.28#ibcon#about to write, iclass 30, count 0 2006.189.08:10:51.28#ibcon#wrote, iclass 30, count 0 2006.189.08:10:51.28#ibcon#about to read 3, iclass 30, count 0 2006.189.08:10:51.31#ibcon#read 3, iclass 30, count 0 2006.189.08:10:51.31#ibcon#about to read 4, iclass 30, count 0 2006.189.08:10:51.31#ibcon#read 4, iclass 30, count 0 2006.189.08:10:51.31#ibcon#about to read 5, iclass 30, count 0 2006.189.08:10:51.31#ibcon#read 5, iclass 30, count 0 2006.189.08:10:51.31#ibcon#about to read 6, iclass 30, count 0 2006.189.08:10:51.31#ibcon#read 6, iclass 30, count 0 2006.189.08:10:51.31#ibcon#end of sib2, iclass 30, count 0 2006.189.08:10:51.31#ibcon#*after write, iclass 30, count 0 2006.189.08:10:51.31#ibcon#*before return 0, iclass 30, count 0 2006.189.08:10:51.31#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:51.31#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:10:51.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:10:51.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:10:51.31$vc4f8/vblo=3,656.99 2006.189.08:10:51.31#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.08:10:51.31#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.08:10:51.31#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:51.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:51.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:51.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:51.31#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:10:51.32#ibcon#first serial, iclass 32, count 0 2006.189.08:10:51.32#ibcon#enter sib2, iclass 32, count 0 2006.189.08:10:51.32#ibcon#flushed, iclass 32, count 0 2006.189.08:10:51.32#ibcon#about to write, iclass 32, count 0 2006.189.08:10:51.32#ibcon#wrote, iclass 32, count 0 2006.189.08:10:51.32#ibcon#about to read 3, iclass 32, count 0 2006.189.08:10:51.33#ibcon#read 3, iclass 32, count 0 2006.189.08:10:51.33#ibcon#about to read 4, iclass 32, count 0 2006.189.08:10:51.33#ibcon#read 4, iclass 32, count 0 2006.189.08:10:51.33#ibcon#about to read 5, iclass 32, count 0 2006.189.08:10:51.33#ibcon#read 5, iclass 32, count 0 2006.189.08:10:51.33#ibcon#about to read 6, iclass 32, count 0 2006.189.08:10:51.33#ibcon#read 6, iclass 32, count 0 2006.189.08:10:51.33#ibcon#end of sib2, iclass 32, count 0 2006.189.08:10:51.33#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:10:51.33#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:10:51.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:10:51.33#ibcon#*before write, iclass 32, count 0 2006.189.08:10:51.33#ibcon#enter sib2, iclass 32, count 0 2006.189.08:10:51.33#ibcon#flushed, iclass 32, count 0 2006.189.08:10:51.33#ibcon#about to write, iclass 32, count 0 2006.189.08:10:51.33#ibcon#wrote, iclass 32, count 0 2006.189.08:10:51.33#ibcon#about to read 3, iclass 32, count 0 2006.189.08:10:51.37#ibcon#read 3, iclass 32, count 0 2006.189.08:10:51.37#ibcon#about to read 4, iclass 32, count 0 2006.189.08:10:51.37#ibcon#read 4, iclass 32, count 0 2006.189.08:10:51.37#ibcon#about to read 5, iclass 32, count 0 2006.189.08:10:51.37#ibcon#read 5, iclass 32, count 0 2006.189.08:10:51.37#ibcon#about to read 6, iclass 32, count 0 2006.189.08:10:51.37#ibcon#read 6, iclass 32, count 0 2006.189.08:10:51.37#ibcon#end of sib2, iclass 32, count 0 2006.189.08:10:51.37#ibcon#*after write, iclass 32, count 0 2006.189.08:10:51.37#ibcon#*before return 0, iclass 32, count 0 2006.189.08:10:51.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:51.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:10:51.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:10:51.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:10:51.37$vc4f8/vb=3,4 2006.189.08:10:51.37#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.08:10:51.37#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.08:10:51.37#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:51.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:51.43#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:51.43#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:51.43#ibcon#enter wrdev, iclass 34, count 2 2006.189.08:10:51.43#ibcon#first serial, iclass 34, count 2 2006.189.08:10:51.43#ibcon#enter sib2, iclass 34, count 2 2006.189.08:10:51.43#ibcon#flushed, iclass 34, count 2 2006.189.08:10:51.43#ibcon#about to write, iclass 34, count 2 2006.189.08:10:51.43#ibcon#wrote, iclass 34, count 2 2006.189.08:10:51.43#ibcon#about to read 3, iclass 34, count 2 2006.189.08:10:51.45#ibcon#read 3, iclass 34, count 2 2006.189.08:10:51.45#ibcon#about to read 4, iclass 34, count 2 2006.189.08:10:51.45#ibcon#read 4, iclass 34, count 2 2006.189.08:10:51.45#ibcon#about to read 5, iclass 34, count 2 2006.189.08:10:51.45#ibcon#read 5, iclass 34, count 2 2006.189.08:10:51.45#ibcon#about to read 6, iclass 34, count 2 2006.189.08:10:51.45#ibcon#read 6, iclass 34, count 2 2006.189.08:10:51.45#ibcon#end of sib2, iclass 34, count 2 2006.189.08:10:51.45#ibcon#*mode == 0, iclass 34, count 2 2006.189.08:10:51.45#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.08:10:51.45#ibcon#[27=AT03-04\r\n] 2006.189.08:10:51.45#ibcon#*before write, iclass 34, count 2 2006.189.08:10:51.45#ibcon#enter sib2, iclass 34, count 2 2006.189.08:10:51.45#ibcon#flushed, iclass 34, count 2 2006.189.08:10:51.45#ibcon#about to write, iclass 34, count 2 2006.189.08:10:51.45#ibcon#wrote, iclass 34, count 2 2006.189.08:10:51.45#ibcon#about to read 3, iclass 34, count 2 2006.189.08:10:51.48#ibcon#read 3, iclass 34, count 2 2006.189.08:10:51.48#ibcon#about to read 4, iclass 34, count 2 2006.189.08:10:51.48#ibcon#read 4, iclass 34, count 2 2006.189.08:10:51.48#ibcon#about to read 5, iclass 34, count 2 2006.189.08:10:51.48#ibcon#read 5, iclass 34, count 2 2006.189.08:10:51.48#ibcon#about to read 6, iclass 34, count 2 2006.189.08:10:51.48#ibcon#read 6, iclass 34, count 2 2006.189.08:10:51.48#ibcon#end of sib2, iclass 34, count 2 2006.189.08:10:51.48#ibcon#*after write, iclass 34, count 2 2006.189.08:10:51.48#ibcon#*before return 0, iclass 34, count 2 2006.189.08:10:51.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:51.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:10:51.48#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.08:10:51.48#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:51.48#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:51.60#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:51.60#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:51.60#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:10:51.60#ibcon#first serial, iclass 34, count 0 2006.189.08:10:51.60#ibcon#enter sib2, iclass 34, count 0 2006.189.08:10:51.60#ibcon#flushed, iclass 34, count 0 2006.189.08:10:51.60#ibcon#about to write, iclass 34, count 0 2006.189.08:10:51.60#ibcon#wrote, iclass 34, count 0 2006.189.08:10:51.60#ibcon#about to read 3, iclass 34, count 0 2006.189.08:10:51.62#ibcon#read 3, iclass 34, count 0 2006.189.08:10:51.62#ibcon#about to read 4, iclass 34, count 0 2006.189.08:10:51.62#ibcon#read 4, iclass 34, count 0 2006.189.08:10:51.62#ibcon#about to read 5, iclass 34, count 0 2006.189.08:10:51.62#ibcon#read 5, iclass 34, count 0 2006.189.08:10:51.62#ibcon#about to read 6, iclass 34, count 0 2006.189.08:10:51.62#ibcon#read 6, iclass 34, count 0 2006.189.08:10:51.62#ibcon#end of sib2, iclass 34, count 0 2006.189.08:10:51.62#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:10:51.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:10:51.62#ibcon#[27=USB\r\n] 2006.189.08:10:51.62#ibcon#*before write, iclass 34, count 0 2006.189.08:10:51.62#ibcon#enter sib2, iclass 34, count 0 2006.189.08:10:51.62#ibcon#flushed, iclass 34, count 0 2006.189.08:10:51.62#ibcon#about to write, iclass 34, count 0 2006.189.08:10:51.62#ibcon#wrote, iclass 34, count 0 2006.189.08:10:51.62#ibcon#about to read 3, iclass 34, count 0 2006.189.08:10:51.65#ibcon#read 3, iclass 34, count 0 2006.189.08:10:51.65#ibcon#about to read 4, iclass 34, count 0 2006.189.08:10:51.65#ibcon#read 4, iclass 34, count 0 2006.189.08:10:51.65#ibcon#about to read 5, iclass 34, count 0 2006.189.08:10:51.65#ibcon#read 5, iclass 34, count 0 2006.189.08:10:51.65#ibcon#about to read 6, iclass 34, count 0 2006.189.08:10:51.65#ibcon#read 6, iclass 34, count 0 2006.189.08:10:51.65#ibcon#end of sib2, iclass 34, count 0 2006.189.08:10:51.65#ibcon#*after write, iclass 34, count 0 2006.189.08:10:51.65#ibcon#*before return 0, iclass 34, count 0 2006.189.08:10:51.65#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:51.65#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:10:51.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:10:51.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:10:51.65$vc4f8/vblo=4,712.99 2006.189.08:10:51.65#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.08:10:51.65#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.08:10:51.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:51.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:51.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:51.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:51.65#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:10:51.66#ibcon#first serial, iclass 36, count 0 2006.189.08:10:51.66#ibcon#enter sib2, iclass 36, count 0 2006.189.08:10:51.66#ibcon#flushed, iclass 36, count 0 2006.189.08:10:51.66#ibcon#about to write, iclass 36, count 0 2006.189.08:10:51.66#ibcon#wrote, iclass 36, count 0 2006.189.08:10:51.66#ibcon#about to read 3, iclass 36, count 0 2006.189.08:10:51.67#ibcon#read 3, iclass 36, count 0 2006.189.08:10:51.67#ibcon#about to read 4, iclass 36, count 0 2006.189.08:10:51.67#ibcon#read 4, iclass 36, count 0 2006.189.08:10:51.67#ibcon#about to read 5, iclass 36, count 0 2006.189.08:10:51.67#ibcon#read 5, iclass 36, count 0 2006.189.08:10:51.67#ibcon#about to read 6, iclass 36, count 0 2006.189.08:10:51.67#ibcon#read 6, iclass 36, count 0 2006.189.08:10:51.67#ibcon#end of sib2, iclass 36, count 0 2006.189.08:10:51.67#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:10:51.67#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:10:51.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:10:51.67#ibcon#*before write, iclass 36, count 0 2006.189.08:10:51.67#ibcon#enter sib2, iclass 36, count 0 2006.189.08:10:51.67#ibcon#flushed, iclass 36, count 0 2006.189.08:10:51.67#ibcon#about to write, iclass 36, count 0 2006.189.08:10:51.67#ibcon#wrote, iclass 36, count 0 2006.189.08:10:51.67#ibcon#about to read 3, iclass 36, count 0 2006.189.08:10:51.71#ibcon#read 3, iclass 36, count 0 2006.189.08:10:51.71#ibcon#about to read 4, iclass 36, count 0 2006.189.08:10:51.71#ibcon#read 4, iclass 36, count 0 2006.189.08:10:51.71#ibcon#about to read 5, iclass 36, count 0 2006.189.08:10:51.71#ibcon#read 5, iclass 36, count 0 2006.189.08:10:51.71#ibcon#about to read 6, iclass 36, count 0 2006.189.08:10:51.71#ibcon#read 6, iclass 36, count 0 2006.189.08:10:51.71#ibcon#end of sib2, iclass 36, count 0 2006.189.08:10:51.71#ibcon#*after write, iclass 36, count 0 2006.189.08:10:51.71#ibcon#*before return 0, iclass 36, count 0 2006.189.08:10:51.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:51.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:10:51.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:10:51.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:10:51.71$vc4f8/vb=4,4 2006.189.08:10:51.71#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.08:10:51.71#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.08:10:51.71#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:51.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:51.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:51.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:51.77#ibcon#enter wrdev, iclass 38, count 2 2006.189.08:10:51.77#ibcon#first serial, iclass 38, count 2 2006.189.08:10:51.77#ibcon#enter sib2, iclass 38, count 2 2006.189.08:10:51.77#ibcon#flushed, iclass 38, count 2 2006.189.08:10:51.77#ibcon#about to write, iclass 38, count 2 2006.189.08:10:51.77#ibcon#wrote, iclass 38, count 2 2006.189.08:10:51.77#ibcon#about to read 3, iclass 38, count 2 2006.189.08:10:51.79#ibcon#read 3, iclass 38, count 2 2006.189.08:10:51.79#ibcon#about to read 4, iclass 38, count 2 2006.189.08:10:51.79#ibcon#read 4, iclass 38, count 2 2006.189.08:10:51.79#ibcon#about to read 5, iclass 38, count 2 2006.189.08:10:51.79#ibcon#read 5, iclass 38, count 2 2006.189.08:10:51.79#ibcon#about to read 6, iclass 38, count 2 2006.189.08:10:51.79#ibcon#read 6, iclass 38, count 2 2006.189.08:10:51.79#ibcon#end of sib2, iclass 38, count 2 2006.189.08:10:51.79#ibcon#*mode == 0, iclass 38, count 2 2006.189.08:10:51.79#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.08:10:51.79#ibcon#[27=AT04-04\r\n] 2006.189.08:10:51.79#ibcon#*before write, iclass 38, count 2 2006.189.08:10:51.79#ibcon#enter sib2, iclass 38, count 2 2006.189.08:10:51.79#ibcon#flushed, iclass 38, count 2 2006.189.08:10:51.79#ibcon#about to write, iclass 38, count 2 2006.189.08:10:51.79#ibcon#wrote, iclass 38, count 2 2006.189.08:10:51.79#ibcon#about to read 3, iclass 38, count 2 2006.189.08:10:51.82#ibcon#read 3, iclass 38, count 2 2006.189.08:10:51.82#ibcon#about to read 4, iclass 38, count 2 2006.189.08:10:51.82#ibcon#read 4, iclass 38, count 2 2006.189.08:10:51.82#ibcon#about to read 5, iclass 38, count 2 2006.189.08:10:51.82#ibcon#read 5, iclass 38, count 2 2006.189.08:10:51.82#ibcon#about to read 6, iclass 38, count 2 2006.189.08:10:51.82#ibcon#read 6, iclass 38, count 2 2006.189.08:10:51.82#ibcon#end of sib2, iclass 38, count 2 2006.189.08:10:51.82#ibcon#*after write, iclass 38, count 2 2006.189.08:10:51.82#ibcon#*before return 0, iclass 38, count 2 2006.189.08:10:51.82#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:51.82#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:10:51.82#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.08:10:51.82#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:51.82#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:51.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:51.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:51.94#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:10:51.94#ibcon#first serial, iclass 38, count 0 2006.189.08:10:51.94#ibcon#enter sib2, iclass 38, count 0 2006.189.08:10:51.94#ibcon#flushed, iclass 38, count 0 2006.189.08:10:51.94#ibcon#about to write, iclass 38, count 0 2006.189.08:10:51.94#ibcon#wrote, iclass 38, count 0 2006.189.08:10:51.94#ibcon#about to read 3, iclass 38, count 0 2006.189.08:10:51.96#ibcon#read 3, iclass 38, count 0 2006.189.08:10:51.96#ibcon#about to read 4, iclass 38, count 0 2006.189.08:10:51.96#ibcon#read 4, iclass 38, count 0 2006.189.08:10:51.96#ibcon#about to read 5, iclass 38, count 0 2006.189.08:10:51.96#ibcon#read 5, iclass 38, count 0 2006.189.08:10:51.96#ibcon#about to read 6, iclass 38, count 0 2006.189.08:10:51.96#ibcon#read 6, iclass 38, count 0 2006.189.08:10:51.96#ibcon#end of sib2, iclass 38, count 0 2006.189.08:10:51.96#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:10:51.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:10:51.96#ibcon#[27=USB\r\n] 2006.189.08:10:51.96#ibcon#*before write, iclass 38, count 0 2006.189.08:10:51.96#ibcon#enter sib2, iclass 38, count 0 2006.189.08:10:51.96#ibcon#flushed, iclass 38, count 0 2006.189.08:10:51.96#ibcon#about to write, iclass 38, count 0 2006.189.08:10:51.96#ibcon#wrote, iclass 38, count 0 2006.189.08:10:51.96#ibcon#about to read 3, iclass 38, count 0 2006.189.08:10:51.99#ibcon#read 3, iclass 38, count 0 2006.189.08:10:51.99#ibcon#about to read 4, iclass 38, count 0 2006.189.08:10:51.99#ibcon#read 4, iclass 38, count 0 2006.189.08:10:51.99#ibcon#about to read 5, iclass 38, count 0 2006.189.08:10:51.99#ibcon#read 5, iclass 38, count 0 2006.189.08:10:51.99#ibcon#about to read 6, iclass 38, count 0 2006.189.08:10:51.99#ibcon#read 6, iclass 38, count 0 2006.189.08:10:51.99#ibcon#end of sib2, iclass 38, count 0 2006.189.08:10:51.99#ibcon#*after write, iclass 38, count 0 2006.189.08:10:51.99#ibcon#*before return 0, iclass 38, count 0 2006.189.08:10:51.99#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:51.99#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:10:51.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:10:51.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:10:51.99$vc4f8/vblo=5,744.99 2006.189.08:10:51.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.08:10:51.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.08:10:51.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:51.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:51.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:51.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:51.99#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:10:51.99#ibcon#first serial, iclass 40, count 0 2006.189.08:10:51.99#ibcon#enter sib2, iclass 40, count 0 2006.189.08:10:51.99#ibcon#flushed, iclass 40, count 0 2006.189.08:10:52.00#ibcon#about to write, iclass 40, count 0 2006.189.08:10:52.00#ibcon#wrote, iclass 40, count 0 2006.189.08:10:52.00#ibcon#about to read 3, iclass 40, count 0 2006.189.08:10:52.01#ibcon#read 3, iclass 40, count 0 2006.189.08:10:52.01#ibcon#about to read 4, iclass 40, count 0 2006.189.08:10:52.01#ibcon#read 4, iclass 40, count 0 2006.189.08:10:52.01#ibcon#about to read 5, iclass 40, count 0 2006.189.08:10:52.01#ibcon#read 5, iclass 40, count 0 2006.189.08:10:52.01#ibcon#about to read 6, iclass 40, count 0 2006.189.08:10:52.01#ibcon#read 6, iclass 40, count 0 2006.189.08:10:52.01#ibcon#end of sib2, iclass 40, count 0 2006.189.08:10:52.01#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:10:52.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:10:52.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:10:52.01#ibcon#*before write, iclass 40, count 0 2006.189.08:10:52.01#ibcon#enter sib2, iclass 40, count 0 2006.189.08:10:52.01#ibcon#flushed, iclass 40, count 0 2006.189.08:10:52.01#ibcon#about to write, iclass 40, count 0 2006.189.08:10:52.01#ibcon#wrote, iclass 40, count 0 2006.189.08:10:52.01#ibcon#about to read 3, iclass 40, count 0 2006.189.08:10:52.05#ibcon#read 3, iclass 40, count 0 2006.189.08:10:52.05#ibcon#about to read 4, iclass 40, count 0 2006.189.08:10:52.05#ibcon#read 4, iclass 40, count 0 2006.189.08:10:52.05#ibcon#about to read 5, iclass 40, count 0 2006.189.08:10:52.05#ibcon#read 5, iclass 40, count 0 2006.189.08:10:52.05#ibcon#about to read 6, iclass 40, count 0 2006.189.08:10:52.05#ibcon#read 6, iclass 40, count 0 2006.189.08:10:52.05#ibcon#end of sib2, iclass 40, count 0 2006.189.08:10:52.05#ibcon#*after write, iclass 40, count 0 2006.189.08:10:52.05#ibcon#*before return 0, iclass 40, count 0 2006.189.08:10:52.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:52.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:10:52.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:10:52.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:10:52.05$vc4f8/vb=5,4 2006.189.08:10:52.05#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.08:10:52.05#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.08:10:52.05#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:52.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:52.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:52.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:52.11#ibcon#enter wrdev, iclass 4, count 2 2006.189.08:10:52.11#ibcon#first serial, iclass 4, count 2 2006.189.08:10:52.11#ibcon#enter sib2, iclass 4, count 2 2006.189.08:10:52.11#ibcon#flushed, iclass 4, count 2 2006.189.08:10:52.11#ibcon#about to write, iclass 4, count 2 2006.189.08:10:52.11#ibcon#wrote, iclass 4, count 2 2006.189.08:10:52.11#ibcon#about to read 3, iclass 4, count 2 2006.189.08:10:52.13#ibcon#read 3, iclass 4, count 2 2006.189.08:10:52.13#ibcon#about to read 4, iclass 4, count 2 2006.189.08:10:52.13#ibcon#read 4, iclass 4, count 2 2006.189.08:10:52.13#ibcon#about to read 5, iclass 4, count 2 2006.189.08:10:52.13#ibcon#read 5, iclass 4, count 2 2006.189.08:10:52.13#ibcon#about to read 6, iclass 4, count 2 2006.189.08:10:52.13#ibcon#read 6, iclass 4, count 2 2006.189.08:10:52.13#ibcon#end of sib2, iclass 4, count 2 2006.189.08:10:52.13#ibcon#*mode == 0, iclass 4, count 2 2006.189.08:10:52.13#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.08:10:52.13#ibcon#[27=AT05-04\r\n] 2006.189.08:10:52.13#ibcon#*before write, iclass 4, count 2 2006.189.08:10:52.13#ibcon#enter sib2, iclass 4, count 2 2006.189.08:10:52.13#ibcon#flushed, iclass 4, count 2 2006.189.08:10:52.13#ibcon#about to write, iclass 4, count 2 2006.189.08:10:52.13#ibcon#wrote, iclass 4, count 2 2006.189.08:10:52.13#ibcon#about to read 3, iclass 4, count 2 2006.189.08:10:52.16#ibcon#read 3, iclass 4, count 2 2006.189.08:10:52.16#ibcon#about to read 4, iclass 4, count 2 2006.189.08:10:52.16#ibcon#read 4, iclass 4, count 2 2006.189.08:10:52.16#ibcon#about to read 5, iclass 4, count 2 2006.189.08:10:52.16#ibcon#read 5, iclass 4, count 2 2006.189.08:10:52.16#ibcon#about to read 6, iclass 4, count 2 2006.189.08:10:52.16#ibcon#read 6, iclass 4, count 2 2006.189.08:10:52.16#ibcon#end of sib2, iclass 4, count 2 2006.189.08:10:52.16#ibcon#*after write, iclass 4, count 2 2006.189.08:10:52.16#ibcon#*before return 0, iclass 4, count 2 2006.189.08:10:52.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:52.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:10:52.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.08:10:52.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:52.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:52.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:52.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:52.28#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:10:52.28#ibcon#first serial, iclass 4, count 0 2006.189.08:10:52.28#ibcon#enter sib2, iclass 4, count 0 2006.189.08:10:52.28#ibcon#flushed, iclass 4, count 0 2006.189.08:10:52.28#ibcon#about to write, iclass 4, count 0 2006.189.08:10:52.28#ibcon#wrote, iclass 4, count 0 2006.189.08:10:52.28#ibcon#about to read 3, iclass 4, count 0 2006.189.08:10:52.30#ibcon#read 3, iclass 4, count 0 2006.189.08:10:52.30#ibcon#about to read 4, iclass 4, count 0 2006.189.08:10:52.30#ibcon#read 4, iclass 4, count 0 2006.189.08:10:52.30#ibcon#about to read 5, iclass 4, count 0 2006.189.08:10:52.30#ibcon#read 5, iclass 4, count 0 2006.189.08:10:52.30#ibcon#about to read 6, iclass 4, count 0 2006.189.08:10:52.30#ibcon#read 6, iclass 4, count 0 2006.189.08:10:52.30#ibcon#end of sib2, iclass 4, count 0 2006.189.08:10:52.30#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:10:52.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:10:52.30#ibcon#[27=USB\r\n] 2006.189.08:10:52.30#ibcon#*before write, iclass 4, count 0 2006.189.08:10:52.30#ibcon#enter sib2, iclass 4, count 0 2006.189.08:10:52.30#ibcon#flushed, iclass 4, count 0 2006.189.08:10:52.30#ibcon#about to write, iclass 4, count 0 2006.189.08:10:52.30#ibcon#wrote, iclass 4, count 0 2006.189.08:10:52.30#ibcon#about to read 3, iclass 4, count 0 2006.189.08:10:52.33#ibcon#read 3, iclass 4, count 0 2006.189.08:10:52.33#ibcon#about to read 4, iclass 4, count 0 2006.189.08:10:52.33#ibcon#read 4, iclass 4, count 0 2006.189.08:10:52.33#ibcon#about to read 5, iclass 4, count 0 2006.189.08:10:52.33#ibcon#read 5, iclass 4, count 0 2006.189.08:10:52.33#ibcon#about to read 6, iclass 4, count 0 2006.189.08:10:52.33#ibcon#read 6, iclass 4, count 0 2006.189.08:10:52.33#ibcon#end of sib2, iclass 4, count 0 2006.189.08:10:52.33#ibcon#*after write, iclass 4, count 0 2006.189.08:10:52.33#ibcon#*before return 0, iclass 4, count 0 2006.189.08:10:52.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:52.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:10:52.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:10:52.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:10:52.33$vc4f8/vblo=6,752.99 2006.189.08:10:52.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.08:10:52.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.08:10:52.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:10:52.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:52.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:52.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:52.33#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:10:52.33#ibcon#first serial, iclass 6, count 0 2006.189.08:10:52.33#ibcon#enter sib2, iclass 6, count 0 2006.189.08:10:52.33#ibcon#flushed, iclass 6, count 0 2006.189.08:10:52.34#ibcon#about to write, iclass 6, count 0 2006.189.08:10:52.34#ibcon#wrote, iclass 6, count 0 2006.189.08:10:52.34#ibcon#about to read 3, iclass 6, count 0 2006.189.08:10:52.35#ibcon#read 3, iclass 6, count 0 2006.189.08:10:52.35#ibcon#about to read 4, iclass 6, count 0 2006.189.08:10:52.35#ibcon#read 4, iclass 6, count 0 2006.189.08:10:52.35#ibcon#about to read 5, iclass 6, count 0 2006.189.08:10:52.35#ibcon#read 5, iclass 6, count 0 2006.189.08:10:52.35#ibcon#about to read 6, iclass 6, count 0 2006.189.08:10:52.35#ibcon#read 6, iclass 6, count 0 2006.189.08:10:52.35#ibcon#end of sib2, iclass 6, count 0 2006.189.08:10:52.35#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:10:52.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:10:52.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:10:52.35#ibcon#*before write, iclass 6, count 0 2006.189.08:10:52.35#ibcon#enter sib2, iclass 6, count 0 2006.189.08:10:52.35#ibcon#flushed, iclass 6, count 0 2006.189.08:10:52.35#ibcon#about to write, iclass 6, count 0 2006.189.08:10:52.35#ibcon#wrote, iclass 6, count 0 2006.189.08:10:52.35#ibcon#about to read 3, iclass 6, count 0 2006.189.08:10:52.39#ibcon#read 3, iclass 6, count 0 2006.189.08:10:52.39#ibcon#about to read 4, iclass 6, count 0 2006.189.08:10:52.39#ibcon#read 4, iclass 6, count 0 2006.189.08:10:52.39#ibcon#about to read 5, iclass 6, count 0 2006.189.08:10:52.39#ibcon#read 5, iclass 6, count 0 2006.189.08:10:52.39#ibcon#about to read 6, iclass 6, count 0 2006.189.08:10:52.39#ibcon#read 6, iclass 6, count 0 2006.189.08:10:52.39#ibcon#end of sib2, iclass 6, count 0 2006.189.08:10:52.39#ibcon#*after write, iclass 6, count 0 2006.189.08:10:52.39#ibcon#*before return 0, iclass 6, count 0 2006.189.08:10:52.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:52.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:10:52.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:10:52.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:10:52.39$vc4f8/vb=6,4 2006.189.08:10:52.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.08:10:52.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.08:10:52.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:10:52.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:52.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:52.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:52.45#ibcon#enter wrdev, iclass 10, count 2 2006.189.08:10:52.45#ibcon#first serial, iclass 10, count 2 2006.189.08:10:52.45#ibcon#enter sib2, iclass 10, count 2 2006.189.08:10:52.45#ibcon#flushed, iclass 10, count 2 2006.189.08:10:52.45#ibcon#about to write, iclass 10, count 2 2006.189.08:10:52.45#ibcon#wrote, iclass 10, count 2 2006.189.08:10:52.45#ibcon#about to read 3, iclass 10, count 2 2006.189.08:10:52.47#ibcon#read 3, iclass 10, count 2 2006.189.08:10:52.47#ibcon#about to read 4, iclass 10, count 2 2006.189.08:10:52.47#ibcon#read 4, iclass 10, count 2 2006.189.08:10:52.47#ibcon#about to read 5, iclass 10, count 2 2006.189.08:10:52.47#ibcon#read 5, iclass 10, count 2 2006.189.08:10:52.47#ibcon#about to read 6, iclass 10, count 2 2006.189.08:10:52.47#ibcon#read 6, iclass 10, count 2 2006.189.08:10:52.47#ibcon#end of sib2, iclass 10, count 2 2006.189.08:10:52.47#ibcon#*mode == 0, iclass 10, count 2 2006.189.08:10:52.47#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.08:10:52.47#ibcon#[27=AT06-04\r\n] 2006.189.08:10:52.47#ibcon#*before write, iclass 10, count 2 2006.189.08:10:52.47#ibcon#enter sib2, iclass 10, count 2 2006.189.08:10:52.47#ibcon#flushed, iclass 10, count 2 2006.189.08:10:52.47#ibcon#about to write, iclass 10, count 2 2006.189.08:10:52.47#ibcon#wrote, iclass 10, count 2 2006.189.08:10:52.47#ibcon#about to read 3, iclass 10, count 2 2006.189.08:10:52.50#ibcon#read 3, iclass 10, count 2 2006.189.08:10:52.50#ibcon#about to read 4, iclass 10, count 2 2006.189.08:10:52.50#ibcon#read 4, iclass 10, count 2 2006.189.08:10:52.50#ibcon#about to read 5, iclass 10, count 2 2006.189.08:10:52.50#ibcon#read 5, iclass 10, count 2 2006.189.08:10:52.50#ibcon#about to read 6, iclass 10, count 2 2006.189.08:10:52.50#ibcon#read 6, iclass 10, count 2 2006.189.08:10:52.50#ibcon#end of sib2, iclass 10, count 2 2006.189.08:10:52.50#ibcon#*after write, iclass 10, count 2 2006.189.08:10:52.50#ibcon#*before return 0, iclass 10, count 2 2006.189.08:10:52.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:52.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:10:52.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.08:10:52.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:10:52.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:52.62#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:52.62#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:52.62#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:10:52.62#ibcon#first serial, iclass 10, count 0 2006.189.08:10:52.62#ibcon#enter sib2, iclass 10, count 0 2006.189.08:10:52.62#ibcon#flushed, iclass 10, count 0 2006.189.08:10:52.62#ibcon#about to write, iclass 10, count 0 2006.189.08:10:52.62#ibcon#wrote, iclass 10, count 0 2006.189.08:10:52.62#ibcon#about to read 3, iclass 10, count 0 2006.189.08:10:52.64#ibcon#read 3, iclass 10, count 0 2006.189.08:10:52.64#ibcon#about to read 4, iclass 10, count 0 2006.189.08:10:52.64#ibcon#read 4, iclass 10, count 0 2006.189.08:10:52.64#ibcon#about to read 5, iclass 10, count 0 2006.189.08:10:52.64#ibcon#read 5, iclass 10, count 0 2006.189.08:10:52.64#ibcon#about to read 6, iclass 10, count 0 2006.189.08:10:52.64#ibcon#read 6, iclass 10, count 0 2006.189.08:10:52.64#ibcon#end of sib2, iclass 10, count 0 2006.189.08:10:52.64#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:10:52.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:10:52.64#ibcon#[27=USB\r\n] 2006.189.08:10:52.64#ibcon#*before write, iclass 10, count 0 2006.189.08:10:52.64#ibcon#enter sib2, iclass 10, count 0 2006.189.08:10:52.64#ibcon#flushed, iclass 10, count 0 2006.189.08:10:52.64#ibcon#about to write, iclass 10, count 0 2006.189.08:10:52.64#ibcon#wrote, iclass 10, count 0 2006.189.08:10:52.64#ibcon#about to read 3, iclass 10, count 0 2006.189.08:10:52.67#ibcon#read 3, iclass 10, count 0 2006.189.08:10:52.67#ibcon#about to read 4, iclass 10, count 0 2006.189.08:10:52.67#ibcon#read 4, iclass 10, count 0 2006.189.08:10:52.67#ibcon#about to read 5, iclass 10, count 0 2006.189.08:10:52.67#ibcon#read 5, iclass 10, count 0 2006.189.08:10:52.67#ibcon#about to read 6, iclass 10, count 0 2006.189.08:10:52.67#ibcon#read 6, iclass 10, count 0 2006.189.08:10:52.67#ibcon#end of sib2, iclass 10, count 0 2006.189.08:10:52.67#ibcon#*after write, iclass 10, count 0 2006.189.08:10:52.67#ibcon#*before return 0, iclass 10, count 0 2006.189.08:10:52.67#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:52.67#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:10:52.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:10:52.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:10:52.67$vc4f8/vabw=wide 2006.189.08:10:52.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.08:10:52.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.08:10:52.67#ibcon#ireg 8 cls_cnt 0 2006.189.08:10:52.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:10:52.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:10:52.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:10:52.67#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:10:52.67#ibcon#first serial, iclass 12, count 0 2006.189.08:10:52.67#ibcon#enter sib2, iclass 12, count 0 2006.189.08:10:52.67#ibcon#flushed, iclass 12, count 0 2006.189.08:10:52.67#ibcon#about to write, iclass 12, count 0 2006.189.08:10:52.68#ibcon#wrote, iclass 12, count 0 2006.189.08:10:52.68#ibcon#about to read 3, iclass 12, count 0 2006.189.08:10:52.69#ibcon#read 3, iclass 12, count 0 2006.189.08:10:52.69#ibcon#about to read 4, iclass 12, count 0 2006.189.08:10:52.69#ibcon#read 4, iclass 12, count 0 2006.189.08:10:52.69#ibcon#about to read 5, iclass 12, count 0 2006.189.08:10:52.69#ibcon#read 5, iclass 12, count 0 2006.189.08:10:52.69#ibcon#about to read 6, iclass 12, count 0 2006.189.08:10:52.69#ibcon#read 6, iclass 12, count 0 2006.189.08:10:52.69#ibcon#end of sib2, iclass 12, count 0 2006.189.08:10:52.69#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:10:52.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:10:52.69#ibcon#[25=BW32\r\n] 2006.189.08:10:52.69#ibcon#*before write, iclass 12, count 0 2006.189.08:10:52.69#ibcon#enter sib2, iclass 12, count 0 2006.189.08:10:52.69#ibcon#flushed, iclass 12, count 0 2006.189.08:10:52.69#ibcon#about to write, iclass 12, count 0 2006.189.08:10:52.69#ibcon#wrote, iclass 12, count 0 2006.189.08:10:52.69#ibcon#about to read 3, iclass 12, count 0 2006.189.08:10:52.72#ibcon#read 3, iclass 12, count 0 2006.189.08:10:52.72#ibcon#about to read 4, iclass 12, count 0 2006.189.08:10:52.72#ibcon#read 4, iclass 12, count 0 2006.189.08:10:52.72#ibcon#about to read 5, iclass 12, count 0 2006.189.08:10:52.72#ibcon#read 5, iclass 12, count 0 2006.189.08:10:52.72#ibcon#about to read 6, iclass 12, count 0 2006.189.08:10:52.72#ibcon#read 6, iclass 12, count 0 2006.189.08:10:52.72#ibcon#end of sib2, iclass 12, count 0 2006.189.08:10:52.72#ibcon#*after write, iclass 12, count 0 2006.189.08:10:52.72#ibcon#*before return 0, iclass 12, count 0 2006.189.08:10:52.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:10:52.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:10:52.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:10:52.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:10:52.72$vc4f8/vbbw=wide 2006.189.08:10:52.72#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.08:10:52.72#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.08:10:52.72#ibcon#ireg 8 cls_cnt 0 2006.189.08:10:52.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:10:52.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:10:52.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:10:52.79#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:10:52.79#ibcon#first serial, iclass 14, count 0 2006.189.08:10:52.79#ibcon#enter sib2, iclass 14, count 0 2006.189.08:10:52.79#ibcon#flushed, iclass 14, count 0 2006.189.08:10:52.79#ibcon#about to write, iclass 14, count 0 2006.189.08:10:52.79#ibcon#wrote, iclass 14, count 0 2006.189.08:10:52.79#ibcon#about to read 3, iclass 14, count 0 2006.189.08:10:52.81#ibcon#read 3, iclass 14, count 0 2006.189.08:10:52.81#ibcon#about to read 4, iclass 14, count 0 2006.189.08:10:52.81#ibcon#read 4, iclass 14, count 0 2006.189.08:10:52.81#ibcon#about to read 5, iclass 14, count 0 2006.189.08:10:52.81#ibcon#read 5, iclass 14, count 0 2006.189.08:10:52.81#ibcon#about to read 6, iclass 14, count 0 2006.189.08:10:52.81#ibcon#read 6, iclass 14, count 0 2006.189.08:10:52.81#ibcon#end of sib2, iclass 14, count 0 2006.189.08:10:52.81#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:10:52.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:10:52.81#ibcon#[27=BW32\r\n] 2006.189.08:10:52.81#ibcon#*before write, iclass 14, count 0 2006.189.08:10:52.81#ibcon#enter sib2, iclass 14, count 0 2006.189.08:10:52.81#ibcon#flushed, iclass 14, count 0 2006.189.08:10:52.81#ibcon#about to write, iclass 14, count 0 2006.189.08:10:52.81#ibcon#wrote, iclass 14, count 0 2006.189.08:10:52.81#ibcon#about to read 3, iclass 14, count 0 2006.189.08:10:52.84#ibcon#read 3, iclass 14, count 0 2006.189.08:10:52.84#ibcon#about to read 4, iclass 14, count 0 2006.189.08:10:52.84#ibcon#read 4, iclass 14, count 0 2006.189.08:10:52.84#ibcon#about to read 5, iclass 14, count 0 2006.189.08:10:52.84#ibcon#read 5, iclass 14, count 0 2006.189.08:10:52.84#ibcon#about to read 6, iclass 14, count 0 2006.189.08:10:52.84#ibcon#read 6, iclass 14, count 0 2006.189.08:10:52.84#ibcon#end of sib2, iclass 14, count 0 2006.189.08:10:52.84#ibcon#*after write, iclass 14, count 0 2006.189.08:10:52.84#ibcon#*before return 0, iclass 14, count 0 2006.189.08:10:52.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:10:52.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:10:52.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:10:52.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:10:52.84$4f8m12a/ifd4f 2006.189.08:10:52.84$ifd4f/lo= 2006.189.08:10:52.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:10:52.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:10:52.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:10:52.85$ifd4f/patch= 2006.189.08:10:52.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:10:52.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:10:52.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:10:52.85$4f8m12a/"form=m,16.000,1:2 2006.189.08:10:52.85$4f8m12a/"tpicd 2006.189.08:10:52.85$4f8m12a/echo=off 2006.189.08:10:52.85$4f8m12a/xlog=off 2006.189.08:10:52.85:!2006.189.08:11:40 2006.189.08:11:19.14#trakl#Source acquired 2006.189.08:11:20.14#flagr#flagr/antenna,acquired 2006.189.08:11:40.01:preob 2006.189.08:11:41.14/onsource/TRACKING 2006.189.08:11:41.14:!2006.189.08:11:50 2006.189.08:11:50.00:data_valid=on 2006.189.08:11:50.00:midob 2006.189.08:11:50.14/onsource/TRACKING 2006.189.08:11:50.15/wx/25.50,1009.3,91 2006.189.08:11:50.19/cable/+6.4576E-03 2006.189.08:11:51.30/va/01,08,usb,yes,28,30 2006.189.08:11:51.30/va/02,07,usb,yes,28,29 2006.189.08:11:51.30/va/03,06,usb,yes,30,30 2006.189.08:11:51.30/va/04,07,usb,yes,29,31 2006.189.08:11:51.30/va/05,07,usb,yes,31,32 2006.189.08:11:51.30/va/06,06,usb,yes,30,29 2006.189.08:11:51.30/va/07,06,usb,yes,30,30 2006.189.08:11:51.30/va/08,06,usb,yes,32,32 2006.189.08:11:51.53/valo/01,532.99,yes,locked 2006.189.08:11:51.53/valo/02,572.99,yes,locked 2006.189.08:11:51.53/valo/03,672.99,yes,locked 2006.189.08:11:51.53/valo/04,832.99,yes,locked 2006.189.08:11:51.53/valo/05,652.99,yes,locked 2006.189.08:11:51.53/valo/06,772.99,yes,locked 2006.189.08:11:51.53/valo/07,832.99,yes,locked 2006.189.08:11:51.53/valo/08,852.99,yes,locked 2006.189.08:11:52.62/vb/01,04,usb,yes,28,27 2006.189.08:11:52.62/vb/02,04,usb,yes,30,31 2006.189.08:11:52.62/vb/03,04,usb,yes,27,30 2006.189.08:11:52.62/vb/04,04,usb,yes,27,27 2006.189.08:11:52.62/vb/05,04,usb,yes,26,30 2006.189.08:11:52.62/vb/06,04,usb,yes,27,29 2006.189.08:11:52.62/vb/07,04,usb,yes,29,29 2006.189.08:11:52.62/vb/08,04,usb,yes,27,30 2006.189.08:11:52.85/vblo/01,632.99,yes,locked 2006.189.08:11:52.85/vblo/02,640.99,yes,locked 2006.189.08:11:52.85/vblo/03,656.99,yes,locked 2006.189.08:11:52.85/vblo/04,712.99,yes,locked 2006.189.08:11:52.85/vblo/05,744.99,yes,locked 2006.189.08:11:52.85/vblo/06,752.99,yes,locked 2006.189.08:11:52.85/vblo/07,734.99,yes,locked 2006.189.08:11:52.85/vblo/08,744.99,yes,locked 2006.189.08:11:53.00/vabw/8 2006.189.08:11:53.15/vbbw/8 2006.189.08:11:53.24/xfe/off,on,15.0 2006.189.08:11:53.65/ifatt/23,28,28,28 2006.189.08:11:54.07/fmout-gps/S +2.97E-07 2006.189.08:11:54.16:!2006.189.08:13:40 2006.189.08:13:40.01:data_valid=off 2006.189.08:13:40.02:postob 2006.189.08:13:40.20/cable/+6.4579E-03 2006.189.08:13:40.21/wx/25.47,1009.3,91 2006.189.08:13:41.07/fmout-gps/S +2.98E-07 2006.189.08:13:41.08:scan_name=189-0815,k06189,60 2006.189.08:13:41.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.189.08:13:41.14#flagr#flagr/antenna,new-source 2006.189.08:13:42.14:checkk5 2006.189.08:13:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:13:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:13:43.30/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:13:43.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:13:44.05/chk_obsdata//k5ts1/T1890811??a.dat file size is correct (nominal:880MB, actual:872MB). 2006.189.08:13:44.42/chk_obsdata//k5ts2/T1890811??b.dat file size is correct (nominal:880MB, actual:872MB). 2006.189.08:13:44.79/chk_obsdata//k5ts3/T1890811??c.dat file size is correct (nominal:880MB, actual:872MB). 2006.189.08:13:45.17/chk_obsdata//k5ts4/T1890811??d.dat file size is correct (nominal:880MB, actual:872MB). 2006.189.08:13:45.87/k5log//k5ts1_log_newline 2006.189.08:13:46.58/k5log//k5ts2_log_newline 2006.189.08:13:47.28/k5log//k5ts3_log_newline 2006.189.08:13:47.97/k5log//k5ts4_log_newline 2006.189.08:13:48.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:13:48.00:4f8m12a=2 2006.189.08:13:48.00$4f8m12a/echo=on 2006.189.08:13:48.00$4f8m12a/pcalon 2006.189.08:13:48.00$pcalon/"no phase cal control is implemented here 2006.189.08:13:48.00$4f8m12a/"tpicd=stop 2006.189.08:13:48.00$4f8m12a/vc4f8 2006.189.08:13:48.00$vc4f8/valo=1,532.99 2006.189.08:13:48.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.08:13:48.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.08:13:48.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:48.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:48.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:48.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:48.00#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:13:48.00#ibcon#first serial, iclass 13, count 0 2006.189.08:13:48.00#ibcon#enter sib2, iclass 13, count 0 2006.189.08:13:48.00#ibcon#flushed, iclass 13, count 0 2006.189.08:13:48.00#ibcon#about to write, iclass 13, count 0 2006.189.08:13:48.00#ibcon#wrote, iclass 13, count 0 2006.189.08:13:48.00#ibcon#about to read 3, iclass 13, count 0 2006.189.08:13:48.01#ibcon#read 3, iclass 13, count 0 2006.189.08:13:48.01#ibcon#about to read 4, iclass 13, count 0 2006.189.08:13:48.01#ibcon#read 4, iclass 13, count 0 2006.189.08:13:48.01#ibcon#about to read 5, iclass 13, count 0 2006.189.08:13:48.01#ibcon#read 5, iclass 13, count 0 2006.189.08:13:48.01#ibcon#about to read 6, iclass 13, count 0 2006.189.08:13:48.01#ibcon#read 6, iclass 13, count 0 2006.189.08:13:48.01#ibcon#end of sib2, iclass 13, count 0 2006.189.08:13:48.01#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:13:48.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:13:48.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:13:48.01#ibcon#*before write, iclass 13, count 0 2006.189.08:13:48.01#ibcon#enter sib2, iclass 13, count 0 2006.189.08:13:48.01#ibcon#flushed, iclass 13, count 0 2006.189.08:13:48.01#ibcon#about to write, iclass 13, count 0 2006.189.08:13:48.01#ibcon#wrote, iclass 13, count 0 2006.189.08:13:48.01#ibcon#about to read 3, iclass 13, count 0 2006.189.08:13:48.06#ibcon#read 3, iclass 13, count 0 2006.189.08:13:48.06#ibcon#about to read 4, iclass 13, count 0 2006.189.08:13:48.06#ibcon#read 4, iclass 13, count 0 2006.189.08:13:48.06#ibcon#about to read 5, iclass 13, count 0 2006.189.08:13:48.06#ibcon#read 5, iclass 13, count 0 2006.189.08:13:48.06#ibcon#about to read 6, iclass 13, count 0 2006.189.08:13:48.06#ibcon#read 6, iclass 13, count 0 2006.189.08:13:48.06#ibcon#end of sib2, iclass 13, count 0 2006.189.08:13:48.06#ibcon#*after write, iclass 13, count 0 2006.189.08:13:48.06#ibcon#*before return 0, iclass 13, count 0 2006.189.08:13:48.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:48.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:48.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:13:48.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:13:48.06$vc4f8/va=1,8 2006.189.08:13:48.06#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.08:13:48.06#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.08:13:48.06#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:48.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:48.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:48.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:48.06#ibcon#enter wrdev, iclass 15, count 2 2006.189.08:13:48.06#ibcon#first serial, iclass 15, count 2 2006.189.08:13:48.06#ibcon#enter sib2, iclass 15, count 2 2006.189.08:13:48.06#ibcon#flushed, iclass 15, count 2 2006.189.08:13:48.06#ibcon#about to write, iclass 15, count 2 2006.189.08:13:48.06#ibcon#wrote, iclass 15, count 2 2006.189.08:13:48.06#ibcon#about to read 3, iclass 15, count 2 2006.189.08:13:48.08#ibcon#read 3, iclass 15, count 2 2006.189.08:13:48.08#ibcon#about to read 4, iclass 15, count 2 2006.189.08:13:48.08#ibcon#read 4, iclass 15, count 2 2006.189.08:13:48.08#ibcon#about to read 5, iclass 15, count 2 2006.189.08:13:48.08#ibcon#read 5, iclass 15, count 2 2006.189.08:13:48.08#ibcon#about to read 6, iclass 15, count 2 2006.189.08:13:48.08#ibcon#read 6, iclass 15, count 2 2006.189.08:13:48.08#ibcon#end of sib2, iclass 15, count 2 2006.189.08:13:48.08#ibcon#*mode == 0, iclass 15, count 2 2006.189.08:13:48.08#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.08:13:48.08#ibcon#[25=AT01-08\r\n] 2006.189.08:13:48.08#ibcon#*before write, iclass 15, count 2 2006.189.08:13:48.08#ibcon#enter sib2, iclass 15, count 2 2006.189.08:13:48.08#ibcon#flushed, iclass 15, count 2 2006.189.08:13:48.08#ibcon#about to write, iclass 15, count 2 2006.189.08:13:48.08#ibcon#wrote, iclass 15, count 2 2006.189.08:13:48.08#ibcon#about to read 3, iclass 15, count 2 2006.189.08:13:48.12#ibcon#read 3, iclass 15, count 2 2006.189.08:13:48.12#ibcon#about to read 4, iclass 15, count 2 2006.189.08:13:48.12#ibcon#read 4, iclass 15, count 2 2006.189.08:13:48.12#ibcon#about to read 5, iclass 15, count 2 2006.189.08:13:48.12#ibcon#read 5, iclass 15, count 2 2006.189.08:13:48.12#ibcon#about to read 6, iclass 15, count 2 2006.189.08:13:48.12#ibcon#read 6, iclass 15, count 2 2006.189.08:13:48.12#ibcon#end of sib2, iclass 15, count 2 2006.189.08:13:48.12#ibcon#*after write, iclass 15, count 2 2006.189.08:13:48.12#ibcon#*before return 0, iclass 15, count 2 2006.189.08:13:48.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:48.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:48.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.08:13:48.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:48.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:48.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:48.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:48.24#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:13:48.24#ibcon#first serial, iclass 15, count 0 2006.189.08:13:48.24#ibcon#enter sib2, iclass 15, count 0 2006.189.08:13:48.24#ibcon#flushed, iclass 15, count 0 2006.189.08:13:48.24#ibcon#about to write, iclass 15, count 0 2006.189.08:13:48.24#ibcon#wrote, iclass 15, count 0 2006.189.08:13:48.24#ibcon#about to read 3, iclass 15, count 0 2006.189.08:13:48.26#ibcon#read 3, iclass 15, count 0 2006.189.08:13:48.26#ibcon#about to read 4, iclass 15, count 0 2006.189.08:13:48.26#ibcon#read 4, iclass 15, count 0 2006.189.08:13:48.26#ibcon#about to read 5, iclass 15, count 0 2006.189.08:13:48.26#ibcon#read 5, iclass 15, count 0 2006.189.08:13:48.26#ibcon#about to read 6, iclass 15, count 0 2006.189.08:13:48.26#ibcon#read 6, iclass 15, count 0 2006.189.08:13:48.26#ibcon#end of sib2, iclass 15, count 0 2006.189.08:13:48.26#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:13:48.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:13:48.26#ibcon#[25=USB\r\n] 2006.189.08:13:48.26#ibcon#*before write, iclass 15, count 0 2006.189.08:13:48.26#ibcon#enter sib2, iclass 15, count 0 2006.189.08:13:48.26#ibcon#flushed, iclass 15, count 0 2006.189.08:13:48.26#ibcon#about to write, iclass 15, count 0 2006.189.08:13:48.26#ibcon#wrote, iclass 15, count 0 2006.189.08:13:48.26#ibcon#about to read 3, iclass 15, count 0 2006.189.08:13:48.29#ibcon#read 3, iclass 15, count 0 2006.189.08:13:48.29#ibcon#about to read 4, iclass 15, count 0 2006.189.08:13:48.29#ibcon#read 4, iclass 15, count 0 2006.189.08:13:48.29#ibcon#about to read 5, iclass 15, count 0 2006.189.08:13:48.29#ibcon#read 5, iclass 15, count 0 2006.189.08:13:48.29#ibcon#about to read 6, iclass 15, count 0 2006.189.08:13:48.29#ibcon#read 6, iclass 15, count 0 2006.189.08:13:48.29#ibcon#end of sib2, iclass 15, count 0 2006.189.08:13:48.29#ibcon#*after write, iclass 15, count 0 2006.189.08:13:48.29#ibcon#*before return 0, iclass 15, count 0 2006.189.08:13:48.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:48.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:48.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:13:48.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:13:48.29$vc4f8/valo=2,572.99 2006.189.08:13:48.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.08:13:48.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.08:13:48.29#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:48.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:48.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:48.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:48.29#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:13:48.29#ibcon#first serial, iclass 17, count 0 2006.189.08:13:48.29#ibcon#enter sib2, iclass 17, count 0 2006.189.08:13:48.29#ibcon#flushed, iclass 17, count 0 2006.189.08:13:48.29#ibcon#about to write, iclass 17, count 0 2006.189.08:13:48.29#ibcon#wrote, iclass 17, count 0 2006.189.08:13:48.29#ibcon#about to read 3, iclass 17, count 0 2006.189.08:13:48.31#ibcon#read 3, iclass 17, count 0 2006.189.08:13:48.31#ibcon#about to read 4, iclass 17, count 0 2006.189.08:13:48.31#ibcon#read 4, iclass 17, count 0 2006.189.08:13:48.31#ibcon#about to read 5, iclass 17, count 0 2006.189.08:13:48.31#ibcon#read 5, iclass 17, count 0 2006.189.08:13:48.31#ibcon#about to read 6, iclass 17, count 0 2006.189.08:13:48.31#ibcon#read 6, iclass 17, count 0 2006.189.08:13:48.31#ibcon#end of sib2, iclass 17, count 0 2006.189.08:13:48.31#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:13:48.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:13:48.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:13:48.31#ibcon#*before write, iclass 17, count 0 2006.189.08:13:48.31#ibcon#enter sib2, iclass 17, count 0 2006.189.08:13:48.31#ibcon#flushed, iclass 17, count 0 2006.189.08:13:48.31#ibcon#about to write, iclass 17, count 0 2006.189.08:13:48.31#ibcon#wrote, iclass 17, count 0 2006.189.08:13:48.31#ibcon#about to read 3, iclass 17, count 0 2006.189.08:13:48.35#ibcon#read 3, iclass 17, count 0 2006.189.08:13:48.35#ibcon#about to read 4, iclass 17, count 0 2006.189.08:13:48.35#ibcon#read 4, iclass 17, count 0 2006.189.08:13:48.35#ibcon#about to read 5, iclass 17, count 0 2006.189.08:13:48.35#ibcon#read 5, iclass 17, count 0 2006.189.08:13:48.35#ibcon#about to read 6, iclass 17, count 0 2006.189.08:13:48.35#ibcon#read 6, iclass 17, count 0 2006.189.08:13:48.35#ibcon#end of sib2, iclass 17, count 0 2006.189.08:13:48.35#ibcon#*after write, iclass 17, count 0 2006.189.08:13:48.35#ibcon#*before return 0, iclass 17, count 0 2006.189.08:13:48.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:48.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:48.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:13:48.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:13:48.36$vc4f8/va=2,7 2006.189.08:13:48.36#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.08:13:48.36#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.08:13:48.36#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:48.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:48.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:48.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:48.40#ibcon#enter wrdev, iclass 19, count 2 2006.189.08:13:48.40#ibcon#first serial, iclass 19, count 2 2006.189.08:13:48.40#ibcon#enter sib2, iclass 19, count 2 2006.189.08:13:48.40#ibcon#flushed, iclass 19, count 2 2006.189.08:13:48.40#ibcon#about to write, iclass 19, count 2 2006.189.08:13:48.40#ibcon#wrote, iclass 19, count 2 2006.189.08:13:48.40#ibcon#about to read 3, iclass 19, count 2 2006.189.08:13:48.42#ibcon#read 3, iclass 19, count 2 2006.189.08:13:48.42#ibcon#about to read 4, iclass 19, count 2 2006.189.08:13:48.42#ibcon#read 4, iclass 19, count 2 2006.189.08:13:48.42#ibcon#about to read 5, iclass 19, count 2 2006.189.08:13:48.42#ibcon#read 5, iclass 19, count 2 2006.189.08:13:48.42#ibcon#about to read 6, iclass 19, count 2 2006.189.08:13:48.42#ibcon#read 6, iclass 19, count 2 2006.189.08:13:48.42#ibcon#end of sib2, iclass 19, count 2 2006.189.08:13:48.42#ibcon#*mode == 0, iclass 19, count 2 2006.189.08:13:48.42#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.08:13:48.42#ibcon#[25=AT02-07\r\n] 2006.189.08:13:48.42#ibcon#*before write, iclass 19, count 2 2006.189.08:13:48.42#ibcon#enter sib2, iclass 19, count 2 2006.189.08:13:48.42#ibcon#flushed, iclass 19, count 2 2006.189.08:13:48.42#ibcon#about to write, iclass 19, count 2 2006.189.08:13:48.42#ibcon#wrote, iclass 19, count 2 2006.189.08:13:48.42#ibcon#about to read 3, iclass 19, count 2 2006.189.08:13:48.46#ibcon#read 3, iclass 19, count 2 2006.189.08:13:48.46#ibcon#about to read 4, iclass 19, count 2 2006.189.08:13:48.46#ibcon#read 4, iclass 19, count 2 2006.189.08:13:48.46#ibcon#about to read 5, iclass 19, count 2 2006.189.08:13:48.46#ibcon#read 5, iclass 19, count 2 2006.189.08:13:48.46#ibcon#about to read 6, iclass 19, count 2 2006.189.08:13:48.46#ibcon#read 6, iclass 19, count 2 2006.189.08:13:48.46#ibcon#end of sib2, iclass 19, count 2 2006.189.08:13:48.46#ibcon#*after write, iclass 19, count 2 2006.189.08:13:48.46#ibcon#*before return 0, iclass 19, count 2 2006.189.08:13:48.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:48.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:48.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.08:13:48.46#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:48.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:48.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:48.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:48.57#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:13:48.57#ibcon#first serial, iclass 19, count 0 2006.189.08:13:48.57#ibcon#enter sib2, iclass 19, count 0 2006.189.08:13:48.57#ibcon#flushed, iclass 19, count 0 2006.189.08:13:48.57#ibcon#about to write, iclass 19, count 0 2006.189.08:13:48.57#ibcon#wrote, iclass 19, count 0 2006.189.08:13:48.57#ibcon#about to read 3, iclass 19, count 0 2006.189.08:13:48.59#ibcon#read 3, iclass 19, count 0 2006.189.08:13:48.59#ibcon#about to read 4, iclass 19, count 0 2006.189.08:13:48.59#ibcon#read 4, iclass 19, count 0 2006.189.08:13:48.59#ibcon#about to read 5, iclass 19, count 0 2006.189.08:13:48.59#ibcon#read 5, iclass 19, count 0 2006.189.08:13:48.59#ibcon#about to read 6, iclass 19, count 0 2006.189.08:13:48.59#ibcon#read 6, iclass 19, count 0 2006.189.08:13:48.59#ibcon#end of sib2, iclass 19, count 0 2006.189.08:13:48.59#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:13:48.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:13:48.59#ibcon#[25=USB\r\n] 2006.189.08:13:48.59#ibcon#*before write, iclass 19, count 0 2006.189.08:13:48.59#ibcon#enter sib2, iclass 19, count 0 2006.189.08:13:48.59#ibcon#flushed, iclass 19, count 0 2006.189.08:13:48.59#ibcon#about to write, iclass 19, count 0 2006.189.08:13:48.59#ibcon#wrote, iclass 19, count 0 2006.189.08:13:48.59#ibcon#about to read 3, iclass 19, count 0 2006.189.08:13:48.62#ibcon#read 3, iclass 19, count 0 2006.189.08:13:48.62#ibcon#about to read 4, iclass 19, count 0 2006.189.08:13:48.62#ibcon#read 4, iclass 19, count 0 2006.189.08:13:48.62#ibcon#about to read 5, iclass 19, count 0 2006.189.08:13:48.62#ibcon#read 5, iclass 19, count 0 2006.189.08:13:48.62#ibcon#about to read 6, iclass 19, count 0 2006.189.08:13:48.62#ibcon#read 6, iclass 19, count 0 2006.189.08:13:48.62#ibcon#end of sib2, iclass 19, count 0 2006.189.08:13:48.62#ibcon#*after write, iclass 19, count 0 2006.189.08:13:48.62#ibcon#*before return 0, iclass 19, count 0 2006.189.08:13:48.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:48.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:48.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:13:48.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:13:48.62$vc4f8/valo=3,672.99 2006.189.08:13:48.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.08:13:48.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.08:13:48.62#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:48.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:48.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:48.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:48.62#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:13:48.62#ibcon#first serial, iclass 21, count 0 2006.189.08:13:48.62#ibcon#enter sib2, iclass 21, count 0 2006.189.08:13:48.62#ibcon#flushed, iclass 21, count 0 2006.189.08:13:48.62#ibcon#about to write, iclass 21, count 0 2006.189.08:13:48.62#ibcon#wrote, iclass 21, count 0 2006.189.08:13:48.62#ibcon#about to read 3, iclass 21, count 0 2006.189.08:13:48.64#ibcon#read 3, iclass 21, count 0 2006.189.08:13:48.64#ibcon#about to read 4, iclass 21, count 0 2006.189.08:13:48.64#ibcon#read 4, iclass 21, count 0 2006.189.08:13:48.64#ibcon#about to read 5, iclass 21, count 0 2006.189.08:13:48.64#ibcon#read 5, iclass 21, count 0 2006.189.08:13:48.64#ibcon#about to read 6, iclass 21, count 0 2006.189.08:13:48.64#ibcon#read 6, iclass 21, count 0 2006.189.08:13:48.64#ibcon#end of sib2, iclass 21, count 0 2006.189.08:13:48.64#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:13:48.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:13:48.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:13:48.64#ibcon#*before write, iclass 21, count 0 2006.189.08:13:48.64#ibcon#enter sib2, iclass 21, count 0 2006.189.08:13:48.64#ibcon#flushed, iclass 21, count 0 2006.189.08:13:48.64#ibcon#about to write, iclass 21, count 0 2006.189.08:13:48.64#ibcon#wrote, iclass 21, count 0 2006.189.08:13:48.64#ibcon#about to read 3, iclass 21, count 0 2006.189.08:13:48.68#ibcon#read 3, iclass 21, count 0 2006.189.08:13:48.68#ibcon#about to read 4, iclass 21, count 0 2006.189.08:13:48.68#ibcon#read 4, iclass 21, count 0 2006.189.08:13:48.68#ibcon#about to read 5, iclass 21, count 0 2006.189.08:13:48.68#ibcon#read 5, iclass 21, count 0 2006.189.08:13:48.68#ibcon#about to read 6, iclass 21, count 0 2006.189.08:13:48.68#ibcon#read 6, iclass 21, count 0 2006.189.08:13:48.68#ibcon#end of sib2, iclass 21, count 0 2006.189.08:13:48.68#ibcon#*after write, iclass 21, count 0 2006.189.08:13:48.68#ibcon#*before return 0, iclass 21, count 0 2006.189.08:13:48.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:48.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:48.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:13:48.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:13:48.69$vc4f8/va=3,6 2006.189.08:13:48.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.08:13:48.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.08:13:48.69#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:48.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:48.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:48.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:48.73#ibcon#enter wrdev, iclass 23, count 2 2006.189.08:13:48.73#ibcon#first serial, iclass 23, count 2 2006.189.08:13:48.73#ibcon#enter sib2, iclass 23, count 2 2006.189.08:13:48.73#ibcon#flushed, iclass 23, count 2 2006.189.08:13:48.73#ibcon#about to write, iclass 23, count 2 2006.189.08:13:48.73#ibcon#wrote, iclass 23, count 2 2006.189.08:13:48.73#ibcon#about to read 3, iclass 23, count 2 2006.189.08:13:48.75#ibcon#read 3, iclass 23, count 2 2006.189.08:13:48.75#ibcon#about to read 4, iclass 23, count 2 2006.189.08:13:48.75#ibcon#read 4, iclass 23, count 2 2006.189.08:13:48.75#ibcon#about to read 5, iclass 23, count 2 2006.189.08:13:48.75#ibcon#read 5, iclass 23, count 2 2006.189.08:13:48.75#ibcon#about to read 6, iclass 23, count 2 2006.189.08:13:48.75#ibcon#read 6, iclass 23, count 2 2006.189.08:13:48.75#ibcon#end of sib2, iclass 23, count 2 2006.189.08:13:48.75#ibcon#*mode == 0, iclass 23, count 2 2006.189.08:13:48.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.08:13:48.75#ibcon#[25=AT03-06\r\n] 2006.189.08:13:48.75#ibcon#*before write, iclass 23, count 2 2006.189.08:13:48.75#ibcon#enter sib2, iclass 23, count 2 2006.189.08:13:48.75#ibcon#flushed, iclass 23, count 2 2006.189.08:13:48.75#ibcon#about to write, iclass 23, count 2 2006.189.08:13:48.75#ibcon#wrote, iclass 23, count 2 2006.189.08:13:48.75#ibcon#about to read 3, iclass 23, count 2 2006.189.08:13:48.78#ibcon#read 3, iclass 23, count 2 2006.189.08:13:48.78#ibcon#about to read 4, iclass 23, count 2 2006.189.08:13:48.78#ibcon#read 4, iclass 23, count 2 2006.189.08:13:48.78#ibcon#about to read 5, iclass 23, count 2 2006.189.08:13:48.78#ibcon#read 5, iclass 23, count 2 2006.189.08:13:48.78#ibcon#about to read 6, iclass 23, count 2 2006.189.08:13:48.78#ibcon#read 6, iclass 23, count 2 2006.189.08:13:48.78#ibcon#end of sib2, iclass 23, count 2 2006.189.08:13:48.78#ibcon#*after write, iclass 23, count 2 2006.189.08:13:48.78#ibcon#*before return 0, iclass 23, count 2 2006.189.08:13:48.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:48.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:48.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.08:13:48.78#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:48.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:48.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:48.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:48.90#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:13:48.90#ibcon#first serial, iclass 23, count 0 2006.189.08:13:48.90#ibcon#enter sib2, iclass 23, count 0 2006.189.08:13:48.90#ibcon#flushed, iclass 23, count 0 2006.189.08:13:48.90#ibcon#about to write, iclass 23, count 0 2006.189.08:13:48.90#ibcon#wrote, iclass 23, count 0 2006.189.08:13:48.90#ibcon#about to read 3, iclass 23, count 0 2006.189.08:13:48.92#ibcon#read 3, iclass 23, count 0 2006.189.08:13:48.92#ibcon#about to read 4, iclass 23, count 0 2006.189.08:13:48.92#ibcon#read 4, iclass 23, count 0 2006.189.08:13:48.92#ibcon#about to read 5, iclass 23, count 0 2006.189.08:13:48.92#ibcon#read 5, iclass 23, count 0 2006.189.08:13:48.92#ibcon#about to read 6, iclass 23, count 0 2006.189.08:13:48.92#ibcon#read 6, iclass 23, count 0 2006.189.08:13:48.92#ibcon#end of sib2, iclass 23, count 0 2006.189.08:13:48.92#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:13:48.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:13:48.92#ibcon#[25=USB\r\n] 2006.189.08:13:48.92#ibcon#*before write, iclass 23, count 0 2006.189.08:13:48.92#ibcon#enter sib2, iclass 23, count 0 2006.189.08:13:48.92#ibcon#flushed, iclass 23, count 0 2006.189.08:13:48.92#ibcon#about to write, iclass 23, count 0 2006.189.08:13:48.92#ibcon#wrote, iclass 23, count 0 2006.189.08:13:48.92#ibcon#about to read 3, iclass 23, count 0 2006.189.08:13:48.95#ibcon#read 3, iclass 23, count 0 2006.189.08:13:48.95#ibcon#about to read 4, iclass 23, count 0 2006.189.08:13:48.95#ibcon#read 4, iclass 23, count 0 2006.189.08:13:48.95#ibcon#about to read 5, iclass 23, count 0 2006.189.08:13:48.95#ibcon#read 5, iclass 23, count 0 2006.189.08:13:48.95#ibcon#about to read 6, iclass 23, count 0 2006.189.08:13:48.95#ibcon#read 6, iclass 23, count 0 2006.189.08:13:48.95#ibcon#end of sib2, iclass 23, count 0 2006.189.08:13:48.95#ibcon#*after write, iclass 23, count 0 2006.189.08:13:48.95#ibcon#*before return 0, iclass 23, count 0 2006.189.08:13:48.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:48.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:48.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:13:48.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:13:48.95$vc4f8/valo=4,832.99 2006.189.08:13:48.95#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.08:13:48.95#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.08:13:48.95#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:48.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:48.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:48.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:48.95#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:13:48.95#ibcon#first serial, iclass 25, count 0 2006.189.08:13:48.95#ibcon#enter sib2, iclass 25, count 0 2006.189.08:13:48.95#ibcon#flushed, iclass 25, count 0 2006.189.08:13:48.95#ibcon#about to write, iclass 25, count 0 2006.189.08:13:48.95#ibcon#wrote, iclass 25, count 0 2006.189.08:13:48.95#ibcon#about to read 3, iclass 25, count 0 2006.189.08:13:48.97#ibcon#read 3, iclass 25, count 0 2006.189.08:13:48.97#ibcon#about to read 4, iclass 25, count 0 2006.189.08:13:48.97#ibcon#read 4, iclass 25, count 0 2006.189.08:13:48.97#ibcon#about to read 5, iclass 25, count 0 2006.189.08:13:48.97#ibcon#read 5, iclass 25, count 0 2006.189.08:13:48.97#ibcon#about to read 6, iclass 25, count 0 2006.189.08:13:48.97#ibcon#read 6, iclass 25, count 0 2006.189.08:13:48.97#ibcon#end of sib2, iclass 25, count 0 2006.189.08:13:48.97#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:13:48.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:13:48.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:13:48.97#ibcon#*before write, iclass 25, count 0 2006.189.08:13:48.97#ibcon#enter sib2, iclass 25, count 0 2006.189.08:13:48.97#ibcon#flushed, iclass 25, count 0 2006.189.08:13:48.97#ibcon#about to write, iclass 25, count 0 2006.189.08:13:48.97#ibcon#wrote, iclass 25, count 0 2006.189.08:13:48.97#ibcon#about to read 3, iclass 25, count 0 2006.189.08:13:49.01#ibcon#read 3, iclass 25, count 0 2006.189.08:13:49.01#ibcon#about to read 4, iclass 25, count 0 2006.189.08:13:49.01#ibcon#read 4, iclass 25, count 0 2006.189.08:13:49.01#ibcon#about to read 5, iclass 25, count 0 2006.189.08:13:49.01#ibcon#read 5, iclass 25, count 0 2006.189.08:13:49.01#ibcon#about to read 6, iclass 25, count 0 2006.189.08:13:49.01#ibcon#read 6, iclass 25, count 0 2006.189.08:13:49.01#ibcon#end of sib2, iclass 25, count 0 2006.189.08:13:49.01#ibcon#*after write, iclass 25, count 0 2006.189.08:13:49.01#ibcon#*before return 0, iclass 25, count 0 2006.189.08:13:49.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:49.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:49.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:13:49.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:13:49.01$vc4f8/va=4,7 2006.189.08:13:49.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.08:13:49.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.08:13:49.01#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:49.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:49.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:49.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:49.07#ibcon#enter wrdev, iclass 27, count 2 2006.189.08:13:49.07#ibcon#first serial, iclass 27, count 2 2006.189.08:13:49.07#ibcon#enter sib2, iclass 27, count 2 2006.189.08:13:49.07#ibcon#flushed, iclass 27, count 2 2006.189.08:13:49.07#ibcon#about to write, iclass 27, count 2 2006.189.08:13:49.07#ibcon#wrote, iclass 27, count 2 2006.189.08:13:49.07#ibcon#about to read 3, iclass 27, count 2 2006.189.08:13:49.09#ibcon#read 3, iclass 27, count 2 2006.189.08:13:49.09#ibcon#about to read 4, iclass 27, count 2 2006.189.08:13:49.09#ibcon#read 4, iclass 27, count 2 2006.189.08:13:49.09#ibcon#about to read 5, iclass 27, count 2 2006.189.08:13:49.09#ibcon#read 5, iclass 27, count 2 2006.189.08:13:49.09#ibcon#about to read 6, iclass 27, count 2 2006.189.08:13:49.09#ibcon#read 6, iclass 27, count 2 2006.189.08:13:49.09#ibcon#end of sib2, iclass 27, count 2 2006.189.08:13:49.09#ibcon#*mode == 0, iclass 27, count 2 2006.189.08:13:49.09#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.08:13:49.09#ibcon#[25=AT04-07\r\n] 2006.189.08:13:49.09#ibcon#*before write, iclass 27, count 2 2006.189.08:13:49.09#ibcon#enter sib2, iclass 27, count 2 2006.189.08:13:49.09#ibcon#flushed, iclass 27, count 2 2006.189.08:13:49.09#ibcon#about to write, iclass 27, count 2 2006.189.08:13:49.09#ibcon#wrote, iclass 27, count 2 2006.189.08:13:49.09#ibcon#about to read 3, iclass 27, count 2 2006.189.08:13:49.12#ibcon#read 3, iclass 27, count 2 2006.189.08:13:49.12#ibcon#about to read 4, iclass 27, count 2 2006.189.08:13:49.12#ibcon#read 4, iclass 27, count 2 2006.189.08:13:49.12#ibcon#about to read 5, iclass 27, count 2 2006.189.08:13:49.12#ibcon#read 5, iclass 27, count 2 2006.189.08:13:49.12#ibcon#about to read 6, iclass 27, count 2 2006.189.08:13:49.12#ibcon#read 6, iclass 27, count 2 2006.189.08:13:49.12#ibcon#end of sib2, iclass 27, count 2 2006.189.08:13:49.12#ibcon#*after write, iclass 27, count 2 2006.189.08:13:49.12#ibcon#*before return 0, iclass 27, count 2 2006.189.08:13:49.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:49.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:49.12#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.08:13:49.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:49.12#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:49.24#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:49.24#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:49.24#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:13:49.24#ibcon#first serial, iclass 27, count 0 2006.189.08:13:49.24#ibcon#enter sib2, iclass 27, count 0 2006.189.08:13:49.24#ibcon#flushed, iclass 27, count 0 2006.189.08:13:49.24#ibcon#about to write, iclass 27, count 0 2006.189.08:13:49.24#ibcon#wrote, iclass 27, count 0 2006.189.08:13:49.24#ibcon#about to read 3, iclass 27, count 0 2006.189.08:13:49.26#ibcon#read 3, iclass 27, count 0 2006.189.08:13:49.26#ibcon#about to read 4, iclass 27, count 0 2006.189.08:13:49.26#ibcon#read 4, iclass 27, count 0 2006.189.08:13:49.26#ibcon#about to read 5, iclass 27, count 0 2006.189.08:13:49.26#ibcon#read 5, iclass 27, count 0 2006.189.08:13:49.26#ibcon#about to read 6, iclass 27, count 0 2006.189.08:13:49.26#ibcon#read 6, iclass 27, count 0 2006.189.08:13:49.26#ibcon#end of sib2, iclass 27, count 0 2006.189.08:13:49.26#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:13:49.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:13:49.26#ibcon#[25=USB\r\n] 2006.189.08:13:49.26#ibcon#*before write, iclass 27, count 0 2006.189.08:13:49.26#ibcon#enter sib2, iclass 27, count 0 2006.189.08:13:49.26#ibcon#flushed, iclass 27, count 0 2006.189.08:13:49.26#ibcon#about to write, iclass 27, count 0 2006.189.08:13:49.26#ibcon#wrote, iclass 27, count 0 2006.189.08:13:49.26#ibcon#about to read 3, iclass 27, count 0 2006.189.08:13:49.29#ibcon#read 3, iclass 27, count 0 2006.189.08:13:49.29#ibcon#about to read 4, iclass 27, count 0 2006.189.08:13:49.29#ibcon#read 4, iclass 27, count 0 2006.189.08:13:49.29#ibcon#about to read 5, iclass 27, count 0 2006.189.08:13:49.29#ibcon#read 5, iclass 27, count 0 2006.189.08:13:49.29#ibcon#about to read 6, iclass 27, count 0 2006.189.08:13:49.29#ibcon#read 6, iclass 27, count 0 2006.189.08:13:49.29#ibcon#end of sib2, iclass 27, count 0 2006.189.08:13:49.29#ibcon#*after write, iclass 27, count 0 2006.189.08:13:49.29#ibcon#*before return 0, iclass 27, count 0 2006.189.08:13:49.29#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:49.29#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:49.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:13:49.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:13:49.29$vc4f8/valo=5,652.99 2006.189.08:13:49.29#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.08:13:49.29#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.08:13:49.29#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:49.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:49.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:49.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:49.29#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:13:49.29#ibcon#first serial, iclass 29, count 0 2006.189.08:13:49.29#ibcon#enter sib2, iclass 29, count 0 2006.189.08:13:49.29#ibcon#flushed, iclass 29, count 0 2006.189.08:13:49.29#ibcon#about to write, iclass 29, count 0 2006.189.08:13:49.29#ibcon#wrote, iclass 29, count 0 2006.189.08:13:49.29#ibcon#about to read 3, iclass 29, count 0 2006.189.08:13:49.31#ibcon#read 3, iclass 29, count 0 2006.189.08:13:49.31#ibcon#about to read 4, iclass 29, count 0 2006.189.08:13:49.31#ibcon#read 4, iclass 29, count 0 2006.189.08:13:49.31#ibcon#about to read 5, iclass 29, count 0 2006.189.08:13:49.31#ibcon#read 5, iclass 29, count 0 2006.189.08:13:49.31#ibcon#about to read 6, iclass 29, count 0 2006.189.08:13:49.31#ibcon#read 6, iclass 29, count 0 2006.189.08:13:49.31#ibcon#end of sib2, iclass 29, count 0 2006.189.08:13:49.31#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:13:49.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:13:49.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:13:49.31#ibcon#*before write, iclass 29, count 0 2006.189.08:13:49.31#ibcon#enter sib2, iclass 29, count 0 2006.189.08:13:49.31#ibcon#flushed, iclass 29, count 0 2006.189.08:13:49.31#ibcon#about to write, iclass 29, count 0 2006.189.08:13:49.31#ibcon#wrote, iclass 29, count 0 2006.189.08:13:49.31#ibcon#about to read 3, iclass 29, count 0 2006.189.08:13:49.35#ibcon#read 3, iclass 29, count 0 2006.189.08:13:49.35#ibcon#about to read 4, iclass 29, count 0 2006.189.08:13:49.35#ibcon#read 4, iclass 29, count 0 2006.189.08:13:49.35#ibcon#about to read 5, iclass 29, count 0 2006.189.08:13:49.35#ibcon#read 5, iclass 29, count 0 2006.189.08:13:49.35#ibcon#about to read 6, iclass 29, count 0 2006.189.08:13:49.35#ibcon#read 6, iclass 29, count 0 2006.189.08:13:49.35#ibcon#end of sib2, iclass 29, count 0 2006.189.08:13:49.35#ibcon#*after write, iclass 29, count 0 2006.189.08:13:49.35#ibcon#*before return 0, iclass 29, count 0 2006.189.08:13:49.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:49.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:49.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:13:49.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:13:49.35$vc4f8/va=5,7 2006.189.08:13:49.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.08:13:49.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.08:13:49.35#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:49.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:49.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:49.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:49.41#ibcon#enter wrdev, iclass 31, count 2 2006.189.08:13:49.41#ibcon#first serial, iclass 31, count 2 2006.189.08:13:49.41#ibcon#enter sib2, iclass 31, count 2 2006.189.08:13:49.41#ibcon#flushed, iclass 31, count 2 2006.189.08:13:49.41#ibcon#about to write, iclass 31, count 2 2006.189.08:13:49.41#ibcon#wrote, iclass 31, count 2 2006.189.08:13:49.41#ibcon#about to read 3, iclass 31, count 2 2006.189.08:13:49.43#ibcon#read 3, iclass 31, count 2 2006.189.08:13:49.43#ibcon#about to read 4, iclass 31, count 2 2006.189.08:13:49.43#ibcon#read 4, iclass 31, count 2 2006.189.08:13:49.43#ibcon#about to read 5, iclass 31, count 2 2006.189.08:13:49.43#ibcon#read 5, iclass 31, count 2 2006.189.08:13:49.43#ibcon#about to read 6, iclass 31, count 2 2006.189.08:13:49.43#ibcon#read 6, iclass 31, count 2 2006.189.08:13:49.43#ibcon#end of sib2, iclass 31, count 2 2006.189.08:13:49.43#ibcon#*mode == 0, iclass 31, count 2 2006.189.08:13:49.43#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.08:13:49.43#ibcon#[25=AT05-07\r\n] 2006.189.08:13:49.43#ibcon#*before write, iclass 31, count 2 2006.189.08:13:49.43#ibcon#enter sib2, iclass 31, count 2 2006.189.08:13:49.43#ibcon#flushed, iclass 31, count 2 2006.189.08:13:49.43#ibcon#about to write, iclass 31, count 2 2006.189.08:13:49.43#ibcon#wrote, iclass 31, count 2 2006.189.08:13:49.43#ibcon#about to read 3, iclass 31, count 2 2006.189.08:13:49.46#ibcon#read 3, iclass 31, count 2 2006.189.08:13:49.46#ibcon#about to read 4, iclass 31, count 2 2006.189.08:13:49.46#ibcon#read 4, iclass 31, count 2 2006.189.08:13:49.46#ibcon#about to read 5, iclass 31, count 2 2006.189.08:13:49.46#ibcon#read 5, iclass 31, count 2 2006.189.08:13:49.46#ibcon#about to read 6, iclass 31, count 2 2006.189.08:13:49.46#ibcon#read 6, iclass 31, count 2 2006.189.08:13:49.46#ibcon#end of sib2, iclass 31, count 2 2006.189.08:13:49.46#ibcon#*after write, iclass 31, count 2 2006.189.08:13:49.46#ibcon#*before return 0, iclass 31, count 2 2006.189.08:13:49.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:49.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:49.46#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.08:13:49.46#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:49.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:49.58#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:49.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:49.58#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:13:49.58#ibcon#first serial, iclass 31, count 0 2006.189.08:13:49.58#ibcon#enter sib2, iclass 31, count 0 2006.189.08:13:49.58#ibcon#flushed, iclass 31, count 0 2006.189.08:13:49.58#ibcon#about to write, iclass 31, count 0 2006.189.08:13:49.58#ibcon#wrote, iclass 31, count 0 2006.189.08:13:49.58#ibcon#about to read 3, iclass 31, count 0 2006.189.08:13:49.60#ibcon#read 3, iclass 31, count 0 2006.189.08:13:49.60#ibcon#about to read 4, iclass 31, count 0 2006.189.08:13:49.60#ibcon#read 4, iclass 31, count 0 2006.189.08:13:49.60#ibcon#about to read 5, iclass 31, count 0 2006.189.08:13:49.60#ibcon#read 5, iclass 31, count 0 2006.189.08:13:49.60#ibcon#about to read 6, iclass 31, count 0 2006.189.08:13:49.60#ibcon#read 6, iclass 31, count 0 2006.189.08:13:49.60#ibcon#end of sib2, iclass 31, count 0 2006.189.08:13:49.60#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:13:49.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:13:49.60#ibcon#[25=USB\r\n] 2006.189.08:13:49.60#ibcon#*before write, iclass 31, count 0 2006.189.08:13:49.60#ibcon#enter sib2, iclass 31, count 0 2006.189.08:13:49.60#ibcon#flushed, iclass 31, count 0 2006.189.08:13:49.60#ibcon#about to write, iclass 31, count 0 2006.189.08:13:49.60#ibcon#wrote, iclass 31, count 0 2006.189.08:13:49.60#ibcon#about to read 3, iclass 31, count 0 2006.189.08:13:49.63#ibcon#read 3, iclass 31, count 0 2006.189.08:13:49.63#ibcon#about to read 4, iclass 31, count 0 2006.189.08:13:49.63#ibcon#read 4, iclass 31, count 0 2006.189.08:13:49.63#ibcon#about to read 5, iclass 31, count 0 2006.189.08:13:49.63#ibcon#read 5, iclass 31, count 0 2006.189.08:13:49.63#ibcon#about to read 6, iclass 31, count 0 2006.189.08:13:49.63#ibcon#read 6, iclass 31, count 0 2006.189.08:13:49.63#ibcon#end of sib2, iclass 31, count 0 2006.189.08:13:49.63#ibcon#*after write, iclass 31, count 0 2006.189.08:13:49.63#ibcon#*before return 0, iclass 31, count 0 2006.189.08:13:49.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:49.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:49.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:13:49.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:13:49.63$vc4f8/valo=6,772.99 2006.189.08:13:49.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.08:13:49.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.08:13:49.63#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:49.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:49.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:49.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:49.63#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:13:49.63#ibcon#first serial, iclass 33, count 0 2006.189.08:13:49.63#ibcon#enter sib2, iclass 33, count 0 2006.189.08:13:49.63#ibcon#flushed, iclass 33, count 0 2006.189.08:13:49.63#ibcon#about to write, iclass 33, count 0 2006.189.08:13:49.63#ibcon#wrote, iclass 33, count 0 2006.189.08:13:49.63#ibcon#about to read 3, iclass 33, count 0 2006.189.08:13:49.65#ibcon#read 3, iclass 33, count 0 2006.189.08:13:49.65#ibcon#about to read 4, iclass 33, count 0 2006.189.08:13:49.65#ibcon#read 4, iclass 33, count 0 2006.189.08:13:49.65#ibcon#about to read 5, iclass 33, count 0 2006.189.08:13:49.65#ibcon#read 5, iclass 33, count 0 2006.189.08:13:49.65#ibcon#about to read 6, iclass 33, count 0 2006.189.08:13:49.65#ibcon#read 6, iclass 33, count 0 2006.189.08:13:49.65#ibcon#end of sib2, iclass 33, count 0 2006.189.08:13:49.65#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:13:49.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:13:49.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:13:49.65#ibcon#*before write, iclass 33, count 0 2006.189.08:13:49.65#ibcon#enter sib2, iclass 33, count 0 2006.189.08:13:49.65#ibcon#flushed, iclass 33, count 0 2006.189.08:13:49.65#ibcon#about to write, iclass 33, count 0 2006.189.08:13:49.65#ibcon#wrote, iclass 33, count 0 2006.189.08:13:49.65#ibcon#about to read 3, iclass 33, count 0 2006.189.08:13:49.69#ibcon#read 3, iclass 33, count 0 2006.189.08:13:49.69#ibcon#about to read 4, iclass 33, count 0 2006.189.08:13:49.69#ibcon#read 4, iclass 33, count 0 2006.189.08:13:49.69#ibcon#about to read 5, iclass 33, count 0 2006.189.08:13:49.69#ibcon#read 5, iclass 33, count 0 2006.189.08:13:49.69#ibcon#about to read 6, iclass 33, count 0 2006.189.08:13:49.69#ibcon#read 6, iclass 33, count 0 2006.189.08:13:49.69#ibcon#end of sib2, iclass 33, count 0 2006.189.08:13:49.69#ibcon#*after write, iclass 33, count 0 2006.189.08:13:49.69#ibcon#*before return 0, iclass 33, count 0 2006.189.08:13:49.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:49.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:49.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:13:49.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:13:49.69$vc4f8/va=6,6 2006.189.08:13:49.69#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.08:13:49.69#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.08:13:49.69#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:49.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:13:49.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:13:49.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:13:49.75#ibcon#enter wrdev, iclass 35, count 2 2006.189.08:13:49.75#ibcon#first serial, iclass 35, count 2 2006.189.08:13:49.75#ibcon#enter sib2, iclass 35, count 2 2006.189.08:13:49.75#ibcon#flushed, iclass 35, count 2 2006.189.08:13:49.75#ibcon#about to write, iclass 35, count 2 2006.189.08:13:49.75#ibcon#wrote, iclass 35, count 2 2006.189.08:13:49.75#ibcon#about to read 3, iclass 35, count 2 2006.189.08:13:49.77#ibcon#read 3, iclass 35, count 2 2006.189.08:13:49.77#ibcon#about to read 4, iclass 35, count 2 2006.189.08:13:49.77#ibcon#read 4, iclass 35, count 2 2006.189.08:13:49.77#ibcon#about to read 5, iclass 35, count 2 2006.189.08:13:49.77#ibcon#read 5, iclass 35, count 2 2006.189.08:13:49.77#ibcon#about to read 6, iclass 35, count 2 2006.189.08:13:49.77#ibcon#read 6, iclass 35, count 2 2006.189.08:13:49.77#ibcon#end of sib2, iclass 35, count 2 2006.189.08:13:49.77#ibcon#*mode == 0, iclass 35, count 2 2006.189.08:13:49.77#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.08:13:49.77#ibcon#[25=AT06-06\r\n] 2006.189.08:13:49.77#ibcon#*before write, iclass 35, count 2 2006.189.08:13:49.77#ibcon#enter sib2, iclass 35, count 2 2006.189.08:13:49.77#ibcon#flushed, iclass 35, count 2 2006.189.08:13:49.77#ibcon#about to write, iclass 35, count 2 2006.189.08:13:49.77#ibcon#wrote, iclass 35, count 2 2006.189.08:13:49.77#ibcon#about to read 3, iclass 35, count 2 2006.189.08:13:49.80#ibcon#read 3, iclass 35, count 2 2006.189.08:13:49.80#ibcon#about to read 4, iclass 35, count 2 2006.189.08:13:49.80#ibcon#read 4, iclass 35, count 2 2006.189.08:13:49.80#ibcon#about to read 5, iclass 35, count 2 2006.189.08:13:49.80#ibcon#read 5, iclass 35, count 2 2006.189.08:13:49.80#ibcon#about to read 6, iclass 35, count 2 2006.189.08:13:49.80#ibcon#read 6, iclass 35, count 2 2006.189.08:13:49.80#ibcon#end of sib2, iclass 35, count 2 2006.189.08:13:49.80#ibcon#*after write, iclass 35, count 2 2006.189.08:13:49.80#ibcon#*before return 0, iclass 35, count 2 2006.189.08:13:49.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:13:49.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:13:49.80#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.08:13:49.80#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:49.80#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:13:49.92#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:13:49.92#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:13:49.92#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:13:49.92#ibcon#first serial, iclass 35, count 0 2006.189.08:13:49.92#ibcon#enter sib2, iclass 35, count 0 2006.189.08:13:49.92#ibcon#flushed, iclass 35, count 0 2006.189.08:13:49.92#ibcon#about to write, iclass 35, count 0 2006.189.08:13:49.92#ibcon#wrote, iclass 35, count 0 2006.189.08:13:49.92#ibcon#about to read 3, iclass 35, count 0 2006.189.08:13:49.94#ibcon#read 3, iclass 35, count 0 2006.189.08:13:49.94#ibcon#about to read 4, iclass 35, count 0 2006.189.08:13:49.94#ibcon#read 4, iclass 35, count 0 2006.189.08:13:49.94#ibcon#about to read 5, iclass 35, count 0 2006.189.08:13:49.94#ibcon#read 5, iclass 35, count 0 2006.189.08:13:49.94#ibcon#about to read 6, iclass 35, count 0 2006.189.08:13:49.94#ibcon#read 6, iclass 35, count 0 2006.189.08:13:49.94#ibcon#end of sib2, iclass 35, count 0 2006.189.08:13:49.94#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:13:49.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:13:49.94#ibcon#[25=USB\r\n] 2006.189.08:13:49.94#ibcon#*before write, iclass 35, count 0 2006.189.08:13:49.94#ibcon#enter sib2, iclass 35, count 0 2006.189.08:13:49.94#ibcon#flushed, iclass 35, count 0 2006.189.08:13:49.94#ibcon#about to write, iclass 35, count 0 2006.189.08:13:49.94#ibcon#wrote, iclass 35, count 0 2006.189.08:13:49.94#ibcon#about to read 3, iclass 35, count 0 2006.189.08:13:49.97#ibcon#read 3, iclass 35, count 0 2006.189.08:13:49.97#ibcon#about to read 4, iclass 35, count 0 2006.189.08:13:49.97#ibcon#read 4, iclass 35, count 0 2006.189.08:13:49.97#ibcon#about to read 5, iclass 35, count 0 2006.189.08:13:49.97#ibcon#read 5, iclass 35, count 0 2006.189.08:13:49.97#ibcon#about to read 6, iclass 35, count 0 2006.189.08:13:49.97#ibcon#read 6, iclass 35, count 0 2006.189.08:13:49.97#ibcon#end of sib2, iclass 35, count 0 2006.189.08:13:49.97#ibcon#*after write, iclass 35, count 0 2006.189.08:13:49.97#ibcon#*before return 0, iclass 35, count 0 2006.189.08:13:49.97#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:13:49.97#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:13:49.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:13:49.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:13:49.97$vc4f8/valo=7,832.99 2006.189.08:13:49.97#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.08:13:49.97#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.08:13:49.97#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:49.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:13:49.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:13:49.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:13:49.97#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:13:49.97#ibcon#first serial, iclass 37, count 0 2006.189.08:13:49.97#ibcon#enter sib2, iclass 37, count 0 2006.189.08:13:49.97#ibcon#flushed, iclass 37, count 0 2006.189.08:13:49.97#ibcon#about to write, iclass 37, count 0 2006.189.08:13:49.97#ibcon#wrote, iclass 37, count 0 2006.189.08:13:49.97#ibcon#about to read 3, iclass 37, count 0 2006.189.08:13:49.99#ibcon#read 3, iclass 37, count 0 2006.189.08:13:49.99#ibcon#about to read 4, iclass 37, count 0 2006.189.08:13:49.99#ibcon#read 4, iclass 37, count 0 2006.189.08:13:49.99#ibcon#about to read 5, iclass 37, count 0 2006.189.08:13:49.99#ibcon#read 5, iclass 37, count 0 2006.189.08:13:49.99#ibcon#about to read 6, iclass 37, count 0 2006.189.08:13:49.99#ibcon#read 6, iclass 37, count 0 2006.189.08:13:49.99#ibcon#end of sib2, iclass 37, count 0 2006.189.08:13:49.99#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:13:49.99#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:13:49.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:13:49.99#ibcon#*before write, iclass 37, count 0 2006.189.08:13:49.99#ibcon#enter sib2, iclass 37, count 0 2006.189.08:13:49.99#ibcon#flushed, iclass 37, count 0 2006.189.08:13:49.99#ibcon#about to write, iclass 37, count 0 2006.189.08:13:49.99#ibcon#wrote, iclass 37, count 0 2006.189.08:13:49.99#ibcon#about to read 3, iclass 37, count 0 2006.189.08:13:50.03#ibcon#read 3, iclass 37, count 0 2006.189.08:13:50.03#ibcon#about to read 4, iclass 37, count 0 2006.189.08:13:50.03#ibcon#read 4, iclass 37, count 0 2006.189.08:13:50.03#ibcon#about to read 5, iclass 37, count 0 2006.189.08:13:50.03#ibcon#read 5, iclass 37, count 0 2006.189.08:13:50.03#ibcon#about to read 6, iclass 37, count 0 2006.189.08:13:50.03#ibcon#read 6, iclass 37, count 0 2006.189.08:13:50.03#ibcon#end of sib2, iclass 37, count 0 2006.189.08:13:50.03#ibcon#*after write, iclass 37, count 0 2006.189.08:13:50.03#ibcon#*before return 0, iclass 37, count 0 2006.189.08:13:50.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:13:50.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:13:50.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:13:50.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:13:50.03$vc4f8/va=7,6 2006.189.08:13:50.03#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.08:13:50.03#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.08:13:50.03#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:50.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:13:50.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:13:50.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:13:50.09#ibcon#enter wrdev, iclass 39, count 2 2006.189.08:13:50.09#ibcon#first serial, iclass 39, count 2 2006.189.08:13:50.09#ibcon#enter sib2, iclass 39, count 2 2006.189.08:13:50.09#ibcon#flushed, iclass 39, count 2 2006.189.08:13:50.09#ibcon#about to write, iclass 39, count 2 2006.189.08:13:50.09#ibcon#wrote, iclass 39, count 2 2006.189.08:13:50.09#ibcon#about to read 3, iclass 39, count 2 2006.189.08:13:50.11#ibcon#read 3, iclass 39, count 2 2006.189.08:13:50.11#ibcon#about to read 4, iclass 39, count 2 2006.189.08:13:50.11#ibcon#read 4, iclass 39, count 2 2006.189.08:13:50.11#ibcon#about to read 5, iclass 39, count 2 2006.189.08:13:50.11#ibcon#read 5, iclass 39, count 2 2006.189.08:13:50.11#ibcon#about to read 6, iclass 39, count 2 2006.189.08:13:50.11#ibcon#read 6, iclass 39, count 2 2006.189.08:13:50.11#ibcon#end of sib2, iclass 39, count 2 2006.189.08:13:50.11#ibcon#*mode == 0, iclass 39, count 2 2006.189.08:13:50.11#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.08:13:50.11#ibcon#[25=AT07-06\r\n] 2006.189.08:13:50.11#ibcon#*before write, iclass 39, count 2 2006.189.08:13:50.11#ibcon#enter sib2, iclass 39, count 2 2006.189.08:13:50.11#ibcon#flushed, iclass 39, count 2 2006.189.08:13:50.11#ibcon#about to write, iclass 39, count 2 2006.189.08:13:50.11#ibcon#wrote, iclass 39, count 2 2006.189.08:13:50.11#ibcon#about to read 3, iclass 39, count 2 2006.189.08:13:50.14#ibcon#read 3, iclass 39, count 2 2006.189.08:13:50.14#ibcon#about to read 4, iclass 39, count 2 2006.189.08:13:50.14#ibcon#read 4, iclass 39, count 2 2006.189.08:13:50.14#ibcon#about to read 5, iclass 39, count 2 2006.189.08:13:50.14#ibcon#read 5, iclass 39, count 2 2006.189.08:13:50.14#ibcon#about to read 6, iclass 39, count 2 2006.189.08:13:50.14#ibcon#read 6, iclass 39, count 2 2006.189.08:13:50.14#ibcon#end of sib2, iclass 39, count 2 2006.189.08:13:50.14#ibcon#*after write, iclass 39, count 2 2006.189.08:13:50.14#ibcon#*before return 0, iclass 39, count 2 2006.189.08:13:50.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:13:50.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:13:50.14#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.08:13:50.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:50.14#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:13:50.26#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:13:50.26#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:13:50.26#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:13:50.26#ibcon#first serial, iclass 39, count 0 2006.189.08:13:50.26#ibcon#enter sib2, iclass 39, count 0 2006.189.08:13:50.26#ibcon#flushed, iclass 39, count 0 2006.189.08:13:50.26#ibcon#about to write, iclass 39, count 0 2006.189.08:13:50.26#ibcon#wrote, iclass 39, count 0 2006.189.08:13:50.26#ibcon#about to read 3, iclass 39, count 0 2006.189.08:13:50.28#ibcon#read 3, iclass 39, count 0 2006.189.08:13:50.28#ibcon#about to read 4, iclass 39, count 0 2006.189.08:13:50.28#ibcon#read 4, iclass 39, count 0 2006.189.08:13:50.28#ibcon#about to read 5, iclass 39, count 0 2006.189.08:13:50.28#ibcon#read 5, iclass 39, count 0 2006.189.08:13:50.28#ibcon#about to read 6, iclass 39, count 0 2006.189.08:13:50.28#ibcon#read 6, iclass 39, count 0 2006.189.08:13:50.28#ibcon#end of sib2, iclass 39, count 0 2006.189.08:13:50.28#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:13:50.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:13:50.28#ibcon#[25=USB\r\n] 2006.189.08:13:50.28#ibcon#*before write, iclass 39, count 0 2006.189.08:13:50.28#ibcon#enter sib2, iclass 39, count 0 2006.189.08:13:50.28#ibcon#flushed, iclass 39, count 0 2006.189.08:13:50.28#ibcon#about to write, iclass 39, count 0 2006.189.08:13:50.28#ibcon#wrote, iclass 39, count 0 2006.189.08:13:50.28#ibcon#about to read 3, iclass 39, count 0 2006.189.08:13:50.31#ibcon#read 3, iclass 39, count 0 2006.189.08:13:50.31#ibcon#about to read 4, iclass 39, count 0 2006.189.08:13:50.31#ibcon#read 4, iclass 39, count 0 2006.189.08:13:50.31#ibcon#about to read 5, iclass 39, count 0 2006.189.08:13:50.31#ibcon#read 5, iclass 39, count 0 2006.189.08:13:50.31#ibcon#about to read 6, iclass 39, count 0 2006.189.08:13:50.31#ibcon#read 6, iclass 39, count 0 2006.189.08:13:50.31#ibcon#end of sib2, iclass 39, count 0 2006.189.08:13:50.31#ibcon#*after write, iclass 39, count 0 2006.189.08:13:50.31#ibcon#*before return 0, iclass 39, count 0 2006.189.08:13:50.31#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:13:50.31#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:13:50.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:13:50.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:13:50.31$vc4f8/valo=8,852.99 2006.189.08:13:50.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.08:13:50.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.08:13:50.31#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:50.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:13:50.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:13:50.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:13:50.31#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:13:50.31#ibcon#first serial, iclass 3, count 0 2006.189.08:13:50.31#ibcon#enter sib2, iclass 3, count 0 2006.189.08:13:50.31#ibcon#flushed, iclass 3, count 0 2006.189.08:13:50.31#ibcon#about to write, iclass 3, count 0 2006.189.08:13:50.31#ibcon#wrote, iclass 3, count 0 2006.189.08:13:50.31#ibcon#about to read 3, iclass 3, count 0 2006.189.08:13:50.33#ibcon#read 3, iclass 3, count 0 2006.189.08:13:50.33#ibcon#about to read 4, iclass 3, count 0 2006.189.08:13:50.33#ibcon#read 4, iclass 3, count 0 2006.189.08:13:50.33#ibcon#about to read 5, iclass 3, count 0 2006.189.08:13:50.33#ibcon#read 5, iclass 3, count 0 2006.189.08:13:50.33#ibcon#about to read 6, iclass 3, count 0 2006.189.08:13:50.33#ibcon#read 6, iclass 3, count 0 2006.189.08:13:50.33#ibcon#end of sib2, iclass 3, count 0 2006.189.08:13:50.33#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:13:50.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:13:50.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:13:50.33#ibcon#*before write, iclass 3, count 0 2006.189.08:13:50.33#ibcon#enter sib2, iclass 3, count 0 2006.189.08:13:50.33#ibcon#flushed, iclass 3, count 0 2006.189.08:13:50.33#ibcon#about to write, iclass 3, count 0 2006.189.08:13:50.33#ibcon#wrote, iclass 3, count 0 2006.189.08:13:50.33#ibcon#about to read 3, iclass 3, count 0 2006.189.08:13:50.37#ibcon#read 3, iclass 3, count 0 2006.189.08:13:50.37#ibcon#about to read 4, iclass 3, count 0 2006.189.08:13:50.37#ibcon#read 4, iclass 3, count 0 2006.189.08:13:50.37#ibcon#about to read 5, iclass 3, count 0 2006.189.08:13:50.37#ibcon#read 5, iclass 3, count 0 2006.189.08:13:50.37#ibcon#about to read 6, iclass 3, count 0 2006.189.08:13:50.37#ibcon#read 6, iclass 3, count 0 2006.189.08:13:50.37#ibcon#end of sib2, iclass 3, count 0 2006.189.08:13:50.37#ibcon#*after write, iclass 3, count 0 2006.189.08:13:50.37#ibcon#*before return 0, iclass 3, count 0 2006.189.08:13:50.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:13:50.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:13:50.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:13:50.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:13:50.37$vc4f8/va=8,6 2006.189.08:13:50.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.08:13:50.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.08:13:50.37#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:50.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:13:50.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:13:50.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:13:50.43#ibcon#enter wrdev, iclass 5, count 2 2006.189.08:13:50.43#ibcon#first serial, iclass 5, count 2 2006.189.08:13:50.43#ibcon#enter sib2, iclass 5, count 2 2006.189.08:13:50.43#ibcon#flushed, iclass 5, count 2 2006.189.08:13:50.43#ibcon#about to write, iclass 5, count 2 2006.189.08:13:50.43#ibcon#wrote, iclass 5, count 2 2006.189.08:13:50.43#ibcon#about to read 3, iclass 5, count 2 2006.189.08:13:50.45#ibcon#read 3, iclass 5, count 2 2006.189.08:13:50.45#ibcon#about to read 4, iclass 5, count 2 2006.189.08:13:50.45#ibcon#read 4, iclass 5, count 2 2006.189.08:13:50.45#ibcon#about to read 5, iclass 5, count 2 2006.189.08:13:50.45#ibcon#read 5, iclass 5, count 2 2006.189.08:13:50.45#ibcon#about to read 6, iclass 5, count 2 2006.189.08:13:50.45#ibcon#read 6, iclass 5, count 2 2006.189.08:13:50.45#ibcon#end of sib2, iclass 5, count 2 2006.189.08:13:50.45#ibcon#*mode == 0, iclass 5, count 2 2006.189.08:13:50.45#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.08:13:50.45#ibcon#[25=AT08-06\r\n] 2006.189.08:13:50.45#ibcon#*before write, iclass 5, count 2 2006.189.08:13:50.45#ibcon#enter sib2, iclass 5, count 2 2006.189.08:13:50.45#ibcon#flushed, iclass 5, count 2 2006.189.08:13:50.45#ibcon#about to write, iclass 5, count 2 2006.189.08:13:50.45#ibcon#wrote, iclass 5, count 2 2006.189.08:13:50.45#ibcon#about to read 3, iclass 5, count 2 2006.189.08:13:50.48#ibcon#read 3, iclass 5, count 2 2006.189.08:13:50.48#ibcon#about to read 4, iclass 5, count 2 2006.189.08:13:50.48#ibcon#read 4, iclass 5, count 2 2006.189.08:13:50.48#ibcon#about to read 5, iclass 5, count 2 2006.189.08:13:50.48#ibcon#read 5, iclass 5, count 2 2006.189.08:13:50.48#ibcon#about to read 6, iclass 5, count 2 2006.189.08:13:50.48#ibcon#read 6, iclass 5, count 2 2006.189.08:13:50.48#ibcon#end of sib2, iclass 5, count 2 2006.189.08:13:50.48#ibcon#*after write, iclass 5, count 2 2006.189.08:13:50.48#ibcon#*before return 0, iclass 5, count 2 2006.189.08:13:50.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:13:50.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:13:50.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.08:13:50.48#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:50.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:13:50.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:13:50.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:13:50.60#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:13:50.60#ibcon#first serial, iclass 5, count 0 2006.189.08:13:50.60#ibcon#enter sib2, iclass 5, count 0 2006.189.08:13:50.60#ibcon#flushed, iclass 5, count 0 2006.189.08:13:50.60#ibcon#about to write, iclass 5, count 0 2006.189.08:13:50.60#ibcon#wrote, iclass 5, count 0 2006.189.08:13:50.60#ibcon#about to read 3, iclass 5, count 0 2006.189.08:13:50.62#ibcon#read 3, iclass 5, count 0 2006.189.08:13:50.62#ibcon#about to read 4, iclass 5, count 0 2006.189.08:13:50.62#ibcon#read 4, iclass 5, count 0 2006.189.08:13:50.62#ibcon#about to read 5, iclass 5, count 0 2006.189.08:13:50.62#ibcon#read 5, iclass 5, count 0 2006.189.08:13:50.62#ibcon#about to read 6, iclass 5, count 0 2006.189.08:13:50.62#ibcon#read 6, iclass 5, count 0 2006.189.08:13:50.62#ibcon#end of sib2, iclass 5, count 0 2006.189.08:13:50.62#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:13:50.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:13:50.62#ibcon#[25=USB\r\n] 2006.189.08:13:50.62#ibcon#*before write, iclass 5, count 0 2006.189.08:13:50.62#ibcon#enter sib2, iclass 5, count 0 2006.189.08:13:50.62#ibcon#flushed, iclass 5, count 0 2006.189.08:13:50.62#ibcon#about to write, iclass 5, count 0 2006.189.08:13:50.62#ibcon#wrote, iclass 5, count 0 2006.189.08:13:50.62#ibcon#about to read 3, iclass 5, count 0 2006.189.08:13:50.65#ibcon#read 3, iclass 5, count 0 2006.189.08:13:50.65#ibcon#about to read 4, iclass 5, count 0 2006.189.08:13:50.65#ibcon#read 4, iclass 5, count 0 2006.189.08:13:50.65#ibcon#about to read 5, iclass 5, count 0 2006.189.08:13:50.65#ibcon#read 5, iclass 5, count 0 2006.189.08:13:50.65#ibcon#about to read 6, iclass 5, count 0 2006.189.08:13:50.65#ibcon#read 6, iclass 5, count 0 2006.189.08:13:50.65#ibcon#end of sib2, iclass 5, count 0 2006.189.08:13:50.65#ibcon#*after write, iclass 5, count 0 2006.189.08:13:50.65#ibcon#*before return 0, iclass 5, count 0 2006.189.08:13:50.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:13:50.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:13:50.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:13:50.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:13:50.65$vc4f8/vblo=1,632.99 2006.189.08:13:50.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.08:13:50.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.08:13:50.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:50.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:13:50.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:13:50.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:13:50.65#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:13:50.65#ibcon#first serial, iclass 7, count 0 2006.189.08:13:50.65#ibcon#enter sib2, iclass 7, count 0 2006.189.08:13:50.65#ibcon#flushed, iclass 7, count 0 2006.189.08:13:50.65#ibcon#about to write, iclass 7, count 0 2006.189.08:13:50.65#ibcon#wrote, iclass 7, count 0 2006.189.08:13:50.65#ibcon#about to read 3, iclass 7, count 0 2006.189.08:13:50.67#ibcon#read 3, iclass 7, count 0 2006.189.08:13:50.67#ibcon#about to read 4, iclass 7, count 0 2006.189.08:13:50.67#ibcon#read 4, iclass 7, count 0 2006.189.08:13:50.67#ibcon#about to read 5, iclass 7, count 0 2006.189.08:13:50.67#ibcon#read 5, iclass 7, count 0 2006.189.08:13:50.67#ibcon#about to read 6, iclass 7, count 0 2006.189.08:13:50.67#ibcon#read 6, iclass 7, count 0 2006.189.08:13:50.67#ibcon#end of sib2, iclass 7, count 0 2006.189.08:13:50.67#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:13:50.67#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:13:50.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:13:50.67#ibcon#*before write, iclass 7, count 0 2006.189.08:13:50.67#ibcon#enter sib2, iclass 7, count 0 2006.189.08:13:50.67#ibcon#flushed, iclass 7, count 0 2006.189.08:13:50.67#ibcon#about to write, iclass 7, count 0 2006.189.08:13:50.67#ibcon#wrote, iclass 7, count 0 2006.189.08:13:50.67#ibcon#about to read 3, iclass 7, count 0 2006.189.08:13:50.71#ibcon#read 3, iclass 7, count 0 2006.189.08:13:50.71#ibcon#about to read 4, iclass 7, count 0 2006.189.08:13:50.71#ibcon#read 4, iclass 7, count 0 2006.189.08:13:50.71#ibcon#about to read 5, iclass 7, count 0 2006.189.08:13:50.71#ibcon#read 5, iclass 7, count 0 2006.189.08:13:50.71#ibcon#about to read 6, iclass 7, count 0 2006.189.08:13:50.71#ibcon#read 6, iclass 7, count 0 2006.189.08:13:50.71#ibcon#end of sib2, iclass 7, count 0 2006.189.08:13:50.71#ibcon#*after write, iclass 7, count 0 2006.189.08:13:50.71#ibcon#*before return 0, iclass 7, count 0 2006.189.08:13:50.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:13:50.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:13:50.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:13:50.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:13:50.71$vc4f8/vb=1,4 2006.189.08:13:50.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.08:13:50.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.08:13:50.71#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:50.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:13:50.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:13:50.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:13:50.71#ibcon#enter wrdev, iclass 11, count 2 2006.189.08:13:50.71#ibcon#first serial, iclass 11, count 2 2006.189.08:13:50.71#ibcon#enter sib2, iclass 11, count 2 2006.189.08:13:50.71#ibcon#flushed, iclass 11, count 2 2006.189.08:13:50.71#ibcon#about to write, iclass 11, count 2 2006.189.08:13:50.71#ibcon#wrote, iclass 11, count 2 2006.189.08:13:50.71#ibcon#about to read 3, iclass 11, count 2 2006.189.08:13:50.73#ibcon#read 3, iclass 11, count 2 2006.189.08:13:50.73#ibcon#about to read 4, iclass 11, count 2 2006.189.08:13:50.73#ibcon#read 4, iclass 11, count 2 2006.189.08:13:50.73#ibcon#about to read 5, iclass 11, count 2 2006.189.08:13:50.73#ibcon#read 5, iclass 11, count 2 2006.189.08:13:50.73#ibcon#about to read 6, iclass 11, count 2 2006.189.08:13:50.73#ibcon#read 6, iclass 11, count 2 2006.189.08:13:50.73#ibcon#end of sib2, iclass 11, count 2 2006.189.08:13:50.73#ibcon#*mode == 0, iclass 11, count 2 2006.189.08:13:50.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.08:13:50.73#ibcon#[27=AT01-04\r\n] 2006.189.08:13:50.73#ibcon#*before write, iclass 11, count 2 2006.189.08:13:50.73#ibcon#enter sib2, iclass 11, count 2 2006.189.08:13:50.73#ibcon#flushed, iclass 11, count 2 2006.189.08:13:50.73#ibcon#about to write, iclass 11, count 2 2006.189.08:13:50.73#ibcon#wrote, iclass 11, count 2 2006.189.08:13:50.73#ibcon#about to read 3, iclass 11, count 2 2006.189.08:13:50.76#ibcon#read 3, iclass 11, count 2 2006.189.08:13:50.76#ibcon#about to read 4, iclass 11, count 2 2006.189.08:13:50.76#ibcon#read 4, iclass 11, count 2 2006.189.08:13:50.76#ibcon#about to read 5, iclass 11, count 2 2006.189.08:13:50.76#ibcon#read 5, iclass 11, count 2 2006.189.08:13:50.76#ibcon#about to read 6, iclass 11, count 2 2006.189.08:13:50.76#ibcon#read 6, iclass 11, count 2 2006.189.08:13:50.76#ibcon#end of sib2, iclass 11, count 2 2006.189.08:13:50.76#ibcon#*after write, iclass 11, count 2 2006.189.08:13:50.76#ibcon#*before return 0, iclass 11, count 2 2006.189.08:13:50.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:13:50.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:13:50.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.08:13:50.76#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:50.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:13:50.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:13:50.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:13:50.88#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:13:50.88#ibcon#first serial, iclass 11, count 0 2006.189.08:13:50.88#ibcon#enter sib2, iclass 11, count 0 2006.189.08:13:50.88#ibcon#flushed, iclass 11, count 0 2006.189.08:13:50.88#ibcon#about to write, iclass 11, count 0 2006.189.08:13:50.88#ibcon#wrote, iclass 11, count 0 2006.189.08:13:50.88#ibcon#about to read 3, iclass 11, count 0 2006.189.08:13:50.90#ibcon#read 3, iclass 11, count 0 2006.189.08:13:50.90#ibcon#about to read 4, iclass 11, count 0 2006.189.08:13:50.90#ibcon#read 4, iclass 11, count 0 2006.189.08:13:50.90#ibcon#about to read 5, iclass 11, count 0 2006.189.08:13:50.90#ibcon#read 5, iclass 11, count 0 2006.189.08:13:50.90#ibcon#about to read 6, iclass 11, count 0 2006.189.08:13:50.90#ibcon#read 6, iclass 11, count 0 2006.189.08:13:50.90#ibcon#end of sib2, iclass 11, count 0 2006.189.08:13:50.90#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:13:50.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:13:50.90#ibcon#[27=USB\r\n] 2006.189.08:13:50.90#ibcon#*before write, iclass 11, count 0 2006.189.08:13:50.90#ibcon#enter sib2, iclass 11, count 0 2006.189.08:13:50.90#ibcon#flushed, iclass 11, count 0 2006.189.08:13:50.90#ibcon#about to write, iclass 11, count 0 2006.189.08:13:50.90#ibcon#wrote, iclass 11, count 0 2006.189.08:13:50.90#ibcon#about to read 3, iclass 11, count 0 2006.189.08:13:50.93#ibcon#read 3, iclass 11, count 0 2006.189.08:13:50.93#ibcon#about to read 4, iclass 11, count 0 2006.189.08:13:50.93#ibcon#read 4, iclass 11, count 0 2006.189.08:13:50.93#ibcon#about to read 5, iclass 11, count 0 2006.189.08:13:50.93#ibcon#read 5, iclass 11, count 0 2006.189.08:13:50.93#ibcon#about to read 6, iclass 11, count 0 2006.189.08:13:50.93#ibcon#read 6, iclass 11, count 0 2006.189.08:13:50.93#ibcon#end of sib2, iclass 11, count 0 2006.189.08:13:50.93#ibcon#*after write, iclass 11, count 0 2006.189.08:13:50.93#ibcon#*before return 0, iclass 11, count 0 2006.189.08:13:50.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:13:50.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:13:50.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:13:50.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:13:50.93$vc4f8/vblo=2,640.99 2006.189.08:13:50.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.08:13:50.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.08:13:50.93#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:50.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:50.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:50.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:50.93#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:13:50.93#ibcon#first serial, iclass 13, count 0 2006.189.08:13:50.93#ibcon#enter sib2, iclass 13, count 0 2006.189.08:13:50.93#ibcon#flushed, iclass 13, count 0 2006.189.08:13:50.93#ibcon#about to write, iclass 13, count 0 2006.189.08:13:50.93#ibcon#wrote, iclass 13, count 0 2006.189.08:13:50.93#ibcon#about to read 3, iclass 13, count 0 2006.189.08:13:50.95#ibcon#read 3, iclass 13, count 0 2006.189.08:13:50.95#ibcon#about to read 4, iclass 13, count 0 2006.189.08:13:50.95#ibcon#read 4, iclass 13, count 0 2006.189.08:13:50.95#ibcon#about to read 5, iclass 13, count 0 2006.189.08:13:50.95#ibcon#read 5, iclass 13, count 0 2006.189.08:13:50.95#ibcon#about to read 6, iclass 13, count 0 2006.189.08:13:50.95#ibcon#read 6, iclass 13, count 0 2006.189.08:13:50.95#ibcon#end of sib2, iclass 13, count 0 2006.189.08:13:50.95#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:13:50.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:13:50.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:13:50.95#ibcon#*before write, iclass 13, count 0 2006.189.08:13:50.95#ibcon#enter sib2, iclass 13, count 0 2006.189.08:13:50.95#ibcon#flushed, iclass 13, count 0 2006.189.08:13:50.95#ibcon#about to write, iclass 13, count 0 2006.189.08:13:50.95#ibcon#wrote, iclass 13, count 0 2006.189.08:13:50.95#ibcon#about to read 3, iclass 13, count 0 2006.189.08:13:50.99#ibcon#read 3, iclass 13, count 0 2006.189.08:13:50.99#ibcon#about to read 4, iclass 13, count 0 2006.189.08:13:50.99#ibcon#read 4, iclass 13, count 0 2006.189.08:13:50.99#ibcon#about to read 5, iclass 13, count 0 2006.189.08:13:50.99#ibcon#read 5, iclass 13, count 0 2006.189.08:13:50.99#ibcon#about to read 6, iclass 13, count 0 2006.189.08:13:50.99#ibcon#read 6, iclass 13, count 0 2006.189.08:13:50.99#ibcon#end of sib2, iclass 13, count 0 2006.189.08:13:50.99#ibcon#*after write, iclass 13, count 0 2006.189.08:13:50.99#ibcon#*before return 0, iclass 13, count 0 2006.189.08:13:50.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:50.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:13:50.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:13:50.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:13:50.99$vc4f8/vb=2,4 2006.189.08:13:50.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.08:13:50.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.08:13:50.99#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:50.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:51.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:51.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:51.05#ibcon#enter wrdev, iclass 15, count 2 2006.189.08:13:51.05#ibcon#first serial, iclass 15, count 2 2006.189.08:13:51.05#ibcon#enter sib2, iclass 15, count 2 2006.189.08:13:51.05#ibcon#flushed, iclass 15, count 2 2006.189.08:13:51.05#ibcon#about to write, iclass 15, count 2 2006.189.08:13:51.05#ibcon#wrote, iclass 15, count 2 2006.189.08:13:51.05#ibcon#about to read 3, iclass 15, count 2 2006.189.08:13:51.07#ibcon#read 3, iclass 15, count 2 2006.189.08:13:51.07#ibcon#about to read 4, iclass 15, count 2 2006.189.08:13:51.07#ibcon#read 4, iclass 15, count 2 2006.189.08:13:51.07#ibcon#about to read 5, iclass 15, count 2 2006.189.08:13:51.07#ibcon#read 5, iclass 15, count 2 2006.189.08:13:51.07#ibcon#about to read 6, iclass 15, count 2 2006.189.08:13:51.07#ibcon#read 6, iclass 15, count 2 2006.189.08:13:51.07#ibcon#end of sib2, iclass 15, count 2 2006.189.08:13:51.07#ibcon#*mode == 0, iclass 15, count 2 2006.189.08:13:51.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.08:13:51.07#ibcon#[27=AT02-04\r\n] 2006.189.08:13:51.07#ibcon#*before write, iclass 15, count 2 2006.189.08:13:51.07#ibcon#enter sib2, iclass 15, count 2 2006.189.08:13:51.07#ibcon#flushed, iclass 15, count 2 2006.189.08:13:51.07#ibcon#about to write, iclass 15, count 2 2006.189.08:13:51.07#ibcon#wrote, iclass 15, count 2 2006.189.08:13:51.07#ibcon#about to read 3, iclass 15, count 2 2006.189.08:13:51.10#ibcon#read 3, iclass 15, count 2 2006.189.08:13:51.10#ibcon#about to read 4, iclass 15, count 2 2006.189.08:13:51.10#ibcon#read 4, iclass 15, count 2 2006.189.08:13:51.10#ibcon#about to read 5, iclass 15, count 2 2006.189.08:13:51.10#ibcon#read 5, iclass 15, count 2 2006.189.08:13:51.10#ibcon#about to read 6, iclass 15, count 2 2006.189.08:13:51.10#ibcon#read 6, iclass 15, count 2 2006.189.08:13:51.10#ibcon#end of sib2, iclass 15, count 2 2006.189.08:13:51.10#ibcon#*after write, iclass 15, count 2 2006.189.08:13:51.10#ibcon#*before return 0, iclass 15, count 2 2006.189.08:13:51.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:51.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:13:51.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.08:13:51.10#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:51.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:51.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:51.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:51.22#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:13:51.22#ibcon#first serial, iclass 15, count 0 2006.189.08:13:51.22#ibcon#enter sib2, iclass 15, count 0 2006.189.08:13:51.22#ibcon#flushed, iclass 15, count 0 2006.189.08:13:51.22#ibcon#about to write, iclass 15, count 0 2006.189.08:13:51.22#ibcon#wrote, iclass 15, count 0 2006.189.08:13:51.22#ibcon#about to read 3, iclass 15, count 0 2006.189.08:13:51.24#ibcon#read 3, iclass 15, count 0 2006.189.08:13:51.24#ibcon#about to read 4, iclass 15, count 0 2006.189.08:13:51.24#ibcon#read 4, iclass 15, count 0 2006.189.08:13:51.24#ibcon#about to read 5, iclass 15, count 0 2006.189.08:13:51.24#ibcon#read 5, iclass 15, count 0 2006.189.08:13:51.24#ibcon#about to read 6, iclass 15, count 0 2006.189.08:13:51.24#ibcon#read 6, iclass 15, count 0 2006.189.08:13:51.24#ibcon#end of sib2, iclass 15, count 0 2006.189.08:13:51.24#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:13:51.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:13:51.24#ibcon#[27=USB\r\n] 2006.189.08:13:51.24#ibcon#*before write, iclass 15, count 0 2006.189.08:13:51.24#ibcon#enter sib2, iclass 15, count 0 2006.189.08:13:51.24#ibcon#flushed, iclass 15, count 0 2006.189.08:13:51.24#ibcon#about to write, iclass 15, count 0 2006.189.08:13:51.24#ibcon#wrote, iclass 15, count 0 2006.189.08:13:51.24#ibcon#about to read 3, iclass 15, count 0 2006.189.08:13:51.27#ibcon#read 3, iclass 15, count 0 2006.189.08:13:51.27#ibcon#about to read 4, iclass 15, count 0 2006.189.08:13:51.27#ibcon#read 4, iclass 15, count 0 2006.189.08:13:51.27#ibcon#about to read 5, iclass 15, count 0 2006.189.08:13:51.27#ibcon#read 5, iclass 15, count 0 2006.189.08:13:51.27#ibcon#about to read 6, iclass 15, count 0 2006.189.08:13:51.27#ibcon#read 6, iclass 15, count 0 2006.189.08:13:51.27#ibcon#end of sib2, iclass 15, count 0 2006.189.08:13:51.27#ibcon#*after write, iclass 15, count 0 2006.189.08:13:51.27#ibcon#*before return 0, iclass 15, count 0 2006.189.08:13:51.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:51.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:13:51.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:13:51.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:13:51.27$vc4f8/vblo=3,656.99 2006.189.08:13:51.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.08:13:51.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.08:13:51.27#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:51.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:51.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:51.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:51.27#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:13:51.27#ibcon#first serial, iclass 17, count 0 2006.189.08:13:51.27#ibcon#enter sib2, iclass 17, count 0 2006.189.08:13:51.27#ibcon#flushed, iclass 17, count 0 2006.189.08:13:51.27#ibcon#about to write, iclass 17, count 0 2006.189.08:13:51.27#ibcon#wrote, iclass 17, count 0 2006.189.08:13:51.27#ibcon#about to read 3, iclass 17, count 0 2006.189.08:13:51.29#ibcon#read 3, iclass 17, count 0 2006.189.08:13:51.29#ibcon#about to read 4, iclass 17, count 0 2006.189.08:13:51.29#ibcon#read 4, iclass 17, count 0 2006.189.08:13:51.29#ibcon#about to read 5, iclass 17, count 0 2006.189.08:13:51.29#ibcon#read 5, iclass 17, count 0 2006.189.08:13:51.29#ibcon#about to read 6, iclass 17, count 0 2006.189.08:13:51.29#ibcon#read 6, iclass 17, count 0 2006.189.08:13:51.29#ibcon#end of sib2, iclass 17, count 0 2006.189.08:13:51.29#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:13:51.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:13:51.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:13:51.29#ibcon#*before write, iclass 17, count 0 2006.189.08:13:51.29#ibcon#enter sib2, iclass 17, count 0 2006.189.08:13:51.29#ibcon#flushed, iclass 17, count 0 2006.189.08:13:51.29#ibcon#about to write, iclass 17, count 0 2006.189.08:13:51.29#ibcon#wrote, iclass 17, count 0 2006.189.08:13:51.29#ibcon#about to read 3, iclass 17, count 0 2006.189.08:13:51.33#ibcon#read 3, iclass 17, count 0 2006.189.08:13:51.33#ibcon#about to read 4, iclass 17, count 0 2006.189.08:13:51.33#ibcon#read 4, iclass 17, count 0 2006.189.08:13:51.33#ibcon#about to read 5, iclass 17, count 0 2006.189.08:13:51.33#ibcon#read 5, iclass 17, count 0 2006.189.08:13:51.33#ibcon#about to read 6, iclass 17, count 0 2006.189.08:13:51.33#ibcon#read 6, iclass 17, count 0 2006.189.08:13:51.33#ibcon#end of sib2, iclass 17, count 0 2006.189.08:13:51.33#ibcon#*after write, iclass 17, count 0 2006.189.08:13:51.33#ibcon#*before return 0, iclass 17, count 0 2006.189.08:13:51.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:51.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:13:51.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:13:51.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:13:51.33$vc4f8/vb=3,4 2006.189.08:13:51.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.08:13:51.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.08:13:51.33#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:51.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:51.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:51.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:51.39#ibcon#enter wrdev, iclass 19, count 2 2006.189.08:13:51.39#ibcon#first serial, iclass 19, count 2 2006.189.08:13:51.39#ibcon#enter sib2, iclass 19, count 2 2006.189.08:13:51.39#ibcon#flushed, iclass 19, count 2 2006.189.08:13:51.39#ibcon#about to write, iclass 19, count 2 2006.189.08:13:51.39#ibcon#wrote, iclass 19, count 2 2006.189.08:13:51.39#ibcon#about to read 3, iclass 19, count 2 2006.189.08:13:51.41#ibcon#read 3, iclass 19, count 2 2006.189.08:13:51.41#ibcon#about to read 4, iclass 19, count 2 2006.189.08:13:51.41#ibcon#read 4, iclass 19, count 2 2006.189.08:13:51.41#ibcon#about to read 5, iclass 19, count 2 2006.189.08:13:51.41#ibcon#read 5, iclass 19, count 2 2006.189.08:13:51.41#ibcon#about to read 6, iclass 19, count 2 2006.189.08:13:51.41#ibcon#read 6, iclass 19, count 2 2006.189.08:13:51.41#ibcon#end of sib2, iclass 19, count 2 2006.189.08:13:51.41#ibcon#*mode == 0, iclass 19, count 2 2006.189.08:13:51.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.08:13:51.41#ibcon#[27=AT03-04\r\n] 2006.189.08:13:51.41#ibcon#*before write, iclass 19, count 2 2006.189.08:13:51.41#ibcon#enter sib2, iclass 19, count 2 2006.189.08:13:51.41#ibcon#flushed, iclass 19, count 2 2006.189.08:13:51.41#ibcon#about to write, iclass 19, count 2 2006.189.08:13:51.41#ibcon#wrote, iclass 19, count 2 2006.189.08:13:51.41#ibcon#about to read 3, iclass 19, count 2 2006.189.08:13:51.44#ibcon#read 3, iclass 19, count 2 2006.189.08:13:51.44#ibcon#about to read 4, iclass 19, count 2 2006.189.08:13:51.44#ibcon#read 4, iclass 19, count 2 2006.189.08:13:51.44#ibcon#about to read 5, iclass 19, count 2 2006.189.08:13:51.44#ibcon#read 5, iclass 19, count 2 2006.189.08:13:51.44#ibcon#about to read 6, iclass 19, count 2 2006.189.08:13:51.44#ibcon#read 6, iclass 19, count 2 2006.189.08:13:51.44#ibcon#end of sib2, iclass 19, count 2 2006.189.08:13:51.44#ibcon#*after write, iclass 19, count 2 2006.189.08:13:51.44#ibcon#*before return 0, iclass 19, count 2 2006.189.08:13:51.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:51.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:13:51.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.08:13:51.44#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:51.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:51.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:51.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:51.56#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:13:51.56#ibcon#first serial, iclass 19, count 0 2006.189.08:13:51.56#ibcon#enter sib2, iclass 19, count 0 2006.189.08:13:51.56#ibcon#flushed, iclass 19, count 0 2006.189.08:13:51.56#ibcon#about to write, iclass 19, count 0 2006.189.08:13:51.56#ibcon#wrote, iclass 19, count 0 2006.189.08:13:51.56#ibcon#about to read 3, iclass 19, count 0 2006.189.08:13:51.58#ibcon#read 3, iclass 19, count 0 2006.189.08:13:51.58#ibcon#about to read 4, iclass 19, count 0 2006.189.08:13:51.58#ibcon#read 4, iclass 19, count 0 2006.189.08:13:51.58#ibcon#about to read 5, iclass 19, count 0 2006.189.08:13:51.58#ibcon#read 5, iclass 19, count 0 2006.189.08:13:51.58#ibcon#about to read 6, iclass 19, count 0 2006.189.08:13:51.58#ibcon#read 6, iclass 19, count 0 2006.189.08:13:51.58#ibcon#end of sib2, iclass 19, count 0 2006.189.08:13:51.58#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:13:51.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:13:51.58#ibcon#[27=USB\r\n] 2006.189.08:13:51.58#ibcon#*before write, iclass 19, count 0 2006.189.08:13:51.58#ibcon#enter sib2, iclass 19, count 0 2006.189.08:13:51.58#ibcon#flushed, iclass 19, count 0 2006.189.08:13:51.58#ibcon#about to write, iclass 19, count 0 2006.189.08:13:51.58#ibcon#wrote, iclass 19, count 0 2006.189.08:13:51.58#ibcon#about to read 3, iclass 19, count 0 2006.189.08:13:51.61#ibcon#read 3, iclass 19, count 0 2006.189.08:13:51.61#ibcon#about to read 4, iclass 19, count 0 2006.189.08:13:51.61#ibcon#read 4, iclass 19, count 0 2006.189.08:13:51.61#ibcon#about to read 5, iclass 19, count 0 2006.189.08:13:51.61#ibcon#read 5, iclass 19, count 0 2006.189.08:13:51.61#ibcon#about to read 6, iclass 19, count 0 2006.189.08:13:51.61#ibcon#read 6, iclass 19, count 0 2006.189.08:13:51.61#ibcon#end of sib2, iclass 19, count 0 2006.189.08:13:51.61#ibcon#*after write, iclass 19, count 0 2006.189.08:13:51.61#ibcon#*before return 0, iclass 19, count 0 2006.189.08:13:51.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:51.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:13:51.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:13:51.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:13:51.61$vc4f8/vblo=4,712.99 2006.189.08:13:51.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.08:13:51.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.08:13:51.61#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:51.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:51.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:51.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:51.61#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:13:51.61#ibcon#first serial, iclass 21, count 0 2006.189.08:13:51.61#ibcon#enter sib2, iclass 21, count 0 2006.189.08:13:51.61#ibcon#flushed, iclass 21, count 0 2006.189.08:13:51.61#ibcon#about to write, iclass 21, count 0 2006.189.08:13:51.61#ibcon#wrote, iclass 21, count 0 2006.189.08:13:51.61#ibcon#about to read 3, iclass 21, count 0 2006.189.08:13:51.63#ibcon#read 3, iclass 21, count 0 2006.189.08:13:51.63#ibcon#about to read 4, iclass 21, count 0 2006.189.08:13:51.63#ibcon#read 4, iclass 21, count 0 2006.189.08:13:51.63#ibcon#about to read 5, iclass 21, count 0 2006.189.08:13:51.63#ibcon#read 5, iclass 21, count 0 2006.189.08:13:51.63#ibcon#about to read 6, iclass 21, count 0 2006.189.08:13:51.63#ibcon#read 6, iclass 21, count 0 2006.189.08:13:51.63#ibcon#end of sib2, iclass 21, count 0 2006.189.08:13:51.63#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:13:51.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:13:51.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:13:51.63#ibcon#*before write, iclass 21, count 0 2006.189.08:13:51.63#ibcon#enter sib2, iclass 21, count 0 2006.189.08:13:51.63#ibcon#flushed, iclass 21, count 0 2006.189.08:13:51.63#ibcon#about to write, iclass 21, count 0 2006.189.08:13:51.63#ibcon#wrote, iclass 21, count 0 2006.189.08:13:51.63#ibcon#about to read 3, iclass 21, count 0 2006.189.08:13:51.67#ibcon#read 3, iclass 21, count 0 2006.189.08:13:51.67#ibcon#about to read 4, iclass 21, count 0 2006.189.08:13:51.67#ibcon#read 4, iclass 21, count 0 2006.189.08:13:51.67#ibcon#about to read 5, iclass 21, count 0 2006.189.08:13:51.67#ibcon#read 5, iclass 21, count 0 2006.189.08:13:51.67#ibcon#about to read 6, iclass 21, count 0 2006.189.08:13:51.67#ibcon#read 6, iclass 21, count 0 2006.189.08:13:51.67#ibcon#end of sib2, iclass 21, count 0 2006.189.08:13:51.67#ibcon#*after write, iclass 21, count 0 2006.189.08:13:51.67#ibcon#*before return 0, iclass 21, count 0 2006.189.08:13:51.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:51.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:13:51.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:13:51.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:13:51.67$vc4f8/vb=4,4 2006.189.08:13:51.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.08:13:51.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.08:13:51.67#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:51.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:51.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:51.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:51.73#ibcon#enter wrdev, iclass 23, count 2 2006.189.08:13:51.73#ibcon#first serial, iclass 23, count 2 2006.189.08:13:51.73#ibcon#enter sib2, iclass 23, count 2 2006.189.08:13:51.73#ibcon#flushed, iclass 23, count 2 2006.189.08:13:51.73#ibcon#about to write, iclass 23, count 2 2006.189.08:13:51.73#ibcon#wrote, iclass 23, count 2 2006.189.08:13:51.73#ibcon#about to read 3, iclass 23, count 2 2006.189.08:13:51.75#ibcon#read 3, iclass 23, count 2 2006.189.08:13:51.75#ibcon#about to read 4, iclass 23, count 2 2006.189.08:13:51.75#ibcon#read 4, iclass 23, count 2 2006.189.08:13:51.75#ibcon#about to read 5, iclass 23, count 2 2006.189.08:13:51.75#ibcon#read 5, iclass 23, count 2 2006.189.08:13:51.75#ibcon#about to read 6, iclass 23, count 2 2006.189.08:13:51.75#ibcon#read 6, iclass 23, count 2 2006.189.08:13:51.75#ibcon#end of sib2, iclass 23, count 2 2006.189.08:13:51.75#ibcon#*mode == 0, iclass 23, count 2 2006.189.08:13:51.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.08:13:51.75#ibcon#[27=AT04-04\r\n] 2006.189.08:13:51.75#ibcon#*before write, iclass 23, count 2 2006.189.08:13:51.75#ibcon#enter sib2, iclass 23, count 2 2006.189.08:13:51.75#ibcon#flushed, iclass 23, count 2 2006.189.08:13:51.75#ibcon#about to write, iclass 23, count 2 2006.189.08:13:51.75#ibcon#wrote, iclass 23, count 2 2006.189.08:13:51.75#ibcon#about to read 3, iclass 23, count 2 2006.189.08:13:51.78#ibcon#read 3, iclass 23, count 2 2006.189.08:13:51.78#ibcon#about to read 4, iclass 23, count 2 2006.189.08:13:51.78#ibcon#read 4, iclass 23, count 2 2006.189.08:13:51.78#ibcon#about to read 5, iclass 23, count 2 2006.189.08:13:51.78#ibcon#read 5, iclass 23, count 2 2006.189.08:13:51.78#ibcon#about to read 6, iclass 23, count 2 2006.189.08:13:51.78#ibcon#read 6, iclass 23, count 2 2006.189.08:13:51.78#ibcon#end of sib2, iclass 23, count 2 2006.189.08:13:51.78#ibcon#*after write, iclass 23, count 2 2006.189.08:13:51.78#ibcon#*before return 0, iclass 23, count 2 2006.189.08:13:51.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:51.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:13:51.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.08:13:51.78#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:51.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:51.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:51.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:51.90#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:13:51.90#ibcon#first serial, iclass 23, count 0 2006.189.08:13:51.90#ibcon#enter sib2, iclass 23, count 0 2006.189.08:13:51.90#ibcon#flushed, iclass 23, count 0 2006.189.08:13:51.90#ibcon#about to write, iclass 23, count 0 2006.189.08:13:51.90#ibcon#wrote, iclass 23, count 0 2006.189.08:13:51.90#ibcon#about to read 3, iclass 23, count 0 2006.189.08:13:51.92#ibcon#read 3, iclass 23, count 0 2006.189.08:13:51.92#ibcon#about to read 4, iclass 23, count 0 2006.189.08:13:51.92#ibcon#read 4, iclass 23, count 0 2006.189.08:13:51.92#ibcon#about to read 5, iclass 23, count 0 2006.189.08:13:51.92#ibcon#read 5, iclass 23, count 0 2006.189.08:13:51.92#ibcon#about to read 6, iclass 23, count 0 2006.189.08:13:51.92#ibcon#read 6, iclass 23, count 0 2006.189.08:13:51.92#ibcon#end of sib2, iclass 23, count 0 2006.189.08:13:51.92#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:13:51.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:13:51.92#ibcon#[27=USB\r\n] 2006.189.08:13:51.92#ibcon#*before write, iclass 23, count 0 2006.189.08:13:51.92#ibcon#enter sib2, iclass 23, count 0 2006.189.08:13:51.92#ibcon#flushed, iclass 23, count 0 2006.189.08:13:51.92#ibcon#about to write, iclass 23, count 0 2006.189.08:13:51.92#ibcon#wrote, iclass 23, count 0 2006.189.08:13:51.92#ibcon#about to read 3, iclass 23, count 0 2006.189.08:13:51.95#ibcon#read 3, iclass 23, count 0 2006.189.08:13:51.95#ibcon#about to read 4, iclass 23, count 0 2006.189.08:13:51.95#ibcon#read 4, iclass 23, count 0 2006.189.08:13:51.95#ibcon#about to read 5, iclass 23, count 0 2006.189.08:13:51.95#ibcon#read 5, iclass 23, count 0 2006.189.08:13:51.95#ibcon#about to read 6, iclass 23, count 0 2006.189.08:13:51.95#ibcon#read 6, iclass 23, count 0 2006.189.08:13:51.95#ibcon#end of sib2, iclass 23, count 0 2006.189.08:13:51.95#ibcon#*after write, iclass 23, count 0 2006.189.08:13:51.95#ibcon#*before return 0, iclass 23, count 0 2006.189.08:13:51.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:51.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:13:51.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:13:51.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:13:51.95$vc4f8/vblo=5,744.99 2006.189.08:13:51.95#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.08:13:51.95#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.08:13:51.95#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:51.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:51.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:51.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:51.95#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:13:51.95#ibcon#first serial, iclass 25, count 0 2006.189.08:13:51.95#ibcon#enter sib2, iclass 25, count 0 2006.189.08:13:51.95#ibcon#flushed, iclass 25, count 0 2006.189.08:13:51.95#ibcon#about to write, iclass 25, count 0 2006.189.08:13:51.95#ibcon#wrote, iclass 25, count 0 2006.189.08:13:51.95#ibcon#about to read 3, iclass 25, count 0 2006.189.08:13:51.97#ibcon#read 3, iclass 25, count 0 2006.189.08:13:51.97#ibcon#about to read 4, iclass 25, count 0 2006.189.08:13:51.97#ibcon#read 4, iclass 25, count 0 2006.189.08:13:51.97#ibcon#about to read 5, iclass 25, count 0 2006.189.08:13:51.97#ibcon#read 5, iclass 25, count 0 2006.189.08:13:51.97#ibcon#about to read 6, iclass 25, count 0 2006.189.08:13:51.97#ibcon#read 6, iclass 25, count 0 2006.189.08:13:51.97#ibcon#end of sib2, iclass 25, count 0 2006.189.08:13:51.97#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:13:51.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:13:51.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:13:51.97#ibcon#*before write, iclass 25, count 0 2006.189.08:13:51.97#ibcon#enter sib2, iclass 25, count 0 2006.189.08:13:51.97#ibcon#flushed, iclass 25, count 0 2006.189.08:13:51.97#ibcon#about to write, iclass 25, count 0 2006.189.08:13:51.97#ibcon#wrote, iclass 25, count 0 2006.189.08:13:51.97#ibcon#about to read 3, iclass 25, count 0 2006.189.08:13:52.01#ibcon#read 3, iclass 25, count 0 2006.189.08:13:52.01#ibcon#about to read 4, iclass 25, count 0 2006.189.08:13:52.01#ibcon#read 4, iclass 25, count 0 2006.189.08:13:52.01#ibcon#about to read 5, iclass 25, count 0 2006.189.08:13:52.01#ibcon#read 5, iclass 25, count 0 2006.189.08:13:52.01#ibcon#about to read 6, iclass 25, count 0 2006.189.08:13:52.01#ibcon#read 6, iclass 25, count 0 2006.189.08:13:52.01#ibcon#end of sib2, iclass 25, count 0 2006.189.08:13:52.01#ibcon#*after write, iclass 25, count 0 2006.189.08:13:52.01#ibcon#*before return 0, iclass 25, count 0 2006.189.08:13:52.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:52.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:13:52.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:13:52.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:13:52.01$vc4f8/vb=5,4 2006.189.08:13:52.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.08:13:52.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.08:13:52.01#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:52.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:52.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:52.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:52.07#ibcon#enter wrdev, iclass 27, count 2 2006.189.08:13:52.07#ibcon#first serial, iclass 27, count 2 2006.189.08:13:52.07#ibcon#enter sib2, iclass 27, count 2 2006.189.08:13:52.07#ibcon#flushed, iclass 27, count 2 2006.189.08:13:52.07#ibcon#about to write, iclass 27, count 2 2006.189.08:13:52.07#ibcon#wrote, iclass 27, count 2 2006.189.08:13:52.07#ibcon#about to read 3, iclass 27, count 2 2006.189.08:13:52.09#ibcon#read 3, iclass 27, count 2 2006.189.08:13:52.09#ibcon#about to read 4, iclass 27, count 2 2006.189.08:13:52.09#ibcon#read 4, iclass 27, count 2 2006.189.08:13:52.09#ibcon#about to read 5, iclass 27, count 2 2006.189.08:13:52.09#ibcon#read 5, iclass 27, count 2 2006.189.08:13:52.09#ibcon#about to read 6, iclass 27, count 2 2006.189.08:13:52.09#ibcon#read 6, iclass 27, count 2 2006.189.08:13:52.09#ibcon#end of sib2, iclass 27, count 2 2006.189.08:13:52.09#ibcon#*mode == 0, iclass 27, count 2 2006.189.08:13:52.09#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.08:13:52.09#ibcon#[27=AT05-04\r\n] 2006.189.08:13:52.09#ibcon#*before write, iclass 27, count 2 2006.189.08:13:52.09#ibcon#enter sib2, iclass 27, count 2 2006.189.08:13:52.09#ibcon#flushed, iclass 27, count 2 2006.189.08:13:52.09#ibcon#about to write, iclass 27, count 2 2006.189.08:13:52.09#ibcon#wrote, iclass 27, count 2 2006.189.08:13:52.09#ibcon#about to read 3, iclass 27, count 2 2006.189.08:13:52.12#ibcon#read 3, iclass 27, count 2 2006.189.08:13:52.12#ibcon#about to read 4, iclass 27, count 2 2006.189.08:13:52.12#ibcon#read 4, iclass 27, count 2 2006.189.08:13:52.12#ibcon#about to read 5, iclass 27, count 2 2006.189.08:13:52.12#ibcon#read 5, iclass 27, count 2 2006.189.08:13:52.12#ibcon#about to read 6, iclass 27, count 2 2006.189.08:13:52.12#ibcon#read 6, iclass 27, count 2 2006.189.08:13:52.12#ibcon#end of sib2, iclass 27, count 2 2006.189.08:13:52.12#ibcon#*after write, iclass 27, count 2 2006.189.08:13:52.12#ibcon#*before return 0, iclass 27, count 2 2006.189.08:13:52.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:52.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:13:52.12#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.08:13:52.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:52.12#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:52.24#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:52.24#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:52.24#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:13:52.24#ibcon#first serial, iclass 27, count 0 2006.189.08:13:52.24#ibcon#enter sib2, iclass 27, count 0 2006.189.08:13:52.24#ibcon#flushed, iclass 27, count 0 2006.189.08:13:52.24#ibcon#about to write, iclass 27, count 0 2006.189.08:13:52.24#ibcon#wrote, iclass 27, count 0 2006.189.08:13:52.24#ibcon#about to read 3, iclass 27, count 0 2006.189.08:13:52.26#ibcon#read 3, iclass 27, count 0 2006.189.08:13:52.26#ibcon#about to read 4, iclass 27, count 0 2006.189.08:13:52.26#ibcon#read 4, iclass 27, count 0 2006.189.08:13:52.26#ibcon#about to read 5, iclass 27, count 0 2006.189.08:13:52.26#ibcon#read 5, iclass 27, count 0 2006.189.08:13:52.26#ibcon#about to read 6, iclass 27, count 0 2006.189.08:13:52.26#ibcon#read 6, iclass 27, count 0 2006.189.08:13:52.26#ibcon#end of sib2, iclass 27, count 0 2006.189.08:13:52.26#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:13:52.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:13:52.26#ibcon#[27=USB\r\n] 2006.189.08:13:52.26#ibcon#*before write, iclass 27, count 0 2006.189.08:13:52.26#ibcon#enter sib2, iclass 27, count 0 2006.189.08:13:52.26#ibcon#flushed, iclass 27, count 0 2006.189.08:13:52.26#ibcon#about to write, iclass 27, count 0 2006.189.08:13:52.26#ibcon#wrote, iclass 27, count 0 2006.189.08:13:52.26#ibcon#about to read 3, iclass 27, count 0 2006.189.08:13:52.29#ibcon#read 3, iclass 27, count 0 2006.189.08:13:52.29#ibcon#about to read 4, iclass 27, count 0 2006.189.08:13:52.29#ibcon#read 4, iclass 27, count 0 2006.189.08:13:52.29#ibcon#about to read 5, iclass 27, count 0 2006.189.08:13:52.29#ibcon#read 5, iclass 27, count 0 2006.189.08:13:52.29#ibcon#about to read 6, iclass 27, count 0 2006.189.08:13:52.29#ibcon#read 6, iclass 27, count 0 2006.189.08:13:52.29#ibcon#end of sib2, iclass 27, count 0 2006.189.08:13:52.29#ibcon#*after write, iclass 27, count 0 2006.189.08:13:52.29#ibcon#*before return 0, iclass 27, count 0 2006.189.08:13:52.29#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:52.29#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:13:52.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:13:52.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:13:52.29$vc4f8/vblo=6,752.99 2006.189.08:13:52.29#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.08:13:52.29#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.08:13:52.29#ibcon#ireg 17 cls_cnt 0 2006.189.08:13:52.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:52.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:52.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:52.29#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:13:52.29#ibcon#first serial, iclass 29, count 0 2006.189.08:13:52.29#ibcon#enter sib2, iclass 29, count 0 2006.189.08:13:52.29#ibcon#flushed, iclass 29, count 0 2006.189.08:13:52.29#ibcon#about to write, iclass 29, count 0 2006.189.08:13:52.29#ibcon#wrote, iclass 29, count 0 2006.189.08:13:52.29#ibcon#about to read 3, iclass 29, count 0 2006.189.08:13:52.31#ibcon#read 3, iclass 29, count 0 2006.189.08:13:52.31#ibcon#about to read 4, iclass 29, count 0 2006.189.08:13:52.31#ibcon#read 4, iclass 29, count 0 2006.189.08:13:52.31#ibcon#about to read 5, iclass 29, count 0 2006.189.08:13:52.31#ibcon#read 5, iclass 29, count 0 2006.189.08:13:52.31#ibcon#about to read 6, iclass 29, count 0 2006.189.08:13:52.31#ibcon#read 6, iclass 29, count 0 2006.189.08:13:52.31#ibcon#end of sib2, iclass 29, count 0 2006.189.08:13:52.31#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:13:52.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:13:52.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:13:52.31#ibcon#*before write, iclass 29, count 0 2006.189.08:13:52.31#ibcon#enter sib2, iclass 29, count 0 2006.189.08:13:52.31#ibcon#flushed, iclass 29, count 0 2006.189.08:13:52.31#ibcon#about to write, iclass 29, count 0 2006.189.08:13:52.31#ibcon#wrote, iclass 29, count 0 2006.189.08:13:52.31#ibcon#about to read 3, iclass 29, count 0 2006.189.08:13:52.35#ibcon#read 3, iclass 29, count 0 2006.189.08:13:52.35#ibcon#about to read 4, iclass 29, count 0 2006.189.08:13:52.35#ibcon#read 4, iclass 29, count 0 2006.189.08:13:52.35#ibcon#about to read 5, iclass 29, count 0 2006.189.08:13:52.35#ibcon#read 5, iclass 29, count 0 2006.189.08:13:52.35#ibcon#about to read 6, iclass 29, count 0 2006.189.08:13:52.35#ibcon#read 6, iclass 29, count 0 2006.189.08:13:52.35#ibcon#end of sib2, iclass 29, count 0 2006.189.08:13:52.35#ibcon#*after write, iclass 29, count 0 2006.189.08:13:52.35#ibcon#*before return 0, iclass 29, count 0 2006.189.08:13:52.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:52.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:13:52.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:13:52.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:13:52.35$vc4f8/vb=6,4 2006.189.08:13:52.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.08:13:52.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.08:13:52.35#ibcon#ireg 11 cls_cnt 2 2006.189.08:13:52.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:52.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:52.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:52.41#ibcon#enter wrdev, iclass 31, count 2 2006.189.08:13:52.41#ibcon#first serial, iclass 31, count 2 2006.189.08:13:52.41#ibcon#enter sib2, iclass 31, count 2 2006.189.08:13:52.41#ibcon#flushed, iclass 31, count 2 2006.189.08:13:52.41#ibcon#about to write, iclass 31, count 2 2006.189.08:13:52.41#ibcon#wrote, iclass 31, count 2 2006.189.08:13:52.41#ibcon#about to read 3, iclass 31, count 2 2006.189.08:13:52.43#ibcon#read 3, iclass 31, count 2 2006.189.08:13:52.43#ibcon#about to read 4, iclass 31, count 2 2006.189.08:13:52.43#ibcon#read 4, iclass 31, count 2 2006.189.08:13:52.43#ibcon#about to read 5, iclass 31, count 2 2006.189.08:13:52.43#ibcon#read 5, iclass 31, count 2 2006.189.08:13:52.43#ibcon#about to read 6, iclass 31, count 2 2006.189.08:13:52.43#ibcon#read 6, iclass 31, count 2 2006.189.08:13:52.43#ibcon#end of sib2, iclass 31, count 2 2006.189.08:13:52.43#ibcon#*mode == 0, iclass 31, count 2 2006.189.08:13:52.43#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.08:13:52.43#ibcon#[27=AT06-04\r\n] 2006.189.08:13:52.43#ibcon#*before write, iclass 31, count 2 2006.189.08:13:52.43#ibcon#enter sib2, iclass 31, count 2 2006.189.08:13:52.43#ibcon#flushed, iclass 31, count 2 2006.189.08:13:52.43#ibcon#about to write, iclass 31, count 2 2006.189.08:13:52.43#ibcon#wrote, iclass 31, count 2 2006.189.08:13:52.43#ibcon#about to read 3, iclass 31, count 2 2006.189.08:13:52.46#ibcon#read 3, iclass 31, count 2 2006.189.08:13:52.46#ibcon#about to read 4, iclass 31, count 2 2006.189.08:13:52.46#ibcon#read 4, iclass 31, count 2 2006.189.08:13:52.46#ibcon#about to read 5, iclass 31, count 2 2006.189.08:13:52.46#ibcon#read 5, iclass 31, count 2 2006.189.08:13:52.46#ibcon#about to read 6, iclass 31, count 2 2006.189.08:13:52.46#ibcon#read 6, iclass 31, count 2 2006.189.08:13:52.46#ibcon#end of sib2, iclass 31, count 2 2006.189.08:13:52.46#ibcon#*after write, iclass 31, count 2 2006.189.08:13:52.46#ibcon#*before return 0, iclass 31, count 2 2006.189.08:13:52.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:52.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:13:52.46#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.08:13:52.46#ibcon#ireg 7 cls_cnt 0 2006.189.08:13:52.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:52.58#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:52.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:52.58#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:13:52.58#ibcon#first serial, iclass 31, count 0 2006.189.08:13:52.58#ibcon#enter sib2, iclass 31, count 0 2006.189.08:13:52.58#ibcon#flushed, iclass 31, count 0 2006.189.08:13:52.58#ibcon#about to write, iclass 31, count 0 2006.189.08:13:52.58#ibcon#wrote, iclass 31, count 0 2006.189.08:13:52.58#ibcon#about to read 3, iclass 31, count 0 2006.189.08:13:52.60#ibcon#read 3, iclass 31, count 0 2006.189.08:13:52.60#ibcon#about to read 4, iclass 31, count 0 2006.189.08:13:52.60#ibcon#read 4, iclass 31, count 0 2006.189.08:13:52.60#ibcon#about to read 5, iclass 31, count 0 2006.189.08:13:52.60#ibcon#read 5, iclass 31, count 0 2006.189.08:13:52.60#ibcon#about to read 6, iclass 31, count 0 2006.189.08:13:52.60#ibcon#read 6, iclass 31, count 0 2006.189.08:13:52.60#ibcon#end of sib2, iclass 31, count 0 2006.189.08:13:52.60#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:13:52.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:13:52.60#ibcon#[27=USB\r\n] 2006.189.08:13:52.60#ibcon#*before write, iclass 31, count 0 2006.189.08:13:52.60#ibcon#enter sib2, iclass 31, count 0 2006.189.08:13:52.60#ibcon#flushed, iclass 31, count 0 2006.189.08:13:52.60#ibcon#about to write, iclass 31, count 0 2006.189.08:13:52.60#ibcon#wrote, iclass 31, count 0 2006.189.08:13:52.60#ibcon#about to read 3, iclass 31, count 0 2006.189.08:13:52.63#ibcon#read 3, iclass 31, count 0 2006.189.08:13:52.63#ibcon#about to read 4, iclass 31, count 0 2006.189.08:13:52.63#ibcon#read 4, iclass 31, count 0 2006.189.08:13:52.63#ibcon#about to read 5, iclass 31, count 0 2006.189.08:13:52.63#ibcon#read 5, iclass 31, count 0 2006.189.08:13:52.63#ibcon#about to read 6, iclass 31, count 0 2006.189.08:13:52.63#ibcon#read 6, iclass 31, count 0 2006.189.08:13:52.63#ibcon#end of sib2, iclass 31, count 0 2006.189.08:13:52.63#ibcon#*after write, iclass 31, count 0 2006.189.08:13:52.63#ibcon#*before return 0, iclass 31, count 0 2006.189.08:13:52.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:52.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:13:52.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:13:52.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:13:52.63$vc4f8/vabw=wide 2006.189.08:13:52.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.08:13:52.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.08:13:52.63#ibcon#ireg 8 cls_cnt 0 2006.189.08:13:52.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:52.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:52.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:52.63#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:13:52.63#ibcon#first serial, iclass 33, count 0 2006.189.08:13:52.63#ibcon#enter sib2, iclass 33, count 0 2006.189.08:13:52.63#ibcon#flushed, iclass 33, count 0 2006.189.08:13:52.63#ibcon#about to write, iclass 33, count 0 2006.189.08:13:52.63#ibcon#wrote, iclass 33, count 0 2006.189.08:13:52.63#ibcon#about to read 3, iclass 33, count 0 2006.189.08:13:52.65#ibcon#read 3, iclass 33, count 0 2006.189.08:13:52.65#ibcon#about to read 4, iclass 33, count 0 2006.189.08:13:52.65#ibcon#read 4, iclass 33, count 0 2006.189.08:13:52.65#ibcon#about to read 5, iclass 33, count 0 2006.189.08:13:52.65#ibcon#read 5, iclass 33, count 0 2006.189.08:13:52.65#ibcon#about to read 6, iclass 33, count 0 2006.189.08:13:52.65#ibcon#read 6, iclass 33, count 0 2006.189.08:13:52.65#ibcon#end of sib2, iclass 33, count 0 2006.189.08:13:52.65#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:13:52.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:13:52.65#ibcon#[25=BW32\r\n] 2006.189.08:13:52.65#ibcon#*before write, iclass 33, count 0 2006.189.08:13:52.65#ibcon#enter sib2, iclass 33, count 0 2006.189.08:13:52.65#ibcon#flushed, iclass 33, count 0 2006.189.08:13:52.65#ibcon#about to write, iclass 33, count 0 2006.189.08:13:52.65#ibcon#wrote, iclass 33, count 0 2006.189.08:13:52.65#ibcon#about to read 3, iclass 33, count 0 2006.189.08:13:52.68#ibcon#read 3, iclass 33, count 0 2006.189.08:13:52.68#ibcon#about to read 4, iclass 33, count 0 2006.189.08:13:52.68#ibcon#read 4, iclass 33, count 0 2006.189.08:13:52.68#ibcon#about to read 5, iclass 33, count 0 2006.189.08:13:52.68#ibcon#read 5, iclass 33, count 0 2006.189.08:13:52.68#ibcon#about to read 6, iclass 33, count 0 2006.189.08:13:52.68#ibcon#read 6, iclass 33, count 0 2006.189.08:13:52.68#ibcon#end of sib2, iclass 33, count 0 2006.189.08:13:52.68#ibcon#*after write, iclass 33, count 0 2006.189.08:13:52.68#ibcon#*before return 0, iclass 33, count 0 2006.189.08:13:52.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:52.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:13:52.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:13:52.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:13:52.68$vc4f8/vbbw=wide 2006.189.08:13:52.68#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.08:13:52.68#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.08:13:52.68#ibcon#ireg 8 cls_cnt 0 2006.189.08:13:52.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:13:52.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:13:52.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:13:52.75#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:13:52.75#ibcon#first serial, iclass 35, count 0 2006.189.08:13:52.75#ibcon#enter sib2, iclass 35, count 0 2006.189.08:13:52.75#ibcon#flushed, iclass 35, count 0 2006.189.08:13:52.75#ibcon#about to write, iclass 35, count 0 2006.189.08:13:52.75#ibcon#wrote, iclass 35, count 0 2006.189.08:13:52.75#ibcon#about to read 3, iclass 35, count 0 2006.189.08:13:52.77#ibcon#read 3, iclass 35, count 0 2006.189.08:13:52.77#ibcon#about to read 4, iclass 35, count 0 2006.189.08:13:52.77#ibcon#read 4, iclass 35, count 0 2006.189.08:13:52.77#ibcon#about to read 5, iclass 35, count 0 2006.189.08:13:52.77#ibcon#read 5, iclass 35, count 0 2006.189.08:13:52.77#ibcon#about to read 6, iclass 35, count 0 2006.189.08:13:52.77#ibcon#read 6, iclass 35, count 0 2006.189.08:13:52.77#ibcon#end of sib2, iclass 35, count 0 2006.189.08:13:52.77#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:13:52.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:13:52.77#ibcon#[27=BW32\r\n] 2006.189.08:13:52.77#ibcon#*before write, iclass 35, count 0 2006.189.08:13:52.77#ibcon#enter sib2, iclass 35, count 0 2006.189.08:13:52.77#ibcon#flushed, iclass 35, count 0 2006.189.08:13:52.77#ibcon#about to write, iclass 35, count 0 2006.189.08:13:52.77#ibcon#wrote, iclass 35, count 0 2006.189.08:13:52.77#ibcon#about to read 3, iclass 35, count 0 2006.189.08:13:52.80#ibcon#read 3, iclass 35, count 0 2006.189.08:13:52.80#ibcon#about to read 4, iclass 35, count 0 2006.189.08:13:52.80#ibcon#read 4, iclass 35, count 0 2006.189.08:13:52.80#ibcon#about to read 5, iclass 35, count 0 2006.189.08:13:52.80#ibcon#read 5, iclass 35, count 0 2006.189.08:13:52.80#ibcon#about to read 6, iclass 35, count 0 2006.189.08:13:52.80#ibcon#read 6, iclass 35, count 0 2006.189.08:13:52.80#ibcon#end of sib2, iclass 35, count 0 2006.189.08:13:52.80#ibcon#*after write, iclass 35, count 0 2006.189.08:13:52.80#ibcon#*before return 0, iclass 35, count 0 2006.189.08:13:52.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:13:52.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:13:52.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:13:52.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:13:52.80$4f8m12a/ifd4f 2006.189.08:13:52.80$ifd4f/lo= 2006.189.08:13:52.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:13:52.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:13:52.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:13:52.80$ifd4f/patch= 2006.189.08:13:52.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:13:52.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:13:52.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:13:52.81$4f8m12a/"form=m,16.000,1:2 2006.189.08:13:52.81$4f8m12a/"tpicd 2006.189.08:13:52.81$4f8m12a/echo=off 2006.189.08:13:52.81$4f8m12a/xlog=off 2006.189.08:13:52.81:!2006.189.08:15:00 2006.189.08:14:41.14#trakl#Source acquired 2006.189.08:14:41.14#flagr#flagr/antenna,acquired 2006.189.08:15:00.01:preob 2006.189.08:15:01.14/onsource/TRACKING 2006.189.08:15:01.14:!2006.189.08:15:10 2006.189.08:15:10.00:data_valid=on 2006.189.08:15:10.00:midob 2006.189.08:15:10.14/onsource/TRACKING 2006.189.08:15:10.14/wx/25.45,1009.2,91 2006.189.08:15:10.36/cable/+6.4567E-03 2006.189.08:15:11.45/va/01,08,usb,yes,28,30 2006.189.08:15:11.45/va/02,07,usb,yes,29,30 2006.189.08:15:11.45/va/03,06,usb,yes,30,30 2006.189.08:15:11.45/va/04,07,usb,yes,30,32 2006.189.08:15:11.45/va/05,07,usb,yes,32,34 2006.189.08:15:11.45/va/06,06,usb,yes,31,31 2006.189.08:15:11.45/va/07,06,usb,yes,31,31 2006.189.08:15:11.45/va/08,06,usb,yes,34,33 2006.189.08:15:11.68/valo/01,532.99,yes,locked 2006.189.08:15:11.68/valo/02,572.99,yes,locked 2006.189.08:15:11.68/valo/03,672.99,yes,locked 2006.189.08:15:11.68/valo/04,832.99,yes,locked 2006.189.08:15:11.68/valo/05,652.99,yes,locked 2006.189.08:15:11.68/valo/06,772.99,yes,locked 2006.189.08:15:11.68/valo/07,832.99,yes,locked 2006.189.08:15:11.68/valo/08,852.99,yes,locked 2006.189.08:15:12.77/vb/01,04,usb,yes,29,27 2006.189.08:15:12.77/vb/02,04,usb,yes,30,32 2006.189.08:15:12.77/vb/03,04,usb,yes,27,31 2006.189.08:15:12.77/vb/04,04,usb,yes,28,28 2006.189.08:15:12.77/vb/05,04,usb,yes,26,30 2006.189.08:15:12.77/vb/06,04,usb,yes,27,30 2006.189.08:15:12.77/vb/07,04,usb,yes,29,29 2006.189.08:15:12.77/vb/08,04,usb,yes,27,30 2006.189.08:15:13.01/vblo/01,632.99,yes,locked 2006.189.08:15:13.01/vblo/02,640.99,yes,locked 2006.189.08:15:13.01/vblo/03,656.99,yes,locked 2006.189.08:15:13.01/vblo/04,712.99,yes,locked 2006.189.08:15:13.01/vblo/05,744.99,yes,locked 2006.189.08:15:13.01/vblo/06,752.99,yes,locked 2006.189.08:15:13.01/vblo/07,734.99,yes,locked 2006.189.08:15:13.01/vblo/08,744.99,yes,locked 2006.189.08:15:13.16/vabw/8 2006.189.08:15:13.31/vbbw/8 2006.189.08:15:13.40/xfe/off,on,15.0 2006.189.08:15:13.77/ifatt/23,28,28,28 2006.189.08:15:14.07/fmout-gps/S +3.00E-07 2006.189.08:15:14.16:!2006.189.08:16:10 2006.189.08:16:10.01:data_valid=off 2006.189.08:16:10.02:postob 2006.189.08:16:10.10/cable/+6.4556E-03 2006.189.08:16:10.11/wx/25.43,1009.2,91 2006.189.08:16:11.07/fmout-gps/S +2.99E-07 2006.189.08:16:11.08:scan_name=189-0817,k06189,60 2006.189.08:16:11.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.189.08:16:12.14#flagr#flagr/antenna,new-source 2006.189.08:16:12.15:checkk5 2006.189.08:16:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:16:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:16:13.30/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:16:13.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:16:14.05/chk_obsdata//k5ts1/T1890815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:16:14.43/chk_obsdata//k5ts2/T1890815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:16:14.81/chk_obsdata//k5ts3/T1890815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:16:15.18/chk_obsdata//k5ts4/T1890815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:16:15.90/k5log//k5ts1_log_newline 2006.189.08:16:16.59/k5log//k5ts2_log_newline 2006.189.08:16:17.29/k5log//k5ts3_log_newline 2006.189.08:16:17.98/k5log//k5ts4_log_newline 2006.189.08:16:18.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:16:18.01:4f8m12a=2 2006.189.08:16:18.01$4f8m12a/echo=on 2006.189.08:16:18.01$4f8m12a/pcalon 2006.189.08:16:18.01$pcalon/"no phase cal control is implemented here 2006.189.08:16:18.01$4f8m12a/"tpicd=stop 2006.189.08:16:18.01$4f8m12a/vc4f8 2006.189.08:16:18.01$vc4f8/valo=1,532.99 2006.189.08:16:18.01#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.08:16:18.01#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.08:16:18.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:18.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:18.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:18.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:18.01#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:16:18.01#ibcon#first serial, iclass 26, count 0 2006.189.08:16:18.01#ibcon#enter sib2, iclass 26, count 0 2006.189.08:16:18.01#ibcon#flushed, iclass 26, count 0 2006.189.08:16:18.01#ibcon#about to write, iclass 26, count 0 2006.189.08:16:18.01#ibcon#wrote, iclass 26, count 0 2006.189.08:16:18.01#ibcon#about to read 3, iclass 26, count 0 2006.189.08:16:18.02#ibcon#read 3, iclass 26, count 0 2006.189.08:16:18.02#ibcon#about to read 4, iclass 26, count 0 2006.189.08:16:18.02#ibcon#read 4, iclass 26, count 0 2006.189.08:16:18.02#ibcon#about to read 5, iclass 26, count 0 2006.189.08:16:18.02#ibcon#read 5, iclass 26, count 0 2006.189.08:16:18.02#ibcon#about to read 6, iclass 26, count 0 2006.189.08:16:18.02#ibcon#read 6, iclass 26, count 0 2006.189.08:16:18.02#ibcon#end of sib2, iclass 26, count 0 2006.189.08:16:18.02#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:16:18.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:16:18.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:16:18.02#ibcon#*before write, iclass 26, count 0 2006.189.08:16:18.02#ibcon#enter sib2, iclass 26, count 0 2006.189.08:16:18.02#ibcon#flushed, iclass 26, count 0 2006.189.08:16:18.02#ibcon#about to write, iclass 26, count 0 2006.189.08:16:18.02#ibcon#wrote, iclass 26, count 0 2006.189.08:16:18.02#ibcon#about to read 3, iclass 26, count 0 2006.189.08:16:18.08#ibcon#read 3, iclass 26, count 0 2006.189.08:16:18.08#ibcon#about to read 4, iclass 26, count 0 2006.189.08:16:18.08#ibcon#read 4, iclass 26, count 0 2006.189.08:16:18.08#ibcon#about to read 5, iclass 26, count 0 2006.189.08:16:18.08#ibcon#read 5, iclass 26, count 0 2006.189.08:16:18.08#ibcon#about to read 6, iclass 26, count 0 2006.189.08:16:18.08#ibcon#read 6, iclass 26, count 0 2006.189.08:16:18.08#ibcon#end of sib2, iclass 26, count 0 2006.189.08:16:18.08#ibcon#*after write, iclass 26, count 0 2006.189.08:16:18.08#ibcon#*before return 0, iclass 26, count 0 2006.189.08:16:18.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:18.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:18.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:16:18.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:16:18.08$vc4f8/va=1,8 2006.189.08:16:18.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.08:16:18.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.08:16:18.08#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:18.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:18.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:18.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:18.08#ibcon#enter wrdev, iclass 28, count 2 2006.189.08:16:18.08#ibcon#first serial, iclass 28, count 2 2006.189.08:16:18.08#ibcon#enter sib2, iclass 28, count 2 2006.189.08:16:18.08#ibcon#flushed, iclass 28, count 2 2006.189.08:16:18.08#ibcon#about to write, iclass 28, count 2 2006.189.08:16:18.08#ibcon#wrote, iclass 28, count 2 2006.189.08:16:18.08#ibcon#about to read 3, iclass 28, count 2 2006.189.08:16:18.09#ibcon#read 3, iclass 28, count 2 2006.189.08:16:18.09#ibcon#about to read 4, iclass 28, count 2 2006.189.08:16:18.09#ibcon#read 4, iclass 28, count 2 2006.189.08:16:18.09#ibcon#about to read 5, iclass 28, count 2 2006.189.08:16:18.09#ibcon#read 5, iclass 28, count 2 2006.189.08:16:18.09#ibcon#about to read 6, iclass 28, count 2 2006.189.08:16:18.09#ibcon#read 6, iclass 28, count 2 2006.189.08:16:18.09#ibcon#end of sib2, iclass 28, count 2 2006.189.08:16:18.09#ibcon#*mode == 0, iclass 28, count 2 2006.189.08:16:18.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.08:16:18.09#ibcon#[25=AT01-08\r\n] 2006.189.08:16:18.09#ibcon#*before write, iclass 28, count 2 2006.189.08:16:18.09#ibcon#enter sib2, iclass 28, count 2 2006.189.08:16:18.09#ibcon#flushed, iclass 28, count 2 2006.189.08:16:18.09#ibcon#about to write, iclass 28, count 2 2006.189.08:16:18.09#ibcon#wrote, iclass 28, count 2 2006.189.08:16:18.09#ibcon#about to read 3, iclass 28, count 2 2006.189.08:16:18.12#ibcon#read 3, iclass 28, count 2 2006.189.08:16:18.12#ibcon#about to read 4, iclass 28, count 2 2006.189.08:16:18.12#ibcon#read 4, iclass 28, count 2 2006.189.08:16:18.12#ibcon#about to read 5, iclass 28, count 2 2006.189.08:16:18.12#ibcon#read 5, iclass 28, count 2 2006.189.08:16:18.12#ibcon#about to read 6, iclass 28, count 2 2006.189.08:16:18.12#ibcon#read 6, iclass 28, count 2 2006.189.08:16:18.12#ibcon#end of sib2, iclass 28, count 2 2006.189.08:16:18.12#ibcon#*after write, iclass 28, count 2 2006.189.08:16:18.12#ibcon#*before return 0, iclass 28, count 2 2006.189.08:16:18.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:18.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:18.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.08:16:18.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:18.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:18.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:18.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:18.26#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:16:18.26#ibcon#first serial, iclass 28, count 0 2006.189.08:16:18.26#ibcon#enter sib2, iclass 28, count 0 2006.189.08:16:18.26#ibcon#flushed, iclass 28, count 0 2006.189.08:16:18.26#ibcon#about to write, iclass 28, count 0 2006.189.08:16:18.26#ibcon#wrote, iclass 28, count 0 2006.189.08:16:18.26#ibcon#about to read 3, iclass 28, count 0 2006.189.08:16:18.28#ibcon#read 3, iclass 28, count 0 2006.189.08:16:18.28#ibcon#about to read 4, iclass 28, count 0 2006.189.08:16:18.28#ibcon#read 4, iclass 28, count 0 2006.189.08:16:18.28#ibcon#about to read 5, iclass 28, count 0 2006.189.08:16:18.28#ibcon#read 5, iclass 28, count 0 2006.189.08:16:18.28#ibcon#about to read 6, iclass 28, count 0 2006.189.08:16:18.28#ibcon#read 6, iclass 28, count 0 2006.189.08:16:18.28#ibcon#end of sib2, iclass 28, count 0 2006.189.08:16:18.28#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:16:18.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:16:18.28#ibcon#[25=USB\r\n] 2006.189.08:16:18.28#ibcon#*before write, iclass 28, count 0 2006.189.08:16:18.28#ibcon#enter sib2, iclass 28, count 0 2006.189.08:16:18.28#ibcon#flushed, iclass 28, count 0 2006.189.08:16:18.28#ibcon#about to write, iclass 28, count 0 2006.189.08:16:18.28#ibcon#wrote, iclass 28, count 0 2006.189.08:16:18.28#ibcon#about to read 3, iclass 28, count 0 2006.189.08:16:18.30#ibcon#read 3, iclass 28, count 0 2006.189.08:16:18.30#ibcon#about to read 4, iclass 28, count 0 2006.189.08:16:18.30#ibcon#read 4, iclass 28, count 0 2006.189.08:16:18.30#ibcon#about to read 5, iclass 28, count 0 2006.189.08:16:18.30#ibcon#read 5, iclass 28, count 0 2006.189.08:16:18.30#ibcon#about to read 6, iclass 28, count 0 2006.189.08:16:18.30#ibcon#read 6, iclass 28, count 0 2006.189.08:16:18.30#ibcon#end of sib2, iclass 28, count 0 2006.189.08:16:18.30#ibcon#*after write, iclass 28, count 0 2006.189.08:16:18.30#ibcon#*before return 0, iclass 28, count 0 2006.189.08:16:18.30#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:18.30#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:18.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:16:18.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:16:18.30$vc4f8/valo=2,572.99 2006.189.08:16:18.30#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.08:16:18.30#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.08:16:18.30#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:18.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:18.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:18.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:18.30#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:16:18.30#ibcon#first serial, iclass 30, count 0 2006.189.08:16:18.30#ibcon#enter sib2, iclass 30, count 0 2006.189.08:16:18.30#ibcon#flushed, iclass 30, count 0 2006.189.08:16:18.30#ibcon#about to write, iclass 30, count 0 2006.189.08:16:18.30#ibcon#wrote, iclass 30, count 0 2006.189.08:16:18.30#ibcon#about to read 3, iclass 30, count 0 2006.189.08:16:18.32#ibcon#read 3, iclass 30, count 0 2006.189.08:16:18.32#ibcon#about to read 4, iclass 30, count 0 2006.189.08:16:18.32#ibcon#read 4, iclass 30, count 0 2006.189.08:16:18.32#ibcon#about to read 5, iclass 30, count 0 2006.189.08:16:18.32#ibcon#read 5, iclass 30, count 0 2006.189.08:16:18.32#ibcon#about to read 6, iclass 30, count 0 2006.189.08:16:18.32#ibcon#read 6, iclass 30, count 0 2006.189.08:16:18.32#ibcon#end of sib2, iclass 30, count 0 2006.189.08:16:18.32#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:16:18.32#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:16:18.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:16:18.32#ibcon#*before write, iclass 30, count 0 2006.189.08:16:18.32#ibcon#enter sib2, iclass 30, count 0 2006.189.08:16:18.32#ibcon#flushed, iclass 30, count 0 2006.189.08:16:18.32#ibcon#about to write, iclass 30, count 0 2006.189.08:16:18.32#ibcon#wrote, iclass 30, count 0 2006.189.08:16:18.32#ibcon#about to read 3, iclass 30, count 0 2006.189.08:16:18.37#ibcon#read 3, iclass 30, count 0 2006.189.08:16:18.37#ibcon#about to read 4, iclass 30, count 0 2006.189.08:16:18.37#ibcon#read 4, iclass 30, count 0 2006.189.08:16:18.37#ibcon#about to read 5, iclass 30, count 0 2006.189.08:16:18.37#ibcon#read 5, iclass 30, count 0 2006.189.08:16:18.37#ibcon#about to read 6, iclass 30, count 0 2006.189.08:16:18.37#ibcon#read 6, iclass 30, count 0 2006.189.08:16:18.37#ibcon#end of sib2, iclass 30, count 0 2006.189.08:16:18.37#ibcon#*after write, iclass 30, count 0 2006.189.08:16:18.37#ibcon#*before return 0, iclass 30, count 0 2006.189.08:16:18.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:18.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:18.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:16:18.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:16:18.37$vc4f8/va=2,7 2006.189.08:16:18.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.08:16:18.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.08:16:18.37#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:18.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:18.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:18.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:18.41#ibcon#enter wrdev, iclass 32, count 2 2006.189.08:16:18.41#ibcon#first serial, iclass 32, count 2 2006.189.08:16:18.41#ibcon#enter sib2, iclass 32, count 2 2006.189.08:16:18.41#ibcon#flushed, iclass 32, count 2 2006.189.08:16:18.41#ibcon#about to write, iclass 32, count 2 2006.189.08:16:18.41#ibcon#wrote, iclass 32, count 2 2006.189.08:16:18.41#ibcon#about to read 3, iclass 32, count 2 2006.189.08:16:18.43#ibcon#read 3, iclass 32, count 2 2006.189.08:16:18.43#ibcon#about to read 4, iclass 32, count 2 2006.189.08:16:18.43#ibcon#read 4, iclass 32, count 2 2006.189.08:16:18.43#ibcon#about to read 5, iclass 32, count 2 2006.189.08:16:18.43#ibcon#read 5, iclass 32, count 2 2006.189.08:16:18.43#ibcon#about to read 6, iclass 32, count 2 2006.189.08:16:18.43#ibcon#read 6, iclass 32, count 2 2006.189.08:16:18.43#ibcon#end of sib2, iclass 32, count 2 2006.189.08:16:18.43#ibcon#*mode == 0, iclass 32, count 2 2006.189.08:16:18.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.08:16:18.43#ibcon#[25=AT02-07\r\n] 2006.189.08:16:18.43#ibcon#*before write, iclass 32, count 2 2006.189.08:16:18.43#ibcon#enter sib2, iclass 32, count 2 2006.189.08:16:18.43#ibcon#flushed, iclass 32, count 2 2006.189.08:16:18.43#ibcon#about to write, iclass 32, count 2 2006.189.08:16:18.43#ibcon#wrote, iclass 32, count 2 2006.189.08:16:18.43#ibcon#about to read 3, iclass 32, count 2 2006.189.08:16:18.47#ibcon#read 3, iclass 32, count 2 2006.189.08:16:18.47#ibcon#about to read 4, iclass 32, count 2 2006.189.08:16:18.47#ibcon#read 4, iclass 32, count 2 2006.189.08:16:18.47#ibcon#about to read 5, iclass 32, count 2 2006.189.08:16:18.47#ibcon#read 5, iclass 32, count 2 2006.189.08:16:18.47#ibcon#about to read 6, iclass 32, count 2 2006.189.08:16:18.47#ibcon#read 6, iclass 32, count 2 2006.189.08:16:18.47#ibcon#end of sib2, iclass 32, count 2 2006.189.08:16:18.47#ibcon#*after write, iclass 32, count 2 2006.189.08:16:18.47#ibcon#*before return 0, iclass 32, count 2 2006.189.08:16:18.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:18.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:18.47#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.08:16:18.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:18.47#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:18.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:18.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:18.58#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:16:18.58#ibcon#first serial, iclass 32, count 0 2006.189.08:16:18.58#ibcon#enter sib2, iclass 32, count 0 2006.189.08:16:18.58#ibcon#flushed, iclass 32, count 0 2006.189.08:16:18.58#ibcon#about to write, iclass 32, count 0 2006.189.08:16:18.58#ibcon#wrote, iclass 32, count 0 2006.189.08:16:18.58#ibcon#about to read 3, iclass 32, count 0 2006.189.08:16:18.60#ibcon#read 3, iclass 32, count 0 2006.189.08:16:18.60#ibcon#about to read 4, iclass 32, count 0 2006.189.08:16:18.60#ibcon#read 4, iclass 32, count 0 2006.189.08:16:18.60#ibcon#about to read 5, iclass 32, count 0 2006.189.08:16:18.60#ibcon#read 5, iclass 32, count 0 2006.189.08:16:18.60#ibcon#about to read 6, iclass 32, count 0 2006.189.08:16:18.60#ibcon#read 6, iclass 32, count 0 2006.189.08:16:18.60#ibcon#end of sib2, iclass 32, count 0 2006.189.08:16:18.60#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:16:18.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:16:18.60#ibcon#[25=USB\r\n] 2006.189.08:16:18.60#ibcon#*before write, iclass 32, count 0 2006.189.08:16:18.60#ibcon#enter sib2, iclass 32, count 0 2006.189.08:16:18.60#ibcon#flushed, iclass 32, count 0 2006.189.08:16:18.60#ibcon#about to write, iclass 32, count 0 2006.189.08:16:18.60#ibcon#wrote, iclass 32, count 0 2006.189.08:16:18.60#ibcon#about to read 3, iclass 32, count 0 2006.189.08:16:18.63#ibcon#read 3, iclass 32, count 0 2006.189.08:16:18.63#ibcon#about to read 4, iclass 32, count 0 2006.189.08:16:18.63#ibcon#read 4, iclass 32, count 0 2006.189.08:16:18.63#ibcon#about to read 5, iclass 32, count 0 2006.189.08:16:18.63#ibcon#read 5, iclass 32, count 0 2006.189.08:16:18.63#ibcon#about to read 6, iclass 32, count 0 2006.189.08:16:18.63#ibcon#read 6, iclass 32, count 0 2006.189.08:16:18.63#ibcon#end of sib2, iclass 32, count 0 2006.189.08:16:18.63#ibcon#*after write, iclass 32, count 0 2006.189.08:16:18.63#ibcon#*before return 0, iclass 32, count 0 2006.189.08:16:18.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:18.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:18.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:16:18.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:16:18.63$vc4f8/valo=3,672.99 2006.189.08:16:18.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.08:16:18.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.08:16:18.63#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:18.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:18.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:18.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:18.63#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:16:18.63#ibcon#first serial, iclass 34, count 0 2006.189.08:16:18.63#ibcon#enter sib2, iclass 34, count 0 2006.189.08:16:18.63#ibcon#flushed, iclass 34, count 0 2006.189.08:16:18.63#ibcon#about to write, iclass 34, count 0 2006.189.08:16:18.63#ibcon#wrote, iclass 34, count 0 2006.189.08:16:18.63#ibcon#about to read 3, iclass 34, count 0 2006.189.08:16:18.65#ibcon#read 3, iclass 34, count 0 2006.189.08:16:18.65#ibcon#about to read 4, iclass 34, count 0 2006.189.08:16:18.65#ibcon#read 4, iclass 34, count 0 2006.189.08:16:18.65#ibcon#about to read 5, iclass 34, count 0 2006.189.08:16:18.65#ibcon#read 5, iclass 34, count 0 2006.189.08:16:18.65#ibcon#about to read 6, iclass 34, count 0 2006.189.08:16:18.65#ibcon#read 6, iclass 34, count 0 2006.189.08:16:18.65#ibcon#end of sib2, iclass 34, count 0 2006.189.08:16:18.65#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:16:18.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:16:18.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:16:18.65#ibcon#*before write, iclass 34, count 0 2006.189.08:16:18.65#ibcon#enter sib2, iclass 34, count 0 2006.189.08:16:18.65#ibcon#flushed, iclass 34, count 0 2006.189.08:16:18.65#ibcon#about to write, iclass 34, count 0 2006.189.08:16:18.65#ibcon#wrote, iclass 34, count 0 2006.189.08:16:18.65#ibcon#about to read 3, iclass 34, count 0 2006.189.08:16:18.69#ibcon#read 3, iclass 34, count 0 2006.189.08:16:18.69#ibcon#about to read 4, iclass 34, count 0 2006.189.08:16:18.69#ibcon#read 4, iclass 34, count 0 2006.189.08:16:18.69#ibcon#about to read 5, iclass 34, count 0 2006.189.08:16:18.69#ibcon#read 5, iclass 34, count 0 2006.189.08:16:18.69#ibcon#about to read 6, iclass 34, count 0 2006.189.08:16:18.69#ibcon#read 6, iclass 34, count 0 2006.189.08:16:18.69#ibcon#end of sib2, iclass 34, count 0 2006.189.08:16:18.69#ibcon#*after write, iclass 34, count 0 2006.189.08:16:18.69#ibcon#*before return 0, iclass 34, count 0 2006.189.08:16:18.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:18.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:18.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:16:18.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:16:18.69$vc4f8/va=3,6 2006.189.08:16:18.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.08:16:18.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.08:16:18.69#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:18.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:18.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:18.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:18.75#ibcon#enter wrdev, iclass 36, count 2 2006.189.08:16:18.75#ibcon#first serial, iclass 36, count 2 2006.189.08:16:18.75#ibcon#enter sib2, iclass 36, count 2 2006.189.08:16:18.75#ibcon#flushed, iclass 36, count 2 2006.189.08:16:18.75#ibcon#about to write, iclass 36, count 2 2006.189.08:16:18.75#ibcon#wrote, iclass 36, count 2 2006.189.08:16:18.75#ibcon#about to read 3, iclass 36, count 2 2006.189.08:16:18.77#ibcon#read 3, iclass 36, count 2 2006.189.08:16:18.77#ibcon#about to read 4, iclass 36, count 2 2006.189.08:16:18.77#ibcon#read 4, iclass 36, count 2 2006.189.08:16:18.77#ibcon#about to read 5, iclass 36, count 2 2006.189.08:16:18.77#ibcon#read 5, iclass 36, count 2 2006.189.08:16:18.77#ibcon#about to read 6, iclass 36, count 2 2006.189.08:16:18.77#ibcon#read 6, iclass 36, count 2 2006.189.08:16:18.77#ibcon#end of sib2, iclass 36, count 2 2006.189.08:16:18.77#ibcon#*mode == 0, iclass 36, count 2 2006.189.08:16:18.77#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.08:16:18.77#ibcon#[25=AT03-06\r\n] 2006.189.08:16:18.77#ibcon#*before write, iclass 36, count 2 2006.189.08:16:18.77#ibcon#enter sib2, iclass 36, count 2 2006.189.08:16:18.77#ibcon#flushed, iclass 36, count 2 2006.189.08:16:18.77#ibcon#about to write, iclass 36, count 2 2006.189.08:16:18.77#ibcon#wrote, iclass 36, count 2 2006.189.08:16:18.77#ibcon#about to read 3, iclass 36, count 2 2006.189.08:16:18.80#ibcon#read 3, iclass 36, count 2 2006.189.08:16:18.80#ibcon#about to read 4, iclass 36, count 2 2006.189.08:16:18.80#ibcon#read 4, iclass 36, count 2 2006.189.08:16:18.80#ibcon#about to read 5, iclass 36, count 2 2006.189.08:16:18.80#ibcon#read 5, iclass 36, count 2 2006.189.08:16:18.80#ibcon#about to read 6, iclass 36, count 2 2006.189.08:16:18.80#ibcon#read 6, iclass 36, count 2 2006.189.08:16:18.80#ibcon#end of sib2, iclass 36, count 2 2006.189.08:16:18.80#ibcon#*after write, iclass 36, count 2 2006.189.08:16:18.80#ibcon#*before return 0, iclass 36, count 2 2006.189.08:16:18.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:18.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:18.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.08:16:18.80#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:18.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:18.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:18.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:18.92#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:16:18.92#ibcon#first serial, iclass 36, count 0 2006.189.08:16:18.92#ibcon#enter sib2, iclass 36, count 0 2006.189.08:16:18.92#ibcon#flushed, iclass 36, count 0 2006.189.08:16:18.92#ibcon#about to write, iclass 36, count 0 2006.189.08:16:18.92#ibcon#wrote, iclass 36, count 0 2006.189.08:16:18.92#ibcon#about to read 3, iclass 36, count 0 2006.189.08:16:18.94#ibcon#read 3, iclass 36, count 0 2006.189.08:16:18.94#ibcon#about to read 4, iclass 36, count 0 2006.189.08:16:18.94#ibcon#read 4, iclass 36, count 0 2006.189.08:16:18.94#ibcon#about to read 5, iclass 36, count 0 2006.189.08:16:18.94#ibcon#read 5, iclass 36, count 0 2006.189.08:16:18.94#ibcon#about to read 6, iclass 36, count 0 2006.189.08:16:18.94#ibcon#read 6, iclass 36, count 0 2006.189.08:16:18.94#ibcon#end of sib2, iclass 36, count 0 2006.189.08:16:18.94#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:16:18.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:16:18.94#ibcon#[25=USB\r\n] 2006.189.08:16:18.94#ibcon#*before write, iclass 36, count 0 2006.189.08:16:18.94#ibcon#enter sib2, iclass 36, count 0 2006.189.08:16:18.94#ibcon#flushed, iclass 36, count 0 2006.189.08:16:18.94#ibcon#about to write, iclass 36, count 0 2006.189.08:16:18.94#ibcon#wrote, iclass 36, count 0 2006.189.08:16:18.94#ibcon#about to read 3, iclass 36, count 0 2006.189.08:16:18.97#ibcon#read 3, iclass 36, count 0 2006.189.08:16:18.97#ibcon#about to read 4, iclass 36, count 0 2006.189.08:16:18.97#ibcon#read 4, iclass 36, count 0 2006.189.08:16:18.97#ibcon#about to read 5, iclass 36, count 0 2006.189.08:16:18.97#ibcon#read 5, iclass 36, count 0 2006.189.08:16:18.97#ibcon#about to read 6, iclass 36, count 0 2006.189.08:16:18.97#ibcon#read 6, iclass 36, count 0 2006.189.08:16:18.97#ibcon#end of sib2, iclass 36, count 0 2006.189.08:16:18.97#ibcon#*after write, iclass 36, count 0 2006.189.08:16:18.97#ibcon#*before return 0, iclass 36, count 0 2006.189.08:16:18.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:18.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:18.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:16:18.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:16:18.97$vc4f8/valo=4,832.99 2006.189.08:16:18.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.08:16:18.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.08:16:18.97#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:18.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:18.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:18.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:18.97#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:16:18.97#ibcon#first serial, iclass 38, count 0 2006.189.08:16:18.97#ibcon#enter sib2, iclass 38, count 0 2006.189.08:16:18.97#ibcon#flushed, iclass 38, count 0 2006.189.08:16:18.97#ibcon#about to write, iclass 38, count 0 2006.189.08:16:18.97#ibcon#wrote, iclass 38, count 0 2006.189.08:16:18.97#ibcon#about to read 3, iclass 38, count 0 2006.189.08:16:18.99#ibcon#read 3, iclass 38, count 0 2006.189.08:16:18.99#ibcon#about to read 4, iclass 38, count 0 2006.189.08:16:18.99#ibcon#read 4, iclass 38, count 0 2006.189.08:16:18.99#ibcon#about to read 5, iclass 38, count 0 2006.189.08:16:18.99#ibcon#read 5, iclass 38, count 0 2006.189.08:16:18.99#ibcon#about to read 6, iclass 38, count 0 2006.189.08:16:18.99#ibcon#read 6, iclass 38, count 0 2006.189.08:16:18.99#ibcon#end of sib2, iclass 38, count 0 2006.189.08:16:18.99#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:16:18.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:16:18.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:16:18.99#ibcon#*before write, iclass 38, count 0 2006.189.08:16:18.99#ibcon#enter sib2, iclass 38, count 0 2006.189.08:16:18.99#ibcon#flushed, iclass 38, count 0 2006.189.08:16:18.99#ibcon#about to write, iclass 38, count 0 2006.189.08:16:18.99#ibcon#wrote, iclass 38, count 0 2006.189.08:16:18.99#ibcon#about to read 3, iclass 38, count 0 2006.189.08:16:19.03#ibcon#read 3, iclass 38, count 0 2006.189.08:16:19.03#ibcon#about to read 4, iclass 38, count 0 2006.189.08:16:19.03#ibcon#read 4, iclass 38, count 0 2006.189.08:16:19.03#ibcon#about to read 5, iclass 38, count 0 2006.189.08:16:19.03#ibcon#read 5, iclass 38, count 0 2006.189.08:16:19.03#ibcon#about to read 6, iclass 38, count 0 2006.189.08:16:19.03#ibcon#read 6, iclass 38, count 0 2006.189.08:16:19.03#ibcon#end of sib2, iclass 38, count 0 2006.189.08:16:19.03#ibcon#*after write, iclass 38, count 0 2006.189.08:16:19.03#ibcon#*before return 0, iclass 38, count 0 2006.189.08:16:19.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:19.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:19.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:16:19.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:16:19.03$vc4f8/va=4,7 2006.189.08:16:19.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.08:16:19.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.08:16:19.03#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:19.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:19.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:19.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:19.09#ibcon#enter wrdev, iclass 40, count 2 2006.189.08:16:19.09#ibcon#first serial, iclass 40, count 2 2006.189.08:16:19.09#ibcon#enter sib2, iclass 40, count 2 2006.189.08:16:19.09#ibcon#flushed, iclass 40, count 2 2006.189.08:16:19.09#ibcon#about to write, iclass 40, count 2 2006.189.08:16:19.09#ibcon#wrote, iclass 40, count 2 2006.189.08:16:19.09#ibcon#about to read 3, iclass 40, count 2 2006.189.08:16:19.11#ibcon#read 3, iclass 40, count 2 2006.189.08:16:19.11#ibcon#about to read 4, iclass 40, count 2 2006.189.08:16:19.11#ibcon#read 4, iclass 40, count 2 2006.189.08:16:19.11#ibcon#about to read 5, iclass 40, count 2 2006.189.08:16:19.11#ibcon#read 5, iclass 40, count 2 2006.189.08:16:19.11#ibcon#about to read 6, iclass 40, count 2 2006.189.08:16:19.11#ibcon#read 6, iclass 40, count 2 2006.189.08:16:19.11#ibcon#end of sib2, iclass 40, count 2 2006.189.08:16:19.11#ibcon#*mode == 0, iclass 40, count 2 2006.189.08:16:19.11#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.08:16:19.11#ibcon#[25=AT04-07\r\n] 2006.189.08:16:19.11#ibcon#*before write, iclass 40, count 2 2006.189.08:16:19.11#ibcon#enter sib2, iclass 40, count 2 2006.189.08:16:19.11#ibcon#flushed, iclass 40, count 2 2006.189.08:16:19.11#ibcon#about to write, iclass 40, count 2 2006.189.08:16:19.11#ibcon#wrote, iclass 40, count 2 2006.189.08:16:19.11#ibcon#about to read 3, iclass 40, count 2 2006.189.08:16:19.14#ibcon#read 3, iclass 40, count 2 2006.189.08:16:19.14#ibcon#about to read 4, iclass 40, count 2 2006.189.08:16:19.14#ibcon#read 4, iclass 40, count 2 2006.189.08:16:19.14#ibcon#about to read 5, iclass 40, count 2 2006.189.08:16:19.14#ibcon#read 5, iclass 40, count 2 2006.189.08:16:19.14#ibcon#about to read 6, iclass 40, count 2 2006.189.08:16:19.14#ibcon#read 6, iclass 40, count 2 2006.189.08:16:19.14#ibcon#end of sib2, iclass 40, count 2 2006.189.08:16:19.14#ibcon#*after write, iclass 40, count 2 2006.189.08:16:19.14#ibcon#*before return 0, iclass 40, count 2 2006.189.08:16:19.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:19.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:19.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.08:16:19.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:19.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:19.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:19.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:19.26#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:16:19.26#ibcon#first serial, iclass 40, count 0 2006.189.08:16:19.26#ibcon#enter sib2, iclass 40, count 0 2006.189.08:16:19.26#ibcon#flushed, iclass 40, count 0 2006.189.08:16:19.26#ibcon#about to write, iclass 40, count 0 2006.189.08:16:19.26#ibcon#wrote, iclass 40, count 0 2006.189.08:16:19.26#ibcon#about to read 3, iclass 40, count 0 2006.189.08:16:19.28#ibcon#read 3, iclass 40, count 0 2006.189.08:16:19.28#ibcon#about to read 4, iclass 40, count 0 2006.189.08:16:19.28#ibcon#read 4, iclass 40, count 0 2006.189.08:16:19.28#ibcon#about to read 5, iclass 40, count 0 2006.189.08:16:19.28#ibcon#read 5, iclass 40, count 0 2006.189.08:16:19.28#ibcon#about to read 6, iclass 40, count 0 2006.189.08:16:19.28#ibcon#read 6, iclass 40, count 0 2006.189.08:16:19.28#ibcon#end of sib2, iclass 40, count 0 2006.189.08:16:19.28#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:16:19.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:16:19.28#ibcon#[25=USB\r\n] 2006.189.08:16:19.28#ibcon#*before write, iclass 40, count 0 2006.189.08:16:19.28#ibcon#enter sib2, iclass 40, count 0 2006.189.08:16:19.28#ibcon#flushed, iclass 40, count 0 2006.189.08:16:19.28#ibcon#about to write, iclass 40, count 0 2006.189.08:16:19.28#ibcon#wrote, iclass 40, count 0 2006.189.08:16:19.28#ibcon#about to read 3, iclass 40, count 0 2006.189.08:16:19.31#ibcon#read 3, iclass 40, count 0 2006.189.08:16:19.31#ibcon#about to read 4, iclass 40, count 0 2006.189.08:16:19.31#ibcon#read 4, iclass 40, count 0 2006.189.08:16:19.31#ibcon#about to read 5, iclass 40, count 0 2006.189.08:16:19.31#ibcon#read 5, iclass 40, count 0 2006.189.08:16:19.31#ibcon#about to read 6, iclass 40, count 0 2006.189.08:16:19.31#ibcon#read 6, iclass 40, count 0 2006.189.08:16:19.31#ibcon#end of sib2, iclass 40, count 0 2006.189.08:16:19.31#ibcon#*after write, iclass 40, count 0 2006.189.08:16:19.31#ibcon#*before return 0, iclass 40, count 0 2006.189.08:16:19.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:19.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:19.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:16:19.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:16:19.31$vc4f8/valo=5,652.99 2006.189.08:16:19.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.08:16:19.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.08:16:19.31#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:19.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:19.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:19.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:19.31#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:16:19.31#ibcon#first serial, iclass 4, count 0 2006.189.08:16:19.31#ibcon#enter sib2, iclass 4, count 0 2006.189.08:16:19.31#ibcon#flushed, iclass 4, count 0 2006.189.08:16:19.31#ibcon#about to write, iclass 4, count 0 2006.189.08:16:19.31#ibcon#wrote, iclass 4, count 0 2006.189.08:16:19.31#ibcon#about to read 3, iclass 4, count 0 2006.189.08:16:19.33#ibcon#read 3, iclass 4, count 0 2006.189.08:16:19.33#ibcon#about to read 4, iclass 4, count 0 2006.189.08:16:19.33#ibcon#read 4, iclass 4, count 0 2006.189.08:16:19.33#ibcon#about to read 5, iclass 4, count 0 2006.189.08:16:19.33#ibcon#read 5, iclass 4, count 0 2006.189.08:16:19.33#ibcon#about to read 6, iclass 4, count 0 2006.189.08:16:19.33#ibcon#read 6, iclass 4, count 0 2006.189.08:16:19.33#ibcon#end of sib2, iclass 4, count 0 2006.189.08:16:19.33#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:16:19.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:16:19.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:16:19.33#ibcon#*before write, iclass 4, count 0 2006.189.08:16:19.33#ibcon#enter sib2, iclass 4, count 0 2006.189.08:16:19.33#ibcon#flushed, iclass 4, count 0 2006.189.08:16:19.33#ibcon#about to write, iclass 4, count 0 2006.189.08:16:19.33#ibcon#wrote, iclass 4, count 0 2006.189.08:16:19.33#ibcon#about to read 3, iclass 4, count 0 2006.189.08:16:19.38#ibcon#read 3, iclass 4, count 0 2006.189.08:16:19.38#ibcon#about to read 4, iclass 4, count 0 2006.189.08:16:19.38#ibcon#read 4, iclass 4, count 0 2006.189.08:16:19.38#ibcon#about to read 5, iclass 4, count 0 2006.189.08:16:19.38#ibcon#read 5, iclass 4, count 0 2006.189.08:16:19.38#ibcon#about to read 6, iclass 4, count 0 2006.189.08:16:19.38#ibcon#read 6, iclass 4, count 0 2006.189.08:16:19.38#ibcon#end of sib2, iclass 4, count 0 2006.189.08:16:19.38#ibcon#*after write, iclass 4, count 0 2006.189.08:16:19.38#ibcon#*before return 0, iclass 4, count 0 2006.189.08:16:19.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:19.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:19.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:16:19.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:16:19.38$vc4f8/va=5,7 2006.189.08:16:19.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.08:16:19.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.08:16:19.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:19.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:19.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:19.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:19.42#ibcon#enter wrdev, iclass 6, count 2 2006.189.08:16:19.42#ibcon#first serial, iclass 6, count 2 2006.189.08:16:19.42#ibcon#enter sib2, iclass 6, count 2 2006.189.08:16:19.42#ibcon#flushed, iclass 6, count 2 2006.189.08:16:19.42#ibcon#about to write, iclass 6, count 2 2006.189.08:16:19.42#ibcon#wrote, iclass 6, count 2 2006.189.08:16:19.42#ibcon#about to read 3, iclass 6, count 2 2006.189.08:16:19.44#ibcon#read 3, iclass 6, count 2 2006.189.08:16:19.44#ibcon#about to read 4, iclass 6, count 2 2006.189.08:16:19.44#ibcon#read 4, iclass 6, count 2 2006.189.08:16:19.44#ibcon#about to read 5, iclass 6, count 2 2006.189.08:16:19.44#ibcon#read 5, iclass 6, count 2 2006.189.08:16:19.44#ibcon#about to read 6, iclass 6, count 2 2006.189.08:16:19.44#ibcon#read 6, iclass 6, count 2 2006.189.08:16:19.44#ibcon#end of sib2, iclass 6, count 2 2006.189.08:16:19.44#ibcon#*mode == 0, iclass 6, count 2 2006.189.08:16:19.44#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.08:16:19.44#ibcon#[25=AT05-07\r\n] 2006.189.08:16:19.44#ibcon#*before write, iclass 6, count 2 2006.189.08:16:19.44#ibcon#enter sib2, iclass 6, count 2 2006.189.08:16:19.44#ibcon#flushed, iclass 6, count 2 2006.189.08:16:19.44#ibcon#about to write, iclass 6, count 2 2006.189.08:16:19.44#ibcon#wrote, iclass 6, count 2 2006.189.08:16:19.44#ibcon#about to read 3, iclass 6, count 2 2006.189.08:16:19.47#ibcon#read 3, iclass 6, count 2 2006.189.08:16:19.47#ibcon#about to read 4, iclass 6, count 2 2006.189.08:16:19.47#ibcon#read 4, iclass 6, count 2 2006.189.08:16:19.47#ibcon#about to read 5, iclass 6, count 2 2006.189.08:16:19.47#ibcon#read 5, iclass 6, count 2 2006.189.08:16:19.47#ibcon#about to read 6, iclass 6, count 2 2006.189.08:16:19.47#ibcon#read 6, iclass 6, count 2 2006.189.08:16:19.47#ibcon#end of sib2, iclass 6, count 2 2006.189.08:16:19.47#ibcon#*after write, iclass 6, count 2 2006.189.08:16:19.47#ibcon#*before return 0, iclass 6, count 2 2006.189.08:16:19.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:19.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:19.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.08:16:19.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:19.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:19.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:19.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:19.59#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:16:19.59#ibcon#first serial, iclass 6, count 0 2006.189.08:16:19.59#ibcon#enter sib2, iclass 6, count 0 2006.189.08:16:19.59#ibcon#flushed, iclass 6, count 0 2006.189.08:16:19.59#ibcon#about to write, iclass 6, count 0 2006.189.08:16:19.59#ibcon#wrote, iclass 6, count 0 2006.189.08:16:19.59#ibcon#about to read 3, iclass 6, count 0 2006.189.08:16:19.61#ibcon#read 3, iclass 6, count 0 2006.189.08:16:19.61#ibcon#about to read 4, iclass 6, count 0 2006.189.08:16:19.61#ibcon#read 4, iclass 6, count 0 2006.189.08:16:19.61#ibcon#about to read 5, iclass 6, count 0 2006.189.08:16:19.61#ibcon#read 5, iclass 6, count 0 2006.189.08:16:19.61#ibcon#about to read 6, iclass 6, count 0 2006.189.08:16:19.61#ibcon#read 6, iclass 6, count 0 2006.189.08:16:19.61#ibcon#end of sib2, iclass 6, count 0 2006.189.08:16:19.61#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:16:19.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:16:19.61#ibcon#[25=USB\r\n] 2006.189.08:16:19.61#ibcon#*before write, iclass 6, count 0 2006.189.08:16:19.61#ibcon#enter sib2, iclass 6, count 0 2006.189.08:16:19.61#ibcon#flushed, iclass 6, count 0 2006.189.08:16:19.61#ibcon#about to write, iclass 6, count 0 2006.189.08:16:19.61#ibcon#wrote, iclass 6, count 0 2006.189.08:16:19.61#ibcon#about to read 3, iclass 6, count 0 2006.189.08:16:19.64#ibcon#read 3, iclass 6, count 0 2006.189.08:16:19.64#ibcon#about to read 4, iclass 6, count 0 2006.189.08:16:19.64#ibcon#read 4, iclass 6, count 0 2006.189.08:16:19.64#ibcon#about to read 5, iclass 6, count 0 2006.189.08:16:19.64#ibcon#read 5, iclass 6, count 0 2006.189.08:16:19.64#ibcon#about to read 6, iclass 6, count 0 2006.189.08:16:19.64#ibcon#read 6, iclass 6, count 0 2006.189.08:16:19.64#ibcon#end of sib2, iclass 6, count 0 2006.189.08:16:19.64#ibcon#*after write, iclass 6, count 0 2006.189.08:16:19.64#ibcon#*before return 0, iclass 6, count 0 2006.189.08:16:19.64#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:19.64#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:19.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:16:19.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:16:19.64$vc4f8/valo=6,772.99 2006.189.08:16:19.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.08:16:19.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.08:16:19.64#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:19.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:19.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:19.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:19.64#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:16:19.64#ibcon#first serial, iclass 10, count 0 2006.189.08:16:19.64#ibcon#enter sib2, iclass 10, count 0 2006.189.08:16:19.64#ibcon#flushed, iclass 10, count 0 2006.189.08:16:19.64#ibcon#about to write, iclass 10, count 0 2006.189.08:16:19.64#ibcon#wrote, iclass 10, count 0 2006.189.08:16:19.64#ibcon#about to read 3, iclass 10, count 0 2006.189.08:16:19.66#ibcon#read 3, iclass 10, count 0 2006.189.08:16:19.66#ibcon#about to read 4, iclass 10, count 0 2006.189.08:16:19.66#ibcon#read 4, iclass 10, count 0 2006.189.08:16:19.66#ibcon#about to read 5, iclass 10, count 0 2006.189.08:16:19.66#ibcon#read 5, iclass 10, count 0 2006.189.08:16:19.66#ibcon#about to read 6, iclass 10, count 0 2006.189.08:16:19.66#ibcon#read 6, iclass 10, count 0 2006.189.08:16:19.66#ibcon#end of sib2, iclass 10, count 0 2006.189.08:16:19.66#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:16:19.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:16:19.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:16:19.66#ibcon#*before write, iclass 10, count 0 2006.189.08:16:19.66#ibcon#enter sib2, iclass 10, count 0 2006.189.08:16:19.66#ibcon#flushed, iclass 10, count 0 2006.189.08:16:19.66#ibcon#about to write, iclass 10, count 0 2006.189.08:16:19.66#ibcon#wrote, iclass 10, count 0 2006.189.08:16:19.66#ibcon#about to read 3, iclass 10, count 0 2006.189.08:16:19.70#ibcon#read 3, iclass 10, count 0 2006.189.08:16:19.70#ibcon#about to read 4, iclass 10, count 0 2006.189.08:16:19.70#ibcon#read 4, iclass 10, count 0 2006.189.08:16:19.70#ibcon#about to read 5, iclass 10, count 0 2006.189.08:16:19.70#ibcon#read 5, iclass 10, count 0 2006.189.08:16:19.70#ibcon#about to read 6, iclass 10, count 0 2006.189.08:16:19.70#ibcon#read 6, iclass 10, count 0 2006.189.08:16:19.70#ibcon#end of sib2, iclass 10, count 0 2006.189.08:16:19.70#ibcon#*after write, iclass 10, count 0 2006.189.08:16:19.70#ibcon#*before return 0, iclass 10, count 0 2006.189.08:16:19.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:19.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:19.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:16:19.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:16:19.70$vc4f8/va=6,6 2006.189.08:16:19.70#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.08:16:19.70#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.08:16:19.70#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:19.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:16:19.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:16:19.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:16:19.76#ibcon#enter wrdev, iclass 12, count 2 2006.189.08:16:19.76#ibcon#first serial, iclass 12, count 2 2006.189.08:16:19.76#ibcon#enter sib2, iclass 12, count 2 2006.189.08:16:19.76#ibcon#flushed, iclass 12, count 2 2006.189.08:16:19.76#ibcon#about to write, iclass 12, count 2 2006.189.08:16:19.76#ibcon#wrote, iclass 12, count 2 2006.189.08:16:19.76#ibcon#about to read 3, iclass 12, count 2 2006.189.08:16:19.78#ibcon#read 3, iclass 12, count 2 2006.189.08:16:19.78#ibcon#about to read 4, iclass 12, count 2 2006.189.08:16:19.78#ibcon#read 4, iclass 12, count 2 2006.189.08:16:19.78#ibcon#about to read 5, iclass 12, count 2 2006.189.08:16:19.78#ibcon#read 5, iclass 12, count 2 2006.189.08:16:19.78#ibcon#about to read 6, iclass 12, count 2 2006.189.08:16:19.78#ibcon#read 6, iclass 12, count 2 2006.189.08:16:19.78#ibcon#end of sib2, iclass 12, count 2 2006.189.08:16:19.78#ibcon#*mode == 0, iclass 12, count 2 2006.189.08:16:19.78#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.08:16:19.78#ibcon#[25=AT06-06\r\n] 2006.189.08:16:19.78#ibcon#*before write, iclass 12, count 2 2006.189.08:16:19.78#ibcon#enter sib2, iclass 12, count 2 2006.189.08:16:19.78#ibcon#flushed, iclass 12, count 2 2006.189.08:16:19.78#ibcon#about to write, iclass 12, count 2 2006.189.08:16:19.78#ibcon#wrote, iclass 12, count 2 2006.189.08:16:19.78#ibcon#about to read 3, iclass 12, count 2 2006.189.08:16:19.81#ibcon#read 3, iclass 12, count 2 2006.189.08:16:19.81#ibcon#about to read 4, iclass 12, count 2 2006.189.08:16:19.81#ibcon#read 4, iclass 12, count 2 2006.189.08:16:19.81#ibcon#about to read 5, iclass 12, count 2 2006.189.08:16:19.81#ibcon#read 5, iclass 12, count 2 2006.189.08:16:19.81#ibcon#about to read 6, iclass 12, count 2 2006.189.08:16:19.81#ibcon#read 6, iclass 12, count 2 2006.189.08:16:19.81#ibcon#end of sib2, iclass 12, count 2 2006.189.08:16:19.81#ibcon#*after write, iclass 12, count 2 2006.189.08:16:19.81#ibcon#*before return 0, iclass 12, count 2 2006.189.08:16:19.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:16:19.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:16:19.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.08:16:19.81#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:19.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:16:19.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:16:19.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:16:19.93#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:16:19.93#ibcon#first serial, iclass 12, count 0 2006.189.08:16:19.93#ibcon#enter sib2, iclass 12, count 0 2006.189.08:16:19.93#ibcon#flushed, iclass 12, count 0 2006.189.08:16:19.93#ibcon#about to write, iclass 12, count 0 2006.189.08:16:19.93#ibcon#wrote, iclass 12, count 0 2006.189.08:16:19.93#ibcon#about to read 3, iclass 12, count 0 2006.189.08:16:19.95#ibcon#read 3, iclass 12, count 0 2006.189.08:16:19.95#ibcon#about to read 4, iclass 12, count 0 2006.189.08:16:19.95#ibcon#read 4, iclass 12, count 0 2006.189.08:16:19.95#ibcon#about to read 5, iclass 12, count 0 2006.189.08:16:19.95#ibcon#read 5, iclass 12, count 0 2006.189.08:16:19.95#ibcon#about to read 6, iclass 12, count 0 2006.189.08:16:19.95#ibcon#read 6, iclass 12, count 0 2006.189.08:16:19.95#ibcon#end of sib2, iclass 12, count 0 2006.189.08:16:19.95#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:16:19.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:16:19.95#ibcon#[25=USB\r\n] 2006.189.08:16:19.95#ibcon#*before write, iclass 12, count 0 2006.189.08:16:19.95#ibcon#enter sib2, iclass 12, count 0 2006.189.08:16:19.95#ibcon#flushed, iclass 12, count 0 2006.189.08:16:19.95#ibcon#about to write, iclass 12, count 0 2006.189.08:16:19.95#ibcon#wrote, iclass 12, count 0 2006.189.08:16:19.95#ibcon#about to read 3, iclass 12, count 0 2006.189.08:16:19.98#ibcon#read 3, iclass 12, count 0 2006.189.08:16:19.98#ibcon#about to read 4, iclass 12, count 0 2006.189.08:16:19.98#ibcon#read 4, iclass 12, count 0 2006.189.08:16:19.98#ibcon#about to read 5, iclass 12, count 0 2006.189.08:16:19.98#ibcon#read 5, iclass 12, count 0 2006.189.08:16:19.98#ibcon#about to read 6, iclass 12, count 0 2006.189.08:16:19.98#ibcon#read 6, iclass 12, count 0 2006.189.08:16:19.98#ibcon#end of sib2, iclass 12, count 0 2006.189.08:16:19.98#ibcon#*after write, iclass 12, count 0 2006.189.08:16:19.98#ibcon#*before return 0, iclass 12, count 0 2006.189.08:16:19.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:16:19.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:16:19.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:16:19.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:16:19.98$vc4f8/valo=7,832.99 2006.189.08:16:19.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.08:16:19.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.08:16:19.98#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:19.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:16:19.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:16:19.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:16:19.98#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:16:19.98#ibcon#first serial, iclass 14, count 0 2006.189.08:16:19.98#ibcon#enter sib2, iclass 14, count 0 2006.189.08:16:19.98#ibcon#flushed, iclass 14, count 0 2006.189.08:16:19.98#ibcon#about to write, iclass 14, count 0 2006.189.08:16:19.98#ibcon#wrote, iclass 14, count 0 2006.189.08:16:19.98#ibcon#about to read 3, iclass 14, count 0 2006.189.08:16:20.00#ibcon#read 3, iclass 14, count 0 2006.189.08:16:20.00#ibcon#about to read 4, iclass 14, count 0 2006.189.08:16:20.00#ibcon#read 4, iclass 14, count 0 2006.189.08:16:20.00#ibcon#about to read 5, iclass 14, count 0 2006.189.08:16:20.00#ibcon#read 5, iclass 14, count 0 2006.189.08:16:20.00#ibcon#about to read 6, iclass 14, count 0 2006.189.08:16:20.00#ibcon#read 6, iclass 14, count 0 2006.189.08:16:20.00#ibcon#end of sib2, iclass 14, count 0 2006.189.08:16:20.00#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:16:20.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:16:20.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:16:20.00#ibcon#*before write, iclass 14, count 0 2006.189.08:16:20.00#ibcon#enter sib2, iclass 14, count 0 2006.189.08:16:20.00#ibcon#flushed, iclass 14, count 0 2006.189.08:16:20.00#ibcon#about to write, iclass 14, count 0 2006.189.08:16:20.00#ibcon#wrote, iclass 14, count 0 2006.189.08:16:20.00#ibcon#about to read 3, iclass 14, count 0 2006.189.08:16:20.04#ibcon#read 3, iclass 14, count 0 2006.189.08:16:20.04#ibcon#about to read 4, iclass 14, count 0 2006.189.08:16:20.04#ibcon#read 4, iclass 14, count 0 2006.189.08:16:20.04#ibcon#about to read 5, iclass 14, count 0 2006.189.08:16:20.04#ibcon#read 5, iclass 14, count 0 2006.189.08:16:20.04#ibcon#about to read 6, iclass 14, count 0 2006.189.08:16:20.04#ibcon#read 6, iclass 14, count 0 2006.189.08:16:20.04#ibcon#end of sib2, iclass 14, count 0 2006.189.08:16:20.04#ibcon#*after write, iclass 14, count 0 2006.189.08:16:20.04#ibcon#*before return 0, iclass 14, count 0 2006.189.08:16:20.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:16:20.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:16:20.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:16:20.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:16:20.04$vc4f8/va=7,6 2006.189.08:16:20.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.08:16:20.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.08:16:20.04#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:20.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:16:20.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:16:20.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:16:20.10#ibcon#enter wrdev, iclass 16, count 2 2006.189.08:16:20.10#ibcon#first serial, iclass 16, count 2 2006.189.08:16:20.10#ibcon#enter sib2, iclass 16, count 2 2006.189.08:16:20.10#ibcon#flushed, iclass 16, count 2 2006.189.08:16:20.10#ibcon#about to write, iclass 16, count 2 2006.189.08:16:20.10#ibcon#wrote, iclass 16, count 2 2006.189.08:16:20.10#ibcon#about to read 3, iclass 16, count 2 2006.189.08:16:20.12#ibcon#read 3, iclass 16, count 2 2006.189.08:16:20.12#ibcon#about to read 4, iclass 16, count 2 2006.189.08:16:20.12#ibcon#read 4, iclass 16, count 2 2006.189.08:16:20.12#ibcon#about to read 5, iclass 16, count 2 2006.189.08:16:20.12#ibcon#read 5, iclass 16, count 2 2006.189.08:16:20.12#ibcon#about to read 6, iclass 16, count 2 2006.189.08:16:20.12#ibcon#read 6, iclass 16, count 2 2006.189.08:16:20.12#ibcon#end of sib2, iclass 16, count 2 2006.189.08:16:20.12#ibcon#*mode == 0, iclass 16, count 2 2006.189.08:16:20.12#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.08:16:20.12#ibcon#[25=AT07-06\r\n] 2006.189.08:16:20.12#ibcon#*before write, iclass 16, count 2 2006.189.08:16:20.12#ibcon#enter sib2, iclass 16, count 2 2006.189.08:16:20.12#ibcon#flushed, iclass 16, count 2 2006.189.08:16:20.12#ibcon#about to write, iclass 16, count 2 2006.189.08:16:20.12#ibcon#wrote, iclass 16, count 2 2006.189.08:16:20.12#ibcon#about to read 3, iclass 16, count 2 2006.189.08:16:20.15#ibcon#read 3, iclass 16, count 2 2006.189.08:16:20.15#ibcon#about to read 4, iclass 16, count 2 2006.189.08:16:20.15#ibcon#read 4, iclass 16, count 2 2006.189.08:16:20.15#ibcon#about to read 5, iclass 16, count 2 2006.189.08:16:20.15#ibcon#read 5, iclass 16, count 2 2006.189.08:16:20.15#ibcon#about to read 6, iclass 16, count 2 2006.189.08:16:20.15#ibcon#read 6, iclass 16, count 2 2006.189.08:16:20.15#ibcon#end of sib2, iclass 16, count 2 2006.189.08:16:20.15#ibcon#*after write, iclass 16, count 2 2006.189.08:16:20.15#ibcon#*before return 0, iclass 16, count 2 2006.189.08:16:20.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:16:20.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:16:20.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.08:16:20.15#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:20.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:16:20.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:16:20.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:16:20.27#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:16:20.27#ibcon#first serial, iclass 16, count 0 2006.189.08:16:20.27#ibcon#enter sib2, iclass 16, count 0 2006.189.08:16:20.27#ibcon#flushed, iclass 16, count 0 2006.189.08:16:20.27#ibcon#about to write, iclass 16, count 0 2006.189.08:16:20.27#ibcon#wrote, iclass 16, count 0 2006.189.08:16:20.27#ibcon#about to read 3, iclass 16, count 0 2006.189.08:16:20.29#ibcon#read 3, iclass 16, count 0 2006.189.08:16:20.29#ibcon#about to read 4, iclass 16, count 0 2006.189.08:16:20.29#ibcon#read 4, iclass 16, count 0 2006.189.08:16:20.29#ibcon#about to read 5, iclass 16, count 0 2006.189.08:16:20.29#ibcon#read 5, iclass 16, count 0 2006.189.08:16:20.29#ibcon#about to read 6, iclass 16, count 0 2006.189.08:16:20.29#ibcon#read 6, iclass 16, count 0 2006.189.08:16:20.29#ibcon#end of sib2, iclass 16, count 0 2006.189.08:16:20.29#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:16:20.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:16:20.29#ibcon#[25=USB\r\n] 2006.189.08:16:20.29#ibcon#*before write, iclass 16, count 0 2006.189.08:16:20.29#ibcon#enter sib2, iclass 16, count 0 2006.189.08:16:20.29#ibcon#flushed, iclass 16, count 0 2006.189.08:16:20.29#ibcon#about to write, iclass 16, count 0 2006.189.08:16:20.29#ibcon#wrote, iclass 16, count 0 2006.189.08:16:20.29#ibcon#about to read 3, iclass 16, count 0 2006.189.08:16:20.32#ibcon#read 3, iclass 16, count 0 2006.189.08:16:20.32#ibcon#about to read 4, iclass 16, count 0 2006.189.08:16:20.32#ibcon#read 4, iclass 16, count 0 2006.189.08:16:20.32#ibcon#about to read 5, iclass 16, count 0 2006.189.08:16:20.32#ibcon#read 5, iclass 16, count 0 2006.189.08:16:20.32#ibcon#about to read 6, iclass 16, count 0 2006.189.08:16:20.32#ibcon#read 6, iclass 16, count 0 2006.189.08:16:20.32#ibcon#end of sib2, iclass 16, count 0 2006.189.08:16:20.32#ibcon#*after write, iclass 16, count 0 2006.189.08:16:20.32#ibcon#*before return 0, iclass 16, count 0 2006.189.08:16:20.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:16:20.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:16:20.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:16:20.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:16:20.32$vc4f8/valo=8,852.99 2006.189.08:16:20.32#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.08:16:20.32#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.08:16:20.32#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:20.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:16:20.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:16:20.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:16:20.32#ibcon#enter wrdev, iclass 18, count 0 2006.189.08:16:20.32#ibcon#first serial, iclass 18, count 0 2006.189.08:16:20.32#ibcon#enter sib2, iclass 18, count 0 2006.189.08:16:20.32#ibcon#flushed, iclass 18, count 0 2006.189.08:16:20.32#ibcon#about to write, iclass 18, count 0 2006.189.08:16:20.32#ibcon#wrote, iclass 18, count 0 2006.189.08:16:20.32#ibcon#about to read 3, iclass 18, count 0 2006.189.08:16:20.34#ibcon#read 3, iclass 18, count 0 2006.189.08:16:20.34#ibcon#about to read 4, iclass 18, count 0 2006.189.08:16:20.34#ibcon#read 4, iclass 18, count 0 2006.189.08:16:20.34#ibcon#about to read 5, iclass 18, count 0 2006.189.08:16:20.34#ibcon#read 5, iclass 18, count 0 2006.189.08:16:20.34#ibcon#about to read 6, iclass 18, count 0 2006.189.08:16:20.34#ibcon#read 6, iclass 18, count 0 2006.189.08:16:20.34#ibcon#end of sib2, iclass 18, count 0 2006.189.08:16:20.34#ibcon#*mode == 0, iclass 18, count 0 2006.189.08:16:20.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.08:16:20.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:16:20.34#ibcon#*before write, iclass 18, count 0 2006.189.08:16:20.34#ibcon#enter sib2, iclass 18, count 0 2006.189.08:16:20.34#ibcon#flushed, iclass 18, count 0 2006.189.08:16:20.34#ibcon#about to write, iclass 18, count 0 2006.189.08:16:20.34#ibcon#wrote, iclass 18, count 0 2006.189.08:16:20.34#ibcon#about to read 3, iclass 18, count 0 2006.189.08:16:20.38#ibcon#read 3, iclass 18, count 0 2006.189.08:16:20.38#ibcon#about to read 4, iclass 18, count 0 2006.189.08:16:20.38#ibcon#read 4, iclass 18, count 0 2006.189.08:16:20.38#ibcon#about to read 5, iclass 18, count 0 2006.189.08:16:20.38#ibcon#read 5, iclass 18, count 0 2006.189.08:16:20.38#ibcon#about to read 6, iclass 18, count 0 2006.189.08:16:20.38#ibcon#read 6, iclass 18, count 0 2006.189.08:16:20.38#ibcon#end of sib2, iclass 18, count 0 2006.189.08:16:20.38#ibcon#*after write, iclass 18, count 0 2006.189.08:16:20.38#ibcon#*before return 0, iclass 18, count 0 2006.189.08:16:20.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:16:20.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:16:20.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.08:16:20.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.08:16:20.38$vc4f8/va=8,6 2006.189.08:16:20.38#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.08:16:20.38#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.08:16:20.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:20.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:16:20.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:16:20.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:16:20.44#ibcon#enter wrdev, iclass 20, count 2 2006.189.08:16:20.44#ibcon#first serial, iclass 20, count 2 2006.189.08:16:20.44#ibcon#enter sib2, iclass 20, count 2 2006.189.08:16:20.44#ibcon#flushed, iclass 20, count 2 2006.189.08:16:20.44#ibcon#about to write, iclass 20, count 2 2006.189.08:16:20.44#ibcon#wrote, iclass 20, count 2 2006.189.08:16:20.44#ibcon#about to read 3, iclass 20, count 2 2006.189.08:16:20.46#ibcon#read 3, iclass 20, count 2 2006.189.08:16:20.46#ibcon#about to read 4, iclass 20, count 2 2006.189.08:16:20.46#ibcon#read 4, iclass 20, count 2 2006.189.08:16:20.46#ibcon#about to read 5, iclass 20, count 2 2006.189.08:16:20.46#ibcon#read 5, iclass 20, count 2 2006.189.08:16:20.46#ibcon#about to read 6, iclass 20, count 2 2006.189.08:16:20.46#ibcon#read 6, iclass 20, count 2 2006.189.08:16:20.46#ibcon#end of sib2, iclass 20, count 2 2006.189.08:16:20.46#ibcon#*mode == 0, iclass 20, count 2 2006.189.08:16:20.46#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.08:16:20.46#ibcon#[25=AT08-06\r\n] 2006.189.08:16:20.46#ibcon#*before write, iclass 20, count 2 2006.189.08:16:20.46#ibcon#enter sib2, iclass 20, count 2 2006.189.08:16:20.46#ibcon#flushed, iclass 20, count 2 2006.189.08:16:20.46#ibcon#about to write, iclass 20, count 2 2006.189.08:16:20.46#ibcon#wrote, iclass 20, count 2 2006.189.08:16:20.46#ibcon#about to read 3, iclass 20, count 2 2006.189.08:16:20.49#ibcon#read 3, iclass 20, count 2 2006.189.08:16:20.49#ibcon#about to read 4, iclass 20, count 2 2006.189.08:16:20.49#ibcon#read 4, iclass 20, count 2 2006.189.08:16:20.49#ibcon#about to read 5, iclass 20, count 2 2006.189.08:16:20.49#ibcon#read 5, iclass 20, count 2 2006.189.08:16:20.49#ibcon#about to read 6, iclass 20, count 2 2006.189.08:16:20.49#ibcon#read 6, iclass 20, count 2 2006.189.08:16:20.49#ibcon#end of sib2, iclass 20, count 2 2006.189.08:16:20.49#ibcon#*after write, iclass 20, count 2 2006.189.08:16:20.49#ibcon#*before return 0, iclass 20, count 2 2006.189.08:16:20.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:16:20.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:16:20.49#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.08:16:20.49#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:20.49#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:16:20.61#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:16:20.61#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:16:20.61#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:16:20.61#ibcon#first serial, iclass 20, count 0 2006.189.08:16:20.61#ibcon#enter sib2, iclass 20, count 0 2006.189.08:16:20.61#ibcon#flushed, iclass 20, count 0 2006.189.08:16:20.61#ibcon#about to write, iclass 20, count 0 2006.189.08:16:20.61#ibcon#wrote, iclass 20, count 0 2006.189.08:16:20.61#ibcon#about to read 3, iclass 20, count 0 2006.189.08:16:20.63#ibcon#read 3, iclass 20, count 0 2006.189.08:16:20.63#ibcon#about to read 4, iclass 20, count 0 2006.189.08:16:20.63#ibcon#read 4, iclass 20, count 0 2006.189.08:16:20.63#ibcon#about to read 5, iclass 20, count 0 2006.189.08:16:20.63#ibcon#read 5, iclass 20, count 0 2006.189.08:16:20.63#ibcon#about to read 6, iclass 20, count 0 2006.189.08:16:20.63#ibcon#read 6, iclass 20, count 0 2006.189.08:16:20.63#ibcon#end of sib2, iclass 20, count 0 2006.189.08:16:20.63#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:16:20.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:16:20.63#ibcon#[25=USB\r\n] 2006.189.08:16:20.63#ibcon#*before write, iclass 20, count 0 2006.189.08:16:20.63#ibcon#enter sib2, iclass 20, count 0 2006.189.08:16:20.63#ibcon#flushed, iclass 20, count 0 2006.189.08:16:20.63#ibcon#about to write, iclass 20, count 0 2006.189.08:16:20.63#ibcon#wrote, iclass 20, count 0 2006.189.08:16:20.63#ibcon#about to read 3, iclass 20, count 0 2006.189.08:16:20.66#ibcon#read 3, iclass 20, count 0 2006.189.08:16:20.66#ibcon#about to read 4, iclass 20, count 0 2006.189.08:16:20.66#ibcon#read 4, iclass 20, count 0 2006.189.08:16:20.66#ibcon#about to read 5, iclass 20, count 0 2006.189.08:16:20.66#ibcon#read 5, iclass 20, count 0 2006.189.08:16:20.66#ibcon#about to read 6, iclass 20, count 0 2006.189.08:16:20.66#ibcon#read 6, iclass 20, count 0 2006.189.08:16:20.66#ibcon#end of sib2, iclass 20, count 0 2006.189.08:16:20.66#ibcon#*after write, iclass 20, count 0 2006.189.08:16:20.66#ibcon#*before return 0, iclass 20, count 0 2006.189.08:16:20.66#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:16:20.66#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:16:20.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:16:20.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:16:20.66$vc4f8/vblo=1,632.99 2006.189.08:16:20.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.08:16:20.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.08:16:20.66#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:20.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:16:20.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:16:20.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:16:20.66#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:16:20.66#ibcon#first serial, iclass 22, count 0 2006.189.08:16:20.66#ibcon#enter sib2, iclass 22, count 0 2006.189.08:16:20.66#ibcon#flushed, iclass 22, count 0 2006.189.08:16:20.66#ibcon#about to write, iclass 22, count 0 2006.189.08:16:20.66#ibcon#wrote, iclass 22, count 0 2006.189.08:16:20.66#ibcon#about to read 3, iclass 22, count 0 2006.189.08:16:20.68#ibcon#read 3, iclass 22, count 0 2006.189.08:16:20.68#ibcon#about to read 4, iclass 22, count 0 2006.189.08:16:20.68#ibcon#read 4, iclass 22, count 0 2006.189.08:16:20.68#ibcon#about to read 5, iclass 22, count 0 2006.189.08:16:20.68#ibcon#read 5, iclass 22, count 0 2006.189.08:16:20.68#ibcon#about to read 6, iclass 22, count 0 2006.189.08:16:20.68#ibcon#read 6, iclass 22, count 0 2006.189.08:16:20.68#ibcon#end of sib2, iclass 22, count 0 2006.189.08:16:20.68#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:16:20.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:16:20.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:16:20.68#ibcon#*before write, iclass 22, count 0 2006.189.08:16:20.68#ibcon#enter sib2, iclass 22, count 0 2006.189.08:16:20.68#ibcon#flushed, iclass 22, count 0 2006.189.08:16:20.68#ibcon#about to write, iclass 22, count 0 2006.189.08:16:20.68#ibcon#wrote, iclass 22, count 0 2006.189.08:16:20.68#ibcon#about to read 3, iclass 22, count 0 2006.189.08:16:20.72#ibcon#read 3, iclass 22, count 0 2006.189.08:16:20.72#ibcon#about to read 4, iclass 22, count 0 2006.189.08:16:20.72#ibcon#read 4, iclass 22, count 0 2006.189.08:16:20.72#ibcon#about to read 5, iclass 22, count 0 2006.189.08:16:20.72#ibcon#read 5, iclass 22, count 0 2006.189.08:16:20.72#ibcon#about to read 6, iclass 22, count 0 2006.189.08:16:20.72#ibcon#read 6, iclass 22, count 0 2006.189.08:16:20.72#ibcon#end of sib2, iclass 22, count 0 2006.189.08:16:20.72#ibcon#*after write, iclass 22, count 0 2006.189.08:16:20.72#ibcon#*before return 0, iclass 22, count 0 2006.189.08:16:20.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:16:20.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:16:20.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:16:20.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:16:20.72$vc4f8/vb=1,4 2006.189.08:16:20.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.08:16:20.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.08:16:20.72#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:20.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:16:20.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:16:20.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:16:20.72#ibcon#enter wrdev, iclass 24, count 2 2006.189.08:16:20.72#ibcon#first serial, iclass 24, count 2 2006.189.08:16:20.72#ibcon#enter sib2, iclass 24, count 2 2006.189.08:16:20.72#ibcon#flushed, iclass 24, count 2 2006.189.08:16:20.72#ibcon#about to write, iclass 24, count 2 2006.189.08:16:20.72#ibcon#wrote, iclass 24, count 2 2006.189.08:16:20.72#ibcon#about to read 3, iclass 24, count 2 2006.189.08:16:20.74#ibcon#read 3, iclass 24, count 2 2006.189.08:16:20.74#ibcon#about to read 4, iclass 24, count 2 2006.189.08:16:20.74#ibcon#read 4, iclass 24, count 2 2006.189.08:16:20.74#ibcon#about to read 5, iclass 24, count 2 2006.189.08:16:20.74#ibcon#read 5, iclass 24, count 2 2006.189.08:16:20.74#ibcon#about to read 6, iclass 24, count 2 2006.189.08:16:20.74#ibcon#read 6, iclass 24, count 2 2006.189.08:16:20.74#ibcon#end of sib2, iclass 24, count 2 2006.189.08:16:20.74#ibcon#*mode == 0, iclass 24, count 2 2006.189.08:16:20.74#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.08:16:20.74#ibcon#[27=AT01-04\r\n] 2006.189.08:16:20.74#ibcon#*before write, iclass 24, count 2 2006.189.08:16:20.74#ibcon#enter sib2, iclass 24, count 2 2006.189.08:16:20.74#ibcon#flushed, iclass 24, count 2 2006.189.08:16:20.74#ibcon#about to write, iclass 24, count 2 2006.189.08:16:20.74#ibcon#wrote, iclass 24, count 2 2006.189.08:16:20.74#ibcon#about to read 3, iclass 24, count 2 2006.189.08:16:20.77#ibcon#read 3, iclass 24, count 2 2006.189.08:16:20.77#ibcon#about to read 4, iclass 24, count 2 2006.189.08:16:20.77#ibcon#read 4, iclass 24, count 2 2006.189.08:16:20.77#ibcon#about to read 5, iclass 24, count 2 2006.189.08:16:20.77#ibcon#read 5, iclass 24, count 2 2006.189.08:16:20.77#ibcon#about to read 6, iclass 24, count 2 2006.189.08:16:20.77#ibcon#read 6, iclass 24, count 2 2006.189.08:16:20.77#ibcon#end of sib2, iclass 24, count 2 2006.189.08:16:20.77#ibcon#*after write, iclass 24, count 2 2006.189.08:16:20.77#ibcon#*before return 0, iclass 24, count 2 2006.189.08:16:20.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:16:20.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:16:20.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.08:16:20.77#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:20.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:16:20.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:16:20.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:16:20.89#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:16:20.89#ibcon#first serial, iclass 24, count 0 2006.189.08:16:20.89#ibcon#enter sib2, iclass 24, count 0 2006.189.08:16:20.89#ibcon#flushed, iclass 24, count 0 2006.189.08:16:20.89#ibcon#about to write, iclass 24, count 0 2006.189.08:16:20.89#ibcon#wrote, iclass 24, count 0 2006.189.08:16:20.89#ibcon#about to read 3, iclass 24, count 0 2006.189.08:16:20.91#ibcon#read 3, iclass 24, count 0 2006.189.08:16:20.91#ibcon#about to read 4, iclass 24, count 0 2006.189.08:16:20.91#ibcon#read 4, iclass 24, count 0 2006.189.08:16:20.91#ibcon#about to read 5, iclass 24, count 0 2006.189.08:16:20.91#ibcon#read 5, iclass 24, count 0 2006.189.08:16:20.91#ibcon#about to read 6, iclass 24, count 0 2006.189.08:16:20.91#ibcon#read 6, iclass 24, count 0 2006.189.08:16:20.91#ibcon#end of sib2, iclass 24, count 0 2006.189.08:16:20.91#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:16:20.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:16:20.91#ibcon#[27=USB\r\n] 2006.189.08:16:20.91#ibcon#*before write, iclass 24, count 0 2006.189.08:16:20.91#ibcon#enter sib2, iclass 24, count 0 2006.189.08:16:20.91#ibcon#flushed, iclass 24, count 0 2006.189.08:16:20.91#ibcon#about to write, iclass 24, count 0 2006.189.08:16:20.91#ibcon#wrote, iclass 24, count 0 2006.189.08:16:20.91#ibcon#about to read 3, iclass 24, count 0 2006.189.08:16:20.94#ibcon#read 3, iclass 24, count 0 2006.189.08:16:20.94#ibcon#about to read 4, iclass 24, count 0 2006.189.08:16:20.94#ibcon#read 4, iclass 24, count 0 2006.189.08:16:20.94#ibcon#about to read 5, iclass 24, count 0 2006.189.08:16:20.94#ibcon#read 5, iclass 24, count 0 2006.189.08:16:20.94#ibcon#about to read 6, iclass 24, count 0 2006.189.08:16:20.94#ibcon#read 6, iclass 24, count 0 2006.189.08:16:20.94#ibcon#end of sib2, iclass 24, count 0 2006.189.08:16:20.94#ibcon#*after write, iclass 24, count 0 2006.189.08:16:20.94#ibcon#*before return 0, iclass 24, count 0 2006.189.08:16:20.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:16:20.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:16:20.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:16:20.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:16:20.94$vc4f8/vblo=2,640.99 2006.189.08:16:20.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.08:16:20.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.08:16:20.94#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:20.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:20.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:20.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:20.94#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:16:20.94#ibcon#first serial, iclass 26, count 0 2006.189.08:16:20.94#ibcon#enter sib2, iclass 26, count 0 2006.189.08:16:20.94#ibcon#flushed, iclass 26, count 0 2006.189.08:16:20.94#ibcon#about to write, iclass 26, count 0 2006.189.08:16:20.94#ibcon#wrote, iclass 26, count 0 2006.189.08:16:20.94#ibcon#about to read 3, iclass 26, count 0 2006.189.08:16:20.96#ibcon#read 3, iclass 26, count 0 2006.189.08:16:20.96#ibcon#about to read 4, iclass 26, count 0 2006.189.08:16:20.96#ibcon#read 4, iclass 26, count 0 2006.189.08:16:20.96#ibcon#about to read 5, iclass 26, count 0 2006.189.08:16:20.96#ibcon#read 5, iclass 26, count 0 2006.189.08:16:20.96#ibcon#about to read 6, iclass 26, count 0 2006.189.08:16:20.96#ibcon#read 6, iclass 26, count 0 2006.189.08:16:20.96#ibcon#end of sib2, iclass 26, count 0 2006.189.08:16:20.96#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:16:20.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:16:20.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:16:20.96#ibcon#*before write, iclass 26, count 0 2006.189.08:16:20.96#ibcon#enter sib2, iclass 26, count 0 2006.189.08:16:20.96#ibcon#flushed, iclass 26, count 0 2006.189.08:16:20.96#ibcon#about to write, iclass 26, count 0 2006.189.08:16:20.96#ibcon#wrote, iclass 26, count 0 2006.189.08:16:20.96#ibcon#about to read 3, iclass 26, count 0 2006.189.08:16:21.00#ibcon#read 3, iclass 26, count 0 2006.189.08:16:21.00#ibcon#about to read 4, iclass 26, count 0 2006.189.08:16:21.00#ibcon#read 4, iclass 26, count 0 2006.189.08:16:21.00#ibcon#about to read 5, iclass 26, count 0 2006.189.08:16:21.00#ibcon#read 5, iclass 26, count 0 2006.189.08:16:21.00#ibcon#about to read 6, iclass 26, count 0 2006.189.08:16:21.00#ibcon#read 6, iclass 26, count 0 2006.189.08:16:21.00#ibcon#end of sib2, iclass 26, count 0 2006.189.08:16:21.00#ibcon#*after write, iclass 26, count 0 2006.189.08:16:21.00#ibcon#*before return 0, iclass 26, count 0 2006.189.08:16:21.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:21.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:16:21.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:16:21.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:16:21.00$vc4f8/vb=2,4 2006.189.08:16:21.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.08:16:21.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.08:16:21.00#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:21.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:21.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:21.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:21.06#ibcon#enter wrdev, iclass 28, count 2 2006.189.08:16:21.06#ibcon#first serial, iclass 28, count 2 2006.189.08:16:21.06#ibcon#enter sib2, iclass 28, count 2 2006.189.08:16:21.06#ibcon#flushed, iclass 28, count 2 2006.189.08:16:21.06#ibcon#about to write, iclass 28, count 2 2006.189.08:16:21.06#ibcon#wrote, iclass 28, count 2 2006.189.08:16:21.06#ibcon#about to read 3, iclass 28, count 2 2006.189.08:16:21.08#ibcon#read 3, iclass 28, count 2 2006.189.08:16:21.08#ibcon#about to read 4, iclass 28, count 2 2006.189.08:16:21.08#ibcon#read 4, iclass 28, count 2 2006.189.08:16:21.08#ibcon#about to read 5, iclass 28, count 2 2006.189.08:16:21.08#ibcon#read 5, iclass 28, count 2 2006.189.08:16:21.08#ibcon#about to read 6, iclass 28, count 2 2006.189.08:16:21.08#ibcon#read 6, iclass 28, count 2 2006.189.08:16:21.08#ibcon#end of sib2, iclass 28, count 2 2006.189.08:16:21.08#ibcon#*mode == 0, iclass 28, count 2 2006.189.08:16:21.08#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.08:16:21.08#ibcon#[27=AT02-04\r\n] 2006.189.08:16:21.08#ibcon#*before write, iclass 28, count 2 2006.189.08:16:21.08#ibcon#enter sib2, iclass 28, count 2 2006.189.08:16:21.08#ibcon#flushed, iclass 28, count 2 2006.189.08:16:21.08#ibcon#about to write, iclass 28, count 2 2006.189.08:16:21.08#ibcon#wrote, iclass 28, count 2 2006.189.08:16:21.08#ibcon#about to read 3, iclass 28, count 2 2006.189.08:16:21.11#ibcon#read 3, iclass 28, count 2 2006.189.08:16:21.11#ibcon#about to read 4, iclass 28, count 2 2006.189.08:16:21.11#ibcon#read 4, iclass 28, count 2 2006.189.08:16:21.11#ibcon#about to read 5, iclass 28, count 2 2006.189.08:16:21.11#ibcon#read 5, iclass 28, count 2 2006.189.08:16:21.11#ibcon#about to read 6, iclass 28, count 2 2006.189.08:16:21.11#ibcon#read 6, iclass 28, count 2 2006.189.08:16:21.11#ibcon#end of sib2, iclass 28, count 2 2006.189.08:16:21.11#ibcon#*after write, iclass 28, count 2 2006.189.08:16:21.11#ibcon#*before return 0, iclass 28, count 2 2006.189.08:16:21.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:21.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:16:21.11#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.08:16:21.11#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:21.11#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:21.23#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:21.23#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:21.23#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:16:21.23#ibcon#first serial, iclass 28, count 0 2006.189.08:16:21.23#ibcon#enter sib2, iclass 28, count 0 2006.189.08:16:21.23#ibcon#flushed, iclass 28, count 0 2006.189.08:16:21.23#ibcon#about to write, iclass 28, count 0 2006.189.08:16:21.23#ibcon#wrote, iclass 28, count 0 2006.189.08:16:21.23#ibcon#about to read 3, iclass 28, count 0 2006.189.08:16:21.25#ibcon#read 3, iclass 28, count 0 2006.189.08:16:21.25#ibcon#about to read 4, iclass 28, count 0 2006.189.08:16:21.25#ibcon#read 4, iclass 28, count 0 2006.189.08:16:21.25#ibcon#about to read 5, iclass 28, count 0 2006.189.08:16:21.25#ibcon#read 5, iclass 28, count 0 2006.189.08:16:21.25#ibcon#about to read 6, iclass 28, count 0 2006.189.08:16:21.25#ibcon#read 6, iclass 28, count 0 2006.189.08:16:21.25#ibcon#end of sib2, iclass 28, count 0 2006.189.08:16:21.25#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:16:21.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:16:21.25#ibcon#[27=USB\r\n] 2006.189.08:16:21.25#ibcon#*before write, iclass 28, count 0 2006.189.08:16:21.25#ibcon#enter sib2, iclass 28, count 0 2006.189.08:16:21.25#ibcon#flushed, iclass 28, count 0 2006.189.08:16:21.25#ibcon#about to write, iclass 28, count 0 2006.189.08:16:21.25#ibcon#wrote, iclass 28, count 0 2006.189.08:16:21.25#ibcon#about to read 3, iclass 28, count 0 2006.189.08:16:21.28#ibcon#read 3, iclass 28, count 0 2006.189.08:16:21.28#ibcon#about to read 4, iclass 28, count 0 2006.189.08:16:21.28#ibcon#read 4, iclass 28, count 0 2006.189.08:16:21.28#ibcon#about to read 5, iclass 28, count 0 2006.189.08:16:21.28#ibcon#read 5, iclass 28, count 0 2006.189.08:16:21.28#ibcon#about to read 6, iclass 28, count 0 2006.189.08:16:21.28#ibcon#read 6, iclass 28, count 0 2006.189.08:16:21.28#ibcon#end of sib2, iclass 28, count 0 2006.189.08:16:21.28#ibcon#*after write, iclass 28, count 0 2006.189.08:16:21.28#ibcon#*before return 0, iclass 28, count 0 2006.189.08:16:21.28#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:21.28#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:16:21.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:16:21.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:16:21.28$vc4f8/vblo=3,656.99 2006.189.08:16:21.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.08:16:21.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.08:16:21.28#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:21.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:21.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:21.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:21.28#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:16:21.28#ibcon#first serial, iclass 30, count 0 2006.189.08:16:21.28#ibcon#enter sib2, iclass 30, count 0 2006.189.08:16:21.28#ibcon#flushed, iclass 30, count 0 2006.189.08:16:21.28#ibcon#about to write, iclass 30, count 0 2006.189.08:16:21.28#ibcon#wrote, iclass 30, count 0 2006.189.08:16:21.28#ibcon#about to read 3, iclass 30, count 0 2006.189.08:16:21.30#ibcon#read 3, iclass 30, count 0 2006.189.08:16:21.30#ibcon#about to read 4, iclass 30, count 0 2006.189.08:16:21.30#ibcon#read 4, iclass 30, count 0 2006.189.08:16:21.30#ibcon#about to read 5, iclass 30, count 0 2006.189.08:16:21.30#ibcon#read 5, iclass 30, count 0 2006.189.08:16:21.30#ibcon#about to read 6, iclass 30, count 0 2006.189.08:16:21.30#ibcon#read 6, iclass 30, count 0 2006.189.08:16:21.30#ibcon#end of sib2, iclass 30, count 0 2006.189.08:16:21.30#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:16:21.30#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:16:21.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:16:21.30#ibcon#*before write, iclass 30, count 0 2006.189.08:16:21.30#ibcon#enter sib2, iclass 30, count 0 2006.189.08:16:21.30#ibcon#flushed, iclass 30, count 0 2006.189.08:16:21.30#ibcon#about to write, iclass 30, count 0 2006.189.08:16:21.30#ibcon#wrote, iclass 30, count 0 2006.189.08:16:21.30#ibcon#about to read 3, iclass 30, count 0 2006.189.08:16:21.34#ibcon#read 3, iclass 30, count 0 2006.189.08:16:21.34#ibcon#about to read 4, iclass 30, count 0 2006.189.08:16:21.34#ibcon#read 4, iclass 30, count 0 2006.189.08:16:21.34#ibcon#about to read 5, iclass 30, count 0 2006.189.08:16:21.34#ibcon#read 5, iclass 30, count 0 2006.189.08:16:21.34#ibcon#about to read 6, iclass 30, count 0 2006.189.08:16:21.34#ibcon#read 6, iclass 30, count 0 2006.189.08:16:21.34#ibcon#end of sib2, iclass 30, count 0 2006.189.08:16:21.34#ibcon#*after write, iclass 30, count 0 2006.189.08:16:21.34#ibcon#*before return 0, iclass 30, count 0 2006.189.08:16:21.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:21.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:16:21.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:16:21.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:16:21.34$vc4f8/vb=3,4 2006.189.08:16:21.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.08:16:21.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.08:16:21.34#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:21.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:21.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:21.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:21.40#ibcon#enter wrdev, iclass 32, count 2 2006.189.08:16:21.40#ibcon#first serial, iclass 32, count 2 2006.189.08:16:21.40#ibcon#enter sib2, iclass 32, count 2 2006.189.08:16:21.40#ibcon#flushed, iclass 32, count 2 2006.189.08:16:21.40#ibcon#about to write, iclass 32, count 2 2006.189.08:16:21.40#ibcon#wrote, iclass 32, count 2 2006.189.08:16:21.40#ibcon#about to read 3, iclass 32, count 2 2006.189.08:16:21.42#ibcon#read 3, iclass 32, count 2 2006.189.08:16:21.42#ibcon#about to read 4, iclass 32, count 2 2006.189.08:16:21.42#ibcon#read 4, iclass 32, count 2 2006.189.08:16:21.42#ibcon#about to read 5, iclass 32, count 2 2006.189.08:16:21.42#ibcon#read 5, iclass 32, count 2 2006.189.08:16:21.42#ibcon#about to read 6, iclass 32, count 2 2006.189.08:16:21.42#ibcon#read 6, iclass 32, count 2 2006.189.08:16:21.42#ibcon#end of sib2, iclass 32, count 2 2006.189.08:16:21.42#ibcon#*mode == 0, iclass 32, count 2 2006.189.08:16:21.42#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.08:16:21.42#ibcon#[27=AT03-04\r\n] 2006.189.08:16:21.42#ibcon#*before write, iclass 32, count 2 2006.189.08:16:21.42#ibcon#enter sib2, iclass 32, count 2 2006.189.08:16:21.42#ibcon#flushed, iclass 32, count 2 2006.189.08:16:21.42#ibcon#about to write, iclass 32, count 2 2006.189.08:16:21.42#ibcon#wrote, iclass 32, count 2 2006.189.08:16:21.42#ibcon#about to read 3, iclass 32, count 2 2006.189.08:16:21.45#ibcon#read 3, iclass 32, count 2 2006.189.08:16:21.45#ibcon#about to read 4, iclass 32, count 2 2006.189.08:16:21.45#ibcon#read 4, iclass 32, count 2 2006.189.08:16:21.45#ibcon#about to read 5, iclass 32, count 2 2006.189.08:16:21.45#ibcon#read 5, iclass 32, count 2 2006.189.08:16:21.45#ibcon#about to read 6, iclass 32, count 2 2006.189.08:16:21.45#ibcon#read 6, iclass 32, count 2 2006.189.08:16:21.45#ibcon#end of sib2, iclass 32, count 2 2006.189.08:16:21.45#ibcon#*after write, iclass 32, count 2 2006.189.08:16:21.45#ibcon#*before return 0, iclass 32, count 2 2006.189.08:16:21.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:21.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:16:21.45#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.08:16:21.45#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:21.45#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:21.57#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:21.57#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:21.57#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:16:21.57#ibcon#first serial, iclass 32, count 0 2006.189.08:16:21.57#ibcon#enter sib2, iclass 32, count 0 2006.189.08:16:21.57#ibcon#flushed, iclass 32, count 0 2006.189.08:16:21.57#ibcon#about to write, iclass 32, count 0 2006.189.08:16:21.57#ibcon#wrote, iclass 32, count 0 2006.189.08:16:21.57#ibcon#about to read 3, iclass 32, count 0 2006.189.08:16:21.59#ibcon#read 3, iclass 32, count 0 2006.189.08:16:21.59#ibcon#about to read 4, iclass 32, count 0 2006.189.08:16:21.59#ibcon#read 4, iclass 32, count 0 2006.189.08:16:21.59#ibcon#about to read 5, iclass 32, count 0 2006.189.08:16:21.59#ibcon#read 5, iclass 32, count 0 2006.189.08:16:21.59#ibcon#about to read 6, iclass 32, count 0 2006.189.08:16:21.59#ibcon#read 6, iclass 32, count 0 2006.189.08:16:21.59#ibcon#end of sib2, iclass 32, count 0 2006.189.08:16:21.59#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:16:21.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:16:21.59#ibcon#[27=USB\r\n] 2006.189.08:16:21.59#ibcon#*before write, iclass 32, count 0 2006.189.08:16:21.59#ibcon#enter sib2, iclass 32, count 0 2006.189.08:16:21.59#ibcon#flushed, iclass 32, count 0 2006.189.08:16:21.59#ibcon#about to write, iclass 32, count 0 2006.189.08:16:21.59#ibcon#wrote, iclass 32, count 0 2006.189.08:16:21.59#ibcon#about to read 3, iclass 32, count 0 2006.189.08:16:21.62#ibcon#read 3, iclass 32, count 0 2006.189.08:16:21.62#ibcon#about to read 4, iclass 32, count 0 2006.189.08:16:21.62#ibcon#read 4, iclass 32, count 0 2006.189.08:16:21.62#ibcon#about to read 5, iclass 32, count 0 2006.189.08:16:21.62#ibcon#read 5, iclass 32, count 0 2006.189.08:16:21.62#ibcon#about to read 6, iclass 32, count 0 2006.189.08:16:21.62#ibcon#read 6, iclass 32, count 0 2006.189.08:16:21.62#ibcon#end of sib2, iclass 32, count 0 2006.189.08:16:21.62#ibcon#*after write, iclass 32, count 0 2006.189.08:16:21.62#ibcon#*before return 0, iclass 32, count 0 2006.189.08:16:21.62#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:21.62#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:16:21.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:16:21.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:16:21.62$vc4f8/vblo=4,712.99 2006.189.08:16:21.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.08:16:21.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.08:16:21.62#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:21.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:21.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:21.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:21.62#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:16:21.62#ibcon#first serial, iclass 34, count 0 2006.189.08:16:21.62#ibcon#enter sib2, iclass 34, count 0 2006.189.08:16:21.62#ibcon#flushed, iclass 34, count 0 2006.189.08:16:21.62#ibcon#about to write, iclass 34, count 0 2006.189.08:16:21.62#ibcon#wrote, iclass 34, count 0 2006.189.08:16:21.62#ibcon#about to read 3, iclass 34, count 0 2006.189.08:16:21.64#ibcon#read 3, iclass 34, count 0 2006.189.08:16:21.64#ibcon#about to read 4, iclass 34, count 0 2006.189.08:16:21.64#ibcon#read 4, iclass 34, count 0 2006.189.08:16:21.64#ibcon#about to read 5, iclass 34, count 0 2006.189.08:16:21.64#ibcon#read 5, iclass 34, count 0 2006.189.08:16:21.64#ibcon#about to read 6, iclass 34, count 0 2006.189.08:16:21.64#ibcon#read 6, iclass 34, count 0 2006.189.08:16:21.64#ibcon#end of sib2, iclass 34, count 0 2006.189.08:16:21.64#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:16:21.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:16:21.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:16:21.64#ibcon#*before write, iclass 34, count 0 2006.189.08:16:21.64#ibcon#enter sib2, iclass 34, count 0 2006.189.08:16:21.64#ibcon#flushed, iclass 34, count 0 2006.189.08:16:21.64#ibcon#about to write, iclass 34, count 0 2006.189.08:16:21.64#ibcon#wrote, iclass 34, count 0 2006.189.08:16:21.64#ibcon#about to read 3, iclass 34, count 0 2006.189.08:16:21.68#ibcon#read 3, iclass 34, count 0 2006.189.08:16:21.68#ibcon#about to read 4, iclass 34, count 0 2006.189.08:16:21.68#ibcon#read 4, iclass 34, count 0 2006.189.08:16:21.68#ibcon#about to read 5, iclass 34, count 0 2006.189.08:16:21.68#ibcon#read 5, iclass 34, count 0 2006.189.08:16:21.68#ibcon#about to read 6, iclass 34, count 0 2006.189.08:16:21.68#ibcon#read 6, iclass 34, count 0 2006.189.08:16:21.68#ibcon#end of sib2, iclass 34, count 0 2006.189.08:16:21.68#ibcon#*after write, iclass 34, count 0 2006.189.08:16:21.68#ibcon#*before return 0, iclass 34, count 0 2006.189.08:16:21.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:21.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:16:21.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:16:21.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:16:21.68$vc4f8/vb=4,4 2006.189.08:16:21.68#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.08:16:21.68#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.08:16:21.68#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:21.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:21.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:21.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:21.74#ibcon#enter wrdev, iclass 36, count 2 2006.189.08:16:21.74#ibcon#first serial, iclass 36, count 2 2006.189.08:16:21.74#ibcon#enter sib2, iclass 36, count 2 2006.189.08:16:21.74#ibcon#flushed, iclass 36, count 2 2006.189.08:16:21.74#ibcon#about to write, iclass 36, count 2 2006.189.08:16:21.74#ibcon#wrote, iclass 36, count 2 2006.189.08:16:21.74#ibcon#about to read 3, iclass 36, count 2 2006.189.08:16:21.76#ibcon#read 3, iclass 36, count 2 2006.189.08:16:21.76#ibcon#about to read 4, iclass 36, count 2 2006.189.08:16:21.76#ibcon#read 4, iclass 36, count 2 2006.189.08:16:21.76#ibcon#about to read 5, iclass 36, count 2 2006.189.08:16:21.76#ibcon#read 5, iclass 36, count 2 2006.189.08:16:21.76#ibcon#about to read 6, iclass 36, count 2 2006.189.08:16:21.76#ibcon#read 6, iclass 36, count 2 2006.189.08:16:21.76#ibcon#end of sib2, iclass 36, count 2 2006.189.08:16:21.76#ibcon#*mode == 0, iclass 36, count 2 2006.189.08:16:21.76#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.08:16:21.76#ibcon#[27=AT04-04\r\n] 2006.189.08:16:21.76#ibcon#*before write, iclass 36, count 2 2006.189.08:16:21.76#ibcon#enter sib2, iclass 36, count 2 2006.189.08:16:21.76#ibcon#flushed, iclass 36, count 2 2006.189.08:16:21.76#ibcon#about to write, iclass 36, count 2 2006.189.08:16:21.76#ibcon#wrote, iclass 36, count 2 2006.189.08:16:21.76#ibcon#about to read 3, iclass 36, count 2 2006.189.08:16:21.79#ibcon#read 3, iclass 36, count 2 2006.189.08:16:21.79#ibcon#about to read 4, iclass 36, count 2 2006.189.08:16:21.79#ibcon#read 4, iclass 36, count 2 2006.189.08:16:21.79#ibcon#about to read 5, iclass 36, count 2 2006.189.08:16:21.79#ibcon#read 5, iclass 36, count 2 2006.189.08:16:21.79#ibcon#about to read 6, iclass 36, count 2 2006.189.08:16:21.79#ibcon#read 6, iclass 36, count 2 2006.189.08:16:21.79#ibcon#end of sib2, iclass 36, count 2 2006.189.08:16:21.79#ibcon#*after write, iclass 36, count 2 2006.189.08:16:21.79#ibcon#*before return 0, iclass 36, count 2 2006.189.08:16:21.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:21.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:16:21.79#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.08:16:21.79#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:21.79#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:21.91#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:21.91#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:21.91#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:16:21.91#ibcon#first serial, iclass 36, count 0 2006.189.08:16:21.91#ibcon#enter sib2, iclass 36, count 0 2006.189.08:16:21.91#ibcon#flushed, iclass 36, count 0 2006.189.08:16:21.91#ibcon#about to write, iclass 36, count 0 2006.189.08:16:21.91#ibcon#wrote, iclass 36, count 0 2006.189.08:16:21.91#ibcon#about to read 3, iclass 36, count 0 2006.189.08:16:21.93#ibcon#read 3, iclass 36, count 0 2006.189.08:16:21.93#ibcon#about to read 4, iclass 36, count 0 2006.189.08:16:21.93#ibcon#read 4, iclass 36, count 0 2006.189.08:16:21.93#ibcon#about to read 5, iclass 36, count 0 2006.189.08:16:21.93#ibcon#read 5, iclass 36, count 0 2006.189.08:16:21.93#ibcon#about to read 6, iclass 36, count 0 2006.189.08:16:21.93#ibcon#read 6, iclass 36, count 0 2006.189.08:16:21.93#ibcon#end of sib2, iclass 36, count 0 2006.189.08:16:21.93#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:16:21.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:16:21.93#ibcon#[27=USB\r\n] 2006.189.08:16:21.93#ibcon#*before write, iclass 36, count 0 2006.189.08:16:21.93#ibcon#enter sib2, iclass 36, count 0 2006.189.08:16:21.93#ibcon#flushed, iclass 36, count 0 2006.189.08:16:21.93#ibcon#about to write, iclass 36, count 0 2006.189.08:16:21.93#ibcon#wrote, iclass 36, count 0 2006.189.08:16:21.93#ibcon#about to read 3, iclass 36, count 0 2006.189.08:16:21.96#ibcon#read 3, iclass 36, count 0 2006.189.08:16:21.96#ibcon#about to read 4, iclass 36, count 0 2006.189.08:16:21.96#ibcon#read 4, iclass 36, count 0 2006.189.08:16:21.96#ibcon#about to read 5, iclass 36, count 0 2006.189.08:16:21.96#ibcon#read 5, iclass 36, count 0 2006.189.08:16:21.96#ibcon#about to read 6, iclass 36, count 0 2006.189.08:16:21.96#ibcon#read 6, iclass 36, count 0 2006.189.08:16:21.96#ibcon#end of sib2, iclass 36, count 0 2006.189.08:16:21.96#ibcon#*after write, iclass 36, count 0 2006.189.08:16:21.96#ibcon#*before return 0, iclass 36, count 0 2006.189.08:16:21.96#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:21.96#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:16:21.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:16:21.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:16:21.96$vc4f8/vblo=5,744.99 2006.189.08:16:21.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.08:16:21.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.08:16:21.96#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:21.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:21.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:21.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:21.96#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:16:21.96#ibcon#first serial, iclass 38, count 0 2006.189.08:16:21.96#ibcon#enter sib2, iclass 38, count 0 2006.189.08:16:21.96#ibcon#flushed, iclass 38, count 0 2006.189.08:16:21.96#ibcon#about to write, iclass 38, count 0 2006.189.08:16:21.96#ibcon#wrote, iclass 38, count 0 2006.189.08:16:21.96#ibcon#about to read 3, iclass 38, count 0 2006.189.08:16:21.98#ibcon#read 3, iclass 38, count 0 2006.189.08:16:21.98#ibcon#about to read 4, iclass 38, count 0 2006.189.08:16:21.98#ibcon#read 4, iclass 38, count 0 2006.189.08:16:21.98#ibcon#about to read 5, iclass 38, count 0 2006.189.08:16:21.98#ibcon#read 5, iclass 38, count 0 2006.189.08:16:21.98#ibcon#about to read 6, iclass 38, count 0 2006.189.08:16:21.98#ibcon#read 6, iclass 38, count 0 2006.189.08:16:21.98#ibcon#end of sib2, iclass 38, count 0 2006.189.08:16:21.98#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:16:21.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:16:21.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:16:21.98#ibcon#*before write, iclass 38, count 0 2006.189.08:16:21.98#ibcon#enter sib2, iclass 38, count 0 2006.189.08:16:21.98#ibcon#flushed, iclass 38, count 0 2006.189.08:16:21.98#ibcon#about to write, iclass 38, count 0 2006.189.08:16:21.98#ibcon#wrote, iclass 38, count 0 2006.189.08:16:21.98#ibcon#about to read 3, iclass 38, count 0 2006.189.08:16:22.02#ibcon#read 3, iclass 38, count 0 2006.189.08:16:22.02#ibcon#about to read 4, iclass 38, count 0 2006.189.08:16:22.02#ibcon#read 4, iclass 38, count 0 2006.189.08:16:22.02#ibcon#about to read 5, iclass 38, count 0 2006.189.08:16:22.02#ibcon#read 5, iclass 38, count 0 2006.189.08:16:22.02#ibcon#about to read 6, iclass 38, count 0 2006.189.08:16:22.02#ibcon#read 6, iclass 38, count 0 2006.189.08:16:22.02#ibcon#end of sib2, iclass 38, count 0 2006.189.08:16:22.02#ibcon#*after write, iclass 38, count 0 2006.189.08:16:22.02#ibcon#*before return 0, iclass 38, count 0 2006.189.08:16:22.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:22.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:16:22.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:16:22.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:16:22.02$vc4f8/vb=5,4 2006.189.08:16:22.02#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.08:16:22.02#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.08:16:22.02#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:22.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:22.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:22.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:22.08#ibcon#enter wrdev, iclass 40, count 2 2006.189.08:16:22.08#ibcon#first serial, iclass 40, count 2 2006.189.08:16:22.08#ibcon#enter sib2, iclass 40, count 2 2006.189.08:16:22.08#ibcon#flushed, iclass 40, count 2 2006.189.08:16:22.08#ibcon#about to write, iclass 40, count 2 2006.189.08:16:22.08#ibcon#wrote, iclass 40, count 2 2006.189.08:16:22.08#ibcon#about to read 3, iclass 40, count 2 2006.189.08:16:22.10#ibcon#read 3, iclass 40, count 2 2006.189.08:16:22.10#ibcon#about to read 4, iclass 40, count 2 2006.189.08:16:22.10#ibcon#read 4, iclass 40, count 2 2006.189.08:16:22.10#ibcon#about to read 5, iclass 40, count 2 2006.189.08:16:22.10#ibcon#read 5, iclass 40, count 2 2006.189.08:16:22.10#ibcon#about to read 6, iclass 40, count 2 2006.189.08:16:22.10#ibcon#read 6, iclass 40, count 2 2006.189.08:16:22.10#ibcon#end of sib2, iclass 40, count 2 2006.189.08:16:22.10#ibcon#*mode == 0, iclass 40, count 2 2006.189.08:16:22.10#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.08:16:22.10#ibcon#[27=AT05-04\r\n] 2006.189.08:16:22.10#ibcon#*before write, iclass 40, count 2 2006.189.08:16:22.10#ibcon#enter sib2, iclass 40, count 2 2006.189.08:16:22.10#ibcon#flushed, iclass 40, count 2 2006.189.08:16:22.10#ibcon#about to write, iclass 40, count 2 2006.189.08:16:22.10#ibcon#wrote, iclass 40, count 2 2006.189.08:16:22.10#ibcon#about to read 3, iclass 40, count 2 2006.189.08:16:22.13#ibcon#read 3, iclass 40, count 2 2006.189.08:16:22.13#ibcon#about to read 4, iclass 40, count 2 2006.189.08:16:22.13#ibcon#read 4, iclass 40, count 2 2006.189.08:16:22.13#ibcon#about to read 5, iclass 40, count 2 2006.189.08:16:22.13#ibcon#read 5, iclass 40, count 2 2006.189.08:16:22.13#ibcon#about to read 6, iclass 40, count 2 2006.189.08:16:22.13#ibcon#read 6, iclass 40, count 2 2006.189.08:16:22.13#ibcon#end of sib2, iclass 40, count 2 2006.189.08:16:22.13#ibcon#*after write, iclass 40, count 2 2006.189.08:16:22.13#ibcon#*before return 0, iclass 40, count 2 2006.189.08:16:22.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:22.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:16:22.13#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.08:16:22.13#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:22.13#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:22.25#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:22.25#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:22.25#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:16:22.25#ibcon#first serial, iclass 40, count 0 2006.189.08:16:22.25#ibcon#enter sib2, iclass 40, count 0 2006.189.08:16:22.25#ibcon#flushed, iclass 40, count 0 2006.189.08:16:22.25#ibcon#about to write, iclass 40, count 0 2006.189.08:16:22.25#ibcon#wrote, iclass 40, count 0 2006.189.08:16:22.25#ibcon#about to read 3, iclass 40, count 0 2006.189.08:16:22.27#ibcon#read 3, iclass 40, count 0 2006.189.08:16:22.27#ibcon#about to read 4, iclass 40, count 0 2006.189.08:16:22.27#ibcon#read 4, iclass 40, count 0 2006.189.08:16:22.27#ibcon#about to read 5, iclass 40, count 0 2006.189.08:16:22.27#ibcon#read 5, iclass 40, count 0 2006.189.08:16:22.27#ibcon#about to read 6, iclass 40, count 0 2006.189.08:16:22.27#ibcon#read 6, iclass 40, count 0 2006.189.08:16:22.27#ibcon#end of sib2, iclass 40, count 0 2006.189.08:16:22.27#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:16:22.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:16:22.27#ibcon#[27=USB\r\n] 2006.189.08:16:22.27#ibcon#*before write, iclass 40, count 0 2006.189.08:16:22.27#ibcon#enter sib2, iclass 40, count 0 2006.189.08:16:22.27#ibcon#flushed, iclass 40, count 0 2006.189.08:16:22.27#ibcon#about to write, iclass 40, count 0 2006.189.08:16:22.27#ibcon#wrote, iclass 40, count 0 2006.189.08:16:22.27#ibcon#about to read 3, iclass 40, count 0 2006.189.08:16:22.30#ibcon#read 3, iclass 40, count 0 2006.189.08:16:22.30#ibcon#about to read 4, iclass 40, count 0 2006.189.08:16:22.30#ibcon#read 4, iclass 40, count 0 2006.189.08:16:22.30#ibcon#about to read 5, iclass 40, count 0 2006.189.08:16:22.30#ibcon#read 5, iclass 40, count 0 2006.189.08:16:22.30#ibcon#about to read 6, iclass 40, count 0 2006.189.08:16:22.30#ibcon#read 6, iclass 40, count 0 2006.189.08:16:22.30#ibcon#end of sib2, iclass 40, count 0 2006.189.08:16:22.30#ibcon#*after write, iclass 40, count 0 2006.189.08:16:22.30#ibcon#*before return 0, iclass 40, count 0 2006.189.08:16:22.30#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:22.30#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:16:22.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:16:22.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:16:22.30$vc4f8/vblo=6,752.99 2006.189.08:16:22.30#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.08:16:22.30#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.08:16:22.30#ibcon#ireg 17 cls_cnt 0 2006.189.08:16:22.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:22.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:22.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:22.30#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:16:22.30#ibcon#first serial, iclass 4, count 0 2006.189.08:16:22.30#ibcon#enter sib2, iclass 4, count 0 2006.189.08:16:22.30#ibcon#flushed, iclass 4, count 0 2006.189.08:16:22.30#ibcon#about to write, iclass 4, count 0 2006.189.08:16:22.30#ibcon#wrote, iclass 4, count 0 2006.189.08:16:22.30#ibcon#about to read 3, iclass 4, count 0 2006.189.08:16:22.32#ibcon#read 3, iclass 4, count 0 2006.189.08:16:22.32#ibcon#about to read 4, iclass 4, count 0 2006.189.08:16:22.32#ibcon#read 4, iclass 4, count 0 2006.189.08:16:22.32#ibcon#about to read 5, iclass 4, count 0 2006.189.08:16:22.32#ibcon#read 5, iclass 4, count 0 2006.189.08:16:22.32#ibcon#about to read 6, iclass 4, count 0 2006.189.08:16:22.32#ibcon#read 6, iclass 4, count 0 2006.189.08:16:22.32#ibcon#end of sib2, iclass 4, count 0 2006.189.08:16:22.32#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:16:22.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:16:22.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:16:22.32#ibcon#*before write, iclass 4, count 0 2006.189.08:16:22.32#ibcon#enter sib2, iclass 4, count 0 2006.189.08:16:22.32#ibcon#flushed, iclass 4, count 0 2006.189.08:16:22.32#ibcon#about to write, iclass 4, count 0 2006.189.08:16:22.32#ibcon#wrote, iclass 4, count 0 2006.189.08:16:22.32#ibcon#about to read 3, iclass 4, count 0 2006.189.08:16:22.36#ibcon#read 3, iclass 4, count 0 2006.189.08:16:22.36#ibcon#about to read 4, iclass 4, count 0 2006.189.08:16:22.36#ibcon#read 4, iclass 4, count 0 2006.189.08:16:22.36#ibcon#about to read 5, iclass 4, count 0 2006.189.08:16:22.36#ibcon#read 5, iclass 4, count 0 2006.189.08:16:22.36#ibcon#about to read 6, iclass 4, count 0 2006.189.08:16:22.36#ibcon#read 6, iclass 4, count 0 2006.189.08:16:22.36#ibcon#end of sib2, iclass 4, count 0 2006.189.08:16:22.36#ibcon#*after write, iclass 4, count 0 2006.189.08:16:22.36#ibcon#*before return 0, iclass 4, count 0 2006.189.08:16:22.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:22.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:16:22.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:16:22.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:16:22.36$vc4f8/vb=6,4 2006.189.08:16:22.36#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.08:16:22.36#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.08:16:22.36#ibcon#ireg 11 cls_cnt 2 2006.189.08:16:22.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:22.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:22.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:22.42#ibcon#enter wrdev, iclass 6, count 2 2006.189.08:16:22.42#ibcon#first serial, iclass 6, count 2 2006.189.08:16:22.42#ibcon#enter sib2, iclass 6, count 2 2006.189.08:16:22.42#ibcon#flushed, iclass 6, count 2 2006.189.08:16:22.42#ibcon#about to write, iclass 6, count 2 2006.189.08:16:22.42#ibcon#wrote, iclass 6, count 2 2006.189.08:16:22.42#ibcon#about to read 3, iclass 6, count 2 2006.189.08:16:22.44#ibcon#read 3, iclass 6, count 2 2006.189.08:16:22.44#ibcon#about to read 4, iclass 6, count 2 2006.189.08:16:22.44#ibcon#read 4, iclass 6, count 2 2006.189.08:16:22.44#ibcon#about to read 5, iclass 6, count 2 2006.189.08:16:22.44#ibcon#read 5, iclass 6, count 2 2006.189.08:16:22.44#ibcon#about to read 6, iclass 6, count 2 2006.189.08:16:22.44#ibcon#read 6, iclass 6, count 2 2006.189.08:16:22.44#ibcon#end of sib2, iclass 6, count 2 2006.189.08:16:22.44#ibcon#*mode == 0, iclass 6, count 2 2006.189.08:16:22.44#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.08:16:22.44#ibcon#[27=AT06-04\r\n] 2006.189.08:16:22.44#ibcon#*before write, iclass 6, count 2 2006.189.08:16:22.44#ibcon#enter sib2, iclass 6, count 2 2006.189.08:16:22.44#ibcon#flushed, iclass 6, count 2 2006.189.08:16:22.44#ibcon#about to write, iclass 6, count 2 2006.189.08:16:22.44#ibcon#wrote, iclass 6, count 2 2006.189.08:16:22.44#ibcon#about to read 3, iclass 6, count 2 2006.189.08:16:22.47#ibcon#read 3, iclass 6, count 2 2006.189.08:16:22.47#ibcon#about to read 4, iclass 6, count 2 2006.189.08:16:22.47#ibcon#read 4, iclass 6, count 2 2006.189.08:16:22.47#ibcon#about to read 5, iclass 6, count 2 2006.189.08:16:22.47#ibcon#read 5, iclass 6, count 2 2006.189.08:16:22.47#ibcon#about to read 6, iclass 6, count 2 2006.189.08:16:22.47#ibcon#read 6, iclass 6, count 2 2006.189.08:16:22.47#ibcon#end of sib2, iclass 6, count 2 2006.189.08:16:22.47#ibcon#*after write, iclass 6, count 2 2006.189.08:16:22.47#ibcon#*before return 0, iclass 6, count 2 2006.189.08:16:22.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:22.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:16:22.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.08:16:22.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:16:22.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:22.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:22.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:22.59#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:16:22.59#ibcon#first serial, iclass 6, count 0 2006.189.08:16:22.59#ibcon#enter sib2, iclass 6, count 0 2006.189.08:16:22.59#ibcon#flushed, iclass 6, count 0 2006.189.08:16:22.59#ibcon#about to write, iclass 6, count 0 2006.189.08:16:22.59#ibcon#wrote, iclass 6, count 0 2006.189.08:16:22.59#ibcon#about to read 3, iclass 6, count 0 2006.189.08:16:22.61#ibcon#read 3, iclass 6, count 0 2006.189.08:16:22.61#ibcon#about to read 4, iclass 6, count 0 2006.189.08:16:22.61#ibcon#read 4, iclass 6, count 0 2006.189.08:16:22.61#ibcon#about to read 5, iclass 6, count 0 2006.189.08:16:22.61#ibcon#read 5, iclass 6, count 0 2006.189.08:16:22.61#ibcon#about to read 6, iclass 6, count 0 2006.189.08:16:22.61#ibcon#read 6, iclass 6, count 0 2006.189.08:16:22.61#ibcon#end of sib2, iclass 6, count 0 2006.189.08:16:22.61#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:16:22.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:16:22.61#ibcon#[27=USB\r\n] 2006.189.08:16:22.61#ibcon#*before write, iclass 6, count 0 2006.189.08:16:22.61#ibcon#enter sib2, iclass 6, count 0 2006.189.08:16:22.61#ibcon#flushed, iclass 6, count 0 2006.189.08:16:22.61#ibcon#about to write, iclass 6, count 0 2006.189.08:16:22.61#ibcon#wrote, iclass 6, count 0 2006.189.08:16:22.61#ibcon#about to read 3, iclass 6, count 0 2006.189.08:16:22.64#ibcon#read 3, iclass 6, count 0 2006.189.08:16:22.64#ibcon#about to read 4, iclass 6, count 0 2006.189.08:16:22.64#ibcon#read 4, iclass 6, count 0 2006.189.08:16:22.64#ibcon#about to read 5, iclass 6, count 0 2006.189.08:16:22.64#ibcon#read 5, iclass 6, count 0 2006.189.08:16:22.64#ibcon#about to read 6, iclass 6, count 0 2006.189.08:16:22.64#ibcon#read 6, iclass 6, count 0 2006.189.08:16:22.64#ibcon#end of sib2, iclass 6, count 0 2006.189.08:16:22.64#ibcon#*after write, iclass 6, count 0 2006.189.08:16:22.64#ibcon#*before return 0, iclass 6, count 0 2006.189.08:16:22.64#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:22.64#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:16:22.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:16:22.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:16:22.64$vc4f8/vabw=wide 2006.189.08:16:22.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.08:16:22.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.08:16:22.64#ibcon#ireg 8 cls_cnt 0 2006.189.08:16:22.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:22.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:22.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:22.64#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:16:22.64#ibcon#first serial, iclass 10, count 0 2006.189.08:16:22.64#ibcon#enter sib2, iclass 10, count 0 2006.189.08:16:22.64#ibcon#flushed, iclass 10, count 0 2006.189.08:16:22.64#ibcon#about to write, iclass 10, count 0 2006.189.08:16:22.64#ibcon#wrote, iclass 10, count 0 2006.189.08:16:22.64#ibcon#about to read 3, iclass 10, count 0 2006.189.08:16:22.66#ibcon#read 3, iclass 10, count 0 2006.189.08:16:22.66#ibcon#about to read 4, iclass 10, count 0 2006.189.08:16:22.66#ibcon#read 4, iclass 10, count 0 2006.189.08:16:22.66#ibcon#about to read 5, iclass 10, count 0 2006.189.08:16:22.66#ibcon#read 5, iclass 10, count 0 2006.189.08:16:22.66#ibcon#about to read 6, iclass 10, count 0 2006.189.08:16:22.66#ibcon#read 6, iclass 10, count 0 2006.189.08:16:22.66#ibcon#end of sib2, iclass 10, count 0 2006.189.08:16:22.66#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:16:22.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:16:22.66#ibcon#[25=BW32\r\n] 2006.189.08:16:22.66#ibcon#*before write, iclass 10, count 0 2006.189.08:16:22.66#ibcon#enter sib2, iclass 10, count 0 2006.189.08:16:22.66#ibcon#flushed, iclass 10, count 0 2006.189.08:16:22.66#ibcon#about to write, iclass 10, count 0 2006.189.08:16:22.66#ibcon#wrote, iclass 10, count 0 2006.189.08:16:22.66#ibcon#about to read 3, iclass 10, count 0 2006.189.08:16:22.69#ibcon#read 3, iclass 10, count 0 2006.189.08:16:22.69#ibcon#about to read 4, iclass 10, count 0 2006.189.08:16:22.69#ibcon#read 4, iclass 10, count 0 2006.189.08:16:22.69#ibcon#about to read 5, iclass 10, count 0 2006.189.08:16:22.69#ibcon#read 5, iclass 10, count 0 2006.189.08:16:22.69#ibcon#about to read 6, iclass 10, count 0 2006.189.08:16:22.69#ibcon#read 6, iclass 10, count 0 2006.189.08:16:22.69#ibcon#end of sib2, iclass 10, count 0 2006.189.08:16:22.69#ibcon#*after write, iclass 10, count 0 2006.189.08:16:22.69#ibcon#*before return 0, iclass 10, count 0 2006.189.08:16:22.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:22.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:16:22.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:16:22.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:16:22.69$vc4f8/vbbw=wide 2006.189.08:16:22.69#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.08:16:22.69#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.08:16:22.69#ibcon#ireg 8 cls_cnt 0 2006.189.08:16:22.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:16:22.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:16:22.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:16:22.76#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:16:22.76#ibcon#first serial, iclass 12, count 0 2006.189.08:16:22.76#ibcon#enter sib2, iclass 12, count 0 2006.189.08:16:22.76#ibcon#flushed, iclass 12, count 0 2006.189.08:16:22.76#ibcon#about to write, iclass 12, count 0 2006.189.08:16:22.76#ibcon#wrote, iclass 12, count 0 2006.189.08:16:22.76#ibcon#about to read 3, iclass 12, count 0 2006.189.08:16:22.78#ibcon#read 3, iclass 12, count 0 2006.189.08:16:22.78#ibcon#about to read 4, iclass 12, count 0 2006.189.08:16:22.78#ibcon#read 4, iclass 12, count 0 2006.189.08:16:22.78#ibcon#about to read 5, iclass 12, count 0 2006.189.08:16:22.78#ibcon#read 5, iclass 12, count 0 2006.189.08:16:22.78#ibcon#about to read 6, iclass 12, count 0 2006.189.08:16:22.78#ibcon#read 6, iclass 12, count 0 2006.189.08:16:22.78#ibcon#end of sib2, iclass 12, count 0 2006.189.08:16:22.78#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:16:22.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:16:22.78#ibcon#[27=BW32\r\n] 2006.189.08:16:22.78#ibcon#*before write, iclass 12, count 0 2006.189.08:16:22.78#ibcon#enter sib2, iclass 12, count 0 2006.189.08:16:22.78#ibcon#flushed, iclass 12, count 0 2006.189.08:16:22.78#ibcon#about to write, iclass 12, count 0 2006.189.08:16:22.78#ibcon#wrote, iclass 12, count 0 2006.189.08:16:22.78#ibcon#about to read 3, iclass 12, count 0 2006.189.08:16:22.81#ibcon#read 3, iclass 12, count 0 2006.189.08:16:22.81#ibcon#about to read 4, iclass 12, count 0 2006.189.08:16:22.81#ibcon#read 4, iclass 12, count 0 2006.189.08:16:22.81#ibcon#about to read 5, iclass 12, count 0 2006.189.08:16:22.81#ibcon#read 5, iclass 12, count 0 2006.189.08:16:22.81#ibcon#about to read 6, iclass 12, count 0 2006.189.08:16:22.81#ibcon#read 6, iclass 12, count 0 2006.189.08:16:22.81#ibcon#end of sib2, iclass 12, count 0 2006.189.08:16:22.81#ibcon#*after write, iclass 12, count 0 2006.189.08:16:22.81#ibcon#*before return 0, iclass 12, count 0 2006.189.08:16:22.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:16:22.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:16:22.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:16:22.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:16:22.81$4f8m12a/ifd4f 2006.189.08:16:22.81$ifd4f/lo= 2006.189.08:16:22.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:16:22.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:16:22.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:16:22.81$ifd4f/patch= 2006.189.08:16:22.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:16:22.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:16:22.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:16:22.81$4f8m12a/"form=m,16.000,1:2 2006.189.08:16:22.81$4f8m12a/"tpicd 2006.189.08:16:22.82$4f8m12a/echo=off 2006.189.08:16:22.82$4f8m12a/xlog=off 2006.189.08:16:22.82:!2006.189.08:16:50 2006.189.08:16:32.14#trakl#Source acquired 2006.189.08:16:34.14#flagr#flagr/antenna,acquired 2006.189.08:16:50.01:preob 2006.189.08:16:51.14/onsource/TRACKING 2006.189.08:16:51.14:!2006.189.08:17:00 2006.189.08:17:00.00:data_valid=on 2006.189.08:17:00.00:midob 2006.189.08:17:00.14/onsource/TRACKING 2006.189.08:17:00.14/wx/25.42,1009.2,91 2006.189.08:17:00.29/cable/+6.4569E-03 2006.189.08:17:01.38/va/01,08,usb,yes,33,35 2006.189.08:17:01.38/va/02,07,usb,yes,33,35 2006.189.08:17:01.38/va/03,06,usb,yes,35,35 2006.189.08:17:01.38/va/04,07,usb,yes,34,37 2006.189.08:17:01.38/va/05,07,usb,yes,37,39 2006.189.08:17:01.38/va/06,06,usb,yes,36,36 2006.189.08:17:01.38/va/07,06,usb,yes,37,36 2006.189.08:17:01.38/va/08,06,usb,yes,39,39 2006.189.08:17:01.61/valo/01,532.99,yes,locked 2006.189.08:17:01.61/valo/02,572.99,yes,locked 2006.189.08:17:01.61/valo/03,672.99,yes,locked 2006.189.08:17:01.61/valo/04,832.99,yes,locked 2006.189.08:17:01.61/valo/05,652.99,yes,locked 2006.189.08:17:01.61/valo/06,772.99,yes,locked 2006.189.08:17:01.61/valo/07,832.99,yes,locked 2006.189.08:17:01.61/valo/08,852.99,yes,locked 2006.189.08:17:02.70/vb/01,04,usb,yes,32,31 2006.189.08:17:02.70/vb/02,04,usb,yes,34,36 2006.189.08:17:02.70/vb/03,04,usb,yes,30,34 2006.189.08:17:02.70/vb/04,04,usb,yes,32,31 2006.189.08:17:02.70/vb/05,04,usb,yes,29,33 2006.189.08:17:02.70/vb/06,04,usb,yes,30,33 2006.189.08:17:02.70/vb/07,04,usb,yes,32,33 2006.189.08:17:02.70/vb/08,04,usb,yes,30,33 2006.189.08:17:02.93/vblo/01,632.99,yes,locked 2006.189.08:17:02.93/vblo/02,640.99,yes,locked 2006.189.08:17:02.93/vblo/03,656.99,yes,locked 2006.189.08:17:02.93/vblo/04,712.99,yes,locked 2006.189.08:17:02.93/vblo/05,744.99,yes,locked 2006.189.08:17:02.93/vblo/06,752.99,yes,locked 2006.189.08:17:02.93/vblo/07,734.99,yes,locked 2006.189.08:17:02.93/vblo/08,744.99,yes,locked 2006.189.08:17:03.08/vabw/8 2006.189.08:17:03.23/vbbw/8 2006.189.08:17:03.32/xfe/off,on,14.7 2006.189.08:17:03.70/ifatt/23,28,28,28 2006.189.08:17:04.07/fmout-gps/S +2.99E-07 2006.189.08:17:04.16:!2006.189.08:18:00 2006.189.08:18:00.01:data_valid=off 2006.189.08:18:00.02:postob 2006.189.08:18:00.08/cable/+6.4579E-03 2006.189.08:18:00.09/wx/25.39,1009.2,91 2006.189.08:18:01.07/fmout-gps/S +2.99E-07 2006.189.08:18:01.08:scan_name=189-0820,k06189,70 2006.189.08:18:01.08:source=1053+815,105811.54,811432.7,2000.0,neutral 2006.189.08:18:02.13#flagr#flagr/antenna,new-source 2006.189.08:18:02.14:checkk5 2006.189.08:18:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:18:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:18:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:18:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:18:04.03/chk_obsdata//k5ts1/T1890817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:18:04.41/chk_obsdata//k5ts2/T1890817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:18:04.79/chk_obsdata//k5ts3/T1890817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:18:05.16/chk_obsdata//k5ts4/T1890817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:18:05.87/k5log//k5ts1_log_newline 2006.189.08:18:06.58/k5log//k5ts2_log_newline 2006.189.08:18:07.28/k5log//k5ts3_log_newline 2006.189.08:18:07.97/k5log//k5ts4_log_newline 2006.189.08:18:07.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:18:07.99:4f8m12a=3 2006.189.08:18:07.99$4f8m12a/echo=on 2006.189.08:18:08.00$4f8m12a/pcalon 2006.189.08:18:08.00$pcalon/"no phase cal control is implemented here 2006.189.08:18:08.00$4f8m12a/"tpicd=stop 2006.189.08:18:08.00$4f8m12a/vc4f8 2006.189.08:18:08.00$vc4f8/valo=1,532.99 2006.189.08:18:08.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.08:18:08.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.08:18:08.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:08.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:08.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:08.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:08.00#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:18:08.00#ibcon#first serial, iclass 23, count 0 2006.189.08:18:08.00#ibcon#enter sib2, iclass 23, count 0 2006.189.08:18:08.00#ibcon#flushed, iclass 23, count 0 2006.189.08:18:08.00#ibcon#about to write, iclass 23, count 0 2006.189.08:18:08.00#ibcon#wrote, iclass 23, count 0 2006.189.08:18:08.00#ibcon#about to read 3, iclass 23, count 0 2006.189.08:18:08.01#ibcon#read 3, iclass 23, count 0 2006.189.08:18:08.01#ibcon#about to read 4, iclass 23, count 0 2006.189.08:18:08.01#ibcon#read 4, iclass 23, count 0 2006.189.08:18:08.01#ibcon#about to read 5, iclass 23, count 0 2006.189.08:18:08.01#ibcon#read 5, iclass 23, count 0 2006.189.08:18:08.01#ibcon#about to read 6, iclass 23, count 0 2006.189.08:18:08.01#ibcon#read 6, iclass 23, count 0 2006.189.08:18:08.01#ibcon#end of sib2, iclass 23, count 0 2006.189.08:18:08.01#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:18:08.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:18:08.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:18:08.01#ibcon#*before write, iclass 23, count 0 2006.189.08:18:08.01#ibcon#enter sib2, iclass 23, count 0 2006.189.08:18:08.01#ibcon#flushed, iclass 23, count 0 2006.189.08:18:08.01#ibcon#about to write, iclass 23, count 0 2006.189.08:18:08.01#ibcon#wrote, iclass 23, count 0 2006.189.08:18:08.01#ibcon#about to read 3, iclass 23, count 0 2006.189.08:18:08.06#ibcon#read 3, iclass 23, count 0 2006.189.08:18:08.06#ibcon#about to read 4, iclass 23, count 0 2006.189.08:18:08.06#ibcon#read 4, iclass 23, count 0 2006.189.08:18:08.06#ibcon#about to read 5, iclass 23, count 0 2006.189.08:18:08.06#ibcon#read 5, iclass 23, count 0 2006.189.08:18:08.06#ibcon#about to read 6, iclass 23, count 0 2006.189.08:18:08.06#ibcon#read 6, iclass 23, count 0 2006.189.08:18:08.06#ibcon#end of sib2, iclass 23, count 0 2006.189.08:18:08.06#ibcon#*after write, iclass 23, count 0 2006.189.08:18:08.06#ibcon#*before return 0, iclass 23, count 0 2006.189.08:18:08.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:08.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:08.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:18:08.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:18:08.06$vc4f8/va=1,8 2006.189.08:18:08.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.08:18:08.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.08:18:08.06#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:08.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:08.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:08.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:08.06#ibcon#enter wrdev, iclass 25, count 2 2006.189.08:18:08.06#ibcon#first serial, iclass 25, count 2 2006.189.08:18:08.06#ibcon#enter sib2, iclass 25, count 2 2006.189.08:18:08.06#ibcon#flushed, iclass 25, count 2 2006.189.08:18:08.06#ibcon#about to write, iclass 25, count 2 2006.189.08:18:08.06#ibcon#wrote, iclass 25, count 2 2006.189.08:18:08.06#ibcon#about to read 3, iclass 25, count 2 2006.189.08:18:08.08#ibcon#read 3, iclass 25, count 2 2006.189.08:18:08.08#ibcon#about to read 4, iclass 25, count 2 2006.189.08:18:08.08#ibcon#read 4, iclass 25, count 2 2006.189.08:18:08.08#ibcon#about to read 5, iclass 25, count 2 2006.189.08:18:08.08#ibcon#read 5, iclass 25, count 2 2006.189.08:18:08.08#ibcon#about to read 6, iclass 25, count 2 2006.189.08:18:08.08#ibcon#read 6, iclass 25, count 2 2006.189.08:18:08.08#ibcon#end of sib2, iclass 25, count 2 2006.189.08:18:08.08#ibcon#*mode == 0, iclass 25, count 2 2006.189.08:18:08.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.08:18:08.08#ibcon#[25=AT01-08\r\n] 2006.189.08:18:08.08#ibcon#*before write, iclass 25, count 2 2006.189.08:18:08.08#ibcon#enter sib2, iclass 25, count 2 2006.189.08:18:08.08#ibcon#flushed, iclass 25, count 2 2006.189.08:18:08.08#ibcon#about to write, iclass 25, count 2 2006.189.08:18:08.08#ibcon#wrote, iclass 25, count 2 2006.189.08:18:08.08#ibcon#about to read 3, iclass 25, count 2 2006.189.08:18:08.12#ibcon#read 3, iclass 25, count 2 2006.189.08:18:08.12#ibcon#about to read 4, iclass 25, count 2 2006.189.08:18:08.12#ibcon#read 4, iclass 25, count 2 2006.189.08:18:08.12#ibcon#about to read 5, iclass 25, count 2 2006.189.08:18:08.12#ibcon#read 5, iclass 25, count 2 2006.189.08:18:08.12#ibcon#about to read 6, iclass 25, count 2 2006.189.08:18:08.12#ibcon#read 6, iclass 25, count 2 2006.189.08:18:08.12#ibcon#end of sib2, iclass 25, count 2 2006.189.08:18:08.12#ibcon#*after write, iclass 25, count 2 2006.189.08:18:08.12#ibcon#*before return 0, iclass 25, count 2 2006.189.08:18:08.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:08.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:08.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.08:18:08.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:08.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:08.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:08.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:08.24#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:18:08.24#ibcon#first serial, iclass 25, count 0 2006.189.08:18:08.24#ibcon#enter sib2, iclass 25, count 0 2006.189.08:18:08.24#ibcon#flushed, iclass 25, count 0 2006.189.08:18:08.24#ibcon#about to write, iclass 25, count 0 2006.189.08:18:08.24#ibcon#wrote, iclass 25, count 0 2006.189.08:18:08.24#ibcon#about to read 3, iclass 25, count 0 2006.189.08:18:08.26#ibcon#read 3, iclass 25, count 0 2006.189.08:18:08.26#ibcon#about to read 4, iclass 25, count 0 2006.189.08:18:08.26#ibcon#read 4, iclass 25, count 0 2006.189.08:18:08.26#ibcon#about to read 5, iclass 25, count 0 2006.189.08:18:08.26#ibcon#read 5, iclass 25, count 0 2006.189.08:18:08.26#ibcon#about to read 6, iclass 25, count 0 2006.189.08:18:08.26#ibcon#read 6, iclass 25, count 0 2006.189.08:18:08.26#ibcon#end of sib2, iclass 25, count 0 2006.189.08:18:08.26#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:18:08.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:18:08.26#ibcon#[25=USB\r\n] 2006.189.08:18:08.26#ibcon#*before write, iclass 25, count 0 2006.189.08:18:08.26#ibcon#enter sib2, iclass 25, count 0 2006.189.08:18:08.26#ibcon#flushed, iclass 25, count 0 2006.189.08:18:08.26#ibcon#about to write, iclass 25, count 0 2006.189.08:18:08.26#ibcon#wrote, iclass 25, count 0 2006.189.08:18:08.26#ibcon#about to read 3, iclass 25, count 0 2006.189.08:18:08.29#ibcon#read 3, iclass 25, count 0 2006.189.08:18:08.29#ibcon#about to read 4, iclass 25, count 0 2006.189.08:18:08.29#ibcon#read 4, iclass 25, count 0 2006.189.08:18:08.29#ibcon#about to read 5, iclass 25, count 0 2006.189.08:18:08.29#ibcon#read 5, iclass 25, count 0 2006.189.08:18:08.29#ibcon#about to read 6, iclass 25, count 0 2006.189.08:18:08.29#ibcon#read 6, iclass 25, count 0 2006.189.08:18:08.29#ibcon#end of sib2, iclass 25, count 0 2006.189.08:18:08.29#ibcon#*after write, iclass 25, count 0 2006.189.08:18:08.29#ibcon#*before return 0, iclass 25, count 0 2006.189.08:18:08.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:08.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:08.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:18:08.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:18:08.29$vc4f8/valo=2,572.99 2006.189.08:18:08.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.08:18:08.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.08:18:08.29#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:08.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:08.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:08.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:08.29#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:18:08.29#ibcon#first serial, iclass 27, count 0 2006.189.08:18:08.29#ibcon#enter sib2, iclass 27, count 0 2006.189.08:18:08.29#ibcon#flushed, iclass 27, count 0 2006.189.08:18:08.29#ibcon#about to write, iclass 27, count 0 2006.189.08:18:08.29#ibcon#wrote, iclass 27, count 0 2006.189.08:18:08.29#ibcon#about to read 3, iclass 27, count 0 2006.189.08:18:08.31#ibcon#read 3, iclass 27, count 0 2006.189.08:18:08.31#ibcon#about to read 4, iclass 27, count 0 2006.189.08:18:08.31#ibcon#read 4, iclass 27, count 0 2006.189.08:18:08.31#ibcon#about to read 5, iclass 27, count 0 2006.189.08:18:08.31#ibcon#read 5, iclass 27, count 0 2006.189.08:18:08.31#ibcon#about to read 6, iclass 27, count 0 2006.189.08:18:08.31#ibcon#read 6, iclass 27, count 0 2006.189.08:18:08.31#ibcon#end of sib2, iclass 27, count 0 2006.189.08:18:08.31#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:18:08.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:18:08.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:18:08.31#ibcon#*before write, iclass 27, count 0 2006.189.08:18:08.31#ibcon#enter sib2, iclass 27, count 0 2006.189.08:18:08.31#ibcon#flushed, iclass 27, count 0 2006.189.08:18:08.31#ibcon#about to write, iclass 27, count 0 2006.189.08:18:08.31#ibcon#wrote, iclass 27, count 0 2006.189.08:18:08.31#ibcon#about to read 3, iclass 27, count 0 2006.189.08:18:08.35#ibcon#read 3, iclass 27, count 0 2006.189.08:18:08.35#ibcon#about to read 4, iclass 27, count 0 2006.189.08:18:08.35#ibcon#read 4, iclass 27, count 0 2006.189.08:18:08.35#ibcon#about to read 5, iclass 27, count 0 2006.189.08:18:08.35#ibcon#read 5, iclass 27, count 0 2006.189.08:18:08.35#ibcon#about to read 6, iclass 27, count 0 2006.189.08:18:08.35#ibcon#read 6, iclass 27, count 0 2006.189.08:18:08.35#ibcon#end of sib2, iclass 27, count 0 2006.189.08:18:08.35#ibcon#*after write, iclass 27, count 0 2006.189.08:18:08.35#ibcon#*before return 0, iclass 27, count 0 2006.189.08:18:08.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:08.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:08.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:18:08.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:18:08.35$vc4f8/va=2,7 2006.189.08:18:08.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.08:18:08.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.08:18:08.35#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:08.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:08.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:08.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:08.41#ibcon#enter wrdev, iclass 29, count 2 2006.189.08:18:08.41#ibcon#first serial, iclass 29, count 2 2006.189.08:18:08.41#ibcon#enter sib2, iclass 29, count 2 2006.189.08:18:08.41#ibcon#flushed, iclass 29, count 2 2006.189.08:18:08.41#ibcon#about to write, iclass 29, count 2 2006.189.08:18:08.41#ibcon#wrote, iclass 29, count 2 2006.189.08:18:08.41#ibcon#about to read 3, iclass 29, count 2 2006.189.08:18:08.43#ibcon#read 3, iclass 29, count 2 2006.189.08:18:08.43#ibcon#about to read 4, iclass 29, count 2 2006.189.08:18:08.43#ibcon#read 4, iclass 29, count 2 2006.189.08:18:08.43#ibcon#about to read 5, iclass 29, count 2 2006.189.08:18:08.43#ibcon#read 5, iclass 29, count 2 2006.189.08:18:08.43#ibcon#about to read 6, iclass 29, count 2 2006.189.08:18:08.43#ibcon#read 6, iclass 29, count 2 2006.189.08:18:08.43#ibcon#end of sib2, iclass 29, count 2 2006.189.08:18:08.43#ibcon#*mode == 0, iclass 29, count 2 2006.189.08:18:08.43#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.08:18:08.43#ibcon#[25=AT02-07\r\n] 2006.189.08:18:08.43#ibcon#*before write, iclass 29, count 2 2006.189.08:18:08.43#ibcon#enter sib2, iclass 29, count 2 2006.189.08:18:08.43#ibcon#flushed, iclass 29, count 2 2006.189.08:18:08.43#ibcon#about to write, iclass 29, count 2 2006.189.08:18:08.43#ibcon#wrote, iclass 29, count 2 2006.189.08:18:08.43#ibcon#about to read 3, iclass 29, count 2 2006.189.08:18:08.46#ibcon#read 3, iclass 29, count 2 2006.189.08:18:08.46#ibcon#about to read 4, iclass 29, count 2 2006.189.08:18:08.46#ibcon#read 4, iclass 29, count 2 2006.189.08:18:08.46#ibcon#about to read 5, iclass 29, count 2 2006.189.08:18:08.46#ibcon#read 5, iclass 29, count 2 2006.189.08:18:08.46#ibcon#about to read 6, iclass 29, count 2 2006.189.08:18:08.46#ibcon#read 6, iclass 29, count 2 2006.189.08:18:08.46#ibcon#end of sib2, iclass 29, count 2 2006.189.08:18:08.46#ibcon#*after write, iclass 29, count 2 2006.189.08:18:08.46#ibcon#*before return 0, iclass 29, count 2 2006.189.08:18:08.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:08.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:08.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.08:18:08.46#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:08.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:08.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:08.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:08.59#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:18:08.59#ibcon#first serial, iclass 29, count 0 2006.189.08:18:08.59#ibcon#enter sib2, iclass 29, count 0 2006.189.08:18:08.59#ibcon#flushed, iclass 29, count 0 2006.189.08:18:08.59#ibcon#about to write, iclass 29, count 0 2006.189.08:18:08.59#ibcon#wrote, iclass 29, count 0 2006.189.08:18:08.59#ibcon#about to read 3, iclass 29, count 0 2006.189.08:18:08.60#ibcon#read 3, iclass 29, count 0 2006.189.08:18:08.60#ibcon#about to read 4, iclass 29, count 0 2006.189.08:18:08.60#ibcon#read 4, iclass 29, count 0 2006.189.08:18:08.60#ibcon#about to read 5, iclass 29, count 0 2006.189.08:18:08.60#ibcon#read 5, iclass 29, count 0 2006.189.08:18:08.60#ibcon#about to read 6, iclass 29, count 0 2006.189.08:18:08.60#ibcon#read 6, iclass 29, count 0 2006.189.08:18:08.60#ibcon#end of sib2, iclass 29, count 0 2006.189.08:18:08.60#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:18:08.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:18:08.60#ibcon#[25=USB\r\n] 2006.189.08:18:08.60#ibcon#*before write, iclass 29, count 0 2006.189.08:18:08.60#ibcon#enter sib2, iclass 29, count 0 2006.189.08:18:08.60#ibcon#flushed, iclass 29, count 0 2006.189.08:18:08.60#ibcon#about to write, iclass 29, count 0 2006.189.08:18:08.60#ibcon#wrote, iclass 29, count 0 2006.189.08:18:08.60#ibcon#about to read 3, iclass 29, count 0 2006.189.08:18:08.63#ibcon#read 3, iclass 29, count 0 2006.189.08:18:08.63#ibcon#about to read 4, iclass 29, count 0 2006.189.08:18:08.63#ibcon#read 4, iclass 29, count 0 2006.189.08:18:08.63#ibcon#about to read 5, iclass 29, count 0 2006.189.08:18:08.63#ibcon#read 5, iclass 29, count 0 2006.189.08:18:08.63#ibcon#about to read 6, iclass 29, count 0 2006.189.08:18:08.63#ibcon#read 6, iclass 29, count 0 2006.189.08:18:08.63#ibcon#end of sib2, iclass 29, count 0 2006.189.08:18:08.63#ibcon#*after write, iclass 29, count 0 2006.189.08:18:08.63#ibcon#*before return 0, iclass 29, count 0 2006.189.08:18:08.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:08.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:08.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:18:08.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:18:08.63$vc4f8/valo=3,672.99 2006.189.08:18:08.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.08:18:08.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.08:18:08.63#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:08.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:08.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:08.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:08.63#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:18:08.63#ibcon#first serial, iclass 31, count 0 2006.189.08:18:08.63#ibcon#enter sib2, iclass 31, count 0 2006.189.08:18:08.63#ibcon#flushed, iclass 31, count 0 2006.189.08:18:08.63#ibcon#about to write, iclass 31, count 0 2006.189.08:18:08.63#ibcon#wrote, iclass 31, count 0 2006.189.08:18:08.63#ibcon#about to read 3, iclass 31, count 0 2006.189.08:18:08.65#ibcon#read 3, iclass 31, count 0 2006.189.08:18:08.65#ibcon#about to read 4, iclass 31, count 0 2006.189.08:18:08.65#ibcon#read 4, iclass 31, count 0 2006.189.08:18:08.65#ibcon#about to read 5, iclass 31, count 0 2006.189.08:18:08.65#ibcon#read 5, iclass 31, count 0 2006.189.08:18:08.65#ibcon#about to read 6, iclass 31, count 0 2006.189.08:18:08.65#ibcon#read 6, iclass 31, count 0 2006.189.08:18:08.65#ibcon#end of sib2, iclass 31, count 0 2006.189.08:18:08.65#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:18:08.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:18:08.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:18:08.65#ibcon#*before write, iclass 31, count 0 2006.189.08:18:08.65#ibcon#enter sib2, iclass 31, count 0 2006.189.08:18:08.65#ibcon#flushed, iclass 31, count 0 2006.189.08:18:08.65#ibcon#about to write, iclass 31, count 0 2006.189.08:18:08.65#ibcon#wrote, iclass 31, count 0 2006.189.08:18:08.65#ibcon#about to read 3, iclass 31, count 0 2006.189.08:18:08.70#ibcon#read 3, iclass 31, count 0 2006.189.08:18:08.70#ibcon#about to read 4, iclass 31, count 0 2006.189.08:18:08.70#ibcon#read 4, iclass 31, count 0 2006.189.08:18:08.70#ibcon#about to read 5, iclass 31, count 0 2006.189.08:18:08.70#ibcon#read 5, iclass 31, count 0 2006.189.08:18:08.70#ibcon#about to read 6, iclass 31, count 0 2006.189.08:18:08.70#ibcon#read 6, iclass 31, count 0 2006.189.08:18:08.70#ibcon#end of sib2, iclass 31, count 0 2006.189.08:18:08.70#ibcon#*after write, iclass 31, count 0 2006.189.08:18:08.70#ibcon#*before return 0, iclass 31, count 0 2006.189.08:18:08.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:08.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:08.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:18:08.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:18:08.70$vc4f8/va=3,6 2006.189.08:18:08.70#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.08:18:08.70#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.08:18:08.70#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:08.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:08.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:08.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:08.74#ibcon#enter wrdev, iclass 33, count 2 2006.189.08:18:08.74#ibcon#first serial, iclass 33, count 2 2006.189.08:18:08.74#ibcon#enter sib2, iclass 33, count 2 2006.189.08:18:08.74#ibcon#flushed, iclass 33, count 2 2006.189.08:18:08.74#ibcon#about to write, iclass 33, count 2 2006.189.08:18:08.74#ibcon#wrote, iclass 33, count 2 2006.189.08:18:08.74#ibcon#about to read 3, iclass 33, count 2 2006.189.08:18:08.76#ibcon#read 3, iclass 33, count 2 2006.189.08:18:08.76#ibcon#about to read 4, iclass 33, count 2 2006.189.08:18:08.76#ibcon#read 4, iclass 33, count 2 2006.189.08:18:08.76#ibcon#about to read 5, iclass 33, count 2 2006.189.08:18:08.76#ibcon#read 5, iclass 33, count 2 2006.189.08:18:08.76#ibcon#about to read 6, iclass 33, count 2 2006.189.08:18:08.76#ibcon#read 6, iclass 33, count 2 2006.189.08:18:08.76#ibcon#end of sib2, iclass 33, count 2 2006.189.08:18:08.76#ibcon#*mode == 0, iclass 33, count 2 2006.189.08:18:08.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.08:18:08.76#ibcon#[25=AT03-06\r\n] 2006.189.08:18:08.76#ibcon#*before write, iclass 33, count 2 2006.189.08:18:08.76#ibcon#enter sib2, iclass 33, count 2 2006.189.08:18:08.76#ibcon#flushed, iclass 33, count 2 2006.189.08:18:08.76#ibcon#about to write, iclass 33, count 2 2006.189.08:18:08.76#ibcon#wrote, iclass 33, count 2 2006.189.08:18:08.76#ibcon#about to read 3, iclass 33, count 2 2006.189.08:18:08.79#ibcon#read 3, iclass 33, count 2 2006.189.08:18:08.79#ibcon#about to read 4, iclass 33, count 2 2006.189.08:18:08.79#ibcon#read 4, iclass 33, count 2 2006.189.08:18:08.79#ibcon#about to read 5, iclass 33, count 2 2006.189.08:18:08.79#ibcon#read 5, iclass 33, count 2 2006.189.08:18:08.79#ibcon#about to read 6, iclass 33, count 2 2006.189.08:18:08.79#ibcon#read 6, iclass 33, count 2 2006.189.08:18:08.79#ibcon#end of sib2, iclass 33, count 2 2006.189.08:18:08.79#ibcon#*after write, iclass 33, count 2 2006.189.08:18:08.79#ibcon#*before return 0, iclass 33, count 2 2006.189.08:18:08.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:08.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:08.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.08:18:08.79#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:08.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:08.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:08.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:08.91#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:18:08.91#ibcon#first serial, iclass 33, count 0 2006.189.08:18:08.91#ibcon#enter sib2, iclass 33, count 0 2006.189.08:18:08.91#ibcon#flushed, iclass 33, count 0 2006.189.08:18:08.91#ibcon#about to write, iclass 33, count 0 2006.189.08:18:08.91#ibcon#wrote, iclass 33, count 0 2006.189.08:18:08.91#ibcon#about to read 3, iclass 33, count 0 2006.189.08:18:08.93#ibcon#read 3, iclass 33, count 0 2006.189.08:18:08.93#ibcon#about to read 4, iclass 33, count 0 2006.189.08:18:08.93#ibcon#read 4, iclass 33, count 0 2006.189.08:18:08.93#ibcon#about to read 5, iclass 33, count 0 2006.189.08:18:08.93#ibcon#read 5, iclass 33, count 0 2006.189.08:18:08.93#ibcon#about to read 6, iclass 33, count 0 2006.189.08:18:08.93#ibcon#read 6, iclass 33, count 0 2006.189.08:18:08.93#ibcon#end of sib2, iclass 33, count 0 2006.189.08:18:08.93#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:18:08.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:18:08.93#ibcon#[25=USB\r\n] 2006.189.08:18:08.93#ibcon#*before write, iclass 33, count 0 2006.189.08:18:08.93#ibcon#enter sib2, iclass 33, count 0 2006.189.08:18:08.93#ibcon#flushed, iclass 33, count 0 2006.189.08:18:08.93#ibcon#about to write, iclass 33, count 0 2006.189.08:18:08.93#ibcon#wrote, iclass 33, count 0 2006.189.08:18:08.93#ibcon#about to read 3, iclass 33, count 0 2006.189.08:18:08.96#ibcon#read 3, iclass 33, count 0 2006.189.08:18:08.96#ibcon#about to read 4, iclass 33, count 0 2006.189.08:18:08.96#ibcon#read 4, iclass 33, count 0 2006.189.08:18:08.96#ibcon#about to read 5, iclass 33, count 0 2006.189.08:18:08.96#ibcon#read 5, iclass 33, count 0 2006.189.08:18:08.96#ibcon#about to read 6, iclass 33, count 0 2006.189.08:18:08.96#ibcon#read 6, iclass 33, count 0 2006.189.08:18:08.96#ibcon#end of sib2, iclass 33, count 0 2006.189.08:18:08.96#ibcon#*after write, iclass 33, count 0 2006.189.08:18:08.96#ibcon#*before return 0, iclass 33, count 0 2006.189.08:18:08.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:08.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:08.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:18:08.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:18:08.96$vc4f8/valo=4,832.99 2006.189.08:18:08.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.08:18:08.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.08:18:08.96#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:08.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:08.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:08.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:08.96#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:18:08.96#ibcon#first serial, iclass 35, count 0 2006.189.08:18:08.96#ibcon#enter sib2, iclass 35, count 0 2006.189.08:18:08.96#ibcon#flushed, iclass 35, count 0 2006.189.08:18:08.96#ibcon#about to write, iclass 35, count 0 2006.189.08:18:08.96#ibcon#wrote, iclass 35, count 0 2006.189.08:18:08.96#ibcon#about to read 3, iclass 35, count 0 2006.189.08:18:08.98#ibcon#read 3, iclass 35, count 0 2006.189.08:18:08.98#ibcon#about to read 4, iclass 35, count 0 2006.189.08:18:08.98#ibcon#read 4, iclass 35, count 0 2006.189.08:18:08.98#ibcon#about to read 5, iclass 35, count 0 2006.189.08:18:08.98#ibcon#read 5, iclass 35, count 0 2006.189.08:18:08.98#ibcon#about to read 6, iclass 35, count 0 2006.189.08:18:08.98#ibcon#read 6, iclass 35, count 0 2006.189.08:18:08.98#ibcon#end of sib2, iclass 35, count 0 2006.189.08:18:08.98#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:18:08.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:18:08.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:18:08.98#ibcon#*before write, iclass 35, count 0 2006.189.08:18:08.98#ibcon#enter sib2, iclass 35, count 0 2006.189.08:18:08.98#ibcon#flushed, iclass 35, count 0 2006.189.08:18:08.98#ibcon#about to write, iclass 35, count 0 2006.189.08:18:08.98#ibcon#wrote, iclass 35, count 0 2006.189.08:18:08.98#ibcon#about to read 3, iclass 35, count 0 2006.189.08:18:09.02#ibcon#read 3, iclass 35, count 0 2006.189.08:18:09.02#ibcon#about to read 4, iclass 35, count 0 2006.189.08:18:09.02#ibcon#read 4, iclass 35, count 0 2006.189.08:18:09.02#ibcon#about to read 5, iclass 35, count 0 2006.189.08:18:09.02#ibcon#read 5, iclass 35, count 0 2006.189.08:18:09.02#ibcon#about to read 6, iclass 35, count 0 2006.189.08:18:09.02#ibcon#read 6, iclass 35, count 0 2006.189.08:18:09.02#ibcon#end of sib2, iclass 35, count 0 2006.189.08:18:09.02#ibcon#*after write, iclass 35, count 0 2006.189.08:18:09.02#ibcon#*before return 0, iclass 35, count 0 2006.189.08:18:09.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:09.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:09.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:18:09.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:18:09.02$vc4f8/va=4,7 2006.189.08:18:09.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.08:18:09.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.08:18:09.02#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:09.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:09.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:09.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:09.08#ibcon#enter wrdev, iclass 37, count 2 2006.189.08:18:09.08#ibcon#first serial, iclass 37, count 2 2006.189.08:18:09.08#ibcon#enter sib2, iclass 37, count 2 2006.189.08:18:09.08#ibcon#flushed, iclass 37, count 2 2006.189.08:18:09.08#ibcon#about to write, iclass 37, count 2 2006.189.08:18:09.08#ibcon#wrote, iclass 37, count 2 2006.189.08:18:09.08#ibcon#about to read 3, iclass 37, count 2 2006.189.08:18:09.10#ibcon#read 3, iclass 37, count 2 2006.189.08:18:09.10#ibcon#about to read 4, iclass 37, count 2 2006.189.08:18:09.10#ibcon#read 4, iclass 37, count 2 2006.189.08:18:09.10#ibcon#about to read 5, iclass 37, count 2 2006.189.08:18:09.10#ibcon#read 5, iclass 37, count 2 2006.189.08:18:09.10#ibcon#about to read 6, iclass 37, count 2 2006.189.08:18:09.10#ibcon#read 6, iclass 37, count 2 2006.189.08:18:09.10#ibcon#end of sib2, iclass 37, count 2 2006.189.08:18:09.10#ibcon#*mode == 0, iclass 37, count 2 2006.189.08:18:09.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.08:18:09.10#ibcon#[25=AT04-07\r\n] 2006.189.08:18:09.10#ibcon#*before write, iclass 37, count 2 2006.189.08:18:09.10#ibcon#enter sib2, iclass 37, count 2 2006.189.08:18:09.10#ibcon#flushed, iclass 37, count 2 2006.189.08:18:09.10#ibcon#about to write, iclass 37, count 2 2006.189.08:18:09.10#ibcon#wrote, iclass 37, count 2 2006.189.08:18:09.10#ibcon#about to read 3, iclass 37, count 2 2006.189.08:18:09.13#ibcon#read 3, iclass 37, count 2 2006.189.08:18:09.13#ibcon#about to read 4, iclass 37, count 2 2006.189.08:18:09.13#ibcon#read 4, iclass 37, count 2 2006.189.08:18:09.13#ibcon#about to read 5, iclass 37, count 2 2006.189.08:18:09.13#ibcon#read 5, iclass 37, count 2 2006.189.08:18:09.13#ibcon#about to read 6, iclass 37, count 2 2006.189.08:18:09.13#ibcon#read 6, iclass 37, count 2 2006.189.08:18:09.13#ibcon#end of sib2, iclass 37, count 2 2006.189.08:18:09.13#ibcon#*after write, iclass 37, count 2 2006.189.08:18:09.13#ibcon#*before return 0, iclass 37, count 2 2006.189.08:18:09.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:09.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:09.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.08:18:09.13#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:09.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:09.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:09.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:09.25#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:18:09.25#ibcon#first serial, iclass 37, count 0 2006.189.08:18:09.25#ibcon#enter sib2, iclass 37, count 0 2006.189.08:18:09.25#ibcon#flushed, iclass 37, count 0 2006.189.08:18:09.25#ibcon#about to write, iclass 37, count 0 2006.189.08:18:09.25#ibcon#wrote, iclass 37, count 0 2006.189.08:18:09.25#ibcon#about to read 3, iclass 37, count 0 2006.189.08:18:09.27#ibcon#read 3, iclass 37, count 0 2006.189.08:18:09.27#ibcon#about to read 4, iclass 37, count 0 2006.189.08:18:09.27#ibcon#read 4, iclass 37, count 0 2006.189.08:18:09.27#ibcon#about to read 5, iclass 37, count 0 2006.189.08:18:09.27#ibcon#read 5, iclass 37, count 0 2006.189.08:18:09.27#ibcon#about to read 6, iclass 37, count 0 2006.189.08:18:09.27#ibcon#read 6, iclass 37, count 0 2006.189.08:18:09.27#ibcon#end of sib2, iclass 37, count 0 2006.189.08:18:09.27#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:18:09.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:18:09.27#ibcon#[25=USB\r\n] 2006.189.08:18:09.27#ibcon#*before write, iclass 37, count 0 2006.189.08:18:09.27#ibcon#enter sib2, iclass 37, count 0 2006.189.08:18:09.27#ibcon#flushed, iclass 37, count 0 2006.189.08:18:09.27#ibcon#about to write, iclass 37, count 0 2006.189.08:18:09.27#ibcon#wrote, iclass 37, count 0 2006.189.08:18:09.27#ibcon#about to read 3, iclass 37, count 0 2006.189.08:18:09.30#ibcon#read 3, iclass 37, count 0 2006.189.08:18:09.30#ibcon#about to read 4, iclass 37, count 0 2006.189.08:18:09.30#ibcon#read 4, iclass 37, count 0 2006.189.08:18:09.30#ibcon#about to read 5, iclass 37, count 0 2006.189.08:18:09.30#ibcon#read 5, iclass 37, count 0 2006.189.08:18:09.30#ibcon#about to read 6, iclass 37, count 0 2006.189.08:18:09.30#ibcon#read 6, iclass 37, count 0 2006.189.08:18:09.30#ibcon#end of sib2, iclass 37, count 0 2006.189.08:18:09.30#ibcon#*after write, iclass 37, count 0 2006.189.08:18:09.30#ibcon#*before return 0, iclass 37, count 0 2006.189.08:18:09.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:09.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:09.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:18:09.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:18:09.30$vc4f8/valo=5,652.99 2006.189.08:18:09.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.08:18:09.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.08:18:09.30#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:09.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:09.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:09.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:09.30#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:18:09.30#ibcon#first serial, iclass 39, count 0 2006.189.08:18:09.30#ibcon#enter sib2, iclass 39, count 0 2006.189.08:18:09.30#ibcon#flushed, iclass 39, count 0 2006.189.08:18:09.30#ibcon#about to write, iclass 39, count 0 2006.189.08:18:09.30#ibcon#wrote, iclass 39, count 0 2006.189.08:18:09.30#ibcon#about to read 3, iclass 39, count 0 2006.189.08:18:09.32#ibcon#read 3, iclass 39, count 0 2006.189.08:18:09.32#ibcon#about to read 4, iclass 39, count 0 2006.189.08:18:09.32#ibcon#read 4, iclass 39, count 0 2006.189.08:18:09.32#ibcon#about to read 5, iclass 39, count 0 2006.189.08:18:09.32#ibcon#read 5, iclass 39, count 0 2006.189.08:18:09.32#ibcon#about to read 6, iclass 39, count 0 2006.189.08:18:09.32#ibcon#read 6, iclass 39, count 0 2006.189.08:18:09.32#ibcon#end of sib2, iclass 39, count 0 2006.189.08:18:09.32#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:18:09.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:18:09.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:18:09.32#ibcon#*before write, iclass 39, count 0 2006.189.08:18:09.32#ibcon#enter sib2, iclass 39, count 0 2006.189.08:18:09.32#ibcon#flushed, iclass 39, count 0 2006.189.08:18:09.32#ibcon#about to write, iclass 39, count 0 2006.189.08:18:09.32#ibcon#wrote, iclass 39, count 0 2006.189.08:18:09.32#ibcon#about to read 3, iclass 39, count 0 2006.189.08:18:09.36#ibcon#read 3, iclass 39, count 0 2006.189.08:18:09.36#ibcon#about to read 4, iclass 39, count 0 2006.189.08:18:09.36#ibcon#read 4, iclass 39, count 0 2006.189.08:18:09.36#ibcon#about to read 5, iclass 39, count 0 2006.189.08:18:09.36#ibcon#read 5, iclass 39, count 0 2006.189.08:18:09.36#ibcon#about to read 6, iclass 39, count 0 2006.189.08:18:09.36#ibcon#read 6, iclass 39, count 0 2006.189.08:18:09.36#ibcon#end of sib2, iclass 39, count 0 2006.189.08:18:09.36#ibcon#*after write, iclass 39, count 0 2006.189.08:18:09.36#ibcon#*before return 0, iclass 39, count 0 2006.189.08:18:09.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:09.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:09.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:18:09.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:18:09.36$vc4f8/va=5,7 2006.189.08:18:09.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.08:18:09.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.08:18:09.36#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:09.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:09.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:09.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:09.42#ibcon#enter wrdev, iclass 3, count 2 2006.189.08:18:09.42#ibcon#first serial, iclass 3, count 2 2006.189.08:18:09.42#ibcon#enter sib2, iclass 3, count 2 2006.189.08:18:09.42#ibcon#flushed, iclass 3, count 2 2006.189.08:18:09.42#ibcon#about to write, iclass 3, count 2 2006.189.08:18:09.42#ibcon#wrote, iclass 3, count 2 2006.189.08:18:09.42#ibcon#about to read 3, iclass 3, count 2 2006.189.08:18:09.44#ibcon#read 3, iclass 3, count 2 2006.189.08:18:09.44#ibcon#about to read 4, iclass 3, count 2 2006.189.08:18:09.44#ibcon#read 4, iclass 3, count 2 2006.189.08:18:09.44#ibcon#about to read 5, iclass 3, count 2 2006.189.08:18:09.44#ibcon#read 5, iclass 3, count 2 2006.189.08:18:09.44#ibcon#about to read 6, iclass 3, count 2 2006.189.08:18:09.44#ibcon#read 6, iclass 3, count 2 2006.189.08:18:09.44#ibcon#end of sib2, iclass 3, count 2 2006.189.08:18:09.44#ibcon#*mode == 0, iclass 3, count 2 2006.189.08:18:09.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.08:18:09.44#ibcon#[25=AT05-07\r\n] 2006.189.08:18:09.44#ibcon#*before write, iclass 3, count 2 2006.189.08:18:09.44#ibcon#enter sib2, iclass 3, count 2 2006.189.08:18:09.44#ibcon#flushed, iclass 3, count 2 2006.189.08:18:09.44#ibcon#about to write, iclass 3, count 2 2006.189.08:18:09.44#ibcon#wrote, iclass 3, count 2 2006.189.08:18:09.44#ibcon#about to read 3, iclass 3, count 2 2006.189.08:18:09.47#ibcon#read 3, iclass 3, count 2 2006.189.08:18:09.47#ibcon#about to read 4, iclass 3, count 2 2006.189.08:18:09.47#ibcon#read 4, iclass 3, count 2 2006.189.08:18:09.47#ibcon#about to read 5, iclass 3, count 2 2006.189.08:18:09.47#ibcon#read 5, iclass 3, count 2 2006.189.08:18:09.47#ibcon#about to read 6, iclass 3, count 2 2006.189.08:18:09.47#ibcon#read 6, iclass 3, count 2 2006.189.08:18:09.47#ibcon#end of sib2, iclass 3, count 2 2006.189.08:18:09.47#ibcon#*after write, iclass 3, count 2 2006.189.08:18:09.47#ibcon#*before return 0, iclass 3, count 2 2006.189.08:18:09.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:09.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:09.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.08:18:09.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:09.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:09.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:09.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:09.59#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:18:09.59#ibcon#first serial, iclass 3, count 0 2006.189.08:18:09.59#ibcon#enter sib2, iclass 3, count 0 2006.189.08:18:09.59#ibcon#flushed, iclass 3, count 0 2006.189.08:18:09.59#ibcon#about to write, iclass 3, count 0 2006.189.08:18:09.59#ibcon#wrote, iclass 3, count 0 2006.189.08:18:09.59#ibcon#about to read 3, iclass 3, count 0 2006.189.08:18:09.61#ibcon#read 3, iclass 3, count 0 2006.189.08:18:09.61#ibcon#about to read 4, iclass 3, count 0 2006.189.08:18:09.61#ibcon#read 4, iclass 3, count 0 2006.189.08:18:09.61#ibcon#about to read 5, iclass 3, count 0 2006.189.08:18:09.61#ibcon#read 5, iclass 3, count 0 2006.189.08:18:09.61#ibcon#about to read 6, iclass 3, count 0 2006.189.08:18:09.61#ibcon#read 6, iclass 3, count 0 2006.189.08:18:09.61#ibcon#end of sib2, iclass 3, count 0 2006.189.08:18:09.61#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:18:09.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:18:09.61#ibcon#[25=USB\r\n] 2006.189.08:18:09.61#ibcon#*before write, iclass 3, count 0 2006.189.08:18:09.61#ibcon#enter sib2, iclass 3, count 0 2006.189.08:18:09.61#ibcon#flushed, iclass 3, count 0 2006.189.08:18:09.61#ibcon#about to write, iclass 3, count 0 2006.189.08:18:09.61#ibcon#wrote, iclass 3, count 0 2006.189.08:18:09.61#ibcon#about to read 3, iclass 3, count 0 2006.189.08:18:09.64#ibcon#read 3, iclass 3, count 0 2006.189.08:18:09.64#ibcon#about to read 4, iclass 3, count 0 2006.189.08:18:09.64#ibcon#read 4, iclass 3, count 0 2006.189.08:18:09.64#ibcon#about to read 5, iclass 3, count 0 2006.189.08:18:09.64#ibcon#read 5, iclass 3, count 0 2006.189.08:18:09.64#ibcon#about to read 6, iclass 3, count 0 2006.189.08:18:09.64#ibcon#read 6, iclass 3, count 0 2006.189.08:18:09.64#ibcon#end of sib2, iclass 3, count 0 2006.189.08:18:09.64#ibcon#*after write, iclass 3, count 0 2006.189.08:18:09.64#ibcon#*before return 0, iclass 3, count 0 2006.189.08:18:09.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:09.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:09.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:18:09.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:18:09.65$vc4f8/valo=6,772.99 2006.189.08:18:09.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.08:18:09.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.08:18:09.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:09.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:09.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:09.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:09.65#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:18:09.65#ibcon#first serial, iclass 5, count 0 2006.189.08:18:09.65#ibcon#enter sib2, iclass 5, count 0 2006.189.08:18:09.65#ibcon#flushed, iclass 5, count 0 2006.189.08:18:09.65#ibcon#about to write, iclass 5, count 0 2006.189.08:18:09.65#ibcon#wrote, iclass 5, count 0 2006.189.08:18:09.65#ibcon#about to read 3, iclass 5, count 0 2006.189.08:18:09.66#ibcon#read 3, iclass 5, count 0 2006.189.08:18:09.66#ibcon#about to read 4, iclass 5, count 0 2006.189.08:18:09.66#ibcon#read 4, iclass 5, count 0 2006.189.08:18:09.66#ibcon#about to read 5, iclass 5, count 0 2006.189.08:18:09.66#ibcon#read 5, iclass 5, count 0 2006.189.08:18:09.66#ibcon#about to read 6, iclass 5, count 0 2006.189.08:18:09.66#ibcon#read 6, iclass 5, count 0 2006.189.08:18:09.66#ibcon#end of sib2, iclass 5, count 0 2006.189.08:18:09.66#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:18:09.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:18:09.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:18:09.66#ibcon#*before write, iclass 5, count 0 2006.189.08:18:09.66#ibcon#enter sib2, iclass 5, count 0 2006.189.08:18:09.66#ibcon#flushed, iclass 5, count 0 2006.189.08:18:09.66#ibcon#about to write, iclass 5, count 0 2006.189.08:18:09.66#ibcon#wrote, iclass 5, count 0 2006.189.08:18:09.66#ibcon#about to read 3, iclass 5, count 0 2006.189.08:18:09.70#ibcon#read 3, iclass 5, count 0 2006.189.08:18:09.70#ibcon#about to read 4, iclass 5, count 0 2006.189.08:18:09.70#ibcon#read 4, iclass 5, count 0 2006.189.08:18:09.70#ibcon#about to read 5, iclass 5, count 0 2006.189.08:18:09.70#ibcon#read 5, iclass 5, count 0 2006.189.08:18:09.70#ibcon#about to read 6, iclass 5, count 0 2006.189.08:18:09.70#ibcon#read 6, iclass 5, count 0 2006.189.08:18:09.70#ibcon#end of sib2, iclass 5, count 0 2006.189.08:18:09.70#ibcon#*after write, iclass 5, count 0 2006.189.08:18:09.70#ibcon#*before return 0, iclass 5, count 0 2006.189.08:18:09.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:09.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:09.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:18:09.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:18:09.70$vc4f8/va=6,6 2006.189.08:18:09.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.189.08:18:09.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.189.08:18:09.70#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:09.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:18:09.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:18:09.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:18:09.76#ibcon#enter wrdev, iclass 7, count 2 2006.189.08:18:09.76#ibcon#first serial, iclass 7, count 2 2006.189.08:18:09.76#ibcon#enter sib2, iclass 7, count 2 2006.189.08:18:09.76#ibcon#flushed, iclass 7, count 2 2006.189.08:18:09.76#ibcon#about to write, iclass 7, count 2 2006.189.08:18:09.76#ibcon#wrote, iclass 7, count 2 2006.189.08:18:09.76#ibcon#about to read 3, iclass 7, count 2 2006.189.08:18:09.78#ibcon#read 3, iclass 7, count 2 2006.189.08:18:09.78#ibcon#about to read 4, iclass 7, count 2 2006.189.08:18:09.78#ibcon#read 4, iclass 7, count 2 2006.189.08:18:09.78#ibcon#about to read 5, iclass 7, count 2 2006.189.08:18:09.78#ibcon#read 5, iclass 7, count 2 2006.189.08:18:09.78#ibcon#about to read 6, iclass 7, count 2 2006.189.08:18:09.78#ibcon#read 6, iclass 7, count 2 2006.189.08:18:09.78#ibcon#end of sib2, iclass 7, count 2 2006.189.08:18:09.78#ibcon#*mode == 0, iclass 7, count 2 2006.189.08:18:09.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.189.08:18:09.78#ibcon#[25=AT06-06\r\n] 2006.189.08:18:09.78#ibcon#*before write, iclass 7, count 2 2006.189.08:18:09.78#ibcon#enter sib2, iclass 7, count 2 2006.189.08:18:09.78#ibcon#flushed, iclass 7, count 2 2006.189.08:18:09.78#ibcon#about to write, iclass 7, count 2 2006.189.08:18:09.78#ibcon#wrote, iclass 7, count 2 2006.189.08:18:09.78#ibcon#about to read 3, iclass 7, count 2 2006.189.08:18:09.81#ibcon#read 3, iclass 7, count 2 2006.189.08:18:09.81#ibcon#about to read 4, iclass 7, count 2 2006.189.08:18:09.81#ibcon#read 4, iclass 7, count 2 2006.189.08:18:09.81#ibcon#about to read 5, iclass 7, count 2 2006.189.08:18:09.81#ibcon#read 5, iclass 7, count 2 2006.189.08:18:09.81#ibcon#about to read 6, iclass 7, count 2 2006.189.08:18:09.81#ibcon#read 6, iclass 7, count 2 2006.189.08:18:09.81#ibcon#end of sib2, iclass 7, count 2 2006.189.08:18:09.81#ibcon#*after write, iclass 7, count 2 2006.189.08:18:09.81#ibcon#*before return 0, iclass 7, count 2 2006.189.08:18:09.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:18:09.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.189.08:18:09.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.189.08:18:09.81#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:09.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:18:09.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:18:09.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:18:09.93#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:18:09.93#ibcon#first serial, iclass 7, count 0 2006.189.08:18:09.93#ibcon#enter sib2, iclass 7, count 0 2006.189.08:18:09.93#ibcon#flushed, iclass 7, count 0 2006.189.08:18:09.93#ibcon#about to write, iclass 7, count 0 2006.189.08:18:09.93#ibcon#wrote, iclass 7, count 0 2006.189.08:18:09.93#ibcon#about to read 3, iclass 7, count 0 2006.189.08:18:09.95#ibcon#read 3, iclass 7, count 0 2006.189.08:18:09.95#ibcon#about to read 4, iclass 7, count 0 2006.189.08:18:09.95#ibcon#read 4, iclass 7, count 0 2006.189.08:18:09.95#ibcon#about to read 5, iclass 7, count 0 2006.189.08:18:09.95#ibcon#read 5, iclass 7, count 0 2006.189.08:18:09.95#ibcon#about to read 6, iclass 7, count 0 2006.189.08:18:09.95#ibcon#read 6, iclass 7, count 0 2006.189.08:18:09.95#ibcon#end of sib2, iclass 7, count 0 2006.189.08:18:09.95#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:18:09.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:18:09.95#ibcon#[25=USB\r\n] 2006.189.08:18:09.95#ibcon#*before write, iclass 7, count 0 2006.189.08:18:09.95#ibcon#enter sib2, iclass 7, count 0 2006.189.08:18:09.95#ibcon#flushed, iclass 7, count 0 2006.189.08:18:09.95#ibcon#about to write, iclass 7, count 0 2006.189.08:18:09.95#ibcon#wrote, iclass 7, count 0 2006.189.08:18:09.95#ibcon#about to read 3, iclass 7, count 0 2006.189.08:18:09.98#ibcon#read 3, iclass 7, count 0 2006.189.08:18:09.98#ibcon#about to read 4, iclass 7, count 0 2006.189.08:18:09.98#ibcon#read 4, iclass 7, count 0 2006.189.08:18:09.98#ibcon#about to read 5, iclass 7, count 0 2006.189.08:18:09.98#ibcon#read 5, iclass 7, count 0 2006.189.08:18:09.98#ibcon#about to read 6, iclass 7, count 0 2006.189.08:18:09.98#ibcon#read 6, iclass 7, count 0 2006.189.08:18:09.98#ibcon#end of sib2, iclass 7, count 0 2006.189.08:18:09.98#ibcon#*after write, iclass 7, count 0 2006.189.08:18:09.98#ibcon#*before return 0, iclass 7, count 0 2006.189.08:18:09.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:18:09.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.189.08:18:09.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:18:09.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:18:09.98$vc4f8/valo=7,832.99 2006.189.08:18:09.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.189.08:18:09.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.189.08:18:09.98#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:09.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:18:09.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:18:09.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:18:09.98#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:18:09.98#ibcon#first serial, iclass 11, count 0 2006.189.08:18:09.98#ibcon#enter sib2, iclass 11, count 0 2006.189.08:18:09.98#ibcon#flushed, iclass 11, count 0 2006.189.08:18:09.98#ibcon#about to write, iclass 11, count 0 2006.189.08:18:09.98#ibcon#wrote, iclass 11, count 0 2006.189.08:18:09.98#ibcon#about to read 3, iclass 11, count 0 2006.189.08:18:10.00#ibcon#read 3, iclass 11, count 0 2006.189.08:18:10.00#ibcon#about to read 4, iclass 11, count 0 2006.189.08:18:10.00#ibcon#read 4, iclass 11, count 0 2006.189.08:18:10.00#ibcon#about to read 5, iclass 11, count 0 2006.189.08:18:10.00#ibcon#read 5, iclass 11, count 0 2006.189.08:18:10.00#ibcon#about to read 6, iclass 11, count 0 2006.189.08:18:10.00#ibcon#read 6, iclass 11, count 0 2006.189.08:18:10.00#ibcon#end of sib2, iclass 11, count 0 2006.189.08:18:10.00#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:18:10.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:18:10.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:18:10.00#ibcon#*before write, iclass 11, count 0 2006.189.08:18:10.00#ibcon#enter sib2, iclass 11, count 0 2006.189.08:18:10.00#ibcon#flushed, iclass 11, count 0 2006.189.08:18:10.00#ibcon#about to write, iclass 11, count 0 2006.189.08:18:10.00#ibcon#wrote, iclass 11, count 0 2006.189.08:18:10.00#ibcon#about to read 3, iclass 11, count 0 2006.189.08:18:10.04#ibcon#read 3, iclass 11, count 0 2006.189.08:18:10.04#ibcon#about to read 4, iclass 11, count 0 2006.189.08:18:10.04#ibcon#read 4, iclass 11, count 0 2006.189.08:18:10.04#ibcon#about to read 5, iclass 11, count 0 2006.189.08:18:10.04#ibcon#read 5, iclass 11, count 0 2006.189.08:18:10.04#ibcon#about to read 6, iclass 11, count 0 2006.189.08:18:10.04#ibcon#read 6, iclass 11, count 0 2006.189.08:18:10.04#ibcon#end of sib2, iclass 11, count 0 2006.189.08:18:10.04#ibcon#*after write, iclass 11, count 0 2006.189.08:18:10.04#ibcon#*before return 0, iclass 11, count 0 2006.189.08:18:10.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:18:10.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.189.08:18:10.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:18:10.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:18:10.04$vc4f8/va=7,6 2006.189.08:18:10.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.189.08:18:10.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.189.08:18:10.04#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:10.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:18:10.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:18:10.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:18:10.10#ibcon#enter wrdev, iclass 13, count 2 2006.189.08:18:10.10#ibcon#first serial, iclass 13, count 2 2006.189.08:18:10.10#ibcon#enter sib2, iclass 13, count 2 2006.189.08:18:10.10#ibcon#flushed, iclass 13, count 2 2006.189.08:18:10.10#ibcon#about to write, iclass 13, count 2 2006.189.08:18:10.10#ibcon#wrote, iclass 13, count 2 2006.189.08:18:10.10#ibcon#about to read 3, iclass 13, count 2 2006.189.08:18:10.12#ibcon#read 3, iclass 13, count 2 2006.189.08:18:10.12#ibcon#about to read 4, iclass 13, count 2 2006.189.08:18:10.12#ibcon#read 4, iclass 13, count 2 2006.189.08:18:10.12#ibcon#about to read 5, iclass 13, count 2 2006.189.08:18:10.12#ibcon#read 5, iclass 13, count 2 2006.189.08:18:10.12#ibcon#about to read 6, iclass 13, count 2 2006.189.08:18:10.12#ibcon#read 6, iclass 13, count 2 2006.189.08:18:10.12#ibcon#end of sib2, iclass 13, count 2 2006.189.08:18:10.12#ibcon#*mode == 0, iclass 13, count 2 2006.189.08:18:10.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.189.08:18:10.12#ibcon#[25=AT07-06\r\n] 2006.189.08:18:10.12#ibcon#*before write, iclass 13, count 2 2006.189.08:18:10.12#ibcon#enter sib2, iclass 13, count 2 2006.189.08:18:10.12#ibcon#flushed, iclass 13, count 2 2006.189.08:18:10.12#ibcon#about to write, iclass 13, count 2 2006.189.08:18:10.12#ibcon#wrote, iclass 13, count 2 2006.189.08:18:10.12#ibcon#about to read 3, iclass 13, count 2 2006.189.08:18:10.15#ibcon#read 3, iclass 13, count 2 2006.189.08:18:10.15#ibcon#about to read 4, iclass 13, count 2 2006.189.08:18:10.15#ibcon#read 4, iclass 13, count 2 2006.189.08:18:10.15#ibcon#about to read 5, iclass 13, count 2 2006.189.08:18:10.15#ibcon#read 5, iclass 13, count 2 2006.189.08:18:10.15#ibcon#about to read 6, iclass 13, count 2 2006.189.08:18:10.15#ibcon#read 6, iclass 13, count 2 2006.189.08:18:10.15#ibcon#end of sib2, iclass 13, count 2 2006.189.08:18:10.15#ibcon#*after write, iclass 13, count 2 2006.189.08:18:10.15#ibcon#*before return 0, iclass 13, count 2 2006.189.08:18:10.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:18:10.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.189.08:18:10.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.189.08:18:10.15#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:10.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:18:10.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:18:10.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:18:10.27#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:18:10.27#ibcon#first serial, iclass 13, count 0 2006.189.08:18:10.27#ibcon#enter sib2, iclass 13, count 0 2006.189.08:18:10.27#ibcon#flushed, iclass 13, count 0 2006.189.08:18:10.27#ibcon#about to write, iclass 13, count 0 2006.189.08:18:10.27#ibcon#wrote, iclass 13, count 0 2006.189.08:18:10.27#ibcon#about to read 3, iclass 13, count 0 2006.189.08:18:10.29#ibcon#read 3, iclass 13, count 0 2006.189.08:18:10.29#ibcon#about to read 4, iclass 13, count 0 2006.189.08:18:10.29#ibcon#read 4, iclass 13, count 0 2006.189.08:18:10.29#ibcon#about to read 5, iclass 13, count 0 2006.189.08:18:10.29#ibcon#read 5, iclass 13, count 0 2006.189.08:18:10.29#ibcon#about to read 6, iclass 13, count 0 2006.189.08:18:10.29#ibcon#read 6, iclass 13, count 0 2006.189.08:18:10.29#ibcon#end of sib2, iclass 13, count 0 2006.189.08:18:10.29#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:18:10.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:18:10.29#ibcon#[25=USB\r\n] 2006.189.08:18:10.29#ibcon#*before write, iclass 13, count 0 2006.189.08:18:10.29#ibcon#enter sib2, iclass 13, count 0 2006.189.08:18:10.29#ibcon#flushed, iclass 13, count 0 2006.189.08:18:10.29#ibcon#about to write, iclass 13, count 0 2006.189.08:18:10.29#ibcon#wrote, iclass 13, count 0 2006.189.08:18:10.29#ibcon#about to read 3, iclass 13, count 0 2006.189.08:18:10.32#ibcon#read 3, iclass 13, count 0 2006.189.08:18:10.32#ibcon#about to read 4, iclass 13, count 0 2006.189.08:18:10.32#ibcon#read 4, iclass 13, count 0 2006.189.08:18:10.32#ibcon#about to read 5, iclass 13, count 0 2006.189.08:18:10.32#ibcon#read 5, iclass 13, count 0 2006.189.08:18:10.32#ibcon#about to read 6, iclass 13, count 0 2006.189.08:18:10.32#ibcon#read 6, iclass 13, count 0 2006.189.08:18:10.32#ibcon#end of sib2, iclass 13, count 0 2006.189.08:18:10.32#ibcon#*after write, iclass 13, count 0 2006.189.08:18:10.32#ibcon#*before return 0, iclass 13, count 0 2006.189.08:18:10.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:18:10.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.189.08:18:10.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:18:10.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:18:10.32$vc4f8/valo=8,852.99 2006.189.08:18:10.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.189.08:18:10.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.189.08:18:10.32#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:10.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:18:10.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:18:10.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:18:10.32#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:18:10.32#ibcon#first serial, iclass 15, count 0 2006.189.08:18:10.32#ibcon#enter sib2, iclass 15, count 0 2006.189.08:18:10.32#ibcon#flushed, iclass 15, count 0 2006.189.08:18:10.32#ibcon#about to write, iclass 15, count 0 2006.189.08:18:10.32#ibcon#wrote, iclass 15, count 0 2006.189.08:18:10.32#ibcon#about to read 3, iclass 15, count 0 2006.189.08:18:10.34#ibcon#read 3, iclass 15, count 0 2006.189.08:18:10.34#ibcon#about to read 4, iclass 15, count 0 2006.189.08:18:10.34#ibcon#read 4, iclass 15, count 0 2006.189.08:18:10.34#ibcon#about to read 5, iclass 15, count 0 2006.189.08:18:10.34#ibcon#read 5, iclass 15, count 0 2006.189.08:18:10.34#ibcon#about to read 6, iclass 15, count 0 2006.189.08:18:10.34#ibcon#read 6, iclass 15, count 0 2006.189.08:18:10.34#ibcon#end of sib2, iclass 15, count 0 2006.189.08:18:10.34#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:18:10.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:18:10.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:18:10.34#ibcon#*before write, iclass 15, count 0 2006.189.08:18:10.34#ibcon#enter sib2, iclass 15, count 0 2006.189.08:18:10.34#ibcon#flushed, iclass 15, count 0 2006.189.08:18:10.34#ibcon#about to write, iclass 15, count 0 2006.189.08:18:10.34#ibcon#wrote, iclass 15, count 0 2006.189.08:18:10.34#ibcon#about to read 3, iclass 15, count 0 2006.189.08:18:10.38#ibcon#read 3, iclass 15, count 0 2006.189.08:18:10.38#ibcon#about to read 4, iclass 15, count 0 2006.189.08:18:10.38#ibcon#read 4, iclass 15, count 0 2006.189.08:18:10.38#ibcon#about to read 5, iclass 15, count 0 2006.189.08:18:10.38#ibcon#read 5, iclass 15, count 0 2006.189.08:18:10.38#ibcon#about to read 6, iclass 15, count 0 2006.189.08:18:10.38#ibcon#read 6, iclass 15, count 0 2006.189.08:18:10.38#ibcon#end of sib2, iclass 15, count 0 2006.189.08:18:10.38#ibcon#*after write, iclass 15, count 0 2006.189.08:18:10.38#ibcon#*before return 0, iclass 15, count 0 2006.189.08:18:10.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:18:10.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.189.08:18:10.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:18:10.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:18:10.38$vc4f8/va=8,6 2006.189.08:18:10.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.189.08:18:10.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.189.08:18:10.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:10.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:18:10.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:18:10.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:18:10.44#ibcon#enter wrdev, iclass 17, count 2 2006.189.08:18:10.44#ibcon#first serial, iclass 17, count 2 2006.189.08:18:10.44#ibcon#enter sib2, iclass 17, count 2 2006.189.08:18:10.44#ibcon#flushed, iclass 17, count 2 2006.189.08:18:10.44#ibcon#about to write, iclass 17, count 2 2006.189.08:18:10.44#ibcon#wrote, iclass 17, count 2 2006.189.08:18:10.44#ibcon#about to read 3, iclass 17, count 2 2006.189.08:18:10.46#ibcon#read 3, iclass 17, count 2 2006.189.08:18:10.46#ibcon#about to read 4, iclass 17, count 2 2006.189.08:18:10.46#ibcon#read 4, iclass 17, count 2 2006.189.08:18:10.46#ibcon#about to read 5, iclass 17, count 2 2006.189.08:18:10.46#ibcon#read 5, iclass 17, count 2 2006.189.08:18:10.46#ibcon#about to read 6, iclass 17, count 2 2006.189.08:18:10.46#ibcon#read 6, iclass 17, count 2 2006.189.08:18:10.46#ibcon#end of sib2, iclass 17, count 2 2006.189.08:18:10.46#ibcon#*mode == 0, iclass 17, count 2 2006.189.08:18:10.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.189.08:18:10.46#ibcon#[25=AT08-06\r\n] 2006.189.08:18:10.46#ibcon#*before write, iclass 17, count 2 2006.189.08:18:10.46#ibcon#enter sib2, iclass 17, count 2 2006.189.08:18:10.46#ibcon#flushed, iclass 17, count 2 2006.189.08:18:10.46#ibcon#about to write, iclass 17, count 2 2006.189.08:18:10.46#ibcon#wrote, iclass 17, count 2 2006.189.08:18:10.46#ibcon#about to read 3, iclass 17, count 2 2006.189.08:18:10.49#ibcon#read 3, iclass 17, count 2 2006.189.08:18:10.49#ibcon#about to read 4, iclass 17, count 2 2006.189.08:18:10.49#ibcon#read 4, iclass 17, count 2 2006.189.08:18:10.49#ibcon#about to read 5, iclass 17, count 2 2006.189.08:18:10.49#ibcon#read 5, iclass 17, count 2 2006.189.08:18:10.49#ibcon#about to read 6, iclass 17, count 2 2006.189.08:18:10.49#ibcon#read 6, iclass 17, count 2 2006.189.08:18:10.49#ibcon#end of sib2, iclass 17, count 2 2006.189.08:18:10.49#ibcon#*after write, iclass 17, count 2 2006.189.08:18:10.49#ibcon#*before return 0, iclass 17, count 2 2006.189.08:18:10.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:18:10.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.189.08:18:10.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.189.08:18:10.49#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:10.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:18:10.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:18:10.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:18:10.61#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:18:10.61#ibcon#first serial, iclass 17, count 0 2006.189.08:18:10.61#ibcon#enter sib2, iclass 17, count 0 2006.189.08:18:10.61#ibcon#flushed, iclass 17, count 0 2006.189.08:18:10.61#ibcon#about to write, iclass 17, count 0 2006.189.08:18:10.61#ibcon#wrote, iclass 17, count 0 2006.189.08:18:10.61#ibcon#about to read 3, iclass 17, count 0 2006.189.08:18:10.63#ibcon#read 3, iclass 17, count 0 2006.189.08:18:10.63#ibcon#about to read 4, iclass 17, count 0 2006.189.08:18:10.63#ibcon#read 4, iclass 17, count 0 2006.189.08:18:10.63#ibcon#about to read 5, iclass 17, count 0 2006.189.08:18:10.63#ibcon#read 5, iclass 17, count 0 2006.189.08:18:10.63#ibcon#about to read 6, iclass 17, count 0 2006.189.08:18:10.63#ibcon#read 6, iclass 17, count 0 2006.189.08:18:10.63#ibcon#end of sib2, iclass 17, count 0 2006.189.08:18:10.63#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:18:10.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:18:10.63#ibcon#[25=USB\r\n] 2006.189.08:18:10.63#ibcon#*before write, iclass 17, count 0 2006.189.08:18:10.63#ibcon#enter sib2, iclass 17, count 0 2006.189.08:18:10.63#ibcon#flushed, iclass 17, count 0 2006.189.08:18:10.63#ibcon#about to write, iclass 17, count 0 2006.189.08:18:10.63#ibcon#wrote, iclass 17, count 0 2006.189.08:18:10.63#ibcon#about to read 3, iclass 17, count 0 2006.189.08:18:10.66#ibcon#read 3, iclass 17, count 0 2006.189.08:18:10.66#ibcon#about to read 4, iclass 17, count 0 2006.189.08:18:10.66#ibcon#read 4, iclass 17, count 0 2006.189.08:18:10.66#ibcon#about to read 5, iclass 17, count 0 2006.189.08:18:10.66#ibcon#read 5, iclass 17, count 0 2006.189.08:18:10.66#ibcon#about to read 6, iclass 17, count 0 2006.189.08:18:10.66#ibcon#read 6, iclass 17, count 0 2006.189.08:18:10.66#ibcon#end of sib2, iclass 17, count 0 2006.189.08:18:10.66#ibcon#*after write, iclass 17, count 0 2006.189.08:18:10.66#ibcon#*before return 0, iclass 17, count 0 2006.189.08:18:10.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:18:10.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.189.08:18:10.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:18:10.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:18:10.66$vc4f8/vblo=1,632.99 2006.189.08:18:10.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.189.08:18:10.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.189.08:18:10.66#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:10.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:18:10.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:18:10.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:18:10.66#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:18:10.66#ibcon#first serial, iclass 19, count 0 2006.189.08:18:10.66#ibcon#enter sib2, iclass 19, count 0 2006.189.08:18:10.66#ibcon#flushed, iclass 19, count 0 2006.189.08:18:10.66#ibcon#about to write, iclass 19, count 0 2006.189.08:18:10.66#ibcon#wrote, iclass 19, count 0 2006.189.08:18:10.66#ibcon#about to read 3, iclass 19, count 0 2006.189.08:18:10.68#ibcon#read 3, iclass 19, count 0 2006.189.08:18:10.68#ibcon#about to read 4, iclass 19, count 0 2006.189.08:18:10.68#ibcon#read 4, iclass 19, count 0 2006.189.08:18:10.68#ibcon#about to read 5, iclass 19, count 0 2006.189.08:18:10.68#ibcon#read 5, iclass 19, count 0 2006.189.08:18:10.68#ibcon#about to read 6, iclass 19, count 0 2006.189.08:18:10.68#ibcon#read 6, iclass 19, count 0 2006.189.08:18:10.68#ibcon#end of sib2, iclass 19, count 0 2006.189.08:18:10.68#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:18:10.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:18:10.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:18:10.68#ibcon#*before write, iclass 19, count 0 2006.189.08:18:10.68#ibcon#enter sib2, iclass 19, count 0 2006.189.08:18:10.68#ibcon#flushed, iclass 19, count 0 2006.189.08:18:10.68#ibcon#about to write, iclass 19, count 0 2006.189.08:18:10.68#ibcon#wrote, iclass 19, count 0 2006.189.08:18:10.68#ibcon#about to read 3, iclass 19, count 0 2006.189.08:18:10.72#ibcon#read 3, iclass 19, count 0 2006.189.08:18:10.72#ibcon#about to read 4, iclass 19, count 0 2006.189.08:18:10.72#ibcon#read 4, iclass 19, count 0 2006.189.08:18:10.72#ibcon#about to read 5, iclass 19, count 0 2006.189.08:18:10.72#ibcon#read 5, iclass 19, count 0 2006.189.08:18:10.72#ibcon#about to read 6, iclass 19, count 0 2006.189.08:18:10.72#ibcon#read 6, iclass 19, count 0 2006.189.08:18:10.72#ibcon#end of sib2, iclass 19, count 0 2006.189.08:18:10.72#ibcon#*after write, iclass 19, count 0 2006.189.08:18:10.72#ibcon#*before return 0, iclass 19, count 0 2006.189.08:18:10.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:18:10.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.189.08:18:10.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:18:10.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:18:10.72$vc4f8/vb=1,4 2006.189.08:18:10.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.189.08:18:10.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.189.08:18:10.72#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:10.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:18:10.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:18:10.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:18:10.72#ibcon#enter wrdev, iclass 21, count 2 2006.189.08:18:10.72#ibcon#first serial, iclass 21, count 2 2006.189.08:18:10.72#ibcon#enter sib2, iclass 21, count 2 2006.189.08:18:10.72#ibcon#flushed, iclass 21, count 2 2006.189.08:18:10.72#ibcon#about to write, iclass 21, count 2 2006.189.08:18:10.72#ibcon#wrote, iclass 21, count 2 2006.189.08:18:10.72#ibcon#about to read 3, iclass 21, count 2 2006.189.08:18:10.74#ibcon#read 3, iclass 21, count 2 2006.189.08:18:10.74#ibcon#about to read 4, iclass 21, count 2 2006.189.08:18:10.74#ibcon#read 4, iclass 21, count 2 2006.189.08:18:10.74#ibcon#about to read 5, iclass 21, count 2 2006.189.08:18:10.74#ibcon#read 5, iclass 21, count 2 2006.189.08:18:10.74#ibcon#about to read 6, iclass 21, count 2 2006.189.08:18:10.74#ibcon#read 6, iclass 21, count 2 2006.189.08:18:10.74#ibcon#end of sib2, iclass 21, count 2 2006.189.08:18:10.74#ibcon#*mode == 0, iclass 21, count 2 2006.189.08:18:10.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.189.08:18:10.74#ibcon#[27=AT01-04\r\n] 2006.189.08:18:10.74#ibcon#*before write, iclass 21, count 2 2006.189.08:18:10.74#ibcon#enter sib2, iclass 21, count 2 2006.189.08:18:10.74#ibcon#flushed, iclass 21, count 2 2006.189.08:18:10.74#ibcon#about to write, iclass 21, count 2 2006.189.08:18:10.74#ibcon#wrote, iclass 21, count 2 2006.189.08:18:10.74#ibcon#about to read 3, iclass 21, count 2 2006.189.08:18:10.77#ibcon#read 3, iclass 21, count 2 2006.189.08:18:10.77#ibcon#about to read 4, iclass 21, count 2 2006.189.08:18:10.77#ibcon#read 4, iclass 21, count 2 2006.189.08:18:10.77#ibcon#about to read 5, iclass 21, count 2 2006.189.08:18:10.77#ibcon#read 5, iclass 21, count 2 2006.189.08:18:10.77#ibcon#about to read 6, iclass 21, count 2 2006.189.08:18:10.77#ibcon#read 6, iclass 21, count 2 2006.189.08:18:10.77#ibcon#end of sib2, iclass 21, count 2 2006.189.08:18:10.77#ibcon#*after write, iclass 21, count 2 2006.189.08:18:10.77#ibcon#*before return 0, iclass 21, count 2 2006.189.08:18:10.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:18:10.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.189.08:18:10.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.189.08:18:10.77#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:10.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:18:10.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:18:10.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:18:10.89#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:18:10.89#ibcon#first serial, iclass 21, count 0 2006.189.08:18:10.89#ibcon#enter sib2, iclass 21, count 0 2006.189.08:18:10.89#ibcon#flushed, iclass 21, count 0 2006.189.08:18:10.89#ibcon#about to write, iclass 21, count 0 2006.189.08:18:10.89#ibcon#wrote, iclass 21, count 0 2006.189.08:18:10.89#ibcon#about to read 3, iclass 21, count 0 2006.189.08:18:10.91#ibcon#read 3, iclass 21, count 0 2006.189.08:18:10.91#ibcon#about to read 4, iclass 21, count 0 2006.189.08:18:10.91#ibcon#read 4, iclass 21, count 0 2006.189.08:18:10.91#ibcon#about to read 5, iclass 21, count 0 2006.189.08:18:10.91#ibcon#read 5, iclass 21, count 0 2006.189.08:18:10.91#ibcon#about to read 6, iclass 21, count 0 2006.189.08:18:10.91#ibcon#read 6, iclass 21, count 0 2006.189.08:18:10.91#ibcon#end of sib2, iclass 21, count 0 2006.189.08:18:10.91#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:18:10.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:18:10.91#ibcon#[27=USB\r\n] 2006.189.08:18:10.91#ibcon#*before write, iclass 21, count 0 2006.189.08:18:10.91#ibcon#enter sib2, iclass 21, count 0 2006.189.08:18:10.91#ibcon#flushed, iclass 21, count 0 2006.189.08:18:10.91#ibcon#about to write, iclass 21, count 0 2006.189.08:18:10.91#ibcon#wrote, iclass 21, count 0 2006.189.08:18:10.91#ibcon#about to read 3, iclass 21, count 0 2006.189.08:18:10.94#ibcon#read 3, iclass 21, count 0 2006.189.08:18:10.94#ibcon#about to read 4, iclass 21, count 0 2006.189.08:18:10.94#ibcon#read 4, iclass 21, count 0 2006.189.08:18:10.94#ibcon#about to read 5, iclass 21, count 0 2006.189.08:18:10.94#ibcon#read 5, iclass 21, count 0 2006.189.08:18:10.94#ibcon#about to read 6, iclass 21, count 0 2006.189.08:18:10.94#ibcon#read 6, iclass 21, count 0 2006.189.08:18:10.94#ibcon#end of sib2, iclass 21, count 0 2006.189.08:18:10.94#ibcon#*after write, iclass 21, count 0 2006.189.08:18:10.94#ibcon#*before return 0, iclass 21, count 0 2006.189.08:18:10.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:18:10.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.189.08:18:10.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:18:10.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:18:10.94$vc4f8/vblo=2,640.99 2006.189.08:18:10.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.189.08:18:10.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.189.08:18:10.94#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:10.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:10.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:10.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:10.94#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:18:10.94#ibcon#first serial, iclass 23, count 0 2006.189.08:18:10.94#ibcon#enter sib2, iclass 23, count 0 2006.189.08:18:10.94#ibcon#flushed, iclass 23, count 0 2006.189.08:18:10.94#ibcon#about to write, iclass 23, count 0 2006.189.08:18:10.94#ibcon#wrote, iclass 23, count 0 2006.189.08:18:10.94#ibcon#about to read 3, iclass 23, count 0 2006.189.08:18:10.96#ibcon#read 3, iclass 23, count 0 2006.189.08:18:10.96#ibcon#about to read 4, iclass 23, count 0 2006.189.08:18:10.96#ibcon#read 4, iclass 23, count 0 2006.189.08:18:10.96#ibcon#about to read 5, iclass 23, count 0 2006.189.08:18:10.96#ibcon#read 5, iclass 23, count 0 2006.189.08:18:10.96#ibcon#about to read 6, iclass 23, count 0 2006.189.08:18:10.96#ibcon#read 6, iclass 23, count 0 2006.189.08:18:10.96#ibcon#end of sib2, iclass 23, count 0 2006.189.08:18:10.96#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:18:10.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:18:10.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:18:10.96#ibcon#*before write, iclass 23, count 0 2006.189.08:18:10.96#ibcon#enter sib2, iclass 23, count 0 2006.189.08:18:10.96#ibcon#flushed, iclass 23, count 0 2006.189.08:18:10.96#ibcon#about to write, iclass 23, count 0 2006.189.08:18:10.96#ibcon#wrote, iclass 23, count 0 2006.189.08:18:10.96#ibcon#about to read 3, iclass 23, count 0 2006.189.08:18:11.00#ibcon#read 3, iclass 23, count 0 2006.189.08:18:11.00#ibcon#about to read 4, iclass 23, count 0 2006.189.08:18:11.00#ibcon#read 4, iclass 23, count 0 2006.189.08:18:11.00#ibcon#about to read 5, iclass 23, count 0 2006.189.08:18:11.00#ibcon#read 5, iclass 23, count 0 2006.189.08:18:11.00#ibcon#about to read 6, iclass 23, count 0 2006.189.08:18:11.00#ibcon#read 6, iclass 23, count 0 2006.189.08:18:11.00#ibcon#end of sib2, iclass 23, count 0 2006.189.08:18:11.00#ibcon#*after write, iclass 23, count 0 2006.189.08:18:11.00#ibcon#*before return 0, iclass 23, count 0 2006.189.08:18:11.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:11.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.189.08:18:11.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:18:11.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:18:11.00$vc4f8/vb=2,4 2006.189.08:18:11.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.189.08:18:11.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.189.08:18:11.00#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:11.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:11.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:11.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:11.06#ibcon#enter wrdev, iclass 25, count 2 2006.189.08:18:11.06#ibcon#first serial, iclass 25, count 2 2006.189.08:18:11.06#ibcon#enter sib2, iclass 25, count 2 2006.189.08:18:11.06#ibcon#flushed, iclass 25, count 2 2006.189.08:18:11.06#ibcon#about to write, iclass 25, count 2 2006.189.08:18:11.06#ibcon#wrote, iclass 25, count 2 2006.189.08:18:11.06#ibcon#about to read 3, iclass 25, count 2 2006.189.08:18:11.08#ibcon#read 3, iclass 25, count 2 2006.189.08:18:11.08#ibcon#about to read 4, iclass 25, count 2 2006.189.08:18:11.08#ibcon#read 4, iclass 25, count 2 2006.189.08:18:11.08#ibcon#about to read 5, iclass 25, count 2 2006.189.08:18:11.08#ibcon#read 5, iclass 25, count 2 2006.189.08:18:11.08#ibcon#about to read 6, iclass 25, count 2 2006.189.08:18:11.08#ibcon#read 6, iclass 25, count 2 2006.189.08:18:11.08#ibcon#end of sib2, iclass 25, count 2 2006.189.08:18:11.08#ibcon#*mode == 0, iclass 25, count 2 2006.189.08:18:11.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.189.08:18:11.08#ibcon#[27=AT02-04\r\n] 2006.189.08:18:11.08#ibcon#*before write, iclass 25, count 2 2006.189.08:18:11.08#ibcon#enter sib2, iclass 25, count 2 2006.189.08:18:11.08#ibcon#flushed, iclass 25, count 2 2006.189.08:18:11.08#ibcon#about to write, iclass 25, count 2 2006.189.08:18:11.08#ibcon#wrote, iclass 25, count 2 2006.189.08:18:11.08#ibcon#about to read 3, iclass 25, count 2 2006.189.08:18:11.12#ibcon#read 3, iclass 25, count 2 2006.189.08:18:11.12#ibcon#about to read 4, iclass 25, count 2 2006.189.08:18:11.12#ibcon#read 4, iclass 25, count 2 2006.189.08:18:11.12#ibcon#about to read 5, iclass 25, count 2 2006.189.08:18:11.12#ibcon#read 5, iclass 25, count 2 2006.189.08:18:11.12#ibcon#about to read 6, iclass 25, count 2 2006.189.08:18:11.12#ibcon#read 6, iclass 25, count 2 2006.189.08:18:11.12#ibcon#end of sib2, iclass 25, count 2 2006.189.08:18:11.12#ibcon#*after write, iclass 25, count 2 2006.189.08:18:11.12#ibcon#*before return 0, iclass 25, count 2 2006.189.08:18:11.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:11.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.189.08:18:11.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.189.08:18:11.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:11.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:11.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:11.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:11.23#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:18:11.23#ibcon#first serial, iclass 25, count 0 2006.189.08:18:11.23#ibcon#enter sib2, iclass 25, count 0 2006.189.08:18:11.23#ibcon#flushed, iclass 25, count 0 2006.189.08:18:11.23#ibcon#about to write, iclass 25, count 0 2006.189.08:18:11.23#ibcon#wrote, iclass 25, count 0 2006.189.08:18:11.23#ibcon#about to read 3, iclass 25, count 0 2006.189.08:18:11.25#ibcon#read 3, iclass 25, count 0 2006.189.08:18:11.25#ibcon#about to read 4, iclass 25, count 0 2006.189.08:18:11.25#ibcon#read 4, iclass 25, count 0 2006.189.08:18:11.25#ibcon#about to read 5, iclass 25, count 0 2006.189.08:18:11.25#ibcon#read 5, iclass 25, count 0 2006.189.08:18:11.25#ibcon#about to read 6, iclass 25, count 0 2006.189.08:18:11.25#ibcon#read 6, iclass 25, count 0 2006.189.08:18:11.25#ibcon#end of sib2, iclass 25, count 0 2006.189.08:18:11.25#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:18:11.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:18:11.25#ibcon#[27=USB\r\n] 2006.189.08:18:11.25#ibcon#*before write, iclass 25, count 0 2006.189.08:18:11.25#ibcon#enter sib2, iclass 25, count 0 2006.189.08:18:11.25#ibcon#flushed, iclass 25, count 0 2006.189.08:18:11.25#ibcon#about to write, iclass 25, count 0 2006.189.08:18:11.25#ibcon#wrote, iclass 25, count 0 2006.189.08:18:11.25#ibcon#about to read 3, iclass 25, count 0 2006.189.08:18:11.28#ibcon#read 3, iclass 25, count 0 2006.189.08:18:11.28#ibcon#about to read 4, iclass 25, count 0 2006.189.08:18:11.28#ibcon#read 4, iclass 25, count 0 2006.189.08:18:11.28#ibcon#about to read 5, iclass 25, count 0 2006.189.08:18:11.28#ibcon#read 5, iclass 25, count 0 2006.189.08:18:11.28#ibcon#about to read 6, iclass 25, count 0 2006.189.08:18:11.28#ibcon#read 6, iclass 25, count 0 2006.189.08:18:11.28#ibcon#end of sib2, iclass 25, count 0 2006.189.08:18:11.28#ibcon#*after write, iclass 25, count 0 2006.189.08:18:11.28#ibcon#*before return 0, iclass 25, count 0 2006.189.08:18:11.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:11.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.189.08:18:11.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:18:11.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:18:11.28$vc4f8/vblo=3,656.99 2006.189.08:18:11.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.189.08:18:11.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.189.08:18:11.28#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:11.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:11.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:11.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:11.28#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:18:11.28#ibcon#first serial, iclass 27, count 0 2006.189.08:18:11.28#ibcon#enter sib2, iclass 27, count 0 2006.189.08:18:11.28#ibcon#flushed, iclass 27, count 0 2006.189.08:18:11.28#ibcon#about to write, iclass 27, count 0 2006.189.08:18:11.28#ibcon#wrote, iclass 27, count 0 2006.189.08:18:11.28#ibcon#about to read 3, iclass 27, count 0 2006.189.08:18:11.30#ibcon#read 3, iclass 27, count 0 2006.189.08:18:11.30#ibcon#about to read 4, iclass 27, count 0 2006.189.08:18:11.30#ibcon#read 4, iclass 27, count 0 2006.189.08:18:11.30#ibcon#about to read 5, iclass 27, count 0 2006.189.08:18:11.30#ibcon#read 5, iclass 27, count 0 2006.189.08:18:11.30#ibcon#about to read 6, iclass 27, count 0 2006.189.08:18:11.30#ibcon#read 6, iclass 27, count 0 2006.189.08:18:11.30#ibcon#end of sib2, iclass 27, count 0 2006.189.08:18:11.30#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:18:11.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:18:11.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:18:11.30#ibcon#*before write, iclass 27, count 0 2006.189.08:18:11.30#ibcon#enter sib2, iclass 27, count 0 2006.189.08:18:11.30#ibcon#flushed, iclass 27, count 0 2006.189.08:18:11.30#ibcon#about to write, iclass 27, count 0 2006.189.08:18:11.30#ibcon#wrote, iclass 27, count 0 2006.189.08:18:11.30#ibcon#about to read 3, iclass 27, count 0 2006.189.08:18:11.34#ibcon#read 3, iclass 27, count 0 2006.189.08:18:11.34#ibcon#about to read 4, iclass 27, count 0 2006.189.08:18:11.34#ibcon#read 4, iclass 27, count 0 2006.189.08:18:11.34#ibcon#about to read 5, iclass 27, count 0 2006.189.08:18:11.34#ibcon#read 5, iclass 27, count 0 2006.189.08:18:11.34#ibcon#about to read 6, iclass 27, count 0 2006.189.08:18:11.34#ibcon#read 6, iclass 27, count 0 2006.189.08:18:11.34#ibcon#end of sib2, iclass 27, count 0 2006.189.08:18:11.34#ibcon#*after write, iclass 27, count 0 2006.189.08:18:11.34#ibcon#*before return 0, iclass 27, count 0 2006.189.08:18:11.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:11.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.189.08:18:11.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:18:11.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:18:11.34$vc4f8/vb=3,4 2006.189.08:18:11.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.189.08:18:11.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.189.08:18:11.34#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:11.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:11.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:11.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:11.40#ibcon#enter wrdev, iclass 29, count 2 2006.189.08:18:11.40#ibcon#first serial, iclass 29, count 2 2006.189.08:18:11.40#ibcon#enter sib2, iclass 29, count 2 2006.189.08:18:11.40#ibcon#flushed, iclass 29, count 2 2006.189.08:18:11.40#ibcon#about to write, iclass 29, count 2 2006.189.08:18:11.40#ibcon#wrote, iclass 29, count 2 2006.189.08:18:11.40#ibcon#about to read 3, iclass 29, count 2 2006.189.08:18:11.42#ibcon#read 3, iclass 29, count 2 2006.189.08:18:11.42#ibcon#about to read 4, iclass 29, count 2 2006.189.08:18:11.42#ibcon#read 4, iclass 29, count 2 2006.189.08:18:11.42#ibcon#about to read 5, iclass 29, count 2 2006.189.08:18:11.42#ibcon#read 5, iclass 29, count 2 2006.189.08:18:11.42#ibcon#about to read 6, iclass 29, count 2 2006.189.08:18:11.42#ibcon#read 6, iclass 29, count 2 2006.189.08:18:11.42#ibcon#end of sib2, iclass 29, count 2 2006.189.08:18:11.42#ibcon#*mode == 0, iclass 29, count 2 2006.189.08:18:11.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.189.08:18:11.42#ibcon#[27=AT03-04\r\n] 2006.189.08:18:11.42#ibcon#*before write, iclass 29, count 2 2006.189.08:18:11.42#ibcon#enter sib2, iclass 29, count 2 2006.189.08:18:11.42#ibcon#flushed, iclass 29, count 2 2006.189.08:18:11.42#ibcon#about to write, iclass 29, count 2 2006.189.08:18:11.42#ibcon#wrote, iclass 29, count 2 2006.189.08:18:11.42#ibcon#about to read 3, iclass 29, count 2 2006.189.08:18:11.45#ibcon#read 3, iclass 29, count 2 2006.189.08:18:11.45#ibcon#about to read 4, iclass 29, count 2 2006.189.08:18:11.45#ibcon#read 4, iclass 29, count 2 2006.189.08:18:11.45#ibcon#about to read 5, iclass 29, count 2 2006.189.08:18:11.45#ibcon#read 5, iclass 29, count 2 2006.189.08:18:11.45#ibcon#about to read 6, iclass 29, count 2 2006.189.08:18:11.45#ibcon#read 6, iclass 29, count 2 2006.189.08:18:11.45#ibcon#end of sib2, iclass 29, count 2 2006.189.08:18:11.45#ibcon#*after write, iclass 29, count 2 2006.189.08:18:11.45#ibcon#*before return 0, iclass 29, count 2 2006.189.08:18:11.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:11.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.189.08:18:11.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.189.08:18:11.45#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:11.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:11.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:11.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:11.57#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:18:11.57#ibcon#first serial, iclass 29, count 0 2006.189.08:18:11.57#ibcon#enter sib2, iclass 29, count 0 2006.189.08:18:11.57#ibcon#flushed, iclass 29, count 0 2006.189.08:18:11.57#ibcon#about to write, iclass 29, count 0 2006.189.08:18:11.57#ibcon#wrote, iclass 29, count 0 2006.189.08:18:11.57#ibcon#about to read 3, iclass 29, count 0 2006.189.08:18:11.59#ibcon#read 3, iclass 29, count 0 2006.189.08:18:11.59#ibcon#about to read 4, iclass 29, count 0 2006.189.08:18:11.59#ibcon#read 4, iclass 29, count 0 2006.189.08:18:11.59#ibcon#about to read 5, iclass 29, count 0 2006.189.08:18:11.59#ibcon#read 5, iclass 29, count 0 2006.189.08:18:11.59#ibcon#about to read 6, iclass 29, count 0 2006.189.08:18:11.59#ibcon#read 6, iclass 29, count 0 2006.189.08:18:11.59#ibcon#end of sib2, iclass 29, count 0 2006.189.08:18:11.59#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:18:11.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:18:11.59#ibcon#[27=USB\r\n] 2006.189.08:18:11.59#ibcon#*before write, iclass 29, count 0 2006.189.08:18:11.59#ibcon#enter sib2, iclass 29, count 0 2006.189.08:18:11.59#ibcon#flushed, iclass 29, count 0 2006.189.08:18:11.59#ibcon#about to write, iclass 29, count 0 2006.189.08:18:11.59#ibcon#wrote, iclass 29, count 0 2006.189.08:18:11.59#ibcon#about to read 3, iclass 29, count 0 2006.189.08:18:11.62#ibcon#read 3, iclass 29, count 0 2006.189.08:18:11.62#ibcon#about to read 4, iclass 29, count 0 2006.189.08:18:11.62#ibcon#read 4, iclass 29, count 0 2006.189.08:18:11.62#ibcon#about to read 5, iclass 29, count 0 2006.189.08:18:11.62#ibcon#read 5, iclass 29, count 0 2006.189.08:18:11.62#ibcon#about to read 6, iclass 29, count 0 2006.189.08:18:11.62#ibcon#read 6, iclass 29, count 0 2006.189.08:18:11.62#ibcon#end of sib2, iclass 29, count 0 2006.189.08:18:11.62#ibcon#*after write, iclass 29, count 0 2006.189.08:18:11.62#ibcon#*before return 0, iclass 29, count 0 2006.189.08:18:11.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:11.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.189.08:18:11.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:18:11.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:18:11.62$vc4f8/vblo=4,712.99 2006.189.08:18:11.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.189.08:18:11.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.189.08:18:11.62#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:11.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:11.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:11.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:11.62#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:18:11.62#ibcon#first serial, iclass 31, count 0 2006.189.08:18:11.62#ibcon#enter sib2, iclass 31, count 0 2006.189.08:18:11.62#ibcon#flushed, iclass 31, count 0 2006.189.08:18:11.62#ibcon#about to write, iclass 31, count 0 2006.189.08:18:11.62#ibcon#wrote, iclass 31, count 0 2006.189.08:18:11.62#ibcon#about to read 3, iclass 31, count 0 2006.189.08:18:11.64#ibcon#read 3, iclass 31, count 0 2006.189.08:18:11.64#ibcon#about to read 4, iclass 31, count 0 2006.189.08:18:11.64#ibcon#read 4, iclass 31, count 0 2006.189.08:18:11.64#ibcon#about to read 5, iclass 31, count 0 2006.189.08:18:11.64#ibcon#read 5, iclass 31, count 0 2006.189.08:18:11.64#ibcon#about to read 6, iclass 31, count 0 2006.189.08:18:11.64#ibcon#read 6, iclass 31, count 0 2006.189.08:18:11.64#ibcon#end of sib2, iclass 31, count 0 2006.189.08:18:11.64#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:18:11.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:18:11.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:18:11.64#ibcon#*before write, iclass 31, count 0 2006.189.08:18:11.64#ibcon#enter sib2, iclass 31, count 0 2006.189.08:18:11.64#ibcon#flushed, iclass 31, count 0 2006.189.08:18:11.64#ibcon#about to write, iclass 31, count 0 2006.189.08:18:11.64#ibcon#wrote, iclass 31, count 0 2006.189.08:18:11.64#ibcon#about to read 3, iclass 31, count 0 2006.189.08:18:11.68#ibcon#read 3, iclass 31, count 0 2006.189.08:18:11.68#ibcon#about to read 4, iclass 31, count 0 2006.189.08:18:11.68#ibcon#read 4, iclass 31, count 0 2006.189.08:18:11.68#ibcon#about to read 5, iclass 31, count 0 2006.189.08:18:11.68#ibcon#read 5, iclass 31, count 0 2006.189.08:18:11.68#ibcon#about to read 6, iclass 31, count 0 2006.189.08:18:11.68#ibcon#read 6, iclass 31, count 0 2006.189.08:18:11.68#ibcon#end of sib2, iclass 31, count 0 2006.189.08:18:11.68#ibcon#*after write, iclass 31, count 0 2006.189.08:18:11.68#ibcon#*before return 0, iclass 31, count 0 2006.189.08:18:11.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:11.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.189.08:18:11.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:18:11.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:18:11.68$vc4f8/vb=4,4 2006.189.08:18:11.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.189.08:18:11.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.189.08:18:11.68#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:11.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:11.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:11.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:11.74#ibcon#enter wrdev, iclass 33, count 2 2006.189.08:18:11.74#ibcon#first serial, iclass 33, count 2 2006.189.08:18:11.74#ibcon#enter sib2, iclass 33, count 2 2006.189.08:18:11.74#ibcon#flushed, iclass 33, count 2 2006.189.08:18:11.74#ibcon#about to write, iclass 33, count 2 2006.189.08:18:11.74#ibcon#wrote, iclass 33, count 2 2006.189.08:18:11.74#ibcon#about to read 3, iclass 33, count 2 2006.189.08:18:11.76#ibcon#read 3, iclass 33, count 2 2006.189.08:18:11.76#ibcon#about to read 4, iclass 33, count 2 2006.189.08:18:11.76#ibcon#read 4, iclass 33, count 2 2006.189.08:18:11.76#ibcon#about to read 5, iclass 33, count 2 2006.189.08:18:11.76#ibcon#read 5, iclass 33, count 2 2006.189.08:18:11.76#ibcon#about to read 6, iclass 33, count 2 2006.189.08:18:11.76#ibcon#read 6, iclass 33, count 2 2006.189.08:18:11.76#ibcon#end of sib2, iclass 33, count 2 2006.189.08:18:11.76#ibcon#*mode == 0, iclass 33, count 2 2006.189.08:18:11.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.189.08:18:11.76#ibcon#[27=AT04-04\r\n] 2006.189.08:18:11.76#ibcon#*before write, iclass 33, count 2 2006.189.08:18:11.76#ibcon#enter sib2, iclass 33, count 2 2006.189.08:18:11.76#ibcon#flushed, iclass 33, count 2 2006.189.08:18:11.76#ibcon#about to write, iclass 33, count 2 2006.189.08:18:11.76#ibcon#wrote, iclass 33, count 2 2006.189.08:18:11.76#ibcon#about to read 3, iclass 33, count 2 2006.189.08:18:11.79#ibcon#read 3, iclass 33, count 2 2006.189.08:18:11.79#ibcon#about to read 4, iclass 33, count 2 2006.189.08:18:11.79#ibcon#read 4, iclass 33, count 2 2006.189.08:18:11.79#ibcon#about to read 5, iclass 33, count 2 2006.189.08:18:11.79#ibcon#read 5, iclass 33, count 2 2006.189.08:18:11.79#ibcon#about to read 6, iclass 33, count 2 2006.189.08:18:11.79#ibcon#read 6, iclass 33, count 2 2006.189.08:18:11.79#ibcon#end of sib2, iclass 33, count 2 2006.189.08:18:11.79#ibcon#*after write, iclass 33, count 2 2006.189.08:18:11.79#ibcon#*before return 0, iclass 33, count 2 2006.189.08:18:11.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:11.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.189.08:18:11.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.189.08:18:11.79#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:11.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:11.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:11.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:11.91#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:18:11.91#ibcon#first serial, iclass 33, count 0 2006.189.08:18:11.91#ibcon#enter sib2, iclass 33, count 0 2006.189.08:18:11.91#ibcon#flushed, iclass 33, count 0 2006.189.08:18:11.91#ibcon#about to write, iclass 33, count 0 2006.189.08:18:11.91#ibcon#wrote, iclass 33, count 0 2006.189.08:18:11.91#ibcon#about to read 3, iclass 33, count 0 2006.189.08:18:11.93#ibcon#read 3, iclass 33, count 0 2006.189.08:18:11.93#ibcon#about to read 4, iclass 33, count 0 2006.189.08:18:11.93#ibcon#read 4, iclass 33, count 0 2006.189.08:18:11.93#ibcon#about to read 5, iclass 33, count 0 2006.189.08:18:11.93#ibcon#read 5, iclass 33, count 0 2006.189.08:18:11.93#ibcon#about to read 6, iclass 33, count 0 2006.189.08:18:11.93#ibcon#read 6, iclass 33, count 0 2006.189.08:18:11.93#ibcon#end of sib2, iclass 33, count 0 2006.189.08:18:11.93#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:18:11.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:18:11.93#ibcon#[27=USB\r\n] 2006.189.08:18:11.93#ibcon#*before write, iclass 33, count 0 2006.189.08:18:11.93#ibcon#enter sib2, iclass 33, count 0 2006.189.08:18:11.93#ibcon#flushed, iclass 33, count 0 2006.189.08:18:11.93#ibcon#about to write, iclass 33, count 0 2006.189.08:18:11.93#ibcon#wrote, iclass 33, count 0 2006.189.08:18:11.93#ibcon#about to read 3, iclass 33, count 0 2006.189.08:18:11.96#ibcon#read 3, iclass 33, count 0 2006.189.08:18:11.96#ibcon#about to read 4, iclass 33, count 0 2006.189.08:18:11.96#ibcon#read 4, iclass 33, count 0 2006.189.08:18:11.96#ibcon#about to read 5, iclass 33, count 0 2006.189.08:18:11.96#ibcon#read 5, iclass 33, count 0 2006.189.08:18:11.96#ibcon#about to read 6, iclass 33, count 0 2006.189.08:18:11.96#ibcon#read 6, iclass 33, count 0 2006.189.08:18:11.96#ibcon#end of sib2, iclass 33, count 0 2006.189.08:18:11.96#ibcon#*after write, iclass 33, count 0 2006.189.08:18:11.96#ibcon#*before return 0, iclass 33, count 0 2006.189.08:18:11.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:11.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.189.08:18:11.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:18:11.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:18:11.96$vc4f8/vblo=5,744.99 2006.189.08:18:11.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.189.08:18:11.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.189.08:18:11.96#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:11.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:11.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:11.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:11.96#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:18:11.96#ibcon#first serial, iclass 35, count 0 2006.189.08:18:11.96#ibcon#enter sib2, iclass 35, count 0 2006.189.08:18:11.96#ibcon#flushed, iclass 35, count 0 2006.189.08:18:11.96#ibcon#about to write, iclass 35, count 0 2006.189.08:18:11.96#ibcon#wrote, iclass 35, count 0 2006.189.08:18:11.96#ibcon#about to read 3, iclass 35, count 0 2006.189.08:18:11.98#ibcon#read 3, iclass 35, count 0 2006.189.08:18:11.98#ibcon#about to read 4, iclass 35, count 0 2006.189.08:18:11.98#ibcon#read 4, iclass 35, count 0 2006.189.08:18:11.98#ibcon#about to read 5, iclass 35, count 0 2006.189.08:18:11.98#ibcon#read 5, iclass 35, count 0 2006.189.08:18:11.98#ibcon#about to read 6, iclass 35, count 0 2006.189.08:18:11.98#ibcon#read 6, iclass 35, count 0 2006.189.08:18:11.98#ibcon#end of sib2, iclass 35, count 0 2006.189.08:18:11.98#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:18:11.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:18:11.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:18:11.98#ibcon#*before write, iclass 35, count 0 2006.189.08:18:11.98#ibcon#enter sib2, iclass 35, count 0 2006.189.08:18:11.98#ibcon#flushed, iclass 35, count 0 2006.189.08:18:11.98#ibcon#about to write, iclass 35, count 0 2006.189.08:18:11.98#ibcon#wrote, iclass 35, count 0 2006.189.08:18:11.98#ibcon#about to read 3, iclass 35, count 0 2006.189.08:18:12.02#ibcon#read 3, iclass 35, count 0 2006.189.08:18:12.02#ibcon#about to read 4, iclass 35, count 0 2006.189.08:18:12.02#ibcon#read 4, iclass 35, count 0 2006.189.08:18:12.02#ibcon#about to read 5, iclass 35, count 0 2006.189.08:18:12.02#ibcon#read 5, iclass 35, count 0 2006.189.08:18:12.02#ibcon#about to read 6, iclass 35, count 0 2006.189.08:18:12.02#ibcon#read 6, iclass 35, count 0 2006.189.08:18:12.02#ibcon#end of sib2, iclass 35, count 0 2006.189.08:18:12.02#ibcon#*after write, iclass 35, count 0 2006.189.08:18:12.02#ibcon#*before return 0, iclass 35, count 0 2006.189.08:18:12.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:12.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.189.08:18:12.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:18:12.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:18:12.02$vc4f8/vb=5,4 2006.189.08:18:12.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.189.08:18:12.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.189.08:18:12.02#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:12.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:12.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:12.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:12.08#ibcon#enter wrdev, iclass 37, count 2 2006.189.08:18:12.08#ibcon#first serial, iclass 37, count 2 2006.189.08:18:12.08#ibcon#enter sib2, iclass 37, count 2 2006.189.08:18:12.08#ibcon#flushed, iclass 37, count 2 2006.189.08:18:12.08#ibcon#about to write, iclass 37, count 2 2006.189.08:18:12.08#ibcon#wrote, iclass 37, count 2 2006.189.08:18:12.08#ibcon#about to read 3, iclass 37, count 2 2006.189.08:18:12.10#ibcon#read 3, iclass 37, count 2 2006.189.08:18:12.10#ibcon#about to read 4, iclass 37, count 2 2006.189.08:18:12.10#ibcon#read 4, iclass 37, count 2 2006.189.08:18:12.10#ibcon#about to read 5, iclass 37, count 2 2006.189.08:18:12.10#ibcon#read 5, iclass 37, count 2 2006.189.08:18:12.10#ibcon#about to read 6, iclass 37, count 2 2006.189.08:18:12.10#ibcon#read 6, iclass 37, count 2 2006.189.08:18:12.10#ibcon#end of sib2, iclass 37, count 2 2006.189.08:18:12.10#ibcon#*mode == 0, iclass 37, count 2 2006.189.08:18:12.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.189.08:18:12.10#ibcon#[27=AT05-04\r\n] 2006.189.08:18:12.10#ibcon#*before write, iclass 37, count 2 2006.189.08:18:12.10#ibcon#enter sib2, iclass 37, count 2 2006.189.08:18:12.10#ibcon#flushed, iclass 37, count 2 2006.189.08:18:12.10#ibcon#about to write, iclass 37, count 2 2006.189.08:18:12.10#ibcon#wrote, iclass 37, count 2 2006.189.08:18:12.10#ibcon#about to read 3, iclass 37, count 2 2006.189.08:18:12.13#ibcon#read 3, iclass 37, count 2 2006.189.08:18:12.13#ibcon#about to read 4, iclass 37, count 2 2006.189.08:18:12.13#ibcon#read 4, iclass 37, count 2 2006.189.08:18:12.13#ibcon#about to read 5, iclass 37, count 2 2006.189.08:18:12.13#ibcon#read 5, iclass 37, count 2 2006.189.08:18:12.13#ibcon#about to read 6, iclass 37, count 2 2006.189.08:18:12.13#ibcon#read 6, iclass 37, count 2 2006.189.08:18:12.13#ibcon#end of sib2, iclass 37, count 2 2006.189.08:18:12.13#ibcon#*after write, iclass 37, count 2 2006.189.08:18:12.13#ibcon#*before return 0, iclass 37, count 2 2006.189.08:18:12.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:12.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.189.08:18:12.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.189.08:18:12.13#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:12.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:12.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:12.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:12.25#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:18:12.25#ibcon#first serial, iclass 37, count 0 2006.189.08:18:12.25#ibcon#enter sib2, iclass 37, count 0 2006.189.08:18:12.25#ibcon#flushed, iclass 37, count 0 2006.189.08:18:12.25#ibcon#about to write, iclass 37, count 0 2006.189.08:18:12.25#ibcon#wrote, iclass 37, count 0 2006.189.08:18:12.25#ibcon#about to read 3, iclass 37, count 0 2006.189.08:18:12.27#ibcon#read 3, iclass 37, count 0 2006.189.08:18:12.27#ibcon#about to read 4, iclass 37, count 0 2006.189.08:18:12.27#ibcon#read 4, iclass 37, count 0 2006.189.08:18:12.27#ibcon#about to read 5, iclass 37, count 0 2006.189.08:18:12.27#ibcon#read 5, iclass 37, count 0 2006.189.08:18:12.27#ibcon#about to read 6, iclass 37, count 0 2006.189.08:18:12.27#ibcon#read 6, iclass 37, count 0 2006.189.08:18:12.27#ibcon#end of sib2, iclass 37, count 0 2006.189.08:18:12.27#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:18:12.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:18:12.27#ibcon#[27=USB\r\n] 2006.189.08:18:12.27#ibcon#*before write, iclass 37, count 0 2006.189.08:18:12.27#ibcon#enter sib2, iclass 37, count 0 2006.189.08:18:12.27#ibcon#flushed, iclass 37, count 0 2006.189.08:18:12.27#ibcon#about to write, iclass 37, count 0 2006.189.08:18:12.27#ibcon#wrote, iclass 37, count 0 2006.189.08:18:12.27#ibcon#about to read 3, iclass 37, count 0 2006.189.08:18:12.30#ibcon#read 3, iclass 37, count 0 2006.189.08:18:12.30#ibcon#about to read 4, iclass 37, count 0 2006.189.08:18:12.30#ibcon#read 4, iclass 37, count 0 2006.189.08:18:12.30#ibcon#about to read 5, iclass 37, count 0 2006.189.08:18:12.30#ibcon#read 5, iclass 37, count 0 2006.189.08:18:12.30#ibcon#about to read 6, iclass 37, count 0 2006.189.08:18:12.30#ibcon#read 6, iclass 37, count 0 2006.189.08:18:12.30#ibcon#end of sib2, iclass 37, count 0 2006.189.08:18:12.30#ibcon#*after write, iclass 37, count 0 2006.189.08:18:12.30#ibcon#*before return 0, iclass 37, count 0 2006.189.08:18:12.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:12.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.189.08:18:12.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:18:12.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:18:12.30$vc4f8/vblo=6,752.99 2006.189.08:18:12.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.08:18:12.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.08:18:12.30#ibcon#ireg 17 cls_cnt 0 2006.189.08:18:12.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:12.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:12.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:12.30#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:18:12.30#ibcon#first serial, iclass 39, count 0 2006.189.08:18:12.30#ibcon#enter sib2, iclass 39, count 0 2006.189.08:18:12.30#ibcon#flushed, iclass 39, count 0 2006.189.08:18:12.30#ibcon#about to write, iclass 39, count 0 2006.189.08:18:12.30#ibcon#wrote, iclass 39, count 0 2006.189.08:18:12.30#ibcon#about to read 3, iclass 39, count 0 2006.189.08:18:12.32#ibcon#read 3, iclass 39, count 0 2006.189.08:18:12.32#ibcon#about to read 4, iclass 39, count 0 2006.189.08:18:12.32#ibcon#read 4, iclass 39, count 0 2006.189.08:18:12.32#ibcon#about to read 5, iclass 39, count 0 2006.189.08:18:12.32#ibcon#read 5, iclass 39, count 0 2006.189.08:18:12.32#ibcon#about to read 6, iclass 39, count 0 2006.189.08:18:12.32#ibcon#read 6, iclass 39, count 0 2006.189.08:18:12.32#ibcon#end of sib2, iclass 39, count 0 2006.189.08:18:12.32#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:18:12.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:18:12.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:18:12.32#ibcon#*before write, iclass 39, count 0 2006.189.08:18:12.32#ibcon#enter sib2, iclass 39, count 0 2006.189.08:18:12.32#ibcon#flushed, iclass 39, count 0 2006.189.08:18:12.32#ibcon#about to write, iclass 39, count 0 2006.189.08:18:12.32#ibcon#wrote, iclass 39, count 0 2006.189.08:18:12.32#ibcon#about to read 3, iclass 39, count 0 2006.189.08:18:12.36#ibcon#read 3, iclass 39, count 0 2006.189.08:18:12.36#ibcon#about to read 4, iclass 39, count 0 2006.189.08:18:12.36#ibcon#read 4, iclass 39, count 0 2006.189.08:18:12.36#ibcon#about to read 5, iclass 39, count 0 2006.189.08:18:12.36#ibcon#read 5, iclass 39, count 0 2006.189.08:18:12.36#ibcon#about to read 6, iclass 39, count 0 2006.189.08:18:12.36#ibcon#read 6, iclass 39, count 0 2006.189.08:18:12.36#ibcon#end of sib2, iclass 39, count 0 2006.189.08:18:12.36#ibcon#*after write, iclass 39, count 0 2006.189.08:18:12.36#ibcon#*before return 0, iclass 39, count 0 2006.189.08:18:12.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:12.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:18:12.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:18:12.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:18:12.36$vc4f8/vb=6,4 2006.189.08:18:12.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.189.08:18:12.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.189.08:18:12.36#ibcon#ireg 11 cls_cnt 2 2006.189.08:18:12.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:12.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:12.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:12.42#ibcon#enter wrdev, iclass 3, count 2 2006.189.08:18:12.42#ibcon#first serial, iclass 3, count 2 2006.189.08:18:12.42#ibcon#enter sib2, iclass 3, count 2 2006.189.08:18:12.42#ibcon#flushed, iclass 3, count 2 2006.189.08:18:12.42#ibcon#about to write, iclass 3, count 2 2006.189.08:18:12.42#ibcon#wrote, iclass 3, count 2 2006.189.08:18:12.42#ibcon#about to read 3, iclass 3, count 2 2006.189.08:18:12.44#ibcon#read 3, iclass 3, count 2 2006.189.08:18:12.44#ibcon#about to read 4, iclass 3, count 2 2006.189.08:18:12.44#ibcon#read 4, iclass 3, count 2 2006.189.08:18:12.44#ibcon#about to read 5, iclass 3, count 2 2006.189.08:18:12.44#ibcon#read 5, iclass 3, count 2 2006.189.08:18:12.44#ibcon#about to read 6, iclass 3, count 2 2006.189.08:18:12.44#ibcon#read 6, iclass 3, count 2 2006.189.08:18:12.44#ibcon#end of sib2, iclass 3, count 2 2006.189.08:18:12.44#ibcon#*mode == 0, iclass 3, count 2 2006.189.08:18:12.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.189.08:18:12.44#ibcon#[27=AT06-04\r\n] 2006.189.08:18:12.44#ibcon#*before write, iclass 3, count 2 2006.189.08:18:12.44#ibcon#enter sib2, iclass 3, count 2 2006.189.08:18:12.44#ibcon#flushed, iclass 3, count 2 2006.189.08:18:12.44#ibcon#about to write, iclass 3, count 2 2006.189.08:18:12.44#ibcon#wrote, iclass 3, count 2 2006.189.08:18:12.44#ibcon#about to read 3, iclass 3, count 2 2006.189.08:18:12.47#ibcon#read 3, iclass 3, count 2 2006.189.08:18:12.47#ibcon#about to read 4, iclass 3, count 2 2006.189.08:18:12.47#ibcon#read 4, iclass 3, count 2 2006.189.08:18:12.47#ibcon#about to read 5, iclass 3, count 2 2006.189.08:18:12.47#ibcon#read 5, iclass 3, count 2 2006.189.08:18:12.47#ibcon#about to read 6, iclass 3, count 2 2006.189.08:18:12.47#ibcon#read 6, iclass 3, count 2 2006.189.08:18:12.47#ibcon#end of sib2, iclass 3, count 2 2006.189.08:18:12.47#ibcon#*after write, iclass 3, count 2 2006.189.08:18:12.47#ibcon#*before return 0, iclass 3, count 2 2006.189.08:18:12.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:12.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.189.08:18:12.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.189.08:18:12.47#ibcon#ireg 7 cls_cnt 0 2006.189.08:18:12.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:12.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:12.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:12.59#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:18:12.59#ibcon#first serial, iclass 3, count 0 2006.189.08:18:12.59#ibcon#enter sib2, iclass 3, count 0 2006.189.08:18:12.59#ibcon#flushed, iclass 3, count 0 2006.189.08:18:12.59#ibcon#about to write, iclass 3, count 0 2006.189.08:18:12.59#ibcon#wrote, iclass 3, count 0 2006.189.08:18:12.59#ibcon#about to read 3, iclass 3, count 0 2006.189.08:18:12.61#ibcon#read 3, iclass 3, count 0 2006.189.08:18:12.61#ibcon#about to read 4, iclass 3, count 0 2006.189.08:18:12.61#ibcon#read 4, iclass 3, count 0 2006.189.08:18:12.61#ibcon#about to read 5, iclass 3, count 0 2006.189.08:18:12.61#ibcon#read 5, iclass 3, count 0 2006.189.08:18:12.61#ibcon#about to read 6, iclass 3, count 0 2006.189.08:18:12.61#ibcon#read 6, iclass 3, count 0 2006.189.08:18:12.61#ibcon#end of sib2, iclass 3, count 0 2006.189.08:18:12.61#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:18:12.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:18:12.61#ibcon#[27=USB\r\n] 2006.189.08:18:12.61#ibcon#*before write, iclass 3, count 0 2006.189.08:18:12.61#ibcon#enter sib2, iclass 3, count 0 2006.189.08:18:12.61#ibcon#flushed, iclass 3, count 0 2006.189.08:18:12.61#ibcon#about to write, iclass 3, count 0 2006.189.08:18:12.61#ibcon#wrote, iclass 3, count 0 2006.189.08:18:12.61#ibcon#about to read 3, iclass 3, count 0 2006.189.08:18:12.64#ibcon#read 3, iclass 3, count 0 2006.189.08:18:12.64#ibcon#about to read 4, iclass 3, count 0 2006.189.08:18:12.64#ibcon#read 4, iclass 3, count 0 2006.189.08:18:12.64#ibcon#about to read 5, iclass 3, count 0 2006.189.08:18:12.64#ibcon#read 5, iclass 3, count 0 2006.189.08:18:12.64#ibcon#about to read 6, iclass 3, count 0 2006.189.08:18:12.64#ibcon#read 6, iclass 3, count 0 2006.189.08:18:12.64#ibcon#end of sib2, iclass 3, count 0 2006.189.08:18:12.64#ibcon#*after write, iclass 3, count 0 2006.189.08:18:12.64#ibcon#*before return 0, iclass 3, count 0 2006.189.08:18:12.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:12.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.189.08:18:12.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:18:12.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:18:12.64$vc4f8/vabw=wide 2006.189.08:18:12.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.189.08:18:12.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.189.08:18:12.64#ibcon#ireg 8 cls_cnt 0 2006.189.08:18:12.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:12.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:12.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:12.64#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:18:12.64#ibcon#first serial, iclass 5, count 0 2006.189.08:18:12.64#ibcon#enter sib2, iclass 5, count 0 2006.189.08:18:12.64#ibcon#flushed, iclass 5, count 0 2006.189.08:18:12.64#ibcon#about to write, iclass 5, count 0 2006.189.08:18:12.64#ibcon#wrote, iclass 5, count 0 2006.189.08:18:12.64#ibcon#about to read 3, iclass 5, count 0 2006.189.08:18:12.66#ibcon#read 3, iclass 5, count 0 2006.189.08:18:12.66#ibcon#about to read 4, iclass 5, count 0 2006.189.08:18:12.66#ibcon#read 4, iclass 5, count 0 2006.189.08:18:12.66#ibcon#about to read 5, iclass 5, count 0 2006.189.08:18:12.66#ibcon#read 5, iclass 5, count 0 2006.189.08:18:12.66#ibcon#about to read 6, iclass 5, count 0 2006.189.08:18:12.66#ibcon#read 6, iclass 5, count 0 2006.189.08:18:12.66#ibcon#end of sib2, iclass 5, count 0 2006.189.08:18:12.66#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:18:12.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:18:12.66#ibcon#[25=BW32\r\n] 2006.189.08:18:12.66#ibcon#*before write, iclass 5, count 0 2006.189.08:18:12.66#ibcon#enter sib2, iclass 5, count 0 2006.189.08:18:12.66#ibcon#flushed, iclass 5, count 0 2006.189.08:18:12.66#ibcon#about to write, iclass 5, count 0 2006.189.08:18:12.66#ibcon#wrote, iclass 5, count 0 2006.189.08:18:12.66#ibcon#about to read 3, iclass 5, count 0 2006.189.08:18:12.69#ibcon#read 3, iclass 5, count 0 2006.189.08:18:12.69#ibcon#about to read 4, iclass 5, count 0 2006.189.08:18:12.69#ibcon#read 4, iclass 5, count 0 2006.189.08:18:12.69#ibcon#about to read 5, iclass 5, count 0 2006.189.08:18:12.69#ibcon#read 5, iclass 5, count 0 2006.189.08:18:12.69#ibcon#about to read 6, iclass 5, count 0 2006.189.08:18:12.69#ibcon#read 6, iclass 5, count 0 2006.189.08:18:12.69#ibcon#end of sib2, iclass 5, count 0 2006.189.08:18:12.69#ibcon#*after write, iclass 5, count 0 2006.189.08:18:12.69#ibcon#*before return 0, iclass 5, count 0 2006.189.08:18:12.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:12.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.189.08:18:12.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:18:12.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:18:12.69$vc4f8/vbbw=wide 2006.189.08:18:12.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.08:18:12.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.08:18:12.69#ibcon#ireg 8 cls_cnt 0 2006.189.08:18:12.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:18:12.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:18:12.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:18:12.76#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:18:12.76#ibcon#first serial, iclass 7, count 0 2006.189.08:18:12.76#ibcon#enter sib2, iclass 7, count 0 2006.189.08:18:12.76#ibcon#flushed, iclass 7, count 0 2006.189.08:18:12.76#ibcon#about to write, iclass 7, count 0 2006.189.08:18:12.76#ibcon#wrote, iclass 7, count 0 2006.189.08:18:12.76#ibcon#about to read 3, iclass 7, count 0 2006.189.08:18:12.78#ibcon#read 3, iclass 7, count 0 2006.189.08:18:12.78#ibcon#about to read 4, iclass 7, count 0 2006.189.08:18:12.78#ibcon#read 4, iclass 7, count 0 2006.189.08:18:12.78#ibcon#about to read 5, iclass 7, count 0 2006.189.08:18:12.78#ibcon#read 5, iclass 7, count 0 2006.189.08:18:12.78#ibcon#about to read 6, iclass 7, count 0 2006.189.08:18:12.78#ibcon#read 6, iclass 7, count 0 2006.189.08:18:12.78#ibcon#end of sib2, iclass 7, count 0 2006.189.08:18:12.78#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:18:12.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:18:12.78#ibcon#[27=BW32\r\n] 2006.189.08:18:12.78#ibcon#*before write, iclass 7, count 0 2006.189.08:18:12.78#ibcon#enter sib2, iclass 7, count 0 2006.189.08:18:12.78#ibcon#flushed, iclass 7, count 0 2006.189.08:18:12.78#ibcon#about to write, iclass 7, count 0 2006.189.08:18:12.78#ibcon#wrote, iclass 7, count 0 2006.189.08:18:12.78#ibcon#about to read 3, iclass 7, count 0 2006.189.08:18:12.81#ibcon#read 3, iclass 7, count 0 2006.189.08:18:12.81#ibcon#about to read 4, iclass 7, count 0 2006.189.08:18:12.81#ibcon#read 4, iclass 7, count 0 2006.189.08:18:12.81#ibcon#about to read 5, iclass 7, count 0 2006.189.08:18:12.81#ibcon#read 5, iclass 7, count 0 2006.189.08:18:12.81#ibcon#about to read 6, iclass 7, count 0 2006.189.08:18:12.81#ibcon#read 6, iclass 7, count 0 2006.189.08:18:12.81#ibcon#end of sib2, iclass 7, count 0 2006.189.08:18:12.81#ibcon#*after write, iclass 7, count 0 2006.189.08:18:12.81#ibcon#*before return 0, iclass 7, count 0 2006.189.08:18:12.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:18:12.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:18:12.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:18:12.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:18:12.81$4f8m12a/ifd4f 2006.189.08:18:12.81$ifd4f/lo= 2006.189.08:18:12.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:18:12.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:18:12.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:18:12.81$ifd4f/patch= 2006.189.08:18:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:18:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:18:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:18:12.81$4f8m12a/"form=m,16.000,1:2 2006.189.08:18:12.81$4f8m12a/"tpicd 2006.189.08:18:12.81$4f8m12a/echo=off 2006.189.08:18:12.81$4f8m12a/xlog=off 2006.189.08:18:12.81:!2006.189.08:20:00 2006.189.08:18:25.13#trakl#Source acquired 2006.189.08:18:27.13#flagr#flagr/antenna,acquired 2006.189.08:20:00.00:preob 2006.189.08:20:01.14/onsource/TRACKING 2006.189.08:20:01.14:!2006.189.08:20:10 2006.189.08:20:10.00:data_valid=on 2006.189.08:20:10.00:midob 2006.189.08:20:10.14/onsource/TRACKING 2006.189.08:20:10.14/wx/25.35,1009.2,91 2006.189.08:20:10.29/cable/+6.4573E-03 2006.189.08:20:11.38/va/01,08,usb,yes,28,30 2006.189.08:20:11.38/va/02,07,usb,yes,28,30 2006.189.08:20:11.38/va/03,06,usb,yes,30,30 2006.189.08:20:11.38/va/04,07,usb,yes,29,31 2006.189.08:20:11.38/va/05,07,usb,yes,31,33 2006.189.08:20:11.38/va/06,06,usb,yes,30,30 2006.189.08:20:11.38/va/07,06,usb,yes,30,30 2006.189.08:20:11.38/va/08,06,usb,yes,33,32 2006.189.08:20:11.61/valo/01,532.99,yes,locked 2006.189.08:20:11.61/valo/02,572.99,yes,locked 2006.189.08:20:11.61/valo/03,672.99,yes,locked 2006.189.08:20:11.61/valo/04,832.99,yes,locked 2006.189.08:20:11.61/valo/05,652.99,yes,locked 2006.189.08:20:11.61/valo/06,772.99,yes,locked 2006.189.08:20:11.61/valo/07,832.99,yes,locked 2006.189.08:20:11.61/valo/08,852.99,yes,locked 2006.189.08:20:12.70/vb/01,04,usb,yes,28,27 2006.189.08:20:12.70/vb/02,04,usb,yes,30,32 2006.189.08:20:12.70/vb/03,04,usb,yes,27,30 2006.189.08:20:12.70/vb/04,04,usb,yes,28,28 2006.189.08:20:12.70/vb/05,04,usb,yes,26,30 2006.189.08:20:12.70/vb/06,04,usb,yes,27,30 2006.189.08:20:12.70/vb/07,04,usb,yes,29,29 2006.189.08:20:12.70/vb/08,04,usb,yes,27,30 2006.189.08:20:12.94/vblo/01,632.99,yes,locked 2006.189.08:20:12.94/vblo/02,640.99,yes,locked 2006.189.08:20:12.94/vblo/03,656.99,yes,locked 2006.189.08:20:12.94/vblo/04,712.99,yes,locked 2006.189.08:20:12.94/vblo/05,744.99,yes,locked 2006.189.08:20:12.94/vblo/06,752.99,yes,locked 2006.189.08:20:12.94/vblo/07,734.99,yes,locked 2006.189.08:20:12.94/vblo/08,744.99,yes,locked 2006.189.08:20:13.09/vabw/8 2006.189.08:20:13.24/vbbw/8 2006.189.08:20:13.38/xfe/off,on,14.7 2006.189.08:20:13.75/ifatt/23,28,28,28 2006.189.08:20:14.08/fmout-gps/S +2.99E-07 2006.189.08:20:14.17:!2006.189.08:21:20 2006.189.08:21:20.01:data_valid=off 2006.189.08:21:20.02:postob 2006.189.08:21:20.12/cable/+6.4555E-03 2006.189.08:21:20.13/wx/25.33,1009.2,91 2006.189.08:21:21.07/fmout-gps/S +2.99E-07 2006.189.08:21:21.08:scan_name=189-0823,k06189,60 2006.189.08:21:21.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.189.08:21:22.14#flagr#flagr/antenna,new-source 2006.189.08:21:22.15:checkk5 2006.189.08:21:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:21:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:21:23.30/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:21:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:21:24.05/chk_obsdata//k5ts1/T1890820??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.189.08:21:24.43/chk_obsdata//k5ts2/T1890820??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.189.08:21:24.81/chk_obsdata//k5ts3/T1890820??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.189.08:21:25.18/chk_obsdata//k5ts4/T1890820??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.189.08:21:25.88/k5log//k5ts1_log_newline 2006.189.08:21:26.58/k5log//k5ts2_log_newline 2006.189.08:21:27.28/k5log//k5ts3_log_newline 2006.189.08:21:27.97/k5log//k5ts4_log_newline 2006.189.08:21:28.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:21:28.00:4f8m12a=3 2006.189.08:21:28.00$4f8m12a/echo=on 2006.189.08:21:28.00$4f8m12a/pcalon 2006.189.08:21:28.00$pcalon/"no phase cal control is implemented here 2006.189.08:21:28.00$4f8m12a/"tpicd=stop 2006.189.08:21:28.00$4f8m12a/vc4f8 2006.189.08:21:28.00$vc4f8/valo=1,532.99 2006.189.08:21:28.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.189.08:21:28.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.189.08:21:28.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:28.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:21:28.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:21:28.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:21:28.00#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:21:28.00#ibcon#first serial, iclass 16, count 0 2006.189.08:21:28.00#ibcon#enter sib2, iclass 16, count 0 2006.189.08:21:28.00#ibcon#flushed, iclass 16, count 0 2006.189.08:21:28.00#ibcon#about to write, iclass 16, count 0 2006.189.08:21:28.00#ibcon#wrote, iclass 16, count 0 2006.189.08:21:28.00#ibcon#about to read 3, iclass 16, count 0 2006.189.08:21:28.01#ibcon#read 3, iclass 16, count 0 2006.189.08:21:28.01#ibcon#about to read 4, iclass 16, count 0 2006.189.08:21:28.01#ibcon#read 4, iclass 16, count 0 2006.189.08:21:28.01#ibcon#about to read 5, iclass 16, count 0 2006.189.08:21:28.01#ibcon#read 5, iclass 16, count 0 2006.189.08:21:28.01#ibcon#about to read 6, iclass 16, count 0 2006.189.08:21:28.01#ibcon#read 6, iclass 16, count 0 2006.189.08:21:28.01#ibcon#end of sib2, iclass 16, count 0 2006.189.08:21:28.01#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:21:28.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:21:28.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:21:28.01#ibcon#*before write, iclass 16, count 0 2006.189.08:21:28.01#ibcon#enter sib2, iclass 16, count 0 2006.189.08:21:28.01#ibcon#flushed, iclass 16, count 0 2006.189.08:21:28.01#ibcon#about to write, iclass 16, count 0 2006.189.08:21:28.01#ibcon#wrote, iclass 16, count 0 2006.189.08:21:28.01#ibcon#about to read 3, iclass 16, count 0 2006.189.08:21:28.06#ibcon#read 3, iclass 16, count 0 2006.189.08:21:28.06#ibcon#about to read 4, iclass 16, count 0 2006.189.08:21:28.06#ibcon#read 4, iclass 16, count 0 2006.189.08:21:28.06#ibcon#about to read 5, iclass 16, count 0 2006.189.08:21:28.06#ibcon#read 5, iclass 16, count 0 2006.189.08:21:28.06#ibcon#about to read 6, iclass 16, count 0 2006.189.08:21:28.06#ibcon#read 6, iclass 16, count 0 2006.189.08:21:28.06#ibcon#end of sib2, iclass 16, count 0 2006.189.08:21:28.06#ibcon#*after write, iclass 16, count 0 2006.189.08:21:28.06#ibcon#*before return 0, iclass 16, count 0 2006.189.08:21:28.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:21:28.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.189.08:21:28.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:21:28.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:21:28.06$vc4f8/va=1,8 2006.189.08:21:28.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.189.08:21:28.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.189.08:21:28.06#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:28.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:21:28.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:21:28.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:21:28.06#ibcon#enter wrdev, iclass 18, count 2 2006.189.08:21:28.06#ibcon#first serial, iclass 18, count 2 2006.189.08:21:28.06#ibcon#enter sib2, iclass 18, count 2 2006.189.08:21:28.06#ibcon#flushed, iclass 18, count 2 2006.189.08:21:28.06#ibcon#about to write, iclass 18, count 2 2006.189.08:21:28.06#ibcon#wrote, iclass 18, count 2 2006.189.08:21:28.06#ibcon#about to read 3, iclass 18, count 2 2006.189.08:21:28.08#ibcon#read 3, iclass 18, count 2 2006.189.08:21:28.08#ibcon#about to read 4, iclass 18, count 2 2006.189.08:21:28.08#ibcon#read 4, iclass 18, count 2 2006.189.08:21:28.08#ibcon#about to read 5, iclass 18, count 2 2006.189.08:21:28.08#ibcon#read 5, iclass 18, count 2 2006.189.08:21:28.08#ibcon#about to read 6, iclass 18, count 2 2006.189.08:21:28.08#ibcon#read 6, iclass 18, count 2 2006.189.08:21:28.08#ibcon#end of sib2, iclass 18, count 2 2006.189.08:21:28.08#ibcon#*mode == 0, iclass 18, count 2 2006.189.08:21:28.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.189.08:21:28.08#ibcon#[25=AT01-08\r\n] 2006.189.08:21:28.08#ibcon#*before write, iclass 18, count 2 2006.189.08:21:28.08#ibcon#enter sib2, iclass 18, count 2 2006.189.08:21:28.08#ibcon#flushed, iclass 18, count 2 2006.189.08:21:28.08#ibcon#about to write, iclass 18, count 2 2006.189.08:21:28.08#ibcon#wrote, iclass 18, count 2 2006.189.08:21:28.08#ibcon#about to read 3, iclass 18, count 2 2006.189.08:21:28.12#ibcon#read 3, iclass 18, count 2 2006.189.08:21:28.12#ibcon#about to read 4, iclass 18, count 2 2006.189.08:21:28.12#ibcon#read 4, iclass 18, count 2 2006.189.08:21:28.12#ibcon#about to read 5, iclass 18, count 2 2006.189.08:21:28.12#ibcon#read 5, iclass 18, count 2 2006.189.08:21:28.12#ibcon#about to read 6, iclass 18, count 2 2006.189.08:21:28.12#ibcon#read 6, iclass 18, count 2 2006.189.08:21:28.12#ibcon#end of sib2, iclass 18, count 2 2006.189.08:21:28.12#ibcon#*after write, iclass 18, count 2 2006.189.08:21:28.12#ibcon#*before return 0, iclass 18, count 2 2006.189.08:21:28.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:21:28.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.189.08:21:28.12#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.189.08:21:28.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:28.12#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:21:28.24#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:21:28.24#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:21:28.24#ibcon#enter wrdev, iclass 18, count 0 2006.189.08:21:28.24#ibcon#first serial, iclass 18, count 0 2006.189.08:21:28.24#ibcon#enter sib2, iclass 18, count 0 2006.189.08:21:28.24#ibcon#flushed, iclass 18, count 0 2006.189.08:21:28.24#ibcon#about to write, iclass 18, count 0 2006.189.08:21:28.24#ibcon#wrote, iclass 18, count 0 2006.189.08:21:28.24#ibcon#about to read 3, iclass 18, count 0 2006.189.08:21:28.26#ibcon#read 3, iclass 18, count 0 2006.189.08:21:28.26#ibcon#about to read 4, iclass 18, count 0 2006.189.08:21:28.26#ibcon#read 4, iclass 18, count 0 2006.189.08:21:28.26#ibcon#about to read 5, iclass 18, count 0 2006.189.08:21:28.26#ibcon#read 5, iclass 18, count 0 2006.189.08:21:28.26#ibcon#about to read 6, iclass 18, count 0 2006.189.08:21:28.26#ibcon#read 6, iclass 18, count 0 2006.189.08:21:28.26#ibcon#end of sib2, iclass 18, count 0 2006.189.08:21:28.26#ibcon#*mode == 0, iclass 18, count 0 2006.189.08:21:28.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.08:21:28.26#ibcon#[25=USB\r\n] 2006.189.08:21:28.26#ibcon#*before write, iclass 18, count 0 2006.189.08:21:28.26#ibcon#enter sib2, iclass 18, count 0 2006.189.08:21:28.26#ibcon#flushed, iclass 18, count 0 2006.189.08:21:28.26#ibcon#about to write, iclass 18, count 0 2006.189.08:21:28.26#ibcon#wrote, iclass 18, count 0 2006.189.08:21:28.26#ibcon#about to read 3, iclass 18, count 0 2006.189.08:21:28.28#ibcon#read 3, iclass 18, count 0 2006.189.08:21:28.28#ibcon#about to read 4, iclass 18, count 0 2006.189.08:21:28.28#ibcon#read 4, iclass 18, count 0 2006.189.08:21:28.28#ibcon#about to read 5, iclass 18, count 0 2006.189.08:21:28.28#ibcon#read 5, iclass 18, count 0 2006.189.08:21:28.28#ibcon#about to read 6, iclass 18, count 0 2006.189.08:21:28.28#ibcon#read 6, iclass 18, count 0 2006.189.08:21:28.28#ibcon#end of sib2, iclass 18, count 0 2006.189.08:21:28.28#ibcon#*after write, iclass 18, count 0 2006.189.08:21:28.28#ibcon#*before return 0, iclass 18, count 0 2006.189.08:21:28.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:21:28.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.189.08:21:28.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.08:21:28.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.08:21:28.28$vc4f8/valo=2,572.99 2006.189.08:21:28.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.08:21:28.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.08:21:28.28#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:28.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:28.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:28.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:28.28#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:21:28.28#ibcon#first serial, iclass 20, count 0 2006.189.08:21:28.28#ibcon#enter sib2, iclass 20, count 0 2006.189.08:21:28.28#ibcon#flushed, iclass 20, count 0 2006.189.08:21:28.28#ibcon#about to write, iclass 20, count 0 2006.189.08:21:28.28#ibcon#wrote, iclass 20, count 0 2006.189.08:21:28.28#ibcon#about to read 3, iclass 20, count 0 2006.189.08:21:28.30#ibcon#read 3, iclass 20, count 0 2006.189.08:21:28.30#ibcon#about to read 4, iclass 20, count 0 2006.189.08:21:28.30#ibcon#read 4, iclass 20, count 0 2006.189.08:21:28.30#ibcon#about to read 5, iclass 20, count 0 2006.189.08:21:28.30#ibcon#read 5, iclass 20, count 0 2006.189.08:21:28.30#ibcon#about to read 6, iclass 20, count 0 2006.189.08:21:28.30#ibcon#read 6, iclass 20, count 0 2006.189.08:21:28.30#ibcon#end of sib2, iclass 20, count 0 2006.189.08:21:28.30#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:21:28.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:21:28.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:21:28.30#ibcon#*before write, iclass 20, count 0 2006.189.08:21:28.30#ibcon#enter sib2, iclass 20, count 0 2006.189.08:21:28.30#ibcon#flushed, iclass 20, count 0 2006.189.08:21:28.30#ibcon#about to write, iclass 20, count 0 2006.189.08:21:28.30#ibcon#wrote, iclass 20, count 0 2006.189.08:21:28.30#ibcon#about to read 3, iclass 20, count 0 2006.189.08:21:28.35#ibcon#read 3, iclass 20, count 0 2006.189.08:21:28.35#ibcon#about to read 4, iclass 20, count 0 2006.189.08:21:28.35#ibcon#read 4, iclass 20, count 0 2006.189.08:21:28.35#ibcon#about to read 5, iclass 20, count 0 2006.189.08:21:28.35#ibcon#read 5, iclass 20, count 0 2006.189.08:21:28.35#ibcon#about to read 6, iclass 20, count 0 2006.189.08:21:28.35#ibcon#read 6, iclass 20, count 0 2006.189.08:21:28.35#ibcon#end of sib2, iclass 20, count 0 2006.189.08:21:28.35#ibcon#*after write, iclass 20, count 0 2006.189.08:21:28.35#ibcon#*before return 0, iclass 20, count 0 2006.189.08:21:28.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:28.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:28.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:21:28.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:21:28.35$vc4f8/va=2,7 2006.189.08:21:28.35#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.08:21:28.35#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.08:21:28.35#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:28.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:28.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:28.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:28.39#ibcon#enter wrdev, iclass 22, count 2 2006.189.08:21:28.39#ibcon#first serial, iclass 22, count 2 2006.189.08:21:28.39#ibcon#enter sib2, iclass 22, count 2 2006.189.08:21:28.39#ibcon#flushed, iclass 22, count 2 2006.189.08:21:28.39#ibcon#about to write, iclass 22, count 2 2006.189.08:21:28.39#ibcon#wrote, iclass 22, count 2 2006.189.08:21:28.39#ibcon#about to read 3, iclass 22, count 2 2006.189.08:21:28.41#ibcon#read 3, iclass 22, count 2 2006.189.08:21:28.41#ibcon#about to read 4, iclass 22, count 2 2006.189.08:21:28.41#ibcon#read 4, iclass 22, count 2 2006.189.08:21:28.41#ibcon#about to read 5, iclass 22, count 2 2006.189.08:21:28.41#ibcon#read 5, iclass 22, count 2 2006.189.08:21:28.41#ibcon#about to read 6, iclass 22, count 2 2006.189.08:21:28.41#ibcon#read 6, iclass 22, count 2 2006.189.08:21:28.41#ibcon#end of sib2, iclass 22, count 2 2006.189.08:21:28.41#ibcon#*mode == 0, iclass 22, count 2 2006.189.08:21:28.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.08:21:28.41#ibcon#[25=AT02-07\r\n] 2006.189.08:21:28.41#ibcon#*before write, iclass 22, count 2 2006.189.08:21:28.41#ibcon#enter sib2, iclass 22, count 2 2006.189.08:21:28.41#ibcon#flushed, iclass 22, count 2 2006.189.08:21:28.41#ibcon#about to write, iclass 22, count 2 2006.189.08:21:28.41#ibcon#wrote, iclass 22, count 2 2006.189.08:21:28.41#ibcon#about to read 3, iclass 22, count 2 2006.189.08:21:28.44#ibcon#read 3, iclass 22, count 2 2006.189.08:21:28.44#ibcon#about to read 4, iclass 22, count 2 2006.189.08:21:28.44#ibcon#read 4, iclass 22, count 2 2006.189.08:21:28.44#ibcon#about to read 5, iclass 22, count 2 2006.189.08:21:28.44#ibcon#read 5, iclass 22, count 2 2006.189.08:21:28.44#ibcon#about to read 6, iclass 22, count 2 2006.189.08:21:28.44#ibcon#read 6, iclass 22, count 2 2006.189.08:21:28.44#ibcon#end of sib2, iclass 22, count 2 2006.189.08:21:28.44#ibcon#*after write, iclass 22, count 2 2006.189.08:21:28.44#ibcon#*before return 0, iclass 22, count 2 2006.189.08:21:28.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:28.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:28.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.08:21:28.44#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:28.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:28.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:28.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:28.56#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:21:28.56#ibcon#first serial, iclass 22, count 0 2006.189.08:21:28.56#ibcon#enter sib2, iclass 22, count 0 2006.189.08:21:28.56#ibcon#flushed, iclass 22, count 0 2006.189.08:21:28.56#ibcon#about to write, iclass 22, count 0 2006.189.08:21:28.56#ibcon#wrote, iclass 22, count 0 2006.189.08:21:28.56#ibcon#about to read 3, iclass 22, count 0 2006.189.08:21:28.58#ibcon#read 3, iclass 22, count 0 2006.189.08:21:28.58#ibcon#about to read 4, iclass 22, count 0 2006.189.08:21:28.58#ibcon#read 4, iclass 22, count 0 2006.189.08:21:28.58#ibcon#about to read 5, iclass 22, count 0 2006.189.08:21:28.58#ibcon#read 5, iclass 22, count 0 2006.189.08:21:28.58#ibcon#about to read 6, iclass 22, count 0 2006.189.08:21:28.58#ibcon#read 6, iclass 22, count 0 2006.189.08:21:28.58#ibcon#end of sib2, iclass 22, count 0 2006.189.08:21:28.58#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:21:28.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:21:28.58#ibcon#[25=USB\r\n] 2006.189.08:21:28.58#ibcon#*before write, iclass 22, count 0 2006.189.08:21:28.58#ibcon#enter sib2, iclass 22, count 0 2006.189.08:21:28.58#ibcon#flushed, iclass 22, count 0 2006.189.08:21:28.58#ibcon#about to write, iclass 22, count 0 2006.189.08:21:28.58#ibcon#wrote, iclass 22, count 0 2006.189.08:21:28.58#ibcon#about to read 3, iclass 22, count 0 2006.189.08:21:28.61#ibcon#read 3, iclass 22, count 0 2006.189.08:21:28.61#ibcon#about to read 4, iclass 22, count 0 2006.189.08:21:28.61#ibcon#read 4, iclass 22, count 0 2006.189.08:21:28.61#ibcon#about to read 5, iclass 22, count 0 2006.189.08:21:28.61#ibcon#read 5, iclass 22, count 0 2006.189.08:21:28.61#ibcon#about to read 6, iclass 22, count 0 2006.189.08:21:28.61#ibcon#read 6, iclass 22, count 0 2006.189.08:21:28.61#ibcon#end of sib2, iclass 22, count 0 2006.189.08:21:28.61#ibcon#*after write, iclass 22, count 0 2006.189.08:21:28.61#ibcon#*before return 0, iclass 22, count 0 2006.189.08:21:28.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:28.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:28.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:21:28.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:21:28.61$vc4f8/valo=3,672.99 2006.189.08:21:28.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.08:21:28.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.08:21:28.61#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:28.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:28.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:28.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:28.61#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:21:28.61#ibcon#first serial, iclass 24, count 0 2006.189.08:21:28.61#ibcon#enter sib2, iclass 24, count 0 2006.189.08:21:28.61#ibcon#flushed, iclass 24, count 0 2006.189.08:21:28.61#ibcon#about to write, iclass 24, count 0 2006.189.08:21:28.61#ibcon#wrote, iclass 24, count 0 2006.189.08:21:28.61#ibcon#about to read 3, iclass 24, count 0 2006.189.08:21:28.63#ibcon#read 3, iclass 24, count 0 2006.189.08:21:28.63#ibcon#about to read 4, iclass 24, count 0 2006.189.08:21:28.63#ibcon#read 4, iclass 24, count 0 2006.189.08:21:28.63#ibcon#about to read 5, iclass 24, count 0 2006.189.08:21:28.63#ibcon#read 5, iclass 24, count 0 2006.189.08:21:28.63#ibcon#about to read 6, iclass 24, count 0 2006.189.08:21:28.63#ibcon#read 6, iclass 24, count 0 2006.189.08:21:28.63#ibcon#end of sib2, iclass 24, count 0 2006.189.08:21:28.63#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:21:28.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:21:28.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:21:28.63#ibcon#*before write, iclass 24, count 0 2006.189.08:21:28.63#ibcon#enter sib2, iclass 24, count 0 2006.189.08:21:28.63#ibcon#flushed, iclass 24, count 0 2006.189.08:21:28.63#ibcon#about to write, iclass 24, count 0 2006.189.08:21:28.63#ibcon#wrote, iclass 24, count 0 2006.189.08:21:28.63#ibcon#about to read 3, iclass 24, count 0 2006.189.08:21:28.67#ibcon#read 3, iclass 24, count 0 2006.189.08:21:28.67#ibcon#about to read 4, iclass 24, count 0 2006.189.08:21:28.67#ibcon#read 4, iclass 24, count 0 2006.189.08:21:28.67#ibcon#about to read 5, iclass 24, count 0 2006.189.08:21:28.67#ibcon#read 5, iclass 24, count 0 2006.189.08:21:28.67#ibcon#about to read 6, iclass 24, count 0 2006.189.08:21:28.67#ibcon#read 6, iclass 24, count 0 2006.189.08:21:28.67#ibcon#end of sib2, iclass 24, count 0 2006.189.08:21:28.67#ibcon#*after write, iclass 24, count 0 2006.189.08:21:28.67#ibcon#*before return 0, iclass 24, count 0 2006.189.08:21:28.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:28.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:28.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:21:28.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:21:28.67$vc4f8/va=3,6 2006.189.08:21:28.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.08:21:28.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.08:21:28.67#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:28.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:28.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:28.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:28.73#ibcon#enter wrdev, iclass 26, count 2 2006.189.08:21:28.73#ibcon#first serial, iclass 26, count 2 2006.189.08:21:28.73#ibcon#enter sib2, iclass 26, count 2 2006.189.08:21:28.73#ibcon#flushed, iclass 26, count 2 2006.189.08:21:28.73#ibcon#about to write, iclass 26, count 2 2006.189.08:21:28.73#ibcon#wrote, iclass 26, count 2 2006.189.08:21:28.73#ibcon#about to read 3, iclass 26, count 2 2006.189.08:21:28.75#ibcon#read 3, iclass 26, count 2 2006.189.08:21:28.75#ibcon#about to read 4, iclass 26, count 2 2006.189.08:21:28.75#ibcon#read 4, iclass 26, count 2 2006.189.08:21:28.75#ibcon#about to read 5, iclass 26, count 2 2006.189.08:21:28.75#ibcon#read 5, iclass 26, count 2 2006.189.08:21:28.75#ibcon#about to read 6, iclass 26, count 2 2006.189.08:21:28.75#ibcon#read 6, iclass 26, count 2 2006.189.08:21:28.75#ibcon#end of sib2, iclass 26, count 2 2006.189.08:21:28.75#ibcon#*mode == 0, iclass 26, count 2 2006.189.08:21:28.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.08:21:28.75#ibcon#[25=AT03-06\r\n] 2006.189.08:21:28.75#ibcon#*before write, iclass 26, count 2 2006.189.08:21:28.75#ibcon#enter sib2, iclass 26, count 2 2006.189.08:21:28.75#ibcon#flushed, iclass 26, count 2 2006.189.08:21:28.75#ibcon#about to write, iclass 26, count 2 2006.189.08:21:28.75#ibcon#wrote, iclass 26, count 2 2006.189.08:21:28.75#ibcon#about to read 3, iclass 26, count 2 2006.189.08:21:28.78#ibcon#read 3, iclass 26, count 2 2006.189.08:21:28.78#ibcon#about to read 4, iclass 26, count 2 2006.189.08:21:28.78#ibcon#read 4, iclass 26, count 2 2006.189.08:21:28.78#ibcon#about to read 5, iclass 26, count 2 2006.189.08:21:28.78#ibcon#read 5, iclass 26, count 2 2006.189.08:21:28.78#ibcon#about to read 6, iclass 26, count 2 2006.189.08:21:28.78#ibcon#read 6, iclass 26, count 2 2006.189.08:21:28.78#ibcon#end of sib2, iclass 26, count 2 2006.189.08:21:28.78#ibcon#*after write, iclass 26, count 2 2006.189.08:21:28.78#ibcon#*before return 0, iclass 26, count 2 2006.189.08:21:28.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:28.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:28.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.08:21:28.78#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:28.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:28.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:28.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:28.90#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:21:28.90#ibcon#first serial, iclass 26, count 0 2006.189.08:21:28.90#ibcon#enter sib2, iclass 26, count 0 2006.189.08:21:28.90#ibcon#flushed, iclass 26, count 0 2006.189.08:21:28.90#ibcon#about to write, iclass 26, count 0 2006.189.08:21:28.90#ibcon#wrote, iclass 26, count 0 2006.189.08:21:28.90#ibcon#about to read 3, iclass 26, count 0 2006.189.08:21:28.92#ibcon#read 3, iclass 26, count 0 2006.189.08:21:28.92#ibcon#about to read 4, iclass 26, count 0 2006.189.08:21:28.92#ibcon#read 4, iclass 26, count 0 2006.189.08:21:28.92#ibcon#about to read 5, iclass 26, count 0 2006.189.08:21:28.92#ibcon#read 5, iclass 26, count 0 2006.189.08:21:28.92#ibcon#about to read 6, iclass 26, count 0 2006.189.08:21:28.92#ibcon#read 6, iclass 26, count 0 2006.189.08:21:28.92#ibcon#end of sib2, iclass 26, count 0 2006.189.08:21:28.92#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:21:28.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:21:28.92#ibcon#[25=USB\r\n] 2006.189.08:21:28.92#ibcon#*before write, iclass 26, count 0 2006.189.08:21:28.92#ibcon#enter sib2, iclass 26, count 0 2006.189.08:21:28.92#ibcon#flushed, iclass 26, count 0 2006.189.08:21:28.92#ibcon#about to write, iclass 26, count 0 2006.189.08:21:28.92#ibcon#wrote, iclass 26, count 0 2006.189.08:21:28.92#ibcon#about to read 3, iclass 26, count 0 2006.189.08:21:28.95#ibcon#read 3, iclass 26, count 0 2006.189.08:21:28.95#ibcon#about to read 4, iclass 26, count 0 2006.189.08:21:28.95#ibcon#read 4, iclass 26, count 0 2006.189.08:21:28.95#ibcon#about to read 5, iclass 26, count 0 2006.189.08:21:28.95#ibcon#read 5, iclass 26, count 0 2006.189.08:21:28.95#ibcon#about to read 6, iclass 26, count 0 2006.189.08:21:28.95#ibcon#read 6, iclass 26, count 0 2006.189.08:21:28.95#ibcon#end of sib2, iclass 26, count 0 2006.189.08:21:28.95#ibcon#*after write, iclass 26, count 0 2006.189.08:21:28.95#ibcon#*before return 0, iclass 26, count 0 2006.189.08:21:28.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:28.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:28.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:21:28.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:21:28.95$vc4f8/valo=4,832.99 2006.189.08:21:28.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.08:21:28.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.08:21:28.95#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:28.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:28.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:28.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:28.95#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:21:28.95#ibcon#first serial, iclass 28, count 0 2006.189.08:21:28.95#ibcon#enter sib2, iclass 28, count 0 2006.189.08:21:28.95#ibcon#flushed, iclass 28, count 0 2006.189.08:21:28.95#ibcon#about to write, iclass 28, count 0 2006.189.08:21:28.95#ibcon#wrote, iclass 28, count 0 2006.189.08:21:28.95#ibcon#about to read 3, iclass 28, count 0 2006.189.08:21:28.97#ibcon#read 3, iclass 28, count 0 2006.189.08:21:28.97#ibcon#about to read 4, iclass 28, count 0 2006.189.08:21:28.97#ibcon#read 4, iclass 28, count 0 2006.189.08:21:28.97#ibcon#about to read 5, iclass 28, count 0 2006.189.08:21:28.97#ibcon#read 5, iclass 28, count 0 2006.189.08:21:28.97#ibcon#about to read 6, iclass 28, count 0 2006.189.08:21:28.97#ibcon#read 6, iclass 28, count 0 2006.189.08:21:28.97#ibcon#end of sib2, iclass 28, count 0 2006.189.08:21:28.97#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:21:28.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:21:28.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:21:28.97#ibcon#*before write, iclass 28, count 0 2006.189.08:21:28.97#ibcon#enter sib2, iclass 28, count 0 2006.189.08:21:28.97#ibcon#flushed, iclass 28, count 0 2006.189.08:21:28.97#ibcon#about to write, iclass 28, count 0 2006.189.08:21:28.97#ibcon#wrote, iclass 28, count 0 2006.189.08:21:28.97#ibcon#about to read 3, iclass 28, count 0 2006.189.08:21:29.01#ibcon#read 3, iclass 28, count 0 2006.189.08:21:29.01#ibcon#about to read 4, iclass 28, count 0 2006.189.08:21:29.01#ibcon#read 4, iclass 28, count 0 2006.189.08:21:29.01#ibcon#about to read 5, iclass 28, count 0 2006.189.08:21:29.01#ibcon#read 5, iclass 28, count 0 2006.189.08:21:29.01#ibcon#about to read 6, iclass 28, count 0 2006.189.08:21:29.01#ibcon#read 6, iclass 28, count 0 2006.189.08:21:29.01#ibcon#end of sib2, iclass 28, count 0 2006.189.08:21:29.01#ibcon#*after write, iclass 28, count 0 2006.189.08:21:29.01#ibcon#*before return 0, iclass 28, count 0 2006.189.08:21:29.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:29.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:29.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:21:29.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:21:29.01$vc4f8/va=4,7 2006.189.08:21:29.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.08:21:29.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.08:21:29.01#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:29.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:29.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:29.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:29.07#ibcon#enter wrdev, iclass 30, count 2 2006.189.08:21:29.07#ibcon#first serial, iclass 30, count 2 2006.189.08:21:29.07#ibcon#enter sib2, iclass 30, count 2 2006.189.08:21:29.07#ibcon#flushed, iclass 30, count 2 2006.189.08:21:29.07#ibcon#about to write, iclass 30, count 2 2006.189.08:21:29.07#ibcon#wrote, iclass 30, count 2 2006.189.08:21:29.07#ibcon#about to read 3, iclass 30, count 2 2006.189.08:21:29.09#ibcon#read 3, iclass 30, count 2 2006.189.08:21:29.09#ibcon#about to read 4, iclass 30, count 2 2006.189.08:21:29.09#ibcon#read 4, iclass 30, count 2 2006.189.08:21:29.09#ibcon#about to read 5, iclass 30, count 2 2006.189.08:21:29.09#ibcon#read 5, iclass 30, count 2 2006.189.08:21:29.09#ibcon#about to read 6, iclass 30, count 2 2006.189.08:21:29.09#ibcon#read 6, iclass 30, count 2 2006.189.08:21:29.09#ibcon#end of sib2, iclass 30, count 2 2006.189.08:21:29.09#ibcon#*mode == 0, iclass 30, count 2 2006.189.08:21:29.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.08:21:29.09#ibcon#[25=AT04-07\r\n] 2006.189.08:21:29.09#ibcon#*before write, iclass 30, count 2 2006.189.08:21:29.09#ibcon#enter sib2, iclass 30, count 2 2006.189.08:21:29.09#ibcon#flushed, iclass 30, count 2 2006.189.08:21:29.09#ibcon#about to write, iclass 30, count 2 2006.189.08:21:29.09#ibcon#wrote, iclass 30, count 2 2006.189.08:21:29.09#ibcon#about to read 3, iclass 30, count 2 2006.189.08:21:29.12#ibcon#read 3, iclass 30, count 2 2006.189.08:21:29.12#ibcon#about to read 4, iclass 30, count 2 2006.189.08:21:29.12#ibcon#read 4, iclass 30, count 2 2006.189.08:21:29.12#ibcon#about to read 5, iclass 30, count 2 2006.189.08:21:29.12#ibcon#read 5, iclass 30, count 2 2006.189.08:21:29.12#ibcon#about to read 6, iclass 30, count 2 2006.189.08:21:29.12#ibcon#read 6, iclass 30, count 2 2006.189.08:21:29.12#ibcon#end of sib2, iclass 30, count 2 2006.189.08:21:29.12#ibcon#*after write, iclass 30, count 2 2006.189.08:21:29.12#ibcon#*before return 0, iclass 30, count 2 2006.189.08:21:29.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:29.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:29.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.08:21:29.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:29.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:29.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:29.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:29.24#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:21:29.24#ibcon#first serial, iclass 30, count 0 2006.189.08:21:29.24#ibcon#enter sib2, iclass 30, count 0 2006.189.08:21:29.24#ibcon#flushed, iclass 30, count 0 2006.189.08:21:29.24#ibcon#about to write, iclass 30, count 0 2006.189.08:21:29.24#ibcon#wrote, iclass 30, count 0 2006.189.08:21:29.24#ibcon#about to read 3, iclass 30, count 0 2006.189.08:21:29.26#ibcon#read 3, iclass 30, count 0 2006.189.08:21:29.26#ibcon#about to read 4, iclass 30, count 0 2006.189.08:21:29.26#ibcon#read 4, iclass 30, count 0 2006.189.08:21:29.26#ibcon#about to read 5, iclass 30, count 0 2006.189.08:21:29.26#ibcon#read 5, iclass 30, count 0 2006.189.08:21:29.26#ibcon#about to read 6, iclass 30, count 0 2006.189.08:21:29.26#ibcon#read 6, iclass 30, count 0 2006.189.08:21:29.26#ibcon#end of sib2, iclass 30, count 0 2006.189.08:21:29.26#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:21:29.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:21:29.26#ibcon#[25=USB\r\n] 2006.189.08:21:29.26#ibcon#*before write, iclass 30, count 0 2006.189.08:21:29.26#ibcon#enter sib2, iclass 30, count 0 2006.189.08:21:29.26#ibcon#flushed, iclass 30, count 0 2006.189.08:21:29.26#ibcon#about to write, iclass 30, count 0 2006.189.08:21:29.26#ibcon#wrote, iclass 30, count 0 2006.189.08:21:29.26#ibcon#about to read 3, iclass 30, count 0 2006.189.08:21:29.29#ibcon#read 3, iclass 30, count 0 2006.189.08:21:29.29#ibcon#about to read 4, iclass 30, count 0 2006.189.08:21:29.29#ibcon#read 4, iclass 30, count 0 2006.189.08:21:29.29#ibcon#about to read 5, iclass 30, count 0 2006.189.08:21:29.29#ibcon#read 5, iclass 30, count 0 2006.189.08:21:29.29#ibcon#about to read 6, iclass 30, count 0 2006.189.08:21:29.29#ibcon#read 6, iclass 30, count 0 2006.189.08:21:29.29#ibcon#end of sib2, iclass 30, count 0 2006.189.08:21:29.29#ibcon#*after write, iclass 30, count 0 2006.189.08:21:29.29#ibcon#*before return 0, iclass 30, count 0 2006.189.08:21:29.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:29.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:29.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:21:29.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:21:29.29$vc4f8/valo=5,652.99 2006.189.08:21:29.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.08:21:29.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.08:21:29.29#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:29.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:29.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:29.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:29.29#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:21:29.29#ibcon#first serial, iclass 32, count 0 2006.189.08:21:29.29#ibcon#enter sib2, iclass 32, count 0 2006.189.08:21:29.29#ibcon#flushed, iclass 32, count 0 2006.189.08:21:29.29#ibcon#about to write, iclass 32, count 0 2006.189.08:21:29.29#ibcon#wrote, iclass 32, count 0 2006.189.08:21:29.29#ibcon#about to read 3, iclass 32, count 0 2006.189.08:21:29.31#ibcon#read 3, iclass 32, count 0 2006.189.08:21:29.31#ibcon#about to read 4, iclass 32, count 0 2006.189.08:21:29.31#ibcon#read 4, iclass 32, count 0 2006.189.08:21:29.31#ibcon#about to read 5, iclass 32, count 0 2006.189.08:21:29.31#ibcon#read 5, iclass 32, count 0 2006.189.08:21:29.31#ibcon#about to read 6, iclass 32, count 0 2006.189.08:21:29.31#ibcon#read 6, iclass 32, count 0 2006.189.08:21:29.31#ibcon#end of sib2, iclass 32, count 0 2006.189.08:21:29.31#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:21:29.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:21:29.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:21:29.31#ibcon#*before write, iclass 32, count 0 2006.189.08:21:29.31#ibcon#enter sib2, iclass 32, count 0 2006.189.08:21:29.31#ibcon#flushed, iclass 32, count 0 2006.189.08:21:29.31#ibcon#about to write, iclass 32, count 0 2006.189.08:21:29.31#ibcon#wrote, iclass 32, count 0 2006.189.08:21:29.31#ibcon#about to read 3, iclass 32, count 0 2006.189.08:21:29.35#ibcon#read 3, iclass 32, count 0 2006.189.08:21:29.35#ibcon#about to read 4, iclass 32, count 0 2006.189.08:21:29.35#ibcon#read 4, iclass 32, count 0 2006.189.08:21:29.35#ibcon#about to read 5, iclass 32, count 0 2006.189.08:21:29.35#ibcon#read 5, iclass 32, count 0 2006.189.08:21:29.35#ibcon#about to read 6, iclass 32, count 0 2006.189.08:21:29.35#ibcon#read 6, iclass 32, count 0 2006.189.08:21:29.35#ibcon#end of sib2, iclass 32, count 0 2006.189.08:21:29.35#ibcon#*after write, iclass 32, count 0 2006.189.08:21:29.35#ibcon#*before return 0, iclass 32, count 0 2006.189.08:21:29.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:29.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:29.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:21:29.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:21:29.35$vc4f8/va=5,7 2006.189.08:21:29.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.08:21:29.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.08:21:29.35#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:29.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:29.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:29.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:29.41#ibcon#enter wrdev, iclass 34, count 2 2006.189.08:21:29.41#ibcon#first serial, iclass 34, count 2 2006.189.08:21:29.41#ibcon#enter sib2, iclass 34, count 2 2006.189.08:21:29.41#ibcon#flushed, iclass 34, count 2 2006.189.08:21:29.41#ibcon#about to write, iclass 34, count 2 2006.189.08:21:29.41#ibcon#wrote, iclass 34, count 2 2006.189.08:21:29.41#ibcon#about to read 3, iclass 34, count 2 2006.189.08:21:29.43#ibcon#read 3, iclass 34, count 2 2006.189.08:21:29.43#ibcon#about to read 4, iclass 34, count 2 2006.189.08:21:29.43#ibcon#read 4, iclass 34, count 2 2006.189.08:21:29.43#ibcon#about to read 5, iclass 34, count 2 2006.189.08:21:29.43#ibcon#read 5, iclass 34, count 2 2006.189.08:21:29.43#ibcon#about to read 6, iclass 34, count 2 2006.189.08:21:29.43#ibcon#read 6, iclass 34, count 2 2006.189.08:21:29.43#ibcon#end of sib2, iclass 34, count 2 2006.189.08:21:29.43#ibcon#*mode == 0, iclass 34, count 2 2006.189.08:21:29.43#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.08:21:29.43#ibcon#[25=AT05-07\r\n] 2006.189.08:21:29.43#ibcon#*before write, iclass 34, count 2 2006.189.08:21:29.43#ibcon#enter sib2, iclass 34, count 2 2006.189.08:21:29.43#ibcon#flushed, iclass 34, count 2 2006.189.08:21:29.43#ibcon#about to write, iclass 34, count 2 2006.189.08:21:29.43#ibcon#wrote, iclass 34, count 2 2006.189.08:21:29.43#ibcon#about to read 3, iclass 34, count 2 2006.189.08:21:29.46#ibcon#read 3, iclass 34, count 2 2006.189.08:21:29.46#ibcon#about to read 4, iclass 34, count 2 2006.189.08:21:29.46#ibcon#read 4, iclass 34, count 2 2006.189.08:21:29.46#ibcon#about to read 5, iclass 34, count 2 2006.189.08:21:29.46#ibcon#read 5, iclass 34, count 2 2006.189.08:21:29.46#ibcon#about to read 6, iclass 34, count 2 2006.189.08:21:29.46#ibcon#read 6, iclass 34, count 2 2006.189.08:21:29.46#ibcon#end of sib2, iclass 34, count 2 2006.189.08:21:29.46#ibcon#*after write, iclass 34, count 2 2006.189.08:21:29.46#ibcon#*before return 0, iclass 34, count 2 2006.189.08:21:29.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:29.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:29.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.08:21:29.46#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:29.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:29.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:29.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:29.58#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:21:29.58#ibcon#first serial, iclass 34, count 0 2006.189.08:21:29.58#ibcon#enter sib2, iclass 34, count 0 2006.189.08:21:29.58#ibcon#flushed, iclass 34, count 0 2006.189.08:21:29.58#ibcon#about to write, iclass 34, count 0 2006.189.08:21:29.58#ibcon#wrote, iclass 34, count 0 2006.189.08:21:29.58#ibcon#about to read 3, iclass 34, count 0 2006.189.08:21:29.60#ibcon#read 3, iclass 34, count 0 2006.189.08:21:29.60#ibcon#about to read 4, iclass 34, count 0 2006.189.08:21:29.60#ibcon#read 4, iclass 34, count 0 2006.189.08:21:29.60#ibcon#about to read 5, iclass 34, count 0 2006.189.08:21:29.60#ibcon#read 5, iclass 34, count 0 2006.189.08:21:29.60#ibcon#about to read 6, iclass 34, count 0 2006.189.08:21:29.60#ibcon#read 6, iclass 34, count 0 2006.189.08:21:29.60#ibcon#end of sib2, iclass 34, count 0 2006.189.08:21:29.60#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:21:29.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:21:29.60#ibcon#[25=USB\r\n] 2006.189.08:21:29.60#ibcon#*before write, iclass 34, count 0 2006.189.08:21:29.60#ibcon#enter sib2, iclass 34, count 0 2006.189.08:21:29.60#ibcon#flushed, iclass 34, count 0 2006.189.08:21:29.60#ibcon#about to write, iclass 34, count 0 2006.189.08:21:29.60#ibcon#wrote, iclass 34, count 0 2006.189.08:21:29.60#ibcon#about to read 3, iclass 34, count 0 2006.189.08:21:29.63#ibcon#read 3, iclass 34, count 0 2006.189.08:21:29.63#ibcon#about to read 4, iclass 34, count 0 2006.189.08:21:29.63#ibcon#read 4, iclass 34, count 0 2006.189.08:21:29.63#ibcon#about to read 5, iclass 34, count 0 2006.189.08:21:29.63#ibcon#read 5, iclass 34, count 0 2006.189.08:21:29.63#ibcon#about to read 6, iclass 34, count 0 2006.189.08:21:29.63#ibcon#read 6, iclass 34, count 0 2006.189.08:21:29.63#ibcon#end of sib2, iclass 34, count 0 2006.189.08:21:29.63#ibcon#*after write, iclass 34, count 0 2006.189.08:21:29.63#ibcon#*before return 0, iclass 34, count 0 2006.189.08:21:29.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:29.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:29.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:21:29.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:21:29.63$vc4f8/valo=6,772.99 2006.189.08:21:29.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.08:21:29.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.08:21:29.63#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:29.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:29.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:29.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:29.63#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:21:29.63#ibcon#first serial, iclass 36, count 0 2006.189.08:21:29.63#ibcon#enter sib2, iclass 36, count 0 2006.189.08:21:29.63#ibcon#flushed, iclass 36, count 0 2006.189.08:21:29.63#ibcon#about to write, iclass 36, count 0 2006.189.08:21:29.63#ibcon#wrote, iclass 36, count 0 2006.189.08:21:29.63#ibcon#about to read 3, iclass 36, count 0 2006.189.08:21:29.65#ibcon#read 3, iclass 36, count 0 2006.189.08:21:29.65#ibcon#about to read 4, iclass 36, count 0 2006.189.08:21:29.65#ibcon#read 4, iclass 36, count 0 2006.189.08:21:29.65#ibcon#about to read 5, iclass 36, count 0 2006.189.08:21:29.65#ibcon#read 5, iclass 36, count 0 2006.189.08:21:29.65#ibcon#about to read 6, iclass 36, count 0 2006.189.08:21:29.65#ibcon#read 6, iclass 36, count 0 2006.189.08:21:29.65#ibcon#end of sib2, iclass 36, count 0 2006.189.08:21:29.65#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:21:29.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:21:29.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:21:29.65#ibcon#*before write, iclass 36, count 0 2006.189.08:21:29.65#ibcon#enter sib2, iclass 36, count 0 2006.189.08:21:29.65#ibcon#flushed, iclass 36, count 0 2006.189.08:21:29.65#ibcon#about to write, iclass 36, count 0 2006.189.08:21:29.65#ibcon#wrote, iclass 36, count 0 2006.189.08:21:29.65#ibcon#about to read 3, iclass 36, count 0 2006.189.08:21:29.69#ibcon#read 3, iclass 36, count 0 2006.189.08:21:29.69#ibcon#about to read 4, iclass 36, count 0 2006.189.08:21:29.69#ibcon#read 4, iclass 36, count 0 2006.189.08:21:29.69#ibcon#about to read 5, iclass 36, count 0 2006.189.08:21:29.69#ibcon#read 5, iclass 36, count 0 2006.189.08:21:29.69#ibcon#about to read 6, iclass 36, count 0 2006.189.08:21:29.69#ibcon#read 6, iclass 36, count 0 2006.189.08:21:29.69#ibcon#end of sib2, iclass 36, count 0 2006.189.08:21:29.69#ibcon#*after write, iclass 36, count 0 2006.189.08:21:29.69#ibcon#*before return 0, iclass 36, count 0 2006.189.08:21:29.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:29.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:29.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:21:29.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:21:29.69$vc4f8/va=6,6 2006.189.08:21:29.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.08:21:29.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.08:21:29.69#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:29.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:29.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:29.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:29.75#ibcon#enter wrdev, iclass 38, count 2 2006.189.08:21:29.75#ibcon#first serial, iclass 38, count 2 2006.189.08:21:29.75#ibcon#enter sib2, iclass 38, count 2 2006.189.08:21:29.75#ibcon#flushed, iclass 38, count 2 2006.189.08:21:29.75#ibcon#about to write, iclass 38, count 2 2006.189.08:21:29.75#ibcon#wrote, iclass 38, count 2 2006.189.08:21:29.75#ibcon#about to read 3, iclass 38, count 2 2006.189.08:21:29.77#ibcon#read 3, iclass 38, count 2 2006.189.08:21:29.77#ibcon#about to read 4, iclass 38, count 2 2006.189.08:21:29.77#ibcon#read 4, iclass 38, count 2 2006.189.08:21:29.77#ibcon#about to read 5, iclass 38, count 2 2006.189.08:21:29.77#ibcon#read 5, iclass 38, count 2 2006.189.08:21:29.77#ibcon#about to read 6, iclass 38, count 2 2006.189.08:21:29.77#ibcon#read 6, iclass 38, count 2 2006.189.08:21:29.77#ibcon#end of sib2, iclass 38, count 2 2006.189.08:21:29.77#ibcon#*mode == 0, iclass 38, count 2 2006.189.08:21:29.77#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.08:21:29.77#ibcon#[25=AT06-06\r\n] 2006.189.08:21:29.77#ibcon#*before write, iclass 38, count 2 2006.189.08:21:29.77#ibcon#enter sib2, iclass 38, count 2 2006.189.08:21:29.77#ibcon#flushed, iclass 38, count 2 2006.189.08:21:29.77#ibcon#about to write, iclass 38, count 2 2006.189.08:21:29.77#ibcon#wrote, iclass 38, count 2 2006.189.08:21:29.77#ibcon#about to read 3, iclass 38, count 2 2006.189.08:21:29.80#ibcon#read 3, iclass 38, count 2 2006.189.08:21:29.80#ibcon#about to read 4, iclass 38, count 2 2006.189.08:21:29.80#ibcon#read 4, iclass 38, count 2 2006.189.08:21:29.80#ibcon#about to read 5, iclass 38, count 2 2006.189.08:21:29.80#ibcon#read 5, iclass 38, count 2 2006.189.08:21:29.80#ibcon#about to read 6, iclass 38, count 2 2006.189.08:21:29.80#ibcon#read 6, iclass 38, count 2 2006.189.08:21:29.80#ibcon#end of sib2, iclass 38, count 2 2006.189.08:21:29.80#ibcon#*after write, iclass 38, count 2 2006.189.08:21:29.80#ibcon#*before return 0, iclass 38, count 2 2006.189.08:21:29.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:29.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:29.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.08:21:29.80#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:29.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:29.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:29.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:29.92#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:21:29.92#ibcon#first serial, iclass 38, count 0 2006.189.08:21:29.92#ibcon#enter sib2, iclass 38, count 0 2006.189.08:21:29.92#ibcon#flushed, iclass 38, count 0 2006.189.08:21:29.92#ibcon#about to write, iclass 38, count 0 2006.189.08:21:29.92#ibcon#wrote, iclass 38, count 0 2006.189.08:21:29.92#ibcon#about to read 3, iclass 38, count 0 2006.189.08:21:29.94#ibcon#read 3, iclass 38, count 0 2006.189.08:21:29.94#ibcon#about to read 4, iclass 38, count 0 2006.189.08:21:29.94#ibcon#read 4, iclass 38, count 0 2006.189.08:21:29.94#ibcon#about to read 5, iclass 38, count 0 2006.189.08:21:29.94#ibcon#read 5, iclass 38, count 0 2006.189.08:21:29.94#ibcon#about to read 6, iclass 38, count 0 2006.189.08:21:29.94#ibcon#read 6, iclass 38, count 0 2006.189.08:21:29.94#ibcon#end of sib2, iclass 38, count 0 2006.189.08:21:29.94#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:21:29.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:21:29.94#ibcon#[25=USB\r\n] 2006.189.08:21:29.94#ibcon#*before write, iclass 38, count 0 2006.189.08:21:29.94#ibcon#enter sib2, iclass 38, count 0 2006.189.08:21:29.94#ibcon#flushed, iclass 38, count 0 2006.189.08:21:29.94#ibcon#about to write, iclass 38, count 0 2006.189.08:21:29.94#ibcon#wrote, iclass 38, count 0 2006.189.08:21:29.94#ibcon#about to read 3, iclass 38, count 0 2006.189.08:21:29.97#ibcon#read 3, iclass 38, count 0 2006.189.08:21:29.97#ibcon#about to read 4, iclass 38, count 0 2006.189.08:21:29.97#ibcon#read 4, iclass 38, count 0 2006.189.08:21:29.97#ibcon#about to read 5, iclass 38, count 0 2006.189.08:21:29.97#ibcon#read 5, iclass 38, count 0 2006.189.08:21:29.97#ibcon#about to read 6, iclass 38, count 0 2006.189.08:21:29.97#ibcon#read 6, iclass 38, count 0 2006.189.08:21:29.97#ibcon#end of sib2, iclass 38, count 0 2006.189.08:21:29.97#ibcon#*after write, iclass 38, count 0 2006.189.08:21:29.97#ibcon#*before return 0, iclass 38, count 0 2006.189.08:21:29.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:29.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:29.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:21:29.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:21:29.97$vc4f8/valo=7,832.99 2006.189.08:21:29.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.08:21:29.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.08:21:29.97#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:29.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:29.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:29.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:29.97#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:21:29.97#ibcon#first serial, iclass 40, count 0 2006.189.08:21:29.97#ibcon#enter sib2, iclass 40, count 0 2006.189.08:21:29.97#ibcon#flushed, iclass 40, count 0 2006.189.08:21:29.97#ibcon#about to write, iclass 40, count 0 2006.189.08:21:29.97#ibcon#wrote, iclass 40, count 0 2006.189.08:21:29.97#ibcon#about to read 3, iclass 40, count 0 2006.189.08:21:29.99#ibcon#read 3, iclass 40, count 0 2006.189.08:21:29.99#ibcon#about to read 4, iclass 40, count 0 2006.189.08:21:29.99#ibcon#read 4, iclass 40, count 0 2006.189.08:21:29.99#ibcon#about to read 5, iclass 40, count 0 2006.189.08:21:29.99#ibcon#read 5, iclass 40, count 0 2006.189.08:21:29.99#ibcon#about to read 6, iclass 40, count 0 2006.189.08:21:29.99#ibcon#read 6, iclass 40, count 0 2006.189.08:21:29.99#ibcon#end of sib2, iclass 40, count 0 2006.189.08:21:29.99#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:21:29.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:21:29.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:21:29.99#ibcon#*before write, iclass 40, count 0 2006.189.08:21:29.99#ibcon#enter sib2, iclass 40, count 0 2006.189.08:21:29.99#ibcon#flushed, iclass 40, count 0 2006.189.08:21:29.99#ibcon#about to write, iclass 40, count 0 2006.189.08:21:29.99#ibcon#wrote, iclass 40, count 0 2006.189.08:21:29.99#ibcon#about to read 3, iclass 40, count 0 2006.189.08:21:30.03#ibcon#read 3, iclass 40, count 0 2006.189.08:21:30.03#ibcon#about to read 4, iclass 40, count 0 2006.189.08:21:30.03#ibcon#read 4, iclass 40, count 0 2006.189.08:21:30.03#ibcon#about to read 5, iclass 40, count 0 2006.189.08:21:30.03#ibcon#read 5, iclass 40, count 0 2006.189.08:21:30.03#ibcon#about to read 6, iclass 40, count 0 2006.189.08:21:30.03#ibcon#read 6, iclass 40, count 0 2006.189.08:21:30.03#ibcon#end of sib2, iclass 40, count 0 2006.189.08:21:30.03#ibcon#*after write, iclass 40, count 0 2006.189.08:21:30.03#ibcon#*before return 0, iclass 40, count 0 2006.189.08:21:30.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:30.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:30.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:21:30.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:21:30.03$vc4f8/va=7,6 2006.189.08:21:30.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.189.08:21:30.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.189.08:21:30.03#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:30.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:21:30.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:21:30.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:21:30.09#ibcon#enter wrdev, iclass 4, count 2 2006.189.08:21:30.09#ibcon#first serial, iclass 4, count 2 2006.189.08:21:30.09#ibcon#enter sib2, iclass 4, count 2 2006.189.08:21:30.09#ibcon#flushed, iclass 4, count 2 2006.189.08:21:30.09#ibcon#about to write, iclass 4, count 2 2006.189.08:21:30.09#ibcon#wrote, iclass 4, count 2 2006.189.08:21:30.09#ibcon#about to read 3, iclass 4, count 2 2006.189.08:21:30.11#ibcon#read 3, iclass 4, count 2 2006.189.08:21:30.11#ibcon#about to read 4, iclass 4, count 2 2006.189.08:21:30.11#ibcon#read 4, iclass 4, count 2 2006.189.08:21:30.11#ibcon#about to read 5, iclass 4, count 2 2006.189.08:21:30.11#ibcon#read 5, iclass 4, count 2 2006.189.08:21:30.11#ibcon#about to read 6, iclass 4, count 2 2006.189.08:21:30.11#ibcon#read 6, iclass 4, count 2 2006.189.08:21:30.11#ibcon#end of sib2, iclass 4, count 2 2006.189.08:21:30.11#ibcon#*mode == 0, iclass 4, count 2 2006.189.08:21:30.11#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.189.08:21:30.11#ibcon#[25=AT07-06\r\n] 2006.189.08:21:30.11#ibcon#*before write, iclass 4, count 2 2006.189.08:21:30.11#ibcon#enter sib2, iclass 4, count 2 2006.189.08:21:30.11#ibcon#flushed, iclass 4, count 2 2006.189.08:21:30.11#ibcon#about to write, iclass 4, count 2 2006.189.08:21:30.11#ibcon#wrote, iclass 4, count 2 2006.189.08:21:30.11#ibcon#about to read 3, iclass 4, count 2 2006.189.08:21:30.14#ibcon#read 3, iclass 4, count 2 2006.189.08:21:30.14#ibcon#about to read 4, iclass 4, count 2 2006.189.08:21:30.14#ibcon#read 4, iclass 4, count 2 2006.189.08:21:30.14#ibcon#about to read 5, iclass 4, count 2 2006.189.08:21:30.14#ibcon#read 5, iclass 4, count 2 2006.189.08:21:30.14#ibcon#about to read 6, iclass 4, count 2 2006.189.08:21:30.14#ibcon#read 6, iclass 4, count 2 2006.189.08:21:30.14#ibcon#end of sib2, iclass 4, count 2 2006.189.08:21:30.14#ibcon#*after write, iclass 4, count 2 2006.189.08:21:30.14#ibcon#*before return 0, iclass 4, count 2 2006.189.08:21:30.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:21:30.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.189.08:21:30.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.189.08:21:30.14#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:30.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:21:30.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:21:30.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:21:30.26#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:21:30.26#ibcon#first serial, iclass 4, count 0 2006.189.08:21:30.26#ibcon#enter sib2, iclass 4, count 0 2006.189.08:21:30.26#ibcon#flushed, iclass 4, count 0 2006.189.08:21:30.26#ibcon#about to write, iclass 4, count 0 2006.189.08:21:30.26#ibcon#wrote, iclass 4, count 0 2006.189.08:21:30.26#ibcon#about to read 3, iclass 4, count 0 2006.189.08:21:30.28#ibcon#read 3, iclass 4, count 0 2006.189.08:21:30.28#ibcon#about to read 4, iclass 4, count 0 2006.189.08:21:30.28#ibcon#read 4, iclass 4, count 0 2006.189.08:21:30.28#ibcon#about to read 5, iclass 4, count 0 2006.189.08:21:30.28#ibcon#read 5, iclass 4, count 0 2006.189.08:21:30.28#ibcon#about to read 6, iclass 4, count 0 2006.189.08:21:30.28#ibcon#read 6, iclass 4, count 0 2006.189.08:21:30.28#ibcon#end of sib2, iclass 4, count 0 2006.189.08:21:30.28#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:21:30.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:21:30.28#ibcon#[25=USB\r\n] 2006.189.08:21:30.28#ibcon#*before write, iclass 4, count 0 2006.189.08:21:30.28#ibcon#enter sib2, iclass 4, count 0 2006.189.08:21:30.28#ibcon#flushed, iclass 4, count 0 2006.189.08:21:30.28#ibcon#about to write, iclass 4, count 0 2006.189.08:21:30.28#ibcon#wrote, iclass 4, count 0 2006.189.08:21:30.28#ibcon#about to read 3, iclass 4, count 0 2006.189.08:21:30.31#ibcon#read 3, iclass 4, count 0 2006.189.08:21:30.31#ibcon#about to read 4, iclass 4, count 0 2006.189.08:21:30.31#ibcon#read 4, iclass 4, count 0 2006.189.08:21:30.31#ibcon#about to read 5, iclass 4, count 0 2006.189.08:21:30.31#ibcon#read 5, iclass 4, count 0 2006.189.08:21:30.31#ibcon#about to read 6, iclass 4, count 0 2006.189.08:21:30.31#ibcon#read 6, iclass 4, count 0 2006.189.08:21:30.31#ibcon#end of sib2, iclass 4, count 0 2006.189.08:21:30.31#ibcon#*after write, iclass 4, count 0 2006.189.08:21:30.31#ibcon#*before return 0, iclass 4, count 0 2006.189.08:21:30.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:21:30.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.189.08:21:30.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:21:30.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:21:30.31$vc4f8/valo=8,852.99 2006.189.08:21:30.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.189.08:21:30.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.189.08:21:30.31#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:30.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:21:30.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:21:30.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:21:30.31#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:21:30.31#ibcon#first serial, iclass 6, count 0 2006.189.08:21:30.31#ibcon#enter sib2, iclass 6, count 0 2006.189.08:21:30.31#ibcon#flushed, iclass 6, count 0 2006.189.08:21:30.31#ibcon#about to write, iclass 6, count 0 2006.189.08:21:30.31#ibcon#wrote, iclass 6, count 0 2006.189.08:21:30.31#ibcon#about to read 3, iclass 6, count 0 2006.189.08:21:30.33#ibcon#read 3, iclass 6, count 0 2006.189.08:21:30.33#ibcon#about to read 4, iclass 6, count 0 2006.189.08:21:30.33#ibcon#read 4, iclass 6, count 0 2006.189.08:21:30.33#ibcon#about to read 5, iclass 6, count 0 2006.189.08:21:30.33#ibcon#read 5, iclass 6, count 0 2006.189.08:21:30.33#ibcon#about to read 6, iclass 6, count 0 2006.189.08:21:30.33#ibcon#read 6, iclass 6, count 0 2006.189.08:21:30.33#ibcon#end of sib2, iclass 6, count 0 2006.189.08:21:30.33#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:21:30.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:21:30.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:21:30.33#ibcon#*before write, iclass 6, count 0 2006.189.08:21:30.33#ibcon#enter sib2, iclass 6, count 0 2006.189.08:21:30.33#ibcon#flushed, iclass 6, count 0 2006.189.08:21:30.33#ibcon#about to write, iclass 6, count 0 2006.189.08:21:30.33#ibcon#wrote, iclass 6, count 0 2006.189.08:21:30.33#ibcon#about to read 3, iclass 6, count 0 2006.189.08:21:30.37#ibcon#read 3, iclass 6, count 0 2006.189.08:21:30.37#ibcon#about to read 4, iclass 6, count 0 2006.189.08:21:30.37#ibcon#read 4, iclass 6, count 0 2006.189.08:21:30.37#ibcon#about to read 5, iclass 6, count 0 2006.189.08:21:30.37#ibcon#read 5, iclass 6, count 0 2006.189.08:21:30.37#ibcon#about to read 6, iclass 6, count 0 2006.189.08:21:30.37#ibcon#read 6, iclass 6, count 0 2006.189.08:21:30.37#ibcon#end of sib2, iclass 6, count 0 2006.189.08:21:30.37#ibcon#*after write, iclass 6, count 0 2006.189.08:21:30.37#ibcon#*before return 0, iclass 6, count 0 2006.189.08:21:30.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:21:30.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.189.08:21:30.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:21:30.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:21:30.37$vc4f8/va=8,6 2006.189.08:21:30.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.189.08:21:30.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.189.08:21:30.37#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:30.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:21:30.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:21:30.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:21:30.43#ibcon#enter wrdev, iclass 10, count 2 2006.189.08:21:30.43#ibcon#first serial, iclass 10, count 2 2006.189.08:21:30.43#ibcon#enter sib2, iclass 10, count 2 2006.189.08:21:30.43#ibcon#flushed, iclass 10, count 2 2006.189.08:21:30.43#ibcon#about to write, iclass 10, count 2 2006.189.08:21:30.43#ibcon#wrote, iclass 10, count 2 2006.189.08:21:30.43#ibcon#about to read 3, iclass 10, count 2 2006.189.08:21:30.45#ibcon#read 3, iclass 10, count 2 2006.189.08:21:30.45#ibcon#about to read 4, iclass 10, count 2 2006.189.08:21:30.45#ibcon#read 4, iclass 10, count 2 2006.189.08:21:30.45#ibcon#about to read 5, iclass 10, count 2 2006.189.08:21:30.45#ibcon#read 5, iclass 10, count 2 2006.189.08:21:30.45#ibcon#about to read 6, iclass 10, count 2 2006.189.08:21:30.45#ibcon#read 6, iclass 10, count 2 2006.189.08:21:30.45#ibcon#end of sib2, iclass 10, count 2 2006.189.08:21:30.45#ibcon#*mode == 0, iclass 10, count 2 2006.189.08:21:30.45#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.189.08:21:30.45#ibcon#[25=AT08-06\r\n] 2006.189.08:21:30.45#ibcon#*before write, iclass 10, count 2 2006.189.08:21:30.45#ibcon#enter sib2, iclass 10, count 2 2006.189.08:21:30.45#ibcon#flushed, iclass 10, count 2 2006.189.08:21:30.45#ibcon#about to write, iclass 10, count 2 2006.189.08:21:30.45#ibcon#wrote, iclass 10, count 2 2006.189.08:21:30.45#ibcon#about to read 3, iclass 10, count 2 2006.189.08:21:30.48#ibcon#read 3, iclass 10, count 2 2006.189.08:21:30.48#ibcon#about to read 4, iclass 10, count 2 2006.189.08:21:30.48#ibcon#read 4, iclass 10, count 2 2006.189.08:21:30.48#ibcon#about to read 5, iclass 10, count 2 2006.189.08:21:30.48#ibcon#read 5, iclass 10, count 2 2006.189.08:21:30.48#ibcon#about to read 6, iclass 10, count 2 2006.189.08:21:30.48#ibcon#read 6, iclass 10, count 2 2006.189.08:21:30.48#ibcon#end of sib2, iclass 10, count 2 2006.189.08:21:30.48#ibcon#*after write, iclass 10, count 2 2006.189.08:21:30.48#ibcon#*before return 0, iclass 10, count 2 2006.189.08:21:30.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:21:30.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.189.08:21:30.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.189.08:21:30.48#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:30.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:21:30.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:21:30.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:21:30.60#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:21:30.60#ibcon#first serial, iclass 10, count 0 2006.189.08:21:30.60#ibcon#enter sib2, iclass 10, count 0 2006.189.08:21:30.60#ibcon#flushed, iclass 10, count 0 2006.189.08:21:30.60#ibcon#about to write, iclass 10, count 0 2006.189.08:21:30.60#ibcon#wrote, iclass 10, count 0 2006.189.08:21:30.60#ibcon#about to read 3, iclass 10, count 0 2006.189.08:21:30.62#ibcon#read 3, iclass 10, count 0 2006.189.08:21:30.62#ibcon#about to read 4, iclass 10, count 0 2006.189.08:21:30.62#ibcon#read 4, iclass 10, count 0 2006.189.08:21:30.62#ibcon#about to read 5, iclass 10, count 0 2006.189.08:21:30.62#ibcon#read 5, iclass 10, count 0 2006.189.08:21:30.62#ibcon#about to read 6, iclass 10, count 0 2006.189.08:21:30.62#ibcon#read 6, iclass 10, count 0 2006.189.08:21:30.62#ibcon#end of sib2, iclass 10, count 0 2006.189.08:21:30.62#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:21:30.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:21:30.62#ibcon#[25=USB\r\n] 2006.189.08:21:30.62#ibcon#*before write, iclass 10, count 0 2006.189.08:21:30.62#ibcon#enter sib2, iclass 10, count 0 2006.189.08:21:30.62#ibcon#flushed, iclass 10, count 0 2006.189.08:21:30.62#ibcon#about to write, iclass 10, count 0 2006.189.08:21:30.62#ibcon#wrote, iclass 10, count 0 2006.189.08:21:30.62#ibcon#about to read 3, iclass 10, count 0 2006.189.08:21:30.65#ibcon#read 3, iclass 10, count 0 2006.189.08:21:30.65#ibcon#about to read 4, iclass 10, count 0 2006.189.08:21:30.65#ibcon#read 4, iclass 10, count 0 2006.189.08:21:30.65#ibcon#about to read 5, iclass 10, count 0 2006.189.08:21:30.65#ibcon#read 5, iclass 10, count 0 2006.189.08:21:30.65#ibcon#about to read 6, iclass 10, count 0 2006.189.08:21:30.65#ibcon#read 6, iclass 10, count 0 2006.189.08:21:30.65#ibcon#end of sib2, iclass 10, count 0 2006.189.08:21:30.65#ibcon#*after write, iclass 10, count 0 2006.189.08:21:30.65#ibcon#*before return 0, iclass 10, count 0 2006.189.08:21:30.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:21:30.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.189.08:21:30.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:21:30.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:21:30.65$vc4f8/vblo=1,632.99 2006.189.08:21:30.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.189.08:21:30.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.189.08:21:30.65#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:30.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:21:30.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:21:30.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:21:30.65#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:21:30.65#ibcon#first serial, iclass 12, count 0 2006.189.08:21:30.65#ibcon#enter sib2, iclass 12, count 0 2006.189.08:21:30.65#ibcon#flushed, iclass 12, count 0 2006.189.08:21:30.65#ibcon#about to write, iclass 12, count 0 2006.189.08:21:30.65#ibcon#wrote, iclass 12, count 0 2006.189.08:21:30.65#ibcon#about to read 3, iclass 12, count 0 2006.189.08:21:30.67#ibcon#read 3, iclass 12, count 0 2006.189.08:21:30.67#ibcon#about to read 4, iclass 12, count 0 2006.189.08:21:30.67#ibcon#read 4, iclass 12, count 0 2006.189.08:21:30.67#ibcon#about to read 5, iclass 12, count 0 2006.189.08:21:30.67#ibcon#read 5, iclass 12, count 0 2006.189.08:21:30.67#ibcon#about to read 6, iclass 12, count 0 2006.189.08:21:30.67#ibcon#read 6, iclass 12, count 0 2006.189.08:21:30.67#ibcon#end of sib2, iclass 12, count 0 2006.189.08:21:30.67#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:21:30.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:21:30.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:21:30.67#ibcon#*before write, iclass 12, count 0 2006.189.08:21:30.67#ibcon#enter sib2, iclass 12, count 0 2006.189.08:21:30.67#ibcon#flushed, iclass 12, count 0 2006.189.08:21:30.67#ibcon#about to write, iclass 12, count 0 2006.189.08:21:30.67#ibcon#wrote, iclass 12, count 0 2006.189.08:21:30.67#ibcon#about to read 3, iclass 12, count 0 2006.189.08:21:30.71#ibcon#read 3, iclass 12, count 0 2006.189.08:21:30.71#ibcon#about to read 4, iclass 12, count 0 2006.189.08:21:30.71#ibcon#read 4, iclass 12, count 0 2006.189.08:21:30.71#ibcon#about to read 5, iclass 12, count 0 2006.189.08:21:30.71#ibcon#read 5, iclass 12, count 0 2006.189.08:21:30.71#ibcon#about to read 6, iclass 12, count 0 2006.189.08:21:30.71#ibcon#read 6, iclass 12, count 0 2006.189.08:21:30.71#ibcon#end of sib2, iclass 12, count 0 2006.189.08:21:30.71#ibcon#*after write, iclass 12, count 0 2006.189.08:21:30.71#ibcon#*before return 0, iclass 12, count 0 2006.189.08:21:30.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:21:30.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.189.08:21:30.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:21:30.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:21:30.71$vc4f8/vb=1,4 2006.189.08:21:30.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.189.08:21:30.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.189.08:21:30.71#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:30.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:21:30.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:21:30.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:21:30.71#ibcon#enter wrdev, iclass 14, count 2 2006.189.08:21:30.71#ibcon#first serial, iclass 14, count 2 2006.189.08:21:30.71#ibcon#enter sib2, iclass 14, count 2 2006.189.08:21:30.71#ibcon#flushed, iclass 14, count 2 2006.189.08:21:30.71#ibcon#about to write, iclass 14, count 2 2006.189.08:21:30.71#ibcon#wrote, iclass 14, count 2 2006.189.08:21:30.71#ibcon#about to read 3, iclass 14, count 2 2006.189.08:21:30.73#ibcon#read 3, iclass 14, count 2 2006.189.08:21:30.73#ibcon#about to read 4, iclass 14, count 2 2006.189.08:21:30.73#ibcon#read 4, iclass 14, count 2 2006.189.08:21:30.73#ibcon#about to read 5, iclass 14, count 2 2006.189.08:21:30.73#ibcon#read 5, iclass 14, count 2 2006.189.08:21:30.73#ibcon#about to read 6, iclass 14, count 2 2006.189.08:21:30.73#ibcon#read 6, iclass 14, count 2 2006.189.08:21:30.73#ibcon#end of sib2, iclass 14, count 2 2006.189.08:21:30.73#ibcon#*mode == 0, iclass 14, count 2 2006.189.08:21:30.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.189.08:21:30.73#ibcon#[27=AT01-04\r\n] 2006.189.08:21:30.73#ibcon#*before write, iclass 14, count 2 2006.189.08:21:30.73#ibcon#enter sib2, iclass 14, count 2 2006.189.08:21:30.73#ibcon#flushed, iclass 14, count 2 2006.189.08:21:30.73#ibcon#about to write, iclass 14, count 2 2006.189.08:21:30.73#ibcon#wrote, iclass 14, count 2 2006.189.08:21:30.73#ibcon#about to read 3, iclass 14, count 2 2006.189.08:21:30.76#ibcon#read 3, iclass 14, count 2 2006.189.08:21:30.76#ibcon#about to read 4, iclass 14, count 2 2006.189.08:21:30.76#ibcon#read 4, iclass 14, count 2 2006.189.08:21:30.76#ibcon#about to read 5, iclass 14, count 2 2006.189.08:21:30.76#ibcon#read 5, iclass 14, count 2 2006.189.08:21:30.76#ibcon#about to read 6, iclass 14, count 2 2006.189.08:21:30.76#ibcon#read 6, iclass 14, count 2 2006.189.08:21:30.76#ibcon#end of sib2, iclass 14, count 2 2006.189.08:21:30.76#ibcon#*after write, iclass 14, count 2 2006.189.08:21:30.76#ibcon#*before return 0, iclass 14, count 2 2006.189.08:21:30.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:21:30.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.189.08:21:30.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.189.08:21:30.76#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:30.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:21:30.83#abcon#<5=/04 4.1 8.5 25.33 921009.2\r\n> 2006.189.08:21:30.85#abcon#{5=INTERFACE CLEAR} 2006.189.08:21:30.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:21:30.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:21:30.88#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:21:30.88#ibcon#first serial, iclass 14, count 0 2006.189.08:21:30.88#ibcon#enter sib2, iclass 14, count 0 2006.189.08:21:30.88#ibcon#flushed, iclass 14, count 0 2006.189.08:21:30.88#ibcon#about to write, iclass 14, count 0 2006.189.08:21:30.88#ibcon#wrote, iclass 14, count 0 2006.189.08:21:30.88#ibcon#about to read 3, iclass 14, count 0 2006.189.08:21:30.90#ibcon#read 3, iclass 14, count 0 2006.189.08:21:30.90#ibcon#about to read 4, iclass 14, count 0 2006.189.08:21:30.90#ibcon#read 4, iclass 14, count 0 2006.189.08:21:30.90#ibcon#about to read 5, iclass 14, count 0 2006.189.08:21:30.90#ibcon#read 5, iclass 14, count 0 2006.189.08:21:30.90#ibcon#about to read 6, iclass 14, count 0 2006.189.08:21:30.90#ibcon#read 6, iclass 14, count 0 2006.189.08:21:30.90#ibcon#end of sib2, iclass 14, count 0 2006.189.08:21:30.90#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:21:30.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:21:30.90#ibcon#[27=USB\r\n] 2006.189.08:21:30.90#ibcon#*before write, iclass 14, count 0 2006.189.08:21:30.90#ibcon#enter sib2, iclass 14, count 0 2006.189.08:21:30.90#ibcon#flushed, iclass 14, count 0 2006.189.08:21:30.90#ibcon#about to write, iclass 14, count 0 2006.189.08:21:30.90#ibcon#wrote, iclass 14, count 0 2006.189.08:21:30.90#ibcon#about to read 3, iclass 14, count 0 2006.189.08:21:30.91#abcon#[5=S1D000X0/0*\r\n] 2006.189.08:21:30.93#ibcon#read 3, iclass 14, count 0 2006.189.08:21:30.93#ibcon#about to read 4, iclass 14, count 0 2006.189.08:21:30.93#ibcon#read 4, iclass 14, count 0 2006.189.08:21:30.93#ibcon#about to read 5, iclass 14, count 0 2006.189.08:21:30.93#ibcon#read 5, iclass 14, count 0 2006.189.08:21:30.93#ibcon#about to read 6, iclass 14, count 0 2006.189.08:21:30.93#ibcon#read 6, iclass 14, count 0 2006.189.08:21:30.93#ibcon#end of sib2, iclass 14, count 0 2006.189.08:21:30.93#ibcon#*after write, iclass 14, count 0 2006.189.08:21:30.93#ibcon#*before return 0, iclass 14, count 0 2006.189.08:21:30.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:21:30.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.189.08:21:30.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:21:30.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:21:30.93$vc4f8/vblo=2,640.99 2006.189.08:21:30.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.189.08:21:30.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.189.08:21:30.93#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:30.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:30.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:30.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:30.93#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:21:30.93#ibcon#first serial, iclass 20, count 0 2006.189.08:21:30.93#ibcon#enter sib2, iclass 20, count 0 2006.189.08:21:30.93#ibcon#flushed, iclass 20, count 0 2006.189.08:21:30.93#ibcon#about to write, iclass 20, count 0 2006.189.08:21:30.93#ibcon#wrote, iclass 20, count 0 2006.189.08:21:30.93#ibcon#about to read 3, iclass 20, count 0 2006.189.08:21:30.95#ibcon#read 3, iclass 20, count 0 2006.189.08:21:30.95#ibcon#about to read 4, iclass 20, count 0 2006.189.08:21:30.95#ibcon#read 4, iclass 20, count 0 2006.189.08:21:30.95#ibcon#about to read 5, iclass 20, count 0 2006.189.08:21:30.95#ibcon#read 5, iclass 20, count 0 2006.189.08:21:30.95#ibcon#about to read 6, iclass 20, count 0 2006.189.08:21:30.95#ibcon#read 6, iclass 20, count 0 2006.189.08:21:30.95#ibcon#end of sib2, iclass 20, count 0 2006.189.08:21:30.95#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:21:30.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:21:30.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:21:30.95#ibcon#*before write, iclass 20, count 0 2006.189.08:21:30.95#ibcon#enter sib2, iclass 20, count 0 2006.189.08:21:30.95#ibcon#flushed, iclass 20, count 0 2006.189.08:21:30.95#ibcon#about to write, iclass 20, count 0 2006.189.08:21:30.95#ibcon#wrote, iclass 20, count 0 2006.189.08:21:30.95#ibcon#about to read 3, iclass 20, count 0 2006.189.08:21:30.99#ibcon#read 3, iclass 20, count 0 2006.189.08:21:30.99#ibcon#about to read 4, iclass 20, count 0 2006.189.08:21:30.99#ibcon#read 4, iclass 20, count 0 2006.189.08:21:30.99#ibcon#about to read 5, iclass 20, count 0 2006.189.08:21:30.99#ibcon#read 5, iclass 20, count 0 2006.189.08:21:30.99#ibcon#about to read 6, iclass 20, count 0 2006.189.08:21:30.99#ibcon#read 6, iclass 20, count 0 2006.189.08:21:30.99#ibcon#end of sib2, iclass 20, count 0 2006.189.08:21:30.99#ibcon#*after write, iclass 20, count 0 2006.189.08:21:30.99#ibcon#*before return 0, iclass 20, count 0 2006.189.08:21:30.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:30.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.189.08:21:30.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:21:30.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:21:30.99$vc4f8/vb=2,4 2006.189.08:21:30.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.189.08:21:30.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.189.08:21:30.99#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:30.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:31.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:31.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:31.05#ibcon#enter wrdev, iclass 22, count 2 2006.189.08:21:31.05#ibcon#first serial, iclass 22, count 2 2006.189.08:21:31.05#ibcon#enter sib2, iclass 22, count 2 2006.189.08:21:31.05#ibcon#flushed, iclass 22, count 2 2006.189.08:21:31.05#ibcon#about to write, iclass 22, count 2 2006.189.08:21:31.05#ibcon#wrote, iclass 22, count 2 2006.189.08:21:31.05#ibcon#about to read 3, iclass 22, count 2 2006.189.08:21:31.07#ibcon#read 3, iclass 22, count 2 2006.189.08:21:31.07#ibcon#about to read 4, iclass 22, count 2 2006.189.08:21:31.07#ibcon#read 4, iclass 22, count 2 2006.189.08:21:31.07#ibcon#about to read 5, iclass 22, count 2 2006.189.08:21:31.07#ibcon#read 5, iclass 22, count 2 2006.189.08:21:31.07#ibcon#about to read 6, iclass 22, count 2 2006.189.08:21:31.07#ibcon#read 6, iclass 22, count 2 2006.189.08:21:31.07#ibcon#end of sib2, iclass 22, count 2 2006.189.08:21:31.07#ibcon#*mode == 0, iclass 22, count 2 2006.189.08:21:31.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.189.08:21:31.07#ibcon#[27=AT02-04\r\n] 2006.189.08:21:31.07#ibcon#*before write, iclass 22, count 2 2006.189.08:21:31.07#ibcon#enter sib2, iclass 22, count 2 2006.189.08:21:31.07#ibcon#flushed, iclass 22, count 2 2006.189.08:21:31.07#ibcon#about to write, iclass 22, count 2 2006.189.08:21:31.07#ibcon#wrote, iclass 22, count 2 2006.189.08:21:31.07#ibcon#about to read 3, iclass 22, count 2 2006.189.08:21:31.10#ibcon#read 3, iclass 22, count 2 2006.189.08:21:31.10#ibcon#about to read 4, iclass 22, count 2 2006.189.08:21:31.10#ibcon#read 4, iclass 22, count 2 2006.189.08:21:31.10#ibcon#about to read 5, iclass 22, count 2 2006.189.08:21:31.10#ibcon#read 5, iclass 22, count 2 2006.189.08:21:31.10#ibcon#about to read 6, iclass 22, count 2 2006.189.08:21:31.10#ibcon#read 6, iclass 22, count 2 2006.189.08:21:31.10#ibcon#end of sib2, iclass 22, count 2 2006.189.08:21:31.10#ibcon#*after write, iclass 22, count 2 2006.189.08:21:31.10#ibcon#*before return 0, iclass 22, count 2 2006.189.08:21:31.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:31.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.189.08:21:31.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.189.08:21:31.10#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:31.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:31.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:31.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:31.22#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:21:31.22#ibcon#first serial, iclass 22, count 0 2006.189.08:21:31.22#ibcon#enter sib2, iclass 22, count 0 2006.189.08:21:31.22#ibcon#flushed, iclass 22, count 0 2006.189.08:21:31.22#ibcon#about to write, iclass 22, count 0 2006.189.08:21:31.22#ibcon#wrote, iclass 22, count 0 2006.189.08:21:31.22#ibcon#about to read 3, iclass 22, count 0 2006.189.08:21:31.24#ibcon#read 3, iclass 22, count 0 2006.189.08:21:31.24#ibcon#about to read 4, iclass 22, count 0 2006.189.08:21:31.24#ibcon#read 4, iclass 22, count 0 2006.189.08:21:31.24#ibcon#about to read 5, iclass 22, count 0 2006.189.08:21:31.24#ibcon#read 5, iclass 22, count 0 2006.189.08:21:31.24#ibcon#about to read 6, iclass 22, count 0 2006.189.08:21:31.24#ibcon#read 6, iclass 22, count 0 2006.189.08:21:31.24#ibcon#end of sib2, iclass 22, count 0 2006.189.08:21:31.24#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:21:31.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:21:31.24#ibcon#[27=USB\r\n] 2006.189.08:21:31.24#ibcon#*before write, iclass 22, count 0 2006.189.08:21:31.24#ibcon#enter sib2, iclass 22, count 0 2006.189.08:21:31.24#ibcon#flushed, iclass 22, count 0 2006.189.08:21:31.24#ibcon#about to write, iclass 22, count 0 2006.189.08:21:31.24#ibcon#wrote, iclass 22, count 0 2006.189.08:21:31.24#ibcon#about to read 3, iclass 22, count 0 2006.189.08:21:31.27#ibcon#read 3, iclass 22, count 0 2006.189.08:21:31.27#ibcon#about to read 4, iclass 22, count 0 2006.189.08:21:31.27#ibcon#read 4, iclass 22, count 0 2006.189.08:21:31.27#ibcon#about to read 5, iclass 22, count 0 2006.189.08:21:31.27#ibcon#read 5, iclass 22, count 0 2006.189.08:21:31.27#ibcon#about to read 6, iclass 22, count 0 2006.189.08:21:31.27#ibcon#read 6, iclass 22, count 0 2006.189.08:21:31.27#ibcon#end of sib2, iclass 22, count 0 2006.189.08:21:31.27#ibcon#*after write, iclass 22, count 0 2006.189.08:21:31.27#ibcon#*before return 0, iclass 22, count 0 2006.189.08:21:31.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:31.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.189.08:21:31.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:21:31.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:21:31.27$vc4f8/vblo=3,656.99 2006.189.08:21:31.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.189.08:21:31.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.189.08:21:31.27#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:31.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:31.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:31.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:31.27#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:21:31.27#ibcon#first serial, iclass 24, count 0 2006.189.08:21:31.27#ibcon#enter sib2, iclass 24, count 0 2006.189.08:21:31.27#ibcon#flushed, iclass 24, count 0 2006.189.08:21:31.27#ibcon#about to write, iclass 24, count 0 2006.189.08:21:31.27#ibcon#wrote, iclass 24, count 0 2006.189.08:21:31.27#ibcon#about to read 3, iclass 24, count 0 2006.189.08:21:31.29#ibcon#read 3, iclass 24, count 0 2006.189.08:21:31.29#ibcon#about to read 4, iclass 24, count 0 2006.189.08:21:31.29#ibcon#read 4, iclass 24, count 0 2006.189.08:21:31.29#ibcon#about to read 5, iclass 24, count 0 2006.189.08:21:31.29#ibcon#read 5, iclass 24, count 0 2006.189.08:21:31.29#ibcon#about to read 6, iclass 24, count 0 2006.189.08:21:31.29#ibcon#read 6, iclass 24, count 0 2006.189.08:21:31.29#ibcon#end of sib2, iclass 24, count 0 2006.189.08:21:31.29#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:21:31.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:21:31.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:21:31.29#ibcon#*before write, iclass 24, count 0 2006.189.08:21:31.29#ibcon#enter sib2, iclass 24, count 0 2006.189.08:21:31.29#ibcon#flushed, iclass 24, count 0 2006.189.08:21:31.29#ibcon#about to write, iclass 24, count 0 2006.189.08:21:31.29#ibcon#wrote, iclass 24, count 0 2006.189.08:21:31.29#ibcon#about to read 3, iclass 24, count 0 2006.189.08:21:31.33#ibcon#read 3, iclass 24, count 0 2006.189.08:21:31.33#ibcon#about to read 4, iclass 24, count 0 2006.189.08:21:31.33#ibcon#read 4, iclass 24, count 0 2006.189.08:21:31.33#ibcon#about to read 5, iclass 24, count 0 2006.189.08:21:31.33#ibcon#read 5, iclass 24, count 0 2006.189.08:21:31.33#ibcon#about to read 6, iclass 24, count 0 2006.189.08:21:31.33#ibcon#read 6, iclass 24, count 0 2006.189.08:21:31.33#ibcon#end of sib2, iclass 24, count 0 2006.189.08:21:31.33#ibcon#*after write, iclass 24, count 0 2006.189.08:21:31.33#ibcon#*before return 0, iclass 24, count 0 2006.189.08:21:31.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:31.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.189.08:21:31.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:21:31.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:21:31.33$vc4f8/vb=3,4 2006.189.08:21:31.33#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.189.08:21:31.33#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.189.08:21:31.33#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:31.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:31.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:31.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:31.39#ibcon#enter wrdev, iclass 26, count 2 2006.189.08:21:31.39#ibcon#first serial, iclass 26, count 2 2006.189.08:21:31.39#ibcon#enter sib2, iclass 26, count 2 2006.189.08:21:31.39#ibcon#flushed, iclass 26, count 2 2006.189.08:21:31.39#ibcon#about to write, iclass 26, count 2 2006.189.08:21:31.39#ibcon#wrote, iclass 26, count 2 2006.189.08:21:31.39#ibcon#about to read 3, iclass 26, count 2 2006.189.08:21:31.41#ibcon#read 3, iclass 26, count 2 2006.189.08:21:31.41#ibcon#about to read 4, iclass 26, count 2 2006.189.08:21:31.41#ibcon#read 4, iclass 26, count 2 2006.189.08:21:31.41#ibcon#about to read 5, iclass 26, count 2 2006.189.08:21:31.41#ibcon#read 5, iclass 26, count 2 2006.189.08:21:31.41#ibcon#about to read 6, iclass 26, count 2 2006.189.08:21:31.41#ibcon#read 6, iclass 26, count 2 2006.189.08:21:31.41#ibcon#end of sib2, iclass 26, count 2 2006.189.08:21:31.41#ibcon#*mode == 0, iclass 26, count 2 2006.189.08:21:31.41#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.189.08:21:31.41#ibcon#[27=AT03-04\r\n] 2006.189.08:21:31.41#ibcon#*before write, iclass 26, count 2 2006.189.08:21:31.41#ibcon#enter sib2, iclass 26, count 2 2006.189.08:21:31.41#ibcon#flushed, iclass 26, count 2 2006.189.08:21:31.41#ibcon#about to write, iclass 26, count 2 2006.189.08:21:31.41#ibcon#wrote, iclass 26, count 2 2006.189.08:21:31.41#ibcon#about to read 3, iclass 26, count 2 2006.189.08:21:31.44#ibcon#read 3, iclass 26, count 2 2006.189.08:21:31.44#ibcon#about to read 4, iclass 26, count 2 2006.189.08:21:31.44#ibcon#read 4, iclass 26, count 2 2006.189.08:21:31.44#ibcon#about to read 5, iclass 26, count 2 2006.189.08:21:31.44#ibcon#read 5, iclass 26, count 2 2006.189.08:21:31.44#ibcon#about to read 6, iclass 26, count 2 2006.189.08:21:31.44#ibcon#read 6, iclass 26, count 2 2006.189.08:21:31.44#ibcon#end of sib2, iclass 26, count 2 2006.189.08:21:31.44#ibcon#*after write, iclass 26, count 2 2006.189.08:21:31.44#ibcon#*before return 0, iclass 26, count 2 2006.189.08:21:31.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:31.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.189.08:21:31.44#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.189.08:21:31.44#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:31.44#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:31.56#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:31.56#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:31.56#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:21:31.56#ibcon#first serial, iclass 26, count 0 2006.189.08:21:31.56#ibcon#enter sib2, iclass 26, count 0 2006.189.08:21:31.56#ibcon#flushed, iclass 26, count 0 2006.189.08:21:31.56#ibcon#about to write, iclass 26, count 0 2006.189.08:21:31.56#ibcon#wrote, iclass 26, count 0 2006.189.08:21:31.56#ibcon#about to read 3, iclass 26, count 0 2006.189.08:21:31.58#ibcon#read 3, iclass 26, count 0 2006.189.08:21:31.58#ibcon#about to read 4, iclass 26, count 0 2006.189.08:21:31.58#ibcon#read 4, iclass 26, count 0 2006.189.08:21:31.58#ibcon#about to read 5, iclass 26, count 0 2006.189.08:21:31.58#ibcon#read 5, iclass 26, count 0 2006.189.08:21:31.58#ibcon#about to read 6, iclass 26, count 0 2006.189.08:21:31.58#ibcon#read 6, iclass 26, count 0 2006.189.08:21:31.58#ibcon#end of sib2, iclass 26, count 0 2006.189.08:21:31.58#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:21:31.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:21:31.58#ibcon#[27=USB\r\n] 2006.189.08:21:31.58#ibcon#*before write, iclass 26, count 0 2006.189.08:21:31.58#ibcon#enter sib2, iclass 26, count 0 2006.189.08:21:31.58#ibcon#flushed, iclass 26, count 0 2006.189.08:21:31.58#ibcon#about to write, iclass 26, count 0 2006.189.08:21:31.58#ibcon#wrote, iclass 26, count 0 2006.189.08:21:31.58#ibcon#about to read 3, iclass 26, count 0 2006.189.08:21:31.61#ibcon#read 3, iclass 26, count 0 2006.189.08:21:31.61#ibcon#about to read 4, iclass 26, count 0 2006.189.08:21:31.61#ibcon#read 4, iclass 26, count 0 2006.189.08:21:31.61#ibcon#about to read 5, iclass 26, count 0 2006.189.08:21:31.61#ibcon#read 5, iclass 26, count 0 2006.189.08:21:31.61#ibcon#about to read 6, iclass 26, count 0 2006.189.08:21:31.61#ibcon#read 6, iclass 26, count 0 2006.189.08:21:31.61#ibcon#end of sib2, iclass 26, count 0 2006.189.08:21:31.61#ibcon#*after write, iclass 26, count 0 2006.189.08:21:31.61#ibcon#*before return 0, iclass 26, count 0 2006.189.08:21:31.61#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:31.61#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.189.08:21:31.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:21:31.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:21:31.61$vc4f8/vblo=4,712.99 2006.189.08:21:31.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.189.08:21:31.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.189.08:21:31.61#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:31.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:31.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:31.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:31.61#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:21:31.61#ibcon#first serial, iclass 28, count 0 2006.189.08:21:31.61#ibcon#enter sib2, iclass 28, count 0 2006.189.08:21:31.61#ibcon#flushed, iclass 28, count 0 2006.189.08:21:31.61#ibcon#about to write, iclass 28, count 0 2006.189.08:21:31.61#ibcon#wrote, iclass 28, count 0 2006.189.08:21:31.61#ibcon#about to read 3, iclass 28, count 0 2006.189.08:21:31.63#ibcon#read 3, iclass 28, count 0 2006.189.08:21:31.63#ibcon#about to read 4, iclass 28, count 0 2006.189.08:21:31.63#ibcon#read 4, iclass 28, count 0 2006.189.08:21:31.63#ibcon#about to read 5, iclass 28, count 0 2006.189.08:21:31.63#ibcon#read 5, iclass 28, count 0 2006.189.08:21:31.63#ibcon#about to read 6, iclass 28, count 0 2006.189.08:21:31.63#ibcon#read 6, iclass 28, count 0 2006.189.08:21:31.63#ibcon#end of sib2, iclass 28, count 0 2006.189.08:21:31.63#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:21:31.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:21:31.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:21:31.63#ibcon#*before write, iclass 28, count 0 2006.189.08:21:31.63#ibcon#enter sib2, iclass 28, count 0 2006.189.08:21:31.63#ibcon#flushed, iclass 28, count 0 2006.189.08:21:31.63#ibcon#about to write, iclass 28, count 0 2006.189.08:21:31.63#ibcon#wrote, iclass 28, count 0 2006.189.08:21:31.63#ibcon#about to read 3, iclass 28, count 0 2006.189.08:21:31.67#ibcon#read 3, iclass 28, count 0 2006.189.08:21:31.67#ibcon#about to read 4, iclass 28, count 0 2006.189.08:21:31.67#ibcon#read 4, iclass 28, count 0 2006.189.08:21:31.67#ibcon#about to read 5, iclass 28, count 0 2006.189.08:21:31.67#ibcon#read 5, iclass 28, count 0 2006.189.08:21:31.67#ibcon#about to read 6, iclass 28, count 0 2006.189.08:21:31.67#ibcon#read 6, iclass 28, count 0 2006.189.08:21:31.67#ibcon#end of sib2, iclass 28, count 0 2006.189.08:21:31.67#ibcon#*after write, iclass 28, count 0 2006.189.08:21:31.67#ibcon#*before return 0, iclass 28, count 0 2006.189.08:21:31.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:31.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.189.08:21:31.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:21:31.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:21:31.67$vc4f8/vb=4,4 2006.189.08:21:31.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.189.08:21:31.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.189.08:21:31.67#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:31.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:31.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:31.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:31.73#ibcon#enter wrdev, iclass 30, count 2 2006.189.08:21:31.73#ibcon#first serial, iclass 30, count 2 2006.189.08:21:31.73#ibcon#enter sib2, iclass 30, count 2 2006.189.08:21:31.73#ibcon#flushed, iclass 30, count 2 2006.189.08:21:31.73#ibcon#about to write, iclass 30, count 2 2006.189.08:21:31.73#ibcon#wrote, iclass 30, count 2 2006.189.08:21:31.73#ibcon#about to read 3, iclass 30, count 2 2006.189.08:21:31.75#ibcon#read 3, iclass 30, count 2 2006.189.08:21:31.75#ibcon#about to read 4, iclass 30, count 2 2006.189.08:21:31.75#ibcon#read 4, iclass 30, count 2 2006.189.08:21:31.75#ibcon#about to read 5, iclass 30, count 2 2006.189.08:21:31.75#ibcon#read 5, iclass 30, count 2 2006.189.08:21:31.75#ibcon#about to read 6, iclass 30, count 2 2006.189.08:21:31.75#ibcon#read 6, iclass 30, count 2 2006.189.08:21:31.75#ibcon#end of sib2, iclass 30, count 2 2006.189.08:21:31.75#ibcon#*mode == 0, iclass 30, count 2 2006.189.08:21:31.75#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.189.08:21:31.75#ibcon#[27=AT04-04\r\n] 2006.189.08:21:31.75#ibcon#*before write, iclass 30, count 2 2006.189.08:21:31.75#ibcon#enter sib2, iclass 30, count 2 2006.189.08:21:31.75#ibcon#flushed, iclass 30, count 2 2006.189.08:21:31.75#ibcon#about to write, iclass 30, count 2 2006.189.08:21:31.75#ibcon#wrote, iclass 30, count 2 2006.189.08:21:31.75#ibcon#about to read 3, iclass 30, count 2 2006.189.08:21:31.78#ibcon#read 3, iclass 30, count 2 2006.189.08:21:31.78#ibcon#about to read 4, iclass 30, count 2 2006.189.08:21:31.78#ibcon#read 4, iclass 30, count 2 2006.189.08:21:31.78#ibcon#about to read 5, iclass 30, count 2 2006.189.08:21:31.78#ibcon#read 5, iclass 30, count 2 2006.189.08:21:31.78#ibcon#about to read 6, iclass 30, count 2 2006.189.08:21:31.78#ibcon#read 6, iclass 30, count 2 2006.189.08:21:31.78#ibcon#end of sib2, iclass 30, count 2 2006.189.08:21:31.78#ibcon#*after write, iclass 30, count 2 2006.189.08:21:31.78#ibcon#*before return 0, iclass 30, count 2 2006.189.08:21:31.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:31.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.189.08:21:31.78#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.189.08:21:31.78#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:31.78#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:31.90#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:31.90#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:31.90#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:21:31.90#ibcon#first serial, iclass 30, count 0 2006.189.08:21:31.90#ibcon#enter sib2, iclass 30, count 0 2006.189.08:21:31.90#ibcon#flushed, iclass 30, count 0 2006.189.08:21:31.90#ibcon#about to write, iclass 30, count 0 2006.189.08:21:31.90#ibcon#wrote, iclass 30, count 0 2006.189.08:21:31.90#ibcon#about to read 3, iclass 30, count 0 2006.189.08:21:31.92#ibcon#read 3, iclass 30, count 0 2006.189.08:21:31.92#ibcon#about to read 4, iclass 30, count 0 2006.189.08:21:31.92#ibcon#read 4, iclass 30, count 0 2006.189.08:21:31.92#ibcon#about to read 5, iclass 30, count 0 2006.189.08:21:31.92#ibcon#read 5, iclass 30, count 0 2006.189.08:21:31.92#ibcon#about to read 6, iclass 30, count 0 2006.189.08:21:31.92#ibcon#read 6, iclass 30, count 0 2006.189.08:21:31.92#ibcon#end of sib2, iclass 30, count 0 2006.189.08:21:31.92#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:21:31.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:21:31.92#ibcon#[27=USB\r\n] 2006.189.08:21:31.92#ibcon#*before write, iclass 30, count 0 2006.189.08:21:31.92#ibcon#enter sib2, iclass 30, count 0 2006.189.08:21:31.92#ibcon#flushed, iclass 30, count 0 2006.189.08:21:31.92#ibcon#about to write, iclass 30, count 0 2006.189.08:21:31.92#ibcon#wrote, iclass 30, count 0 2006.189.08:21:31.92#ibcon#about to read 3, iclass 30, count 0 2006.189.08:21:31.95#ibcon#read 3, iclass 30, count 0 2006.189.08:21:31.95#ibcon#about to read 4, iclass 30, count 0 2006.189.08:21:31.95#ibcon#read 4, iclass 30, count 0 2006.189.08:21:31.95#ibcon#about to read 5, iclass 30, count 0 2006.189.08:21:31.95#ibcon#read 5, iclass 30, count 0 2006.189.08:21:31.95#ibcon#about to read 6, iclass 30, count 0 2006.189.08:21:31.95#ibcon#read 6, iclass 30, count 0 2006.189.08:21:31.95#ibcon#end of sib2, iclass 30, count 0 2006.189.08:21:31.95#ibcon#*after write, iclass 30, count 0 2006.189.08:21:31.95#ibcon#*before return 0, iclass 30, count 0 2006.189.08:21:31.95#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:31.95#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.189.08:21:31.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:21:31.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:21:31.95$vc4f8/vblo=5,744.99 2006.189.08:21:31.95#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.189.08:21:31.95#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.189.08:21:31.95#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:31.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:31.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:31.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:31.95#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:21:31.95#ibcon#first serial, iclass 32, count 0 2006.189.08:21:31.95#ibcon#enter sib2, iclass 32, count 0 2006.189.08:21:31.95#ibcon#flushed, iclass 32, count 0 2006.189.08:21:31.95#ibcon#about to write, iclass 32, count 0 2006.189.08:21:31.95#ibcon#wrote, iclass 32, count 0 2006.189.08:21:31.95#ibcon#about to read 3, iclass 32, count 0 2006.189.08:21:31.97#ibcon#read 3, iclass 32, count 0 2006.189.08:21:31.97#ibcon#about to read 4, iclass 32, count 0 2006.189.08:21:31.97#ibcon#read 4, iclass 32, count 0 2006.189.08:21:31.97#ibcon#about to read 5, iclass 32, count 0 2006.189.08:21:31.97#ibcon#read 5, iclass 32, count 0 2006.189.08:21:31.97#ibcon#about to read 6, iclass 32, count 0 2006.189.08:21:31.97#ibcon#read 6, iclass 32, count 0 2006.189.08:21:31.97#ibcon#end of sib2, iclass 32, count 0 2006.189.08:21:31.97#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:21:31.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:21:31.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:21:31.97#ibcon#*before write, iclass 32, count 0 2006.189.08:21:31.97#ibcon#enter sib2, iclass 32, count 0 2006.189.08:21:31.97#ibcon#flushed, iclass 32, count 0 2006.189.08:21:31.97#ibcon#about to write, iclass 32, count 0 2006.189.08:21:31.97#ibcon#wrote, iclass 32, count 0 2006.189.08:21:31.97#ibcon#about to read 3, iclass 32, count 0 2006.189.08:21:32.01#ibcon#read 3, iclass 32, count 0 2006.189.08:21:32.01#ibcon#about to read 4, iclass 32, count 0 2006.189.08:21:32.01#ibcon#read 4, iclass 32, count 0 2006.189.08:21:32.01#ibcon#about to read 5, iclass 32, count 0 2006.189.08:21:32.01#ibcon#read 5, iclass 32, count 0 2006.189.08:21:32.01#ibcon#about to read 6, iclass 32, count 0 2006.189.08:21:32.01#ibcon#read 6, iclass 32, count 0 2006.189.08:21:32.01#ibcon#end of sib2, iclass 32, count 0 2006.189.08:21:32.01#ibcon#*after write, iclass 32, count 0 2006.189.08:21:32.01#ibcon#*before return 0, iclass 32, count 0 2006.189.08:21:32.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:32.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.189.08:21:32.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:21:32.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:21:32.01$vc4f8/vb=5,4 2006.189.08:21:32.01#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.189.08:21:32.01#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.189.08:21:32.01#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:32.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:32.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:32.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:32.07#ibcon#enter wrdev, iclass 34, count 2 2006.189.08:21:32.07#ibcon#first serial, iclass 34, count 2 2006.189.08:21:32.07#ibcon#enter sib2, iclass 34, count 2 2006.189.08:21:32.07#ibcon#flushed, iclass 34, count 2 2006.189.08:21:32.07#ibcon#about to write, iclass 34, count 2 2006.189.08:21:32.07#ibcon#wrote, iclass 34, count 2 2006.189.08:21:32.07#ibcon#about to read 3, iclass 34, count 2 2006.189.08:21:32.09#ibcon#read 3, iclass 34, count 2 2006.189.08:21:32.09#ibcon#about to read 4, iclass 34, count 2 2006.189.08:21:32.09#ibcon#read 4, iclass 34, count 2 2006.189.08:21:32.09#ibcon#about to read 5, iclass 34, count 2 2006.189.08:21:32.09#ibcon#read 5, iclass 34, count 2 2006.189.08:21:32.09#ibcon#about to read 6, iclass 34, count 2 2006.189.08:21:32.09#ibcon#read 6, iclass 34, count 2 2006.189.08:21:32.09#ibcon#end of sib2, iclass 34, count 2 2006.189.08:21:32.09#ibcon#*mode == 0, iclass 34, count 2 2006.189.08:21:32.09#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.189.08:21:32.09#ibcon#[27=AT05-04\r\n] 2006.189.08:21:32.09#ibcon#*before write, iclass 34, count 2 2006.189.08:21:32.09#ibcon#enter sib2, iclass 34, count 2 2006.189.08:21:32.09#ibcon#flushed, iclass 34, count 2 2006.189.08:21:32.09#ibcon#about to write, iclass 34, count 2 2006.189.08:21:32.09#ibcon#wrote, iclass 34, count 2 2006.189.08:21:32.09#ibcon#about to read 3, iclass 34, count 2 2006.189.08:21:32.12#ibcon#read 3, iclass 34, count 2 2006.189.08:21:32.12#ibcon#about to read 4, iclass 34, count 2 2006.189.08:21:32.12#ibcon#read 4, iclass 34, count 2 2006.189.08:21:32.12#ibcon#about to read 5, iclass 34, count 2 2006.189.08:21:32.12#ibcon#read 5, iclass 34, count 2 2006.189.08:21:32.12#ibcon#about to read 6, iclass 34, count 2 2006.189.08:21:32.12#ibcon#read 6, iclass 34, count 2 2006.189.08:21:32.12#ibcon#end of sib2, iclass 34, count 2 2006.189.08:21:32.12#ibcon#*after write, iclass 34, count 2 2006.189.08:21:32.12#ibcon#*before return 0, iclass 34, count 2 2006.189.08:21:32.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:32.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.189.08:21:32.12#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.189.08:21:32.12#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:32.12#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:32.24#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:32.24#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:32.24#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:21:32.24#ibcon#first serial, iclass 34, count 0 2006.189.08:21:32.24#ibcon#enter sib2, iclass 34, count 0 2006.189.08:21:32.24#ibcon#flushed, iclass 34, count 0 2006.189.08:21:32.24#ibcon#about to write, iclass 34, count 0 2006.189.08:21:32.24#ibcon#wrote, iclass 34, count 0 2006.189.08:21:32.24#ibcon#about to read 3, iclass 34, count 0 2006.189.08:21:32.26#ibcon#read 3, iclass 34, count 0 2006.189.08:21:32.26#ibcon#about to read 4, iclass 34, count 0 2006.189.08:21:32.26#ibcon#read 4, iclass 34, count 0 2006.189.08:21:32.26#ibcon#about to read 5, iclass 34, count 0 2006.189.08:21:32.26#ibcon#read 5, iclass 34, count 0 2006.189.08:21:32.26#ibcon#about to read 6, iclass 34, count 0 2006.189.08:21:32.26#ibcon#read 6, iclass 34, count 0 2006.189.08:21:32.26#ibcon#end of sib2, iclass 34, count 0 2006.189.08:21:32.26#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:21:32.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:21:32.26#ibcon#[27=USB\r\n] 2006.189.08:21:32.26#ibcon#*before write, iclass 34, count 0 2006.189.08:21:32.26#ibcon#enter sib2, iclass 34, count 0 2006.189.08:21:32.26#ibcon#flushed, iclass 34, count 0 2006.189.08:21:32.26#ibcon#about to write, iclass 34, count 0 2006.189.08:21:32.26#ibcon#wrote, iclass 34, count 0 2006.189.08:21:32.26#ibcon#about to read 3, iclass 34, count 0 2006.189.08:21:32.29#ibcon#read 3, iclass 34, count 0 2006.189.08:21:32.29#ibcon#about to read 4, iclass 34, count 0 2006.189.08:21:32.29#ibcon#read 4, iclass 34, count 0 2006.189.08:21:32.29#ibcon#about to read 5, iclass 34, count 0 2006.189.08:21:32.29#ibcon#read 5, iclass 34, count 0 2006.189.08:21:32.29#ibcon#about to read 6, iclass 34, count 0 2006.189.08:21:32.29#ibcon#read 6, iclass 34, count 0 2006.189.08:21:32.29#ibcon#end of sib2, iclass 34, count 0 2006.189.08:21:32.29#ibcon#*after write, iclass 34, count 0 2006.189.08:21:32.29#ibcon#*before return 0, iclass 34, count 0 2006.189.08:21:32.29#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:32.29#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.189.08:21:32.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:21:32.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:21:32.29$vc4f8/vblo=6,752.99 2006.189.08:21:32.29#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.08:21:32.29#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.08:21:32.29#ibcon#ireg 17 cls_cnt 0 2006.189.08:21:32.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:32.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:32.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:32.29#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:21:32.29#ibcon#first serial, iclass 36, count 0 2006.189.08:21:32.29#ibcon#enter sib2, iclass 36, count 0 2006.189.08:21:32.29#ibcon#flushed, iclass 36, count 0 2006.189.08:21:32.29#ibcon#about to write, iclass 36, count 0 2006.189.08:21:32.29#ibcon#wrote, iclass 36, count 0 2006.189.08:21:32.29#ibcon#about to read 3, iclass 36, count 0 2006.189.08:21:32.31#ibcon#read 3, iclass 36, count 0 2006.189.08:21:32.31#ibcon#about to read 4, iclass 36, count 0 2006.189.08:21:32.31#ibcon#read 4, iclass 36, count 0 2006.189.08:21:32.31#ibcon#about to read 5, iclass 36, count 0 2006.189.08:21:32.31#ibcon#read 5, iclass 36, count 0 2006.189.08:21:32.31#ibcon#about to read 6, iclass 36, count 0 2006.189.08:21:32.31#ibcon#read 6, iclass 36, count 0 2006.189.08:21:32.31#ibcon#end of sib2, iclass 36, count 0 2006.189.08:21:32.31#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:21:32.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:21:32.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:21:32.31#ibcon#*before write, iclass 36, count 0 2006.189.08:21:32.31#ibcon#enter sib2, iclass 36, count 0 2006.189.08:21:32.31#ibcon#flushed, iclass 36, count 0 2006.189.08:21:32.31#ibcon#about to write, iclass 36, count 0 2006.189.08:21:32.31#ibcon#wrote, iclass 36, count 0 2006.189.08:21:32.31#ibcon#about to read 3, iclass 36, count 0 2006.189.08:21:32.35#ibcon#read 3, iclass 36, count 0 2006.189.08:21:32.35#ibcon#about to read 4, iclass 36, count 0 2006.189.08:21:32.35#ibcon#read 4, iclass 36, count 0 2006.189.08:21:32.35#ibcon#about to read 5, iclass 36, count 0 2006.189.08:21:32.35#ibcon#read 5, iclass 36, count 0 2006.189.08:21:32.35#ibcon#about to read 6, iclass 36, count 0 2006.189.08:21:32.35#ibcon#read 6, iclass 36, count 0 2006.189.08:21:32.35#ibcon#end of sib2, iclass 36, count 0 2006.189.08:21:32.35#ibcon#*after write, iclass 36, count 0 2006.189.08:21:32.35#ibcon#*before return 0, iclass 36, count 0 2006.189.08:21:32.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:32.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:21:32.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:21:32.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:21:32.35$vc4f8/vb=6,4 2006.189.08:21:32.35#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.189.08:21:32.35#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.189.08:21:32.35#ibcon#ireg 11 cls_cnt 2 2006.189.08:21:32.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:32.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:32.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:32.41#ibcon#enter wrdev, iclass 38, count 2 2006.189.08:21:32.41#ibcon#first serial, iclass 38, count 2 2006.189.08:21:32.41#ibcon#enter sib2, iclass 38, count 2 2006.189.08:21:32.41#ibcon#flushed, iclass 38, count 2 2006.189.08:21:32.41#ibcon#about to write, iclass 38, count 2 2006.189.08:21:32.41#ibcon#wrote, iclass 38, count 2 2006.189.08:21:32.41#ibcon#about to read 3, iclass 38, count 2 2006.189.08:21:32.43#ibcon#read 3, iclass 38, count 2 2006.189.08:21:32.43#ibcon#about to read 4, iclass 38, count 2 2006.189.08:21:32.43#ibcon#read 4, iclass 38, count 2 2006.189.08:21:32.43#ibcon#about to read 5, iclass 38, count 2 2006.189.08:21:32.43#ibcon#read 5, iclass 38, count 2 2006.189.08:21:32.43#ibcon#about to read 6, iclass 38, count 2 2006.189.08:21:32.43#ibcon#read 6, iclass 38, count 2 2006.189.08:21:32.43#ibcon#end of sib2, iclass 38, count 2 2006.189.08:21:32.43#ibcon#*mode == 0, iclass 38, count 2 2006.189.08:21:32.43#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.189.08:21:32.43#ibcon#[27=AT06-04\r\n] 2006.189.08:21:32.43#ibcon#*before write, iclass 38, count 2 2006.189.08:21:32.43#ibcon#enter sib2, iclass 38, count 2 2006.189.08:21:32.43#ibcon#flushed, iclass 38, count 2 2006.189.08:21:32.43#ibcon#about to write, iclass 38, count 2 2006.189.08:21:32.43#ibcon#wrote, iclass 38, count 2 2006.189.08:21:32.43#ibcon#about to read 3, iclass 38, count 2 2006.189.08:21:32.46#ibcon#read 3, iclass 38, count 2 2006.189.08:21:32.46#ibcon#about to read 4, iclass 38, count 2 2006.189.08:21:32.46#ibcon#read 4, iclass 38, count 2 2006.189.08:21:32.46#ibcon#about to read 5, iclass 38, count 2 2006.189.08:21:32.46#ibcon#read 5, iclass 38, count 2 2006.189.08:21:32.46#ibcon#about to read 6, iclass 38, count 2 2006.189.08:21:32.46#ibcon#read 6, iclass 38, count 2 2006.189.08:21:32.46#ibcon#end of sib2, iclass 38, count 2 2006.189.08:21:32.46#ibcon#*after write, iclass 38, count 2 2006.189.08:21:32.46#ibcon#*before return 0, iclass 38, count 2 2006.189.08:21:32.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:32.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.189.08:21:32.46#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.189.08:21:32.46#ibcon#ireg 7 cls_cnt 0 2006.189.08:21:32.46#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:32.58#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:32.58#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:32.58#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:21:32.58#ibcon#first serial, iclass 38, count 0 2006.189.08:21:32.58#ibcon#enter sib2, iclass 38, count 0 2006.189.08:21:32.58#ibcon#flushed, iclass 38, count 0 2006.189.08:21:32.58#ibcon#about to write, iclass 38, count 0 2006.189.08:21:32.58#ibcon#wrote, iclass 38, count 0 2006.189.08:21:32.58#ibcon#about to read 3, iclass 38, count 0 2006.189.08:21:32.60#ibcon#read 3, iclass 38, count 0 2006.189.08:21:32.60#ibcon#about to read 4, iclass 38, count 0 2006.189.08:21:32.60#ibcon#read 4, iclass 38, count 0 2006.189.08:21:32.60#ibcon#about to read 5, iclass 38, count 0 2006.189.08:21:32.60#ibcon#read 5, iclass 38, count 0 2006.189.08:21:32.60#ibcon#about to read 6, iclass 38, count 0 2006.189.08:21:32.60#ibcon#read 6, iclass 38, count 0 2006.189.08:21:32.60#ibcon#end of sib2, iclass 38, count 0 2006.189.08:21:32.60#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:21:32.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:21:32.60#ibcon#[27=USB\r\n] 2006.189.08:21:32.60#ibcon#*before write, iclass 38, count 0 2006.189.08:21:32.60#ibcon#enter sib2, iclass 38, count 0 2006.189.08:21:32.60#ibcon#flushed, iclass 38, count 0 2006.189.08:21:32.60#ibcon#about to write, iclass 38, count 0 2006.189.08:21:32.60#ibcon#wrote, iclass 38, count 0 2006.189.08:21:32.60#ibcon#about to read 3, iclass 38, count 0 2006.189.08:21:32.63#ibcon#read 3, iclass 38, count 0 2006.189.08:21:32.63#ibcon#about to read 4, iclass 38, count 0 2006.189.08:21:32.63#ibcon#read 4, iclass 38, count 0 2006.189.08:21:32.63#ibcon#about to read 5, iclass 38, count 0 2006.189.08:21:32.63#ibcon#read 5, iclass 38, count 0 2006.189.08:21:32.63#ibcon#about to read 6, iclass 38, count 0 2006.189.08:21:32.63#ibcon#read 6, iclass 38, count 0 2006.189.08:21:32.63#ibcon#end of sib2, iclass 38, count 0 2006.189.08:21:32.63#ibcon#*after write, iclass 38, count 0 2006.189.08:21:32.63#ibcon#*before return 0, iclass 38, count 0 2006.189.08:21:32.63#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:32.63#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.189.08:21:32.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:21:32.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:21:32.63$vc4f8/vabw=wide 2006.189.08:21:32.63#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.189.08:21:32.63#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.189.08:21:32.63#ibcon#ireg 8 cls_cnt 0 2006.189.08:21:32.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:32.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:32.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:32.63#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:21:32.63#ibcon#first serial, iclass 40, count 0 2006.189.08:21:32.63#ibcon#enter sib2, iclass 40, count 0 2006.189.08:21:32.63#ibcon#flushed, iclass 40, count 0 2006.189.08:21:32.63#ibcon#about to write, iclass 40, count 0 2006.189.08:21:32.63#ibcon#wrote, iclass 40, count 0 2006.189.08:21:32.63#ibcon#about to read 3, iclass 40, count 0 2006.189.08:21:32.65#ibcon#read 3, iclass 40, count 0 2006.189.08:21:32.65#ibcon#about to read 4, iclass 40, count 0 2006.189.08:21:32.65#ibcon#read 4, iclass 40, count 0 2006.189.08:21:32.65#ibcon#about to read 5, iclass 40, count 0 2006.189.08:21:32.65#ibcon#read 5, iclass 40, count 0 2006.189.08:21:32.65#ibcon#about to read 6, iclass 40, count 0 2006.189.08:21:32.65#ibcon#read 6, iclass 40, count 0 2006.189.08:21:32.65#ibcon#end of sib2, iclass 40, count 0 2006.189.08:21:32.65#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:21:32.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:21:32.65#ibcon#[25=BW32\r\n] 2006.189.08:21:32.65#ibcon#*before write, iclass 40, count 0 2006.189.08:21:32.65#ibcon#enter sib2, iclass 40, count 0 2006.189.08:21:32.65#ibcon#flushed, iclass 40, count 0 2006.189.08:21:32.65#ibcon#about to write, iclass 40, count 0 2006.189.08:21:32.65#ibcon#wrote, iclass 40, count 0 2006.189.08:21:32.65#ibcon#about to read 3, iclass 40, count 0 2006.189.08:21:32.68#ibcon#read 3, iclass 40, count 0 2006.189.08:21:32.68#ibcon#about to read 4, iclass 40, count 0 2006.189.08:21:32.68#ibcon#read 4, iclass 40, count 0 2006.189.08:21:32.68#ibcon#about to read 5, iclass 40, count 0 2006.189.08:21:32.68#ibcon#read 5, iclass 40, count 0 2006.189.08:21:32.68#ibcon#about to read 6, iclass 40, count 0 2006.189.08:21:32.68#ibcon#read 6, iclass 40, count 0 2006.189.08:21:32.68#ibcon#end of sib2, iclass 40, count 0 2006.189.08:21:32.68#ibcon#*after write, iclass 40, count 0 2006.189.08:21:32.68#ibcon#*before return 0, iclass 40, count 0 2006.189.08:21:32.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:32.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.189.08:21:32.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:21:32.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:21:32.68$vc4f8/vbbw=wide 2006.189.08:21:32.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.08:21:32.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.08:21:32.68#ibcon#ireg 8 cls_cnt 0 2006.189.08:21:32.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:21:32.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:21:32.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:21:32.75#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:21:32.75#ibcon#first serial, iclass 4, count 0 2006.189.08:21:32.75#ibcon#enter sib2, iclass 4, count 0 2006.189.08:21:32.75#ibcon#flushed, iclass 4, count 0 2006.189.08:21:32.75#ibcon#about to write, iclass 4, count 0 2006.189.08:21:32.75#ibcon#wrote, iclass 4, count 0 2006.189.08:21:32.75#ibcon#about to read 3, iclass 4, count 0 2006.189.08:21:32.77#ibcon#read 3, iclass 4, count 0 2006.189.08:21:32.77#ibcon#about to read 4, iclass 4, count 0 2006.189.08:21:32.77#ibcon#read 4, iclass 4, count 0 2006.189.08:21:32.77#ibcon#about to read 5, iclass 4, count 0 2006.189.08:21:32.77#ibcon#read 5, iclass 4, count 0 2006.189.08:21:32.77#ibcon#about to read 6, iclass 4, count 0 2006.189.08:21:32.77#ibcon#read 6, iclass 4, count 0 2006.189.08:21:32.77#ibcon#end of sib2, iclass 4, count 0 2006.189.08:21:32.77#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:21:32.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:21:32.77#ibcon#[27=BW32\r\n] 2006.189.08:21:32.77#ibcon#*before write, iclass 4, count 0 2006.189.08:21:32.77#ibcon#enter sib2, iclass 4, count 0 2006.189.08:21:32.77#ibcon#flushed, iclass 4, count 0 2006.189.08:21:32.77#ibcon#about to write, iclass 4, count 0 2006.189.08:21:32.77#ibcon#wrote, iclass 4, count 0 2006.189.08:21:32.77#ibcon#about to read 3, iclass 4, count 0 2006.189.08:21:32.80#ibcon#read 3, iclass 4, count 0 2006.189.08:21:32.80#ibcon#about to read 4, iclass 4, count 0 2006.189.08:21:32.80#ibcon#read 4, iclass 4, count 0 2006.189.08:21:32.80#ibcon#about to read 5, iclass 4, count 0 2006.189.08:21:32.80#ibcon#read 5, iclass 4, count 0 2006.189.08:21:32.80#ibcon#about to read 6, iclass 4, count 0 2006.189.08:21:32.80#ibcon#read 6, iclass 4, count 0 2006.189.08:21:32.80#ibcon#end of sib2, iclass 4, count 0 2006.189.08:21:32.80#ibcon#*after write, iclass 4, count 0 2006.189.08:21:32.80#ibcon#*before return 0, iclass 4, count 0 2006.189.08:21:32.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:21:32.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:21:32.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:21:32.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:21:32.80$4f8m12a/ifd4f 2006.189.08:21:32.80$ifd4f/lo= 2006.189.08:21:32.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:21:32.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:21:32.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:21:32.80$ifd4f/patch= 2006.189.08:21:32.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:21:32.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:21:32.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:21:32.80$4f8m12a/"form=m,16.000,1:2 2006.189.08:21:32.80$4f8m12a/"tpicd 2006.189.08:21:32.80$4f8m12a/echo=off 2006.189.08:21:32.80$4f8m12a/xlog=off 2006.189.08:21:32.80:!2006.189.08:23:40 2006.189.08:22:02.14#trakl#Source acquired 2006.189.08:22:02.14#flagr#flagr/antenna,acquired 2006.189.08:23:40.00:preob 2006.189.08:23:40.14/onsource/TRACKING 2006.189.08:23:40.14:!2006.189.08:23:50 2006.189.08:23:50.00:data_valid=on 2006.189.08:23:50.00:midob 2006.189.08:23:50.14/onsource/TRACKING 2006.189.08:23:50.14/wx/25.29,1009.2,92 2006.189.08:23:50.21/cable/+6.4586E-03 2006.189.08:23:51.30/va/01,08,usb,yes,30,32 2006.189.08:23:51.30/va/02,07,usb,yes,30,32 2006.189.08:23:51.30/va/03,06,usb,yes,32,32 2006.189.08:23:51.30/va/04,07,usb,yes,31,33 2006.189.08:23:51.30/va/05,07,usb,yes,33,35 2006.189.08:23:51.30/va/06,06,usb,yes,32,32 2006.189.08:23:51.30/va/07,06,usb,yes,32,32 2006.189.08:23:51.30/va/08,06,usb,yes,35,34 2006.189.08:23:51.53/valo/01,532.99,yes,locked 2006.189.08:23:51.53/valo/02,572.99,yes,locked 2006.189.08:23:51.53/valo/03,672.99,yes,locked 2006.189.08:23:51.53/valo/04,832.99,yes,locked 2006.189.08:23:51.53/valo/05,652.99,yes,locked 2006.189.08:23:51.53/valo/06,772.99,yes,locked 2006.189.08:23:51.53/valo/07,832.99,yes,locked 2006.189.08:23:51.53/valo/08,852.99,yes,locked 2006.189.08:23:52.62/vb/01,04,usb,yes,29,28 2006.189.08:23:52.62/vb/02,04,usb,yes,31,32 2006.189.08:23:52.62/vb/03,04,usb,yes,27,31 2006.189.08:23:52.62/vb/04,04,usb,yes,28,28 2006.189.08:23:52.62/vb/05,04,usb,yes,34,32 2006.189.08:23:52.62/vb/06,04,usb,yes,35,38 2006.189.08:23:52.62/vb/07,04,usb,yes,36,31 2006.189.08:23:52.62/vb/08,04,usb,yes,34,31 2006.189.08:23:52.85/vblo/01,632.99,yes,locked 2006.189.08:23:52.85/vblo/02,640.99,yes,locked 2006.189.08:23:52.85/vblo/03,656.99,yes,locked 2006.189.08:23:52.85/vblo/04,712.99,yes,locked 2006.189.08:23:52.85/vblo/05,744.99,yes,locked 2006.189.08:23:52.85/vblo/06,752.99,yes,locked 2006.189.08:23:52.85/vblo/07,734.99,yes,locked 2006.189.08:23:52.85/vblo/08,744.99,yes,locked 2006.189.08:23:53.00/vabw/8 2006.189.08:23:53.15/vbbw/8 2006.189.08:23:53.24/xfe/off,on,14.5 2006.189.08:23:53.61/ifatt/23,28,28,28 2006.189.08:23:54.08/fmout-gps/S +2.99E-07 2006.189.08:23:54.16:!2006.189.08:24:50 2006.189.08:24:50.01:data_valid=off 2006.189.08:24:50.02:postob 2006.189.08:24:50.17/cable/+6.4573E-03 2006.189.08:24:50.17/wx/25.28,1009.2,92 2006.189.08:24:51.08/fmout-gps/S +2.98E-07 2006.189.08:24:51.08:scan_name=189-0825,k06189,60 2006.189.08:24:51.09:source=oj287,085448.87,200630.6,2000.0,ccw 2006.189.08:24:51.14#flagr#flagr/antenna,new-source 2006.189.08:24:52.14:checkk5 2006.189.08:24:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:24:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:24:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:24:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:24:54.04/chk_obsdata//k5ts1/T1890823??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:24:54.41/chk_obsdata//k5ts2/T1890823??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:24:54.79/chk_obsdata//k5ts3/T1890823??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:24:55.17/chk_obsdata//k5ts4/T1890823??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:24:55.87/k5log//k5ts1_log_newline 2006.189.08:24:56.58/k5log//k5ts2_log_newline 2006.189.08:24:57.28/k5log//k5ts3_log_newline 2006.189.08:24:57.98/k5log//k5ts4_log_newline 2006.189.08:24:58.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:24:58.01:4f8m12a=3 2006.189.08:24:58.01$4f8m12a/echo=on 2006.189.08:24:58.01$4f8m12a/pcalon 2006.189.08:24:58.01$pcalon/"no phase cal control is implemented here 2006.189.08:24:58.01$4f8m12a/"tpicd=stop 2006.189.08:24:58.01$4f8m12a/vc4f8 2006.189.08:24:58.01$vc4f8/valo=1,532.99 2006.189.08:24:58.01#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.08:24:58.01#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.08:24:58.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:24:58.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:24:58.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:24:58.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:24:58.01#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:24:58.01#ibcon#first serial, iclass 17, count 0 2006.189.08:24:58.01#ibcon#enter sib2, iclass 17, count 0 2006.189.08:24:58.01#ibcon#flushed, iclass 17, count 0 2006.189.08:24:58.01#ibcon#about to write, iclass 17, count 0 2006.189.08:24:58.01#ibcon#wrote, iclass 17, count 0 2006.189.08:24:58.01#ibcon#about to read 3, iclass 17, count 0 2006.189.08:24:58.06#ibcon#read 3, iclass 17, count 0 2006.189.08:24:58.06#ibcon#about to read 4, iclass 17, count 0 2006.189.08:24:58.06#ibcon#read 4, iclass 17, count 0 2006.189.08:24:58.06#ibcon#about to read 5, iclass 17, count 0 2006.189.08:24:58.06#ibcon#read 5, iclass 17, count 0 2006.189.08:24:58.06#ibcon#about to read 6, iclass 17, count 0 2006.189.08:24:58.06#ibcon#read 6, iclass 17, count 0 2006.189.08:24:58.06#ibcon#end of sib2, iclass 17, count 0 2006.189.08:24:58.06#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:24:58.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:24:58.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:24:58.06#ibcon#*before write, iclass 17, count 0 2006.189.08:24:58.06#ibcon#enter sib2, iclass 17, count 0 2006.189.08:24:58.06#ibcon#flushed, iclass 17, count 0 2006.189.08:24:58.06#ibcon#about to write, iclass 17, count 0 2006.189.08:24:58.06#ibcon#wrote, iclass 17, count 0 2006.189.08:24:58.06#ibcon#about to read 3, iclass 17, count 0 2006.189.08:24:58.11#ibcon#read 3, iclass 17, count 0 2006.189.08:24:58.11#ibcon#about to read 4, iclass 17, count 0 2006.189.08:24:58.11#ibcon#read 4, iclass 17, count 0 2006.189.08:24:58.11#ibcon#about to read 5, iclass 17, count 0 2006.189.08:24:58.11#ibcon#read 5, iclass 17, count 0 2006.189.08:24:58.11#ibcon#about to read 6, iclass 17, count 0 2006.189.08:24:58.11#ibcon#read 6, iclass 17, count 0 2006.189.08:24:58.11#ibcon#end of sib2, iclass 17, count 0 2006.189.08:24:58.11#ibcon#*after write, iclass 17, count 0 2006.189.08:24:58.11#ibcon#*before return 0, iclass 17, count 0 2006.189.08:24:58.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:24:58.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:24:58.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:24:58.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:24:58.11$vc4f8/va=1,8 2006.189.08:24:58.11#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.08:24:58.11#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.08:24:58.11#ibcon#ireg 11 cls_cnt 2 2006.189.08:24:58.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:24:58.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:24:58.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:24:58.11#ibcon#enter wrdev, iclass 19, count 2 2006.189.08:24:58.11#ibcon#first serial, iclass 19, count 2 2006.189.08:24:58.11#ibcon#enter sib2, iclass 19, count 2 2006.189.08:24:58.11#ibcon#flushed, iclass 19, count 2 2006.189.08:24:58.11#ibcon#about to write, iclass 19, count 2 2006.189.08:24:58.11#ibcon#wrote, iclass 19, count 2 2006.189.08:24:58.11#ibcon#about to read 3, iclass 19, count 2 2006.189.08:24:58.13#ibcon#read 3, iclass 19, count 2 2006.189.08:24:58.13#ibcon#about to read 4, iclass 19, count 2 2006.189.08:24:58.13#ibcon#read 4, iclass 19, count 2 2006.189.08:24:58.13#ibcon#about to read 5, iclass 19, count 2 2006.189.08:24:58.13#ibcon#read 5, iclass 19, count 2 2006.189.08:24:58.13#ibcon#about to read 6, iclass 19, count 2 2006.189.08:24:58.13#ibcon#read 6, iclass 19, count 2 2006.189.08:24:58.13#ibcon#end of sib2, iclass 19, count 2 2006.189.08:24:58.13#ibcon#*mode == 0, iclass 19, count 2 2006.189.08:24:58.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.08:24:58.13#ibcon#[25=AT01-08\r\n] 2006.189.08:24:58.13#ibcon#*before write, iclass 19, count 2 2006.189.08:24:58.13#ibcon#enter sib2, iclass 19, count 2 2006.189.08:24:58.13#ibcon#flushed, iclass 19, count 2 2006.189.08:24:58.13#ibcon#about to write, iclass 19, count 2 2006.189.08:24:58.13#ibcon#wrote, iclass 19, count 2 2006.189.08:24:58.13#ibcon#about to read 3, iclass 19, count 2 2006.189.08:24:58.16#ibcon#read 3, iclass 19, count 2 2006.189.08:24:58.16#ibcon#about to read 4, iclass 19, count 2 2006.189.08:24:58.16#ibcon#read 4, iclass 19, count 2 2006.189.08:24:58.16#ibcon#about to read 5, iclass 19, count 2 2006.189.08:24:58.16#ibcon#read 5, iclass 19, count 2 2006.189.08:24:58.16#ibcon#about to read 6, iclass 19, count 2 2006.189.08:24:58.16#ibcon#read 6, iclass 19, count 2 2006.189.08:24:58.16#ibcon#end of sib2, iclass 19, count 2 2006.189.08:24:58.16#ibcon#*after write, iclass 19, count 2 2006.189.08:24:58.16#ibcon#*before return 0, iclass 19, count 2 2006.189.08:24:58.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:24:58.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:24:58.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.08:24:58.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:24:58.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:24:58.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:24:58.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:24:58.28#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:24:58.28#ibcon#first serial, iclass 19, count 0 2006.189.08:24:58.28#ibcon#enter sib2, iclass 19, count 0 2006.189.08:24:58.28#ibcon#flushed, iclass 19, count 0 2006.189.08:24:58.28#ibcon#about to write, iclass 19, count 0 2006.189.08:24:58.28#ibcon#wrote, iclass 19, count 0 2006.189.08:24:58.28#ibcon#about to read 3, iclass 19, count 0 2006.189.08:24:58.30#ibcon#read 3, iclass 19, count 0 2006.189.08:24:58.30#ibcon#about to read 4, iclass 19, count 0 2006.189.08:24:58.30#ibcon#read 4, iclass 19, count 0 2006.189.08:24:58.30#ibcon#about to read 5, iclass 19, count 0 2006.189.08:24:58.30#ibcon#read 5, iclass 19, count 0 2006.189.08:24:58.30#ibcon#about to read 6, iclass 19, count 0 2006.189.08:24:58.30#ibcon#read 6, iclass 19, count 0 2006.189.08:24:58.30#ibcon#end of sib2, iclass 19, count 0 2006.189.08:24:58.30#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:24:58.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:24:58.30#ibcon#[25=USB\r\n] 2006.189.08:24:58.30#ibcon#*before write, iclass 19, count 0 2006.189.08:24:58.30#ibcon#enter sib2, iclass 19, count 0 2006.189.08:24:58.30#ibcon#flushed, iclass 19, count 0 2006.189.08:24:58.30#ibcon#about to write, iclass 19, count 0 2006.189.08:24:58.30#ibcon#wrote, iclass 19, count 0 2006.189.08:24:58.30#ibcon#about to read 3, iclass 19, count 0 2006.189.08:24:58.33#ibcon#read 3, iclass 19, count 0 2006.189.08:24:58.33#ibcon#about to read 4, iclass 19, count 0 2006.189.08:24:58.33#ibcon#read 4, iclass 19, count 0 2006.189.08:24:58.33#ibcon#about to read 5, iclass 19, count 0 2006.189.08:24:58.33#ibcon#read 5, iclass 19, count 0 2006.189.08:24:58.33#ibcon#about to read 6, iclass 19, count 0 2006.189.08:24:58.33#ibcon#read 6, iclass 19, count 0 2006.189.08:24:58.33#ibcon#end of sib2, iclass 19, count 0 2006.189.08:24:58.33#ibcon#*after write, iclass 19, count 0 2006.189.08:24:58.33#ibcon#*before return 0, iclass 19, count 0 2006.189.08:24:58.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:24:58.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:24:58.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:24:58.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:24:58.33$vc4f8/valo=2,572.99 2006.189.08:24:58.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.08:24:58.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.08:24:58.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:24:58.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:24:58.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:24:58.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:24:58.33#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:24:58.33#ibcon#first serial, iclass 21, count 0 2006.189.08:24:58.33#ibcon#enter sib2, iclass 21, count 0 2006.189.08:24:58.33#ibcon#flushed, iclass 21, count 0 2006.189.08:24:58.33#ibcon#about to write, iclass 21, count 0 2006.189.08:24:58.33#ibcon#wrote, iclass 21, count 0 2006.189.08:24:58.33#ibcon#about to read 3, iclass 21, count 0 2006.189.08:24:58.35#ibcon#read 3, iclass 21, count 0 2006.189.08:24:58.35#ibcon#about to read 4, iclass 21, count 0 2006.189.08:24:58.35#ibcon#read 4, iclass 21, count 0 2006.189.08:24:58.35#ibcon#about to read 5, iclass 21, count 0 2006.189.08:24:58.35#ibcon#read 5, iclass 21, count 0 2006.189.08:24:58.35#ibcon#about to read 6, iclass 21, count 0 2006.189.08:24:58.35#ibcon#read 6, iclass 21, count 0 2006.189.08:24:58.35#ibcon#end of sib2, iclass 21, count 0 2006.189.08:24:58.35#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:24:58.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:24:58.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:24:58.35#ibcon#*before write, iclass 21, count 0 2006.189.08:24:58.35#ibcon#enter sib2, iclass 21, count 0 2006.189.08:24:58.35#ibcon#flushed, iclass 21, count 0 2006.189.08:24:58.35#ibcon#about to write, iclass 21, count 0 2006.189.08:24:58.35#ibcon#wrote, iclass 21, count 0 2006.189.08:24:58.35#ibcon#about to read 3, iclass 21, count 0 2006.189.08:24:58.39#ibcon#read 3, iclass 21, count 0 2006.189.08:24:58.39#ibcon#about to read 4, iclass 21, count 0 2006.189.08:24:58.39#ibcon#read 4, iclass 21, count 0 2006.189.08:24:58.39#ibcon#about to read 5, iclass 21, count 0 2006.189.08:24:58.39#ibcon#read 5, iclass 21, count 0 2006.189.08:24:58.39#ibcon#about to read 6, iclass 21, count 0 2006.189.08:24:58.39#ibcon#read 6, iclass 21, count 0 2006.189.08:24:58.39#ibcon#end of sib2, iclass 21, count 0 2006.189.08:24:58.39#ibcon#*after write, iclass 21, count 0 2006.189.08:24:58.39#ibcon#*before return 0, iclass 21, count 0 2006.189.08:24:58.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:24:58.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:24:58.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:24:58.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:24:58.39$vc4f8/va=2,7 2006.189.08:24:58.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.08:24:58.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.08:24:58.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:24:58.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:24:58.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:24:58.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:24:58.45#ibcon#enter wrdev, iclass 23, count 2 2006.189.08:24:58.45#ibcon#first serial, iclass 23, count 2 2006.189.08:24:58.45#ibcon#enter sib2, iclass 23, count 2 2006.189.08:24:58.45#ibcon#flushed, iclass 23, count 2 2006.189.08:24:58.45#ibcon#about to write, iclass 23, count 2 2006.189.08:24:58.45#ibcon#wrote, iclass 23, count 2 2006.189.08:24:58.45#ibcon#about to read 3, iclass 23, count 2 2006.189.08:24:58.47#ibcon#read 3, iclass 23, count 2 2006.189.08:24:58.47#ibcon#about to read 4, iclass 23, count 2 2006.189.08:24:58.47#ibcon#read 4, iclass 23, count 2 2006.189.08:24:58.47#ibcon#about to read 5, iclass 23, count 2 2006.189.08:24:58.47#ibcon#read 5, iclass 23, count 2 2006.189.08:24:58.47#ibcon#about to read 6, iclass 23, count 2 2006.189.08:24:58.47#ibcon#read 6, iclass 23, count 2 2006.189.08:24:58.47#ibcon#end of sib2, iclass 23, count 2 2006.189.08:24:58.47#ibcon#*mode == 0, iclass 23, count 2 2006.189.08:24:58.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.08:24:58.47#ibcon#[25=AT02-07\r\n] 2006.189.08:24:58.47#ibcon#*before write, iclass 23, count 2 2006.189.08:24:58.47#ibcon#enter sib2, iclass 23, count 2 2006.189.08:24:58.47#ibcon#flushed, iclass 23, count 2 2006.189.08:24:58.47#ibcon#about to write, iclass 23, count 2 2006.189.08:24:58.47#ibcon#wrote, iclass 23, count 2 2006.189.08:24:58.47#ibcon#about to read 3, iclass 23, count 2 2006.189.08:24:58.50#ibcon#read 3, iclass 23, count 2 2006.189.08:24:58.50#ibcon#about to read 4, iclass 23, count 2 2006.189.08:24:58.50#ibcon#read 4, iclass 23, count 2 2006.189.08:24:58.50#ibcon#about to read 5, iclass 23, count 2 2006.189.08:24:58.50#ibcon#read 5, iclass 23, count 2 2006.189.08:24:58.50#ibcon#about to read 6, iclass 23, count 2 2006.189.08:24:58.50#ibcon#read 6, iclass 23, count 2 2006.189.08:24:58.50#ibcon#end of sib2, iclass 23, count 2 2006.189.08:24:58.50#ibcon#*after write, iclass 23, count 2 2006.189.08:24:58.50#ibcon#*before return 0, iclass 23, count 2 2006.189.08:24:58.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:24:58.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:24:58.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.08:24:58.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:24:58.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:24:58.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:24:58.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:24:58.62#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:24:58.62#ibcon#first serial, iclass 23, count 0 2006.189.08:24:58.62#ibcon#enter sib2, iclass 23, count 0 2006.189.08:24:58.62#ibcon#flushed, iclass 23, count 0 2006.189.08:24:58.62#ibcon#about to write, iclass 23, count 0 2006.189.08:24:58.62#ibcon#wrote, iclass 23, count 0 2006.189.08:24:58.62#ibcon#about to read 3, iclass 23, count 0 2006.189.08:24:58.64#ibcon#read 3, iclass 23, count 0 2006.189.08:24:58.64#ibcon#about to read 4, iclass 23, count 0 2006.189.08:24:58.64#ibcon#read 4, iclass 23, count 0 2006.189.08:24:58.64#ibcon#about to read 5, iclass 23, count 0 2006.189.08:24:58.64#ibcon#read 5, iclass 23, count 0 2006.189.08:24:58.64#ibcon#about to read 6, iclass 23, count 0 2006.189.08:24:58.64#ibcon#read 6, iclass 23, count 0 2006.189.08:24:58.64#ibcon#end of sib2, iclass 23, count 0 2006.189.08:24:58.64#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:24:58.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:24:58.64#ibcon#[25=USB\r\n] 2006.189.08:24:58.64#ibcon#*before write, iclass 23, count 0 2006.189.08:24:58.64#ibcon#enter sib2, iclass 23, count 0 2006.189.08:24:58.64#ibcon#flushed, iclass 23, count 0 2006.189.08:24:58.64#ibcon#about to write, iclass 23, count 0 2006.189.08:24:58.64#ibcon#wrote, iclass 23, count 0 2006.189.08:24:58.64#ibcon#about to read 3, iclass 23, count 0 2006.189.08:24:58.67#ibcon#read 3, iclass 23, count 0 2006.189.08:24:58.67#ibcon#about to read 4, iclass 23, count 0 2006.189.08:24:58.67#ibcon#read 4, iclass 23, count 0 2006.189.08:24:58.67#ibcon#about to read 5, iclass 23, count 0 2006.189.08:24:58.67#ibcon#read 5, iclass 23, count 0 2006.189.08:24:58.67#ibcon#about to read 6, iclass 23, count 0 2006.189.08:24:58.67#ibcon#read 6, iclass 23, count 0 2006.189.08:24:58.67#ibcon#end of sib2, iclass 23, count 0 2006.189.08:24:58.67#ibcon#*after write, iclass 23, count 0 2006.189.08:24:58.67#ibcon#*before return 0, iclass 23, count 0 2006.189.08:24:58.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:24:58.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:24:58.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:24:58.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:24:58.67$vc4f8/valo=3,672.99 2006.189.08:24:58.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.08:24:58.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.08:24:58.67#ibcon#ireg 17 cls_cnt 0 2006.189.08:24:58.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:24:58.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:24:58.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:24:58.67#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:24:58.67#ibcon#first serial, iclass 25, count 0 2006.189.08:24:58.67#ibcon#enter sib2, iclass 25, count 0 2006.189.08:24:58.67#ibcon#flushed, iclass 25, count 0 2006.189.08:24:58.67#ibcon#about to write, iclass 25, count 0 2006.189.08:24:58.67#ibcon#wrote, iclass 25, count 0 2006.189.08:24:58.67#ibcon#about to read 3, iclass 25, count 0 2006.189.08:24:58.69#ibcon#read 3, iclass 25, count 0 2006.189.08:24:58.69#ibcon#about to read 4, iclass 25, count 0 2006.189.08:24:58.69#ibcon#read 4, iclass 25, count 0 2006.189.08:24:58.69#ibcon#about to read 5, iclass 25, count 0 2006.189.08:24:58.69#ibcon#read 5, iclass 25, count 0 2006.189.08:24:58.69#ibcon#about to read 6, iclass 25, count 0 2006.189.08:24:58.69#ibcon#read 6, iclass 25, count 0 2006.189.08:24:58.69#ibcon#end of sib2, iclass 25, count 0 2006.189.08:24:58.69#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:24:58.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:24:58.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:24:58.69#ibcon#*before write, iclass 25, count 0 2006.189.08:24:58.69#ibcon#enter sib2, iclass 25, count 0 2006.189.08:24:58.69#ibcon#flushed, iclass 25, count 0 2006.189.08:24:58.69#ibcon#about to write, iclass 25, count 0 2006.189.08:24:58.69#ibcon#wrote, iclass 25, count 0 2006.189.08:24:58.69#ibcon#about to read 3, iclass 25, count 0 2006.189.08:24:58.73#ibcon#read 3, iclass 25, count 0 2006.189.08:24:58.73#ibcon#about to read 4, iclass 25, count 0 2006.189.08:24:58.73#ibcon#read 4, iclass 25, count 0 2006.189.08:24:58.73#ibcon#about to read 5, iclass 25, count 0 2006.189.08:24:58.73#ibcon#read 5, iclass 25, count 0 2006.189.08:24:58.73#ibcon#about to read 6, iclass 25, count 0 2006.189.08:24:58.73#ibcon#read 6, iclass 25, count 0 2006.189.08:24:58.73#ibcon#end of sib2, iclass 25, count 0 2006.189.08:24:58.73#ibcon#*after write, iclass 25, count 0 2006.189.08:24:58.73#ibcon#*before return 0, iclass 25, count 0 2006.189.08:24:58.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:24:58.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:24:58.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:24:58.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:24:58.73$vc4f8/va=3,6 2006.189.08:24:58.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.08:24:58.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.08:24:58.73#ibcon#ireg 11 cls_cnt 2 2006.189.08:24:58.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:24:58.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:24:58.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:24:58.79#ibcon#enter wrdev, iclass 27, count 2 2006.189.08:24:58.79#ibcon#first serial, iclass 27, count 2 2006.189.08:24:58.79#ibcon#enter sib2, iclass 27, count 2 2006.189.08:24:58.79#ibcon#flushed, iclass 27, count 2 2006.189.08:24:58.79#ibcon#about to write, iclass 27, count 2 2006.189.08:24:58.79#ibcon#wrote, iclass 27, count 2 2006.189.08:24:58.79#ibcon#about to read 3, iclass 27, count 2 2006.189.08:24:58.81#ibcon#read 3, iclass 27, count 2 2006.189.08:24:58.81#ibcon#about to read 4, iclass 27, count 2 2006.189.08:24:58.81#ibcon#read 4, iclass 27, count 2 2006.189.08:24:58.81#ibcon#about to read 5, iclass 27, count 2 2006.189.08:24:58.81#ibcon#read 5, iclass 27, count 2 2006.189.08:24:58.81#ibcon#about to read 6, iclass 27, count 2 2006.189.08:24:58.81#ibcon#read 6, iclass 27, count 2 2006.189.08:24:58.81#ibcon#end of sib2, iclass 27, count 2 2006.189.08:24:58.81#ibcon#*mode == 0, iclass 27, count 2 2006.189.08:24:58.81#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.08:24:58.81#ibcon#[25=AT03-06\r\n] 2006.189.08:24:58.81#ibcon#*before write, iclass 27, count 2 2006.189.08:24:58.81#ibcon#enter sib2, iclass 27, count 2 2006.189.08:24:58.81#ibcon#flushed, iclass 27, count 2 2006.189.08:24:58.81#ibcon#about to write, iclass 27, count 2 2006.189.08:24:58.81#ibcon#wrote, iclass 27, count 2 2006.189.08:24:58.81#ibcon#about to read 3, iclass 27, count 2 2006.189.08:24:58.84#ibcon#read 3, iclass 27, count 2 2006.189.08:24:58.84#ibcon#about to read 4, iclass 27, count 2 2006.189.08:24:58.84#ibcon#read 4, iclass 27, count 2 2006.189.08:24:58.84#ibcon#about to read 5, iclass 27, count 2 2006.189.08:24:58.84#ibcon#read 5, iclass 27, count 2 2006.189.08:24:58.84#ibcon#about to read 6, iclass 27, count 2 2006.189.08:24:58.84#ibcon#read 6, iclass 27, count 2 2006.189.08:24:58.84#ibcon#end of sib2, iclass 27, count 2 2006.189.08:24:58.84#ibcon#*after write, iclass 27, count 2 2006.189.08:24:58.84#ibcon#*before return 0, iclass 27, count 2 2006.189.08:24:58.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:24:58.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:24:58.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.08:24:58.84#ibcon#ireg 7 cls_cnt 0 2006.189.08:24:58.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:24:58.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:24:58.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:24:58.96#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:24:58.96#ibcon#first serial, iclass 27, count 0 2006.189.08:24:58.96#ibcon#enter sib2, iclass 27, count 0 2006.189.08:24:58.96#ibcon#flushed, iclass 27, count 0 2006.189.08:24:58.96#ibcon#about to write, iclass 27, count 0 2006.189.08:24:58.96#ibcon#wrote, iclass 27, count 0 2006.189.08:24:58.96#ibcon#about to read 3, iclass 27, count 0 2006.189.08:24:58.98#ibcon#read 3, iclass 27, count 0 2006.189.08:24:58.98#ibcon#about to read 4, iclass 27, count 0 2006.189.08:24:58.98#ibcon#read 4, iclass 27, count 0 2006.189.08:24:58.98#ibcon#about to read 5, iclass 27, count 0 2006.189.08:24:58.98#ibcon#read 5, iclass 27, count 0 2006.189.08:24:58.98#ibcon#about to read 6, iclass 27, count 0 2006.189.08:24:58.98#ibcon#read 6, iclass 27, count 0 2006.189.08:24:58.98#ibcon#end of sib2, iclass 27, count 0 2006.189.08:24:58.98#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:24:58.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:24:58.98#ibcon#[25=USB\r\n] 2006.189.08:24:58.98#ibcon#*before write, iclass 27, count 0 2006.189.08:24:58.98#ibcon#enter sib2, iclass 27, count 0 2006.189.08:24:58.98#ibcon#flushed, iclass 27, count 0 2006.189.08:24:58.98#ibcon#about to write, iclass 27, count 0 2006.189.08:24:58.98#ibcon#wrote, iclass 27, count 0 2006.189.08:24:58.98#ibcon#about to read 3, iclass 27, count 0 2006.189.08:24:59.01#ibcon#read 3, iclass 27, count 0 2006.189.08:24:59.01#ibcon#about to read 4, iclass 27, count 0 2006.189.08:24:59.01#ibcon#read 4, iclass 27, count 0 2006.189.08:24:59.01#ibcon#about to read 5, iclass 27, count 0 2006.189.08:24:59.01#ibcon#read 5, iclass 27, count 0 2006.189.08:24:59.01#ibcon#about to read 6, iclass 27, count 0 2006.189.08:24:59.01#ibcon#read 6, iclass 27, count 0 2006.189.08:24:59.01#ibcon#end of sib2, iclass 27, count 0 2006.189.08:24:59.01#ibcon#*after write, iclass 27, count 0 2006.189.08:24:59.01#ibcon#*before return 0, iclass 27, count 0 2006.189.08:24:59.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:24:59.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:24:59.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:24:59.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:24:59.01$vc4f8/valo=4,832.99 2006.189.08:24:59.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.08:24:59.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.08:24:59.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:24:59.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:24:59.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:24:59.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:24:59.01#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:24:59.01#ibcon#first serial, iclass 29, count 0 2006.189.08:24:59.01#ibcon#enter sib2, iclass 29, count 0 2006.189.08:24:59.01#ibcon#flushed, iclass 29, count 0 2006.189.08:24:59.01#ibcon#about to write, iclass 29, count 0 2006.189.08:24:59.01#ibcon#wrote, iclass 29, count 0 2006.189.08:24:59.01#ibcon#about to read 3, iclass 29, count 0 2006.189.08:24:59.03#ibcon#read 3, iclass 29, count 0 2006.189.08:24:59.03#ibcon#about to read 4, iclass 29, count 0 2006.189.08:24:59.03#ibcon#read 4, iclass 29, count 0 2006.189.08:24:59.03#ibcon#about to read 5, iclass 29, count 0 2006.189.08:24:59.03#ibcon#read 5, iclass 29, count 0 2006.189.08:24:59.03#ibcon#about to read 6, iclass 29, count 0 2006.189.08:24:59.03#ibcon#read 6, iclass 29, count 0 2006.189.08:24:59.03#ibcon#end of sib2, iclass 29, count 0 2006.189.08:24:59.03#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:24:59.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:24:59.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:24:59.03#ibcon#*before write, iclass 29, count 0 2006.189.08:24:59.03#ibcon#enter sib2, iclass 29, count 0 2006.189.08:24:59.03#ibcon#flushed, iclass 29, count 0 2006.189.08:24:59.03#ibcon#about to write, iclass 29, count 0 2006.189.08:24:59.03#ibcon#wrote, iclass 29, count 0 2006.189.08:24:59.03#ibcon#about to read 3, iclass 29, count 0 2006.189.08:24:59.07#ibcon#read 3, iclass 29, count 0 2006.189.08:24:59.07#ibcon#about to read 4, iclass 29, count 0 2006.189.08:24:59.07#ibcon#read 4, iclass 29, count 0 2006.189.08:24:59.07#ibcon#about to read 5, iclass 29, count 0 2006.189.08:24:59.07#ibcon#read 5, iclass 29, count 0 2006.189.08:24:59.07#ibcon#about to read 6, iclass 29, count 0 2006.189.08:24:59.07#ibcon#read 6, iclass 29, count 0 2006.189.08:24:59.07#ibcon#end of sib2, iclass 29, count 0 2006.189.08:24:59.07#ibcon#*after write, iclass 29, count 0 2006.189.08:24:59.07#ibcon#*before return 0, iclass 29, count 0 2006.189.08:24:59.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:24:59.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:24:59.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:24:59.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:24:59.07$vc4f8/va=4,7 2006.189.08:24:59.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.08:24:59.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.08:24:59.07#ibcon#ireg 11 cls_cnt 2 2006.189.08:24:59.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:24:59.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:24:59.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:24:59.13#ibcon#enter wrdev, iclass 31, count 2 2006.189.08:24:59.13#ibcon#first serial, iclass 31, count 2 2006.189.08:24:59.13#ibcon#enter sib2, iclass 31, count 2 2006.189.08:24:59.13#ibcon#flushed, iclass 31, count 2 2006.189.08:24:59.13#ibcon#about to write, iclass 31, count 2 2006.189.08:24:59.13#ibcon#wrote, iclass 31, count 2 2006.189.08:24:59.13#ibcon#about to read 3, iclass 31, count 2 2006.189.08:24:59.15#ibcon#read 3, iclass 31, count 2 2006.189.08:24:59.15#ibcon#about to read 4, iclass 31, count 2 2006.189.08:24:59.15#ibcon#read 4, iclass 31, count 2 2006.189.08:24:59.15#ibcon#about to read 5, iclass 31, count 2 2006.189.08:24:59.15#ibcon#read 5, iclass 31, count 2 2006.189.08:24:59.15#ibcon#about to read 6, iclass 31, count 2 2006.189.08:24:59.15#ibcon#read 6, iclass 31, count 2 2006.189.08:24:59.15#ibcon#end of sib2, iclass 31, count 2 2006.189.08:24:59.15#ibcon#*mode == 0, iclass 31, count 2 2006.189.08:24:59.15#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.08:24:59.15#ibcon#[25=AT04-07\r\n] 2006.189.08:24:59.15#ibcon#*before write, iclass 31, count 2 2006.189.08:24:59.15#ibcon#enter sib2, iclass 31, count 2 2006.189.08:24:59.15#ibcon#flushed, iclass 31, count 2 2006.189.08:24:59.15#ibcon#about to write, iclass 31, count 2 2006.189.08:24:59.15#ibcon#wrote, iclass 31, count 2 2006.189.08:24:59.15#ibcon#about to read 3, iclass 31, count 2 2006.189.08:24:59.18#ibcon#read 3, iclass 31, count 2 2006.189.08:24:59.18#ibcon#about to read 4, iclass 31, count 2 2006.189.08:24:59.18#ibcon#read 4, iclass 31, count 2 2006.189.08:24:59.18#ibcon#about to read 5, iclass 31, count 2 2006.189.08:24:59.18#ibcon#read 5, iclass 31, count 2 2006.189.08:24:59.18#ibcon#about to read 6, iclass 31, count 2 2006.189.08:24:59.18#ibcon#read 6, iclass 31, count 2 2006.189.08:24:59.18#ibcon#end of sib2, iclass 31, count 2 2006.189.08:24:59.18#ibcon#*after write, iclass 31, count 2 2006.189.08:24:59.18#ibcon#*before return 0, iclass 31, count 2 2006.189.08:24:59.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:24:59.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:24:59.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.08:24:59.18#ibcon#ireg 7 cls_cnt 0 2006.189.08:24:59.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:24:59.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:24:59.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:24:59.30#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:24:59.30#ibcon#first serial, iclass 31, count 0 2006.189.08:24:59.30#ibcon#enter sib2, iclass 31, count 0 2006.189.08:24:59.30#ibcon#flushed, iclass 31, count 0 2006.189.08:24:59.30#ibcon#about to write, iclass 31, count 0 2006.189.08:24:59.30#ibcon#wrote, iclass 31, count 0 2006.189.08:24:59.30#ibcon#about to read 3, iclass 31, count 0 2006.189.08:24:59.32#ibcon#read 3, iclass 31, count 0 2006.189.08:24:59.32#ibcon#about to read 4, iclass 31, count 0 2006.189.08:24:59.32#ibcon#read 4, iclass 31, count 0 2006.189.08:24:59.32#ibcon#about to read 5, iclass 31, count 0 2006.189.08:24:59.32#ibcon#read 5, iclass 31, count 0 2006.189.08:24:59.32#ibcon#about to read 6, iclass 31, count 0 2006.189.08:24:59.32#ibcon#read 6, iclass 31, count 0 2006.189.08:24:59.32#ibcon#end of sib2, iclass 31, count 0 2006.189.08:24:59.32#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:24:59.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:24:59.32#ibcon#[25=USB\r\n] 2006.189.08:24:59.32#ibcon#*before write, iclass 31, count 0 2006.189.08:24:59.32#ibcon#enter sib2, iclass 31, count 0 2006.189.08:24:59.32#ibcon#flushed, iclass 31, count 0 2006.189.08:24:59.32#ibcon#about to write, iclass 31, count 0 2006.189.08:24:59.32#ibcon#wrote, iclass 31, count 0 2006.189.08:24:59.32#ibcon#about to read 3, iclass 31, count 0 2006.189.08:24:59.35#ibcon#read 3, iclass 31, count 0 2006.189.08:24:59.35#ibcon#about to read 4, iclass 31, count 0 2006.189.08:24:59.35#ibcon#read 4, iclass 31, count 0 2006.189.08:24:59.35#ibcon#about to read 5, iclass 31, count 0 2006.189.08:24:59.35#ibcon#read 5, iclass 31, count 0 2006.189.08:24:59.35#ibcon#about to read 6, iclass 31, count 0 2006.189.08:24:59.35#ibcon#read 6, iclass 31, count 0 2006.189.08:24:59.35#ibcon#end of sib2, iclass 31, count 0 2006.189.08:24:59.35#ibcon#*after write, iclass 31, count 0 2006.189.08:24:59.35#ibcon#*before return 0, iclass 31, count 0 2006.189.08:24:59.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:24:59.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:24:59.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:24:59.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:24:59.35$vc4f8/valo=5,652.99 2006.189.08:24:59.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.08:24:59.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.08:24:59.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:24:59.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:24:59.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:24:59.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:24:59.35#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:24:59.35#ibcon#first serial, iclass 33, count 0 2006.189.08:24:59.35#ibcon#enter sib2, iclass 33, count 0 2006.189.08:24:59.35#ibcon#flushed, iclass 33, count 0 2006.189.08:24:59.35#ibcon#about to write, iclass 33, count 0 2006.189.08:24:59.35#ibcon#wrote, iclass 33, count 0 2006.189.08:24:59.35#ibcon#about to read 3, iclass 33, count 0 2006.189.08:24:59.37#ibcon#read 3, iclass 33, count 0 2006.189.08:24:59.37#ibcon#about to read 4, iclass 33, count 0 2006.189.08:24:59.37#ibcon#read 4, iclass 33, count 0 2006.189.08:24:59.37#ibcon#about to read 5, iclass 33, count 0 2006.189.08:24:59.37#ibcon#read 5, iclass 33, count 0 2006.189.08:24:59.37#ibcon#about to read 6, iclass 33, count 0 2006.189.08:24:59.37#ibcon#read 6, iclass 33, count 0 2006.189.08:24:59.37#ibcon#end of sib2, iclass 33, count 0 2006.189.08:24:59.37#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:24:59.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:24:59.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:24:59.37#ibcon#*before write, iclass 33, count 0 2006.189.08:24:59.37#ibcon#enter sib2, iclass 33, count 0 2006.189.08:24:59.37#ibcon#flushed, iclass 33, count 0 2006.189.08:24:59.37#ibcon#about to write, iclass 33, count 0 2006.189.08:24:59.37#ibcon#wrote, iclass 33, count 0 2006.189.08:24:59.37#ibcon#about to read 3, iclass 33, count 0 2006.189.08:24:59.41#ibcon#read 3, iclass 33, count 0 2006.189.08:24:59.41#ibcon#about to read 4, iclass 33, count 0 2006.189.08:24:59.41#ibcon#read 4, iclass 33, count 0 2006.189.08:24:59.41#ibcon#about to read 5, iclass 33, count 0 2006.189.08:24:59.41#ibcon#read 5, iclass 33, count 0 2006.189.08:24:59.41#ibcon#about to read 6, iclass 33, count 0 2006.189.08:24:59.41#ibcon#read 6, iclass 33, count 0 2006.189.08:24:59.41#ibcon#end of sib2, iclass 33, count 0 2006.189.08:24:59.41#ibcon#*after write, iclass 33, count 0 2006.189.08:24:59.41#ibcon#*before return 0, iclass 33, count 0 2006.189.08:24:59.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:24:59.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:24:59.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:24:59.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:24:59.41$vc4f8/va=5,7 2006.189.08:24:59.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.08:24:59.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.08:24:59.41#ibcon#ireg 11 cls_cnt 2 2006.189.08:24:59.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:24:59.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:24:59.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:24:59.47#ibcon#enter wrdev, iclass 35, count 2 2006.189.08:24:59.47#ibcon#first serial, iclass 35, count 2 2006.189.08:24:59.47#ibcon#enter sib2, iclass 35, count 2 2006.189.08:24:59.47#ibcon#flushed, iclass 35, count 2 2006.189.08:24:59.47#ibcon#about to write, iclass 35, count 2 2006.189.08:24:59.47#ibcon#wrote, iclass 35, count 2 2006.189.08:24:59.47#ibcon#about to read 3, iclass 35, count 2 2006.189.08:24:59.49#ibcon#read 3, iclass 35, count 2 2006.189.08:24:59.49#ibcon#about to read 4, iclass 35, count 2 2006.189.08:24:59.49#ibcon#read 4, iclass 35, count 2 2006.189.08:24:59.49#ibcon#about to read 5, iclass 35, count 2 2006.189.08:24:59.49#ibcon#read 5, iclass 35, count 2 2006.189.08:24:59.49#ibcon#about to read 6, iclass 35, count 2 2006.189.08:24:59.49#ibcon#read 6, iclass 35, count 2 2006.189.08:24:59.49#ibcon#end of sib2, iclass 35, count 2 2006.189.08:24:59.49#ibcon#*mode == 0, iclass 35, count 2 2006.189.08:24:59.49#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.08:24:59.49#ibcon#[25=AT05-07\r\n] 2006.189.08:24:59.49#ibcon#*before write, iclass 35, count 2 2006.189.08:24:59.49#ibcon#enter sib2, iclass 35, count 2 2006.189.08:24:59.49#ibcon#flushed, iclass 35, count 2 2006.189.08:24:59.49#ibcon#about to write, iclass 35, count 2 2006.189.08:24:59.49#ibcon#wrote, iclass 35, count 2 2006.189.08:24:59.49#ibcon#about to read 3, iclass 35, count 2 2006.189.08:24:59.52#ibcon#read 3, iclass 35, count 2 2006.189.08:24:59.52#ibcon#about to read 4, iclass 35, count 2 2006.189.08:24:59.52#ibcon#read 4, iclass 35, count 2 2006.189.08:24:59.52#ibcon#about to read 5, iclass 35, count 2 2006.189.08:24:59.52#ibcon#read 5, iclass 35, count 2 2006.189.08:24:59.52#ibcon#about to read 6, iclass 35, count 2 2006.189.08:24:59.52#ibcon#read 6, iclass 35, count 2 2006.189.08:24:59.52#ibcon#end of sib2, iclass 35, count 2 2006.189.08:24:59.52#ibcon#*after write, iclass 35, count 2 2006.189.08:24:59.52#ibcon#*before return 0, iclass 35, count 2 2006.189.08:24:59.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:24:59.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:24:59.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.08:24:59.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:24:59.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:24:59.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:24:59.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:24:59.64#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:24:59.64#ibcon#first serial, iclass 35, count 0 2006.189.08:24:59.64#ibcon#enter sib2, iclass 35, count 0 2006.189.08:24:59.64#ibcon#flushed, iclass 35, count 0 2006.189.08:24:59.64#ibcon#about to write, iclass 35, count 0 2006.189.08:24:59.64#ibcon#wrote, iclass 35, count 0 2006.189.08:24:59.64#ibcon#about to read 3, iclass 35, count 0 2006.189.08:24:59.66#ibcon#read 3, iclass 35, count 0 2006.189.08:24:59.66#ibcon#about to read 4, iclass 35, count 0 2006.189.08:24:59.66#ibcon#read 4, iclass 35, count 0 2006.189.08:24:59.66#ibcon#about to read 5, iclass 35, count 0 2006.189.08:24:59.66#ibcon#read 5, iclass 35, count 0 2006.189.08:24:59.66#ibcon#about to read 6, iclass 35, count 0 2006.189.08:24:59.66#ibcon#read 6, iclass 35, count 0 2006.189.08:24:59.66#ibcon#end of sib2, iclass 35, count 0 2006.189.08:24:59.66#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:24:59.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:24:59.66#ibcon#[25=USB\r\n] 2006.189.08:24:59.66#ibcon#*before write, iclass 35, count 0 2006.189.08:24:59.66#ibcon#enter sib2, iclass 35, count 0 2006.189.08:24:59.66#ibcon#flushed, iclass 35, count 0 2006.189.08:24:59.66#ibcon#about to write, iclass 35, count 0 2006.189.08:24:59.66#ibcon#wrote, iclass 35, count 0 2006.189.08:24:59.66#ibcon#about to read 3, iclass 35, count 0 2006.189.08:24:59.69#ibcon#read 3, iclass 35, count 0 2006.189.08:24:59.69#ibcon#about to read 4, iclass 35, count 0 2006.189.08:24:59.69#ibcon#read 4, iclass 35, count 0 2006.189.08:24:59.69#ibcon#about to read 5, iclass 35, count 0 2006.189.08:24:59.69#ibcon#read 5, iclass 35, count 0 2006.189.08:24:59.69#ibcon#about to read 6, iclass 35, count 0 2006.189.08:24:59.69#ibcon#read 6, iclass 35, count 0 2006.189.08:24:59.69#ibcon#end of sib2, iclass 35, count 0 2006.189.08:24:59.69#ibcon#*after write, iclass 35, count 0 2006.189.08:24:59.69#ibcon#*before return 0, iclass 35, count 0 2006.189.08:24:59.69#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:24:59.69#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:24:59.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:24:59.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:24:59.69$vc4f8/valo=6,772.99 2006.189.08:24:59.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.08:24:59.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.08:24:59.69#ibcon#ireg 17 cls_cnt 0 2006.189.08:24:59.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:24:59.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:24:59.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:24:59.69#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:24:59.69#ibcon#first serial, iclass 37, count 0 2006.189.08:24:59.69#ibcon#enter sib2, iclass 37, count 0 2006.189.08:24:59.69#ibcon#flushed, iclass 37, count 0 2006.189.08:24:59.69#ibcon#about to write, iclass 37, count 0 2006.189.08:24:59.69#ibcon#wrote, iclass 37, count 0 2006.189.08:24:59.69#ibcon#about to read 3, iclass 37, count 0 2006.189.08:24:59.71#ibcon#read 3, iclass 37, count 0 2006.189.08:24:59.71#ibcon#about to read 4, iclass 37, count 0 2006.189.08:24:59.71#ibcon#read 4, iclass 37, count 0 2006.189.08:24:59.71#ibcon#about to read 5, iclass 37, count 0 2006.189.08:24:59.71#ibcon#read 5, iclass 37, count 0 2006.189.08:24:59.71#ibcon#about to read 6, iclass 37, count 0 2006.189.08:24:59.71#ibcon#read 6, iclass 37, count 0 2006.189.08:24:59.71#ibcon#end of sib2, iclass 37, count 0 2006.189.08:24:59.71#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:24:59.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:24:59.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:24:59.71#ibcon#*before write, iclass 37, count 0 2006.189.08:24:59.71#ibcon#enter sib2, iclass 37, count 0 2006.189.08:24:59.71#ibcon#flushed, iclass 37, count 0 2006.189.08:24:59.71#ibcon#about to write, iclass 37, count 0 2006.189.08:24:59.71#ibcon#wrote, iclass 37, count 0 2006.189.08:24:59.71#ibcon#about to read 3, iclass 37, count 0 2006.189.08:24:59.75#ibcon#read 3, iclass 37, count 0 2006.189.08:24:59.75#ibcon#about to read 4, iclass 37, count 0 2006.189.08:24:59.75#ibcon#read 4, iclass 37, count 0 2006.189.08:24:59.75#ibcon#about to read 5, iclass 37, count 0 2006.189.08:24:59.75#ibcon#read 5, iclass 37, count 0 2006.189.08:24:59.75#ibcon#about to read 6, iclass 37, count 0 2006.189.08:24:59.75#ibcon#read 6, iclass 37, count 0 2006.189.08:24:59.75#ibcon#end of sib2, iclass 37, count 0 2006.189.08:24:59.75#ibcon#*after write, iclass 37, count 0 2006.189.08:24:59.75#ibcon#*before return 0, iclass 37, count 0 2006.189.08:24:59.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:24:59.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:24:59.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:24:59.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:24:59.75$vc4f8/va=6,6 2006.189.08:24:59.75#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.189.08:24:59.75#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.189.08:24:59.75#ibcon#ireg 11 cls_cnt 2 2006.189.08:24:59.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:24:59.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:24:59.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:24:59.81#ibcon#enter wrdev, iclass 39, count 2 2006.189.08:24:59.81#ibcon#first serial, iclass 39, count 2 2006.189.08:24:59.81#ibcon#enter sib2, iclass 39, count 2 2006.189.08:24:59.81#ibcon#flushed, iclass 39, count 2 2006.189.08:24:59.81#ibcon#about to write, iclass 39, count 2 2006.189.08:24:59.81#ibcon#wrote, iclass 39, count 2 2006.189.08:24:59.81#ibcon#about to read 3, iclass 39, count 2 2006.189.08:24:59.83#ibcon#read 3, iclass 39, count 2 2006.189.08:24:59.83#ibcon#about to read 4, iclass 39, count 2 2006.189.08:24:59.83#ibcon#read 4, iclass 39, count 2 2006.189.08:24:59.83#ibcon#about to read 5, iclass 39, count 2 2006.189.08:24:59.83#ibcon#read 5, iclass 39, count 2 2006.189.08:24:59.83#ibcon#about to read 6, iclass 39, count 2 2006.189.08:24:59.83#ibcon#read 6, iclass 39, count 2 2006.189.08:24:59.83#ibcon#end of sib2, iclass 39, count 2 2006.189.08:24:59.83#ibcon#*mode == 0, iclass 39, count 2 2006.189.08:24:59.83#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.189.08:24:59.83#ibcon#[25=AT06-06\r\n] 2006.189.08:24:59.83#ibcon#*before write, iclass 39, count 2 2006.189.08:24:59.83#ibcon#enter sib2, iclass 39, count 2 2006.189.08:24:59.83#ibcon#flushed, iclass 39, count 2 2006.189.08:24:59.83#ibcon#about to write, iclass 39, count 2 2006.189.08:24:59.83#ibcon#wrote, iclass 39, count 2 2006.189.08:24:59.83#ibcon#about to read 3, iclass 39, count 2 2006.189.08:24:59.86#ibcon#read 3, iclass 39, count 2 2006.189.08:24:59.86#ibcon#about to read 4, iclass 39, count 2 2006.189.08:24:59.86#ibcon#read 4, iclass 39, count 2 2006.189.08:24:59.86#ibcon#about to read 5, iclass 39, count 2 2006.189.08:24:59.86#ibcon#read 5, iclass 39, count 2 2006.189.08:24:59.86#ibcon#about to read 6, iclass 39, count 2 2006.189.08:24:59.86#ibcon#read 6, iclass 39, count 2 2006.189.08:24:59.86#ibcon#end of sib2, iclass 39, count 2 2006.189.08:24:59.86#ibcon#*after write, iclass 39, count 2 2006.189.08:24:59.86#ibcon#*before return 0, iclass 39, count 2 2006.189.08:24:59.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:24:59.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.189.08:24:59.86#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.189.08:24:59.86#ibcon#ireg 7 cls_cnt 0 2006.189.08:24:59.86#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:24:59.98#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:24:59.98#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:24:59.98#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:24:59.98#ibcon#first serial, iclass 39, count 0 2006.189.08:24:59.98#ibcon#enter sib2, iclass 39, count 0 2006.189.08:24:59.98#ibcon#flushed, iclass 39, count 0 2006.189.08:24:59.98#ibcon#about to write, iclass 39, count 0 2006.189.08:24:59.98#ibcon#wrote, iclass 39, count 0 2006.189.08:24:59.98#ibcon#about to read 3, iclass 39, count 0 2006.189.08:25:00.00#ibcon#read 3, iclass 39, count 0 2006.189.08:25:00.00#ibcon#about to read 4, iclass 39, count 0 2006.189.08:25:00.00#ibcon#read 4, iclass 39, count 0 2006.189.08:25:00.00#ibcon#about to read 5, iclass 39, count 0 2006.189.08:25:00.00#ibcon#read 5, iclass 39, count 0 2006.189.08:25:00.00#ibcon#about to read 6, iclass 39, count 0 2006.189.08:25:00.00#ibcon#read 6, iclass 39, count 0 2006.189.08:25:00.00#ibcon#end of sib2, iclass 39, count 0 2006.189.08:25:00.00#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:25:00.00#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:25:00.00#ibcon#[25=USB\r\n] 2006.189.08:25:00.00#ibcon#*before write, iclass 39, count 0 2006.189.08:25:00.00#ibcon#enter sib2, iclass 39, count 0 2006.189.08:25:00.00#ibcon#flushed, iclass 39, count 0 2006.189.08:25:00.00#ibcon#about to write, iclass 39, count 0 2006.189.08:25:00.00#ibcon#wrote, iclass 39, count 0 2006.189.08:25:00.00#ibcon#about to read 3, iclass 39, count 0 2006.189.08:25:00.03#ibcon#read 3, iclass 39, count 0 2006.189.08:25:00.03#ibcon#about to read 4, iclass 39, count 0 2006.189.08:25:00.03#ibcon#read 4, iclass 39, count 0 2006.189.08:25:00.03#ibcon#about to read 5, iclass 39, count 0 2006.189.08:25:00.03#ibcon#read 5, iclass 39, count 0 2006.189.08:25:00.03#ibcon#about to read 6, iclass 39, count 0 2006.189.08:25:00.03#ibcon#read 6, iclass 39, count 0 2006.189.08:25:00.03#ibcon#end of sib2, iclass 39, count 0 2006.189.08:25:00.03#ibcon#*after write, iclass 39, count 0 2006.189.08:25:00.03#ibcon#*before return 0, iclass 39, count 0 2006.189.08:25:00.03#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:25:00.03#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.189.08:25:00.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:25:00.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:25:00.03$vc4f8/valo=7,832.99 2006.189.08:25:00.03#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.189.08:25:00.03#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.189.08:25:00.03#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:00.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:25:00.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:25:00.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:25:00.03#ibcon#enter wrdev, iclass 3, count 0 2006.189.08:25:00.03#ibcon#first serial, iclass 3, count 0 2006.189.08:25:00.03#ibcon#enter sib2, iclass 3, count 0 2006.189.08:25:00.03#ibcon#flushed, iclass 3, count 0 2006.189.08:25:00.03#ibcon#about to write, iclass 3, count 0 2006.189.08:25:00.03#ibcon#wrote, iclass 3, count 0 2006.189.08:25:00.03#ibcon#about to read 3, iclass 3, count 0 2006.189.08:25:00.05#ibcon#read 3, iclass 3, count 0 2006.189.08:25:00.05#ibcon#about to read 4, iclass 3, count 0 2006.189.08:25:00.05#ibcon#read 4, iclass 3, count 0 2006.189.08:25:00.05#ibcon#about to read 5, iclass 3, count 0 2006.189.08:25:00.05#ibcon#read 5, iclass 3, count 0 2006.189.08:25:00.05#ibcon#about to read 6, iclass 3, count 0 2006.189.08:25:00.05#ibcon#read 6, iclass 3, count 0 2006.189.08:25:00.05#ibcon#end of sib2, iclass 3, count 0 2006.189.08:25:00.05#ibcon#*mode == 0, iclass 3, count 0 2006.189.08:25:00.05#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.189.08:25:00.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:25:00.05#ibcon#*before write, iclass 3, count 0 2006.189.08:25:00.05#ibcon#enter sib2, iclass 3, count 0 2006.189.08:25:00.05#ibcon#flushed, iclass 3, count 0 2006.189.08:25:00.05#ibcon#about to write, iclass 3, count 0 2006.189.08:25:00.05#ibcon#wrote, iclass 3, count 0 2006.189.08:25:00.05#ibcon#about to read 3, iclass 3, count 0 2006.189.08:25:00.09#ibcon#read 3, iclass 3, count 0 2006.189.08:25:00.09#ibcon#about to read 4, iclass 3, count 0 2006.189.08:25:00.09#ibcon#read 4, iclass 3, count 0 2006.189.08:25:00.09#ibcon#about to read 5, iclass 3, count 0 2006.189.08:25:00.09#ibcon#read 5, iclass 3, count 0 2006.189.08:25:00.09#ibcon#about to read 6, iclass 3, count 0 2006.189.08:25:00.09#ibcon#read 6, iclass 3, count 0 2006.189.08:25:00.09#ibcon#end of sib2, iclass 3, count 0 2006.189.08:25:00.09#ibcon#*after write, iclass 3, count 0 2006.189.08:25:00.09#ibcon#*before return 0, iclass 3, count 0 2006.189.08:25:00.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:25:00.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.189.08:25:00.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.189.08:25:00.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.189.08:25:00.09$vc4f8/va=7,6 2006.189.08:25:00.09#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.189.08:25:00.09#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.189.08:25:00.09#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:00.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:25:00.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:25:00.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:25:00.15#ibcon#enter wrdev, iclass 5, count 2 2006.189.08:25:00.15#ibcon#first serial, iclass 5, count 2 2006.189.08:25:00.15#ibcon#enter sib2, iclass 5, count 2 2006.189.08:25:00.15#ibcon#flushed, iclass 5, count 2 2006.189.08:25:00.15#ibcon#about to write, iclass 5, count 2 2006.189.08:25:00.15#ibcon#wrote, iclass 5, count 2 2006.189.08:25:00.15#ibcon#about to read 3, iclass 5, count 2 2006.189.08:25:00.17#ibcon#read 3, iclass 5, count 2 2006.189.08:25:00.17#ibcon#about to read 4, iclass 5, count 2 2006.189.08:25:00.17#ibcon#read 4, iclass 5, count 2 2006.189.08:25:00.17#ibcon#about to read 5, iclass 5, count 2 2006.189.08:25:00.17#ibcon#read 5, iclass 5, count 2 2006.189.08:25:00.17#ibcon#about to read 6, iclass 5, count 2 2006.189.08:25:00.17#ibcon#read 6, iclass 5, count 2 2006.189.08:25:00.17#ibcon#end of sib2, iclass 5, count 2 2006.189.08:25:00.17#ibcon#*mode == 0, iclass 5, count 2 2006.189.08:25:00.17#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.189.08:25:00.17#ibcon#[25=AT07-06\r\n] 2006.189.08:25:00.17#ibcon#*before write, iclass 5, count 2 2006.189.08:25:00.17#ibcon#enter sib2, iclass 5, count 2 2006.189.08:25:00.17#ibcon#flushed, iclass 5, count 2 2006.189.08:25:00.17#ibcon#about to write, iclass 5, count 2 2006.189.08:25:00.17#ibcon#wrote, iclass 5, count 2 2006.189.08:25:00.17#ibcon#about to read 3, iclass 5, count 2 2006.189.08:25:00.20#ibcon#read 3, iclass 5, count 2 2006.189.08:25:00.20#ibcon#about to read 4, iclass 5, count 2 2006.189.08:25:00.20#ibcon#read 4, iclass 5, count 2 2006.189.08:25:00.20#ibcon#about to read 5, iclass 5, count 2 2006.189.08:25:00.20#ibcon#read 5, iclass 5, count 2 2006.189.08:25:00.20#ibcon#about to read 6, iclass 5, count 2 2006.189.08:25:00.20#ibcon#read 6, iclass 5, count 2 2006.189.08:25:00.20#ibcon#end of sib2, iclass 5, count 2 2006.189.08:25:00.20#ibcon#*after write, iclass 5, count 2 2006.189.08:25:00.20#ibcon#*before return 0, iclass 5, count 2 2006.189.08:25:00.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:25:00.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.189.08:25:00.20#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.189.08:25:00.20#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:00.20#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:25:00.32#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:25:00.32#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:25:00.32#ibcon#enter wrdev, iclass 5, count 0 2006.189.08:25:00.32#ibcon#first serial, iclass 5, count 0 2006.189.08:25:00.32#ibcon#enter sib2, iclass 5, count 0 2006.189.08:25:00.32#ibcon#flushed, iclass 5, count 0 2006.189.08:25:00.32#ibcon#about to write, iclass 5, count 0 2006.189.08:25:00.32#ibcon#wrote, iclass 5, count 0 2006.189.08:25:00.32#ibcon#about to read 3, iclass 5, count 0 2006.189.08:25:00.34#ibcon#read 3, iclass 5, count 0 2006.189.08:25:00.34#ibcon#about to read 4, iclass 5, count 0 2006.189.08:25:00.34#ibcon#read 4, iclass 5, count 0 2006.189.08:25:00.34#ibcon#about to read 5, iclass 5, count 0 2006.189.08:25:00.34#ibcon#read 5, iclass 5, count 0 2006.189.08:25:00.34#ibcon#about to read 6, iclass 5, count 0 2006.189.08:25:00.34#ibcon#read 6, iclass 5, count 0 2006.189.08:25:00.34#ibcon#end of sib2, iclass 5, count 0 2006.189.08:25:00.34#ibcon#*mode == 0, iclass 5, count 0 2006.189.08:25:00.34#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.189.08:25:00.34#ibcon#[25=USB\r\n] 2006.189.08:25:00.34#ibcon#*before write, iclass 5, count 0 2006.189.08:25:00.34#ibcon#enter sib2, iclass 5, count 0 2006.189.08:25:00.34#ibcon#flushed, iclass 5, count 0 2006.189.08:25:00.34#ibcon#about to write, iclass 5, count 0 2006.189.08:25:00.34#ibcon#wrote, iclass 5, count 0 2006.189.08:25:00.34#ibcon#about to read 3, iclass 5, count 0 2006.189.08:25:00.37#ibcon#read 3, iclass 5, count 0 2006.189.08:25:00.37#ibcon#about to read 4, iclass 5, count 0 2006.189.08:25:00.37#ibcon#read 4, iclass 5, count 0 2006.189.08:25:00.37#ibcon#about to read 5, iclass 5, count 0 2006.189.08:25:00.37#ibcon#read 5, iclass 5, count 0 2006.189.08:25:00.37#ibcon#about to read 6, iclass 5, count 0 2006.189.08:25:00.37#ibcon#read 6, iclass 5, count 0 2006.189.08:25:00.37#ibcon#end of sib2, iclass 5, count 0 2006.189.08:25:00.37#ibcon#*after write, iclass 5, count 0 2006.189.08:25:00.37#ibcon#*before return 0, iclass 5, count 0 2006.189.08:25:00.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:25:00.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.189.08:25:00.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.189.08:25:00.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.189.08:25:00.37$vc4f8/valo=8,852.99 2006.189.08:25:00.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.189.08:25:00.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.189.08:25:00.37#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:00.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:25:00.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:25:00.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:25:00.37#ibcon#enter wrdev, iclass 7, count 0 2006.189.08:25:00.37#ibcon#first serial, iclass 7, count 0 2006.189.08:25:00.37#ibcon#enter sib2, iclass 7, count 0 2006.189.08:25:00.37#ibcon#flushed, iclass 7, count 0 2006.189.08:25:00.37#ibcon#about to write, iclass 7, count 0 2006.189.08:25:00.37#ibcon#wrote, iclass 7, count 0 2006.189.08:25:00.37#ibcon#about to read 3, iclass 7, count 0 2006.189.08:25:00.39#ibcon#read 3, iclass 7, count 0 2006.189.08:25:00.39#ibcon#about to read 4, iclass 7, count 0 2006.189.08:25:00.39#ibcon#read 4, iclass 7, count 0 2006.189.08:25:00.39#ibcon#about to read 5, iclass 7, count 0 2006.189.08:25:00.39#ibcon#read 5, iclass 7, count 0 2006.189.08:25:00.39#ibcon#about to read 6, iclass 7, count 0 2006.189.08:25:00.39#ibcon#read 6, iclass 7, count 0 2006.189.08:25:00.39#ibcon#end of sib2, iclass 7, count 0 2006.189.08:25:00.39#ibcon#*mode == 0, iclass 7, count 0 2006.189.08:25:00.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.189.08:25:00.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:25:00.39#ibcon#*before write, iclass 7, count 0 2006.189.08:25:00.39#ibcon#enter sib2, iclass 7, count 0 2006.189.08:25:00.39#ibcon#flushed, iclass 7, count 0 2006.189.08:25:00.39#ibcon#about to write, iclass 7, count 0 2006.189.08:25:00.39#ibcon#wrote, iclass 7, count 0 2006.189.08:25:00.39#ibcon#about to read 3, iclass 7, count 0 2006.189.08:25:00.43#ibcon#read 3, iclass 7, count 0 2006.189.08:25:00.43#ibcon#about to read 4, iclass 7, count 0 2006.189.08:25:00.43#ibcon#read 4, iclass 7, count 0 2006.189.08:25:00.43#ibcon#about to read 5, iclass 7, count 0 2006.189.08:25:00.43#ibcon#read 5, iclass 7, count 0 2006.189.08:25:00.43#ibcon#about to read 6, iclass 7, count 0 2006.189.08:25:00.43#ibcon#read 6, iclass 7, count 0 2006.189.08:25:00.43#ibcon#end of sib2, iclass 7, count 0 2006.189.08:25:00.43#ibcon#*after write, iclass 7, count 0 2006.189.08:25:00.43#ibcon#*before return 0, iclass 7, count 0 2006.189.08:25:00.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:25:00.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.189.08:25:00.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.189.08:25:00.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.189.08:25:00.43$vc4f8/va=8,6 2006.189.08:25:00.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.189.08:25:00.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.189.08:25:00.43#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:00.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:25:00.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:25:00.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:25:00.49#ibcon#enter wrdev, iclass 11, count 2 2006.189.08:25:00.49#ibcon#first serial, iclass 11, count 2 2006.189.08:25:00.49#ibcon#enter sib2, iclass 11, count 2 2006.189.08:25:00.49#ibcon#flushed, iclass 11, count 2 2006.189.08:25:00.49#ibcon#about to write, iclass 11, count 2 2006.189.08:25:00.49#ibcon#wrote, iclass 11, count 2 2006.189.08:25:00.49#ibcon#about to read 3, iclass 11, count 2 2006.189.08:25:00.51#ibcon#read 3, iclass 11, count 2 2006.189.08:25:00.51#ibcon#about to read 4, iclass 11, count 2 2006.189.08:25:00.51#ibcon#read 4, iclass 11, count 2 2006.189.08:25:00.51#ibcon#about to read 5, iclass 11, count 2 2006.189.08:25:00.51#ibcon#read 5, iclass 11, count 2 2006.189.08:25:00.51#ibcon#about to read 6, iclass 11, count 2 2006.189.08:25:00.51#ibcon#read 6, iclass 11, count 2 2006.189.08:25:00.51#ibcon#end of sib2, iclass 11, count 2 2006.189.08:25:00.51#ibcon#*mode == 0, iclass 11, count 2 2006.189.08:25:00.51#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.189.08:25:00.51#ibcon#[25=AT08-06\r\n] 2006.189.08:25:00.51#ibcon#*before write, iclass 11, count 2 2006.189.08:25:00.51#ibcon#enter sib2, iclass 11, count 2 2006.189.08:25:00.51#ibcon#flushed, iclass 11, count 2 2006.189.08:25:00.51#ibcon#about to write, iclass 11, count 2 2006.189.08:25:00.51#ibcon#wrote, iclass 11, count 2 2006.189.08:25:00.51#ibcon#about to read 3, iclass 11, count 2 2006.189.08:25:00.54#ibcon#read 3, iclass 11, count 2 2006.189.08:25:00.54#ibcon#about to read 4, iclass 11, count 2 2006.189.08:25:00.54#ibcon#read 4, iclass 11, count 2 2006.189.08:25:00.54#ibcon#about to read 5, iclass 11, count 2 2006.189.08:25:00.54#ibcon#read 5, iclass 11, count 2 2006.189.08:25:00.54#ibcon#about to read 6, iclass 11, count 2 2006.189.08:25:00.54#ibcon#read 6, iclass 11, count 2 2006.189.08:25:00.54#ibcon#end of sib2, iclass 11, count 2 2006.189.08:25:00.54#ibcon#*after write, iclass 11, count 2 2006.189.08:25:00.54#ibcon#*before return 0, iclass 11, count 2 2006.189.08:25:00.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:25:00.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.189.08:25:00.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.189.08:25:00.54#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:00.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:25:00.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:25:00.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:25:00.66#ibcon#enter wrdev, iclass 11, count 0 2006.189.08:25:00.66#ibcon#first serial, iclass 11, count 0 2006.189.08:25:00.66#ibcon#enter sib2, iclass 11, count 0 2006.189.08:25:00.66#ibcon#flushed, iclass 11, count 0 2006.189.08:25:00.66#ibcon#about to write, iclass 11, count 0 2006.189.08:25:00.66#ibcon#wrote, iclass 11, count 0 2006.189.08:25:00.66#ibcon#about to read 3, iclass 11, count 0 2006.189.08:25:00.68#ibcon#read 3, iclass 11, count 0 2006.189.08:25:00.68#ibcon#about to read 4, iclass 11, count 0 2006.189.08:25:00.68#ibcon#read 4, iclass 11, count 0 2006.189.08:25:00.68#ibcon#about to read 5, iclass 11, count 0 2006.189.08:25:00.68#ibcon#read 5, iclass 11, count 0 2006.189.08:25:00.68#ibcon#about to read 6, iclass 11, count 0 2006.189.08:25:00.68#ibcon#read 6, iclass 11, count 0 2006.189.08:25:00.68#ibcon#end of sib2, iclass 11, count 0 2006.189.08:25:00.68#ibcon#*mode == 0, iclass 11, count 0 2006.189.08:25:00.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.189.08:25:00.68#ibcon#[25=USB\r\n] 2006.189.08:25:00.68#ibcon#*before write, iclass 11, count 0 2006.189.08:25:00.68#ibcon#enter sib2, iclass 11, count 0 2006.189.08:25:00.68#ibcon#flushed, iclass 11, count 0 2006.189.08:25:00.68#ibcon#about to write, iclass 11, count 0 2006.189.08:25:00.68#ibcon#wrote, iclass 11, count 0 2006.189.08:25:00.68#ibcon#about to read 3, iclass 11, count 0 2006.189.08:25:00.71#ibcon#read 3, iclass 11, count 0 2006.189.08:25:00.71#ibcon#about to read 4, iclass 11, count 0 2006.189.08:25:00.71#ibcon#read 4, iclass 11, count 0 2006.189.08:25:00.71#ibcon#about to read 5, iclass 11, count 0 2006.189.08:25:00.71#ibcon#read 5, iclass 11, count 0 2006.189.08:25:00.71#ibcon#about to read 6, iclass 11, count 0 2006.189.08:25:00.71#ibcon#read 6, iclass 11, count 0 2006.189.08:25:00.71#ibcon#end of sib2, iclass 11, count 0 2006.189.08:25:00.71#ibcon#*after write, iclass 11, count 0 2006.189.08:25:00.71#ibcon#*before return 0, iclass 11, count 0 2006.189.08:25:00.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:25:00.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.189.08:25:00.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.189.08:25:00.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.189.08:25:00.71$vc4f8/vblo=1,632.99 2006.189.08:25:00.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.189.08:25:00.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.189.08:25:00.71#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:00.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:25:00.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:25:00.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:25:00.71#ibcon#enter wrdev, iclass 13, count 0 2006.189.08:25:00.71#ibcon#first serial, iclass 13, count 0 2006.189.08:25:00.71#ibcon#enter sib2, iclass 13, count 0 2006.189.08:25:00.71#ibcon#flushed, iclass 13, count 0 2006.189.08:25:00.71#ibcon#about to write, iclass 13, count 0 2006.189.08:25:00.71#ibcon#wrote, iclass 13, count 0 2006.189.08:25:00.71#ibcon#about to read 3, iclass 13, count 0 2006.189.08:25:00.73#ibcon#read 3, iclass 13, count 0 2006.189.08:25:00.73#ibcon#about to read 4, iclass 13, count 0 2006.189.08:25:00.73#ibcon#read 4, iclass 13, count 0 2006.189.08:25:00.73#ibcon#about to read 5, iclass 13, count 0 2006.189.08:25:00.73#ibcon#read 5, iclass 13, count 0 2006.189.08:25:00.73#ibcon#about to read 6, iclass 13, count 0 2006.189.08:25:00.73#ibcon#read 6, iclass 13, count 0 2006.189.08:25:00.73#ibcon#end of sib2, iclass 13, count 0 2006.189.08:25:00.73#ibcon#*mode == 0, iclass 13, count 0 2006.189.08:25:00.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.189.08:25:00.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:25:00.73#ibcon#*before write, iclass 13, count 0 2006.189.08:25:00.73#ibcon#enter sib2, iclass 13, count 0 2006.189.08:25:00.73#ibcon#flushed, iclass 13, count 0 2006.189.08:25:00.73#ibcon#about to write, iclass 13, count 0 2006.189.08:25:00.73#ibcon#wrote, iclass 13, count 0 2006.189.08:25:00.73#ibcon#about to read 3, iclass 13, count 0 2006.189.08:25:00.77#ibcon#read 3, iclass 13, count 0 2006.189.08:25:00.77#ibcon#about to read 4, iclass 13, count 0 2006.189.08:25:00.77#ibcon#read 4, iclass 13, count 0 2006.189.08:25:00.77#ibcon#about to read 5, iclass 13, count 0 2006.189.08:25:00.77#ibcon#read 5, iclass 13, count 0 2006.189.08:25:00.77#ibcon#about to read 6, iclass 13, count 0 2006.189.08:25:00.77#ibcon#read 6, iclass 13, count 0 2006.189.08:25:00.77#ibcon#end of sib2, iclass 13, count 0 2006.189.08:25:00.77#ibcon#*after write, iclass 13, count 0 2006.189.08:25:00.77#ibcon#*before return 0, iclass 13, count 0 2006.189.08:25:00.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:25:00.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.189.08:25:00.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.189.08:25:00.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.189.08:25:00.77$vc4f8/vb=1,4 2006.189.08:25:00.77#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.189.08:25:00.77#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.189.08:25:00.77#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:00.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:25:00.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:25:00.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:25:00.77#ibcon#enter wrdev, iclass 15, count 2 2006.189.08:25:00.77#ibcon#first serial, iclass 15, count 2 2006.189.08:25:00.77#ibcon#enter sib2, iclass 15, count 2 2006.189.08:25:00.77#ibcon#flushed, iclass 15, count 2 2006.189.08:25:00.77#ibcon#about to write, iclass 15, count 2 2006.189.08:25:00.77#ibcon#wrote, iclass 15, count 2 2006.189.08:25:00.77#ibcon#about to read 3, iclass 15, count 2 2006.189.08:25:00.79#ibcon#read 3, iclass 15, count 2 2006.189.08:25:00.79#ibcon#about to read 4, iclass 15, count 2 2006.189.08:25:00.79#ibcon#read 4, iclass 15, count 2 2006.189.08:25:00.79#ibcon#about to read 5, iclass 15, count 2 2006.189.08:25:00.79#ibcon#read 5, iclass 15, count 2 2006.189.08:25:00.79#ibcon#about to read 6, iclass 15, count 2 2006.189.08:25:00.79#ibcon#read 6, iclass 15, count 2 2006.189.08:25:00.79#ibcon#end of sib2, iclass 15, count 2 2006.189.08:25:00.79#ibcon#*mode == 0, iclass 15, count 2 2006.189.08:25:00.79#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.189.08:25:00.79#ibcon#[27=AT01-04\r\n] 2006.189.08:25:00.79#ibcon#*before write, iclass 15, count 2 2006.189.08:25:00.79#ibcon#enter sib2, iclass 15, count 2 2006.189.08:25:00.79#ibcon#flushed, iclass 15, count 2 2006.189.08:25:00.79#ibcon#about to write, iclass 15, count 2 2006.189.08:25:00.79#ibcon#wrote, iclass 15, count 2 2006.189.08:25:00.79#ibcon#about to read 3, iclass 15, count 2 2006.189.08:25:00.82#ibcon#read 3, iclass 15, count 2 2006.189.08:25:00.82#ibcon#about to read 4, iclass 15, count 2 2006.189.08:25:00.82#ibcon#read 4, iclass 15, count 2 2006.189.08:25:00.82#ibcon#about to read 5, iclass 15, count 2 2006.189.08:25:00.82#ibcon#read 5, iclass 15, count 2 2006.189.08:25:00.82#ibcon#about to read 6, iclass 15, count 2 2006.189.08:25:00.82#ibcon#read 6, iclass 15, count 2 2006.189.08:25:00.82#ibcon#end of sib2, iclass 15, count 2 2006.189.08:25:00.82#ibcon#*after write, iclass 15, count 2 2006.189.08:25:00.82#ibcon#*before return 0, iclass 15, count 2 2006.189.08:25:00.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:25:00.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.189.08:25:00.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.189.08:25:00.82#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:00.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:25:00.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:25:00.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:25:00.94#ibcon#enter wrdev, iclass 15, count 0 2006.189.08:25:00.94#ibcon#first serial, iclass 15, count 0 2006.189.08:25:00.94#ibcon#enter sib2, iclass 15, count 0 2006.189.08:25:00.94#ibcon#flushed, iclass 15, count 0 2006.189.08:25:00.94#ibcon#about to write, iclass 15, count 0 2006.189.08:25:00.94#ibcon#wrote, iclass 15, count 0 2006.189.08:25:00.94#ibcon#about to read 3, iclass 15, count 0 2006.189.08:25:00.96#ibcon#read 3, iclass 15, count 0 2006.189.08:25:00.96#ibcon#about to read 4, iclass 15, count 0 2006.189.08:25:00.96#ibcon#read 4, iclass 15, count 0 2006.189.08:25:00.96#ibcon#about to read 5, iclass 15, count 0 2006.189.08:25:00.96#ibcon#read 5, iclass 15, count 0 2006.189.08:25:00.96#ibcon#about to read 6, iclass 15, count 0 2006.189.08:25:00.96#ibcon#read 6, iclass 15, count 0 2006.189.08:25:00.96#ibcon#end of sib2, iclass 15, count 0 2006.189.08:25:00.96#ibcon#*mode == 0, iclass 15, count 0 2006.189.08:25:00.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.189.08:25:00.96#ibcon#[27=USB\r\n] 2006.189.08:25:00.96#ibcon#*before write, iclass 15, count 0 2006.189.08:25:00.96#ibcon#enter sib2, iclass 15, count 0 2006.189.08:25:00.96#ibcon#flushed, iclass 15, count 0 2006.189.08:25:00.96#ibcon#about to write, iclass 15, count 0 2006.189.08:25:00.96#ibcon#wrote, iclass 15, count 0 2006.189.08:25:00.96#ibcon#about to read 3, iclass 15, count 0 2006.189.08:25:00.99#ibcon#read 3, iclass 15, count 0 2006.189.08:25:00.99#ibcon#about to read 4, iclass 15, count 0 2006.189.08:25:00.99#ibcon#read 4, iclass 15, count 0 2006.189.08:25:00.99#ibcon#about to read 5, iclass 15, count 0 2006.189.08:25:00.99#ibcon#read 5, iclass 15, count 0 2006.189.08:25:00.99#ibcon#about to read 6, iclass 15, count 0 2006.189.08:25:00.99#ibcon#read 6, iclass 15, count 0 2006.189.08:25:00.99#ibcon#end of sib2, iclass 15, count 0 2006.189.08:25:00.99#ibcon#*after write, iclass 15, count 0 2006.189.08:25:00.99#ibcon#*before return 0, iclass 15, count 0 2006.189.08:25:00.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:25:00.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.189.08:25:00.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.189.08:25:00.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.189.08:25:00.99$vc4f8/vblo=2,640.99 2006.189.08:25:00.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.189.08:25:00.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.189.08:25:00.99#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:00.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:25:00.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:25:00.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:25:00.99#ibcon#enter wrdev, iclass 17, count 0 2006.189.08:25:00.99#ibcon#first serial, iclass 17, count 0 2006.189.08:25:00.99#ibcon#enter sib2, iclass 17, count 0 2006.189.08:25:00.99#ibcon#flushed, iclass 17, count 0 2006.189.08:25:00.99#ibcon#about to write, iclass 17, count 0 2006.189.08:25:00.99#ibcon#wrote, iclass 17, count 0 2006.189.08:25:00.99#ibcon#about to read 3, iclass 17, count 0 2006.189.08:25:01.01#ibcon#read 3, iclass 17, count 0 2006.189.08:25:01.01#ibcon#about to read 4, iclass 17, count 0 2006.189.08:25:01.01#ibcon#read 4, iclass 17, count 0 2006.189.08:25:01.01#ibcon#about to read 5, iclass 17, count 0 2006.189.08:25:01.01#ibcon#read 5, iclass 17, count 0 2006.189.08:25:01.01#ibcon#about to read 6, iclass 17, count 0 2006.189.08:25:01.01#ibcon#read 6, iclass 17, count 0 2006.189.08:25:01.01#ibcon#end of sib2, iclass 17, count 0 2006.189.08:25:01.01#ibcon#*mode == 0, iclass 17, count 0 2006.189.08:25:01.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.189.08:25:01.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:25:01.01#ibcon#*before write, iclass 17, count 0 2006.189.08:25:01.01#ibcon#enter sib2, iclass 17, count 0 2006.189.08:25:01.01#ibcon#flushed, iclass 17, count 0 2006.189.08:25:01.01#ibcon#about to write, iclass 17, count 0 2006.189.08:25:01.01#ibcon#wrote, iclass 17, count 0 2006.189.08:25:01.01#ibcon#about to read 3, iclass 17, count 0 2006.189.08:25:01.05#ibcon#read 3, iclass 17, count 0 2006.189.08:25:01.05#ibcon#about to read 4, iclass 17, count 0 2006.189.08:25:01.05#ibcon#read 4, iclass 17, count 0 2006.189.08:25:01.05#ibcon#about to read 5, iclass 17, count 0 2006.189.08:25:01.05#ibcon#read 5, iclass 17, count 0 2006.189.08:25:01.05#ibcon#about to read 6, iclass 17, count 0 2006.189.08:25:01.05#ibcon#read 6, iclass 17, count 0 2006.189.08:25:01.05#ibcon#end of sib2, iclass 17, count 0 2006.189.08:25:01.05#ibcon#*after write, iclass 17, count 0 2006.189.08:25:01.05#ibcon#*before return 0, iclass 17, count 0 2006.189.08:25:01.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:25:01.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.189.08:25:01.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.189.08:25:01.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.189.08:25:01.05$vc4f8/vb=2,4 2006.189.08:25:01.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.189.08:25:01.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.189.08:25:01.05#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:01.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:25:01.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:25:01.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:25:01.11#ibcon#enter wrdev, iclass 19, count 2 2006.189.08:25:01.11#ibcon#first serial, iclass 19, count 2 2006.189.08:25:01.11#ibcon#enter sib2, iclass 19, count 2 2006.189.08:25:01.11#ibcon#flushed, iclass 19, count 2 2006.189.08:25:01.11#ibcon#about to write, iclass 19, count 2 2006.189.08:25:01.11#ibcon#wrote, iclass 19, count 2 2006.189.08:25:01.11#ibcon#about to read 3, iclass 19, count 2 2006.189.08:25:01.13#ibcon#read 3, iclass 19, count 2 2006.189.08:25:01.13#ibcon#about to read 4, iclass 19, count 2 2006.189.08:25:01.13#ibcon#read 4, iclass 19, count 2 2006.189.08:25:01.13#ibcon#about to read 5, iclass 19, count 2 2006.189.08:25:01.13#ibcon#read 5, iclass 19, count 2 2006.189.08:25:01.13#ibcon#about to read 6, iclass 19, count 2 2006.189.08:25:01.13#ibcon#read 6, iclass 19, count 2 2006.189.08:25:01.13#ibcon#end of sib2, iclass 19, count 2 2006.189.08:25:01.13#ibcon#*mode == 0, iclass 19, count 2 2006.189.08:25:01.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.189.08:25:01.13#ibcon#[27=AT02-04\r\n] 2006.189.08:25:01.13#ibcon#*before write, iclass 19, count 2 2006.189.08:25:01.13#ibcon#enter sib2, iclass 19, count 2 2006.189.08:25:01.13#ibcon#flushed, iclass 19, count 2 2006.189.08:25:01.13#ibcon#about to write, iclass 19, count 2 2006.189.08:25:01.13#ibcon#wrote, iclass 19, count 2 2006.189.08:25:01.13#ibcon#about to read 3, iclass 19, count 2 2006.189.08:25:01.16#ibcon#read 3, iclass 19, count 2 2006.189.08:25:01.16#ibcon#about to read 4, iclass 19, count 2 2006.189.08:25:01.16#ibcon#read 4, iclass 19, count 2 2006.189.08:25:01.16#ibcon#about to read 5, iclass 19, count 2 2006.189.08:25:01.16#ibcon#read 5, iclass 19, count 2 2006.189.08:25:01.16#ibcon#about to read 6, iclass 19, count 2 2006.189.08:25:01.16#ibcon#read 6, iclass 19, count 2 2006.189.08:25:01.16#ibcon#end of sib2, iclass 19, count 2 2006.189.08:25:01.16#ibcon#*after write, iclass 19, count 2 2006.189.08:25:01.16#ibcon#*before return 0, iclass 19, count 2 2006.189.08:25:01.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:25:01.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.189.08:25:01.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.189.08:25:01.16#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:01.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:25:01.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:25:01.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:25:01.28#ibcon#enter wrdev, iclass 19, count 0 2006.189.08:25:01.28#ibcon#first serial, iclass 19, count 0 2006.189.08:25:01.28#ibcon#enter sib2, iclass 19, count 0 2006.189.08:25:01.28#ibcon#flushed, iclass 19, count 0 2006.189.08:25:01.28#ibcon#about to write, iclass 19, count 0 2006.189.08:25:01.28#ibcon#wrote, iclass 19, count 0 2006.189.08:25:01.28#ibcon#about to read 3, iclass 19, count 0 2006.189.08:25:01.30#ibcon#read 3, iclass 19, count 0 2006.189.08:25:01.30#ibcon#about to read 4, iclass 19, count 0 2006.189.08:25:01.30#ibcon#read 4, iclass 19, count 0 2006.189.08:25:01.30#ibcon#about to read 5, iclass 19, count 0 2006.189.08:25:01.30#ibcon#read 5, iclass 19, count 0 2006.189.08:25:01.30#ibcon#about to read 6, iclass 19, count 0 2006.189.08:25:01.30#ibcon#read 6, iclass 19, count 0 2006.189.08:25:01.30#ibcon#end of sib2, iclass 19, count 0 2006.189.08:25:01.30#ibcon#*mode == 0, iclass 19, count 0 2006.189.08:25:01.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.189.08:25:01.30#ibcon#[27=USB\r\n] 2006.189.08:25:01.30#ibcon#*before write, iclass 19, count 0 2006.189.08:25:01.30#ibcon#enter sib2, iclass 19, count 0 2006.189.08:25:01.30#ibcon#flushed, iclass 19, count 0 2006.189.08:25:01.30#ibcon#about to write, iclass 19, count 0 2006.189.08:25:01.30#ibcon#wrote, iclass 19, count 0 2006.189.08:25:01.30#ibcon#about to read 3, iclass 19, count 0 2006.189.08:25:01.33#ibcon#read 3, iclass 19, count 0 2006.189.08:25:01.33#ibcon#about to read 4, iclass 19, count 0 2006.189.08:25:01.33#ibcon#read 4, iclass 19, count 0 2006.189.08:25:01.33#ibcon#about to read 5, iclass 19, count 0 2006.189.08:25:01.33#ibcon#read 5, iclass 19, count 0 2006.189.08:25:01.33#ibcon#about to read 6, iclass 19, count 0 2006.189.08:25:01.33#ibcon#read 6, iclass 19, count 0 2006.189.08:25:01.33#ibcon#end of sib2, iclass 19, count 0 2006.189.08:25:01.33#ibcon#*after write, iclass 19, count 0 2006.189.08:25:01.33#ibcon#*before return 0, iclass 19, count 0 2006.189.08:25:01.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:25:01.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.189.08:25:01.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.189.08:25:01.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.189.08:25:01.33$vc4f8/vblo=3,656.99 2006.189.08:25:01.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.189.08:25:01.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.189.08:25:01.33#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:01.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:25:01.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:25:01.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:25:01.33#ibcon#enter wrdev, iclass 21, count 0 2006.189.08:25:01.33#ibcon#first serial, iclass 21, count 0 2006.189.08:25:01.33#ibcon#enter sib2, iclass 21, count 0 2006.189.08:25:01.33#ibcon#flushed, iclass 21, count 0 2006.189.08:25:01.33#ibcon#about to write, iclass 21, count 0 2006.189.08:25:01.33#ibcon#wrote, iclass 21, count 0 2006.189.08:25:01.33#ibcon#about to read 3, iclass 21, count 0 2006.189.08:25:01.35#ibcon#read 3, iclass 21, count 0 2006.189.08:25:01.35#ibcon#about to read 4, iclass 21, count 0 2006.189.08:25:01.35#ibcon#read 4, iclass 21, count 0 2006.189.08:25:01.35#ibcon#about to read 5, iclass 21, count 0 2006.189.08:25:01.35#ibcon#read 5, iclass 21, count 0 2006.189.08:25:01.35#ibcon#about to read 6, iclass 21, count 0 2006.189.08:25:01.35#ibcon#read 6, iclass 21, count 0 2006.189.08:25:01.35#ibcon#end of sib2, iclass 21, count 0 2006.189.08:25:01.35#ibcon#*mode == 0, iclass 21, count 0 2006.189.08:25:01.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.189.08:25:01.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:25:01.35#ibcon#*before write, iclass 21, count 0 2006.189.08:25:01.35#ibcon#enter sib2, iclass 21, count 0 2006.189.08:25:01.35#ibcon#flushed, iclass 21, count 0 2006.189.08:25:01.35#ibcon#about to write, iclass 21, count 0 2006.189.08:25:01.35#ibcon#wrote, iclass 21, count 0 2006.189.08:25:01.35#ibcon#about to read 3, iclass 21, count 0 2006.189.08:25:01.39#ibcon#read 3, iclass 21, count 0 2006.189.08:25:01.39#ibcon#about to read 4, iclass 21, count 0 2006.189.08:25:01.39#ibcon#read 4, iclass 21, count 0 2006.189.08:25:01.39#ibcon#about to read 5, iclass 21, count 0 2006.189.08:25:01.39#ibcon#read 5, iclass 21, count 0 2006.189.08:25:01.39#ibcon#about to read 6, iclass 21, count 0 2006.189.08:25:01.39#ibcon#read 6, iclass 21, count 0 2006.189.08:25:01.39#ibcon#end of sib2, iclass 21, count 0 2006.189.08:25:01.39#ibcon#*after write, iclass 21, count 0 2006.189.08:25:01.39#ibcon#*before return 0, iclass 21, count 0 2006.189.08:25:01.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:25:01.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.189.08:25:01.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.189.08:25:01.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.189.08:25:01.39$vc4f8/vb=3,4 2006.189.08:25:01.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.189.08:25:01.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.189.08:25:01.39#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:01.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:25:01.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:25:01.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:25:01.45#ibcon#enter wrdev, iclass 23, count 2 2006.189.08:25:01.45#ibcon#first serial, iclass 23, count 2 2006.189.08:25:01.45#ibcon#enter sib2, iclass 23, count 2 2006.189.08:25:01.45#ibcon#flushed, iclass 23, count 2 2006.189.08:25:01.45#ibcon#about to write, iclass 23, count 2 2006.189.08:25:01.45#ibcon#wrote, iclass 23, count 2 2006.189.08:25:01.45#ibcon#about to read 3, iclass 23, count 2 2006.189.08:25:01.47#ibcon#read 3, iclass 23, count 2 2006.189.08:25:01.47#ibcon#about to read 4, iclass 23, count 2 2006.189.08:25:01.47#ibcon#read 4, iclass 23, count 2 2006.189.08:25:01.47#ibcon#about to read 5, iclass 23, count 2 2006.189.08:25:01.47#ibcon#read 5, iclass 23, count 2 2006.189.08:25:01.47#ibcon#about to read 6, iclass 23, count 2 2006.189.08:25:01.47#ibcon#read 6, iclass 23, count 2 2006.189.08:25:01.47#ibcon#end of sib2, iclass 23, count 2 2006.189.08:25:01.47#ibcon#*mode == 0, iclass 23, count 2 2006.189.08:25:01.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.189.08:25:01.47#ibcon#[27=AT03-04\r\n] 2006.189.08:25:01.47#ibcon#*before write, iclass 23, count 2 2006.189.08:25:01.47#ibcon#enter sib2, iclass 23, count 2 2006.189.08:25:01.47#ibcon#flushed, iclass 23, count 2 2006.189.08:25:01.47#ibcon#about to write, iclass 23, count 2 2006.189.08:25:01.47#ibcon#wrote, iclass 23, count 2 2006.189.08:25:01.47#ibcon#about to read 3, iclass 23, count 2 2006.189.08:25:01.50#ibcon#read 3, iclass 23, count 2 2006.189.08:25:01.50#ibcon#about to read 4, iclass 23, count 2 2006.189.08:25:01.50#ibcon#read 4, iclass 23, count 2 2006.189.08:25:01.50#ibcon#about to read 5, iclass 23, count 2 2006.189.08:25:01.50#ibcon#read 5, iclass 23, count 2 2006.189.08:25:01.50#ibcon#about to read 6, iclass 23, count 2 2006.189.08:25:01.50#ibcon#read 6, iclass 23, count 2 2006.189.08:25:01.50#ibcon#end of sib2, iclass 23, count 2 2006.189.08:25:01.50#ibcon#*after write, iclass 23, count 2 2006.189.08:25:01.50#ibcon#*before return 0, iclass 23, count 2 2006.189.08:25:01.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:25:01.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.189.08:25:01.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.189.08:25:01.50#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:01.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:25:01.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:25:01.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:25:01.62#ibcon#enter wrdev, iclass 23, count 0 2006.189.08:25:01.62#ibcon#first serial, iclass 23, count 0 2006.189.08:25:01.62#ibcon#enter sib2, iclass 23, count 0 2006.189.08:25:01.62#ibcon#flushed, iclass 23, count 0 2006.189.08:25:01.62#ibcon#about to write, iclass 23, count 0 2006.189.08:25:01.62#ibcon#wrote, iclass 23, count 0 2006.189.08:25:01.62#ibcon#about to read 3, iclass 23, count 0 2006.189.08:25:01.64#ibcon#read 3, iclass 23, count 0 2006.189.08:25:01.64#ibcon#about to read 4, iclass 23, count 0 2006.189.08:25:01.64#ibcon#read 4, iclass 23, count 0 2006.189.08:25:01.64#ibcon#about to read 5, iclass 23, count 0 2006.189.08:25:01.64#ibcon#read 5, iclass 23, count 0 2006.189.08:25:01.64#ibcon#about to read 6, iclass 23, count 0 2006.189.08:25:01.64#ibcon#read 6, iclass 23, count 0 2006.189.08:25:01.64#ibcon#end of sib2, iclass 23, count 0 2006.189.08:25:01.64#ibcon#*mode == 0, iclass 23, count 0 2006.189.08:25:01.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.189.08:25:01.64#ibcon#[27=USB\r\n] 2006.189.08:25:01.64#ibcon#*before write, iclass 23, count 0 2006.189.08:25:01.64#ibcon#enter sib2, iclass 23, count 0 2006.189.08:25:01.64#ibcon#flushed, iclass 23, count 0 2006.189.08:25:01.64#ibcon#about to write, iclass 23, count 0 2006.189.08:25:01.64#ibcon#wrote, iclass 23, count 0 2006.189.08:25:01.64#ibcon#about to read 3, iclass 23, count 0 2006.189.08:25:01.67#ibcon#read 3, iclass 23, count 0 2006.189.08:25:01.67#ibcon#about to read 4, iclass 23, count 0 2006.189.08:25:01.67#ibcon#read 4, iclass 23, count 0 2006.189.08:25:01.67#ibcon#about to read 5, iclass 23, count 0 2006.189.08:25:01.67#ibcon#read 5, iclass 23, count 0 2006.189.08:25:01.67#ibcon#about to read 6, iclass 23, count 0 2006.189.08:25:01.67#ibcon#read 6, iclass 23, count 0 2006.189.08:25:01.67#ibcon#end of sib2, iclass 23, count 0 2006.189.08:25:01.67#ibcon#*after write, iclass 23, count 0 2006.189.08:25:01.67#ibcon#*before return 0, iclass 23, count 0 2006.189.08:25:01.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:25:01.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.189.08:25:01.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.189.08:25:01.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.189.08:25:01.67$vc4f8/vblo=4,712.99 2006.189.08:25:01.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.189.08:25:01.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.189.08:25:01.67#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:01.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:25:01.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:25:01.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:25:01.67#ibcon#enter wrdev, iclass 25, count 0 2006.189.08:25:01.67#ibcon#first serial, iclass 25, count 0 2006.189.08:25:01.67#ibcon#enter sib2, iclass 25, count 0 2006.189.08:25:01.67#ibcon#flushed, iclass 25, count 0 2006.189.08:25:01.67#ibcon#about to write, iclass 25, count 0 2006.189.08:25:01.67#ibcon#wrote, iclass 25, count 0 2006.189.08:25:01.67#ibcon#about to read 3, iclass 25, count 0 2006.189.08:25:01.69#ibcon#read 3, iclass 25, count 0 2006.189.08:25:01.69#ibcon#about to read 4, iclass 25, count 0 2006.189.08:25:01.69#ibcon#read 4, iclass 25, count 0 2006.189.08:25:01.69#ibcon#about to read 5, iclass 25, count 0 2006.189.08:25:01.69#ibcon#read 5, iclass 25, count 0 2006.189.08:25:01.69#ibcon#about to read 6, iclass 25, count 0 2006.189.08:25:01.69#ibcon#read 6, iclass 25, count 0 2006.189.08:25:01.69#ibcon#end of sib2, iclass 25, count 0 2006.189.08:25:01.69#ibcon#*mode == 0, iclass 25, count 0 2006.189.08:25:01.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.189.08:25:01.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:25:01.69#ibcon#*before write, iclass 25, count 0 2006.189.08:25:01.69#ibcon#enter sib2, iclass 25, count 0 2006.189.08:25:01.69#ibcon#flushed, iclass 25, count 0 2006.189.08:25:01.69#ibcon#about to write, iclass 25, count 0 2006.189.08:25:01.69#ibcon#wrote, iclass 25, count 0 2006.189.08:25:01.69#ibcon#about to read 3, iclass 25, count 0 2006.189.08:25:01.73#ibcon#read 3, iclass 25, count 0 2006.189.08:25:01.73#ibcon#about to read 4, iclass 25, count 0 2006.189.08:25:01.73#ibcon#read 4, iclass 25, count 0 2006.189.08:25:01.73#ibcon#about to read 5, iclass 25, count 0 2006.189.08:25:01.73#ibcon#read 5, iclass 25, count 0 2006.189.08:25:01.73#ibcon#about to read 6, iclass 25, count 0 2006.189.08:25:01.73#ibcon#read 6, iclass 25, count 0 2006.189.08:25:01.73#ibcon#end of sib2, iclass 25, count 0 2006.189.08:25:01.73#ibcon#*after write, iclass 25, count 0 2006.189.08:25:01.73#ibcon#*before return 0, iclass 25, count 0 2006.189.08:25:01.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:25:01.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.189.08:25:01.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.189.08:25:01.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.189.08:25:01.73$vc4f8/vb=4,4 2006.189.08:25:01.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.189.08:25:01.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.189.08:25:01.73#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:01.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:25:01.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:25:01.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:25:01.79#ibcon#enter wrdev, iclass 27, count 2 2006.189.08:25:01.79#ibcon#first serial, iclass 27, count 2 2006.189.08:25:01.79#ibcon#enter sib2, iclass 27, count 2 2006.189.08:25:01.79#ibcon#flushed, iclass 27, count 2 2006.189.08:25:01.79#ibcon#about to write, iclass 27, count 2 2006.189.08:25:01.79#ibcon#wrote, iclass 27, count 2 2006.189.08:25:01.79#ibcon#about to read 3, iclass 27, count 2 2006.189.08:25:01.81#ibcon#read 3, iclass 27, count 2 2006.189.08:25:01.81#ibcon#about to read 4, iclass 27, count 2 2006.189.08:25:01.81#ibcon#read 4, iclass 27, count 2 2006.189.08:25:01.81#ibcon#about to read 5, iclass 27, count 2 2006.189.08:25:01.81#ibcon#read 5, iclass 27, count 2 2006.189.08:25:01.81#ibcon#about to read 6, iclass 27, count 2 2006.189.08:25:01.81#ibcon#read 6, iclass 27, count 2 2006.189.08:25:01.81#ibcon#end of sib2, iclass 27, count 2 2006.189.08:25:01.81#ibcon#*mode == 0, iclass 27, count 2 2006.189.08:25:01.81#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.189.08:25:01.81#ibcon#[27=AT04-04\r\n] 2006.189.08:25:01.81#ibcon#*before write, iclass 27, count 2 2006.189.08:25:01.81#ibcon#enter sib2, iclass 27, count 2 2006.189.08:25:01.81#ibcon#flushed, iclass 27, count 2 2006.189.08:25:01.81#ibcon#about to write, iclass 27, count 2 2006.189.08:25:01.81#ibcon#wrote, iclass 27, count 2 2006.189.08:25:01.81#ibcon#about to read 3, iclass 27, count 2 2006.189.08:25:01.84#ibcon#read 3, iclass 27, count 2 2006.189.08:25:01.84#ibcon#about to read 4, iclass 27, count 2 2006.189.08:25:01.84#ibcon#read 4, iclass 27, count 2 2006.189.08:25:01.84#ibcon#about to read 5, iclass 27, count 2 2006.189.08:25:01.84#ibcon#read 5, iclass 27, count 2 2006.189.08:25:01.84#ibcon#about to read 6, iclass 27, count 2 2006.189.08:25:01.84#ibcon#read 6, iclass 27, count 2 2006.189.08:25:01.84#ibcon#end of sib2, iclass 27, count 2 2006.189.08:25:01.84#ibcon#*after write, iclass 27, count 2 2006.189.08:25:01.84#ibcon#*before return 0, iclass 27, count 2 2006.189.08:25:01.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:25:01.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.189.08:25:01.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.189.08:25:01.84#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:01.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:25:01.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:25:01.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:25:01.96#ibcon#enter wrdev, iclass 27, count 0 2006.189.08:25:01.96#ibcon#first serial, iclass 27, count 0 2006.189.08:25:01.96#ibcon#enter sib2, iclass 27, count 0 2006.189.08:25:01.96#ibcon#flushed, iclass 27, count 0 2006.189.08:25:01.96#ibcon#about to write, iclass 27, count 0 2006.189.08:25:01.96#ibcon#wrote, iclass 27, count 0 2006.189.08:25:01.96#ibcon#about to read 3, iclass 27, count 0 2006.189.08:25:01.98#ibcon#read 3, iclass 27, count 0 2006.189.08:25:01.98#ibcon#about to read 4, iclass 27, count 0 2006.189.08:25:01.98#ibcon#read 4, iclass 27, count 0 2006.189.08:25:01.98#ibcon#about to read 5, iclass 27, count 0 2006.189.08:25:01.98#ibcon#read 5, iclass 27, count 0 2006.189.08:25:01.98#ibcon#about to read 6, iclass 27, count 0 2006.189.08:25:01.98#ibcon#read 6, iclass 27, count 0 2006.189.08:25:01.98#ibcon#end of sib2, iclass 27, count 0 2006.189.08:25:01.98#ibcon#*mode == 0, iclass 27, count 0 2006.189.08:25:01.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.189.08:25:01.98#ibcon#[27=USB\r\n] 2006.189.08:25:01.98#ibcon#*before write, iclass 27, count 0 2006.189.08:25:01.98#ibcon#enter sib2, iclass 27, count 0 2006.189.08:25:01.98#ibcon#flushed, iclass 27, count 0 2006.189.08:25:01.98#ibcon#about to write, iclass 27, count 0 2006.189.08:25:01.98#ibcon#wrote, iclass 27, count 0 2006.189.08:25:01.98#ibcon#about to read 3, iclass 27, count 0 2006.189.08:25:02.01#ibcon#read 3, iclass 27, count 0 2006.189.08:25:02.01#ibcon#about to read 4, iclass 27, count 0 2006.189.08:25:02.01#ibcon#read 4, iclass 27, count 0 2006.189.08:25:02.01#ibcon#about to read 5, iclass 27, count 0 2006.189.08:25:02.01#ibcon#read 5, iclass 27, count 0 2006.189.08:25:02.01#ibcon#about to read 6, iclass 27, count 0 2006.189.08:25:02.01#ibcon#read 6, iclass 27, count 0 2006.189.08:25:02.01#ibcon#end of sib2, iclass 27, count 0 2006.189.08:25:02.01#ibcon#*after write, iclass 27, count 0 2006.189.08:25:02.01#ibcon#*before return 0, iclass 27, count 0 2006.189.08:25:02.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:25:02.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.189.08:25:02.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.189.08:25:02.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.189.08:25:02.01$vc4f8/vblo=5,744.99 2006.189.08:25:02.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.189.08:25:02.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.189.08:25:02.01#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:02.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:25:02.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:25:02.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:25:02.01#ibcon#enter wrdev, iclass 29, count 0 2006.189.08:25:02.01#ibcon#first serial, iclass 29, count 0 2006.189.08:25:02.01#ibcon#enter sib2, iclass 29, count 0 2006.189.08:25:02.01#ibcon#flushed, iclass 29, count 0 2006.189.08:25:02.01#ibcon#about to write, iclass 29, count 0 2006.189.08:25:02.01#ibcon#wrote, iclass 29, count 0 2006.189.08:25:02.01#ibcon#about to read 3, iclass 29, count 0 2006.189.08:25:02.03#ibcon#read 3, iclass 29, count 0 2006.189.08:25:02.03#ibcon#about to read 4, iclass 29, count 0 2006.189.08:25:02.03#ibcon#read 4, iclass 29, count 0 2006.189.08:25:02.03#ibcon#about to read 5, iclass 29, count 0 2006.189.08:25:02.03#ibcon#read 5, iclass 29, count 0 2006.189.08:25:02.03#ibcon#about to read 6, iclass 29, count 0 2006.189.08:25:02.03#ibcon#read 6, iclass 29, count 0 2006.189.08:25:02.03#ibcon#end of sib2, iclass 29, count 0 2006.189.08:25:02.03#ibcon#*mode == 0, iclass 29, count 0 2006.189.08:25:02.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.189.08:25:02.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:25:02.03#ibcon#*before write, iclass 29, count 0 2006.189.08:25:02.03#ibcon#enter sib2, iclass 29, count 0 2006.189.08:25:02.03#ibcon#flushed, iclass 29, count 0 2006.189.08:25:02.03#ibcon#about to write, iclass 29, count 0 2006.189.08:25:02.03#ibcon#wrote, iclass 29, count 0 2006.189.08:25:02.03#ibcon#about to read 3, iclass 29, count 0 2006.189.08:25:02.07#ibcon#read 3, iclass 29, count 0 2006.189.08:25:02.07#ibcon#about to read 4, iclass 29, count 0 2006.189.08:25:02.07#ibcon#read 4, iclass 29, count 0 2006.189.08:25:02.07#ibcon#about to read 5, iclass 29, count 0 2006.189.08:25:02.07#ibcon#read 5, iclass 29, count 0 2006.189.08:25:02.07#ibcon#about to read 6, iclass 29, count 0 2006.189.08:25:02.07#ibcon#read 6, iclass 29, count 0 2006.189.08:25:02.07#ibcon#end of sib2, iclass 29, count 0 2006.189.08:25:02.07#ibcon#*after write, iclass 29, count 0 2006.189.08:25:02.07#ibcon#*before return 0, iclass 29, count 0 2006.189.08:25:02.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:25:02.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.189.08:25:02.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.189.08:25:02.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.189.08:25:02.07$vc4f8/vb=5,4 2006.189.08:25:02.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.189.08:25:02.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.189.08:25:02.07#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:02.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:25:02.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:25:02.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:25:02.13#ibcon#enter wrdev, iclass 31, count 2 2006.189.08:25:02.13#ibcon#first serial, iclass 31, count 2 2006.189.08:25:02.13#ibcon#enter sib2, iclass 31, count 2 2006.189.08:25:02.13#ibcon#flushed, iclass 31, count 2 2006.189.08:25:02.13#ibcon#about to write, iclass 31, count 2 2006.189.08:25:02.13#ibcon#wrote, iclass 31, count 2 2006.189.08:25:02.13#ibcon#about to read 3, iclass 31, count 2 2006.189.08:25:02.15#ibcon#read 3, iclass 31, count 2 2006.189.08:25:02.15#ibcon#about to read 4, iclass 31, count 2 2006.189.08:25:02.15#ibcon#read 4, iclass 31, count 2 2006.189.08:25:02.15#ibcon#about to read 5, iclass 31, count 2 2006.189.08:25:02.15#ibcon#read 5, iclass 31, count 2 2006.189.08:25:02.15#ibcon#about to read 6, iclass 31, count 2 2006.189.08:25:02.15#ibcon#read 6, iclass 31, count 2 2006.189.08:25:02.15#ibcon#end of sib2, iclass 31, count 2 2006.189.08:25:02.15#ibcon#*mode == 0, iclass 31, count 2 2006.189.08:25:02.15#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.189.08:25:02.15#ibcon#[27=AT05-04\r\n] 2006.189.08:25:02.15#ibcon#*before write, iclass 31, count 2 2006.189.08:25:02.15#ibcon#enter sib2, iclass 31, count 2 2006.189.08:25:02.15#ibcon#flushed, iclass 31, count 2 2006.189.08:25:02.15#ibcon#about to write, iclass 31, count 2 2006.189.08:25:02.15#ibcon#wrote, iclass 31, count 2 2006.189.08:25:02.15#ibcon#about to read 3, iclass 31, count 2 2006.189.08:25:02.18#ibcon#read 3, iclass 31, count 2 2006.189.08:25:02.18#ibcon#about to read 4, iclass 31, count 2 2006.189.08:25:02.18#ibcon#read 4, iclass 31, count 2 2006.189.08:25:02.18#ibcon#about to read 5, iclass 31, count 2 2006.189.08:25:02.18#ibcon#read 5, iclass 31, count 2 2006.189.08:25:02.18#ibcon#about to read 6, iclass 31, count 2 2006.189.08:25:02.18#ibcon#read 6, iclass 31, count 2 2006.189.08:25:02.18#ibcon#end of sib2, iclass 31, count 2 2006.189.08:25:02.18#ibcon#*after write, iclass 31, count 2 2006.189.08:25:02.18#ibcon#*before return 0, iclass 31, count 2 2006.189.08:25:02.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:25:02.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.189.08:25:02.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.189.08:25:02.18#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:02.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:25:02.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:25:02.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:25:02.30#ibcon#enter wrdev, iclass 31, count 0 2006.189.08:25:02.30#ibcon#first serial, iclass 31, count 0 2006.189.08:25:02.30#ibcon#enter sib2, iclass 31, count 0 2006.189.08:25:02.30#ibcon#flushed, iclass 31, count 0 2006.189.08:25:02.30#ibcon#about to write, iclass 31, count 0 2006.189.08:25:02.30#ibcon#wrote, iclass 31, count 0 2006.189.08:25:02.30#ibcon#about to read 3, iclass 31, count 0 2006.189.08:25:02.32#ibcon#read 3, iclass 31, count 0 2006.189.08:25:02.32#ibcon#about to read 4, iclass 31, count 0 2006.189.08:25:02.32#ibcon#read 4, iclass 31, count 0 2006.189.08:25:02.32#ibcon#about to read 5, iclass 31, count 0 2006.189.08:25:02.32#ibcon#read 5, iclass 31, count 0 2006.189.08:25:02.32#ibcon#about to read 6, iclass 31, count 0 2006.189.08:25:02.32#ibcon#read 6, iclass 31, count 0 2006.189.08:25:02.32#ibcon#end of sib2, iclass 31, count 0 2006.189.08:25:02.32#ibcon#*mode == 0, iclass 31, count 0 2006.189.08:25:02.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.189.08:25:02.32#ibcon#[27=USB\r\n] 2006.189.08:25:02.32#ibcon#*before write, iclass 31, count 0 2006.189.08:25:02.32#ibcon#enter sib2, iclass 31, count 0 2006.189.08:25:02.32#ibcon#flushed, iclass 31, count 0 2006.189.08:25:02.32#ibcon#about to write, iclass 31, count 0 2006.189.08:25:02.32#ibcon#wrote, iclass 31, count 0 2006.189.08:25:02.32#ibcon#about to read 3, iclass 31, count 0 2006.189.08:25:02.35#ibcon#read 3, iclass 31, count 0 2006.189.08:25:02.35#ibcon#about to read 4, iclass 31, count 0 2006.189.08:25:02.35#ibcon#read 4, iclass 31, count 0 2006.189.08:25:02.35#ibcon#about to read 5, iclass 31, count 0 2006.189.08:25:02.35#ibcon#read 5, iclass 31, count 0 2006.189.08:25:02.35#ibcon#about to read 6, iclass 31, count 0 2006.189.08:25:02.35#ibcon#read 6, iclass 31, count 0 2006.189.08:25:02.35#ibcon#end of sib2, iclass 31, count 0 2006.189.08:25:02.35#ibcon#*after write, iclass 31, count 0 2006.189.08:25:02.35#ibcon#*before return 0, iclass 31, count 0 2006.189.08:25:02.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:25:02.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.189.08:25:02.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.189.08:25:02.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.189.08:25:02.35$vc4f8/vblo=6,752.99 2006.189.08:25:02.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.189.08:25:02.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.189.08:25:02.35#ibcon#ireg 17 cls_cnt 0 2006.189.08:25:02.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:25:02.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:25:02.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:25:02.35#ibcon#enter wrdev, iclass 33, count 0 2006.189.08:25:02.35#ibcon#first serial, iclass 33, count 0 2006.189.08:25:02.35#ibcon#enter sib2, iclass 33, count 0 2006.189.08:25:02.35#ibcon#flushed, iclass 33, count 0 2006.189.08:25:02.35#ibcon#about to write, iclass 33, count 0 2006.189.08:25:02.35#ibcon#wrote, iclass 33, count 0 2006.189.08:25:02.35#ibcon#about to read 3, iclass 33, count 0 2006.189.08:25:02.37#ibcon#read 3, iclass 33, count 0 2006.189.08:25:02.37#ibcon#about to read 4, iclass 33, count 0 2006.189.08:25:02.37#ibcon#read 4, iclass 33, count 0 2006.189.08:25:02.37#ibcon#about to read 5, iclass 33, count 0 2006.189.08:25:02.37#ibcon#read 5, iclass 33, count 0 2006.189.08:25:02.37#ibcon#about to read 6, iclass 33, count 0 2006.189.08:25:02.37#ibcon#read 6, iclass 33, count 0 2006.189.08:25:02.37#ibcon#end of sib2, iclass 33, count 0 2006.189.08:25:02.37#ibcon#*mode == 0, iclass 33, count 0 2006.189.08:25:02.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.189.08:25:02.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:25:02.37#ibcon#*before write, iclass 33, count 0 2006.189.08:25:02.37#ibcon#enter sib2, iclass 33, count 0 2006.189.08:25:02.37#ibcon#flushed, iclass 33, count 0 2006.189.08:25:02.37#ibcon#about to write, iclass 33, count 0 2006.189.08:25:02.37#ibcon#wrote, iclass 33, count 0 2006.189.08:25:02.37#ibcon#about to read 3, iclass 33, count 0 2006.189.08:25:02.41#ibcon#read 3, iclass 33, count 0 2006.189.08:25:02.41#ibcon#about to read 4, iclass 33, count 0 2006.189.08:25:02.41#ibcon#read 4, iclass 33, count 0 2006.189.08:25:02.41#ibcon#about to read 5, iclass 33, count 0 2006.189.08:25:02.41#ibcon#read 5, iclass 33, count 0 2006.189.08:25:02.41#ibcon#about to read 6, iclass 33, count 0 2006.189.08:25:02.41#ibcon#read 6, iclass 33, count 0 2006.189.08:25:02.41#ibcon#end of sib2, iclass 33, count 0 2006.189.08:25:02.41#ibcon#*after write, iclass 33, count 0 2006.189.08:25:02.41#ibcon#*before return 0, iclass 33, count 0 2006.189.08:25:02.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:25:02.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.189.08:25:02.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.189.08:25:02.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.189.08:25:02.41$vc4f8/vb=6,4 2006.189.08:25:02.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.189.08:25:02.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.189.08:25:02.41#ibcon#ireg 11 cls_cnt 2 2006.189.08:25:02.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:25:02.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:25:02.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:25:02.47#ibcon#enter wrdev, iclass 35, count 2 2006.189.08:25:02.47#ibcon#first serial, iclass 35, count 2 2006.189.08:25:02.47#ibcon#enter sib2, iclass 35, count 2 2006.189.08:25:02.47#ibcon#flushed, iclass 35, count 2 2006.189.08:25:02.47#ibcon#about to write, iclass 35, count 2 2006.189.08:25:02.47#ibcon#wrote, iclass 35, count 2 2006.189.08:25:02.47#ibcon#about to read 3, iclass 35, count 2 2006.189.08:25:02.49#ibcon#read 3, iclass 35, count 2 2006.189.08:25:02.49#ibcon#about to read 4, iclass 35, count 2 2006.189.08:25:02.49#ibcon#read 4, iclass 35, count 2 2006.189.08:25:02.49#ibcon#about to read 5, iclass 35, count 2 2006.189.08:25:02.49#ibcon#read 5, iclass 35, count 2 2006.189.08:25:02.49#ibcon#about to read 6, iclass 35, count 2 2006.189.08:25:02.49#ibcon#read 6, iclass 35, count 2 2006.189.08:25:02.49#ibcon#end of sib2, iclass 35, count 2 2006.189.08:25:02.49#ibcon#*mode == 0, iclass 35, count 2 2006.189.08:25:02.49#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.189.08:25:02.49#ibcon#[27=AT06-04\r\n] 2006.189.08:25:02.49#ibcon#*before write, iclass 35, count 2 2006.189.08:25:02.49#ibcon#enter sib2, iclass 35, count 2 2006.189.08:25:02.49#ibcon#flushed, iclass 35, count 2 2006.189.08:25:02.49#ibcon#about to write, iclass 35, count 2 2006.189.08:25:02.49#ibcon#wrote, iclass 35, count 2 2006.189.08:25:02.49#ibcon#about to read 3, iclass 35, count 2 2006.189.08:25:02.52#ibcon#read 3, iclass 35, count 2 2006.189.08:25:02.52#ibcon#about to read 4, iclass 35, count 2 2006.189.08:25:02.52#ibcon#read 4, iclass 35, count 2 2006.189.08:25:02.52#ibcon#about to read 5, iclass 35, count 2 2006.189.08:25:02.52#ibcon#read 5, iclass 35, count 2 2006.189.08:25:02.52#ibcon#about to read 6, iclass 35, count 2 2006.189.08:25:02.52#ibcon#read 6, iclass 35, count 2 2006.189.08:25:02.52#ibcon#end of sib2, iclass 35, count 2 2006.189.08:25:02.52#ibcon#*after write, iclass 35, count 2 2006.189.08:25:02.52#ibcon#*before return 0, iclass 35, count 2 2006.189.08:25:02.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:25:02.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.189.08:25:02.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.189.08:25:02.52#ibcon#ireg 7 cls_cnt 0 2006.189.08:25:02.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:25:02.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:25:02.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:25:02.64#ibcon#enter wrdev, iclass 35, count 0 2006.189.08:25:02.64#ibcon#first serial, iclass 35, count 0 2006.189.08:25:02.64#ibcon#enter sib2, iclass 35, count 0 2006.189.08:25:02.64#ibcon#flushed, iclass 35, count 0 2006.189.08:25:02.64#ibcon#about to write, iclass 35, count 0 2006.189.08:25:02.64#ibcon#wrote, iclass 35, count 0 2006.189.08:25:02.64#ibcon#about to read 3, iclass 35, count 0 2006.189.08:25:02.66#ibcon#read 3, iclass 35, count 0 2006.189.08:25:02.66#ibcon#about to read 4, iclass 35, count 0 2006.189.08:25:02.66#ibcon#read 4, iclass 35, count 0 2006.189.08:25:02.66#ibcon#about to read 5, iclass 35, count 0 2006.189.08:25:02.66#ibcon#read 5, iclass 35, count 0 2006.189.08:25:02.66#ibcon#about to read 6, iclass 35, count 0 2006.189.08:25:02.66#ibcon#read 6, iclass 35, count 0 2006.189.08:25:02.66#ibcon#end of sib2, iclass 35, count 0 2006.189.08:25:02.66#ibcon#*mode == 0, iclass 35, count 0 2006.189.08:25:02.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.189.08:25:02.66#ibcon#[27=USB\r\n] 2006.189.08:25:02.66#ibcon#*before write, iclass 35, count 0 2006.189.08:25:02.66#ibcon#enter sib2, iclass 35, count 0 2006.189.08:25:02.66#ibcon#flushed, iclass 35, count 0 2006.189.08:25:02.66#ibcon#about to write, iclass 35, count 0 2006.189.08:25:02.66#ibcon#wrote, iclass 35, count 0 2006.189.08:25:02.66#ibcon#about to read 3, iclass 35, count 0 2006.189.08:25:02.69#ibcon#read 3, iclass 35, count 0 2006.189.08:25:02.69#ibcon#about to read 4, iclass 35, count 0 2006.189.08:25:02.69#ibcon#read 4, iclass 35, count 0 2006.189.08:25:02.69#ibcon#about to read 5, iclass 35, count 0 2006.189.08:25:02.69#ibcon#read 5, iclass 35, count 0 2006.189.08:25:02.69#ibcon#about to read 6, iclass 35, count 0 2006.189.08:25:02.69#ibcon#read 6, iclass 35, count 0 2006.189.08:25:02.69#ibcon#end of sib2, iclass 35, count 0 2006.189.08:25:02.69#ibcon#*after write, iclass 35, count 0 2006.189.08:25:02.69#ibcon#*before return 0, iclass 35, count 0 2006.189.08:25:02.69#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:25:02.69#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.189.08:25:02.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.189.08:25:02.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.189.08:25:02.69$vc4f8/vabw=wide 2006.189.08:25:02.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.189.08:25:02.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.189.08:25:02.69#ibcon#ireg 8 cls_cnt 0 2006.189.08:25:02.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:25:02.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:25:02.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:25:02.69#ibcon#enter wrdev, iclass 37, count 0 2006.189.08:25:02.69#ibcon#first serial, iclass 37, count 0 2006.189.08:25:02.69#ibcon#enter sib2, iclass 37, count 0 2006.189.08:25:02.69#ibcon#flushed, iclass 37, count 0 2006.189.08:25:02.69#ibcon#about to write, iclass 37, count 0 2006.189.08:25:02.69#ibcon#wrote, iclass 37, count 0 2006.189.08:25:02.69#ibcon#about to read 3, iclass 37, count 0 2006.189.08:25:02.71#ibcon#read 3, iclass 37, count 0 2006.189.08:25:02.71#ibcon#about to read 4, iclass 37, count 0 2006.189.08:25:02.71#ibcon#read 4, iclass 37, count 0 2006.189.08:25:02.71#ibcon#about to read 5, iclass 37, count 0 2006.189.08:25:02.71#ibcon#read 5, iclass 37, count 0 2006.189.08:25:02.71#ibcon#about to read 6, iclass 37, count 0 2006.189.08:25:02.71#ibcon#read 6, iclass 37, count 0 2006.189.08:25:02.71#ibcon#end of sib2, iclass 37, count 0 2006.189.08:25:02.71#ibcon#*mode == 0, iclass 37, count 0 2006.189.08:25:02.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.189.08:25:02.71#ibcon#[25=BW32\r\n] 2006.189.08:25:02.71#ibcon#*before write, iclass 37, count 0 2006.189.08:25:02.71#ibcon#enter sib2, iclass 37, count 0 2006.189.08:25:02.71#ibcon#flushed, iclass 37, count 0 2006.189.08:25:02.71#ibcon#about to write, iclass 37, count 0 2006.189.08:25:02.71#ibcon#wrote, iclass 37, count 0 2006.189.08:25:02.71#ibcon#about to read 3, iclass 37, count 0 2006.189.08:25:02.74#ibcon#read 3, iclass 37, count 0 2006.189.08:25:02.74#ibcon#about to read 4, iclass 37, count 0 2006.189.08:25:02.74#ibcon#read 4, iclass 37, count 0 2006.189.08:25:02.74#ibcon#about to read 5, iclass 37, count 0 2006.189.08:25:02.74#ibcon#read 5, iclass 37, count 0 2006.189.08:25:02.74#ibcon#about to read 6, iclass 37, count 0 2006.189.08:25:02.74#ibcon#read 6, iclass 37, count 0 2006.189.08:25:02.74#ibcon#end of sib2, iclass 37, count 0 2006.189.08:25:02.74#ibcon#*after write, iclass 37, count 0 2006.189.08:25:02.74#ibcon#*before return 0, iclass 37, count 0 2006.189.08:25:02.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:25:02.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.189.08:25:02.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.189.08:25:02.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.189.08:25:02.74$vc4f8/vbbw=wide 2006.189.08:25:02.74#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.189.08:25:02.74#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.189.08:25:02.74#ibcon#ireg 8 cls_cnt 0 2006.189.08:25:02.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:25:02.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:25:02.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:25:02.81#ibcon#enter wrdev, iclass 39, count 0 2006.189.08:25:02.81#ibcon#first serial, iclass 39, count 0 2006.189.08:25:02.81#ibcon#enter sib2, iclass 39, count 0 2006.189.08:25:02.81#ibcon#flushed, iclass 39, count 0 2006.189.08:25:02.81#ibcon#about to write, iclass 39, count 0 2006.189.08:25:02.81#ibcon#wrote, iclass 39, count 0 2006.189.08:25:02.81#ibcon#about to read 3, iclass 39, count 0 2006.189.08:25:02.83#ibcon#read 3, iclass 39, count 0 2006.189.08:25:02.83#ibcon#about to read 4, iclass 39, count 0 2006.189.08:25:02.83#ibcon#read 4, iclass 39, count 0 2006.189.08:25:02.83#ibcon#about to read 5, iclass 39, count 0 2006.189.08:25:02.83#ibcon#read 5, iclass 39, count 0 2006.189.08:25:02.83#ibcon#about to read 6, iclass 39, count 0 2006.189.08:25:02.83#ibcon#read 6, iclass 39, count 0 2006.189.08:25:02.83#ibcon#end of sib2, iclass 39, count 0 2006.189.08:25:02.83#ibcon#*mode == 0, iclass 39, count 0 2006.189.08:25:02.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.189.08:25:02.83#ibcon#[27=BW32\r\n] 2006.189.08:25:02.83#ibcon#*before write, iclass 39, count 0 2006.189.08:25:02.83#ibcon#enter sib2, iclass 39, count 0 2006.189.08:25:02.83#ibcon#flushed, iclass 39, count 0 2006.189.08:25:02.83#ibcon#about to write, iclass 39, count 0 2006.189.08:25:02.83#ibcon#wrote, iclass 39, count 0 2006.189.08:25:02.83#ibcon#about to read 3, iclass 39, count 0 2006.189.08:25:02.86#ibcon#read 3, iclass 39, count 0 2006.189.08:25:02.86#ibcon#about to read 4, iclass 39, count 0 2006.189.08:25:02.86#ibcon#read 4, iclass 39, count 0 2006.189.08:25:02.86#ibcon#about to read 5, iclass 39, count 0 2006.189.08:25:02.86#ibcon#read 5, iclass 39, count 0 2006.189.08:25:02.86#ibcon#about to read 6, iclass 39, count 0 2006.189.08:25:02.86#ibcon#read 6, iclass 39, count 0 2006.189.08:25:02.86#ibcon#end of sib2, iclass 39, count 0 2006.189.08:25:02.86#ibcon#*after write, iclass 39, count 0 2006.189.08:25:02.86#ibcon#*before return 0, iclass 39, count 0 2006.189.08:25:02.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:25:02.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.189.08:25:02.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.189.08:25:02.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.189.08:25:02.86$4f8m12a/ifd4f 2006.189.08:25:02.86$ifd4f/lo= 2006.189.08:25:02.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:25:02.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:25:02.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:25:02.86$ifd4f/patch= 2006.189.08:25:02.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:25:02.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:25:02.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:25:02.86$4f8m12a/"form=m,16.000,1:2 2006.189.08:25:02.86$4f8m12a/"tpicd 2006.189.08:25:02.86$4f8m12a/echo=off 2006.189.08:25:02.86$4f8m12a/xlog=off 2006.189.08:25:02.86:!2006.189.08:25:30 2006.189.08:25:08.14#trakl#Source acquired 2006.189.08:25:09.14#flagr#flagr/antenna,acquired 2006.189.08:25:30.00:preob 2006.189.08:25:31.14/onsource/TRACKING 2006.189.08:25:31.14:!2006.189.08:25:40 2006.189.08:25:40.00:data_valid=on 2006.189.08:25:40.00:midob 2006.189.08:25:40.14/onsource/TRACKING 2006.189.08:25:40.14/wx/25.27,1009.2,92 2006.189.08:25:40.34/cable/+6.4574E-03 2006.189.08:25:41.43/va/01,08,usb,yes,29,30 2006.189.08:25:41.43/va/02,07,usb,yes,29,30 2006.189.08:25:41.43/va/03,06,usb,yes,30,30 2006.189.08:25:41.43/va/04,07,usb,yes,30,32 2006.189.08:25:41.43/va/05,07,usb,yes,32,33 2006.189.08:25:41.43/va/06,06,usb,yes,31,30 2006.189.08:25:41.43/va/07,06,usb,yes,31,31 2006.189.08:25:41.43/va/08,06,usb,yes,33,33 2006.189.08:25:41.66/valo/01,532.99,yes,locked 2006.189.08:25:41.66/valo/02,572.99,yes,locked 2006.189.08:25:41.66/valo/03,672.99,yes,locked 2006.189.08:25:41.66/valo/04,832.99,yes,locked 2006.189.08:25:41.66/valo/05,652.99,yes,locked 2006.189.08:25:41.66/valo/06,772.99,yes,locked 2006.189.08:25:41.66/valo/07,832.99,yes,locked 2006.189.08:25:41.66/valo/08,852.99,yes,locked 2006.189.08:25:42.75/vb/01,04,usb,yes,28,27 2006.189.08:25:42.75/vb/02,04,usb,yes,30,31 2006.189.08:25:42.75/vb/03,04,usb,yes,26,30 2006.189.08:25:42.75/vb/04,04,usb,yes,27,27 2006.189.08:25:42.75/vb/05,04,usb,yes,27,30 2006.189.08:25:42.75/vb/06,04,usb,yes,27,30 2006.189.08:25:42.75/vb/07,04,usb,yes,30,29 2006.189.08:25:42.75/vb/08,04,usb,yes,28,30 2006.189.08:25:42.98/vblo/01,632.99,yes,locked 2006.189.08:25:42.98/vblo/02,640.99,yes,locked 2006.189.08:25:42.98/vblo/03,656.99,yes,locked 2006.189.08:25:42.98/vblo/04,712.99,yes,locked 2006.189.08:25:42.98/vblo/05,744.99,yes,locked 2006.189.08:25:42.98/vblo/06,752.99,yes,locked 2006.189.08:25:42.98/vblo/07,734.99,yes,locked 2006.189.08:25:42.98/vblo/08,744.99,yes,locked 2006.189.08:25:43.13/vabw/8 2006.189.08:25:43.28/vbbw/8 2006.189.08:25:43.37/xfe/off,on,14.5 2006.189.08:25:43.75/ifatt/23,28,28,28 2006.189.08:25:44.08/fmout-gps/S +2.98E-07 2006.189.08:25:44.16:!2006.189.08:26:40 2006.189.08:26:40.01:data_valid=off 2006.189.08:26:40.02:postob 2006.189.08:26:40.17/cable/+6.4573E-03 2006.189.08:26:40.18/wx/25.26,1009.3,92 2006.189.08:26:41.08/fmout-gps/S +2.98E-07 2006.189.08:26:41.08:scan_name=189-0827,k06189,60 2006.189.08:26:41.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.189.08:26:41.13#flagr#flagr/antenna,new-source 2006.189.08:26:42.13:checkk5 2006.189.08:26:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.189.08:26:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.189.08:26:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.189.08:26:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.189.08:26:44.03/chk_obsdata//k5ts1/T1890825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:26:44.40/chk_obsdata//k5ts2/T1890825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:26:44.78/chk_obsdata//k5ts3/T1890825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:26:45.17/chk_obsdata//k5ts4/T1890825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.189.08:26:45.86/k5log//k5ts1_log_newline 2006.189.08:26:46.57/k5log//k5ts2_log_newline 2006.189.08:26:47.27/k5log//k5ts3_log_newline 2006.189.08:26:47.97/k5log//k5ts4_log_newline 2006.189.08:26:48.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:26:48.00:4f8m12a=3 2006.189.08:26:48.00$4f8m12a/echo=on 2006.189.08:26:48.00$4f8m12a/pcalon 2006.189.08:26:48.00$pcalon/"no phase cal control is implemented here 2006.189.08:26:48.00$4f8m12a/"tpicd=stop 2006.189.08:26:48.00$4f8m12a/vc4f8 2006.189.08:26:48.00$vc4f8/valo=1,532.99 2006.189.08:26:48.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.08:26:48.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.08:26:48.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:48.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:48.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:48.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:48.00#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:26:48.00#ibcon#first serial, iclass 14, count 0 2006.189.08:26:48.00#ibcon#enter sib2, iclass 14, count 0 2006.189.08:26:48.00#ibcon#flushed, iclass 14, count 0 2006.189.08:26:48.00#ibcon#about to write, iclass 14, count 0 2006.189.08:26:48.00#ibcon#wrote, iclass 14, count 0 2006.189.08:26:48.00#ibcon#about to read 3, iclass 14, count 0 2006.189.08:26:48.05#ibcon#read 3, iclass 14, count 0 2006.189.08:26:48.05#ibcon#about to read 4, iclass 14, count 0 2006.189.08:26:48.05#ibcon#read 4, iclass 14, count 0 2006.189.08:26:48.05#ibcon#about to read 5, iclass 14, count 0 2006.189.08:26:48.05#ibcon#read 5, iclass 14, count 0 2006.189.08:26:48.05#ibcon#about to read 6, iclass 14, count 0 2006.189.08:26:48.05#ibcon#read 6, iclass 14, count 0 2006.189.08:26:48.05#ibcon#end of sib2, iclass 14, count 0 2006.189.08:26:48.05#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:26:48.05#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:26:48.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.189.08:26:48.05#ibcon#*before write, iclass 14, count 0 2006.189.08:26:48.05#ibcon#enter sib2, iclass 14, count 0 2006.189.08:26:48.05#ibcon#flushed, iclass 14, count 0 2006.189.08:26:48.05#ibcon#about to write, iclass 14, count 0 2006.189.08:26:48.05#ibcon#wrote, iclass 14, count 0 2006.189.08:26:48.05#ibcon#about to read 3, iclass 14, count 0 2006.189.08:26:48.10#ibcon#read 3, iclass 14, count 0 2006.189.08:26:48.10#ibcon#about to read 4, iclass 14, count 0 2006.189.08:26:48.10#ibcon#read 4, iclass 14, count 0 2006.189.08:26:48.10#ibcon#about to read 5, iclass 14, count 0 2006.189.08:26:48.10#ibcon#read 5, iclass 14, count 0 2006.189.08:26:48.10#ibcon#about to read 6, iclass 14, count 0 2006.189.08:26:48.10#ibcon#read 6, iclass 14, count 0 2006.189.08:26:48.10#ibcon#end of sib2, iclass 14, count 0 2006.189.08:26:48.10#ibcon#*after write, iclass 14, count 0 2006.189.08:26:48.10#ibcon#*before return 0, iclass 14, count 0 2006.189.08:26:48.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:48.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:48.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:26:48.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:26:48.10$vc4f8/va=1,8 2006.189.08:26:48.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.08:26:48.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.08:26:48.10#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:48.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:48.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:48.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:48.10#ibcon#enter wrdev, iclass 16, count 2 2006.189.08:26:48.10#ibcon#first serial, iclass 16, count 2 2006.189.08:26:48.10#ibcon#enter sib2, iclass 16, count 2 2006.189.08:26:48.10#ibcon#flushed, iclass 16, count 2 2006.189.08:26:48.10#ibcon#about to write, iclass 16, count 2 2006.189.08:26:48.10#ibcon#wrote, iclass 16, count 2 2006.189.08:26:48.10#ibcon#about to read 3, iclass 16, count 2 2006.189.08:26:48.12#ibcon#read 3, iclass 16, count 2 2006.189.08:26:48.12#ibcon#about to read 4, iclass 16, count 2 2006.189.08:26:48.12#ibcon#read 4, iclass 16, count 2 2006.189.08:26:48.12#ibcon#about to read 5, iclass 16, count 2 2006.189.08:26:48.12#ibcon#read 5, iclass 16, count 2 2006.189.08:26:48.12#ibcon#about to read 6, iclass 16, count 2 2006.189.08:26:48.12#ibcon#read 6, iclass 16, count 2 2006.189.08:26:48.12#ibcon#end of sib2, iclass 16, count 2 2006.189.08:26:48.12#ibcon#*mode == 0, iclass 16, count 2 2006.189.08:26:48.12#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.08:26:48.12#ibcon#[25=AT01-08\r\n] 2006.189.08:26:48.12#ibcon#*before write, iclass 16, count 2 2006.189.08:26:48.12#ibcon#enter sib2, iclass 16, count 2 2006.189.08:26:48.12#ibcon#flushed, iclass 16, count 2 2006.189.08:26:48.12#ibcon#about to write, iclass 16, count 2 2006.189.08:26:48.12#ibcon#wrote, iclass 16, count 2 2006.189.08:26:48.12#ibcon#about to read 3, iclass 16, count 2 2006.189.08:26:48.15#ibcon#read 3, iclass 16, count 2 2006.189.08:26:48.15#ibcon#about to read 4, iclass 16, count 2 2006.189.08:26:48.15#ibcon#read 4, iclass 16, count 2 2006.189.08:26:48.15#ibcon#about to read 5, iclass 16, count 2 2006.189.08:26:48.15#ibcon#read 5, iclass 16, count 2 2006.189.08:26:48.15#ibcon#about to read 6, iclass 16, count 2 2006.189.08:26:48.15#ibcon#read 6, iclass 16, count 2 2006.189.08:26:48.15#ibcon#end of sib2, iclass 16, count 2 2006.189.08:26:48.15#ibcon#*after write, iclass 16, count 2 2006.189.08:26:48.15#ibcon#*before return 0, iclass 16, count 2 2006.189.08:26:48.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:48.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:48.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.08:26:48.15#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:48.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:48.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:48.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:48.27#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:26:48.27#ibcon#first serial, iclass 16, count 0 2006.189.08:26:48.27#ibcon#enter sib2, iclass 16, count 0 2006.189.08:26:48.27#ibcon#flushed, iclass 16, count 0 2006.189.08:26:48.27#ibcon#about to write, iclass 16, count 0 2006.189.08:26:48.27#ibcon#wrote, iclass 16, count 0 2006.189.08:26:48.27#ibcon#about to read 3, iclass 16, count 0 2006.189.08:26:48.29#ibcon#read 3, iclass 16, count 0 2006.189.08:26:48.29#ibcon#about to read 4, iclass 16, count 0 2006.189.08:26:48.29#ibcon#read 4, iclass 16, count 0 2006.189.08:26:48.29#ibcon#about to read 5, iclass 16, count 0 2006.189.08:26:48.29#ibcon#read 5, iclass 16, count 0 2006.189.08:26:48.29#ibcon#about to read 6, iclass 16, count 0 2006.189.08:26:48.29#ibcon#read 6, iclass 16, count 0 2006.189.08:26:48.29#ibcon#end of sib2, iclass 16, count 0 2006.189.08:26:48.29#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:26:48.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:26:48.29#ibcon#[25=USB\r\n] 2006.189.08:26:48.29#ibcon#*before write, iclass 16, count 0 2006.189.08:26:48.29#ibcon#enter sib2, iclass 16, count 0 2006.189.08:26:48.29#ibcon#flushed, iclass 16, count 0 2006.189.08:26:48.29#ibcon#about to write, iclass 16, count 0 2006.189.08:26:48.29#ibcon#wrote, iclass 16, count 0 2006.189.08:26:48.29#ibcon#about to read 3, iclass 16, count 0 2006.189.08:26:48.32#ibcon#read 3, iclass 16, count 0 2006.189.08:26:48.32#ibcon#about to read 4, iclass 16, count 0 2006.189.08:26:48.32#ibcon#read 4, iclass 16, count 0 2006.189.08:26:48.32#ibcon#about to read 5, iclass 16, count 0 2006.189.08:26:48.32#ibcon#read 5, iclass 16, count 0 2006.189.08:26:48.32#ibcon#about to read 6, iclass 16, count 0 2006.189.08:26:48.32#ibcon#read 6, iclass 16, count 0 2006.189.08:26:48.32#ibcon#end of sib2, iclass 16, count 0 2006.189.08:26:48.32#ibcon#*after write, iclass 16, count 0 2006.189.08:26:48.32#ibcon#*before return 0, iclass 16, count 0 2006.189.08:26:48.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:48.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:48.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:26:48.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:26:48.32$vc4f8/valo=2,572.99 2006.189.08:26:48.32#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.08:26:48.32#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.08:26:48.32#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:48.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:48.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:48.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:48.32#ibcon#enter wrdev, iclass 18, count 0 2006.189.08:26:48.32#ibcon#first serial, iclass 18, count 0 2006.189.08:26:48.32#ibcon#enter sib2, iclass 18, count 0 2006.189.08:26:48.32#ibcon#flushed, iclass 18, count 0 2006.189.08:26:48.32#ibcon#about to write, iclass 18, count 0 2006.189.08:26:48.32#ibcon#wrote, iclass 18, count 0 2006.189.08:26:48.32#ibcon#about to read 3, iclass 18, count 0 2006.189.08:26:48.34#ibcon#read 3, iclass 18, count 0 2006.189.08:26:48.34#ibcon#about to read 4, iclass 18, count 0 2006.189.08:26:48.34#ibcon#read 4, iclass 18, count 0 2006.189.08:26:48.34#ibcon#about to read 5, iclass 18, count 0 2006.189.08:26:48.34#ibcon#read 5, iclass 18, count 0 2006.189.08:26:48.34#ibcon#about to read 6, iclass 18, count 0 2006.189.08:26:48.34#ibcon#read 6, iclass 18, count 0 2006.189.08:26:48.34#ibcon#end of sib2, iclass 18, count 0 2006.189.08:26:48.34#ibcon#*mode == 0, iclass 18, count 0 2006.189.08:26:48.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.08:26:48.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.189.08:26:48.34#ibcon#*before write, iclass 18, count 0 2006.189.08:26:48.34#ibcon#enter sib2, iclass 18, count 0 2006.189.08:26:48.34#ibcon#flushed, iclass 18, count 0 2006.189.08:26:48.34#ibcon#about to write, iclass 18, count 0 2006.189.08:26:48.34#ibcon#wrote, iclass 18, count 0 2006.189.08:26:48.34#ibcon#about to read 3, iclass 18, count 0 2006.189.08:26:48.38#ibcon#read 3, iclass 18, count 0 2006.189.08:26:48.38#ibcon#about to read 4, iclass 18, count 0 2006.189.08:26:48.38#ibcon#read 4, iclass 18, count 0 2006.189.08:26:48.38#ibcon#about to read 5, iclass 18, count 0 2006.189.08:26:48.38#ibcon#read 5, iclass 18, count 0 2006.189.08:26:48.38#ibcon#about to read 6, iclass 18, count 0 2006.189.08:26:48.38#ibcon#read 6, iclass 18, count 0 2006.189.08:26:48.38#ibcon#end of sib2, iclass 18, count 0 2006.189.08:26:48.38#ibcon#*after write, iclass 18, count 0 2006.189.08:26:48.38#ibcon#*before return 0, iclass 18, count 0 2006.189.08:26:48.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:48.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:48.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.08:26:48.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.08:26:48.38$vc4f8/va=2,7 2006.189.08:26:48.38#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.08:26:48.38#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.08:26:48.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:48.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:48.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:48.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:48.44#ibcon#enter wrdev, iclass 20, count 2 2006.189.08:26:48.44#ibcon#first serial, iclass 20, count 2 2006.189.08:26:48.44#ibcon#enter sib2, iclass 20, count 2 2006.189.08:26:48.44#ibcon#flushed, iclass 20, count 2 2006.189.08:26:48.44#ibcon#about to write, iclass 20, count 2 2006.189.08:26:48.44#ibcon#wrote, iclass 20, count 2 2006.189.08:26:48.44#ibcon#about to read 3, iclass 20, count 2 2006.189.08:26:48.46#ibcon#read 3, iclass 20, count 2 2006.189.08:26:48.46#ibcon#about to read 4, iclass 20, count 2 2006.189.08:26:48.46#ibcon#read 4, iclass 20, count 2 2006.189.08:26:48.46#ibcon#about to read 5, iclass 20, count 2 2006.189.08:26:48.46#ibcon#read 5, iclass 20, count 2 2006.189.08:26:48.46#ibcon#about to read 6, iclass 20, count 2 2006.189.08:26:48.46#ibcon#read 6, iclass 20, count 2 2006.189.08:26:48.46#ibcon#end of sib2, iclass 20, count 2 2006.189.08:26:48.46#ibcon#*mode == 0, iclass 20, count 2 2006.189.08:26:48.46#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.08:26:48.46#ibcon#[25=AT02-07\r\n] 2006.189.08:26:48.46#ibcon#*before write, iclass 20, count 2 2006.189.08:26:48.46#ibcon#enter sib2, iclass 20, count 2 2006.189.08:26:48.46#ibcon#flushed, iclass 20, count 2 2006.189.08:26:48.46#ibcon#about to write, iclass 20, count 2 2006.189.08:26:48.46#ibcon#wrote, iclass 20, count 2 2006.189.08:26:48.46#ibcon#about to read 3, iclass 20, count 2 2006.189.08:26:48.49#ibcon#read 3, iclass 20, count 2 2006.189.08:26:48.49#ibcon#about to read 4, iclass 20, count 2 2006.189.08:26:48.49#ibcon#read 4, iclass 20, count 2 2006.189.08:26:48.49#ibcon#about to read 5, iclass 20, count 2 2006.189.08:26:48.49#ibcon#read 5, iclass 20, count 2 2006.189.08:26:48.49#ibcon#about to read 6, iclass 20, count 2 2006.189.08:26:48.49#ibcon#read 6, iclass 20, count 2 2006.189.08:26:48.49#ibcon#end of sib2, iclass 20, count 2 2006.189.08:26:48.49#ibcon#*after write, iclass 20, count 2 2006.189.08:26:48.49#ibcon#*before return 0, iclass 20, count 2 2006.189.08:26:48.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:48.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:48.49#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.08:26:48.49#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:48.49#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:48.61#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:48.61#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:48.61#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:26:48.61#ibcon#first serial, iclass 20, count 0 2006.189.08:26:48.61#ibcon#enter sib2, iclass 20, count 0 2006.189.08:26:48.61#ibcon#flushed, iclass 20, count 0 2006.189.08:26:48.61#ibcon#about to write, iclass 20, count 0 2006.189.08:26:48.61#ibcon#wrote, iclass 20, count 0 2006.189.08:26:48.61#ibcon#about to read 3, iclass 20, count 0 2006.189.08:26:48.63#ibcon#read 3, iclass 20, count 0 2006.189.08:26:48.63#ibcon#about to read 4, iclass 20, count 0 2006.189.08:26:48.63#ibcon#read 4, iclass 20, count 0 2006.189.08:26:48.63#ibcon#about to read 5, iclass 20, count 0 2006.189.08:26:48.63#ibcon#read 5, iclass 20, count 0 2006.189.08:26:48.63#ibcon#about to read 6, iclass 20, count 0 2006.189.08:26:48.63#ibcon#read 6, iclass 20, count 0 2006.189.08:26:48.63#ibcon#end of sib2, iclass 20, count 0 2006.189.08:26:48.63#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:26:48.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:26:48.63#ibcon#[25=USB\r\n] 2006.189.08:26:48.63#ibcon#*before write, iclass 20, count 0 2006.189.08:26:48.63#ibcon#enter sib2, iclass 20, count 0 2006.189.08:26:48.63#ibcon#flushed, iclass 20, count 0 2006.189.08:26:48.63#ibcon#about to write, iclass 20, count 0 2006.189.08:26:48.63#ibcon#wrote, iclass 20, count 0 2006.189.08:26:48.63#ibcon#about to read 3, iclass 20, count 0 2006.189.08:26:48.66#ibcon#read 3, iclass 20, count 0 2006.189.08:26:48.66#ibcon#about to read 4, iclass 20, count 0 2006.189.08:26:48.66#ibcon#read 4, iclass 20, count 0 2006.189.08:26:48.66#ibcon#about to read 5, iclass 20, count 0 2006.189.08:26:48.66#ibcon#read 5, iclass 20, count 0 2006.189.08:26:48.66#ibcon#about to read 6, iclass 20, count 0 2006.189.08:26:48.66#ibcon#read 6, iclass 20, count 0 2006.189.08:26:48.66#ibcon#end of sib2, iclass 20, count 0 2006.189.08:26:48.66#ibcon#*after write, iclass 20, count 0 2006.189.08:26:48.66#ibcon#*before return 0, iclass 20, count 0 2006.189.08:26:48.66#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:48.66#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:48.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:26:48.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:26:48.66$vc4f8/valo=3,672.99 2006.189.08:26:48.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.08:26:48.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.08:26:48.66#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:48.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:48.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:48.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:48.66#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:26:48.66#ibcon#first serial, iclass 22, count 0 2006.189.08:26:48.66#ibcon#enter sib2, iclass 22, count 0 2006.189.08:26:48.66#ibcon#flushed, iclass 22, count 0 2006.189.08:26:48.66#ibcon#about to write, iclass 22, count 0 2006.189.08:26:48.66#ibcon#wrote, iclass 22, count 0 2006.189.08:26:48.66#ibcon#about to read 3, iclass 22, count 0 2006.189.08:26:48.68#ibcon#read 3, iclass 22, count 0 2006.189.08:26:48.68#ibcon#about to read 4, iclass 22, count 0 2006.189.08:26:48.68#ibcon#read 4, iclass 22, count 0 2006.189.08:26:48.68#ibcon#about to read 5, iclass 22, count 0 2006.189.08:26:48.68#ibcon#read 5, iclass 22, count 0 2006.189.08:26:48.68#ibcon#about to read 6, iclass 22, count 0 2006.189.08:26:48.68#ibcon#read 6, iclass 22, count 0 2006.189.08:26:48.68#ibcon#end of sib2, iclass 22, count 0 2006.189.08:26:48.68#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:26:48.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:26:48.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.189.08:26:48.68#ibcon#*before write, iclass 22, count 0 2006.189.08:26:48.68#ibcon#enter sib2, iclass 22, count 0 2006.189.08:26:48.68#ibcon#flushed, iclass 22, count 0 2006.189.08:26:48.68#ibcon#about to write, iclass 22, count 0 2006.189.08:26:48.68#ibcon#wrote, iclass 22, count 0 2006.189.08:26:48.68#ibcon#about to read 3, iclass 22, count 0 2006.189.08:26:48.72#ibcon#read 3, iclass 22, count 0 2006.189.08:26:48.72#ibcon#about to read 4, iclass 22, count 0 2006.189.08:26:48.72#ibcon#read 4, iclass 22, count 0 2006.189.08:26:48.72#ibcon#about to read 5, iclass 22, count 0 2006.189.08:26:48.72#ibcon#read 5, iclass 22, count 0 2006.189.08:26:48.72#ibcon#about to read 6, iclass 22, count 0 2006.189.08:26:48.72#ibcon#read 6, iclass 22, count 0 2006.189.08:26:48.72#ibcon#end of sib2, iclass 22, count 0 2006.189.08:26:48.72#ibcon#*after write, iclass 22, count 0 2006.189.08:26:48.72#ibcon#*before return 0, iclass 22, count 0 2006.189.08:26:48.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:48.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:48.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:26:48.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:26:48.72$vc4f8/va=3,6 2006.189.08:26:48.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.08:26:48.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.08:26:48.72#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:48.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:48.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:48.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:48.78#ibcon#enter wrdev, iclass 24, count 2 2006.189.08:26:48.78#ibcon#first serial, iclass 24, count 2 2006.189.08:26:48.78#ibcon#enter sib2, iclass 24, count 2 2006.189.08:26:48.78#ibcon#flushed, iclass 24, count 2 2006.189.08:26:48.78#ibcon#about to write, iclass 24, count 2 2006.189.08:26:48.78#ibcon#wrote, iclass 24, count 2 2006.189.08:26:48.78#ibcon#about to read 3, iclass 24, count 2 2006.189.08:26:48.80#ibcon#read 3, iclass 24, count 2 2006.189.08:26:48.80#ibcon#about to read 4, iclass 24, count 2 2006.189.08:26:48.80#ibcon#read 4, iclass 24, count 2 2006.189.08:26:48.80#ibcon#about to read 5, iclass 24, count 2 2006.189.08:26:48.80#ibcon#read 5, iclass 24, count 2 2006.189.08:26:48.80#ibcon#about to read 6, iclass 24, count 2 2006.189.08:26:48.80#ibcon#read 6, iclass 24, count 2 2006.189.08:26:48.80#ibcon#end of sib2, iclass 24, count 2 2006.189.08:26:48.80#ibcon#*mode == 0, iclass 24, count 2 2006.189.08:26:48.80#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.08:26:48.80#ibcon#[25=AT03-06\r\n] 2006.189.08:26:48.80#ibcon#*before write, iclass 24, count 2 2006.189.08:26:48.80#ibcon#enter sib2, iclass 24, count 2 2006.189.08:26:48.80#ibcon#flushed, iclass 24, count 2 2006.189.08:26:48.80#ibcon#about to write, iclass 24, count 2 2006.189.08:26:48.80#ibcon#wrote, iclass 24, count 2 2006.189.08:26:48.80#ibcon#about to read 3, iclass 24, count 2 2006.189.08:26:48.83#ibcon#read 3, iclass 24, count 2 2006.189.08:26:48.83#ibcon#about to read 4, iclass 24, count 2 2006.189.08:26:48.83#ibcon#read 4, iclass 24, count 2 2006.189.08:26:48.83#ibcon#about to read 5, iclass 24, count 2 2006.189.08:26:48.83#ibcon#read 5, iclass 24, count 2 2006.189.08:26:48.83#ibcon#about to read 6, iclass 24, count 2 2006.189.08:26:48.83#ibcon#read 6, iclass 24, count 2 2006.189.08:26:48.83#ibcon#end of sib2, iclass 24, count 2 2006.189.08:26:48.83#ibcon#*after write, iclass 24, count 2 2006.189.08:26:48.83#ibcon#*before return 0, iclass 24, count 2 2006.189.08:26:48.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:48.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:48.83#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.08:26:48.83#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:48.83#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:48.95#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:48.95#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:48.95#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:26:48.95#ibcon#first serial, iclass 24, count 0 2006.189.08:26:48.95#ibcon#enter sib2, iclass 24, count 0 2006.189.08:26:48.95#ibcon#flushed, iclass 24, count 0 2006.189.08:26:48.95#ibcon#about to write, iclass 24, count 0 2006.189.08:26:48.95#ibcon#wrote, iclass 24, count 0 2006.189.08:26:48.95#ibcon#about to read 3, iclass 24, count 0 2006.189.08:26:48.97#ibcon#read 3, iclass 24, count 0 2006.189.08:26:48.97#ibcon#about to read 4, iclass 24, count 0 2006.189.08:26:48.97#ibcon#read 4, iclass 24, count 0 2006.189.08:26:48.97#ibcon#about to read 5, iclass 24, count 0 2006.189.08:26:48.97#ibcon#read 5, iclass 24, count 0 2006.189.08:26:48.97#ibcon#about to read 6, iclass 24, count 0 2006.189.08:26:48.97#ibcon#read 6, iclass 24, count 0 2006.189.08:26:48.97#ibcon#end of sib2, iclass 24, count 0 2006.189.08:26:48.97#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:26:48.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:26:48.97#ibcon#[25=USB\r\n] 2006.189.08:26:48.97#ibcon#*before write, iclass 24, count 0 2006.189.08:26:48.97#ibcon#enter sib2, iclass 24, count 0 2006.189.08:26:48.97#ibcon#flushed, iclass 24, count 0 2006.189.08:26:48.97#ibcon#about to write, iclass 24, count 0 2006.189.08:26:48.97#ibcon#wrote, iclass 24, count 0 2006.189.08:26:48.97#ibcon#about to read 3, iclass 24, count 0 2006.189.08:26:49.00#ibcon#read 3, iclass 24, count 0 2006.189.08:26:49.00#ibcon#about to read 4, iclass 24, count 0 2006.189.08:26:49.00#ibcon#read 4, iclass 24, count 0 2006.189.08:26:49.00#ibcon#about to read 5, iclass 24, count 0 2006.189.08:26:49.00#ibcon#read 5, iclass 24, count 0 2006.189.08:26:49.00#ibcon#about to read 6, iclass 24, count 0 2006.189.08:26:49.00#ibcon#read 6, iclass 24, count 0 2006.189.08:26:49.00#ibcon#end of sib2, iclass 24, count 0 2006.189.08:26:49.00#ibcon#*after write, iclass 24, count 0 2006.189.08:26:49.00#ibcon#*before return 0, iclass 24, count 0 2006.189.08:26:49.00#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:49.00#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:49.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:26:49.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:26:49.00$vc4f8/valo=4,832.99 2006.189.08:26:49.00#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.08:26:49.00#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.08:26:49.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:49.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:49.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:49.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:49.00#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:26:49.00#ibcon#first serial, iclass 26, count 0 2006.189.08:26:49.00#ibcon#enter sib2, iclass 26, count 0 2006.189.08:26:49.00#ibcon#flushed, iclass 26, count 0 2006.189.08:26:49.00#ibcon#about to write, iclass 26, count 0 2006.189.08:26:49.00#ibcon#wrote, iclass 26, count 0 2006.189.08:26:49.00#ibcon#about to read 3, iclass 26, count 0 2006.189.08:26:49.02#ibcon#read 3, iclass 26, count 0 2006.189.08:26:49.02#ibcon#about to read 4, iclass 26, count 0 2006.189.08:26:49.02#ibcon#read 4, iclass 26, count 0 2006.189.08:26:49.02#ibcon#about to read 5, iclass 26, count 0 2006.189.08:26:49.02#ibcon#read 5, iclass 26, count 0 2006.189.08:26:49.02#ibcon#about to read 6, iclass 26, count 0 2006.189.08:26:49.02#ibcon#read 6, iclass 26, count 0 2006.189.08:26:49.02#ibcon#end of sib2, iclass 26, count 0 2006.189.08:26:49.02#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:26:49.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:26:49.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.189.08:26:49.02#ibcon#*before write, iclass 26, count 0 2006.189.08:26:49.02#ibcon#enter sib2, iclass 26, count 0 2006.189.08:26:49.02#ibcon#flushed, iclass 26, count 0 2006.189.08:26:49.02#ibcon#about to write, iclass 26, count 0 2006.189.08:26:49.02#ibcon#wrote, iclass 26, count 0 2006.189.08:26:49.02#ibcon#about to read 3, iclass 26, count 0 2006.189.08:26:49.06#ibcon#read 3, iclass 26, count 0 2006.189.08:26:49.06#ibcon#about to read 4, iclass 26, count 0 2006.189.08:26:49.06#ibcon#read 4, iclass 26, count 0 2006.189.08:26:49.06#ibcon#about to read 5, iclass 26, count 0 2006.189.08:26:49.06#ibcon#read 5, iclass 26, count 0 2006.189.08:26:49.06#ibcon#about to read 6, iclass 26, count 0 2006.189.08:26:49.06#ibcon#read 6, iclass 26, count 0 2006.189.08:26:49.06#ibcon#end of sib2, iclass 26, count 0 2006.189.08:26:49.06#ibcon#*after write, iclass 26, count 0 2006.189.08:26:49.06#ibcon#*before return 0, iclass 26, count 0 2006.189.08:26:49.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:49.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:49.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:26:49.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:26:49.06$vc4f8/va=4,7 2006.189.08:26:49.06#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.08:26:49.06#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.08:26:49.06#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:49.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:49.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:49.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:49.12#ibcon#enter wrdev, iclass 28, count 2 2006.189.08:26:49.12#ibcon#first serial, iclass 28, count 2 2006.189.08:26:49.12#ibcon#enter sib2, iclass 28, count 2 2006.189.08:26:49.12#ibcon#flushed, iclass 28, count 2 2006.189.08:26:49.12#ibcon#about to write, iclass 28, count 2 2006.189.08:26:49.12#ibcon#wrote, iclass 28, count 2 2006.189.08:26:49.12#ibcon#about to read 3, iclass 28, count 2 2006.189.08:26:49.14#ibcon#read 3, iclass 28, count 2 2006.189.08:26:49.14#ibcon#about to read 4, iclass 28, count 2 2006.189.08:26:49.14#ibcon#read 4, iclass 28, count 2 2006.189.08:26:49.14#ibcon#about to read 5, iclass 28, count 2 2006.189.08:26:49.14#ibcon#read 5, iclass 28, count 2 2006.189.08:26:49.14#ibcon#about to read 6, iclass 28, count 2 2006.189.08:26:49.14#ibcon#read 6, iclass 28, count 2 2006.189.08:26:49.14#ibcon#end of sib2, iclass 28, count 2 2006.189.08:26:49.14#ibcon#*mode == 0, iclass 28, count 2 2006.189.08:26:49.14#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.08:26:49.14#ibcon#[25=AT04-07\r\n] 2006.189.08:26:49.14#ibcon#*before write, iclass 28, count 2 2006.189.08:26:49.14#ibcon#enter sib2, iclass 28, count 2 2006.189.08:26:49.14#ibcon#flushed, iclass 28, count 2 2006.189.08:26:49.14#ibcon#about to write, iclass 28, count 2 2006.189.08:26:49.14#ibcon#wrote, iclass 28, count 2 2006.189.08:26:49.14#ibcon#about to read 3, iclass 28, count 2 2006.189.08:26:49.17#ibcon#read 3, iclass 28, count 2 2006.189.08:26:49.17#ibcon#about to read 4, iclass 28, count 2 2006.189.08:26:49.17#ibcon#read 4, iclass 28, count 2 2006.189.08:26:49.17#ibcon#about to read 5, iclass 28, count 2 2006.189.08:26:49.17#ibcon#read 5, iclass 28, count 2 2006.189.08:26:49.17#ibcon#about to read 6, iclass 28, count 2 2006.189.08:26:49.17#ibcon#read 6, iclass 28, count 2 2006.189.08:26:49.17#ibcon#end of sib2, iclass 28, count 2 2006.189.08:26:49.17#ibcon#*after write, iclass 28, count 2 2006.189.08:26:49.17#ibcon#*before return 0, iclass 28, count 2 2006.189.08:26:49.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:49.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:49.17#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.08:26:49.17#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:49.17#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:49.29#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:49.29#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:49.29#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:26:49.29#ibcon#first serial, iclass 28, count 0 2006.189.08:26:49.29#ibcon#enter sib2, iclass 28, count 0 2006.189.08:26:49.29#ibcon#flushed, iclass 28, count 0 2006.189.08:26:49.29#ibcon#about to write, iclass 28, count 0 2006.189.08:26:49.29#ibcon#wrote, iclass 28, count 0 2006.189.08:26:49.29#ibcon#about to read 3, iclass 28, count 0 2006.189.08:26:49.31#ibcon#read 3, iclass 28, count 0 2006.189.08:26:49.31#ibcon#about to read 4, iclass 28, count 0 2006.189.08:26:49.31#ibcon#read 4, iclass 28, count 0 2006.189.08:26:49.31#ibcon#about to read 5, iclass 28, count 0 2006.189.08:26:49.31#ibcon#read 5, iclass 28, count 0 2006.189.08:26:49.31#ibcon#about to read 6, iclass 28, count 0 2006.189.08:26:49.31#ibcon#read 6, iclass 28, count 0 2006.189.08:26:49.31#ibcon#end of sib2, iclass 28, count 0 2006.189.08:26:49.31#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:26:49.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:26:49.31#ibcon#[25=USB\r\n] 2006.189.08:26:49.31#ibcon#*before write, iclass 28, count 0 2006.189.08:26:49.31#ibcon#enter sib2, iclass 28, count 0 2006.189.08:26:49.31#ibcon#flushed, iclass 28, count 0 2006.189.08:26:49.31#ibcon#about to write, iclass 28, count 0 2006.189.08:26:49.31#ibcon#wrote, iclass 28, count 0 2006.189.08:26:49.31#ibcon#about to read 3, iclass 28, count 0 2006.189.08:26:49.34#ibcon#read 3, iclass 28, count 0 2006.189.08:26:49.34#ibcon#about to read 4, iclass 28, count 0 2006.189.08:26:49.34#ibcon#read 4, iclass 28, count 0 2006.189.08:26:49.34#ibcon#about to read 5, iclass 28, count 0 2006.189.08:26:49.34#ibcon#read 5, iclass 28, count 0 2006.189.08:26:49.34#ibcon#about to read 6, iclass 28, count 0 2006.189.08:26:49.34#ibcon#read 6, iclass 28, count 0 2006.189.08:26:49.34#ibcon#end of sib2, iclass 28, count 0 2006.189.08:26:49.34#ibcon#*after write, iclass 28, count 0 2006.189.08:26:49.34#ibcon#*before return 0, iclass 28, count 0 2006.189.08:26:49.34#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:49.34#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:49.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:26:49.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:26:49.34$vc4f8/valo=5,652.99 2006.189.08:26:49.34#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.08:26:49.34#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.08:26:49.34#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:49.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:49.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:49.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:49.34#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:26:49.34#ibcon#first serial, iclass 30, count 0 2006.189.08:26:49.34#ibcon#enter sib2, iclass 30, count 0 2006.189.08:26:49.34#ibcon#flushed, iclass 30, count 0 2006.189.08:26:49.34#ibcon#about to write, iclass 30, count 0 2006.189.08:26:49.34#ibcon#wrote, iclass 30, count 0 2006.189.08:26:49.34#ibcon#about to read 3, iclass 30, count 0 2006.189.08:26:49.36#ibcon#read 3, iclass 30, count 0 2006.189.08:26:49.36#ibcon#about to read 4, iclass 30, count 0 2006.189.08:26:49.36#ibcon#read 4, iclass 30, count 0 2006.189.08:26:49.36#ibcon#about to read 5, iclass 30, count 0 2006.189.08:26:49.36#ibcon#read 5, iclass 30, count 0 2006.189.08:26:49.36#ibcon#about to read 6, iclass 30, count 0 2006.189.08:26:49.36#ibcon#read 6, iclass 30, count 0 2006.189.08:26:49.36#ibcon#end of sib2, iclass 30, count 0 2006.189.08:26:49.36#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:26:49.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:26:49.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.189.08:26:49.36#ibcon#*before write, iclass 30, count 0 2006.189.08:26:49.36#ibcon#enter sib2, iclass 30, count 0 2006.189.08:26:49.36#ibcon#flushed, iclass 30, count 0 2006.189.08:26:49.36#ibcon#about to write, iclass 30, count 0 2006.189.08:26:49.36#ibcon#wrote, iclass 30, count 0 2006.189.08:26:49.36#ibcon#about to read 3, iclass 30, count 0 2006.189.08:26:49.40#ibcon#read 3, iclass 30, count 0 2006.189.08:26:49.40#ibcon#about to read 4, iclass 30, count 0 2006.189.08:26:49.40#ibcon#read 4, iclass 30, count 0 2006.189.08:26:49.40#ibcon#about to read 5, iclass 30, count 0 2006.189.08:26:49.40#ibcon#read 5, iclass 30, count 0 2006.189.08:26:49.40#ibcon#about to read 6, iclass 30, count 0 2006.189.08:26:49.40#ibcon#read 6, iclass 30, count 0 2006.189.08:26:49.40#ibcon#end of sib2, iclass 30, count 0 2006.189.08:26:49.40#ibcon#*after write, iclass 30, count 0 2006.189.08:26:49.40#ibcon#*before return 0, iclass 30, count 0 2006.189.08:26:49.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:49.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:49.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:26:49.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:26:49.40$vc4f8/va=5,7 2006.189.08:26:49.40#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.08:26:49.40#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.08:26:49.40#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:49.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:49.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:49.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:49.46#ibcon#enter wrdev, iclass 32, count 2 2006.189.08:26:49.46#ibcon#first serial, iclass 32, count 2 2006.189.08:26:49.46#ibcon#enter sib2, iclass 32, count 2 2006.189.08:26:49.46#ibcon#flushed, iclass 32, count 2 2006.189.08:26:49.46#ibcon#about to write, iclass 32, count 2 2006.189.08:26:49.46#ibcon#wrote, iclass 32, count 2 2006.189.08:26:49.46#ibcon#about to read 3, iclass 32, count 2 2006.189.08:26:49.48#ibcon#read 3, iclass 32, count 2 2006.189.08:26:49.48#ibcon#about to read 4, iclass 32, count 2 2006.189.08:26:49.48#ibcon#read 4, iclass 32, count 2 2006.189.08:26:49.48#ibcon#about to read 5, iclass 32, count 2 2006.189.08:26:49.48#ibcon#read 5, iclass 32, count 2 2006.189.08:26:49.48#ibcon#about to read 6, iclass 32, count 2 2006.189.08:26:49.48#ibcon#read 6, iclass 32, count 2 2006.189.08:26:49.48#ibcon#end of sib2, iclass 32, count 2 2006.189.08:26:49.48#ibcon#*mode == 0, iclass 32, count 2 2006.189.08:26:49.48#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.08:26:49.48#ibcon#[25=AT05-07\r\n] 2006.189.08:26:49.48#ibcon#*before write, iclass 32, count 2 2006.189.08:26:49.48#ibcon#enter sib2, iclass 32, count 2 2006.189.08:26:49.48#ibcon#flushed, iclass 32, count 2 2006.189.08:26:49.48#ibcon#about to write, iclass 32, count 2 2006.189.08:26:49.48#ibcon#wrote, iclass 32, count 2 2006.189.08:26:49.48#ibcon#about to read 3, iclass 32, count 2 2006.189.08:26:49.51#ibcon#read 3, iclass 32, count 2 2006.189.08:26:49.51#ibcon#about to read 4, iclass 32, count 2 2006.189.08:26:49.51#ibcon#read 4, iclass 32, count 2 2006.189.08:26:49.51#ibcon#about to read 5, iclass 32, count 2 2006.189.08:26:49.51#ibcon#read 5, iclass 32, count 2 2006.189.08:26:49.51#ibcon#about to read 6, iclass 32, count 2 2006.189.08:26:49.51#ibcon#read 6, iclass 32, count 2 2006.189.08:26:49.51#ibcon#end of sib2, iclass 32, count 2 2006.189.08:26:49.51#ibcon#*after write, iclass 32, count 2 2006.189.08:26:49.51#ibcon#*before return 0, iclass 32, count 2 2006.189.08:26:49.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:49.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:49.51#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.08:26:49.51#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:49.51#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:49.63#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:49.63#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:49.63#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:26:49.63#ibcon#first serial, iclass 32, count 0 2006.189.08:26:49.63#ibcon#enter sib2, iclass 32, count 0 2006.189.08:26:49.63#ibcon#flushed, iclass 32, count 0 2006.189.08:26:49.63#ibcon#about to write, iclass 32, count 0 2006.189.08:26:49.63#ibcon#wrote, iclass 32, count 0 2006.189.08:26:49.63#ibcon#about to read 3, iclass 32, count 0 2006.189.08:26:49.65#ibcon#read 3, iclass 32, count 0 2006.189.08:26:49.65#ibcon#about to read 4, iclass 32, count 0 2006.189.08:26:49.65#ibcon#read 4, iclass 32, count 0 2006.189.08:26:49.65#ibcon#about to read 5, iclass 32, count 0 2006.189.08:26:49.65#ibcon#read 5, iclass 32, count 0 2006.189.08:26:49.65#ibcon#about to read 6, iclass 32, count 0 2006.189.08:26:49.65#ibcon#read 6, iclass 32, count 0 2006.189.08:26:49.65#ibcon#end of sib2, iclass 32, count 0 2006.189.08:26:49.65#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:26:49.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:26:49.65#ibcon#[25=USB\r\n] 2006.189.08:26:49.65#ibcon#*before write, iclass 32, count 0 2006.189.08:26:49.65#ibcon#enter sib2, iclass 32, count 0 2006.189.08:26:49.65#ibcon#flushed, iclass 32, count 0 2006.189.08:26:49.65#ibcon#about to write, iclass 32, count 0 2006.189.08:26:49.65#ibcon#wrote, iclass 32, count 0 2006.189.08:26:49.65#ibcon#about to read 3, iclass 32, count 0 2006.189.08:26:49.68#ibcon#read 3, iclass 32, count 0 2006.189.08:26:49.68#ibcon#about to read 4, iclass 32, count 0 2006.189.08:26:49.68#ibcon#read 4, iclass 32, count 0 2006.189.08:26:49.68#ibcon#about to read 5, iclass 32, count 0 2006.189.08:26:49.68#ibcon#read 5, iclass 32, count 0 2006.189.08:26:49.68#ibcon#about to read 6, iclass 32, count 0 2006.189.08:26:49.68#ibcon#read 6, iclass 32, count 0 2006.189.08:26:49.68#ibcon#end of sib2, iclass 32, count 0 2006.189.08:26:49.68#ibcon#*after write, iclass 32, count 0 2006.189.08:26:49.68#ibcon#*before return 0, iclass 32, count 0 2006.189.08:26:49.68#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:49.68#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:49.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:26:49.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:26:49.68$vc4f8/valo=6,772.99 2006.189.08:26:49.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.08:26:49.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.08:26:49.68#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:49.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:49.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:49.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:49.68#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:26:49.68#ibcon#first serial, iclass 34, count 0 2006.189.08:26:49.68#ibcon#enter sib2, iclass 34, count 0 2006.189.08:26:49.68#ibcon#flushed, iclass 34, count 0 2006.189.08:26:49.68#ibcon#about to write, iclass 34, count 0 2006.189.08:26:49.68#ibcon#wrote, iclass 34, count 0 2006.189.08:26:49.68#ibcon#about to read 3, iclass 34, count 0 2006.189.08:26:49.70#ibcon#read 3, iclass 34, count 0 2006.189.08:26:49.70#ibcon#about to read 4, iclass 34, count 0 2006.189.08:26:49.70#ibcon#read 4, iclass 34, count 0 2006.189.08:26:49.70#ibcon#about to read 5, iclass 34, count 0 2006.189.08:26:49.70#ibcon#read 5, iclass 34, count 0 2006.189.08:26:49.70#ibcon#about to read 6, iclass 34, count 0 2006.189.08:26:49.70#ibcon#read 6, iclass 34, count 0 2006.189.08:26:49.70#ibcon#end of sib2, iclass 34, count 0 2006.189.08:26:49.70#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:26:49.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:26:49.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.189.08:26:49.70#ibcon#*before write, iclass 34, count 0 2006.189.08:26:49.70#ibcon#enter sib2, iclass 34, count 0 2006.189.08:26:49.70#ibcon#flushed, iclass 34, count 0 2006.189.08:26:49.70#ibcon#about to write, iclass 34, count 0 2006.189.08:26:49.70#ibcon#wrote, iclass 34, count 0 2006.189.08:26:49.70#ibcon#about to read 3, iclass 34, count 0 2006.189.08:26:49.74#ibcon#read 3, iclass 34, count 0 2006.189.08:26:49.74#ibcon#about to read 4, iclass 34, count 0 2006.189.08:26:49.74#ibcon#read 4, iclass 34, count 0 2006.189.08:26:49.74#ibcon#about to read 5, iclass 34, count 0 2006.189.08:26:49.74#ibcon#read 5, iclass 34, count 0 2006.189.08:26:49.74#ibcon#about to read 6, iclass 34, count 0 2006.189.08:26:49.74#ibcon#read 6, iclass 34, count 0 2006.189.08:26:49.74#ibcon#end of sib2, iclass 34, count 0 2006.189.08:26:49.74#ibcon#*after write, iclass 34, count 0 2006.189.08:26:49.74#ibcon#*before return 0, iclass 34, count 0 2006.189.08:26:49.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:49.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:49.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:26:49.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:26:49.74$vc4f8/va=6,6 2006.189.08:26:49.74#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.189.08:26:49.74#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.189.08:26:49.74#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:49.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:26:49.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:26:49.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:26:49.80#ibcon#enter wrdev, iclass 36, count 2 2006.189.08:26:49.80#ibcon#first serial, iclass 36, count 2 2006.189.08:26:49.80#ibcon#enter sib2, iclass 36, count 2 2006.189.08:26:49.80#ibcon#flushed, iclass 36, count 2 2006.189.08:26:49.80#ibcon#about to write, iclass 36, count 2 2006.189.08:26:49.80#ibcon#wrote, iclass 36, count 2 2006.189.08:26:49.80#ibcon#about to read 3, iclass 36, count 2 2006.189.08:26:49.82#ibcon#read 3, iclass 36, count 2 2006.189.08:26:49.82#ibcon#about to read 4, iclass 36, count 2 2006.189.08:26:49.82#ibcon#read 4, iclass 36, count 2 2006.189.08:26:49.82#ibcon#about to read 5, iclass 36, count 2 2006.189.08:26:49.82#ibcon#read 5, iclass 36, count 2 2006.189.08:26:49.82#ibcon#about to read 6, iclass 36, count 2 2006.189.08:26:49.82#ibcon#read 6, iclass 36, count 2 2006.189.08:26:49.82#ibcon#end of sib2, iclass 36, count 2 2006.189.08:26:49.82#ibcon#*mode == 0, iclass 36, count 2 2006.189.08:26:49.82#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.189.08:26:49.82#ibcon#[25=AT06-06\r\n] 2006.189.08:26:49.82#ibcon#*before write, iclass 36, count 2 2006.189.08:26:49.82#ibcon#enter sib2, iclass 36, count 2 2006.189.08:26:49.82#ibcon#flushed, iclass 36, count 2 2006.189.08:26:49.82#ibcon#about to write, iclass 36, count 2 2006.189.08:26:49.82#ibcon#wrote, iclass 36, count 2 2006.189.08:26:49.82#ibcon#about to read 3, iclass 36, count 2 2006.189.08:26:49.85#ibcon#read 3, iclass 36, count 2 2006.189.08:26:49.85#ibcon#about to read 4, iclass 36, count 2 2006.189.08:26:49.85#ibcon#read 4, iclass 36, count 2 2006.189.08:26:49.85#ibcon#about to read 5, iclass 36, count 2 2006.189.08:26:49.85#ibcon#read 5, iclass 36, count 2 2006.189.08:26:49.85#ibcon#about to read 6, iclass 36, count 2 2006.189.08:26:49.85#ibcon#read 6, iclass 36, count 2 2006.189.08:26:49.85#ibcon#end of sib2, iclass 36, count 2 2006.189.08:26:49.85#ibcon#*after write, iclass 36, count 2 2006.189.08:26:49.85#ibcon#*before return 0, iclass 36, count 2 2006.189.08:26:49.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:26:49.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.189.08:26:49.85#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.189.08:26:49.85#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:49.85#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:26:49.97#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:26:49.97#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:26:49.97#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:26:49.97#ibcon#first serial, iclass 36, count 0 2006.189.08:26:49.97#ibcon#enter sib2, iclass 36, count 0 2006.189.08:26:49.97#ibcon#flushed, iclass 36, count 0 2006.189.08:26:49.97#ibcon#about to write, iclass 36, count 0 2006.189.08:26:49.97#ibcon#wrote, iclass 36, count 0 2006.189.08:26:49.97#ibcon#about to read 3, iclass 36, count 0 2006.189.08:26:49.99#ibcon#read 3, iclass 36, count 0 2006.189.08:26:49.99#ibcon#about to read 4, iclass 36, count 0 2006.189.08:26:49.99#ibcon#read 4, iclass 36, count 0 2006.189.08:26:49.99#ibcon#about to read 5, iclass 36, count 0 2006.189.08:26:49.99#ibcon#read 5, iclass 36, count 0 2006.189.08:26:49.99#ibcon#about to read 6, iclass 36, count 0 2006.189.08:26:49.99#ibcon#read 6, iclass 36, count 0 2006.189.08:26:49.99#ibcon#end of sib2, iclass 36, count 0 2006.189.08:26:49.99#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:26:49.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:26:49.99#ibcon#[25=USB\r\n] 2006.189.08:26:49.99#ibcon#*before write, iclass 36, count 0 2006.189.08:26:49.99#ibcon#enter sib2, iclass 36, count 0 2006.189.08:26:49.99#ibcon#flushed, iclass 36, count 0 2006.189.08:26:49.99#ibcon#about to write, iclass 36, count 0 2006.189.08:26:49.99#ibcon#wrote, iclass 36, count 0 2006.189.08:26:49.99#ibcon#about to read 3, iclass 36, count 0 2006.189.08:26:50.02#ibcon#read 3, iclass 36, count 0 2006.189.08:26:50.02#ibcon#about to read 4, iclass 36, count 0 2006.189.08:26:50.02#ibcon#read 4, iclass 36, count 0 2006.189.08:26:50.02#ibcon#about to read 5, iclass 36, count 0 2006.189.08:26:50.02#ibcon#read 5, iclass 36, count 0 2006.189.08:26:50.02#ibcon#about to read 6, iclass 36, count 0 2006.189.08:26:50.02#ibcon#read 6, iclass 36, count 0 2006.189.08:26:50.02#ibcon#end of sib2, iclass 36, count 0 2006.189.08:26:50.02#ibcon#*after write, iclass 36, count 0 2006.189.08:26:50.02#ibcon#*before return 0, iclass 36, count 0 2006.189.08:26:50.02#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:26:50.02#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.189.08:26:50.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:26:50.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:26:50.02$vc4f8/valo=7,832.99 2006.189.08:26:50.02#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.189.08:26:50.02#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.189.08:26:50.02#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:50.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:26:50.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:26:50.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:26:50.02#ibcon#enter wrdev, iclass 38, count 0 2006.189.08:26:50.02#ibcon#first serial, iclass 38, count 0 2006.189.08:26:50.02#ibcon#enter sib2, iclass 38, count 0 2006.189.08:26:50.02#ibcon#flushed, iclass 38, count 0 2006.189.08:26:50.02#ibcon#about to write, iclass 38, count 0 2006.189.08:26:50.02#ibcon#wrote, iclass 38, count 0 2006.189.08:26:50.02#ibcon#about to read 3, iclass 38, count 0 2006.189.08:26:50.04#ibcon#read 3, iclass 38, count 0 2006.189.08:26:50.04#ibcon#about to read 4, iclass 38, count 0 2006.189.08:26:50.04#ibcon#read 4, iclass 38, count 0 2006.189.08:26:50.04#ibcon#about to read 5, iclass 38, count 0 2006.189.08:26:50.04#ibcon#read 5, iclass 38, count 0 2006.189.08:26:50.04#ibcon#about to read 6, iclass 38, count 0 2006.189.08:26:50.04#ibcon#read 6, iclass 38, count 0 2006.189.08:26:50.04#ibcon#end of sib2, iclass 38, count 0 2006.189.08:26:50.04#ibcon#*mode == 0, iclass 38, count 0 2006.189.08:26:50.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.189.08:26:50.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.189.08:26:50.04#ibcon#*before write, iclass 38, count 0 2006.189.08:26:50.04#ibcon#enter sib2, iclass 38, count 0 2006.189.08:26:50.04#ibcon#flushed, iclass 38, count 0 2006.189.08:26:50.04#ibcon#about to write, iclass 38, count 0 2006.189.08:26:50.04#ibcon#wrote, iclass 38, count 0 2006.189.08:26:50.04#ibcon#about to read 3, iclass 38, count 0 2006.189.08:26:50.08#ibcon#read 3, iclass 38, count 0 2006.189.08:26:50.08#ibcon#about to read 4, iclass 38, count 0 2006.189.08:26:50.08#ibcon#read 4, iclass 38, count 0 2006.189.08:26:50.08#ibcon#about to read 5, iclass 38, count 0 2006.189.08:26:50.08#ibcon#read 5, iclass 38, count 0 2006.189.08:26:50.08#ibcon#about to read 6, iclass 38, count 0 2006.189.08:26:50.08#ibcon#read 6, iclass 38, count 0 2006.189.08:26:50.08#ibcon#end of sib2, iclass 38, count 0 2006.189.08:26:50.08#ibcon#*after write, iclass 38, count 0 2006.189.08:26:50.08#ibcon#*before return 0, iclass 38, count 0 2006.189.08:26:50.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:26:50.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.189.08:26:50.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.189.08:26:50.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.189.08:26:50.08$vc4f8/va=7,6 2006.189.08:26:50.08#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.189.08:26:50.08#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.189.08:26:50.08#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:50.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:26:50.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:26:50.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:26:50.14#ibcon#enter wrdev, iclass 40, count 2 2006.189.08:26:50.14#ibcon#first serial, iclass 40, count 2 2006.189.08:26:50.14#ibcon#enter sib2, iclass 40, count 2 2006.189.08:26:50.14#ibcon#flushed, iclass 40, count 2 2006.189.08:26:50.14#ibcon#about to write, iclass 40, count 2 2006.189.08:26:50.14#ibcon#wrote, iclass 40, count 2 2006.189.08:26:50.14#ibcon#about to read 3, iclass 40, count 2 2006.189.08:26:50.16#ibcon#read 3, iclass 40, count 2 2006.189.08:26:50.16#ibcon#about to read 4, iclass 40, count 2 2006.189.08:26:50.16#ibcon#read 4, iclass 40, count 2 2006.189.08:26:50.16#ibcon#about to read 5, iclass 40, count 2 2006.189.08:26:50.16#ibcon#read 5, iclass 40, count 2 2006.189.08:26:50.16#ibcon#about to read 6, iclass 40, count 2 2006.189.08:26:50.16#ibcon#read 6, iclass 40, count 2 2006.189.08:26:50.16#ibcon#end of sib2, iclass 40, count 2 2006.189.08:26:50.16#ibcon#*mode == 0, iclass 40, count 2 2006.189.08:26:50.16#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.189.08:26:50.16#ibcon#[25=AT07-06\r\n] 2006.189.08:26:50.16#ibcon#*before write, iclass 40, count 2 2006.189.08:26:50.16#ibcon#enter sib2, iclass 40, count 2 2006.189.08:26:50.16#ibcon#flushed, iclass 40, count 2 2006.189.08:26:50.16#ibcon#about to write, iclass 40, count 2 2006.189.08:26:50.16#ibcon#wrote, iclass 40, count 2 2006.189.08:26:50.16#ibcon#about to read 3, iclass 40, count 2 2006.189.08:26:50.19#ibcon#read 3, iclass 40, count 2 2006.189.08:26:50.19#ibcon#about to read 4, iclass 40, count 2 2006.189.08:26:50.19#ibcon#read 4, iclass 40, count 2 2006.189.08:26:50.19#ibcon#about to read 5, iclass 40, count 2 2006.189.08:26:50.19#ibcon#read 5, iclass 40, count 2 2006.189.08:26:50.19#ibcon#about to read 6, iclass 40, count 2 2006.189.08:26:50.19#ibcon#read 6, iclass 40, count 2 2006.189.08:26:50.19#ibcon#end of sib2, iclass 40, count 2 2006.189.08:26:50.19#ibcon#*after write, iclass 40, count 2 2006.189.08:26:50.19#ibcon#*before return 0, iclass 40, count 2 2006.189.08:26:50.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:26:50.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.189.08:26:50.19#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.189.08:26:50.19#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:50.19#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:26:50.31#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:26:50.31#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:26:50.31#ibcon#enter wrdev, iclass 40, count 0 2006.189.08:26:50.31#ibcon#first serial, iclass 40, count 0 2006.189.08:26:50.31#ibcon#enter sib2, iclass 40, count 0 2006.189.08:26:50.31#ibcon#flushed, iclass 40, count 0 2006.189.08:26:50.31#ibcon#about to write, iclass 40, count 0 2006.189.08:26:50.31#ibcon#wrote, iclass 40, count 0 2006.189.08:26:50.31#ibcon#about to read 3, iclass 40, count 0 2006.189.08:26:50.33#ibcon#read 3, iclass 40, count 0 2006.189.08:26:50.33#ibcon#about to read 4, iclass 40, count 0 2006.189.08:26:50.33#ibcon#read 4, iclass 40, count 0 2006.189.08:26:50.33#ibcon#about to read 5, iclass 40, count 0 2006.189.08:26:50.33#ibcon#read 5, iclass 40, count 0 2006.189.08:26:50.33#ibcon#about to read 6, iclass 40, count 0 2006.189.08:26:50.33#ibcon#read 6, iclass 40, count 0 2006.189.08:26:50.33#ibcon#end of sib2, iclass 40, count 0 2006.189.08:26:50.33#ibcon#*mode == 0, iclass 40, count 0 2006.189.08:26:50.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.189.08:26:50.33#ibcon#[25=USB\r\n] 2006.189.08:26:50.33#ibcon#*before write, iclass 40, count 0 2006.189.08:26:50.33#ibcon#enter sib2, iclass 40, count 0 2006.189.08:26:50.33#ibcon#flushed, iclass 40, count 0 2006.189.08:26:50.33#ibcon#about to write, iclass 40, count 0 2006.189.08:26:50.33#ibcon#wrote, iclass 40, count 0 2006.189.08:26:50.33#ibcon#about to read 3, iclass 40, count 0 2006.189.08:26:50.36#ibcon#read 3, iclass 40, count 0 2006.189.08:26:50.36#ibcon#about to read 4, iclass 40, count 0 2006.189.08:26:50.36#ibcon#read 4, iclass 40, count 0 2006.189.08:26:50.36#ibcon#about to read 5, iclass 40, count 0 2006.189.08:26:50.36#ibcon#read 5, iclass 40, count 0 2006.189.08:26:50.36#ibcon#about to read 6, iclass 40, count 0 2006.189.08:26:50.36#ibcon#read 6, iclass 40, count 0 2006.189.08:26:50.36#ibcon#end of sib2, iclass 40, count 0 2006.189.08:26:50.36#ibcon#*after write, iclass 40, count 0 2006.189.08:26:50.36#ibcon#*before return 0, iclass 40, count 0 2006.189.08:26:50.36#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:26:50.36#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.189.08:26:50.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.189.08:26:50.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.189.08:26:50.36$vc4f8/valo=8,852.99 2006.189.08:26:50.36#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.189.08:26:50.36#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.189.08:26:50.36#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:50.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:26:50.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:26:50.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:26:50.36#ibcon#enter wrdev, iclass 4, count 0 2006.189.08:26:50.36#ibcon#first serial, iclass 4, count 0 2006.189.08:26:50.36#ibcon#enter sib2, iclass 4, count 0 2006.189.08:26:50.36#ibcon#flushed, iclass 4, count 0 2006.189.08:26:50.36#ibcon#about to write, iclass 4, count 0 2006.189.08:26:50.36#ibcon#wrote, iclass 4, count 0 2006.189.08:26:50.36#ibcon#about to read 3, iclass 4, count 0 2006.189.08:26:50.38#ibcon#read 3, iclass 4, count 0 2006.189.08:26:50.38#ibcon#about to read 4, iclass 4, count 0 2006.189.08:26:50.38#ibcon#read 4, iclass 4, count 0 2006.189.08:26:50.38#ibcon#about to read 5, iclass 4, count 0 2006.189.08:26:50.38#ibcon#read 5, iclass 4, count 0 2006.189.08:26:50.38#ibcon#about to read 6, iclass 4, count 0 2006.189.08:26:50.38#ibcon#read 6, iclass 4, count 0 2006.189.08:26:50.38#ibcon#end of sib2, iclass 4, count 0 2006.189.08:26:50.38#ibcon#*mode == 0, iclass 4, count 0 2006.189.08:26:50.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.189.08:26:50.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.189.08:26:50.38#ibcon#*before write, iclass 4, count 0 2006.189.08:26:50.38#ibcon#enter sib2, iclass 4, count 0 2006.189.08:26:50.38#ibcon#flushed, iclass 4, count 0 2006.189.08:26:50.38#ibcon#about to write, iclass 4, count 0 2006.189.08:26:50.38#ibcon#wrote, iclass 4, count 0 2006.189.08:26:50.38#ibcon#about to read 3, iclass 4, count 0 2006.189.08:26:50.42#ibcon#read 3, iclass 4, count 0 2006.189.08:26:50.42#ibcon#about to read 4, iclass 4, count 0 2006.189.08:26:50.42#ibcon#read 4, iclass 4, count 0 2006.189.08:26:50.42#ibcon#about to read 5, iclass 4, count 0 2006.189.08:26:50.42#ibcon#read 5, iclass 4, count 0 2006.189.08:26:50.42#ibcon#about to read 6, iclass 4, count 0 2006.189.08:26:50.42#ibcon#read 6, iclass 4, count 0 2006.189.08:26:50.42#ibcon#end of sib2, iclass 4, count 0 2006.189.08:26:50.42#ibcon#*after write, iclass 4, count 0 2006.189.08:26:50.42#ibcon#*before return 0, iclass 4, count 0 2006.189.08:26:50.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:26:50.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.189.08:26:50.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.189.08:26:50.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.189.08:26:50.42$vc4f8/va=8,6 2006.189.08:26:50.42#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.189.08:26:50.42#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.189.08:26:50.42#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:50.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:26:50.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:26:50.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:26:50.48#ibcon#enter wrdev, iclass 6, count 2 2006.189.08:26:50.48#ibcon#first serial, iclass 6, count 2 2006.189.08:26:50.48#ibcon#enter sib2, iclass 6, count 2 2006.189.08:26:50.48#ibcon#flushed, iclass 6, count 2 2006.189.08:26:50.48#ibcon#about to write, iclass 6, count 2 2006.189.08:26:50.48#ibcon#wrote, iclass 6, count 2 2006.189.08:26:50.48#ibcon#about to read 3, iclass 6, count 2 2006.189.08:26:50.50#ibcon#read 3, iclass 6, count 2 2006.189.08:26:50.50#ibcon#about to read 4, iclass 6, count 2 2006.189.08:26:50.50#ibcon#read 4, iclass 6, count 2 2006.189.08:26:50.50#ibcon#about to read 5, iclass 6, count 2 2006.189.08:26:50.50#ibcon#read 5, iclass 6, count 2 2006.189.08:26:50.50#ibcon#about to read 6, iclass 6, count 2 2006.189.08:26:50.50#ibcon#read 6, iclass 6, count 2 2006.189.08:26:50.50#ibcon#end of sib2, iclass 6, count 2 2006.189.08:26:50.50#ibcon#*mode == 0, iclass 6, count 2 2006.189.08:26:50.50#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.189.08:26:50.50#ibcon#[25=AT08-06\r\n] 2006.189.08:26:50.50#ibcon#*before write, iclass 6, count 2 2006.189.08:26:50.50#ibcon#enter sib2, iclass 6, count 2 2006.189.08:26:50.50#ibcon#flushed, iclass 6, count 2 2006.189.08:26:50.50#ibcon#about to write, iclass 6, count 2 2006.189.08:26:50.50#ibcon#wrote, iclass 6, count 2 2006.189.08:26:50.50#ibcon#about to read 3, iclass 6, count 2 2006.189.08:26:50.53#ibcon#read 3, iclass 6, count 2 2006.189.08:26:50.53#ibcon#about to read 4, iclass 6, count 2 2006.189.08:26:50.53#ibcon#read 4, iclass 6, count 2 2006.189.08:26:50.53#ibcon#about to read 5, iclass 6, count 2 2006.189.08:26:50.53#ibcon#read 5, iclass 6, count 2 2006.189.08:26:50.53#ibcon#about to read 6, iclass 6, count 2 2006.189.08:26:50.53#ibcon#read 6, iclass 6, count 2 2006.189.08:26:50.53#ibcon#end of sib2, iclass 6, count 2 2006.189.08:26:50.53#ibcon#*after write, iclass 6, count 2 2006.189.08:26:50.53#ibcon#*before return 0, iclass 6, count 2 2006.189.08:26:50.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:26:50.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.189.08:26:50.53#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.189.08:26:50.53#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:50.53#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:26:50.65#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:26:50.65#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:26:50.65#ibcon#enter wrdev, iclass 6, count 0 2006.189.08:26:50.65#ibcon#first serial, iclass 6, count 0 2006.189.08:26:50.65#ibcon#enter sib2, iclass 6, count 0 2006.189.08:26:50.65#ibcon#flushed, iclass 6, count 0 2006.189.08:26:50.65#ibcon#about to write, iclass 6, count 0 2006.189.08:26:50.65#ibcon#wrote, iclass 6, count 0 2006.189.08:26:50.65#ibcon#about to read 3, iclass 6, count 0 2006.189.08:26:50.67#ibcon#read 3, iclass 6, count 0 2006.189.08:26:50.67#ibcon#about to read 4, iclass 6, count 0 2006.189.08:26:50.67#ibcon#read 4, iclass 6, count 0 2006.189.08:26:50.67#ibcon#about to read 5, iclass 6, count 0 2006.189.08:26:50.67#ibcon#read 5, iclass 6, count 0 2006.189.08:26:50.67#ibcon#about to read 6, iclass 6, count 0 2006.189.08:26:50.67#ibcon#read 6, iclass 6, count 0 2006.189.08:26:50.67#ibcon#end of sib2, iclass 6, count 0 2006.189.08:26:50.67#ibcon#*mode == 0, iclass 6, count 0 2006.189.08:26:50.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.189.08:26:50.67#ibcon#[25=USB\r\n] 2006.189.08:26:50.67#ibcon#*before write, iclass 6, count 0 2006.189.08:26:50.67#ibcon#enter sib2, iclass 6, count 0 2006.189.08:26:50.67#ibcon#flushed, iclass 6, count 0 2006.189.08:26:50.67#ibcon#about to write, iclass 6, count 0 2006.189.08:26:50.67#ibcon#wrote, iclass 6, count 0 2006.189.08:26:50.67#ibcon#about to read 3, iclass 6, count 0 2006.189.08:26:50.70#ibcon#read 3, iclass 6, count 0 2006.189.08:26:50.70#ibcon#about to read 4, iclass 6, count 0 2006.189.08:26:50.70#ibcon#read 4, iclass 6, count 0 2006.189.08:26:50.70#ibcon#about to read 5, iclass 6, count 0 2006.189.08:26:50.70#ibcon#read 5, iclass 6, count 0 2006.189.08:26:50.70#ibcon#about to read 6, iclass 6, count 0 2006.189.08:26:50.70#ibcon#read 6, iclass 6, count 0 2006.189.08:26:50.70#ibcon#end of sib2, iclass 6, count 0 2006.189.08:26:50.70#ibcon#*after write, iclass 6, count 0 2006.189.08:26:50.70#ibcon#*before return 0, iclass 6, count 0 2006.189.08:26:50.70#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:26:50.70#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.189.08:26:50.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.189.08:26:50.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.189.08:26:50.70$vc4f8/vblo=1,632.99 2006.189.08:26:50.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.189.08:26:50.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.189.08:26:50.70#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:50.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:26:50.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:26:50.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:26:50.70#ibcon#enter wrdev, iclass 10, count 0 2006.189.08:26:50.70#ibcon#first serial, iclass 10, count 0 2006.189.08:26:50.70#ibcon#enter sib2, iclass 10, count 0 2006.189.08:26:50.70#ibcon#flushed, iclass 10, count 0 2006.189.08:26:50.70#ibcon#about to write, iclass 10, count 0 2006.189.08:26:50.70#ibcon#wrote, iclass 10, count 0 2006.189.08:26:50.70#ibcon#about to read 3, iclass 10, count 0 2006.189.08:26:50.72#ibcon#read 3, iclass 10, count 0 2006.189.08:26:50.72#ibcon#about to read 4, iclass 10, count 0 2006.189.08:26:50.72#ibcon#read 4, iclass 10, count 0 2006.189.08:26:50.72#ibcon#about to read 5, iclass 10, count 0 2006.189.08:26:50.72#ibcon#read 5, iclass 10, count 0 2006.189.08:26:50.72#ibcon#about to read 6, iclass 10, count 0 2006.189.08:26:50.72#ibcon#read 6, iclass 10, count 0 2006.189.08:26:50.72#ibcon#end of sib2, iclass 10, count 0 2006.189.08:26:50.72#ibcon#*mode == 0, iclass 10, count 0 2006.189.08:26:50.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.189.08:26:50.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.189.08:26:50.72#ibcon#*before write, iclass 10, count 0 2006.189.08:26:50.72#ibcon#enter sib2, iclass 10, count 0 2006.189.08:26:50.72#ibcon#flushed, iclass 10, count 0 2006.189.08:26:50.72#ibcon#about to write, iclass 10, count 0 2006.189.08:26:50.72#ibcon#wrote, iclass 10, count 0 2006.189.08:26:50.72#ibcon#about to read 3, iclass 10, count 0 2006.189.08:26:50.76#ibcon#read 3, iclass 10, count 0 2006.189.08:26:50.76#ibcon#about to read 4, iclass 10, count 0 2006.189.08:26:50.76#ibcon#read 4, iclass 10, count 0 2006.189.08:26:50.76#ibcon#about to read 5, iclass 10, count 0 2006.189.08:26:50.76#ibcon#read 5, iclass 10, count 0 2006.189.08:26:50.76#ibcon#about to read 6, iclass 10, count 0 2006.189.08:26:50.76#ibcon#read 6, iclass 10, count 0 2006.189.08:26:50.76#ibcon#end of sib2, iclass 10, count 0 2006.189.08:26:50.76#ibcon#*after write, iclass 10, count 0 2006.189.08:26:50.76#ibcon#*before return 0, iclass 10, count 0 2006.189.08:26:50.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:26:50.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.189.08:26:50.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.189.08:26:50.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.189.08:26:50.76$vc4f8/vb=1,4 2006.189.08:26:50.76#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.189.08:26:50.76#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.189.08:26:50.76#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:50.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:26:50.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:26:50.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:26:50.76#ibcon#enter wrdev, iclass 12, count 2 2006.189.08:26:50.76#ibcon#first serial, iclass 12, count 2 2006.189.08:26:50.76#ibcon#enter sib2, iclass 12, count 2 2006.189.08:26:50.76#ibcon#flushed, iclass 12, count 2 2006.189.08:26:50.76#ibcon#about to write, iclass 12, count 2 2006.189.08:26:50.76#ibcon#wrote, iclass 12, count 2 2006.189.08:26:50.76#ibcon#about to read 3, iclass 12, count 2 2006.189.08:26:50.78#ibcon#read 3, iclass 12, count 2 2006.189.08:26:50.78#ibcon#about to read 4, iclass 12, count 2 2006.189.08:26:50.78#ibcon#read 4, iclass 12, count 2 2006.189.08:26:50.78#ibcon#about to read 5, iclass 12, count 2 2006.189.08:26:50.78#ibcon#read 5, iclass 12, count 2 2006.189.08:26:50.78#ibcon#about to read 6, iclass 12, count 2 2006.189.08:26:50.78#ibcon#read 6, iclass 12, count 2 2006.189.08:26:50.78#ibcon#end of sib2, iclass 12, count 2 2006.189.08:26:50.78#ibcon#*mode == 0, iclass 12, count 2 2006.189.08:26:50.78#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.189.08:26:50.78#ibcon#[27=AT01-04\r\n] 2006.189.08:26:50.78#ibcon#*before write, iclass 12, count 2 2006.189.08:26:50.78#ibcon#enter sib2, iclass 12, count 2 2006.189.08:26:50.78#ibcon#flushed, iclass 12, count 2 2006.189.08:26:50.78#ibcon#about to write, iclass 12, count 2 2006.189.08:26:50.78#ibcon#wrote, iclass 12, count 2 2006.189.08:26:50.78#ibcon#about to read 3, iclass 12, count 2 2006.189.08:26:50.81#ibcon#read 3, iclass 12, count 2 2006.189.08:26:50.81#ibcon#about to read 4, iclass 12, count 2 2006.189.08:26:50.81#ibcon#read 4, iclass 12, count 2 2006.189.08:26:50.81#ibcon#about to read 5, iclass 12, count 2 2006.189.08:26:50.81#ibcon#read 5, iclass 12, count 2 2006.189.08:26:50.81#ibcon#about to read 6, iclass 12, count 2 2006.189.08:26:50.81#ibcon#read 6, iclass 12, count 2 2006.189.08:26:50.81#ibcon#end of sib2, iclass 12, count 2 2006.189.08:26:50.81#ibcon#*after write, iclass 12, count 2 2006.189.08:26:50.81#ibcon#*before return 0, iclass 12, count 2 2006.189.08:26:50.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:26:50.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.189.08:26:50.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.189.08:26:50.81#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:50.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:26:50.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:26:50.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:26:50.93#ibcon#enter wrdev, iclass 12, count 0 2006.189.08:26:50.93#ibcon#first serial, iclass 12, count 0 2006.189.08:26:50.93#ibcon#enter sib2, iclass 12, count 0 2006.189.08:26:50.93#ibcon#flushed, iclass 12, count 0 2006.189.08:26:50.93#ibcon#about to write, iclass 12, count 0 2006.189.08:26:50.93#ibcon#wrote, iclass 12, count 0 2006.189.08:26:50.93#ibcon#about to read 3, iclass 12, count 0 2006.189.08:26:50.95#ibcon#read 3, iclass 12, count 0 2006.189.08:26:50.95#ibcon#about to read 4, iclass 12, count 0 2006.189.08:26:50.95#ibcon#read 4, iclass 12, count 0 2006.189.08:26:50.95#ibcon#about to read 5, iclass 12, count 0 2006.189.08:26:50.95#ibcon#read 5, iclass 12, count 0 2006.189.08:26:50.95#ibcon#about to read 6, iclass 12, count 0 2006.189.08:26:50.95#ibcon#read 6, iclass 12, count 0 2006.189.08:26:50.95#ibcon#end of sib2, iclass 12, count 0 2006.189.08:26:50.95#ibcon#*mode == 0, iclass 12, count 0 2006.189.08:26:50.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.189.08:26:50.95#ibcon#[27=USB\r\n] 2006.189.08:26:50.95#ibcon#*before write, iclass 12, count 0 2006.189.08:26:50.95#ibcon#enter sib2, iclass 12, count 0 2006.189.08:26:50.95#ibcon#flushed, iclass 12, count 0 2006.189.08:26:50.95#ibcon#about to write, iclass 12, count 0 2006.189.08:26:50.95#ibcon#wrote, iclass 12, count 0 2006.189.08:26:50.95#ibcon#about to read 3, iclass 12, count 0 2006.189.08:26:50.98#ibcon#read 3, iclass 12, count 0 2006.189.08:26:50.98#ibcon#about to read 4, iclass 12, count 0 2006.189.08:26:50.98#ibcon#read 4, iclass 12, count 0 2006.189.08:26:50.98#ibcon#about to read 5, iclass 12, count 0 2006.189.08:26:50.98#ibcon#read 5, iclass 12, count 0 2006.189.08:26:50.98#ibcon#about to read 6, iclass 12, count 0 2006.189.08:26:50.98#ibcon#read 6, iclass 12, count 0 2006.189.08:26:50.98#ibcon#end of sib2, iclass 12, count 0 2006.189.08:26:50.98#ibcon#*after write, iclass 12, count 0 2006.189.08:26:50.98#ibcon#*before return 0, iclass 12, count 0 2006.189.08:26:50.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:26:50.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.189.08:26:50.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.189.08:26:50.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.189.08:26:50.98$vc4f8/vblo=2,640.99 2006.189.08:26:50.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.189.08:26:50.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.189.08:26:50.98#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:50.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:50.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:50.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:50.98#ibcon#enter wrdev, iclass 14, count 0 2006.189.08:26:50.98#ibcon#first serial, iclass 14, count 0 2006.189.08:26:50.98#ibcon#enter sib2, iclass 14, count 0 2006.189.08:26:50.98#ibcon#flushed, iclass 14, count 0 2006.189.08:26:50.98#ibcon#about to write, iclass 14, count 0 2006.189.08:26:50.98#ibcon#wrote, iclass 14, count 0 2006.189.08:26:50.98#ibcon#about to read 3, iclass 14, count 0 2006.189.08:26:51.00#ibcon#read 3, iclass 14, count 0 2006.189.08:26:51.00#ibcon#about to read 4, iclass 14, count 0 2006.189.08:26:51.00#ibcon#read 4, iclass 14, count 0 2006.189.08:26:51.00#ibcon#about to read 5, iclass 14, count 0 2006.189.08:26:51.00#ibcon#read 5, iclass 14, count 0 2006.189.08:26:51.00#ibcon#about to read 6, iclass 14, count 0 2006.189.08:26:51.00#ibcon#read 6, iclass 14, count 0 2006.189.08:26:51.00#ibcon#end of sib2, iclass 14, count 0 2006.189.08:26:51.00#ibcon#*mode == 0, iclass 14, count 0 2006.189.08:26:51.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.189.08:26:51.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.189.08:26:51.00#ibcon#*before write, iclass 14, count 0 2006.189.08:26:51.00#ibcon#enter sib2, iclass 14, count 0 2006.189.08:26:51.00#ibcon#flushed, iclass 14, count 0 2006.189.08:26:51.00#ibcon#about to write, iclass 14, count 0 2006.189.08:26:51.00#ibcon#wrote, iclass 14, count 0 2006.189.08:26:51.00#ibcon#about to read 3, iclass 14, count 0 2006.189.08:26:51.04#ibcon#read 3, iclass 14, count 0 2006.189.08:26:51.04#ibcon#about to read 4, iclass 14, count 0 2006.189.08:26:51.04#ibcon#read 4, iclass 14, count 0 2006.189.08:26:51.04#ibcon#about to read 5, iclass 14, count 0 2006.189.08:26:51.04#ibcon#read 5, iclass 14, count 0 2006.189.08:26:51.04#ibcon#about to read 6, iclass 14, count 0 2006.189.08:26:51.04#ibcon#read 6, iclass 14, count 0 2006.189.08:26:51.04#ibcon#end of sib2, iclass 14, count 0 2006.189.08:26:51.04#ibcon#*after write, iclass 14, count 0 2006.189.08:26:51.04#ibcon#*before return 0, iclass 14, count 0 2006.189.08:26:51.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:51.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.189.08:26:51.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.189.08:26:51.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.189.08:26:51.04$vc4f8/vb=2,4 2006.189.08:26:51.04#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.189.08:26:51.04#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.189.08:26:51.04#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:51.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:51.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:51.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:51.10#ibcon#enter wrdev, iclass 16, count 2 2006.189.08:26:51.10#ibcon#first serial, iclass 16, count 2 2006.189.08:26:51.10#ibcon#enter sib2, iclass 16, count 2 2006.189.08:26:51.10#ibcon#flushed, iclass 16, count 2 2006.189.08:26:51.10#ibcon#about to write, iclass 16, count 2 2006.189.08:26:51.10#ibcon#wrote, iclass 16, count 2 2006.189.08:26:51.10#ibcon#about to read 3, iclass 16, count 2 2006.189.08:26:51.12#ibcon#read 3, iclass 16, count 2 2006.189.08:26:51.12#ibcon#about to read 4, iclass 16, count 2 2006.189.08:26:51.12#ibcon#read 4, iclass 16, count 2 2006.189.08:26:51.12#ibcon#about to read 5, iclass 16, count 2 2006.189.08:26:51.12#ibcon#read 5, iclass 16, count 2 2006.189.08:26:51.12#ibcon#about to read 6, iclass 16, count 2 2006.189.08:26:51.12#ibcon#read 6, iclass 16, count 2 2006.189.08:26:51.12#ibcon#end of sib2, iclass 16, count 2 2006.189.08:26:51.12#ibcon#*mode == 0, iclass 16, count 2 2006.189.08:26:51.12#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.189.08:26:51.12#ibcon#[27=AT02-04\r\n] 2006.189.08:26:51.12#ibcon#*before write, iclass 16, count 2 2006.189.08:26:51.12#ibcon#enter sib2, iclass 16, count 2 2006.189.08:26:51.12#ibcon#flushed, iclass 16, count 2 2006.189.08:26:51.12#ibcon#about to write, iclass 16, count 2 2006.189.08:26:51.12#ibcon#wrote, iclass 16, count 2 2006.189.08:26:51.12#ibcon#about to read 3, iclass 16, count 2 2006.189.08:26:51.15#ibcon#read 3, iclass 16, count 2 2006.189.08:26:51.15#ibcon#about to read 4, iclass 16, count 2 2006.189.08:26:51.15#ibcon#read 4, iclass 16, count 2 2006.189.08:26:51.15#ibcon#about to read 5, iclass 16, count 2 2006.189.08:26:51.15#ibcon#read 5, iclass 16, count 2 2006.189.08:26:51.15#ibcon#about to read 6, iclass 16, count 2 2006.189.08:26:51.15#ibcon#read 6, iclass 16, count 2 2006.189.08:26:51.15#ibcon#end of sib2, iclass 16, count 2 2006.189.08:26:51.15#ibcon#*after write, iclass 16, count 2 2006.189.08:26:51.15#ibcon#*before return 0, iclass 16, count 2 2006.189.08:26:51.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:51.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.189.08:26:51.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.189.08:26:51.15#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:51.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:51.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:51.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:51.27#ibcon#enter wrdev, iclass 16, count 0 2006.189.08:26:51.27#ibcon#first serial, iclass 16, count 0 2006.189.08:26:51.27#ibcon#enter sib2, iclass 16, count 0 2006.189.08:26:51.27#ibcon#flushed, iclass 16, count 0 2006.189.08:26:51.27#ibcon#about to write, iclass 16, count 0 2006.189.08:26:51.27#ibcon#wrote, iclass 16, count 0 2006.189.08:26:51.27#ibcon#about to read 3, iclass 16, count 0 2006.189.08:26:51.29#ibcon#read 3, iclass 16, count 0 2006.189.08:26:51.29#ibcon#about to read 4, iclass 16, count 0 2006.189.08:26:51.29#ibcon#read 4, iclass 16, count 0 2006.189.08:26:51.29#ibcon#about to read 5, iclass 16, count 0 2006.189.08:26:51.29#ibcon#read 5, iclass 16, count 0 2006.189.08:26:51.29#ibcon#about to read 6, iclass 16, count 0 2006.189.08:26:51.29#ibcon#read 6, iclass 16, count 0 2006.189.08:26:51.29#ibcon#end of sib2, iclass 16, count 0 2006.189.08:26:51.29#ibcon#*mode == 0, iclass 16, count 0 2006.189.08:26:51.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.189.08:26:51.29#ibcon#[27=USB\r\n] 2006.189.08:26:51.29#ibcon#*before write, iclass 16, count 0 2006.189.08:26:51.29#ibcon#enter sib2, iclass 16, count 0 2006.189.08:26:51.29#ibcon#flushed, iclass 16, count 0 2006.189.08:26:51.29#ibcon#about to write, iclass 16, count 0 2006.189.08:26:51.29#ibcon#wrote, iclass 16, count 0 2006.189.08:26:51.29#ibcon#about to read 3, iclass 16, count 0 2006.189.08:26:51.32#ibcon#read 3, iclass 16, count 0 2006.189.08:26:51.32#ibcon#about to read 4, iclass 16, count 0 2006.189.08:26:51.32#ibcon#read 4, iclass 16, count 0 2006.189.08:26:51.32#ibcon#about to read 5, iclass 16, count 0 2006.189.08:26:51.32#ibcon#read 5, iclass 16, count 0 2006.189.08:26:51.32#ibcon#about to read 6, iclass 16, count 0 2006.189.08:26:51.32#ibcon#read 6, iclass 16, count 0 2006.189.08:26:51.32#ibcon#end of sib2, iclass 16, count 0 2006.189.08:26:51.32#ibcon#*after write, iclass 16, count 0 2006.189.08:26:51.32#ibcon#*before return 0, iclass 16, count 0 2006.189.08:26:51.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:51.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.189.08:26:51.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.189.08:26:51.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.189.08:26:51.32$vc4f8/vblo=3,656.99 2006.189.08:26:51.32#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.189.08:26:51.32#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.189.08:26:51.32#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:51.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:51.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:51.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:51.32#ibcon#enter wrdev, iclass 18, count 0 2006.189.08:26:51.32#ibcon#first serial, iclass 18, count 0 2006.189.08:26:51.32#ibcon#enter sib2, iclass 18, count 0 2006.189.08:26:51.32#ibcon#flushed, iclass 18, count 0 2006.189.08:26:51.32#ibcon#about to write, iclass 18, count 0 2006.189.08:26:51.32#ibcon#wrote, iclass 18, count 0 2006.189.08:26:51.32#ibcon#about to read 3, iclass 18, count 0 2006.189.08:26:51.34#ibcon#read 3, iclass 18, count 0 2006.189.08:26:51.34#ibcon#about to read 4, iclass 18, count 0 2006.189.08:26:51.34#ibcon#read 4, iclass 18, count 0 2006.189.08:26:51.34#ibcon#about to read 5, iclass 18, count 0 2006.189.08:26:51.34#ibcon#read 5, iclass 18, count 0 2006.189.08:26:51.34#ibcon#about to read 6, iclass 18, count 0 2006.189.08:26:51.34#ibcon#read 6, iclass 18, count 0 2006.189.08:26:51.34#ibcon#end of sib2, iclass 18, count 0 2006.189.08:26:51.34#ibcon#*mode == 0, iclass 18, count 0 2006.189.08:26:51.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.189.08:26:51.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.189.08:26:51.34#ibcon#*before write, iclass 18, count 0 2006.189.08:26:51.34#ibcon#enter sib2, iclass 18, count 0 2006.189.08:26:51.34#ibcon#flushed, iclass 18, count 0 2006.189.08:26:51.34#ibcon#about to write, iclass 18, count 0 2006.189.08:26:51.34#ibcon#wrote, iclass 18, count 0 2006.189.08:26:51.34#ibcon#about to read 3, iclass 18, count 0 2006.189.08:26:51.38#ibcon#read 3, iclass 18, count 0 2006.189.08:26:51.38#ibcon#about to read 4, iclass 18, count 0 2006.189.08:26:51.38#ibcon#read 4, iclass 18, count 0 2006.189.08:26:51.38#ibcon#about to read 5, iclass 18, count 0 2006.189.08:26:51.38#ibcon#read 5, iclass 18, count 0 2006.189.08:26:51.38#ibcon#about to read 6, iclass 18, count 0 2006.189.08:26:51.38#ibcon#read 6, iclass 18, count 0 2006.189.08:26:51.38#ibcon#end of sib2, iclass 18, count 0 2006.189.08:26:51.38#ibcon#*after write, iclass 18, count 0 2006.189.08:26:51.38#ibcon#*before return 0, iclass 18, count 0 2006.189.08:26:51.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:51.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.189.08:26:51.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.189.08:26:51.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.189.08:26:51.38$vc4f8/vb=3,4 2006.189.08:26:51.38#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.189.08:26:51.38#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.189.08:26:51.38#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:51.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:51.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:51.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:51.44#ibcon#enter wrdev, iclass 20, count 2 2006.189.08:26:51.44#ibcon#first serial, iclass 20, count 2 2006.189.08:26:51.44#ibcon#enter sib2, iclass 20, count 2 2006.189.08:26:51.44#ibcon#flushed, iclass 20, count 2 2006.189.08:26:51.44#ibcon#about to write, iclass 20, count 2 2006.189.08:26:51.44#ibcon#wrote, iclass 20, count 2 2006.189.08:26:51.44#ibcon#about to read 3, iclass 20, count 2 2006.189.08:26:51.46#ibcon#read 3, iclass 20, count 2 2006.189.08:26:51.46#ibcon#about to read 4, iclass 20, count 2 2006.189.08:26:51.46#ibcon#read 4, iclass 20, count 2 2006.189.08:26:51.46#ibcon#about to read 5, iclass 20, count 2 2006.189.08:26:51.46#ibcon#read 5, iclass 20, count 2 2006.189.08:26:51.46#ibcon#about to read 6, iclass 20, count 2 2006.189.08:26:51.46#ibcon#read 6, iclass 20, count 2 2006.189.08:26:51.46#ibcon#end of sib2, iclass 20, count 2 2006.189.08:26:51.46#ibcon#*mode == 0, iclass 20, count 2 2006.189.08:26:51.46#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.189.08:26:51.46#ibcon#[27=AT03-04\r\n] 2006.189.08:26:51.46#ibcon#*before write, iclass 20, count 2 2006.189.08:26:51.46#ibcon#enter sib2, iclass 20, count 2 2006.189.08:26:51.46#ibcon#flushed, iclass 20, count 2 2006.189.08:26:51.46#ibcon#about to write, iclass 20, count 2 2006.189.08:26:51.46#ibcon#wrote, iclass 20, count 2 2006.189.08:26:51.46#ibcon#about to read 3, iclass 20, count 2 2006.189.08:26:51.49#ibcon#read 3, iclass 20, count 2 2006.189.08:26:51.49#ibcon#about to read 4, iclass 20, count 2 2006.189.08:26:51.49#ibcon#read 4, iclass 20, count 2 2006.189.08:26:51.49#ibcon#about to read 5, iclass 20, count 2 2006.189.08:26:51.49#ibcon#read 5, iclass 20, count 2 2006.189.08:26:51.49#ibcon#about to read 6, iclass 20, count 2 2006.189.08:26:51.49#ibcon#read 6, iclass 20, count 2 2006.189.08:26:51.49#ibcon#end of sib2, iclass 20, count 2 2006.189.08:26:51.49#ibcon#*after write, iclass 20, count 2 2006.189.08:26:51.49#ibcon#*before return 0, iclass 20, count 2 2006.189.08:26:51.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:51.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.189.08:26:51.49#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.189.08:26:51.49#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:51.49#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:51.61#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:51.61#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:51.61#ibcon#enter wrdev, iclass 20, count 0 2006.189.08:26:51.61#ibcon#first serial, iclass 20, count 0 2006.189.08:26:51.61#ibcon#enter sib2, iclass 20, count 0 2006.189.08:26:51.61#ibcon#flushed, iclass 20, count 0 2006.189.08:26:51.61#ibcon#about to write, iclass 20, count 0 2006.189.08:26:51.61#ibcon#wrote, iclass 20, count 0 2006.189.08:26:51.61#ibcon#about to read 3, iclass 20, count 0 2006.189.08:26:51.63#ibcon#read 3, iclass 20, count 0 2006.189.08:26:51.63#ibcon#about to read 4, iclass 20, count 0 2006.189.08:26:51.63#ibcon#read 4, iclass 20, count 0 2006.189.08:26:51.63#ibcon#about to read 5, iclass 20, count 0 2006.189.08:26:51.63#ibcon#read 5, iclass 20, count 0 2006.189.08:26:51.63#ibcon#about to read 6, iclass 20, count 0 2006.189.08:26:51.63#ibcon#read 6, iclass 20, count 0 2006.189.08:26:51.63#ibcon#end of sib2, iclass 20, count 0 2006.189.08:26:51.63#ibcon#*mode == 0, iclass 20, count 0 2006.189.08:26:51.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.189.08:26:51.63#ibcon#[27=USB\r\n] 2006.189.08:26:51.63#ibcon#*before write, iclass 20, count 0 2006.189.08:26:51.63#ibcon#enter sib2, iclass 20, count 0 2006.189.08:26:51.63#ibcon#flushed, iclass 20, count 0 2006.189.08:26:51.63#ibcon#about to write, iclass 20, count 0 2006.189.08:26:51.63#ibcon#wrote, iclass 20, count 0 2006.189.08:26:51.63#ibcon#about to read 3, iclass 20, count 0 2006.189.08:26:51.66#ibcon#read 3, iclass 20, count 0 2006.189.08:26:51.66#ibcon#about to read 4, iclass 20, count 0 2006.189.08:26:51.66#ibcon#read 4, iclass 20, count 0 2006.189.08:26:51.66#ibcon#about to read 5, iclass 20, count 0 2006.189.08:26:51.66#ibcon#read 5, iclass 20, count 0 2006.189.08:26:51.66#ibcon#about to read 6, iclass 20, count 0 2006.189.08:26:51.66#ibcon#read 6, iclass 20, count 0 2006.189.08:26:51.66#ibcon#end of sib2, iclass 20, count 0 2006.189.08:26:51.66#ibcon#*after write, iclass 20, count 0 2006.189.08:26:51.66#ibcon#*before return 0, iclass 20, count 0 2006.189.08:26:51.66#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:51.66#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.189.08:26:51.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.189.08:26:51.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.189.08:26:51.66$vc4f8/vblo=4,712.99 2006.189.08:26:51.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.189.08:26:51.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.189.08:26:51.66#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:51.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:51.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:51.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:51.66#ibcon#enter wrdev, iclass 22, count 0 2006.189.08:26:51.66#ibcon#first serial, iclass 22, count 0 2006.189.08:26:51.66#ibcon#enter sib2, iclass 22, count 0 2006.189.08:26:51.66#ibcon#flushed, iclass 22, count 0 2006.189.08:26:51.66#ibcon#about to write, iclass 22, count 0 2006.189.08:26:51.66#ibcon#wrote, iclass 22, count 0 2006.189.08:26:51.66#ibcon#about to read 3, iclass 22, count 0 2006.189.08:26:51.68#ibcon#read 3, iclass 22, count 0 2006.189.08:26:51.68#ibcon#about to read 4, iclass 22, count 0 2006.189.08:26:51.68#ibcon#read 4, iclass 22, count 0 2006.189.08:26:51.68#ibcon#about to read 5, iclass 22, count 0 2006.189.08:26:51.68#ibcon#read 5, iclass 22, count 0 2006.189.08:26:51.68#ibcon#about to read 6, iclass 22, count 0 2006.189.08:26:51.68#ibcon#read 6, iclass 22, count 0 2006.189.08:26:51.68#ibcon#end of sib2, iclass 22, count 0 2006.189.08:26:51.68#ibcon#*mode == 0, iclass 22, count 0 2006.189.08:26:51.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.189.08:26:51.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.189.08:26:51.68#ibcon#*before write, iclass 22, count 0 2006.189.08:26:51.68#ibcon#enter sib2, iclass 22, count 0 2006.189.08:26:51.68#ibcon#flushed, iclass 22, count 0 2006.189.08:26:51.68#ibcon#about to write, iclass 22, count 0 2006.189.08:26:51.68#ibcon#wrote, iclass 22, count 0 2006.189.08:26:51.68#ibcon#about to read 3, iclass 22, count 0 2006.189.08:26:51.72#ibcon#read 3, iclass 22, count 0 2006.189.08:26:51.72#ibcon#about to read 4, iclass 22, count 0 2006.189.08:26:51.72#ibcon#read 4, iclass 22, count 0 2006.189.08:26:51.72#ibcon#about to read 5, iclass 22, count 0 2006.189.08:26:51.72#ibcon#read 5, iclass 22, count 0 2006.189.08:26:51.72#ibcon#about to read 6, iclass 22, count 0 2006.189.08:26:51.72#ibcon#read 6, iclass 22, count 0 2006.189.08:26:51.72#ibcon#end of sib2, iclass 22, count 0 2006.189.08:26:51.72#ibcon#*after write, iclass 22, count 0 2006.189.08:26:51.72#ibcon#*before return 0, iclass 22, count 0 2006.189.08:26:51.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:51.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.189.08:26:51.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.189.08:26:51.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.189.08:26:51.72$vc4f8/vb=4,4 2006.189.08:26:51.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.189.08:26:51.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.189.08:26:51.72#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:51.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:51.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:51.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:51.78#ibcon#enter wrdev, iclass 24, count 2 2006.189.08:26:51.78#ibcon#first serial, iclass 24, count 2 2006.189.08:26:51.78#ibcon#enter sib2, iclass 24, count 2 2006.189.08:26:51.78#ibcon#flushed, iclass 24, count 2 2006.189.08:26:51.78#ibcon#about to write, iclass 24, count 2 2006.189.08:26:51.78#ibcon#wrote, iclass 24, count 2 2006.189.08:26:51.78#ibcon#about to read 3, iclass 24, count 2 2006.189.08:26:51.80#ibcon#read 3, iclass 24, count 2 2006.189.08:26:51.80#ibcon#about to read 4, iclass 24, count 2 2006.189.08:26:51.80#ibcon#read 4, iclass 24, count 2 2006.189.08:26:51.80#ibcon#about to read 5, iclass 24, count 2 2006.189.08:26:51.80#ibcon#read 5, iclass 24, count 2 2006.189.08:26:51.80#ibcon#about to read 6, iclass 24, count 2 2006.189.08:26:51.80#ibcon#read 6, iclass 24, count 2 2006.189.08:26:51.80#ibcon#end of sib2, iclass 24, count 2 2006.189.08:26:51.80#ibcon#*mode == 0, iclass 24, count 2 2006.189.08:26:51.80#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.189.08:26:51.80#ibcon#[27=AT04-04\r\n] 2006.189.08:26:51.80#ibcon#*before write, iclass 24, count 2 2006.189.08:26:51.80#ibcon#enter sib2, iclass 24, count 2 2006.189.08:26:51.80#ibcon#flushed, iclass 24, count 2 2006.189.08:26:51.80#ibcon#about to write, iclass 24, count 2 2006.189.08:26:51.80#ibcon#wrote, iclass 24, count 2 2006.189.08:26:51.80#ibcon#about to read 3, iclass 24, count 2 2006.189.08:26:51.83#ibcon#read 3, iclass 24, count 2 2006.189.08:26:51.83#ibcon#about to read 4, iclass 24, count 2 2006.189.08:26:51.83#ibcon#read 4, iclass 24, count 2 2006.189.08:26:51.83#ibcon#about to read 5, iclass 24, count 2 2006.189.08:26:51.83#ibcon#read 5, iclass 24, count 2 2006.189.08:26:51.83#ibcon#about to read 6, iclass 24, count 2 2006.189.08:26:51.83#ibcon#read 6, iclass 24, count 2 2006.189.08:26:51.83#ibcon#end of sib2, iclass 24, count 2 2006.189.08:26:51.83#ibcon#*after write, iclass 24, count 2 2006.189.08:26:51.83#ibcon#*before return 0, iclass 24, count 2 2006.189.08:26:51.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:51.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.189.08:26:51.83#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.189.08:26:51.83#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:51.83#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:51.95#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:51.95#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:51.95#ibcon#enter wrdev, iclass 24, count 0 2006.189.08:26:51.95#ibcon#first serial, iclass 24, count 0 2006.189.08:26:51.95#ibcon#enter sib2, iclass 24, count 0 2006.189.08:26:51.95#ibcon#flushed, iclass 24, count 0 2006.189.08:26:51.95#ibcon#about to write, iclass 24, count 0 2006.189.08:26:51.95#ibcon#wrote, iclass 24, count 0 2006.189.08:26:51.95#ibcon#about to read 3, iclass 24, count 0 2006.189.08:26:51.97#ibcon#read 3, iclass 24, count 0 2006.189.08:26:51.97#ibcon#about to read 4, iclass 24, count 0 2006.189.08:26:51.97#ibcon#read 4, iclass 24, count 0 2006.189.08:26:51.97#ibcon#about to read 5, iclass 24, count 0 2006.189.08:26:51.97#ibcon#read 5, iclass 24, count 0 2006.189.08:26:51.97#ibcon#about to read 6, iclass 24, count 0 2006.189.08:26:51.97#ibcon#read 6, iclass 24, count 0 2006.189.08:26:51.97#ibcon#end of sib2, iclass 24, count 0 2006.189.08:26:51.97#ibcon#*mode == 0, iclass 24, count 0 2006.189.08:26:51.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.189.08:26:51.97#ibcon#[27=USB\r\n] 2006.189.08:26:51.97#ibcon#*before write, iclass 24, count 0 2006.189.08:26:51.97#ibcon#enter sib2, iclass 24, count 0 2006.189.08:26:51.97#ibcon#flushed, iclass 24, count 0 2006.189.08:26:51.97#ibcon#about to write, iclass 24, count 0 2006.189.08:26:51.97#ibcon#wrote, iclass 24, count 0 2006.189.08:26:51.97#ibcon#about to read 3, iclass 24, count 0 2006.189.08:26:52.00#ibcon#read 3, iclass 24, count 0 2006.189.08:26:52.00#ibcon#about to read 4, iclass 24, count 0 2006.189.08:26:52.00#ibcon#read 4, iclass 24, count 0 2006.189.08:26:52.00#ibcon#about to read 5, iclass 24, count 0 2006.189.08:26:52.00#ibcon#read 5, iclass 24, count 0 2006.189.08:26:52.00#ibcon#about to read 6, iclass 24, count 0 2006.189.08:26:52.00#ibcon#read 6, iclass 24, count 0 2006.189.08:26:52.00#ibcon#end of sib2, iclass 24, count 0 2006.189.08:26:52.00#ibcon#*after write, iclass 24, count 0 2006.189.08:26:52.00#ibcon#*before return 0, iclass 24, count 0 2006.189.08:26:52.00#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:52.00#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.189.08:26:52.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.189.08:26:52.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.189.08:26:52.00$vc4f8/vblo=5,744.99 2006.189.08:26:52.00#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.189.08:26:52.00#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.189.08:26:52.00#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:52.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:52.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:52.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:52.00#ibcon#enter wrdev, iclass 26, count 0 2006.189.08:26:52.00#ibcon#first serial, iclass 26, count 0 2006.189.08:26:52.00#ibcon#enter sib2, iclass 26, count 0 2006.189.08:26:52.00#ibcon#flushed, iclass 26, count 0 2006.189.08:26:52.00#ibcon#about to write, iclass 26, count 0 2006.189.08:26:52.00#ibcon#wrote, iclass 26, count 0 2006.189.08:26:52.00#ibcon#about to read 3, iclass 26, count 0 2006.189.08:26:52.02#ibcon#read 3, iclass 26, count 0 2006.189.08:26:52.02#ibcon#about to read 4, iclass 26, count 0 2006.189.08:26:52.02#ibcon#read 4, iclass 26, count 0 2006.189.08:26:52.02#ibcon#about to read 5, iclass 26, count 0 2006.189.08:26:52.02#ibcon#read 5, iclass 26, count 0 2006.189.08:26:52.02#ibcon#about to read 6, iclass 26, count 0 2006.189.08:26:52.02#ibcon#read 6, iclass 26, count 0 2006.189.08:26:52.02#ibcon#end of sib2, iclass 26, count 0 2006.189.08:26:52.02#ibcon#*mode == 0, iclass 26, count 0 2006.189.08:26:52.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.189.08:26:52.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.189.08:26:52.02#ibcon#*before write, iclass 26, count 0 2006.189.08:26:52.02#ibcon#enter sib2, iclass 26, count 0 2006.189.08:26:52.02#ibcon#flushed, iclass 26, count 0 2006.189.08:26:52.02#ibcon#about to write, iclass 26, count 0 2006.189.08:26:52.02#ibcon#wrote, iclass 26, count 0 2006.189.08:26:52.02#ibcon#about to read 3, iclass 26, count 0 2006.189.08:26:52.06#ibcon#read 3, iclass 26, count 0 2006.189.08:26:52.06#ibcon#about to read 4, iclass 26, count 0 2006.189.08:26:52.06#ibcon#read 4, iclass 26, count 0 2006.189.08:26:52.06#ibcon#about to read 5, iclass 26, count 0 2006.189.08:26:52.06#ibcon#read 5, iclass 26, count 0 2006.189.08:26:52.06#ibcon#about to read 6, iclass 26, count 0 2006.189.08:26:52.06#ibcon#read 6, iclass 26, count 0 2006.189.08:26:52.06#ibcon#end of sib2, iclass 26, count 0 2006.189.08:26:52.06#ibcon#*after write, iclass 26, count 0 2006.189.08:26:52.06#ibcon#*before return 0, iclass 26, count 0 2006.189.08:26:52.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:52.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.189.08:26:52.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.189.08:26:52.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.189.08:26:52.06$vc4f8/vb=5,4 2006.189.08:26:52.06#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.189.08:26:52.06#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.189.08:26:52.06#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:52.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:52.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:52.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:52.12#ibcon#enter wrdev, iclass 28, count 2 2006.189.08:26:52.12#ibcon#first serial, iclass 28, count 2 2006.189.08:26:52.12#ibcon#enter sib2, iclass 28, count 2 2006.189.08:26:52.12#ibcon#flushed, iclass 28, count 2 2006.189.08:26:52.12#ibcon#about to write, iclass 28, count 2 2006.189.08:26:52.12#ibcon#wrote, iclass 28, count 2 2006.189.08:26:52.12#ibcon#about to read 3, iclass 28, count 2 2006.189.08:26:52.14#ibcon#read 3, iclass 28, count 2 2006.189.08:26:52.14#ibcon#about to read 4, iclass 28, count 2 2006.189.08:26:52.14#ibcon#read 4, iclass 28, count 2 2006.189.08:26:52.14#ibcon#about to read 5, iclass 28, count 2 2006.189.08:26:52.14#ibcon#read 5, iclass 28, count 2 2006.189.08:26:52.14#ibcon#about to read 6, iclass 28, count 2 2006.189.08:26:52.14#ibcon#read 6, iclass 28, count 2 2006.189.08:26:52.14#ibcon#end of sib2, iclass 28, count 2 2006.189.08:26:52.14#ibcon#*mode == 0, iclass 28, count 2 2006.189.08:26:52.14#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.189.08:26:52.14#ibcon#[27=AT05-04\r\n] 2006.189.08:26:52.14#ibcon#*before write, iclass 28, count 2 2006.189.08:26:52.14#ibcon#enter sib2, iclass 28, count 2 2006.189.08:26:52.14#ibcon#flushed, iclass 28, count 2 2006.189.08:26:52.14#ibcon#about to write, iclass 28, count 2 2006.189.08:26:52.14#ibcon#wrote, iclass 28, count 2 2006.189.08:26:52.14#ibcon#about to read 3, iclass 28, count 2 2006.189.08:26:52.17#ibcon#read 3, iclass 28, count 2 2006.189.08:26:52.17#ibcon#about to read 4, iclass 28, count 2 2006.189.08:26:52.17#ibcon#read 4, iclass 28, count 2 2006.189.08:26:52.17#ibcon#about to read 5, iclass 28, count 2 2006.189.08:26:52.17#ibcon#read 5, iclass 28, count 2 2006.189.08:26:52.17#ibcon#about to read 6, iclass 28, count 2 2006.189.08:26:52.17#ibcon#read 6, iclass 28, count 2 2006.189.08:26:52.17#ibcon#end of sib2, iclass 28, count 2 2006.189.08:26:52.17#ibcon#*after write, iclass 28, count 2 2006.189.08:26:52.17#ibcon#*before return 0, iclass 28, count 2 2006.189.08:26:52.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:52.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.189.08:26:52.17#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.189.08:26:52.17#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:52.17#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:52.29#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:52.29#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:52.29#ibcon#enter wrdev, iclass 28, count 0 2006.189.08:26:52.29#ibcon#first serial, iclass 28, count 0 2006.189.08:26:52.29#ibcon#enter sib2, iclass 28, count 0 2006.189.08:26:52.29#ibcon#flushed, iclass 28, count 0 2006.189.08:26:52.29#ibcon#about to write, iclass 28, count 0 2006.189.08:26:52.29#ibcon#wrote, iclass 28, count 0 2006.189.08:26:52.29#ibcon#about to read 3, iclass 28, count 0 2006.189.08:26:52.31#ibcon#read 3, iclass 28, count 0 2006.189.08:26:52.31#ibcon#about to read 4, iclass 28, count 0 2006.189.08:26:52.31#ibcon#read 4, iclass 28, count 0 2006.189.08:26:52.31#ibcon#about to read 5, iclass 28, count 0 2006.189.08:26:52.31#ibcon#read 5, iclass 28, count 0 2006.189.08:26:52.31#ibcon#about to read 6, iclass 28, count 0 2006.189.08:26:52.31#ibcon#read 6, iclass 28, count 0 2006.189.08:26:52.31#ibcon#end of sib2, iclass 28, count 0 2006.189.08:26:52.31#ibcon#*mode == 0, iclass 28, count 0 2006.189.08:26:52.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.189.08:26:52.31#ibcon#[27=USB\r\n] 2006.189.08:26:52.31#ibcon#*before write, iclass 28, count 0 2006.189.08:26:52.31#ibcon#enter sib2, iclass 28, count 0 2006.189.08:26:52.31#ibcon#flushed, iclass 28, count 0 2006.189.08:26:52.31#ibcon#about to write, iclass 28, count 0 2006.189.08:26:52.31#ibcon#wrote, iclass 28, count 0 2006.189.08:26:52.31#ibcon#about to read 3, iclass 28, count 0 2006.189.08:26:52.34#ibcon#read 3, iclass 28, count 0 2006.189.08:26:52.34#ibcon#about to read 4, iclass 28, count 0 2006.189.08:26:52.34#ibcon#read 4, iclass 28, count 0 2006.189.08:26:52.34#ibcon#about to read 5, iclass 28, count 0 2006.189.08:26:52.34#ibcon#read 5, iclass 28, count 0 2006.189.08:26:52.34#ibcon#about to read 6, iclass 28, count 0 2006.189.08:26:52.34#ibcon#read 6, iclass 28, count 0 2006.189.08:26:52.34#ibcon#end of sib2, iclass 28, count 0 2006.189.08:26:52.34#ibcon#*after write, iclass 28, count 0 2006.189.08:26:52.34#ibcon#*before return 0, iclass 28, count 0 2006.189.08:26:52.34#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:52.34#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.189.08:26:52.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.189.08:26:52.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.189.08:26:52.34$vc4f8/vblo=6,752.99 2006.189.08:26:52.34#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.189.08:26:52.34#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.189.08:26:52.34#ibcon#ireg 17 cls_cnt 0 2006.189.08:26:52.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:52.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:52.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:52.34#ibcon#enter wrdev, iclass 30, count 0 2006.189.08:26:52.34#ibcon#first serial, iclass 30, count 0 2006.189.08:26:52.34#ibcon#enter sib2, iclass 30, count 0 2006.189.08:26:52.34#ibcon#flushed, iclass 30, count 0 2006.189.08:26:52.34#ibcon#about to write, iclass 30, count 0 2006.189.08:26:52.34#ibcon#wrote, iclass 30, count 0 2006.189.08:26:52.34#ibcon#about to read 3, iclass 30, count 0 2006.189.08:26:52.36#ibcon#read 3, iclass 30, count 0 2006.189.08:26:52.36#ibcon#about to read 4, iclass 30, count 0 2006.189.08:26:52.36#ibcon#read 4, iclass 30, count 0 2006.189.08:26:52.36#ibcon#about to read 5, iclass 30, count 0 2006.189.08:26:52.36#ibcon#read 5, iclass 30, count 0 2006.189.08:26:52.36#ibcon#about to read 6, iclass 30, count 0 2006.189.08:26:52.36#ibcon#read 6, iclass 30, count 0 2006.189.08:26:52.36#ibcon#end of sib2, iclass 30, count 0 2006.189.08:26:52.36#ibcon#*mode == 0, iclass 30, count 0 2006.189.08:26:52.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.189.08:26:52.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.189.08:26:52.36#ibcon#*before write, iclass 30, count 0 2006.189.08:26:52.36#ibcon#enter sib2, iclass 30, count 0 2006.189.08:26:52.36#ibcon#flushed, iclass 30, count 0 2006.189.08:26:52.36#ibcon#about to write, iclass 30, count 0 2006.189.08:26:52.36#ibcon#wrote, iclass 30, count 0 2006.189.08:26:52.36#ibcon#about to read 3, iclass 30, count 0 2006.189.08:26:52.40#ibcon#read 3, iclass 30, count 0 2006.189.08:26:52.40#ibcon#about to read 4, iclass 30, count 0 2006.189.08:26:52.40#ibcon#read 4, iclass 30, count 0 2006.189.08:26:52.40#ibcon#about to read 5, iclass 30, count 0 2006.189.08:26:52.40#ibcon#read 5, iclass 30, count 0 2006.189.08:26:52.40#ibcon#about to read 6, iclass 30, count 0 2006.189.08:26:52.40#ibcon#read 6, iclass 30, count 0 2006.189.08:26:52.40#ibcon#end of sib2, iclass 30, count 0 2006.189.08:26:52.40#ibcon#*after write, iclass 30, count 0 2006.189.08:26:52.40#ibcon#*before return 0, iclass 30, count 0 2006.189.08:26:52.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:52.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.189.08:26:52.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.189.08:26:52.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.189.08:26:52.40$vc4f8/vb=6,4 2006.189.08:26:52.40#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.189.08:26:52.40#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.189.08:26:52.40#ibcon#ireg 11 cls_cnt 2 2006.189.08:26:52.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:52.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:52.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:52.46#ibcon#enter wrdev, iclass 32, count 2 2006.189.08:26:52.46#ibcon#first serial, iclass 32, count 2 2006.189.08:26:52.46#ibcon#enter sib2, iclass 32, count 2 2006.189.08:26:52.46#ibcon#flushed, iclass 32, count 2 2006.189.08:26:52.46#ibcon#about to write, iclass 32, count 2 2006.189.08:26:52.46#ibcon#wrote, iclass 32, count 2 2006.189.08:26:52.46#ibcon#about to read 3, iclass 32, count 2 2006.189.08:26:52.48#ibcon#read 3, iclass 32, count 2 2006.189.08:26:52.48#ibcon#about to read 4, iclass 32, count 2 2006.189.08:26:52.48#ibcon#read 4, iclass 32, count 2 2006.189.08:26:52.48#ibcon#about to read 5, iclass 32, count 2 2006.189.08:26:52.48#ibcon#read 5, iclass 32, count 2 2006.189.08:26:52.48#ibcon#about to read 6, iclass 32, count 2 2006.189.08:26:52.48#ibcon#read 6, iclass 32, count 2 2006.189.08:26:52.48#ibcon#end of sib2, iclass 32, count 2 2006.189.08:26:52.48#ibcon#*mode == 0, iclass 32, count 2 2006.189.08:26:52.48#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.189.08:26:52.48#ibcon#[27=AT06-04\r\n] 2006.189.08:26:52.48#ibcon#*before write, iclass 32, count 2 2006.189.08:26:52.48#ibcon#enter sib2, iclass 32, count 2 2006.189.08:26:52.48#ibcon#flushed, iclass 32, count 2 2006.189.08:26:52.48#ibcon#about to write, iclass 32, count 2 2006.189.08:26:52.48#ibcon#wrote, iclass 32, count 2 2006.189.08:26:52.48#ibcon#about to read 3, iclass 32, count 2 2006.189.08:26:52.51#ibcon#read 3, iclass 32, count 2 2006.189.08:26:52.51#ibcon#about to read 4, iclass 32, count 2 2006.189.08:26:52.51#ibcon#read 4, iclass 32, count 2 2006.189.08:26:52.51#ibcon#about to read 5, iclass 32, count 2 2006.189.08:26:52.51#ibcon#read 5, iclass 32, count 2 2006.189.08:26:52.51#ibcon#about to read 6, iclass 32, count 2 2006.189.08:26:52.51#ibcon#read 6, iclass 32, count 2 2006.189.08:26:52.51#ibcon#end of sib2, iclass 32, count 2 2006.189.08:26:52.51#ibcon#*after write, iclass 32, count 2 2006.189.08:26:52.51#ibcon#*before return 0, iclass 32, count 2 2006.189.08:26:52.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:52.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.189.08:26:52.51#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.189.08:26:52.51#ibcon#ireg 7 cls_cnt 0 2006.189.08:26:52.51#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:52.63#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:52.63#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:52.63#ibcon#enter wrdev, iclass 32, count 0 2006.189.08:26:52.63#ibcon#first serial, iclass 32, count 0 2006.189.08:26:52.63#ibcon#enter sib2, iclass 32, count 0 2006.189.08:26:52.63#ibcon#flushed, iclass 32, count 0 2006.189.08:26:52.63#ibcon#about to write, iclass 32, count 0 2006.189.08:26:52.63#ibcon#wrote, iclass 32, count 0 2006.189.08:26:52.63#ibcon#about to read 3, iclass 32, count 0 2006.189.08:26:52.65#ibcon#read 3, iclass 32, count 0 2006.189.08:26:52.65#ibcon#about to read 4, iclass 32, count 0 2006.189.08:26:52.65#ibcon#read 4, iclass 32, count 0 2006.189.08:26:52.65#ibcon#about to read 5, iclass 32, count 0 2006.189.08:26:52.65#ibcon#read 5, iclass 32, count 0 2006.189.08:26:52.65#ibcon#about to read 6, iclass 32, count 0 2006.189.08:26:52.65#ibcon#read 6, iclass 32, count 0 2006.189.08:26:52.65#ibcon#end of sib2, iclass 32, count 0 2006.189.08:26:52.65#ibcon#*mode == 0, iclass 32, count 0 2006.189.08:26:52.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.189.08:26:52.65#ibcon#[27=USB\r\n] 2006.189.08:26:52.65#ibcon#*before write, iclass 32, count 0 2006.189.08:26:52.65#ibcon#enter sib2, iclass 32, count 0 2006.189.08:26:52.65#ibcon#flushed, iclass 32, count 0 2006.189.08:26:52.65#ibcon#about to write, iclass 32, count 0 2006.189.08:26:52.65#ibcon#wrote, iclass 32, count 0 2006.189.08:26:52.65#ibcon#about to read 3, iclass 32, count 0 2006.189.08:26:52.68#ibcon#read 3, iclass 32, count 0 2006.189.08:26:52.68#ibcon#about to read 4, iclass 32, count 0 2006.189.08:26:52.68#ibcon#read 4, iclass 32, count 0 2006.189.08:26:52.68#ibcon#about to read 5, iclass 32, count 0 2006.189.08:26:52.68#ibcon#read 5, iclass 32, count 0 2006.189.08:26:52.68#ibcon#about to read 6, iclass 32, count 0 2006.189.08:26:52.68#ibcon#read 6, iclass 32, count 0 2006.189.08:26:52.68#ibcon#end of sib2, iclass 32, count 0 2006.189.08:26:52.68#ibcon#*after write, iclass 32, count 0 2006.189.08:26:52.68#ibcon#*before return 0, iclass 32, count 0 2006.189.08:26:52.68#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:52.68#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.189.08:26:52.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.189.08:26:52.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.189.08:26:52.68$vc4f8/vabw=wide 2006.189.08:26:52.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.189.08:26:52.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.189.08:26:52.68#ibcon#ireg 8 cls_cnt 0 2006.189.08:26:52.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:52.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:52.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:52.68#ibcon#enter wrdev, iclass 34, count 0 2006.189.08:26:52.68#ibcon#first serial, iclass 34, count 0 2006.189.08:26:52.68#ibcon#enter sib2, iclass 34, count 0 2006.189.08:26:52.68#ibcon#flushed, iclass 34, count 0 2006.189.08:26:52.68#ibcon#about to write, iclass 34, count 0 2006.189.08:26:52.68#ibcon#wrote, iclass 34, count 0 2006.189.08:26:52.68#ibcon#about to read 3, iclass 34, count 0 2006.189.08:26:52.70#ibcon#read 3, iclass 34, count 0 2006.189.08:26:52.70#ibcon#about to read 4, iclass 34, count 0 2006.189.08:26:52.70#ibcon#read 4, iclass 34, count 0 2006.189.08:26:52.70#ibcon#about to read 5, iclass 34, count 0 2006.189.08:26:52.70#ibcon#read 5, iclass 34, count 0 2006.189.08:26:52.70#ibcon#about to read 6, iclass 34, count 0 2006.189.08:26:52.70#ibcon#read 6, iclass 34, count 0 2006.189.08:26:52.70#ibcon#end of sib2, iclass 34, count 0 2006.189.08:26:52.70#ibcon#*mode == 0, iclass 34, count 0 2006.189.08:26:52.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.189.08:26:52.70#ibcon#[25=BW32\r\n] 2006.189.08:26:52.70#ibcon#*before write, iclass 34, count 0 2006.189.08:26:52.70#ibcon#enter sib2, iclass 34, count 0 2006.189.08:26:52.70#ibcon#flushed, iclass 34, count 0 2006.189.08:26:52.70#ibcon#about to write, iclass 34, count 0 2006.189.08:26:52.70#ibcon#wrote, iclass 34, count 0 2006.189.08:26:52.70#ibcon#about to read 3, iclass 34, count 0 2006.189.08:26:52.73#ibcon#read 3, iclass 34, count 0 2006.189.08:26:52.73#ibcon#about to read 4, iclass 34, count 0 2006.189.08:26:52.73#ibcon#read 4, iclass 34, count 0 2006.189.08:26:52.73#ibcon#about to read 5, iclass 34, count 0 2006.189.08:26:52.73#ibcon#read 5, iclass 34, count 0 2006.189.08:26:52.73#ibcon#about to read 6, iclass 34, count 0 2006.189.08:26:52.73#ibcon#read 6, iclass 34, count 0 2006.189.08:26:52.73#ibcon#end of sib2, iclass 34, count 0 2006.189.08:26:52.73#ibcon#*after write, iclass 34, count 0 2006.189.08:26:52.73#ibcon#*before return 0, iclass 34, count 0 2006.189.08:26:52.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:52.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.189.08:26:52.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.189.08:26:52.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.189.08:26:52.73$vc4f8/vbbw=wide 2006.189.08:26:52.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.189.08:26:52.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.189.08:26:52.73#ibcon#ireg 8 cls_cnt 0 2006.189.08:26:52.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:26:52.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:26:52.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:26:52.80#ibcon#enter wrdev, iclass 36, count 0 2006.189.08:26:52.80#ibcon#first serial, iclass 36, count 0 2006.189.08:26:52.80#ibcon#enter sib2, iclass 36, count 0 2006.189.08:26:52.80#ibcon#flushed, iclass 36, count 0 2006.189.08:26:52.80#ibcon#about to write, iclass 36, count 0 2006.189.08:26:52.80#ibcon#wrote, iclass 36, count 0 2006.189.08:26:52.80#ibcon#about to read 3, iclass 36, count 0 2006.189.08:26:52.82#ibcon#read 3, iclass 36, count 0 2006.189.08:26:52.82#ibcon#about to read 4, iclass 36, count 0 2006.189.08:26:52.82#ibcon#read 4, iclass 36, count 0 2006.189.08:26:52.82#ibcon#about to read 5, iclass 36, count 0 2006.189.08:26:52.82#ibcon#read 5, iclass 36, count 0 2006.189.08:26:52.82#ibcon#about to read 6, iclass 36, count 0 2006.189.08:26:52.82#ibcon#read 6, iclass 36, count 0 2006.189.08:26:52.82#ibcon#end of sib2, iclass 36, count 0 2006.189.08:26:52.82#ibcon#*mode == 0, iclass 36, count 0 2006.189.08:26:52.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.189.08:26:52.82#ibcon#[27=BW32\r\n] 2006.189.08:26:52.82#ibcon#*before write, iclass 36, count 0 2006.189.08:26:52.82#ibcon#enter sib2, iclass 36, count 0 2006.189.08:26:52.82#ibcon#flushed, iclass 36, count 0 2006.189.08:26:52.82#ibcon#about to write, iclass 36, count 0 2006.189.08:26:52.82#ibcon#wrote, iclass 36, count 0 2006.189.08:26:52.82#ibcon#about to read 3, iclass 36, count 0 2006.189.08:26:52.85#ibcon#read 3, iclass 36, count 0 2006.189.08:26:52.85#ibcon#about to read 4, iclass 36, count 0 2006.189.08:26:52.85#ibcon#read 4, iclass 36, count 0 2006.189.08:26:52.85#ibcon#about to read 5, iclass 36, count 0 2006.189.08:26:52.85#ibcon#read 5, iclass 36, count 0 2006.189.08:26:52.85#ibcon#about to read 6, iclass 36, count 0 2006.189.08:26:52.85#ibcon#read 6, iclass 36, count 0 2006.189.08:26:52.85#ibcon#end of sib2, iclass 36, count 0 2006.189.08:26:52.85#ibcon#*after write, iclass 36, count 0 2006.189.08:26:52.85#ibcon#*before return 0, iclass 36, count 0 2006.189.08:26:52.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:26:52.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.189.08:26:52.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.189.08:26:52.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.189.08:26:52.85$4f8m12a/ifd4f 2006.189.08:26:52.85$ifd4f/lo= 2006.189.08:26:52.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.189.08:26:52.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.189.08:26:52.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.189.08:26:52.85$ifd4f/patch= 2006.189.08:26:52.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.189.08:26:52.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.189.08:26:52.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.189.08:26:52.85$4f8m12a/"form=m,16.000,1:2 2006.189.08:26:52.85$4f8m12a/"tpicd 2006.189.08:26:52.85$4f8m12a/echo=off 2006.189.08:26:52.85$4f8m12a/xlog=off 2006.189.08:26:52.85:!2006.189.08:27:20 2006.189.08:27:04.13#trakl#Source acquired 2006.189.08:27:05.13#flagr#flagr/antenna,acquired 2006.189.08:27:20.00:preob 2006.189.08:27:21.13/onsource/TRACKING 2006.189.08:27:21.13:!2006.189.08:27:30 2006.189.08:27:30.00:data_valid=on 2006.189.08:27:30.00:midob 2006.189.08:27:30.13/onsource/TRACKING 2006.189.08:27:30.13/wx/25.25,1009.2,92 2006.189.08:27:30.29/cable/+6.4584E-03 2006.189.08:27:31.38/va/01,08,usb,yes,42,44 2006.189.08:27:31.38/va/02,07,usb,yes,42,44 2006.189.08:27:31.38/va/03,06,usb,yes,44,44 2006.189.08:27:31.38/va/04,07,usb,yes,43,46 2006.189.08:27:31.38/va/05,07,usb,yes,46,49 2006.189.08:27:31.38/va/06,06,usb,yes,45,44 2006.189.08:27:31.38/va/07,06,usb,yes,45,45 2006.189.08:27:31.38/va/08,06,usb,yes,48,47 2006.189.08:27:31.61/valo/01,532.99,yes,locked 2006.189.08:27:31.61/valo/02,572.99,yes,locked 2006.189.08:27:31.61/valo/03,672.99,yes,locked 2006.189.08:27:31.61/valo/04,832.99,yes,locked 2006.189.08:27:31.61/valo/05,652.99,yes,locked 2006.189.08:27:31.61/valo/06,772.99,yes,locked 2006.189.08:27:31.61/valo/07,832.99,yes,locked 2006.189.08:27:31.61/valo/08,852.99,yes,locked 2006.189.08:27:32.70/vb/01,04,usb,yes,37,35 2006.189.08:27:32.70/vb/02,04,usb,yes,38,40 2006.189.08:27:32.70/vb/03,04,usb,yes,34,39 2006.189.08:27:32.70/vb/04,04,usb,yes,36,36 2006.189.08:27:32.70/vb/05,04,usb,yes,34,38 2006.189.08:27:32.70/vb/06,04,usb,yes,35,38 2006.189.08:27:32.70/vb/07,04,usb,yes,38,37 2006.189.08:27:32.70/vb/08,04,usb,yes,34,38 2006.189.08:27:32.94/vblo/01,632.99,yes,locked 2006.189.08:27:32.94/vblo/02,640.99,yes,locked 2006.189.08:27:32.94/vblo/03,656.99,yes,locked 2006.189.08:27:32.94/vblo/04,712.99,yes,locked 2006.189.08:27:32.94/vblo/05,744.99,yes,locked 2006.189.08:27:32.94/vblo/06,752.99,yes,locked 2006.189.08:27:32.94/vblo/07,734.99,yes,locked 2006.189.08:27:32.94/vblo/08,744.99,yes,locked 2006.189.08:27:33.09/vabw/8 2006.189.08:27:33.24/vbbw/8 2006.189.08:27:33.33/xfe/off,on,14.7 2006.189.08:27:33.71/ifatt/23,28,28,28 2006.189.08:27:34.08/fmout-gps/S +2.98E-07 2006.189.08:27:34.16:!2006.189.08:28:30 2006.189.08:28:30.01:data_valid=off 2006.189.08:28:30.01:postob 2006.189.08:28:30.10/cable/+6.4578E-03 2006.189.08:28:30.11/wx/25.23,1009.2,92 2006.189.08:28:31.08/fmout-gps/S +2.98E-07 2006.189.08:28:31.08:checkk5last 2006.189.08:28:31.09&checkk5last/chk_obsdata=1 2006.189.08:28:31.09&checkk5last/chk_obsdata=2 2006.189.08:28:31.10&checkk5last/chk_obsdata=3 2006.189.08:28:31.10&checkk5last/chk_obsdata=4 2006.189.08:28:31.10&checkk5last/k5log=1 2006.189.08:28:31.11&checkk5last/k5log=2 2006.189.08:28:31.11&checkk5last/k5log=3 2006.189.08:28:31.11&checkk5last/k5log=4 2006.189.08:28:31.12&checkk5last/obsinfo 2006.189.08:28:31.51/chk_obsdata//k5ts1/T1890827??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:28:31.88/chk_obsdata//k5ts2/T1890827??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:28:32.27/chk_obsdata//k5ts3/T1890827??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:28:32.64/chk_obsdata//k5ts4/T1890827??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.189.08:28:33.34/k5log//k5ts1_log_newline 2006.189.08:28:34.04/k5log//k5ts2_log_newline 2006.189.08:28:34.74/k5log//k5ts3_log_newline 2006.189.08:28:35.43/k5log//k5ts4_log_newline 2006.189.08:28:35.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.189.08:28:35.46:"sched_end 2006.189.08:28:35.46:source=idle 2006.189.08:28:36.14:stow 2006.189.08:28:36.14&stow/source=idle 2006.189.08:28:36.14&stow/"this is stow command. 2006.189.08:28:36.14&stow/antenna=m3 2006.189.08:28:36.14#flagr#flagr/antenna,new-source 2006.189.08:28:39.01:!+10m 2006.189.08:38:39.02:standby 2006.189.08:38:39.02&standby/"this is standby command. 2006.189.08:38:39.02&standby/antenna=m0 2006.189.08:38:40.01:sy=cp /usr2/log/k06189ts.log /usr2/log_backup/ 2006.189.08:38:40.10:log=u06190ts