2006.182.08:41:21.11:Log Opened: Mark IV Field System Version 9.7.7 2006.182.08:41:21.11:location,TSUKUB32,-140.09,36.10,61.0 2006.182.08:41:21.11:horizon1,0.,5.,360. 2006.182.08:41:21.12:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.182.08:41:21.12:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.182.08:41:21.12:drivev11,330,270,no 2006.182.08:41:21.12:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.182.08:41:21.12:drivev13,15.000,268,10.000,10.000,10.000 2006.182.08:41:21.12:drivev21,330,270,no 2006.182.08:41:21.12:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.182.08:41:21.12:drivev23,15.000,268,10.000,10.000,10.000 2006.182.08:41:21.12:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.182.08:41:21.12:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.182.08:41:21.12:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.182.08:41:21.12:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.182.08:41:21.12:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.182.08:41:21.12:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.182.08:41:21.12:time,-0.364,101.533,rate 2006.182.08:41:21.12:flagr,200 2006.182.08:41:21.12:proc=k06183ts 2006.182.08:41:21.12:" k06183 2006 tsukub32 t ts 2006.182.08:41:21.12:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.182.08:41:21.12:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.182.08:41:21.12:" 108 tsukub32 14 17400 2006.182.08:41:21.12:" drudg version 050216 compiled under fs 9.7.07 2006.182.08:41:21.12:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.182.08:41:21.12:!2006.183.06:29:50 2006.183.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.183.06:29:50.02:!2006.183.07:19:50 2006.183.07:19:50.00:unstow 2006.183.07:19:50.00&unstow/antenna=e 2006.183.07:19:50.00&unstow/!+10s 2006.183.07:19:50.00&unstow/antenna=m2 2006.183.07:20:02.01:scan_name=183-0730,k06183,60 2006.183.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.183.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.183.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.183.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.183.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.183.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.183.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.183.07:20:03.14:ready_k5 2006.183.07:20:03.14&ready_k5/obsinfo=st 2006.183.07:20:03.14&ready_k5/autoobs=1 2006.183.07:20:03.14&ready_k5/autoobs=2 2006.183.07:20:03.14&ready_k5/autoobs=3 2006.183.07:20:03.14&ready_k5/autoobs=4 2006.183.07:20:03.14&ready_k5/obsinfo 2006.183.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.183.07:20:03.14#flagr#flagr/antenna,new-source 2006.183.07:20:06.34/autoobs//k5ts1/ autoobs started! 2006.183.07:20:09.47/autoobs//k5ts2/ autoobs started! 2006.183.07:20:12.59/autoobs//k5ts3/ autoobs started! 2006.183.07:20:15.71/autoobs//k5ts4/ autoobs started! 2006.183.07:20:15.74/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:20:15.74:4f8m12a=1 2006.183.07:20:15.74&4f8m12a/xlog=on 2006.183.07:20:15.74&4f8m12a/echo=on 2006.183.07:20:15.74&4f8m12a/pcalon 2006.183.07:20:15.74&4f8m12a/"tpicd=stop 2006.183.07:20:15.74&4f8m12a/vc4f8 2006.183.07:20:15.74&4f8m12a/ifd4f 2006.183.07:20:15.74&4f8m12a/"form=m,16.000,1:2 2006.183.07:20:15.74&4f8m12a/"tpicd 2006.183.07:20:15.74&4f8m12a/echo=off 2006.183.07:20:15.74&4f8m12a/xlog=off 2006.183.07:20:15.74$4f8m12a/echo=on 2006.183.07:20:15.74$4f8m12a/pcalon 2006.183.07:20:15.74&pcalon/"no phase cal control is implemented here 2006.183.07:20:15.74$pcalon/"no phase cal control is implemented here 2006.183.07:20:15.74$4f8m12a/"tpicd=stop 2006.183.07:20:15.74$4f8m12a/vc4f8 2006.183.07:20:15.74&vc4f8/valo=1,532.99 2006.183.07:20:15.74&vc4f8/va=1,8 2006.183.07:20:15.74&vc4f8/valo=2,572.99 2006.183.07:20:15.74&vc4f8/va=2,7 2006.183.07:20:15.74&vc4f8/valo=3,672.99 2006.183.07:20:15.74&vc4f8/va=3,6 2006.183.07:20:15.74&vc4f8/valo=4,832.99 2006.183.07:20:15.74&vc4f8/va=4,7 2006.183.07:20:15.74&vc4f8/valo=5,652.99 2006.183.07:20:15.74&vc4f8/va=5,7 2006.183.07:20:15.74&vc4f8/valo=6,772.99 2006.183.07:20:15.74&vc4f8/va=6,6 2006.183.07:20:15.74&vc4f8/valo=7,832.99 2006.183.07:20:15.74&vc4f8/va=7,6 2006.183.07:20:15.74&vc4f8/valo=8,852.99 2006.183.07:20:15.74&vc4f8/va=8,7 2006.183.07:20:15.74&vc4f8/vblo=1,632.99 2006.183.07:20:15.74&vc4f8/vb=1,4 2006.183.07:20:15.74&vc4f8/vblo=2,640.99 2006.183.07:20:15.74&vc4f8/vb=2,4 2006.183.07:20:15.74&vc4f8/vblo=3,656.99 2006.183.07:20:15.74&vc4f8/vb=3,4 2006.183.07:20:15.74&vc4f8/vblo=4,712.99 2006.183.07:20:15.74&vc4f8/vb=4,4 2006.183.07:20:15.74&vc4f8/vblo=5,744.99 2006.183.07:20:15.74&vc4f8/vb=5,4 2006.183.07:20:15.74&vc4f8/vblo=6,752.99 2006.183.07:20:15.74&vc4f8/vb=6,4 2006.183.07:20:15.74&vc4f8/vabw=wide 2006.183.07:20:15.74&vc4f8/vbbw=wide 2006.183.07:20:15.74$vc4f8/valo=1,532.99 2006.183.07:20:15.74#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.07:20:15.74#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.07:20:15.74#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:15.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:15.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:15.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:15.74#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:20:15.74#ibcon#first serial, iclass 20, count 0 2006.183.07:20:15.74#ibcon#enter sib2, iclass 20, count 0 2006.183.07:20:15.74#ibcon#flushed, iclass 20, count 0 2006.183.07:20:15.74#ibcon#about to write, iclass 20, count 0 2006.183.07:20:15.74#ibcon#wrote, iclass 20, count 0 2006.183.07:20:15.74#ibcon#about to read 3, iclass 20, count 0 2006.183.07:20:15.78#ibcon#read 3, iclass 20, count 0 2006.183.07:20:15.78#ibcon#about to read 4, iclass 20, count 0 2006.183.07:20:15.78#ibcon#read 4, iclass 20, count 0 2006.183.07:20:15.78#ibcon#about to read 5, iclass 20, count 0 2006.183.07:20:15.78#ibcon#read 5, iclass 20, count 0 2006.183.07:20:15.78#ibcon#about to read 6, iclass 20, count 0 2006.183.07:20:15.78#ibcon#read 6, iclass 20, count 0 2006.183.07:20:15.78#ibcon#end of sib2, iclass 20, count 0 2006.183.07:20:15.78#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:20:15.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:20:15.78#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:20:15.78#ibcon#*before write, iclass 20, count 0 2006.183.07:20:15.78#ibcon#enter sib2, iclass 20, count 0 2006.183.07:20:15.78#ibcon#flushed, iclass 20, count 0 2006.183.07:20:15.78#ibcon#about to write, iclass 20, count 0 2006.183.07:20:15.78#ibcon#wrote, iclass 20, count 0 2006.183.07:20:15.78#ibcon#about to read 3, iclass 20, count 0 2006.183.07:20:15.83#ibcon#read 3, iclass 20, count 0 2006.183.07:20:15.83#ibcon#about to read 4, iclass 20, count 0 2006.183.07:20:15.83#ibcon#read 4, iclass 20, count 0 2006.183.07:20:15.83#ibcon#about to read 5, iclass 20, count 0 2006.183.07:20:15.83#ibcon#read 5, iclass 20, count 0 2006.183.07:20:15.83#ibcon#about to read 6, iclass 20, count 0 2006.183.07:20:15.83#ibcon#read 6, iclass 20, count 0 2006.183.07:20:15.83#ibcon#end of sib2, iclass 20, count 0 2006.183.07:20:15.83#ibcon#*after write, iclass 20, count 0 2006.183.07:20:15.83#ibcon#*before return 0, iclass 20, count 0 2006.183.07:20:15.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:15.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:15.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:20:15.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:20:15.83$vc4f8/va=1,8 2006.183.07:20:15.83#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.07:20:15.83#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.07:20:15.83#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:15.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:15.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:15.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:15.83#ibcon#enter wrdev, iclass 22, count 2 2006.183.07:20:15.83#ibcon#first serial, iclass 22, count 2 2006.183.07:20:15.83#ibcon#enter sib2, iclass 22, count 2 2006.183.07:20:15.83#ibcon#flushed, iclass 22, count 2 2006.183.07:20:15.83#ibcon#about to write, iclass 22, count 2 2006.183.07:20:15.83#ibcon#wrote, iclass 22, count 2 2006.183.07:20:15.83#ibcon#about to read 3, iclass 22, count 2 2006.183.07:20:15.85#ibcon#read 3, iclass 22, count 2 2006.183.07:20:15.85#ibcon#about to read 4, iclass 22, count 2 2006.183.07:20:15.85#ibcon#read 4, iclass 22, count 2 2006.183.07:20:15.85#ibcon#about to read 5, iclass 22, count 2 2006.183.07:20:15.85#ibcon#read 5, iclass 22, count 2 2006.183.07:20:15.85#ibcon#about to read 6, iclass 22, count 2 2006.183.07:20:15.85#ibcon#read 6, iclass 22, count 2 2006.183.07:20:15.85#ibcon#end of sib2, iclass 22, count 2 2006.183.07:20:15.85#ibcon#*mode == 0, iclass 22, count 2 2006.183.07:20:15.85#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.07:20:15.85#ibcon#[25=AT01-08\r\n] 2006.183.07:20:15.85#ibcon#*before write, iclass 22, count 2 2006.183.07:20:15.85#ibcon#enter sib2, iclass 22, count 2 2006.183.07:20:15.85#ibcon#flushed, iclass 22, count 2 2006.183.07:20:15.85#ibcon#about to write, iclass 22, count 2 2006.183.07:20:15.85#ibcon#wrote, iclass 22, count 2 2006.183.07:20:15.85#ibcon#about to read 3, iclass 22, count 2 2006.183.07:20:15.88#ibcon#read 3, iclass 22, count 2 2006.183.07:20:15.88#ibcon#about to read 4, iclass 22, count 2 2006.183.07:20:15.88#ibcon#read 4, iclass 22, count 2 2006.183.07:20:15.88#ibcon#about to read 5, iclass 22, count 2 2006.183.07:20:15.88#ibcon#read 5, iclass 22, count 2 2006.183.07:20:15.88#ibcon#about to read 6, iclass 22, count 2 2006.183.07:20:15.88#ibcon#read 6, iclass 22, count 2 2006.183.07:20:15.88#ibcon#end of sib2, iclass 22, count 2 2006.183.07:20:15.88#ibcon#*after write, iclass 22, count 2 2006.183.07:20:15.88#ibcon#*before return 0, iclass 22, count 2 2006.183.07:20:15.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:15.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:15.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.07:20:15.88#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:15.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:16.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:16.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:16.00#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:20:16.00#ibcon#first serial, iclass 22, count 0 2006.183.07:20:16.00#ibcon#enter sib2, iclass 22, count 0 2006.183.07:20:16.00#ibcon#flushed, iclass 22, count 0 2006.183.07:20:16.00#ibcon#about to write, iclass 22, count 0 2006.183.07:20:16.00#ibcon#wrote, iclass 22, count 0 2006.183.07:20:16.00#ibcon#about to read 3, iclass 22, count 0 2006.183.07:20:16.02#ibcon#read 3, iclass 22, count 0 2006.183.07:20:16.02#ibcon#about to read 4, iclass 22, count 0 2006.183.07:20:16.02#ibcon#read 4, iclass 22, count 0 2006.183.07:20:16.02#ibcon#about to read 5, iclass 22, count 0 2006.183.07:20:16.02#ibcon#read 5, iclass 22, count 0 2006.183.07:20:16.02#ibcon#about to read 6, iclass 22, count 0 2006.183.07:20:16.02#ibcon#read 6, iclass 22, count 0 2006.183.07:20:16.02#ibcon#end of sib2, iclass 22, count 0 2006.183.07:20:16.02#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:20:16.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:20:16.02#ibcon#[25=USB\r\n] 2006.183.07:20:16.02#ibcon#*before write, iclass 22, count 0 2006.183.07:20:16.02#ibcon#enter sib2, iclass 22, count 0 2006.183.07:20:16.02#ibcon#flushed, iclass 22, count 0 2006.183.07:20:16.02#ibcon#about to write, iclass 22, count 0 2006.183.07:20:16.02#ibcon#wrote, iclass 22, count 0 2006.183.07:20:16.02#ibcon#about to read 3, iclass 22, count 0 2006.183.07:20:16.05#ibcon#read 3, iclass 22, count 0 2006.183.07:20:16.05#ibcon#about to read 4, iclass 22, count 0 2006.183.07:20:16.05#ibcon#read 4, iclass 22, count 0 2006.183.07:20:16.05#ibcon#about to read 5, iclass 22, count 0 2006.183.07:20:16.05#ibcon#read 5, iclass 22, count 0 2006.183.07:20:16.05#ibcon#about to read 6, iclass 22, count 0 2006.183.07:20:16.05#ibcon#read 6, iclass 22, count 0 2006.183.07:20:16.05#ibcon#end of sib2, iclass 22, count 0 2006.183.07:20:16.05#ibcon#*after write, iclass 22, count 0 2006.183.07:20:16.05#ibcon#*before return 0, iclass 22, count 0 2006.183.07:20:16.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:16.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:16.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:20:16.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:20:16.05$vc4f8/valo=2,572.99 2006.183.07:20:16.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.07:20:16.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.07:20:16.05#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:16.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:16.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:16.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:16.05#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:20:16.05#ibcon#first serial, iclass 24, count 0 2006.183.07:20:16.05#ibcon#enter sib2, iclass 24, count 0 2006.183.07:20:16.05#ibcon#flushed, iclass 24, count 0 2006.183.07:20:16.05#ibcon#about to write, iclass 24, count 0 2006.183.07:20:16.05#ibcon#wrote, iclass 24, count 0 2006.183.07:20:16.05#ibcon#about to read 3, iclass 24, count 0 2006.183.07:20:16.07#ibcon#read 3, iclass 24, count 0 2006.183.07:20:16.07#ibcon#about to read 4, iclass 24, count 0 2006.183.07:20:16.07#ibcon#read 4, iclass 24, count 0 2006.183.07:20:16.07#ibcon#about to read 5, iclass 24, count 0 2006.183.07:20:16.07#ibcon#read 5, iclass 24, count 0 2006.183.07:20:16.07#ibcon#about to read 6, iclass 24, count 0 2006.183.07:20:16.07#ibcon#read 6, iclass 24, count 0 2006.183.07:20:16.08#ibcon#end of sib2, iclass 24, count 0 2006.183.07:20:16.08#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:20:16.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:20:16.08#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:20:16.08#ibcon#*before write, iclass 24, count 0 2006.183.07:20:16.08#ibcon#enter sib2, iclass 24, count 0 2006.183.07:20:16.08#ibcon#flushed, iclass 24, count 0 2006.183.07:20:16.08#ibcon#about to write, iclass 24, count 0 2006.183.07:20:16.08#ibcon#wrote, iclass 24, count 0 2006.183.07:20:16.08#ibcon#about to read 3, iclass 24, count 0 2006.183.07:20:16.12#ibcon#read 3, iclass 24, count 0 2006.183.07:20:16.12#ibcon#about to read 4, iclass 24, count 0 2006.183.07:20:16.12#ibcon#read 4, iclass 24, count 0 2006.183.07:20:16.12#ibcon#about to read 5, iclass 24, count 0 2006.183.07:20:16.12#ibcon#read 5, iclass 24, count 0 2006.183.07:20:16.12#ibcon#about to read 6, iclass 24, count 0 2006.183.07:20:16.12#ibcon#read 6, iclass 24, count 0 2006.183.07:20:16.12#ibcon#end of sib2, iclass 24, count 0 2006.183.07:20:16.12#ibcon#*after write, iclass 24, count 0 2006.183.07:20:16.12#ibcon#*before return 0, iclass 24, count 0 2006.183.07:20:16.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:16.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:16.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:20:16.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:20:16.12$vc4f8/va=2,7 2006.183.07:20:16.12#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.07:20:16.12#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.07:20:16.12#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:16.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:16.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:16.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:16.17#ibcon#enter wrdev, iclass 26, count 2 2006.183.07:20:16.17#ibcon#first serial, iclass 26, count 2 2006.183.07:20:16.17#ibcon#enter sib2, iclass 26, count 2 2006.183.07:20:16.17#ibcon#flushed, iclass 26, count 2 2006.183.07:20:16.17#ibcon#about to write, iclass 26, count 2 2006.183.07:20:16.17#ibcon#wrote, iclass 26, count 2 2006.183.07:20:16.17#ibcon#about to read 3, iclass 26, count 2 2006.183.07:20:16.19#ibcon#read 3, iclass 26, count 2 2006.183.07:20:16.19#ibcon#about to read 4, iclass 26, count 2 2006.183.07:20:16.19#ibcon#read 4, iclass 26, count 2 2006.183.07:20:16.19#ibcon#about to read 5, iclass 26, count 2 2006.183.07:20:16.19#ibcon#read 5, iclass 26, count 2 2006.183.07:20:16.19#ibcon#about to read 6, iclass 26, count 2 2006.183.07:20:16.19#ibcon#read 6, iclass 26, count 2 2006.183.07:20:16.19#ibcon#end of sib2, iclass 26, count 2 2006.183.07:20:16.19#ibcon#*mode == 0, iclass 26, count 2 2006.183.07:20:16.19#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.07:20:16.19#ibcon#[25=AT02-07\r\n] 2006.183.07:20:16.19#ibcon#*before write, iclass 26, count 2 2006.183.07:20:16.19#ibcon#enter sib2, iclass 26, count 2 2006.183.07:20:16.19#ibcon#flushed, iclass 26, count 2 2006.183.07:20:16.19#ibcon#about to write, iclass 26, count 2 2006.183.07:20:16.19#ibcon#wrote, iclass 26, count 2 2006.183.07:20:16.19#ibcon#about to read 3, iclass 26, count 2 2006.183.07:20:16.22#ibcon#read 3, iclass 26, count 2 2006.183.07:20:16.22#ibcon#about to read 4, iclass 26, count 2 2006.183.07:20:16.22#ibcon#read 4, iclass 26, count 2 2006.183.07:20:16.22#ibcon#about to read 5, iclass 26, count 2 2006.183.07:20:16.22#ibcon#read 5, iclass 26, count 2 2006.183.07:20:16.22#ibcon#about to read 6, iclass 26, count 2 2006.183.07:20:16.22#ibcon#read 6, iclass 26, count 2 2006.183.07:20:16.22#ibcon#end of sib2, iclass 26, count 2 2006.183.07:20:16.22#ibcon#*after write, iclass 26, count 2 2006.183.07:20:16.22#ibcon#*before return 0, iclass 26, count 2 2006.183.07:20:16.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:16.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:16.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.07:20:16.22#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:16.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:16.34#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:16.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:16.34#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:20:16.34#ibcon#first serial, iclass 26, count 0 2006.183.07:20:16.34#ibcon#enter sib2, iclass 26, count 0 2006.183.07:20:16.34#ibcon#flushed, iclass 26, count 0 2006.183.07:20:16.34#ibcon#about to write, iclass 26, count 0 2006.183.07:20:16.34#ibcon#wrote, iclass 26, count 0 2006.183.07:20:16.34#ibcon#about to read 3, iclass 26, count 0 2006.183.07:20:16.36#ibcon#read 3, iclass 26, count 0 2006.183.07:20:16.36#ibcon#about to read 4, iclass 26, count 0 2006.183.07:20:16.36#ibcon#read 4, iclass 26, count 0 2006.183.07:20:16.36#ibcon#about to read 5, iclass 26, count 0 2006.183.07:20:16.36#ibcon#read 5, iclass 26, count 0 2006.183.07:20:16.36#ibcon#about to read 6, iclass 26, count 0 2006.183.07:20:16.36#ibcon#read 6, iclass 26, count 0 2006.183.07:20:16.36#ibcon#end of sib2, iclass 26, count 0 2006.183.07:20:16.36#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:20:16.36#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:20:16.36#ibcon#[25=USB\r\n] 2006.183.07:20:16.36#ibcon#*before write, iclass 26, count 0 2006.183.07:20:16.36#ibcon#enter sib2, iclass 26, count 0 2006.183.07:20:16.36#ibcon#flushed, iclass 26, count 0 2006.183.07:20:16.36#ibcon#about to write, iclass 26, count 0 2006.183.07:20:16.36#ibcon#wrote, iclass 26, count 0 2006.183.07:20:16.36#ibcon#about to read 3, iclass 26, count 0 2006.183.07:20:16.39#ibcon#read 3, iclass 26, count 0 2006.183.07:20:16.39#ibcon#about to read 4, iclass 26, count 0 2006.183.07:20:16.39#ibcon#read 4, iclass 26, count 0 2006.183.07:20:16.39#ibcon#about to read 5, iclass 26, count 0 2006.183.07:20:16.39#ibcon#read 5, iclass 26, count 0 2006.183.07:20:16.39#ibcon#about to read 6, iclass 26, count 0 2006.183.07:20:16.39#ibcon#read 6, iclass 26, count 0 2006.183.07:20:16.39#ibcon#end of sib2, iclass 26, count 0 2006.183.07:20:16.39#ibcon#*after write, iclass 26, count 0 2006.183.07:20:16.39#ibcon#*before return 0, iclass 26, count 0 2006.183.07:20:16.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:16.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:16.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:20:16.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:20:16.39$vc4f8/valo=3,672.99 2006.183.07:20:16.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.07:20:16.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.07:20:16.39#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:16.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:16.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:16.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:16.39#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:20:16.39#ibcon#first serial, iclass 28, count 0 2006.183.07:20:16.39#ibcon#enter sib2, iclass 28, count 0 2006.183.07:20:16.39#ibcon#flushed, iclass 28, count 0 2006.183.07:20:16.39#ibcon#about to write, iclass 28, count 0 2006.183.07:20:16.39#ibcon#wrote, iclass 28, count 0 2006.183.07:20:16.39#ibcon#about to read 3, iclass 28, count 0 2006.183.07:20:16.41#ibcon#read 3, iclass 28, count 0 2006.183.07:20:16.41#ibcon#about to read 4, iclass 28, count 0 2006.183.07:20:16.41#ibcon#read 4, iclass 28, count 0 2006.183.07:20:16.41#ibcon#about to read 5, iclass 28, count 0 2006.183.07:20:16.41#ibcon#read 5, iclass 28, count 0 2006.183.07:20:16.41#ibcon#about to read 6, iclass 28, count 0 2006.183.07:20:16.41#ibcon#read 6, iclass 28, count 0 2006.183.07:20:16.41#ibcon#end of sib2, iclass 28, count 0 2006.183.07:20:16.41#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:20:16.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:20:16.41#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:20:16.41#ibcon#*before write, iclass 28, count 0 2006.183.07:20:16.41#ibcon#enter sib2, iclass 28, count 0 2006.183.07:20:16.41#ibcon#flushed, iclass 28, count 0 2006.183.07:20:16.41#ibcon#about to write, iclass 28, count 0 2006.183.07:20:16.41#ibcon#wrote, iclass 28, count 0 2006.183.07:20:16.41#ibcon#about to read 3, iclass 28, count 0 2006.183.07:20:16.46#ibcon#read 3, iclass 28, count 0 2006.183.07:20:16.46#ibcon#about to read 4, iclass 28, count 0 2006.183.07:20:16.46#ibcon#read 4, iclass 28, count 0 2006.183.07:20:16.46#ibcon#about to read 5, iclass 28, count 0 2006.183.07:20:16.46#ibcon#read 5, iclass 28, count 0 2006.183.07:20:16.46#ibcon#about to read 6, iclass 28, count 0 2006.183.07:20:16.46#ibcon#read 6, iclass 28, count 0 2006.183.07:20:16.46#ibcon#end of sib2, iclass 28, count 0 2006.183.07:20:16.46#ibcon#*after write, iclass 28, count 0 2006.183.07:20:16.46#ibcon#*before return 0, iclass 28, count 0 2006.183.07:20:16.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:16.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:16.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:20:16.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:20:16.46$vc4f8/va=3,6 2006.183.07:20:16.46#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.07:20:16.46#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.07:20:16.46#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:16.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:16.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:16.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:16.51#ibcon#enter wrdev, iclass 30, count 2 2006.183.07:20:16.51#ibcon#first serial, iclass 30, count 2 2006.183.07:20:16.51#ibcon#enter sib2, iclass 30, count 2 2006.183.07:20:16.51#ibcon#flushed, iclass 30, count 2 2006.183.07:20:16.51#ibcon#about to write, iclass 30, count 2 2006.183.07:20:16.51#ibcon#wrote, iclass 30, count 2 2006.183.07:20:16.51#ibcon#about to read 3, iclass 30, count 2 2006.183.07:20:16.53#ibcon#read 3, iclass 30, count 2 2006.183.07:20:16.53#ibcon#about to read 4, iclass 30, count 2 2006.183.07:20:16.53#ibcon#read 4, iclass 30, count 2 2006.183.07:20:16.53#ibcon#about to read 5, iclass 30, count 2 2006.183.07:20:16.53#ibcon#read 5, iclass 30, count 2 2006.183.07:20:16.53#ibcon#about to read 6, iclass 30, count 2 2006.183.07:20:16.53#ibcon#read 6, iclass 30, count 2 2006.183.07:20:16.53#ibcon#end of sib2, iclass 30, count 2 2006.183.07:20:16.53#ibcon#*mode == 0, iclass 30, count 2 2006.183.07:20:16.53#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.07:20:16.53#ibcon#[25=AT03-06\r\n] 2006.183.07:20:16.53#ibcon#*before write, iclass 30, count 2 2006.183.07:20:16.53#ibcon#enter sib2, iclass 30, count 2 2006.183.07:20:16.53#ibcon#flushed, iclass 30, count 2 2006.183.07:20:16.53#ibcon#about to write, iclass 30, count 2 2006.183.07:20:16.53#ibcon#wrote, iclass 30, count 2 2006.183.07:20:16.53#ibcon#about to read 3, iclass 30, count 2 2006.183.07:20:16.56#ibcon#read 3, iclass 30, count 2 2006.183.07:20:16.56#ibcon#about to read 4, iclass 30, count 2 2006.183.07:20:16.56#ibcon#read 4, iclass 30, count 2 2006.183.07:20:16.56#ibcon#about to read 5, iclass 30, count 2 2006.183.07:20:16.56#ibcon#read 5, iclass 30, count 2 2006.183.07:20:16.56#ibcon#about to read 6, iclass 30, count 2 2006.183.07:20:16.56#ibcon#read 6, iclass 30, count 2 2006.183.07:20:16.56#ibcon#end of sib2, iclass 30, count 2 2006.183.07:20:16.56#ibcon#*after write, iclass 30, count 2 2006.183.07:20:16.56#ibcon#*before return 0, iclass 30, count 2 2006.183.07:20:16.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:16.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:16.56#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.07:20:16.56#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:16.56#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:16.68#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:16.68#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:16.68#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:20:16.68#ibcon#first serial, iclass 30, count 0 2006.183.07:20:16.68#ibcon#enter sib2, iclass 30, count 0 2006.183.07:20:16.68#ibcon#flushed, iclass 30, count 0 2006.183.07:20:16.68#ibcon#about to write, iclass 30, count 0 2006.183.07:20:16.68#ibcon#wrote, iclass 30, count 0 2006.183.07:20:16.68#ibcon#about to read 3, iclass 30, count 0 2006.183.07:20:16.70#ibcon#read 3, iclass 30, count 0 2006.183.07:20:16.70#ibcon#about to read 4, iclass 30, count 0 2006.183.07:20:16.70#ibcon#read 4, iclass 30, count 0 2006.183.07:20:16.70#ibcon#about to read 5, iclass 30, count 0 2006.183.07:20:16.70#ibcon#read 5, iclass 30, count 0 2006.183.07:20:16.70#ibcon#about to read 6, iclass 30, count 0 2006.183.07:20:16.70#ibcon#read 6, iclass 30, count 0 2006.183.07:20:16.70#ibcon#end of sib2, iclass 30, count 0 2006.183.07:20:16.70#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:20:16.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:20:16.70#ibcon#[25=USB\r\n] 2006.183.07:20:16.70#ibcon#*before write, iclass 30, count 0 2006.183.07:20:16.70#ibcon#enter sib2, iclass 30, count 0 2006.183.07:20:16.70#ibcon#flushed, iclass 30, count 0 2006.183.07:20:16.70#ibcon#about to write, iclass 30, count 0 2006.183.07:20:16.70#ibcon#wrote, iclass 30, count 0 2006.183.07:20:16.70#ibcon#about to read 3, iclass 30, count 0 2006.183.07:20:16.73#ibcon#read 3, iclass 30, count 0 2006.183.07:20:16.73#ibcon#about to read 4, iclass 30, count 0 2006.183.07:20:16.73#ibcon#read 4, iclass 30, count 0 2006.183.07:20:16.73#ibcon#about to read 5, iclass 30, count 0 2006.183.07:20:16.73#ibcon#read 5, iclass 30, count 0 2006.183.07:20:16.73#ibcon#about to read 6, iclass 30, count 0 2006.183.07:20:16.73#ibcon#read 6, iclass 30, count 0 2006.183.07:20:16.73#ibcon#end of sib2, iclass 30, count 0 2006.183.07:20:16.73#ibcon#*after write, iclass 30, count 0 2006.183.07:20:16.73#ibcon#*before return 0, iclass 30, count 0 2006.183.07:20:16.73#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:16.73#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:16.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:20:16.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:20:16.73$vc4f8/valo=4,832.99 2006.183.07:20:16.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.07:20:16.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.07:20:16.73#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:16.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:16.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:16.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:16.73#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:20:16.73#ibcon#first serial, iclass 32, count 0 2006.183.07:20:16.73#ibcon#enter sib2, iclass 32, count 0 2006.183.07:20:16.73#ibcon#flushed, iclass 32, count 0 2006.183.07:20:16.73#ibcon#about to write, iclass 32, count 0 2006.183.07:20:16.73#ibcon#wrote, iclass 32, count 0 2006.183.07:20:16.73#ibcon#about to read 3, iclass 32, count 0 2006.183.07:20:16.75#ibcon#read 3, iclass 32, count 0 2006.183.07:20:16.75#ibcon#about to read 4, iclass 32, count 0 2006.183.07:20:16.75#ibcon#read 4, iclass 32, count 0 2006.183.07:20:16.75#ibcon#about to read 5, iclass 32, count 0 2006.183.07:20:16.75#ibcon#read 5, iclass 32, count 0 2006.183.07:20:16.75#ibcon#about to read 6, iclass 32, count 0 2006.183.07:20:16.75#ibcon#read 6, iclass 32, count 0 2006.183.07:20:16.75#ibcon#end of sib2, iclass 32, count 0 2006.183.07:20:16.75#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:20:16.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:20:16.75#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:20:16.75#ibcon#*before write, iclass 32, count 0 2006.183.07:20:16.75#ibcon#enter sib2, iclass 32, count 0 2006.183.07:20:16.75#ibcon#flushed, iclass 32, count 0 2006.183.07:20:16.75#ibcon#about to write, iclass 32, count 0 2006.183.07:20:16.75#ibcon#wrote, iclass 32, count 0 2006.183.07:20:16.75#ibcon#about to read 3, iclass 32, count 0 2006.183.07:20:16.80#ibcon#read 3, iclass 32, count 0 2006.183.07:20:16.80#ibcon#about to read 4, iclass 32, count 0 2006.183.07:20:16.80#ibcon#read 4, iclass 32, count 0 2006.183.07:20:16.80#ibcon#about to read 5, iclass 32, count 0 2006.183.07:20:16.80#ibcon#read 5, iclass 32, count 0 2006.183.07:20:16.80#ibcon#about to read 6, iclass 32, count 0 2006.183.07:20:16.80#ibcon#read 6, iclass 32, count 0 2006.183.07:20:16.80#ibcon#end of sib2, iclass 32, count 0 2006.183.07:20:16.80#ibcon#*after write, iclass 32, count 0 2006.183.07:20:16.80#ibcon#*before return 0, iclass 32, count 0 2006.183.07:20:16.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:16.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:16.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:20:16.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:20:16.80$vc4f8/va=4,7 2006.183.07:20:16.80#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.07:20:16.80#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.07:20:16.80#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:16.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:16.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:16.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:16.85#ibcon#enter wrdev, iclass 34, count 2 2006.183.07:20:16.85#ibcon#first serial, iclass 34, count 2 2006.183.07:20:16.85#ibcon#enter sib2, iclass 34, count 2 2006.183.07:20:16.85#ibcon#flushed, iclass 34, count 2 2006.183.07:20:16.85#ibcon#about to write, iclass 34, count 2 2006.183.07:20:16.85#ibcon#wrote, iclass 34, count 2 2006.183.07:20:16.85#ibcon#about to read 3, iclass 34, count 2 2006.183.07:20:16.87#ibcon#read 3, iclass 34, count 2 2006.183.07:20:16.87#ibcon#about to read 4, iclass 34, count 2 2006.183.07:20:16.87#ibcon#read 4, iclass 34, count 2 2006.183.07:20:16.87#ibcon#about to read 5, iclass 34, count 2 2006.183.07:20:16.87#ibcon#read 5, iclass 34, count 2 2006.183.07:20:16.87#ibcon#about to read 6, iclass 34, count 2 2006.183.07:20:16.87#ibcon#read 6, iclass 34, count 2 2006.183.07:20:16.87#ibcon#end of sib2, iclass 34, count 2 2006.183.07:20:16.87#ibcon#*mode == 0, iclass 34, count 2 2006.183.07:20:16.87#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.07:20:16.87#ibcon#[25=AT04-07\r\n] 2006.183.07:20:16.87#ibcon#*before write, iclass 34, count 2 2006.183.07:20:16.87#ibcon#enter sib2, iclass 34, count 2 2006.183.07:20:16.87#ibcon#flushed, iclass 34, count 2 2006.183.07:20:16.87#ibcon#about to write, iclass 34, count 2 2006.183.07:20:16.87#ibcon#wrote, iclass 34, count 2 2006.183.07:20:16.87#ibcon#about to read 3, iclass 34, count 2 2006.183.07:20:16.90#ibcon#read 3, iclass 34, count 2 2006.183.07:20:16.90#ibcon#about to read 4, iclass 34, count 2 2006.183.07:20:16.90#ibcon#read 4, iclass 34, count 2 2006.183.07:20:16.90#ibcon#about to read 5, iclass 34, count 2 2006.183.07:20:16.90#ibcon#read 5, iclass 34, count 2 2006.183.07:20:16.90#ibcon#about to read 6, iclass 34, count 2 2006.183.07:20:16.90#ibcon#read 6, iclass 34, count 2 2006.183.07:20:16.90#ibcon#end of sib2, iclass 34, count 2 2006.183.07:20:16.90#ibcon#*after write, iclass 34, count 2 2006.183.07:20:16.90#ibcon#*before return 0, iclass 34, count 2 2006.183.07:20:16.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:16.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:16.90#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.07:20:16.90#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:16.90#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:17.02#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:17.02#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:17.02#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:20:17.02#ibcon#first serial, iclass 34, count 0 2006.183.07:20:17.02#ibcon#enter sib2, iclass 34, count 0 2006.183.07:20:17.02#ibcon#flushed, iclass 34, count 0 2006.183.07:20:17.02#ibcon#about to write, iclass 34, count 0 2006.183.07:20:17.02#ibcon#wrote, iclass 34, count 0 2006.183.07:20:17.02#ibcon#about to read 3, iclass 34, count 0 2006.183.07:20:17.04#ibcon#read 3, iclass 34, count 0 2006.183.07:20:17.04#ibcon#about to read 4, iclass 34, count 0 2006.183.07:20:17.04#ibcon#read 4, iclass 34, count 0 2006.183.07:20:17.04#ibcon#about to read 5, iclass 34, count 0 2006.183.07:20:17.04#ibcon#read 5, iclass 34, count 0 2006.183.07:20:17.04#ibcon#about to read 6, iclass 34, count 0 2006.183.07:20:17.04#ibcon#read 6, iclass 34, count 0 2006.183.07:20:17.04#ibcon#end of sib2, iclass 34, count 0 2006.183.07:20:17.04#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:20:17.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:20:17.04#ibcon#[25=USB\r\n] 2006.183.07:20:17.04#ibcon#*before write, iclass 34, count 0 2006.183.07:20:17.04#ibcon#enter sib2, iclass 34, count 0 2006.183.07:20:17.04#ibcon#flushed, iclass 34, count 0 2006.183.07:20:17.04#ibcon#about to write, iclass 34, count 0 2006.183.07:20:17.04#ibcon#wrote, iclass 34, count 0 2006.183.07:20:17.04#ibcon#about to read 3, iclass 34, count 0 2006.183.07:20:17.07#ibcon#read 3, iclass 34, count 0 2006.183.07:20:17.07#ibcon#about to read 4, iclass 34, count 0 2006.183.07:20:17.07#ibcon#read 4, iclass 34, count 0 2006.183.07:20:17.07#ibcon#about to read 5, iclass 34, count 0 2006.183.07:20:17.07#ibcon#read 5, iclass 34, count 0 2006.183.07:20:17.07#ibcon#about to read 6, iclass 34, count 0 2006.183.07:20:17.07#ibcon#read 6, iclass 34, count 0 2006.183.07:20:17.07#ibcon#end of sib2, iclass 34, count 0 2006.183.07:20:17.07#ibcon#*after write, iclass 34, count 0 2006.183.07:20:17.07#ibcon#*before return 0, iclass 34, count 0 2006.183.07:20:17.07#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:17.07#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:17.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:20:17.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:20:17.07$vc4f8/valo=5,652.99 2006.183.07:20:17.07#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:20:17.07#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:20:17.07#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:17.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:17.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:17.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:17.07#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:20:17.07#ibcon#first serial, iclass 36, count 0 2006.183.07:20:17.07#ibcon#enter sib2, iclass 36, count 0 2006.183.07:20:17.07#ibcon#flushed, iclass 36, count 0 2006.183.07:20:17.07#ibcon#about to write, iclass 36, count 0 2006.183.07:20:17.07#ibcon#wrote, iclass 36, count 0 2006.183.07:20:17.07#ibcon#about to read 3, iclass 36, count 0 2006.183.07:20:17.09#ibcon#read 3, iclass 36, count 0 2006.183.07:20:17.09#ibcon#about to read 4, iclass 36, count 0 2006.183.07:20:17.09#ibcon#read 4, iclass 36, count 0 2006.183.07:20:17.09#ibcon#about to read 5, iclass 36, count 0 2006.183.07:20:17.09#ibcon#read 5, iclass 36, count 0 2006.183.07:20:17.09#ibcon#about to read 6, iclass 36, count 0 2006.183.07:20:17.09#ibcon#read 6, iclass 36, count 0 2006.183.07:20:17.09#ibcon#end of sib2, iclass 36, count 0 2006.183.07:20:17.09#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:20:17.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:20:17.09#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:20:17.09#ibcon#*before write, iclass 36, count 0 2006.183.07:20:17.09#ibcon#enter sib2, iclass 36, count 0 2006.183.07:20:17.09#ibcon#flushed, iclass 36, count 0 2006.183.07:20:17.09#ibcon#about to write, iclass 36, count 0 2006.183.07:20:17.09#ibcon#wrote, iclass 36, count 0 2006.183.07:20:17.09#ibcon#about to read 3, iclass 36, count 0 2006.183.07:20:17.13#ibcon#read 3, iclass 36, count 0 2006.183.07:20:17.13#ibcon#about to read 4, iclass 36, count 0 2006.183.07:20:17.13#ibcon#read 4, iclass 36, count 0 2006.183.07:20:17.13#ibcon#about to read 5, iclass 36, count 0 2006.183.07:20:17.13#ibcon#read 5, iclass 36, count 0 2006.183.07:20:17.13#ibcon#about to read 6, iclass 36, count 0 2006.183.07:20:17.13#ibcon#read 6, iclass 36, count 0 2006.183.07:20:17.13#ibcon#end of sib2, iclass 36, count 0 2006.183.07:20:17.13#ibcon#*after write, iclass 36, count 0 2006.183.07:20:17.13#ibcon#*before return 0, iclass 36, count 0 2006.183.07:20:17.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:17.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:17.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:20:17.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:20:17.13$vc4f8/va=5,7 2006.183.07:20:17.13#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.07:20:17.13#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.07:20:17.13#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:17.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:17.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:17.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:17.19#ibcon#enter wrdev, iclass 38, count 2 2006.183.07:20:17.19#ibcon#first serial, iclass 38, count 2 2006.183.07:20:17.19#ibcon#enter sib2, iclass 38, count 2 2006.183.07:20:17.19#ibcon#flushed, iclass 38, count 2 2006.183.07:20:17.19#ibcon#about to write, iclass 38, count 2 2006.183.07:20:17.19#ibcon#wrote, iclass 38, count 2 2006.183.07:20:17.19#ibcon#about to read 3, iclass 38, count 2 2006.183.07:20:17.21#ibcon#read 3, iclass 38, count 2 2006.183.07:20:17.21#ibcon#about to read 4, iclass 38, count 2 2006.183.07:20:17.21#ibcon#read 4, iclass 38, count 2 2006.183.07:20:17.21#ibcon#about to read 5, iclass 38, count 2 2006.183.07:20:17.21#ibcon#read 5, iclass 38, count 2 2006.183.07:20:17.21#ibcon#about to read 6, iclass 38, count 2 2006.183.07:20:17.21#ibcon#read 6, iclass 38, count 2 2006.183.07:20:17.21#ibcon#end of sib2, iclass 38, count 2 2006.183.07:20:17.21#ibcon#*mode == 0, iclass 38, count 2 2006.183.07:20:17.21#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.07:20:17.21#ibcon#[25=AT05-07\r\n] 2006.183.07:20:17.21#ibcon#*before write, iclass 38, count 2 2006.183.07:20:17.21#ibcon#enter sib2, iclass 38, count 2 2006.183.07:20:17.21#ibcon#flushed, iclass 38, count 2 2006.183.07:20:17.21#ibcon#about to write, iclass 38, count 2 2006.183.07:20:17.21#ibcon#wrote, iclass 38, count 2 2006.183.07:20:17.21#ibcon#about to read 3, iclass 38, count 2 2006.183.07:20:17.24#ibcon#read 3, iclass 38, count 2 2006.183.07:20:17.24#ibcon#about to read 4, iclass 38, count 2 2006.183.07:20:17.24#ibcon#read 4, iclass 38, count 2 2006.183.07:20:17.24#ibcon#about to read 5, iclass 38, count 2 2006.183.07:20:17.24#ibcon#read 5, iclass 38, count 2 2006.183.07:20:17.24#ibcon#about to read 6, iclass 38, count 2 2006.183.07:20:17.24#ibcon#read 6, iclass 38, count 2 2006.183.07:20:17.24#ibcon#end of sib2, iclass 38, count 2 2006.183.07:20:17.24#ibcon#*after write, iclass 38, count 2 2006.183.07:20:17.24#ibcon#*before return 0, iclass 38, count 2 2006.183.07:20:17.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:17.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:17.24#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.07:20:17.24#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:17.24#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:17.36#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:17.36#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:17.36#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:20:17.36#ibcon#first serial, iclass 38, count 0 2006.183.07:20:17.36#ibcon#enter sib2, iclass 38, count 0 2006.183.07:20:17.36#ibcon#flushed, iclass 38, count 0 2006.183.07:20:17.36#ibcon#about to write, iclass 38, count 0 2006.183.07:20:17.36#ibcon#wrote, iclass 38, count 0 2006.183.07:20:17.36#ibcon#about to read 3, iclass 38, count 0 2006.183.07:20:17.38#ibcon#read 3, iclass 38, count 0 2006.183.07:20:17.38#ibcon#about to read 4, iclass 38, count 0 2006.183.07:20:17.38#ibcon#read 4, iclass 38, count 0 2006.183.07:20:17.38#ibcon#about to read 5, iclass 38, count 0 2006.183.07:20:17.38#ibcon#read 5, iclass 38, count 0 2006.183.07:20:17.38#ibcon#about to read 6, iclass 38, count 0 2006.183.07:20:17.38#ibcon#read 6, iclass 38, count 0 2006.183.07:20:17.38#ibcon#end of sib2, iclass 38, count 0 2006.183.07:20:17.38#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:20:17.38#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:20:17.38#ibcon#[25=USB\r\n] 2006.183.07:20:17.38#ibcon#*before write, iclass 38, count 0 2006.183.07:20:17.38#ibcon#enter sib2, iclass 38, count 0 2006.183.07:20:17.38#ibcon#flushed, iclass 38, count 0 2006.183.07:20:17.38#ibcon#about to write, iclass 38, count 0 2006.183.07:20:17.38#ibcon#wrote, iclass 38, count 0 2006.183.07:20:17.38#ibcon#about to read 3, iclass 38, count 0 2006.183.07:20:17.41#ibcon#read 3, iclass 38, count 0 2006.183.07:20:17.41#ibcon#about to read 4, iclass 38, count 0 2006.183.07:20:17.41#ibcon#read 4, iclass 38, count 0 2006.183.07:20:17.41#ibcon#about to read 5, iclass 38, count 0 2006.183.07:20:17.41#ibcon#read 5, iclass 38, count 0 2006.183.07:20:17.41#ibcon#about to read 6, iclass 38, count 0 2006.183.07:20:17.41#ibcon#read 6, iclass 38, count 0 2006.183.07:20:17.41#ibcon#end of sib2, iclass 38, count 0 2006.183.07:20:17.41#ibcon#*after write, iclass 38, count 0 2006.183.07:20:17.41#ibcon#*before return 0, iclass 38, count 0 2006.183.07:20:17.41#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:17.41#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:17.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:20:17.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:20:17.41$vc4f8/valo=6,772.99 2006.183.07:20:17.41#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:20:17.41#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:20:17.41#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:17.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:17.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:17.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:17.41#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:20:17.41#ibcon#first serial, iclass 40, count 0 2006.183.07:20:17.41#ibcon#enter sib2, iclass 40, count 0 2006.183.07:20:17.41#ibcon#flushed, iclass 40, count 0 2006.183.07:20:17.41#ibcon#about to write, iclass 40, count 0 2006.183.07:20:17.41#ibcon#wrote, iclass 40, count 0 2006.183.07:20:17.41#ibcon#about to read 3, iclass 40, count 0 2006.183.07:20:17.43#ibcon#read 3, iclass 40, count 0 2006.183.07:20:17.43#ibcon#about to read 4, iclass 40, count 0 2006.183.07:20:17.43#ibcon#read 4, iclass 40, count 0 2006.183.07:20:17.43#ibcon#about to read 5, iclass 40, count 0 2006.183.07:20:17.43#ibcon#read 5, iclass 40, count 0 2006.183.07:20:17.43#ibcon#about to read 6, iclass 40, count 0 2006.183.07:20:17.43#ibcon#read 6, iclass 40, count 0 2006.183.07:20:17.43#ibcon#end of sib2, iclass 40, count 0 2006.183.07:20:17.43#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:20:17.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:20:17.43#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:20:17.43#ibcon#*before write, iclass 40, count 0 2006.183.07:20:17.43#ibcon#enter sib2, iclass 40, count 0 2006.183.07:20:17.43#ibcon#flushed, iclass 40, count 0 2006.183.07:20:17.43#ibcon#about to write, iclass 40, count 0 2006.183.07:20:17.43#ibcon#wrote, iclass 40, count 0 2006.183.07:20:17.43#ibcon#about to read 3, iclass 40, count 0 2006.183.07:20:17.48#ibcon#read 3, iclass 40, count 0 2006.183.07:20:17.48#ibcon#about to read 4, iclass 40, count 0 2006.183.07:20:17.48#ibcon#read 4, iclass 40, count 0 2006.183.07:20:17.48#ibcon#about to read 5, iclass 40, count 0 2006.183.07:20:17.48#ibcon#read 5, iclass 40, count 0 2006.183.07:20:17.48#ibcon#about to read 6, iclass 40, count 0 2006.183.07:20:17.48#ibcon#read 6, iclass 40, count 0 2006.183.07:20:17.48#ibcon#end of sib2, iclass 40, count 0 2006.183.07:20:17.48#ibcon#*after write, iclass 40, count 0 2006.183.07:20:17.48#ibcon#*before return 0, iclass 40, count 0 2006.183.07:20:17.48#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:17.48#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:17.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:20:17.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:20:17.48$vc4f8/va=6,6 2006.183.07:20:17.48#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.07:20:17.48#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.07:20:17.48#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:17.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:20:17.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:20:17.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:20:17.53#ibcon#enter wrdev, iclass 4, count 2 2006.183.07:20:17.53#ibcon#first serial, iclass 4, count 2 2006.183.07:20:17.53#ibcon#enter sib2, iclass 4, count 2 2006.183.07:20:17.53#ibcon#flushed, iclass 4, count 2 2006.183.07:20:17.53#ibcon#about to write, iclass 4, count 2 2006.183.07:20:17.53#ibcon#wrote, iclass 4, count 2 2006.183.07:20:17.53#ibcon#about to read 3, iclass 4, count 2 2006.183.07:20:17.55#ibcon#read 3, iclass 4, count 2 2006.183.07:20:17.55#ibcon#about to read 4, iclass 4, count 2 2006.183.07:20:17.55#ibcon#read 4, iclass 4, count 2 2006.183.07:20:17.55#ibcon#about to read 5, iclass 4, count 2 2006.183.07:20:17.55#ibcon#read 5, iclass 4, count 2 2006.183.07:20:17.55#ibcon#about to read 6, iclass 4, count 2 2006.183.07:20:17.55#ibcon#read 6, iclass 4, count 2 2006.183.07:20:17.55#ibcon#end of sib2, iclass 4, count 2 2006.183.07:20:17.55#ibcon#*mode == 0, iclass 4, count 2 2006.183.07:20:17.55#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.07:20:17.55#ibcon#[25=AT06-06\r\n] 2006.183.07:20:17.55#ibcon#*before write, iclass 4, count 2 2006.183.07:20:17.55#ibcon#enter sib2, iclass 4, count 2 2006.183.07:20:17.55#ibcon#flushed, iclass 4, count 2 2006.183.07:20:17.55#ibcon#about to write, iclass 4, count 2 2006.183.07:20:17.55#ibcon#wrote, iclass 4, count 2 2006.183.07:20:17.55#ibcon#about to read 3, iclass 4, count 2 2006.183.07:20:17.58#ibcon#read 3, iclass 4, count 2 2006.183.07:20:17.58#ibcon#about to read 4, iclass 4, count 2 2006.183.07:20:17.58#ibcon#read 4, iclass 4, count 2 2006.183.07:20:17.58#ibcon#about to read 5, iclass 4, count 2 2006.183.07:20:17.58#ibcon#read 5, iclass 4, count 2 2006.183.07:20:17.58#ibcon#about to read 6, iclass 4, count 2 2006.183.07:20:17.58#ibcon#read 6, iclass 4, count 2 2006.183.07:20:17.58#ibcon#end of sib2, iclass 4, count 2 2006.183.07:20:17.58#ibcon#*after write, iclass 4, count 2 2006.183.07:20:17.58#ibcon#*before return 0, iclass 4, count 2 2006.183.07:20:17.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:20:17.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:20:17.58#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.07:20:17.58#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:17.58#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:20:17.70#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:20:17.70#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:20:17.70#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:20:17.70#ibcon#first serial, iclass 4, count 0 2006.183.07:20:17.70#ibcon#enter sib2, iclass 4, count 0 2006.183.07:20:17.70#ibcon#flushed, iclass 4, count 0 2006.183.07:20:17.70#ibcon#about to write, iclass 4, count 0 2006.183.07:20:17.70#ibcon#wrote, iclass 4, count 0 2006.183.07:20:17.70#ibcon#about to read 3, iclass 4, count 0 2006.183.07:20:17.72#ibcon#read 3, iclass 4, count 0 2006.183.07:20:17.72#ibcon#about to read 4, iclass 4, count 0 2006.183.07:20:17.72#ibcon#read 4, iclass 4, count 0 2006.183.07:20:17.72#ibcon#about to read 5, iclass 4, count 0 2006.183.07:20:17.72#ibcon#read 5, iclass 4, count 0 2006.183.07:20:17.72#ibcon#about to read 6, iclass 4, count 0 2006.183.07:20:17.72#ibcon#read 6, iclass 4, count 0 2006.183.07:20:17.72#ibcon#end of sib2, iclass 4, count 0 2006.183.07:20:17.72#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:20:17.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:20:17.72#ibcon#[25=USB\r\n] 2006.183.07:20:17.72#ibcon#*before write, iclass 4, count 0 2006.183.07:20:17.72#ibcon#enter sib2, iclass 4, count 0 2006.183.07:20:17.72#ibcon#flushed, iclass 4, count 0 2006.183.07:20:17.72#ibcon#about to write, iclass 4, count 0 2006.183.07:20:17.72#ibcon#wrote, iclass 4, count 0 2006.183.07:20:17.72#ibcon#about to read 3, iclass 4, count 0 2006.183.07:20:17.75#ibcon#read 3, iclass 4, count 0 2006.183.07:20:17.75#ibcon#about to read 4, iclass 4, count 0 2006.183.07:20:17.75#ibcon#read 4, iclass 4, count 0 2006.183.07:20:17.75#ibcon#about to read 5, iclass 4, count 0 2006.183.07:20:17.75#ibcon#read 5, iclass 4, count 0 2006.183.07:20:17.75#ibcon#about to read 6, iclass 4, count 0 2006.183.07:20:17.75#ibcon#read 6, iclass 4, count 0 2006.183.07:20:17.75#ibcon#end of sib2, iclass 4, count 0 2006.183.07:20:17.75#ibcon#*after write, iclass 4, count 0 2006.183.07:20:17.75#ibcon#*before return 0, iclass 4, count 0 2006.183.07:20:17.75#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:20:17.75#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:20:17.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:20:17.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:20:17.75$vc4f8/valo=7,832.99 2006.183.07:20:17.75#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:20:17.75#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:20:17.75#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:17.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:20:17.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:20:17.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:20:17.75#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:20:17.75#ibcon#first serial, iclass 6, count 0 2006.183.07:20:17.75#ibcon#enter sib2, iclass 6, count 0 2006.183.07:20:17.75#ibcon#flushed, iclass 6, count 0 2006.183.07:20:17.75#ibcon#about to write, iclass 6, count 0 2006.183.07:20:17.75#ibcon#wrote, iclass 6, count 0 2006.183.07:20:17.75#ibcon#about to read 3, iclass 6, count 0 2006.183.07:20:17.77#ibcon#read 3, iclass 6, count 0 2006.183.07:20:17.77#ibcon#about to read 4, iclass 6, count 0 2006.183.07:20:17.77#ibcon#read 4, iclass 6, count 0 2006.183.07:20:17.77#ibcon#about to read 5, iclass 6, count 0 2006.183.07:20:17.77#ibcon#read 5, iclass 6, count 0 2006.183.07:20:17.77#ibcon#about to read 6, iclass 6, count 0 2006.183.07:20:17.77#ibcon#read 6, iclass 6, count 0 2006.183.07:20:17.77#ibcon#end of sib2, iclass 6, count 0 2006.183.07:20:17.77#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:20:17.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:20:17.77#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:20:17.77#ibcon#*before write, iclass 6, count 0 2006.183.07:20:17.77#ibcon#enter sib2, iclass 6, count 0 2006.183.07:20:17.77#ibcon#flushed, iclass 6, count 0 2006.183.07:20:17.77#ibcon#about to write, iclass 6, count 0 2006.183.07:20:17.77#ibcon#wrote, iclass 6, count 0 2006.183.07:20:17.77#ibcon#about to read 3, iclass 6, count 0 2006.183.07:20:17.81#ibcon#read 3, iclass 6, count 0 2006.183.07:20:17.81#ibcon#about to read 4, iclass 6, count 0 2006.183.07:20:17.81#ibcon#read 4, iclass 6, count 0 2006.183.07:20:17.81#ibcon#about to read 5, iclass 6, count 0 2006.183.07:20:17.81#ibcon#read 5, iclass 6, count 0 2006.183.07:20:17.81#ibcon#about to read 6, iclass 6, count 0 2006.183.07:20:17.81#ibcon#read 6, iclass 6, count 0 2006.183.07:20:17.81#ibcon#end of sib2, iclass 6, count 0 2006.183.07:20:17.81#ibcon#*after write, iclass 6, count 0 2006.183.07:20:17.81#ibcon#*before return 0, iclass 6, count 0 2006.183.07:20:17.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:20:17.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:20:17.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:20:17.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:20:17.81$vc4f8/va=7,6 2006.183.07:20:17.81#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.07:20:17.81#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.07:20:17.81#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:17.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:20:17.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:20:17.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:20:17.87#ibcon#enter wrdev, iclass 10, count 2 2006.183.07:20:17.87#ibcon#first serial, iclass 10, count 2 2006.183.07:20:17.87#ibcon#enter sib2, iclass 10, count 2 2006.183.07:20:17.87#ibcon#flushed, iclass 10, count 2 2006.183.07:20:17.87#ibcon#about to write, iclass 10, count 2 2006.183.07:20:17.87#ibcon#wrote, iclass 10, count 2 2006.183.07:20:17.87#ibcon#about to read 3, iclass 10, count 2 2006.183.07:20:17.89#ibcon#read 3, iclass 10, count 2 2006.183.07:20:17.89#ibcon#about to read 4, iclass 10, count 2 2006.183.07:20:17.89#ibcon#read 4, iclass 10, count 2 2006.183.07:20:17.89#ibcon#about to read 5, iclass 10, count 2 2006.183.07:20:17.89#ibcon#read 5, iclass 10, count 2 2006.183.07:20:17.89#ibcon#about to read 6, iclass 10, count 2 2006.183.07:20:17.89#ibcon#read 6, iclass 10, count 2 2006.183.07:20:17.89#ibcon#end of sib2, iclass 10, count 2 2006.183.07:20:17.89#ibcon#*mode == 0, iclass 10, count 2 2006.183.07:20:17.89#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.07:20:17.89#ibcon#[25=AT07-06\r\n] 2006.183.07:20:17.89#ibcon#*before write, iclass 10, count 2 2006.183.07:20:17.89#ibcon#enter sib2, iclass 10, count 2 2006.183.07:20:17.89#ibcon#flushed, iclass 10, count 2 2006.183.07:20:17.89#ibcon#about to write, iclass 10, count 2 2006.183.07:20:17.89#ibcon#wrote, iclass 10, count 2 2006.183.07:20:17.89#ibcon#about to read 3, iclass 10, count 2 2006.183.07:20:17.92#ibcon#read 3, iclass 10, count 2 2006.183.07:20:17.92#ibcon#about to read 4, iclass 10, count 2 2006.183.07:20:17.92#ibcon#read 4, iclass 10, count 2 2006.183.07:20:17.92#ibcon#about to read 5, iclass 10, count 2 2006.183.07:20:17.92#ibcon#read 5, iclass 10, count 2 2006.183.07:20:17.92#ibcon#about to read 6, iclass 10, count 2 2006.183.07:20:17.92#ibcon#read 6, iclass 10, count 2 2006.183.07:20:17.92#ibcon#end of sib2, iclass 10, count 2 2006.183.07:20:17.92#ibcon#*after write, iclass 10, count 2 2006.183.07:20:17.92#ibcon#*before return 0, iclass 10, count 2 2006.183.07:20:17.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:20:17.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:20:17.92#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.07:20:17.92#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:17.92#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:20:18.04#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:20:18.04#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:20:18.04#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:20:18.04#ibcon#first serial, iclass 10, count 0 2006.183.07:20:18.04#ibcon#enter sib2, iclass 10, count 0 2006.183.07:20:18.04#ibcon#flushed, iclass 10, count 0 2006.183.07:20:18.04#ibcon#about to write, iclass 10, count 0 2006.183.07:20:18.04#ibcon#wrote, iclass 10, count 0 2006.183.07:20:18.04#ibcon#about to read 3, iclass 10, count 0 2006.183.07:20:18.06#ibcon#read 3, iclass 10, count 0 2006.183.07:20:18.06#ibcon#about to read 4, iclass 10, count 0 2006.183.07:20:18.06#ibcon#read 4, iclass 10, count 0 2006.183.07:20:18.06#ibcon#about to read 5, iclass 10, count 0 2006.183.07:20:18.06#ibcon#read 5, iclass 10, count 0 2006.183.07:20:18.06#ibcon#about to read 6, iclass 10, count 0 2006.183.07:20:18.06#ibcon#read 6, iclass 10, count 0 2006.183.07:20:18.06#ibcon#end of sib2, iclass 10, count 0 2006.183.07:20:18.06#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:20:18.06#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:20:18.06#ibcon#[25=USB\r\n] 2006.183.07:20:18.06#ibcon#*before write, iclass 10, count 0 2006.183.07:20:18.06#ibcon#enter sib2, iclass 10, count 0 2006.183.07:20:18.06#ibcon#flushed, iclass 10, count 0 2006.183.07:20:18.06#ibcon#about to write, iclass 10, count 0 2006.183.07:20:18.06#ibcon#wrote, iclass 10, count 0 2006.183.07:20:18.06#ibcon#about to read 3, iclass 10, count 0 2006.183.07:20:18.09#ibcon#read 3, iclass 10, count 0 2006.183.07:20:18.09#ibcon#about to read 4, iclass 10, count 0 2006.183.07:20:18.09#ibcon#read 4, iclass 10, count 0 2006.183.07:20:18.09#ibcon#about to read 5, iclass 10, count 0 2006.183.07:20:18.09#ibcon#read 5, iclass 10, count 0 2006.183.07:20:18.09#ibcon#about to read 6, iclass 10, count 0 2006.183.07:20:18.09#ibcon#read 6, iclass 10, count 0 2006.183.07:20:18.09#ibcon#end of sib2, iclass 10, count 0 2006.183.07:20:18.09#ibcon#*after write, iclass 10, count 0 2006.183.07:20:18.09#ibcon#*before return 0, iclass 10, count 0 2006.183.07:20:18.09#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:20:18.09#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:20:18.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:20:18.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:20:18.09$vc4f8/valo=8,852.99 2006.183.07:20:18.09#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.07:20:18.09#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.07:20:18.09#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:18.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:20:18.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:20:18.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:20:18.09#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:20:18.09#ibcon#first serial, iclass 12, count 0 2006.183.07:20:18.09#ibcon#enter sib2, iclass 12, count 0 2006.183.07:20:18.09#ibcon#flushed, iclass 12, count 0 2006.183.07:20:18.09#ibcon#about to write, iclass 12, count 0 2006.183.07:20:18.09#ibcon#wrote, iclass 12, count 0 2006.183.07:20:18.09#ibcon#about to read 3, iclass 12, count 0 2006.183.07:20:18.11#ibcon#read 3, iclass 12, count 0 2006.183.07:20:18.11#ibcon#about to read 4, iclass 12, count 0 2006.183.07:20:18.11#ibcon#read 4, iclass 12, count 0 2006.183.07:20:18.11#ibcon#about to read 5, iclass 12, count 0 2006.183.07:20:18.11#ibcon#read 5, iclass 12, count 0 2006.183.07:20:18.11#ibcon#about to read 6, iclass 12, count 0 2006.183.07:20:18.11#ibcon#read 6, iclass 12, count 0 2006.183.07:20:18.11#ibcon#end of sib2, iclass 12, count 0 2006.183.07:20:18.11#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:20:18.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:20:18.11#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:20:18.11#ibcon#*before write, iclass 12, count 0 2006.183.07:20:18.11#ibcon#enter sib2, iclass 12, count 0 2006.183.07:20:18.11#ibcon#flushed, iclass 12, count 0 2006.183.07:20:18.11#ibcon#about to write, iclass 12, count 0 2006.183.07:20:18.11#ibcon#wrote, iclass 12, count 0 2006.183.07:20:18.11#ibcon#about to read 3, iclass 12, count 0 2006.183.07:20:18.15#ibcon#read 3, iclass 12, count 0 2006.183.07:20:18.15#ibcon#about to read 4, iclass 12, count 0 2006.183.07:20:18.15#ibcon#read 4, iclass 12, count 0 2006.183.07:20:18.15#ibcon#about to read 5, iclass 12, count 0 2006.183.07:20:18.15#ibcon#read 5, iclass 12, count 0 2006.183.07:20:18.15#ibcon#about to read 6, iclass 12, count 0 2006.183.07:20:18.15#ibcon#read 6, iclass 12, count 0 2006.183.07:20:18.15#ibcon#end of sib2, iclass 12, count 0 2006.183.07:20:18.15#ibcon#*after write, iclass 12, count 0 2006.183.07:20:18.15#ibcon#*before return 0, iclass 12, count 0 2006.183.07:20:18.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:20:18.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:20:18.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:20:18.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:20:18.15$vc4f8/va=8,7 2006.183.07:20:18.15#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.07:20:18.15#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.07:20:18.15#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:18.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:20:18.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:20:18.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:20:18.21#ibcon#enter wrdev, iclass 14, count 2 2006.183.07:20:18.21#ibcon#first serial, iclass 14, count 2 2006.183.07:20:18.21#ibcon#enter sib2, iclass 14, count 2 2006.183.07:20:18.21#ibcon#flushed, iclass 14, count 2 2006.183.07:20:18.21#ibcon#about to write, iclass 14, count 2 2006.183.07:20:18.21#ibcon#wrote, iclass 14, count 2 2006.183.07:20:18.21#ibcon#about to read 3, iclass 14, count 2 2006.183.07:20:18.23#ibcon#read 3, iclass 14, count 2 2006.183.07:20:18.23#ibcon#about to read 4, iclass 14, count 2 2006.183.07:20:18.23#ibcon#read 4, iclass 14, count 2 2006.183.07:20:18.23#ibcon#about to read 5, iclass 14, count 2 2006.183.07:20:18.23#ibcon#read 5, iclass 14, count 2 2006.183.07:20:18.23#ibcon#about to read 6, iclass 14, count 2 2006.183.07:20:18.23#ibcon#read 6, iclass 14, count 2 2006.183.07:20:18.23#ibcon#end of sib2, iclass 14, count 2 2006.183.07:20:18.23#ibcon#*mode == 0, iclass 14, count 2 2006.183.07:20:18.23#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.07:20:18.23#ibcon#[25=AT08-07\r\n] 2006.183.07:20:18.23#ibcon#*before write, iclass 14, count 2 2006.183.07:20:18.23#ibcon#enter sib2, iclass 14, count 2 2006.183.07:20:18.23#ibcon#flushed, iclass 14, count 2 2006.183.07:20:18.23#ibcon#about to write, iclass 14, count 2 2006.183.07:20:18.23#ibcon#wrote, iclass 14, count 2 2006.183.07:20:18.23#ibcon#about to read 3, iclass 14, count 2 2006.183.07:20:18.26#ibcon#read 3, iclass 14, count 2 2006.183.07:20:18.26#ibcon#about to read 4, iclass 14, count 2 2006.183.07:20:18.26#ibcon#read 4, iclass 14, count 2 2006.183.07:20:18.26#ibcon#about to read 5, iclass 14, count 2 2006.183.07:20:18.26#ibcon#read 5, iclass 14, count 2 2006.183.07:20:18.26#ibcon#about to read 6, iclass 14, count 2 2006.183.07:20:18.26#ibcon#read 6, iclass 14, count 2 2006.183.07:20:18.26#ibcon#end of sib2, iclass 14, count 2 2006.183.07:20:18.26#ibcon#*after write, iclass 14, count 2 2006.183.07:20:18.26#ibcon#*before return 0, iclass 14, count 2 2006.183.07:20:18.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:20:18.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:20:18.26#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.07:20:18.26#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:18.26#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:20:18.38#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:20:18.38#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:20:18.38#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:20:18.38#ibcon#first serial, iclass 14, count 0 2006.183.07:20:18.38#ibcon#enter sib2, iclass 14, count 0 2006.183.07:20:18.38#ibcon#flushed, iclass 14, count 0 2006.183.07:20:18.38#ibcon#about to write, iclass 14, count 0 2006.183.07:20:18.38#ibcon#wrote, iclass 14, count 0 2006.183.07:20:18.38#ibcon#about to read 3, iclass 14, count 0 2006.183.07:20:18.40#ibcon#read 3, iclass 14, count 0 2006.183.07:20:18.40#ibcon#about to read 4, iclass 14, count 0 2006.183.07:20:18.40#ibcon#read 4, iclass 14, count 0 2006.183.07:20:18.40#ibcon#about to read 5, iclass 14, count 0 2006.183.07:20:18.40#ibcon#read 5, iclass 14, count 0 2006.183.07:20:18.40#ibcon#about to read 6, iclass 14, count 0 2006.183.07:20:18.40#ibcon#read 6, iclass 14, count 0 2006.183.07:20:18.40#ibcon#end of sib2, iclass 14, count 0 2006.183.07:20:18.40#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:20:18.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:20:18.40#ibcon#[25=USB\r\n] 2006.183.07:20:18.40#ibcon#*before write, iclass 14, count 0 2006.183.07:20:18.40#ibcon#enter sib2, iclass 14, count 0 2006.183.07:20:18.40#ibcon#flushed, iclass 14, count 0 2006.183.07:20:18.40#ibcon#about to write, iclass 14, count 0 2006.183.07:20:18.40#ibcon#wrote, iclass 14, count 0 2006.183.07:20:18.40#ibcon#about to read 3, iclass 14, count 0 2006.183.07:20:18.43#ibcon#read 3, iclass 14, count 0 2006.183.07:20:18.43#ibcon#about to read 4, iclass 14, count 0 2006.183.07:20:18.43#ibcon#read 4, iclass 14, count 0 2006.183.07:20:18.43#ibcon#about to read 5, iclass 14, count 0 2006.183.07:20:18.43#ibcon#read 5, iclass 14, count 0 2006.183.07:20:18.43#ibcon#about to read 6, iclass 14, count 0 2006.183.07:20:18.43#ibcon#read 6, iclass 14, count 0 2006.183.07:20:18.43#ibcon#end of sib2, iclass 14, count 0 2006.183.07:20:18.43#ibcon#*after write, iclass 14, count 0 2006.183.07:20:18.43#ibcon#*before return 0, iclass 14, count 0 2006.183.07:20:18.43#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:20:18.43#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:20:18.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:20:18.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:20:18.43$vc4f8/vblo=1,632.99 2006.183.07:20:18.43#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.07:20:18.43#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.07:20:18.43#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:18.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:20:18.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:20:18.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:20:18.43#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:20:18.43#ibcon#first serial, iclass 16, count 0 2006.183.07:20:18.43#ibcon#enter sib2, iclass 16, count 0 2006.183.07:20:18.43#ibcon#flushed, iclass 16, count 0 2006.183.07:20:18.43#ibcon#about to write, iclass 16, count 0 2006.183.07:20:18.43#ibcon#wrote, iclass 16, count 0 2006.183.07:20:18.43#ibcon#about to read 3, iclass 16, count 0 2006.183.07:20:18.45#ibcon#read 3, iclass 16, count 0 2006.183.07:20:18.45#ibcon#about to read 4, iclass 16, count 0 2006.183.07:20:18.45#ibcon#read 4, iclass 16, count 0 2006.183.07:20:18.45#ibcon#about to read 5, iclass 16, count 0 2006.183.07:20:18.45#ibcon#read 5, iclass 16, count 0 2006.183.07:20:18.45#ibcon#about to read 6, iclass 16, count 0 2006.183.07:20:18.45#ibcon#read 6, iclass 16, count 0 2006.183.07:20:18.45#ibcon#end of sib2, iclass 16, count 0 2006.183.07:20:18.45#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:20:18.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:20:18.45#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:20:18.45#ibcon#*before write, iclass 16, count 0 2006.183.07:20:18.45#ibcon#enter sib2, iclass 16, count 0 2006.183.07:20:18.45#ibcon#flushed, iclass 16, count 0 2006.183.07:20:18.45#ibcon#about to write, iclass 16, count 0 2006.183.07:20:18.45#ibcon#wrote, iclass 16, count 0 2006.183.07:20:18.45#ibcon#about to read 3, iclass 16, count 0 2006.183.07:20:18.49#ibcon#read 3, iclass 16, count 0 2006.183.07:20:18.49#ibcon#about to read 4, iclass 16, count 0 2006.183.07:20:18.49#ibcon#read 4, iclass 16, count 0 2006.183.07:20:18.49#ibcon#about to read 5, iclass 16, count 0 2006.183.07:20:18.49#ibcon#read 5, iclass 16, count 0 2006.183.07:20:18.49#ibcon#about to read 6, iclass 16, count 0 2006.183.07:20:18.49#ibcon#read 6, iclass 16, count 0 2006.183.07:20:18.49#ibcon#end of sib2, iclass 16, count 0 2006.183.07:20:18.49#ibcon#*after write, iclass 16, count 0 2006.183.07:20:18.49#ibcon#*before return 0, iclass 16, count 0 2006.183.07:20:18.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:20:18.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:20:18.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:20:18.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:20:18.49$vc4f8/vb=1,4 2006.183.07:20:18.49#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.07:20:18.49#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.07:20:18.49#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:18.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:20:18.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:20:18.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:20:18.49#ibcon#enter wrdev, iclass 18, count 2 2006.183.07:20:18.49#ibcon#first serial, iclass 18, count 2 2006.183.07:20:18.49#ibcon#enter sib2, iclass 18, count 2 2006.183.07:20:18.49#ibcon#flushed, iclass 18, count 2 2006.183.07:20:18.49#ibcon#about to write, iclass 18, count 2 2006.183.07:20:18.49#ibcon#wrote, iclass 18, count 2 2006.183.07:20:18.49#ibcon#about to read 3, iclass 18, count 2 2006.183.07:20:18.51#ibcon#read 3, iclass 18, count 2 2006.183.07:20:18.51#ibcon#about to read 4, iclass 18, count 2 2006.183.07:20:18.51#ibcon#read 4, iclass 18, count 2 2006.183.07:20:18.51#ibcon#about to read 5, iclass 18, count 2 2006.183.07:20:18.51#ibcon#read 5, iclass 18, count 2 2006.183.07:20:18.51#ibcon#about to read 6, iclass 18, count 2 2006.183.07:20:18.51#ibcon#read 6, iclass 18, count 2 2006.183.07:20:18.51#ibcon#end of sib2, iclass 18, count 2 2006.183.07:20:18.51#ibcon#*mode == 0, iclass 18, count 2 2006.183.07:20:18.51#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.07:20:18.51#ibcon#[27=AT01-04\r\n] 2006.183.07:20:18.51#ibcon#*before write, iclass 18, count 2 2006.183.07:20:18.51#ibcon#enter sib2, iclass 18, count 2 2006.183.07:20:18.51#ibcon#flushed, iclass 18, count 2 2006.183.07:20:18.51#ibcon#about to write, iclass 18, count 2 2006.183.07:20:18.51#ibcon#wrote, iclass 18, count 2 2006.183.07:20:18.51#ibcon#about to read 3, iclass 18, count 2 2006.183.07:20:18.54#ibcon#read 3, iclass 18, count 2 2006.183.07:20:18.54#ibcon#about to read 4, iclass 18, count 2 2006.183.07:20:18.54#ibcon#read 4, iclass 18, count 2 2006.183.07:20:18.54#ibcon#about to read 5, iclass 18, count 2 2006.183.07:20:18.54#ibcon#read 5, iclass 18, count 2 2006.183.07:20:18.54#ibcon#about to read 6, iclass 18, count 2 2006.183.07:20:18.54#ibcon#read 6, iclass 18, count 2 2006.183.07:20:18.54#ibcon#end of sib2, iclass 18, count 2 2006.183.07:20:18.54#ibcon#*after write, iclass 18, count 2 2006.183.07:20:18.54#ibcon#*before return 0, iclass 18, count 2 2006.183.07:20:18.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:20:18.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:20:18.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.07:20:18.54#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:18.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:20:18.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:20:18.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:20:18.66#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:20:18.66#ibcon#first serial, iclass 18, count 0 2006.183.07:20:18.66#ibcon#enter sib2, iclass 18, count 0 2006.183.07:20:18.66#ibcon#flushed, iclass 18, count 0 2006.183.07:20:18.66#ibcon#about to write, iclass 18, count 0 2006.183.07:20:18.66#ibcon#wrote, iclass 18, count 0 2006.183.07:20:18.66#ibcon#about to read 3, iclass 18, count 0 2006.183.07:20:18.68#ibcon#read 3, iclass 18, count 0 2006.183.07:20:18.68#ibcon#about to read 4, iclass 18, count 0 2006.183.07:20:18.68#ibcon#read 4, iclass 18, count 0 2006.183.07:20:18.68#ibcon#about to read 5, iclass 18, count 0 2006.183.07:20:18.68#ibcon#read 5, iclass 18, count 0 2006.183.07:20:18.68#ibcon#about to read 6, iclass 18, count 0 2006.183.07:20:18.68#ibcon#read 6, iclass 18, count 0 2006.183.07:20:18.68#ibcon#end of sib2, iclass 18, count 0 2006.183.07:20:18.68#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:20:18.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:20:18.68#ibcon#[27=USB\r\n] 2006.183.07:20:18.68#ibcon#*before write, iclass 18, count 0 2006.183.07:20:18.68#ibcon#enter sib2, iclass 18, count 0 2006.183.07:20:18.68#ibcon#flushed, iclass 18, count 0 2006.183.07:20:18.68#ibcon#about to write, iclass 18, count 0 2006.183.07:20:18.68#ibcon#wrote, iclass 18, count 0 2006.183.07:20:18.68#ibcon#about to read 3, iclass 18, count 0 2006.183.07:20:18.71#ibcon#read 3, iclass 18, count 0 2006.183.07:20:18.71#ibcon#about to read 4, iclass 18, count 0 2006.183.07:20:18.71#ibcon#read 4, iclass 18, count 0 2006.183.07:20:18.71#ibcon#about to read 5, iclass 18, count 0 2006.183.07:20:18.71#ibcon#read 5, iclass 18, count 0 2006.183.07:20:18.71#ibcon#about to read 6, iclass 18, count 0 2006.183.07:20:18.71#ibcon#read 6, iclass 18, count 0 2006.183.07:20:18.71#ibcon#end of sib2, iclass 18, count 0 2006.183.07:20:18.71#ibcon#*after write, iclass 18, count 0 2006.183.07:20:18.71#ibcon#*before return 0, iclass 18, count 0 2006.183.07:20:18.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:20:18.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:20:18.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:20:18.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:20:18.71$vc4f8/vblo=2,640.99 2006.183.07:20:18.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.07:20:18.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.07:20:18.71#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:18.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:18.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:18.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:18.71#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:20:18.71#ibcon#first serial, iclass 20, count 0 2006.183.07:20:18.71#ibcon#enter sib2, iclass 20, count 0 2006.183.07:20:18.71#ibcon#flushed, iclass 20, count 0 2006.183.07:20:18.71#ibcon#about to write, iclass 20, count 0 2006.183.07:20:18.71#ibcon#wrote, iclass 20, count 0 2006.183.07:20:18.71#ibcon#about to read 3, iclass 20, count 0 2006.183.07:20:18.73#ibcon#read 3, iclass 20, count 0 2006.183.07:20:18.73#ibcon#about to read 4, iclass 20, count 0 2006.183.07:20:18.73#ibcon#read 4, iclass 20, count 0 2006.183.07:20:18.73#ibcon#about to read 5, iclass 20, count 0 2006.183.07:20:18.73#ibcon#read 5, iclass 20, count 0 2006.183.07:20:18.73#ibcon#about to read 6, iclass 20, count 0 2006.183.07:20:18.73#ibcon#read 6, iclass 20, count 0 2006.183.07:20:18.73#ibcon#end of sib2, iclass 20, count 0 2006.183.07:20:18.73#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:20:18.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:20:18.73#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:20:18.73#ibcon#*before write, iclass 20, count 0 2006.183.07:20:18.73#ibcon#enter sib2, iclass 20, count 0 2006.183.07:20:18.73#ibcon#flushed, iclass 20, count 0 2006.183.07:20:18.73#ibcon#about to write, iclass 20, count 0 2006.183.07:20:18.73#ibcon#wrote, iclass 20, count 0 2006.183.07:20:18.73#ibcon#about to read 3, iclass 20, count 0 2006.183.07:20:18.77#ibcon#read 3, iclass 20, count 0 2006.183.07:20:18.77#ibcon#about to read 4, iclass 20, count 0 2006.183.07:20:18.77#ibcon#read 4, iclass 20, count 0 2006.183.07:20:18.77#ibcon#about to read 5, iclass 20, count 0 2006.183.07:20:18.77#ibcon#read 5, iclass 20, count 0 2006.183.07:20:18.77#ibcon#about to read 6, iclass 20, count 0 2006.183.07:20:18.77#ibcon#read 6, iclass 20, count 0 2006.183.07:20:18.77#ibcon#end of sib2, iclass 20, count 0 2006.183.07:20:18.77#ibcon#*after write, iclass 20, count 0 2006.183.07:20:18.77#ibcon#*before return 0, iclass 20, count 0 2006.183.07:20:18.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:18.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:20:18.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:20:18.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:20:18.77$vc4f8/vb=2,4 2006.183.07:20:18.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.07:20:18.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.07:20:18.77#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:18.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:18.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:18.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:18.83#ibcon#enter wrdev, iclass 22, count 2 2006.183.07:20:18.83#ibcon#first serial, iclass 22, count 2 2006.183.07:20:18.83#ibcon#enter sib2, iclass 22, count 2 2006.183.07:20:18.83#ibcon#flushed, iclass 22, count 2 2006.183.07:20:18.83#ibcon#about to write, iclass 22, count 2 2006.183.07:20:18.83#ibcon#wrote, iclass 22, count 2 2006.183.07:20:18.83#ibcon#about to read 3, iclass 22, count 2 2006.183.07:20:18.85#ibcon#read 3, iclass 22, count 2 2006.183.07:20:18.85#ibcon#about to read 4, iclass 22, count 2 2006.183.07:20:18.85#ibcon#read 4, iclass 22, count 2 2006.183.07:20:18.85#ibcon#about to read 5, iclass 22, count 2 2006.183.07:20:18.85#ibcon#read 5, iclass 22, count 2 2006.183.07:20:18.85#ibcon#about to read 6, iclass 22, count 2 2006.183.07:20:18.85#ibcon#read 6, iclass 22, count 2 2006.183.07:20:18.85#ibcon#end of sib2, iclass 22, count 2 2006.183.07:20:18.85#ibcon#*mode == 0, iclass 22, count 2 2006.183.07:20:18.85#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.07:20:18.85#ibcon#[27=AT02-04\r\n] 2006.183.07:20:18.85#ibcon#*before write, iclass 22, count 2 2006.183.07:20:18.85#ibcon#enter sib2, iclass 22, count 2 2006.183.07:20:18.85#ibcon#flushed, iclass 22, count 2 2006.183.07:20:18.85#ibcon#about to write, iclass 22, count 2 2006.183.07:20:18.85#ibcon#wrote, iclass 22, count 2 2006.183.07:20:18.85#ibcon#about to read 3, iclass 22, count 2 2006.183.07:20:18.88#ibcon#read 3, iclass 22, count 2 2006.183.07:20:18.88#ibcon#about to read 4, iclass 22, count 2 2006.183.07:20:18.88#ibcon#read 4, iclass 22, count 2 2006.183.07:20:18.88#ibcon#about to read 5, iclass 22, count 2 2006.183.07:20:18.88#ibcon#read 5, iclass 22, count 2 2006.183.07:20:18.88#ibcon#about to read 6, iclass 22, count 2 2006.183.07:20:18.88#ibcon#read 6, iclass 22, count 2 2006.183.07:20:18.88#ibcon#end of sib2, iclass 22, count 2 2006.183.07:20:18.88#ibcon#*after write, iclass 22, count 2 2006.183.07:20:18.88#ibcon#*before return 0, iclass 22, count 2 2006.183.07:20:18.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:18.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:20:18.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.07:20:18.88#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:18.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:19.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:19.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:19.00#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:20:19.00#ibcon#first serial, iclass 22, count 0 2006.183.07:20:19.00#ibcon#enter sib2, iclass 22, count 0 2006.183.07:20:19.00#ibcon#flushed, iclass 22, count 0 2006.183.07:20:19.00#ibcon#about to write, iclass 22, count 0 2006.183.07:20:19.00#ibcon#wrote, iclass 22, count 0 2006.183.07:20:19.00#ibcon#about to read 3, iclass 22, count 0 2006.183.07:20:19.02#ibcon#read 3, iclass 22, count 0 2006.183.07:20:19.02#ibcon#about to read 4, iclass 22, count 0 2006.183.07:20:19.02#ibcon#read 4, iclass 22, count 0 2006.183.07:20:19.02#ibcon#about to read 5, iclass 22, count 0 2006.183.07:20:19.02#ibcon#read 5, iclass 22, count 0 2006.183.07:20:19.02#ibcon#about to read 6, iclass 22, count 0 2006.183.07:20:19.02#ibcon#read 6, iclass 22, count 0 2006.183.07:20:19.02#ibcon#end of sib2, iclass 22, count 0 2006.183.07:20:19.02#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:20:19.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:20:19.02#ibcon#[27=USB\r\n] 2006.183.07:20:19.02#ibcon#*before write, iclass 22, count 0 2006.183.07:20:19.02#ibcon#enter sib2, iclass 22, count 0 2006.183.07:20:19.02#ibcon#flushed, iclass 22, count 0 2006.183.07:20:19.02#ibcon#about to write, iclass 22, count 0 2006.183.07:20:19.02#ibcon#wrote, iclass 22, count 0 2006.183.07:20:19.02#ibcon#about to read 3, iclass 22, count 0 2006.183.07:20:19.05#ibcon#read 3, iclass 22, count 0 2006.183.07:20:19.05#ibcon#about to read 4, iclass 22, count 0 2006.183.07:20:19.05#ibcon#read 4, iclass 22, count 0 2006.183.07:20:19.05#ibcon#about to read 5, iclass 22, count 0 2006.183.07:20:19.05#ibcon#read 5, iclass 22, count 0 2006.183.07:20:19.05#ibcon#about to read 6, iclass 22, count 0 2006.183.07:20:19.05#ibcon#read 6, iclass 22, count 0 2006.183.07:20:19.05#ibcon#end of sib2, iclass 22, count 0 2006.183.07:20:19.05#ibcon#*after write, iclass 22, count 0 2006.183.07:20:19.05#ibcon#*before return 0, iclass 22, count 0 2006.183.07:20:19.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:19.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:20:19.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:20:19.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:20:19.05$vc4f8/vblo=3,656.99 2006.183.07:20:19.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.07:20:19.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.07:20:19.05#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:19.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:19.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:19.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:19.05#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:20:19.05#ibcon#first serial, iclass 24, count 0 2006.183.07:20:19.05#ibcon#enter sib2, iclass 24, count 0 2006.183.07:20:19.05#ibcon#flushed, iclass 24, count 0 2006.183.07:20:19.05#ibcon#about to write, iclass 24, count 0 2006.183.07:20:19.05#ibcon#wrote, iclass 24, count 0 2006.183.07:20:19.05#ibcon#about to read 3, iclass 24, count 0 2006.183.07:20:19.07#ibcon#read 3, iclass 24, count 0 2006.183.07:20:19.07#ibcon#about to read 4, iclass 24, count 0 2006.183.07:20:19.07#ibcon#read 4, iclass 24, count 0 2006.183.07:20:19.07#ibcon#about to read 5, iclass 24, count 0 2006.183.07:20:19.07#ibcon#read 5, iclass 24, count 0 2006.183.07:20:19.07#ibcon#about to read 6, iclass 24, count 0 2006.183.07:20:19.07#ibcon#read 6, iclass 24, count 0 2006.183.07:20:19.07#ibcon#end of sib2, iclass 24, count 0 2006.183.07:20:19.07#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:20:19.07#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:20:19.07#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:20:19.07#ibcon#*before write, iclass 24, count 0 2006.183.07:20:19.07#ibcon#enter sib2, iclass 24, count 0 2006.183.07:20:19.07#ibcon#flushed, iclass 24, count 0 2006.183.07:20:19.07#ibcon#about to write, iclass 24, count 0 2006.183.07:20:19.07#ibcon#wrote, iclass 24, count 0 2006.183.07:20:19.07#ibcon#about to read 3, iclass 24, count 0 2006.183.07:20:19.12#ibcon#read 3, iclass 24, count 0 2006.183.07:20:19.12#ibcon#about to read 4, iclass 24, count 0 2006.183.07:20:19.12#ibcon#read 4, iclass 24, count 0 2006.183.07:20:19.12#ibcon#about to read 5, iclass 24, count 0 2006.183.07:20:19.12#ibcon#read 5, iclass 24, count 0 2006.183.07:20:19.12#ibcon#about to read 6, iclass 24, count 0 2006.183.07:20:19.12#ibcon#read 6, iclass 24, count 0 2006.183.07:20:19.12#ibcon#end of sib2, iclass 24, count 0 2006.183.07:20:19.12#ibcon#*after write, iclass 24, count 0 2006.183.07:20:19.12#ibcon#*before return 0, iclass 24, count 0 2006.183.07:20:19.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:19.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:20:19.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:20:19.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:20:19.12$vc4f8/vb=3,4 2006.183.07:20:19.12#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.07:20:19.12#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.07:20:19.12#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:19.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:19.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:19.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:19.17#ibcon#enter wrdev, iclass 26, count 2 2006.183.07:20:19.17#ibcon#first serial, iclass 26, count 2 2006.183.07:20:19.17#ibcon#enter sib2, iclass 26, count 2 2006.183.07:20:19.17#ibcon#flushed, iclass 26, count 2 2006.183.07:20:19.17#ibcon#about to write, iclass 26, count 2 2006.183.07:20:19.17#ibcon#wrote, iclass 26, count 2 2006.183.07:20:19.17#ibcon#about to read 3, iclass 26, count 2 2006.183.07:20:19.19#ibcon#read 3, iclass 26, count 2 2006.183.07:20:19.19#ibcon#about to read 4, iclass 26, count 2 2006.183.07:20:19.19#ibcon#read 4, iclass 26, count 2 2006.183.07:20:19.19#ibcon#about to read 5, iclass 26, count 2 2006.183.07:20:19.19#ibcon#read 5, iclass 26, count 2 2006.183.07:20:19.19#ibcon#about to read 6, iclass 26, count 2 2006.183.07:20:19.19#ibcon#read 6, iclass 26, count 2 2006.183.07:20:19.19#ibcon#end of sib2, iclass 26, count 2 2006.183.07:20:19.19#ibcon#*mode == 0, iclass 26, count 2 2006.183.07:20:19.19#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.07:20:19.19#ibcon#[27=AT03-04\r\n] 2006.183.07:20:19.19#ibcon#*before write, iclass 26, count 2 2006.183.07:20:19.19#ibcon#enter sib2, iclass 26, count 2 2006.183.07:20:19.19#ibcon#flushed, iclass 26, count 2 2006.183.07:20:19.19#ibcon#about to write, iclass 26, count 2 2006.183.07:20:19.19#ibcon#wrote, iclass 26, count 2 2006.183.07:20:19.19#ibcon#about to read 3, iclass 26, count 2 2006.183.07:20:19.22#ibcon#read 3, iclass 26, count 2 2006.183.07:20:19.22#ibcon#about to read 4, iclass 26, count 2 2006.183.07:20:19.22#ibcon#read 4, iclass 26, count 2 2006.183.07:20:19.22#ibcon#about to read 5, iclass 26, count 2 2006.183.07:20:19.22#ibcon#read 5, iclass 26, count 2 2006.183.07:20:19.22#ibcon#about to read 6, iclass 26, count 2 2006.183.07:20:19.22#ibcon#read 6, iclass 26, count 2 2006.183.07:20:19.22#ibcon#end of sib2, iclass 26, count 2 2006.183.07:20:19.22#ibcon#*after write, iclass 26, count 2 2006.183.07:20:19.22#ibcon#*before return 0, iclass 26, count 2 2006.183.07:20:19.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:19.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:20:19.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.07:20:19.22#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:19.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:19.34#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:19.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:19.34#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:20:19.34#ibcon#first serial, iclass 26, count 0 2006.183.07:20:19.34#ibcon#enter sib2, iclass 26, count 0 2006.183.07:20:19.34#ibcon#flushed, iclass 26, count 0 2006.183.07:20:19.34#ibcon#about to write, iclass 26, count 0 2006.183.07:20:19.34#ibcon#wrote, iclass 26, count 0 2006.183.07:20:19.34#ibcon#about to read 3, iclass 26, count 0 2006.183.07:20:19.36#ibcon#read 3, iclass 26, count 0 2006.183.07:20:19.36#ibcon#about to read 4, iclass 26, count 0 2006.183.07:20:19.36#ibcon#read 4, iclass 26, count 0 2006.183.07:20:19.36#ibcon#about to read 5, iclass 26, count 0 2006.183.07:20:19.36#ibcon#read 5, iclass 26, count 0 2006.183.07:20:19.36#ibcon#about to read 6, iclass 26, count 0 2006.183.07:20:19.36#ibcon#read 6, iclass 26, count 0 2006.183.07:20:19.36#ibcon#end of sib2, iclass 26, count 0 2006.183.07:20:19.36#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:20:19.36#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:20:19.36#ibcon#[27=USB\r\n] 2006.183.07:20:19.36#ibcon#*before write, iclass 26, count 0 2006.183.07:20:19.36#ibcon#enter sib2, iclass 26, count 0 2006.183.07:20:19.36#ibcon#flushed, iclass 26, count 0 2006.183.07:20:19.36#ibcon#about to write, iclass 26, count 0 2006.183.07:20:19.36#ibcon#wrote, iclass 26, count 0 2006.183.07:20:19.36#ibcon#about to read 3, iclass 26, count 0 2006.183.07:20:19.39#ibcon#read 3, iclass 26, count 0 2006.183.07:20:19.39#ibcon#about to read 4, iclass 26, count 0 2006.183.07:20:19.39#ibcon#read 4, iclass 26, count 0 2006.183.07:20:19.39#ibcon#about to read 5, iclass 26, count 0 2006.183.07:20:19.39#ibcon#read 5, iclass 26, count 0 2006.183.07:20:19.39#ibcon#about to read 6, iclass 26, count 0 2006.183.07:20:19.39#ibcon#read 6, iclass 26, count 0 2006.183.07:20:19.39#ibcon#end of sib2, iclass 26, count 0 2006.183.07:20:19.39#ibcon#*after write, iclass 26, count 0 2006.183.07:20:19.39#ibcon#*before return 0, iclass 26, count 0 2006.183.07:20:19.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:19.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:20:19.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:20:19.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:20:19.39$vc4f8/vblo=4,712.99 2006.183.07:20:19.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.07:20:19.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.07:20:19.39#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:19.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:19.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:19.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:19.39#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:20:19.39#ibcon#first serial, iclass 28, count 0 2006.183.07:20:19.39#ibcon#enter sib2, iclass 28, count 0 2006.183.07:20:19.39#ibcon#flushed, iclass 28, count 0 2006.183.07:20:19.39#ibcon#about to write, iclass 28, count 0 2006.183.07:20:19.39#ibcon#wrote, iclass 28, count 0 2006.183.07:20:19.39#ibcon#about to read 3, iclass 28, count 0 2006.183.07:20:19.41#ibcon#read 3, iclass 28, count 0 2006.183.07:20:19.41#ibcon#about to read 4, iclass 28, count 0 2006.183.07:20:19.41#ibcon#read 4, iclass 28, count 0 2006.183.07:20:19.41#ibcon#about to read 5, iclass 28, count 0 2006.183.07:20:19.41#ibcon#read 5, iclass 28, count 0 2006.183.07:20:19.41#ibcon#about to read 6, iclass 28, count 0 2006.183.07:20:19.41#ibcon#read 6, iclass 28, count 0 2006.183.07:20:19.41#ibcon#end of sib2, iclass 28, count 0 2006.183.07:20:19.41#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:20:19.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:20:19.41#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:20:19.41#ibcon#*before write, iclass 28, count 0 2006.183.07:20:19.41#ibcon#enter sib2, iclass 28, count 0 2006.183.07:20:19.41#ibcon#flushed, iclass 28, count 0 2006.183.07:20:19.41#ibcon#about to write, iclass 28, count 0 2006.183.07:20:19.41#ibcon#wrote, iclass 28, count 0 2006.183.07:20:19.41#ibcon#about to read 3, iclass 28, count 0 2006.183.07:20:19.45#ibcon#read 3, iclass 28, count 0 2006.183.07:20:19.45#ibcon#about to read 4, iclass 28, count 0 2006.183.07:20:19.45#ibcon#read 4, iclass 28, count 0 2006.183.07:20:19.45#ibcon#about to read 5, iclass 28, count 0 2006.183.07:20:19.45#ibcon#read 5, iclass 28, count 0 2006.183.07:20:19.45#ibcon#about to read 6, iclass 28, count 0 2006.183.07:20:19.45#ibcon#read 6, iclass 28, count 0 2006.183.07:20:19.45#ibcon#end of sib2, iclass 28, count 0 2006.183.07:20:19.45#ibcon#*after write, iclass 28, count 0 2006.183.07:20:19.45#ibcon#*before return 0, iclass 28, count 0 2006.183.07:20:19.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:19.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:20:19.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:20:19.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:20:19.45$vc4f8/vb=4,4 2006.183.07:20:19.45#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.07:20:19.45#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.07:20:19.45#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:19.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:19.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:19.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:19.51#ibcon#enter wrdev, iclass 30, count 2 2006.183.07:20:19.51#ibcon#first serial, iclass 30, count 2 2006.183.07:20:19.51#ibcon#enter sib2, iclass 30, count 2 2006.183.07:20:19.51#ibcon#flushed, iclass 30, count 2 2006.183.07:20:19.51#ibcon#about to write, iclass 30, count 2 2006.183.07:20:19.51#ibcon#wrote, iclass 30, count 2 2006.183.07:20:19.51#ibcon#about to read 3, iclass 30, count 2 2006.183.07:20:19.53#ibcon#read 3, iclass 30, count 2 2006.183.07:20:19.53#ibcon#about to read 4, iclass 30, count 2 2006.183.07:20:19.53#ibcon#read 4, iclass 30, count 2 2006.183.07:20:19.53#ibcon#about to read 5, iclass 30, count 2 2006.183.07:20:19.53#ibcon#read 5, iclass 30, count 2 2006.183.07:20:19.53#ibcon#about to read 6, iclass 30, count 2 2006.183.07:20:19.53#ibcon#read 6, iclass 30, count 2 2006.183.07:20:19.53#ibcon#end of sib2, iclass 30, count 2 2006.183.07:20:19.53#ibcon#*mode == 0, iclass 30, count 2 2006.183.07:20:19.53#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.07:20:19.53#ibcon#[27=AT04-04\r\n] 2006.183.07:20:19.53#ibcon#*before write, iclass 30, count 2 2006.183.07:20:19.53#ibcon#enter sib2, iclass 30, count 2 2006.183.07:20:19.53#ibcon#flushed, iclass 30, count 2 2006.183.07:20:19.53#ibcon#about to write, iclass 30, count 2 2006.183.07:20:19.53#ibcon#wrote, iclass 30, count 2 2006.183.07:20:19.53#ibcon#about to read 3, iclass 30, count 2 2006.183.07:20:19.56#ibcon#read 3, iclass 30, count 2 2006.183.07:20:19.56#ibcon#about to read 4, iclass 30, count 2 2006.183.07:20:19.56#ibcon#read 4, iclass 30, count 2 2006.183.07:20:19.56#ibcon#about to read 5, iclass 30, count 2 2006.183.07:20:19.56#ibcon#read 5, iclass 30, count 2 2006.183.07:20:19.56#ibcon#about to read 6, iclass 30, count 2 2006.183.07:20:19.56#ibcon#read 6, iclass 30, count 2 2006.183.07:20:19.56#ibcon#end of sib2, iclass 30, count 2 2006.183.07:20:19.56#ibcon#*after write, iclass 30, count 2 2006.183.07:20:19.56#ibcon#*before return 0, iclass 30, count 2 2006.183.07:20:19.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:19.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:20:19.56#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.07:20:19.56#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:19.56#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:19.68#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:19.68#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:19.68#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:20:19.68#ibcon#first serial, iclass 30, count 0 2006.183.07:20:19.68#ibcon#enter sib2, iclass 30, count 0 2006.183.07:20:19.68#ibcon#flushed, iclass 30, count 0 2006.183.07:20:19.68#ibcon#about to write, iclass 30, count 0 2006.183.07:20:19.68#ibcon#wrote, iclass 30, count 0 2006.183.07:20:19.68#ibcon#about to read 3, iclass 30, count 0 2006.183.07:20:19.70#ibcon#read 3, iclass 30, count 0 2006.183.07:20:19.70#ibcon#about to read 4, iclass 30, count 0 2006.183.07:20:19.70#ibcon#read 4, iclass 30, count 0 2006.183.07:20:19.70#ibcon#about to read 5, iclass 30, count 0 2006.183.07:20:19.70#ibcon#read 5, iclass 30, count 0 2006.183.07:20:19.70#ibcon#about to read 6, iclass 30, count 0 2006.183.07:20:19.70#ibcon#read 6, iclass 30, count 0 2006.183.07:20:19.70#ibcon#end of sib2, iclass 30, count 0 2006.183.07:20:19.70#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:20:19.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:20:19.70#ibcon#[27=USB\r\n] 2006.183.07:20:19.70#ibcon#*before write, iclass 30, count 0 2006.183.07:20:19.70#ibcon#enter sib2, iclass 30, count 0 2006.183.07:20:19.70#ibcon#flushed, iclass 30, count 0 2006.183.07:20:19.70#ibcon#about to write, iclass 30, count 0 2006.183.07:20:19.70#ibcon#wrote, iclass 30, count 0 2006.183.07:20:19.70#ibcon#about to read 3, iclass 30, count 0 2006.183.07:20:19.73#ibcon#read 3, iclass 30, count 0 2006.183.07:20:19.73#ibcon#about to read 4, iclass 30, count 0 2006.183.07:20:19.73#ibcon#read 4, iclass 30, count 0 2006.183.07:20:19.73#ibcon#about to read 5, iclass 30, count 0 2006.183.07:20:19.73#ibcon#read 5, iclass 30, count 0 2006.183.07:20:19.73#ibcon#about to read 6, iclass 30, count 0 2006.183.07:20:19.73#ibcon#read 6, iclass 30, count 0 2006.183.07:20:19.73#ibcon#end of sib2, iclass 30, count 0 2006.183.07:20:19.73#ibcon#*after write, iclass 30, count 0 2006.183.07:20:19.73#ibcon#*before return 0, iclass 30, count 0 2006.183.07:20:19.73#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:19.73#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:20:19.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:20:19.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:20:19.73$vc4f8/vblo=5,744.99 2006.183.07:20:19.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.07:20:19.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.07:20:19.73#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:19.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:19.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:19.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:19.73#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:20:19.73#ibcon#first serial, iclass 32, count 0 2006.183.07:20:19.73#ibcon#enter sib2, iclass 32, count 0 2006.183.07:20:19.73#ibcon#flushed, iclass 32, count 0 2006.183.07:20:19.73#ibcon#about to write, iclass 32, count 0 2006.183.07:20:19.73#ibcon#wrote, iclass 32, count 0 2006.183.07:20:19.73#ibcon#about to read 3, iclass 32, count 0 2006.183.07:20:19.75#ibcon#read 3, iclass 32, count 0 2006.183.07:20:19.75#ibcon#about to read 4, iclass 32, count 0 2006.183.07:20:19.75#ibcon#read 4, iclass 32, count 0 2006.183.07:20:19.75#ibcon#about to read 5, iclass 32, count 0 2006.183.07:20:19.75#ibcon#read 5, iclass 32, count 0 2006.183.07:20:19.75#ibcon#about to read 6, iclass 32, count 0 2006.183.07:20:19.75#ibcon#read 6, iclass 32, count 0 2006.183.07:20:19.75#ibcon#end of sib2, iclass 32, count 0 2006.183.07:20:19.75#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:20:19.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:20:19.75#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:20:19.75#ibcon#*before write, iclass 32, count 0 2006.183.07:20:19.75#ibcon#enter sib2, iclass 32, count 0 2006.183.07:20:19.75#ibcon#flushed, iclass 32, count 0 2006.183.07:20:19.75#ibcon#about to write, iclass 32, count 0 2006.183.07:20:19.75#ibcon#wrote, iclass 32, count 0 2006.183.07:20:19.75#ibcon#about to read 3, iclass 32, count 0 2006.183.07:20:19.79#ibcon#read 3, iclass 32, count 0 2006.183.07:20:19.79#ibcon#about to read 4, iclass 32, count 0 2006.183.07:20:19.79#ibcon#read 4, iclass 32, count 0 2006.183.07:20:19.79#ibcon#about to read 5, iclass 32, count 0 2006.183.07:20:19.79#ibcon#read 5, iclass 32, count 0 2006.183.07:20:19.79#ibcon#about to read 6, iclass 32, count 0 2006.183.07:20:19.79#ibcon#read 6, iclass 32, count 0 2006.183.07:20:19.79#ibcon#end of sib2, iclass 32, count 0 2006.183.07:20:19.79#ibcon#*after write, iclass 32, count 0 2006.183.07:20:19.79#ibcon#*before return 0, iclass 32, count 0 2006.183.07:20:19.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:19.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:20:19.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:20:19.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:20:19.79$vc4f8/vb=5,4 2006.183.07:20:19.79#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.07:20:19.79#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.07:20:19.79#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:19.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:19.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:19.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:19.85#ibcon#enter wrdev, iclass 34, count 2 2006.183.07:20:19.85#ibcon#first serial, iclass 34, count 2 2006.183.07:20:19.85#ibcon#enter sib2, iclass 34, count 2 2006.183.07:20:19.85#ibcon#flushed, iclass 34, count 2 2006.183.07:20:19.85#ibcon#about to write, iclass 34, count 2 2006.183.07:20:19.85#ibcon#wrote, iclass 34, count 2 2006.183.07:20:19.85#ibcon#about to read 3, iclass 34, count 2 2006.183.07:20:19.87#ibcon#read 3, iclass 34, count 2 2006.183.07:20:19.87#ibcon#about to read 4, iclass 34, count 2 2006.183.07:20:19.87#ibcon#read 4, iclass 34, count 2 2006.183.07:20:19.87#ibcon#about to read 5, iclass 34, count 2 2006.183.07:20:19.87#ibcon#read 5, iclass 34, count 2 2006.183.07:20:19.87#ibcon#about to read 6, iclass 34, count 2 2006.183.07:20:19.87#ibcon#read 6, iclass 34, count 2 2006.183.07:20:19.87#ibcon#end of sib2, iclass 34, count 2 2006.183.07:20:19.87#ibcon#*mode == 0, iclass 34, count 2 2006.183.07:20:19.87#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.07:20:19.87#ibcon#[27=AT05-04\r\n] 2006.183.07:20:19.87#ibcon#*before write, iclass 34, count 2 2006.183.07:20:19.87#ibcon#enter sib2, iclass 34, count 2 2006.183.07:20:19.87#ibcon#flushed, iclass 34, count 2 2006.183.07:20:19.87#ibcon#about to write, iclass 34, count 2 2006.183.07:20:19.87#ibcon#wrote, iclass 34, count 2 2006.183.07:20:19.87#ibcon#about to read 3, iclass 34, count 2 2006.183.07:20:19.90#ibcon#read 3, iclass 34, count 2 2006.183.07:20:19.90#ibcon#about to read 4, iclass 34, count 2 2006.183.07:20:19.90#ibcon#read 4, iclass 34, count 2 2006.183.07:20:19.90#ibcon#about to read 5, iclass 34, count 2 2006.183.07:20:19.90#ibcon#read 5, iclass 34, count 2 2006.183.07:20:19.90#ibcon#about to read 6, iclass 34, count 2 2006.183.07:20:19.90#ibcon#read 6, iclass 34, count 2 2006.183.07:20:19.90#ibcon#end of sib2, iclass 34, count 2 2006.183.07:20:19.90#ibcon#*after write, iclass 34, count 2 2006.183.07:20:19.90#ibcon#*before return 0, iclass 34, count 2 2006.183.07:20:19.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:19.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:20:19.90#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.07:20:19.90#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:19.90#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:20.02#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:20.02#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:20.02#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:20:20.02#ibcon#first serial, iclass 34, count 0 2006.183.07:20:20.02#ibcon#enter sib2, iclass 34, count 0 2006.183.07:20:20.02#ibcon#flushed, iclass 34, count 0 2006.183.07:20:20.02#ibcon#about to write, iclass 34, count 0 2006.183.07:20:20.02#ibcon#wrote, iclass 34, count 0 2006.183.07:20:20.02#ibcon#about to read 3, iclass 34, count 0 2006.183.07:20:20.04#ibcon#read 3, iclass 34, count 0 2006.183.07:20:20.04#ibcon#about to read 4, iclass 34, count 0 2006.183.07:20:20.04#ibcon#read 4, iclass 34, count 0 2006.183.07:20:20.04#ibcon#about to read 5, iclass 34, count 0 2006.183.07:20:20.04#ibcon#read 5, iclass 34, count 0 2006.183.07:20:20.04#ibcon#about to read 6, iclass 34, count 0 2006.183.07:20:20.04#ibcon#read 6, iclass 34, count 0 2006.183.07:20:20.04#ibcon#end of sib2, iclass 34, count 0 2006.183.07:20:20.04#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:20:20.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:20:20.04#ibcon#[27=USB\r\n] 2006.183.07:20:20.04#ibcon#*before write, iclass 34, count 0 2006.183.07:20:20.04#ibcon#enter sib2, iclass 34, count 0 2006.183.07:20:20.04#ibcon#flushed, iclass 34, count 0 2006.183.07:20:20.04#ibcon#about to write, iclass 34, count 0 2006.183.07:20:20.04#ibcon#wrote, iclass 34, count 0 2006.183.07:20:20.04#ibcon#about to read 3, iclass 34, count 0 2006.183.07:20:20.07#ibcon#read 3, iclass 34, count 0 2006.183.07:20:20.07#ibcon#about to read 4, iclass 34, count 0 2006.183.07:20:20.07#ibcon#read 4, iclass 34, count 0 2006.183.07:20:20.07#ibcon#about to read 5, iclass 34, count 0 2006.183.07:20:20.07#ibcon#read 5, iclass 34, count 0 2006.183.07:20:20.07#ibcon#about to read 6, iclass 34, count 0 2006.183.07:20:20.07#ibcon#read 6, iclass 34, count 0 2006.183.07:20:20.07#ibcon#end of sib2, iclass 34, count 0 2006.183.07:20:20.07#ibcon#*after write, iclass 34, count 0 2006.183.07:20:20.07#ibcon#*before return 0, iclass 34, count 0 2006.183.07:20:20.07#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:20.07#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:20:20.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:20:20.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:20:20.07$vc4f8/vblo=6,752.99 2006.183.07:20:20.08#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:20:20.08#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:20:20.08#ibcon#ireg 17 cls_cnt 0 2006.183.07:20:20.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:20.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:20.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:20.08#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:20:20.08#ibcon#first serial, iclass 36, count 0 2006.183.07:20:20.08#ibcon#enter sib2, iclass 36, count 0 2006.183.07:20:20.08#ibcon#flushed, iclass 36, count 0 2006.183.07:20:20.08#ibcon#about to write, iclass 36, count 0 2006.183.07:20:20.08#ibcon#wrote, iclass 36, count 0 2006.183.07:20:20.08#ibcon#about to read 3, iclass 36, count 0 2006.183.07:20:20.09#ibcon#read 3, iclass 36, count 0 2006.183.07:20:20.09#ibcon#about to read 4, iclass 36, count 0 2006.183.07:20:20.09#ibcon#read 4, iclass 36, count 0 2006.183.07:20:20.09#ibcon#about to read 5, iclass 36, count 0 2006.183.07:20:20.09#ibcon#read 5, iclass 36, count 0 2006.183.07:20:20.09#ibcon#about to read 6, iclass 36, count 0 2006.183.07:20:20.09#ibcon#read 6, iclass 36, count 0 2006.183.07:20:20.09#ibcon#end of sib2, iclass 36, count 0 2006.183.07:20:20.09#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:20:20.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:20:20.09#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:20:20.09#ibcon#*before write, iclass 36, count 0 2006.183.07:20:20.09#ibcon#enter sib2, iclass 36, count 0 2006.183.07:20:20.09#ibcon#flushed, iclass 36, count 0 2006.183.07:20:20.09#ibcon#about to write, iclass 36, count 0 2006.183.07:20:20.09#ibcon#wrote, iclass 36, count 0 2006.183.07:20:20.09#ibcon#about to read 3, iclass 36, count 0 2006.183.07:20:20.13#ibcon#read 3, iclass 36, count 0 2006.183.07:20:20.13#ibcon#about to read 4, iclass 36, count 0 2006.183.07:20:20.13#ibcon#read 4, iclass 36, count 0 2006.183.07:20:20.13#ibcon#about to read 5, iclass 36, count 0 2006.183.07:20:20.13#ibcon#read 5, iclass 36, count 0 2006.183.07:20:20.13#ibcon#about to read 6, iclass 36, count 0 2006.183.07:20:20.13#ibcon#read 6, iclass 36, count 0 2006.183.07:20:20.13#ibcon#end of sib2, iclass 36, count 0 2006.183.07:20:20.13#ibcon#*after write, iclass 36, count 0 2006.183.07:20:20.13#ibcon#*before return 0, iclass 36, count 0 2006.183.07:20:20.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:20.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:20:20.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:20:20.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:20:20.13$vc4f8/vb=6,4 2006.183.07:20:20.13#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.07:20:20.13#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.07:20:20.13#ibcon#ireg 11 cls_cnt 2 2006.183.07:20:20.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:20.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:20.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:20.19#ibcon#enter wrdev, iclass 38, count 2 2006.183.07:20:20.19#ibcon#first serial, iclass 38, count 2 2006.183.07:20:20.19#ibcon#enter sib2, iclass 38, count 2 2006.183.07:20:20.19#ibcon#flushed, iclass 38, count 2 2006.183.07:20:20.19#ibcon#about to write, iclass 38, count 2 2006.183.07:20:20.19#ibcon#wrote, iclass 38, count 2 2006.183.07:20:20.19#ibcon#about to read 3, iclass 38, count 2 2006.183.07:20:20.21#ibcon#read 3, iclass 38, count 2 2006.183.07:20:20.21#ibcon#about to read 4, iclass 38, count 2 2006.183.07:20:20.21#ibcon#read 4, iclass 38, count 2 2006.183.07:20:20.21#ibcon#about to read 5, iclass 38, count 2 2006.183.07:20:20.21#ibcon#read 5, iclass 38, count 2 2006.183.07:20:20.21#ibcon#about to read 6, iclass 38, count 2 2006.183.07:20:20.21#ibcon#read 6, iclass 38, count 2 2006.183.07:20:20.21#ibcon#end of sib2, iclass 38, count 2 2006.183.07:20:20.21#ibcon#*mode == 0, iclass 38, count 2 2006.183.07:20:20.21#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.07:20:20.21#ibcon#[27=AT06-04\r\n] 2006.183.07:20:20.21#ibcon#*before write, iclass 38, count 2 2006.183.07:20:20.21#ibcon#enter sib2, iclass 38, count 2 2006.183.07:20:20.21#ibcon#flushed, iclass 38, count 2 2006.183.07:20:20.21#ibcon#about to write, iclass 38, count 2 2006.183.07:20:20.21#ibcon#wrote, iclass 38, count 2 2006.183.07:20:20.21#ibcon#about to read 3, iclass 38, count 2 2006.183.07:20:20.24#ibcon#read 3, iclass 38, count 2 2006.183.07:20:20.24#ibcon#about to read 4, iclass 38, count 2 2006.183.07:20:20.24#ibcon#read 4, iclass 38, count 2 2006.183.07:20:20.24#ibcon#about to read 5, iclass 38, count 2 2006.183.07:20:20.24#ibcon#read 5, iclass 38, count 2 2006.183.07:20:20.24#ibcon#about to read 6, iclass 38, count 2 2006.183.07:20:20.24#ibcon#read 6, iclass 38, count 2 2006.183.07:20:20.24#ibcon#end of sib2, iclass 38, count 2 2006.183.07:20:20.24#ibcon#*after write, iclass 38, count 2 2006.183.07:20:20.24#ibcon#*before return 0, iclass 38, count 2 2006.183.07:20:20.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:20.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:20:20.24#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.07:20:20.24#ibcon#ireg 7 cls_cnt 0 2006.183.07:20:20.24#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:20.36#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:20.36#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:20.36#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:20:20.36#ibcon#first serial, iclass 38, count 0 2006.183.07:20:20.36#ibcon#enter sib2, iclass 38, count 0 2006.183.07:20:20.36#ibcon#flushed, iclass 38, count 0 2006.183.07:20:20.36#ibcon#about to write, iclass 38, count 0 2006.183.07:20:20.36#ibcon#wrote, iclass 38, count 0 2006.183.07:20:20.36#ibcon#about to read 3, iclass 38, count 0 2006.183.07:20:20.38#ibcon#read 3, iclass 38, count 0 2006.183.07:20:20.38#ibcon#about to read 4, iclass 38, count 0 2006.183.07:20:20.38#ibcon#read 4, iclass 38, count 0 2006.183.07:20:20.38#ibcon#about to read 5, iclass 38, count 0 2006.183.07:20:20.38#ibcon#read 5, iclass 38, count 0 2006.183.07:20:20.38#ibcon#about to read 6, iclass 38, count 0 2006.183.07:20:20.38#ibcon#read 6, iclass 38, count 0 2006.183.07:20:20.38#ibcon#end of sib2, iclass 38, count 0 2006.183.07:20:20.38#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:20:20.38#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:20:20.38#ibcon#[27=USB\r\n] 2006.183.07:20:20.38#ibcon#*before write, iclass 38, count 0 2006.183.07:20:20.38#ibcon#enter sib2, iclass 38, count 0 2006.183.07:20:20.38#ibcon#flushed, iclass 38, count 0 2006.183.07:20:20.38#ibcon#about to write, iclass 38, count 0 2006.183.07:20:20.38#ibcon#wrote, iclass 38, count 0 2006.183.07:20:20.38#ibcon#about to read 3, iclass 38, count 0 2006.183.07:20:20.41#ibcon#read 3, iclass 38, count 0 2006.183.07:20:20.41#ibcon#about to read 4, iclass 38, count 0 2006.183.07:20:20.41#ibcon#read 4, iclass 38, count 0 2006.183.07:20:20.41#ibcon#about to read 5, iclass 38, count 0 2006.183.07:20:20.41#ibcon#read 5, iclass 38, count 0 2006.183.07:20:20.41#ibcon#about to read 6, iclass 38, count 0 2006.183.07:20:20.41#ibcon#read 6, iclass 38, count 0 2006.183.07:20:20.41#ibcon#end of sib2, iclass 38, count 0 2006.183.07:20:20.41#ibcon#*after write, iclass 38, count 0 2006.183.07:20:20.41#ibcon#*before return 0, iclass 38, count 0 2006.183.07:20:20.41#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:20.41#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:20:20.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:20:20.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:20:20.41$vc4f8/vabw=wide 2006.183.07:20:20.41#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:20:20.41#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:20:20.41#ibcon#ireg 8 cls_cnt 0 2006.183.07:20:20.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:20.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:20.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:20.41#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:20:20.41#ibcon#first serial, iclass 40, count 0 2006.183.07:20:20.41#ibcon#enter sib2, iclass 40, count 0 2006.183.07:20:20.41#ibcon#flushed, iclass 40, count 0 2006.183.07:20:20.41#ibcon#about to write, iclass 40, count 0 2006.183.07:20:20.41#ibcon#wrote, iclass 40, count 0 2006.183.07:20:20.41#ibcon#about to read 3, iclass 40, count 0 2006.183.07:20:20.43#ibcon#read 3, iclass 40, count 0 2006.183.07:20:20.43#ibcon#about to read 4, iclass 40, count 0 2006.183.07:20:20.43#ibcon#read 4, iclass 40, count 0 2006.183.07:20:20.43#ibcon#about to read 5, iclass 40, count 0 2006.183.07:20:20.43#ibcon#read 5, iclass 40, count 0 2006.183.07:20:20.43#ibcon#about to read 6, iclass 40, count 0 2006.183.07:20:20.43#ibcon#read 6, iclass 40, count 0 2006.183.07:20:20.43#ibcon#end of sib2, iclass 40, count 0 2006.183.07:20:20.43#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:20:20.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:20:20.43#ibcon#[25=BW32\r\n] 2006.183.07:20:20.43#ibcon#*before write, iclass 40, count 0 2006.183.07:20:20.43#ibcon#enter sib2, iclass 40, count 0 2006.183.07:20:20.43#ibcon#flushed, iclass 40, count 0 2006.183.07:20:20.43#ibcon#about to write, iclass 40, count 0 2006.183.07:20:20.43#ibcon#wrote, iclass 40, count 0 2006.183.07:20:20.43#ibcon#about to read 3, iclass 40, count 0 2006.183.07:20:20.46#ibcon#read 3, iclass 40, count 0 2006.183.07:20:20.46#ibcon#about to read 4, iclass 40, count 0 2006.183.07:20:20.46#ibcon#read 4, iclass 40, count 0 2006.183.07:20:20.46#ibcon#about to read 5, iclass 40, count 0 2006.183.07:20:20.46#ibcon#read 5, iclass 40, count 0 2006.183.07:20:20.46#ibcon#about to read 6, iclass 40, count 0 2006.183.07:20:20.46#ibcon#read 6, iclass 40, count 0 2006.183.07:20:20.46#ibcon#end of sib2, iclass 40, count 0 2006.183.07:20:20.46#ibcon#*after write, iclass 40, count 0 2006.183.07:20:20.46#ibcon#*before return 0, iclass 40, count 0 2006.183.07:20:20.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:20.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:20:20.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:20:20.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:20:20.46$vc4f8/vbbw=wide 2006.183.07:20:20.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.07:20:20.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.07:20:20.46#ibcon#ireg 8 cls_cnt 0 2006.183.07:20:20.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:20:20.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:20:20.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:20:20.53#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:20:20.53#ibcon#first serial, iclass 4, count 0 2006.183.07:20:20.53#ibcon#enter sib2, iclass 4, count 0 2006.183.07:20:20.53#ibcon#flushed, iclass 4, count 0 2006.183.07:20:20.53#ibcon#about to write, iclass 4, count 0 2006.183.07:20:20.53#ibcon#wrote, iclass 4, count 0 2006.183.07:20:20.53#ibcon#about to read 3, iclass 4, count 0 2006.183.07:20:20.55#ibcon#read 3, iclass 4, count 0 2006.183.07:20:20.55#ibcon#about to read 4, iclass 4, count 0 2006.183.07:20:20.55#ibcon#read 4, iclass 4, count 0 2006.183.07:20:20.55#ibcon#about to read 5, iclass 4, count 0 2006.183.07:20:20.55#ibcon#read 5, iclass 4, count 0 2006.183.07:20:20.55#ibcon#about to read 6, iclass 4, count 0 2006.183.07:20:20.55#ibcon#read 6, iclass 4, count 0 2006.183.07:20:20.55#ibcon#end of sib2, iclass 4, count 0 2006.183.07:20:20.55#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:20:20.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:20:20.55#ibcon#[27=BW32\r\n] 2006.183.07:20:20.55#ibcon#*before write, iclass 4, count 0 2006.183.07:20:20.55#ibcon#enter sib2, iclass 4, count 0 2006.183.07:20:20.55#ibcon#flushed, iclass 4, count 0 2006.183.07:20:20.55#ibcon#about to write, iclass 4, count 0 2006.183.07:20:20.55#ibcon#wrote, iclass 4, count 0 2006.183.07:20:20.55#ibcon#about to read 3, iclass 4, count 0 2006.183.07:20:20.58#ibcon#read 3, iclass 4, count 0 2006.183.07:20:20.58#ibcon#about to read 4, iclass 4, count 0 2006.183.07:20:20.58#ibcon#read 4, iclass 4, count 0 2006.183.07:20:20.58#ibcon#about to read 5, iclass 4, count 0 2006.183.07:20:20.58#ibcon#read 5, iclass 4, count 0 2006.183.07:20:20.58#ibcon#about to read 6, iclass 4, count 0 2006.183.07:20:20.58#ibcon#read 6, iclass 4, count 0 2006.183.07:20:20.58#ibcon#end of sib2, iclass 4, count 0 2006.183.07:20:20.58#ibcon#*after write, iclass 4, count 0 2006.183.07:20:20.58#ibcon#*before return 0, iclass 4, count 0 2006.183.07:20:20.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:20:20.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:20:20.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:20:20.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:20:20.58$4f8m12a/ifd4f 2006.183.07:20:20.58&ifd4f/lo= 2006.183.07:20:20.58&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:20:20.58&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:20:20.58&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:20:20.58&ifd4f/patch= 2006.183.07:20:20.58&ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:20:20.58&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:20:20.58&ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:20:20.58$ifd4f/lo= 2006.183.07:20:20.58$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:20:20.58$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:20:20.58$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:20:20.58$ifd4f/patch= 2006.183.07:20:20.58$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:20:20.58$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:20:20.58$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:20:20.58$4f8m12a/"form=m,16.000,1:2 2006.183.07:20:20.58$4f8m12a/"tpicd 2006.183.07:20:20.58$4f8m12a/echo=off 2006.183.07:20:20.58$4f8m12a/xlog=off 2006.183.07:20:20.58:!2006.183.07:29:50 2006.183.07:20:39.14#trakl#Source acquired 2006.183.07:20:41.14#flagr#flagr/antenna,acquired 2006.183.07:29:50.00:preob 2006.183.07:29:50.00&preob/onsource 2006.183.07:29:51.14/onsource/TRACKING 2006.183.07:29:51.14:!2006.183.07:30:00 2006.183.07:30:00.00:data_valid=on 2006.183.07:30:00.00:midob 2006.183.07:30:00.00&midob/onsource 2006.183.07:30:00.00&midob/wx 2006.183.07:30:00.00&midob/cable 2006.183.07:30:00.00&midob/va 2006.183.07:30:00.00&midob/valo 2006.183.07:30:00.00&midob/vb 2006.183.07:30:00.00&midob/vblo 2006.183.07:30:00.00&midob/vabw 2006.183.07:30:00.00&midob/vbbw 2006.183.07:30:00.00&midob/"form 2006.183.07:30:00.00&midob/xfe 2006.183.07:30:00.00&midob/ifatt 2006.183.07:30:00.00&midob/clockoff 2006.183.07:30:00.00&midob/sy=logmail 2006.183.07:30:00.00&midob/"sy=run setcl adapt & 2006.183.07:30:00.14/onsource/TRACKING 2006.183.07:30:00.14/wx/27.90,996.2,87 2006.183.07:30:00.29/cable/+6.4512E-03 2006.183.07:30:01.38/va/01,08,usb,yes,30,31 2006.183.07:30:01.38/va/02,07,usb,yes,30,31 2006.183.07:30:01.38/va/03,06,usb,yes,31,32 2006.183.07:30:01.38/va/04,07,usb,yes,31,33 2006.183.07:30:01.38/va/05,07,usb,yes,33,34 2006.183.07:30:01.38/va/06,06,usb,yes,32,32 2006.183.07:30:01.38/va/07,06,usb,yes,32,32 2006.183.07:30:01.38/va/08,07,usb,yes,31,30 2006.183.07:30:01.61/valo/01,532.99,yes,locked 2006.183.07:30:01.61/valo/02,572.99,yes,locked 2006.183.07:30:01.61/valo/03,672.99,yes,locked 2006.183.07:30:01.61/valo/04,832.99,yes,locked 2006.183.07:30:01.61/valo/05,652.99,yes,locked 2006.183.07:30:01.61/valo/06,772.99,yes,locked 2006.183.07:30:01.61/valo/07,832.99,yes,locked 2006.183.07:30:01.61/valo/08,852.99,yes,locked 2006.183.07:30:02.70/vb/01,04,usb,yes,29,28 2006.183.07:30:02.70/vb/02,04,usb,yes,31,33 2006.183.07:30:02.70/vb/03,04,usb,yes,28,31 2006.183.07:30:02.70/vb/04,04,usb,yes,28,29 2006.183.07:30:02.70/vb/05,04,usb,yes,27,31 2006.183.07:30:02.70/vb/06,04,usb,yes,28,31 2006.183.07:30:02.70/vb/07,04,usb,yes,30,30 2006.183.07:30:02.70/vb/08,04,usb,yes,28,31 2006.183.07:30:02.93/vblo/01,632.99,yes,locked 2006.183.07:30:02.93/vblo/02,640.99,yes,locked 2006.183.07:30:02.93/vblo/03,656.99,yes,locked 2006.183.07:30:02.93/vblo/04,712.99,yes,locked 2006.183.07:30:02.93/vblo/05,744.99,yes,locked 2006.183.07:30:02.93/vblo/06,752.99,yes,locked 2006.183.07:30:02.93/vblo/07,734.99,yes,locked 2006.183.07:30:02.93/vblo/08,744.99,yes,locked 2006.183.07:30:03.08/vabw/8 2006.183.07:30:03.23/vbbw/8 2006.183.07:30:03.34/xfe/off,on,15.0 2006.183.07:30:03.72/ifatt/23,28,28,28 2006.183.07:30:03.72&clockoff/"gps-fmout=1p 2006.183.07:30:03.72&clockoff/fmout-gps=1p 2006.183.07:30:04.08/fmout-gps/S +3.30E-07 2006.183.07:30:04.16:!2006.183.07:31:00 2006.183.07:31:00.00:data_valid=off 2006.183.07:31:00.00:postob 2006.183.07:31:00.00&postob/cable 2006.183.07:31:00.01&postob/wx 2006.183.07:31:00.01&postob/clockoff 2006.183.07:31:00.16/cable/+6.4513E-03 2006.183.07:31:00.16/wx/27.90,996.2,88 2006.183.07:31:01.08/fmout-gps/S +3.30E-07 2006.183.07:31:01.08:scan_name=183-0733,k06183,60 2006.183.07:31:01.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.183.07:31:01.15#flagr#flagr/antenna,new-source 2006.183.07:31:02.14:checkk5 2006.183.07:31:02.14&checkk5/chk_autoobs=1 2006.183.07:31:02.14&checkk5/chk_autoobs=2 2006.183.07:31:02.15&checkk5/chk_autoobs=3 2006.183.07:31:02.15&checkk5/chk_autoobs=4 2006.183.07:31:02.15&checkk5/chk_obsdata=1 2006.183.07:31:02.16&checkk5/chk_obsdata=2 2006.183.07:31:02.16&checkk5/chk_obsdata=3 2006.183.07:31:02.16&checkk5/chk_obsdata=4 2006.183.07:31:02.17&checkk5/k5log=1 2006.183.07:31:02.17&checkk5/k5log=2 2006.183.07:31:02.17&checkk5/k5log=3 2006.183.07:31:02.18&checkk5/k5log=4 2006.183.07:31:02.18&checkk5/obsinfo 2006.183.07:31:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:31:02.94/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:31:03.33/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:31:03.70/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:31:04.08/chk_obsdata//k5ts1/T1830730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:31:04.44/chk_obsdata//k5ts2/T1830730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:31:04.82/chk_obsdata//k5ts3/T1830730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:31:05.18/chk_obsdata//k5ts4/T1830730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:31:05.89/k5log//k5ts1_log_newline 2006.183.07:31:06.60/k5log//k5ts2_log_newline 2006.183.07:31:07.29/k5log//k5ts3_log_newline 2006.183.07:31:07.97/k5log//k5ts4_log_newline 2006.183.07:31:07.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:31:07.99:4f8m12a=1 2006.183.07:31:08.00$4f8m12a/echo=on 2006.183.07:31:08.00$4f8m12a/pcalon 2006.183.07:31:08.00$pcalon/"no phase cal control is implemented here 2006.183.07:31:08.00$4f8m12a/"tpicd=stop 2006.183.07:31:08.00$4f8m12a/vc4f8 2006.183.07:31:08.00$vc4f8/valo=1,532.99 2006.183.07:31:08.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:31:08.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:31:08.00#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:08.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:08.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:08.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:08.00#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:31:08.00#ibcon#first serial, iclass 13, count 0 2006.183.07:31:08.00#ibcon#enter sib2, iclass 13, count 0 2006.183.07:31:08.00#ibcon#flushed, iclass 13, count 0 2006.183.07:31:08.00#ibcon#about to write, iclass 13, count 0 2006.183.07:31:08.00#ibcon#wrote, iclass 13, count 0 2006.183.07:31:08.00#ibcon#about to read 3, iclass 13, count 0 2006.183.07:31:08.04#ibcon#read 3, iclass 13, count 0 2006.183.07:31:08.04#ibcon#about to read 4, iclass 13, count 0 2006.183.07:31:08.04#ibcon#read 4, iclass 13, count 0 2006.183.07:31:08.04#ibcon#about to read 5, iclass 13, count 0 2006.183.07:31:08.04#ibcon#read 5, iclass 13, count 0 2006.183.07:31:08.04#ibcon#about to read 6, iclass 13, count 0 2006.183.07:31:08.04#ibcon#read 6, iclass 13, count 0 2006.183.07:31:08.04#ibcon#end of sib2, iclass 13, count 0 2006.183.07:31:08.04#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:31:08.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:31:08.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:31:08.04#ibcon#*before write, iclass 13, count 0 2006.183.07:31:08.04#ibcon#enter sib2, iclass 13, count 0 2006.183.07:31:08.04#ibcon#flushed, iclass 13, count 0 2006.183.07:31:08.04#ibcon#about to write, iclass 13, count 0 2006.183.07:31:08.04#ibcon#wrote, iclass 13, count 0 2006.183.07:31:08.04#ibcon#about to read 3, iclass 13, count 0 2006.183.07:31:08.08#ibcon#read 3, iclass 13, count 0 2006.183.07:31:08.08#ibcon#about to read 4, iclass 13, count 0 2006.183.07:31:08.08#ibcon#read 4, iclass 13, count 0 2006.183.07:31:08.08#ibcon#about to read 5, iclass 13, count 0 2006.183.07:31:08.08#ibcon#read 5, iclass 13, count 0 2006.183.07:31:08.08#ibcon#about to read 6, iclass 13, count 0 2006.183.07:31:08.08#ibcon#read 6, iclass 13, count 0 2006.183.07:31:08.08#ibcon#end of sib2, iclass 13, count 0 2006.183.07:31:08.09#ibcon#*after write, iclass 13, count 0 2006.183.07:31:08.09#ibcon#*before return 0, iclass 13, count 0 2006.183.07:31:08.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:08.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:08.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:31:08.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:31:08.09$vc4f8/va=1,8 2006.183.07:31:08.09#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:31:08.09#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:31:08.09#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:08.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:08.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:08.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:08.09#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:31:08.09#ibcon#first serial, iclass 15, count 2 2006.183.07:31:08.09#ibcon#enter sib2, iclass 15, count 2 2006.183.07:31:08.09#ibcon#flushed, iclass 15, count 2 2006.183.07:31:08.09#ibcon#about to write, iclass 15, count 2 2006.183.07:31:08.09#ibcon#wrote, iclass 15, count 2 2006.183.07:31:08.09#ibcon#about to read 3, iclass 15, count 2 2006.183.07:31:08.10#ibcon#read 3, iclass 15, count 2 2006.183.07:31:08.11#ibcon#about to read 4, iclass 15, count 2 2006.183.07:31:08.11#ibcon#read 4, iclass 15, count 2 2006.183.07:31:08.11#ibcon#about to read 5, iclass 15, count 2 2006.183.07:31:08.11#ibcon#read 5, iclass 15, count 2 2006.183.07:31:08.11#ibcon#about to read 6, iclass 15, count 2 2006.183.07:31:08.11#ibcon#read 6, iclass 15, count 2 2006.183.07:31:08.11#ibcon#end of sib2, iclass 15, count 2 2006.183.07:31:08.11#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:31:08.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:31:08.11#ibcon#[25=AT01-08\r\n] 2006.183.07:31:08.11#ibcon#*before write, iclass 15, count 2 2006.183.07:31:08.11#ibcon#enter sib2, iclass 15, count 2 2006.183.07:31:08.11#ibcon#flushed, iclass 15, count 2 2006.183.07:31:08.11#ibcon#about to write, iclass 15, count 2 2006.183.07:31:08.11#ibcon#wrote, iclass 15, count 2 2006.183.07:31:08.11#ibcon#about to read 3, iclass 15, count 2 2006.183.07:31:08.13#ibcon#read 3, iclass 15, count 2 2006.183.07:31:08.14#ibcon#about to read 4, iclass 15, count 2 2006.183.07:31:08.14#ibcon#read 4, iclass 15, count 2 2006.183.07:31:08.14#ibcon#about to read 5, iclass 15, count 2 2006.183.07:31:08.14#ibcon#read 5, iclass 15, count 2 2006.183.07:31:08.14#ibcon#about to read 6, iclass 15, count 2 2006.183.07:31:08.14#ibcon#read 6, iclass 15, count 2 2006.183.07:31:08.14#ibcon#end of sib2, iclass 15, count 2 2006.183.07:31:08.14#ibcon#*after write, iclass 15, count 2 2006.183.07:31:08.14#ibcon#*before return 0, iclass 15, count 2 2006.183.07:31:08.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:08.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:08.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:31:08.14#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:08.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:08.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:08.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:08.25#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:31:08.25#ibcon#first serial, iclass 15, count 0 2006.183.07:31:08.25#ibcon#enter sib2, iclass 15, count 0 2006.183.07:31:08.25#ibcon#flushed, iclass 15, count 0 2006.183.07:31:08.25#ibcon#about to write, iclass 15, count 0 2006.183.07:31:08.26#ibcon#wrote, iclass 15, count 0 2006.183.07:31:08.26#ibcon#about to read 3, iclass 15, count 0 2006.183.07:31:08.27#ibcon#read 3, iclass 15, count 0 2006.183.07:31:08.27#ibcon#about to read 4, iclass 15, count 0 2006.183.07:31:08.27#ibcon#read 4, iclass 15, count 0 2006.183.07:31:08.27#ibcon#about to read 5, iclass 15, count 0 2006.183.07:31:08.27#ibcon#read 5, iclass 15, count 0 2006.183.07:31:08.27#ibcon#about to read 6, iclass 15, count 0 2006.183.07:31:08.27#ibcon#read 6, iclass 15, count 0 2006.183.07:31:08.28#ibcon#end of sib2, iclass 15, count 0 2006.183.07:31:08.28#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:31:08.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:31:08.28#ibcon#[25=USB\r\n] 2006.183.07:31:08.28#ibcon#*before write, iclass 15, count 0 2006.183.07:31:08.28#ibcon#enter sib2, iclass 15, count 0 2006.183.07:31:08.28#ibcon#flushed, iclass 15, count 0 2006.183.07:31:08.28#ibcon#about to write, iclass 15, count 0 2006.183.07:31:08.28#ibcon#wrote, iclass 15, count 0 2006.183.07:31:08.28#ibcon#about to read 3, iclass 15, count 0 2006.183.07:31:08.30#ibcon#read 3, iclass 15, count 0 2006.183.07:31:08.30#ibcon#about to read 4, iclass 15, count 0 2006.183.07:31:08.30#ibcon#read 4, iclass 15, count 0 2006.183.07:31:08.30#ibcon#about to read 5, iclass 15, count 0 2006.183.07:31:08.30#ibcon#read 5, iclass 15, count 0 2006.183.07:31:08.30#ibcon#about to read 6, iclass 15, count 0 2006.183.07:31:08.30#ibcon#read 6, iclass 15, count 0 2006.183.07:31:08.30#ibcon#end of sib2, iclass 15, count 0 2006.183.07:31:08.31#ibcon#*after write, iclass 15, count 0 2006.183.07:31:08.31#ibcon#*before return 0, iclass 15, count 0 2006.183.07:31:08.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:08.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:08.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:31:08.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:31:08.31$vc4f8/valo=2,572.99 2006.183.07:31:08.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:31:08.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:31:08.31#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:08.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:08.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:08.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:08.31#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:31:08.31#ibcon#first serial, iclass 17, count 0 2006.183.07:31:08.31#ibcon#enter sib2, iclass 17, count 0 2006.183.07:31:08.31#ibcon#flushed, iclass 17, count 0 2006.183.07:31:08.31#ibcon#about to write, iclass 17, count 0 2006.183.07:31:08.31#ibcon#wrote, iclass 17, count 0 2006.183.07:31:08.31#ibcon#about to read 3, iclass 17, count 0 2006.183.07:31:08.33#ibcon#read 3, iclass 17, count 0 2006.183.07:31:08.33#ibcon#about to read 4, iclass 17, count 0 2006.183.07:31:08.33#ibcon#read 4, iclass 17, count 0 2006.183.07:31:08.33#ibcon#about to read 5, iclass 17, count 0 2006.183.07:31:08.33#ibcon#read 5, iclass 17, count 0 2006.183.07:31:08.33#ibcon#about to read 6, iclass 17, count 0 2006.183.07:31:08.33#ibcon#read 6, iclass 17, count 0 2006.183.07:31:08.33#ibcon#end of sib2, iclass 17, count 0 2006.183.07:31:08.33#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:31:08.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:31:08.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:31:08.33#ibcon#*before write, iclass 17, count 0 2006.183.07:31:08.33#ibcon#enter sib2, iclass 17, count 0 2006.183.07:31:08.33#ibcon#flushed, iclass 17, count 0 2006.183.07:31:08.33#ibcon#about to write, iclass 17, count 0 2006.183.07:31:08.33#ibcon#wrote, iclass 17, count 0 2006.183.07:31:08.33#ibcon#about to read 3, iclass 17, count 0 2006.183.07:31:08.37#ibcon#read 3, iclass 17, count 0 2006.183.07:31:08.37#ibcon#about to read 4, iclass 17, count 0 2006.183.07:31:08.37#ibcon#read 4, iclass 17, count 0 2006.183.07:31:08.37#ibcon#about to read 5, iclass 17, count 0 2006.183.07:31:08.38#ibcon#read 5, iclass 17, count 0 2006.183.07:31:08.38#ibcon#about to read 6, iclass 17, count 0 2006.183.07:31:08.38#ibcon#read 6, iclass 17, count 0 2006.183.07:31:08.38#ibcon#end of sib2, iclass 17, count 0 2006.183.07:31:08.38#ibcon#*after write, iclass 17, count 0 2006.183.07:31:08.38#ibcon#*before return 0, iclass 17, count 0 2006.183.07:31:08.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:08.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:08.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:31:08.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:31:08.38$vc4f8/va=2,7 2006.183.07:31:08.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:31:08.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:31:08.38#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:08.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:08.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:08.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:08.43#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:31:08.43#ibcon#first serial, iclass 19, count 2 2006.183.07:31:08.43#ibcon#enter sib2, iclass 19, count 2 2006.183.07:31:08.43#ibcon#flushed, iclass 19, count 2 2006.183.07:31:08.43#ibcon#about to write, iclass 19, count 2 2006.183.07:31:08.43#ibcon#wrote, iclass 19, count 2 2006.183.07:31:08.43#ibcon#about to read 3, iclass 19, count 2 2006.183.07:31:08.44#ibcon#read 3, iclass 19, count 2 2006.183.07:31:08.44#ibcon#about to read 4, iclass 19, count 2 2006.183.07:31:08.44#ibcon#read 4, iclass 19, count 2 2006.183.07:31:08.44#ibcon#about to read 5, iclass 19, count 2 2006.183.07:31:08.44#ibcon#read 5, iclass 19, count 2 2006.183.07:31:08.44#ibcon#about to read 6, iclass 19, count 2 2006.183.07:31:08.45#ibcon#read 6, iclass 19, count 2 2006.183.07:31:08.45#ibcon#end of sib2, iclass 19, count 2 2006.183.07:31:08.45#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:31:08.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:31:08.45#ibcon#[25=AT02-07\r\n] 2006.183.07:31:08.45#ibcon#*before write, iclass 19, count 2 2006.183.07:31:08.45#ibcon#enter sib2, iclass 19, count 2 2006.183.07:31:08.45#ibcon#flushed, iclass 19, count 2 2006.183.07:31:08.45#ibcon#about to write, iclass 19, count 2 2006.183.07:31:08.45#ibcon#wrote, iclass 19, count 2 2006.183.07:31:08.45#ibcon#about to read 3, iclass 19, count 2 2006.183.07:31:08.47#ibcon#read 3, iclass 19, count 2 2006.183.07:31:08.47#ibcon#about to read 4, iclass 19, count 2 2006.183.07:31:08.47#ibcon#read 4, iclass 19, count 2 2006.183.07:31:08.47#ibcon#about to read 5, iclass 19, count 2 2006.183.07:31:08.47#ibcon#read 5, iclass 19, count 2 2006.183.07:31:08.48#ibcon#about to read 6, iclass 19, count 2 2006.183.07:31:08.48#ibcon#read 6, iclass 19, count 2 2006.183.07:31:08.48#ibcon#end of sib2, iclass 19, count 2 2006.183.07:31:08.48#ibcon#*after write, iclass 19, count 2 2006.183.07:31:08.48#ibcon#*before return 0, iclass 19, count 2 2006.183.07:31:08.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:08.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:08.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:31:08.48#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:08.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:08.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:08.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:08.59#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:31:08.59#ibcon#first serial, iclass 19, count 0 2006.183.07:31:08.59#ibcon#enter sib2, iclass 19, count 0 2006.183.07:31:08.59#ibcon#flushed, iclass 19, count 0 2006.183.07:31:08.59#ibcon#about to write, iclass 19, count 0 2006.183.07:31:08.59#ibcon#wrote, iclass 19, count 0 2006.183.07:31:08.60#ibcon#about to read 3, iclass 19, count 0 2006.183.07:31:08.61#ibcon#read 3, iclass 19, count 0 2006.183.07:31:08.61#ibcon#about to read 4, iclass 19, count 0 2006.183.07:31:08.61#ibcon#read 4, iclass 19, count 0 2006.183.07:31:08.61#ibcon#about to read 5, iclass 19, count 0 2006.183.07:31:08.61#ibcon#read 5, iclass 19, count 0 2006.183.07:31:08.61#ibcon#about to read 6, iclass 19, count 0 2006.183.07:31:08.61#ibcon#read 6, iclass 19, count 0 2006.183.07:31:08.61#ibcon#end of sib2, iclass 19, count 0 2006.183.07:31:08.62#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:31:08.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:31:08.62#ibcon#[25=USB\r\n] 2006.183.07:31:08.62#ibcon#*before write, iclass 19, count 0 2006.183.07:31:08.62#ibcon#enter sib2, iclass 19, count 0 2006.183.07:31:08.62#ibcon#flushed, iclass 19, count 0 2006.183.07:31:08.62#ibcon#about to write, iclass 19, count 0 2006.183.07:31:08.62#ibcon#wrote, iclass 19, count 0 2006.183.07:31:08.62#ibcon#about to read 3, iclass 19, count 0 2006.183.07:31:08.64#ibcon#read 3, iclass 19, count 0 2006.183.07:31:08.64#ibcon#about to read 4, iclass 19, count 0 2006.183.07:31:08.64#ibcon#read 4, iclass 19, count 0 2006.183.07:31:08.64#ibcon#about to read 5, iclass 19, count 0 2006.183.07:31:08.64#ibcon#read 5, iclass 19, count 0 2006.183.07:31:08.64#ibcon#about to read 6, iclass 19, count 0 2006.183.07:31:08.64#ibcon#read 6, iclass 19, count 0 2006.183.07:31:08.64#ibcon#end of sib2, iclass 19, count 0 2006.183.07:31:08.65#ibcon#*after write, iclass 19, count 0 2006.183.07:31:08.65#ibcon#*before return 0, iclass 19, count 0 2006.183.07:31:08.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:08.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:08.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:31:08.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:31:08.65$vc4f8/valo=3,672.99 2006.183.07:31:08.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:31:08.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:31:08.65#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:08.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:08.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:08.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:08.65#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:31:08.65#ibcon#first serial, iclass 21, count 0 2006.183.07:31:08.65#ibcon#enter sib2, iclass 21, count 0 2006.183.07:31:08.65#ibcon#flushed, iclass 21, count 0 2006.183.07:31:08.65#ibcon#about to write, iclass 21, count 0 2006.183.07:31:08.65#ibcon#wrote, iclass 21, count 0 2006.183.07:31:08.65#ibcon#about to read 3, iclass 21, count 0 2006.183.07:31:08.67#ibcon#read 3, iclass 21, count 0 2006.183.07:31:08.67#ibcon#about to read 4, iclass 21, count 0 2006.183.07:31:08.67#ibcon#read 4, iclass 21, count 0 2006.183.07:31:08.67#ibcon#about to read 5, iclass 21, count 0 2006.183.07:31:08.67#ibcon#read 5, iclass 21, count 0 2006.183.07:31:08.67#ibcon#about to read 6, iclass 21, count 0 2006.183.07:31:08.67#ibcon#read 6, iclass 21, count 0 2006.183.07:31:08.67#ibcon#end of sib2, iclass 21, count 0 2006.183.07:31:08.67#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:31:08.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:31:08.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:31:08.67#ibcon#*before write, iclass 21, count 0 2006.183.07:31:08.67#ibcon#enter sib2, iclass 21, count 0 2006.183.07:31:08.67#ibcon#flushed, iclass 21, count 0 2006.183.07:31:08.67#ibcon#about to write, iclass 21, count 0 2006.183.07:31:08.67#ibcon#wrote, iclass 21, count 0 2006.183.07:31:08.67#ibcon#about to read 3, iclass 21, count 0 2006.183.07:31:08.71#ibcon#read 3, iclass 21, count 0 2006.183.07:31:08.71#ibcon#about to read 4, iclass 21, count 0 2006.183.07:31:08.71#ibcon#read 4, iclass 21, count 0 2006.183.07:31:08.71#ibcon#about to read 5, iclass 21, count 0 2006.183.07:31:08.72#ibcon#read 5, iclass 21, count 0 2006.183.07:31:08.72#ibcon#about to read 6, iclass 21, count 0 2006.183.07:31:08.72#ibcon#read 6, iclass 21, count 0 2006.183.07:31:08.72#ibcon#end of sib2, iclass 21, count 0 2006.183.07:31:08.72#ibcon#*after write, iclass 21, count 0 2006.183.07:31:08.72#ibcon#*before return 0, iclass 21, count 0 2006.183.07:31:08.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:08.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:08.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:31:08.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:31:08.72$vc4f8/va=3,6 2006.183.07:31:08.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:31:08.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:31:08.72#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:08.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:08.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:08.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:08.77#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:31:08.77#ibcon#first serial, iclass 23, count 2 2006.183.07:31:08.77#ibcon#enter sib2, iclass 23, count 2 2006.183.07:31:08.77#ibcon#flushed, iclass 23, count 2 2006.183.07:31:08.77#ibcon#about to write, iclass 23, count 2 2006.183.07:31:08.77#ibcon#wrote, iclass 23, count 2 2006.183.07:31:08.77#ibcon#about to read 3, iclass 23, count 2 2006.183.07:31:08.78#ibcon#read 3, iclass 23, count 2 2006.183.07:31:08.78#ibcon#about to read 4, iclass 23, count 2 2006.183.07:31:08.78#ibcon#read 4, iclass 23, count 2 2006.183.07:31:08.78#ibcon#about to read 5, iclass 23, count 2 2006.183.07:31:08.78#ibcon#read 5, iclass 23, count 2 2006.183.07:31:08.78#ibcon#about to read 6, iclass 23, count 2 2006.183.07:31:08.79#ibcon#read 6, iclass 23, count 2 2006.183.07:31:08.79#ibcon#end of sib2, iclass 23, count 2 2006.183.07:31:08.79#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:31:08.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:31:08.79#ibcon#[25=AT03-06\r\n] 2006.183.07:31:08.79#ibcon#*before write, iclass 23, count 2 2006.183.07:31:08.79#ibcon#enter sib2, iclass 23, count 2 2006.183.07:31:08.79#ibcon#flushed, iclass 23, count 2 2006.183.07:31:08.79#ibcon#about to write, iclass 23, count 2 2006.183.07:31:08.79#ibcon#wrote, iclass 23, count 2 2006.183.07:31:08.79#ibcon#about to read 3, iclass 23, count 2 2006.183.07:31:08.81#ibcon#read 3, iclass 23, count 2 2006.183.07:31:08.81#ibcon#about to read 4, iclass 23, count 2 2006.183.07:31:08.81#ibcon#read 4, iclass 23, count 2 2006.183.07:31:08.81#ibcon#about to read 5, iclass 23, count 2 2006.183.07:31:08.81#ibcon#read 5, iclass 23, count 2 2006.183.07:31:08.82#ibcon#about to read 6, iclass 23, count 2 2006.183.07:31:08.82#ibcon#read 6, iclass 23, count 2 2006.183.07:31:08.82#ibcon#end of sib2, iclass 23, count 2 2006.183.07:31:08.82#ibcon#*after write, iclass 23, count 2 2006.183.07:31:08.82#ibcon#*before return 0, iclass 23, count 2 2006.183.07:31:08.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:08.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:08.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:31:08.82#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:08.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:08.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:08.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:08.93#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:31:08.93#ibcon#first serial, iclass 23, count 0 2006.183.07:31:08.93#ibcon#enter sib2, iclass 23, count 0 2006.183.07:31:08.93#ibcon#flushed, iclass 23, count 0 2006.183.07:31:08.93#ibcon#about to write, iclass 23, count 0 2006.183.07:31:08.93#ibcon#wrote, iclass 23, count 0 2006.183.07:31:08.94#ibcon#about to read 3, iclass 23, count 0 2006.183.07:31:08.95#ibcon#read 3, iclass 23, count 0 2006.183.07:31:08.95#ibcon#about to read 4, iclass 23, count 0 2006.183.07:31:08.95#ibcon#read 4, iclass 23, count 0 2006.183.07:31:08.95#ibcon#about to read 5, iclass 23, count 0 2006.183.07:31:08.95#ibcon#read 5, iclass 23, count 0 2006.183.07:31:08.95#ibcon#about to read 6, iclass 23, count 0 2006.183.07:31:08.95#ibcon#read 6, iclass 23, count 0 2006.183.07:31:08.95#ibcon#end of sib2, iclass 23, count 0 2006.183.07:31:08.96#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:31:08.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:31:08.96#ibcon#[25=USB\r\n] 2006.183.07:31:08.96#ibcon#*before write, iclass 23, count 0 2006.183.07:31:08.96#ibcon#enter sib2, iclass 23, count 0 2006.183.07:31:08.96#ibcon#flushed, iclass 23, count 0 2006.183.07:31:08.96#ibcon#about to write, iclass 23, count 0 2006.183.07:31:08.96#ibcon#wrote, iclass 23, count 0 2006.183.07:31:08.96#ibcon#about to read 3, iclass 23, count 0 2006.183.07:31:08.98#ibcon#read 3, iclass 23, count 0 2006.183.07:31:08.98#ibcon#about to read 4, iclass 23, count 0 2006.183.07:31:08.98#ibcon#read 4, iclass 23, count 0 2006.183.07:31:08.98#ibcon#about to read 5, iclass 23, count 0 2006.183.07:31:08.98#ibcon#read 5, iclass 23, count 0 2006.183.07:31:08.98#ibcon#about to read 6, iclass 23, count 0 2006.183.07:31:08.98#ibcon#read 6, iclass 23, count 0 2006.183.07:31:08.98#ibcon#end of sib2, iclass 23, count 0 2006.183.07:31:08.99#ibcon#*after write, iclass 23, count 0 2006.183.07:31:08.99#ibcon#*before return 0, iclass 23, count 0 2006.183.07:31:08.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:08.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:08.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:31:08.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:31:08.99$vc4f8/valo=4,832.99 2006.183.07:31:08.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:31:08.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:31:08.99#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:08.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:08.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:08.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:08.99#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:31:08.99#ibcon#first serial, iclass 25, count 0 2006.183.07:31:08.99#ibcon#enter sib2, iclass 25, count 0 2006.183.07:31:08.99#ibcon#flushed, iclass 25, count 0 2006.183.07:31:08.99#ibcon#about to write, iclass 25, count 0 2006.183.07:31:08.99#ibcon#wrote, iclass 25, count 0 2006.183.07:31:08.99#ibcon#about to read 3, iclass 25, count 0 2006.183.07:31:09.00#ibcon#read 3, iclass 25, count 0 2006.183.07:31:09.00#ibcon#about to read 4, iclass 25, count 0 2006.183.07:31:09.00#ibcon#read 4, iclass 25, count 0 2006.183.07:31:09.00#ibcon#about to read 5, iclass 25, count 0 2006.183.07:31:09.00#ibcon#read 5, iclass 25, count 0 2006.183.07:31:09.00#ibcon#about to read 6, iclass 25, count 0 2006.183.07:31:09.00#ibcon#read 6, iclass 25, count 0 2006.183.07:31:09.01#ibcon#end of sib2, iclass 25, count 0 2006.183.07:31:09.01#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:31:09.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:31:09.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:31:09.01#ibcon#*before write, iclass 25, count 0 2006.183.07:31:09.01#ibcon#enter sib2, iclass 25, count 0 2006.183.07:31:09.01#ibcon#flushed, iclass 25, count 0 2006.183.07:31:09.01#ibcon#about to write, iclass 25, count 0 2006.183.07:31:09.01#ibcon#wrote, iclass 25, count 0 2006.183.07:31:09.01#ibcon#about to read 3, iclass 25, count 0 2006.183.07:31:09.04#ibcon#read 3, iclass 25, count 0 2006.183.07:31:09.04#ibcon#about to read 4, iclass 25, count 0 2006.183.07:31:09.04#ibcon#read 4, iclass 25, count 0 2006.183.07:31:09.04#ibcon#about to read 5, iclass 25, count 0 2006.183.07:31:09.04#ibcon#read 5, iclass 25, count 0 2006.183.07:31:09.04#ibcon#about to read 6, iclass 25, count 0 2006.183.07:31:09.05#ibcon#read 6, iclass 25, count 0 2006.183.07:31:09.05#ibcon#end of sib2, iclass 25, count 0 2006.183.07:31:09.05#ibcon#*after write, iclass 25, count 0 2006.183.07:31:09.05#ibcon#*before return 0, iclass 25, count 0 2006.183.07:31:09.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:09.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:09.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:31:09.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:31:09.05$vc4f8/va=4,7 2006.183.07:31:09.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.07:31:09.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.07:31:09.05#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:09.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:09.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:09.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:09.10#ibcon#enter wrdev, iclass 27, count 2 2006.183.07:31:09.10#ibcon#first serial, iclass 27, count 2 2006.183.07:31:09.10#ibcon#enter sib2, iclass 27, count 2 2006.183.07:31:09.10#ibcon#flushed, iclass 27, count 2 2006.183.07:31:09.10#ibcon#about to write, iclass 27, count 2 2006.183.07:31:09.10#ibcon#wrote, iclass 27, count 2 2006.183.07:31:09.11#ibcon#about to read 3, iclass 27, count 2 2006.183.07:31:09.12#ibcon#read 3, iclass 27, count 2 2006.183.07:31:09.12#ibcon#about to read 4, iclass 27, count 2 2006.183.07:31:09.12#ibcon#read 4, iclass 27, count 2 2006.183.07:31:09.12#ibcon#about to read 5, iclass 27, count 2 2006.183.07:31:09.12#ibcon#read 5, iclass 27, count 2 2006.183.07:31:09.12#ibcon#about to read 6, iclass 27, count 2 2006.183.07:31:09.13#ibcon#read 6, iclass 27, count 2 2006.183.07:31:09.13#ibcon#end of sib2, iclass 27, count 2 2006.183.07:31:09.13#ibcon#*mode == 0, iclass 27, count 2 2006.183.07:31:09.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.07:31:09.13#ibcon#[25=AT04-07\r\n] 2006.183.07:31:09.13#ibcon#*before write, iclass 27, count 2 2006.183.07:31:09.13#ibcon#enter sib2, iclass 27, count 2 2006.183.07:31:09.13#ibcon#flushed, iclass 27, count 2 2006.183.07:31:09.13#ibcon#about to write, iclass 27, count 2 2006.183.07:31:09.13#ibcon#wrote, iclass 27, count 2 2006.183.07:31:09.13#ibcon#about to read 3, iclass 27, count 2 2006.183.07:31:09.15#ibcon#read 3, iclass 27, count 2 2006.183.07:31:09.15#ibcon#about to read 4, iclass 27, count 2 2006.183.07:31:09.15#ibcon#read 4, iclass 27, count 2 2006.183.07:31:09.15#ibcon#about to read 5, iclass 27, count 2 2006.183.07:31:09.15#ibcon#read 5, iclass 27, count 2 2006.183.07:31:09.16#ibcon#about to read 6, iclass 27, count 2 2006.183.07:31:09.16#ibcon#read 6, iclass 27, count 2 2006.183.07:31:09.16#ibcon#end of sib2, iclass 27, count 2 2006.183.07:31:09.16#ibcon#*after write, iclass 27, count 2 2006.183.07:31:09.16#ibcon#*before return 0, iclass 27, count 2 2006.183.07:31:09.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:09.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:09.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.07:31:09.16#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:09.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:09.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:09.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:09.27#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:31:09.27#ibcon#first serial, iclass 27, count 0 2006.183.07:31:09.27#ibcon#enter sib2, iclass 27, count 0 2006.183.07:31:09.27#ibcon#flushed, iclass 27, count 0 2006.183.07:31:09.27#ibcon#about to write, iclass 27, count 0 2006.183.07:31:09.27#ibcon#wrote, iclass 27, count 0 2006.183.07:31:09.28#ibcon#about to read 3, iclass 27, count 0 2006.183.07:31:09.29#ibcon#read 3, iclass 27, count 0 2006.183.07:31:09.29#ibcon#about to read 4, iclass 27, count 0 2006.183.07:31:09.29#ibcon#read 4, iclass 27, count 0 2006.183.07:31:09.29#ibcon#about to read 5, iclass 27, count 0 2006.183.07:31:09.29#ibcon#read 5, iclass 27, count 0 2006.183.07:31:09.29#ibcon#about to read 6, iclass 27, count 0 2006.183.07:31:09.29#ibcon#read 6, iclass 27, count 0 2006.183.07:31:09.29#ibcon#end of sib2, iclass 27, count 0 2006.183.07:31:09.30#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:31:09.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:31:09.30#ibcon#[25=USB\r\n] 2006.183.07:31:09.30#ibcon#*before write, iclass 27, count 0 2006.183.07:31:09.30#ibcon#enter sib2, iclass 27, count 0 2006.183.07:31:09.30#ibcon#flushed, iclass 27, count 0 2006.183.07:31:09.30#ibcon#about to write, iclass 27, count 0 2006.183.07:31:09.30#ibcon#wrote, iclass 27, count 0 2006.183.07:31:09.30#ibcon#about to read 3, iclass 27, count 0 2006.183.07:31:09.32#ibcon#read 3, iclass 27, count 0 2006.183.07:31:09.32#ibcon#about to read 4, iclass 27, count 0 2006.183.07:31:09.32#ibcon#read 4, iclass 27, count 0 2006.183.07:31:09.32#ibcon#about to read 5, iclass 27, count 0 2006.183.07:31:09.32#ibcon#read 5, iclass 27, count 0 2006.183.07:31:09.32#ibcon#about to read 6, iclass 27, count 0 2006.183.07:31:09.32#ibcon#read 6, iclass 27, count 0 2006.183.07:31:09.32#ibcon#end of sib2, iclass 27, count 0 2006.183.07:31:09.33#ibcon#*after write, iclass 27, count 0 2006.183.07:31:09.33#ibcon#*before return 0, iclass 27, count 0 2006.183.07:31:09.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:09.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:09.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:31:09.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:31:09.33$vc4f8/valo=5,652.99 2006.183.07:31:09.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.07:31:09.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.07:31:09.33#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:09.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:09.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:09.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:09.33#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:31:09.33#ibcon#first serial, iclass 29, count 0 2006.183.07:31:09.33#ibcon#enter sib2, iclass 29, count 0 2006.183.07:31:09.33#ibcon#flushed, iclass 29, count 0 2006.183.07:31:09.33#ibcon#about to write, iclass 29, count 0 2006.183.07:31:09.33#ibcon#wrote, iclass 29, count 0 2006.183.07:31:09.33#ibcon#about to read 3, iclass 29, count 0 2006.183.07:31:09.34#ibcon#read 3, iclass 29, count 0 2006.183.07:31:09.34#ibcon#about to read 4, iclass 29, count 0 2006.183.07:31:09.34#ibcon#read 4, iclass 29, count 0 2006.183.07:31:09.34#ibcon#about to read 5, iclass 29, count 0 2006.183.07:31:09.34#ibcon#read 5, iclass 29, count 0 2006.183.07:31:09.34#ibcon#about to read 6, iclass 29, count 0 2006.183.07:31:09.34#ibcon#read 6, iclass 29, count 0 2006.183.07:31:09.34#ibcon#end of sib2, iclass 29, count 0 2006.183.07:31:09.35#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:31:09.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:31:09.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:31:09.35#ibcon#*before write, iclass 29, count 0 2006.183.07:31:09.35#ibcon#enter sib2, iclass 29, count 0 2006.183.07:31:09.35#ibcon#flushed, iclass 29, count 0 2006.183.07:31:09.35#ibcon#about to write, iclass 29, count 0 2006.183.07:31:09.35#ibcon#wrote, iclass 29, count 0 2006.183.07:31:09.35#ibcon#about to read 3, iclass 29, count 0 2006.183.07:31:09.38#ibcon#read 3, iclass 29, count 0 2006.183.07:31:09.38#ibcon#about to read 4, iclass 29, count 0 2006.183.07:31:09.38#ibcon#read 4, iclass 29, count 0 2006.183.07:31:09.38#ibcon#about to read 5, iclass 29, count 0 2006.183.07:31:09.38#ibcon#read 5, iclass 29, count 0 2006.183.07:31:09.38#ibcon#about to read 6, iclass 29, count 0 2006.183.07:31:09.38#ibcon#read 6, iclass 29, count 0 2006.183.07:31:09.39#ibcon#end of sib2, iclass 29, count 0 2006.183.07:31:09.39#ibcon#*after write, iclass 29, count 0 2006.183.07:31:09.39#ibcon#*before return 0, iclass 29, count 0 2006.183.07:31:09.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:09.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:09.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:31:09.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:31:09.39$vc4f8/va=5,7 2006.183.07:31:09.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.07:31:09.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.07:31:09.39#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:09.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:09.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:09.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:09.44#ibcon#enter wrdev, iclass 31, count 2 2006.183.07:31:09.44#ibcon#first serial, iclass 31, count 2 2006.183.07:31:09.44#ibcon#enter sib2, iclass 31, count 2 2006.183.07:31:09.44#ibcon#flushed, iclass 31, count 2 2006.183.07:31:09.44#ibcon#about to write, iclass 31, count 2 2006.183.07:31:09.44#ibcon#wrote, iclass 31, count 2 2006.183.07:31:09.45#ibcon#about to read 3, iclass 31, count 2 2006.183.07:31:09.46#ibcon#read 3, iclass 31, count 2 2006.183.07:31:09.46#ibcon#about to read 4, iclass 31, count 2 2006.183.07:31:09.46#ibcon#read 4, iclass 31, count 2 2006.183.07:31:09.46#ibcon#about to read 5, iclass 31, count 2 2006.183.07:31:09.46#ibcon#read 5, iclass 31, count 2 2006.183.07:31:09.46#ibcon#about to read 6, iclass 31, count 2 2006.183.07:31:09.46#ibcon#read 6, iclass 31, count 2 2006.183.07:31:09.46#ibcon#end of sib2, iclass 31, count 2 2006.183.07:31:09.47#ibcon#*mode == 0, iclass 31, count 2 2006.183.07:31:09.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.07:31:09.47#ibcon#[25=AT05-07\r\n] 2006.183.07:31:09.47#ibcon#*before write, iclass 31, count 2 2006.183.07:31:09.47#ibcon#enter sib2, iclass 31, count 2 2006.183.07:31:09.47#ibcon#flushed, iclass 31, count 2 2006.183.07:31:09.47#ibcon#about to write, iclass 31, count 2 2006.183.07:31:09.47#ibcon#wrote, iclass 31, count 2 2006.183.07:31:09.47#ibcon#about to read 3, iclass 31, count 2 2006.183.07:31:09.49#ibcon#read 3, iclass 31, count 2 2006.183.07:31:09.49#ibcon#about to read 4, iclass 31, count 2 2006.183.07:31:09.49#ibcon#read 4, iclass 31, count 2 2006.183.07:31:09.49#ibcon#about to read 5, iclass 31, count 2 2006.183.07:31:09.49#ibcon#read 5, iclass 31, count 2 2006.183.07:31:09.50#ibcon#about to read 6, iclass 31, count 2 2006.183.07:31:09.50#ibcon#read 6, iclass 31, count 2 2006.183.07:31:09.50#ibcon#end of sib2, iclass 31, count 2 2006.183.07:31:09.50#ibcon#*after write, iclass 31, count 2 2006.183.07:31:09.50#ibcon#*before return 0, iclass 31, count 2 2006.183.07:31:09.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:09.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:09.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.07:31:09.50#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:09.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:09.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:09.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:09.61#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:31:09.61#ibcon#first serial, iclass 31, count 0 2006.183.07:31:09.61#ibcon#enter sib2, iclass 31, count 0 2006.183.07:31:09.61#ibcon#flushed, iclass 31, count 0 2006.183.07:31:09.61#ibcon#about to write, iclass 31, count 0 2006.183.07:31:09.61#ibcon#wrote, iclass 31, count 0 2006.183.07:31:09.62#ibcon#about to read 3, iclass 31, count 0 2006.183.07:31:09.63#ibcon#read 3, iclass 31, count 0 2006.183.07:31:09.63#ibcon#about to read 4, iclass 31, count 0 2006.183.07:31:09.63#ibcon#read 4, iclass 31, count 0 2006.183.07:31:09.63#ibcon#about to read 5, iclass 31, count 0 2006.183.07:31:09.63#ibcon#read 5, iclass 31, count 0 2006.183.07:31:09.63#ibcon#about to read 6, iclass 31, count 0 2006.183.07:31:09.63#ibcon#read 6, iclass 31, count 0 2006.183.07:31:09.63#ibcon#end of sib2, iclass 31, count 0 2006.183.07:31:09.64#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:31:09.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:31:09.64#ibcon#[25=USB\r\n] 2006.183.07:31:09.64#ibcon#*before write, iclass 31, count 0 2006.183.07:31:09.64#ibcon#enter sib2, iclass 31, count 0 2006.183.07:31:09.64#ibcon#flushed, iclass 31, count 0 2006.183.07:31:09.64#ibcon#about to write, iclass 31, count 0 2006.183.07:31:09.64#ibcon#wrote, iclass 31, count 0 2006.183.07:31:09.64#ibcon#about to read 3, iclass 31, count 0 2006.183.07:31:09.66#ibcon#read 3, iclass 31, count 0 2006.183.07:31:09.66#ibcon#about to read 4, iclass 31, count 0 2006.183.07:31:09.66#ibcon#read 4, iclass 31, count 0 2006.183.07:31:09.66#ibcon#about to read 5, iclass 31, count 0 2006.183.07:31:09.66#ibcon#read 5, iclass 31, count 0 2006.183.07:31:09.66#ibcon#about to read 6, iclass 31, count 0 2006.183.07:31:09.66#ibcon#read 6, iclass 31, count 0 2006.183.07:31:09.66#ibcon#end of sib2, iclass 31, count 0 2006.183.07:31:09.67#ibcon#*after write, iclass 31, count 0 2006.183.07:31:09.67#ibcon#*before return 0, iclass 31, count 0 2006.183.07:31:09.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:09.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:09.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:31:09.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:31:09.67$vc4f8/valo=6,772.99 2006.183.07:31:09.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.07:31:09.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.07:31:09.67#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:09.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:09.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:09.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:09.67#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:31:09.67#ibcon#first serial, iclass 33, count 0 2006.183.07:31:09.67#ibcon#enter sib2, iclass 33, count 0 2006.183.07:31:09.67#ibcon#flushed, iclass 33, count 0 2006.183.07:31:09.67#ibcon#about to write, iclass 33, count 0 2006.183.07:31:09.67#ibcon#wrote, iclass 33, count 0 2006.183.07:31:09.67#ibcon#about to read 3, iclass 33, count 0 2006.183.07:31:09.68#ibcon#read 3, iclass 33, count 0 2006.183.07:31:09.68#ibcon#about to read 4, iclass 33, count 0 2006.183.07:31:09.68#ibcon#read 4, iclass 33, count 0 2006.183.07:31:09.68#ibcon#about to read 5, iclass 33, count 0 2006.183.07:31:09.68#ibcon#read 5, iclass 33, count 0 2006.183.07:31:09.68#ibcon#about to read 6, iclass 33, count 0 2006.183.07:31:09.68#ibcon#read 6, iclass 33, count 0 2006.183.07:31:09.68#ibcon#end of sib2, iclass 33, count 0 2006.183.07:31:09.69#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:31:09.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:31:09.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:31:09.69#ibcon#*before write, iclass 33, count 0 2006.183.07:31:09.69#ibcon#enter sib2, iclass 33, count 0 2006.183.07:31:09.69#ibcon#flushed, iclass 33, count 0 2006.183.07:31:09.69#ibcon#about to write, iclass 33, count 0 2006.183.07:31:09.69#ibcon#wrote, iclass 33, count 0 2006.183.07:31:09.69#ibcon#about to read 3, iclass 33, count 0 2006.183.07:31:09.72#ibcon#read 3, iclass 33, count 0 2006.183.07:31:09.72#ibcon#about to read 4, iclass 33, count 0 2006.183.07:31:09.72#ibcon#read 4, iclass 33, count 0 2006.183.07:31:09.72#ibcon#about to read 5, iclass 33, count 0 2006.183.07:31:09.72#ibcon#read 5, iclass 33, count 0 2006.183.07:31:09.72#ibcon#about to read 6, iclass 33, count 0 2006.183.07:31:09.73#ibcon#read 6, iclass 33, count 0 2006.183.07:31:09.73#ibcon#end of sib2, iclass 33, count 0 2006.183.07:31:09.73#ibcon#*after write, iclass 33, count 0 2006.183.07:31:09.73#ibcon#*before return 0, iclass 33, count 0 2006.183.07:31:09.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:09.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:09.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:31:09.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:31:09.73$vc4f8/va=6,6 2006.183.07:31:09.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.183.07:31:09.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.183.07:31:09.73#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:09.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:31:09.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:31:09.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:31:09.79#ibcon#enter wrdev, iclass 35, count 2 2006.183.07:31:09.79#ibcon#first serial, iclass 35, count 2 2006.183.07:31:09.79#ibcon#enter sib2, iclass 35, count 2 2006.183.07:31:09.79#ibcon#flushed, iclass 35, count 2 2006.183.07:31:09.79#ibcon#about to write, iclass 35, count 2 2006.183.07:31:09.79#ibcon#wrote, iclass 35, count 2 2006.183.07:31:09.79#ibcon#about to read 3, iclass 35, count 2 2006.183.07:31:09.80#ibcon#read 3, iclass 35, count 2 2006.183.07:31:09.80#ibcon#about to read 4, iclass 35, count 2 2006.183.07:31:09.80#ibcon#read 4, iclass 35, count 2 2006.183.07:31:09.80#ibcon#about to read 5, iclass 35, count 2 2006.183.07:31:09.80#ibcon#read 5, iclass 35, count 2 2006.183.07:31:09.81#ibcon#about to read 6, iclass 35, count 2 2006.183.07:31:09.81#ibcon#read 6, iclass 35, count 2 2006.183.07:31:09.81#ibcon#end of sib2, iclass 35, count 2 2006.183.07:31:09.81#ibcon#*mode == 0, iclass 35, count 2 2006.183.07:31:09.81#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.183.07:31:09.81#ibcon#[25=AT06-06\r\n] 2006.183.07:31:09.81#ibcon#*before write, iclass 35, count 2 2006.183.07:31:09.81#ibcon#enter sib2, iclass 35, count 2 2006.183.07:31:09.81#ibcon#flushed, iclass 35, count 2 2006.183.07:31:09.81#ibcon#about to write, iclass 35, count 2 2006.183.07:31:09.81#ibcon#wrote, iclass 35, count 2 2006.183.07:31:09.81#ibcon#about to read 3, iclass 35, count 2 2006.183.07:31:09.83#ibcon#read 3, iclass 35, count 2 2006.183.07:31:09.83#ibcon#about to read 4, iclass 35, count 2 2006.183.07:31:09.83#ibcon#read 4, iclass 35, count 2 2006.183.07:31:09.83#ibcon#about to read 5, iclass 35, count 2 2006.183.07:31:09.83#ibcon#read 5, iclass 35, count 2 2006.183.07:31:09.84#ibcon#about to read 6, iclass 35, count 2 2006.183.07:31:09.84#ibcon#read 6, iclass 35, count 2 2006.183.07:31:09.84#ibcon#end of sib2, iclass 35, count 2 2006.183.07:31:09.84#ibcon#*after write, iclass 35, count 2 2006.183.07:31:09.84#ibcon#*before return 0, iclass 35, count 2 2006.183.07:31:09.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:31:09.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:31:09.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.183.07:31:09.84#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:09.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:31:09.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:31:09.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:31:09.95#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:31:09.95#ibcon#first serial, iclass 35, count 0 2006.183.07:31:09.95#ibcon#enter sib2, iclass 35, count 0 2006.183.07:31:09.95#ibcon#flushed, iclass 35, count 0 2006.183.07:31:09.95#ibcon#about to write, iclass 35, count 0 2006.183.07:31:09.95#ibcon#wrote, iclass 35, count 0 2006.183.07:31:09.96#ibcon#about to read 3, iclass 35, count 0 2006.183.07:31:09.97#ibcon#read 3, iclass 35, count 0 2006.183.07:31:09.97#ibcon#about to read 4, iclass 35, count 0 2006.183.07:31:09.97#ibcon#read 4, iclass 35, count 0 2006.183.07:31:09.97#ibcon#about to read 5, iclass 35, count 0 2006.183.07:31:09.97#ibcon#read 5, iclass 35, count 0 2006.183.07:31:09.97#ibcon#about to read 6, iclass 35, count 0 2006.183.07:31:09.97#ibcon#read 6, iclass 35, count 0 2006.183.07:31:09.97#ibcon#end of sib2, iclass 35, count 0 2006.183.07:31:09.98#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:31:09.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:31:09.98#ibcon#[25=USB\r\n] 2006.183.07:31:09.98#ibcon#*before write, iclass 35, count 0 2006.183.07:31:09.98#ibcon#enter sib2, iclass 35, count 0 2006.183.07:31:09.98#ibcon#flushed, iclass 35, count 0 2006.183.07:31:09.98#ibcon#about to write, iclass 35, count 0 2006.183.07:31:09.98#ibcon#wrote, iclass 35, count 0 2006.183.07:31:09.98#ibcon#about to read 3, iclass 35, count 0 2006.183.07:31:10.00#ibcon#read 3, iclass 35, count 0 2006.183.07:31:10.00#ibcon#about to read 4, iclass 35, count 0 2006.183.07:31:10.00#ibcon#read 4, iclass 35, count 0 2006.183.07:31:10.00#ibcon#about to read 5, iclass 35, count 0 2006.183.07:31:10.00#ibcon#read 5, iclass 35, count 0 2006.183.07:31:10.00#ibcon#about to read 6, iclass 35, count 0 2006.183.07:31:10.00#ibcon#read 6, iclass 35, count 0 2006.183.07:31:10.00#ibcon#end of sib2, iclass 35, count 0 2006.183.07:31:10.01#ibcon#*after write, iclass 35, count 0 2006.183.07:31:10.01#ibcon#*before return 0, iclass 35, count 0 2006.183.07:31:10.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:31:10.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:31:10.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:31:10.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:31:10.01$vc4f8/valo=7,832.99 2006.183.07:31:10.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.07:31:10.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.07:31:10.01#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:10.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:31:10.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:31:10.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:31:10.01#ibcon#enter wrdev, iclass 37, count 0 2006.183.07:31:10.01#ibcon#first serial, iclass 37, count 0 2006.183.07:31:10.01#ibcon#enter sib2, iclass 37, count 0 2006.183.07:31:10.01#ibcon#flushed, iclass 37, count 0 2006.183.07:31:10.01#ibcon#about to write, iclass 37, count 0 2006.183.07:31:10.01#ibcon#wrote, iclass 37, count 0 2006.183.07:31:10.01#ibcon#about to read 3, iclass 37, count 0 2006.183.07:31:10.02#ibcon#read 3, iclass 37, count 0 2006.183.07:31:10.02#ibcon#about to read 4, iclass 37, count 0 2006.183.07:31:10.02#ibcon#read 4, iclass 37, count 0 2006.183.07:31:10.02#ibcon#about to read 5, iclass 37, count 0 2006.183.07:31:10.02#ibcon#read 5, iclass 37, count 0 2006.183.07:31:10.02#ibcon#about to read 6, iclass 37, count 0 2006.183.07:31:10.02#ibcon#read 6, iclass 37, count 0 2006.183.07:31:10.02#ibcon#end of sib2, iclass 37, count 0 2006.183.07:31:10.03#ibcon#*mode == 0, iclass 37, count 0 2006.183.07:31:10.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.07:31:10.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:31:10.03#ibcon#*before write, iclass 37, count 0 2006.183.07:31:10.03#ibcon#enter sib2, iclass 37, count 0 2006.183.07:31:10.03#ibcon#flushed, iclass 37, count 0 2006.183.07:31:10.03#ibcon#about to write, iclass 37, count 0 2006.183.07:31:10.03#ibcon#wrote, iclass 37, count 0 2006.183.07:31:10.03#ibcon#about to read 3, iclass 37, count 0 2006.183.07:31:10.06#ibcon#read 3, iclass 37, count 0 2006.183.07:31:10.06#ibcon#about to read 4, iclass 37, count 0 2006.183.07:31:10.06#ibcon#read 4, iclass 37, count 0 2006.183.07:31:10.06#ibcon#about to read 5, iclass 37, count 0 2006.183.07:31:10.06#ibcon#read 5, iclass 37, count 0 2006.183.07:31:10.06#ibcon#about to read 6, iclass 37, count 0 2006.183.07:31:10.06#ibcon#read 6, iclass 37, count 0 2006.183.07:31:10.07#ibcon#end of sib2, iclass 37, count 0 2006.183.07:31:10.07#ibcon#*after write, iclass 37, count 0 2006.183.07:31:10.07#ibcon#*before return 0, iclass 37, count 0 2006.183.07:31:10.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:31:10.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:31:10.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.07:31:10.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.07:31:10.07$vc4f8/va=7,6 2006.183.07:31:10.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.07:31:10.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.07:31:10.07#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:10.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:31:10.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:31:10.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:31:10.12#ibcon#enter wrdev, iclass 39, count 2 2006.183.07:31:10.12#ibcon#first serial, iclass 39, count 2 2006.183.07:31:10.12#ibcon#enter sib2, iclass 39, count 2 2006.183.07:31:10.12#ibcon#flushed, iclass 39, count 2 2006.183.07:31:10.12#ibcon#about to write, iclass 39, count 2 2006.183.07:31:10.12#ibcon#wrote, iclass 39, count 2 2006.183.07:31:10.13#ibcon#about to read 3, iclass 39, count 2 2006.183.07:31:10.14#ibcon#read 3, iclass 39, count 2 2006.183.07:31:10.14#ibcon#about to read 4, iclass 39, count 2 2006.183.07:31:10.14#ibcon#read 4, iclass 39, count 2 2006.183.07:31:10.14#ibcon#about to read 5, iclass 39, count 2 2006.183.07:31:10.14#ibcon#read 5, iclass 39, count 2 2006.183.07:31:10.14#ibcon#about to read 6, iclass 39, count 2 2006.183.07:31:10.14#ibcon#read 6, iclass 39, count 2 2006.183.07:31:10.14#ibcon#end of sib2, iclass 39, count 2 2006.183.07:31:10.14#ibcon#*mode == 0, iclass 39, count 2 2006.183.07:31:10.15#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.07:31:10.15#ibcon#[25=AT07-06\r\n] 2006.183.07:31:10.15#ibcon#*before write, iclass 39, count 2 2006.183.07:31:10.15#ibcon#enter sib2, iclass 39, count 2 2006.183.07:31:10.15#ibcon#flushed, iclass 39, count 2 2006.183.07:31:10.15#ibcon#about to write, iclass 39, count 2 2006.183.07:31:10.15#ibcon#wrote, iclass 39, count 2 2006.183.07:31:10.15#ibcon#about to read 3, iclass 39, count 2 2006.183.07:31:10.17#ibcon#read 3, iclass 39, count 2 2006.183.07:31:10.17#ibcon#about to read 4, iclass 39, count 2 2006.183.07:31:10.17#ibcon#read 4, iclass 39, count 2 2006.183.07:31:10.17#ibcon#about to read 5, iclass 39, count 2 2006.183.07:31:10.17#ibcon#read 5, iclass 39, count 2 2006.183.07:31:10.18#ibcon#about to read 6, iclass 39, count 2 2006.183.07:31:10.18#ibcon#read 6, iclass 39, count 2 2006.183.07:31:10.18#ibcon#end of sib2, iclass 39, count 2 2006.183.07:31:10.18#ibcon#*after write, iclass 39, count 2 2006.183.07:31:10.18#ibcon#*before return 0, iclass 39, count 2 2006.183.07:31:10.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:31:10.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:31:10.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.07:31:10.18#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:10.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:31:10.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:31:10.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:31:10.29#ibcon#enter wrdev, iclass 39, count 0 2006.183.07:31:10.29#ibcon#first serial, iclass 39, count 0 2006.183.07:31:10.29#ibcon#enter sib2, iclass 39, count 0 2006.183.07:31:10.29#ibcon#flushed, iclass 39, count 0 2006.183.07:31:10.29#ibcon#about to write, iclass 39, count 0 2006.183.07:31:10.29#ibcon#wrote, iclass 39, count 0 2006.183.07:31:10.30#ibcon#about to read 3, iclass 39, count 0 2006.183.07:31:10.31#ibcon#read 3, iclass 39, count 0 2006.183.07:31:10.31#ibcon#about to read 4, iclass 39, count 0 2006.183.07:31:10.31#ibcon#read 4, iclass 39, count 0 2006.183.07:31:10.31#ibcon#about to read 5, iclass 39, count 0 2006.183.07:31:10.31#ibcon#read 5, iclass 39, count 0 2006.183.07:31:10.31#ibcon#about to read 6, iclass 39, count 0 2006.183.07:31:10.31#ibcon#read 6, iclass 39, count 0 2006.183.07:31:10.31#ibcon#end of sib2, iclass 39, count 0 2006.183.07:31:10.32#ibcon#*mode == 0, iclass 39, count 0 2006.183.07:31:10.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.07:31:10.32#ibcon#[25=USB\r\n] 2006.183.07:31:10.32#ibcon#*before write, iclass 39, count 0 2006.183.07:31:10.32#ibcon#enter sib2, iclass 39, count 0 2006.183.07:31:10.32#ibcon#flushed, iclass 39, count 0 2006.183.07:31:10.32#ibcon#about to write, iclass 39, count 0 2006.183.07:31:10.32#ibcon#wrote, iclass 39, count 0 2006.183.07:31:10.32#ibcon#about to read 3, iclass 39, count 0 2006.183.07:31:10.34#ibcon#read 3, iclass 39, count 0 2006.183.07:31:10.34#ibcon#about to read 4, iclass 39, count 0 2006.183.07:31:10.34#ibcon#read 4, iclass 39, count 0 2006.183.07:31:10.34#ibcon#about to read 5, iclass 39, count 0 2006.183.07:31:10.34#ibcon#read 5, iclass 39, count 0 2006.183.07:31:10.34#ibcon#about to read 6, iclass 39, count 0 2006.183.07:31:10.34#ibcon#read 6, iclass 39, count 0 2006.183.07:31:10.34#ibcon#end of sib2, iclass 39, count 0 2006.183.07:31:10.35#ibcon#*after write, iclass 39, count 0 2006.183.07:31:10.35#ibcon#*before return 0, iclass 39, count 0 2006.183.07:31:10.35#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:31:10.35#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:31:10.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.07:31:10.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.07:31:10.35$vc4f8/valo=8,852.99 2006.183.07:31:10.35#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.07:31:10.35#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.07:31:10.35#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:10.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:31:10.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:31:10.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:31:10.35#ibcon#enter wrdev, iclass 3, count 0 2006.183.07:31:10.35#ibcon#first serial, iclass 3, count 0 2006.183.07:31:10.35#ibcon#enter sib2, iclass 3, count 0 2006.183.07:31:10.35#ibcon#flushed, iclass 3, count 0 2006.183.07:31:10.35#ibcon#about to write, iclass 3, count 0 2006.183.07:31:10.35#ibcon#wrote, iclass 3, count 0 2006.183.07:31:10.35#ibcon#about to read 3, iclass 3, count 0 2006.183.07:31:10.36#ibcon#read 3, iclass 3, count 0 2006.183.07:31:10.36#ibcon#about to read 4, iclass 3, count 0 2006.183.07:31:10.36#ibcon#read 4, iclass 3, count 0 2006.183.07:31:10.36#ibcon#about to read 5, iclass 3, count 0 2006.183.07:31:10.36#ibcon#read 5, iclass 3, count 0 2006.183.07:31:10.36#ibcon#about to read 6, iclass 3, count 0 2006.183.07:31:10.36#ibcon#read 6, iclass 3, count 0 2006.183.07:31:10.36#ibcon#end of sib2, iclass 3, count 0 2006.183.07:31:10.37#ibcon#*mode == 0, iclass 3, count 0 2006.183.07:31:10.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.07:31:10.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:31:10.37#ibcon#*before write, iclass 3, count 0 2006.183.07:31:10.37#ibcon#enter sib2, iclass 3, count 0 2006.183.07:31:10.37#ibcon#flushed, iclass 3, count 0 2006.183.07:31:10.37#ibcon#about to write, iclass 3, count 0 2006.183.07:31:10.37#ibcon#wrote, iclass 3, count 0 2006.183.07:31:10.37#ibcon#about to read 3, iclass 3, count 0 2006.183.07:31:10.40#ibcon#read 3, iclass 3, count 0 2006.183.07:31:10.40#ibcon#about to read 4, iclass 3, count 0 2006.183.07:31:10.40#ibcon#read 4, iclass 3, count 0 2006.183.07:31:10.40#ibcon#about to read 5, iclass 3, count 0 2006.183.07:31:10.40#ibcon#read 5, iclass 3, count 0 2006.183.07:31:10.40#ibcon#about to read 6, iclass 3, count 0 2006.183.07:31:10.40#ibcon#read 6, iclass 3, count 0 2006.183.07:31:10.40#ibcon#end of sib2, iclass 3, count 0 2006.183.07:31:10.41#ibcon#*after write, iclass 3, count 0 2006.183.07:31:10.41#ibcon#*before return 0, iclass 3, count 0 2006.183.07:31:10.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:31:10.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:31:10.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.07:31:10.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.07:31:10.41$vc4f8/va=8,7 2006.183.07:31:10.41#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.07:31:10.41#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.07:31:10.41#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:10.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:31:10.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:31:10.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:31:10.46#ibcon#enter wrdev, iclass 5, count 2 2006.183.07:31:10.46#ibcon#first serial, iclass 5, count 2 2006.183.07:31:10.46#ibcon#enter sib2, iclass 5, count 2 2006.183.07:31:10.46#ibcon#flushed, iclass 5, count 2 2006.183.07:31:10.46#ibcon#about to write, iclass 5, count 2 2006.183.07:31:10.46#ibcon#wrote, iclass 5, count 2 2006.183.07:31:10.47#ibcon#about to read 3, iclass 5, count 2 2006.183.07:31:10.48#ibcon#read 3, iclass 5, count 2 2006.183.07:31:10.48#ibcon#about to read 4, iclass 5, count 2 2006.183.07:31:10.48#ibcon#read 4, iclass 5, count 2 2006.183.07:31:10.48#ibcon#about to read 5, iclass 5, count 2 2006.183.07:31:10.48#ibcon#read 5, iclass 5, count 2 2006.183.07:31:10.48#ibcon#about to read 6, iclass 5, count 2 2006.183.07:31:10.48#ibcon#read 6, iclass 5, count 2 2006.183.07:31:10.49#ibcon#end of sib2, iclass 5, count 2 2006.183.07:31:10.49#ibcon#*mode == 0, iclass 5, count 2 2006.183.07:31:10.49#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.07:31:10.49#ibcon#[25=AT08-07\r\n] 2006.183.07:31:10.49#ibcon#*before write, iclass 5, count 2 2006.183.07:31:10.49#ibcon#enter sib2, iclass 5, count 2 2006.183.07:31:10.49#ibcon#flushed, iclass 5, count 2 2006.183.07:31:10.49#ibcon#about to write, iclass 5, count 2 2006.183.07:31:10.49#ibcon#wrote, iclass 5, count 2 2006.183.07:31:10.49#ibcon#about to read 3, iclass 5, count 2 2006.183.07:31:10.51#ibcon#read 3, iclass 5, count 2 2006.183.07:31:10.51#ibcon#about to read 4, iclass 5, count 2 2006.183.07:31:10.51#ibcon#read 4, iclass 5, count 2 2006.183.07:31:10.51#ibcon#about to read 5, iclass 5, count 2 2006.183.07:31:10.51#ibcon#read 5, iclass 5, count 2 2006.183.07:31:10.52#ibcon#about to read 6, iclass 5, count 2 2006.183.07:31:10.52#ibcon#read 6, iclass 5, count 2 2006.183.07:31:10.52#ibcon#end of sib2, iclass 5, count 2 2006.183.07:31:10.52#ibcon#*after write, iclass 5, count 2 2006.183.07:31:10.52#ibcon#*before return 0, iclass 5, count 2 2006.183.07:31:10.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:31:10.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:31:10.52#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.07:31:10.52#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:10.52#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:31:10.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:31:10.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:31:10.63#ibcon#enter wrdev, iclass 5, count 0 2006.183.07:31:10.63#ibcon#first serial, iclass 5, count 0 2006.183.07:31:10.63#ibcon#enter sib2, iclass 5, count 0 2006.183.07:31:10.63#ibcon#flushed, iclass 5, count 0 2006.183.07:31:10.63#ibcon#about to write, iclass 5, count 0 2006.183.07:31:10.63#ibcon#wrote, iclass 5, count 0 2006.183.07:31:10.64#ibcon#about to read 3, iclass 5, count 0 2006.183.07:31:10.65#ibcon#read 3, iclass 5, count 0 2006.183.07:31:10.65#ibcon#about to read 4, iclass 5, count 0 2006.183.07:31:10.65#ibcon#read 4, iclass 5, count 0 2006.183.07:31:10.65#ibcon#about to read 5, iclass 5, count 0 2006.183.07:31:10.65#ibcon#read 5, iclass 5, count 0 2006.183.07:31:10.65#ibcon#about to read 6, iclass 5, count 0 2006.183.07:31:10.65#ibcon#read 6, iclass 5, count 0 2006.183.07:31:10.65#ibcon#end of sib2, iclass 5, count 0 2006.183.07:31:10.66#ibcon#*mode == 0, iclass 5, count 0 2006.183.07:31:10.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.07:31:10.66#ibcon#[25=USB\r\n] 2006.183.07:31:10.66#ibcon#*before write, iclass 5, count 0 2006.183.07:31:10.66#ibcon#enter sib2, iclass 5, count 0 2006.183.07:31:10.66#ibcon#flushed, iclass 5, count 0 2006.183.07:31:10.66#ibcon#about to write, iclass 5, count 0 2006.183.07:31:10.66#ibcon#wrote, iclass 5, count 0 2006.183.07:31:10.66#ibcon#about to read 3, iclass 5, count 0 2006.183.07:31:10.68#ibcon#read 3, iclass 5, count 0 2006.183.07:31:10.68#ibcon#about to read 4, iclass 5, count 0 2006.183.07:31:10.68#ibcon#read 4, iclass 5, count 0 2006.183.07:31:10.68#ibcon#about to read 5, iclass 5, count 0 2006.183.07:31:10.68#ibcon#read 5, iclass 5, count 0 2006.183.07:31:10.68#ibcon#about to read 6, iclass 5, count 0 2006.183.07:31:10.68#ibcon#read 6, iclass 5, count 0 2006.183.07:31:10.68#ibcon#end of sib2, iclass 5, count 0 2006.183.07:31:10.69#ibcon#*after write, iclass 5, count 0 2006.183.07:31:10.69#ibcon#*before return 0, iclass 5, count 0 2006.183.07:31:10.69#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:31:10.69#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:31:10.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.07:31:10.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.07:31:10.69$vc4f8/vblo=1,632.99 2006.183.07:31:10.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.07:31:10.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.07:31:10.69#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:10.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:31:10.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:31:10.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:31:10.69#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:31:10.69#ibcon#first serial, iclass 7, count 0 2006.183.07:31:10.69#ibcon#enter sib2, iclass 7, count 0 2006.183.07:31:10.69#ibcon#flushed, iclass 7, count 0 2006.183.07:31:10.69#ibcon#about to write, iclass 7, count 0 2006.183.07:31:10.69#ibcon#wrote, iclass 7, count 0 2006.183.07:31:10.69#ibcon#about to read 3, iclass 7, count 0 2006.183.07:31:10.70#ibcon#read 3, iclass 7, count 0 2006.183.07:31:10.70#ibcon#about to read 4, iclass 7, count 0 2006.183.07:31:10.70#ibcon#read 4, iclass 7, count 0 2006.183.07:31:10.70#ibcon#about to read 5, iclass 7, count 0 2006.183.07:31:10.70#ibcon#read 5, iclass 7, count 0 2006.183.07:31:10.70#ibcon#about to read 6, iclass 7, count 0 2006.183.07:31:10.70#ibcon#read 6, iclass 7, count 0 2006.183.07:31:10.70#ibcon#end of sib2, iclass 7, count 0 2006.183.07:31:10.71#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:31:10.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:31:10.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:31:10.71#ibcon#*before write, iclass 7, count 0 2006.183.07:31:10.71#ibcon#enter sib2, iclass 7, count 0 2006.183.07:31:10.71#ibcon#flushed, iclass 7, count 0 2006.183.07:31:10.71#ibcon#about to write, iclass 7, count 0 2006.183.07:31:10.71#ibcon#wrote, iclass 7, count 0 2006.183.07:31:10.71#ibcon#about to read 3, iclass 7, count 0 2006.183.07:31:10.74#ibcon#read 3, iclass 7, count 0 2006.183.07:31:10.74#ibcon#about to read 4, iclass 7, count 0 2006.183.07:31:10.74#ibcon#read 4, iclass 7, count 0 2006.183.07:31:10.74#ibcon#about to read 5, iclass 7, count 0 2006.183.07:31:10.74#ibcon#read 5, iclass 7, count 0 2006.183.07:31:10.74#ibcon#about to read 6, iclass 7, count 0 2006.183.07:31:10.74#ibcon#read 6, iclass 7, count 0 2006.183.07:31:10.74#ibcon#end of sib2, iclass 7, count 0 2006.183.07:31:10.75#ibcon#*after write, iclass 7, count 0 2006.183.07:31:10.75#ibcon#*before return 0, iclass 7, count 0 2006.183.07:31:10.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:31:10.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:31:10.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:31:10.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:31:10.75$vc4f8/vb=1,4 2006.183.07:31:10.75#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.07:31:10.75#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.07:31:10.75#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:10.75#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:31:10.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:31:10.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:31:10.75#ibcon#enter wrdev, iclass 11, count 2 2006.183.07:31:10.75#ibcon#first serial, iclass 11, count 2 2006.183.07:31:10.75#ibcon#enter sib2, iclass 11, count 2 2006.183.07:31:10.75#ibcon#flushed, iclass 11, count 2 2006.183.07:31:10.75#ibcon#about to write, iclass 11, count 2 2006.183.07:31:10.75#ibcon#wrote, iclass 11, count 2 2006.183.07:31:10.75#ibcon#about to read 3, iclass 11, count 2 2006.183.07:31:10.76#ibcon#read 3, iclass 11, count 2 2006.183.07:31:10.76#ibcon#about to read 4, iclass 11, count 2 2006.183.07:31:10.76#ibcon#read 4, iclass 11, count 2 2006.183.07:31:10.76#ibcon#about to read 5, iclass 11, count 2 2006.183.07:31:10.76#ibcon#read 5, iclass 11, count 2 2006.183.07:31:10.76#ibcon#about to read 6, iclass 11, count 2 2006.183.07:31:10.76#ibcon#read 6, iclass 11, count 2 2006.183.07:31:10.76#ibcon#end of sib2, iclass 11, count 2 2006.183.07:31:10.77#ibcon#*mode == 0, iclass 11, count 2 2006.183.07:31:10.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.07:31:10.77#ibcon#[27=AT01-04\r\n] 2006.183.07:31:10.77#ibcon#*before write, iclass 11, count 2 2006.183.07:31:10.77#ibcon#enter sib2, iclass 11, count 2 2006.183.07:31:10.77#ibcon#flushed, iclass 11, count 2 2006.183.07:31:10.77#ibcon#about to write, iclass 11, count 2 2006.183.07:31:10.77#ibcon#wrote, iclass 11, count 2 2006.183.07:31:10.77#ibcon#about to read 3, iclass 11, count 2 2006.183.07:31:10.80#ibcon#read 3, iclass 11, count 2 2006.183.07:31:10.80#ibcon#about to read 4, iclass 11, count 2 2006.183.07:31:10.80#ibcon#read 4, iclass 11, count 2 2006.183.07:31:10.80#ibcon#about to read 5, iclass 11, count 2 2006.183.07:31:10.80#ibcon#read 5, iclass 11, count 2 2006.183.07:31:10.80#ibcon#about to read 6, iclass 11, count 2 2006.183.07:31:10.80#ibcon#read 6, iclass 11, count 2 2006.183.07:31:10.80#ibcon#end of sib2, iclass 11, count 2 2006.183.07:31:10.80#ibcon#*after write, iclass 11, count 2 2006.183.07:31:10.80#ibcon#*before return 0, iclass 11, count 2 2006.183.07:31:10.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:31:10.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:31:10.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.07:31:10.80#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:10.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:31:10.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:31:10.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:31:10.91#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:31:10.91#ibcon#first serial, iclass 11, count 0 2006.183.07:31:10.91#ibcon#enter sib2, iclass 11, count 0 2006.183.07:31:10.91#ibcon#flushed, iclass 11, count 0 2006.183.07:31:10.91#ibcon#about to write, iclass 11, count 0 2006.183.07:31:10.92#ibcon#wrote, iclass 11, count 0 2006.183.07:31:10.92#ibcon#about to read 3, iclass 11, count 0 2006.183.07:31:10.93#ibcon#read 3, iclass 11, count 0 2006.183.07:31:10.93#ibcon#about to read 4, iclass 11, count 0 2006.183.07:31:10.93#ibcon#read 4, iclass 11, count 0 2006.183.07:31:10.93#ibcon#about to read 5, iclass 11, count 0 2006.183.07:31:10.93#ibcon#read 5, iclass 11, count 0 2006.183.07:31:10.93#ibcon#about to read 6, iclass 11, count 0 2006.183.07:31:10.94#ibcon#read 6, iclass 11, count 0 2006.183.07:31:10.94#ibcon#end of sib2, iclass 11, count 0 2006.183.07:31:10.94#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:31:10.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:31:10.94#ibcon#[27=USB\r\n] 2006.183.07:31:10.94#ibcon#*before write, iclass 11, count 0 2006.183.07:31:10.94#ibcon#enter sib2, iclass 11, count 0 2006.183.07:31:10.94#ibcon#flushed, iclass 11, count 0 2006.183.07:31:10.94#ibcon#about to write, iclass 11, count 0 2006.183.07:31:10.94#ibcon#wrote, iclass 11, count 0 2006.183.07:31:10.94#ibcon#about to read 3, iclass 11, count 0 2006.183.07:31:10.96#ibcon#read 3, iclass 11, count 0 2006.183.07:31:10.96#ibcon#about to read 4, iclass 11, count 0 2006.183.07:31:10.96#ibcon#read 4, iclass 11, count 0 2006.183.07:31:10.96#ibcon#about to read 5, iclass 11, count 0 2006.183.07:31:10.96#ibcon#read 5, iclass 11, count 0 2006.183.07:31:10.96#ibcon#about to read 6, iclass 11, count 0 2006.183.07:31:10.96#ibcon#read 6, iclass 11, count 0 2006.183.07:31:10.96#ibcon#end of sib2, iclass 11, count 0 2006.183.07:31:10.97#ibcon#*after write, iclass 11, count 0 2006.183.07:31:10.97#ibcon#*before return 0, iclass 11, count 0 2006.183.07:31:10.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:31:10.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:31:10.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:31:10.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:31:10.97$vc4f8/vblo=2,640.99 2006.183.07:31:10.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:31:10.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:31:10.97#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:10.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:10.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:10.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:10.97#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:31:10.97#ibcon#first serial, iclass 13, count 0 2006.183.07:31:10.97#ibcon#enter sib2, iclass 13, count 0 2006.183.07:31:10.97#ibcon#flushed, iclass 13, count 0 2006.183.07:31:10.97#ibcon#about to write, iclass 13, count 0 2006.183.07:31:10.97#ibcon#wrote, iclass 13, count 0 2006.183.07:31:10.97#ibcon#about to read 3, iclass 13, count 0 2006.183.07:31:10.98#ibcon#read 3, iclass 13, count 0 2006.183.07:31:10.98#ibcon#about to read 4, iclass 13, count 0 2006.183.07:31:10.98#ibcon#read 4, iclass 13, count 0 2006.183.07:31:10.98#ibcon#about to read 5, iclass 13, count 0 2006.183.07:31:10.98#ibcon#read 5, iclass 13, count 0 2006.183.07:31:10.98#ibcon#about to read 6, iclass 13, count 0 2006.183.07:31:10.98#ibcon#read 6, iclass 13, count 0 2006.183.07:31:10.98#ibcon#end of sib2, iclass 13, count 0 2006.183.07:31:10.99#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:31:10.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:31:10.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:31:10.99#ibcon#*before write, iclass 13, count 0 2006.183.07:31:10.99#ibcon#enter sib2, iclass 13, count 0 2006.183.07:31:10.99#ibcon#flushed, iclass 13, count 0 2006.183.07:31:10.99#ibcon#about to write, iclass 13, count 0 2006.183.07:31:10.99#ibcon#wrote, iclass 13, count 0 2006.183.07:31:10.99#ibcon#about to read 3, iclass 13, count 0 2006.183.07:31:11.03#ibcon#read 3, iclass 13, count 0 2006.183.07:31:11.03#ibcon#about to read 4, iclass 13, count 0 2006.183.07:31:11.03#ibcon#read 4, iclass 13, count 0 2006.183.07:31:11.03#ibcon#about to read 5, iclass 13, count 0 2006.183.07:31:11.03#ibcon#read 5, iclass 13, count 0 2006.183.07:31:11.03#ibcon#about to read 6, iclass 13, count 0 2006.183.07:31:11.03#ibcon#read 6, iclass 13, count 0 2006.183.07:31:11.03#ibcon#end of sib2, iclass 13, count 0 2006.183.07:31:11.03#ibcon#*after write, iclass 13, count 0 2006.183.07:31:11.03#ibcon#*before return 0, iclass 13, count 0 2006.183.07:31:11.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:11.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:31:11.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:31:11.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:31:11.03$vc4f8/vb=2,4 2006.183.07:31:11.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:31:11.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:31:11.03#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:11.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:11.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:11.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:11.08#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:31:11.08#ibcon#first serial, iclass 15, count 2 2006.183.07:31:11.08#ibcon#enter sib2, iclass 15, count 2 2006.183.07:31:11.08#ibcon#flushed, iclass 15, count 2 2006.183.07:31:11.08#ibcon#about to write, iclass 15, count 2 2006.183.07:31:11.08#ibcon#wrote, iclass 15, count 2 2006.183.07:31:11.09#ibcon#about to read 3, iclass 15, count 2 2006.183.07:31:11.10#ibcon#read 3, iclass 15, count 2 2006.183.07:31:11.10#ibcon#about to read 4, iclass 15, count 2 2006.183.07:31:11.10#ibcon#read 4, iclass 15, count 2 2006.183.07:31:11.10#ibcon#about to read 5, iclass 15, count 2 2006.183.07:31:11.10#ibcon#read 5, iclass 15, count 2 2006.183.07:31:11.10#ibcon#about to read 6, iclass 15, count 2 2006.183.07:31:11.10#ibcon#read 6, iclass 15, count 2 2006.183.07:31:11.10#ibcon#end of sib2, iclass 15, count 2 2006.183.07:31:11.11#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:31:11.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:31:11.11#ibcon#[27=AT02-04\r\n] 2006.183.07:31:11.11#ibcon#*before write, iclass 15, count 2 2006.183.07:31:11.11#ibcon#enter sib2, iclass 15, count 2 2006.183.07:31:11.11#ibcon#flushed, iclass 15, count 2 2006.183.07:31:11.11#ibcon#about to write, iclass 15, count 2 2006.183.07:31:11.11#ibcon#wrote, iclass 15, count 2 2006.183.07:31:11.11#ibcon#about to read 3, iclass 15, count 2 2006.183.07:31:11.13#ibcon#read 3, iclass 15, count 2 2006.183.07:31:11.13#ibcon#about to read 4, iclass 15, count 2 2006.183.07:31:11.13#ibcon#read 4, iclass 15, count 2 2006.183.07:31:11.13#ibcon#about to read 5, iclass 15, count 2 2006.183.07:31:11.13#ibcon#read 5, iclass 15, count 2 2006.183.07:31:11.14#ibcon#about to read 6, iclass 15, count 2 2006.183.07:31:11.14#ibcon#read 6, iclass 15, count 2 2006.183.07:31:11.14#ibcon#end of sib2, iclass 15, count 2 2006.183.07:31:11.14#ibcon#*after write, iclass 15, count 2 2006.183.07:31:11.14#ibcon#*before return 0, iclass 15, count 2 2006.183.07:31:11.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:11.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:31:11.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:31:11.14#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:11.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:11.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:11.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:11.25#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:31:11.25#ibcon#first serial, iclass 15, count 0 2006.183.07:31:11.25#ibcon#enter sib2, iclass 15, count 0 2006.183.07:31:11.25#ibcon#flushed, iclass 15, count 0 2006.183.07:31:11.25#ibcon#about to write, iclass 15, count 0 2006.183.07:31:11.25#ibcon#wrote, iclass 15, count 0 2006.183.07:31:11.26#ibcon#about to read 3, iclass 15, count 0 2006.183.07:31:11.27#ibcon#read 3, iclass 15, count 0 2006.183.07:31:11.27#ibcon#about to read 4, iclass 15, count 0 2006.183.07:31:11.27#ibcon#read 4, iclass 15, count 0 2006.183.07:31:11.27#ibcon#about to read 5, iclass 15, count 0 2006.183.07:31:11.27#ibcon#read 5, iclass 15, count 0 2006.183.07:31:11.27#ibcon#about to read 6, iclass 15, count 0 2006.183.07:31:11.27#ibcon#read 6, iclass 15, count 0 2006.183.07:31:11.27#ibcon#end of sib2, iclass 15, count 0 2006.183.07:31:11.28#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:31:11.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:31:11.28#ibcon#[27=USB\r\n] 2006.183.07:31:11.28#ibcon#*before write, iclass 15, count 0 2006.183.07:31:11.28#ibcon#enter sib2, iclass 15, count 0 2006.183.07:31:11.28#ibcon#flushed, iclass 15, count 0 2006.183.07:31:11.28#ibcon#about to write, iclass 15, count 0 2006.183.07:31:11.28#ibcon#wrote, iclass 15, count 0 2006.183.07:31:11.28#ibcon#about to read 3, iclass 15, count 0 2006.183.07:31:11.30#ibcon#read 3, iclass 15, count 0 2006.183.07:31:11.30#ibcon#about to read 4, iclass 15, count 0 2006.183.07:31:11.30#ibcon#read 4, iclass 15, count 0 2006.183.07:31:11.30#ibcon#about to read 5, iclass 15, count 0 2006.183.07:31:11.30#ibcon#read 5, iclass 15, count 0 2006.183.07:31:11.30#ibcon#about to read 6, iclass 15, count 0 2006.183.07:31:11.30#ibcon#read 6, iclass 15, count 0 2006.183.07:31:11.30#ibcon#end of sib2, iclass 15, count 0 2006.183.07:31:11.31#ibcon#*after write, iclass 15, count 0 2006.183.07:31:11.31#ibcon#*before return 0, iclass 15, count 0 2006.183.07:31:11.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:11.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:31:11.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:31:11.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:31:11.31$vc4f8/vblo=3,656.99 2006.183.07:31:11.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:31:11.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:31:11.31#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:11.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:11.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:11.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:11.31#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:31:11.31#ibcon#first serial, iclass 17, count 0 2006.183.07:31:11.31#ibcon#enter sib2, iclass 17, count 0 2006.183.07:31:11.31#ibcon#flushed, iclass 17, count 0 2006.183.07:31:11.31#ibcon#about to write, iclass 17, count 0 2006.183.07:31:11.31#ibcon#wrote, iclass 17, count 0 2006.183.07:31:11.31#ibcon#about to read 3, iclass 17, count 0 2006.183.07:31:11.32#ibcon#read 3, iclass 17, count 0 2006.183.07:31:11.32#ibcon#about to read 4, iclass 17, count 0 2006.183.07:31:11.32#ibcon#read 4, iclass 17, count 0 2006.183.07:31:11.32#ibcon#about to read 5, iclass 17, count 0 2006.183.07:31:11.32#ibcon#read 5, iclass 17, count 0 2006.183.07:31:11.32#ibcon#about to read 6, iclass 17, count 0 2006.183.07:31:11.32#ibcon#read 6, iclass 17, count 0 2006.183.07:31:11.32#ibcon#end of sib2, iclass 17, count 0 2006.183.07:31:11.33#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:31:11.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:31:11.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:31:11.33#ibcon#*before write, iclass 17, count 0 2006.183.07:31:11.33#ibcon#enter sib2, iclass 17, count 0 2006.183.07:31:11.33#ibcon#flushed, iclass 17, count 0 2006.183.07:31:11.33#ibcon#about to write, iclass 17, count 0 2006.183.07:31:11.33#ibcon#wrote, iclass 17, count 0 2006.183.07:31:11.33#ibcon#about to read 3, iclass 17, count 0 2006.183.07:31:11.36#ibcon#read 3, iclass 17, count 0 2006.183.07:31:11.36#ibcon#about to read 4, iclass 17, count 0 2006.183.07:31:11.36#ibcon#read 4, iclass 17, count 0 2006.183.07:31:11.36#ibcon#about to read 5, iclass 17, count 0 2006.183.07:31:11.36#ibcon#read 5, iclass 17, count 0 2006.183.07:31:11.36#ibcon#about to read 6, iclass 17, count 0 2006.183.07:31:11.36#ibcon#read 6, iclass 17, count 0 2006.183.07:31:11.36#ibcon#end of sib2, iclass 17, count 0 2006.183.07:31:11.37#ibcon#*after write, iclass 17, count 0 2006.183.07:31:11.37#ibcon#*before return 0, iclass 17, count 0 2006.183.07:31:11.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:11.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:31:11.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:31:11.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:31:11.37$vc4f8/vb=3,4 2006.183.07:31:11.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:31:11.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:31:11.37#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:11.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:11.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:11.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:11.42#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:31:11.42#ibcon#first serial, iclass 19, count 2 2006.183.07:31:11.42#ibcon#enter sib2, iclass 19, count 2 2006.183.07:31:11.42#ibcon#flushed, iclass 19, count 2 2006.183.07:31:11.42#ibcon#about to write, iclass 19, count 2 2006.183.07:31:11.42#ibcon#wrote, iclass 19, count 2 2006.183.07:31:11.43#ibcon#about to read 3, iclass 19, count 2 2006.183.07:31:11.44#ibcon#read 3, iclass 19, count 2 2006.183.07:31:11.44#ibcon#about to read 4, iclass 19, count 2 2006.183.07:31:11.44#ibcon#read 4, iclass 19, count 2 2006.183.07:31:11.44#ibcon#about to read 5, iclass 19, count 2 2006.183.07:31:11.44#ibcon#read 5, iclass 19, count 2 2006.183.07:31:11.44#ibcon#about to read 6, iclass 19, count 2 2006.183.07:31:11.44#ibcon#read 6, iclass 19, count 2 2006.183.07:31:11.45#ibcon#end of sib2, iclass 19, count 2 2006.183.07:31:11.45#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:31:11.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:31:11.45#ibcon#[27=AT03-04\r\n] 2006.183.07:31:11.45#ibcon#*before write, iclass 19, count 2 2006.183.07:31:11.45#ibcon#enter sib2, iclass 19, count 2 2006.183.07:31:11.45#ibcon#flushed, iclass 19, count 2 2006.183.07:31:11.45#ibcon#about to write, iclass 19, count 2 2006.183.07:31:11.45#ibcon#wrote, iclass 19, count 2 2006.183.07:31:11.45#ibcon#about to read 3, iclass 19, count 2 2006.183.07:31:11.47#ibcon#read 3, iclass 19, count 2 2006.183.07:31:11.47#ibcon#about to read 4, iclass 19, count 2 2006.183.07:31:11.47#ibcon#read 4, iclass 19, count 2 2006.183.07:31:11.47#ibcon#about to read 5, iclass 19, count 2 2006.183.07:31:11.47#ibcon#read 5, iclass 19, count 2 2006.183.07:31:11.47#ibcon#about to read 6, iclass 19, count 2 2006.183.07:31:11.48#ibcon#read 6, iclass 19, count 2 2006.183.07:31:11.48#ibcon#end of sib2, iclass 19, count 2 2006.183.07:31:11.48#ibcon#*after write, iclass 19, count 2 2006.183.07:31:11.48#ibcon#*before return 0, iclass 19, count 2 2006.183.07:31:11.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:11.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:31:11.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:31:11.48#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:11.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:11.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:11.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:11.59#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:31:11.59#ibcon#first serial, iclass 19, count 0 2006.183.07:31:11.59#ibcon#enter sib2, iclass 19, count 0 2006.183.07:31:11.59#ibcon#flushed, iclass 19, count 0 2006.183.07:31:11.59#ibcon#about to write, iclass 19, count 0 2006.183.07:31:11.59#ibcon#wrote, iclass 19, count 0 2006.183.07:31:11.59#ibcon#about to read 3, iclass 19, count 0 2006.183.07:31:11.61#ibcon#read 3, iclass 19, count 0 2006.183.07:31:11.61#ibcon#about to read 4, iclass 19, count 0 2006.183.07:31:11.61#ibcon#read 4, iclass 19, count 0 2006.183.07:31:11.61#ibcon#about to read 5, iclass 19, count 0 2006.183.07:31:11.61#ibcon#read 5, iclass 19, count 0 2006.183.07:31:11.61#ibcon#about to read 6, iclass 19, count 0 2006.183.07:31:11.61#ibcon#read 6, iclass 19, count 0 2006.183.07:31:11.61#ibcon#end of sib2, iclass 19, count 0 2006.183.07:31:11.62#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:31:11.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:31:11.62#ibcon#[27=USB\r\n] 2006.183.07:31:11.62#ibcon#*before write, iclass 19, count 0 2006.183.07:31:11.62#ibcon#enter sib2, iclass 19, count 0 2006.183.07:31:11.62#ibcon#flushed, iclass 19, count 0 2006.183.07:31:11.62#ibcon#about to write, iclass 19, count 0 2006.183.07:31:11.62#ibcon#wrote, iclass 19, count 0 2006.183.07:31:11.62#ibcon#about to read 3, iclass 19, count 0 2006.183.07:31:11.64#ibcon#read 3, iclass 19, count 0 2006.183.07:31:11.64#ibcon#about to read 4, iclass 19, count 0 2006.183.07:31:11.64#ibcon#read 4, iclass 19, count 0 2006.183.07:31:11.64#ibcon#about to read 5, iclass 19, count 0 2006.183.07:31:11.64#ibcon#read 5, iclass 19, count 0 2006.183.07:31:11.64#ibcon#about to read 6, iclass 19, count 0 2006.183.07:31:11.64#ibcon#read 6, iclass 19, count 0 2006.183.07:31:11.64#ibcon#end of sib2, iclass 19, count 0 2006.183.07:31:11.65#ibcon#*after write, iclass 19, count 0 2006.183.07:31:11.65#ibcon#*before return 0, iclass 19, count 0 2006.183.07:31:11.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:11.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:31:11.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:31:11.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:31:11.65$vc4f8/vblo=4,712.99 2006.183.07:31:11.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:31:11.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:31:11.65#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:11.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:11.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:11.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:11.65#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:31:11.65#ibcon#first serial, iclass 21, count 0 2006.183.07:31:11.65#ibcon#enter sib2, iclass 21, count 0 2006.183.07:31:11.65#ibcon#flushed, iclass 21, count 0 2006.183.07:31:11.65#ibcon#about to write, iclass 21, count 0 2006.183.07:31:11.65#ibcon#wrote, iclass 21, count 0 2006.183.07:31:11.65#ibcon#about to read 3, iclass 21, count 0 2006.183.07:31:11.67#ibcon#read 3, iclass 21, count 0 2006.183.07:31:11.67#ibcon#about to read 4, iclass 21, count 0 2006.183.07:31:11.67#ibcon#read 4, iclass 21, count 0 2006.183.07:31:11.67#ibcon#about to read 5, iclass 21, count 0 2006.183.07:31:11.67#ibcon#read 5, iclass 21, count 0 2006.183.07:31:11.67#ibcon#about to read 6, iclass 21, count 0 2006.183.07:31:11.67#ibcon#read 6, iclass 21, count 0 2006.183.07:31:11.67#ibcon#end of sib2, iclass 21, count 0 2006.183.07:31:11.67#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:31:11.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:31:11.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:31:11.67#ibcon#*before write, iclass 21, count 0 2006.183.07:31:11.67#ibcon#enter sib2, iclass 21, count 0 2006.183.07:31:11.67#ibcon#flushed, iclass 21, count 0 2006.183.07:31:11.67#ibcon#about to write, iclass 21, count 0 2006.183.07:31:11.67#ibcon#wrote, iclass 21, count 0 2006.183.07:31:11.67#ibcon#about to read 3, iclass 21, count 0 2006.183.07:31:11.71#ibcon#read 3, iclass 21, count 0 2006.183.07:31:11.71#ibcon#about to read 4, iclass 21, count 0 2006.183.07:31:11.71#ibcon#read 4, iclass 21, count 0 2006.183.07:31:11.71#ibcon#about to read 5, iclass 21, count 0 2006.183.07:31:11.71#ibcon#read 5, iclass 21, count 0 2006.183.07:31:11.72#ibcon#about to read 6, iclass 21, count 0 2006.183.07:31:11.72#ibcon#read 6, iclass 21, count 0 2006.183.07:31:11.72#ibcon#end of sib2, iclass 21, count 0 2006.183.07:31:11.72#ibcon#*after write, iclass 21, count 0 2006.183.07:31:11.72#ibcon#*before return 0, iclass 21, count 0 2006.183.07:31:11.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:11.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:31:11.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:31:11.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:31:11.72$vc4f8/vb=4,4 2006.183.07:31:11.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:31:11.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:31:11.72#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:11.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:11.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:11.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:11.77#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:31:11.77#ibcon#first serial, iclass 23, count 2 2006.183.07:31:11.77#ibcon#enter sib2, iclass 23, count 2 2006.183.07:31:11.77#ibcon#flushed, iclass 23, count 2 2006.183.07:31:11.77#ibcon#about to write, iclass 23, count 2 2006.183.07:31:11.77#ibcon#wrote, iclass 23, count 2 2006.183.07:31:11.77#ibcon#about to read 3, iclass 23, count 2 2006.183.07:31:11.78#ibcon#read 3, iclass 23, count 2 2006.183.07:31:11.78#ibcon#about to read 4, iclass 23, count 2 2006.183.07:31:11.78#ibcon#read 4, iclass 23, count 2 2006.183.07:31:11.78#ibcon#about to read 5, iclass 23, count 2 2006.183.07:31:11.78#ibcon#read 5, iclass 23, count 2 2006.183.07:31:11.78#ibcon#about to read 6, iclass 23, count 2 2006.183.07:31:11.78#ibcon#read 6, iclass 23, count 2 2006.183.07:31:11.78#ibcon#end of sib2, iclass 23, count 2 2006.183.07:31:11.78#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:31:11.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:31:11.79#ibcon#[27=AT04-04\r\n] 2006.183.07:31:11.79#ibcon#*before write, iclass 23, count 2 2006.183.07:31:11.79#ibcon#enter sib2, iclass 23, count 2 2006.183.07:31:11.79#ibcon#flushed, iclass 23, count 2 2006.183.07:31:11.79#ibcon#about to write, iclass 23, count 2 2006.183.07:31:11.79#ibcon#wrote, iclass 23, count 2 2006.183.07:31:11.79#ibcon#about to read 3, iclass 23, count 2 2006.183.07:31:11.81#ibcon#read 3, iclass 23, count 2 2006.183.07:31:11.81#ibcon#about to read 4, iclass 23, count 2 2006.183.07:31:11.81#ibcon#read 4, iclass 23, count 2 2006.183.07:31:11.81#ibcon#about to read 5, iclass 23, count 2 2006.183.07:31:11.81#ibcon#read 5, iclass 23, count 2 2006.183.07:31:11.81#ibcon#about to read 6, iclass 23, count 2 2006.183.07:31:11.82#ibcon#read 6, iclass 23, count 2 2006.183.07:31:11.82#ibcon#end of sib2, iclass 23, count 2 2006.183.07:31:11.82#ibcon#*after write, iclass 23, count 2 2006.183.07:31:11.82#ibcon#*before return 0, iclass 23, count 2 2006.183.07:31:11.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:11.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:31:11.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:31:11.82#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:11.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:11.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:11.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:11.93#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:31:11.93#ibcon#first serial, iclass 23, count 0 2006.183.07:31:11.93#ibcon#enter sib2, iclass 23, count 0 2006.183.07:31:11.93#ibcon#flushed, iclass 23, count 0 2006.183.07:31:11.93#ibcon#about to write, iclass 23, count 0 2006.183.07:31:11.93#ibcon#wrote, iclass 23, count 0 2006.183.07:31:11.93#ibcon#about to read 3, iclass 23, count 0 2006.183.07:31:11.95#ibcon#read 3, iclass 23, count 0 2006.183.07:31:11.95#ibcon#about to read 4, iclass 23, count 0 2006.183.07:31:11.95#ibcon#read 4, iclass 23, count 0 2006.183.07:31:11.95#ibcon#about to read 5, iclass 23, count 0 2006.183.07:31:11.95#ibcon#read 5, iclass 23, count 0 2006.183.07:31:11.95#ibcon#about to read 6, iclass 23, count 0 2006.183.07:31:11.95#ibcon#read 6, iclass 23, count 0 2006.183.07:31:11.95#ibcon#end of sib2, iclass 23, count 0 2006.183.07:31:11.95#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:31:11.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:31:11.96#ibcon#[27=USB\r\n] 2006.183.07:31:11.96#ibcon#*before write, iclass 23, count 0 2006.183.07:31:11.96#ibcon#enter sib2, iclass 23, count 0 2006.183.07:31:11.96#ibcon#flushed, iclass 23, count 0 2006.183.07:31:11.96#ibcon#about to write, iclass 23, count 0 2006.183.07:31:11.96#ibcon#wrote, iclass 23, count 0 2006.183.07:31:11.96#ibcon#about to read 3, iclass 23, count 0 2006.183.07:31:11.98#ibcon#read 3, iclass 23, count 0 2006.183.07:31:11.98#ibcon#about to read 4, iclass 23, count 0 2006.183.07:31:11.98#ibcon#read 4, iclass 23, count 0 2006.183.07:31:11.98#ibcon#about to read 5, iclass 23, count 0 2006.183.07:31:11.98#ibcon#read 5, iclass 23, count 0 2006.183.07:31:11.98#ibcon#about to read 6, iclass 23, count 0 2006.183.07:31:11.98#ibcon#read 6, iclass 23, count 0 2006.183.07:31:11.98#ibcon#end of sib2, iclass 23, count 0 2006.183.07:31:11.99#ibcon#*after write, iclass 23, count 0 2006.183.07:31:11.99#ibcon#*before return 0, iclass 23, count 0 2006.183.07:31:11.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:11.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:31:11.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:31:11.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:31:11.99$vc4f8/vblo=5,744.99 2006.183.07:31:11.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:31:11.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:31:11.99#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:11.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:11.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:11.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:11.99#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:31:11.99#ibcon#first serial, iclass 25, count 0 2006.183.07:31:11.99#ibcon#enter sib2, iclass 25, count 0 2006.183.07:31:11.99#ibcon#flushed, iclass 25, count 0 2006.183.07:31:11.99#ibcon#about to write, iclass 25, count 0 2006.183.07:31:11.99#ibcon#wrote, iclass 25, count 0 2006.183.07:31:11.99#ibcon#about to read 3, iclass 25, count 0 2006.183.07:31:12.00#ibcon#read 3, iclass 25, count 0 2006.183.07:31:12.00#ibcon#about to read 4, iclass 25, count 0 2006.183.07:31:12.00#ibcon#read 4, iclass 25, count 0 2006.183.07:31:12.00#ibcon#about to read 5, iclass 25, count 0 2006.183.07:31:12.00#ibcon#read 5, iclass 25, count 0 2006.183.07:31:12.00#ibcon#about to read 6, iclass 25, count 0 2006.183.07:31:12.00#ibcon#read 6, iclass 25, count 0 2006.183.07:31:12.00#ibcon#end of sib2, iclass 25, count 0 2006.183.07:31:12.01#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:31:12.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:31:12.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:31:12.01#ibcon#*before write, iclass 25, count 0 2006.183.07:31:12.01#ibcon#enter sib2, iclass 25, count 0 2006.183.07:31:12.01#ibcon#flushed, iclass 25, count 0 2006.183.07:31:12.01#ibcon#about to write, iclass 25, count 0 2006.183.07:31:12.01#ibcon#wrote, iclass 25, count 0 2006.183.07:31:12.01#ibcon#about to read 3, iclass 25, count 0 2006.183.07:31:12.04#ibcon#read 3, iclass 25, count 0 2006.183.07:31:12.04#ibcon#about to read 4, iclass 25, count 0 2006.183.07:31:12.04#ibcon#read 4, iclass 25, count 0 2006.183.07:31:12.04#ibcon#about to read 5, iclass 25, count 0 2006.183.07:31:12.04#ibcon#read 5, iclass 25, count 0 2006.183.07:31:12.04#ibcon#about to read 6, iclass 25, count 0 2006.183.07:31:12.04#ibcon#read 6, iclass 25, count 0 2006.183.07:31:12.04#ibcon#end of sib2, iclass 25, count 0 2006.183.07:31:12.05#ibcon#*after write, iclass 25, count 0 2006.183.07:31:12.05#ibcon#*before return 0, iclass 25, count 0 2006.183.07:31:12.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:12.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:31:12.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:31:12.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:31:12.05$vc4f8/vb=5,4 2006.183.07:31:12.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.07:31:12.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.07:31:12.05#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:12.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:12.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:12.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:12.10#ibcon#enter wrdev, iclass 27, count 2 2006.183.07:31:12.10#ibcon#first serial, iclass 27, count 2 2006.183.07:31:12.10#ibcon#enter sib2, iclass 27, count 2 2006.183.07:31:12.10#ibcon#flushed, iclass 27, count 2 2006.183.07:31:12.10#ibcon#about to write, iclass 27, count 2 2006.183.07:31:12.10#ibcon#wrote, iclass 27, count 2 2006.183.07:31:12.10#ibcon#about to read 3, iclass 27, count 2 2006.183.07:31:12.12#ibcon#read 3, iclass 27, count 2 2006.183.07:31:12.12#ibcon#about to read 4, iclass 27, count 2 2006.183.07:31:12.12#ibcon#read 4, iclass 27, count 2 2006.183.07:31:12.12#ibcon#about to read 5, iclass 27, count 2 2006.183.07:31:12.12#ibcon#read 5, iclass 27, count 2 2006.183.07:31:12.12#ibcon#about to read 6, iclass 27, count 2 2006.183.07:31:12.12#ibcon#read 6, iclass 27, count 2 2006.183.07:31:12.12#ibcon#end of sib2, iclass 27, count 2 2006.183.07:31:12.12#ibcon#*mode == 0, iclass 27, count 2 2006.183.07:31:12.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.07:31:12.13#ibcon#[27=AT05-04\r\n] 2006.183.07:31:12.13#ibcon#*before write, iclass 27, count 2 2006.183.07:31:12.13#ibcon#enter sib2, iclass 27, count 2 2006.183.07:31:12.13#ibcon#flushed, iclass 27, count 2 2006.183.07:31:12.13#ibcon#about to write, iclass 27, count 2 2006.183.07:31:12.13#ibcon#wrote, iclass 27, count 2 2006.183.07:31:12.13#ibcon#about to read 3, iclass 27, count 2 2006.183.07:31:12.15#ibcon#read 3, iclass 27, count 2 2006.183.07:31:12.15#ibcon#about to read 4, iclass 27, count 2 2006.183.07:31:12.15#ibcon#read 4, iclass 27, count 2 2006.183.07:31:12.15#ibcon#about to read 5, iclass 27, count 2 2006.183.07:31:12.15#ibcon#read 5, iclass 27, count 2 2006.183.07:31:12.15#ibcon#about to read 6, iclass 27, count 2 2006.183.07:31:12.16#ibcon#read 6, iclass 27, count 2 2006.183.07:31:12.16#ibcon#end of sib2, iclass 27, count 2 2006.183.07:31:12.16#ibcon#*after write, iclass 27, count 2 2006.183.07:31:12.16#ibcon#*before return 0, iclass 27, count 2 2006.183.07:31:12.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:12.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:31:12.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.07:31:12.16#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:12.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:12.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:12.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:12.27#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:31:12.27#ibcon#first serial, iclass 27, count 0 2006.183.07:31:12.27#ibcon#enter sib2, iclass 27, count 0 2006.183.07:31:12.27#ibcon#flushed, iclass 27, count 0 2006.183.07:31:12.27#ibcon#about to write, iclass 27, count 0 2006.183.07:31:12.27#ibcon#wrote, iclass 27, count 0 2006.183.07:31:12.27#ibcon#about to read 3, iclass 27, count 0 2006.183.07:31:12.29#ibcon#read 3, iclass 27, count 0 2006.183.07:31:12.29#ibcon#about to read 4, iclass 27, count 0 2006.183.07:31:12.29#ibcon#read 4, iclass 27, count 0 2006.183.07:31:12.29#ibcon#about to read 5, iclass 27, count 0 2006.183.07:31:12.29#ibcon#read 5, iclass 27, count 0 2006.183.07:31:12.29#ibcon#about to read 6, iclass 27, count 0 2006.183.07:31:12.29#ibcon#read 6, iclass 27, count 0 2006.183.07:31:12.29#ibcon#end of sib2, iclass 27, count 0 2006.183.07:31:12.29#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:31:12.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:31:12.30#ibcon#[27=USB\r\n] 2006.183.07:31:12.30#ibcon#*before write, iclass 27, count 0 2006.183.07:31:12.30#ibcon#enter sib2, iclass 27, count 0 2006.183.07:31:12.30#ibcon#flushed, iclass 27, count 0 2006.183.07:31:12.30#ibcon#about to write, iclass 27, count 0 2006.183.07:31:12.30#ibcon#wrote, iclass 27, count 0 2006.183.07:31:12.30#ibcon#about to read 3, iclass 27, count 0 2006.183.07:31:12.32#ibcon#read 3, iclass 27, count 0 2006.183.07:31:12.32#ibcon#about to read 4, iclass 27, count 0 2006.183.07:31:12.32#ibcon#read 4, iclass 27, count 0 2006.183.07:31:12.32#ibcon#about to read 5, iclass 27, count 0 2006.183.07:31:12.32#ibcon#read 5, iclass 27, count 0 2006.183.07:31:12.32#ibcon#about to read 6, iclass 27, count 0 2006.183.07:31:12.32#ibcon#read 6, iclass 27, count 0 2006.183.07:31:12.32#ibcon#end of sib2, iclass 27, count 0 2006.183.07:31:12.32#ibcon#*after write, iclass 27, count 0 2006.183.07:31:12.33#ibcon#*before return 0, iclass 27, count 0 2006.183.07:31:12.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:12.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:31:12.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:31:12.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:31:12.33$vc4f8/vblo=6,752.99 2006.183.07:31:12.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.07:31:12.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.07:31:12.33#ibcon#ireg 17 cls_cnt 0 2006.183.07:31:12.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:12.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:12.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:12.33#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:31:12.33#ibcon#first serial, iclass 29, count 0 2006.183.07:31:12.33#ibcon#enter sib2, iclass 29, count 0 2006.183.07:31:12.33#ibcon#flushed, iclass 29, count 0 2006.183.07:31:12.33#ibcon#about to write, iclass 29, count 0 2006.183.07:31:12.33#ibcon#wrote, iclass 29, count 0 2006.183.07:31:12.33#ibcon#about to read 3, iclass 29, count 0 2006.183.07:31:12.34#ibcon#read 3, iclass 29, count 0 2006.183.07:31:12.34#ibcon#about to read 4, iclass 29, count 0 2006.183.07:31:12.34#ibcon#read 4, iclass 29, count 0 2006.183.07:31:12.34#ibcon#about to read 5, iclass 29, count 0 2006.183.07:31:12.34#ibcon#read 5, iclass 29, count 0 2006.183.07:31:12.34#ibcon#about to read 6, iclass 29, count 0 2006.183.07:31:12.34#ibcon#read 6, iclass 29, count 0 2006.183.07:31:12.34#ibcon#end of sib2, iclass 29, count 0 2006.183.07:31:12.35#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:31:12.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:31:12.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:31:12.35#ibcon#*before write, iclass 29, count 0 2006.183.07:31:12.35#ibcon#enter sib2, iclass 29, count 0 2006.183.07:31:12.35#ibcon#flushed, iclass 29, count 0 2006.183.07:31:12.35#ibcon#about to write, iclass 29, count 0 2006.183.07:31:12.35#ibcon#wrote, iclass 29, count 0 2006.183.07:31:12.35#ibcon#about to read 3, iclass 29, count 0 2006.183.07:31:12.38#ibcon#read 3, iclass 29, count 0 2006.183.07:31:12.38#ibcon#about to read 4, iclass 29, count 0 2006.183.07:31:12.38#ibcon#read 4, iclass 29, count 0 2006.183.07:31:12.38#ibcon#about to read 5, iclass 29, count 0 2006.183.07:31:12.38#ibcon#read 5, iclass 29, count 0 2006.183.07:31:12.38#ibcon#about to read 6, iclass 29, count 0 2006.183.07:31:12.38#ibcon#read 6, iclass 29, count 0 2006.183.07:31:12.38#ibcon#end of sib2, iclass 29, count 0 2006.183.07:31:12.39#ibcon#*after write, iclass 29, count 0 2006.183.07:31:12.39#ibcon#*before return 0, iclass 29, count 0 2006.183.07:31:12.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:12.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:31:12.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:31:12.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:31:12.39$vc4f8/vb=6,4 2006.183.07:31:12.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.07:31:12.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.07:31:12.39#ibcon#ireg 11 cls_cnt 2 2006.183.07:31:12.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:12.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:12.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:12.44#ibcon#enter wrdev, iclass 31, count 2 2006.183.07:31:12.44#ibcon#first serial, iclass 31, count 2 2006.183.07:31:12.44#ibcon#enter sib2, iclass 31, count 2 2006.183.07:31:12.44#ibcon#flushed, iclass 31, count 2 2006.183.07:31:12.44#ibcon#about to write, iclass 31, count 2 2006.183.07:31:12.44#ibcon#wrote, iclass 31, count 2 2006.183.07:31:12.44#ibcon#about to read 3, iclass 31, count 2 2006.183.07:31:12.46#ibcon#read 3, iclass 31, count 2 2006.183.07:31:12.46#ibcon#about to read 4, iclass 31, count 2 2006.183.07:31:12.46#ibcon#read 4, iclass 31, count 2 2006.183.07:31:12.46#ibcon#about to read 5, iclass 31, count 2 2006.183.07:31:12.46#ibcon#read 5, iclass 31, count 2 2006.183.07:31:12.46#ibcon#about to read 6, iclass 31, count 2 2006.183.07:31:12.46#ibcon#read 6, iclass 31, count 2 2006.183.07:31:12.46#ibcon#end of sib2, iclass 31, count 2 2006.183.07:31:12.47#ibcon#*mode == 0, iclass 31, count 2 2006.183.07:31:12.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.07:31:12.47#ibcon#[27=AT06-04\r\n] 2006.183.07:31:12.47#ibcon#*before write, iclass 31, count 2 2006.183.07:31:12.47#ibcon#enter sib2, iclass 31, count 2 2006.183.07:31:12.47#ibcon#flushed, iclass 31, count 2 2006.183.07:31:12.47#ibcon#about to write, iclass 31, count 2 2006.183.07:31:12.47#ibcon#wrote, iclass 31, count 2 2006.183.07:31:12.47#ibcon#about to read 3, iclass 31, count 2 2006.183.07:31:12.49#ibcon#read 3, iclass 31, count 2 2006.183.07:31:12.49#ibcon#about to read 4, iclass 31, count 2 2006.183.07:31:12.49#ibcon#read 4, iclass 31, count 2 2006.183.07:31:12.49#ibcon#about to read 5, iclass 31, count 2 2006.183.07:31:12.49#ibcon#read 5, iclass 31, count 2 2006.183.07:31:12.49#ibcon#about to read 6, iclass 31, count 2 2006.183.07:31:12.50#ibcon#read 6, iclass 31, count 2 2006.183.07:31:12.50#ibcon#end of sib2, iclass 31, count 2 2006.183.07:31:12.50#ibcon#*after write, iclass 31, count 2 2006.183.07:31:12.50#ibcon#*before return 0, iclass 31, count 2 2006.183.07:31:12.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:12.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:31:12.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.07:31:12.50#ibcon#ireg 7 cls_cnt 0 2006.183.07:31:12.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:12.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:12.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:12.61#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:31:12.61#ibcon#first serial, iclass 31, count 0 2006.183.07:31:12.61#ibcon#enter sib2, iclass 31, count 0 2006.183.07:31:12.61#ibcon#flushed, iclass 31, count 0 2006.183.07:31:12.61#ibcon#about to write, iclass 31, count 0 2006.183.07:31:12.61#ibcon#wrote, iclass 31, count 0 2006.183.07:31:12.61#ibcon#about to read 3, iclass 31, count 0 2006.183.07:31:12.63#ibcon#read 3, iclass 31, count 0 2006.183.07:31:12.63#ibcon#about to read 4, iclass 31, count 0 2006.183.07:31:12.63#ibcon#read 4, iclass 31, count 0 2006.183.07:31:12.63#ibcon#about to read 5, iclass 31, count 0 2006.183.07:31:12.63#ibcon#read 5, iclass 31, count 0 2006.183.07:31:12.63#ibcon#about to read 6, iclass 31, count 0 2006.183.07:31:12.63#ibcon#read 6, iclass 31, count 0 2006.183.07:31:12.63#ibcon#end of sib2, iclass 31, count 0 2006.183.07:31:12.63#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:31:12.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:31:12.64#ibcon#[27=USB\r\n] 2006.183.07:31:12.64#ibcon#*before write, iclass 31, count 0 2006.183.07:31:12.64#ibcon#enter sib2, iclass 31, count 0 2006.183.07:31:12.64#ibcon#flushed, iclass 31, count 0 2006.183.07:31:12.64#ibcon#about to write, iclass 31, count 0 2006.183.07:31:12.64#ibcon#wrote, iclass 31, count 0 2006.183.07:31:12.64#ibcon#about to read 3, iclass 31, count 0 2006.183.07:31:12.66#ibcon#read 3, iclass 31, count 0 2006.183.07:31:12.66#ibcon#about to read 4, iclass 31, count 0 2006.183.07:31:12.66#ibcon#read 4, iclass 31, count 0 2006.183.07:31:12.66#ibcon#about to read 5, iclass 31, count 0 2006.183.07:31:12.66#ibcon#read 5, iclass 31, count 0 2006.183.07:31:12.66#ibcon#about to read 6, iclass 31, count 0 2006.183.07:31:12.66#ibcon#read 6, iclass 31, count 0 2006.183.07:31:12.66#ibcon#end of sib2, iclass 31, count 0 2006.183.07:31:12.66#ibcon#*after write, iclass 31, count 0 2006.183.07:31:12.67#ibcon#*before return 0, iclass 31, count 0 2006.183.07:31:12.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:12.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:31:12.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:31:12.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:31:12.67$vc4f8/vabw=wide 2006.183.07:31:12.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.07:31:12.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.07:31:12.67#ibcon#ireg 8 cls_cnt 0 2006.183.07:31:12.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:12.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:12.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:12.67#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:31:12.67#ibcon#first serial, iclass 33, count 0 2006.183.07:31:12.67#ibcon#enter sib2, iclass 33, count 0 2006.183.07:31:12.67#ibcon#flushed, iclass 33, count 0 2006.183.07:31:12.67#ibcon#about to write, iclass 33, count 0 2006.183.07:31:12.67#ibcon#wrote, iclass 33, count 0 2006.183.07:31:12.67#ibcon#about to read 3, iclass 33, count 0 2006.183.07:31:12.69#ibcon#read 3, iclass 33, count 0 2006.183.07:31:12.69#ibcon#about to read 4, iclass 33, count 0 2006.183.07:31:12.69#ibcon#read 4, iclass 33, count 0 2006.183.07:31:12.69#ibcon#about to read 5, iclass 33, count 0 2006.183.07:31:12.69#ibcon#read 5, iclass 33, count 0 2006.183.07:31:12.69#ibcon#about to read 6, iclass 33, count 0 2006.183.07:31:12.69#ibcon#read 6, iclass 33, count 0 2006.183.07:31:12.69#ibcon#end of sib2, iclass 33, count 0 2006.183.07:31:12.69#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:31:12.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:31:12.69#ibcon#[25=BW32\r\n] 2006.183.07:31:12.69#ibcon#*before write, iclass 33, count 0 2006.183.07:31:12.69#ibcon#enter sib2, iclass 33, count 0 2006.183.07:31:12.69#ibcon#flushed, iclass 33, count 0 2006.183.07:31:12.69#ibcon#about to write, iclass 33, count 0 2006.183.07:31:12.69#ibcon#wrote, iclass 33, count 0 2006.183.07:31:12.69#ibcon#about to read 3, iclass 33, count 0 2006.183.07:31:12.72#ibcon#read 3, iclass 33, count 0 2006.183.07:31:12.72#ibcon#about to read 4, iclass 33, count 0 2006.183.07:31:12.72#ibcon#read 4, iclass 33, count 0 2006.183.07:31:12.72#ibcon#about to read 5, iclass 33, count 0 2006.183.07:31:12.72#ibcon#read 5, iclass 33, count 0 2006.183.07:31:12.72#ibcon#about to read 6, iclass 33, count 0 2006.183.07:31:12.72#ibcon#read 6, iclass 33, count 0 2006.183.07:31:12.72#ibcon#end of sib2, iclass 33, count 0 2006.183.07:31:12.73#ibcon#*after write, iclass 33, count 0 2006.183.07:31:12.73#ibcon#*before return 0, iclass 33, count 0 2006.183.07:31:12.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:12.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:31:12.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:31:12.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:31:12.73$vc4f8/vbbw=wide 2006.183.07:31:12.73#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.07:31:12.73#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.07:31:12.73#ibcon#ireg 8 cls_cnt 0 2006.183.07:31:12.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:31:12.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:31:12.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:31:12.79#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:31:12.79#ibcon#first serial, iclass 35, count 0 2006.183.07:31:12.79#ibcon#enter sib2, iclass 35, count 0 2006.183.07:31:12.79#ibcon#flushed, iclass 35, count 0 2006.183.07:31:12.79#ibcon#about to write, iclass 35, count 0 2006.183.07:31:12.79#ibcon#wrote, iclass 35, count 0 2006.183.07:31:12.79#ibcon#about to read 3, iclass 35, count 0 2006.183.07:31:12.80#ibcon#read 3, iclass 35, count 0 2006.183.07:31:12.80#ibcon#about to read 4, iclass 35, count 0 2006.183.07:31:12.80#ibcon#read 4, iclass 35, count 0 2006.183.07:31:12.80#ibcon#about to read 5, iclass 35, count 0 2006.183.07:31:12.80#ibcon#read 5, iclass 35, count 0 2006.183.07:31:12.80#ibcon#about to read 6, iclass 35, count 0 2006.183.07:31:12.80#ibcon#read 6, iclass 35, count 0 2006.183.07:31:12.80#ibcon#end of sib2, iclass 35, count 0 2006.183.07:31:12.80#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:31:12.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:31:12.81#ibcon#[27=BW32\r\n] 2006.183.07:31:12.81#ibcon#*before write, iclass 35, count 0 2006.183.07:31:12.81#ibcon#enter sib2, iclass 35, count 0 2006.183.07:31:12.81#ibcon#flushed, iclass 35, count 0 2006.183.07:31:12.81#ibcon#about to write, iclass 35, count 0 2006.183.07:31:12.81#ibcon#wrote, iclass 35, count 0 2006.183.07:31:12.81#ibcon#about to read 3, iclass 35, count 0 2006.183.07:31:12.83#ibcon#read 3, iclass 35, count 0 2006.183.07:31:12.83#ibcon#about to read 4, iclass 35, count 0 2006.183.07:31:12.83#ibcon#read 4, iclass 35, count 0 2006.183.07:31:12.83#ibcon#about to read 5, iclass 35, count 0 2006.183.07:31:12.83#ibcon#read 5, iclass 35, count 0 2006.183.07:31:12.83#ibcon#about to read 6, iclass 35, count 0 2006.183.07:31:12.84#ibcon#read 6, iclass 35, count 0 2006.183.07:31:12.84#ibcon#end of sib2, iclass 35, count 0 2006.183.07:31:12.84#ibcon#*after write, iclass 35, count 0 2006.183.07:31:12.84#ibcon#*before return 0, iclass 35, count 0 2006.183.07:31:12.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:31:12.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:31:12.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:31:12.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:31:12.84$4f8m12a/ifd4f 2006.183.07:31:12.84$ifd4f/lo= 2006.183.07:31:12.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:31:12.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:31:12.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:31:12.84$ifd4f/patch= 2006.183.07:31:12.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:31:12.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:31:12.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:31:12.84$4f8m12a/"form=m,16.000,1:2 2006.183.07:31:12.84$4f8m12a/"tpicd 2006.183.07:31:12.84$4f8m12a/echo=off 2006.183.07:31:12.84$4f8m12a/xlog=off 2006.183.07:31:12.84:!2006.183.07:33:20 2006.183.07:31:57.14#trakl#Source acquired 2006.183.07:31:58.15#flagr#flagr/antenna,acquired 2006.183.07:33:20.01:preob 2006.183.07:33:21.13/onsource/TRACKING 2006.183.07:33:21.14:!2006.183.07:33:30 2006.183.07:33:30.01:data_valid=on 2006.183.07:33:30.02:midob 2006.183.07:33:31.13/onsource/TRACKING 2006.183.07:33:31.14/wx/27.90,996.3,88 2006.183.07:33:31.31/cable/+6.4537E-03 2006.183.07:33:32.40/va/01,08,usb,yes,29,31 2006.183.07:33:32.40/va/02,07,usb,yes,29,31 2006.183.07:33:32.40/va/03,06,usb,yes,31,31 2006.183.07:33:32.40/va/04,07,usb,yes,30,33 2006.183.07:33:32.40/va/05,07,usb,yes,32,34 2006.183.07:33:32.40/va/06,06,usb,yes,31,31 2006.183.07:33:32.40/va/07,06,usb,yes,32,31 2006.183.07:33:32.40/va/08,07,usb,yes,30,29 2006.183.07:33:32.63/valo/01,532.99,yes,locked 2006.183.07:33:32.63/valo/02,572.99,yes,locked 2006.183.07:33:32.63/valo/03,672.99,yes,locked 2006.183.07:33:32.63/valo/04,832.99,yes,locked 2006.183.07:33:32.63/valo/05,652.99,yes,locked 2006.183.07:33:32.63/valo/06,772.99,yes,locked 2006.183.07:33:32.63/valo/07,832.99,yes,locked 2006.183.07:33:32.63/valo/08,852.99,yes,locked 2006.183.07:33:33.72/vb/01,04,usb,yes,29,28 2006.183.07:33:33.72/vb/02,04,usb,yes,31,33 2006.183.07:33:33.72/vb/03,04,usb,yes,27,31 2006.183.07:33:33.72/vb/04,04,usb,yes,28,28 2006.183.07:33:33.72/vb/05,04,usb,yes,27,31 2006.183.07:33:33.72/vb/06,04,usb,yes,28,30 2006.183.07:33:33.72/vb/07,04,usb,yes,30,30 2006.183.07:33:33.72/vb/08,04,usb,yes,27,31 2006.183.07:33:33.95/vblo/01,632.99,yes,locked 2006.183.07:33:33.95/vblo/02,640.99,yes,locked 2006.183.07:33:33.95/vblo/03,656.99,yes,locked 2006.183.07:33:33.95/vblo/04,712.99,yes,locked 2006.183.07:33:33.95/vblo/05,744.99,yes,locked 2006.183.07:33:33.95/vblo/06,752.99,yes,locked 2006.183.07:33:33.95/vblo/07,734.99,yes,locked 2006.183.07:33:33.95/vblo/08,744.99,yes,locked 2006.183.07:33:34.10/vabw/8 2006.183.07:33:34.25/vbbw/8 2006.183.07:33:34.34/xfe/off,on,16.0 2006.183.07:33:34.71/ifatt/23,28,28,28 2006.183.07:33:35.07/fmout-gps/S +3.29E-07 2006.183.07:33:35.12:!2006.183.07:34:30 2006.183.07:34:30.01:data_valid=off 2006.183.07:34:30.02:postob 2006.183.07:34:30.07/cable/+6.4522E-03 2006.183.07:34:30.08/wx/27.90,996.3,88 2006.183.07:34:31.07/fmout-gps/S +3.30E-07 2006.183.07:34:31.08:scan_name=183-0735,k06183,60 2006.183.07:34:31.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.183.07:34:32.13#flagr#flagr/antenna,new-source 2006.183.07:34:32.15:checkk5 2006.183.07:34:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:34:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:34:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:34:34.01/chk_obsdata//k5ts1/T1830733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:34:34.38/chk_obsdata//k5ts2/T1830733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:34:34.75/chk_obsdata//k5ts3/T1830733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:34:35.12/chk_obsdata//k5ts4/T1830733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:34:35.81/k5log//k5ts1_log_newline 2006.183.07:34:36.51/k5log//k5ts2_log_newline 2006.183.07:34:37.20/k5log//k5ts3_log_newline 2006.183.07:34:37.89/k5log//k5ts4_log_newline 2006.183.07:34:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:34:37.92:4f8m12a=1 2006.183.07:34:37.92$4f8m12a/echo=on 2006.183.07:34:37.92$4f8m12a/pcalon 2006.183.07:34:37.92$pcalon/"no phase cal control is implemented here 2006.183.07:34:37.92$4f8m12a/"tpicd=stop 2006.183.07:34:37.92$4f8m12a/vc4f8 2006.183.07:34:37.92$vc4f8/valo=1,532.99 2006.183.07:34:37.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.07:34:37.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.07:34:37.92#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:37.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:37.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:37.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:37.92#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:34:37.92#ibcon#first serial, iclass 10, count 0 2006.183.07:34:37.92#ibcon#enter sib2, iclass 10, count 0 2006.183.07:34:37.92#ibcon#flushed, iclass 10, count 0 2006.183.07:34:37.92#ibcon#about to write, iclass 10, count 0 2006.183.07:34:37.92#ibcon#wrote, iclass 10, count 0 2006.183.07:34:37.92#ibcon#about to read 3, iclass 10, count 0 2006.183.07:34:37.93#ibcon#read 3, iclass 10, count 0 2006.183.07:34:37.93#ibcon#about to read 4, iclass 10, count 0 2006.183.07:34:37.93#ibcon#read 4, iclass 10, count 0 2006.183.07:34:37.93#ibcon#about to read 5, iclass 10, count 0 2006.183.07:34:37.93#ibcon#read 5, iclass 10, count 0 2006.183.07:34:37.93#ibcon#about to read 6, iclass 10, count 0 2006.183.07:34:37.93#ibcon#read 6, iclass 10, count 0 2006.183.07:34:37.93#ibcon#end of sib2, iclass 10, count 0 2006.183.07:34:37.93#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:34:37.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:34:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:34:37.93#ibcon#*before write, iclass 10, count 0 2006.183.07:34:37.93#ibcon#enter sib2, iclass 10, count 0 2006.183.07:34:37.93#ibcon#flushed, iclass 10, count 0 2006.183.07:34:37.93#ibcon#about to write, iclass 10, count 0 2006.183.07:34:37.93#ibcon#wrote, iclass 10, count 0 2006.183.07:34:37.93#ibcon#about to read 3, iclass 10, count 0 2006.183.07:34:37.98#ibcon#read 3, iclass 10, count 0 2006.183.07:34:37.98#ibcon#about to read 4, iclass 10, count 0 2006.183.07:34:37.98#ibcon#read 4, iclass 10, count 0 2006.183.07:34:37.98#ibcon#about to read 5, iclass 10, count 0 2006.183.07:34:37.98#ibcon#read 5, iclass 10, count 0 2006.183.07:34:37.98#ibcon#about to read 6, iclass 10, count 0 2006.183.07:34:37.98#ibcon#read 6, iclass 10, count 0 2006.183.07:34:37.98#ibcon#end of sib2, iclass 10, count 0 2006.183.07:34:37.98#ibcon#*after write, iclass 10, count 0 2006.183.07:34:37.98#ibcon#*before return 0, iclass 10, count 0 2006.183.07:34:37.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:37.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:37.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:34:37.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:34:37.98$vc4f8/va=1,8 2006.183.07:34:37.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.07:34:37.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.07:34:37.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:37.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:37.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:37.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:37.98#ibcon#enter wrdev, iclass 12, count 2 2006.183.07:34:37.98#ibcon#first serial, iclass 12, count 2 2006.183.07:34:37.98#ibcon#enter sib2, iclass 12, count 2 2006.183.07:34:37.98#ibcon#flushed, iclass 12, count 2 2006.183.07:34:37.98#ibcon#about to write, iclass 12, count 2 2006.183.07:34:37.98#ibcon#wrote, iclass 12, count 2 2006.183.07:34:37.98#ibcon#about to read 3, iclass 12, count 2 2006.183.07:34:38.00#ibcon#read 3, iclass 12, count 2 2006.183.07:34:38.00#ibcon#about to read 4, iclass 12, count 2 2006.183.07:34:38.00#ibcon#read 4, iclass 12, count 2 2006.183.07:34:38.00#ibcon#about to read 5, iclass 12, count 2 2006.183.07:34:38.00#ibcon#read 5, iclass 12, count 2 2006.183.07:34:38.00#ibcon#about to read 6, iclass 12, count 2 2006.183.07:34:38.00#ibcon#read 6, iclass 12, count 2 2006.183.07:34:38.00#ibcon#end of sib2, iclass 12, count 2 2006.183.07:34:38.00#ibcon#*mode == 0, iclass 12, count 2 2006.183.07:34:38.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.07:34:38.00#ibcon#[25=AT01-08\r\n] 2006.183.07:34:38.00#ibcon#*before write, iclass 12, count 2 2006.183.07:34:38.00#ibcon#enter sib2, iclass 12, count 2 2006.183.07:34:38.00#ibcon#flushed, iclass 12, count 2 2006.183.07:34:38.00#ibcon#about to write, iclass 12, count 2 2006.183.07:34:38.00#ibcon#wrote, iclass 12, count 2 2006.183.07:34:38.00#ibcon#about to read 3, iclass 12, count 2 2006.183.07:34:38.04#ibcon#read 3, iclass 12, count 2 2006.183.07:34:38.04#ibcon#about to read 4, iclass 12, count 2 2006.183.07:34:38.04#ibcon#read 4, iclass 12, count 2 2006.183.07:34:38.04#ibcon#about to read 5, iclass 12, count 2 2006.183.07:34:38.04#ibcon#read 5, iclass 12, count 2 2006.183.07:34:38.04#ibcon#about to read 6, iclass 12, count 2 2006.183.07:34:38.04#ibcon#read 6, iclass 12, count 2 2006.183.07:34:38.04#ibcon#end of sib2, iclass 12, count 2 2006.183.07:34:38.04#ibcon#*after write, iclass 12, count 2 2006.183.07:34:38.04#ibcon#*before return 0, iclass 12, count 2 2006.183.07:34:38.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:38.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:38.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.07:34:38.04#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:38.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:38.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:38.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:38.15#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:34:38.15#ibcon#first serial, iclass 12, count 0 2006.183.07:34:38.15#ibcon#enter sib2, iclass 12, count 0 2006.183.07:34:38.15#ibcon#flushed, iclass 12, count 0 2006.183.07:34:38.15#ibcon#about to write, iclass 12, count 0 2006.183.07:34:38.15#ibcon#wrote, iclass 12, count 0 2006.183.07:34:38.15#ibcon#about to read 3, iclass 12, count 0 2006.183.07:34:38.17#ibcon#read 3, iclass 12, count 0 2006.183.07:34:38.17#ibcon#about to read 4, iclass 12, count 0 2006.183.07:34:38.17#ibcon#read 4, iclass 12, count 0 2006.183.07:34:38.17#ibcon#about to read 5, iclass 12, count 0 2006.183.07:34:38.17#ibcon#read 5, iclass 12, count 0 2006.183.07:34:38.17#ibcon#about to read 6, iclass 12, count 0 2006.183.07:34:38.17#ibcon#read 6, iclass 12, count 0 2006.183.07:34:38.17#ibcon#end of sib2, iclass 12, count 0 2006.183.07:34:38.17#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:34:38.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:34:38.17#ibcon#[25=USB\r\n] 2006.183.07:34:38.17#ibcon#*before write, iclass 12, count 0 2006.183.07:34:38.17#ibcon#enter sib2, iclass 12, count 0 2006.183.07:34:38.17#ibcon#flushed, iclass 12, count 0 2006.183.07:34:38.17#ibcon#about to write, iclass 12, count 0 2006.183.07:34:38.17#ibcon#wrote, iclass 12, count 0 2006.183.07:34:38.17#ibcon#about to read 3, iclass 12, count 0 2006.183.07:34:38.20#ibcon#read 3, iclass 12, count 0 2006.183.07:34:38.20#ibcon#about to read 4, iclass 12, count 0 2006.183.07:34:38.20#ibcon#read 4, iclass 12, count 0 2006.183.07:34:38.20#ibcon#about to read 5, iclass 12, count 0 2006.183.07:34:38.20#ibcon#read 5, iclass 12, count 0 2006.183.07:34:38.20#ibcon#about to read 6, iclass 12, count 0 2006.183.07:34:38.20#ibcon#read 6, iclass 12, count 0 2006.183.07:34:38.20#ibcon#end of sib2, iclass 12, count 0 2006.183.07:34:38.20#ibcon#*after write, iclass 12, count 0 2006.183.07:34:38.20#ibcon#*before return 0, iclass 12, count 0 2006.183.07:34:38.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:38.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:38.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:34:38.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:34:38.20$vc4f8/valo=2,572.99 2006.183.07:34:38.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.07:34:38.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.07:34:38.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:38.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:38.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:38.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:38.20#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:34:38.20#ibcon#first serial, iclass 14, count 0 2006.183.07:34:38.20#ibcon#enter sib2, iclass 14, count 0 2006.183.07:34:38.20#ibcon#flushed, iclass 14, count 0 2006.183.07:34:38.20#ibcon#about to write, iclass 14, count 0 2006.183.07:34:38.20#ibcon#wrote, iclass 14, count 0 2006.183.07:34:38.20#ibcon#about to read 3, iclass 14, count 0 2006.183.07:34:38.23#ibcon#read 3, iclass 14, count 0 2006.183.07:34:38.23#ibcon#about to read 4, iclass 14, count 0 2006.183.07:34:38.23#ibcon#read 4, iclass 14, count 0 2006.183.07:34:38.23#ibcon#about to read 5, iclass 14, count 0 2006.183.07:34:38.23#ibcon#read 5, iclass 14, count 0 2006.183.07:34:38.23#ibcon#about to read 6, iclass 14, count 0 2006.183.07:34:38.23#ibcon#read 6, iclass 14, count 0 2006.183.07:34:38.23#ibcon#end of sib2, iclass 14, count 0 2006.183.07:34:38.23#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:34:38.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:34:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:34:38.23#ibcon#*before write, iclass 14, count 0 2006.183.07:34:38.23#ibcon#enter sib2, iclass 14, count 0 2006.183.07:34:38.23#ibcon#flushed, iclass 14, count 0 2006.183.07:34:38.23#ibcon#about to write, iclass 14, count 0 2006.183.07:34:38.23#ibcon#wrote, iclass 14, count 0 2006.183.07:34:38.23#ibcon#about to read 3, iclass 14, count 0 2006.183.07:34:38.27#ibcon#read 3, iclass 14, count 0 2006.183.07:34:38.27#ibcon#about to read 4, iclass 14, count 0 2006.183.07:34:38.27#ibcon#read 4, iclass 14, count 0 2006.183.07:34:38.27#ibcon#about to read 5, iclass 14, count 0 2006.183.07:34:38.27#ibcon#read 5, iclass 14, count 0 2006.183.07:34:38.27#ibcon#about to read 6, iclass 14, count 0 2006.183.07:34:38.27#ibcon#read 6, iclass 14, count 0 2006.183.07:34:38.27#ibcon#end of sib2, iclass 14, count 0 2006.183.07:34:38.27#ibcon#*after write, iclass 14, count 0 2006.183.07:34:38.27#ibcon#*before return 0, iclass 14, count 0 2006.183.07:34:38.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:38.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:38.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:34:38.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:34:38.27$vc4f8/va=2,7 2006.183.07:34:38.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.07:34:38.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.07:34:38.27#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:38.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:38.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:38.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:38.33#ibcon#enter wrdev, iclass 16, count 2 2006.183.07:34:38.33#ibcon#first serial, iclass 16, count 2 2006.183.07:34:38.33#ibcon#enter sib2, iclass 16, count 2 2006.183.07:34:38.33#ibcon#flushed, iclass 16, count 2 2006.183.07:34:38.33#ibcon#about to write, iclass 16, count 2 2006.183.07:34:38.33#ibcon#wrote, iclass 16, count 2 2006.183.07:34:38.33#ibcon#about to read 3, iclass 16, count 2 2006.183.07:34:38.34#ibcon#read 3, iclass 16, count 2 2006.183.07:34:38.34#ibcon#about to read 4, iclass 16, count 2 2006.183.07:34:38.34#ibcon#read 4, iclass 16, count 2 2006.183.07:34:38.34#ibcon#about to read 5, iclass 16, count 2 2006.183.07:34:38.34#ibcon#read 5, iclass 16, count 2 2006.183.07:34:38.34#ibcon#about to read 6, iclass 16, count 2 2006.183.07:34:38.34#ibcon#read 6, iclass 16, count 2 2006.183.07:34:38.34#ibcon#end of sib2, iclass 16, count 2 2006.183.07:34:38.34#ibcon#*mode == 0, iclass 16, count 2 2006.183.07:34:38.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.07:34:38.34#ibcon#[25=AT02-07\r\n] 2006.183.07:34:38.34#ibcon#*before write, iclass 16, count 2 2006.183.07:34:38.34#ibcon#enter sib2, iclass 16, count 2 2006.183.07:34:38.34#ibcon#flushed, iclass 16, count 2 2006.183.07:34:38.34#ibcon#about to write, iclass 16, count 2 2006.183.07:34:38.34#ibcon#wrote, iclass 16, count 2 2006.183.07:34:38.34#ibcon#about to read 3, iclass 16, count 2 2006.183.07:34:38.37#ibcon#read 3, iclass 16, count 2 2006.183.07:34:38.37#ibcon#about to read 4, iclass 16, count 2 2006.183.07:34:38.37#ibcon#read 4, iclass 16, count 2 2006.183.07:34:38.37#ibcon#about to read 5, iclass 16, count 2 2006.183.07:34:38.37#ibcon#read 5, iclass 16, count 2 2006.183.07:34:38.37#ibcon#about to read 6, iclass 16, count 2 2006.183.07:34:38.37#ibcon#read 6, iclass 16, count 2 2006.183.07:34:38.37#ibcon#end of sib2, iclass 16, count 2 2006.183.07:34:38.37#ibcon#*after write, iclass 16, count 2 2006.183.07:34:38.37#ibcon#*before return 0, iclass 16, count 2 2006.183.07:34:38.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:38.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:38.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.07:34:38.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:38.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:38.49#abcon#<5=/10 3.1 8.2 27.90 88 996.3\r\n> 2006.183.07:34:38.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:38.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:38.49#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:34:38.49#ibcon#first serial, iclass 16, count 0 2006.183.07:34:38.49#ibcon#enter sib2, iclass 16, count 0 2006.183.07:34:38.49#ibcon#flushed, iclass 16, count 0 2006.183.07:34:38.49#ibcon#about to write, iclass 16, count 0 2006.183.07:34:38.49#ibcon#wrote, iclass 16, count 0 2006.183.07:34:38.49#ibcon#about to read 3, iclass 16, count 0 2006.183.07:34:38.51#ibcon#read 3, iclass 16, count 0 2006.183.07:34:38.51#ibcon#about to read 4, iclass 16, count 0 2006.183.07:34:38.51#ibcon#read 4, iclass 16, count 0 2006.183.07:34:38.51#ibcon#about to read 5, iclass 16, count 0 2006.183.07:34:38.51#ibcon#read 5, iclass 16, count 0 2006.183.07:34:38.51#ibcon#about to read 6, iclass 16, count 0 2006.183.07:34:38.51#ibcon#read 6, iclass 16, count 0 2006.183.07:34:38.51#ibcon#end of sib2, iclass 16, count 0 2006.183.07:34:38.51#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:34:38.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:34:38.51#ibcon#[25=USB\r\n] 2006.183.07:34:38.51#ibcon#*before write, iclass 16, count 0 2006.183.07:34:38.51#ibcon#enter sib2, iclass 16, count 0 2006.183.07:34:38.51#ibcon#flushed, iclass 16, count 0 2006.183.07:34:38.51#ibcon#about to write, iclass 16, count 0 2006.183.07:34:38.51#ibcon#wrote, iclass 16, count 0 2006.183.07:34:38.51#ibcon#about to read 3, iclass 16, count 0 2006.183.07:34:38.51#abcon#{5=INTERFACE CLEAR} 2006.183.07:34:38.54#ibcon#read 3, iclass 16, count 0 2006.183.07:34:38.54#ibcon#about to read 4, iclass 16, count 0 2006.183.07:34:38.54#ibcon#read 4, iclass 16, count 0 2006.183.07:34:38.54#ibcon#about to read 5, iclass 16, count 0 2006.183.07:34:38.54#ibcon#read 5, iclass 16, count 0 2006.183.07:34:38.54#ibcon#about to read 6, iclass 16, count 0 2006.183.07:34:38.54#ibcon#read 6, iclass 16, count 0 2006.183.07:34:38.54#ibcon#end of sib2, iclass 16, count 0 2006.183.07:34:38.54#ibcon#*after write, iclass 16, count 0 2006.183.07:34:38.54#ibcon#*before return 0, iclass 16, count 0 2006.183.07:34:38.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:38.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:38.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:34:38.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:34:38.54$vc4f8/valo=3,672.99 2006.183.07:34:38.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:34:38.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:34:38.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:38.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:34:38.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:34:38.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:34:38.54#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:34:38.54#ibcon#first serial, iclass 21, count 0 2006.183.07:34:38.54#ibcon#enter sib2, iclass 21, count 0 2006.183.07:34:38.54#ibcon#flushed, iclass 21, count 0 2006.183.07:34:38.54#ibcon#about to write, iclass 21, count 0 2006.183.07:34:38.54#ibcon#wrote, iclass 21, count 0 2006.183.07:34:38.54#ibcon#about to read 3, iclass 21, count 0 2006.183.07:34:38.57#ibcon#read 3, iclass 21, count 0 2006.183.07:34:38.57#ibcon#about to read 4, iclass 21, count 0 2006.183.07:34:38.57#ibcon#read 4, iclass 21, count 0 2006.183.07:34:38.57#ibcon#about to read 5, iclass 21, count 0 2006.183.07:34:38.57#ibcon#read 5, iclass 21, count 0 2006.183.07:34:38.57#ibcon#about to read 6, iclass 21, count 0 2006.183.07:34:38.57#ibcon#read 6, iclass 21, count 0 2006.183.07:34:38.57#ibcon#end of sib2, iclass 21, count 0 2006.183.07:34:38.57#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:34:38.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:34:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:34:38.57#ibcon#*before write, iclass 21, count 0 2006.183.07:34:38.57#ibcon#enter sib2, iclass 21, count 0 2006.183.07:34:38.57#ibcon#flushed, iclass 21, count 0 2006.183.07:34:38.57#ibcon#about to write, iclass 21, count 0 2006.183.07:34:38.57#ibcon#wrote, iclass 21, count 0 2006.183.07:34:38.57#ibcon#about to read 3, iclass 21, count 0 2006.183.07:34:38.57#abcon#[5=S1D000X0/0*\r\n] 2006.183.07:34:38.61#ibcon#read 3, iclass 21, count 0 2006.183.07:34:38.61#ibcon#about to read 4, iclass 21, count 0 2006.183.07:34:38.61#ibcon#read 4, iclass 21, count 0 2006.183.07:34:38.61#ibcon#about to read 5, iclass 21, count 0 2006.183.07:34:38.61#ibcon#read 5, iclass 21, count 0 2006.183.07:34:38.61#ibcon#about to read 6, iclass 21, count 0 2006.183.07:34:38.61#ibcon#read 6, iclass 21, count 0 2006.183.07:34:38.61#ibcon#end of sib2, iclass 21, count 0 2006.183.07:34:38.61#ibcon#*after write, iclass 21, count 0 2006.183.07:34:38.61#ibcon#*before return 0, iclass 21, count 0 2006.183.07:34:38.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:34:38.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:34:38.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:34:38.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:34:38.61$vc4f8/va=3,6 2006.183.07:34:38.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.07:34:38.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.07:34:38.61#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:38.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:38.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:38.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:38.67#ibcon#enter wrdev, iclass 24, count 2 2006.183.07:34:38.67#ibcon#first serial, iclass 24, count 2 2006.183.07:34:38.67#ibcon#enter sib2, iclass 24, count 2 2006.183.07:34:38.67#ibcon#flushed, iclass 24, count 2 2006.183.07:34:38.67#ibcon#about to write, iclass 24, count 2 2006.183.07:34:38.67#ibcon#wrote, iclass 24, count 2 2006.183.07:34:38.67#ibcon#about to read 3, iclass 24, count 2 2006.183.07:34:38.68#ibcon#read 3, iclass 24, count 2 2006.183.07:34:38.68#ibcon#about to read 4, iclass 24, count 2 2006.183.07:34:38.68#ibcon#read 4, iclass 24, count 2 2006.183.07:34:38.68#ibcon#about to read 5, iclass 24, count 2 2006.183.07:34:38.68#ibcon#read 5, iclass 24, count 2 2006.183.07:34:38.68#ibcon#about to read 6, iclass 24, count 2 2006.183.07:34:38.68#ibcon#read 6, iclass 24, count 2 2006.183.07:34:38.68#ibcon#end of sib2, iclass 24, count 2 2006.183.07:34:38.68#ibcon#*mode == 0, iclass 24, count 2 2006.183.07:34:38.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.07:34:38.68#ibcon#[25=AT03-06\r\n] 2006.183.07:34:38.68#ibcon#*before write, iclass 24, count 2 2006.183.07:34:38.68#ibcon#enter sib2, iclass 24, count 2 2006.183.07:34:38.68#ibcon#flushed, iclass 24, count 2 2006.183.07:34:38.68#ibcon#about to write, iclass 24, count 2 2006.183.07:34:38.68#ibcon#wrote, iclass 24, count 2 2006.183.07:34:38.68#ibcon#about to read 3, iclass 24, count 2 2006.183.07:34:38.71#ibcon#read 3, iclass 24, count 2 2006.183.07:34:38.71#ibcon#about to read 4, iclass 24, count 2 2006.183.07:34:38.71#ibcon#read 4, iclass 24, count 2 2006.183.07:34:38.71#ibcon#about to read 5, iclass 24, count 2 2006.183.07:34:38.71#ibcon#read 5, iclass 24, count 2 2006.183.07:34:38.71#ibcon#about to read 6, iclass 24, count 2 2006.183.07:34:38.71#ibcon#read 6, iclass 24, count 2 2006.183.07:34:38.71#ibcon#end of sib2, iclass 24, count 2 2006.183.07:34:38.71#ibcon#*after write, iclass 24, count 2 2006.183.07:34:38.71#ibcon#*before return 0, iclass 24, count 2 2006.183.07:34:38.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:38.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:38.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.07:34:38.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:38.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:38.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:38.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:38.83#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:34:38.83#ibcon#first serial, iclass 24, count 0 2006.183.07:34:38.83#ibcon#enter sib2, iclass 24, count 0 2006.183.07:34:38.83#ibcon#flushed, iclass 24, count 0 2006.183.07:34:38.83#ibcon#about to write, iclass 24, count 0 2006.183.07:34:38.83#ibcon#wrote, iclass 24, count 0 2006.183.07:34:38.83#ibcon#about to read 3, iclass 24, count 0 2006.183.07:34:38.85#ibcon#read 3, iclass 24, count 0 2006.183.07:34:38.85#ibcon#about to read 4, iclass 24, count 0 2006.183.07:34:38.85#ibcon#read 4, iclass 24, count 0 2006.183.07:34:38.85#ibcon#about to read 5, iclass 24, count 0 2006.183.07:34:38.85#ibcon#read 5, iclass 24, count 0 2006.183.07:34:38.85#ibcon#about to read 6, iclass 24, count 0 2006.183.07:34:38.85#ibcon#read 6, iclass 24, count 0 2006.183.07:34:38.85#ibcon#end of sib2, iclass 24, count 0 2006.183.07:34:38.85#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:34:38.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:34:38.85#ibcon#[25=USB\r\n] 2006.183.07:34:38.85#ibcon#*before write, iclass 24, count 0 2006.183.07:34:38.85#ibcon#enter sib2, iclass 24, count 0 2006.183.07:34:38.85#ibcon#flushed, iclass 24, count 0 2006.183.07:34:38.85#ibcon#about to write, iclass 24, count 0 2006.183.07:34:38.85#ibcon#wrote, iclass 24, count 0 2006.183.07:34:38.85#ibcon#about to read 3, iclass 24, count 0 2006.183.07:34:38.88#ibcon#read 3, iclass 24, count 0 2006.183.07:34:38.88#ibcon#about to read 4, iclass 24, count 0 2006.183.07:34:38.88#ibcon#read 4, iclass 24, count 0 2006.183.07:34:38.88#ibcon#about to read 5, iclass 24, count 0 2006.183.07:34:38.88#ibcon#read 5, iclass 24, count 0 2006.183.07:34:38.88#ibcon#about to read 6, iclass 24, count 0 2006.183.07:34:38.88#ibcon#read 6, iclass 24, count 0 2006.183.07:34:38.88#ibcon#end of sib2, iclass 24, count 0 2006.183.07:34:38.88#ibcon#*after write, iclass 24, count 0 2006.183.07:34:38.88#ibcon#*before return 0, iclass 24, count 0 2006.183.07:34:38.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:38.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:38.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:34:38.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:34:38.88$vc4f8/valo=4,832.99 2006.183.07:34:38.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.07:34:38.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.07:34:38.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:38.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:38.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:38.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:38.88#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:34:38.88#ibcon#first serial, iclass 26, count 0 2006.183.07:34:38.88#ibcon#enter sib2, iclass 26, count 0 2006.183.07:34:38.88#ibcon#flushed, iclass 26, count 0 2006.183.07:34:38.88#ibcon#about to write, iclass 26, count 0 2006.183.07:34:38.88#ibcon#wrote, iclass 26, count 0 2006.183.07:34:38.88#ibcon#about to read 3, iclass 26, count 0 2006.183.07:34:38.90#ibcon#read 3, iclass 26, count 0 2006.183.07:34:38.90#ibcon#about to read 4, iclass 26, count 0 2006.183.07:34:38.90#ibcon#read 4, iclass 26, count 0 2006.183.07:34:38.90#ibcon#about to read 5, iclass 26, count 0 2006.183.07:34:38.90#ibcon#read 5, iclass 26, count 0 2006.183.07:34:38.90#ibcon#about to read 6, iclass 26, count 0 2006.183.07:34:38.90#ibcon#read 6, iclass 26, count 0 2006.183.07:34:38.90#ibcon#end of sib2, iclass 26, count 0 2006.183.07:34:38.90#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:34:38.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:34:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:34:38.90#ibcon#*before write, iclass 26, count 0 2006.183.07:34:38.90#ibcon#enter sib2, iclass 26, count 0 2006.183.07:34:38.90#ibcon#flushed, iclass 26, count 0 2006.183.07:34:38.90#ibcon#about to write, iclass 26, count 0 2006.183.07:34:38.90#ibcon#wrote, iclass 26, count 0 2006.183.07:34:38.90#ibcon#about to read 3, iclass 26, count 0 2006.183.07:34:38.94#ibcon#read 3, iclass 26, count 0 2006.183.07:34:38.94#ibcon#about to read 4, iclass 26, count 0 2006.183.07:34:38.94#ibcon#read 4, iclass 26, count 0 2006.183.07:34:38.94#ibcon#about to read 5, iclass 26, count 0 2006.183.07:34:38.94#ibcon#read 5, iclass 26, count 0 2006.183.07:34:38.94#ibcon#about to read 6, iclass 26, count 0 2006.183.07:34:38.94#ibcon#read 6, iclass 26, count 0 2006.183.07:34:38.94#ibcon#end of sib2, iclass 26, count 0 2006.183.07:34:38.94#ibcon#*after write, iclass 26, count 0 2006.183.07:34:38.94#ibcon#*before return 0, iclass 26, count 0 2006.183.07:34:38.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:38.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:38.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:34:38.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:34:38.94$vc4f8/va=4,7 2006.183.07:34:38.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.07:34:38.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.07:34:38.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:38.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:39.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:39.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:39.00#ibcon#enter wrdev, iclass 28, count 2 2006.183.07:34:39.00#ibcon#first serial, iclass 28, count 2 2006.183.07:34:39.00#ibcon#enter sib2, iclass 28, count 2 2006.183.07:34:39.00#ibcon#flushed, iclass 28, count 2 2006.183.07:34:39.00#ibcon#about to write, iclass 28, count 2 2006.183.07:34:39.00#ibcon#wrote, iclass 28, count 2 2006.183.07:34:39.00#ibcon#about to read 3, iclass 28, count 2 2006.183.07:34:39.02#ibcon#read 3, iclass 28, count 2 2006.183.07:34:39.02#ibcon#about to read 4, iclass 28, count 2 2006.183.07:34:39.02#ibcon#read 4, iclass 28, count 2 2006.183.07:34:39.02#ibcon#about to read 5, iclass 28, count 2 2006.183.07:34:39.02#ibcon#read 5, iclass 28, count 2 2006.183.07:34:39.02#ibcon#about to read 6, iclass 28, count 2 2006.183.07:34:39.02#ibcon#read 6, iclass 28, count 2 2006.183.07:34:39.02#ibcon#end of sib2, iclass 28, count 2 2006.183.07:34:39.02#ibcon#*mode == 0, iclass 28, count 2 2006.183.07:34:39.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.07:34:39.02#ibcon#[25=AT04-07\r\n] 2006.183.07:34:39.02#ibcon#*before write, iclass 28, count 2 2006.183.07:34:39.02#ibcon#enter sib2, iclass 28, count 2 2006.183.07:34:39.02#ibcon#flushed, iclass 28, count 2 2006.183.07:34:39.02#ibcon#about to write, iclass 28, count 2 2006.183.07:34:39.02#ibcon#wrote, iclass 28, count 2 2006.183.07:34:39.02#ibcon#about to read 3, iclass 28, count 2 2006.183.07:34:39.05#ibcon#read 3, iclass 28, count 2 2006.183.07:34:39.05#ibcon#about to read 4, iclass 28, count 2 2006.183.07:34:39.05#ibcon#read 4, iclass 28, count 2 2006.183.07:34:39.05#ibcon#about to read 5, iclass 28, count 2 2006.183.07:34:39.05#ibcon#read 5, iclass 28, count 2 2006.183.07:34:39.05#ibcon#about to read 6, iclass 28, count 2 2006.183.07:34:39.05#ibcon#read 6, iclass 28, count 2 2006.183.07:34:39.05#ibcon#end of sib2, iclass 28, count 2 2006.183.07:34:39.05#ibcon#*after write, iclass 28, count 2 2006.183.07:34:39.05#ibcon#*before return 0, iclass 28, count 2 2006.183.07:34:39.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:39.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:39.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.07:34:39.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:39.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:39.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:39.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:39.17#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:34:39.17#ibcon#first serial, iclass 28, count 0 2006.183.07:34:39.17#ibcon#enter sib2, iclass 28, count 0 2006.183.07:34:39.17#ibcon#flushed, iclass 28, count 0 2006.183.07:34:39.17#ibcon#about to write, iclass 28, count 0 2006.183.07:34:39.17#ibcon#wrote, iclass 28, count 0 2006.183.07:34:39.17#ibcon#about to read 3, iclass 28, count 0 2006.183.07:34:39.19#ibcon#read 3, iclass 28, count 0 2006.183.07:34:39.19#ibcon#about to read 4, iclass 28, count 0 2006.183.07:34:39.19#ibcon#read 4, iclass 28, count 0 2006.183.07:34:39.19#ibcon#about to read 5, iclass 28, count 0 2006.183.07:34:39.19#ibcon#read 5, iclass 28, count 0 2006.183.07:34:39.19#ibcon#about to read 6, iclass 28, count 0 2006.183.07:34:39.19#ibcon#read 6, iclass 28, count 0 2006.183.07:34:39.19#ibcon#end of sib2, iclass 28, count 0 2006.183.07:34:39.19#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:34:39.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:34:39.19#ibcon#[25=USB\r\n] 2006.183.07:34:39.19#ibcon#*before write, iclass 28, count 0 2006.183.07:34:39.19#ibcon#enter sib2, iclass 28, count 0 2006.183.07:34:39.19#ibcon#flushed, iclass 28, count 0 2006.183.07:34:39.19#ibcon#about to write, iclass 28, count 0 2006.183.07:34:39.19#ibcon#wrote, iclass 28, count 0 2006.183.07:34:39.19#ibcon#about to read 3, iclass 28, count 0 2006.183.07:34:39.22#ibcon#read 3, iclass 28, count 0 2006.183.07:34:39.22#ibcon#about to read 4, iclass 28, count 0 2006.183.07:34:39.22#ibcon#read 4, iclass 28, count 0 2006.183.07:34:39.22#ibcon#about to read 5, iclass 28, count 0 2006.183.07:34:39.22#ibcon#read 5, iclass 28, count 0 2006.183.07:34:39.22#ibcon#about to read 6, iclass 28, count 0 2006.183.07:34:39.22#ibcon#read 6, iclass 28, count 0 2006.183.07:34:39.22#ibcon#end of sib2, iclass 28, count 0 2006.183.07:34:39.22#ibcon#*after write, iclass 28, count 0 2006.183.07:34:39.22#ibcon#*before return 0, iclass 28, count 0 2006.183.07:34:39.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:39.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:39.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:34:39.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:34:39.22$vc4f8/valo=5,652.99 2006.183.07:34:39.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.07:34:39.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.07:34:39.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:39.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:39.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:39.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:39.22#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:34:39.22#ibcon#first serial, iclass 30, count 0 2006.183.07:34:39.22#ibcon#enter sib2, iclass 30, count 0 2006.183.07:34:39.22#ibcon#flushed, iclass 30, count 0 2006.183.07:34:39.22#ibcon#about to write, iclass 30, count 0 2006.183.07:34:39.22#ibcon#wrote, iclass 30, count 0 2006.183.07:34:39.22#ibcon#about to read 3, iclass 30, count 0 2006.183.07:34:39.24#ibcon#read 3, iclass 30, count 0 2006.183.07:34:39.24#ibcon#about to read 4, iclass 30, count 0 2006.183.07:34:39.24#ibcon#read 4, iclass 30, count 0 2006.183.07:34:39.24#ibcon#about to read 5, iclass 30, count 0 2006.183.07:34:39.24#ibcon#read 5, iclass 30, count 0 2006.183.07:34:39.24#ibcon#about to read 6, iclass 30, count 0 2006.183.07:34:39.24#ibcon#read 6, iclass 30, count 0 2006.183.07:34:39.24#ibcon#end of sib2, iclass 30, count 0 2006.183.07:34:39.24#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:34:39.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:34:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:34:39.24#ibcon#*before write, iclass 30, count 0 2006.183.07:34:39.24#ibcon#enter sib2, iclass 30, count 0 2006.183.07:34:39.24#ibcon#flushed, iclass 30, count 0 2006.183.07:34:39.24#ibcon#about to write, iclass 30, count 0 2006.183.07:34:39.24#ibcon#wrote, iclass 30, count 0 2006.183.07:34:39.24#ibcon#about to read 3, iclass 30, count 0 2006.183.07:34:39.28#ibcon#read 3, iclass 30, count 0 2006.183.07:34:39.28#ibcon#about to read 4, iclass 30, count 0 2006.183.07:34:39.28#ibcon#read 4, iclass 30, count 0 2006.183.07:34:39.28#ibcon#about to read 5, iclass 30, count 0 2006.183.07:34:39.28#ibcon#read 5, iclass 30, count 0 2006.183.07:34:39.28#ibcon#about to read 6, iclass 30, count 0 2006.183.07:34:39.28#ibcon#read 6, iclass 30, count 0 2006.183.07:34:39.28#ibcon#end of sib2, iclass 30, count 0 2006.183.07:34:39.28#ibcon#*after write, iclass 30, count 0 2006.183.07:34:39.28#ibcon#*before return 0, iclass 30, count 0 2006.183.07:34:39.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:39.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:39.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:34:39.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:34:39.28$vc4f8/va=5,7 2006.183.07:34:39.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.07:34:39.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.07:34:39.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:39.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:39.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:39.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:39.34#ibcon#enter wrdev, iclass 32, count 2 2006.183.07:34:39.34#ibcon#first serial, iclass 32, count 2 2006.183.07:34:39.34#ibcon#enter sib2, iclass 32, count 2 2006.183.07:34:39.34#ibcon#flushed, iclass 32, count 2 2006.183.07:34:39.34#ibcon#about to write, iclass 32, count 2 2006.183.07:34:39.34#ibcon#wrote, iclass 32, count 2 2006.183.07:34:39.34#ibcon#about to read 3, iclass 32, count 2 2006.183.07:34:39.36#ibcon#read 3, iclass 32, count 2 2006.183.07:34:39.36#ibcon#about to read 4, iclass 32, count 2 2006.183.07:34:39.36#ibcon#read 4, iclass 32, count 2 2006.183.07:34:39.36#ibcon#about to read 5, iclass 32, count 2 2006.183.07:34:39.36#ibcon#read 5, iclass 32, count 2 2006.183.07:34:39.36#ibcon#about to read 6, iclass 32, count 2 2006.183.07:34:39.36#ibcon#read 6, iclass 32, count 2 2006.183.07:34:39.36#ibcon#end of sib2, iclass 32, count 2 2006.183.07:34:39.36#ibcon#*mode == 0, iclass 32, count 2 2006.183.07:34:39.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.07:34:39.36#ibcon#[25=AT05-07\r\n] 2006.183.07:34:39.36#ibcon#*before write, iclass 32, count 2 2006.183.07:34:39.36#ibcon#enter sib2, iclass 32, count 2 2006.183.07:34:39.36#ibcon#flushed, iclass 32, count 2 2006.183.07:34:39.36#ibcon#about to write, iclass 32, count 2 2006.183.07:34:39.36#ibcon#wrote, iclass 32, count 2 2006.183.07:34:39.36#ibcon#about to read 3, iclass 32, count 2 2006.183.07:34:39.39#ibcon#read 3, iclass 32, count 2 2006.183.07:34:39.39#ibcon#about to read 4, iclass 32, count 2 2006.183.07:34:39.39#ibcon#read 4, iclass 32, count 2 2006.183.07:34:39.39#ibcon#about to read 5, iclass 32, count 2 2006.183.07:34:39.39#ibcon#read 5, iclass 32, count 2 2006.183.07:34:39.39#ibcon#about to read 6, iclass 32, count 2 2006.183.07:34:39.39#ibcon#read 6, iclass 32, count 2 2006.183.07:34:39.39#ibcon#end of sib2, iclass 32, count 2 2006.183.07:34:39.39#ibcon#*after write, iclass 32, count 2 2006.183.07:34:39.39#ibcon#*before return 0, iclass 32, count 2 2006.183.07:34:39.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:39.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:39.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.07:34:39.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:39.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:39.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:39.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:39.51#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:34:39.51#ibcon#first serial, iclass 32, count 0 2006.183.07:34:39.51#ibcon#enter sib2, iclass 32, count 0 2006.183.07:34:39.51#ibcon#flushed, iclass 32, count 0 2006.183.07:34:39.51#ibcon#about to write, iclass 32, count 0 2006.183.07:34:39.51#ibcon#wrote, iclass 32, count 0 2006.183.07:34:39.51#ibcon#about to read 3, iclass 32, count 0 2006.183.07:34:39.53#ibcon#read 3, iclass 32, count 0 2006.183.07:34:39.53#ibcon#about to read 4, iclass 32, count 0 2006.183.07:34:39.53#ibcon#read 4, iclass 32, count 0 2006.183.07:34:39.53#ibcon#about to read 5, iclass 32, count 0 2006.183.07:34:39.53#ibcon#read 5, iclass 32, count 0 2006.183.07:34:39.53#ibcon#about to read 6, iclass 32, count 0 2006.183.07:34:39.53#ibcon#read 6, iclass 32, count 0 2006.183.07:34:39.53#ibcon#end of sib2, iclass 32, count 0 2006.183.07:34:39.53#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:34:39.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:34:39.53#ibcon#[25=USB\r\n] 2006.183.07:34:39.53#ibcon#*before write, iclass 32, count 0 2006.183.07:34:39.53#ibcon#enter sib2, iclass 32, count 0 2006.183.07:34:39.53#ibcon#flushed, iclass 32, count 0 2006.183.07:34:39.53#ibcon#about to write, iclass 32, count 0 2006.183.07:34:39.53#ibcon#wrote, iclass 32, count 0 2006.183.07:34:39.53#ibcon#about to read 3, iclass 32, count 0 2006.183.07:34:39.56#ibcon#read 3, iclass 32, count 0 2006.183.07:34:39.56#ibcon#about to read 4, iclass 32, count 0 2006.183.07:34:39.56#ibcon#read 4, iclass 32, count 0 2006.183.07:34:39.56#ibcon#about to read 5, iclass 32, count 0 2006.183.07:34:39.56#ibcon#read 5, iclass 32, count 0 2006.183.07:34:39.56#ibcon#about to read 6, iclass 32, count 0 2006.183.07:34:39.56#ibcon#read 6, iclass 32, count 0 2006.183.07:34:39.56#ibcon#end of sib2, iclass 32, count 0 2006.183.07:34:39.56#ibcon#*after write, iclass 32, count 0 2006.183.07:34:39.56#ibcon#*before return 0, iclass 32, count 0 2006.183.07:34:39.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:39.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:39.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:34:39.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:34:39.56$vc4f8/valo=6,772.99 2006.183.07:34:39.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.07:34:39.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.07:34:39.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:39.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:39.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:39.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:39.56#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:34:39.56#ibcon#first serial, iclass 34, count 0 2006.183.07:34:39.56#ibcon#enter sib2, iclass 34, count 0 2006.183.07:34:39.56#ibcon#flushed, iclass 34, count 0 2006.183.07:34:39.56#ibcon#about to write, iclass 34, count 0 2006.183.07:34:39.56#ibcon#wrote, iclass 34, count 0 2006.183.07:34:39.56#ibcon#about to read 3, iclass 34, count 0 2006.183.07:34:39.58#ibcon#read 3, iclass 34, count 0 2006.183.07:34:39.58#ibcon#about to read 4, iclass 34, count 0 2006.183.07:34:39.58#ibcon#read 4, iclass 34, count 0 2006.183.07:34:39.58#ibcon#about to read 5, iclass 34, count 0 2006.183.07:34:39.58#ibcon#read 5, iclass 34, count 0 2006.183.07:34:39.58#ibcon#about to read 6, iclass 34, count 0 2006.183.07:34:39.58#ibcon#read 6, iclass 34, count 0 2006.183.07:34:39.58#ibcon#end of sib2, iclass 34, count 0 2006.183.07:34:39.58#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:34:39.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:34:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:34:39.58#ibcon#*before write, iclass 34, count 0 2006.183.07:34:39.58#ibcon#enter sib2, iclass 34, count 0 2006.183.07:34:39.58#ibcon#flushed, iclass 34, count 0 2006.183.07:34:39.58#ibcon#about to write, iclass 34, count 0 2006.183.07:34:39.58#ibcon#wrote, iclass 34, count 0 2006.183.07:34:39.58#ibcon#about to read 3, iclass 34, count 0 2006.183.07:34:39.62#ibcon#read 3, iclass 34, count 0 2006.183.07:34:39.62#ibcon#about to read 4, iclass 34, count 0 2006.183.07:34:39.62#ibcon#read 4, iclass 34, count 0 2006.183.07:34:39.62#ibcon#about to read 5, iclass 34, count 0 2006.183.07:34:39.62#ibcon#read 5, iclass 34, count 0 2006.183.07:34:39.62#ibcon#about to read 6, iclass 34, count 0 2006.183.07:34:39.62#ibcon#read 6, iclass 34, count 0 2006.183.07:34:39.62#ibcon#end of sib2, iclass 34, count 0 2006.183.07:34:39.62#ibcon#*after write, iclass 34, count 0 2006.183.07:34:39.62#ibcon#*before return 0, iclass 34, count 0 2006.183.07:34:39.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:39.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:39.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:34:39.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:34:39.62$vc4f8/va=6,6 2006.183.07:34:39.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.07:34:39.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.07:34:39.62#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:39.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:34:39.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:34:39.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:34:39.68#ibcon#enter wrdev, iclass 36, count 2 2006.183.07:34:39.68#ibcon#first serial, iclass 36, count 2 2006.183.07:34:39.68#ibcon#enter sib2, iclass 36, count 2 2006.183.07:34:39.68#ibcon#flushed, iclass 36, count 2 2006.183.07:34:39.68#ibcon#about to write, iclass 36, count 2 2006.183.07:34:39.68#ibcon#wrote, iclass 36, count 2 2006.183.07:34:39.68#ibcon#about to read 3, iclass 36, count 2 2006.183.07:34:39.70#ibcon#read 3, iclass 36, count 2 2006.183.07:34:39.70#ibcon#about to read 4, iclass 36, count 2 2006.183.07:34:39.70#ibcon#read 4, iclass 36, count 2 2006.183.07:34:39.70#ibcon#about to read 5, iclass 36, count 2 2006.183.07:34:39.70#ibcon#read 5, iclass 36, count 2 2006.183.07:34:39.70#ibcon#about to read 6, iclass 36, count 2 2006.183.07:34:39.70#ibcon#read 6, iclass 36, count 2 2006.183.07:34:39.70#ibcon#end of sib2, iclass 36, count 2 2006.183.07:34:39.70#ibcon#*mode == 0, iclass 36, count 2 2006.183.07:34:39.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.07:34:39.70#ibcon#[25=AT06-06\r\n] 2006.183.07:34:39.70#ibcon#*before write, iclass 36, count 2 2006.183.07:34:39.70#ibcon#enter sib2, iclass 36, count 2 2006.183.07:34:39.70#ibcon#flushed, iclass 36, count 2 2006.183.07:34:39.70#ibcon#about to write, iclass 36, count 2 2006.183.07:34:39.70#ibcon#wrote, iclass 36, count 2 2006.183.07:34:39.70#ibcon#about to read 3, iclass 36, count 2 2006.183.07:34:39.73#ibcon#read 3, iclass 36, count 2 2006.183.07:34:39.73#ibcon#about to read 4, iclass 36, count 2 2006.183.07:34:39.73#ibcon#read 4, iclass 36, count 2 2006.183.07:34:39.73#ibcon#about to read 5, iclass 36, count 2 2006.183.07:34:39.73#ibcon#read 5, iclass 36, count 2 2006.183.07:34:39.73#ibcon#about to read 6, iclass 36, count 2 2006.183.07:34:39.73#ibcon#read 6, iclass 36, count 2 2006.183.07:34:39.73#ibcon#end of sib2, iclass 36, count 2 2006.183.07:34:39.73#ibcon#*after write, iclass 36, count 2 2006.183.07:34:39.73#ibcon#*before return 0, iclass 36, count 2 2006.183.07:34:39.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:34:39.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:34:39.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.07:34:39.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:39.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:34:39.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:34:39.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:34:39.85#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:34:39.85#ibcon#first serial, iclass 36, count 0 2006.183.07:34:39.85#ibcon#enter sib2, iclass 36, count 0 2006.183.07:34:39.85#ibcon#flushed, iclass 36, count 0 2006.183.07:34:39.85#ibcon#about to write, iclass 36, count 0 2006.183.07:34:39.85#ibcon#wrote, iclass 36, count 0 2006.183.07:34:39.85#ibcon#about to read 3, iclass 36, count 0 2006.183.07:34:39.87#ibcon#read 3, iclass 36, count 0 2006.183.07:34:39.87#ibcon#about to read 4, iclass 36, count 0 2006.183.07:34:39.87#ibcon#read 4, iclass 36, count 0 2006.183.07:34:39.87#ibcon#about to read 5, iclass 36, count 0 2006.183.07:34:39.87#ibcon#read 5, iclass 36, count 0 2006.183.07:34:39.87#ibcon#about to read 6, iclass 36, count 0 2006.183.07:34:39.87#ibcon#read 6, iclass 36, count 0 2006.183.07:34:39.87#ibcon#end of sib2, iclass 36, count 0 2006.183.07:34:39.87#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:34:39.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:34:39.87#ibcon#[25=USB\r\n] 2006.183.07:34:39.87#ibcon#*before write, iclass 36, count 0 2006.183.07:34:39.87#ibcon#enter sib2, iclass 36, count 0 2006.183.07:34:39.87#ibcon#flushed, iclass 36, count 0 2006.183.07:34:39.87#ibcon#about to write, iclass 36, count 0 2006.183.07:34:39.87#ibcon#wrote, iclass 36, count 0 2006.183.07:34:39.87#ibcon#about to read 3, iclass 36, count 0 2006.183.07:34:39.90#ibcon#read 3, iclass 36, count 0 2006.183.07:34:39.90#ibcon#about to read 4, iclass 36, count 0 2006.183.07:34:39.90#ibcon#read 4, iclass 36, count 0 2006.183.07:34:39.90#ibcon#about to read 5, iclass 36, count 0 2006.183.07:34:39.90#ibcon#read 5, iclass 36, count 0 2006.183.07:34:39.90#ibcon#about to read 6, iclass 36, count 0 2006.183.07:34:39.90#ibcon#read 6, iclass 36, count 0 2006.183.07:34:39.90#ibcon#end of sib2, iclass 36, count 0 2006.183.07:34:39.90#ibcon#*after write, iclass 36, count 0 2006.183.07:34:39.90#ibcon#*before return 0, iclass 36, count 0 2006.183.07:34:39.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:34:39.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:34:39.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:34:39.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:34:39.90$vc4f8/valo=7,832.99 2006.183.07:34:39.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.07:34:39.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.07:34:39.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:39.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:34:39.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:34:39.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:34:39.90#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:34:39.90#ibcon#first serial, iclass 38, count 0 2006.183.07:34:39.90#ibcon#enter sib2, iclass 38, count 0 2006.183.07:34:39.90#ibcon#flushed, iclass 38, count 0 2006.183.07:34:39.90#ibcon#about to write, iclass 38, count 0 2006.183.07:34:39.90#ibcon#wrote, iclass 38, count 0 2006.183.07:34:39.90#ibcon#about to read 3, iclass 38, count 0 2006.183.07:34:39.92#ibcon#read 3, iclass 38, count 0 2006.183.07:34:39.92#ibcon#about to read 4, iclass 38, count 0 2006.183.07:34:39.92#ibcon#read 4, iclass 38, count 0 2006.183.07:34:39.92#ibcon#about to read 5, iclass 38, count 0 2006.183.07:34:39.92#ibcon#read 5, iclass 38, count 0 2006.183.07:34:39.92#ibcon#about to read 6, iclass 38, count 0 2006.183.07:34:39.92#ibcon#read 6, iclass 38, count 0 2006.183.07:34:39.92#ibcon#end of sib2, iclass 38, count 0 2006.183.07:34:39.92#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:34:39.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:34:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:34:39.92#ibcon#*before write, iclass 38, count 0 2006.183.07:34:39.92#ibcon#enter sib2, iclass 38, count 0 2006.183.07:34:39.92#ibcon#flushed, iclass 38, count 0 2006.183.07:34:39.92#ibcon#about to write, iclass 38, count 0 2006.183.07:34:39.92#ibcon#wrote, iclass 38, count 0 2006.183.07:34:39.92#ibcon#about to read 3, iclass 38, count 0 2006.183.07:34:39.96#ibcon#read 3, iclass 38, count 0 2006.183.07:34:39.96#ibcon#about to read 4, iclass 38, count 0 2006.183.07:34:39.96#ibcon#read 4, iclass 38, count 0 2006.183.07:34:39.96#ibcon#about to read 5, iclass 38, count 0 2006.183.07:34:39.96#ibcon#read 5, iclass 38, count 0 2006.183.07:34:39.96#ibcon#about to read 6, iclass 38, count 0 2006.183.07:34:39.96#ibcon#read 6, iclass 38, count 0 2006.183.07:34:39.96#ibcon#end of sib2, iclass 38, count 0 2006.183.07:34:39.96#ibcon#*after write, iclass 38, count 0 2006.183.07:34:39.96#ibcon#*before return 0, iclass 38, count 0 2006.183.07:34:39.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:34:39.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:34:39.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:34:39.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:34:39.96$vc4f8/va=7,6 2006.183.07:34:39.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.07:34:39.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.07:34:39.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:39.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:34:40.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:34:40.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:34:40.03#ibcon#enter wrdev, iclass 40, count 2 2006.183.07:34:40.03#ibcon#first serial, iclass 40, count 2 2006.183.07:34:40.03#ibcon#enter sib2, iclass 40, count 2 2006.183.07:34:40.03#ibcon#flushed, iclass 40, count 2 2006.183.07:34:40.03#ibcon#about to write, iclass 40, count 2 2006.183.07:34:40.03#ibcon#wrote, iclass 40, count 2 2006.183.07:34:40.03#ibcon#about to read 3, iclass 40, count 2 2006.183.07:34:40.04#ibcon#read 3, iclass 40, count 2 2006.183.07:34:40.04#ibcon#about to read 4, iclass 40, count 2 2006.183.07:34:40.04#ibcon#read 4, iclass 40, count 2 2006.183.07:34:40.04#ibcon#about to read 5, iclass 40, count 2 2006.183.07:34:40.04#ibcon#read 5, iclass 40, count 2 2006.183.07:34:40.04#ibcon#about to read 6, iclass 40, count 2 2006.183.07:34:40.04#ibcon#read 6, iclass 40, count 2 2006.183.07:34:40.04#ibcon#end of sib2, iclass 40, count 2 2006.183.07:34:40.04#ibcon#*mode == 0, iclass 40, count 2 2006.183.07:34:40.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.07:34:40.04#ibcon#[25=AT07-06\r\n] 2006.183.07:34:40.04#ibcon#*before write, iclass 40, count 2 2006.183.07:34:40.04#ibcon#enter sib2, iclass 40, count 2 2006.183.07:34:40.04#ibcon#flushed, iclass 40, count 2 2006.183.07:34:40.04#ibcon#about to write, iclass 40, count 2 2006.183.07:34:40.04#ibcon#wrote, iclass 40, count 2 2006.183.07:34:40.04#ibcon#about to read 3, iclass 40, count 2 2006.183.07:34:40.07#ibcon#read 3, iclass 40, count 2 2006.183.07:34:40.07#ibcon#about to read 4, iclass 40, count 2 2006.183.07:34:40.07#ibcon#read 4, iclass 40, count 2 2006.183.07:34:40.07#ibcon#about to read 5, iclass 40, count 2 2006.183.07:34:40.07#ibcon#read 5, iclass 40, count 2 2006.183.07:34:40.07#ibcon#about to read 6, iclass 40, count 2 2006.183.07:34:40.07#ibcon#read 6, iclass 40, count 2 2006.183.07:34:40.07#ibcon#end of sib2, iclass 40, count 2 2006.183.07:34:40.07#ibcon#*after write, iclass 40, count 2 2006.183.07:34:40.07#ibcon#*before return 0, iclass 40, count 2 2006.183.07:34:40.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:34:40.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:34:40.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.07:34:40.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:40.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:34:40.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:34:40.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:34:40.19#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:34:40.19#ibcon#first serial, iclass 40, count 0 2006.183.07:34:40.19#ibcon#enter sib2, iclass 40, count 0 2006.183.07:34:40.19#ibcon#flushed, iclass 40, count 0 2006.183.07:34:40.19#ibcon#about to write, iclass 40, count 0 2006.183.07:34:40.19#ibcon#wrote, iclass 40, count 0 2006.183.07:34:40.19#ibcon#about to read 3, iclass 40, count 0 2006.183.07:34:40.21#ibcon#read 3, iclass 40, count 0 2006.183.07:34:40.21#ibcon#about to read 4, iclass 40, count 0 2006.183.07:34:40.21#ibcon#read 4, iclass 40, count 0 2006.183.07:34:40.21#ibcon#about to read 5, iclass 40, count 0 2006.183.07:34:40.21#ibcon#read 5, iclass 40, count 0 2006.183.07:34:40.21#ibcon#about to read 6, iclass 40, count 0 2006.183.07:34:40.21#ibcon#read 6, iclass 40, count 0 2006.183.07:34:40.21#ibcon#end of sib2, iclass 40, count 0 2006.183.07:34:40.21#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:34:40.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:34:40.21#ibcon#[25=USB\r\n] 2006.183.07:34:40.21#ibcon#*before write, iclass 40, count 0 2006.183.07:34:40.21#ibcon#enter sib2, iclass 40, count 0 2006.183.07:34:40.21#ibcon#flushed, iclass 40, count 0 2006.183.07:34:40.21#ibcon#about to write, iclass 40, count 0 2006.183.07:34:40.21#ibcon#wrote, iclass 40, count 0 2006.183.07:34:40.21#ibcon#about to read 3, iclass 40, count 0 2006.183.07:34:40.24#ibcon#read 3, iclass 40, count 0 2006.183.07:34:40.24#ibcon#about to read 4, iclass 40, count 0 2006.183.07:34:40.24#ibcon#read 4, iclass 40, count 0 2006.183.07:34:40.24#ibcon#about to read 5, iclass 40, count 0 2006.183.07:34:40.24#ibcon#read 5, iclass 40, count 0 2006.183.07:34:40.24#ibcon#about to read 6, iclass 40, count 0 2006.183.07:34:40.24#ibcon#read 6, iclass 40, count 0 2006.183.07:34:40.24#ibcon#end of sib2, iclass 40, count 0 2006.183.07:34:40.24#ibcon#*after write, iclass 40, count 0 2006.183.07:34:40.24#ibcon#*before return 0, iclass 40, count 0 2006.183.07:34:40.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:34:40.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:34:40.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:34:40.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:34:40.24$vc4f8/valo=8,852.99 2006.183.07:34:40.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.07:34:40.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.07:34:40.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:40.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:34:40.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:34:40.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:34:40.25#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:34:40.25#ibcon#first serial, iclass 4, count 0 2006.183.07:34:40.25#ibcon#enter sib2, iclass 4, count 0 2006.183.07:34:40.25#ibcon#flushed, iclass 4, count 0 2006.183.07:34:40.25#ibcon#about to write, iclass 4, count 0 2006.183.07:34:40.25#ibcon#wrote, iclass 4, count 0 2006.183.07:34:40.25#ibcon#about to read 3, iclass 4, count 0 2006.183.07:34:40.26#ibcon#read 3, iclass 4, count 0 2006.183.07:34:40.26#ibcon#about to read 4, iclass 4, count 0 2006.183.07:34:40.26#ibcon#read 4, iclass 4, count 0 2006.183.07:34:40.26#ibcon#about to read 5, iclass 4, count 0 2006.183.07:34:40.26#ibcon#read 5, iclass 4, count 0 2006.183.07:34:40.26#ibcon#about to read 6, iclass 4, count 0 2006.183.07:34:40.26#ibcon#read 6, iclass 4, count 0 2006.183.07:34:40.26#ibcon#end of sib2, iclass 4, count 0 2006.183.07:34:40.26#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:34:40.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:34:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:34:40.26#ibcon#*before write, iclass 4, count 0 2006.183.07:34:40.26#ibcon#enter sib2, iclass 4, count 0 2006.183.07:34:40.26#ibcon#flushed, iclass 4, count 0 2006.183.07:34:40.26#ibcon#about to write, iclass 4, count 0 2006.183.07:34:40.26#ibcon#wrote, iclass 4, count 0 2006.183.07:34:40.26#ibcon#about to read 3, iclass 4, count 0 2006.183.07:34:40.30#ibcon#read 3, iclass 4, count 0 2006.183.07:34:40.30#ibcon#about to read 4, iclass 4, count 0 2006.183.07:34:40.30#ibcon#read 4, iclass 4, count 0 2006.183.07:34:40.30#ibcon#about to read 5, iclass 4, count 0 2006.183.07:34:40.30#ibcon#read 5, iclass 4, count 0 2006.183.07:34:40.30#ibcon#about to read 6, iclass 4, count 0 2006.183.07:34:40.30#ibcon#read 6, iclass 4, count 0 2006.183.07:34:40.30#ibcon#end of sib2, iclass 4, count 0 2006.183.07:34:40.30#ibcon#*after write, iclass 4, count 0 2006.183.07:34:40.30#ibcon#*before return 0, iclass 4, count 0 2006.183.07:34:40.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:34:40.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:34:40.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:34:40.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:34:40.30$vc4f8/va=8,7 2006.183.07:34:40.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.07:34:40.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.07:34:40.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:40.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:34:40.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:34:40.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:34:40.36#ibcon#enter wrdev, iclass 6, count 2 2006.183.07:34:40.36#ibcon#first serial, iclass 6, count 2 2006.183.07:34:40.36#ibcon#enter sib2, iclass 6, count 2 2006.183.07:34:40.36#ibcon#flushed, iclass 6, count 2 2006.183.07:34:40.36#ibcon#about to write, iclass 6, count 2 2006.183.07:34:40.36#ibcon#wrote, iclass 6, count 2 2006.183.07:34:40.36#ibcon#about to read 3, iclass 6, count 2 2006.183.07:34:40.38#ibcon#read 3, iclass 6, count 2 2006.183.07:34:40.38#ibcon#about to read 4, iclass 6, count 2 2006.183.07:34:40.38#ibcon#read 4, iclass 6, count 2 2006.183.07:34:40.38#ibcon#about to read 5, iclass 6, count 2 2006.183.07:34:40.38#ibcon#read 5, iclass 6, count 2 2006.183.07:34:40.38#ibcon#about to read 6, iclass 6, count 2 2006.183.07:34:40.38#ibcon#read 6, iclass 6, count 2 2006.183.07:34:40.38#ibcon#end of sib2, iclass 6, count 2 2006.183.07:34:40.38#ibcon#*mode == 0, iclass 6, count 2 2006.183.07:34:40.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.07:34:40.38#ibcon#[25=AT08-07\r\n] 2006.183.07:34:40.38#ibcon#*before write, iclass 6, count 2 2006.183.07:34:40.38#ibcon#enter sib2, iclass 6, count 2 2006.183.07:34:40.38#ibcon#flushed, iclass 6, count 2 2006.183.07:34:40.38#ibcon#about to write, iclass 6, count 2 2006.183.07:34:40.38#ibcon#wrote, iclass 6, count 2 2006.183.07:34:40.38#ibcon#about to read 3, iclass 6, count 2 2006.183.07:34:40.41#ibcon#read 3, iclass 6, count 2 2006.183.07:34:40.41#ibcon#about to read 4, iclass 6, count 2 2006.183.07:34:40.41#ibcon#read 4, iclass 6, count 2 2006.183.07:34:40.41#ibcon#about to read 5, iclass 6, count 2 2006.183.07:34:40.41#ibcon#read 5, iclass 6, count 2 2006.183.07:34:40.41#ibcon#about to read 6, iclass 6, count 2 2006.183.07:34:40.41#ibcon#read 6, iclass 6, count 2 2006.183.07:34:40.41#ibcon#end of sib2, iclass 6, count 2 2006.183.07:34:40.41#ibcon#*after write, iclass 6, count 2 2006.183.07:34:40.41#ibcon#*before return 0, iclass 6, count 2 2006.183.07:34:40.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:34:40.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:34:40.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.07:34:40.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:40.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:34:40.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:34:40.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:34:40.53#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:34:40.53#ibcon#first serial, iclass 6, count 0 2006.183.07:34:40.53#ibcon#enter sib2, iclass 6, count 0 2006.183.07:34:40.53#ibcon#flushed, iclass 6, count 0 2006.183.07:34:40.53#ibcon#about to write, iclass 6, count 0 2006.183.07:34:40.53#ibcon#wrote, iclass 6, count 0 2006.183.07:34:40.53#ibcon#about to read 3, iclass 6, count 0 2006.183.07:34:40.55#ibcon#read 3, iclass 6, count 0 2006.183.07:34:40.55#ibcon#about to read 4, iclass 6, count 0 2006.183.07:34:40.55#ibcon#read 4, iclass 6, count 0 2006.183.07:34:40.55#ibcon#about to read 5, iclass 6, count 0 2006.183.07:34:40.55#ibcon#read 5, iclass 6, count 0 2006.183.07:34:40.55#ibcon#about to read 6, iclass 6, count 0 2006.183.07:34:40.55#ibcon#read 6, iclass 6, count 0 2006.183.07:34:40.55#ibcon#end of sib2, iclass 6, count 0 2006.183.07:34:40.55#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:34:40.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:34:40.55#ibcon#[25=USB\r\n] 2006.183.07:34:40.55#ibcon#*before write, iclass 6, count 0 2006.183.07:34:40.55#ibcon#enter sib2, iclass 6, count 0 2006.183.07:34:40.55#ibcon#flushed, iclass 6, count 0 2006.183.07:34:40.55#ibcon#about to write, iclass 6, count 0 2006.183.07:34:40.55#ibcon#wrote, iclass 6, count 0 2006.183.07:34:40.55#ibcon#about to read 3, iclass 6, count 0 2006.183.07:34:40.58#ibcon#read 3, iclass 6, count 0 2006.183.07:34:40.58#ibcon#about to read 4, iclass 6, count 0 2006.183.07:34:40.58#ibcon#read 4, iclass 6, count 0 2006.183.07:34:40.58#ibcon#about to read 5, iclass 6, count 0 2006.183.07:34:40.58#ibcon#read 5, iclass 6, count 0 2006.183.07:34:40.58#ibcon#about to read 6, iclass 6, count 0 2006.183.07:34:40.58#ibcon#read 6, iclass 6, count 0 2006.183.07:34:40.58#ibcon#end of sib2, iclass 6, count 0 2006.183.07:34:40.58#ibcon#*after write, iclass 6, count 0 2006.183.07:34:40.58#ibcon#*before return 0, iclass 6, count 0 2006.183.07:34:40.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:34:40.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:34:40.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:34:40.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:34:40.58$vc4f8/vblo=1,632.99 2006.183.07:34:40.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.07:34:40.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.07:34:40.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:40.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:40.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:40.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:40.58#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:34:40.58#ibcon#first serial, iclass 10, count 0 2006.183.07:34:40.58#ibcon#enter sib2, iclass 10, count 0 2006.183.07:34:40.58#ibcon#flushed, iclass 10, count 0 2006.183.07:34:40.58#ibcon#about to write, iclass 10, count 0 2006.183.07:34:40.58#ibcon#wrote, iclass 10, count 0 2006.183.07:34:40.58#ibcon#about to read 3, iclass 10, count 0 2006.183.07:34:40.60#ibcon#read 3, iclass 10, count 0 2006.183.07:34:40.60#ibcon#about to read 4, iclass 10, count 0 2006.183.07:34:40.60#ibcon#read 4, iclass 10, count 0 2006.183.07:34:40.60#ibcon#about to read 5, iclass 10, count 0 2006.183.07:34:40.60#ibcon#read 5, iclass 10, count 0 2006.183.07:34:40.60#ibcon#about to read 6, iclass 10, count 0 2006.183.07:34:40.60#ibcon#read 6, iclass 10, count 0 2006.183.07:34:40.60#ibcon#end of sib2, iclass 10, count 0 2006.183.07:34:40.60#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:34:40.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:34:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:34:40.60#ibcon#*before write, iclass 10, count 0 2006.183.07:34:40.60#ibcon#enter sib2, iclass 10, count 0 2006.183.07:34:40.60#ibcon#flushed, iclass 10, count 0 2006.183.07:34:40.60#ibcon#about to write, iclass 10, count 0 2006.183.07:34:40.60#ibcon#wrote, iclass 10, count 0 2006.183.07:34:40.60#ibcon#about to read 3, iclass 10, count 0 2006.183.07:34:40.64#ibcon#read 3, iclass 10, count 0 2006.183.07:34:40.64#ibcon#about to read 4, iclass 10, count 0 2006.183.07:34:40.64#ibcon#read 4, iclass 10, count 0 2006.183.07:34:40.64#ibcon#about to read 5, iclass 10, count 0 2006.183.07:34:40.64#ibcon#read 5, iclass 10, count 0 2006.183.07:34:40.64#ibcon#about to read 6, iclass 10, count 0 2006.183.07:34:40.64#ibcon#read 6, iclass 10, count 0 2006.183.07:34:40.64#ibcon#end of sib2, iclass 10, count 0 2006.183.07:34:40.64#ibcon#*after write, iclass 10, count 0 2006.183.07:34:40.64#ibcon#*before return 0, iclass 10, count 0 2006.183.07:34:40.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:40.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:34:40.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:34:40.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:34:40.64$vc4f8/vb=1,4 2006.183.07:34:40.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.07:34:40.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.07:34:40.64#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:40.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:40.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:40.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:40.64#ibcon#enter wrdev, iclass 12, count 2 2006.183.07:34:40.64#ibcon#first serial, iclass 12, count 2 2006.183.07:34:40.64#ibcon#enter sib2, iclass 12, count 2 2006.183.07:34:40.64#ibcon#flushed, iclass 12, count 2 2006.183.07:34:40.64#ibcon#about to write, iclass 12, count 2 2006.183.07:34:40.64#ibcon#wrote, iclass 12, count 2 2006.183.07:34:40.64#ibcon#about to read 3, iclass 12, count 2 2006.183.07:34:40.66#ibcon#read 3, iclass 12, count 2 2006.183.07:34:40.66#ibcon#about to read 4, iclass 12, count 2 2006.183.07:34:40.66#ibcon#read 4, iclass 12, count 2 2006.183.07:34:40.66#ibcon#about to read 5, iclass 12, count 2 2006.183.07:34:40.66#ibcon#read 5, iclass 12, count 2 2006.183.07:34:40.66#ibcon#about to read 6, iclass 12, count 2 2006.183.07:34:40.66#ibcon#read 6, iclass 12, count 2 2006.183.07:34:40.66#ibcon#end of sib2, iclass 12, count 2 2006.183.07:34:40.66#ibcon#*mode == 0, iclass 12, count 2 2006.183.07:34:40.66#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.07:34:40.66#ibcon#[27=AT01-04\r\n] 2006.183.07:34:40.66#ibcon#*before write, iclass 12, count 2 2006.183.07:34:40.66#ibcon#enter sib2, iclass 12, count 2 2006.183.07:34:40.66#ibcon#flushed, iclass 12, count 2 2006.183.07:34:40.66#ibcon#about to write, iclass 12, count 2 2006.183.07:34:40.66#ibcon#wrote, iclass 12, count 2 2006.183.07:34:40.66#ibcon#about to read 3, iclass 12, count 2 2006.183.07:34:40.69#ibcon#read 3, iclass 12, count 2 2006.183.07:34:40.69#ibcon#about to read 4, iclass 12, count 2 2006.183.07:34:40.69#ibcon#read 4, iclass 12, count 2 2006.183.07:34:40.69#ibcon#about to read 5, iclass 12, count 2 2006.183.07:34:40.69#ibcon#read 5, iclass 12, count 2 2006.183.07:34:40.69#ibcon#about to read 6, iclass 12, count 2 2006.183.07:34:40.69#ibcon#read 6, iclass 12, count 2 2006.183.07:34:40.69#ibcon#end of sib2, iclass 12, count 2 2006.183.07:34:40.69#ibcon#*after write, iclass 12, count 2 2006.183.07:34:40.69#ibcon#*before return 0, iclass 12, count 2 2006.183.07:34:40.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:40.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:34:40.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.07:34:40.69#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:40.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:40.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:40.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:40.82#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:34:40.82#ibcon#first serial, iclass 12, count 0 2006.183.07:34:40.82#ibcon#enter sib2, iclass 12, count 0 2006.183.07:34:40.82#ibcon#flushed, iclass 12, count 0 2006.183.07:34:40.82#ibcon#about to write, iclass 12, count 0 2006.183.07:34:40.82#ibcon#wrote, iclass 12, count 0 2006.183.07:34:40.82#ibcon#about to read 3, iclass 12, count 0 2006.183.07:34:40.83#ibcon#read 3, iclass 12, count 0 2006.183.07:34:40.83#ibcon#about to read 4, iclass 12, count 0 2006.183.07:34:40.83#ibcon#read 4, iclass 12, count 0 2006.183.07:34:40.83#ibcon#about to read 5, iclass 12, count 0 2006.183.07:34:40.83#ibcon#read 5, iclass 12, count 0 2006.183.07:34:40.83#ibcon#about to read 6, iclass 12, count 0 2006.183.07:34:40.83#ibcon#read 6, iclass 12, count 0 2006.183.07:34:40.83#ibcon#end of sib2, iclass 12, count 0 2006.183.07:34:40.83#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:34:40.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:34:40.83#ibcon#[27=USB\r\n] 2006.183.07:34:40.83#ibcon#*before write, iclass 12, count 0 2006.183.07:34:40.83#ibcon#enter sib2, iclass 12, count 0 2006.183.07:34:40.83#ibcon#flushed, iclass 12, count 0 2006.183.07:34:40.83#ibcon#about to write, iclass 12, count 0 2006.183.07:34:40.83#ibcon#wrote, iclass 12, count 0 2006.183.07:34:40.83#ibcon#about to read 3, iclass 12, count 0 2006.183.07:34:40.86#ibcon#read 3, iclass 12, count 0 2006.183.07:34:40.86#ibcon#about to read 4, iclass 12, count 0 2006.183.07:34:40.86#ibcon#read 4, iclass 12, count 0 2006.183.07:34:40.86#ibcon#about to read 5, iclass 12, count 0 2006.183.07:34:40.86#ibcon#read 5, iclass 12, count 0 2006.183.07:34:40.86#ibcon#about to read 6, iclass 12, count 0 2006.183.07:34:40.86#ibcon#read 6, iclass 12, count 0 2006.183.07:34:40.86#ibcon#end of sib2, iclass 12, count 0 2006.183.07:34:40.86#ibcon#*after write, iclass 12, count 0 2006.183.07:34:40.86#ibcon#*before return 0, iclass 12, count 0 2006.183.07:34:40.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:40.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:34:40.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:34:40.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:34:40.86$vc4f8/vblo=2,640.99 2006.183.07:34:40.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.07:34:40.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.07:34:40.86#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:40.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:40.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:40.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:40.86#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:34:40.86#ibcon#first serial, iclass 14, count 0 2006.183.07:34:40.86#ibcon#enter sib2, iclass 14, count 0 2006.183.07:34:40.86#ibcon#flushed, iclass 14, count 0 2006.183.07:34:40.86#ibcon#about to write, iclass 14, count 0 2006.183.07:34:40.86#ibcon#wrote, iclass 14, count 0 2006.183.07:34:40.86#ibcon#about to read 3, iclass 14, count 0 2006.183.07:34:40.89#ibcon#read 3, iclass 14, count 0 2006.183.07:34:40.89#ibcon#about to read 4, iclass 14, count 0 2006.183.07:34:40.89#ibcon#read 4, iclass 14, count 0 2006.183.07:34:40.89#ibcon#about to read 5, iclass 14, count 0 2006.183.07:34:40.89#ibcon#read 5, iclass 14, count 0 2006.183.07:34:40.89#ibcon#about to read 6, iclass 14, count 0 2006.183.07:34:40.89#ibcon#read 6, iclass 14, count 0 2006.183.07:34:40.89#ibcon#end of sib2, iclass 14, count 0 2006.183.07:34:40.89#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:34:40.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:34:40.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:34:40.89#ibcon#*before write, iclass 14, count 0 2006.183.07:34:40.89#ibcon#enter sib2, iclass 14, count 0 2006.183.07:34:40.89#ibcon#flushed, iclass 14, count 0 2006.183.07:34:40.89#ibcon#about to write, iclass 14, count 0 2006.183.07:34:40.89#ibcon#wrote, iclass 14, count 0 2006.183.07:34:40.89#ibcon#about to read 3, iclass 14, count 0 2006.183.07:34:40.93#ibcon#read 3, iclass 14, count 0 2006.183.07:34:40.93#ibcon#about to read 4, iclass 14, count 0 2006.183.07:34:40.93#ibcon#read 4, iclass 14, count 0 2006.183.07:34:40.93#ibcon#about to read 5, iclass 14, count 0 2006.183.07:34:40.93#ibcon#read 5, iclass 14, count 0 2006.183.07:34:40.93#ibcon#about to read 6, iclass 14, count 0 2006.183.07:34:40.93#ibcon#read 6, iclass 14, count 0 2006.183.07:34:40.93#ibcon#end of sib2, iclass 14, count 0 2006.183.07:34:40.93#ibcon#*after write, iclass 14, count 0 2006.183.07:34:40.93#ibcon#*before return 0, iclass 14, count 0 2006.183.07:34:40.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:40.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:34:40.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:34:40.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:34:40.93$vc4f8/vb=2,4 2006.183.07:34:40.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.07:34:40.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.07:34:40.93#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:40.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:40.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:40.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:40.98#ibcon#enter wrdev, iclass 16, count 2 2006.183.07:34:40.98#ibcon#first serial, iclass 16, count 2 2006.183.07:34:40.98#ibcon#enter sib2, iclass 16, count 2 2006.183.07:34:40.98#ibcon#flushed, iclass 16, count 2 2006.183.07:34:40.98#ibcon#about to write, iclass 16, count 2 2006.183.07:34:40.98#ibcon#wrote, iclass 16, count 2 2006.183.07:34:40.98#ibcon#about to read 3, iclass 16, count 2 2006.183.07:34:41.00#ibcon#read 3, iclass 16, count 2 2006.183.07:34:41.00#ibcon#about to read 4, iclass 16, count 2 2006.183.07:34:41.00#ibcon#read 4, iclass 16, count 2 2006.183.07:34:41.00#ibcon#about to read 5, iclass 16, count 2 2006.183.07:34:41.00#ibcon#read 5, iclass 16, count 2 2006.183.07:34:41.00#ibcon#about to read 6, iclass 16, count 2 2006.183.07:34:41.00#ibcon#read 6, iclass 16, count 2 2006.183.07:34:41.00#ibcon#end of sib2, iclass 16, count 2 2006.183.07:34:41.00#ibcon#*mode == 0, iclass 16, count 2 2006.183.07:34:41.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.07:34:41.00#ibcon#[27=AT02-04\r\n] 2006.183.07:34:41.00#ibcon#*before write, iclass 16, count 2 2006.183.07:34:41.00#ibcon#enter sib2, iclass 16, count 2 2006.183.07:34:41.00#ibcon#flushed, iclass 16, count 2 2006.183.07:34:41.00#ibcon#about to write, iclass 16, count 2 2006.183.07:34:41.00#ibcon#wrote, iclass 16, count 2 2006.183.07:34:41.00#ibcon#about to read 3, iclass 16, count 2 2006.183.07:34:41.03#ibcon#read 3, iclass 16, count 2 2006.183.07:34:41.03#ibcon#about to read 4, iclass 16, count 2 2006.183.07:34:41.03#ibcon#read 4, iclass 16, count 2 2006.183.07:34:41.03#ibcon#about to read 5, iclass 16, count 2 2006.183.07:34:41.03#ibcon#read 5, iclass 16, count 2 2006.183.07:34:41.03#ibcon#about to read 6, iclass 16, count 2 2006.183.07:34:41.03#ibcon#read 6, iclass 16, count 2 2006.183.07:34:41.03#ibcon#end of sib2, iclass 16, count 2 2006.183.07:34:41.03#ibcon#*after write, iclass 16, count 2 2006.183.07:34:41.03#ibcon#*before return 0, iclass 16, count 2 2006.183.07:34:41.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:41.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:34:41.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.07:34:41.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:41.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:41.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:41.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:41.15#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:34:41.15#ibcon#first serial, iclass 16, count 0 2006.183.07:34:41.15#ibcon#enter sib2, iclass 16, count 0 2006.183.07:34:41.15#ibcon#flushed, iclass 16, count 0 2006.183.07:34:41.15#ibcon#about to write, iclass 16, count 0 2006.183.07:34:41.15#ibcon#wrote, iclass 16, count 0 2006.183.07:34:41.15#ibcon#about to read 3, iclass 16, count 0 2006.183.07:34:41.17#ibcon#read 3, iclass 16, count 0 2006.183.07:34:41.17#ibcon#about to read 4, iclass 16, count 0 2006.183.07:34:41.17#ibcon#read 4, iclass 16, count 0 2006.183.07:34:41.17#ibcon#about to read 5, iclass 16, count 0 2006.183.07:34:41.17#ibcon#read 5, iclass 16, count 0 2006.183.07:34:41.17#ibcon#about to read 6, iclass 16, count 0 2006.183.07:34:41.17#ibcon#read 6, iclass 16, count 0 2006.183.07:34:41.17#ibcon#end of sib2, iclass 16, count 0 2006.183.07:34:41.17#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:34:41.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:34:41.17#ibcon#[27=USB\r\n] 2006.183.07:34:41.17#ibcon#*before write, iclass 16, count 0 2006.183.07:34:41.17#ibcon#enter sib2, iclass 16, count 0 2006.183.07:34:41.17#ibcon#flushed, iclass 16, count 0 2006.183.07:34:41.17#ibcon#about to write, iclass 16, count 0 2006.183.07:34:41.17#ibcon#wrote, iclass 16, count 0 2006.183.07:34:41.17#ibcon#about to read 3, iclass 16, count 0 2006.183.07:34:41.20#ibcon#read 3, iclass 16, count 0 2006.183.07:34:41.20#ibcon#about to read 4, iclass 16, count 0 2006.183.07:34:41.20#ibcon#read 4, iclass 16, count 0 2006.183.07:34:41.20#ibcon#about to read 5, iclass 16, count 0 2006.183.07:34:41.20#ibcon#read 5, iclass 16, count 0 2006.183.07:34:41.20#ibcon#about to read 6, iclass 16, count 0 2006.183.07:34:41.20#ibcon#read 6, iclass 16, count 0 2006.183.07:34:41.20#ibcon#end of sib2, iclass 16, count 0 2006.183.07:34:41.20#ibcon#*after write, iclass 16, count 0 2006.183.07:34:41.20#ibcon#*before return 0, iclass 16, count 0 2006.183.07:34:41.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:41.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:34:41.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:34:41.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:34:41.20$vc4f8/vblo=3,656.99 2006.183.07:34:41.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.07:34:41.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.07:34:41.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:41.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:34:41.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:34:41.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:34:41.20#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:34:41.20#ibcon#first serial, iclass 18, count 0 2006.183.07:34:41.20#ibcon#enter sib2, iclass 18, count 0 2006.183.07:34:41.20#ibcon#flushed, iclass 18, count 0 2006.183.07:34:41.20#ibcon#about to write, iclass 18, count 0 2006.183.07:34:41.20#ibcon#wrote, iclass 18, count 0 2006.183.07:34:41.20#ibcon#about to read 3, iclass 18, count 0 2006.183.07:34:41.22#ibcon#read 3, iclass 18, count 0 2006.183.07:34:41.22#ibcon#about to read 4, iclass 18, count 0 2006.183.07:34:41.22#ibcon#read 4, iclass 18, count 0 2006.183.07:34:41.22#ibcon#about to read 5, iclass 18, count 0 2006.183.07:34:41.22#ibcon#read 5, iclass 18, count 0 2006.183.07:34:41.22#ibcon#about to read 6, iclass 18, count 0 2006.183.07:34:41.22#ibcon#read 6, iclass 18, count 0 2006.183.07:34:41.22#ibcon#end of sib2, iclass 18, count 0 2006.183.07:34:41.22#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:34:41.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:34:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:34:41.22#ibcon#*before write, iclass 18, count 0 2006.183.07:34:41.22#ibcon#enter sib2, iclass 18, count 0 2006.183.07:34:41.22#ibcon#flushed, iclass 18, count 0 2006.183.07:34:41.22#ibcon#about to write, iclass 18, count 0 2006.183.07:34:41.22#ibcon#wrote, iclass 18, count 0 2006.183.07:34:41.22#ibcon#about to read 3, iclass 18, count 0 2006.183.07:34:41.26#ibcon#read 3, iclass 18, count 0 2006.183.07:34:41.26#ibcon#about to read 4, iclass 18, count 0 2006.183.07:34:41.26#ibcon#read 4, iclass 18, count 0 2006.183.07:34:41.26#ibcon#about to read 5, iclass 18, count 0 2006.183.07:34:41.26#ibcon#read 5, iclass 18, count 0 2006.183.07:34:41.26#ibcon#about to read 6, iclass 18, count 0 2006.183.07:34:41.26#ibcon#read 6, iclass 18, count 0 2006.183.07:34:41.26#ibcon#end of sib2, iclass 18, count 0 2006.183.07:34:41.26#ibcon#*after write, iclass 18, count 0 2006.183.07:34:41.26#ibcon#*before return 0, iclass 18, count 0 2006.183.07:34:41.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:34:41.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:34:41.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:34:41.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:34:41.26$vc4f8/vb=3,4 2006.183.07:34:41.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.07:34:41.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.07:34:41.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:41.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:34:41.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:34:41.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:34:41.32#ibcon#enter wrdev, iclass 20, count 2 2006.183.07:34:41.32#ibcon#first serial, iclass 20, count 2 2006.183.07:34:41.32#ibcon#enter sib2, iclass 20, count 2 2006.183.07:34:41.32#ibcon#flushed, iclass 20, count 2 2006.183.07:34:41.32#ibcon#about to write, iclass 20, count 2 2006.183.07:34:41.32#ibcon#wrote, iclass 20, count 2 2006.183.07:34:41.32#ibcon#about to read 3, iclass 20, count 2 2006.183.07:34:41.34#ibcon#read 3, iclass 20, count 2 2006.183.07:34:41.34#ibcon#about to read 4, iclass 20, count 2 2006.183.07:34:41.34#ibcon#read 4, iclass 20, count 2 2006.183.07:34:41.34#ibcon#about to read 5, iclass 20, count 2 2006.183.07:34:41.34#ibcon#read 5, iclass 20, count 2 2006.183.07:34:41.34#ibcon#about to read 6, iclass 20, count 2 2006.183.07:34:41.34#ibcon#read 6, iclass 20, count 2 2006.183.07:34:41.34#ibcon#end of sib2, iclass 20, count 2 2006.183.07:34:41.34#ibcon#*mode == 0, iclass 20, count 2 2006.183.07:34:41.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.07:34:41.34#ibcon#[27=AT03-04\r\n] 2006.183.07:34:41.34#ibcon#*before write, iclass 20, count 2 2006.183.07:34:41.34#ibcon#enter sib2, iclass 20, count 2 2006.183.07:34:41.34#ibcon#flushed, iclass 20, count 2 2006.183.07:34:41.34#ibcon#about to write, iclass 20, count 2 2006.183.07:34:41.34#ibcon#wrote, iclass 20, count 2 2006.183.07:34:41.34#ibcon#about to read 3, iclass 20, count 2 2006.183.07:34:41.37#ibcon#read 3, iclass 20, count 2 2006.183.07:34:41.37#ibcon#about to read 4, iclass 20, count 2 2006.183.07:34:41.37#ibcon#read 4, iclass 20, count 2 2006.183.07:34:41.37#ibcon#about to read 5, iclass 20, count 2 2006.183.07:34:41.37#ibcon#read 5, iclass 20, count 2 2006.183.07:34:41.37#ibcon#about to read 6, iclass 20, count 2 2006.183.07:34:41.37#ibcon#read 6, iclass 20, count 2 2006.183.07:34:41.37#ibcon#end of sib2, iclass 20, count 2 2006.183.07:34:41.37#ibcon#*after write, iclass 20, count 2 2006.183.07:34:41.37#ibcon#*before return 0, iclass 20, count 2 2006.183.07:34:41.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:34:41.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:34:41.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.07:34:41.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:41.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:34:41.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:34:41.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:34:41.49#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:34:41.49#ibcon#first serial, iclass 20, count 0 2006.183.07:34:41.49#ibcon#enter sib2, iclass 20, count 0 2006.183.07:34:41.49#ibcon#flushed, iclass 20, count 0 2006.183.07:34:41.49#ibcon#about to write, iclass 20, count 0 2006.183.07:34:41.49#ibcon#wrote, iclass 20, count 0 2006.183.07:34:41.49#ibcon#about to read 3, iclass 20, count 0 2006.183.07:34:41.51#ibcon#read 3, iclass 20, count 0 2006.183.07:34:41.51#ibcon#about to read 4, iclass 20, count 0 2006.183.07:34:41.51#ibcon#read 4, iclass 20, count 0 2006.183.07:34:41.51#ibcon#about to read 5, iclass 20, count 0 2006.183.07:34:41.51#ibcon#read 5, iclass 20, count 0 2006.183.07:34:41.51#ibcon#about to read 6, iclass 20, count 0 2006.183.07:34:41.51#ibcon#read 6, iclass 20, count 0 2006.183.07:34:41.51#ibcon#end of sib2, iclass 20, count 0 2006.183.07:34:41.51#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:34:41.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:34:41.51#ibcon#[27=USB\r\n] 2006.183.07:34:41.51#ibcon#*before write, iclass 20, count 0 2006.183.07:34:41.51#ibcon#enter sib2, iclass 20, count 0 2006.183.07:34:41.51#ibcon#flushed, iclass 20, count 0 2006.183.07:34:41.51#ibcon#about to write, iclass 20, count 0 2006.183.07:34:41.51#ibcon#wrote, iclass 20, count 0 2006.183.07:34:41.51#ibcon#about to read 3, iclass 20, count 0 2006.183.07:34:41.54#ibcon#read 3, iclass 20, count 0 2006.183.07:34:41.54#ibcon#about to read 4, iclass 20, count 0 2006.183.07:34:41.54#ibcon#read 4, iclass 20, count 0 2006.183.07:34:41.54#ibcon#about to read 5, iclass 20, count 0 2006.183.07:34:41.54#ibcon#read 5, iclass 20, count 0 2006.183.07:34:41.54#ibcon#about to read 6, iclass 20, count 0 2006.183.07:34:41.54#ibcon#read 6, iclass 20, count 0 2006.183.07:34:41.54#ibcon#end of sib2, iclass 20, count 0 2006.183.07:34:41.54#ibcon#*after write, iclass 20, count 0 2006.183.07:34:41.54#ibcon#*before return 0, iclass 20, count 0 2006.183.07:34:41.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:34:41.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:34:41.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:34:41.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:34:41.54$vc4f8/vblo=4,712.99 2006.183.07:34:41.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.07:34:41.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.07:34:41.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:41.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:34:41.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:34:41.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:34:41.54#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:34:41.54#ibcon#first serial, iclass 22, count 0 2006.183.07:34:41.54#ibcon#enter sib2, iclass 22, count 0 2006.183.07:34:41.54#ibcon#flushed, iclass 22, count 0 2006.183.07:34:41.54#ibcon#about to write, iclass 22, count 0 2006.183.07:34:41.54#ibcon#wrote, iclass 22, count 0 2006.183.07:34:41.54#ibcon#about to read 3, iclass 22, count 0 2006.183.07:34:41.57#ibcon#read 3, iclass 22, count 0 2006.183.07:34:41.57#ibcon#about to read 4, iclass 22, count 0 2006.183.07:34:41.57#ibcon#read 4, iclass 22, count 0 2006.183.07:34:41.57#ibcon#about to read 5, iclass 22, count 0 2006.183.07:34:41.57#ibcon#read 5, iclass 22, count 0 2006.183.07:34:41.57#ibcon#about to read 6, iclass 22, count 0 2006.183.07:34:41.57#ibcon#read 6, iclass 22, count 0 2006.183.07:34:41.57#ibcon#end of sib2, iclass 22, count 0 2006.183.07:34:41.57#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:34:41.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:34:41.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:34:41.57#ibcon#*before write, iclass 22, count 0 2006.183.07:34:41.57#ibcon#enter sib2, iclass 22, count 0 2006.183.07:34:41.57#ibcon#flushed, iclass 22, count 0 2006.183.07:34:41.57#ibcon#about to write, iclass 22, count 0 2006.183.07:34:41.57#ibcon#wrote, iclass 22, count 0 2006.183.07:34:41.57#ibcon#about to read 3, iclass 22, count 0 2006.183.07:34:41.61#ibcon#read 3, iclass 22, count 0 2006.183.07:34:41.61#ibcon#about to read 4, iclass 22, count 0 2006.183.07:34:41.61#ibcon#read 4, iclass 22, count 0 2006.183.07:34:41.61#ibcon#about to read 5, iclass 22, count 0 2006.183.07:34:41.61#ibcon#read 5, iclass 22, count 0 2006.183.07:34:41.61#ibcon#about to read 6, iclass 22, count 0 2006.183.07:34:41.61#ibcon#read 6, iclass 22, count 0 2006.183.07:34:41.61#ibcon#end of sib2, iclass 22, count 0 2006.183.07:34:41.61#ibcon#*after write, iclass 22, count 0 2006.183.07:34:41.61#ibcon#*before return 0, iclass 22, count 0 2006.183.07:34:41.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:34:41.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:34:41.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:34:41.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:34:41.61$vc4f8/vb=4,4 2006.183.07:34:41.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.07:34:41.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.07:34:41.61#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:41.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:41.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:41.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:41.67#ibcon#enter wrdev, iclass 24, count 2 2006.183.07:34:41.67#ibcon#first serial, iclass 24, count 2 2006.183.07:34:41.67#ibcon#enter sib2, iclass 24, count 2 2006.183.07:34:41.67#ibcon#flushed, iclass 24, count 2 2006.183.07:34:41.67#ibcon#about to write, iclass 24, count 2 2006.183.07:34:41.67#ibcon#wrote, iclass 24, count 2 2006.183.07:34:41.67#ibcon#about to read 3, iclass 24, count 2 2006.183.07:34:41.68#ibcon#read 3, iclass 24, count 2 2006.183.07:34:41.68#ibcon#about to read 4, iclass 24, count 2 2006.183.07:34:41.68#ibcon#read 4, iclass 24, count 2 2006.183.07:34:41.68#ibcon#about to read 5, iclass 24, count 2 2006.183.07:34:41.68#ibcon#read 5, iclass 24, count 2 2006.183.07:34:41.68#ibcon#about to read 6, iclass 24, count 2 2006.183.07:34:41.68#ibcon#read 6, iclass 24, count 2 2006.183.07:34:41.68#ibcon#end of sib2, iclass 24, count 2 2006.183.07:34:41.68#ibcon#*mode == 0, iclass 24, count 2 2006.183.07:34:41.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.07:34:41.68#ibcon#[27=AT04-04\r\n] 2006.183.07:34:41.68#ibcon#*before write, iclass 24, count 2 2006.183.07:34:41.68#ibcon#enter sib2, iclass 24, count 2 2006.183.07:34:41.68#ibcon#flushed, iclass 24, count 2 2006.183.07:34:41.68#ibcon#about to write, iclass 24, count 2 2006.183.07:34:41.68#ibcon#wrote, iclass 24, count 2 2006.183.07:34:41.68#ibcon#about to read 3, iclass 24, count 2 2006.183.07:34:41.71#ibcon#read 3, iclass 24, count 2 2006.183.07:34:41.71#ibcon#about to read 4, iclass 24, count 2 2006.183.07:34:41.71#ibcon#read 4, iclass 24, count 2 2006.183.07:34:41.71#ibcon#about to read 5, iclass 24, count 2 2006.183.07:34:41.71#ibcon#read 5, iclass 24, count 2 2006.183.07:34:41.71#ibcon#about to read 6, iclass 24, count 2 2006.183.07:34:41.71#ibcon#read 6, iclass 24, count 2 2006.183.07:34:41.71#ibcon#end of sib2, iclass 24, count 2 2006.183.07:34:41.71#ibcon#*after write, iclass 24, count 2 2006.183.07:34:41.71#ibcon#*before return 0, iclass 24, count 2 2006.183.07:34:41.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:41.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:34:41.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.07:34:41.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:41.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:41.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:41.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:41.83#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:34:41.83#ibcon#first serial, iclass 24, count 0 2006.183.07:34:41.83#ibcon#enter sib2, iclass 24, count 0 2006.183.07:34:41.83#ibcon#flushed, iclass 24, count 0 2006.183.07:34:41.83#ibcon#about to write, iclass 24, count 0 2006.183.07:34:41.83#ibcon#wrote, iclass 24, count 0 2006.183.07:34:41.83#ibcon#about to read 3, iclass 24, count 0 2006.183.07:34:41.85#ibcon#read 3, iclass 24, count 0 2006.183.07:34:41.85#ibcon#about to read 4, iclass 24, count 0 2006.183.07:34:41.85#ibcon#read 4, iclass 24, count 0 2006.183.07:34:41.85#ibcon#about to read 5, iclass 24, count 0 2006.183.07:34:41.85#ibcon#read 5, iclass 24, count 0 2006.183.07:34:41.85#ibcon#about to read 6, iclass 24, count 0 2006.183.07:34:41.85#ibcon#read 6, iclass 24, count 0 2006.183.07:34:41.85#ibcon#end of sib2, iclass 24, count 0 2006.183.07:34:41.85#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:34:41.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:34:41.85#ibcon#[27=USB\r\n] 2006.183.07:34:41.85#ibcon#*before write, iclass 24, count 0 2006.183.07:34:41.85#ibcon#enter sib2, iclass 24, count 0 2006.183.07:34:41.85#ibcon#flushed, iclass 24, count 0 2006.183.07:34:41.85#ibcon#about to write, iclass 24, count 0 2006.183.07:34:41.85#ibcon#wrote, iclass 24, count 0 2006.183.07:34:41.85#ibcon#about to read 3, iclass 24, count 0 2006.183.07:34:41.88#ibcon#read 3, iclass 24, count 0 2006.183.07:34:41.88#ibcon#about to read 4, iclass 24, count 0 2006.183.07:34:41.88#ibcon#read 4, iclass 24, count 0 2006.183.07:34:41.88#ibcon#about to read 5, iclass 24, count 0 2006.183.07:34:41.88#ibcon#read 5, iclass 24, count 0 2006.183.07:34:41.88#ibcon#about to read 6, iclass 24, count 0 2006.183.07:34:41.88#ibcon#read 6, iclass 24, count 0 2006.183.07:34:41.88#ibcon#end of sib2, iclass 24, count 0 2006.183.07:34:41.88#ibcon#*after write, iclass 24, count 0 2006.183.07:34:41.88#ibcon#*before return 0, iclass 24, count 0 2006.183.07:34:41.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:41.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:34:41.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:34:41.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:34:41.88$vc4f8/vblo=5,744.99 2006.183.07:34:41.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.07:34:41.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.07:34:41.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:41.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:41.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:41.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:41.88#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:34:41.88#ibcon#first serial, iclass 26, count 0 2006.183.07:34:41.88#ibcon#enter sib2, iclass 26, count 0 2006.183.07:34:41.88#ibcon#flushed, iclass 26, count 0 2006.183.07:34:41.88#ibcon#about to write, iclass 26, count 0 2006.183.07:34:41.88#ibcon#wrote, iclass 26, count 0 2006.183.07:34:41.88#ibcon#about to read 3, iclass 26, count 0 2006.183.07:34:41.90#ibcon#read 3, iclass 26, count 0 2006.183.07:34:41.90#ibcon#about to read 4, iclass 26, count 0 2006.183.07:34:41.90#ibcon#read 4, iclass 26, count 0 2006.183.07:34:41.90#ibcon#about to read 5, iclass 26, count 0 2006.183.07:34:41.90#ibcon#read 5, iclass 26, count 0 2006.183.07:34:41.90#ibcon#about to read 6, iclass 26, count 0 2006.183.07:34:41.90#ibcon#read 6, iclass 26, count 0 2006.183.07:34:41.90#ibcon#end of sib2, iclass 26, count 0 2006.183.07:34:41.90#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:34:41.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:34:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:34:41.90#ibcon#*before write, iclass 26, count 0 2006.183.07:34:41.90#ibcon#enter sib2, iclass 26, count 0 2006.183.07:34:41.90#ibcon#flushed, iclass 26, count 0 2006.183.07:34:41.90#ibcon#about to write, iclass 26, count 0 2006.183.07:34:41.90#ibcon#wrote, iclass 26, count 0 2006.183.07:34:41.90#ibcon#about to read 3, iclass 26, count 0 2006.183.07:34:41.94#ibcon#read 3, iclass 26, count 0 2006.183.07:34:41.94#ibcon#about to read 4, iclass 26, count 0 2006.183.07:34:41.94#ibcon#read 4, iclass 26, count 0 2006.183.07:34:41.94#ibcon#about to read 5, iclass 26, count 0 2006.183.07:34:41.94#ibcon#read 5, iclass 26, count 0 2006.183.07:34:41.94#ibcon#about to read 6, iclass 26, count 0 2006.183.07:34:41.94#ibcon#read 6, iclass 26, count 0 2006.183.07:34:41.94#ibcon#end of sib2, iclass 26, count 0 2006.183.07:34:41.94#ibcon#*after write, iclass 26, count 0 2006.183.07:34:41.94#ibcon#*before return 0, iclass 26, count 0 2006.183.07:34:41.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:41.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:34:41.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:34:41.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:34:41.94$vc4f8/vb=5,4 2006.183.07:34:41.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.07:34:41.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.07:34:41.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:41.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:42.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:42.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:42.00#ibcon#enter wrdev, iclass 28, count 2 2006.183.07:34:42.00#ibcon#first serial, iclass 28, count 2 2006.183.07:34:42.00#ibcon#enter sib2, iclass 28, count 2 2006.183.07:34:42.00#ibcon#flushed, iclass 28, count 2 2006.183.07:34:42.00#ibcon#about to write, iclass 28, count 2 2006.183.07:34:42.00#ibcon#wrote, iclass 28, count 2 2006.183.07:34:42.00#ibcon#about to read 3, iclass 28, count 2 2006.183.07:34:42.02#ibcon#read 3, iclass 28, count 2 2006.183.07:34:42.02#ibcon#about to read 4, iclass 28, count 2 2006.183.07:34:42.02#ibcon#read 4, iclass 28, count 2 2006.183.07:34:42.02#ibcon#about to read 5, iclass 28, count 2 2006.183.07:34:42.02#ibcon#read 5, iclass 28, count 2 2006.183.07:34:42.02#ibcon#about to read 6, iclass 28, count 2 2006.183.07:34:42.02#ibcon#read 6, iclass 28, count 2 2006.183.07:34:42.02#ibcon#end of sib2, iclass 28, count 2 2006.183.07:34:42.02#ibcon#*mode == 0, iclass 28, count 2 2006.183.07:34:42.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.07:34:42.02#ibcon#[27=AT05-04\r\n] 2006.183.07:34:42.02#ibcon#*before write, iclass 28, count 2 2006.183.07:34:42.02#ibcon#enter sib2, iclass 28, count 2 2006.183.07:34:42.02#ibcon#flushed, iclass 28, count 2 2006.183.07:34:42.02#ibcon#about to write, iclass 28, count 2 2006.183.07:34:42.02#ibcon#wrote, iclass 28, count 2 2006.183.07:34:42.02#ibcon#about to read 3, iclass 28, count 2 2006.183.07:34:42.05#ibcon#read 3, iclass 28, count 2 2006.183.07:34:42.05#ibcon#about to read 4, iclass 28, count 2 2006.183.07:34:42.05#ibcon#read 4, iclass 28, count 2 2006.183.07:34:42.05#ibcon#about to read 5, iclass 28, count 2 2006.183.07:34:42.05#ibcon#read 5, iclass 28, count 2 2006.183.07:34:42.05#ibcon#about to read 6, iclass 28, count 2 2006.183.07:34:42.05#ibcon#read 6, iclass 28, count 2 2006.183.07:34:42.05#ibcon#end of sib2, iclass 28, count 2 2006.183.07:34:42.05#ibcon#*after write, iclass 28, count 2 2006.183.07:34:42.05#ibcon#*before return 0, iclass 28, count 2 2006.183.07:34:42.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:42.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:34:42.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.07:34:42.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:42.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:42.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:42.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:42.17#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:34:42.17#ibcon#first serial, iclass 28, count 0 2006.183.07:34:42.17#ibcon#enter sib2, iclass 28, count 0 2006.183.07:34:42.17#ibcon#flushed, iclass 28, count 0 2006.183.07:34:42.17#ibcon#about to write, iclass 28, count 0 2006.183.07:34:42.17#ibcon#wrote, iclass 28, count 0 2006.183.07:34:42.17#ibcon#about to read 3, iclass 28, count 0 2006.183.07:34:42.19#ibcon#read 3, iclass 28, count 0 2006.183.07:34:42.19#ibcon#about to read 4, iclass 28, count 0 2006.183.07:34:42.19#ibcon#read 4, iclass 28, count 0 2006.183.07:34:42.19#ibcon#about to read 5, iclass 28, count 0 2006.183.07:34:42.19#ibcon#read 5, iclass 28, count 0 2006.183.07:34:42.19#ibcon#about to read 6, iclass 28, count 0 2006.183.07:34:42.19#ibcon#read 6, iclass 28, count 0 2006.183.07:34:42.19#ibcon#end of sib2, iclass 28, count 0 2006.183.07:34:42.19#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:34:42.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:34:42.19#ibcon#[27=USB\r\n] 2006.183.07:34:42.19#ibcon#*before write, iclass 28, count 0 2006.183.07:34:42.19#ibcon#enter sib2, iclass 28, count 0 2006.183.07:34:42.19#ibcon#flushed, iclass 28, count 0 2006.183.07:34:42.19#ibcon#about to write, iclass 28, count 0 2006.183.07:34:42.19#ibcon#wrote, iclass 28, count 0 2006.183.07:34:42.19#ibcon#about to read 3, iclass 28, count 0 2006.183.07:34:42.22#ibcon#read 3, iclass 28, count 0 2006.183.07:34:42.22#ibcon#about to read 4, iclass 28, count 0 2006.183.07:34:42.22#ibcon#read 4, iclass 28, count 0 2006.183.07:34:42.22#ibcon#about to read 5, iclass 28, count 0 2006.183.07:34:42.22#ibcon#read 5, iclass 28, count 0 2006.183.07:34:42.22#ibcon#about to read 6, iclass 28, count 0 2006.183.07:34:42.22#ibcon#read 6, iclass 28, count 0 2006.183.07:34:42.22#ibcon#end of sib2, iclass 28, count 0 2006.183.07:34:42.22#ibcon#*after write, iclass 28, count 0 2006.183.07:34:42.22#ibcon#*before return 0, iclass 28, count 0 2006.183.07:34:42.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:42.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:34:42.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:34:42.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:34:42.22$vc4f8/vblo=6,752.99 2006.183.07:34:42.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.07:34:42.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.07:34:42.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:34:42.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:42.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:42.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:42.22#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:34:42.22#ibcon#first serial, iclass 30, count 0 2006.183.07:34:42.22#ibcon#enter sib2, iclass 30, count 0 2006.183.07:34:42.22#ibcon#flushed, iclass 30, count 0 2006.183.07:34:42.22#ibcon#about to write, iclass 30, count 0 2006.183.07:34:42.22#ibcon#wrote, iclass 30, count 0 2006.183.07:34:42.22#ibcon#about to read 3, iclass 30, count 0 2006.183.07:34:42.24#ibcon#read 3, iclass 30, count 0 2006.183.07:34:42.24#ibcon#about to read 4, iclass 30, count 0 2006.183.07:34:42.24#ibcon#read 4, iclass 30, count 0 2006.183.07:34:42.24#ibcon#about to read 5, iclass 30, count 0 2006.183.07:34:42.24#ibcon#read 5, iclass 30, count 0 2006.183.07:34:42.24#ibcon#about to read 6, iclass 30, count 0 2006.183.07:34:42.24#ibcon#read 6, iclass 30, count 0 2006.183.07:34:42.24#ibcon#end of sib2, iclass 30, count 0 2006.183.07:34:42.24#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:34:42.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:34:42.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:34:42.24#ibcon#*before write, iclass 30, count 0 2006.183.07:34:42.24#ibcon#enter sib2, iclass 30, count 0 2006.183.07:34:42.24#ibcon#flushed, iclass 30, count 0 2006.183.07:34:42.24#ibcon#about to write, iclass 30, count 0 2006.183.07:34:42.24#ibcon#wrote, iclass 30, count 0 2006.183.07:34:42.24#ibcon#about to read 3, iclass 30, count 0 2006.183.07:34:42.28#ibcon#read 3, iclass 30, count 0 2006.183.07:34:42.28#ibcon#about to read 4, iclass 30, count 0 2006.183.07:34:42.28#ibcon#read 4, iclass 30, count 0 2006.183.07:34:42.28#ibcon#about to read 5, iclass 30, count 0 2006.183.07:34:42.28#ibcon#read 5, iclass 30, count 0 2006.183.07:34:42.28#ibcon#about to read 6, iclass 30, count 0 2006.183.07:34:42.28#ibcon#read 6, iclass 30, count 0 2006.183.07:34:42.28#ibcon#end of sib2, iclass 30, count 0 2006.183.07:34:42.28#ibcon#*after write, iclass 30, count 0 2006.183.07:34:42.28#ibcon#*before return 0, iclass 30, count 0 2006.183.07:34:42.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:42.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:34:42.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:34:42.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:34:42.28$vc4f8/vb=6,4 2006.183.07:34:42.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.07:34:42.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.07:34:42.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:34:42.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:42.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:42.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:42.34#ibcon#enter wrdev, iclass 32, count 2 2006.183.07:34:42.34#ibcon#first serial, iclass 32, count 2 2006.183.07:34:42.34#ibcon#enter sib2, iclass 32, count 2 2006.183.07:34:42.34#ibcon#flushed, iclass 32, count 2 2006.183.07:34:42.34#ibcon#about to write, iclass 32, count 2 2006.183.07:34:42.34#ibcon#wrote, iclass 32, count 2 2006.183.07:34:42.34#ibcon#about to read 3, iclass 32, count 2 2006.183.07:34:42.36#ibcon#read 3, iclass 32, count 2 2006.183.07:34:42.36#ibcon#about to read 4, iclass 32, count 2 2006.183.07:34:42.36#ibcon#read 4, iclass 32, count 2 2006.183.07:34:42.36#ibcon#about to read 5, iclass 32, count 2 2006.183.07:34:42.36#ibcon#read 5, iclass 32, count 2 2006.183.07:34:42.36#ibcon#about to read 6, iclass 32, count 2 2006.183.07:34:42.36#ibcon#read 6, iclass 32, count 2 2006.183.07:34:42.36#ibcon#end of sib2, iclass 32, count 2 2006.183.07:34:42.36#ibcon#*mode == 0, iclass 32, count 2 2006.183.07:34:42.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.07:34:42.36#ibcon#[27=AT06-04\r\n] 2006.183.07:34:42.36#ibcon#*before write, iclass 32, count 2 2006.183.07:34:42.36#ibcon#enter sib2, iclass 32, count 2 2006.183.07:34:42.36#ibcon#flushed, iclass 32, count 2 2006.183.07:34:42.36#ibcon#about to write, iclass 32, count 2 2006.183.07:34:42.36#ibcon#wrote, iclass 32, count 2 2006.183.07:34:42.36#ibcon#about to read 3, iclass 32, count 2 2006.183.07:34:42.39#ibcon#read 3, iclass 32, count 2 2006.183.07:34:42.39#ibcon#about to read 4, iclass 32, count 2 2006.183.07:34:42.39#ibcon#read 4, iclass 32, count 2 2006.183.07:34:42.39#ibcon#about to read 5, iclass 32, count 2 2006.183.07:34:42.39#ibcon#read 5, iclass 32, count 2 2006.183.07:34:42.39#ibcon#about to read 6, iclass 32, count 2 2006.183.07:34:42.39#ibcon#read 6, iclass 32, count 2 2006.183.07:34:42.39#ibcon#end of sib2, iclass 32, count 2 2006.183.07:34:42.39#ibcon#*after write, iclass 32, count 2 2006.183.07:34:42.39#ibcon#*before return 0, iclass 32, count 2 2006.183.07:34:42.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:42.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:34:42.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.07:34:42.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:34:42.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:42.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:42.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:42.51#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:34:42.51#ibcon#first serial, iclass 32, count 0 2006.183.07:34:42.51#ibcon#enter sib2, iclass 32, count 0 2006.183.07:34:42.51#ibcon#flushed, iclass 32, count 0 2006.183.07:34:42.51#ibcon#about to write, iclass 32, count 0 2006.183.07:34:42.51#ibcon#wrote, iclass 32, count 0 2006.183.07:34:42.51#ibcon#about to read 3, iclass 32, count 0 2006.183.07:34:42.53#ibcon#read 3, iclass 32, count 0 2006.183.07:34:42.53#ibcon#about to read 4, iclass 32, count 0 2006.183.07:34:42.53#ibcon#read 4, iclass 32, count 0 2006.183.07:34:42.53#ibcon#about to read 5, iclass 32, count 0 2006.183.07:34:42.53#ibcon#read 5, iclass 32, count 0 2006.183.07:34:42.53#ibcon#about to read 6, iclass 32, count 0 2006.183.07:34:42.53#ibcon#read 6, iclass 32, count 0 2006.183.07:34:42.53#ibcon#end of sib2, iclass 32, count 0 2006.183.07:34:42.53#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:34:42.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:34:42.53#ibcon#[27=USB\r\n] 2006.183.07:34:42.53#ibcon#*before write, iclass 32, count 0 2006.183.07:34:42.53#ibcon#enter sib2, iclass 32, count 0 2006.183.07:34:42.53#ibcon#flushed, iclass 32, count 0 2006.183.07:34:42.53#ibcon#about to write, iclass 32, count 0 2006.183.07:34:42.53#ibcon#wrote, iclass 32, count 0 2006.183.07:34:42.53#ibcon#about to read 3, iclass 32, count 0 2006.183.07:34:42.56#ibcon#read 3, iclass 32, count 0 2006.183.07:34:42.56#ibcon#about to read 4, iclass 32, count 0 2006.183.07:34:42.56#ibcon#read 4, iclass 32, count 0 2006.183.07:34:42.56#ibcon#about to read 5, iclass 32, count 0 2006.183.07:34:42.56#ibcon#read 5, iclass 32, count 0 2006.183.07:34:42.56#ibcon#about to read 6, iclass 32, count 0 2006.183.07:34:42.56#ibcon#read 6, iclass 32, count 0 2006.183.07:34:42.56#ibcon#end of sib2, iclass 32, count 0 2006.183.07:34:42.56#ibcon#*after write, iclass 32, count 0 2006.183.07:34:42.56#ibcon#*before return 0, iclass 32, count 0 2006.183.07:34:42.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:42.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:34:42.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:34:42.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:34:42.56$vc4f8/vabw=wide 2006.183.07:34:42.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.07:34:42.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.07:34:42.56#ibcon#ireg 8 cls_cnt 0 2006.183.07:34:42.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:42.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:42.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:42.56#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:34:42.56#ibcon#first serial, iclass 34, count 0 2006.183.07:34:42.56#ibcon#enter sib2, iclass 34, count 0 2006.183.07:34:42.56#ibcon#flushed, iclass 34, count 0 2006.183.07:34:42.56#ibcon#about to write, iclass 34, count 0 2006.183.07:34:42.56#ibcon#wrote, iclass 34, count 0 2006.183.07:34:42.56#ibcon#about to read 3, iclass 34, count 0 2006.183.07:34:42.58#ibcon#read 3, iclass 34, count 0 2006.183.07:34:42.58#ibcon#about to read 4, iclass 34, count 0 2006.183.07:34:42.58#ibcon#read 4, iclass 34, count 0 2006.183.07:34:42.58#ibcon#about to read 5, iclass 34, count 0 2006.183.07:34:42.58#ibcon#read 5, iclass 34, count 0 2006.183.07:34:42.58#ibcon#about to read 6, iclass 34, count 0 2006.183.07:34:42.58#ibcon#read 6, iclass 34, count 0 2006.183.07:34:42.58#ibcon#end of sib2, iclass 34, count 0 2006.183.07:34:42.58#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:34:42.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:34:42.58#ibcon#[25=BW32\r\n] 2006.183.07:34:42.58#ibcon#*before write, iclass 34, count 0 2006.183.07:34:42.58#ibcon#enter sib2, iclass 34, count 0 2006.183.07:34:42.58#ibcon#flushed, iclass 34, count 0 2006.183.07:34:42.58#ibcon#about to write, iclass 34, count 0 2006.183.07:34:42.58#ibcon#wrote, iclass 34, count 0 2006.183.07:34:42.58#ibcon#about to read 3, iclass 34, count 0 2006.183.07:34:42.61#ibcon#read 3, iclass 34, count 0 2006.183.07:34:42.61#ibcon#about to read 4, iclass 34, count 0 2006.183.07:34:42.61#ibcon#read 4, iclass 34, count 0 2006.183.07:34:42.61#ibcon#about to read 5, iclass 34, count 0 2006.183.07:34:42.61#ibcon#read 5, iclass 34, count 0 2006.183.07:34:42.61#ibcon#about to read 6, iclass 34, count 0 2006.183.07:34:42.61#ibcon#read 6, iclass 34, count 0 2006.183.07:34:42.61#ibcon#end of sib2, iclass 34, count 0 2006.183.07:34:42.61#ibcon#*after write, iclass 34, count 0 2006.183.07:34:42.61#ibcon#*before return 0, iclass 34, count 0 2006.183.07:34:42.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:42.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:34:42.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:34:42.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:34:42.61$vc4f8/vbbw=wide 2006.183.07:34:42.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:34:42.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:34:42.61#ibcon#ireg 8 cls_cnt 0 2006.183.07:34:42.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:34:42.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:34:42.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:34:42.68#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:34:42.68#ibcon#first serial, iclass 36, count 0 2006.183.07:34:42.68#ibcon#enter sib2, iclass 36, count 0 2006.183.07:34:42.68#ibcon#flushed, iclass 36, count 0 2006.183.07:34:42.68#ibcon#about to write, iclass 36, count 0 2006.183.07:34:42.68#ibcon#wrote, iclass 36, count 0 2006.183.07:34:42.68#ibcon#about to read 3, iclass 36, count 0 2006.183.07:34:42.70#ibcon#read 3, iclass 36, count 0 2006.183.07:34:42.70#ibcon#about to read 4, iclass 36, count 0 2006.183.07:34:42.70#ibcon#read 4, iclass 36, count 0 2006.183.07:34:42.70#ibcon#about to read 5, iclass 36, count 0 2006.183.07:34:42.70#ibcon#read 5, iclass 36, count 0 2006.183.07:34:42.70#ibcon#about to read 6, iclass 36, count 0 2006.183.07:34:42.70#ibcon#read 6, iclass 36, count 0 2006.183.07:34:42.70#ibcon#end of sib2, iclass 36, count 0 2006.183.07:34:42.70#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:34:42.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:34:42.70#ibcon#[27=BW32\r\n] 2006.183.07:34:42.70#ibcon#*before write, iclass 36, count 0 2006.183.07:34:42.70#ibcon#enter sib2, iclass 36, count 0 2006.183.07:34:42.70#ibcon#flushed, iclass 36, count 0 2006.183.07:34:42.70#ibcon#about to write, iclass 36, count 0 2006.183.07:34:42.70#ibcon#wrote, iclass 36, count 0 2006.183.07:34:42.70#ibcon#about to read 3, iclass 36, count 0 2006.183.07:34:42.73#ibcon#read 3, iclass 36, count 0 2006.183.07:34:42.73#ibcon#about to read 4, iclass 36, count 0 2006.183.07:34:42.73#ibcon#read 4, iclass 36, count 0 2006.183.07:34:42.73#ibcon#about to read 5, iclass 36, count 0 2006.183.07:34:42.73#ibcon#read 5, iclass 36, count 0 2006.183.07:34:42.73#ibcon#about to read 6, iclass 36, count 0 2006.183.07:34:42.73#ibcon#read 6, iclass 36, count 0 2006.183.07:34:42.73#ibcon#end of sib2, iclass 36, count 0 2006.183.07:34:42.73#ibcon#*after write, iclass 36, count 0 2006.183.07:34:42.73#ibcon#*before return 0, iclass 36, count 0 2006.183.07:34:42.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:34:42.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:34:42.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:34:42.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:34:42.73$4f8m12a/ifd4f 2006.183.07:34:42.73$ifd4f/lo= 2006.183.07:34:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:34:42.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:34:42.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:34:42.74$ifd4f/patch= 2006.183.07:34:42.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:34:42.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:34:42.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:34:42.74$4f8m12a/"form=m,16.000,1:2 2006.183.07:34:42.74$4f8m12a/"tpicd 2006.183.07:34:42.74$4f8m12a/echo=off 2006.183.07:34:42.74$4f8m12a/xlog=off 2006.183.07:34:42.74:!2006.183.07:35:10 2006.183.07:34:48.14#trakl#Source acquired 2006.183.07:34:49.14#flagr#flagr/antenna,acquired 2006.183.07:34:55.14#trakl#Off source 2006.183.07:34:55.14?ERROR st -7 Antenna off-source! 2006.183.07:34:55.14#trakl#az 256.531 el 51.400 azerr*cos(el) -0.0002 elerr -0.0196 2006.183.07:34:55.14#flagr#flagr/antenna,off-source 2006.183.07:35:01.14#trakl#Source re-acquired 2006.183.07:35:01.14#flagr#flagr/antenna,re-acquired 2006.183.07:35:10.01:preob 2006.183.07:35:11.14/onsource/TRACKING 2006.183.07:35:11.14:!2006.183.07:35:20 2006.183.07:35:20.00:data_valid=on 2006.183.07:35:20.00:midob 2006.183.07:35:20.14/onsource/TRACKING 2006.183.07:35:20.14/wx/27.90,996.2,88 2006.183.07:35:20.20/cable/+6.4522E-03 2006.183.07:35:21.29/va/01,08,usb,yes,28,30 2006.183.07:35:21.29/va/02,07,usb,yes,29,30 2006.183.07:35:21.29/va/03,06,usb,yes,30,30 2006.183.07:35:21.29/va/04,07,usb,yes,30,32 2006.183.07:35:21.29/va/05,07,usb,yes,31,33 2006.183.07:35:21.29/va/06,06,usb,yes,30,30 2006.183.07:35:21.29/va/07,06,usb,yes,31,30 2006.183.07:35:21.29/va/08,07,usb,yes,29,29 2006.183.07:35:21.52/valo/01,532.99,yes,locked 2006.183.07:35:21.52/valo/02,572.99,yes,locked 2006.183.07:35:21.52/valo/03,672.99,yes,locked 2006.183.07:35:21.52/valo/04,832.99,yes,locked 2006.183.07:35:21.52/valo/05,652.99,yes,locked 2006.183.07:35:21.52/valo/06,772.99,yes,locked 2006.183.07:35:21.52/valo/07,832.99,yes,locked 2006.183.07:35:21.52/valo/08,852.99,yes,locked 2006.183.07:35:22.61/vb/01,04,usb,yes,29,27 2006.183.07:35:22.61/vb/02,04,usb,yes,30,32 2006.183.07:35:22.61/vb/03,04,usb,yes,27,30 2006.183.07:35:22.61/vb/04,04,usb,yes,28,28 2006.183.07:35:22.61/vb/05,04,usb,yes,26,30 2006.183.07:35:22.61/vb/06,04,usb,yes,27,30 2006.183.07:35:22.61/vb/07,04,usb,yes,29,29 2006.183.07:35:22.61/vb/08,04,usb,yes,27,30 2006.183.07:35:22.84/vblo/01,632.99,yes,locked 2006.183.07:35:22.84/vblo/02,640.99,yes,locked 2006.183.07:35:22.84/vblo/03,656.99,yes,locked 2006.183.07:35:22.84/vblo/04,712.99,yes,locked 2006.183.07:35:22.84/vblo/05,744.99,yes,locked 2006.183.07:35:22.84/vblo/06,752.99,yes,locked 2006.183.07:35:22.84/vblo/07,734.99,yes,locked 2006.183.07:35:22.84/vblo/08,744.99,yes,locked 2006.183.07:35:22.99/vabw/8 2006.183.07:35:23.14/vbbw/8 2006.183.07:35:23.23/xfe/off,on,14.7 2006.183.07:35:23.60/ifatt/23,28,28,28 2006.183.07:35:24.07/fmout-gps/S +3.31E-07 2006.183.07:35:24.15:!2006.183.07:36:20 2006.183.07:36:20.00:data_valid=off 2006.183.07:36:20.01:postob 2006.183.07:36:20.20/cable/+6.4532E-03 2006.183.07:36:20.21/wx/27.90,996.2,87 2006.183.07:36:21.07/fmout-gps/S +3.30E-07 2006.183.07:36:21.08:scan_name=183-0737,k06183,60 2006.183.07:36:21.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.183.07:36:21.14#flagr#flagr/antenna,new-source 2006.183.07:36:22.14:checkk5 2006.183.07:36:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:36:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:36:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:36:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:36:24.02/chk_obsdata//k5ts1/T1830735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:36:24.39/chk_obsdata//k5ts2/T1830735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:36:24.76/chk_obsdata//k5ts3/T1830735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:36:25.14/chk_obsdata//k5ts4/T1830735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:36:25.83/k5log//k5ts1_log_newline 2006.183.07:36:26.52/k5log//k5ts2_log_newline 2006.183.07:36:27.20/k5log//k5ts3_log_newline 2006.183.07:36:27.89/k5log//k5ts4_log_newline 2006.183.07:36:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:36:27.92:4f8m12a=1 2006.183.07:36:27.92$4f8m12a/echo=on 2006.183.07:36:27.92$4f8m12a/pcalon 2006.183.07:36:27.92$pcalon/"no phase cal control is implemented here 2006.183.07:36:27.92$4f8m12a/"tpicd=stop 2006.183.07:36:27.92$4f8m12a/vc4f8 2006.183.07:36:27.92$vc4f8/valo=1,532.99 2006.183.07:36:27.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.07:36:27.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.07:36:27.92#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:27.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:27.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:27.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:27.92#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:36:27.92#ibcon#first serial, iclass 7, count 0 2006.183.07:36:27.92#ibcon#enter sib2, iclass 7, count 0 2006.183.07:36:27.92#ibcon#flushed, iclass 7, count 0 2006.183.07:36:27.92#ibcon#about to write, iclass 7, count 0 2006.183.07:36:27.92#ibcon#wrote, iclass 7, count 0 2006.183.07:36:27.92#ibcon#about to read 3, iclass 7, count 0 2006.183.07:36:27.96#ibcon#read 3, iclass 7, count 0 2006.183.07:36:27.96#ibcon#about to read 4, iclass 7, count 0 2006.183.07:36:27.96#ibcon#read 4, iclass 7, count 0 2006.183.07:36:27.96#ibcon#about to read 5, iclass 7, count 0 2006.183.07:36:27.96#ibcon#read 5, iclass 7, count 0 2006.183.07:36:27.96#ibcon#about to read 6, iclass 7, count 0 2006.183.07:36:27.96#ibcon#read 6, iclass 7, count 0 2006.183.07:36:27.96#ibcon#end of sib2, iclass 7, count 0 2006.183.07:36:27.96#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:36:27.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:36:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:36:27.96#ibcon#*before write, iclass 7, count 0 2006.183.07:36:27.96#ibcon#enter sib2, iclass 7, count 0 2006.183.07:36:27.96#ibcon#flushed, iclass 7, count 0 2006.183.07:36:27.96#ibcon#about to write, iclass 7, count 0 2006.183.07:36:27.96#ibcon#wrote, iclass 7, count 0 2006.183.07:36:27.96#ibcon#about to read 3, iclass 7, count 0 2006.183.07:36:28.00#ibcon#read 3, iclass 7, count 0 2006.183.07:36:28.00#ibcon#about to read 4, iclass 7, count 0 2006.183.07:36:28.00#ibcon#read 4, iclass 7, count 0 2006.183.07:36:28.00#ibcon#about to read 5, iclass 7, count 0 2006.183.07:36:28.00#ibcon#read 5, iclass 7, count 0 2006.183.07:36:28.00#ibcon#about to read 6, iclass 7, count 0 2006.183.07:36:28.00#ibcon#read 6, iclass 7, count 0 2006.183.07:36:28.00#ibcon#end of sib2, iclass 7, count 0 2006.183.07:36:28.00#ibcon#*after write, iclass 7, count 0 2006.183.07:36:28.00#ibcon#*before return 0, iclass 7, count 0 2006.183.07:36:28.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:28.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:28.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:36:28.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:36:28.00$vc4f8/va=1,8 2006.183.07:36:28.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.07:36:28.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.07:36:28.00#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:28.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:28.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:28.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:28.00#ibcon#enter wrdev, iclass 11, count 2 2006.183.07:36:28.00#ibcon#first serial, iclass 11, count 2 2006.183.07:36:28.00#ibcon#enter sib2, iclass 11, count 2 2006.183.07:36:28.00#ibcon#flushed, iclass 11, count 2 2006.183.07:36:28.00#ibcon#about to write, iclass 11, count 2 2006.183.07:36:28.00#ibcon#wrote, iclass 11, count 2 2006.183.07:36:28.00#ibcon#about to read 3, iclass 11, count 2 2006.183.07:36:28.03#ibcon#read 3, iclass 11, count 2 2006.183.07:36:28.03#ibcon#about to read 4, iclass 11, count 2 2006.183.07:36:28.03#ibcon#read 4, iclass 11, count 2 2006.183.07:36:28.03#ibcon#about to read 5, iclass 11, count 2 2006.183.07:36:28.03#ibcon#read 5, iclass 11, count 2 2006.183.07:36:28.03#ibcon#about to read 6, iclass 11, count 2 2006.183.07:36:28.03#ibcon#read 6, iclass 11, count 2 2006.183.07:36:28.03#ibcon#end of sib2, iclass 11, count 2 2006.183.07:36:28.03#ibcon#*mode == 0, iclass 11, count 2 2006.183.07:36:28.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.07:36:28.03#ibcon#[25=AT01-08\r\n] 2006.183.07:36:28.03#ibcon#*before write, iclass 11, count 2 2006.183.07:36:28.03#ibcon#enter sib2, iclass 11, count 2 2006.183.07:36:28.03#ibcon#flushed, iclass 11, count 2 2006.183.07:36:28.03#ibcon#about to write, iclass 11, count 2 2006.183.07:36:28.03#ibcon#wrote, iclass 11, count 2 2006.183.07:36:28.03#ibcon#about to read 3, iclass 11, count 2 2006.183.07:36:28.06#ibcon#read 3, iclass 11, count 2 2006.183.07:36:28.06#ibcon#about to read 4, iclass 11, count 2 2006.183.07:36:28.06#ibcon#read 4, iclass 11, count 2 2006.183.07:36:28.06#ibcon#about to read 5, iclass 11, count 2 2006.183.07:36:28.06#ibcon#read 5, iclass 11, count 2 2006.183.07:36:28.06#ibcon#about to read 6, iclass 11, count 2 2006.183.07:36:28.06#ibcon#read 6, iclass 11, count 2 2006.183.07:36:28.06#ibcon#end of sib2, iclass 11, count 2 2006.183.07:36:28.06#ibcon#*after write, iclass 11, count 2 2006.183.07:36:28.06#ibcon#*before return 0, iclass 11, count 2 2006.183.07:36:28.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:28.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:28.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.07:36:28.06#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:28.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:28.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:28.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:28.17#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:36:28.17#ibcon#first serial, iclass 11, count 0 2006.183.07:36:28.17#ibcon#enter sib2, iclass 11, count 0 2006.183.07:36:28.17#ibcon#flushed, iclass 11, count 0 2006.183.07:36:28.17#ibcon#about to write, iclass 11, count 0 2006.183.07:36:28.17#ibcon#wrote, iclass 11, count 0 2006.183.07:36:28.17#ibcon#about to read 3, iclass 11, count 0 2006.183.07:36:28.19#ibcon#read 3, iclass 11, count 0 2006.183.07:36:28.19#ibcon#about to read 4, iclass 11, count 0 2006.183.07:36:28.19#ibcon#read 4, iclass 11, count 0 2006.183.07:36:28.19#ibcon#about to read 5, iclass 11, count 0 2006.183.07:36:28.19#ibcon#read 5, iclass 11, count 0 2006.183.07:36:28.19#ibcon#about to read 6, iclass 11, count 0 2006.183.07:36:28.19#ibcon#read 6, iclass 11, count 0 2006.183.07:36:28.19#ibcon#end of sib2, iclass 11, count 0 2006.183.07:36:28.19#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:36:28.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:36:28.19#ibcon#[25=USB\r\n] 2006.183.07:36:28.19#ibcon#*before write, iclass 11, count 0 2006.183.07:36:28.19#ibcon#enter sib2, iclass 11, count 0 2006.183.07:36:28.19#ibcon#flushed, iclass 11, count 0 2006.183.07:36:28.19#ibcon#about to write, iclass 11, count 0 2006.183.07:36:28.19#ibcon#wrote, iclass 11, count 0 2006.183.07:36:28.19#ibcon#about to read 3, iclass 11, count 0 2006.183.07:36:28.22#ibcon#read 3, iclass 11, count 0 2006.183.07:36:28.22#ibcon#about to read 4, iclass 11, count 0 2006.183.07:36:28.22#ibcon#read 4, iclass 11, count 0 2006.183.07:36:28.22#ibcon#about to read 5, iclass 11, count 0 2006.183.07:36:28.22#ibcon#read 5, iclass 11, count 0 2006.183.07:36:28.22#ibcon#about to read 6, iclass 11, count 0 2006.183.07:36:28.22#ibcon#read 6, iclass 11, count 0 2006.183.07:36:28.22#ibcon#end of sib2, iclass 11, count 0 2006.183.07:36:28.22#ibcon#*after write, iclass 11, count 0 2006.183.07:36:28.22#ibcon#*before return 0, iclass 11, count 0 2006.183.07:36:28.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:28.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:28.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:36:28.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:36:28.22$vc4f8/valo=2,572.99 2006.183.07:36:28.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:36:28.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:36:28.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:28.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:28.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:28.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:28.22#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:36:28.22#ibcon#first serial, iclass 13, count 0 2006.183.07:36:28.22#ibcon#enter sib2, iclass 13, count 0 2006.183.07:36:28.22#ibcon#flushed, iclass 13, count 0 2006.183.07:36:28.22#ibcon#about to write, iclass 13, count 0 2006.183.07:36:28.22#ibcon#wrote, iclass 13, count 0 2006.183.07:36:28.22#ibcon#about to read 3, iclass 13, count 0 2006.183.07:36:28.25#ibcon#read 3, iclass 13, count 0 2006.183.07:36:28.25#ibcon#about to read 4, iclass 13, count 0 2006.183.07:36:28.25#ibcon#read 4, iclass 13, count 0 2006.183.07:36:28.25#ibcon#about to read 5, iclass 13, count 0 2006.183.07:36:28.25#ibcon#read 5, iclass 13, count 0 2006.183.07:36:28.25#ibcon#about to read 6, iclass 13, count 0 2006.183.07:36:28.25#ibcon#read 6, iclass 13, count 0 2006.183.07:36:28.25#ibcon#end of sib2, iclass 13, count 0 2006.183.07:36:28.25#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:36:28.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:36:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:36:28.25#ibcon#*before write, iclass 13, count 0 2006.183.07:36:28.25#ibcon#enter sib2, iclass 13, count 0 2006.183.07:36:28.25#ibcon#flushed, iclass 13, count 0 2006.183.07:36:28.25#ibcon#about to write, iclass 13, count 0 2006.183.07:36:28.25#ibcon#wrote, iclass 13, count 0 2006.183.07:36:28.25#ibcon#about to read 3, iclass 13, count 0 2006.183.07:36:28.28#ibcon#read 3, iclass 13, count 0 2006.183.07:36:28.28#ibcon#about to read 4, iclass 13, count 0 2006.183.07:36:28.28#ibcon#read 4, iclass 13, count 0 2006.183.07:36:28.28#ibcon#about to read 5, iclass 13, count 0 2006.183.07:36:28.28#ibcon#read 5, iclass 13, count 0 2006.183.07:36:28.28#ibcon#about to read 6, iclass 13, count 0 2006.183.07:36:28.28#ibcon#read 6, iclass 13, count 0 2006.183.07:36:28.28#ibcon#end of sib2, iclass 13, count 0 2006.183.07:36:28.28#ibcon#*after write, iclass 13, count 0 2006.183.07:36:28.28#ibcon#*before return 0, iclass 13, count 0 2006.183.07:36:28.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:28.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:28.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:36:28.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:36:28.28$vc4f8/va=2,7 2006.183.07:36:28.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:36:28.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:36:28.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:28.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:28.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:28.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:28.35#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:36:28.35#ibcon#first serial, iclass 15, count 2 2006.183.07:36:28.35#ibcon#enter sib2, iclass 15, count 2 2006.183.07:36:28.35#ibcon#flushed, iclass 15, count 2 2006.183.07:36:28.35#ibcon#about to write, iclass 15, count 2 2006.183.07:36:28.35#ibcon#wrote, iclass 15, count 2 2006.183.07:36:28.35#ibcon#about to read 3, iclass 15, count 2 2006.183.07:36:28.37#ibcon#read 3, iclass 15, count 2 2006.183.07:36:28.37#ibcon#about to read 4, iclass 15, count 2 2006.183.07:36:28.37#ibcon#read 4, iclass 15, count 2 2006.183.07:36:28.37#ibcon#about to read 5, iclass 15, count 2 2006.183.07:36:28.37#ibcon#read 5, iclass 15, count 2 2006.183.07:36:28.37#ibcon#about to read 6, iclass 15, count 2 2006.183.07:36:28.37#ibcon#read 6, iclass 15, count 2 2006.183.07:36:28.37#ibcon#end of sib2, iclass 15, count 2 2006.183.07:36:28.37#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:36:28.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:36:28.37#ibcon#[25=AT02-07\r\n] 2006.183.07:36:28.37#ibcon#*before write, iclass 15, count 2 2006.183.07:36:28.37#ibcon#enter sib2, iclass 15, count 2 2006.183.07:36:28.37#ibcon#flushed, iclass 15, count 2 2006.183.07:36:28.37#ibcon#about to write, iclass 15, count 2 2006.183.07:36:28.37#ibcon#wrote, iclass 15, count 2 2006.183.07:36:28.37#ibcon#about to read 3, iclass 15, count 2 2006.183.07:36:28.39#ibcon#read 3, iclass 15, count 2 2006.183.07:36:28.39#ibcon#about to read 4, iclass 15, count 2 2006.183.07:36:28.39#ibcon#read 4, iclass 15, count 2 2006.183.07:36:28.39#ibcon#about to read 5, iclass 15, count 2 2006.183.07:36:28.39#ibcon#read 5, iclass 15, count 2 2006.183.07:36:28.39#ibcon#about to read 6, iclass 15, count 2 2006.183.07:36:28.39#ibcon#read 6, iclass 15, count 2 2006.183.07:36:28.39#ibcon#end of sib2, iclass 15, count 2 2006.183.07:36:28.39#ibcon#*after write, iclass 15, count 2 2006.183.07:36:28.39#ibcon#*before return 0, iclass 15, count 2 2006.183.07:36:28.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:28.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:28.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:36:28.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:28.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:28.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:28.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:28.51#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:36:28.51#ibcon#first serial, iclass 15, count 0 2006.183.07:36:28.51#ibcon#enter sib2, iclass 15, count 0 2006.183.07:36:28.51#ibcon#flushed, iclass 15, count 0 2006.183.07:36:28.51#ibcon#about to write, iclass 15, count 0 2006.183.07:36:28.51#ibcon#wrote, iclass 15, count 0 2006.183.07:36:28.51#ibcon#about to read 3, iclass 15, count 0 2006.183.07:36:28.53#ibcon#read 3, iclass 15, count 0 2006.183.07:36:28.53#ibcon#about to read 4, iclass 15, count 0 2006.183.07:36:28.53#ibcon#read 4, iclass 15, count 0 2006.183.07:36:28.53#ibcon#about to read 5, iclass 15, count 0 2006.183.07:36:28.53#ibcon#read 5, iclass 15, count 0 2006.183.07:36:28.53#ibcon#about to read 6, iclass 15, count 0 2006.183.07:36:28.53#ibcon#read 6, iclass 15, count 0 2006.183.07:36:28.53#ibcon#end of sib2, iclass 15, count 0 2006.183.07:36:28.53#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:36:28.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:36:28.53#ibcon#[25=USB\r\n] 2006.183.07:36:28.53#ibcon#*before write, iclass 15, count 0 2006.183.07:36:28.53#ibcon#enter sib2, iclass 15, count 0 2006.183.07:36:28.53#ibcon#flushed, iclass 15, count 0 2006.183.07:36:28.53#ibcon#about to write, iclass 15, count 0 2006.183.07:36:28.53#ibcon#wrote, iclass 15, count 0 2006.183.07:36:28.53#ibcon#about to read 3, iclass 15, count 0 2006.183.07:36:28.56#ibcon#read 3, iclass 15, count 0 2006.183.07:36:28.56#ibcon#about to read 4, iclass 15, count 0 2006.183.07:36:28.56#ibcon#read 4, iclass 15, count 0 2006.183.07:36:28.56#ibcon#about to read 5, iclass 15, count 0 2006.183.07:36:28.56#ibcon#read 5, iclass 15, count 0 2006.183.07:36:28.56#ibcon#about to read 6, iclass 15, count 0 2006.183.07:36:28.56#ibcon#read 6, iclass 15, count 0 2006.183.07:36:28.56#ibcon#end of sib2, iclass 15, count 0 2006.183.07:36:28.56#ibcon#*after write, iclass 15, count 0 2006.183.07:36:28.56#ibcon#*before return 0, iclass 15, count 0 2006.183.07:36:28.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:28.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:28.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:36:28.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:36:28.56$vc4f8/valo=3,672.99 2006.183.07:36:28.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:36:28.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:36:28.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:28.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:28.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:28.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:28.56#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:36:28.56#ibcon#first serial, iclass 17, count 0 2006.183.07:36:28.56#ibcon#enter sib2, iclass 17, count 0 2006.183.07:36:28.56#ibcon#flushed, iclass 17, count 0 2006.183.07:36:28.56#ibcon#about to write, iclass 17, count 0 2006.183.07:36:28.56#ibcon#wrote, iclass 17, count 0 2006.183.07:36:28.56#ibcon#about to read 3, iclass 17, count 0 2006.183.07:36:28.59#ibcon#read 3, iclass 17, count 0 2006.183.07:36:28.59#ibcon#about to read 4, iclass 17, count 0 2006.183.07:36:28.59#ibcon#read 4, iclass 17, count 0 2006.183.07:36:28.59#ibcon#about to read 5, iclass 17, count 0 2006.183.07:36:28.59#ibcon#read 5, iclass 17, count 0 2006.183.07:36:28.59#ibcon#about to read 6, iclass 17, count 0 2006.183.07:36:28.59#ibcon#read 6, iclass 17, count 0 2006.183.07:36:28.59#ibcon#end of sib2, iclass 17, count 0 2006.183.07:36:28.59#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:36:28.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:36:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:36:28.59#ibcon#*before write, iclass 17, count 0 2006.183.07:36:28.59#ibcon#enter sib2, iclass 17, count 0 2006.183.07:36:28.59#ibcon#flushed, iclass 17, count 0 2006.183.07:36:28.59#ibcon#about to write, iclass 17, count 0 2006.183.07:36:28.59#ibcon#wrote, iclass 17, count 0 2006.183.07:36:28.59#ibcon#about to read 3, iclass 17, count 0 2006.183.07:36:28.63#ibcon#read 3, iclass 17, count 0 2006.183.07:36:28.63#ibcon#about to read 4, iclass 17, count 0 2006.183.07:36:28.63#ibcon#read 4, iclass 17, count 0 2006.183.07:36:28.63#ibcon#about to read 5, iclass 17, count 0 2006.183.07:36:28.63#ibcon#read 5, iclass 17, count 0 2006.183.07:36:28.63#ibcon#about to read 6, iclass 17, count 0 2006.183.07:36:28.63#ibcon#read 6, iclass 17, count 0 2006.183.07:36:28.63#ibcon#end of sib2, iclass 17, count 0 2006.183.07:36:28.63#ibcon#*after write, iclass 17, count 0 2006.183.07:36:28.63#ibcon#*before return 0, iclass 17, count 0 2006.183.07:36:28.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:28.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:28.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:36:28.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:36:28.63$vc4f8/va=3,6 2006.183.07:36:28.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:36:28.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:36:28.63#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:28.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:28.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:28.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:28.69#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:36:28.69#ibcon#first serial, iclass 19, count 2 2006.183.07:36:28.69#ibcon#enter sib2, iclass 19, count 2 2006.183.07:36:28.69#ibcon#flushed, iclass 19, count 2 2006.183.07:36:28.69#ibcon#about to write, iclass 19, count 2 2006.183.07:36:28.69#ibcon#wrote, iclass 19, count 2 2006.183.07:36:28.69#ibcon#about to read 3, iclass 19, count 2 2006.183.07:36:28.70#ibcon#read 3, iclass 19, count 2 2006.183.07:36:28.70#ibcon#about to read 4, iclass 19, count 2 2006.183.07:36:28.70#ibcon#read 4, iclass 19, count 2 2006.183.07:36:28.70#ibcon#about to read 5, iclass 19, count 2 2006.183.07:36:28.70#ibcon#read 5, iclass 19, count 2 2006.183.07:36:28.70#ibcon#about to read 6, iclass 19, count 2 2006.183.07:36:28.70#ibcon#read 6, iclass 19, count 2 2006.183.07:36:28.70#ibcon#end of sib2, iclass 19, count 2 2006.183.07:36:28.70#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:36:28.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:36:28.70#ibcon#[25=AT03-06\r\n] 2006.183.07:36:28.70#ibcon#*before write, iclass 19, count 2 2006.183.07:36:28.70#ibcon#enter sib2, iclass 19, count 2 2006.183.07:36:28.70#ibcon#flushed, iclass 19, count 2 2006.183.07:36:28.70#ibcon#about to write, iclass 19, count 2 2006.183.07:36:28.70#ibcon#wrote, iclass 19, count 2 2006.183.07:36:28.70#ibcon#about to read 3, iclass 19, count 2 2006.183.07:36:28.73#ibcon#read 3, iclass 19, count 2 2006.183.07:36:28.73#ibcon#about to read 4, iclass 19, count 2 2006.183.07:36:28.73#ibcon#read 4, iclass 19, count 2 2006.183.07:36:28.73#ibcon#about to read 5, iclass 19, count 2 2006.183.07:36:28.73#ibcon#read 5, iclass 19, count 2 2006.183.07:36:28.73#ibcon#about to read 6, iclass 19, count 2 2006.183.07:36:28.73#ibcon#read 6, iclass 19, count 2 2006.183.07:36:28.73#ibcon#end of sib2, iclass 19, count 2 2006.183.07:36:28.73#ibcon#*after write, iclass 19, count 2 2006.183.07:36:28.73#ibcon#*before return 0, iclass 19, count 2 2006.183.07:36:28.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:28.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:28.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:36:28.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:28.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:28.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:28.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:28.85#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:36:28.85#ibcon#first serial, iclass 19, count 0 2006.183.07:36:28.85#ibcon#enter sib2, iclass 19, count 0 2006.183.07:36:28.85#ibcon#flushed, iclass 19, count 0 2006.183.07:36:28.85#ibcon#about to write, iclass 19, count 0 2006.183.07:36:28.85#ibcon#wrote, iclass 19, count 0 2006.183.07:36:28.85#ibcon#about to read 3, iclass 19, count 0 2006.183.07:36:28.87#ibcon#read 3, iclass 19, count 0 2006.183.07:36:28.87#ibcon#about to read 4, iclass 19, count 0 2006.183.07:36:28.87#ibcon#read 4, iclass 19, count 0 2006.183.07:36:28.87#ibcon#about to read 5, iclass 19, count 0 2006.183.07:36:28.87#ibcon#read 5, iclass 19, count 0 2006.183.07:36:28.87#ibcon#about to read 6, iclass 19, count 0 2006.183.07:36:28.87#ibcon#read 6, iclass 19, count 0 2006.183.07:36:28.87#ibcon#end of sib2, iclass 19, count 0 2006.183.07:36:28.87#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:36:28.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:36:28.87#ibcon#[25=USB\r\n] 2006.183.07:36:28.87#ibcon#*before write, iclass 19, count 0 2006.183.07:36:28.87#ibcon#enter sib2, iclass 19, count 0 2006.183.07:36:28.87#ibcon#flushed, iclass 19, count 0 2006.183.07:36:28.87#ibcon#about to write, iclass 19, count 0 2006.183.07:36:28.87#ibcon#wrote, iclass 19, count 0 2006.183.07:36:28.87#ibcon#about to read 3, iclass 19, count 0 2006.183.07:36:28.90#ibcon#read 3, iclass 19, count 0 2006.183.07:36:28.90#ibcon#about to read 4, iclass 19, count 0 2006.183.07:36:28.90#ibcon#read 4, iclass 19, count 0 2006.183.07:36:28.90#ibcon#about to read 5, iclass 19, count 0 2006.183.07:36:28.90#ibcon#read 5, iclass 19, count 0 2006.183.07:36:28.90#ibcon#about to read 6, iclass 19, count 0 2006.183.07:36:28.90#ibcon#read 6, iclass 19, count 0 2006.183.07:36:28.90#ibcon#end of sib2, iclass 19, count 0 2006.183.07:36:28.90#ibcon#*after write, iclass 19, count 0 2006.183.07:36:28.90#ibcon#*before return 0, iclass 19, count 0 2006.183.07:36:28.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:28.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:28.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:36:28.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:36:28.90$vc4f8/valo=4,832.99 2006.183.07:36:28.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:36:28.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:36:28.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:28.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:28.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:28.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:28.90#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:36:28.90#ibcon#first serial, iclass 21, count 0 2006.183.07:36:28.90#ibcon#enter sib2, iclass 21, count 0 2006.183.07:36:28.90#ibcon#flushed, iclass 21, count 0 2006.183.07:36:28.90#ibcon#about to write, iclass 21, count 0 2006.183.07:36:28.90#ibcon#wrote, iclass 21, count 0 2006.183.07:36:28.90#ibcon#about to read 3, iclass 21, count 0 2006.183.07:36:28.93#ibcon#read 3, iclass 21, count 0 2006.183.07:36:28.93#ibcon#about to read 4, iclass 21, count 0 2006.183.07:36:28.93#ibcon#read 4, iclass 21, count 0 2006.183.07:36:28.93#ibcon#about to read 5, iclass 21, count 0 2006.183.07:36:28.93#ibcon#read 5, iclass 21, count 0 2006.183.07:36:28.93#ibcon#about to read 6, iclass 21, count 0 2006.183.07:36:28.93#ibcon#read 6, iclass 21, count 0 2006.183.07:36:28.93#ibcon#end of sib2, iclass 21, count 0 2006.183.07:36:28.93#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:36:28.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:36:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:36:28.93#ibcon#*before write, iclass 21, count 0 2006.183.07:36:28.93#ibcon#enter sib2, iclass 21, count 0 2006.183.07:36:28.93#ibcon#flushed, iclass 21, count 0 2006.183.07:36:28.93#ibcon#about to write, iclass 21, count 0 2006.183.07:36:28.93#ibcon#wrote, iclass 21, count 0 2006.183.07:36:28.93#ibcon#about to read 3, iclass 21, count 0 2006.183.07:36:28.97#ibcon#read 3, iclass 21, count 0 2006.183.07:36:28.97#ibcon#about to read 4, iclass 21, count 0 2006.183.07:36:28.97#ibcon#read 4, iclass 21, count 0 2006.183.07:36:28.97#ibcon#about to read 5, iclass 21, count 0 2006.183.07:36:28.97#ibcon#read 5, iclass 21, count 0 2006.183.07:36:28.97#ibcon#about to read 6, iclass 21, count 0 2006.183.07:36:28.97#ibcon#read 6, iclass 21, count 0 2006.183.07:36:28.97#ibcon#end of sib2, iclass 21, count 0 2006.183.07:36:28.97#ibcon#*after write, iclass 21, count 0 2006.183.07:36:28.97#ibcon#*before return 0, iclass 21, count 0 2006.183.07:36:28.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:28.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:28.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:36:28.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:36:28.97$vc4f8/va=4,7 2006.183.07:36:28.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:36:28.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:36:28.97#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:28.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:29.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:29.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:29.02#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:36:29.02#ibcon#first serial, iclass 23, count 2 2006.183.07:36:29.02#ibcon#enter sib2, iclass 23, count 2 2006.183.07:36:29.02#ibcon#flushed, iclass 23, count 2 2006.183.07:36:29.02#ibcon#about to write, iclass 23, count 2 2006.183.07:36:29.02#ibcon#wrote, iclass 23, count 2 2006.183.07:36:29.02#ibcon#about to read 3, iclass 23, count 2 2006.183.07:36:29.04#ibcon#read 3, iclass 23, count 2 2006.183.07:36:29.04#ibcon#about to read 4, iclass 23, count 2 2006.183.07:36:29.04#ibcon#read 4, iclass 23, count 2 2006.183.07:36:29.04#ibcon#about to read 5, iclass 23, count 2 2006.183.07:36:29.04#ibcon#read 5, iclass 23, count 2 2006.183.07:36:29.04#ibcon#about to read 6, iclass 23, count 2 2006.183.07:36:29.04#ibcon#read 6, iclass 23, count 2 2006.183.07:36:29.04#ibcon#end of sib2, iclass 23, count 2 2006.183.07:36:29.04#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:36:29.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:36:29.04#ibcon#[25=AT04-07\r\n] 2006.183.07:36:29.04#ibcon#*before write, iclass 23, count 2 2006.183.07:36:29.04#ibcon#enter sib2, iclass 23, count 2 2006.183.07:36:29.04#ibcon#flushed, iclass 23, count 2 2006.183.07:36:29.04#ibcon#about to write, iclass 23, count 2 2006.183.07:36:29.04#ibcon#wrote, iclass 23, count 2 2006.183.07:36:29.04#ibcon#about to read 3, iclass 23, count 2 2006.183.07:36:29.07#ibcon#read 3, iclass 23, count 2 2006.183.07:36:29.07#ibcon#about to read 4, iclass 23, count 2 2006.183.07:36:29.07#ibcon#read 4, iclass 23, count 2 2006.183.07:36:29.07#ibcon#about to read 5, iclass 23, count 2 2006.183.07:36:29.07#ibcon#read 5, iclass 23, count 2 2006.183.07:36:29.07#ibcon#about to read 6, iclass 23, count 2 2006.183.07:36:29.07#ibcon#read 6, iclass 23, count 2 2006.183.07:36:29.07#ibcon#end of sib2, iclass 23, count 2 2006.183.07:36:29.07#ibcon#*after write, iclass 23, count 2 2006.183.07:36:29.07#ibcon#*before return 0, iclass 23, count 2 2006.183.07:36:29.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:29.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:29.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:36:29.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:29.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:29.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:29.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:29.19#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:36:29.19#ibcon#first serial, iclass 23, count 0 2006.183.07:36:29.19#ibcon#enter sib2, iclass 23, count 0 2006.183.07:36:29.19#ibcon#flushed, iclass 23, count 0 2006.183.07:36:29.19#ibcon#about to write, iclass 23, count 0 2006.183.07:36:29.19#ibcon#wrote, iclass 23, count 0 2006.183.07:36:29.19#ibcon#about to read 3, iclass 23, count 0 2006.183.07:36:29.21#ibcon#read 3, iclass 23, count 0 2006.183.07:36:29.21#ibcon#about to read 4, iclass 23, count 0 2006.183.07:36:29.21#ibcon#read 4, iclass 23, count 0 2006.183.07:36:29.21#ibcon#about to read 5, iclass 23, count 0 2006.183.07:36:29.21#ibcon#read 5, iclass 23, count 0 2006.183.07:36:29.21#ibcon#about to read 6, iclass 23, count 0 2006.183.07:36:29.21#ibcon#read 6, iclass 23, count 0 2006.183.07:36:29.21#ibcon#end of sib2, iclass 23, count 0 2006.183.07:36:29.21#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:36:29.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:36:29.21#ibcon#[25=USB\r\n] 2006.183.07:36:29.21#ibcon#*before write, iclass 23, count 0 2006.183.07:36:29.21#ibcon#enter sib2, iclass 23, count 0 2006.183.07:36:29.21#ibcon#flushed, iclass 23, count 0 2006.183.07:36:29.21#ibcon#about to write, iclass 23, count 0 2006.183.07:36:29.21#ibcon#wrote, iclass 23, count 0 2006.183.07:36:29.21#ibcon#about to read 3, iclass 23, count 0 2006.183.07:36:29.24#ibcon#read 3, iclass 23, count 0 2006.183.07:36:29.24#ibcon#about to read 4, iclass 23, count 0 2006.183.07:36:29.24#ibcon#read 4, iclass 23, count 0 2006.183.07:36:29.24#ibcon#about to read 5, iclass 23, count 0 2006.183.07:36:29.24#ibcon#read 5, iclass 23, count 0 2006.183.07:36:29.24#ibcon#about to read 6, iclass 23, count 0 2006.183.07:36:29.24#ibcon#read 6, iclass 23, count 0 2006.183.07:36:29.24#ibcon#end of sib2, iclass 23, count 0 2006.183.07:36:29.24#ibcon#*after write, iclass 23, count 0 2006.183.07:36:29.24#ibcon#*before return 0, iclass 23, count 0 2006.183.07:36:29.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:29.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:29.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:36:29.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:36:29.24$vc4f8/valo=5,652.99 2006.183.07:36:29.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:36:29.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:36:29.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:29.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:29.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:29.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:29.24#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:36:29.24#ibcon#first serial, iclass 25, count 0 2006.183.07:36:29.24#ibcon#enter sib2, iclass 25, count 0 2006.183.07:36:29.24#ibcon#flushed, iclass 25, count 0 2006.183.07:36:29.24#ibcon#about to write, iclass 25, count 0 2006.183.07:36:29.24#ibcon#wrote, iclass 25, count 0 2006.183.07:36:29.24#ibcon#about to read 3, iclass 25, count 0 2006.183.07:36:29.26#ibcon#read 3, iclass 25, count 0 2006.183.07:36:29.26#ibcon#about to read 4, iclass 25, count 0 2006.183.07:36:29.26#ibcon#read 4, iclass 25, count 0 2006.183.07:36:29.26#ibcon#about to read 5, iclass 25, count 0 2006.183.07:36:29.26#ibcon#read 5, iclass 25, count 0 2006.183.07:36:29.26#ibcon#about to read 6, iclass 25, count 0 2006.183.07:36:29.26#ibcon#read 6, iclass 25, count 0 2006.183.07:36:29.26#ibcon#end of sib2, iclass 25, count 0 2006.183.07:36:29.26#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:36:29.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:36:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:36:29.26#ibcon#*before write, iclass 25, count 0 2006.183.07:36:29.26#ibcon#enter sib2, iclass 25, count 0 2006.183.07:36:29.26#ibcon#flushed, iclass 25, count 0 2006.183.07:36:29.26#ibcon#about to write, iclass 25, count 0 2006.183.07:36:29.26#ibcon#wrote, iclass 25, count 0 2006.183.07:36:29.26#ibcon#about to read 3, iclass 25, count 0 2006.183.07:36:29.30#ibcon#read 3, iclass 25, count 0 2006.183.07:36:29.30#ibcon#about to read 4, iclass 25, count 0 2006.183.07:36:29.30#ibcon#read 4, iclass 25, count 0 2006.183.07:36:29.30#ibcon#about to read 5, iclass 25, count 0 2006.183.07:36:29.30#ibcon#read 5, iclass 25, count 0 2006.183.07:36:29.30#ibcon#about to read 6, iclass 25, count 0 2006.183.07:36:29.30#ibcon#read 6, iclass 25, count 0 2006.183.07:36:29.30#ibcon#end of sib2, iclass 25, count 0 2006.183.07:36:29.30#ibcon#*after write, iclass 25, count 0 2006.183.07:36:29.30#ibcon#*before return 0, iclass 25, count 0 2006.183.07:36:29.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:29.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:29.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:36:29.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:36:29.30$vc4f8/va=5,7 2006.183.07:36:29.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.07:36:29.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.07:36:29.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:29.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:29.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:29.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:29.36#ibcon#enter wrdev, iclass 27, count 2 2006.183.07:36:29.36#ibcon#first serial, iclass 27, count 2 2006.183.07:36:29.36#ibcon#enter sib2, iclass 27, count 2 2006.183.07:36:29.36#ibcon#flushed, iclass 27, count 2 2006.183.07:36:29.36#ibcon#about to write, iclass 27, count 2 2006.183.07:36:29.36#ibcon#wrote, iclass 27, count 2 2006.183.07:36:29.36#ibcon#about to read 3, iclass 27, count 2 2006.183.07:36:29.38#ibcon#read 3, iclass 27, count 2 2006.183.07:36:29.38#ibcon#about to read 4, iclass 27, count 2 2006.183.07:36:29.38#ibcon#read 4, iclass 27, count 2 2006.183.07:36:29.38#ibcon#about to read 5, iclass 27, count 2 2006.183.07:36:29.38#ibcon#read 5, iclass 27, count 2 2006.183.07:36:29.38#ibcon#about to read 6, iclass 27, count 2 2006.183.07:36:29.38#ibcon#read 6, iclass 27, count 2 2006.183.07:36:29.38#ibcon#end of sib2, iclass 27, count 2 2006.183.07:36:29.38#ibcon#*mode == 0, iclass 27, count 2 2006.183.07:36:29.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.07:36:29.38#ibcon#[25=AT05-07\r\n] 2006.183.07:36:29.38#ibcon#*before write, iclass 27, count 2 2006.183.07:36:29.38#ibcon#enter sib2, iclass 27, count 2 2006.183.07:36:29.38#ibcon#flushed, iclass 27, count 2 2006.183.07:36:29.38#ibcon#about to write, iclass 27, count 2 2006.183.07:36:29.38#ibcon#wrote, iclass 27, count 2 2006.183.07:36:29.38#ibcon#about to read 3, iclass 27, count 2 2006.183.07:36:29.41#ibcon#read 3, iclass 27, count 2 2006.183.07:36:29.41#ibcon#about to read 4, iclass 27, count 2 2006.183.07:36:29.41#ibcon#read 4, iclass 27, count 2 2006.183.07:36:29.41#ibcon#about to read 5, iclass 27, count 2 2006.183.07:36:29.41#ibcon#read 5, iclass 27, count 2 2006.183.07:36:29.41#ibcon#about to read 6, iclass 27, count 2 2006.183.07:36:29.41#ibcon#read 6, iclass 27, count 2 2006.183.07:36:29.41#ibcon#end of sib2, iclass 27, count 2 2006.183.07:36:29.41#ibcon#*after write, iclass 27, count 2 2006.183.07:36:29.41#ibcon#*before return 0, iclass 27, count 2 2006.183.07:36:29.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:29.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:29.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.07:36:29.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:29.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:29.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:29.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:29.53#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:36:29.53#ibcon#first serial, iclass 27, count 0 2006.183.07:36:29.53#ibcon#enter sib2, iclass 27, count 0 2006.183.07:36:29.53#ibcon#flushed, iclass 27, count 0 2006.183.07:36:29.53#ibcon#about to write, iclass 27, count 0 2006.183.07:36:29.53#ibcon#wrote, iclass 27, count 0 2006.183.07:36:29.53#ibcon#about to read 3, iclass 27, count 0 2006.183.07:36:29.55#ibcon#read 3, iclass 27, count 0 2006.183.07:36:29.55#ibcon#about to read 4, iclass 27, count 0 2006.183.07:36:29.55#ibcon#read 4, iclass 27, count 0 2006.183.07:36:29.55#ibcon#about to read 5, iclass 27, count 0 2006.183.07:36:29.55#ibcon#read 5, iclass 27, count 0 2006.183.07:36:29.55#ibcon#about to read 6, iclass 27, count 0 2006.183.07:36:29.55#ibcon#read 6, iclass 27, count 0 2006.183.07:36:29.55#ibcon#end of sib2, iclass 27, count 0 2006.183.07:36:29.55#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:36:29.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:36:29.55#ibcon#[25=USB\r\n] 2006.183.07:36:29.55#ibcon#*before write, iclass 27, count 0 2006.183.07:36:29.55#ibcon#enter sib2, iclass 27, count 0 2006.183.07:36:29.55#ibcon#flushed, iclass 27, count 0 2006.183.07:36:29.55#ibcon#about to write, iclass 27, count 0 2006.183.07:36:29.55#ibcon#wrote, iclass 27, count 0 2006.183.07:36:29.55#ibcon#about to read 3, iclass 27, count 0 2006.183.07:36:29.58#ibcon#read 3, iclass 27, count 0 2006.183.07:36:29.58#ibcon#about to read 4, iclass 27, count 0 2006.183.07:36:29.58#ibcon#read 4, iclass 27, count 0 2006.183.07:36:29.58#ibcon#about to read 5, iclass 27, count 0 2006.183.07:36:29.58#ibcon#read 5, iclass 27, count 0 2006.183.07:36:29.58#ibcon#about to read 6, iclass 27, count 0 2006.183.07:36:29.58#ibcon#read 6, iclass 27, count 0 2006.183.07:36:29.58#ibcon#end of sib2, iclass 27, count 0 2006.183.07:36:29.58#ibcon#*after write, iclass 27, count 0 2006.183.07:36:29.58#ibcon#*before return 0, iclass 27, count 0 2006.183.07:36:29.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:29.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:29.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:36:29.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:36:29.58$vc4f8/valo=6,772.99 2006.183.07:36:29.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.07:36:29.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.07:36:29.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:29.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:29.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:29.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:29.58#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:36:29.58#ibcon#first serial, iclass 29, count 0 2006.183.07:36:29.58#ibcon#enter sib2, iclass 29, count 0 2006.183.07:36:29.58#ibcon#flushed, iclass 29, count 0 2006.183.07:36:29.58#ibcon#about to write, iclass 29, count 0 2006.183.07:36:29.58#ibcon#wrote, iclass 29, count 0 2006.183.07:36:29.58#ibcon#about to read 3, iclass 29, count 0 2006.183.07:36:29.61#ibcon#read 3, iclass 29, count 0 2006.183.07:36:29.61#ibcon#about to read 4, iclass 29, count 0 2006.183.07:36:29.61#ibcon#read 4, iclass 29, count 0 2006.183.07:36:29.61#ibcon#about to read 5, iclass 29, count 0 2006.183.07:36:29.61#ibcon#read 5, iclass 29, count 0 2006.183.07:36:29.61#ibcon#about to read 6, iclass 29, count 0 2006.183.07:36:29.61#ibcon#read 6, iclass 29, count 0 2006.183.07:36:29.61#ibcon#end of sib2, iclass 29, count 0 2006.183.07:36:29.61#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:36:29.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:36:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:36:29.61#ibcon#*before write, iclass 29, count 0 2006.183.07:36:29.61#ibcon#enter sib2, iclass 29, count 0 2006.183.07:36:29.61#ibcon#flushed, iclass 29, count 0 2006.183.07:36:29.61#ibcon#about to write, iclass 29, count 0 2006.183.07:36:29.61#ibcon#wrote, iclass 29, count 0 2006.183.07:36:29.61#ibcon#about to read 3, iclass 29, count 0 2006.183.07:36:29.65#ibcon#read 3, iclass 29, count 0 2006.183.07:36:29.65#ibcon#about to read 4, iclass 29, count 0 2006.183.07:36:29.65#ibcon#read 4, iclass 29, count 0 2006.183.07:36:29.65#ibcon#about to read 5, iclass 29, count 0 2006.183.07:36:29.65#ibcon#read 5, iclass 29, count 0 2006.183.07:36:29.65#ibcon#about to read 6, iclass 29, count 0 2006.183.07:36:29.65#ibcon#read 6, iclass 29, count 0 2006.183.07:36:29.65#ibcon#end of sib2, iclass 29, count 0 2006.183.07:36:29.65#ibcon#*after write, iclass 29, count 0 2006.183.07:36:29.65#ibcon#*before return 0, iclass 29, count 0 2006.183.07:36:29.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:29.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:29.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:36:29.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:36:29.65$vc4f8/va=6,6 2006.183.07:36:29.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.07:36:29.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.07:36:29.65#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:29.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:29.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:29.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:29.70#ibcon#enter wrdev, iclass 31, count 2 2006.183.07:36:29.70#ibcon#first serial, iclass 31, count 2 2006.183.07:36:29.70#ibcon#enter sib2, iclass 31, count 2 2006.183.07:36:29.70#ibcon#flushed, iclass 31, count 2 2006.183.07:36:29.70#ibcon#about to write, iclass 31, count 2 2006.183.07:36:29.70#ibcon#wrote, iclass 31, count 2 2006.183.07:36:29.70#ibcon#about to read 3, iclass 31, count 2 2006.183.07:36:29.72#ibcon#read 3, iclass 31, count 2 2006.183.07:36:29.72#ibcon#about to read 4, iclass 31, count 2 2006.183.07:36:29.72#ibcon#read 4, iclass 31, count 2 2006.183.07:36:29.72#ibcon#about to read 5, iclass 31, count 2 2006.183.07:36:29.72#ibcon#read 5, iclass 31, count 2 2006.183.07:36:29.72#ibcon#about to read 6, iclass 31, count 2 2006.183.07:36:29.72#ibcon#read 6, iclass 31, count 2 2006.183.07:36:29.72#ibcon#end of sib2, iclass 31, count 2 2006.183.07:36:29.72#ibcon#*mode == 0, iclass 31, count 2 2006.183.07:36:29.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.07:36:29.72#ibcon#[25=AT06-06\r\n] 2006.183.07:36:29.72#ibcon#*before write, iclass 31, count 2 2006.183.07:36:29.72#ibcon#enter sib2, iclass 31, count 2 2006.183.07:36:29.72#ibcon#flushed, iclass 31, count 2 2006.183.07:36:29.72#ibcon#about to write, iclass 31, count 2 2006.183.07:36:29.72#ibcon#wrote, iclass 31, count 2 2006.183.07:36:29.72#ibcon#about to read 3, iclass 31, count 2 2006.183.07:36:29.75#ibcon#read 3, iclass 31, count 2 2006.183.07:36:29.75#ibcon#about to read 4, iclass 31, count 2 2006.183.07:36:29.75#ibcon#read 4, iclass 31, count 2 2006.183.07:36:29.75#ibcon#about to read 5, iclass 31, count 2 2006.183.07:36:29.75#ibcon#read 5, iclass 31, count 2 2006.183.07:36:29.75#ibcon#about to read 6, iclass 31, count 2 2006.183.07:36:29.75#ibcon#read 6, iclass 31, count 2 2006.183.07:36:29.75#ibcon#end of sib2, iclass 31, count 2 2006.183.07:36:29.75#ibcon#*after write, iclass 31, count 2 2006.183.07:36:29.75#ibcon#*before return 0, iclass 31, count 2 2006.183.07:36:29.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:29.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:29.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.07:36:29.75#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:29.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:29.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:29.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:29.87#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:36:29.87#ibcon#first serial, iclass 31, count 0 2006.183.07:36:29.87#ibcon#enter sib2, iclass 31, count 0 2006.183.07:36:29.87#ibcon#flushed, iclass 31, count 0 2006.183.07:36:29.87#ibcon#about to write, iclass 31, count 0 2006.183.07:36:29.87#ibcon#wrote, iclass 31, count 0 2006.183.07:36:29.87#ibcon#about to read 3, iclass 31, count 0 2006.183.07:36:29.89#ibcon#read 3, iclass 31, count 0 2006.183.07:36:29.89#ibcon#about to read 4, iclass 31, count 0 2006.183.07:36:29.89#ibcon#read 4, iclass 31, count 0 2006.183.07:36:29.89#ibcon#about to read 5, iclass 31, count 0 2006.183.07:36:29.89#ibcon#read 5, iclass 31, count 0 2006.183.07:36:29.89#ibcon#about to read 6, iclass 31, count 0 2006.183.07:36:29.89#ibcon#read 6, iclass 31, count 0 2006.183.07:36:29.89#ibcon#end of sib2, iclass 31, count 0 2006.183.07:36:29.89#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:36:29.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:36:29.89#ibcon#[25=USB\r\n] 2006.183.07:36:29.89#ibcon#*before write, iclass 31, count 0 2006.183.07:36:29.89#ibcon#enter sib2, iclass 31, count 0 2006.183.07:36:29.89#ibcon#flushed, iclass 31, count 0 2006.183.07:36:29.89#ibcon#about to write, iclass 31, count 0 2006.183.07:36:29.89#ibcon#wrote, iclass 31, count 0 2006.183.07:36:29.89#ibcon#about to read 3, iclass 31, count 0 2006.183.07:36:29.92#ibcon#read 3, iclass 31, count 0 2006.183.07:36:29.92#ibcon#about to read 4, iclass 31, count 0 2006.183.07:36:29.92#ibcon#read 4, iclass 31, count 0 2006.183.07:36:29.92#ibcon#about to read 5, iclass 31, count 0 2006.183.07:36:29.92#ibcon#read 5, iclass 31, count 0 2006.183.07:36:29.92#ibcon#about to read 6, iclass 31, count 0 2006.183.07:36:29.92#ibcon#read 6, iclass 31, count 0 2006.183.07:36:29.92#ibcon#end of sib2, iclass 31, count 0 2006.183.07:36:29.92#ibcon#*after write, iclass 31, count 0 2006.183.07:36:29.92#ibcon#*before return 0, iclass 31, count 0 2006.183.07:36:29.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:29.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:29.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:36:29.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:36:29.92$vc4f8/valo=7,832.99 2006.183.07:36:29.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.07:36:29.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.07:36:29.92#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:29.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:29.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:29.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:29.92#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:36:29.92#ibcon#first serial, iclass 33, count 0 2006.183.07:36:29.92#ibcon#enter sib2, iclass 33, count 0 2006.183.07:36:29.92#ibcon#flushed, iclass 33, count 0 2006.183.07:36:29.92#ibcon#about to write, iclass 33, count 0 2006.183.07:36:29.92#ibcon#wrote, iclass 33, count 0 2006.183.07:36:29.92#ibcon#about to read 3, iclass 33, count 0 2006.183.07:36:29.94#ibcon#read 3, iclass 33, count 0 2006.183.07:36:29.94#ibcon#about to read 4, iclass 33, count 0 2006.183.07:36:29.94#ibcon#read 4, iclass 33, count 0 2006.183.07:36:29.94#ibcon#about to read 5, iclass 33, count 0 2006.183.07:36:29.94#ibcon#read 5, iclass 33, count 0 2006.183.07:36:29.94#ibcon#about to read 6, iclass 33, count 0 2006.183.07:36:29.94#ibcon#read 6, iclass 33, count 0 2006.183.07:36:29.94#ibcon#end of sib2, iclass 33, count 0 2006.183.07:36:29.94#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:36:29.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:36:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:36:29.94#ibcon#*before write, iclass 33, count 0 2006.183.07:36:29.94#ibcon#enter sib2, iclass 33, count 0 2006.183.07:36:29.94#ibcon#flushed, iclass 33, count 0 2006.183.07:36:29.94#ibcon#about to write, iclass 33, count 0 2006.183.07:36:29.94#ibcon#wrote, iclass 33, count 0 2006.183.07:36:29.94#ibcon#about to read 3, iclass 33, count 0 2006.183.07:36:29.98#ibcon#read 3, iclass 33, count 0 2006.183.07:36:29.98#ibcon#about to read 4, iclass 33, count 0 2006.183.07:36:29.98#ibcon#read 4, iclass 33, count 0 2006.183.07:36:29.98#ibcon#about to read 5, iclass 33, count 0 2006.183.07:36:29.98#ibcon#read 5, iclass 33, count 0 2006.183.07:36:29.98#ibcon#about to read 6, iclass 33, count 0 2006.183.07:36:29.98#ibcon#read 6, iclass 33, count 0 2006.183.07:36:29.98#ibcon#end of sib2, iclass 33, count 0 2006.183.07:36:29.98#ibcon#*after write, iclass 33, count 0 2006.183.07:36:29.98#ibcon#*before return 0, iclass 33, count 0 2006.183.07:36:29.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:29.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:29.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:36:29.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:36:29.98$vc4f8/va=7,6 2006.183.07:36:29.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.183.07:36:29.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.183.07:36:29.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:29.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:36:30.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:36:30.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:36:30.04#ibcon#enter wrdev, iclass 35, count 2 2006.183.07:36:30.04#ibcon#first serial, iclass 35, count 2 2006.183.07:36:30.04#ibcon#enter sib2, iclass 35, count 2 2006.183.07:36:30.04#ibcon#flushed, iclass 35, count 2 2006.183.07:36:30.04#ibcon#about to write, iclass 35, count 2 2006.183.07:36:30.04#ibcon#wrote, iclass 35, count 2 2006.183.07:36:30.04#ibcon#about to read 3, iclass 35, count 2 2006.183.07:36:30.06#ibcon#read 3, iclass 35, count 2 2006.183.07:36:30.06#ibcon#about to read 4, iclass 35, count 2 2006.183.07:36:30.06#ibcon#read 4, iclass 35, count 2 2006.183.07:36:30.06#ibcon#about to read 5, iclass 35, count 2 2006.183.07:36:30.06#ibcon#read 5, iclass 35, count 2 2006.183.07:36:30.06#ibcon#about to read 6, iclass 35, count 2 2006.183.07:36:30.06#ibcon#read 6, iclass 35, count 2 2006.183.07:36:30.06#ibcon#end of sib2, iclass 35, count 2 2006.183.07:36:30.06#ibcon#*mode == 0, iclass 35, count 2 2006.183.07:36:30.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.183.07:36:30.06#ibcon#[25=AT07-06\r\n] 2006.183.07:36:30.06#ibcon#*before write, iclass 35, count 2 2006.183.07:36:30.06#ibcon#enter sib2, iclass 35, count 2 2006.183.07:36:30.06#ibcon#flushed, iclass 35, count 2 2006.183.07:36:30.06#ibcon#about to write, iclass 35, count 2 2006.183.07:36:30.06#ibcon#wrote, iclass 35, count 2 2006.183.07:36:30.06#ibcon#about to read 3, iclass 35, count 2 2006.183.07:36:30.09#ibcon#read 3, iclass 35, count 2 2006.183.07:36:30.09#ibcon#about to read 4, iclass 35, count 2 2006.183.07:36:30.09#ibcon#read 4, iclass 35, count 2 2006.183.07:36:30.09#ibcon#about to read 5, iclass 35, count 2 2006.183.07:36:30.09#ibcon#read 5, iclass 35, count 2 2006.183.07:36:30.09#ibcon#about to read 6, iclass 35, count 2 2006.183.07:36:30.09#ibcon#read 6, iclass 35, count 2 2006.183.07:36:30.09#ibcon#end of sib2, iclass 35, count 2 2006.183.07:36:30.09#ibcon#*after write, iclass 35, count 2 2006.183.07:36:30.09#ibcon#*before return 0, iclass 35, count 2 2006.183.07:36:30.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:36:30.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:36:30.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.183.07:36:30.09#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:30.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:36:30.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:36:30.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:36:30.21#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:36:30.21#ibcon#first serial, iclass 35, count 0 2006.183.07:36:30.21#ibcon#enter sib2, iclass 35, count 0 2006.183.07:36:30.21#ibcon#flushed, iclass 35, count 0 2006.183.07:36:30.21#ibcon#about to write, iclass 35, count 0 2006.183.07:36:30.21#ibcon#wrote, iclass 35, count 0 2006.183.07:36:30.21#ibcon#about to read 3, iclass 35, count 0 2006.183.07:36:30.25#ibcon#read 3, iclass 35, count 0 2006.183.07:36:30.25#ibcon#about to read 4, iclass 35, count 0 2006.183.07:36:30.25#ibcon#read 4, iclass 35, count 0 2006.183.07:36:30.25#ibcon#about to read 5, iclass 35, count 0 2006.183.07:36:30.25#ibcon#read 5, iclass 35, count 0 2006.183.07:36:30.25#ibcon#about to read 6, iclass 35, count 0 2006.183.07:36:30.25#ibcon#read 6, iclass 35, count 0 2006.183.07:36:30.25#ibcon#end of sib2, iclass 35, count 0 2006.183.07:36:30.25#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:36:30.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:36:30.25#ibcon#[25=USB\r\n] 2006.183.07:36:30.25#ibcon#*before write, iclass 35, count 0 2006.183.07:36:30.25#ibcon#enter sib2, iclass 35, count 0 2006.183.07:36:30.25#ibcon#flushed, iclass 35, count 0 2006.183.07:36:30.25#ibcon#about to write, iclass 35, count 0 2006.183.07:36:30.25#ibcon#wrote, iclass 35, count 0 2006.183.07:36:30.25#ibcon#about to read 3, iclass 35, count 0 2006.183.07:36:30.27#ibcon#read 3, iclass 35, count 0 2006.183.07:36:30.27#ibcon#about to read 4, iclass 35, count 0 2006.183.07:36:30.27#ibcon#read 4, iclass 35, count 0 2006.183.07:36:30.27#ibcon#about to read 5, iclass 35, count 0 2006.183.07:36:30.27#ibcon#read 5, iclass 35, count 0 2006.183.07:36:30.27#ibcon#about to read 6, iclass 35, count 0 2006.183.07:36:30.27#ibcon#read 6, iclass 35, count 0 2006.183.07:36:30.27#ibcon#end of sib2, iclass 35, count 0 2006.183.07:36:30.27#ibcon#*after write, iclass 35, count 0 2006.183.07:36:30.27#ibcon#*before return 0, iclass 35, count 0 2006.183.07:36:30.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:36:30.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:36:30.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:36:30.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:36:30.27$vc4f8/valo=8,852.99 2006.183.07:36:30.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.07:36:30.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.07:36:30.27#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:30.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:36:30.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:36:30.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:36:30.27#ibcon#enter wrdev, iclass 37, count 0 2006.183.07:36:30.27#ibcon#first serial, iclass 37, count 0 2006.183.07:36:30.27#ibcon#enter sib2, iclass 37, count 0 2006.183.07:36:30.27#ibcon#flushed, iclass 37, count 0 2006.183.07:36:30.27#ibcon#about to write, iclass 37, count 0 2006.183.07:36:30.27#ibcon#wrote, iclass 37, count 0 2006.183.07:36:30.27#ibcon#about to read 3, iclass 37, count 0 2006.183.07:36:30.29#ibcon#read 3, iclass 37, count 0 2006.183.07:36:30.29#ibcon#about to read 4, iclass 37, count 0 2006.183.07:36:30.29#ibcon#read 4, iclass 37, count 0 2006.183.07:36:30.29#ibcon#about to read 5, iclass 37, count 0 2006.183.07:36:30.29#ibcon#read 5, iclass 37, count 0 2006.183.07:36:30.29#ibcon#about to read 6, iclass 37, count 0 2006.183.07:36:30.29#ibcon#read 6, iclass 37, count 0 2006.183.07:36:30.29#ibcon#end of sib2, iclass 37, count 0 2006.183.07:36:30.29#ibcon#*mode == 0, iclass 37, count 0 2006.183.07:36:30.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.07:36:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:36:30.29#ibcon#*before write, iclass 37, count 0 2006.183.07:36:30.29#ibcon#enter sib2, iclass 37, count 0 2006.183.07:36:30.29#ibcon#flushed, iclass 37, count 0 2006.183.07:36:30.29#ibcon#about to write, iclass 37, count 0 2006.183.07:36:30.29#ibcon#wrote, iclass 37, count 0 2006.183.07:36:30.29#ibcon#about to read 3, iclass 37, count 0 2006.183.07:36:30.34#ibcon#read 3, iclass 37, count 0 2006.183.07:36:30.34#ibcon#about to read 4, iclass 37, count 0 2006.183.07:36:30.34#ibcon#read 4, iclass 37, count 0 2006.183.07:36:30.34#ibcon#about to read 5, iclass 37, count 0 2006.183.07:36:30.34#ibcon#read 5, iclass 37, count 0 2006.183.07:36:30.34#ibcon#about to read 6, iclass 37, count 0 2006.183.07:36:30.34#ibcon#read 6, iclass 37, count 0 2006.183.07:36:30.34#ibcon#end of sib2, iclass 37, count 0 2006.183.07:36:30.34#ibcon#*after write, iclass 37, count 0 2006.183.07:36:30.34#ibcon#*before return 0, iclass 37, count 0 2006.183.07:36:30.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:36:30.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:36:30.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.07:36:30.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.07:36:30.34$vc4f8/va=8,7 2006.183.07:36:30.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.07:36:30.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.07:36:30.34#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:30.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:36:30.36#abcon#<5=/10 3.2 8.2 27.90 87 996.3\r\n> 2006.183.07:36:30.38#abcon#{5=INTERFACE CLEAR} 2006.183.07:36:30.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:36:30.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:36:30.38#ibcon#enter wrdev, iclass 40, count 2 2006.183.07:36:30.38#ibcon#first serial, iclass 40, count 2 2006.183.07:36:30.38#ibcon#enter sib2, iclass 40, count 2 2006.183.07:36:30.38#ibcon#flushed, iclass 40, count 2 2006.183.07:36:30.38#ibcon#about to write, iclass 40, count 2 2006.183.07:36:30.38#ibcon#wrote, iclass 40, count 2 2006.183.07:36:30.38#ibcon#about to read 3, iclass 40, count 2 2006.183.07:36:30.40#ibcon#read 3, iclass 40, count 2 2006.183.07:36:30.40#ibcon#about to read 4, iclass 40, count 2 2006.183.07:36:30.40#ibcon#read 4, iclass 40, count 2 2006.183.07:36:30.40#ibcon#about to read 5, iclass 40, count 2 2006.183.07:36:30.40#ibcon#read 5, iclass 40, count 2 2006.183.07:36:30.40#ibcon#about to read 6, iclass 40, count 2 2006.183.07:36:30.40#ibcon#read 6, iclass 40, count 2 2006.183.07:36:30.40#ibcon#end of sib2, iclass 40, count 2 2006.183.07:36:30.40#ibcon#*mode == 0, iclass 40, count 2 2006.183.07:36:30.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.07:36:30.40#ibcon#[25=AT08-07\r\n] 2006.183.07:36:30.40#ibcon#*before write, iclass 40, count 2 2006.183.07:36:30.40#ibcon#enter sib2, iclass 40, count 2 2006.183.07:36:30.40#ibcon#flushed, iclass 40, count 2 2006.183.07:36:30.40#ibcon#about to write, iclass 40, count 2 2006.183.07:36:30.40#ibcon#wrote, iclass 40, count 2 2006.183.07:36:30.40#ibcon#about to read 3, iclass 40, count 2 2006.183.07:36:30.43#ibcon#read 3, iclass 40, count 2 2006.183.07:36:30.43#ibcon#about to read 4, iclass 40, count 2 2006.183.07:36:30.43#ibcon#read 4, iclass 40, count 2 2006.183.07:36:30.43#ibcon#about to read 5, iclass 40, count 2 2006.183.07:36:30.43#ibcon#read 5, iclass 40, count 2 2006.183.07:36:30.43#ibcon#about to read 6, iclass 40, count 2 2006.183.07:36:30.43#ibcon#read 6, iclass 40, count 2 2006.183.07:36:30.43#ibcon#end of sib2, iclass 40, count 2 2006.183.07:36:30.43#ibcon#*after write, iclass 40, count 2 2006.183.07:36:30.43#ibcon#*before return 0, iclass 40, count 2 2006.183.07:36:30.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:36:30.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:36:30.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.07:36:30.43#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:30.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:36:30.44#abcon#[5=S1D000X0/0*\r\n] 2006.183.07:36:30.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:36:30.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:36:30.55#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:36:30.55#ibcon#first serial, iclass 40, count 0 2006.183.07:36:30.55#ibcon#enter sib2, iclass 40, count 0 2006.183.07:36:30.55#ibcon#flushed, iclass 40, count 0 2006.183.07:36:30.55#ibcon#about to write, iclass 40, count 0 2006.183.07:36:30.55#ibcon#wrote, iclass 40, count 0 2006.183.07:36:30.55#ibcon#about to read 3, iclass 40, count 0 2006.183.07:36:30.57#ibcon#read 3, iclass 40, count 0 2006.183.07:36:30.57#ibcon#about to read 4, iclass 40, count 0 2006.183.07:36:30.57#ibcon#read 4, iclass 40, count 0 2006.183.07:36:30.57#ibcon#about to read 5, iclass 40, count 0 2006.183.07:36:30.57#ibcon#read 5, iclass 40, count 0 2006.183.07:36:30.57#ibcon#about to read 6, iclass 40, count 0 2006.183.07:36:30.57#ibcon#read 6, iclass 40, count 0 2006.183.07:36:30.57#ibcon#end of sib2, iclass 40, count 0 2006.183.07:36:30.57#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:36:30.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:36:30.57#ibcon#[25=USB\r\n] 2006.183.07:36:30.57#ibcon#*before write, iclass 40, count 0 2006.183.07:36:30.57#ibcon#enter sib2, iclass 40, count 0 2006.183.07:36:30.57#ibcon#flushed, iclass 40, count 0 2006.183.07:36:30.57#ibcon#about to write, iclass 40, count 0 2006.183.07:36:30.57#ibcon#wrote, iclass 40, count 0 2006.183.07:36:30.57#ibcon#about to read 3, iclass 40, count 0 2006.183.07:36:30.60#ibcon#read 3, iclass 40, count 0 2006.183.07:36:30.60#ibcon#about to read 4, iclass 40, count 0 2006.183.07:36:30.60#ibcon#read 4, iclass 40, count 0 2006.183.07:36:30.60#ibcon#about to read 5, iclass 40, count 0 2006.183.07:36:30.60#ibcon#read 5, iclass 40, count 0 2006.183.07:36:30.60#ibcon#about to read 6, iclass 40, count 0 2006.183.07:36:30.60#ibcon#read 6, iclass 40, count 0 2006.183.07:36:30.60#ibcon#end of sib2, iclass 40, count 0 2006.183.07:36:30.60#ibcon#*after write, iclass 40, count 0 2006.183.07:36:30.60#ibcon#*before return 0, iclass 40, count 0 2006.183.07:36:30.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:36:30.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:36:30.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:36:30.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:36:30.60$vc4f8/vblo=1,632.99 2006.183.07:36:30.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.07:36:30.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.07:36:30.60#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:30.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:30.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:30.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:30.60#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:36:30.60#ibcon#first serial, iclass 7, count 0 2006.183.07:36:30.60#ibcon#enter sib2, iclass 7, count 0 2006.183.07:36:30.60#ibcon#flushed, iclass 7, count 0 2006.183.07:36:30.60#ibcon#about to write, iclass 7, count 0 2006.183.07:36:30.60#ibcon#wrote, iclass 7, count 0 2006.183.07:36:30.60#ibcon#about to read 3, iclass 7, count 0 2006.183.07:36:30.62#ibcon#read 3, iclass 7, count 0 2006.183.07:36:30.62#ibcon#about to read 4, iclass 7, count 0 2006.183.07:36:30.62#ibcon#read 4, iclass 7, count 0 2006.183.07:36:30.62#ibcon#about to read 5, iclass 7, count 0 2006.183.07:36:30.62#ibcon#read 5, iclass 7, count 0 2006.183.07:36:30.62#ibcon#about to read 6, iclass 7, count 0 2006.183.07:36:30.62#ibcon#read 6, iclass 7, count 0 2006.183.07:36:30.62#ibcon#end of sib2, iclass 7, count 0 2006.183.07:36:30.62#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:36:30.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:36:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:36:30.62#ibcon#*before write, iclass 7, count 0 2006.183.07:36:30.62#ibcon#enter sib2, iclass 7, count 0 2006.183.07:36:30.62#ibcon#flushed, iclass 7, count 0 2006.183.07:36:30.62#ibcon#about to write, iclass 7, count 0 2006.183.07:36:30.62#ibcon#wrote, iclass 7, count 0 2006.183.07:36:30.62#ibcon#about to read 3, iclass 7, count 0 2006.183.07:36:30.66#ibcon#read 3, iclass 7, count 0 2006.183.07:36:30.66#ibcon#about to read 4, iclass 7, count 0 2006.183.07:36:30.66#ibcon#read 4, iclass 7, count 0 2006.183.07:36:30.66#ibcon#about to read 5, iclass 7, count 0 2006.183.07:36:30.66#ibcon#read 5, iclass 7, count 0 2006.183.07:36:30.66#ibcon#about to read 6, iclass 7, count 0 2006.183.07:36:30.66#ibcon#read 6, iclass 7, count 0 2006.183.07:36:30.66#ibcon#end of sib2, iclass 7, count 0 2006.183.07:36:30.66#ibcon#*after write, iclass 7, count 0 2006.183.07:36:30.66#ibcon#*before return 0, iclass 7, count 0 2006.183.07:36:30.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:30.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:36:30.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:36:30.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:36:30.66$vc4f8/vb=1,4 2006.183.07:36:30.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.07:36:30.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.07:36:30.66#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:30.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:30.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:30.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:30.66#ibcon#enter wrdev, iclass 11, count 2 2006.183.07:36:30.66#ibcon#first serial, iclass 11, count 2 2006.183.07:36:30.66#ibcon#enter sib2, iclass 11, count 2 2006.183.07:36:30.66#ibcon#flushed, iclass 11, count 2 2006.183.07:36:30.66#ibcon#about to write, iclass 11, count 2 2006.183.07:36:30.66#ibcon#wrote, iclass 11, count 2 2006.183.07:36:30.66#ibcon#about to read 3, iclass 11, count 2 2006.183.07:36:30.68#ibcon#read 3, iclass 11, count 2 2006.183.07:36:30.68#ibcon#about to read 4, iclass 11, count 2 2006.183.07:36:30.68#ibcon#read 4, iclass 11, count 2 2006.183.07:36:30.68#ibcon#about to read 5, iclass 11, count 2 2006.183.07:36:30.68#ibcon#read 5, iclass 11, count 2 2006.183.07:36:30.68#ibcon#about to read 6, iclass 11, count 2 2006.183.07:36:30.68#ibcon#read 6, iclass 11, count 2 2006.183.07:36:30.68#ibcon#end of sib2, iclass 11, count 2 2006.183.07:36:30.68#ibcon#*mode == 0, iclass 11, count 2 2006.183.07:36:30.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.07:36:30.68#ibcon#[27=AT01-04\r\n] 2006.183.07:36:30.68#ibcon#*before write, iclass 11, count 2 2006.183.07:36:30.68#ibcon#enter sib2, iclass 11, count 2 2006.183.07:36:30.68#ibcon#flushed, iclass 11, count 2 2006.183.07:36:30.68#ibcon#about to write, iclass 11, count 2 2006.183.07:36:30.68#ibcon#wrote, iclass 11, count 2 2006.183.07:36:30.68#ibcon#about to read 3, iclass 11, count 2 2006.183.07:36:30.71#ibcon#read 3, iclass 11, count 2 2006.183.07:36:30.71#ibcon#about to read 4, iclass 11, count 2 2006.183.07:36:30.71#ibcon#read 4, iclass 11, count 2 2006.183.07:36:30.71#ibcon#about to read 5, iclass 11, count 2 2006.183.07:36:30.71#ibcon#read 5, iclass 11, count 2 2006.183.07:36:30.71#ibcon#about to read 6, iclass 11, count 2 2006.183.07:36:30.71#ibcon#read 6, iclass 11, count 2 2006.183.07:36:30.71#ibcon#end of sib2, iclass 11, count 2 2006.183.07:36:30.71#ibcon#*after write, iclass 11, count 2 2006.183.07:36:30.71#ibcon#*before return 0, iclass 11, count 2 2006.183.07:36:30.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:30.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:36:30.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.07:36:30.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:30.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:30.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:30.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:30.83#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:36:30.83#ibcon#first serial, iclass 11, count 0 2006.183.07:36:30.83#ibcon#enter sib2, iclass 11, count 0 2006.183.07:36:30.83#ibcon#flushed, iclass 11, count 0 2006.183.07:36:30.83#ibcon#about to write, iclass 11, count 0 2006.183.07:36:30.83#ibcon#wrote, iclass 11, count 0 2006.183.07:36:30.83#ibcon#about to read 3, iclass 11, count 0 2006.183.07:36:30.85#ibcon#read 3, iclass 11, count 0 2006.183.07:36:30.85#ibcon#about to read 4, iclass 11, count 0 2006.183.07:36:30.85#ibcon#read 4, iclass 11, count 0 2006.183.07:36:30.85#ibcon#about to read 5, iclass 11, count 0 2006.183.07:36:30.85#ibcon#read 5, iclass 11, count 0 2006.183.07:36:30.85#ibcon#about to read 6, iclass 11, count 0 2006.183.07:36:30.85#ibcon#read 6, iclass 11, count 0 2006.183.07:36:30.85#ibcon#end of sib2, iclass 11, count 0 2006.183.07:36:30.85#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:36:30.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:36:30.85#ibcon#[27=USB\r\n] 2006.183.07:36:30.85#ibcon#*before write, iclass 11, count 0 2006.183.07:36:30.85#ibcon#enter sib2, iclass 11, count 0 2006.183.07:36:30.85#ibcon#flushed, iclass 11, count 0 2006.183.07:36:30.85#ibcon#about to write, iclass 11, count 0 2006.183.07:36:30.85#ibcon#wrote, iclass 11, count 0 2006.183.07:36:30.85#ibcon#about to read 3, iclass 11, count 0 2006.183.07:36:30.88#ibcon#read 3, iclass 11, count 0 2006.183.07:36:30.88#ibcon#about to read 4, iclass 11, count 0 2006.183.07:36:30.88#ibcon#read 4, iclass 11, count 0 2006.183.07:36:30.88#ibcon#about to read 5, iclass 11, count 0 2006.183.07:36:30.88#ibcon#read 5, iclass 11, count 0 2006.183.07:36:30.88#ibcon#about to read 6, iclass 11, count 0 2006.183.07:36:30.88#ibcon#read 6, iclass 11, count 0 2006.183.07:36:30.88#ibcon#end of sib2, iclass 11, count 0 2006.183.07:36:30.88#ibcon#*after write, iclass 11, count 0 2006.183.07:36:30.88#ibcon#*before return 0, iclass 11, count 0 2006.183.07:36:30.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:30.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:36:30.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:36:30.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:36:30.88$vc4f8/vblo=2,640.99 2006.183.07:36:30.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:36:30.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:36:30.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:30.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:30.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:30.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:30.88#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:36:30.88#ibcon#first serial, iclass 13, count 0 2006.183.07:36:30.88#ibcon#enter sib2, iclass 13, count 0 2006.183.07:36:30.88#ibcon#flushed, iclass 13, count 0 2006.183.07:36:30.88#ibcon#about to write, iclass 13, count 0 2006.183.07:36:30.88#ibcon#wrote, iclass 13, count 0 2006.183.07:36:30.88#ibcon#about to read 3, iclass 13, count 0 2006.183.07:36:30.90#ibcon#read 3, iclass 13, count 0 2006.183.07:36:30.90#ibcon#about to read 4, iclass 13, count 0 2006.183.07:36:30.90#ibcon#read 4, iclass 13, count 0 2006.183.07:36:30.90#ibcon#about to read 5, iclass 13, count 0 2006.183.07:36:30.90#ibcon#read 5, iclass 13, count 0 2006.183.07:36:30.90#ibcon#about to read 6, iclass 13, count 0 2006.183.07:36:30.90#ibcon#read 6, iclass 13, count 0 2006.183.07:36:30.90#ibcon#end of sib2, iclass 13, count 0 2006.183.07:36:30.90#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:36:30.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:36:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:36:30.90#ibcon#*before write, iclass 13, count 0 2006.183.07:36:30.90#ibcon#enter sib2, iclass 13, count 0 2006.183.07:36:30.90#ibcon#flushed, iclass 13, count 0 2006.183.07:36:30.90#ibcon#about to write, iclass 13, count 0 2006.183.07:36:30.90#ibcon#wrote, iclass 13, count 0 2006.183.07:36:30.90#ibcon#about to read 3, iclass 13, count 0 2006.183.07:36:30.94#ibcon#read 3, iclass 13, count 0 2006.183.07:36:30.94#ibcon#about to read 4, iclass 13, count 0 2006.183.07:36:30.94#ibcon#read 4, iclass 13, count 0 2006.183.07:36:30.94#ibcon#about to read 5, iclass 13, count 0 2006.183.07:36:30.94#ibcon#read 5, iclass 13, count 0 2006.183.07:36:30.94#ibcon#about to read 6, iclass 13, count 0 2006.183.07:36:30.94#ibcon#read 6, iclass 13, count 0 2006.183.07:36:30.94#ibcon#end of sib2, iclass 13, count 0 2006.183.07:36:30.94#ibcon#*after write, iclass 13, count 0 2006.183.07:36:30.94#ibcon#*before return 0, iclass 13, count 0 2006.183.07:36:30.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:30.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:36:30.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:36:30.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:36:30.94$vc4f8/vb=2,4 2006.183.07:36:30.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:36:30.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:36:30.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:30.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:31.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:31.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:31.01#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:36:31.01#ibcon#first serial, iclass 15, count 2 2006.183.07:36:31.01#ibcon#enter sib2, iclass 15, count 2 2006.183.07:36:31.01#ibcon#flushed, iclass 15, count 2 2006.183.07:36:31.01#ibcon#about to write, iclass 15, count 2 2006.183.07:36:31.01#ibcon#wrote, iclass 15, count 2 2006.183.07:36:31.01#ibcon#about to read 3, iclass 15, count 2 2006.183.07:36:31.02#ibcon#read 3, iclass 15, count 2 2006.183.07:36:31.02#ibcon#about to read 4, iclass 15, count 2 2006.183.07:36:31.02#ibcon#read 4, iclass 15, count 2 2006.183.07:36:31.02#ibcon#about to read 5, iclass 15, count 2 2006.183.07:36:31.02#ibcon#read 5, iclass 15, count 2 2006.183.07:36:31.02#ibcon#about to read 6, iclass 15, count 2 2006.183.07:36:31.02#ibcon#read 6, iclass 15, count 2 2006.183.07:36:31.02#ibcon#end of sib2, iclass 15, count 2 2006.183.07:36:31.02#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:36:31.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:36:31.02#ibcon#[27=AT02-04\r\n] 2006.183.07:36:31.02#ibcon#*before write, iclass 15, count 2 2006.183.07:36:31.02#ibcon#enter sib2, iclass 15, count 2 2006.183.07:36:31.02#ibcon#flushed, iclass 15, count 2 2006.183.07:36:31.02#ibcon#about to write, iclass 15, count 2 2006.183.07:36:31.02#ibcon#wrote, iclass 15, count 2 2006.183.07:36:31.02#ibcon#about to read 3, iclass 15, count 2 2006.183.07:36:31.05#ibcon#read 3, iclass 15, count 2 2006.183.07:36:31.05#ibcon#about to read 4, iclass 15, count 2 2006.183.07:36:31.05#ibcon#read 4, iclass 15, count 2 2006.183.07:36:31.05#ibcon#about to read 5, iclass 15, count 2 2006.183.07:36:31.05#ibcon#read 5, iclass 15, count 2 2006.183.07:36:31.05#ibcon#about to read 6, iclass 15, count 2 2006.183.07:36:31.05#ibcon#read 6, iclass 15, count 2 2006.183.07:36:31.05#ibcon#end of sib2, iclass 15, count 2 2006.183.07:36:31.05#ibcon#*after write, iclass 15, count 2 2006.183.07:36:31.05#ibcon#*before return 0, iclass 15, count 2 2006.183.07:36:31.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:31.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:36:31.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:36:31.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:31.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:31.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:31.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:31.17#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:36:31.17#ibcon#first serial, iclass 15, count 0 2006.183.07:36:31.17#ibcon#enter sib2, iclass 15, count 0 2006.183.07:36:31.17#ibcon#flushed, iclass 15, count 0 2006.183.07:36:31.17#ibcon#about to write, iclass 15, count 0 2006.183.07:36:31.17#ibcon#wrote, iclass 15, count 0 2006.183.07:36:31.17#ibcon#about to read 3, iclass 15, count 0 2006.183.07:36:31.19#ibcon#read 3, iclass 15, count 0 2006.183.07:36:31.19#ibcon#about to read 4, iclass 15, count 0 2006.183.07:36:31.19#ibcon#read 4, iclass 15, count 0 2006.183.07:36:31.19#ibcon#about to read 5, iclass 15, count 0 2006.183.07:36:31.19#ibcon#read 5, iclass 15, count 0 2006.183.07:36:31.19#ibcon#about to read 6, iclass 15, count 0 2006.183.07:36:31.19#ibcon#read 6, iclass 15, count 0 2006.183.07:36:31.19#ibcon#end of sib2, iclass 15, count 0 2006.183.07:36:31.19#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:36:31.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:36:31.19#ibcon#[27=USB\r\n] 2006.183.07:36:31.19#ibcon#*before write, iclass 15, count 0 2006.183.07:36:31.19#ibcon#enter sib2, iclass 15, count 0 2006.183.07:36:31.19#ibcon#flushed, iclass 15, count 0 2006.183.07:36:31.19#ibcon#about to write, iclass 15, count 0 2006.183.07:36:31.19#ibcon#wrote, iclass 15, count 0 2006.183.07:36:31.19#ibcon#about to read 3, iclass 15, count 0 2006.183.07:36:31.22#ibcon#read 3, iclass 15, count 0 2006.183.07:36:31.22#ibcon#about to read 4, iclass 15, count 0 2006.183.07:36:31.22#ibcon#read 4, iclass 15, count 0 2006.183.07:36:31.22#ibcon#about to read 5, iclass 15, count 0 2006.183.07:36:31.22#ibcon#read 5, iclass 15, count 0 2006.183.07:36:31.22#ibcon#about to read 6, iclass 15, count 0 2006.183.07:36:31.22#ibcon#read 6, iclass 15, count 0 2006.183.07:36:31.22#ibcon#end of sib2, iclass 15, count 0 2006.183.07:36:31.22#ibcon#*after write, iclass 15, count 0 2006.183.07:36:31.22#ibcon#*before return 0, iclass 15, count 0 2006.183.07:36:31.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:31.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:36:31.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:36:31.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:36:31.22$vc4f8/vblo=3,656.99 2006.183.07:36:31.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:36:31.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:36:31.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:31.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:31.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:31.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:31.22#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:36:31.22#ibcon#first serial, iclass 17, count 0 2006.183.07:36:31.22#ibcon#enter sib2, iclass 17, count 0 2006.183.07:36:31.22#ibcon#flushed, iclass 17, count 0 2006.183.07:36:31.22#ibcon#about to write, iclass 17, count 0 2006.183.07:36:31.22#ibcon#wrote, iclass 17, count 0 2006.183.07:36:31.22#ibcon#about to read 3, iclass 17, count 0 2006.183.07:36:31.24#ibcon#read 3, iclass 17, count 0 2006.183.07:36:31.24#ibcon#about to read 4, iclass 17, count 0 2006.183.07:36:31.24#ibcon#read 4, iclass 17, count 0 2006.183.07:36:31.24#ibcon#about to read 5, iclass 17, count 0 2006.183.07:36:31.24#ibcon#read 5, iclass 17, count 0 2006.183.07:36:31.24#ibcon#about to read 6, iclass 17, count 0 2006.183.07:36:31.24#ibcon#read 6, iclass 17, count 0 2006.183.07:36:31.24#ibcon#end of sib2, iclass 17, count 0 2006.183.07:36:31.24#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:36:31.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:36:31.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:36:31.24#ibcon#*before write, iclass 17, count 0 2006.183.07:36:31.24#ibcon#enter sib2, iclass 17, count 0 2006.183.07:36:31.24#ibcon#flushed, iclass 17, count 0 2006.183.07:36:31.24#ibcon#about to write, iclass 17, count 0 2006.183.07:36:31.24#ibcon#wrote, iclass 17, count 0 2006.183.07:36:31.24#ibcon#about to read 3, iclass 17, count 0 2006.183.07:36:31.28#ibcon#read 3, iclass 17, count 0 2006.183.07:36:31.28#ibcon#about to read 4, iclass 17, count 0 2006.183.07:36:31.28#ibcon#read 4, iclass 17, count 0 2006.183.07:36:31.28#ibcon#about to read 5, iclass 17, count 0 2006.183.07:36:31.28#ibcon#read 5, iclass 17, count 0 2006.183.07:36:31.28#ibcon#about to read 6, iclass 17, count 0 2006.183.07:36:31.28#ibcon#read 6, iclass 17, count 0 2006.183.07:36:31.28#ibcon#end of sib2, iclass 17, count 0 2006.183.07:36:31.28#ibcon#*after write, iclass 17, count 0 2006.183.07:36:31.28#ibcon#*before return 0, iclass 17, count 0 2006.183.07:36:31.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:31.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:36:31.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:36:31.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:36:31.28$vc4f8/vb=3,4 2006.183.07:36:31.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:36:31.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:36:31.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:31.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:31.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:31.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:31.34#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:36:31.34#ibcon#first serial, iclass 19, count 2 2006.183.07:36:31.34#ibcon#enter sib2, iclass 19, count 2 2006.183.07:36:31.34#ibcon#flushed, iclass 19, count 2 2006.183.07:36:31.34#ibcon#about to write, iclass 19, count 2 2006.183.07:36:31.34#ibcon#wrote, iclass 19, count 2 2006.183.07:36:31.34#ibcon#about to read 3, iclass 19, count 2 2006.183.07:36:31.36#ibcon#read 3, iclass 19, count 2 2006.183.07:36:31.36#ibcon#about to read 4, iclass 19, count 2 2006.183.07:36:31.36#ibcon#read 4, iclass 19, count 2 2006.183.07:36:31.36#ibcon#about to read 5, iclass 19, count 2 2006.183.07:36:31.36#ibcon#read 5, iclass 19, count 2 2006.183.07:36:31.36#ibcon#about to read 6, iclass 19, count 2 2006.183.07:36:31.36#ibcon#read 6, iclass 19, count 2 2006.183.07:36:31.36#ibcon#end of sib2, iclass 19, count 2 2006.183.07:36:31.36#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:36:31.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:36:31.36#ibcon#[27=AT03-04\r\n] 2006.183.07:36:31.36#ibcon#*before write, iclass 19, count 2 2006.183.07:36:31.36#ibcon#enter sib2, iclass 19, count 2 2006.183.07:36:31.36#ibcon#flushed, iclass 19, count 2 2006.183.07:36:31.36#ibcon#about to write, iclass 19, count 2 2006.183.07:36:31.36#ibcon#wrote, iclass 19, count 2 2006.183.07:36:31.36#ibcon#about to read 3, iclass 19, count 2 2006.183.07:36:31.39#ibcon#read 3, iclass 19, count 2 2006.183.07:36:31.39#ibcon#about to read 4, iclass 19, count 2 2006.183.07:36:31.39#ibcon#read 4, iclass 19, count 2 2006.183.07:36:31.39#ibcon#about to read 5, iclass 19, count 2 2006.183.07:36:31.39#ibcon#read 5, iclass 19, count 2 2006.183.07:36:31.39#ibcon#about to read 6, iclass 19, count 2 2006.183.07:36:31.39#ibcon#read 6, iclass 19, count 2 2006.183.07:36:31.39#ibcon#end of sib2, iclass 19, count 2 2006.183.07:36:31.39#ibcon#*after write, iclass 19, count 2 2006.183.07:36:31.39#ibcon#*before return 0, iclass 19, count 2 2006.183.07:36:31.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:31.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:36:31.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:36:31.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:31.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:31.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:31.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:31.51#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:36:31.51#ibcon#first serial, iclass 19, count 0 2006.183.07:36:31.51#ibcon#enter sib2, iclass 19, count 0 2006.183.07:36:31.51#ibcon#flushed, iclass 19, count 0 2006.183.07:36:31.51#ibcon#about to write, iclass 19, count 0 2006.183.07:36:31.51#ibcon#wrote, iclass 19, count 0 2006.183.07:36:31.51#ibcon#about to read 3, iclass 19, count 0 2006.183.07:36:31.53#ibcon#read 3, iclass 19, count 0 2006.183.07:36:31.53#ibcon#about to read 4, iclass 19, count 0 2006.183.07:36:31.53#ibcon#read 4, iclass 19, count 0 2006.183.07:36:31.53#ibcon#about to read 5, iclass 19, count 0 2006.183.07:36:31.53#ibcon#read 5, iclass 19, count 0 2006.183.07:36:31.53#ibcon#about to read 6, iclass 19, count 0 2006.183.07:36:31.53#ibcon#read 6, iclass 19, count 0 2006.183.07:36:31.53#ibcon#end of sib2, iclass 19, count 0 2006.183.07:36:31.53#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:36:31.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:36:31.53#ibcon#[27=USB\r\n] 2006.183.07:36:31.53#ibcon#*before write, iclass 19, count 0 2006.183.07:36:31.53#ibcon#enter sib2, iclass 19, count 0 2006.183.07:36:31.53#ibcon#flushed, iclass 19, count 0 2006.183.07:36:31.53#ibcon#about to write, iclass 19, count 0 2006.183.07:36:31.53#ibcon#wrote, iclass 19, count 0 2006.183.07:36:31.53#ibcon#about to read 3, iclass 19, count 0 2006.183.07:36:31.56#ibcon#read 3, iclass 19, count 0 2006.183.07:36:31.56#ibcon#about to read 4, iclass 19, count 0 2006.183.07:36:31.56#ibcon#read 4, iclass 19, count 0 2006.183.07:36:31.56#ibcon#about to read 5, iclass 19, count 0 2006.183.07:36:31.56#ibcon#read 5, iclass 19, count 0 2006.183.07:36:31.56#ibcon#about to read 6, iclass 19, count 0 2006.183.07:36:31.56#ibcon#read 6, iclass 19, count 0 2006.183.07:36:31.56#ibcon#end of sib2, iclass 19, count 0 2006.183.07:36:31.56#ibcon#*after write, iclass 19, count 0 2006.183.07:36:31.56#ibcon#*before return 0, iclass 19, count 0 2006.183.07:36:31.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:31.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:36:31.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:36:31.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:36:31.56$vc4f8/vblo=4,712.99 2006.183.07:36:31.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:36:31.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:36:31.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:31.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:31.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:31.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:31.56#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:36:31.56#ibcon#first serial, iclass 21, count 0 2006.183.07:36:31.56#ibcon#enter sib2, iclass 21, count 0 2006.183.07:36:31.56#ibcon#flushed, iclass 21, count 0 2006.183.07:36:31.56#ibcon#about to write, iclass 21, count 0 2006.183.07:36:31.56#ibcon#wrote, iclass 21, count 0 2006.183.07:36:31.56#ibcon#about to read 3, iclass 21, count 0 2006.183.07:36:31.58#ibcon#read 3, iclass 21, count 0 2006.183.07:36:31.58#ibcon#about to read 4, iclass 21, count 0 2006.183.07:36:31.58#ibcon#read 4, iclass 21, count 0 2006.183.07:36:31.58#ibcon#about to read 5, iclass 21, count 0 2006.183.07:36:31.58#ibcon#read 5, iclass 21, count 0 2006.183.07:36:31.58#ibcon#about to read 6, iclass 21, count 0 2006.183.07:36:31.58#ibcon#read 6, iclass 21, count 0 2006.183.07:36:31.58#ibcon#end of sib2, iclass 21, count 0 2006.183.07:36:31.58#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:36:31.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:36:31.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:36:31.58#ibcon#*before write, iclass 21, count 0 2006.183.07:36:31.58#ibcon#enter sib2, iclass 21, count 0 2006.183.07:36:31.58#ibcon#flushed, iclass 21, count 0 2006.183.07:36:31.58#ibcon#about to write, iclass 21, count 0 2006.183.07:36:31.58#ibcon#wrote, iclass 21, count 0 2006.183.07:36:31.58#ibcon#about to read 3, iclass 21, count 0 2006.183.07:36:31.62#ibcon#read 3, iclass 21, count 0 2006.183.07:36:31.62#ibcon#about to read 4, iclass 21, count 0 2006.183.07:36:31.62#ibcon#read 4, iclass 21, count 0 2006.183.07:36:31.62#ibcon#about to read 5, iclass 21, count 0 2006.183.07:36:31.62#ibcon#read 5, iclass 21, count 0 2006.183.07:36:31.62#ibcon#about to read 6, iclass 21, count 0 2006.183.07:36:31.62#ibcon#read 6, iclass 21, count 0 2006.183.07:36:31.62#ibcon#end of sib2, iclass 21, count 0 2006.183.07:36:31.62#ibcon#*after write, iclass 21, count 0 2006.183.07:36:31.62#ibcon#*before return 0, iclass 21, count 0 2006.183.07:36:31.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:31.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:36:31.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:36:31.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:36:31.62$vc4f8/vb=4,4 2006.183.07:36:31.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:36:31.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:36:31.62#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:31.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:31.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:31.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:31.68#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:36:31.68#ibcon#first serial, iclass 23, count 2 2006.183.07:36:31.68#ibcon#enter sib2, iclass 23, count 2 2006.183.07:36:31.68#ibcon#flushed, iclass 23, count 2 2006.183.07:36:31.68#ibcon#about to write, iclass 23, count 2 2006.183.07:36:31.68#ibcon#wrote, iclass 23, count 2 2006.183.07:36:31.68#ibcon#about to read 3, iclass 23, count 2 2006.183.07:36:31.70#ibcon#read 3, iclass 23, count 2 2006.183.07:36:31.70#ibcon#about to read 4, iclass 23, count 2 2006.183.07:36:31.70#ibcon#read 4, iclass 23, count 2 2006.183.07:36:31.70#ibcon#about to read 5, iclass 23, count 2 2006.183.07:36:31.70#ibcon#read 5, iclass 23, count 2 2006.183.07:36:31.70#ibcon#about to read 6, iclass 23, count 2 2006.183.07:36:31.70#ibcon#read 6, iclass 23, count 2 2006.183.07:36:31.70#ibcon#end of sib2, iclass 23, count 2 2006.183.07:36:31.70#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:36:31.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:36:31.70#ibcon#[27=AT04-04\r\n] 2006.183.07:36:31.70#ibcon#*before write, iclass 23, count 2 2006.183.07:36:31.70#ibcon#enter sib2, iclass 23, count 2 2006.183.07:36:31.70#ibcon#flushed, iclass 23, count 2 2006.183.07:36:31.70#ibcon#about to write, iclass 23, count 2 2006.183.07:36:31.70#ibcon#wrote, iclass 23, count 2 2006.183.07:36:31.70#ibcon#about to read 3, iclass 23, count 2 2006.183.07:36:31.73#ibcon#read 3, iclass 23, count 2 2006.183.07:36:31.73#ibcon#about to read 4, iclass 23, count 2 2006.183.07:36:31.73#ibcon#read 4, iclass 23, count 2 2006.183.07:36:31.73#ibcon#about to read 5, iclass 23, count 2 2006.183.07:36:31.73#ibcon#read 5, iclass 23, count 2 2006.183.07:36:31.73#ibcon#about to read 6, iclass 23, count 2 2006.183.07:36:31.73#ibcon#read 6, iclass 23, count 2 2006.183.07:36:31.73#ibcon#end of sib2, iclass 23, count 2 2006.183.07:36:31.73#ibcon#*after write, iclass 23, count 2 2006.183.07:36:31.73#ibcon#*before return 0, iclass 23, count 2 2006.183.07:36:31.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:31.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:36:31.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:36:31.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:31.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:31.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:31.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:31.85#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:36:31.85#ibcon#first serial, iclass 23, count 0 2006.183.07:36:31.85#ibcon#enter sib2, iclass 23, count 0 2006.183.07:36:31.85#ibcon#flushed, iclass 23, count 0 2006.183.07:36:31.85#ibcon#about to write, iclass 23, count 0 2006.183.07:36:31.85#ibcon#wrote, iclass 23, count 0 2006.183.07:36:31.85#ibcon#about to read 3, iclass 23, count 0 2006.183.07:36:31.87#ibcon#read 3, iclass 23, count 0 2006.183.07:36:31.87#ibcon#about to read 4, iclass 23, count 0 2006.183.07:36:31.87#ibcon#read 4, iclass 23, count 0 2006.183.07:36:31.87#ibcon#about to read 5, iclass 23, count 0 2006.183.07:36:31.87#ibcon#read 5, iclass 23, count 0 2006.183.07:36:31.87#ibcon#about to read 6, iclass 23, count 0 2006.183.07:36:31.87#ibcon#read 6, iclass 23, count 0 2006.183.07:36:31.87#ibcon#end of sib2, iclass 23, count 0 2006.183.07:36:31.87#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:36:31.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:36:31.87#ibcon#[27=USB\r\n] 2006.183.07:36:31.87#ibcon#*before write, iclass 23, count 0 2006.183.07:36:31.87#ibcon#enter sib2, iclass 23, count 0 2006.183.07:36:31.87#ibcon#flushed, iclass 23, count 0 2006.183.07:36:31.87#ibcon#about to write, iclass 23, count 0 2006.183.07:36:31.87#ibcon#wrote, iclass 23, count 0 2006.183.07:36:31.87#ibcon#about to read 3, iclass 23, count 0 2006.183.07:36:31.90#ibcon#read 3, iclass 23, count 0 2006.183.07:36:31.90#ibcon#about to read 4, iclass 23, count 0 2006.183.07:36:31.90#ibcon#read 4, iclass 23, count 0 2006.183.07:36:31.90#ibcon#about to read 5, iclass 23, count 0 2006.183.07:36:31.90#ibcon#read 5, iclass 23, count 0 2006.183.07:36:31.90#ibcon#about to read 6, iclass 23, count 0 2006.183.07:36:31.90#ibcon#read 6, iclass 23, count 0 2006.183.07:36:31.90#ibcon#end of sib2, iclass 23, count 0 2006.183.07:36:31.90#ibcon#*after write, iclass 23, count 0 2006.183.07:36:31.90#ibcon#*before return 0, iclass 23, count 0 2006.183.07:36:31.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:31.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:36:31.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:36:31.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:36:31.90$vc4f8/vblo=5,744.99 2006.183.07:36:31.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:36:31.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:36:31.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:31.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:31.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:31.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:31.90#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:36:31.90#ibcon#first serial, iclass 25, count 0 2006.183.07:36:31.90#ibcon#enter sib2, iclass 25, count 0 2006.183.07:36:31.90#ibcon#flushed, iclass 25, count 0 2006.183.07:36:31.90#ibcon#about to write, iclass 25, count 0 2006.183.07:36:31.90#ibcon#wrote, iclass 25, count 0 2006.183.07:36:31.90#ibcon#about to read 3, iclass 25, count 0 2006.183.07:36:31.92#ibcon#read 3, iclass 25, count 0 2006.183.07:36:31.92#ibcon#about to read 4, iclass 25, count 0 2006.183.07:36:31.92#ibcon#read 4, iclass 25, count 0 2006.183.07:36:31.92#ibcon#about to read 5, iclass 25, count 0 2006.183.07:36:31.92#ibcon#read 5, iclass 25, count 0 2006.183.07:36:31.92#ibcon#about to read 6, iclass 25, count 0 2006.183.07:36:31.92#ibcon#read 6, iclass 25, count 0 2006.183.07:36:31.92#ibcon#end of sib2, iclass 25, count 0 2006.183.07:36:31.92#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:36:31.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:36:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:36:31.92#ibcon#*before write, iclass 25, count 0 2006.183.07:36:31.92#ibcon#enter sib2, iclass 25, count 0 2006.183.07:36:31.92#ibcon#flushed, iclass 25, count 0 2006.183.07:36:31.92#ibcon#about to write, iclass 25, count 0 2006.183.07:36:31.92#ibcon#wrote, iclass 25, count 0 2006.183.07:36:31.92#ibcon#about to read 3, iclass 25, count 0 2006.183.07:36:31.96#ibcon#read 3, iclass 25, count 0 2006.183.07:36:31.96#ibcon#about to read 4, iclass 25, count 0 2006.183.07:36:31.96#ibcon#read 4, iclass 25, count 0 2006.183.07:36:31.96#ibcon#about to read 5, iclass 25, count 0 2006.183.07:36:31.96#ibcon#read 5, iclass 25, count 0 2006.183.07:36:31.96#ibcon#about to read 6, iclass 25, count 0 2006.183.07:36:31.96#ibcon#read 6, iclass 25, count 0 2006.183.07:36:31.96#ibcon#end of sib2, iclass 25, count 0 2006.183.07:36:31.96#ibcon#*after write, iclass 25, count 0 2006.183.07:36:31.96#ibcon#*before return 0, iclass 25, count 0 2006.183.07:36:31.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:31.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:36:31.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:36:31.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:36:31.96$vc4f8/vb=5,4 2006.183.07:36:31.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.07:36:31.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.07:36:31.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:31.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:32.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:32.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:32.02#ibcon#enter wrdev, iclass 27, count 2 2006.183.07:36:32.02#ibcon#first serial, iclass 27, count 2 2006.183.07:36:32.02#ibcon#enter sib2, iclass 27, count 2 2006.183.07:36:32.02#ibcon#flushed, iclass 27, count 2 2006.183.07:36:32.02#ibcon#about to write, iclass 27, count 2 2006.183.07:36:32.02#ibcon#wrote, iclass 27, count 2 2006.183.07:36:32.02#ibcon#about to read 3, iclass 27, count 2 2006.183.07:36:32.04#ibcon#read 3, iclass 27, count 2 2006.183.07:36:32.04#ibcon#about to read 4, iclass 27, count 2 2006.183.07:36:32.04#ibcon#read 4, iclass 27, count 2 2006.183.07:36:32.04#ibcon#about to read 5, iclass 27, count 2 2006.183.07:36:32.04#ibcon#read 5, iclass 27, count 2 2006.183.07:36:32.04#ibcon#about to read 6, iclass 27, count 2 2006.183.07:36:32.04#ibcon#read 6, iclass 27, count 2 2006.183.07:36:32.04#ibcon#end of sib2, iclass 27, count 2 2006.183.07:36:32.04#ibcon#*mode == 0, iclass 27, count 2 2006.183.07:36:32.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.07:36:32.04#ibcon#[27=AT05-04\r\n] 2006.183.07:36:32.04#ibcon#*before write, iclass 27, count 2 2006.183.07:36:32.04#ibcon#enter sib2, iclass 27, count 2 2006.183.07:36:32.04#ibcon#flushed, iclass 27, count 2 2006.183.07:36:32.04#ibcon#about to write, iclass 27, count 2 2006.183.07:36:32.04#ibcon#wrote, iclass 27, count 2 2006.183.07:36:32.04#ibcon#about to read 3, iclass 27, count 2 2006.183.07:36:32.07#ibcon#read 3, iclass 27, count 2 2006.183.07:36:32.07#ibcon#about to read 4, iclass 27, count 2 2006.183.07:36:32.07#ibcon#read 4, iclass 27, count 2 2006.183.07:36:32.07#ibcon#about to read 5, iclass 27, count 2 2006.183.07:36:32.07#ibcon#read 5, iclass 27, count 2 2006.183.07:36:32.07#ibcon#about to read 6, iclass 27, count 2 2006.183.07:36:32.07#ibcon#read 6, iclass 27, count 2 2006.183.07:36:32.07#ibcon#end of sib2, iclass 27, count 2 2006.183.07:36:32.07#ibcon#*after write, iclass 27, count 2 2006.183.07:36:32.07#ibcon#*before return 0, iclass 27, count 2 2006.183.07:36:32.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:32.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:36:32.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.07:36:32.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:32.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:32.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:32.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:32.19#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:36:32.19#ibcon#first serial, iclass 27, count 0 2006.183.07:36:32.19#ibcon#enter sib2, iclass 27, count 0 2006.183.07:36:32.19#ibcon#flushed, iclass 27, count 0 2006.183.07:36:32.19#ibcon#about to write, iclass 27, count 0 2006.183.07:36:32.19#ibcon#wrote, iclass 27, count 0 2006.183.07:36:32.19#ibcon#about to read 3, iclass 27, count 0 2006.183.07:36:32.21#ibcon#read 3, iclass 27, count 0 2006.183.07:36:32.21#ibcon#about to read 4, iclass 27, count 0 2006.183.07:36:32.21#ibcon#read 4, iclass 27, count 0 2006.183.07:36:32.21#ibcon#about to read 5, iclass 27, count 0 2006.183.07:36:32.21#ibcon#read 5, iclass 27, count 0 2006.183.07:36:32.21#ibcon#about to read 6, iclass 27, count 0 2006.183.07:36:32.21#ibcon#read 6, iclass 27, count 0 2006.183.07:36:32.21#ibcon#end of sib2, iclass 27, count 0 2006.183.07:36:32.21#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:36:32.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:36:32.21#ibcon#[27=USB\r\n] 2006.183.07:36:32.21#ibcon#*before write, iclass 27, count 0 2006.183.07:36:32.21#ibcon#enter sib2, iclass 27, count 0 2006.183.07:36:32.21#ibcon#flushed, iclass 27, count 0 2006.183.07:36:32.21#ibcon#about to write, iclass 27, count 0 2006.183.07:36:32.21#ibcon#wrote, iclass 27, count 0 2006.183.07:36:32.21#ibcon#about to read 3, iclass 27, count 0 2006.183.07:36:32.24#ibcon#read 3, iclass 27, count 0 2006.183.07:36:32.24#ibcon#about to read 4, iclass 27, count 0 2006.183.07:36:32.24#ibcon#read 4, iclass 27, count 0 2006.183.07:36:32.24#ibcon#about to read 5, iclass 27, count 0 2006.183.07:36:32.24#ibcon#read 5, iclass 27, count 0 2006.183.07:36:32.24#ibcon#about to read 6, iclass 27, count 0 2006.183.07:36:32.24#ibcon#read 6, iclass 27, count 0 2006.183.07:36:32.24#ibcon#end of sib2, iclass 27, count 0 2006.183.07:36:32.24#ibcon#*after write, iclass 27, count 0 2006.183.07:36:32.24#ibcon#*before return 0, iclass 27, count 0 2006.183.07:36:32.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:32.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:36:32.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:36:32.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:36:32.24$vc4f8/vblo=6,752.99 2006.183.07:36:32.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.07:36:32.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.07:36:32.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:36:32.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:32.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:32.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:32.24#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:36:32.24#ibcon#first serial, iclass 29, count 0 2006.183.07:36:32.24#ibcon#enter sib2, iclass 29, count 0 2006.183.07:36:32.24#ibcon#flushed, iclass 29, count 0 2006.183.07:36:32.24#ibcon#about to write, iclass 29, count 0 2006.183.07:36:32.24#ibcon#wrote, iclass 29, count 0 2006.183.07:36:32.24#ibcon#about to read 3, iclass 29, count 0 2006.183.07:36:32.26#ibcon#read 3, iclass 29, count 0 2006.183.07:36:32.26#ibcon#about to read 4, iclass 29, count 0 2006.183.07:36:32.26#ibcon#read 4, iclass 29, count 0 2006.183.07:36:32.26#ibcon#about to read 5, iclass 29, count 0 2006.183.07:36:32.26#ibcon#read 5, iclass 29, count 0 2006.183.07:36:32.26#ibcon#about to read 6, iclass 29, count 0 2006.183.07:36:32.26#ibcon#read 6, iclass 29, count 0 2006.183.07:36:32.26#ibcon#end of sib2, iclass 29, count 0 2006.183.07:36:32.26#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:36:32.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:36:32.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:36:32.26#ibcon#*before write, iclass 29, count 0 2006.183.07:36:32.26#ibcon#enter sib2, iclass 29, count 0 2006.183.07:36:32.26#ibcon#flushed, iclass 29, count 0 2006.183.07:36:32.26#ibcon#about to write, iclass 29, count 0 2006.183.07:36:32.26#ibcon#wrote, iclass 29, count 0 2006.183.07:36:32.26#ibcon#about to read 3, iclass 29, count 0 2006.183.07:36:32.30#ibcon#read 3, iclass 29, count 0 2006.183.07:36:32.30#ibcon#about to read 4, iclass 29, count 0 2006.183.07:36:32.30#ibcon#read 4, iclass 29, count 0 2006.183.07:36:32.30#ibcon#about to read 5, iclass 29, count 0 2006.183.07:36:32.30#ibcon#read 5, iclass 29, count 0 2006.183.07:36:32.30#ibcon#about to read 6, iclass 29, count 0 2006.183.07:36:32.30#ibcon#read 6, iclass 29, count 0 2006.183.07:36:32.30#ibcon#end of sib2, iclass 29, count 0 2006.183.07:36:32.30#ibcon#*after write, iclass 29, count 0 2006.183.07:36:32.30#ibcon#*before return 0, iclass 29, count 0 2006.183.07:36:32.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:32.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:36:32.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:36:32.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:36:32.30$vc4f8/vb=6,4 2006.183.07:36:32.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.07:36:32.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.07:36:32.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:36:32.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:32.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:32.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:32.36#ibcon#enter wrdev, iclass 31, count 2 2006.183.07:36:32.36#ibcon#first serial, iclass 31, count 2 2006.183.07:36:32.36#ibcon#enter sib2, iclass 31, count 2 2006.183.07:36:32.36#ibcon#flushed, iclass 31, count 2 2006.183.07:36:32.36#ibcon#about to write, iclass 31, count 2 2006.183.07:36:32.36#ibcon#wrote, iclass 31, count 2 2006.183.07:36:32.36#ibcon#about to read 3, iclass 31, count 2 2006.183.07:36:32.38#ibcon#read 3, iclass 31, count 2 2006.183.07:36:32.38#ibcon#about to read 4, iclass 31, count 2 2006.183.07:36:32.38#ibcon#read 4, iclass 31, count 2 2006.183.07:36:32.38#ibcon#about to read 5, iclass 31, count 2 2006.183.07:36:32.38#ibcon#read 5, iclass 31, count 2 2006.183.07:36:32.38#ibcon#about to read 6, iclass 31, count 2 2006.183.07:36:32.38#ibcon#read 6, iclass 31, count 2 2006.183.07:36:32.38#ibcon#end of sib2, iclass 31, count 2 2006.183.07:36:32.38#ibcon#*mode == 0, iclass 31, count 2 2006.183.07:36:32.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.07:36:32.38#ibcon#[27=AT06-04\r\n] 2006.183.07:36:32.38#ibcon#*before write, iclass 31, count 2 2006.183.07:36:32.38#ibcon#enter sib2, iclass 31, count 2 2006.183.07:36:32.38#ibcon#flushed, iclass 31, count 2 2006.183.07:36:32.38#ibcon#about to write, iclass 31, count 2 2006.183.07:36:32.38#ibcon#wrote, iclass 31, count 2 2006.183.07:36:32.38#ibcon#about to read 3, iclass 31, count 2 2006.183.07:36:32.41#ibcon#read 3, iclass 31, count 2 2006.183.07:36:32.41#ibcon#about to read 4, iclass 31, count 2 2006.183.07:36:32.41#ibcon#read 4, iclass 31, count 2 2006.183.07:36:32.41#ibcon#about to read 5, iclass 31, count 2 2006.183.07:36:32.41#ibcon#read 5, iclass 31, count 2 2006.183.07:36:32.41#ibcon#about to read 6, iclass 31, count 2 2006.183.07:36:32.41#ibcon#read 6, iclass 31, count 2 2006.183.07:36:32.41#ibcon#end of sib2, iclass 31, count 2 2006.183.07:36:32.41#ibcon#*after write, iclass 31, count 2 2006.183.07:36:32.41#ibcon#*before return 0, iclass 31, count 2 2006.183.07:36:32.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:32.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:36:32.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.07:36:32.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:36:32.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:32.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:32.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:32.53#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:36:32.53#ibcon#first serial, iclass 31, count 0 2006.183.07:36:32.53#ibcon#enter sib2, iclass 31, count 0 2006.183.07:36:32.53#ibcon#flushed, iclass 31, count 0 2006.183.07:36:32.53#ibcon#about to write, iclass 31, count 0 2006.183.07:36:32.53#ibcon#wrote, iclass 31, count 0 2006.183.07:36:32.53#ibcon#about to read 3, iclass 31, count 0 2006.183.07:36:32.55#ibcon#read 3, iclass 31, count 0 2006.183.07:36:32.55#ibcon#about to read 4, iclass 31, count 0 2006.183.07:36:32.55#ibcon#read 4, iclass 31, count 0 2006.183.07:36:32.55#ibcon#about to read 5, iclass 31, count 0 2006.183.07:36:32.55#ibcon#read 5, iclass 31, count 0 2006.183.07:36:32.55#ibcon#about to read 6, iclass 31, count 0 2006.183.07:36:32.55#ibcon#read 6, iclass 31, count 0 2006.183.07:36:32.55#ibcon#end of sib2, iclass 31, count 0 2006.183.07:36:32.55#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:36:32.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:36:32.55#ibcon#[27=USB\r\n] 2006.183.07:36:32.55#ibcon#*before write, iclass 31, count 0 2006.183.07:36:32.55#ibcon#enter sib2, iclass 31, count 0 2006.183.07:36:32.55#ibcon#flushed, iclass 31, count 0 2006.183.07:36:32.55#ibcon#about to write, iclass 31, count 0 2006.183.07:36:32.55#ibcon#wrote, iclass 31, count 0 2006.183.07:36:32.55#ibcon#about to read 3, iclass 31, count 0 2006.183.07:36:32.58#ibcon#read 3, iclass 31, count 0 2006.183.07:36:32.58#ibcon#about to read 4, iclass 31, count 0 2006.183.07:36:32.58#ibcon#read 4, iclass 31, count 0 2006.183.07:36:32.58#ibcon#about to read 5, iclass 31, count 0 2006.183.07:36:32.58#ibcon#read 5, iclass 31, count 0 2006.183.07:36:32.58#ibcon#about to read 6, iclass 31, count 0 2006.183.07:36:32.58#ibcon#read 6, iclass 31, count 0 2006.183.07:36:32.58#ibcon#end of sib2, iclass 31, count 0 2006.183.07:36:32.58#ibcon#*after write, iclass 31, count 0 2006.183.07:36:32.58#ibcon#*before return 0, iclass 31, count 0 2006.183.07:36:32.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:32.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:36:32.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:36:32.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:36:32.58$vc4f8/vabw=wide 2006.183.07:36:32.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.07:36:32.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.07:36:32.58#ibcon#ireg 8 cls_cnt 0 2006.183.07:36:32.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:32.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:32.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:32.58#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:36:32.58#ibcon#first serial, iclass 33, count 0 2006.183.07:36:32.58#ibcon#enter sib2, iclass 33, count 0 2006.183.07:36:32.58#ibcon#flushed, iclass 33, count 0 2006.183.07:36:32.58#ibcon#about to write, iclass 33, count 0 2006.183.07:36:32.58#ibcon#wrote, iclass 33, count 0 2006.183.07:36:32.58#ibcon#about to read 3, iclass 33, count 0 2006.183.07:36:32.60#ibcon#read 3, iclass 33, count 0 2006.183.07:36:32.60#ibcon#about to read 4, iclass 33, count 0 2006.183.07:36:32.60#ibcon#read 4, iclass 33, count 0 2006.183.07:36:32.60#ibcon#about to read 5, iclass 33, count 0 2006.183.07:36:32.60#ibcon#read 5, iclass 33, count 0 2006.183.07:36:32.60#ibcon#about to read 6, iclass 33, count 0 2006.183.07:36:32.60#ibcon#read 6, iclass 33, count 0 2006.183.07:36:32.60#ibcon#end of sib2, iclass 33, count 0 2006.183.07:36:32.60#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:36:32.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:36:32.60#ibcon#[25=BW32\r\n] 2006.183.07:36:32.60#ibcon#*before write, iclass 33, count 0 2006.183.07:36:32.60#ibcon#enter sib2, iclass 33, count 0 2006.183.07:36:32.60#ibcon#flushed, iclass 33, count 0 2006.183.07:36:32.60#ibcon#about to write, iclass 33, count 0 2006.183.07:36:32.60#ibcon#wrote, iclass 33, count 0 2006.183.07:36:32.60#ibcon#about to read 3, iclass 33, count 0 2006.183.07:36:32.63#ibcon#read 3, iclass 33, count 0 2006.183.07:36:32.63#ibcon#about to read 4, iclass 33, count 0 2006.183.07:36:32.63#ibcon#read 4, iclass 33, count 0 2006.183.07:36:32.63#ibcon#about to read 5, iclass 33, count 0 2006.183.07:36:32.63#ibcon#read 5, iclass 33, count 0 2006.183.07:36:32.63#ibcon#about to read 6, iclass 33, count 0 2006.183.07:36:32.63#ibcon#read 6, iclass 33, count 0 2006.183.07:36:32.63#ibcon#end of sib2, iclass 33, count 0 2006.183.07:36:32.63#ibcon#*after write, iclass 33, count 0 2006.183.07:36:32.63#ibcon#*before return 0, iclass 33, count 0 2006.183.07:36:32.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:32.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:36:32.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:36:32.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:36:32.63$vc4f8/vbbw=wide 2006.183.07:36:32.63#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.07:36:32.63#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.07:36:32.63#ibcon#ireg 8 cls_cnt 0 2006.183.07:36:32.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:36:32.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:36:32.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:36:32.71#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:36:32.71#ibcon#first serial, iclass 35, count 0 2006.183.07:36:32.71#ibcon#enter sib2, iclass 35, count 0 2006.183.07:36:32.71#ibcon#flushed, iclass 35, count 0 2006.183.07:36:32.71#ibcon#about to write, iclass 35, count 0 2006.183.07:36:32.71#ibcon#wrote, iclass 35, count 0 2006.183.07:36:32.71#ibcon#about to read 3, iclass 35, count 0 2006.183.07:36:32.72#ibcon#read 3, iclass 35, count 0 2006.183.07:36:32.72#ibcon#about to read 4, iclass 35, count 0 2006.183.07:36:32.72#ibcon#read 4, iclass 35, count 0 2006.183.07:36:32.72#ibcon#about to read 5, iclass 35, count 0 2006.183.07:36:32.72#ibcon#read 5, iclass 35, count 0 2006.183.07:36:32.72#ibcon#about to read 6, iclass 35, count 0 2006.183.07:36:32.72#ibcon#read 6, iclass 35, count 0 2006.183.07:36:32.72#ibcon#end of sib2, iclass 35, count 0 2006.183.07:36:32.72#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:36:32.72#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:36:32.72#ibcon#[27=BW32\r\n] 2006.183.07:36:32.72#ibcon#*before write, iclass 35, count 0 2006.183.07:36:32.72#ibcon#enter sib2, iclass 35, count 0 2006.183.07:36:32.72#ibcon#flushed, iclass 35, count 0 2006.183.07:36:32.72#ibcon#about to write, iclass 35, count 0 2006.183.07:36:32.72#ibcon#wrote, iclass 35, count 0 2006.183.07:36:32.72#ibcon#about to read 3, iclass 35, count 0 2006.183.07:36:32.75#ibcon#read 3, iclass 35, count 0 2006.183.07:36:32.75#ibcon#about to read 4, iclass 35, count 0 2006.183.07:36:32.75#ibcon#read 4, iclass 35, count 0 2006.183.07:36:32.75#ibcon#about to read 5, iclass 35, count 0 2006.183.07:36:32.75#ibcon#read 5, iclass 35, count 0 2006.183.07:36:32.75#ibcon#about to read 6, iclass 35, count 0 2006.183.07:36:32.75#ibcon#read 6, iclass 35, count 0 2006.183.07:36:32.75#ibcon#end of sib2, iclass 35, count 0 2006.183.07:36:32.75#ibcon#*after write, iclass 35, count 0 2006.183.07:36:32.75#ibcon#*before return 0, iclass 35, count 0 2006.183.07:36:32.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:36:32.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:36:32.75#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:36:32.75#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:36:32.75$4f8m12a/ifd4f 2006.183.07:36:32.75$ifd4f/lo= 2006.183.07:36:32.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:36:32.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:36:32.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:36:32.75$ifd4f/patch= 2006.183.07:36:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:36:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:36:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:36:32.76$4f8m12a/"form=m,16.000,1:2 2006.183.07:36:32.76$4f8m12a/"tpicd 2006.183.07:36:32.76$4f8m12a/echo=off 2006.183.07:36:32.76$4f8m12a/xlog=off 2006.183.07:36:32.76:!2006.183.07:37:00 2006.183.07:36:41.14#trakl#Source acquired 2006.183.07:36:42.14#flagr#flagr/antenna,acquired 2006.183.07:37:00.01:preob 2006.183.07:37:01.14/onsource/TRACKING 2006.183.07:37:01.14:!2006.183.07:37:10 2006.183.07:37:10.00:data_valid=on 2006.183.07:37:10.00:midob 2006.183.07:37:10.14/onsource/TRACKING 2006.183.07:37:10.14/wx/27.90,996.2,88 2006.183.07:37:10.24/cable/+6.4550E-03 2006.183.07:37:11.33/va/01,08,usb,yes,29,30 2006.183.07:37:11.33/va/02,07,usb,yes,29,30 2006.183.07:37:11.33/va/03,06,usb,yes,30,31 2006.183.07:37:11.33/va/04,07,usb,yes,30,32 2006.183.07:37:11.33/va/05,07,usb,yes,32,33 2006.183.07:37:11.33/va/06,06,usb,yes,31,31 2006.183.07:37:11.33/va/07,06,usb,yes,31,31 2006.183.07:37:11.33/va/08,07,usb,yes,30,29 2006.183.07:37:11.56/valo/01,532.99,yes,locked 2006.183.07:37:11.56/valo/02,572.99,yes,locked 2006.183.07:37:11.56/valo/03,672.99,yes,locked 2006.183.07:37:11.56/valo/04,832.99,yes,locked 2006.183.07:37:11.56/valo/05,652.99,yes,locked 2006.183.07:37:11.56/valo/06,772.99,yes,locked 2006.183.07:37:11.56/valo/07,832.99,yes,locked 2006.183.07:37:11.56/valo/08,852.99,yes,locked 2006.183.07:37:12.65/vb/01,04,usb,yes,29,27 2006.183.07:37:12.65/vb/02,04,usb,yes,30,32 2006.183.07:37:12.65/vb/03,04,usb,yes,27,30 2006.183.07:37:12.65/vb/04,04,usb,yes,28,28 2006.183.07:37:12.65/vb/05,04,usb,yes,26,30 2006.183.07:37:12.65/vb/06,04,usb,yes,27,30 2006.183.07:37:12.65/vb/07,04,usb,yes,29,29 2006.183.07:37:12.65/vb/08,04,usb,yes,27,30 2006.183.07:37:12.88/vblo/01,632.99,yes,locked 2006.183.07:37:12.88/vblo/02,640.99,yes,locked 2006.183.07:37:12.88/vblo/03,656.99,yes,locked 2006.183.07:37:12.88/vblo/04,712.99,yes,locked 2006.183.07:37:12.88/vblo/05,744.99,yes,locked 2006.183.07:37:12.88/vblo/06,752.99,yes,locked 2006.183.07:37:12.88/vblo/07,734.99,yes,locked 2006.183.07:37:12.88/vblo/08,744.99,yes,locked 2006.183.07:37:13.03/vabw/8 2006.183.07:37:13.18/vbbw/8 2006.183.07:37:13.38/xfe/off,on,14.7 2006.183.07:37:13.76/ifatt/23,28,28,28 2006.183.07:37:14.07/fmout-gps/S +3.31E-07 2006.183.07:37:14.12:!2006.183.07:38:10 2006.183.07:38:10.00:data_valid=off 2006.183.07:38:10.01:postob 2006.183.07:38:10.09/cable/+6.4525E-03 2006.183.07:38:10.10/wx/27.91,996.3,88 2006.183.07:38:11.07/fmout-gps/S +3.29E-07 2006.183.07:38:11.08:scan_name=183-0739,k06183,60 2006.183.07:38:11.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.183.07:38:11.14#flagr#flagr/antenna,new-source 2006.183.07:38:12.14:checkk5 2006.183.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:38:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:38:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:38:14.02/chk_obsdata//k5ts1/T1830737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:38:14.39/chk_obsdata//k5ts2/T1830737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:38:14.76/chk_obsdata//k5ts3/T1830737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:38:15.14/chk_obsdata//k5ts4/T1830737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:38:15.83/k5log//k5ts1_log_newline 2006.183.07:38:16.52/k5log//k5ts2_log_newline 2006.183.07:38:17.21/k5log//k5ts3_log_newline 2006.183.07:38:17.90/k5log//k5ts4_log_newline 2006.183.07:38:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:38:17.93:4f8m12a=1 2006.183.07:38:17.93$4f8m12a/echo=on 2006.183.07:38:17.93$4f8m12a/pcalon 2006.183.07:38:17.93$pcalon/"no phase cal control is implemented here 2006.183.07:38:17.93$4f8m12a/"tpicd=stop 2006.183.07:38:17.93$4f8m12a/vc4f8 2006.183.07:38:17.93$vc4f8/valo=1,532.99 2006.183.07:38:17.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.07:38:17.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.07:38:17.93#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:17.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:17.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:17.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:17.93#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:38:17.93#ibcon#first serial, iclass 4, count 0 2006.183.07:38:17.93#ibcon#enter sib2, iclass 4, count 0 2006.183.07:38:17.93#ibcon#flushed, iclass 4, count 0 2006.183.07:38:17.93#ibcon#about to write, iclass 4, count 0 2006.183.07:38:17.93#ibcon#wrote, iclass 4, count 0 2006.183.07:38:17.93#ibcon#about to read 3, iclass 4, count 0 2006.183.07:38:17.97#ibcon#read 3, iclass 4, count 0 2006.183.07:38:17.97#ibcon#about to read 4, iclass 4, count 0 2006.183.07:38:17.97#ibcon#read 4, iclass 4, count 0 2006.183.07:38:17.97#ibcon#about to read 5, iclass 4, count 0 2006.183.07:38:17.97#ibcon#read 5, iclass 4, count 0 2006.183.07:38:17.97#ibcon#about to read 6, iclass 4, count 0 2006.183.07:38:17.97#ibcon#read 6, iclass 4, count 0 2006.183.07:38:17.97#ibcon#end of sib2, iclass 4, count 0 2006.183.07:38:17.97#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:38:17.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:38:17.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:38:17.97#ibcon#*before write, iclass 4, count 0 2006.183.07:38:17.97#ibcon#enter sib2, iclass 4, count 0 2006.183.07:38:17.97#ibcon#flushed, iclass 4, count 0 2006.183.07:38:17.97#ibcon#about to write, iclass 4, count 0 2006.183.07:38:17.97#ibcon#wrote, iclass 4, count 0 2006.183.07:38:17.97#ibcon#about to read 3, iclass 4, count 0 2006.183.07:38:18.01#ibcon#read 3, iclass 4, count 0 2006.183.07:38:18.01#ibcon#about to read 4, iclass 4, count 0 2006.183.07:38:18.01#ibcon#read 4, iclass 4, count 0 2006.183.07:38:18.01#ibcon#about to read 5, iclass 4, count 0 2006.183.07:38:18.01#ibcon#read 5, iclass 4, count 0 2006.183.07:38:18.01#ibcon#about to read 6, iclass 4, count 0 2006.183.07:38:18.01#ibcon#read 6, iclass 4, count 0 2006.183.07:38:18.01#ibcon#end of sib2, iclass 4, count 0 2006.183.07:38:18.01#ibcon#*after write, iclass 4, count 0 2006.183.07:38:18.01#ibcon#*before return 0, iclass 4, count 0 2006.183.07:38:18.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:18.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:18.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:38:18.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:38:18.01$vc4f8/va=1,8 2006.183.07:38:18.01#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.07:38:18.01#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.07:38:18.01#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:18.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:18.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:18.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:18.01#ibcon#enter wrdev, iclass 6, count 2 2006.183.07:38:18.01#ibcon#first serial, iclass 6, count 2 2006.183.07:38:18.01#ibcon#enter sib2, iclass 6, count 2 2006.183.07:38:18.01#ibcon#flushed, iclass 6, count 2 2006.183.07:38:18.01#ibcon#about to write, iclass 6, count 2 2006.183.07:38:18.01#ibcon#wrote, iclass 6, count 2 2006.183.07:38:18.01#ibcon#about to read 3, iclass 6, count 2 2006.183.07:38:18.03#ibcon#read 3, iclass 6, count 2 2006.183.07:38:18.03#ibcon#about to read 4, iclass 6, count 2 2006.183.07:38:18.03#ibcon#read 4, iclass 6, count 2 2006.183.07:38:18.03#ibcon#about to read 5, iclass 6, count 2 2006.183.07:38:18.03#ibcon#read 5, iclass 6, count 2 2006.183.07:38:18.03#ibcon#about to read 6, iclass 6, count 2 2006.183.07:38:18.03#ibcon#read 6, iclass 6, count 2 2006.183.07:38:18.03#ibcon#end of sib2, iclass 6, count 2 2006.183.07:38:18.03#ibcon#*mode == 0, iclass 6, count 2 2006.183.07:38:18.03#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.07:38:18.03#ibcon#[25=AT01-08\r\n] 2006.183.07:38:18.03#ibcon#*before write, iclass 6, count 2 2006.183.07:38:18.03#ibcon#enter sib2, iclass 6, count 2 2006.183.07:38:18.03#ibcon#flushed, iclass 6, count 2 2006.183.07:38:18.03#ibcon#about to write, iclass 6, count 2 2006.183.07:38:18.03#ibcon#wrote, iclass 6, count 2 2006.183.07:38:18.03#ibcon#about to read 3, iclass 6, count 2 2006.183.07:38:18.06#ibcon#read 3, iclass 6, count 2 2006.183.07:38:18.06#ibcon#about to read 4, iclass 6, count 2 2006.183.07:38:18.06#ibcon#read 4, iclass 6, count 2 2006.183.07:38:18.06#ibcon#about to read 5, iclass 6, count 2 2006.183.07:38:18.06#ibcon#read 5, iclass 6, count 2 2006.183.07:38:18.06#ibcon#about to read 6, iclass 6, count 2 2006.183.07:38:18.06#ibcon#read 6, iclass 6, count 2 2006.183.07:38:18.06#ibcon#end of sib2, iclass 6, count 2 2006.183.07:38:18.06#ibcon#*after write, iclass 6, count 2 2006.183.07:38:18.06#ibcon#*before return 0, iclass 6, count 2 2006.183.07:38:18.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:18.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:18.06#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.07:38:18.06#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:18.06#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:18.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:18.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:18.18#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:38:18.18#ibcon#first serial, iclass 6, count 0 2006.183.07:38:18.18#ibcon#enter sib2, iclass 6, count 0 2006.183.07:38:18.18#ibcon#flushed, iclass 6, count 0 2006.183.07:38:18.18#ibcon#about to write, iclass 6, count 0 2006.183.07:38:18.18#ibcon#wrote, iclass 6, count 0 2006.183.07:38:18.18#ibcon#about to read 3, iclass 6, count 0 2006.183.07:38:18.20#ibcon#read 3, iclass 6, count 0 2006.183.07:38:18.20#ibcon#about to read 4, iclass 6, count 0 2006.183.07:38:18.20#ibcon#read 4, iclass 6, count 0 2006.183.07:38:18.20#ibcon#about to read 5, iclass 6, count 0 2006.183.07:38:18.20#ibcon#read 5, iclass 6, count 0 2006.183.07:38:18.20#ibcon#about to read 6, iclass 6, count 0 2006.183.07:38:18.20#ibcon#read 6, iclass 6, count 0 2006.183.07:38:18.20#ibcon#end of sib2, iclass 6, count 0 2006.183.07:38:18.20#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:38:18.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:38:18.20#ibcon#[25=USB\r\n] 2006.183.07:38:18.20#ibcon#*before write, iclass 6, count 0 2006.183.07:38:18.20#ibcon#enter sib2, iclass 6, count 0 2006.183.07:38:18.20#ibcon#flushed, iclass 6, count 0 2006.183.07:38:18.20#ibcon#about to write, iclass 6, count 0 2006.183.07:38:18.20#ibcon#wrote, iclass 6, count 0 2006.183.07:38:18.20#ibcon#about to read 3, iclass 6, count 0 2006.183.07:38:18.24#ibcon#read 3, iclass 6, count 0 2006.183.07:38:18.24#ibcon#about to read 4, iclass 6, count 0 2006.183.07:38:18.24#ibcon#read 4, iclass 6, count 0 2006.183.07:38:18.24#ibcon#about to read 5, iclass 6, count 0 2006.183.07:38:18.24#ibcon#read 5, iclass 6, count 0 2006.183.07:38:18.24#ibcon#about to read 6, iclass 6, count 0 2006.183.07:38:18.24#ibcon#read 6, iclass 6, count 0 2006.183.07:38:18.24#ibcon#end of sib2, iclass 6, count 0 2006.183.07:38:18.24#ibcon#*after write, iclass 6, count 0 2006.183.07:38:18.24#ibcon#*before return 0, iclass 6, count 0 2006.183.07:38:18.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:18.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:18.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:38:18.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:38:18.24$vc4f8/valo=2,572.99 2006.183.07:38:18.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.07:38:18.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.07:38:18.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:18.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:18.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:18.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:18.24#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:38:18.24#ibcon#first serial, iclass 10, count 0 2006.183.07:38:18.24#ibcon#enter sib2, iclass 10, count 0 2006.183.07:38:18.24#ibcon#flushed, iclass 10, count 0 2006.183.07:38:18.24#ibcon#about to write, iclass 10, count 0 2006.183.07:38:18.24#ibcon#wrote, iclass 10, count 0 2006.183.07:38:18.24#ibcon#about to read 3, iclass 10, count 0 2006.183.07:38:18.25#ibcon#read 3, iclass 10, count 0 2006.183.07:38:18.25#ibcon#about to read 4, iclass 10, count 0 2006.183.07:38:18.25#ibcon#read 4, iclass 10, count 0 2006.183.07:38:18.25#ibcon#about to read 5, iclass 10, count 0 2006.183.07:38:18.25#ibcon#read 5, iclass 10, count 0 2006.183.07:38:18.25#ibcon#about to read 6, iclass 10, count 0 2006.183.07:38:18.25#ibcon#read 6, iclass 10, count 0 2006.183.07:38:18.25#ibcon#end of sib2, iclass 10, count 0 2006.183.07:38:18.25#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:38:18.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:38:18.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:38:18.25#ibcon#*before write, iclass 10, count 0 2006.183.07:38:18.25#ibcon#enter sib2, iclass 10, count 0 2006.183.07:38:18.25#ibcon#flushed, iclass 10, count 0 2006.183.07:38:18.25#ibcon#about to write, iclass 10, count 0 2006.183.07:38:18.25#ibcon#wrote, iclass 10, count 0 2006.183.07:38:18.25#ibcon#about to read 3, iclass 10, count 0 2006.183.07:38:18.29#ibcon#read 3, iclass 10, count 0 2006.183.07:38:18.29#ibcon#about to read 4, iclass 10, count 0 2006.183.07:38:18.29#ibcon#read 4, iclass 10, count 0 2006.183.07:38:18.29#ibcon#about to read 5, iclass 10, count 0 2006.183.07:38:18.29#ibcon#read 5, iclass 10, count 0 2006.183.07:38:18.29#ibcon#about to read 6, iclass 10, count 0 2006.183.07:38:18.29#ibcon#read 6, iclass 10, count 0 2006.183.07:38:18.29#ibcon#end of sib2, iclass 10, count 0 2006.183.07:38:18.29#ibcon#*after write, iclass 10, count 0 2006.183.07:38:18.29#ibcon#*before return 0, iclass 10, count 0 2006.183.07:38:18.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:18.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:18.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:38:18.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:38:18.29$vc4f8/va=2,7 2006.183.07:38:18.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.07:38:18.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.07:38:18.29#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:18.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:18.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:18.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:18.36#ibcon#enter wrdev, iclass 12, count 2 2006.183.07:38:18.36#ibcon#first serial, iclass 12, count 2 2006.183.07:38:18.36#ibcon#enter sib2, iclass 12, count 2 2006.183.07:38:18.36#ibcon#flushed, iclass 12, count 2 2006.183.07:38:18.36#ibcon#about to write, iclass 12, count 2 2006.183.07:38:18.37#ibcon#wrote, iclass 12, count 2 2006.183.07:38:18.37#ibcon#about to read 3, iclass 12, count 2 2006.183.07:38:18.38#ibcon#read 3, iclass 12, count 2 2006.183.07:38:18.38#ibcon#about to read 4, iclass 12, count 2 2006.183.07:38:18.38#ibcon#read 4, iclass 12, count 2 2006.183.07:38:18.38#ibcon#about to read 5, iclass 12, count 2 2006.183.07:38:18.38#ibcon#read 5, iclass 12, count 2 2006.183.07:38:18.38#ibcon#about to read 6, iclass 12, count 2 2006.183.07:38:18.38#ibcon#read 6, iclass 12, count 2 2006.183.07:38:18.38#ibcon#end of sib2, iclass 12, count 2 2006.183.07:38:18.38#ibcon#*mode == 0, iclass 12, count 2 2006.183.07:38:18.38#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.07:38:18.38#ibcon#[25=AT02-07\r\n] 2006.183.07:38:18.38#ibcon#*before write, iclass 12, count 2 2006.183.07:38:18.38#ibcon#enter sib2, iclass 12, count 2 2006.183.07:38:18.38#ibcon#flushed, iclass 12, count 2 2006.183.07:38:18.38#ibcon#about to write, iclass 12, count 2 2006.183.07:38:18.38#ibcon#wrote, iclass 12, count 2 2006.183.07:38:18.38#ibcon#about to read 3, iclass 12, count 2 2006.183.07:38:18.41#ibcon#read 3, iclass 12, count 2 2006.183.07:38:18.41#ibcon#about to read 4, iclass 12, count 2 2006.183.07:38:18.41#ibcon#read 4, iclass 12, count 2 2006.183.07:38:18.41#ibcon#about to read 5, iclass 12, count 2 2006.183.07:38:18.41#ibcon#read 5, iclass 12, count 2 2006.183.07:38:18.41#ibcon#about to read 6, iclass 12, count 2 2006.183.07:38:18.41#ibcon#read 6, iclass 12, count 2 2006.183.07:38:18.41#ibcon#end of sib2, iclass 12, count 2 2006.183.07:38:18.41#ibcon#*after write, iclass 12, count 2 2006.183.07:38:18.41#ibcon#*before return 0, iclass 12, count 2 2006.183.07:38:18.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:18.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:18.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.07:38:18.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:18.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:18.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:18.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:18.53#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:38:18.53#ibcon#first serial, iclass 12, count 0 2006.183.07:38:18.53#ibcon#enter sib2, iclass 12, count 0 2006.183.07:38:18.53#ibcon#flushed, iclass 12, count 0 2006.183.07:38:18.53#ibcon#about to write, iclass 12, count 0 2006.183.07:38:18.53#ibcon#wrote, iclass 12, count 0 2006.183.07:38:18.53#ibcon#about to read 3, iclass 12, count 0 2006.183.07:38:18.56#ibcon#read 3, iclass 12, count 0 2006.183.07:38:18.56#ibcon#about to read 4, iclass 12, count 0 2006.183.07:38:18.56#ibcon#read 4, iclass 12, count 0 2006.183.07:38:18.56#ibcon#about to read 5, iclass 12, count 0 2006.183.07:38:18.56#ibcon#read 5, iclass 12, count 0 2006.183.07:38:18.56#ibcon#about to read 6, iclass 12, count 0 2006.183.07:38:18.56#ibcon#read 6, iclass 12, count 0 2006.183.07:38:18.56#ibcon#end of sib2, iclass 12, count 0 2006.183.07:38:18.56#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:38:18.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:38:18.56#ibcon#[25=USB\r\n] 2006.183.07:38:18.56#ibcon#*before write, iclass 12, count 0 2006.183.07:38:18.56#ibcon#enter sib2, iclass 12, count 0 2006.183.07:38:18.56#ibcon#flushed, iclass 12, count 0 2006.183.07:38:18.56#ibcon#about to write, iclass 12, count 0 2006.183.07:38:18.56#ibcon#wrote, iclass 12, count 0 2006.183.07:38:18.56#ibcon#about to read 3, iclass 12, count 0 2006.183.07:38:18.58#ibcon#read 3, iclass 12, count 0 2006.183.07:38:18.58#ibcon#about to read 4, iclass 12, count 0 2006.183.07:38:18.58#ibcon#read 4, iclass 12, count 0 2006.183.07:38:18.58#ibcon#about to read 5, iclass 12, count 0 2006.183.07:38:18.58#ibcon#read 5, iclass 12, count 0 2006.183.07:38:18.58#ibcon#about to read 6, iclass 12, count 0 2006.183.07:38:18.58#ibcon#read 6, iclass 12, count 0 2006.183.07:38:18.58#ibcon#end of sib2, iclass 12, count 0 2006.183.07:38:18.58#ibcon#*after write, iclass 12, count 0 2006.183.07:38:18.58#ibcon#*before return 0, iclass 12, count 0 2006.183.07:38:18.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:18.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:18.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:38:18.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:38:18.58$vc4f8/valo=3,672.99 2006.183.07:38:18.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.07:38:18.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.07:38:18.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:18.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:18.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:18.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:18.58#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:38:18.58#ibcon#first serial, iclass 14, count 0 2006.183.07:38:18.58#ibcon#enter sib2, iclass 14, count 0 2006.183.07:38:18.58#ibcon#flushed, iclass 14, count 0 2006.183.07:38:18.58#ibcon#about to write, iclass 14, count 0 2006.183.07:38:18.58#ibcon#wrote, iclass 14, count 0 2006.183.07:38:18.58#ibcon#about to read 3, iclass 14, count 0 2006.183.07:38:18.61#ibcon#read 3, iclass 14, count 0 2006.183.07:38:18.61#ibcon#about to read 4, iclass 14, count 0 2006.183.07:38:18.61#ibcon#read 4, iclass 14, count 0 2006.183.07:38:18.61#ibcon#about to read 5, iclass 14, count 0 2006.183.07:38:18.61#ibcon#read 5, iclass 14, count 0 2006.183.07:38:18.61#ibcon#about to read 6, iclass 14, count 0 2006.183.07:38:18.61#ibcon#read 6, iclass 14, count 0 2006.183.07:38:18.61#ibcon#end of sib2, iclass 14, count 0 2006.183.07:38:18.61#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:38:18.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:38:18.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:38:18.61#ibcon#*before write, iclass 14, count 0 2006.183.07:38:18.61#ibcon#enter sib2, iclass 14, count 0 2006.183.07:38:18.61#ibcon#flushed, iclass 14, count 0 2006.183.07:38:18.61#ibcon#about to write, iclass 14, count 0 2006.183.07:38:18.61#ibcon#wrote, iclass 14, count 0 2006.183.07:38:18.61#ibcon#about to read 3, iclass 14, count 0 2006.183.07:38:18.64#ibcon#read 3, iclass 14, count 0 2006.183.07:38:18.64#ibcon#about to read 4, iclass 14, count 0 2006.183.07:38:18.64#ibcon#read 4, iclass 14, count 0 2006.183.07:38:18.64#ibcon#about to read 5, iclass 14, count 0 2006.183.07:38:18.64#ibcon#read 5, iclass 14, count 0 2006.183.07:38:18.64#ibcon#about to read 6, iclass 14, count 0 2006.183.07:38:18.64#ibcon#read 6, iclass 14, count 0 2006.183.07:38:18.64#ibcon#end of sib2, iclass 14, count 0 2006.183.07:38:18.64#ibcon#*after write, iclass 14, count 0 2006.183.07:38:18.64#ibcon#*before return 0, iclass 14, count 0 2006.183.07:38:18.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:18.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:18.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:38:18.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:38:18.65$vc4f8/va=3,6 2006.183.07:38:18.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.07:38:18.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.07:38:18.65#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:18.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:18.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:18.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:18.69#ibcon#enter wrdev, iclass 16, count 2 2006.183.07:38:18.69#ibcon#first serial, iclass 16, count 2 2006.183.07:38:18.69#ibcon#enter sib2, iclass 16, count 2 2006.183.07:38:18.69#ibcon#flushed, iclass 16, count 2 2006.183.07:38:18.69#ibcon#about to write, iclass 16, count 2 2006.183.07:38:18.69#ibcon#wrote, iclass 16, count 2 2006.183.07:38:18.69#ibcon#about to read 3, iclass 16, count 2 2006.183.07:38:18.72#ibcon#read 3, iclass 16, count 2 2006.183.07:38:18.72#ibcon#about to read 4, iclass 16, count 2 2006.183.07:38:18.72#ibcon#read 4, iclass 16, count 2 2006.183.07:38:18.72#ibcon#about to read 5, iclass 16, count 2 2006.183.07:38:18.72#ibcon#read 5, iclass 16, count 2 2006.183.07:38:18.72#ibcon#about to read 6, iclass 16, count 2 2006.183.07:38:18.72#ibcon#read 6, iclass 16, count 2 2006.183.07:38:18.72#ibcon#end of sib2, iclass 16, count 2 2006.183.07:38:18.72#ibcon#*mode == 0, iclass 16, count 2 2006.183.07:38:18.72#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.07:38:18.72#ibcon#[25=AT03-06\r\n] 2006.183.07:38:18.72#ibcon#*before write, iclass 16, count 2 2006.183.07:38:18.72#ibcon#enter sib2, iclass 16, count 2 2006.183.07:38:18.72#ibcon#flushed, iclass 16, count 2 2006.183.07:38:18.72#ibcon#about to write, iclass 16, count 2 2006.183.07:38:18.72#ibcon#wrote, iclass 16, count 2 2006.183.07:38:18.72#ibcon#about to read 3, iclass 16, count 2 2006.183.07:38:18.75#ibcon#read 3, iclass 16, count 2 2006.183.07:38:18.75#ibcon#about to read 4, iclass 16, count 2 2006.183.07:38:18.75#ibcon#read 4, iclass 16, count 2 2006.183.07:38:18.75#ibcon#about to read 5, iclass 16, count 2 2006.183.07:38:18.75#ibcon#read 5, iclass 16, count 2 2006.183.07:38:18.75#ibcon#about to read 6, iclass 16, count 2 2006.183.07:38:18.75#ibcon#read 6, iclass 16, count 2 2006.183.07:38:18.75#ibcon#end of sib2, iclass 16, count 2 2006.183.07:38:18.75#ibcon#*after write, iclass 16, count 2 2006.183.07:38:18.75#ibcon#*before return 0, iclass 16, count 2 2006.183.07:38:18.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:18.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:18.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.07:38:18.75#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:18.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:18.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:18.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:18.87#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:38:18.87#ibcon#first serial, iclass 16, count 0 2006.183.07:38:18.87#ibcon#enter sib2, iclass 16, count 0 2006.183.07:38:18.87#ibcon#flushed, iclass 16, count 0 2006.183.07:38:18.87#ibcon#about to write, iclass 16, count 0 2006.183.07:38:18.87#ibcon#wrote, iclass 16, count 0 2006.183.07:38:18.87#ibcon#about to read 3, iclass 16, count 0 2006.183.07:38:18.89#ibcon#read 3, iclass 16, count 0 2006.183.07:38:18.89#ibcon#about to read 4, iclass 16, count 0 2006.183.07:38:18.89#ibcon#read 4, iclass 16, count 0 2006.183.07:38:18.89#ibcon#about to read 5, iclass 16, count 0 2006.183.07:38:18.89#ibcon#read 5, iclass 16, count 0 2006.183.07:38:18.89#ibcon#about to read 6, iclass 16, count 0 2006.183.07:38:18.89#ibcon#read 6, iclass 16, count 0 2006.183.07:38:18.89#ibcon#end of sib2, iclass 16, count 0 2006.183.07:38:18.89#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:38:18.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:38:18.89#ibcon#[25=USB\r\n] 2006.183.07:38:18.89#ibcon#*before write, iclass 16, count 0 2006.183.07:38:18.89#ibcon#enter sib2, iclass 16, count 0 2006.183.07:38:18.89#ibcon#flushed, iclass 16, count 0 2006.183.07:38:18.89#ibcon#about to write, iclass 16, count 0 2006.183.07:38:18.89#ibcon#wrote, iclass 16, count 0 2006.183.07:38:18.89#ibcon#about to read 3, iclass 16, count 0 2006.183.07:38:18.92#ibcon#read 3, iclass 16, count 0 2006.183.07:38:18.92#ibcon#about to read 4, iclass 16, count 0 2006.183.07:38:18.92#ibcon#read 4, iclass 16, count 0 2006.183.07:38:18.92#ibcon#about to read 5, iclass 16, count 0 2006.183.07:38:18.92#ibcon#read 5, iclass 16, count 0 2006.183.07:38:18.92#ibcon#about to read 6, iclass 16, count 0 2006.183.07:38:18.92#ibcon#read 6, iclass 16, count 0 2006.183.07:38:18.92#ibcon#end of sib2, iclass 16, count 0 2006.183.07:38:18.92#ibcon#*after write, iclass 16, count 0 2006.183.07:38:18.92#ibcon#*before return 0, iclass 16, count 0 2006.183.07:38:18.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:18.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:18.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:38:18.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:38:18.92$vc4f8/valo=4,832.99 2006.183.07:38:18.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.07:38:18.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.07:38:18.92#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:18.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:18.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:18.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:18.92#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:38:18.92#ibcon#first serial, iclass 18, count 0 2006.183.07:38:18.92#ibcon#enter sib2, iclass 18, count 0 2006.183.07:38:18.92#ibcon#flushed, iclass 18, count 0 2006.183.07:38:18.92#ibcon#about to write, iclass 18, count 0 2006.183.07:38:18.92#ibcon#wrote, iclass 18, count 0 2006.183.07:38:18.92#ibcon#about to read 3, iclass 18, count 0 2006.183.07:38:18.94#ibcon#read 3, iclass 18, count 0 2006.183.07:38:18.94#ibcon#about to read 4, iclass 18, count 0 2006.183.07:38:18.94#ibcon#read 4, iclass 18, count 0 2006.183.07:38:18.94#ibcon#about to read 5, iclass 18, count 0 2006.183.07:38:18.94#ibcon#read 5, iclass 18, count 0 2006.183.07:38:18.94#ibcon#about to read 6, iclass 18, count 0 2006.183.07:38:18.94#ibcon#read 6, iclass 18, count 0 2006.183.07:38:18.94#ibcon#end of sib2, iclass 18, count 0 2006.183.07:38:18.94#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:38:18.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:38:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:38:18.94#ibcon#*before write, iclass 18, count 0 2006.183.07:38:18.94#ibcon#enter sib2, iclass 18, count 0 2006.183.07:38:18.94#ibcon#flushed, iclass 18, count 0 2006.183.07:38:18.94#ibcon#about to write, iclass 18, count 0 2006.183.07:38:18.94#ibcon#wrote, iclass 18, count 0 2006.183.07:38:18.94#ibcon#about to read 3, iclass 18, count 0 2006.183.07:38:18.98#ibcon#read 3, iclass 18, count 0 2006.183.07:38:18.98#ibcon#about to read 4, iclass 18, count 0 2006.183.07:38:18.98#ibcon#read 4, iclass 18, count 0 2006.183.07:38:18.98#ibcon#about to read 5, iclass 18, count 0 2006.183.07:38:18.98#ibcon#read 5, iclass 18, count 0 2006.183.07:38:18.98#ibcon#about to read 6, iclass 18, count 0 2006.183.07:38:18.98#ibcon#read 6, iclass 18, count 0 2006.183.07:38:18.98#ibcon#end of sib2, iclass 18, count 0 2006.183.07:38:18.98#ibcon#*after write, iclass 18, count 0 2006.183.07:38:18.98#ibcon#*before return 0, iclass 18, count 0 2006.183.07:38:18.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:18.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:18.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:38:18.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:38:18.98$vc4f8/va=4,7 2006.183.07:38:18.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.07:38:18.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.07:38:18.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:18.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:19.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:19.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:19.04#ibcon#enter wrdev, iclass 20, count 2 2006.183.07:38:19.04#ibcon#first serial, iclass 20, count 2 2006.183.07:38:19.04#ibcon#enter sib2, iclass 20, count 2 2006.183.07:38:19.04#ibcon#flushed, iclass 20, count 2 2006.183.07:38:19.04#ibcon#about to write, iclass 20, count 2 2006.183.07:38:19.04#ibcon#wrote, iclass 20, count 2 2006.183.07:38:19.04#ibcon#about to read 3, iclass 20, count 2 2006.183.07:38:19.06#ibcon#read 3, iclass 20, count 2 2006.183.07:38:19.06#ibcon#about to read 4, iclass 20, count 2 2006.183.07:38:19.06#ibcon#read 4, iclass 20, count 2 2006.183.07:38:19.06#ibcon#about to read 5, iclass 20, count 2 2006.183.07:38:19.06#ibcon#read 5, iclass 20, count 2 2006.183.07:38:19.06#ibcon#about to read 6, iclass 20, count 2 2006.183.07:38:19.06#ibcon#read 6, iclass 20, count 2 2006.183.07:38:19.06#ibcon#end of sib2, iclass 20, count 2 2006.183.07:38:19.06#ibcon#*mode == 0, iclass 20, count 2 2006.183.07:38:19.06#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.07:38:19.06#ibcon#[25=AT04-07\r\n] 2006.183.07:38:19.06#ibcon#*before write, iclass 20, count 2 2006.183.07:38:19.06#ibcon#enter sib2, iclass 20, count 2 2006.183.07:38:19.06#ibcon#flushed, iclass 20, count 2 2006.183.07:38:19.06#ibcon#about to write, iclass 20, count 2 2006.183.07:38:19.06#ibcon#wrote, iclass 20, count 2 2006.183.07:38:19.06#ibcon#about to read 3, iclass 20, count 2 2006.183.07:38:19.09#ibcon#read 3, iclass 20, count 2 2006.183.07:38:19.09#ibcon#about to read 4, iclass 20, count 2 2006.183.07:38:19.09#ibcon#read 4, iclass 20, count 2 2006.183.07:38:19.09#ibcon#about to read 5, iclass 20, count 2 2006.183.07:38:19.09#ibcon#read 5, iclass 20, count 2 2006.183.07:38:19.09#ibcon#about to read 6, iclass 20, count 2 2006.183.07:38:19.09#ibcon#read 6, iclass 20, count 2 2006.183.07:38:19.09#ibcon#end of sib2, iclass 20, count 2 2006.183.07:38:19.09#ibcon#*after write, iclass 20, count 2 2006.183.07:38:19.09#ibcon#*before return 0, iclass 20, count 2 2006.183.07:38:19.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:19.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:19.09#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.07:38:19.09#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:19.09#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:19.21#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:19.21#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:19.21#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:38:19.21#ibcon#first serial, iclass 20, count 0 2006.183.07:38:19.21#ibcon#enter sib2, iclass 20, count 0 2006.183.07:38:19.21#ibcon#flushed, iclass 20, count 0 2006.183.07:38:19.21#ibcon#about to write, iclass 20, count 0 2006.183.07:38:19.21#ibcon#wrote, iclass 20, count 0 2006.183.07:38:19.21#ibcon#about to read 3, iclass 20, count 0 2006.183.07:38:19.23#ibcon#read 3, iclass 20, count 0 2006.183.07:38:19.23#ibcon#about to read 4, iclass 20, count 0 2006.183.07:38:19.23#ibcon#read 4, iclass 20, count 0 2006.183.07:38:19.23#ibcon#about to read 5, iclass 20, count 0 2006.183.07:38:19.23#ibcon#read 5, iclass 20, count 0 2006.183.07:38:19.23#ibcon#about to read 6, iclass 20, count 0 2006.183.07:38:19.23#ibcon#read 6, iclass 20, count 0 2006.183.07:38:19.23#ibcon#end of sib2, iclass 20, count 0 2006.183.07:38:19.23#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:38:19.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:38:19.23#ibcon#[25=USB\r\n] 2006.183.07:38:19.23#ibcon#*before write, iclass 20, count 0 2006.183.07:38:19.23#ibcon#enter sib2, iclass 20, count 0 2006.183.07:38:19.23#ibcon#flushed, iclass 20, count 0 2006.183.07:38:19.23#ibcon#about to write, iclass 20, count 0 2006.183.07:38:19.23#ibcon#wrote, iclass 20, count 0 2006.183.07:38:19.23#ibcon#about to read 3, iclass 20, count 0 2006.183.07:38:19.26#ibcon#read 3, iclass 20, count 0 2006.183.07:38:19.26#ibcon#about to read 4, iclass 20, count 0 2006.183.07:38:19.26#ibcon#read 4, iclass 20, count 0 2006.183.07:38:19.26#ibcon#about to read 5, iclass 20, count 0 2006.183.07:38:19.26#ibcon#read 5, iclass 20, count 0 2006.183.07:38:19.26#ibcon#about to read 6, iclass 20, count 0 2006.183.07:38:19.26#ibcon#read 6, iclass 20, count 0 2006.183.07:38:19.26#ibcon#end of sib2, iclass 20, count 0 2006.183.07:38:19.26#ibcon#*after write, iclass 20, count 0 2006.183.07:38:19.26#ibcon#*before return 0, iclass 20, count 0 2006.183.07:38:19.26#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:19.26#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:19.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:38:19.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:38:19.26$vc4f8/valo=5,652.99 2006.183.07:38:19.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.07:38:19.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.07:38:19.26#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:19.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:38:19.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:38:19.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:38:19.26#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:38:19.26#ibcon#first serial, iclass 22, count 0 2006.183.07:38:19.26#ibcon#enter sib2, iclass 22, count 0 2006.183.07:38:19.26#ibcon#flushed, iclass 22, count 0 2006.183.07:38:19.26#ibcon#about to write, iclass 22, count 0 2006.183.07:38:19.26#ibcon#wrote, iclass 22, count 0 2006.183.07:38:19.26#ibcon#about to read 3, iclass 22, count 0 2006.183.07:38:19.28#ibcon#read 3, iclass 22, count 0 2006.183.07:38:19.28#ibcon#about to read 4, iclass 22, count 0 2006.183.07:38:19.28#ibcon#read 4, iclass 22, count 0 2006.183.07:38:19.28#ibcon#about to read 5, iclass 22, count 0 2006.183.07:38:19.28#ibcon#read 5, iclass 22, count 0 2006.183.07:38:19.28#ibcon#about to read 6, iclass 22, count 0 2006.183.07:38:19.28#ibcon#read 6, iclass 22, count 0 2006.183.07:38:19.28#ibcon#end of sib2, iclass 22, count 0 2006.183.07:38:19.28#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:38:19.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:38:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:38:19.28#ibcon#*before write, iclass 22, count 0 2006.183.07:38:19.28#ibcon#enter sib2, iclass 22, count 0 2006.183.07:38:19.28#ibcon#flushed, iclass 22, count 0 2006.183.07:38:19.28#ibcon#about to write, iclass 22, count 0 2006.183.07:38:19.28#ibcon#wrote, iclass 22, count 0 2006.183.07:38:19.28#ibcon#about to read 3, iclass 22, count 0 2006.183.07:38:19.32#ibcon#read 3, iclass 22, count 0 2006.183.07:38:19.32#ibcon#about to read 4, iclass 22, count 0 2006.183.07:38:19.32#ibcon#read 4, iclass 22, count 0 2006.183.07:38:19.32#ibcon#about to read 5, iclass 22, count 0 2006.183.07:38:19.32#ibcon#read 5, iclass 22, count 0 2006.183.07:38:19.32#ibcon#about to read 6, iclass 22, count 0 2006.183.07:38:19.32#ibcon#read 6, iclass 22, count 0 2006.183.07:38:19.32#ibcon#end of sib2, iclass 22, count 0 2006.183.07:38:19.32#ibcon#*after write, iclass 22, count 0 2006.183.07:38:19.32#ibcon#*before return 0, iclass 22, count 0 2006.183.07:38:19.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:38:19.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:38:19.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:38:19.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:38:19.32$vc4f8/va=5,7 2006.183.07:38:19.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.07:38:19.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.07:38:19.32#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:19.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:38:19.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:38:19.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:38:19.38#ibcon#enter wrdev, iclass 24, count 2 2006.183.07:38:19.38#ibcon#first serial, iclass 24, count 2 2006.183.07:38:19.38#ibcon#enter sib2, iclass 24, count 2 2006.183.07:38:19.38#ibcon#flushed, iclass 24, count 2 2006.183.07:38:19.38#ibcon#about to write, iclass 24, count 2 2006.183.07:38:19.38#ibcon#wrote, iclass 24, count 2 2006.183.07:38:19.38#ibcon#about to read 3, iclass 24, count 2 2006.183.07:38:19.40#ibcon#read 3, iclass 24, count 2 2006.183.07:38:19.40#ibcon#about to read 4, iclass 24, count 2 2006.183.07:38:19.40#ibcon#read 4, iclass 24, count 2 2006.183.07:38:19.40#ibcon#about to read 5, iclass 24, count 2 2006.183.07:38:19.40#ibcon#read 5, iclass 24, count 2 2006.183.07:38:19.40#ibcon#about to read 6, iclass 24, count 2 2006.183.07:38:19.40#ibcon#read 6, iclass 24, count 2 2006.183.07:38:19.40#ibcon#end of sib2, iclass 24, count 2 2006.183.07:38:19.40#ibcon#*mode == 0, iclass 24, count 2 2006.183.07:38:19.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.07:38:19.40#ibcon#[25=AT05-07\r\n] 2006.183.07:38:19.40#ibcon#*before write, iclass 24, count 2 2006.183.07:38:19.40#ibcon#enter sib2, iclass 24, count 2 2006.183.07:38:19.40#ibcon#flushed, iclass 24, count 2 2006.183.07:38:19.40#ibcon#about to write, iclass 24, count 2 2006.183.07:38:19.40#ibcon#wrote, iclass 24, count 2 2006.183.07:38:19.40#ibcon#about to read 3, iclass 24, count 2 2006.183.07:38:19.43#ibcon#read 3, iclass 24, count 2 2006.183.07:38:19.43#ibcon#about to read 4, iclass 24, count 2 2006.183.07:38:19.43#ibcon#read 4, iclass 24, count 2 2006.183.07:38:19.43#ibcon#about to read 5, iclass 24, count 2 2006.183.07:38:19.43#ibcon#read 5, iclass 24, count 2 2006.183.07:38:19.43#ibcon#about to read 6, iclass 24, count 2 2006.183.07:38:19.43#ibcon#read 6, iclass 24, count 2 2006.183.07:38:19.43#ibcon#end of sib2, iclass 24, count 2 2006.183.07:38:19.43#ibcon#*after write, iclass 24, count 2 2006.183.07:38:19.43#ibcon#*before return 0, iclass 24, count 2 2006.183.07:38:19.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:38:19.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:38:19.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.07:38:19.43#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:19.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:38:19.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:38:19.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:38:19.55#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:38:19.55#ibcon#first serial, iclass 24, count 0 2006.183.07:38:19.55#ibcon#enter sib2, iclass 24, count 0 2006.183.07:38:19.55#ibcon#flushed, iclass 24, count 0 2006.183.07:38:19.55#ibcon#about to write, iclass 24, count 0 2006.183.07:38:19.55#ibcon#wrote, iclass 24, count 0 2006.183.07:38:19.55#ibcon#about to read 3, iclass 24, count 0 2006.183.07:38:19.57#ibcon#read 3, iclass 24, count 0 2006.183.07:38:19.57#ibcon#about to read 4, iclass 24, count 0 2006.183.07:38:19.57#ibcon#read 4, iclass 24, count 0 2006.183.07:38:19.57#ibcon#about to read 5, iclass 24, count 0 2006.183.07:38:19.57#ibcon#read 5, iclass 24, count 0 2006.183.07:38:19.57#ibcon#about to read 6, iclass 24, count 0 2006.183.07:38:19.57#ibcon#read 6, iclass 24, count 0 2006.183.07:38:19.57#ibcon#end of sib2, iclass 24, count 0 2006.183.07:38:19.57#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:38:19.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:38:19.57#ibcon#[25=USB\r\n] 2006.183.07:38:19.57#ibcon#*before write, iclass 24, count 0 2006.183.07:38:19.57#ibcon#enter sib2, iclass 24, count 0 2006.183.07:38:19.57#ibcon#flushed, iclass 24, count 0 2006.183.07:38:19.57#ibcon#about to write, iclass 24, count 0 2006.183.07:38:19.57#ibcon#wrote, iclass 24, count 0 2006.183.07:38:19.57#ibcon#about to read 3, iclass 24, count 0 2006.183.07:38:19.60#ibcon#read 3, iclass 24, count 0 2006.183.07:38:19.60#ibcon#about to read 4, iclass 24, count 0 2006.183.07:38:19.60#ibcon#read 4, iclass 24, count 0 2006.183.07:38:19.60#ibcon#about to read 5, iclass 24, count 0 2006.183.07:38:19.60#ibcon#read 5, iclass 24, count 0 2006.183.07:38:19.60#ibcon#about to read 6, iclass 24, count 0 2006.183.07:38:19.60#ibcon#read 6, iclass 24, count 0 2006.183.07:38:19.60#ibcon#end of sib2, iclass 24, count 0 2006.183.07:38:19.60#ibcon#*after write, iclass 24, count 0 2006.183.07:38:19.60#ibcon#*before return 0, iclass 24, count 0 2006.183.07:38:19.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:38:19.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:38:19.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:38:19.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:38:19.60$vc4f8/valo=6,772.99 2006.183.07:38:19.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.07:38:19.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.07:38:19.60#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:19.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:38:19.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:38:19.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:38:19.60#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:38:19.60#ibcon#first serial, iclass 26, count 0 2006.183.07:38:19.60#ibcon#enter sib2, iclass 26, count 0 2006.183.07:38:19.60#ibcon#flushed, iclass 26, count 0 2006.183.07:38:19.60#ibcon#about to write, iclass 26, count 0 2006.183.07:38:19.60#ibcon#wrote, iclass 26, count 0 2006.183.07:38:19.60#ibcon#about to read 3, iclass 26, count 0 2006.183.07:38:19.62#ibcon#read 3, iclass 26, count 0 2006.183.07:38:19.62#ibcon#about to read 4, iclass 26, count 0 2006.183.07:38:19.62#ibcon#read 4, iclass 26, count 0 2006.183.07:38:19.62#ibcon#about to read 5, iclass 26, count 0 2006.183.07:38:19.62#ibcon#read 5, iclass 26, count 0 2006.183.07:38:19.62#ibcon#about to read 6, iclass 26, count 0 2006.183.07:38:19.62#ibcon#read 6, iclass 26, count 0 2006.183.07:38:19.62#ibcon#end of sib2, iclass 26, count 0 2006.183.07:38:19.62#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:38:19.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:38:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:38:19.62#ibcon#*before write, iclass 26, count 0 2006.183.07:38:19.62#ibcon#enter sib2, iclass 26, count 0 2006.183.07:38:19.62#ibcon#flushed, iclass 26, count 0 2006.183.07:38:19.62#ibcon#about to write, iclass 26, count 0 2006.183.07:38:19.62#ibcon#wrote, iclass 26, count 0 2006.183.07:38:19.62#ibcon#about to read 3, iclass 26, count 0 2006.183.07:38:19.66#ibcon#read 3, iclass 26, count 0 2006.183.07:38:19.66#ibcon#about to read 4, iclass 26, count 0 2006.183.07:38:19.66#ibcon#read 4, iclass 26, count 0 2006.183.07:38:19.66#ibcon#about to read 5, iclass 26, count 0 2006.183.07:38:19.66#ibcon#read 5, iclass 26, count 0 2006.183.07:38:19.66#ibcon#about to read 6, iclass 26, count 0 2006.183.07:38:19.66#ibcon#read 6, iclass 26, count 0 2006.183.07:38:19.66#ibcon#end of sib2, iclass 26, count 0 2006.183.07:38:19.66#ibcon#*after write, iclass 26, count 0 2006.183.07:38:19.66#ibcon#*before return 0, iclass 26, count 0 2006.183.07:38:19.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:38:19.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:38:19.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:38:19.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:38:19.66$vc4f8/va=6,6 2006.183.07:38:19.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.07:38:19.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.07:38:19.66#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:19.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:19.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:19.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:19.72#ibcon#enter wrdev, iclass 28, count 2 2006.183.07:38:19.72#ibcon#first serial, iclass 28, count 2 2006.183.07:38:19.72#ibcon#enter sib2, iclass 28, count 2 2006.183.07:38:19.72#ibcon#flushed, iclass 28, count 2 2006.183.07:38:19.72#ibcon#about to write, iclass 28, count 2 2006.183.07:38:19.72#ibcon#wrote, iclass 28, count 2 2006.183.07:38:19.72#ibcon#about to read 3, iclass 28, count 2 2006.183.07:38:19.74#ibcon#read 3, iclass 28, count 2 2006.183.07:38:19.74#ibcon#about to read 4, iclass 28, count 2 2006.183.07:38:19.74#ibcon#read 4, iclass 28, count 2 2006.183.07:38:19.74#ibcon#about to read 5, iclass 28, count 2 2006.183.07:38:19.74#ibcon#read 5, iclass 28, count 2 2006.183.07:38:19.74#ibcon#about to read 6, iclass 28, count 2 2006.183.07:38:19.74#ibcon#read 6, iclass 28, count 2 2006.183.07:38:19.74#ibcon#end of sib2, iclass 28, count 2 2006.183.07:38:19.74#ibcon#*mode == 0, iclass 28, count 2 2006.183.07:38:19.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.07:38:19.74#ibcon#[25=AT06-06\r\n] 2006.183.07:38:19.74#ibcon#*before write, iclass 28, count 2 2006.183.07:38:19.74#ibcon#enter sib2, iclass 28, count 2 2006.183.07:38:19.74#ibcon#flushed, iclass 28, count 2 2006.183.07:38:19.74#ibcon#about to write, iclass 28, count 2 2006.183.07:38:19.74#ibcon#wrote, iclass 28, count 2 2006.183.07:38:19.74#ibcon#about to read 3, iclass 28, count 2 2006.183.07:38:19.77#ibcon#read 3, iclass 28, count 2 2006.183.07:38:19.77#ibcon#about to read 4, iclass 28, count 2 2006.183.07:38:19.77#ibcon#read 4, iclass 28, count 2 2006.183.07:38:19.77#ibcon#about to read 5, iclass 28, count 2 2006.183.07:38:19.77#ibcon#read 5, iclass 28, count 2 2006.183.07:38:19.77#ibcon#about to read 6, iclass 28, count 2 2006.183.07:38:19.77#ibcon#read 6, iclass 28, count 2 2006.183.07:38:19.77#ibcon#end of sib2, iclass 28, count 2 2006.183.07:38:19.77#ibcon#*after write, iclass 28, count 2 2006.183.07:38:19.77#ibcon#*before return 0, iclass 28, count 2 2006.183.07:38:19.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:19.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:19.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.07:38:19.77#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:19.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:19.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:19.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:19.89#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:38:19.89#ibcon#first serial, iclass 28, count 0 2006.183.07:38:19.89#ibcon#enter sib2, iclass 28, count 0 2006.183.07:38:19.89#ibcon#flushed, iclass 28, count 0 2006.183.07:38:19.89#ibcon#about to write, iclass 28, count 0 2006.183.07:38:19.89#ibcon#wrote, iclass 28, count 0 2006.183.07:38:19.89#ibcon#about to read 3, iclass 28, count 0 2006.183.07:38:19.91#ibcon#read 3, iclass 28, count 0 2006.183.07:38:19.91#ibcon#about to read 4, iclass 28, count 0 2006.183.07:38:19.91#ibcon#read 4, iclass 28, count 0 2006.183.07:38:19.91#ibcon#about to read 5, iclass 28, count 0 2006.183.07:38:19.91#ibcon#read 5, iclass 28, count 0 2006.183.07:38:19.91#ibcon#about to read 6, iclass 28, count 0 2006.183.07:38:19.91#ibcon#read 6, iclass 28, count 0 2006.183.07:38:19.91#ibcon#end of sib2, iclass 28, count 0 2006.183.07:38:19.91#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:38:19.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:38:19.91#ibcon#[25=USB\r\n] 2006.183.07:38:19.91#ibcon#*before write, iclass 28, count 0 2006.183.07:38:19.91#ibcon#enter sib2, iclass 28, count 0 2006.183.07:38:19.91#ibcon#flushed, iclass 28, count 0 2006.183.07:38:19.91#ibcon#about to write, iclass 28, count 0 2006.183.07:38:19.91#ibcon#wrote, iclass 28, count 0 2006.183.07:38:19.91#ibcon#about to read 3, iclass 28, count 0 2006.183.07:38:19.94#ibcon#read 3, iclass 28, count 0 2006.183.07:38:19.94#ibcon#about to read 4, iclass 28, count 0 2006.183.07:38:19.94#ibcon#read 4, iclass 28, count 0 2006.183.07:38:19.94#ibcon#about to read 5, iclass 28, count 0 2006.183.07:38:19.94#ibcon#read 5, iclass 28, count 0 2006.183.07:38:19.94#ibcon#about to read 6, iclass 28, count 0 2006.183.07:38:19.94#ibcon#read 6, iclass 28, count 0 2006.183.07:38:19.94#ibcon#end of sib2, iclass 28, count 0 2006.183.07:38:19.94#ibcon#*after write, iclass 28, count 0 2006.183.07:38:19.94#ibcon#*before return 0, iclass 28, count 0 2006.183.07:38:19.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:19.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:19.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:38:19.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:38:19.94$vc4f8/valo=7,832.99 2006.183.07:38:19.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.07:38:19.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.07:38:19.94#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:19.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:19.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:19.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:19.94#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:38:19.94#ibcon#first serial, iclass 30, count 0 2006.183.07:38:19.94#ibcon#enter sib2, iclass 30, count 0 2006.183.07:38:19.94#ibcon#flushed, iclass 30, count 0 2006.183.07:38:19.94#ibcon#about to write, iclass 30, count 0 2006.183.07:38:19.94#ibcon#wrote, iclass 30, count 0 2006.183.07:38:19.94#ibcon#about to read 3, iclass 30, count 0 2006.183.07:38:19.96#ibcon#read 3, iclass 30, count 0 2006.183.07:38:19.96#ibcon#about to read 4, iclass 30, count 0 2006.183.07:38:19.96#ibcon#read 4, iclass 30, count 0 2006.183.07:38:19.96#ibcon#about to read 5, iclass 30, count 0 2006.183.07:38:19.96#ibcon#read 5, iclass 30, count 0 2006.183.07:38:19.96#ibcon#about to read 6, iclass 30, count 0 2006.183.07:38:19.96#ibcon#read 6, iclass 30, count 0 2006.183.07:38:19.96#ibcon#end of sib2, iclass 30, count 0 2006.183.07:38:19.96#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:38:19.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:38:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:38:19.96#ibcon#*before write, iclass 30, count 0 2006.183.07:38:19.96#ibcon#enter sib2, iclass 30, count 0 2006.183.07:38:19.96#ibcon#flushed, iclass 30, count 0 2006.183.07:38:19.96#ibcon#about to write, iclass 30, count 0 2006.183.07:38:19.96#ibcon#wrote, iclass 30, count 0 2006.183.07:38:19.96#ibcon#about to read 3, iclass 30, count 0 2006.183.07:38:20.00#ibcon#read 3, iclass 30, count 0 2006.183.07:38:20.00#ibcon#about to read 4, iclass 30, count 0 2006.183.07:38:20.00#ibcon#read 4, iclass 30, count 0 2006.183.07:38:20.00#ibcon#about to read 5, iclass 30, count 0 2006.183.07:38:20.00#ibcon#read 5, iclass 30, count 0 2006.183.07:38:20.00#ibcon#about to read 6, iclass 30, count 0 2006.183.07:38:20.00#ibcon#read 6, iclass 30, count 0 2006.183.07:38:20.00#ibcon#end of sib2, iclass 30, count 0 2006.183.07:38:20.00#ibcon#*after write, iclass 30, count 0 2006.183.07:38:20.00#ibcon#*before return 0, iclass 30, count 0 2006.183.07:38:20.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:20.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:20.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:38:20.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:38:20.00$vc4f8/va=7,6 2006.183.07:38:20.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.07:38:20.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.07:38:20.00#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:20.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:38:20.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:38:20.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:38:20.06#ibcon#enter wrdev, iclass 32, count 2 2006.183.07:38:20.06#ibcon#first serial, iclass 32, count 2 2006.183.07:38:20.06#ibcon#enter sib2, iclass 32, count 2 2006.183.07:38:20.06#ibcon#flushed, iclass 32, count 2 2006.183.07:38:20.06#ibcon#about to write, iclass 32, count 2 2006.183.07:38:20.06#ibcon#wrote, iclass 32, count 2 2006.183.07:38:20.06#ibcon#about to read 3, iclass 32, count 2 2006.183.07:38:20.08#ibcon#read 3, iclass 32, count 2 2006.183.07:38:20.08#ibcon#about to read 4, iclass 32, count 2 2006.183.07:38:20.08#ibcon#read 4, iclass 32, count 2 2006.183.07:38:20.08#ibcon#about to read 5, iclass 32, count 2 2006.183.07:38:20.08#ibcon#read 5, iclass 32, count 2 2006.183.07:38:20.08#ibcon#about to read 6, iclass 32, count 2 2006.183.07:38:20.08#ibcon#read 6, iclass 32, count 2 2006.183.07:38:20.08#ibcon#end of sib2, iclass 32, count 2 2006.183.07:38:20.08#ibcon#*mode == 0, iclass 32, count 2 2006.183.07:38:20.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.07:38:20.08#ibcon#[25=AT07-06\r\n] 2006.183.07:38:20.08#ibcon#*before write, iclass 32, count 2 2006.183.07:38:20.08#ibcon#enter sib2, iclass 32, count 2 2006.183.07:38:20.08#ibcon#flushed, iclass 32, count 2 2006.183.07:38:20.08#ibcon#about to write, iclass 32, count 2 2006.183.07:38:20.08#ibcon#wrote, iclass 32, count 2 2006.183.07:38:20.08#ibcon#about to read 3, iclass 32, count 2 2006.183.07:38:20.11#ibcon#read 3, iclass 32, count 2 2006.183.07:38:20.11#ibcon#about to read 4, iclass 32, count 2 2006.183.07:38:20.11#ibcon#read 4, iclass 32, count 2 2006.183.07:38:20.11#ibcon#about to read 5, iclass 32, count 2 2006.183.07:38:20.11#ibcon#read 5, iclass 32, count 2 2006.183.07:38:20.11#ibcon#about to read 6, iclass 32, count 2 2006.183.07:38:20.11#ibcon#read 6, iclass 32, count 2 2006.183.07:38:20.11#ibcon#end of sib2, iclass 32, count 2 2006.183.07:38:20.11#ibcon#*after write, iclass 32, count 2 2006.183.07:38:20.11#ibcon#*before return 0, iclass 32, count 2 2006.183.07:38:20.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:38:20.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:38:20.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.07:38:20.11#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:20.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:38:20.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:38:20.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:38:20.23#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:38:20.23#ibcon#first serial, iclass 32, count 0 2006.183.07:38:20.23#ibcon#enter sib2, iclass 32, count 0 2006.183.07:38:20.23#ibcon#flushed, iclass 32, count 0 2006.183.07:38:20.23#ibcon#about to write, iclass 32, count 0 2006.183.07:38:20.23#ibcon#wrote, iclass 32, count 0 2006.183.07:38:20.23#ibcon#about to read 3, iclass 32, count 0 2006.183.07:38:20.25#ibcon#read 3, iclass 32, count 0 2006.183.07:38:20.25#ibcon#about to read 4, iclass 32, count 0 2006.183.07:38:20.25#ibcon#read 4, iclass 32, count 0 2006.183.07:38:20.25#ibcon#about to read 5, iclass 32, count 0 2006.183.07:38:20.25#ibcon#read 5, iclass 32, count 0 2006.183.07:38:20.25#ibcon#about to read 6, iclass 32, count 0 2006.183.07:38:20.25#ibcon#read 6, iclass 32, count 0 2006.183.07:38:20.25#ibcon#end of sib2, iclass 32, count 0 2006.183.07:38:20.25#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:38:20.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:38:20.25#ibcon#[25=USB\r\n] 2006.183.07:38:20.25#ibcon#*before write, iclass 32, count 0 2006.183.07:38:20.25#ibcon#enter sib2, iclass 32, count 0 2006.183.07:38:20.25#ibcon#flushed, iclass 32, count 0 2006.183.07:38:20.25#ibcon#about to write, iclass 32, count 0 2006.183.07:38:20.25#ibcon#wrote, iclass 32, count 0 2006.183.07:38:20.25#ibcon#about to read 3, iclass 32, count 0 2006.183.07:38:20.28#ibcon#read 3, iclass 32, count 0 2006.183.07:38:20.28#ibcon#about to read 4, iclass 32, count 0 2006.183.07:38:20.28#ibcon#read 4, iclass 32, count 0 2006.183.07:38:20.28#ibcon#about to read 5, iclass 32, count 0 2006.183.07:38:20.28#ibcon#read 5, iclass 32, count 0 2006.183.07:38:20.28#ibcon#about to read 6, iclass 32, count 0 2006.183.07:38:20.28#ibcon#read 6, iclass 32, count 0 2006.183.07:38:20.28#ibcon#end of sib2, iclass 32, count 0 2006.183.07:38:20.28#ibcon#*after write, iclass 32, count 0 2006.183.07:38:20.28#ibcon#*before return 0, iclass 32, count 0 2006.183.07:38:20.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:38:20.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:38:20.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:38:20.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:38:20.28$vc4f8/valo=8,852.99 2006.183.07:38:20.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.07:38:20.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.07:38:20.28#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:20.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:38:20.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:38:20.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:38:20.28#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:38:20.28#ibcon#first serial, iclass 34, count 0 2006.183.07:38:20.28#ibcon#enter sib2, iclass 34, count 0 2006.183.07:38:20.28#ibcon#flushed, iclass 34, count 0 2006.183.07:38:20.28#ibcon#about to write, iclass 34, count 0 2006.183.07:38:20.28#ibcon#wrote, iclass 34, count 0 2006.183.07:38:20.28#ibcon#about to read 3, iclass 34, count 0 2006.183.07:38:20.30#ibcon#read 3, iclass 34, count 0 2006.183.07:38:20.30#ibcon#about to read 4, iclass 34, count 0 2006.183.07:38:20.30#ibcon#read 4, iclass 34, count 0 2006.183.07:38:20.30#ibcon#about to read 5, iclass 34, count 0 2006.183.07:38:20.30#ibcon#read 5, iclass 34, count 0 2006.183.07:38:20.30#ibcon#about to read 6, iclass 34, count 0 2006.183.07:38:20.30#ibcon#read 6, iclass 34, count 0 2006.183.07:38:20.30#ibcon#end of sib2, iclass 34, count 0 2006.183.07:38:20.30#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:38:20.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:38:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:38:20.30#ibcon#*before write, iclass 34, count 0 2006.183.07:38:20.30#ibcon#enter sib2, iclass 34, count 0 2006.183.07:38:20.30#ibcon#flushed, iclass 34, count 0 2006.183.07:38:20.30#ibcon#about to write, iclass 34, count 0 2006.183.07:38:20.30#ibcon#wrote, iclass 34, count 0 2006.183.07:38:20.30#ibcon#about to read 3, iclass 34, count 0 2006.183.07:38:20.34#ibcon#read 3, iclass 34, count 0 2006.183.07:38:20.34#ibcon#about to read 4, iclass 34, count 0 2006.183.07:38:20.34#ibcon#read 4, iclass 34, count 0 2006.183.07:38:20.34#ibcon#about to read 5, iclass 34, count 0 2006.183.07:38:20.34#ibcon#read 5, iclass 34, count 0 2006.183.07:38:20.34#ibcon#about to read 6, iclass 34, count 0 2006.183.07:38:20.34#ibcon#read 6, iclass 34, count 0 2006.183.07:38:20.34#ibcon#end of sib2, iclass 34, count 0 2006.183.07:38:20.34#ibcon#*after write, iclass 34, count 0 2006.183.07:38:20.34#ibcon#*before return 0, iclass 34, count 0 2006.183.07:38:20.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:38:20.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:38:20.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:38:20.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:38:20.34$vc4f8/va=8,7 2006.183.07:38:20.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.07:38:20.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.07:38:20.34#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:20.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:38:20.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:38:20.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:38:20.40#ibcon#enter wrdev, iclass 36, count 2 2006.183.07:38:20.40#ibcon#first serial, iclass 36, count 2 2006.183.07:38:20.40#ibcon#enter sib2, iclass 36, count 2 2006.183.07:38:20.40#ibcon#flushed, iclass 36, count 2 2006.183.07:38:20.40#ibcon#about to write, iclass 36, count 2 2006.183.07:38:20.40#ibcon#wrote, iclass 36, count 2 2006.183.07:38:20.40#ibcon#about to read 3, iclass 36, count 2 2006.183.07:38:20.42#ibcon#read 3, iclass 36, count 2 2006.183.07:38:20.42#ibcon#about to read 4, iclass 36, count 2 2006.183.07:38:20.42#ibcon#read 4, iclass 36, count 2 2006.183.07:38:20.42#ibcon#about to read 5, iclass 36, count 2 2006.183.07:38:20.42#ibcon#read 5, iclass 36, count 2 2006.183.07:38:20.42#ibcon#about to read 6, iclass 36, count 2 2006.183.07:38:20.42#ibcon#read 6, iclass 36, count 2 2006.183.07:38:20.42#ibcon#end of sib2, iclass 36, count 2 2006.183.07:38:20.42#ibcon#*mode == 0, iclass 36, count 2 2006.183.07:38:20.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.07:38:20.42#ibcon#[25=AT08-07\r\n] 2006.183.07:38:20.42#ibcon#*before write, iclass 36, count 2 2006.183.07:38:20.42#ibcon#enter sib2, iclass 36, count 2 2006.183.07:38:20.42#ibcon#flushed, iclass 36, count 2 2006.183.07:38:20.42#ibcon#about to write, iclass 36, count 2 2006.183.07:38:20.42#ibcon#wrote, iclass 36, count 2 2006.183.07:38:20.42#ibcon#about to read 3, iclass 36, count 2 2006.183.07:38:20.45#ibcon#read 3, iclass 36, count 2 2006.183.07:38:20.45#ibcon#about to read 4, iclass 36, count 2 2006.183.07:38:20.45#ibcon#read 4, iclass 36, count 2 2006.183.07:38:20.45#ibcon#about to read 5, iclass 36, count 2 2006.183.07:38:20.45#ibcon#read 5, iclass 36, count 2 2006.183.07:38:20.45#ibcon#about to read 6, iclass 36, count 2 2006.183.07:38:20.45#ibcon#read 6, iclass 36, count 2 2006.183.07:38:20.45#ibcon#end of sib2, iclass 36, count 2 2006.183.07:38:20.45#ibcon#*after write, iclass 36, count 2 2006.183.07:38:20.45#ibcon#*before return 0, iclass 36, count 2 2006.183.07:38:20.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:38:20.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:38:20.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.07:38:20.45#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:20.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:38:20.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:38:20.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:38:20.57#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:38:20.57#ibcon#first serial, iclass 36, count 0 2006.183.07:38:20.57#ibcon#enter sib2, iclass 36, count 0 2006.183.07:38:20.57#ibcon#flushed, iclass 36, count 0 2006.183.07:38:20.57#ibcon#about to write, iclass 36, count 0 2006.183.07:38:20.57#ibcon#wrote, iclass 36, count 0 2006.183.07:38:20.57#ibcon#about to read 3, iclass 36, count 0 2006.183.07:38:20.59#ibcon#read 3, iclass 36, count 0 2006.183.07:38:20.59#ibcon#about to read 4, iclass 36, count 0 2006.183.07:38:20.59#ibcon#read 4, iclass 36, count 0 2006.183.07:38:20.59#ibcon#about to read 5, iclass 36, count 0 2006.183.07:38:20.59#ibcon#read 5, iclass 36, count 0 2006.183.07:38:20.59#ibcon#about to read 6, iclass 36, count 0 2006.183.07:38:20.59#ibcon#read 6, iclass 36, count 0 2006.183.07:38:20.59#ibcon#end of sib2, iclass 36, count 0 2006.183.07:38:20.59#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:38:20.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:38:20.59#ibcon#[25=USB\r\n] 2006.183.07:38:20.59#ibcon#*before write, iclass 36, count 0 2006.183.07:38:20.59#ibcon#enter sib2, iclass 36, count 0 2006.183.07:38:20.59#ibcon#flushed, iclass 36, count 0 2006.183.07:38:20.59#ibcon#about to write, iclass 36, count 0 2006.183.07:38:20.59#ibcon#wrote, iclass 36, count 0 2006.183.07:38:20.59#ibcon#about to read 3, iclass 36, count 0 2006.183.07:38:20.62#ibcon#read 3, iclass 36, count 0 2006.183.07:38:20.62#ibcon#about to read 4, iclass 36, count 0 2006.183.07:38:20.62#ibcon#read 4, iclass 36, count 0 2006.183.07:38:20.62#ibcon#about to read 5, iclass 36, count 0 2006.183.07:38:20.62#ibcon#read 5, iclass 36, count 0 2006.183.07:38:20.62#ibcon#about to read 6, iclass 36, count 0 2006.183.07:38:20.62#ibcon#read 6, iclass 36, count 0 2006.183.07:38:20.62#ibcon#end of sib2, iclass 36, count 0 2006.183.07:38:20.62#ibcon#*after write, iclass 36, count 0 2006.183.07:38:20.62#ibcon#*before return 0, iclass 36, count 0 2006.183.07:38:20.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:38:20.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:38:20.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:38:20.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:38:20.62$vc4f8/vblo=1,632.99 2006.183.07:38:20.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.07:38:20.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.07:38:20.62#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:20.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:38:20.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:38:20.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:38:20.62#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:38:20.62#ibcon#first serial, iclass 38, count 0 2006.183.07:38:20.62#ibcon#enter sib2, iclass 38, count 0 2006.183.07:38:20.62#ibcon#flushed, iclass 38, count 0 2006.183.07:38:20.62#ibcon#about to write, iclass 38, count 0 2006.183.07:38:20.62#ibcon#wrote, iclass 38, count 0 2006.183.07:38:20.62#ibcon#about to read 3, iclass 38, count 0 2006.183.07:38:20.65#ibcon#read 3, iclass 38, count 0 2006.183.07:38:20.65#ibcon#about to read 4, iclass 38, count 0 2006.183.07:38:20.65#ibcon#read 4, iclass 38, count 0 2006.183.07:38:20.65#ibcon#about to read 5, iclass 38, count 0 2006.183.07:38:20.65#ibcon#read 5, iclass 38, count 0 2006.183.07:38:20.65#ibcon#about to read 6, iclass 38, count 0 2006.183.07:38:20.65#ibcon#read 6, iclass 38, count 0 2006.183.07:38:20.65#ibcon#end of sib2, iclass 38, count 0 2006.183.07:38:20.65#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:38:20.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:38:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:38:20.65#ibcon#*before write, iclass 38, count 0 2006.183.07:38:20.65#ibcon#enter sib2, iclass 38, count 0 2006.183.07:38:20.65#ibcon#flushed, iclass 38, count 0 2006.183.07:38:20.65#ibcon#about to write, iclass 38, count 0 2006.183.07:38:20.65#ibcon#wrote, iclass 38, count 0 2006.183.07:38:20.65#ibcon#about to read 3, iclass 38, count 0 2006.183.07:38:20.69#ibcon#read 3, iclass 38, count 0 2006.183.07:38:20.69#ibcon#about to read 4, iclass 38, count 0 2006.183.07:38:20.69#ibcon#read 4, iclass 38, count 0 2006.183.07:38:20.69#ibcon#about to read 5, iclass 38, count 0 2006.183.07:38:20.69#ibcon#read 5, iclass 38, count 0 2006.183.07:38:20.69#ibcon#about to read 6, iclass 38, count 0 2006.183.07:38:20.69#ibcon#read 6, iclass 38, count 0 2006.183.07:38:20.69#ibcon#end of sib2, iclass 38, count 0 2006.183.07:38:20.69#ibcon#*after write, iclass 38, count 0 2006.183.07:38:20.69#ibcon#*before return 0, iclass 38, count 0 2006.183.07:38:20.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:38:20.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:38:20.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:38:20.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:38:20.69$vc4f8/vb=1,4 2006.183.07:38:20.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.07:38:20.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.07:38:20.69#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:20.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:38:20.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:38:20.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:38:20.69#ibcon#enter wrdev, iclass 40, count 2 2006.183.07:38:20.69#ibcon#first serial, iclass 40, count 2 2006.183.07:38:20.69#ibcon#enter sib2, iclass 40, count 2 2006.183.07:38:20.69#ibcon#flushed, iclass 40, count 2 2006.183.07:38:20.69#ibcon#about to write, iclass 40, count 2 2006.183.07:38:20.69#ibcon#wrote, iclass 40, count 2 2006.183.07:38:20.69#ibcon#about to read 3, iclass 40, count 2 2006.183.07:38:20.71#ibcon#read 3, iclass 40, count 2 2006.183.07:38:20.71#ibcon#about to read 4, iclass 40, count 2 2006.183.07:38:20.71#ibcon#read 4, iclass 40, count 2 2006.183.07:38:20.71#ibcon#about to read 5, iclass 40, count 2 2006.183.07:38:20.71#ibcon#read 5, iclass 40, count 2 2006.183.07:38:20.71#ibcon#about to read 6, iclass 40, count 2 2006.183.07:38:20.71#ibcon#read 6, iclass 40, count 2 2006.183.07:38:20.71#ibcon#end of sib2, iclass 40, count 2 2006.183.07:38:20.71#ibcon#*mode == 0, iclass 40, count 2 2006.183.07:38:20.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.07:38:20.71#ibcon#[27=AT01-04\r\n] 2006.183.07:38:20.71#ibcon#*before write, iclass 40, count 2 2006.183.07:38:20.71#ibcon#enter sib2, iclass 40, count 2 2006.183.07:38:20.71#ibcon#flushed, iclass 40, count 2 2006.183.07:38:20.71#ibcon#about to write, iclass 40, count 2 2006.183.07:38:20.71#ibcon#wrote, iclass 40, count 2 2006.183.07:38:20.71#ibcon#about to read 3, iclass 40, count 2 2006.183.07:38:20.74#ibcon#read 3, iclass 40, count 2 2006.183.07:38:20.74#ibcon#about to read 4, iclass 40, count 2 2006.183.07:38:20.74#ibcon#read 4, iclass 40, count 2 2006.183.07:38:20.74#ibcon#about to read 5, iclass 40, count 2 2006.183.07:38:20.74#ibcon#read 5, iclass 40, count 2 2006.183.07:38:20.74#ibcon#about to read 6, iclass 40, count 2 2006.183.07:38:20.74#ibcon#read 6, iclass 40, count 2 2006.183.07:38:20.74#ibcon#end of sib2, iclass 40, count 2 2006.183.07:38:20.74#ibcon#*after write, iclass 40, count 2 2006.183.07:38:20.74#ibcon#*before return 0, iclass 40, count 2 2006.183.07:38:20.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:38:20.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:38:20.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.07:38:20.74#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:20.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:38:20.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:38:20.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:38:20.86#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:38:20.86#ibcon#first serial, iclass 40, count 0 2006.183.07:38:20.86#ibcon#enter sib2, iclass 40, count 0 2006.183.07:38:20.86#ibcon#flushed, iclass 40, count 0 2006.183.07:38:20.86#ibcon#about to write, iclass 40, count 0 2006.183.07:38:20.86#ibcon#wrote, iclass 40, count 0 2006.183.07:38:20.86#ibcon#about to read 3, iclass 40, count 0 2006.183.07:38:20.88#ibcon#read 3, iclass 40, count 0 2006.183.07:38:20.88#ibcon#about to read 4, iclass 40, count 0 2006.183.07:38:20.88#ibcon#read 4, iclass 40, count 0 2006.183.07:38:20.88#ibcon#about to read 5, iclass 40, count 0 2006.183.07:38:20.88#ibcon#read 5, iclass 40, count 0 2006.183.07:38:20.88#ibcon#about to read 6, iclass 40, count 0 2006.183.07:38:20.88#ibcon#read 6, iclass 40, count 0 2006.183.07:38:20.88#ibcon#end of sib2, iclass 40, count 0 2006.183.07:38:20.88#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:38:20.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:38:20.88#ibcon#[27=USB\r\n] 2006.183.07:38:20.88#ibcon#*before write, iclass 40, count 0 2006.183.07:38:20.88#ibcon#enter sib2, iclass 40, count 0 2006.183.07:38:20.88#ibcon#flushed, iclass 40, count 0 2006.183.07:38:20.88#ibcon#about to write, iclass 40, count 0 2006.183.07:38:20.88#ibcon#wrote, iclass 40, count 0 2006.183.07:38:20.88#ibcon#about to read 3, iclass 40, count 0 2006.183.07:38:20.91#ibcon#read 3, iclass 40, count 0 2006.183.07:38:20.91#ibcon#about to read 4, iclass 40, count 0 2006.183.07:38:20.91#ibcon#read 4, iclass 40, count 0 2006.183.07:38:20.91#ibcon#about to read 5, iclass 40, count 0 2006.183.07:38:20.91#ibcon#read 5, iclass 40, count 0 2006.183.07:38:20.91#ibcon#about to read 6, iclass 40, count 0 2006.183.07:38:20.91#ibcon#read 6, iclass 40, count 0 2006.183.07:38:20.91#ibcon#end of sib2, iclass 40, count 0 2006.183.07:38:20.91#ibcon#*after write, iclass 40, count 0 2006.183.07:38:20.91#ibcon#*before return 0, iclass 40, count 0 2006.183.07:38:20.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:38:20.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:38:20.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:38:20.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:38:20.91$vc4f8/vblo=2,640.99 2006.183.07:38:20.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.07:38:20.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.07:38:20.91#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:20.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:20.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:20.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:20.91#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:38:20.91#ibcon#first serial, iclass 4, count 0 2006.183.07:38:20.91#ibcon#enter sib2, iclass 4, count 0 2006.183.07:38:20.91#ibcon#flushed, iclass 4, count 0 2006.183.07:38:20.91#ibcon#about to write, iclass 4, count 0 2006.183.07:38:20.91#ibcon#wrote, iclass 4, count 0 2006.183.07:38:20.91#ibcon#about to read 3, iclass 4, count 0 2006.183.07:38:20.93#ibcon#read 3, iclass 4, count 0 2006.183.07:38:20.93#ibcon#about to read 4, iclass 4, count 0 2006.183.07:38:20.93#ibcon#read 4, iclass 4, count 0 2006.183.07:38:20.93#ibcon#about to read 5, iclass 4, count 0 2006.183.07:38:20.93#ibcon#read 5, iclass 4, count 0 2006.183.07:38:20.93#ibcon#about to read 6, iclass 4, count 0 2006.183.07:38:20.93#ibcon#read 6, iclass 4, count 0 2006.183.07:38:20.93#ibcon#end of sib2, iclass 4, count 0 2006.183.07:38:20.93#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:38:20.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:38:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:38:20.93#ibcon#*before write, iclass 4, count 0 2006.183.07:38:20.93#ibcon#enter sib2, iclass 4, count 0 2006.183.07:38:20.93#ibcon#flushed, iclass 4, count 0 2006.183.07:38:20.93#ibcon#about to write, iclass 4, count 0 2006.183.07:38:20.93#ibcon#wrote, iclass 4, count 0 2006.183.07:38:20.93#ibcon#about to read 3, iclass 4, count 0 2006.183.07:38:20.97#ibcon#read 3, iclass 4, count 0 2006.183.07:38:20.97#ibcon#about to read 4, iclass 4, count 0 2006.183.07:38:20.97#ibcon#read 4, iclass 4, count 0 2006.183.07:38:20.97#ibcon#about to read 5, iclass 4, count 0 2006.183.07:38:20.97#ibcon#read 5, iclass 4, count 0 2006.183.07:38:20.97#ibcon#about to read 6, iclass 4, count 0 2006.183.07:38:20.97#ibcon#read 6, iclass 4, count 0 2006.183.07:38:20.97#ibcon#end of sib2, iclass 4, count 0 2006.183.07:38:20.97#ibcon#*after write, iclass 4, count 0 2006.183.07:38:20.97#ibcon#*before return 0, iclass 4, count 0 2006.183.07:38:20.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:20.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:38:20.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:38:20.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:38:20.97$vc4f8/vb=2,4 2006.183.07:38:20.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.07:38:20.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.07:38:20.97#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:20.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:21.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:21.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:21.03#ibcon#enter wrdev, iclass 6, count 2 2006.183.07:38:21.03#ibcon#first serial, iclass 6, count 2 2006.183.07:38:21.03#ibcon#enter sib2, iclass 6, count 2 2006.183.07:38:21.03#ibcon#flushed, iclass 6, count 2 2006.183.07:38:21.03#ibcon#about to write, iclass 6, count 2 2006.183.07:38:21.03#ibcon#wrote, iclass 6, count 2 2006.183.07:38:21.03#ibcon#about to read 3, iclass 6, count 2 2006.183.07:38:21.05#ibcon#read 3, iclass 6, count 2 2006.183.07:38:21.05#ibcon#about to read 4, iclass 6, count 2 2006.183.07:38:21.05#ibcon#read 4, iclass 6, count 2 2006.183.07:38:21.05#ibcon#about to read 5, iclass 6, count 2 2006.183.07:38:21.05#ibcon#read 5, iclass 6, count 2 2006.183.07:38:21.05#ibcon#about to read 6, iclass 6, count 2 2006.183.07:38:21.05#ibcon#read 6, iclass 6, count 2 2006.183.07:38:21.05#ibcon#end of sib2, iclass 6, count 2 2006.183.07:38:21.05#ibcon#*mode == 0, iclass 6, count 2 2006.183.07:38:21.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.07:38:21.05#ibcon#[27=AT02-04\r\n] 2006.183.07:38:21.05#ibcon#*before write, iclass 6, count 2 2006.183.07:38:21.05#ibcon#enter sib2, iclass 6, count 2 2006.183.07:38:21.05#ibcon#flushed, iclass 6, count 2 2006.183.07:38:21.05#ibcon#about to write, iclass 6, count 2 2006.183.07:38:21.05#ibcon#wrote, iclass 6, count 2 2006.183.07:38:21.05#ibcon#about to read 3, iclass 6, count 2 2006.183.07:38:21.08#ibcon#read 3, iclass 6, count 2 2006.183.07:38:21.08#ibcon#about to read 4, iclass 6, count 2 2006.183.07:38:21.08#ibcon#read 4, iclass 6, count 2 2006.183.07:38:21.08#ibcon#about to read 5, iclass 6, count 2 2006.183.07:38:21.08#ibcon#read 5, iclass 6, count 2 2006.183.07:38:21.08#ibcon#about to read 6, iclass 6, count 2 2006.183.07:38:21.08#ibcon#read 6, iclass 6, count 2 2006.183.07:38:21.08#ibcon#end of sib2, iclass 6, count 2 2006.183.07:38:21.08#ibcon#*after write, iclass 6, count 2 2006.183.07:38:21.08#ibcon#*before return 0, iclass 6, count 2 2006.183.07:38:21.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:21.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:38:21.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.07:38:21.08#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:21.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:21.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:21.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:21.20#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:38:21.20#ibcon#first serial, iclass 6, count 0 2006.183.07:38:21.20#ibcon#enter sib2, iclass 6, count 0 2006.183.07:38:21.20#ibcon#flushed, iclass 6, count 0 2006.183.07:38:21.20#ibcon#about to write, iclass 6, count 0 2006.183.07:38:21.20#ibcon#wrote, iclass 6, count 0 2006.183.07:38:21.20#ibcon#about to read 3, iclass 6, count 0 2006.183.07:38:21.22#ibcon#read 3, iclass 6, count 0 2006.183.07:38:21.22#ibcon#about to read 4, iclass 6, count 0 2006.183.07:38:21.22#ibcon#read 4, iclass 6, count 0 2006.183.07:38:21.22#ibcon#about to read 5, iclass 6, count 0 2006.183.07:38:21.22#ibcon#read 5, iclass 6, count 0 2006.183.07:38:21.22#ibcon#about to read 6, iclass 6, count 0 2006.183.07:38:21.22#ibcon#read 6, iclass 6, count 0 2006.183.07:38:21.22#ibcon#end of sib2, iclass 6, count 0 2006.183.07:38:21.22#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:38:21.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:38:21.22#ibcon#[27=USB\r\n] 2006.183.07:38:21.22#ibcon#*before write, iclass 6, count 0 2006.183.07:38:21.22#ibcon#enter sib2, iclass 6, count 0 2006.183.07:38:21.22#ibcon#flushed, iclass 6, count 0 2006.183.07:38:21.22#ibcon#about to write, iclass 6, count 0 2006.183.07:38:21.22#ibcon#wrote, iclass 6, count 0 2006.183.07:38:21.22#ibcon#about to read 3, iclass 6, count 0 2006.183.07:38:21.25#ibcon#read 3, iclass 6, count 0 2006.183.07:38:21.25#ibcon#about to read 4, iclass 6, count 0 2006.183.07:38:21.25#ibcon#read 4, iclass 6, count 0 2006.183.07:38:21.25#ibcon#about to read 5, iclass 6, count 0 2006.183.07:38:21.25#ibcon#read 5, iclass 6, count 0 2006.183.07:38:21.25#ibcon#about to read 6, iclass 6, count 0 2006.183.07:38:21.25#ibcon#read 6, iclass 6, count 0 2006.183.07:38:21.25#ibcon#end of sib2, iclass 6, count 0 2006.183.07:38:21.25#ibcon#*after write, iclass 6, count 0 2006.183.07:38:21.25#ibcon#*before return 0, iclass 6, count 0 2006.183.07:38:21.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:21.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:38:21.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:38:21.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:38:21.25$vc4f8/vblo=3,656.99 2006.183.07:38:21.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.07:38:21.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.07:38:21.25#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:21.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:21.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:21.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:21.25#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:38:21.25#ibcon#first serial, iclass 10, count 0 2006.183.07:38:21.25#ibcon#enter sib2, iclass 10, count 0 2006.183.07:38:21.25#ibcon#flushed, iclass 10, count 0 2006.183.07:38:21.25#ibcon#about to write, iclass 10, count 0 2006.183.07:38:21.25#ibcon#wrote, iclass 10, count 0 2006.183.07:38:21.25#ibcon#about to read 3, iclass 10, count 0 2006.183.07:38:21.27#ibcon#read 3, iclass 10, count 0 2006.183.07:38:21.27#ibcon#about to read 4, iclass 10, count 0 2006.183.07:38:21.27#ibcon#read 4, iclass 10, count 0 2006.183.07:38:21.27#ibcon#about to read 5, iclass 10, count 0 2006.183.07:38:21.27#ibcon#read 5, iclass 10, count 0 2006.183.07:38:21.27#ibcon#about to read 6, iclass 10, count 0 2006.183.07:38:21.27#ibcon#read 6, iclass 10, count 0 2006.183.07:38:21.27#ibcon#end of sib2, iclass 10, count 0 2006.183.07:38:21.27#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:38:21.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:38:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:38:21.27#ibcon#*before write, iclass 10, count 0 2006.183.07:38:21.27#ibcon#enter sib2, iclass 10, count 0 2006.183.07:38:21.27#ibcon#flushed, iclass 10, count 0 2006.183.07:38:21.27#ibcon#about to write, iclass 10, count 0 2006.183.07:38:21.27#ibcon#wrote, iclass 10, count 0 2006.183.07:38:21.27#ibcon#about to read 3, iclass 10, count 0 2006.183.07:38:21.31#ibcon#read 3, iclass 10, count 0 2006.183.07:38:21.31#ibcon#about to read 4, iclass 10, count 0 2006.183.07:38:21.31#ibcon#read 4, iclass 10, count 0 2006.183.07:38:21.31#ibcon#about to read 5, iclass 10, count 0 2006.183.07:38:21.31#ibcon#read 5, iclass 10, count 0 2006.183.07:38:21.31#ibcon#about to read 6, iclass 10, count 0 2006.183.07:38:21.31#ibcon#read 6, iclass 10, count 0 2006.183.07:38:21.31#ibcon#end of sib2, iclass 10, count 0 2006.183.07:38:21.31#ibcon#*after write, iclass 10, count 0 2006.183.07:38:21.31#ibcon#*before return 0, iclass 10, count 0 2006.183.07:38:21.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:21.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:38:21.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:38:21.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:38:21.31$vc4f8/vb=3,4 2006.183.07:38:21.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.07:38:21.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.07:38:21.31#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:21.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:21.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:21.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:21.37#ibcon#enter wrdev, iclass 12, count 2 2006.183.07:38:21.37#ibcon#first serial, iclass 12, count 2 2006.183.07:38:21.37#ibcon#enter sib2, iclass 12, count 2 2006.183.07:38:21.37#ibcon#flushed, iclass 12, count 2 2006.183.07:38:21.37#ibcon#about to write, iclass 12, count 2 2006.183.07:38:21.37#ibcon#wrote, iclass 12, count 2 2006.183.07:38:21.37#ibcon#about to read 3, iclass 12, count 2 2006.183.07:38:21.39#ibcon#read 3, iclass 12, count 2 2006.183.07:38:21.39#ibcon#about to read 4, iclass 12, count 2 2006.183.07:38:21.39#ibcon#read 4, iclass 12, count 2 2006.183.07:38:21.39#ibcon#about to read 5, iclass 12, count 2 2006.183.07:38:21.39#ibcon#read 5, iclass 12, count 2 2006.183.07:38:21.39#ibcon#about to read 6, iclass 12, count 2 2006.183.07:38:21.39#ibcon#read 6, iclass 12, count 2 2006.183.07:38:21.39#ibcon#end of sib2, iclass 12, count 2 2006.183.07:38:21.39#ibcon#*mode == 0, iclass 12, count 2 2006.183.07:38:21.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.07:38:21.39#ibcon#[27=AT03-04\r\n] 2006.183.07:38:21.39#ibcon#*before write, iclass 12, count 2 2006.183.07:38:21.39#ibcon#enter sib2, iclass 12, count 2 2006.183.07:38:21.39#ibcon#flushed, iclass 12, count 2 2006.183.07:38:21.39#ibcon#about to write, iclass 12, count 2 2006.183.07:38:21.39#ibcon#wrote, iclass 12, count 2 2006.183.07:38:21.39#ibcon#about to read 3, iclass 12, count 2 2006.183.07:38:21.42#ibcon#read 3, iclass 12, count 2 2006.183.07:38:21.42#ibcon#about to read 4, iclass 12, count 2 2006.183.07:38:21.42#ibcon#read 4, iclass 12, count 2 2006.183.07:38:21.42#ibcon#about to read 5, iclass 12, count 2 2006.183.07:38:21.42#ibcon#read 5, iclass 12, count 2 2006.183.07:38:21.42#ibcon#about to read 6, iclass 12, count 2 2006.183.07:38:21.42#ibcon#read 6, iclass 12, count 2 2006.183.07:38:21.42#ibcon#end of sib2, iclass 12, count 2 2006.183.07:38:21.42#ibcon#*after write, iclass 12, count 2 2006.183.07:38:21.42#ibcon#*before return 0, iclass 12, count 2 2006.183.07:38:21.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:21.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:38:21.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.07:38:21.42#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:21.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:21.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:21.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:21.54#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:38:21.54#ibcon#first serial, iclass 12, count 0 2006.183.07:38:21.54#ibcon#enter sib2, iclass 12, count 0 2006.183.07:38:21.54#ibcon#flushed, iclass 12, count 0 2006.183.07:38:21.54#ibcon#about to write, iclass 12, count 0 2006.183.07:38:21.54#ibcon#wrote, iclass 12, count 0 2006.183.07:38:21.54#ibcon#about to read 3, iclass 12, count 0 2006.183.07:38:21.56#ibcon#read 3, iclass 12, count 0 2006.183.07:38:21.56#ibcon#about to read 4, iclass 12, count 0 2006.183.07:38:21.56#ibcon#read 4, iclass 12, count 0 2006.183.07:38:21.56#ibcon#about to read 5, iclass 12, count 0 2006.183.07:38:21.56#ibcon#read 5, iclass 12, count 0 2006.183.07:38:21.56#ibcon#about to read 6, iclass 12, count 0 2006.183.07:38:21.56#ibcon#read 6, iclass 12, count 0 2006.183.07:38:21.56#ibcon#end of sib2, iclass 12, count 0 2006.183.07:38:21.56#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:38:21.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:38:21.56#ibcon#[27=USB\r\n] 2006.183.07:38:21.56#ibcon#*before write, iclass 12, count 0 2006.183.07:38:21.56#ibcon#enter sib2, iclass 12, count 0 2006.183.07:38:21.56#ibcon#flushed, iclass 12, count 0 2006.183.07:38:21.56#ibcon#about to write, iclass 12, count 0 2006.183.07:38:21.56#ibcon#wrote, iclass 12, count 0 2006.183.07:38:21.56#ibcon#about to read 3, iclass 12, count 0 2006.183.07:38:21.59#ibcon#read 3, iclass 12, count 0 2006.183.07:38:21.59#ibcon#about to read 4, iclass 12, count 0 2006.183.07:38:21.59#ibcon#read 4, iclass 12, count 0 2006.183.07:38:21.59#ibcon#about to read 5, iclass 12, count 0 2006.183.07:38:21.59#ibcon#read 5, iclass 12, count 0 2006.183.07:38:21.59#ibcon#about to read 6, iclass 12, count 0 2006.183.07:38:21.59#ibcon#read 6, iclass 12, count 0 2006.183.07:38:21.59#ibcon#end of sib2, iclass 12, count 0 2006.183.07:38:21.59#ibcon#*after write, iclass 12, count 0 2006.183.07:38:21.59#ibcon#*before return 0, iclass 12, count 0 2006.183.07:38:21.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:21.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:38:21.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:38:21.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:38:21.59$vc4f8/vblo=4,712.99 2006.183.07:38:21.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.07:38:21.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.07:38:21.59#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:21.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:21.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:21.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:21.59#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:38:21.59#ibcon#first serial, iclass 14, count 0 2006.183.07:38:21.59#ibcon#enter sib2, iclass 14, count 0 2006.183.07:38:21.59#ibcon#flushed, iclass 14, count 0 2006.183.07:38:21.59#ibcon#about to write, iclass 14, count 0 2006.183.07:38:21.59#ibcon#wrote, iclass 14, count 0 2006.183.07:38:21.59#ibcon#about to read 3, iclass 14, count 0 2006.183.07:38:21.61#ibcon#read 3, iclass 14, count 0 2006.183.07:38:21.61#ibcon#about to read 4, iclass 14, count 0 2006.183.07:38:21.61#ibcon#read 4, iclass 14, count 0 2006.183.07:38:21.61#ibcon#about to read 5, iclass 14, count 0 2006.183.07:38:21.61#ibcon#read 5, iclass 14, count 0 2006.183.07:38:21.61#ibcon#about to read 6, iclass 14, count 0 2006.183.07:38:21.61#ibcon#read 6, iclass 14, count 0 2006.183.07:38:21.61#ibcon#end of sib2, iclass 14, count 0 2006.183.07:38:21.61#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:38:21.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:38:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:38:21.61#ibcon#*before write, iclass 14, count 0 2006.183.07:38:21.61#ibcon#enter sib2, iclass 14, count 0 2006.183.07:38:21.61#ibcon#flushed, iclass 14, count 0 2006.183.07:38:21.61#ibcon#about to write, iclass 14, count 0 2006.183.07:38:21.61#ibcon#wrote, iclass 14, count 0 2006.183.07:38:21.61#ibcon#about to read 3, iclass 14, count 0 2006.183.07:38:21.65#ibcon#read 3, iclass 14, count 0 2006.183.07:38:21.65#ibcon#about to read 4, iclass 14, count 0 2006.183.07:38:21.65#ibcon#read 4, iclass 14, count 0 2006.183.07:38:21.65#ibcon#about to read 5, iclass 14, count 0 2006.183.07:38:21.65#ibcon#read 5, iclass 14, count 0 2006.183.07:38:21.65#ibcon#about to read 6, iclass 14, count 0 2006.183.07:38:21.65#ibcon#read 6, iclass 14, count 0 2006.183.07:38:21.65#ibcon#end of sib2, iclass 14, count 0 2006.183.07:38:21.65#ibcon#*after write, iclass 14, count 0 2006.183.07:38:21.65#ibcon#*before return 0, iclass 14, count 0 2006.183.07:38:21.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:21.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:38:21.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:38:21.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:38:21.65$vc4f8/vb=4,4 2006.183.07:38:21.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.07:38:21.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.07:38:21.65#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:21.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:21.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:21.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:21.71#ibcon#enter wrdev, iclass 16, count 2 2006.183.07:38:21.71#ibcon#first serial, iclass 16, count 2 2006.183.07:38:21.71#ibcon#enter sib2, iclass 16, count 2 2006.183.07:38:21.71#ibcon#flushed, iclass 16, count 2 2006.183.07:38:21.71#ibcon#about to write, iclass 16, count 2 2006.183.07:38:21.71#ibcon#wrote, iclass 16, count 2 2006.183.07:38:21.71#ibcon#about to read 3, iclass 16, count 2 2006.183.07:38:21.73#ibcon#read 3, iclass 16, count 2 2006.183.07:38:21.73#ibcon#about to read 4, iclass 16, count 2 2006.183.07:38:21.73#ibcon#read 4, iclass 16, count 2 2006.183.07:38:21.73#ibcon#about to read 5, iclass 16, count 2 2006.183.07:38:21.73#ibcon#read 5, iclass 16, count 2 2006.183.07:38:21.73#ibcon#about to read 6, iclass 16, count 2 2006.183.07:38:21.73#ibcon#read 6, iclass 16, count 2 2006.183.07:38:21.73#ibcon#end of sib2, iclass 16, count 2 2006.183.07:38:21.73#ibcon#*mode == 0, iclass 16, count 2 2006.183.07:38:21.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.07:38:21.73#ibcon#[27=AT04-04\r\n] 2006.183.07:38:21.73#ibcon#*before write, iclass 16, count 2 2006.183.07:38:21.73#ibcon#enter sib2, iclass 16, count 2 2006.183.07:38:21.73#ibcon#flushed, iclass 16, count 2 2006.183.07:38:21.73#ibcon#about to write, iclass 16, count 2 2006.183.07:38:21.73#ibcon#wrote, iclass 16, count 2 2006.183.07:38:21.73#ibcon#about to read 3, iclass 16, count 2 2006.183.07:38:21.76#ibcon#read 3, iclass 16, count 2 2006.183.07:38:21.76#ibcon#about to read 4, iclass 16, count 2 2006.183.07:38:21.76#ibcon#read 4, iclass 16, count 2 2006.183.07:38:21.76#ibcon#about to read 5, iclass 16, count 2 2006.183.07:38:21.76#ibcon#read 5, iclass 16, count 2 2006.183.07:38:21.76#ibcon#about to read 6, iclass 16, count 2 2006.183.07:38:21.76#ibcon#read 6, iclass 16, count 2 2006.183.07:38:21.76#ibcon#end of sib2, iclass 16, count 2 2006.183.07:38:21.76#ibcon#*after write, iclass 16, count 2 2006.183.07:38:21.76#ibcon#*before return 0, iclass 16, count 2 2006.183.07:38:21.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:21.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:38:21.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.07:38:21.76#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:21.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:21.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:21.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:21.88#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:38:21.88#ibcon#first serial, iclass 16, count 0 2006.183.07:38:21.88#ibcon#enter sib2, iclass 16, count 0 2006.183.07:38:21.88#ibcon#flushed, iclass 16, count 0 2006.183.07:38:21.88#ibcon#about to write, iclass 16, count 0 2006.183.07:38:21.88#ibcon#wrote, iclass 16, count 0 2006.183.07:38:21.88#ibcon#about to read 3, iclass 16, count 0 2006.183.07:38:21.90#ibcon#read 3, iclass 16, count 0 2006.183.07:38:21.90#ibcon#about to read 4, iclass 16, count 0 2006.183.07:38:21.90#ibcon#read 4, iclass 16, count 0 2006.183.07:38:21.90#ibcon#about to read 5, iclass 16, count 0 2006.183.07:38:21.90#ibcon#read 5, iclass 16, count 0 2006.183.07:38:21.90#ibcon#about to read 6, iclass 16, count 0 2006.183.07:38:21.90#ibcon#read 6, iclass 16, count 0 2006.183.07:38:21.90#ibcon#end of sib2, iclass 16, count 0 2006.183.07:38:21.90#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:38:21.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:38:21.90#ibcon#[27=USB\r\n] 2006.183.07:38:21.90#ibcon#*before write, iclass 16, count 0 2006.183.07:38:21.90#ibcon#enter sib2, iclass 16, count 0 2006.183.07:38:21.90#ibcon#flushed, iclass 16, count 0 2006.183.07:38:21.90#ibcon#about to write, iclass 16, count 0 2006.183.07:38:21.90#ibcon#wrote, iclass 16, count 0 2006.183.07:38:21.90#ibcon#about to read 3, iclass 16, count 0 2006.183.07:38:21.93#ibcon#read 3, iclass 16, count 0 2006.183.07:38:21.93#ibcon#about to read 4, iclass 16, count 0 2006.183.07:38:21.93#ibcon#read 4, iclass 16, count 0 2006.183.07:38:21.93#ibcon#about to read 5, iclass 16, count 0 2006.183.07:38:21.93#ibcon#read 5, iclass 16, count 0 2006.183.07:38:21.93#ibcon#about to read 6, iclass 16, count 0 2006.183.07:38:21.93#ibcon#read 6, iclass 16, count 0 2006.183.07:38:21.93#ibcon#end of sib2, iclass 16, count 0 2006.183.07:38:21.93#ibcon#*after write, iclass 16, count 0 2006.183.07:38:21.93#ibcon#*before return 0, iclass 16, count 0 2006.183.07:38:21.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:21.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:38:21.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:38:21.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:38:21.93$vc4f8/vblo=5,744.99 2006.183.07:38:21.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.07:38:21.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.07:38:21.93#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:21.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:21.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:21.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:21.93#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:38:21.93#ibcon#first serial, iclass 18, count 0 2006.183.07:38:21.93#ibcon#enter sib2, iclass 18, count 0 2006.183.07:38:21.93#ibcon#flushed, iclass 18, count 0 2006.183.07:38:21.93#ibcon#about to write, iclass 18, count 0 2006.183.07:38:21.93#ibcon#wrote, iclass 18, count 0 2006.183.07:38:21.93#ibcon#about to read 3, iclass 18, count 0 2006.183.07:38:21.95#ibcon#read 3, iclass 18, count 0 2006.183.07:38:21.95#ibcon#about to read 4, iclass 18, count 0 2006.183.07:38:21.95#ibcon#read 4, iclass 18, count 0 2006.183.07:38:21.95#ibcon#about to read 5, iclass 18, count 0 2006.183.07:38:21.95#ibcon#read 5, iclass 18, count 0 2006.183.07:38:21.95#ibcon#about to read 6, iclass 18, count 0 2006.183.07:38:21.95#ibcon#read 6, iclass 18, count 0 2006.183.07:38:21.95#ibcon#end of sib2, iclass 18, count 0 2006.183.07:38:21.95#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:38:21.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:38:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:38:21.95#ibcon#*before write, iclass 18, count 0 2006.183.07:38:21.95#ibcon#enter sib2, iclass 18, count 0 2006.183.07:38:21.95#ibcon#flushed, iclass 18, count 0 2006.183.07:38:21.95#ibcon#about to write, iclass 18, count 0 2006.183.07:38:21.95#ibcon#wrote, iclass 18, count 0 2006.183.07:38:21.95#ibcon#about to read 3, iclass 18, count 0 2006.183.07:38:21.99#ibcon#read 3, iclass 18, count 0 2006.183.07:38:21.99#ibcon#about to read 4, iclass 18, count 0 2006.183.07:38:21.99#ibcon#read 4, iclass 18, count 0 2006.183.07:38:21.99#ibcon#about to read 5, iclass 18, count 0 2006.183.07:38:21.99#ibcon#read 5, iclass 18, count 0 2006.183.07:38:21.99#ibcon#about to read 6, iclass 18, count 0 2006.183.07:38:21.99#ibcon#read 6, iclass 18, count 0 2006.183.07:38:21.99#ibcon#end of sib2, iclass 18, count 0 2006.183.07:38:21.99#ibcon#*after write, iclass 18, count 0 2006.183.07:38:21.99#ibcon#*before return 0, iclass 18, count 0 2006.183.07:38:21.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:21.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:38:21.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:38:21.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:38:21.99$vc4f8/vb=5,4 2006.183.07:38:21.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.07:38:21.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.07:38:21.99#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:21.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:22.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:22.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:22.05#ibcon#enter wrdev, iclass 20, count 2 2006.183.07:38:22.05#ibcon#first serial, iclass 20, count 2 2006.183.07:38:22.05#ibcon#enter sib2, iclass 20, count 2 2006.183.07:38:22.05#ibcon#flushed, iclass 20, count 2 2006.183.07:38:22.05#ibcon#about to write, iclass 20, count 2 2006.183.07:38:22.05#ibcon#wrote, iclass 20, count 2 2006.183.07:38:22.05#ibcon#about to read 3, iclass 20, count 2 2006.183.07:38:22.07#ibcon#read 3, iclass 20, count 2 2006.183.07:38:22.07#ibcon#about to read 4, iclass 20, count 2 2006.183.07:38:22.07#ibcon#read 4, iclass 20, count 2 2006.183.07:38:22.07#ibcon#about to read 5, iclass 20, count 2 2006.183.07:38:22.07#ibcon#read 5, iclass 20, count 2 2006.183.07:38:22.07#ibcon#about to read 6, iclass 20, count 2 2006.183.07:38:22.07#ibcon#read 6, iclass 20, count 2 2006.183.07:38:22.07#ibcon#end of sib2, iclass 20, count 2 2006.183.07:38:22.07#ibcon#*mode == 0, iclass 20, count 2 2006.183.07:38:22.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.07:38:22.07#ibcon#[27=AT05-04\r\n] 2006.183.07:38:22.07#ibcon#*before write, iclass 20, count 2 2006.183.07:38:22.07#ibcon#enter sib2, iclass 20, count 2 2006.183.07:38:22.07#ibcon#flushed, iclass 20, count 2 2006.183.07:38:22.07#ibcon#about to write, iclass 20, count 2 2006.183.07:38:22.07#ibcon#wrote, iclass 20, count 2 2006.183.07:38:22.07#ibcon#about to read 3, iclass 20, count 2 2006.183.07:38:22.10#ibcon#read 3, iclass 20, count 2 2006.183.07:38:22.10#ibcon#about to read 4, iclass 20, count 2 2006.183.07:38:22.10#ibcon#read 4, iclass 20, count 2 2006.183.07:38:22.10#ibcon#about to read 5, iclass 20, count 2 2006.183.07:38:22.10#ibcon#read 5, iclass 20, count 2 2006.183.07:38:22.10#ibcon#about to read 6, iclass 20, count 2 2006.183.07:38:22.10#ibcon#read 6, iclass 20, count 2 2006.183.07:38:22.10#ibcon#end of sib2, iclass 20, count 2 2006.183.07:38:22.10#ibcon#*after write, iclass 20, count 2 2006.183.07:38:22.10#ibcon#*before return 0, iclass 20, count 2 2006.183.07:38:22.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:22.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:38:22.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.07:38:22.10#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:22.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:22.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:22.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:22.22#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:38:22.22#ibcon#first serial, iclass 20, count 0 2006.183.07:38:22.22#ibcon#enter sib2, iclass 20, count 0 2006.183.07:38:22.22#ibcon#flushed, iclass 20, count 0 2006.183.07:38:22.22#ibcon#about to write, iclass 20, count 0 2006.183.07:38:22.22#ibcon#wrote, iclass 20, count 0 2006.183.07:38:22.22#ibcon#about to read 3, iclass 20, count 0 2006.183.07:38:22.26#ibcon#read 3, iclass 20, count 0 2006.183.07:38:22.26#ibcon#about to read 4, iclass 20, count 0 2006.183.07:38:22.26#ibcon#read 4, iclass 20, count 0 2006.183.07:38:22.26#ibcon#about to read 5, iclass 20, count 0 2006.183.07:38:22.26#ibcon#read 5, iclass 20, count 0 2006.183.07:38:22.26#ibcon#about to read 6, iclass 20, count 0 2006.183.07:38:22.26#ibcon#read 6, iclass 20, count 0 2006.183.07:38:22.26#ibcon#end of sib2, iclass 20, count 0 2006.183.07:38:22.26#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:38:22.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:38:22.26#ibcon#[27=USB\r\n] 2006.183.07:38:22.26#ibcon#*before write, iclass 20, count 0 2006.183.07:38:22.26#ibcon#enter sib2, iclass 20, count 0 2006.183.07:38:22.26#ibcon#flushed, iclass 20, count 0 2006.183.07:38:22.26#ibcon#about to write, iclass 20, count 0 2006.183.07:38:22.26#ibcon#wrote, iclass 20, count 0 2006.183.07:38:22.26#ibcon#about to read 3, iclass 20, count 0 2006.183.07:38:22.26#abcon#<5=/10 2.9 7.6 27.91 88 996.3\r\n> 2006.183.07:38:22.27#abcon#{5=INTERFACE CLEAR} 2006.183.07:38:22.28#ibcon#read 3, iclass 20, count 0 2006.183.07:38:22.28#ibcon#about to read 4, iclass 20, count 0 2006.183.07:38:22.28#ibcon#read 4, iclass 20, count 0 2006.183.07:38:22.28#ibcon#about to read 5, iclass 20, count 0 2006.183.07:38:22.28#ibcon#read 5, iclass 20, count 0 2006.183.07:38:22.28#ibcon#about to read 6, iclass 20, count 0 2006.183.07:38:22.28#ibcon#read 6, iclass 20, count 0 2006.183.07:38:22.28#ibcon#end of sib2, iclass 20, count 0 2006.183.07:38:22.28#ibcon#*after write, iclass 20, count 0 2006.183.07:38:22.28#ibcon#*before return 0, iclass 20, count 0 2006.183.07:38:22.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:22.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:38:22.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:38:22.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:38:22.28$vc4f8/vblo=6,752.99 2006.183.07:38:22.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:38:22.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:38:22.28#ibcon#ireg 17 cls_cnt 0 2006.183.07:38:22.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:38:22.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:38:22.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:38:22.28#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:38:22.28#ibcon#first serial, iclass 25, count 0 2006.183.07:38:22.28#ibcon#enter sib2, iclass 25, count 0 2006.183.07:38:22.28#ibcon#flushed, iclass 25, count 0 2006.183.07:38:22.28#ibcon#about to write, iclass 25, count 0 2006.183.07:38:22.28#ibcon#wrote, iclass 25, count 0 2006.183.07:38:22.28#ibcon#about to read 3, iclass 25, count 0 2006.183.07:38:22.30#ibcon#read 3, iclass 25, count 0 2006.183.07:38:22.30#ibcon#about to read 4, iclass 25, count 0 2006.183.07:38:22.30#ibcon#read 4, iclass 25, count 0 2006.183.07:38:22.30#ibcon#about to read 5, iclass 25, count 0 2006.183.07:38:22.30#ibcon#read 5, iclass 25, count 0 2006.183.07:38:22.30#ibcon#about to read 6, iclass 25, count 0 2006.183.07:38:22.30#ibcon#read 6, iclass 25, count 0 2006.183.07:38:22.30#ibcon#end of sib2, iclass 25, count 0 2006.183.07:38:22.30#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:38:22.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:38:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:38:22.30#ibcon#*before write, iclass 25, count 0 2006.183.07:38:22.30#ibcon#enter sib2, iclass 25, count 0 2006.183.07:38:22.30#ibcon#flushed, iclass 25, count 0 2006.183.07:38:22.30#ibcon#about to write, iclass 25, count 0 2006.183.07:38:22.30#ibcon#wrote, iclass 25, count 0 2006.183.07:38:22.30#ibcon#about to read 3, iclass 25, count 0 2006.183.07:38:22.33#abcon#[5=S1D000X0/0*\r\n] 2006.183.07:38:22.34#ibcon#read 3, iclass 25, count 0 2006.183.07:38:22.34#ibcon#about to read 4, iclass 25, count 0 2006.183.07:38:22.34#ibcon#read 4, iclass 25, count 0 2006.183.07:38:22.34#ibcon#about to read 5, iclass 25, count 0 2006.183.07:38:22.34#ibcon#read 5, iclass 25, count 0 2006.183.07:38:22.34#ibcon#about to read 6, iclass 25, count 0 2006.183.07:38:22.34#ibcon#read 6, iclass 25, count 0 2006.183.07:38:22.34#ibcon#end of sib2, iclass 25, count 0 2006.183.07:38:22.34#ibcon#*after write, iclass 25, count 0 2006.183.07:38:22.34#ibcon#*before return 0, iclass 25, count 0 2006.183.07:38:22.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:38:22.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:38:22.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:38:22.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:38:22.34$vc4f8/vb=6,4 2006.183.07:38:22.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.07:38:22.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.07:38:22.34#ibcon#ireg 11 cls_cnt 2 2006.183.07:38:22.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:22.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:22.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:22.40#ibcon#enter wrdev, iclass 28, count 2 2006.183.07:38:22.40#ibcon#first serial, iclass 28, count 2 2006.183.07:38:22.40#ibcon#enter sib2, iclass 28, count 2 2006.183.07:38:22.40#ibcon#flushed, iclass 28, count 2 2006.183.07:38:22.40#ibcon#about to write, iclass 28, count 2 2006.183.07:38:22.40#ibcon#wrote, iclass 28, count 2 2006.183.07:38:22.40#ibcon#about to read 3, iclass 28, count 2 2006.183.07:38:22.42#ibcon#read 3, iclass 28, count 2 2006.183.07:38:22.42#ibcon#about to read 4, iclass 28, count 2 2006.183.07:38:22.42#ibcon#read 4, iclass 28, count 2 2006.183.07:38:22.42#ibcon#about to read 5, iclass 28, count 2 2006.183.07:38:22.42#ibcon#read 5, iclass 28, count 2 2006.183.07:38:22.42#ibcon#about to read 6, iclass 28, count 2 2006.183.07:38:22.42#ibcon#read 6, iclass 28, count 2 2006.183.07:38:22.42#ibcon#end of sib2, iclass 28, count 2 2006.183.07:38:22.42#ibcon#*mode == 0, iclass 28, count 2 2006.183.07:38:22.42#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.07:38:22.42#ibcon#[27=AT06-04\r\n] 2006.183.07:38:22.42#ibcon#*before write, iclass 28, count 2 2006.183.07:38:22.42#ibcon#enter sib2, iclass 28, count 2 2006.183.07:38:22.42#ibcon#flushed, iclass 28, count 2 2006.183.07:38:22.42#ibcon#about to write, iclass 28, count 2 2006.183.07:38:22.42#ibcon#wrote, iclass 28, count 2 2006.183.07:38:22.42#ibcon#about to read 3, iclass 28, count 2 2006.183.07:38:22.45#ibcon#read 3, iclass 28, count 2 2006.183.07:38:22.45#ibcon#about to read 4, iclass 28, count 2 2006.183.07:38:22.45#ibcon#read 4, iclass 28, count 2 2006.183.07:38:22.45#ibcon#about to read 5, iclass 28, count 2 2006.183.07:38:22.45#ibcon#read 5, iclass 28, count 2 2006.183.07:38:22.45#ibcon#about to read 6, iclass 28, count 2 2006.183.07:38:22.45#ibcon#read 6, iclass 28, count 2 2006.183.07:38:22.45#ibcon#end of sib2, iclass 28, count 2 2006.183.07:38:22.45#ibcon#*after write, iclass 28, count 2 2006.183.07:38:22.45#ibcon#*before return 0, iclass 28, count 2 2006.183.07:38:22.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:22.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:38:22.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.07:38:22.45#ibcon#ireg 7 cls_cnt 0 2006.183.07:38:22.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:22.57#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:22.57#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:22.57#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:38:22.57#ibcon#first serial, iclass 28, count 0 2006.183.07:38:22.57#ibcon#enter sib2, iclass 28, count 0 2006.183.07:38:22.57#ibcon#flushed, iclass 28, count 0 2006.183.07:38:22.57#ibcon#about to write, iclass 28, count 0 2006.183.07:38:22.57#ibcon#wrote, iclass 28, count 0 2006.183.07:38:22.57#ibcon#about to read 3, iclass 28, count 0 2006.183.07:38:22.59#ibcon#read 3, iclass 28, count 0 2006.183.07:38:22.59#ibcon#about to read 4, iclass 28, count 0 2006.183.07:38:22.59#ibcon#read 4, iclass 28, count 0 2006.183.07:38:22.59#ibcon#about to read 5, iclass 28, count 0 2006.183.07:38:22.59#ibcon#read 5, iclass 28, count 0 2006.183.07:38:22.59#ibcon#about to read 6, iclass 28, count 0 2006.183.07:38:22.59#ibcon#read 6, iclass 28, count 0 2006.183.07:38:22.59#ibcon#end of sib2, iclass 28, count 0 2006.183.07:38:22.59#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:38:22.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:38:22.59#ibcon#[27=USB\r\n] 2006.183.07:38:22.59#ibcon#*before write, iclass 28, count 0 2006.183.07:38:22.59#ibcon#enter sib2, iclass 28, count 0 2006.183.07:38:22.59#ibcon#flushed, iclass 28, count 0 2006.183.07:38:22.59#ibcon#about to write, iclass 28, count 0 2006.183.07:38:22.59#ibcon#wrote, iclass 28, count 0 2006.183.07:38:22.59#ibcon#about to read 3, iclass 28, count 0 2006.183.07:38:22.62#ibcon#read 3, iclass 28, count 0 2006.183.07:38:22.62#ibcon#about to read 4, iclass 28, count 0 2006.183.07:38:22.62#ibcon#read 4, iclass 28, count 0 2006.183.07:38:22.62#ibcon#about to read 5, iclass 28, count 0 2006.183.07:38:22.62#ibcon#read 5, iclass 28, count 0 2006.183.07:38:22.62#ibcon#about to read 6, iclass 28, count 0 2006.183.07:38:22.62#ibcon#read 6, iclass 28, count 0 2006.183.07:38:22.62#ibcon#end of sib2, iclass 28, count 0 2006.183.07:38:22.62#ibcon#*after write, iclass 28, count 0 2006.183.07:38:22.62#ibcon#*before return 0, iclass 28, count 0 2006.183.07:38:22.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:22.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:38:22.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:38:22.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:38:22.62$vc4f8/vabw=wide 2006.183.07:38:22.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.07:38:22.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.07:38:22.62#ibcon#ireg 8 cls_cnt 0 2006.183.07:38:22.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:22.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:22.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:22.62#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:38:22.62#ibcon#first serial, iclass 30, count 0 2006.183.07:38:22.62#ibcon#enter sib2, iclass 30, count 0 2006.183.07:38:22.62#ibcon#flushed, iclass 30, count 0 2006.183.07:38:22.62#ibcon#about to write, iclass 30, count 0 2006.183.07:38:22.62#ibcon#wrote, iclass 30, count 0 2006.183.07:38:22.62#ibcon#about to read 3, iclass 30, count 0 2006.183.07:38:22.64#ibcon#read 3, iclass 30, count 0 2006.183.07:38:22.64#ibcon#about to read 4, iclass 30, count 0 2006.183.07:38:22.64#ibcon#read 4, iclass 30, count 0 2006.183.07:38:22.64#ibcon#about to read 5, iclass 30, count 0 2006.183.07:38:22.64#ibcon#read 5, iclass 30, count 0 2006.183.07:38:22.64#ibcon#about to read 6, iclass 30, count 0 2006.183.07:38:22.64#ibcon#read 6, iclass 30, count 0 2006.183.07:38:22.64#ibcon#end of sib2, iclass 30, count 0 2006.183.07:38:22.64#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:38:22.64#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:38:22.64#ibcon#[25=BW32\r\n] 2006.183.07:38:22.64#ibcon#*before write, iclass 30, count 0 2006.183.07:38:22.64#ibcon#enter sib2, iclass 30, count 0 2006.183.07:38:22.64#ibcon#flushed, iclass 30, count 0 2006.183.07:38:22.64#ibcon#about to write, iclass 30, count 0 2006.183.07:38:22.64#ibcon#wrote, iclass 30, count 0 2006.183.07:38:22.64#ibcon#about to read 3, iclass 30, count 0 2006.183.07:38:22.67#ibcon#read 3, iclass 30, count 0 2006.183.07:38:22.67#ibcon#about to read 4, iclass 30, count 0 2006.183.07:38:22.67#ibcon#read 4, iclass 30, count 0 2006.183.07:38:22.67#ibcon#about to read 5, iclass 30, count 0 2006.183.07:38:22.67#ibcon#read 5, iclass 30, count 0 2006.183.07:38:22.67#ibcon#about to read 6, iclass 30, count 0 2006.183.07:38:22.67#ibcon#read 6, iclass 30, count 0 2006.183.07:38:22.67#ibcon#end of sib2, iclass 30, count 0 2006.183.07:38:22.67#ibcon#*after write, iclass 30, count 0 2006.183.07:38:22.67#ibcon#*before return 0, iclass 30, count 0 2006.183.07:38:22.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:22.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:38:22.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:38:22.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:38:22.67$vc4f8/vbbw=wide 2006.183.07:38:22.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.07:38:22.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.07:38:22.67#ibcon#ireg 8 cls_cnt 0 2006.183.07:38:22.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:38:22.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:38:22.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:38:22.74#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:38:22.74#ibcon#first serial, iclass 32, count 0 2006.183.07:38:22.74#ibcon#enter sib2, iclass 32, count 0 2006.183.07:38:22.74#ibcon#flushed, iclass 32, count 0 2006.183.07:38:22.74#ibcon#about to write, iclass 32, count 0 2006.183.07:38:22.74#ibcon#wrote, iclass 32, count 0 2006.183.07:38:22.74#ibcon#about to read 3, iclass 32, count 0 2006.183.07:38:22.76#ibcon#read 3, iclass 32, count 0 2006.183.07:38:22.76#ibcon#about to read 4, iclass 32, count 0 2006.183.07:38:22.76#ibcon#read 4, iclass 32, count 0 2006.183.07:38:22.76#ibcon#about to read 5, iclass 32, count 0 2006.183.07:38:22.76#ibcon#read 5, iclass 32, count 0 2006.183.07:38:22.76#ibcon#about to read 6, iclass 32, count 0 2006.183.07:38:22.76#ibcon#read 6, iclass 32, count 0 2006.183.07:38:22.76#ibcon#end of sib2, iclass 32, count 0 2006.183.07:38:22.76#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:38:22.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:38:22.76#ibcon#[27=BW32\r\n] 2006.183.07:38:22.76#ibcon#*before write, iclass 32, count 0 2006.183.07:38:22.76#ibcon#enter sib2, iclass 32, count 0 2006.183.07:38:22.76#ibcon#flushed, iclass 32, count 0 2006.183.07:38:22.76#ibcon#about to write, iclass 32, count 0 2006.183.07:38:22.76#ibcon#wrote, iclass 32, count 0 2006.183.07:38:22.76#ibcon#about to read 3, iclass 32, count 0 2006.183.07:38:22.79#ibcon#read 3, iclass 32, count 0 2006.183.07:38:22.79#ibcon#about to read 4, iclass 32, count 0 2006.183.07:38:22.79#ibcon#read 4, iclass 32, count 0 2006.183.07:38:22.79#ibcon#about to read 5, iclass 32, count 0 2006.183.07:38:22.79#ibcon#read 5, iclass 32, count 0 2006.183.07:38:22.79#ibcon#about to read 6, iclass 32, count 0 2006.183.07:38:22.79#ibcon#read 6, iclass 32, count 0 2006.183.07:38:22.79#ibcon#end of sib2, iclass 32, count 0 2006.183.07:38:22.79#ibcon#*after write, iclass 32, count 0 2006.183.07:38:22.79#ibcon#*before return 0, iclass 32, count 0 2006.183.07:38:22.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:38:22.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:38:22.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:38:22.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:38:22.79$4f8m12a/ifd4f 2006.183.07:38:22.79$ifd4f/lo= 2006.183.07:38:22.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:38:22.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:38:22.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:38:22.79$ifd4f/patch= 2006.183.07:38:22.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:38:22.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:38:22.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:38:22.80$4f8m12a/"form=m,16.000,1:2 2006.183.07:38:22.80$4f8m12a/"tpicd 2006.183.07:38:22.80$4f8m12a/echo=off 2006.183.07:38:22.80$4f8m12a/xlog=off 2006.183.07:38:22.80:!2006.183.07:38:50 2006.183.07:38:36.14#trakl#Source acquired 2006.183.07:38:38.14#flagr#flagr/antenna,acquired 2006.183.07:38:50.01:preob 2006.183.07:38:51.14/onsource/TRACKING 2006.183.07:38:51.14:!2006.183.07:39:00 2006.183.07:39:00.00:data_valid=on 2006.183.07:39:00.00:midob 2006.183.07:39:00.14/onsource/TRACKING 2006.183.07:39:00.14/wx/27.91,996.3,88 2006.183.07:39:00.27/cable/+6.4525E-03 2006.183.07:39:01.36/va/01,08,usb,yes,30,32 2006.183.07:39:01.36/va/02,07,usb,yes,30,32 2006.183.07:39:01.36/va/03,06,usb,yes,32,32 2006.183.07:39:01.36/va/04,07,usb,yes,31,34 2006.183.07:39:01.36/va/05,07,usb,yes,33,35 2006.183.07:39:01.36/va/06,06,usb,yes,33,32 2006.183.07:39:01.36/va/07,06,usb,yes,33,33 2006.183.07:39:01.36/va/08,07,usb,yes,31,31 2006.183.07:39:01.59/valo/01,532.99,yes,locked 2006.183.07:39:01.59/valo/02,572.99,yes,locked 2006.183.07:39:01.59/valo/03,672.99,yes,locked 2006.183.07:39:01.59/valo/04,832.99,yes,locked 2006.183.07:39:01.59/valo/05,652.99,yes,locked 2006.183.07:39:01.59/valo/06,772.99,yes,locked 2006.183.07:39:01.59/valo/07,832.99,yes,locked 2006.183.07:39:01.59/valo/08,852.99,yes,locked 2006.183.07:39:02.68/vb/01,04,usb,yes,30,29 2006.183.07:39:02.68/vb/02,04,usb,yes,32,33 2006.183.07:39:02.68/vb/03,04,usb,yes,28,32 2006.183.07:39:02.68/vb/04,04,usb,yes,29,29 2006.183.07:39:02.68/vb/05,04,usb,yes,28,31 2006.183.07:39:02.68/vb/06,04,usb,yes,29,31 2006.183.07:39:02.68/vb/07,04,usb,yes,31,30 2006.183.07:39:02.68/vb/08,04,usb,yes,28,31 2006.183.07:39:02.91/vblo/01,632.99,yes,locked 2006.183.07:39:02.91/vblo/02,640.99,yes,locked 2006.183.07:39:02.91/vblo/03,656.99,yes,locked 2006.183.07:39:02.91/vblo/04,712.99,yes,locked 2006.183.07:39:02.91/vblo/05,744.99,yes,locked 2006.183.07:39:02.91/vblo/06,752.99,yes,locked 2006.183.07:39:02.91/vblo/07,734.99,yes,locked 2006.183.07:39:02.91/vblo/08,744.99,yes,locked 2006.183.07:39:03.06/vabw/8 2006.183.07:39:03.21/vbbw/8 2006.183.07:39:03.32/xfe/off,on,14.7 2006.183.07:39:03.70/ifatt/23,28,28,28 2006.183.07:39:04.07/fmout-gps/S +3.30E-07 2006.183.07:39:04.15:!2006.183.07:40:00 2006.183.07:40:00.00:data_valid=off 2006.183.07:40:00.01:postob 2006.183.07:40:00.12/cable/+6.4507E-03 2006.183.07:40:00.13/wx/27.91,996.3,88 2006.183.07:40:01.07/fmout-gps/S +3.30E-07 2006.183.07:40:01.08:scan_name=183-0740,k06183,60 2006.183.07:40:01.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.183.07:40:01.14#flagr#flagr/antenna,new-source 2006.183.07:40:02.14:checkk5 2006.183.07:40:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:40:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:40:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:40:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:40:04.00/chk_obsdata//k5ts1/T1830739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:40:04.37/chk_obsdata//k5ts2/T1830739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:40:04.74/chk_obsdata//k5ts3/T1830739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:40:05.11/chk_obsdata//k5ts4/T1830739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:40:05.81/k5log//k5ts1_log_newline 2006.183.07:40:06.50/k5log//k5ts2_log_newline 2006.183.07:40:07.18/k5log//k5ts3_log_newline 2006.183.07:40:07.87/k5log//k5ts4_log_newline 2006.183.07:40:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:40:07.90:4f8m12a=1 2006.183.07:40:07.90$4f8m12a/echo=on 2006.183.07:40:07.90$4f8m12a/pcalon 2006.183.07:40:07.90$pcalon/"no phase cal control is implemented here 2006.183.07:40:07.90$4f8m12a/"tpicd=stop 2006.183.07:40:07.90$4f8m12a/vc4f8 2006.183.07:40:07.90$vc4f8/valo=1,532.99 2006.183.07:40:07.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.07:40:07.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.07:40:07.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:07.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:07.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:07.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:07.90#ibcon#enter wrdev, iclass 39, count 0 2006.183.07:40:07.90#ibcon#first serial, iclass 39, count 0 2006.183.07:40:07.90#ibcon#enter sib2, iclass 39, count 0 2006.183.07:40:07.90#ibcon#flushed, iclass 39, count 0 2006.183.07:40:07.90#ibcon#about to write, iclass 39, count 0 2006.183.07:40:07.90#ibcon#wrote, iclass 39, count 0 2006.183.07:40:07.90#ibcon#about to read 3, iclass 39, count 0 2006.183.07:40:07.91#ibcon#read 3, iclass 39, count 0 2006.183.07:40:07.91#ibcon#about to read 4, iclass 39, count 0 2006.183.07:40:07.91#ibcon#read 4, iclass 39, count 0 2006.183.07:40:07.91#ibcon#about to read 5, iclass 39, count 0 2006.183.07:40:07.91#ibcon#read 5, iclass 39, count 0 2006.183.07:40:07.91#ibcon#about to read 6, iclass 39, count 0 2006.183.07:40:07.91#ibcon#read 6, iclass 39, count 0 2006.183.07:40:07.91#ibcon#end of sib2, iclass 39, count 0 2006.183.07:40:07.91#ibcon#*mode == 0, iclass 39, count 0 2006.183.07:40:07.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.07:40:07.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:40:07.91#ibcon#*before write, iclass 39, count 0 2006.183.07:40:07.91#ibcon#enter sib2, iclass 39, count 0 2006.183.07:40:07.91#ibcon#flushed, iclass 39, count 0 2006.183.07:40:07.91#ibcon#about to write, iclass 39, count 0 2006.183.07:40:07.91#ibcon#wrote, iclass 39, count 0 2006.183.07:40:07.91#ibcon#about to read 3, iclass 39, count 0 2006.183.07:40:07.96#ibcon#read 3, iclass 39, count 0 2006.183.07:40:07.96#ibcon#about to read 4, iclass 39, count 0 2006.183.07:40:07.96#ibcon#read 4, iclass 39, count 0 2006.183.07:40:07.96#ibcon#about to read 5, iclass 39, count 0 2006.183.07:40:07.96#ibcon#read 5, iclass 39, count 0 2006.183.07:40:07.96#ibcon#about to read 6, iclass 39, count 0 2006.183.07:40:07.96#ibcon#read 6, iclass 39, count 0 2006.183.07:40:07.96#ibcon#end of sib2, iclass 39, count 0 2006.183.07:40:07.96#ibcon#*after write, iclass 39, count 0 2006.183.07:40:07.96#ibcon#*before return 0, iclass 39, count 0 2006.183.07:40:07.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:07.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:07.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.07:40:07.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.07:40:07.96$vc4f8/va=1,8 2006.183.07:40:07.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.183.07:40:07.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.183.07:40:07.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:07.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:07.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:07.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:07.96#ibcon#enter wrdev, iclass 3, count 2 2006.183.07:40:07.96#ibcon#first serial, iclass 3, count 2 2006.183.07:40:07.96#ibcon#enter sib2, iclass 3, count 2 2006.183.07:40:07.96#ibcon#flushed, iclass 3, count 2 2006.183.07:40:07.96#ibcon#about to write, iclass 3, count 2 2006.183.07:40:07.96#ibcon#wrote, iclass 3, count 2 2006.183.07:40:07.96#ibcon#about to read 3, iclass 3, count 2 2006.183.07:40:07.98#ibcon#read 3, iclass 3, count 2 2006.183.07:40:07.98#ibcon#about to read 4, iclass 3, count 2 2006.183.07:40:07.98#ibcon#read 4, iclass 3, count 2 2006.183.07:40:07.98#ibcon#about to read 5, iclass 3, count 2 2006.183.07:40:07.98#ibcon#read 5, iclass 3, count 2 2006.183.07:40:07.98#ibcon#about to read 6, iclass 3, count 2 2006.183.07:40:07.98#ibcon#read 6, iclass 3, count 2 2006.183.07:40:07.98#ibcon#end of sib2, iclass 3, count 2 2006.183.07:40:07.98#ibcon#*mode == 0, iclass 3, count 2 2006.183.07:40:07.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.183.07:40:07.98#ibcon#[25=AT01-08\r\n] 2006.183.07:40:07.98#ibcon#*before write, iclass 3, count 2 2006.183.07:40:07.98#ibcon#enter sib2, iclass 3, count 2 2006.183.07:40:07.98#ibcon#flushed, iclass 3, count 2 2006.183.07:40:07.98#ibcon#about to write, iclass 3, count 2 2006.183.07:40:07.98#ibcon#wrote, iclass 3, count 2 2006.183.07:40:07.98#ibcon#about to read 3, iclass 3, count 2 2006.183.07:40:08.02#ibcon#read 3, iclass 3, count 2 2006.183.07:40:08.02#ibcon#about to read 4, iclass 3, count 2 2006.183.07:40:08.02#ibcon#read 4, iclass 3, count 2 2006.183.07:40:08.02#ibcon#about to read 5, iclass 3, count 2 2006.183.07:40:08.02#ibcon#read 5, iclass 3, count 2 2006.183.07:40:08.02#ibcon#about to read 6, iclass 3, count 2 2006.183.07:40:08.02#ibcon#read 6, iclass 3, count 2 2006.183.07:40:08.02#ibcon#end of sib2, iclass 3, count 2 2006.183.07:40:08.02#ibcon#*after write, iclass 3, count 2 2006.183.07:40:08.02#ibcon#*before return 0, iclass 3, count 2 2006.183.07:40:08.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:08.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:08.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.183.07:40:08.02#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:08.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:08.14#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:08.14#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:08.14#ibcon#enter wrdev, iclass 3, count 0 2006.183.07:40:08.14#ibcon#first serial, iclass 3, count 0 2006.183.07:40:08.14#ibcon#enter sib2, iclass 3, count 0 2006.183.07:40:08.14#ibcon#flushed, iclass 3, count 0 2006.183.07:40:08.14#ibcon#about to write, iclass 3, count 0 2006.183.07:40:08.14#ibcon#wrote, iclass 3, count 0 2006.183.07:40:08.14#ibcon#about to read 3, iclass 3, count 0 2006.183.07:40:08.15#ibcon#read 3, iclass 3, count 0 2006.183.07:40:08.15#ibcon#about to read 4, iclass 3, count 0 2006.183.07:40:08.15#ibcon#read 4, iclass 3, count 0 2006.183.07:40:08.15#ibcon#about to read 5, iclass 3, count 0 2006.183.07:40:08.15#ibcon#read 5, iclass 3, count 0 2006.183.07:40:08.15#ibcon#about to read 6, iclass 3, count 0 2006.183.07:40:08.15#ibcon#read 6, iclass 3, count 0 2006.183.07:40:08.15#ibcon#end of sib2, iclass 3, count 0 2006.183.07:40:08.15#ibcon#*mode == 0, iclass 3, count 0 2006.183.07:40:08.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.07:40:08.15#ibcon#[25=USB\r\n] 2006.183.07:40:08.15#ibcon#*before write, iclass 3, count 0 2006.183.07:40:08.15#ibcon#enter sib2, iclass 3, count 0 2006.183.07:40:08.15#ibcon#flushed, iclass 3, count 0 2006.183.07:40:08.15#ibcon#about to write, iclass 3, count 0 2006.183.07:40:08.15#ibcon#wrote, iclass 3, count 0 2006.183.07:40:08.15#ibcon#about to read 3, iclass 3, count 0 2006.183.07:40:08.18#ibcon#read 3, iclass 3, count 0 2006.183.07:40:08.18#ibcon#about to read 4, iclass 3, count 0 2006.183.07:40:08.18#ibcon#read 4, iclass 3, count 0 2006.183.07:40:08.18#ibcon#about to read 5, iclass 3, count 0 2006.183.07:40:08.18#ibcon#read 5, iclass 3, count 0 2006.183.07:40:08.18#ibcon#about to read 6, iclass 3, count 0 2006.183.07:40:08.18#ibcon#read 6, iclass 3, count 0 2006.183.07:40:08.18#ibcon#end of sib2, iclass 3, count 0 2006.183.07:40:08.18#ibcon#*after write, iclass 3, count 0 2006.183.07:40:08.18#ibcon#*before return 0, iclass 3, count 0 2006.183.07:40:08.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:08.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:08.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.07:40:08.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.07:40:08.18$vc4f8/valo=2,572.99 2006.183.07:40:08.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.07:40:08.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.07:40:08.18#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:08.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:08.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:08.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:08.18#ibcon#enter wrdev, iclass 5, count 0 2006.183.07:40:08.18#ibcon#first serial, iclass 5, count 0 2006.183.07:40:08.18#ibcon#enter sib2, iclass 5, count 0 2006.183.07:40:08.18#ibcon#flushed, iclass 5, count 0 2006.183.07:40:08.18#ibcon#about to write, iclass 5, count 0 2006.183.07:40:08.18#ibcon#wrote, iclass 5, count 0 2006.183.07:40:08.18#ibcon#about to read 3, iclass 5, count 0 2006.183.07:40:08.21#ibcon#read 3, iclass 5, count 0 2006.183.07:40:08.21#ibcon#about to read 4, iclass 5, count 0 2006.183.07:40:08.21#ibcon#read 4, iclass 5, count 0 2006.183.07:40:08.21#ibcon#about to read 5, iclass 5, count 0 2006.183.07:40:08.21#ibcon#read 5, iclass 5, count 0 2006.183.07:40:08.21#ibcon#about to read 6, iclass 5, count 0 2006.183.07:40:08.21#ibcon#read 6, iclass 5, count 0 2006.183.07:40:08.21#ibcon#end of sib2, iclass 5, count 0 2006.183.07:40:08.21#ibcon#*mode == 0, iclass 5, count 0 2006.183.07:40:08.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.07:40:08.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:40:08.21#ibcon#*before write, iclass 5, count 0 2006.183.07:40:08.21#ibcon#enter sib2, iclass 5, count 0 2006.183.07:40:08.21#ibcon#flushed, iclass 5, count 0 2006.183.07:40:08.21#ibcon#about to write, iclass 5, count 0 2006.183.07:40:08.21#ibcon#wrote, iclass 5, count 0 2006.183.07:40:08.21#ibcon#about to read 3, iclass 5, count 0 2006.183.07:40:08.25#ibcon#read 3, iclass 5, count 0 2006.183.07:40:08.25#ibcon#about to read 4, iclass 5, count 0 2006.183.07:40:08.25#ibcon#read 4, iclass 5, count 0 2006.183.07:40:08.25#ibcon#about to read 5, iclass 5, count 0 2006.183.07:40:08.25#ibcon#read 5, iclass 5, count 0 2006.183.07:40:08.25#ibcon#about to read 6, iclass 5, count 0 2006.183.07:40:08.25#ibcon#read 6, iclass 5, count 0 2006.183.07:40:08.25#ibcon#end of sib2, iclass 5, count 0 2006.183.07:40:08.25#ibcon#*after write, iclass 5, count 0 2006.183.07:40:08.25#ibcon#*before return 0, iclass 5, count 0 2006.183.07:40:08.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:08.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:08.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.07:40:08.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.07:40:08.25$vc4f8/va=2,7 2006.183.07:40:08.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.07:40:08.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.07:40:08.25#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:08.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:08.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:08.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:08.30#ibcon#enter wrdev, iclass 7, count 2 2006.183.07:40:08.30#ibcon#first serial, iclass 7, count 2 2006.183.07:40:08.30#ibcon#enter sib2, iclass 7, count 2 2006.183.07:40:08.30#ibcon#flushed, iclass 7, count 2 2006.183.07:40:08.30#ibcon#about to write, iclass 7, count 2 2006.183.07:40:08.30#ibcon#wrote, iclass 7, count 2 2006.183.07:40:08.30#ibcon#about to read 3, iclass 7, count 2 2006.183.07:40:08.32#ibcon#read 3, iclass 7, count 2 2006.183.07:40:08.32#ibcon#about to read 4, iclass 7, count 2 2006.183.07:40:08.32#ibcon#read 4, iclass 7, count 2 2006.183.07:40:08.32#ibcon#about to read 5, iclass 7, count 2 2006.183.07:40:08.32#ibcon#read 5, iclass 7, count 2 2006.183.07:40:08.32#ibcon#about to read 6, iclass 7, count 2 2006.183.07:40:08.32#ibcon#read 6, iclass 7, count 2 2006.183.07:40:08.32#ibcon#end of sib2, iclass 7, count 2 2006.183.07:40:08.32#ibcon#*mode == 0, iclass 7, count 2 2006.183.07:40:08.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.07:40:08.32#ibcon#[25=AT02-07\r\n] 2006.183.07:40:08.32#ibcon#*before write, iclass 7, count 2 2006.183.07:40:08.32#ibcon#enter sib2, iclass 7, count 2 2006.183.07:40:08.32#ibcon#flushed, iclass 7, count 2 2006.183.07:40:08.32#ibcon#about to write, iclass 7, count 2 2006.183.07:40:08.32#ibcon#wrote, iclass 7, count 2 2006.183.07:40:08.32#ibcon#about to read 3, iclass 7, count 2 2006.183.07:40:08.35#ibcon#read 3, iclass 7, count 2 2006.183.07:40:08.35#ibcon#about to read 4, iclass 7, count 2 2006.183.07:40:08.35#ibcon#read 4, iclass 7, count 2 2006.183.07:40:08.35#ibcon#about to read 5, iclass 7, count 2 2006.183.07:40:08.35#ibcon#read 5, iclass 7, count 2 2006.183.07:40:08.35#ibcon#about to read 6, iclass 7, count 2 2006.183.07:40:08.35#ibcon#read 6, iclass 7, count 2 2006.183.07:40:08.35#ibcon#end of sib2, iclass 7, count 2 2006.183.07:40:08.35#ibcon#*after write, iclass 7, count 2 2006.183.07:40:08.35#ibcon#*before return 0, iclass 7, count 2 2006.183.07:40:08.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:08.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:08.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.07:40:08.35#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:08.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:08.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:08.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:08.47#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:40:08.47#ibcon#first serial, iclass 7, count 0 2006.183.07:40:08.47#ibcon#enter sib2, iclass 7, count 0 2006.183.07:40:08.47#ibcon#flushed, iclass 7, count 0 2006.183.07:40:08.47#ibcon#about to write, iclass 7, count 0 2006.183.07:40:08.47#ibcon#wrote, iclass 7, count 0 2006.183.07:40:08.47#ibcon#about to read 3, iclass 7, count 0 2006.183.07:40:08.49#ibcon#read 3, iclass 7, count 0 2006.183.07:40:08.49#ibcon#about to read 4, iclass 7, count 0 2006.183.07:40:08.49#ibcon#read 4, iclass 7, count 0 2006.183.07:40:08.49#ibcon#about to read 5, iclass 7, count 0 2006.183.07:40:08.49#ibcon#read 5, iclass 7, count 0 2006.183.07:40:08.49#ibcon#about to read 6, iclass 7, count 0 2006.183.07:40:08.49#ibcon#read 6, iclass 7, count 0 2006.183.07:40:08.49#ibcon#end of sib2, iclass 7, count 0 2006.183.07:40:08.49#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:40:08.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:40:08.49#ibcon#[25=USB\r\n] 2006.183.07:40:08.49#ibcon#*before write, iclass 7, count 0 2006.183.07:40:08.49#ibcon#enter sib2, iclass 7, count 0 2006.183.07:40:08.49#ibcon#flushed, iclass 7, count 0 2006.183.07:40:08.49#ibcon#about to write, iclass 7, count 0 2006.183.07:40:08.49#ibcon#wrote, iclass 7, count 0 2006.183.07:40:08.49#ibcon#about to read 3, iclass 7, count 0 2006.183.07:40:08.52#ibcon#read 3, iclass 7, count 0 2006.183.07:40:08.52#ibcon#about to read 4, iclass 7, count 0 2006.183.07:40:08.52#ibcon#read 4, iclass 7, count 0 2006.183.07:40:08.52#ibcon#about to read 5, iclass 7, count 0 2006.183.07:40:08.52#ibcon#read 5, iclass 7, count 0 2006.183.07:40:08.52#ibcon#about to read 6, iclass 7, count 0 2006.183.07:40:08.52#ibcon#read 6, iclass 7, count 0 2006.183.07:40:08.52#ibcon#end of sib2, iclass 7, count 0 2006.183.07:40:08.52#ibcon#*after write, iclass 7, count 0 2006.183.07:40:08.52#ibcon#*before return 0, iclass 7, count 0 2006.183.07:40:08.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:08.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:08.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:40:08.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:40:08.52$vc4f8/valo=3,672.99 2006.183.07:40:08.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.07:40:08.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.07:40:08.52#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:08.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:08.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:08.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:08.52#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:40:08.52#ibcon#first serial, iclass 11, count 0 2006.183.07:40:08.52#ibcon#enter sib2, iclass 11, count 0 2006.183.07:40:08.52#ibcon#flushed, iclass 11, count 0 2006.183.07:40:08.52#ibcon#about to write, iclass 11, count 0 2006.183.07:40:08.52#ibcon#wrote, iclass 11, count 0 2006.183.07:40:08.52#ibcon#about to read 3, iclass 11, count 0 2006.183.07:40:08.55#ibcon#read 3, iclass 11, count 0 2006.183.07:40:08.55#ibcon#about to read 4, iclass 11, count 0 2006.183.07:40:08.55#ibcon#read 4, iclass 11, count 0 2006.183.07:40:08.55#ibcon#about to read 5, iclass 11, count 0 2006.183.07:40:08.55#ibcon#read 5, iclass 11, count 0 2006.183.07:40:08.55#ibcon#about to read 6, iclass 11, count 0 2006.183.07:40:08.55#ibcon#read 6, iclass 11, count 0 2006.183.07:40:08.55#ibcon#end of sib2, iclass 11, count 0 2006.183.07:40:08.55#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:40:08.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:40:08.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:40:08.55#ibcon#*before write, iclass 11, count 0 2006.183.07:40:08.55#ibcon#enter sib2, iclass 11, count 0 2006.183.07:40:08.55#ibcon#flushed, iclass 11, count 0 2006.183.07:40:08.55#ibcon#about to write, iclass 11, count 0 2006.183.07:40:08.55#ibcon#wrote, iclass 11, count 0 2006.183.07:40:08.55#ibcon#about to read 3, iclass 11, count 0 2006.183.07:40:08.59#ibcon#read 3, iclass 11, count 0 2006.183.07:40:08.59#ibcon#about to read 4, iclass 11, count 0 2006.183.07:40:08.59#ibcon#read 4, iclass 11, count 0 2006.183.07:40:08.59#ibcon#about to read 5, iclass 11, count 0 2006.183.07:40:08.59#ibcon#read 5, iclass 11, count 0 2006.183.07:40:08.59#ibcon#about to read 6, iclass 11, count 0 2006.183.07:40:08.59#ibcon#read 6, iclass 11, count 0 2006.183.07:40:08.59#ibcon#end of sib2, iclass 11, count 0 2006.183.07:40:08.59#ibcon#*after write, iclass 11, count 0 2006.183.07:40:08.59#ibcon#*before return 0, iclass 11, count 0 2006.183.07:40:08.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:08.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:08.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:40:08.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:40:08.59$vc4f8/va=3,6 2006.183.07:40:08.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.07:40:08.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.07:40:08.59#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:08.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:08.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:08.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:08.64#ibcon#enter wrdev, iclass 13, count 2 2006.183.07:40:08.64#ibcon#first serial, iclass 13, count 2 2006.183.07:40:08.64#ibcon#enter sib2, iclass 13, count 2 2006.183.07:40:08.64#ibcon#flushed, iclass 13, count 2 2006.183.07:40:08.64#ibcon#about to write, iclass 13, count 2 2006.183.07:40:08.64#ibcon#wrote, iclass 13, count 2 2006.183.07:40:08.64#ibcon#about to read 3, iclass 13, count 2 2006.183.07:40:08.66#ibcon#read 3, iclass 13, count 2 2006.183.07:40:08.66#ibcon#about to read 4, iclass 13, count 2 2006.183.07:40:08.66#ibcon#read 4, iclass 13, count 2 2006.183.07:40:08.66#ibcon#about to read 5, iclass 13, count 2 2006.183.07:40:08.66#ibcon#read 5, iclass 13, count 2 2006.183.07:40:08.66#ibcon#about to read 6, iclass 13, count 2 2006.183.07:40:08.66#ibcon#read 6, iclass 13, count 2 2006.183.07:40:08.66#ibcon#end of sib2, iclass 13, count 2 2006.183.07:40:08.66#ibcon#*mode == 0, iclass 13, count 2 2006.183.07:40:08.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.07:40:08.66#ibcon#[25=AT03-06\r\n] 2006.183.07:40:08.66#ibcon#*before write, iclass 13, count 2 2006.183.07:40:08.66#ibcon#enter sib2, iclass 13, count 2 2006.183.07:40:08.66#ibcon#flushed, iclass 13, count 2 2006.183.07:40:08.66#ibcon#about to write, iclass 13, count 2 2006.183.07:40:08.66#ibcon#wrote, iclass 13, count 2 2006.183.07:40:08.66#ibcon#about to read 3, iclass 13, count 2 2006.183.07:40:08.69#ibcon#read 3, iclass 13, count 2 2006.183.07:40:08.69#ibcon#about to read 4, iclass 13, count 2 2006.183.07:40:08.69#ibcon#read 4, iclass 13, count 2 2006.183.07:40:08.69#ibcon#about to read 5, iclass 13, count 2 2006.183.07:40:08.69#ibcon#read 5, iclass 13, count 2 2006.183.07:40:08.69#ibcon#about to read 6, iclass 13, count 2 2006.183.07:40:08.69#ibcon#read 6, iclass 13, count 2 2006.183.07:40:08.69#ibcon#end of sib2, iclass 13, count 2 2006.183.07:40:08.69#ibcon#*after write, iclass 13, count 2 2006.183.07:40:08.69#ibcon#*before return 0, iclass 13, count 2 2006.183.07:40:08.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:08.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:08.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.07:40:08.69#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:08.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:08.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:08.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:08.81#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:40:08.81#ibcon#first serial, iclass 13, count 0 2006.183.07:40:08.81#ibcon#enter sib2, iclass 13, count 0 2006.183.07:40:08.81#ibcon#flushed, iclass 13, count 0 2006.183.07:40:08.81#ibcon#about to write, iclass 13, count 0 2006.183.07:40:08.81#ibcon#wrote, iclass 13, count 0 2006.183.07:40:08.81#ibcon#about to read 3, iclass 13, count 0 2006.183.07:40:08.83#ibcon#read 3, iclass 13, count 0 2006.183.07:40:08.83#ibcon#about to read 4, iclass 13, count 0 2006.183.07:40:08.83#ibcon#read 4, iclass 13, count 0 2006.183.07:40:08.83#ibcon#about to read 5, iclass 13, count 0 2006.183.07:40:08.83#ibcon#read 5, iclass 13, count 0 2006.183.07:40:08.83#ibcon#about to read 6, iclass 13, count 0 2006.183.07:40:08.83#ibcon#read 6, iclass 13, count 0 2006.183.07:40:08.83#ibcon#end of sib2, iclass 13, count 0 2006.183.07:40:08.83#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:40:08.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:40:08.83#ibcon#[25=USB\r\n] 2006.183.07:40:08.83#ibcon#*before write, iclass 13, count 0 2006.183.07:40:08.83#ibcon#enter sib2, iclass 13, count 0 2006.183.07:40:08.83#ibcon#flushed, iclass 13, count 0 2006.183.07:40:08.83#ibcon#about to write, iclass 13, count 0 2006.183.07:40:08.83#ibcon#wrote, iclass 13, count 0 2006.183.07:40:08.83#ibcon#about to read 3, iclass 13, count 0 2006.183.07:40:08.86#ibcon#read 3, iclass 13, count 0 2006.183.07:40:08.86#ibcon#about to read 4, iclass 13, count 0 2006.183.07:40:08.86#ibcon#read 4, iclass 13, count 0 2006.183.07:40:08.86#ibcon#about to read 5, iclass 13, count 0 2006.183.07:40:08.86#ibcon#read 5, iclass 13, count 0 2006.183.07:40:08.86#ibcon#about to read 6, iclass 13, count 0 2006.183.07:40:08.86#ibcon#read 6, iclass 13, count 0 2006.183.07:40:08.86#ibcon#end of sib2, iclass 13, count 0 2006.183.07:40:08.86#ibcon#*after write, iclass 13, count 0 2006.183.07:40:08.86#ibcon#*before return 0, iclass 13, count 0 2006.183.07:40:08.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:08.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:08.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:40:08.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:40:08.86$vc4f8/valo=4,832.99 2006.183.07:40:08.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.07:40:08.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.07:40:08.86#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:08.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:08.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:08.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:08.86#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:40:08.86#ibcon#first serial, iclass 15, count 0 2006.183.07:40:08.86#ibcon#enter sib2, iclass 15, count 0 2006.183.07:40:08.86#ibcon#flushed, iclass 15, count 0 2006.183.07:40:08.86#ibcon#about to write, iclass 15, count 0 2006.183.07:40:08.86#ibcon#wrote, iclass 15, count 0 2006.183.07:40:08.86#ibcon#about to read 3, iclass 15, count 0 2006.183.07:40:08.88#ibcon#read 3, iclass 15, count 0 2006.183.07:40:08.88#ibcon#about to read 4, iclass 15, count 0 2006.183.07:40:08.88#ibcon#read 4, iclass 15, count 0 2006.183.07:40:08.88#ibcon#about to read 5, iclass 15, count 0 2006.183.07:40:08.88#ibcon#read 5, iclass 15, count 0 2006.183.07:40:08.88#ibcon#about to read 6, iclass 15, count 0 2006.183.07:40:08.88#ibcon#read 6, iclass 15, count 0 2006.183.07:40:08.88#ibcon#end of sib2, iclass 15, count 0 2006.183.07:40:08.88#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:40:08.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:40:08.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:40:08.88#ibcon#*before write, iclass 15, count 0 2006.183.07:40:08.88#ibcon#enter sib2, iclass 15, count 0 2006.183.07:40:08.88#ibcon#flushed, iclass 15, count 0 2006.183.07:40:08.88#ibcon#about to write, iclass 15, count 0 2006.183.07:40:08.88#ibcon#wrote, iclass 15, count 0 2006.183.07:40:08.88#ibcon#about to read 3, iclass 15, count 0 2006.183.07:40:08.92#ibcon#read 3, iclass 15, count 0 2006.183.07:40:08.92#ibcon#about to read 4, iclass 15, count 0 2006.183.07:40:08.92#ibcon#read 4, iclass 15, count 0 2006.183.07:40:08.92#ibcon#about to read 5, iclass 15, count 0 2006.183.07:40:08.92#ibcon#read 5, iclass 15, count 0 2006.183.07:40:08.92#ibcon#about to read 6, iclass 15, count 0 2006.183.07:40:08.92#ibcon#read 6, iclass 15, count 0 2006.183.07:40:08.92#ibcon#end of sib2, iclass 15, count 0 2006.183.07:40:08.92#ibcon#*after write, iclass 15, count 0 2006.183.07:40:08.92#ibcon#*before return 0, iclass 15, count 0 2006.183.07:40:08.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:08.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:08.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:40:08.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:40:08.92$vc4f8/va=4,7 2006.183.07:40:08.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.07:40:08.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.07:40:08.92#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:08.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:08.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:08.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:08.98#ibcon#enter wrdev, iclass 17, count 2 2006.183.07:40:08.98#ibcon#first serial, iclass 17, count 2 2006.183.07:40:08.98#ibcon#enter sib2, iclass 17, count 2 2006.183.07:40:08.98#ibcon#flushed, iclass 17, count 2 2006.183.07:40:08.98#ibcon#about to write, iclass 17, count 2 2006.183.07:40:08.98#ibcon#wrote, iclass 17, count 2 2006.183.07:40:08.98#ibcon#about to read 3, iclass 17, count 2 2006.183.07:40:09.00#ibcon#read 3, iclass 17, count 2 2006.183.07:40:09.00#ibcon#about to read 4, iclass 17, count 2 2006.183.07:40:09.00#ibcon#read 4, iclass 17, count 2 2006.183.07:40:09.00#ibcon#about to read 5, iclass 17, count 2 2006.183.07:40:09.00#ibcon#read 5, iclass 17, count 2 2006.183.07:40:09.00#ibcon#about to read 6, iclass 17, count 2 2006.183.07:40:09.00#ibcon#read 6, iclass 17, count 2 2006.183.07:40:09.00#ibcon#end of sib2, iclass 17, count 2 2006.183.07:40:09.00#ibcon#*mode == 0, iclass 17, count 2 2006.183.07:40:09.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.07:40:09.00#ibcon#[25=AT04-07\r\n] 2006.183.07:40:09.00#ibcon#*before write, iclass 17, count 2 2006.183.07:40:09.00#ibcon#enter sib2, iclass 17, count 2 2006.183.07:40:09.00#ibcon#flushed, iclass 17, count 2 2006.183.07:40:09.00#ibcon#about to write, iclass 17, count 2 2006.183.07:40:09.00#ibcon#wrote, iclass 17, count 2 2006.183.07:40:09.00#ibcon#about to read 3, iclass 17, count 2 2006.183.07:40:09.03#ibcon#read 3, iclass 17, count 2 2006.183.07:40:09.03#ibcon#about to read 4, iclass 17, count 2 2006.183.07:40:09.03#ibcon#read 4, iclass 17, count 2 2006.183.07:40:09.03#ibcon#about to read 5, iclass 17, count 2 2006.183.07:40:09.03#ibcon#read 5, iclass 17, count 2 2006.183.07:40:09.03#ibcon#about to read 6, iclass 17, count 2 2006.183.07:40:09.03#ibcon#read 6, iclass 17, count 2 2006.183.07:40:09.03#ibcon#end of sib2, iclass 17, count 2 2006.183.07:40:09.03#ibcon#*after write, iclass 17, count 2 2006.183.07:40:09.03#ibcon#*before return 0, iclass 17, count 2 2006.183.07:40:09.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:09.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:09.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.07:40:09.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:09.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:09.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:09.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:09.15#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:40:09.15#ibcon#first serial, iclass 17, count 0 2006.183.07:40:09.15#ibcon#enter sib2, iclass 17, count 0 2006.183.07:40:09.15#ibcon#flushed, iclass 17, count 0 2006.183.07:40:09.15#ibcon#about to write, iclass 17, count 0 2006.183.07:40:09.15#ibcon#wrote, iclass 17, count 0 2006.183.07:40:09.15#ibcon#about to read 3, iclass 17, count 0 2006.183.07:40:09.17#ibcon#read 3, iclass 17, count 0 2006.183.07:40:09.17#ibcon#about to read 4, iclass 17, count 0 2006.183.07:40:09.17#ibcon#read 4, iclass 17, count 0 2006.183.07:40:09.17#ibcon#about to read 5, iclass 17, count 0 2006.183.07:40:09.17#ibcon#read 5, iclass 17, count 0 2006.183.07:40:09.17#ibcon#about to read 6, iclass 17, count 0 2006.183.07:40:09.17#ibcon#read 6, iclass 17, count 0 2006.183.07:40:09.17#ibcon#end of sib2, iclass 17, count 0 2006.183.07:40:09.17#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:40:09.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:40:09.17#ibcon#[25=USB\r\n] 2006.183.07:40:09.17#ibcon#*before write, iclass 17, count 0 2006.183.07:40:09.17#ibcon#enter sib2, iclass 17, count 0 2006.183.07:40:09.17#ibcon#flushed, iclass 17, count 0 2006.183.07:40:09.17#ibcon#about to write, iclass 17, count 0 2006.183.07:40:09.17#ibcon#wrote, iclass 17, count 0 2006.183.07:40:09.17#ibcon#about to read 3, iclass 17, count 0 2006.183.07:40:09.20#ibcon#read 3, iclass 17, count 0 2006.183.07:40:09.20#ibcon#about to read 4, iclass 17, count 0 2006.183.07:40:09.20#ibcon#read 4, iclass 17, count 0 2006.183.07:40:09.20#ibcon#about to read 5, iclass 17, count 0 2006.183.07:40:09.20#ibcon#read 5, iclass 17, count 0 2006.183.07:40:09.20#ibcon#about to read 6, iclass 17, count 0 2006.183.07:40:09.20#ibcon#read 6, iclass 17, count 0 2006.183.07:40:09.20#ibcon#end of sib2, iclass 17, count 0 2006.183.07:40:09.20#ibcon#*after write, iclass 17, count 0 2006.183.07:40:09.20#ibcon#*before return 0, iclass 17, count 0 2006.183.07:40:09.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:09.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:09.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:40:09.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:40:09.20$vc4f8/valo=5,652.99 2006.183.07:40:09.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.07:40:09.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.07:40:09.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:09.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:09.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:09.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:09.20#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:40:09.20#ibcon#first serial, iclass 19, count 0 2006.183.07:40:09.20#ibcon#enter sib2, iclass 19, count 0 2006.183.07:40:09.20#ibcon#flushed, iclass 19, count 0 2006.183.07:40:09.20#ibcon#about to write, iclass 19, count 0 2006.183.07:40:09.20#ibcon#wrote, iclass 19, count 0 2006.183.07:40:09.20#ibcon#about to read 3, iclass 19, count 0 2006.183.07:40:09.22#ibcon#read 3, iclass 19, count 0 2006.183.07:40:09.22#ibcon#about to read 4, iclass 19, count 0 2006.183.07:40:09.22#ibcon#read 4, iclass 19, count 0 2006.183.07:40:09.22#ibcon#about to read 5, iclass 19, count 0 2006.183.07:40:09.22#ibcon#read 5, iclass 19, count 0 2006.183.07:40:09.22#ibcon#about to read 6, iclass 19, count 0 2006.183.07:40:09.22#ibcon#read 6, iclass 19, count 0 2006.183.07:40:09.22#ibcon#end of sib2, iclass 19, count 0 2006.183.07:40:09.22#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:40:09.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:40:09.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:40:09.22#ibcon#*before write, iclass 19, count 0 2006.183.07:40:09.22#ibcon#enter sib2, iclass 19, count 0 2006.183.07:40:09.22#ibcon#flushed, iclass 19, count 0 2006.183.07:40:09.22#ibcon#about to write, iclass 19, count 0 2006.183.07:40:09.22#ibcon#wrote, iclass 19, count 0 2006.183.07:40:09.22#ibcon#about to read 3, iclass 19, count 0 2006.183.07:40:09.26#ibcon#read 3, iclass 19, count 0 2006.183.07:40:09.26#ibcon#about to read 4, iclass 19, count 0 2006.183.07:40:09.26#ibcon#read 4, iclass 19, count 0 2006.183.07:40:09.26#ibcon#about to read 5, iclass 19, count 0 2006.183.07:40:09.26#ibcon#read 5, iclass 19, count 0 2006.183.07:40:09.26#ibcon#about to read 6, iclass 19, count 0 2006.183.07:40:09.26#ibcon#read 6, iclass 19, count 0 2006.183.07:40:09.26#ibcon#end of sib2, iclass 19, count 0 2006.183.07:40:09.26#ibcon#*after write, iclass 19, count 0 2006.183.07:40:09.26#ibcon#*before return 0, iclass 19, count 0 2006.183.07:40:09.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:09.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:09.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:40:09.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:40:09.26$vc4f8/va=5,7 2006.183.07:40:09.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.07:40:09.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.07:40:09.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:09.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:09.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:09.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:09.32#ibcon#enter wrdev, iclass 21, count 2 2006.183.07:40:09.32#ibcon#first serial, iclass 21, count 2 2006.183.07:40:09.32#ibcon#enter sib2, iclass 21, count 2 2006.183.07:40:09.32#ibcon#flushed, iclass 21, count 2 2006.183.07:40:09.32#ibcon#about to write, iclass 21, count 2 2006.183.07:40:09.32#ibcon#wrote, iclass 21, count 2 2006.183.07:40:09.32#ibcon#about to read 3, iclass 21, count 2 2006.183.07:40:09.34#ibcon#read 3, iclass 21, count 2 2006.183.07:40:09.34#ibcon#about to read 4, iclass 21, count 2 2006.183.07:40:09.34#ibcon#read 4, iclass 21, count 2 2006.183.07:40:09.34#ibcon#about to read 5, iclass 21, count 2 2006.183.07:40:09.34#ibcon#read 5, iclass 21, count 2 2006.183.07:40:09.34#ibcon#about to read 6, iclass 21, count 2 2006.183.07:40:09.34#ibcon#read 6, iclass 21, count 2 2006.183.07:40:09.34#ibcon#end of sib2, iclass 21, count 2 2006.183.07:40:09.34#ibcon#*mode == 0, iclass 21, count 2 2006.183.07:40:09.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.07:40:09.34#ibcon#[25=AT05-07\r\n] 2006.183.07:40:09.34#ibcon#*before write, iclass 21, count 2 2006.183.07:40:09.34#ibcon#enter sib2, iclass 21, count 2 2006.183.07:40:09.34#ibcon#flushed, iclass 21, count 2 2006.183.07:40:09.34#ibcon#about to write, iclass 21, count 2 2006.183.07:40:09.34#ibcon#wrote, iclass 21, count 2 2006.183.07:40:09.34#ibcon#about to read 3, iclass 21, count 2 2006.183.07:40:09.37#ibcon#read 3, iclass 21, count 2 2006.183.07:40:09.37#ibcon#about to read 4, iclass 21, count 2 2006.183.07:40:09.37#ibcon#read 4, iclass 21, count 2 2006.183.07:40:09.37#ibcon#about to read 5, iclass 21, count 2 2006.183.07:40:09.37#ibcon#read 5, iclass 21, count 2 2006.183.07:40:09.37#ibcon#about to read 6, iclass 21, count 2 2006.183.07:40:09.37#ibcon#read 6, iclass 21, count 2 2006.183.07:40:09.37#ibcon#end of sib2, iclass 21, count 2 2006.183.07:40:09.37#ibcon#*after write, iclass 21, count 2 2006.183.07:40:09.37#ibcon#*before return 0, iclass 21, count 2 2006.183.07:40:09.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:09.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:09.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.07:40:09.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:09.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:09.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:09.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:09.49#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:40:09.49#ibcon#first serial, iclass 21, count 0 2006.183.07:40:09.49#ibcon#enter sib2, iclass 21, count 0 2006.183.07:40:09.49#ibcon#flushed, iclass 21, count 0 2006.183.07:40:09.49#ibcon#about to write, iclass 21, count 0 2006.183.07:40:09.49#ibcon#wrote, iclass 21, count 0 2006.183.07:40:09.49#ibcon#about to read 3, iclass 21, count 0 2006.183.07:40:09.52#ibcon#read 3, iclass 21, count 0 2006.183.07:40:09.52#ibcon#about to read 4, iclass 21, count 0 2006.183.07:40:09.52#ibcon#read 4, iclass 21, count 0 2006.183.07:40:09.52#ibcon#about to read 5, iclass 21, count 0 2006.183.07:40:09.52#ibcon#read 5, iclass 21, count 0 2006.183.07:40:09.52#ibcon#about to read 6, iclass 21, count 0 2006.183.07:40:09.52#ibcon#read 6, iclass 21, count 0 2006.183.07:40:09.52#ibcon#end of sib2, iclass 21, count 0 2006.183.07:40:09.52#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:40:09.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:40:09.52#ibcon#[25=USB\r\n] 2006.183.07:40:09.52#ibcon#*before write, iclass 21, count 0 2006.183.07:40:09.52#ibcon#enter sib2, iclass 21, count 0 2006.183.07:40:09.52#ibcon#flushed, iclass 21, count 0 2006.183.07:40:09.52#ibcon#about to write, iclass 21, count 0 2006.183.07:40:09.52#ibcon#wrote, iclass 21, count 0 2006.183.07:40:09.52#ibcon#about to read 3, iclass 21, count 0 2006.183.07:40:09.54#ibcon#read 3, iclass 21, count 0 2006.183.07:40:09.54#ibcon#about to read 4, iclass 21, count 0 2006.183.07:40:09.54#ibcon#read 4, iclass 21, count 0 2006.183.07:40:09.54#ibcon#about to read 5, iclass 21, count 0 2006.183.07:40:09.54#ibcon#read 5, iclass 21, count 0 2006.183.07:40:09.54#ibcon#about to read 6, iclass 21, count 0 2006.183.07:40:09.54#ibcon#read 6, iclass 21, count 0 2006.183.07:40:09.54#ibcon#end of sib2, iclass 21, count 0 2006.183.07:40:09.54#ibcon#*after write, iclass 21, count 0 2006.183.07:40:09.54#ibcon#*before return 0, iclass 21, count 0 2006.183.07:40:09.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:09.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:09.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:40:09.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:40:09.54$vc4f8/valo=6,772.99 2006.183.07:40:09.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.07:40:09.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.07:40:09.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:09.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:09.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:09.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:09.54#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:40:09.54#ibcon#first serial, iclass 23, count 0 2006.183.07:40:09.54#ibcon#enter sib2, iclass 23, count 0 2006.183.07:40:09.54#ibcon#flushed, iclass 23, count 0 2006.183.07:40:09.54#ibcon#about to write, iclass 23, count 0 2006.183.07:40:09.54#ibcon#wrote, iclass 23, count 0 2006.183.07:40:09.54#ibcon#about to read 3, iclass 23, count 0 2006.183.07:40:09.56#ibcon#read 3, iclass 23, count 0 2006.183.07:40:09.56#ibcon#about to read 4, iclass 23, count 0 2006.183.07:40:09.56#ibcon#read 4, iclass 23, count 0 2006.183.07:40:09.56#ibcon#about to read 5, iclass 23, count 0 2006.183.07:40:09.56#ibcon#read 5, iclass 23, count 0 2006.183.07:40:09.56#ibcon#about to read 6, iclass 23, count 0 2006.183.07:40:09.56#ibcon#read 6, iclass 23, count 0 2006.183.07:40:09.56#ibcon#end of sib2, iclass 23, count 0 2006.183.07:40:09.56#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:40:09.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:40:09.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:40:09.56#ibcon#*before write, iclass 23, count 0 2006.183.07:40:09.56#ibcon#enter sib2, iclass 23, count 0 2006.183.07:40:09.56#ibcon#flushed, iclass 23, count 0 2006.183.07:40:09.56#ibcon#about to write, iclass 23, count 0 2006.183.07:40:09.56#ibcon#wrote, iclass 23, count 0 2006.183.07:40:09.56#ibcon#about to read 3, iclass 23, count 0 2006.183.07:40:09.60#ibcon#read 3, iclass 23, count 0 2006.183.07:40:09.60#ibcon#about to read 4, iclass 23, count 0 2006.183.07:40:09.60#ibcon#read 4, iclass 23, count 0 2006.183.07:40:09.60#ibcon#about to read 5, iclass 23, count 0 2006.183.07:40:09.60#ibcon#read 5, iclass 23, count 0 2006.183.07:40:09.60#ibcon#about to read 6, iclass 23, count 0 2006.183.07:40:09.60#ibcon#read 6, iclass 23, count 0 2006.183.07:40:09.60#ibcon#end of sib2, iclass 23, count 0 2006.183.07:40:09.60#ibcon#*after write, iclass 23, count 0 2006.183.07:40:09.60#ibcon#*before return 0, iclass 23, count 0 2006.183.07:40:09.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:09.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:09.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:40:09.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:40:09.60$vc4f8/va=6,6 2006.183.07:40:09.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.07:40:09.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.07:40:09.60#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:09.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:40:09.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:40:09.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:40:09.66#ibcon#enter wrdev, iclass 25, count 2 2006.183.07:40:09.66#ibcon#first serial, iclass 25, count 2 2006.183.07:40:09.66#ibcon#enter sib2, iclass 25, count 2 2006.183.07:40:09.66#ibcon#flushed, iclass 25, count 2 2006.183.07:40:09.66#ibcon#about to write, iclass 25, count 2 2006.183.07:40:09.66#ibcon#wrote, iclass 25, count 2 2006.183.07:40:09.66#ibcon#about to read 3, iclass 25, count 2 2006.183.07:40:09.68#ibcon#read 3, iclass 25, count 2 2006.183.07:40:09.68#ibcon#about to read 4, iclass 25, count 2 2006.183.07:40:09.68#ibcon#read 4, iclass 25, count 2 2006.183.07:40:09.68#ibcon#about to read 5, iclass 25, count 2 2006.183.07:40:09.68#ibcon#read 5, iclass 25, count 2 2006.183.07:40:09.68#ibcon#about to read 6, iclass 25, count 2 2006.183.07:40:09.68#ibcon#read 6, iclass 25, count 2 2006.183.07:40:09.68#ibcon#end of sib2, iclass 25, count 2 2006.183.07:40:09.68#ibcon#*mode == 0, iclass 25, count 2 2006.183.07:40:09.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.07:40:09.68#ibcon#[25=AT06-06\r\n] 2006.183.07:40:09.68#ibcon#*before write, iclass 25, count 2 2006.183.07:40:09.68#ibcon#enter sib2, iclass 25, count 2 2006.183.07:40:09.68#ibcon#flushed, iclass 25, count 2 2006.183.07:40:09.68#ibcon#about to write, iclass 25, count 2 2006.183.07:40:09.68#ibcon#wrote, iclass 25, count 2 2006.183.07:40:09.68#ibcon#about to read 3, iclass 25, count 2 2006.183.07:40:09.71#ibcon#read 3, iclass 25, count 2 2006.183.07:40:09.71#ibcon#about to read 4, iclass 25, count 2 2006.183.07:40:09.71#ibcon#read 4, iclass 25, count 2 2006.183.07:40:09.71#ibcon#about to read 5, iclass 25, count 2 2006.183.07:40:09.71#ibcon#read 5, iclass 25, count 2 2006.183.07:40:09.71#ibcon#about to read 6, iclass 25, count 2 2006.183.07:40:09.71#ibcon#read 6, iclass 25, count 2 2006.183.07:40:09.71#ibcon#end of sib2, iclass 25, count 2 2006.183.07:40:09.71#ibcon#*after write, iclass 25, count 2 2006.183.07:40:09.71#ibcon#*before return 0, iclass 25, count 2 2006.183.07:40:09.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:40:09.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:40:09.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.07:40:09.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:09.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:40:09.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:40:09.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:40:09.83#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:40:09.83#ibcon#first serial, iclass 25, count 0 2006.183.07:40:09.83#ibcon#enter sib2, iclass 25, count 0 2006.183.07:40:09.83#ibcon#flushed, iclass 25, count 0 2006.183.07:40:09.83#ibcon#about to write, iclass 25, count 0 2006.183.07:40:09.83#ibcon#wrote, iclass 25, count 0 2006.183.07:40:09.83#ibcon#about to read 3, iclass 25, count 0 2006.183.07:40:09.85#ibcon#read 3, iclass 25, count 0 2006.183.07:40:09.85#ibcon#about to read 4, iclass 25, count 0 2006.183.07:40:09.85#ibcon#read 4, iclass 25, count 0 2006.183.07:40:09.85#ibcon#about to read 5, iclass 25, count 0 2006.183.07:40:09.85#ibcon#read 5, iclass 25, count 0 2006.183.07:40:09.85#ibcon#about to read 6, iclass 25, count 0 2006.183.07:40:09.85#ibcon#read 6, iclass 25, count 0 2006.183.07:40:09.85#ibcon#end of sib2, iclass 25, count 0 2006.183.07:40:09.85#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:40:09.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:40:09.85#ibcon#[25=USB\r\n] 2006.183.07:40:09.85#ibcon#*before write, iclass 25, count 0 2006.183.07:40:09.85#ibcon#enter sib2, iclass 25, count 0 2006.183.07:40:09.85#ibcon#flushed, iclass 25, count 0 2006.183.07:40:09.85#ibcon#about to write, iclass 25, count 0 2006.183.07:40:09.85#ibcon#wrote, iclass 25, count 0 2006.183.07:40:09.85#ibcon#about to read 3, iclass 25, count 0 2006.183.07:40:09.88#ibcon#read 3, iclass 25, count 0 2006.183.07:40:09.88#ibcon#about to read 4, iclass 25, count 0 2006.183.07:40:09.88#ibcon#read 4, iclass 25, count 0 2006.183.07:40:09.88#ibcon#about to read 5, iclass 25, count 0 2006.183.07:40:09.88#ibcon#read 5, iclass 25, count 0 2006.183.07:40:09.88#ibcon#about to read 6, iclass 25, count 0 2006.183.07:40:09.88#ibcon#read 6, iclass 25, count 0 2006.183.07:40:09.88#ibcon#end of sib2, iclass 25, count 0 2006.183.07:40:09.88#ibcon#*after write, iclass 25, count 0 2006.183.07:40:09.88#ibcon#*before return 0, iclass 25, count 0 2006.183.07:40:09.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:40:09.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:40:09.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:40:09.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:40:09.88$vc4f8/valo=7,832.99 2006.183.07:40:09.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.07:40:09.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.07:40:09.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:09.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:40:09.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:40:09.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:40:09.88#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:40:09.88#ibcon#first serial, iclass 27, count 0 2006.183.07:40:09.88#ibcon#enter sib2, iclass 27, count 0 2006.183.07:40:09.88#ibcon#flushed, iclass 27, count 0 2006.183.07:40:09.88#ibcon#about to write, iclass 27, count 0 2006.183.07:40:09.88#ibcon#wrote, iclass 27, count 0 2006.183.07:40:09.88#ibcon#about to read 3, iclass 27, count 0 2006.183.07:40:09.90#ibcon#read 3, iclass 27, count 0 2006.183.07:40:09.90#ibcon#about to read 4, iclass 27, count 0 2006.183.07:40:09.90#ibcon#read 4, iclass 27, count 0 2006.183.07:40:09.90#ibcon#about to read 5, iclass 27, count 0 2006.183.07:40:09.90#ibcon#read 5, iclass 27, count 0 2006.183.07:40:09.90#ibcon#about to read 6, iclass 27, count 0 2006.183.07:40:09.90#ibcon#read 6, iclass 27, count 0 2006.183.07:40:09.90#ibcon#end of sib2, iclass 27, count 0 2006.183.07:40:09.90#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:40:09.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:40:09.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:40:09.90#ibcon#*before write, iclass 27, count 0 2006.183.07:40:09.90#ibcon#enter sib2, iclass 27, count 0 2006.183.07:40:09.90#ibcon#flushed, iclass 27, count 0 2006.183.07:40:09.90#ibcon#about to write, iclass 27, count 0 2006.183.07:40:09.90#ibcon#wrote, iclass 27, count 0 2006.183.07:40:09.90#ibcon#about to read 3, iclass 27, count 0 2006.183.07:40:09.94#ibcon#read 3, iclass 27, count 0 2006.183.07:40:09.94#ibcon#about to read 4, iclass 27, count 0 2006.183.07:40:09.94#ibcon#read 4, iclass 27, count 0 2006.183.07:40:09.94#ibcon#about to read 5, iclass 27, count 0 2006.183.07:40:09.94#ibcon#read 5, iclass 27, count 0 2006.183.07:40:09.94#ibcon#about to read 6, iclass 27, count 0 2006.183.07:40:09.94#ibcon#read 6, iclass 27, count 0 2006.183.07:40:09.94#ibcon#end of sib2, iclass 27, count 0 2006.183.07:40:09.94#ibcon#*after write, iclass 27, count 0 2006.183.07:40:09.94#ibcon#*before return 0, iclass 27, count 0 2006.183.07:40:09.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:40:09.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:40:09.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:40:09.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:40:09.94$vc4f8/va=7,6 2006.183.07:40:09.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.07:40:09.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.07:40:09.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:09.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:40:10.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:40:10.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:40:10.00#ibcon#enter wrdev, iclass 29, count 2 2006.183.07:40:10.00#ibcon#first serial, iclass 29, count 2 2006.183.07:40:10.00#ibcon#enter sib2, iclass 29, count 2 2006.183.07:40:10.00#ibcon#flushed, iclass 29, count 2 2006.183.07:40:10.00#ibcon#about to write, iclass 29, count 2 2006.183.07:40:10.00#ibcon#wrote, iclass 29, count 2 2006.183.07:40:10.00#ibcon#about to read 3, iclass 29, count 2 2006.183.07:40:10.02#ibcon#read 3, iclass 29, count 2 2006.183.07:40:10.02#ibcon#about to read 4, iclass 29, count 2 2006.183.07:40:10.02#ibcon#read 4, iclass 29, count 2 2006.183.07:40:10.02#ibcon#about to read 5, iclass 29, count 2 2006.183.07:40:10.02#ibcon#read 5, iclass 29, count 2 2006.183.07:40:10.02#ibcon#about to read 6, iclass 29, count 2 2006.183.07:40:10.02#ibcon#read 6, iclass 29, count 2 2006.183.07:40:10.02#ibcon#end of sib2, iclass 29, count 2 2006.183.07:40:10.02#ibcon#*mode == 0, iclass 29, count 2 2006.183.07:40:10.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.07:40:10.02#ibcon#[25=AT07-06\r\n] 2006.183.07:40:10.02#ibcon#*before write, iclass 29, count 2 2006.183.07:40:10.02#ibcon#enter sib2, iclass 29, count 2 2006.183.07:40:10.02#ibcon#flushed, iclass 29, count 2 2006.183.07:40:10.02#ibcon#about to write, iclass 29, count 2 2006.183.07:40:10.02#ibcon#wrote, iclass 29, count 2 2006.183.07:40:10.02#ibcon#about to read 3, iclass 29, count 2 2006.183.07:40:10.05#ibcon#read 3, iclass 29, count 2 2006.183.07:40:10.05#ibcon#about to read 4, iclass 29, count 2 2006.183.07:40:10.05#ibcon#read 4, iclass 29, count 2 2006.183.07:40:10.05#ibcon#about to read 5, iclass 29, count 2 2006.183.07:40:10.05#ibcon#read 5, iclass 29, count 2 2006.183.07:40:10.05#ibcon#about to read 6, iclass 29, count 2 2006.183.07:40:10.05#ibcon#read 6, iclass 29, count 2 2006.183.07:40:10.05#ibcon#end of sib2, iclass 29, count 2 2006.183.07:40:10.05#ibcon#*after write, iclass 29, count 2 2006.183.07:40:10.05#ibcon#*before return 0, iclass 29, count 2 2006.183.07:40:10.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:40:10.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:40:10.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.07:40:10.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:10.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:40:10.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:40:10.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:40:10.17#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:40:10.17#ibcon#first serial, iclass 29, count 0 2006.183.07:40:10.17#ibcon#enter sib2, iclass 29, count 0 2006.183.07:40:10.17#ibcon#flushed, iclass 29, count 0 2006.183.07:40:10.17#ibcon#about to write, iclass 29, count 0 2006.183.07:40:10.17#ibcon#wrote, iclass 29, count 0 2006.183.07:40:10.17#ibcon#about to read 3, iclass 29, count 0 2006.183.07:40:10.19#ibcon#read 3, iclass 29, count 0 2006.183.07:40:10.19#ibcon#about to read 4, iclass 29, count 0 2006.183.07:40:10.19#ibcon#read 4, iclass 29, count 0 2006.183.07:40:10.19#ibcon#about to read 5, iclass 29, count 0 2006.183.07:40:10.19#ibcon#read 5, iclass 29, count 0 2006.183.07:40:10.19#ibcon#about to read 6, iclass 29, count 0 2006.183.07:40:10.19#ibcon#read 6, iclass 29, count 0 2006.183.07:40:10.19#ibcon#end of sib2, iclass 29, count 0 2006.183.07:40:10.19#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:40:10.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:40:10.19#ibcon#[25=USB\r\n] 2006.183.07:40:10.19#ibcon#*before write, iclass 29, count 0 2006.183.07:40:10.19#ibcon#enter sib2, iclass 29, count 0 2006.183.07:40:10.19#ibcon#flushed, iclass 29, count 0 2006.183.07:40:10.19#ibcon#about to write, iclass 29, count 0 2006.183.07:40:10.19#ibcon#wrote, iclass 29, count 0 2006.183.07:40:10.19#ibcon#about to read 3, iclass 29, count 0 2006.183.07:40:10.22#ibcon#read 3, iclass 29, count 0 2006.183.07:40:10.22#ibcon#about to read 4, iclass 29, count 0 2006.183.07:40:10.22#ibcon#read 4, iclass 29, count 0 2006.183.07:40:10.22#ibcon#about to read 5, iclass 29, count 0 2006.183.07:40:10.22#ibcon#read 5, iclass 29, count 0 2006.183.07:40:10.22#ibcon#about to read 6, iclass 29, count 0 2006.183.07:40:10.22#ibcon#read 6, iclass 29, count 0 2006.183.07:40:10.22#ibcon#end of sib2, iclass 29, count 0 2006.183.07:40:10.22#ibcon#*after write, iclass 29, count 0 2006.183.07:40:10.22#ibcon#*before return 0, iclass 29, count 0 2006.183.07:40:10.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:40:10.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:40:10.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:40:10.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:40:10.22$vc4f8/valo=8,852.99 2006.183.07:40:10.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.07:40:10.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.07:40:10.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:10.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:40:10.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:40:10.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:40:10.22#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:40:10.22#ibcon#first serial, iclass 31, count 0 2006.183.07:40:10.22#ibcon#enter sib2, iclass 31, count 0 2006.183.07:40:10.22#ibcon#flushed, iclass 31, count 0 2006.183.07:40:10.22#ibcon#about to write, iclass 31, count 0 2006.183.07:40:10.22#ibcon#wrote, iclass 31, count 0 2006.183.07:40:10.22#ibcon#about to read 3, iclass 31, count 0 2006.183.07:40:10.24#ibcon#read 3, iclass 31, count 0 2006.183.07:40:10.24#ibcon#about to read 4, iclass 31, count 0 2006.183.07:40:10.24#ibcon#read 4, iclass 31, count 0 2006.183.07:40:10.24#ibcon#about to read 5, iclass 31, count 0 2006.183.07:40:10.24#ibcon#read 5, iclass 31, count 0 2006.183.07:40:10.24#ibcon#about to read 6, iclass 31, count 0 2006.183.07:40:10.24#ibcon#read 6, iclass 31, count 0 2006.183.07:40:10.24#ibcon#end of sib2, iclass 31, count 0 2006.183.07:40:10.24#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:40:10.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:40:10.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:40:10.24#ibcon#*before write, iclass 31, count 0 2006.183.07:40:10.24#ibcon#enter sib2, iclass 31, count 0 2006.183.07:40:10.24#ibcon#flushed, iclass 31, count 0 2006.183.07:40:10.24#ibcon#about to write, iclass 31, count 0 2006.183.07:40:10.24#ibcon#wrote, iclass 31, count 0 2006.183.07:40:10.24#ibcon#about to read 3, iclass 31, count 0 2006.183.07:40:10.28#ibcon#read 3, iclass 31, count 0 2006.183.07:40:10.28#ibcon#about to read 4, iclass 31, count 0 2006.183.07:40:10.28#ibcon#read 4, iclass 31, count 0 2006.183.07:40:10.28#ibcon#about to read 5, iclass 31, count 0 2006.183.07:40:10.28#ibcon#read 5, iclass 31, count 0 2006.183.07:40:10.28#ibcon#about to read 6, iclass 31, count 0 2006.183.07:40:10.28#ibcon#read 6, iclass 31, count 0 2006.183.07:40:10.28#ibcon#end of sib2, iclass 31, count 0 2006.183.07:40:10.28#ibcon#*after write, iclass 31, count 0 2006.183.07:40:10.28#ibcon#*before return 0, iclass 31, count 0 2006.183.07:40:10.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:40:10.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:40:10.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:40:10.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:40:10.28$vc4f8/va=8,7 2006.183.07:40:10.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.07:40:10.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.07:40:10.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:10.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:40:10.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:40:10.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:40:10.34#ibcon#enter wrdev, iclass 33, count 2 2006.183.07:40:10.34#ibcon#first serial, iclass 33, count 2 2006.183.07:40:10.34#ibcon#enter sib2, iclass 33, count 2 2006.183.07:40:10.34#ibcon#flushed, iclass 33, count 2 2006.183.07:40:10.34#ibcon#about to write, iclass 33, count 2 2006.183.07:40:10.34#ibcon#wrote, iclass 33, count 2 2006.183.07:40:10.34#ibcon#about to read 3, iclass 33, count 2 2006.183.07:40:10.36#ibcon#read 3, iclass 33, count 2 2006.183.07:40:10.36#ibcon#about to read 4, iclass 33, count 2 2006.183.07:40:10.36#ibcon#read 4, iclass 33, count 2 2006.183.07:40:10.36#ibcon#about to read 5, iclass 33, count 2 2006.183.07:40:10.36#ibcon#read 5, iclass 33, count 2 2006.183.07:40:10.36#ibcon#about to read 6, iclass 33, count 2 2006.183.07:40:10.36#ibcon#read 6, iclass 33, count 2 2006.183.07:40:10.36#ibcon#end of sib2, iclass 33, count 2 2006.183.07:40:10.36#ibcon#*mode == 0, iclass 33, count 2 2006.183.07:40:10.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.07:40:10.36#ibcon#[25=AT08-07\r\n] 2006.183.07:40:10.36#ibcon#*before write, iclass 33, count 2 2006.183.07:40:10.36#ibcon#enter sib2, iclass 33, count 2 2006.183.07:40:10.36#ibcon#flushed, iclass 33, count 2 2006.183.07:40:10.36#ibcon#about to write, iclass 33, count 2 2006.183.07:40:10.36#ibcon#wrote, iclass 33, count 2 2006.183.07:40:10.36#ibcon#about to read 3, iclass 33, count 2 2006.183.07:40:10.39#ibcon#read 3, iclass 33, count 2 2006.183.07:40:10.39#ibcon#about to read 4, iclass 33, count 2 2006.183.07:40:10.39#ibcon#read 4, iclass 33, count 2 2006.183.07:40:10.39#ibcon#about to read 5, iclass 33, count 2 2006.183.07:40:10.39#ibcon#read 5, iclass 33, count 2 2006.183.07:40:10.39#ibcon#about to read 6, iclass 33, count 2 2006.183.07:40:10.39#ibcon#read 6, iclass 33, count 2 2006.183.07:40:10.39#ibcon#end of sib2, iclass 33, count 2 2006.183.07:40:10.39#ibcon#*after write, iclass 33, count 2 2006.183.07:40:10.39#ibcon#*before return 0, iclass 33, count 2 2006.183.07:40:10.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:40:10.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:40:10.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.07:40:10.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:10.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:40:10.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:40:10.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:40:10.51#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:40:10.51#ibcon#first serial, iclass 33, count 0 2006.183.07:40:10.51#ibcon#enter sib2, iclass 33, count 0 2006.183.07:40:10.51#ibcon#flushed, iclass 33, count 0 2006.183.07:40:10.51#ibcon#about to write, iclass 33, count 0 2006.183.07:40:10.51#ibcon#wrote, iclass 33, count 0 2006.183.07:40:10.51#ibcon#about to read 3, iclass 33, count 0 2006.183.07:40:10.53#ibcon#read 3, iclass 33, count 0 2006.183.07:40:10.53#ibcon#about to read 4, iclass 33, count 0 2006.183.07:40:10.53#ibcon#read 4, iclass 33, count 0 2006.183.07:40:10.53#ibcon#about to read 5, iclass 33, count 0 2006.183.07:40:10.53#ibcon#read 5, iclass 33, count 0 2006.183.07:40:10.53#ibcon#about to read 6, iclass 33, count 0 2006.183.07:40:10.53#ibcon#read 6, iclass 33, count 0 2006.183.07:40:10.53#ibcon#end of sib2, iclass 33, count 0 2006.183.07:40:10.53#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:40:10.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:40:10.53#ibcon#[25=USB\r\n] 2006.183.07:40:10.53#ibcon#*before write, iclass 33, count 0 2006.183.07:40:10.53#ibcon#enter sib2, iclass 33, count 0 2006.183.07:40:10.53#ibcon#flushed, iclass 33, count 0 2006.183.07:40:10.53#ibcon#about to write, iclass 33, count 0 2006.183.07:40:10.53#ibcon#wrote, iclass 33, count 0 2006.183.07:40:10.53#ibcon#about to read 3, iclass 33, count 0 2006.183.07:40:10.56#ibcon#read 3, iclass 33, count 0 2006.183.07:40:10.56#ibcon#about to read 4, iclass 33, count 0 2006.183.07:40:10.56#ibcon#read 4, iclass 33, count 0 2006.183.07:40:10.56#ibcon#about to read 5, iclass 33, count 0 2006.183.07:40:10.56#ibcon#read 5, iclass 33, count 0 2006.183.07:40:10.56#ibcon#about to read 6, iclass 33, count 0 2006.183.07:40:10.56#ibcon#read 6, iclass 33, count 0 2006.183.07:40:10.56#ibcon#end of sib2, iclass 33, count 0 2006.183.07:40:10.56#ibcon#*after write, iclass 33, count 0 2006.183.07:40:10.56#ibcon#*before return 0, iclass 33, count 0 2006.183.07:40:10.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:40:10.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:40:10.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:40:10.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:40:10.56$vc4f8/vblo=1,632.99 2006.183.07:40:10.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.07:40:10.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.07:40:10.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:10.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:40:10.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:40:10.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:40:10.56#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:40:10.56#ibcon#first serial, iclass 35, count 0 2006.183.07:40:10.56#ibcon#enter sib2, iclass 35, count 0 2006.183.07:40:10.56#ibcon#flushed, iclass 35, count 0 2006.183.07:40:10.56#ibcon#about to write, iclass 35, count 0 2006.183.07:40:10.56#ibcon#wrote, iclass 35, count 0 2006.183.07:40:10.56#ibcon#about to read 3, iclass 35, count 0 2006.183.07:40:10.58#ibcon#read 3, iclass 35, count 0 2006.183.07:40:10.58#ibcon#about to read 4, iclass 35, count 0 2006.183.07:40:10.58#ibcon#read 4, iclass 35, count 0 2006.183.07:40:10.58#ibcon#about to read 5, iclass 35, count 0 2006.183.07:40:10.58#ibcon#read 5, iclass 35, count 0 2006.183.07:40:10.58#ibcon#about to read 6, iclass 35, count 0 2006.183.07:40:10.58#ibcon#read 6, iclass 35, count 0 2006.183.07:40:10.58#ibcon#end of sib2, iclass 35, count 0 2006.183.07:40:10.58#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:40:10.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:40:10.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:40:10.58#ibcon#*before write, iclass 35, count 0 2006.183.07:40:10.58#ibcon#enter sib2, iclass 35, count 0 2006.183.07:40:10.58#ibcon#flushed, iclass 35, count 0 2006.183.07:40:10.58#ibcon#about to write, iclass 35, count 0 2006.183.07:40:10.58#ibcon#wrote, iclass 35, count 0 2006.183.07:40:10.58#ibcon#about to read 3, iclass 35, count 0 2006.183.07:40:10.62#ibcon#read 3, iclass 35, count 0 2006.183.07:40:10.62#ibcon#about to read 4, iclass 35, count 0 2006.183.07:40:10.62#ibcon#read 4, iclass 35, count 0 2006.183.07:40:10.62#ibcon#about to read 5, iclass 35, count 0 2006.183.07:40:10.62#ibcon#read 5, iclass 35, count 0 2006.183.07:40:10.62#ibcon#about to read 6, iclass 35, count 0 2006.183.07:40:10.62#ibcon#read 6, iclass 35, count 0 2006.183.07:40:10.62#ibcon#end of sib2, iclass 35, count 0 2006.183.07:40:10.62#ibcon#*after write, iclass 35, count 0 2006.183.07:40:10.62#ibcon#*before return 0, iclass 35, count 0 2006.183.07:40:10.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:40:10.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:40:10.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:40:10.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:40:10.62$vc4f8/vb=1,4 2006.183.07:40:10.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.07:40:10.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.07:40:10.62#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:10.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:40:10.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:40:10.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:40:10.62#ibcon#enter wrdev, iclass 37, count 2 2006.183.07:40:10.62#ibcon#first serial, iclass 37, count 2 2006.183.07:40:10.62#ibcon#enter sib2, iclass 37, count 2 2006.183.07:40:10.62#ibcon#flushed, iclass 37, count 2 2006.183.07:40:10.62#ibcon#about to write, iclass 37, count 2 2006.183.07:40:10.62#ibcon#wrote, iclass 37, count 2 2006.183.07:40:10.62#ibcon#about to read 3, iclass 37, count 2 2006.183.07:40:10.64#ibcon#read 3, iclass 37, count 2 2006.183.07:40:10.64#ibcon#about to read 4, iclass 37, count 2 2006.183.07:40:10.64#ibcon#read 4, iclass 37, count 2 2006.183.07:40:10.64#ibcon#about to read 5, iclass 37, count 2 2006.183.07:40:10.64#ibcon#read 5, iclass 37, count 2 2006.183.07:40:10.64#ibcon#about to read 6, iclass 37, count 2 2006.183.07:40:10.64#ibcon#read 6, iclass 37, count 2 2006.183.07:40:10.64#ibcon#end of sib2, iclass 37, count 2 2006.183.07:40:10.64#ibcon#*mode == 0, iclass 37, count 2 2006.183.07:40:10.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.07:40:10.64#ibcon#[27=AT01-04\r\n] 2006.183.07:40:10.64#ibcon#*before write, iclass 37, count 2 2006.183.07:40:10.64#ibcon#enter sib2, iclass 37, count 2 2006.183.07:40:10.64#ibcon#flushed, iclass 37, count 2 2006.183.07:40:10.64#ibcon#about to write, iclass 37, count 2 2006.183.07:40:10.64#ibcon#wrote, iclass 37, count 2 2006.183.07:40:10.64#ibcon#about to read 3, iclass 37, count 2 2006.183.07:40:10.67#ibcon#read 3, iclass 37, count 2 2006.183.07:40:10.67#ibcon#about to read 4, iclass 37, count 2 2006.183.07:40:10.67#ibcon#read 4, iclass 37, count 2 2006.183.07:40:10.67#ibcon#about to read 5, iclass 37, count 2 2006.183.07:40:10.67#ibcon#read 5, iclass 37, count 2 2006.183.07:40:10.67#ibcon#about to read 6, iclass 37, count 2 2006.183.07:40:10.67#ibcon#read 6, iclass 37, count 2 2006.183.07:40:10.67#ibcon#end of sib2, iclass 37, count 2 2006.183.07:40:10.67#ibcon#*after write, iclass 37, count 2 2006.183.07:40:10.67#ibcon#*before return 0, iclass 37, count 2 2006.183.07:40:10.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:40:10.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:40:10.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.07:40:10.67#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:10.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:40:10.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:40:10.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:40:10.79#ibcon#enter wrdev, iclass 37, count 0 2006.183.07:40:10.79#ibcon#first serial, iclass 37, count 0 2006.183.07:40:10.79#ibcon#enter sib2, iclass 37, count 0 2006.183.07:40:10.79#ibcon#flushed, iclass 37, count 0 2006.183.07:40:10.79#ibcon#about to write, iclass 37, count 0 2006.183.07:40:10.79#ibcon#wrote, iclass 37, count 0 2006.183.07:40:10.79#ibcon#about to read 3, iclass 37, count 0 2006.183.07:40:10.81#ibcon#read 3, iclass 37, count 0 2006.183.07:40:10.81#ibcon#about to read 4, iclass 37, count 0 2006.183.07:40:10.81#ibcon#read 4, iclass 37, count 0 2006.183.07:40:10.81#ibcon#about to read 5, iclass 37, count 0 2006.183.07:40:10.81#ibcon#read 5, iclass 37, count 0 2006.183.07:40:10.81#ibcon#about to read 6, iclass 37, count 0 2006.183.07:40:10.81#ibcon#read 6, iclass 37, count 0 2006.183.07:40:10.81#ibcon#end of sib2, iclass 37, count 0 2006.183.07:40:10.81#ibcon#*mode == 0, iclass 37, count 0 2006.183.07:40:10.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.07:40:10.81#ibcon#[27=USB\r\n] 2006.183.07:40:10.81#ibcon#*before write, iclass 37, count 0 2006.183.07:40:10.81#ibcon#enter sib2, iclass 37, count 0 2006.183.07:40:10.81#ibcon#flushed, iclass 37, count 0 2006.183.07:40:10.81#ibcon#about to write, iclass 37, count 0 2006.183.07:40:10.81#ibcon#wrote, iclass 37, count 0 2006.183.07:40:10.81#ibcon#about to read 3, iclass 37, count 0 2006.183.07:40:10.84#ibcon#read 3, iclass 37, count 0 2006.183.07:40:10.84#ibcon#about to read 4, iclass 37, count 0 2006.183.07:40:10.84#ibcon#read 4, iclass 37, count 0 2006.183.07:40:10.84#ibcon#about to read 5, iclass 37, count 0 2006.183.07:40:10.84#ibcon#read 5, iclass 37, count 0 2006.183.07:40:10.84#ibcon#about to read 6, iclass 37, count 0 2006.183.07:40:10.84#ibcon#read 6, iclass 37, count 0 2006.183.07:40:10.84#ibcon#end of sib2, iclass 37, count 0 2006.183.07:40:10.84#ibcon#*after write, iclass 37, count 0 2006.183.07:40:10.84#ibcon#*before return 0, iclass 37, count 0 2006.183.07:40:10.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:40:10.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:40:10.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.07:40:10.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.07:40:10.84$vc4f8/vblo=2,640.99 2006.183.07:40:10.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.07:40:10.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.07:40:10.84#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:10.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:10.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:10.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:10.84#ibcon#enter wrdev, iclass 39, count 0 2006.183.07:40:10.84#ibcon#first serial, iclass 39, count 0 2006.183.07:40:10.84#ibcon#enter sib2, iclass 39, count 0 2006.183.07:40:10.84#ibcon#flushed, iclass 39, count 0 2006.183.07:40:10.84#ibcon#about to write, iclass 39, count 0 2006.183.07:40:10.84#ibcon#wrote, iclass 39, count 0 2006.183.07:40:10.84#ibcon#about to read 3, iclass 39, count 0 2006.183.07:40:10.86#ibcon#read 3, iclass 39, count 0 2006.183.07:40:10.86#ibcon#about to read 4, iclass 39, count 0 2006.183.07:40:10.86#ibcon#read 4, iclass 39, count 0 2006.183.07:40:10.86#ibcon#about to read 5, iclass 39, count 0 2006.183.07:40:10.86#ibcon#read 5, iclass 39, count 0 2006.183.07:40:10.86#ibcon#about to read 6, iclass 39, count 0 2006.183.07:40:10.86#ibcon#read 6, iclass 39, count 0 2006.183.07:40:10.86#ibcon#end of sib2, iclass 39, count 0 2006.183.07:40:10.86#ibcon#*mode == 0, iclass 39, count 0 2006.183.07:40:10.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.07:40:10.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:40:10.86#ibcon#*before write, iclass 39, count 0 2006.183.07:40:10.86#ibcon#enter sib2, iclass 39, count 0 2006.183.07:40:10.86#ibcon#flushed, iclass 39, count 0 2006.183.07:40:10.86#ibcon#about to write, iclass 39, count 0 2006.183.07:40:10.86#ibcon#wrote, iclass 39, count 0 2006.183.07:40:10.86#ibcon#about to read 3, iclass 39, count 0 2006.183.07:40:10.90#ibcon#read 3, iclass 39, count 0 2006.183.07:40:10.90#ibcon#about to read 4, iclass 39, count 0 2006.183.07:40:10.90#ibcon#read 4, iclass 39, count 0 2006.183.07:40:10.90#ibcon#about to read 5, iclass 39, count 0 2006.183.07:40:10.90#ibcon#read 5, iclass 39, count 0 2006.183.07:40:10.90#ibcon#about to read 6, iclass 39, count 0 2006.183.07:40:10.90#ibcon#read 6, iclass 39, count 0 2006.183.07:40:10.90#ibcon#end of sib2, iclass 39, count 0 2006.183.07:40:10.90#ibcon#*after write, iclass 39, count 0 2006.183.07:40:10.90#ibcon#*before return 0, iclass 39, count 0 2006.183.07:40:10.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:10.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:40:10.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.07:40:10.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.07:40:10.90$vc4f8/vb=2,4 2006.183.07:40:10.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.183.07:40:10.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.183.07:40:10.90#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:10.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:10.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:10.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:10.96#ibcon#enter wrdev, iclass 3, count 2 2006.183.07:40:10.96#ibcon#first serial, iclass 3, count 2 2006.183.07:40:10.96#ibcon#enter sib2, iclass 3, count 2 2006.183.07:40:10.96#ibcon#flushed, iclass 3, count 2 2006.183.07:40:10.96#ibcon#about to write, iclass 3, count 2 2006.183.07:40:10.96#ibcon#wrote, iclass 3, count 2 2006.183.07:40:10.96#ibcon#about to read 3, iclass 3, count 2 2006.183.07:40:10.98#ibcon#read 3, iclass 3, count 2 2006.183.07:40:10.98#ibcon#about to read 4, iclass 3, count 2 2006.183.07:40:10.98#ibcon#read 4, iclass 3, count 2 2006.183.07:40:10.98#ibcon#about to read 5, iclass 3, count 2 2006.183.07:40:10.98#ibcon#read 5, iclass 3, count 2 2006.183.07:40:10.98#ibcon#about to read 6, iclass 3, count 2 2006.183.07:40:10.98#ibcon#read 6, iclass 3, count 2 2006.183.07:40:10.98#ibcon#end of sib2, iclass 3, count 2 2006.183.07:40:10.98#ibcon#*mode == 0, iclass 3, count 2 2006.183.07:40:10.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.183.07:40:10.98#ibcon#[27=AT02-04\r\n] 2006.183.07:40:10.98#ibcon#*before write, iclass 3, count 2 2006.183.07:40:10.98#ibcon#enter sib2, iclass 3, count 2 2006.183.07:40:10.98#ibcon#flushed, iclass 3, count 2 2006.183.07:40:10.98#ibcon#about to write, iclass 3, count 2 2006.183.07:40:10.98#ibcon#wrote, iclass 3, count 2 2006.183.07:40:10.98#ibcon#about to read 3, iclass 3, count 2 2006.183.07:40:11.01#ibcon#read 3, iclass 3, count 2 2006.183.07:40:11.01#ibcon#about to read 4, iclass 3, count 2 2006.183.07:40:11.01#ibcon#read 4, iclass 3, count 2 2006.183.07:40:11.01#ibcon#about to read 5, iclass 3, count 2 2006.183.07:40:11.01#ibcon#read 5, iclass 3, count 2 2006.183.07:40:11.01#ibcon#about to read 6, iclass 3, count 2 2006.183.07:40:11.01#ibcon#read 6, iclass 3, count 2 2006.183.07:40:11.01#ibcon#end of sib2, iclass 3, count 2 2006.183.07:40:11.01#ibcon#*after write, iclass 3, count 2 2006.183.07:40:11.01#ibcon#*before return 0, iclass 3, count 2 2006.183.07:40:11.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:11.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.183.07:40:11.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.183.07:40:11.01#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:11.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:11.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:11.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:11.13#ibcon#enter wrdev, iclass 3, count 0 2006.183.07:40:11.13#ibcon#first serial, iclass 3, count 0 2006.183.07:40:11.13#ibcon#enter sib2, iclass 3, count 0 2006.183.07:40:11.13#ibcon#flushed, iclass 3, count 0 2006.183.07:40:11.13#ibcon#about to write, iclass 3, count 0 2006.183.07:40:11.13#ibcon#wrote, iclass 3, count 0 2006.183.07:40:11.13#ibcon#about to read 3, iclass 3, count 0 2006.183.07:40:11.15#ibcon#read 3, iclass 3, count 0 2006.183.07:40:11.15#ibcon#about to read 4, iclass 3, count 0 2006.183.07:40:11.15#ibcon#read 4, iclass 3, count 0 2006.183.07:40:11.15#ibcon#about to read 5, iclass 3, count 0 2006.183.07:40:11.15#ibcon#read 5, iclass 3, count 0 2006.183.07:40:11.15#ibcon#about to read 6, iclass 3, count 0 2006.183.07:40:11.15#ibcon#read 6, iclass 3, count 0 2006.183.07:40:11.15#ibcon#end of sib2, iclass 3, count 0 2006.183.07:40:11.15#ibcon#*mode == 0, iclass 3, count 0 2006.183.07:40:11.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.07:40:11.15#ibcon#[27=USB\r\n] 2006.183.07:40:11.15#ibcon#*before write, iclass 3, count 0 2006.183.07:40:11.15#ibcon#enter sib2, iclass 3, count 0 2006.183.07:40:11.15#ibcon#flushed, iclass 3, count 0 2006.183.07:40:11.15#ibcon#about to write, iclass 3, count 0 2006.183.07:40:11.15#ibcon#wrote, iclass 3, count 0 2006.183.07:40:11.15#ibcon#about to read 3, iclass 3, count 0 2006.183.07:40:11.18#ibcon#read 3, iclass 3, count 0 2006.183.07:40:11.18#ibcon#about to read 4, iclass 3, count 0 2006.183.07:40:11.18#ibcon#read 4, iclass 3, count 0 2006.183.07:40:11.18#ibcon#about to read 5, iclass 3, count 0 2006.183.07:40:11.18#ibcon#read 5, iclass 3, count 0 2006.183.07:40:11.18#ibcon#about to read 6, iclass 3, count 0 2006.183.07:40:11.18#ibcon#read 6, iclass 3, count 0 2006.183.07:40:11.18#ibcon#end of sib2, iclass 3, count 0 2006.183.07:40:11.18#ibcon#*after write, iclass 3, count 0 2006.183.07:40:11.18#ibcon#*before return 0, iclass 3, count 0 2006.183.07:40:11.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:11.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.183.07:40:11.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.07:40:11.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.07:40:11.18$vc4f8/vblo=3,656.99 2006.183.07:40:11.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.07:40:11.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.07:40:11.18#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:11.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:11.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:11.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:11.18#ibcon#enter wrdev, iclass 5, count 0 2006.183.07:40:11.18#ibcon#first serial, iclass 5, count 0 2006.183.07:40:11.18#ibcon#enter sib2, iclass 5, count 0 2006.183.07:40:11.18#ibcon#flushed, iclass 5, count 0 2006.183.07:40:11.18#ibcon#about to write, iclass 5, count 0 2006.183.07:40:11.18#ibcon#wrote, iclass 5, count 0 2006.183.07:40:11.18#ibcon#about to read 3, iclass 5, count 0 2006.183.07:40:11.21#ibcon#read 3, iclass 5, count 0 2006.183.07:40:11.21#ibcon#about to read 4, iclass 5, count 0 2006.183.07:40:11.21#ibcon#read 4, iclass 5, count 0 2006.183.07:40:11.21#ibcon#about to read 5, iclass 5, count 0 2006.183.07:40:11.21#ibcon#read 5, iclass 5, count 0 2006.183.07:40:11.21#ibcon#about to read 6, iclass 5, count 0 2006.183.07:40:11.21#ibcon#read 6, iclass 5, count 0 2006.183.07:40:11.21#ibcon#end of sib2, iclass 5, count 0 2006.183.07:40:11.21#ibcon#*mode == 0, iclass 5, count 0 2006.183.07:40:11.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.07:40:11.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:40:11.21#ibcon#*before write, iclass 5, count 0 2006.183.07:40:11.21#ibcon#enter sib2, iclass 5, count 0 2006.183.07:40:11.21#ibcon#flushed, iclass 5, count 0 2006.183.07:40:11.21#ibcon#about to write, iclass 5, count 0 2006.183.07:40:11.21#ibcon#wrote, iclass 5, count 0 2006.183.07:40:11.21#ibcon#about to read 3, iclass 5, count 0 2006.183.07:40:11.25#ibcon#read 3, iclass 5, count 0 2006.183.07:40:11.25#ibcon#about to read 4, iclass 5, count 0 2006.183.07:40:11.25#ibcon#read 4, iclass 5, count 0 2006.183.07:40:11.25#ibcon#about to read 5, iclass 5, count 0 2006.183.07:40:11.25#ibcon#read 5, iclass 5, count 0 2006.183.07:40:11.25#ibcon#about to read 6, iclass 5, count 0 2006.183.07:40:11.25#ibcon#read 6, iclass 5, count 0 2006.183.07:40:11.25#ibcon#end of sib2, iclass 5, count 0 2006.183.07:40:11.25#ibcon#*after write, iclass 5, count 0 2006.183.07:40:11.25#ibcon#*before return 0, iclass 5, count 0 2006.183.07:40:11.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:11.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:40:11.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.07:40:11.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.07:40:11.25$vc4f8/vb=3,4 2006.183.07:40:11.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.07:40:11.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.07:40:11.25#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:11.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:11.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:11.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:11.30#ibcon#enter wrdev, iclass 7, count 2 2006.183.07:40:11.30#ibcon#first serial, iclass 7, count 2 2006.183.07:40:11.30#ibcon#enter sib2, iclass 7, count 2 2006.183.07:40:11.30#ibcon#flushed, iclass 7, count 2 2006.183.07:40:11.30#ibcon#about to write, iclass 7, count 2 2006.183.07:40:11.30#ibcon#wrote, iclass 7, count 2 2006.183.07:40:11.30#ibcon#about to read 3, iclass 7, count 2 2006.183.07:40:11.32#ibcon#read 3, iclass 7, count 2 2006.183.07:40:11.32#ibcon#about to read 4, iclass 7, count 2 2006.183.07:40:11.32#ibcon#read 4, iclass 7, count 2 2006.183.07:40:11.32#ibcon#about to read 5, iclass 7, count 2 2006.183.07:40:11.32#ibcon#read 5, iclass 7, count 2 2006.183.07:40:11.32#ibcon#about to read 6, iclass 7, count 2 2006.183.07:40:11.32#ibcon#read 6, iclass 7, count 2 2006.183.07:40:11.32#ibcon#end of sib2, iclass 7, count 2 2006.183.07:40:11.32#ibcon#*mode == 0, iclass 7, count 2 2006.183.07:40:11.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.07:40:11.32#ibcon#[27=AT03-04\r\n] 2006.183.07:40:11.32#ibcon#*before write, iclass 7, count 2 2006.183.07:40:11.32#ibcon#enter sib2, iclass 7, count 2 2006.183.07:40:11.32#ibcon#flushed, iclass 7, count 2 2006.183.07:40:11.32#ibcon#about to write, iclass 7, count 2 2006.183.07:40:11.32#ibcon#wrote, iclass 7, count 2 2006.183.07:40:11.32#ibcon#about to read 3, iclass 7, count 2 2006.183.07:40:11.35#ibcon#read 3, iclass 7, count 2 2006.183.07:40:11.35#ibcon#about to read 4, iclass 7, count 2 2006.183.07:40:11.35#ibcon#read 4, iclass 7, count 2 2006.183.07:40:11.35#ibcon#about to read 5, iclass 7, count 2 2006.183.07:40:11.35#ibcon#read 5, iclass 7, count 2 2006.183.07:40:11.35#ibcon#about to read 6, iclass 7, count 2 2006.183.07:40:11.35#ibcon#read 6, iclass 7, count 2 2006.183.07:40:11.35#ibcon#end of sib2, iclass 7, count 2 2006.183.07:40:11.35#ibcon#*after write, iclass 7, count 2 2006.183.07:40:11.35#ibcon#*before return 0, iclass 7, count 2 2006.183.07:40:11.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:11.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:40:11.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.07:40:11.35#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:11.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:11.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:11.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:11.47#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:40:11.47#ibcon#first serial, iclass 7, count 0 2006.183.07:40:11.47#ibcon#enter sib2, iclass 7, count 0 2006.183.07:40:11.47#ibcon#flushed, iclass 7, count 0 2006.183.07:40:11.47#ibcon#about to write, iclass 7, count 0 2006.183.07:40:11.47#ibcon#wrote, iclass 7, count 0 2006.183.07:40:11.47#ibcon#about to read 3, iclass 7, count 0 2006.183.07:40:11.49#ibcon#read 3, iclass 7, count 0 2006.183.07:40:11.49#ibcon#about to read 4, iclass 7, count 0 2006.183.07:40:11.49#ibcon#read 4, iclass 7, count 0 2006.183.07:40:11.49#ibcon#about to read 5, iclass 7, count 0 2006.183.07:40:11.49#ibcon#read 5, iclass 7, count 0 2006.183.07:40:11.49#ibcon#about to read 6, iclass 7, count 0 2006.183.07:40:11.49#ibcon#read 6, iclass 7, count 0 2006.183.07:40:11.49#ibcon#end of sib2, iclass 7, count 0 2006.183.07:40:11.49#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:40:11.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:40:11.49#ibcon#[27=USB\r\n] 2006.183.07:40:11.49#ibcon#*before write, iclass 7, count 0 2006.183.07:40:11.49#ibcon#enter sib2, iclass 7, count 0 2006.183.07:40:11.49#ibcon#flushed, iclass 7, count 0 2006.183.07:40:11.49#ibcon#about to write, iclass 7, count 0 2006.183.07:40:11.49#ibcon#wrote, iclass 7, count 0 2006.183.07:40:11.49#ibcon#about to read 3, iclass 7, count 0 2006.183.07:40:11.52#ibcon#read 3, iclass 7, count 0 2006.183.07:40:11.52#ibcon#about to read 4, iclass 7, count 0 2006.183.07:40:11.52#ibcon#read 4, iclass 7, count 0 2006.183.07:40:11.52#ibcon#about to read 5, iclass 7, count 0 2006.183.07:40:11.52#ibcon#read 5, iclass 7, count 0 2006.183.07:40:11.52#ibcon#about to read 6, iclass 7, count 0 2006.183.07:40:11.52#ibcon#read 6, iclass 7, count 0 2006.183.07:40:11.52#ibcon#end of sib2, iclass 7, count 0 2006.183.07:40:11.52#ibcon#*after write, iclass 7, count 0 2006.183.07:40:11.52#ibcon#*before return 0, iclass 7, count 0 2006.183.07:40:11.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:11.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:40:11.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:40:11.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:40:11.52$vc4f8/vblo=4,712.99 2006.183.07:40:11.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.07:40:11.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.07:40:11.52#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:11.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:11.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:11.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:11.52#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:40:11.52#ibcon#first serial, iclass 11, count 0 2006.183.07:40:11.52#ibcon#enter sib2, iclass 11, count 0 2006.183.07:40:11.52#ibcon#flushed, iclass 11, count 0 2006.183.07:40:11.52#ibcon#about to write, iclass 11, count 0 2006.183.07:40:11.52#ibcon#wrote, iclass 11, count 0 2006.183.07:40:11.52#ibcon#about to read 3, iclass 11, count 0 2006.183.07:40:11.54#ibcon#read 3, iclass 11, count 0 2006.183.07:40:11.54#ibcon#about to read 4, iclass 11, count 0 2006.183.07:40:11.54#ibcon#read 4, iclass 11, count 0 2006.183.07:40:11.54#ibcon#about to read 5, iclass 11, count 0 2006.183.07:40:11.54#ibcon#read 5, iclass 11, count 0 2006.183.07:40:11.54#ibcon#about to read 6, iclass 11, count 0 2006.183.07:40:11.54#ibcon#read 6, iclass 11, count 0 2006.183.07:40:11.54#ibcon#end of sib2, iclass 11, count 0 2006.183.07:40:11.54#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:40:11.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:40:11.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:40:11.54#ibcon#*before write, iclass 11, count 0 2006.183.07:40:11.54#ibcon#enter sib2, iclass 11, count 0 2006.183.07:40:11.54#ibcon#flushed, iclass 11, count 0 2006.183.07:40:11.54#ibcon#about to write, iclass 11, count 0 2006.183.07:40:11.54#ibcon#wrote, iclass 11, count 0 2006.183.07:40:11.54#ibcon#about to read 3, iclass 11, count 0 2006.183.07:40:11.58#ibcon#read 3, iclass 11, count 0 2006.183.07:40:11.58#ibcon#about to read 4, iclass 11, count 0 2006.183.07:40:11.58#ibcon#read 4, iclass 11, count 0 2006.183.07:40:11.58#ibcon#about to read 5, iclass 11, count 0 2006.183.07:40:11.58#ibcon#read 5, iclass 11, count 0 2006.183.07:40:11.58#ibcon#about to read 6, iclass 11, count 0 2006.183.07:40:11.58#ibcon#read 6, iclass 11, count 0 2006.183.07:40:11.58#ibcon#end of sib2, iclass 11, count 0 2006.183.07:40:11.58#ibcon#*after write, iclass 11, count 0 2006.183.07:40:11.58#ibcon#*before return 0, iclass 11, count 0 2006.183.07:40:11.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:11.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:40:11.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:40:11.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:40:11.58$vc4f8/vb=4,4 2006.183.07:40:11.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.07:40:11.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.07:40:11.58#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:11.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:11.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:11.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:11.64#ibcon#enter wrdev, iclass 13, count 2 2006.183.07:40:11.64#ibcon#first serial, iclass 13, count 2 2006.183.07:40:11.64#ibcon#enter sib2, iclass 13, count 2 2006.183.07:40:11.64#ibcon#flushed, iclass 13, count 2 2006.183.07:40:11.64#ibcon#about to write, iclass 13, count 2 2006.183.07:40:11.64#ibcon#wrote, iclass 13, count 2 2006.183.07:40:11.64#ibcon#about to read 3, iclass 13, count 2 2006.183.07:40:11.66#ibcon#read 3, iclass 13, count 2 2006.183.07:40:11.66#ibcon#about to read 4, iclass 13, count 2 2006.183.07:40:11.66#ibcon#read 4, iclass 13, count 2 2006.183.07:40:11.66#ibcon#about to read 5, iclass 13, count 2 2006.183.07:40:11.66#ibcon#read 5, iclass 13, count 2 2006.183.07:40:11.66#ibcon#about to read 6, iclass 13, count 2 2006.183.07:40:11.66#ibcon#read 6, iclass 13, count 2 2006.183.07:40:11.66#ibcon#end of sib2, iclass 13, count 2 2006.183.07:40:11.66#ibcon#*mode == 0, iclass 13, count 2 2006.183.07:40:11.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.07:40:11.66#ibcon#[27=AT04-04\r\n] 2006.183.07:40:11.66#ibcon#*before write, iclass 13, count 2 2006.183.07:40:11.66#ibcon#enter sib2, iclass 13, count 2 2006.183.07:40:11.66#ibcon#flushed, iclass 13, count 2 2006.183.07:40:11.66#ibcon#about to write, iclass 13, count 2 2006.183.07:40:11.66#ibcon#wrote, iclass 13, count 2 2006.183.07:40:11.66#ibcon#about to read 3, iclass 13, count 2 2006.183.07:40:11.69#ibcon#read 3, iclass 13, count 2 2006.183.07:40:11.69#ibcon#about to read 4, iclass 13, count 2 2006.183.07:40:11.69#ibcon#read 4, iclass 13, count 2 2006.183.07:40:11.69#ibcon#about to read 5, iclass 13, count 2 2006.183.07:40:11.69#ibcon#read 5, iclass 13, count 2 2006.183.07:40:11.69#ibcon#about to read 6, iclass 13, count 2 2006.183.07:40:11.69#ibcon#read 6, iclass 13, count 2 2006.183.07:40:11.69#ibcon#end of sib2, iclass 13, count 2 2006.183.07:40:11.69#ibcon#*after write, iclass 13, count 2 2006.183.07:40:11.69#ibcon#*before return 0, iclass 13, count 2 2006.183.07:40:11.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:11.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:40:11.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.07:40:11.69#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:11.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:11.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:11.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:11.81#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:40:11.81#ibcon#first serial, iclass 13, count 0 2006.183.07:40:11.81#ibcon#enter sib2, iclass 13, count 0 2006.183.07:40:11.81#ibcon#flushed, iclass 13, count 0 2006.183.07:40:11.81#ibcon#about to write, iclass 13, count 0 2006.183.07:40:11.81#ibcon#wrote, iclass 13, count 0 2006.183.07:40:11.81#ibcon#about to read 3, iclass 13, count 0 2006.183.07:40:11.83#ibcon#read 3, iclass 13, count 0 2006.183.07:40:11.83#ibcon#about to read 4, iclass 13, count 0 2006.183.07:40:11.83#ibcon#read 4, iclass 13, count 0 2006.183.07:40:11.83#ibcon#about to read 5, iclass 13, count 0 2006.183.07:40:11.83#ibcon#read 5, iclass 13, count 0 2006.183.07:40:11.83#ibcon#about to read 6, iclass 13, count 0 2006.183.07:40:11.83#ibcon#read 6, iclass 13, count 0 2006.183.07:40:11.83#ibcon#end of sib2, iclass 13, count 0 2006.183.07:40:11.83#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:40:11.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:40:11.83#ibcon#[27=USB\r\n] 2006.183.07:40:11.83#ibcon#*before write, iclass 13, count 0 2006.183.07:40:11.83#ibcon#enter sib2, iclass 13, count 0 2006.183.07:40:11.83#ibcon#flushed, iclass 13, count 0 2006.183.07:40:11.83#ibcon#about to write, iclass 13, count 0 2006.183.07:40:11.83#ibcon#wrote, iclass 13, count 0 2006.183.07:40:11.83#ibcon#about to read 3, iclass 13, count 0 2006.183.07:40:11.86#ibcon#read 3, iclass 13, count 0 2006.183.07:40:11.86#ibcon#about to read 4, iclass 13, count 0 2006.183.07:40:11.86#ibcon#read 4, iclass 13, count 0 2006.183.07:40:11.86#ibcon#about to read 5, iclass 13, count 0 2006.183.07:40:11.86#ibcon#read 5, iclass 13, count 0 2006.183.07:40:11.86#ibcon#about to read 6, iclass 13, count 0 2006.183.07:40:11.86#ibcon#read 6, iclass 13, count 0 2006.183.07:40:11.86#ibcon#end of sib2, iclass 13, count 0 2006.183.07:40:11.86#ibcon#*after write, iclass 13, count 0 2006.183.07:40:11.86#ibcon#*before return 0, iclass 13, count 0 2006.183.07:40:11.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:11.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:40:11.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:40:11.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:40:11.86$vc4f8/vblo=5,744.99 2006.183.07:40:11.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.07:40:11.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.07:40:11.86#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:11.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:11.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:11.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:11.86#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:40:11.86#ibcon#first serial, iclass 15, count 0 2006.183.07:40:11.86#ibcon#enter sib2, iclass 15, count 0 2006.183.07:40:11.86#ibcon#flushed, iclass 15, count 0 2006.183.07:40:11.86#ibcon#about to write, iclass 15, count 0 2006.183.07:40:11.86#ibcon#wrote, iclass 15, count 0 2006.183.07:40:11.86#ibcon#about to read 3, iclass 15, count 0 2006.183.07:40:11.89#ibcon#read 3, iclass 15, count 0 2006.183.07:40:11.89#ibcon#about to read 4, iclass 15, count 0 2006.183.07:40:11.89#ibcon#read 4, iclass 15, count 0 2006.183.07:40:11.89#ibcon#about to read 5, iclass 15, count 0 2006.183.07:40:11.89#ibcon#read 5, iclass 15, count 0 2006.183.07:40:11.89#ibcon#about to read 6, iclass 15, count 0 2006.183.07:40:11.89#ibcon#read 6, iclass 15, count 0 2006.183.07:40:11.89#ibcon#end of sib2, iclass 15, count 0 2006.183.07:40:11.89#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:40:11.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:40:11.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:40:11.89#ibcon#*before write, iclass 15, count 0 2006.183.07:40:11.89#ibcon#enter sib2, iclass 15, count 0 2006.183.07:40:11.89#ibcon#flushed, iclass 15, count 0 2006.183.07:40:11.89#ibcon#about to write, iclass 15, count 0 2006.183.07:40:11.89#ibcon#wrote, iclass 15, count 0 2006.183.07:40:11.89#ibcon#about to read 3, iclass 15, count 0 2006.183.07:40:11.93#ibcon#read 3, iclass 15, count 0 2006.183.07:40:11.93#ibcon#about to read 4, iclass 15, count 0 2006.183.07:40:11.93#ibcon#read 4, iclass 15, count 0 2006.183.07:40:11.93#ibcon#about to read 5, iclass 15, count 0 2006.183.07:40:11.93#ibcon#read 5, iclass 15, count 0 2006.183.07:40:11.93#ibcon#about to read 6, iclass 15, count 0 2006.183.07:40:11.93#ibcon#read 6, iclass 15, count 0 2006.183.07:40:11.93#ibcon#end of sib2, iclass 15, count 0 2006.183.07:40:11.93#ibcon#*after write, iclass 15, count 0 2006.183.07:40:11.93#ibcon#*before return 0, iclass 15, count 0 2006.183.07:40:11.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:11.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:40:11.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:40:11.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:40:11.93$vc4f8/vb=5,4 2006.183.07:40:11.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.07:40:11.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.07:40:11.93#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:11.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:11.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:11.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:11.98#ibcon#enter wrdev, iclass 17, count 2 2006.183.07:40:11.98#ibcon#first serial, iclass 17, count 2 2006.183.07:40:11.98#ibcon#enter sib2, iclass 17, count 2 2006.183.07:40:11.98#ibcon#flushed, iclass 17, count 2 2006.183.07:40:11.98#ibcon#about to write, iclass 17, count 2 2006.183.07:40:11.98#ibcon#wrote, iclass 17, count 2 2006.183.07:40:11.98#ibcon#about to read 3, iclass 17, count 2 2006.183.07:40:12.00#ibcon#read 3, iclass 17, count 2 2006.183.07:40:12.00#ibcon#about to read 4, iclass 17, count 2 2006.183.07:40:12.00#ibcon#read 4, iclass 17, count 2 2006.183.07:40:12.00#ibcon#about to read 5, iclass 17, count 2 2006.183.07:40:12.00#ibcon#read 5, iclass 17, count 2 2006.183.07:40:12.00#ibcon#about to read 6, iclass 17, count 2 2006.183.07:40:12.00#ibcon#read 6, iclass 17, count 2 2006.183.07:40:12.00#ibcon#end of sib2, iclass 17, count 2 2006.183.07:40:12.00#ibcon#*mode == 0, iclass 17, count 2 2006.183.07:40:12.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.07:40:12.00#ibcon#[27=AT05-04\r\n] 2006.183.07:40:12.00#ibcon#*before write, iclass 17, count 2 2006.183.07:40:12.00#ibcon#enter sib2, iclass 17, count 2 2006.183.07:40:12.00#ibcon#flushed, iclass 17, count 2 2006.183.07:40:12.00#ibcon#about to write, iclass 17, count 2 2006.183.07:40:12.00#ibcon#wrote, iclass 17, count 2 2006.183.07:40:12.00#ibcon#about to read 3, iclass 17, count 2 2006.183.07:40:12.03#ibcon#read 3, iclass 17, count 2 2006.183.07:40:12.03#ibcon#about to read 4, iclass 17, count 2 2006.183.07:40:12.03#ibcon#read 4, iclass 17, count 2 2006.183.07:40:12.03#ibcon#about to read 5, iclass 17, count 2 2006.183.07:40:12.03#ibcon#read 5, iclass 17, count 2 2006.183.07:40:12.03#ibcon#about to read 6, iclass 17, count 2 2006.183.07:40:12.03#ibcon#read 6, iclass 17, count 2 2006.183.07:40:12.03#ibcon#end of sib2, iclass 17, count 2 2006.183.07:40:12.03#ibcon#*after write, iclass 17, count 2 2006.183.07:40:12.03#ibcon#*before return 0, iclass 17, count 2 2006.183.07:40:12.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:12.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:40:12.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.07:40:12.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:12.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:12.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:12.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:12.15#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:40:12.15#ibcon#first serial, iclass 17, count 0 2006.183.07:40:12.15#ibcon#enter sib2, iclass 17, count 0 2006.183.07:40:12.15#ibcon#flushed, iclass 17, count 0 2006.183.07:40:12.15#ibcon#about to write, iclass 17, count 0 2006.183.07:40:12.15#ibcon#wrote, iclass 17, count 0 2006.183.07:40:12.15#ibcon#about to read 3, iclass 17, count 0 2006.183.07:40:12.17#ibcon#read 3, iclass 17, count 0 2006.183.07:40:12.17#ibcon#about to read 4, iclass 17, count 0 2006.183.07:40:12.17#ibcon#read 4, iclass 17, count 0 2006.183.07:40:12.17#ibcon#about to read 5, iclass 17, count 0 2006.183.07:40:12.17#ibcon#read 5, iclass 17, count 0 2006.183.07:40:12.17#ibcon#about to read 6, iclass 17, count 0 2006.183.07:40:12.17#ibcon#read 6, iclass 17, count 0 2006.183.07:40:12.17#ibcon#end of sib2, iclass 17, count 0 2006.183.07:40:12.17#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:40:12.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:40:12.17#ibcon#[27=USB\r\n] 2006.183.07:40:12.17#ibcon#*before write, iclass 17, count 0 2006.183.07:40:12.17#ibcon#enter sib2, iclass 17, count 0 2006.183.07:40:12.17#ibcon#flushed, iclass 17, count 0 2006.183.07:40:12.17#ibcon#about to write, iclass 17, count 0 2006.183.07:40:12.17#ibcon#wrote, iclass 17, count 0 2006.183.07:40:12.17#ibcon#about to read 3, iclass 17, count 0 2006.183.07:40:12.20#ibcon#read 3, iclass 17, count 0 2006.183.07:40:12.20#ibcon#about to read 4, iclass 17, count 0 2006.183.07:40:12.20#ibcon#read 4, iclass 17, count 0 2006.183.07:40:12.20#ibcon#about to read 5, iclass 17, count 0 2006.183.07:40:12.20#ibcon#read 5, iclass 17, count 0 2006.183.07:40:12.20#ibcon#about to read 6, iclass 17, count 0 2006.183.07:40:12.20#ibcon#read 6, iclass 17, count 0 2006.183.07:40:12.20#ibcon#end of sib2, iclass 17, count 0 2006.183.07:40:12.20#ibcon#*after write, iclass 17, count 0 2006.183.07:40:12.20#ibcon#*before return 0, iclass 17, count 0 2006.183.07:40:12.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:12.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:40:12.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:40:12.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:40:12.20$vc4f8/vblo=6,752.99 2006.183.07:40:12.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.07:40:12.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.07:40:12.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:40:12.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:12.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:12.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:12.20#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:40:12.20#ibcon#first serial, iclass 19, count 0 2006.183.07:40:12.20#ibcon#enter sib2, iclass 19, count 0 2006.183.07:40:12.20#ibcon#flushed, iclass 19, count 0 2006.183.07:40:12.20#ibcon#about to write, iclass 19, count 0 2006.183.07:40:12.20#ibcon#wrote, iclass 19, count 0 2006.183.07:40:12.20#ibcon#about to read 3, iclass 19, count 0 2006.183.07:40:12.22#ibcon#read 3, iclass 19, count 0 2006.183.07:40:12.22#ibcon#about to read 4, iclass 19, count 0 2006.183.07:40:12.22#ibcon#read 4, iclass 19, count 0 2006.183.07:40:12.22#ibcon#about to read 5, iclass 19, count 0 2006.183.07:40:12.22#ibcon#read 5, iclass 19, count 0 2006.183.07:40:12.22#ibcon#about to read 6, iclass 19, count 0 2006.183.07:40:12.22#ibcon#read 6, iclass 19, count 0 2006.183.07:40:12.22#ibcon#end of sib2, iclass 19, count 0 2006.183.07:40:12.22#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:40:12.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:40:12.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:40:12.22#ibcon#*before write, iclass 19, count 0 2006.183.07:40:12.22#ibcon#enter sib2, iclass 19, count 0 2006.183.07:40:12.22#ibcon#flushed, iclass 19, count 0 2006.183.07:40:12.22#ibcon#about to write, iclass 19, count 0 2006.183.07:40:12.22#ibcon#wrote, iclass 19, count 0 2006.183.07:40:12.22#ibcon#about to read 3, iclass 19, count 0 2006.183.07:40:12.26#ibcon#read 3, iclass 19, count 0 2006.183.07:40:12.26#ibcon#about to read 4, iclass 19, count 0 2006.183.07:40:12.26#ibcon#read 4, iclass 19, count 0 2006.183.07:40:12.26#ibcon#about to read 5, iclass 19, count 0 2006.183.07:40:12.26#ibcon#read 5, iclass 19, count 0 2006.183.07:40:12.26#ibcon#about to read 6, iclass 19, count 0 2006.183.07:40:12.26#ibcon#read 6, iclass 19, count 0 2006.183.07:40:12.26#ibcon#end of sib2, iclass 19, count 0 2006.183.07:40:12.26#ibcon#*after write, iclass 19, count 0 2006.183.07:40:12.26#ibcon#*before return 0, iclass 19, count 0 2006.183.07:40:12.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:12.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:40:12.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:40:12.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:40:12.26$vc4f8/vb=6,4 2006.183.07:40:12.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.07:40:12.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.07:40:12.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:40:12.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:12.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:12.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:12.32#ibcon#enter wrdev, iclass 21, count 2 2006.183.07:40:12.32#ibcon#first serial, iclass 21, count 2 2006.183.07:40:12.32#ibcon#enter sib2, iclass 21, count 2 2006.183.07:40:12.32#ibcon#flushed, iclass 21, count 2 2006.183.07:40:12.32#ibcon#about to write, iclass 21, count 2 2006.183.07:40:12.32#ibcon#wrote, iclass 21, count 2 2006.183.07:40:12.32#ibcon#about to read 3, iclass 21, count 2 2006.183.07:40:12.34#ibcon#read 3, iclass 21, count 2 2006.183.07:40:12.34#ibcon#about to read 4, iclass 21, count 2 2006.183.07:40:12.34#ibcon#read 4, iclass 21, count 2 2006.183.07:40:12.34#ibcon#about to read 5, iclass 21, count 2 2006.183.07:40:12.34#ibcon#read 5, iclass 21, count 2 2006.183.07:40:12.34#ibcon#about to read 6, iclass 21, count 2 2006.183.07:40:12.34#ibcon#read 6, iclass 21, count 2 2006.183.07:40:12.34#ibcon#end of sib2, iclass 21, count 2 2006.183.07:40:12.34#ibcon#*mode == 0, iclass 21, count 2 2006.183.07:40:12.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.07:40:12.34#ibcon#[27=AT06-04\r\n] 2006.183.07:40:12.34#ibcon#*before write, iclass 21, count 2 2006.183.07:40:12.34#ibcon#enter sib2, iclass 21, count 2 2006.183.07:40:12.34#ibcon#flushed, iclass 21, count 2 2006.183.07:40:12.34#ibcon#about to write, iclass 21, count 2 2006.183.07:40:12.34#ibcon#wrote, iclass 21, count 2 2006.183.07:40:12.34#ibcon#about to read 3, iclass 21, count 2 2006.183.07:40:12.37#ibcon#read 3, iclass 21, count 2 2006.183.07:40:12.37#ibcon#about to read 4, iclass 21, count 2 2006.183.07:40:12.37#ibcon#read 4, iclass 21, count 2 2006.183.07:40:12.37#ibcon#about to read 5, iclass 21, count 2 2006.183.07:40:12.37#ibcon#read 5, iclass 21, count 2 2006.183.07:40:12.37#ibcon#about to read 6, iclass 21, count 2 2006.183.07:40:12.37#ibcon#read 6, iclass 21, count 2 2006.183.07:40:12.37#ibcon#end of sib2, iclass 21, count 2 2006.183.07:40:12.37#ibcon#*after write, iclass 21, count 2 2006.183.07:40:12.37#ibcon#*before return 0, iclass 21, count 2 2006.183.07:40:12.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:12.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:40:12.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.07:40:12.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:40:12.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:12.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:12.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:12.49#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:40:12.49#ibcon#first serial, iclass 21, count 0 2006.183.07:40:12.49#ibcon#enter sib2, iclass 21, count 0 2006.183.07:40:12.49#ibcon#flushed, iclass 21, count 0 2006.183.07:40:12.49#ibcon#about to write, iclass 21, count 0 2006.183.07:40:12.49#ibcon#wrote, iclass 21, count 0 2006.183.07:40:12.49#ibcon#about to read 3, iclass 21, count 0 2006.183.07:40:12.51#ibcon#read 3, iclass 21, count 0 2006.183.07:40:12.51#ibcon#about to read 4, iclass 21, count 0 2006.183.07:40:12.51#ibcon#read 4, iclass 21, count 0 2006.183.07:40:12.51#ibcon#about to read 5, iclass 21, count 0 2006.183.07:40:12.51#ibcon#read 5, iclass 21, count 0 2006.183.07:40:12.51#ibcon#about to read 6, iclass 21, count 0 2006.183.07:40:12.51#ibcon#read 6, iclass 21, count 0 2006.183.07:40:12.51#ibcon#end of sib2, iclass 21, count 0 2006.183.07:40:12.51#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:40:12.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:40:12.51#ibcon#[27=USB\r\n] 2006.183.07:40:12.51#ibcon#*before write, iclass 21, count 0 2006.183.07:40:12.51#ibcon#enter sib2, iclass 21, count 0 2006.183.07:40:12.51#ibcon#flushed, iclass 21, count 0 2006.183.07:40:12.51#ibcon#about to write, iclass 21, count 0 2006.183.07:40:12.51#ibcon#wrote, iclass 21, count 0 2006.183.07:40:12.51#ibcon#about to read 3, iclass 21, count 0 2006.183.07:40:12.54#ibcon#read 3, iclass 21, count 0 2006.183.07:40:12.54#ibcon#about to read 4, iclass 21, count 0 2006.183.07:40:12.54#ibcon#read 4, iclass 21, count 0 2006.183.07:40:12.54#ibcon#about to read 5, iclass 21, count 0 2006.183.07:40:12.54#ibcon#read 5, iclass 21, count 0 2006.183.07:40:12.54#ibcon#about to read 6, iclass 21, count 0 2006.183.07:40:12.54#ibcon#read 6, iclass 21, count 0 2006.183.07:40:12.54#ibcon#end of sib2, iclass 21, count 0 2006.183.07:40:12.54#ibcon#*after write, iclass 21, count 0 2006.183.07:40:12.54#ibcon#*before return 0, iclass 21, count 0 2006.183.07:40:12.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:12.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:40:12.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:40:12.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:40:12.54$vc4f8/vabw=wide 2006.183.07:40:12.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.07:40:12.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.07:40:12.54#ibcon#ireg 8 cls_cnt 0 2006.183.07:40:12.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:12.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:12.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:12.54#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:40:12.54#ibcon#first serial, iclass 23, count 0 2006.183.07:40:12.54#ibcon#enter sib2, iclass 23, count 0 2006.183.07:40:12.54#ibcon#flushed, iclass 23, count 0 2006.183.07:40:12.54#ibcon#about to write, iclass 23, count 0 2006.183.07:40:12.54#ibcon#wrote, iclass 23, count 0 2006.183.07:40:12.54#ibcon#about to read 3, iclass 23, count 0 2006.183.07:40:12.56#ibcon#read 3, iclass 23, count 0 2006.183.07:40:12.56#ibcon#about to read 4, iclass 23, count 0 2006.183.07:40:12.56#ibcon#read 4, iclass 23, count 0 2006.183.07:40:12.56#ibcon#about to read 5, iclass 23, count 0 2006.183.07:40:12.56#ibcon#read 5, iclass 23, count 0 2006.183.07:40:12.56#ibcon#about to read 6, iclass 23, count 0 2006.183.07:40:12.56#ibcon#read 6, iclass 23, count 0 2006.183.07:40:12.56#ibcon#end of sib2, iclass 23, count 0 2006.183.07:40:12.56#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:40:12.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:40:12.56#ibcon#[25=BW32\r\n] 2006.183.07:40:12.56#ibcon#*before write, iclass 23, count 0 2006.183.07:40:12.56#ibcon#enter sib2, iclass 23, count 0 2006.183.07:40:12.56#ibcon#flushed, iclass 23, count 0 2006.183.07:40:12.56#ibcon#about to write, iclass 23, count 0 2006.183.07:40:12.56#ibcon#wrote, iclass 23, count 0 2006.183.07:40:12.56#ibcon#about to read 3, iclass 23, count 0 2006.183.07:40:12.60#ibcon#read 3, iclass 23, count 0 2006.183.07:40:12.60#ibcon#about to read 4, iclass 23, count 0 2006.183.07:40:12.60#ibcon#read 4, iclass 23, count 0 2006.183.07:40:12.60#ibcon#about to read 5, iclass 23, count 0 2006.183.07:40:12.60#ibcon#read 5, iclass 23, count 0 2006.183.07:40:12.60#ibcon#about to read 6, iclass 23, count 0 2006.183.07:40:12.60#ibcon#read 6, iclass 23, count 0 2006.183.07:40:12.60#ibcon#end of sib2, iclass 23, count 0 2006.183.07:40:12.60#ibcon#*after write, iclass 23, count 0 2006.183.07:40:12.60#ibcon#*before return 0, iclass 23, count 0 2006.183.07:40:12.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:12.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:40:12.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:40:12.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:40:12.60$vc4f8/vbbw=wide 2006.183.07:40:12.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:40:12.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:40:12.60#ibcon#ireg 8 cls_cnt 0 2006.183.07:40:12.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:40:12.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:40:12.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:40:12.65#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:40:12.65#ibcon#first serial, iclass 25, count 0 2006.183.07:40:12.65#ibcon#enter sib2, iclass 25, count 0 2006.183.07:40:12.65#ibcon#flushed, iclass 25, count 0 2006.183.07:40:12.65#ibcon#about to write, iclass 25, count 0 2006.183.07:40:12.65#ibcon#wrote, iclass 25, count 0 2006.183.07:40:12.65#ibcon#about to read 3, iclass 25, count 0 2006.183.07:40:12.68#ibcon#read 3, iclass 25, count 0 2006.183.07:40:12.68#ibcon#about to read 4, iclass 25, count 0 2006.183.07:40:12.68#ibcon#read 4, iclass 25, count 0 2006.183.07:40:12.68#ibcon#about to read 5, iclass 25, count 0 2006.183.07:40:12.68#ibcon#read 5, iclass 25, count 0 2006.183.07:40:12.68#ibcon#about to read 6, iclass 25, count 0 2006.183.07:40:12.68#ibcon#read 6, iclass 25, count 0 2006.183.07:40:12.68#ibcon#end of sib2, iclass 25, count 0 2006.183.07:40:12.68#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:40:12.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:40:12.68#ibcon#[27=BW32\r\n] 2006.183.07:40:12.68#ibcon#*before write, iclass 25, count 0 2006.183.07:40:12.68#ibcon#enter sib2, iclass 25, count 0 2006.183.07:40:12.68#ibcon#flushed, iclass 25, count 0 2006.183.07:40:12.68#ibcon#about to write, iclass 25, count 0 2006.183.07:40:12.68#ibcon#wrote, iclass 25, count 0 2006.183.07:40:12.68#ibcon#about to read 3, iclass 25, count 0 2006.183.07:40:12.70#ibcon#read 3, iclass 25, count 0 2006.183.07:40:12.70#ibcon#about to read 4, iclass 25, count 0 2006.183.07:40:12.70#ibcon#read 4, iclass 25, count 0 2006.183.07:40:12.70#ibcon#about to read 5, iclass 25, count 0 2006.183.07:40:12.70#ibcon#read 5, iclass 25, count 0 2006.183.07:40:12.70#ibcon#about to read 6, iclass 25, count 0 2006.183.07:40:12.70#ibcon#read 6, iclass 25, count 0 2006.183.07:40:12.70#ibcon#end of sib2, iclass 25, count 0 2006.183.07:40:12.70#ibcon#*after write, iclass 25, count 0 2006.183.07:40:12.70#ibcon#*before return 0, iclass 25, count 0 2006.183.07:40:12.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:40:12.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:40:12.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:40:12.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:40:12.70$4f8m12a/ifd4f 2006.183.07:40:12.70$ifd4f/lo= 2006.183.07:40:12.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:40:12.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:40:12.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:40:12.71$ifd4f/patch= 2006.183.07:40:12.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:40:12.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:40:12.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:40:12.71$4f8m12a/"form=m,16.000,1:2 2006.183.07:40:12.71$4f8m12a/"tpicd 2006.183.07:40:12.71$4f8m12a/echo=off 2006.183.07:40:12.71$4f8m12a/xlog=off 2006.183.07:40:12.71:!2006.183.07:40:40 2006.183.07:40:21.14#trakl#Source acquired 2006.183.07:40:22.14#flagr#flagr/antenna,acquired 2006.183.07:40:40.01:preob 2006.183.07:40:41.14/onsource/TRACKING 2006.183.07:40:41.14:!2006.183.07:40:50 2006.183.07:40:50.00:data_valid=on 2006.183.07:40:50.00:midob 2006.183.07:40:50.14/onsource/TRACKING 2006.183.07:40:50.14/wx/27.92,996.3,88 2006.183.07:40:50.27/cable/+6.4505E-03 2006.183.07:40:51.36/va/01,08,usb,yes,29,31 2006.183.07:40:51.36/va/02,07,usb,yes,29,31 2006.183.07:40:51.36/va/03,06,usb,yes,31,31 2006.183.07:40:51.36/va/04,07,usb,yes,30,32 2006.183.07:40:51.36/va/05,07,usb,yes,32,34 2006.183.07:40:51.36/va/06,06,usb,yes,31,31 2006.183.07:40:51.36/va/07,06,usb,yes,32,31 2006.183.07:40:51.36/va/08,07,usb,yes,30,29 2006.183.07:40:51.59/valo/01,532.99,yes,locked 2006.183.07:40:51.59/valo/02,572.99,yes,locked 2006.183.07:40:51.59/valo/03,672.99,yes,locked 2006.183.07:40:51.59/valo/04,832.99,yes,locked 2006.183.07:40:51.59/valo/05,652.99,yes,locked 2006.183.07:40:51.59/valo/06,772.99,yes,locked 2006.183.07:40:51.59/valo/07,832.99,yes,locked 2006.183.07:40:51.59/valo/08,852.99,yes,locked 2006.183.07:40:52.68/vb/01,04,usb,yes,29,28 2006.183.07:40:52.68/vb/02,04,usb,yes,31,32 2006.183.07:40:52.68/vb/03,04,usb,yes,27,31 2006.183.07:40:52.68/vb/04,04,usb,yes,28,28 2006.183.07:40:52.68/vb/05,04,usb,yes,27,31 2006.183.07:40:52.68/vb/06,04,usb,yes,28,31 2006.183.07:40:52.68/vb/07,04,usb,yes,30,30 2006.183.07:40:52.68/vb/08,04,usb,yes,27,31 2006.183.07:40:52.91/vblo/01,632.99,yes,locked 2006.183.07:40:52.91/vblo/02,640.99,yes,locked 2006.183.07:40:52.91/vblo/03,656.99,yes,locked 2006.183.07:40:52.91/vblo/04,712.99,yes,locked 2006.183.07:40:52.91/vblo/05,744.99,yes,locked 2006.183.07:40:52.91/vblo/06,752.99,yes,locked 2006.183.07:40:52.91/vblo/07,734.99,yes,locked 2006.183.07:40:52.91/vblo/08,744.99,yes,locked 2006.183.07:40:53.06/vabw/8 2006.183.07:40:53.21/vbbw/8 2006.183.07:40:53.30/xfe/off,on,15.0 2006.183.07:40:53.68/ifatt/23,28,28,28 2006.183.07:40:54.07/fmout-gps/S +3.30E-07 2006.183.07:40:54.11:!2006.183.07:41:50 2006.183.07:41:50.00:data_valid=off 2006.183.07:41:50.01:postob 2006.183.07:41:50.21/cable/+6.4513E-03 2006.183.07:41:50.22/wx/27.92,996.3,88 2006.183.07:41:51.07/fmout-gps/S +3.31E-07 2006.183.07:41:51.08:scan_name=183-0742,k06183,60 2006.183.07:41:51.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.183.07:41:51.13#flagr#flagr/antenna,new-source 2006.183.07:41:52.13:checkk5 2006.183.07:41:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:41:52.87/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:41:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:41:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:41:54.00/chk_obsdata//k5ts1/T1830740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:41:54.37/chk_obsdata//k5ts2/T1830740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:41:54.75/chk_obsdata//k5ts3/T1830740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:41:55.12/chk_obsdata//k5ts4/T1830740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:41:55.80/k5log//k5ts1_log_newline 2006.183.07:41:56.50/k5log//k5ts2_log_newline 2006.183.07:41:57.18/k5log//k5ts3_log_newline 2006.183.07:41:57.87/k5log//k5ts4_log_newline 2006.183.07:41:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:41:57.90:4f8m12a=1 2006.183.07:41:57.90$4f8m12a/echo=on 2006.183.07:41:57.90$4f8m12a/pcalon 2006.183.07:41:57.90$pcalon/"no phase cal control is implemented here 2006.183.07:41:57.90$4f8m12a/"tpicd=stop 2006.183.07:41:57.90$4f8m12a/vc4f8 2006.183.07:41:57.90$vc4f8/valo=1,532.99 2006.183.07:41:57.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:41:57.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:41:57.91#ibcon#ireg 17 cls_cnt 0 2006.183.07:41:57.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:41:57.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:41:57.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:41:57.91#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:41:57.91#ibcon#first serial, iclass 36, count 0 2006.183.07:41:57.91#ibcon#enter sib2, iclass 36, count 0 2006.183.07:41:57.91#ibcon#flushed, iclass 36, count 0 2006.183.07:41:57.91#ibcon#about to write, iclass 36, count 0 2006.183.07:41:57.91#ibcon#wrote, iclass 36, count 0 2006.183.07:41:57.91#ibcon#about to read 3, iclass 36, count 0 2006.183.07:41:57.94#ibcon#read 3, iclass 36, count 0 2006.183.07:41:57.94#ibcon#about to read 4, iclass 36, count 0 2006.183.07:41:57.94#ibcon#read 4, iclass 36, count 0 2006.183.07:41:57.94#ibcon#about to read 5, iclass 36, count 0 2006.183.07:41:57.94#ibcon#read 5, iclass 36, count 0 2006.183.07:41:57.94#ibcon#about to read 6, iclass 36, count 0 2006.183.07:41:57.94#ibcon#read 6, iclass 36, count 0 2006.183.07:41:57.94#ibcon#end of sib2, iclass 36, count 0 2006.183.07:41:57.94#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:41:57.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:41:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:41:57.94#ibcon#*before write, iclass 36, count 0 2006.183.07:41:57.94#ibcon#enter sib2, iclass 36, count 0 2006.183.07:41:57.94#ibcon#flushed, iclass 36, count 0 2006.183.07:41:57.94#ibcon#about to write, iclass 36, count 0 2006.183.07:41:57.94#ibcon#wrote, iclass 36, count 0 2006.183.07:41:57.94#ibcon#about to read 3, iclass 36, count 0 2006.183.07:41:57.99#ibcon#read 3, iclass 36, count 0 2006.183.07:41:57.99#ibcon#about to read 4, iclass 36, count 0 2006.183.07:41:57.99#ibcon#read 4, iclass 36, count 0 2006.183.07:41:57.99#ibcon#about to read 5, iclass 36, count 0 2006.183.07:41:57.99#ibcon#read 5, iclass 36, count 0 2006.183.07:41:57.99#ibcon#about to read 6, iclass 36, count 0 2006.183.07:41:57.99#ibcon#read 6, iclass 36, count 0 2006.183.07:41:57.99#ibcon#end of sib2, iclass 36, count 0 2006.183.07:41:57.99#ibcon#*after write, iclass 36, count 0 2006.183.07:41:57.99#ibcon#*before return 0, iclass 36, count 0 2006.183.07:41:57.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:41:57.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:41:57.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:41:57.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:41:57.99$vc4f8/va=1,8 2006.183.07:41:57.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.07:41:57.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.07:41:57.99#ibcon#ireg 11 cls_cnt 2 2006.183.07:41:57.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:41:57.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:41:57.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:41:57.99#ibcon#enter wrdev, iclass 38, count 2 2006.183.07:41:57.99#ibcon#first serial, iclass 38, count 2 2006.183.07:41:57.99#ibcon#enter sib2, iclass 38, count 2 2006.183.07:41:57.99#ibcon#flushed, iclass 38, count 2 2006.183.07:41:57.99#ibcon#about to write, iclass 38, count 2 2006.183.07:41:57.99#ibcon#wrote, iclass 38, count 2 2006.183.07:41:57.99#ibcon#about to read 3, iclass 38, count 2 2006.183.07:41:58.02#ibcon#read 3, iclass 38, count 2 2006.183.07:41:58.02#ibcon#about to read 4, iclass 38, count 2 2006.183.07:41:58.02#ibcon#read 4, iclass 38, count 2 2006.183.07:41:58.02#ibcon#about to read 5, iclass 38, count 2 2006.183.07:41:58.02#ibcon#read 5, iclass 38, count 2 2006.183.07:41:58.02#ibcon#about to read 6, iclass 38, count 2 2006.183.07:41:58.02#ibcon#read 6, iclass 38, count 2 2006.183.07:41:58.02#ibcon#end of sib2, iclass 38, count 2 2006.183.07:41:58.02#ibcon#*mode == 0, iclass 38, count 2 2006.183.07:41:58.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.07:41:58.02#ibcon#[25=AT01-08\r\n] 2006.183.07:41:58.02#ibcon#*before write, iclass 38, count 2 2006.183.07:41:58.02#ibcon#enter sib2, iclass 38, count 2 2006.183.07:41:58.02#ibcon#flushed, iclass 38, count 2 2006.183.07:41:58.02#ibcon#about to write, iclass 38, count 2 2006.183.07:41:58.02#ibcon#wrote, iclass 38, count 2 2006.183.07:41:58.02#ibcon#about to read 3, iclass 38, count 2 2006.183.07:41:58.05#ibcon#read 3, iclass 38, count 2 2006.183.07:41:58.05#ibcon#about to read 4, iclass 38, count 2 2006.183.07:41:58.05#ibcon#read 4, iclass 38, count 2 2006.183.07:41:58.05#ibcon#about to read 5, iclass 38, count 2 2006.183.07:41:58.05#ibcon#read 5, iclass 38, count 2 2006.183.07:41:58.05#ibcon#about to read 6, iclass 38, count 2 2006.183.07:41:58.05#ibcon#read 6, iclass 38, count 2 2006.183.07:41:58.05#ibcon#end of sib2, iclass 38, count 2 2006.183.07:41:58.05#ibcon#*after write, iclass 38, count 2 2006.183.07:41:58.05#ibcon#*before return 0, iclass 38, count 2 2006.183.07:41:58.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:41:58.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:41:58.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.07:41:58.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:41:58.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:41:58.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:41:58.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:41:58.17#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:41:58.17#ibcon#first serial, iclass 38, count 0 2006.183.07:41:58.17#ibcon#enter sib2, iclass 38, count 0 2006.183.07:41:58.17#ibcon#flushed, iclass 38, count 0 2006.183.07:41:58.17#ibcon#about to write, iclass 38, count 0 2006.183.07:41:58.17#ibcon#wrote, iclass 38, count 0 2006.183.07:41:58.17#ibcon#about to read 3, iclass 38, count 0 2006.183.07:41:58.19#ibcon#read 3, iclass 38, count 0 2006.183.07:41:58.19#ibcon#about to read 4, iclass 38, count 0 2006.183.07:41:58.19#ibcon#read 4, iclass 38, count 0 2006.183.07:41:58.19#ibcon#about to read 5, iclass 38, count 0 2006.183.07:41:58.19#ibcon#read 5, iclass 38, count 0 2006.183.07:41:58.19#ibcon#about to read 6, iclass 38, count 0 2006.183.07:41:58.19#ibcon#read 6, iclass 38, count 0 2006.183.07:41:58.19#ibcon#end of sib2, iclass 38, count 0 2006.183.07:41:58.19#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:41:58.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:41:58.19#ibcon#[25=USB\r\n] 2006.183.07:41:58.19#ibcon#*before write, iclass 38, count 0 2006.183.07:41:58.19#ibcon#enter sib2, iclass 38, count 0 2006.183.07:41:58.19#ibcon#flushed, iclass 38, count 0 2006.183.07:41:58.19#ibcon#about to write, iclass 38, count 0 2006.183.07:41:58.19#ibcon#wrote, iclass 38, count 0 2006.183.07:41:58.19#ibcon#about to read 3, iclass 38, count 0 2006.183.07:41:58.22#ibcon#read 3, iclass 38, count 0 2006.183.07:41:58.22#ibcon#about to read 4, iclass 38, count 0 2006.183.07:41:58.22#ibcon#read 4, iclass 38, count 0 2006.183.07:41:58.22#ibcon#about to read 5, iclass 38, count 0 2006.183.07:41:58.22#ibcon#read 5, iclass 38, count 0 2006.183.07:41:58.22#ibcon#about to read 6, iclass 38, count 0 2006.183.07:41:58.22#ibcon#read 6, iclass 38, count 0 2006.183.07:41:58.22#ibcon#end of sib2, iclass 38, count 0 2006.183.07:41:58.22#ibcon#*after write, iclass 38, count 0 2006.183.07:41:58.22#ibcon#*before return 0, iclass 38, count 0 2006.183.07:41:58.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:41:58.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:41:58.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:41:58.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:41:58.22$vc4f8/valo=2,572.99 2006.183.07:41:58.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:41:58.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:41:58.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:41:58.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:41:58.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:41:58.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:41:58.22#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:41:58.22#ibcon#first serial, iclass 40, count 0 2006.183.07:41:58.22#ibcon#enter sib2, iclass 40, count 0 2006.183.07:41:58.22#ibcon#flushed, iclass 40, count 0 2006.183.07:41:58.22#ibcon#about to write, iclass 40, count 0 2006.183.07:41:58.22#ibcon#wrote, iclass 40, count 0 2006.183.07:41:58.22#ibcon#about to read 3, iclass 40, count 0 2006.183.07:41:58.24#ibcon#read 3, iclass 40, count 0 2006.183.07:41:58.24#ibcon#about to read 4, iclass 40, count 0 2006.183.07:41:58.24#ibcon#read 4, iclass 40, count 0 2006.183.07:41:58.24#ibcon#about to read 5, iclass 40, count 0 2006.183.07:41:58.24#ibcon#read 5, iclass 40, count 0 2006.183.07:41:58.24#ibcon#about to read 6, iclass 40, count 0 2006.183.07:41:58.24#ibcon#read 6, iclass 40, count 0 2006.183.07:41:58.24#ibcon#end of sib2, iclass 40, count 0 2006.183.07:41:58.24#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:41:58.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:41:58.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:41:58.24#ibcon#*before write, iclass 40, count 0 2006.183.07:41:58.24#ibcon#enter sib2, iclass 40, count 0 2006.183.07:41:58.24#ibcon#flushed, iclass 40, count 0 2006.183.07:41:58.24#ibcon#about to write, iclass 40, count 0 2006.183.07:41:58.24#ibcon#wrote, iclass 40, count 0 2006.183.07:41:58.24#ibcon#about to read 3, iclass 40, count 0 2006.183.07:41:58.28#ibcon#read 3, iclass 40, count 0 2006.183.07:41:58.28#ibcon#about to read 4, iclass 40, count 0 2006.183.07:41:58.28#ibcon#read 4, iclass 40, count 0 2006.183.07:41:58.28#ibcon#about to read 5, iclass 40, count 0 2006.183.07:41:58.28#ibcon#read 5, iclass 40, count 0 2006.183.07:41:58.28#ibcon#about to read 6, iclass 40, count 0 2006.183.07:41:58.28#ibcon#read 6, iclass 40, count 0 2006.183.07:41:58.28#ibcon#end of sib2, iclass 40, count 0 2006.183.07:41:58.28#ibcon#*after write, iclass 40, count 0 2006.183.07:41:58.28#ibcon#*before return 0, iclass 40, count 0 2006.183.07:41:58.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:41:58.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:41:58.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:41:58.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:41:58.28$vc4f8/va=2,7 2006.183.07:41:58.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.07:41:58.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.07:41:58.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:41:58.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:41:58.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:41:58.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:41:58.34#ibcon#enter wrdev, iclass 4, count 2 2006.183.07:41:58.34#ibcon#first serial, iclass 4, count 2 2006.183.07:41:58.34#ibcon#enter sib2, iclass 4, count 2 2006.183.07:41:58.34#ibcon#flushed, iclass 4, count 2 2006.183.07:41:58.34#ibcon#about to write, iclass 4, count 2 2006.183.07:41:58.34#ibcon#wrote, iclass 4, count 2 2006.183.07:41:58.34#ibcon#about to read 3, iclass 4, count 2 2006.183.07:41:58.36#ibcon#read 3, iclass 4, count 2 2006.183.07:41:58.36#ibcon#about to read 4, iclass 4, count 2 2006.183.07:41:58.36#ibcon#read 4, iclass 4, count 2 2006.183.07:41:58.36#ibcon#about to read 5, iclass 4, count 2 2006.183.07:41:58.36#ibcon#read 5, iclass 4, count 2 2006.183.07:41:58.36#ibcon#about to read 6, iclass 4, count 2 2006.183.07:41:58.36#ibcon#read 6, iclass 4, count 2 2006.183.07:41:58.36#ibcon#end of sib2, iclass 4, count 2 2006.183.07:41:58.36#ibcon#*mode == 0, iclass 4, count 2 2006.183.07:41:58.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.07:41:58.36#ibcon#[25=AT02-07\r\n] 2006.183.07:41:58.36#ibcon#*before write, iclass 4, count 2 2006.183.07:41:58.36#ibcon#enter sib2, iclass 4, count 2 2006.183.07:41:58.36#ibcon#flushed, iclass 4, count 2 2006.183.07:41:58.36#ibcon#about to write, iclass 4, count 2 2006.183.07:41:58.36#ibcon#wrote, iclass 4, count 2 2006.183.07:41:58.36#ibcon#about to read 3, iclass 4, count 2 2006.183.07:41:58.39#ibcon#read 3, iclass 4, count 2 2006.183.07:41:58.39#ibcon#about to read 4, iclass 4, count 2 2006.183.07:41:58.39#ibcon#read 4, iclass 4, count 2 2006.183.07:41:58.39#ibcon#about to read 5, iclass 4, count 2 2006.183.07:41:58.39#ibcon#read 5, iclass 4, count 2 2006.183.07:41:58.39#ibcon#about to read 6, iclass 4, count 2 2006.183.07:41:58.39#ibcon#read 6, iclass 4, count 2 2006.183.07:41:58.39#ibcon#end of sib2, iclass 4, count 2 2006.183.07:41:58.39#ibcon#*after write, iclass 4, count 2 2006.183.07:41:58.39#ibcon#*before return 0, iclass 4, count 2 2006.183.07:41:58.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:41:58.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:41:58.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.07:41:58.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:41:58.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:41:58.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:41:58.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:41:58.52#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:41:58.52#ibcon#first serial, iclass 4, count 0 2006.183.07:41:58.52#ibcon#enter sib2, iclass 4, count 0 2006.183.07:41:58.52#ibcon#flushed, iclass 4, count 0 2006.183.07:41:58.52#ibcon#about to write, iclass 4, count 0 2006.183.07:41:58.52#ibcon#wrote, iclass 4, count 0 2006.183.07:41:58.52#ibcon#about to read 3, iclass 4, count 0 2006.183.07:41:58.53#ibcon#read 3, iclass 4, count 0 2006.183.07:41:58.53#ibcon#about to read 4, iclass 4, count 0 2006.183.07:41:58.53#ibcon#read 4, iclass 4, count 0 2006.183.07:41:58.53#ibcon#about to read 5, iclass 4, count 0 2006.183.07:41:58.53#ibcon#read 5, iclass 4, count 0 2006.183.07:41:58.53#ibcon#about to read 6, iclass 4, count 0 2006.183.07:41:58.53#ibcon#read 6, iclass 4, count 0 2006.183.07:41:58.53#ibcon#end of sib2, iclass 4, count 0 2006.183.07:41:58.53#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:41:58.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:41:58.53#ibcon#[25=USB\r\n] 2006.183.07:41:58.53#ibcon#*before write, iclass 4, count 0 2006.183.07:41:58.53#ibcon#enter sib2, iclass 4, count 0 2006.183.07:41:58.53#ibcon#flushed, iclass 4, count 0 2006.183.07:41:58.53#ibcon#about to write, iclass 4, count 0 2006.183.07:41:58.53#ibcon#wrote, iclass 4, count 0 2006.183.07:41:58.53#ibcon#about to read 3, iclass 4, count 0 2006.183.07:41:58.56#ibcon#read 3, iclass 4, count 0 2006.183.07:41:58.56#ibcon#about to read 4, iclass 4, count 0 2006.183.07:41:58.56#ibcon#read 4, iclass 4, count 0 2006.183.07:41:58.56#ibcon#about to read 5, iclass 4, count 0 2006.183.07:41:58.56#ibcon#read 5, iclass 4, count 0 2006.183.07:41:58.56#ibcon#about to read 6, iclass 4, count 0 2006.183.07:41:58.56#ibcon#read 6, iclass 4, count 0 2006.183.07:41:58.56#ibcon#end of sib2, iclass 4, count 0 2006.183.07:41:58.56#ibcon#*after write, iclass 4, count 0 2006.183.07:41:58.56#ibcon#*before return 0, iclass 4, count 0 2006.183.07:41:58.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:41:58.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:41:58.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:41:58.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:41:58.56$vc4f8/valo=3,672.99 2006.183.07:41:58.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:41:58.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:41:58.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:41:58.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:41:58.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:41:58.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:41:58.56#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:41:58.56#ibcon#first serial, iclass 6, count 0 2006.183.07:41:58.56#ibcon#enter sib2, iclass 6, count 0 2006.183.07:41:58.56#ibcon#flushed, iclass 6, count 0 2006.183.07:41:58.56#ibcon#about to write, iclass 6, count 0 2006.183.07:41:58.56#ibcon#wrote, iclass 6, count 0 2006.183.07:41:58.56#ibcon#about to read 3, iclass 6, count 0 2006.183.07:41:58.59#ibcon#read 3, iclass 6, count 0 2006.183.07:41:58.59#ibcon#about to read 4, iclass 6, count 0 2006.183.07:41:58.59#ibcon#read 4, iclass 6, count 0 2006.183.07:41:58.59#ibcon#about to read 5, iclass 6, count 0 2006.183.07:41:58.59#ibcon#read 5, iclass 6, count 0 2006.183.07:41:58.59#ibcon#about to read 6, iclass 6, count 0 2006.183.07:41:58.59#ibcon#read 6, iclass 6, count 0 2006.183.07:41:58.59#ibcon#end of sib2, iclass 6, count 0 2006.183.07:41:58.59#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:41:58.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:41:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:41:58.59#ibcon#*before write, iclass 6, count 0 2006.183.07:41:58.59#ibcon#enter sib2, iclass 6, count 0 2006.183.07:41:58.59#ibcon#flushed, iclass 6, count 0 2006.183.07:41:58.59#ibcon#about to write, iclass 6, count 0 2006.183.07:41:58.59#ibcon#wrote, iclass 6, count 0 2006.183.07:41:58.59#ibcon#about to read 3, iclass 6, count 0 2006.183.07:41:58.63#ibcon#read 3, iclass 6, count 0 2006.183.07:41:58.63#ibcon#about to read 4, iclass 6, count 0 2006.183.07:41:58.63#ibcon#read 4, iclass 6, count 0 2006.183.07:41:58.63#ibcon#about to read 5, iclass 6, count 0 2006.183.07:41:58.63#ibcon#read 5, iclass 6, count 0 2006.183.07:41:58.63#ibcon#about to read 6, iclass 6, count 0 2006.183.07:41:58.63#ibcon#read 6, iclass 6, count 0 2006.183.07:41:58.63#ibcon#end of sib2, iclass 6, count 0 2006.183.07:41:58.63#ibcon#*after write, iclass 6, count 0 2006.183.07:41:58.63#ibcon#*before return 0, iclass 6, count 0 2006.183.07:41:58.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:41:58.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:41:58.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:41:58.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:41:58.63$vc4f8/va=3,6 2006.183.07:41:58.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.07:41:58.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.07:41:58.63#ibcon#ireg 11 cls_cnt 2 2006.183.07:41:58.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:41:58.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:41:58.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:41:58.68#ibcon#enter wrdev, iclass 10, count 2 2006.183.07:41:58.68#ibcon#first serial, iclass 10, count 2 2006.183.07:41:58.68#ibcon#enter sib2, iclass 10, count 2 2006.183.07:41:58.68#ibcon#flushed, iclass 10, count 2 2006.183.07:41:58.68#ibcon#about to write, iclass 10, count 2 2006.183.07:41:58.68#ibcon#wrote, iclass 10, count 2 2006.183.07:41:58.68#ibcon#about to read 3, iclass 10, count 2 2006.183.07:41:58.70#ibcon#read 3, iclass 10, count 2 2006.183.07:41:58.70#ibcon#about to read 4, iclass 10, count 2 2006.183.07:41:58.70#ibcon#read 4, iclass 10, count 2 2006.183.07:41:58.70#ibcon#about to read 5, iclass 10, count 2 2006.183.07:41:58.70#ibcon#read 5, iclass 10, count 2 2006.183.07:41:58.70#ibcon#about to read 6, iclass 10, count 2 2006.183.07:41:58.70#ibcon#read 6, iclass 10, count 2 2006.183.07:41:58.70#ibcon#end of sib2, iclass 10, count 2 2006.183.07:41:58.70#ibcon#*mode == 0, iclass 10, count 2 2006.183.07:41:58.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.07:41:58.70#ibcon#[25=AT03-06\r\n] 2006.183.07:41:58.70#ibcon#*before write, iclass 10, count 2 2006.183.07:41:58.70#ibcon#enter sib2, iclass 10, count 2 2006.183.07:41:58.70#ibcon#flushed, iclass 10, count 2 2006.183.07:41:58.70#ibcon#about to write, iclass 10, count 2 2006.183.07:41:58.70#ibcon#wrote, iclass 10, count 2 2006.183.07:41:58.70#ibcon#about to read 3, iclass 10, count 2 2006.183.07:41:58.73#ibcon#read 3, iclass 10, count 2 2006.183.07:41:58.73#ibcon#about to read 4, iclass 10, count 2 2006.183.07:41:58.73#ibcon#read 4, iclass 10, count 2 2006.183.07:41:58.73#ibcon#about to read 5, iclass 10, count 2 2006.183.07:41:58.73#ibcon#read 5, iclass 10, count 2 2006.183.07:41:58.73#ibcon#about to read 6, iclass 10, count 2 2006.183.07:41:58.73#ibcon#read 6, iclass 10, count 2 2006.183.07:41:58.73#ibcon#end of sib2, iclass 10, count 2 2006.183.07:41:58.73#ibcon#*after write, iclass 10, count 2 2006.183.07:41:58.73#ibcon#*before return 0, iclass 10, count 2 2006.183.07:41:58.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:41:58.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:41:58.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.07:41:58.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:41:58.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:41:58.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:41:58.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:41:58.85#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:41:58.85#ibcon#first serial, iclass 10, count 0 2006.183.07:41:58.85#ibcon#enter sib2, iclass 10, count 0 2006.183.07:41:58.85#ibcon#flushed, iclass 10, count 0 2006.183.07:41:58.85#ibcon#about to write, iclass 10, count 0 2006.183.07:41:58.85#ibcon#wrote, iclass 10, count 0 2006.183.07:41:58.85#ibcon#about to read 3, iclass 10, count 0 2006.183.07:41:58.87#ibcon#read 3, iclass 10, count 0 2006.183.07:41:58.87#ibcon#about to read 4, iclass 10, count 0 2006.183.07:41:58.87#ibcon#read 4, iclass 10, count 0 2006.183.07:41:58.87#ibcon#about to read 5, iclass 10, count 0 2006.183.07:41:58.87#ibcon#read 5, iclass 10, count 0 2006.183.07:41:58.87#ibcon#about to read 6, iclass 10, count 0 2006.183.07:41:58.87#ibcon#read 6, iclass 10, count 0 2006.183.07:41:58.87#ibcon#end of sib2, iclass 10, count 0 2006.183.07:41:58.87#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:41:58.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:41:58.87#ibcon#[25=USB\r\n] 2006.183.07:41:58.87#ibcon#*before write, iclass 10, count 0 2006.183.07:41:58.87#ibcon#enter sib2, iclass 10, count 0 2006.183.07:41:58.87#ibcon#flushed, iclass 10, count 0 2006.183.07:41:58.87#ibcon#about to write, iclass 10, count 0 2006.183.07:41:58.87#ibcon#wrote, iclass 10, count 0 2006.183.07:41:58.87#ibcon#about to read 3, iclass 10, count 0 2006.183.07:41:58.90#ibcon#read 3, iclass 10, count 0 2006.183.07:41:58.90#ibcon#about to read 4, iclass 10, count 0 2006.183.07:41:58.90#ibcon#read 4, iclass 10, count 0 2006.183.07:41:58.90#ibcon#about to read 5, iclass 10, count 0 2006.183.07:41:58.90#ibcon#read 5, iclass 10, count 0 2006.183.07:41:58.90#ibcon#about to read 6, iclass 10, count 0 2006.183.07:41:58.90#ibcon#read 6, iclass 10, count 0 2006.183.07:41:58.90#ibcon#end of sib2, iclass 10, count 0 2006.183.07:41:58.90#ibcon#*after write, iclass 10, count 0 2006.183.07:41:58.90#ibcon#*before return 0, iclass 10, count 0 2006.183.07:41:58.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:41:58.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:41:58.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:41:58.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:41:58.90$vc4f8/valo=4,832.99 2006.183.07:41:58.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.07:41:58.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.07:41:58.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:41:58.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:41:58.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:41:58.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:41:58.90#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:41:58.90#ibcon#first serial, iclass 12, count 0 2006.183.07:41:58.90#ibcon#enter sib2, iclass 12, count 0 2006.183.07:41:58.90#ibcon#flushed, iclass 12, count 0 2006.183.07:41:58.90#ibcon#about to write, iclass 12, count 0 2006.183.07:41:58.90#ibcon#wrote, iclass 12, count 0 2006.183.07:41:58.90#ibcon#about to read 3, iclass 12, count 0 2006.183.07:41:58.92#ibcon#read 3, iclass 12, count 0 2006.183.07:41:58.92#ibcon#about to read 4, iclass 12, count 0 2006.183.07:41:58.92#ibcon#read 4, iclass 12, count 0 2006.183.07:41:58.92#ibcon#about to read 5, iclass 12, count 0 2006.183.07:41:58.92#ibcon#read 5, iclass 12, count 0 2006.183.07:41:58.92#ibcon#about to read 6, iclass 12, count 0 2006.183.07:41:58.92#ibcon#read 6, iclass 12, count 0 2006.183.07:41:58.92#ibcon#end of sib2, iclass 12, count 0 2006.183.07:41:58.92#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:41:58.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:41:58.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:41:58.92#ibcon#*before write, iclass 12, count 0 2006.183.07:41:58.92#ibcon#enter sib2, iclass 12, count 0 2006.183.07:41:58.92#ibcon#flushed, iclass 12, count 0 2006.183.07:41:58.92#ibcon#about to write, iclass 12, count 0 2006.183.07:41:58.92#ibcon#wrote, iclass 12, count 0 2006.183.07:41:58.92#ibcon#about to read 3, iclass 12, count 0 2006.183.07:41:58.96#ibcon#read 3, iclass 12, count 0 2006.183.07:41:58.96#ibcon#about to read 4, iclass 12, count 0 2006.183.07:41:58.96#ibcon#read 4, iclass 12, count 0 2006.183.07:41:58.96#ibcon#about to read 5, iclass 12, count 0 2006.183.07:41:58.96#ibcon#read 5, iclass 12, count 0 2006.183.07:41:58.96#ibcon#about to read 6, iclass 12, count 0 2006.183.07:41:58.96#ibcon#read 6, iclass 12, count 0 2006.183.07:41:58.96#ibcon#end of sib2, iclass 12, count 0 2006.183.07:41:58.96#ibcon#*after write, iclass 12, count 0 2006.183.07:41:58.96#ibcon#*before return 0, iclass 12, count 0 2006.183.07:41:58.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:41:58.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:41:58.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:41:58.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:41:58.96$vc4f8/va=4,7 2006.183.07:41:58.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.07:41:58.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.07:41:58.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:41:58.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:41:59.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:41:59.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:41:59.02#ibcon#enter wrdev, iclass 14, count 2 2006.183.07:41:59.02#ibcon#first serial, iclass 14, count 2 2006.183.07:41:59.02#ibcon#enter sib2, iclass 14, count 2 2006.183.07:41:59.02#ibcon#flushed, iclass 14, count 2 2006.183.07:41:59.02#ibcon#about to write, iclass 14, count 2 2006.183.07:41:59.02#ibcon#wrote, iclass 14, count 2 2006.183.07:41:59.02#ibcon#about to read 3, iclass 14, count 2 2006.183.07:41:59.04#ibcon#read 3, iclass 14, count 2 2006.183.07:41:59.04#ibcon#about to read 4, iclass 14, count 2 2006.183.07:41:59.04#ibcon#read 4, iclass 14, count 2 2006.183.07:41:59.04#ibcon#about to read 5, iclass 14, count 2 2006.183.07:41:59.04#ibcon#read 5, iclass 14, count 2 2006.183.07:41:59.04#ibcon#about to read 6, iclass 14, count 2 2006.183.07:41:59.04#ibcon#read 6, iclass 14, count 2 2006.183.07:41:59.04#ibcon#end of sib2, iclass 14, count 2 2006.183.07:41:59.04#ibcon#*mode == 0, iclass 14, count 2 2006.183.07:41:59.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.07:41:59.04#ibcon#[25=AT04-07\r\n] 2006.183.07:41:59.04#ibcon#*before write, iclass 14, count 2 2006.183.07:41:59.04#ibcon#enter sib2, iclass 14, count 2 2006.183.07:41:59.04#ibcon#flushed, iclass 14, count 2 2006.183.07:41:59.04#ibcon#about to write, iclass 14, count 2 2006.183.07:41:59.04#ibcon#wrote, iclass 14, count 2 2006.183.07:41:59.04#ibcon#about to read 3, iclass 14, count 2 2006.183.07:41:59.07#ibcon#read 3, iclass 14, count 2 2006.183.07:41:59.07#ibcon#about to read 4, iclass 14, count 2 2006.183.07:41:59.07#ibcon#read 4, iclass 14, count 2 2006.183.07:41:59.07#ibcon#about to read 5, iclass 14, count 2 2006.183.07:41:59.07#ibcon#read 5, iclass 14, count 2 2006.183.07:41:59.07#ibcon#about to read 6, iclass 14, count 2 2006.183.07:41:59.07#ibcon#read 6, iclass 14, count 2 2006.183.07:41:59.07#ibcon#end of sib2, iclass 14, count 2 2006.183.07:41:59.07#ibcon#*after write, iclass 14, count 2 2006.183.07:41:59.07#ibcon#*before return 0, iclass 14, count 2 2006.183.07:41:59.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:41:59.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:41:59.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.07:41:59.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:41:59.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:41:59.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:41:59.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:41:59.19#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:41:59.19#ibcon#first serial, iclass 14, count 0 2006.183.07:41:59.19#ibcon#enter sib2, iclass 14, count 0 2006.183.07:41:59.19#ibcon#flushed, iclass 14, count 0 2006.183.07:41:59.19#ibcon#about to write, iclass 14, count 0 2006.183.07:41:59.19#ibcon#wrote, iclass 14, count 0 2006.183.07:41:59.19#ibcon#about to read 3, iclass 14, count 0 2006.183.07:41:59.21#ibcon#read 3, iclass 14, count 0 2006.183.07:41:59.21#ibcon#about to read 4, iclass 14, count 0 2006.183.07:41:59.21#ibcon#read 4, iclass 14, count 0 2006.183.07:41:59.21#ibcon#about to read 5, iclass 14, count 0 2006.183.07:41:59.21#ibcon#read 5, iclass 14, count 0 2006.183.07:41:59.21#ibcon#about to read 6, iclass 14, count 0 2006.183.07:41:59.21#ibcon#read 6, iclass 14, count 0 2006.183.07:41:59.21#ibcon#end of sib2, iclass 14, count 0 2006.183.07:41:59.21#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:41:59.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:41:59.21#ibcon#[25=USB\r\n] 2006.183.07:41:59.21#ibcon#*before write, iclass 14, count 0 2006.183.07:41:59.21#ibcon#enter sib2, iclass 14, count 0 2006.183.07:41:59.21#ibcon#flushed, iclass 14, count 0 2006.183.07:41:59.21#ibcon#about to write, iclass 14, count 0 2006.183.07:41:59.21#ibcon#wrote, iclass 14, count 0 2006.183.07:41:59.21#ibcon#about to read 3, iclass 14, count 0 2006.183.07:41:59.24#ibcon#read 3, iclass 14, count 0 2006.183.07:41:59.24#ibcon#about to read 4, iclass 14, count 0 2006.183.07:41:59.24#ibcon#read 4, iclass 14, count 0 2006.183.07:41:59.24#ibcon#about to read 5, iclass 14, count 0 2006.183.07:41:59.24#ibcon#read 5, iclass 14, count 0 2006.183.07:41:59.24#ibcon#about to read 6, iclass 14, count 0 2006.183.07:41:59.24#ibcon#read 6, iclass 14, count 0 2006.183.07:41:59.24#ibcon#end of sib2, iclass 14, count 0 2006.183.07:41:59.24#ibcon#*after write, iclass 14, count 0 2006.183.07:41:59.24#ibcon#*before return 0, iclass 14, count 0 2006.183.07:41:59.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:41:59.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:41:59.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:41:59.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:41:59.24$vc4f8/valo=5,652.99 2006.183.07:41:59.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.07:41:59.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.07:41:59.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:41:59.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:41:59.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:41:59.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:41:59.24#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:41:59.24#ibcon#first serial, iclass 16, count 0 2006.183.07:41:59.24#ibcon#enter sib2, iclass 16, count 0 2006.183.07:41:59.24#ibcon#flushed, iclass 16, count 0 2006.183.07:41:59.24#ibcon#about to write, iclass 16, count 0 2006.183.07:41:59.24#ibcon#wrote, iclass 16, count 0 2006.183.07:41:59.24#ibcon#about to read 3, iclass 16, count 0 2006.183.07:41:59.26#ibcon#read 3, iclass 16, count 0 2006.183.07:41:59.26#ibcon#about to read 4, iclass 16, count 0 2006.183.07:41:59.26#ibcon#read 4, iclass 16, count 0 2006.183.07:41:59.26#ibcon#about to read 5, iclass 16, count 0 2006.183.07:41:59.26#ibcon#read 5, iclass 16, count 0 2006.183.07:41:59.26#ibcon#about to read 6, iclass 16, count 0 2006.183.07:41:59.26#ibcon#read 6, iclass 16, count 0 2006.183.07:41:59.26#ibcon#end of sib2, iclass 16, count 0 2006.183.07:41:59.26#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:41:59.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:41:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:41:59.26#ibcon#*before write, iclass 16, count 0 2006.183.07:41:59.26#ibcon#enter sib2, iclass 16, count 0 2006.183.07:41:59.26#ibcon#flushed, iclass 16, count 0 2006.183.07:41:59.26#ibcon#about to write, iclass 16, count 0 2006.183.07:41:59.26#ibcon#wrote, iclass 16, count 0 2006.183.07:41:59.26#ibcon#about to read 3, iclass 16, count 0 2006.183.07:41:59.30#ibcon#read 3, iclass 16, count 0 2006.183.07:41:59.30#ibcon#about to read 4, iclass 16, count 0 2006.183.07:41:59.30#ibcon#read 4, iclass 16, count 0 2006.183.07:41:59.30#ibcon#about to read 5, iclass 16, count 0 2006.183.07:41:59.30#ibcon#read 5, iclass 16, count 0 2006.183.07:41:59.30#ibcon#about to read 6, iclass 16, count 0 2006.183.07:41:59.30#ibcon#read 6, iclass 16, count 0 2006.183.07:41:59.30#ibcon#end of sib2, iclass 16, count 0 2006.183.07:41:59.30#ibcon#*after write, iclass 16, count 0 2006.183.07:41:59.30#ibcon#*before return 0, iclass 16, count 0 2006.183.07:41:59.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:41:59.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:41:59.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:41:59.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:41:59.30$vc4f8/va=5,7 2006.183.07:41:59.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.07:41:59.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.07:41:59.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:41:59.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:41:59.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:41:59.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:41:59.36#ibcon#enter wrdev, iclass 18, count 2 2006.183.07:41:59.36#ibcon#first serial, iclass 18, count 2 2006.183.07:41:59.36#ibcon#enter sib2, iclass 18, count 2 2006.183.07:41:59.36#ibcon#flushed, iclass 18, count 2 2006.183.07:41:59.36#ibcon#about to write, iclass 18, count 2 2006.183.07:41:59.36#ibcon#wrote, iclass 18, count 2 2006.183.07:41:59.36#ibcon#about to read 3, iclass 18, count 2 2006.183.07:41:59.38#ibcon#read 3, iclass 18, count 2 2006.183.07:41:59.38#ibcon#about to read 4, iclass 18, count 2 2006.183.07:41:59.38#ibcon#read 4, iclass 18, count 2 2006.183.07:41:59.38#ibcon#about to read 5, iclass 18, count 2 2006.183.07:41:59.38#ibcon#read 5, iclass 18, count 2 2006.183.07:41:59.38#ibcon#about to read 6, iclass 18, count 2 2006.183.07:41:59.38#ibcon#read 6, iclass 18, count 2 2006.183.07:41:59.38#ibcon#end of sib2, iclass 18, count 2 2006.183.07:41:59.38#ibcon#*mode == 0, iclass 18, count 2 2006.183.07:41:59.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.07:41:59.38#ibcon#[25=AT05-07\r\n] 2006.183.07:41:59.38#ibcon#*before write, iclass 18, count 2 2006.183.07:41:59.38#ibcon#enter sib2, iclass 18, count 2 2006.183.07:41:59.38#ibcon#flushed, iclass 18, count 2 2006.183.07:41:59.38#ibcon#about to write, iclass 18, count 2 2006.183.07:41:59.38#ibcon#wrote, iclass 18, count 2 2006.183.07:41:59.38#ibcon#about to read 3, iclass 18, count 2 2006.183.07:41:59.41#ibcon#read 3, iclass 18, count 2 2006.183.07:41:59.41#ibcon#about to read 4, iclass 18, count 2 2006.183.07:41:59.41#ibcon#read 4, iclass 18, count 2 2006.183.07:41:59.41#ibcon#about to read 5, iclass 18, count 2 2006.183.07:41:59.41#ibcon#read 5, iclass 18, count 2 2006.183.07:41:59.41#ibcon#about to read 6, iclass 18, count 2 2006.183.07:41:59.41#ibcon#read 6, iclass 18, count 2 2006.183.07:41:59.41#ibcon#end of sib2, iclass 18, count 2 2006.183.07:41:59.41#ibcon#*after write, iclass 18, count 2 2006.183.07:41:59.41#ibcon#*before return 0, iclass 18, count 2 2006.183.07:41:59.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:41:59.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:41:59.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.07:41:59.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:41:59.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:41:59.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:41:59.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:41:59.53#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:41:59.53#ibcon#first serial, iclass 18, count 0 2006.183.07:41:59.53#ibcon#enter sib2, iclass 18, count 0 2006.183.07:41:59.53#ibcon#flushed, iclass 18, count 0 2006.183.07:41:59.53#ibcon#about to write, iclass 18, count 0 2006.183.07:41:59.53#ibcon#wrote, iclass 18, count 0 2006.183.07:41:59.53#ibcon#about to read 3, iclass 18, count 0 2006.183.07:41:59.55#ibcon#read 3, iclass 18, count 0 2006.183.07:41:59.55#ibcon#about to read 4, iclass 18, count 0 2006.183.07:41:59.55#ibcon#read 4, iclass 18, count 0 2006.183.07:41:59.55#ibcon#about to read 5, iclass 18, count 0 2006.183.07:41:59.55#ibcon#read 5, iclass 18, count 0 2006.183.07:41:59.55#ibcon#about to read 6, iclass 18, count 0 2006.183.07:41:59.55#ibcon#read 6, iclass 18, count 0 2006.183.07:41:59.55#ibcon#end of sib2, iclass 18, count 0 2006.183.07:41:59.55#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:41:59.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:41:59.55#ibcon#[25=USB\r\n] 2006.183.07:41:59.55#ibcon#*before write, iclass 18, count 0 2006.183.07:41:59.55#ibcon#enter sib2, iclass 18, count 0 2006.183.07:41:59.55#ibcon#flushed, iclass 18, count 0 2006.183.07:41:59.55#ibcon#about to write, iclass 18, count 0 2006.183.07:41:59.55#ibcon#wrote, iclass 18, count 0 2006.183.07:41:59.55#ibcon#about to read 3, iclass 18, count 0 2006.183.07:41:59.58#ibcon#read 3, iclass 18, count 0 2006.183.07:41:59.58#ibcon#about to read 4, iclass 18, count 0 2006.183.07:41:59.58#ibcon#read 4, iclass 18, count 0 2006.183.07:41:59.58#ibcon#about to read 5, iclass 18, count 0 2006.183.07:41:59.58#ibcon#read 5, iclass 18, count 0 2006.183.07:41:59.58#ibcon#about to read 6, iclass 18, count 0 2006.183.07:41:59.58#ibcon#read 6, iclass 18, count 0 2006.183.07:41:59.58#ibcon#end of sib2, iclass 18, count 0 2006.183.07:41:59.58#ibcon#*after write, iclass 18, count 0 2006.183.07:41:59.58#ibcon#*before return 0, iclass 18, count 0 2006.183.07:41:59.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:41:59.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:41:59.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:41:59.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:41:59.58$vc4f8/valo=6,772.99 2006.183.07:41:59.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.07:41:59.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.07:41:59.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:41:59.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:41:59.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:41:59.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:41:59.58#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:41:59.58#ibcon#first serial, iclass 20, count 0 2006.183.07:41:59.58#ibcon#enter sib2, iclass 20, count 0 2006.183.07:41:59.58#ibcon#flushed, iclass 20, count 0 2006.183.07:41:59.58#ibcon#about to write, iclass 20, count 0 2006.183.07:41:59.58#ibcon#wrote, iclass 20, count 0 2006.183.07:41:59.58#ibcon#about to read 3, iclass 20, count 0 2006.183.07:41:59.61#ibcon#read 3, iclass 20, count 0 2006.183.07:41:59.61#ibcon#about to read 4, iclass 20, count 0 2006.183.07:41:59.61#ibcon#read 4, iclass 20, count 0 2006.183.07:41:59.61#ibcon#about to read 5, iclass 20, count 0 2006.183.07:41:59.61#ibcon#read 5, iclass 20, count 0 2006.183.07:41:59.61#ibcon#about to read 6, iclass 20, count 0 2006.183.07:41:59.61#ibcon#read 6, iclass 20, count 0 2006.183.07:41:59.61#ibcon#end of sib2, iclass 20, count 0 2006.183.07:41:59.61#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:41:59.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:41:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:41:59.61#ibcon#*before write, iclass 20, count 0 2006.183.07:41:59.61#ibcon#enter sib2, iclass 20, count 0 2006.183.07:41:59.61#ibcon#flushed, iclass 20, count 0 2006.183.07:41:59.61#ibcon#about to write, iclass 20, count 0 2006.183.07:41:59.61#ibcon#wrote, iclass 20, count 0 2006.183.07:41:59.61#ibcon#about to read 3, iclass 20, count 0 2006.183.07:41:59.65#ibcon#read 3, iclass 20, count 0 2006.183.07:41:59.65#ibcon#about to read 4, iclass 20, count 0 2006.183.07:41:59.65#ibcon#read 4, iclass 20, count 0 2006.183.07:41:59.65#ibcon#about to read 5, iclass 20, count 0 2006.183.07:41:59.65#ibcon#read 5, iclass 20, count 0 2006.183.07:41:59.65#ibcon#about to read 6, iclass 20, count 0 2006.183.07:41:59.65#ibcon#read 6, iclass 20, count 0 2006.183.07:41:59.65#ibcon#end of sib2, iclass 20, count 0 2006.183.07:41:59.65#ibcon#*after write, iclass 20, count 0 2006.183.07:41:59.65#ibcon#*before return 0, iclass 20, count 0 2006.183.07:41:59.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:41:59.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:41:59.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:41:59.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:41:59.65$vc4f8/va=6,6 2006.183.07:41:59.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.07:41:59.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.07:41:59.65#ibcon#ireg 11 cls_cnt 2 2006.183.07:41:59.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:41:59.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:41:59.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:41:59.70#ibcon#enter wrdev, iclass 22, count 2 2006.183.07:41:59.70#ibcon#first serial, iclass 22, count 2 2006.183.07:41:59.70#ibcon#enter sib2, iclass 22, count 2 2006.183.07:41:59.70#ibcon#flushed, iclass 22, count 2 2006.183.07:41:59.70#ibcon#about to write, iclass 22, count 2 2006.183.07:41:59.70#ibcon#wrote, iclass 22, count 2 2006.183.07:41:59.70#ibcon#about to read 3, iclass 22, count 2 2006.183.07:41:59.72#ibcon#read 3, iclass 22, count 2 2006.183.07:41:59.72#ibcon#about to read 4, iclass 22, count 2 2006.183.07:41:59.72#ibcon#read 4, iclass 22, count 2 2006.183.07:41:59.72#ibcon#about to read 5, iclass 22, count 2 2006.183.07:41:59.72#ibcon#read 5, iclass 22, count 2 2006.183.07:41:59.72#ibcon#about to read 6, iclass 22, count 2 2006.183.07:41:59.72#ibcon#read 6, iclass 22, count 2 2006.183.07:41:59.72#ibcon#end of sib2, iclass 22, count 2 2006.183.07:41:59.72#ibcon#*mode == 0, iclass 22, count 2 2006.183.07:41:59.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.07:41:59.72#ibcon#[25=AT06-06\r\n] 2006.183.07:41:59.72#ibcon#*before write, iclass 22, count 2 2006.183.07:41:59.72#ibcon#enter sib2, iclass 22, count 2 2006.183.07:41:59.72#ibcon#flushed, iclass 22, count 2 2006.183.07:41:59.72#ibcon#about to write, iclass 22, count 2 2006.183.07:41:59.72#ibcon#wrote, iclass 22, count 2 2006.183.07:41:59.72#ibcon#about to read 3, iclass 22, count 2 2006.183.07:41:59.75#ibcon#read 3, iclass 22, count 2 2006.183.07:41:59.75#ibcon#about to read 4, iclass 22, count 2 2006.183.07:41:59.75#ibcon#read 4, iclass 22, count 2 2006.183.07:41:59.75#ibcon#about to read 5, iclass 22, count 2 2006.183.07:41:59.75#ibcon#read 5, iclass 22, count 2 2006.183.07:41:59.75#ibcon#about to read 6, iclass 22, count 2 2006.183.07:41:59.75#ibcon#read 6, iclass 22, count 2 2006.183.07:41:59.75#ibcon#end of sib2, iclass 22, count 2 2006.183.07:41:59.75#ibcon#*after write, iclass 22, count 2 2006.183.07:41:59.75#ibcon#*before return 0, iclass 22, count 2 2006.183.07:41:59.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:41:59.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:41:59.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.07:41:59.75#ibcon#ireg 7 cls_cnt 0 2006.183.07:41:59.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:41:59.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:41:59.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:41:59.87#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:41:59.87#ibcon#first serial, iclass 22, count 0 2006.183.07:41:59.87#ibcon#enter sib2, iclass 22, count 0 2006.183.07:41:59.87#ibcon#flushed, iclass 22, count 0 2006.183.07:41:59.87#ibcon#about to write, iclass 22, count 0 2006.183.07:41:59.87#ibcon#wrote, iclass 22, count 0 2006.183.07:41:59.87#ibcon#about to read 3, iclass 22, count 0 2006.183.07:41:59.89#ibcon#read 3, iclass 22, count 0 2006.183.07:41:59.89#ibcon#about to read 4, iclass 22, count 0 2006.183.07:41:59.89#ibcon#read 4, iclass 22, count 0 2006.183.07:41:59.89#ibcon#about to read 5, iclass 22, count 0 2006.183.07:41:59.89#ibcon#read 5, iclass 22, count 0 2006.183.07:41:59.89#ibcon#about to read 6, iclass 22, count 0 2006.183.07:41:59.89#ibcon#read 6, iclass 22, count 0 2006.183.07:41:59.89#ibcon#end of sib2, iclass 22, count 0 2006.183.07:41:59.89#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:41:59.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:41:59.89#ibcon#[25=USB\r\n] 2006.183.07:41:59.89#ibcon#*before write, iclass 22, count 0 2006.183.07:41:59.89#ibcon#enter sib2, iclass 22, count 0 2006.183.07:41:59.89#ibcon#flushed, iclass 22, count 0 2006.183.07:41:59.89#ibcon#about to write, iclass 22, count 0 2006.183.07:41:59.89#ibcon#wrote, iclass 22, count 0 2006.183.07:41:59.89#ibcon#about to read 3, iclass 22, count 0 2006.183.07:41:59.92#ibcon#read 3, iclass 22, count 0 2006.183.07:41:59.92#ibcon#about to read 4, iclass 22, count 0 2006.183.07:41:59.92#ibcon#read 4, iclass 22, count 0 2006.183.07:41:59.92#ibcon#about to read 5, iclass 22, count 0 2006.183.07:41:59.92#ibcon#read 5, iclass 22, count 0 2006.183.07:41:59.92#ibcon#about to read 6, iclass 22, count 0 2006.183.07:41:59.92#ibcon#read 6, iclass 22, count 0 2006.183.07:41:59.92#ibcon#end of sib2, iclass 22, count 0 2006.183.07:41:59.92#ibcon#*after write, iclass 22, count 0 2006.183.07:41:59.92#ibcon#*before return 0, iclass 22, count 0 2006.183.07:41:59.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:41:59.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:41:59.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:41:59.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:41:59.92$vc4f8/valo=7,832.99 2006.183.07:41:59.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.07:41:59.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.07:41:59.92#ibcon#ireg 17 cls_cnt 0 2006.183.07:41:59.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:41:59.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:41:59.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:41:59.92#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:41:59.92#ibcon#first serial, iclass 24, count 0 2006.183.07:41:59.92#ibcon#enter sib2, iclass 24, count 0 2006.183.07:41:59.92#ibcon#flushed, iclass 24, count 0 2006.183.07:41:59.92#ibcon#about to write, iclass 24, count 0 2006.183.07:41:59.92#ibcon#wrote, iclass 24, count 0 2006.183.07:41:59.92#ibcon#about to read 3, iclass 24, count 0 2006.183.07:41:59.94#ibcon#read 3, iclass 24, count 0 2006.183.07:41:59.94#ibcon#about to read 4, iclass 24, count 0 2006.183.07:41:59.94#ibcon#read 4, iclass 24, count 0 2006.183.07:41:59.94#ibcon#about to read 5, iclass 24, count 0 2006.183.07:41:59.94#ibcon#read 5, iclass 24, count 0 2006.183.07:41:59.94#ibcon#about to read 6, iclass 24, count 0 2006.183.07:41:59.94#ibcon#read 6, iclass 24, count 0 2006.183.07:41:59.94#ibcon#end of sib2, iclass 24, count 0 2006.183.07:41:59.94#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:41:59.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:41:59.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:41:59.94#ibcon#*before write, iclass 24, count 0 2006.183.07:41:59.94#ibcon#enter sib2, iclass 24, count 0 2006.183.07:41:59.94#ibcon#flushed, iclass 24, count 0 2006.183.07:41:59.94#ibcon#about to write, iclass 24, count 0 2006.183.07:41:59.94#ibcon#wrote, iclass 24, count 0 2006.183.07:41:59.94#ibcon#about to read 3, iclass 24, count 0 2006.183.07:41:59.98#ibcon#read 3, iclass 24, count 0 2006.183.07:41:59.98#ibcon#about to read 4, iclass 24, count 0 2006.183.07:41:59.98#ibcon#read 4, iclass 24, count 0 2006.183.07:41:59.98#ibcon#about to read 5, iclass 24, count 0 2006.183.07:41:59.98#ibcon#read 5, iclass 24, count 0 2006.183.07:41:59.98#ibcon#about to read 6, iclass 24, count 0 2006.183.07:41:59.98#ibcon#read 6, iclass 24, count 0 2006.183.07:41:59.98#ibcon#end of sib2, iclass 24, count 0 2006.183.07:41:59.98#ibcon#*after write, iclass 24, count 0 2006.183.07:41:59.98#ibcon#*before return 0, iclass 24, count 0 2006.183.07:41:59.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:41:59.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:41:59.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:41:59.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:41:59.98$vc4f8/va=7,6 2006.183.07:41:59.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.07:41:59.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.07:41:59.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:41:59.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:42:00.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:42:00.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:42:00.04#ibcon#enter wrdev, iclass 26, count 2 2006.183.07:42:00.04#ibcon#first serial, iclass 26, count 2 2006.183.07:42:00.04#ibcon#enter sib2, iclass 26, count 2 2006.183.07:42:00.04#ibcon#flushed, iclass 26, count 2 2006.183.07:42:00.04#ibcon#about to write, iclass 26, count 2 2006.183.07:42:00.04#ibcon#wrote, iclass 26, count 2 2006.183.07:42:00.04#ibcon#about to read 3, iclass 26, count 2 2006.183.07:42:00.06#ibcon#read 3, iclass 26, count 2 2006.183.07:42:00.06#ibcon#about to read 4, iclass 26, count 2 2006.183.07:42:00.06#ibcon#read 4, iclass 26, count 2 2006.183.07:42:00.06#ibcon#about to read 5, iclass 26, count 2 2006.183.07:42:00.06#ibcon#read 5, iclass 26, count 2 2006.183.07:42:00.06#ibcon#about to read 6, iclass 26, count 2 2006.183.07:42:00.06#ibcon#read 6, iclass 26, count 2 2006.183.07:42:00.06#ibcon#end of sib2, iclass 26, count 2 2006.183.07:42:00.06#ibcon#*mode == 0, iclass 26, count 2 2006.183.07:42:00.06#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.07:42:00.06#ibcon#[25=AT07-06\r\n] 2006.183.07:42:00.06#ibcon#*before write, iclass 26, count 2 2006.183.07:42:00.06#ibcon#enter sib2, iclass 26, count 2 2006.183.07:42:00.06#ibcon#flushed, iclass 26, count 2 2006.183.07:42:00.06#ibcon#about to write, iclass 26, count 2 2006.183.07:42:00.06#ibcon#wrote, iclass 26, count 2 2006.183.07:42:00.06#ibcon#about to read 3, iclass 26, count 2 2006.183.07:42:00.09#ibcon#read 3, iclass 26, count 2 2006.183.07:42:00.09#ibcon#about to read 4, iclass 26, count 2 2006.183.07:42:00.09#ibcon#read 4, iclass 26, count 2 2006.183.07:42:00.09#ibcon#about to read 5, iclass 26, count 2 2006.183.07:42:00.09#ibcon#read 5, iclass 26, count 2 2006.183.07:42:00.09#ibcon#about to read 6, iclass 26, count 2 2006.183.07:42:00.09#ibcon#read 6, iclass 26, count 2 2006.183.07:42:00.09#ibcon#end of sib2, iclass 26, count 2 2006.183.07:42:00.09#ibcon#*after write, iclass 26, count 2 2006.183.07:42:00.09#ibcon#*before return 0, iclass 26, count 2 2006.183.07:42:00.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:42:00.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:42:00.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.07:42:00.09#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:00.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:42:00.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:42:00.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:42:00.21#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:42:00.21#ibcon#first serial, iclass 26, count 0 2006.183.07:42:00.21#ibcon#enter sib2, iclass 26, count 0 2006.183.07:42:00.21#ibcon#flushed, iclass 26, count 0 2006.183.07:42:00.21#ibcon#about to write, iclass 26, count 0 2006.183.07:42:00.21#ibcon#wrote, iclass 26, count 0 2006.183.07:42:00.21#ibcon#about to read 3, iclass 26, count 0 2006.183.07:42:00.23#ibcon#read 3, iclass 26, count 0 2006.183.07:42:00.23#ibcon#about to read 4, iclass 26, count 0 2006.183.07:42:00.23#ibcon#read 4, iclass 26, count 0 2006.183.07:42:00.23#ibcon#about to read 5, iclass 26, count 0 2006.183.07:42:00.23#ibcon#read 5, iclass 26, count 0 2006.183.07:42:00.23#ibcon#about to read 6, iclass 26, count 0 2006.183.07:42:00.23#ibcon#read 6, iclass 26, count 0 2006.183.07:42:00.23#ibcon#end of sib2, iclass 26, count 0 2006.183.07:42:00.23#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:42:00.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:42:00.23#ibcon#[25=USB\r\n] 2006.183.07:42:00.23#ibcon#*before write, iclass 26, count 0 2006.183.07:42:00.23#ibcon#enter sib2, iclass 26, count 0 2006.183.07:42:00.23#ibcon#flushed, iclass 26, count 0 2006.183.07:42:00.23#ibcon#about to write, iclass 26, count 0 2006.183.07:42:00.23#ibcon#wrote, iclass 26, count 0 2006.183.07:42:00.23#ibcon#about to read 3, iclass 26, count 0 2006.183.07:42:00.26#ibcon#read 3, iclass 26, count 0 2006.183.07:42:00.26#ibcon#about to read 4, iclass 26, count 0 2006.183.07:42:00.26#ibcon#read 4, iclass 26, count 0 2006.183.07:42:00.26#ibcon#about to read 5, iclass 26, count 0 2006.183.07:42:00.26#ibcon#read 5, iclass 26, count 0 2006.183.07:42:00.26#ibcon#about to read 6, iclass 26, count 0 2006.183.07:42:00.26#ibcon#read 6, iclass 26, count 0 2006.183.07:42:00.26#ibcon#end of sib2, iclass 26, count 0 2006.183.07:42:00.26#ibcon#*after write, iclass 26, count 0 2006.183.07:42:00.26#ibcon#*before return 0, iclass 26, count 0 2006.183.07:42:00.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:42:00.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:42:00.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:42:00.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:42:00.26$vc4f8/valo=8,852.99 2006.183.07:42:00.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.07:42:00.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.07:42:00.26#ibcon#ireg 17 cls_cnt 0 2006.183.07:42:00.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:42:00.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:42:00.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:42:00.26#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:42:00.26#ibcon#first serial, iclass 28, count 0 2006.183.07:42:00.26#ibcon#enter sib2, iclass 28, count 0 2006.183.07:42:00.26#ibcon#flushed, iclass 28, count 0 2006.183.07:42:00.26#ibcon#about to write, iclass 28, count 0 2006.183.07:42:00.26#ibcon#wrote, iclass 28, count 0 2006.183.07:42:00.26#ibcon#about to read 3, iclass 28, count 0 2006.183.07:42:00.28#ibcon#read 3, iclass 28, count 0 2006.183.07:42:00.28#ibcon#about to read 4, iclass 28, count 0 2006.183.07:42:00.28#ibcon#read 4, iclass 28, count 0 2006.183.07:42:00.28#ibcon#about to read 5, iclass 28, count 0 2006.183.07:42:00.28#ibcon#read 5, iclass 28, count 0 2006.183.07:42:00.28#ibcon#about to read 6, iclass 28, count 0 2006.183.07:42:00.28#ibcon#read 6, iclass 28, count 0 2006.183.07:42:00.28#ibcon#end of sib2, iclass 28, count 0 2006.183.07:42:00.28#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:42:00.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:42:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:42:00.28#ibcon#*before write, iclass 28, count 0 2006.183.07:42:00.28#ibcon#enter sib2, iclass 28, count 0 2006.183.07:42:00.28#ibcon#flushed, iclass 28, count 0 2006.183.07:42:00.28#ibcon#about to write, iclass 28, count 0 2006.183.07:42:00.28#ibcon#wrote, iclass 28, count 0 2006.183.07:42:00.28#ibcon#about to read 3, iclass 28, count 0 2006.183.07:42:00.32#ibcon#read 3, iclass 28, count 0 2006.183.07:42:00.32#ibcon#about to read 4, iclass 28, count 0 2006.183.07:42:00.32#ibcon#read 4, iclass 28, count 0 2006.183.07:42:00.32#ibcon#about to read 5, iclass 28, count 0 2006.183.07:42:00.32#ibcon#read 5, iclass 28, count 0 2006.183.07:42:00.32#ibcon#about to read 6, iclass 28, count 0 2006.183.07:42:00.32#ibcon#read 6, iclass 28, count 0 2006.183.07:42:00.32#ibcon#end of sib2, iclass 28, count 0 2006.183.07:42:00.32#ibcon#*after write, iclass 28, count 0 2006.183.07:42:00.32#ibcon#*before return 0, iclass 28, count 0 2006.183.07:42:00.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:42:00.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:42:00.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:42:00.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:42:00.32$vc4f8/va=8,7 2006.183.07:42:00.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.07:42:00.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.07:42:00.32#ibcon#ireg 11 cls_cnt 2 2006.183.07:42:00.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:42:00.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:42:00.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:42:00.38#ibcon#enter wrdev, iclass 30, count 2 2006.183.07:42:00.38#ibcon#first serial, iclass 30, count 2 2006.183.07:42:00.38#ibcon#enter sib2, iclass 30, count 2 2006.183.07:42:00.38#ibcon#flushed, iclass 30, count 2 2006.183.07:42:00.38#ibcon#about to write, iclass 30, count 2 2006.183.07:42:00.38#ibcon#wrote, iclass 30, count 2 2006.183.07:42:00.38#ibcon#about to read 3, iclass 30, count 2 2006.183.07:42:00.40#ibcon#read 3, iclass 30, count 2 2006.183.07:42:00.40#ibcon#about to read 4, iclass 30, count 2 2006.183.07:42:00.40#ibcon#read 4, iclass 30, count 2 2006.183.07:42:00.40#ibcon#about to read 5, iclass 30, count 2 2006.183.07:42:00.40#ibcon#read 5, iclass 30, count 2 2006.183.07:42:00.40#ibcon#about to read 6, iclass 30, count 2 2006.183.07:42:00.40#ibcon#read 6, iclass 30, count 2 2006.183.07:42:00.40#ibcon#end of sib2, iclass 30, count 2 2006.183.07:42:00.40#ibcon#*mode == 0, iclass 30, count 2 2006.183.07:42:00.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.07:42:00.40#ibcon#[25=AT08-07\r\n] 2006.183.07:42:00.40#ibcon#*before write, iclass 30, count 2 2006.183.07:42:00.40#ibcon#enter sib2, iclass 30, count 2 2006.183.07:42:00.40#ibcon#flushed, iclass 30, count 2 2006.183.07:42:00.40#ibcon#about to write, iclass 30, count 2 2006.183.07:42:00.40#ibcon#wrote, iclass 30, count 2 2006.183.07:42:00.40#ibcon#about to read 3, iclass 30, count 2 2006.183.07:42:00.43#ibcon#read 3, iclass 30, count 2 2006.183.07:42:00.43#ibcon#about to read 4, iclass 30, count 2 2006.183.07:42:00.43#ibcon#read 4, iclass 30, count 2 2006.183.07:42:00.43#ibcon#about to read 5, iclass 30, count 2 2006.183.07:42:00.43#ibcon#read 5, iclass 30, count 2 2006.183.07:42:00.43#ibcon#about to read 6, iclass 30, count 2 2006.183.07:42:00.43#ibcon#read 6, iclass 30, count 2 2006.183.07:42:00.43#ibcon#end of sib2, iclass 30, count 2 2006.183.07:42:00.43#ibcon#*after write, iclass 30, count 2 2006.183.07:42:00.43#ibcon#*before return 0, iclass 30, count 2 2006.183.07:42:00.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:42:00.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:42:00.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.07:42:00.43#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:00.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:42:00.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:42:00.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:42:00.55#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:42:00.55#ibcon#first serial, iclass 30, count 0 2006.183.07:42:00.55#ibcon#enter sib2, iclass 30, count 0 2006.183.07:42:00.55#ibcon#flushed, iclass 30, count 0 2006.183.07:42:00.55#ibcon#about to write, iclass 30, count 0 2006.183.07:42:00.55#ibcon#wrote, iclass 30, count 0 2006.183.07:42:00.55#ibcon#about to read 3, iclass 30, count 0 2006.183.07:42:00.57#ibcon#read 3, iclass 30, count 0 2006.183.07:42:00.57#ibcon#about to read 4, iclass 30, count 0 2006.183.07:42:00.57#ibcon#read 4, iclass 30, count 0 2006.183.07:42:00.57#ibcon#about to read 5, iclass 30, count 0 2006.183.07:42:00.57#ibcon#read 5, iclass 30, count 0 2006.183.07:42:00.57#ibcon#about to read 6, iclass 30, count 0 2006.183.07:42:00.57#ibcon#read 6, iclass 30, count 0 2006.183.07:42:00.57#ibcon#end of sib2, iclass 30, count 0 2006.183.07:42:00.57#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:42:00.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:42:00.57#ibcon#[25=USB\r\n] 2006.183.07:42:00.57#ibcon#*before write, iclass 30, count 0 2006.183.07:42:00.57#ibcon#enter sib2, iclass 30, count 0 2006.183.07:42:00.57#ibcon#flushed, iclass 30, count 0 2006.183.07:42:00.57#ibcon#about to write, iclass 30, count 0 2006.183.07:42:00.57#ibcon#wrote, iclass 30, count 0 2006.183.07:42:00.57#ibcon#about to read 3, iclass 30, count 0 2006.183.07:42:00.60#ibcon#read 3, iclass 30, count 0 2006.183.07:42:00.60#ibcon#about to read 4, iclass 30, count 0 2006.183.07:42:00.60#ibcon#read 4, iclass 30, count 0 2006.183.07:42:00.60#ibcon#about to read 5, iclass 30, count 0 2006.183.07:42:00.60#ibcon#read 5, iclass 30, count 0 2006.183.07:42:00.60#ibcon#about to read 6, iclass 30, count 0 2006.183.07:42:00.60#ibcon#read 6, iclass 30, count 0 2006.183.07:42:00.60#ibcon#end of sib2, iclass 30, count 0 2006.183.07:42:00.60#ibcon#*after write, iclass 30, count 0 2006.183.07:42:00.60#ibcon#*before return 0, iclass 30, count 0 2006.183.07:42:00.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:42:00.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:42:00.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:42:00.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:42:00.60$vc4f8/vblo=1,632.99 2006.183.07:42:00.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.07:42:00.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.07:42:00.60#ibcon#ireg 17 cls_cnt 0 2006.183.07:42:00.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:42:00.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:42:00.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:42:00.60#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:42:00.60#ibcon#first serial, iclass 32, count 0 2006.183.07:42:00.60#ibcon#enter sib2, iclass 32, count 0 2006.183.07:42:00.60#ibcon#flushed, iclass 32, count 0 2006.183.07:42:00.60#ibcon#about to write, iclass 32, count 0 2006.183.07:42:00.60#ibcon#wrote, iclass 32, count 0 2006.183.07:42:00.60#ibcon#about to read 3, iclass 32, count 0 2006.183.07:42:00.62#ibcon#read 3, iclass 32, count 0 2006.183.07:42:00.62#ibcon#about to read 4, iclass 32, count 0 2006.183.07:42:00.62#ibcon#read 4, iclass 32, count 0 2006.183.07:42:00.62#ibcon#about to read 5, iclass 32, count 0 2006.183.07:42:00.62#ibcon#read 5, iclass 32, count 0 2006.183.07:42:00.62#ibcon#about to read 6, iclass 32, count 0 2006.183.07:42:00.62#ibcon#read 6, iclass 32, count 0 2006.183.07:42:00.62#ibcon#end of sib2, iclass 32, count 0 2006.183.07:42:00.62#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:42:00.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:42:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:42:00.62#ibcon#*before write, iclass 32, count 0 2006.183.07:42:00.62#ibcon#enter sib2, iclass 32, count 0 2006.183.07:42:00.62#ibcon#flushed, iclass 32, count 0 2006.183.07:42:00.62#ibcon#about to write, iclass 32, count 0 2006.183.07:42:00.62#ibcon#wrote, iclass 32, count 0 2006.183.07:42:00.62#ibcon#about to read 3, iclass 32, count 0 2006.183.07:42:00.66#ibcon#read 3, iclass 32, count 0 2006.183.07:42:00.66#ibcon#about to read 4, iclass 32, count 0 2006.183.07:42:00.66#ibcon#read 4, iclass 32, count 0 2006.183.07:42:00.66#ibcon#about to read 5, iclass 32, count 0 2006.183.07:42:00.66#ibcon#read 5, iclass 32, count 0 2006.183.07:42:00.66#ibcon#about to read 6, iclass 32, count 0 2006.183.07:42:00.66#ibcon#read 6, iclass 32, count 0 2006.183.07:42:00.66#ibcon#end of sib2, iclass 32, count 0 2006.183.07:42:00.66#ibcon#*after write, iclass 32, count 0 2006.183.07:42:00.66#ibcon#*before return 0, iclass 32, count 0 2006.183.07:42:00.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:42:00.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:42:00.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:42:00.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:42:00.66$vc4f8/vb=1,4 2006.183.07:42:00.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.07:42:00.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.07:42:00.66#ibcon#ireg 11 cls_cnt 2 2006.183.07:42:00.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:42:00.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:42:00.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:42:00.66#ibcon#enter wrdev, iclass 34, count 2 2006.183.07:42:00.66#ibcon#first serial, iclass 34, count 2 2006.183.07:42:00.66#ibcon#enter sib2, iclass 34, count 2 2006.183.07:42:00.66#ibcon#flushed, iclass 34, count 2 2006.183.07:42:00.66#ibcon#about to write, iclass 34, count 2 2006.183.07:42:00.66#ibcon#wrote, iclass 34, count 2 2006.183.07:42:00.66#ibcon#about to read 3, iclass 34, count 2 2006.183.07:42:00.68#ibcon#read 3, iclass 34, count 2 2006.183.07:42:00.68#ibcon#about to read 4, iclass 34, count 2 2006.183.07:42:00.68#ibcon#read 4, iclass 34, count 2 2006.183.07:42:00.68#ibcon#about to read 5, iclass 34, count 2 2006.183.07:42:00.68#ibcon#read 5, iclass 34, count 2 2006.183.07:42:00.68#ibcon#about to read 6, iclass 34, count 2 2006.183.07:42:00.68#ibcon#read 6, iclass 34, count 2 2006.183.07:42:00.68#ibcon#end of sib2, iclass 34, count 2 2006.183.07:42:00.68#ibcon#*mode == 0, iclass 34, count 2 2006.183.07:42:00.68#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.07:42:00.68#ibcon#[27=AT01-04\r\n] 2006.183.07:42:00.68#ibcon#*before write, iclass 34, count 2 2006.183.07:42:00.68#ibcon#enter sib2, iclass 34, count 2 2006.183.07:42:00.68#ibcon#flushed, iclass 34, count 2 2006.183.07:42:00.68#ibcon#about to write, iclass 34, count 2 2006.183.07:42:00.68#ibcon#wrote, iclass 34, count 2 2006.183.07:42:00.68#ibcon#about to read 3, iclass 34, count 2 2006.183.07:42:00.71#ibcon#read 3, iclass 34, count 2 2006.183.07:42:00.71#ibcon#about to read 4, iclass 34, count 2 2006.183.07:42:00.71#ibcon#read 4, iclass 34, count 2 2006.183.07:42:00.71#ibcon#about to read 5, iclass 34, count 2 2006.183.07:42:00.71#ibcon#read 5, iclass 34, count 2 2006.183.07:42:00.71#ibcon#about to read 6, iclass 34, count 2 2006.183.07:42:00.71#ibcon#read 6, iclass 34, count 2 2006.183.07:42:00.71#ibcon#end of sib2, iclass 34, count 2 2006.183.07:42:00.71#ibcon#*after write, iclass 34, count 2 2006.183.07:42:00.71#ibcon#*before return 0, iclass 34, count 2 2006.183.07:42:00.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:42:00.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:42:00.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.07:42:00.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:00.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:42:00.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:42:00.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:42:00.83#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:42:00.83#ibcon#first serial, iclass 34, count 0 2006.183.07:42:00.83#ibcon#enter sib2, iclass 34, count 0 2006.183.07:42:00.83#ibcon#flushed, iclass 34, count 0 2006.183.07:42:00.83#ibcon#about to write, iclass 34, count 0 2006.183.07:42:00.83#ibcon#wrote, iclass 34, count 0 2006.183.07:42:00.83#ibcon#about to read 3, iclass 34, count 0 2006.183.07:42:00.85#ibcon#read 3, iclass 34, count 0 2006.183.07:42:00.85#ibcon#about to read 4, iclass 34, count 0 2006.183.07:42:00.85#ibcon#read 4, iclass 34, count 0 2006.183.07:42:00.85#ibcon#about to read 5, iclass 34, count 0 2006.183.07:42:00.85#ibcon#read 5, iclass 34, count 0 2006.183.07:42:00.85#ibcon#about to read 6, iclass 34, count 0 2006.183.07:42:00.85#ibcon#read 6, iclass 34, count 0 2006.183.07:42:00.85#ibcon#end of sib2, iclass 34, count 0 2006.183.07:42:00.85#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:42:00.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:42:00.85#ibcon#[27=USB\r\n] 2006.183.07:42:00.85#ibcon#*before write, iclass 34, count 0 2006.183.07:42:00.85#ibcon#enter sib2, iclass 34, count 0 2006.183.07:42:00.85#ibcon#flushed, iclass 34, count 0 2006.183.07:42:00.85#ibcon#about to write, iclass 34, count 0 2006.183.07:42:00.85#ibcon#wrote, iclass 34, count 0 2006.183.07:42:00.85#ibcon#about to read 3, iclass 34, count 0 2006.183.07:42:00.88#ibcon#read 3, iclass 34, count 0 2006.183.07:42:00.88#ibcon#about to read 4, iclass 34, count 0 2006.183.07:42:00.88#ibcon#read 4, iclass 34, count 0 2006.183.07:42:00.88#ibcon#about to read 5, iclass 34, count 0 2006.183.07:42:00.88#ibcon#read 5, iclass 34, count 0 2006.183.07:42:00.88#ibcon#about to read 6, iclass 34, count 0 2006.183.07:42:00.88#ibcon#read 6, iclass 34, count 0 2006.183.07:42:00.88#ibcon#end of sib2, iclass 34, count 0 2006.183.07:42:00.88#ibcon#*after write, iclass 34, count 0 2006.183.07:42:00.88#ibcon#*before return 0, iclass 34, count 0 2006.183.07:42:00.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:42:00.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:42:00.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:42:00.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:42:00.88$vc4f8/vblo=2,640.99 2006.183.07:42:00.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:42:00.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:42:00.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:42:00.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:42:00.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:42:00.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:42:00.88#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:42:00.88#ibcon#first serial, iclass 36, count 0 2006.183.07:42:00.88#ibcon#enter sib2, iclass 36, count 0 2006.183.07:42:00.88#ibcon#flushed, iclass 36, count 0 2006.183.07:42:00.88#ibcon#about to write, iclass 36, count 0 2006.183.07:42:00.88#ibcon#wrote, iclass 36, count 0 2006.183.07:42:00.88#ibcon#about to read 3, iclass 36, count 0 2006.183.07:42:00.90#ibcon#read 3, iclass 36, count 0 2006.183.07:42:00.90#ibcon#about to read 4, iclass 36, count 0 2006.183.07:42:00.90#ibcon#read 4, iclass 36, count 0 2006.183.07:42:00.90#ibcon#about to read 5, iclass 36, count 0 2006.183.07:42:00.90#ibcon#read 5, iclass 36, count 0 2006.183.07:42:00.90#ibcon#about to read 6, iclass 36, count 0 2006.183.07:42:00.90#ibcon#read 6, iclass 36, count 0 2006.183.07:42:00.90#ibcon#end of sib2, iclass 36, count 0 2006.183.07:42:00.90#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:42:00.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:42:00.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:42:00.90#ibcon#*before write, iclass 36, count 0 2006.183.07:42:00.90#ibcon#enter sib2, iclass 36, count 0 2006.183.07:42:00.90#ibcon#flushed, iclass 36, count 0 2006.183.07:42:00.90#ibcon#about to write, iclass 36, count 0 2006.183.07:42:00.90#ibcon#wrote, iclass 36, count 0 2006.183.07:42:00.90#ibcon#about to read 3, iclass 36, count 0 2006.183.07:42:00.94#ibcon#read 3, iclass 36, count 0 2006.183.07:42:00.94#ibcon#about to read 4, iclass 36, count 0 2006.183.07:42:00.94#ibcon#read 4, iclass 36, count 0 2006.183.07:42:00.94#ibcon#about to read 5, iclass 36, count 0 2006.183.07:42:00.94#ibcon#read 5, iclass 36, count 0 2006.183.07:42:00.94#ibcon#about to read 6, iclass 36, count 0 2006.183.07:42:00.94#ibcon#read 6, iclass 36, count 0 2006.183.07:42:00.94#ibcon#end of sib2, iclass 36, count 0 2006.183.07:42:00.94#ibcon#*after write, iclass 36, count 0 2006.183.07:42:00.94#ibcon#*before return 0, iclass 36, count 0 2006.183.07:42:00.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:42:00.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:42:00.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:42:00.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:42:00.94$vc4f8/vb=2,4 2006.183.07:42:00.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.07:42:00.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.07:42:00.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:42:00.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:42:01.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:42:01.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:42:01.00#ibcon#enter wrdev, iclass 38, count 2 2006.183.07:42:01.00#ibcon#first serial, iclass 38, count 2 2006.183.07:42:01.00#ibcon#enter sib2, iclass 38, count 2 2006.183.07:42:01.00#ibcon#flushed, iclass 38, count 2 2006.183.07:42:01.00#ibcon#about to write, iclass 38, count 2 2006.183.07:42:01.00#ibcon#wrote, iclass 38, count 2 2006.183.07:42:01.00#ibcon#about to read 3, iclass 38, count 2 2006.183.07:42:01.02#ibcon#read 3, iclass 38, count 2 2006.183.07:42:01.02#ibcon#about to read 4, iclass 38, count 2 2006.183.07:42:01.02#ibcon#read 4, iclass 38, count 2 2006.183.07:42:01.02#ibcon#about to read 5, iclass 38, count 2 2006.183.07:42:01.02#ibcon#read 5, iclass 38, count 2 2006.183.07:42:01.02#ibcon#about to read 6, iclass 38, count 2 2006.183.07:42:01.02#ibcon#read 6, iclass 38, count 2 2006.183.07:42:01.02#ibcon#end of sib2, iclass 38, count 2 2006.183.07:42:01.02#ibcon#*mode == 0, iclass 38, count 2 2006.183.07:42:01.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.07:42:01.02#ibcon#[27=AT02-04\r\n] 2006.183.07:42:01.02#ibcon#*before write, iclass 38, count 2 2006.183.07:42:01.02#ibcon#enter sib2, iclass 38, count 2 2006.183.07:42:01.02#ibcon#flushed, iclass 38, count 2 2006.183.07:42:01.02#ibcon#about to write, iclass 38, count 2 2006.183.07:42:01.02#ibcon#wrote, iclass 38, count 2 2006.183.07:42:01.02#ibcon#about to read 3, iclass 38, count 2 2006.183.07:42:01.05#ibcon#read 3, iclass 38, count 2 2006.183.07:42:01.05#ibcon#about to read 4, iclass 38, count 2 2006.183.07:42:01.05#ibcon#read 4, iclass 38, count 2 2006.183.07:42:01.05#ibcon#about to read 5, iclass 38, count 2 2006.183.07:42:01.05#ibcon#read 5, iclass 38, count 2 2006.183.07:42:01.05#ibcon#about to read 6, iclass 38, count 2 2006.183.07:42:01.05#ibcon#read 6, iclass 38, count 2 2006.183.07:42:01.05#ibcon#end of sib2, iclass 38, count 2 2006.183.07:42:01.05#ibcon#*after write, iclass 38, count 2 2006.183.07:42:01.05#ibcon#*before return 0, iclass 38, count 2 2006.183.07:42:01.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:42:01.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:42:01.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.07:42:01.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:01.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:42:01.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:42:01.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:42:01.17#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:42:01.17#ibcon#first serial, iclass 38, count 0 2006.183.07:42:01.17#ibcon#enter sib2, iclass 38, count 0 2006.183.07:42:01.17#ibcon#flushed, iclass 38, count 0 2006.183.07:42:01.17#ibcon#about to write, iclass 38, count 0 2006.183.07:42:01.17#ibcon#wrote, iclass 38, count 0 2006.183.07:42:01.17#ibcon#about to read 3, iclass 38, count 0 2006.183.07:42:01.21#ibcon#read 3, iclass 38, count 0 2006.183.07:42:01.21#ibcon#about to read 4, iclass 38, count 0 2006.183.07:42:01.21#ibcon#read 4, iclass 38, count 0 2006.183.07:42:01.21#ibcon#about to read 5, iclass 38, count 0 2006.183.07:42:01.21#ibcon#read 5, iclass 38, count 0 2006.183.07:42:01.21#ibcon#about to read 6, iclass 38, count 0 2006.183.07:42:01.21#ibcon#read 6, iclass 38, count 0 2006.183.07:42:01.21#ibcon#end of sib2, iclass 38, count 0 2006.183.07:42:01.21#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:42:01.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:42:01.21#ibcon#[27=USB\r\n] 2006.183.07:42:01.21#ibcon#*before write, iclass 38, count 0 2006.183.07:42:01.21#ibcon#enter sib2, iclass 38, count 0 2006.183.07:42:01.21#ibcon#flushed, iclass 38, count 0 2006.183.07:42:01.21#ibcon#about to write, iclass 38, count 0 2006.183.07:42:01.21#ibcon#wrote, iclass 38, count 0 2006.183.07:42:01.21#ibcon#about to read 3, iclass 38, count 0 2006.183.07:42:01.23#ibcon#read 3, iclass 38, count 0 2006.183.07:42:01.23#ibcon#about to read 4, iclass 38, count 0 2006.183.07:42:01.23#ibcon#read 4, iclass 38, count 0 2006.183.07:42:01.23#ibcon#about to read 5, iclass 38, count 0 2006.183.07:42:01.23#ibcon#read 5, iclass 38, count 0 2006.183.07:42:01.23#ibcon#about to read 6, iclass 38, count 0 2006.183.07:42:01.23#ibcon#read 6, iclass 38, count 0 2006.183.07:42:01.23#ibcon#end of sib2, iclass 38, count 0 2006.183.07:42:01.23#ibcon#*after write, iclass 38, count 0 2006.183.07:42:01.23#ibcon#*before return 0, iclass 38, count 0 2006.183.07:42:01.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:42:01.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:42:01.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:42:01.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:42:01.23$vc4f8/vblo=3,656.99 2006.183.07:42:01.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:42:01.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:42:01.23#ibcon#ireg 17 cls_cnt 0 2006.183.07:42:01.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:42:01.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:42:01.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:42:01.23#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:42:01.23#ibcon#first serial, iclass 40, count 0 2006.183.07:42:01.23#ibcon#enter sib2, iclass 40, count 0 2006.183.07:42:01.23#ibcon#flushed, iclass 40, count 0 2006.183.07:42:01.23#ibcon#about to write, iclass 40, count 0 2006.183.07:42:01.23#ibcon#wrote, iclass 40, count 0 2006.183.07:42:01.23#ibcon#about to read 3, iclass 40, count 0 2006.183.07:42:01.25#ibcon#read 3, iclass 40, count 0 2006.183.07:42:01.25#ibcon#about to read 4, iclass 40, count 0 2006.183.07:42:01.25#ibcon#read 4, iclass 40, count 0 2006.183.07:42:01.25#ibcon#about to read 5, iclass 40, count 0 2006.183.07:42:01.25#ibcon#read 5, iclass 40, count 0 2006.183.07:42:01.25#ibcon#about to read 6, iclass 40, count 0 2006.183.07:42:01.25#ibcon#read 6, iclass 40, count 0 2006.183.07:42:01.25#ibcon#end of sib2, iclass 40, count 0 2006.183.07:42:01.25#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:42:01.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:42:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:42:01.25#ibcon#*before write, iclass 40, count 0 2006.183.07:42:01.25#ibcon#enter sib2, iclass 40, count 0 2006.183.07:42:01.25#ibcon#flushed, iclass 40, count 0 2006.183.07:42:01.25#ibcon#about to write, iclass 40, count 0 2006.183.07:42:01.25#ibcon#wrote, iclass 40, count 0 2006.183.07:42:01.25#ibcon#about to read 3, iclass 40, count 0 2006.183.07:42:01.29#ibcon#read 3, iclass 40, count 0 2006.183.07:42:01.29#ibcon#about to read 4, iclass 40, count 0 2006.183.07:42:01.29#ibcon#read 4, iclass 40, count 0 2006.183.07:42:01.29#ibcon#about to read 5, iclass 40, count 0 2006.183.07:42:01.29#ibcon#read 5, iclass 40, count 0 2006.183.07:42:01.29#ibcon#about to read 6, iclass 40, count 0 2006.183.07:42:01.29#ibcon#read 6, iclass 40, count 0 2006.183.07:42:01.29#ibcon#end of sib2, iclass 40, count 0 2006.183.07:42:01.29#ibcon#*after write, iclass 40, count 0 2006.183.07:42:01.29#ibcon#*before return 0, iclass 40, count 0 2006.183.07:42:01.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:42:01.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:42:01.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:42:01.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:42:01.29$vc4f8/vb=3,4 2006.183.07:42:01.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.07:42:01.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.07:42:01.29#ibcon#ireg 11 cls_cnt 2 2006.183.07:42:01.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:42:01.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:42:01.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:42:01.35#ibcon#enter wrdev, iclass 4, count 2 2006.183.07:42:01.35#ibcon#first serial, iclass 4, count 2 2006.183.07:42:01.35#ibcon#enter sib2, iclass 4, count 2 2006.183.07:42:01.35#ibcon#flushed, iclass 4, count 2 2006.183.07:42:01.35#ibcon#about to write, iclass 4, count 2 2006.183.07:42:01.35#ibcon#wrote, iclass 4, count 2 2006.183.07:42:01.35#ibcon#about to read 3, iclass 4, count 2 2006.183.07:42:01.37#ibcon#read 3, iclass 4, count 2 2006.183.07:42:01.37#ibcon#about to read 4, iclass 4, count 2 2006.183.07:42:01.37#ibcon#read 4, iclass 4, count 2 2006.183.07:42:01.37#ibcon#about to read 5, iclass 4, count 2 2006.183.07:42:01.37#ibcon#read 5, iclass 4, count 2 2006.183.07:42:01.37#ibcon#about to read 6, iclass 4, count 2 2006.183.07:42:01.37#ibcon#read 6, iclass 4, count 2 2006.183.07:42:01.37#ibcon#end of sib2, iclass 4, count 2 2006.183.07:42:01.37#ibcon#*mode == 0, iclass 4, count 2 2006.183.07:42:01.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.07:42:01.37#ibcon#[27=AT03-04\r\n] 2006.183.07:42:01.37#ibcon#*before write, iclass 4, count 2 2006.183.07:42:01.37#ibcon#enter sib2, iclass 4, count 2 2006.183.07:42:01.37#ibcon#flushed, iclass 4, count 2 2006.183.07:42:01.37#ibcon#about to write, iclass 4, count 2 2006.183.07:42:01.37#ibcon#wrote, iclass 4, count 2 2006.183.07:42:01.37#ibcon#about to read 3, iclass 4, count 2 2006.183.07:42:01.40#ibcon#read 3, iclass 4, count 2 2006.183.07:42:01.40#ibcon#about to read 4, iclass 4, count 2 2006.183.07:42:01.40#ibcon#read 4, iclass 4, count 2 2006.183.07:42:01.40#ibcon#about to read 5, iclass 4, count 2 2006.183.07:42:01.40#ibcon#read 5, iclass 4, count 2 2006.183.07:42:01.40#ibcon#about to read 6, iclass 4, count 2 2006.183.07:42:01.40#ibcon#read 6, iclass 4, count 2 2006.183.07:42:01.40#ibcon#end of sib2, iclass 4, count 2 2006.183.07:42:01.40#ibcon#*after write, iclass 4, count 2 2006.183.07:42:01.40#ibcon#*before return 0, iclass 4, count 2 2006.183.07:42:01.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:42:01.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:42:01.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.07:42:01.40#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:01.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:42:01.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:42:01.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:42:01.52#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:42:01.52#ibcon#first serial, iclass 4, count 0 2006.183.07:42:01.52#ibcon#enter sib2, iclass 4, count 0 2006.183.07:42:01.52#ibcon#flushed, iclass 4, count 0 2006.183.07:42:01.52#ibcon#about to write, iclass 4, count 0 2006.183.07:42:01.52#ibcon#wrote, iclass 4, count 0 2006.183.07:42:01.52#ibcon#about to read 3, iclass 4, count 0 2006.183.07:42:01.54#ibcon#read 3, iclass 4, count 0 2006.183.07:42:01.54#ibcon#about to read 4, iclass 4, count 0 2006.183.07:42:01.54#ibcon#read 4, iclass 4, count 0 2006.183.07:42:01.54#ibcon#about to read 5, iclass 4, count 0 2006.183.07:42:01.54#ibcon#read 5, iclass 4, count 0 2006.183.07:42:01.54#ibcon#about to read 6, iclass 4, count 0 2006.183.07:42:01.54#ibcon#read 6, iclass 4, count 0 2006.183.07:42:01.54#ibcon#end of sib2, iclass 4, count 0 2006.183.07:42:01.54#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:42:01.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:42:01.54#ibcon#[27=USB\r\n] 2006.183.07:42:01.54#ibcon#*before write, iclass 4, count 0 2006.183.07:42:01.54#ibcon#enter sib2, iclass 4, count 0 2006.183.07:42:01.54#ibcon#flushed, iclass 4, count 0 2006.183.07:42:01.54#ibcon#about to write, iclass 4, count 0 2006.183.07:42:01.54#ibcon#wrote, iclass 4, count 0 2006.183.07:42:01.54#ibcon#about to read 3, iclass 4, count 0 2006.183.07:42:01.57#ibcon#read 3, iclass 4, count 0 2006.183.07:42:01.57#ibcon#about to read 4, iclass 4, count 0 2006.183.07:42:01.57#ibcon#read 4, iclass 4, count 0 2006.183.07:42:01.57#ibcon#about to read 5, iclass 4, count 0 2006.183.07:42:01.57#ibcon#read 5, iclass 4, count 0 2006.183.07:42:01.57#ibcon#about to read 6, iclass 4, count 0 2006.183.07:42:01.57#ibcon#read 6, iclass 4, count 0 2006.183.07:42:01.57#ibcon#end of sib2, iclass 4, count 0 2006.183.07:42:01.57#ibcon#*after write, iclass 4, count 0 2006.183.07:42:01.57#ibcon#*before return 0, iclass 4, count 0 2006.183.07:42:01.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:42:01.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:42:01.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:42:01.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:42:01.57$vc4f8/vblo=4,712.99 2006.183.07:42:01.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:42:01.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:42:01.57#ibcon#ireg 17 cls_cnt 0 2006.183.07:42:01.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:42:01.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:42:01.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:42:01.57#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:42:01.57#ibcon#first serial, iclass 6, count 0 2006.183.07:42:01.57#ibcon#enter sib2, iclass 6, count 0 2006.183.07:42:01.57#ibcon#flushed, iclass 6, count 0 2006.183.07:42:01.57#ibcon#about to write, iclass 6, count 0 2006.183.07:42:01.57#ibcon#wrote, iclass 6, count 0 2006.183.07:42:01.57#ibcon#about to read 3, iclass 6, count 0 2006.183.07:42:01.59#ibcon#read 3, iclass 6, count 0 2006.183.07:42:01.59#ibcon#about to read 4, iclass 6, count 0 2006.183.07:42:01.59#ibcon#read 4, iclass 6, count 0 2006.183.07:42:01.59#ibcon#about to read 5, iclass 6, count 0 2006.183.07:42:01.59#ibcon#read 5, iclass 6, count 0 2006.183.07:42:01.59#ibcon#about to read 6, iclass 6, count 0 2006.183.07:42:01.59#ibcon#read 6, iclass 6, count 0 2006.183.07:42:01.59#ibcon#end of sib2, iclass 6, count 0 2006.183.07:42:01.59#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:42:01.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:42:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:42:01.59#ibcon#*before write, iclass 6, count 0 2006.183.07:42:01.59#ibcon#enter sib2, iclass 6, count 0 2006.183.07:42:01.59#ibcon#flushed, iclass 6, count 0 2006.183.07:42:01.59#ibcon#about to write, iclass 6, count 0 2006.183.07:42:01.59#ibcon#wrote, iclass 6, count 0 2006.183.07:42:01.59#ibcon#about to read 3, iclass 6, count 0 2006.183.07:42:01.63#ibcon#read 3, iclass 6, count 0 2006.183.07:42:01.63#ibcon#about to read 4, iclass 6, count 0 2006.183.07:42:01.63#ibcon#read 4, iclass 6, count 0 2006.183.07:42:01.63#ibcon#about to read 5, iclass 6, count 0 2006.183.07:42:01.63#ibcon#read 5, iclass 6, count 0 2006.183.07:42:01.63#ibcon#about to read 6, iclass 6, count 0 2006.183.07:42:01.63#ibcon#read 6, iclass 6, count 0 2006.183.07:42:01.63#ibcon#end of sib2, iclass 6, count 0 2006.183.07:42:01.63#ibcon#*after write, iclass 6, count 0 2006.183.07:42:01.63#ibcon#*before return 0, iclass 6, count 0 2006.183.07:42:01.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:42:01.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:42:01.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:42:01.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:42:01.63$vc4f8/vb=4,4 2006.183.07:42:01.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.07:42:01.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.07:42:01.63#ibcon#ireg 11 cls_cnt 2 2006.183.07:42:01.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:42:01.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:42:01.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:42:01.69#ibcon#enter wrdev, iclass 10, count 2 2006.183.07:42:01.69#ibcon#first serial, iclass 10, count 2 2006.183.07:42:01.69#ibcon#enter sib2, iclass 10, count 2 2006.183.07:42:01.69#ibcon#flushed, iclass 10, count 2 2006.183.07:42:01.69#ibcon#about to write, iclass 10, count 2 2006.183.07:42:01.69#ibcon#wrote, iclass 10, count 2 2006.183.07:42:01.69#ibcon#about to read 3, iclass 10, count 2 2006.183.07:42:01.71#ibcon#read 3, iclass 10, count 2 2006.183.07:42:01.71#ibcon#about to read 4, iclass 10, count 2 2006.183.07:42:01.71#ibcon#read 4, iclass 10, count 2 2006.183.07:42:01.71#ibcon#about to read 5, iclass 10, count 2 2006.183.07:42:01.71#ibcon#read 5, iclass 10, count 2 2006.183.07:42:01.71#ibcon#about to read 6, iclass 10, count 2 2006.183.07:42:01.71#ibcon#read 6, iclass 10, count 2 2006.183.07:42:01.71#ibcon#end of sib2, iclass 10, count 2 2006.183.07:42:01.71#ibcon#*mode == 0, iclass 10, count 2 2006.183.07:42:01.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.07:42:01.71#ibcon#[27=AT04-04\r\n] 2006.183.07:42:01.71#ibcon#*before write, iclass 10, count 2 2006.183.07:42:01.71#ibcon#enter sib2, iclass 10, count 2 2006.183.07:42:01.71#ibcon#flushed, iclass 10, count 2 2006.183.07:42:01.71#ibcon#about to write, iclass 10, count 2 2006.183.07:42:01.71#ibcon#wrote, iclass 10, count 2 2006.183.07:42:01.71#ibcon#about to read 3, iclass 10, count 2 2006.183.07:42:01.74#ibcon#read 3, iclass 10, count 2 2006.183.07:42:01.74#ibcon#about to read 4, iclass 10, count 2 2006.183.07:42:01.74#ibcon#read 4, iclass 10, count 2 2006.183.07:42:01.74#ibcon#about to read 5, iclass 10, count 2 2006.183.07:42:01.74#ibcon#read 5, iclass 10, count 2 2006.183.07:42:01.74#ibcon#about to read 6, iclass 10, count 2 2006.183.07:42:01.74#ibcon#read 6, iclass 10, count 2 2006.183.07:42:01.74#ibcon#end of sib2, iclass 10, count 2 2006.183.07:42:01.74#ibcon#*after write, iclass 10, count 2 2006.183.07:42:01.74#ibcon#*before return 0, iclass 10, count 2 2006.183.07:42:01.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:42:01.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:42:01.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.07:42:01.74#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:01.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:42:01.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:42:01.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:42:01.86#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:42:01.86#ibcon#first serial, iclass 10, count 0 2006.183.07:42:01.86#ibcon#enter sib2, iclass 10, count 0 2006.183.07:42:01.86#ibcon#flushed, iclass 10, count 0 2006.183.07:42:01.86#ibcon#about to write, iclass 10, count 0 2006.183.07:42:01.86#ibcon#wrote, iclass 10, count 0 2006.183.07:42:01.86#ibcon#about to read 3, iclass 10, count 0 2006.183.07:42:01.88#ibcon#read 3, iclass 10, count 0 2006.183.07:42:01.88#ibcon#about to read 4, iclass 10, count 0 2006.183.07:42:01.88#ibcon#read 4, iclass 10, count 0 2006.183.07:42:01.88#ibcon#about to read 5, iclass 10, count 0 2006.183.07:42:01.88#ibcon#read 5, iclass 10, count 0 2006.183.07:42:01.88#ibcon#about to read 6, iclass 10, count 0 2006.183.07:42:01.88#ibcon#read 6, iclass 10, count 0 2006.183.07:42:01.88#ibcon#end of sib2, iclass 10, count 0 2006.183.07:42:01.88#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:42:01.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:42:01.88#ibcon#[27=USB\r\n] 2006.183.07:42:01.88#ibcon#*before write, iclass 10, count 0 2006.183.07:42:01.88#ibcon#enter sib2, iclass 10, count 0 2006.183.07:42:01.88#ibcon#flushed, iclass 10, count 0 2006.183.07:42:01.88#ibcon#about to write, iclass 10, count 0 2006.183.07:42:01.88#ibcon#wrote, iclass 10, count 0 2006.183.07:42:01.88#ibcon#about to read 3, iclass 10, count 0 2006.183.07:42:01.91#ibcon#read 3, iclass 10, count 0 2006.183.07:42:01.91#ibcon#about to read 4, iclass 10, count 0 2006.183.07:42:01.91#ibcon#read 4, iclass 10, count 0 2006.183.07:42:01.91#ibcon#about to read 5, iclass 10, count 0 2006.183.07:42:01.91#ibcon#read 5, iclass 10, count 0 2006.183.07:42:01.91#ibcon#about to read 6, iclass 10, count 0 2006.183.07:42:01.91#ibcon#read 6, iclass 10, count 0 2006.183.07:42:01.91#ibcon#end of sib2, iclass 10, count 0 2006.183.07:42:01.91#ibcon#*after write, iclass 10, count 0 2006.183.07:42:01.91#ibcon#*before return 0, iclass 10, count 0 2006.183.07:42:01.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:42:01.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:42:01.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:42:01.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:42:01.91$vc4f8/vblo=5,744.99 2006.183.07:42:01.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.07:42:01.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.07:42:01.91#ibcon#ireg 17 cls_cnt 0 2006.183.07:42:01.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:42:01.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:42:01.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:42:01.91#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:42:01.91#ibcon#first serial, iclass 12, count 0 2006.183.07:42:01.91#ibcon#enter sib2, iclass 12, count 0 2006.183.07:42:01.91#ibcon#flushed, iclass 12, count 0 2006.183.07:42:01.91#ibcon#about to write, iclass 12, count 0 2006.183.07:42:01.91#ibcon#wrote, iclass 12, count 0 2006.183.07:42:01.91#ibcon#about to read 3, iclass 12, count 0 2006.183.07:42:01.94#ibcon#read 3, iclass 12, count 0 2006.183.07:42:01.94#ibcon#about to read 4, iclass 12, count 0 2006.183.07:42:01.94#ibcon#read 4, iclass 12, count 0 2006.183.07:42:01.94#ibcon#about to read 5, iclass 12, count 0 2006.183.07:42:01.94#ibcon#read 5, iclass 12, count 0 2006.183.07:42:01.94#ibcon#about to read 6, iclass 12, count 0 2006.183.07:42:01.94#ibcon#read 6, iclass 12, count 0 2006.183.07:42:01.94#ibcon#end of sib2, iclass 12, count 0 2006.183.07:42:01.94#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:42:01.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:42:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:42:01.94#ibcon#*before write, iclass 12, count 0 2006.183.07:42:01.94#ibcon#enter sib2, iclass 12, count 0 2006.183.07:42:01.94#ibcon#flushed, iclass 12, count 0 2006.183.07:42:01.94#ibcon#about to write, iclass 12, count 0 2006.183.07:42:01.94#ibcon#wrote, iclass 12, count 0 2006.183.07:42:01.94#ibcon#about to read 3, iclass 12, count 0 2006.183.07:42:01.98#ibcon#read 3, iclass 12, count 0 2006.183.07:42:01.98#ibcon#about to read 4, iclass 12, count 0 2006.183.07:42:01.98#ibcon#read 4, iclass 12, count 0 2006.183.07:42:01.98#ibcon#about to read 5, iclass 12, count 0 2006.183.07:42:01.98#ibcon#read 5, iclass 12, count 0 2006.183.07:42:01.98#ibcon#about to read 6, iclass 12, count 0 2006.183.07:42:01.98#ibcon#read 6, iclass 12, count 0 2006.183.07:42:01.98#ibcon#end of sib2, iclass 12, count 0 2006.183.07:42:01.98#ibcon#*after write, iclass 12, count 0 2006.183.07:42:01.98#ibcon#*before return 0, iclass 12, count 0 2006.183.07:42:01.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:42:01.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:42:01.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:42:01.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:42:01.98$vc4f8/vb=5,4 2006.183.07:42:01.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.07:42:01.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.07:42:01.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:42:01.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:42:02.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:42:02.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:42:02.03#ibcon#enter wrdev, iclass 14, count 2 2006.183.07:42:02.03#ibcon#first serial, iclass 14, count 2 2006.183.07:42:02.03#ibcon#enter sib2, iclass 14, count 2 2006.183.07:42:02.03#ibcon#flushed, iclass 14, count 2 2006.183.07:42:02.03#ibcon#about to write, iclass 14, count 2 2006.183.07:42:02.03#ibcon#wrote, iclass 14, count 2 2006.183.07:42:02.03#ibcon#about to read 3, iclass 14, count 2 2006.183.07:42:02.05#ibcon#read 3, iclass 14, count 2 2006.183.07:42:02.05#ibcon#about to read 4, iclass 14, count 2 2006.183.07:42:02.05#ibcon#read 4, iclass 14, count 2 2006.183.07:42:02.05#ibcon#about to read 5, iclass 14, count 2 2006.183.07:42:02.05#ibcon#read 5, iclass 14, count 2 2006.183.07:42:02.05#ibcon#about to read 6, iclass 14, count 2 2006.183.07:42:02.05#ibcon#read 6, iclass 14, count 2 2006.183.07:42:02.05#ibcon#end of sib2, iclass 14, count 2 2006.183.07:42:02.05#ibcon#*mode == 0, iclass 14, count 2 2006.183.07:42:02.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.07:42:02.05#ibcon#[27=AT05-04\r\n] 2006.183.07:42:02.05#ibcon#*before write, iclass 14, count 2 2006.183.07:42:02.05#ibcon#enter sib2, iclass 14, count 2 2006.183.07:42:02.05#ibcon#flushed, iclass 14, count 2 2006.183.07:42:02.05#ibcon#about to write, iclass 14, count 2 2006.183.07:42:02.05#ibcon#wrote, iclass 14, count 2 2006.183.07:42:02.05#ibcon#about to read 3, iclass 14, count 2 2006.183.07:42:02.08#ibcon#read 3, iclass 14, count 2 2006.183.07:42:02.08#ibcon#about to read 4, iclass 14, count 2 2006.183.07:42:02.08#ibcon#read 4, iclass 14, count 2 2006.183.07:42:02.08#ibcon#about to read 5, iclass 14, count 2 2006.183.07:42:02.08#ibcon#read 5, iclass 14, count 2 2006.183.07:42:02.08#ibcon#about to read 6, iclass 14, count 2 2006.183.07:42:02.08#ibcon#read 6, iclass 14, count 2 2006.183.07:42:02.08#ibcon#end of sib2, iclass 14, count 2 2006.183.07:42:02.08#ibcon#*after write, iclass 14, count 2 2006.183.07:42:02.08#ibcon#*before return 0, iclass 14, count 2 2006.183.07:42:02.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:42:02.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:42:02.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.07:42:02.08#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:02.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:42:02.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:42:02.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:42:02.20#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:42:02.20#ibcon#first serial, iclass 14, count 0 2006.183.07:42:02.20#ibcon#enter sib2, iclass 14, count 0 2006.183.07:42:02.20#ibcon#flushed, iclass 14, count 0 2006.183.07:42:02.20#ibcon#about to write, iclass 14, count 0 2006.183.07:42:02.20#ibcon#wrote, iclass 14, count 0 2006.183.07:42:02.20#ibcon#about to read 3, iclass 14, count 0 2006.183.07:42:02.22#ibcon#read 3, iclass 14, count 0 2006.183.07:42:02.22#ibcon#about to read 4, iclass 14, count 0 2006.183.07:42:02.22#ibcon#read 4, iclass 14, count 0 2006.183.07:42:02.22#ibcon#about to read 5, iclass 14, count 0 2006.183.07:42:02.22#ibcon#read 5, iclass 14, count 0 2006.183.07:42:02.22#ibcon#about to read 6, iclass 14, count 0 2006.183.07:42:02.22#ibcon#read 6, iclass 14, count 0 2006.183.07:42:02.22#ibcon#end of sib2, iclass 14, count 0 2006.183.07:42:02.22#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:42:02.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:42:02.22#ibcon#[27=USB\r\n] 2006.183.07:42:02.22#ibcon#*before write, iclass 14, count 0 2006.183.07:42:02.22#ibcon#enter sib2, iclass 14, count 0 2006.183.07:42:02.22#ibcon#flushed, iclass 14, count 0 2006.183.07:42:02.22#ibcon#about to write, iclass 14, count 0 2006.183.07:42:02.22#ibcon#wrote, iclass 14, count 0 2006.183.07:42:02.22#ibcon#about to read 3, iclass 14, count 0 2006.183.07:42:02.25#ibcon#read 3, iclass 14, count 0 2006.183.07:42:02.25#ibcon#about to read 4, iclass 14, count 0 2006.183.07:42:02.25#ibcon#read 4, iclass 14, count 0 2006.183.07:42:02.25#ibcon#about to read 5, iclass 14, count 0 2006.183.07:42:02.25#ibcon#read 5, iclass 14, count 0 2006.183.07:42:02.25#ibcon#about to read 6, iclass 14, count 0 2006.183.07:42:02.25#ibcon#read 6, iclass 14, count 0 2006.183.07:42:02.25#ibcon#end of sib2, iclass 14, count 0 2006.183.07:42:02.25#ibcon#*after write, iclass 14, count 0 2006.183.07:42:02.25#ibcon#*before return 0, iclass 14, count 0 2006.183.07:42:02.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:42:02.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:42:02.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:42:02.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:42:02.25$vc4f8/vblo=6,752.99 2006.183.07:42:02.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.07:42:02.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.07:42:02.25#ibcon#ireg 17 cls_cnt 0 2006.183.07:42:02.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:42:02.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:42:02.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:42:02.25#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:42:02.25#ibcon#first serial, iclass 16, count 0 2006.183.07:42:02.25#ibcon#enter sib2, iclass 16, count 0 2006.183.07:42:02.25#ibcon#flushed, iclass 16, count 0 2006.183.07:42:02.25#ibcon#about to write, iclass 16, count 0 2006.183.07:42:02.25#ibcon#wrote, iclass 16, count 0 2006.183.07:42:02.25#ibcon#about to read 3, iclass 16, count 0 2006.183.07:42:02.27#ibcon#read 3, iclass 16, count 0 2006.183.07:42:02.27#ibcon#about to read 4, iclass 16, count 0 2006.183.07:42:02.27#ibcon#read 4, iclass 16, count 0 2006.183.07:42:02.27#ibcon#about to read 5, iclass 16, count 0 2006.183.07:42:02.27#ibcon#read 5, iclass 16, count 0 2006.183.07:42:02.27#ibcon#about to read 6, iclass 16, count 0 2006.183.07:42:02.27#ibcon#read 6, iclass 16, count 0 2006.183.07:42:02.27#ibcon#end of sib2, iclass 16, count 0 2006.183.07:42:02.27#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:42:02.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:42:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:42:02.27#ibcon#*before write, iclass 16, count 0 2006.183.07:42:02.27#ibcon#enter sib2, iclass 16, count 0 2006.183.07:42:02.27#ibcon#flushed, iclass 16, count 0 2006.183.07:42:02.27#ibcon#about to write, iclass 16, count 0 2006.183.07:42:02.27#ibcon#wrote, iclass 16, count 0 2006.183.07:42:02.27#ibcon#about to read 3, iclass 16, count 0 2006.183.07:42:02.31#ibcon#read 3, iclass 16, count 0 2006.183.07:42:02.31#ibcon#about to read 4, iclass 16, count 0 2006.183.07:42:02.31#ibcon#read 4, iclass 16, count 0 2006.183.07:42:02.31#ibcon#about to read 5, iclass 16, count 0 2006.183.07:42:02.31#ibcon#read 5, iclass 16, count 0 2006.183.07:42:02.31#ibcon#about to read 6, iclass 16, count 0 2006.183.07:42:02.31#ibcon#read 6, iclass 16, count 0 2006.183.07:42:02.31#ibcon#end of sib2, iclass 16, count 0 2006.183.07:42:02.31#ibcon#*after write, iclass 16, count 0 2006.183.07:42:02.31#ibcon#*before return 0, iclass 16, count 0 2006.183.07:42:02.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:42:02.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:42:02.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:42:02.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:42:02.31$vc4f8/vb=6,4 2006.183.07:42:02.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.07:42:02.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.07:42:02.31#ibcon#ireg 11 cls_cnt 2 2006.183.07:42:02.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:42:02.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:42:02.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:42:02.37#ibcon#enter wrdev, iclass 18, count 2 2006.183.07:42:02.37#ibcon#first serial, iclass 18, count 2 2006.183.07:42:02.37#ibcon#enter sib2, iclass 18, count 2 2006.183.07:42:02.37#ibcon#flushed, iclass 18, count 2 2006.183.07:42:02.37#ibcon#about to write, iclass 18, count 2 2006.183.07:42:02.37#ibcon#wrote, iclass 18, count 2 2006.183.07:42:02.37#ibcon#about to read 3, iclass 18, count 2 2006.183.07:42:02.39#ibcon#read 3, iclass 18, count 2 2006.183.07:42:02.39#ibcon#about to read 4, iclass 18, count 2 2006.183.07:42:02.39#ibcon#read 4, iclass 18, count 2 2006.183.07:42:02.39#ibcon#about to read 5, iclass 18, count 2 2006.183.07:42:02.39#ibcon#read 5, iclass 18, count 2 2006.183.07:42:02.39#ibcon#about to read 6, iclass 18, count 2 2006.183.07:42:02.39#ibcon#read 6, iclass 18, count 2 2006.183.07:42:02.39#ibcon#end of sib2, iclass 18, count 2 2006.183.07:42:02.39#ibcon#*mode == 0, iclass 18, count 2 2006.183.07:42:02.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.07:42:02.39#ibcon#[27=AT06-04\r\n] 2006.183.07:42:02.39#ibcon#*before write, iclass 18, count 2 2006.183.07:42:02.39#ibcon#enter sib2, iclass 18, count 2 2006.183.07:42:02.39#ibcon#flushed, iclass 18, count 2 2006.183.07:42:02.39#ibcon#about to write, iclass 18, count 2 2006.183.07:42:02.39#ibcon#wrote, iclass 18, count 2 2006.183.07:42:02.39#ibcon#about to read 3, iclass 18, count 2 2006.183.07:42:02.42#ibcon#read 3, iclass 18, count 2 2006.183.07:42:02.42#ibcon#about to read 4, iclass 18, count 2 2006.183.07:42:02.42#ibcon#read 4, iclass 18, count 2 2006.183.07:42:02.42#ibcon#about to read 5, iclass 18, count 2 2006.183.07:42:02.42#ibcon#read 5, iclass 18, count 2 2006.183.07:42:02.42#ibcon#about to read 6, iclass 18, count 2 2006.183.07:42:02.42#ibcon#read 6, iclass 18, count 2 2006.183.07:42:02.42#ibcon#end of sib2, iclass 18, count 2 2006.183.07:42:02.42#ibcon#*after write, iclass 18, count 2 2006.183.07:42:02.42#ibcon#*before return 0, iclass 18, count 2 2006.183.07:42:02.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:42:02.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:42:02.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.07:42:02.42#ibcon#ireg 7 cls_cnt 0 2006.183.07:42:02.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:42:02.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:42:02.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:42:02.54#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:42:02.54#ibcon#first serial, iclass 18, count 0 2006.183.07:42:02.54#ibcon#enter sib2, iclass 18, count 0 2006.183.07:42:02.54#ibcon#flushed, iclass 18, count 0 2006.183.07:42:02.54#ibcon#about to write, iclass 18, count 0 2006.183.07:42:02.54#ibcon#wrote, iclass 18, count 0 2006.183.07:42:02.54#ibcon#about to read 3, iclass 18, count 0 2006.183.07:42:02.56#ibcon#read 3, iclass 18, count 0 2006.183.07:42:02.56#ibcon#about to read 4, iclass 18, count 0 2006.183.07:42:02.56#ibcon#read 4, iclass 18, count 0 2006.183.07:42:02.56#ibcon#about to read 5, iclass 18, count 0 2006.183.07:42:02.56#ibcon#read 5, iclass 18, count 0 2006.183.07:42:02.56#ibcon#about to read 6, iclass 18, count 0 2006.183.07:42:02.56#ibcon#read 6, iclass 18, count 0 2006.183.07:42:02.56#ibcon#end of sib2, iclass 18, count 0 2006.183.07:42:02.56#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:42:02.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:42:02.56#ibcon#[27=USB\r\n] 2006.183.07:42:02.56#ibcon#*before write, iclass 18, count 0 2006.183.07:42:02.56#ibcon#enter sib2, iclass 18, count 0 2006.183.07:42:02.56#ibcon#flushed, iclass 18, count 0 2006.183.07:42:02.56#ibcon#about to write, iclass 18, count 0 2006.183.07:42:02.56#ibcon#wrote, iclass 18, count 0 2006.183.07:42:02.56#ibcon#about to read 3, iclass 18, count 0 2006.183.07:42:02.59#ibcon#read 3, iclass 18, count 0 2006.183.07:42:02.59#ibcon#about to read 4, iclass 18, count 0 2006.183.07:42:02.59#ibcon#read 4, iclass 18, count 0 2006.183.07:42:02.59#ibcon#about to read 5, iclass 18, count 0 2006.183.07:42:02.59#ibcon#read 5, iclass 18, count 0 2006.183.07:42:02.59#ibcon#about to read 6, iclass 18, count 0 2006.183.07:42:02.59#ibcon#read 6, iclass 18, count 0 2006.183.07:42:02.59#ibcon#end of sib2, iclass 18, count 0 2006.183.07:42:02.59#ibcon#*after write, iclass 18, count 0 2006.183.07:42:02.59#ibcon#*before return 0, iclass 18, count 0 2006.183.07:42:02.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:42:02.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:42:02.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:42:02.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:42:02.59$vc4f8/vabw=wide 2006.183.07:42:02.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.07:42:02.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.07:42:02.59#ibcon#ireg 8 cls_cnt 0 2006.183.07:42:02.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:42:02.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:42:02.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:42:02.59#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:42:02.59#ibcon#first serial, iclass 20, count 0 2006.183.07:42:02.59#ibcon#enter sib2, iclass 20, count 0 2006.183.07:42:02.59#ibcon#flushed, iclass 20, count 0 2006.183.07:42:02.59#ibcon#about to write, iclass 20, count 0 2006.183.07:42:02.59#ibcon#wrote, iclass 20, count 0 2006.183.07:42:02.59#ibcon#about to read 3, iclass 20, count 0 2006.183.07:42:02.61#ibcon#read 3, iclass 20, count 0 2006.183.07:42:02.61#ibcon#about to read 4, iclass 20, count 0 2006.183.07:42:02.61#ibcon#read 4, iclass 20, count 0 2006.183.07:42:02.61#ibcon#about to read 5, iclass 20, count 0 2006.183.07:42:02.61#ibcon#read 5, iclass 20, count 0 2006.183.07:42:02.61#ibcon#about to read 6, iclass 20, count 0 2006.183.07:42:02.61#ibcon#read 6, iclass 20, count 0 2006.183.07:42:02.61#ibcon#end of sib2, iclass 20, count 0 2006.183.07:42:02.61#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:42:02.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:42:02.61#ibcon#[25=BW32\r\n] 2006.183.07:42:02.61#ibcon#*before write, iclass 20, count 0 2006.183.07:42:02.61#ibcon#enter sib2, iclass 20, count 0 2006.183.07:42:02.61#ibcon#flushed, iclass 20, count 0 2006.183.07:42:02.61#ibcon#about to write, iclass 20, count 0 2006.183.07:42:02.61#ibcon#wrote, iclass 20, count 0 2006.183.07:42:02.61#ibcon#about to read 3, iclass 20, count 0 2006.183.07:42:02.64#ibcon#read 3, iclass 20, count 0 2006.183.07:42:02.64#ibcon#about to read 4, iclass 20, count 0 2006.183.07:42:02.64#ibcon#read 4, iclass 20, count 0 2006.183.07:42:02.64#ibcon#about to read 5, iclass 20, count 0 2006.183.07:42:02.64#ibcon#read 5, iclass 20, count 0 2006.183.07:42:02.64#ibcon#about to read 6, iclass 20, count 0 2006.183.07:42:02.64#ibcon#read 6, iclass 20, count 0 2006.183.07:42:02.64#ibcon#end of sib2, iclass 20, count 0 2006.183.07:42:02.64#ibcon#*after write, iclass 20, count 0 2006.183.07:42:02.64#ibcon#*before return 0, iclass 20, count 0 2006.183.07:42:02.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:42:02.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:42:02.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:42:02.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:42:02.64$vc4f8/vbbw=wide 2006.183.07:42:02.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.07:42:02.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.07:42:02.64#ibcon#ireg 8 cls_cnt 0 2006.183.07:42:02.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:42:02.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:42:02.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:42:02.71#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:42:02.71#ibcon#first serial, iclass 22, count 0 2006.183.07:42:02.71#ibcon#enter sib2, iclass 22, count 0 2006.183.07:42:02.71#ibcon#flushed, iclass 22, count 0 2006.183.07:42:02.71#ibcon#about to write, iclass 22, count 0 2006.183.07:42:02.71#ibcon#wrote, iclass 22, count 0 2006.183.07:42:02.71#ibcon#about to read 3, iclass 22, count 0 2006.183.07:42:02.73#ibcon#read 3, iclass 22, count 0 2006.183.07:42:02.73#ibcon#about to read 4, iclass 22, count 0 2006.183.07:42:02.73#ibcon#read 4, iclass 22, count 0 2006.183.07:42:02.73#ibcon#about to read 5, iclass 22, count 0 2006.183.07:42:02.73#ibcon#read 5, iclass 22, count 0 2006.183.07:42:02.73#ibcon#about to read 6, iclass 22, count 0 2006.183.07:42:02.73#ibcon#read 6, iclass 22, count 0 2006.183.07:42:02.73#ibcon#end of sib2, iclass 22, count 0 2006.183.07:42:02.73#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:42:02.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:42:02.73#ibcon#[27=BW32\r\n] 2006.183.07:42:02.73#ibcon#*before write, iclass 22, count 0 2006.183.07:42:02.73#ibcon#enter sib2, iclass 22, count 0 2006.183.07:42:02.73#ibcon#flushed, iclass 22, count 0 2006.183.07:42:02.73#ibcon#about to write, iclass 22, count 0 2006.183.07:42:02.73#ibcon#wrote, iclass 22, count 0 2006.183.07:42:02.73#ibcon#about to read 3, iclass 22, count 0 2006.183.07:42:02.76#ibcon#read 3, iclass 22, count 0 2006.183.07:42:02.76#ibcon#about to read 4, iclass 22, count 0 2006.183.07:42:02.76#ibcon#read 4, iclass 22, count 0 2006.183.07:42:02.76#ibcon#about to read 5, iclass 22, count 0 2006.183.07:42:02.76#ibcon#read 5, iclass 22, count 0 2006.183.07:42:02.76#ibcon#about to read 6, iclass 22, count 0 2006.183.07:42:02.76#ibcon#read 6, iclass 22, count 0 2006.183.07:42:02.76#ibcon#end of sib2, iclass 22, count 0 2006.183.07:42:02.76#ibcon#*after write, iclass 22, count 0 2006.183.07:42:02.76#ibcon#*before return 0, iclass 22, count 0 2006.183.07:42:02.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:42:02.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:42:02.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:42:02.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:42:02.76$4f8m12a/ifd4f 2006.183.07:42:02.76$ifd4f/lo= 2006.183.07:42:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:42:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:42:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:42:02.76$ifd4f/patch= 2006.183.07:42:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:42:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:42:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:42:02.76$4f8m12a/"form=m,16.000,1:2 2006.183.07:42:02.76$4f8m12a/"tpicd 2006.183.07:42:02.76$4f8m12a/echo=off 2006.183.07:42:02.76$4f8m12a/xlog=off 2006.183.07:42:02.76:!2006.183.07:42:30 2006.183.07:42:14.13#trakl#Source acquired 2006.183.07:42:15.13#flagr#flagr/antenna,acquired 2006.183.07:42:30.00:preob 2006.183.07:42:31.13/onsource/TRACKING 2006.183.07:42:31.13:!2006.183.07:42:40 2006.183.07:42:40.00:data_valid=on 2006.183.07:42:40.00:midob 2006.183.07:42:40.13/onsource/TRACKING 2006.183.07:42:40.13/wx/27.92,996.2,88 2006.183.07:42:40.32/cable/+6.4511E-03 2006.183.07:42:41.41/va/01,08,usb,yes,28,30 2006.183.07:42:41.41/va/02,07,usb,yes,29,30 2006.183.07:42:41.41/va/03,06,usb,yes,30,30 2006.183.07:42:41.41/va/04,07,usb,yes,29,32 2006.183.07:42:41.41/va/05,07,usb,yes,31,33 2006.183.07:42:41.41/va/06,06,usb,yes,30,30 2006.183.07:42:41.41/va/07,06,usb,yes,31,30 2006.183.07:42:41.41/va/08,07,usb,yes,29,29 2006.183.07:42:41.64/valo/01,532.99,yes,locked 2006.183.07:42:41.64/valo/02,572.99,yes,locked 2006.183.07:42:41.64/valo/03,672.99,yes,locked 2006.183.07:42:41.64/valo/04,832.99,yes,locked 2006.183.07:42:41.64/valo/05,652.99,yes,locked 2006.183.07:42:41.64/valo/06,772.99,yes,locked 2006.183.07:42:41.64/valo/07,832.99,yes,locked 2006.183.07:42:41.64/valo/08,852.99,yes,locked 2006.183.07:42:42.73/vb/01,04,usb,yes,29,27 2006.183.07:42:42.73/vb/02,04,usb,yes,31,32 2006.183.07:42:42.73/vb/03,04,usb,yes,27,31 2006.183.07:42:42.73/vb/04,04,usb,yes,28,28 2006.183.07:42:42.73/vb/05,04,usb,yes,26,30 2006.183.07:42:42.73/vb/06,04,usb,yes,27,30 2006.183.07:42:42.73/vb/07,04,usb,yes,29,29 2006.183.07:42:42.73/vb/08,04,usb,yes,27,30 2006.183.07:42:42.96/vblo/01,632.99,yes,locked 2006.183.07:42:42.96/vblo/02,640.99,yes,locked 2006.183.07:42:42.96/vblo/03,656.99,yes,locked 2006.183.07:42:42.96/vblo/04,712.99,yes,locked 2006.183.07:42:42.96/vblo/05,744.99,yes,locked 2006.183.07:42:42.96/vblo/06,752.99,yes,locked 2006.183.07:42:42.96/vblo/07,734.99,yes,locked 2006.183.07:42:42.96/vblo/08,744.99,yes,locked 2006.183.07:42:43.11/vabw/8 2006.183.07:42:43.26/vbbw/8 2006.183.07:42:43.35/xfe/off,on,14.5 2006.183.07:42:43.73/ifatt/23,28,28,28 2006.183.07:42:44.07/fmout-gps/S +3.30E-07 2006.183.07:42:44.15:!2006.183.07:43:40 2006.183.07:43:40.00:data_valid=off 2006.183.07:43:40.01:postob 2006.183.07:43:40.24/cable/+6.4516E-03 2006.183.07:43:40.25/wx/27.92,996.2,88 2006.183.07:43:41.07/fmout-gps/S +3.30E-07 2006.183.07:43:41.08:scan_name=183-0745,k06183,180 2006.183.07:43:41.08:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.183.07:43:41.14#flagr#flagr/antenna,new-source 2006.183.07:43:42.14:checkk5 2006.183.07:43:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:43:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:43:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:43:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:43:44.01/chk_obsdata//k5ts1/T1830742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:43:44.38/chk_obsdata//k5ts2/T1830742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:43:44.76/chk_obsdata//k5ts3/T1830742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:43:45.13/chk_obsdata//k5ts4/T1830742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:43:45.82/k5log//k5ts1_log_newline 2006.183.07:43:46.51/k5log//k5ts2_log_newline 2006.183.07:43:47.21/k5log//k5ts3_log_newline 2006.183.07:43:47.90/k5log//k5ts4_log_newline 2006.183.07:43:47.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:43:47.93:4f8m12a=1 2006.183.07:43:47.93$4f8m12a/echo=on 2006.183.07:43:47.93$4f8m12a/pcalon 2006.183.07:43:47.93$pcalon/"no phase cal control is implemented here 2006.183.07:43:47.93$4f8m12a/"tpicd=stop 2006.183.07:43:47.93$4f8m12a/vc4f8 2006.183.07:43:47.93$vc4f8/valo=1,532.99 2006.183.07:43:47.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.07:43:47.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.07:43:47.93#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:47.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:43:47.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:43:47.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:43:47.93#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:43:47.93#ibcon#first serial, iclass 24, count 0 2006.183.07:43:47.93#ibcon#enter sib2, iclass 24, count 0 2006.183.07:43:47.93#ibcon#flushed, iclass 24, count 0 2006.183.07:43:47.93#ibcon#about to write, iclass 24, count 0 2006.183.07:43:47.93#ibcon#wrote, iclass 24, count 0 2006.183.07:43:47.93#ibcon#about to read 3, iclass 24, count 0 2006.183.07:43:47.97#ibcon#read 3, iclass 24, count 0 2006.183.07:43:47.97#ibcon#about to read 4, iclass 24, count 0 2006.183.07:43:47.97#ibcon#read 4, iclass 24, count 0 2006.183.07:43:47.97#ibcon#about to read 5, iclass 24, count 0 2006.183.07:43:47.97#ibcon#read 5, iclass 24, count 0 2006.183.07:43:47.97#ibcon#about to read 6, iclass 24, count 0 2006.183.07:43:47.97#ibcon#read 6, iclass 24, count 0 2006.183.07:43:47.97#ibcon#end of sib2, iclass 24, count 0 2006.183.07:43:47.97#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:43:47.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:43:47.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:43:47.97#ibcon#*before write, iclass 24, count 0 2006.183.07:43:47.97#ibcon#enter sib2, iclass 24, count 0 2006.183.07:43:47.97#ibcon#flushed, iclass 24, count 0 2006.183.07:43:47.97#ibcon#about to write, iclass 24, count 0 2006.183.07:43:47.97#ibcon#wrote, iclass 24, count 0 2006.183.07:43:47.97#ibcon#about to read 3, iclass 24, count 0 2006.183.07:43:48.02#ibcon#read 3, iclass 24, count 0 2006.183.07:43:48.02#ibcon#about to read 4, iclass 24, count 0 2006.183.07:43:48.02#ibcon#read 4, iclass 24, count 0 2006.183.07:43:48.02#ibcon#about to read 5, iclass 24, count 0 2006.183.07:43:48.02#ibcon#read 5, iclass 24, count 0 2006.183.07:43:48.02#ibcon#about to read 6, iclass 24, count 0 2006.183.07:43:48.02#ibcon#read 6, iclass 24, count 0 2006.183.07:43:48.02#ibcon#end of sib2, iclass 24, count 0 2006.183.07:43:48.02#ibcon#*after write, iclass 24, count 0 2006.183.07:43:48.02#ibcon#*before return 0, iclass 24, count 0 2006.183.07:43:48.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:43:48.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:43:48.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:43:48.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:43:48.02$vc4f8/va=1,8 2006.183.07:43:48.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.07:43:48.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.07:43:48.02#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:48.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:43:48.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:43:48.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:43:48.02#ibcon#enter wrdev, iclass 26, count 2 2006.183.07:43:48.02#ibcon#first serial, iclass 26, count 2 2006.183.07:43:48.02#ibcon#enter sib2, iclass 26, count 2 2006.183.07:43:48.02#ibcon#flushed, iclass 26, count 2 2006.183.07:43:48.02#ibcon#about to write, iclass 26, count 2 2006.183.07:43:48.02#ibcon#wrote, iclass 26, count 2 2006.183.07:43:48.02#ibcon#about to read 3, iclass 26, count 2 2006.183.07:43:48.04#ibcon#read 3, iclass 26, count 2 2006.183.07:43:48.04#ibcon#about to read 4, iclass 26, count 2 2006.183.07:43:48.04#ibcon#read 4, iclass 26, count 2 2006.183.07:43:48.04#ibcon#about to read 5, iclass 26, count 2 2006.183.07:43:48.04#ibcon#read 5, iclass 26, count 2 2006.183.07:43:48.04#ibcon#about to read 6, iclass 26, count 2 2006.183.07:43:48.04#ibcon#read 6, iclass 26, count 2 2006.183.07:43:48.04#ibcon#end of sib2, iclass 26, count 2 2006.183.07:43:48.04#ibcon#*mode == 0, iclass 26, count 2 2006.183.07:43:48.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.07:43:48.04#ibcon#[25=AT01-08\r\n] 2006.183.07:43:48.04#ibcon#*before write, iclass 26, count 2 2006.183.07:43:48.04#ibcon#enter sib2, iclass 26, count 2 2006.183.07:43:48.04#ibcon#flushed, iclass 26, count 2 2006.183.07:43:48.04#ibcon#about to write, iclass 26, count 2 2006.183.07:43:48.04#ibcon#wrote, iclass 26, count 2 2006.183.07:43:48.04#ibcon#about to read 3, iclass 26, count 2 2006.183.07:43:48.08#ibcon#read 3, iclass 26, count 2 2006.183.07:43:48.08#ibcon#about to read 4, iclass 26, count 2 2006.183.07:43:48.08#ibcon#read 4, iclass 26, count 2 2006.183.07:43:48.08#ibcon#about to read 5, iclass 26, count 2 2006.183.07:43:48.08#ibcon#read 5, iclass 26, count 2 2006.183.07:43:48.08#ibcon#about to read 6, iclass 26, count 2 2006.183.07:43:48.08#ibcon#read 6, iclass 26, count 2 2006.183.07:43:48.08#ibcon#end of sib2, iclass 26, count 2 2006.183.07:43:48.08#ibcon#*after write, iclass 26, count 2 2006.183.07:43:48.08#ibcon#*before return 0, iclass 26, count 2 2006.183.07:43:48.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:43:48.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:43:48.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.07:43:48.08#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:48.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:43:48.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:43:48.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:43:48.19#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:43:48.19#ibcon#first serial, iclass 26, count 0 2006.183.07:43:48.19#ibcon#enter sib2, iclass 26, count 0 2006.183.07:43:48.19#ibcon#flushed, iclass 26, count 0 2006.183.07:43:48.19#ibcon#about to write, iclass 26, count 0 2006.183.07:43:48.19#ibcon#wrote, iclass 26, count 0 2006.183.07:43:48.19#ibcon#about to read 3, iclass 26, count 0 2006.183.07:43:48.21#ibcon#read 3, iclass 26, count 0 2006.183.07:43:48.21#ibcon#about to read 4, iclass 26, count 0 2006.183.07:43:48.21#ibcon#read 4, iclass 26, count 0 2006.183.07:43:48.21#ibcon#about to read 5, iclass 26, count 0 2006.183.07:43:48.21#ibcon#read 5, iclass 26, count 0 2006.183.07:43:48.21#ibcon#about to read 6, iclass 26, count 0 2006.183.07:43:48.21#ibcon#read 6, iclass 26, count 0 2006.183.07:43:48.21#ibcon#end of sib2, iclass 26, count 0 2006.183.07:43:48.21#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:43:48.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:43:48.21#ibcon#[25=USB\r\n] 2006.183.07:43:48.21#ibcon#*before write, iclass 26, count 0 2006.183.07:43:48.21#ibcon#enter sib2, iclass 26, count 0 2006.183.07:43:48.21#ibcon#flushed, iclass 26, count 0 2006.183.07:43:48.21#ibcon#about to write, iclass 26, count 0 2006.183.07:43:48.21#ibcon#wrote, iclass 26, count 0 2006.183.07:43:48.21#ibcon#about to read 3, iclass 26, count 0 2006.183.07:43:48.24#ibcon#read 3, iclass 26, count 0 2006.183.07:43:48.24#ibcon#about to read 4, iclass 26, count 0 2006.183.07:43:48.24#ibcon#read 4, iclass 26, count 0 2006.183.07:43:48.24#ibcon#about to read 5, iclass 26, count 0 2006.183.07:43:48.24#ibcon#read 5, iclass 26, count 0 2006.183.07:43:48.24#ibcon#about to read 6, iclass 26, count 0 2006.183.07:43:48.24#ibcon#read 6, iclass 26, count 0 2006.183.07:43:48.24#ibcon#end of sib2, iclass 26, count 0 2006.183.07:43:48.24#ibcon#*after write, iclass 26, count 0 2006.183.07:43:48.24#ibcon#*before return 0, iclass 26, count 0 2006.183.07:43:48.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:43:48.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:43:48.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:43:48.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:43:48.24$vc4f8/valo=2,572.99 2006.183.07:43:48.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.07:43:48.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.07:43:48.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:48.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:48.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:48.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:48.24#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:43:48.24#ibcon#first serial, iclass 28, count 0 2006.183.07:43:48.24#ibcon#enter sib2, iclass 28, count 0 2006.183.07:43:48.24#ibcon#flushed, iclass 28, count 0 2006.183.07:43:48.24#ibcon#about to write, iclass 28, count 0 2006.183.07:43:48.24#ibcon#wrote, iclass 28, count 0 2006.183.07:43:48.24#ibcon#about to read 3, iclass 28, count 0 2006.183.07:43:48.26#ibcon#read 3, iclass 28, count 0 2006.183.07:43:48.26#ibcon#about to read 4, iclass 28, count 0 2006.183.07:43:48.26#ibcon#read 4, iclass 28, count 0 2006.183.07:43:48.26#ibcon#about to read 5, iclass 28, count 0 2006.183.07:43:48.26#ibcon#read 5, iclass 28, count 0 2006.183.07:43:48.26#ibcon#about to read 6, iclass 28, count 0 2006.183.07:43:48.26#ibcon#read 6, iclass 28, count 0 2006.183.07:43:48.26#ibcon#end of sib2, iclass 28, count 0 2006.183.07:43:48.26#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:43:48.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:43:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:43:48.26#ibcon#*before write, iclass 28, count 0 2006.183.07:43:48.26#ibcon#enter sib2, iclass 28, count 0 2006.183.07:43:48.26#ibcon#flushed, iclass 28, count 0 2006.183.07:43:48.26#ibcon#about to write, iclass 28, count 0 2006.183.07:43:48.26#ibcon#wrote, iclass 28, count 0 2006.183.07:43:48.26#ibcon#about to read 3, iclass 28, count 0 2006.183.07:43:48.30#ibcon#read 3, iclass 28, count 0 2006.183.07:43:48.30#ibcon#about to read 4, iclass 28, count 0 2006.183.07:43:48.30#ibcon#read 4, iclass 28, count 0 2006.183.07:43:48.30#ibcon#about to read 5, iclass 28, count 0 2006.183.07:43:48.30#ibcon#read 5, iclass 28, count 0 2006.183.07:43:48.30#ibcon#about to read 6, iclass 28, count 0 2006.183.07:43:48.30#ibcon#read 6, iclass 28, count 0 2006.183.07:43:48.30#ibcon#end of sib2, iclass 28, count 0 2006.183.07:43:48.30#ibcon#*after write, iclass 28, count 0 2006.183.07:43:48.30#ibcon#*before return 0, iclass 28, count 0 2006.183.07:43:48.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:48.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:48.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:43:48.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:43:48.30$vc4f8/va=2,7 2006.183.07:43:48.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.07:43:48.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.07:43:48.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:48.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:48.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:48.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:48.37#ibcon#enter wrdev, iclass 30, count 2 2006.183.07:43:48.37#ibcon#first serial, iclass 30, count 2 2006.183.07:43:48.37#ibcon#enter sib2, iclass 30, count 2 2006.183.07:43:48.37#ibcon#flushed, iclass 30, count 2 2006.183.07:43:48.37#ibcon#about to write, iclass 30, count 2 2006.183.07:43:48.37#ibcon#wrote, iclass 30, count 2 2006.183.07:43:48.37#ibcon#about to read 3, iclass 30, count 2 2006.183.07:43:48.38#ibcon#read 3, iclass 30, count 2 2006.183.07:43:48.38#ibcon#about to read 4, iclass 30, count 2 2006.183.07:43:48.38#ibcon#read 4, iclass 30, count 2 2006.183.07:43:48.38#ibcon#about to read 5, iclass 30, count 2 2006.183.07:43:48.38#ibcon#read 5, iclass 30, count 2 2006.183.07:43:48.38#ibcon#about to read 6, iclass 30, count 2 2006.183.07:43:48.38#ibcon#read 6, iclass 30, count 2 2006.183.07:43:48.38#ibcon#end of sib2, iclass 30, count 2 2006.183.07:43:48.38#ibcon#*mode == 0, iclass 30, count 2 2006.183.07:43:48.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.07:43:48.38#ibcon#[25=AT02-07\r\n] 2006.183.07:43:48.38#ibcon#*before write, iclass 30, count 2 2006.183.07:43:48.38#ibcon#enter sib2, iclass 30, count 2 2006.183.07:43:48.38#ibcon#flushed, iclass 30, count 2 2006.183.07:43:48.38#ibcon#about to write, iclass 30, count 2 2006.183.07:43:48.38#ibcon#wrote, iclass 30, count 2 2006.183.07:43:48.38#ibcon#about to read 3, iclass 30, count 2 2006.183.07:43:48.41#ibcon#read 3, iclass 30, count 2 2006.183.07:43:48.41#ibcon#about to read 4, iclass 30, count 2 2006.183.07:43:48.41#ibcon#read 4, iclass 30, count 2 2006.183.07:43:48.41#ibcon#about to read 5, iclass 30, count 2 2006.183.07:43:48.41#ibcon#read 5, iclass 30, count 2 2006.183.07:43:48.41#ibcon#about to read 6, iclass 30, count 2 2006.183.07:43:48.41#ibcon#read 6, iclass 30, count 2 2006.183.07:43:48.41#ibcon#end of sib2, iclass 30, count 2 2006.183.07:43:48.41#ibcon#*after write, iclass 30, count 2 2006.183.07:43:48.41#ibcon#*before return 0, iclass 30, count 2 2006.183.07:43:48.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:48.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:48.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.07:43:48.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:48.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:48.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:48.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:48.53#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:43:48.53#ibcon#first serial, iclass 30, count 0 2006.183.07:43:48.53#ibcon#enter sib2, iclass 30, count 0 2006.183.07:43:48.53#ibcon#flushed, iclass 30, count 0 2006.183.07:43:48.53#ibcon#about to write, iclass 30, count 0 2006.183.07:43:48.53#ibcon#wrote, iclass 30, count 0 2006.183.07:43:48.53#ibcon#about to read 3, iclass 30, count 0 2006.183.07:43:48.55#ibcon#read 3, iclass 30, count 0 2006.183.07:43:48.55#ibcon#about to read 4, iclass 30, count 0 2006.183.07:43:48.55#ibcon#read 4, iclass 30, count 0 2006.183.07:43:48.55#ibcon#about to read 5, iclass 30, count 0 2006.183.07:43:48.55#ibcon#read 5, iclass 30, count 0 2006.183.07:43:48.55#ibcon#about to read 6, iclass 30, count 0 2006.183.07:43:48.55#ibcon#read 6, iclass 30, count 0 2006.183.07:43:48.55#ibcon#end of sib2, iclass 30, count 0 2006.183.07:43:48.55#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:43:48.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:43:48.55#ibcon#[25=USB\r\n] 2006.183.07:43:48.55#ibcon#*before write, iclass 30, count 0 2006.183.07:43:48.55#ibcon#enter sib2, iclass 30, count 0 2006.183.07:43:48.55#ibcon#flushed, iclass 30, count 0 2006.183.07:43:48.55#ibcon#about to write, iclass 30, count 0 2006.183.07:43:48.55#ibcon#wrote, iclass 30, count 0 2006.183.07:43:48.55#ibcon#about to read 3, iclass 30, count 0 2006.183.07:43:48.58#ibcon#read 3, iclass 30, count 0 2006.183.07:43:48.58#ibcon#about to read 4, iclass 30, count 0 2006.183.07:43:48.58#ibcon#read 4, iclass 30, count 0 2006.183.07:43:48.58#ibcon#about to read 5, iclass 30, count 0 2006.183.07:43:48.58#ibcon#read 5, iclass 30, count 0 2006.183.07:43:48.58#ibcon#about to read 6, iclass 30, count 0 2006.183.07:43:48.58#ibcon#read 6, iclass 30, count 0 2006.183.07:43:48.58#ibcon#end of sib2, iclass 30, count 0 2006.183.07:43:48.58#ibcon#*after write, iclass 30, count 0 2006.183.07:43:48.58#ibcon#*before return 0, iclass 30, count 0 2006.183.07:43:48.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:48.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:48.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:43:48.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:43:48.58$vc4f8/valo=3,672.99 2006.183.07:43:48.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.07:43:48.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.07:43:48.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:48.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:48.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:48.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:48.58#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:43:48.58#ibcon#first serial, iclass 32, count 0 2006.183.07:43:48.58#ibcon#enter sib2, iclass 32, count 0 2006.183.07:43:48.58#ibcon#flushed, iclass 32, count 0 2006.183.07:43:48.58#ibcon#about to write, iclass 32, count 0 2006.183.07:43:48.58#ibcon#wrote, iclass 32, count 0 2006.183.07:43:48.58#ibcon#about to read 3, iclass 32, count 0 2006.183.07:43:48.61#ibcon#read 3, iclass 32, count 0 2006.183.07:43:48.61#ibcon#about to read 4, iclass 32, count 0 2006.183.07:43:48.61#ibcon#read 4, iclass 32, count 0 2006.183.07:43:48.61#ibcon#about to read 5, iclass 32, count 0 2006.183.07:43:48.61#ibcon#read 5, iclass 32, count 0 2006.183.07:43:48.61#ibcon#about to read 6, iclass 32, count 0 2006.183.07:43:48.61#ibcon#read 6, iclass 32, count 0 2006.183.07:43:48.61#ibcon#end of sib2, iclass 32, count 0 2006.183.07:43:48.61#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:43:48.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:43:48.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:43:48.61#ibcon#*before write, iclass 32, count 0 2006.183.07:43:48.61#ibcon#enter sib2, iclass 32, count 0 2006.183.07:43:48.61#ibcon#flushed, iclass 32, count 0 2006.183.07:43:48.61#ibcon#about to write, iclass 32, count 0 2006.183.07:43:48.61#ibcon#wrote, iclass 32, count 0 2006.183.07:43:48.61#ibcon#about to read 3, iclass 32, count 0 2006.183.07:43:48.65#ibcon#read 3, iclass 32, count 0 2006.183.07:43:48.65#ibcon#about to read 4, iclass 32, count 0 2006.183.07:43:48.65#ibcon#read 4, iclass 32, count 0 2006.183.07:43:48.65#ibcon#about to read 5, iclass 32, count 0 2006.183.07:43:48.65#ibcon#read 5, iclass 32, count 0 2006.183.07:43:48.65#ibcon#about to read 6, iclass 32, count 0 2006.183.07:43:48.65#ibcon#read 6, iclass 32, count 0 2006.183.07:43:48.65#ibcon#end of sib2, iclass 32, count 0 2006.183.07:43:48.65#ibcon#*after write, iclass 32, count 0 2006.183.07:43:48.65#ibcon#*before return 0, iclass 32, count 0 2006.183.07:43:48.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:48.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:48.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:43:48.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:43:48.65$vc4f8/va=3,6 2006.183.07:43:48.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.07:43:48.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.07:43:48.65#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:48.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:48.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:48.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:48.70#ibcon#enter wrdev, iclass 34, count 2 2006.183.07:43:48.70#ibcon#first serial, iclass 34, count 2 2006.183.07:43:48.70#ibcon#enter sib2, iclass 34, count 2 2006.183.07:43:48.70#ibcon#flushed, iclass 34, count 2 2006.183.07:43:48.70#ibcon#about to write, iclass 34, count 2 2006.183.07:43:48.70#ibcon#wrote, iclass 34, count 2 2006.183.07:43:48.70#ibcon#about to read 3, iclass 34, count 2 2006.183.07:43:48.72#ibcon#read 3, iclass 34, count 2 2006.183.07:43:48.72#ibcon#about to read 4, iclass 34, count 2 2006.183.07:43:48.72#ibcon#read 4, iclass 34, count 2 2006.183.07:43:48.72#ibcon#about to read 5, iclass 34, count 2 2006.183.07:43:48.72#ibcon#read 5, iclass 34, count 2 2006.183.07:43:48.72#ibcon#about to read 6, iclass 34, count 2 2006.183.07:43:48.72#ibcon#read 6, iclass 34, count 2 2006.183.07:43:48.72#ibcon#end of sib2, iclass 34, count 2 2006.183.07:43:48.72#ibcon#*mode == 0, iclass 34, count 2 2006.183.07:43:48.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.07:43:48.72#ibcon#[25=AT03-06\r\n] 2006.183.07:43:48.72#ibcon#*before write, iclass 34, count 2 2006.183.07:43:48.72#ibcon#enter sib2, iclass 34, count 2 2006.183.07:43:48.72#ibcon#flushed, iclass 34, count 2 2006.183.07:43:48.72#ibcon#about to write, iclass 34, count 2 2006.183.07:43:48.72#ibcon#wrote, iclass 34, count 2 2006.183.07:43:48.72#ibcon#about to read 3, iclass 34, count 2 2006.183.07:43:48.75#ibcon#read 3, iclass 34, count 2 2006.183.07:43:48.75#ibcon#about to read 4, iclass 34, count 2 2006.183.07:43:48.75#ibcon#read 4, iclass 34, count 2 2006.183.07:43:48.75#ibcon#about to read 5, iclass 34, count 2 2006.183.07:43:48.75#ibcon#read 5, iclass 34, count 2 2006.183.07:43:48.75#ibcon#about to read 6, iclass 34, count 2 2006.183.07:43:48.75#ibcon#read 6, iclass 34, count 2 2006.183.07:43:48.75#ibcon#end of sib2, iclass 34, count 2 2006.183.07:43:48.75#ibcon#*after write, iclass 34, count 2 2006.183.07:43:48.75#ibcon#*before return 0, iclass 34, count 2 2006.183.07:43:48.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:48.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:48.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.07:43:48.75#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:48.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:48.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:48.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:48.87#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:43:48.87#ibcon#first serial, iclass 34, count 0 2006.183.07:43:48.87#ibcon#enter sib2, iclass 34, count 0 2006.183.07:43:48.87#ibcon#flushed, iclass 34, count 0 2006.183.07:43:48.87#ibcon#about to write, iclass 34, count 0 2006.183.07:43:48.87#ibcon#wrote, iclass 34, count 0 2006.183.07:43:48.87#ibcon#about to read 3, iclass 34, count 0 2006.183.07:43:48.89#ibcon#read 3, iclass 34, count 0 2006.183.07:43:48.89#ibcon#about to read 4, iclass 34, count 0 2006.183.07:43:48.89#ibcon#read 4, iclass 34, count 0 2006.183.07:43:48.89#ibcon#about to read 5, iclass 34, count 0 2006.183.07:43:48.89#ibcon#read 5, iclass 34, count 0 2006.183.07:43:48.89#ibcon#about to read 6, iclass 34, count 0 2006.183.07:43:48.89#ibcon#read 6, iclass 34, count 0 2006.183.07:43:48.89#ibcon#end of sib2, iclass 34, count 0 2006.183.07:43:48.89#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:43:48.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:43:48.89#ibcon#[25=USB\r\n] 2006.183.07:43:48.89#ibcon#*before write, iclass 34, count 0 2006.183.07:43:48.89#ibcon#enter sib2, iclass 34, count 0 2006.183.07:43:48.89#ibcon#flushed, iclass 34, count 0 2006.183.07:43:48.89#ibcon#about to write, iclass 34, count 0 2006.183.07:43:48.89#ibcon#wrote, iclass 34, count 0 2006.183.07:43:48.89#ibcon#about to read 3, iclass 34, count 0 2006.183.07:43:48.92#ibcon#read 3, iclass 34, count 0 2006.183.07:43:48.92#ibcon#about to read 4, iclass 34, count 0 2006.183.07:43:48.92#ibcon#read 4, iclass 34, count 0 2006.183.07:43:48.92#ibcon#about to read 5, iclass 34, count 0 2006.183.07:43:48.92#ibcon#read 5, iclass 34, count 0 2006.183.07:43:48.92#ibcon#about to read 6, iclass 34, count 0 2006.183.07:43:48.92#ibcon#read 6, iclass 34, count 0 2006.183.07:43:48.92#ibcon#end of sib2, iclass 34, count 0 2006.183.07:43:48.92#ibcon#*after write, iclass 34, count 0 2006.183.07:43:48.92#ibcon#*before return 0, iclass 34, count 0 2006.183.07:43:48.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:48.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:48.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:43:48.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:43:48.92$vc4f8/valo=4,832.99 2006.183.07:43:48.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:43:48.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:43:48.92#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:48.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:48.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:48.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:48.92#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:43:48.92#ibcon#first serial, iclass 36, count 0 2006.183.07:43:48.92#ibcon#enter sib2, iclass 36, count 0 2006.183.07:43:48.92#ibcon#flushed, iclass 36, count 0 2006.183.07:43:48.92#ibcon#about to write, iclass 36, count 0 2006.183.07:43:48.92#ibcon#wrote, iclass 36, count 0 2006.183.07:43:48.92#ibcon#about to read 3, iclass 36, count 0 2006.183.07:43:48.95#ibcon#read 3, iclass 36, count 0 2006.183.07:43:48.95#ibcon#about to read 4, iclass 36, count 0 2006.183.07:43:48.95#ibcon#read 4, iclass 36, count 0 2006.183.07:43:48.95#ibcon#about to read 5, iclass 36, count 0 2006.183.07:43:48.95#ibcon#read 5, iclass 36, count 0 2006.183.07:43:48.95#ibcon#about to read 6, iclass 36, count 0 2006.183.07:43:48.95#ibcon#read 6, iclass 36, count 0 2006.183.07:43:48.95#ibcon#end of sib2, iclass 36, count 0 2006.183.07:43:48.95#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:43:48.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:43:48.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:43:48.95#ibcon#*before write, iclass 36, count 0 2006.183.07:43:48.95#ibcon#enter sib2, iclass 36, count 0 2006.183.07:43:48.95#ibcon#flushed, iclass 36, count 0 2006.183.07:43:48.95#ibcon#about to write, iclass 36, count 0 2006.183.07:43:48.95#ibcon#wrote, iclass 36, count 0 2006.183.07:43:48.95#ibcon#about to read 3, iclass 36, count 0 2006.183.07:43:48.99#ibcon#read 3, iclass 36, count 0 2006.183.07:43:48.99#ibcon#about to read 4, iclass 36, count 0 2006.183.07:43:48.99#ibcon#read 4, iclass 36, count 0 2006.183.07:43:48.99#ibcon#about to read 5, iclass 36, count 0 2006.183.07:43:48.99#ibcon#read 5, iclass 36, count 0 2006.183.07:43:48.99#ibcon#about to read 6, iclass 36, count 0 2006.183.07:43:48.99#ibcon#read 6, iclass 36, count 0 2006.183.07:43:48.99#ibcon#end of sib2, iclass 36, count 0 2006.183.07:43:48.99#ibcon#*after write, iclass 36, count 0 2006.183.07:43:48.99#ibcon#*before return 0, iclass 36, count 0 2006.183.07:43:48.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:48.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:48.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:43:48.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:43:48.99$vc4f8/va=4,7 2006.183.07:43:48.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.07:43:48.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.07:43:48.99#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:48.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:49.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:49.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:49.04#ibcon#enter wrdev, iclass 38, count 2 2006.183.07:43:49.04#ibcon#first serial, iclass 38, count 2 2006.183.07:43:49.04#ibcon#enter sib2, iclass 38, count 2 2006.183.07:43:49.04#ibcon#flushed, iclass 38, count 2 2006.183.07:43:49.04#ibcon#about to write, iclass 38, count 2 2006.183.07:43:49.04#ibcon#wrote, iclass 38, count 2 2006.183.07:43:49.04#ibcon#about to read 3, iclass 38, count 2 2006.183.07:43:49.06#ibcon#read 3, iclass 38, count 2 2006.183.07:43:49.06#ibcon#about to read 4, iclass 38, count 2 2006.183.07:43:49.06#ibcon#read 4, iclass 38, count 2 2006.183.07:43:49.06#ibcon#about to read 5, iclass 38, count 2 2006.183.07:43:49.06#ibcon#read 5, iclass 38, count 2 2006.183.07:43:49.06#ibcon#about to read 6, iclass 38, count 2 2006.183.07:43:49.06#ibcon#read 6, iclass 38, count 2 2006.183.07:43:49.06#ibcon#end of sib2, iclass 38, count 2 2006.183.07:43:49.06#ibcon#*mode == 0, iclass 38, count 2 2006.183.07:43:49.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.07:43:49.06#ibcon#[25=AT04-07\r\n] 2006.183.07:43:49.06#ibcon#*before write, iclass 38, count 2 2006.183.07:43:49.06#ibcon#enter sib2, iclass 38, count 2 2006.183.07:43:49.06#ibcon#flushed, iclass 38, count 2 2006.183.07:43:49.06#ibcon#about to write, iclass 38, count 2 2006.183.07:43:49.06#ibcon#wrote, iclass 38, count 2 2006.183.07:43:49.06#ibcon#about to read 3, iclass 38, count 2 2006.183.07:43:49.09#ibcon#read 3, iclass 38, count 2 2006.183.07:43:49.09#ibcon#about to read 4, iclass 38, count 2 2006.183.07:43:49.09#ibcon#read 4, iclass 38, count 2 2006.183.07:43:49.09#ibcon#about to read 5, iclass 38, count 2 2006.183.07:43:49.09#ibcon#read 5, iclass 38, count 2 2006.183.07:43:49.09#ibcon#about to read 6, iclass 38, count 2 2006.183.07:43:49.09#ibcon#read 6, iclass 38, count 2 2006.183.07:43:49.09#ibcon#end of sib2, iclass 38, count 2 2006.183.07:43:49.09#ibcon#*after write, iclass 38, count 2 2006.183.07:43:49.09#ibcon#*before return 0, iclass 38, count 2 2006.183.07:43:49.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:49.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:49.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.07:43:49.09#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:49.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:49.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:49.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:49.21#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:43:49.21#ibcon#first serial, iclass 38, count 0 2006.183.07:43:49.21#ibcon#enter sib2, iclass 38, count 0 2006.183.07:43:49.21#ibcon#flushed, iclass 38, count 0 2006.183.07:43:49.21#ibcon#about to write, iclass 38, count 0 2006.183.07:43:49.21#ibcon#wrote, iclass 38, count 0 2006.183.07:43:49.21#ibcon#about to read 3, iclass 38, count 0 2006.183.07:43:49.23#ibcon#read 3, iclass 38, count 0 2006.183.07:43:49.23#ibcon#about to read 4, iclass 38, count 0 2006.183.07:43:49.23#ibcon#read 4, iclass 38, count 0 2006.183.07:43:49.23#ibcon#about to read 5, iclass 38, count 0 2006.183.07:43:49.23#ibcon#read 5, iclass 38, count 0 2006.183.07:43:49.23#ibcon#about to read 6, iclass 38, count 0 2006.183.07:43:49.23#ibcon#read 6, iclass 38, count 0 2006.183.07:43:49.23#ibcon#end of sib2, iclass 38, count 0 2006.183.07:43:49.23#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:43:49.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:43:49.23#ibcon#[25=USB\r\n] 2006.183.07:43:49.23#ibcon#*before write, iclass 38, count 0 2006.183.07:43:49.23#ibcon#enter sib2, iclass 38, count 0 2006.183.07:43:49.23#ibcon#flushed, iclass 38, count 0 2006.183.07:43:49.23#ibcon#about to write, iclass 38, count 0 2006.183.07:43:49.23#ibcon#wrote, iclass 38, count 0 2006.183.07:43:49.23#ibcon#about to read 3, iclass 38, count 0 2006.183.07:43:49.26#ibcon#read 3, iclass 38, count 0 2006.183.07:43:49.26#ibcon#about to read 4, iclass 38, count 0 2006.183.07:43:49.26#ibcon#read 4, iclass 38, count 0 2006.183.07:43:49.26#ibcon#about to read 5, iclass 38, count 0 2006.183.07:43:49.26#ibcon#read 5, iclass 38, count 0 2006.183.07:43:49.26#ibcon#about to read 6, iclass 38, count 0 2006.183.07:43:49.26#ibcon#read 6, iclass 38, count 0 2006.183.07:43:49.26#ibcon#end of sib2, iclass 38, count 0 2006.183.07:43:49.26#ibcon#*after write, iclass 38, count 0 2006.183.07:43:49.26#ibcon#*before return 0, iclass 38, count 0 2006.183.07:43:49.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:49.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:49.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:43:49.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:43:49.26$vc4f8/valo=5,652.99 2006.183.07:43:49.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:43:49.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:43:49.26#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:49.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:49.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:49.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:49.26#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:43:49.26#ibcon#first serial, iclass 40, count 0 2006.183.07:43:49.26#ibcon#enter sib2, iclass 40, count 0 2006.183.07:43:49.26#ibcon#flushed, iclass 40, count 0 2006.183.07:43:49.26#ibcon#about to write, iclass 40, count 0 2006.183.07:43:49.26#ibcon#wrote, iclass 40, count 0 2006.183.07:43:49.26#ibcon#about to read 3, iclass 40, count 0 2006.183.07:43:49.28#ibcon#read 3, iclass 40, count 0 2006.183.07:43:49.28#ibcon#about to read 4, iclass 40, count 0 2006.183.07:43:49.28#ibcon#read 4, iclass 40, count 0 2006.183.07:43:49.28#ibcon#about to read 5, iclass 40, count 0 2006.183.07:43:49.28#ibcon#read 5, iclass 40, count 0 2006.183.07:43:49.28#ibcon#about to read 6, iclass 40, count 0 2006.183.07:43:49.28#ibcon#read 6, iclass 40, count 0 2006.183.07:43:49.28#ibcon#end of sib2, iclass 40, count 0 2006.183.07:43:49.28#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:43:49.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:43:49.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:43:49.28#ibcon#*before write, iclass 40, count 0 2006.183.07:43:49.28#ibcon#enter sib2, iclass 40, count 0 2006.183.07:43:49.28#ibcon#flushed, iclass 40, count 0 2006.183.07:43:49.28#ibcon#about to write, iclass 40, count 0 2006.183.07:43:49.28#ibcon#wrote, iclass 40, count 0 2006.183.07:43:49.28#ibcon#about to read 3, iclass 40, count 0 2006.183.07:43:49.32#ibcon#read 3, iclass 40, count 0 2006.183.07:43:49.32#ibcon#about to read 4, iclass 40, count 0 2006.183.07:43:49.32#ibcon#read 4, iclass 40, count 0 2006.183.07:43:49.32#ibcon#about to read 5, iclass 40, count 0 2006.183.07:43:49.32#ibcon#read 5, iclass 40, count 0 2006.183.07:43:49.32#ibcon#about to read 6, iclass 40, count 0 2006.183.07:43:49.32#ibcon#read 6, iclass 40, count 0 2006.183.07:43:49.32#ibcon#end of sib2, iclass 40, count 0 2006.183.07:43:49.32#ibcon#*after write, iclass 40, count 0 2006.183.07:43:49.32#ibcon#*before return 0, iclass 40, count 0 2006.183.07:43:49.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:49.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:49.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:43:49.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:43:49.32$vc4f8/va=5,7 2006.183.07:43:49.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.07:43:49.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.07:43:49.32#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:49.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:49.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:49.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:49.38#ibcon#enter wrdev, iclass 4, count 2 2006.183.07:43:49.38#ibcon#first serial, iclass 4, count 2 2006.183.07:43:49.38#ibcon#enter sib2, iclass 4, count 2 2006.183.07:43:49.38#ibcon#flushed, iclass 4, count 2 2006.183.07:43:49.38#ibcon#about to write, iclass 4, count 2 2006.183.07:43:49.38#ibcon#wrote, iclass 4, count 2 2006.183.07:43:49.38#ibcon#about to read 3, iclass 4, count 2 2006.183.07:43:49.40#ibcon#read 3, iclass 4, count 2 2006.183.07:43:49.40#ibcon#about to read 4, iclass 4, count 2 2006.183.07:43:49.40#ibcon#read 4, iclass 4, count 2 2006.183.07:43:49.40#ibcon#about to read 5, iclass 4, count 2 2006.183.07:43:49.40#ibcon#read 5, iclass 4, count 2 2006.183.07:43:49.40#ibcon#about to read 6, iclass 4, count 2 2006.183.07:43:49.40#ibcon#read 6, iclass 4, count 2 2006.183.07:43:49.40#ibcon#end of sib2, iclass 4, count 2 2006.183.07:43:49.40#ibcon#*mode == 0, iclass 4, count 2 2006.183.07:43:49.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.07:43:49.40#ibcon#[25=AT05-07\r\n] 2006.183.07:43:49.40#ibcon#*before write, iclass 4, count 2 2006.183.07:43:49.40#ibcon#enter sib2, iclass 4, count 2 2006.183.07:43:49.40#ibcon#flushed, iclass 4, count 2 2006.183.07:43:49.40#ibcon#about to write, iclass 4, count 2 2006.183.07:43:49.40#ibcon#wrote, iclass 4, count 2 2006.183.07:43:49.40#ibcon#about to read 3, iclass 4, count 2 2006.183.07:43:49.43#ibcon#read 3, iclass 4, count 2 2006.183.07:43:49.43#ibcon#about to read 4, iclass 4, count 2 2006.183.07:43:49.43#ibcon#read 4, iclass 4, count 2 2006.183.07:43:49.43#ibcon#about to read 5, iclass 4, count 2 2006.183.07:43:49.43#ibcon#read 5, iclass 4, count 2 2006.183.07:43:49.43#ibcon#about to read 6, iclass 4, count 2 2006.183.07:43:49.43#ibcon#read 6, iclass 4, count 2 2006.183.07:43:49.43#ibcon#end of sib2, iclass 4, count 2 2006.183.07:43:49.43#ibcon#*after write, iclass 4, count 2 2006.183.07:43:49.43#ibcon#*before return 0, iclass 4, count 2 2006.183.07:43:49.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:49.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:49.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.07:43:49.43#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:49.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:49.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:49.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:49.55#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:43:49.55#ibcon#first serial, iclass 4, count 0 2006.183.07:43:49.55#ibcon#enter sib2, iclass 4, count 0 2006.183.07:43:49.55#ibcon#flushed, iclass 4, count 0 2006.183.07:43:49.55#ibcon#about to write, iclass 4, count 0 2006.183.07:43:49.55#ibcon#wrote, iclass 4, count 0 2006.183.07:43:49.55#ibcon#about to read 3, iclass 4, count 0 2006.183.07:43:49.57#ibcon#read 3, iclass 4, count 0 2006.183.07:43:49.57#ibcon#about to read 4, iclass 4, count 0 2006.183.07:43:49.57#ibcon#read 4, iclass 4, count 0 2006.183.07:43:49.57#ibcon#about to read 5, iclass 4, count 0 2006.183.07:43:49.57#ibcon#read 5, iclass 4, count 0 2006.183.07:43:49.57#ibcon#about to read 6, iclass 4, count 0 2006.183.07:43:49.57#ibcon#read 6, iclass 4, count 0 2006.183.07:43:49.57#ibcon#end of sib2, iclass 4, count 0 2006.183.07:43:49.57#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:43:49.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:43:49.57#ibcon#[25=USB\r\n] 2006.183.07:43:49.57#ibcon#*before write, iclass 4, count 0 2006.183.07:43:49.57#ibcon#enter sib2, iclass 4, count 0 2006.183.07:43:49.57#ibcon#flushed, iclass 4, count 0 2006.183.07:43:49.57#ibcon#about to write, iclass 4, count 0 2006.183.07:43:49.57#ibcon#wrote, iclass 4, count 0 2006.183.07:43:49.57#ibcon#about to read 3, iclass 4, count 0 2006.183.07:43:49.60#ibcon#read 3, iclass 4, count 0 2006.183.07:43:49.60#ibcon#about to read 4, iclass 4, count 0 2006.183.07:43:49.60#ibcon#read 4, iclass 4, count 0 2006.183.07:43:49.60#ibcon#about to read 5, iclass 4, count 0 2006.183.07:43:49.60#ibcon#read 5, iclass 4, count 0 2006.183.07:43:49.60#ibcon#about to read 6, iclass 4, count 0 2006.183.07:43:49.60#ibcon#read 6, iclass 4, count 0 2006.183.07:43:49.60#ibcon#end of sib2, iclass 4, count 0 2006.183.07:43:49.60#ibcon#*after write, iclass 4, count 0 2006.183.07:43:49.60#ibcon#*before return 0, iclass 4, count 0 2006.183.07:43:49.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:49.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:49.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:43:49.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:43:49.60$vc4f8/valo=6,772.99 2006.183.07:43:49.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:43:49.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:43:49.60#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:49.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:49.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:49.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:49.60#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:43:49.60#ibcon#first serial, iclass 6, count 0 2006.183.07:43:49.60#ibcon#enter sib2, iclass 6, count 0 2006.183.07:43:49.60#ibcon#flushed, iclass 6, count 0 2006.183.07:43:49.60#ibcon#about to write, iclass 6, count 0 2006.183.07:43:49.60#ibcon#wrote, iclass 6, count 0 2006.183.07:43:49.60#ibcon#about to read 3, iclass 6, count 0 2006.183.07:43:49.63#ibcon#read 3, iclass 6, count 0 2006.183.07:43:49.63#ibcon#about to read 4, iclass 6, count 0 2006.183.07:43:49.63#ibcon#read 4, iclass 6, count 0 2006.183.07:43:49.63#ibcon#about to read 5, iclass 6, count 0 2006.183.07:43:49.63#ibcon#read 5, iclass 6, count 0 2006.183.07:43:49.63#ibcon#about to read 6, iclass 6, count 0 2006.183.07:43:49.63#ibcon#read 6, iclass 6, count 0 2006.183.07:43:49.63#ibcon#end of sib2, iclass 6, count 0 2006.183.07:43:49.63#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:43:49.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:43:49.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:43:49.63#ibcon#*before write, iclass 6, count 0 2006.183.07:43:49.63#ibcon#enter sib2, iclass 6, count 0 2006.183.07:43:49.63#ibcon#flushed, iclass 6, count 0 2006.183.07:43:49.63#ibcon#about to write, iclass 6, count 0 2006.183.07:43:49.63#ibcon#wrote, iclass 6, count 0 2006.183.07:43:49.63#ibcon#about to read 3, iclass 6, count 0 2006.183.07:43:49.67#ibcon#read 3, iclass 6, count 0 2006.183.07:43:49.67#ibcon#about to read 4, iclass 6, count 0 2006.183.07:43:49.67#ibcon#read 4, iclass 6, count 0 2006.183.07:43:49.67#ibcon#about to read 5, iclass 6, count 0 2006.183.07:43:49.67#ibcon#read 5, iclass 6, count 0 2006.183.07:43:49.67#ibcon#about to read 6, iclass 6, count 0 2006.183.07:43:49.67#ibcon#read 6, iclass 6, count 0 2006.183.07:43:49.67#ibcon#end of sib2, iclass 6, count 0 2006.183.07:43:49.67#ibcon#*after write, iclass 6, count 0 2006.183.07:43:49.67#ibcon#*before return 0, iclass 6, count 0 2006.183.07:43:49.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:49.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:49.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:43:49.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:43:49.67$vc4f8/va=6,6 2006.183.07:43:49.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.07:43:49.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.07:43:49.67#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:49.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:49.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:49.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:49.72#ibcon#enter wrdev, iclass 10, count 2 2006.183.07:43:49.72#ibcon#first serial, iclass 10, count 2 2006.183.07:43:49.72#ibcon#enter sib2, iclass 10, count 2 2006.183.07:43:49.72#ibcon#flushed, iclass 10, count 2 2006.183.07:43:49.72#ibcon#about to write, iclass 10, count 2 2006.183.07:43:49.72#ibcon#wrote, iclass 10, count 2 2006.183.07:43:49.72#ibcon#about to read 3, iclass 10, count 2 2006.183.07:43:49.74#ibcon#read 3, iclass 10, count 2 2006.183.07:43:49.74#ibcon#about to read 4, iclass 10, count 2 2006.183.07:43:49.74#ibcon#read 4, iclass 10, count 2 2006.183.07:43:49.74#ibcon#about to read 5, iclass 10, count 2 2006.183.07:43:49.74#ibcon#read 5, iclass 10, count 2 2006.183.07:43:49.74#ibcon#about to read 6, iclass 10, count 2 2006.183.07:43:49.74#ibcon#read 6, iclass 10, count 2 2006.183.07:43:49.74#ibcon#end of sib2, iclass 10, count 2 2006.183.07:43:49.74#ibcon#*mode == 0, iclass 10, count 2 2006.183.07:43:49.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.07:43:49.74#ibcon#[25=AT06-06\r\n] 2006.183.07:43:49.74#ibcon#*before write, iclass 10, count 2 2006.183.07:43:49.74#ibcon#enter sib2, iclass 10, count 2 2006.183.07:43:49.74#ibcon#flushed, iclass 10, count 2 2006.183.07:43:49.74#ibcon#about to write, iclass 10, count 2 2006.183.07:43:49.74#ibcon#wrote, iclass 10, count 2 2006.183.07:43:49.74#ibcon#about to read 3, iclass 10, count 2 2006.183.07:43:49.77#ibcon#read 3, iclass 10, count 2 2006.183.07:43:49.77#ibcon#about to read 4, iclass 10, count 2 2006.183.07:43:49.77#ibcon#read 4, iclass 10, count 2 2006.183.07:43:49.77#ibcon#about to read 5, iclass 10, count 2 2006.183.07:43:49.77#ibcon#read 5, iclass 10, count 2 2006.183.07:43:49.77#ibcon#about to read 6, iclass 10, count 2 2006.183.07:43:49.77#ibcon#read 6, iclass 10, count 2 2006.183.07:43:49.77#ibcon#end of sib2, iclass 10, count 2 2006.183.07:43:49.77#ibcon#*after write, iclass 10, count 2 2006.183.07:43:49.77#ibcon#*before return 0, iclass 10, count 2 2006.183.07:43:49.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:49.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:49.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.07:43:49.77#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:49.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:49.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:49.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:49.89#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:43:49.89#ibcon#first serial, iclass 10, count 0 2006.183.07:43:49.89#ibcon#enter sib2, iclass 10, count 0 2006.183.07:43:49.89#ibcon#flushed, iclass 10, count 0 2006.183.07:43:49.89#ibcon#about to write, iclass 10, count 0 2006.183.07:43:49.89#ibcon#wrote, iclass 10, count 0 2006.183.07:43:49.89#ibcon#about to read 3, iclass 10, count 0 2006.183.07:43:49.91#ibcon#read 3, iclass 10, count 0 2006.183.07:43:49.91#ibcon#about to read 4, iclass 10, count 0 2006.183.07:43:49.91#ibcon#read 4, iclass 10, count 0 2006.183.07:43:49.91#ibcon#about to read 5, iclass 10, count 0 2006.183.07:43:49.91#ibcon#read 5, iclass 10, count 0 2006.183.07:43:49.91#ibcon#about to read 6, iclass 10, count 0 2006.183.07:43:49.91#ibcon#read 6, iclass 10, count 0 2006.183.07:43:49.91#ibcon#end of sib2, iclass 10, count 0 2006.183.07:43:49.91#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:43:49.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:43:49.91#ibcon#[25=USB\r\n] 2006.183.07:43:49.91#ibcon#*before write, iclass 10, count 0 2006.183.07:43:49.91#ibcon#enter sib2, iclass 10, count 0 2006.183.07:43:49.91#ibcon#flushed, iclass 10, count 0 2006.183.07:43:49.91#ibcon#about to write, iclass 10, count 0 2006.183.07:43:49.91#ibcon#wrote, iclass 10, count 0 2006.183.07:43:49.91#ibcon#about to read 3, iclass 10, count 0 2006.183.07:43:49.94#ibcon#read 3, iclass 10, count 0 2006.183.07:43:49.94#ibcon#about to read 4, iclass 10, count 0 2006.183.07:43:49.94#ibcon#read 4, iclass 10, count 0 2006.183.07:43:49.94#ibcon#about to read 5, iclass 10, count 0 2006.183.07:43:49.94#ibcon#read 5, iclass 10, count 0 2006.183.07:43:49.94#ibcon#about to read 6, iclass 10, count 0 2006.183.07:43:49.94#ibcon#read 6, iclass 10, count 0 2006.183.07:43:49.94#ibcon#end of sib2, iclass 10, count 0 2006.183.07:43:49.94#ibcon#*after write, iclass 10, count 0 2006.183.07:43:49.94#ibcon#*before return 0, iclass 10, count 0 2006.183.07:43:49.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:49.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:49.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:43:49.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:43:49.94$vc4f8/valo=7,832.99 2006.183.07:43:49.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.07:43:49.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.07:43:49.94#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:49.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:49.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:49.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:49.94#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:43:49.94#ibcon#first serial, iclass 12, count 0 2006.183.07:43:49.94#ibcon#enter sib2, iclass 12, count 0 2006.183.07:43:49.94#ibcon#flushed, iclass 12, count 0 2006.183.07:43:49.94#ibcon#about to write, iclass 12, count 0 2006.183.07:43:49.94#ibcon#wrote, iclass 12, count 0 2006.183.07:43:49.94#ibcon#about to read 3, iclass 12, count 0 2006.183.07:43:49.96#ibcon#read 3, iclass 12, count 0 2006.183.07:43:49.96#ibcon#about to read 4, iclass 12, count 0 2006.183.07:43:49.96#ibcon#read 4, iclass 12, count 0 2006.183.07:43:49.96#ibcon#about to read 5, iclass 12, count 0 2006.183.07:43:49.96#ibcon#read 5, iclass 12, count 0 2006.183.07:43:49.96#ibcon#about to read 6, iclass 12, count 0 2006.183.07:43:49.96#ibcon#read 6, iclass 12, count 0 2006.183.07:43:49.96#ibcon#end of sib2, iclass 12, count 0 2006.183.07:43:49.96#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:43:49.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:43:49.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:43:49.96#ibcon#*before write, iclass 12, count 0 2006.183.07:43:49.96#ibcon#enter sib2, iclass 12, count 0 2006.183.07:43:49.96#ibcon#flushed, iclass 12, count 0 2006.183.07:43:49.96#ibcon#about to write, iclass 12, count 0 2006.183.07:43:49.96#ibcon#wrote, iclass 12, count 0 2006.183.07:43:49.96#ibcon#about to read 3, iclass 12, count 0 2006.183.07:43:50.00#ibcon#read 3, iclass 12, count 0 2006.183.07:43:50.00#ibcon#about to read 4, iclass 12, count 0 2006.183.07:43:50.00#ibcon#read 4, iclass 12, count 0 2006.183.07:43:50.00#ibcon#about to read 5, iclass 12, count 0 2006.183.07:43:50.00#ibcon#read 5, iclass 12, count 0 2006.183.07:43:50.00#ibcon#about to read 6, iclass 12, count 0 2006.183.07:43:50.00#ibcon#read 6, iclass 12, count 0 2006.183.07:43:50.00#ibcon#end of sib2, iclass 12, count 0 2006.183.07:43:50.00#ibcon#*after write, iclass 12, count 0 2006.183.07:43:50.00#ibcon#*before return 0, iclass 12, count 0 2006.183.07:43:50.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:50.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:50.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:43:50.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:43:50.00$vc4f8/va=7,6 2006.183.07:43:50.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.07:43:50.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.07:43:50.00#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:50.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:43:50.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:43:50.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:43:50.06#ibcon#enter wrdev, iclass 14, count 2 2006.183.07:43:50.06#ibcon#first serial, iclass 14, count 2 2006.183.07:43:50.06#ibcon#enter sib2, iclass 14, count 2 2006.183.07:43:50.06#ibcon#flushed, iclass 14, count 2 2006.183.07:43:50.06#ibcon#about to write, iclass 14, count 2 2006.183.07:43:50.06#ibcon#wrote, iclass 14, count 2 2006.183.07:43:50.06#ibcon#about to read 3, iclass 14, count 2 2006.183.07:43:50.08#ibcon#read 3, iclass 14, count 2 2006.183.07:43:50.08#ibcon#about to read 4, iclass 14, count 2 2006.183.07:43:50.08#ibcon#read 4, iclass 14, count 2 2006.183.07:43:50.08#ibcon#about to read 5, iclass 14, count 2 2006.183.07:43:50.08#ibcon#read 5, iclass 14, count 2 2006.183.07:43:50.08#ibcon#about to read 6, iclass 14, count 2 2006.183.07:43:50.08#ibcon#read 6, iclass 14, count 2 2006.183.07:43:50.08#ibcon#end of sib2, iclass 14, count 2 2006.183.07:43:50.08#ibcon#*mode == 0, iclass 14, count 2 2006.183.07:43:50.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.07:43:50.08#ibcon#[25=AT07-06\r\n] 2006.183.07:43:50.08#ibcon#*before write, iclass 14, count 2 2006.183.07:43:50.08#ibcon#enter sib2, iclass 14, count 2 2006.183.07:43:50.08#ibcon#flushed, iclass 14, count 2 2006.183.07:43:50.08#ibcon#about to write, iclass 14, count 2 2006.183.07:43:50.08#ibcon#wrote, iclass 14, count 2 2006.183.07:43:50.08#ibcon#about to read 3, iclass 14, count 2 2006.183.07:43:50.11#ibcon#read 3, iclass 14, count 2 2006.183.07:43:50.11#ibcon#about to read 4, iclass 14, count 2 2006.183.07:43:50.11#ibcon#read 4, iclass 14, count 2 2006.183.07:43:50.11#ibcon#about to read 5, iclass 14, count 2 2006.183.07:43:50.11#ibcon#read 5, iclass 14, count 2 2006.183.07:43:50.11#ibcon#about to read 6, iclass 14, count 2 2006.183.07:43:50.11#ibcon#read 6, iclass 14, count 2 2006.183.07:43:50.11#ibcon#end of sib2, iclass 14, count 2 2006.183.07:43:50.11#ibcon#*after write, iclass 14, count 2 2006.183.07:43:50.11#ibcon#*before return 0, iclass 14, count 2 2006.183.07:43:50.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:43:50.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:43:50.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.07:43:50.11#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:50.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:43:50.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:43:50.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:43:50.23#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:43:50.23#ibcon#first serial, iclass 14, count 0 2006.183.07:43:50.23#ibcon#enter sib2, iclass 14, count 0 2006.183.07:43:50.23#ibcon#flushed, iclass 14, count 0 2006.183.07:43:50.23#ibcon#about to write, iclass 14, count 0 2006.183.07:43:50.23#ibcon#wrote, iclass 14, count 0 2006.183.07:43:50.23#ibcon#about to read 3, iclass 14, count 0 2006.183.07:43:50.25#ibcon#read 3, iclass 14, count 0 2006.183.07:43:50.25#ibcon#about to read 4, iclass 14, count 0 2006.183.07:43:50.25#ibcon#read 4, iclass 14, count 0 2006.183.07:43:50.25#ibcon#about to read 5, iclass 14, count 0 2006.183.07:43:50.25#ibcon#read 5, iclass 14, count 0 2006.183.07:43:50.25#ibcon#about to read 6, iclass 14, count 0 2006.183.07:43:50.25#ibcon#read 6, iclass 14, count 0 2006.183.07:43:50.25#ibcon#end of sib2, iclass 14, count 0 2006.183.07:43:50.25#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:43:50.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:43:50.25#ibcon#[25=USB\r\n] 2006.183.07:43:50.25#ibcon#*before write, iclass 14, count 0 2006.183.07:43:50.25#ibcon#enter sib2, iclass 14, count 0 2006.183.07:43:50.25#ibcon#flushed, iclass 14, count 0 2006.183.07:43:50.25#ibcon#about to write, iclass 14, count 0 2006.183.07:43:50.25#ibcon#wrote, iclass 14, count 0 2006.183.07:43:50.25#ibcon#about to read 3, iclass 14, count 0 2006.183.07:43:50.28#ibcon#read 3, iclass 14, count 0 2006.183.07:43:50.28#ibcon#about to read 4, iclass 14, count 0 2006.183.07:43:50.28#ibcon#read 4, iclass 14, count 0 2006.183.07:43:50.28#ibcon#about to read 5, iclass 14, count 0 2006.183.07:43:50.28#ibcon#read 5, iclass 14, count 0 2006.183.07:43:50.28#ibcon#about to read 6, iclass 14, count 0 2006.183.07:43:50.28#ibcon#read 6, iclass 14, count 0 2006.183.07:43:50.28#ibcon#end of sib2, iclass 14, count 0 2006.183.07:43:50.28#ibcon#*after write, iclass 14, count 0 2006.183.07:43:50.28#ibcon#*before return 0, iclass 14, count 0 2006.183.07:43:50.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:43:50.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:43:50.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:43:50.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:43:50.28$vc4f8/valo=8,852.99 2006.183.07:43:50.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.07:43:50.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.07:43:50.28#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:50.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:43:50.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:43:50.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:43:50.28#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:43:50.28#ibcon#first serial, iclass 16, count 0 2006.183.07:43:50.28#ibcon#enter sib2, iclass 16, count 0 2006.183.07:43:50.28#ibcon#flushed, iclass 16, count 0 2006.183.07:43:50.28#ibcon#about to write, iclass 16, count 0 2006.183.07:43:50.28#ibcon#wrote, iclass 16, count 0 2006.183.07:43:50.28#ibcon#about to read 3, iclass 16, count 0 2006.183.07:43:50.30#ibcon#read 3, iclass 16, count 0 2006.183.07:43:50.30#ibcon#about to read 4, iclass 16, count 0 2006.183.07:43:50.30#ibcon#read 4, iclass 16, count 0 2006.183.07:43:50.30#ibcon#about to read 5, iclass 16, count 0 2006.183.07:43:50.30#ibcon#read 5, iclass 16, count 0 2006.183.07:43:50.30#ibcon#about to read 6, iclass 16, count 0 2006.183.07:43:50.30#ibcon#read 6, iclass 16, count 0 2006.183.07:43:50.30#ibcon#end of sib2, iclass 16, count 0 2006.183.07:43:50.30#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:43:50.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:43:50.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:43:50.30#ibcon#*before write, iclass 16, count 0 2006.183.07:43:50.30#ibcon#enter sib2, iclass 16, count 0 2006.183.07:43:50.30#ibcon#flushed, iclass 16, count 0 2006.183.07:43:50.30#ibcon#about to write, iclass 16, count 0 2006.183.07:43:50.30#ibcon#wrote, iclass 16, count 0 2006.183.07:43:50.30#ibcon#about to read 3, iclass 16, count 0 2006.183.07:43:50.34#ibcon#read 3, iclass 16, count 0 2006.183.07:43:50.34#ibcon#about to read 4, iclass 16, count 0 2006.183.07:43:50.34#ibcon#read 4, iclass 16, count 0 2006.183.07:43:50.34#ibcon#about to read 5, iclass 16, count 0 2006.183.07:43:50.34#ibcon#read 5, iclass 16, count 0 2006.183.07:43:50.34#ibcon#about to read 6, iclass 16, count 0 2006.183.07:43:50.34#ibcon#read 6, iclass 16, count 0 2006.183.07:43:50.34#ibcon#end of sib2, iclass 16, count 0 2006.183.07:43:50.34#ibcon#*after write, iclass 16, count 0 2006.183.07:43:50.34#ibcon#*before return 0, iclass 16, count 0 2006.183.07:43:50.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:43:50.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:43:50.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:43:50.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:43:50.34$vc4f8/va=8,7 2006.183.07:43:50.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.07:43:50.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.07:43:50.34#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:50.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:43:50.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:43:50.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:43:50.40#ibcon#enter wrdev, iclass 18, count 2 2006.183.07:43:50.40#ibcon#first serial, iclass 18, count 2 2006.183.07:43:50.40#ibcon#enter sib2, iclass 18, count 2 2006.183.07:43:50.40#ibcon#flushed, iclass 18, count 2 2006.183.07:43:50.40#ibcon#about to write, iclass 18, count 2 2006.183.07:43:50.40#ibcon#wrote, iclass 18, count 2 2006.183.07:43:50.40#ibcon#about to read 3, iclass 18, count 2 2006.183.07:43:50.42#ibcon#read 3, iclass 18, count 2 2006.183.07:43:50.42#ibcon#about to read 4, iclass 18, count 2 2006.183.07:43:50.42#ibcon#read 4, iclass 18, count 2 2006.183.07:43:50.42#ibcon#about to read 5, iclass 18, count 2 2006.183.07:43:50.42#ibcon#read 5, iclass 18, count 2 2006.183.07:43:50.42#ibcon#about to read 6, iclass 18, count 2 2006.183.07:43:50.42#ibcon#read 6, iclass 18, count 2 2006.183.07:43:50.42#ibcon#end of sib2, iclass 18, count 2 2006.183.07:43:50.42#ibcon#*mode == 0, iclass 18, count 2 2006.183.07:43:50.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.07:43:50.42#ibcon#[25=AT08-07\r\n] 2006.183.07:43:50.42#ibcon#*before write, iclass 18, count 2 2006.183.07:43:50.42#ibcon#enter sib2, iclass 18, count 2 2006.183.07:43:50.42#ibcon#flushed, iclass 18, count 2 2006.183.07:43:50.42#ibcon#about to write, iclass 18, count 2 2006.183.07:43:50.42#ibcon#wrote, iclass 18, count 2 2006.183.07:43:50.42#ibcon#about to read 3, iclass 18, count 2 2006.183.07:43:50.45#ibcon#read 3, iclass 18, count 2 2006.183.07:43:50.45#ibcon#about to read 4, iclass 18, count 2 2006.183.07:43:50.45#ibcon#read 4, iclass 18, count 2 2006.183.07:43:50.45#ibcon#about to read 5, iclass 18, count 2 2006.183.07:43:50.45#ibcon#read 5, iclass 18, count 2 2006.183.07:43:50.45#ibcon#about to read 6, iclass 18, count 2 2006.183.07:43:50.45#ibcon#read 6, iclass 18, count 2 2006.183.07:43:50.45#ibcon#end of sib2, iclass 18, count 2 2006.183.07:43:50.45#ibcon#*after write, iclass 18, count 2 2006.183.07:43:50.45#ibcon#*before return 0, iclass 18, count 2 2006.183.07:43:50.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:43:50.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:43:50.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.07:43:50.45#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:50.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:43:50.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:43:50.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:43:50.57#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:43:50.57#ibcon#first serial, iclass 18, count 0 2006.183.07:43:50.57#ibcon#enter sib2, iclass 18, count 0 2006.183.07:43:50.57#ibcon#flushed, iclass 18, count 0 2006.183.07:43:50.57#ibcon#about to write, iclass 18, count 0 2006.183.07:43:50.57#ibcon#wrote, iclass 18, count 0 2006.183.07:43:50.57#ibcon#about to read 3, iclass 18, count 0 2006.183.07:43:50.59#ibcon#read 3, iclass 18, count 0 2006.183.07:43:50.59#ibcon#about to read 4, iclass 18, count 0 2006.183.07:43:50.59#ibcon#read 4, iclass 18, count 0 2006.183.07:43:50.59#ibcon#about to read 5, iclass 18, count 0 2006.183.07:43:50.59#ibcon#read 5, iclass 18, count 0 2006.183.07:43:50.59#ibcon#about to read 6, iclass 18, count 0 2006.183.07:43:50.59#ibcon#read 6, iclass 18, count 0 2006.183.07:43:50.59#ibcon#end of sib2, iclass 18, count 0 2006.183.07:43:50.59#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:43:50.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:43:50.59#ibcon#[25=USB\r\n] 2006.183.07:43:50.59#ibcon#*before write, iclass 18, count 0 2006.183.07:43:50.59#ibcon#enter sib2, iclass 18, count 0 2006.183.07:43:50.59#ibcon#flushed, iclass 18, count 0 2006.183.07:43:50.59#ibcon#about to write, iclass 18, count 0 2006.183.07:43:50.59#ibcon#wrote, iclass 18, count 0 2006.183.07:43:50.59#ibcon#about to read 3, iclass 18, count 0 2006.183.07:43:50.62#ibcon#read 3, iclass 18, count 0 2006.183.07:43:50.62#ibcon#about to read 4, iclass 18, count 0 2006.183.07:43:50.62#ibcon#read 4, iclass 18, count 0 2006.183.07:43:50.62#ibcon#about to read 5, iclass 18, count 0 2006.183.07:43:50.62#ibcon#read 5, iclass 18, count 0 2006.183.07:43:50.62#ibcon#about to read 6, iclass 18, count 0 2006.183.07:43:50.62#ibcon#read 6, iclass 18, count 0 2006.183.07:43:50.62#ibcon#end of sib2, iclass 18, count 0 2006.183.07:43:50.62#ibcon#*after write, iclass 18, count 0 2006.183.07:43:50.62#ibcon#*before return 0, iclass 18, count 0 2006.183.07:43:50.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:43:50.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:43:50.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:43:50.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:43:50.62$vc4f8/vblo=1,632.99 2006.183.07:43:50.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.07:43:50.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.07:43:50.62#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:50.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:43:50.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:43:50.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:43:50.62#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:43:50.62#ibcon#first serial, iclass 20, count 0 2006.183.07:43:50.62#ibcon#enter sib2, iclass 20, count 0 2006.183.07:43:50.62#ibcon#flushed, iclass 20, count 0 2006.183.07:43:50.62#ibcon#about to write, iclass 20, count 0 2006.183.07:43:50.62#ibcon#wrote, iclass 20, count 0 2006.183.07:43:50.62#ibcon#about to read 3, iclass 20, count 0 2006.183.07:43:50.65#ibcon#read 3, iclass 20, count 0 2006.183.07:43:50.65#ibcon#about to read 4, iclass 20, count 0 2006.183.07:43:50.65#ibcon#read 4, iclass 20, count 0 2006.183.07:43:50.65#ibcon#about to read 5, iclass 20, count 0 2006.183.07:43:50.65#ibcon#read 5, iclass 20, count 0 2006.183.07:43:50.65#ibcon#about to read 6, iclass 20, count 0 2006.183.07:43:50.65#ibcon#read 6, iclass 20, count 0 2006.183.07:43:50.65#ibcon#end of sib2, iclass 20, count 0 2006.183.07:43:50.65#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:43:50.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:43:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:43:50.65#ibcon#*before write, iclass 20, count 0 2006.183.07:43:50.65#ibcon#enter sib2, iclass 20, count 0 2006.183.07:43:50.65#ibcon#flushed, iclass 20, count 0 2006.183.07:43:50.65#ibcon#about to write, iclass 20, count 0 2006.183.07:43:50.65#ibcon#wrote, iclass 20, count 0 2006.183.07:43:50.65#ibcon#about to read 3, iclass 20, count 0 2006.183.07:43:50.69#ibcon#read 3, iclass 20, count 0 2006.183.07:43:50.69#ibcon#about to read 4, iclass 20, count 0 2006.183.07:43:50.69#ibcon#read 4, iclass 20, count 0 2006.183.07:43:50.69#ibcon#about to read 5, iclass 20, count 0 2006.183.07:43:50.69#ibcon#read 5, iclass 20, count 0 2006.183.07:43:50.69#ibcon#about to read 6, iclass 20, count 0 2006.183.07:43:50.69#ibcon#read 6, iclass 20, count 0 2006.183.07:43:50.69#ibcon#end of sib2, iclass 20, count 0 2006.183.07:43:50.69#ibcon#*after write, iclass 20, count 0 2006.183.07:43:50.69#ibcon#*before return 0, iclass 20, count 0 2006.183.07:43:50.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:43:50.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:43:50.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:43:50.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:43:50.69$vc4f8/vb=1,4 2006.183.07:43:50.69#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.07:43:50.69#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.07:43:50.69#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:50.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:43:50.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:43:50.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:43:50.69#ibcon#enter wrdev, iclass 22, count 2 2006.183.07:43:50.69#ibcon#first serial, iclass 22, count 2 2006.183.07:43:50.69#ibcon#enter sib2, iclass 22, count 2 2006.183.07:43:50.69#ibcon#flushed, iclass 22, count 2 2006.183.07:43:50.69#ibcon#about to write, iclass 22, count 2 2006.183.07:43:50.69#ibcon#wrote, iclass 22, count 2 2006.183.07:43:50.69#ibcon#about to read 3, iclass 22, count 2 2006.183.07:43:50.71#ibcon#read 3, iclass 22, count 2 2006.183.07:43:50.71#ibcon#about to read 4, iclass 22, count 2 2006.183.07:43:50.71#ibcon#read 4, iclass 22, count 2 2006.183.07:43:50.71#ibcon#about to read 5, iclass 22, count 2 2006.183.07:43:50.71#ibcon#read 5, iclass 22, count 2 2006.183.07:43:50.71#ibcon#about to read 6, iclass 22, count 2 2006.183.07:43:50.71#ibcon#read 6, iclass 22, count 2 2006.183.07:43:50.71#ibcon#end of sib2, iclass 22, count 2 2006.183.07:43:50.71#ibcon#*mode == 0, iclass 22, count 2 2006.183.07:43:50.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.07:43:50.71#ibcon#[27=AT01-04\r\n] 2006.183.07:43:50.71#ibcon#*before write, iclass 22, count 2 2006.183.07:43:50.71#ibcon#enter sib2, iclass 22, count 2 2006.183.07:43:50.71#ibcon#flushed, iclass 22, count 2 2006.183.07:43:50.71#ibcon#about to write, iclass 22, count 2 2006.183.07:43:50.71#ibcon#wrote, iclass 22, count 2 2006.183.07:43:50.71#ibcon#about to read 3, iclass 22, count 2 2006.183.07:43:50.74#abcon#<5=/09 2.2 6.8 27.92 88 996.2\r\n> 2006.183.07:43:50.74#ibcon#read 3, iclass 22, count 2 2006.183.07:43:50.74#ibcon#about to read 4, iclass 22, count 2 2006.183.07:43:50.74#ibcon#read 4, iclass 22, count 2 2006.183.07:43:50.74#ibcon#about to read 5, iclass 22, count 2 2006.183.07:43:50.74#ibcon#read 5, iclass 22, count 2 2006.183.07:43:50.74#ibcon#about to read 6, iclass 22, count 2 2006.183.07:43:50.74#ibcon#read 6, iclass 22, count 2 2006.183.07:43:50.74#ibcon#end of sib2, iclass 22, count 2 2006.183.07:43:50.74#ibcon#*after write, iclass 22, count 2 2006.183.07:43:50.74#ibcon#*before return 0, iclass 22, count 2 2006.183.07:43:50.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:43:50.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:43:50.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.07:43:50.74#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:50.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:43:50.76#abcon#{5=INTERFACE CLEAR} 2006.183.07:43:50.82#abcon#[5=S1D000X0/0*\r\n] 2006.183.07:43:50.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:43:50.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:43:50.86#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:43:50.86#ibcon#first serial, iclass 22, count 0 2006.183.07:43:50.86#ibcon#enter sib2, iclass 22, count 0 2006.183.07:43:50.86#ibcon#flushed, iclass 22, count 0 2006.183.07:43:50.86#ibcon#about to write, iclass 22, count 0 2006.183.07:43:50.86#ibcon#wrote, iclass 22, count 0 2006.183.07:43:50.86#ibcon#about to read 3, iclass 22, count 0 2006.183.07:43:50.88#ibcon#read 3, iclass 22, count 0 2006.183.07:43:50.88#ibcon#about to read 4, iclass 22, count 0 2006.183.07:43:50.88#ibcon#read 4, iclass 22, count 0 2006.183.07:43:50.88#ibcon#about to read 5, iclass 22, count 0 2006.183.07:43:50.88#ibcon#read 5, iclass 22, count 0 2006.183.07:43:50.88#ibcon#about to read 6, iclass 22, count 0 2006.183.07:43:50.88#ibcon#read 6, iclass 22, count 0 2006.183.07:43:50.88#ibcon#end of sib2, iclass 22, count 0 2006.183.07:43:50.88#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:43:50.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:43:50.88#ibcon#[27=USB\r\n] 2006.183.07:43:50.88#ibcon#*before write, iclass 22, count 0 2006.183.07:43:50.88#ibcon#enter sib2, iclass 22, count 0 2006.183.07:43:50.88#ibcon#flushed, iclass 22, count 0 2006.183.07:43:50.88#ibcon#about to write, iclass 22, count 0 2006.183.07:43:50.88#ibcon#wrote, iclass 22, count 0 2006.183.07:43:50.88#ibcon#about to read 3, iclass 22, count 0 2006.183.07:43:50.91#ibcon#read 3, iclass 22, count 0 2006.183.07:43:50.91#ibcon#about to read 4, iclass 22, count 0 2006.183.07:43:50.91#ibcon#read 4, iclass 22, count 0 2006.183.07:43:50.91#ibcon#about to read 5, iclass 22, count 0 2006.183.07:43:50.91#ibcon#read 5, iclass 22, count 0 2006.183.07:43:50.91#ibcon#about to read 6, iclass 22, count 0 2006.183.07:43:50.91#ibcon#read 6, iclass 22, count 0 2006.183.07:43:50.91#ibcon#end of sib2, iclass 22, count 0 2006.183.07:43:50.91#ibcon#*after write, iclass 22, count 0 2006.183.07:43:50.91#ibcon#*before return 0, iclass 22, count 0 2006.183.07:43:50.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:43:50.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:43:50.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:43:50.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:43:50.91$vc4f8/vblo=2,640.99 2006.183.07:43:50.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.07:43:50.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.07:43:50.91#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:50.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:50.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:50.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:50.91#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:43:50.91#ibcon#first serial, iclass 28, count 0 2006.183.07:43:50.91#ibcon#enter sib2, iclass 28, count 0 2006.183.07:43:50.91#ibcon#flushed, iclass 28, count 0 2006.183.07:43:50.91#ibcon#about to write, iclass 28, count 0 2006.183.07:43:50.91#ibcon#wrote, iclass 28, count 0 2006.183.07:43:50.91#ibcon#about to read 3, iclass 28, count 0 2006.183.07:43:50.93#ibcon#read 3, iclass 28, count 0 2006.183.07:43:50.93#ibcon#about to read 4, iclass 28, count 0 2006.183.07:43:50.93#ibcon#read 4, iclass 28, count 0 2006.183.07:43:50.93#ibcon#about to read 5, iclass 28, count 0 2006.183.07:43:50.93#ibcon#read 5, iclass 28, count 0 2006.183.07:43:50.93#ibcon#about to read 6, iclass 28, count 0 2006.183.07:43:50.93#ibcon#read 6, iclass 28, count 0 2006.183.07:43:50.93#ibcon#end of sib2, iclass 28, count 0 2006.183.07:43:50.93#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:43:50.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:43:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:43:50.93#ibcon#*before write, iclass 28, count 0 2006.183.07:43:50.93#ibcon#enter sib2, iclass 28, count 0 2006.183.07:43:50.93#ibcon#flushed, iclass 28, count 0 2006.183.07:43:50.93#ibcon#about to write, iclass 28, count 0 2006.183.07:43:50.93#ibcon#wrote, iclass 28, count 0 2006.183.07:43:50.93#ibcon#about to read 3, iclass 28, count 0 2006.183.07:43:50.97#ibcon#read 3, iclass 28, count 0 2006.183.07:43:50.97#ibcon#about to read 4, iclass 28, count 0 2006.183.07:43:50.97#ibcon#read 4, iclass 28, count 0 2006.183.07:43:50.97#ibcon#about to read 5, iclass 28, count 0 2006.183.07:43:50.97#ibcon#read 5, iclass 28, count 0 2006.183.07:43:50.97#ibcon#about to read 6, iclass 28, count 0 2006.183.07:43:50.97#ibcon#read 6, iclass 28, count 0 2006.183.07:43:50.97#ibcon#end of sib2, iclass 28, count 0 2006.183.07:43:50.97#ibcon#*after write, iclass 28, count 0 2006.183.07:43:50.97#ibcon#*before return 0, iclass 28, count 0 2006.183.07:43:50.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:50.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:43:50.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:43:50.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:43:50.97$vc4f8/vb=2,4 2006.183.07:43:50.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.07:43:50.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.07:43:50.97#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:50.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:51.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:51.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:51.03#ibcon#enter wrdev, iclass 30, count 2 2006.183.07:43:51.03#ibcon#first serial, iclass 30, count 2 2006.183.07:43:51.03#ibcon#enter sib2, iclass 30, count 2 2006.183.07:43:51.03#ibcon#flushed, iclass 30, count 2 2006.183.07:43:51.03#ibcon#about to write, iclass 30, count 2 2006.183.07:43:51.03#ibcon#wrote, iclass 30, count 2 2006.183.07:43:51.03#ibcon#about to read 3, iclass 30, count 2 2006.183.07:43:51.05#ibcon#read 3, iclass 30, count 2 2006.183.07:43:51.05#ibcon#about to read 4, iclass 30, count 2 2006.183.07:43:51.05#ibcon#read 4, iclass 30, count 2 2006.183.07:43:51.05#ibcon#about to read 5, iclass 30, count 2 2006.183.07:43:51.05#ibcon#read 5, iclass 30, count 2 2006.183.07:43:51.05#ibcon#about to read 6, iclass 30, count 2 2006.183.07:43:51.05#ibcon#read 6, iclass 30, count 2 2006.183.07:43:51.05#ibcon#end of sib2, iclass 30, count 2 2006.183.07:43:51.05#ibcon#*mode == 0, iclass 30, count 2 2006.183.07:43:51.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.07:43:51.05#ibcon#[27=AT02-04\r\n] 2006.183.07:43:51.05#ibcon#*before write, iclass 30, count 2 2006.183.07:43:51.05#ibcon#enter sib2, iclass 30, count 2 2006.183.07:43:51.05#ibcon#flushed, iclass 30, count 2 2006.183.07:43:51.05#ibcon#about to write, iclass 30, count 2 2006.183.07:43:51.05#ibcon#wrote, iclass 30, count 2 2006.183.07:43:51.05#ibcon#about to read 3, iclass 30, count 2 2006.183.07:43:51.08#ibcon#read 3, iclass 30, count 2 2006.183.07:43:51.08#ibcon#about to read 4, iclass 30, count 2 2006.183.07:43:51.08#ibcon#read 4, iclass 30, count 2 2006.183.07:43:51.08#ibcon#about to read 5, iclass 30, count 2 2006.183.07:43:51.08#ibcon#read 5, iclass 30, count 2 2006.183.07:43:51.08#ibcon#about to read 6, iclass 30, count 2 2006.183.07:43:51.08#ibcon#read 6, iclass 30, count 2 2006.183.07:43:51.08#ibcon#end of sib2, iclass 30, count 2 2006.183.07:43:51.08#ibcon#*after write, iclass 30, count 2 2006.183.07:43:51.08#ibcon#*before return 0, iclass 30, count 2 2006.183.07:43:51.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:51.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:43:51.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.07:43:51.08#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:51.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:51.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:51.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:51.20#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:43:51.20#ibcon#first serial, iclass 30, count 0 2006.183.07:43:51.20#ibcon#enter sib2, iclass 30, count 0 2006.183.07:43:51.20#ibcon#flushed, iclass 30, count 0 2006.183.07:43:51.20#ibcon#about to write, iclass 30, count 0 2006.183.07:43:51.20#ibcon#wrote, iclass 30, count 0 2006.183.07:43:51.20#ibcon#about to read 3, iclass 30, count 0 2006.183.07:43:51.22#ibcon#read 3, iclass 30, count 0 2006.183.07:43:51.22#ibcon#about to read 4, iclass 30, count 0 2006.183.07:43:51.22#ibcon#read 4, iclass 30, count 0 2006.183.07:43:51.22#ibcon#about to read 5, iclass 30, count 0 2006.183.07:43:51.22#ibcon#read 5, iclass 30, count 0 2006.183.07:43:51.22#ibcon#about to read 6, iclass 30, count 0 2006.183.07:43:51.22#ibcon#read 6, iclass 30, count 0 2006.183.07:43:51.22#ibcon#end of sib2, iclass 30, count 0 2006.183.07:43:51.22#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:43:51.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:43:51.22#ibcon#[27=USB\r\n] 2006.183.07:43:51.22#ibcon#*before write, iclass 30, count 0 2006.183.07:43:51.22#ibcon#enter sib2, iclass 30, count 0 2006.183.07:43:51.22#ibcon#flushed, iclass 30, count 0 2006.183.07:43:51.22#ibcon#about to write, iclass 30, count 0 2006.183.07:43:51.22#ibcon#wrote, iclass 30, count 0 2006.183.07:43:51.22#ibcon#about to read 3, iclass 30, count 0 2006.183.07:43:51.25#ibcon#read 3, iclass 30, count 0 2006.183.07:43:51.25#ibcon#about to read 4, iclass 30, count 0 2006.183.07:43:51.25#ibcon#read 4, iclass 30, count 0 2006.183.07:43:51.25#ibcon#about to read 5, iclass 30, count 0 2006.183.07:43:51.25#ibcon#read 5, iclass 30, count 0 2006.183.07:43:51.25#ibcon#about to read 6, iclass 30, count 0 2006.183.07:43:51.25#ibcon#read 6, iclass 30, count 0 2006.183.07:43:51.25#ibcon#end of sib2, iclass 30, count 0 2006.183.07:43:51.25#ibcon#*after write, iclass 30, count 0 2006.183.07:43:51.25#ibcon#*before return 0, iclass 30, count 0 2006.183.07:43:51.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:51.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:43:51.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:43:51.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:43:51.25$vc4f8/vblo=3,656.99 2006.183.07:43:51.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.07:43:51.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.07:43:51.25#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:51.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:51.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:51.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:51.25#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:43:51.25#ibcon#first serial, iclass 32, count 0 2006.183.07:43:51.25#ibcon#enter sib2, iclass 32, count 0 2006.183.07:43:51.25#ibcon#flushed, iclass 32, count 0 2006.183.07:43:51.25#ibcon#about to write, iclass 32, count 0 2006.183.07:43:51.25#ibcon#wrote, iclass 32, count 0 2006.183.07:43:51.25#ibcon#about to read 3, iclass 32, count 0 2006.183.07:43:51.27#ibcon#read 3, iclass 32, count 0 2006.183.07:43:51.27#ibcon#about to read 4, iclass 32, count 0 2006.183.07:43:51.27#ibcon#read 4, iclass 32, count 0 2006.183.07:43:51.27#ibcon#about to read 5, iclass 32, count 0 2006.183.07:43:51.27#ibcon#read 5, iclass 32, count 0 2006.183.07:43:51.27#ibcon#about to read 6, iclass 32, count 0 2006.183.07:43:51.27#ibcon#read 6, iclass 32, count 0 2006.183.07:43:51.27#ibcon#end of sib2, iclass 32, count 0 2006.183.07:43:51.27#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:43:51.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:43:51.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:43:51.27#ibcon#*before write, iclass 32, count 0 2006.183.07:43:51.27#ibcon#enter sib2, iclass 32, count 0 2006.183.07:43:51.27#ibcon#flushed, iclass 32, count 0 2006.183.07:43:51.27#ibcon#about to write, iclass 32, count 0 2006.183.07:43:51.27#ibcon#wrote, iclass 32, count 0 2006.183.07:43:51.27#ibcon#about to read 3, iclass 32, count 0 2006.183.07:43:51.31#ibcon#read 3, iclass 32, count 0 2006.183.07:43:51.31#ibcon#about to read 4, iclass 32, count 0 2006.183.07:43:51.31#ibcon#read 4, iclass 32, count 0 2006.183.07:43:51.31#ibcon#about to read 5, iclass 32, count 0 2006.183.07:43:51.31#ibcon#read 5, iclass 32, count 0 2006.183.07:43:51.31#ibcon#about to read 6, iclass 32, count 0 2006.183.07:43:51.31#ibcon#read 6, iclass 32, count 0 2006.183.07:43:51.31#ibcon#end of sib2, iclass 32, count 0 2006.183.07:43:51.31#ibcon#*after write, iclass 32, count 0 2006.183.07:43:51.31#ibcon#*before return 0, iclass 32, count 0 2006.183.07:43:51.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:51.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:43:51.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:43:51.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:43:51.31$vc4f8/vb=3,4 2006.183.07:43:51.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.07:43:51.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.07:43:51.31#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:51.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:51.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:51.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:51.37#ibcon#enter wrdev, iclass 34, count 2 2006.183.07:43:51.37#ibcon#first serial, iclass 34, count 2 2006.183.07:43:51.37#ibcon#enter sib2, iclass 34, count 2 2006.183.07:43:51.37#ibcon#flushed, iclass 34, count 2 2006.183.07:43:51.37#ibcon#about to write, iclass 34, count 2 2006.183.07:43:51.37#ibcon#wrote, iclass 34, count 2 2006.183.07:43:51.37#ibcon#about to read 3, iclass 34, count 2 2006.183.07:43:51.39#ibcon#read 3, iclass 34, count 2 2006.183.07:43:51.39#ibcon#about to read 4, iclass 34, count 2 2006.183.07:43:51.39#ibcon#read 4, iclass 34, count 2 2006.183.07:43:51.39#ibcon#about to read 5, iclass 34, count 2 2006.183.07:43:51.39#ibcon#read 5, iclass 34, count 2 2006.183.07:43:51.39#ibcon#about to read 6, iclass 34, count 2 2006.183.07:43:51.39#ibcon#read 6, iclass 34, count 2 2006.183.07:43:51.39#ibcon#end of sib2, iclass 34, count 2 2006.183.07:43:51.39#ibcon#*mode == 0, iclass 34, count 2 2006.183.07:43:51.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.07:43:51.39#ibcon#[27=AT03-04\r\n] 2006.183.07:43:51.39#ibcon#*before write, iclass 34, count 2 2006.183.07:43:51.39#ibcon#enter sib2, iclass 34, count 2 2006.183.07:43:51.39#ibcon#flushed, iclass 34, count 2 2006.183.07:43:51.39#ibcon#about to write, iclass 34, count 2 2006.183.07:43:51.39#ibcon#wrote, iclass 34, count 2 2006.183.07:43:51.39#ibcon#about to read 3, iclass 34, count 2 2006.183.07:43:51.42#ibcon#read 3, iclass 34, count 2 2006.183.07:43:51.42#ibcon#about to read 4, iclass 34, count 2 2006.183.07:43:51.42#ibcon#read 4, iclass 34, count 2 2006.183.07:43:51.42#ibcon#about to read 5, iclass 34, count 2 2006.183.07:43:51.42#ibcon#read 5, iclass 34, count 2 2006.183.07:43:51.42#ibcon#about to read 6, iclass 34, count 2 2006.183.07:43:51.42#ibcon#read 6, iclass 34, count 2 2006.183.07:43:51.42#ibcon#end of sib2, iclass 34, count 2 2006.183.07:43:51.42#ibcon#*after write, iclass 34, count 2 2006.183.07:43:51.42#ibcon#*before return 0, iclass 34, count 2 2006.183.07:43:51.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:51.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:43:51.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.07:43:51.42#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:51.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:51.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:51.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:51.54#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:43:51.54#ibcon#first serial, iclass 34, count 0 2006.183.07:43:51.54#ibcon#enter sib2, iclass 34, count 0 2006.183.07:43:51.54#ibcon#flushed, iclass 34, count 0 2006.183.07:43:51.54#ibcon#about to write, iclass 34, count 0 2006.183.07:43:51.54#ibcon#wrote, iclass 34, count 0 2006.183.07:43:51.54#ibcon#about to read 3, iclass 34, count 0 2006.183.07:43:51.56#ibcon#read 3, iclass 34, count 0 2006.183.07:43:51.56#ibcon#about to read 4, iclass 34, count 0 2006.183.07:43:51.56#ibcon#read 4, iclass 34, count 0 2006.183.07:43:51.56#ibcon#about to read 5, iclass 34, count 0 2006.183.07:43:51.56#ibcon#read 5, iclass 34, count 0 2006.183.07:43:51.56#ibcon#about to read 6, iclass 34, count 0 2006.183.07:43:51.56#ibcon#read 6, iclass 34, count 0 2006.183.07:43:51.56#ibcon#end of sib2, iclass 34, count 0 2006.183.07:43:51.56#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:43:51.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:43:51.56#ibcon#[27=USB\r\n] 2006.183.07:43:51.56#ibcon#*before write, iclass 34, count 0 2006.183.07:43:51.56#ibcon#enter sib2, iclass 34, count 0 2006.183.07:43:51.56#ibcon#flushed, iclass 34, count 0 2006.183.07:43:51.56#ibcon#about to write, iclass 34, count 0 2006.183.07:43:51.56#ibcon#wrote, iclass 34, count 0 2006.183.07:43:51.56#ibcon#about to read 3, iclass 34, count 0 2006.183.07:43:51.59#ibcon#read 3, iclass 34, count 0 2006.183.07:43:51.59#ibcon#about to read 4, iclass 34, count 0 2006.183.07:43:51.59#ibcon#read 4, iclass 34, count 0 2006.183.07:43:51.59#ibcon#about to read 5, iclass 34, count 0 2006.183.07:43:51.59#ibcon#read 5, iclass 34, count 0 2006.183.07:43:51.59#ibcon#about to read 6, iclass 34, count 0 2006.183.07:43:51.59#ibcon#read 6, iclass 34, count 0 2006.183.07:43:51.59#ibcon#end of sib2, iclass 34, count 0 2006.183.07:43:51.59#ibcon#*after write, iclass 34, count 0 2006.183.07:43:51.59#ibcon#*before return 0, iclass 34, count 0 2006.183.07:43:51.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:51.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:43:51.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:43:51.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:43:51.59$vc4f8/vblo=4,712.99 2006.183.07:43:51.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:43:51.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:43:51.59#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:51.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:51.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:51.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:51.59#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:43:51.59#ibcon#first serial, iclass 36, count 0 2006.183.07:43:51.59#ibcon#enter sib2, iclass 36, count 0 2006.183.07:43:51.59#ibcon#flushed, iclass 36, count 0 2006.183.07:43:51.59#ibcon#about to write, iclass 36, count 0 2006.183.07:43:51.59#ibcon#wrote, iclass 36, count 0 2006.183.07:43:51.59#ibcon#about to read 3, iclass 36, count 0 2006.183.07:43:51.61#ibcon#read 3, iclass 36, count 0 2006.183.07:43:51.61#ibcon#about to read 4, iclass 36, count 0 2006.183.07:43:51.61#ibcon#read 4, iclass 36, count 0 2006.183.07:43:51.61#ibcon#about to read 5, iclass 36, count 0 2006.183.07:43:51.61#ibcon#read 5, iclass 36, count 0 2006.183.07:43:51.61#ibcon#about to read 6, iclass 36, count 0 2006.183.07:43:51.61#ibcon#read 6, iclass 36, count 0 2006.183.07:43:51.61#ibcon#end of sib2, iclass 36, count 0 2006.183.07:43:51.61#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:43:51.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:43:51.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:43:51.61#ibcon#*before write, iclass 36, count 0 2006.183.07:43:51.61#ibcon#enter sib2, iclass 36, count 0 2006.183.07:43:51.61#ibcon#flushed, iclass 36, count 0 2006.183.07:43:51.61#ibcon#about to write, iclass 36, count 0 2006.183.07:43:51.61#ibcon#wrote, iclass 36, count 0 2006.183.07:43:51.61#ibcon#about to read 3, iclass 36, count 0 2006.183.07:43:51.65#ibcon#read 3, iclass 36, count 0 2006.183.07:43:51.65#ibcon#about to read 4, iclass 36, count 0 2006.183.07:43:51.65#ibcon#read 4, iclass 36, count 0 2006.183.07:43:51.65#ibcon#about to read 5, iclass 36, count 0 2006.183.07:43:51.65#ibcon#read 5, iclass 36, count 0 2006.183.07:43:51.65#ibcon#about to read 6, iclass 36, count 0 2006.183.07:43:51.65#ibcon#read 6, iclass 36, count 0 2006.183.07:43:51.65#ibcon#end of sib2, iclass 36, count 0 2006.183.07:43:51.65#ibcon#*after write, iclass 36, count 0 2006.183.07:43:51.65#ibcon#*before return 0, iclass 36, count 0 2006.183.07:43:51.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:51.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:43:51.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:43:51.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:43:51.65$vc4f8/vb=4,4 2006.183.07:43:51.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.07:43:51.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.07:43:51.65#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:51.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:51.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:51.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:51.71#ibcon#enter wrdev, iclass 38, count 2 2006.183.07:43:51.71#ibcon#first serial, iclass 38, count 2 2006.183.07:43:51.71#ibcon#enter sib2, iclass 38, count 2 2006.183.07:43:51.71#ibcon#flushed, iclass 38, count 2 2006.183.07:43:51.71#ibcon#about to write, iclass 38, count 2 2006.183.07:43:51.71#ibcon#wrote, iclass 38, count 2 2006.183.07:43:51.71#ibcon#about to read 3, iclass 38, count 2 2006.183.07:43:51.73#ibcon#read 3, iclass 38, count 2 2006.183.07:43:51.73#ibcon#about to read 4, iclass 38, count 2 2006.183.07:43:51.73#ibcon#read 4, iclass 38, count 2 2006.183.07:43:51.73#ibcon#about to read 5, iclass 38, count 2 2006.183.07:43:51.73#ibcon#read 5, iclass 38, count 2 2006.183.07:43:51.73#ibcon#about to read 6, iclass 38, count 2 2006.183.07:43:51.73#ibcon#read 6, iclass 38, count 2 2006.183.07:43:51.73#ibcon#end of sib2, iclass 38, count 2 2006.183.07:43:51.73#ibcon#*mode == 0, iclass 38, count 2 2006.183.07:43:51.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.07:43:51.73#ibcon#[27=AT04-04\r\n] 2006.183.07:43:51.73#ibcon#*before write, iclass 38, count 2 2006.183.07:43:51.73#ibcon#enter sib2, iclass 38, count 2 2006.183.07:43:51.73#ibcon#flushed, iclass 38, count 2 2006.183.07:43:51.73#ibcon#about to write, iclass 38, count 2 2006.183.07:43:51.73#ibcon#wrote, iclass 38, count 2 2006.183.07:43:51.73#ibcon#about to read 3, iclass 38, count 2 2006.183.07:43:51.76#ibcon#read 3, iclass 38, count 2 2006.183.07:43:51.76#ibcon#about to read 4, iclass 38, count 2 2006.183.07:43:51.76#ibcon#read 4, iclass 38, count 2 2006.183.07:43:51.76#ibcon#about to read 5, iclass 38, count 2 2006.183.07:43:51.76#ibcon#read 5, iclass 38, count 2 2006.183.07:43:51.76#ibcon#about to read 6, iclass 38, count 2 2006.183.07:43:51.76#ibcon#read 6, iclass 38, count 2 2006.183.07:43:51.76#ibcon#end of sib2, iclass 38, count 2 2006.183.07:43:51.76#ibcon#*after write, iclass 38, count 2 2006.183.07:43:51.76#ibcon#*before return 0, iclass 38, count 2 2006.183.07:43:51.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:51.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:43:51.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.07:43:51.76#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:51.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:51.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:51.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:51.88#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:43:51.88#ibcon#first serial, iclass 38, count 0 2006.183.07:43:51.88#ibcon#enter sib2, iclass 38, count 0 2006.183.07:43:51.88#ibcon#flushed, iclass 38, count 0 2006.183.07:43:51.88#ibcon#about to write, iclass 38, count 0 2006.183.07:43:51.88#ibcon#wrote, iclass 38, count 0 2006.183.07:43:51.88#ibcon#about to read 3, iclass 38, count 0 2006.183.07:43:51.90#ibcon#read 3, iclass 38, count 0 2006.183.07:43:51.90#ibcon#about to read 4, iclass 38, count 0 2006.183.07:43:51.90#ibcon#read 4, iclass 38, count 0 2006.183.07:43:51.90#ibcon#about to read 5, iclass 38, count 0 2006.183.07:43:51.90#ibcon#read 5, iclass 38, count 0 2006.183.07:43:51.90#ibcon#about to read 6, iclass 38, count 0 2006.183.07:43:51.90#ibcon#read 6, iclass 38, count 0 2006.183.07:43:51.90#ibcon#end of sib2, iclass 38, count 0 2006.183.07:43:51.90#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:43:51.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:43:51.90#ibcon#[27=USB\r\n] 2006.183.07:43:51.90#ibcon#*before write, iclass 38, count 0 2006.183.07:43:51.90#ibcon#enter sib2, iclass 38, count 0 2006.183.07:43:51.90#ibcon#flushed, iclass 38, count 0 2006.183.07:43:51.90#ibcon#about to write, iclass 38, count 0 2006.183.07:43:51.90#ibcon#wrote, iclass 38, count 0 2006.183.07:43:51.90#ibcon#about to read 3, iclass 38, count 0 2006.183.07:43:51.93#ibcon#read 3, iclass 38, count 0 2006.183.07:43:51.93#ibcon#about to read 4, iclass 38, count 0 2006.183.07:43:51.93#ibcon#read 4, iclass 38, count 0 2006.183.07:43:51.93#ibcon#about to read 5, iclass 38, count 0 2006.183.07:43:51.93#ibcon#read 5, iclass 38, count 0 2006.183.07:43:51.93#ibcon#about to read 6, iclass 38, count 0 2006.183.07:43:51.93#ibcon#read 6, iclass 38, count 0 2006.183.07:43:51.93#ibcon#end of sib2, iclass 38, count 0 2006.183.07:43:51.93#ibcon#*after write, iclass 38, count 0 2006.183.07:43:51.93#ibcon#*before return 0, iclass 38, count 0 2006.183.07:43:51.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:51.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:43:51.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:43:51.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:43:51.93$vc4f8/vblo=5,744.99 2006.183.07:43:51.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:43:51.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:43:51.93#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:51.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:51.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:51.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:51.93#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:43:51.93#ibcon#first serial, iclass 40, count 0 2006.183.07:43:51.93#ibcon#enter sib2, iclass 40, count 0 2006.183.07:43:51.93#ibcon#flushed, iclass 40, count 0 2006.183.07:43:51.93#ibcon#about to write, iclass 40, count 0 2006.183.07:43:51.93#ibcon#wrote, iclass 40, count 0 2006.183.07:43:51.93#ibcon#about to read 3, iclass 40, count 0 2006.183.07:43:51.95#ibcon#read 3, iclass 40, count 0 2006.183.07:43:51.95#ibcon#about to read 4, iclass 40, count 0 2006.183.07:43:51.95#ibcon#read 4, iclass 40, count 0 2006.183.07:43:51.95#ibcon#about to read 5, iclass 40, count 0 2006.183.07:43:51.95#ibcon#read 5, iclass 40, count 0 2006.183.07:43:51.95#ibcon#about to read 6, iclass 40, count 0 2006.183.07:43:51.95#ibcon#read 6, iclass 40, count 0 2006.183.07:43:51.95#ibcon#end of sib2, iclass 40, count 0 2006.183.07:43:51.95#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:43:51.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:43:51.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:43:51.95#ibcon#*before write, iclass 40, count 0 2006.183.07:43:51.95#ibcon#enter sib2, iclass 40, count 0 2006.183.07:43:51.95#ibcon#flushed, iclass 40, count 0 2006.183.07:43:51.95#ibcon#about to write, iclass 40, count 0 2006.183.07:43:51.95#ibcon#wrote, iclass 40, count 0 2006.183.07:43:51.95#ibcon#about to read 3, iclass 40, count 0 2006.183.07:43:51.99#ibcon#read 3, iclass 40, count 0 2006.183.07:43:51.99#ibcon#about to read 4, iclass 40, count 0 2006.183.07:43:51.99#ibcon#read 4, iclass 40, count 0 2006.183.07:43:51.99#ibcon#about to read 5, iclass 40, count 0 2006.183.07:43:51.99#ibcon#read 5, iclass 40, count 0 2006.183.07:43:51.99#ibcon#about to read 6, iclass 40, count 0 2006.183.07:43:51.99#ibcon#read 6, iclass 40, count 0 2006.183.07:43:51.99#ibcon#end of sib2, iclass 40, count 0 2006.183.07:43:51.99#ibcon#*after write, iclass 40, count 0 2006.183.07:43:51.99#ibcon#*before return 0, iclass 40, count 0 2006.183.07:43:51.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:51.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:43:51.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:43:51.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:43:51.99$vc4f8/vb=5,4 2006.183.07:43:51.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.07:43:51.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.07:43:51.99#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:51.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:52.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:52.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:52.05#ibcon#enter wrdev, iclass 4, count 2 2006.183.07:43:52.05#ibcon#first serial, iclass 4, count 2 2006.183.07:43:52.05#ibcon#enter sib2, iclass 4, count 2 2006.183.07:43:52.05#ibcon#flushed, iclass 4, count 2 2006.183.07:43:52.05#ibcon#about to write, iclass 4, count 2 2006.183.07:43:52.05#ibcon#wrote, iclass 4, count 2 2006.183.07:43:52.05#ibcon#about to read 3, iclass 4, count 2 2006.183.07:43:52.07#ibcon#read 3, iclass 4, count 2 2006.183.07:43:52.07#ibcon#about to read 4, iclass 4, count 2 2006.183.07:43:52.07#ibcon#read 4, iclass 4, count 2 2006.183.07:43:52.07#ibcon#about to read 5, iclass 4, count 2 2006.183.07:43:52.07#ibcon#read 5, iclass 4, count 2 2006.183.07:43:52.07#ibcon#about to read 6, iclass 4, count 2 2006.183.07:43:52.07#ibcon#read 6, iclass 4, count 2 2006.183.07:43:52.07#ibcon#end of sib2, iclass 4, count 2 2006.183.07:43:52.07#ibcon#*mode == 0, iclass 4, count 2 2006.183.07:43:52.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.07:43:52.07#ibcon#[27=AT05-04\r\n] 2006.183.07:43:52.07#ibcon#*before write, iclass 4, count 2 2006.183.07:43:52.07#ibcon#enter sib2, iclass 4, count 2 2006.183.07:43:52.07#ibcon#flushed, iclass 4, count 2 2006.183.07:43:52.07#ibcon#about to write, iclass 4, count 2 2006.183.07:43:52.07#ibcon#wrote, iclass 4, count 2 2006.183.07:43:52.07#ibcon#about to read 3, iclass 4, count 2 2006.183.07:43:52.10#ibcon#read 3, iclass 4, count 2 2006.183.07:43:52.10#ibcon#about to read 4, iclass 4, count 2 2006.183.07:43:52.10#ibcon#read 4, iclass 4, count 2 2006.183.07:43:52.10#ibcon#about to read 5, iclass 4, count 2 2006.183.07:43:52.10#ibcon#read 5, iclass 4, count 2 2006.183.07:43:52.10#ibcon#about to read 6, iclass 4, count 2 2006.183.07:43:52.10#ibcon#read 6, iclass 4, count 2 2006.183.07:43:52.10#ibcon#end of sib2, iclass 4, count 2 2006.183.07:43:52.10#ibcon#*after write, iclass 4, count 2 2006.183.07:43:52.10#ibcon#*before return 0, iclass 4, count 2 2006.183.07:43:52.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:52.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:43:52.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.07:43:52.10#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:52.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:52.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:52.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:52.22#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:43:52.22#ibcon#first serial, iclass 4, count 0 2006.183.07:43:52.22#ibcon#enter sib2, iclass 4, count 0 2006.183.07:43:52.22#ibcon#flushed, iclass 4, count 0 2006.183.07:43:52.22#ibcon#about to write, iclass 4, count 0 2006.183.07:43:52.22#ibcon#wrote, iclass 4, count 0 2006.183.07:43:52.22#ibcon#about to read 3, iclass 4, count 0 2006.183.07:43:52.24#ibcon#read 3, iclass 4, count 0 2006.183.07:43:52.24#ibcon#about to read 4, iclass 4, count 0 2006.183.07:43:52.24#ibcon#read 4, iclass 4, count 0 2006.183.07:43:52.24#ibcon#about to read 5, iclass 4, count 0 2006.183.07:43:52.24#ibcon#read 5, iclass 4, count 0 2006.183.07:43:52.24#ibcon#about to read 6, iclass 4, count 0 2006.183.07:43:52.24#ibcon#read 6, iclass 4, count 0 2006.183.07:43:52.24#ibcon#end of sib2, iclass 4, count 0 2006.183.07:43:52.24#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:43:52.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:43:52.24#ibcon#[27=USB\r\n] 2006.183.07:43:52.24#ibcon#*before write, iclass 4, count 0 2006.183.07:43:52.24#ibcon#enter sib2, iclass 4, count 0 2006.183.07:43:52.24#ibcon#flushed, iclass 4, count 0 2006.183.07:43:52.24#ibcon#about to write, iclass 4, count 0 2006.183.07:43:52.24#ibcon#wrote, iclass 4, count 0 2006.183.07:43:52.24#ibcon#about to read 3, iclass 4, count 0 2006.183.07:43:52.27#ibcon#read 3, iclass 4, count 0 2006.183.07:43:52.27#ibcon#about to read 4, iclass 4, count 0 2006.183.07:43:52.27#ibcon#read 4, iclass 4, count 0 2006.183.07:43:52.27#ibcon#about to read 5, iclass 4, count 0 2006.183.07:43:52.27#ibcon#read 5, iclass 4, count 0 2006.183.07:43:52.27#ibcon#about to read 6, iclass 4, count 0 2006.183.07:43:52.27#ibcon#read 6, iclass 4, count 0 2006.183.07:43:52.27#ibcon#end of sib2, iclass 4, count 0 2006.183.07:43:52.27#ibcon#*after write, iclass 4, count 0 2006.183.07:43:52.27#ibcon#*before return 0, iclass 4, count 0 2006.183.07:43:52.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:52.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:43:52.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:43:52.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:43:52.27$vc4f8/vblo=6,752.99 2006.183.07:43:52.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:43:52.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:43:52.27#ibcon#ireg 17 cls_cnt 0 2006.183.07:43:52.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:52.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:52.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:52.27#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:43:52.27#ibcon#first serial, iclass 6, count 0 2006.183.07:43:52.27#ibcon#enter sib2, iclass 6, count 0 2006.183.07:43:52.27#ibcon#flushed, iclass 6, count 0 2006.183.07:43:52.27#ibcon#about to write, iclass 6, count 0 2006.183.07:43:52.27#ibcon#wrote, iclass 6, count 0 2006.183.07:43:52.27#ibcon#about to read 3, iclass 6, count 0 2006.183.07:43:52.29#ibcon#read 3, iclass 6, count 0 2006.183.07:43:52.29#ibcon#about to read 4, iclass 6, count 0 2006.183.07:43:52.29#ibcon#read 4, iclass 6, count 0 2006.183.07:43:52.29#ibcon#about to read 5, iclass 6, count 0 2006.183.07:43:52.29#ibcon#read 5, iclass 6, count 0 2006.183.07:43:52.29#ibcon#about to read 6, iclass 6, count 0 2006.183.07:43:52.29#ibcon#read 6, iclass 6, count 0 2006.183.07:43:52.29#ibcon#end of sib2, iclass 6, count 0 2006.183.07:43:52.29#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:43:52.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:43:52.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:43:52.29#ibcon#*before write, iclass 6, count 0 2006.183.07:43:52.29#ibcon#enter sib2, iclass 6, count 0 2006.183.07:43:52.29#ibcon#flushed, iclass 6, count 0 2006.183.07:43:52.29#ibcon#about to write, iclass 6, count 0 2006.183.07:43:52.29#ibcon#wrote, iclass 6, count 0 2006.183.07:43:52.29#ibcon#about to read 3, iclass 6, count 0 2006.183.07:43:52.33#ibcon#read 3, iclass 6, count 0 2006.183.07:43:52.33#ibcon#about to read 4, iclass 6, count 0 2006.183.07:43:52.33#ibcon#read 4, iclass 6, count 0 2006.183.07:43:52.33#ibcon#about to read 5, iclass 6, count 0 2006.183.07:43:52.33#ibcon#read 5, iclass 6, count 0 2006.183.07:43:52.33#ibcon#about to read 6, iclass 6, count 0 2006.183.07:43:52.33#ibcon#read 6, iclass 6, count 0 2006.183.07:43:52.33#ibcon#end of sib2, iclass 6, count 0 2006.183.07:43:52.33#ibcon#*after write, iclass 6, count 0 2006.183.07:43:52.33#ibcon#*before return 0, iclass 6, count 0 2006.183.07:43:52.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:52.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:43:52.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:43:52.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:43:52.33$vc4f8/vb=6,4 2006.183.07:43:52.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.07:43:52.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.07:43:52.33#ibcon#ireg 11 cls_cnt 2 2006.183.07:43:52.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:52.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:52.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:52.39#ibcon#enter wrdev, iclass 10, count 2 2006.183.07:43:52.39#ibcon#first serial, iclass 10, count 2 2006.183.07:43:52.39#ibcon#enter sib2, iclass 10, count 2 2006.183.07:43:52.39#ibcon#flushed, iclass 10, count 2 2006.183.07:43:52.39#ibcon#about to write, iclass 10, count 2 2006.183.07:43:52.39#ibcon#wrote, iclass 10, count 2 2006.183.07:43:52.39#ibcon#about to read 3, iclass 10, count 2 2006.183.07:43:52.41#ibcon#read 3, iclass 10, count 2 2006.183.07:43:52.41#ibcon#about to read 4, iclass 10, count 2 2006.183.07:43:52.41#ibcon#read 4, iclass 10, count 2 2006.183.07:43:52.41#ibcon#about to read 5, iclass 10, count 2 2006.183.07:43:52.41#ibcon#read 5, iclass 10, count 2 2006.183.07:43:52.41#ibcon#about to read 6, iclass 10, count 2 2006.183.07:43:52.41#ibcon#read 6, iclass 10, count 2 2006.183.07:43:52.41#ibcon#end of sib2, iclass 10, count 2 2006.183.07:43:52.41#ibcon#*mode == 0, iclass 10, count 2 2006.183.07:43:52.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.07:43:52.41#ibcon#[27=AT06-04\r\n] 2006.183.07:43:52.41#ibcon#*before write, iclass 10, count 2 2006.183.07:43:52.41#ibcon#enter sib2, iclass 10, count 2 2006.183.07:43:52.41#ibcon#flushed, iclass 10, count 2 2006.183.07:43:52.41#ibcon#about to write, iclass 10, count 2 2006.183.07:43:52.41#ibcon#wrote, iclass 10, count 2 2006.183.07:43:52.41#ibcon#about to read 3, iclass 10, count 2 2006.183.07:43:52.44#ibcon#read 3, iclass 10, count 2 2006.183.07:43:52.44#ibcon#about to read 4, iclass 10, count 2 2006.183.07:43:52.44#ibcon#read 4, iclass 10, count 2 2006.183.07:43:52.44#ibcon#about to read 5, iclass 10, count 2 2006.183.07:43:52.44#ibcon#read 5, iclass 10, count 2 2006.183.07:43:52.44#ibcon#about to read 6, iclass 10, count 2 2006.183.07:43:52.44#ibcon#read 6, iclass 10, count 2 2006.183.07:43:52.44#ibcon#end of sib2, iclass 10, count 2 2006.183.07:43:52.44#ibcon#*after write, iclass 10, count 2 2006.183.07:43:52.44#ibcon#*before return 0, iclass 10, count 2 2006.183.07:43:52.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:52.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:43:52.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.07:43:52.44#ibcon#ireg 7 cls_cnt 0 2006.183.07:43:52.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:52.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:52.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:52.56#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:43:52.56#ibcon#first serial, iclass 10, count 0 2006.183.07:43:52.56#ibcon#enter sib2, iclass 10, count 0 2006.183.07:43:52.56#ibcon#flushed, iclass 10, count 0 2006.183.07:43:52.56#ibcon#about to write, iclass 10, count 0 2006.183.07:43:52.56#ibcon#wrote, iclass 10, count 0 2006.183.07:43:52.56#ibcon#about to read 3, iclass 10, count 0 2006.183.07:43:52.58#ibcon#read 3, iclass 10, count 0 2006.183.07:43:52.58#ibcon#about to read 4, iclass 10, count 0 2006.183.07:43:52.58#ibcon#read 4, iclass 10, count 0 2006.183.07:43:52.58#ibcon#about to read 5, iclass 10, count 0 2006.183.07:43:52.58#ibcon#read 5, iclass 10, count 0 2006.183.07:43:52.58#ibcon#about to read 6, iclass 10, count 0 2006.183.07:43:52.58#ibcon#read 6, iclass 10, count 0 2006.183.07:43:52.58#ibcon#end of sib2, iclass 10, count 0 2006.183.07:43:52.58#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:43:52.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:43:52.58#ibcon#[27=USB\r\n] 2006.183.07:43:52.58#ibcon#*before write, iclass 10, count 0 2006.183.07:43:52.58#ibcon#enter sib2, iclass 10, count 0 2006.183.07:43:52.58#ibcon#flushed, iclass 10, count 0 2006.183.07:43:52.58#ibcon#about to write, iclass 10, count 0 2006.183.07:43:52.58#ibcon#wrote, iclass 10, count 0 2006.183.07:43:52.58#ibcon#about to read 3, iclass 10, count 0 2006.183.07:43:52.61#ibcon#read 3, iclass 10, count 0 2006.183.07:43:52.61#ibcon#about to read 4, iclass 10, count 0 2006.183.07:43:52.61#ibcon#read 4, iclass 10, count 0 2006.183.07:43:52.61#ibcon#about to read 5, iclass 10, count 0 2006.183.07:43:52.61#ibcon#read 5, iclass 10, count 0 2006.183.07:43:52.61#ibcon#about to read 6, iclass 10, count 0 2006.183.07:43:52.61#ibcon#read 6, iclass 10, count 0 2006.183.07:43:52.61#ibcon#end of sib2, iclass 10, count 0 2006.183.07:43:52.61#ibcon#*after write, iclass 10, count 0 2006.183.07:43:52.61#ibcon#*before return 0, iclass 10, count 0 2006.183.07:43:52.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:52.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:43:52.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:43:52.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:43:52.61$vc4f8/vabw=wide 2006.183.07:43:52.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.07:43:52.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.07:43:52.61#ibcon#ireg 8 cls_cnt 0 2006.183.07:43:52.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:52.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:52.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:52.61#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:43:52.61#ibcon#first serial, iclass 12, count 0 2006.183.07:43:52.61#ibcon#enter sib2, iclass 12, count 0 2006.183.07:43:52.61#ibcon#flushed, iclass 12, count 0 2006.183.07:43:52.61#ibcon#about to write, iclass 12, count 0 2006.183.07:43:52.61#ibcon#wrote, iclass 12, count 0 2006.183.07:43:52.61#ibcon#about to read 3, iclass 12, count 0 2006.183.07:43:52.63#ibcon#read 3, iclass 12, count 0 2006.183.07:43:52.63#ibcon#about to read 4, iclass 12, count 0 2006.183.07:43:52.63#ibcon#read 4, iclass 12, count 0 2006.183.07:43:52.63#ibcon#about to read 5, iclass 12, count 0 2006.183.07:43:52.63#ibcon#read 5, iclass 12, count 0 2006.183.07:43:52.63#ibcon#about to read 6, iclass 12, count 0 2006.183.07:43:52.63#ibcon#read 6, iclass 12, count 0 2006.183.07:43:52.63#ibcon#end of sib2, iclass 12, count 0 2006.183.07:43:52.63#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:43:52.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:43:52.63#ibcon#[25=BW32\r\n] 2006.183.07:43:52.63#ibcon#*before write, iclass 12, count 0 2006.183.07:43:52.63#ibcon#enter sib2, iclass 12, count 0 2006.183.07:43:52.63#ibcon#flushed, iclass 12, count 0 2006.183.07:43:52.63#ibcon#about to write, iclass 12, count 0 2006.183.07:43:52.63#ibcon#wrote, iclass 12, count 0 2006.183.07:43:52.63#ibcon#about to read 3, iclass 12, count 0 2006.183.07:43:52.66#ibcon#read 3, iclass 12, count 0 2006.183.07:43:52.66#ibcon#about to read 4, iclass 12, count 0 2006.183.07:43:52.66#ibcon#read 4, iclass 12, count 0 2006.183.07:43:52.66#ibcon#about to read 5, iclass 12, count 0 2006.183.07:43:52.66#ibcon#read 5, iclass 12, count 0 2006.183.07:43:52.66#ibcon#about to read 6, iclass 12, count 0 2006.183.07:43:52.66#ibcon#read 6, iclass 12, count 0 2006.183.07:43:52.66#ibcon#end of sib2, iclass 12, count 0 2006.183.07:43:52.66#ibcon#*after write, iclass 12, count 0 2006.183.07:43:52.66#ibcon#*before return 0, iclass 12, count 0 2006.183.07:43:52.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:52.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:43:52.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:43:52.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:43:52.66$vc4f8/vbbw=wide 2006.183.07:43:52.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.07:43:52.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.07:43:52.66#ibcon#ireg 8 cls_cnt 0 2006.183.07:43:52.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:43:52.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:43:52.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:43:52.73#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:43:52.73#ibcon#first serial, iclass 14, count 0 2006.183.07:43:52.73#ibcon#enter sib2, iclass 14, count 0 2006.183.07:43:52.73#ibcon#flushed, iclass 14, count 0 2006.183.07:43:52.73#ibcon#about to write, iclass 14, count 0 2006.183.07:43:52.73#ibcon#wrote, iclass 14, count 0 2006.183.07:43:52.73#ibcon#about to read 3, iclass 14, count 0 2006.183.07:43:52.75#ibcon#read 3, iclass 14, count 0 2006.183.07:43:52.75#ibcon#about to read 4, iclass 14, count 0 2006.183.07:43:52.75#ibcon#read 4, iclass 14, count 0 2006.183.07:43:52.75#ibcon#about to read 5, iclass 14, count 0 2006.183.07:43:52.75#ibcon#read 5, iclass 14, count 0 2006.183.07:43:52.75#ibcon#about to read 6, iclass 14, count 0 2006.183.07:43:52.75#ibcon#read 6, iclass 14, count 0 2006.183.07:43:52.75#ibcon#end of sib2, iclass 14, count 0 2006.183.07:43:52.75#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:43:52.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:43:52.75#ibcon#[27=BW32\r\n] 2006.183.07:43:52.75#ibcon#*before write, iclass 14, count 0 2006.183.07:43:52.75#ibcon#enter sib2, iclass 14, count 0 2006.183.07:43:52.75#ibcon#flushed, iclass 14, count 0 2006.183.07:43:52.75#ibcon#about to write, iclass 14, count 0 2006.183.07:43:52.75#ibcon#wrote, iclass 14, count 0 2006.183.07:43:52.75#ibcon#about to read 3, iclass 14, count 0 2006.183.07:43:52.78#ibcon#read 3, iclass 14, count 0 2006.183.07:43:52.78#ibcon#about to read 4, iclass 14, count 0 2006.183.07:43:52.78#ibcon#read 4, iclass 14, count 0 2006.183.07:43:52.78#ibcon#about to read 5, iclass 14, count 0 2006.183.07:43:52.78#ibcon#read 5, iclass 14, count 0 2006.183.07:43:52.78#ibcon#about to read 6, iclass 14, count 0 2006.183.07:43:52.78#ibcon#read 6, iclass 14, count 0 2006.183.07:43:52.78#ibcon#end of sib2, iclass 14, count 0 2006.183.07:43:52.78#ibcon#*after write, iclass 14, count 0 2006.183.07:43:52.78#ibcon#*before return 0, iclass 14, count 0 2006.183.07:43:52.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:43:52.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:43:52.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:43:52.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:43:52.78$4f8m12a/ifd4f 2006.183.07:43:52.78$ifd4f/lo= 2006.183.07:43:52.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:43:52.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:43:52.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:43:52.78$ifd4f/patch= 2006.183.07:43:52.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:43:52.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:43:52.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:43:52.78$4f8m12a/"form=m,16.000,1:2 2006.183.07:43:52.78$4f8m12a/"tpicd 2006.183.07:43:52.78$4f8m12a/echo=off 2006.183.07:43:52.78$4f8m12a/xlog=off 2006.183.07:43:52.78:!2006.183.07:44:50 2006.183.07:44:30.14#trakl#Source acquired 2006.183.07:44:32.14#flagr#flagr/antenna,acquired 2006.183.07:44:50.00:preob 2006.183.07:44:51.14/onsource/TRACKING 2006.183.07:44:51.14:!2006.183.07:45:00 2006.183.07:45:00.00:data_valid=on 2006.183.07:45:00.00:midob 2006.183.07:45:00.14/onsource/TRACKING 2006.183.07:45:00.14/wx/27.93,996.2,87 2006.183.07:45:00.36/cable/+6.4528E-03 2006.183.07:45:01.45/va/01,08,usb,yes,29,31 2006.183.07:45:01.45/va/02,07,usb,yes,30,31 2006.183.07:45:01.45/va/03,06,usb,yes,31,31 2006.183.07:45:01.45/va/04,07,usb,yes,30,33 2006.183.07:45:01.45/va/05,07,usb,yes,32,34 2006.183.07:45:01.45/va/06,06,usb,yes,31,31 2006.183.07:45:01.45/va/07,06,usb,yes,32,31 2006.183.07:45:01.45/va/08,07,usb,yes,30,29 2006.183.07:45:01.68/valo/01,532.99,yes,locked 2006.183.07:45:01.68/valo/02,572.99,yes,locked 2006.183.07:45:01.68/valo/03,672.99,yes,locked 2006.183.07:45:01.68/valo/04,832.99,yes,locked 2006.183.07:45:01.68/valo/05,652.99,yes,locked 2006.183.07:45:01.68/valo/06,772.99,yes,locked 2006.183.07:45:01.68/valo/07,832.99,yes,locked 2006.183.07:45:01.68/valo/08,852.99,yes,locked 2006.183.07:45:02.77/vb/01,04,usb,yes,29,28 2006.183.07:45:02.77/vb/02,04,usb,yes,31,33 2006.183.07:45:02.77/vb/03,04,usb,yes,27,31 2006.183.07:45:02.77/vb/04,04,usb,yes,28,28 2006.183.07:45:02.77/vb/05,04,usb,yes,27,31 2006.183.07:45:02.77/vb/06,04,usb,yes,28,31 2006.183.07:45:02.77/vb/07,04,usb,yes,30,30 2006.183.07:45:02.77/vb/08,04,usb,yes,27,31 2006.183.07:45:03.00/vblo/01,632.99,yes,locked 2006.183.07:45:03.00/vblo/02,640.99,yes,locked 2006.183.07:45:03.00/vblo/03,656.99,yes,locked 2006.183.07:45:03.00/vblo/04,712.99,yes,locked 2006.183.07:45:03.00/vblo/05,744.99,yes,locked 2006.183.07:45:03.00/vblo/06,752.99,yes,locked 2006.183.07:45:03.00/vblo/07,734.99,yes,locked 2006.183.07:45:03.00/vblo/08,744.99,yes,locked 2006.183.07:45:03.15/vabw/8 2006.183.07:45:03.30/vbbw/8 2006.183.07:45:03.39/xfe/off,on,15.5 2006.183.07:45:03.77/ifatt/23,28,28,28 2006.183.07:45:04.07/fmout-gps/S +3.32E-07 2006.183.07:45:04.11:!2006.183.07:48:00 2006.183.07:48:00.00:data_valid=off 2006.183.07:48:00.00:postob 2006.183.07:48:00.13/cable/+6.4536E-03 2006.183.07:48:00.13/wx/27.94,996.2,88 2006.183.07:48:01.07/fmout-gps/S +3.33E-07 2006.183.07:48:01.07:scan_name=183-0749,k06183,60 2006.183.07:48:01.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.183.07:48:01.14#flagr#flagr/antenna,new-source 2006.183.07:48:02.14:checkk5 2006.183.07:48:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:48:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:48:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:48:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:48:04.01/chk_obsdata//k5ts1/T1830745??a.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.183.07:48:04.38/chk_obsdata//k5ts2/T1830745??b.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.183.07:48:04.75/chk_obsdata//k5ts3/T1830745??c.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.183.07:48:05.12/chk_obsdata//k5ts4/T1830745??d.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.183.07:48:05.81/k5log//k5ts1_log_newline 2006.183.07:48:06.50/k5log//k5ts2_log_newline 2006.183.07:48:07.19/k5log//k5ts3_log_newline 2006.183.07:48:07.87/k5log//k5ts4_log_newline 2006.183.07:48:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:48:07.90:4f8m12a=1 2006.183.07:48:07.90$4f8m12a/echo=on 2006.183.07:48:07.90$4f8m12a/pcalon 2006.183.07:48:07.90$pcalon/"no phase cal control is implemented here 2006.183.07:48:07.90$4f8m12a/"tpicd=stop 2006.183.07:48:07.90$4f8m12a/vc4f8 2006.183.07:48:07.90$vc4f8/valo=1,532.99 2006.183.07:48:07.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.07:48:07.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.07:48:07.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:07.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:07.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:07.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:07.90#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:48:07.90#ibcon#first serial, iclass 7, count 0 2006.183.07:48:07.90#ibcon#enter sib2, iclass 7, count 0 2006.183.07:48:07.90#ibcon#flushed, iclass 7, count 0 2006.183.07:48:07.90#ibcon#about to write, iclass 7, count 0 2006.183.07:48:07.90#ibcon#wrote, iclass 7, count 0 2006.183.07:48:07.90#ibcon#about to read 3, iclass 7, count 0 2006.183.07:48:07.94#ibcon#read 3, iclass 7, count 0 2006.183.07:48:07.94#ibcon#about to read 4, iclass 7, count 0 2006.183.07:48:07.94#ibcon#read 4, iclass 7, count 0 2006.183.07:48:07.94#ibcon#about to read 5, iclass 7, count 0 2006.183.07:48:07.94#ibcon#read 5, iclass 7, count 0 2006.183.07:48:07.94#ibcon#about to read 6, iclass 7, count 0 2006.183.07:48:07.94#ibcon#read 6, iclass 7, count 0 2006.183.07:48:07.94#ibcon#end of sib2, iclass 7, count 0 2006.183.07:48:07.94#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:48:07.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:48:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:48:07.94#ibcon#*before write, iclass 7, count 0 2006.183.07:48:07.94#ibcon#enter sib2, iclass 7, count 0 2006.183.07:48:07.94#ibcon#flushed, iclass 7, count 0 2006.183.07:48:07.94#ibcon#about to write, iclass 7, count 0 2006.183.07:48:07.94#ibcon#wrote, iclass 7, count 0 2006.183.07:48:07.94#ibcon#about to read 3, iclass 7, count 0 2006.183.07:48:07.99#ibcon#read 3, iclass 7, count 0 2006.183.07:48:07.99#ibcon#about to read 4, iclass 7, count 0 2006.183.07:48:07.99#ibcon#read 4, iclass 7, count 0 2006.183.07:48:07.99#ibcon#about to read 5, iclass 7, count 0 2006.183.07:48:07.99#ibcon#read 5, iclass 7, count 0 2006.183.07:48:07.99#ibcon#about to read 6, iclass 7, count 0 2006.183.07:48:07.99#ibcon#read 6, iclass 7, count 0 2006.183.07:48:07.99#ibcon#end of sib2, iclass 7, count 0 2006.183.07:48:07.99#ibcon#*after write, iclass 7, count 0 2006.183.07:48:07.99#ibcon#*before return 0, iclass 7, count 0 2006.183.07:48:07.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:07.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:07.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:48:07.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:48:07.99$vc4f8/va=1,8 2006.183.07:48:07.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.07:48:07.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.07:48:07.99#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:07.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:07.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:07.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:07.99#ibcon#enter wrdev, iclass 11, count 2 2006.183.07:48:07.99#ibcon#first serial, iclass 11, count 2 2006.183.07:48:07.99#ibcon#enter sib2, iclass 11, count 2 2006.183.07:48:07.99#ibcon#flushed, iclass 11, count 2 2006.183.07:48:07.99#ibcon#about to write, iclass 11, count 2 2006.183.07:48:07.99#ibcon#wrote, iclass 11, count 2 2006.183.07:48:07.99#ibcon#about to read 3, iclass 11, count 2 2006.183.07:48:08.02#ibcon#read 3, iclass 11, count 2 2006.183.07:48:08.02#ibcon#about to read 4, iclass 11, count 2 2006.183.07:48:08.02#ibcon#read 4, iclass 11, count 2 2006.183.07:48:08.02#ibcon#about to read 5, iclass 11, count 2 2006.183.07:48:08.02#ibcon#read 5, iclass 11, count 2 2006.183.07:48:08.02#ibcon#about to read 6, iclass 11, count 2 2006.183.07:48:08.02#ibcon#read 6, iclass 11, count 2 2006.183.07:48:08.02#ibcon#end of sib2, iclass 11, count 2 2006.183.07:48:08.02#ibcon#*mode == 0, iclass 11, count 2 2006.183.07:48:08.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.07:48:08.02#ibcon#[25=AT01-08\r\n] 2006.183.07:48:08.02#ibcon#*before write, iclass 11, count 2 2006.183.07:48:08.02#ibcon#enter sib2, iclass 11, count 2 2006.183.07:48:08.02#ibcon#flushed, iclass 11, count 2 2006.183.07:48:08.02#ibcon#about to write, iclass 11, count 2 2006.183.07:48:08.02#ibcon#wrote, iclass 11, count 2 2006.183.07:48:08.02#ibcon#about to read 3, iclass 11, count 2 2006.183.07:48:08.05#ibcon#read 3, iclass 11, count 2 2006.183.07:48:08.05#ibcon#about to read 4, iclass 11, count 2 2006.183.07:48:08.05#ibcon#read 4, iclass 11, count 2 2006.183.07:48:08.05#ibcon#about to read 5, iclass 11, count 2 2006.183.07:48:08.05#ibcon#read 5, iclass 11, count 2 2006.183.07:48:08.05#ibcon#about to read 6, iclass 11, count 2 2006.183.07:48:08.05#ibcon#read 6, iclass 11, count 2 2006.183.07:48:08.05#ibcon#end of sib2, iclass 11, count 2 2006.183.07:48:08.05#ibcon#*after write, iclass 11, count 2 2006.183.07:48:08.05#ibcon#*before return 0, iclass 11, count 2 2006.183.07:48:08.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:08.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:08.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.07:48:08.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:08.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:08.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:08.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:08.17#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:48:08.17#ibcon#first serial, iclass 11, count 0 2006.183.07:48:08.17#ibcon#enter sib2, iclass 11, count 0 2006.183.07:48:08.17#ibcon#flushed, iclass 11, count 0 2006.183.07:48:08.17#ibcon#about to write, iclass 11, count 0 2006.183.07:48:08.17#ibcon#wrote, iclass 11, count 0 2006.183.07:48:08.17#ibcon#about to read 3, iclass 11, count 0 2006.183.07:48:08.19#ibcon#read 3, iclass 11, count 0 2006.183.07:48:08.19#ibcon#about to read 4, iclass 11, count 0 2006.183.07:48:08.19#ibcon#read 4, iclass 11, count 0 2006.183.07:48:08.19#ibcon#about to read 5, iclass 11, count 0 2006.183.07:48:08.19#ibcon#read 5, iclass 11, count 0 2006.183.07:48:08.19#ibcon#about to read 6, iclass 11, count 0 2006.183.07:48:08.19#ibcon#read 6, iclass 11, count 0 2006.183.07:48:08.19#ibcon#end of sib2, iclass 11, count 0 2006.183.07:48:08.19#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:48:08.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:48:08.19#ibcon#[25=USB\r\n] 2006.183.07:48:08.19#ibcon#*before write, iclass 11, count 0 2006.183.07:48:08.19#ibcon#enter sib2, iclass 11, count 0 2006.183.07:48:08.19#ibcon#flushed, iclass 11, count 0 2006.183.07:48:08.19#ibcon#about to write, iclass 11, count 0 2006.183.07:48:08.19#ibcon#wrote, iclass 11, count 0 2006.183.07:48:08.19#ibcon#about to read 3, iclass 11, count 0 2006.183.07:48:08.22#ibcon#read 3, iclass 11, count 0 2006.183.07:48:08.22#ibcon#about to read 4, iclass 11, count 0 2006.183.07:48:08.22#ibcon#read 4, iclass 11, count 0 2006.183.07:48:08.22#ibcon#about to read 5, iclass 11, count 0 2006.183.07:48:08.22#ibcon#read 5, iclass 11, count 0 2006.183.07:48:08.22#ibcon#about to read 6, iclass 11, count 0 2006.183.07:48:08.22#ibcon#read 6, iclass 11, count 0 2006.183.07:48:08.22#ibcon#end of sib2, iclass 11, count 0 2006.183.07:48:08.22#ibcon#*after write, iclass 11, count 0 2006.183.07:48:08.22#ibcon#*before return 0, iclass 11, count 0 2006.183.07:48:08.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:08.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:08.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:48:08.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:48:08.22$vc4f8/valo=2,572.99 2006.183.07:48:08.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:48:08.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:48:08.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:08.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:08.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:08.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:08.22#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:48:08.22#ibcon#first serial, iclass 13, count 0 2006.183.07:48:08.22#ibcon#enter sib2, iclass 13, count 0 2006.183.07:48:08.22#ibcon#flushed, iclass 13, count 0 2006.183.07:48:08.22#ibcon#about to write, iclass 13, count 0 2006.183.07:48:08.22#ibcon#wrote, iclass 13, count 0 2006.183.07:48:08.22#ibcon#about to read 3, iclass 13, count 0 2006.183.07:48:08.24#ibcon#read 3, iclass 13, count 0 2006.183.07:48:08.24#ibcon#about to read 4, iclass 13, count 0 2006.183.07:48:08.24#ibcon#read 4, iclass 13, count 0 2006.183.07:48:08.24#ibcon#about to read 5, iclass 13, count 0 2006.183.07:48:08.24#ibcon#read 5, iclass 13, count 0 2006.183.07:48:08.24#ibcon#about to read 6, iclass 13, count 0 2006.183.07:48:08.24#ibcon#read 6, iclass 13, count 0 2006.183.07:48:08.24#ibcon#end of sib2, iclass 13, count 0 2006.183.07:48:08.24#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:48:08.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:48:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:48:08.24#ibcon#*before write, iclass 13, count 0 2006.183.07:48:08.24#ibcon#enter sib2, iclass 13, count 0 2006.183.07:48:08.24#ibcon#flushed, iclass 13, count 0 2006.183.07:48:08.24#ibcon#about to write, iclass 13, count 0 2006.183.07:48:08.24#ibcon#wrote, iclass 13, count 0 2006.183.07:48:08.24#ibcon#about to read 3, iclass 13, count 0 2006.183.07:48:08.28#ibcon#read 3, iclass 13, count 0 2006.183.07:48:08.28#ibcon#about to read 4, iclass 13, count 0 2006.183.07:48:08.28#ibcon#read 4, iclass 13, count 0 2006.183.07:48:08.28#ibcon#about to read 5, iclass 13, count 0 2006.183.07:48:08.28#ibcon#read 5, iclass 13, count 0 2006.183.07:48:08.28#ibcon#about to read 6, iclass 13, count 0 2006.183.07:48:08.28#ibcon#read 6, iclass 13, count 0 2006.183.07:48:08.28#ibcon#end of sib2, iclass 13, count 0 2006.183.07:48:08.28#ibcon#*after write, iclass 13, count 0 2006.183.07:48:08.28#ibcon#*before return 0, iclass 13, count 0 2006.183.07:48:08.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:08.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:08.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:48:08.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:48:08.28$vc4f8/va=2,7 2006.183.07:48:08.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:48:08.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:48:08.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:08.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:08.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:08.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:08.34#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:48:08.34#ibcon#first serial, iclass 15, count 2 2006.183.07:48:08.34#ibcon#enter sib2, iclass 15, count 2 2006.183.07:48:08.34#ibcon#flushed, iclass 15, count 2 2006.183.07:48:08.34#ibcon#about to write, iclass 15, count 2 2006.183.07:48:08.34#ibcon#wrote, iclass 15, count 2 2006.183.07:48:08.34#ibcon#about to read 3, iclass 15, count 2 2006.183.07:48:08.36#ibcon#read 3, iclass 15, count 2 2006.183.07:48:08.36#ibcon#about to read 4, iclass 15, count 2 2006.183.07:48:08.36#ibcon#read 4, iclass 15, count 2 2006.183.07:48:08.36#ibcon#about to read 5, iclass 15, count 2 2006.183.07:48:08.36#ibcon#read 5, iclass 15, count 2 2006.183.07:48:08.36#ibcon#about to read 6, iclass 15, count 2 2006.183.07:48:08.36#ibcon#read 6, iclass 15, count 2 2006.183.07:48:08.36#ibcon#end of sib2, iclass 15, count 2 2006.183.07:48:08.36#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:48:08.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:48:08.36#ibcon#[25=AT02-07\r\n] 2006.183.07:48:08.36#ibcon#*before write, iclass 15, count 2 2006.183.07:48:08.36#ibcon#enter sib2, iclass 15, count 2 2006.183.07:48:08.36#ibcon#flushed, iclass 15, count 2 2006.183.07:48:08.36#ibcon#about to write, iclass 15, count 2 2006.183.07:48:08.36#ibcon#wrote, iclass 15, count 2 2006.183.07:48:08.36#ibcon#about to read 3, iclass 15, count 2 2006.183.07:48:08.39#ibcon#read 3, iclass 15, count 2 2006.183.07:48:08.39#ibcon#about to read 4, iclass 15, count 2 2006.183.07:48:08.39#ibcon#read 4, iclass 15, count 2 2006.183.07:48:08.39#ibcon#about to read 5, iclass 15, count 2 2006.183.07:48:08.39#ibcon#read 5, iclass 15, count 2 2006.183.07:48:08.39#ibcon#about to read 6, iclass 15, count 2 2006.183.07:48:08.39#ibcon#read 6, iclass 15, count 2 2006.183.07:48:08.39#ibcon#end of sib2, iclass 15, count 2 2006.183.07:48:08.39#ibcon#*after write, iclass 15, count 2 2006.183.07:48:08.39#ibcon#*before return 0, iclass 15, count 2 2006.183.07:48:08.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:08.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:08.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:48:08.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:08.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:08.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:08.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:08.52#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:48:08.52#ibcon#first serial, iclass 15, count 0 2006.183.07:48:08.52#ibcon#enter sib2, iclass 15, count 0 2006.183.07:48:08.52#ibcon#flushed, iclass 15, count 0 2006.183.07:48:08.52#ibcon#about to write, iclass 15, count 0 2006.183.07:48:08.52#ibcon#wrote, iclass 15, count 0 2006.183.07:48:08.52#ibcon#about to read 3, iclass 15, count 0 2006.183.07:48:08.53#ibcon#read 3, iclass 15, count 0 2006.183.07:48:08.53#ibcon#about to read 4, iclass 15, count 0 2006.183.07:48:08.53#ibcon#read 4, iclass 15, count 0 2006.183.07:48:08.53#ibcon#about to read 5, iclass 15, count 0 2006.183.07:48:08.53#ibcon#read 5, iclass 15, count 0 2006.183.07:48:08.53#ibcon#about to read 6, iclass 15, count 0 2006.183.07:48:08.53#ibcon#read 6, iclass 15, count 0 2006.183.07:48:08.53#ibcon#end of sib2, iclass 15, count 0 2006.183.07:48:08.53#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:48:08.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:48:08.53#ibcon#[25=USB\r\n] 2006.183.07:48:08.53#ibcon#*before write, iclass 15, count 0 2006.183.07:48:08.53#ibcon#enter sib2, iclass 15, count 0 2006.183.07:48:08.53#ibcon#flushed, iclass 15, count 0 2006.183.07:48:08.53#ibcon#about to write, iclass 15, count 0 2006.183.07:48:08.53#ibcon#wrote, iclass 15, count 0 2006.183.07:48:08.53#ibcon#about to read 3, iclass 15, count 0 2006.183.07:48:08.56#ibcon#read 3, iclass 15, count 0 2006.183.07:48:08.56#ibcon#about to read 4, iclass 15, count 0 2006.183.07:48:08.56#ibcon#read 4, iclass 15, count 0 2006.183.07:48:08.56#ibcon#about to read 5, iclass 15, count 0 2006.183.07:48:08.56#ibcon#read 5, iclass 15, count 0 2006.183.07:48:08.56#ibcon#about to read 6, iclass 15, count 0 2006.183.07:48:08.56#ibcon#read 6, iclass 15, count 0 2006.183.07:48:08.56#ibcon#end of sib2, iclass 15, count 0 2006.183.07:48:08.56#ibcon#*after write, iclass 15, count 0 2006.183.07:48:08.56#ibcon#*before return 0, iclass 15, count 0 2006.183.07:48:08.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:08.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:08.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:48:08.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:48:08.56$vc4f8/valo=3,672.99 2006.183.07:48:08.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:48:08.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:48:08.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:08.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:08.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:08.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:08.56#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:48:08.56#ibcon#first serial, iclass 17, count 0 2006.183.07:48:08.56#ibcon#enter sib2, iclass 17, count 0 2006.183.07:48:08.56#ibcon#flushed, iclass 17, count 0 2006.183.07:48:08.56#ibcon#about to write, iclass 17, count 0 2006.183.07:48:08.56#ibcon#wrote, iclass 17, count 0 2006.183.07:48:08.56#ibcon#about to read 3, iclass 17, count 0 2006.183.07:48:08.59#ibcon#read 3, iclass 17, count 0 2006.183.07:48:08.59#ibcon#about to read 4, iclass 17, count 0 2006.183.07:48:08.59#ibcon#read 4, iclass 17, count 0 2006.183.07:48:08.59#ibcon#about to read 5, iclass 17, count 0 2006.183.07:48:08.59#ibcon#read 5, iclass 17, count 0 2006.183.07:48:08.59#ibcon#about to read 6, iclass 17, count 0 2006.183.07:48:08.59#ibcon#read 6, iclass 17, count 0 2006.183.07:48:08.59#ibcon#end of sib2, iclass 17, count 0 2006.183.07:48:08.59#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:48:08.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:48:08.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:48:08.59#ibcon#*before write, iclass 17, count 0 2006.183.07:48:08.59#ibcon#enter sib2, iclass 17, count 0 2006.183.07:48:08.59#ibcon#flushed, iclass 17, count 0 2006.183.07:48:08.59#ibcon#about to write, iclass 17, count 0 2006.183.07:48:08.59#ibcon#wrote, iclass 17, count 0 2006.183.07:48:08.59#ibcon#about to read 3, iclass 17, count 0 2006.183.07:48:08.63#ibcon#read 3, iclass 17, count 0 2006.183.07:48:08.63#ibcon#about to read 4, iclass 17, count 0 2006.183.07:48:08.63#ibcon#read 4, iclass 17, count 0 2006.183.07:48:08.63#ibcon#about to read 5, iclass 17, count 0 2006.183.07:48:08.63#ibcon#read 5, iclass 17, count 0 2006.183.07:48:08.63#ibcon#about to read 6, iclass 17, count 0 2006.183.07:48:08.63#ibcon#read 6, iclass 17, count 0 2006.183.07:48:08.63#ibcon#end of sib2, iclass 17, count 0 2006.183.07:48:08.63#ibcon#*after write, iclass 17, count 0 2006.183.07:48:08.63#ibcon#*before return 0, iclass 17, count 0 2006.183.07:48:08.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:08.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:08.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:48:08.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:48:08.63$vc4f8/va=3,6 2006.183.07:48:08.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:48:08.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:48:08.63#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:08.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:08.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:08.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:08.68#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:48:08.68#ibcon#first serial, iclass 19, count 2 2006.183.07:48:08.68#ibcon#enter sib2, iclass 19, count 2 2006.183.07:48:08.68#ibcon#flushed, iclass 19, count 2 2006.183.07:48:08.68#ibcon#about to write, iclass 19, count 2 2006.183.07:48:08.68#ibcon#wrote, iclass 19, count 2 2006.183.07:48:08.68#ibcon#about to read 3, iclass 19, count 2 2006.183.07:48:08.70#ibcon#read 3, iclass 19, count 2 2006.183.07:48:08.70#ibcon#about to read 4, iclass 19, count 2 2006.183.07:48:08.70#ibcon#read 4, iclass 19, count 2 2006.183.07:48:08.70#ibcon#about to read 5, iclass 19, count 2 2006.183.07:48:08.70#ibcon#read 5, iclass 19, count 2 2006.183.07:48:08.70#ibcon#about to read 6, iclass 19, count 2 2006.183.07:48:08.70#ibcon#read 6, iclass 19, count 2 2006.183.07:48:08.70#ibcon#end of sib2, iclass 19, count 2 2006.183.07:48:08.70#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:48:08.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:48:08.70#ibcon#[25=AT03-06\r\n] 2006.183.07:48:08.70#ibcon#*before write, iclass 19, count 2 2006.183.07:48:08.70#ibcon#enter sib2, iclass 19, count 2 2006.183.07:48:08.70#ibcon#flushed, iclass 19, count 2 2006.183.07:48:08.70#ibcon#about to write, iclass 19, count 2 2006.183.07:48:08.70#ibcon#wrote, iclass 19, count 2 2006.183.07:48:08.70#ibcon#about to read 3, iclass 19, count 2 2006.183.07:48:08.73#ibcon#read 3, iclass 19, count 2 2006.183.07:48:08.73#ibcon#about to read 4, iclass 19, count 2 2006.183.07:48:08.73#ibcon#read 4, iclass 19, count 2 2006.183.07:48:08.73#ibcon#about to read 5, iclass 19, count 2 2006.183.07:48:08.73#ibcon#read 5, iclass 19, count 2 2006.183.07:48:08.73#ibcon#about to read 6, iclass 19, count 2 2006.183.07:48:08.73#ibcon#read 6, iclass 19, count 2 2006.183.07:48:08.73#ibcon#end of sib2, iclass 19, count 2 2006.183.07:48:08.73#ibcon#*after write, iclass 19, count 2 2006.183.07:48:08.73#ibcon#*before return 0, iclass 19, count 2 2006.183.07:48:08.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:08.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:08.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:48:08.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:08.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:08.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:08.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:08.85#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:48:08.85#ibcon#first serial, iclass 19, count 0 2006.183.07:48:08.85#ibcon#enter sib2, iclass 19, count 0 2006.183.07:48:08.85#ibcon#flushed, iclass 19, count 0 2006.183.07:48:08.85#ibcon#about to write, iclass 19, count 0 2006.183.07:48:08.85#ibcon#wrote, iclass 19, count 0 2006.183.07:48:08.85#ibcon#about to read 3, iclass 19, count 0 2006.183.07:48:08.87#ibcon#read 3, iclass 19, count 0 2006.183.07:48:08.87#ibcon#about to read 4, iclass 19, count 0 2006.183.07:48:08.87#ibcon#read 4, iclass 19, count 0 2006.183.07:48:08.87#ibcon#about to read 5, iclass 19, count 0 2006.183.07:48:08.87#ibcon#read 5, iclass 19, count 0 2006.183.07:48:08.87#ibcon#about to read 6, iclass 19, count 0 2006.183.07:48:08.87#ibcon#read 6, iclass 19, count 0 2006.183.07:48:08.87#ibcon#end of sib2, iclass 19, count 0 2006.183.07:48:08.87#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:48:08.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:48:08.87#ibcon#[25=USB\r\n] 2006.183.07:48:08.87#ibcon#*before write, iclass 19, count 0 2006.183.07:48:08.87#ibcon#enter sib2, iclass 19, count 0 2006.183.07:48:08.87#ibcon#flushed, iclass 19, count 0 2006.183.07:48:08.87#ibcon#about to write, iclass 19, count 0 2006.183.07:48:08.87#ibcon#wrote, iclass 19, count 0 2006.183.07:48:08.87#ibcon#about to read 3, iclass 19, count 0 2006.183.07:48:08.90#ibcon#read 3, iclass 19, count 0 2006.183.07:48:08.90#ibcon#about to read 4, iclass 19, count 0 2006.183.07:48:08.90#ibcon#read 4, iclass 19, count 0 2006.183.07:48:08.90#ibcon#about to read 5, iclass 19, count 0 2006.183.07:48:08.90#ibcon#read 5, iclass 19, count 0 2006.183.07:48:08.90#ibcon#about to read 6, iclass 19, count 0 2006.183.07:48:08.90#ibcon#read 6, iclass 19, count 0 2006.183.07:48:08.90#ibcon#end of sib2, iclass 19, count 0 2006.183.07:48:08.90#ibcon#*after write, iclass 19, count 0 2006.183.07:48:08.90#ibcon#*before return 0, iclass 19, count 0 2006.183.07:48:08.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:08.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:08.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:48:08.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:48:08.90$vc4f8/valo=4,832.99 2006.183.07:48:08.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:48:08.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:48:08.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:08.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:08.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:08.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:08.90#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:48:08.90#ibcon#first serial, iclass 21, count 0 2006.183.07:48:08.90#ibcon#enter sib2, iclass 21, count 0 2006.183.07:48:08.90#ibcon#flushed, iclass 21, count 0 2006.183.07:48:08.90#ibcon#about to write, iclass 21, count 0 2006.183.07:48:08.90#ibcon#wrote, iclass 21, count 0 2006.183.07:48:08.90#ibcon#about to read 3, iclass 21, count 0 2006.183.07:48:08.92#ibcon#read 3, iclass 21, count 0 2006.183.07:48:08.92#ibcon#about to read 4, iclass 21, count 0 2006.183.07:48:08.92#ibcon#read 4, iclass 21, count 0 2006.183.07:48:08.92#ibcon#about to read 5, iclass 21, count 0 2006.183.07:48:08.92#ibcon#read 5, iclass 21, count 0 2006.183.07:48:08.92#ibcon#about to read 6, iclass 21, count 0 2006.183.07:48:08.92#ibcon#read 6, iclass 21, count 0 2006.183.07:48:08.92#ibcon#end of sib2, iclass 21, count 0 2006.183.07:48:08.92#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:48:08.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:48:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:48:08.92#ibcon#*before write, iclass 21, count 0 2006.183.07:48:08.92#ibcon#enter sib2, iclass 21, count 0 2006.183.07:48:08.92#ibcon#flushed, iclass 21, count 0 2006.183.07:48:08.92#ibcon#about to write, iclass 21, count 0 2006.183.07:48:08.92#ibcon#wrote, iclass 21, count 0 2006.183.07:48:08.92#ibcon#about to read 3, iclass 21, count 0 2006.183.07:48:08.96#ibcon#read 3, iclass 21, count 0 2006.183.07:48:08.96#ibcon#about to read 4, iclass 21, count 0 2006.183.07:48:08.96#ibcon#read 4, iclass 21, count 0 2006.183.07:48:08.96#ibcon#about to read 5, iclass 21, count 0 2006.183.07:48:08.96#ibcon#read 5, iclass 21, count 0 2006.183.07:48:08.96#ibcon#about to read 6, iclass 21, count 0 2006.183.07:48:08.96#ibcon#read 6, iclass 21, count 0 2006.183.07:48:08.96#ibcon#end of sib2, iclass 21, count 0 2006.183.07:48:08.96#ibcon#*after write, iclass 21, count 0 2006.183.07:48:08.96#ibcon#*before return 0, iclass 21, count 0 2006.183.07:48:08.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:08.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:08.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:48:08.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:48:08.96$vc4f8/va=4,7 2006.183.07:48:08.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:48:08.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:48:08.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:08.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:09.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:09.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:09.02#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:48:09.02#ibcon#first serial, iclass 23, count 2 2006.183.07:48:09.02#ibcon#enter sib2, iclass 23, count 2 2006.183.07:48:09.02#ibcon#flushed, iclass 23, count 2 2006.183.07:48:09.02#ibcon#about to write, iclass 23, count 2 2006.183.07:48:09.02#ibcon#wrote, iclass 23, count 2 2006.183.07:48:09.02#ibcon#about to read 3, iclass 23, count 2 2006.183.07:48:09.04#ibcon#read 3, iclass 23, count 2 2006.183.07:48:09.04#ibcon#about to read 4, iclass 23, count 2 2006.183.07:48:09.04#ibcon#read 4, iclass 23, count 2 2006.183.07:48:09.04#ibcon#about to read 5, iclass 23, count 2 2006.183.07:48:09.04#ibcon#read 5, iclass 23, count 2 2006.183.07:48:09.04#ibcon#about to read 6, iclass 23, count 2 2006.183.07:48:09.04#ibcon#read 6, iclass 23, count 2 2006.183.07:48:09.04#ibcon#end of sib2, iclass 23, count 2 2006.183.07:48:09.04#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:48:09.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:48:09.04#ibcon#[25=AT04-07\r\n] 2006.183.07:48:09.04#ibcon#*before write, iclass 23, count 2 2006.183.07:48:09.04#ibcon#enter sib2, iclass 23, count 2 2006.183.07:48:09.04#ibcon#flushed, iclass 23, count 2 2006.183.07:48:09.04#ibcon#about to write, iclass 23, count 2 2006.183.07:48:09.04#ibcon#wrote, iclass 23, count 2 2006.183.07:48:09.04#ibcon#about to read 3, iclass 23, count 2 2006.183.07:48:09.07#ibcon#read 3, iclass 23, count 2 2006.183.07:48:09.07#ibcon#about to read 4, iclass 23, count 2 2006.183.07:48:09.07#ibcon#read 4, iclass 23, count 2 2006.183.07:48:09.07#ibcon#about to read 5, iclass 23, count 2 2006.183.07:48:09.07#ibcon#read 5, iclass 23, count 2 2006.183.07:48:09.07#ibcon#about to read 6, iclass 23, count 2 2006.183.07:48:09.07#ibcon#read 6, iclass 23, count 2 2006.183.07:48:09.07#ibcon#end of sib2, iclass 23, count 2 2006.183.07:48:09.07#ibcon#*after write, iclass 23, count 2 2006.183.07:48:09.07#ibcon#*before return 0, iclass 23, count 2 2006.183.07:48:09.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:09.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:09.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:48:09.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:09.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:09.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:09.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:09.19#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:48:09.19#ibcon#first serial, iclass 23, count 0 2006.183.07:48:09.19#ibcon#enter sib2, iclass 23, count 0 2006.183.07:48:09.19#ibcon#flushed, iclass 23, count 0 2006.183.07:48:09.19#ibcon#about to write, iclass 23, count 0 2006.183.07:48:09.19#ibcon#wrote, iclass 23, count 0 2006.183.07:48:09.19#ibcon#about to read 3, iclass 23, count 0 2006.183.07:48:09.21#ibcon#read 3, iclass 23, count 0 2006.183.07:48:09.21#ibcon#about to read 4, iclass 23, count 0 2006.183.07:48:09.21#ibcon#read 4, iclass 23, count 0 2006.183.07:48:09.21#ibcon#about to read 5, iclass 23, count 0 2006.183.07:48:09.21#ibcon#read 5, iclass 23, count 0 2006.183.07:48:09.21#ibcon#about to read 6, iclass 23, count 0 2006.183.07:48:09.21#ibcon#read 6, iclass 23, count 0 2006.183.07:48:09.21#ibcon#end of sib2, iclass 23, count 0 2006.183.07:48:09.21#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:48:09.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:48:09.21#ibcon#[25=USB\r\n] 2006.183.07:48:09.21#ibcon#*before write, iclass 23, count 0 2006.183.07:48:09.21#ibcon#enter sib2, iclass 23, count 0 2006.183.07:48:09.21#ibcon#flushed, iclass 23, count 0 2006.183.07:48:09.21#ibcon#about to write, iclass 23, count 0 2006.183.07:48:09.21#ibcon#wrote, iclass 23, count 0 2006.183.07:48:09.21#ibcon#about to read 3, iclass 23, count 0 2006.183.07:48:09.24#ibcon#read 3, iclass 23, count 0 2006.183.07:48:09.24#ibcon#about to read 4, iclass 23, count 0 2006.183.07:48:09.24#ibcon#read 4, iclass 23, count 0 2006.183.07:48:09.24#ibcon#about to read 5, iclass 23, count 0 2006.183.07:48:09.24#ibcon#read 5, iclass 23, count 0 2006.183.07:48:09.24#ibcon#about to read 6, iclass 23, count 0 2006.183.07:48:09.24#ibcon#read 6, iclass 23, count 0 2006.183.07:48:09.24#ibcon#end of sib2, iclass 23, count 0 2006.183.07:48:09.24#ibcon#*after write, iclass 23, count 0 2006.183.07:48:09.24#ibcon#*before return 0, iclass 23, count 0 2006.183.07:48:09.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:09.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:09.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:48:09.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:48:09.24$vc4f8/valo=5,652.99 2006.183.07:48:09.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:48:09.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:48:09.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:09.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:09.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:09.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:09.24#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:48:09.24#ibcon#first serial, iclass 25, count 0 2006.183.07:48:09.24#ibcon#enter sib2, iclass 25, count 0 2006.183.07:48:09.24#ibcon#flushed, iclass 25, count 0 2006.183.07:48:09.24#ibcon#about to write, iclass 25, count 0 2006.183.07:48:09.24#ibcon#wrote, iclass 25, count 0 2006.183.07:48:09.24#ibcon#about to read 3, iclass 25, count 0 2006.183.07:48:09.26#ibcon#read 3, iclass 25, count 0 2006.183.07:48:09.26#ibcon#about to read 4, iclass 25, count 0 2006.183.07:48:09.26#ibcon#read 4, iclass 25, count 0 2006.183.07:48:09.26#ibcon#about to read 5, iclass 25, count 0 2006.183.07:48:09.26#ibcon#read 5, iclass 25, count 0 2006.183.07:48:09.26#ibcon#about to read 6, iclass 25, count 0 2006.183.07:48:09.26#ibcon#read 6, iclass 25, count 0 2006.183.07:48:09.26#ibcon#end of sib2, iclass 25, count 0 2006.183.07:48:09.26#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:48:09.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:48:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:48:09.26#ibcon#*before write, iclass 25, count 0 2006.183.07:48:09.26#ibcon#enter sib2, iclass 25, count 0 2006.183.07:48:09.26#ibcon#flushed, iclass 25, count 0 2006.183.07:48:09.26#ibcon#about to write, iclass 25, count 0 2006.183.07:48:09.26#ibcon#wrote, iclass 25, count 0 2006.183.07:48:09.26#ibcon#about to read 3, iclass 25, count 0 2006.183.07:48:09.30#ibcon#read 3, iclass 25, count 0 2006.183.07:48:09.30#ibcon#about to read 4, iclass 25, count 0 2006.183.07:48:09.30#ibcon#read 4, iclass 25, count 0 2006.183.07:48:09.30#ibcon#about to read 5, iclass 25, count 0 2006.183.07:48:09.30#ibcon#read 5, iclass 25, count 0 2006.183.07:48:09.30#ibcon#about to read 6, iclass 25, count 0 2006.183.07:48:09.30#ibcon#read 6, iclass 25, count 0 2006.183.07:48:09.30#ibcon#end of sib2, iclass 25, count 0 2006.183.07:48:09.30#ibcon#*after write, iclass 25, count 0 2006.183.07:48:09.30#ibcon#*before return 0, iclass 25, count 0 2006.183.07:48:09.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:09.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:09.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:48:09.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:48:09.30$vc4f8/va=5,7 2006.183.07:48:09.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.07:48:09.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.07:48:09.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:09.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:09.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:09.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:09.36#ibcon#enter wrdev, iclass 27, count 2 2006.183.07:48:09.36#ibcon#first serial, iclass 27, count 2 2006.183.07:48:09.36#ibcon#enter sib2, iclass 27, count 2 2006.183.07:48:09.36#ibcon#flushed, iclass 27, count 2 2006.183.07:48:09.36#ibcon#about to write, iclass 27, count 2 2006.183.07:48:09.36#ibcon#wrote, iclass 27, count 2 2006.183.07:48:09.36#ibcon#about to read 3, iclass 27, count 2 2006.183.07:48:09.38#ibcon#read 3, iclass 27, count 2 2006.183.07:48:09.38#ibcon#about to read 4, iclass 27, count 2 2006.183.07:48:09.38#ibcon#read 4, iclass 27, count 2 2006.183.07:48:09.38#ibcon#about to read 5, iclass 27, count 2 2006.183.07:48:09.38#ibcon#read 5, iclass 27, count 2 2006.183.07:48:09.38#ibcon#about to read 6, iclass 27, count 2 2006.183.07:48:09.38#ibcon#read 6, iclass 27, count 2 2006.183.07:48:09.38#ibcon#end of sib2, iclass 27, count 2 2006.183.07:48:09.38#ibcon#*mode == 0, iclass 27, count 2 2006.183.07:48:09.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.07:48:09.38#ibcon#[25=AT05-07\r\n] 2006.183.07:48:09.38#ibcon#*before write, iclass 27, count 2 2006.183.07:48:09.38#ibcon#enter sib2, iclass 27, count 2 2006.183.07:48:09.38#ibcon#flushed, iclass 27, count 2 2006.183.07:48:09.38#ibcon#about to write, iclass 27, count 2 2006.183.07:48:09.38#ibcon#wrote, iclass 27, count 2 2006.183.07:48:09.38#ibcon#about to read 3, iclass 27, count 2 2006.183.07:48:09.41#ibcon#read 3, iclass 27, count 2 2006.183.07:48:09.41#ibcon#about to read 4, iclass 27, count 2 2006.183.07:48:09.41#ibcon#read 4, iclass 27, count 2 2006.183.07:48:09.41#ibcon#about to read 5, iclass 27, count 2 2006.183.07:48:09.41#ibcon#read 5, iclass 27, count 2 2006.183.07:48:09.41#ibcon#about to read 6, iclass 27, count 2 2006.183.07:48:09.41#ibcon#read 6, iclass 27, count 2 2006.183.07:48:09.41#ibcon#end of sib2, iclass 27, count 2 2006.183.07:48:09.41#ibcon#*after write, iclass 27, count 2 2006.183.07:48:09.41#ibcon#*before return 0, iclass 27, count 2 2006.183.07:48:09.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:09.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:09.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.07:48:09.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:09.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:09.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:09.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:09.53#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:48:09.53#ibcon#first serial, iclass 27, count 0 2006.183.07:48:09.53#ibcon#enter sib2, iclass 27, count 0 2006.183.07:48:09.53#ibcon#flushed, iclass 27, count 0 2006.183.07:48:09.53#ibcon#about to write, iclass 27, count 0 2006.183.07:48:09.53#ibcon#wrote, iclass 27, count 0 2006.183.07:48:09.53#ibcon#about to read 3, iclass 27, count 0 2006.183.07:48:09.55#ibcon#read 3, iclass 27, count 0 2006.183.07:48:09.55#ibcon#about to read 4, iclass 27, count 0 2006.183.07:48:09.55#ibcon#read 4, iclass 27, count 0 2006.183.07:48:09.55#ibcon#about to read 5, iclass 27, count 0 2006.183.07:48:09.55#ibcon#read 5, iclass 27, count 0 2006.183.07:48:09.55#ibcon#about to read 6, iclass 27, count 0 2006.183.07:48:09.55#ibcon#read 6, iclass 27, count 0 2006.183.07:48:09.55#ibcon#end of sib2, iclass 27, count 0 2006.183.07:48:09.55#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:48:09.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:48:09.55#ibcon#[25=USB\r\n] 2006.183.07:48:09.55#ibcon#*before write, iclass 27, count 0 2006.183.07:48:09.55#ibcon#enter sib2, iclass 27, count 0 2006.183.07:48:09.55#ibcon#flushed, iclass 27, count 0 2006.183.07:48:09.55#ibcon#about to write, iclass 27, count 0 2006.183.07:48:09.55#ibcon#wrote, iclass 27, count 0 2006.183.07:48:09.55#ibcon#about to read 3, iclass 27, count 0 2006.183.07:48:09.58#ibcon#read 3, iclass 27, count 0 2006.183.07:48:09.58#ibcon#about to read 4, iclass 27, count 0 2006.183.07:48:09.58#ibcon#read 4, iclass 27, count 0 2006.183.07:48:09.58#ibcon#about to read 5, iclass 27, count 0 2006.183.07:48:09.58#ibcon#read 5, iclass 27, count 0 2006.183.07:48:09.58#ibcon#about to read 6, iclass 27, count 0 2006.183.07:48:09.58#ibcon#read 6, iclass 27, count 0 2006.183.07:48:09.58#ibcon#end of sib2, iclass 27, count 0 2006.183.07:48:09.58#ibcon#*after write, iclass 27, count 0 2006.183.07:48:09.58#ibcon#*before return 0, iclass 27, count 0 2006.183.07:48:09.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:09.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:09.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:48:09.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:48:09.58$vc4f8/valo=6,772.99 2006.183.07:48:09.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.07:48:09.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.07:48:09.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:09.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:09.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:09.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:09.58#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:48:09.58#ibcon#first serial, iclass 29, count 0 2006.183.07:48:09.58#ibcon#enter sib2, iclass 29, count 0 2006.183.07:48:09.58#ibcon#flushed, iclass 29, count 0 2006.183.07:48:09.58#ibcon#about to write, iclass 29, count 0 2006.183.07:48:09.58#ibcon#wrote, iclass 29, count 0 2006.183.07:48:09.58#ibcon#about to read 3, iclass 29, count 0 2006.183.07:48:09.60#ibcon#read 3, iclass 29, count 0 2006.183.07:48:09.60#ibcon#about to read 4, iclass 29, count 0 2006.183.07:48:09.60#ibcon#read 4, iclass 29, count 0 2006.183.07:48:09.60#ibcon#about to read 5, iclass 29, count 0 2006.183.07:48:09.60#ibcon#read 5, iclass 29, count 0 2006.183.07:48:09.60#ibcon#about to read 6, iclass 29, count 0 2006.183.07:48:09.60#ibcon#read 6, iclass 29, count 0 2006.183.07:48:09.60#ibcon#end of sib2, iclass 29, count 0 2006.183.07:48:09.60#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:48:09.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:48:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:48:09.60#ibcon#*before write, iclass 29, count 0 2006.183.07:48:09.60#ibcon#enter sib2, iclass 29, count 0 2006.183.07:48:09.60#ibcon#flushed, iclass 29, count 0 2006.183.07:48:09.60#ibcon#about to write, iclass 29, count 0 2006.183.07:48:09.60#ibcon#wrote, iclass 29, count 0 2006.183.07:48:09.60#ibcon#about to read 3, iclass 29, count 0 2006.183.07:48:09.64#ibcon#read 3, iclass 29, count 0 2006.183.07:48:09.64#ibcon#about to read 4, iclass 29, count 0 2006.183.07:48:09.64#ibcon#read 4, iclass 29, count 0 2006.183.07:48:09.64#ibcon#about to read 5, iclass 29, count 0 2006.183.07:48:09.64#ibcon#read 5, iclass 29, count 0 2006.183.07:48:09.64#ibcon#about to read 6, iclass 29, count 0 2006.183.07:48:09.64#ibcon#read 6, iclass 29, count 0 2006.183.07:48:09.64#ibcon#end of sib2, iclass 29, count 0 2006.183.07:48:09.64#ibcon#*after write, iclass 29, count 0 2006.183.07:48:09.64#ibcon#*before return 0, iclass 29, count 0 2006.183.07:48:09.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:09.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:09.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:48:09.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:48:09.64$vc4f8/va=6,6 2006.183.07:48:09.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.07:48:09.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.07:48:09.64#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:09.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:48:09.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:48:09.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:48:09.70#ibcon#enter wrdev, iclass 31, count 2 2006.183.07:48:09.70#ibcon#first serial, iclass 31, count 2 2006.183.07:48:09.70#ibcon#enter sib2, iclass 31, count 2 2006.183.07:48:09.70#ibcon#flushed, iclass 31, count 2 2006.183.07:48:09.70#ibcon#about to write, iclass 31, count 2 2006.183.07:48:09.70#ibcon#wrote, iclass 31, count 2 2006.183.07:48:09.70#ibcon#about to read 3, iclass 31, count 2 2006.183.07:48:09.72#ibcon#read 3, iclass 31, count 2 2006.183.07:48:09.72#ibcon#about to read 4, iclass 31, count 2 2006.183.07:48:09.72#ibcon#read 4, iclass 31, count 2 2006.183.07:48:09.72#ibcon#about to read 5, iclass 31, count 2 2006.183.07:48:09.72#ibcon#read 5, iclass 31, count 2 2006.183.07:48:09.72#ibcon#about to read 6, iclass 31, count 2 2006.183.07:48:09.72#ibcon#read 6, iclass 31, count 2 2006.183.07:48:09.72#ibcon#end of sib2, iclass 31, count 2 2006.183.07:48:09.72#ibcon#*mode == 0, iclass 31, count 2 2006.183.07:48:09.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.07:48:09.72#ibcon#[25=AT06-06\r\n] 2006.183.07:48:09.72#ibcon#*before write, iclass 31, count 2 2006.183.07:48:09.72#ibcon#enter sib2, iclass 31, count 2 2006.183.07:48:09.72#ibcon#flushed, iclass 31, count 2 2006.183.07:48:09.72#ibcon#about to write, iclass 31, count 2 2006.183.07:48:09.72#ibcon#wrote, iclass 31, count 2 2006.183.07:48:09.72#ibcon#about to read 3, iclass 31, count 2 2006.183.07:48:09.75#ibcon#read 3, iclass 31, count 2 2006.183.07:48:09.75#ibcon#about to read 4, iclass 31, count 2 2006.183.07:48:09.75#ibcon#read 4, iclass 31, count 2 2006.183.07:48:09.75#ibcon#about to read 5, iclass 31, count 2 2006.183.07:48:09.75#ibcon#read 5, iclass 31, count 2 2006.183.07:48:09.75#ibcon#about to read 6, iclass 31, count 2 2006.183.07:48:09.75#ibcon#read 6, iclass 31, count 2 2006.183.07:48:09.75#ibcon#end of sib2, iclass 31, count 2 2006.183.07:48:09.75#ibcon#*after write, iclass 31, count 2 2006.183.07:48:09.75#ibcon#*before return 0, iclass 31, count 2 2006.183.07:48:09.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:48:09.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:48:09.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.07:48:09.75#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:09.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:48:09.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:48:09.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:48:09.87#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:48:09.87#ibcon#first serial, iclass 31, count 0 2006.183.07:48:09.87#ibcon#enter sib2, iclass 31, count 0 2006.183.07:48:09.87#ibcon#flushed, iclass 31, count 0 2006.183.07:48:09.87#ibcon#about to write, iclass 31, count 0 2006.183.07:48:09.87#ibcon#wrote, iclass 31, count 0 2006.183.07:48:09.87#ibcon#about to read 3, iclass 31, count 0 2006.183.07:48:09.89#ibcon#read 3, iclass 31, count 0 2006.183.07:48:09.89#ibcon#about to read 4, iclass 31, count 0 2006.183.07:48:09.89#ibcon#read 4, iclass 31, count 0 2006.183.07:48:09.89#ibcon#about to read 5, iclass 31, count 0 2006.183.07:48:09.89#ibcon#read 5, iclass 31, count 0 2006.183.07:48:09.89#ibcon#about to read 6, iclass 31, count 0 2006.183.07:48:09.89#ibcon#read 6, iclass 31, count 0 2006.183.07:48:09.89#ibcon#end of sib2, iclass 31, count 0 2006.183.07:48:09.89#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:48:09.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:48:09.89#ibcon#[25=USB\r\n] 2006.183.07:48:09.89#ibcon#*before write, iclass 31, count 0 2006.183.07:48:09.89#ibcon#enter sib2, iclass 31, count 0 2006.183.07:48:09.89#ibcon#flushed, iclass 31, count 0 2006.183.07:48:09.89#ibcon#about to write, iclass 31, count 0 2006.183.07:48:09.89#ibcon#wrote, iclass 31, count 0 2006.183.07:48:09.89#ibcon#about to read 3, iclass 31, count 0 2006.183.07:48:09.92#ibcon#read 3, iclass 31, count 0 2006.183.07:48:09.92#ibcon#about to read 4, iclass 31, count 0 2006.183.07:48:09.92#ibcon#read 4, iclass 31, count 0 2006.183.07:48:09.92#ibcon#about to read 5, iclass 31, count 0 2006.183.07:48:09.92#ibcon#read 5, iclass 31, count 0 2006.183.07:48:09.92#ibcon#about to read 6, iclass 31, count 0 2006.183.07:48:09.92#ibcon#read 6, iclass 31, count 0 2006.183.07:48:09.92#ibcon#end of sib2, iclass 31, count 0 2006.183.07:48:09.92#ibcon#*after write, iclass 31, count 0 2006.183.07:48:09.92#ibcon#*before return 0, iclass 31, count 0 2006.183.07:48:09.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:48:09.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:48:09.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:48:09.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:48:09.92$vc4f8/valo=7,832.99 2006.183.07:48:09.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.07:48:09.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.07:48:09.92#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:09.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:48:09.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:48:09.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:48:09.92#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:48:09.92#ibcon#first serial, iclass 33, count 0 2006.183.07:48:09.92#ibcon#enter sib2, iclass 33, count 0 2006.183.07:48:09.92#ibcon#flushed, iclass 33, count 0 2006.183.07:48:09.92#ibcon#about to write, iclass 33, count 0 2006.183.07:48:09.92#ibcon#wrote, iclass 33, count 0 2006.183.07:48:09.92#ibcon#about to read 3, iclass 33, count 0 2006.183.07:48:09.94#ibcon#read 3, iclass 33, count 0 2006.183.07:48:09.94#ibcon#about to read 4, iclass 33, count 0 2006.183.07:48:09.94#ibcon#read 4, iclass 33, count 0 2006.183.07:48:09.94#ibcon#about to read 5, iclass 33, count 0 2006.183.07:48:09.94#ibcon#read 5, iclass 33, count 0 2006.183.07:48:09.94#ibcon#about to read 6, iclass 33, count 0 2006.183.07:48:09.94#ibcon#read 6, iclass 33, count 0 2006.183.07:48:09.94#ibcon#end of sib2, iclass 33, count 0 2006.183.07:48:09.94#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:48:09.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:48:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:48:09.94#ibcon#*before write, iclass 33, count 0 2006.183.07:48:09.94#ibcon#enter sib2, iclass 33, count 0 2006.183.07:48:09.94#ibcon#flushed, iclass 33, count 0 2006.183.07:48:09.94#ibcon#about to write, iclass 33, count 0 2006.183.07:48:09.94#ibcon#wrote, iclass 33, count 0 2006.183.07:48:09.94#ibcon#about to read 3, iclass 33, count 0 2006.183.07:48:09.98#ibcon#read 3, iclass 33, count 0 2006.183.07:48:09.98#ibcon#about to read 4, iclass 33, count 0 2006.183.07:48:09.98#ibcon#read 4, iclass 33, count 0 2006.183.07:48:09.98#ibcon#about to read 5, iclass 33, count 0 2006.183.07:48:09.98#ibcon#read 5, iclass 33, count 0 2006.183.07:48:09.98#ibcon#about to read 6, iclass 33, count 0 2006.183.07:48:09.98#ibcon#read 6, iclass 33, count 0 2006.183.07:48:09.98#ibcon#end of sib2, iclass 33, count 0 2006.183.07:48:09.98#ibcon#*after write, iclass 33, count 0 2006.183.07:48:09.98#ibcon#*before return 0, iclass 33, count 0 2006.183.07:48:09.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:48:09.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:48:09.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:48:09.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:48:09.98$vc4f8/va=7,6 2006.183.07:48:09.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.183.07:48:09.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.183.07:48:09.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:09.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:48:10.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:48:10.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:48:10.04#ibcon#enter wrdev, iclass 35, count 2 2006.183.07:48:10.04#ibcon#first serial, iclass 35, count 2 2006.183.07:48:10.04#ibcon#enter sib2, iclass 35, count 2 2006.183.07:48:10.04#ibcon#flushed, iclass 35, count 2 2006.183.07:48:10.04#ibcon#about to write, iclass 35, count 2 2006.183.07:48:10.04#ibcon#wrote, iclass 35, count 2 2006.183.07:48:10.04#ibcon#about to read 3, iclass 35, count 2 2006.183.07:48:10.06#ibcon#read 3, iclass 35, count 2 2006.183.07:48:10.06#ibcon#about to read 4, iclass 35, count 2 2006.183.07:48:10.06#ibcon#read 4, iclass 35, count 2 2006.183.07:48:10.06#ibcon#about to read 5, iclass 35, count 2 2006.183.07:48:10.06#ibcon#read 5, iclass 35, count 2 2006.183.07:48:10.06#ibcon#about to read 6, iclass 35, count 2 2006.183.07:48:10.06#ibcon#read 6, iclass 35, count 2 2006.183.07:48:10.06#ibcon#end of sib2, iclass 35, count 2 2006.183.07:48:10.06#ibcon#*mode == 0, iclass 35, count 2 2006.183.07:48:10.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.183.07:48:10.06#ibcon#[25=AT07-06\r\n] 2006.183.07:48:10.06#ibcon#*before write, iclass 35, count 2 2006.183.07:48:10.06#ibcon#enter sib2, iclass 35, count 2 2006.183.07:48:10.06#ibcon#flushed, iclass 35, count 2 2006.183.07:48:10.06#ibcon#about to write, iclass 35, count 2 2006.183.07:48:10.06#ibcon#wrote, iclass 35, count 2 2006.183.07:48:10.06#ibcon#about to read 3, iclass 35, count 2 2006.183.07:48:10.09#ibcon#read 3, iclass 35, count 2 2006.183.07:48:10.09#ibcon#about to read 4, iclass 35, count 2 2006.183.07:48:10.09#ibcon#read 4, iclass 35, count 2 2006.183.07:48:10.09#ibcon#about to read 5, iclass 35, count 2 2006.183.07:48:10.09#ibcon#read 5, iclass 35, count 2 2006.183.07:48:10.09#ibcon#about to read 6, iclass 35, count 2 2006.183.07:48:10.09#ibcon#read 6, iclass 35, count 2 2006.183.07:48:10.09#ibcon#end of sib2, iclass 35, count 2 2006.183.07:48:10.09#ibcon#*after write, iclass 35, count 2 2006.183.07:48:10.09#ibcon#*before return 0, iclass 35, count 2 2006.183.07:48:10.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:48:10.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:48:10.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.183.07:48:10.09#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:10.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:48:10.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:48:10.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:48:10.21#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:48:10.21#ibcon#first serial, iclass 35, count 0 2006.183.07:48:10.21#ibcon#enter sib2, iclass 35, count 0 2006.183.07:48:10.21#ibcon#flushed, iclass 35, count 0 2006.183.07:48:10.21#ibcon#about to write, iclass 35, count 0 2006.183.07:48:10.21#ibcon#wrote, iclass 35, count 0 2006.183.07:48:10.21#ibcon#about to read 3, iclass 35, count 0 2006.183.07:48:10.23#ibcon#read 3, iclass 35, count 0 2006.183.07:48:10.23#ibcon#about to read 4, iclass 35, count 0 2006.183.07:48:10.23#ibcon#read 4, iclass 35, count 0 2006.183.07:48:10.23#ibcon#about to read 5, iclass 35, count 0 2006.183.07:48:10.23#ibcon#read 5, iclass 35, count 0 2006.183.07:48:10.23#ibcon#about to read 6, iclass 35, count 0 2006.183.07:48:10.23#ibcon#read 6, iclass 35, count 0 2006.183.07:48:10.23#ibcon#end of sib2, iclass 35, count 0 2006.183.07:48:10.23#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:48:10.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:48:10.23#ibcon#[25=USB\r\n] 2006.183.07:48:10.23#ibcon#*before write, iclass 35, count 0 2006.183.07:48:10.23#ibcon#enter sib2, iclass 35, count 0 2006.183.07:48:10.23#ibcon#flushed, iclass 35, count 0 2006.183.07:48:10.23#ibcon#about to write, iclass 35, count 0 2006.183.07:48:10.23#ibcon#wrote, iclass 35, count 0 2006.183.07:48:10.23#ibcon#about to read 3, iclass 35, count 0 2006.183.07:48:10.26#ibcon#read 3, iclass 35, count 0 2006.183.07:48:10.26#ibcon#about to read 4, iclass 35, count 0 2006.183.07:48:10.26#ibcon#read 4, iclass 35, count 0 2006.183.07:48:10.26#ibcon#about to read 5, iclass 35, count 0 2006.183.07:48:10.26#ibcon#read 5, iclass 35, count 0 2006.183.07:48:10.26#ibcon#about to read 6, iclass 35, count 0 2006.183.07:48:10.26#ibcon#read 6, iclass 35, count 0 2006.183.07:48:10.26#ibcon#end of sib2, iclass 35, count 0 2006.183.07:48:10.26#ibcon#*after write, iclass 35, count 0 2006.183.07:48:10.26#ibcon#*before return 0, iclass 35, count 0 2006.183.07:48:10.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:48:10.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:48:10.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:48:10.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:48:10.26$vc4f8/valo=8,852.99 2006.183.07:48:10.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.07:48:10.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.07:48:10.26#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:10.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:48:10.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:48:10.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:48:10.26#ibcon#enter wrdev, iclass 37, count 0 2006.183.07:48:10.26#ibcon#first serial, iclass 37, count 0 2006.183.07:48:10.26#ibcon#enter sib2, iclass 37, count 0 2006.183.07:48:10.26#ibcon#flushed, iclass 37, count 0 2006.183.07:48:10.26#ibcon#about to write, iclass 37, count 0 2006.183.07:48:10.26#ibcon#wrote, iclass 37, count 0 2006.183.07:48:10.26#ibcon#about to read 3, iclass 37, count 0 2006.183.07:48:10.28#ibcon#read 3, iclass 37, count 0 2006.183.07:48:10.28#ibcon#about to read 4, iclass 37, count 0 2006.183.07:48:10.28#ibcon#read 4, iclass 37, count 0 2006.183.07:48:10.28#ibcon#about to read 5, iclass 37, count 0 2006.183.07:48:10.28#ibcon#read 5, iclass 37, count 0 2006.183.07:48:10.28#ibcon#about to read 6, iclass 37, count 0 2006.183.07:48:10.28#ibcon#read 6, iclass 37, count 0 2006.183.07:48:10.28#ibcon#end of sib2, iclass 37, count 0 2006.183.07:48:10.28#ibcon#*mode == 0, iclass 37, count 0 2006.183.07:48:10.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.07:48:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:48:10.28#ibcon#*before write, iclass 37, count 0 2006.183.07:48:10.28#ibcon#enter sib2, iclass 37, count 0 2006.183.07:48:10.28#ibcon#flushed, iclass 37, count 0 2006.183.07:48:10.28#ibcon#about to write, iclass 37, count 0 2006.183.07:48:10.28#ibcon#wrote, iclass 37, count 0 2006.183.07:48:10.28#ibcon#about to read 3, iclass 37, count 0 2006.183.07:48:10.32#ibcon#read 3, iclass 37, count 0 2006.183.07:48:10.32#ibcon#about to read 4, iclass 37, count 0 2006.183.07:48:10.32#ibcon#read 4, iclass 37, count 0 2006.183.07:48:10.32#ibcon#about to read 5, iclass 37, count 0 2006.183.07:48:10.32#ibcon#read 5, iclass 37, count 0 2006.183.07:48:10.32#ibcon#about to read 6, iclass 37, count 0 2006.183.07:48:10.32#ibcon#read 6, iclass 37, count 0 2006.183.07:48:10.32#ibcon#end of sib2, iclass 37, count 0 2006.183.07:48:10.32#ibcon#*after write, iclass 37, count 0 2006.183.07:48:10.32#ibcon#*before return 0, iclass 37, count 0 2006.183.07:48:10.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:48:10.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:48:10.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.07:48:10.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.07:48:10.32$vc4f8/va=8,7 2006.183.07:48:10.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.07:48:10.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.07:48:10.32#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:10.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:48:10.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:48:10.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:48:10.38#ibcon#enter wrdev, iclass 39, count 2 2006.183.07:48:10.38#ibcon#first serial, iclass 39, count 2 2006.183.07:48:10.38#ibcon#enter sib2, iclass 39, count 2 2006.183.07:48:10.38#ibcon#flushed, iclass 39, count 2 2006.183.07:48:10.38#ibcon#about to write, iclass 39, count 2 2006.183.07:48:10.38#ibcon#wrote, iclass 39, count 2 2006.183.07:48:10.38#ibcon#about to read 3, iclass 39, count 2 2006.183.07:48:10.40#ibcon#read 3, iclass 39, count 2 2006.183.07:48:10.40#ibcon#about to read 4, iclass 39, count 2 2006.183.07:48:10.40#ibcon#read 4, iclass 39, count 2 2006.183.07:48:10.40#ibcon#about to read 5, iclass 39, count 2 2006.183.07:48:10.40#ibcon#read 5, iclass 39, count 2 2006.183.07:48:10.40#ibcon#about to read 6, iclass 39, count 2 2006.183.07:48:10.40#ibcon#read 6, iclass 39, count 2 2006.183.07:48:10.40#ibcon#end of sib2, iclass 39, count 2 2006.183.07:48:10.40#ibcon#*mode == 0, iclass 39, count 2 2006.183.07:48:10.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.07:48:10.40#ibcon#[25=AT08-07\r\n] 2006.183.07:48:10.40#ibcon#*before write, iclass 39, count 2 2006.183.07:48:10.40#ibcon#enter sib2, iclass 39, count 2 2006.183.07:48:10.40#ibcon#flushed, iclass 39, count 2 2006.183.07:48:10.40#ibcon#about to write, iclass 39, count 2 2006.183.07:48:10.40#ibcon#wrote, iclass 39, count 2 2006.183.07:48:10.40#ibcon#about to read 3, iclass 39, count 2 2006.183.07:48:10.43#ibcon#read 3, iclass 39, count 2 2006.183.07:48:10.43#ibcon#about to read 4, iclass 39, count 2 2006.183.07:48:10.43#ibcon#read 4, iclass 39, count 2 2006.183.07:48:10.43#ibcon#about to read 5, iclass 39, count 2 2006.183.07:48:10.43#ibcon#read 5, iclass 39, count 2 2006.183.07:48:10.43#ibcon#about to read 6, iclass 39, count 2 2006.183.07:48:10.43#ibcon#read 6, iclass 39, count 2 2006.183.07:48:10.43#ibcon#end of sib2, iclass 39, count 2 2006.183.07:48:10.43#ibcon#*after write, iclass 39, count 2 2006.183.07:48:10.43#ibcon#*before return 0, iclass 39, count 2 2006.183.07:48:10.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:48:10.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:48:10.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.07:48:10.43#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:10.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:48:10.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:48:10.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:48:10.55#ibcon#enter wrdev, iclass 39, count 0 2006.183.07:48:10.55#ibcon#first serial, iclass 39, count 0 2006.183.07:48:10.55#ibcon#enter sib2, iclass 39, count 0 2006.183.07:48:10.55#ibcon#flushed, iclass 39, count 0 2006.183.07:48:10.55#ibcon#about to write, iclass 39, count 0 2006.183.07:48:10.55#ibcon#wrote, iclass 39, count 0 2006.183.07:48:10.55#ibcon#about to read 3, iclass 39, count 0 2006.183.07:48:10.57#ibcon#read 3, iclass 39, count 0 2006.183.07:48:10.57#ibcon#about to read 4, iclass 39, count 0 2006.183.07:48:10.57#ibcon#read 4, iclass 39, count 0 2006.183.07:48:10.57#ibcon#about to read 5, iclass 39, count 0 2006.183.07:48:10.57#ibcon#read 5, iclass 39, count 0 2006.183.07:48:10.57#ibcon#about to read 6, iclass 39, count 0 2006.183.07:48:10.57#ibcon#read 6, iclass 39, count 0 2006.183.07:48:10.57#ibcon#end of sib2, iclass 39, count 0 2006.183.07:48:10.57#ibcon#*mode == 0, iclass 39, count 0 2006.183.07:48:10.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.07:48:10.57#ibcon#[25=USB\r\n] 2006.183.07:48:10.57#ibcon#*before write, iclass 39, count 0 2006.183.07:48:10.57#ibcon#enter sib2, iclass 39, count 0 2006.183.07:48:10.57#ibcon#flushed, iclass 39, count 0 2006.183.07:48:10.57#ibcon#about to write, iclass 39, count 0 2006.183.07:48:10.57#ibcon#wrote, iclass 39, count 0 2006.183.07:48:10.57#ibcon#about to read 3, iclass 39, count 0 2006.183.07:48:10.60#ibcon#read 3, iclass 39, count 0 2006.183.07:48:10.60#ibcon#about to read 4, iclass 39, count 0 2006.183.07:48:10.60#ibcon#read 4, iclass 39, count 0 2006.183.07:48:10.60#ibcon#about to read 5, iclass 39, count 0 2006.183.07:48:10.60#ibcon#read 5, iclass 39, count 0 2006.183.07:48:10.60#ibcon#about to read 6, iclass 39, count 0 2006.183.07:48:10.60#ibcon#read 6, iclass 39, count 0 2006.183.07:48:10.60#ibcon#end of sib2, iclass 39, count 0 2006.183.07:48:10.60#ibcon#*after write, iclass 39, count 0 2006.183.07:48:10.60#ibcon#*before return 0, iclass 39, count 0 2006.183.07:48:10.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:48:10.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:48:10.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.07:48:10.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.07:48:10.60$vc4f8/vblo=1,632.99 2006.183.07:48:10.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.07:48:10.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.07:48:10.60#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:10.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:48:10.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:48:10.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:48:10.60#ibcon#enter wrdev, iclass 3, count 0 2006.183.07:48:10.60#ibcon#first serial, iclass 3, count 0 2006.183.07:48:10.60#ibcon#enter sib2, iclass 3, count 0 2006.183.07:48:10.60#ibcon#flushed, iclass 3, count 0 2006.183.07:48:10.60#ibcon#about to write, iclass 3, count 0 2006.183.07:48:10.60#ibcon#wrote, iclass 3, count 0 2006.183.07:48:10.60#ibcon#about to read 3, iclass 3, count 0 2006.183.07:48:10.62#ibcon#read 3, iclass 3, count 0 2006.183.07:48:10.62#ibcon#about to read 4, iclass 3, count 0 2006.183.07:48:10.62#ibcon#read 4, iclass 3, count 0 2006.183.07:48:10.62#ibcon#about to read 5, iclass 3, count 0 2006.183.07:48:10.62#ibcon#read 5, iclass 3, count 0 2006.183.07:48:10.62#ibcon#about to read 6, iclass 3, count 0 2006.183.07:48:10.62#ibcon#read 6, iclass 3, count 0 2006.183.07:48:10.62#ibcon#end of sib2, iclass 3, count 0 2006.183.07:48:10.62#ibcon#*mode == 0, iclass 3, count 0 2006.183.07:48:10.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.07:48:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:48:10.62#ibcon#*before write, iclass 3, count 0 2006.183.07:48:10.62#ibcon#enter sib2, iclass 3, count 0 2006.183.07:48:10.62#ibcon#flushed, iclass 3, count 0 2006.183.07:48:10.62#ibcon#about to write, iclass 3, count 0 2006.183.07:48:10.62#ibcon#wrote, iclass 3, count 0 2006.183.07:48:10.62#ibcon#about to read 3, iclass 3, count 0 2006.183.07:48:10.66#ibcon#read 3, iclass 3, count 0 2006.183.07:48:10.66#ibcon#about to read 4, iclass 3, count 0 2006.183.07:48:10.66#ibcon#read 4, iclass 3, count 0 2006.183.07:48:10.66#ibcon#about to read 5, iclass 3, count 0 2006.183.07:48:10.66#ibcon#read 5, iclass 3, count 0 2006.183.07:48:10.66#ibcon#about to read 6, iclass 3, count 0 2006.183.07:48:10.66#ibcon#read 6, iclass 3, count 0 2006.183.07:48:10.66#ibcon#end of sib2, iclass 3, count 0 2006.183.07:48:10.66#ibcon#*after write, iclass 3, count 0 2006.183.07:48:10.66#ibcon#*before return 0, iclass 3, count 0 2006.183.07:48:10.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:48:10.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:48:10.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.07:48:10.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.07:48:10.66$vc4f8/vb=1,4 2006.183.07:48:10.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.07:48:10.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.07:48:10.66#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:10.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:48:10.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:48:10.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:48:10.66#ibcon#enter wrdev, iclass 5, count 2 2006.183.07:48:10.66#ibcon#first serial, iclass 5, count 2 2006.183.07:48:10.66#ibcon#enter sib2, iclass 5, count 2 2006.183.07:48:10.66#ibcon#flushed, iclass 5, count 2 2006.183.07:48:10.66#ibcon#about to write, iclass 5, count 2 2006.183.07:48:10.66#ibcon#wrote, iclass 5, count 2 2006.183.07:48:10.66#ibcon#about to read 3, iclass 5, count 2 2006.183.07:48:10.68#ibcon#read 3, iclass 5, count 2 2006.183.07:48:10.68#ibcon#about to read 4, iclass 5, count 2 2006.183.07:48:10.68#ibcon#read 4, iclass 5, count 2 2006.183.07:48:10.68#ibcon#about to read 5, iclass 5, count 2 2006.183.07:48:10.68#ibcon#read 5, iclass 5, count 2 2006.183.07:48:10.68#ibcon#about to read 6, iclass 5, count 2 2006.183.07:48:10.68#ibcon#read 6, iclass 5, count 2 2006.183.07:48:10.68#ibcon#end of sib2, iclass 5, count 2 2006.183.07:48:10.68#ibcon#*mode == 0, iclass 5, count 2 2006.183.07:48:10.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.07:48:10.68#ibcon#[27=AT01-04\r\n] 2006.183.07:48:10.68#ibcon#*before write, iclass 5, count 2 2006.183.07:48:10.68#ibcon#enter sib2, iclass 5, count 2 2006.183.07:48:10.68#ibcon#flushed, iclass 5, count 2 2006.183.07:48:10.68#ibcon#about to write, iclass 5, count 2 2006.183.07:48:10.68#ibcon#wrote, iclass 5, count 2 2006.183.07:48:10.68#ibcon#about to read 3, iclass 5, count 2 2006.183.07:48:10.71#ibcon#read 3, iclass 5, count 2 2006.183.07:48:10.71#ibcon#about to read 4, iclass 5, count 2 2006.183.07:48:10.71#ibcon#read 4, iclass 5, count 2 2006.183.07:48:10.71#ibcon#about to read 5, iclass 5, count 2 2006.183.07:48:10.71#ibcon#read 5, iclass 5, count 2 2006.183.07:48:10.71#ibcon#about to read 6, iclass 5, count 2 2006.183.07:48:10.71#ibcon#read 6, iclass 5, count 2 2006.183.07:48:10.71#ibcon#end of sib2, iclass 5, count 2 2006.183.07:48:10.71#ibcon#*after write, iclass 5, count 2 2006.183.07:48:10.71#ibcon#*before return 0, iclass 5, count 2 2006.183.07:48:10.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:48:10.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:48:10.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.07:48:10.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:10.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:48:10.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:48:10.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:48:10.83#ibcon#enter wrdev, iclass 5, count 0 2006.183.07:48:10.83#ibcon#first serial, iclass 5, count 0 2006.183.07:48:10.83#ibcon#enter sib2, iclass 5, count 0 2006.183.07:48:10.83#ibcon#flushed, iclass 5, count 0 2006.183.07:48:10.83#ibcon#about to write, iclass 5, count 0 2006.183.07:48:10.83#ibcon#wrote, iclass 5, count 0 2006.183.07:48:10.83#ibcon#about to read 3, iclass 5, count 0 2006.183.07:48:10.85#ibcon#read 3, iclass 5, count 0 2006.183.07:48:10.85#ibcon#about to read 4, iclass 5, count 0 2006.183.07:48:10.85#ibcon#read 4, iclass 5, count 0 2006.183.07:48:10.85#ibcon#about to read 5, iclass 5, count 0 2006.183.07:48:10.85#ibcon#read 5, iclass 5, count 0 2006.183.07:48:10.85#ibcon#about to read 6, iclass 5, count 0 2006.183.07:48:10.85#ibcon#read 6, iclass 5, count 0 2006.183.07:48:10.85#ibcon#end of sib2, iclass 5, count 0 2006.183.07:48:10.85#ibcon#*mode == 0, iclass 5, count 0 2006.183.07:48:10.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.07:48:10.85#ibcon#[27=USB\r\n] 2006.183.07:48:10.85#ibcon#*before write, iclass 5, count 0 2006.183.07:48:10.85#ibcon#enter sib2, iclass 5, count 0 2006.183.07:48:10.85#ibcon#flushed, iclass 5, count 0 2006.183.07:48:10.85#ibcon#about to write, iclass 5, count 0 2006.183.07:48:10.85#ibcon#wrote, iclass 5, count 0 2006.183.07:48:10.85#ibcon#about to read 3, iclass 5, count 0 2006.183.07:48:10.88#ibcon#read 3, iclass 5, count 0 2006.183.07:48:10.88#ibcon#about to read 4, iclass 5, count 0 2006.183.07:48:10.88#ibcon#read 4, iclass 5, count 0 2006.183.07:48:10.88#ibcon#about to read 5, iclass 5, count 0 2006.183.07:48:10.88#ibcon#read 5, iclass 5, count 0 2006.183.07:48:10.88#ibcon#about to read 6, iclass 5, count 0 2006.183.07:48:10.88#ibcon#read 6, iclass 5, count 0 2006.183.07:48:10.88#ibcon#end of sib2, iclass 5, count 0 2006.183.07:48:10.88#ibcon#*after write, iclass 5, count 0 2006.183.07:48:10.88#ibcon#*before return 0, iclass 5, count 0 2006.183.07:48:10.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:48:10.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:48:10.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.07:48:10.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.07:48:10.88$vc4f8/vblo=2,640.99 2006.183.07:48:10.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.07:48:10.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.07:48:10.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:10.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:10.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:10.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:10.88#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:48:10.88#ibcon#first serial, iclass 7, count 0 2006.183.07:48:10.88#ibcon#enter sib2, iclass 7, count 0 2006.183.07:48:10.88#ibcon#flushed, iclass 7, count 0 2006.183.07:48:10.88#ibcon#about to write, iclass 7, count 0 2006.183.07:48:10.88#ibcon#wrote, iclass 7, count 0 2006.183.07:48:10.88#ibcon#about to read 3, iclass 7, count 0 2006.183.07:48:10.90#ibcon#read 3, iclass 7, count 0 2006.183.07:48:10.90#ibcon#about to read 4, iclass 7, count 0 2006.183.07:48:10.90#ibcon#read 4, iclass 7, count 0 2006.183.07:48:10.90#ibcon#about to read 5, iclass 7, count 0 2006.183.07:48:10.90#ibcon#read 5, iclass 7, count 0 2006.183.07:48:10.90#ibcon#about to read 6, iclass 7, count 0 2006.183.07:48:10.90#ibcon#read 6, iclass 7, count 0 2006.183.07:48:10.90#ibcon#end of sib2, iclass 7, count 0 2006.183.07:48:10.90#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:48:10.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:48:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:48:10.90#ibcon#*before write, iclass 7, count 0 2006.183.07:48:10.90#ibcon#enter sib2, iclass 7, count 0 2006.183.07:48:10.90#ibcon#flushed, iclass 7, count 0 2006.183.07:48:10.90#ibcon#about to write, iclass 7, count 0 2006.183.07:48:10.90#ibcon#wrote, iclass 7, count 0 2006.183.07:48:10.90#ibcon#about to read 3, iclass 7, count 0 2006.183.07:48:10.94#ibcon#read 3, iclass 7, count 0 2006.183.07:48:10.94#ibcon#about to read 4, iclass 7, count 0 2006.183.07:48:10.94#ibcon#read 4, iclass 7, count 0 2006.183.07:48:10.94#ibcon#about to read 5, iclass 7, count 0 2006.183.07:48:10.94#ibcon#read 5, iclass 7, count 0 2006.183.07:48:10.94#ibcon#about to read 6, iclass 7, count 0 2006.183.07:48:10.94#ibcon#read 6, iclass 7, count 0 2006.183.07:48:10.94#ibcon#end of sib2, iclass 7, count 0 2006.183.07:48:10.94#ibcon#*after write, iclass 7, count 0 2006.183.07:48:10.94#ibcon#*before return 0, iclass 7, count 0 2006.183.07:48:10.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:10.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:48:10.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:48:10.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:48:10.94$vc4f8/vb=2,4 2006.183.07:48:10.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.07:48:10.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.07:48:10.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:10.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:11.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:11.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:11.00#ibcon#enter wrdev, iclass 11, count 2 2006.183.07:48:11.00#ibcon#first serial, iclass 11, count 2 2006.183.07:48:11.00#ibcon#enter sib2, iclass 11, count 2 2006.183.07:48:11.00#ibcon#flushed, iclass 11, count 2 2006.183.07:48:11.00#ibcon#about to write, iclass 11, count 2 2006.183.07:48:11.00#ibcon#wrote, iclass 11, count 2 2006.183.07:48:11.00#ibcon#about to read 3, iclass 11, count 2 2006.183.07:48:11.02#ibcon#read 3, iclass 11, count 2 2006.183.07:48:11.02#ibcon#about to read 4, iclass 11, count 2 2006.183.07:48:11.02#ibcon#read 4, iclass 11, count 2 2006.183.07:48:11.02#ibcon#about to read 5, iclass 11, count 2 2006.183.07:48:11.02#ibcon#read 5, iclass 11, count 2 2006.183.07:48:11.02#ibcon#about to read 6, iclass 11, count 2 2006.183.07:48:11.02#ibcon#read 6, iclass 11, count 2 2006.183.07:48:11.02#ibcon#end of sib2, iclass 11, count 2 2006.183.07:48:11.02#ibcon#*mode == 0, iclass 11, count 2 2006.183.07:48:11.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.07:48:11.02#ibcon#[27=AT02-04\r\n] 2006.183.07:48:11.02#ibcon#*before write, iclass 11, count 2 2006.183.07:48:11.02#ibcon#enter sib2, iclass 11, count 2 2006.183.07:48:11.02#ibcon#flushed, iclass 11, count 2 2006.183.07:48:11.02#ibcon#about to write, iclass 11, count 2 2006.183.07:48:11.02#ibcon#wrote, iclass 11, count 2 2006.183.07:48:11.02#ibcon#about to read 3, iclass 11, count 2 2006.183.07:48:11.05#ibcon#read 3, iclass 11, count 2 2006.183.07:48:11.05#ibcon#about to read 4, iclass 11, count 2 2006.183.07:48:11.05#ibcon#read 4, iclass 11, count 2 2006.183.07:48:11.05#ibcon#about to read 5, iclass 11, count 2 2006.183.07:48:11.05#ibcon#read 5, iclass 11, count 2 2006.183.07:48:11.05#ibcon#about to read 6, iclass 11, count 2 2006.183.07:48:11.05#ibcon#read 6, iclass 11, count 2 2006.183.07:48:11.05#ibcon#end of sib2, iclass 11, count 2 2006.183.07:48:11.05#ibcon#*after write, iclass 11, count 2 2006.183.07:48:11.05#ibcon#*before return 0, iclass 11, count 2 2006.183.07:48:11.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:11.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:48:11.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.07:48:11.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:11.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:11.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:11.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:11.17#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:48:11.17#ibcon#first serial, iclass 11, count 0 2006.183.07:48:11.17#ibcon#enter sib2, iclass 11, count 0 2006.183.07:48:11.17#ibcon#flushed, iclass 11, count 0 2006.183.07:48:11.17#ibcon#about to write, iclass 11, count 0 2006.183.07:48:11.17#ibcon#wrote, iclass 11, count 0 2006.183.07:48:11.17#ibcon#about to read 3, iclass 11, count 0 2006.183.07:48:11.19#ibcon#read 3, iclass 11, count 0 2006.183.07:48:11.19#ibcon#about to read 4, iclass 11, count 0 2006.183.07:48:11.19#ibcon#read 4, iclass 11, count 0 2006.183.07:48:11.19#ibcon#about to read 5, iclass 11, count 0 2006.183.07:48:11.19#ibcon#read 5, iclass 11, count 0 2006.183.07:48:11.19#ibcon#about to read 6, iclass 11, count 0 2006.183.07:48:11.19#ibcon#read 6, iclass 11, count 0 2006.183.07:48:11.19#ibcon#end of sib2, iclass 11, count 0 2006.183.07:48:11.19#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:48:11.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:48:11.19#ibcon#[27=USB\r\n] 2006.183.07:48:11.19#ibcon#*before write, iclass 11, count 0 2006.183.07:48:11.19#ibcon#enter sib2, iclass 11, count 0 2006.183.07:48:11.19#ibcon#flushed, iclass 11, count 0 2006.183.07:48:11.19#ibcon#about to write, iclass 11, count 0 2006.183.07:48:11.19#ibcon#wrote, iclass 11, count 0 2006.183.07:48:11.19#ibcon#about to read 3, iclass 11, count 0 2006.183.07:48:11.22#ibcon#read 3, iclass 11, count 0 2006.183.07:48:11.22#ibcon#about to read 4, iclass 11, count 0 2006.183.07:48:11.22#ibcon#read 4, iclass 11, count 0 2006.183.07:48:11.22#ibcon#about to read 5, iclass 11, count 0 2006.183.07:48:11.22#ibcon#read 5, iclass 11, count 0 2006.183.07:48:11.22#ibcon#about to read 6, iclass 11, count 0 2006.183.07:48:11.22#ibcon#read 6, iclass 11, count 0 2006.183.07:48:11.22#ibcon#end of sib2, iclass 11, count 0 2006.183.07:48:11.22#ibcon#*after write, iclass 11, count 0 2006.183.07:48:11.22#ibcon#*before return 0, iclass 11, count 0 2006.183.07:48:11.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:11.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:48:11.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:48:11.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:48:11.22$vc4f8/vblo=3,656.99 2006.183.07:48:11.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:48:11.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:48:11.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:11.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:11.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:11.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:11.22#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:48:11.22#ibcon#first serial, iclass 13, count 0 2006.183.07:48:11.22#ibcon#enter sib2, iclass 13, count 0 2006.183.07:48:11.22#ibcon#flushed, iclass 13, count 0 2006.183.07:48:11.22#ibcon#about to write, iclass 13, count 0 2006.183.07:48:11.22#ibcon#wrote, iclass 13, count 0 2006.183.07:48:11.22#ibcon#about to read 3, iclass 13, count 0 2006.183.07:48:11.24#ibcon#read 3, iclass 13, count 0 2006.183.07:48:11.24#ibcon#about to read 4, iclass 13, count 0 2006.183.07:48:11.24#ibcon#read 4, iclass 13, count 0 2006.183.07:48:11.24#ibcon#about to read 5, iclass 13, count 0 2006.183.07:48:11.24#ibcon#read 5, iclass 13, count 0 2006.183.07:48:11.24#ibcon#about to read 6, iclass 13, count 0 2006.183.07:48:11.24#ibcon#read 6, iclass 13, count 0 2006.183.07:48:11.24#ibcon#end of sib2, iclass 13, count 0 2006.183.07:48:11.24#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:48:11.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:48:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:48:11.24#ibcon#*before write, iclass 13, count 0 2006.183.07:48:11.24#ibcon#enter sib2, iclass 13, count 0 2006.183.07:48:11.24#ibcon#flushed, iclass 13, count 0 2006.183.07:48:11.24#ibcon#about to write, iclass 13, count 0 2006.183.07:48:11.24#ibcon#wrote, iclass 13, count 0 2006.183.07:48:11.24#ibcon#about to read 3, iclass 13, count 0 2006.183.07:48:11.28#ibcon#read 3, iclass 13, count 0 2006.183.07:48:11.28#ibcon#about to read 4, iclass 13, count 0 2006.183.07:48:11.28#ibcon#read 4, iclass 13, count 0 2006.183.07:48:11.28#ibcon#about to read 5, iclass 13, count 0 2006.183.07:48:11.28#ibcon#read 5, iclass 13, count 0 2006.183.07:48:11.28#ibcon#about to read 6, iclass 13, count 0 2006.183.07:48:11.28#ibcon#read 6, iclass 13, count 0 2006.183.07:48:11.28#ibcon#end of sib2, iclass 13, count 0 2006.183.07:48:11.28#ibcon#*after write, iclass 13, count 0 2006.183.07:48:11.28#ibcon#*before return 0, iclass 13, count 0 2006.183.07:48:11.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:11.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:48:11.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:48:11.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:48:11.28$vc4f8/vb=3,4 2006.183.07:48:11.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:48:11.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:48:11.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:11.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:11.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:11.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:11.34#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:48:11.34#ibcon#first serial, iclass 15, count 2 2006.183.07:48:11.34#ibcon#enter sib2, iclass 15, count 2 2006.183.07:48:11.34#ibcon#flushed, iclass 15, count 2 2006.183.07:48:11.34#ibcon#about to write, iclass 15, count 2 2006.183.07:48:11.34#ibcon#wrote, iclass 15, count 2 2006.183.07:48:11.34#ibcon#about to read 3, iclass 15, count 2 2006.183.07:48:11.36#ibcon#read 3, iclass 15, count 2 2006.183.07:48:11.36#ibcon#about to read 4, iclass 15, count 2 2006.183.07:48:11.36#ibcon#read 4, iclass 15, count 2 2006.183.07:48:11.36#ibcon#about to read 5, iclass 15, count 2 2006.183.07:48:11.36#ibcon#read 5, iclass 15, count 2 2006.183.07:48:11.36#ibcon#about to read 6, iclass 15, count 2 2006.183.07:48:11.36#ibcon#read 6, iclass 15, count 2 2006.183.07:48:11.36#ibcon#end of sib2, iclass 15, count 2 2006.183.07:48:11.36#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:48:11.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:48:11.36#ibcon#[27=AT03-04\r\n] 2006.183.07:48:11.36#ibcon#*before write, iclass 15, count 2 2006.183.07:48:11.36#ibcon#enter sib2, iclass 15, count 2 2006.183.07:48:11.36#ibcon#flushed, iclass 15, count 2 2006.183.07:48:11.36#ibcon#about to write, iclass 15, count 2 2006.183.07:48:11.36#ibcon#wrote, iclass 15, count 2 2006.183.07:48:11.36#ibcon#about to read 3, iclass 15, count 2 2006.183.07:48:11.39#ibcon#read 3, iclass 15, count 2 2006.183.07:48:11.39#ibcon#about to read 4, iclass 15, count 2 2006.183.07:48:11.39#ibcon#read 4, iclass 15, count 2 2006.183.07:48:11.39#ibcon#about to read 5, iclass 15, count 2 2006.183.07:48:11.39#ibcon#read 5, iclass 15, count 2 2006.183.07:48:11.39#ibcon#about to read 6, iclass 15, count 2 2006.183.07:48:11.39#ibcon#read 6, iclass 15, count 2 2006.183.07:48:11.39#ibcon#end of sib2, iclass 15, count 2 2006.183.07:48:11.39#ibcon#*after write, iclass 15, count 2 2006.183.07:48:11.39#ibcon#*before return 0, iclass 15, count 2 2006.183.07:48:11.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:11.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:48:11.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:48:11.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:11.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:11.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:11.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:11.51#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:48:11.51#ibcon#first serial, iclass 15, count 0 2006.183.07:48:11.51#ibcon#enter sib2, iclass 15, count 0 2006.183.07:48:11.51#ibcon#flushed, iclass 15, count 0 2006.183.07:48:11.51#ibcon#about to write, iclass 15, count 0 2006.183.07:48:11.51#ibcon#wrote, iclass 15, count 0 2006.183.07:48:11.51#ibcon#about to read 3, iclass 15, count 0 2006.183.07:48:11.53#ibcon#read 3, iclass 15, count 0 2006.183.07:48:11.53#ibcon#about to read 4, iclass 15, count 0 2006.183.07:48:11.53#ibcon#read 4, iclass 15, count 0 2006.183.07:48:11.53#ibcon#about to read 5, iclass 15, count 0 2006.183.07:48:11.53#ibcon#read 5, iclass 15, count 0 2006.183.07:48:11.53#ibcon#about to read 6, iclass 15, count 0 2006.183.07:48:11.53#ibcon#read 6, iclass 15, count 0 2006.183.07:48:11.53#ibcon#end of sib2, iclass 15, count 0 2006.183.07:48:11.53#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:48:11.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:48:11.53#ibcon#[27=USB\r\n] 2006.183.07:48:11.53#ibcon#*before write, iclass 15, count 0 2006.183.07:48:11.53#ibcon#enter sib2, iclass 15, count 0 2006.183.07:48:11.53#ibcon#flushed, iclass 15, count 0 2006.183.07:48:11.53#ibcon#about to write, iclass 15, count 0 2006.183.07:48:11.53#ibcon#wrote, iclass 15, count 0 2006.183.07:48:11.53#ibcon#about to read 3, iclass 15, count 0 2006.183.07:48:11.56#ibcon#read 3, iclass 15, count 0 2006.183.07:48:11.56#ibcon#about to read 4, iclass 15, count 0 2006.183.07:48:11.56#ibcon#read 4, iclass 15, count 0 2006.183.07:48:11.56#ibcon#about to read 5, iclass 15, count 0 2006.183.07:48:11.56#ibcon#read 5, iclass 15, count 0 2006.183.07:48:11.56#ibcon#about to read 6, iclass 15, count 0 2006.183.07:48:11.56#ibcon#read 6, iclass 15, count 0 2006.183.07:48:11.56#ibcon#end of sib2, iclass 15, count 0 2006.183.07:48:11.56#ibcon#*after write, iclass 15, count 0 2006.183.07:48:11.56#ibcon#*before return 0, iclass 15, count 0 2006.183.07:48:11.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:11.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:48:11.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:48:11.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:48:11.56$vc4f8/vblo=4,712.99 2006.183.07:48:11.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:48:11.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:48:11.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:11.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:11.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:11.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:11.56#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:48:11.56#ibcon#first serial, iclass 17, count 0 2006.183.07:48:11.56#ibcon#enter sib2, iclass 17, count 0 2006.183.07:48:11.56#ibcon#flushed, iclass 17, count 0 2006.183.07:48:11.56#ibcon#about to write, iclass 17, count 0 2006.183.07:48:11.56#ibcon#wrote, iclass 17, count 0 2006.183.07:48:11.56#ibcon#about to read 3, iclass 17, count 0 2006.183.07:48:11.58#ibcon#read 3, iclass 17, count 0 2006.183.07:48:11.58#ibcon#about to read 4, iclass 17, count 0 2006.183.07:48:11.58#ibcon#read 4, iclass 17, count 0 2006.183.07:48:11.58#ibcon#about to read 5, iclass 17, count 0 2006.183.07:48:11.58#ibcon#read 5, iclass 17, count 0 2006.183.07:48:11.58#ibcon#about to read 6, iclass 17, count 0 2006.183.07:48:11.58#ibcon#read 6, iclass 17, count 0 2006.183.07:48:11.58#ibcon#end of sib2, iclass 17, count 0 2006.183.07:48:11.58#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:48:11.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:48:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:48:11.58#ibcon#*before write, iclass 17, count 0 2006.183.07:48:11.58#ibcon#enter sib2, iclass 17, count 0 2006.183.07:48:11.58#ibcon#flushed, iclass 17, count 0 2006.183.07:48:11.58#ibcon#about to write, iclass 17, count 0 2006.183.07:48:11.58#ibcon#wrote, iclass 17, count 0 2006.183.07:48:11.58#ibcon#about to read 3, iclass 17, count 0 2006.183.07:48:11.62#ibcon#read 3, iclass 17, count 0 2006.183.07:48:11.62#ibcon#about to read 4, iclass 17, count 0 2006.183.07:48:11.62#ibcon#read 4, iclass 17, count 0 2006.183.07:48:11.62#ibcon#about to read 5, iclass 17, count 0 2006.183.07:48:11.62#ibcon#read 5, iclass 17, count 0 2006.183.07:48:11.62#ibcon#about to read 6, iclass 17, count 0 2006.183.07:48:11.62#ibcon#read 6, iclass 17, count 0 2006.183.07:48:11.62#ibcon#end of sib2, iclass 17, count 0 2006.183.07:48:11.62#ibcon#*after write, iclass 17, count 0 2006.183.07:48:11.62#ibcon#*before return 0, iclass 17, count 0 2006.183.07:48:11.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:11.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:48:11.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:48:11.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:48:11.62$vc4f8/vb=4,4 2006.183.07:48:11.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:48:11.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:48:11.62#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:11.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:11.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:11.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:11.68#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:48:11.68#ibcon#first serial, iclass 19, count 2 2006.183.07:48:11.68#ibcon#enter sib2, iclass 19, count 2 2006.183.07:48:11.68#ibcon#flushed, iclass 19, count 2 2006.183.07:48:11.68#ibcon#about to write, iclass 19, count 2 2006.183.07:48:11.68#ibcon#wrote, iclass 19, count 2 2006.183.07:48:11.68#ibcon#about to read 3, iclass 19, count 2 2006.183.07:48:11.70#ibcon#read 3, iclass 19, count 2 2006.183.07:48:11.70#ibcon#about to read 4, iclass 19, count 2 2006.183.07:48:11.70#ibcon#read 4, iclass 19, count 2 2006.183.07:48:11.70#ibcon#about to read 5, iclass 19, count 2 2006.183.07:48:11.70#ibcon#read 5, iclass 19, count 2 2006.183.07:48:11.70#ibcon#about to read 6, iclass 19, count 2 2006.183.07:48:11.70#ibcon#read 6, iclass 19, count 2 2006.183.07:48:11.70#ibcon#end of sib2, iclass 19, count 2 2006.183.07:48:11.70#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:48:11.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:48:11.70#ibcon#[27=AT04-04\r\n] 2006.183.07:48:11.70#ibcon#*before write, iclass 19, count 2 2006.183.07:48:11.70#ibcon#enter sib2, iclass 19, count 2 2006.183.07:48:11.70#ibcon#flushed, iclass 19, count 2 2006.183.07:48:11.70#ibcon#about to write, iclass 19, count 2 2006.183.07:48:11.70#ibcon#wrote, iclass 19, count 2 2006.183.07:48:11.70#ibcon#about to read 3, iclass 19, count 2 2006.183.07:48:11.73#ibcon#read 3, iclass 19, count 2 2006.183.07:48:11.73#ibcon#about to read 4, iclass 19, count 2 2006.183.07:48:11.73#ibcon#read 4, iclass 19, count 2 2006.183.07:48:11.73#ibcon#about to read 5, iclass 19, count 2 2006.183.07:48:11.73#ibcon#read 5, iclass 19, count 2 2006.183.07:48:11.73#ibcon#about to read 6, iclass 19, count 2 2006.183.07:48:11.73#ibcon#read 6, iclass 19, count 2 2006.183.07:48:11.73#ibcon#end of sib2, iclass 19, count 2 2006.183.07:48:11.73#ibcon#*after write, iclass 19, count 2 2006.183.07:48:11.73#ibcon#*before return 0, iclass 19, count 2 2006.183.07:48:11.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:11.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:48:11.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:48:11.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:11.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:11.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:11.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:11.85#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:48:11.85#ibcon#first serial, iclass 19, count 0 2006.183.07:48:11.85#ibcon#enter sib2, iclass 19, count 0 2006.183.07:48:11.85#ibcon#flushed, iclass 19, count 0 2006.183.07:48:11.85#ibcon#about to write, iclass 19, count 0 2006.183.07:48:11.85#ibcon#wrote, iclass 19, count 0 2006.183.07:48:11.85#ibcon#about to read 3, iclass 19, count 0 2006.183.07:48:11.87#ibcon#read 3, iclass 19, count 0 2006.183.07:48:11.87#ibcon#about to read 4, iclass 19, count 0 2006.183.07:48:11.87#ibcon#read 4, iclass 19, count 0 2006.183.07:48:11.87#ibcon#about to read 5, iclass 19, count 0 2006.183.07:48:11.87#ibcon#read 5, iclass 19, count 0 2006.183.07:48:11.87#ibcon#about to read 6, iclass 19, count 0 2006.183.07:48:11.87#ibcon#read 6, iclass 19, count 0 2006.183.07:48:11.87#ibcon#end of sib2, iclass 19, count 0 2006.183.07:48:11.87#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:48:11.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:48:11.87#ibcon#[27=USB\r\n] 2006.183.07:48:11.87#ibcon#*before write, iclass 19, count 0 2006.183.07:48:11.87#ibcon#enter sib2, iclass 19, count 0 2006.183.07:48:11.87#ibcon#flushed, iclass 19, count 0 2006.183.07:48:11.87#ibcon#about to write, iclass 19, count 0 2006.183.07:48:11.87#ibcon#wrote, iclass 19, count 0 2006.183.07:48:11.87#ibcon#about to read 3, iclass 19, count 0 2006.183.07:48:11.90#ibcon#read 3, iclass 19, count 0 2006.183.07:48:11.90#ibcon#about to read 4, iclass 19, count 0 2006.183.07:48:11.90#ibcon#read 4, iclass 19, count 0 2006.183.07:48:11.90#ibcon#about to read 5, iclass 19, count 0 2006.183.07:48:11.90#ibcon#read 5, iclass 19, count 0 2006.183.07:48:11.90#ibcon#about to read 6, iclass 19, count 0 2006.183.07:48:11.90#ibcon#read 6, iclass 19, count 0 2006.183.07:48:11.90#ibcon#end of sib2, iclass 19, count 0 2006.183.07:48:11.90#ibcon#*after write, iclass 19, count 0 2006.183.07:48:11.90#ibcon#*before return 0, iclass 19, count 0 2006.183.07:48:11.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:11.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:48:11.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:48:11.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:48:11.90$vc4f8/vblo=5,744.99 2006.183.07:48:11.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:48:11.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:48:11.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:11.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:11.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:11.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:11.90#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:48:11.90#ibcon#first serial, iclass 21, count 0 2006.183.07:48:11.90#ibcon#enter sib2, iclass 21, count 0 2006.183.07:48:11.90#ibcon#flushed, iclass 21, count 0 2006.183.07:48:11.90#ibcon#about to write, iclass 21, count 0 2006.183.07:48:11.90#ibcon#wrote, iclass 21, count 0 2006.183.07:48:11.90#ibcon#about to read 3, iclass 21, count 0 2006.183.07:48:11.92#ibcon#read 3, iclass 21, count 0 2006.183.07:48:11.92#ibcon#about to read 4, iclass 21, count 0 2006.183.07:48:11.92#ibcon#read 4, iclass 21, count 0 2006.183.07:48:11.92#ibcon#about to read 5, iclass 21, count 0 2006.183.07:48:11.92#ibcon#read 5, iclass 21, count 0 2006.183.07:48:11.92#ibcon#about to read 6, iclass 21, count 0 2006.183.07:48:11.92#ibcon#read 6, iclass 21, count 0 2006.183.07:48:11.92#ibcon#end of sib2, iclass 21, count 0 2006.183.07:48:11.92#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:48:11.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:48:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:48:11.92#ibcon#*before write, iclass 21, count 0 2006.183.07:48:11.92#ibcon#enter sib2, iclass 21, count 0 2006.183.07:48:11.92#ibcon#flushed, iclass 21, count 0 2006.183.07:48:11.92#ibcon#about to write, iclass 21, count 0 2006.183.07:48:11.92#ibcon#wrote, iclass 21, count 0 2006.183.07:48:11.92#ibcon#about to read 3, iclass 21, count 0 2006.183.07:48:11.96#ibcon#read 3, iclass 21, count 0 2006.183.07:48:11.96#ibcon#about to read 4, iclass 21, count 0 2006.183.07:48:11.96#ibcon#read 4, iclass 21, count 0 2006.183.07:48:11.96#ibcon#about to read 5, iclass 21, count 0 2006.183.07:48:11.96#ibcon#read 5, iclass 21, count 0 2006.183.07:48:11.96#ibcon#about to read 6, iclass 21, count 0 2006.183.07:48:11.96#ibcon#read 6, iclass 21, count 0 2006.183.07:48:11.96#ibcon#end of sib2, iclass 21, count 0 2006.183.07:48:11.96#ibcon#*after write, iclass 21, count 0 2006.183.07:48:11.96#ibcon#*before return 0, iclass 21, count 0 2006.183.07:48:11.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:11.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:48:11.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:48:11.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:48:11.96$vc4f8/vb=5,4 2006.183.07:48:11.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:48:11.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:48:11.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:11.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:12.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:12.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:12.03#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:48:12.03#ibcon#first serial, iclass 23, count 2 2006.183.07:48:12.03#ibcon#enter sib2, iclass 23, count 2 2006.183.07:48:12.03#ibcon#flushed, iclass 23, count 2 2006.183.07:48:12.03#ibcon#about to write, iclass 23, count 2 2006.183.07:48:12.03#ibcon#wrote, iclass 23, count 2 2006.183.07:48:12.03#ibcon#about to read 3, iclass 23, count 2 2006.183.07:48:12.04#ibcon#read 3, iclass 23, count 2 2006.183.07:48:12.04#ibcon#about to read 4, iclass 23, count 2 2006.183.07:48:12.04#ibcon#read 4, iclass 23, count 2 2006.183.07:48:12.04#ibcon#about to read 5, iclass 23, count 2 2006.183.07:48:12.04#ibcon#read 5, iclass 23, count 2 2006.183.07:48:12.04#ibcon#about to read 6, iclass 23, count 2 2006.183.07:48:12.04#ibcon#read 6, iclass 23, count 2 2006.183.07:48:12.04#ibcon#end of sib2, iclass 23, count 2 2006.183.07:48:12.04#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:48:12.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:48:12.04#ibcon#[27=AT05-04\r\n] 2006.183.07:48:12.04#ibcon#*before write, iclass 23, count 2 2006.183.07:48:12.04#ibcon#enter sib2, iclass 23, count 2 2006.183.07:48:12.04#ibcon#flushed, iclass 23, count 2 2006.183.07:48:12.04#ibcon#about to write, iclass 23, count 2 2006.183.07:48:12.04#ibcon#wrote, iclass 23, count 2 2006.183.07:48:12.04#ibcon#about to read 3, iclass 23, count 2 2006.183.07:48:12.07#ibcon#read 3, iclass 23, count 2 2006.183.07:48:12.07#ibcon#about to read 4, iclass 23, count 2 2006.183.07:48:12.07#ibcon#read 4, iclass 23, count 2 2006.183.07:48:12.07#ibcon#about to read 5, iclass 23, count 2 2006.183.07:48:12.07#ibcon#read 5, iclass 23, count 2 2006.183.07:48:12.07#ibcon#about to read 6, iclass 23, count 2 2006.183.07:48:12.07#ibcon#read 6, iclass 23, count 2 2006.183.07:48:12.07#ibcon#end of sib2, iclass 23, count 2 2006.183.07:48:12.07#ibcon#*after write, iclass 23, count 2 2006.183.07:48:12.07#ibcon#*before return 0, iclass 23, count 2 2006.183.07:48:12.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:12.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:48:12.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:48:12.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:12.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:12.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:12.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:12.19#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:48:12.19#ibcon#first serial, iclass 23, count 0 2006.183.07:48:12.19#ibcon#enter sib2, iclass 23, count 0 2006.183.07:48:12.19#ibcon#flushed, iclass 23, count 0 2006.183.07:48:12.19#ibcon#about to write, iclass 23, count 0 2006.183.07:48:12.19#ibcon#wrote, iclass 23, count 0 2006.183.07:48:12.19#ibcon#about to read 3, iclass 23, count 0 2006.183.07:48:12.21#ibcon#read 3, iclass 23, count 0 2006.183.07:48:12.21#ibcon#about to read 4, iclass 23, count 0 2006.183.07:48:12.21#ibcon#read 4, iclass 23, count 0 2006.183.07:48:12.21#ibcon#about to read 5, iclass 23, count 0 2006.183.07:48:12.21#ibcon#read 5, iclass 23, count 0 2006.183.07:48:12.21#ibcon#about to read 6, iclass 23, count 0 2006.183.07:48:12.21#ibcon#read 6, iclass 23, count 0 2006.183.07:48:12.21#ibcon#end of sib2, iclass 23, count 0 2006.183.07:48:12.21#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:48:12.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:48:12.21#ibcon#[27=USB\r\n] 2006.183.07:48:12.21#ibcon#*before write, iclass 23, count 0 2006.183.07:48:12.21#ibcon#enter sib2, iclass 23, count 0 2006.183.07:48:12.21#ibcon#flushed, iclass 23, count 0 2006.183.07:48:12.21#ibcon#about to write, iclass 23, count 0 2006.183.07:48:12.21#ibcon#wrote, iclass 23, count 0 2006.183.07:48:12.21#ibcon#about to read 3, iclass 23, count 0 2006.183.07:48:12.24#ibcon#read 3, iclass 23, count 0 2006.183.07:48:12.24#ibcon#about to read 4, iclass 23, count 0 2006.183.07:48:12.24#ibcon#read 4, iclass 23, count 0 2006.183.07:48:12.24#ibcon#about to read 5, iclass 23, count 0 2006.183.07:48:12.24#ibcon#read 5, iclass 23, count 0 2006.183.07:48:12.24#ibcon#about to read 6, iclass 23, count 0 2006.183.07:48:12.24#ibcon#read 6, iclass 23, count 0 2006.183.07:48:12.24#ibcon#end of sib2, iclass 23, count 0 2006.183.07:48:12.24#ibcon#*after write, iclass 23, count 0 2006.183.07:48:12.24#ibcon#*before return 0, iclass 23, count 0 2006.183.07:48:12.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:12.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:48:12.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:48:12.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:48:12.24$vc4f8/vblo=6,752.99 2006.183.07:48:12.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:48:12.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:48:12.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:48:12.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:12.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:12.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:12.24#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:48:12.24#ibcon#first serial, iclass 25, count 0 2006.183.07:48:12.24#ibcon#enter sib2, iclass 25, count 0 2006.183.07:48:12.24#ibcon#flushed, iclass 25, count 0 2006.183.07:48:12.24#ibcon#about to write, iclass 25, count 0 2006.183.07:48:12.24#ibcon#wrote, iclass 25, count 0 2006.183.07:48:12.24#ibcon#about to read 3, iclass 25, count 0 2006.183.07:48:12.26#ibcon#read 3, iclass 25, count 0 2006.183.07:48:12.26#ibcon#about to read 4, iclass 25, count 0 2006.183.07:48:12.26#ibcon#read 4, iclass 25, count 0 2006.183.07:48:12.26#ibcon#about to read 5, iclass 25, count 0 2006.183.07:48:12.26#ibcon#read 5, iclass 25, count 0 2006.183.07:48:12.26#ibcon#about to read 6, iclass 25, count 0 2006.183.07:48:12.26#ibcon#read 6, iclass 25, count 0 2006.183.07:48:12.26#ibcon#end of sib2, iclass 25, count 0 2006.183.07:48:12.26#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:48:12.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:48:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:48:12.26#ibcon#*before write, iclass 25, count 0 2006.183.07:48:12.26#ibcon#enter sib2, iclass 25, count 0 2006.183.07:48:12.26#ibcon#flushed, iclass 25, count 0 2006.183.07:48:12.26#ibcon#about to write, iclass 25, count 0 2006.183.07:48:12.26#ibcon#wrote, iclass 25, count 0 2006.183.07:48:12.26#ibcon#about to read 3, iclass 25, count 0 2006.183.07:48:12.30#ibcon#read 3, iclass 25, count 0 2006.183.07:48:12.30#ibcon#about to read 4, iclass 25, count 0 2006.183.07:48:12.30#ibcon#read 4, iclass 25, count 0 2006.183.07:48:12.30#ibcon#about to read 5, iclass 25, count 0 2006.183.07:48:12.30#ibcon#read 5, iclass 25, count 0 2006.183.07:48:12.30#ibcon#about to read 6, iclass 25, count 0 2006.183.07:48:12.30#ibcon#read 6, iclass 25, count 0 2006.183.07:48:12.30#ibcon#end of sib2, iclass 25, count 0 2006.183.07:48:12.30#ibcon#*after write, iclass 25, count 0 2006.183.07:48:12.30#ibcon#*before return 0, iclass 25, count 0 2006.183.07:48:12.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:12.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:48:12.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:48:12.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:48:12.30$vc4f8/vb=6,4 2006.183.07:48:12.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.07:48:12.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.07:48:12.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:48:12.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:12.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:12.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:12.36#ibcon#enter wrdev, iclass 27, count 2 2006.183.07:48:12.36#ibcon#first serial, iclass 27, count 2 2006.183.07:48:12.36#ibcon#enter sib2, iclass 27, count 2 2006.183.07:48:12.36#ibcon#flushed, iclass 27, count 2 2006.183.07:48:12.36#ibcon#about to write, iclass 27, count 2 2006.183.07:48:12.36#ibcon#wrote, iclass 27, count 2 2006.183.07:48:12.36#ibcon#about to read 3, iclass 27, count 2 2006.183.07:48:12.38#ibcon#read 3, iclass 27, count 2 2006.183.07:48:12.38#ibcon#about to read 4, iclass 27, count 2 2006.183.07:48:12.38#ibcon#read 4, iclass 27, count 2 2006.183.07:48:12.38#ibcon#about to read 5, iclass 27, count 2 2006.183.07:48:12.38#ibcon#read 5, iclass 27, count 2 2006.183.07:48:12.38#ibcon#about to read 6, iclass 27, count 2 2006.183.07:48:12.38#ibcon#read 6, iclass 27, count 2 2006.183.07:48:12.38#ibcon#end of sib2, iclass 27, count 2 2006.183.07:48:12.38#ibcon#*mode == 0, iclass 27, count 2 2006.183.07:48:12.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.07:48:12.38#ibcon#[27=AT06-04\r\n] 2006.183.07:48:12.38#ibcon#*before write, iclass 27, count 2 2006.183.07:48:12.38#ibcon#enter sib2, iclass 27, count 2 2006.183.07:48:12.38#ibcon#flushed, iclass 27, count 2 2006.183.07:48:12.38#ibcon#about to write, iclass 27, count 2 2006.183.07:48:12.38#ibcon#wrote, iclass 27, count 2 2006.183.07:48:12.38#ibcon#about to read 3, iclass 27, count 2 2006.183.07:48:12.41#ibcon#read 3, iclass 27, count 2 2006.183.07:48:12.41#ibcon#about to read 4, iclass 27, count 2 2006.183.07:48:12.41#ibcon#read 4, iclass 27, count 2 2006.183.07:48:12.41#ibcon#about to read 5, iclass 27, count 2 2006.183.07:48:12.41#ibcon#read 5, iclass 27, count 2 2006.183.07:48:12.41#ibcon#about to read 6, iclass 27, count 2 2006.183.07:48:12.41#ibcon#read 6, iclass 27, count 2 2006.183.07:48:12.41#ibcon#end of sib2, iclass 27, count 2 2006.183.07:48:12.41#ibcon#*after write, iclass 27, count 2 2006.183.07:48:12.41#ibcon#*before return 0, iclass 27, count 2 2006.183.07:48:12.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:12.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:48:12.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.07:48:12.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:48:12.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:12.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:12.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:12.53#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:48:12.53#ibcon#first serial, iclass 27, count 0 2006.183.07:48:12.53#ibcon#enter sib2, iclass 27, count 0 2006.183.07:48:12.53#ibcon#flushed, iclass 27, count 0 2006.183.07:48:12.53#ibcon#about to write, iclass 27, count 0 2006.183.07:48:12.53#ibcon#wrote, iclass 27, count 0 2006.183.07:48:12.53#ibcon#about to read 3, iclass 27, count 0 2006.183.07:48:12.55#ibcon#read 3, iclass 27, count 0 2006.183.07:48:12.55#ibcon#about to read 4, iclass 27, count 0 2006.183.07:48:12.55#ibcon#read 4, iclass 27, count 0 2006.183.07:48:12.55#ibcon#about to read 5, iclass 27, count 0 2006.183.07:48:12.55#ibcon#read 5, iclass 27, count 0 2006.183.07:48:12.55#ibcon#about to read 6, iclass 27, count 0 2006.183.07:48:12.55#ibcon#read 6, iclass 27, count 0 2006.183.07:48:12.55#ibcon#end of sib2, iclass 27, count 0 2006.183.07:48:12.55#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:48:12.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:48:12.55#ibcon#[27=USB\r\n] 2006.183.07:48:12.55#ibcon#*before write, iclass 27, count 0 2006.183.07:48:12.55#ibcon#enter sib2, iclass 27, count 0 2006.183.07:48:12.55#ibcon#flushed, iclass 27, count 0 2006.183.07:48:12.55#ibcon#about to write, iclass 27, count 0 2006.183.07:48:12.55#ibcon#wrote, iclass 27, count 0 2006.183.07:48:12.55#ibcon#about to read 3, iclass 27, count 0 2006.183.07:48:12.58#ibcon#read 3, iclass 27, count 0 2006.183.07:48:12.58#ibcon#about to read 4, iclass 27, count 0 2006.183.07:48:12.58#ibcon#read 4, iclass 27, count 0 2006.183.07:48:12.58#ibcon#about to read 5, iclass 27, count 0 2006.183.07:48:12.58#ibcon#read 5, iclass 27, count 0 2006.183.07:48:12.58#ibcon#about to read 6, iclass 27, count 0 2006.183.07:48:12.58#ibcon#read 6, iclass 27, count 0 2006.183.07:48:12.58#ibcon#end of sib2, iclass 27, count 0 2006.183.07:48:12.58#ibcon#*after write, iclass 27, count 0 2006.183.07:48:12.58#ibcon#*before return 0, iclass 27, count 0 2006.183.07:48:12.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:12.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:48:12.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:48:12.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:48:12.58$vc4f8/vabw=wide 2006.183.07:48:12.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.07:48:12.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.07:48:12.58#ibcon#ireg 8 cls_cnt 0 2006.183.07:48:12.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:12.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:12.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:12.58#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:48:12.58#ibcon#first serial, iclass 29, count 0 2006.183.07:48:12.58#ibcon#enter sib2, iclass 29, count 0 2006.183.07:48:12.58#ibcon#flushed, iclass 29, count 0 2006.183.07:48:12.58#ibcon#about to write, iclass 29, count 0 2006.183.07:48:12.58#ibcon#wrote, iclass 29, count 0 2006.183.07:48:12.58#ibcon#about to read 3, iclass 29, count 0 2006.183.07:48:12.60#ibcon#read 3, iclass 29, count 0 2006.183.07:48:12.60#ibcon#about to read 4, iclass 29, count 0 2006.183.07:48:12.60#ibcon#read 4, iclass 29, count 0 2006.183.07:48:12.60#ibcon#about to read 5, iclass 29, count 0 2006.183.07:48:12.60#ibcon#read 5, iclass 29, count 0 2006.183.07:48:12.60#ibcon#about to read 6, iclass 29, count 0 2006.183.07:48:12.60#ibcon#read 6, iclass 29, count 0 2006.183.07:48:12.60#ibcon#end of sib2, iclass 29, count 0 2006.183.07:48:12.60#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:48:12.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:48:12.60#ibcon#[25=BW32\r\n] 2006.183.07:48:12.60#ibcon#*before write, iclass 29, count 0 2006.183.07:48:12.60#ibcon#enter sib2, iclass 29, count 0 2006.183.07:48:12.60#ibcon#flushed, iclass 29, count 0 2006.183.07:48:12.60#ibcon#about to write, iclass 29, count 0 2006.183.07:48:12.60#ibcon#wrote, iclass 29, count 0 2006.183.07:48:12.60#ibcon#about to read 3, iclass 29, count 0 2006.183.07:48:12.63#ibcon#read 3, iclass 29, count 0 2006.183.07:48:12.63#ibcon#about to read 4, iclass 29, count 0 2006.183.07:48:12.63#ibcon#read 4, iclass 29, count 0 2006.183.07:48:12.63#ibcon#about to read 5, iclass 29, count 0 2006.183.07:48:12.63#ibcon#read 5, iclass 29, count 0 2006.183.07:48:12.63#ibcon#about to read 6, iclass 29, count 0 2006.183.07:48:12.63#ibcon#read 6, iclass 29, count 0 2006.183.07:48:12.63#ibcon#end of sib2, iclass 29, count 0 2006.183.07:48:12.63#ibcon#*after write, iclass 29, count 0 2006.183.07:48:12.63#ibcon#*before return 0, iclass 29, count 0 2006.183.07:48:12.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:12.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:48:12.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:48:12.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:48:12.63$vc4f8/vbbw=wide 2006.183.07:48:12.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.07:48:12.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.07:48:12.63#ibcon#ireg 8 cls_cnt 0 2006.183.07:48:12.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:48:12.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:48:12.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:48:12.70#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:48:12.70#ibcon#first serial, iclass 31, count 0 2006.183.07:48:12.70#ibcon#enter sib2, iclass 31, count 0 2006.183.07:48:12.70#ibcon#flushed, iclass 31, count 0 2006.183.07:48:12.70#ibcon#about to write, iclass 31, count 0 2006.183.07:48:12.70#ibcon#wrote, iclass 31, count 0 2006.183.07:48:12.70#ibcon#about to read 3, iclass 31, count 0 2006.183.07:48:12.72#ibcon#read 3, iclass 31, count 0 2006.183.07:48:12.72#ibcon#about to read 4, iclass 31, count 0 2006.183.07:48:12.72#ibcon#read 4, iclass 31, count 0 2006.183.07:48:12.72#ibcon#about to read 5, iclass 31, count 0 2006.183.07:48:12.72#ibcon#read 5, iclass 31, count 0 2006.183.07:48:12.72#ibcon#about to read 6, iclass 31, count 0 2006.183.07:48:12.72#ibcon#read 6, iclass 31, count 0 2006.183.07:48:12.72#ibcon#end of sib2, iclass 31, count 0 2006.183.07:48:12.72#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:48:12.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:48:12.72#ibcon#[27=BW32\r\n] 2006.183.07:48:12.72#ibcon#*before write, iclass 31, count 0 2006.183.07:48:12.72#ibcon#enter sib2, iclass 31, count 0 2006.183.07:48:12.72#ibcon#flushed, iclass 31, count 0 2006.183.07:48:12.72#ibcon#about to write, iclass 31, count 0 2006.183.07:48:12.72#ibcon#wrote, iclass 31, count 0 2006.183.07:48:12.72#ibcon#about to read 3, iclass 31, count 0 2006.183.07:48:12.75#ibcon#read 3, iclass 31, count 0 2006.183.07:48:12.75#ibcon#about to read 4, iclass 31, count 0 2006.183.07:48:12.75#ibcon#read 4, iclass 31, count 0 2006.183.07:48:12.75#ibcon#about to read 5, iclass 31, count 0 2006.183.07:48:12.75#ibcon#read 5, iclass 31, count 0 2006.183.07:48:12.75#ibcon#about to read 6, iclass 31, count 0 2006.183.07:48:12.75#ibcon#read 6, iclass 31, count 0 2006.183.07:48:12.75#ibcon#end of sib2, iclass 31, count 0 2006.183.07:48:12.75#ibcon#*after write, iclass 31, count 0 2006.183.07:48:12.75#ibcon#*before return 0, iclass 31, count 0 2006.183.07:48:12.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:48:12.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:48:12.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:48:12.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:48:12.75$4f8m12a/ifd4f 2006.183.07:48:12.75$ifd4f/lo= 2006.183.07:48:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:48:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:48:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:48:12.75$ifd4f/patch= 2006.183.07:48:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:48:12.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:48:12.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:48:12.75$4f8m12a/"form=m,16.000,1:2 2006.183.07:48:12.75$4f8m12a/"tpicd 2006.183.07:48:12.75$4f8m12a/echo=off 2006.183.07:48:12.75$4f8m12a/xlog=off 2006.183.07:48:12.75:!2006.183.07:49:20 2006.183.07:49:00.14#trakl#Source acquired 2006.183.07:49:01.14#flagr#flagr/antenna,acquired 2006.183.07:49:20.00:preob 2006.183.07:49:20.13/onsource/TRACKING 2006.183.07:49:20.13:!2006.183.07:49:30 2006.183.07:49:30.00:data_valid=on 2006.183.07:49:30.00:midob 2006.183.07:49:31.13/onsource/TRACKING 2006.183.07:49:31.13/wx/27.95,996.3,88 2006.183.07:49:31.33/cable/+6.4510E-03 2006.183.07:49:32.42/va/01,08,usb,yes,29,31 2006.183.07:49:32.42/va/02,07,usb,yes,30,31 2006.183.07:49:32.42/va/03,06,usb,yes,31,32 2006.183.07:49:32.42/va/04,07,usb,yes,31,33 2006.183.07:49:32.42/va/05,07,usb,yes,33,35 2006.183.07:49:32.42/va/06,06,usb,yes,32,32 2006.183.07:49:32.42/va/07,06,usb,yes,33,32 2006.183.07:49:32.42/va/08,07,usb,yes,31,30 2006.183.07:49:32.65/valo/01,532.99,yes,locked 2006.183.07:49:32.65/valo/02,572.99,yes,locked 2006.183.07:49:32.65/valo/03,672.99,yes,locked 2006.183.07:49:32.65/valo/04,832.99,yes,locked 2006.183.07:49:32.65/valo/05,652.99,yes,locked 2006.183.07:49:32.65/valo/06,772.99,yes,locked 2006.183.07:49:32.65/valo/07,832.99,yes,locked 2006.183.07:49:32.65/valo/08,852.99,yes,locked 2006.183.07:49:33.74/vb/01,04,usb,yes,29,28 2006.183.07:49:33.74/vb/02,04,usb,yes,31,32 2006.183.07:49:33.74/vb/03,04,usb,yes,28,31 2006.183.07:49:33.74/vb/04,04,usb,yes,28,29 2006.183.07:49:33.74/vb/05,04,usb,yes,27,31 2006.183.07:49:33.74/vb/06,04,usb,yes,28,31 2006.183.07:49:33.74/vb/07,04,usb,yes,30,30 2006.183.07:49:33.74/vb/08,04,usb,yes,28,31 2006.183.07:49:33.97/vblo/01,632.99,yes,locked 2006.183.07:49:33.97/vblo/02,640.99,yes,locked 2006.183.07:49:33.97/vblo/03,656.99,yes,locked 2006.183.07:49:33.97/vblo/04,712.99,yes,locked 2006.183.07:49:33.97/vblo/05,744.99,yes,locked 2006.183.07:49:33.97/vblo/06,752.99,yes,locked 2006.183.07:49:33.97/vblo/07,734.99,yes,locked 2006.183.07:49:33.97/vblo/08,744.99,yes,locked 2006.183.07:49:34.12/vabw/8 2006.183.07:49:34.27/vbbw/8 2006.183.07:49:34.36/xfe/off,on,15.2 2006.183.07:49:34.75/ifatt/23,28,28,28 2006.183.07:49:35.08/fmout-gps/S +3.32E-07 2006.183.07:49:35.16:!2006.183.07:50:30 2006.183.07:50:30.00:data_valid=off 2006.183.07:50:30.00:postob 2006.183.07:50:30.20/cable/+6.4510E-03 2006.183.07:50:30.20/wx/27.96,996.4,87 2006.183.07:50:31.08/fmout-gps/S +3.32E-07 2006.183.07:50:31.08:scan_name=183-0751,k06183,60 2006.183.07:50:31.09:source=1300+580,130252.47,574837.6,2000.0,cw 2006.183.07:50:31.13#flagr#flagr/antenna,new-source 2006.183.07:50:32.13:checkk5 2006.183.07:50:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:50:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:50:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:50:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:50:34.00/chk_obsdata//k5ts1/T1830749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:50:34.37/chk_obsdata//k5ts2/T1830749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:50:34.74/chk_obsdata//k5ts3/T1830749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:50:35.10/chk_obsdata//k5ts4/T1830749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:50:35.80/k5log//k5ts1_log_newline 2006.183.07:50:36.48/k5log//k5ts2_log_newline 2006.183.07:50:37.17/k5log//k5ts3_log_newline 2006.183.07:50:37.86/k5log//k5ts4_log_newline 2006.183.07:50:37.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:50:37.89:4f8m12a=1 2006.183.07:50:37.89$4f8m12a/echo=on 2006.183.07:50:37.89$4f8m12a/pcalon 2006.183.07:50:37.89$pcalon/"no phase cal control is implemented here 2006.183.07:50:37.89$4f8m12a/"tpicd=stop 2006.183.07:50:37.89$4f8m12a/vc4f8 2006.183.07:50:37.89$vc4f8/valo=1,532.99 2006.183.07:50:37.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.07:50:37.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.07:50:37.89#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:37.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:37.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:37.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:37.89#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:50:37.89#ibcon#first serial, iclass 22, count 0 2006.183.07:50:37.89#ibcon#enter sib2, iclass 22, count 0 2006.183.07:50:37.89#ibcon#flushed, iclass 22, count 0 2006.183.07:50:37.89#ibcon#about to write, iclass 22, count 0 2006.183.07:50:37.89#ibcon#wrote, iclass 22, count 0 2006.183.07:50:37.89#ibcon#about to read 3, iclass 22, count 0 2006.183.07:50:37.93#ibcon#read 3, iclass 22, count 0 2006.183.07:50:37.93#ibcon#about to read 4, iclass 22, count 0 2006.183.07:50:37.93#ibcon#read 4, iclass 22, count 0 2006.183.07:50:37.93#ibcon#about to read 5, iclass 22, count 0 2006.183.07:50:37.93#ibcon#read 5, iclass 22, count 0 2006.183.07:50:37.93#ibcon#about to read 6, iclass 22, count 0 2006.183.07:50:37.93#ibcon#read 6, iclass 22, count 0 2006.183.07:50:37.93#ibcon#end of sib2, iclass 22, count 0 2006.183.07:50:37.93#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:50:37.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:50:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:50:37.93#ibcon#*before write, iclass 22, count 0 2006.183.07:50:37.93#ibcon#enter sib2, iclass 22, count 0 2006.183.07:50:37.93#ibcon#flushed, iclass 22, count 0 2006.183.07:50:37.93#ibcon#about to write, iclass 22, count 0 2006.183.07:50:37.93#ibcon#wrote, iclass 22, count 0 2006.183.07:50:37.93#ibcon#about to read 3, iclass 22, count 0 2006.183.07:50:37.98#ibcon#read 3, iclass 22, count 0 2006.183.07:50:37.98#ibcon#about to read 4, iclass 22, count 0 2006.183.07:50:37.98#ibcon#read 4, iclass 22, count 0 2006.183.07:50:37.98#ibcon#about to read 5, iclass 22, count 0 2006.183.07:50:37.98#ibcon#read 5, iclass 22, count 0 2006.183.07:50:37.98#ibcon#about to read 6, iclass 22, count 0 2006.183.07:50:37.98#ibcon#read 6, iclass 22, count 0 2006.183.07:50:37.98#ibcon#end of sib2, iclass 22, count 0 2006.183.07:50:37.98#ibcon#*after write, iclass 22, count 0 2006.183.07:50:37.98#ibcon#*before return 0, iclass 22, count 0 2006.183.07:50:37.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:37.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:37.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:50:37.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:50:37.98$vc4f8/va=1,8 2006.183.07:50:37.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.07:50:37.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.07:50:37.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:37.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:37.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:37.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:37.98#ibcon#enter wrdev, iclass 24, count 2 2006.183.07:50:37.98#ibcon#first serial, iclass 24, count 2 2006.183.07:50:37.98#ibcon#enter sib2, iclass 24, count 2 2006.183.07:50:37.98#ibcon#flushed, iclass 24, count 2 2006.183.07:50:37.98#ibcon#about to write, iclass 24, count 2 2006.183.07:50:37.98#ibcon#wrote, iclass 24, count 2 2006.183.07:50:37.98#ibcon#about to read 3, iclass 24, count 2 2006.183.07:50:38.00#ibcon#read 3, iclass 24, count 2 2006.183.07:50:38.00#ibcon#about to read 4, iclass 24, count 2 2006.183.07:50:38.00#ibcon#read 4, iclass 24, count 2 2006.183.07:50:38.00#ibcon#about to read 5, iclass 24, count 2 2006.183.07:50:38.00#ibcon#read 5, iclass 24, count 2 2006.183.07:50:38.00#ibcon#about to read 6, iclass 24, count 2 2006.183.07:50:38.00#ibcon#read 6, iclass 24, count 2 2006.183.07:50:38.00#ibcon#end of sib2, iclass 24, count 2 2006.183.07:50:38.00#ibcon#*mode == 0, iclass 24, count 2 2006.183.07:50:38.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.07:50:38.00#ibcon#[25=AT01-08\r\n] 2006.183.07:50:38.00#ibcon#*before write, iclass 24, count 2 2006.183.07:50:38.00#ibcon#enter sib2, iclass 24, count 2 2006.183.07:50:38.00#ibcon#flushed, iclass 24, count 2 2006.183.07:50:38.00#ibcon#about to write, iclass 24, count 2 2006.183.07:50:38.00#ibcon#wrote, iclass 24, count 2 2006.183.07:50:38.00#ibcon#about to read 3, iclass 24, count 2 2006.183.07:50:38.03#ibcon#read 3, iclass 24, count 2 2006.183.07:50:38.03#ibcon#about to read 4, iclass 24, count 2 2006.183.07:50:38.03#ibcon#read 4, iclass 24, count 2 2006.183.07:50:38.03#ibcon#about to read 5, iclass 24, count 2 2006.183.07:50:38.03#ibcon#read 5, iclass 24, count 2 2006.183.07:50:38.03#ibcon#about to read 6, iclass 24, count 2 2006.183.07:50:38.03#ibcon#read 6, iclass 24, count 2 2006.183.07:50:38.03#ibcon#end of sib2, iclass 24, count 2 2006.183.07:50:38.03#ibcon#*after write, iclass 24, count 2 2006.183.07:50:38.03#ibcon#*before return 0, iclass 24, count 2 2006.183.07:50:38.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:38.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:38.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.07:50:38.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:38.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:38.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:38.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:38.15#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:50:38.15#ibcon#first serial, iclass 24, count 0 2006.183.07:50:38.15#ibcon#enter sib2, iclass 24, count 0 2006.183.07:50:38.15#ibcon#flushed, iclass 24, count 0 2006.183.07:50:38.15#ibcon#about to write, iclass 24, count 0 2006.183.07:50:38.15#ibcon#wrote, iclass 24, count 0 2006.183.07:50:38.15#ibcon#about to read 3, iclass 24, count 0 2006.183.07:50:38.17#ibcon#read 3, iclass 24, count 0 2006.183.07:50:38.17#ibcon#about to read 4, iclass 24, count 0 2006.183.07:50:38.17#ibcon#read 4, iclass 24, count 0 2006.183.07:50:38.17#ibcon#about to read 5, iclass 24, count 0 2006.183.07:50:38.17#ibcon#read 5, iclass 24, count 0 2006.183.07:50:38.17#ibcon#about to read 6, iclass 24, count 0 2006.183.07:50:38.17#ibcon#read 6, iclass 24, count 0 2006.183.07:50:38.17#ibcon#end of sib2, iclass 24, count 0 2006.183.07:50:38.17#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:50:38.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:50:38.17#ibcon#[25=USB\r\n] 2006.183.07:50:38.17#ibcon#*before write, iclass 24, count 0 2006.183.07:50:38.17#ibcon#enter sib2, iclass 24, count 0 2006.183.07:50:38.17#ibcon#flushed, iclass 24, count 0 2006.183.07:50:38.17#ibcon#about to write, iclass 24, count 0 2006.183.07:50:38.17#ibcon#wrote, iclass 24, count 0 2006.183.07:50:38.17#ibcon#about to read 3, iclass 24, count 0 2006.183.07:50:38.20#ibcon#read 3, iclass 24, count 0 2006.183.07:50:38.20#ibcon#about to read 4, iclass 24, count 0 2006.183.07:50:38.20#ibcon#read 4, iclass 24, count 0 2006.183.07:50:38.20#ibcon#about to read 5, iclass 24, count 0 2006.183.07:50:38.20#ibcon#read 5, iclass 24, count 0 2006.183.07:50:38.20#ibcon#about to read 6, iclass 24, count 0 2006.183.07:50:38.20#ibcon#read 6, iclass 24, count 0 2006.183.07:50:38.20#ibcon#end of sib2, iclass 24, count 0 2006.183.07:50:38.20#ibcon#*after write, iclass 24, count 0 2006.183.07:50:38.20#ibcon#*before return 0, iclass 24, count 0 2006.183.07:50:38.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:38.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:38.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:50:38.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:50:38.20$vc4f8/valo=2,572.99 2006.183.07:50:38.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.07:50:38.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.07:50:38.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:38.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:38.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:38.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:38.20#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:50:38.20#ibcon#first serial, iclass 26, count 0 2006.183.07:50:38.20#ibcon#enter sib2, iclass 26, count 0 2006.183.07:50:38.20#ibcon#flushed, iclass 26, count 0 2006.183.07:50:38.20#ibcon#about to write, iclass 26, count 0 2006.183.07:50:38.20#ibcon#wrote, iclass 26, count 0 2006.183.07:50:38.20#ibcon#about to read 3, iclass 26, count 0 2006.183.07:50:38.22#ibcon#read 3, iclass 26, count 0 2006.183.07:50:38.22#ibcon#about to read 4, iclass 26, count 0 2006.183.07:50:38.22#ibcon#read 4, iclass 26, count 0 2006.183.07:50:38.22#ibcon#about to read 5, iclass 26, count 0 2006.183.07:50:38.22#ibcon#read 5, iclass 26, count 0 2006.183.07:50:38.22#ibcon#about to read 6, iclass 26, count 0 2006.183.07:50:38.22#ibcon#read 6, iclass 26, count 0 2006.183.07:50:38.22#ibcon#end of sib2, iclass 26, count 0 2006.183.07:50:38.22#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:50:38.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:50:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:50:38.22#ibcon#*before write, iclass 26, count 0 2006.183.07:50:38.22#ibcon#enter sib2, iclass 26, count 0 2006.183.07:50:38.22#ibcon#flushed, iclass 26, count 0 2006.183.07:50:38.22#ibcon#about to write, iclass 26, count 0 2006.183.07:50:38.22#ibcon#wrote, iclass 26, count 0 2006.183.07:50:38.22#ibcon#about to read 3, iclass 26, count 0 2006.183.07:50:38.26#ibcon#read 3, iclass 26, count 0 2006.183.07:50:38.26#ibcon#about to read 4, iclass 26, count 0 2006.183.07:50:38.26#ibcon#read 4, iclass 26, count 0 2006.183.07:50:38.26#ibcon#about to read 5, iclass 26, count 0 2006.183.07:50:38.26#ibcon#read 5, iclass 26, count 0 2006.183.07:50:38.26#ibcon#about to read 6, iclass 26, count 0 2006.183.07:50:38.26#ibcon#read 6, iclass 26, count 0 2006.183.07:50:38.26#ibcon#end of sib2, iclass 26, count 0 2006.183.07:50:38.26#ibcon#*after write, iclass 26, count 0 2006.183.07:50:38.26#ibcon#*before return 0, iclass 26, count 0 2006.183.07:50:38.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:38.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:38.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:50:38.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:50:38.26$vc4f8/va=2,7 2006.183.07:50:38.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.07:50:38.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.07:50:38.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:38.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:38.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:38.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:38.33#ibcon#enter wrdev, iclass 28, count 2 2006.183.07:50:38.33#ibcon#first serial, iclass 28, count 2 2006.183.07:50:38.33#ibcon#enter sib2, iclass 28, count 2 2006.183.07:50:38.33#ibcon#flushed, iclass 28, count 2 2006.183.07:50:38.33#ibcon#about to write, iclass 28, count 2 2006.183.07:50:38.33#ibcon#wrote, iclass 28, count 2 2006.183.07:50:38.33#ibcon#about to read 3, iclass 28, count 2 2006.183.07:50:38.34#ibcon#read 3, iclass 28, count 2 2006.183.07:50:38.34#ibcon#about to read 4, iclass 28, count 2 2006.183.07:50:38.34#ibcon#read 4, iclass 28, count 2 2006.183.07:50:38.34#ibcon#about to read 5, iclass 28, count 2 2006.183.07:50:38.34#ibcon#read 5, iclass 28, count 2 2006.183.07:50:38.34#ibcon#about to read 6, iclass 28, count 2 2006.183.07:50:38.34#ibcon#read 6, iclass 28, count 2 2006.183.07:50:38.34#ibcon#end of sib2, iclass 28, count 2 2006.183.07:50:38.34#ibcon#*mode == 0, iclass 28, count 2 2006.183.07:50:38.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.07:50:38.34#ibcon#[25=AT02-07\r\n] 2006.183.07:50:38.34#ibcon#*before write, iclass 28, count 2 2006.183.07:50:38.34#ibcon#enter sib2, iclass 28, count 2 2006.183.07:50:38.34#ibcon#flushed, iclass 28, count 2 2006.183.07:50:38.34#ibcon#about to write, iclass 28, count 2 2006.183.07:50:38.34#ibcon#wrote, iclass 28, count 2 2006.183.07:50:38.34#ibcon#about to read 3, iclass 28, count 2 2006.183.07:50:38.37#ibcon#read 3, iclass 28, count 2 2006.183.07:50:38.37#ibcon#about to read 4, iclass 28, count 2 2006.183.07:50:38.37#ibcon#read 4, iclass 28, count 2 2006.183.07:50:38.37#ibcon#about to read 5, iclass 28, count 2 2006.183.07:50:38.37#ibcon#read 5, iclass 28, count 2 2006.183.07:50:38.37#ibcon#about to read 6, iclass 28, count 2 2006.183.07:50:38.37#ibcon#read 6, iclass 28, count 2 2006.183.07:50:38.37#ibcon#end of sib2, iclass 28, count 2 2006.183.07:50:38.37#ibcon#*after write, iclass 28, count 2 2006.183.07:50:38.37#ibcon#*before return 0, iclass 28, count 2 2006.183.07:50:38.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:38.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:38.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.07:50:38.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:38.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:38.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:38.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:38.49#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:50:38.49#ibcon#first serial, iclass 28, count 0 2006.183.07:50:38.49#ibcon#enter sib2, iclass 28, count 0 2006.183.07:50:38.49#ibcon#flushed, iclass 28, count 0 2006.183.07:50:38.49#ibcon#about to write, iclass 28, count 0 2006.183.07:50:38.49#ibcon#wrote, iclass 28, count 0 2006.183.07:50:38.49#ibcon#about to read 3, iclass 28, count 0 2006.183.07:50:38.51#ibcon#read 3, iclass 28, count 0 2006.183.07:50:38.51#ibcon#about to read 4, iclass 28, count 0 2006.183.07:50:38.51#ibcon#read 4, iclass 28, count 0 2006.183.07:50:38.51#ibcon#about to read 5, iclass 28, count 0 2006.183.07:50:38.51#ibcon#read 5, iclass 28, count 0 2006.183.07:50:38.51#ibcon#about to read 6, iclass 28, count 0 2006.183.07:50:38.51#ibcon#read 6, iclass 28, count 0 2006.183.07:50:38.51#ibcon#end of sib2, iclass 28, count 0 2006.183.07:50:38.51#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:50:38.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:50:38.51#ibcon#[25=USB\r\n] 2006.183.07:50:38.51#ibcon#*before write, iclass 28, count 0 2006.183.07:50:38.51#ibcon#enter sib2, iclass 28, count 0 2006.183.07:50:38.51#ibcon#flushed, iclass 28, count 0 2006.183.07:50:38.51#ibcon#about to write, iclass 28, count 0 2006.183.07:50:38.51#ibcon#wrote, iclass 28, count 0 2006.183.07:50:38.51#ibcon#about to read 3, iclass 28, count 0 2006.183.07:50:38.54#ibcon#read 3, iclass 28, count 0 2006.183.07:50:38.54#ibcon#about to read 4, iclass 28, count 0 2006.183.07:50:38.54#ibcon#read 4, iclass 28, count 0 2006.183.07:50:38.54#ibcon#about to read 5, iclass 28, count 0 2006.183.07:50:38.54#ibcon#read 5, iclass 28, count 0 2006.183.07:50:38.54#ibcon#about to read 6, iclass 28, count 0 2006.183.07:50:38.54#ibcon#read 6, iclass 28, count 0 2006.183.07:50:38.54#ibcon#end of sib2, iclass 28, count 0 2006.183.07:50:38.54#ibcon#*after write, iclass 28, count 0 2006.183.07:50:38.54#ibcon#*before return 0, iclass 28, count 0 2006.183.07:50:38.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:38.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:38.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:50:38.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:50:38.54$vc4f8/valo=3,672.99 2006.183.07:50:38.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.07:50:38.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.07:50:38.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:38.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:38.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:38.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:38.54#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:50:38.54#ibcon#first serial, iclass 30, count 0 2006.183.07:50:38.54#ibcon#enter sib2, iclass 30, count 0 2006.183.07:50:38.54#ibcon#flushed, iclass 30, count 0 2006.183.07:50:38.54#ibcon#about to write, iclass 30, count 0 2006.183.07:50:38.54#ibcon#wrote, iclass 30, count 0 2006.183.07:50:38.54#ibcon#about to read 3, iclass 30, count 0 2006.183.07:50:38.57#ibcon#read 3, iclass 30, count 0 2006.183.07:50:38.57#ibcon#about to read 4, iclass 30, count 0 2006.183.07:50:38.57#ibcon#read 4, iclass 30, count 0 2006.183.07:50:38.57#ibcon#about to read 5, iclass 30, count 0 2006.183.07:50:38.57#ibcon#read 5, iclass 30, count 0 2006.183.07:50:38.57#ibcon#about to read 6, iclass 30, count 0 2006.183.07:50:38.57#ibcon#read 6, iclass 30, count 0 2006.183.07:50:38.57#ibcon#end of sib2, iclass 30, count 0 2006.183.07:50:38.57#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:50:38.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:50:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:50:38.57#ibcon#*before write, iclass 30, count 0 2006.183.07:50:38.57#ibcon#enter sib2, iclass 30, count 0 2006.183.07:50:38.57#ibcon#flushed, iclass 30, count 0 2006.183.07:50:38.57#ibcon#about to write, iclass 30, count 0 2006.183.07:50:38.57#ibcon#wrote, iclass 30, count 0 2006.183.07:50:38.57#ibcon#about to read 3, iclass 30, count 0 2006.183.07:50:38.61#ibcon#read 3, iclass 30, count 0 2006.183.07:50:38.61#ibcon#about to read 4, iclass 30, count 0 2006.183.07:50:38.61#ibcon#read 4, iclass 30, count 0 2006.183.07:50:38.61#ibcon#about to read 5, iclass 30, count 0 2006.183.07:50:38.61#ibcon#read 5, iclass 30, count 0 2006.183.07:50:38.61#ibcon#about to read 6, iclass 30, count 0 2006.183.07:50:38.61#ibcon#read 6, iclass 30, count 0 2006.183.07:50:38.61#ibcon#end of sib2, iclass 30, count 0 2006.183.07:50:38.61#ibcon#*after write, iclass 30, count 0 2006.183.07:50:38.61#ibcon#*before return 0, iclass 30, count 0 2006.183.07:50:38.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:38.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:38.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:50:38.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:50:38.61$vc4f8/va=3,6 2006.183.07:50:38.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.07:50:38.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.07:50:38.61#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:38.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:38.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:38.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:38.66#ibcon#enter wrdev, iclass 32, count 2 2006.183.07:50:38.66#ibcon#first serial, iclass 32, count 2 2006.183.07:50:38.66#ibcon#enter sib2, iclass 32, count 2 2006.183.07:50:38.66#ibcon#flushed, iclass 32, count 2 2006.183.07:50:38.66#ibcon#about to write, iclass 32, count 2 2006.183.07:50:38.66#ibcon#wrote, iclass 32, count 2 2006.183.07:50:38.66#ibcon#about to read 3, iclass 32, count 2 2006.183.07:50:38.68#ibcon#read 3, iclass 32, count 2 2006.183.07:50:38.68#ibcon#about to read 4, iclass 32, count 2 2006.183.07:50:38.68#ibcon#read 4, iclass 32, count 2 2006.183.07:50:38.68#ibcon#about to read 5, iclass 32, count 2 2006.183.07:50:38.68#ibcon#read 5, iclass 32, count 2 2006.183.07:50:38.68#ibcon#about to read 6, iclass 32, count 2 2006.183.07:50:38.68#ibcon#read 6, iclass 32, count 2 2006.183.07:50:38.68#ibcon#end of sib2, iclass 32, count 2 2006.183.07:50:38.68#ibcon#*mode == 0, iclass 32, count 2 2006.183.07:50:38.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.07:50:38.68#ibcon#[25=AT03-06\r\n] 2006.183.07:50:38.68#ibcon#*before write, iclass 32, count 2 2006.183.07:50:38.68#ibcon#enter sib2, iclass 32, count 2 2006.183.07:50:38.68#ibcon#flushed, iclass 32, count 2 2006.183.07:50:38.68#ibcon#about to write, iclass 32, count 2 2006.183.07:50:38.68#ibcon#wrote, iclass 32, count 2 2006.183.07:50:38.68#ibcon#about to read 3, iclass 32, count 2 2006.183.07:50:38.71#ibcon#read 3, iclass 32, count 2 2006.183.07:50:38.71#ibcon#about to read 4, iclass 32, count 2 2006.183.07:50:38.71#ibcon#read 4, iclass 32, count 2 2006.183.07:50:38.71#ibcon#about to read 5, iclass 32, count 2 2006.183.07:50:38.71#ibcon#read 5, iclass 32, count 2 2006.183.07:50:38.71#ibcon#about to read 6, iclass 32, count 2 2006.183.07:50:38.71#ibcon#read 6, iclass 32, count 2 2006.183.07:50:38.71#ibcon#end of sib2, iclass 32, count 2 2006.183.07:50:38.71#ibcon#*after write, iclass 32, count 2 2006.183.07:50:38.71#ibcon#*before return 0, iclass 32, count 2 2006.183.07:50:38.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:38.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:38.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.07:50:38.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:38.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:38.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:38.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:38.83#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:50:38.83#ibcon#first serial, iclass 32, count 0 2006.183.07:50:38.83#ibcon#enter sib2, iclass 32, count 0 2006.183.07:50:38.83#ibcon#flushed, iclass 32, count 0 2006.183.07:50:38.83#ibcon#about to write, iclass 32, count 0 2006.183.07:50:38.83#ibcon#wrote, iclass 32, count 0 2006.183.07:50:38.83#ibcon#about to read 3, iclass 32, count 0 2006.183.07:50:38.85#ibcon#read 3, iclass 32, count 0 2006.183.07:50:38.85#ibcon#about to read 4, iclass 32, count 0 2006.183.07:50:38.85#ibcon#read 4, iclass 32, count 0 2006.183.07:50:38.85#ibcon#about to read 5, iclass 32, count 0 2006.183.07:50:38.85#ibcon#read 5, iclass 32, count 0 2006.183.07:50:38.85#ibcon#about to read 6, iclass 32, count 0 2006.183.07:50:38.85#ibcon#read 6, iclass 32, count 0 2006.183.07:50:38.85#ibcon#end of sib2, iclass 32, count 0 2006.183.07:50:38.85#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:50:38.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:50:38.85#ibcon#[25=USB\r\n] 2006.183.07:50:38.85#ibcon#*before write, iclass 32, count 0 2006.183.07:50:38.85#ibcon#enter sib2, iclass 32, count 0 2006.183.07:50:38.85#ibcon#flushed, iclass 32, count 0 2006.183.07:50:38.85#ibcon#about to write, iclass 32, count 0 2006.183.07:50:38.85#ibcon#wrote, iclass 32, count 0 2006.183.07:50:38.85#ibcon#about to read 3, iclass 32, count 0 2006.183.07:50:38.88#ibcon#read 3, iclass 32, count 0 2006.183.07:50:38.88#ibcon#about to read 4, iclass 32, count 0 2006.183.07:50:38.88#ibcon#read 4, iclass 32, count 0 2006.183.07:50:38.88#ibcon#about to read 5, iclass 32, count 0 2006.183.07:50:38.88#ibcon#read 5, iclass 32, count 0 2006.183.07:50:38.88#ibcon#about to read 6, iclass 32, count 0 2006.183.07:50:38.88#ibcon#read 6, iclass 32, count 0 2006.183.07:50:38.88#ibcon#end of sib2, iclass 32, count 0 2006.183.07:50:38.88#ibcon#*after write, iclass 32, count 0 2006.183.07:50:38.88#ibcon#*before return 0, iclass 32, count 0 2006.183.07:50:38.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:38.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:38.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:50:38.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:50:38.88$vc4f8/valo=4,832.99 2006.183.07:50:38.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.07:50:38.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.07:50:38.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:38.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:38.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:38.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:38.88#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:50:38.88#ibcon#first serial, iclass 34, count 0 2006.183.07:50:38.88#ibcon#enter sib2, iclass 34, count 0 2006.183.07:50:38.88#ibcon#flushed, iclass 34, count 0 2006.183.07:50:38.88#ibcon#about to write, iclass 34, count 0 2006.183.07:50:38.88#ibcon#wrote, iclass 34, count 0 2006.183.07:50:38.88#ibcon#about to read 3, iclass 34, count 0 2006.183.07:50:38.91#ibcon#read 3, iclass 34, count 0 2006.183.07:50:38.91#ibcon#about to read 4, iclass 34, count 0 2006.183.07:50:38.91#ibcon#read 4, iclass 34, count 0 2006.183.07:50:38.91#ibcon#about to read 5, iclass 34, count 0 2006.183.07:50:38.91#ibcon#read 5, iclass 34, count 0 2006.183.07:50:38.91#ibcon#about to read 6, iclass 34, count 0 2006.183.07:50:38.91#ibcon#read 6, iclass 34, count 0 2006.183.07:50:38.91#ibcon#end of sib2, iclass 34, count 0 2006.183.07:50:38.91#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:50:38.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:50:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:50:38.91#ibcon#*before write, iclass 34, count 0 2006.183.07:50:38.91#ibcon#enter sib2, iclass 34, count 0 2006.183.07:50:38.91#ibcon#flushed, iclass 34, count 0 2006.183.07:50:38.91#ibcon#about to write, iclass 34, count 0 2006.183.07:50:38.91#ibcon#wrote, iclass 34, count 0 2006.183.07:50:38.91#ibcon#about to read 3, iclass 34, count 0 2006.183.07:50:38.95#ibcon#read 3, iclass 34, count 0 2006.183.07:50:38.95#ibcon#about to read 4, iclass 34, count 0 2006.183.07:50:38.95#ibcon#read 4, iclass 34, count 0 2006.183.07:50:38.95#ibcon#about to read 5, iclass 34, count 0 2006.183.07:50:38.95#ibcon#read 5, iclass 34, count 0 2006.183.07:50:38.95#ibcon#about to read 6, iclass 34, count 0 2006.183.07:50:38.95#ibcon#read 6, iclass 34, count 0 2006.183.07:50:38.95#ibcon#end of sib2, iclass 34, count 0 2006.183.07:50:38.95#ibcon#*after write, iclass 34, count 0 2006.183.07:50:38.95#ibcon#*before return 0, iclass 34, count 0 2006.183.07:50:38.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:38.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:38.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:50:38.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:50:38.95$vc4f8/va=4,7 2006.183.07:50:38.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.07:50:38.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.07:50:38.95#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:38.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:39.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:39.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:39.00#ibcon#enter wrdev, iclass 36, count 2 2006.183.07:50:39.00#ibcon#first serial, iclass 36, count 2 2006.183.07:50:39.00#ibcon#enter sib2, iclass 36, count 2 2006.183.07:50:39.00#ibcon#flushed, iclass 36, count 2 2006.183.07:50:39.00#ibcon#about to write, iclass 36, count 2 2006.183.07:50:39.00#ibcon#wrote, iclass 36, count 2 2006.183.07:50:39.00#ibcon#about to read 3, iclass 36, count 2 2006.183.07:50:39.02#ibcon#read 3, iclass 36, count 2 2006.183.07:50:39.02#ibcon#about to read 4, iclass 36, count 2 2006.183.07:50:39.02#ibcon#read 4, iclass 36, count 2 2006.183.07:50:39.02#ibcon#about to read 5, iclass 36, count 2 2006.183.07:50:39.02#ibcon#read 5, iclass 36, count 2 2006.183.07:50:39.02#ibcon#about to read 6, iclass 36, count 2 2006.183.07:50:39.02#ibcon#read 6, iclass 36, count 2 2006.183.07:50:39.02#ibcon#end of sib2, iclass 36, count 2 2006.183.07:50:39.02#ibcon#*mode == 0, iclass 36, count 2 2006.183.07:50:39.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.07:50:39.02#ibcon#[25=AT04-07\r\n] 2006.183.07:50:39.02#ibcon#*before write, iclass 36, count 2 2006.183.07:50:39.02#ibcon#enter sib2, iclass 36, count 2 2006.183.07:50:39.02#ibcon#flushed, iclass 36, count 2 2006.183.07:50:39.02#ibcon#about to write, iclass 36, count 2 2006.183.07:50:39.02#ibcon#wrote, iclass 36, count 2 2006.183.07:50:39.02#ibcon#about to read 3, iclass 36, count 2 2006.183.07:50:39.05#ibcon#read 3, iclass 36, count 2 2006.183.07:50:39.05#ibcon#about to read 4, iclass 36, count 2 2006.183.07:50:39.05#ibcon#read 4, iclass 36, count 2 2006.183.07:50:39.05#ibcon#about to read 5, iclass 36, count 2 2006.183.07:50:39.05#ibcon#read 5, iclass 36, count 2 2006.183.07:50:39.05#ibcon#about to read 6, iclass 36, count 2 2006.183.07:50:39.05#ibcon#read 6, iclass 36, count 2 2006.183.07:50:39.05#ibcon#end of sib2, iclass 36, count 2 2006.183.07:50:39.05#ibcon#*after write, iclass 36, count 2 2006.183.07:50:39.05#ibcon#*before return 0, iclass 36, count 2 2006.183.07:50:39.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:39.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:39.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.07:50:39.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:39.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:39.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:39.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:39.17#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:50:39.17#ibcon#first serial, iclass 36, count 0 2006.183.07:50:39.17#ibcon#enter sib2, iclass 36, count 0 2006.183.07:50:39.17#ibcon#flushed, iclass 36, count 0 2006.183.07:50:39.17#ibcon#about to write, iclass 36, count 0 2006.183.07:50:39.17#ibcon#wrote, iclass 36, count 0 2006.183.07:50:39.17#ibcon#about to read 3, iclass 36, count 0 2006.183.07:50:39.19#ibcon#read 3, iclass 36, count 0 2006.183.07:50:39.19#ibcon#about to read 4, iclass 36, count 0 2006.183.07:50:39.19#ibcon#read 4, iclass 36, count 0 2006.183.07:50:39.19#ibcon#about to read 5, iclass 36, count 0 2006.183.07:50:39.19#ibcon#read 5, iclass 36, count 0 2006.183.07:50:39.19#ibcon#about to read 6, iclass 36, count 0 2006.183.07:50:39.19#ibcon#read 6, iclass 36, count 0 2006.183.07:50:39.19#ibcon#end of sib2, iclass 36, count 0 2006.183.07:50:39.19#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:50:39.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:50:39.19#ibcon#[25=USB\r\n] 2006.183.07:50:39.19#ibcon#*before write, iclass 36, count 0 2006.183.07:50:39.19#ibcon#enter sib2, iclass 36, count 0 2006.183.07:50:39.19#ibcon#flushed, iclass 36, count 0 2006.183.07:50:39.19#ibcon#about to write, iclass 36, count 0 2006.183.07:50:39.19#ibcon#wrote, iclass 36, count 0 2006.183.07:50:39.19#ibcon#about to read 3, iclass 36, count 0 2006.183.07:50:39.22#ibcon#read 3, iclass 36, count 0 2006.183.07:50:39.22#ibcon#about to read 4, iclass 36, count 0 2006.183.07:50:39.22#ibcon#read 4, iclass 36, count 0 2006.183.07:50:39.22#ibcon#about to read 5, iclass 36, count 0 2006.183.07:50:39.22#ibcon#read 5, iclass 36, count 0 2006.183.07:50:39.22#ibcon#about to read 6, iclass 36, count 0 2006.183.07:50:39.22#ibcon#read 6, iclass 36, count 0 2006.183.07:50:39.22#ibcon#end of sib2, iclass 36, count 0 2006.183.07:50:39.22#ibcon#*after write, iclass 36, count 0 2006.183.07:50:39.22#ibcon#*before return 0, iclass 36, count 0 2006.183.07:50:39.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:39.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:39.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:50:39.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:50:39.22$vc4f8/valo=5,652.99 2006.183.07:50:39.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.07:50:39.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.07:50:39.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:39.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:39.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:39.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:39.22#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:50:39.22#ibcon#first serial, iclass 38, count 0 2006.183.07:50:39.22#ibcon#enter sib2, iclass 38, count 0 2006.183.07:50:39.22#ibcon#flushed, iclass 38, count 0 2006.183.07:50:39.22#ibcon#about to write, iclass 38, count 0 2006.183.07:50:39.22#ibcon#wrote, iclass 38, count 0 2006.183.07:50:39.22#ibcon#about to read 3, iclass 38, count 0 2006.183.07:50:39.24#ibcon#read 3, iclass 38, count 0 2006.183.07:50:39.24#ibcon#about to read 4, iclass 38, count 0 2006.183.07:50:39.24#ibcon#read 4, iclass 38, count 0 2006.183.07:50:39.24#ibcon#about to read 5, iclass 38, count 0 2006.183.07:50:39.24#ibcon#read 5, iclass 38, count 0 2006.183.07:50:39.24#ibcon#about to read 6, iclass 38, count 0 2006.183.07:50:39.24#ibcon#read 6, iclass 38, count 0 2006.183.07:50:39.24#ibcon#end of sib2, iclass 38, count 0 2006.183.07:50:39.24#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:50:39.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:50:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:50:39.24#ibcon#*before write, iclass 38, count 0 2006.183.07:50:39.24#ibcon#enter sib2, iclass 38, count 0 2006.183.07:50:39.24#ibcon#flushed, iclass 38, count 0 2006.183.07:50:39.24#ibcon#about to write, iclass 38, count 0 2006.183.07:50:39.24#ibcon#wrote, iclass 38, count 0 2006.183.07:50:39.24#ibcon#about to read 3, iclass 38, count 0 2006.183.07:50:39.28#ibcon#read 3, iclass 38, count 0 2006.183.07:50:39.28#ibcon#about to read 4, iclass 38, count 0 2006.183.07:50:39.28#ibcon#read 4, iclass 38, count 0 2006.183.07:50:39.28#ibcon#about to read 5, iclass 38, count 0 2006.183.07:50:39.28#ibcon#read 5, iclass 38, count 0 2006.183.07:50:39.28#ibcon#about to read 6, iclass 38, count 0 2006.183.07:50:39.28#ibcon#read 6, iclass 38, count 0 2006.183.07:50:39.28#ibcon#end of sib2, iclass 38, count 0 2006.183.07:50:39.28#ibcon#*after write, iclass 38, count 0 2006.183.07:50:39.28#ibcon#*before return 0, iclass 38, count 0 2006.183.07:50:39.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:39.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:39.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:50:39.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:50:39.28$vc4f8/va=5,7 2006.183.07:50:39.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.07:50:39.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.07:50:39.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:39.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:39.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:39.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:39.34#ibcon#enter wrdev, iclass 40, count 2 2006.183.07:50:39.34#ibcon#first serial, iclass 40, count 2 2006.183.07:50:39.34#ibcon#enter sib2, iclass 40, count 2 2006.183.07:50:39.34#ibcon#flushed, iclass 40, count 2 2006.183.07:50:39.34#ibcon#about to write, iclass 40, count 2 2006.183.07:50:39.34#ibcon#wrote, iclass 40, count 2 2006.183.07:50:39.34#ibcon#about to read 3, iclass 40, count 2 2006.183.07:50:39.36#ibcon#read 3, iclass 40, count 2 2006.183.07:50:39.36#ibcon#about to read 4, iclass 40, count 2 2006.183.07:50:39.36#ibcon#read 4, iclass 40, count 2 2006.183.07:50:39.36#ibcon#about to read 5, iclass 40, count 2 2006.183.07:50:39.36#ibcon#read 5, iclass 40, count 2 2006.183.07:50:39.36#ibcon#about to read 6, iclass 40, count 2 2006.183.07:50:39.36#ibcon#read 6, iclass 40, count 2 2006.183.07:50:39.36#ibcon#end of sib2, iclass 40, count 2 2006.183.07:50:39.36#ibcon#*mode == 0, iclass 40, count 2 2006.183.07:50:39.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.07:50:39.36#ibcon#[25=AT05-07\r\n] 2006.183.07:50:39.36#ibcon#*before write, iclass 40, count 2 2006.183.07:50:39.36#ibcon#enter sib2, iclass 40, count 2 2006.183.07:50:39.36#ibcon#flushed, iclass 40, count 2 2006.183.07:50:39.36#ibcon#about to write, iclass 40, count 2 2006.183.07:50:39.36#ibcon#wrote, iclass 40, count 2 2006.183.07:50:39.36#ibcon#about to read 3, iclass 40, count 2 2006.183.07:50:39.39#ibcon#read 3, iclass 40, count 2 2006.183.07:50:39.39#ibcon#about to read 4, iclass 40, count 2 2006.183.07:50:39.39#ibcon#read 4, iclass 40, count 2 2006.183.07:50:39.39#ibcon#about to read 5, iclass 40, count 2 2006.183.07:50:39.39#ibcon#read 5, iclass 40, count 2 2006.183.07:50:39.39#ibcon#about to read 6, iclass 40, count 2 2006.183.07:50:39.39#ibcon#read 6, iclass 40, count 2 2006.183.07:50:39.39#ibcon#end of sib2, iclass 40, count 2 2006.183.07:50:39.39#ibcon#*after write, iclass 40, count 2 2006.183.07:50:39.39#ibcon#*before return 0, iclass 40, count 2 2006.183.07:50:39.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:39.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:39.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.07:50:39.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:39.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:39.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:39.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:39.51#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:50:39.51#ibcon#first serial, iclass 40, count 0 2006.183.07:50:39.51#ibcon#enter sib2, iclass 40, count 0 2006.183.07:50:39.51#ibcon#flushed, iclass 40, count 0 2006.183.07:50:39.51#ibcon#about to write, iclass 40, count 0 2006.183.07:50:39.51#ibcon#wrote, iclass 40, count 0 2006.183.07:50:39.51#ibcon#about to read 3, iclass 40, count 0 2006.183.07:50:39.53#ibcon#read 3, iclass 40, count 0 2006.183.07:50:39.53#ibcon#about to read 4, iclass 40, count 0 2006.183.07:50:39.53#ibcon#read 4, iclass 40, count 0 2006.183.07:50:39.53#ibcon#about to read 5, iclass 40, count 0 2006.183.07:50:39.53#ibcon#read 5, iclass 40, count 0 2006.183.07:50:39.53#ibcon#about to read 6, iclass 40, count 0 2006.183.07:50:39.53#ibcon#read 6, iclass 40, count 0 2006.183.07:50:39.53#ibcon#end of sib2, iclass 40, count 0 2006.183.07:50:39.53#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:50:39.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:50:39.53#ibcon#[25=USB\r\n] 2006.183.07:50:39.53#ibcon#*before write, iclass 40, count 0 2006.183.07:50:39.53#ibcon#enter sib2, iclass 40, count 0 2006.183.07:50:39.53#ibcon#flushed, iclass 40, count 0 2006.183.07:50:39.53#ibcon#about to write, iclass 40, count 0 2006.183.07:50:39.53#ibcon#wrote, iclass 40, count 0 2006.183.07:50:39.53#ibcon#about to read 3, iclass 40, count 0 2006.183.07:50:39.56#ibcon#read 3, iclass 40, count 0 2006.183.07:50:39.56#ibcon#about to read 4, iclass 40, count 0 2006.183.07:50:39.56#ibcon#read 4, iclass 40, count 0 2006.183.07:50:39.56#ibcon#about to read 5, iclass 40, count 0 2006.183.07:50:39.56#ibcon#read 5, iclass 40, count 0 2006.183.07:50:39.56#ibcon#about to read 6, iclass 40, count 0 2006.183.07:50:39.56#ibcon#read 6, iclass 40, count 0 2006.183.07:50:39.56#ibcon#end of sib2, iclass 40, count 0 2006.183.07:50:39.56#ibcon#*after write, iclass 40, count 0 2006.183.07:50:39.56#ibcon#*before return 0, iclass 40, count 0 2006.183.07:50:39.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:39.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:39.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:50:39.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:50:39.56$vc4f8/valo=6,772.99 2006.183.07:50:39.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.07:50:39.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.07:50:39.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:39.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:39.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:39.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:39.56#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:50:39.56#ibcon#first serial, iclass 4, count 0 2006.183.07:50:39.56#ibcon#enter sib2, iclass 4, count 0 2006.183.07:50:39.56#ibcon#flushed, iclass 4, count 0 2006.183.07:50:39.56#ibcon#about to write, iclass 4, count 0 2006.183.07:50:39.56#ibcon#wrote, iclass 4, count 0 2006.183.07:50:39.56#ibcon#about to read 3, iclass 4, count 0 2006.183.07:50:39.59#ibcon#read 3, iclass 4, count 0 2006.183.07:50:39.59#ibcon#about to read 4, iclass 4, count 0 2006.183.07:50:39.59#ibcon#read 4, iclass 4, count 0 2006.183.07:50:39.59#ibcon#about to read 5, iclass 4, count 0 2006.183.07:50:39.59#ibcon#read 5, iclass 4, count 0 2006.183.07:50:39.59#ibcon#about to read 6, iclass 4, count 0 2006.183.07:50:39.59#ibcon#read 6, iclass 4, count 0 2006.183.07:50:39.59#ibcon#end of sib2, iclass 4, count 0 2006.183.07:50:39.59#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:50:39.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:50:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:50:39.59#ibcon#*before write, iclass 4, count 0 2006.183.07:50:39.59#ibcon#enter sib2, iclass 4, count 0 2006.183.07:50:39.59#ibcon#flushed, iclass 4, count 0 2006.183.07:50:39.59#ibcon#about to write, iclass 4, count 0 2006.183.07:50:39.59#ibcon#wrote, iclass 4, count 0 2006.183.07:50:39.59#ibcon#about to read 3, iclass 4, count 0 2006.183.07:50:39.63#ibcon#read 3, iclass 4, count 0 2006.183.07:50:39.63#ibcon#about to read 4, iclass 4, count 0 2006.183.07:50:39.63#ibcon#read 4, iclass 4, count 0 2006.183.07:50:39.63#ibcon#about to read 5, iclass 4, count 0 2006.183.07:50:39.63#ibcon#read 5, iclass 4, count 0 2006.183.07:50:39.63#ibcon#about to read 6, iclass 4, count 0 2006.183.07:50:39.63#ibcon#read 6, iclass 4, count 0 2006.183.07:50:39.63#ibcon#end of sib2, iclass 4, count 0 2006.183.07:50:39.63#ibcon#*after write, iclass 4, count 0 2006.183.07:50:39.63#ibcon#*before return 0, iclass 4, count 0 2006.183.07:50:39.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:39.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:39.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:50:39.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:50:39.63$vc4f8/va=6,6 2006.183.07:50:39.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.07:50:39.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.07:50:39.63#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:39.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:50:39.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:50:39.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:50:39.68#ibcon#enter wrdev, iclass 6, count 2 2006.183.07:50:39.68#ibcon#first serial, iclass 6, count 2 2006.183.07:50:39.68#ibcon#enter sib2, iclass 6, count 2 2006.183.07:50:39.68#ibcon#flushed, iclass 6, count 2 2006.183.07:50:39.68#ibcon#about to write, iclass 6, count 2 2006.183.07:50:39.68#ibcon#wrote, iclass 6, count 2 2006.183.07:50:39.68#ibcon#about to read 3, iclass 6, count 2 2006.183.07:50:39.70#ibcon#read 3, iclass 6, count 2 2006.183.07:50:39.70#ibcon#about to read 4, iclass 6, count 2 2006.183.07:50:39.70#ibcon#read 4, iclass 6, count 2 2006.183.07:50:39.70#ibcon#about to read 5, iclass 6, count 2 2006.183.07:50:39.70#ibcon#read 5, iclass 6, count 2 2006.183.07:50:39.70#ibcon#about to read 6, iclass 6, count 2 2006.183.07:50:39.70#ibcon#read 6, iclass 6, count 2 2006.183.07:50:39.70#ibcon#end of sib2, iclass 6, count 2 2006.183.07:50:39.70#ibcon#*mode == 0, iclass 6, count 2 2006.183.07:50:39.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.07:50:39.70#ibcon#[25=AT06-06\r\n] 2006.183.07:50:39.70#ibcon#*before write, iclass 6, count 2 2006.183.07:50:39.70#ibcon#enter sib2, iclass 6, count 2 2006.183.07:50:39.70#ibcon#flushed, iclass 6, count 2 2006.183.07:50:39.70#ibcon#about to write, iclass 6, count 2 2006.183.07:50:39.70#ibcon#wrote, iclass 6, count 2 2006.183.07:50:39.70#ibcon#about to read 3, iclass 6, count 2 2006.183.07:50:39.73#ibcon#read 3, iclass 6, count 2 2006.183.07:50:39.73#ibcon#about to read 4, iclass 6, count 2 2006.183.07:50:39.73#ibcon#read 4, iclass 6, count 2 2006.183.07:50:39.73#ibcon#about to read 5, iclass 6, count 2 2006.183.07:50:39.73#ibcon#read 5, iclass 6, count 2 2006.183.07:50:39.73#ibcon#about to read 6, iclass 6, count 2 2006.183.07:50:39.73#ibcon#read 6, iclass 6, count 2 2006.183.07:50:39.73#ibcon#end of sib2, iclass 6, count 2 2006.183.07:50:39.73#ibcon#*after write, iclass 6, count 2 2006.183.07:50:39.73#ibcon#*before return 0, iclass 6, count 2 2006.183.07:50:39.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:50:39.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.07:50:39.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.07:50:39.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:39.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:50:39.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:50:39.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:50:39.85#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:50:39.85#ibcon#first serial, iclass 6, count 0 2006.183.07:50:39.85#ibcon#enter sib2, iclass 6, count 0 2006.183.07:50:39.85#ibcon#flushed, iclass 6, count 0 2006.183.07:50:39.85#ibcon#about to write, iclass 6, count 0 2006.183.07:50:39.85#ibcon#wrote, iclass 6, count 0 2006.183.07:50:39.85#ibcon#about to read 3, iclass 6, count 0 2006.183.07:50:39.87#ibcon#read 3, iclass 6, count 0 2006.183.07:50:39.87#ibcon#about to read 4, iclass 6, count 0 2006.183.07:50:39.87#ibcon#read 4, iclass 6, count 0 2006.183.07:50:39.87#ibcon#about to read 5, iclass 6, count 0 2006.183.07:50:39.87#ibcon#read 5, iclass 6, count 0 2006.183.07:50:39.87#ibcon#about to read 6, iclass 6, count 0 2006.183.07:50:39.87#ibcon#read 6, iclass 6, count 0 2006.183.07:50:39.87#ibcon#end of sib2, iclass 6, count 0 2006.183.07:50:39.87#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:50:39.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:50:39.87#ibcon#[25=USB\r\n] 2006.183.07:50:39.87#ibcon#*before write, iclass 6, count 0 2006.183.07:50:39.87#ibcon#enter sib2, iclass 6, count 0 2006.183.07:50:39.87#ibcon#flushed, iclass 6, count 0 2006.183.07:50:39.87#ibcon#about to write, iclass 6, count 0 2006.183.07:50:39.87#ibcon#wrote, iclass 6, count 0 2006.183.07:50:39.87#ibcon#about to read 3, iclass 6, count 0 2006.183.07:50:39.90#ibcon#read 3, iclass 6, count 0 2006.183.07:50:39.90#ibcon#about to read 4, iclass 6, count 0 2006.183.07:50:39.90#ibcon#read 4, iclass 6, count 0 2006.183.07:50:39.90#ibcon#about to read 5, iclass 6, count 0 2006.183.07:50:39.90#ibcon#read 5, iclass 6, count 0 2006.183.07:50:39.90#ibcon#about to read 6, iclass 6, count 0 2006.183.07:50:39.90#ibcon#read 6, iclass 6, count 0 2006.183.07:50:39.90#ibcon#end of sib2, iclass 6, count 0 2006.183.07:50:39.90#ibcon#*after write, iclass 6, count 0 2006.183.07:50:39.90#ibcon#*before return 0, iclass 6, count 0 2006.183.07:50:39.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:50:39.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.07:50:39.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:50:39.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:50:39.90$vc4f8/valo=7,832.99 2006.183.07:50:39.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.07:50:39.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.07:50:39.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:39.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:50:39.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:50:39.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:50:39.90#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:50:39.90#ibcon#first serial, iclass 10, count 0 2006.183.07:50:39.90#ibcon#enter sib2, iclass 10, count 0 2006.183.07:50:39.90#ibcon#flushed, iclass 10, count 0 2006.183.07:50:39.90#ibcon#about to write, iclass 10, count 0 2006.183.07:50:39.90#ibcon#wrote, iclass 10, count 0 2006.183.07:50:39.90#ibcon#about to read 3, iclass 10, count 0 2006.183.07:50:39.92#ibcon#read 3, iclass 10, count 0 2006.183.07:50:39.92#ibcon#about to read 4, iclass 10, count 0 2006.183.07:50:39.92#ibcon#read 4, iclass 10, count 0 2006.183.07:50:39.92#ibcon#about to read 5, iclass 10, count 0 2006.183.07:50:39.92#ibcon#read 5, iclass 10, count 0 2006.183.07:50:39.92#ibcon#about to read 6, iclass 10, count 0 2006.183.07:50:39.92#ibcon#read 6, iclass 10, count 0 2006.183.07:50:39.92#ibcon#end of sib2, iclass 10, count 0 2006.183.07:50:39.92#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:50:39.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:50:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:50:39.92#ibcon#*before write, iclass 10, count 0 2006.183.07:50:39.92#ibcon#enter sib2, iclass 10, count 0 2006.183.07:50:39.92#ibcon#flushed, iclass 10, count 0 2006.183.07:50:39.92#ibcon#about to write, iclass 10, count 0 2006.183.07:50:39.92#ibcon#wrote, iclass 10, count 0 2006.183.07:50:39.92#ibcon#about to read 3, iclass 10, count 0 2006.183.07:50:39.96#ibcon#read 3, iclass 10, count 0 2006.183.07:50:39.96#ibcon#about to read 4, iclass 10, count 0 2006.183.07:50:39.96#ibcon#read 4, iclass 10, count 0 2006.183.07:50:39.96#ibcon#about to read 5, iclass 10, count 0 2006.183.07:50:39.96#ibcon#read 5, iclass 10, count 0 2006.183.07:50:39.96#ibcon#about to read 6, iclass 10, count 0 2006.183.07:50:39.96#ibcon#read 6, iclass 10, count 0 2006.183.07:50:39.96#ibcon#end of sib2, iclass 10, count 0 2006.183.07:50:39.96#ibcon#*after write, iclass 10, count 0 2006.183.07:50:39.96#ibcon#*before return 0, iclass 10, count 0 2006.183.07:50:39.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:50:39.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.07:50:39.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:50:39.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:50:39.96$vc4f8/va=7,6 2006.183.07:50:39.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.07:50:39.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.07:50:39.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:39.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:50:40.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:50:40.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:50:40.02#ibcon#enter wrdev, iclass 12, count 2 2006.183.07:50:40.02#ibcon#first serial, iclass 12, count 2 2006.183.07:50:40.02#ibcon#enter sib2, iclass 12, count 2 2006.183.07:50:40.02#ibcon#flushed, iclass 12, count 2 2006.183.07:50:40.02#ibcon#about to write, iclass 12, count 2 2006.183.07:50:40.02#ibcon#wrote, iclass 12, count 2 2006.183.07:50:40.02#ibcon#about to read 3, iclass 12, count 2 2006.183.07:50:40.04#ibcon#read 3, iclass 12, count 2 2006.183.07:50:40.04#ibcon#about to read 4, iclass 12, count 2 2006.183.07:50:40.04#ibcon#read 4, iclass 12, count 2 2006.183.07:50:40.04#ibcon#about to read 5, iclass 12, count 2 2006.183.07:50:40.04#ibcon#read 5, iclass 12, count 2 2006.183.07:50:40.04#ibcon#about to read 6, iclass 12, count 2 2006.183.07:50:40.04#ibcon#read 6, iclass 12, count 2 2006.183.07:50:40.04#ibcon#end of sib2, iclass 12, count 2 2006.183.07:50:40.04#ibcon#*mode == 0, iclass 12, count 2 2006.183.07:50:40.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.07:50:40.04#ibcon#[25=AT07-06\r\n] 2006.183.07:50:40.04#ibcon#*before write, iclass 12, count 2 2006.183.07:50:40.04#ibcon#enter sib2, iclass 12, count 2 2006.183.07:50:40.04#ibcon#flushed, iclass 12, count 2 2006.183.07:50:40.04#ibcon#about to write, iclass 12, count 2 2006.183.07:50:40.04#ibcon#wrote, iclass 12, count 2 2006.183.07:50:40.04#ibcon#about to read 3, iclass 12, count 2 2006.183.07:50:40.07#ibcon#read 3, iclass 12, count 2 2006.183.07:50:40.07#ibcon#about to read 4, iclass 12, count 2 2006.183.07:50:40.07#ibcon#read 4, iclass 12, count 2 2006.183.07:50:40.07#ibcon#about to read 5, iclass 12, count 2 2006.183.07:50:40.07#ibcon#read 5, iclass 12, count 2 2006.183.07:50:40.07#ibcon#about to read 6, iclass 12, count 2 2006.183.07:50:40.07#ibcon#read 6, iclass 12, count 2 2006.183.07:50:40.07#ibcon#end of sib2, iclass 12, count 2 2006.183.07:50:40.07#ibcon#*after write, iclass 12, count 2 2006.183.07:50:40.07#ibcon#*before return 0, iclass 12, count 2 2006.183.07:50:40.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:50:40.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.07:50:40.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.07:50:40.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:40.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:50:40.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:50:40.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:50:40.19#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:50:40.19#ibcon#first serial, iclass 12, count 0 2006.183.07:50:40.19#ibcon#enter sib2, iclass 12, count 0 2006.183.07:50:40.19#ibcon#flushed, iclass 12, count 0 2006.183.07:50:40.19#ibcon#about to write, iclass 12, count 0 2006.183.07:50:40.19#ibcon#wrote, iclass 12, count 0 2006.183.07:50:40.19#ibcon#about to read 3, iclass 12, count 0 2006.183.07:50:40.21#ibcon#read 3, iclass 12, count 0 2006.183.07:50:40.21#ibcon#about to read 4, iclass 12, count 0 2006.183.07:50:40.21#ibcon#read 4, iclass 12, count 0 2006.183.07:50:40.21#ibcon#about to read 5, iclass 12, count 0 2006.183.07:50:40.21#ibcon#read 5, iclass 12, count 0 2006.183.07:50:40.21#ibcon#about to read 6, iclass 12, count 0 2006.183.07:50:40.21#ibcon#read 6, iclass 12, count 0 2006.183.07:50:40.21#ibcon#end of sib2, iclass 12, count 0 2006.183.07:50:40.21#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:50:40.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:50:40.21#ibcon#[25=USB\r\n] 2006.183.07:50:40.21#ibcon#*before write, iclass 12, count 0 2006.183.07:50:40.21#ibcon#enter sib2, iclass 12, count 0 2006.183.07:50:40.21#ibcon#flushed, iclass 12, count 0 2006.183.07:50:40.21#ibcon#about to write, iclass 12, count 0 2006.183.07:50:40.21#ibcon#wrote, iclass 12, count 0 2006.183.07:50:40.21#ibcon#about to read 3, iclass 12, count 0 2006.183.07:50:40.24#ibcon#read 3, iclass 12, count 0 2006.183.07:50:40.24#ibcon#about to read 4, iclass 12, count 0 2006.183.07:50:40.24#ibcon#read 4, iclass 12, count 0 2006.183.07:50:40.24#ibcon#about to read 5, iclass 12, count 0 2006.183.07:50:40.24#ibcon#read 5, iclass 12, count 0 2006.183.07:50:40.24#ibcon#about to read 6, iclass 12, count 0 2006.183.07:50:40.24#ibcon#read 6, iclass 12, count 0 2006.183.07:50:40.24#ibcon#end of sib2, iclass 12, count 0 2006.183.07:50:40.24#ibcon#*after write, iclass 12, count 0 2006.183.07:50:40.24#ibcon#*before return 0, iclass 12, count 0 2006.183.07:50:40.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:50:40.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.07:50:40.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:50:40.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:50:40.24$vc4f8/valo=8,852.99 2006.183.07:50:40.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.07:50:40.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.07:50:40.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:40.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:50:40.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:50:40.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:50:40.24#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:50:40.24#ibcon#first serial, iclass 14, count 0 2006.183.07:50:40.24#ibcon#enter sib2, iclass 14, count 0 2006.183.07:50:40.24#ibcon#flushed, iclass 14, count 0 2006.183.07:50:40.24#ibcon#about to write, iclass 14, count 0 2006.183.07:50:40.24#ibcon#wrote, iclass 14, count 0 2006.183.07:50:40.24#ibcon#about to read 3, iclass 14, count 0 2006.183.07:50:40.26#ibcon#read 3, iclass 14, count 0 2006.183.07:50:40.26#ibcon#about to read 4, iclass 14, count 0 2006.183.07:50:40.26#ibcon#read 4, iclass 14, count 0 2006.183.07:50:40.26#ibcon#about to read 5, iclass 14, count 0 2006.183.07:50:40.26#ibcon#read 5, iclass 14, count 0 2006.183.07:50:40.26#ibcon#about to read 6, iclass 14, count 0 2006.183.07:50:40.26#ibcon#read 6, iclass 14, count 0 2006.183.07:50:40.26#ibcon#end of sib2, iclass 14, count 0 2006.183.07:50:40.26#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:50:40.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:50:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:50:40.26#ibcon#*before write, iclass 14, count 0 2006.183.07:50:40.26#ibcon#enter sib2, iclass 14, count 0 2006.183.07:50:40.26#ibcon#flushed, iclass 14, count 0 2006.183.07:50:40.26#ibcon#about to write, iclass 14, count 0 2006.183.07:50:40.26#ibcon#wrote, iclass 14, count 0 2006.183.07:50:40.26#ibcon#about to read 3, iclass 14, count 0 2006.183.07:50:40.30#ibcon#read 3, iclass 14, count 0 2006.183.07:50:40.30#ibcon#about to read 4, iclass 14, count 0 2006.183.07:50:40.30#ibcon#read 4, iclass 14, count 0 2006.183.07:50:40.30#ibcon#about to read 5, iclass 14, count 0 2006.183.07:50:40.30#ibcon#read 5, iclass 14, count 0 2006.183.07:50:40.30#ibcon#about to read 6, iclass 14, count 0 2006.183.07:50:40.30#ibcon#read 6, iclass 14, count 0 2006.183.07:50:40.30#ibcon#end of sib2, iclass 14, count 0 2006.183.07:50:40.30#ibcon#*after write, iclass 14, count 0 2006.183.07:50:40.30#ibcon#*before return 0, iclass 14, count 0 2006.183.07:50:40.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:50:40.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.07:50:40.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:50:40.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:50:40.30$vc4f8/va=8,7 2006.183.07:50:40.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.07:50:40.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.07:50:40.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:40.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:50:40.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:50:40.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:50:40.36#ibcon#enter wrdev, iclass 16, count 2 2006.183.07:50:40.36#ibcon#first serial, iclass 16, count 2 2006.183.07:50:40.36#ibcon#enter sib2, iclass 16, count 2 2006.183.07:50:40.36#ibcon#flushed, iclass 16, count 2 2006.183.07:50:40.36#ibcon#about to write, iclass 16, count 2 2006.183.07:50:40.36#ibcon#wrote, iclass 16, count 2 2006.183.07:50:40.36#ibcon#about to read 3, iclass 16, count 2 2006.183.07:50:40.38#ibcon#read 3, iclass 16, count 2 2006.183.07:50:40.38#ibcon#about to read 4, iclass 16, count 2 2006.183.07:50:40.38#ibcon#read 4, iclass 16, count 2 2006.183.07:50:40.38#ibcon#about to read 5, iclass 16, count 2 2006.183.07:50:40.38#ibcon#read 5, iclass 16, count 2 2006.183.07:50:40.38#ibcon#about to read 6, iclass 16, count 2 2006.183.07:50:40.38#ibcon#read 6, iclass 16, count 2 2006.183.07:50:40.38#ibcon#end of sib2, iclass 16, count 2 2006.183.07:50:40.38#ibcon#*mode == 0, iclass 16, count 2 2006.183.07:50:40.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.07:50:40.38#ibcon#[25=AT08-07\r\n] 2006.183.07:50:40.38#ibcon#*before write, iclass 16, count 2 2006.183.07:50:40.38#ibcon#enter sib2, iclass 16, count 2 2006.183.07:50:40.38#ibcon#flushed, iclass 16, count 2 2006.183.07:50:40.38#ibcon#about to write, iclass 16, count 2 2006.183.07:50:40.38#ibcon#wrote, iclass 16, count 2 2006.183.07:50:40.38#ibcon#about to read 3, iclass 16, count 2 2006.183.07:50:40.41#ibcon#read 3, iclass 16, count 2 2006.183.07:50:40.41#ibcon#about to read 4, iclass 16, count 2 2006.183.07:50:40.41#ibcon#read 4, iclass 16, count 2 2006.183.07:50:40.41#ibcon#about to read 5, iclass 16, count 2 2006.183.07:50:40.41#ibcon#read 5, iclass 16, count 2 2006.183.07:50:40.41#ibcon#about to read 6, iclass 16, count 2 2006.183.07:50:40.41#ibcon#read 6, iclass 16, count 2 2006.183.07:50:40.41#ibcon#end of sib2, iclass 16, count 2 2006.183.07:50:40.41#ibcon#*after write, iclass 16, count 2 2006.183.07:50:40.41#ibcon#*before return 0, iclass 16, count 2 2006.183.07:50:40.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:50:40.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.07:50:40.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.07:50:40.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:40.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:50:40.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:50:40.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:50:40.53#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:50:40.53#ibcon#first serial, iclass 16, count 0 2006.183.07:50:40.53#ibcon#enter sib2, iclass 16, count 0 2006.183.07:50:40.53#ibcon#flushed, iclass 16, count 0 2006.183.07:50:40.53#ibcon#about to write, iclass 16, count 0 2006.183.07:50:40.53#ibcon#wrote, iclass 16, count 0 2006.183.07:50:40.53#ibcon#about to read 3, iclass 16, count 0 2006.183.07:50:40.55#ibcon#read 3, iclass 16, count 0 2006.183.07:50:40.55#ibcon#about to read 4, iclass 16, count 0 2006.183.07:50:40.55#ibcon#read 4, iclass 16, count 0 2006.183.07:50:40.55#ibcon#about to read 5, iclass 16, count 0 2006.183.07:50:40.55#ibcon#read 5, iclass 16, count 0 2006.183.07:50:40.55#ibcon#about to read 6, iclass 16, count 0 2006.183.07:50:40.55#ibcon#read 6, iclass 16, count 0 2006.183.07:50:40.55#ibcon#end of sib2, iclass 16, count 0 2006.183.07:50:40.55#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:50:40.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:50:40.55#ibcon#[25=USB\r\n] 2006.183.07:50:40.55#ibcon#*before write, iclass 16, count 0 2006.183.07:50:40.55#ibcon#enter sib2, iclass 16, count 0 2006.183.07:50:40.55#ibcon#flushed, iclass 16, count 0 2006.183.07:50:40.55#ibcon#about to write, iclass 16, count 0 2006.183.07:50:40.55#ibcon#wrote, iclass 16, count 0 2006.183.07:50:40.55#ibcon#about to read 3, iclass 16, count 0 2006.183.07:50:40.58#ibcon#read 3, iclass 16, count 0 2006.183.07:50:40.58#ibcon#about to read 4, iclass 16, count 0 2006.183.07:50:40.58#ibcon#read 4, iclass 16, count 0 2006.183.07:50:40.58#ibcon#about to read 5, iclass 16, count 0 2006.183.07:50:40.58#ibcon#read 5, iclass 16, count 0 2006.183.07:50:40.58#ibcon#about to read 6, iclass 16, count 0 2006.183.07:50:40.58#ibcon#read 6, iclass 16, count 0 2006.183.07:50:40.58#ibcon#end of sib2, iclass 16, count 0 2006.183.07:50:40.58#ibcon#*after write, iclass 16, count 0 2006.183.07:50:40.58#ibcon#*before return 0, iclass 16, count 0 2006.183.07:50:40.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:50:40.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.07:50:40.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:50:40.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:50:40.58$vc4f8/vblo=1,632.99 2006.183.07:50:40.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.07:50:40.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.07:50:40.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:40.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:50:40.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:50:40.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:50:40.58#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:50:40.58#ibcon#first serial, iclass 18, count 0 2006.183.07:50:40.58#ibcon#enter sib2, iclass 18, count 0 2006.183.07:50:40.58#ibcon#flushed, iclass 18, count 0 2006.183.07:50:40.58#ibcon#about to write, iclass 18, count 0 2006.183.07:50:40.58#ibcon#wrote, iclass 18, count 0 2006.183.07:50:40.58#ibcon#about to read 3, iclass 18, count 0 2006.183.07:50:40.60#ibcon#read 3, iclass 18, count 0 2006.183.07:50:40.60#ibcon#about to read 4, iclass 18, count 0 2006.183.07:50:40.60#ibcon#read 4, iclass 18, count 0 2006.183.07:50:40.60#ibcon#about to read 5, iclass 18, count 0 2006.183.07:50:40.60#ibcon#read 5, iclass 18, count 0 2006.183.07:50:40.60#ibcon#about to read 6, iclass 18, count 0 2006.183.07:50:40.60#ibcon#read 6, iclass 18, count 0 2006.183.07:50:40.60#ibcon#end of sib2, iclass 18, count 0 2006.183.07:50:40.60#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:50:40.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:50:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:50:40.60#ibcon#*before write, iclass 18, count 0 2006.183.07:50:40.60#ibcon#enter sib2, iclass 18, count 0 2006.183.07:50:40.60#ibcon#flushed, iclass 18, count 0 2006.183.07:50:40.60#ibcon#about to write, iclass 18, count 0 2006.183.07:50:40.60#ibcon#wrote, iclass 18, count 0 2006.183.07:50:40.60#ibcon#about to read 3, iclass 18, count 0 2006.183.07:50:40.64#ibcon#read 3, iclass 18, count 0 2006.183.07:50:40.64#ibcon#about to read 4, iclass 18, count 0 2006.183.07:50:40.64#ibcon#read 4, iclass 18, count 0 2006.183.07:50:40.64#ibcon#about to read 5, iclass 18, count 0 2006.183.07:50:40.64#ibcon#read 5, iclass 18, count 0 2006.183.07:50:40.64#ibcon#about to read 6, iclass 18, count 0 2006.183.07:50:40.64#ibcon#read 6, iclass 18, count 0 2006.183.07:50:40.64#ibcon#end of sib2, iclass 18, count 0 2006.183.07:50:40.64#ibcon#*after write, iclass 18, count 0 2006.183.07:50:40.64#ibcon#*before return 0, iclass 18, count 0 2006.183.07:50:40.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:50:40.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.07:50:40.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:50:40.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:50:40.64$vc4f8/vb=1,4 2006.183.07:50:40.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.07:50:40.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.07:50:40.64#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:40.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:50:40.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:50:40.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:50:40.64#ibcon#enter wrdev, iclass 20, count 2 2006.183.07:50:40.64#ibcon#first serial, iclass 20, count 2 2006.183.07:50:40.64#ibcon#enter sib2, iclass 20, count 2 2006.183.07:50:40.64#ibcon#flushed, iclass 20, count 2 2006.183.07:50:40.64#ibcon#about to write, iclass 20, count 2 2006.183.07:50:40.64#ibcon#wrote, iclass 20, count 2 2006.183.07:50:40.64#ibcon#about to read 3, iclass 20, count 2 2006.183.07:50:40.66#ibcon#read 3, iclass 20, count 2 2006.183.07:50:40.66#ibcon#about to read 4, iclass 20, count 2 2006.183.07:50:40.66#ibcon#read 4, iclass 20, count 2 2006.183.07:50:40.66#ibcon#about to read 5, iclass 20, count 2 2006.183.07:50:40.66#ibcon#read 5, iclass 20, count 2 2006.183.07:50:40.66#ibcon#about to read 6, iclass 20, count 2 2006.183.07:50:40.66#ibcon#read 6, iclass 20, count 2 2006.183.07:50:40.66#ibcon#end of sib2, iclass 20, count 2 2006.183.07:50:40.66#ibcon#*mode == 0, iclass 20, count 2 2006.183.07:50:40.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.07:50:40.66#ibcon#[27=AT01-04\r\n] 2006.183.07:50:40.66#ibcon#*before write, iclass 20, count 2 2006.183.07:50:40.66#ibcon#enter sib2, iclass 20, count 2 2006.183.07:50:40.66#ibcon#flushed, iclass 20, count 2 2006.183.07:50:40.66#ibcon#about to write, iclass 20, count 2 2006.183.07:50:40.66#ibcon#wrote, iclass 20, count 2 2006.183.07:50:40.66#ibcon#about to read 3, iclass 20, count 2 2006.183.07:50:40.69#ibcon#read 3, iclass 20, count 2 2006.183.07:50:40.69#ibcon#about to read 4, iclass 20, count 2 2006.183.07:50:40.69#ibcon#read 4, iclass 20, count 2 2006.183.07:50:40.69#ibcon#about to read 5, iclass 20, count 2 2006.183.07:50:40.69#ibcon#read 5, iclass 20, count 2 2006.183.07:50:40.69#ibcon#about to read 6, iclass 20, count 2 2006.183.07:50:40.69#ibcon#read 6, iclass 20, count 2 2006.183.07:50:40.69#ibcon#end of sib2, iclass 20, count 2 2006.183.07:50:40.69#ibcon#*after write, iclass 20, count 2 2006.183.07:50:40.69#ibcon#*before return 0, iclass 20, count 2 2006.183.07:50:40.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:50:40.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.07:50:40.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.07:50:40.69#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:40.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:50:40.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:50:40.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:50:40.81#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:50:40.81#ibcon#first serial, iclass 20, count 0 2006.183.07:50:40.81#ibcon#enter sib2, iclass 20, count 0 2006.183.07:50:40.81#ibcon#flushed, iclass 20, count 0 2006.183.07:50:40.81#ibcon#about to write, iclass 20, count 0 2006.183.07:50:40.81#ibcon#wrote, iclass 20, count 0 2006.183.07:50:40.81#ibcon#about to read 3, iclass 20, count 0 2006.183.07:50:40.83#ibcon#read 3, iclass 20, count 0 2006.183.07:50:40.83#ibcon#about to read 4, iclass 20, count 0 2006.183.07:50:40.83#ibcon#read 4, iclass 20, count 0 2006.183.07:50:40.83#ibcon#about to read 5, iclass 20, count 0 2006.183.07:50:40.83#ibcon#read 5, iclass 20, count 0 2006.183.07:50:40.83#ibcon#about to read 6, iclass 20, count 0 2006.183.07:50:40.83#ibcon#read 6, iclass 20, count 0 2006.183.07:50:40.83#ibcon#end of sib2, iclass 20, count 0 2006.183.07:50:40.83#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:50:40.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:50:40.83#ibcon#[27=USB\r\n] 2006.183.07:50:40.83#ibcon#*before write, iclass 20, count 0 2006.183.07:50:40.83#ibcon#enter sib2, iclass 20, count 0 2006.183.07:50:40.83#ibcon#flushed, iclass 20, count 0 2006.183.07:50:40.83#ibcon#about to write, iclass 20, count 0 2006.183.07:50:40.83#ibcon#wrote, iclass 20, count 0 2006.183.07:50:40.83#ibcon#about to read 3, iclass 20, count 0 2006.183.07:50:40.86#ibcon#read 3, iclass 20, count 0 2006.183.07:50:40.86#ibcon#about to read 4, iclass 20, count 0 2006.183.07:50:40.86#ibcon#read 4, iclass 20, count 0 2006.183.07:50:40.86#ibcon#about to read 5, iclass 20, count 0 2006.183.07:50:40.86#ibcon#read 5, iclass 20, count 0 2006.183.07:50:40.86#ibcon#about to read 6, iclass 20, count 0 2006.183.07:50:40.86#ibcon#read 6, iclass 20, count 0 2006.183.07:50:40.86#ibcon#end of sib2, iclass 20, count 0 2006.183.07:50:40.86#ibcon#*after write, iclass 20, count 0 2006.183.07:50:40.86#ibcon#*before return 0, iclass 20, count 0 2006.183.07:50:40.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:50:40.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.07:50:40.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:50:40.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:50:40.86$vc4f8/vblo=2,640.99 2006.183.07:50:40.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.07:50:40.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.07:50:40.86#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:40.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:40.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:40.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:40.86#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:50:40.86#ibcon#first serial, iclass 22, count 0 2006.183.07:50:40.86#ibcon#enter sib2, iclass 22, count 0 2006.183.07:50:40.86#ibcon#flushed, iclass 22, count 0 2006.183.07:50:40.86#ibcon#about to write, iclass 22, count 0 2006.183.07:50:40.86#ibcon#wrote, iclass 22, count 0 2006.183.07:50:40.86#ibcon#about to read 3, iclass 22, count 0 2006.183.07:50:40.88#ibcon#read 3, iclass 22, count 0 2006.183.07:50:40.88#ibcon#about to read 4, iclass 22, count 0 2006.183.07:50:40.88#ibcon#read 4, iclass 22, count 0 2006.183.07:50:40.88#ibcon#about to read 5, iclass 22, count 0 2006.183.07:50:40.88#ibcon#read 5, iclass 22, count 0 2006.183.07:50:40.88#ibcon#about to read 6, iclass 22, count 0 2006.183.07:50:40.88#ibcon#read 6, iclass 22, count 0 2006.183.07:50:40.88#ibcon#end of sib2, iclass 22, count 0 2006.183.07:50:40.88#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:50:40.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:50:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:50:40.88#ibcon#*before write, iclass 22, count 0 2006.183.07:50:40.88#ibcon#enter sib2, iclass 22, count 0 2006.183.07:50:40.88#ibcon#flushed, iclass 22, count 0 2006.183.07:50:40.88#ibcon#about to write, iclass 22, count 0 2006.183.07:50:40.88#ibcon#wrote, iclass 22, count 0 2006.183.07:50:40.88#ibcon#about to read 3, iclass 22, count 0 2006.183.07:50:40.92#ibcon#read 3, iclass 22, count 0 2006.183.07:50:40.92#ibcon#about to read 4, iclass 22, count 0 2006.183.07:50:40.92#ibcon#read 4, iclass 22, count 0 2006.183.07:50:40.92#ibcon#about to read 5, iclass 22, count 0 2006.183.07:50:40.92#ibcon#read 5, iclass 22, count 0 2006.183.07:50:40.92#ibcon#about to read 6, iclass 22, count 0 2006.183.07:50:40.92#ibcon#read 6, iclass 22, count 0 2006.183.07:50:40.92#ibcon#end of sib2, iclass 22, count 0 2006.183.07:50:40.92#ibcon#*after write, iclass 22, count 0 2006.183.07:50:40.92#ibcon#*before return 0, iclass 22, count 0 2006.183.07:50:40.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:40.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.07:50:40.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:50:40.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:50:40.92$vc4f8/vb=2,4 2006.183.07:50:40.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.07:50:40.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.07:50:40.92#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:40.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:40.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:40.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:40.98#ibcon#enter wrdev, iclass 24, count 2 2006.183.07:50:40.98#ibcon#first serial, iclass 24, count 2 2006.183.07:50:40.98#ibcon#enter sib2, iclass 24, count 2 2006.183.07:50:40.98#ibcon#flushed, iclass 24, count 2 2006.183.07:50:40.98#ibcon#about to write, iclass 24, count 2 2006.183.07:50:40.98#ibcon#wrote, iclass 24, count 2 2006.183.07:50:40.98#ibcon#about to read 3, iclass 24, count 2 2006.183.07:50:41.00#ibcon#read 3, iclass 24, count 2 2006.183.07:50:41.00#ibcon#about to read 4, iclass 24, count 2 2006.183.07:50:41.00#ibcon#read 4, iclass 24, count 2 2006.183.07:50:41.00#ibcon#about to read 5, iclass 24, count 2 2006.183.07:50:41.00#ibcon#read 5, iclass 24, count 2 2006.183.07:50:41.00#ibcon#about to read 6, iclass 24, count 2 2006.183.07:50:41.00#ibcon#read 6, iclass 24, count 2 2006.183.07:50:41.00#ibcon#end of sib2, iclass 24, count 2 2006.183.07:50:41.00#ibcon#*mode == 0, iclass 24, count 2 2006.183.07:50:41.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.07:50:41.00#ibcon#[27=AT02-04\r\n] 2006.183.07:50:41.00#ibcon#*before write, iclass 24, count 2 2006.183.07:50:41.00#ibcon#enter sib2, iclass 24, count 2 2006.183.07:50:41.00#ibcon#flushed, iclass 24, count 2 2006.183.07:50:41.00#ibcon#about to write, iclass 24, count 2 2006.183.07:50:41.00#ibcon#wrote, iclass 24, count 2 2006.183.07:50:41.00#ibcon#about to read 3, iclass 24, count 2 2006.183.07:50:41.03#ibcon#read 3, iclass 24, count 2 2006.183.07:50:41.03#ibcon#about to read 4, iclass 24, count 2 2006.183.07:50:41.03#ibcon#read 4, iclass 24, count 2 2006.183.07:50:41.03#ibcon#about to read 5, iclass 24, count 2 2006.183.07:50:41.03#ibcon#read 5, iclass 24, count 2 2006.183.07:50:41.03#ibcon#about to read 6, iclass 24, count 2 2006.183.07:50:41.03#ibcon#read 6, iclass 24, count 2 2006.183.07:50:41.03#ibcon#end of sib2, iclass 24, count 2 2006.183.07:50:41.03#ibcon#*after write, iclass 24, count 2 2006.183.07:50:41.03#ibcon#*before return 0, iclass 24, count 2 2006.183.07:50:41.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:41.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.07:50:41.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.07:50:41.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:41.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:41.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:41.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:41.15#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:50:41.15#ibcon#first serial, iclass 24, count 0 2006.183.07:50:41.15#ibcon#enter sib2, iclass 24, count 0 2006.183.07:50:41.15#ibcon#flushed, iclass 24, count 0 2006.183.07:50:41.15#ibcon#about to write, iclass 24, count 0 2006.183.07:50:41.15#ibcon#wrote, iclass 24, count 0 2006.183.07:50:41.15#ibcon#about to read 3, iclass 24, count 0 2006.183.07:50:41.17#ibcon#read 3, iclass 24, count 0 2006.183.07:50:41.17#ibcon#about to read 4, iclass 24, count 0 2006.183.07:50:41.17#ibcon#read 4, iclass 24, count 0 2006.183.07:50:41.17#ibcon#about to read 5, iclass 24, count 0 2006.183.07:50:41.17#ibcon#read 5, iclass 24, count 0 2006.183.07:50:41.17#ibcon#about to read 6, iclass 24, count 0 2006.183.07:50:41.17#ibcon#read 6, iclass 24, count 0 2006.183.07:50:41.17#ibcon#end of sib2, iclass 24, count 0 2006.183.07:50:41.17#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:50:41.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:50:41.17#ibcon#[27=USB\r\n] 2006.183.07:50:41.17#ibcon#*before write, iclass 24, count 0 2006.183.07:50:41.17#ibcon#enter sib2, iclass 24, count 0 2006.183.07:50:41.17#ibcon#flushed, iclass 24, count 0 2006.183.07:50:41.17#ibcon#about to write, iclass 24, count 0 2006.183.07:50:41.17#ibcon#wrote, iclass 24, count 0 2006.183.07:50:41.17#ibcon#about to read 3, iclass 24, count 0 2006.183.07:50:41.20#ibcon#read 3, iclass 24, count 0 2006.183.07:50:41.20#ibcon#about to read 4, iclass 24, count 0 2006.183.07:50:41.20#ibcon#read 4, iclass 24, count 0 2006.183.07:50:41.20#ibcon#about to read 5, iclass 24, count 0 2006.183.07:50:41.20#ibcon#read 5, iclass 24, count 0 2006.183.07:50:41.20#ibcon#about to read 6, iclass 24, count 0 2006.183.07:50:41.20#ibcon#read 6, iclass 24, count 0 2006.183.07:50:41.20#ibcon#end of sib2, iclass 24, count 0 2006.183.07:50:41.20#ibcon#*after write, iclass 24, count 0 2006.183.07:50:41.20#ibcon#*before return 0, iclass 24, count 0 2006.183.07:50:41.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:41.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.07:50:41.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:50:41.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:50:41.20$vc4f8/vblo=3,656.99 2006.183.07:50:41.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.07:50:41.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.07:50:41.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:41.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:41.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:41.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:41.20#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:50:41.20#ibcon#first serial, iclass 26, count 0 2006.183.07:50:41.20#ibcon#enter sib2, iclass 26, count 0 2006.183.07:50:41.20#ibcon#flushed, iclass 26, count 0 2006.183.07:50:41.20#ibcon#about to write, iclass 26, count 0 2006.183.07:50:41.20#ibcon#wrote, iclass 26, count 0 2006.183.07:50:41.20#ibcon#about to read 3, iclass 26, count 0 2006.183.07:50:41.22#ibcon#read 3, iclass 26, count 0 2006.183.07:50:41.22#ibcon#about to read 4, iclass 26, count 0 2006.183.07:50:41.22#ibcon#read 4, iclass 26, count 0 2006.183.07:50:41.22#ibcon#about to read 5, iclass 26, count 0 2006.183.07:50:41.22#ibcon#read 5, iclass 26, count 0 2006.183.07:50:41.22#ibcon#about to read 6, iclass 26, count 0 2006.183.07:50:41.22#ibcon#read 6, iclass 26, count 0 2006.183.07:50:41.22#ibcon#end of sib2, iclass 26, count 0 2006.183.07:50:41.22#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:50:41.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:50:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:50:41.22#ibcon#*before write, iclass 26, count 0 2006.183.07:50:41.22#ibcon#enter sib2, iclass 26, count 0 2006.183.07:50:41.22#ibcon#flushed, iclass 26, count 0 2006.183.07:50:41.22#ibcon#about to write, iclass 26, count 0 2006.183.07:50:41.22#ibcon#wrote, iclass 26, count 0 2006.183.07:50:41.22#ibcon#about to read 3, iclass 26, count 0 2006.183.07:50:41.26#ibcon#read 3, iclass 26, count 0 2006.183.07:50:41.26#ibcon#about to read 4, iclass 26, count 0 2006.183.07:50:41.26#ibcon#read 4, iclass 26, count 0 2006.183.07:50:41.26#ibcon#about to read 5, iclass 26, count 0 2006.183.07:50:41.26#ibcon#read 5, iclass 26, count 0 2006.183.07:50:41.26#ibcon#about to read 6, iclass 26, count 0 2006.183.07:50:41.26#ibcon#read 6, iclass 26, count 0 2006.183.07:50:41.26#ibcon#end of sib2, iclass 26, count 0 2006.183.07:50:41.26#ibcon#*after write, iclass 26, count 0 2006.183.07:50:41.26#ibcon#*before return 0, iclass 26, count 0 2006.183.07:50:41.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:41.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:50:41.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:50:41.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:50:41.26$vc4f8/vb=3,4 2006.183.07:50:41.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.07:50:41.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.07:50:41.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:41.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:41.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:41.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:41.32#ibcon#enter wrdev, iclass 28, count 2 2006.183.07:50:41.32#ibcon#first serial, iclass 28, count 2 2006.183.07:50:41.32#ibcon#enter sib2, iclass 28, count 2 2006.183.07:50:41.32#ibcon#flushed, iclass 28, count 2 2006.183.07:50:41.32#ibcon#about to write, iclass 28, count 2 2006.183.07:50:41.32#ibcon#wrote, iclass 28, count 2 2006.183.07:50:41.32#ibcon#about to read 3, iclass 28, count 2 2006.183.07:50:41.34#ibcon#read 3, iclass 28, count 2 2006.183.07:50:41.34#ibcon#about to read 4, iclass 28, count 2 2006.183.07:50:41.34#ibcon#read 4, iclass 28, count 2 2006.183.07:50:41.34#ibcon#about to read 5, iclass 28, count 2 2006.183.07:50:41.34#ibcon#read 5, iclass 28, count 2 2006.183.07:50:41.34#ibcon#about to read 6, iclass 28, count 2 2006.183.07:50:41.34#ibcon#read 6, iclass 28, count 2 2006.183.07:50:41.34#ibcon#end of sib2, iclass 28, count 2 2006.183.07:50:41.34#ibcon#*mode == 0, iclass 28, count 2 2006.183.07:50:41.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.07:50:41.34#ibcon#[27=AT03-04\r\n] 2006.183.07:50:41.34#ibcon#*before write, iclass 28, count 2 2006.183.07:50:41.34#ibcon#enter sib2, iclass 28, count 2 2006.183.07:50:41.34#ibcon#flushed, iclass 28, count 2 2006.183.07:50:41.34#ibcon#about to write, iclass 28, count 2 2006.183.07:50:41.34#ibcon#wrote, iclass 28, count 2 2006.183.07:50:41.34#ibcon#about to read 3, iclass 28, count 2 2006.183.07:50:41.37#ibcon#read 3, iclass 28, count 2 2006.183.07:50:41.37#ibcon#about to read 4, iclass 28, count 2 2006.183.07:50:41.37#ibcon#read 4, iclass 28, count 2 2006.183.07:50:41.37#ibcon#about to read 5, iclass 28, count 2 2006.183.07:50:41.37#ibcon#read 5, iclass 28, count 2 2006.183.07:50:41.37#ibcon#about to read 6, iclass 28, count 2 2006.183.07:50:41.37#ibcon#read 6, iclass 28, count 2 2006.183.07:50:41.37#ibcon#end of sib2, iclass 28, count 2 2006.183.07:50:41.37#ibcon#*after write, iclass 28, count 2 2006.183.07:50:41.37#ibcon#*before return 0, iclass 28, count 2 2006.183.07:50:41.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:41.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.07:50:41.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.07:50:41.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:41.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:41.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:41.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:41.49#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:50:41.49#ibcon#first serial, iclass 28, count 0 2006.183.07:50:41.49#ibcon#enter sib2, iclass 28, count 0 2006.183.07:50:41.49#ibcon#flushed, iclass 28, count 0 2006.183.07:50:41.49#ibcon#about to write, iclass 28, count 0 2006.183.07:50:41.49#ibcon#wrote, iclass 28, count 0 2006.183.07:50:41.49#ibcon#about to read 3, iclass 28, count 0 2006.183.07:50:41.51#ibcon#read 3, iclass 28, count 0 2006.183.07:50:41.51#ibcon#about to read 4, iclass 28, count 0 2006.183.07:50:41.51#ibcon#read 4, iclass 28, count 0 2006.183.07:50:41.51#ibcon#about to read 5, iclass 28, count 0 2006.183.07:50:41.51#ibcon#read 5, iclass 28, count 0 2006.183.07:50:41.51#ibcon#about to read 6, iclass 28, count 0 2006.183.07:50:41.51#ibcon#read 6, iclass 28, count 0 2006.183.07:50:41.51#ibcon#end of sib2, iclass 28, count 0 2006.183.07:50:41.51#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:50:41.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:50:41.51#ibcon#[27=USB\r\n] 2006.183.07:50:41.51#ibcon#*before write, iclass 28, count 0 2006.183.07:50:41.51#ibcon#enter sib2, iclass 28, count 0 2006.183.07:50:41.51#ibcon#flushed, iclass 28, count 0 2006.183.07:50:41.51#ibcon#about to write, iclass 28, count 0 2006.183.07:50:41.51#ibcon#wrote, iclass 28, count 0 2006.183.07:50:41.51#ibcon#about to read 3, iclass 28, count 0 2006.183.07:50:41.54#ibcon#read 3, iclass 28, count 0 2006.183.07:50:41.54#ibcon#about to read 4, iclass 28, count 0 2006.183.07:50:41.54#ibcon#read 4, iclass 28, count 0 2006.183.07:50:41.54#ibcon#about to read 5, iclass 28, count 0 2006.183.07:50:41.54#ibcon#read 5, iclass 28, count 0 2006.183.07:50:41.54#ibcon#about to read 6, iclass 28, count 0 2006.183.07:50:41.54#ibcon#read 6, iclass 28, count 0 2006.183.07:50:41.54#ibcon#end of sib2, iclass 28, count 0 2006.183.07:50:41.54#ibcon#*after write, iclass 28, count 0 2006.183.07:50:41.54#ibcon#*before return 0, iclass 28, count 0 2006.183.07:50:41.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:41.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.07:50:41.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:50:41.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:50:41.54$vc4f8/vblo=4,712.99 2006.183.07:50:41.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.07:50:41.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.07:50:41.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:41.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:41.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:41.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:41.54#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:50:41.54#ibcon#first serial, iclass 30, count 0 2006.183.07:50:41.54#ibcon#enter sib2, iclass 30, count 0 2006.183.07:50:41.54#ibcon#flushed, iclass 30, count 0 2006.183.07:50:41.54#ibcon#about to write, iclass 30, count 0 2006.183.07:50:41.54#ibcon#wrote, iclass 30, count 0 2006.183.07:50:41.54#ibcon#about to read 3, iclass 30, count 0 2006.183.07:50:41.56#ibcon#read 3, iclass 30, count 0 2006.183.07:50:41.56#ibcon#about to read 4, iclass 30, count 0 2006.183.07:50:41.56#ibcon#read 4, iclass 30, count 0 2006.183.07:50:41.56#ibcon#about to read 5, iclass 30, count 0 2006.183.07:50:41.56#ibcon#read 5, iclass 30, count 0 2006.183.07:50:41.56#ibcon#about to read 6, iclass 30, count 0 2006.183.07:50:41.56#ibcon#read 6, iclass 30, count 0 2006.183.07:50:41.56#ibcon#end of sib2, iclass 30, count 0 2006.183.07:50:41.56#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:50:41.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:50:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:50:41.56#ibcon#*before write, iclass 30, count 0 2006.183.07:50:41.56#ibcon#enter sib2, iclass 30, count 0 2006.183.07:50:41.56#ibcon#flushed, iclass 30, count 0 2006.183.07:50:41.56#ibcon#about to write, iclass 30, count 0 2006.183.07:50:41.56#ibcon#wrote, iclass 30, count 0 2006.183.07:50:41.56#ibcon#about to read 3, iclass 30, count 0 2006.183.07:50:41.60#ibcon#read 3, iclass 30, count 0 2006.183.07:50:41.60#ibcon#about to read 4, iclass 30, count 0 2006.183.07:50:41.60#ibcon#read 4, iclass 30, count 0 2006.183.07:50:41.60#ibcon#about to read 5, iclass 30, count 0 2006.183.07:50:41.60#ibcon#read 5, iclass 30, count 0 2006.183.07:50:41.60#ibcon#about to read 6, iclass 30, count 0 2006.183.07:50:41.60#ibcon#read 6, iclass 30, count 0 2006.183.07:50:41.60#ibcon#end of sib2, iclass 30, count 0 2006.183.07:50:41.60#ibcon#*after write, iclass 30, count 0 2006.183.07:50:41.60#ibcon#*before return 0, iclass 30, count 0 2006.183.07:50:41.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:41.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.07:50:41.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:50:41.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:50:41.60$vc4f8/vb=4,4 2006.183.07:50:41.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.07:50:41.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.07:50:41.60#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:41.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:41.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:41.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:41.66#ibcon#enter wrdev, iclass 32, count 2 2006.183.07:50:41.66#ibcon#first serial, iclass 32, count 2 2006.183.07:50:41.66#ibcon#enter sib2, iclass 32, count 2 2006.183.07:50:41.66#ibcon#flushed, iclass 32, count 2 2006.183.07:50:41.66#ibcon#about to write, iclass 32, count 2 2006.183.07:50:41.66#ibcon#wrote, iclass 32, count 2 2006.183.07:50:41.66#ibcon#about to read 3, iclass 32, count 2 2006.183.07:50:41.68#ibcon#read 3, iclass 32, count 2 2006.183.07:50:41.68#ibcon#about to read 4, iclass 32, count 2 2006.183.07:50:41.68#ibcon#read 4, iclass 32, count 2 2006.183.07:50:41.68#ibcon#about to read 5, iclass 32, count 2 2006.183.07:50:41.68#ibcon#read 5, iclass 32, count 2 2006.183.07:50:41.68#ibcon#about to read 6, iclass 32, count 2 2006.183.07:50:41.68#ibcon#read 6, iclass 32, count 2 2006.183.07:50:41.68#ibcon#end of sib2, iclass 32, count 2 2006.183.07:50:41.68#ibcon#*mode == 0, iclass 32, count 2 2006.183.07:50:41.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.07:50:41.68#ibcon#[27=AT04-04\r\n] 2006.183.07:50:41.68#ibcon#*before write, iclass 32, count 2 2006.183.07:50:41.68#ibcon#enter sib2, iclass 32, count 2 2006.183.07:50:41.68#ibcon#flushed, iclass 32, count 2 2006.183.07:50:41.68#ibcon#about to write, iclass 32, count 2 2006.183.07:50:41.68#ibcon#wrote, iclass 32, count 2 2006.183.07:50:41.68#ibcon#about to read 3, iclass 32, count 2 2006.183.07:50:41.71#ibcon#read 3, iclass 32, count 2 2006.183.07:50:41.71#ibcon#about to read 4, iclass 32, count 2 2006.183.07:50:41.71#ibcon#read 4, iclass 32, count 2 2006.183.07:50:41.71#ibcon#about to read 5, iclass 32, count 2 2006.183.07:50:41.71#ibcon#read 5, iclass 32, count 2 2006.183.07:50:41.71#ibcon#about to read 6, iclass 32, count 2 2006.183.07:50:41.71#ibcon#read 6, iclass 32, count 2 2006.183.07:50:41.71#ibcon#end of sib2, iclass 32, count 2 2006.183.07:50:41.71#ibcon#*after write, iclass 32, count 2 2006.183.07:50:41.71#ibcon#*before return 0, iclass 32, count 2 2006.183.07:50:41.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:41.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.07:50:41.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.07:50:41.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:41.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:41.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:41.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:41.83#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:50:41.83#ibcon#first serial, iclass 32, count 0 2006.183.07:50:41.83#ibcon#enter sib2, iclass 32, count 0 2006.183.07:50:41.83#ibcon#flushed, iclass 32, count 0 2006.183.07:50:41.83#ibcon#about to write, iclass 32, count 0 2006.183.07:50:41.83#ibcon#wrote, iclass 32, count 0 2006.183.07:50:41.83#ibcon#about to read 3, iclass 32, count 0 2006.183.07:50:41.85#ibcon#read 3, iclass 32, count 0 2006.183.07:50:41.85#ibcon#about to read 4, iclass 32, count 0 2006.183.07:50:41.85#ibcon#read 4, iclass 32, count 0 2006.183.07:50:41.85#ibcon#about to read 5, iclass 32, count 0 2006.183.07:50:41.85#ibcon#read 5, iclass 32, count 0 2006.183.07:50:41.85#ibcon#about to read 6, iclass 32, count 0 2006.183.07:50:41.85#ibcon#read 6, iclass 32, count 0 2006.183.07:50:41.85#ibcon#end of sib2, iclass 32, count 0 2006.183.07:50:41.85#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:50:41.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:50:41.85#ibcon#[27=USB\r\n] 2006.183.07:50:41.85#ibcon#*before write, iclass 32, count 0 2006.183.07:50:41.85#ibcon#enter sib2, iclass 32, count 0 2006.183.07:50:41.85#ibcon#flushed, iclass 32, count 0 2006.183.07:50:41.85#ibcon#about to write, iclass 32, count 0 2006.183.07:50:41.85#ibcon#wrote, iclass 32, count 0 2006.183.07:50:41.85#ibcon#about to read 3, iclass 32, count 0 2006.183.07:50:41.88#ibcon#read 3, iclass 32, count 0 2006.183.07:50:41.88#ibcon#about to read 4, iclass 32, count 0 2006.183.07:50:41.88#ibcon#read 4, iclass 32, count 0 2006.183.07:50:41.88#ibcon#about to read 5, iclass 32, count 0 2006.183.07:50:41.88#ibcon#read 5, iclass 32, count 0 2006.183.07:50:41.88#ibcon#about to read 6, iclass 32, count 0 2006.183.07:50:41.88#ibcon#read 6, iclass 32, count 0 2006.183.07:50:41.88#ibcon#end of sib2, iclass 32, count 0 2006.183.07:50:41.88#ibcon#*after write, iclass 32, count 0 2006.183.07:50:41.88#ibcon#*before return 0, iclass 32, count 0 2006.183.07:50:41.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:41.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.07:50:41.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:50:41.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:50:41.88$vc4f8/vblo=5,744.99 2006.183.07:50:41.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.07:50:41.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.07:50:41.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:41.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:41.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:41.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:41.88#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:50:41.88#ibcon#first serial, iclass 34, count 0 2006.183.07:50:41.88#ibcon#enter sib2, iclass 34, count 0 2006.183.07:50:41.88#ibcon#flushed, iclass 34, count 0 2006.183.07:50:41.88#ibcon#about to write, iclass 34, count 0 2006.183.07:50:41.88#ibcon#wrote, iclass 34, count 0 2006.183.07:50:41.88#ibcon#about to read 3, iclass 34, count 0 2006.183.07:50:41.91#ibcon#read 3, iclass 34, count 0 2006.183.07:50:41.91#ibcon#about to read 4, iclass 34, count 0 2006.183.07:50:41.91#ibcon#read 4, iclass 34, count 0 2006.183.07:50:41.91#ibcon#about to read 5, iclass 34, count 0 2006.183.07:50:41.91#ibcon#read 5, iclass 34, count 0 2006.183.07:50:41.91#ibcon#about to read 6, iclass 34, count 0 2006.183.07:50:41.91#ibcon#read 6, iclass 34, count 0 2006.183.07:50:41.91#ibcon#end of sib2, iclass 34, count 0 2006.183.07:50:41.91#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:50:41.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:50:41.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:50:41.91#ibcon#*before write, iclass 34, count 0 2006.183.07:50:41.91#ibcon#enter sib2, iclass 34, count 0 2006.183.07:50:41.91#ibcon#flushed, iclass 34, count 0 2006.183.07:50:41.91#ibcon#about to write, iclass 34, count 0 2006.183.07:50:41.91#ibcon#wrote, iclass 34, count 0 2006.183.07:50:41.91#ibcon#about to read 3, iclass 34, count 0 2006.183.07:50:41.95#ibcon#read 3, iclass 34, count 0 2006.183.07:50:41.95#ibcon#about to read 4, iclass 34, count 0 2006.183.07:50:41.95#ibcon#read 4, iclass 34, count 0 2006.183.07:50:41.95#ibcon#about to read 5, iclass 34, count 0 2006.183.07:50:41.95#ibcon#read 5, iclass 34, count 0 2006.183.07:50:41.95#ibcon#about to read 6, iclass 34, count 0 2006.183.07:50:41.95#ibcon#read 6, iclass 34, count 0 2006.183.07:50:41.95#ibcon#end of sib2, iclass 34, count 0 2006.183.07:50:41.95#ibcon#*after write, iclass 34, count 0 2006.183.07:50:41.95#ibcon#*before return 0, iclass 34, count 0 2006.183.07:50:41.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:41.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.07:50:41.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:50:41.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:50:41.95$vc4f8/vb=5,4 2006.183.07:50:41.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.07:50:41.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.07:50:41.95#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:41.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:42.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:42.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:42.00#ibcon#enter wrdev, iclass 36, count 2 2006.183.07:50:42.00#ibcon#first serial, iclass 36, count 2 2006.183.07:50:42.00#ibcon#enter sib2, iclass 36, count 2 2006.183.07:50:42.00#ibcon#flushed, iclass 36, count 2 2006.183.07:50:42.00#ibcon#about to write, iclass 36, count 2 2006.183.07:50:42.00#ibcon#wrote, iclass 36, count 2 2006.183.07:50:42.00#ibcon#about to read 3, iclass 36, count 2 2006.183.07:50:42.02#ibcon#read 3, iclass 36, count 2 2006.183.07:50:42.02#ibcon#about to read 4, iclass 36, count 2 2006.183.07:50:42.02#ibcon#read 4, iclass 36, count 2 2006.183.07:50:42.02#ibcon#about to read 5, iclass 36, count 2 2006.183.07:50:42.02#ibcon#read 5, iclass 36, count 2 2006.183.07:50:42.02#ibcon#about to read 6, iclass 36, count 2 2006.183.07:50:42.02#ibcon#read 6, iclass 36, count 2 2006.183.07:50:42.02#ibcon#end of sib2, iclass 36, count 2 2006.183.07:50:42.02#ibcon#*mode == 0, iclass 36, count 2 2006.183.07:50:42.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.07:50:42.02#ibcon#[27=AT05-04\r\n] 2006.183.07:50:42.02#ibcon#*before write, iclass 36, count 2 2006.183.07:50:42.02#ibcon#enter sib2, iclass 36, count 2 2006.183.07:50:42.02#ibcon#flushed, iclass 36, count 2 2006.183.07:50:42.02#ibcon#about to write, iclass 36, count 2 2006.183.07:50:42.02#ibcon#wrote, iclass 36, count 2 2006.183.07:50:42.02#ibcon#about to read 3, iclass 36, count 2 2006.183.07:50:42.05#ibcon#read 3, iclass 36, count 2 2006.183.07:50:42.05#ibcon#about to read 4, iclass 36, count 2 2006.183.07:50:42.05#ibcon#read 4, iclass 36, count 2 2006.183.07:50:42.05#ibcon#about to read 5, iclass 36, count 2 2006.183.07:50:42.05#ibcon#read 5, iclass 36, count 2 2006.183.07:50:42.05#ibcon#about to read 6, iclass 36, count 2 2006.183.07:50:42.05#ibcon#read 6, iclass 36, count 2 2006.183.07:50:42.05#ibcon#end of sib2, iclass 36, count 2 2006.183.07:50:42.05#ibcon#*after write, iclass 36, count 2 2006.183.07:50:42.05#ibcon#*before return 0, iclass 36, count 2 2006.183.07:50:42.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:42.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.07:50:42.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.07:50:42.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:42.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:42.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:42.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:42.17#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:50:42.17#ibcon#first serial, iclass 36, count 0 2006.183.07:50:42.17#ibcon#enter sib2, iclass 36, count 0 2006.183.07:50:42.17#ibcon#flushed, iclass 36, count 0 2006.183.07:50:42.17#ibcon#about to write, iclass 36, count 0 2006.183.07:50:42.17#ibcon#wrote, iclass 36, count 0 2006.183.07:50:42.17#ibcon#about to read 3, iclass 36, count 0 2006.183.07:50:42.19#ibcon#read 3, iclass 36, count 0 2006.183.07:50:42.19#ibcon#about to read 4, iclass 36, count 0 2006.183.07:50:42.19#ibcon#read 4, iclass 36, count 0 2006.183.07:50:42.19#ibcon#about to read 5, iclass 36, count 0 2006.183.07:50:42.19#ibcon#read 5, iclass 36, count 0 2006.183.07:50:42.19#ibcon#about to read 6, iclass 36, count 0 2006.183.07:50:42.19#ibcon#read 6, iclass 36, count 0 2006.183.07:50:42.19#ibcon#end of sib2, iclass 36, count 0 2006.183.07:50:42.19#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:50:42.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:50:42.19#ibcon#[27=USB\r\n] 2006.183.07:50:42.19#ibcon#*before write, iclass 36, count 0 2006.183.07:50:42.19#ibcon#enter sib2, iclass 36, count 0 2006.183.07:50:42.19#ibcon#flushed, iclass 36, count 0 2006.183.07:50:42.19#ibcon#about to write, iclass 36, count 0 2006.183.07:50:42.19#ibcon#wrote, iclass 36, count 0 2006.183.07:50:42.19#ibcon#about to read 3, iclass 36, count 0 2006.183.07:50:42.22#ibcon#read 3, iclass 36, count 0 2006.183.07:50:42.22#ibcon#about to read 4, iclass 36, count 0 2006.183.07:50:42.22#ibcon#read 4, iclass 36, count 0 2006.183.07:50:42.22#ibcon#about to read 5, iclass 36, count 0 2006.183.07:50:42.22#ibcon#read 5, iclass 36, count 0 2006.183.07:50:42.22#ibcon#about to read 6, iclass 36, count 0 2006.183.07:50:42.22#ibcon#read 6, iclass 36, count 0 2006.183.07:50:42.22#ibcon#end of sib2, iclass 36, count 0 2006.183.07:50:42.22#ibcon#*after write, iclass 36, count 0 2006.183.07:50:42.22#ibcon#*before return 0, iclass 36, count 0 2006.183.07:50:42.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:42.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.07:50:42.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:50:42.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:50:42.22$vc4f8/vblo=6,752.99 2006.183.07:50:42.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.07:50:42.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.07:50:42.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:50:42.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:42.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:42.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:42.22#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:50:42.22#ibcon#first serial, iclass 38, count 0 2006.183.07:50:42.22#ibcon#enter sib2, iclass 38, count 0 2006.183.07:50:42.22#ibcon#flushed, iclass 38, count 0 2006.183.07:50:42.22#ibcon#about to write, iclass 38, count 0 2006.183.07:50:42.22#ibcon#wrote, iclass 38, count 0 2006.183.07:50:42.22#ibcon#about to read 3, iclass 38, count 0 2006.183.07:50:42.24#ibcon#read 3, iclass 38, count 0 2006.183.07:50:42.24#ibcon#about to read 4, iclass 38, count 0 2006.183.07:50:42.24#ibcon#read 4, iclass 38, count 0 2006.183.07:50:42.24#ibcon#about to read 5, iclass 38, count 0 2006.183.07:50:42.24#ibcon#read 5, iclass 38, count 0 2006.183.07:50:42.24#ibcon#about to read 6, iclass 38, count 0 2006.183.07:50:42.24#ibcon#read 6, iclass 38, count 0 2006.183.07:50:42.24#ibcon#end of sib2, iclass 38, count 0 2006.183.07:50:42.24#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:50:42.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:50:42.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:50:42.24#ibcon#*before write, iclass 38, count 0 2006.183.07:50:42.24#ibcon#enter sib2, iclass 38, count 0 2006.183.07:50:42.24#ibcon#flushed, iclass 38, count 0 2006.183.07:50:42.24#ibcon#about to write, iclass 38, count 0 2006.183.07:50:42.24#ibcon#wrote, iclass 38, count 0 2006.183.07:50:42.24#ibcon#about to read 3, iclass 38, count 0 2006.183.07:50:42.28#ibcon#read 3, iclass 38, count 0 2006.183.07:50:42.28#ibcon#about to read 4, iclass 38, count 0 2006.183.07:50:42.28#ibcon#read 4, iclass 38, count 0 2006.183.07:50:42.28#ibcon#about to read 5, iclass 38, count 0 2006.183.07:50:42.28#ibcon#read 5, iclass 38, count 0 2006.183.07:50:42.28#ibcon#about to read 6, iclass 38, count 0 2006.183.07:50:42.28#ibcon#read 6, iclass 38, count 0 2006.183.07:50:42.28#ibcon#end of sib2, iclass 38, count 0 2006.183.07:50:42.28#ibcon#*after write, iclass 38, count 0 2006.183.07:50:42.28#ibcon#*before return 0, iclass 38, count 0 2006.183.07:50:42.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:42.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.07:50:42.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:50:42.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:50:42.28$vc4f8/vb=6,4 2006.183.07:50:42.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.07:50:42.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.07:50:42.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:50:42.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:42.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:42.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:42.34#ibcon#enter wrdev, iclass 40, count 2 2006.183.07:50:42.34#ibcon#first serial, iclass 40, count 2 2006.183.07:50:42.34#ibcon#enter sib2, iclass 40, count 2 2006.183.07:50:42.34#ibcon#flushed, iclass 40, count 2 2006.183.07:50:42.34#ibcon#about to write, iclass 40, count 2 2006.183.07:50:42.34#ibcon#wrote, iclass 40, count 2 2006.183.07:50:42.34#ibcon#about to read 3, iclass 40, count 2 2006.183.07:50:42.36#ibcon#read 3, iclass 40, count 2 2006.183.07:50:42.36#ibcon#about to read 4, iclass 40, count 2 2006.183.07:50:42.36#ibcon#read 4, iclass 40, count 2 2006.183.07:50:42.36#ibcon#about to read 5, iclass 40, count 2 2006.183.07:50:42.36#ibcon#read 5, iclass 40, count 2 2006.183.07:50:42.36#ibcon#about to read 6, iclass 40, count 2 2006.183.07:50:42.36#ibcon#read 6, iclass 40, count 2 2006.183.07:50:42.36#ibcon#end of sib2, iclass 40, count 2 2006.183.07:50:42.36#ibcon#*mode == 0, iclass 40, count 2 2006.183.07:50:42.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.07:50:42.36#ibcon#[27=AT06-04\r\n] 2006.183.07:50:42.36#ibcon#*before write, iclass 40, count 2 2006.183.07:50:42.36#ibcon#enter sib2, iclass 40, count 2 2006.183.07:50:42.36#ibcon#flushed, iclass 40, count 2 2006.183.07:50:42.36#ibcon#about to write, iclass 40, count 2 2006.183.07:50:42.36#ibcon#wrote, iclass 40, count 2 2006.183.07:50:42.36#ibcon#about to read 3, iclass 40, count 2 2006.183.07:50:42.39#ibcon#read 3, iclass 40, count 2 2006.183.07:50:42.39#ibcon#about to read 4, iclass 40, count 2 2006.183.07:50:42.39#ibcon#read 4, iclass 40, count 2 2006.183.07:50:42.39#ibcon#about to read 5, iclass 40, count 2 2006.183.07:50:42.39#ibcon#read 5, iclass 40, count 2 2006.183.07:50:42.39#ibcon#about to read 6, iclass 40, count 2 2006.183.07:50:42.39#ibcon#read 6, iclass 40, count 2 2006.183.07:50:42.39#ibcon#end of sib2, iclass 40, count 2 2006.183.07:50:42.39#ibcon#*after write, iclass 40, count 2 2006.183.07:50:42.39#ibcon#*before return 0, iclass 40, count 2 2006.183.07:50:42.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:42.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.07:50:42.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.07:50:42.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:50:42.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:42.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:42.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:42.51#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:50:42.51#ibcon#first serial, iclass 40, count 0 2006.183.07:50:42.51#ibcon#enter sib2, iclass 40, count 0 2006.183.07:50:42.51#ibcon#flushed, iclass 40, count 0 2006.183.07:50:42.51#ibcon#about to write, iclass 40, count 0 2006.183.07:50:42.51#ibcon#wrote, iclass 40, count 0 2006.183.07:50:42.51#ibcon#about to read 3, iclass 40, count 0 2006.183.07:50:42.53#ibcon#read 3, iclass 40, count 0 2006.183.07:50:42.53#ibcon#about to read 4, iclass 40, count 0 2006.183.07:50:42.53#ibcon#read 4, iclass 40, count 0 2006.183.07:50:42.53#ibcon#about to read 5, iclass 40, count 0 2006.183.07:50:42.53#ibcon#read 5, iclass 40, count 0 2006.183.07:50:42.53#ibcon#about to read 6, iclass 40, count 0 2006.183.07:50:42.53#ibcon#read 6, iclass 40, count 0 2006.183.07:50:42.53#ibcon#end of sib2, iclass 40, count 0 2006.183.07:50:42.53#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:50:42.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:50:42.53#ibcon#[27=USB\r\n] 2006.183.07:50:42.53#ibcon#*before write, iclass 40, count 0 2006.183.07:50:42.53#ibcon#enter sib2, iclass 40, count 0 2006.183.07:50:42.53#ibcon#flushed, iclass 40, count 0 2006.183.07:50:42.53#ibcon#about to write, iclass 40, count 0 2006.183.07:50:42.53#ibcon#wrote, iclass 40, count 0 2006.183.07:50:42.53#ibcon#about to read 3, iclass 40, count 0 2006.183.07:50:42.56#ibcon#read 3, iclass 40, count 0 2006.183.07:50:42.56#ibcon#about to read 4, iclass 40, count 0 2006.183.07:50:42.56#ibcon#read 4, iclass 40, count 0 2006.183.07:50:42.56#ibcon#about to read 5, iclass 40, count 0 2006.183.07:50:42.56#ibcon#read 5, iclass 40, count 0 2006.183.07:50:42.56#ibcon#about to read 6, iclass 40, count 0 2006.183.07:50:42.56#ibcon#read 6, iclass 40, count 0 2006.183.07:50:42.56#ibcon#end of sib2, iclass 40, count 0 2006.183.07:50:42.56#ibcon#*after write, iclass 40, count 0 2006.183.07:50:42.56#ibcon#*before return 0, iclass 40, count 0 2006.183.07:50:42.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:42.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.07:50:42.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:50:42.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:50:42.56$vc4f8/vabw=wide 2006.183.07:50:42.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.07:50:42.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.07:50:42.56#ibcon#ireg 8 cls_cnt 0 2006.183.07:50:42.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:42.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:42.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:42.56#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:50:42.56#ibcon#first serial, iclass 4, count 0 2006.183.07:50:42.56#ibcon#enter sib2, iclass 4, count 0 2006.183.07:50:42.56#ibcon#flushed, iclass 4, count 0 2006.183.07:50:42.56#ibcon#about to write, iclass 4, count 0 2006.183.07:50:42.56#ibcon#wrote, iclass 4, count 0 2006.183.07:50:42.56#ibcon#about to read 3, iclass 4, count 0 2006.183.07:50:42.58#ibcon#read 3, iclass 4, count 0 2006.183.07:50:42.58#ibcon#about to read 4, iclass 4, count 0 2006.183.07:50:42.58#ibcon#read 4, iclass 4, count 0 2006.183.07:50:42.58#ibcon#about to read 5, iclass 4, count 0 2006.183.07:50:42.58#ibcon#read 5, iclass 4, count 0 2006.183.07:50:42.58#ibcon#about to read 6, iclass 4, count 0 2006.183.07:50:42.58#ibcon#read 6, iclass 4, count 0 2006.183.07:50:42.58#ibcon#end of sib2, iclass 4, count 0 2006.183.07:50:42.58#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:50:42.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:50:42.58#ibcon#[25=BW32\r\n] 2006.183.07:50:42.58#ibcon#*before write, iclass 4, count 0 2006.183.07:50:42.58#ibcon#enter sib2, iclass 4, count 0 2006.183.07:50:42.58#ibcon#flushed, iclass 4, count 0 2006.183.07:50:42.58#ibcon#about to write, iclass 4, count 0 2006.183.07:50:42.58#ibcon#wrote, iclass 4, count 0 2006.183.07:50:42.58#ibcon#about to read 3, iclass 4, count 0 2006.183.07:50:42.61#ibcon#read 3, iclass 4, count 0 2006.183.07:50:42.61#ibcon#about to read 4, iclass 4, count 0 2006.183.07:50:42.61#ibcon#read 4, iclass 4, count 0 2006.183.07:50:42.61#ibcon#about to read 5, iclass 4, count 0 2006.183.07:50:42.61#ibcon#read 5, iclass 4, count 0 2006.183.07:50:42.61#ibcon#about to read 6, iclass 4, count 0 2006.183.07:50:42.61#ibcon#read 6, iclass 4, count 0 2006.183.07:50:42.61#ibcon#end of sib2, iclass 4, count 0 2006.183.07:50:42.61#ibcon#*after write, iclass 4, count 0 2006.183.07:50:42.61#ibcon#*before return 0, iclass 4, count 0 2006.183.07:50:42.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:42.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.07:50:42.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:50:42.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:50:42.61$vc4f8/vbbw=wide 2006.183.07:50:42.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:50:42.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:50:42.61#ibcon#ireg 8 cls_cnt 0 2006.183.07:50:42.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:50:42.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:50:42.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:50:42.68#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:50:42.68#ibcon#first serial, iclass 6, count 0 2006.183.07:50:42.68#ibcon#enter sib2, iclass 6, count 0 2006.183.07:50:42.68#ibcon#flushed, iclass 6, count 0 2006.183.07:50:42.68#ibcon#about to write, iclass 6, count 0 2006.183.07:50:42.68#ibcon#wrote, iclass 6, count 0 2006.183.07:50:42.68#ibcon#about to read 3, iclass 6, count 0 2006.183.07:50:42.70#ibcon#read 3, iclass 6, count 0 2006.183.07:50:42.70#ibcon#about to read 4, iclass 6, count 0 2006.183.07:50:42.70#ibcon#read 4, iclass 6, count 0 2006.183.07:50:42.70#ibcon#about to read 5, iclass 6, count 0 2006.183.07:50:42.70#ibcon#read 5, iclass 6, count 0 2006.183.07:50:42.70#ibcon#about to read 6, iclass 6, count 0 2006.183.07:50:42.70#ibcon#read 6, iclass 6, count 0 2006.183.07:50:42.70#ibcon#end of sib2, iclass 6, count 0 2006.183.07:50:42.70#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:50:42.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:50:42.70#ibcon#[27=BW32\r\n] 2006.183.07:50:42.70#ibcon#*before write, iclass 6, count 0 2006.183.07:50:42.70#ibcon#enter sib2, iclass 6, count 0 2006.183.07:50:42.70#ibcon#flushed, iclass 6, count 0 2006.183.07:50:42.70#ibcon#about to write, iclass 6, count 0 2006.183.07:50:42.70#ibcon#wrote, iclass 6, count 0 2006.183.07:50:42.70#ibcon#about to read 3, iclass 6, count 0 2006.183.07:50:42.73#ibcon#read 3, iclass 6, count 0 2006.183.07:50:42.73#ibcon#about to read 4, iclass 6, count 0 2006.183.07:50:42.73#ibcon#read 4, iclass 6, count 0 2006.183.07:50:42.73#ibcon#about to read 5, iclass 6, count 0 2006.183.07:50:42.73#ibcon#read 5, iclass 6, count 0 2006.183.07:50:42.73#ibcon#about to read 6, iclass 6, count 0 2006.183.07:50:42.73#ibcon#read 6, iclass 6, count 0 2006.183.07:50:42.73#ibcon#end of sib2, iclass 6, count 0 2006.183.07:50:42.73#ibcon#*after write, iclass 6, count 0 2006.183.07:50:42.73#ibcon#*before return 0, iclass 6, count 0 2006.183.07:50:42.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:50:42.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:50:42.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:50:42.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:50:42.73$4f8m12a/ifd4f 2006.183.07:50:42.73$ifd4f/lo= 2006.183.07:50:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:50:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:50:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:50:42.73$ifd4f/patch= 2006.183.07:50:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:50:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:50:42.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:50:42.73$4f8m12a/"form=m,16.000,1:2 2006.183.07:50:42.73$4f8m12a/"tpicd 2006.183.07:50:42.73$4f8m12a/echo=off 2006.183.07:50:42.73$4f8m12a/xlog=off 2006.183.07:50:42.73:!2006.183.07:51:10 2006.183.07:50:57.13#trakl#Source acquired 2006.183.07:50:58.13#flagr#flagr/antenna,acquired 2006.183.07:51:10.00:preob 2006.183.07:51:11.13/onsource/TRACKING 2006.183.07:51:11.13:!2006.183.07:51:20 2006.183.07:51:20.00:data_valid=on 2006.183.07:51:20.00:midob 2006.183.07:51:20.13/onsource/TRACKING 2006.183.07:51:20.13/wx/27.97,996.4,88 2006.183.07:51:20.20/cable/+6.4531E-03 2006.183.07:51:21.29/va/01,08,usb,yes,28,30 2006.183.07:51:21.29/va/02,07,usb,yes,28,30 2006.183.07:51:21.29/va/03,06,usb,yes,30,30 2006.183.07:51:21.29/va/04,07,usb,yes,29,31 2006.183.07:51:21.29/va/05,07,usb,yes,31,33 2006.183.07:51:21.29/va/06,06,usb,yes,30,30 2006.183.07:51:21.29/va/07,06,usb,yes,31,30 2006.183.07:51:21.29/va/08,07,usb,yes,29,28 2006.183.07:51:21.52/valo/01,532.99,yes,locked 2006.183.07:51:21.52/valo/02,572.99,yes,locked 2006.183.07:51:21.52/valo/03,672.99,yes,locked 2006.183.07:51:21.52/valo/04,832.99,yes,locked 2006.183.07:51:21.52/valo/05,652.99,yes,locked 2006.183.07:51:21.52/valo/06,772.99,yes,locked 2006.183.07:51:21.52/valo/07,832.99,yes,locked 2006.183.07:51:21.52/valo/08,852.99,yes,locked 2006.183.07:51:22.61/vb/01,04,usb,yes,28,27 2006.183.07:51:22.61/vb/02,04,usb,yes,30,32 2006.183.07:51:22.61/vb/03,04,usb,yes,27,30 2006.183.07:51:22.61/vb/04,04,usb,yes,27,28 2006.183.07:51:22.61/vb/05,04,usb,yes,26,30 2006.183.07:51:22.61/vb/06,04,usb,yes,27,30 2006.183.07:51:22.61/vb/07,04,usb,yes,29,29 2006.183.07:51:22.61/vb/08,04,usb,yes,27,30 2006.183.07:51:22.84/vblo/01,632.99,yes,locked 2006.183.07:51:22.84/vblo/02,640.99,yes,locked 2006.183.07:51:22.84/vblo/03,656.99,yes,locked 2006.183.07:51:22.84/vblo/04,712.99,yes,locked 2006.183.07:51:22.84/vblo/05,744.99,yes,locked 2006.183.07:51:22.84/vblo/06,752.99,yes,locked 2006.183.07:51:22.84/vblo/07,734.99,yes,locked 2006.183.07:51:22.84/vblo/08,744.99,yes,locked 2006.183.07:51:22.99/vabw/8 2006.183.07:51:23.14/vbbw/8 2006.183.07:51:23.23/xfe/off,on,14.7 2006.183.07:51:23.60/ifatt/23,28,28,28 2006.183.07:51:24.07/fmout-gps/S +3.32E-07 2006.183.07:51:24.15:!2006.183.07:52:20 2006.183.07:52:20.00:data_valid=off 2006.183.07:52:20.00:postob 2006.183.07:52:20.05/cable/+6.4524E-03 2006.183.07:52:20.05/wx/27.97,996.4,88 2006.183.07:52:21.08/fmout-gps/S +3.31E-07 2006.183.07:52:21.08:scan_name=183-0754,k06183,60 2006.183.07:52:21.09:source=1803+784,180045.68,782804.0,2000.0,cw 2006.183.07:52:21.14#flagr#flagr/antenna,new-source 2006.183.07:52:22.14:checkk5 2006.183.07:52:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:52:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:52:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:52:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:52:24.01/chk_obsdata//k5ts1/T1830751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:52:24.38/chk_obsdata//k5ts2/T1830751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:52:24.74/chk_obsdata//k5ts3/T1830751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:52:25.11/chk_obsdata//k5ts4/T1830751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:52:25.80/k5log//k5ts1_log_newline 2006.183.07:52:26.49/k5log//k5ts2_log_newline 2006.183.07:52:27.17/k5log//k5ts3_log_newline 2006.183.07:52:27.86/k5log//k5ts4_log_newline 2006.183.07:52:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:52:27.89:4f8m12a=2 2006.183.07:52:27.89$4f8m12a/echo=on 2006.183.07:52:27.89$4f8m12a/pcalon 2006.183.07:52:27.89$pcalon/"no phase cal control is implemented here 2006.183.07:52:27.89$4f8m12a/"tpicd=stop 2006.183.07:52:27.89$4f8m12a/vc4f8 2006.183.07:52:27.89$vc4f8/valo=1,532.99 2006.183.07:52:27.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.07:52:27.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.07:52:27.89#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:27.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:27.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:27.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:27.89#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:52:27.89#ibcon#first serial, iclass 15, count 0 2006.183.07:52:27.89#ibcon#enter sib2, iclass 15, count 0 2006.183.07:52:27.89#ibcon#flushed, iclass 15, count 0 2006.183.07:52:27.89#ibcon#about to write, iclass 15, count 0 2006.183.07:52:27.89#ibcon#wrote, iclass 15, count 0 2006.183.07:52:27.89#ibcon#about to read 3, iclass 15, count 0 2006.183.07:52:27.93#ibcon#read 3, iclass 15, count 0 2006.183.07:52:27.93#ibcon#about to read 4, iclass 15, count 0 2006.183.07:52:27.93#ibcon#read 4, iclass 15, count 0 2006.183.07:52:27.93#ibcon#about to read 5, iclass 15, count 0 2006.183.07:52:27.93#ibcon#read 5, iclass 15, count 0 2006.183.07:52:27.93#ibcon#about to read 6, iclass 15, count 0 2006.183.07:52:27.93#ibcon#read 6, iclass 15, count 0 2006.183.07:52:27.93#ibcon#end of sib2, iclass 15, count 0 2006.183.07:52:27.93#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:52:27.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:52:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:52:27.93#ibcon#*before write, iclass 15, count 0 2006.183.07:52:27.93#ibcon#enter sib2, iclass 15, count 0 2006.183.07:52:27.93#ibcon#flushed, iclass 15, count 0 2006.183.07:52:27.93#ibcon#about to write, iclass 15, count 0 2006.183.07:52:27.93#ibcon#wrote, iclass 15, count 0 2006.183.07:52:27.93#ibcon#about to read 3, iclass 15, count 0 2006.183.07:52:27.98#ibcon#read 3, iclass 15, count 0 2006.183.07:52:27.98#ibcon#about to read 4, iclass 15, count 0 2006.183.07:52:27.98#ibcon#read 4, iclass 15, count 0 2006.183.07:52:27.98#ibcon#about to read 5, iclass 15, count 0 2006.183.07:52:27.98#ibcon#read 5, iclass 15, count 0 2006.183.07:52:27.98#ibcon#about to read 6, iclass 15, count 0 2006.183.07:52:27.98#ibcon#read 6, iclass 15, count 0 2006.183.07:52:27.98#ibcon#end of sib2, iclass 15, count 0 2006.183.07:52:27.98#ibcon#*after write, iclass 15, count 0 2006.183.07:52:27.98#ibcon#*before return 0, iclass 15, count 0 2006.183.07:52:27.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:27.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:27.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:52:27.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:52:27.98$vc4f8/va=1,8 2006.183.07:52:27.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.07:52:27.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.07:52:27.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:27.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:27.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:27.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:27.98#ibcon#enter wrdev, iclass 17, count 2 2006.183.07:52:27.98#ibcon#first serial, iclass 17, count 2 2006.183.07:52:27.98#ibcon#enter sib2, iclass 17, count 2 2006.183.07:52:27.98#ibcon#flushed, iclass 17, count 2 2006.183.07:52:27.98#ibcon#about to write, iclass 17, count 2 2006.183.07:52:27.98#ibcon#wrote, iclass 17, count 2 2006.183.07:52:27.98#ibcon#about to read 3, iclass 17, count 2 2006.183.07:52:28.00#ibcon#read 3, iclass 17, count 2 2006.183.07:52:28.00#ibcon#about to read 4, iclass 17, count 2 2006.183.07:52:28.00#ibcon#read 4, iclass 17, count 2 2006.183.07:52:28.00#ibcon#about to read 5, iclass 17, count 2 2006.183.07:52:28.00#ibcon#read 5, iclass 17, count 2 2006.183.07:52:28.00#ibcon#about to read 6, iclass 17, count 2 2006.183.07:52:28.00#ibcon#read 6, iclass 17, count 2 2006.183.07:52:28.00#ibcon#end of sib2, iclass 17, count 2 2006.183.07:52:28.00#ibcon#*mode == 0, iclass 17, count 2 2006.183.07:52:28.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.07:52:28.00#ibcon#[25=AT01-08\r\n] 2006.183.07:52:28.00#ibcon#*before write, iclass 17, count 2 2006.183.07:52:28.00#ibcon#enter sib2, iclass 17, count 2 2006.183.07:52:28.00#ibcon#flushed, iclass 17, count 2 2006.183.07:52:28.00#ibcon#about to write, iclass 17, count 2 2006.183.07:52:28.00#ibcon#wrote, iclass 17, count 2 2006.183.07:52:28.00#ibcon#about to read 3, iclass 17, count 2 2006.183.07:52:28.03#ibcon#read 3, iclass 17, count 2 2006.183.07:52:28.03#ibcon#about to read 4, iclass 17, count 2 2006.183.07:52:28.03#ibcon#read 4, iclass 17, count 2 2006.183.07:52:28.03#ibcon#about to read 5, iclass 17, count 2 2006.183.07:52:28.03#ibcon#read 5, iclass 17, count 2 2006.183.07:52:28.03#ibcon#about to read 6, iclass 17, count 2 2006.183.07:52:28.03#ibcon#read 6, iclass 17, count 2 2006.183.07:52:28.03#ibcon#end of sib2, iclass 17, count 2 2006.183.07:52:28.03#ibcon#*after write, iclass 17, count 2 2006.183.07:52:28.03#ibcon#*before return 0, iclass 17, count 2 2006.183.07:52:28.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:28.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:28.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.07:52:28.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:28.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:28.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:28.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:28.15#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:52:28.15#ibcon#first serial, iclass 17, count 0 2006.183.07:52:28.15#ibcon#enter sib2, iclass 17, count 0 2006.183.07:52:28.15#ibcon#flushed, iclass 17, count 0 2006.183.07:52:28.15#ibcon#about to write, iclass 17, count 0 2006.183.07:52:28.15#ibcon#wrote, iclass 17, count 0 2006.183.07:52:28.15#ibcon#about to read 3, iclass 17, count 0 2006.183.07:52:28.17#ibcon#read 3, iclass 17, count 0 2006.183.07:52:28.17#ibcon#about to read 4, iclass 17, count 0 2006.183.07:52:28.17#ibcon#read 4, iclass 17, count 0 2006.183.07:52:28.17#ibcon#about to read 5, iclass 17, count 0 2006.183.07:52:28.17#ibcon#read 5, iclass 17, count 0 2006.183.07:52:28.17#ibcon#about to read 6, iclass 17, count 0 2006.183.07:52:28.17#ibcon#read 6, iclass 17, count 0 2006.183.07:52:28.17#ibcon#end of sib2, iclass 17, count 0 2006.183.07:52:28.17#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:52:28.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:52:28.17#ibcon#[25=USB\r\n] 2006.183.07:52:28.17#ibcon#*before write, iclass 17, count 0 2006.183.07:52:28.17#ibcon#enter sib2, iclass 17, count 0 2006.183.07:52:28.17#ibcon#flushed, iclass 17, count 0 2006.183.07:52:28.17#ibcon#about to write, iclass 17, count 0 2006.183.07:52:28.17#ibcon#wrote, iclass 17, count 0 2006.183.07:52:28.17#ibcon#about to read 3, iclass 17, count 0 2006.183.07:52:28.20#ibcon#read 3, iclass 17, count 0 2006.183.07:52:28.20#ibcon#about to read 4, iclass 17, count 0 2006.183.07:52:28.20#ibcon#read 4, iclass 17, count 0 2006.183.07:52:28.20#ibcon#about to read 5, iclass 17, count 0 2006.183.07:52:28.20#ibcon#read 5, iclass 17, count 0 2006.183.07:52:28.20#ibcon#about to read 6, iclass 17, count 0 2006.183.07:52:28.20#ibcon#read 6, iclass 17, count 0 2006.183.07:52:28.20#ibcon#end of sib2, iclass 17, count 0 2006.183.07:52:28.20#ibcon#*after write, iclass 17, count 0 2006.183.07:52:28.20#ibcon#*before return 0, iclass 17, count 0 2006.183.07:52:28.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:28.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:28.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:52:28.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:52:28.20$vc4f8/valo=2,572.99 2006.183.07:52:28.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.07:52:28.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.07:52:28.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:28.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:28.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:28.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:28.20#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:52:28.20#ibcon#first serial, iclass 19, count 0 2006.183.07:52:28.20#ibcon#enter sib2, iclass 19, count 0 2006.183.07:52:28.20#ibcon#flushed, iclass 19, count 0 2006.183.07:52:28.20#ibcon#about to write, iclass 19, count 0 2006.183.07:52:28.20#ibcon#wrote, iclass 19, count 0 2006.183.07:52:28.20#ibcon#about to read 3, iclass 19, count 0 2006.183.07:52:28.22#ibcon#read 3, iclass 19, count 0 2006.183.07:52:28.22#ibcon#about to read 4, iclass 19, count 0 2006.183.07:52:28.22#ibcon#read 4, iclass 19, count 0 2006.183.07:52:28.22#ibcon#about to read 5, iclass 19, count 0 2006.183.07:52:28.22#ibcon#read 5, iclass 19, count 0 2006.183.07:52:28.22#ibcon#about to read 6, iclass 19, count 0 2006.183.07:52:28.22#ibcon#read 6, iclass 19, count 0 2006.183.07:52:28.22#ibcon#end of sib2, iclass 19, count 0 2006.183.07:52:28.22#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:52:28.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:52:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:52:28.22#ibcon#*before write, iclass 19, count 0 2006.183.07:52:28.22#ibcon#enter sib2, iclass 19, count 0 2006.183.07:52:28.22#ibcon#flushed, iclass 19, count 0 2006.183.07:52:28.22#ibcon#about to write, iclass 19, count 0 2006.183.07:52:28.22#ibcon#wrote, iclass 19, count 0 2006.183.07:52:28.22#ibcon#about to read 3, iclass 19, count 0 2006.183.07:52:28.26#ibcon#read 3, iclass 19, count 0 2006.183.07:52:28.26#ibcon#about to read 4, iclass 19, count 0 2006.183.07:52:28.26#ibcon#read 4, iclass 19, count 0 2006.183.07:52:28.26#ibcon#about to read 5, iclass 19, count 0 2006.183.07:52:28.26#ibcon#read 5, iclass 19, count 0 2006.183.07:52:28.26#ibcon#about to read 6, iclass 19, count 0 2006.183.07:52:28.26#ibcon#read 6, iclass 19, count 0 2006.183.07:52:28.26#ibcon#end of sib2, iclass 19, count 0 2006.183.07:52:28.26#ibcon#*after write, iclass 19, count 0 2006.183.07:52:28.26#ibcon#*before return 0, iclass 19, count 0 2006.183.07:52:28.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:28.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:28.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:52:28.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:52:28.26$vc4f8/va=2,7 2006.183.07:52:28.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.07:52:28.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.07:52:28.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:28.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:28.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:28.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:28.33#ibcon#enter wrdev, iclass 21, count 2 2006.183.07:52:28.33#ibcon#first serial, iclass 21, count 2 2006.183.07:52:28.33#ibcon#enter sib2, iclass 21, count 2 2006.183.07:52:28.33#ibcon#flushed, iclass 21, count 2 2006.183.07:52:28.33#ibcon#about to write, iclass 21, count 2 2006.183.07:52:28.33#ibcon#wrote, iclass 21, count 2 2006.183.07:52:28.33#ibcon#about to read 3, iclass 21, count 2 2006.183.07:52:28.34#ibcon#read 3, iclass 21, count 2 2006.183.07:52:28.34#ibcon#about to read 4, iclass 21, count 2 2006.183.07:52:28.34#ibcon#read 4, iclass 21, count 2 2006.183.07:52:28.34#ibcon#about to read 5, iclass 21, count 2 2006.183.07:52:28.34#ibcon#read 5, iclass 21, count 2 2006.183.07:52:28.34#ibcon#about to read 6, iclass 21, count 2 2006.183.07:52:28.34#ibcon#read 6, iclass 21, count 2 2006.183.07:52:28.34#ibcon#end of sib2, iclass 21, count 2 2006.183.07:52:28.34#ibcon#*mode == 0, iclass 21, count 2 2006.183.07:52:28.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.07:52:28.34#ibcon#[25=AT02-07\r\n] 2006.183.07:52:28.34#ibcon#*before write, iclass 21, count 2 2006.183.07:52:28.34#ibcon#enter sib2, iclass 21, count 2 2006.183.07:52:28.34#ibcon#flushed, iclass 21, count 2 2006.183.07:52:28.34#ibcon#about to write, iclass 21, count 2 2006.183.07:52:28.34#ibcon#wrote, iclass 21, count 2 2006.183.07:52:28.34#ibcon#about to read 3, iclass 21, count 2 2006.183.07:52:28.37#ibcon#read 3, iclass 21, count 2 2006.183.07:52:28.37#ibcon#about to read 4, iclass 21, count 2 2006.183.07:52:28.37#ibcon#read 4, iclass 21, count 2 2006.183.07:52:28.37#ibcon#about to read 5, iclass 21, count 2 2006.183.07:52:28.37#ibcon#read 5, iclass 21, count 2 2006.183.07:52:28.37#ibcon#about to read 6, iclass 21, count 2 2006.183.07:52:28.37#ibcon#read 6, iclass 21, count 2 2006.183.07:52:28.37#ibcon#end of sib2, iclass 21, count 2 2006.183.07:52:28.37#ibcon#*after write, iclass 21, count 2 2006.183.07:52:28.37#ibcon#*before return 0, iclass 21, count 2 2006.183.07:52:28.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:28.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:28.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.07:52:28.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:28.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:28.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:28.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:28.49#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:52:28.49#ibcon#first serial, iclass 21, count 0 2006.183.07:52:28.49#ibcon#enter sib2, iclass 21, count 0 2006.183.07:52:28.49#ibcon#flushed, iclass 21, count 0 2006.183.07:52:28.49#ibcon#about to write, iclass 21, count 0 2006.183.07:52:28.49#ibcon#wrote, iclass 21, count 0 2006.183.07:52:28.49#ibcon#about to read 3, iclass 21, count 0 2006.183.07:52:28.51#ibcon#read 3, iclass 21, count 0 2006.183.07:52:28.51#ibcon#about to read 4, iclass 21, count 0 2006.183.07:52:28.51#ibcon#read 4, iclass 21, count 0 2006.183.07:52:28.51#ibcon#about to read 5, iclass 21, count 0 2006.183.07:52:28.51#ibcon#read 5, iclass 21, count 0 2006.183.07:52:28.51#ibcon#about to read 6, iclass 21, count 0 2006.183.07:52:28.51#ibcon#read 6, iclass 21, count 0 2006.183.07:52:28.51#ibcon#end of sib2, iclass 21, count 0 2006.183.07:52:28.51#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:52:28.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:52:28.51#ibcon#[25=USB\r\n] 2006.183.07:52:28.51#ibcon#*before write, iclass 21, count 0 2006.183.07:52:28.51#ibcon#enter sib2, iclass 21, count 0 2006.183.07:52:28.51#ibcon#flushed, iclass 21, count 0 2006.183.07:52:28.51#ibcon#about to write, iclass 21, count 0 2006.183.07:52:28.51#ibcon#wrote, iclass 21, count 0 2006.183.07:52:28.51#ibcon#about to read 3, iclass 21, count 0 2006.183.07:52:28.54#ibcon#read 3, iclass 21, count 0 2006.183.07:52:28.54#ibcon#about to read 4, iclass 21, count 0 2006.183.07:52:28.54#ibcon#read 4, iclass 21, count 0 2006.183.07:52:28.54#ibcon#about to read 5, iclass 21, count 0 2006.183.07:52:28.54#ibcon#read 5, iclass 21, count 0 2006.183.07:52:28.54#ibcon#about to read 6, iclass 21, count 0 2006.183.07:52:28.54#ibcon#read 6, iclass 21, count 0 2006.183.07:52:28.54#ibcon#end of sib2, iclass 21, count 0 2006.183.07:52:28.54#ibcon#*after write, iclass 21, count 0 2006.183.07:52:28.54#ibcon#*before return 0, iclass 21, count 0 2006.183.07:52:28.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:28.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:28.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:52:28.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:52:28.54$vc4f8/valo=3,672.99 2006.183.07:52:28.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.07:52:28.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.07:52:28.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:28.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:28.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:28.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:28.54#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:52:28.54#ibcon#first serial, iclass 23, count 0 2006.183.07:52:28.54#ibcon#enter sib2, iclass 23, count 0 2006.183.07:52:28.54#ibcon#flushed, iclass 23, count 0 2006.183.07:52:28.54#ibcon#about to write, iclass 23, count 0 2006.183.07:52:28.54#ibcon#wrote, iclass 23, count 0 2006.183.07:52:28.54#ibcon#about to read 3, iclass 23, count 0 2006.183.07:52:28.56#ibcon#read 3, iclass 23, count 0 2006.183.07:52:28.56#ibcon#about to read 4, iclass 23, count 0 2006.183.07:52:28.56#ibcon#read 4, iclass 23, count 0 2006.183.07:52:28.56#ibcon#about to read 5, iclass 23, count 0 2006.183.07:52:28.56#ibcon#read 5, iclass 23, count 0 2006.183.07:52:28.56#ibcon#about to read 6, iclass 23, count 0 2006.183.07:52:28.56#ibcon#read 6, iclass 23, count 0 2006.183.07:52:28.56#ibcon#end of sib2, iclass 23, count 0 2006.183.07:52:28.56#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:52:28.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:52:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:52:28.56#ibcon#*before write, iclass 23, count 0 2006.183.07:52:28.56#ibcon#enter sib2, iclass 23, count 0 2006.183.07:52:28.56#ibcon#flushed, iclass 23, count 0 2006.183.07:52:28.56#ibcon#about to write, iclass 23, count 0 2006.183.07:52:28.56#ibcon#wrote, iclass 23, count 0 2006.183.07:52:28.56#ibcon#about to read 3, iclass 23, count 0 2006.183.07:52:28.60#ibcon#read 3, iclass 23, count 0 2006.183.07:52:28.60#ibcon#about to read 4, iclass 23, count 0 2006.183.07:52:28.60#ibcon#read 4, iclass 23, count 0 2006.183.07:52:28.60#ibcon#about to read 5, iclass 23, count 0 2006.183.07:52:28.60#ibcon#read 5, iclass 23, count 0 2006.183.07:52:28.60#ibcon#about to read 6, iclass 23, count 0 2006.183.07:52:28.60#ibcon#read 6, iclass 23, count 0 2006.183.07:52:28.60#ibcon#end of sib2, iclass 23, count 0 2006.183.07:52:28.60#ibcon#*after write, iclass 23, count 0 2006.183.07:52:28.60#ibcon#*before return 0, iclass 23, count 0 2006.183.07:52:28.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:28.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:28.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:52:28.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:52:28.60$vc4f8/va=3,6 2006.183.07:52:28.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.07:52:28.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.07:52:28.60#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:28.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:28.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:28.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:28.67#ibcon#enter wrdev, iclass 25, count 2 2006.183.07:52:28.67#ibcon#first serial, iclass 25, count 2 2006.183.07:52:28.67#ibcon#enter sib2, iclass 25, count 2 2006.183.07:52:28.67#ibcon#flushed, iclass 25, count 2 2006.183.07:52:28.67#ibcon#about to write, iclass 25, count 2 2006.183.07:52:28.67#ibcon#wrote, iclass 25, count 2 2006.183.07:52:28.67#ibcon#about to read 3, iclass 25, count 2 2006.183.07:52:28.68#ibcon#read 3, iclass 25, count 2 2006.183.07:52:28.68#ibcon#about to read 4, iclass 25, count 2 2006.183.07:52:28.68#ibcon#read 4, iclass 25, count 2 2006.183.07:52:28.68#ibcon#about to read 5, iclass 25, count 2 2006.183.07:52:28.68#ibcon#read 5, iclass 25, count 2 2006.183.07:52:28.68#ibcon#about to read 6, iclass 25, count 2 2006.183.07:52:28.68#ibcon#read 6, iclass 25, count 2 2006.183.07:52:28.68#ibcon#end of sib2, iclass 25, count 2 2006.183.07:52:28.68#ibcon#*mode == 0, iclass 25, count 2 2006.183.07:52:28.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.07:52:28.68#ibcon#[25=AT03-06\r\n] 2006.183.07:52:28.68#ibcon#*before write, iclass 25, count 2 2006.183.07:52:28.68#ibcon#enter sib2, iclass 25, count 2 2006.183.07:52:28.68#ibcon#flushed, iclass 25, count 2 2006.183.07:52:28.68#ibcon#about to write, iclass 25, count 2 2006.183.07:52:28.68#ibcon#wrote, iclass 25, count 2 2006.183.07:52:28.68#ibcon#about to read 3, iclass 25, count 2 2006.183.07:52:28.71#ibcon#read 3, iclass 25, count 2 2006.183.07:52:28.71#ibcon#about to read 4, iclass 25, count 2 2006.183.07:52:28.71#ibcon#read 4, iclass 25, count 2 2006.183.07:52:28.71#ibcon#about to read 5, iclass 25, count 2 2006.183.07:52:28.71#ibcon#read 5, iclass 25, count 2 2006.183.07:52:28.71#ibcon#about to read 6, iclass 25, count 2 2006.183.07:52:28.71#ibcon#read 6, iclass 25, count 2 2006.183.07:52:28.71#ibcon#end of sib2, iclass 25, count 2 2006.183.07:52:28.71#ibcon#*after write, iclass 25, count 2 2006.183.07:52:28.71#ibcon#*before return 0, iclass 25, count 2 2006.183.07:52:28.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:28.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:28.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.07:52:28.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:28.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:28.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:28.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:28.83#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:52:28.83#ibcon#first serial, iclass 25, count 0 2006.183.07:52:28.83#ibcon#enter sib2, iclass 25, count 0 2006.183.07:52:28.83#ibcon#flushed, iclass 25, count 0 2006.183.07:52:28.83#ibcon#about to write, iclass 25, count 0 2006.183.07:52:28.83#ibcon#wrote, iclass 25, count 0 2006.183.07:52:28.83#ibcon#about to read 3, iclass 25, count 0 2006.183.07:52:28.85#ibcon#read 3, iclass 25, count 0 2006.183.07:52:28.85#ibcon#about to read 4, iclass 25, count 0 2006.183.07:52:28.85#ibcon#read 4, iclass 25, count 0 2006.183.07:52:28.85#ibcon#about to read 5, iclass 25, count 0 2006.183.07:52:28.85#ibcon#read 5, iclass 25, count 0 2006.183.07:52:28.85#ibcon#about to read 6, iclass 25, count 0 2006.183.07:52:28.85#ibcon#read 6, iclass 25, count 0 2006.183.07:52:28.85#ibcon#end of sib2, iclass 25, count 0 2006.183.07:52:28.85#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:52:28.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:52:28.85#ibcon#[25=USB\r\n] 2006.183.07:52:28.85#ibcon#*before write, iclass 25, count 0 2006.183.07:52:28.85#ibcon#enter sib2, iclass 25, count 0 2006.183.07:52:28.85#ibcon#flushed, iclass 25, count 0 2006.183.07:52:28.85#ibcon#about to write, iclass 25, count 0 2006.183.07:52:28.85#ibcon#wrote, iclass 25, count 0 2006.183.07:52:28.85#ibcon#about to read 3, iclass 25, count 0 2006.183.07:52:28.88#ibcon#read 3, iclass 25, count 0 2006.183.07:52:28.88#ibcon#about to read 4, iclass 25, count 0 2006.183.07:52:28.88#ibcon#read 4, iclass 25, count 0 2006.183.07:52:28.88#ibcon#about to read 5, iclass 25, count 0 2006.183.07:52:28.88#ibcon#read 5, iclass 25, count 0 2006.183.07:52:28.88#ibcon#about to read 6, iclass 25, count 0 2006.183.07:52:28.88#ibcon#read 6, iclass 25, count 0 2006.183.07:52:28.88#ibcon#end of sib2, iclass 25, count 0 2006.183.07:52:28.88#ibcon#*after write, iclass 25, count 0 2006.183.07:52:28.88#ibcon#*before return 0, iclass 25, count 0 2006.183.07:52:28.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:28.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:28.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:52:28.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:52:28.88$vc4f8/valo=4,832.99 2006.183.07:52:28.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.07:52:28.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.07:52:28.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:28.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:28.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:28.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:28.88#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:52:28.88#ibcon#first serial, iclass 27, count 0 2006.183.07:52:28.88#ibcon#enter sib2, iclass 27, count 0 2006.183.07:52:28.88#ibcon#flushed, iclass 27, count 0 2006.183.07:52:28.88#ibcon#about to write, iclass 27, count 0 2006.183.07:52:28.88#ibcon#wrote, iclass 27, count 0 2006.183.07:52:28.88#ibcon#about to read 3, iclass 27, count 0 2006.183.07:52:28.90#ibcon#read 3, iclass 27, count 0 2006.183.07:52:28.90#ibcon#about to read 4, iclass 27, count 0 2006.183.07:52:28.90#ibcon#read 4, iclass 27, count 0 2006.183.07:52:28.90#ibcon#about to read 5, iclass 27, count 0 2006.183.07:52:28.90#ibcon#read 5, iclass 27, count 0 2006.183.07:52:28.90#ibcon#about to read 6, iclass 27, count 0 2006.183.07:52:28.90#ibcon#read 6, iclass 27, count 0 2006.183.07:52:28.90#ibcon#end of sib2, iclass 27, count 0 2006.183.07:52:28.90#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:52:28.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:52:28.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:52:28.90#ibcon#*before write, iclass 27, count 0 2006.183.07:52:28.90#ibcon#enter sib2, iclass 27, count 0 2006.183.07:52:28.90#ibcon#flushed, iclass 27, count 0 2006.183.07:52:28.90#ibcon#about to write, iclass 27, count 0 2006.183.07:52:28.90#ibcon#wrote, iclass 27, count 0 2006.183.07:52:28.90#ibcon#about to read 3, iclass 27, count 0 2006.183.07:52:28.94#ibcon#read 3, iclass 27, count 0 2006.183.07:52:28.94#ibcon#about to read 4, iclass 27, count 0 2006.183.07:52:28.94#ibcon#read 4, iclass 27, count 0 2006.183.07:52:28.94#ibcon#about to read 5, iclass 27, count 0 2006.183.07:52:28.94#ibcon#read 5, iclass 27, count 0 2006.183.07:52:28.94#ibcon#about to read 6, iclass 27, count 0 2006.183.07:52:28.94#ibcon#read 6, iclass 27, count 0 2006.183.07:52:28.94#ibcon#end of sib2, iclass 27, count 0 2006.183.07:52:28.94#ibcon#*after write, iclass 27, count 0 2006.183.07:52:28.94#ibcon#*before return 0, iclass 27, count 0 2006.183.07:52:28.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:28.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:28.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:52:28.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:52:28.94$vc4f8/va=4,7 2006.183.07:52:28.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.07:52:28.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.07:52:28.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:28.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:29.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:29.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:29.00#ibcon#enter wrdev, iclass 29, count 2 2006.183.07:52:29.00#ibcon#first serial, iclass 29, count 2 2006.183.07:52:29.00#ibcon#enter sib2, iclass 29, count 2 2006.183.07:52:29.00#ibcon#flushed, iclass 29, count 2 2006.183.07:52:29.00#ibcon#about to write, iclass 29, count 2 2006.183.07:52:29.00#ibcon#wrote, iclass 29, count 2 2006.183.07:52:29.00#ibcon#about to read 3, iclass 29, count 2 2006.183.07:52:29.02#ibcon#read 3, iclass 29, count 2 2006.183.07:52:29.02#ibcon#about to read 4, iclass 29, count 2 2006.183.07:52:29.02#ibcon#read 4, iclass 29, count 2 2006.183.07:52:29.02#ibcon#about to read 5, iclass 29, count 2 2006.183.07:52:29.02#ibcon#read 5, iclass 29, count 2 2006.183.07:52:29.02#ibcon#about to read 6, iclass 29, count 2 2006.183.07:52:29.02#ibcon#read 6, iclass 29, count 2 2006.183.07:52:29.02#ibcon#end of sib2, iclass 29, count 2 2006.183.07:52:29.02#ibcon#*mode == 0, iclass 29, count 2 2006.183.07:52:29.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.07:52:29.02#ibcon#[25=AT04-07\r\n] 2006.183.07:52:29.02#ibcon#*before write, iclass 29, count 2 2006.183.07:52:29.02#ibcon#enter sib2, iclass 29, count 2 2006.183.07:52:29.02#ibcon#flushed, iclass 29, count 2 2006.183.07:52:29.02#ibcon#about to write, iclass 29, count 2 2006.183.07:52:29.02#ibcon#wrote, iclass 29, count 2 2006.183.07:52:29.02#ibcon#about to read 3, iclass 29, count 2 2006.183.07:52:29.05#ibcon#read 3, iclass 29, count 2 2006.183.07:52:29.05#ibcon#about to read 4, iclass 29, count 2 2006.183.07:52:29.05#ibcon#read 4, iclass 29, count 2 2006.183.07:52:29.05#ibcon#about to read 5, iclass 29, count 2 2006.183.07:52:29.05#ibcon#read 5, iclass 29, count 2 2006.183.07:52:29.05#ibcon#about to read 6, iclass 29, count 2 2006.183.07:52:29.05#ibcon#read 6, iclass 29, count 2 2006.183.07:52:29.05#ibcon#end of sib2, iclass 29, count 2 2006.183.07:52:29.05#ibcon#*after write, iclass 29, count 2 2006.183.07:52:29.05#ibcon#*before return 0, iclass 29, count 2 2006.183.07:52:29.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:29.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:29.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.07:52:29.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:29.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:29.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:29.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:29.17#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:52:29.17#ibcon#first serial, iclass 29, count 0 2006.183.07:52:29.17#ibcon#enter sib2, iclass 29, count 0 2006.183.07:52:29.17#ibcon#flushed, iclass 29, count 0 2006.183.07:52:29.17#ibcon#about to write, iclass 29, count 0 2006.183.07:52:29.17#ibcon#wrote, iclass 29, count 0 2006.183.07:52:29.17#ibcon#about to read 3, iclass 29, count 0 2006.183.07:52:29.19#ibcon#read 3, iclass 29, count 0 2006.183.07:52:29.19#ibcon#about to read 4, iclass 29, count 0 2006.183.07:52:29.19#ibcon#read 4, iclass 29, count 0 2006.183.07:52:29.19#ibcon#about to read 5, iclass 29, count 0 2006.183.07:52:29.19#ibcon#read 5, iclass 29, count 0 2006.183.07:52:29.19#ibcon#about to read 6, iclass 29, count 0 2006.183.07:52:29.19#ibcon#read 6, iclass 29, count 0 2006.183.07:52:29.19#ibcon#end of sib2, iclass 29, count 0 2006.183.07:52:29.19#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:52:29.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:52:29.19#ibcon#[25=USB\r\n] 2006.183.07:52:29.19#ibcon#*before write, iclass 29, count 0 2006.183.07:52:29.19#ibcon#enter sib2, iclass 29, count 0 2006.183.07:52:29.19#ibcon#flushed, iclass 29, count 0 2006.183.07:52:29.19#ibcon#about to write, iclass 29, count 0 2006.183.07:52:29.19#ibcon#wrote, iclass 29, count 0 2006.183.07:52:29.19#ibcon#about to read 3, iclass 29, count 0 2006.183.07:52:29.22#ibcon#read 3, iclass 29, count 0 2006.183.07:52:29.22#ibcon#about to read 4, iclass 29, count 0 2006.183.07:52:29.22#ibcon#read 4, iclass 29, count 0 2006.183.07:52:29.22#ibcon#about to read 5, iclass 29, count 0 2006.183.07:52:29.22#ibcon#read 5, iclass 29, count 0 2006.183.07:52:29.22#ibcon#about to read 6, iclass 29, count 0 2006.183.07:52:29.22#ibcon#read 6, iclass 29, count 0 2006.183.07:52:29.22#ibcon#end of sib2, iclass 29, count 0 2006.183.07:52:29.22#ibcon#*after write, iclass 29, count 0 2006.183.07:52:29.22#ibcon#*before return 0, iclass 29, count 0 2006.183.07:52:29.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:29.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:29.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:52:29.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:52:29.22$vc4f8/valo=5,652.99 2006.183.07:52:29.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.07:52:29.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.07:52:29.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:29.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:29.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:29.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:29.22#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:52:29.22#ibcon#first serial, iclass 31, count 0 2006.183.07:52:29.22#ibcon#enter sib2, iclass 31, count 0 2006.183.07:52:29.22#ibcon#flushed, iclass 31, count 0 2006.183.07:52:29.22#ibcon#about to write, iclass 31, count 0 2006.183.07:52:29.22#ibcon#wrote, iclass 31, count 0 2006.183.07:52:29.22#ibcon#about to read 3, iclass 31, count 0 2006.183.07:52:29.24#ibcon#read 3, iclass 31, count 0 2006.183.07:52:29.24#ibcon#about to read 4, iclass 31, count 0 2006.183.07:52:29.24#ibcon#read 4, iclass 31, count 0 2006.183.07:52:29.24#ibcon#about to read 5, iclass 31, count 0 2006.183.07:52:29.24#ibcon#read 5, iclass 31, count 0 2006.183.07:52:29.24#ibcon#about to read 6, iclass 31, count 0 2006.183.07:52:29.24#ibcon#read 6, iclass 31, count 0 2006.183.07:52:29.24#ibcon#end of sib2, iclass 31, count 0 2006.183.07:52:29.24#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:52:29.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:52:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:52:29.24#ibcon#*before write, iclass 31, count 0 2006.183.07:52:29.24#ibcon#enter sib2, iclass 31, count 0 2006.183.07:52:29.24#ibcon#flushed, iclass 31, count 0 2006.183.07:52:29.24#ibcon#about to write, iclass 31, count 0 2006.183.07:52:29.24#ibcon#wrote, iclass 31, count 0 2006.183.07:52:29.24#ibcon#about to read 3, iclass 31, count 0 2006.183.07:52:29.28#ibcon#read 3, iclass 31, count 0 2006.183.07:52:29.28#ibcon#about to read 4, iclass 31, count 0 2006.183.07:52:29.28#ibcon#read 4, iclass 31, count 0 2006.183.07:52:29.28#ibcon#about to read 5, iclass 31, count 0 2006.183.07:52:29.28#ibcon#read 5, iclass 31, count 0 2006.183.07:52:29.28#ibcon#about to read 6, iclass 31, count 0 2006.183.07:52:29.28#ibcon#read 6, iclass 31, count 0 2006.183.07:52:29.28#ibcon#end of sib2, iclass 31, count 0 2006.183.07:52:29.28#ibcon#*after write, iclass 31, count 0 2006.183.07:52:29.28#ibcon#*before return 0, iclass 31, count 0 2006.183.07:52:29.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:29.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:29.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:52:29.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:52:29.28$vc4f8/va=5,7 2006.183.07:52:29.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.07:52:29.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.07:52:29.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:29.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:29.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:29.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:29.34#ibcon#enter wrdev, iclass 33, count 2 2006.183.07:52:29.34#ibcon#first serial, iclass 33, count 2 2006.183.07:52:29.34#ibcon#enter sib2, iclass 33, count 2 2006.183.07:52:29.34#ibcon#flushed, iclass 33, count 2 2006.183.07:52:29.34#ibcon#about to write, iclass 33, count 2 2006.183.07:52:29.34#ibcon#wrote, iclass 33, count 2 2006.183.07:52:29.34#ibcon#about to read 3, iclass 33, count 2 2006.183.07:52:29.36#ibcon#read 3, iclass 33, count 2 2006.183.07:52:29.36#ibcon#about to read 4, iclass 33, count 2 2006.183.07:52:29.36#ibcon#read 4, iclass 33, count 2 2006.183.07:52:29.36#ibcon#about to read 5, iclass 33, count 2 2006.183.07:52:29.36#ibcon#read 5, iclass 33, count 2 2006.183.07:52:29.36#ibcon#about to read 6, iclass 33, count 2 2006.183.07:52:29.36#ibcon#read 6, iclass 33, count 2 2006.183.07:52:29.36#ibcon#end of sib2, iclass 33, count 2 2006.183.07:52:29.36#ibcon#*mode == 0, iclass 33, count 2 2006.183.07:52:29.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.07:52:29.36#ibcon#[25=AT05-07\r\n] 2006.183.07:52:29.36#ibcon#*before write, iclass 33, count 2 2006.183.07:52:29.36#ibcon#enter sib2, iclass 33, count 2 2006.183.07:52:29.36#ibcon#flushed, iclass 33, count 2 2006.183.07:52:29.36#ibcon#about to write, iclass 33, count 2 2006.183.07:52:29.36#ibcon#wrote, iclass 33, count 2 2006.183.07:52:29.36#ibcon#about to read 3, iclass 33, count 2 2006.183.07:52:29.39#ibcon#read 3, iclass 33, count 2 2006.183.07:52:29.39#ibcon#about to read 4, iclass 33, count 2 2006.183.07:52:29.39#ibcon#read 4, iclass 33, count 2 2006.183.07:52:29.39#ibcon#about to read 5, iclass 33, count 2 2006.183.07:52:29.39#ibcon#read 5, iclass 33, count 2 2006.183.07:52:29.39#ibcon#about to read 6, iclass 33, count 2 2006.183.07:52:29.39#ibcon#read 6, iclass 33, count 2 2006.183.07:52:29.39#ibcon#end of sib2, iclass 33, count 2 2006.183.07:52:29.39#ibcon#*after write, iclass 33, count 2 2006.183.07:52:29.39#ibcon#*before return 0, iclass 33, count 2 2006.183.07:52:29.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:29.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:29.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.07:52:29.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:29.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:29.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:29.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:29.51#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:52:29.51#ibcon#first serial, iclass 33, count 0 2006.183.07:52:29.51#ibcon#enter sib2, iclass 33, count 0 2006.183.07:52:29.51#ibcon#flushed, iclass 33, count 0 2006.183.07:52:29.51#ibcon#about to write, iclass 33, count 0 2006.183.07:52:29.51#ibcon#wrote, iclass 33, count 0 2006.183.07:52:29.51#ibcon#about to read 3, iclass 33, count 0 2006.183.07:52:29.53#ibcon#read 3, iclass 33, count 0 2006.183.07:52:29.53#ibcon#about to read 4, iclass 33, count 0 2006.183.07:52:29.53#ibcon#read 4, iclass 33, count 0 2006.183.07:52:29.53#ibcon#about to read 5, iclass 33, count 0 2006.183.07:52:29.53#ibcon#read 5, iclass 33, count 0 2006.183.07:52:29.53#ibcon#about to read 6, iclass 33, count 0 2006.183.07:52:29.53#ibcon#read 6, iclass 33, count 0 2006.183.07:52:29.53#ibcon#end of sib2, iclass 33, count 0 2006.183.07:52:29.53#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:52:29.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:52:29.53#ibcon#[25=USB\r\n] 2006.183.07:52:29.53#ibcon#*before write, iclass 33, count 0 2006.183.07:52:29.53#ibcon#enter sib2, iclass 33, count 0 2006.183.07:52:29.53#ibcon#flushed, iclass 33, count 0 2006.183.07:52:29.53#ibcon#about to write, iclass 33, count 0 2006.183.07:52:29.53#ibcon#wrote, iclass 33, count 0 2006.183.07:52:29.53#ibcon#about to read 3, iclass 33, count 0 2006.183.07:52:29.56#ibcon#read 3, iclass 33, count 0 2006.183.07:52:29.56#ibcon#about to read 4, iclass 33, count 0 2006.183.07:52:29.56#ibcon#read 4, iclass 33, count 0 2006.183.07:52:29.56#ibcon#about to read 5, iclass 33, count 0 2006.183.07:52:29.56#ibcon#read 5, iclass 33, count 0 2006.183.07:52:29.56#ibcon#about to read 6, iclass 33, count 0 2006.183.07:52:29.56#ibcon#read 6, iclass 33, count 0 2006.183.07:52:29.56#ibcon#end of sib2, iclass 33, count 0 2006.183.07:52:29.56#ibcon#*after write, iclass 33, count 0 2006.183.07:52:29.56#ibcon#*before return 0, iclass 33, count 0 2006.183.07:52:29.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:29.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:29.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:52:29.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:52:29.56$vc4f8/valo=6,772.99 2006.183.07:52:29.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.07:52:29.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.07:52:29.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:29.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:29.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:29.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:29.56#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:52:29.56#ibcon#first serial, iclass 35, count 0 2006.183.07:52:29.56#ibcon#enter sib2, iclass 35, count 0 2006.183.07:52:29.56#ibcon#flushed, iclass 35, count 0 2006.183.07:52:29.56#ibcon#about to write, iclass 35, count 0 2006.183.07:52:29.56#ibcon#wrote, iclass 35, count 0 2006.183.07:52:29.56#ibcon#about to read 3, iclass 35, count 0 2006.183.07:52:29.58#ibcon#read 3, iclass 35, count 0 2006.183.07:52:29.58#ibcon#about to read 4, iclass 35, count 0 2006.183.07:52:29.58#ibcon#read 4, iclass 35, count 0 2006.183.07:52:29.58#ibcon#about to read 5, iclass 35, count 0 2006.183.07:52:29.58#ibcon#read 5, iclass 35, count 0 2006.183.07:52:29.58#ibcon#about to read 6, iclass 35, count 0 2006.183.07:52:29.58#ibcon#read 6, iclass 35, count 0 2006.183.07:52:29.58#ibcon#end of sib2, iclass 35, count 0 2006.183.07:52:29.58#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:52:29.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:52:29.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:52:29.58#ibcon#*before write, iclass 35, count 0 2006.183.07:52:29.58#ibcon#enter sib2, iclass 35, count 0 2006.183.07:52:29.58#ibcon#flushed, iclass 35, count 0 2006.183.07:52:29.58#ibcon#about to write, iclass 35, count 0 2006.183.07:52:29.58#ibcon#wrote, iclass 35, count 0 2006.183.07:52:29.58#ibcon#about to read 3, iclass 35, count 0 2006.183.07:52:29.62#ibcon#read 3, iclass 35, count 0 2006.183.07:52:29.62#ibcon#about to read 4, iclass 35, count 0 2006.183.07:52:29.62#ibcon#read 4, iclass 35, count 0 2006.183.07:52:29.62#ibcon#about to read 5, iclass 35, count 0 2006.183.07:52:29.62#ibcon#read 5, iclass 35, count 0 2006.183.07:52:29.62#ibcon#about to read 6, iclass 35, count 0 2006.183.07:52:29.62#ibcon#read 6, iclass 35, count 0 2006.183.07:52:29.62#ibcon#end of sib2, iclass 35, count 0 2006.183.07:52:29.62#ibcon#*after write, iclass 35, count 0 2006.183.07:52:29.62#ibcon#*before return 0, iclass 35, count 0 2006.183.07:52:29.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:29.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:29.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:52:29.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:52:29.62$vc4f8/va=6,6 2006.183.07:52:29.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.07:52:29.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.07:52:29.62#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:29.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:29.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:29.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:29.69#ibcon#enter wrdev, iclass 37, count 2 2006.183.07:52:29.69#ibcon#first serial, iclass 37, count 2 2006.183.07:52:29.69#ibcon#enter sib2, iclass 37, count 2 2006.183.07:52:29.69#ibcon#flushed, iclass 37, count 2 2006.183.07:52:29.69#ibcon#about to write, iclass 37, count 2 2006.183.07:52:29.69#ibcon#wrote, iclass 37, count 2 2006.183.07:52:29.69#ibcon#about to read 3, iclass 37, count 2 2006.183.07:52:29.70#abcon#<5=/09 2.0 5.9 27.97 88 996.4\r\n> 2006.183.07:52:29.70#ibcon#read 3, iclass 37, count 2 2006.183.07:52:29.70#ibcon#about to read 4, iclass 37, count 2 2006.183.07:52:29.70#ibcon#read 4, iclass 37, count 2 2006.183.07:52:29.70#ibcon#about to read 5, iclass 37, count 2 2006.183.07:52:29.70#ibcon#read 5, iclass 37, count 2 2006.183.07:52:29.70#ibcon#about to read 6, iclass 37, count 2 2006.183.07:52:29.70#ibcon#read 6, iclass 37, count 2 2006.183.07:52:29.70#ibcon#end of sib2, iclass 37, count 2 2006.183.07:52:29.70#ibcon#*mode == 0, iclass 37, count 2 2006.183.07:52:29.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.07:52:29.70#ibcon#[25=AT06-06\r\n] 2006.183.07:52:29.70#ibcon#*before write, iclass 37, count 2 2006.183.07:52:29.70#ibcon#enter sib2, iclass 37, count 2 2006.183.07:52:29.70#ibcon#flushed, iclass 37, count 2 2006.183.07:52:29.70#ibcon#about to write, iclass 37, count 2 2006.183.07:52:29.70#ibcon#wrote, iclass 37, count 2 2006.183.07:52:29.70#ibcon#about to read 3, iclass 37, count 2 2006.183.07:52:29.72#abcon#{5=INTERFACE CLEAR} 2006.183.07:52:29.73#ibcon#read 3, iclass 37, count 2 2006.183.07:52:29.73#ibcon#about to read 4, iclass 37, count 2 2006.183.07:52:29.73#ibcon#read 4, iclass 37, count 2 2006.183.07:52:29.73#ibcon#about to read 5, iclass 37, count 2 2006.183.07:52:29.73#ibcon#read 5, iclass 37, count 2 2006.183.07:52:29.73#ibcon#about to read 6, iclass 37, count 2 2006.183.07:52:29.73#ibcon#read 6, iclass 37, count 2 2006.183.07:52:29.73#ibcon#end of sib2, iclass 37, count 2 2006.183.07:52:29.73#ibcon#*after write, iclass 37, count 2 2006.183.07:52:29.73#ibcon#*before return 0, iclass 37, count 2 2006.183.07:52:29.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:29.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:29.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.07:52:29.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:29.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:29.78#abcon#[5=S1D000X0/0*\r\n] 2006.183.07:52:29.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:29.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:29.85#ibcon#enter wrdev, iclass 37, count 0 2006.183.07:52:29.85#ibcon#first serial, iclass 37, count 0 2006.183.07:52:29.85#ibcon#enter sib2, iclass 37, count 0 2006.183.07:52:29.85#ibcon#flushed, iclass 37, count 0 2006.183.07:52:29.85#ibcon#about to write, iclass 37, count 0 2006.183.07:52:29.85#ibcon#wrote, iclass 37, count 0 2006.183.07:52:29.85#ibcon#about to read 3, iclass 37, count 0 2006.183.07:52:29.87#ibcon#read 3, iclass 37, count 0 2006.183.07:52:29.87#ibcon#about to read 4, iclass 37, count 0 2006.183.07:52:29.87#ibcon#read 4, iclass 37, count 0 2006.183.07:52:29.87#ibcon#about to read 5, iclass 37, count 0 2006.183.07:52:29.87#ibcon#read 5, iclass 37, count 0 2006.183.07:52:29.87#ibcon#about to read 6, iclass 37, count 0 2006.183.07:52:29.87#ibcon#read 6, iclass 37, count 0 2006.183.07:52:29.87#ibcon#end of sib2, iclass 37, count 0 2006.183.07:52:29.87#ibcon#*mode == 0, iclass 37, count 0 2006.183.07:52:29.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.07:52:29.87#ibcon#[25=USB\r\n] 2006.183.07:52:29.87#ibcon#*before write, iclass 37, count 0 2006.183.07:52:29.87#ibcon#enter sib2, iclass 37, count 0 2006.183.07:52:29.87#ibcon#flushed, iclass 37, count 0 2006.183.07:52:29.87#ibcon#about to write, iclass 37, count 0 2006.183.07:52:29.87#ibcon#wrote, iclass 37, count 0 2006.183.07:52:29.87#ibcon#about to read 3, iclass 37, count 0 2006.183.07:52:29.90#ibcon#read 3, iclass 37, count 0 2006.183.07:52:29.90#ibcon#about to read 4, iclass 37, count 0 2006.183.07:52:29.90#ibcon#read 4, iclass 37, count 0 2006.183.07:52:29.90#ibcon#about to read 5, iclass 37, count 0 2006.183.07:52:29.90#ibcon#read 5, iclass 37, count 0 2006.183.07:52:29.90#ibcon#about to read 6, iclass 37, count 0 2006.183.07:52:29.90#ibcon#read 6, iclass 37, count 0 2006.183.07:52:29.90#ibcon#end of sib2, iclass 37, count 0 2006.183.07:52:29.90#ibcon#*after write, iclass 37, count 0 2006.183.07:52:29.90#ibcon#*before return 0, iclass 37, count 0 2006.183.07:52:29.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:29.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:29.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.07:52:29.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.07:52:29.90$vc4f8/valo=7,832.99 2006.183.07:52:29.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.07:52:29.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.07:52:29.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:29.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:52:29.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:52:29.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:52:29.90#ibcon#enter wrdev, iclass 5, count 0 2006.183.07:52:29.90#ibcon#first serial, iclass 5, count 0 2006.183.07:52:29.90#ibcon#enter sib2, iclass 5, count 0 2006.183.07:52:29.90#ibcon#flushed, iclass 5, count 0 2006.183.07:52:29.90#ibcon#about to write, iclass 5, count 0 2006.183.07:52:29.90#ibcon#wrote, iclass 5, count 0 2006.183.07:52:29.90#ibcon#about to read 3, iclass 5, count 0 2006.183.07:52:29.92#ibcon#read 3, iclass 5, count 0 2006.183.07:52:29.92#ibcon#about to read 4, iclass 5, count 0 2006.183.07:52:29.92#ibcon#read 4, iclass 5, count 0 2006.183.07:52:29.92#ibcon#about to read 5, iclass 5, count 0 2006.183.07:52:29.92#ibcon#read 5, iclass 5, count 0 2006.183.07:52:29.92#ibcon#about to read 6, iclass 5, count 0 2006.183.07:52:29.92#ibcon#read 6, iclass 5, count 0 2006.183.07:52:29.92#ibcon#end of sib2, iclass 5, count 0 2006.183.07:52:29.92#ibcon#*mode == 0, iclass 5, count 0 2006.183.07:52:29.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.07:52:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:52:29.92#ibcon#*before write, iclass 5, count 0 2006.183.07:52:29.92#ibcon#enter sib2, iclass 5, count 0 2006.183.07:52:29.92#ibcon#flushed, iclass 5, count 0 2006.183.07:52:29.92#ibcon#about to write, iclass 5, count 0 2006.183.07:52:29.92#ibcon#wrote, iclass 5, count 0 2006.183.07:52:29.92#ibcon#about to read 3, iclass 5, count 0 2006.183.07:52:29.96#ibcon#read 3, iclass 5, count 0 2006.183.07:52:29.96#ibcon#about to read 4, iclass 5, count 0 2006.183.07:52:29.96#ibcon#read 4, iclass 5, count 0 2006.183.07:52:29.96#ibcon#about to read 5, iclass 5, count 0 2006.183.07:52:29.96#ibcon#read 5, iclass 5, count 0 2006.183.07:52:29.96#ibcon#about to read 6, iclass 5, count 0 2006.183.07:52:29.96#ibcon#read 6, iclass 5, count 0 2006.183.07:52:29.96#ibcon#end of sib2, iclass 5, count 0 2006.183.07:52:29.96#ibcon#*after write, iclass 5, count 0 2006.183.07:52:29.96#ibcon#*before return 0, iclass 5, count 0 2006.183.07:52:29.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:52:29.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.07:52:29.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.07:52:29.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.07:52:29.96$vc4f8/va=7,6 2006.183.07:52:29.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.07:52:29.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.07:52:29.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:29.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:52:30.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:52:30.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:52:30.02#ibcon#enter wrdev, iclass 7, count 2 2006.183.07:52:30.02#ibcon#first serial, iclass 7, count 2 2006.183.07:52:30.02#ibcon#enter sib2, iclass 7, count 2 2006.183.07:52:30.02#ibcon#flushed, iclass 7, count 2 2006.183.07:52:30.02#ibcon#about to write, iclass 7, count 2 2006.183.07:52:30.02#ibcon#wrote, iclass 7, count 2 2006.183.07:52:30.02#ibcon#about to read 3, iclass 7, count 2 2006.183.07:52:30.04#ibcon#read 3, iclass 7, count 2 2006.183.07:52:30.04#ibcon#about to read 4, iclass 7, count 2 2006.183.07:52:30.04#ibcon#read 4, iclass 7, count 2 2006.183.07:52:30.04#ibcon#about to read 5, iclass 7, count 2 2006.183.07:52:30.04#ibcon#read 5, iclass 7, count 2 2006.183.07:52:30.04#ibcon#about to read 6, iclass 7, count 2 2006.183.07:52:30.04#ibcon#read 6, iclass 7, count 2 2006.183.07:52:30.04#ibcon#end of sib2, iclass 7, count 2 2006.183.07:52:30.04#ibcon#*mode == 0, iclass 7, count 2 2006.183.07:52:30.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.07:52:30.04#ibcon#[25=AT07-06\r\n] 2006.183.07:52:30.04#ibcon#*before write, iclass 7, count 2 2006.183.07:52:30.04#ibcon#enter sib2, iclass 7, count 2 2006.183.07:52:30.04#ibcon#flushed, iclass 7, count 2 2006.183.07:52:30.04#ibcon#about to write, iclass 7, count 2 2006.183.07:52:30.04#ibcon#wrote, iclass 7, count 2 2006.183.07:52:30.04#ibcon#about to read 3, iclass 7, count 2 2006.183.07:52:30.07#ibcon#read 3, iclass 7, count 2 2006.183.07:52:30.07#ibcon#about to read 4, iclass 7, count 2 2006.183.07:52:30.07#ibcon#read 4, iclass 7, count 2 2006.183.07:52:30.07#ibcon#about to read 5, iclass 7, count 2 2006.183.07:52:30.07#ibcon#read 5, iclass 7, count 2 2006.183.07:52:30.07#ibcon#about to read 6, iclass 7, count 2 2006.183.07:52:30.07#ibcon#read 6, iclass 7, count 2 2006.183.07:52:30.07#ibcon#end of sib2, iclass 7, count 2 2006.183.07:52:30.07#ibcon#*after write, iclass 7, count 2 2006.183.07:52:30.07#ibcon#*before return 0, iclass 7, count 2 2006.183.07:52:30.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:52:30.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.07:52:30.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.07:52:30.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:30.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:52:30.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:52:30.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:52:30.19#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:52:30.19#ibcon#first serial, iclass 7, count 0 2006.183.07:52:30.19#ibcon#enter sib2, iclass 7, count 0 2006.183.07:52:30.19#ibcon#flushed, iclass 7, count 0 2006.183.07:52:30.19#ibcon#about to write, iclass 7, count 0 2006.183.07:52:30.19#ibcon#wrote, iclass 7, count 0 2006.183.07:52:30.19#ibcon#about to read 3, iclass 7, count 0 2006.183.07:52:30.21#ibcon#read 3, iclass 7, count 0 2006.183.07:52:30.21#ibcon#about to read 4, iclass 7, count 0 2006.183.07:52:30.21#ibcon#read 4, iclass 7, count 0 2006.183.07:52:30.21#ibcon#about to read 5, iclass 7, count 0 2006.183.07:52:30.21#ibcon#read 5, iclass 7, count 0 2006.183.07:52:30.21#ibcon#about to read 6, iclass 7, count 0 2006.183.07:52:30.21#ibcon#read 6, iclass 7, count 0 2006.183.07:52:30.21#ibcon#end of sib2, iclass 7, count 0 2006.183.07:52:30.21#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:52:30.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:52:30.21#ibcon#[25=USB\r\n] 2006.183.07:52:30.21#ibcon#*before write, iclass 7, count 0 2006.183.07:52:30.21#ibcon#enter sib2, iclass 7, count 0 2006.183.07:52:30.21#ibcon#flushed, iclass 7, count 0 2006.183.07:52:30.21#ibcon#about to write, iclass 7, count 0 2006.183.07:52:30.21#ibcon#wrote, iclass 7, count 0 2006.183.07:52:30.21#ibcon#about to read 3, iclass 7, count 0 2006.183.07:52:30.24#ibcon#read 3, iclass 7, count 0 2006.183.07:52:30.24#ibcon#about to read 4, iclass 7, count 0 2006.183.07:52:30.24#ibcon#read 4, iclass 7, count 0 2006.183.07:52:30.24#ibcon#about to read 5, iclass 7, count 0 2006.183.07:52:30.24#ibcon#read 5, iclass 7, count 0 2006.183.07:52:30.24#ibcon#about to read 6, iclass 7, count 0 2006.183.07:52:30.24#ibcon#read 6, iclass 7, count 0 2006.183.07:52:30.24#ibcon#end of sib2, iclass 7, count 0 2006.183.07:52:30.24#ibcon#*after write, iclass 7, count 0 2006.183.07:52:30.24#ibcon#*before return 0, iclass 7, count 0 2006.183.07:52:30.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:52:30.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.07:52:30.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:52:30.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:52:30.24$vc4f8/valo=8,852.99 2006.183.07:52:30.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.07:52:30.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.07:52:30.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:30.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:52:30.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:52:30.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:52:30.24#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:52:30.24#ibcon#first serial, iclass 11, count 0 2006.183.07:52:30.24#ibcon#enter sib2, iclass 11, count 0 2006.183.07:52:30.24#ibcon#flushed, iclass 11, count 0 2006.183.07:52:30.24#ibcon#about to write, iclass 11, count 0 2006.183.07:52:30.24#ibcon#wrote, iclass 11, count 0 2006.183.07:52:30.24#ibcon#about to read 3, iclass 11, count 0 2006.183.07:52:30.26#ibcon#read 3, iclass 11, count 0 2006.183.07:52:30.26#ibcon#about to read 4, iclass 11, count 0 2006.183.07:52:30.26#ibcon#read 4, iclass 11, count 0 2006.183.07:52:30.26#ibcon#about to read 5, iclass 11, count 0 2006.183.07:52:30.26#ibcon#read 5, iclass 11, count 0 2006.183.07:52:30.26#ibcon#about to read 6, iclass 11, count 0 2006.183.07:52:30.26#ibcon#read 6, iclass 11, count 0 2006.183.07:52:30.26#ibcon#end of sib2, iclass 11, count 0 2006.183.07:52:30.26#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:52:30.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:52:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:52:30.26#ibcon#*before write, iclass 11, count 0 2006.183.07:52:30.26#ibcon#enter sib2, iclass 11, count 0 2006.183.07:52:30.26#ibcon#flushed, iclass 11, count 0 2006.183.07:52:30.26#ibcon#about to write, iclass 11, count 0 2006.183.07:52:30.26#ibcon#wrote, iclass 11, count 0 2006.183.07:52:30.26#ibcon#about to read 3, iclass 11, count 0 2006.183.07:52:30.30#ibcon#read 3, iclass 11, count 0 2006.183.07:52:30.30#ibcon#about to read 4, iclass 11, count 0 2006.183.07:52:30.30#ibcon#read 4, iclass 11, count 0 2006.183.07:52:30.30#ibcon#about to read 5, iclass 11, count 0 2006.183.07:52:30.30#ibcon#read 5, iclass 11, count 0 2006.183.07:52:30.30#ibcon#about to read 6, iclass 11, count 0 2006.183.07:52:30.30#ibcon#read 6, iclass 11, count 0 2006.183.07:52:30.30#ibcon#end of sib2, iclass 11, count 0 2006.183.07:52:30.30#ibcon#*after write, iclass 11, count 0 2006.183.07:52:30.30#ibcon#*before return 0, iclass 11, count 0 2006.183.07:52:30.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:52:30.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.07:52:30.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:52:30.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:52:30.30$vc4f8/va=8,7 2006.183.07:52:30.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.07:52:30.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.07:52:30.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:30.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:52:30.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:52:30.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:52:30.36#ibcon#enter wrdev, iclass 13, count 2 2006.183.07:52:30.36#ibcon#first serial, iclass 13, count 2 2006.183.07:52:30.36#ibcon#enter sib2, iclass 13, count 2 2006.183.07:52:30.36#ibcon#flushed, iclass 13, count 2 2006.183.07:52:30.36#ibcon#about to write, iclass 13, count 2 2006.183.07:52:30.36#ibcon#wrote, iclass 13, count 2 2006.183.07:52:30.36#ibcon#about to read 3, iclass 13, count 2 2006.183.07:52:30.38#ibcon#read 3, iclass 13, count 2 2006.183.07:52:30.38#ibcon#about to read 4, iclass 13, count 2 2006.183.07:52:30.38#ibcon#read 4, iclass 13, count 2 2006.183.07:52:30.38#ibcon#about to read 5, iclass 13, count 2 2006.183.07:52:30.38#ibcon#read 5, iclass 13, count 2 2006.183.07:52:30.38#ibcon#about to read 6, iclass 13, count 2 2006.183.07:52:30.38#ibcon#read 6, iclass 13, count 2 2006.183.07:52:30.38#ibcon#end of sib2, iclass 13, count 2 2006.183.07:52:30.38#ibcon#*mode == 0, iclass 13, count 2 2006.183.07:52:30.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.07:52:30.38#ibcon#[25=AT08-07\r\n] 2006.183.07:52:30.38#ibcon#*before write, iclass 13, count 2 2006.183.07:52:30.38#ibcon#enter sib2, iclass 13, count 2 2006.183.07:52:30.38#ibcon#flushed, iclass 13, count 2 2006.183.07:52:30.38#ibcon#about to write, iclass 13, count 2 2006.183.07:52:30.38#ibcon#wrote, iclass 13, count 2 2006.183.07:52:30.38#ibcon#about to read 3, iclass 13, count 2 2006.183.07:52:30.41#ibcon#read 3, iclass 13, count 2 2006.183.07:52:30.41#ibcon#about to read 4, iclass 13, count 2 2006.183.07:52:30.41#ibcon#read 4, iclass 13, count 2 2006.183.07:52:30.41#ibcon#about to read 5, iclass 13, count 2 2006.183.07:52:30.41#ibcon#read 5, iclass 13, count 2 2006.183.07:52:30.41#ibcon#about to read 6, iclass 13, count 2 2006.183.07:52:30.41#ibcon#read 6, iclass 13, count 2 2006.183.07:52:30.41#ibcon#end of sib2, iclass 13, count 2 2006.183.07:52:30.41#ibcon#*after write, iclass 13, count 2 2006.183.07:52:30.41#ibcon#*before return 0, iclass 13, count 2 2006.183.07:52:30.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:52:30.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.07:52:30.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.07:52:30.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:30.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:52:30.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:52:30.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:52:30.53#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:52:30.53#ibcon#first serial, iclass 13, count 0 2006.183.07:52:30.53#ibcon#enter sib2, iclass 13, count 0 2006.183.07:52:30.53#ibcon#flushed, iclass 13, count 0 2006.183.07:52:30.53#ibcon#about to write, iclass 13, count 0 2006.183.07:52:30.53#ibcon#wrote, iclass 13, count 0 2006.183.07:52:30.53#ibcon#about to read 3, iclass 13, count 0 2006.183.07:52:30.55#ibcon#read 3, iclass 13, count 0 2006.183.07:52:30.55#ibcon#about to read 4, iclass 13, count 0 2006.183.07:52:30.55#ibcon#read 4, iclass 13, count 0 2006.183.07:52:30.55#ibcon#about to read 5, iclass 13, count 0 2006.183.07:52:30.55#ibcon#read 5, iclass 13, count 0 2006.183.07:52:30.55#ibcon#about to read 6, iclass 13, count 0 2006.183.07:52:30.55#ibcon#read 6, iclass 13, count 0 2006.183.07:52:30.55#ibcon#end of sib2, iclass 13, count 0 2006.183.07:52:30.55#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:52:30.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:52:30.55#ibcon#[25=USB\r\n] 2006.183.07:52:30.55#ibcon#*before write, iclass 13, count 0 2006.183.07:52:30.55#ibcon#enter sib2, iclass 13, count 0 2006.183.07:52:30.55#ibcon#flushed, iclass 13, count 0 2006.183.07:52:30.55#ibcon#about to write, iclass 13, count 0 2006.183.07:52:30.55#ibcon#wrote, iclass 13, count 0 2006.183.07:52:30.55#ibcon#about to read 3, iclass 13, count 0 2006.183.07:52:30.58#ibcon#read 3, iclass 13, count 0 2006.183.07:52:30.58#ibcon#about to read 4, iclass 13, count 0 2006.183.07:52:30.58#ibcon#read 4, iclass 13, count 0 2006.183.07:52:30.58#ibcon#about to read 5, iclass 13, count 0 2006.183.07:52:30.58#ibcon#read 5, iclass 13, count 0 2006.183.07:52:30.58#ibcon#about to read 6, iclass 13, count 0 2006.183.07:52:30.58#ibcon#read 6, iclass 13, count 0 2006.183.07:52:30.58#ibcon#end of sib2, iclass 13, count 0 2006.183.07:52:30.58#ibcon#*after write, iclass 13, count 0 2006.183.07:52:30.58#ibcon#*before return 0, iclass 13, count 0 2006.183.07:52:30.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:52:30.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.07:52:30.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:52:30.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:52:30.58$vc4f8/vblo=1,632.99 2006.183.07:52:30.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.07:52:30.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.07:52:30.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:30.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:30.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:30.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:30.58#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:52:30.58#ibcon#first serial, iclass 15, count 0 2006.183.07:52:30.58#ibcon#enter sib2, iclass 15, count 0 2006.183.07:52:30.58#ibcon#flushed, iclass 15, count 0 2006.183.07:52:30.58#ibcon#about to write, iclass 15, count 0 2006.183.07:52:30.58#ibcon#wrote, iclass 15, count 0 2006.183.07:52:30.58#ibcon#about to read 3, iclass 15, count 0 2006.183.07:52:30.60#ibcon#read 3, iclass 15, count 0 2006.183.07:52:30.60#ibcon#about to read 4, iclass 15, count 0 2006.183.07:52:30.60#ibcon#read 4, iclass 15, count 0 2006.183.07:52:30.60#ibcon#about to read 5, iclass 15, count 0 2006.183.07:52:30.60#ibcon#read 5, iclass 15, count 0 2006.183.07:52:30.60#ibcon#about to read 6, iclass 15, count 0 2006.183.07:52:30.60#ibcon#read 6, iclass 15, count 0 2006.183.07:52:30.60#ibcon#end of sib2, iclass 15, count 0 2006.183.07:52:30.60#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:52:30.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:52:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:52:30.60#ibcon#*before write, iclass 15, count 0 2006.183.07:52:30.60#ibcon#enter sib2, iclass 15, count 0 2006.183.07:52:30.60#ibcon#flushed, iclass 15, count 0 2006.183.07:52:30.60#ibcon#about to write, iclass 15, count 0 2006.183.07:52:30.60#ibcon#wrote, iclass 15, count 0 2006.183.07:52:30.60#ibcon#about to read 3, iclass 15, count 0 2006.183.07:52:30.64#ibcon#read 3, iclass 15, count 0 2006.183.07:52:30.64#ibcon#about to read 4, iclass 15, count 0 2006.183.07:52:30.64#ibcon#read 4, iclass 15, count 0 2006.183.07:52:30.64#ibcon#about to read 5, iclass 15, count 0 2006.183.07:52:30.64#ibcon#read 5, iclass 15, count 0 2006.183.07:52:30.64#ibcon#about to read 6, iclass 15, count 0 2006.183.07:52:30.64#ibcon#read 6, iclass 15, count 0 2006.183.07:52:30.64#ibcon#end of sib2, iclass 15, count 0 2006.183.07:52:30.64#ibcon#*after write, iclass 15, count 0 2006.183.07:52:30.64#ibcon#*before return 0, iclass 15, count 0 2006.183.07:52:30.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:30.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.07:52:30.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:52:30.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:52:30.64$vc4f8/vb=1,4 2006.183.07:52:30.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.07:52:30.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.07:52:30.64#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:30.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:30.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:30.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:30.64#ibcon#enter wrdev, iclass 17, count 2 2006.183.07:52:30.64#ibcon#first serial, iclass 17, count 2 2006.183.07:52:30.64#ibcon#enter sib2, iclass 17, count 2 2006.183.07:52:30.64#ibcon#flushed, iclass 17, count 2 2006.183.07:52:30.64#ibcon#about to write, iclass 17, count 2 2006.183.07:52:30.64#ibcon#wrote, iclass 17, count 2 2006.183.07:52:30.64#ibcon#about to read 3, iclass 17, count 2 2006.183.07:52:30.66#ibcon#read 3, iclass 17, count 2 2006.183.07:52:30.66#ibcon#about to read 4, iclass 17, count 2 2006.183.07:52:30.66#ibcon#read 4, iclass 17, count 2 2006.183.07:52:30.66#ibcon#about to read 5, iclass 17, count 2 2006.183.07:52:30.66#ibcon#read 5, iclass 17, count 2 2006.183.07:52:30.66#ibcon#about to read 6, iclass 17, count 2 2006.183.07:52:30.66#ibcon#read 6, iclass 17, count 2 2006.183.07:52:30.66#ibcon#end of sib2, iclass 17, count 2 2006.183.07:52:30.66#ibcon#*mode == 0, iclass 17, count 2 2006.183.07:52:30.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.07:52:30.66#ibcon#[27=AT01-04\r\n] 2006.183.07:52:30.66#ibcon#*before write, iclass 17, count 2 2006.183.07:52:30.66#ibcon#enter sib2, iclass 17, count 2 2006.183.07:52:30.66#ibcon#flushed, iclass 17, count 2 2006.183.07:52:30.66#ibcon#about to write, iclass 17, count 2 2006.183.07:52:30.66#ibcon#wrote, iclass 17, count 2 2006.183.07:52:30.66#ibcon#about to read 3, iclass 17, count 2 2006.183.07:52:30.69#ibcon#read 3, iclass 17, count 2 2006.183.07:52:30.69#ibcon#about to read 4, iclass 17, count 2 2006.183.07:52:30.69#ibcon#read 4, iclass 17, count 2 2006.183.07:52:30.69#ibcon#about to read 5, iclass 17, count 2 2006.183.07:52:30.69#ibcon#read 5, iclass 17, count 2 2006.183.07:52:30.69#ibcon#about to read 6, iclass 17, count 2 2006.183.07:52:30.69#ibcon#read 6, iclass 17, count 2 2006.183.07:52:30.69#ibcon#end of sib2, iclass 17, count 2 2006.183.07:52:30.69#ibcon#*after write, iclass 17, count 2 2006.183.07:52:30.69#ibcon#*before return 0, iclass 17, count 2 2006.183.07:52:30.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:30.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.07:52:30.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.07:52:30.69#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:30.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:30.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:30.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:30.81#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:52:30.81#ibcon#first serial, iclass 17, count 0 2006.183.07:52:30.81#ibcon#enter sib2, iclass 17, count 0 2006.183.07:52:30.81#ibcon#flushed, iclass 17, count 0 2006.183.07:52:30.81#ibcon#about to write, iclass 17, count 0 2006.183.07:52:30.81#ibcon#wrote, iclass 17, count 0 2006.183.07:52:30.81#ibcon#about to read 3, iclass 17, count 0 2006.183.07:52:30.83#ibcon#read 3, iclass 17, count 0 2006.183.07:52:30.83#ibcon#about to read 4, iclass 17, count 0 2006.183.07:52:30.83#ibcon#read 4, iclass 17, count 0 2006.183.07:52:30.83#ibcon#about to read 5, iclass 17, count 0 2006.183.07:52:30.83#ibcon#read 5, iclass 17, count 0 2006.183.07:52:30.83#ibcon#about to read 6, iclass 17, count 0 2006.183.07:52:30.83#ibcon#read 6, iclass 17, count 0 2006.183.07:52:30.83#ibcon#end of sib2, iclass 17, count 0 2006.183.07:52:30.83#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:52:30.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:52:30.83#ibcon#[27=USB\r\n] 2006.183.07:52:30.83#ibcon#*before write, iclass 17, count 0 2006.183.07:52:30.83#ibcon#enter sib2, iclass 17, count 0 2006.183.07:52:30.83#ibcon#flushed, iclass 17, count 0 2006.183.07:52:30.83#ibcon#about to write, iclass 17, count 0 2006.183.07:52:30.83#ibcon#wrote, iclass 17, count 0 2006.183.07:52:30.83#ibcon#about to read 3, iclass 17, count 0 2006.183.07:52:30.86#ibcon#read 3, iclass 17, count 0 2006.183.07:52:30.86#ibcon#about to read 4, iclass 17, count 0 2006.183.07:52:30.86#ibcon#read 4, iclass 17, count 0 2006.183.07:52:30.86#ibcon#about to read 5, iclass 17, count 0 2006.183.07:52:30.86#ibcon#read 5, iclass 17, count 0 2006.183.07:52:30.86#ibcon#about to read 6, iclass 17, count 0 2006.183.07:52:30.86#ibcon#read 6, iclass 17, count 0 2006.183.07:52:30.86#ibcon#end of sib2, iclass 17, count 0 2006.183.07:52:30.86#ibcon#*after write, iclass 17, count 0 2006.183.07:52:30.86#ibcon#*before return 0, iclass 17, count 0 2006.183.07:52:30.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:30.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.07:52:30.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:52:30.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:52:30.86$vc4f8/vblo=2,640.99 2006.183.07:52:30.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.07:52:30.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.07:52:30.86#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:30.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:30.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:30.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:30.86#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:52:30.86#ibcon#first serial, iclass 19, count 0 2006.183.07:52:30.86#ibcon#enter sib2, iclass 19, count 0 2006.183.07:52:30.86#ibcon#flushed, iclass 19, count 0 2006.183.07:52:30.86#ibcon#about to write, iclass 19, count 0 2006.183.07:52:30.86#ibcon#wrote, iclass 19, count 0 2006.183.07:52:30.86#ibcon#about to read 3, iclass 19, count 0 2006.183.07:52:30.88#ibcon#read 3, iclass 19, count 0 2006.183.07:52:30.88#ibcon#about to read 4, iclass 19, count 0 2006.183.07:52:30.88#ibcon#read 4, iclass 19, count 0 2006.183.07:52:30.88#ibcon#about to read 5, iclass 19, count 0 2006.183.07:52:30.88#ibcon#read 5, iclass 19, count 0 2006.183.07:52:30.88#ibcon#about to read 6, iclass 19, count 0 2006.183.07:52:30.88#ibcon#read 6, iclass 19, count 0 2006.183.07:52:30.88#ibcon#end of sib2, iclass 19, count 0 2006.183.07:52:30.88#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:52:30.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:52:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:52:30.88#ibcon#*before write, iclass 19, count 0 2006.183.07:52:30.88#ibcon#enter sib2, iclass 19, count 0 2006.183.07:52:30.88#ibcon#flushed, iclass 19, count 0 2006.183.07:52:30.88#ibcon#about to write, iclass 19, count 0 2006.183.07:52:30.88#ibcon#wrote, iclass 19, count 0 2006.183.07:52:30.88#ibcon#about to read 3, iclass 19, count 0 2006.183.07:52:30.92#ibcon#read 3, iclass 19, count 0 2006.183.07:52:30.92#ibcon#about to read 4, iclass 19, count 0 2006.183.07:52:30.92#ibcon#read 4, iclass 19, count 0 2006.183.07:52:30.92#ibcon#about to read 5, iclass 19, count 0 2006.183.07:52:30.92#ibcon#read 5, iclass 19, count 0 2006.183.07:52:30.92#ibcon#about to read 6, iclass 19, count 0 2006.183.07:52:30.92#ibcon#read 6, iclass 19, count 0 2006.183.07:52:30.92#ibcon#end of sib2, iclass 19, count 0 2006.183.07:52:30.92#ibcon#*after write, iclass 19, count 0 2006.183.07:52:30.92#ibcon#*before return 0, iclass 19, count 0 2006.183.07:52:30.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:30.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.07:52:30.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:52:30.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:52:30.92$vc4f8/vb=2,4 2006.183.07:52:30.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.07:52:30.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.07:52:30.92#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:30.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:30.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:30.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:30.98#ibcon#enter wrdev, iclass 21, count 2 2006.183.07:52:30.98#ibcon#first serial, iclass 21, count 2 2006.183.07:52:30.98#ibcon#enter sib2, iclass 21, count 2 2006.183.07:52:30.98#ibcon#flushed, iclass 21, count 2 2006.183.07:52:30.98#ibcon#about to write, iclass 21, count 2 2006.183.07:52:30.98#ibcon#wrote, iclass 21, count 2 2006.183.07:52:30.98#ibcon#about to read 3, iclass 21, count 2 2006.183.07:52:31.00#ibcon#read 3, iclass 21, count 2 2006.183.07:52:31.00#ibcon#about to read 4, iclass 21, count 2 2006.183.07:52:31.00#ibcon#read 4, iclass 21, count 2 2006.183.07:52:31.00#ibcon#about to read 5, iclass 21, count 2 2006.183.07:52:31.00#ibcon#read 5, iclass 21, count 2 2006.183.07:52:31.00#ibcon#about to read 6, iclass 21, count 2 2006.183.07:52:31.00#ibcon#read 6, iclass 21, count 2 2006.183.07:52:31.00#ibcon#end of sib2, iclass 21, count 2 2006.183.07:52:31.00#ibcon#*mode == 0, iclass 21, count 2 2006.183.07:52:31.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.07:52:31.00#ibcon#[27=AT02-04\r\n] 2006.183.07:52:31.00#ibcon#*before write, iclass 21, count 2 2006.183.07:52:31.00#ibcon#enter sib2, iclass 21, count 2 2006.183.07:52:31.00#ibcon#flushed, iclass 21, count 2 2006.183.07:52:31.00#ibcon#about to write, iclass 21, count 2 2006.183.07:52:31.00#ibcon#wrote, iclass 21, count 2 2006.183.07:52:31.00#ibcon#about to read 3, iclass 21, count 2 2006.183.07:52:31.03#ibcon#read 3, iclass 21, count 2 2006.183.07:52:31.03#ibcon#about to read 4, iclass 21, count 2 2006.183.07:52:31.03#ibcon#read 4, iclass 21, count 2 2006.183.07:52:31.03#ibcon#about to read 5, iclass 21, count 2 2006.183.07:52:31.03#ibcon#read 5, iclass 21, count 2 2006.183.07:52:31.03#ibcon#about to read 6, iclass 21, count 2 2006.183.07:52:31.03#ibcon#read 6, iclass 21, count 2 2006.183.07:52:31.03#ibcon#end of sib2, iclass 21, count 2 2006.183.07:52:31.03#ibcon#*after write, iclass 21, count 2 2006.183.07:52:31.03#ibcon#*before return 0, iclass 21, count 2 2006.183.07:52:31.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:31.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.07:52:31.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.07:52:31.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:31.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:31.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:31.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:31.15#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:52:31.15#ibcon#first serial, iclass 21, count 0 2006.183.07:52:31.15#ibcon#enter sib2, iclass 21, count 0 2006.183.07:52:31.15#ibcon#flushed, iclass 21, count 0 2006.183.07:52:31.15#ibcon#about to write, iclass 21, count 0 2006.183.07:52:31.15#ibcon#wrote, iclass 21, count 0 2006.183.07:52:31.15#ibcon#about to read 3, iclass 21, count 0 2006.183.07:52:31.17#ibcon#read 3, iclass 21, count 0 2006.183.07:52:31.17#ibcon#about to read 4, iclass 21, count 0 2006.183.07:52:31.17#ibcon#read 4, iclass 21, count 0 2006.183.07:52:31.17#ibcon#about to read 5, iclass 21, count 0 2006.183.07:52:31.17#ibcon#read 5, iclass 21, count 0 2006.183.07:52:31.17#ibcon#about to read 6, iclass 21, count 0 2006.183.07:52:31.17#ibcon#read 6, iclass 21, count 0 2006.183.07:52:31.17#ibcon#end of sib2, iclass 21, count 0 2006.183.07:52:31.17#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:52:31.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:52:31.17#ibcon#[27=USB\r\n] 2006.183.07:52:31.17#ibcon#*before write, iclass 21, count 0 2006.183.07:52:31.17#ibcon#enter sib2, iclass 21, count 0 2006.183.07:52:31.17#ibcon#flushed, iclass 21, count 0 2006.183.07:52:31.17#ibcon#about to write, iclass 21, count 0 2006.183.07:52:31.17#ibcon#wrote, iclass 21, count 0 2006.183.07:52:31.17#ibcon#about to read 3, iclass 21, count 0 2006.183.07:52:31.20#ibcon#read 3, iclass 21, count 0 2006.183.07:52:31.20#ibcon#about to read 4, iclass 21, count 0 2006.183.07:52:31.20#ibcon#read 4, iclass 21, count 0 2006.183.07:52:31.20#ibcon#about to read 5, iclass 21, count 0 2006.183.07:52:31.20#ibcon#read 5, iclass 21, count 0 2006.183.07:52:31.20#ibcon#about to read 6, iclass 21, count 0 2006.183.07:52:31.20#ibcon#read 6, iclass 21, count 0 2006.183.07:52:31.20#ibcon#end of sib2, iclass 21, count 0 2006.183.07:52:31.20#ibcon#*after write, iclass 21, count 0 2006.183.07:52:31.20#ibcon#*before return 0, iclass 21, count 0 2006.183.07:52:31.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:31.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.07:52:31.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:52:31.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:52:31.20$vc4f8/vblo=3,656.99 2006.183.07:52:31.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.07:52:31.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.07:52:31.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:31.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:31.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:31.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:31.20#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:52:31.20#ibcon#first serial, iclass 23, count 0 2006.183.07:52:31.20#ibcon#enter sib2, iclass 23, count 0 2006.183.07:52:31.20#ibcon#flushed, iclass 23, count 0 2006.183.07:52:31.20#ibcon#about to write, iclass 23, count 0 2006.183.07:52:31.20#ibcon#wrote, iclass 23, count 0 2006.183.07:52:31.20#ibcon#about to read 3, iclass 23, count 0 2006.183.07:52:31.22#ibcon#read 3, iclass 23, count 0 2006.183.07:52:31.22#ibcon#about to read 4, iclass 23, count 0 2006.183.07:52:31.22#ibcon#read 4, iclass 23, count 0 2006.183.07:52:31.22#ibcon#about to read 5, iclass 23, count 0 2006.183.07:52:31.22#ibcon#read 5, iclass 23, count 0 2006.183.07:52:31.22#ibcon#about to read 6, iclass 23, count 0 2006.183.07:52:31.22#ibcon#read 6, iclass 23, count 0 2006.183.07:52:31.22#ibcon#end of sib2, iclass 23, count 0 2006.183.07:52:31.22#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:52:31.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:52:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:52:31.22#ibcon#*before write, iclass 23, count 0 2006.183.07:52:31.22#ibcon#enter sib2, iclass 23, count 0 2006.183.07:52:31.22#ibcon#flushed, iclass 23, count 0 2006.183.07:52:31.22#ibcon#about to write, iclass 23, count 0 2006.183.07:52:31.22#ibcon#wrote, iclass 23, count 0 2006.183.07:52:31.22#ibcon#about to read 3, iclass 23, count 0 2006.183.07:52:31.26#ibcon#read 3, iclass 23, count 0 2006.183.07:52:31.26#ibcon#about to read 4, iclass 23, count 0 2006.183.07:52:31.26#ibcon#read 4, iclass 23, count 0 2006.183.07:52:31.26#ibcon#about to read 5, iclass 23, count 0 2006.183.07:52:31.26#ibcon#read 5, iclass 23, count 0 2006.183.07:52:31.26#ibcon#about to read 6, iclass 23, count 0 2006.183.07:52:31.26#ibcon#read 6, iclass 23, count 0 2006.183.07:52:31.26#ibcon#end of sib2, iclass 23, count 0 2006.183.07:52:31.26#ibcon#*after write, iclass 23, count 0 2006.183.07:52:31.26#ibcon#*before return 0, iclass 23, count 0 2006.183.07:52:31.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:31.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.07:52:31.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:52:31.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:52:31.26$vc4f8/vb=3,4 2006.183.07:52:31.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.07:52:31.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.07:52:31.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:31.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:31.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:31.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:31.32#ibcon#enter wrdev, iclass 25, count 2 2006.183.07:52:31.32#ibcon#first serial, iclass 25, count 2 2006.183.07:52:31.32#ibcon#enter sib2, iclass 25, count 2 2006.183.07:52:31.32#ibcon#flushed, iclass 25, count 2 2006.183.07:52:31.32#ibcon#about to write, iclass 25, count 2 2006.183.07:52:31.32#ibcon#wrote, iclass 25, count 2 2006.183.07:52:31.32#ibcon#about to read 3, iclass 25, count 2 2006.183.07:52:31.34#ibcon#read 3, iclass 25, count 2 2006.183.07:52:31.34#ibcon#about to read 4, iclass 25, count 2 2006.183.07:52:31.34#ibcon#read 4, iclass 25, count 2 2006.183.07:52:31.34#ibcon#about to read 5, iclass 25, count 2 2006.183.07:52:31.34#ibcon#read 5, iclass 25, count 2 2006.183.07:52:31.34#ibcon#about to read 6, iclass 25, count 2 2006.183.07:52:31.34#ibcon#read 6, iclass 25, count 2 2006.183.07:52:31.34#ibcon#end of sib2, iclass 25, count 2 2006.183.07:52:31.34#ibcon#*mode == 0, iclass 25, count 2 2006.183.07:52:31.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.07:52:31.34#ibcon#[27=AT03-04\r\n] 2006.183.07:52:31.34#ibcon#*before write, iclass 25, count 2 2006.183.07:52:31.34#ibcon#enter sib2, iclass 25, count 2 2006.183.07:52:31.34#ibcon#flushed, iclass 25, count 2 2006.183.07:52:31.34#ibcon#about to write, iclass 25, count 2 2006.183.07:52:31.34#ibcon#wrote, iclass 25, count 2 2006.183.07:52:31.34#ibcon#about to read 3, iclass 25, count 2 2006.183.07:52:31.37#ibcon#read 3, iclass 25, count 2 2006.183.07:52:31.37#ibcon#about to read 4, iclass 25, count 2 2006.183.07:52:31.37#ibcon#read 4, iclass 25, count 2 2006.183.07:52:31.37#ibcon#about to read 5, iclass 25, count 2 2006.183.07:52:31.37#ibcon#read 5, iclass 25, count 2 2006.183.07:52:31.37#ibcon#about to read 6, iclass 25, count 2 2006.183.07:52:31.37#ibcon#read 6, iclass 25, count 2 2006.183.07:52:31.37#ibcon#end of sib2, iclass 25, count 2 2006.183.07:52:31.37#ibcon#*after write, iclass 25, count 2 2006.183.07:52:31.37#ibcon#*before return 0, iclass 25, count 2 2006.183.07:52:31.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:31.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.07:52:31.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.07:52:31.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:31.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:31.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:31.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:31.49#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:52:31.49#ibcon#first serial, iclass 25, count 0 2006.183.07:52:31.49#ibcon#enter sib2, iclass 25, count 0 2006.183.07:52:31.49#ibcon#flushed, iclass 25, count 0 2006.183.07:52:31.49#ibcon#about to write, iclass 25, count 0 2006.183.07:52:31.49#ibcon#wrote, iclass 25, count 0 2006.183.07:52:31.49#ibcon#about to read 3, iclass 25, count 0 2006.183.07:52:31.51#ibcon#read 3, iclass 25, count 0 2006.183.07:52:31.51#ibcon#about to read 4, iclass 25, count 0 2006.183.07:52:31.51#ibcon#read 4, iclass 25, count 0 2006.183.07:52:31.51#ibcon#about to read 5, iclass 25, count 0 2006.183.07:52:31.51#ibcon#read 5, iclass 25, count 0 2006.183.07:52:31.51#ibcon#about to read 6, iclass 25, count 0 2006.183.07:52:31.51#ibcon#read 6, iclass 25, count 0 2006.183.07:52:31.51#ibcon#end of sib2, iclass 25, count 0 2006.183.07:52:31.51#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:52:31.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:52:31.51#ibcon#[27=USB\r\n] 2006.183.07:52:31.51#ibcon#*before write, iclass 25, count 0 2006.183.07:52:31.51#ibcon#enter sib2, iclass 25, count 0 2006.183.07:52:31.51#ibcon#flushed, iclass 25, count 0 2006.183.07:52:31.51#ibcon#about to write, iclass 25, count 0 2006.183.07:52:31.51#ibcon#wrote, iclass 25, count 0 2006.183.07:52:31.51#ibcon#about to read 3, iclass 25, count 0 2006.183.07:52:31.54#ibcon#read 3, iclass 25, count 0 2006.183.07:52:31.54#ibcon#about to read 4, iclass 25, count 0 2006.183.07:52:31.54#ibcon#read 4, iclass 25, count 0 2006.183.07:52:31.54#ibcon#about to read 5, iclass 25, count 0 2006.183.07:52:31.54#ibcon#read 5, iclass 25, count 0 2006.183.07:52:31.54#ibcon#about to read 6, iclass 25, count 0 2006.183.07:52:31.54#ibcon#read 6, iclass 25, count 0 2006.183.07:52:31.54#ibcon#end of sib2, iclass 25, count 0 2006.183.07:52:31.54#ibcon#*after write, iclass 25, count 0 2006.183.07:52:31.54#ibcon#*before return 0, iclass 25, count 0 2006.183.07:52:31.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:31.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.07:52:31.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:52:31.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:52:31.54$vc4f8/vblo=4,712.99 2006.183.07:52:31.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.07:52:31.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.07:52:31.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:31.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:31.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:31.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:31.54#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:52:31.54#ibcon#first serial, iclass 27, count 0 2006.183.07:52:31.54#ibcon#enter sib2, iclass 27, count 0 2006.183.07:52:31.54#ibcon#flushed, iclass 27, count 0 2006.183.07:52:31.54#ibcon#about to write, iclass 27, count 0 2006.183.07:52:31.54#ibcon#wrote, iclass 27, count 0 2006.183.07:52:31.54#ibcon#about to read 3, iclass 27, count 0 2006.183.07:52:31.56#ibcon#read 3, iclass 27, count 0 2006.183.07:52:31.56#ibcon#about to read 4, iclass 27, count 0 2006.183.07:52:31.56#ibcon#read 4, iclass 27, count 0 2006.183.07:52:31.56#ibcon#about to read 5, iclass 27, count 0 2006.183.07:52:31.56#ibcon#read 5, iclass 27, count 0 2006.183.07:52:31.56#ibcon#about to read 6, iclass 27, count 0 2006.183.07:52:31.56#ibcon#read 6, iclass 27, count 0 2006.183.07:52:31.56#ibcon#end of sib2, iclass 27, count 0 2006.183.07:52:31.56#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:52:31.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:52:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:52:31.56#ibcon#*before write, iclass 27, count 0 2006.183.07:52:31.56#ibcon#enter sib2, iclass 27, count 0 2006.183.07:52:31.56#ibcon#flushed, iclass 27, count 0 2006.183.07:52:31.56#ibcon#about to write, iclass 27, count 0 2006.183.07:52:31.56#ibcon#wrote, iclass 27, count 0 2006.183.07:52:31.56#ibcon#about to read 3, iclass 27, count 0 2006.183.07:52:31.60#ibcon#read 3, iclass 27, count 0 2006.183.07:52:31.60#ibcon#about to read 4, iclass 27, count 0 2006.183.07:52:31.60#ibcon#read 4, iclass 27, count 0 2006.183.07:52:31.60#ibcon#about to read 5, iclass 27, count 0 2006.183.07:52:31.60#ibcon#read 5, iclass 27, count 0 2006.183.07:52:31.60#ibcon#about to read 6, iclass 27, count 0 2006.183.07:52:31.60#ibcon#read 6, iclass 27, count 0 2006.183.07:52:31.60#ibcon#end of sib2, iclass 27, count 0 2006.183.07:52:31.60#ibcon#*after write, iclass 27, count 0 2006.183.07:52:31.60#ibcon#*before return 0, iclass 27, count 0 2006.183.07:52:31.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:31.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:52:31.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:52:31.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:52:31.60$vc4f8/vb=4,4 2006.183.07:52:31.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.07:52:31.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.07:52:31.60#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:31.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:31.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:31.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:31.66#ibcon#enter wrdev, iclass 29, count 2 2006.183.07:52:31.66#ibcon#first serial, iclass 29, count 2 2006.183.07:52:31.66#ibcon#enter sib2, iclass 29, count 2 2006.183.07:52:31.66#ibcon#flushed, iclass 29, count 2 2006.183.07:52:31.66#ibcon#about to write, iclass 29, count 2 2006.183.07:52:31.66#ibcon#wrote, iclass 29, count 2 2006.183.07:52:31.66#ibcon#about to read 3, iclass 29, count 2 2006.183.07:52:31.68#ibcon#read 3, iclass 29, count 2 2006.183.07:52:31.68#ibcon#about to read 4, iclass 29, count 2 2006.183.07:52:31.68#ibcon#read 4, iclass 29, count 2 2006.183.07:52:31.68#ibcon#about to read 5, iclass 29, count 2 2006.183.07:52:31.68#ibcon#read 5, iclass 29, count 2 2006.183.07:52:31.68#ibcon#about to read 6, iclass 29, count 2 2006.183.07:52:31.68#ibcon#read 6, iclass 29, count 2 2006.183.07:52:31.68#ibcon#end of sib2, iclass 29, count 2 2006.183.07:52:31.68#ibcon#*mode == 0, iclass 29, count 2 2006.183.07:52:31.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.07:52:31.68#ibcon#[27=AT04-04\r\n] 2006.183.07:52:31.68#ibcon#*before write, iclass 29, count 2 2006.183.07:52:31.68#ibcon#enter sib2, iclass 29, count 2 2006.183.07:52:31.68#ibcon#flushed, iclass 29, count 2 2006.183.07:52:31.68#ibcon#about to write, iclass 29, count 2 2006.183.07:52:31.68#ibcon#wrote, iclass 29, count 2 2006.183.07:52:31.68#ibcon#about to read 3, iclass 29, count 2 2006.183.07:52:31.71#ibcon#read 3, iclass 29, count 2 2006.183.07:52:31.71#ibcon#about to read 4, iclass 29, count 2 2006.183.07:52:31.71#ibcon#read 4, iclass 29, count 2 2006.183.07:52:31.71#ibcon#about to read 5, iclass 29, count 2 2006.183.07:52:31.71#ibcon#read 5, iclass 29, count 2 2006.183.07:52:31.71#ibcon#about to read 6, iclass 29, count 2 2006.183.07:52:31.71#ibcon#read 6, iclass 29, count 2 2006.183.07:52:31.71#ibcon#end of sib2, iclass 29, count 2 2006.183.07:52:31.71#ibcon#*after write, iclass 29, count 2 2006.183.07:52:31.71#ibcon#*before return 0, iclass 29, count 2 2006.183.07:52:31.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:31.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.07:52:31.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.07:52:31.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:31.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:31.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:31.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:31.83#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:52:31.83#ibcon#first serial, iclass 29, count 0 2006.183.07:52:31.83#ibcon#enter sib2, iclass 29, count 0 2006.183.07:52:31.83#ibcon#flushed, iclass 29, count 0 2006.183.07:52:31.83#ibcon#about to write, iclass 29, count 0 2006.183.07:52:31.83#ibcon#wrote, iclass 29, count 0 2006.183.07:52:31.83#ibcon#about to read 3, iclass 29, count 0 2006.183.07:52:31.85#ibcon#read 3, iclass 29, count 0 2006.183.07:52:31.85#ibcon#about to read 4, iclass 29, count 0 2006.183.07:52:31.85#ibcon#read 4, iclass 29, count 0 2006.183.07:52:31.85#ibcon#about to read 5, iclass 29, count 0 2006.183.07:52:31.85#ibcon#read 5, iclass 29, count 0 2006.183.07:52:31.85#ibcon#about to read 6, iclass 29, count 0 2006.183.07:52:31.85#ibcon#read 6, iclass 29, count 0 2006.183.07:52:31.85#ibcon#end of sib2, iclass 29, count 0 2006.183.07:52:31.85#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:52:31.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:52:31.85#ibcon#[27=USB\r\n] 2006.183.07:52:31.85#ibcon#*before write, iclass 29, count 0 2006.183.07:52:31.85#ibcon#enter sib2, iclass 29, count 0 2006.183.07:52:31.85#ibcon#flushed, iclass 29, count 0 2006.183.07:52:31.85#ibcon#about to write, iclass 29, count 0 2006.183.07:52:31.85#ibcon#wrote, iclass 29, count 0 2006.183.07:52:31.85#ibcon#about to read 3, iclass 29, count 0 2006.183.07:52:31.88#ibcon#read 3, iclass 29, count 0 2006.183.07:52:31.88#ibcon#about to read 4, iclass 29, count 0 2006.183.07:52:31.88#ibcon#read 4, iclass 29, count 0 2006.183.07:52:31.88#ibcon#about to read 5, iclass 29, count 0 2006.183.07:52:31.88#ibcon#read 5, iclass 29, count 0 2006.183.07:52:31.88#ibcon#about to read 6, iclass 29, count 0 2006.183.07:52:31.88#ibcon#read 6, iclass 29, count 0 2006.183.07:52:31.88#ibcon#end of sib2, iclass 29, count 0 2006.183.07:52:31.88#ibcon#*after write, iclass 29, count 0 2006.183.07:52:31.88#ibcon#*before return 0, iclass 29, count 0 2006.183.07:52:31.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:31.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.07:52:31.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:52:31.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:52:31.88$vc4f8/vblo=5,744.99 2006.183.07:52:31.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.07:52:31.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.07:52:31.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:31.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:31.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:31.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:31.88#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:52:31.88#ibcon#first serial, iclass 31, count 0 2006.183.07:52:31.88#ibcon#enter sib2, iclass 31, count 0 2006.183.07:52:31.88#ibcon#flushed, iclass 31, count 0 2006.183.07:52:31.88#ibcon#about to write, iclass 31, count 0 2006.183.07:52:31.88#ibcon#wrote, iclass 31, count 0 2006.183.07:52:31.88#ibcon#about to read 3, iclass 31, count 0 2006.183.07:52:31.90#ibcon#read 3, iclass 31, count 0 2006.183.07:52:31.90#ibcon#about to read 4, iclass 31, count 0 2006.183.07:52:31.90#ibcon#read 4, iclass 31, count 0 2006.183.07:52:31.90#ibcon#about to read 5, iclass 31, count 0 2006.183.07:52:31.90#ibcon#read 5, iclass 31, count 0 2006.183.07:52:31.90#ibcon#about to read 6, iclass 31, count 0 2006.183.07:52:31.90#ibcon#read 6, iclass 31, count 0 2006.183.07:52:31.90#ibcon#end of sib2, iclass 31, count 0 2006.183.07:52:31.90#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:52:31.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:52:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:52:31.90#ibcon#*before write, iclass 31, count 0 2006.183.07:52:31.90#ibcon#enter sib2, iclass 31, count 0 2006.183.07:52:31.90#ibcon#flushed, iclass 31, count 0 2006.183.07:52:31.90#ibcon#about to write, iclass 31, count 0 2006.183.07:52:31.90#ibcon#wrote, iclass 31, count 0 2006.183.07:52:31.90#ibcon#about to read 3, iclass 31, count 0 2006.183.07:52:31.94#ibcon#read 3, iclass 31, count 0 2006.183.07:52:31.94#ibcon#about to read 4, iclass 31, count 0 2006.183.07:52:31.94#ibcon#read 4, iclass 31, count 0 2006.183.07:52:31.94#ibcon#about to read 5, iclass 31, count 0 2006.183.07:52:31.94#ibcon#read 5, iclass 31, count 0 2006.183.07:52:31.94#ibcon#about to read 6, iclass 31, count 0 2006.183.07:52:31.94#ibcon#read 6, iclass 31, count 0 2006.183.07:52:31.94#ibcon#end of sib2, iclass 31, count 0 2006.183.07:52:31.94#ibcon#*after write, iclass 31, count 0 2006.183.07:52:31.94#ibcon#*before return 0, iclass 31, count 0 2006.183.07:52:31.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:31.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.07:52:31.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:52:31.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:52:31.94$vc4f8/vb=5,4 2006.183.07:52:31.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.07:52:31.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.07:52:31.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:31.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:32.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:32.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:32.01#ibcon#enter wrdev, iclass 33, count 2 2006.183.07:52:32.01#ibcon#first serial, iclass 33, count 2 2006.183.07:52:32.01#ibcon#enter sib2, iclass 33, count 2 2006.183.07:52:32.01#ibcon#flushed, iclass 33, count 2 2006.183.07:52:32.01#ibcon#about to write, iclass 33, count 2 2006.183.07:52:32.01#ibcon#wrote, iclass 33, count 2 2006.183.07:52:32.01#ibcon#about to read 3, iclass 33, count 2 2006.183.07:52:32.02#ibcon#read 3, iclass 33, count 2 2006.183.07:52:32.02#ibcon#about to read 4, iclass 33, count 2 2006.183.07:52:32.02#ibcon#read 4, iclass 33, count 2 2006.183.07:52:32.02#ibcon#about to read 5, iclass 33, count 2 2006.183.07:52:32.02#ibcon#read 5, iclass 33, count 2 2006.183.07:52:32.02#ibcon#about to read 6, iclass 33, count 2 2006.183.07:52:32.02#ibcon#read 6, iclass 33, count 2 2006.183.07:52:32.02#ibcon#end of sib2, iclass 33, count 2 2006.183.07:52:32.02#ibcon#*mode == 0, iclass 33, count 2 2006.183.07:52:32.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.07:52:32.02#ibcon#[27=AT05-04\r\n] 2006.183.07:52:32.02#ibcon#*before write, iclass 33, count 2 2006.183.07:52:32.02#ibcon#enter sib2, iclass 33, count 2 2006.183.07:52:32.02#ibcon#flushed, iclass 33, count 2 2006.183.07:52:32.02#ibcon#about to write, iclass 33, count 2 2006.183.07:52:32.02#ibcon#wrote, iclass 33, count 2 2006.183.07:52:32.02#ibcon#about to read 3, iclass 33, count 2 2006.183.07:52:32.05#ibcon#read 3, iclass 33, count 2 2006.183.07:52:32.05#ibcon#about to read 4, iclass 33, count 2 2006.183.07:52:32.05#ibcon#read 4, iclass 33, count 2 2006.183.07:52:32.05#ibcon#about to read 5, iclass 33, count 2 2006.183.07:52:32.05#ibcon#read 5, iclass 33, count 2 2006.183.07:52:32.05#ibcon#about to read 6, iclass 33, count 2 2006.183.07:52:32.05#ibcon#read 6, iclass 33, count 2 2006.183.07:52:32.05#ibcon#end of sib2, iclass 33, count 2 2006.183.07:52:32.05#ibcon#*after write, iclass 33, count 2 2006.183.07:52:32.05#ibcon#*before return 0, iclass 33, count 2 2006.183.07:52:32.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:32.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.07:52:32.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.07:52:32.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:32.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:32.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:32.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:32.17#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:52:32.17#ibcon#first serial, iclass 33, count 0 2006.183.07:52:32.17#ibcon#enter sib2, iclass 33, count 0 2006.183.07:52:32.17#ibcon#flushed, iclass 33, count 0 2006.183.07:52:32.17#ibcon#about to write, iclass 33, count 0 2006.183.07:52:32.17#ibcon#wrote, iclass 33, count 0 2006.183.07:52:32.17#ibcon#about to read 3, iclass 33, count 0 2006.183.07:52:32.19#ibcon#read 3, iclass 33, count 0 2006.183.07:52:32.19#ibcon#about to read 4, iclass 33, count 0 2006.183.07:52:32.19#ibcon#read 4, iclass 33, count 0 2006.183.07:52:32.19#ibcon#about to read 5, iclass 33, count 0 2006.183.07:52:32.19#ibcon#read 5, iclass 33, count 0 2006.183.07:52:32.19#ibcon#about to read 6, iclass 33, count 0 2006.183.07:52:32.19#ibcon#read 6, iclass 33, count 0 2006.183.07:52:32.19#ibcon#end of sib2, iclass 33, count 0 2006.183.07:52:32.19#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:52:32.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:52:32.19#ibcon#[27=USB\r\n] 2006.183.07:52:32.19#ibcon#*before write, iclass 33, count 0 2006.183.07:52:32.19#ibcon#enter sib2, iclass 33, count 0 2006.183.07:52:32.19#ibcon#flushed, iclass 33, count 0 2006.183.07:52:32.19#ibcon#about to write, iclass 33, count 0 2006.183.07:52:32.19#ibcon#wrote, iclass 33, count 0 2006.183.07:52:32.19#ibcon#about to read 3, iclass 33, count 0 2006.183.07:52:32.22#ibcon#read 3, iclass 33, count 0 2006.183.07:52:32.22#ibcon#about to read 4, iclass 33, count 0 2006.183.07:52:32.22#ibcon#read 4, iclass 33, count 0 2006.183.07:52:32.22#ibcon#about to read 5, iclass 33, count 0 2006.183.07:52:32.22#ibcon#read 5, iclass 33, count 0 2006.183.07:52:32.22#ibcon#about to read 6, iclass 33, count 0 2006.183.07:52:32.22#ibcon#read 6, iclass 33, count 0 2006.183.07:52:32.22#ibcon#end of sib2, iclass 33, count 0 2006.183.07:52:32.22#ibcon#*after write, iclass 33, count 0 2006.183.07:52:32.22#ibcon#*before return 0, iclass 33, count 0 2006.183.07:52:32.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:32.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.07:52:32.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:52:32.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:52:32.22$vc4f8/vblo=6,752.99 2006.183.07:52:32.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.07:52:32.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.07:52:32.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:52:32.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:32.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:32.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:32.22#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:52:32.22#ibcon#first serial, iclass 35, count 0 2006.183.07:52:32.22#ibcon#enter sib2, iclass 35, count 0 2006.183.07:52:32.22#ibcon#flushed, iclass 35, count 0 2006.183.07:52:32.22#ibcon#about to write, iclass 35, count 0 2006.183.07:52:32.22#ibcon#wrote, iclass 35, count 0 2006.183.07:52:32.22#ibcon#about to read 3, iclass 35, count 0 2006.183.07:52:32.24#ibcon#read 3, iclass 35, count 0 2006.183.07:52:32.24#ibcon#about to read 4, iclass 35, count 0 2006.183.07:52:32.24#ibcon#read 4, iclass 35, count 0 2006.183.07:52:32.24#ibcon#about to read 5, iclass 35, count 0 2006.183.07:52:32.24#ibcon#read 5, iclass 35, count 0 2006.183.07:52:32.24#ibcon#about to read 6, iclass 35, count 0 2006.183.07:52:32.24#ibcon#read 6, iclass 35, count 0 2006.183.07:52:32.24#ibcon#end of sib2, iclass 35, count 0 2006.183.07:52:32.24#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:52:32.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:52:32.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:52:32.24#ibcon#*before write, iclass 35, count 0 2006.183.07:52:32.24#ibcon#enter sib2, iclass 35, count 0 2006.183.07:52:32.24#ibcon#flushed, iclass 35, count 0 2006.183.07:52:32.24#ibcon#about to write, iclass 35, count 0 2006.183.07:52:32.24#ibcon#wrote, iclass 35, count 0 2006.183.07:52:32.24#ibcon#about to read 3, iclass 35, count 0 2006.183.07:52:32.28#ibcon#read 3, iclass 35, count 0 2006.183.07:52:32.28#ibcon#about to read 4, iclass 35, count 0 2006.183.07:52:32.28#ibcon#read 4, iclass 35, count 0 2006.183.07:52:32.28#ibcon#about to read 5, iclass 35, count 0 2006.183.07:52:32.28#ibcon#read 5, iclass 35, count 0 2006.183.07:52:32.28#ibcon#about to read 6, iclass 35, count 0 2006.183.07:52:32.28#ibcon#read 6, iclass 35, count 0 2006.183.07:52:32.28#ibcon#end of sib2, iclass 35, count 0 2006.183.07:52:32.28#ibcon#*after write, iclass 35, count 0 2006.183.07:52:32.28#ibcon#*before return 0, iclass 35, count 0 2006.183.07:52:32.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:32.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.07:52:32.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:52:32.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:52:32.28$vc4f8/vb=6,4 2006.183.07:52:32.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.07:52:32.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.07:52:32.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:52:32.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:32.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:32.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:32.34#ibcon#enter wrdev, iclass 37, count 2 2006.183.07:52:32.34#ibcon#first serial, iclass 37, count 2 2006.183.07:52:32.34#ibcon#enter sib2, iclass 37, count 2 2006.183.07:52:32.34#ibcon#flushed, iclass 37, count 2 2006.183.07:52:32.34#ibcon#about to write, iclass 37, count 2 2006.183.07:52:32.34#ibcon#wrote, iclass 37, count 2 2006.183.07:52:32.34#ibcon#about to read 3, iclass 37, count 2 2006.183.07:52:32.36#ibcon#read 3, iclass 37, count 2 2006.183.07:52:32.36#ibcon#about to read 4, iclass 37, count 2 2006.183.07:52:32.36#ibcon#read 4, iclass 37, count 2 2006.183.07:52:32.36#ibcon#about to read 5, iclass 37, count 2 2006.183.07:52:32.36#ibcon#read 5, iclass 37, count 2 2006.183.07:52:32.36#ibcon#about to read 6, iclass 37, count 2 2006.183.07:52:32.36#ibcon#read 6, iclass 37, count 2 2006.183.07:52:32.36#ibcon#end of sib2, iclass 37, count 2 2006.183.07:52:32.36#ibcon#*mode == 0, iclass 37, count 2 2006.183.07:52:32.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.07:52:32.36#ibcon#[27=AT06-04\r\n] 2006.183.07:52:32.36#ibcon#*before write, iclass 37, count 2 2006.183.07:52:32.36#ibcon#enter sib2, iclass 37, count 2 2006.183.07:52:32.36#ibcon#flushed, iclass 37, count 2 2006.183.07:52:32.36#ibcon#about to write, iclass 37, count 2 2006.183.07:52:32.36#ibcon#wrote, iclass 37, count 2 2006.183.07:52:32.36#ibcon#about to read 3, iclass 37, count 2 2006.183.07:52:32.39#ibcon#read 3, iclass 37, count 2 2006.183.07:52:32.39#ibcon#about to read 4, iclass 37, count 2 2006.183.07:52:32.39#ibcon#read 4, iclass 37, count 2 2006.183.07:52:32.39#ibcon#about to read 5, iclass 37, count 2 2006.183.07:52:32.39#ibcon#read 5, iclass 37, count 2 2006.183.07:52:32.39#ibcon#about to read 6, iclass 37, count 2 2006.183.07:52:32.39#ibcon#read 6, iclass 37, count 2 2006.183.07:52:32.39#ibcon#end of sib2, iclass 37, count 2 2006.183.07:52:32.39#ibcon#*after write, iclass 37, count 2 2006.183.07:52:32.39#ibcon#*before return 0, iclass 37, count 2 2006.183.07:52:32.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:32.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.07:52:32.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.07:52:32.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:52:32.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:32.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:32.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:32.51#ibcon#enter wrdev, iclass 37, count 0 2006.183.07:52:32.51#ibcon#first serial, iclass 37, count 0 2006.183.07:52:32.51#ibcon#enter sib2, iclass 37, count 0 2006.183.07:52:32.51#ibcon#flushed, iclass 37, count 0 2006.183.07:52:32.51#ibcon#about to write, iclass 37, count 0 2006.183.07:52:32.51#ibcon#wrote, iclass 37, count 0 2006.183.07:52:32.51#ibcon#about to read 3, iclass 37, count 0 2006.183.07:52:32.53#ibcon#read 3, iclass 37, count 0 2006.183.07:52:32.53#ibcon#about to read 4, iclass 37, count 0 2006.183.07:52:32.53#ibcon#read 4, iclass 37, count 0 2006.183.07:52:32.53#ibcon#about to read 5, iclass 37, count 0 2006.183.07:52:32.53#ibcon#read 5, iclass 37, count 0 2006.183.07:52:32.53#ibcon#about to read 6, iclass 37, count 0 2006.183.07:52:32.53#ibcon#read 6, iclass 37, count 0 2006.183.07:52:32.53#ibcon#end of sib2, iclass 37, count 0 2006.183.07:52:32.53#ibcon#*mode == 0, iclass 37, count 0 2006.183.07:52:32.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.07:52:32.53#ibcon#[27=USB\r\n] 2006.183.07:52:32.53#ibcon#*before write, iclass 37, count 0 2006.183.07:52:32.53#ibcon#enter sib2, iclass 37, count 0 2006.183.07:52:32.53#ibcon#flushed, iclass 37, count 0 2006.183.07:52:32.53#ibcon#about to write, iclass 37, count 0 2006.183.07:52:32.53#ibcon#wrote, iclass 37, count 0 2006.183.07:52:32.53#ibcon#about to read 3, iclass 37, count 0 2006.183.07:52:32.56#ibcon#read 3, iclass 37, count 0 2006.183.07:52:32.56#ibcon#about to read 4, iclass 37, count 0 2006.183.07:52:32.56#ibcon#read 4, iclass 37, count 0 2006.183.07:52:32.56#ibcon#about to read 5, iclass 37, count 0 2006.183.07:52:32.56#ibcon#read 5, iclass 37, count 0 2006.183.07:52:32.56#ibcon#about to read 6, iclass 37, count 0 2006.183.07:52:32.56#ibcon#read 6, iclass 37, count 0 2006.183.07:52:32.56#ibcon#end of sib2, iclass 37, count 0 2006.183.07:52:32.56#ibcon#*after write, iclass 37, count 0 2006.183.07:52:32.56#ibcon#*before return 0, iclass 37, count 0 2006.183.07:52:32.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:32.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.07:52:32.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.07:52:32.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.07:52:32.56$vc4f8/vabw=wide 2006.183.07:52:32.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.07:52:32.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.07:52:32.56#ibcon#ireg 8 cls_cnt 0 2006.183.07:52:32.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:52:32.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:52:32.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:52:32.56#ibcon#enter wrdev, iclass 39, count 0 2006.183.07:52:32.56#ibcon#first serial, iclass 39, count 0 2006.183.07:52:32.56#ibcon#enter sib2, iclass 39, count 0 2006.183.07:52:32.56#ibcon#flushed, iclass 39, count 0 2006.183.07:52:32.56#ibcon#about to write, iclass 39, count 0 2006.183.07:52:32.56#ibcon#wrote, iclass 39, count 0 2006.183.07:52:32.56#ibcon#about to read 3, iclass 39, count 0 2006.183.07:52:32.58#ibcon#read 3, iclass 39, count 0 2006.183.07:52:32.58#ibcon#about to read 4, iclass 39, count 0 2006.183.07:52:32.58#ibcon#read 4, iclass 39, count 0 2006.183.07:52:32.58#ibcon#about to read 5, iclass 39, count 0 2006.183.07:52:32.58#ibcon#read 5, iclass 39, count 0 2006.183.07:52:32.58#ibcon#about to read 6, iclass 39, count 0 2006.183.07:52:32.58#ibcon#read 6, iclass 39, count 0 2006.183.07:52:32.58#ibcon#end of sib2, iclass 39, count 0 2006.183.07:52:32.58#ibcon#*mode == 0, iclass 39, count 0 2006.183.07:52:32.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.07:52:32.58#ibcon#[25=BW32\r\n] 2006.183.07:52:32.58#ibcon#*before write, iclass 39, count 0 2006.183.07:52:32.58#ibcon#enter sib2, iclass 39, count 0 2006.183.07:52:32.58#ibcon#flushed, iclass 39, count 0 2006.183.07:52:32.58#ibcon#about to write, iclass 39, count 0 2006.183.07:52:32.58#ibcon#wrote, iclass 39, count 0 2006.183.07:52:32.58#ibcon#about to read 3, iclass 39, count 0 2006.183.07:52:32.61#ibcon#read 3, iclass 39, count 0 2006.183.07:52:32.61#ibcon#about to read 4, iclass 39, count 0 2006.183.07:52:32.61#ibcon#read 4, iclass 39, count 0 2006.183.07:52:32.61#ibcon#about to read 5, iclass 39, count 0 2006.183.07:52:32.61#ibcon#read 5, iclass 39, count 0 2006.183.07:52:32.61#ibcon#about to read 6, iclass 39, count 0 2006.183.07:52:32.61#ibcon#read 6, iclass 39, count 0 2006.183.07:52:32.61#ibcon#end of sib2, iclass 39, count 0 2006.183.07:52:32.61#ibcon#*after write, iclass 39, count 0 2006.183.07:52:32.61#ibcon#*before return 0, iclass 39, count 0 2006.183.07:52:32.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:52:32.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.07:52:32.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.07:52:32.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.07:52:32.61$vc4f8/vbbw=wide 2006.183.07:52:32.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.07:52:32.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.07:52:32.61#ibcon#ireg 8 cls_cnt 0 2006.183.07:52:32.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:52:32.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:52:32.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:52:32.68#ibcon#enter wrdev, iclass 3, count 0 2006.183.07:52:32.68#ibcon#first serial, iclass 3, count 0 2006.183.07:52:32.68#ibcon#enter sib2, iclass 3, count 0 2006.183.07:52:32.68#ibcon#flushed, iclass 3, count 0 2006.183.07:52:32.68#ibcon#about to write, iclass 3, count 0 2006.183.07:52:32.68#ibcon#wrote, iclass 3, count 0 2006.183.07:52:32.68#ibcon#about to read 3, iclass 3, count 0 2006.183.07:52:32.70#ibcon#read 3, iclass 3, count 0 2006.183.07:52:32.70#ibcon#about to read 4, iclass 3, count 0 2006.183.07:52:32.70#ibcon#read 4, iclass 3, count 0 2006.183.07:52:32.70#ibcon#about to read 5, iclass 3, count 0 2006.183.07:52:32.70#ibcon#read 5, iclass 3, count 0 2006.183.07:52:32.70#ibcon#about to read 6, iclass 3, count 0 2006.183.07:52:32.70#ibcon#read 6, iclass 3, count 0 2006.183.07:52:32.70#ibcon#end of sib2, iclass 3, count 0 2006.183.07:52:32.70#ibcon#*mode == 0, iclass 3, count 0 2006.183.07:52:32.70#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.07:52:32.70#ibcon#[27=BW32\r\n] 2006.183.07:52:32.70#ibcon#*before write, iclass 3, count 0 2006.183.07:52:32.70#ibcon#enter sib2, iclass 3, count 0 2006.183.07:52:32.70#ibcon#flushed, iclass 3, count 0 2006.183.07:52:32.70#ibcon#about to write, iclass 3, count 0 2006.183.07:52:32.70#ibcon#wrote, iclass 3, count 0 2006.183.07:52:32.70#ibcon#about to read 3, iclass 3, count 0 2006.183.07:52:32.73#ibcon#read 3, iclass 3, count 0 2006.183.07:52:32.73#ibcon#about to read 4, iclass 3, count 0 2006.183.07:52:32.73#ibcon#read 4, iclass 3, count 0 2006.183.07:52:32.73#ibcon#about to read 5, iclass 3, count 0 2006.183.07:52:32.73#ibcon#read 5, iclass 3, count 0 2006.183.07:52:32.73#ibcon#about to read 6, iclass 3, count 0 2006.183.07:52:32.73#ibcon#read 6, iclass 3, count 0 2006.183.07:52:32.73#ibcon#end of sib2, iclass 3, count 0 2006.183.07:52:32.73#ibcon#*after write, iclass 3, count 0 2006.183.07:52:32.73#ibcon#*before return 0, iclass 3, count 0 2006.183.07:52:32.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:52:32.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:52:32.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.07:52:32.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.07:52:32.73$4f8m12a/ifd4f 2006.183.07:52:32.73$ifd4f/lo= 2006.183.07:52:32.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:52:32.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:52:32.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:52:32.73$ifd4f/patch= 2006.183.07:52:32.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:52:32.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:52:32.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:52:32.73$4f8m12a/"form=m,16.000,1:2 2006.183.07:52:32.73$4f8m12a/"tpicd 2006.183.07:52:32.73$4f8m12a/echo=off 2006.183.07:52:32.73$4f8m12a/xlog=off 2006.183.07:52:32.73:!2006.183.07:54:10 2006.183.07:52:44.14#trakl#Source acquired 2006.183.07:52:45.14#flagr#flagr/antenna,acquired 2006.183.07:54:10.00:preob 2006.183.07:54:10.14/onsource/TRACKING 2006.183.07:54:10.14:!2006.183.07:54:20 2006.183.07:54:20.00:data_valid=on 2006.183.07:54:20.00:midob 2006.183.07:54:21.14/onsource/TRACKING 2006.183.07:54:21.14/wx/27.99,996.4,87 2006.183.07:54:21.25/cable/+6.4514E-03 2006.183.07:54:22.34/va/01,08,usb,yes,29,31 2006.183.07:54:22.34/va/02,07,usb,yes,29,31 2006.183.07:54:22.34/va/03,06,usb,yes,31,31 2006.183.07:54:22.34/va/04,07,usb,yes,30,32 2006.183.07:54:22.34/va/05,07,usb,yes,32,34 2006.183.07:54:22.34/va/06,06,usb,yes,31,31 2006.183.07:54:22.34/va/07,06,usb,yes,32,31 2006.183.07:54:22.34/va/08,07,usb,yes,30,29 2006.183.07:54:22.57/valo/01,532.99,yes,locked 2006.183.07:54:22.57/valo/02,572.99,yes,locked 2006.183.07:54:22.57/valo/03,672.99,yes,locked 2006.183.07:54:22.57/valo/04,832.99,yes,locked 2006.183.07:54:22.57/valo/05,652.99,yes,locked 2006.183.07:54:22.57/valo/06,772.99,yes,locked 2006.183.07:54:22.57/valo/07,832.99,yes,locked 2006.183.07:54:22.57/valo/08,852.99,yes,locked 2006.183.07:54:23.66/vb/01,04,usb,yes,29,28 2006.183.07:54:23.66/vb/02,04,usb,yes,31,32 2006.183.07:54:23.66/vb/03,04,usb,yes,27,31 2006.183.07:54:23.66/vb/04,04,usb,yes,28,28 2006.183.07:54:23.66/vb/05,04,usb,yes,27,31 2006.183.07:54:23.66/vb/06,04,usb,yes,28,30 2006.183.07:54:23.66/vb/07,04,usb,yes,30,29 2006.183.07:54:23.66/vb/08,04,usb,yes,27,31 2006.183.07:54:23.89/vblo/01,632.99,yes,locked 2006.183.07:54:23.89/vblo/02,640.99,yes,locked 2006.183.07:54:23.89/vblo/03,656.99,yes,locked 2006.183.07:54:23.89/vblo/04,712.99,yes,locked 2006.183.07:54:23.89/vblo/05,744.99,yes,locked 2006.183.07:54:23.89/vblo/06,752.99,yes,locked 2006.183.07:54:23.89/vblo/07,734.99,yes,locked 2006.183.07:54:23.89/vblo/08,744.99,yes,locked 2006.183.07:54:24.04/vabw/8 2006.183.07:54:24.19/vbbw/8 2006.183.07:54:24.28/xfe/off,on,14.7 2006.183.07:54:24.68/ifatt/23,28,28,28 2006.183.07:54:25.08/fmout-gps/S +3.32E-07 2006.183.07:54:25.16:!2006.183.07:55:20 2006.183.07:55:20.00:data_valid=off 2006.183.07:55:20.00:postob 2006.183.07:55:20.10/cable/+6.4507E-03 2006.183.07:55:20.10/wx/28.00,996.3,87 2006.183.07:55:21.08/fmout-gps/S +3.32E-07 2006.183.07:55:21.08:scan_name=183-0757,k06183,60 2006.183.07:55:21.09:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.183.07:55:21.14#flagr#flagr/antenna,new-source 2006.183.07:55:22.14:checkk5 2006.183.07:55:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:55:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:55:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:55:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:55:24.01/chk_obsdata//k5ts1/T1830754??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:55:24.38/chk_obsdata//k5ts2/T1830754??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:55:24.74/chk_obsdata//k5ts3/T1830754??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:55:25.11/chk_obsdata//k5ts4/T1830754??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:55:25.79/k5log//k5ts1_log_newline 2006.183.07:55:26.48/k5log//k5ts2_log_newline 2006.183.07:55:27.17/k5log//k5ts3_log_newline 2006.183.07:55:27.86/k5log//k5ts4_log_newline 2006.183.07:55:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:55:27.89:4f8m12a=2 2006.183.07:55:27.89$4f8m12a/echo=on 2006.183.07:55:27.89$4f8m12a/pcalon 2006.183.07:55:27.89$pcalon/"no phase cal control is implemented here 2006.183.07:55:27.89$4f8m12a/"tpicd=stop 2006.183.07:55:27.89$4f8m12a/vc4f8 2006.183.07:55:27.89$vc4f8/valo=1,532.99 2006.183.07:55:27.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:55:27.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:55:27.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:27.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:27.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:27.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:27.90#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:55:27.90#ibcon#first serial, iclass 40, count 0 2006.183.07:55:27.90#ibcon#enter sib2, iclass 40, count 0 2006.183.07:55:27.90#ibcon#flushed, iclass 40, count 0 2006.183.07:55:27.90#ibcon#about to write, iclass 40, count 0 2006.183.07:55:27.90#ibcon#wrote, iclass 40, count 0 2006.183.07:55:27.90#ibcon#about to read 3, iclass 40, count 0 2006.183.07:55:27.93#ibcon#read 3, iclass 40, count 0 2006.183.07:55:27.93#ibcon#about to read 4, iclass 40, count 0 2006.183.07:55:27.93#ibcon#read 4, iclass 40, count 0 2006.183.07:55:27.93#ibcon#about to read 5, iclass 40, count 0 2006.183.07:55:27.93#ibcon#read 5, iclass 40, count 0 2006.183.07:55:27.93#ibcon#about to read 6, iclass 40, count 0 2006.183.07:55:27.93#ibcon#read 6, iclass 40, count 0 2006.183.07:55:27.93#ibcon#end of sib2, iclass 40, count 0 2006.183.07:55:27.93#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:55:27.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:55:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:55:27.93#ibcon#*before write, iclass 40, count 0 2006.183.07:55:27.93#ibcon#enter sib2, iclass 40, count 0 2006.183.07:55:27.93#ibcon#flushed, iclass 40, count 0 2006.183.07:55:27.93#ibcon#about to write, iclass 40, count 0 2006.183.07:55:27.93#ibcon#wrote, iclass 40, count 0 2006.183.07:55:27.93#ibcon#about to read 3, iclass 40, count 0 2006.183.07:55:27.98#ibcon#read 3, iclass 40, count 0 2006.183.07:55:27.98#ibcon#about to read 4, iclass 40, count 0 2006.183.07:55:27.98#ibcon#read 4, iclass 40, count 0 2006.183.07:55:27.98#ibcon#about to read 5, iclass 40, count 0 2006.183.07:55:27.98#ibcon#read 5, iclass 40, count 0 2006.183.07:55:27.98#ibcon#about to read 6, iclass 40, count 0 2006.183.07:55:27.98#ibcon#read 6, iclass 40, count 0 2006.183.07:55:27.98#ibcon#end of sib2, iclass 40, count 0 2006.183.07:55:27.98#ibcon#*after write, iclass 40, count 0 2006.183.07:55:27.98#ibcon#*before return 0, iclass 40, count 0 2006.183.07:55:27.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:27.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:27.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:55:27.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:55:27.98$vc4f8/va=1,8 2006.183.07:55:27.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.07:55:27.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.07:55:27.98#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:27.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:27.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:27.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:27.98#ibcon#enter wrdev, iclass 4, count 2 2006.183.07:55:27.98#ibcon#first serial, iclass 4, count 2 2006.183.07:55:27.98#ibcon#enter sib2, iclass 4, count 2 2006.183.07:55:27.98#ibcon#flushed, iclass 4, count 2 2006.183.07:55:27.98#ibcon#about to write, iclass 4, count 2 2006.183.07:55:27.98#ibcon#wrote, iclass 4, count 2 2006.183.07:55:27.98#ibcon#about to read 3, iclass 4, count 2 2006.183.07:55:28.00#ibcon#read 3, iclass 4, count 2 2006.183.07:55:28.00#ibcon#about to read 4, iclass 4, count 2 2006.183.07:55:28.00#ibcon#read 4, iclass 4, count 2 2006.183.07:55:28.00#ibcon#about to read 5, iclass 4, count 2 2006.183.07:55:28.00#ibcon#read 5, iclass 4, count 2 2006.183.07:55:28.00#ibcon#about to read 6, iclass 4, count 2 2006.183.07:55:28.00#ibcon#read 6, iclass 4, count 2 2006.183.07:55:28.00#ibcon#end of sib2, iclass 4, count 2 2006.183.07:55:28.00#ibcon#*mode == 0, iclass 4, count 2 2006.183.07:55:28.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.07:55:28.00#ibcon#[25=AT01-08\r\n] 2006.183.07:55:28.00#ibcon#*before write, iclass 4, count 2 2006.183.07:55:28.00#ibcon#enter sib2, iclass 4, count 2 2006.183.07:55:28.00#ibcon#flushed, iclass 4, count 2 2006.183.07:55:28.00#ibcon#about to write, iclass 4, count 2 2006.183.07:55:28.00#ibcon#wrote, iclass 4, count 2 2006.183.07:55:28.00#ibcon#about to read 3, iclass 4, count 2 2006.183.07:55:28.03#ibcon#read 3, iclass 4, count 2 2006.183.07:55:28.03#ibcon#about to read 4, iclass 4, count 2 2006.183.07:55:28.03#ibcon#read 4, iclass 4, count 2 2006.183.07:55:28.03#ibcon#about to read 5, iclass 4, count 2 2006.183.07:55:28.03#ibcon#read 5, iclass 4, count 2 2006.183.07:55:28.03#ibcon#about to read 6, iclass 4, count 2 2006.183.07:55:28.03#ibcon#read 6, iclass 4, count 2 2006.183.07:55:28.03#ibcon#end of sib2, iclass 4, count 2 2006.183.07:55:28.03#ibcon#*after write, iclass 4, count 2 2006.183.07:55:28.03#ibcon#*before return 0, iclass 4, count 2 2006.183.07:55:28.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:28.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:28.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.07:55:28.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:28.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:28.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:28.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:28.15#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:55:28.15#ibcon#first serial, iclass 4, count 0 2006.183.07:55:28.15#ibcon#enter sib2, iclass 4, count 0 2006.183.07:55:28.15#ibcon#flushed, iclass 4, count 0 2006.183.07:55:28.15#ibcon#about to write, iclass 4, count 0 2006.183.07:55:28.15#ibcon#wrote, iclass 4, count 0 2006.183.07:55:28.15#ibcon#about to read 3, iclass 4, count 0 2006.183.07:55:28.17#ibcon#read 3, iclass 4, count 0 2006.183.07:55:28.17#ibcon#about to read 4, iclass 4, count 0 2006.183.07:55:28.17#ibcon#read 4, iclass 4, count 0 2006.183.07:55:28.17#ibcon#about to read 5, iclass 4, count 0 2006.183.07:55:28.17#ibcon#read 5, iclass 4, count 0 2006.183.07:55:28.17#ibcon#about to read 6, iclass 4, count 0 2006.183.07:55:28.17#ibcon#read 6, iclass 4, count 0 2006.183.07:55:28.17#ibcon#end of sib2, iclass 4, count 0 2006.183.07:55:28.17#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:55:28.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:55:28.17#ibcon#[25=USB\r\n] 2006.183.07:55:28.17#ibcon#*before write, iclass 4, count 0 2006.183.07:55:28.17#ibcon#enter sib2, iclass 4, count 0 2006.183.07:55:28.17#ibcon#flushed, iclass 4, count 0 2006.183.07:55:28.17#ibcon#about to write, iclass 4, count 0 2006.183.07:55:28.17#ibcon#wrote, iclass 4, count 0 2006.183.07:55:28.17#ibcon#about to read 3, iclass 4, count 0 2006.183.07:55:28.20#ibcon#read 3, iclass 4, count 0 2006.183.07:55:28.20#ibcon#about to read 4, iclass 4, count 0 2006.183.07:55:28.20#ibcon#read 4, iclass 4, count 0 2006.183.07:55:28.20#ibcon#about to read 5, iclass 4, count 0 2006.183.07:55:28.20#ibcon#read 5, iclass 4, count 0 2006.183.07:55:28.20#ibcon#about to read 6, iclass 4, count 0 2006.183.07:55:28.20#ibcon#read 6, iclass 4, count 0 2006.183.07:55:28.20#ibcon#end of sib2, iclass 4, count 0 2006.183.07:55:28.20#ibcon#*after write, iclass 4, count 0 2006.183.07:55:28.20#ibcon#*before return 0, iclass 4, count 0 2006.183.07:55:28.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:28.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:28.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:55:28.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:55:28.21$vc4f8/valo=2,572.99 2006.183.07:55:28.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:55:28.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:55:28.21#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:28.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:28.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:28.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:28.21#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:55:28.21#ibcon#first serial, iclass 6, count 0 2006.183.07:55:28.21#ibcon#enter sib2, iclass 6, count 0 2006.183.07:55:28.21#ibcon#flushed, iclass 6, count 0 2006.183.07:55:28.21#ibcon#about to write, iclass 6, count 0 2006.183.07:55:28.21#ibcon#wrote, iclass 6, count 0 2006.183.07:55:28.21#ibcon#about to read 3, iclass 6, count 0 2006.183.07:55:28.22#ibcon#read 3, iclass 6, count 0 2006.183.07:55:28.22#ibcon#about to read 4, iclass 6, count 0 2006.183.07:55:28.22#ibcon#read 4, iclass 6, count 0 2006.183.07:55:28.22#ibcon#about to read 5, iclass 6, count 0 2006.183.07:55:28.22#ibcon#read 5, iclass 6, count 0 2006.183.07:55:28.22#ibcon#about to read 6, iclass 6, count 0 2006.183.07:55:28.22#ibcon#read 6, iclass 6, count 0 2006.183.07:55:28.22#ibcon#end of sib2, iclass 6, count 0 2006.183.07:55:28.22#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:55:28.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:55:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:55:28.22#ibcon#*before write, iclass 6, count 0 2006.183.07:55:28.22#ibcon#enter sib2, iclass 6, count 0 2006.183.07:55:28.22#ibcon#flushed, iclass 6, count 0 2006.183.07:55:28.22#ibcon#about to write, iclass 6, count 0 2006.183.07:55:28.22#ibcon#wrote, iclass 6, count 0 2006.183.07:55:28.22#ibcon#about to read 3, iclass 6, count 0 2006.183.07:55:28.26#ibcon#read 3, iclass 6, count 0 2006.183.07:55:28.26#ibcon#about to read 4, iclass 6, count 0 2006.183.07:55:28.26#ibcon#read 4, iclass 6, count 0 2006.183.07:55:28.26#ibcon#about to read 5, iclass 6, count 0 2006.183.07:55:28.26#ibcon#read 5, iclass 6, count 0 2006.183.07:55:28.26#ibcon#about to read 6, iclass 6, count 0 2006.183.07:55:28.26#ibcon#read 6, iclass 6, count 0 2006.183.07:55:28.26#ibcon#end of sib2, iclass 6, count 0 2006.183.07:55:28.26#ibcon#*after write, iclass 6, count 0 2006.183.07:55:28.26#ibcon#*before return 0, iclass 6, count 0 2006.183.07:55:28.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:28.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:28.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:55:28.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:55:28.26$vc4f8/va=2,7 2006.183.07:55:28.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.07:55:28.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.07:55:28.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:28.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:28.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:28.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:28.32#ibcon#enter wrdev, iclass 10, count 2 2006.183.07:55:28.32#ibcon#first serial, iclass 10, count 2 2006.183.07:55:28.32#ibcon#enter sib2, iclass 10, count 2 2006.183.07:55:28.32#ibcon#flushed, iclass 10, count 2 2006.183.07:55:28.32#ibcon#about to write, iclass 10, count 2 2006.183.07:55:28.32#ibcon#wrote, iclass 10, count 2 2006.183.07:55:28.32#ibcon#about to read 3, iclass 10, count 2 2006.183.07:55:28.34#ibcon#read 3, iclass 10, count 2 2006.183.07:55:28.34#ibcon#about to read 4, iclass 10, count 2 2006.183.07:55:28.34#ibcon#read 4, iclass 10, count 2 2006.183.07:55:28.34#ibcon#about to read 5, iclass 10, count 2 2006.183.07:55:28.34#ibcon#read 5, iclass 10, count 2 2006.183.07:55:28.34#ibcon#about to read 6, iclass 10, count 2 2006.183.07:55:28.34#ibcon#read 6, iclass 10, count 2 2006.183.07:55:28.34#ibcon#end of sib2, iclass 10, count 2 2006.183.07:55:28.34#ibcon#*mode == 0, iclass 10, count 2 2006.183.07:55:28.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.07:55:28.34#ibcon#[25=AT02-07\r\n] 2006.183.07:55:28.34#ibcon#*before write, iclass 10, count 2 2006.183.07:55:28.34#ibcon#enter sib2, iclass 10, count 2 2006.183.07:55:28.34#ibcon#flushed, iclass 10, count 2 2006.183.07:55:28.34#ibcon#about to write, iclass 10, count 2 2006.183.07:55:28.34#ibcon#wrote, iclass 10, count 2 2006.183.07:55:28.34#ibcon#about to read 3, iclass 10, count 2 2006.183.07:55:28.37#ibcon#read 3, iclass 10, count 2 2006.183.07:55:28.37#ibcon#about to read 4, iclass 10, count 2 2006.183.07:55:28.37#ibcon#read 4, iclass 10, count 2 2006.183.07:55:28.37#ibcon#about to read 5, iclass 10, count 2 2006.183.07:55:28.37#ibcon#read 5, iclass 10, count 2 2006.183.07:55:28.37#ibcon#about to read 6, iclass 10, count 2 2006.183.07:55:28.37#ibcon#read 6, iclass 10, count 2 2006.183.07:55:28.37#ibcon#end of sib2, iclass 10, count 2 2006.183.07:55:28.37#ibcon#*after write, iclass 10, count 2 2006.183.07:55:28.37#ibcon#*before return 0, iclass 10, count 2 2006.183.07:55:28.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:28.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:28.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.07:55:28.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:28.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:28.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:28.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:28.49#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:55:28.49#ibcon#first serial, iclass 10, count 0 2006.183.07:55:28.49#ibcon#enter sib2, iclass 10, count 0 2006.183.07:55:28.49#ibcon#flushed, iclass 10, count 0 2006.183.07:55:28.49#ibcon#about to write, iclass 10, count 0 2006.183.07:55:28.49#ibcon#wrote, iclass 10, count 0 2006.183.07:55:28.49#ibcon#about to read 3, iclass 10, count 0 2006.183.07:55:28.51#ibcon#read 3, iclass 10, count 0 2006.183.07:55:28.51#ibcon#about to read 4, iclass 10, count 0 2006.183.07:55:28.51#ibcon#read 4, iclass 10, count 0 2006.183.07:55:28.51#ibcon#about to read 5, iclass 10, count 0 2006.183.07:55:28.51#ibcon#read 5, iclass 10, count 0 2006.183.07:55:28.51#ibcon#about to read 6, iclass 10, count 0 2006.183.07:55:28.51#ibcon#read 6, iclass 10, count 0 2006.183.07:55:28.51#ibcon#end of sib2, iclass 10, count 0 2006.183.07:55:28.51#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:55:28.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:55:28.51#ibcon#[25=USB\r\n] 2006.183.07:55:28.51#ibcon#*before write, iclass 10, count 0 2006.183.07:55:28.51#ibcon#enter sib2, iclass 10, count 0 2006.183.07:55:28.51#ibcon#flushed, iclass 10, count 0 2006.183.07:55:28.51#ibcon#about to write, iclass 10, count 0 2006.183.07:55:28.51#ibcon#wrote, iclass 10, count 0 2006.183.07:55:28.51#ibcon#about to read 3, iclass 10, count 0 2006.183.07:55:28.54#ibcon#read 3, iclass 10, count 0 2006.183.07:55:28.54#ibcon#about to read 4, iclass 10, count 0 2006.183.07:55:28.54#ibcon#read 4, iclass 10, count 0 2006.183.07:55:28.54#ibcon#about to read 5, iclass 10, count 0 2006.183.07:55:28.54#ibcon#read 5, iclass 10, count 0 2006.183.07:55:28.54#ibcon#about to read 6, iclass 10, count 0 2006.183.07:55:28.54#ibcon#read 6, iclass 10, count 0 2006.183.07:55:28.54#ibcon#end of sib2, iclass 10, count 0 2006.183.07:55:28.54#ibcon#*after write, iclass 10, count 0 2006.183.07:55:28.54#ibcon#*before return 0, iclass 10, count 0 2006.183.07:55:28.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:28.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:28.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:55:28.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:55:28.54$vc4f8/valo=3,672.99 2006.183.07:55:28.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.07:55:28.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.07:55:28.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:28.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:28.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:28.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:28.54#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:55:28.54#ibcon#first serial, iclass 12, count 0 2006.183.07:55:28.54#ibcon#enter sib2, iclass 12, count 0 2006.183.07:55:28.54#ibcon#flushed, iclass 12, count 0 2006.183.07:55:28.54#ibcon#about to write, iclass 12, count 0 2006.183.07:55:28.54#ibcon#wrote, iclass 12, count 0 2006.183.07:55:28.54#ibcon#about to read 3, iclass 12, count 0 2006.183.07:55:28.56#ibcon#read 3, iclass 12, count 0 2006.183.07:55:28.56#ibcon#about to read 4, iclass 12, count 0 2006.183.07:55:28.56#ibcon#read 4, iclass 12, count 0 2006.183.07:55:28.56#ibcon#about to read 5, iclass 12, count 0 2006.183.07:55:28.56#ibcon#read 5, iclass 12, count 0 2006.183.07:55:28.56#ibcon#about to read 6, iclass 12, count 0 2006.183.07:55:28.56#ibcon#read 6, iclass 12, count 0 2006.183.07:55:28.56#ibcon#end of sib2, iclass 12, count 0 2006.183.07:55:28.56#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:55:28.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:55:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:55:28.56#ibcon#*before write, iclass 12, count 0 2006.183.07:55:28.56#ibcon#enter sib2, iclass 12, count 0 2006.183.07:55:28.56#ibcon#flushed, iclass 12, count 0 2006.183.07:55:28.56#ibcon#about to write, iclass 12, count 0 2006.183.07:55:28.56#ibcon#wrote, iclass 12, count 0 2006.183.07:55:28.56#ibcon#about to read 3, iclass 12, count 0 2006.183.07:55:28.60#ibcon#read 3, iclass 12, count 0 2006.183.07:55:28.60#ibcon#about to read 4, iclass 12, count 0 2006.183.07:55:28.60#ibcon#read 4, iclass 12, count 0 2006.183.07:55:28.60#ibcon#about to read 5, iclass 12, count 0 2006.183.07:55:28.60#ibcon#read 5, iclass 12, count 0 2006.183.07:55:28.60#ibcon#about to read 6, iclass 12, count 0 2006.183.07:55:28.60#ibcon#read 6, iclass 12, count 0 2006.183.07:55:28.60#ibcon#end of sib2, iclass 12, count 0 2006.183.07:55:28.60#ibcon#*after write, iclass 12, count 0 2006.183.07:55:28.60#ibcon#*before return 0, iclass 12, count 0 2006.183.07:55:28.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:28.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:28.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:55:28.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:55:28.60$vc4f8/va=3,6 2006.183.07:55:28.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.07:55:28.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.07:55:28.60#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:28.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:28.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:28.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:28.66#ibcon#enter wrdev, iclass 14, count 2 2006.183.07:55:28.66#ibcon#first serial, iclass 14, count 2 2006.183.07:55:28.66#ibcon#enter sib2, iclass 14, count 2 2006.183.07:55:28.66#ibcon#flushed, iclass 14, count 2 2006.183.07:55:28.66#ibcon#about to write, iclass 14, count 2 2006.183.07:55:28.66#ibcon#wrote, iclass 14, count 2 2006.183.07:55:28.66#ibcon#about to read 3, iclass 14, count 2 2006.183.07:55:28.68#ibcon#read 3, iclass 14, count 2 2006.183.07:55:28.68#ibcon#about to read 4, iclass 14, count 2 2006.183.07:55:28.68#ibcon#read 4, iclass 14, count 2 2006.183.07:55:28.68#ibcon#about to read 5, iclass 14, count 2 2006.183.07:55:28.68#ibcon#read 5, iclass 14, count 2 2006.183.07:55:28.68#ibcon#about to read 6, iclass 14, count 2 2006.183.07:55:28.68#ibcon#read 6, iclass 14, count 2 2006.183.07:55:28.68#ibcon#end of sib2, iclass 14, count 2 2006.183.07:55:28.68#ibcon#*mode == 0, iclass 14, count 2 2006.183.07:55:28.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.07:55:28.68#ibcon#[25=AT03-06\r\n] 2006.183.07:55:28.68#ibcon#*before write, iclass 14, count 2 2006.183.07:55:28.68#ibcon#enter sib2, iclass 14, count 2 2006.183.07:55:28.68#ibcon#flushed, iclass 14, count 2 2006.183.07:55:28.68#ibcon#about to write, iclass 14, count 2 2006.183.07:55:28.68#ibcon#wrote, iclass 14, count 2 2006.183.07:55:28.68#ibcon#about to read 3, iclass 14, count 2 2006.183.07:55:28.71#ibcon#read 3, iclass 14, count 2 2006.183.07:55:28.71#ibcon#about to read 4, iclass 14, count 2 2006.183.07:55:28.71#ibcon#read 4, iclass 14, count 2 2006.183.07:55:28.71#ibcon#about to read 5, iclass 14, count 2 2006.183.07:55:28.71#ibcon#read 5, iclass 14, count 2 2006.183.07:55:28.71#ibcon#about to read 6, iclass 14, count 2 2006.183.07:55:28.71#ibcon#read 6, iclass 14, count 2 2006.183.07:55:28.71#ibcon#end of sib2, iclass 14, count 2 2006.183.07:55:28.71#ibcon#*after write, iclass 14, count 2 2006.183.07:55:28.71#ibcon#*before return 0, iclass 14, count 2 2006.183.07:55:28.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:28.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:28.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.07:55:28.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:28.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:28.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:28.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:28.83#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:55:28.83#ibcon#first serial, iclass 14, count 0 2006.183.07:55:28.83#ibcon#enter sib2, iclass 14, count 0 2006.183.07:55:28.83#ibcon#flushed, iclass 14, count 0 2006.183.07:55:28.83#ibcon#about to write, iclass 14, count 0 2006.183.07:55:28.83#ibcon#wrote, iclass 14, count 0 2006.183.07:55:28.83#ibcon#about to read 3, iclass 14, count 0 2006.183.07:55:28.85#ibcon#read 3, iclass 14, count 0 2006.183.07:55:28.85#ibcon#about to read 4, iclass 14, count 0 2006.183.07:55:28.85#ibcon#read 4, iclass 14, count 0 2006.183.07:55:28.85#ibcon#about to read 5, iclass 14, count 0 2006.183.07:55:28.85#ibcon#read 5, iclass 14, count 0 2006.183.07:55:28.85#ibcon#about to read 6, iclass 14, count 0 2006.183.07:55:28.85#ibcon#read 6, iclass 14, count 0 2006.183.07:55:28.85#ibcon#end of sib2, iclass 14, count 0 2006.183.07:55:28.85#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:55:28.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:55:28.85#ibcon#[25=USB\r\n] 2006.183.07:55:28.85#ibcon#*before write, iclass 14, count 0 2006.183.07:55:28.85#ibcon#enter sib2, iclass 14, count 0 2006.183.07:55:28.85#ibcon#flushed, iclass 14, count 0 2006.183.07:55:28.85#ibcon#about to write, iclass 14, count 0 2006.183.07:55:28.85#ibcon#wrote, iclass 14, count 0 2006.183.07:55:28.85#ibcon#about to read 3, iclass 14, count 0 2006.183.07:55:28.88#ibcon#read 3, iclass 14, count 0 2006.183.07:55:28.88#ibcon#about to read 4, iclass 14, count 0 2006.183.07:55:28.88#ibcon#read 4, iclass 14, count 0 2006.183.07:55:28.88#ibcon#about to read 5, iclass 14, count 0 2006.183.07:55:28.88#ibcon#read 5, iclass 14, count 0 2006.183.07:55:28.88#ibcon#about to read 6, iclass 14, count 0 2006.183.07:55:28.88#ibcon#read 6, iclass 14, count 0 2006.183.07:55:28.88#ibcon#end of sib2, iclass 14, count 0 2006.183.07:55:28.88#ibcon#*after write, iclass 14, count 0 2006.183.07:55:28.88#ibcon#*before return 0, iclass 14, count 0 2006.183.07:55:28.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:28.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:28.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:55:28.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:55:28.88$vc4f8/valo=4,832.99 2006.183.07:55:28.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.07:55:28.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.07:55:28.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:28.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:28.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:28.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:28.88#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:55:28.88#ibcon#first serial, iclass 16, count 0 2006.183.07:55:28.88#ibcon#enter sib2, iclass 16, count 0 2006.183.07:55:28.88#ibcon#flushed, iclass 16, count 0 2006.183.07:55:28.88#ibcon#about to write, iclass 16, count 0 2006.183.07:55:28.88#ibcon#wrote, iclass 16, count 0 2006.183.07:55:28.88#ibcon#about to read 3, iclass 16, count 0 2006.183.07:55:28.90#ibcon#read 3, iclass 16, count 0 2006.183.07:55:28.90#ibcon#about to read 4, iclass 16, count 0 2006.183.07:55:28.90#ibcon#read 4, iclass 16, count 0 2006.183.07:55:28.90#ibcon#about to read 5, iclass 16, count 0 2006.183.07:55:28.90#ibcon#read 5, iclass 16, count 0 2006.183.07:55:28.90#ibcon#about to read 6, iclass 16, count 0 2006.183.07:55:28.90#ibcon#read 6, iclass 16, count 0 2006.183.07:55:28.90#ibcon#end of sib2, iclass 16, count 0 2006.183.07:55:28.90#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:55:28.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:55:28.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:55:28.90#ibcon#*before write, iclass 16, count 0 2006.183.07:55:28.90#ibcon#enter sib2, iclass 16, count 0 2006.183.07:55:28.90#ibcon#flushed, iclass 16, count 0 2006.183.07:55:28.90#ibcon#about to write, iclass 16, count 0 2006.183.07:55:28.90#ibcon#wrote, iclass 16, count 0 2006.183.07:55:28.90#ibcon#about to read 3, iclass 16, count 0 2006.183.07:55:28.94#ibcon#read 3, iclass 16, count 0 2006.183.07:55:28.94#ibcon#about to read 4, iclass 16, count 0 2006.183.07:55:28.94#ibcon#read 4, iclass 16, count 0 2006.183.07:55:28.94#ibcon#about to read 5, iclass 16, count 0 2006.183.07:55:28.94#ibcon#read 5, iclass 16, count 0 2006.183.07:55:28.94#ibcon#about to read 6, iclass 16, count 0 2006.183.07:55:28.94#ibcon#read 6, iclass 16, count 0 2006.183.07:55:28.94#ibcon#end of sib2, iclass 16, count 0 2006.183.07:55:28.94#ibcon#*after write, iclass 16, count 0 2006.183.07:55:28.94#ibcon#*before return 0, iclass 16, count 0 2006.183.07:55:28.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:28.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:28.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:55:28.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:55:28.94$vc4f8/va=4,7 2006.183.07:55:28.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.07:55:28.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.07:55:28.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:28.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:29.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:29.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:29.00#ibcon#enter wrdev, iclass 18, count 2 2006.183.07:55:29.00#ibcon#first serial, iclass 18, count 2 2006.183.07:55:29.00#ibcon#enter sib2, iclass 18, count 2 2006.183.07:55:29.00#ibcon#flushed, iclass 18, count 2 2006.183.07:55:29.00#ibcon#about to write, iclass 18, count 2 2006.183.07:55:29.00#ibcon#wrote, iclass 18, count 2 2006.183.07:55:29.00#ibcon#about to read 3, iclass 18, count 2 2006.183.07:55:29.02#ibcon#read 3, iclass 18, count 2 2006.183.07:55:29.02#ibcon#about to read 4, iclass 18, count 2 2006.183.07:55:29.02#ibcon#read 4, iclass 18, count 2 2006.183.07:55:29.02#ibcon#about to read 5, iclass 18, count 2 2006.183.07:55:29.02#ibcon#read 5, iclass 18, count 2 2006.183.07:55:29.02#ibcon#about to read 6, iclass 18, count 2 2006.183.07:55:29.02#ibcon#read 6, iclass 18, count 2 2006.183.07:55:29.02#ibcon#end of sib2, iclass 18, count 2 2006.183.07:55:29.02#ibcon#*mode == 0, iclass 18, count 2 2006.183.07:55:29.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.07:55:29.02#ibcon#[25=AT04-07\r\n] 2006.183.07:55:29.02#ibcon#*before write, iclass 18, count 2 2006.183.07:55:29.02#ibcon#enter sib2, iclass 18, count 2 2006.183.07:55:29.02#ibcon#flushed, iclass 18, count 2 2006.183.07:55:29.02#ibcon#about to write, iclass 18, count 2 2006.183.07:55:29.02#ibcon#wrote, iclass 18, count 2 2006.183.07:55:29.02#ibcon#about to read 3, iclass 18, count 2 2006.183.07:55:29.05#ibcon#read 3, iclass 18, count 2 2006.183.07:55:29.05#ibcon#about to read 4, iclass 18, count 2 2006.183.07:55:29.05#ibcon#read 4, iclass 18, count 2 2006.183.07:55:29.05#ibcon#about to read 5, iclass 18, count 2 2006.183.07:55:29.05#ibcon#read 5, iclass 18, count 2 2006.183.07:55:29.05#ibcon#about to read 6, iclass 18, count 2 2006.183.07:55:29.05#ibcon#read 6, iclass 18, count 2 2006.183.07:55:29.05#ibcon#end of sib2, iclass 18, count 2 2006.183.07:55:29.05#ibcon#*after write, iclass 18, count 2 2006.183.07:55:29.05#ibcon#*before return 0, iclass 18, count 2 2006.183.07:55:29.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:29.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:29.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.07:55:29.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:29.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:29.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:29.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:29.17#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:55:29.17#ibcon#first serial, iclass 18, count 0 2006.183.07:55:29.17#ibcon#enter sib2, iclass 18, count 0 2006.183.07:55:29.17#ibcon#flushed, iclass 18, count 0 2006.183.07:55:29.17#ibcon#about to write, iclass 18, count 0 2006.183.07:55:29.17#ibcon#wrote, iclass 18, count 0 2006.183.07:55:29.17#ibcon#about to read 3, iclass 18, count 0 2006.183.07:55:29.19#ibcon#read 3, iclass 18, count 0 2006.183.07:55:29.19#ibcon#about to read 4, iclass 18, count 0 2006.183.07:55:29.19#ibcon#read 4, iclass 18, count 0 2006.183.07:55:29.19#ibcon#about to read 5, iclass 18, count 0 2006.183.07:55:29.19#ibcon#read 5, iclass 18, count 0 2006.183.07:55:29.19#ibcon#about to read 6, iclass 18, count 0 2006.183.07:55:29.19#ibcon#read 6, iclass 18, count 0 2006.183.07:55:29.19#ibcon#end of sib2, iclass 18, count 0 2006.183.07:55:29.19#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:55:29.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:55:29.19#ibcon#[25=USB\r\n] 2006.183.07:55:29.19#ibcon#*before write, iclass 18, count 0 2006.183.07:55:29.19#ibcon#enter sib2, iclass 18, count 0 2006.183.07:55:29.19#ibcon#flushed, iclass 18, count 0 2006.183.07:55:29.19#ibcon#about to write, iclass 18, count 0 2006.183.07:55:29.19#ibcon#wrote, iclass 18, count 0 2006.183.07:55:29.19#ibcon#about to read 3, iclass 18, count 0 2006.183.07:55:29.22#ibcon#read 3, iclass 18, count 0 2006.183.07:55:29.22#ibcon#about to read 4, iclass 18, count 0 2006.183.07:55:29.22#ibcon#read 4, iclass 18, count 0 2006.183.07:55:29.22#ibcon#about to read 5, iclass 18, count 0 2006.183.07:55:29.22#ibcon#read 5, iclass 18, count 0 2006.183.07:55:29.22#ibcon#about to read 6, iclass 18, count 0 2006.183.07:55:29.22#ibcon#read 6, iclass 18, count 0 2006.183.07:55:29.22#ibcon#end of sib2, iclass 18, count 0 2006.183.07:55:29.22#ibcon#*after write, iclass 18, count 0 2006.183.07:55:29.22#ibcon#*before return 0, iclass 18, count 0 2006.183.07:55:29.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:29.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:29.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:55:29.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:55:29.22$vc4f8/valo=5,652.99 2006.183.07:55:29.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.07:55:29.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.07:55:29.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:29.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:29.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:29.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:29.22#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:55:29.22#ibcon#first serial, iclass 20, count 0 2006.183.07:55:29.22#ibcon#enter sib2, iclass 20, count 0 2006.183.07:55:29.22#ibcon#flushed, iclass 20, count 0 2006.183.07:55:29.22#ibcon#about to write, iclass 20, count 0 2006.183.07:55:29.22#ibcon#wrote, iclass 20, count 0 2006.183.07:55:29.22#ibcon#about to read 3, iclass 20, count 0 2006.183.07:55:29.24#ibcon#read 3, iclass 20, count 0 2006.183.07:55:29.24#ibcon#about to read 4, iclass 20, count 0 2006.183.07:55:29.24#ibcon#read 4, iclass 20, count 0 2006.183.07:55:29.24#ibcon#about to read 5, iclass 20, count 0 2006.183.07:55:29.24#ibcon#read 5, iclass 20, count 0 2006.183.07:55:29.24#ibcon#about to read 6, iclass 20, count 0 2006.183.07:55:29.24#ibcon#read 6, iclass 20, count 0 2006.183.07:55:29.24#ibcon#end of sib2, iclass 20, count 0 2006.183.07:55:29.24#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:55:29.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:55:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:55:29.24#ibcon#*before write, iclass 20, count 0 2006.183.07:55:29.24#ibcon#enter sib2, iclass 20, count 0 2006.183.07:55:29.24#ibcon#flushed, iclass 20, count 0 2006.183.07:55:29.24#ibcon#about to write, iclass 20, count 0 2006.183.07:55:29.24#ibcon#wrote, iclass 20, count 0 2006.183.07:55:29.24#ibcon#about to read 3, iclass 20, count 0 2006.183.07:55:29.28#ibcon#read 3, iclass 20, count 0 2006.183.07:55:29.28#ibcon#about to read 4, iclass 20, count 0 2006.183.07:55:29.28#ibcon#read 4, iclass 20, count 0 2006.183.07:55:29.28#ibcon#about to read 5, iclass 20, count 0 2006.183.07:55:29.28#ibcon#read 5, iclass 20, count 0 2006.183.07:55:29.28#ibcon#about to read 6, iclass 20, count 0 2006.183.07:55:29.28#ibcon#read 6, iclass 20, count 0 2006.183.07:55:29.28#ibcon#end of sib2, iclass 20, count 0 2006.183.07:55:29.28#ibcon#*after write, iclass 20, count 0 2006.183.07:55:29.28#ibcon#*before return 0, iclass 20, count 0 2006.183.07:55:29.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:29.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:29.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:55:29.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:55:29.28$vc4f8/va=5,7 2006.183.07:55:29.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.07:55:29.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.07:55:29.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:29.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:29.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:29.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:29.34#ibcon#enter wrdev, iclass 22, count 2 2006.183.07:55:29.34#ibcon#first serial, iclass 22, count 2 2006.183.07:55:29.34#ibcon#enter sib2, iclass 22, count 2 2006.183.07:55:29.34#ibcon#flushed, iclass 22, count 2 2006.183.07:55:29.34#ibcon#about to write, iclass 22, count 2 2006.183.07:55:29.34#ibcon#wrote, iclass 22, count 2 2006.183.07:55:29.34#ibcon#about to read 3, iclass 22, count 2 2006.183.07:55:29.36#ibcon#read 3, iclass 22, count 2 2006.183.07:55:29.36#ibcon#about to read 4, iclass 22, count 2 2006.183.07:55:29.36#ibcon#read 4, iclass 22, count 2 2006.183.07:55:29.36#ibcon#about to read 5, iclass 22, count 2 2006.183.07:55:29.36#ibcon#read 5, iclass 22, count 2 2006.183.07:55:29.36#ibcon#about to read 6, iclass 22, count 2 2006.183.07:55:29.36#ibcon#read 6, iclass 22, count 2 2006.183.07:55:29.36#ibcon#end of sib2, iclass 22, count 2 2006.183.07:55:29.36#ibcon#*mode == 0, iclass 22, count 2 2006.183.07:55:29.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.07:55:29.36#ibcon#[25=AT05-07\r\n] 2006.183.07:55:29.36#ibcon#*before write, iclass 22, count 2 2006.183.07:55:29.36#ibcon#enter sib2, iclass 22, count 2 2006.183.07:55:29.36#ibcon#flushed, iclass 22, count 2 2006.183.07:55:29.36#ibcon#about to write, iclass 22, count 2 2006.183.07:55:29.36#ibcon#wrote, iclass 22, count 2 2006.183.07:55:29.36#ibcon#about to read 3, iclass 22, count 2 2006.183.07:55:29.39#ibcon#read 3, iclass 22, count 2 2006.183.07:55:29.39#ibcon#about to read 4, iclass 22, count 2 2006.183.07:55:29.39#ibcon#read 4, iclass 22, count 2 2006.183.07:55:29.39#ibcon#about to read 5, iclass 22, count 2 2006.183.07:55:29.39#ibcon#read 5, iclass 22, count 2 2006.183.07:55:29.39#ibcon#about to read 6, iclass 22, count 2 2006.183.07:55:29.39#ibcon#read 6, iclass 22, count 2 2006.183.07:55:29.39#ibcon#end of sib2, iclass 22, count 2 2006.183.07:55:29.39#ibcon#*after write, iclass 22, count 2 2006.183.07:55:29.39#ibcon#*before return 0, iclass 22, count 2 2006.183.07:55:29.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:29.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:29.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.07:55:29.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:29.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:29.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:29.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:29.51#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:55:29.51#ibcon#first serial, iclass 22, count 0 2006.183.07:55:29.51#ibcon#enter sib2, iclass 22, count 0 2006.183.07:55:29.51#ibcon#flushed, iclass 22, count 0 2006.183.07:55:29.51#ibcon#about to write, iclass 22, count 0 2006.183.07:55:29.51#ibcon#wrote, iclass 22, count 0 2006.183.07:55:29.51#ibcon#about to read 3, iclass 22, count 0 2006.183.07:55:29.53#ibcon#read 3, iclass 22, count 0 2006.183.07:55:29.53#ibcon#about to read 4, iclass 22, count 0 2006.183.07:55:29.53#ibcon#read 4, iclass 22, count 0 2006.183.07:55:29.53#ibcon#about to read 5, iclass 22, count 0 2006.183.07:55:29.53#ibcon#read 5, iclass 22, count 0 2006.183.07:55:29.53#ibcon#about to read 6, iclass 22, count 0 2006.183.07:55:29.53#ibcon#read 6, iclass 22, count 0 2006.183.07:55:29.53#ibcon#end of sib2, iclass 22, count 0 2006.183.07:55:29.53#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:55:29.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:55:29.53#ibcon#[25=USB\r\n] 2006.183.07:55:29.53#ibcon#*before write, iclass 22, count 0 2006.183.07:55:29.53#ibcon#enter sib2, iclass 22, count 0 2006.183.07:55:29.53#ibcon#flushed, iclass 22, count 0 2006.183.07:55:29.53#ibcon#about to write, iclass 22, count 0 2006.183.07:55:29.53#ibcon#wrote, iclass 22, count 0 2006.183.07:55:29.53#ibcon#about to read 3, iclass 22, count 0 2006.183.07:55:29.56#ibcon#read 3, iclass 22, count 0 2006.183.07:55:29.56#ibcon#about to read 4, iclass 22, count 0 2006.183.07:55:29.56#ibcon#read 4, iclass 22, count 0 2006.183.07:55:29.56#ibcon#about to read 5, iclass 22, count 0 2006.183.07:55:29.56#ibcon#read 5, iclass 22, count 0 2006.183.07:55:29.56#ibcon#about to read 6, iclass 22, count 0 2006.183.07:55:29.56#ibcon#read 6, iclass 22, count 0 2006.183.07:55:29.56#ibcon#end of sib2, iclass 22, count 0 2006.183.07:55:29.56#ibcon#*after write, iclass 22, count 0 2006.183.07:55:29.56#ibcon#*before return 0, iclass 22, count 0 2006.183.07:55:29.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:29.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:29.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:55:29.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:55:29.56$vc4f8/valo=6,772.99 2006.183.07:55:29.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.07:55:29.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.07:55:29.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:29.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:29.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:29.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:29.56#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:55:29.56#ibcon#first serial, iclass 24, count 0 2006.183.07:55:29.56#ibcon#enter sib2, iclass 24, count 0 2006.183.07:55:29.56#ibcon#flushed, iclass 24, count 0 2006.183.07:55:29.56#ibcon#about to write, iclass 24, count 0 2006.183.07:55:29.56#ibcon#wrote, iclass 24, count 0 2006.183.07:55:29.56#ibcon#about to read 3, iclass 24, count 0 2006.183.07:55:29.58#ibcon#read 3, iclass 24, count 0 2006.183.07:55:29.58#ibcon#about to read 4, iclass 24, count 0 2006.183.07:55:29.58#ibcon#read 4, iclass 24, count 0 2006.183.07:55:29.58#ibcon#about to read 5, iclass 24, count 0 2006.183.07:55:29.58#ibcon#read 5, iclass 24, count 0 2006.183.07:55:29.58#ibcon#about to read 6, iclass 24, count 0 2006.183.07:55:29.58#ibcon#read 6, iclass 24, count 0 2006.183.07:55:29.59#ibcon#end of sib2, iclass 24, count 0 2006.183.07:55:29.59#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:55:29.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:55:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:55:29.59#ibcon#*before write, iclass 24, count 0 2006.183.07:55:29.59#ibcon#enter sib2, iclass 24, count 0 2006.183.07:55:29.59#ibcon#flushed, iclass 24, count 0 2006.183.07:55:29.59#ibcon#about to write, iclass 24, count 0 2006.183.07:55:29.59#ibcon#wrote, iclass 24, count 0 2006.183.07:55:29.59#ibcon#about to read 3, iclass 24, count 0 2006.183.07:55:29.63#ibcon#read 3, iclass 24, count 0 2006.183.07:55:29.63#ibcon#about to read 4, iclass 24, count 0 2006.183.07:55:29.63#ibcon#read 4, iclass 24, count 0 2006.183.07:55:29.63#ibcon#about to read 5, iclass 24, count 0 2006.183.07:55:29.63#ibcon#read 5, iclass 24, count 0 2006.183.07:55:29.63#ibcon#about to read 6, iclass 24, count 0 2006.183.07:55:29.63#ibcon#read 6, iclass 24, count 0 2006.183.07:55:29.63#ibcon#end of sib2, iclass 24, count 0 2006.183.07:55:29.63#ibcon#*after write, iclass 24, count 0 2006.183.07:55:29.63#ibcon#*before return 0, iclass 24, count 0 2006.183.07:55:29.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:29.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:29.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:55:29.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:55:29.63$vc4f8/va=6,6 2006.183.07:55:29.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.07:55:29.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.07:55:29.63#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:29.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:55:29.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:55:29.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:55:29.68#ibcon#enter wrdev, iclass 26, count 2 2006.183.07:55:29.68#ibcon#first serial, iclass 26, count 2 2006.183.07:55:29.68#ibcon#enter sib2, iclass 26, count 2 2006.183.07:55:29.68#ibcon#flushed, iclass 26, count 2 2006.183.07:55:29.68#ibcon#about to write, iclass 26, count 2 2006.183.07:55:29.68#ibcon#wrote, iclass 26, count 2 2006.183.07:55:29.68#ibcon#about to read 3, iclass 26, count 2 2006.183.07:55:29.70#ibcon#read 3, iclass 26, count 2 2006.183.07:55:29.70#ibcon#about to read 4, iclass 26, count 2 2006.183.07:55:29.70#ibcon#read 4, iclass 26, count 2 2006.183.07:55:29.70#ibcon#about to read 5, iclass 26, count 2 2006.183.07:55:29.70#ibcon#read 5, iclass 26, count 2 2006.183.07:55:29.70#ibcon#about to read 6, iclass 26, count 2 2006.183.07:55:29.70#ibcon#read 6, iclass 26, count 2 2006.183.07:55:29.70#ibcon#end of sib2, iclass 26, count 2 2006.183.07:55:29.70#ibcon#*mode == 0, iclass 26, count 2 2006.183.07:55:29.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.07:55:29.70#ibcon#[25=AT06-06\r\n] 2006.183.07:55:29.70#ibcon#*before write, iclass 26, count 2 2006.183.07:55:29.70#ibcon#enter sib2, iclass 26, count 2 2006.183.07:55:29.70#ibcon#flushed, iclass 26, count 2 2006.183.07:55:29.70#ibcon#about to write, iclass 26, count 2 2006.183.07:55:29.70#ibcon#wrote, iclass 26, count 2 2006.183.07:55:29.70#ibcon#about to read 3, iclass 26, count 2 2006.183.07:55:29.73#ibcon#read 3, iclass 26, count 2 2006.183.07:55:29.73#ibcon#about to read 4, iclass 26, count 2 2006.183.07:55:29.73#ibcon#read 4, iclass 26, count 2 2006.183.07:55:29.73#ibcon#about to read 5, iclass 26, count 2 2006.183.07:55:29.73#ibcon#read 5, iclass 26, count 2 2006.183.07:55:29.73#ibcon#about to read 6, iclass 26, count 2 2006.183.07:55:29.73#ibcon#read 6, iclass 26, count 2 2006.183.07:55:29.73#ibcon#end of sib2, iclass 26, count 2 2006.183.07:55:29.73#ibcon#*after write, iclass 26, count 2 2006.183.07:55:29.73#ibcon#*before return 0, iclass 26, count 2 2006.183.07:55:29.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:55:29.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.07:55:29.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.07:55:29.73#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:29.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:55:29.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:55:29.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:55:29.85#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:55:29.85#ibcon#first serial, iclass 26, count 0 2006.183.07:55:29.85#ibcon#enter sib2, iclass 26, count 0 2006.183.07:55:29.85#ibcon#flushed, iclass 26, count 0 2006.183.07:55:29.85#ibcon#about to write, iclass 26, count 0 2006.183.07:55:29.85#ibcon#wrote, iclass 26, count 0 2006.183.07:55:29.85#ibcon#about to read 3, iclass 26, count 0 2006.183.07:55:29.87#ibcon#read 3, iclass 26, count 0 2006.183.07:55:29.87#ibcon#about to read 4, iclass 26, count 0 2006.183.07:55:29.87#ibcon#read 4, iclass 26, count 0 2006.183.07:55:29.87#ibcon#about to read 5, iclass 26, count 0 2006.183.07:55:29.87#ibcon#read 5, iclass 26, count 0 2006.183.07:55:29.87#ibcon#about to read 6, iclass 26, count 0 2006.183.07:55:29.87#ibcon#read 6, iclass 26, count 0 2006.183.07:55:29.87#ibcon#end of sib2, iclass 26, count 0 2006.183.07:55:29.87#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:55:29.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:55:29.87#ibcon#[25=USB\r\n] 2006.183.07:55:29.87#ibcon#*before write, iclass 26, count 0 2006.183.07:55:29.87#ibcon#enter sib2, iclass 26, count 0 2006.183.07:55:29.87#ibcon#flushed, iclass 26, count 0 2006.183.07:55:29.87#ibcon#about to write, iclass 26, count 0 2006.183.07:55:29.87#ibcon#wrote, iclass 26, count 0 2006.183.07:55:29.87#ibcon#about to read 3, iclass 26, count 0 2006.183.07:55:29.90#ibcon#read 3, iclass 26, count 0 2006.183.07:55:29.90#ibcon#about to read 4, iclass 26, count 0 2006.183.07:55:29.90#ibcon#read 4, iclass 26, count 0 2006.183.07:55:29.90#ibcon#about to read 5, iclass 26, count 0 2006.183.07:55:29.90#ibcon#read 5, iclass 26, count 0 2006.183.07:55:29.90#ibcon#about to read 6, iclass 26, count 0 2006.183.07:55:29.90#ibcon#read 6, iclass 26, count 0 2006.183.07:55:29.90#ibcon#end of sib2, iclass 26, count 0 2006.183.07:55:29.90#ibcon#*after write, iclass 26, count 0 2006.183.07:55:29.90#ibcon#*before return 0, iclass 26, count 0 2006.183.07:55:29.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:55:29.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.07:55:29.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:55:29.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:55:29.90$vc4f8/valo=7,832.99 2006.183.07:55:29.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.07:55:29.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.07:55:29.90#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:29.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:55:29.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:55:29.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:55:29.90#ibcon#enter wrdev, iclass 28, count 0 2006.183.07:55:29.90#ibcon#first serial, iclass 28, count 0 2006.183.07:55:29.90#ibcon#enter sib2, iclass 28, count 0 2006.183.07:55:29.90#ibcon#flushed, iclass 28, count 0 2006.183.07:55:29.90#ibcon#about to write, iclass 28, count 0 2006.183.07:55:29.90#ibcon#wrote, iclass 28, count 0 2006.183.07:55:29.90#ibcon#about to read 3, iclass 28, count 0 2006.183.07:55:29.92#ibcon#read 3, iclass 28, count 0 2006.183.07:55:29.92#ibcon#about to read 4, iclass 28, count 0 2006.183.07:55:29.92#ibcon#read 4, iclass 28, count 0 2006.183.07:55:29.92#ibcon#about to read 5, iclass 28, count 0 2006.183.07:55:29.92#ibcon#read 5, iclass 28, count 0 2006.183.07:55:29.92#ibcon#about to read 6, iclass 28, count 0 2006.183.07:55:29.92#ibcon#read 6, iclass 28, count 0 2006.183.07:55:29.92#ibcon#end of sib2, iclass 28, count 0 2006.183.07:55:29.92#ibcon#*mode == 0, iclass 28, count 0 2006.183.07:55:29.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.07:55:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:55:29.92#ibcon#*before write, iclass 28, count 0 2006.183.07:55:29.92#ibcon#enter sib2, iclass 28, count 0 2006.183.07:55:29.92#ibcon#flushed, iclass 28, count 0 2006.183.07:55:29.92#ibcon#about to write, iclass 28, count 0 2006.183.07:55:29.92#ibcon#wrote, iclass 28, count 0 2006.183.07:55:29.92#ibcon#about to read 3, iclass 28, count 0 2006.183.07:55:29.96#ibcon#read 3, iclass 28, count 0 2006.183.07:55:29.96#ibcon#about to read 4, iclass 28, count 0 2006.183.07:55:29.96#ibcon#read 4, iclass 28, count 0 2006.183.07:55:29.96#ibcon#about to read 5, iclass 28, count 0 2006.183.07:55:29.96#ibcon#read 5, iclass 28, count 0 2006.183.07:55:29.96#ibcon#about to read 6, iclass 28, count 0 2006.183.07:55:29.96#ibcon#read 6, iclass 28, count 0 2006.183.07:55:29.96#ibcon#end of sib2, iclass 28, count 0 2006.183.07:55:29.96#ibcon#*after write, iclass 28, count 0 2006.183.07:55:29.96#ibcon#*before return 0, iclass 28, count 0 2006.183.07:55:29.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:55:29.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.07:55:29.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.07:55:29.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.07:55:29.96$vc4f8/va=7,6 2006.183.07:55:29.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.07:55:29.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.07:55:29.96#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:29.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:55:30.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:55:30.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:55:30.02#ibcon#enter wrdev, iclass 30, count 2 2006.183.07:55:30.02#ibcon#first serial, iclass 30, count 2 2006.183.07:55:30.02#ibcon#enter sib2, iclass 30, count 2 2006.183.07:55:30.02#ibcon#flushed, iclass 30, count 2 2006.183.07:55:30.02#ibcon#about to write, iclass 30, count 2 2006.183.07:55:30.02#ibcon#wrote, iclass 30, count 2 2006.183.07:55:30.02#ibcon#about to read 3, iclass 30, count 2 2006.183.07:55:30.04#ibcon#read 3, iclass 30, count 2 2006.183.07:55:30.04#ibcon#about to read 4, iclass 30, count 2 2006.183.07:55:30.04#ibcon#read 4, iclass 30, count 2 2006.183.07:55:30.04#ibcon#about to read 5, iclass 30, count 2 2006.183.07:55:30.04#ibcon#read 5, iclass 30, count 2 2006.183.07:55:30.04#ibcon#about to read 6, iclass 30, count 2 2006.183.07:55:30.04#ibcon#read 6, iclass 30, count 2 2006.183.07:55:30.04#ibcon#end of sib2, iclass 30, count 2 2006.183.07:55:30.04#ibcon#*mode == 0, iclass 30, count 2 2006.183.07:55:30.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.07:55:30.04#ibcon#[25=AT07-06\r\n] 2006.183.07:55:30.04#ibcon#*before write, iclass 30, count 2 2006.183.07:55:30.04#ibcon#enter sib2, iclass 30, count 2 2006.183.07:55:30.04#ibcon#flushed, iclass 30, count 2 2006.183.07:55:30.04#ibcon#about to write, iclass 30, count 2 2006.183.07:55:30.04#ibcon#wrote, iclass 30, count 2 2006.183.07:55:30.04#ibcon#about to read 3, iclass 30, count 2 2006.183.07:55:30.07#ibcon#read 3, iclass 30, count 2 2006.183.07:55:30.07#ibcon#about to read 4, iclass 30, count 2 2006.183.07:55:30.07#ibcon#read 4, iclass 30, count 2 2006.183.07:55:30.07#ibcon#about to read 5, iclass 30, count 2 2006.183.07:55:30.07#ibcon#read 5, iclass 30, count 2 2006.183.07:55:30.07#ibcon#about to read 6, iclass 30, count 2 2006.183.07:55:30.07#ibcon#read 6, iclass 30, count 2 2006.183.07:55:30.07#ibcon#end of sib2, iclass 30, count 2 2006.183.07:55:30.07#ibcon#*after write, iclass 30, count 2 2006.183.07:55:30.07#ibcon#*before return 0, iclass 30, count 2 2006.183.07:55:30.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:55:30.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.07:55:30.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.07:55:30.07#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:30.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:55:30.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:55:30.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:55:30.19#ibcon#enter wrdev, iclass 30, count 0 2006.183.07:55:30.19#ibcon#first serial, iclass 30, count 0 2006.183.07:55:30.19#ibcon#enter sib2, iclass 30, count 0 2006.183.07:55:30.19#ibcon#flushed, iclass 30, count 0 2006.183.07:55:30.19#ibcon#about to write, iclass 30, count 0 2006.183.07:55:30.19#ibcon#wrote, iclass 30, count 0 2006.183.07:55:30.19#ibcon#about to read 3, iclass 30, count 0 2006.183.07:55:30.21#ibcon#read 3, iclass 30, count 0 2006.183.07:55:30.21#ibcon#about to read 4, iclass 30, count 0 2006.183.07:55:30.21#ibcon#read 4, iclass 30, count 0 2006.183.07:55:30.21#ibcon#about to read 5, iclass 30, count 0 2006.183.07:55:30.21#ibcon#read 5, iclass 30, count 0 2006.183.07:55:30.21#ibcon#about to read 6, iclass 30, count 0 2006.183.07:55:30.21#ibcon#read 6, iclass 30, count 0 2006.183.07:55:30.21#ibcon#end of sib2, iclass 30, count 0 2006.183.07:55:30.21#ibcon#*mode == 0, iclass 30, count 0 2006.183.07:55:30.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.07:55:30.21#ibcon#[25=USB\r\n] 2006.183.07:55:30.21#ibcon#*before write, iclass 30, count 0 2006.183.07:55:30.21#ibcon#enter sib2, iclass 30, count 0 2006.183.07:55:30.21#ibcon#flushed, iclass 30, count 0 2006.183.07:55:30.21#ibcon#about to write, iclass 30, count 0 2006.183.07:55:30.21#ibcon#wrote, iclass 30, count 0 2006.183.07:55:30.21#ibcon#about to read 3, iclass 30, count 0 2006.183.07:55:30.24#ibcon#read 3, iclass 30, count 0 2006.183.07:55:30.24#ibcon#about to read 4, iclass 30, count 0 2006.183.07:55:30.24#ibcon#read 4, iclass 30, count 0 2006.183.07:55:30.24#ibcon#about to read 5, iclass 30, count 0 2006.183.07:55:30.24#ibcon#read 5, iclass 30, count 0 2006.183.07:55:30.24#ibcon#about to read 6, iclass 30, count 0 2006.183.07:55:30.24#ibcon#read 6, iclass 30, count 0 2006.183.07:55:30.24#ibcon#end of sib2, iclass 30, count 0 2006.183.07:55:30.24#ibcon#*after write, iclass 30, count 0 2006.183.07:55:30.24#ibcon#*before return 0, iclass 30, count 0 2006.183.07:55:30.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:55:30.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.07:55:30.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.07:55:30.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.07:55:30.24$vc4f8/valo=8,852.99 2006.183.07:55:30.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.07:55:30.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.07:55:30.24#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:30.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:55:30.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:55:30.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:55:30.24#ibcon#enter wrdev, iclass 32, count 0 2006.183.07:55:30.24#ibcon#first serial, iclass 32, count 0 2006.183.07:55:30.24#ibcon#enter sib2, iclass 32, count 0 2006.183.07:55:30.24#ibcon#flushed, iclass 32, count 0 2006.183.07:55:30.24#ibcon#about to write, iclass 32, count 0 2006.183.07:55:30.24#ibcon#wrote, iclass 32, count 0 2006.183.07:55:30.24#ibcon#about to read 3, iclass 32, count 0 2006.183.07:55:30.26#ibcon#read 3, iclass 32, count 0 2006.183.07:55:30.26#ibcon#about to read 4, iclass 32, count 0 2006.183.07:55:30.26#ibcon#read 4, iclass 32, count 0 2006.183.07:55:30.26#ibcon#about to read 5, iclass 32, count 0 2006.183.07:55:30.26#ibcon#read 5, iclass 32, count 0 2006.183.07:55:30.26#ibcon#about to read 6, iclass 32, count 0 2006.183.07:55:30.26#ibcon#read 6, iclass 32, count 0 2006.183.07:55:30.26#ibcon#end of sib2, iclass 32, count 0 2006.183.07:55:30.26#ibcon#*mode == 0, iclass 32, count 0 2006.183.07:55:30.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.07:55:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:55:30.26#ibcon#*before write, iclass 32, count 0 2006.183.07:55:30.26#ibcon#enter sib2, iclass 32, count 0 2006.183.07:55:30.26#ibcon#flushed, iclass 32, count 0 2006.183.07:55:30.26#ibcon#about to write, iclass 32, count 0 2006.183.07:55:30.26#ibcon#wrote, iclass 32, count 0 2006.183.07:55:30.26#ibcon#about to read 3, iclass 32, count 0 2006.183.07:55:30.30#ibcon#read 3, iclass 32, count 0 2006.183.07:55:30.30#ibcon#about to read 4, iclass 32, count 0 2006.183.07:55:30.30#ibcon#read 4, iclass 32, count 0 2006.183.07:55:30.30#ibcon#about to read 5, iclass 32, count 0 2006.183.07:55:30.30#ibcon#read 5, iclass 32, count 0 2006.183.07:55:30.30#ibcon#about to read 6, iclass 32, count 0 2006.183.07:55:30.30#ibcon#read 6, iclass 32, count 0 2006.183.07:55:30.30#ibcon#end of sib2, iclass 32, count 0 2006.183.07:55:30.30#ibcon#*after write, iclass 32, count 0 2006.183.07:55:30.30#ibcon#*before return 0, iclass 32, count 0 2006.183.07:55:30.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:55:30.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.07:55:30.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.07:55:30.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.07:55:30.30$vc4f8/va=8,7 2006.183.07:55:30.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.07:55:30.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.07:55:30.30#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:30.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:55:30.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:55:30.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:55:30.36#ibcon#enter wrdev, iclass 34, count 2 2006.183.07:55:30.36#ibcon#first serial, iclass 34, count 2 2006.183.07:55:30.36#ibcon#enter sib2, iclass 34, count 2 2006.183.07:55:30.36#ibcon#flushed, iclass 34, count 2 2006.183.07:55:30.36#ibcon#about to write, iclass 34, count 2 2006.183.07:55:30.36#ibcon#wrote, iclass 34, count 2 2006.183.07:55:30.36#ibcon#about to read 3, iclass 34, count 2 2006.183.07:55:30.38#ibcon#read 3, iclass 34, count 2 2006.183.07:55:30.38#ibcon#about to read 4, iclass 34, count 2 2006.183.07:55:30.38#ibcon#read 4, iclass 34, count 2 2006.183.07:55:30.38#ibcon#about to read 5, iclass 34, count 2 2006.183.07:55:30.38#ibcon#read 5, iclass 34, count 2 2006.183.07:55:30.38#ibcon#about to read 6, iclass 34, count 2 2006.183.07:55:30.38#ibcon#read 6, iclass 34, count 2 2006.183.07:55:30.38#ibcon#end of sib2, iclass 34, count 2 2006.183.07:55:30.38#ibcon#*mode == 0, iclass 34, count 2 2006.183.07:55:30.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.07:55:30.38#ibcon#[25=AT08-07\r\n] 2006.183.07:55:30.38#ibcon#*before write, iclass 34, count 2 2006.183.07:55:30.38#ibcon#enter sib2, iclass 34, count 2 2006.183.07:55:30.38#ibcon#flushed, iclass 34, count 2 2006.183.07:55:30.38#ibcon#about to write, iclass 34, count 2 2006.183.07:55:30.38#ibcon#wrote, iclass 34, count 2 2006.183.07:55:30.38#ibcon#about to read 3, iclass 34, count 2 2006.183.07:55:30.41#ibcon#read 3, iclass 34, count 2 2006.183.07:55:30.41#ibcon#about to read 4, iclass 34, count 2 2006.183.07:55:30.41#ibcon#read 4, iclass 34, count 2 2006.183.07:55:30.41#ibcon#about to read 5, iclass 34, count 2 2006.183.07:55:30.41#ibcon#read 5, iclass 34, count 2 2006.183.07:55:30.41#ibcon#about to read 6, iclass 34, count 2 2006.183.07:55:30.41#ibcon#read 6, iclass 34, count 2 2006.183.07:55:30.41#ibcon#end of sib2, iclass 34, count 2 2006.183.07:55:30.41#ibcon#*after write, iclass 34, count 2 2006.183.07:55:30.41#ibcon#*before return 0, iclass 34, count 2 2006.183.07:55:30.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:55:30.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.07:55:30.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.07:55:30.41#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:30.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:55:30.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:55:30.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:55:30.53#ibcon#enter wrdev, iclass 34, count 0 2006.183.07:55:30.53#ibcon#first serial, iclass 34, count 0 2006.183.07:55:30.53#ibcon#enter sib2, iclass 34, count 0 2006.183.07:55:30.53#ibcon#flushed, iclass 34, count 0 2006.183.07:55:30.53#ibcon#about to write, iclass 34, count 0 2006.183.07:55:30.53#ibcon#wrote, iclass 34, count 0 2006.183.07:55:30.53#ibcon#about to read 3, iclass 34, count 0 2006.183.07:55:30.55#ibcon#read 3, iclass 34, count 0 2006.183.07:55:30.55#ibcon#about to read 4, iclass 34, count 0 2006.183.07:55:30.55#ibcon#read 4, iclass 34, count 0 2006.183.07:55:30.55#ibcon#about to read 5, iclass 34, count 0 2006.183.07:55:30.55#ibcon#read 5, iclass 34, count 0 2006.183.07:55:30.55#ibcon#about to read 6, iclass 34, count 0 2006.183.07:55:30.55#ibcon#read 6, iclass 34, count 0 2006.183.07:55:30.55#ibcon#end of sib2, iclass 34, count 0 2006.183.07:55:30.55#ibcon#*mode == 0, iclass 34, count 0 2006.183.07:55:30.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.07:55:30.55#ibcon#[25=USB\r\n] 2006.183.07:55:30.55#ibcon#*before write, iclass 34, count 0 2006.183.07:55:30.55#ibcon#enter sib2, iclass 34, count 0 2006.183.07:55:30.55#ibcon#flushed, iclass 34, count 0 2006.183.07:55:30.55#ibcon#about to write, iclass 34, count 0 2006.183.07:55:30.55#ibcon#wrote, iclass 34, count 0 2006.183.07:55:30.55#ibcon#about to read 3, iclass 34, count 0 2006.183.07:55:30.58#ibcon#read 3, iclass 34, count 0 2006.183.07:55:30.58#ibcon#about to read 4, iclass 34, count 0 2006.183.07:55:30.58#ibcon#read 4, iclass 34, count 0 2006.183.07:55:30.58#ibcon#about to read 5, iclass 34, count 0 2006.183.07:55:30.58#ibcon#read 5, iclass 34, count 0 2006.183.07:55:30.58#ibcon#about to read 6, iclass 34, count 0 2006.183.07:55:30.58#ibcon#read 6, iclass 34, count 0 2006.183.07:55:30.58#ibcon#end of sib2, iclass 34, count 0 2006.183.07:55:30.58#ibcon#*after write, iclass 34, count 0 2006.183.07:55:30.58#ibcon#*before return 0, iclass 34, count 0 2006.183.07:55:30.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:55:30.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.07:55:30.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.07:55:30.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.07:55:30.58$vc4f8/vblo=1,632.99 2006.183.07:55:30.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.07:55:30.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.07:55:30.58#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:30.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:55:30.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:55:30.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:55:30.58#ibcon#enter wrdev, iclass 36, count 0 2006.183.07:55:30.58#ibcon#first serial, iclass 36, count 0 2006.183.07:55:30.58#ibcon#enter sib2, iclass 36, count 0 2006.183.07:55:30.58#ibcon#flushed, iclass 36, count 0 2006.183.07:55:30.58#ibcon#about to write, iclass 36, count 0 2006.183.07:55:30.58#ibcon#wrote, iclass 36, count 0 2006.183.07:55:30.58#ibcon#about to read 3, iclass 36, count 0 2006.183.07:55:30.60#ibcon#read 3, iclass 36, count 0 2006.183.07:55:30.60#ibcon#about to read 4, iclass 36, count 0 2006.183.07:55:30.60#ibcon#read 4, iclass 36, count 0 2006.183.07:55:30.60#ibcon#about to read 5, iclass 36, count 0 2006.183.07:55:30.60#ibcon#read 5, iclass 36, count 0 2006.183.07:55:30.60#ibcon#about to read 6, iclass 36, count 0 2006.183.07:55:30.60#ibcon#read 6, iclass 36, count 0 2006.183.07:55:30.60#ibcon#end of sib2, iclass 36, count 0 2006.183.07:55:30.60#ibcon#*mode == 0, iclass 36, count 0 2006.183.07:55:30.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.07:55:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:55:30.60#ibcon#*before write, iclass 36, count 0 2006.183.07:55:30.60#ibcon#enter sib2, iclass 36, count 0 2006.183.07:55:30.60#ibcon#flushed, iclass 36, count 0 2006.183.07:55:30.60#ibcon#about to write, iclass 36, count 0 2006.183.07:55:30.60#ibcon#wrote, iclass 36, count 0 2006.183.07:55:30.60#ibcon#about to read 3, iclass 36, count 0 2006.183.07:55:30.64#ibcon#read 3, iclass 36, count 0 2006.183.07:55:30.64#ibcon#about to read 4, iclass 36, count 0 2006.183.07:55:30.64#ibcon#read 4, iclass 36, count 0 2006.183.07:55:30.64#ibcon#about to read 5, iclass 36, count 0 2006.183.07:55:30.64#ibcon#read 5, iclass 36, count 0 2006.183.07:55:30.64#ibcon#about to read 6, iclass 36, count 0 2006.183.07:55:30.64#ibcon#read 6, iclass 36, count 0 2006.183.07:55:30.64#ibcon#end of sib2, iclass 36, count 0 2006.183.07:55:30.64#ibcon#*after write, iclass 36, count 0 2006.183.07:55:30.64#ibcon#*before return 0, iclass 36, count 0 2006.183.07:55:30.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:55:30.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.07:55:30.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.07:55:30.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.07:55:30.64$vc4f8/vb=1,4 2006.183.07:55:30.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.07:55:30.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.07:55:30.64#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:30.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:55:30.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:55:30.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:55:30.64#ibcon#enter wrdev, iclass 38, count 2 2006.183.07:55:30.64#ibcon#first serial, iclass 38, count 2 2006.183.07:55:30.64#ibcon#enter sib2, iclass 38, count 2 2006.183.07:55:30.64#ibcon#flushed, iclass 38, count 2 2006.183.07:55:30.64#ibcon#about to write, iclass 38, count 2 2006.183.07:55:30.64#ibcon#wrote, iclass 38, count 2 2006.183.07:55:30.64#ibcon#about to read 3, iclass 38, count 2 2006.183.07:55:30.66#ibcon#read 3, iclass 38, count 2 2006.183.07:55:30.66#ibcon#about to read 4, iclass 38, count 2 2006.183.07:55:30.66#ibcon#read 4, iclass 38, count 2 2006.183.07:55:30.66#ibcon#about to read 5, iclass 38, count 2 2006.183.07:55:30.66#ibcon#read 5, iclass 38, count 2 2006.183.07:55:30.66#ibcon#about to read 6, iclass 38, count 2 2006.183.07:55:30.66#ibcon#read 6, iclass 38, count 2 2006.183.07:55:30.66#ibcon#end of sib2, iclass 38, count 2 2006.183.07:55:30.66#ibcon#*mode == 0, iclass 38, count 2 2006.183.07:55:30.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.07:55:30.66#ibcon#[27=AT01-04\r\n] 2006.183.07:55:30.66#ibcon#*before write, iclass 38, count 2 2006.183.07:55:30.66#ibcon#enter sib2, iclass 38, count 2 2006.183.07:55:30.66#ibcon#flushed, iclass 38, count 2 2006.183.07:55:30.66#ibcon#about to write, iclass 38, count 2 2006.183.07:55:30.66#ibcon#wrote, iclass 38, count 2 2006.183.07:55:30.66#ibcon#about to read 3, iclass 38, count 2 2006.183.07:55:30.69#ibcon#read 3, iclass 38, count 2 2006.183.07:55:30.69#ibcon#about to read 4, iclass 38, count 2 2006.183.07:55:30.69#ibcon#read 4, iclass 38, count 2 2006.183.07:55:30.69#ibcon#about to read 5, iclass 38, count 2 2006.183.07:55:30.69#ibcon#read 5, iclass 38, count 2 2006.183.07:55:30.69#ibcon#about to read 6, iclass 38, count 2 2006.183.07:55:30.69#ibcon#read 6, iclass 38, count 2 2006.183.07:55:30.69#ibcon#end of sib2, iclass 38, count 2 2006.183.07:55:30.69#ibcon#*after write, iclass 38, count 2 2006.183.07:55:30.69#ibcon#*before return 0, iclass 38, count 2 2006.183.07:55:30.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:55:30.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.07:55:30.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.07:55:30.69#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:30.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:55:30.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:55:30.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:55:30.81#ibcon#enter wrdev, iclass 38, count 0 2006.183.07:55:30.81#ibcon#first serial, iclass 38, count 0 2006.183.07:55:30.81#ibcon#enter sib2, iclass 38, count 0 2006.183.07:55:30.81#ibcon#flushed, iclass 38, count 0 2006.183.07:55:30.81#ibcon#about to write, iclass 38, count 0 2006.183.07:55:30.81#ibcon#wrote, iclass 38, count 0 2006.183.07:55:30.81#ibcon#about to read 3, iclass 38, count 0 2006.183.07:55:30.83#ibcon#read 3, iclass 38, count 0 2006.183.07:55:30.83#ibcon#about to read 4, iclass 38, count 0 2006.183.07:55:30.83#ibcon#read 4, iclass 38, count 0 2006.183.07:55:30.83#ibcon#about to read 5, iclass 38, count 0 2006.183.07:55:30.83#ibcon#read 5, iclass 38, count 0 2006.183.07:55:30.83#ibcon#about to read 6, iclass 38, count 0 2006.183.07:55:30.83#ibcon#read 6, iclass 38, count 0 2006.183.07:55:30.83#ibcon#end of sib2, iclass 38, count 0 2006.183.07:55:30.83#ibcon#*mode == 0, iclass 38, count 0 2006.183.07:55:30.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.07:55:30.83#ibcon#[27=USB\r\n] 2006.183.07:55:30.83#ibcon#*before write, iclass 38, count 0 2006.183.07:55:30.83#ibcon#enter sib2, iclass 38, count 0 2006.183.07:55:30.83#ibcon#flushed, iclass 38, count 0 2006.183.07:55:30.83#ibcon#about to write, iclass 38, count 0 2006.183.07:55:30.83#ibcon#wrote, iclass 38, count 0 2006.183.07:55:30.83#ibcon#about to read 3, iclass 38, count 0 2006.183.07:55:30.86#ibcon#read 3, iclass 38, count 0 2006.183.07:55:30.86#ibcon#about to read 4, iclass 38, count 0 2006.183.07:55:30.86#ibcon#read 4, iclass 38, count 0 2006.183.07:55:30.86#ibcon#about to read 5, iclass 38, count 0 2006.183.07:55:30.86#ibcon#read 5, iclass 38, count 0 2006.183.07:55:30.86#ibcon#about to read 6, iclass 38, count 0 2006.183.07:55:30.86#ibcon#read 6, iclass 38, count 0 2006.183.07:55:30.86#ibcon#end of sib2, iclass 38, count 0 2006.183.07:55:30.86#ibcon#*after write, iclass 38, count 0 2006.183.07:55:30.86#ibcon#*before return 0, iclass 38, count 0 2006.183.07:55:30.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:55:30.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.07:55:30.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.07:55:30.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.07:55:30.86$vc4f8/vblo=2,640.99 2006.183.07:55:30.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.07:55:30.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.07:55:30.86#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:30.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:30.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:30.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:30.86#ibcon#enter wrdev, iclass 40, count 0 2006.183.07:55:30.86#ibcon#first serial, iclass 40, count 0 2006.183.07:55:30.86#ibcon#enter sib2, iclass 40, count 0 2006.183.07:55:30.86#ibcon#flushed, iclass 40, count 0 2006.183.07:55:30.86#ibcon#about to write, iclass 40, count 0 2006.183.07:55:30.86#ibcon#wrote, iclass 40, count 0 2006.183.07:55:30.86#ibcon#about to read 3, iclass 40, count 0 2006.183.07:55:30.88#ibcon#read 3, iclass 40, count 0 2006.183.07:55:30.88#ibcon#about to read 4, iclass 40, count 0 2006.183.07:55:30.88#ibcon#read 4, iclass 40, count 0 2006.183.07:55:30.88#ibcon#about to read 5, iclass 40, count 0 2006.183.07:55:30.88#ibcon#read 5, iclass 40, count 0 2006.183.07:55:30.88#ibcon#about to read 6, iclass 40, count 0 2006.183.07:55:30.88#ibcon#read 6, iclass 40, count 0 2006.183.07:55:30.88#ibcon#end of sib2, iclass 40, count 0 2006.183.07:55:30.88#ibcon#*mode == 0, iclass 40, count 0 2006.183.07:55:30.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.07:55:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:55:30.88#ibcon#*before write, iclass 40, count 0 2006.183.07:55:30.88#ibcon#enter sib2, iclass 40, count 0 2006.183.07:55:30.88#ibcon#flushed, iclass 40, count 0 2006.183.07:55:30.88#ibcon#about to write, iclass 40, count 0 2006.183.07:55:30.88#ibcon#wrote, iclass 40, count 0 2006.183.07:55:30.88#ibcon#about to read 3, iclass 40, count 0 2006.183.07:55:30.92#ibcon#read 3, iclass 40, count 0 2006.183.07:55:30.92#ibcon#about to read 4, iclass 40, count 0 2006.183.07:55:30.92#ibcon#read 4, iclass 40, count 0 2006.183.07:55:30.92#ibcon#about to read 5, iclass 40, count 0 2006.183.07:55:30.92#ibcon#read 5, iclass 40, count 0 2006.183.07:55:30.92#ibcon#about to read 6, iclass 40, count 0 2006.183.07:55:30.92#ibcon#read 6, iclass 40, count 0 2006.183.07:55:30.92#ibcon#end of sib2, iclass 40, count 0 2006.183.07:55:30.92#ibcon#*after write, iclass 40, count 0 2006.183.07:55:30.92#ibcon#*before return 0, iclass 40, count 0 2006.183.07:55:30.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:30.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.07:55:30.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.07:55:30.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.07:55:30.92$vc4f8/vb=2,4 2006.183.07:55:30.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.07:55:30.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.07:55:30.92#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:30.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:30.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:30.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:30.98#ibcon#enter wrdev, iclass 4, count 2 2006.183.07:55:30.98#ibcon#first serial, iclass 4, count 2 2006.183.07:55:30.98#ibcon#enter sib2, iclass 4, count 2 2006.183.07:55:30.98#ibcon#flushed, iclass 4, count 2 2006.183.07:55:30.98#ibcon#about to write, iclass 4, count 2 2006.183.07:55:30.98#ibcon#wrote, iclass 4, count 2 2006.183.07:55:30.98#ibcon#about to read 3, iclass 4, count 2 2006.183.07:55:31.00#ibcon#read 3, iclass 4, count 2 2006.183.07:55:31.00#ibcon#about to read 4, iclass 4, count 2 2006.183.07:55:31.00#ibcon#read 4, iclass 4, count 2 2006.183.07:55:31.00#ibcon#about to read 5, iclass 4, count 2 2006.183.07:55:31.00#ibcon#read 5, iclass 4, count 2 2006.183.07:55:31.00#ibcon#about to read 6, iclass 4, count 2 2006.183.07:55:31.00#ibcon#read 6, iclass 4, count 2 2006.183.07:55:31.00#ibcon#end of sib2, iclass 4, count 2 2006.183.07:55:31.00#ibcon#*mode == 0, iclass 4, count 2 2006.183.07:55:31.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.07:55:31.00#ibcon#[27=AT02-04\r\n] 2006.183.07:55:31.00#ibcon#*before write, iclass 4, count 2 2006.183.07:55:31.00#ibcon#enter sib2, iclass 4, count 2 2006.183.07:55:31.00#ibcon#flushed, iclass 4, count 2 2006.183.07:55:31.00#ibcon#about to write, iclass 4, count 2 2006.183.07:55:31.00#ibcon#wrote, iclass 4, count 2 2006.183.07:55:31.00#ibcon#about to read 3, iclass 4, count 2 2006.183.07:55:31.03#ibcon#read 3, iclass 4, count 2 2006.183.07:55:31.03#ibcon#about to read 4, iclass 4, count 2 2006.183.07:55:31.03#ibcon#read 4, iclass 4, count 2 2006.183.07:55:31.03#ibcon#about to read 5, iclass 4, count 2 2006.183.07:55:31.03#ibcon#read 5, iclass 4, count 2 2006.183.07:55:31.03#ibcon#about to read 6, iclass 4, count 2 2006.183.07:55:31.03#ibcon#read 6, iclass 4, count 2 2006.183.07:55:31.03#ibcon#end of sib2, iclass 4, count 2 2006.183.07:55:31.03#ibcon#*after write, iclass 4, count 2 2006.183.07:55:31.03#ibcon#*before return 0, iclass 4, count 2 2006.183.07:55:31.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:31.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.07:55:31.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.07:55:31.03#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:31.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:31.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:31.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:31.15#ibcon#enter wrdev, iclass 4, count 0 2006.183.07:55:31.15#ibcon#first serial, iclass 4, count 0 2006.183.07:55:31.15#ibcon#enter sib2, iclass 4, count 0 2006.183.07:55:31.15#ibcon#flushed, iclass 4, count 0 2006.183.07:55:31.15#ibcon#about to write, iclass 4, count 0 2006.183.07:55:31.15#ibcon#wrote, iclass 4, count 0 2006.183.07:55:31.15#ibcon#about to read 3, iclass 4, count 0 2006.183.07:55:31.17#ibcon#read 3, iclass 4, count 0 2006.183.07:55:31.17#ibcon#about to read 4, iclass 4, count 0 2006.183.07:55:31.17#ibcon#read 4, iclass 4, count 0 2006.183.07:55:31.17#ibcon#about to read 5, iclass 4, count 0 2006.183.07:55:31.17#ibcon#read 5, iclass 4, count 0 2006.183.07:55:31.17#ibcon#about to read 6, iclass 4, count 0 2006.183.07:55:31.17#ibcon#read 6, iclass 4, count 0 2006.183.07:55:31.17#ibcon#end of sib2, iclass 4, count 0 2006.183.07:55:31.17#ibcon#*mode == 0, iclass 4, count 0 2006.183.07:55:31.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.07:55:31.17#ibcon#[27=USB\r\n] 2006.183.07:55:31.17#ibcon#*before write, iclass 4, count 0 2006.183.07:55:31.17#ibcon#enter sib2, iclass 4, count 0 2006.183.07:55:31.17#ibcon#flushed, iclass 4, count 0 2006.183.07:55:31.17#ibcon#about to write, iclass 4, count 0 2006.183.07:55:31.17#ibcon#wrote, iclass 4, count 0 2006.183.07:55:31.17#ibcon#about to read 3, iclass 4, count 0 2006.183.07:55:31.20#ibcon#read 3, iclass 4, count 0 2006.183.07:55:31.20#ibcon#about to read 4, iclass 4, count 0 2006.183.07:55:31.20#ibcon#read 4, iclass 4, count 0 2006.183.07:55:31.20#ibcon#about to read 5, iclass 4, count 0 2006.183.07:55:31.20#ibcon#read 5, iclass 4, count 0 2006.183.07:55:31.20#ibcon#about to read 6, iclass 4, count 0 2006.183.07:55:31.20#ibcon#read 6, iclass 4, count 0 2006.183.07:55:31.20#ibcon#end of sib2, iclass 4, count 0 2006.183.07:55:31.20#ibcon#*after write, iclass 4, count 0 2006.183.07:55:31.20#ibcon#*before return 0, iclass 4, count 0 2006.183.07:55:31.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:31.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.07:55:31.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.07:55:31.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.07:55:31.20$vc4f8/vblo=3,656.99 2006.183.07:55:31.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.07:55:31.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.07:55:31.20#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:31.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:31.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:31.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:31.20#ibcon#enter wrdev, iclass 6, count 0 2006.183.07:55:31.20#ibcon#first serial, iclass 6, count 0 2006.183.07:55:31.20#ibcon#enter sib2, iclass 6, count 0 2006.183.07:55:31.20#ibcon#flushed, iclass 6, count 0 2006.183.07:55:31.20#ibcon#about to write, iclass 6, count 0 2006.183.07:55:31.20#ibcon#wrote, iclass 6, count 0 2006.183.07:55:31.20#ibcon#about to read 3, iclass 6, count 0 2006.183.07:55:31.22#ibcon#read 3, iclass 6, count 0 2006.183.07:55:31.22#ibcon#about to read 4, iclass 6, count 0 2006.183.07:55:31.22#ibcon#read 4, iclass 6, count 0 2006.183.07:55:31.22#ibcon#about to read 5, iclass 6, count 0 2006.183.07:55:31.22#ibcon#read 5, iclass 6, count 0 2006.183.07:55:31.22#ibcon#about to read 6, iclass 6, count 0 2006.183.07:55:31.22#ibcon#read 6, iclass 6, count 0 2006.183.07:55:31.22#ibcon#end of sib2, iclass 6, count 0 2006.183.07:55:31.22#ibcon#*mode == 0, iclass 6, count 0 2006.183.07:55:31.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.07:55:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:55:31.22#ibcon#*before write, iclass 6, count 0 2006.183.07:55:31.22#ibcon#enter sib2, iclass 6, count 0 2006.183.07:55:31.22#ibcon#flushed, iclass 6, count 0 2006.183.07:55:31.22#ibcon#about to write, iclass 6, count 0 2006.183.07:55:31.22#ibcon#wrote, iclass 6, count 0 2006.183.07:55:31.22#ibcon#about to read 3, iclass 6, count 0 2006.183.07:55:31.26#ibcon#read 3, iclass 6, count 0 2006.183.07:55:31.26#ibcon#about to read 4, iclass 6, count 0 2006.183.07:55:31.26#ibcon#read 4, iclass 6, count 0 2006.183.07:55:31.26#ibcon#about to read 5, iclass 6, count 0 2006.183.07:55:31.26#ibcon#read 5, iclass 6, count 0 2006.183.07:55:31.26#ibcon#about to read 6, iclass 6, count 0 2006.183.07:55:31.26#ibcon#read 6, iclass 6, count 0 2006.183.07:55:31.26#ibcon#end of sib2, iclass 6, count 0 2006.183.07:55:31.26#ibcon#*after write, iclass 6, count 0 2006.183.07:55:31.26#ibcon#*before return 0, iclass 6, count 0 2006.183.07:55:31.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:31.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.07:55:31.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.07:55:31.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.07:55:31.26$vc4f8/vb=3,4 2006.183.07:55:31.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.07:55:31.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.07:55:31.26#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:31.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:31.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:31.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:31.32#ibcon#enter wrdev, iclass 10, count 2 2006.183.07:55:31.32#ibcon#first serial, iclass 10, count 2 2006.183.07:55:31.32#ibcon#enter sib2, iclass 10, count 2 2006.183.07:55:31.32#ibcon#flushed, iclass 10, count 2 2006.183.07:55:31.32#ibcon#about to write, iclass 10, count 2 2006.183.07:55:31.32#ibcon#wrote, iclass 10, count 2 2006.183.07:55:31.32#ibcon#about to read 3, iclass 10, count 2 2006.183.07:55:31.34#ibcon#read 3, iclass 10, count 2 2006.183.07:55:31.34#ibcon#about to read 4, iclass 10, count 2 2006.183.07:55:31.34#ibcon#read 4, iclass 10, count 2 2006.183.07:55:31.34#ibcon#about to read 5, iclass 10, count 2 2006.183.07:55:31.34#ibcon#read 5, iclass 10, count 2 2006.183.07:55:31.34#ibcon#about to read 6, iclass 10, count 2 2006.183.07:55:31.34#ibcon#read 6, iclass 10, count 2 2006.183.07:55:31.34#ibcon#end of sib2, iclass 10, count 2 2006.183.07:55:31.34#ibcon#*mode == 0, iclass 10, count 2 2006.183.07:55:31.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.07:55:31.34#ibcon#[27=AT03-04\r\n] 2006.183.07:55:31.34#ibcon#*before write, iclass 10, count 2 2006.183.07:55:31.34#ibcon#enter sib2, iclass 10, count 2 2006.183.07:55:31.34#ibcon#flushed, iclass 10, count 2 2006.183.07:55:31.34#ibcon#about to write, iclass 10, count 2 2006.183.07:55:31.34#ibcon#wrote, iclass 10, count 2 2006.183.07:55:31.34#ibcon#about to read 3, iclass 10, count 2 2006.183.07:55:31.37#ibcon#read 3, iclass 10, count 2 2006.183.07:55:31.37#ibcon#about to read 4, iclass 10, count 2 2006.183.07:55:31.37#ibcon#read 4, iclass 10, count 2 2006.183.07:55:31.37#ibcon#about to read 5, iclass 10, count 2 2006.183.07:55:31.37#ibcon#read 5, iclass 10, count 2 2006.183.07:55:31.37#ibcon#about to read 6, iclass 10, count 2 2006.183.07:55:31.37#ibcon#read 6, iclass 10, count 2 2006.183.07:55:31.37#ibcon#end of sib2, iclass 10, count 2 2006.183.07:55:31.37#ibcon#*after write, iclass 10, count 2 2006.183.07:55:31.37#ibcon#*before return 0, iclass 10, count 2 2006.183.07:55:31.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:31.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.07:55:31.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.07:55:31.37#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:31.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:31.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:31.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:31.49#ibcon#enter wrdev, iclass 10, count 0 2006.183.07:55:31.49#ibcon#first serial, iclass 10, count 0 2006.183.07:55:31.49#ibcon#enter sib2, iclass 10, count 0 2006.183.07:55:31.49#ibcon#flushed, iclass 10, count 0 2006.183.07:55:31.49#ibcon#about to write, iclass 10, count 0 2006.183.07:55:31.49#ibcon#wrote, iclass 10, count 0 2006.183.07:55:31.49#ibcon#about to read 3, iclass 10, count 0 2006.183.07:55:31.51#ibcon#read 3, iclass 10, count 0 2006.183.07:55:31.51#ibcon#about to read 4, iclass 10, count 0 2006.183.07:55:31.51#ibcon#read 4, iclass 10, count 0 2006.183.07:55:31.51#ibcon#about to read 5, iclass 10, count 0 2006.183.07:55:31.51#ibcon#read 5, iclass 10, count 0 2006.183.07:55:31.51#ibcon#about to read 6, iclass 10, count 0 2006.183.07:55:31.51#ibcon#read 6, iclass 10, count 0 2006.183.07:55:31.51#ibcon#end of sib2, iclass 10, count 0 2006.183.07:55:31.51#ibcon#*mode == 0, iclass 10, count 0 2006.183.07:55:31.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.07:55:31.51#ibcon#[27=USB\r\n] 2006.183.07:55:31.51#ibcon#*before write, iclass 10, count 0 2006.183.07:55:31.51#ibcon#enter sib2, iclass 10, count 0 2006.183.07:55:31.51#ibcon#flushed, iclass 10, count 0 2006.183.07:55:31.51#ibcon#about to write, iclass 10, count 0 2006.183.07:55:31.51#ibcon#wrote, iclass 10, count 0 2006.183.07:55:31.51#ibcon#about to read 3, iclass 10, count 0 2006.183.07:55:31.54#ibcon#read 3, iclass 10, count 0 2006.183.07:55:31.54#ibcon#about to read 4, iclass 10, count 0 2006.183.07:55:31.54#ibcon#read 4, iclass 10, count 0 2006.183.07:55:31.54#ibcon#about to read 5, iclass 10, count 0 2006.183.07:55:31.54#ibcon#read 5, iclass 10, count 0 2006.183.07:55:31.54#ibcon#about to read 6, iclass 10, count 0 2006.183.07:55:31.54#ibcon#read 6, iclass 10, count 0 2006.183.07:55:31.54#ibcon#end of sib2, iclass 10, count 0 2006.183.07:55:31.54#ibcon#*after write, iclass 10, count 0 2006.183.07:55:31.54#ibcon#*before return 0, iclass 10, count 0 2006.183.07:55:31.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:31.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.07:55:31.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.07:55:31.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.07:55:31.54$vc4f8/vblo=4,712.99 2006.183.07:55:31.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.07:55:31.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.07:55:31.54#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:31.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:31.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:31.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:31.54#ibcon#enter wrdev, iclass 12, count 0 2006.183.07:55:31.54#ibcon#first serial, iclass 12, count 0 2006.183.07:55:31.54#ibcon#enter sib2, iclass 12, count 0 2006.183.07:55:31.54#ibcon#flushed, iclass 12, count 0 2006.183.07:55:31.54#ibcon#about to write, iclass 12, count 0 2006.183.07:55:31.54#ibcon#wrote, iclass 12, count 0 2006.183.07:55:31.54#ibcon#about to read 3, iclass 12, count 0 2006.183.07:55:31.56#ibcon#read 3, iclass 12, count 0 2006.183.07:55:31.56#ibcon#about to read 4, iclass 12, count 0 2006.183.07:55:31.56#ibcon#read 4, iclass 12, count 0 2006.183.07:55:31.56#ibcon#about to read 5, iclass 12, count 0 2006.183.07:55:31.56#ibcon#read 5, iclass 12, count 0 2006.183.07:55:31.56#ibcon#about to read 6, iclass 12, count 0 2006.183.07:55:31.56#ibcon#read 6, iclass 12, count 0 2006.183.07:55:31.56#ibcon#end of sib2, iclass 12, count 0 2006.183.07:55:31.56#ibcon#*mode == 0, iclass 12, count 0 2006.183.07:55:31.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.07:55:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:55:31.56#ibcon#*before write, iclass 12, count 0 2006.183.07:55:31.56#ibcon#enter sib2, iclass 12, count 0 2006.183.07:55:31.56#ibcon#flushed, iclass 12, count 0 2006.183.07:55:31.56#ibcon#about to write, iclass 12, count 0 2006.183.07:55:31.56#ibcon#wrote, iclass 12, count 0 2006.183.07:55:31.56#ibcon#about to read 3, iclass 12, count 0 2006.183.07:55:31.60#ibcon#read 3, iclass 12, count 0 2006.183.07:55:31.60#ibcon#about to read 4, iclass 12, count 0 2006.183.07:55:31.60#ibcon#read 4, iclass 12, count 0 2006.183.07:55:31.60#ibcon#about to read 5, iclass 12, count 0 2006.183.07:55:31.60#ibcon#read 5, iclass 12, count 0 2006.183.07:55:31.60#ibcon#about to read 6, iclass 12, count 0 2006.183.07:55:31.60#ibcon#read 6, iclass 12, count 0 2006.183.07:55:31.60#ibcon#end of sib2, iclass 12, count 0 2006.183.07:55:31.60#ibcon#*after write, iclass 12, count 0 2006.183.07:55:31.60#ibcon#*before return 0, iclass 12, count 0 2006.183.07:55:31.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:31.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.07:55:31.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.07:55:31.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.07:55:31.60$vc4f8/vb=4,4 2006.183.07:55:31.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.07:55:31.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.07:55:31.60#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:31.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:31.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:31.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:31.66#ibcon#enter wrdev, iclass 14, count 2 2006.183.07:55:31.66#ibcon#first serial, iclass 14, count 2 2006.183.07:55:31.66#ibcon#enter sib2, iclass 14, count 2 2006.183.07:55:31.66#ibcon#flushed, iclass 14, count 2 2006.183.07:55:31.66#ibcon#about to write, iclass 14, count 2 2006.183.07:55:31.66#ibcon#wrote, iclass 14, count 2 2006.183.07:55:31.66#ibcon#about to read 3, iclass 14, count 2 2006.183.07:55:31.68#ibcon#read 3, iclass 14, count 2 2006.183.07:55:31.68#ibcon#about to read 4, iclass 14, count 2 2006.183.07:55:31.68#ibcon#read 4, iclass 14, count 2 2006.183.07:55:31.68#ibcon#about to read 5, iclass 14, count 2 2006.183.07:55:31.68#ibcon#read 5, iclass 14, count 2 2006.183.07:55:31.68#ibcon#about to read 6, iclass 14, count 2 2006.183.07:55:31.68#ibcon#read 6, iclass 14, count 2 2006.183.07:55:31.68#ibcon#end of sib2, iclass 14, count 2 2006.183.07:55:31.68#ibcon#*mode == 0, iclass 14, count 2 2006.183.07:55:31.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.07:55:31.68#ibcon#[27=AT04-04\r\n] 2006.183.07:55:31.68#ibcon#*before write, iclass 14, count 2 2006.183.07:55:31.68#ibcon#enter sib2, iclass 14, count 2 2006.183.07:55:31.68#ibcon#flushed, iclass 14, count 2 2006.183.07:55:31.68#ibcon#about to write, iclass 14, count 2 2006.183.07:55:31.68#ibcon#wrote, iclass 14, count 2 2006.183.07:55:31.68#ibcon#about to read 3, iclass 14, count 2 2006.183.07:55:31.71#ibcon#read 3, iclass 14, count 2 2006.183.07:55:31.71#ibcon#about to read 4, iclass 14, count 2 2006.183.07:55:31.71#ibcon#read 4, iclass 14, count 2 2006.183.07:55:31.71#ibcon#about to read 5, iclass 14, count 2 2006.183.07:55:31.71#ibcon#read 5, iclass 14, count 2 2006.183.07:55:31.71#ibcon#about to read 6, iclass 14, count 2 2006.183.07:55:31.71#ibcon#read 6, iclass 14, count 2 2006.183.07:55:31.71#ibcon#end of sib2, iclass 14, count 2 2006.183.07:55:31.71#ibcon#*after write, iclass 14, count 2 2006.183.07:55:31.71#ibcon#*before return 0, iclass 14, count 2 2006.183.07:55:31.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:31.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.07:55:31.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.07:55:31.71#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:31.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:31.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:31.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:31.83#ibcon#enter wrdev, iclass 14, count 0 2006.183.07:55:31.83#ibcon#first serial, iclass 14, count 0 2006.183.07:55:31.83#ibcon#enter sib2, iclass 14, count 0 2006.183.07:55:31.83#ibcon#flushed, iclass 14, count 0 2006.183.07:55:31.83#ibcon#about to write, iclass 14, count 0 2006.183.07:55:31.83#ibcon#wrote, iclass 14, count 0 2006.183.07:55:31.83#ibcon#about to read 3, iclass 14, count 0 2006.183.07:55:31.85#ibcon#read 3, iclass 14, count 0 2006.183.07:55:31.85#ibcon#about to read 4, iclass 14, count 0 2006.183.07:55:31.85#ibcon#read 4, iclass 14, count 0 2006.183.07:55:31.85#ibcon#about to read 5, iclass 14, count 0 2006.183.07:55:31.85#ibcon#read 5, iclass 14, count 0 2006.183.07:55:31.85#ibcon#about to read 6, iclass 14, count 0 2006.183.07:55:31.85#ibcon#read 6, iclass 14, count 0 2006.183.07:55:31.85#ibcon#end of sib2, iclass 14, count 0 2006.183.07:55:31.85#ibcon#*mode == 0, iclass 14, count 0 2006.183.07:55:31.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.07:55:31.85#ibcon#[27=USB\r\n] 2006.183.07:55:31.85#ibcon#*before write, iclass 14, count 0 2006.183.07:55:31.85#ibcon#enter sib2, iclass 14, count 0 2006.183.07:55:31.85#ibcon#flushed, iclass 14, count 0 2006.183.07:55:31.85#ibcon#about to write, iclass 14, count 0 2006.183.07:55:31.85#ibcon#wrote, iclass 14, count 0 2006.183.07:55:31.85#ibcon#about to read 3, iclass 14, count 0 2006.183.07:55:31.88#ibcon#read 3, iclass 14, count 0 2006.183.07:55:31.88#ibcon#about to read 4, iclass 14, count 0 2006.183.07:55:31.88#ibcon#read 4, iclass 14, count 0 2006.183.07:55:31.88#ibcon#about to read 5, iclass 14, count 0 2006.183.07:55:31.88#ibcon#read 5, iclass 14, count 0 2006.183.07:55:31.88#ibcon#about to read 6, iclass 14, count 0 2006.183.07:55:31.88#ibcon#read 6, iclass 14, count 0 2006.183.07:55:31.88#ibcon#end of sib2, iclass 14, count 0 2006.183.07:55:31.88#ibcon#*after write, iclass 14, count 0 2006.183.07:55:31.88#ibcon#*before return 0, iclass 14, count 0 2006.183.07:55:31.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:31.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.07:55:31.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.07:55:31.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.07:55:31.88$vc4f8/vblo=5,744.99 2006.183.07:55:31.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.07:55:31.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.07:55:31.88#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:31.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:31.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:31.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:31.88#ibcon#enter wrdev, iclass 16, count 0 2006.183.07:55:31.88#ibcon#first serial, iclass 16, count 0 2006.183.07:55:31.88#ibcon#enter sib2, iclass 16, count 0 2006.183.07:55:31.88#ibcon#flushed, iclass 16, count 0 2006.183.07:55:31.88#ibcon#about to write, iclass 16, count 0 2006.183.07:55:31.88#ibcon#wrote, iclass 16, count 0 2006.183.07:55:31.88#ibcon#about to read 3, iclass 16, count 0 2006.183.07:55:31.90#ibcon#read 3, iclass 16, count 0 2006.183.07:55:31.90#ibcon#about to read 4, iclass 16, count 0 2006.183.07:55:31.90#ibcon#read 4, iclass 16, count 0 2006.183.07:55:31.90#ibcon#about to read 5, iclass 16, count 0 2006.183.07:55:31.90#ibcon#read 5, iclass 16, count 0 2006.183.07:55:31.90#ibcon#about to read 6, iclass 16, count 0 2006.183.07:55:31.90#ibcon#read 6, iclass 16, count 0 2006.183.07:55:31.90#ibcon#end of sib2, iclass 16, count 0 2006.183.07:55:31.90#ibcon#*mode == 0, iclass 16, count 0 2006.183.07:55:31.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.07:55:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:55:31.90#ibcon#*before write, iclass 16, count 0 2006.183.07:55:31.90#ibcon#enter sib2, iclass 16, count 0 2006.183.07:55:31.90#ibcon#flushed, iclass 16, count 0 2006.183.07:55:31.90#ibcon#about to write, iclass 16, count 0 2006.183.07:55:31.90#ibcon#wrote, iclass 16, count 0 2006.183.07:55:31.90#ibcon#about to read 3, iclass 16, count 0 2006.183.07:55:31.94#ibcon#read 3, iclass 16, count 0 2006.183.07:55:31.94#ibcon#about to read 4, iclass 16, count 0 2006.183.07:55:31.94#ibcon#read 4, iclass 16, count 0 2006.183.07:55:31.94#ibcon#about to read 5, iclass 16, count 0 2006.183.07:55:31.94#ibcon#read 5, iclass 16, count 0 2006.183.07:55:31.94#ibcon#about to read 6, iclass 16, count 0 2006.183.07:55:31.94#ibcon#read 6, iclass 16, count 0 2006.183.07:55:31.94#ibcon#end of sib2, iclass 16, count 0 2006.183.07:55:31.94#ibcon#*after write, iclass 16, count 0 2006.183.07:55:31.94#ibcon#*before return 0, iclass 16, count 0 2006.183.07:55:31.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:31.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.07:55:31.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.07:55:31.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.07:55:31.94$vc4f8/vb=5,4 2006.183.07:55:31.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.07:55:31.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.07:55:31.94#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:31.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:32.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:32.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:32.00#ibcon#enter wrdev, iclass 18, count 2 2006.183.07:55:32.00#ibcon#first serial, iclass 18, count 2 2006.183.07:55:32.00#ibcon#enter sib2, iclass 18, count 2 2006.183.07:55:32.00#ibcon#flushed, iclass 18, count 2 2006.183.07:55:32.00#ibcon#about to write, iclass 18, count 2 2006.183.07:55:32.00#ibcon#wrote, iclass 18, count 2 2006.183.07:55:32.00#ibcon#about to read 3, iclass 18, count 2 2006.183.07:55:32.02#ibcon#read 3, iclass 18, count 2 2006.183.07:55:32.02#ibcon#about to read 4, iclass 18, count 2 2006.183.07:55:32.02#ibcon#read 4, iclass 18, count 2 2006.183.07:55:32.02#ibcon#about to read 5, iclass 18, count 2 2006.183.07:55:32.02#ibcon#read 5, iclass 18, count 2 2006.183.07:55:32.02#ibcon#about to read 6, iclass 18, count 2 2006.183.07:55:32.02#ibcon#read 6, iclass 18, count 2 2006.183.07:55:32.02#ibcon#end of sib2, iclass 18, count 2 2006.183.07:55:32.02#ibcon#*mode == 0, iclass 18, count 2 2006.183.07:55:32.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.07:55:32.02#ibcon#[27=AT05-04\r\n] 2006.183.07:55:32.02#ibcon#*before write, iclass 18, count 2 2006.183.07:55:32.02#ibcon#enter sib2, iclass 18, count 2 2006.183.07:55:32.02#ibcon#flushed, iclass 18, count 2 2006.183.07:55:32.02#ibcon#about to write, iclass 18, count 2 2006.183.07:55:32.02#ibcon#wrote, iclass 18, count 2 2006.183.07:55:32.02#ibcon#about to read 3, iclass 18, count 2 2006.183.07:55:32.05#ibcon#read 3, iclass 18, count 2 2006.183.07:55:32.05#ibcon#about to read 4, iclass 18, count 2 2006.183.07:55:32.05#ibcon#read 4, iclass 18, count 2 2006.183.07:55:32.05#ibcon#about to read 5, iclass 18, count 2 2006.183.07:55:32.05#ibcon#read 5, iclass 18, count 2 2006.183.07:55:32.05#ibcon#about to read 6, iclass 18, count 2 2006.183.07:55:32.05#ibcon#read 6, iclass 18, count 2 2006.183.07:55:32.05#ibcon#end of sib2, iclass 18, count 2 2006.183.07:55:32.05#ibcon#*after write, iclass 18, count 2 2006.183.07:55:32.05#ibcon#*before return 0, iclass 18, count 2 2006.183.07:55:32.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:32.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.07:55:32.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.07:55:32.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:32.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:32.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:32.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:32.17#ibcon#enter wrdev, iclass 18, count 0 2006.183.07:55:32.17#ibcon#first serial, iclass 18, count 0 2006.183.07:55:32.17#ibcon#enter sib2, iclass 18, count 0 2006.183.07:55:32.17#ibcon#flushed, iclass 18, count 0 2006.183.07:55:32.17#ibcon#about to write, iclass 18, count 0 2006.183.07:55:32.17#ibcon#wrote, iclass 18, count 0 2006.183.07:55:32.17#ibcon#about to read 3, iclass 18, count 0 2006.183.07:55:32.20#ibcon#read 3, iclass 18, count 0 2006.183.07:55:32.20#ibcon#about to read 4, iclass 18, count 0 2006.183.07:55:32.20#ibcon#read 4, iclass 18, count 0 2006.183.07:55:32.20#ibcon#about to read 5, iclass 18, count 0 2006.183.07:55:32.20#ibcon#read 5, iclass 18, count 0 2006.183.07:55:32.20#ibcon#about to read 6, iclass 18, count 0 2006.183.07:55:32.20#ibcon#read 6, iclass 18, count 0 2006.183.07:55:32.20#ibcon#end of sib2, iclass 18, count 0 2006.183.07:55:32.20#ibcon#*mode == 0, iclass 18, count 0 2006.183.07:55:32.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.07:55:32.20#ibcon#[27=USB\r\n] 2006.183.07:55:32.20#ibcon#*before write, iclass 18, count 0 2006.183.07:55:32.20#ibcon#enter sib2, iclass 18, count 0 2006.183.07:55:32.20#ibcon#flushed, iclass 18, count 0 2006.183.07:55:32.20#ibcon#about to write, iclass 18, count 0 2006.183.07:55:32.20#ibcon#wrote, iclass 18, count 0 2006.183.07:55:32.20#ibcon#about to read 3, iclass 18, count 0 2006.183.07:55:32.23#ibcon#read 3, iclass 18, count 0 2006.183.07:55:32.23#ibcon#about to read 4, iclass 18, count 0 2006.183.07:55:32.23#ibcon#read 4, iclass 18, count 0 2006.183.07:55:32.23#ibcon#about to read 5, iclass 18, count 0 2006.183.07:55:32.23#ibcon#read 5, iclass 18, count 0 2006.183.07:55:32.23#ibcon#about to read 6, iclass 18, count 0 2006.183.07:55:32.23#ibcon#read 6, iclass 18, count 0 2006.183.07:55:32.23#ibcon#end of sib2, iclass 18, count 0 2006.183.07:55:32.23#ibcon#*after write, iclass 18, count 0 2006.183.07:55:32.23#ibcon#*before return 0, iclass 18, count 0 2006.183.07:55:32.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:32.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.07:55:32.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.07:55:32.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.07:55:32.23$vc4f8/vblo=6,752.99 2006.183.07:55:32.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.07:55:32.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.07:55:32.23#ibcon#ireg 17 cls_cnt 0 2006.183.07:55:32.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:32.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:32.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:32.23#ibcon#enter wrdev, iclass 20, count 0 2006.183.07:55:32.23#ibcon#first serial, iclass 20, count 0 2006.183.07:55:32.23#ibcon#enter sib2, iclass 20, count 0 2006.183.07:55:32.23#ibcon#flushed, iclass 20, count 0 2006.183.07:55:32.23#ibcon#about to write, iclass 20, count 0 2006.183.07:55:32.23#ibcon#wrote, iclass 20, count 0 2006.183.07:55:32.23#ibcon#about to read 3, iclass 20, count 0 2006.183.07:55:32.25#ibcon#read 3, iclass 20, count 0 2006.183.07:55:32.25#ibcon#about to read 4, iclass 20, count 0 2006.183.07:55:32.25#ibcon#read 4, iclass 20, count 0 2006.183.07:55:32.25#ibcon#about to read 5, iclass 20, count 0 2006.183.07:55:32.25#ibcon#read 5, iclass 20, count 0 2006.183.07:55:32.25#ibcon#about to read 6, iclass 20, count 0 2006.183.07:55:32.25#ibcon#read 6, iclass 20, count 0 2006.183.07:55:32.25#ibcon#end of sib2, iclass 20, count 0 2006.183.07:55:32.25#ibcon#*mode == 0, iclass 20, count 0 2006.183.07:55:32.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.07:55:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:55:32.25#ibcon#*before write, iclass 20, count 0 2006.183.07:55:32.25#ibcon#enter sib2, iclass 20, count 0 2006.183.07:55:32.25#ibcon#flushed, iclass 20, count 0 2006.183.07:55:32.25#ibcon#about to write, iclass 20, count 0 2006.183.07:55:32.25#ibcon#wrote, iclass 20, count 0 2006.183.07:55:32.25#ibcon#about to read 3, iclass 20, count 0 2006.183.07:55:32.29#ibcon#read 3, iclass 20, count 0 2006.183.07:55:32.29#ibcon#about to read 4, iclass 20, count 0 2006.183.07:55:32.29#ibcon#read 4, iclass 20, count 0 2006.183.07:55:32.29#ibcon#about to read 5, iclass 20, count 0 2006.183.07:55:32.29#ibcon#read 5, iclass 20, count 0 2006.183.07:55:32.29#ibcon#about to read 6, iclass 20, count 0 2006.183.07:55:32.29#ibcon#read 6, iclass 20, count 0 2006.183.07:55:32.29#ibcon#end of sib2, iclass 20, count 0 2006.183.07:55:32.29#ibcon#*after write, iclass 20, count 0 2006.183.07:55:32.29#ibcon#*before return 0, iclass 20, count 0 2006.183.07:55:32.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:32.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.07:55:32.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.07:55:32.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.07:55:32.29$vc4f8/vb=6,4 2006.183.07:55:32.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.07:55:32.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.07:55:32.29#ibcon#ireg 11 cls_cnt 2 2006.183.07:55:32.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:32.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:32.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:32.35#ibcon#enter wrdev, iclass 22, count 2 2006.183.07:55:32.35#ibcon#first serial, iclass 22, count 2 2006.183.07:55:32.35#ibcon#enter sib2, iclass 22, count 2 2006.183.07:55:32.35#ibcon#flushed, iclass 22, count 2 2006.183.07:55:32.35#ibcon#about to write, iclass 22, count 2 2006.183.07:55:32.35#ibcon#wrote, iclass 22, count 2 2006.183.07:55:32.35#ibcon#about to read 3, iclass 22, count 2 2006.183.07:55:32.37#ibcon#read 3, iclass 22, count 2 2006.183.07:55:32.37#ibcon#about to read 4, iclass 22, count 2 2006.183.07:55:32.37#ibcon#read 4, iclass 22, count 2 2006.183.07:55:32.37#ibcon#about to read 5, iclass 22, count 2 2006.183.07:55:32.37#ibcon#read 5, iclass 22, count 2 2006.183.07:55:32.37#ibcon#about to read 6, iclass 22, count 2 2006.183.07:55:32.37#ibcon#read 6, iclass 22, count 2 2006.183.07:55:32.37#ibcon#end of sib2, iclass 22, count 2 2006.183.07:55:32.37#ibcon#*mode == 0, iclass 22, count 2 2006.183.07:55:32.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.07:55:32.37#ibcon#[27=AT06-04\r\n] 2006.183.07:55:32.37#ibcon#*before write, iclass 22, count 2 2006.183.07:55:32.37#ibcon#enter sib2, iclass 22, count 2 2006.183.07:55:32.37#ibcon#flushed, iclass 22, count 2 2006.183.07:55:32.37#ibcon#about to write, iclass 22, count 2 2006.183.07:55:32.37#ibcon#wrote, iclass 22, count 2 2006.183.07:55:32.37#ibcon#about to read 3, iclass 22, count 2 2006.183.07:55:32.40#ibcon#read 3, iclass 22, count 2 2006.183.07:55:32.40#ibcon#about to read 4, iclass 22, count 2 2006.183.07:55:32.40#ibcon#read 4, iclass 22, count 2 2006.183.07:55:32.40#ibcon#about to read 5, iclass 22, count 2 2006.183.07:55:32.40#ibcon#read 5, iclass 22, count 2 2006.183.07:55:32.40#ibcon#about to read 6, iclass 22, count 2 2006.183.07:55:32.40#ibcon#read 6, iclass 22, count 2 2006.183.07:55:32.40#ibcon#end of sib2, iclass 22, count 2 2006.183.07:55:32.40#ibcon#*after write, iclass 22, count 2 2006.183.07:55:32.40#ibcon#*before return 0, iclass 22, count 2 2006.183.07:55:32.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:32.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.07:55:32.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.07:55:32.40#ibcon#ireg 7 cls_cnt 0 2006.183.07:55:32.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:32.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:32.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:32.52#ibcon#enter wrdev, iclass 22, count 0 2006.183.07:55:32.52#ibcon#first serial, iclass 22, count 0 2006.183.07:55:32.52#ibcon#enter sib2, iclass 22, count 0 2006.183.07:55:32.52#ibcon#flushed, iclass 22, count 0 2006.183.07:55:32.52#ibcon#about to write, iclass 22, count 0 2006.183.07:55:32.52#ibcon#wrote, iclass 22, count 0 2006.183.07:55:32.52#ibcon#about to read 3, iclass 22, count 0 2006.183.07:55:32.54#ibcon#read 3, iclass 22, count 0 2006.183.07:55:32.54#ibcon#about to read 4, iclass 22, count 0 2006.183.07:55:32.54#ibcon#read 4, iclass 22, count 0 2006.183.07:55:32.54#ibcon#about to read 5, iclass 22, count 0 2006.183.07:55:32.54#ibcon#read 5, iclass 22, count 0 2006.183.07:55:32.54#ibcon#about to read 6, iclass 22, count 0 2006.183.07:55:32.54#ibcon#read 6, iclass 22, count 0 2006.183.07:55:32.54#ibcon#end of sib2, iclass 22, count 0 2006.183.07:55:32.54#ibcon#*mode == 0, iclass 22, count 0 2006.183.07:55:32.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.07:55:32.54#ibcon#[27=USB\r\n] 2006.183.07:55:32.54#ibcon#*before write, iclass 22, count 0 2006.183.07:55:32.54#ibcon#enter sib2, iclass 22, count 0 2006.183.07:55:32.54#ibcon#flushed, iclass 22, count 0 2006.183.07:55:32.54#ibcon#about to write, iclass 22, count 0 2006.183.07:55:32.54#ibcon#wrote, iclass 22, count 0 2006.183.07:55:32.54#ibcon#about to read 3, iclass 22, count 0 2006.183.07:55:32.57#ibcon#read 3, iclass 22, count 0 2006.183.07:55:32.57#ibcon#about to read 4, iclass 22, count 0 2006.183.07:55:32.57#ibcon#read 4, iclass 22, count 0 2006.183.07:55:32.57#ibcon#about to read 5, iclass 22, count 0 2006.183.07:55:32.57#ibcon#read 5, iclass 22, count 0 2006.183.07:55:32.57#ibcon#about to read 6, iclass 22, count 0 2006.183.07:55:32.57#ibcon#read 6, iclass 22, count 0 2006.183.07:55:32.57#ibcon#end of sib2, iclass 22, count 0 2006.183.07:55:32.57#ibcon#*after write, iclass 22, count 0 2006.183.07:55:32.57#ibcon#*before return 0, iclass 22, count 0 2006.183.07:55:32.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:32.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.07:55:32.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.07:55:32.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.07:55:32.57$vc4f8/vabw=wide 2006.183.07:55:32.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.07:55:32.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.07:55:32.57#ibcon#ireg 8 cls_cnt 0 2006.183.07:55:32.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:32.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:32.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:32.57#ibcon#enter wrdev, iclass 24, count 0 2006.183.07:55:32.57#ibcon#first serial, iclass 24, count 0 2006.183.07:55:32.57#ibcon#enter sib2, iclass 24, count 0 2006.183.07:55:32.57#ibcon#flushed, iclass 24, count 0 2006.183.07:55:32.57#ibcon#about to write, iclass 24, count 0 2006.183.07:55:32.57#ibcon#wrote, iclass 24, count 0 2006.183.07:55:32.57#ibcon#about to read 3, iclass 24, count 0 2006.183.07:55:32.59#ibcon#read 3, iclass 24, count 0 2006.183.07:55:32.59#ibcon#about to read 4, iclass 24, count 0 2006.183.07:55:32.59#ibcon#read 4, iclass 24, count 0 2006.183.07:55:32.59#ibcon#about to read 5, iclass 24, count 0 2006.183.07:55:32.59#ibcon#read 5, iclass 24, count 0 2006.183.07:55:32.59#ibcon#about to read 6, iclass 24, count 0 2006.183.07:55:32.59#ibcon#read 6, iclass 24, count 0 2006.183.07:55:32.59#ibcon#end of sib2, iclass 24, count 0 2006.183.07:55:32.59#ibcon#*mode == 0, iclass 24, count 0 2006.183.07:55:32.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.07:55:32.59#ibcon#[25=BW32\r\n] 2006.183.07:55:32.59#ibcon#*before write, iclass 24, count 0 2006.183.07:55:32.59#ibcon#enter sib2, iclass 24, count 0 2006.183.07:55:32.59#ibcon#flushed, iclass 24, count 0 2006.183.07:55:32.59#ibcon#about to write, iclass 24, count 0 2006.183.07:55:32.59#ibcon#wrote, iclass 24, count 0 2006.183.07:55:32.59#ibcon#about to read 3, iclass 24, count 0 2006.183.07:55:32.62#ibcon#read 3, iclass 24, count 0 2006.183.07:55:32.62#ibcon#about to read 4, iclass 24, count 0 2006.183.07:55:32.62#ibcon#read 4, iclass 24, count 0 2006.183.07:55:32.62#ibcon#about to read 5, iclass 24, count 0 2006.183.07:55:32.62#ibcon#read 5, iclass 24, count 0 2006.183.07:55:32.62#ibcon#about to read 6, iclass 24, count 0 2006.183.07:55:32.62#ibcon#read 6, iclass 24, count 0 2006.183.07:55:32.62#ibcon#end of sib2, iclass 24, count 0 2006.183.07:55:32.62#ibcon#*after write, iclass 24, count 0 2006.183.07:55:32.62#ibcon#*before return 0, iclass 24, count 0 2006.183.07:55:32.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:32.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.07:55:32.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.07:55:32.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.07:55:32.62$vc4f8/vbbw=wide 2006.183.07:55:32.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.07:55:32.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.07:55:32.62#ibcon#ireg 8 cls_cnt 0 2006.183.07:55:32.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:55:32.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:55:32.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:55:32.69#ibcon#enter wrdev, iclass 26, count 0 2006.183.07:55:32.69#ibcon#first serial, iclass 26, count 0 2006.183.07:55:32.69#ibcon#enter sib2, iclass 26, count 0 2006.183.07:55:32.69#ibcon#flushed, iclass 26, count 0 2006.183.07:55:32.69#ibcon#about to write, iclass 26, count 0 2006.183.07:55:32.69#ibcon#wrote, iclass 26, count 0 2006.183.07:55:32.69#ibcon#about to read 3, iclass 26, count 0 2006.183.07:55:32.71#ibcon#read 3, iclass 26, count 0 2006.183.07:55:32.71#ibcon#about to read 4, iclass 26, count 0 2006.183.07:55:32.71#ibcon#read 4, iclass 26, count 0 2006.183.07:55:32.71#ibcon#about to read 5, iclass 26, count 0 2006.183.07:55:32.71#ibcon#read 5, iclass 26, count 0 2006.183.07:55:32.71#ibcon#about to read 6, iclass 26, count 0 2006.183.07:55:32.71#ibcon#read 6, iclass 26, count 0 2006.183.07:55:32.71#ibcon#end of sib2, iclass 26, count 0 2006.183.07:55:32.71#ibcon#*mode == 0, iclass 26, count 0 2006.183.07:55:32.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.07:55:32.71#ibcon#[27=BW32\r\n] 2006.183.07:55:32.71#ibcon#*before write, iclass 26, count 0 2006.183.07:55:32.71#ibcon#enter sib2, iclass 26, count 0 2006.183.07:55:32.71#ibcon#flushed, iclass 26, count 0 2006.183.07:55:32.71#ibcon#about to write, iclass 26, count 0 2006.183.07:55:32.71#ibcon#wrote, iclass 26, count 0 2006.183.07:55:32.71#ibcon#about to read 3, iclass 26, count 0 2006.183.07:55:32.74#ibcon#read 3, iclass 26, count 0 2006.183.07:55:32.74#ibcon#about to read 4, iclass 26, count 0 2006.183.07:55:32.74#ibcon#read 4, iclass 26, count 0 2006.183.07:55:32.74#ibcon#about to read 5, iclass 26, count 0 2006.183.07:55:32.74#ibcon#read 5, iclass 26, count 0 2006.183.07:55:32.74#ibcon#about to read 6, iclass 26, count 0 2006.183.07:55:32.74#ibcon#read 6, iclass 26, count 0 2006.183.07:55:32.74#ibcon#end of sib2, iclass 26, count 0 2006.183.07:55:32.74#ibcon#*after write, iclass 26, count 0 2006.183.07:55:32.74#ibcon#*before return 0, iclass 26, count 0 2006.183.07:55:32.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:55:32.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.07:55:32.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.07:55:32.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.07:55:32.74$4f8m12a/ifd4f 2006.183.07:55:32.74$ifd4f/lo= 2006.183.07:55:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:55:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:55:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:55:32.74$ifd4f/patch= 2006.183.07:55:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:55:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:55:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:55:32.74$4f8m12a/"form=m,16.000,1:2 2006.183.07:55:32.74$4f8m12a/"tpicd 2006.183.07:55:32.74$4f8m12a/echo=off 2006.183.07:55:32.74$4f8m12a/xlog=off 2006.183.07:55:32.74:!2006.183.07:57:40 2006.183.07:55:32.78#abcon#<5=/09 1.9 7.0 28.00 87 996.3\r\n> 2006.183.07:55:53.14#trakl#Source acquired 2006.183.07:55:54.14#flagr#flagr/antenna,acquired 2006.183.07:57:40.00:preob 2006.183.07:57:40.13/onsource/TRACKING 2006.183.07:57:40.13:!2006.183.07:57:50 2006.183.07:57:50.00:data_valid=on 2006.183.07:57:50.00:midob 2006.183.07:57:51.13/onsource/TRACKING 2006.183.07:57:51.13/wx/28.05,996.3,87 2006.183.07:57:51.25/cable/+6.4524E-03 2006.183.07:57:52.34/va/01,08,usb,yes,29,31 2006.183.07:57:52.34/va/02,07,usb,yes,29,31 2006.183.07:57:52.34/va/03,06,usb,yes,31,31 2006.183.07:57:52.34/va/04,07,usb,yes,30,33 2006.183.07:57:52.34/va/05,07,usb,yes,32,34 2006.183.07:57:52.34/va/06,06,usb,yes,32,31 2006.183.07:57:52.34/va/07,06,usb,yes,32,32 2006.183.07:57:52.34/va/08,07,usb,yes,30,30 2006.183.07:57:52.57/valo/01,532.99,yes,locked 2006.183.07:57:52.57/valo/02,572.99,yes,locked 2006.183.07:57:52.57/valo/03,672.99,yes,locked 2006.183.07:57:52.57/valo/04,832.99,yes,locked 2006.183.07:57:52.57/valo/05,652.99,yes,locked 2006.183.07:57:52.57/valo/06,772.99,yes,locked 2006.183.07:57:52.57/valo/07,832.99,yes,locked 2006.183.07:57:52.57/valo/08,852.99,yes,locked 2006.183.07:57:53.66/vb/01,04,usb,yes,29,28 2006.183.07:57:53.66/vb/02,04,usb,yes,31,32 2006.183.07:57:53.66/vb/03,04,usb,yes,28,31 2006.183.07:57:53.66/vb/04,04,usb,yes,28,29 2006.183.07:57:53.66/vb/05,04,usb,yes,27,31 2006.183.07:57:53.66/vb/06,04,usb,yes,28,31 2006.183.07:57:53.66/vb/07,04,usb,yes,30,30 2006.183.07:57:53.66/vb/08,04,usb,yes,28,31 2006.183.07:57:53.90/vblo/01,632.99,yes,locked 2006.183.07:57:53.90/vblo/02,640.99,yes,locked 2006.183.07:57:53.90/vblo/03,656.99,yes,locked 2006.183.07:57:53.90/vblo/04,712.99,yes,locked 2006.183.07:57:53.90/vblo/05,744.99,yes,locked 2006.183.07:57:53.90/vblo/06,752.99,yes,locked 2006.183.07:57:53.90/vblo/07,734.99,yes,locked 2006.183.07:57:53.90/vblo/08,744.99,yes,locked 2006.183.07:57:54.05/vabw/8 2006.183.07:57:54.20/vbbw/8 2006.183.07:57:54.29/xfe/off,on,15.0 2006.183.07:57:54.66/ifatt/23,28,28,28 2006.183.07:57:55.08/fmout-gps/S +3.31E-07 2006.183.07:57:55.16:!2006.183.07:58:50 2006.183.07:58:50.00:data_valid=off 2006.183.07:58:50.00:postob 2006.183.07:58:50.20/cable/+6.4537E-03 2006.183.07:58:50.20/wx/28.08,996.3,87 2006.183.07:58:51.08/fmout-gps/S +3.31E-07 2006.183.07:58:51.08:scan_name=183-0759,k06183,60 2006.183.07:58:51.09:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.183.07:58:51.13#flagr#flagr/antenna,new-source 2006.183.07:58:52.13:checkk5 2006.183.07:58:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.183.07:58:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.07:58:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.07:58:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.183.07:58:54.00/chk_obsdata//k5ts1/T1830757??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:58:54.38/chk_obsdata//k5ts2/T1830757??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:58:54.74/chk_obsdata//k5ts3/T1830757??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:58:55.12/chk_obsdata//k5ts4/T1830757??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.07:58:55.81/k5log//k5ts1_log_newline 2006.183.07:58:56.50/k5log//k5ts2_log_newline 2006.183.07:58:57.20/k5log//k5ts3_log_newline 2006.183.07:58:57.88/k5log//k5ts4_log_newline 2006.183.07:58:57.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.07:58:57.91:4f8m12a=2 2006.183.07:58:57.91$4f8m12a/echo=on 2006.183.07:58:57.91$4f8m12a/pcalon 2006.183.07:58:57.91$pcalon/"no phase cal control is implemented here 2006.183.07:58:57.91$4f8m12a/"tpicd=stop 2006.183.07:58:57.91$4f8m12a/vc4f8 2006.183.07:58:57.91$vc4f8/valo=1,532.99 2006.183.07:58:57.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.07:58:57.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.07:58:57.91#ibcon#ireg 17 cls_cnt 0 2006.183.07:58:57.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:58:57.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:58:57.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:58:57.91#ibcon#enter wrdev, iclass 3, count 0 2006.183.07:58:57.91#ibcon#first serial, iclass 3, count 0 2006.183.07:58:57.91#ibcon#enter sib2, iclass 3, count 0 2006.183.07:58:57.91#ibcon#flushed, iclass 3, count 0 2006.183.07:58:57.91#ibcon#about to write, iclass 3, count 0 2006.183.07:58:57.91#ibcon#wrote, iclass 3, count 0 2006.183.07:58:57.91#ibcon#about to read 3, iclass 3, count 0 2006.183.07:58:57.95#ibcon#read 3, iclass 3, count 0 2006.183.07:58:57.95#ibcon#about to read 4, iclass 3, count 0 2006.183.07:58:57.95#ibcon#read 4, iclass 3, count 0 2006.183.07:58:57.95#ibcon#about to read 5, iclass 3, count 0 2006.183.07:58:57.95#ibcon#read 5, iclass 3, count 0 2006.183.07:58:57.95#ibcon#about to read 6, iclass 3, count 0 2006.183.07:58:57.95#ibcon#read 6, iclass 3, count 0 2006.183.07:58:57.95#ibcon#end of sib2, iclass 3, count 0 2006.183.07:58:57.95#ibcon#*mode == 0, iclass 3, count 0 2006.183.07:58:57.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.07:58:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.07:58:57.95#ibcon#*before write, iclass 3, count 0 2006.183.07:58:57.95#ibcon#enter sib2, iclass 3, count 0 2006.183.07:58:57.95#ibcon#flushed, iclass 3, count 0 2006.183.07:58:57.95#ibcon#about to write, iclass 3, count 0 2006.183.07:58:57.95#ibcon#wrote, iclass 3, count 0 2006.183.07:58:57.95#ibcon#about to read 3, iclass 3, count 0 2006.183.07:58:58.00#ibcon#read 3, iclass 3, count 0 2006.183.07:58:58.00#ibcon#about to read 4, iclass 3, count 0 2006.183.07:58:58.00#ibcon#read 4, iclass 3, count 0 2006.183.07:58:58.00#ibcon#about to read 5, iclass 3, count 0 2006.183.07:58:58.00#ibcon#read 5, iclass 3, count 0 2006.183.07:58:58.00#ibcon#about to read 6, iclass 3, count 0 2006.183.07:58:58.00#ibcon#read 6, iclass 3, count 0 2006.183.07:58:58.00#ibcon#end of sib2, iclass 3, count 0 2006.183.07:58:58.00#ibcon#*after write, iclass 3, count 0 2006.183.07:58:58.00#ibcon#*before return 0, iclass 3, count 0 2006.183.07:58:58.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:58:58.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:58:58.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.07:58:58.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.07:58:58.00$vc4f8/va=1,8 2006.183.07:58:58.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.07:58:58.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.07:58:58.00#ibcon#ireg 11 cls_cnt 2 2006.183.07:58:58.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:58:58.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:58:58.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:58:58.00#ibcon#enter wrdev, iclass 5, count 2 2006.183.07:58:58.00#ibcon#first serial, iclass 5, count 2 2006.183.07:58:58.00#ibcon#enter sib2, iclass 5, count 2 2006.183.07:58:58.00#ibcon#flushed, iclass 5, count 2 2006.183.07:58:58.00#ibcon#about to write, iclass 5, count 2 2006.183.07:58:58.00#ibcon#wrote, iclass 5, count 2 2006.183.07:58:58.00#ibcon#about to read 3, iclass 5, count 2 2006.183.07:58:58.02#ibcon#read 3, iclass 5, count 2 2006.183.07:58:58.02#ibcon#about to read 4, iclass 5, count 2 2006.183.07:58:58.02#ibcon#read 4, iclass 5, count 2 2006.183.07:58:58.02#ibcon#about to read 5, iclass 5, count 2 2006.183.07:58:58.02#ibcon#read 5, iclass 5, count 2 2006.183.07:58:58.02#ibcon#about to read 6, iclass 5, count 2 2006.183.07:58:58.02#ibcon#read 6, iclass 5, count 2 2006.183.07:58:58.02#ibcon#end of sib2, iclass 5, count 2 2006.183.07:58:58.02#ibcon#*mode == 0, iclass 5, count 2 2006.183.07:58:58.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.07:58:58.02#ibcon#[25=AT01-08\r\n] 2006.183.07:58:58.02#ibcon#*before write, iclass 5, count 2 2006.183.07:58:58.02#ibcon#enter sib2, iclass 5, count 2 2006.183.07:58:58.02#ibcon#flushed, iclass 5, count 2 2006.183.07:58:58.02#ibcon#about to write, iclass 5, count 2 2006.183.07:58:58.02#ibcon#wrote, iclass 5, count 2 2006.183.07:58:58.02#ibcon#about to read 3, iclass 5, count 2 2006.183.07:58:58.05#ibcon#read 3, iclass 5, count 2 2006.183.07:58:58.05#ibcon#about to read 4, iclass 5, count 2 2006.183.07:58:58.05#ibcon#read 4, iclass 5, count 2 2006.183.07:58:58.05#ibcon#about to read 5, iclass 5, count 2 2006.183.07:58:58.05#ibcon#read 5, iclass 5, count 2 2006.183.07:58:58.05#ibcon#about to read 6, iclass 5, count 2 2006.183.07:58:58.05#ibcon#read 6, iclass 5, count 2 2006.183.07:58:58.05#ibcon#end of sib2, iclass 5, count 2 2006.183.07:58:58.05#ibcon#*after write, iclass 5, count 2 2006.183.07:58:58.05#ibcon#*before return 0, iclass 5, count 2 2006.183.07:58:58.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:58:58.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:58:58.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.07:58:58.05#ibcon#ireg 7 cls_cnt 0 2006.183.07:58:58.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:58:58.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:58:58.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:58:58.17#ibcon#enter wrdev, iclass 5, count 0 2006.183.07:58:58.17#ibcon#first serial, iclass 5, count 0 2006.183.07:58:58.17#ibcon#enter sib2, iclass 5, count 0 2006.183.07:58:58.17#ibcon#flushed, iclass 5, count 0 2006.183.07:58:58.17#ibcon#about to write, iclass 5, count 0 2006.183.07:58:58.17#ibcon#wrote, iclass 5, count 0 2006.183.07:58:58.17#ibcon#about to read 3, iclass 5, count 0 2006.183.07:58:58.19#ibcon#read 3, iclass 5, count 0 2006.183.07:58:58.19#ibcon#about to read 4, iclass 5, count 0 2006.183.07:58:58.19#ibcon#read 4, iclass 5, count 0 2006.183.07:58:58.19#ibcon#about to read 5, iclass 5, count 0 2006.183.07:58:58.19#ibcon#read 5, iclass 5, count 0 2006.183.07:58:58.19#ibcon#about to read 6, iclass 5, count 0 2006.183.07:58:58.19#ibcon#read 6, iclass 5, count 0 2006.183.07:58:58.19#ibcon#end of sib2, iclass 5, count 0 2006.183.07:58:58.19#ibcon#*mode == 0, iclass 5, count 0 2006.183.07:58:58.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.07:58:58.19#ibcon#[25=USB\r\n] 2006.183.07:58:58.19#ibcon#*before write, iclass 5, count 0 2006.183.07:58:58.19#ibcon#enter sib2, iclass 5, count 0 2006.183.07:58:58.19#ibcon#flushed, iclass 5, count 0 2006.183.07:58:58.19#ibcon#about to write, iclass 5, count 0 2006.183.07:58:58.19#ibcon#wrote, iclass 5, count 0 2006.183.07:58:58.19#ibcon#about to read 3, iclass 5, count 0 2006.183.07:58:58.22#ibcon#read 3, iclass 5, count 0 2006.183.07:58:58.22#ibcon#about to read 4, iclass 5, count 0 2006.183.07:58:58.22#ibcon#read 4, iclass 5, count 0 2006.183.07:58:58.22#ibcon#about to read 5, iclass 5, count 0 2006.183.07:58:58.22#ibcon#read 5, iclass 5, count 0 2006.183.07:58:58.22#ibcon#about to read 6, iclass 5, count 0 2006.183.07:58:58.22#ibcon#read 6, iclass 5, count 0 2006.183.07:58:58.22#ibcon#end of sib2, iclass 5, count 0 2006.183.07:58:58.22#ibcon#*after write, iclass 5, count 0 2006.183.07:58:58.22#ibcon#*before return 0, iclass 5, count 0 2006.183.07:58:58.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:58:58.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:58:58.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.07:58:58.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.07:58:58.22$vc4f8/valo=2,572.99 2006.183.07:58:58.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.07:58:58.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.07:58:58.22#ibcon#ireg 17 cls_cnt 0 2006.183.07:58:58.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:58:58.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:58:58.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:58:58.22#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:58:58.22#ibcon#first serial, iclass 7, count 0 2006.183.07:58:58.22#ibcon#enter sib2, iclass 7, count 0 2006.183.07:58:58.22#ibcon#flushed, iclass 7, count 0 2006.183.07:58:58.22#ibcon#about to write, iclass 7, count 0 2006.183.07:58:58.22#ibcon#wrote, iclass 7, count 0 2006.183.07:58:58.22#ibcon#about to read 3, iclass 7, count 0 2006.183.07:58:58.24#ibcon#read 3, iclass 7, count 0 2006.183.07:58:58.24#ibcon#about to read 4, iclass 7, count 0 2006.183.07:58:58.24#ibcon#read 4, iclass 7, count 0 2006.183.07:58:58.24#ibcon#about to read 5, iclass 7, count 0 2006.183.07:58:58.24#ibcon#read 5, iclass 7, count 0 2006.183.07:58:58.24#ibcon#about to read 6, iclass 7, count 0 2006.183.07:58:58.24#ibcon#read 6, iclass 7, count 0 2006.183.07:58:58.24#ibcon#end of sib2, iclass 7, count 0 2006.183.07:58:58.24#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:58:58.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:58:58.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.07:58:58.24#ibcon#*before write, iclass 7, count 0 2006.183.07:58:58.24#ibcon#enter sib2, iclass 7, count 0 2006.183.07:58:58.24#ibcon#flushed, iclass 7, count 0 2006.183.07:58:58.24#ibcon#about to write, iclass 7, count 0 2006.183.07:58:58.24#ibcon#wrote, iclass 7, count 0 2006.183.07:58:58.24#ibcon#about to read 3, iclass 7, count 0 2006.183.07:58:58.28#ibcon#read 3, iclass 7, count 0 2006.183.07:58:58.28#ibcon#about to read 4, iclass 7, count 0 2006.183.07:58:58.28#ibcon#read 4, iclass 7, count 0 2006.183.07:58:58.28#ibcon#about to read 5, iclass 7, count 0 2006.183.07:58:58.28#ibcon#read 5, iclass 7, count 0 2006.183.07:58:58.28#ibcon#about to read 6, iclass 7, count 0 2006.183.07:58:58.28#ibcon#read 6, iclass 7, count 0 2006.183.07:58:58.28#ibcon#end of sib2, iclass 7, count 0 2006.183.07:58:58.28#ibcon#*after write, iclass 7, count 0 2006.183.07:58:58.28#ibcon#*before return 0, iclass 7, count 0 2006.183.07:58:58.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:58:58.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:58:58.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:58:58.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:58:58.28$vc4f8/va=2,7 2006.183.07:58:58.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.07:58:58.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.07:58:58.28#ibcon#ireg 11 cls_cnt 2 2006.183.07:58:58.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:58:58.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:58:58.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:58:58.34#ibcon#enter wrdev, iclass 11, count 2 2006.183.07:58:58.34#ibcon#first serial, iclass 11, count 2 2006.183.07:58:58.34#ibcon#enter sib2, iclass 11, count 2 2006.183.07:58:58.34#ibcon#flushed, iclass 11, count 2 2006.183.07:58:58.34#ibcon#about to write, iclass 11, count 2 2006.183.07:58:58.34#ibcon#wrote, iclass 11, count 2 2006.183.07:58:58.34#ibcon#about to read 3, iclass 11, count 2 2006.183.07:58:58.36#ibcon#read 3, iclass 11, count 2 2006.183.07:58:58.36#ibcon#about to read 4, iclass 11, count 2 2006.183.07:58:58.36#ibcon#read 4, iclass 11, count 2 2006.183.07:58:58.36#ibcon#about to read 5, iclass 11, count 2 2006.183.07:58:58.36#ibcon#read 5, iclass 11, count 2 2006.183.07:58:58.36#ibcon#about to read 6, iclass 11, count 2 2006.183.07:58:58.36#ibcon#read 6, iclass 11, count 2 2006.183.07:58:58.36#ibcon#end of sib2, iclass 11, count 2 2006.183.07:58:58.36#ibcon#*mode == 0, iclass 11, count 2 2006.183.07:58:58.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.07:58:58.36#ibcon#[25=AT02-07\r\n] 2006.183.07:58:58.36#ibcon#*before write, iclass 11, count 2 2006.183.07:58:58.36#ibcon#enter sib2, iclass 11, count 2 2006.183.07:58:58.36#ibcon#flushed, iclass 11, count 2 2006.183.07:58:58.36#ibcon#about to write, iclass 11, count 2 2006.183.07:58:58.36#ibcon#wrote, iclass 11, count 2 2006.183.07:58:58.36#ibcon#about to read 3, iclass 11, count 2 2006.183.07:58:58.39#ibcon#read 3, iclass 11, count 2 2006.183.07:58:58.39#ibcon#about to read 4, iclass 11, count 2 2006.183.07:58:58.39#ibcon#read 4, iclass 11, count 2 2006.183.07:58:58.39#ibcon#about to read 5, iclass 11, count 2 2006.183.07:58:58.39#ibcon#read 5, iclass 11, count 2 2006.183.07:58:58.39#ibcon#about to read 6, iclass 11, count 2 2006.183.07:58:58.39#ibcon#read 6, iclass 11, count 2 2006.183.07:58:58.39#ibcon#end of sib2, iclass 11, count 2 2006.183.07:58:58.39#ibcon#*after write, iclass 11, count 2 2006.183.07:58:58.39#ibcon#*before return 0, iclass 11, count 2 2006.183.07:58:58.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:58:58.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:58:58.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.07:58:58.39#ibcon#ireg 7 cls_cnt 0 2006.183.07:58:58.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:58:58.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:58:58.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:58:58.51#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:58:58.51#ibcon#first serial, iclass 11, count 0 2006.183.07:58:58.51#ibcon#enter sib2, iclass 11, count 0 2006.183.07:58:58.51#ibcon#flushed, iclass 11, count 0 2006.183.07:58:58.51#ibcon#about to write, iclass 11, count 0 2006.183.07:58:58.51#ibcon#wrote, iclass 11, count 0 2006.183.07:58:58.51#ibcon#about to read 3, iclass 11, count 0 2006.183.07:58:58.53#ibcon#read 3, iclass 11, count 0 2006.183.07:58:58.53#ibcon#about to read 4, iclass 11, count 0 2006.183.07:58:58.53#ibcon#read 4, iclass 11, count 0 2006.183.07:58:58.53#ibcon#about to read 5, iclass 11, count 0 2006.183.07:58:58.53#ibcon#read 5, iclass 11, count 0 2006.183.07:58:58.53#ibcon#about to read 6, iclass 11, count 0 2006.183.07:58:58.53#ibcon#read 6, iclass 11, count 0 2006.183.07:58:58.53#ibcon#end of sib2, iclass 11, count 0 2006.183.07:58:58.53#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:58:58.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:58:58.53#ibcon#[25=USB\r\n] 2006.183.07:58:58.53#ibcon#*before write, iclass 11, count 0 2006.183.07:58:58.53#ibcon#enter sib2, iclass 11, count 0 2006.183.07:58:58.53#ibcon#flushed, iclass 11, count 0 2006.183.07:58:58.53#ibcon#about to write, iclass 11, count 0 2006.183.07:58:58.53#ibcon#wrote, iclass 11, count 0 2006.183.07:58:58.53#ibcon#about to read 3, iclass 11, count 0 2006.183.07:58:58.56#ibcon#read 3, iclass 11, count 0 2006.183.07:58:58.56#ibcon#about to read 4, iclass 11, count 0 2006.183.07:58:58.56#ibcon#read 4, iclass 11, count 0 2006.183.07:58:58.56#ibcon#about to read 5, iclass 11, count 0 2006.183.07:58:58.56#ibcon#read 5, iclass 11, count 0 2006.183.07:58:58.56#ibcon#about to read 6, iclass 11, count 0 2006.183.07:58:58.56#ibcon#read 6, iclass 11, count 0 2006.183.07:58:58.56#ibcon#end of sib2, iclass 11, count 0 2006.183.07:58:58.56#ibcon#*after write, iclass 11, count 0 2006.183.07:58:58.56#ibcon#*before return 0, iclass 11, count 0 2006.183.07:58:58.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:58:58.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:58:58.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:58:58.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:58:58.56$vc4f8/valo=3,672.99 2006.183.07:58:58.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:58:58.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:58:58.56#ibcon#ireg 17 cls_cnt 0 2006.183.07:58:58.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:58:58.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:58:58.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:58:58.56#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:58:58.56#ibcon#first serial, iclass 13, count 0 2006.183.07:58:58.56#ibcon#enter sib2, iclass 13, count 0 2006.183.07:58:58.56#ibcon#flushed, iclass 13, count 0 2006.183.07:58:58.56#ibcon#about to write, iclass 13, count 0 2006.183.07:58:58.56#ibcon#wrote, iclass 13, count 0 2006.183.07:58:58.56#ibcon#about to read 3, iclass 13, count 0 2006.183.07:58:58.58#ibcon#read 3, iclass 13, count 0 2006.183.07:58:58.58#ibcon#about to read 4, iclass 13, count 0 2006.183.07:58:58.58#ibcon#read 4, iclass 13, count 0 2006.183.07:58:58.58#ibcon#about to read 5, iclass 13, count 0 2006.183.07:58:58.58#ibcon#read 5, iclass 13, count 0 2006.183.07:58:58.58#ibcon#about to read 6, iclass 13, count 0 2006.183.07:58:58.58#ibcon#read 6, iclass 13, count 0 2006.183.07:58:58.58#ibcon#end of sib2, iclass 13, count 0 2006.183.07:58:58.58#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:58:58.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:58:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.07:58:58.58#ibcon#*before write, iclass 13, count 0 2006.183.07:58:58.58#ibcon#enter sib2, iclass 13, count 0 2006.183.07:58:58.58#ibcon#flushed, iclass 13, count 0 2006.183.07:58:58.58#ibcon#about to write, iclass 13, count 0 2006.183.07:58:58.58#ibcon#wrote, iclass 13, count 0 2006.183.07:58:58.58#ibcon#about to read 3, iclass 13, count 0 2006.183.07:58:58.62#ibcon#read 3, iclass 13, count 0 2006.183.07:58:58.62#ibcon#about to read 4, iclass 13, count 0 2006.183.07:58:58.62#ibcon#read 4, iclass 13, count 0 2006.183.07:58:58.62#ibcon#about to read 5, iclass 13, count 0 2006.183.07:58:58.62#ibcon#read 5, iclass 13, count 0 2006.183.07:58:58.62#ibcon#about to read 6, iclass 13, count 0 2006.183.07:58:58.62#ibcon#read 6, iclass 13, count 0 2006.183.07:58:58.62#ibcon#end of sib2, iclass 13, count 0 2006.183.07:58:58.62#ibcon#*after write, iclass 13, count 0 2006.183.07:58:58.62#ibcon#*before return 0, iclass 13, count 0 2006.183.07:58:58.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:58:58.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:58:58.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:58:58.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:58:58.62$vc4f8/va=3,6 2006.183.07:58:58.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:58:58.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:58:58.62#ibcon#ireg 11 cls_cnt 2 2006.183.07:58:58.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:58:58.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:58:58.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:58:58.68#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:58:58.68#ibcon#first serial, iclass 15, count 2 2006.183.07:58:58.68#ibcon#enter sib2, iclass 15, count 2 2006.183.07:58:58.68#ibcon#flushed, iclass 15, count 2 2006.183.07:58:58.68#ibcon#about to write, iclass 15, count 2 2006.183.07:58:58.68#ibcon#wrote, iclass 15, count 2 2006.183.07:58:58.68#ibcon#about to read 3, iclass 15, count 2 2006.183.07:58:58.70#ibcon#read 3, iclass 15, count 2 2006.183.07:58:58.70#ibcon#about to read 4, iclass 15, count 2 2006.183.07:58:58.70#ibcon#read 4, iclass 15, count 2 2006.183.07:58:58.70#ibcon#about to read 5, iclass 15, count 2 2006.183.07:58:58.70#ibcon#read 5, iclass 15, count 2 2006.183.07:58:58.70#ibcon#about to read 6, iclass 15, count 2 2006.183.07:58:58.70#ibcon#read 6, iclass 15, count 2 2006.183.07:58:58.70#ibcon#end of sib2, iclass 15, count 2 2006.183.07:58:58.70#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:58:58.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:58:58.70#ibcon#[25=AT03-06\r\n] 2006.183.07:58:58.70#ibcon#*before write, iclass 15, count 2 2006.183.07:58:58.70#ibcon#enter sib2, iclass 15, count 2 2006.183.07:58:58.70#ibcon#flushed, iclass 15, count 2 2006.183.07:58:58.70#ibcon#about to write, iclass 15, count 2 2006.183.07:58:58.70#ibcon#wrote, iclass 15, count 2 2006.183.07:58:58.70#ibcon#about to read 3, iclass 15, count 2 2006.183.07:58:58.74#ibcon#read 3, iclass 15, count 2 2006.183.07:58:58.74#ibcon#about to read 4, iclass 15, count 2 2006.183.07:58:58.74#ibcon#read 4, iclass 15, count 2 2006.183.07:58:58.74#ibcon#about to read 5, iclass 15, count 2 2006.183.07:58:58.74#ibcon#read 5, iclass 15, count 2 2006.183.07:58:58.74#ibcon#about to read 6, iclass 15, count 2 2006.183.07:58:58.74#ibcon#read 6, iclass 15, count 2 2006.183.07:58:58.74#ibcon#end of sib2, iclass 15, count 2 2006.183.07:58:58.74#ibcon#*after write, iclass 15, count 2 2006.183.07:58:58.74#ibcon#*before return 0, iclass 15, count 2 2006.183.07:58:58.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:58:58.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:58:58.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:58:58.74#ibcon#ireg 7 cls_cnt 0 2006.183.07:58:58.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:58:58.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:58:58.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:58:58.86#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:58:58.86#ibcon#first serial, iclass 15, count 0 2006.183.07:58:58.86#ibcon#enter sib2, iclass 15, count 0 2006.183.07:58:58.86#ibcon#flushed, iclass 15, count 0 2006.183.07:58:58.86#ibcon#about to write, iclass 15, count 0 2006.183.07:58:58.86#ibcon#wrote, iclass 15, count 0 2006.183.07:58:58.86#ibcon#about to read 3, iclass 15, count 0 2006.183.07:58:58.88#ibcon#read 3, iclass 15, count 0 2006.183.07:58:58.88#ibcon#about to read 4, iclass 15, count 0 2006.183.07:58:58.88#ibcon#read 4, iclass 15, count 0 2006.183.07:58:58.88#ibcon#about to read 5, iclass 15, count 0 2006.183.07:58:58.88#ibcon#read 5, iclass 15, count 0 2006.183.07:58:58.88#ibcon#about to read 6, iclass 15, count 0 2006.183.07:58:58.88#ibcon#read 6, iclass 15, count 0 2006.183.07:58:58.88#ibcon#end of sib2, iclass 15, count 0 2006.183.07:58:58.88#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:58:58.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:58:58.88#ibcon#[25=USB\r\n] 2006.183.07:58:58.88#ibcon#*before write, iclass 15, count 0 2006.183.07:58:58.88#ibcon#enter sib2, iclass 15, count 0 2006.183.07:58:58.88#ibcon#flushed, iclass 15, count 0 2006.183.07:58:58.88#ibcon#about to write, iclass 15, count 0 2006.183.07:58:58.88#ibcon#wrote, iclass 15, count 0 2006.183.07:58:58.88#ibcon#about to read 3, iclass 15, count 0 2006.183.07:58:58.91#ibcon#read 3, iclass 15, count 0 2006.183.07:58:58.91#ibcon#about to read 4, iclass 15, count 0 2006.183.07:58:58.91#ibcon#read 4, iclass 15, count 0 2006.183.07:58:58.91#ibcon#about to read 5, iclass 15, count 0 2006.183.07:58:58.91#ibcon#read 5, iclass 15, count 0 2006.183.07:58:58.91#ibcon#about to read 6, iclass 15, count 0 2006.183.07:58:58.91#ibcon#read 6, iclass 15, count 0 2006.183.07:58:58.91#ibcon#end of sib2, iclass 15, count 0 2006.183.07:58:58.91#ibcon#*after write, iclass 15, count 0 2006.183.07:58:58.91#ibcon#*before return 0, iclass 15, count 0 2006.183.07:58:58.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:58:58.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:58:58.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:58:58.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:58:58.91$vc4f8/valo=4,832.99 2006.183.07:58:58.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:58:58.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:58:58.91#ibcon#ireg 17 cls_cnt 0 2006.183.07:58:58.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:58:58.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:58:58.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:58:58.91#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:58:58.91#ibcon#first serial, iclass 17, count 0 2006.183.07:58:58.91#ibcon#enter sib2, iclass 17, count 0 2006.183.07:58:58.91#ibcon#flushed, iclass 17, count 0 2006.183.07:58:58.91#ibcon#about to write, iclass 17, count 0 2006.183.07:58:58.91#ibcon#wrote, iclass 17, count 0 2006.183.07:58:58.91#ibcon#about to read 3, iclass 17, count 0 2006.183.07:58:58.93#ibcon#read 3, iclass 17, count 0 2006.183.07:58:58.93#ibcon#about to read 4, iclass 17, count 0 2006.183.07:58:58.93#ibcon#read 4, iclass 17, count 0 2006.183.07:58:58.93#ibcon#about to read 5, iclass 17, count 0 2006.183.07:58:58.93#ibcon#read 5, iclass 17, count 0 2006.183.07:58:58.93#ibcon#about to read 6, iclass 17, count 0 2006.183.07:58:58.93#ibcon#read 6, iclass 17, count 0 2006.183.07:58:58.93#ibcon#end of sib2, iclass 17, count 0 2006.183.07:58:58.93#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:58:58.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:58:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.07:58:58.93#ibcon#*before write, iclass 17, count 0 2006.183.07:58:58.93#ibcon#enter sib2, iclass 17, count 0 2006.183.07:58:58.93#ibcon#flushed, iclass 17, count 0 2006.183.07:58:58.93#ibcon#about to write, iclass 17, count 0 2006.183.07:58:58.93#ibcon#wrote, iclass 17, count 0 2006.183.07:58:58.93#ibcon#about to read 3, iclass 17, count 0 2006.183.07:58:58.97#ibcon#read 3, iclass 17, count 0 2006.183.07:58:58.97#ibcon#about to read 4, iclass 17, count 0 2006.183.07:58:58.97#ibcon#read 4, iclass 17, count 0 2006.183.07:58:58.97#ibcon#about to read 5, iclass 17, count 0 2006.183.07:58:58.97#ibcon#read 5, iclass 17, count 0 2006.183.07:58:58.97#ibcon#about to read 6, iclass 17, count 0 2006.183.07:58:58.97#ibcon#read 6, iclass 17, count 0 2006.183.07:58:58.97#ibcon#end of sib2, iclass 17, count 0 2006.183.07:58:58.97#ibcon#*after write, iclass 17, count 0 2006.183.07:58:58.97#ibcon#*before return 0, iclass 17, count 0 2006.183.07:58:58.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:58:58.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:58:58.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:58:58.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:58:58.97$vc4f8/va=4,7 2006.183.07:58:58.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:58:58.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:58:58.97#ibcon#ireg 11 cls_cnt 2 2006.183.07:58:58.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:58:59.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:58:59.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:58:59.03#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:58:59.03#ibcon#first serial, iclass 19, count 2 2006.183.07:58:59.03#ibcon#enter sib2, iclass 19, count 2 2006.183.07:58:59.03#ibcon#flushed, iclass 19, count 2 2006.183.07:58:59.03#ibcon#about to write, iclass 19, count 2 2006.183.07:58:59.03#ibcon#wrote, iclass 19, count 2 2006.183.07:58:59.03#ibcon#about to read 3, iclass 19, count 2 2006.183.07:58:59.05#ibcon#read 3, iclass 19, count 2 2006.183.07:58:59.05#ibcon#about to read 4, iclass 19, count 2 2006.183.07:58:59.05#ibcon#read 4, iclass 19, count 2 2006.183.07:58:59.05#ibcon#about to read 5, iclass 19, count 2 2006.183.07:58:59.05#ibcon#read 5, iclass 19, count 2 2006.183.07:58:59.05#ibcon#about to read 6, iclass 19, count 2 2006.183.07:58:59.05#ibcon#read 6, iclass 19, count 2 2006.183.07:58:59.05#ibcon#end of sib2, iclass 19, count 2 2006.183.07:58:59.05#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:58:59.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:58:59.05#ibcon#[25=AT04-07\r\n] 2006.183.07:58:59.05#ibcon#*before write, iclass 19, count 2 2006.183.07:58:59.05#ibcon#enter sib2, iclass 19, count 2 2006.183.07:58:59.05#ibcon#flushed, iclass 19, count 2 2006.183.07:58:59.05#ibcon#about to write, iclass 19, count 2 2006.183.07:58:59.05#ibcon#wrote, iclass 19, count 2 2006.183.07:58:59.05#ibcon#about to read 3, iclass 19, count 2 2006.183.07:58:59.08#ibcon#read 3, iclass 19, count 2 2006.183.07:58:59.08#ibcon#about to read 4, iclass 19, count 2 2006.183.07:58:59.08#ibcon#read 4, iclass 19, count 2 2006.183.07:58:59.08#ibcon#about to read 5, iclass 19, count 2 2006.183.07:58:59.08#ibcon#read 5, iclass 19, count 2 2006.183.07:58:59.08#ibcon#about to read 6, iclass 19, count 2 2006.183.07:58:59.08#ibcon#read 6, iclass 19, count 2 2006.183.07:58:59.08#ibcon#end of sib2, iclass 19, count 2 2006.183.07:58:59.08#ibcon#*after write, iclass 19, count 2 2006.183.07:58:59.08#ibcon#*before return 0, iclass 19, count 2 2006.183.07:58:59.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:58:59.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:58:59.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:58:59.08#ibcon#ireg 7 cls_cnt 0 2006.183.07:58:59.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:58:59.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:58:59.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:58:59.20#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:58:59.20#ibcon#first serial, iclass 19, count 0 2006.183.07:58:59.20#ibcon#enter sib2, iclass 19, count 0 2006.183.07:58:59.20#ibcon#flushed, iclass 19, count 0 2006.183.07:58:59.20#ibcon#about to write, iclass 19, count 0 2006.183.07:58:59.20#ibcon#wrote, iclass 19, count 0 2006.183.07:58:59.20#ibcon#about to read 3, iclass 19, count 0 2006.183.07:58:59.22#ibcon#read 3, iclass 19, count 0 2006.183.07:58:59.22#ibcon#about to read 4, iclass 19, count 0 2006.183.07:58:59.22#ibcon#read 4, iclass 19, count 0 2006.183.07:58:59.22#ibcon#about to read 5, iclass 19, count 0 2006.183.07:58:59.22#ibcon#read 5, iclass 19, count 0 2006.183.07:58:59.22#ibcon#about to read 6, iclass 19, count 0 2006.183.07:58:59.22#ibcon#read 6, iclass 19, count 0 2006.183.07:58:59.22#ibcon#end of sib2, iclass 19, count 0 2006.183.07:58:59.22#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:58:59.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:58:59.22#ibcon#[25=USB\r\n] 2006.183.07:58:59.22#ibcon#*before write, iclass 19, count 0 2006.183.07:58:59.22#ibcon#enter sib2, iclass 19, count 0 2006.183.07:58:59.22#ibcon#flushed, iclass 19, count 0 2006.183.07:58:59.22#ibcon#about to write, iclass 19, count 0 2006.183.07:58:59.22#ibcon#wrote, iclass 19, count 0 2006.183.07:58:59.22#ibcon#about to read 3, iclass 19, count 0 2006.183.07:58:59.25#ibcon#read 3, iclass 19, count 0 2006.183.07:58:59.25#ibcon#about to read 4, iclass 19, count 0 2006.183.07:58:59.25#ibcon#read 4, iclass 19, count 0 2006.183.07:58:59.25#ibcon#about to read 5, iclass 19, count 0 2006.183.07:58:59.25#ibcon#read 5, iclass 19, count 0 2006.183.07:58:59.25#ibcon#about to read 6, iclass 19, count 0 2006.183.07:58:59.25#ibcon#read 6, iclass 19, count 0 2006.183.07:58:59.25#ibcon#end of sib2, iclass 19, count 0 2006.183.07:58:59.25#ibcon#*after write, iclass 19, count 0 2006.183.07:58:59.25#ibcon#*before return 0, iclass 19, count 0 2006.183.07:58:59.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:58:59.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:58:59.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:58:59.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:58:59.25$vc4f8/valo=5,652.99 2006.183.07:58:59.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:58:59.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:58:59.25#ibcon#ireg 17 cls_cnt 0 2006.183.07:58:59.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:58:59.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:58:59.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:58:59.25#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:58:59.25#ibcon#first serial, iclass 21, count 0 2006.183.07:58:59.25#ibcon#enter sib2, iclass 21, count 0 2006.183.07:58:59.25#ibcon#flushed, iclass 21, count 0 2006.183.07:58:59.25#ibcon#about to write, iclass 21, count 0 2006.183.07:58:59.25#ibcon#wrote, iclass 21, count 0 2006.183.07:58:59.25#ibcon#about to read 3, iclass 21, count 0 2006.183.07:58:59.27#ibcon#read 3, iclass 21, count 0 2006.183.07:58:59.27#ibcon#about to read 4, iclass 21, count 0 2006.183.07:58:59.27#ibcon#read 4, iclass 21, count 0 2006.183.07:58:59.27#ibcon#about to read 5, iclass 21, count 0 2006.183.07:58:59.27#ibcon#read 5, iclass 21, count 0 2006.183.07:58:59.27#ibcon#about to read 6, iclass 21, count 0 2006.183.07:58:59.27#ibcon#read 6, iclass 21, count 0 2006.183.07:58:59.27#ibcon#end of sib2, iclass 21, count 0 2006.183.07:58:59.27#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:58:59.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:58:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.07:58:59.27#ibcon#*before write, iclass 21, count 0 2006.183.07:58:59.27#ibcon#enter sib2, iclass 21, count 0 2006.183.07:58:59.27#ibcon#flushed, iclass 21, count 0 2006.183.07:58:59.27#ibcon#about to write, iclass 21, count 0 2006.183.07:58:59.27#ibcon#wrote, iclass 21, count 0 2006.183.07:58:59.27#ibcon#about to read 3, iclass 21, count 0 2006.183.07:58:59.31#ibcon#read 3, iclass 21, count 0 2006.183.07:58:59.31#ibcon#about to read 4, iclass 21, count 0 2006.183.07:58:59.31#ibcon#read 4, iclass 21, count 0 2006.183.07:58:59.31#ibcon#about to read 5, iclass 21, count 0 2006.183.07:58:59.31#ibcon#read 5, iclass 21, count 0 2006.183.07:58:59.31#ibcon#about to read 6, iclass 21, count 0 2006.183.07:58:59.31#ibcon#read 6, iclass 21, count 0 2006.183.07:58:59.31#ibcon#end of sib2, iclass 21, count 0 2006.183.07:58:59.31#ibcon#*after write, iclass 21, count 0 2006.183.07:58:59.31#ibcon#*before return 0, iclass 21, count 0 2006.183.07:58:59.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:58:59.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:58:59.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:58:59.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:58:59.31$vc4f8/va=5,7 2006.183.07:58:59.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:58:59.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:58:59.31#ibcon#ireg 11 cls_cnt 2 2006.183.07:58:59.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:58:59.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:58:59.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:58:59.37#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:58:59.37#ibcon#first serial, iclass 23, count 2 2006.183.07:58:59.37#ibcon#enter sib2, iclass 23, count 2 2006.183.07:58:59.37#ibcon#flushed, iclass 23, count 2 2006.183.07:58:59.37#ibcon#about to write, iclass 23, count 2 2006.183.07:58:59.37#ibcon#wrote, iclass 23, count 2 2006.183.07:58:59.37#ibcon#about to read 3, iclass 23, count 2 2006.183.07:58:59.39#ibcon#read 3, iclass 23, count 2 2006.183.07:58:59.39#ibcon#about to read 4, iclass 23, count 2 2006.183.07:58:59.39#ibcon#read 4, iclass 23, count 2 2006.183.07:58:59.39#ibcon#about to read 5, iclass 23, count 2 2006.183.07:58:59.39#ibcon#read 5, iclass 23, count 2 2006.183.07:58:59.39#ibcon#about to read 6, iclass 23, count 2 2006.183.07:58:59.39#ibcon#read 6, iclass 23, count 2 2006.183.07:58:59.39#ibcon#end of sib2, iclass 23, count 2 2006.183.07:58:59.39#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:58:59.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:58:59.39#ibcon#[25=AT05-07\r\n] 2006.183.07:58:59.39#ibcon#*before write, iclass 23, count 2 2006.183.07:58:59.39#ibcon#enter sib2, iclass 23, count 2 2006.183.07:58:59.39#ibcon#flushed, iclass 23, count 2 2006.183.07:58:59.39#ibcon#about to write, iclass 23, count 2 2006.183.07:58:59.39#ibcon#wrote, iclass 23, count 2 2006.183.07:58:59.39#ibcon#about to read 3, iclass 23, count 2 2006.183.07:58:59.42#ibcon#read 3, iclass 23, count 2 2006.183.07:58:59.42#ibcon#about to read 4, iclass 23, count 2 2006.183.07:58:59.42#ibcon#read 4, iclass 23, count 2 2006.183.07:58:59.42#ibcon#about to read 5, iclass 23, count 2 2006.183.07:58:59.42#ibcon#read 5, iclass 23, count 2 2006.183.07:58:59.42#ibcon#about to read 6, iclass 23, count 2 2006.183.07:58:59.42#ibcon#read 6, iclass 23, count 2 2006.183.07:58:59.42#ibcon#end of sib2, iclass 23, count 2 2006.183.07:58:59.42#ibcon#*after write, iclass 23, count 2 2006.183.07:58:59.42#ibcon#*before return 0, iclass 23, count 2 2006.183.07:58:59.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:58:59.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:58:59.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:58:59.42#ibcon#ireg 7 cls_cnt 0 2006.183.07:58:59.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:58:59.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:58:59.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:58:59.54#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:58:59.54#ibcon#first serial, iclass 23, count 0 2006.183.07:58:59.54#ibcon#enter sib2, iclass 23, count 0 2006.183.07:58:59.54#ibcon#flushed, iclass 23, count 0 2006.183.07:58:59.54#ibcon#about to write, iclass 23, count 0 2006.183.07:58:59.54#ibcon#wrote, iclass 23, count 0 2006.183.07:58:59.54#ibcon#about to read 3, iclass 23, count 0 2006.183.07:58:59.56#ibcon#read 3, iclass 23, count 0 2006.183.07:58:59.56#ibcon#about to read 4, iclass 23, count 0 2006.183.07:58:59.56#ibcon#read 4, iclass 23, count 0 2006.183.07:58:59.56#ibcon#about to read 5, iclass 23, count 0 2006.183.07:58:59.56#ibcon#read 5, iclass 23, count 0 2006.183.07:58:59.56#ibcon#about to read 6, iclass 23, count 0 2006.183.07:58:59.56#ibcon#read 6, iclass 23, count 0 2006.183.07:58:59.56#ibcon#end of sib2, iclass 23, count 0 2006.183.07:58:59.56#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:58:59.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:58:59.56#ibcon#[25=USB\r\n] 2006.183.07:58:59.56#ibcon#*before write, iclass 23, count 0 2006.183.07:58:59.56#ibcon#enter sib2, iclass 23, count 0 2006.183.07:58:59.56#ibcon#flushed, iclass 23, count 0 2006.183.07:58:59.56#ibcon#about to write, iclass 23, count 0 2006.183.07:58:59.56#ibcon#wrote, iclass 23, count 0 2006.183.07:58:59.56#ibcon#about to read 3, iclass 23, count 0 2006.183.07:58:59.59#ibcon#read 3, iclass 23, count 0 2006.183.07:58:59.59#ibcon#about to read 4, iclass 23, count 0 2006.183.07:58:59.59#ibcon#read 4, iclass 23, count 0 2006.183.07:58:59.59#ibcon#about to read 5, iclass 23, count 0 2006.183.07:58:59.59#ibcon#read 5, iclass 23, count 0 2006.183.07:58:59.59#ibcon#about to read 6, iclass 23, count 0 2006.183.07:58:59.59#ibcon#read 6, iclass 23, count 0 2006.183.07:58:59.59#ibcon#end of sib2, iclass 23, count 0 2006.183.07:58:59.59#ibcon#*after write, iclass 23, count 0 2006.183.07:58:59.59#ibcon#*before return 0, iclass 23, count 0 2006.183.07:58:59.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:58:59.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:58:59.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:58:59.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:58:59.59$vc4f8/valo=6,772.99 2006.183.07:58:59.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:58:59.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:58:59.59#ibcon#ireg 17 cls_cnt 0 2006.183.07:58:59.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:58:59.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:58:59.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:58:59.59#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:58:59.59#ibcon#first serial, iclass 25, count 0 2006.183.07:58:59.59#ibcon#enter sib2, iclass 25, count 0 2006.183.07:58:59.59#ibcon#flushed, iclass 25, count 0 2006.183.07:58:59.59#ibcon#about to write, iclass 25, count 0 2006.183.07:58:59.59#ibcon#wrote, iclass 25, count 0 2006.183.07:58:59.59#ibcon#about to read 3, iclass 25, count 0 2006.183.07:58:59.61#ibcon#read 3, iclass 25, count 0 2006.183.07:58:59.61#ibcon#about to read 4, iclass 25, count 0 2006.183.07:58:59.61#ibcon#read 4, iclass 25, count 0 2006.183.07:58:59.61#ibcon#about to read 5, iclass 25, count 0 2006.183.07:58:59.61#ibcon#read 5, iclass 25, count 0 2006.183.07:58:59.61#ibcon#about to read 6, iclass 25, count 0 2006.183.07:58:59.61#ibcon#read 6, iclass 25, count 0 2006.183.07:58:59.61#ibcon#end of sib2, iclass 25, count 0 2006.183.07:58:59.61#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:58:59.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:58:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.07:58:59.61#ibcon#*before write, iclass 25, count 0 2006.183.07:58:59.61#ibcon#enter sib2, iclass 25, count 0 2006.183.07:58:59.61#ibcon#flushed, iclass 25, count 0 2006.183.07:58:59.61#ibcon#about to write, iclass 25, count 0 2006.183.07:58:59.61#ibcon#wrote, iclass 25, count 0 2006.183.07:58:59.61#ibcon#about to read 3, iclass 25, count 0 2006.183.07:58:59.65#ibcon#read 3, iclass 25, count 0 2006.183.07:58:59.65#ibcon#about to read 4, iclass 25, count 0 2006.183.07:58:59.65#ibcon#read 4, iclass 25, count 0 2006.183.07:58:59.65#ibcon#about to read 5, iclass 25, count 0 2006.183.07:58:59.65#ibcon#read 5, iclass 25, count 0 2006.183.07:58:59.65#ibcon#about to read 6, iclass 25, count 0 2006.183.07:58:59.65#ibcon#read 6, iclass 25, count 0 2006.183.07:58:59.65#ibcon#end of sib2, iclass 25, count 0 2006.183.07:58:59.65#ibcon#*after write, iclass 25, count 0 2006.183.07:58:59.65#ibcon#*before return 0, iclass 25, count 0 2006.183.07:58:59.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:58:59.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:58:59.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:58:59.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:58:59.65$vc4f8/va=6,6 2006.183.07:58:59.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.07:58:59.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.07:58:59.65#ibcon#ireg 11 cls_cnt 2 2006.183.07:58:59.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:58:59.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:58:59.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:58:59.71#ibcon#enter wrdev, iclass 27, count 2 2006.183.07:58:59.71#ibcon#first serial, iclass 27, count 2 2006.183.07:58:59.71#ibcon#enter sib2, iclass 27, count 2 2006.183.07:58:59.71#ibcon#flushed, iclass 27, count 2 2006.183.07:58:59.71#ibcon#about to write, iclass 27, count 2 2006.183.07:58:59.71#ibcon#wrote, iclass 27, count 2 2006.183.07:58:59.71#ibcon#about to read 3, iclass 27, count 2 2006.183.07:58:59.73#ibcon#read 3, iclass 27, count 2 2006.183.07:58:59.73#ibcon#about to read 4, iclass 27, count 2 2006.183.07:58:59.73#ibcon#read 4, iclass 27, count 2 2006.183.07:58:59.73#ibcon#about to read 5, iclass 27, count 2 2006.183.07:58:59.73#ibcon#read 5, iclass 27, count 2 2006.183.07:58:59.73#ibcon#about to read 6, iclass 27, count 2 2006.183.07:58:59.73#ibcon#read 6, iclass 27, count 2 2006.183.07:58:59.73#ibcon#end of sib2, iclass 27, count 2 2006.183.07:58:59.73#ibcon#*mode == 0, iclass 27, count 2 2006.183.07:58:59.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.07:58:59.73#ibcon#[25=AT06-06\r\n] 2006.183.07:58:59.73#ibcon#*before write, iclass 27, count 2 2006.183.07:58:59.73#ibcon#enter sib2, iclass 27, count 2 2006.183.07:58:59.73#ibcon#flushed, iclass 27, count 2 2006.183.07:58:59.73#ibcon#about to write, iclass 27, count 2 2006.183.07:58:59.73#ibcon#wrote, iclass 27, count 2 2006.183.07:58:59.73#ibcon#about to read 3, iclass 27, count 2 2006.183.07:58:59.76#ibcon#read 3, iclass 27, count 2 2006.183.07:58:59.76#ibcon#about to read 4, iclass 27, count 2 2006.183.07:58:59.76#ibcon#read 4, iclass 27, count 2 2006.183.07:58:59.76#ibcon#about to read 5, iclass 27, count 2 2006.183.07:58:59.76#ibcon#read 5, iclass 27, count 2 2006.183.07:58:59.76#ibcon#about to read 6, iclass 27, count 2 2006.183.07:58:59.76#ibcon#read 6, iclass 27, count 2 2006.183.07:58:59.76#ibcon#end of sib2, iclass 27, count 2 2006.183.07:58:59.76#ibcon#*after write, iclass 27, count 2 2006.183.07:58:59.76#ibcon#*before return 0, iclass 27, count 2 2006.183.07:58:59.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:58:59.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.07:58:59.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.07:58:59.76#ibcon#ireg 7 cls_cnt 0 2006.183.07:58:59.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:58:59.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:58:59.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:58:59.88#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:58:59.88#ibcon#first serial, iclass 27, count 0 2006.183.07:58:59.88#ibcon#enter sib2, iclass 27, count 0 2006.183.07:58:59.88#ibcon#flushed, iclass 27, count 0 2006.183.07:58:59.88#ibcon#about to write, iclass 27, count 0 2006.183.07:58:59.88#ibcon#wrote, iclass 27, count 0 2006.183.07:58:59.88#ibcon#about to read 3, iclass 27, count 0 2006.183.07:58:59.90#ibcon#read 3, iclass 27, count 0 2006.183.07:58:59.90#ibcon#about to read 4, iclass 27, count 0 2006.183.07:58:59.90#ibcon#read 4, iclass 27, count 0 2006.183.07:58:59.90#ibcon#about to read 5, iclass 27, count 0 2006.183.07:58:59.90#ibcon#read 5, iclass 27, count 0 2006.183.07:58:59.90#ibcon#about to read 6, iclass 27, count 0 2006.183.07:58:59.90#ibcon#read 6, iclass 27, count 0 2006.183.07:58:59.90#ibcon#end of sib2, iclass 27, count 0 2006.183.07:58:59.90#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:58:59.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:58:59.90#ibcon#[25=USB\r\n] 2006.183.07:58:59.90#ibcon#*before write, iclass 27, count 0 2006.183.07:58:59.90#ibcon#enter sib2, iclass 27, count 0 2006.183.07:58:59.90#ibcon#flushed, iclass 27, count 0 2006.183.07:58:59.90#ibcon#about to write, iclass 27, count 0 2006.183.07:58:59.90#ibcon#wrote, iclass 27, count 0 2006.183.07:58:59.90#ibcon#about to read 3, iclass 27, count 0 2006.183.07:58:59.93#ibcon#read 3, iclass 27, count 0 2006.183.07:58:59.93#ibcon#about to read 4, iclass 27, count 0 2006.183.07:58:59.93#ibcon#read 4, iclass 27, count 0 2006.183.07:58:59.93#ibcon#about to read 5, iclass 27, count 0 2006.183.07:58:59.93#ibcon#read 5, iclass 27, count 0 2006.183.07:58:59.93#ibcon#about to read 6, iclass 27, count 0 2006.183.07:58:59.93#ibcon#read 6, iclass 27, count 0 2006.183.07:58:59.93#ibcon#end of sib2, iclass 27, count 0 2006.183.07:58:59.93#ibcon#*after write, iclass 27, count 0 2006.183.07:58:59.93#ibcon#*before return 0, iclass 27, count 0 2006.183.07:58:59.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:58:59.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.07:58:59.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:58:59.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:58:59.93$vc4f8/valo=7,832.99 2006.183.07:58:59.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.07:58:59.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.07:58:59.93#ibcon#ireg 17 cls_cnt 0 2006.183.07:58:59.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:58:59.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:58:59.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:58:59.93#ibcon#enter wrdev, iclass 29, count 0 2006.183.07:58:59.93#ibcon#first serial, iclass 29, count 0 2006.183.07:58:59.93#ibcon#enter sib2, iclass 29, count 0 2006.183.07:58:59.93#ibcon#flushed, iclass 29, count 0 2006.183.07:58:59.93#ibcon#about to write, iclass 29, count 0 2006.183.07:58:59.93#ibcon#wrote, iclass 29, count 0 2006.183.07:58:59.93#ibcon#about to read 3, iclass 29, count 0 2006.183.07:58:59.95#ibcon#read 3, iclass 29, count 0 2006.183.07:58:59.95#ibcon#about to read 4, iclass 29, count 0 2006.183.07:58:59.95#ibcon#read 4, iclass 29, count 0 2006.183.07:58:59.95#ibcon#about to read 5, iclass 29, count 0 2006.183.07:58:59.95#ibcon#read 5, iclass 29, count 0 2006.183.07:58:59.95#ibcon#about to read 6, iclass 29, count 0 2006.183.07:58:59.95#ibcon#read 6, iclass 29, count 0 2006.183.07:58:59.95#ibcon#end of sib2, iclass 29, count 0 2006.183.07:58:59.95#ibcon#*mode == 0, iclass 29, count 0 2006.183.07:58:59.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.07:58:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.07:58:59.95#ibcon#*before write, iclass 29, count 0 2006.183.07:58:59.95#ibcon#enter sib2, iclass 29, count 0 2006.183.07:58:59.95#ibcon#flushed, iclass 29, count 0 2006.183.07:58:59.95#ibcon#about to write, iclass 29, count 0 2006.183.07:58:59.95#ibcon#wrote, iclass 29, count 0 2006.183.07:58:59.95#ibcon#about to read 3, iclass 29, count 0 2006.183.07:58:59.99#ibcon#read 3, iclass 29, count 0 2006.183.07:58:59.99#ibcon#about to read 4, iclass 29, count 0 2006.183.07:58:59.99#ibcon#read 4, iclass 29, count 0 2006.183.07:58:59.99#ibcon#about to read 5, iclass 29, count 0 2006.183.07:58:59.99#ibcon#read 5, iclass 29, count 0 2006.183.07:58:59.99#ibcon#about to read 6, iclass 29, count 0 2006.183.07:58:59.99#ibcon#read 6, iclass 29, count 0 2006.183.07:58:59.99#ibcon#end of sib2, iclass 29, count 0 2006.183.07:58:59.99#ibcon#*after write, iclass 29, count 0 2006.183.07:58:59.99#ibcon#*before return 0, iclass 29, count 0 2006.183.07:58:59.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:58:59.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.07:58:59.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.07:58:59.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.07:58:59.99$vc4f8/va=7,6 2006.183.07:58:59.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.07:58:59.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.07:58:59.99#ibcon#ireg 11 cls_cnt 2 2006.183.07:58:59.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:59:00.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:59:00.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:59:00.05#ibcon#enter wrdev, iclass 31, count 2 2006.183.07:59:00.05#ibcon#first serial, iclass 31, count 2 2006.183.07:59:00.05#ibcon#enter sib2, iclass 31, count 2 2006.183.07:59:00.05#ibcon#flushed, iclass 31, count 2 2006.183.07:59:00.05#ibcon#about to write, iclass 31, count 2 2006.183.07:59:00.05#ibcon#wrote, iclass 31, count 2 2006.183.07:59:00.05#ibcon#about to read 3, iclass 31, count 2 2006.183.07:59:00.07#ibcon#read 3, iclass 31, count 2 2006.183.07:59:00.07#ibcon#about to read 4, iclass 31, count 2 2006.183.07:59:00.07#ibcon#read 4, iclass 31, count 2 2006.183.07:59:00.07#ibcon#about to read 5, iclass 31, count 2 2006.183.07:59:00.07#ibcon#read 5, iclass 31, count 2 2006.183.07:59:00.07#ibcon#about to read 6, iclass 31, count 2 2006.183.07:59:00.07#ibcon#read 6, iclass 31, count 2 2006.183.07:59:00.07#ibcon#end of sib2, iclass 31, count 2 2006.183.07:59:00.07#ibcon#*mode == 0, iclass 31, count 2 2006.183.07:59:00.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.07:59:00.07#ibcon#[25=AT07-06\r\n] 2006.183.07:59:00.07#ibcon#*before write, iclass 31, count 2 2006.183.07:59:00.07#ibcon#enter sib2, iclass 31, count 2 2006.183.07:59:00.07#ibcon#flushed, iclass 31, count 2 2006.183.07:59:00.07#ibcon#about to write, iclass 31, count 2 2006.183.07:59:00.07#ibcon#wrote, iclass 31, count 2 2006.183.07:59:00.07#ibcon#about to read 3, iclass 31, count 2 2006.183.07:59:00.10#ibcon#read 3, iclass 31, count 2 2006.183.07:59:00.10#ibcon#about to read 4, iclass 31, count 2 2006.183.07:59:00.10#ibcon#read 4, iclass 31, count 2 2006.183.07:59:00.10#ibcon#about to read 5, iclass 31, count 2 2006.183.07:59:00.10#ibcon#read 5, iclass 31, count 2 2006.183.07:59:00.10#ibcon#about to read 6, iclass 31, count 2 2006.183.07:59:00.10#ibcon#read 6, iclass 31, count 2 2006.183.07:59:00.10#ibcon#end of sib2, iclass 31, count 2 2006.183.07:59:00.10#ibcon#*after write, iclass 31, count 2 2006.183.07:59:00.10#ibcon#*before return 0, iclass 31, count 2 2006.183.07:59:00.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:59:00.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.07:59:00.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.07:59:00.10#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:00.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:59:00.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:59:00.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:59:00.22#ibcon#enter wrdev, iclass 31, count 0 2006.183.07:59:00.22#ibcon#first serial, iclass 31, count 0 2006.183.07:59:00.22#ibcon#enter sib2, iclass 31, count 0 2006.183.07:59:00.22#ibcon#flushed, iclass 31, count 0 2006.183.07:59:00.22#ibcon#about to write, iclass 31, count 0 2006.183.07:59:00.22#ibcon#wrote, iclass 31, count 0 2006.183.07:59:00.22#ibcon#about to read 3, iclass 31, count 0 2006.183.07:59:00.24#ibcon#read 3, iclass 31, count 0 2006.183.07:59:00.24#ibcon#about to read 4, iclass 31, count 0 2006.183.07:59:00.24#ibcon#read 4, iclass 31, count 0 2006.183.07:59:00.24#ibcon#about to read 5, iclass 31, count 0 2006.183.07:59:00.24#ibcon#read 5, iclass 31, count 0 2006.183.07:59:00.24#ibcon#about to read 6, iclass 31, count 0 2006.183.07:59:00.24#ibcon#read 6, iclass 31, count 0 2006.183.07:59:00.24#ibcon#end of sib2, iclass 31, count 0 2006.183.07:59:00.24#ibcon#*mode == 0, iclass 31, count 0 2006.183.07:59:00.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.07:59:00.24#ibcon#[25=USB\r\n] 2006.183.07:59:00.24#ibcon#*before write, iclass 31, count 0 2006.183.07:59:00.24#ibcon#enter sib2, iclass 31, count 0 2006.183.07:59:00.24#ibcon#flushed, iclass 31, count 0 2006.183.07:59:00.24#ibcon#about to write, iclass 31, count 0 2006.183.07:59:00.24#ibcon#wrote, iclass 31, count 0 2006.183.07:59:00.24#ibcon#about to read 3, iclass 31, count 0 2006.183.07:59:00.27#ibcon#read 3, iclass 31, count 0 2006.183.07:59:00.27#ibcon#about to read 4, iclass 31, count 0 2006.183.07:59:00.27#ibcon#read 4, iclass 31, count 0 2006.183.07:59:00.27#ibcon#about to read 5, iclass 31, count 0 2006.183.07:59:00.27#ibcon#read 5, iclass 31, count 0 2006.183.07:59:00.27#ibcon#about to read 6, iclass 31, count 0 2006.183.07:59:00.27#ibcon#read 6, iclass 31, count 0 2006.183.07:59:00.27#ibcon#end of sib2, iclass 31, count 0 2006.183.07:59:00.27#ibcon#*after write, iclass 31, count 0 2006.183.07:59:00.27#ibcon#*before return 0, iclass 31, count 0 2006.183.07:59:00.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:59:00.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.07:59:00.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.07:59:00.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.07:59:00.27$vc4f8/valo=8,852.99 2006.183.07:59:00.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.07:59:00.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.07:59:00.27#ibcon#ireg 17 cls_cnt 0 2006.183.07:59:00.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:59:00.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:59:00.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:59:00.27#ibcon#enter wrdev, iclass 33, count 0 2006.183.07:59:00.27#ibcon#first serial, iclass 33, count 0 2006.183.07:59:00.27#ibcon#enter sib2, iclass 33, count 0 2006.183.07:59:00.27#ibcon#flushed, iclass 33, count 0 2006.183.07:59:00.27#ibcon#about to write, iclass 33, count 0 2006.183.07:59:00.27#ibcon#wrote, iclass 33, count 0 2006.183.07:59:00.27#ibcon#about to read 3, iclass 33, count 0 2006.183.07:59:00.29#ibcon#read 3, iclass 33, count 0 2006.183.07:59:00.29#ibcon#about to read 4, iclass 33, count 0 2006.183.07:59:00.29#ibcon#read 4, iclass 33, count 0 2006.183.07:59:00.29#ibcon#about to read 5, iclass 33, count 0 2006.183.07:59:00.29#ibcon#read 5, iclass 33, count 0 2006.183.07:59:00.29#ibcon#about to read 6, iclass 33, count 0 2006.183.07:59:00.29#ibcon#read 6, iclass 33, count 0 2006.183.07:59:00.29#ibcon#end of sib2, iclass 33, count 0 2006.183.07:59:00.29#ibcon#*mode == 0, iclass 33, count 0 2006.183.07:59:00.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.07:59:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.07:59:00.29#ibcon#*before write, iclass 33, count 0 2006.183.07:59:00.29#ibcon#enter sib2, iclass 33, count 0 2006.183.07:59:00.29#ibcon#flushed, iclass 33, count 0 2006.183.07:59:00.29#ibcon#about to write, iclass 33, count 0 2006.183.07:59:00.29#ibcon#wrote, iclass 33, count 0 2006.183.07:59:00.29#ibcon#about to read 3, iclass 33, count 0 2006.183.07:59:00.33#ibcon#read 3, iclass 33, count 0 2006.183.07:59:00.33#ibcon#about to read 4, iclass 33, count 0 2006.183.07:59:00.33#ibcon#read 4, iclass 33, count 0 2006.183.07:59:00.33#ibcon#about to read 5, iclass 33, count 0 2006.183.07:59:00.33#ibcon#read 5, iclass 33, count 0 2006.183.07:59:00.33#ibcon#about to read 6, iclass 33, count 0 2006.183.07:59:00.33#ibcon#read 6, iclass 33, count 0 2006.183.07:59:00.33#ibcon#end of sib2, iclass 33, count 0 2006.183.07:59:00.33#ibcon#*after write, iclass 33, count 0 2006.183.07:59:00.33#ibcon#*before return 0, iclass 33, count 0 2006.183.07:59:00.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:59:00.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.07:59:00.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.07:59:00.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.07:59:00.33$vc4f8/va=8,7 2006.183.07:59:00.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.183.07:59:00.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.183.07:59:00.33#ibcon#ireg 11 cls_cnt 2 2006.183.07:59:00.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:59:00.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:59:00.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:59:00.39#ibcon#enter wrdev, iclass 35, count 2 2006.183.07:59:00.39#ibcon#first serial, iclass 35, count 2 2006.183.07:59:00.39#ibcon#enter sib2, iclass 35, count 2 2006.183.07:59:00.39#ibcon#flushed, iclass 35, count 2 2006.183.07:59:00.39#ibcon#about to write, iclass 35, count 2 2006.183.07:59:00.39#ibcon#wrote, iclass 35, count 2 2006.183.07:59:00.39#ibcon#about to read 3, iclass 35, count 2 2006.183.07:59:00.41#ibcon#read 3, iclass 35, count 2 2006.183.07:59:00.41#ibcon#about to read 4, iclass 35, count 2 2006.183.07:59:00.41#ibcon#read 4, iclass 35, count 2 2006.183.07:59:00.41#ibcon#about to read 5, iclass 35, count 2 2006.183.07:59:00.41#ibcon#read 5, iclass 35, count 2 2006.183.07:59:00.41#ibcon#about to read 6, iclass 35, count 2 2006.183.07:59:00.41#ibcon#read 6, iclass 35, count 2 2006.183.07:59:00.41#ibcon#end of sib2, iclass 35, count 2 2006.183.07:59:00.41#ibcon#*mode == 0, iclass 35, count 2 2006.183.07:59:00.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.183.07:59:00.41#ibcon#[25=AT08-07\r\n] 2006.183.07:59:00.41#ibcon#*before write, iclass 35, count 2 2006.183.07:59:00.41#ibcon#enter sib2, iclass 35, count 2 2006.183.07:59:00.41#ibcon#flushed, iclass 35, count 2 2006.183.07:59:00.41#ibcon#about to write, iclass 35, count 2 2006.183.07:59:00.41#ibcon#wrote, iclass 35, count 2 2006.183.07:59:00.41#ibcon#about to read 3, iclass 35, count 2 2006.183.07:59:00.44#ibcon#read 3, iclass 35, count 2 2006.183.07:59:00.44#ibcon#about to read 4, iclass 35, count 2 2006.183.07:59:00.44#ibcon#read 4, iclass 35, count 2 2006.183.07:59:00.44#ibcon#about to read 5, iclass 35, count 2 2006.183.07:59:00.44#ibcon#read 5, iclass 35, count 2 2006.183.07:59:00.44#ibcon#about to read 6, iclass 35, count 2 2006.183.07:59:00.44#ibcon#read 6, iclass 35, count 2 2006.183.07:59:00.44#ibcon#end of sib2, iclass 35, count 2 2006.183.07:59:00.44#ibcon#*after write, iclass 35, count 2 2006.183.07:59:00.44#ibcon#*before return 0, iclass 35, count 2 2006.183.07:59:00.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:59:00.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.183.07:59:00.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.183.07:59:00.44#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:00.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:59:00.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:59:00.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:59:00.56#ibcon#enter wrdev, iclass 35, count 0 2006.183.07:59:00.56#ibcon#first serial, iclass 35, count 0 2006.183.07:59:00.56#ibcon#enter sib2, iclass 35, count 0 2006.183.07:59:00.56#ibcon#flushed, iclass 35, count 0 2006.183.07:59:00.56#ibcon#about to write, iclass 35, count 0 2006.183.07:59:00.56#ibcon#wrote, iclass 35, count 0 2006.183.07:59:00.56#ibcon#about to read 3, iclass 35, count 0 2006.183.07:59:00.58#ibcon#read 3, iclass 35, count 0 2006.183.07:59:00.58#ibcon#about to read 4, iclass 35, count 0 2006.183.07:59:00.58#ibcon#read 4, iclass 35, count 0 2006.183.07:59:00.58#ibcon#about to read 5, iclass 35, count 0 2006.183.07:59:00.58#ibcon#read 5, iclass 35, count 0 2006.183.07:59:00.58#ibcon#about to read 6, iclass 35, count 0 2006.183.07:59:00.58#ibcon#read 6, iclass 35, count 0 2006.183.07:59:00.58#ibcon#end of sib2, iclass 35, count 0 2006.183.07:59:00.58#ibcon#*mode == 0, iclass 35, count 0 2006.183.07:59:00.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.07:59:00.58#ibcon#[25=USB\r\n] 2006.183.07:59:00.58#ibcon#*before write, iclass 35, count 0 2006.183.07:59:00.58#ibcon#enter sib2, iclass 35, count 0 2006.183.07:59:00.58#ibcon#flushed, iclass 35, count 0 2006.183.07:59:00.58#ibcon#about to write, iclass 35, count 0 2006.183.07:59:00.58#ibcon#wrote, iclass 35, count 0 2006.183.07:59:00.58#ibcon#about to read 3, iclass 35, count 0 2006.183.07:59:00.61#ibcon#read 3, iclass 35, count 0 2006.183.07:59:00.61#ibcon#about to read 4, iclass 35, count 0 2006.183.07:59:00.61#ibcon#read 4, iclass 35, count 0 2006.183.07:59:00.61#ibcon#about to read 5, iclass 35, count 0 2006.183.07:59:00.61#ibcon#read 5, iclass 35, count 0 2006.183.07:59:00.61#ibcon#about to read 6, iclass 35, count 0 2006.183.07:59:00.61#ibcon#read 6, iclass 35, count 0 2006.183.07:59:00.61#ibcon#end of sib2, iclass 35, count 0 2006.183.07:59:00.61#ibcon#*after write, iclass 35, count 0 2006.183.07:59:00.61#ibcon#*before return 0, iclass 35, count 0 2006.183.07:59:00.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:59:00.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.183.07:59:00.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.07:59:00.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.07:59:00.61$vc4f8/vblo=1,632.99 2006.183.07:59:00.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.07:59:00.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.07:59:00.61#ibcon#ireg 17 cls_cnt 0 2006.183.07:59:00.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:59:00.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:59:00.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:59:00.61#ibcon#enter wrdev, iclass 37, count 0 2006.183.07:59:00.61#ibcon#first serial, iclass 37, count 0 2006.183.07:59:00.61#ibcon#enter sib2, iclass 37, count 0 2006.183.07:59:00.61#ibcon#flushed, iclass 37, count 0 2006.183.07:59:00.61#ibcon#about to write, iclass 37, count 0 2006.183.07:59:00.61#ibcon#wrote, iclass 37, count 0 2006.183.07:59:00.61#ibcon#about to read 3, iclass 37, count 0 2006.183.07:59:00.63#ibcon#read 3, iclass 37, count 0 2006.183.07:59:00.63#ibcon#about to read 4, iclass 37, count 0 2006.183.07:59:00.63#ibcon#read 4, iclass 37, count 0 2006.183.07:59:00.63#ibcon#about to read 5, iclass 37, count 0 2006.183.07:59:00.63#ibcon#read 5, iclass 37, count 0 2006.183.07:59:00.63#ibcon#about to read 6, iclass 37, count 0 2006.183.07:59:00.63#ibcon#read 6, iclass 37, count 0 2006.183.07:59:00.63#ibcon#end of sib2, iclass 37, count 0 2006.183.07:59:00.63#ibcon#*mode == 0, iclass 37, count 0 2006.183.07:59:00.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.07:59:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.07:59:00.63#ibcon#*before write, iclass 37, count 0 2006.183.07:59:00.63#ibcon#enter sib2, iclass 37, count 0 2006.183.07:59:00.63#ibcon#flushed, iclass 37, count 0 2006.183.07:59:00.63#ibcon#about to write, iclass 37, count 0 2006.183.07:59:00.63#ibcon#wrote, iclass 37, count 0 2006.183.07:59:00.63#ibcon#about to read 3, iclass 37, count 0 2006.183.07:59:00.67#ibcon#read 3, iclass 37, count 0 2006.183.07:59:00.67#ibcon#about to read 4, iclass 37, count 0 2006.183.07:59:00.67#ibcon#read 4, iclass 37, count 0 2006.183.07:59:00.67#ibcon#about to read 5, iclass 37, count 0 2006.183.07:59:00.67#ibcon#read 5, iclass 37, count 0 2006.183.07:59:00.67#ibcon#about to read 6, iclass 37, count 0 2006.183.07:59:00.67#ibcon#read 6, iclass 37, count 0 2006.183.07:59:00.67#ibcon#end of sib2, iclass 37, count 0 2006.183.07:59:00.67#ibcon#*after write, iclass 37, count 0 2006.183.07:59:00.67#ibcon#*before return 0, iclass 37, count 0 2006.183.07:59:00.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:59:00.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.07:59:00.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.07:59:00.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.07:59:00.67$vc4f8/vb=1,4 2006.183.07:59:00.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.07:59:00.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.07:59:00.67#ibcon#ireg 11 cls_cnt 2 2006.183.07:59:00.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:59:00.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:59:00.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:59:00.67#ibcon#enter wrdev, iclass 39, count 2 2006.183.07:59:00.67#ibcon#first serial, iclass 39, count 2 2006.183.07:59:00.67#ibcon#enter sib2, iclass 39, count 2 2006.183.07:59:00.67#ibcon#flushed, iclass 39, count 2 2006.183.07:59:00.67#ibcon#about to write, iclass 39, count 2 2006.183.07:59:00.67#ibcon#wrote, iclass 39, count 2 2006.183.07:59:00.67#ibcon#about to read 3, iclass 39, count 2 2006.183.07:59:00.69#ibcon#read 3, iclass 39, count 2 2006.183.07:59:00.69#ibcon#about to read 4, iclass 39, count 2 2006.183.07:59:00.69#ibcon#read 4, iclass 39, count 2 2006.183.07:59:00.69#ibcon#about to read 5, iclass 39, count 2 2006.183.07:59:00.69#ibcon#read 5, iclass 39, count 2 2006.183.07:59:00.69#ibcon#about to read 6, iclass 39, count 2 2006.183.07:59:00.69#ibcon#read 6, iclass 39, count 2 2006.183.07:59:00.69#ibcon#end of sib2, iclass 39, count 2 2006.183.07:59:00.69#ibcon#*mode == 0, iclass 39, count 2 2006.183.07:59:00.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.07:59:00.69#ibcon#[27=AT01-04\r\n] 2006.183.07:59:00.69#ibcon#*before write, iclass 39, count 2 2006.183.07:59:00.69#ibcon#enter sib2, iclass 39, count 2 2006.183.07:59:00.69#ibcon#flushed, iclass 39, count 2 2006.183.07:59:00.69#ibcon#about to write, iclass 39, count 2 2006.183.07:59:00.69#ibcon#wrote, iclass 39, count 2 2006.183.07:59:00.69#ibcon#about to read 3, iclass 39, count 2 2006.183.07:59:00.72#ibcon#read 3, iclass 39, count 2 2006.183.07:59:00.72#ibcon#about to read 4, iclass 39, count 2 2006.183.07:59:00.72#ibcon#read 4, iclass 39, count 2 2006.183.07:59:00.72#ibcon#about to read 5, iclass 39, count 2 2006.183.07:59:00.72#ibcon#read 5, iclass 39, count 2 2006.183.07:59:00.72#ibcon#about to read 6, iclass 39, count 2 2006.183.07:59:00.72#ibcon#read 6, iclass 39, count 2 2006.183.07:59:00.72#ibcon#end of sib2, iclass 39, count 2 2006.183.07:59:00.72#ibcon#*after write, iclass 39, count 2 2006.183.07:59:00.72#ibcon#*before return 0, iclass 39, count 2 2006.183.07:59:00.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:59:00.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.07:59:00.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.07:59:00.72#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:00.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:59:00.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:59:00.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:59:00.84#ibcon#enter wrdev, iclass 39, count 0 2006.183.07:59:00.84#ibcon#first serial, iclass 39, count 0 2006.183.07:59:00.84#ibcon#enter sib2, iclass 39, count 0 2006.183.07:59:00.84#ibcon#flushed, iclass 39, count 0 2006.183.07:59:00.84#ibcon#about to write, iclass 39, count 0 2006.183.07:59:00.84#ibcon#wrote, iclass 39, count 0 2006.183.07:59:00.84#ibcon#about to read 3, iclass 39, count 0 2006.183.07:59:00.86#ibcon#read 3, iclass 39, count 0 2006.183.07:59:00.86#ibcon#about to read 4, iclass 39, count 0 2006.183.07:59:00.86#ibcon#read 4, iclass 39, count 0 2006.183.07:59:00.86#ibcon#about to read 5, iclass 39, count 0 2006.183.07:59:00.86#ibcon#read 5, iclass 39, count 0 2006.183.07:59:00.86#ibcon#about to read 6, iclass 39, count 0 2006.183.07:59:00.86#ibcon#read 6, iclass 39, count 0 2006.183.07:59:00.86#ibcon#end of sib2, iclass 39, count 0 2006.183.07:59:00.86#ibcon#*mode == 0, iclass 39, count 0 2006.183.07:59:00.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.07:59:00.86#ibcon#[27=USB\r\n] 2006.183.07:59:00.86#ibcon#*before write, iclass 39, count 0 2006.183.07:59:00.86#ibcon#enter sib2, iclass 39, count 0 2006.183.07:59:00.86#ibcon#flushed, iclass 39, count 0 2006.183.07:59:00.86#ibcon#about to write, iclass 39, count 0 2006.183.07:59:00.86#ibcon#wrote, iclass 39, count 0 2006.183.07:59:00.86#ibcon#about to read 3, iclass 39, count 0 2006.183.07:59:00.89#ibcon#read 3, iclass 39, count 0 2006.183.07:59:00.89#ibcon#about to read 4, iclass 39, count 0 2006.183.07:59:00.89#ibcon#read 4, iclass 39, count 0 2006.183.07:59:00.89#ibcon#about to read 5, iclass 39, count 0 2006.183.07:59:00.89#ibcon#read 5, iclass 39, count 0 2006.183.07:59:00.89#ibcon#about to read 6, iclass 39, count 0 2006.183.07:59:00.89#ibcon#read 6, iclass 39, count 0 2006.183.07:59:00.89#ibcon#end of sib2, iclass 39, count 0 2006.183.07:59:00.89#ibcon#*after write, iclass 39, count 0 2006.183.07:59:00.89#ibcon#*before return 0, iclass 39, count 0 2006.183.07:59:00.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:59:00.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.07:59:00.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.07:59:00.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.07:59:00.89$vc4f8/vblo=2,640.99 2006.183.07:59:00.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.07:59:00.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.07:59:00.89#ibcon#ireg 17 cls_cnt 0 2006.183.07:59:00.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:59:00.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:59:00.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:59:00.89#ibcon#enter wrdev, iclass 3, count 0 2006.183.07:59:00.89#ibcon#first serial, iclass 3, count 0 2006.183.07:59:00.89#ibcon#enter sib2, iclass 3, count 0 2006.183.07:59:00.89#ibcon#flushed, iclass 3, count 0 2006.183.07:59:00.89#ibcon#about to write, iclass 3, count 0 2006.183.07:59:00.89#ibcon#wrote, iclass 3, count 0 2006.183.07:59:00.89#ibcon#about to read 3, iclass 3, count 0 2006.183.07:59:00.91#ibcon#read 3, iclass 3, count 0 2006.183.07:59:00.91#ibcon#about to read 4, iclass 3, count 0 2006.183.07:59:00.91#ibcon#read 4, iclass 3, count 0 2006.183.07:59:00.91#ibcon#about to read 5, iclass 3, count 0 2006.183.07:59:00.91#ibcon#read 5, iclass 3, count 0 2006.183.07:59:00.91#ibcon#about to read 6, iclass 3, count 0 2006.183.07:59:00.91#ibcon#read 6, iclass 3, count 0 2006.183.07:59:00.91#ibcon#end of sib2, iclass 3, count 0 2006.183.07:59:00.91#ibcon#*mode == 0, iclass 3, count 0 2006.183.07:59:00.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.07:59:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.07:59:00.91#ibcon#*before write, iclass 3, count 0 2006.183.07:59:00.91#ibcon#enter sib2, iclass 3, count 0 2006.183.07:59:00.91#ibcon#flushed, iclass 3, count 0 2006.183.07:59:00.91#ibcon#about to write, iclass 3, count 0 2006.183.07:59:00.91#ibcon#wrote, iclass 3, count 0 2006.183.07:59:00.91#ibcon#about to read 3, iclass 3, count 0 2006.183.07:59:00.95#ibcon#read 3, iclass 3, count 0 2006.183.07:59:00.95#ibcon#about to read 4, iclass 3, count 0 2006.183.07:59:00.95#ibcon#read 4, iclass 3, count 0 2006.183.07:59:00.95#ibcon#about to read 5, iclass 3, count 0 2006.183.07:59:00.95#ibcon#read 5, iclass 3, count 0 2006.183.07:59:00.95#ibcon#about to read 6, iclass 3, count 0 2006.183.07:59:00.95#ibcon#read 6, iclass 3, count 0 2006.183.07:59:00.95#ibcon#end of sib2, iclass 3, count 0 2006.183.07:59:00.95#ibcon#*after write, iclass 3, count 0 2006.183.07:59:00.95#ibcon#*before return 0, iclass 3, count 0 2006.183.07:59:00.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:59:00.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.07:59:00.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.07:59:00.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.07:59:00.95$vc4f8/vb=2,4 2006.183.07:59:00.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.07:59:00.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.07:59:00.95#ibcon#ireg 11 cls_cnt 2 2006.183.07:59:00.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:59:01.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:59:01.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:59:01.01#ibcon#enter wrdev, iclass 5, count 2 2006.183.07:59:01.01#ibcon#first serial, iclass 5, count 2 2006.183.07:59:01.01#ibcon#enter sib2, iclass 5, count 2 2006.183.07:59:01.01#ibcon#flushed, iclass 5, count 2 2006.183.07:59:01.01#ibcon#about to write, iclass 5, count 2 2006.183.07:59:01.01#ibcon#wrote, iclass 5, count 2 2006.183.07:59:01.01#ibcon#about to read 3, iclass 5, count 2 2006.183.07:59:01.03#ibcon#read 3, iclass 5, count 2 2006.183.07:59:01.03#ibcon#about to read 4, iclass 5, count 2 2006.183.07:59:01.03#ibcon#read 4, iclass 5, count 2 2006.183.07:59:01.03#ibcon#about to read 5, iclass 5, count 2 2006.183.07:59:01.03#ibcon#read 5, iclass 5, count 2 2006.183.07:59:01.03#ibcon#about to read 6, iclass 5, count 2 2006.183.07:59:01.03#ibcon#read 6, iclass 5, count 2 2006.183.07:59:01.03#ibcon#end of sib2, iclass 5, count 2 2006.183.07:59:01.03#ibcon#*mode == 0, iclass 5, count 2 2006.183.07:59:01.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.07:59:01.03#ibcon#[27=AT02-04\r\n] 2006.183.07:59:01.03#ibcon#*before write, iclass 5, count 2 2006.183.07:59:01.03#ibcon#enter sib2, iclass 5, count 2 2006.183.07:59:01.03#ibcon#flushed, iclass 5, count 2 2006.183.07:59:01.03#ibcon#about to write, iclass 5, count 2 2006.183.07:59:01.03#ibcon#wrote, iclass 5, count 2 2006.183.07:59:01.03#ibcon#about to read 3, iclass 5, count 2 2006.183.07:59:01.06#ibcon#read 3, iclass 5, count 2 2006.183.07:59:01.06#ibcon#about to read 4, iclass 5, count 2 2006.183.07:59:01.06#ibcon#read 4, iclass 5, count 2 2006.183.07:59:01.06#ibcon#about to read 5, iclass 5, count 2 2006.183.07:59:01.06#ibcon#read 5, iclass 5, count 2 2006.183.07:59:01.06#ibcon#about to read 6, iclass 5, count 2 2006.183.07:59:01.06#ibcon#read 6, iclass 5, count 2 2006.183.07:59:01.06#ibcon#end of sib2, iclass 5, count 2 2006.183.07:59:01.06#ibcon#*after write, iclass 5, count 2 2006.183.07:59:01.06#ibcon#*before return 0, iclass 5, count 2 2006.183.07:59:01.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:59:01.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.07:59:01.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.07:59:01.06#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:01.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:59:01.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:59:01.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:59:01.18#ibcon#enter wrdev, iclass 5, count 0 2006.183.07:59:01.18#ibcon#first serial, iclass 5, count 0 2006.183.07:59:01.18#ibcon#enter sib2, iclass 5, count 0 2006.183.07:59:01.18#ibcon#flushed, iclass 5, count 0 2006.183.07:59:01.18#ibcon#about to write, iclass 5, count 0 2006.183.07:59:01.18#ibcon#wrote, iclass 5, count 0 2006.183.07:59:01.18#ibcon#about to read 3, iclass 5, count 0 2006.183.07:59:01.20#ibcon#read 3, iclass 5, count 0 2006.183.07:59:01.20#ibcon#about to read 4, iclass 5, count 0 2006.183.07:59:01.20#ibcon#read 4, iclass 5, count 0 2006.183.07:59:01.20#ibcon#about to read 5, iclass 5, count 0 2006.183.07:59:01.20#ibcon#read 5, iclass 5, count 0 2006.183.07:59:01.20#ibcon#about to read 6, iclass 5, count 0 2006.183.07:59:01.20#ibcon#read 6, iclass 5, count 0 2006.183.07:59:01.20#ibcon#end of sib2, iclass 5, count 0 2006.183.07:59:01.20#ibcon#*mode == 0, iclass 5, count 0 2006.183.07:59:01.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.07:59:01.20#ibcon#[27=USB\r\n] 2006.183.07:59:01.20#ibcon#*before write, iclass 5, count 0 2006.183.07:59:01.20#ibcon#enter sib2, iclass 5, count 0 2006.183.07:59:01.20#ibcon#flushed, iclass 5, count 0 2006.183.07:59:01.20#ibcon#about to write, iclass 5, count 0 2006.183.07:59:01.20#ibcon#wrote, iclass 5, count 0 2006.183.07:59:01.20#ibcon#about to read 3, iclass 5, count 0 2006.183.07:59:01.23#ibcon#read 3, iclass 5, count 0 2006.183.07:59:01.23#ibcon#about to read 4, iclass 5, count 0 2006.183.07:59:01.23#ibcon#read 4, iclass 5, count 0 2006.183.07:59:01.23#ibcon#about to read 5, iclass 5, count 0 2006.183.07:59:01.23#ibcon#read 5, iclass 5, count 0 2006.183.07:59:01.23#ibcon#about to read 6, iclass 5, count 0 2006.183.07:59:01.23#ibcon#read 6, iclass 5, count 0 2006.183.07:59:01.23#ibcon#end of sib2, iclass 5, count 0 2006.183.07:59:01.23#ibcon#*after write, iclass 5, count 0 2006.183.07:59:01.23#ibcon#*before return 0, iclass 5, count 0 2006.183.07:59:01.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:59:01.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.07:59:01.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.07:59:01.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.07:59:01.23$vc4f8/vblo=3,656.99 2006.183.07:59:01.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.07:59:01.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.07:59:01.23#ibcon#ireg 17 cls_cnt 0 2006.183.07:59:01.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:59:01.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:59:01.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:59:01.23#ibcon#enter wrdev, iclass 7, count 0 2006.183.07:59:01.23#ibcon#first serial, iclass 7, count 0 2006.183.07:59:01.23#ibcon#enter sib2, iclass 7, count 0 2006.183.07:59:01.23#ibcon#flushed, iclass 7, count 0 2006.183.07:59:01.23#ibcon#about to write, iclass 7, count 0 2006.183.07:59:01.23#ibcon#wrote, iclass 7, count 0 2006.183.07:59:01.23#ibcon#about to read 3, iclass 7, count 0 2006.183.07:59:01.25#ibcon#read 3, iclass 7, count 0 2006.183.07:59:01.25#ibcon#about to read 4, iclass 7, count 0 2006.183.07:59:01.25#ibcon#read 4, iclass 7, count 0 2006.183.07:59:01.25#ibcon#about to read 5, iclass 7, count 0 2006.183.07:59:01.25#ibcon#read 5, iclass 7, count 0 2006.183.07:59:01.25#ibcon#about to read 6, iclass 7, count 0 2006.183.07:59:01.25#ibcon#read 6, iclass 7, count 0 2006.183.07:59:01.25#ibcon#end of sib2, iclass 7, count 0 2006.183.07:59:01.25#ibcon#*mode == 0, iclass 7, count 0 2006.183.07:59:01.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.07:59:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.07:59:01.25#ibcon#*before write, iclass 7, count 0 2006.183.07:59:01.25#ibcon#enter sib2, iclass 7, count 0 2006.183.07:59:01.25#ibcon#flushed, iclass 7, count 0 2006.183.07:59:01.25#ibcon#about to write, iclass 7, count 0 2006.183.07:59:01.25#ibcon#wrote, iclass 7, count 0 2006.183.07:59:01.25#ibcon#about to read 3, iclass 7, count 0 2006.183.07:59:01.29#ibcon#read 3, iclass 7, count 0 2006.183.07:59:01.29#ibcon#about to read 4, iclass 7, count 0 2006.183.07:59:01.29#ibcon#read 4, iclass 7, count 0 2006.183.07:59:01.29#ibcon#about to read 5, iclass 7, count 0 2006.183.07:59:01.29#ibcon#read 5, iclass 7, count 0 2006.183.07:59:01.29#ibcon#about to read 6, iclass 7, count 0 2006.183.07:59:01.29#ibcon#read 6, iclass 7, count 0 2006.183.07:59:01.29#ibcon#end of sib2, iclass 7, count 0 2006.183.07:59:01.29#ibcon#*after write, iclass 7, count 0 2006.183.07:59:01.29#ibcon#*before return 0, iclass 7, count 0 2006.183.07:59:01.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:59:01.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.07:59:01.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.07:59:01.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.07:59:01.29$vc4f8/vb=3,4 2006.183.07:59:01.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.07:59:01.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.07:59:01.29#ibcon#ireg 11 cls_cnt 2 2006.183.07:59:01.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:59:01.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:59:01.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:59:01.35#ibcon#enter wrdev, iclass 11, count 2 2006.183.07:59:01.35#ibcon#first serial, iclass 11, count 2 2006.183.07:59:01.35#ibcon#enter sib2, iclass 11, count 2 2006.183.07:59:01.35#ibcon#flushed, iclass 11, count 2 2006.183.07:59:01.35#ibcon#about to write, iclass 11, count 2 2006.183.07:59:01.35#ibcon#wrote, iclass 11, count 2 2006.183.07:59:01.35#ibcon#about to read 3, iclass 11, count 2 2006.183.07:59:01.37#ibcon#read 3, iclass 11, count 2 2006.183.07:59:01.37#ibcon#about to read 4, iclass 11, count 2 2006.183.07:59:01.37#ibcon#read 4, iclass 11, count 2 2006.183.07:59:01.37#ibcon#about to read 5, iclass 11, count 2 2006.183.07:59:01.37#ibcon#read 5, iclass 11, count 2 2006.183.07:59:01.37#ibcon#about to read 6, iclass 11, count 2 2006.183.07:59:01.37#ibcon#read 6, iclass 11, count 2 2006.183.07:59:01.37#ibcon#end of sib2, iclass 11, count 2 2006.183.07:59:01.37#ibcon#*mode == 0, iclass 11, count 2 2006.183.07:59:01.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.07:59:01.37#ibcon#[27=AT03-04\r\n] 2006.183.07:59:01.37#ibcon#*before write, iclass 11, count 2 2006.183.07:59:01.37#ibcon#enter sib2, iclass 11, count 2 2006.183.07:59:01.37#ibcon#flushed, iclass 11, count 2 2006.183.07:59:01.37#ibcon#about to write, iclass 11, count 2 2006.183.07:59:01.37#ibcon#wrote, iclass 11, count 2 2006.183.07:59:01.37#ibcon#about to read 3, iclass 11, count 2 2006.183.07:59:01.40#ibcon#read 3, iclass 11, count 2 2006.183.07:59:01.40#ibcon#about to read 4, iclass 11, count 2 2006.183.07:59:01.40#ibcon#read 4, iclass 11, count 2 2006.183.07:59:01.40#ibcon#about to read 5, iclass 11, count 2 2006.183.07:59:01.40#ibcon#read 5, iclass 11, count 2 2006.183.07:59:01.40#ibcon#about to read 6, iclass 11, count 2 2006.183.07:59:01.40#ibcon#read 6, iclass 11, count 2 2006.183.07:59:01.40#ibcon#end of sib2, iclass 11, count 2 2006.183.07:59:01.40#ibcon#*after write, iclass 11, count 2 2006.183.07:59:01.40#ibcon#*before return 0, iclass 11, count 2 2006.183.07:59:01.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:59:01.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.07:59:01.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.07:59:01.40#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:01.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:59:01.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:59:01.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:59:01.52#ibcon#enter wrdev, iclass 11, count 0 2006.183.07:59:01.52#ibcon#first serial, iclass 11, count 0 2006.183.07:59:01.52#ibcon#enter sib2, iclass 11, count 0 2006.183.07:59:01.52#ibcon#flushed, iclass 11, count 0 2006.183.07:59:01.52#ibcon#about to write, iclass 11, count 0 2006.183.07:59:01.52#ibcon#wrote, iclass 11, count 0 2006.183.07:59:01.52#ibcon#about to read 3, iclass 11, count 0 2006.183.07:59:01.54#ibcon#read 3, iclass 11, count 0 2006.183.07:59:01.54#ibcon#about to read 4, iclass 11, count 0 2006.183.07:59:01.54#ibcon#read 4, iclass 11, count 0 2006.183.07:59:01.54#ibcon#about to read 5, iclass 11, count 0 2006.183.07:59:01.54#ibcon#read 5, iclass 11, count 0 2006.183.07:59:01.54#ibcon#about to read 6, iclass 11, count 0 2006.183.07:59:01.54#ibcon#read 6, iclass 11, count 0 2006.183.07:59:01.54#ibcon#end of sib2, iclass 11, count 0 2006.183.07:59:01.54#ibcon#*mode == 0, iclass 11, count 0 2006.183.07:59:01.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.07:59:01.54#ibcon#[27=USB\r\n] 2006.183.07:59:01.54#ibcon#*before write, iclass 11, count 0 2006.183.07:59:01.54#ibcon#enter sib2, iclass 11, count 0 2006.183.07:59:01.54#ibcon#flushed, iclass 11, count 0 2006.183.07:59:01.54#ibcon#about to write, iclass 11, count 0 2006.183.07:59:01.54#ibcon#wrote, iclass 11, count 0 2006.183.07:59:01.54#ibcon#about to read 3, iclass 11, count 0 2006.183.07:59:01.57#ibcon#read 3, iclass 11, count 0 2006.183.07:59:01.57#ibcon#about to read 4, iclass 11, count 0 2006.183.07:59:01.57#ibcon#read 4, iclass 11, count 0 2006.183.07:59:01.57#ibcon#about to read 5, iclass 11, count 0 2006.183.07:59:01.57#ibcon#read 5, iclass 11, count 0 2006.183.07:59:01.57#ibcon#about to read 6, iclass 11, count 0 2006.183.07:59:01.57#ibcon#read 6, iclass 11, count 0 2006.183.07:59:01.57#ibcon#end of sib2, iclass 11, count 0 2006.183.07:59:01.57#ibcon#*after write, iclass 11, count 0 2006.183.07:59:01.57#ibcon#*before return 0, iclass 11, count 0 2006.183.07:59:01.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:59:01.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.07:59:01.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.07:59:01.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.07:59:01.57$vc4f8/vblo=4,712.99 2006.183.07:59:01.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.07:59:01.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.07:59:01.57#ibcon#ireg 17 cls_cnt 0 2006.183.07:59:01.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:59:01.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:59:01.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:59:01.57#ibcon#enter wrdev, iclass 13, count 0 2006.183.07:59:01.57#ibcon#first serial, iclass 13, count 0 2006.183.07:59:01.57#ibcon#enter sib2, iclass 13, count 0 2006.183.07:59:01.57#ibcon#flushed, iclass 13, count 0 2006.183.07:59:01.57#ibcon#about to write, iclass 13, count 0 2006.183.07:59:01.57#ibcon#wrote, iclass 13, count 0 2006.183.07:59:01.57#ibcon#about to read 3, iclass 13, count 0 2006.183.07:59:01.59#ibcon#read 3, iclass 13, count 0 2006.183.07:59:01.59#ibcon#about to read 4, iclass 13, count 0 2006.183.07:59:01.59#ibcon#read 4, iclass 13, count 0 2006.183.07:59:01.59#ibcon#about to read 5, iclass 13, count 0 2006.183.07:59:01.59#ibcon#read 5, iclass 13, count 0 2006.183.07:59:01.59#ibcon#about to read 6, iclass 13, count 0 2006.183.07:59:01.59#ibcon#read 6, iclass 13, count 0 2006.183.07:59:01.59#ibcon#end of sib2, iclass 13, count 0 2006.183.07:59:01.59#ibcon#*mode == 0, iclass 13, count 0 2006.183.07:59:01.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.07:59:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.07:59:01.59#ibcon#*before write, iclass 13, count 0 2006.183.07:59:01.59#ibcon#enter sib2, iclass 13, count 0 2006.183.07:59:01.59#ibcon#flushed, iclass 13, count 0 2006.183.07:59:01.59#ibcon#about to write, iclass 13, count 0 2006.183.07:59:01.59#ibcon#wrote, iclass 13, count 0 2006.183.07:59:01.59#ibcon#about to read 3, iclass 13, count 0 2006.183.07:59:01.63#ibcon#read 3, iclass 13, count 0 2006.183.07:59:01.63#ibcon#about to read 4, iclass 13, count 0 2006.183.07:59:01.63#ibcon#read 4, iclass 13, count 0 2006.183.07:59:01.63#ibcon#about to read 5, iclass 13, count 0 2006.183.07:59:01.63#ibcon#read 5, iclass 13, count 0 2006.183.07:59:01.63#ibcon#about to read 6, iclass 13, count 0 2006.183.07:59:01.63#ibcon#read 6, iclass 13, count 0 2006.183.07:59:01.63#ibcon#end of sib2, iclass 13, count 0 2006.183.07:59:01.63#ibcon#*after write, iclass 13, count 0 2006.183.07:59:01.63#ibcon#*before return 0, iclass 13, count 0 2006.183.07:59:01.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:59:01.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.07:59:01.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.07:59:01.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.07:59:01.63$vc4f8/vb=4,4 2006.183.07:59:01.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.07:59:01.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.07:59:01.63#ibcon#ireg 11 cls_cnt 2 2006.183.07:59:01.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:59:01.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:59:01.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:59:01.69#ibcon#enter wrdev, iclass 15, count 2 2006.183.07:59:01.69#ibcon#first serial, iclass 15, count 2 2006.183.07:59:01.69#ibcon#enter sib2, iclass 15, count 2 2006.183.07:59:01.69#ibcon#flushed, iclass 15, count 2 2006.183.07:59:01.69#ibcon#about to write, iclass 15, count 2 2006.183.07:59:01.69#ibcon#wrote, iclass 15, count 2 2006.183.07:59:01.69#ibcon#about to read 3, iclass 15, count 2 2006.183.07:59:01.71#ibcon#read 3, iclass 15, count 2 2006.183.07:59:01.71#ibcon#about to read 4, iclass 15, count 2 2006.183.07:59:01.71#ibcon#read 4, iclass 15, count 2 2006.183.07:59:01.71#ibcon#about to read 5, iclass 15, count 2 2006.183.07:59:01.71#ibcon#read 5, iclass 15, count 2 2006.183.07:59:01.71#ibcon#about to read 6, iclass 15, count 2 2006.183.07:59:01.71#ibcon#read 6, iclass 15, count 2 2006.183.07:59:01.71#ibcon#end of sib2, iclass 15, count 2 2006.183.07:59:01.71#ibcon#*mode == 0, iclass 15, count 2 2006.183.07:59:01.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.07:59:01.71#ibcon#[27=AT04-04\r\n] 2006.183.07:59:01.71#ibcon#*before write, iclass 15, count 2 2006.183.07:59:01.71#ibcon#enter sib2, iclass 15, count 2 2006.183.07:59:01.71#ibcon#flushed, iclass 15, count 2 2006.183.07:59:01.71#ibcon#about to write, iclass 15, count 2 2006.183.07:59:01.71#ibcon#wrote, iclass 15, count 2 2006.183.07:59:01.71#ibcon#about to read 3, iclass 15, count 2 2006.183.07:59:01.74#ibcon#read 3, iclass 15, count 2 2006.183.07:59:01.74#ibcon#about to read 4, iclass 15, count 2 2006.183.07:59:01.74#ibcon#read 4, iclass 15, count 2 2006.183.07:59:01.74#ibcon#about to read 5, iclass 15, count 2 2006.183.07:59:01.74#ibcon#read 5, iclass 15, count 2 2006.183.07:59:01.74#ibcon#about to read 6, iclass 15, count 2 2006.183.07:59:01.74#ibcon#read 6, iclass 15, count 2 2006.183.07:59:01.74#ibcon#end of sib2, iclass 15, count 2 2006.183.07:59:01.74#ibcon#*after write, iclass 15, count 2 2006.183.07:59:01.74#ibcon#*before return 0, iclass 15, count 2 2006.183.07:59:01.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:59:01.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.07:59:01.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.07:59:01.74#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:01.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:59:01.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:59:01.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:59:01.86#ibcon#enter wrdev, iclass 15, count 0 2006.183.07:59:01.86#ibcon#first serial, iclass 15, count 0 2006.183.07:59:01.86#ibcon#enter sib2, iclass 15, count 0 2006.183.07:59:01.86#ibcon#flushed, iclass 15, count 0 2006.183.07:59:01.86#ibcon#about to write, iclass 15, count 0 2006.183.07:59:01.86#ibcon#wrote, iclass 15, count 0 2006.183.07:59:01.86#ibcon#about to read 3, iclass 15, count 0 2006.183.07:59:01.88#ibcon#read 3, iclass 15, count 0 2006.183.07:59:01.88#ibcon#about to read 4, iclass 15, count 0 2006.183.07:59:01.88#ibcon#read 4, iclass 15, count 0 2006.183.07:59:01.88#ibcon#about to read 5, iclass 15, count 0 2006.183.07:59:01.88#ibcon#read 5, iclass 15, count 0 2006.183.07:59:01.88#ibcon#about to read 6, iclass 15, count 0 2006.183.07:59:01.88#ibcon#read 6, iclass 15, count 0 2006.183.07:59:01.88#ibcon#end of sib2, iclass 15, count 0 2006.183.07:59:01.88#ibcon#*mode == 0, iclass 15, count 0 2006.183.07:59:01.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.07:59:01.88#ibcon#[27=USB\r\n] 2006.183.07:59:01.88#ibcon#*before write, iclass 15, count 0 2006.183.07:59:01.88#ibcon#enter sib2, iclass 15, count 0 2006.183.07:59:01.88#ibcon#flushed, iclass 15, count 0 2006.183.07:59:01.88#ibcon#about to write, iclass 15, count 0 2006.183.07:59:01.88#ibcon#wrote, iclass 15, count 0 2006.183.07:59:01.88#ibcon#about to read 3, iclass 15, count 0 2006.183.07:59:01.91#ibcon#read 3, iclass 15, count 0 2006.183.07:59:01.91#ibcon#about to read 4, iclass 15, count 0 2006.183.07:59:01.91#ibcon#read 4, iclass 15, count 0 2006.183.07:59:01.91#ibcon#about to read 5, iclass 15, count 0 2006.183.07:59:01.91#ibcon#read 5, iclass 15, count 0 2006.183.07:59:01.91#ibcon#about to read 6, iclass 15, count 0 2006.183.07:59:01.91#ibcon#read 6, iclass 15, count 0 2006.183.07:59:01.91#ibcon#end of sib2, iclass 15, count 0 2006.183.07:59:01.91#ibcon#*after write, iclass 15, count 0 2006.183.07:59:01.91#ibcon#*before return 0, iclass 15, count 0 2006.183.07:59:01.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:59:01.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.07:59:01.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.07:59:01.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.07:59:01.91$vc4f8/vblo=5,744.99 2006.183.07:59:01.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.07:59:01.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.07:59:01.91#ibcon#ireg 17 cls_cnt 0 2006.183.07:59:01.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:59:01.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:59:01.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:59:01.91#ibcon#enter wrdev, iclass 17, count 0 2006.183.07:59:01.91#ibcon#first serial, iclass 17, count 0 2006.183.07:59:01.91#ibcon#enter sib2, iclass 17, count 0 2006.183.07:59:01.91#ibcon#flushed, iclass 17, count 0 2006.183.07:59:01.91#ibcon#about to write, iclass 17, count 0 2006.183.07:59:01.91#ibcon#wrote, iclass 17, count 0 2006.183.07:59:01.91#ibcon#about to read 3, iclass 17, count 0 2006.183.07:59:01.93#ibcon#read 3, iclass 17, count 0 2006.183.07:59:01.93#ibcon#about to read 4, iclass 17, count 0 2006.183.07:59:01.93#ibcon#read 4, iclass 17, count 0 2006.183.07:59:01.93#ibcon#about to read 5, iclass 17, count 0 2006.183.07:59:01.93#ibcon#read 5, iclass 17, count 0 2006.183.07:59:01.93#ibcon#about to read 6, iclass 17, count 0 2006.183.07:59:01.93#ibcon#read 6, iclass 17, count 0 2006.183.07:59:01.93#ibcon#end of sib2, iclass 17, count 0 2006.183.07:59:01.93#ibcon#*mode == 0, iclass 17, count 0 2006.183.07:59:01.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.07:59:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.07:59:01.93#ibcon#*before write, iclass 17, count 0 2006.183.07:59:01.93#ibcon#enter sib2, iclass 17, count 0 2006.183.07:59:01.93#ibcon#flushed, iclass 17, count 0 2006.183.07:59:01.93#ibcon#about to write, iclass 17, count 0 2006.183.07:59:01.93#ibcon#wrote, iclass 17, count 0 2006.183.07:59:01.93#ibcon#about to read 3, iclass 17, count 0 2006.183.07:59:01.97#ibcon#read 3, iclass 17, count 0 2006.183.07:59:01.97#ibcon#about to read 4, iclass 17, count 0 2006.183.07:59:01.97#ibcon#read 4, iclass 17, count 0 2006.183.07:59:01.97#ibcon#about to read 5, iclass 17, count 0 2006.183.07:59:01.97#ibcon#read 5, iclass 17, count 0 2006.183.07:59:01.97#ibcon#about to read 6, iclass 17, count 0 2006.183.07:59:01.97#ibcon#read 6, iclass 17, count 0 2006.183.07:59:01.97#ibcon#end of sib2, iclass 17, count 0 2006.183.07:59:01.97#ibcon#*after write, iclass 17, count 0 2006.183.07:59:01.97#ibcon#*before return 0, iclass 17, count 0 2006.183.07:59:01.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:59:01.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.07:59:01.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.07:59:01.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.07:59:01.97$vc4f8/vb=5,4 2006.183.07:59:01.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.07:59:01.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.07:59:01.97#ibcon#ireg 11 cls_cnt 2 2006.183.07:59:01.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:59:02.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:59:02.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:59:02.03#ibcon#enter wrdev, iclass 19, count 2 2006.183.07:59:02.03#ibcon#first serial, iclass 19, count 2 2006.183.07:59:02.03#ibcon#enter sib2, iclass 19, count 2 2006.183.07:59:02.03#ibcon#flushed, iclass 19, count 2 2006.183.07:59:02.03#ibcon#about to write, iclass 19, count 2 2006.183.07:59:02.03#ibcon#wrote, iclass 19, count 2 2006.183.07:59:02.03#ibcon#about to read 3, iclass 19, count 2 2006.183.07:59:02.05#ibcon#read 3, iclass 19, count 2 2006.183.07:59:02.05#ibcon#about to read 4, iclass 19, count 2 2006.183.07:59:02.05#ibcon#read 4, iclass 19, count 2 2006.183.07:59:02.05#ibcon#about to read 5, iclass 19, count 2 2006.183.07:59:02.05#ibcon#read 5, iclass 19, count 2 2006.183.07:59:02.05#ibcon#about to read 6, iclass 19, count 2 2006.183.07:59:02.05#ibcon#read 6, iclass 19, count 2 2006.183.07:59:02.05#ibcon#end of sib2, iclass 19, count 2 2006.183.07:59:02.05#ibcon#*mode == 0, iclass 19, count 2 2006.183.07:59:02.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.07:59:02.05#ibcon#[27=AT05-04\r\n] 2006.183.07:59:02.05#ibcon#*before write, iclass 19, count 2 2006.183.07:59:02.05#ibcon#enter sib2, iclass 19, count 2 2006.183.07:59:02.05#ibcon#flushed, iclass 19, count 2 2006.183.07:59:02.05#ibcon#about to write, iclass 19, count 2 2006.183.07:59:02.05#ibcon#wrote, iclass 19, count 2 2006.183.07:59:02.05#ibcon#about to read 3, iclass 19, count 2 2006.183.07:59:02.08#ibcon#read 3, iclass 19, count 2 2006.183.07:59:02.08#ibcon#about to read 4, iclass 19, count 2 2006.183.07:59:02.08#ibcon#read 4, iclass 19, count 2 2006.183.07:59:02.08#ibcon#about to read 5, iclass 19, count 2 2006.183.07:59:02.08#ibcon#read 5, iclass 19, count 2 2006.183.07:59:02.08#ibcon#about to read 6, iclass 19, count 2 2006.183.07:59:02.08#ibcon#read 6, iclass 19, count 2 2006.183.07:59:02.08#ibcon#end of sib2, iclass 19, count 2 2006.183.07:59:02.08#ibcon#*after write, iclass 19, count 2 2006.183.07:59:02.08#ibcon#*before return 0, iclass 19, count 2 2006.183.07:59:02.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:59:02.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.07:59:02.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.07:59:02.08#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:02.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:59:02.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:59:02.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:59:02.20#ibcon#enter wrdev, iclass 19, count 0 2006.183.07:59:02.20#ibcon#first serial, iclass 19, count 0 2006.183.07:59:02.20#ibcon#enter sib2, iclass 19, count 0 2006.183.07:59:02.20#ibcon#flushed, iclass 19, count 0 2006.183.07:59:02.20#ibcon#about to write, iclass 19, count 0 2006.183.07:59:02.20#ibcon#wrote, iclass 19, count 0 2006.183.07:59:02.20#ibcon#about to read 3, iclass 19, count 0 2006.183.07:59:02.22#ibcon#read 3, iclass 19, count 0 2006.183.07:59:02.22#ibcon#about to read 4, iclass 19, count 0 2006.183.07:59:02.22#ibcon#read 4, iclass 19, count 0 2006.183.07:59:02.22#ibcon#about to read 5, iclass 19, count 0 2006.183.07:59:02.22#ibcon#read 5, iclass 19, count 0 2006.183.07:59:02.22#ibcon#about to read 6, iclass 19, count 0 2006.183.07:59:02.22#ibcon#read 6, iclass 19, count 0 2006.183.07:59:02.22#ibcon#end of sib2, iclass 19, count 0 2006.183.07:59:02.22#ibcon#*mode == 0, iclass 19, count 0 2006.183.07:59:02.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.07:59:02.22#ibcon#[27=USB\r\n] 2006.183.07:59:02.22#ibcon#*before write, iclass 19, count 0 2006.183.07:59:02.22#ibcon#enter sib2, iclass 19, count 0 2006.183.07:59:02.22#ibcon#flushed, iclass 19, count 0 2006.183.07:59:02.22#ibcon#about to write, iclass 19, count 0 2006.183.07:59:02.22#ibcon#wrote, iclass 19, count 0 2006.183.07:59:02.22#ibcon#about to read 3, iclass 19, count 0 2006.183.07:59:02.25#ibcon#read 3, iclass 19, count 0 2006.183.07:59:02.25#ibcon#about to read 4, iclass 19, count 0 2006.183.07:59:02.25#ibcon#read 4, iclass 19, count 0 2006.183.07:59:02.25#ibcon#about to read 5, iclass 19, count 0 2006.183.07:59:02.25#ibcon#read 5, iclass 19, count 0 2006.183.07:59:02.25#ibcon#about to read 6, iclass 19, count 0 2006.183.07:59:02.25#ibcon#read 6, iclass 19, count 0 2006.183.07:59:02.25#ibcon#end of sib2, iclass 19, count 0 2006.183.07:59:02.25#ibcon#*after write, iclass 19, count 0 2006.183.07:59:02.25#ibcon#*before return 0, iclass 19, count 0 2006.183.07:59:02.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:59:02.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.07:59:02.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.07:59:02.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.07:59:02.25$vc4f8/vblo=6,752.99 2006.183.07:59:02.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.07:59:02.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.07:59:02.25#ibcon#ireg 17 cls_cnt 0 2006.183.07:59:02.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:59:02.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:59:02.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:59:02.25#ibcon#enter wrdev, iclass 21, count 0 2006.183.07:59:02.25#ibcon#first serial, iclass 21, count 0 2006.183.07:59:02.25#ibcon#enter sib2, iclass 21, count 0 2006.183.07:59:02.25#ibcon#flushed, iclass 21, count 0 2006.183.07:59:02.25#ibcon#about to write, iclass 21, count 0 2006.183.07:59:02.25#ibcon#wrote, iclass 21, count 0 2006.183.07:59:02.25#ibcon#about to read 3, iclass 21, count 0 2006.183.07:59:02.27#ibcon#read 3, iclass 21, count 0 2006.183.07:59:02.27#ibcon#about to read 4, iclass 21, count 0 2006.183.07:59:02.27#ibcon#read 4, iclass 21, count 0 2006.183.07:59:02.27#ibcon#about to read 5, iclass 21, count 0 2006.183.07:59:02.27#ibcon#read 5, iclass 21, count 0 2006.183.07:59:02.27#ibcon#about to read 6, iclass 21, count 0 2006.183.07:59:02.27#ibcon#read 6, iclass 21, count 0 2006.183.07:59:02.27#ibcon#end of sib2, iclass 21, count 0 2006.183.07:59:02.27#ibcon#*mode == 0, iclass 21, count 0 2006.183.07:59:02.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.07:59:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.07:59:02.27#ibcon#*before write, iclass 21, count 0 2006.183.07:59:02.27#ibcon#enter sib2, iclass 21, count 0 2006.183.07:59:02.27#ibcon#flushed, iclass 21, count 0 2006.183.07:59:02.27#ibcon#about to write, iclass 21, count 0 2006.183.07:59:02.27#ibcon#wrote, iclass 21, count 0 2006.183.07:59:02.27#ibcon#about to read 3, iclass 21, count 0 2006.183.07:59:02.31#ibcon#read 3, iclass 21, count 0 2006.183.07:59:02.31#ibcon#about to read 4, iclass 21, count 0 2006.183.07:59:02.31#ibcon#read 4, iclass 21, count 0 2006.183.07:59:02.31#ibcon#about to read 5, iclass 21, count 0 2006.183.07:59:02.31#ibcon#read 5, iclass 21, count 0 2006.183.07:59:02.31#ibcon#about to read 6, iclass 21, count 0 2006.183.07:59:02.31#ibcon#read 6, iclass 21, count 0 2006.183.07:59:02.31#ibcon#end of sib2, iclass 21, count 0 2006.183.07:59:02.31#ibcon#*after write, iclass 21, count 0 2006.183.07:59:02.31#ibcon#*before return 0, iclass 21, count 0 2006.183.07:59:02.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:59:02.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.07:59:02.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.07:59:02.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.07:59:02.31$vc4f8/vb=6,4 2006.183.07:59:02.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.07:59:02.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.07:59:02.31#ibcon#ireg 11 cls_cnt 2 2006.183.07:59:02.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:59:02.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:59:02.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:59:02.37#ibcon#enter wrdev, iclass 23, count 2 2006.183.07:59:02.37#ibcon#first serial, iclass 23, count 2 2006.183.07:59:02.37#ibcon#enter sib2, iclass 23, count 2 2006.183.07:59:02.37#ibcon#flushed, iclass 23, count 2 2006.183.07:59:02.37#ibcon#about to write, iclass 23, count 2 2006.183.07:59:02.37#ibcon#wrote, iclass 23, count 2 2006.183.07:59:02.37#ibcon#about to read 3, iclass 23, count 2 2006.183.07:59:02.39#ibcon#read 3, iclass 23, count 2 2006.183.07:59:02.39#ibcon#about to read 4, iclass 23, count 2 2006.183.07:59:02.39#ibcon#read 4, iclass 23, count 2 2006.183.07:59:02.39#ibcon#about to read 5, iclass 23, count 2 2006.183.07:59:02.39#ibcon#read 5, iclass 23, count 2 2006.183.07:59:02.39#ibcon#about to read 6, iclass 23, count 2 2006.183.07:59:02.39#ibcon#read 6, iclass 23, count 2 2006.183.07:59:02.39#ibcon#end of sib2, iclass 23, count 2 2006.183.07:59:02.39#ibcon#*mode == 0, iclass 23, count 2 2006.183.07:59:02.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.07:59:02.39#ibcon#[27=AT06-04\r\n] 2006.183.07:59:02.39#ibcon#*before write, iclass 23, count 2 2006.183.07:59:02.39#ibcon#enter sib2, iclass 23, count 2 2006.183.07:59:02.39#ibcon#flushed, iclass 23, count 2 2006.183.07:59:02.39#ibcon#about to write, iclass 23, count 2 2006.183.07:59:02.39#ibcon#wrote, iclass 23, count 2 2006.183.07:59:02.39#ibcon#about to read 3, iclass 23, count 2 2006.183.07:59:02.42#ibcon#read 3, iclass 23, count 2 2006.183.07:59:02.42#ibcon#about to read 4, iclass 23, count 2 2006.183.07:59:02.42#ibcon#read 4, iclass 23, count 2 2006.183.07:59:02.42#ibcon#about to read 5, iclass 23, count 2 2006.183.07:59:02.42#ibcon#read 5, iclass 23, count 2 2006.183.07:59:02.42#ibcon#about to read 6, iclass 23, count 2 2006.183.07:59:02.42#ibcon#read 6, iclass 23, count 2 2006.183.07:59:02.42#ibcon#end of sib2, iclass 23, count 2 2006.183.07:59:02.42#ibcon#*after write, iclass 23, count 2 2006.183.07:59:02.42#ibcon#*before return 0, iclass 23, count 2 2006.183.07:59:02.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:59:02.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.07:59:02.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.07:59:02.42#ibcon#ireg 7 cls_cnt 0 2006.183.07:59:02.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:59:02.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:59:02.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:59:02.54#ibcon#enter wrdev, iclass 23, count 0 2006.183.07:59:02.54#ibcon#first serial, iclass 23, count 0 2006.183.07:59:02.54#ibcon#enter sib2, iclass 23, count 0 2006.183.07:59:02.54#ibcon#flushed, iclass 23, count 0 2006.183.07:59:02.54#ibcon#about to write, iclass 23, count 0 2006.183.07:59:02.54#ibcon#wrote, iclass 23, count 0 2006.183.07:59:02.54#ibcon#about to read 3, iclass 23, count 0 2006.183.07:59:02.56#ibcon#read 3, iclass 23, count 0 2006.183.07:59:02.56#ibcon#about to read 4, iclass 23, count 0 2006.183.07:59:02.56#ibcon#read 4, iclass 23, count 0 2006.183.07:59:02.56#ibcon#about to read 5, iclass 23, count 0 2006.183.07:59:02.56#ibcon#read 5, iclass 23, count 0 2006.183.07:59:02.56#ibcon#about to read 6, iclass 23, count 0 2006.183.07:59:02.56#ibcon#read 6, iclass 23, count 0 2006.183.07:59:02.56#ibcon#end of sib2, iclass 23, count 0 2006.183.07:59:02.56#ibcon#*mode == 0, iclass 23, count 0 2006.183.07:59:02.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.07:59:02.56#ibcon#[27=USB\r\n] 2006.183.07:59:02.56#ibcon#*before write, iclass 23, count 0 2006.183.07:59:02.56#ibcon#enter sib2, iclass 23, count 0 2006.183.07:59:02.56#ibcon#flushed, iclass 23, count 0 2006.183.07:59:02.56#ibcon#about to write, iclass 23, count 0 2006.183.07:59:02.56#ibcon#wrote, iclass 23, count 0 2006.183.07:59:02.56#ibcon#about to read 3, iclass 23, count 0 2006.183.07:59:02.59#ibcon#read 3, iclass 23, count 0 2006.183.07:59:02.59#ibcon#about to read 4, iclass 23, count 0 2006.183.07:59:02.59#ibcon#read 4, iclass 23, count 0 2006.183.07:59:02.59#ibcon#about to read 5, iclass 23, count 0 2006.183.07:59:02.59#ibcon#read 5, iclass 23, count 0 2006.183.07:59:02.59#ibcon#about to read 6, iclass 23, count 0 2006.183.07:59:02.59#ibcon#read 6, iclass 23, count 0 2006.183.07:59:02.59#ibcon#end of sib2, iclass 23, count 0 2006.183.07:59:02.59#ibcon#*after write, iclass 23, count 0 2006.183.07:59:02.59#ibcon#*before return 0, iclass 23, count 0 2006.183.07:59:02.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:59:02.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.07:59:02.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.07:59:02.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.07:59:02.59$vc4f8/vabw=wide 2006.183.07:59:02.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.07:59:02.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.07:59:02.59#ibcon#ireg 8 cls_cnt 0 2006.183.07:59:02.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:59:02.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:59:02.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:59:02.59#ibcon#enter wrdev, iclass 25, count 0 2006.183.07:59:02.59#ibcon#first serial, iclass 25, count 0 2006.183.07:59:02.59#ibcon#enter sib2, iclass 25, count 0 2006.183.07:59:02.59#ibcon#flushed, iclass 25, count 0 2006.183.07:59:02.59#ibcon#about to write, iclass 25, count 0 2006.183.07:59:02.59#ibcon#wrote, iclass 25, count 0 2006.183.07:59:02.59#ibcon#about to read 3, iclass 25, count 0 2006.183.07:59:02.61#ibcon#read 3, iclass 25, count 0 2006.183.07:59:02.61#ibcon#about to read 4, iclass 25, count 0 2006.183.07:59:02.61#ibcon#read 4, iclass 25, count 0 2006.183.07:59:02.61#ibcon#about to read 5, iclass 25, count 0 2006.183.07:59:02.61#ibcon#read 5, iclass 25, count 0 2006.183.07:59:02.61#ibcon#about to read 6, iclass 25, count 0 2006.183.07:59:02.61#ibcon#read 6, iclass 25, count 0 2006.183.07:59:02.61#ibcon#end of sib2, iclass 25, count 0 2006.183.07:59:02.61#ibcon#*mode == 0, iclass 25, count 0 2006.183.07:59:02.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.07:59:02.61#ibcon#[25=BW32\r\n] 2006.183.07:59:02.61#ibcon#*before write, iclass 25, count 0 2006.183.07:59:02.61#ibcon#enter sib2, iclass 25, count 0 2006.183.07:59:02.61#ibcon#flushed, iclass 25, count 0 2006.183.07:59:02.61#ibcon#about to write, iclass 25, count 0 2006.183.07:59:02.61#ibcon#wrote, iclass 25, count 0 2006.183.07:59:02.61#ibcon#about to read 3, iclass 25, count 0 2006.183.07:59:02.64#ibcon#read 3, iclass 25, count 0 2006.183.07:59:02.64#ibcon#about to read 4, iclass 25, count 0 2006.183.07:59:02.64#ibcon#read 4, iclass 25, count 0 2006.183.07:59:02.64#ibcon#about to read 5, iclass 25, count 0 2006.183.07:59:02.64#ibcon#read 5, iclass 25, count 0 2006.183.07:59:02.64#ibcon#about to read 6, iclass 25, count 0 2006.183.07:59:02.64#ibcon#read 6, iclass 25, count 0 2006.183.07:59:02.64#ibcon#end of sib2, iclass 25, count 0 2006.183.07:59:02.64#ibcon#*after write, iclass 25, count 0 2006.183.07:59:02.64#ibcon#*before return 0, iclass 25, count 0 2006.183.07:59:02.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:59:02.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.07:59:02.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.07:59:02.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.07:59:02.64$vc4f8/vbbw=wide 2006.183.07:59:02.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.07:59:02.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.07:59:02.64#ibcon#ireg 8 cls_cnt 0 2006.183.07:59:02.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:59:02.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:59:02.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:59:02.71#ibcon#enter wrdev, iclass 27, count 0 2006.183.07:59:02.71#ibcon#first serial, iclass 27, count 0 2006.183.07:59:02.71#ibcon#enter sib2, iclass 27, count 0 2006.183.07:59:02.71#ibcon#flushed, iclass 27, count 0 2006.183.07:59:02.71#ibcon#about to write, iclass 27, count 0 2006.183.07:59:02.71#ibcon#wrote, iclass 27, count 0 2006.183.07:59:02.71#ibcon#about to read 3, iclass 27, count 0 2006.183.07:59:02.73#ibcon#read 3, iclass 27, count 0 2006.183.07:59:02.73#ibcon#about to read 4, iclass 27, count 0 2006.183.07:59:02.73#ibcon#read 4, iclass 27, count 0 2006.183.07:59:02.73#ibcon#about to read 5, iclass 27, count 0 2006.183.07:59:02.73#ibcon#read 5, iclass 27, count 0 2006.183.07:59:02.73#ibcon#about to read 6, iclass 27, count 0 2006.183.07:59:02.73#ibcon#read 6, iclass 27, count 0 2006.183.07:59:02.73#ibcon#end of sib2, iclass 27, count 0 2006.183.07:59:02.73#ibcon#*mode == 0, iclass 27, count 0 2006.183.07:59:02.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.07:59:02.73#ibcon#[27=BW32\r\n] 2006.183.07:59:02.73#ibcon#*before write, iclass 27, count 0 2006.183.07:59:02.73#ibcon#enter sib2, iclass 27, count 0 2006.183.07:59:02.73#ibcon#flushed, iclass 27, count 0 2006.183.07:59:02.73#ibcon#about to write, iclass 27, count 0 2006.183.07:59:02.73#ibcon#wrote, iclass 27, count 0 2006.183.07:59:02.73#ibcon#about to read 3, iclass 27, count 0 2006.183.07:59:02.76#ibcon#read 3, iclass 27, count 0 2006.183.07:59:02.76#ibcon#about to read 4, iclass 27, count 0 2006.183.07:59:02.76#ibcon#read 4, iclass 27, count 0 2006.183.07:59:02.76#ibcon#about to read 5, iclass 27, count 0 2006.183.07:59:02.76#ibcon#read 5, iclass 27, count 0 2006.183.07:59:02.76#ibcon#about to read 6, iclass 27, count 0 2006.183.07:59:02.76#ibcon#read 6, iclass 27, count 0 2006.183.07:59:02.76#ibcon#end of sib2, iclass 27, count 0 2006.183.07:59:02.76#ibcon#*after write, iclass 27, count 0 2006.183.07:59:02.76#ibcon#*before return 0, iclass 27, count 0 2006.183.07:59:02.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:59:02.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.07:59:02.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.07:59:02.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.07:59:02.76$4f8m12a/ifd4f 2006.183.07:59:02.76$ifd4f/lo= 2006.183.07:59:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.07:59:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.07:59:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.07:59:02.76$ifd4f/patch= 2006.183.07:59:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.07:59:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.07:59:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.07:59:02.76$4f8m12a/"form=m,16.000,1:2 2006.183.07:59:02.76$4f8m12a/"tpicd 2006.183.07:59:02.76$4f8m12a/echo=off 2006.183.07:59:02.76$4f8m12a/xlog=off 2006.183.07:59:02.76:!2006.183.07:59:30 2006.183.07:59:15.13#trakl#Source acquired 2006.183.07:59:15.13#flagr#flagr/antenna,acquired 2006.183.07:59:30.00:preob 2006.183.07:59:31.13/onsource/TRACKING 2006.183.07:59:31.13:!2006.183.07:59:40 2006.183.07:59:40.00:data_valid=on 2006.183.07:59:40.00:midob 2006.183.07:59:40.13/onsource/TRACKING 2006.183.07:59:40.13/wx/28.11,996.3,86 2006.183.07:59:40.20/cable/+6.4532E-03 2006.183.07:59:41.30/va/01,08,usb,yes,29,31 2006.183.07:59:41.30/va/02,07,usb,yes,30,31 2006.183.07:59:41.30/va/03,06,usb,yes,31,31 2006.183.07:59:41.30/va/04,07,usb,yes,30,33 2006.183.07:59:41.30/va/05,07,usb,yes,32,34 2006.183.07:59:41.30/va/06,06,usb,yes,31,31 2006.183.07:59:41.30/va/07,06,usb,yes,32,31 2006.183.07:59:41.30/va/08,07,usb,yes,30,29 2006.183.07:59:41.53/valo/01,532.99,yes,locked 2006.183.07:59:41.53/valo/02,572.99,yes,locked 2006.183.07:59:41.53/valo/03,672.99,yes,locked 2006.183.07:59:41.53/valo/04,832.99,yes,locked 2006.183.07:59:41.53/valo/05,652.99,yes,locked 2006.183.07:59:41.53/valo/06,772.99,yes,locked 2006.183.07:59:41.53/valo/07,832.99,yes,locked 2006.183.07:59:41.53/valo/08,852.99,yes,locked 2006.183.07:59:42.62/vb/01,04,usb,yes,30,28 2006.183.07:59:42.62/vb/02,04,usb,yes,31,33 2006.183.07:59:42.62/vb/03,04,usb,yes,27,31 2006.183.07:59:42.62/vb/04,04,usb,yes,28,28 2006.183.07:59:42.62/vb/05,04,usb,yes,27,31 2006.183.07:59:42.62/vb/06,04,usb,yes,28,31 2006.183.07:59:42.62/vb/07,04,usb,yes,30,30 2006.183.07:59:42.62/vb/08,04,usb,yes,27,31 2006.183.07:59:42.85/vblo/01,632.99,yes,locked 2006.183.07:59:42.85/vblo/02,640.99,yes,locked 2006.183.07:59:42.85/vblo/03,656.99,yes,locked 2006.183.07:59:42.85/vblo/04,712.99,yes,locked 2006.183.07:59:42.85/vblo/05,744.99,yes,locked 2006.183.07:59:42.85/vblo/06,752.99,yes,locked 2006.183.07:59:42.85/vblo/07,734.99,yes,locked 2006.183.07:59:42.85/vblo/08,744.99,yes,locked 2006.183.07:59:43.00/vabw/8 2006.183.07:59:43.15/vbbw/8 2006.183.07:59:43.33/xfe/off,on,15.5 2006.183.07:59:43.71/ifatt/23,28,28,28 2006.183.07:59:44.08/fmout-gps/S +3.31E-07 2006.183.07:59:44.12:!2006.183.08:00:40 2006.183.08:00:40.00:data_valid=off 2006.183.08:00:40.00:postob 2006.183.08:00:40.08/cable/+6.4516E-03 2006.183.08:00:40.09/wx/28.14,996.3,87 2006.183.08:00:41.08/fmout-gps/S +3.32E-07 2006.183.08:00:41.08:scan_name=183-0802,k06183,60 2006.183.08:00:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.183.08:00:41.14#flagr#flagr/antenna,new-source 2006.183.08:00:42.14:checkk5 2006.183.08:00:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:00:42.87/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:00:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:00:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:00:43.99/chk_obsdata//k5ts1/T1830759??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:00:44.37/chk_obsdata//k5ts2/T1830759??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:00:44.73/chk_obsdata//k5ts3/T1830759??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:00:45.11/chk_obsdata//k5ts4/T1830759??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:00:45.80/k5log//k5ts1_log_newline 2006.183.08:00:46.49/k5log//k5ts2_log_newline 2006.183.08:00:47.18/k5log//k5ts3_log_newline 2006.183.08:00:47.86/k5log//k5ts4_log_newline 2006.183.08:00:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:00:47.89:4f8m12a=2 2006.183.08:00:47.89$4f8m12a/echo=on 2006.183.08:00:47.89$4f8m12a/pcalon 2006.183.08:00:47.89$pcalon/"no phase cal control is implemented here 2006.183.08:00:47.89$4f8m12a/"tpicd=stop 2006.183.08:00:47.89$4f8m12a/vc4f8 2006.183.08:00:47.89$vc4f8/valo=1,532.99 2006.183.08:00:47.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.08:00:47.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.08:00:47.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:47.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:47.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:47.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:47.89#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:00:47.89#ibcon#first serial, iclass 34, count 0 2006.183.08:00:47.89#ibcon#enter sib2, iclass 34, count 0 2006.183.08:00:47.89#ibcon#flushed, iclass 34, count 0 2006.183.08:00:47.89#ibcon#about to write, iclass 34, count 0 2006.183.08:00:47.89#ibcon#wrote, iclass 34, count 0 2006.183.08:00:47.89#ibcon#about to read 3, iclass 34, count 0 2006.183.08:00:47.93#ibcon#read 3, iclass 34, count 0 2006.183.08:00:47.93#ibcon#about to read 4, iclass 34, count 0 2006.183.08:00:47.93#ibcon#read 4, iclass 34, count 0 2006.183.08:00:47.93#ibcon#about to read 5, iclass 34, count 0 2006.183.08:00:47.93#ibcon#read 5, iclass 34, count 0 2006.183.08:00:47.93#ibcon#about to read 6, iclass 34, count 0 2006.183.08:00:47.93#ibcon#read 6, iclass 34, count 0 2006.183.08:00:47.93#ibcon#end of sib2, iclass 34, count 0 2006.183.08:00:47.93#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:00:47.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:00:47.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:00:47.93#ibcon#*before write, iclass 34, count 0 2006.183.08:00:47.93#ibcon#enter sib2, iclass 34, count 0 2006.183.08:00:47.93#ibcon#flushed, iclass 34, count 0 2006.183.08:00:47.93#ibcon#about to write, iclass 34, count 0 2006.183.08:00:47.93#ibcon#wrote, iclass 34, count 0 2006.183.08:00:47.93#ibcon#about to read 3, iclass 34, count 0 2006.183.08:00:47.98#ibcon#read 3, iclass 34, count 0 2006.183.08:00:47.98#ibcon#about to read 4, iclass 34, count 0 2006.183.08:00:47.98#ibcon#read 4, iclass 34, count 0 2006.183.08:00:47.98#ibcon#about to read 5, iclass 34, count 0 2006.183.08:00:47.98#ibcon#read 5, iclass 34, count 0 2006.183.08:00:47.98#ibcon#about to read 6, iclass 34, count 0 2006.183.08:00:47.98#ibcon#read 6, iclass 34, count 0 2006.183.08:00:47.98#ibcon#end of sib2, iclass 34, count 0 2006.183.08:00:47.98#ibcon#*after write, iclass 34, count 0 2006.183.08:00:47.98#ibcon#*before return 0, iclass 34, count 0 2006.183.08:00:47.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:47.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:47.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:00:47.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:00:47.98$vc4f8/va=1,8 2006.183.08:00:47.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.08:00:47.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.08:00:47.98#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:47.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:47.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:47.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:47.98#ibcon#enter wrdev, iclass 36, count 2 2006.183.08:00:47.98#ibcon#first serial, iclass 36, count 2 2006.183.08:00:47.98#ibcon#enter sib2, iclass 36, count 2 2006.183.08:00:47.98#ibcon#flushed, iclass 36, count 2 2006.183.08:00:47.98#ibcon#about to write, iclass 36, count 2 2006.183.08:00:47.98#ibcon#wrote, iclass 36, count 2 2006.183.08:00:47.98#ibcon#about to read 3, iclass 36, count 2 2006.183.08:00:48.00#ibcon#read 3, iclass 36, count 2 2006.183.08:00:48.00#ibcon#about to read 4, iclass 36, count 2 2006.183.08:00:48.00#ibcon#read 4, iclass 36, count 2 2006.183.08:00:48.00#ibcon#about to read 5, iclass 36, count 2 2006.183.08:00:48.00#ibcon#read 5, iclass 36, count 2 2006.183.08:00:48.00#ibcon#about to read 6, iclass 36, count 2 2006.183.08:00:48.00#ibcon#read 6, iclass 36, count 2 2006.183.08:00:48.00#ibcon#end of sib2, iclass 36, count 2 2006.183.08:00:48.00#ibcon#*mode == 0, iclass 36, count 2 2006.183.08:00:48.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.08:00:48.00#ibcon#[25=AT01-08\r\n] 2006.183.08:00:48.00#ibcon#*before write, iclass 36, count 2 2006.183.08:00:48.00#ibcon#enter sib2, iclass 36, count 2 2006.183.08:00:48.00#ibcon#flushed, iclass 36, count 2 2006.183.08:00:48.00#ibcon#about to write, iclass 36, count 2 2006.183.08:00:48.00#ibcon#wrote, iclass 36, count 2 2006.183.08:00:48.00#ibcon#about to read 3, iclass 36, count 2 2006.183.08:00:48.03#ibcon#read 3, iclass 36, count 2 2006.183.08:00:48.03#ibcon#about to read 4, iclass 36, count 2 2006.183.08:00:48.03#ibcon#read 4, iclass 36, count 2 2006.183.08:00:48.03#ibcon#about to read 5, iclass 36, count 2 2006.183.08:00:48.03#ibcon#read 5, iclass 36, count 2 2006.183.08:00:48.03#ibcon#about to read 6, iclass 36, count 2 2006.183.08:00:48.03#ibcon#read 6, iclass 36, count 2 2006.183.08:00:48.03#ibcon#end of sib2, iclass 36, count 2 2006.183.08:00:48.03#ibcon#*after write, iclass 36, count 2 2006.183.08:00:48.03#ibcon#*before return 0, iclass 36, count 2 2006.183.08:00:48.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:48.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:48.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.08:00:48.03#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:48.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:48.15#abcon#<5=/09 1.4 7.0 28.15 87 996.3\r\n> 2006.183.08:00:48.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:48.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:48.15#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:00:48.15#ibcon#first serial, iclass 36, count 0 2006.183.08:00:48.15#ibcon#enter sib2, iclass 36, count 0 2006.183.08:00:48.15#ibcon#flushed, iclass 36, count 0 2006.183.08:00:48.15#ibcon#about to write, iclass 36, count 0 2006.183.08:00:48.15#ibcon#wrote, iclass 36, count 0 2006.183.08:00:48.15#ibcon#about to read 3, iclass 36, count 0 2006.183.08:00:48.17#ibcon#read 3, iclass 36, count 0 2006.183.08:00:48.17#ibcon#about to read 4, iclass 36, count 0 2006.183.08:00:48.17#ibcon#read 4, iclass 36, count 0 2006.183.08:00:48.17#ibcon#about to read 5, iclass 36, count 0 2006.183.08:00:48.17#ibcon#read 5, iclass 36, count 0 2006.183.08:00:48.17#ibcon#about to read 6, iclass 36, count 0 2006.183.08:00:48.17#ibcon#read 6, iclass 36, count 0 2006.183.08:00:48.17#ibcon#end of sib2, iclass 36, count 0 2006.183.08:00:48.17#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:00:48.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:00:48.17#ibcon#[25=USB\r\n] 2006.183.08:00:48.17#ibcon#*before write, iclass 36, count 0 2006.183.08:00:48.17#ibcon#enter sib2, iclass 36, count 0 2006.183.08:00:48.17#ibcon#flushed, iclass 36, count 0 2006.183.08:00:48.17#ibcon#about to write, iclass 36, count 0 2006.183.08:00:48.17#ibcon#wrote, iclass 36, count 0 2006.183.08:00:48.17#ibcon#about to read 3, iclass 36, count 0 2006.183.08:00:48.17#abcon#{5=INTERFACE CLEAR} 2006.183.08:00:48.20#ibcon#read 3, iclass 36, count 0 2006.183.08:00:48.20#ibcon#about to read 4, iclass 36, count 0 2006.183.08:00:48.20#ibcon#read 4, iclass 36, count 0 2006.183.08:00:48.20#ibcon#about to read 5, iclass 36, count 0 2006.183.08:00:48.20#ibcon#read 5, iclass 36, count 0 2006.183.08:00:48.20#ibcon#about to read 6, iclass 36, count 0 2006.183.08:00:48.20#ibcon#read 6, iclass 36, count 0 2006.183.08:00:48.20#ibcon#end of sib2, iclass 36, count 0 2006.183.08:00:48.20#ibcon#*after write, iclass 36, count 0 2006.183.08:00:48.20#ibcon#*before return 0, iclass 36, count 0 2006.183.08:00:48.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:48.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:48.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:00:48.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:00:48.20$vc4f8/valo=2,572.99 2006.183.08:00:48.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:00:48.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:00:48.20#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:48.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:00:48.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:00:48.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:00:48.20#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:00:48.20#ibcon#first serial, iclass 3, count 0 2006.183.08:00:48.20#ibcon#enter sib2, iclass 3, count 0 2006.183.08:00:48.20#ibcon#flushed, iclass 3, count 0 2006.183.08:00:48.20#ibcon#about to write, iclass 3, count 0 2006.183.08:00:48.20#ibcon#wrote, iclass 3, count 0 2006.183.08:00:48.20#ibcon#about to read 3, iclass 3, count 0 2006.183.08:00:48.22#ibcon#read 3, iclass 3, count 0 2006.183.08:00:48.22#ibcon#about to read 4, iclass 3, count 0 2006.183.08:00:48.22#ibcon#read 4, iclass 3, count 0 2006.183.08:00:48.22#ibcon#about to read 5, iclass 3, count 0 2006.183.08:00:48.22#ibcon#read 5, iclass 3, count 0 2006.183.08:00:48.22#ibcon#about to read 6, iclass 3, count 0 2006.183.08:00:48.22#ibcon#read 6, iclass 3, count 0 2006.183.08:00:48.22#ibcon#end of sib2, iclass 3, count 0 2006.183.08:00:48.22#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:00:48.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:00:48.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:00:48.22#ibcon#*before write, iclass 3, count 0 2006.183.08:00:48.22#ibcon#enter sib2, iclass 3, count 0 2006.183.08:00:48.22#ibcon#flushed, iclass 3, count 0 2006.183.08:00:48.22#ibcon#about to write, iclass 3, count 0 2006.183.08:00:48.22#ibcon#wrote, iclass 3, count 0 2006.183.08:00:48.22#ibcon#about to read 3, iclass 3, count 0 2006.183.08:00:48.23#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:00:48.26#ibcon#read 3, iclass 3, count 0 2006.183.08:00:48.26#ibcon#about to read 4, iclass 3, count 0 2006.183.08:00:48.26#ibcon#read 4, iclass 3, count 0 2006.183.08:00:48.26#ibcon#about to read 5, iclass 3, count 0 2006.183.08:00:48.26#ibcon#read 5, iclass 3, count 0 2006.183.08:00:48.26#ibcon#about to read 6, iclass 3, count 0 2006.183.08:00:48.26#ibcon#read 6, iclass 3, count 0 2006.183.08:00:48.26#ibcon#end of sib2, iclass 3, count 0 2006.183.08:00:48.26#ibcon#*after write, iclass 3, count 0 2006.183.08:00:48.26#ibcon#*before return 0, iclass 3, count 0 2006.183.08:00:48.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:00:48.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:00:48.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:00:48.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:00:48.26$vc4f8/va=2,7 2006.183.08:00:48.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.08:00:48.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.08:00:48.26#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:48.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:48.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:48.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:48.32#ibcon#enter wrdev, iclass 6, count 2 2006.183.08:00:48.32#ibcon#first serial, iclass 6, count 2 2006.183.08:00:48.32#ibcon#enter sib2, iclass 6, count 2 2006.183.08:00:48.32#ibcon#flushed, iclass 6, count 2 2006.183.08:00:48.32#ibcon#about to write, iclass 6, count 2 2006.183.08:00:48.32#ibcon#wrote, iclass 6, count 2 2006.183.08:00:48.32#ibcon#about to read 3, iclass 6, count 2 2006.183.08:00:48.34#ibcon#read 3, iclass 6, count 2 2006.183.08:00:48.34#ibcon#about to read 4, iclass 6, count 2 2006.183.08:00:48.34#ibcon#read 4, iclass 6, count 2 2006.183.08:00:48.34#ibcon#about to read 5, iclass 6, count 2 2006.183.08:00:48.34#ibcon#read 5, iclass 6, count 2 2006.183.08:00:48.34#ibcon#about to read 6, iclass 6, count 2 2006.183.08:00:48.34#ibcon#read 6, iclass 6, count 2 2006.183.08:00:48.34#ibcon#end of sib2, iclass 6, count 2 2006.183.08:00:48.34#ibcon#*mode == 0, iclass 6, count 2 2006.183.08:00:48.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.08:00:48.34#ibcon#[25=AT02-07\r\n] 2006.183.08:00:48.34#ibcon#*before write, iclass 6, count 2 2006.183.08:00:48.34#ibcon#enter sib2, iclass 6, count 2 2006.183.08:00:48.34#ibcon#flushed, iclass 6, count 2 2006.183.08:00:48.34#ibcon#about to write, iclass 6, count 2 2006.183.08:00:48.34#ibcon#wrote, iclass 6, count 2 2006.183.08:00:48.34#ibcon#about to read 3, iclass 6, count 2 2006.183.08:00:48.37#ibcon#read 3, iclass 6, count 2 2006.183.08:00:48.37#ibcon#about to read 4, iclass 6, count 2 2006.183.08:00:48.37#ibcon#read 4, iclass 6, count 2 2006.183.08:00:48.37#ibcon#about to read 5, iclass 6, count 2 2006.183.08:00:48.37#ibcon#read 5, iclass 6, count 2 2006.183.08:00:48.37#ibcon#about to read 6, iclass 6, count 2 2006.183.08:00:48.37#ibcon#read 6, iclass 6, count 2 2006.183.08:00:48.37#ibcon#end of sib2, iclass 6, count 2 2006.183.08:00:48.37#ibcon#*after write, iclass 6, count 2 2006.183.08:00:48.37#ibcon#*before return 0, iclass 6, count 2 2006.183.08:00:48.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:48.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:48.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.08:00:48.37#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:48.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:48.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:48.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:48.49#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:00:48.49#ibcon#first serial, iclass 6, count 0 2006.183.08:00:48.49#ibcon#enter sib2, iclass 6, count 0 2006.183.08:00:48.49#ibcon#flushed, iclass 6, count 0 2006.183.08:00:48.49#ibcon#about to write, iclass 6, count 0 2006.183.08:00:48.49#ibcon#wrote, iclass 6, count 0 2006.183.08:00:48.49#ibcon#about to read 3, iclass 6, count 0 2006.183.08:00:48.51#ibcon#read 3, iclass 6, count 0 2006.183.08:00:48.51#ibcon#about to read 4, iclass 6, count 0 2006.183.08:00:48.51#ibcon#read 4, iclass 6, count 0 2006.183.08:00:48.51#ibcon#about to read 5, iclass 6, count 0 2006.183.08:00:48.51#ibcon#read 5, iclass 6, count 0 2006.183.08:00:48.51#ibcon#about to read 6, iclass 6, count 0 2006.183.08:00:48.51#ibcon#read 6, iclass 6, count 0 2006.183.08:00:48.51#ibcon#end of sib2, iclass 6, count 0 2006.183.08:00:48.51#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:00:48.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:00:48.51#ibcon#[25=USB\r\n] 2006.183.08:00:48.51#ibcon#*before write, iclass 6, count 0 2006.183.08:00:48.51#ibcon#enter sib2, iclass 6, count 0 2006.183.08:00:48.51#ibcon#flushed, iclass 6, count 0 2006.183.08:00:48.51#ibcon#about to write, iclass 6, count 0 2006.183.08:00:48.51#ibcon#wrote, iclass 6, count 0 2006.183.08:00:48.51#ibcon#about to read 3, iclass 6, count 0 2006.183.08:00:48.54#ibcon#read 3, iclass 6, count 0 2006.183.08:00:48.54#ibcon#about to read 4, iclass 6, count 0 2006.183.08:00:48.54#ibcon#read 4, iclass 6, count 0 2006.183.08:00:48.54#ibcon#about to read 5, iclass 6, count 0 2006.183.08:00:48.54#ibcon#read 5, iclass 6, count 0 2006.183.08:00:48.54#ibcon#about to read 6, iclass 6, count 0 2006.183.08:00:48.54#ibcon#read 6, iclass 6, count 0 2006.183.08:00:48.54#ibcon#end of sib2, iclass 6, count 0 2006.183.08:00:48.54#ibcon#*after write, iclass 6, count 0 2006.183.08:00:48.54#ibcon#*before return 0, iclass 6, count 0 2006.183.08:00:48.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:48.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:48.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:00:48.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:00:48.54$vc4f8/valo=3,672.99 2006.183.08:00:48.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.08:00:48.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.08:00:48.54#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:48.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:48.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:48.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:48.54#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:00:48.54#ibcon#first serial, iclass 10, count 0 2006.183.08:00:48.54#ibcon#enter sib2, iclass 10, count 0 2006.183.08:00:48.54#ibcon#flushed, iclass 10, count 0 2006.183.08:00:48.54#ibcon#about to write, iclass 10, count 0 2006.183.08:00:48.54#ibcon#wrote, iclass 10, count 0 2006.183.08:00:48.54#ibcon#about to read 3, iclass 10, count 0 2006.183.08:00:48.56#ibcon#read 3, iclass 10, count 0 2006.183.08:00:48.56#ibcon#about to read 4, iclass 10, count 0 2006.183.08:00:48.56#ibcon#read 4, iclass 10, count 0 2006.183.08:00:48.56#ibcon#about to read 5, iclass 10, count 0 2006.183.08:00:48.56#ibcon#read 5, iclass 10, count 0 2006.183.08:00:48.56#ibcon#about to read 6, iclass 10, count 0 2006.183.08:00:48.56#ibcon#read 6, iclass 10, count 0 2006.183.08:00:48.56#ibcon#end of sib2, iclass 10, count 0 2006.183.08:00:48.56#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:00:48.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:00:48.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:00:48.56#ibcon#*before write, iclass 10, count 0 2006.183.08:00:48.56#ibcon#enter sib2, iclass 10, count 0 2006.183.08:00:48.56#ibcon#flushed, iclass 10, count 0 2006.183.08:00:48.56#ibcon#about to write, iclass 10, count 0 2006.183.08:00:48.56#ibcon#wrote, iclass 10, count 0 2006.183.08:00:48.56#ibcon#about to read 3, iclass 10, count 0 2006.183.08:00:48.61#ibcon#read 3, iclass 10, count 0 2006.183.08:00:48.61#ibcon#about to read 4, iclass 10, count 0 2006.183.08:00:48.61#ibcon#read 4, iclass 10, count 0 2006.183.08:00:48.61#ibcon#about to read 5, iclass 10, count 0 2006.183.08:00:48.61#ibcon#read 5, iclass 10, count 0 2006.183.08:00:48.61#ibcon#about to read 6, iclass 10, count 0 2006.183.08:00:48.61#ibcon#read 6, iclass 10, count 0 2006.183.08:00:48.61#ibcon#end of sib2, iclass 10, count 0 2006.183.08:00:48.61#ibcon#*after write, iclass 10, count 0 2006.183.08:00:48.61#ibcon#*before return 0, iclass 10, count 0 2006.183.08:00:48.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:48.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:48.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:00:48.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:00:48.61$vc4f8/va=3,6 2006.183.08:00:48.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.08:00:48.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.08:00:48.61#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:48.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:48.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:48.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:48.66#ibcon#enter wrdev, iclass 12, count 2 2006.183.08:00:48.66#ibcon#first serial, iclass 12, count 2 2006.183.08:00:48.66#ibcon#enter sib2, iclass 12, count 2 2006.183.08:00:48.66#ibcon#flushed, iclass 12, count 2 2006.183.08:00:48.66#ibcon#about to write, iclass 12, count 2 2006.183.08:00:48.66#ibcon#wrote, iclass 12, count 2 2006.183.08:00:48.66#ibcon#about to read 3, iclass 12, count 2 2006.183.08:00:48.68#ibcon#read 3, iclass 12, count 2 2006.183.08:00:48.68#ibcon#about to read 4, iclass 12, count 2 2006.183.08:00:48.68#ibcon#read 4, iclass 12, count 2 2006.183.08:00:48.68#ibcon#about to read 5, iclass 12, count 2 2006.183.08:00:48.68#ibcon#read 5, iclass 12, count 2 2006.183.08:00:48.68#ibcon#about to read 6, iclass 12, count 2 2006.183.08:00:48.68#ibcon#read 6, iclass 12, count 2 2006.183.08:00:48.68#ibcon#end of sib2, iclass 12, count 2 2006.183.08:00:48.68#ibcon#*mode == 0, iclass 12, count 2 2006.183.08:00:48.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.08:00:48.68#ibcon#[25=AT03-06\r\n] 2006.183.08:00:48.68#ibcon#*before write, iclass 12, count 2 2006.183.08:00:48.68#ibcon#enter sib2, iclass 12, count 2 2006.183.08:00:48.68#ibcon#flushed, iclass 12, count 2 2006.183.08:00:48.68#ibcon#about to write, iclass 12, count 2 2006.183.08:00:48.68#ibcon#wrote, iclass 12, count 2 2006.183.08:00:48.68#ibcon#about to read 3, iclass 12, count 2 2006.183.08:00:48.71#ibcon#read 3, iclass 12, count 2 2006.183.08:00:48.71#ibcon#about to read 4, iclass 12, count 2 2006.183.08:00:48.71#ibcon#read 4, iclass 12, count 2 2006.183.08:00:48.71#ibcon#about to read 5, iclass 12, count 2 2006.183.08:00:48.71#ibcon#read 5, iclass 12, count 2 2006.183.08:00:48.71#ibcon#about to read 6, iclass 12, count 2 2006.183.08:00:48.71#ibcon#read 6, iclass 12, count 2 2006.183.08:00:48.71#ibcon#end of sib2, iclass 12, count 2 2006.183.08:00:48.71#ibcon#*after write, iclass 12, count 2 2006.183.08:00:48.71#ibcon#*before return 0, iclass 12, count 2 2006.183.08:00:48.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:48.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:48.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.08:00:48.71#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:48.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:48.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:48.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:48.83#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:00:48.83#ibcon#first serial, iclass 12, count 0 2006.183.08:00:48.83#ibcon#enter sib2, iclass 12, count 0 2006.183.08:00:48.83#ibcon#flushed, iclass 12, count 0 2006.183.08:00:48.83#ibcon#about to write, iclass 12, count 0 2006.183.08:00:48.83#ibcon#wrote, iclass 12, count 0 2006.183.08:00:48.83#ibcon#about to read 3, iclass 12, count 0 2006.183.08:00:48.85#ibcon#read 3, iclass 12, count 0 2006.183.08:00:48.85#ibcon#about to read 4, iclass 12, count 0 2006.183.08:00:48.85#ibcon#read 4, iclass 12, count 0 2006.183.08:00:48.85#ibcon#about to read 5, iclass 12, count 0 2006.183.08:00:48.85#ibcon#read 5, iclass 12, count 0 2006.183.08:00:48.85#ibcon#about to read 6, iclass 12, count 0 2006.183.08:00:48.85#ibcon#read 6, iclass 12, count 0 2006.183.08:00:48.85#ibcon#end of sib2, iclass 12, count 0 2006.183.08:00:48.85#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:00:48.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:00:48.85#ibcon#[25=USB\r\n] 2006.183.08:00:48.85#ibcon#*before write, iclass 12, count 0 2006.183.08:00:48.85#ibcon#enter sib2, iclass 12, count 0 2006.183.08:00:48.85#ibcon#flushed, iclass 12, count 0 2006.183.08:00:48.85#ibcon#about to write, iclass 12, count 0 2006.183.08:00:48.85#ibcon#wrote, iclass 12, count 0 2006.183.08:00:48.85#ibcon#about to read 3, iclass 12, count 0 2006.183.08:00:48.88#ibcon#read 3, iclass 12, count 0 2006.183.08:00:48.88#ibcon#about to read 4, iclass 12, count 0 2006.183.08:00:48.88#ibcon#read 4, iclass 12, count 0 2006.183.08:00:48.88#ibcon#about to read 5, iclass 12, count 0 2006.183.08:00:48.88#ibcon#read 5, iclass 12, count 0 2006.183.08:00:48.88#ibcon#about to read 6, iclass 12, count 0 2006.183.08:00:48.88#ibcon#read 6, iclass 12, count 0 2006.183.08:00:48.88#ibcon#end of sib2, iclass 12, count 0 2006.183.08:00:48.88#ibcon#*after write, iclass 12, count 0 2006.183.08:00:48.88#ibcon#*before return 0, iclass 12, count 0 2006.183.08:00:48.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:48.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:48.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:00:48.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:00:48.88$vc4f8/valo=4,832.99 2006.183.08:00:48.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:00:48.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:00:48.88#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:48.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:48.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:48.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:48.88#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:00:48.88#ibcon#first serial, iclass 14, count 0 2006.183.08:00:48.88#ibcon#enter sib2, iclass 14, count 0 2006.183.08:00:48.88#ibcon#flushed, iclass 14, count 0 2006.183.08:00:48.88#ibcon#about to write, iclass 14, count 0 2006.183.08:00:48.88#ibcon#wrote, iclass 14, count 0 2006.183.08:00:48.88#ibcon#about to read 3, iclass 14, count 0 2006.183.08:00:48.90#ibcon#read 3, iclass 14, count 0 2006.183.08:00:48.90#ibcon#about to read 4, iclass 14, count 0 2006.183.08:00:48.90#ibcon#read 4, iclass 14, count 0 2006.183.08:00:48.90#ibcon#about to read 5, iclass 14, count 0 2006.183.08:00:48.90#ibcon#read 5, iclass 14, count 0 2006.183.08:00:48.90#ibcon#about to read 6, iclass 14, count 0 2006.183.08:00:48.90#ibcon#read 6, iclass 14, count 0 2006.183.08:00:48.90#ibcon#end of sib2, iclass 14, count 0 2006.183.08:00:48.90#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:00:48.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:00:48.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:00:48.90#ibcon#*before write, iclass 14, count 0 2006.183.08:00:48.90#ibcon#enter sib2, iclass 14, count 0 2006.183.08:00:48.90#ibcon#flushed, iclass 14, count 0 2006.183.08:00:48.90#ibcon#about to write, iclass 14, count 0 2006.183.08:00:48.90#ibcon#wrote, iclass 14, count 0 2006.183.08:00:48.90#ibcon#about to read 3, iclass 14, count 0 2006.183.08:00:48.95#ibcon#read 3, iclass 14, count 0 2006.183.08:00:48.95#ibcon#about to read 4, iclass 14, count 0 2006.183.08:00:48.95#ibcon#read 4, iclass 14, count 0 2006.183.08:00:48.95#ibcon#about to read 5, iclass 14, count 0 2006.183.08:00:48.95#ibcon#read 5, iclass 14, count 0 2006.183.08:00:48.95#ibcon#about to read 6, iclass 14, count 0 2006.183.08:00:48.95#ibcon#read 6, iclass 14, count 0 2006.183.08:00:48.95#ibcon#end of sib2, iclass 14, count 0 2006.183.08:00:48.95#ibcon#*after write, iclass 14, count 0 2006.183.08:00:48.95#ibcon#*before return 0, iclass 14, count 0 2006.183.08:00:48.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:48.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:48.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:00:48.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:00:48.95$vc4f8/va=4,7 2006.183.08:00:48.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.08:00:48.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.08:00:48.95#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:48.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:49.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:49.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:49.00#ibcon#enter wrdev, iclass 16, count 2 2006.183.08:00:49.00#ibcon#first serial, iclass 16, count 2 2006.183.08:00:49.00#ibcon#enter sib2, iclass 16, count 2 2006.183.08:00:49.00#ibcon#flushed, iclass 16, count 2 2006.183.08:00:49.00#ibcon#about to write, iclass 16, count 2 2006.183.08:00:49.00#ibcon#wrote, iclass 16, count 2 2006.183.08:00:49.00#ibcon#about to read 3, iclass 16, count 2 2006.183.08:00:49.02#ibcon#read 3, iclass 16, count 2 2006.183.08:00:49.02#ibcon#about to read 4, iclass 16, count 2 2006.183.08:00:49.02#ibcon#read 4, iclass 16, count 2 2006.183.08:00:49.02#ibcon#about to read 5, iclass 16, count 2 2006.183.08:00:49.02#ibcon#read 5, iclass 16, count 2 2006.183.08:00:49.02#ibcon#about to read 6, iclass 16, count 2 2006.183.08:00:49.02#ibcon#read 6, iclass 16, count 2 2006.183.08:00:49.02#ibcon#end of sib2, iclass 16, count 2 2006.183.08:00:49.02#ibcon#*mode == 0, iclass 16, count 2 2006.183.08:00:49.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.08:00:49.02#ibcon#[25=AT04-07\r\n] 2006.183.08:00:49.02#ibcon#*before write, iclass 16, count 2 2006.183.08:00:49.02#ibcon#enter sib2, iclass 16, count 2 2006.183.08:00:49.02#ibcon#flushed, iclass 16, count 2 2006.183.08:00:49.02#ibcon#about to write, iclass 16, count 2 2006.183.08:00:49.02#ibcon#wrote, iclass 16, count 2 2006.183.08:00:49.02#ibcon#about to read 3, iclass 16, count 2 2006.183.08:00:49.05#ibcon#read 3, iclass 16, count 2 2006.183.08:00:49.05#ibcon#about to read 4, iclass 16, count 2 2006.183.08:00:49.05#ibcon#read 4, iclass 16, count 2 2006.183.08:00:49.05#ibcon#about to read 5, iclass 16, count 2 2006.183.08:00:49.05#ibcon#read 5, iclass 16, count 2 2006.183.08:00:49.05#ibcon#about to read 6, iclass 16, count 2 2006.183.08:00:49.05#ibcon#read 6, iclass 16, count 2 2006.183.08:00:49.05#ibcon#end of sib2, iclass 16, count 2 2006.183.08:00:49.05#ibcon#*after write, iclass 16, count 2 2006.183.08:00:49.05#ibcon#*before return 0, iclass 16, count 2 2006.183.08:00:49.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:49.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:49.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.08:00:49.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:49.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:49.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:49.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:49.17#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:00:49.17#ibcon#first serial, iclass 16, count 0 2006.183.08:00:49.17#ibcon#enter sib2, iclass 16, count 0 2006.183.08:00:49.17#ibcon#flushed, iclass 16, count 0 2006.183.08:00:49.17#ibcon#about to write, iclass 16, count 0 2006.183.08:00:49.17#ibcon#wrote, iclass 16, count 0 2006.183.08:00:49.17#ibcon#about to read 3, iclass 16, count 0 2006.183.08:00:49.19#ibcon#read 3, iclass 16, count 0 2006.183.08:00:49.19#ibcon#about to read 4, iclass 16, count 0 2006.183.08:00:49.19#ibcon#read 4, iclass 16, count 0 2006.183.08:00:49.19#ibcon#about to read 5, iclass 16, count 0 2006.183.08:00:49.19#ibcon#read 5, iclass 16, count 0 2006.183.08:00:49.19#ibcon#about to read 6, iclass 16, count 0 2006.183.08:00:49.19#ibcon#read 6, iclass 16, count 0 2006.183.08:00:49.19#ibcon#end of sib2, iclass 16, count 0 2006.183.08:00:49.19#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:00:49.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:00:49.19#ibcon#[25=USB\r\n] 2006.183.08:00:49.19#ibcon#*before write, iclass 16, count 0 2006.183.08:00:49.19#ibcon#enter sib2, iclass 16, count 0 2006.183.08:00:49.19#ibcon#flushed, iclass 16, count 0 2006.183.08:00:49.19#ibcon#about to write, iclass 16, count 0 2006.183.08:00:49.19#ibcon#wrote, iclass 16, count 0 2006.183.08:00:49.19#ibcon#about to read 3, iclass 16, count 0 2006.183.08:00:49.22#ibcon#read 3, iclass 16, count 0 2006.183.08:00:49.22#ibcon#about to read 4, iclass 16, count 0 2006.183.08:00:49.22#ibcon#read 4, iclass 16, count 0 2006.183.08:00:49.22#ibcon#about to read 5, iclass 16, count 0 2006.183.08:00:49.22#ibcon#read 5, iclass 16, count 0 2006.183.08:00:49.22#ibcon#about to read 6, iclass 16, count 0 2006.183.08:00:49.22#ibcon#read 6, iclass 16, count 0 2006.183.08:00:49.22#ibcon#end of sib2, iclass 16, count 0 2006.183.08:00:49.22#ibcon#*after write, iclass 16, count 0 2006.183.08:00:49.22#ibcon#*before return 0, iclass 16, count 0 2006.183.08:00:49.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:49.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:49.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:00:49.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:00:49.22$vc4f8/valo=5,652.99 2006.183.08:00:49.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:00:49.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:00:49.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:49.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:49.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:49.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:49.22#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:00:49.22#ibcon#first serial, iclass 18, count 0 2006.183.08:00:49.22#ibcon#enter sib2, iclass 18, count 0 2006.183.08:00:49.22#ibcon#flushed, iclass 18, count 0 2006.183.08:00:49.22#ibcon#about to write, iclass 18, count 0 2006.183.08:00:49.22#ibcon#wrote, iclass 18, count 0 2006.183.08:00:49.22#ibcon#about to read 3, iclass 18, count 0 2006.183.08:00:49.24#ibcon#read 3, iclass 18, count 0 2006.183.08:00:49.24#ibcon#about to read 4, iclass 18, count 0 2006.183.08:00:49.24#ibcon#read 4, iclass 18, count 0 2006.183.08:00:49.24#ibcon#about to read 5, iclass 18, count 0 2006.183.08:00:49.24#ibcon#read 5, iclass 18, count 0 2006.183.08:00:49.24#ibcon#about to read 6, iclass 18, count 0 2006.183.08:00:49.24#ibcon#read 6, iclass 18, count 0 2006.183.08:00:49.24#ibcon#end of sib2, iclass 18, count 0 2006.183.08:00:49.24#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:00:49.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:00:49.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:00:49.24#ibcon#*before write, iclass 18, count 0 2006.183.08:00:49.24#ibcon#enter sib2, iclass 18, count 0 2006.183.08:00:49.24#ibcon#flushed, iclass 18, count 0 2006.183.08:00:49.24#ibcon#about to write, iclass 18, count 0 2006.183.08:00:49.24#ibcon#wrote, iclass 18, count 0 2006.183.08:00:49.24#ibcon#about to read 3, iclass 18, count 0 2006.183.08:00:49.28#ibcon#read 3, iclass 18, count 0 2006.183.08:00:49.28#ibcon#about to read 4, iclass 18, count 0 2006.183.08:00:49.28#ibcon#read 4, iclass 18, count 0 2006.183.08:00:49.28#ibcon#about to read 5, iclass 18, count 0 2006.183.08:00:49.28#ibcon#read 5, iclass 18, count 0 2006.183.08:00:49.28#ibcon#about to read 6, iclass 18, count 0 2006.183.08:00:49.28#ibcon#read 6, iclass 18, count 0 2006.183.08:00:49.28#ibcon#end of sib2, iclass 18, count 0 2006.183.08:00:49.28#ibcon#*after write, iclass 18, count 0 2006.183.08:00:49.28#ibcon#*before return 0, iclass 18, count 0 2006.183.08:00:49.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:49.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:49.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:00:49.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:00:49.28$vc4f8/va=5,7 2006.183.08:00:49.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.08:00:49.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.08:00:49.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:49.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:49.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:49.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:49.34#ibcon#enter wrdev, iclass 20, count 2 2006.183.08:00:49.34#ibcon#first serial, iclass 20, count 2 2006.183.08:00:49.34#ibcon#enter sib2, iclass 20, count 2 2006.183.08:00:49.34#ibcon#flushed, iclass 20, count 2 2006.183.08:00:49.34#ibcon#about to write, iclass 20, count 2 2006.183.08:00:49.34#ibcon#wrote, iclass 20, count 2 2006.183.08:00:49.34#ibcon#about to read 3, iclass 20, count 2 2006.183.08:00:49.36#ibcon#read 3, iclass 20, count 2 2006.183.08:00:49.36#ibcon#about to read 4, iclass 20, count 2 2006.183.08:00:49.36#ibcon#read 4, iclass 20, count 2 2006.183.08:00:49.36#ibcon#about to read 5, iclass 20, count 2 2006.183.08:00:49.36#ibcon#read 5, iclass 20, count 2 2006.183.08:00:49.36#ibcon#about to read 6, iclass 20, count 2 2006.183.08:00:49.36#ibcon#read 6, iclass 20, count 2 2006.183.08:00:49.36#ibcon#end of sib2, iclass 20, count 2 2006.183.08:00:49.36#ibcon#*mode == 0, iclass 20, count 2 2006.183.08:00:49.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.08:00:49.36#ibcon#[25=AT05-07\r\n] 2006.183.08:00:49.36#ibcon#*before write, iclass 20, count 2 2006.183.08:00:49.36#ibcon#enter sib2, iclass 20, count 2 2006.183.08:00:49.36#ibcon#flushed, iclass 20, count 2 2006.183.08:00:49.36#ibcon#about to write, iclass 20, count 2 2006.183.08:00:49.36#ibcon#wrote, iclass 20, count 2 2006.183.08:00:49.36#ibcon#about to read 3, iclass 20, count 2 2006.183.08:00:49.39#ibcon#read 3, iclass 20, count 2 2006.183.08:00:49.39#ibcon#about to read 4, iclass 20, count 2 2006.183.08:00:49.39#ibcon#read 4, iclass 20, count 2 2006.183.08:00:49.39#ibcon#about to read 5, iclass 20, count 2 2006.183.08:00:49.39#ibcon#read 5, iclass 20, count 2 2006.183.08:00:49.39#ibcon#about to read 6, iclass 20, count 2 2006.183.08:00:49.39#ibcon#read 6, iclass 20, count 2 2006.183.08:00:49.39#ibcon#end of sib2, iclass 20, count 2 2006.183.08:00:49.39#ibcon#*after write, iclass 20, count 2 2006.183.08:00:49.39#ibcon#*before return 0, iclass 20, count 2 2006.183.08:00:49.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:49.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:49.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.08:00:49.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:49.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:49.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:49.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:49.51#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:00:49.51#ibcon#first serial, iclass 20, count 0 2006.183.08:00:49.51#ibcon#enter sib2, iclass 20, count 0 2006.183.08:00:49.51#ibcon#flushed, iclass 20, count 0 2006.183.08:00:49.51#ibcon#about to write, iclass 20, count 0 2006.183.08:00:49.51#ibcon#wrote, iclass 20, count 0 2006.183.08:00:49.51#ibcon#about to read 3, iclass 20, count 0 2006.183.08:00:49.53#ibcon#read 3, iclass 20, count 0 2006.183.08:00:49.53#ibcon#about to read 4, iclass 20, count 0 2006.183.08:00:49.53#ibcon#read 4, iclass 20, count 0 2006.183.08:00:49.53#ibcon#about to read 5, iclass 20, count 0 2006.183.08:00:49.53#ibcon#read 5, iclass 20, count 0 2006.183.08:00:49.53#ibcon#about to read 6, iclass 20, count 0 2006.183.08:00:49.53#ibcon#read 6, iclass 20, count 0 2006.183.08:00:49.53#ibcon#end of sib2, iclass 20, count 0 2006.183.08:00:49.53#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:00:49.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:00:49.53#ibcon#[25=USB\r\n] 2006.183.08:00:49.53#ibcon#*before write, iclass 20, count 0 2006.183.08:00:49.53#ibcon#enter sib2, iclass 20, count 0 2006.183.08:00:49.53#ibcon#flushed, iclass 20, count 0 2006.183.08:00:49.53#ibcon#about to write, iclass 20, count 0 2006.183.08:00:49.53#ibcon#wrote, iclass 20, count 0 2006.183.08:00:49.53#ibcon#about to read 3, iclass 20, count 0 2006.183.08:00:49.56#ibcon#read 3, iclass 20, count 0 2006.183.08:00:49.56#ibcon#about to read 4, iclass 20, count 0 2006.183.08:00:49.56#ibcon#read 4, iclass 20, count 0 2006.183.08:00:49.56#ibcon#about to read 5, iclass 20, count 0 2006.183.08:00:49.56#ibcon#read 5, iclass 20, count 0 2006.183.08:00:49.56#ibcon#about to read 6, iclass 20, count 0 2006.183.08:00:49.56#ibcon#read 6, iclass 20, count 0 2006.183.08:00:49.56#ibcon#end of sib2, iclass 20, count 0 2006.183.08:00:49.56#ibcon#*after write, iclass 20, count 0 2006.183.08:00:49.56#ibcon#*before return 0, iclass 20, count 0 2006.183.08:00:49.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:49.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:49.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:00:49.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:00:49.56$vc4f8/valo=6,772.99 2006.183.08:00:49.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.08:00:49.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.08:00:49.56#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:49.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:49.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:49.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:49.56#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:00:49.56#ibcon#first serial, iclass 22, count 0 2006.183.08:00:49.56#ibcon#enter sib2, iclass 22, count 0 2006.183.08:00:49.56#ibcon#flushed, iclass 22, count 0 2006.183.08:00:49.56#ibcon#about to write, iclass 22, count 0 2006.183.08:00:49.56#ibcon#wrote, iclass 22, count 0 2006.183.08:00:49.56#ibcon#about to read 3, iclass 22, count 0 2006.183.08:00:49.58#ibcon#read 3, iclass 22, count 0 2006.183.08:00:49.58#ibcon#about to read 4, iclass 22, count 0 2006.183.08:00:49.58#ibcon#read 4, iclass 22, count 0 2006.183.08:00:49.58#ibcon#about to read 5, iclass 22, count 0 2006.183.08:00:49.58#ibcon#read 5, iclass 22, count 0 2006.183.08:00:49.58#ibcon#about to read 6, iclass 22, count 0 2006.183.08:00:49.58#ibcon#read 6, iclass 22, count 0 2006.183.08:00:49.58#ibcon#end of sib2, iclass 22, count 0 2006.183.08:00:49.58#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:00:49.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:00:49.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:00:49.58#ibcon#*before write, iclass 22, count 0 2006.183.08:00:49.58#ibcon#enter sib2, iclass 22, count 0 2006.183.08:00:49.58#ibcon#flushed, iclass 22, count 0 2006.183.08:00:49.58#ibcon#about to write, iclass 22, count 0 2006.183.08:00:49.58#ibcon#wrote, iclass 22, count 0 2006.183.08:00:49.58#ibcon#about to read 3, iclass 22, count 0 2006.183.08:00:49.62#ibcon#read 3, iclass 22, count 0 2006.183.08:00:49.62#ibcon#about to read 4, iclass 22, count 0 2006.183.08:00:49.62#ibcon#read 4, iclass 22, count 0 2006.183.08:00:49.62#ibcon#about to read 5, iclass 22, count 0 2006.183.08:00:49.62#ibcon#read 5, iclass 22, count 0 2006.183.08:00:49.62#ibcon#about to read 6, iclass 22, count 0 2006.183.08:00:49.62#ibcon#read 6, iclass 22, count 0 2006.183.08:00:49.62#ibcon#end of sib2, iclass 22, count 0 2006.183.08:00:49.62#ibcon#*after write, iclass 22, count 0 2006.183.08:00:49.62#ibcon#*before return 0, iclass 22, count 0 2006.183.08:00:49.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:49.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:49.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:00:49.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:00:49.62$vc4f8/va=6,6 2006.183.08:00:49.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.08:00:49.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.08:00:49.62#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:49.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:00:49.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:00:49.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:00:49.68#ibcon#enter wrdev, iclass 24, count 2 2006.183.08:00:49.68#ibcon#first serial, iclass 24, count 2 2006.183.08:00:49.68#ibcon#enter sib2, iclass 24, count 2 2006.183.08:00:49.68#ibcon#flushed, iclass 24, count 2 2006.183.08:00:49.68#ibcon#about to write, iclass 24, count 2 2006.183.08:00:49.68#ibcon#wrote, iclass 24, count 2 2006.183.08:00:49.68#ibcon#about to read 3, iclass 24, count 2 2006.183.08:00:49.70#ibcon#read 3, iclass 24, count 2 2006.183.08:00:49.70#ibcon#about to read 4, iclass 24, count 2 2006.183.08:00:49.70#ibcon#read 4, iclass 24, count 2 2006.183.08:00:49.70#ibcon#about to read 5, iclass 24, count 2 2006.183.08:00:49.70#ibcon#read 5, iclass 24, count 2 2006.183.08:00:49.70#ibcon#about to read 6, iclass 24, count 2 2006.183.08:00:49.70#ibcon#read 6, iclass 24, count 2 2006.183.08:00:49.70#ibcon#end of sib2, iclass 24, count 2 2006.183.08:00:49.70#ibcon#*mode == 0, iclass 24, count 2 2006.183.08:00:49.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.08:00:49.70#ibcon#[25=AT06-06\r\n] 2006.183.08:00:49.70#ibcon#*before write, iclass 24, count 2 2006.183.08:00:49.70#ibcon#enter sib2, iclass 24, count 2 2006.183.08:00:49.70#ibcon#flushed, iclass 24, count 2 2006.183.08:00:49.70#ibcon#about to write, iclass 24, count 2 2006.183.08:00:49.70#ibcon#wrote, iclass 24, count 2 2006.183.08:00:49.70#ibcon#about to read 3, iclass 24, count 2 2006.183.08:00:49.73#ibcon#read 3, iclass 24, count 2 2006.183.08:00:49.73#ibcon#about to read 4, iclass 24, count 2 2006.183.08:00:49.73#ibcon#read 4, iclass 24, count 2 2006.183.08:00:49.73#ibcon#about to read 5, iclass 24, count 2 2006.183.08:00:49.73#ibcon#read 5, iclass 24, count 2 2006.183.08:00:49.73#ibcon#about to read 6, iclass 24, count 2 2006.183.08:00:49.73#ibcon#read 6, iclass 24, count 2 2006.183.08:00:49.73#ibcon#end of sib2, iclass 24, count 2 2006.183.08:00:49.73#ibcon#*after write, iclass 24, count 2 2006.183.08:00:49.73#ibcon#*before return 0, iclass 24, count 2 2006.183.08:00:49.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:00:49.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:00:49.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.08:00:49.73#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:49.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:00:49.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:00:49.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:00:49.85#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:00:49.85#ibcon#first serial, iclass 24, count 0 2006.183.08:00:49.85#ibcon#enter sib2, iclass 24, count 0 2006.183.08:00:49.85#ibcon#flushed, iclass 24, count 0 2006.183.08:00:49.85#ibcon#about to write, iclass 24, count 0 2006.183.08:00:49.85#ibcon#wrote, iclass 24, count 0 2006.183.08:00:49.85#ibcon#about to read 3, iclass 24, count 0 2006.183.08:00:49.87#ibcon#read 3, iclass 24, count 0 2006.183.08:00:49.87#ibcon#about to read 4, iclass 24, count 0 2006.183.08:00:49.87#ibcon#read 4, iclass 24, count 0 2006.183.08:00:49.87#ibcon#about to read 5, iclass 24, count 0 2006.183.08:00:49.87#ibcon#read 5, iclass 24, count 0 2006.183.08:00:49.87#ibcon#about to read 6, iclass 24, count 0 2006.183.08:00:49.87#ibcon#read 6, iclass 24, count 0 2006.183.08:00:49.87#ibcon#end of sib2, iclass 24, count 0 2006.183.08:00:49.87#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:00:49.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:00:49.87#ibcon#[25=USB\r\n] 2006.183.08:00:49.87#ibcon#*before write, iclass 24, count 0 2006.183.08:00:49.87#ibcon#enter sib2, iclass 24, count 0 2006.183.08:00:49.87#ibcon#flushed, iclass 24, count 0 2006.183.08:00:49.87#ibcon#about to write, iclass 24, count 0 2006.183.08:00:49.87#ibcon#wrote, iclass 24, count 0 2006.183.08:00:49.87#ibcon#about to read 3, iclass 24, count 0 2006.183.08:00:49.90#ibcon#read 3, iclass 24, count 0 2006.183.08:00:49.90#ibcon#about to read 4, iclass 24, count 0 2006.183.08:00:49.90#ibcon#read 4, iclass 24, count 0 2006.183.08:00:49.90#ibcon#about to read 5, iclass 24, count 0 2006.183.08:00:49.90#ibcon#read 5, iclass 24, count 0 2006.183.08:00:49.90#ibcon#about to read 6, iclass 24, count 0 2006.183.08:00:49.90#ibcon#read 6, iclass 24, count 0 2006.183.08:00:49.90#ibcon#end of sib2, iclass 24, count 0 2006.183.08:00:49.90#ibcon#*after write, iclass 24, count 0 2006.183.08:00:49.90#ibcon#*before return 0, iclass 24, count 0 2006.183.08:00:49.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:00:49.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:00:49.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:00:49.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:00:49.90$vc4f8/valo=7,832.99 2006.183.08:00:49.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.08:00:49.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.08:00:49.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:49.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:00:49.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:00:49.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:00:49.90#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:00:49.90#ibcon#first serial, iclass 26, count 0 2006.183.08:00:49.90#ibcon#enter sib2, iclass 26, count 0 2006.183.08:00:49.90#ibcon#flushed, iclass 26, count 0 2006.183.08:00:49.90#ibcon#about to write, iclass 26, count 0 2006.183.08:00:49.90#ibcon#wrote, iclass 26, count 0 2006.183.08:00:49.90#ibcon#about to read 3, iclass 26, count 0 2006.183.08:00:49.92#ibcon#read 3, iclass 26, count 0 2006.183.08:00:49.92#ibcon#about to read 4, iclass 26, count 0 2006.183.08:00:49.92#ibcon#read 4, iclass 26, count 0 2006.183.08:00:49.92#ibcon#about to read 5, iclass 26, count 0 2006.183.08:00:49.92#ibcon#read 5, iclass 26, count 0 2006.183.08:00:49.92#ibcon#about to read 6, iclass 26, count 0 2006.183.08:00:49.92#ibcon#read 6, iclass 26, count 0 2006.183.08:00:49.92#ibcon#end of sib2, iclass 26, count 0 2006.183.08:00:49.92#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:00:49.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:00:49.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:00:49.92#ibcon#*before write, iclass 26, count 0 2006.183.08:00:49.92#ibcon#enter sib2, iclass 26, count 0 2006.183.08:00:49.92#ibcon#flushed, iclass 26, count 0 2006.183.08:00:49.92#ibcon#about to write, iclass 26, count 0 2006.183.08:00:49.92#ibcon#wrote, iclass 26, count 0 2006.183.08:00:49.92#ibcon#about to read 3, iclass 26, count 0 2006.183.08:00:49.96#ibcon#read 3, iclass 26, count 0 2006.183.08:00:49.96#ibcon#about to read 4, iclass 26, count 0 2006.183.08:00:49.96#ibcon#read 4, iclass 26, count 0 2006.183.08:00:49.96#ibcon#about to read 5, iclass 26, count 0 2006.183.08:00:49.96#ibcon#read 5, iclass 26, count 0 2006.183.08:00:49.96#ibcon#about to read 6, iclass 26, count 0 2006.183.08:00:49.96#ibcon#read 6, iclass 26, count 0 2006.183.08:00:49.96#ibcon#end of sib2, iclass 26, count 0 2006.183.08:00:49.96#ibcon#*after write, iclass 26, count 0 2006.183.08:00:49.96#ibcon#*before return 0, iclass 26, count 0 2006.183.08:00:49.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:00:49.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:00:49.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:00:49.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:00:49.96$vc4f8/va=7,6 2006.183.08:00:49.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.08:00:49.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.08:00:49.96#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:49.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:00:50.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:00:50.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:00:50.02#ibcon#enter wrdev, iclass 28, count 2 2006.183.08:00:50.02#ibcon#first serial, iclass 28, count 2 2006.183.08:00:50.02#ibcon#enter sib2, iclass 28, count 2 2006.183.08:00:50.02#ibcon#flushed, iclass 28, count 2 2006.183.08:00:50.02#ibcon#about to write, iclass 28, count 2 2006.183.08:00:50.02#ibcon#wrote, iclass 28, count 2 2006.183.08:00:50.02#ibcon#about to read 3, iclass 28, count 2 2006.183.08:00:50.04#ibcon#read 3, iclass 28, count 2 2006.183.08:00:50.04#ibcon#about to read 4, iclass 28, count 2 2006.183.08:00:50.04#ibcon#read 4, iclass 28, count 2 2006.183.08:00:50.04#ibcon#about to read 5, iclass 28, count 2 2006.183.08:00:50.04#ibcon#read 5, iclass 28, count 2 2006.183.08:00:50.04#ibcon#about to read 6, iclass 28, count 2 2006.183.08:00:50.04#ibcon#read 6, iclass 28, count 2 2006.183.08:00:50.04#ibcon#end of sib2, iclass 28, count 2 2006.183.08:00:50.04#ibcon#*mode == 0, iclass 28, count 2 2006.183.08:00:50.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.08:00:50.04#ibcon#[25=AT07-06\r\n] 2006.183.08:00:50.04#ibcon#*before write, iclass 28, count 2 2006.183.08:00:50.04#ibcon#enter sib2, iclass 28, count 2 2006.183.08:00:50.04#ibcon#flushed, iclass 28, count 2 2006.183.08:00:50.04#ibcon#about to write, iclass 28, count 2 2006.183.08:00:50.04#ibcon#wrote, iclass 28, count 2 2006.183.08:00:50.04#ibcon#about to read 3, iclass 28, count 2 2006.183.08:00:50.07#ibcon#read 3, iclass 28, count 2 2006.183.08:00:50.07#ibcon#about to read 4, iclass 28, count 2 2006.183.08:00:50.07#ibcon#read 4, iclass 28, count 2 2006.183.08:00:50.07#ibcon#about to read 5, iclass 28, count 2 2006.183.08:00:50.07#ibcon#read 5, iclass 28, count 2 2006.183.08:00:50.07#ibcon#about to read 6, iclass 28, count 2 2006.183.08:00:50.07#ibcon#read 6, iclass 28, count 2 2006.183.08:00:50.07#ibcon#end of sib2, iclass 28, count 2 2006.183.08:00:50.07#ibcon#*after write, iclass 28, count 2 2006.183.08:00:50.07#ibcon#*before return 0, iclass 28, count 2 2006.183.08:00:50.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:00:50.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:00:50.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.08:00:50.07#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:50.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:00:50.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:00:50.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:00:50.19#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:00:50.19#ibcon#first serial, iclass 28, count 0 2006.183.08:00:50.19#ibcon#enter sib2, iclass 28, count 0 2006.183.08:00:50.19#ibcon#flushed, iclass 28, count 0 2006.183.08:00:50.19#ibcon#about to write, iclass 28, count 0 2006.183.08:00:50.19#ibcon#wrote, iclass 28, count 0 2006.183.08:00:50.19#ibcon#about to read 3, iclass 28, count 0 2006.183.08:00:50.21#ibcon#read 3, iclass 28, count 0 2006.183.08:00:50.21#ibcon#about to read 4, iclass 28, count 0 2006.183.08:00:50.21#ibcon#read 4, iclass 28, count 0 2006.183.08:00:50.21#ibcon#about to read 5, iclass 28, count 0 2006.183.08:00:50.21#ibcon#read 5, iclass 28, count 0 2006.183.08:00:50.21#ibcon#about to read 6, iclass 28, count 0 2006.183.08:00:50.21#ibcon#read 6, iclass 28, count 0 2006.183.08:00:50.21#ibcon#end of sib2, iclass 28, count 0 2006.183.08:00:50.21#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:00:50.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:00:50.21#ibcon#[25=USB\r\n] 2006.183.08:00:50.21#ibcon#*before write, iclass 28, count 0 2006.183.08:00:50.21#ibcon#enter sib2, iclass 28, count 0 2006.183.08:00:50.21#ibcon#flushed, iclass 28, count 0 2006.183.08:00:50.21#ibcon#about to write, iclass 28, count 0 2006.183.08:00:50.21#ibcon#wrote, iclass 28, count 0 2006.183.08:00:50.21#ibcon#about to read 3, iclass 28, count 0 2006.183.08:00:50.24#ibcon#read 3, iclass 28, count 0 2006.183.08:00:50.24#ibcon#about to read 4, iclass 28, count 0 2006.183.08:00:50.24#ibcon#read 4, iclass 28, count 0 2006.183.08:00:50.24#ibcon#about to read 5, iclass 28, count 0 2006.183.08:00:50.24#ibcon#read 5, iclass 28, count 0 2006.183.08:00:50.24#ibcon#about to read 6, iclass 28, count 0 2006.183.08:00:50.24#ibcon#read 6, iclass 28, count 0 2006.183.08:00:50.24#ibcon#end of sib2, iclass 28, count 0 2006.183.08:00:50.24#ibcon#*after write, iclass 28, count 0 2006.183.08:00:50.24#ibcon#*before return 0, iclass 28, count 0 2006.183.08:00:50.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:00:50.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:00:50.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:00:50.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:00:50.24$vc4f8/valo=8,852.99 2006.183.08:00:50.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:00:50.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:00:50.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:50.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:00:50.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:00:50.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:00:50.24#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:00:50.24#ibcon#first serial, iclass 30, count 0 2006.183.08:00:50.24#ibcon#enter sib2, iclass 30, count 0 2006.183.08:00:50.24#ibcon#flushed, iclass 30, count 0 2006.183.08:00:50.24#ibcon#about to write, iclass 30, count 0 2006.183.08:00:50.24#ibcon#wrote, iclass 30, count 0 2006.183.08:00:50.24#ibcon#about to read 3, iclass 30, count 0 2006.183.08:00:50.26#ibcon#read 3, iclass 30, count 0 2006.183.08:00:50.26#ibcon#about to read 4, iclass 30, count 0 2006.183.08:00:50.26#ibcon#read 4, iclass 30, count 0 2006.183.08:00:50.26#ibcon#about to read 5, iclass 30, count 0 2006.183.08:00:50.26#ibcon#read 5, iclass 30, count 0 2006.183.08:00:50.26#ibcon#about to read 6, iclass 30, count 0 2006.183.08:00:50.26#ibcon#read 6, iclass 30, count 0 2006.183.08:00:50.26#ibcon#end of sib2, iclass 30, count 0 2006.183.08:00:50.26#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:00:50.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:00:50.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:00:50.26#ibcon#*before write, iclass 30, count 0 2006.183.08:00:50.26#ibcon#enter sib2, iclass 30, count 0 2006.183.08:00:50.26#ibcon#flushed, iclass 30, count 0 2006.183.08:00:50.26#ibcon#about to write, iclass 30, count 0 2006.183.08:00:50.26#ibcon#wrote, iclass 30, count 0 2006.183.08:00:50.26#ibcon#about to read 3, iclass 30, count 0 2006.183.08:00:50.30#ibcon#read 3, iclass 30, count 0 2006.183.08:00:50.30#ibcon#about to read 4, iclass 30, count 0 2006.183.08:00:50.30#ibcon#read 4, iclass 30, count 0 2006.183.08:00:50.30#ibcon#about to read 5, iclass 30, count 0 2006.183.08:00:50.30#ibcon#read 5, iclass 30, count 0 2006.183.08:00:50.30#ibcon#about to read 6, iclass 30, count 0 2006.183.08:00:50.30#ibcon#read 6, iclass 30, count 0 2006.183.08:00:50.30#ibcon#end of sib2, iclass 30, count 0 2006.183.08:00:50.30#ibcon#*after write, iclass 30, count 0 2006.183.08:00:50.30#ibcon#*before return 0, iclass 30, count 0 2006.183.08:00:50.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:00:50.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:00:50.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:00:50.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:00:50.30$vc4f8/va=8,7 2006.183.08:00:50.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.08:00:50.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.08:00:50.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:50.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:00:50.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:00:50.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:00:50.36#ibcon#enter wrdev, iclass 32, count 2 2006.183.08:00:50.36#ibcon#first serial, iclass 32, count 2 2006.183.08:00:50.36#ibcon#enter sib2, iclass 32, count 2 2006.183.08:00:50.36#ibcon#flushed, iclass 32, count 2 2006.183.08:00:50.36#ibcon#about to write, iclass 32, count 2 2006.183.08:00:50.36#ibcon#wrote, iclass 32, count 2 2006.183.08:00:50.36#ibcon#about to read 3, iclass 32, count 2 2006.183.08:00:50.38#ibcon#read 3, iclass 32, count 2 2006.183.08:00:50.38#ibcon#about to read 4, iclass 32, count 2 2006.183.08:00:50.38#ibcon#read 4, iclass 32, count 2 2006.183.08:00:50.38#ibcon#about to read 5, iclass 32, count 2 2006.183.08:00:50.38#ibcon#read 5, iclass 32, count 2 2006.183.08:00:50.38#ibcon#about to read 6, iclass 32, count 2 2006.183.08:00:50.38#ibcon#read 6, iclass 32, count 2 2006.183.08:00:50.38#ibcon#end of sib2, iclass 32, count 2 2006.183.08:00:50.38#ibcon#*mode == 0, iclass 32, count 2 2006.183.08:00:50.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.08:00:50.38#ibcon#[25=AT08-07\r\n] 2006.183.08:00:50.38#ibcon#*before write, iclass 32, count 2 2006.183.08:00:50.38#ibcon#enter sib2, iclass 32, count 2 2006.183.08:00:50.38#ibcon#flushed, iclass 32, count 2 2006.183.08:00:50.38#ibcon#about to write, iclass 32, count 2 2006.183.08:00:50.38#ibcon#wrote, iclass 32, count 2 2006.183.08:00:50.38#ibcon#about to read 3, iclass 32, count 2 2006.183.08:00:50.41#ibcon#read 3, iclass 32, count 2 2006.183.08:00:50.41#ibcon#about to read 4, iclass 32, count 2 2006.183.08:00:50.41#ibcon#read 4, iclass 32, count 2 2006.183.08:00:50.41#ibcon#about to read 5, iclass 32, count 2 2006.183.08:00:50.41#ibcon#read 5, iclass 32, count 2 2006.183.08:00:50.41#ibcon#about to read 6, iclass 32, count 2 2006.183.08:00:50.41#ibcon#read 6, iclass 32, count 2 2006.183.08:00:50.41#ibcon#end of sib2, iclass 32, count 2 2006.183.08:00:50.41#ibcon#*after write, iclass 32, count 2 2006.183.08:00:50.41#ibcon#*before return 0, iclass 32, count 2 2006.183.08:00:50.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:00:50.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:00:50.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.08:00:50.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:50.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:00:50.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:00:50.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:00:50.53#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:00:50.53#ibcon#first serial, iclass 32, count 0 2006.183.08:00:50.53#ibcon#enter sib2, iclass 32, count 0 2006.183.08:00:50.53#ibcon#flushed, iclass 32, count 0 2006.183.08:00:50.53#ibcon#about to write, iclass 32, count 0 2006.183.08:00:50.53#ibcon#wrote, iclass 32, count 0 2006.183.08:00:50.53#ibcon#about to read 3, iclass 32, count 0 2006.183.08:00:50.55#ibcon#read 3, iclass 32, count 0 2006.183.08:00:50.55#ibcon#about to read 4, iclass 32, count 0 2006.183.08:00:50.55#ibcon#read 4, iclass 32, count 0 2006.183.08:00:50.55#ibcon#about to read 5, iclass 32, count 0 2006.183.08:00:50.55#ibcon#read 5, iclass 32, count 0 2006.183.08:00:50.55#ibcon#about to read 6, iclass 32, count 0 2006.183.08:00:50.55#ibcon#read 6, iclass 32, count 0 2006.183.08:00:50.55#ibcon#end of sib2, iclass 32, count 0 2006.183.08:00:50.55#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:00:50.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:00:50.55#ibcon#[25=USB\r\n] 2006.183.08:00:50.55#ibcon#*before write, iclass 32, count 0 2006.183.08:00:50.55#ibcon#enter sib2, iclass 32, count 0 2006.183.08:00:50.55#ibcon#flushed, iclass 32, count 0 2006.183.08:00:50.55#ibcon#about to write, iclass 32, count 0 2006.183.08:00:50.55#ibcon#wrote, iclass 32, count 0 2006.183.08:00:50.55#ibcon#about to read 3, iclass 32, count 0 2006.183.08:00:50.58#ibcon#read 3, iclass 32, count 0 2006.183.08:00:50.58#ibcon#about to read 4, iclass 32, count 0 2006.183.08:00:50.58#ibcon#read 4, iclass 32, count 0 2006.183.08:00:50.58#ibcon#about to read 5, iclass 32, count 0 2006.183.08:00:50.58#ibcon#read 5, iclass 32, count 0 2006.183.08:00:50.58#ibcon#about to read 6, iclass 32, count 0 2006.183.08:00:50.58#ibcon#read 6, iclass 32, count 0 2006.183.08:00:50.58#ibcon#end of sib2, iclass 32, count 0 2006.183.08:00:50.58#ibcon#*after write, iclass 32, count 0 2006.183.08:00:50.58#ibcon#*before return 0, iclass 32, count 0 2006.183.08:00:50.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:00:50.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:00:50.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:00:50.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:00:50.58$vc4f8/vblo=1,632.99 2006.183.08:00:50.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.08:00:50.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.08:00:50.58#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:50.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:50.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:50.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:50.58#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:00:50.58#ibcon#first serial, iclass 34, count 0 2006.183.08:00:50.58#ibcon#enter sib2, iclass 34, count 0 2006.183.08:00:50.58#ibcon#flushed, iclass 34, count 0 2006.183.08:00:50.58#ibcon#about to write, iclass 34, count 0 2006.183.08:00:50.58#ibcon#wrote, iclass 34, count 0 2006.183.08:00:50.58#ibcon#about to read 3, iclass 34, count 0 2006.183.08:00:50.60#ibcon#read 3, iclass 34, count 0 2006.183.08:00:50.60#ibcon#about to read 4, iclass 34, count 0 2006.183.08:00:50.60#ibcon#read 4, iclass 34, count 0 2006.183.08:00:50.60#ibcon#about to read 5, iclass 34, count 0 2006.183.08:00:50.60#ibcon#read 5, iclass 34, count 0 2006.183.08:00:50.60#ibcon#about to read 6, iclass 34, count 0 2006.183.08:00:50.60#ibcon#read 6, iclass 34, count 0 2006.183.08:00:50.60#ibcon#end of sib2, iclass 34, count 0 2006.183.08:00:50.60#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:00:50.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:00:50.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:00:50.60#ibcon#*before write, iclass 34, count 0 2006.183.08:00:50.60#ibcon#enter sib2, iclass 34, count 0 2006.183.08:00:50.60#ibcon#flushed, iclass 34, count 0 2006.183.08:00:50.60#ibcon#about to write, iclass 34, count 0 2006.183.08:00:50.60#ibcon#wrote, iclass 34, count 0 2006.183.08:00:50.60#ibcon#about to read 3, iclass 34, count 0 2006.183.08:00:50.65#ibcon#read 3, iclass 34, count 0 2006.183.08:00:50.65#ibcon#about to read 4, iclass 34, count 0 2006.183.08:00:50.65#ibcon#read 4, iclass 34, count 0 2006.183.08:00:50.65#ibcon#about to read 5, iclass 34, count 0 2006.183.08:00:50.65#ibcon#read 5, iclass 34, count 0 2006.183.08:00:50.65#ibcon#about to read 6, iclass 34, count 0 2006.183.08:00:50.65#ibcon#read 6, iclass 34, count 0 2006.183.08:00:50.65#ibcon#end of sib2, iclass 34, count 0 2006.183.08:00:50.65#ibcon#*after write, iclass 34, count 0 2006.183.08:00:50.65#ibcon#*before return 0, iclass 34, count 0 2006.183.08:00:50.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:50.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:00:50.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:00:50.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:00:50.65$vc4f8/vb=1,4 2006.183.08:00:50.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.08:00:50.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.08:00:50.65#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:50.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:50.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:50.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:50.65#ibcon#enter wrdev, iclass 36, count 2 2006.183.08:00:50.65#ibcon#first serial, iclass 36, count 2 2006.183.08:00:50.65#ibcon#enter sib2, iclass 36, count 2 2006.183.08:00:50.65#ibcon#flushed, iclass 36, count 2 2006.183.08:00:50.65#ibcon#about to write, iclass 36, count 2 2006.183.08:00:50.65#ibcon#wrote, iclass 36, count 2 2006.183.08:00:50.65#ibcon#about to read 3, iclass 36, count 2 2006.183.08:00:50.67#ibcon#read 3, iclass 36, count 2 2006.183.08:00:50.67#ibcon#about to read 4, iclass 36, count 2 2006.183.08:00:50.67#ibcon#read 4, iclass 36, count 2 2006.183.08:00:50.67#ibcon#about to read 5, iclass 36, count 2 2006.183.08:00:50.67#ibcon#read 5, iclass 36, count 2 2006.183.08:00:50.67#ibcon#about to read 6, iclass 36, count 2 2006.183.08:00:50.67#ibcon#read 6, iclass 36, count 2 2006.183.08:00:50.67#ibcon#end of sib2, iclass 36, count 2 2006.183.08:00:50.67#ibcon#*mode == 0, iclass 36, count 2 2006.183.08:00:50.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.08:00:50.67#ibcon#[27=AT01-04\r\n] 2006.183.08:00:50.67#ibcon#*before write, iclass 36, count 2 2006.183.08:00:50.67#ibcon#enter sib2, iclass 36, count 2 2006.183.08:00:50.67#ibcon#flushed, iclass 36, count 2 2006.183.08:00:50.67#ibcon#about to write, iclass 36, count 2 2006.183.08:00:50.67#ibcon#wrote, iclass 36, count 2 2006.183.08:00:50.67#ibcon#about to read 3, iclass 36, count 2 2006.183.08:00:50.70#ibcon#read 3, iclass 36, count 2 2006.183.08:00:50.70#ibcon#about to read 4, iclass 36, count 2 2006.183.08:00:50.70#ibcon#read 4, iclass 36, count 2 2006.183.08:00:50.70#ibcon#about to read 5, iclass 36, count 2 2006.183.08:00:50.70#ibcon#read 5, iclass 36, count 2 2006.183.08:00:50.70#ibcon#about to read 6, iclass 36, count 2 2006.183.08:00:50.70#ibcon#read 6, iclass 36, count 2 2006.183.08:00:50.70#ibcon#end of sib2, iclass 36, count 2 2006.183.08:00:50.70#ibcon#*after write, iclass 36, count 2 2006.183.08:00:50.70#ibcon#*before return 0, iclass 36, count 2 2006.183.08:00:50.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:50.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:00:50.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.08:00:50.70#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:50.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:50.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:50.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:50.82#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:00:50.82#ibcon#first serial, iclass 36, count 0 2006.183.08:00:50.82#ibcon#enter sib2, iclass 36, count 0 2006.183.08:00:50.82#ibcon#flushed, iclass 36, count 0 2006.183.08:00:50.82#ibcon#about to write, iclass 36, count 0 2006.183.08:00:50.82#ibcon#wrote, iclass 36, count 0 2006.183.08:00:50.82#ibcon#about to read 3, iclass 36, count 0 2006.183.08:00:50.84#ibcon#read 3, iclass 36, count 0 2006.183.08:00:50.84#ibcon#about to read 4, iclass 36, count 0 2006.183.08:00:50.84#ibcon#read 4, iclass 36, count 0 2006.183.08:00:50.84#ibcon#about to read 5, iclass 36, count 0 2006.183.08:00:50.84#ibcon#read 5, iclass 36, count 0 2006.183.08:00:50.84#ibcon#about to read 6, iclass 36, count 0 2006.183.08:00:50.84#ibcon#read 6, iclass 36, count 0 2006.183.08:00:50.84#ibcon#end of sib2, iclass 36, count 0 2006.183.08:00:50.84#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:00:50.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:00:50.84#ibcon#[27=USB\r\n] 2006.183.08:00:50.84#ibcon#*before write, iclass 36, count 0 2006.183.08:00:50.84#ibcon#enter sib2, iclass 36, count 0 2006.183.08:00:50.84#ibcon#flushed, iclass 36, count 0 2006.183.08:00:50.84#ibcon#about to write, iclass 36, count 0 2006.183.08:00:50.84#ibcon#wrote, iclass 36, count 0 2006.183.08:00:50.84#ibcon#about to read 3, iclass 36, count 0 2006.183.08:00:50.87#ibcon#read 3, iclass 36, count 0 2006.183.08:00:50.87#ibcon#about to read 4, iclass 36, count 0 2006.183.08:00:50.87#ibcon#read 4, iclass 36, count 0 2006.183.08:00:50.87#ibcon#about to read 5, iclass 36, count 0 2006.183.08:00:50.87#ibcon#read 5, iclass 36, count 0 2006.183.08:00:50.87#ibcon#about to read 6, iclass 36, count 0 2006.183.08:00:50.87#ibcon#read 6, iclass 36, count 0 2006.183.08:00:50.87#ibcon#end of sib2, iclass 36, count 0 2006.183.08:00:50.87#ibcon#*after write, iclass 36, count 0 2006.183.08:00:50.87#ibcon#*before return 0, iclass 36, count 0 2006.183.08:00:50.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:50.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:00:50.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:00:50.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:00:50.87$vc4f8/vblo=2,640.99 2006.183.08:00:50.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.08:00:50.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.08:00:50.87#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:50.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:00:50.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:00:50.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:00:50.87#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:00:50.87#ibcon#first serial, iclass 38, count 0 2006.183.08:00:50.87#ibcon#enter sib2, iclass 38, count 0 2006.183.08:00:50.87#ibcon#flushed, iclass 38, count 0 2006.183.08:00:50.87#ibcon#about to write, iclass 38, count 0 2006.183.08:00:50.87#ibcon#wrote, iclass 38, count 0 2006.183.08:00:50.87#ibcon#about to read 3, iclass 38, count 0 2006.183.08:00:50.89#ibcon#read 3, iclass 38, count 0 2006.183.08:00:50.89#ibcon#about to read 4, iclass 38, count 0 2006.183.08:00:50.89#ibcon#read 4, iclass 38, count 0 2006.183.08:00:50.89#ibcon#about to read 5, iclass 38, count 0 2006.183.08:00:50.89#ibcon#read 5, iclass 38, count 0 2006.183.08:00:50.89#ibcon#about to read 6, iclass 38, count 0 2006.183.08:00:50.89#ibcon#read 6, iclass 38, count 0 2006.183.08:00:50.89#ibcon#end of sib2, iclass 38, count 0 2006.183.08:00:50.89#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:00:50.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:00:50.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:00:50.89#ibcon#*before write, iclass 38, count 0 2006.183.08:00:50.89#ibcon#enter sib2, iclass 38, count 0 2006.183.08:00:50.89#ibcon#flushed, iclass 38, count 0 2006.183.08:00:50.89#ibcon#about to write, iclass 38, count 0 2006.183.08:00:50.89#ibcon#wrote, iclass 38, count 0 2006.183.08:00:50.89#ibcon#about to read 3, iclass 38, count 0 2006.183.08:00:50.93#ibcon#read 3, iclass 38, count 0 2006.183.08:00:50.93#ibcon#about to read 4, iclass 38, count 0 2006.183.08:00:50.93#ibcon#read 4, iclass 38, count 0 2006.183.08:00:50.93#ibcon#about to read 5, iclass 38, count 0 2006.183.08:00:50.93#ibcon#read 5, iclass 38, count 0 2006.183.08:00:50.93#ibcon#about to read 6, iclass 38, count 0 2006.183.08:00:50.93#ibcon#read 6, iclass 38, count 0 2006.183.08:00:50.93#ibcon#end of sib2, iclass 38, count 0 2006.183.08:00:50.93#ibcon#*after write, iclass 38, count 0 2006.183.08:00:50.93#ibcon#*before return 0, iclass 38, count 0 2006.183.08:00:50.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:00:50.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:00:50.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:00:50.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:00:50.93$vc4f8/vb=2,4 2006.183.08:00:50.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.08:00:50.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.08:00:50.93#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:50.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:00:50.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:00:50.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:00:50.99#ibcon#enter wrdev, iclass 40, count 2 2006.183.08:00:50.99#ibcon#first serial, iclass 40, count 2 2006.183.08:00:50.99#ibcon#enter sib2, iclass 40, count 2 2006.183.08:00:50.99#ibcon#flushed, iclass 40, count 2 2006.183.08:00:50.99#ibcon#about to write, iclass 40, count 2 2006.183.08:00:50.99#ibcon#wrote, iclass 40, count 2 2006.183.08:00:50.99#ibcon#about to read 3, iclass 40, count 2 2006.183.08:00:51.01#ibcon#read 3, iclass 40, count 2 2006.183.08:00:51.01#ibcon#about to read 4, iclass 40, count 2 2006.183.08:00:51.01#ibcon#read 4, iclass 40, count 2 2006.183.08:00:51.01#ibcon#about to read 5, iclass 40, count 2 2006.183.08:00:51.01#ibcon#read 5, iclass 40, count 2 2006.183.08:00:51.01#ibcon#about to read 6, iclass 40, count 2 2006.183.08:00:51.01#ibcon#read 6, iclass 40, count 2 2006.183.08:00:51.01#ibcon#end of sib2, iclass 40, count 2 2006.183.08:00:51.01#ibcon#*mode == 0, iclass 40, count 2 2006.183.08:00:51.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.08:00:51.01#ibcon#[27=AT02-04\r\n] 2006.183.08:00:51.01#ibcon#*before write, iclass 40, count 2 2006.183.08:00:51.01#ibcon#enter sib2, iclass 40, count 2 2006.183.08:00:51.01#ibcon#flushed, iclass 40, count 2 2006.183.08:00:51.01#ibcon#about to write, iclass 40, count 2 2006.183.08:00:51.01#ibcon#wrote, iclass 40, count 2 2006.183.08:00:51.01#ibcon#about to read 3, iclass 40, count 2 2006.183.08:00:51.04#ibcon#read 3, iclass 40, count 2 2006.183.08:00:51.04#ibcon#about to read 4, iclass 40, count 2 2006.183.08:00:51.04#ibcon#read 4, iclass 40, count 2 2006.183.08:00:51.04#ibcon#about to read 5, iclass 40, count 2 2006.183.08:00:51.04#ibcon#read 5, iclass 40, count 2 2006.183.08:00:51.04#ibcon#about to read 6, iclass 40, count 2 2006.183.08:00:51.04#ibcon#read 6, iclass 40, count 2 2006.183.08:00:51.04#ibcon#end of sib2, iclass 40, count 2 2006.183.08:00:51.04#ibcon#*after write, iclass 40, count 2 2006.183.08:00:51.04#ibcon#*before return 0, iclass 40, count 2 2006.183.08:00:51.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:00:51.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:00:51.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.08:00:51.04#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:51.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:00:51.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:00:51.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:00:51.16#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:00:51.16#ibcon#first serial, iclass 40, count 0 2006.183.08:00:51.16#ibcon#enter sib2, iclass 40, count 0 2006.183.08:00:51.16#ibcon#flushed, iclass 40, count 0 2006.183.08:00:51.16#ibcon#about to write, iclass 40, count 0 2006.183.08:00:51.16#ibcon#wrote, iclass 40, count 0 2006.183.08:00:51.16#ibcon#about to read 3, iclass 40, count 0 2006.183.08:00:51.18#ibcon#read 3, iclass 40, count 0 2006.183.08:00:51.18#ibcon#about to read 4, iclass 40, count 0 2006.183.08:00:51.18#ibcon#read 4, iclass 40, count 0 2006.183.08:00:51.18#ibcon#about to read 5, iclass 40, count 0 2006.183.08:00:51.18#ibcon#read 5, iclass 40, count 0 2006.183.08:00:51.18#ibcon#about to read 6, iclass 40, count 0 2006.183.08:00:51.18#ibcon#read 6, iclass 40, count 0 2006.183.08:00:51.18#ibcon#end of sib2, iclass 40, count 0 2006.183.08:00:51.18#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:00:51.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:00:51.18#ibcon#[27=USB\r\n] 2006.183.08:00:51.18#ibcon#*before write, iclass 40, count 0 2006.183.08:00:51.18#ibcon#enter sib2, iclass 40, count 0 2006.183.08:00:51.18#ibcon#flushed, iclass 40, count 0 2006.183.08:00:51.18#ibcon#about to write, iclass 40, count 0 2006.183.08:00:51.18#ibcon#wrote, iclass 40, count 0 2006.183.08:00:51.18#ibcon#about to read 3, iclass 40, count 0 2006.183.08:00:51.21#ibcon#read 3, iclass 40, count 0 2006.183.08:00:51.21#ibcon#about to read 4, iclass 40, count 0 2006.183.08:00:51.21#ibcon#read 4, iclass 40, count 0 2006.183.08:00:51.21#ibcon#about to read 5, iclass 40, count 0 2006.183.08:00:51.21#ibcon#read 5, iclass 40, count 0 2006.183.08:00:51.21#ibcon#about to read 6, iclass 40, count 0 2006.183.08:00:51.21#ibcon#read 6, iclass 40, count 0 2006.183.08:00:51.21#ibcon#end of sib2, iclass 40, count 0 2006.183.08:00:51.21#ibcon#*after write, iclass 40, count 0 2006.183.08:00:51.21#ibcon#*before return 0, iclass 40, count 0 2006.183.08:00:51.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:00:51.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:00:51.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:00:51.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:00:51.21$vc4f8/vblo=3,656.99 2006.183.08:00:51.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.08:00:51.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.08:00:51.21#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:51.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:00:51.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:00:51.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:00:51.21#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:00:51.21#ibcon#first serial, iclass 4, count 0 2006.183.08:00:51.21#ibcon#enter sib2, iclass 4, count 0 2006.183.08:00:51.21#ibcon#flushed, iclass 4, count 0 2006.183.08:00:51.21#ibcon#about to write, iclass 4, count 0 2006.183.08:00:51.21#ibcon#wrote, iclass 4, count 0 2006.183.08:00:51.21#ibcon#about to read 3, iclass 4, count 0 2006.183.08:00:51.23#ibcon#read 3, iclass 4, count 0 2006.183.08:00:51.23#ibcon#about to read 4, iclass 4, count 0 2006.183.08:00:51.23#ibcon#read 4, iclass 4, count 0 2006.183.08:00:51.23#ibcon#about to read 5, iclass 4, count 0 2006.183.08:00:51.23#ibcon#read 5, iclass 4, count 0 2006.183.08:00:51.23#ibcon#about to read 6, iclass 4, count 0 2006.183.08:00:51.23#ibcon#read 6, iclass 4, count 0 2006.183.08:00:51.23#ibcon#end of sib2, iclass 4, count 0 2006.183.08:00:51.23#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:00:51.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:00:51.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:00:51.23#ibcon#*before write, iclass 4, count 0 2006.183.08:00:51.23#ibcon#enter sib2, iclass 4, count 0 2006.183.08:00:51.23#ibcon#flushed, iclass 4, count 0 2006.183.08:00:51.23#ibcon#about to write, iclass 4, count 0 2006.183.08:00:51.23#ibcon#wrote, iclass 4, count 0 2006.183.08:00:51.23#ibcon#about to read 3, iclass 4, count 0 2006.183.08:00:51.27#ibcon#read 3, iclass 4, count 0 2006.183.08:00:51.27#ibcon#about to read 4, iclass 4, count 0 2006.183.08:00:51.27#ibcon#read 4, iclass 4, count 0 2006.183.08:00:51.27#ibcon#about to read 5, iclass 4, count 0 2006.183.08:00:51.27#ibcon#read 5, iclass 4, count 0 2006.183.08:00:51.27#ibcon#about to read 6, iclass 4, count 0 2006.183.08:00:51.27#ibcon#read 6, iclass 4, count 0 2006.183.08:00:51.27#ibcon#end of sib2, iclass 4, count 0 2006.183.08:00:51.27#ibcon#*after write, iclass 4, count 0 2006.183.08:00:51.27#ibcon#*before return 0, iclass 4, count 0 2006.183.08:00:51.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:00:51.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:00:51.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:00:51.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:00:51.27$vc4f8/vb=3,4 2006.183.08:00:51.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.08:00:51.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.08:00:51.27#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:51.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:51.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:51.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:51.33#ibcon#enter wrdev, iclass 6, count 2 2006.183.08:00:51.33#ibcon#first serial, iclass 6, count 2 2006.183.08:00:51.33#ibcon#enter sib2, iclass 6, count 2 2006.183.08:00:51.33#ibcon#flushed, iclass 6, count 2 2006.183.08:00:51.33#ibcon#about to write, iclass 6, count 2 2006.183.08:00:51.33#ibcon#wrote, iclass 6, count 2 2006.183.08:00:51.33#ibcon#about to read 3, iclass 6, count 2 2006.183.08:00:51.35#ibcon#read 3, iclass 6, count 2 2006.183.08:00:51.35#ibcon#about to read 4, iclass 6, count 2 2006.183.08:00:51.35#ibcon#read 4, iclass 6, count 2 2006.183.08:00:51.35#ibcon#about to read 5, iclass 6, count 2 2006.183.08:00:51.35#ibcon#read 5, iclass 6, count 2 2006.183.08:00:51.35#ibcon#about to read 6, iclass 6, count 2 2006.183.08:00:51.35#ibcon#read 6, iclass 6, count 2 2006.183.08:00:51.35#ibcon#end of sib2, iclass 6, count 2 2006.183.08:00:51.35#ibcon#*mode == 0, iclass 6, count 2 2006.183.08:00:51.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.08:00:51.35#ibcon#[27=AT03-04\r\n] 2006.183.08:00:51.35#ibcon#*before write, iclass 6, count 2 2006.183.08:00:51.35#ibcon#enter sib2, iclass 6, count 2 2006.183.08:00:51.35#ibcon#flushed, iclass 6, count 2 2006.183.08:00:51.35#ibcon#about to write, iclass 6, count 2 2006.183.08:00:51.35#ibcon#wrote, iclass 6, count 2 2006.183.08:00:51.35#ibcon#about to read 3, iclass 6, count 2 2006.183.08:00:51.38#ibcon#read 3, iclass 6, count 2 2006.183.08:00:51.38#ibcon#about to read 4, iclass 6, count 2 2006.183.08:00:51.38#ibcon#read 4, iclass 6, count 2 2006.183.08:00:51.38#ibcon#about to read 5, iclass 6, count 2 2006.183.08:00:51.38#ibcon#read 5, iclass 6, count 2 2006.183.08:00:51.38#ibcon#about to read 6, iclass 6, count 2 2006.183.08:00:51.38#ibcon#read 6, iclass 6, count 2 2006.183.08:00:51.38#ibcon#end of sib2, iclass 6, count 2 2006.183.08:00:51.38#ibcon#*after write, iclass 6, count 2 2006.183.08:00:51.38#ibcon#*before return 0, iclass 6, count 2 2006.183.08:00:51.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:51.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:00:51.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.08:00:51.38#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:51.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:51.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:51.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:51.50#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:00:51.50#ibcon#first serial, iclass 6, count 0 2006.183.08:00:51.50#ibcon#enter sib2, iclass 6, count 0 2006.183.08:00:51.50#ibcon#flushed, iclass 6, count 0 2006.183.08:00:51.50#ibcon#about to write, iclass 6, count 0 2006.183.08:00:51.50#ibcon#wrote, iclass 6, count 0 2006.183.08:00:51.50#ibcon#about to read 3, iclass 6, count 0 2006.183.08:00:51.52#ibcon#read 3, iclass 6, count 0 2006.183.08:00:51.52#ibcon#about to read 4, iclass 6, count 0 2006.183.08:00:51.52#ibcon#read 4, iclass 6, count 0 2006.183.08:00:51.52#ibcon#about to read 5, iclass 6, count 0 2006.183.08:00:51.52#ibcon#read 5, iclass 6, count 0 2006.183.08:00:51.52#ibcon#about to read 6, iclass 6, count 0 2006.183.08:00:51.52#ibcon#read 6, iclass 6, count 0 2006.183.08:00:51.52#ibcon#end of sib2, iclass 6, count 0 2006.183.08:00:51.52#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:00:51.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:00:51.52#ibcon#[27=USB\r\n] 2006.183.08:00:51.52#ibcon#*before write, iclass 6, count 0 2006.183.08:00:51.52#ibcon#enter sib2, iclass 6, count 0 2006.183.08:00:51.52#ibcon#flushed, iclass 6, count 0 2006.183.08:00:51.52#ibcon#about to write, iclass 6, count 0 2006.183.08:00:51.52#ibcon#wrote, iclass 6, count 0 2006.183.08:00:51.52#ibcon#about to read 3, iclass 6, count 0 2006.183.08:00:51.55#ibcon#read 3, iclass 6, count 0 2006.183.08:00:51.55#ibcon#about to read 4, iclass 6, count 0 2006.183.08:00:51.55#ibcon#read 4, iclass 6, count 0 2006.183.08:00:51.55#ibcon#about to read 5, iclass 6, count 0 2006.183.08:00:51.55#ibcon#read 5, iclass 6, count 0 2006.183.08:00:51.55#ibcon#about to read 6, iclass 6, count 0 2006.183.08:00:51.55#ibcon#read 6, iclass 6, count 0 2006.183.08:00:51.55#ibcon#end of sib2, iclass 6, count 0 2006.183.08:00:51.55#ibcon#*after write, iclass 6, count 0 2006.183.08:00:51.55#ibcon#*before return 0, iclass 6, count 0 2006.183.08:00:51.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:51.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:00:51.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:00:51.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:00:51.55$vc4f8/vblo=4,712.99 2006.183.08:00:51.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.08:00:51.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.08:00:51.55#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:51.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:51.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:51.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:51.55#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:00:51.55#ibcon#first serial, iclass 10, count 0 2006.183.08:00:51.55#ibcon#enter sib2, iclass 10, count 0 2006.183.08:00:51.55#ibcon#flushed, iclass 10, count 0 2006.183.08:00:51.55#ibcon#about to write, iclass 10, count 0 2006.183.08:00:51.55#ibcon#wrote, iclass 10, count 0 2006.183.08:00:51.55#ibcon#about to read 3, iclass 10, count 0 2006.183.08:00:51.57#ibcon#read 3, iclass 10, count 0 2006.183.08:00:51.57#ibcon#about to read 4, iclass 10, count 0 2006.183.08:00:51.57#ibcon#read 4, iclass 10, count 0 2006.183.08:00:51.57#ibcon#about to read 5, iclass 10, count 0 2006.183.08:00:51.57#ibcon#read 5, iclass 10, count 0 2006.183.08:00:51.57#ibcon#about to read 6, iclass 10, count 0 2006.183.08:00:51.57#ibcon#read 6, iclass 10, count 0 2006.183.08:00:51.57#ibcon#end of sib2, iclass 10, count 0 2006.183.08:00:51.57#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:00:51.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:00:51.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:00:51.57#ibcon#*before write, iclass 10, count 0 2006.183.08:00:51.57#ibcon#enter sib2, iclass 10, count 0 2006.183.08:00:51.57#ibcon#flushed, iclass 10, count 0 2006.183.08:00:51.57#ibcon#about to write, iclass 10, count 0 2006.183.08:00:51.57#ibcon#wrote, iclass 10, count 0 2006.183.08:00:51.57#ibcon#about to read 3, iclass 10, count 0 2006.183.08:00:51.61#ibcon#read 3, iclass 10, count 0 2006.183.08:00:51.61#ibcon#about to read 4, iclass 10, count 0 2006.183.08:00:51.61#ibcon#read 4, iclass 10, count 0 2006.183.08:00:51.61#ibcon#about to read 5, iclass 10, count 0 2006.183.08:00:51.61#ibcon#read 5, iclass 10, count 0 2006.183.08:00:51.61#ibcon#about to read 6, iclass 10, count 0 2006.183.08:00:51.61#ibcon#read 6, iclass 10, count 0 2006.183.08:00:51.61#ibcon#end of sib2, iclass 10, count 0 2006.183.08:00:51.61#ibcon#*after write, iclass 10, count 0 2006.183.08:00:51.61#ibcon#*before return 0, iclass 10, count 0 2006.183.08:00:51.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:51.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:00:51.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:00:51.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:00:51.61$vc4f8/vb=4,4 2006.183.08:00:51.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.08:00:51.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.08:00:51.61#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:51.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:51.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:51.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:51.67#ibcon#enter wrdev, iclass 12, count 2 2006.183.08:00:51.67#ibcon#first serial, iclass 12, count 2 2006.183.08:00:51.67#ibcon#enter sib2, iclass 12, count 2 2006.183.08:00:51.67#ibcon#flushed, iclass 12, count 2 2006.183.08:00:51.67#ibcon#about to write, iclass 12, count 2 2006.183.08:00:51.67#ibcon#wrote, iclass 12, count 2 2006.183.08:00:51.67#ibcon#about to read 3, iclass 12, count 2 2006.183.08:00:51.69#ibcon#read 3, iclass 12, count 2 2006.183.08:00:51.69#ibcon#about to read 4, iclass 12, count 2 2006.183.08:00:51.69#ibcon#read 4, iclass 12, count 2 2006.183.08:00:51.69#ibcon#about to read 5, iclass 12, count 2 2006.183.08:00:51.69#ibcon#read 5, iclass 12, count 2 2006.183.08:00:51.69#ibcon#about to read 6, iclass 12, count 2 2006.183.08:00:51.69#ibcon#read 6, iclass 12, count 2 2006.183.08:00:51.69#ibcon#end of sib2, iclass 12, count 2 2006.183.08:00:51.69#ibcon#*mode == 0, iclass 12, count 2 2006.183.08:00:51.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.08:00:51.69#ibcon#[27=AT04-04\r\n] 2006.183.08:00:51.69#ibcon#*before write, iclass 12, count 2 2006.183.08:00:51.69#ibcon#enter sib2, iclass 12, count 2 2006.183.08:00:51.69#ibcon#flushed, iclass 12, count 2 2006.183.08:00:51.69#ibcon#about to write, iclass 12, count 2 2006.183.08:00:51.69#ibcon#wrote, iclass 12, count 2 2006.183.08:00:51.69#ibcon#about to read 3, iclass 12, count 2 2006.183.08:00:51.72#ibcon#read 3, iclass 12, count 2 2006.183.08:00:51.72#ibcon#about to read 4, iclass 12, count 2 2006.183.08:00:51.72#ibcon#read 4, iclass 12, count 2 2006.183.08:00:51.72#ibcon#about to read 5, iclass 12, count 2 2006.183.08:00:51.72#ibcon#read 5, iclass 12, count 2 2006.183.08:00:51.72#ibcon#about to read 6, iclass 12, count 2 2006.183.08:00:51.72#ibcon#read 6, iclass 12, count 2 2006.183.08:00:51.72#ibcon#end of sib2, iclass 12, count 2 2006.183.08:00:51.72#ibcon#*after write, iclass 12, count 2 2006.183.08:00:51.72#ibcon#*before return 0, iclass 12, count 2 2006.183.08:00:51.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:51.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:00:51.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.08:00:51.72#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:51.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:51.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:51.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:51.84#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:00:51.84#ibcon#first serial, iclass 12, count 0 2006.183.08:00:51.84#ibcon#enter sib2, iclass 12, count 0 2006.183.08:00:51.84#ibcon#flushed, iclass 12, count 0 2006.183.08:00:51.84#ibcon#about to write, iclass 12, count 0 2006.183.08:00:51.84#ibcon#wrote, iclass 12, count 0 2006.183.08:00:51.84#ibcon#about to read 3, iclass 12, count 0 2006.183.08:00:51.86#ibcon#read 3, iclass 12, count 0 2006.183.08:00:51.86#ibcon#about to read 4, iclass 12, count 0 2006.183.08:00:51.86#ibcon#read 4, iclass 12, count 0 2006.183.08:00:51.86#ibcon#about to read 5, iclass 12, count 0 2006.183.08:00:51.86#ibcon#read 5, iclass 12, count 0 2006.183.08:00:51.86#ibcon#about to read 6, iclass 12, count 0 2006.183.08:00:51.86#ibcon#read 6, iclass 12, count 0 2006.183.08:00:51.86#ibcon#end of sib2, iclass 12, count 0 2006.183.08:00:51.86#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:00:51.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:00:51.86#ibcon#[27=USB\r\n] 2006.183.08:00:51.86#ibcon#*before write, iclass 12, count 0 2006.183.08:00:51.86#ibcon#enter sib2, iclass 12, count 0 2006.183.08:00:51.86#ibcon#flushed, iclass 12, count 0 2006.183.08:00:51.86#ibcon#about to write, iclass 12, count 0 2006.183.08:00:51.86#ibcon#wrote, iclass 12, count 0 2006.183.08:00:51.86#ibcon#about to read 3, iclass 12, count 0 2006.183.08:00:51.89#ibcon#read 3, iclass 12, count 0 2006.183.08:00:51.89#ibcon#about to read 4, iclass 12, count 0 2006.183.08:00:51.89#ibcon#read 4, iclass 12, count 0 2006.183.08:00:51.89#ibcon#about to read 5, iclass 12, count 0 2006.183.08:00:51.89#ibcon#read 5, iclass 12, count 0 2006.183.08:00:51.89#ibcon#about to read 6, iclass 12, count 0 2006.183.08:00:51.89#ibcon#read 6, iclass 12, count 0 2006.183.08:00:51.89#ibcon#end of sib2, iclass 12, count 0 2006.183.08:00:51.89#ibcon#*after write, iclass 12, count 0 2006.183.08:00:51.89#ibcon#*before return 0, iclass 12, count 0 2006.183.08:00:51.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:51.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:00:51.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:00:51.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:00:51.89$vc4f8/vblo=5,744.99 2006.183.08:00:51.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:00:51.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:00:51.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:51.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:51.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:51.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:51.89#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:00:51.89#ibcon#first serial, iclass 14, count 0 2006.183.08:00:51.89#ibcon#enter sib2, iclass 14, count 0 2006.183.08:00:51.89#ibcon#flushed, iclass 14, count 0 2006.183.08:00:51.89#ibcon#about to write, iclass 14, count 0 2006.183.08:00:51.89#ibcon#wrote, iclass 14, count 0 2006.183.08:00:51.89#ibcon#about to read 3, iclass 14, count 0 2006.183.08:00:51.91#ibcon#read 3, iclass 14, count 0 2006.183.08:00:51.91#ibcon#about to read 4, iclass 14, count 0 2006.183.08:00:51.91#ibcon#read 4, iclass 14, count 0 2006.183.08:00:51.91#ibcon#about to read 5, iclass 14, count 0 2006.183.08:00:51.91#ibcon#read 5, iclass 14, count 0 2006.183.08:00:51.91#ibcon#about to read 6, iclass 14, count 0 2006.183.08:00:51.91#ibcon#read 6, iclass 14, count 0 2006.183.08:00:51.91#ibcon#end of sib2, iclass 14, count 0 2006.183.08:00:51.91#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:00:51.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:00:51.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:00:51.91#ibcon#*before write, iclass 14, count 0 2006.183.08:00:51.91#ibcon#enter sib2, iclass 14, count 0 2006.183.08:00:51.91#ibcon#flushed, iclass 14, count 0 2006.183.08:00:51.91#ibcon#about to write, iclass 14, count 0 2006.183.08:00:51.91#ibcon#wrote, iclass 14, count 0 2006.183.08:00:51.91#ibcon#about to read 3, iclass 14, count 0 2006.183.08:00:51.95#ibcon#read 3, iclass 14, count 0 2006.183.08:00:51.95#ibcon#about to read 4, iclass 14, count 0 2006.183.08:00:51.95#ibcon#read 4, iclass 14, count 0 2006.183.08:00:51.95#ibcon#about to read 5, iclass 14, count 0 2006.183.08:00:51.95#ibcon#read 5, iclass 14, count 0 2006.183.08:00:51.95#ibcon#about to read 6, iclass 14, count 0 2006.183.08:00:51.95#ibcon#read 6, iclass 14, count 0 2006.183.08:00:51.95#ibcon#end of sib2, iclass 14, count 0 2006.183.08:00:51.95#ibcon#*after write, iclass 14, count 0 2006.183.08:00:51.95#ibcon#*before return 0, iclass 14, count 0 2006.183.08:00:51.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:51.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:00:51.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:00:51.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:00:51.95$vc4f8/vb=5,4 2006.183.08:00:51.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.08:00:51.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.08:00:51.95#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:51.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:52.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:52.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:52.01#ibcon#enter wrdev, iclass 16, count 2 2006.183.08:00:52.01#ibcon#first serial, iclass 16, count 2 2006.183.08:00:52.01#ibcon#enter sib2, iclass 16, count 2 2006.183.08:00:52.01#ibcon#flushed, iclass 16, count 2 2006.183.08:00:52.01#ibcon#about to write, iclass 16, count 2 2006.183.08:00:52.01#ibcon#wrote, iclass 16, count 2 2006.183.08:00:52.01#ibcon#about to read 3, iclass 16, count 2 2006.183.08:00:52.03#ibcon#read 3, iclass 16, count 2 2006.183.08:00:52.03#ibcon#about to read 4, iclass 16, count 2 2006.183.08:00:52.03#ibcon#read 4, iclass 16, count 2 2006.183.08:00:52.03#ibcon#about to read 5, iclass 16, count 2 2006.183.08:00:52.03#ibcon#read 5, iclass 16, count 2 2006.183.08:00:52.03#ibcon#about to read 6, iclass 16, count 2 2006.183.08:00:52.03#ibcon#read 6, iclass 16, count 2 2006.183.08:00:52.03#ibcon#end of sib2, iclass 16, count 2 2006.183.08:00:52.03#ibcon#*mode == 0, iclass 16, count 2 2006.183.08:00:52.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.08:00:52.03#ibcon#[27=AT05-04\r\n] 2006.183.08:00:52.03#ibcon#*before write, iclass 16, count 2 2006.183.08:00:52.03#ibcon#enter sib2, iclass 16, count 2 2006.183.08:00:52.03#ibcon#flushed, iclass 16, count 2 2006.183.08:00:52.03#ibcon#about to write, iclass 16, count 2 2006.183.08:00:52.03#ibcon#wrote, iclass 16, count 2 2006.183.08:00:52.03#ibcon#about to read 3, iclass 16, count 2 2006.183.08:00:52.06#ibcon#read 3, iclass 16, count 2 2006.183.08:00:52.06#ibcon#about to read 4, iclass 16, count 2 2006.183.08:00:52.06#ibcon#read 4, iclass 16, count 2 2006.183.08:00:52.06#ibcon#about to read 5, iclass 16, count 2 2006.183.08:00:52.06#ibcon#read 5, iclass 16, count 2 2006.183.08:00:52.06#ibcon#about to read 6, iclass 16, count 2 2006.183.08:00:52.06#ibcon#read 6, iclass 16, count 2 2006.183.08:00:52.06#ibcon#end of sib2, iclass 16, count 2 2006.183.08:00:52.06#ibcon#*after write, iclass 16, count 2 2006.183.08:00:52.06#ibcon#*before return 0, iclass 16, count 2 2006.183.08:00:52.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:52.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:00:52.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.08:00:52.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:52.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:52.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:52.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:52.18#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:00:52.18#ibcon#first serial, iclass 16, count 0 2006.183.08:00:52.18#ibcon#enter sib2, iclass 16, count 0 2006.183.08:00:52.18#ibcon#flushed, iclass 16, count 0 2006.183.08:00:52.18#ibcon#about to write, iclass 16, count 0 2006.183.08:00:52.18#ibcon#wrote, iclass 16, count 0 2006.183.08:00:52.18#ibcon#about to read 3, iclass 16, count 0 2006.183.08:00:52.20#ibcon#read 3, iclass 16, count 0 2006.183.08:00:52.20#ibcon#about to read 4, iclass 16, count 0 2006.183.08:00:52.20#ibcon#read 4, iclass 16, count 0 2006.183.08:00:52.20#ibcon#about to read 5, iclass 16, count 0 2006.183.08:00:52.20#ibcon#read 5, iclass 16, count 0 2006.183.08:00:52.20#ibcon#about to read 6, iclass 16, count 0 2006.183.08:00:52.20#ibcon#read 6, iclass 16, count 0 2006.183.08:00:52.20#ibcon#end of sib2, iclass 16, count 0 2006.183.08:00:52.20#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:00:52.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:00:52.20#ibcon#[27=USB\r\n] 2006.183.08:00:52.20#ibcon#*before write, iclass 16, count 0 2006.183.08:00:52.20#ibcon#enter sib2, iclass 16, count 0 2006.183.08:00:52.20#ibcon#flushed, iclass 16, count 0 2006.183.08:00:52.20#ibcon#about to write, iclass 16, count 0 2006.183.08:00:52.20#ibcon#wrote, iclass 16, count 0 2006.183.08:00:52.20#ibcon#about to read 3, iclass 16, count 0 2006.183.08:00:52.23#ibcon#read 3, iclass 16, count 0 2006.183.08:00:52.23#ibcon#about to read 4, iclass 16, count 0 2006.183.08:00:52.23#ibcon#read 4, iclass 16, count 0 2006.183.08:00:52.23#ibcon#about to read 5, iclass 16, count 0 2006.183.08:00:52.23#ibcon#read 5, iclass 16, count 0 2006.183.08:00:52.23#ibcon#about to read 6, iclass 16, count 0 2006.183.08:00:52.23#ibcon#read 6, iclass 16, count 0 2006.183.08:00:52.23#ibcon#end of sib2, iclass 16, count 0 2006.183.08:00:52.23#ibcon#*after write, iclass 16, count 0 2006.183.08:00:52.23#ibcon#*before return 0, iclass 16, count 0 2006.183.08:00:52.23#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:52.23#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:00:52.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:00:52.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:00:52.23$vc4f8/vblo=6,752.99 2006.183.08:00:52.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:00:52.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:00:52.23#ibcon#ireg 17 cls_cnt 0 2006.183.08:00:52.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:52.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:52.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:52.23#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:00:52.23#ibcon#first serial, iclass 18, count 0 2006.183.08:00:52.23#ibcon#enter sib2, iclass 18, count 0 2006.183.08:00:52.23#ibcon#flushed, iclass 18, count 0 2006.183.08:00:52.23#ibcon#about to write, iclass 18, count 0 2006.183.08:00:52.23#ibcon#wrote, iclass 18, count 0 2006.183.08:00:52.23#ibcon#about to read 3, iclass 18, count 0 2006.183.08:00:52.25#ibcon#read 3, iclass 18, count 0 2006.183.08:00:52.25#ibcon#about to read 4, iclass 18, count 0 2006.183.08:00:52.25#ibcon#read 4, iclass 18, count 0 2006.183.08:00:52.25#ibcon#about to read 5, iclass 18, count 0 2006.183.08:00:52.25#ibcon#read 5, iclass 18, count 0 2006.183.08:00:52.25#ibcon#about to read 6, iclass 18, count 0 2006.183.08:00:52.25#ibcon#read 6, iclass 18, count 0 2006.183.08:00:52.25#ibcon#end of sib2, iclass 18, count 0 2006.183.08:00:52.25#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:00:52.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:00:52.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:00:52.25#ibcon#*before write, iclass 18, count 0 2006.183.08:00:52.25#ibcon#enter sib2, iclass 18, count 0 2006.183.08:00:52.25#ibcon#flushed, iclass 18, count 0 2006.183.08:00:52.25#ibcon#about to write, iclass 18, count 0 2006.183.08:00:52.25#ibcon#wrote, iclass 18, count 0 2006.183.08:00:52.25#ibcon#about to read 3, iclass 18, count 0 2006.183.08:00:52.29#ibcon#read 3, iclass 18, count 0 2006.183.08:00:52.29#ibcon#about to read 4, iclass 18, count 0 2006.183.08:00:52.29#ibcon#read 4, iclass 18, count 0 2006.183.08:00:52.29#ibcon#about to read 5, iclass 18, count 0 2006.183.08:00:52.29#ibcon#read 5, iclass 18, count 0 2006.183.08:00:52.29#ibcon#about to read 6, iclass 18, count 0 2006.183.08:00:52.29#ibcon#read 6, iclass 18, count 0 2006.183.08:00:52.29#ibcon#end of sib2, iclass 18, count 0 2006.183.08:00:52.29#ibcon#*after write, iclass 18, count 0 2006.183.08:00:52.29#ibcon#*before return 0, iclass 18, count 0 2006.183.08:00:52.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:52.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:00:52.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:00:52.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:00:52.29$vc4f8/vb=6,4 2006.183.08:00:52.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.08:00:52.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.08:00:52.29#ibcon#ireg 11 cls_cnt 2 2006.183.08:00:52.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:52.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:52.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:52.35#ibcon#enter wrdev, iclass 20, count 2 2006.183.08:00:52.35#ibcon#first serial, iclass 20, count 2 2006.183.08:00:52.35#ibcon#enter sib2, iclass 20, count 2 2006.183.08:00:52.35#ibcon#flushed, iclass 20, count 2 2006.183.08:00:52.35#ibcon#about to write, iclass 20, count 2 2006.183.08:00:52.35#ibcon#wrote, iclass 20, count 2 2006.183.08:00:52.35#ibcon#about to read 3, iclass 20, count 2 2006.183.08:00:52.37#ibcon#read 3, iclass 20, count 2 2006.183.08:00:52.37#ibcon#about to read 4, iclass 20, count 2 2006.183.08:00:52.37#ibcon#read 4, iclass 20, count 2 2006.183.08:00:52.37#ibcon#about to read 5, iclass 20, count 2 2006.183.08:00:52.37#ibcon#read 5, iclass 20, count 2 2006.183.08:00:52.37#ibcon#about to read 6, iclass 20, count 2 2006.183.08:00:52.37#ibcon#read 6, iclass 20, count 2 2006.183.08:00:52.37#ibcon#end of sib2, iclass 20, count 2 2006.183.08:00:52.37#ibcon#*mode == 0, iclass 20, count 2 2006.183.08:00:52.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.08:00:52.37#ibcon#[27=AT06-04\r\n] 2006.183.08:00:52.37#ibcon#*before write, iclass 20, count 2 2006.183.08:00:52.37#ibcon#enter sib2, iclass 20, count 2 2006.183.08:00:52.37#ibcon#flushed, iclass 20, count 2 2006.183.08:00:52.37#ibcon#about to write, iclass 20, count 2 2006.183.08:00:52.37#ibcon#wrote, iclass 20, count 2 2006.183.08:00:52.37#ibcon#about to read 3, iclass 20, count 2 2006.183.08:00:52.40#ibcon#read 3, iclass 20, count 2 2006.183.08:00:52.40#ibcon#about to read 4, iclass 20, count 2 2006.183.08:00:52.40#ibcon#read 4, iclass 20, count 2 2006.183.08:00:52.40#ibcon#about to read 5, iclass 20, count 2 2006.183.08:00:52.40#ibcon#read 5, iclass 20, count 2 2006.183.08:00:52.40#ibcon#about to read 6, iclass 20, count 2 2006.183.08:00:52.40#ibcon#read 6, iclass 20, count 2 2006.183.08:00:52.40#ibcon#end of sib2, iclass 20, count 2 2006.183.08:00:52.40#ibcon#*after write, iclass 20, count 2 2006.183.08:00:52.40#ibcon#*before return 0, iclass 20, count 2 2006.183.08:00:52.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:52.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:00:52.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.08:00:52.40#ibcon#ireg 7 cls_cnt 0 2006.183.08:00:52.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:52.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:52.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:52.52#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:00:52.52#ibcon#first serial, iclass 20, count 0 2006.183.08:00:52.52#ibcon#enter sib2, iclass 20, count 0 2006.183.08:00:52.52#ibcon#flushed, iclass 20, count 0 2006.183.08:00:52.52#ibcon#about to write, iclass 20, count 0 2006.183.08:00:52.52#ibcon#wrote, iclass 20, count 0 2006.183.08:00:52.52#ibcon#about to read 3, iclass 20, count 0 2006.183.08:00:52.54#ibcon#read 3, iclass 20, count 0 2006.183.08:00:52.54#ibcon#about to read 4, iclass 20, count 0 2006.183.08:00:52.54#ibcon#read 4, iclass 20, count 0 2006.183.08:00:52.54#ibcon#about to read 5, iclass 20, count 0 2006.183.08:00:52.54#ibcon#read 5, iclass 20, count 0 2006.183.08:00:52.54#ibcon#about to read 6, iclass 20, count 0 2006.183.08:00:52.54#ibcon#read 6, iclass 20, count 0 2006.183.08:00:52.54#ibcon#end of sib2, iclass 20, count 0 2006.183.08:00:52.54#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:00:52.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:00:52.54#ibcon#[27=USB\r\n] 2006.183.08:00:52.54#ibcon#*before write, iclass 20, count 0 2006.183.08:00:52.54#ibcon#enter sib2, iclass 20, count 0 2006.183.08:00:52.54#ibcon#flushed, iclass 20, count 0 2006.183.08:00:52.54#ibcon#about to write, iclass 20, count 0 2006.183.08:00:52.54#ibcon#wrote, iclass 20, count 0 2006.183.08:00:52.54#ibcon#about to read 3, iclass 20, count 0 2006.183.08:00:52.57#ibcon#read 3, iclass 20, count 0 2006.183.08:00:52.57#ibcon#about to read 4, iclass 20, count 0 2006.183.08:00:52.57#ibcon#read 4, iclass 20, count 0 2006.183.08:00:52.57#ibcon#about to read 5, iclass 20, count 0 2006.183.08:00:52.57#ibcon#read 5, iclass 20, count 0 2006.183.08:00:52.57#ibcon#about to read 6, iclass 20, count 0 2006.183.08:00:52.57#ibcon#read 6, iclass 20, count 0 2006.183.08:00:52.57#ibcon#end of sib2, iclass 20, count 0 2006.183.08:00:52.57#ibcon#*after write, iclass 20, count 0 2006.183.08:00:52.57#ibcon#*before return 0, iclass 20, count 0 2006.183.08:00:52.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:52.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:00:52.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:00:52.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:00:52.57$vc4f8/vabw=wide 2006.183.08:00:52.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.08:00:52.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.08:00:52.57#ibcon#ireg 8 cls_cnt 0 2006.183.08:00:52.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:52.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:52.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:52.57#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:00:52.57#ibcon#first serial, iclass 22, count 0 2006.183.08:00:52.57#ibcon#enter sib2, iclass 22, count 0 2006.183.08:00:52.57#ibcon#flushed, iclass 22, count 0 2006.183.08:00:52.57#ibcon#about to write, iclass 22, count 0 2006.183.08:00:52.57#ibcon#wrote, iclass 22, count 0 2006.183.08:00:52.57#ibcon#about to read 3, iclass 22, count 0 2006.183.08:00:52.59#ibcon#read 3, iclass 22, count 0 2006.183.08:00:52.59#ibcon#about to read 4, iclass 22, count 0 2006.183.08:00:52.59#ibcon#read 4, iclass 22, count 0 2006.183.08:00:52.59#ibcon#about to read 5, iclass 22, count 0 2006.183.08:00:52.59#ibcon#read 5, iclass 22, count 0 2006.183.08:00:52.59#ibcon#about to read 6, iclass 22, count 0 2006.183.08:00:52.59#ibcon#read 6, iclass 22, count 0 2006.183.08:00:52.59#ibcon#end of sib2, iclass 22, count 0 2006.183.08:00:52.59#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:00:52.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:00:52.59#ibcon#[25=BW32\r\n] 2006.183.08:00:52.59#ibcon#*before write, iclass 22, count 0 2006.183.08:00:52.59#ibcon#enter sib2, iclass 22, count 0 2006.183.08:00:52.59#ibcon#flushed, iclass 22, count 0 2006.183.08:00:52.59#ibcon#about to write, iclass 22, count 0 2006.183.08:00:52.59#ibcon#wrote, iclass 22, count 0 2006.183.08:00:52.59#ibcon#about to read 3, iclass 22, count 0 2006.183.08:00:52.62#ibcon#read 3, iclass 22, count 0 2006.183.08:00:52.62#ibcon#about to read 4, iclass 22, count 0 2006.183.08:00:52.62#ibcon#read 4, iclass 22, count 0 2006.183.08:00:52.62#ibcon#about to read 5, iclass 22, count 0 2006.183.08:00:52.62#ibcon#read 5, iclass 22, count 0 2006.183.08:00:52.62#ibcon#about to read 6, iclass 22, count 0 2006.183.08:00:52.62#ibcon#read 6, iclass 22, count 0 2006.183.08:00:52.62#ibcon#end of sib2, iclass 22, count 0 2006.183.08:00:52.62#ibcon#*after write, iclass 22, count 0 2006.183.08:00:52.62#ibcon#*before return 0, iclass 22, count 0 2006.183.08:00:52.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:52.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:00:52.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:00:52.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:00:52.62$vc4f8/vbbw=wide 2006.183.08:00:52.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.08:00:52.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.08:00:52.62#ibcon#ireg 8 cls_cnt 0 2006.183.08:00:52.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:00:52.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:00:52.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:00:52.69#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:00:52.69#ibcon#first serial, iclass 24, count 0 2006.183.08:00:52.69#ibcon#enter sib2, iclass 24, count 0 2006.183.08:00:52.69#ibcon#flushed, iclass 24, count 0 2006.183.08:00:52.69#ibcon#about to write, iclass 24, count 0 2006.183.08:00:52.69#ibcon#wrote, iclass 24, count 0 2006.183.08:00:52.69#ibcon#about to read 3, iclass 24, count 0 2006.183.08:00:52.71#ibcon#read 3, iclass 24, count 0 2006.183.08:00:52.71#ibcon#about to read 4, iclass 24, count 0 2006.183.08:00:52.71#ibcon#read 4, iclass 24, count 0 2006.183.08:00:52.71#ibcon#about to read 5, iclass 24, count 0 2006.183.08:00:52.71#ibcon#read 5, iclass 24, count 0 2006.183.08:00:52.71#ibcon#about to read 6, iclass 24, count 0 2006.183.08:00:52.71#ibcon#read 6, iclass 24, count 0 2006.183.08:00:52.71#ibcon#end of sib2, iclass 24, count 0 2006.183.08:00:52.71#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:00:52.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:00:52.71#ibcon#[27=BW32\r\n] 2006.183.08:00:52.71#ibcon#*before write, iclass 24, count 0 2006.183.08:00:52.71#ibcon#enter sib2, iclass 24, count 0 2006.183.08:00:52.71#ibcon#flushed, iclass 24, count 0 2006.183.08:00:52.71#ibcon#about to write, iclass 24, count 0 2006.183.08:00:52.71#ibcon#wrote, iclass 24, count 0 2006.183.08:00:52.71#ibcon#about to read 3, iclass 24, count 0 2006.183.08:00:52.74#ibcon#read 3, iclass 24, count 0 2006.183.08:00:52.74#ibcon#about to read 4, iclass 24, count 0 2006.183.08:00:52.74#ibcon#read 4, iclass 24, count 0 2006.183.08:00:52.74#ibcon#about to read 5, iclass 24, count 0 2006.183.08:00:52.74#ibcon#read 5, iclass 24, count 0 2006.183.08:00:52.74#ibcon#about to read 6, iclass 24, count 0 2006.183.08:00:52.74#ibcon#read 6, iclass 24, count 0 2006.183.08:00:52.74#ibcon#end of sib2, iclass 24, count 0 2006.183.08:00:52.74#ibcon#*after write, iclass 24, count 0 2006.183.08:00:52.74#ibcon#*before return 0, iclass 24, count 0 2006.183.08:00:52.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:00:52.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:00:52.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:00:52.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:00:52.74$4f8m12a/ifd4f 2006.183.08:00:52.74$ifd4f/lo= 2006.183.08:00:52.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:00:52.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:00:52.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:00:52.74$ifd4f/patch= 2006.183.08:00:52.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:00:52.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:00:52.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:00:52.74$4f8m12a/"form=m,16.000,1:2 2006.183.08:00:52.74$4f8m12a/"tpicd 2006.183.08:00:52.74$4f8m12a/echo=off 2006.183.08:00:52.74$4f8m12a/xlog=off 2006.183.08:00:52.74:!2006.183.08:01:50 2006.183.08:01:29.14#trakl#Source acquired 2006.183.08:01:29.14#flagr#flagr/antenna,acquired 2006.183.08:01:50.00:preob 2006.183.08:01:51.14/onsource/TRACKING 2006.183.08:01:51.14:!2006.183.08:02:00 2006.183.08:02:00.00:data_valid=on 2006.183.08:02:00.00:midob 2006.183.08:02:00.14/onsource/TRACKING 2006.183.08:02:00.14/wx/28.18,996.4,86 2006.183.08:02:00.24/cable/+6.4521E-03 2006.183.08:02:01.33/va/01,08,usb,yes,29,31 2006.183.08:02:01.33/va/02,07,usb,yes,29,31 2006.183.08:02:01.33/va/03,06,usb,yes,31,31 2006.183.08:02:01.33/va/04,07,usb,yes,30,32 2006.183.08:02:01.33/va/05,07,usb,yes,32,34 2006.183.08:02:01.33/va/06,06,usb,yes,31,31 2006.183.08:02:01.33/va/07,06,usb,yes,32,31 2006.183.08:02:01.33/va/08,07,usb,yes,30,29 2006.183.08:02:01.56/valo/01,532.99,yes,locked 2006.183.08:02:01.56/valo/02,572.99,yes,locked 2006.183.08:02:01.56/valo/03,672.99,yes,locked 2006.183.08:02:01.56/valo/04,832.99,yes,locked 2006.183.08:02:01.56/valo/05,652.99,yes,locked 2006.183.08:02:01.56/valo/06,772.99,yes,locked 2006.183.08:02:01.56/valo/07,832.99,yes,locked 2006.183.08:02:01.56/valo/08,852.99,yes,locked 2006.183.08:02:02.65/vb/01,04,usb,yes,29,28 2006.183.08:02:02.65/vb/02,04,usb,yes,31,32 2006.183.08:02:02.65/vb/03,04,usb,yes,27,31 2006.183.08:02:02.65/vb/04,04,usb,yes,28,28 2006.183.08:02:02.65/vb/05,04,usb,yes,27,31 2006.183.08:02:02.65/vb/06,04,usb,yes,28,31 2006.183.08:02:02.65/vb/07,04,usb,yes,30,30 2006.183.08:02:02.65/vb/08,04,usb,yes,27,31 2006.183.08:02:02.88/vblo/01,632.99,yes,locked 2006.183.08:02:02.88/vblo/02,640.99,yes,locked 2006.183.08:02:02.88/vblo/03,656.99,yes,locked 2006.183.08:02:02.88/vblo/04,712.99,yes,locked 2006.183.08:02:02.88/vblo/05,744.99,yes,locked 2006.183.08:02:02.88/vblo/06,752.99,yes,locked 2006.183.08:02:02.88/vblo/07,734.99,yes,locked 2006.183.08:02:02.88/vblo/08,744.99,yes,locked 2006.183.08:02:03.03/vabw/8 2006.183.08:02:03.18/vbbw/8 2006.183.08:02:03.27/xfe/off,on,15.2 2006.183.08:02:03.65/ifatt/23,28,28,28 2006.183.08:02:04.08/fmout-gps/S +3.33E-07 2006.183.08:02:04.12:!2006.183.08:03:00 2006.183.08:03:00.00:data_valid=off 2006.183.08:03:00.00:postob 2006.183.08:03:00.17/cable/+6.4514E-03 2006.183.08:03:00.17/wx/28.21,996.4,86 2006.183.08:03:01.08/fmout-gps/S +3.34E-07 2006.183.08:03:01.08:scan_name=183-0803,k06183,60 2006.183.08:03:01.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.183.08:03:01.14#flagr#flagr/antenna,new-source 2006.183.08:03:02.14:checkk5 2006.183.08:03:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:03:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:03:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:03:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:03:04.00/chk_obsdata//k5ts1/T1830802??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:03:04.37/chk_obsdata//k5ts2/T1830802??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:03:04.74/chk_obsdata//k5ts3/T1830802??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:03:05.11/chk_obsdata//k5ts4/T1830802??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:03:05.80/k5log//k5ts1_log_newline 2006.183.08:03:06.49/k5log//k5ts2_log_newline 2006.183.08:03:07.18/k5log//k5ts3_log_newline 2006.183.08:03:07.86/k5log//k5ts4_log_newline 2006.183.08:03:07.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:03:07.89:4f8m12a=2 2006.183.08:03:07.89$4f8m12a/echo=on 2006.183.08:03:07.89$4f8m12a/pcalon 2006.183.08:03:07.89$pcalon/"no phase cal control is implemented here 2006.183.08:03:07.89$4f8m12a/"tpicd=stop 2006.183.08:03:07.89$4f8m12a/vc4f8 2006.183.08:03:07.89$vc4f8/valo=1,532.99 2006.183.08:03:07.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.08:03:07.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.08:03:07.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:07.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:03:07.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:03:07.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:03:07.89#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:03:07.89#ibcon#first serial, iclass 5, count 0 2006.183.08:03:07.89#ibcon#enter sib2, iclass 5, count 0 2006.183.08:03:07.89#ibcon#flushed, iclass 5, count 0 2006.183.08:03:07.89#ibcon#about to write, iclass 5, count 0 2006.183.08:03:07.89#ibcon#wrote, iclass 5, count 0 2006.183.08:03:07.89#ibcon#about to read 3, iclass 5, count 0 2006.183.08:03:07.93#ibcon#read 3, iclass 5, count 0 2006.183.08:03:07.93#ibcon#about to read 4, iclass 5, count 0 2006.183.08:03:07.93#ibcon#read 4, iclass 5, count 0 2006.183.08:03:07.93#ibcon#about to read 5, iclass 5, count 0 2006.183.08:03:07.93#ibcon#read 5, iclass 5, count 0 2006.183.08:03:07.93#ibcon#about to read 6, iclass 5, count 0 2006.183.08:03:07.93#ibcon#read 6, iclass 5, count 0 2006.183.08:03:07.93#ibcon#end of sib2, iclass 5, count 0 2006.183.08:03:07.93#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:03:07.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:03:07.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:03:07.93#ibcon#*before write, iclass 5, count 0 2006.183.08:03:07.93#ibcon#enter sib2, iclass 5, count 0 2006.183.08:03:07.93#ibcon#flushed, iclass 5, count 0 2006.183.08:03:07.93#ibcon#about to write, iclass 5, count 0 2006.183.08:03:07.93#ibcon#wrote, iclass 5, count 0 2006.183.08:03:07.93#ibcon#about to read 3, iclass 5, count 0 2006.183.08:03:07.98#ibcon#read 3, iclass 5, count 0 2006.183.08:03:07.98#ibcon#about to read 4, iclass 5, count 0 2006.183.08:03:07.98#ibcon#read 4, iclass 5, count 0 2006.183.08:03:07.98#ibcon#about to read 5, iclass 5, count 0 2006.183.08:03:07.98#ibcon#read 5, iclass 5, count 0 2006.183.08:03:07.98#ibcon#about to read 6, iclass 5, count 0 2006.183.08:03:07.98#ibcon#read 6, iclass 5, count 0 2006.183.08:03:07.98#ibcon#end of sib2, iclass 5, count 0 2006.183.08:03:07.98#ibcon#*after write, iclass 5, count 0 2006.183.08:03:07.98#ibcon#*before return 0, iclass 5, count 0 2006.183.08:03:07.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:03:07.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:03:07.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:03:07.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:03:07.98$vc4f8/va=1,8 2006.183.08:03:07.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.08:03:07.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.08:03:07.98#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:07.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:07.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:07.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:07.98#ibcon#enter wrdev, iclass 7, count 2 2006.183.08:03:07.98#ibcon#first serial, iclass 7, count 2 2006.183.08:03:07.98#ibcon#enter sib2, iclass 7, count 2 2006.183.08:03:07.98#ibcon#flushed, iclass 7, count 2 2006.183.08:03:07.98#ibcon#about to write, iclass 7, count 2 2006.183.08:03:07.98#ibcon#wrote, iclass 7, count 2 2006.183.08:03:07.98#ibcon#about to read 3, iclass 7, count 2 2006.183.08:03:08.00#ibcon#read 3, iclass 7, count 2 2006.183.08:03:08.00#ibcon#about to read 4, iclass 7, count 2 2006.183.08:03:08.00#ibcon#read 4, iclass 7, count 2 2006.183.08:03:08.00#ibcon#about to read 5, iclass 7, count 2 2006.183.08:03:08.00#ibcon#read 5, iclass 7, count 2 2006.183.08:03:08.00#ibcon#about to read 6, iclass 7, count 2 2006.183.08:03:08.00#ibcon#read 6, iclass 7, count 2 2006.183.08:03:08.00#ibcon#end of sib2, iclass 7, count 2 2006.183.08:03:08.00#ibcon#*mode == 0, iclass 7, count 2 2006.183.08:03:08.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.08:03:08.00#ibcon#[25=AT01-08\r\n] 2006.183.08:03:08.00#ibcon#*before write, iclass 7, count 2 2006.183.08:03:08.00#ibcon#enter sib2, iclass 7, count 2 2006.183.08:03:08.00#ibcon#flushed, iclass 7, count 2 2006.183.08:03:08.00#ibcon#about to write, iclass 7, count 2 2006.183.08:03:08.00#ibcon#wrote, iclass 7, count 2 2006.183.08:03:08.00#ibcon#about to read 3, iclass 7, count 2 2006.183.08:03:08.03#ibcon#read 3, iclass 7, count 2 2006.183.08:03:08.03#ibcon#about to read 4, iclass 7, count 2 2006.183.08:03:08.03#ibcon#read 4, iclass 7, count 2 2006.183.08:03:08.03#ibcon#about to read 5, iclass 7, count 2 2006.183.08:03:08.03#ibcon#read 5, iclass 7, count 2 2006.183.08:03:08.03#ibcon#about to read 6, iclass 7, count 2 2006.183.08:03:08.03#ibcon#read 6, iclass 7, count 2 2006.183.08:03:08.03#ibcon#end of sib2, iclass 7, count 2 2006.183.08:03:08.03#ibcon#*after write, iclass 7, count 2 2006.183.08:03:08.03#ibcon#*before return 0, iclass 7, count 2 2006.183.08:03:08.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:08.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:08.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.08:03:08.03#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:08.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:08.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:08.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:08.15#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:03:08.15#ibcon#first serial, iclass 7, count 0 2006.183.08:03:08.15#ibcon#enter sib2, iclass 7, count 0 2006.183.08:03:08.15#ibcon#flushed, iclass 7, count 0 2006.183.08:03:08.15#ibcon#about to write, iclass 7, count 0 2006.183.08:03:08.15#ibcon#wrote, iclass 7, count 0 2006.183.08:03:08.15#ibcon#about to read 3, iclass 7, count 0 2006.183.08:03:08.17#ibcon#read 3, iclass 7, count 0 2006.183.08:03:08.17#ibcon#about to read 4, iclass 7, count 0 2006.183.08:03:08.17#ibcon#read 4, iclass 7, count 0 2006.183.08:03:08.17#ibcon#about to read 5, iclass 7, count 0 2006.183.08:03:08.17#ibcon#read 5, iclass 7, count 0 2006.183.08:03:08.17#ibcon#about to read 6, iclass 7, count 0 2006.183.08:03:08.17#ibcon#read 6, iclass 7, count 0 2006.183.08:03:08.17#ibcon#end of sib2, iclass 7, count 0 2006.183.08:03:08.17#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:03:08.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:03:08.17#ibcon#[25=USB\r\n] 2006.183.08:03:08.17#ibcon#*before write, iclass 7, count 0 2006.183.08:03:08.17#ibcon#enter sib2, iclass 7, count 0 2006.183.08:03:08.17#ibcon#flushed, iclass 7, count 0 2006.183.08:03:08.17#ibcon#about to write, iclass 7, count 0 2006.183.08:03:08.17#ibcon#wrote, iclass 7, count 0 2006.183.08:03:08.17#ibcon#about to read 3, iclass 7, count 0 2006.183.08:03:08.20#ibcon#read 3, iclass 7, count 0 2006.183.08:03:08.20#ibcon#about to read 4, iclass 7, count 0 2006.183.08:03:08.20#ibcon#read 4, iclass 7, count 0 2006.183.08:03:08.20#ibcon#about to read 5, iclass 7, count 0 2006.183.08:03:08.20#ibcon#read 5, iclass 7, count 0 2006.183.08:03:08.20#ibcon#about to read 6, iclass 7, count 0 2006.183.08:03:08.20#ibcon#read 6, iclass 7, count 0 2006.183.08:03:08.20#ibcon#end of sib2, iclass 7, count 0 2006.183.08:03:08.20#ibcon#*after write, iclass 7, count 0 2006.183.08:03:08.20#ibcon#*before return 0, iclass 7, count 0 2006.183.08:03:08.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:08.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:08.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:03:08.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:03:08.20$vc4f8/valo=2,572.99 2006.183.08:03:08.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:03:08.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:03:08.20#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:08.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:08.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:08.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:08.20#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:03:08.20#ibcon#first serial, iclass 11, count 0 2006.183.08:03:08.20#ibcon#enter sib2, iclass 11, count 0 2006.183.08:03:08.20#ibcon#flushed, iclass 11, count 0 2006.183.08:03:08.20#ibcon#about to write, iclass 11, count 0 2006.183.08:03:08.20#ibcon#wrote, iclass 11, count 0 2006.183.08:03:08.20#ibcon#about to read 3, iclass 11, count 0 2006.183.08:03:08.22#ibcon#read 3, iclass 11, count 0 2006.183.08:03:08.22#ibcon#about to read 4, iclass 11, count 0 2006.183.08:03:08.22#ibcon#read 4, iclass 11, count 0 2006.183.08:03:08.22#ibcon#about to read 5, iclass 11, count 0 2006.183.08:03:08.22#ibcon#read 5, iclass 11, count 0 2006.183.08:03:08.22#ibcon#about to read 6, iclass 11, count 0 2006.183.08:03:08.22#ibcon#read 6, iclass 11, count 0 2006.183.08:03:08.22#ibcon#end of sib2, iclass 11, count 0 2006.183.08:03:08.22#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:03:08.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:03:08.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:03:08.22#ibcon#*before write, iclass 11, count 0 2006.183.08:03:08.22#ibcon#enter sib2, iclass 11, count 0 2006.183.08:03:08.22#ibcon#flushed, iclass 11, count 0 2006.183.08:03:08.22#ibcon#about to write, iclass 11, count 0 2006.183.08:03:08.22#ibcon#wrote, iclass 11, count 0 2006.183.08:03:08.22#ibcon#about to read 3, iclass 11, count 0 2006.183.08:03:08.27#ibcon#read 3, iclass 11, count 0 2006.183.08:03:08.27#ibcon#about to read 4, iclass 11, count 0 2006.183.08:03:08.27#ibcon#read 4, iclass 11, count 0 2006.183.08:03:08.27#ibcon#about to read 5, iclass 11, count 0 2006.183.08:03:08.27#ibcon#read 5, iclass 11, count 0 2006.183.08:03:08.27#ibcon#about to read 6, iclass 11, count 0 2006.183.08:03:08.27#ibcon#read 6, iclass 11, count 0 2006.183.08:03:08.27#ibcon#end of sib2, iclass 11, count 0 2006.183.08:03:08.27#ibcon#*after write, iclass 11, count 0 2006.183.08:03:08.27#ibcon#*before return 0, iclass 11, count 0 2006.183.08:03:08.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:08.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:08.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:03:08.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:03:08.27$vc4f8/va=2,7 2006.183.08:03:08.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.08:03:08.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.08:03:08.27#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:08.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:08.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:08.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:08.32#ibcon#enter wrdev, iclass 13, count 2 2006.183.08:03:08.32#ibcon#first serial, iclass 13, count 2 2006.183.08:03:08.32#ibcon#enter sib2, iclass 13, count 2 2006.183.08:03:08.32#ibcon#flushed, iclass 13, count 2 2006.183.08:03:08.32#ibcon#about to write, iclass 13, count 2 2006.183.08:03:08.32#ibcon#wrote, iclass 13, count 2 2006.183.08:03:08.32#ibcon#about to read 3, iclass 13, count 2 2006.183.08:03:08.34#ibcon#read 3, iclass 13, count 2 2006.183.08:03:08.34#ibcon#about to read 4, iclass 13, count 2 2006.183.08:03:08.34#ibcon#read 4, iclass 13, count 2 2006.183.08:03:08.34#ibcon#about to read 5, iclass 13, count 2 2006.183.08:03:08.34#ibcon#read 5, iclass 13, count 2 2006.183.08:03:08.34#ibcon#about to read 6, iclass 13, count 2 2006.183.08:03:08.34#ibcon#read 6, iclass 13, count 2 2006.183.08:03:08.34#ibcon#end of sib2, iclass 13, count 2 2006.183.08:03:08.34#ibcon#*mode == 0, iclass 13, count 2 2006.183.08:03:08.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.08:03:08.34#ibcon#[25=AT02-07\r\n] 2006.183.08:03:08.34#ibcon#*before write, iclass 13, count 2 2006.183.08:03:08.34#ibcon#enter sib2, iclass 13, count 2 2006.183.08:03:08.34#ibcon#flushed, iclass 13, count 2 2006.183.08:03:08.34#ibcon#about to write, iclass 13, count 2 2006.183.08:03:08.34#ibcon#wrote, iclass 13, count 2 2006.183.08:03:08.34#ibcon#about to read 3, iclass 13, count 2 2006.183.08:03:08.37#ibcon#read 3, iclass 13, count 2 2006.183.08:03:08.37#ibcon#about to read 4, iclass 13, count 2 2006.183.08:03:08.37#ibcon#read 4, iclass 13, count 2 2006.183.08:03:08.37#ibcon#about to read 5, iclass 13, count 2 2006.183.08:03:08.37#ibcon#read 5, iclass 13, count 2 2006.183.08:03:08.37#ibcon#about to read 6, iclass 13, count 2 2006.183.08:03:08.37#ibcon#read 6, iclass 13, count 2 2006.183.08:03:08.37#ibcon#end of sib2, iclass 13, count 2 2006.183.08:03:08.37#ibcon#*after write, iclass 13, count 2 2006.183.08:03:08.37#ibcon#*before return 0, iclass 13, count 2 2006.183.08:03:08.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:08.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:08.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.08:03:08.37#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:08.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:08.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:08.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:08.49#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:03:08.49#ibcon#first serial, iclass 13, count 0 2006.183.08:03:08.49#ibcon#enter sib2, iclass 13, count 0 2006.183.08:03:08.49#ibcon#flushed, iclass 13, count 0 2006.183.08:03:08.49#ibcon#about to write, iclass 13, count 0 2006.183.08:03:08.49#ibcon#wrote, iclass 13, count 0 2006.183.08:03:08.49#ibcon#about to read 3, iclass 13, count 0 2006.183.08:03:08.51#ibcon#read 3, iclass 13, count 0 2006.183.08:03:08.51#ibcon#about to read 4, iclass 13, count 0 2006.183.08:03:08.51#ibcon#read 4, iclass 13, count 0 2006.183.08:03:08.51#ibcon#about to read 5, iclass 13, count 0 2006.183.08:03:08.51#ibcon#read 5, iclass 13, count 0 2006.183.08:03:08.51#ibcon#about to read 6, iclass 13, count 0 2006.183.08:03:08.51#ibcon#read 6, iclass 13, count 0 2006.183.08:03:08.51#ibcon#end of sib2, iclass 13, count 0 2006.183.08:03:08.51#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:03:08.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:03:08.51#ibcon#[25=USB\r\n] 2006.183.08:03:08.51#ibcon#*before write, iclass 13, count 0 2006.183.08:03:08.51#ibcon#enter sib2, iclass 13, count 0 2006.183.08:03:08.51#ibcon#flushed, iclass 13, count 0 2006.183.08:03:08.51#ibcon#about to write, iclass 13, count 0 2006.183.08:03:08.51#ibcon#wrote, iclass 13, count 0 2006.183.08:03:08.51#ibcon#about to read 3, iclass 13, count 0 2006.183.08:03:08.54#ibcon#read 3, iclass 13, count 0 2006.183.08:03:08.54#ibcon#about to read 4, iclass 13, count 0 2006.183.08:03:08.54#ibcon#read 4, iclass 13, count 0 2006.183.08:03:08.54#ibcon#about to read 5, iclass 13, count 0 2006.183.08:03:08.54#ibcon#read 5, iclass 13, count 0 2006.183.08:03:08.54#ibcon#about to read 6, iclass 13, count 0 2006.183.08:03:08.54#ibcon#read 6, iclass 13, count 0 2006.183.08:03:08.54#ibcon#end of sib2, iclass 13, count 0 2006.183.08:03:08.54#ibcon#*after write, iclass 13, count 0 2006.183.08:03:08.54#ibcon#*before return 0, iclass 13, count 0 2006.183.08:03:08.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:08.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:08.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:03:08.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:03:08.54$vc4f8/valo=3,672.99 2006.183.08:03:08.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.08:03:08.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.08:03:08.54#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:08.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:08.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:08.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:08.54#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:03:08.54#ibcon#first serial, iclass 15, count 0 2006.183.08:03:08.54#ibcon#enter sib2, iclass 15, count 0 2006.183.08:03:08.54#ibcon#flushed, iclass 15, count 0 2006.183.08:03:08.54#ibcon#about to write, iclass 15, count 0 2006.183.08:03:08.54#ibcon#wrote, iclass 15, count 0 2006.183.08:03:08.54#ibcon#about to read 3, iclass 15, count 0 2006.183.08:03:08.56#ibcon#read 3, iclass 15, count 0 2006.183.08:03:08.56#ibcon#about to read 4, iclass 15, count 0 2006.183.08:03:08.56#ibcon#read 4, iclass 15, count 0 2006.183.08:03:08.56#ibcon#about to read 5, iclass 15, count 0 2006.183.08:03:08.56#ibcon#read 5, iclass 15, count 0 2006.183.08:03:08.56#ibcon#about to read 6, iclass 15, count 0 2006.183.08:03:08.56#ibcon#read 6, iclass 15, count 0 2006.183.08:03:08.56#ibcon#end of sib2, iclass 15, count 0 2006.183.08:03:08.56#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:03:08.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:03:08.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:03:08.56#ibcon#*before write, iclass 15, count 0 2006.183.08:03:08.56#ibcon#enter sib2, iclass 15, count 0 2006.183.08:03:08.56#ibcon#flushed, iclass 15, count 0 2006.183.08:03:08.56#ibcon#about to write, iclass 15, count 0 2006.183.08:03:08.56#ibcon#wrote, iclass 15, count 0 2006.183.08:03:08.56#ibcon#about to read 3, iclass 15, count 0 2006.183.08:03:08.60#ibcon#read 3, iclass 15, count 0 2006.183.08:03:08.60#ibcon#about to read 4, iclass 15, count 0 2006.183.08:03:08.60#ibcon#read 4, iclass 15, count 0 2006.183.08:03:08.60#ibcon#about to read 5, iclass 15, count 0 2006.183.08:03:08.60#ibcon#read 5, iclass 15, count 0 2006.183.08:03:08.60#ibcon#about to read 6, iclass 15, count 0 2006.183.08:03:08.60#ibcon#read 6, iclass 15, count 0 2006.183.08:03:08.60#ibcon#end of sib2, iclass 15, count 0 2006.183.08:03:08.60#ibcon#*after write, iclass 15, count 0 2006.183.08:03:08.60#ibcon#*before return 0, iclass 15, count 0 2006.183.08:03:08.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:08.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:08.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:03:08.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:03:08.60$vc4f8/va=3,6 2006.183.08:03:08.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.08:03:08.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.08:03:08.60#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:08.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:08.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:08.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:08.66#ibcon#enter wrdev, iclass 17, count 2 2006.183.08:03:08.66#ibcon#first serial, iclass 17, count 2 2006.183.08:03:08.66#ibcon#enter sib2, iclass 17, count 2 2006.183.08:03:08.66#ibcon#flushed, iclass 17, count 2 2006.183.08:03:08.66#ibcon#about to write, iclass 17, count 2 2006.183.08:03:08.66#ibcon#wrote, iclass 17, count 2 2006.183.08:03:08.66#ibcon#about to read 3, iclass 17, count 2 2006.183.08:03:08.68#ibcon#read 3, iclass 17, count 2 2006.183.08:03:08.68#ibcon#about to read 4, iclass 17, count 2 2006.183.08:03:08.68#ibcon#read 4, iclass 17, count 2 2006.183.08:03:08.68#ibcon#about to read 5, iclass 17, count 2 2006.183.08:03:08.68#ibcon#read 5, iclass 17, count 2 2006.183.08:03:08.68#ibcon#about to read 6, iclass 17, count 2 2006.183.08:03:08.68#ibcon#read 6, iclass 17, count 2 2006.183.08:03:08.68#ibcon#end of sib2, iclass 17, count 2 2006.183.08:03:08.68#ibcon#*mode == 0, iclass 17, count 2 2006.183.08:03:08.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.08:03:08.68#ibcon#[25=AT03-06\r\n] 2006.183.08:03:08.68#ibcon#*before write, iclass 17, count 2 2006.183.08:03:08.68#ibcon#enter sib2, iclass 17, count 2 2006.183.08:03:08.68#ibcon#flushed, iclass 17, count 2 2006.183.08:03:08.68#ibcon#about to write, iclass 17, count 2 2006.183.08:03:08.68#ibcon#wrote, iclass 17, count 2 2006.183.08:03:08.68#ibcon#about to read 3, iclass 17, count 2 2006.183.08:03:08.71#ibcon#read 3, iclass 17, count 2 2006.183.08:03:08.71#ibcon#about to read 4, iclass 17, count 2 2006.183.08:03:08.71#ibcon#read 4, iclass 17, count 2 2006.183.08:03:08.71#ibcon#about to read 5, iclass 17, count 2 2006.183.08:03:08.71#ibcon#read 5, iclass 17, count 2 2006.183.08:03:08.71#ibcon#about to read 6, iclass 17, count 2 2006.183.08:03:08.71#ibcon#read 6, iclass 17, count 2 2006.183.08:03:08.71#ibcon#end of sib2, iclass 17, count 2 2006.183.08:03:08.71#ibcon#*after write, iclass 17, count 2 2006.183.08:03:08.71#ibcon#*before return 0, iclass 17, count 2 2006.183.08:03:08.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:08.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:08.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.08:03:08.71#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:08.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:08.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:08.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:08.83#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:03:08.83#ibcon#first serial, iclass 17, count 0 2006.183.08:03:08.83#ibcon#enter sib2, iclass 17, count 0 2006.183.08:03:08.83#ibcon#flushed, iclass 17, count 0 2006.183.08:03:08.83#ibcon#about to write, iclass 17, count 0 2006.183.08:03:08.83#ibcon#wrote, iclass 17, count 0 2006.183.08:03:08.83#ibcon#about to read 3, iclass 17, count 0 2006.183.08:03:08.85#ibcon#read 3, iclass 17, count 0 2006.183.08:03:08.85#ibcon#about to read 4, iclass 17, count 0 2006.183.08:03:08.85#ibcon#read 4, iclass 17, count 0 2006.183.08:03:08.85#ibcon#about to read 5, iclass 17, count 0 2006.183.08:03:08.85#ibcon#read 5, iclass 17, count 0 2006.183.08:03:08.85#ibcon#about to read 6, iclass 17, count 0 2006.183.08:03:08.85#ibcon#read 6, iclass 17, count 0 2006.183.08:03:08.85#ibcon#end of sib2, iclass 17, count 0 2006.183.08:03:08.85#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:03:08.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:03:08.85#ibcon#[25=USB\r\n] 2006.183.08:03:08.85#ibcon#*before write, iclass 17, count 0 2006.183.08:03:08.85#ibcon#enter sib2, iclass 17, count 0 2006.183.08:03:08.85#ibcon#flushed, iclass 17, count 0 2006.183.08:03:08.85#ibcon#about to write, iclass 17, count 0 2006.183.08:03:08.85#ibcon#wrote, iclass 17, count 0 2006.183.08:03:08.85#ibcon#about to read 3, iclass 17, count 0 2006.183.08:03:08.88#ibcon#read 3, iclass 17, count 0 2006.183.08:03:08.88#ibcon#about to read 4, iclass 17, count 0 2006.183.08:03:08.88#ibcon#read 4, iclass 17, count 0 2006.183.08:03:08.88#ibcon#about to read 5, iclass 17, count 0 2006.183.08:03:08.88#ibcon#read 5, iclass 17, count 0 2006.183.08:03:08.88#ibcon#about to read 6, iclass 17, count 0 2006.183.08:03:08.88#ibcon#read 6, iclass 17, count 0 2006.183.08:03:08.88#ibcon#end of sib2, iclass 17, count 0 2006.183.08:03:08.88#ibcon#*after write, iclass 17, count 0 2006.183.08:03:08.88#ibcon#*before return 0, iclass 17, count 0 2006.183.08:03:08.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:08.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:08.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:03:08.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:03:08.88$vc4f8/valo=4,832.99 2006.183.08:03:08.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.08:03:08.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.08:03:08.88#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:08.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:08.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:08.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:08.88#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:03:08.88#ibcon#first serial, iclass 19, count 0 2006.183.08:03:08.88#ibcon#enter sib2, iclass 19, count 0 2006.183.08:03:08.88#ibcon#flushed, iclass 19, count 0 2006.183.08:03:08.88#ibcon#about to write, iclass 19, count 0 2006.183.08:03:08.88#ibcon#wrote, iclass 19, count 0 2006.183.08:03:08.88#ibcon#about to read 3, iclass 19, count 0 2006.183.08:03:08.90#ibcon#read 3, iclass 19, count 0 2006.183.08:03:08.90#ibcon#about to read 4, iclass 19, count 0 2006.183.08:03:08.90#ibcon#read 4, iclass 19, count 0 2006.183.08:03:08.90#ibcon#about to read 5, iclass 19, count 0 2006.183.08:03:08.90#ibcon#read 5, iclass 19, count 0 2006.183.08:03:08.90#ibcon#about to read 6, iclass 19, count 0 2006.183.08:03:08.90#ibcon#read 6, iclass 19, count 0 2006.183.08:03:08.90#ibcon#end of sib2, iclass 19, count 0 2006.183.08:03:08.90#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:03:08.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:03:08.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:03:08.90#ibcon#*before write, iclass 19, count 0 2006.183.08:03:08.90#ibcon#enter sib2, iclass 19, count 0 2006.183.08:03:08.90#ibcon#flushed, iclass 19, count 0 2006.183.08:03:08.90#ibcon#about to write, iclass 19, count 0 2006.183.08:03:08.90#ibcon#wrote, iclass 19, count 0 2006.183.08:03:08.90#ibcon#about to read 3, iclass 19, count 0 2006.183.08:03:08.94#ibcon#read 3, iclass 19, count 0 2006.183.08:03:08.94#ibcon#about to read 4, iclass 19, count 0 2006.183.08:03:08.94#ibcon#read 4, iclass 19, count 0 2006.183.08:03:08.94#ibcon#about to read 5, iclass 19, count 0 2006.183.08:03:08.94#ibcon#read 5, iclass 19, count 0 2006.183.08:03:08.94#ibcon#about to read 6, iclass 19, count 0 2006.183.08:03:08.94#ibcon#read 6, iclass 19, count 0 2006.183.08:03:08.94#ibcon#end of sib2, iclass 19, count 0 2006.183.08:03:08.94#ibcon#*after write, iclass 19, count 0 2006.183.08:03:08.94#ibcon#*before return 0, iclass 19, count 0 2006.183.08:03:08.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:08.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:08.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:03:08.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:03:08.94$vc4f8/va=4,7 2006.183.08:03:08.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.08:03:08.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.08:03:08.94#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:08.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:09.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:09.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:09.00#ibcon#enter wrdev, iclass 21, count 2 2006.183.08:03:09.00#ibcon#first serial, iclass 21, count 2 2006.183.08:03:09.00#ibcon#enter sib2, iclass 21, count 2 2006.183.08:03:09.00#ibcon#flushed, iclass 21, count 2 2006.183.08:03:09.00#ibcon#about to write, iclass 21, count 2 2006.183.08:03:09.00#ibcon#wrote, iclass 21, count 2 2006.183.08:03:09.00#ibcon#about to read 3, iclass 21, count 2 2006.183.08:03:09.02#ibcon#read 3, iclass 21, count 2 2006.183.08:03:09.02#ibcon#about to read 4, iclass 21, count 2 2006.183.08:03:09.02#ibcon#read 4, iclass 21, count 2 2006.183.08:03:09.02#ibcon#about to read 5, iclass 21, count 2 2006.183.08:03:09.02#ibcon#read 5, iclass 21, count 2 2006.183.08:03:09.02#ibcon#about to read 6, iclass 21, count 2 2006.183.08:03:09.02#ibcon#read 6, iclass 21, count 2 2006.183.08:03:09.02#ibcon#end of sib2, iclass 21, count 2 2006.183.08:03:09.02#ibcon#*mode == 0, iclass 21, count 2 2006.183.08:03:09.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.08:03:09.02#ibcon#[25=AT04-07\r\n] 2006.183.08:03:09.02#ibcon#*before write, iclass 21, count 2 2006.183.08:03:09.02#ibcon#enter sib2, iclass 21, count 2 2006.183.08:03:09.02#ibcon#flushed, iclass 21, count 2 2006.183.08:03:09.02#ibcon#about to write, iclass 21, count 2 2006.183.08:03:09.02#ibcon#wrote, iclass 21, count 2 2006.183.08:03:09.02#ibcon#about to read 3, iclass 21, count 2 2006.183.08:03:09.05#ibcon#read 3, iclass 21, count 2 2006.183.08:03:09.05#ibcon#about to read 4, iclass 21, count 2 2006.183.08:03:09.05#ibcon#read 4, iclass 21, count 2 2006.183.08:03:09.05#ibcon#about to read 5, iclass 21, count 2 2006.183.08:03:09.05#ibcon#read 5, iclass 21, count 2 2006.183.08:03:09.05#ibcon#about to read 6, iclass 21, count 2 2006.183.08:03:09.05#ibcon#read 6, iclass 21, count 2 2006.183.08:03:09.05#ibcon#end of sib2, iclass 21, count 2 2006.183.08:03:09.05#ibcon#*after write, iclass 21, count 2 2006.183.08:03:09.05#ibcon#*before return 0, iclass 21, count 2 2006.183.08:03:09.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:09.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:09.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.08:03:09.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:09.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:09.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:09.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:09.17#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:03:09.17#ibcon#first serial, iclass 21, count 0 2006.183.08:03:09.17#ibcon#enter sib2, iclass 21, count 0 2006.183.08:03:09.17#ibcon#flushed, iclass 21, count 0 2006.183.08:03:09.17#ibcon#about to write, iclass 21, count 0 2006.183.08:03:09.17#ibcon#wrote, iclass 21, count 0 2006.183.08:03:09.17#ibcon#about to read 3, iclass 21, count 0 2006.183.08:03:09.19#ibcon#read 3, iclass 21, count 0 2006.183.08:03:09.19#ibcon#about to read 4, iclass 21, count 0 2006.183.08:03:09.19#ibcon#read 4, iclass 21, count 0 2006.183.08:03:09.19#ibcon#about to read 5, iclass 21, count 0 2006.183.08:03:09.19#ibcon#read 5, iclass 21, count 0 2006.183.08:03:09.19#ibcon#about to read 6, iclass 21, count 0 2006.183.08:03:09.19#ibcon#read 6, iclass 21, count 0 2006.183.08:03:09.19#ibcon#end of sib2, iclass 21, count 0 2006.183.08:03:09.19#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:03:09.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:03:09.19#ibcon#[25=USB\r\n] 2006.183.08:03:09.19#ibcon#*before write, iclass 21, count 0 2006.183.08:03:09.19#ibcon#enter sib2, iclass 21, count 0 2006.183.08:03:09.19#ibcon#flushed, iclass 21, count 0 2006.183.08:03:09.19#ibcon#about to write, iclass 21, count 0 2006.183.08:03:09.19#ibcon#wrote, iclass 21, count 0 2006.183.08:03:09.19#ibcon#about to read 3, iclass 21, count 0 2006.183.08:03:09.22#ibcon#read 3, iclass 21, count 0 2006.183.08:03:09.22#ibcon#about to read 4, iclass 21, count 0 2006.183.08:03:09.22#ibcon#read 4, iclass 21, count 0 2006.183.08:03:09.22#ibcon#about to read 5, iclass 21, count 0 2006.183.08:03:09.22#ibcon#read 5, iclass 21, count 0 2006.183.08:03:09.22#ibcon#about to read 6, iclass 21, count 0 2006.183.08:03:09.22#ibcon#read 6, iclass 21, count 0 2006.183.08:03:09.22#ibcon#end of sib2, iclass 21, count 0 2006.183.08:03:09.22#ibcon#*after write, iclass 21, count 0 2006.183.08:03:09.22#ibcon#*before return 0, iclass 21, count 0 2006.183.08:03:09.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:09.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:09.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:03:09.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:03:09.22$vc4f8/valo=5,652.99 2006.183.08:03:09.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:03:09.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:03:09.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:09.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:09.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:09.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:09.22#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:03:09.22#ibcon#first serial, iclass 23, count 0 2006.183.08:03:09.22#ibcon#enter sib2, iclass 23, count 0 2006.183.08:03:09.22#ibcon#flushed, iclass 23, count 0 2006.183.08:03:09.22#ibcon#about to write, iclass 23, count 0 2006.183.08:03:09.22#ibcon#wrote, iclass 23, count 0 2006.183.08:03:09.22#ibcon#about to read 3, iclass 23, count 0 2006.183.08:03:09.24#ibcon#read 3, iclass 23, count 0 2006.183.08:03:09.24#ibcon#about to read 4, iclass 23, count 0 2006.183.08:03:09.24#ibcon#read 4, iclass 23, count 0 2006.183.08:03:09.24#ibcon#about to read 5, iclass 23, count 0 2006.183.08:03:09.24#ibcon#read 5, iclass 23, count 0 2006.183.08:03:09.24#ibcon#about to read 6, iclass 23, count 0 2006.183.08:03:09.24#ibcon#read 6, iclass 23, count 0 2006.183.08:03:09.24#ibcon#end of sib2, iclass 23, count 0 2006.183.08:03:09.24#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:03:09.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:03:09.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:03:09.24#ibcon#*before write, iclass 23, count 0 2006.183.08:03:09.24#ibcon#enter sib2, iclass 23, count 0 2006.183.08:03:09.24#ibcon#flushed, iclass 23, count 0 2006.183.08:03:09.24#ibcon#about to write, iclass 23, count 0 2006.183.08:03:09.24#ibcon#wrote, iclass 23, count 0 2006.183.08:03:09.24#ibcon#about to read 3, iclass 23, count 0 2006.183.08:03:09.28#ibcon#read 3, iclass 23, count 0 2006.183.08:03:09.28#ibcon#about to read 4, iclass 23, count 0 2006.183.08:03:09.28#ibcon#read 4, iclass 23, count 0 2006.183.08:03:09.28#ibcon#about to read 5, iclass 23, count 0 2006.183.08:03:09.28#ibcon#read 5, iclass 23, count 0 2006.183.08:03:09.28#ibcon#about to read 6, iclass 23, count 0 2006.183.08:03:09.28#ibcon#read 6, iclass 23, count 0 2006.183.08:03:09.28#ibcon#end of sib2, iclass 23, count 0 2006.183.08:03:09.28#ibcon#*after write, iclass 23, count 0 2006.183.08:03:09.28#ibcon#*before return 0, iclass 23, count 0 2006.183.08:03:09.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:09.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:09.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:03:09.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:03:09.28$vc4f8/va=5,7 2006.183.08:03:09.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.08:03:09.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.08:03:09.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:09.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:09.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:09.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:09.34#ibcon#enter wrdev, iclass 25, count 2 2006.183.08:03:09.34#ibcon#first serial, iclass 25, count 2 2006.183.08:03:09.34#ibcon#enter sib2, iclass 25, count 2 2006.183.08:03:09.34#ibcon#flushed, iclass 25, count 2 2006.183.08:03:09.34#ibcon#about to write, iclass 25, count 2 2006.183.08:03:09.34#ibcon#wrote, iclass 25, count 2 2006.183.08:03:09.34#ibcon#about to read 3, iclass 25, count 2 2006.183.08:03:09.36#ibcon#read 3, iclass 25, count 2 2006.183.08:03:09.36#ibcon#about to read 4, iclass 25, count 2 2006.183.08:03:09.36#ibcon#read 4, iclass 25, count 2 2006.183.08:03:09.36#ibcon#about to read 5, iclass 25, count 2 2006.183.08:03:09.36#ibcon#read 5, iclass 25, count 2 2006.183.08:03:09.36#ibcon#about to read 6, iclass 25, count 2 2006.183.08:03:09.36#ibcon#read 6, iclass 25, count 2 2006.183.08:03:09.36#ibcon#end of sib2, iclass 25, count 2 2006.183.08:03:09.36#ibcon#*mode == 0, iclass 25, count 2 2006.183.08:03:09.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.08:03:09.36#ibcon#[25=AT05-07\r\n] 2006.183.08:03:09.36#ibcon#*before write, iclass 25, count 2 2006.183.08:03:09.36#ibcon#enter sib2, iclass 25, count 2 2006.183.08:03:09.36#ibcon#flushed, iclass 25, count 2 2006.183.08:03:09.36#ibcon#about to write, iclass 25, count 2 2006.183.08:03:09.36#ibcon#wrote, iclass 25, count 2 2006.183.08:03:09.36#ibcon#about to read 3, iclass 25, count 2 2006.183.08:03:09.39#ibcon#read 3, iclass 25, count 2 2006.183.08:03:09.39#ibcon#about to read 4, iclass 25, count 2 2006.183.08:03:09.39#ibcon#read 4, iclass 25, count 2 2006.183.08:03:09.39#ibcon#about to read 5, iclass 25, count 2 2006.183.08:03:09.39#ibcon#read 5, iclass 25, count 2 2006.183.08:03:09.39#ibcon#about to read 6, iclass 25, count 2 2006.183.08:03:09.39#ibcon#read 6, iclass 25, count 2 2006.183.08:03:09.39#ibcon#end of sib2, iclass 25, count 2 2006.183.08:03:09.39#ibcon#*after write, iclass 25, count 2 2006.183.08:03:09.39#ibcon#*before return 0, iclass 25, count 2 2006.183.08:03:09.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:09.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:09.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.08:03:09.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:09.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:09.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:09.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:09.51#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:03:09.51#ibcon#first serial, iclass 25, count 0 2006.183.08:03:09.51#ibcon#enter sib2, iclass 25, count 0 2006.183.08:03:09.51#ibcon#flushed, iclass 25, count 0 2006.183.08:03:09.51#ibcon#about to write, iclass 25, count 0 2006.183.08:03:09.51#ibcon#wrote, iclass 25, count 0 2006.183.08:03:09.51#ibcon#about to read 3, iclass 25, count 0 2006.183.08:03:09.53#ibcon#read 3, iclass 25, count 0 2006.183.08:03:09.53#ibcon#about to read 4, iclass 25, count 0 2006.183.08:03:09.53#ibcon#read 4, iclass 25, count 0 2006.183.08:03:09.53#ibcon#about to read 5, iclass 25, count 0 2006.183.08:03:09.53#ibcon#read 5, iclass 25, count 0 2006.183.08:03:09.53#ibcon#about to read 6, iclass 25, count 0 2006.183.08:03:09.53#ibcon#read 6, iclass 25, count 0 2006.183.08:03:09.53#ibcon#end of sib2, iclass 25, count 0 2006.183.08:03:09.53#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:03:09.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:03:09.53#ibcon#[25=USB\r\n] 2006.183.08:03:09.53#ibcon#*before write, iclass 25, count 0 2006.183.08:03:09.53#ibcon#enter sib2, iclass 25, count 0 2006.183.08:03:09.53#ibcon#flushed, iclass 25, count 0 2006.183.08:03:09.53#ibcon#about to write, iclass 25, count 0 2006.183.08:03:09.53#ibcon#wrote, iclass 25, count 0 2006.183.08:03:09.53#ibcon#about to read 3, iclass 25, count 0 2006.183.08:03:09.56#ibcon#read 3, iclass 25, count 0 2006.183.08:03:09.56#ibcon#about to read 4, iclass 25, count 0 2006.183.08:03:09.56#ibcon#read 4, iclass 25, count 0 2006.183.08:03:09.56#ibcon#about to read 5, iclass 25, count 0 2006.183.08:03:09.56#ibcon#read 5, iclass 25, count 0 2006.183.08:03:09.56#ibcon#about to read 6, iclass 25, count 0 2006.183.08:03:09.56#ibcon#read 6, iclass 25, count 0 2006.183.08:03:09.56#ibcon#end of sib2, iclass 25, count 0 2006.183.08:03:09.56#ibcon#*after write, iclass 25, count 0 2006.183.08:03:09.56#ibcon#*before return 0, iclass 25, count 0 2006.183.08:03:09.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:09.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:09.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:03:09.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:03:09.56$vc4f8/valo=6,772.99 2006.183.08:03:09.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.08:03:09.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.08:03:09.56#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:09.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:09.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:09.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:09.56#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:03:09.56#ibcon#first serial, iclass 27, count 0 2006.183.08:03:09.56#ibcon#enter sib2, iclass 27, count 0 2006.183.08:03:09.56#ibcon#flushed, iclass 27, count 0 2006.183.08:03:09.56#ibcon#about to write, iclass 27, count 0 2006.183.08:03:09.56#ibcon#wrote, iclass 27, count 0 2006.183.08:03:09.56#ibcon#about to read 3, iclass 27, count 0 2006.183.08:03:09.58#ibcon#read 3, iclass 27, count 0 2006.183.08:03:09.58#ibcon#about to read 4, iclass 27, count 0 2006.183.08:03:09.58#ibcon#read 4, iclass 27, count 0 2006.183.08:03:09.58#ibcon#about to read 5, iclass 27, count 0 2006.183.08:03:09.58#ibcon#read 5, iclass 27, count 0 2006.183.08:03:09.58#ibcon#about to read 6, iclass 27, count 0 2006.183.08:03:09.58#ibcon#read 6, iclass 27, count 0 2006.183.08:03:09.58#ibcon#end of sib2, iclass 27, count 0 2006.183.08:03:09.58#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:03:09.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:03:09.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:03:09.58#ibcon#*before write, iclass 27, count 0 2006.183.08:03:09.58#ibcon#enter sib2, iclass 27, count 0 2006.183.08:03:09.58#ibcon#flushed, iclass 27, count 0 2006.183.08:03:09.58#ibcon#about to write, iclass 27, count 0 2006.183.08:03:09.58#ibcon#wrote, iclass 27, count 0 2006.183.08:03:09.58#ibcon#about to read 3, iclass 27, count 0 2006.183.08:03:09.63#ibcon#read 3, iclass 27, count 0 2006.183.08:03:09.63#ibcon#about to read 4, iclass 27, count 0 2006.183.08:03:09.63#ibcon#read 4, iclass 27, count 0 2006.183.08:03:09.63#ibcon#about to read 5, iclass 27, count 0 2006.183.08:03:09.63#ibcon#read 5, iclass 27, count 0 2006.183.08:03:09.63#ibcon#about to read 6, iclass 27, count 0 2006.183.08:03:09.63#ibcon#read 6, iclass 27, count 0 2006.183.08:03:09.63#ibcon#end of sib2, iclass 27, count 0 2006.183.08:03:09.63#ibcon#*after write, iclass 27, count 0 2006.183.08:03:09.63#ibcon#*before return 0, iclass 27, count 0 2006.183.08:03:09.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:09.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:09.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:03:09.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:03:09.63$vc4f8/va=6,6 2006.183.08:03:09.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.08:03:09.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.08:03:09.63#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:09.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:09.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:09.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:09.68#ibcon#enter wrdev, iclass 29, count 2 2006.183.08:03:09.68#ibcon#first serial, iclass 29, count 2 2006.183.08:03:09.68#ibcon#enter sib2, iclass 29, count 2 2006.183.08:03:09.68#ibcon#flushed, iclass 29, count 2 2006.183.08:03:09.68#ibcon#about to write, iclass 29, count 2 2006.183.08:03:09.68#ibcon#wrote, iclass 29, count 2 2006.183.08:03:09.68#ibcon#about to read 3, iclass 29, count 2 2006.183.08:03:09.70#ibcon#read 3, iclass 29, count 2 2006.183.08:03:09.70#ibcon#about to read 4, iclass 29, count 2 2006.183.08:03:09.70#ibcon#read 4, iclass 29, count 2 2006.183.08:03:09.70#ibcon#about to read 5, iclass 29, count 2 2006.183.08:03:09.70#ibcon#read 5, iclass 29, count 2 2006.183.08:03:09.70#ibcon#about to read 6, iclass 29, count 2 2006.183.08:03:09.70#ibcon#read 6, iclass 29, count 2 2006.183.08:03:09.70#ibcon#end of sib2, iclass 29, count 2 2006.183.08:03:09.70#ibcon#*mode == 0, iclass 29, count 2 2006.183.08:03:09.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.08:03:09.70#ibcon#[25=AT06-06\r\n] 2006.183.08:03:09.70#ibcon#*before write, iclass 29, count 2 2006.183.08:03:09.70#ibcon#enter sib2, iclass 29, count 2 2006.183.08:03:09.70#ibcon#flushed, iclass 29, count 2 2006.183.08:03:09.70#ibcon#about to write, iclass 29, count 2 2006.183.08:03:09.70#ibcon#wrote, iclass 29, count 2 2006.183.08:03:09.70#ibcon#about to read 3, iclass 29, count 2 2006.183.08:03:09.73#ibcon#read 3, iclass 29, count 2 2006.183.08:03:09.73#ibcon#about to read 4, iclass 29, count 2 2006.183.08:03:09.73#ibcon#read 4, iclass 29, count 2 2006.183.08:03:09.73#ibcon#about to read 5, iclass 29, count 2 2006.183.08:03:09.73#ibcon#read 5, iclass 29, count 2 2006.183.08:03:09.73#ibcon#about to read 6, iclass 29, count 2 2006.183.08:03:09.73#ibcon#read 6, iclass 29, count 2 2006.183.08:03:09.73#ibcon#end of sib2, iclass 29, count 2 2006.183.08:03:09.73#ibcon#*after write, iclass 29, count 2 2006.183.08:03:09.73#ibcon#*before return 0, iclass 29, count 2 2006.183.08:03:09.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:09.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:09.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.08:03:09.73#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:09.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:09.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:09.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:09.85#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:03:09.85#ibcon#first serial, iclass 29, count 0 2006.183.08:03:09.85#ibcon#enter sib2, iclass 29, count 0 2006.183.08:03:09.85#ibcon#flushed, iclass 29, count 0 2006.183.08:03:09.85#ibcon#about to write, iclass 29, count 0 2006.183.08:03:09.85#ibcon#wrote, iclass 29, count 0 2006.183.08:03:09.85#ibcon#about to read 3, iclass 29, count 0 2006.183.08:03:09.87#ibcon#read 3, iclass 29, count 0 2006.183.08:03:09.87#ibcon#about to read 4, iclass 29, count 0 2006.183.08:03:09.87#ibcon#read 4, iclass 29, count 0 2006.183.08:03:09.87#ibcon#about to read 5, iclass 29, count 0 2006.183.08:03:09.87#ibcon#read 5, iclass 29, count 0 2006.183.08:03:09.87#ibcon#about to read 6, iclass 29, count 0 2006.183.08:03:09.87#ibcon#read 6, iclass 29, count 0 2006.183.08:03:09.87#ibcon#end of sib2, iclass 29, count 0 2006.183.08:03:09.87#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:03:09.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:03:09.87#ibcon#[25=USB\r\n] 2006.183.08:03:09.87#ibcon#*before write, iclass 29, count 0 2006.183.08:03:09.87#ibcon#enter sib2, iclass 29, count 0 2006.183.08:03:09.87#ibcon#flushed, iclass 29, count 0 2006.183.08:03:09.87#ibcon#about to write, iclass 29, count 0 2006.183.08:03:09.87#ibcon#wrote, iclass 29, count 0 2006.183.08:03:09.87#ibcon#about to read 3, iclass 29, count 0 2006.183.08:03:09.90#ibcon#read 3, iclass 29, count 0 2006.183.08:03:09.90#ibcon#about to read 4, iclass 29, count 0 2006.183.08:03:09.90#ibcon#read 4, iclass 29, count 0 2006.183.08:03:09.90#ibcon#about to read 5, iclass 29, count 0 2006.183.08:03:09.90#ibcon#read 5, iclass 29, count 0 2006.183.08:03:09.90#ibcon#about to read 6, iclass 29, count 0 2006.183.08:03:09.90#ibcon#read 6, iclass 29, count 0 2006.183.08:03:09.90#ibcon#end of sib2, iclass 29, count 0 2006.183.08:03:09.90#ibcon#*after write, iclass 29, count 0 2006.183.08:03:09.90#ibcon#*before return 0, iclass 29, count 0 2006.183.08:03:09.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:09.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:09.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:03:09.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:03:09.90$vc4f8/valo=7,832.99 2006.183.08:03:09.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.08:03:09.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.08:03:09.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:09.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:09.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:09.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:09.90#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:03:09.90#ibcon#first serial, iclass 31, count 0 2006.183.08:03:09.90#ibcon#enter sib2, iclass 31, count 0 2006.183.08:03:09.90#ibcon#flushed, iclass 31, count 0 2006.183.08:03:09.90#ibcon#about to write, iclass 31, count 0 2006.183.08:03:09.90#ibcon#wrote, iclass 31, count 0 2006.183.08:03:09.90#ibcon#about to read 3, iclass 31, count 0 2006.183.08:03:09.92#ibcon#read 3, iclass 31, count 0 2006.183.08:03:09.92#ibcon#about to read 4, iclass 31, count 0 2006.183.08:03:09.92#ibcon#read 4, iclass 31, count 0 2006.183.08:03:09.92#ibcon#about to read 5, iclass 31, count 0 2006.183.08:03:09.92#ibcon#read 5, iclass 31, count 0 2006.183.08:03:09.92#ibcon#about to read 6, iclass 31, count 0 2006.183.08:03:09.92#ibcon#read 6, iclass 31, count 0 2006.183.08:03:09.92#ibcon#end of sib2, iclass 31, count 0 2006.183.08:03:09.92#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:03:09.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:03:09.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:03:09.92#ibcon#*before write, iclass 31, count 0 2006.183.08:03:09.92#ibcon#enter sib2, iclass 31, count 0 2006.183.08:03:09.92#ibcon#flushed, iclass 31, count 0 2006.183.08:03:09.92#ibcon#about to write, iclass 31, count 0 2006.183.08:03:09.92#ibcon#wrote, iclass 31, count 0 2006.183.08:03:09.92#ibcon#about to read 3, iclass 31, count 0 2006.183.08:03:09.96#ibcon#read 3, iclass 31, count 0 2006.183.08:03:09.96#ibcon#about to read 4, iclass 31, count 0 2006.183.08:03:09.96#ibcon#read 4, iclass 31, count 0 2006.183.08:03:09.96#ibcon#about to read 5, iclass 31, count 0 2006.183.08:03:09.96#ibcon#read 5, iclass 31, count 0 2006.183.08:03:09.96#ibcon#about to read 6, iclass 31, count 0 2006.183.08:03:09.96#ibcon#read 6, iclass 31, count 0 2006.183.08:03:09.96#ibcon#end of sib2, iclass 31, count 0 2006.183.08:03:09.96#ibcon#*after write, iclass 31, count 0 2006.183.08:03:09.96#ibcon#*before return 0, iclass 31, count 0 2006.183.08:03:09.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:09.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:09.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:03:09.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:03:09.96$vc4f8/va=7,6 2006.183.08:03:09.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.08:03:09.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.08:03:09.96#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:09.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:03:10.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:03:10.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:03:10.02#ibcon#enter wrdev, iclass 33, count 2 2006.183.08:03:10.02#ibcon#first serial, iclass 33, count 2 2006.183.08:03:10.02#ibcon#enter sib2, iclass 33, count 2 2006.183.08:03:10.02#ibcon#flushed, iclass 33, count 2 2006.183.08:03:10.02#ibcon#about to write, iclass 33, count 2 2006.183.08:03:10.02#ibcon#wrote, iclass 33, count 2 2006.183.08:03:10.02#ibcon#about to read 3, iclass 33, count 2 2006.183.08:03:10.04#ibcon#read 3, iclass 33, count 2 2006.183.08:03:10.04#ibcon#about to read 4, iclass 33, count 2 2006.183.08:03:10.04#ibcon#read 4, iclass 33, count 2 2006.183.08:03:10.04#ibcon#about to read 5, iclass 33, count 2 2006.183.08:03:10.04#ibcon#read 5, iclass 33, count 2 2006.183.08:03:10.04#ibcon#about to read 6, iclass 33, count 2 2006.183.08:03:10.04#ibcon#read 6, iclass 33, count 2 2006.183.08:03:10.04#ibcon#end of sib2, iclass 33, count 2 2006.183.08:03:10.04#ibcon#*mode == 0, iclass 33, count 2 2006.183.08:03:10.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.08:03:10.04#ibcon#[25=AT07-06\r\n] 2006.183.08:03:10.04#ibcon#*before write, iclass 33, count 2 2006.183.08:03:10.04#ibcon#enter sib2, iclass 33, count 2 2006.183.08:03:10.04#ibcon#flushed, iclass 33, count 2 2006.183.08:03:10.04#ibcon#about to write, iclass 33, count 2 2006.183.08:03:10.04#ibcon#wrote, iclass 33, count 2 2006.183.08:03:10.04#ibcon#about to read 3, iclass 33, count 2 2006.183.08:03:10.07#ibcon#read 3, iclass 33, count 2 2006.183.08:03:10.07#ibcon#about to read 4, iclass 33, count 2 2006.183.08:03:10.07#ibcon#read 4, iclass 33, count 2 2006.183.08:03:10.07#ibcon#about to read 5, iclass 33, count 2 2006.183.08:03:10.07#ibcon#read 5, iclass 33, count 2 2006.183.08:03:10.07#ibcon#about to read 6, iclass 33, count 2 2006.183.08:03:10.07#ibcon#read 6, iclass 33, count 2 2006.183.08:03:10.07#ibcon#end of sib2, iclass 33, count 2 2006.183.08:03:10.07#ibcon#*after write, iclass 33, count 2 2006.183.08:03:10.07#ibcon#*before return 0, iclass 33, count 2 2006.183.08:03:10.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:03:10.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:03:10.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.08:03:10.07#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:10.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:03:10.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:03:10.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:03:10.19#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:03:10.19#ibcon#first serial, iclass 33, count 0 2006.183.08:03:10.19#ibcon#enter sib2, iclass 33, count 0 2006.183.08:03:10.19#ibcon#flushed, iclass 33, count 0 2006.183.08:03:10.19#ibcon#about to write, iclass 33, count 0 2006.183.08:03:10.19#ibcon#wrote, iclass 33, count 0 2006.183.08:03:10.19#ibcon#about to read 3, iclass 33, count 0 2006.183.08:03:10.21#ibcon#read 3, iclass 33, count 0 2006.183.08:03:10.21#ibcon#about to read 4, iclass 33, count 0 2006.183.08:03:10.21#ibcon#read 4, iclass 33, count 0 2006.183.08:03:10.21#ibcon#about to read 5, iclass 33, count 0 2006.183.08:03:10.21#ibcon#read 5, iclass 33, count 0 2006.183.08:03:10.21#ibcon#about to read 6, iclass 33, count 0 2006.183.08:03:10.21#ibcon#read 6, iclass 33, count 0 2006.183.08:03:10.21#ibcon#end of sib2, iclass 33, count 0 2006.183.08:03:10.21#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:03:10.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:03:10.21#ibcon#[25=USB\r\n] 2006.183.08:03:10.21#ibcon#*before write, iclass 33, count 0 2006.183.08:03:10.21#ibcon#enter sib2, iclass 33, count 0 2006.183.08:03:10.21#ibcon#flushed, iclass 33, count 0 2006.183.08:03:10.21#ibcon#about to write, iclass 33, count 0 2006.183.08:03:10.21#ibcon#wrote, iclass 33, count 0 2006.183.08:03:10.21#ibcon#about to read 3, iclass 33, count 0 2006.183.08:03:10.24#ibcon#read 3, iclass 33, count 0 2006.183.08:03:10.24#ibcon#about to read 4, iclass 33, count 0 2006.183.08:03:10.24#ibcon#read 4, iclass 33, count 0 2006.183.08:03:10.24#ibcon#about to read 5, iclass 33, count 0 2006.183.08:03:10.24#ibcon#read 5, iclass 33, count 0 2006.183.08:03:10.24#ibcon#about to read 6, iclass 33, count 0 2006.183.08:03:10.24#ibcon#read 6, iclass 33, count 0 2006.183.08:03:10.24#ibcon#end of sib2, iclass 33, count 0 2006.183.08:03:10.24#ibcon#*after write, iclass 33, count 0 2006.183.08:03:10.24#ibcon#*before return 0, iclass 33, count 0 2006.183.08:03:10.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:03:10.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:03:10.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:03:10.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:03:10.24$vc4f8/valo=8,852.99 2006.183.08:03:10.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.08:03:10.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.08:03:10.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:10.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:03:10.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:03:10.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:03:10.24#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:03:10.24#ibcon#first serial, iclass 35, count 0 2006.183.08:03:10.24#ibcon#enter sib2, iclass 35, count 0 2006.183.08:03:10.24#ibcon#flushed, iclass 35, count 0 2006.183.08:03:10.24#ibcon#about to write, iclass 35, count 0 2006.183.08:03:10.24#ibcon#wrote, iclass 35, count 0 2006.183.08:03:10.24#ibcon#about to read 3, iclass 35, count 0 2006.183.08:03:10.26#ibcon#read 3, iclass 35, count 0 2006.183.08:03:10.26#ibcon#about to read 4, iclass 35, count 0 2006.183.08:03:10.26#ibcon#read 4, iclass 35, count 0 2006.183.08:03:10.26#ibcon#about to read 5, iclass 35, count 0 2006.183.08:03:10.26#ibcon#read 5, iclass 35, count 0 2006.183.08:03:10.26#ibcon#about to read 6, iclass 35, count 0 2006.183.08:03:10.26#ibcon#read 6, iclass 35, count 0 2006.183.08:03:10.26#ibcon#end of sib2, iclass 35, count 0 2006.183.08:03:10.26#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:03:10.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:03:10.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:03:10.26#ibcon#*before write, iclass 35, count 0 2006.183.08:03:10.26#ibcon#enter sib2, iclass 35, count 0 2006.183.08:03:10.26#ibcon#flushed, iclass 35, count 0 2006.183.08:03:10.26#ibcon#about to write, iclass 35, count 0 2006.183.08:03:10.26#ibcon#wrote, iclass 35, count 0 2006.183.08:03:10.26#ibcon#about to read 3, iclass 35, count 0 2006.183.08:03:10.30#ibcon#read 3, iclass 35, count 0 2006.183.08:03:10.30#ibcon#about to read 4, iclass 35, count 0 2006.183.08:03:10.30#ibcon#read 4, iclass 35, count 0 2006.183.08:03:10.30#ibcon#about to read 5, iclass 35, count 0 2006.183.08:03:10.30#ibcon#read 5, iclass 35, count 0 2006.183.08:03:10.30#ibcon#about to read 6, iclass 35, count 0 2006.183.08:03:10.30#ibcon#read 6, iclass 35, count 0 2006.183.08:03:10.30#ibcon#end of sib2, iclass 35, count 0 2006.183.08:03:10.30#ibcon#*after write, iclass 35, count 0 2006.183.08:03:10.30#ibcon#*before return 0, iclass 35, count 0 2006.183.08:03:10.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:03:10.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:03:10.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:03:10.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:03:10.30$vc4f8/va=8,7 2006.183.08:03:10.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.08:03:10.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.08:03:10.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:10.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:03:10.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:03:10.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:03:10.36#ibcon#enter wrdev, iclass 37, count 2 2006.183.08:03:10.36#ibcon#first serial, iclass 37, count 2 2006.183.08:03:10.36#ibcon#enter sib2, iclass 37, count 2 2006.183.08:03:10.36#ibcon#flushed, iclass 37, count 2 2006.183.08:03:10.36#ibcon#about to write, iclass 37, count 2 2006.183.08:03:10.36#ibcon#wrote, iclass 37, count 2 2006.183.08:03:10.36#ibcon#about to read 3, iclass 37, count 2 2006.183.08:03:10.38#ibcon#read 3, iclass 37, count 2 2006.183.08:03:10.38#ibcon#about to read 4, iclass 37, count 2 2006.183.08:03:10.38#ibcon#read 4, iclass 37, count 2 2006.183.08:03:10.38#ibcon#about to read 5, iclass 37, count 2 2006.183.08:03:10.38#ibcon#read 5, iclass 37, count 2 2006.183.08:03:10.38#ibcon#about to read 6, iclass 37, count 2 2006.183.08:03:10.38#ibcon#read 6, iclass 37, count 2 2006.183.08:03:10.38#ibcon#end of sib2, iclass 37, count 2 2006.183.08:03:10.38#ibcon#*mode == 0, iclass 37, count 2 2006.183.08:03:10.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.08:03:10.38#ibcon#[25=AT08-07\r\n] 2006.183.08:03:10.38#ibcon#*before write, iclass 37, count 2 2006.183.08:03:10.38#ibcon#enter sib2, iclass 37, count 2 2006.183.08:03:10.38#ibcon#flushed, iclass 37, count 2 2006.183.08:03:10.38#ibcon#about to write, iclass 37, count 2 2006.183.08:03:10.38#ibcon#wrote, iclass 37, count 2 2006.183.08:03:10.38#ibcon#about to read 3, iclass 37, count 2 2006.183.08:03:10.41#ibcon#read 3, iclass 37, count 2 2006.183.08:03:10.41#ibcon#about to read 4, iclass 37, count 2 2006.183.08:03:10.41#ibcon#read 4, iclass 37, count 2 2006.183.08:03:10.41#ibcon#about to read 5, iclass 37, count 2 2006.183.08:03:10.41#ibcon#read 5, iclass 37, count 2 2006.183.08:03:10.41#ibcon#about to read 6, iclass 37, count 2 2006.183.08:03:10.41#ibcon#read 6, iclass 37, count 2 2006.183.08:03:10.41#ibcon#end of sib2, iclass 37, count 2 2006.183.08:03:10.41#ibcon#*after write, iclass 37, count 2 2006.183.08:03:10.41#ibcon#*before return 0, iclass 37, count 2 2006.183.08:03:10.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:03:10.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:03:10.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.08:03:10.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:10.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:03:10.53#abcon#<5=/09 1.4 7.0 28.22 86 996.4\r\n> 2006.183.08:03:10.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:03:10.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:03:10.53#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:03:10.53#ibcon#first serial, iclass 37, count 0 2006.183.08:03:10.53#ibcon#enter sib2, iclass 37, count 0 2006.183.08:03:10.53#ibcon#flushed, iclass 37, count 0 2006.183.08:03:10.53#ibcon#about to write, iclass 37, count 0 2006.183.08:03:10.53#ibcon#wrote, iclass 37, count 0 2006.183.08:03:10.53#ibcon#about to read 3, iclass 37, count 0 2006.183.08:03:10.55#ibcon#read 3, iclass 37, count 0 2006.183.08:03:10.55#ibcon#about to read 4, iclass 37, count 0 2006.183.08:03:10.55#ibcon#read 4, iclass 37, count 0 2006.183.08:03:10.55#ibcon#about to read 5, iclass 37, count 0 2006.183.08:03:10.55#ibcon#read 5, iclass 37, count 0 2006.183.08:03:10.55#ibcon#about to read 6, iclass 37, count 0 2006.183.08:03:10.55#ibcon#read 6, iclass 37, count 0 2006.183.08:03:10.55#ibcon#end of sib2, iclass 37, count 0 2006.183.08:03:10.55#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:03:10.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:03:10.55#ibcon#[25=USB\r\n] 2006.183.08:03:10.55#ibcon#*before write, iclass 37, count 0 2006.183.08:03:10.55#ibcon#enter sib2, iclass 37, count 0 2006.183.08:03:10.55#ibcon#flushed, iclass 37, count 0 2006.183.08:03:10.55#ibcon#about to write, iclass 37, count 0 2006.183.08:03:10.55#ibcon#wrote, iclass 37, count 0 2006.183.08:03:10.55#ibcon#about to read 3, iclass 37, count 0 2006.183.08:03:10.55#abcon#{5=INTERFACE CLEAR} 2006.183.08:03:10.58#ibcon#read 3, iclass 37, count 0 2006.183.08:03:10.58#ibcon#about to read 4, iclass 37, count 0 2006.183.08:03:10.58#ibcon#read 4, iclass 37, count 0 2006.183.08:03:10.58#ibcon#about to read 5, iclass 37, count 0 2006.183.08:03:10.58#ibcon#read 5, iclass 37, count 0 2006.183.08:03:10.58#ibcon#about to read 6, iclass 37, count 0 2006.183.08:03:10.58#ibcon#read 6, iclass 37, count 0 2006.183.08:03:10.58#ibcon#end of sib2, iclass 37, count 0 2006.183.08:03:10.58#ibcon#*after write, iclass 37, count 0 2006.183.08:03:10.58#ibcon#*before return 0, iclass 37, count 0 2006.183.08:03:10.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:03:10.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:03:10.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:03:10.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:03:10.58$vc4f8/vblo=1,632.99 2006.183.08:03:10.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.08:03:10.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.08:03:10.58#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:10.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:03:10.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:03:10.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:03:10.58#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:03:10.58#ibcon#first serial, iclass 4, count 0 2006.183.08:03:10.58#ibcon#enter sib2, iclass 4, count 0 2006.183.08:03:10.58#ibcon#flushed, iclass 4, count 0 2006.183.08:03:10.58#ibcon#about to write, iclass 4, count 0 2006.183.08:03:10.58#ibcon#wrote, iclass 4, count 0 2006.183.08:03:10.58#ibcon#about to read 3, iclass 4, count 0 2006.183.08:03:10.60#ibcon#read 3, iclass 4, count 0 2006.183.08:03:10.60#ibcon#about to read 4, iclass 4, count 0 2006.183.08:03:10.60#ibcon#read 4, iclass 4, count 0 2006.183.08:03:10.60#ibcon#about to read 5, iclass 4, count 0 2006.183.08:03:10.60#ibcon#read 5, iclass 4, count 0 2006.183.08:03:10.60#ibcon#about to read 6, iclass 4, count 0 2006.183.08:03:10.60#ibcon#read 6, iclass 4, count 0 2006.183.08:03:10.60#ibcon#end of sib2, iclass 4, count 0 2006.183.08:03:10.60#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:03:10.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:03:10.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:03:10.60#ibcon#*before write, iclass 4, count 0 2006.183.08:03:10.60#ibcon#enter sib2, iclass 4, count 0 2006.183.08:03:10.60#ibcon#flushed, iclass 4, count 0 2006.183.08:03:10.60#ibcon#about to write, iclass 4, count 0 2006.183.08:03:10.60#ibcon#wrote, iclass 4, count 0 2006.183.08:03:10.60#ibcon#about to read 3, iclass 4, count 0 2006.183.08:03:10.61#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:03:10.64#ibcon#read 3, iclass 4, count 0 2006.183.08:03:10.64#ibcon#about to read 4, iclass 4, count 0 2006.183.08:03:10.64#ibcon#read 4, iclass 4, count 0 2006.183.08:03:10.64#ibcon#about to read 5, iclass 4, count 0 2006.183.08:03:10.64#ibcon#read 5, iclass 4, count 0 2006.183.08:03:10.64#ibcon#about to read 6, iclass 4, count 0 2006.183.08:03:10.64#ibcon#read 6, iclass 4, count 0 2006.183.08:03:10.64#ibcon#end of sib2, iclass 4, count 0 2006.183.08:03:10.64#ibcon#*after write, iclass 4, count 0 2006.183.08:03:10.64#ibcon#*before return 0, iclass 4, count 0 2006.183.08:03:10.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:03:10.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:03:10.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:03:10.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:03:10.64$vc4f8/vb=1,4 2006.183.08:03:10.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.08:03:10.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.08:03:10.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:10.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:10.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:10.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:10.64#ibcon#enter wrdev, iclass 7, count 2 2006.183.08:03:10.64#ibcon#first serial, iclass 7, count 2 2006.183.08:03:10.64#ibcon#enter sib2, iclass 7, count 2 2006.183.08:03:10.64#ibcon#flushed, iclass 7, count 2 2006.183.08:03:10.64#ibcon#about to write, iclass 7, count 2 2006.183.08:03:10.64#ibcon#wrote, iclass 7, count 2 2006.183.08:03:10.64#ibcon#about to read 3, iclass 7, count 2 2006.183.08:03:10.66#ibcon#read 3, iclass 7, count 2 2006.183.08:03:10.66#ibcon#about to read 4, iclass 7, count 2 2006.183.08:03:10.66#ibcon#read 4, iclass 7, count 2 2006.183.08:03:10.66#ibcon#about to read 5, iclass 7, count 2 2006.183.08:03:10.66#ibcon#read 5, iclass 7, count 2 2006.183.08:03:10.66#ibcon#about to read 6, iclass 7, count 2 2006.183.08:03:10.66#ibcon#read 6, iclass 7, count 2 2006.183.08:03:10.66#ibcon#end of sib2, iclass 7, count 2 2006.183.08:03:10.66#ibcon#*mode == 0, iclass 7, count 2 2006.183.08:03:10.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.08:03:10.66#ibcon#[27=AT01-04\r\n] 2006.183.08:03:10.66#ibcon#*before write, iclass 7, count 2 2006.183.08:03:10.66#ibcon#enter sib2, iclass 7, count 2 2006.183.08:03:10.66#ibcon#flushed, iclass 7, count 2 2006.183.08:03:10.66#ibcon#about to write, iclass 7, count 2 2006.183.08:03:10.66#ibcon#wrote, iclass 7, count 2 2006.183.08:03:10.66#ibcon#about to read 3, iclass 7, count 2 2006.183.08:03:10.69#ibcon#read 3, iclass 7, count 2 2006.183.08:03:10.69#ibcon#about to read 4, iclass 7, count 2 2006.183.08:03:10.69#ibcon#read 4, iclass 7, count 2 2006.183.08:03:10.69#ibcon#about to read 5, iclass 7, count 2 2006.183.08:03:10.69#ibcon#read 5, iclass 7, count 2 2006.183.08:03:10.69#ibcon#about to read 6, iclass 7, count 2 2006.183.08:03:10.69#ibcon#read 6, iclass 7, count 2 2006.183.08:03:10.69#ibcon#end of sib2, iclass 7, count 2 2006.183.08:03:10.69#ibcon#*after write, iclass 7, count 2 2006.183.08:03:10.69#ibcon#*before return 0, iclass 7, count 2 2006.183.08:03:10.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:10.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:03:10.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.08:03:10.69#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:10.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:10.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:10.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:10.81#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:03:10.81#ibcon#first serial, iclass 7, count 0 2006.183.08:03:10.81#ibcon#enter sib2, iclass 7, count 0 2006.183.08:03:10.81#ibcon#flushed, iclass 7, count 0 2006.183.08:03:10.81#ibcon#about to write, iclass 7, count 0 2006.183.08:03:10.81#ibcon#wrote, iclass 7, count 0 2006.183.08:03:10.81#ibcon#about to read 3, iclass 7, count 0 2006.183.08:03:10.83#ibcon#read 3, iclass 7, count 0 2006.183.08:03:10.83#ibcon#about to read 4, iclass 7, count 0 2006.183.08:03:10.83#ibcon#read 4, iclass 7, count 0 2006.183.08:03:10.83#ibcon#about to read 5, iclass 7, count 0 2006.183.08:03:10.83#ibcon#read 5, iclass 7, count 0 2006.183.08:03:10.83#ibcon#about to read 6, iclass 7, count 0 2006.183.08:03:10.83#ibcon#read 6, iclass 7, count 0 2006.183.08:03:10.83#ibcon#end of sib2, iclass 7, count 0 2006.183.08:03:10.83#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:03:10.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:03:10.83#ibcon#[27=USB\r\n] 2006.183.08:03:10.83#ibcon#*before write, iclass 7, count 0 2006.183.08:03:10.83#ibcon#enter sib2, iclass 7, count 0 2006.183.08:03:10.83#ibcon#flushed, iclass 7, count 0 2006.183.08:03:10.83#ibcon#about to write, iclass 7, count 0 2006.183.08:03:10.83#ibcon#wrote, iclass 7, count 0 2006.183.08:03:10.83#ibcon#about to read 3, iclass 7, count 0 2006.183.08:03:10.86#ibcon#read 3, iclass 7, count 0 2006.183.08:03:10.86#ibcon#about to read 4, iclass 7, count 0 2006.183.08:03:10.86#ibcon#read 4, iclass 7, count 0 2006.183.08:03:10.86#ibcon#about to read 5, iclass 7, count 0 2006.183.08:03:10.86#ibcon#read 5, iclass 7, count 0 2006.183.08:03:10.86#ibcon#about to read 6, iclass 7, count 0 2006.183.08:03:10.86#ibcon#read 6, iclass 7, count 0 2006.183.08:03:10.86#ibcon#end of sib2, iclass 7, count 0 2006.183.08:03:10.86#ibcon#*after write, iclass 7, count 0 2006.183.08:03:10.86#ibcon#*before return 0, iclass 7, count 0 2006.183.08:03:10.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:10.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:03:10.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:03:10.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:03:10.86$vc4f8/vblo=2,640.99 2006.183.08:03:10.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:03:10.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:03:10.86#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:10.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:10.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:10.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:10.86#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:03:10.86#ibcon#first serial, iclass 11, count 0 2006.183.08:03:10.86#ibcon#enter sib2, iclass 11, count 0 2006.183.08:03:10.86#ibcon#flushed, iclass 11, count 0 2006.183.08:03:10.86#ibcon#about to write, iclass 11, count 0 2006.183.08:03:10.86#ibcon#wrote, iclass 11, count 0 2006.183.08:03:10.86#ibcon#about to read 3, iclass 11, count 0 2006.183.08:03:10.88#ibcon#read 3, iclass 11, count 0 2006.183.08:03:10.88#ibcon#about to read 4, iclass 11, count 0 2006.183.08:03:10.88#ibcon#read 4, iclass 11, count 0 2006.183.08:03:10.88#ibcon#about to read 5, iclass 11, count 0 2006.183.08:03:10.88#ibcon#read 5, iclass 11, count 0 2006.183.08:03:10.88#ibcon#about to read 6, iclass 11, count 0 2006.183.08:03:10.88#ibcon#read 6, iclass 11, count 0 2006.183.08:03:10.88#ibcon#end of sib2, iclass 11, count 0 2006.183.08:03:10.88#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:03:10.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:03:10.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:03:10.88#ibcon#*before write, iclass 11, count 0 2006.183.08:03:10.88#ibcon#enter sib2, iclass 11, count 0 2006.183.08:03:10.88#ibcon#flushed, iclass 11, count 0 2006.183.08:03:10.88#ibcon#about to write, iclass 11, count 0 2006.183.08:03:10.88#ibcon#wrote, iclass 11, count 0 2006.183.08:03:10.88#ibcon#about to read 3, iclass 11, count 0 2006.183.08:03:10.92#ibcon#read 3, iclass 11, count 0 2006.183.08:03:10.92#ibcon#about to read 4, iclass 11, count 0 2006.183.08:03:10.92#ibcon#read 4, iclass 11, count 0 2006.183.08:03:10.92#ibcon#about to read 5, iclass 11, count 0 2006.183.08:03:10.92#ibcon#read 5, iclass 11, count 0 2006.183.08:03:10.92#ibcon#about to read 6, iclass 11, count 0 2006.183.08:03:10.92#ibcon#read 6, iclass 11, count 0 2006.183.08:03:10.92#ibcon#end of sib2, iclass 11, count 0 2006.183.08:03:10.92#ibcon#*after write, iclass 11, count 0 2006.183.08:03:10.92#ibcon#*before return 0, iclass 11, count 0 2006.183.08:03:10.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:10.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:03:10.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:03:10.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:03:10.92$vc4f8/vb=2,4 2006.183.08:03:10.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.08:03:10.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.08:03:10.92#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:10.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:10.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:10.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:10.98#ibcon#enter wrdev, iclass 13, count 2 2006.183.08:03:10.98#ibcon#first serial, iclass 13, count 2 2006.183.08:03:10.98#ibcon#enter sib2, iclass 13, count 2 2006.183.08:03:10.98#ibcon#flushed, iclass 13, count 2 2006.183.08:03:10.98#ibcon#about to write, iclass 13, count 2 2006.183.08:03:10.98#ibcon#wrote, iclass 13, count 2 2006.183.08:03:10.98#ibcon#about to read 3, iclass 13, count 2 2006.183.08:03:11.00#ibcon#read 3, iclass 13, count 2 2006.183.08:03:11.00#ibcon#about to read 4, iclass 13, count 2 2006.183.08:03:11.00#ibcon#read 4, iclass 13, count 2 2006.183.08:03:11.00#ibcon#about to read 5, iclass 13, count 2 2006.183.08:03:11.00#ibcon#read 5, iclass 13, count 2 2006.183.08:03:11.00#ibcon#about to read 6, iclass 13, count 2 2006.183.08:03:11.00#ibcon#read 6, iclass 13, count 2 2006.183.08:03:11.00#ibcon#end of sib2, iclass 13, count 2 2006.183.08:03:11.00#ibcon#*mode == 0, iclass 13, count 2 2006.183.08:03:11.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.08:03:11.00#ibcon#[27=AT02-04\r\n] 2006.183.08:03:11.00#ibcon#*before write, iclass 13, count 2 2006.183.08:03:11.00#ibcon#enter sib2, iclass 13, count 2 2006.183.08:03:11.00#ibcon#flushed, iclass 13, count 2 2006.183.08:03:11.00#ibcon#about to write, iclass 13, count 2 2006.183.08:03:11.00#ibcon#wrote, iclass 13, count 2 2006.183.08:03:11.00#ibcon#about to read 3, iclass 13, count 2 2006.183.08:03:11.03#ibcon#read 3, iclass 13, count 2 2006.183.08:03:11.03#ibcon#about to read 4, iclass 13, count 2 2006.183.08:03:11.03#ibcon#read 4, iclass 13, count 2 2006.183.08:03:11.03#ibcon#about to read 5, iclass 13, count 2 2006.183.08:03:11.03#ibcon#read 5, iclass 13, count 2 2006.183.08:03:11.03#ibcon#about to read 6, iclass 13, count 2 2006.183.08:03:11.03#ibcon#read 6, iclass 13, count 2 2006.183.08:03:11.03#ibcon#end of sib2, iclass 13, count 2 2006.183.08:03:11.03#ibcon#*after write, iclass 13, count 2 2006.183.08:03:11.03#ibcon#*before return 0, iclass 13, count 2 2006.183.08:03:11.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:11.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:03:11.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.08:03:11.03#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:11.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:11.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:11.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:11.15#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:03:11.15#ibcon#first serial, iclass 13, count 0 2006.183.08:03:11.15#ibcon#enter sib2, iclass 13, count 0 2006.183.08:03:11.15#ibcon#flushed, iclass 13, count 0 2006.183.08:03:11.15#ibcon#about to write, iclass 13, count 0 2006.183.08:03:11.15#ibcon#wrote, iclass 13, count 0 2006.183.08:03:11.15#ibcon#about to read 3, iclass 13, count 0 2006.183.08:03:11.17#ibcon#read 3, iclass 13, count 0 2006.183.08:03:11.17#ibcon#about to read 4, iclass 13, count 0 2006.183.08:03:11.17#ibcon#read 4, iclass 13, count 0 2006.183.08:03:11.17#ibcon#about to read 5, iclass 13, count 0 2006.183.08:03:11.17#ibcon#read 5, iclass 13, count 0 2006.183.08:03:11.17#ibcon#about to read 6, iclass 13, count 0 2006.183.08:03:11.17#ibcon#read 6, iclass 13, count 0 2006.183.08:03:11.17#ibcon#end of sib2, iclass 13, count 0 2006.183.08:03:11.17#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:03:11.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:03:11.17#ibcon#[27=USB\r\n] 2006.183.08:03:11.17#ibcon#*before write, iclass 13, count 0 2006.183.08:03:11.17#ibcon#enter sib2, iclass 13, count 0 2006.183.08:03:11.17#ibcon#flushed, iclass 13, count 0 2006.183.08:03:11.17#ibcon#about to write, iclass 13, count 0 2006.183.08:03:11.17#ibcon#wrote, iclass 13, count 0 2006.183.08:03:11.17#ibcon#about to read 3, iclass 13, count 0 2006.183.08:03:11.20#ibcon#read 3, iclass 13, count 0 2006.183.08:03:11.20#ibcon#about to read 4, iclass 13, count 0 2006.183.08:03:11.20#ibcon#read 4, iclass 13, count 0 2006.183.08:03:11.20#ibcon#about to read 5, iclass 13, count 0 2006.183.08:03:11.20#ibcon#read 5, iclass 13, count 0 2006.183.08:03:11.20#ibcon#about to read 6, iclass 13, count 0 2006.183.08:03:11.20#ibcon#read 6, iclass 13, count 0 2006.183.08:03:11.20#ibcon#end of sib2, iclass 13, count 0 2006.183.08:03:11.20#ibcon#*after write, iclass 13, count 0 2006.183.08:03:11.20#ibcon#*before return 0, iclass 13, count 0 2006.183.08:03:11.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:11.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:03:11.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:03:11.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:03:11.20$vc4f8/vblo=3,656.99 2006.183.08:03:11.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.08:03:11.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.08:03:11.20#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:11.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:11.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:11.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:11.20#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:03:11.20#ibcon#first serial, iclass 15, count 0 2006.183.08:03:11.20#ibcon#enter sib2, iclass 15, count 0 2006.183.08:03:11.20#ibcon#flushed, iclass 15, count 0 2006.183.08:03:11.20#ibcon#about to write, iclass 15, count 0 2006.183.08:03:11.20#ibcon#wrote, iclass 15, count 0 2006.183.08:03:11.20#ibcon#about to read 3, iclass 15, count 0 2006.183.08:03:11.22#ibcon#read 3, iclass 15, count 0 2006.183.08:03:11.22#ibcon#about to read 4, iclass 15, count 0 2006.183.08:03:11.22#ibcon#read 4, iclass 15, count 0 2006.183.08:03:11.22#ibcon#about to read 5, iclass 15, count 0 2006.183.08:03:11.22#ibcon#read 5, iclass 15, count 0 2006.183.08:03:11.22#ibcon#about to read 6, iclass 15, count 0 2006.183.08:03:11.22#ibcon#read 6, iclass 15, count 0 2006.183.08:03:11.22#ibcon#end of sib2, iclass 15, count 0 2006.183.08:03:11.22#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:03:11.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:03:11.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:03:11.22#ibcon#*before write, iclass 15, count 0 2006.183.08:03:11.22#ibcon#enter sib2, iclass 15, count 0 2006.183.08:03:11.22#ibcon#flushed, iclass 15, count 0 2006.183.08:03:11.22#ibcon#about to write, iclass 15, count 0 2006.183.08:03:11.22#ibcon#wrote, iclass 15, count 0 2006.183.08:03:11.22#ibcon#about to read 3, iclass 15, count 0 2006.183.08:03:11.26#ibcon#read 3, iclass 15, count 0 2006.183.08:03:11.26#ibcon#about to read 4, iclass 15, count 0 2006.183.08:03:11.26#ibcon#read 4, iclass 15, count 0 2006.183.08:03:11.26#ibcon#about to read 5, iclass 15, count 0 2006.183.08:03:11.26#ibcon#read 5, iclass 15, count 0 2006.183.08:03:11.26#ibcon#about to read 6, iclass 15, count 0 2006.183.08:03:11.26#ibcon#read 6, iclass 15, count 0 2006.183.08:03:11.26#ibcon#end of sib2, iclass 15, count 0 2006.183.08:03:11.26#ibcon#*after write, iclass 15, count 0 2006.183.08:03:11.26#ibcon#*before return 0, iclass 15, count 0 2006.183.08:03:11.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:11.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:03:11.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:03:11.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:03:11.26$vc4f8/vb=3,4 2006.183.08:03:11.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.08:03:11.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.08:03:11.26#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:11.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:11.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:11.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:11.32#ibcon#enter wrdev, iclass 17, count 2 2006.183.08:03:11.32#ibcon#first serial, iclass 17, count 2 2006.183.08:03:11.32#ibcon#enter sib2, iclass 17, count 2 2006.183.08:03:11.32#ibcon#flushed, iclass 17, count 2 2006.183.08:03:11.32#ibcon#about to write, iclass 17, count 2 2006.183.08:03:11.32#ibcon#wrote, iclass 17, count 2 2006.183.08:03:11.32#ibcon#about to read 3, iclass 17, count 2 2006.183.08:03:11.34#ibcon#read 3, iclass 17, count 2 2006.183.08:03:11.34#ibcon#about to read 4, iclass 17, count 2 2006.183.08:03:11.34#ibcon#read 4, iclass 17, count 2 2006.183.08:03:11.34#ibcon#about to read 5, iclass 17, count 2 2006.183.08:03:11.34#ibcon#read 5, iclass 17, count 2 2006.183.08:03:11.34#ibcon#about to read 6, iclass 17, count 2 2006.183.08:03:11.34#ibcon#read 6, iclass 17, count 2 2006.183.08:03:11.34#ibcon#end of sib2, iclass 17, count 2 2006.183.08:03:11.34#ibcon#*mode == 0, iclass 17, count 2 2006.183.08:03:11.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.08:03:11.34#ibcon#[27=AT03-04\r\n] 2006.183.08:03:11.34#ibcon#*before write, iclass 17, count 2 2006.183.08:03:11.34#ibcon#enter sib2, iclass 17, count 2 2006.183.08:03:11.34#ibcon#flushed, iclass 17, count 2 2006.183.08:03:11.34#ibcon#about to write, iclass 17, count 2 2006.183.08:03:11.34#ibcon#wrote, iclass 17, count 2 2006.183.08:03:11.34#ibcon#about to read 3, iclass 17, count 2 2006.183.08:03:11.37#ibcon#read 3, iclass 17, count 2 2006.183.08:03:11.37#ibcon#about to read 4, iclass 17, count 2 2006.183.08:03:11.37#ibcon#read 4, iclass 17, count 2 2006.183.08:03:11.37#ibcon#about to read 5, iclass 17, count 2 2006.183.08:03:11.37#ibcon#read 5, iclass 17, count 2 2006.183.08:03:11.37#ibcon#about to read 6, iclass 17, count 2 2006.183.08:03:11.37#ibcon#read 6, iclass 17, count 2 2006.183.08:03:11.37#ibcon#end of sib2, iclass 17, count 2 2006.183.08:03:11.37#ibcon#*after write, iclass 17, count 2 2006.183.08:03:11.37#ibcon#*before return 0, iclass 17, count 2 2006.183.08:03:11.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:11.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:03:11.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.08:03:11.37#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:11.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:11.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:11.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:11.49#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:03:11.49#ibcon#first serial, iclass 17, count 0 2006.183.08:03:11.49#ibcon#enter sib2, iclass 17, count 0 2006.183.08:03:11.49#ibcon#flushed, iclass 17, count 0 2006.183.08:03:11.49#ibcon#about to write, iclass 17, count 0 2006.183.08:03:11.49#ibcon#wrote, iclass 17, count 0 2006.183.08:03:11.49#ibcon#about to read 3, iclass 17, count 0 2006.183.08:03:11.51#ibcon#read 3, iclass 17, count 0 2006.183.08:03:11.51#ibcon#about to read 4, iclass 17, count 0 2006.183.08:03:11.51#ibcon#read 4, iclass 17, count 0 2006.183.08:03:11.51#ibcon#about to read 5, iclass 17, count 0 2006.183.08:03:11.51#ibcon#read 5, iclass 17, count 0 2006.183.08:03:11.51#ibcon#about to read 6, iclass 17, count 0 2006.183.08:03:11.51#ibcon#read 6, iclass 17, count 0 2006.183.08:03:11.51#ibcon#end of sib2, iclass 17, count 0 2006.183.08:03:11.51#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:03:11.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:03:11.51#ibcon#[27=USB\r\n] 2006.183.08:03:11.51#ibcon#*before write, iclass 17, count 0 2006.183.08:03:11.51#ibcon#enter sib2, iclass 17, count 0 2006.183.08:03:11.51#ibcon#flushed, iclass 17, count 0 2006.183.08:03:11.51#ibcon#about to write, iclass 17, count 0 2006.183.08:03:11.51#ibcon#wrote, iclass 17, count 0 2006.183.08:03:11.51#ibcon#about to read 3, iclass 17, count 0 2006.183.08:03:11.54#ibcon#read 3, iclass 17, count 0 2006.183.08:03:11.54#ibcon#about to read 4, iclass 17, count 0 2006.183.08:03:11.54#ibcon#read 4, iclass 17, count 0 2006.183.08:03:11.54#ibcon#about to read 5, iclass 17, count 0 2006.183.08:03:11.54#ibcon#read 5, iclass 17, count 0 2006.183.08:03:11.54#ibcon#about to read 6, iclass 17, count 0 2006.183.08:03:11.54#ibcon#read 6, iclass 17, count 0 2006.183.08:03:11.54#ibcon#end of sib2, iclass 17, count 0 2006.183.08:03:11.54#ibcon#*after write, iclass 17, count 0 2006.183.08:03:11.54#ibcon#*before return 0, iclass 17, count 0 2006.183.08:03:11.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:11.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:03:11.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:03:11.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:03:11.54$vc4f8/vblo=4,712.99 2006.183.08:03:11.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.08:03:11.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.08:03:11.54#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:11.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:11.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:11.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:11.54#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:03:11.54#ibcon#first serial, iclass 19, count 0 2006.183.08:03:11.54#ibcon#enter sib2, iclass 19, count 0 2006.183.08:03:11.54#ibcon#flushed, iclass 19, count 0 2006.183.08:03:11.54#ibcon#about to write, iclass 19, count 0 2006.183.08:03:11.54#ibcon#wrote, iclass 19, count 0 2006.183.08:03:11.54#ibcon#about to read 3, iclass 19, count 0 2006.183.08:03:11.56#ibcon#read 3, iclass 19, count 0 2006.183.08:03:11.56#ibcon#about to read 4, iclass 19, count 0 2006.183.08:03:11.56#ibcon#read 4, iclass 19, count 0 2006.183.08:03:11.56#ibcon#about to read 5, iclass 19, count 0 2006.183.08:03:11.56#ibcon#read 5, iclass 19, count 0 2006.183.08:03:11.56#ibcon#about to read 6, iclass 19, count 0 2006.183.08:03:11.56#ibcon#read 6, iclass 19, count 0 2006.183.08:03:11.56#ibcon#end of sib2, iclass 19, count 0 2006.183.08:03:11.56#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:03:11.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:03:11.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:03:11.56#ibcon#*before write, iclass 19, count 0 2006.183.08:03:11.56#ibcon#enter sib2, iclass 19, count 0 2006.183.08:03:11.56#ibcon#flushed, iclass 19, count 0 2006.183.08:03:11.56#ibcon#about to write, iclass 19, count 0 2006.183.08:03:11.56#ibcon#wrote, iclass 19, count 0 2006.183.08:03:11.56#ibcon#about to read 3, iclass 19, count 0 2006.183.08:03:11.60#ibcon#read 3, iclass 19, count 0 2006.183.08:03:11.60#ibcon#about to read 4, iclass 19, count 0 2006.183.08:03:11.60#ibcon#read 4, iclass 19, count 0 2006.183.08:03:11.60#ibcon#about to read 5, iclass 19, count 0 2006.183.08:03:11.60#ibcon#read 5, iclass 19, count 0 2006.183.08:03:11.60#ibcon#about to read 6, iclass 19, count 0 2006.183.08:03:11.60#ibcon#read 6, iclass 19, count 0 2006.183.08:03:11.60#ibcon#end of sib2, iclass 19, count 0 2006.183.08:03:11.60#ibcon#*after write, iclass 19, count 0 2006.183.08:03:11.60#ibcon#*before return 0, iclass 19, count 0 2006.183.08:03:11.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:11.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:03:11.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:03:11.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:03:11.60$vc4f8/vb=4,4 2006.183.08:03:11.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.08:03:11.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.08:03:11.60#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:11.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:11.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:11.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:11.66#ibcon#enter wrdev, iclass 21, count 2 2006.183.08:03:11.66#ibcon#first serial, iclass 21, count 2 2006.183.08:03:11.66#ibcon#enter sib2, iclass 21, count 2 2006.183.08:03:11.66#ibcon#flushed, iclass 21, count 2 2006.183.08:03:11.66#ibcon#about to write, iclass 21, count 2 2006.183.08:03:11.66#ibcon#wrote, iclass 21, count 2 2006.183.08:03:11.66#ibcon#about to read 3, iclass 21, count 2 2006.183.08:03:11.68#ibcon#read 3, iclass 21, count 2 2006.183.08:03:11.68#ibcon#about to read 4, iclass 21, count 2 2006.183.08:03:11.68#ibcon#read 4, iclass 21, count 2 2006.183.08:03:11.68#ibcon#about to read 5, iclass 21, count 2 2006.183.08:03:11.68#ibcon#read 5, iclass 21, count 2 2006.183.08:03:11.68#ibcon#about to read 6, iclass 21, count 2 2006.183.08:03:11.68#ibcon#read 6, iclass 21, count 2 2006.183.08:03:11.68#ibcon#end of sib2, iclass 21, count 2 2006.183.08:03:11.68#ibcon#*mode == 0, iclass 21, count 2 2006.183.08:03:11.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.08:03:11.68#ibcon#[27=AT04-04\r\n] 2006.183.08:03:11.68#ibcon#*before write, iclass 21, count 2 2006.183.08:03:11.68#ibcon#enter sib2, iclass 21, count 2 2006.183.08:03:11.68#ibcon#flushed, iclass 21, count 2 2006.183.08:03:11.68#ibcon#about to write, iclass 21, count 2 2006.183.08:03:11.68#ibcon#wrote, iclass 21, count 2 2006.183.08:03:11.68#ibcon#about to read 3, iclass 21, count 2 2006.183.08:03:11.71#ibcon#read 3, iclass 21, count 2 2006.183.08:03:11.71#ibcon#about to read 4, iclass 21, count 2 2006.183.08:03:11.71#ibcon#read 4, iclass 21, count 2 2006.183.08:03:11.71#ibcon#about to read 5, iclass 21, count 2 2006.183.08:03:11.71#ibcon#read 5, iclass 21, count 2 2006.183.08:03:11.71#ibcon#about to read 6, iclass 21, count 2 2006.183.08:03:11.71#ibcon#read 6, iclass 21, count 2 2006.183.08:03:11.71#ibcon#end of sib2, iclass 21, count 2 2006.183.08:03:11.71#ibcon#*after write, iclass 21, count 2 2006.183.08:03:11.71#ibcon#*before return 0, iclass 21, count 2 2006.183.08:03:11.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:11.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:03:11.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.08:03:11.71#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:11.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:11.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:11.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:11.83#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:03:11.83#ibcon#first serial, iclass 21, count 0 2006.183.08:03:11.83#ibcon#enter sib2, iclass 21, count 0 2006.183.08:03:11.83#ibcon#flushed, iclass 21, count 0 2006.183.08:03:11.83#ibcon#about to write, iclass 21, count 0 2006.183.08:03:11.83#ibcon#wrote, iclass 21, count 0 2006.183.08:03:11.83#ibcon#about to read 3, iclass 21, count 0 2006.183.08:03:11.85#ibcon#read 3, iclass 21, count 0 2006.183.08:03:11.85#ibcon#about to read 4, iclass 21, count 0 2006.183.08:03:11.85#ibcon#read 4, iclass 21, count 0 2006.183.08:03:11.85#ibcon#about to read 5, iclass 21, count 0 2006.183.08:03:11.85#ibcon#read 5, iclass 21, count 0 2006.183.08:03:11.85#ibcon#about to read 6, iclass 21, count 0 2006.183.08:03:11.85#ibcon#read 6, iclass 21, count 0 2006.183.08:03:11.85#ibcon#end of sib2, iclass 21, count 0 2006.183.08:03:11.85#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:03:11.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:03:11.85#ibcon#[27=USB\r\n] 2006.183.08:03:11.85#ibcon#*before write, iclass 21, count 0 2006.183.08:03:11.85#ibcon#enter sib2, iclass 21, count 0 2006.183.08:03:11.85#ibcon#flushed, iclass 21, count 0 2006.183.08:03:11.85#ibcon#about to write, iclass 21, count 0 2006.183.08:03:11.85#ibcon#wrote, iclass 21, count 0 2006.183.08:03:11.85#ibcon#about to read 3, iclass 21, count 0 2006.183.08:03:11.88#ibcon#read 3, iclass 21, count 0 2006.183.08:03:11.88#ibcon#about to read 4, iclass 21, count 0 2006.183.08:03:11.88#ibcon#read 4, iclass 21, count 0 2006.183.08:03:11.88#ibcon#about to read 5, iclass 21, count 0 2006.183.08:03:11.88#ibcon#read 5, iclass 21, count 0 2006.183.08:03:11.88#ibcon#about to read 6, iclass 21, count 0 2006.183.08:03:11.88#ibcon#read 6, iclass 21, count 0 2006.183.08:03:11.88#ibcon#end of sib2, iclass 21, count 0 2006.183.08:03:11.88#ibcon#*after write, iclass 21, count 0 2006.183.08:03:11.88#ibcon#*before return 0, iclass 21, count 0 2006.183.08:03:11.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:11.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:03:11.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:03:11.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:03:11.88$vc4f8/vblo=5,744.99 2006.183.08:03:11.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:03:11.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:03:11.88#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:11.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:11.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:11.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:11.88#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:03:11.88#ibcon#first serial, iclass 23, count 0 2006.183.08:03:11.88#ibcon#enter sib2, iclass 23, count 0 2006.183.08:03:11.88#ibcon#flushed, iclass 23, count 0 2006.183.08:03:11.88#ibcon#about to write, iclass 23, count 0 2006.183.08:03:11.88#ibcon#wrote, iclass 23, count 0 2006.183.08:03:11.88#ibcon#about to read 3, iclass 23, count 0 2006.183.08:03:11.90#ibcon#read 3, iclass 23, count 0 2006.183.08:03:11.90#ibcon#about to read 4, iclass 23, count 0 2006.183.08:03:11.90#ibcon#read 4, iclass 23, count 0 2006.183.08:03:11.90#ibcon#about to read 5, iclass 23, count 0 2006.183.08:03:11.90#ibcon#read 5, iclass 23, count 0 2006.183.08:03:11.90#ibcon#about to read 6, iclass 23, count 0 2006.183.08:03:11.90#ibcon#read 6, iclass 23, count 0 2006.183.08:03:11.90#ibcon#end of sib2, iclass 23, count 0 2006.183.08:03:11.90#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:03:11.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:03:11.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:03:11.90#ibcon#*before write, iclass 23, count 0 2006.183.08:03:11.90#ibcon#enter sib2, iclass 23, count 0 2006.183.08:03:11.90#ibcon#flushed, iclass 23, count 0 2006.183.08:03:11.90#ibcon#about to write, iclass 23, count 0 2006.183.08:03:11.90#ibcon#wrote, iclass 23, count 0 2006.183.08:03:11.90#ibcon#about to read 3, iclass 23, count 0 2006.183.08:03:11.94#ibcon#read 3, iclass 23, count 0 2006.183.08:03:11.94#ibcon#about to read 4, iclass 23, count 0 2006.183.08:03:11.94#ibcon#read 4, iclass 23, count 0 2006.183.08:03:11.94#ibcon#about to read 5, iclass 23, count 0 2006.183.08:03:11.94#ibcon#read 5, iclass 23, count 0 2006.183.08:03:11.94#ibcon#about to read 6, iclass 23, count 0 2006.183.08:03:11.94#ibcon#read 6, iclass 23, count 0 2006.183.08:03:11.94#ibcon#end of sib2, iclass 23, count 0 2006.183.08:03:11.94#ibcon#*after write, iclass 23, count 0 2006.183.08:03:11.94#ibcon#*before return 0, iclass 23, count 0 2006.183.08:03:11.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:11.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:03:11.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:03:11.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:03:11.94$vc4f8/vb=5,4 2006.183.08:03:11.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.08:03:11.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.08:03:11.94#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:11.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:12.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:12.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:12.00#ibcon#enter wrdev, iclass 25, count 2 2006.183.08:03:12.00#ibcon#first serial, iclass 25, count 2 2006.183.08:03:12.00#ibcon#enter sib2, iclass 25, count 2 2006.183.08:03:12.00#ibcon#flushed, iclass 25, count 2 2006.183.08:03:12.00#ibcon#about to write, iclass 25, count 2 2006.183.08:03:12.00#ibcon#wrote, iclass 25, count 2 2006.183.08:03:12.00#ibcon#about to read 3, iclass 25, count 2 2006.183.08:03:12.02#ibcon#read 3, iclass 25, count 2 2006.183.08:03:12.02#ibcon#about to read 4, iclass 25, count 2 2006.183.08:03:12.02#ibcon#read 4, iclass 25, count 2 2006.183.08:03:12.02#ibcon#about to read 5, iclass 25, count 2 2006.183.08:03:12.02#ibcon#read 5, iclass 25, count 2 2006.183.08:03:12.02#ibcon#about to read 6, iclass 25, count 2 2006.183.08:03:12.02#ibcon#read 6, iclass 25, count 2 2006.183.08:03:12.02#ibcon#end of sib2, iclass 25, count 2 2006.183.08:03:12.02#ibcon#*mode == 0, iclass 25, count 2 2006.183.08:03:12.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.08:03:12.02#ibcon#[27=AT05-04\r\n] 2006.183.08:03:12.02#ibcon#*before write, iclass 25, count 2 2006.183.08:03:12.02#ibcon#enter sib2, iclass 25, count 2 2006.183.08:03:12.02#ibcon#flushed, iclass 25, count 2 2006.183.08:03:12.02#ibcon#about to write, iclass 25, count 2 2006.183.08:03:12.02#ibcon#wrote, iclass 25, count 2 2006.183.08:03:12.02#ibcon#about to read 3, iclass 25, count 2 2006.183.08:03:12.05#ibcon#read 3, iclass 25, count 2 2006.183.08:03:12.05#ibcon#about to read 4, iclass 25, count 2 2006.183.08:03:12.05#ibcon#read 4, iclass 25, count 2 2006.183.08:03:12.05#ibcon#about to read 5, iclass 25, count 2 2006.183.08:03:12.05#ibcon#read 5, iclass 25, count 2 2006.183.08:03:12.05#ibcon#about to read 6, iclass 25, count 2 2006.183.08:03:12.05#ibcon#read 6, iclass 25, count 2 2006.183.08:03:12.05#ibcon#end of sib2, iclass 25, count 2 2006.183.08:03:12.05#ibcon#*after write, iclass 25, count 2 2006.183.08:03:12.05#ibcon#*before return 0, iclass 25, count 2 2006.183.08:03:12.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:12.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:03:12.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.08:03:12.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:12.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:12.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:12.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:12.17#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:03:12.17#ibcon#first serial, iclass 25, count 0 2006.183.08:03:12.17#ibcon#enter sib2, iclass 25, count 0 2006.183.08:03:12.17#ibcon#flushed, iclass 25, count 0 2006.183.08:03:12.17#ibcon#about to write, iclass 25, count 0 2006.183.08:03:12.17#ibcon#wrote, iclass 25, count 0 2006.183.08:03:12.17#ibcon#about to read 3, iclass 25, count 0 2006.183.08:03:12.19#ibcon#read 3, iclass 25, count 0 2006.183.08:03:12.19#ibcon#about to read 4, iclass 25, count 0 2006.183.08:03:12.19#ibcon#read 4, iclass 25, count 0 2006.183.08:03:12.19#ibcon#about to read 5, iclass 25, count 0 2006.183.08:03:12.19#ibcon#read 5, iclass 25, count 0 2006.183.08:03:12.19#ibcon#about to read 6, iclass 25, count 0 2006.183.08:03:12.19#ibcon#read 6, iclass 25, count 0 2006.183.08:03:12.19#ibcon#end of sib2, iclass 25, count 0 2006.183.08:03:12.19#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:03:12.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:03:12.19#ibcon#[27=USB\r\n] 2006.183.08:03:12.19#ibcon#*before write, iclass 25, count 0 2006.183.08:03:12.19#ibcon#enter sib2, iclass 25, count 0 2006.183.08:03:12.19#ibcon#flushed, iclass 25, count 0 2006.183.08:03:12.19#ibcon#about to write, iclass 25, count 0 2006.183.08:03:12.19#ibcon#wrote, iclass 25, count 0 2006.183.08:03:12.19#ibcon#about to read 3, iclass 25, count 0 2006.183.08:03:12.22#ibcon#read 3, iclass 25, count 0 2006.183.08:03:12.22#ibcon#about to read 4, iclass 25, count 0 2006.183.08:03:12.22#ibcon#read 4, iclass 25, count 0 2006.183.08:03:12.22#ibcon#about to read 5, iclass 25, count 0 2006.183.08:03:12.22#ibcon#read 5, iclass 25, count 0 2006.183.08:03:12.22#ibcon#about to read 6, iclass 25, count 0 2006.183.08:03:12.22#ibcon#read 6, iclass 25, count 0 2006.183.08:03:12.22#ibcon#end of sib2, iclass 25, count 0 2006.183.08:03:12.22#ibcon#*after write, iclass 25, count 0 2006.183.08:03:12.22#ibcon#*before return 0, iclass 25, count 0 2006.183.08:03:12.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:12.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:03:12.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:03:12.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:03:12.22$vc4f8/vblo=6,752.99 2006.183.08:03:12.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.08:03:12.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.08:03:12.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:03:12.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:12.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:12.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:12.22#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:03:12.22#ibcon#first serial, iclass 27, count 0 2006.183.08:03:12.22#ibcon#enter sib2, iclass 27, count 0 2006.183.08:03:12.22#ibcon#flushed, iclass 27, count 0 2006.183.08:03:12.22#ibcon#about to write, iclass 27, count 0 2006.183.08:03:12.22#ibcon#wrote, iclass 27, count 0 2006.183.08:03:12.22#ibcon#about to read 3, iclass 27, count 0 2006.183.08:03:12.24#ibcon#read 3, iclass 27, count 0 2006.183.08:03:12.24#ibcon#about to read 4, iclass 27, count 0 2006.183.08:03:12.24#ibcon#read 4, iclass 27, count 0 2006.183.08:03:12.24#ibcon#about to read 5, iclass 27, count 0 2006.183.08:03:12.24#ibcon#read 5, iclass 27, count 0 2006.183.08:03:12.24#ibcon#about to read 6, iclass 27, count 0 2006.183.08:03:12.24#ibcon#read 6, iclass 27, count 0 2006.183.08:03:12.24#ibcon#end of sib2, iclass 27, count 0 2006.183.08:03:12.24#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:03:12.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:03:12.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:03:12.24#ibcon#*before write, iclass 27, count 0 2006.183.08:03:12.24#ibcon#enter sib2, iclass 27, count 0 2006.183.08:03:12.24#ibcon#flushed, iclass 27, count 0 2006.183.08:03:12.24#ibcon#about to write, iclass 27, count 0 2006.183.08:03:12.24#ibcon#wrote, iclass 27, count 0 2006.183.08:03:12.24#ibcon#about to read 3, iclass 27, count 0 2006.183.08:03:12.28#ibcon#read 3, iclass 27, count 0 2006.183.08:03:12.28#ibcon#about to read 4, iclass 27, count 0 2006.183.08:03:12.28#ibcon#read 4, iclass 27, count 0 2006.183.08:03:12.28#ibcon#about to read 5, iclass 27, count 0 2006.183.08:03:12.28#ibcon#read 5, iclass 27, count 0 2006.183.08:03:12.28#ibcon#about to read 6, iclass 27, count 0 2006.183.08:03:12.28#ibcon#read 6, iclass 27, count 0 2006.183.08:03:12.28#ibcon#end of sib2, iclass 27, count 0 2006.183.08:03:12.28#ibcon#*after write, iclass 27, count 0 2006.183.08:03:12.28#ibcon#*before return 0, iclass 27, count 0 2006.183.08:03:12.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:12.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:03:12.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:03:12.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:03:12.28$vc4f8/vb=6,4 2006.183.08:03:12.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.08:03:12.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.08:03:12.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:03:12.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:12.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:12.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:12.34#ibcon#enter wrdev, iclass 29, count 2 2006.183.08:03:12.34#ibcon#first serial, iclass 29, count 2 2006.183.08:03:12.34#ibcon#enter sib2, iclass 29, count 2 2006.183.08:03:12.34#ibcon#flushed, iclass 29, count 2 2006.183.08:03:12.34#ibcon#about to write, iclass 29, count 2 2006.183.08:03:12.34#ibcon#wrote, iclass 29, count 2 2006.183.08:03:12.34#ibcon#about to read 3, iclass 29, count 2 2006.183.08:03:12.36#ibcon#read 3, iclass 29, count 2 2006.183.08:03:12.36#ibcon#about to read 4, iclass 29, count 2 2006.183.08:03:12.36#ibcon#read 4, iclass 29, count 2 2006.183.08:03:12.36#ibcon#about to read 5, iclass 29, count 2 2006.183.08:03:12.36#ibcon#read 5, iclass 29, count 2 2006.183.08:03:12.36#ibcon#about to read 6, iclass 29, count 2 2006.183.08:03:12.36#ibcon#read 6, iclass 29, count 2 2006.183.08:03:12.36#ibcon#end of sib2, iclass 29, count 2 2006.183.08:03:12.36#ibcon#*mode == 0, iclass 29, count 2 2006.183.08:03:12.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.08:03:12.36#ibcon#[27=AT06-04\r\n] 2006.183.08:03:12.36#ibcon#*before write, iclass 29, count 2 2006.183.08:03:12.36#ibcon#enter sib2, iclass 29, count 2 2006.183.08:03:12.36#ibcon#flushed, iclass 29, count 2 2006.183.08:03:12.36#ibcon#about to write, iclass 29, count 2 2006.183.08:03:12.36#ibcon#wrote, iclass 29, count 2 2006.183.08:03:12.36#ibcon#about to read 3, iclass 29, count 2 2006.183.08:03:12.39#ibcon#read 3, iclass 29, count 2 2006.183.08:03:12.39#ibcon#about to read 4, iclass 29, count 2 2006.183.08:03:12.39#ibcon#read 4, iclass 29, count 2 2006.183.08:03:12.39#ibcon#about to read 5, iclass 29, count 2 2006.183.08:03:12.39#ibcon#read 5, iclass 29, count 2 2006.183.08:03:12.39#ibcon#about to read 6, iclass 29, count 2 2006.183.08:03:12.39#ibcon#read 6, iclass 29, count 2 2006.183.08:03:12.39#ibcon#end of sib2, iclass 29, count 2 2006.183.08:03:12.39#ibcon#*after write, iclass 29, count 2 2006.183.08:03:12.39#ibcon#*before return 0, iclass 29, count 2 2006.183.08:03:12.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:12.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:03:12.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.08:03:12.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:03:12.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:12.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:12.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:12.51#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:03:12.51#ibcon#first serial, iclass 29, count 0 2006.183.08:03:12.51#ibcon#enter sib2, iclass 29, count 0 2006.183.08:03:12.51#ibcon#flushed, iclass 29, count 0 2006.183.08:03:12.51#ibcon#about to write, iclass 29, count 0 2006.183.08:03:12.51#ibcon#wrote, iclass 29, count 0 2006.183.08:03:12.51#ibcon#about to read 3, iclass 29, count 0 2006.183.08:03:12.53#ibcon#read 3, iclass 29, count 0 2006.183.08:03:12.53#ibcon#about to read 4, iclass 29, count 0 2006.183.08:03:12.53#ibcon#read 4, iclass 29, count 0 2006.183.08:03:12.53#ibcon#about to read 5, iclass 29, count 0 2006.183.08:03:12.53#ibcon#read 5, iclass 29, count 0 2006.183.08:03:12.53#ibcon#about to read 6, iclass 29, count 0 2006.183.08:03:12.53#ibcon#read 6, iclass 29, count 0 2006.183.08:03:12.53#ibcon#end of sib2, iclass 29, count 0 2006.183.08:03:12.53#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:03:12.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:03:12.53#ibcon#[27=USB\r\n] 2006.183.08:03:12.53#ibcon#*before write, iclass 29, count 0 2006.183.08:03:12.53#ibcon#enter sib2, iclass 29, count 0 2006.183.08:03:12.53#ibcon#flushed, iclass 29, count 0 2006.183.08:03:12.53#ibcon#about to write, iclass 29, count 0 2006.183.08:03:12.53#ibcon#wrote, iclass 29, count 0 2006.183.08:03:12.53#ibcon#about to read 3, iclass 29, count 0 2006.183.08:03:12.56#ibcon#read 3, iclass 29, count 0 2006.183.08:03:12.56#ibcon#about to read 4, iclass 29, count 0 2006.183.08:03:12.56#ibcon#read 4, iclass 29, count 0 2006.183.08:03:12.56#ibcon#about to read 5, iclass 29, count 0 2006.183.08:03:12.56#ibcon#read 5, iclass 29, count 0 2006.183.08:03:12.56#ibcon#about to read 6, iclass 29, count 0 2006.183.08:03:12.56#ibcon#read 6, iclass 29, count 0 2006.183.08:03:12.56#ibcon#end of sib2, iclass 29, count 0 2006.183.08:03:12.56#ibcon#*after write, iclass 29, count 0 2006.183.08:03:12.56#ibcon#*before return 0, iclass 29, count 0 2006.183.08:03:12.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:12.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:03:12.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:03:12.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:03:12.56$vc4f8/vabw=wide 2006.183.08:03:12.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.08:03:12.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.08:03:12.56#ibcon#ireg 8 cls_cnt 0 2006.183.08:03:12.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:12.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:12.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:12.56#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:03:12.56#ibcon#first serial, iclass 31, count 0 2006.183.08:03:12.56#ibcon#enter sib2, iclass 31, count 0 2006.183.08:03:12.56#ibcon#flushed, iclass 31, count 0 2006.183.08:03:12.56#ibcon#about to write, iclass 31, count 0 2006.183.08:03:12.56#ibcon#wrote, iclass 31, count 0 2006.183.08:03:12.56#ibcon#about to read 3, iclass 31, count 0 2006.183.08:03:12.58#ibcon#read 3, iclass 31, count 0 2006.183.08:03:12.58#ibcon#about to read 4, iclass 31, count 0 2006.183.08:03:12.58#ibcon#read 4, iclass 31, count 0 2006.183.08:03:12.58#ibcon#about to read 5, iclass 31, count 0 2006.183.08:03:12.58#ibcon#read 5, iclass 31, count 0 2006.183.08:03:12.58#ibcon#about to read 6, iclass 31, count 0 2006.183.08:03:12.58#ibcon#read 6, iclass 31, count 0 2006.183.08:03:12.58#ibcon#end of sib2, iclass 31, count 0 2006.183.08:03:12.58#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:03:12.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:03:12.58#ibcon#[25=BW32\r\n] 2006.183.08:03:12.58#ibcon#*before write, iclass 31, count 0 2006.183.08:03:12.58#ibcon#enter sib2, iclass 31, count 0 2006.183.08:03:12.58#ibcon#flushed, iclass 31, count 0 2006.183.08:03:12.58#ibcon#about to write, iclass 31, count 0 2006.183.08:03:12.58#ibcon#wrote, iclass 31, count 0 2006.183.08:03:12.58#ibcon#about to read 3, iclass 31, count 0 2006.183.08:03:12.61#ibcon#read 3, iclass 31, count 0 2006.183.08:03:12.61#ibcon#about to read 4, iclass 31, count 0 2006.183.08:03:12.61#ibcon#read 4, iclass 31, count 0 2006.183.08:03:12.61#ibcon#about to read 5, iclass 31, count 0 2006.183.08:03:12.61#ibcon#read 5, iclass 31, count 0 2006.183.08:03:12.61#ibcon#about to read 6, iclass 31, count 0 2006.183.08:03:12.61#ibcon#read 6, iclass 31, count 0 2006.183.08:03:12.61#ibcon#end of sib2, iclass 31, count 0 2006.183.08:03:12.61#ibcon#*after write, iclass 31, count 0 2006.183.08:03:12.61#ibcon#*before return 0, iclass 31, count 0 2006.183.08:03:12.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:12.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:03:12.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:03:12.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:03:12.61$vc4f8/vbbw=wide 2006.183.08:03:12.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.08:03:12.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.08:03:12.61#ibcon#ireg 8 cls_cnt 0 2006.183.08:03:12.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:03:12.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:03:12.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:03:12.68#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:03:12.68#ibcon#first serial, iclass 33, count 0 2006.183.08:03:12.68#ibcon#enter sib2, iclass 33, count 0 2006.183.08:03:12.68#ibcon#flushed, iclass 33, count 0 2006.183.08:03:12.68#ibcon#about to write, iclass 33, count 0 2006.183.08:03:12.68#ibcon#wrote, iclass 33, count 0 2006.183.08:03:12.68#ibcon#about to read 3, iclass 33, count 0 2006.183.08:03:12.70#ibcon#read 3, iclass 33, count 0 2006.183.08:03:12.70#ibcon#about to read 4, iclass 33, count 0 2006.183.08:03:12.70#ibcon#read 4, iclass 33, count 0 2006.183.08:03:12.70#ibcon#about to read 5, iclass 33, count 0 2006.183.08:03:12.70#ibcon#read 5, iclass 33, count 0 2006.183.08:03:12.70#ibcon#about to read 6, iclass 33, count 0 2006.183.08:03:12.70#ibcon#read 6, iclass 33, count 0 2006.183.08:03:12.70#ibcon#end of sib2, iclass 33, count 0 2006.183.08:03:12.70#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:03:12.70#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:03:12.70#ibcon#[27=BW32\r\n] 2006.183.08:03:12.70#ibcon#*before write, iclass 33, count 0 2006.183.08:03:12.70#ibcon#enter sib2, iclass 33, count 0 2006.183.08:03:12.70#ibcon#flushed, iclass 33, count 0 2006.183.08:03:12.70#ibcon#about to write, iclass 33, count 0 2006.183.08:03:12.70#ibcon#wrote, iclass 33, count 0 2006.183.08:03:12.70#ibcon#about to read 3, iclass 33, count 0 2006.183.08:03:12.73#ibcon#read 3, iclass 33, count 0 2006.183.08:03:12.73#ibcon#about to read 4, iclass 33, count 0 2006.183.08:03:12.73#ibcon#read 4, iclass 33, count 0 2006.183.08:03:12.73#ibcon#about to read 5, iclass 33, count 0 2006.183.08:03:12.73#ibcon#read 5, iclass 33, count 0 2006.183.08:03:12.73#ibcon#about to read 6, iclass 33, count 0 2006.183.08:03:12.73#ibcon#read 6, iclass 33, count 0 2006.183.08:03:12.73#ibcon#end of sib2, iclass 33, count 0 2006.183.08:03:12.73#ibcon#*after write, iclass 33, count 0 2006.183.08:03:12.73#ibcon#*before return 0, iclass 33, count 0 2006.183.08:03:12.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:03:12.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:03:12.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:03:12.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:03:12.73$4f8m12a/ifd4f 2006.183.08:03:12.73$ifd4f/lo= 2006.183.08:03:12.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:03:12.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:03:12.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:03:12.73$ifd4f/patch= 2006.183.08:03:12.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:03:12.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:03:12.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:03:12.73$4f8m12a/"form=m,16.000,1:2 2006.183.08:03:12.73$4f8m12a/"tpicd 2006.183.08:03:12.73$4f8m12a/echo=off 2006.183.08:03:12.73$4f8m12a/xlog=off 2006.183.08:03:12.73:!2006.183.08:03:40 2006.183.08:03:18.14#trakl#Source acquired 2006.183.08:03:19.14#flagr#flagr/antenna,acquired 2006.183.08:03:40.00:preob 2006.183.08:03:41.14/onsource/TRACKING 2006.183.08:03:41.14:!2006.183.08:03:50 2006.183.08:03:50.00:data_valid=on 2006.183.08:03:50.00:midob 2006.183.08:03:50.14/onsource/TRACKING 2006.183.08:03:50.14/wx/28.24,996.5,86 2006.183.08:03:50.33/cable/+6.4526E-03 2006.183.08:03:51.42/va/01,08,usb,yes,29,31 2006.183.08:03:51.42/va/02,07,usb,yes,30,31 2006.183.08:03:51.42/va/03,06,usb,yes,31,31 2006.183.08:03:51.42/va/04,07,usb,yes,30,33 2006.183.08:03:51.42/va/05,07,usb,yes,32,34 2006.183.08:03:51.42/va/06,06,usb,yes,31,31 2006.183.08:03:51.42/va/07,06,usb,yes,32,31 2006.183.08:03:51.42/va/08,07,usb,yes,30,30 2006.183.08:03:51.65/valo/01,532.99,yes,locked 2006.183.08:03:51.65/valo/02,572.99,yes,locked 2006.183.08:03:51.65/valo/03,672.99,yes,locked 2006.183.08:03:51.65/valo/04,832.99,yes,locked 2006.183.08:03:51.65/valo/05,652.99,yes,locked 2006.183.08:03:51.65/valo/06,772.99,yes,locked 2006.183.08:03:51.65/valo/07,832.99,yes,locked 2006.183.08:03:51.65/valo/08,852.99,yes,locked 2006.183.08:03:52.74/vb/01,04,usb,yes,29,28 2006.183.08:03:52.74/vb/02,04,usb,yes,31,32 2006.183.08:03:52.74/vb/03,04,usb,yes,28,31 2006.183.08:03:52.74/vb/04,04,usb,yes,28,29 2006.183.08:03:52.74/vb/05,04,usb,yes,27,31 2006.183.08:03:52.74/vb/06,04,usb,yes,28,31 2006.183.08:03:52.74/vb/07,04,usb,yes,30,30 2006.183.08:03:52.74/vb/08,04,usb,yes,28,31 2006.183.08:03:52.97/vblo/01,632.99,yes,locked 2006.183.08:03:52.97/vblo/02,640.99,yes,locked 2006.183.08:03:52.97/vblo/03,656.99,yes,locked 2006.183.08:03:52.97/vblo/04,712.99,yes,locked 2006.183.08:03:52.97/vblo/05,744.99,yes,locked 2006.183.08:03:52.97/vblo/06,752.99,yes,locked 2006.183.08:03:52.97/vblo/07,734.99,yes,locked 2006.183.08:03:52.97/vblo/08,744.99,yes,locked 2006.183.08:03:53.12/vabw/8 2006.183.08:03:53.27/vbbw/8 2006.183.08:03:53.36/xfe/off,on,15.2 2006.183.08:03:53.76/ifatt/23,28,28,28 2006.183.08:03:54.08/fmout-gps/S +3.33E-07 2006.183.08:03:54.12:!2006.183.08:04:50 2006.183.08:04:50.00:data_valid=off 2006.183.08:04:50.00:postob 2006.183.08:04:50.09/cable/+6.4514E-03 2006.183.08:04:50.09/wx/28.27,996.5,85 2006.183.08:04:51.08/fmout-gps/S +3.33E-07 2006.183.08:04:51.08:scan_name=183-0805,k06183,60 2006.183.08:04:51.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.183.08:04:51.14#flagr#flagr/antenna,new-source 2006.183.08:04:52.14:checkk5 2006.183.08:04:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:04:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:04:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:04:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:04:54.01/chk_obsdata//k5ts1/T1830803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:04:54.38/chk_obsdata//k5ts2/T1830803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:04:54.75/chk_obsdata//k5ts3/T1830803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:04:55.12/chk_obsdata//k5ts4/T1830803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:04:55.81/k5log//k5ts1_log_newline 2006.183.08:04:56.50/k5log//k5ts2_log_newline 2006.183.08:04:57.19/k5log//k5ts3_log_newline 2006.183.08:04:57.88/k5log//k5ts4_log_newline 2006.183.08:04:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:04:57.90:4f8m12a=2 2006.183.08:04:57.90$4f8m12a/echo=on 2006.183.08:04:57.90$4f8m12a/pcalon 2006.183.08:04:57.90$pcalon/"no phase cal control is implemented here 2006.183.08:04:57.90$4f8m12a/"tpicd=stop 2006.183.08:04:57.90$4f8m12a/vc4f8 2006.183.08:04:57.90$vc4f8/valo=1,532.99 2006.183.08:04:57.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.08:04:57.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.08:04:57.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:04:57.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:04:57.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:04:57.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:04:57.91#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:04:57.91#ibcon#first serial, iclass 40, count 0 2006.183.08:04:57.91#ibcon#enter sib2, iclass 40, count 0 2006.183.08:04:57.91#ibcon#flushed, iclass 40, count 0 2006.183.08:04:57.91#ibcon#about to write, iclass 40, count 0 2006.183.08:04:57.91#ibcon#wrote, iclass 40, count 0 2006.183.08:04:57.91#ibcon#about to read 3, iclass 40, count 0 2006.183.08:04:57.94#ibcon#read 3, iclass 40, count 0 2006.183.08:04:57.94#ibcon#about to read 4, iclass 40, count 0 2006.183.08:04:57.94#ibcon#read 4, iclass 40, count 0 2006.183.08:04:57.94#ibcon#about to read 5, iclass 40, count 0 2006.183.08:04:57.94#ibcon#read 5, iclass 40, count 0 2006.183.08:04:57.94#ibcon#about to read 6, iclass 40, count 0 2006.183.08:04:57.94#ibcon#read 6, iclass 40, count 0 2006.183.08:04:57.94#ibcon#end of sib2, iclass 40, count 0 2006.183.08:04:57.94#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:04:57.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:04:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:04:57.94#ibcon#*before write, iclass 40, count 0 2006.183.08:04:57.94#ibcon#enter sib2, iclass 40, count 0 2006.183.08:04:57.94#ibcon#flushed, iclass 40, count 0 2006.183.08:04:57.94#ibcon#about to write, iclass 40, count 0 2006.183.08:04:57.94#ibcon#wrote, iclass 40, count 0 2006.183.08:04:57.94#ibcon#about to read 3, iclass 40, count 0 2006.183.08:04:58.00#ibcon#read 3, iclass 40, count 0 2006.183.08:04:58.00#ibcon#about to read 4, iclass 40, count 0 2006.183.08:04:58.00#ibcon#read 4, iclass 40, count 0 2006.183.08:04:58.00#ibcon#about to read 5, iclass 40, count 0 2006.183.08:04:58.00#ibcon#read 5, iclass 40, count 0 2006.183.08:04:58.00#ibcon#about to read 6, iclass 40, count 0 2006.183.08:04:58.00#ibcon#read 6, iclass 40, count 0 2006.183.08:04:58.00#ibcon#end of sib2, iclass 40, count 0 2006.183.08:04:58.00#ibcon#*after write, iclass 40, count 0 2006.183.08:04:58.00#ibcon#*before return 0, iclass 40, count 0 2006.183.08:04:58.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:04:58.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:04:58.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:04:58.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:04:58.00$vc4f8/va=1,8 2006.183.08:04:58.00#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.08:04:58.00#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.08:04:58.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:04:58.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:04:58.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:04:58.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:04:58.00#ibcon#enter wrdev, iclass 4, count 2 2006.183.08:04:58.00#ibcon#first serial, iclass 4, count 2 2006.183.08:04:58.00#ibcon#enter sib2, iclass 4, count 2 2006.183.08:04:58.00#ibcon#flushed, iclass 4, count 2 2006.183.08:04:58.00#ibcon#about to write, iclass 4, count 2 2006.183.08:04:58.00#ibcon#wrote, iclass 4, count 2 2006.183.08:04:58.00#ibcon#about to read 3, iclass 4, count 2 2006.183.08:04:58.02#ibcon#read 3, iclass 4, count 2 2006.183.08:04:58.02#ibcon#about to read 4, iclass 4, count 2 2006.183.08:04:58.02#ibcon#read 4, iclass 4, count 2 2006.183.08:04:58.02#ibcon#about to read 5, iclass 4, count 2 2006.183.08:04:58.02#ibcon#read 5, iclass 4, count 2 2006.183.08:04:58.02#ibcon#about to read 6, iclass 4, count 2 2006.183.08:04:58.02#ibcon#read 6, iclass 4, count 2 2006.183.08:04:58.02#ibcon#end of sib2, iclass 4, count 2 2006.183.08:04:58.02#ibcon#*mode == 0, iclass 4, count 2 2006.183.08:04:58.02#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.08:04:58.02#ibcon#[25=AT01-08\r\n] 2006.183.08:04:58.02#ibcon#*before write, iclass 4, count 2 2006.183.08:04:58.02#ibcon#enter sib2, iclass 4, count 2 2006.183.08:04:58.02#ibcon#flushed, iclass 4, count 2 2006.183.08:04:58.02#ibcon#about to write, iclass 4, count 2 2006.183.08:04:58.02#ibcon#wrote, iclass 4, count 2 2006.183.08:04:58.02#ibcon#about to read 3, iclass 4, count 2 2006.183.08:04:58.06#ibcon#read 3, iclass 4, count 2 2006.183.08:04:58.06#ibcon#about to read 4, iclass 4, count 2 2006.183.08:04:58.06#ibcon#read 4, iclass 4, count 2 2006.183.08:04:58.06#ibcon#about to read 5, iclass 4, count 2 2006.183.08:04:58.06#ibcon#read 5, iclass 4, count 2 2006.183.08:04:58.06#ibcon#about to read 6, iclass 4, count 2 2006.183.08:04:58.06#ibcon#read 6, iclass 4, count 2 2006.183.08:04:58.06#ibcon#end of sib2, iclass 4, count 2 2006.183.08:04:58.06#ibcon#*after write, iclass 4, count 2 2006.183.08:04:58.06#ibcon#*before return 0, iclass 4, count 2 2006.183.08:04:58.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:04:58.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:04:58.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.08:04:58.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:04:58.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:04:58.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:04:58.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:04:58.18#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:04:58.18#ibcon#first serial, iclass 4, count 0 2006.183.08:04:58.18#ibcon#enter sib2, iclass 4, count 0 2006.183.08:04:58.18#ibcon#flushed, iclass 4, count 0 2006.183.08:04:58.18#ibcon#about to write, iclass 4, count 0 2006.183.08:04:58.18#ibcon#wrote, iclass 4, count 0 2006.183.08:04:58.18#ibcon#about to read 3, iclass 4, count 0 2006.183.08:04:58.20#ibcon#read 3, iclass 4, count 0 2006.183.08:04:58.20#ibcon#about to read 4, iclass 4, count 0 2006.183.08:04:58.20#ibcon#read 4, iclass 4, count 0 2006.183.08:04:58.20#ibcon#about to read 5, iclass 4, count 0 2006.183.08:04:58.20#ibcon#read 5, iclass 4, count 0 2006.183.08:04:58.20#ibcon#about to read 6, iclass 4, count 0 2006.183.08:04:58.20#ibcon#read 6, iclass 4, count 0 2006.183.08:04:58.20#ibcon#end of sib2, iclass 4, count 0 2006.183.08:04:58.20#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:04:58.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:04:58.20#ibcon#[25=USB\r\n] 2006.183.08:04:58.20#ibcon#*before write, iclass 4, count 0 2006.183.08:04:58.20#ibcon#enter sib2, iclass 4, count 0 2006.183.08:04:58.20#ibcon#flushed, iclass 4, count 0 2006.183.08:04:58.20#ibcon#about to write, iclass 4, count 0 2006.183.08:04:58.20#ibcon#wrote, iclass 4, count 0 2006.183.08:04:58.20#ibcon#about to read 3, iclass 4, count 0 2006.183.08:04:58.23#ibcon#read 3, iclass 4, count 0 2006.183.08:04:58.23#ibcon#about to read 4, iclass 4, count 0 2006.183.08:04:58.23#ibcon#read 4, iclass 4, count 0 2006.183.08:04:58.23#ibcon#about to read 5, iclass 4, count 0 2006.183.08:04:58.23#ibcon#read 5, iclass 4, count 0 2006.183.08:04:58.23#ibcon#about to read 6, iclass 4, count 0 2006.183.08:04:58.23#ibcon#read 6, iclass 4, count 0 2006.183.08:04:58.23#ibcon#end of sib2, iclass 4, count 0 2006.183.08:04:58.23#ibcon#*after write, iclass 4, count 0 2006.183.08:04:58.23#ibcon#*before return 0, iclass 4, count 0 2006.183.08:04:58.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:04:58.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:04:58.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:04:58.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:04:58.23$vc4f8/valo=2,572.99 2006.183.08:04:58.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.08:04:58.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.08:04:58.23#ibcon#ireg 17 cls_cnt 0 2006.183.08:04:58.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:04:58.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:04:58.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:04:58.23#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:04:58.23#ibcon#first serial, iclass 6, count 0 2006.183.08:04:58.23#ibcon#enter sib2, iclass 6, count 0 2006.183.08:04:58.23#ibcon#flushed, iclass 6, count 0 2006.183.08:04:58.23#ibcon#about to write, iclass 6, count 0 2006.183.08:04:58.23#ibcon#wrote, iclass 6, count 0 2006.183.08:04:58.23#ibcon#about to read 3, iclass 6, count 0 2006.183.08:04:58.25#ibcon#read 3, iclass 6, count 0 2006.183.08:04:58.25#ibcon#about to read 4, iclass 6, count 0 2006.183.08:04:58.25#ibcon#read 4, iclass 6, count 0 2006.183.08:04:58.25#ibcon#about to read 5, iclass 6, count 0 2006.183.08:04:58.25#ibcon#read 5, iclass 6, count 0 2006.183.08:04:58.25#ibcon#about to read 6, iclass 6, count 0 2006.183.08:04:58.25#ibcon#read 6, iclass 6, count 0 2006.183.08:04:58.25#ibcon#end of sib2, iclass 6, count 0 2006.183.08:04:58.25#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:04:58.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:04:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:04:58.25#ibcon#*before write, iclass 6, count 0 2006.183.08:04:58.25#ibcon#enter sib2, iclass 6, count 0 2006.183.08:04:58.25#ibcon#flushed, iclass 6, count 0 2006.183.08:04:58.25#ibcon#about to write, iclass 6, count 0 2006.183.08:04:58.25#ibcon#wrote, iclass 6, count 0 2006.183.08:04:58.25#ibcon#about to read 3, iclass 6, count 0 2006.183.08:04:58.29#ibcon#read 3, iclass 6, count 0 2006.183.08:04:58.29#ibcon#about to read 4, iclass 6, count 0 2006.183.08:04:58.29#ibcon#read 4, iclass 6, count 0 2006.183.08:04:58.29#ibcon#about to read 5, iclass 6, count 0 2006.183.08:04:58.29#ibcon#read 5, iclass 6, count 0 2006.183.08:04:58.29#ibcon#about to read 6, iclass 6, count 0 2006.183.08:04:58.29#ibcon#read 6, iclass 6, count 0 2006.183.08:04:58.29#ibcon#end of sib2, iclass 6, count 0 2006.183.08:04:58.29#ibcon#*after write, iclass 6, count 0 2006.183.08:04:58.29#ibcon#*before return 0, iclass 6, count 0 2006.183.08:04:58.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:04:58.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:04:58.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:04:58.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:04:58.29$vc4f8/va=2,7 2006.183.08:04:58.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.08:04:58.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.08:04:58.29#ibcon#ireg 11 cls_cnt 2 2006.183.08:04:58.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:04:58.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:04:58.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:04:58.35#ibcon#enter wrdev, iclass 10, count 2 2006.183.08:04:58.35#ibcon#first serial, iclass 10, count 2 2006.183.08:04:58.35#ibcon#enter sib2, iclass 10, count 2 2006.183.08:04:58.35#ibcon#flushed, iclass 10, count 2 2006.183.08:04:58.35#ibcon#about to write, iclass 10, count 2 2006.183.08:04:58.35#ibcon#wrote, iclass 10, count 2 2006.183.08:04:58.35#ibcon#about to read 3, iclass 10, count 2 2006.183.08:04:58.37#ibcon#read 3, iclass 10, count 2 2006.183.08:04:58.37#ibcon#about to read 4, iclass 10, count 2 2006.183.08:04:58.37#ibcon#read 4, iclass 10, count 2 2006.183.08:04:58.37#ibcon#about to read 5, iclass 10, count 2 2006.183.08:04:58.37#ibcon#read 5, iclass 10, count 2 2006.183.08:04:58.37#ibcon#about to read 6, iclass 10, count 2 2006.183.08:04:58.37#ibcon#read 6, iclass 10, count 2 2006.183.08:04:58.37#ibcon#end of sib2, iclass 10, count 2 2006.183.08:04:58.37#ibcon#*mode == 0, iclass 10, count 2 2006.183.08:04:58.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.08:04:58.37#ibcon#[25=AT02-07\r\n] 2006.183.08:04:58.37#ibcon#*before write, iclass 10, count 2 2006.183.08:04:58.37#ibcon#enter sib2, iclass 10, count 2 2006.183.08:04:58.37#ibcon#flushed, iclass 10, count 2 2006.183.08:04:58.37#ibcon#about to write, iclass 10, count 2 2006.183.08:04:58.37#ibcon#wrote, iclass 10, count 2 2006.183.08:04:58.37#ibcon#about to read 3, iclass 10, count 2 2006.183.08:04:58.40#ibcon#read 3, iclass 10, count 2 2006.183.08:04:58.40#ibcon#about to read 4, iclass 10, count 2 2006.183.08:04:58.40#ibcon#read 4, iclass 10, count 2 2006.183.08:04:58.40#ibcon#about to read 5, iclass 10, count 2 2006.183.08:04:58.40#ibcon#read 5, iclass 10, count 2 2006.183.08:04:58.40#ibcon#about to read 6, iclass 10, count 2 2006.183.08:04:58.40#ibcon#read 6, iclass 10, count 2 2006.183.08:04:58.40#ibcon#end of sib2, iclass 10, count 2 2006.183.08:04:58.40#ibcon#*after write, iclass 10, count 2 2006.183.08:04:58.40#ibcon#*before return 0, iclass 10, count 2 2006.183.08:04:58.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:04:58.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:04:58.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.08:04:58.40#ibcon#ireg 7 cls_cnt 0 2006.183.08:04:58.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:04:58.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:04:58.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:04:58.52#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:04:58.52#ibcon#first serial, iclass 10, count 0 2006.183.08:04:58.52#ibcon#enter sib2, iclass 10, count 0 2006.183.08:04:58.52#ibcon#flushed, iclass 10, count 0 2006.183.08:04:58.52#ibcon#about to write, iclass 10, count 0 2006.183.08:04:58.52#ibcon#wrote, iclass 10, count 0 2006.183.08:04:58.52#ibcon#about to read 3, iclass 10, count 0 2006.183.08:04:58.54#ibcon#read 3, iclass 10, count 0 2006.183.08:04:58.54#ibcon#about to read 4, iclass 10, count 0 2006.183.08:04:58.54#ibcon#read 4, iclass 10, count 0 2006.183.08:04:58.54#ibcon#about to read 5, iclass 10, count 0 2006.183.08:04:58.54#ibcon#read 5, iclass 10, count 0 2006.183.08:04:58.54#ibcon#about to read 6, iclass 10, count 0 2006.183.08:04:58.54#ibcon#read 6, iclass 10, count 0 2006.183.08:04:58.54#ibcon#end of sib2, iclass 10, count 0 2006.183.08:04:58.54#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:04:58.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:04:58.54#ibcon#[25=USB\r\n] 2006.183.08:04:58.54#ibcon#*before write, iclass 10, count 0 2006.183.08:04:58.54#ibcon#enter sib2, iclass 10, count 0 2006.183.08:04:58.54#ibcon#flushed, iclass 10, count 0 2006.183.08:04:58.54#ibcon#about to write, iclass 10, count 0 2006.183.08:04:58.54#ibcon#wrote, iclass 10, count 0 2006.183.08:04:58.54#ibcon#about to read 3, iclass 10, count 0 2006.183.08:04:58.57#ibcon#read 3, iclass 10, count 0 2006.183.08:04:58.57#ibcon#about to read 4, iclass 10, count 0 2006.183.08:04:58.57#ibcon#read 4, iclass 10, count 0 2006.183.08:04:58.57#ibcon#about to read 5, iclass 10, count 0 2006.183.08:04:58.57#ibcon#read 5, iclass 10, count 0 2006.183.08:04:58.57#ibcon#about to read 6, iclass 10, count 0 2006.183.08:04:58.57#ibcon#read 6, iclass 10, count 0 2006.183.08:04:58.57#ibcon#end of sib2, iclass 10, count 0 2006.183.08:04:58.57#ibcon#*after write, iclass 10, count 0 2006.183.08:04:58.57#ibcon#*before return 0, iclass 10, count 0 2006.183.08:04:58.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:04:58.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:04:58.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:04:58.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:04:58.57$vc4f8/valo=3,672.99 2006.183.08:04:58.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.08:04:58.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.08:04:58.57#ibcon#ireg 17 cls_cnt 0 2006.183.08:04:58.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:04:58.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:04:58.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:04:58.57#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:04:58.57#ibcon#first serial, iclass 12, count 0 2006.183.08:04:58.57#ibcon#enter sib2, iclass 12, count 0 2006.183.08:04:58.57#ibcon#flushed, iclass 12, count 0 2006.183.08:04:58.57#ibcon#about to write, iclass 12, count 0 2006.183.08:04:58.57#ibcon#wrote, iclass 12, count 0 2006.183.08:04:58.57#ibcon#about to read 3, iclass 12, count 0 2006.183.08:04:58.59#ibcon#read 3, iclass 12, count 0 2006.183.08:04:58.59#ibcon#about to read 4, iclass 12, count 0 2006.183.08:04:58.59#ibcon#read 4, iclass 12, count 0 2006.183.08:04:58.59#ibcon#about to read 5, iclass 12, count 0 2006.183.08:04:58.59#ibcon#read 5, iclass 12, count 0 2006.183.08:04:58.59#ibcon#about to read 6, iclass 12, count 0 2006.183.08:04:58.59#ibcon#read 6, iclass 12, count 0 2006.183.08:04:58.59#ibcon#end of sib2, iclass 12, count 0 2006.183.08:04:58.59#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:04:58.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:04:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:04:58.59#ibcon#*before write, iclass 12, count 0 2006.183.08:04:58.59#ibcon#enter sib2, iclass 12, count 0 2006.183.08:04:58.59#ibcon#flushed, iclass 12, count 0 2006.183.08:04:58.59#ibcon#about to write, iclass 12, count 0 2006.183.08:04:58.59#ibcon#wrote, iclass 12, count 0 2006.183.08:04:58.59#ibcon#about to read 3, iclass 12, count 0 2006.183.08:04:58.64#ibcon#read 3, iclass 12, count 0 2006.183.08:04:58.64#ibcon#about to read 4, iclass 12, count 0 2006.183.08:04:58.64#ibcon#read 4, iclass 12, count 0 2006.183.08:04:58.64#ibcon#about to read 5, iclass 12, count 0 2006.183.08:04:58.64#ibcon#read 5, iclass 12, count 0 2006.183.08:04:58.64#ibcon#about to read 6, iclass 12, count 0 2006.183.08:04:58.64#ibcon#read 6, iclass 12, count 0 2006.183.08:04:58.64#ibcon#end of sib2, iclass 12, count 0 2006.183.08:04:58.64#ibcon#*after write, iclass 12, count 0 2006.183.08:04:58.64#ibcon#*before return 0, iclass 12, count 0 2006.183.08:04:58.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:04:58.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:04:58.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:04:58.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:04:58.64$vc4f8/va=3,6 2006.183.08:04:58.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.08:04:58.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.08:04:58.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:04:58.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:04:58.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:04:58.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:04:58.69#ibcon#enter wrdev, iclass 14, count 2 2006.183.08:04:58.69#ibcon#first serial, iclass 14, count 2 2006.183.08:04:58.69#ibcon#enter sib2, iclass 14, count 2 2006.183.08:04:58.69#ibcon#flushed, iclass 14, count 2 2006.183.08:04:58.69#ibcon#about to write, iclass 14, count 2 2006.183.08:04:58.69#ibcon#wrote, iclass 14, count 2 2006.183.08:04:58.69#ibcon#about to read 3, iclass 14, count 2 2006.183.08:04:58.71#ibcon#read 3, iclass 14, count 2 2006.183.08:04:58.71#ibcon#about to read 4, iclass 14, count 2 2006.183.08:04:58.71#ibcon#read 4, iclass 14, count 2 2006.183.08:04:58.71#ibcon#about to read 5, iclass 14, count 2 2006.183.08:04:58.71#ibcon#read 5, iclass 14, count 2 2006.183.08:04:58.71#ibcon#about to read 6, iclass 14, count 2 2006.183.08:04:58.71#ibcon#read 6, iclass 14, count 2 2006.183.08:04:58.71#ibcon#end of sib2, iclass 14, count 2 2006.183.08:04:58.71#ibcon#*mode == 0, iclass 14, count 2 2006.183.08:04:58.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.08:04:58.71#ibcon#[25=AT03-06\r\n] 2006.183.08:04:58.71#ibcon#*before write, iclass 14, count 2 2006.183.08:04:58.71#ibcon#enter sib2, iclass 14, count 2 2006.183.08:04:58.71#ibcon#flushed, iclass 14, count 2 2006.183.08:04:58.71#ibcon#about to write, iclass 14, count 2 2006.183.08:04:58.71#ibcon#wrote, iclass 14, count 2 2006.183.08:04:58.71#ibcon#about to read 3, iclass 14, count 2 2006.183.08:04:58.74#ibcon#read 3, iclass 14, count 2 2006.183.08:04:58.74#ibcon#about to read 4, iclass 14, count 2 2006.183.08:04:58.74#ibcon#read 4, iclass 14, count 2 2006.183.08:04:58.74#ibcon#about to read 5, iclass 14, count 2 2006.183.08:04:58.74#ibcon#read 5, iclass 14, count 2 2006.183.08:04:58.74#ibcon#about to read 6, iclass 14, count 2 2006.183.08:04:58.74#ibcon#read 6, iclass 14, count 2 2006.183.08:04:58.74#ibcon#end of sib2, iclass 14, count 2 2006.183.08:04:58.74#ibcon#*after write, iclass 14, count 2 2006.183.08:04:58.74#ibcon#*before return 0, iclass 14, count 2 2006.183.08:04:58.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:04:58.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:04:58.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.08:04:58.74#ibcon#ireg 7 cls_cnt 0 2006.183.08:04:58.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:04:58.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:04:58.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:04:58.86#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:04:58.86#ibcon#first serial, iclass 14, count 0 2006.183.08:04:58.86#ibcon#enter sib2, iclass 14, count 0 2006.183.08:04:58.86#ibcon#flushed, iclass 14, count 0 2006.183.08:04:58.86#ibcon#about to write, iclass 14, count 0 2006.183.08:04:58.86#ibcon#wrote, iclass 14, count 0 2006.183.08:04:58.86#ibcon#about to read 3, iclass 14, count 0 2006.183.08:04:58.88#ibcon#read 3, iclass 14, count 0 2006.183.08:04:58.88#ibcon#about to read 4, iclass 14, count 0 2006.183.08:04:58.88#ibcon#read 4, iclass 14, count 0 2006.183.08:04:58.88#ibcon#about to read 5, iclass 14, count 0 2006.183.08:04:58.88#ibcon#read 5, iclass 14, count 0 2006.183.08:04:58.88#ibcon#about to read 6, iclass 14, count 0 2006.183.08:04:58.88#ibcon#read 6, iclass 14, count 0 2006.183.08:04:58.88#ibcon#end of sib2, iclass 14, count 0 2006.183.08:04:58.88#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:04:58.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:04:58.88#ibcon#[25=USB\r\n] 2006.183.08:04:58.88#ibcon#*before write, iclass 14, count 0 2006.183.08:04:58.88#ibcon#enter sib2, iclass 14, count 0 2006.183.08:04:58.88#ibcon#flushed, iclass 14, count 0 2006.183.08:04:58.88#ibcon#about to write, iclass 14, count 0 2006.183.08:04:58.88#ibcon#wrote, iclass 14, count 0 2006.183.08:04:58.88#ibcon#about to read 3, iclass 14, count 0 2006.183.08:04:58.91#ibcon#read 3, iclass 14, count 0 2006.183.08:04:58.91#ibcon#about to read 4, iclass 14, count 0 2006.183.08:04:58.91#ibcon#read 4, iclass 14, count 0 2006.183.08:04:58.91#ibcon#about to read 5, iclass 14, count 0 2006.183.08:04:58.91#ibcon#read 5, iclass 14, count 0 2006.183.08:04:58.91#ibcon#about to read 6, iclass 14, count 0 2006.183.08:04:58.91#ibcon#read 6, iclass 14, count 0 2006.183.08:04:58.91#ibcon#end of sib2, iclass 14, count 0 2006.183.08:04:58.91#ibcon#*after write, iclass 14, count 0 2006.183.08:04:58.91#ibcon#*before return 0, iclass 14, count 0 2006.183.08:04:58.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:04:58.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:04:58.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:04:58.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:04:58.91$vc4f8/valo=4,832.99 2006.183.08:04:58.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.08:04:58.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.08:04:58.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:04:58.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:04:58.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:04:58.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:04:58.91#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:04:58.91#ibcon#first serial, iclass 16, count 0 2006.183.08:04:58.91#ibcon#enter sib2, iclass 16, count 0 2006.183.08:04:58.91#ibcon#flushed, iclass 16, count 0 2006.183.08:04:58.91#ibcon#about to write, iclass 16, count 0 2006.183.08:04:58.91#ibcon#wrote, iclass 16, count 0 2006.183.08:04:58.91#ibcon#about to read 3, iclass 16, count 0 2006.183.08:04:58.93#ibcon#read 3, iclass 16, count 0 2006.183.08:04:58.93#ibcon#about to read 4, iclass 16, count 0 2006.183.08:04:58.93#ibcon#read 4, iclass 16, count 0 2006.183.08:04:58.93#ibcon#about to read 5, iclass 16, count 0 2006.183.08:04:58.93#ibcon#read 5, iclass 16, count 0 2006.183.08:04:58.93#ibcon#about to read 6, iclass 16, count 0 2006.183.08:04:58.93#ibcon#read 6, iclass 16, count 0 2006.183.08:04:58.93#ibcon#end of sib2, iclass 16, count 0 2006.183.08:04:58.93#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:04:58.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:04:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:04:58.93#ibcon#*before write, iclass 16, count 0 2006.183.08:04:58.93#ibcon#enter sib2, iclass 16, count 0 2006.183.08:04:58.93#ibcon#flushed, iclass 16, count 0 2006.183.08:04:58.93#ibcon#about to write, iclass 16, count 0 2006.183.08:04:58.93#ibcon#wrote, iclass 16, count 0 2006.183.08:04:58.93#ibcon#about to read 3, iclass 16, count 0 2006.183.08:04:58.97#ibcon#read 3, iclass 16, count 0 2006.183.08:04:58.97#ibcon#about to read 4, iclass 16, count 0 2006.183.08:04:58.97#ibcon#read 4, iclass 16, count 0 2006.183.08:04:58.97#ibcon#about to read 5, iclass 16, count 0 2006.183.08:04:58.97#ibcon#read 5, iclass 16, count 0 2006.183.08:04:58.97#ibcon#about to read 6, iclass 16, count 0 2006.183.08:04:58.97#ibcon#read 6, iclass 16, count 0 2006.183.08:04:58.97#ibcon#end of sib2, iclass 16, count 0 2006.183.08:04:58.97#ibcon#*after write, iclass 16, count 0 2006.183.08:04:58.97#ibcon#*before return 0, iclass 16, count 0 2006.183.08:04:58.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:04:58.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:04:58.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:04:58.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:04:58.97$vc4f8/va=4,7 2006.183.08:04:58.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.08:04:58.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.08:04:58.97#ibcon#ireg 11 cls_cnt 2 2006.183.08:04:58.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:04:59.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:04:59.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:04:59.03#ibcon#enter wrdev, iclass 18, count 2 2006.183.08:04:59.03#ibcon#first serial, iclass 18, count 2 2006.183.08:04:59.03#ibcon#enter sib2, iclass 18, count 2 2006.183.08:04:59.03#ibcon#flushed, iclass 18, count 2 2006.183.08:04:59.03#ibcon#about to write, iclass 18, count 2 2006.183.08:04:59.03#ibcon#wrote, iclass 18, count 2 2006.183.08:04:59.03#ibcon#about to read 3, iclass 18, count 2 2006.183.08:04:59.05#ibcon#read 3, iclass 18, count 2 2006.183.08:04:59.05#ibcon#about to read 4, iclass 18, count 2 2006.183.08:04:59.05#ibcon#read 4, iclass 18, count 2 2006.183.08:04:59.05#ibcon#about to read 5, iclass 18, count 2 2006.183.08:04:59.05#ibcon#read 5, iclass 18, count 2 2006.183.08:04:59.05#ibcon#about to read 6, iclass 18, count 2 2006.183.08:04:59.05#ibcon#read 6, iclass 18, count 2 2006.183.08:04:59.05#ibcon#end of sib2, iclass 18, count 2 2006.183.08:04:59.05#ibcon#*mode == 0, iclass 18, count 2 2006.183.08:04:59.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.08:04:59.05#ibcon#[25=AT04-07\r\n] 2006.183.08:04:59.05#ibcon#*before write, iclass 18, count 2 2006.183.08:04:59.05#ibcon#enter sib2, iclass 18, count 2 2006.183.08:04:59.05#ibcon#flushed, iclass 18, count 2 2006.183.08:04:59.05#ibcon#about to write, iclass 18, count 2 2006.183.08:04:59.05#ibcon#wrote, iclass 18, count 2 2006.183.08:04:59.05#ibcon#about to read 3, iclass 18, count 2 2006.183.08:04:59.08#ibcon#read 3, iclass 18, count 2 2006.183.08:04:59.08#ibcon#about to read 4, iclass 18, count 2 2006.183.08:04:59.08#ibcon#read 4, iclass 18, count 2 2006.183.08:04:59.08#ibcon#about to read 5, iclass 18, count 2 2006.183.08:04:59.08#ibcon#read 5, iclass 18, count 2 2006.183.08:04:59.08#ibcon#about to read 6, iclass 18, count 2 2006.183.08:04:59.08#ibcon#read 6, iclass 18, count 2 2006.183.08:04:59.08#ibcon#end of sib2, iclass 18, count 2 2006.183.08:04:59.08#ibcon#*after write, iclass 18, count 2 2006.183.08:04:59.08#ibcon#*before return 0, iclass 18, count 2 2006.183.08:04:59.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:04:59.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:04:59.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.08:04:59.08#ibcon#ireg 7 cls_cnt 0 2006.183.08:04:59.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:04:59.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:04:59.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:04:59.20#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:04:59.20#ibcon#first serial, iclass 18, count 0 2006.183.08:04:59.20#ibcon#enter sib2, iclass 18, count 0 2006.183.08:04:59.20#ibcon#flushed, iclass 18, count 0 2006.183.08:04:59.20#ibcon#about to write, iclass 18, count 0 2006.183.08:04:59.20#ibcon#wrote, iclass 18, count 0 2006.183.08:04:59.20#ibcon#about to read 3, iclass 18, count 0 2006.183.08:04:59.22#ibcon#read 3, iclass 18, count 0 2006.183.08:04:59.22#ibcon#about to read 4, iclass 18, count 0 2006.183.08:04:59.22#ibcon#read 4, iclass 18, count 0 2006.183.08:04:59.22#ibcon#about to read 5, iclass 18, count 0 2006.183.08:04:59.22#ibcon#read 5, iclass 18, count 0 2006.183.08:04:59.22#ibcon#about to read 6, iclass 18, count 0 2006.183.08:04:59.22#ibcon#read 6, iclass 18, count 0 2006.183.08:04:59.22#ibcon#end of sib2, iclass 18, count 0 2006.183.08:04:59.22#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:04:59.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:04:59.22#ibcon#[25=USB\r\n] 2006.183.08:04:59.22#ibcon#*before write, iclass 18, count 0 2006.183.08:04:59.22#ibcon#enter sib2, iclass 18, count 0 2006.183.08:04:59.22#ibcon#flushed, iclass 18, count 0 2006.183.08:04:59.22#ibcon#about to write, iclass 18, count 0 2006.183.08:04:59.22#ibcon#wrote, iclass 18, count 0 2006.183.08:04:59.22#ibcon#about to read 3, iclass 18, count 0 2006.183.08:04:59.25#ibcon#read 3, iclass 18, count 0 2006.183.08:04:59.25#ibcon#about to read 4, iclass 18, count 0 2006.183.08:04:59.25#ibcon#read 4, iclass 18, count 0 2006.183.08:04:59.25#ibcon#about to read 5, iclass 18, count 0 2006.183.08:04:59.25#ibcon#read 5, iclass 18, count 0 2006.183.08:04:59.25#ibcon#about to read 6, iclass 18, count 0 2006.183.08:04:59.25#ibcon#read 6, iclass 18, count 0 2006.183.08:04:59.25#ibcon#end of sib2, iclass 18, count 0 2006.183.08:04:59.25#ibcon#*after write, iclass 18, count 0 2006.183.08:04:59.25#ibcon#*before return 0, iclass 18, count 0 2006.183.08:04:59.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:04:59.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:04:59.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:04:59.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:04:59.25$vc4f8/valo=5,652.99 2006.183.08:04:59.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.08:04:59.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.08:04:59.25#ibcon#ireg 17 cls_cnt 0 2006.183.08:04:59.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:04:59.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:04:59.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:04:59.25#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:04:59.25#ibcon#first serial, iclass 20, count 0 2006.183.08:04:59.25#ibcon#enter sib2, iclass 20, count 0 2006.183.08:04:59.25#ibcon#flushed, iclass 20, count 0 2006.183.08:04:59.25#ibcon#about to write, iclass 20, count 0 2006.183.08:04:59.25#ibcon#wrote, iclass 20, count 0 2006.183.08:04:59.25#ibcon#about to read 3, iclass 20, count 0 2006.183.08:04:59.27#ibcon#read 3, iclass 20, count 0 2006.183.08:04:59.27#ibcon#about to read 4, iclass 20, count 0 2006.183.08:04:59.27#ibcon#read 4, iclass 20, count 0 2006.183.08:04:59.27#ibcon#about to read 5, iclass 20, count 0 2006.183.08:04:59.27#ibcon#read 5, iclass 20, count 0 2006.183.08:04:59.27#ibcon#about to read 6, iclass 20, count 0 2006.183.08:04:59.27#ibcon#read 6, iclass 20, count 0 2006.183.08:04:59.27#ibcon#end of sib2, iclass 20, count 0 2006.183.08:04:59.27#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:04:59.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:04:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:04:59.27#ibcon#*before write, iclass 20, count 0 2006.183.08:04:59.27#ibcon#enter sib2, iclass 20, count 0 2006.183.08:04:59.27#ibcon#flushed, iclass 20, count 0 2006.183.08:04:59.27#ibcon#about to write, iclass 20, count 0 2006.183.08:04:59.27#ibcon#wrote, iclass 20, count 0 2006.183.08:04:59.27#ibcon#about to read 3, iclass 20, count 0 2006.183.08:04:59.31#ibcon#read 3, iclass 20, count 0 2006.183.08:04:59.31#ibcon#about to read 4, iclass 20, count 0 2006.183.08:04:59.31#ibcon#read 4, iclass 20, count 0 2006.183.08:04:59.31#ibcon#about to read 5, iclass 20, count 0 2006.183.08:04:59.31#ibcon#read 5, iclass 20, count 0 2006.183.08:04:59.31#ibcon#about to read 6, iclass 20, count 0 2006.183.08:04:59.31#ibcon#read 6, iclass 20, count 0 2006.183.08:04:59.31#ibcon#end of sib2, iclass 20, count 0 2006.183.08:04:59.31#ibcon#*after write, iclass 20, count 0 2006.183.08:04:59.31#ibcon#*before return 0, iclass 20, count 0 2006.183.08:04:59.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:04:59.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:04:59.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:04:59.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:04:59.31$vc4f8/va=5,7 2006.183.08:04:59.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.08:04:59.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.08:04:59.31#ibcon#ireg 11 cls_cnt 2 2006.183.08:04:59.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:04:59.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:04:59.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:04:59.37#ibcon#enter wrdev, iclass 22, count 2 2006.183.08:04:59.37#ibcon#first serial, iclass 22, count 2 2006.183.08:04:59.37#ibcon#enter sib2, iclass 22, count 2 2006.183.08:04:59.37#ibcon#flushed, iclass 22, count 2 2006.183.08:04:59.37#ibcon#about to write, iclass 22, count 2 2006.183.08:04:59.37#ibcon#wrote, iclass 22, count 2 2006.183.08:04:59.37#ibcon#about to read 3, iclass 22, count 2 2006.183.08:04:59.39#ibcon#read 3, iclass 22, count 2 2006.183.08:04:59.39#ibcon#about to read 4, iclass 22, count 2 2006.183.08:04:59.39#ibcon#read 4, iclass 22, count 2 2006.183.08:04:59.39#ibcon#about to read 5, iclass 22, count 2 2006.183.08:04:59.39#ibcon#read 5, iclass 22, count 2 2006.183.08:04:59.39#ibcon#about to read 6, iclass 22, count 2 2006.183.08:04:59.39#ibcon#read 6, iclass 22, count 2 2006.183.08:04:59.39#ibcon#end of sib2, iclass 22, count 2 2006.183.08:04:59.39#ibcon#*mode == 0, iclass 22, count 2 2006.183.08:04:59.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.08:04:59.39#ibcon#[25=AT05-07\r\n] 2006.183.08:04:59.39#ibcon#*before write, iclass 22, count 2 2006.183.08:04:59.39#ibcon#enter sib2, iclass 22, count 2 2006.183.08:04:59.39#ibcon#flushed, iclass 22, count 2 2006.183.08:04:59.39#ibcon#about to write, iclass 22, count 2 2006.183.08:04:59.39#ibcon#wrote, iclass 22, count 2 2006.183.08:04:59.39#ibcon#about to read 3, iclass 22, count 2 2006.183.08:04:59.42#ibcon#read 3, iclass 22, count 2 2006.183.08:04:59.42#ibcon#about to read 4, iclass 22, count 2 2006.183.08:04:59.42#ibcon#read 4, iclass 22, count 2 2006.183.08:04:59.42#ibcon#about to read 5, iclass 22, count 2 2006.183.08:04:59.42#ibcon#read 5, iclass 22, count 2 2006.183.08:04:59.42#ibcon#about to read 6, iclass 22, count 2 2006.183.08:04:59.42#ibcon#read 6, iclass 22, count 2 2006.183.08:04:59.42#ibcon#end of sib2, iclass 22, count 2 2006.183.08:04:59.42#ibcon#*after write, iclass 22, count 2 2006.183.08:04:59.42#ibcon#*before return 0, iclass 22, count 2 2006.183.08:04:59.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:04:59.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:04:59.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.08:04:59.42#ibcon#ireg 7 cls_cnt 0 2006.183.08:04:59.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:04:59.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:04:59.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:04:59.54#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:04:59.54#ibcon#first serial, iclass 22, count 0 2006.183.08:04:59.54#ibcon#enter sib2, iclass 22, count 0 2006.183.08:04:59.54#ibcon#flushed, iclass 22, count 0 2006.183.08:04:59.54#ibcon#about to write, iclass 22, count 0 2006.183.08:04:59.54#ibcon#wrote, iclass 22, count 0 2006.183.08:04:59.54#ibcon#about to read 3, iclass 22, count 0 2006.183.08:04:59.56#ibcon#read 3, iclass 22, count 0 2006.183.08:04:59.56#ibcon#about to read 4, iclass 22, count 0 2006.183.08:04:59.56#ibcon#read 4, iclass 22, count 0 2006.183.08:04:59.56#ibcon#about to read 5, iclass 22, count 0 2006.183.08:04:59.56#ibcon#read 5, iclass 22, count 0 2006.183.08:04:59.56#ibcon#about to read 6, iclass 22, count 0 2006.183.08:04:59.56#ibcon#read 6, iclass 22, count 0 2006.183.08:04:59.56#ibcon#end of sib2, iclass 22, count 0 2006.183.08:04:59.56#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:04:59.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:04:59.56#ibcon#[25=USB\r\n] 2006.183.08:04:59.56#ibcon#*before write, iclass 22, count 0 2006.183.08:04:59.56#ibcon#enter sib2, iclass 22, count 0 2006.183.08:04:59.56#ibcon#flushed, iclass 22, count 0 2006.183.08:04:59.56#ibcon#about to write, iclass 22, count 0 2006.183.08:04:59.56#ibcon#wrote, iclass 22, count 0 2006.183.08:04:59.56#ibcon#about to read 3, iclass 22, count 0 2006.183.08:04:59.59#ibcon#read 3, iclass 22, count 0 2006.183.08:04:59.59#ibcon#about to read 4, iclass 22, count 0 2006.183.08:04:59.59#ibcon#read 4, iclass 22, count 0 2006.183.08:04:59.59#ibcon#about to read 5, iclass 22, count 0 2006.183.08:04:59.59#ibcon#read 5, iclass 22, count 0 2006.183.08:04:59.59#ibcon#about to read 6, iclass 22, count 0 2006.183.08:04:59.59#ibcon#read 6, iclass 22, count 0 2006.183.08:04:59.59#ibcon#end of sib2, iclass 22, count 0 2006.183.08:04:59.59#ibcon#*after write, iclass 22, count 0 2006.183.08:04:59.59#ibcon#*before return 0, iclass 22, count 0 2006.183.08:04:59.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:04:59.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:04:59.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:04:59.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:04:59.59$vc4f8/valo=6,772.99 2006.183.08:04:59.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.08:04:59.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.08:04:59.59#ibcon#ireg 17 cls_cnt 0 2006.183.08:04:59.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:04:59.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:04:59.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:04:59.59#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:04:59.59#ibcon#first serial, iclass 24, count 0 2006.183.08:04:59.59#ibcon#enter sib2, iclass 24, count 0 2006.183.08:04:59.59#ibcon#flushed, iclass 24, count 0 2006.183.08:04:59.59#ibcon#about to write, iclass 24, count 0 2006.183.08:04:59.59#ibcon#wrote, iclass 24, count 0 2006.183.08:04:59.59#ibcon#about to read 3, iclass 24, count 0 2006.183.08:04:59.61#ibcon#read 3, iclass 24, count 0 2006.183.08:04:59.61#ibcon#about to read 4, iclass 24, count 0 2006.183.08:04:59.61#ibcon#read 4, iclass 24, count 0 2006.183.08:04:59.61#ibcon#about to read 5, iclass 24, count 0 2006.183.08:04:59.61#ibcon#read 5, iclass 24, count 0 2006.183.08:04:59.61#ibcon#about to read 6, iclass 24, count 0 2006.183.08:04:59.61#ibcon#read 6, iclass 24, count 0 2006.183.08:04:59.61#ibcon#end of sib2, iclass 24, count 0 2006.183.08:04:59.61#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:04:59.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:04:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:04:59.61#ibcon#*before write, iclass 24, count 0 2006.183.08:04:59.61#ibcon#enter sib2, iclass 24, count 0 2006.183.08:04:59.61#ibcon#flushed, iclass 24, count 0 2006.183.08:04:59.61#ibcon#about to write, iclass 24, count 0 2006.183.08:04:59.61#ibcon#wrote, iclass 24, count 0 2006.183.08:04:59.61#ibcon#about to read 3, iclass 24, count 0 2006.183.08:04:59.66#ibcon#read 3, iclass 24, count 0 2006.183.08:04:59.66#ibcon#about to read 4, iclass 24, count 0 2006.183.08:04:59.66#ibcon#read 4, iclass 24, count 0 2006.183.08:04:59.66#ibcon#about to read 5, iclass 24, count 0 2006.183.08:04:59.66#ibcon#read 5, iclass 24, count 0 2006.183.08:04:59.66#ibcon#about to read 6, iclass 24, count 0 2006.183.08:04:59.66#ibcon#read 6, iclass 24, count 0 2006.183.08:04:59.66#ibcon#end of sib2, iclass 24, count 0 2006.183.08:04:59.66#ibcon#*after write, iclass 24, count 0 2006.183.08:04:59.66#ibcon#*before return 0, iclass 24, count 0 2006.183.08:04:59.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:04:59.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:04:59.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:04:59.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:04:59.66$vc4f8/va=6,6 2006.183.08:04:59.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.08:04:59.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.08:04:59.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:04:59.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:04:59.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:04:59.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:04:59.71#ibcon#enter wrdev, iclass 26, count 2 2006.183.08:04:59.71#ibcon#first serial, iclass 26, count 2 2006.183.08:04:59.71#ibcon#enter sib2, iclass 26, count 2 2006.183.08:04:59.71#ibcon#flushed, iclass 26, count 2 2006.183.08:04:59.71#ibcon#about to write, iclass 26, count 2 2006.183.08:04:59.71#ibcon#wrote, iclass 26, count 2 2006.183.08:04:59.71#ibcon#about to read 3, iclass 26, count 2 2006.183.08:04:59.73#ibcon#read 3, iclass 26, count 2 2006.183.08:04:59.73#ibcon#about to read 4, iclass 26, count 2 2006.183.08:04:59.73#ibcon#read 4, iclass 26, count 2 2006.183.08:04:59.73#ibcon#about to read 5, iclass 26, count 2 2006.183.08:04:59.73#ibcon#read 5, iclass 26, count 2 2006.183.08:04:59.73#ibcon#about to read 6, iclass 26, count 2 2006.183.08:04:59.73#ibcon#read 6, iclass 26, count 2 2006.183.08:04:59.73#ibcon#end of sib2, iclass 26, count 2 2006.183.08:04:59.73#ibcon#*mode == 0, iclass 26, count 2 2006.183.08:04:59.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.08:04:59.73#ibcon#[25=AT06-06\r\n] 2006.183.08:04:59.73#ibcon#*before write, iclass 26, count 2 2006.183.08:04:59.73#ibcon#enter sib2, iclass 26, count 2 2006.183.08:04:59.73#ibcon#flushed, iclass 26, count 2 2006.183.08:04:59.73#ibcon#about to write, iclass 26, count 2 2006.183.08:04:59.73#ibcon#wrote, iclass 26, count 2 2006.183.08:04:59.73#ibcon#about to read 3, iclass 26, count 2 2006.183.08:04:59.76#ibcon#read 3, iclass 26, count 2 2006.183.08:04:59.76#ibcon#about to read 4, iclass 26, count 2 2006.183.08:04:59.76#ibcon#read 4, iclass 26, count 2 2006.183.08:04:59.76#ibcon#about to read 5, iclass 26, count 2 2006.183.08:04:59.76#ibcon#read 5, iclass 26, count 2 2006.183.08:04:59.76#ibcon#about to read 6, iclass 26, count 2 2006.183.08:04:59.76#ibcon#read 6, iclass 26, count 2 2006.183.08:04:59.76#ibcon#end of sib2, iclass 26, count 2 2006.183.08:04:59.76#ibcon#*after write, iclass 26, count 2 2006.183.08:04:59.76#ibcon#*before return 0, iclass 26, count 2 2006.183.08:04:59.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:04:59.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:04:59.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.08:04:59.76#ibcon#ireg 7 cls_cnt 0 2006.183.08:04:59.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:04:59.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:04:59.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:04:59.88#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:04:59.88#ibcon#first serial, iclass 26, count 0 2006.183.08:04:59.88#ibcon#enter sib2, iclass 26, count 0 2006.183.08:04:59.88#ibcon#flushed, iclass 26, count 0 2006.183.08:04:59.88#ibcon#about to write, iclass 26, count 0 2006.183.08:04:59.88#ibcon#wrote, iclass 26, count 0 2006.183.08:04:59.88#ibcon#about to read 3, iclass 26, count 0 2006.183.08:04:59.90#ibcon#read 3, iclass 26, count 0 2006.183.08:04:59.90#ibcon#about to read 4, iclass 26, count 0 2006.183.08:04:59.90#ibcon#read 4, iclass 26, count 0 2006.183.08:04:59.90#ibcon#about to read 5, iclass 26, count 0 2006.183.08:04:59.90#ibcon#read 5, iclass 26, count 0 2006.183.08:04:59.90#ibcon#about to read 6, iclass 26, count 0 2006.183.08:04:59.90#ibcon#read 6, iclass 26, count 0 2006.183.08:04:59.90#ibcon#end of sib2, iclass 26, count 0 2006.183.08:04:59.90#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:04:59.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:04:59.90#ibcon#[25=USB\r\n] 2006.183.08:04:59.90#ibcon#*before write, iclass 26, count 0 2006.183.08:04:59.90#ibcon#enter sib2, iclass 26, count 0 2006.183.08:04:59.90#ibcon#flushed, iclass 26, count 0 2006.183.08:04:59.90#ibcon#about to write, iclass 26, count 0 2006.183.08:04:59.90#ibcon#wrote, iclass 26, count 0 2006.183.08:04:59.90#ibcon#about to read 3, iclass 26, count 0 2006.183.08:04:59.93#ibcon#read 3, iclass 26, count 0 2006.183.08:04:59.93#ibcon#about to read 4, iclass 26, count 0 2006.183.08:04:59.93#ibcon#read 4, iclass 26, count 0 2006.183.08:04:59.93#ibcon#about to read 5, iclass 26, count 0 2006.183.08:04:59.93#ibcon#read 5, iclass 26, count 0 2006.183.08:04:59.93#ibcon#about to read 6, iclass 26, count 0 2006.183.08:04:59.93#ibcon#read 6, iclass 26, count 0 2006.183.08:04:59.93#ibcon#end of sib2, iclass 26, count 0 2006.183.08:04:59.93#ibcon#*after write, iclass 26, count 0 2006.183.08:04:59.93#ibcon#*before return 0, iclass 26, count 0 2006.183.08:04:59.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:04:59.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:04:59.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:04:59.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:04:59.93$vc4f8/valo=7,832.99 2006.183.08:04:59.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:04:59.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:04:59.93#ibcon#ireg 17 cls_cnt 0 2006.183.08:04:59.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:04:59.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:04:59.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:04:59.93#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:04:59.93#ibcon#first serial, iclass 28, count 0 2006.183.08:04:59.93#ibcon#enter sib2, iclass 28, count 0 2006.183.08:04:59.93#ibcon#flushed, iclass 28, count 0 2006.183.08:04:59.93#ibcon#about to write, iclass 28, count 0 2006.183.08:04:59.93#ibcon#wrote, iclass 28, count 0 2006.183.08:04:59.93#ibcon#about to read 3, iclass 28, count 0 2006.183.08:04:59.95#ibcon#read 3, iclass 28, count 0 2006.183.08:04:59.95#ibcon#about to read 4, iclass 28, count 0 2006.183.08:04:59.95#ibcon#read 4, iclass 28, count 0 2006.183.08:04:59.95#ibcon#about to read 5, iclass 28, count 0 2006.183.08:04:59.95#ibcon#read 5, iclass 28, count 0 2006.183.08:04:59.95#ibcon#about to read 6, iclass 28, count 0 2006.183.08:04:59.95#ibcon#read 6, iclass 28, count 0 2006.183.08:04:59.95#ibcon#end of sib2, iclass 28, count 0 2006.183.08:04:59.95#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:04:59.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:04:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:04:59.95#ibcon#*before write, iclass 28, count 0 2006.183.08:04:59.95#ibcon#enter sib2, iclass 28, count 0 2006.183.08:04:59.95#ibcon#flushed, iclass 28, count 0 2006.183.08:04:59.95#ibcon#about to write, iclass 28, count 0 2006.183.08:04:59.95#ibcon#wrote, iclass 28, count 0 2006.183.08:04:59.95#ibcon#about to read 3, iclass 28, count 0 2006.183.08:04:59.99#ibcon#read 3, iclass 28, count 0 2006.183.08:04:59.99#ibcon#about to read 4, iclass 28, count 0 2006.183.08:04:59.99#ibcon#read 4, iclass 28, count 0 2006.183.08:04:59.99#ibcon#about to read 5, iclass 28, count 0 2006.183.08:04:59.99#ibcon#read 5, iclass 28, count 0 2006.183.08:04:59.99#ibcon#about to read 6, iclass 28, count 0 2006.183.08:04:59.99#ibcon#read 6, iclass 28, count 0 2006.183.08:04:59.99#ibcon#end of sib2, iclass 28, count 0 2006.183.08:04:59.99#ibcon#*after write, iclass 28, count 0 2006.183.08:04:59.99#ibcon#*before return 0, iclass 28, count 0 2006.183.08:04:59.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:04:59.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:04:59.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:04:59.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:04:59.99$vc4f8/va=7,6 2006.183.08:04:59.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.08:04:59.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.08:04:59.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:04:59.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:05:00.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:05:00.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:05:00.05#ibcon#enter wrdev, iclass 30, count 2 2006.183.08:05:00.05#ibcon#first serial, iclass 30, count 2 2006.183.08:05:00.05#ibcon#enter sib2, iclass 30, count 2 2006.183.08:05:00.05#ibcon#flushed, iclass 30, count 2 2006.183.08:05:00.05#ibcon#about to write, iclass 30, count 2 2006.183.08:05:00.05#ibcon#wrote, iclass 30, count 2 2006.183.08:05:00.05#ibcon#about to read 3, iclass 30, count 2 2006.183.08:05:00.07#ibcon#read 3, iclass 30, count 2 2006.183.08:05:00.07#ibcon#about to read 4, iclass 30, count 2 2006.183.08:05:00.07#ibcon#read 4, iclass 30, count 2 2006.183.08:05:00.07#ibcon#about to read 5, iclass 30, count 2 2006.183.08:05:00.07#ibcon#read 5, iclass 30, count 2 2006.183.08:05:00.07#ibcon#about to read 6, iclass 30, count 2 2006.183.08:05:00.07#ibcon#read 6, iclass 30, count 2 2006.183.08:05:00.07#ibcon#end of sib2, iclass 30, count 2 2006.183.08:05:00.07#ibcon#*mode == 0, iclass 30, count 2 2006.183.08:05:00.07#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.08:05:00.07#ibcon#[25=AT07-06\r\n] 2006.183.08:05:00.07#ibcon#*before write, iclass 30, count 2 2006.183.08:05:00.07#ibcon#enter sib2, iclass 30, count 2 2006.183.08:05:00.07#ibcon#flushed, iclass 30, count 2 2006.183.08:05:00.07#ibcon#about to write, iclass 30, count 2 2006.183.08:05:00.07#ibcon#wrote, iclass 30, count 2 2006.183.08:05:00.07#ibcon#about to read 3, iclass 30, count 2 2006.183.08:05:00.10#ibcon#read 3, iclass 30, count 2 2006.183.08:05:00.10#ibcon#about to read 4, iclass 30, count 2 2006.183.08:05:00.10#ibcon#read 4, iclass 30, count 2 2006.183.08:05:00.10#ibcon#about to read 5, iclass 30, count 2 2006.183.08:05:00.10#ibcon#read 5, iclass 30, count 2 2006.183.08:05:00.10#ibcon#about to read 6, iclass 30, count 2 2006.183.08:05:00.10#ibcon#read 6, iclass 30, count 2 2006.183.08:05:00.10#ibcon#end of sib2, iclass 30, count 2 2006.183.08:05:00.10#ibcon#*after write, iclass 30, count 2 2006.183.08:05:00.10#ibcon#*before return 0, iclass 30, count 2 2006.183.08:05:00.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:05:00.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:05:00.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.08:05:00.10#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:00.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:05:00.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:05:00.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:05:00.22#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:05:00.22#ibcon#first serial, iclass 30, count 0 2006.183.08:05:00.22#ibcon#enter sib2, iclass 30, count 0 2006.183.08:05:00.22#ibcon#flushed, iclass 30, count 0 2006.183.08:05:00.22#ibcon#about to write, iclass 30, count 0 2006.183.08:05:00.22#ibcon#wrote, iclass 30, count 0 2006.183.08:05:00.22#ibcon#about to read 3, iclass 30, count 0 2006.183.08:05:00.24#ibcon#read 3, iclass 30, count 0 2006.183.08:05:00.24#ibcon#about to read 4, iclass 30, count 0 2006.183.08:05:00.24#ibcon#read 4, iclass 30, count 0 2006.183.08:05:00.24#ibcon#about to read 5, iclass 30, count 0 2006.183.08:05:00.24#ibcon#read 5, iclass 30, count 0 2006.183.08:05:00.24#ibcon#about to read 6, iclass 30, count 0 2006.183.08:05:00.24#ibcon#read 6, iclass 30, count 0 2006.183.08:05:00.24#ibcon#end of sib2, iclass 30, count 0 2006.183.08:05:00.24#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:05:00.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:05:00.24#ibcon#[25=USB\r\n] 2006.183.08:05:00.24#ibcon#*before write, iclass 30, count 0 2006.183.08:05:00.24#ibcon#enter sib2, iclass 30, count 0 2006.183.08:05:00.24#ibcon#flushed, iclass 30, count 0 2006.183.08:05:00.24#ibcon#about to write, iclass 30, count 0 2006.183.08:05:00.24#ibcon#wrote, iclass 30, count 0 2006.183.08:05:00.24#ibcon#about to read 3, iclass 30, count 0 2006.183.08:05:00.27#ibcon#read 3, iclass 30, count 0 2006.183.08:05:00.27#ibcon#about to read 4, iclass 30, count 0 2006.183.08:05:00.27#ibcon#read 4, iclass 30, count 0 2006.183.08:05:00.27#ibcon#about to read 5, iclass 30, count 0 2006.183.08:05:00.27#ibcon#read 5, iclass 30, count 0 2006.183.08:05:00.27#ibcon#about to read 6, iclass 30, count 0 2006.183.08:05:00.27#ibcon#read 6, iclass 30, count 0 2006.183.08:05:00.27#ibcon#end of sib2, iclass 30, count 0 2006.183.08:05:00.27#ibcon#*after write, iclass 30, count 0 2006.183.08:05:00.27#ibcon#*before return 0, iclass 30, count 0 2006.183.08:05:00.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:05:00.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:05:00.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:05:00.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:05:00.27$vc4f8/valo=8,852.99 2006.183.08:05:00.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.08:05:00.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.08:05:00.27#ibcon#ireg 17 cls_cnt 0 2006.183.08:05:00.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:05:00.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:05:00.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:05:00.27#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:05:00.27#ibcon#first serial, iclass 32, count 0 2006.183.08:05:00.27#ibcon#enter sib2, iclass 32, count 0 2006.183.08:05:00.27#ibcon#flushed, iclass 32, count 0 2006.183.08:05:00.27#ibcon#about to write, iclass 32, count 0 2006.183.08:05:00.27#ibcon#wrote, iclass 32, count 0 2006.183.08:05:00.27#ibcon#about to read 3, iclass 32, count 0 2006.183.08:05:00.29#ibcon#read 3, iclass 32, count 0 2006.183.08:05:00.29#ibcon#about to read 4, iclass 32, count 0 2006.183.08:05:00.29#ibcon#read 4, iclass 32, count 0 2006.183.08:05:00.29#ibcon#about to read 5, iclass 32, count 0 2006.183.08:05:00.29#ibcon#read 5, iclass 32, count 0 2006.183.08:05:00.29#ibcon#about to read 6, iclass 32, count 0 2006.183.08:05:00.29#ibcon#read 6, iclass 32, count 0 2006.183.08:05:00.29#ibcon#end of sib2, iclass 32, count 0 2006.183.08:05:00.29#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:05:00.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:05:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:05:00.29#ibcon#*before write, iclass 32, count 0 2006.183.08:05:00.29#ibcon#enter sib2, iclass 32, count 0 2006.183.08:05:00.29#ibcon#flushed, iclass 32, count 0 2006.183.08:05:00.29#ibcon#about to write, iclass 32, count 0 2006.183.08:05:00.29#ibcon#wrote, iclass 32, count 0 2006.183.08:05:00.29#ibcon#about to read 3, iclass 32, count 0 2006.183.08:05:00.33#ibcon#read 3, iclass 32, count 0 2006.183.08:05:00.33#ibcon#about to read 4, iclass 32, count 0 2006.183.08:05:00.33#ibcon#read 4, iclass 32, count 0 2006.183.08:05:00.33#ibcon#about to read 5, iclass 32, count 0 2006.183.08:05:00.33#ibcon#read 5, iclass 32, count 0 2006.183.08:05:00.33#ibcon#about to read 6, iclass 32, count 0 2006.183.08:05:00.33#ibcon#read 6, iclass 32, count 0 2006.183.08:05:00.33#ibcon#end of sib2, iclass 32, count 0 2006.183.08:05:00.33#ibcon#*after write, iclass 32, count 0 2006.183.08:05:00.33#ibcon#*before return 0, iclass 32, count 0 2006.183.08:05:00.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:05:00.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:05:00.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:05:00.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:05:00.33$vc4f8/va=8,7 2006.183.08:05:00.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.08:05:00.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.08:05:00.33#ibcon#ireg 11 cls_cnt 2 2006.183.08:05:00.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:05:00.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:05:00.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:05:00.39#ibcon#enter wrdev, iclass 34, count 2 2006.183.08:05:00.39#ibcon#first serial, iclass 34, count 2 2006.183.08:05:00.39#ibcon#enter sib2, iclass 34, count 2 2006.183.08:05:00.39#ibcon#flushed, iclass 34, count 2 2006.183.08:05:00.39#ibcon#about to write, iclass 34, count 2 2006.183.08:05:00.39#ibcon#wrote, iclass 34, count 2 2006.183.08:05:00.39#ibcon#about to read 3, iclass 34, count 2 2006.183.08:05:00.41#ibcon#read 3, iclass 34, count 2 2006.183.08:05:00.41#ibcon#about to read 4, iclass 34, count 2 2006.183.08:05:00.41#ibcon#read 4, iclass 34, count 2 2006.183.08:05:00.41#ibcon#about to read 5, iclass 34, count 2 2006.183.08:05:00.41#ibcon#read 5, iclass 34, count 2 2006.183.08:05:00.41#ibcon#about to read 6, iclass 34, count 2 2006.183.08:05:00.41#ibcon#read 6, iclass 34, count 2 2006.183.08:05:00.41#ibcon#end of sib2, iclass 34, count 2 2006.183.08:05:00.41#ibcon#*mode == 0, iclass 34, count 2 2006.183.08:05:00.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.08:05:00.41#ibcon#[25=AT08-07\r\n] 2006.183.08:05:00.41#ibcon#*before write, iclass 34, count 2 2006.183.08:05:00.41#ibcon#enter sib2, iclass 34, count 2 2006.183.08:05:00.41#ibcon#flushed, iclass 34, count 2 2006.183.08:05:00.41#ibcon#about to write, iclass 34, count 2 2006.183.08:05:00.41#ibcon#wrote, iclass 34, count 2 2006.183.08:05:00.41#ibcon#about to read 3, iclass 34, count 2 2006.183.08:05:00.44#ibcon#read 3, iclass 34, count 2 2006.183.08:05:00.44#ibcon#about to read 4, iclass 34, count 2 2006.183.08:05:00.44#ibcon#read 4, iclass 34, count 2 2006.183.08:05:00.44#ibcon#about to read 5, iclass 34, count 2 2006.183.08:05:00.44#ibcon#read 5, iclass 34, count 2 2006.183.08:05:00.44#ibcon#about to read 6, iclass 34, count 2 2006.183.08:05:00.44#ibcon#read 6, iclass 34, count 2 2006.183.08:05:00.44#ibcon#end of sib2, iclass 34, count 2 2006.183.08:05:00.44#ibcon#*after write, iclass 34, count 2 2006.183.08:05:00.44#ibcon#*before return 0, iclass 34, count 2 2006.183.08:05:00.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:05:00.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:05:00.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.08:05:00.44#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:00.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:05:00.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:05:00.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:05:00.56#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:05:00.56#ibcon#first serial, iclass 34, count 0 2006.183.08:05:00.56#ibcon#enter sib2, iclass 34, count 0 2006.183.08:05:00.56#ibcon#flushed, iclass 34, count 0 2006.183.08:05:00.56#ibcon#about to write, iclass 34, count 0 2006.183.08:05:00.56#ibcon#wrote, iclass 34, count 0 2006.183.08:05:00.56#ibcon#about to read 3, iclass 34, count 0 2006.183.08:05:00.58#ibcon#read 3, iclass 34, count 0 2006.183.08:05:00.58#ibcon#about to read 4, iclass 34, count 0 2006.183.08:05:00.58#ibcon#read 4, iclass 34, count 0 2006.183.08:05:00.58#ibcon#about to read 5, iclass 34, count 0 2006.183.08:05:00.58#ibcon#read 5, iclass 34, count 0 2006.183.08:05:00.58#ibcon#about to read 6, iclass 34, count 0 2006.183.08:05:00.58#ibcon#read 6, iclass 34, count 0 2006.183.08:05:00.58#ibcon#end of sib2, iclass 34, count 0 2006.183.08:05:00.58#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:05:00.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:05:00.58#ibcon#[25=USB\r\n] 2006.183.08:05:00.58#ibcon#*before write, iclass 34, count 0 2006.183.08:05:00.58#ibcon#enter sib2, iclass 34, count 0 2006.183.08:05:00.58#ibcon#flushed, iclass 34, count 0 2006.183.08:05:00.58#ibcon#about to write, iclass 34, count 0 2006.183.08:05:00.58#ibcon#wrote, iclass 34, count 0 2006.183.08:05:00.58#ibcon#about to read 3, iclass 34, count 0 2006.183.08:05:00.61#ibcon#read 3, iclass 34, count 0 2006.183.08:05:00.61#ibcon#about to read 4, iclass 34, count 0 2006.183.08:05:00.61#ibcon#read 4, iclass 34, count 0 2006.183.08:05:00.61#ibcon#about to read 5, iclass 34, count 0 2006.183.08:05:00.61#ibcon#read 5, iclass 34, count 0 2006.183.08:05:00.61#ibcon#about to read 6, iclass 34, count 0 2006.183.08:05:00.61#ibcon#read 6, iclass 34, count 0 2006.183.08:05:00.61#ibcon#end of sib2, iclass 34, count 0 2006.183.08:05:00.61#ibcon#*after write, iclass 34, count 0 2006.183.08:05:00.61#ibcon#*before return 0, iclass 34, count 0 2006.183.08:05:00.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:05:00.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:05:00.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:05:00.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:05:00.61$vc4f8/vblo=1,632.99 2006.183.08:05:00.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.08:05:00.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.08:05:00.61#ibcon#ireg 17 cls_cnt 0 2006.183.08:05:00.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:05:00.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:05:00.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:05:00.61#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:05:00.61#ibcon#first serial, iclass 36, count 0 2006.183.08:05:00.61#ibcon#enter sib2, iclass 36, count 0 2006.183.08:05:00.61#ibcon#flushed, iclass 36, count 0 2006.183.08:05:00.61#ibcon#about to write, iclass 36, count 0 2006.183.08:05:00.61#ibcon#wrote, iclass 36, count 0 2006.183.08:05:00.61#ibcon#about to read 3, iclass 36, count 0 2006.183.08:05:00.63#ibcon#read 3, iclass 36, count 0 2006.183.08:05:00.63#ibcon#about to read 4, iclass 36, count 0 2006.183.08:05:00.63#ibcon#read 4, iclass 36, count 0 2006.183.08:05:00.63#ibcon#about to read 5, iclass 36, count 0 2006.183.08:05:00.63#ibcon#read 5, iclass 36, count 0 2006.183.08:05:00.63#ibcon#about to read 6, iclass 36, count 0 2006.183.08:05:00.63#ibcon#read 6, iclass 36, count 0 2006.183.08:05:00.63#ibcon#end of sib2, iclass 36, count 0 2006.183.08:05:00.63#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:05:00.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:05:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:05:00.63#ibcon#*before write, iclass 36, count 0 2006.183.08:05:00.63#ibcon#enter sib2, iclass 36, count 0 2006.183.08:05:00.63#ibcon#flushed, iclass 36, count 0 2006.183.08:05:00.63#ibcon#about to write, iclass 36, count 0 2006.183.08:05:00.63#ibcon#wrote, iclass 36, count 0 2006.183.08:05:00.63#ibcon#about to read 3, iclass 36, count 0 2006.183.08:05:00.67#ibcon#read 3, iclass 36, count 0 2006.183.08:05:00.67#ibcon#about to read 4, iclass 36, count 0 2006.183.08:05:00.67#ibcon#read 4, iclass 36, count 0 2006.183.08:05:00.67#ibcon#about to read 5, iclass 36, count 0 2006.183.08:05:00.67#ibcon#read 5, iclass 36, count 0 2006.183.08:05:00.67#ibcon#about to read 6, iclass 36, count 0 2006.183.08:05:00.67#ibcon#read 6, iclass 36, count 0 2006.183.08:05:00.67#ibcon#end of sib2, iclass 36, count 0 2006.183.08:05:00.67#ibcon#*after write, iclass 36, count 0 2006.183.08:05:00.67#ibcon#*before return 0, iclass 36, count 0 2006.183.08:05:00.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:05:00.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:05:00.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:05:00.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:05:00.67$vc4f8/vb=1,4 2006.183.08:05:00.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.08:05:00.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.08:05:00.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:05:00.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:05:00.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:05:00.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:05:00.67#ibcon#enter wrdev, iclass 38, count 2 2006.183.08:05:00.67#ibcon#first serial, iclass 38, count 2 2006.183.08:05:00.67#ibcon#enter sib2, iclass 38, count 2 2006.183.08:05:00.67#ibcon#flushed, iclass 38, count 2 2006.183.08:05:00.67#ibcon#about to write, iclass 38, count 2 2006.183.08:05:00.67#ibcon#wrote, iclass 38, count 2 2006.183.08:05:00.67#ibcon#about to read 3, iclass 38, count 2 2006.183.08:05:00.69#ibcon#read 3, iclass 38, count 2 2006.183.08:05:00.69#ibcon#about to read 4, iclass 38, count 2 2006.183.08:05:00.69#ibcon#read 4, iclass 38, count 2 2006.183.08:05:00.69#ibcon#about to read 5, iclass 38, count 2 2006.183.08:05:00.69#ibcon#read 5, iclass 38, count 2 2006.183.08:05:00.69#ibcon#about to read 6, iclass 38, count 2 2006.183.08:05:00.69#ibcon#read 6, iclass 38, count 2 2006.183.08:05:00.69#ibcon#end of sib2, iclass 38, count 2 2006.183.08:05:00.69#ibcon#*mode == 0, iclass 38, count 2 2006.183.08:05:00.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.08:05:00.69#ibcon#[27=AT01-04\r\n] 2006.183.08:05:00.69#ibcon#*before write, iclass 38, count 2 2006.183.08:05:00.69#ibcon#enter sib2, iclass 38, count 2 2006.183.08:05:00.69#ibcon#flushed, iclass 38, count 2 2006.183.08:05:00.69#ibcon#about to write, iclass 38, count 2 2006.183.08:05:00.69#ibcon#wrote, iclass 38, count 2 2006.183.08:05:00.69#ibcon#about to read 3, iclass 38, count 2 2006.183.08:05:00.72#ibcon#read 3, iclass 38, count 2 2006.183.08:05:00.72#ibcon#about to read 4, iclass 38, count 2 2006.183.08:05:00.72#ibcon#read 4, iclass 38, count 2 2006.183.08:05:00.72#ibcon#about to read 5, iclass 38, count 2 2006.183.08:05:00.72#ibcon#read 5, iclass 38, count 2 2006.183.08:05:00.72#ibcon#about to read 6, iclass 38, count 2 2006.183.08:05:00.72#ibcon#read 6, iclass 38, count 2 2006.183.08:05:00.72#ibcon#end of sib2, iclass 38, count 2 2006.183.08:05:00.72#ibcon#*after write, iclass 38, count 2 2006.183.08:05:00.72#ibcon#*before return 0, iclass 38, count 2 2006.183.08:05:00.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:05:00.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:05:00.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.08:05:00.72#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:00.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:05:00.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:05:00.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:05:00.84#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:05:00.84#ibcon#first serial, iclass 38, count 0 2006.183.08:05:00.84#ibcon#enter sib2, iclass 38, count 0 2006.183.08:05:00.84#ibcon#flushed, iclass 38, count 0 2006.183.08:05:00.84#ibcon#about to write, iclass 38, count 0 2006.183.08:05:00.84#ibcon#wrote, iclass 38, count 0 2006.183.08:05:00.84#ibcon#about to read 3, iclass 38, count 0 2006.183.08:05:00.86#ibcon#read 3, iclass 38, count 0 2006.183.08:05:00.86#ibcon#about to read 4, iclass 38, count 0 2006.183.08:05:00.86#ibcon#read 4, iclass 38, count 0 2006.183.08:05:00.86#ibcon#about to read 5, iclass 38, count 0 2006.183.08:05:00.86#ibcon#read 5, iclass 38, count 0 2006.183.08:05:00.86#ibcon#about to read 6, iclass 38, count 0 2006.183.08:05:00.86#ibcon#read 6, iclass 38, count 0 2006.183.08:05:00.86#ibcon#end of sib2, iclass 38, count 0 2006.183.08:05:00.86#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:05:00.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:05:00.86#ibcon#[27=USB\r\n] 2006.183.08:05:00.86#ibcon#*before write, iclass 38, count 0 2006.183.08:05:00.86#ibcon#enter sib2, iclass 38, count 0 2006.183.08:05:00.86#ibcon#flushed, iclass 38, count 0 2006.183.08:05:00.86#ibcon#about to write, iclass 38, count 0 2006.183.08:05:00.86#ibcon#wrote, iclass 38, count 0 2006.183.08:05:00.86#ibcon#about to read 3, iclass 38, count 0 2006.183.08:05:00.89#ibcon#read 3, iclass 38, count 0 2006.183.08:05:00.89#ibcon#about to read 4, iclass 38, count 0 2006.183.08:05:00.89#ibcon#read 4, iclass 38, count 0 2006.183.08:05:00.89#ibcon#about to read 5, iclass 38, count 0 2006.183.08:05:00.89#ibcon#read 5, iclass 38, count 0 2006.183.08:05:00.89#ibcon#about to read 6, iclass 38, count 0 2006.183.08:05:00.89#ibcon#read 6, iclass 38, count 0 2006.183.08:05:00.89#ibcon#end of sib2, iclass 38, count 0 2006.183.08:05:00.89#ibcon#*after write, iclass 38, count 0 2006.183.08:05:00.89#ibcon#*before return 0, iclass 38, count 0 2006.183.08:05:00.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:05:00.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:05:00.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:05:00.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:05:00.89$vc4f8/vblo=2,640.99 2006.183.08:05:00.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.08:05:00.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.08:05:00.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:05:00.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:05:00.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:05:00.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:05:00.89#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:05:00.89#ibcon#first serial, iclass 40, count 0 2006.183.08:05:00.89#ibcon#enter sib2, iclass 40, count 0 2006.183.08:05:00.89#ibcon#flushed, iclass 40, count 0 2006.183.08:05:00.89#ibcon#about to write, iclass 40, count 0 2006.183.08:05:00.89#ibcon#wrote, iclass 40, count 0 2006.183.08:05:00.89#ibcon#about to read 3, iclass 40, count 0 2006.183.08:05:00.91#ibcon#read 3, iclass 40, count 0 2006.183.08:05:00.91#ibcon#about to read 4, iclass 40, count 0 2006.183.08:05:00.91#ibcon#read 4, iclass 40, count 0 2006.183.08:05:00.91#ibcon#about to read 5, iclass 40, count 0 2006.183.08:05:00.91#ibcon#read 5, iclass 40, count 0 2006.183.08:05:00.91#ibcon#about to read 6, iclass 40, count 0 2006.183.08:05:00.91#ibcon#read 6, iclass 40, count 0 2006.183.08:05:00.91#ibcon#end of sib2, iclass 40, count 0 2006.183.08:05:00.91#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:05:00.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:05:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:05:00.91#ibcon#*before write, iclass 40, count 0 2006.183.08:05:00.91#ibcon#enter sib2, iclass 40, count 0 2006.183.08:05:00.91#ibcon#flushed, iclass 40, count 0 2006.183.08:05:00.91#ibcon#about to write, iclass 40, count 0 2006.183.08:05:00.91#ibcon#wrote, iclass 40, count 0 2006.183.08:05:00.91#ibcon#about to read 3, iclass 40, count 0 2006.183.08:05:00.95#ibcon#read 3, iclass 40, count 0 2006.183.08:05:00.95#ibcon#about to read 4, iclass 40, count 0 2006.183.08:05:00.95#ibcon#read 4, iclass 40, count 0 2006.183.08:05:00.95#ibcon#about to read 5, iclass 40, count 0 2006.183.08:05:00.95#ibcon#read 5, iclass 40, count 0 2006.183.08:05:00.95#ibcon#about to read 6, iclass 40, count 0 2006.183.08:05:00.95#ibcon#read 6, iclass 40, count 0 2006.183.08:05:00.95#ibcon#end of sib2, iclass 40, count 0 2006.183.08:05:00.95#ibcon#*after write, iclass 40, count 0 2006.183.08:05:00.95#ibcon#*before return 0, iclass 40, count 0 2006.183.08:05:00.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:05:00.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:05:00.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:05:00.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:05:00.95$vc4f8/vb=2,4 2006.183.08:05:00.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.08:05:00.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.08:05:00.95#ibcon#ireg 11 cls_cnt 2 2006.183.08:05:00.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:05:01.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:05:01.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:05:01.01#ibcon#enter wrdev, iclass 4, count 2 2006.183.08:05:01.01#ibcon#first serial, iclass 4, count 2 2006.183.08:05:01.01#ibcon#enter sib2, iclass 4, count 2 2006.183.08:05:01.01#ibcon#flushed, iclass 4, count 2 2006.183.08:05:01.01#ibcon#about to write, iclass 4, count 2 2006.183.08:05:01.01#ibcon#wrote, iclass 4, count 2 2006.183.08:05:01.01#ibcon#about to read 3, iclass 4, count 2 2006.183.08:05:01.03#ibcon#read 3, iclass 4, count 2 2006.183.08:05:01.03#ibcon#about to read 4, iclass 4, count 2 2006.183.08:05:01.03#ibcon#read 4, iclass 4, count 2 2006.183.08:05:01.03#ibcon#about to read 5, iclass 4, count 2 2006.183.08:05:01.03#ibcon#read 5, iclass 4, count 2 2006.183.08:05:01.03#ibcon#about to read 6, iclass 4, count 2 2006.183.08:05:01.03#ibcon#read 6, iclass 4, count 2 2006.183.08:05:01.03#ibcon#end of sib2, iclass 4, count 2 2006.183.08:05:01.03#ibcon#*mode == 0, iclass 4, count 2 2006.183.08:05:01.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.08:05:01.03#ibcon#[27=AT02-04\r\n] 2006.183.08:05:01.03#ibcon#*before write, iclass 4, count 2 2006.183.08:05:01.03#ibcon#enter sib2, iclass 4, count 2 2006.183.08:05:01.03#ibcon#flushed, iclass 4, count 2 2006.183.08:05:01.03#ibcon#about to write, iclass 4, count 2 2006.183.08:05:01.03#ibcon#wrote, iclass 4, count 2 2006.183.08:05:01.03#ibcon#about to read 3, iclass 4, count 2 2006.183.08:05:01.06#ibcon#read 3, iclass 4, count 2 2006.183.08:05:01.06#ibcon#about to read 4, iclass 4, count 2 2006.183.08:05:01.06#ibcon#read 4, iclass 4, count 2 2006.183.08:05:01.06#ibcon#about to read 5, iclass 4, count 2 2006.183.08:05:01.06#ibcon#read 5, iclass 4, count 2 2006.183.08:05:01.06#ibcon#about to read 6, iclass 4, count 2 2006.183.08:05:01.06#ibcon#read 6, iclass 4, count 2 2006.183.08:05:01.06#ibcon#end of sib2, iclass 4, count 2 2006.183.08:05:01.06#ibcon#*after write, iclass 4, count 2 2006.183.08:05:01.06#ibcon#*before return 0, iclass 4, count 2 2006.183.08:05:01.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:05:01.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:05:01.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.08:05:01.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:01.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:05:01.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:05:01.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:05:01.18#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:05:01.18#ibcon#first serial, iclass 4, count 0 2006.183.08:05:01.18#ibcon#enter sib2, iclass 4, count 0 2006.183.08:05:01.18#ibcon#flushed, iclass 4, count 0 2006.183.08:05:01.18#ibcon#about to write, iclass 4, count 0 2006.183.08:05:01.18#ibcon#wrote, iclass 4, count 0 2006.183.08:05:01.18#ibcon#about to read 3, iclass 4, count 0 2006.183.08:05:01.21#ibcon#read 3, iclass 4, count 0 2006.183.08:05:01.21#ibcon#about to read 4, iclass 4, count 0 2006.183.08:05:01.21#ibcon#read 4, iclass 4, count 0 2006.183.08:05:01.21#ibcon#about to read 5, iclass 4, count 0 2006.183.08:05:01.21#ibcon#read 5, iclass 4, count 0 2006.183.08:05:01.21#ibcon#about to read 6, iclass 4, count 0 2006.183.08:05:01.21#ibcon#read 6, iclass 4, count 0 2006.183.08:05:01.21#ibcon#end of sib2, iclass 4, count 0 2006.183.08:05:01.21#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:05:01.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:05:01.21#ibcon#[27=USB\r\n] 2006.183.08:05:01.21#ibcon#*before write, iclass 4, count 0 2006.183.08:05:01.21#ibcon#enter sib2, iclass 4, count 0 2006.183.08:05:01.21#ibcon#flushed, iclass 4, count 0 2006.183.08:05:01.21#ibcon#about to write, iclass 4, count 0 2006.183.08:05:01.21#ibcon#wrote, iclass 4, count 0 2006.183.08:05:01.21#ibcon#about to read 3, iclass 4, count 0 2006.183.08:05:01.24#ibcon#read 3, iclass 4, count 0 2006.183.08:05:01.24#ibcon#about to read 4, iclass 4, count 0 2006.183.08:05:01.24#ibcon#read 4, iclass 4, count 0 2006.183.08:05:01.24#ibcon#about to read 5, iclass 4, count 0 2006.183.08:05:01.24#ibcon#read 5, iclass 4, count 0 2006.183.08:05:01.24#ibcon#about to read 6, iclass 4, count 0 2006.183.08:05:01.24#ibcon#read 6, iclass 4, count 0 2006.183.08:05:01.24#ibcon#end of sib2, iclass 4, count 0 2006.183.08:05:01.24#ibcon#*after write, iclass 4, count 0 2006.183.08:05:01.24#ibcon#*before return 0, iclass 4, count 0 2006.183.08:05:01.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:05:01.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:05:01.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:05:01.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:05:01.24$vc4f8/vblo=3,656.99 2006.183.08:05:01.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.08:05:01.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.08:05:01.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:05:01.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:05:01.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:05:01.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:05:01.24#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:05:01.24#ibcon#first serial, iclass 6, count 0 2006.183.08:05:01.24#ibcon#enter sib2, iclass 6, count 0 2006.183.08:05:01.24#ibcon#flushed, iclass 6, count 0 2006.183.08:05:01.24#ibcon#about to write, iclass 6, count 0 2006.183.08:05:01.24#ibcon#wrote, iclass 6, count 0 2006.183.08:05:01.24#ibcon#about to read 3, iclass 6, count 0 2006.183.08:05:01.26#ibcon#read 3, iclass 6, count 0 2006.183.08:05:01.26#ibcon#about to read 4, iclass 6, count 0 2006.183.08:05:01.26#ibcon#read 4, iclass 6, count 0 2006.183.08:05:01.26#ibcon#about to read 5, iclass 6, count 0 2006.183.08:05:01.26#ibcon#read 5, iclass 6, count 0 2006.183.08:05:01.26#ibcon#about to read 6, iclass 6, count 0 2006.183.08:05:01.26#ibcon#read 6, iclass 6, count 0 2006.183.08:05:01.26#ibcon#end of sib2, iclass 6, count 0 2006.183.08:05:01.26#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:05:01.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:05:01.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:05:01.26#ibcon#*before write, iclass 6, count 0 2006.183.08:05:01.26#ibcon#enter sib2, iclass 6, count 0 2006.183.08:05:01.26#ibcon#flushed, iclass 6, count 0 2006.183.08:05:01.26#ibcon#about to write, iclass 6, count 0 2006.183.08:05:01.26#ibcon#wrote, iclass 6, count 0 2006.183.08:05:01.26#ibcon#about to read 3, iclass 6, count 0 2006.183.08:05:01.30#ibcon#read 3, iclass 6, count 0 2006.183.08:05:01.30#ibcon#about to read 4, iclass 6, count 0 2006.183.08:05:01.30#ibcon#read 4, iclass 6, count 0 2006.183.08:05:01.30#ibcon#about to read 5, iclass 6, count 0 2006.183.08:05:01.30#ibcon#read 5, iclass 6, count 0 2006.183.08:05:01.30#ibcon#about to read 6, iclass 6, count 0 2006.183.08:05:01.30#ibcon#read 6, iclass 6, count 0 2006.183.08:05:01.30#ibcon#end of sib2, iclass 6, count 0 2006.183.08:05:01.30#ibcon#*after write, iclass 6, count 0 2006.183.08:05:01.30#ibcon#*before return 0, iclass 6, count 0 2006.183.08:05:01.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:05:01.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:05:01.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:05:01.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:05:01.30$vc4f8/vb=3,4 2006.183.08:05:01.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.08:05:01.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.08:05:01.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:05:01.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:05:01.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:05:01.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:05:01.36#ibcon#enter wrdev, iclass 10, count 2 2006.183.08:05:01.36#ibcon#first serial, iclass 10, count 2 2006.183.08:05:01.36#ibcon#enter sib2, iclass 10, count 2 2006.183.08:05:01.36#ibcon#flushed, iclass 10, count 2 2006.183.08:05:01.36#ibcon#about to write, iclass 10, count 2 2006.183.08:05:01.36#ibcon#wrote, iclass 10, count 2 2006.183.08:05:01.36#ibcon#about to read 3, iclass 10, count 2 2006.183.08:05:01.38#ibcon#read 3, iclass 10, count 2 2006.183.08:05:01.38#ibcon#about to read 4, iclass 10, count 2 2006.183.08:05:01.38#ibcon#read 4, iclass 10, count 2 2006.183.08:05:01.38#ibcon#about to read 5, iclass 10, count 2 2006.183.08:05:01.38#ibcon#read 5, iclass 10, count 2 2006.183.08:05:01.38#ibcon#about to read 6, iclass 10, count 2 2006.183.08:05:01.38#ibcon#read 6, iclass 10, count 2 2006.183.08:05:01.38#ibcon#end of sib2, iclass 10, count 2 2006.183.08:05:01.38#ibcon#*mode == 0, iclass 10, count 2 2006.183.08:05:01.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.08:05:01.38#ibcon#[27=AT03-04\r\n] 2006.183.08:05:01.38#ibcon#*before write, iclass 10, count 2 2006.183.08:05:01.38#ibcon#enter sib2, iclass 10, count 2 2006.183.08:05:01.38#ibcon#flushed, iclass 10, count 2 2006.183.08:05:01.38#ibcon#about to write, iclass 10, count 2 2006.183.08:05:01.38#ibcon#wrote, iclass 10, count 2 2006.183.08:05:01.38#ibcon#about to read 3, iclass 10, count 2 2006.183.08:05:01.41#ibcon#read 3, iclass 10, count 2 2006.183.08:05:01.41#ibcon#about to read 4, iclass 10, count 2 2006.183.08:05:01.41#ibcon#read 4, iclass 10, count 2 2006.183.08:05:01.41#ibcon#about to read 5, iclass 10, count 2 2006.183.08:05:01.41#ibcon#read 5, iclass 10, count 2 2006.183.08:05:01.41#ibcon#about to read 6, iclass 10, count 2 2006.183.08:05:01.41#ibcon#read 6, iclass 10, count 2 2006.183.08:05:01.41#ibcon#end of sib2, iclass 10, count 2 2006.183.08:05:01.41#ibcon#*after write, iclass 10, count 2 2006.183.08:05:01.41#ibcon#*before return 0, iclass 10, count 2 2006.183.08:05:01.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:05:01.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:05:01.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.08:05:01.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:01.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:05:01.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:05:01.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:05:01.53#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:05:01.53#ibcon#first serial, iclass 10, count 0 2006.183.08:05:01.53#ibcon#enter sib2, iclass 10, count 0 2006.183.08:05:01.53#ibcon#flushed, iclass 10, count 0 2006.183.08:05:01.53#ibcon#about to write, iclass 10, count 0 2006.183.08:05:01.53#ibcon#wrote, iclass 10, count 0 2006.183.08:05:01.53#ibcon#about to read 3, iclass 10, count 0 2006.183.08:05:01.55#ibcon#read 3, iclass 10, count 0 2006.183.08:05:01.55#ibcon#about to read 4, iclass 10, count 0 2006.183.08:05:01.55#ibcon#read 4, iclass 10, count 0 2006.183.08:05:01.55#ibcon#about to read 5, iclass 10, count 0 2006.183.08:05:01.55#ibcon#read 5, iclass 10, count 0 2006.183.08:05:01.55#ibcon#about to read 6, iclass 10, count 0 2006.183.08:05:01.55#ibcon#read 6, iclass 10, count 0 2006.183.08:05:01.55#ibcon#end of sib2, iclass 10, count 0 2006.183.08:05:01.55#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:05:01.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:05:01.55#ibcon#[27=USB\r\n] 2006.183.08:05:01.55#ibcon#*before write, iclass 10, count 0 2006.183.08:05:01.55#ibcon#enter sib2, iclass 10, count 0 2006.183.08:05:01.55#ibcon#flushed, iclass 10, count 0 2006.183.08:05:01.55#ibcon#about to write, iclass 10, count 0 2006.183.08:05:01.55#ibcon#wrote, iclass 10, count 0 2006.183.08:05:01.55#ibcon#about to read 3, iclass 10, count 0 2006.183.08:05:01.58#ibcon#read 3, iclass 10, count 0 2006.183.08:05:01.58#ibcon#about to read 4, iclass 10, count 0 2006.183.08:05:01.58#ibcon#read 4, iclass 10, count 0 2006.183.08:05:01.58#ibcon#about to read 5, iclass 10, count 0 2006.183.08:05:01.58#ibcon#read 5, iclass 10, count 0 2006.183.08:05:01.58#ibcon#about to read 6, iclass 10, count 0 2006.183.08:05:01.58#ibcon#read 6, iclass 10, count 0 2006.183.08:05:01.58#ibcon#end of sib2, iclass 10, count 0 2006.183.08:05:01.58#ibcon#*after write, iclass 10, count 0 2006.183.08:05:01.58#ibcon#*before return 0, iclass 10, count 0 2006.183.08:05:01.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:05:01.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:05:01.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:05:01.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:05:01.58$vc4f8/vblo=4,712.99 2006.183.08:05:01.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.08:05:01.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.08:05:01.58#ibcon#ireg 17 cls_cnt 0 2006.183.08:05:01.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:05:01.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:05:01.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:05:01.58#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:05:01.58#ibcon#first serial, iclass 12, count 0 2006.183.08:05:01.58#ibcon#enter sib2, iclass 12, count 0 2006.183.08:05:01.58#ibcon#flushed, iclass 12, count 0 2006.183.08:05:01.58#ibcon#about to write, iclass 12, count 0 2006.183.08:05:01.58#ibcon#wrote, iclass 12, count 0 2006.183.08:05:01.58#ibcon#about to read 3, iclass 12, count 0 2006.183.08:05:01.60#ibcon#read 3, iclass 12, count 0 2006.183.08:05:01.60#ibcon#about to read 4, iclass 12, count 0 2006.183.08:05:01.60#ibcon#read 4, iclass 12, count 0 2006.183.08:05:01.60#ibcon#about to read 5, iclass 12, count 0 2006.183.08:05:01.60#ibcon#read 5, iclass 12, count 0 2006.183.08:05:01.60#ibcon#about to read 6, iclass 12, count 0 2006.183.08:05:01.60#ibcon#read 6, iclass 12, count 0 2006.183.08:05:01.60#ibcon#end of sib2, iclass 12, count 0 2006.183.08:05:01.60#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:05:01.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:05:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:05:01.60#ibcon#*before write, iclass 12, count 0 2006.183.08:05:01.60#ibcon#enter sib2, iclass 12, count 0 2006.183.08:05:01.60#ibcon#flushed, iclass 12, count 0 2006.183.08:05:01.60#ibcon#about to write, iclass 12, count 0 2006.183.08:05:01.60#ibcon#wrote, iclass 12, count 0 2006.183.08:05:01.60#ibcon#about to read 3, iclass 12, count 0 2006.183.08:05:01.64#ibcon#read 3, iclass 12, count 0 2006.183.08:05:01.64#ibcon#about to read 4, iclass 12, count 0 2006.183.08:05:01.64#ibcon#read 4, iclass 12, count 0 2006.183.08:05:01.64#ibcon#about to read 5, iclass 12, count 0 2006.183.08:05:01.64#ibcon#read 5, iclass 12, count 0 2006.183.08:05:01.64#ibcon#about to read 6, iclass 12, count 0 2006.183.08:05:01.64#ibcon#read 6, iclass 12, count 0 2006.183.08:05:01.64#ibcon#end of sib2, iclass 12, count 0 2006.183.08:05:01.64#ibcon#*after write, iclass 12, count 0 2006.183.08:05:01.64#ibcon#*before return 0, iclass 12, count 0 2006.183.08:05:01.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:05:01.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:05:01.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:05:01.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:05:01.64$vc4f8/vb=4,4 2006.183.08:05:01.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.08:05:01.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.08:05:01.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:05:01.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:05:01.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:05:01.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:05:01.70#ibcon#enter wrdev, iclass 14, count 2 2006.183.08:05:01.70#ibcon#first serial, iclass 14, count 2 2006.183.08:05:01.70#ibcon#enter sib2, iclass 14, count 2 2006.183.08:05:01.70#ibcon#flushed, iclass 14, count 2 2006.183.08:05:01.70#ibcon#about to write, iclass 14, count 2 2006.183.08:05:01.70#ibcon#wrote, iclass 14, count 2 2006.183.08:05:01.70#ibcon#about to read 3, iclass 14, count 2 2006.183.08:05:01.72#ibcon#read 3, iclass 14, count 2 2006.183.08:05:01.72#ibcon#about to read 4, iclass 14, count 2 2006.183.08:05:01.72#ibcon#read 4, iclass 14, count 2 2006.183.08:05:01.72#ibcon#about to read 5, iclass 14, count 2 2006.183.08:05:01.72#ibcon#read 5, iclass 14, count 2 2006.183.08:05:01.72#ibcon#about to read 6, iclass 14, count 2 2006.183.08:05:01.72#ibcon#read 6, iclass 14, count 2 2006.183.08:05:01.72#ibcon#end of sib2, iclass 14, count 2 2006.183.08:05:01.72#ibcon#*mode == 0, iclass 14, count 2 2006.183.08:05:01.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.08:05:01.72#ibcon#[27=AT04-04\r\n] 2006.183.08:05:01.72#ibcon#*before write, iclass 14, count 2 2006.183.08:05:01.72#ibcon#enter sib2, iclass 14, count 2 2006.183.08:05:01.72#ibcon#flushed, iclass 14, count 2 2006.183.08:05:01.72#ibcon#about to write, iclass 14, count 2 2006.183.08:05:01.72#ibcon#wrote, iclass 14, count 2 2006.183.08:05:01.72#ibcon#about to read 3, iclass 14, count 2 2006.183.08:05:01.75#ibcon#read 3, iclass 14, count 2 2006.183.08:05:01.75#ibcon#about to read 4, iclass 14, count 2 2006.183.08:05:01.75#ibcon#read 4, iclass 14, count 2 2006.183.08:05:01.75#ibcon#about to read 5, iclass 14, count 2 2006.183.08:05:01.75#ibcon#read 5, iclass 14, count 2 2006.183.08:05:01.75#ibcon#about to read 6, iclass 14, count 2 2006.183.08:05:01.75#ibcon#read 6, iclass 14, count 2 2006.183.08:05:01.75#ibcon#end of sib2, iclass 14, count 2 2006.183.08:05:01.75#ibcon#*after write, iclass 14, count 2 2006.183.08:05:01.75#ibcon#*before return 0, iclass 14, count 2 2006.183.08:05:01.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:05:01.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:05:01.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.08:05:01.75#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:01.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:05:01.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:05:01.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:05:01.87#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:05:01.87#ibcon#first serial, iclass 14, count 0 2006.183.08:05:01.87#ibcon#enter sib2, iclass 14, count 0 2006.183.08:05:01.87#ibcon#flushed, iclass 14, count 0 2006.183.08:05:01.87#ibcon#about to write, iclass 14, count 0 2006.183.08:05:01.87#ibcon#wrote, iclass 14, count 0 2006.183.08:05:01.87#ibcon#about to read 3, iclass 14, count 0 2006.183.08:05:01.89#ibcon#read 3, iclass 14, count 0 2006.183.08:05:01.89#ibcon#about to read 4, iclass 14, count 0 2006.183.08:05:01.89#ibcon#read 4, iclass 14, count 0 2006.183.08:05:01.89#ibcon#about to read 5, iclass 14, count 0 2006.183.08:05:01.89#ibcon#read 5, iclass 14, count 0 2006.183.08:05:01.89#ibcon#about to read 6, iclass 14, count 0 2006.183.08:05:01.89#ibcon#read 6, iclass 14, count 0 2006.183.08:05:01.89#ibcon#end of sib2, iclass 14, count 0 2006.183.08:05:01.89#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:05:01.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:05:01.89#ibcon#[27=USB\r\n] 2006.183.08:05:01.89#ibcon#*before write, iclass 14, count 0 2006.183.08:05:01.89#ibcon#enter sib2, iclass 14, count 0 2006.183.08:05:01.89#ibcon#flushed, iclass 14, count 0 2006.183.08:05:01.89#ibcon#about to write, iclass 14, count 0 2006.183.08:05:01.89#ibcon#wrote, iclass 14, count 0 2006.183.08:05:01.89#ibcon#about to read 3, iclass 14, count 0 2006.183.08:05:01.92#ibcon#read 3, iclass 14, count 0 2006.183.08:05:01.92#ibcon#about to read 4, iclass 14, count 0 2006.183.08:05:01.92#ibcon#read 4, iclass 14, count 0 2006.183.08:05:01.92#ibcon#about to read 5, iclass 14, count 0 2006.183.08:05:01.92#ibcon#read 5, iclass 14, count 0 2006.183.08:05:01.92#ibcon#about to read 6, iclass 14, count 0 2006.183.08:05:01.92#ibcon#read 6, iclass 14, count 0 2006.183.08:05:01.92#ibcon#end of sib2, iclass 14, count 0 2006.183.08:05:01.92#ibcon#*after write, iclass 14, count 0 2006.183.08:05:01.92#ibcon#*before return 0, iclass 14, count 0 2006.183.08:05:01.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:05:01.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:05:01.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:05:01.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:05:01.92$vc4f8/vblo=5,744.99 2006.183.08:05:01.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.08:05:01.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.08:05:01.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:05:01.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:05:01.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:05:01.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:05:01.92#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:05:01.92#ibcon#first serial, iclass 16, count 0 2006.183.08:05:01.92#ibcon#enter sib2, iclass 16, count 0 2006.183.08:05:01.92#ibcon#flushed, iclass 16, count 0 2006.183.08:05:01.92#ibcon#about to write, iclass 16, count 0 2006.183.08:05:01.92#ibcon#wrote, iclass 16, count 0 2006.183.08:05:01.92#ibcon#about to read 3, iclass 16, count 0 2006.183.08:05:01.94#ibcon#read 3, iclass 16, count 0 2006.183.08:05:01.94#ibcon#about to read 4, iclass 16, count 0 2006.183.08:05:01.94#ibcon#read 4, iclass 16, count 0 2006.183.08:05:01.94#ibcon#about to read 5, iclass 16, count 0 2006.183.08:05:01.94#ibcon#read 5, iclass 16, count 0 2006.183.08:05:01.94#ibcon#about to read 6, iclass 16, count 0 2006.183.08:05:01.94#ibcon#read 6, iclass 16, count 0 2006.183.08:05:01.94#ibcon#end of sib2, iclass 16, count 0 2006.183.08:05:01.94#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:05:01.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:05:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:05:01.94#ibcon#*before write, iclass 16, count 0 2006.183.08:05:01.94#ibcon#enter sib2, iclass 16, count 0 2006.183.08:05:01.94#ibcon#flushed, iclass 16, count 0 2006.183.08:05:01.94#ibcon#about to write, iclass 16, count 0 2006.183.08:05:01.94#ibcon#wrote, iclass 16, count 0 2006.183.08:05:01.94#ibcon#about to read 3, iclass 16, count 0 2006.183.08:05:01.99#ibcon#read 3, iclass 16, count 0 2006.183.08:05:01.99#ibcon#about to read 4, iclass 16, count 0 2006.183.08:05:01.99#ibcon#read 4, iclass 16, count 0 2006.183.08:05:01.99#ibcon#about to read 5, iclass 16, count 0 2006.183.08:05:01.99#ibcon#read 5, iclass 16, count 0 2006.183.08:05:01.99#ibcon#about to read 6, iclass 16, count 0 2006.183.08:05:01.99#ibcon#read 6, iclass 16, count 0 2006.183.08:05:01.99#ibcon#end of sib2, iclass 16, count 0 2006.183.08:05:01.99#ibcon#*after write, iclass 16, count 0 2006.183.08:05:01.99#ibcon#*before return 0, iclass 16, count 0 2006.183.08:05:01.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:05:01.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:05:01.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:05:01.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:05:01.99$vc4f8/vb=5,4 2006.183.08:05:01.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.08:05:01.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.08:05:01.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:05:01.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:05:02.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:05:02.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:05:02.04#ibcon#enter wrdev, iclass 18, count 2 2006.183.08:05:02.04#ibcon#first serial, iclass 18, count 2 2006.183.08:05:02.04#ibcon#enter sib2, iclass 18, count 2 2006.183.08:05:02.04#ibcon#flushed, iclass 18, count 2 2006.183.08:05:02.04#ibcon#about to write, iclass 18, count 2 2006.183.08:05:02.04#ibcon#wrote, iclass 18, count 2 2006.183.08:05:02.04#ibcon#about to read 3, iclass 18, count 2 2006.183.08:05:02.06#ibcon#read 3, iclass 18, count 2 2006.183.08:05:02.06#ibcon#about to read 4, iclass 18, count 2 2006.183.08:05:02.06#ibcon#read 4, iclass 18, count 2 2006.183.08:05:02.06#ibcon#about to read 5, iclass 18, count 2 2006.183.08:05:02.06#ibcon#read 5, iclass 18, count 2 2006.183.08:05:02.06#ibcon#about to read 6, iclass 18, count 2 2006.183.08:05:02.06#ibcon#read 6, iclass 18, count 2 2006.183.08:05:02.06#ibcon#end of sib2, iclass 18, count 2 2006.183.08:05:02.06#ibcon#*mode == 0, iclass 18, count 2 2006.183.08:05:02.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.08:05:02.06#ibcon#[27=AT05-04\r\n] 2006.183.08:05:02.06#ibcon#*before write, iclass 18, count 2 2006.183.08:05:02.06#ibcon#enter sib2, iclass 18, count 2 2006.183.08:05:02.06#ibcon#flushed, iclass 18, count 2 2006.183.08:05:02.06#ibcon#about to write, iclass 18, count 2 2006.183.08:05:02.06#ibcon#wrote, iclass 18, count 2 2006.183.08:05:02.06#ibcon#about to read 3, iclass 18, count 2 2006.183.08:05:02.09#ibcon#read 3, iclass 18, count 2 2006.183.08:05:02.09#ibcon#about to read 4, iclass 18, count 2 2006.183.08:05:02.09#ibcon#read 4, iclass 18, count 2 2006.183.08:05:02.09#ibcon#about to read 5, iclass 18, count 2 2006.183.08:05:02.09#ibcon#read 5, iclass 18, count 2 2006.183.08:05:02.09#ibcon#about to read 6, iclass 18, count 2 2006.183.08:05:02.09#ibcon#read 6, iclass 18, count 2 2006.183.08:05:02.09#ibcon#end of sib2, iclass 18, count 2 2006.183.08:05:02.09#ibcon#*after write, iclass 18, count 2 2006.183.08:05:02.09#ibcon#*before return 0, iclass 18, count 2 2006.183.08:05:02.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:05:02.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:05:02.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.08:05:02.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:02.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:05:02.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:05:02.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:05:02.21#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:05:02.21#ibcon#first serial, iclass 18, count 0 2006.183.08:05:02.21#ibcon#enter sib2, iclass 18, count 0 2006.183.08:05:02.21#ibcon#flushed, iclass 18, count 0 2006.183.08:05:02.21#ibcon#about to write, iclass 18, count 0 2006.183.08:05:02.21#ibcon#wrote, iclass 18, count 0 2006.183.08:05:02.21#ibcon#about to read 3, iclass 18, count 0 2006.183.08:05:02.23#ibcon#read 3, iclass 18, count 0 2006.183.08:05:02.23#ibcon#about to read 4, iclass 18, count 0 2006.183.08:05:02.23#ibcon#read 4, iclass 18, count 0 2006.183.08:05:02.23#ibcon#about to read 5, iclass 18, count 0 2006.183.08:05:02.23#ibcon#read 5, iclass 18, count 0 2006.183.08:05:02.23#ibcon#about to read 6, iclass 18, count 0 2006.183.08:05:02.23#ibcon#read 6, iclass 18, count 0 2006.183.08:05:02.23#ibcon#end of sib2, iclass 18, count 0 2006.183.08:05:02.23#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:05:02.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:05:02.23#ibcon#[27=USB\r\n] 2006.183.08:05:02.23#ibcon#*before write, iclass 18, count 0 2006.183.08:05:02.23#ibcon#enter sib2, iclass 18, count 0 2006.183.08:05:02.23#ibcon#flushed, iclass 18, count 0 2006.183.08:05:02.23#ibcon#about to write, iclass 18, count 0 2006.183.08:05:02.23#ibcon#wrote, iclass 18, count 0 2006.183.08:05:02.23#ibcon#about to read 3, iclass 18, count 0 2006.183.08:05:02.26#ibcon#read 3, iclass 18, count 0 2006.183.08:05:02.26#ibcon#about to read 4, iclass 18, count 0 2006.183.08:05:02.26#ibcon#read 4, iclass 18, count 0 2006.183.08:05:02.26#ibcon#about to read 5, iclass 18, count 0 2006.183.08:05:02.26#ibcon#read 5, iclass 18, count 0 2006.183.08:05:02.26#ibcon#about to read 6, iclass 18, count 0 2006.183.08:05:02.26#ibcon#read 6, iclass 18, count 0 2006.183.08:05:02.26#ibcon#end of sib2, iclass 18, count 0 2006.183.08:05:02.26#ibcon#*after write, iclass 18, count 0 2006.183.08:05:02.26#ibcon#*before return 0, iclass 18, count 0 2006.183.08:05:02.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:05:02.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:05:02.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:05:02.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:05:02.26$vc4f8/vblo=6,752.99 2006.183.08:05:02.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.08:05:02.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.08:05:02.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:05:02.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:05:02.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:05:02.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:05:02.26#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:05:02.26#ibcon#first serial, iclass 20, count 0 2006.183.08:05:02.26#ibcon#enter sib2, iclass 20, count 0 2006.183.08:05:02.26#ibcon#flushed, iclass 20, count 0 2006.183.08:05:02.26#ibcon#about to write, iclass 20, count 0 2006.183.08:05:02.26#ibcon#wrote, iclass 20, count 0 2006.183.08:05:02.26#ibcon#about to read 3, iclass 20, count 0 2006.183.08:05:02.28#ibcon#read 3, iclass 20, count 0 2006.183.08:05:02.28#ibcon#about to read 4, iclass 20, count 0 2006.183.08:05:02.28#ibcon#read 4, iclass 20, count 0 2006.183.08:05:02.28#ibcon#about to read 5, iclass 20, count 0 2006.183.08:05:02.28#ibcon#read 5, iclass 20, count 0 2006.183.08:05:02.28#ibcon#about to read 6, iclass 20, count 0 2006.183.08:05:02.28#ibcon#read 6, iclass 20, count 0 2006.183.08:05:02.28#ibcon#end of sib2, iclass 20, count 0 2006.183.08:05:02.28#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:05:02.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:05:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:05:02.28#ibcon#*before write, iclass 20, count 0 2006.183.08:05:02.28#ibcon#enter sib2, iclass 20, count 0 2006.183.08:05:02.28#ibcon#flushed, iclass 20, count 0 2006.183.08:05:02.28#ibcon#about to write, iclass 20, count 0 2006.183.08:05:02.28#ibcon#wrote, iclass 20, count 0 2006.183.08:05:02.28#ibcon#about to read 3, iclass 20, count 0 2006.183.08:05:02.32#ibcon#read 3, iclass 20, count 0 2006.183.08:05:02.32#ibcon#about to read 4, iclass 20, count 0 2006.183.08:05:02.32#ibcon#read 4, iclass 20, count 0 2006.183.08:05:02.32#ibcon#about to read 5, iclass 20, count 0 2006.183.08:05:02.32#ibcon#read 5, iclass 20, count 0 2006.183.08:05:02.32#ibcon#about to read 6, iclass 20, count 0 2006.183.08:05:02.32#ibcon#read 6, iclass 20, count 0 2006.183.08:05:02.32#ibcon#end of sib2, iclass 20, count 0 2006.183.08:05:02.32#ibcon#*after write, iclass 20, count 0 2006.183.08:05:02.32#ibcon#*before return 0, iclass 20, count 0 2006.183.08:05:02.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:05:02.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:05:02.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:05:02.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:05:02.32$vc4f8/vb=6,4 2006.183.08:05:02.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.08:05:02.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.08:05:02.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:05:02.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:05:02.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:05:02.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:05:02.38#ibcon#enter wrdev, iclass 22, count 2 2006.183.08:05:02.38#ibcon#first serial, iclass 22, count 2 2006.183.08:05:02.38#ibcon#enter sib2, iclass 22, count 2 2006.183.08:05:02.38#ibcon#flushed, iclass 22, count 2 2006.183.08:05:02.38#ibcon#about to write, iclass 22, count 2 2006.183.08:05:02.38#ibcon#wrote, iclass 22, count 2 2006.183.08:05:02.38#ibcon#about to read 3, iclass 22, count 2 2006.183.08:05:02.40#ibcon#read 3, iclass 22, count 2 2006.183.08:05:02.40#ibcon#about to read 4, iclass 22, count 2 2006.183.08:05:02.40#ibcon#read 4, iclass 22, count 2 2006.183.08:05:02.40#ibcon#about to read 5, iclass 22, count 2 2006.183.08:05:02.40#ibcon#read 5, iclass 22, count 2 2006.183.08:05:02.40#ibcon#about to read 6, iclass 22, count 2 2006.183.08:05:02.40#ibcon#read 6, iclass 22, count 2 2006.183.08:05:02.40#ibcon#end of sib2, iclass 22, count 2 2006.183.08:05:02.40#ibcon#*mode == 0, iclass 22, count 2 2006.183.08:05:02.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.08:05:02.40#ibcon#[27=AT06-04\r\n] 2006.183.08:05:02.40#ibcon#*before write, iclass 22, count 2 2006.183.08:05:02.40#ibcon#enter sib2, iclass 22, count 2 2006.183.08:05:02.40#ibcon#flushed, iclass 22, count 2 2006.183.08:05:02.40#ibcon#about to write, iclass 22, count 2 2006.183.08:05:02.40#ibcon#wrote, iclass 22, count 2 2006.183.08:05:02.40#ibcon#about to read 3, iclass 22, count 2 2006.183.08:05:02.40#abcon#<5=/09 1.3 4.3 28.28 85 996.5\r\n> 2006.183.08:05:02.42#abcon#{5=INTERFACE CLEAR} 2006.183.08:05:02.43#ibcon#read 3, iclass 22, count 2 2006.183.08:05:02.43#ibcon#about to read 4, iclass 22, count 2 2006.183.08:05:02.43#ibcon#read 4, iclass 22, count 2 2006.183.08:05:02.43#ibcon#about to read 5, iclass 22, count 2 2006.183.08:05:02.43#ibcon#read 5, iclass 22, count 2 2006.183.08:05:02.43#ibcon#about to read 6, iclass 22, count 2 2006.183.08:05:02.43#ibcon#read 6, iclass 22, count 2 2006.183.08:05:02.43#ibcon#end of sib2, iclass 22, count 2 2006.183.08:05:02.43#ibcon#*after write, iclass 22, count 2 2006.183.08:05:02.43#ibcon#*before return 0, iclass 22, count 2 2006.183.08:05:02.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:05:02.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:05:02.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.08:05:02.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:05:02.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:05:02.48#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:05:02.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:05:02.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:05:02.55#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:05:02.55#ibcon#first serial, iclass 22, count 0 2006.183.08:05:02.55#ibcon#enter sib2, iclass 22, count 0 2006.183.08:05:02.55#ibcon#flushed, iclass 22, count 0 2006.183.08:05:02.55#ibcon#about to write, iclass 22, count 0 2006.183.08:05:02.55#ibcon#wrote, iclass 22, count 0 2006.183.08:05:02.55#ibcon#about to read 3, iclass 22, count 0 2006.183.08:05:02.57#ibcon#read 3, iclass 22, count 0 2006.183.08:05:02.57#ibcon#about to read 4, iclass 22, count 0 2006.183.08:05:02.57#ibcon#read 4, iclass 22, count 0 2006.183.08:05:02.57#ibcon#about to read 5, iclass 22, count 0 2006.183.08:05:02.57#ibcon#read 5, iclass 22, count 0 2006.183.08:05:02.57#ibcon#about to read 6, iclass 22, count 0 2006.183.08:05:02.57#ibcon#read 6, iclass 22, count 0 2006.183.08:05:02.57#ibcon#end of sib2, iclass 22, count 0 2006.183.08:05:02.57#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:05:02.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:05:02.57#ibcon#[27=USB\r\n] 2006.183.08:05:02.57#ibcon#*before write, iclass 22, count 0 2006.183.08:05:02.57#ibcon#enter sib2, iclass 22, count 0 2006.183.08:05:02.57#ibcon#flushed, iclass 22, count 0 2006.183.08:05:02.57#ibcon#about to write, iclass 22, count 0 2006.183.08:05:02.57#ibcon#wrote, iclass 22, count 0 2006.183.08:05:02.57#ibcon#about to read 3, iclass 22, count 0 2006.183.08:05:02.60#ibcon#read 3, iclass 22, count 0 2006.183.08:05:02.60#ibcon#about to read 4, iclass 22, count 0 2006.183.08:05:02.60#ibcon#read 4, iclass 22, count 0 2006.183.08:05:02.60#ibcon#about to read 5, iclass 22, count 0 2006.183.08:05:02.60#ibcon#read 5, iclass 22, count 0 2006.183.08:05:02.60#ibcon#about to read 6, iclass 22, count 0 2006.183.08:05:02.60#ibcon#read 6, iclass 22, count 0 2006.183.08:05:02.60#ibcon#end of sib2, iclass 22, count 0 2006.183.08:05:02.60#ibcon#*after write, iclass 22, count 0 2006.183.08:05:02.60#ibcon#*before return 0, iclass 22, count 0 2006.183.08:05:02.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:05:02.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:05:02.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:05:02.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:05:02.60$vc4f8/vabw=wide 2006.183.08:05:02.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:05:02.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:05:02.60#ibcon#ireg 8 cls_cnt 0 2006.183.08:05:02.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:05:02.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:05:02.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:05:02.60#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:05:02.60#ibcon#first serial, iclass 28, count 0 2006.183.08:05:02.60#ibcon#enter sib2, iclass 28, count 0 2006.183.08:05:02.60#ibcon#flushed, iclass 28, count 0 2006.183.08:05:02.60#ibcon#about to write, iclass 28, count 0 2006.183.08:05:02.60#ibcon#wrote, iclass 28, count 0 2006.183.08:05:02.60#ibcon#about to read 3, iclass 28, count 0 2006.183.08:05:02.62#ibcon#read 3, iclass 28, count 0 2006.183.08:05:02.62#ibcon#about to read 4, iclass 28, count 0 2006.183.08:05:02.62#ibcon#read 4, iclass 28, count 0 2006.183.08:05:02.62#ibcon#about to read 5, iclass 28, count 0 2006.183.08:05:02.62#ibcon#read 5, iclass 28, count 0 2006.183.08:05:02.62#ibcon#about to read 6, iclass 28, count 0 2006.183.08:05:02.62#ibcon#read 6, iclass 28, count 0 2006.183.08:05:02.62#ibcon#end of sib2, iclass 28, count 0 2006.183.08:05:02.62#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:05:02.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:05:02.62#ibcon#[25=BW32\r\n] 2006.183.08:05:02.62#ibcon#*before write, iclass 28, count 0 2006.183.08:05:02.62#ibcon#enter sib2, iclass 28, count 0 2006.183.08:05:02.62#ibcon#flushed, iclass 28, count 0 2006.183.08:05:02.62#ibcon#about to write, iclass 28, count 0 2006.183.08:05:02.62#ibcon#wrote, iclass 28, count 0 2006.183.08:05:02.62#ibcon#about to read 3, iclass 28, count 0 2006.183.08:05:02.65#ibcon#read 3, iclass 28, count 0 2006.183.08:05:02.65#ibcon#about to read 4, iclass 28, count 0 2006.183.08:05:02.65#ibcon#read 4, iclass 28, count 0 2006.183.08:05:02.65#ibcon#about to read 5, iclass 28, count 0 2006.183.08:05:02.65#ibcon#read 5, iclass 28, count 0 2006.183.08:05:02.65#ibcon#about to read 6, iclass 28, count 0 2006.183.08:05:02.65#ibcon#read 6, iclass 28, count 0 2006.183.08:05:02.65#ibcon#end of sib2, iclass 28, count 0 2006.183.08:05:02.65#ibcon#*after write, iclass 28, count 0 2006.183.08:05:02.65#ibcon#*before return 0, iclass 28, count 0 2006.183.08:05:02.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:05:02.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:05:02.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:05:02.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:05:02.65$vc4f8/vbbw=wide 2006.183.08:05:02.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:05:02.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:05:02.65#ibcon#ireg 8 cls_cnt 0 2006.183.08:05:02.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:05:02.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:05:02.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:05:02.72#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:05:02.72#ibcon#first serial, iclass 30, count 0 2006.183.08:05:02.72#ibcon#enter sib2, iclass 30, count 0 2006.183.08:05:02.72#ibcon#flushed, iclass 30, count 0 2006.183.08:05:02.72#ibcon#about to write, iclass 30, count 0 2006.183.08:05:02.72#ibcon#wrote, iclass 30, count 0 2006.183.08:05:02.72#ibcon#about to read 3, iclass 30, count 0 2006.183.08:05:02.74#ibcon#read 3, iclass 30, count 0 2006.183.08:05:02.74#ibcon#about to read 4, iclass 30, count 0 2006.183.08:05:02.74#ibcon#read 4, iclass 30, count 0 2006.183.08:05:02.74#ibcon#about to read 5, iclass 30, count 0 2006.183.08:05:02.74#ibcon#read 5, iclass 30, count 0 2006.183.08:05:02.74#ibcon#about to read 6, iclass 30, count 0 2006.183.08:05:02.74#ibcon#read 6, iclass 30, count 0 2006.183.08:05:02.74#ibcon#end of sib2, iclass 30, count 0 2006.183.08:05:02.74#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:05:02.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:05:02.74#ibcon#[27=BW32\r\n] 2006.183.08:05:02.74#ibcon#*before write, iclass 30, count 0 2006.183.08:05:02.74#ibcon#enter sib2, iclass 30, count 0 2006.183.08:05:02.74#ibcon#flushed, iclass 30, count 0 2006.183.08:05:02.74#ibcon#about to write, iclass 30, count 0 2006.183.08:05:02.74#ibcon#wrote, iclass 30, count 0 2006.183.08:05:02.74#ibcon#about to read 3, iclass 30, count 0 2006.183.08:05:02.77#ibcon#read 3, iclass 30, count 0 2006.183.08:05:02.77#ibcon#about to read 4, iclass 30, count 0 2006.183.08:05:02.77#ibcon#read 4, iclass 30, count 0 2006.183.08:05:02.77#ibcon#about to read 5, iclass 30, count 0 2006.183.08:05:02.77#ibcon#read 5, iclass 30, count 0 2006.183.08:05:02.77#ibcon#about to read 6, iclass 30, count 0 2006.183.08:05:02.77#ibcon#read 6, iclass 30, count 0 2006.183.08:05:02.77#ibcon#end of sib2, iclass 30, count 0 2006.183.08:05:02.77#ibcon#*after write, iclass 30, count 0 2006.183.08:05:02.77#ibcon#*before return 0, iclass 30, count 0 2006.183.08:05:02.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:05:02.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:05:02.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:05:02.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:05:02.77$4f8m12a/ifd4f 2006.183.08:05:02.77$ifd4f/lo= 2006.183.08:05:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:05:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:05:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:05:02.77$ifd4f/patch= 2006.183.08:05:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:05:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:05:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:05:02.77$4f8m12a/"form=m,16.000,1:2 2006.183.08:05:02.77$4f8m12a/"tpicd 2006.183.08:05:02.77$4f8m12a/echo=off 2006.183.08:05:02.77$4f8m12a/xlog=off 2006.183.08:05:02.77:!2006.183.08:05:30 2006.183.08:05:17.14#trakl#Source acquired 2006.183.08:05:18.14#flagr#flagr/antenna,acquired 2006.183.08:05:30.00:preob 2006.183.08:05:31.14/onsource/TRACKING 2006.183.08:05:31.14:!2006.183.08:05:40 2006.183.08:05:40.00:data_valid=on 2006.183.08:05:40.00:midob 2006.183.08:05:40.14/onsource/TRACKING 2006.183.08:05:40.14/wx/28.29,996.5,85 2006.183.08:05:40.33/cable/+6.4513E-03 2006.183.08:05:41.42/va/01,08,usb,yes,28,29 2006.183.08:05:41.42/va/02,07,usb,yes,28,30 2006.183.08:05:41.42/va/03,06,usb,yes,30,30 2006.183.08:05:41.42/va/04,07,usb,yes,29,31 2006.183.08:05:41.42/va/05,07,usb,yes,30,32 2006.183.08:05:41.42/va/06,06,usb,yes,30,29 2006.183.08:05:41.42/va/07,06,usb,yes,30,30 2006.183.08:05:41.42/va/08,07,usb,yes,29,28 2006.183.08:05:41.65/valo/01,532.99,yes,locked 2006.183.08:05:41.65/valo/02,572.99,yes,locked 2006.183.08:05:41.65/valo/03,672.99,yes,locked 2006.183.08:05:41.65/valo/04,832.99,yes,locked 2006.183.08:05:41.65/valo/05,652.99,yes,locked 2006.183.08:05:41.65/valo/06,772.99,yes,locked 2006.183.08:05:41.65/valo/07,832.99,yes,locked 2006.183.08:05:41.65/valo/08,852.99,yes,locked 2006.183.08:05:42.74/vb/01,04,usb,yes,28,27 2006.183.08:05:42.74/vb/02,04,usb,yes,30,32 2006.183.08:05:42.74/vb/03,04,usb,yes,27,30 2006.183.08:05:42.74/vb/04,04,usb,yes,28,28 2006.183.08:05:42.74/vb/05,04,usb,yes,26,30 2006.183.08:05:42.74/vb/06,04,usb,yes,27,30 2006.183.08:05:42.74/vb/07,04,usb,yes,29,29 2006.183.08:05:42.74/vb/08,04,usb,yes,27,30 2006.183.08:05:42.97/vblo/01,632.99,yes,locked 2006.183.08:05:42.97/vblo/02,640.99,yes,locked 2006.183.08:05:42.97/vblo/03,656.99,yes,locked 2006.183.08:05:42.97/vblo/04,712.99,yes,locked 2006.183.08:05:42.97/vblo/05,744.99,yes,locked 2006.183.08:05:42.97/vblo/06,752.99,yes,locked 2006.183.08:05:42.97/vblo/07,734.99,yes,locked 2006.183.08:05:42.97/vblo/08,744.99,yes,locked 2006.183.08:05:43.12/vabw/8 2006.183.08:05:43.27/vbbw/8 2006.183.08:05:43.41/xfe/off,on,14.7 2006.183.08:05:43.79/ifatt/23,28,28,28 2006.183.08:05:44.08/fmout-gps/S +3.33E-07 2006.183.08:05:44.12:!2006.183.08:06:40 2006.183.08:06:40.00:data_valid=off 2006.183.08:06:40.00:postob 2006.183.08:06:40.09/cable/+6.4511E-03 2006.183.08:06:40.09/wx/28.31,996.5,85 2006.183.08:06:41.08/fmout-gps/S +3.34E-07 2006.183.08:06:41.08:scan_name=183-0807,k06183,60 2006.183.08:06:41.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.183.08:06:41.14#flagr#flagr/antenna,new-source 2006.183.08:06:42.13:checkk5 2006.183.08:06:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:06:42.87/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:06:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:06:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:06:43.98/chk_obsdata//k5ts1/T1830805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:06:44.36/chk_obsdata//k5ts2/T1830805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:06:44.73/chk_obsdata//k5ts3/T1830805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:06:45.10/chk_obsdata//k5ts4/T1830805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:06:45.78/k5log//k5ts1_log_newline 2006.183.08:06:46.47/k5log//k5ts2_log_newline 2006.183.08:06:47.18/k5log//k5ts3_log_newline 2006.183.08:06:47.87/k5log//k5ts4_log_newline 2006.183.08:06:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:06:47.89:4f8m12a=2 2006.183.08:06:47.89$4f8m12a/echo=on 2006.183.08:06:47.89$4f8m12a/pcalon 2006.183.08:06:47.89$pcalon/"no phase cal control is implemented here 2006.183.08:06:47.89$4f8m12a/"tpicd=stop 2006.183.08:06:47.89$4f8m12a/vc4f8 2006.183.08:06:47.89$vc4f8/valo=1,532.99 2006.183.08:06:47.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.08:06:47.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.08:06:47.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:47.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:47.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:47.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:47.90#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:06:47.90#ibcon#first serial, iclass 37, count 0 2006.183.08:06:47.90#ibcon#enter sib2, iclass 37, count 0 2006.183.08:06:47.90#ibcon#flushed, iclass 37, count 0 2006.183.08:06:47.90#ibcon#about to write, iclass 37, count 0 2006.183.08:06:47.90#ibcon#wrote, iclass 37, count 0 2006.183.08:06:47.90#ibcon#about to read 3, iclass 37, count 0 2006.183.08:06:47.94#ibcon#read 3, iclass 37, count 0 2006.183.08:06:47.94#ibcon#about to read 4, iclass 37, count 0 2006.183.08:06:47.94#ibcon#read 4, iclass 37, count 0 2006.183.08:06:47.94#ibcon#about to read 5, iclass 37, count 0 2006.183.08:06:47.94#ibcon#read 5, iclass 37, count 0 2006.183.08:06:47.94#ibcon#about to read 6, iclass 37, count 0 2006.183.08:06:47.94#ibcon#read 6, iclass 37, count 0 2006.183.08:06:47.94#ibcon#end of sib2, iclass 37, count 0 2006.183.08:06:47.94#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:06:47.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:06:47.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:06:47.94#ibcon#*before write, iclass 37, count 0 2006.183.08:06:47.94#ibcon#enter sib2, iclass 37, count 0 2006.183.08:06:47.94#ibcon#flushed, iclass 37, count 0 2006.183.08:06:47.94#ibcon#about to write, iclass 37, count 0 2006.183.08:06:47.94#ibcon#wrote, iclass 37, count 0 2006.183.08:06:47.94#ibcon#about to read 3, iclass 37, count 0 2006.183.08:06:47.99#ibcon#read 3, iclass 37, count 0 2006.183.08:06:47.99#ibcon#about to read 4, iclass 37, count 0 2006.183.08:06:47.99#ibcon#read 4, iclass 37, count 0 2006.183.08:06:47.99#ibcon#about to read 5, iclass 37, count 0 2006.183.08:06:47.99#ibcon#read 5, iclass 37, count 0 2006.183.08:06:47.99#ibcon#about to read 6, iclass 37, count 0 2006.183.08:06:47.99#ibcon#read 6, iclass 37, count 0 2006.183.08:06:47.99#ibcon#end of sib2, iclass 37, count 0 2006.183.08:06:47.99#ibcon#*after write, iclass 37, count 0 2006.183.08:06:47.99#ibcon#*before return 0, iclass 37, count 0 2006.183.08:06:47.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:47.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:47.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:06:47.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:06:47.99$vc4f8/va=1,8 2006.183.08:06:47.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.08:06:47.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.08:06:47.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:47.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:47.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:47.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:47.99#ibcon#enter wrdev, iclass 39, count 2 2006.183.08:06:47.99#ibcon#first serial, iclass 39, count 2 2006.183.08:06:47.99#ibcon#enter sib2, iclass 39, count 2 2006.183.08:06:47.99#ibcon#flushed, iclass 39, count 2 2006.183.08:06:47.99#ibcon#about to write, iclass 39, count 2 2006.183.08:06:47.99#ibcon#wrote, iclass 39, count 2 2006.183.08:06:47.99#ibcon#about to read 3, iclass 39, count 2 2006.183.08:06:48.01#ibcon#read 3, iclass 39, count 2 2006.183.08:06:48.01#ibcon#about to read 4, iclass 39, count 2 2006.183.08:06:48.01#ibcon#read 4, iclass 39, count 2 2006.183.08:06:48.01#ibcon#about to read 5, iclass 39, count 2 2006.183.08:06:48.01#ibcon#read 5, iclass 39, count 2 2006.183.08:06:48.01#ibcon#about to read 6, iclass 39, count 2 2006.183.08:06:48.01#ibcon#read 6, iclass 39, count 2 2006.183.08:06:48.01#ibcon#end of sib2, iclass 39, count 2 2006.183.08:06:48.01#ibcon#*mode == 0, iclass 39, count 2 2006.183.08:06:48.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.08:06:48.01#ibcon#[25=AT01-08\r\n] 2006.183.08:06:48.01#ibcon#*before write, iclass 39, count 2 2006.183.08:06:48.01#ibcon#enter sib2, iclass 39, count 2 2006.183.08:06:48.01#ibcon#flushed, iclass 39, count 2 2006.183.08:06:48.01#ibcon#about to write, iclass 39, count 2 2006.183.08:06:48.01#ibcon#wrote, iclass 39, count 2 2006.183.08:06:48.01#ibcon#about to read 3, iclass 39, count 2 2006.183.08:06:48.05#ibcon#read 3, iclass 39, count 2 2006.183.08:06:48.05#ibcon#about to read 4, iclass 39, count 2 2006.183.08:06:48.05#ibcon#read 4, iclass 39, count 2 2006.183.08:06:48.05#ibcon#about to read 5, iclass 39, count 2 2006.183.08:06:48.05#ibcon#read 5, iclass 39, count 2 2006.183.08:06:48.05#ibcon#about to read 6, iclass 39, count 2 2006.183.08:06:48.05#ibcon#read 6, iclass 39, count 2 2006.183.08:06:48.05#ibcon#end of sib2, iclass 39, count 2 2006.183.08:06:48.05#ibcon#*after write, iclass 39, count 2 2006.183.08:06:48.05#ibcon#*before return 0, iclass 39, count 2 2006.183.08:06:48.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:48.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:48.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.08:06:48.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:48.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:48.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:48.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:48.17#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:06:48.17#ibcon#first serial, iclass 39, count 0 2006.183.08:06:48.17#ibcon#enter sib2, iclass 39, count 0 2006.183.08:06:48.17#ibcon#flushed, iclass 39, count 0 2006.183.08:06:48.17#ibcon#about to write, iclass 39, count 0 2006.183.08:06:48.17#ibcon#wrote, iclass 39, count 0 2006.183.08:06:48.17#ibcon#about to read 3, iclass 39, count 0 2006.183.08:06:48.19#ibcon#read 3, iclass 39, count 0 2006.183.08:06:48.19#ibcon#about to read 4, iclass 39, count 0 2006.183.08:06:48.19#ibcon#read 4, iclass 39, count 0 2006.183.08:06:48.19#ibcon#about to read 5, iclass 39, count 0 2006.183.08:06:48.19#ibcon#read 5, iclass 39, count 0 2006.183.08:06:48.19#ibcon#about to read 6, iclass 39, count 0 2006.183.08:06:48.19#ibcon#read 6, iclass 39, count 0 2006.183.08:06:48.19#ibcon#end of sib2, iclass 39, count 0 2006.183.08:06:48.19#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:06:48.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:06:48.19#ibcon#[25=USB\r\n] 2006.183.08:06:48.19#ibcon#*before write, iclass 39, count 0 2006.183.08:06:48.19#ibcon#enter sib2, iclass 39, count 0 2006.183.08:06:48.19#ibcon#flushed, iclass 39, count 0 2006.183.08:06:48.19#ibcon#about to write, iclass 39, count 0 2006.183.08:06:48.19#ibcon#wrote, iclass 39, count 0 2006.183.08:06:48.19#ibcon#about to read 3, iclass 39, count 0 2006.183.08:06:48.22#ibcon#read 3, iclass 39, count 0 2006.183.08:06:48.22#ibcon#about to read 4, iclass 39, count 0 2006.183.08:06:48.22#ibcon#read 4, iclass 39, count 0 2006.183.08:06:48.22#ibcon#about to read 5, iclass 39, count 0 2006.183.08:06:48.22#ibcon#read 5, iclass 39, count 0 2006.183.08:06:48.22#ibcon#about to read 6, iclass 39, count 0 2006.183.08:06:48.22#ibcon#read 6, iclass 39, count 0 2006.183.08:06:48.22#ibcon#end of sib2, iclass 39, count 0 2006.183.08:06:48.22#ibcon#*after write, iclass 39, count 0 2006.183.08:06:48.22#ibcon#*before return 0, iclass 39, count 0 2006.183.08:06:48.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:48.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:48.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:06:48.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:06:48.22$vc4f8/valo=2,572.99 2006.183.08:06:48.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:06:48.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:06:48.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:48.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:48.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:48.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:48.22#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:06:48.22#ibcon#first serial, iclass 3, count 0 2006.183.08:06:48.22#ibcon#enter sib2, iclass 3, count 0 2006.183.08:06:48.22#ibcon#flushed, iclass 3, count 0 2006.183.08:06:48.22#ibcon#about to write, iclass 3, count 0 2006.183.08:06:48.22#ibcon#wrote, iclass 3, count 0 2006.183.08:06:48.22#ibcon#about to read 3, iclass 3, count 0 2006.183.08:06:48.24#ibcon#read 3, iclass 3, count 0 2006.183.08:06:48.24#ibcon#about to read 4, iclass 3, count 0 2006.183.08:06:48.24#ibcon#read 4, iclass 3, count 0 2006.183.08:06:48.24#ibcon#about to read 5, iclass 3, count 0 2006.183.08:06:48.24#ibcon#read 5, iclass 3, count 0 2006.183.08:06:48.24#ibcon#about to read 6, iclass 3, count 0 2006.183.08:06:48.24#ibcon#read 6, iclass 3, count 0 2006.183.08:06:48.24#ibcon#end of sib2, iclass 3, count 0 2006.183.08:06:48.24#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:06:48.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:06:48.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:06:48.24#ibcon#*before write, iclass 3, count 0 2006.183.08:06:48.24#ibcon#enter sib2, iclass 3, count 0 2006.183.08:06:48.24#ibcon#flushed, iclass 3, count 0 2006.183.08:06:48.24#ibcon#about to write, iclass 3, count 0 2006.183.08:06:48.24#ibcon#wrote, iclass 3, count 0 2006.183.08:06:48.24#ibcon#about to read 3, iclass 3, count 0 2006.183.08:06:48.28#ibcon#read 3, iclass 3, count 0 2006.183.08:06:48.28#ibcon#about to read 4, iclass 3, count 0 2006.183.08:06:48.28#ibcon#read 4, iclass 3, count 0 2006.183.08:06:48.28#ibcon#about to read 5, iclass 3, count 0 2006.183.08:06:48.28#ibcon#read 5, iclass 3, count 0 2006.183.08:06:48.28#ibcon#about to read 6, iclass 3, count 0 2006.183.08:06:48.28#ibcon#read 6, iclass 3, count 0 2006.183.08:06:48.28#ibcon#end of sib2, iclass 3, count 0 2006.183.08:06:48.28#ibcon#*after write, iclass 3, count 0 2006.183.08:06:48.28#ibcon#*before return 0, iclass 3, count 0 2006.183.08:06:48.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:48.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:48.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:06:48.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:06:48.28$vc4f8/va=2,7 2006.183.08:06:48.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.08:06:48.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.08:06:48.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:48.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:48.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:48.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:48.34#ibcon#enter wrdev, iclass 5, count 2 2006.183.08:06:48.34#ibcon#first serial, iclass 5, count 2 2006.183.08:06:48.34#ibcon#enter sib2, iclass 5, count 2 2006.183.08:06:48.34#ibcon#flushed, iclass 5, count 2 2006.183.08:06:48.34#ibcon#about to write, iclass 5, count 2 2006.183.08:06:48.34#ibcon#wrote, iclass 5, count 2 2006.183.08:06:48.34#ibcon#about to read 3, iclass 5, count 2 2006.183.08:06:48.36#ibcon#read 3, iclass 5, count 2 2006.183.08:06:48.36#ibcon#about to read 4, iclass 5, count 2 2006.183.08:06:48.36#ibcon#read 4, iclass 5, count 2 2006.183.08:06:48.36#ibcon#about to read 5, iclass 5, count 2 2006.183.08:06:48.36#ibcon#read 5, iclass 5, count 2 2006.183.08:06:48.36#ibcon#about to read 6, iclass 5, count 2 2006.183.08:06:48.36#ibcon#read 6, iclass 5, count 2 2006.183.08:06:48.36#ibcon#end of sib2, iclass 5, count 2 2006.183.08:06:48.36#ibcon#*mode == 0, iclass 5, count 2 2006.183.08:06:48.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.08:06:48.36#ibcon#[25=AT02-07\r\n] 2006.183.08:06:48.36#ibcon#*before write, iclass 5, count 2 2006.183.08:06:48.36#ibcon#enter sib2, iclass 5, count 2 2006.183.08:06:48.36#ibcon#flushed, iclass 5, count 2 2006.183.08:06:48.36#ibcon#about to write, iclass 5, count 2 2006.183.08:06:48.36#ibcon#wrote, iclass 5, count 2 2006.183.08:06:48.36#ibcon#about to read 3, iclass 5, count 2 2006.183.08:06:48.39#ibcon#read 3, iclass 5, count 2 2006.183.08:06:48.39#ibcon#about to read 4, iclass 5, count 2 2006.183.08:06:48.39#ibcon#read 4, iclass 5, count 2 2006.183.08:06:48.39#ibcon#about to read 5, iclass 5, count 2 2006.183.08:06:48.39#ibcon#read 5, iclass 5, count 2 2006.183.08:06:48.39#ibcon#about to read 6, iclass 5, count 2 2006.183.08:06:48.39#ibcon#read 6, iclass 5, count 2 2006.183.08:06:48.39#ibcon#end of sib2, iclass 5, count 2 2006.183.08:06:48.39#ibcon#*after write, iclass 5, count 2 2006.183.08:06:48.39#ibcon#*before return 0, iclass 5, count 2 2006.183.08:06:48.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:48.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:48.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.08:06:48.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:48.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:48.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:48.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:48.51#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:06:48.51#ibcon#first serial, iclass 5, count 0 2006.183.08:06:48.51#ibcon#enter sib2, iclass 5, count 0 2006.183.08:06:48.51#ibcon#flushed, iclass 5, count 0 2006.183.08:06:48.51#ibcon#about to write, iclass 5, count 0 2006.183.08:06:48.51#ibcon#wrote, iclass 5, count 0 2006.183.08:06:48.51#ibcon#about to read 3, iclass 5, count 0 2006.183.08:06:48.53#ibcon#read 3, iclass 5, count 0 2006.183.08:06:48.53#ibcon#about to read 4, iclass 5, count 0 2006.183.08:06:48.53#ibcon#read 4, iclass 5, count 0 2006.183.08:06:48.53#ibcon#about to read 5, iclass 5, count 0 2006.183.08:06:48.53#ibcon#read 5, iclass 5, count 0 2006.183.08:06:48.53#ibcon#about to read 6, iclass 5, count 0 2006.183.08:06:48.53#ibcon#read 6, iclass 5, count 0 2006.183.08:06:48.53#ibcon#end of sib2, iclass 5, count 0 2006.183.08:06:48.53#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:06:48.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:06:48.53#ibcon#[25=USB\r\n] 2006.183.08:06:48.53#ibcon#*before write, iclass 5, count 0 2006.183.08:06:48.53#ibcon#enter sib2, iclass 5, count 0 2006.183.08:06:48.53#ibcon#flushed, iclass 5, count 0 2006.183.08:06:48.53#ibcon#about to write, iclass 5, count 0 2006.183.08:06:48.53#ibcon#wrote, iclass 5, count 0 2006.183.08:06:48.53#ibcon#about to read 3, iclass 5, count 0 2006.183.08:06:48.56#ibcon#read 3, iclass 5, count 0 2006.183.08:06:48.56#ibcon#about to read 4, iclass 5, count 0 2006.183.08:06:48.56#ibcon#read 4, iclass 5, count 0 2006.183.08:06:48.56#ibcon#about to read 5, iclass 5, count 0 2006.183.08:06:48.56#ibcon#read 5, iclass 5, count 0 2006.183.08:06:48.56#ibcon#about to read 6, iclass 5, count 0 2006.183.08:06:48.56#ibcon#read 6, iclass 5, count 0 2006.183.08:06:48.56#ibcon#end of sib2, iclass 5, count 0 2006.183.08:06:48.56#ibcon#*after write, iclass 5, count 0 2006.183.08:06:48.56#ibcon#*before return 0, iclass 5, count 0 2006.183.08:06:48.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:48.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:48.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:06:48.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:06:48.56$vc4f8/valo=3,672.99 2006.183.08:06:48.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.08:06:48.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.08:06:48.56#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:48.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:48.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:48.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:48.56#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:06:48.56#ibcon#first serial, iclass 7, count 0 2006.183.08:06:48.56#ibcon#enter sib2, iclass 7, count 0 2006.183.08:06:48.56#ibcon#flushed, iclass 7, count 0 2006.183.08:06:48.56#ibcon#about to write, iclass 7, count 0 2006.183.08:06:48.56#ibcon#wrote, iclass 7, count 0 2006.183.08:06:48.56#ibcon#about to read 3, iclass 7, count 0 2006.183.08:06:48.58#ibcon#read 3, iclass 7, count 0 2006.183.08:06:48.58#ibcon#about to read 4, iclass 7, count 0 2006.183.08:06:48.58#ibcon#read 4, iclass 7, count 0 2006.183.08:06:48.58#ibcon#about to read 5, iclass 7, count 0 2006.183.08:06:48.58#ibcon#read 5, iclass 7, count 0 2006.183.08:06:48.58#ibcon#about to read 6, iclass 7, count 0 2006.183.08:06:48.58#ibcon#read 6, iclass 7, count 0 2006.183.08:06:48.58#ibcon#end of sib2, iclass 7, count 0 2006.183.08:06:48.58#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:06:48.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:06:48.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:06:48.58#ibcon#*before write, iclass 7, count 0 2006.183.08:06:48.58#ibcon#enter sib2, iclass 7, count 0 2006.183.08:06:48.58#ibcon#flushed, iclass 7, count 0 2006.183.08:06:48.58#ibcon#about to write, iclass 7, count 0 2006.183.08:06:48.58#ibcon#wrote, iclass 7, count 0 2006.183.08:06:48.58#ibcon#about to read 3, iclass 7, count 0 2006.183.08:06:48.63#ibcon#read 3, iclass 7, count 0 2006.183.08:06:48.63#ibcon#about to read 4, iclass 7, count 0 2006.183.08:06:48.63#ibcon#read 4, iclass 7, count 0 2006.183.08:06:48.63#ibcon#about to read 5, iclass 7, count 0 2006.183.08:06:48.63#ibcon#read 5, iclass 7, count 0 2006.183.08:06:48.63#ibcon#about to read 6, iclass 7, count 0 2006.183.08:06:48.63#ibcon#read 6, iclass 7, count 0 2006.183.08:06:48.63#ibcon#end of sib2, iclass 7, count 0 2006.183.08:06:48.63#ibcon#*after write, iclass 7, count 0 2006.183.08:06:48.63#ibcon#*before return 0, iclass 7, count 0 2006.183.08:06:48.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:48.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:48.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:06:48.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:06:48.63$vc4f8/va=3,6 2006.183.08:06:48.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.08:06:48.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.08:06:48.63#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:48.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:48.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:48.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:48.68#ibcon#enter wrdev, iclass 11, count 2 2006.183.08:06:48.68#ibcon#first serial, iclass 11, count 2 2006.183.08:06:48.68#ibcon#enter sib2, iclass 11, count 2 2006.183.08:06:48.68#ibcon#flushed, iclass 11, count 2 2006.183.08:06:48.68#ibcon#about to write, iclass 11, count 2 2006.183.08:06:48.68#ibcon#wrote, iclass 11, count 2 2006.183.08:06:48.68#ibcon#about to read 3, iclass 11, count 2 2006.183.08:06:48.70#ibcon#read 3, iclass 11, count 2 2006.183.08:06:48.70#ibcon#about to read 4, iclass 11, count 2 2006.183.08:06:48.70#ibcon#read 4, iclass 11, count 2 2006.183.08:06:48.70#ibcon#about to read 5, iclass 11, count 2 2006.183.08:06:48.70#ibcon#read 5, iclass 11, count 2 2006.183.08:06:48.70#ibcon#about to read 6, iclass 11, count 2 2006.183.08:06:48.70#ibcon#read 6, iclass 11, count 2 2006.183.08:06:48.70#ibcon#end of sib2, iclass 11, count 2 2006.183.08:06:48.70#ibcon#*mode == 0, iclass 11, count 2 2006.183.08:06:48.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.08:06:48.70#ibcon#[25=AT03-06\r\n] 2006.183.08:06:48.70#ibcon#*before write, iclass 11, count 2 2006.183.08:06:48.70#ibcon#enter sib2, iclass 11, count 2 2006.183.08:06:48.70#ibcon#flushed, iclass 11, count 2 2006.183.08:06:48.70#ibcon#about to write, iclass 11, count 2 2006.183.08:06:48.70#ibcon#wrote, iclass 11, count 2 2006.183.08:06:48.70#ibcon#about to read 3, iclass 11, count 2 2006.183.08:06:48.73#ibcon#read 3, iclass 11, count 2 2006.183.08:06:48.73#ibcon#about to read 4, iclass 11, count 2 2006.183.08:06:48.73#ibcon#read 4, iclass 11, count 2 2006.183.08:06:48.73#ibcon#about to read 5, iclass 11, count 2 2006.183.08:06:48.73#ibcon#read 5, iclass 11, count 2 2006.183.08:06:48.73#ibcon#about to read 6, iclass 11, count 2 2006.183.08:06:48.73#ibcon#read 6, iclass 11, count 2 2006.183.08:06:48.73#ibcon#end of sib2, iclass 11, count 2 2006.183.08:06:48.73#ibcon#*after write, iclass 11, count 2 2006.183.08:06:48.73#ibcon#*before return 0, iclass 11, count 2 2006.183.08:06:48.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:48.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:48.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.08:06:48.73#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:48.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:48.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:48.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:48.85#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:06:48.85#ibcon#first serial, iclass 11, count 0 2006.183.08:06:48.85#ibcon#enter sib2, iclass 11, count 0 2006.183.08:06:48.85#ibcon#flushed, iclass 11, count 0 2006.183.08:06:48.85#ibcon#about to write, iclass 11, count 0 2006.183.08:06:48.85#ibcon#wrote, iclass 11, count 0 2006.183.08:06:48.85#ibcon#about to read 3, iclass 11, count 0 2006.183.08:06:48.87#ibcon#read 3, iclass 11, count 0 2006.183.08:06:48.87#ibcon#about to read 4, iclass 11, count 0 2006.183.08:06:48.87#ibcon#read 4, iclass 11, count 0 2006.183.08:06:48.87#ibcon#about to read 5, iclass 11, count 0 2006.183.08:06:48.87#ibcon#read 5, iclass 11, count 0 2006.183.08:06:48.87#ibcon#about to read 6, iclass 11, count 0 2006.183.08:06:48.87#ibcon#read 6, iclass 11, count 0 2006.183.08:06:48.87#ibcon#end of sib2, iclass 11, count 0 2006.183.08:06:48.87#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:06:48.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:06:48.87#ibcon#[25=USB\r\n] 2006.183.08:06:48.87#ibcon#*before write, iclass 11, count 0 2006.183.08:06:48.87#ibcon#enter sib2, iclass 11, count 0 2006.183.08:06:48.87#ibcon#flushed, iclass 11, count 0 2006.183.08:06:48.87#ibcon#about to write, iclass 11, count 0 2006.183.08:06:48.87#ibcon#wrote, iclass 11, count 0 2006.183.08:06:48.87#ibcon#about to read 3, iclass 11, count 0 2006.183.08:06:48.90#ibcon#read 3, iclass 11, count 0 2006.183.08:06:48.90#ibcon#about to read 4, iclass 11, count 0 2006.183.08:06:48.90#ibcon#read 4, iclass 11, count 0 2006.183.08:06:48.90#ibcon#about to read 5, iclass 11, count 0 2006.183.08:06:48.90#ibcon#read 5, iclass 11, count 0 2006.183.08:06:48.90#ibcon#about to read 6, iclass 11, count 0 2006.183.08:06:48.90#ibcon#read 6, iclass 11, count 0 2006.183.08:06:48.90#ibcon#end of sib2, iclass 11, count 0 2006.183.08:06:48.90#ibcon#*after write, iclass 11, count 0 2006.183.08:06:48.90#ibcon#*before return 0, iclass 11, count 0 2006.183.08:06:48.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:48.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:48.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:06:48.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:06:48.90$vc4f8/valo=4,832.99 2006.183.08:06:48.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.08:06:48.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.08:06:48.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:48.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:48.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:48.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:48.90#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:06:48.90#ibcon#first serial, iclass 13, count 0 2006.183.08:06:48.90#ibcon#enter sib2, iclass 13, count 0 2006.183.08:06:48.90#ibcon#flushed, iclass 13, count 0 2006.183.08:06:48.90#ibcon#about to write, iclass 13, count 0 2006.183.08:06:48.90#ibcon#wrote, iclass 13, count 0 2006.183.08:06:48.90#ibcon#about to read 3, iclass 13, count 0 2006.183.08:06:48.92#ibcon#read 3, iclass 13, count 0 2006.183.08:06:48.92#ibcon#about to read 4, iclass 13, count 0 2006.183.08:06:48.92#ibcon#read 4, iclass 13, count 0 2006.183.08:06:48.92#ibcon#about to read 5, iclass 13, count 0 2006.183.08:06:48.92#ibcon#read 5, iclass 13, count 0 2006.183.08:06:48.92#ibcon#about to read 6, iclass 13, count 0 2006.183.08:06:48.92#ibcon#read 6, iclass 13, count 0 2006.183.08:06:48.92#ibcon#end of sib2, iclass 13, count 0 2006.183.08:06:48.92#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:06:48.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:06:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:06:48.92#ibcon#*before write, iclass 13, count 0 2006.183.08:06:48.92#ibcon#enter sib2, iclass 13, count 0 2006.183.08:06:48.92#ibcon#flushed, iclass 13, count 0 2006.183.08:06:48.92#ibcon#about to write, iclass 13, count 0 2006.183.08:06:48.92#ibcon#wrote, iclass 13, count 0 2006.183.08:06:48.92#ibcon#about to read 3, iclass 13, count 0 2006.183.08:06:48.96#ibcon#read 3, iclass 13, count 0 2006.183.08:06:48.96#ibcon#about to read 4, iclass 13, count 0 2006.183.08:06:48.96#ibcon#read 4, iclass 13, count 0 2006.183.08:06:48.96#ibcon#about to read 5, iclass 13, count 0 2006.183.08:06:48.96#ibcon#read 5, iclass 13, count 0 2006.183.08:06:48.96#ibcon#about to read 6, iclass 13, count 0 2006.183.08:06:48.96#ibcon#read 6, iclass 13, count 0 2006.183.08:06:48.96#ibcon#end of sib2, iclass 13, count 0 2006.183.08:06:48.96#ibcon#*after write, iclass 13, count 0 2006.183.08:06:48.96#ibcon#*before return 0, iclass 13, count 0 2006.183.08:06:48.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:48.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:48.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:06:48.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:06:48.96$vc4f8/va=4,7 2006.183.08:06:48.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.08:06:48.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.08:06:48.96#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:48.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:49.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:49.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:49.02#ibcon#enter wrdev, iclass 15, count 2 2006.183.08:06:49.02#ibcon#first serial, iclass 15, count 2 2006.183.08:06:49.02#ibcon#enter sib2, iclass 15, count 2 2006.183.08:06:49.02#ibcon#flushed, iclass 15, count 2 2006.183.08:06:49.02#ibcon#about to write, iclass 15, count 2 2006.183.08:06:49.02#ibcon#wrote, iclass 15, count 2 2006.183.08:06:49.02#ibcon#about to read 3, iclass 15, count 2 2006.183.08:06:49.04#ibcon#read 3, iclass 15, count 2 2006.183.08:06:49.04#ibcon#about to read 4, iclass 15, count 2 2006.183.08:06:49.04#ibcon#read 4, iclass 15, count 2 2006.183.08:06:49.04#ibcon#about to read 5, iclass 15, count 2 2006.183.08:06:49.04#ibcon#read 5, iclass 15, count 2 2006.183.08:06:49.04#ibcon#about to read 6, iclass 15, count 2 2006.183.08:06:49.04#ibcon#read 6, iclass 15, count 2 2006.183.08:06:49.04#ibcon#end of sib2, iclass 15, count 2 2006.183.08:06:49.04#ibcon#*mode == 0, iclass 15, count 2 2006.183.08:06:49.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.08:06:49.04#ibcon#[25=AT04-07\r\n] 2006.183.08:06:49.04#ibcon#*before write, iclass 15, count 2 2006.183.08:06:49.04#ibcon#enter sib2, iclass 15, count 2 2006.183.08:06:49.04#ibcon#flushed, iclass 15, count 2 2006.183.08:06:49.04#ibcon#about to write, iclass 15, count 2 2006.183.08:06:49.04#ibcon#wrote, iclass 15, count 2 2006.183.08:06:49.04#ibcon#about to read 3, iclass 15, count 2 2006.183.08:06:49.07#ibcon#read 3, iclass 15, count 2 2006.183.08:06:49.07#ibcon#about to read 4, iclass 15, count 2 2006.183.08:06:49.07#ibcon#read 4, iclass 15, count 2 2006.183.08:06:49.07#ibcon#about to read 5, iclass 15, count 2 2006.183.08:06:49.07#ibcon#read 5, iclass 15, count 2 2006.183.08:06:49.07#ibcon#about to read 6, iclass 15, count 2 2006.183.08:06:49.07#ibcon#read 6, iclass 15, count 2 2006.183.08:06:49.07#ibcon#end of sib2, iclass 15, count 2 2006.183.08:06:49.07#ibcon#*after write, iclass 15, count 2 2006.183.08:06:49.07#ibcon#*before return 0, iclass 15, count 2 2006.183.08:06:49.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:49.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:49.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.08:06:49.07#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:49.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:49.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:49.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:49.19#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:06:49.19#ibcon#first serial, iclass 15, count 0 2006.183.08:06:49.19#ibcon#enter sib2, iclass 15, count 0 2006.183.08:06:49.19#ibcon#flushed, iclass 15, count 0 2006.183.08:06:49.19#ibcon#about to write, iclass 15, count 0 2006.183.08:06:49.19#ibcon#wrote, iclass 15, count 0 2006.183.08:06:49.19#ibcon#about to read 3, iclass 15, count 0 2006.183.08:06:49.21#ibcon#read 3, iclass 15, count 0 2006.183.08:06:49.21#ibcon#about to read 4, iclass 15, count 0 2006.183.08:06:49.21#ibcon#read 4, iclass 15, count 0 2006.183.08:06:49.21#ibcon#about to read 5, iclass 15, count 0 2006.183.08:06:49.21#ibcon#read 5, iclass 15, count 0 2006.183.08:06:49.21#ibcon#about to read 6, iclass 15, count 0 2006.183.08:06:49.21#ibcon#read 6, iclass 15, count 0 2006.183.08:06:49.21#ibcon#end of sib2, iclass 15, count 0 2006.183.08:06:49.21#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:06:49.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:06:49.21#ibcon#[25=USB\r\n] 2006.183.08:06:49.21#ibcon#*before write, iclass 15, count 0 2006.183.08:06:49.21#ibcon#enter sib2, iclass 15, count 0 2006.183.08:06:49.21#ibcon#flushed, iclass 15, count 0 2006.183.08:06:49.21#ibcon#about to write, iclass 15, count 0 2006.183.08:06:49.21#ibcon#wrote, iclass 15, count 0 2006.183.08:06:49.21#ibcon#about to read 3, iclass 15, count 0 2006.183.08:06:49.24#ibcon#read 3, iclass 15, count 0 2006.183.08:06:49.24#ibcon#about to read 4, iclass 15, count 0 2006.183.08:06:49.24#ibcon#read 4, iclass 15, count 0 2006.183.08:06:49.24#ibcon#about to read 5, iclass 15, count 0 2006.183.08:06:49.24#ibcon#read 5, iclass 15, count 0 2006.183.08:06:49.24#ibcon#about to read 6, iclass 15, count 0 2006.183.08:06:49.24#ibcon#read 6, iclass 15, count 0 2006.183.08:06:49.24#ibcon#end of sib2, iclass 15, count 0 2006.183.08:06:49.24#ibcon#*after write, iclass 15, count 0 2006.183.08:06:49.24#ibcon#*before return 0, iclass 15, count 0 2006.183.08:06:49.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:49.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:49.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:06:49.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:06:49.24$vc4f8/valo=5,652.99 2006.183.08:06:49.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.08:06:49.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.08:06:49.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:49.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:49.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:49.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:49.24#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:06:49.24#ibcon#first serial, iclass 17, count 0 2006.183.08:06:49.24#ibcon#enter sib2, iclass 17, count 0 2006.183.08:06:49.24#ibcon#flushed, iclass 17, count 0 2006.183.08:06:49.24#ibcon#about to write, iclass 17, count 0 2006.183.08:06:49.24#ibcon#wrote, iclass 17, count 0 2006.183.08:06:49.24#ibcon#about to read 3, iclass 17, count 0 2006.183.08:06:49.26#ibcon#read 3, iclass 17, count 0 2006.183.08:06:49.26#ibcon#about to read 4, iclass 17, count 0 2006.183.08:06:49.26#ibcon#read 4, iclass 17, count 0 2006.183.08:06:49.26#ibcon#about to read 5, iclass 17, count 0 2006.183.08:06:49.26#ibcon#read 5, iclass 17, count 0 2006.183.08:06:49.26#ibcon#about to read 6, iclass 17, count 0 2006.183.08:06:49.26#ibcon#read 6, iclass 17, count 0 2006.183.08:06:49.26#ibcon#end of sib2, iclass 17, count 0 2006.183.08:06:49.26#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:06:49.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:06:49.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:06:49.26#ibcon#*before write, iclass 17, count 0 2006.183.08:06:49.26#ibcon#enter sib2, iclass 17, count 0 2006.183.08:06:49.26#ibcon#flushed, iclass 17, count 0 2006.183.08:06:49.26#ibcon#about to write, iclass 17, count 0 2006.183.08:06:49.26#ibcon#wrote, iclass 17, count 0 2006.183.08:06:49.26#ibcon#about to read 3, iclass 17, count 0 2006.183.08:06:49.30#ibcon#read 3, iclass 17, count 0 2006.183.08:06:49.30#ibcon#about to read 4, iclass 17, count 0 2006.183.08:06:49.30#ibcon#read 4, iclass 17, count 0 2006.183.08:06:49.30#ibcon#about to read 5, iclass 17, count 0 2006.183.08:06:49.30#ibcon#read 5, iclass 17, count 0 2006.183.08:06:49.30#ibcon#about to read 6, iclass 17, count 0 2006.183.08:06:49.30#ibcon#read 6, iclass 17, count 0 2006.183.08:06:49.30#ibcon#end of sib2, iclass 17, count 0 2006.183.08:06:49.30#ibcon#*after write, iclass 17, count 0 2006.183.08:06:49.30#ibcon#*before return 0, iclass 17, count 0 2006.183.08:06:49.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:49.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:49.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:06:49.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:06:49.30$vc4f8/va=5,7 2006.183.08:06:49.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.08:06:49.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.08:06:49.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:49.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:49.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:49.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:49.36#ibcon#enter wrdev, iclass 19, count 2 2006.183.08:06:49.36#ibcon#first serial, iclass 19, count 2 2006.183.08:06:49.36#ibcon#enter sib2, iclass 19, count 2 2006.183.08:06:49.36#ibcon#flushed, iclass 19, count 2 2006.183.08:06:49.36#ibcon#about to write, iclass 19, count 2 2006.183.08:06:49.36#ibcon#wrote, iclass 19, count 2 2006.183.08:06:49.36#ibcon#about to read 3, iclass 19, count 2 2006.183.08:06:49.38#ibcon#read 3, iclass 19, count 2 2006.183.08:06:49.38#ibcon#about to read 4, iclass 19, count 2 2006.183.08:06:49.38#ibcon#read 4, iclass 19, count 2 2006.183.08:06:49.38#ibcon#about to read 5, iclass 19, count 2 2006.183.08:06:49.38#ibcon#read 5, iclass 19, count 2 2006.183.08:06:49.38#ibcon#about to read 6, iclass 19, count 2 2006.183.08:06:49.38#ibcon#read 6, iclass 19, count 2 2006.183.08:06:49.38#ibcon#end of sib2, iclass 19, count 2 2006.183.08:06:49.38#ibcon#*mode == 0, iclass 19, count 2 2006.183.08:06:49.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.08:06:49.38#ibcon#[25=AT05-07\r\n] 2006.183.08:06:49.38#ibcon#*before write, iclass 19, count 2 2006.183.08:06:49.38#ibcon#enter sib2, iclass 19, count 2 2006.183.08:06:49.38#ibcon#flushed, iclass 19, count 2 2006.183.08:06:49.38#ibcon#about to write, iclass 19, count 2 2006.183.08:06:49.38#ibcon#wrote, iclass 19, count 2 2006.183.08:06:49.38#ibcon#about to read 3, iclass 19, count 2 2006.183.08:06:49.41#ibcon#read 3, iclass 19, count 2 2006.183.08:06:49.41#ibcon#about to read 4, iclass 19, count 2 2006.183.08:06:49.41#ibcon#read 4, iclass 19, count 2 2006.183.08:06:49.41#ibcon#about to read 5, iclass 19, count 2 2006.183.08:06:49.41#ibcon#read 5, iclass 19, count 2 2006.183.08:06:49.41#ibcon#about to read 6, iclass 19, count 2 2006.183.08:06:49.41#ibcon#read 6, iclass 19, count 2 2006.183.08:06:49.41#ibcon#end of sib2, iclass 19, count 2 2006.183.08:06:49.41#ibcon#*after write, iclass 19, count 2 2006.183.08:06:49.41#ibcon#*before return 0, iclass 19, count 2 2006.183.08:06:49.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:49.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:49.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.08:06:49.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:49.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:49.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:49.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:49.53#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:06:49.53#ibcon#first serial, iclass 19, count 0 2006.183.08:06:49.53#ibcon#enter sib2, iclass 19, count 0 2006.183.08:06:49.53#ibcon#flushed, iclass 19, count 0 2006.183.08:06:49.53#ibcon#about to write, iclass 19, count 0 2006.183.08:06:49.53#ibcon#wrote, iclass 19, count 0 2006.183.08:06:49.53#ibcon#about to read 3, iclass 19, count 0 2006.183.08:06:49.55#ibcon#read 3, iclass 19, count 0 2006.183.08:06:49.55#ibcon#about to read 4, iclass 19, count 0 2006.183.08:06:49.55#ibcon#read 4, iclass 19, count 0 2006.183.08:06:49.55#ibcon#about to read 5, iclass 19, count 0 2006.183.08:06:49.55#ibcon#read 5, iclass 19, count 0 2006.183.08:06:49.55#ibcon#about to read 6, iclass 19, count 0 2006.183.08:06:49.55#ibcon#read 6, iclass 19, count 0 2006.183.08:06:49.55#ibcon#end of sib2, iclass 19, count 0 2006.183.08:06:49.55#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:06:49.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:06:49.55#ibcon#[25=USB\r\n] 2006.183.08:06:49.55#ibcon#*before write, iclass 19, count 0 2006.183.08:06:49.55#ibcon#enter sib2, iclass 19, count 0 2006.183.08:06:49.55#ibcon#flushed, iclass 19, count 0 2006.183.08:06:49.55#ibcon#about to write, iclass 19, count 0 2006.183.08:06:49.55#ibcon#wrote, iclass 19, count 0 2006.183.08:06:49.55#ibcon#about to read 3, iclass 19, count 0 2006.183.08:06:49.58#ibcon#read 3, iclass 19, count 0 2006.183.08:06:49.58#ibcon#about to read 4, iclass 19, count 0 2006.183.08:06:49.58#ibcon#read 4, iclass 19, count 0 2006.183.08:06:49.58#ibcon#about to read 5, iclass 19, count 0 2006.183.08:06:49.58#ibcon#read 5, iclass 19, count 0 2006.183.08:06:49.58#ibcon#about to read 6, iclass 19, count 0 2006.183.08:06:49.58#ibcon#read 6, iclass 19, count 0 2006.183.08:06:49.58#ibcon#end of sib2, iclass 19, count 0 2006.183.08:06:49.58#ibcon#*after write, iclass 19, count 0 2006.183.08:06:49.58#ibcon#*before return 0, iclass 19, count 0 2006.183.08:06:49.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:49.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:49.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:06:49.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:06:49.58$vc4f8/valo=6,772.99 2006.183.08:06:49.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.08:06:49.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.08:06:49.58#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:49.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:49.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:49.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:49.58#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:06:49.58#ibcon#first serial, iclass 21, count 0 2006.183.08:06:49.58#ibcon#enter sib2, iclass 21, count 0 2006.183.08:06:49.58#ibcon#flushed, iclass 21, count 0 2006.183.08:06:49.58#ibcon#about to write, iclass 21, count 0 2006.183.08:06:49.58#ibcon#wrote, iclass 21, count 0 2006.183.08:06:49.58#ibcon#about to read 3, iclass 21, count 0 2006.183.08:06:49.60#ibcon#read 3, iclass 21, count 0 2006.183.08:06:49.60#ibcon#about to read 4, iclass 21, count 0 2006.183.08:06:49.60#ibcon#read 4, iclass 21, count 0 2006.183.08:06:49.60#ibcon#about to read 5, iclass 21, count 0 2006.183.08:06:49.60#ibcon#read 5, iclass 21, count 0 2006.183.08:06:49.60#ibcon#about to read 6, iclass 21, count 0 2006.183.08:06:49.60#ibcon#read 6, iclass 21, count 0 2006.183.08:06:49.60#ibcon#end of sib2, iclass 21, count 0 2006.183.08:06:49.60#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:06:49.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:06:49.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:06:49.60#ibcon#*before write, iclass 21, count 0 2006.183.08:06:49.60#ibcon#enter sib2, iclass 21, count 0 2006.183.08:06:49.60#ibcon#flushed, iclass 21, count 0 2006.183.08:06:49.60#ibcon#about to write, iclass 21, count 0 2006.183.08:06:49.60#ibcon#wrote, iclass 21, count 0 2006.183.08:06:49.60#ibcon#about to read 3, iclass 21, count 0 2006.183.08:06:49.64#ibcon#read 3, iclass 21, count 0 2006.183.08:06:49.64#ibcon#about to read 4, iclass 21, count 0 2006.183.08:06:49.64#ibcon#read 4, iclass 21, count 0 2006.183.08:06:49.64#ibcon#about to read 5, iclass 21, count 0 2006.183.08:06:49.64#ibcon#read 5, iclass 21, count 0 2006.183.08:06:49.64#ibcon#about to read 6, iclass 21, count 0 2006.183.08:06:49.64#ibcon#read 6, iclass 21, count 0 2006.183.08:06:49.64#ibcon#end of sib2, iclass 21, count 0 2006.183.08:06:49.64#ibcon#*after write, iclass 21, count 0 2006.183.08:06:49.64#ibcon#*before return 0, iclass 21, count 0 2006.183.08:06:49.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:49.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:49.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:06:49.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:06:49.64$vc4f8/va=6,6 2006.183.08:06:49.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.08:06:49.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.08:06:49.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:49.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:06:49.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:06:49.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:06:49.70#ibcon#enter wrdev, iclass 23, count 2 2006.183.08:06:49.70#ibcon#first serial, iclass 23, count 2 2006.183.08:06:49.70#ibcon#enter sib2, iclass 23, count 2 2006.183.08:06:49.70#ibcon#flushed, iclass 23, count 2 2006.183.08:06:49.70#ibcon#about to write, iclass 23, count 2 2006.183.08:06:49.70#ibcon#wrote, iclass 23, count 2 2006.183.08:06:49.70#ibcon#about to read 3, iclass 23, count 2 2006.183.08:06:49.72#ibcon#read 3, iclass 23, count 2 2006.183.08:06:49.72#ibcon#about to read 4, iclass 23, count 2 2006.183.08:06:49.72#ibcon#read 4, iclass 23, count 2 2006.183.08:06:49.72#ibcon#about to read 5, iclass 23, count 2 2006.183.08:06:49.72#ibcon#read 5, iclass 23, count 2 2006.183.08:06:49.72#ibcon#about to read 6, iclass 23, count 2 2006.183.08:06:49.72#ibcon#read 6, iclass 23, count 2 2006.183.08:06:49.72#ibcon#end of sib2, iclass 23, count 2 2006.183.08:06:49.72#ibcon#*mode == 0, iclass 23, count 2 2006.183.08:06:49.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.08:06:49.72#ibcon#[25=AT06-06\r\n] 2006.183.08:06:49.72#ibcon#*before write, iclass 23, count 2 2006.183.08:06:49.72#ibcon#enter sib2, iclass 23, count 2 2006.183.08:06:49.72#ibcon#flushed, iclass 23, count 2 2006.183.08:06:49.72#ibcon#about to write, iclass 23, count 2 2006.183.08:06:49.72#ibcon#wrote, iclass 23, count 2 2006.183.08:06:49.72#ibcon#about to read 3, iclass 23, count 2 2006.183.08:06:49.75#ibcon#read 3, iclass 23, count 2 2006.183.08:06:49.75#ibcon#about to read 4, iclass 23, count 2 2006.183.08:06:49.75#ibcon#read 4, iclass 23, count 2 2006.183.08:06:49.75#ibcon#about to read 5, iclass 23, count 2 2006.183.08:06:49.75#ibcon#read 5, iclass 23, count 2 2006.183.08:06:49.75#ibcon#about to read 6, iclass 23, count 2 2006.183.08:06:49.75#ibcon#read 6, iclass 23, count 2 2006.183.08:06:49.75#ibcon#end of sib2, iclass 23, count 2 2006.183.08:06:49.75#ibcon#*after write, iclass 23, count 2 2006.183.08:06:49.75#ibcon#*before return 0, iclass 23, count 2 2006.183.08:06:49.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:06:49.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:06:49.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.08:06:49.75#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:49.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:06:49.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:06:49.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:06:49.87#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:06:49.87#ibcon#first serial, iclass 23, count 0 2006.183.08:06:49.87#ibcon#enter sib2, iclass 23, count 0 2006.183.08:06:49.87#ibcon#flushed, iclass 23, count 0 2006.183.08:06:49.87#ibcon#about to write, iclass 23, count 0 2006.183.08:06:49.87#ibcon#wrote, iclass 23, count 0 2006.183.08:06:49.87#ibcon#about to read 3, iclass 23, count 0 2006.183.08:06:49.89#ibcon#read 3, iclass 23, count 0 2006.183.08:06:49.89#ibcon#about to read 4, iclass 23, count 0 2006.183.08:06:49.89#ibcon#read 4, iclass 23, count 0 2006.183.08:06:49.89#ibcon#about to read 5, iclass 23, count 0 2006.183.08:06:49.89#ibcon#read 5, iclass 23, count 0 2006.183.08:06:49.89#ibcon#about to read 6, iclass 23, count 0 2006.183.08:06:49.89#ibcon#read 6, iclass 23, count 0 2006.183.08:06:49.89#ibcon#end of sib2, iclass 23, count 0 2006.183.08:06:49.89#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:06:49.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:06:49.89#ibcon#[25=USB\r\n] 2006.183.08:06:49.89#ibcon#*before write, iclass 23, count 0 2006.183.08:06:49.89#ibcon#enter sib2, iclass 23, count 0 2006.183.08:06:49.89#ibcon#flushed, iclass 23, count 0 2006.183.08:06:49.89#ibcon#about to write, iclass 23, count 0 2006.183.08:06:49.89#ibcon#wrote, iclass 23, count 0 2006.183.08:06:49.89#ibcon#about to read 3, iclass 23, count 0 2006.183.08:06:49.92#ibcon#read 3, iclass 23, count 0 2006.183.08:06:49.92#ibcon#about to read 4, iclass 23, count 0 2006.183.08:06:49.92#ibcon#read 4, iclass 23, count 0 2006.183.08:06:49.92#ibcon#about to read 5, iclass 23, count 0 2006.183.08:06:49.92#ibcon#read 5, iclass 23, count 0 2006.183.08:06:49.92#ibcon#about to read 6, iclass 23, count 0 2006.183.08:06:49.92#ibcon#read 6, iclass 23, count 0 2006.183.08:06:49.92#ibcon#end of sib2, iclass 23, count 0 2006.183.08:06:49.92#ibcon#*after write, iclass 23, count 0 2006.183.08:06:49.92#ibcon#*before return 0, iclass 23, count 0 2006.183.08:06:49.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:06:49.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:06:49.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:06:49.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:06:49.92$vc4f8/valo=7,832.99 2006.183.08:06:49.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.08:06:49.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.08:06:49.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:49.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:06:49.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:06:49.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:06:49.92#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:06:49.92#ibcon#first serial, iclass 25, count 0 2006.183.08:06:49.92#ibcon#enter sib2, iclass 25, count 0 2006.183.08:06:49.92#ibcon#flushed, iclass 25, count 0 2006.183.08:06:49.92#ibcon#about to write, iclass 25, count 0 2006.183.08:06:49.92#ibcon#wrote, iclass 25, count 0 2006.183.08:06:49.92#ibcon#about to read 3, iclass 25, count 0 2006.183.08:06:49.94#ibcon#read 3, iclass 25, count 0 2006.183.08:06:49.94#ibcon#about to read 4, iclass 25, count 0 2006.183.08:06:49.94#ibcon#read 4, iclass 25, count 0 2006.183.08:06:49.94#ibcon#about to read 5, iclass 25, count 0 2006.183.08:06:49.94#ibcon#read 5, iclass 25, count 0 2006.183.08:06:49.94#ibcon#about to read 6, iclass 25, count 0 2006.183.08:06:49.94#ibcon#read 6, iclass 25, count 0 2006.183.08:06:49.94#ibcon#end of sib2, iclass 25, count 0 2006.183.08:06:49.94#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:06:49.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:06:49.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:06:49.94#ibcon#*before write, iclass 25, count 0 2006.183.08:06:49.94#ibcon#enter sib2, iclass 25, count 0 2006.183.08:06:49.94#ibcon#flushed, iclass 25, count 0 2006.183.08:06:49.94#ibcon#about to write, iclass 25, count 0 2006.183.08:06:49.94#ibcon#wrote, iclass 25, count 0 2006.183.08:06:49.94#ibcon#about to read 3, iclass 25, count 0 2006.183.08:06:49.98#ibcon#read 3, iclass 25, count 0 2006.183.08:06:49.98#ibcon#about to read 4, iclass 25, count 0 2006.183.08:06:49.98#ibcon#read 4, iclass 25, count 0 2006.183.08:06:49.98#ibcon#about to read 5, iclass 25, count 0 2006.183.08:06:49.98#ibcon#read 5, iclass 25, count 0 2006.183.08:06:49.98#ibcon#about to read 6, iclass 25, count 0 2006.183.08:06:49.98#ibcon#read 6, iclass 25, count 0 2006.183.08:06:49.98#ibcon#end of sib2, iclass 25, count 0 2006.183.08:06:49.98#ibcon#*after write, iclass 25, count 0 2006.183.08:06:49.98#ibcon#*before return 0, iclass 25, count 0 2006.183.08:06:49.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:06:49.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:06:49.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:06:49.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:06:49.98$vc4f8/va=7,6 2006.183.08:06:49.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.08:06:49.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.08:06:49.98#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:49.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:06:50.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:06:50.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:06:50.04#ibcon#enter wrdev, iclass 27, count 2 2006.183.08:06:50.04#ibcon#first serial, iclass 27, count 2 2006.183.08:06:50.04#ibcon#enter sib2, iclass 27, count 2 2006.183.08:06:50.04#ibcon#flushed, iclass 27, count 2 2006.183.08:06:50.04#ibcon#about to write, iclass 27, count 2 2006.183.08:06:50.04#ibcon#wrote, iclass 27, count 2 2006.183.08:06:50.04#ibcon#about to read 3, iclass 27, count 2 2006.183.08:06:50.06#ibcon#read 3, iclass 27, count 2 2006.183.08:06:50.06#ibcon#about to read 4, iclass 27, count 2 2006.183.08:06:50.06#ibcon#read 4, iclass 27, count 2 2006.183.08:06:50.06#ibcon#about to read 5, iclass 27, count 2 2006.183.08:06:50.06#ibcon#read 5, iclass 27, count 2 2006.183.08:06:50.06#ibcon#about to read 6, iclass 27, count 2 2006.183.08:06:50.06#ibcon#read 6, iclass 27, count 2 2006.183.08:06:50.06#ibcon#end of sib2, iclass 27, count 2 2006.183.08:06:50.06#ibcon#*mode == 0, iclass 27, count 2 2006.183.08:06:50.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.08:06:50.06#ibcon#[25=AT07-06\r\n] 2006.183.08:06:50.06#ibcon#*before write, iclass 27, count 2 2006.183.08:06:50.06#ibcon#enter sib2, iclass 27, count 2 2006.183.08:06:50.06#ibcon#flushed, iclass 27, count 2 2006.183.08:06:50.06#ibcon#about to write, iclass 27, count 2 2006.183.08:06:50.06#ibcon#wrote, iclass 27, count 2 2006.183.08:06:50.06#ibcon#about to read 3, iclass 27, count 2 2006.183.08:06:50.09#ibcon#read 3, iclass 27, count 2 2006.183.08:06:50.09#ibcon#about to read 4, iclass 27, count 2 2006.183.08:06:50.09#ibcon#read 4, iclass 27, count 2 2006.183.08:06:50.09#ibcon#about to read 5, iclass 27, count 2 2006.183.08:06:50.09#ibcon#read 5, iclass 27, count 2 2006.183.08:06:50.09#ibcon#about to read 6, iclass 27, count 2 2006.183.08:06:50.09#ibcon#read 6, iclass 27, count 2 2006.183.08:06:50.09#ibcon#end of sib2, iclass 27, count 2 2006.183.08:06:50.09#ibcon#*after write, iclass 27, count 2 2006.183.08:06:50.09#ibcon#*before return 0, iclass 27, count 2 2006.183.08:06:50.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:06:50.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:06:50.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.08:06:50.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:50.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:06:50.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:06:50.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:06:50.21#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:06:50.21#ibcon#first serial, iclass 27, count 0 2006.183.08:06:50.21#ibcon#enter sib2, iclass 27, count 0 2006.183.08:06:50.21#ibcon#flushed, iclass 27, count 0 2006.183.08:06:50.21#ibcon#about to write, iclass 27, count 0 2006.183.08:06:50.21#ibcon#wrote, iclass 27, count 0 2006.183.08:06:50.21#ibcon#about to read 3, iclass 27, count 0 2006.183.08:06:50.23#ibcon#read 3, iclass 27, count 0 2006.183.08:06:50.23#ibcon#about to read 4, iclass 27, count 0 2006.183.08:06:50.23#ibcon#read 4, iclass 27, count 0 2006.183.08:06:50.23#ibcon#about to read 5, iclass 27, count 0 2006.183.08:06:50.23#ibcon#read 5, iclass 27, count 0 2006.183.08:06:50.23#ibcon#about to read 6, iclass 27, count 0 2006.183.08:06:50.23#ibcon#read 6, iclass 27, count 0 2006.183.08:06:50.23#ibcon#end of sib2, iclass 27, count 0 2006.183.08:06:50.23#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:06:50.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:06:50.23#ibcon#[25=USB\r\n] 2006.183.08:06:50.23#ibcon#*before write, iclass 27, count 0 2006.183.08:06:50.23#ibcon#enter sib2, iclass 27, count 0 2006.183.08:06:50.23#ibcon#flushed, iclass 27, count 0 2006.183.08:06:50.23#ibcon#about to write, iclass 27, count 0 2006.183.08:06:50.23#ibcon#wrote, iclass 27, count 0 2006.183.08:06:50.23#ibcon#about to read 3, iclass 27, count 0 2006.183.08:06:50.26#ibcon#read 3, iclass 27, count 0 2006.183.08:06:50.26#ibcon#about to read 4, iclass 27, count 0 2006.183.08:06:50.26#ibcon#read 4, iclass 27, count 0 2006.183.08:06:50.26#ibcon#about to read 5, iclass 27, count 0 2006.183.08:06:50.26#ibcon#read 5, iclass 27, count 0 2006.183.08:06:50.26#ibcon#about to read 6, iclass 27, count 0 2006.183.08:06:50.26#ibcon#read 6, iclass 27, count 0 2006.183.08:06:50.26#ibcon#end of sib2, iclass 27, count 0 2006.183.08:06:50.26#ibcon#*after write, iclass 27, count 0 2006.183.08:06:50.26#ibcon#*before return 0, iclass 27, count 0 2006.183.08:06:50.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:06:50.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:06:50.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:06:50.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:06:50.26$vc4f8/valo=8,852.99 2006.183.08:06:50.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.08:06:50.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.08:06:50.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:50.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:06:50.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:06:50.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:06:50.26#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:06:50.26#ibcon#first serial, iclass 29, count 0 2006.183.08:06:50.26#ibcon#enter sib2, iclass 29, count 0 2006.183.08:06:50.26#ibcon#flushed, iclass 29, count 0 2006.183.08:06:50.26#ibcon#about to write, iclass 29, count 0 2006.183.08:06:50.26#ibcon#wrote, iclass 29, count 0 2006.183.08:06:50.26#ibcon#about to read 3, iclass 29, count 0 2006.183.08:06:50.28#ibcon#read 3, iclass 29, count 0 2006.183.08:06:50.28#ibcon#about to read 4, iclass 29, count 0 2006.183.08:06:50.28#ibcon#read 4, iclass 29, count 0 2006.183.08:06:50.28#ibcon#about to read 5, iclass 29, count 0 2006.183.08:06:50.28#ibcon#read 5, iclass 29, count 0 2006.183.08:06:50.28#ibcon#about to read 6, iclass 29, count 0 2006.183.08:06:50.28#ibcon#read 6, iclass 29, count 0 2006.183.08:06:50.28#ibcon#end of sib2, iclass 29, count 0 2006.183.08:06:50.28#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:06:50.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:06:50.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:06:50.28#ibcon#*before write, iclass 29, count 0 2006.183.08:06:50.28#ibcon#enter sib2, iclass 29, count 0 2006.183.08:06:50.28#ibcon#flushed, iclass 29, count 0 2006.183.08:06:50.28#ibcon#about to write, iclass 29, count 0 2006.183.08:06:50.28#ibcon#wrote, iclass 29, count 0 2006.183.08:06:50.28#ibcon#about to read 3, iclass 29, count 0 2006.183.08:06:50.32#ibcon#read 3, iclass 29, count 0 2006.183.08:06:50.32#ibcon#about to read 4, iclass 29, count 0 2006.183.08:06:50.32#ibcon#read 4, iclass 29, count 0 2006.183.08:06:50.32#ibcon#about to read 5, iclass 29, count 0 2006.183.08:06:50.32#ibcon#read 5, iclass 29, count 0 2006.183.08:06:50.32#ibcon#about to read 6, iclass 29, count 0 2006.183.08:06:50.32#ibcon#read 6, iclass 29, count 0 2006.183.08:06:50.32#ibcon#end of sib2, iclass 29, count 0 2006.183.08:06:50.32#ibcon#*after write, iclass 29, count 0 2006.183.08:06:50.32#ibcon#*before return 0, iclass 29, count 0 2006.183.08:06:50.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:06:50.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:06:50.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:06:50.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:06:50.32$vc4f8/va=8,7 2006.183.08:06:50.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.08:06:50.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.08:06:50.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:50.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:06:50.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:06:50.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:06:50.38#ibcon#enter wrdev, iclass 31, count 2 2006.183.08:06:50.38#ibcon#first serial, iclass 31, count 2 2006.183.08:06:50.38#ibcon#enter sib2, iclass 31, count 2 2006.183.08:06:50.38#ibcon#flushed, iclass 31, count 2 2006.183.08:06:50.38#ibcon#about to write, iclass 31, count 2 2006.183.08:06:50.38#ibcon#wrote, iclass 31, count 2 2006.183.08:06:50.38#ibcon#about to read 3, iclass 31, count 2 2006.183.08:06:50.40#ibcon#read 3, iclass 31, count 2 2006.183.08:06:50.40#ibcon#about to read 4, iclass 31, count 2 2006.183.08:06:50.40#ibcon#read 4, iclass 31, count 2 2006.183.08:06:50.40#ibcon#about to read 5, iclass 31, count 2 2006.183.08:06:50.40#ibcon#read 5, iclass 31, count 2 2006.183.08:06:50.40#ibcon#about to read 6, iclass 31, count 2 2006.183.08:06:50.40#ibcon#read 6, iclass 31, count 2 2006.183.08:06:50.40#ibcon#end of sib2, iclass 31, count 2 2006.183.08:06:50.40#ibcon#*mode == 0, iclass 31, count 2 2006.183.08:06:50.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.08:06:50.40#ibcon#[25=AT08-07\r\n] 2006.183.08:06:50.40#ibcon#*before write, iclass 31, count 2 2006.183.08:06:50.40#ibcon#enter sib2, iclass 31, count 2 2006.183.08:06:50.40#ibcon#flushed, iclass 31, count 2 2006.183.08:06:50.40#ibcon#about to write, iclass 31, count 2 2006.183.08:06:50.40#ibcon#wrote, iclass 31, count 2 2006.183.08:06:50.40#ibcon#about to read 3, iclass 31, count 2 2006.183.08:06:50.43#ibcon#read 3, iclass 31, count 2 2006.183.08:06:50.43#ibcon#about to read 4, iclass 31, count 2 2006.183.08:06:50.43#ibcon#read 4, iclass 31, count 2 2006.183.08:06:50.43#ibcon#about to read 5, iclass 31, count 2 2006.183.08:06:50.43#ibcon#read 5, iclass 31, count 2 2006.183.08:06:50.43#ibcon#about to read 6, iclass 31, count 2 2006.183.08:06:50.43#ibcon#read 6, iclass 31, count 2 2006.183.08:06:50.43#ibcon#end of sib2, iclass 31, count 2 2006.183.08:06:50.43#ibcon#*after write, iclass 31, count 2 2006.183.08:06:50.43#ibcon#*before return 0, iclass 31, count 2 2006.183.08:06:50.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:06:50.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:06:50.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.08:06:50.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:50.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:06:50.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:06:50.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:06:50.55#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:06:50.55#ibcon#first serial, iclass 31, count 0 2006.183.08:06:50.55#ibcon#enter sib2, iclass 31, count 0 2006.183.08:06:50.55#ibcon#flushed, iclass 31, count 0 2006.183.08:06:50.55#ibcon#about to write, iclass 31, count 0 2006.183.08:06:50.55#ibcon#wrote, iclass 31, count 0 2006.183.08:06:50.55#ibcon#about to read 3, iclass 31, count 0 2006.183.08:06:50.57#ibcon#read 3, iclass 31, count 0 2006.183.08:06:50.57#ibcon#about to read 4, iclass 31, count 0 2006.183.08:06:50.57#ibcon#read 4, iclass 31, count 0 2006.183.08:06:50.57#ibcon#about to read 5, iclass 31, count 0 2006.183.08:06:50.57#ibcon#read 5, iclass 31, count 0 2006.183.08:06:50.57#ibcon#about to read 6, iclass 31, count 0 2006.183.08:06:50.57#ibcon#read 6, iclass 31, count 0 2006.183.08:06:50.57#ibcon#end of sib2, iclass 31, count 0 2006.183.08:06:50.57#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:06:50.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:06:50.57#ibcon#[25=USB\r\n] 2006.183.08:06:50.57#ibcon#*before write, iclass 31, count 0 2006.183.08:06:50.57#ibcon#enter sib2, iclass 31, count 0 2006.183.08:06:50.57#ibcon#flushed, iclass 31, count 0 2006.183.08:06:50.57#ibcon#about to write, iclass 31, count 0 2006.183.08:06:50.57#ibcon#wrote, iclass 31, count 0 2006.183.08:06:50.57#ibcon#about to read 3, iclass 31, count 0 2006.183.08:06:50.60#ibcon#read 3, iclass 31, count 0 2006.183.08:06:50.60#ibcon#about to read 4, iclass 31, count 0 2006.183.08:06:50.60#ibcon#read 4, iclass 31, count 0 2006.183.08:06:50.60#ibcon#about to read 5, iclass 31, count 0 2006.183.08:06:50.60#ibcon#read 5, iclass 31, count 0 2006.183.08:06:50.60#ibcon#about to read 6, iclass 31, count 0 2006.183.08:06:50.60#ibcon#read 6, iclass 31, count 0 2006.183.08:06:50.60#ibcon#end of sib2, iclass 31, count 0 2006.183.08:06:50.60#ibcon#*after write, iclass 31, count 0 2006.183.08:06:50.60#ibcon#*before return 0, iclass 31, count 0 2006.183.08:06:50.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:06:50.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:06:50.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:06:50.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:06:50.60$vc4f8/vblo=1,632.99 2006.183.08:06:50.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.08:06:50.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.08:06:50.60#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:50.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:06:50.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:06:50.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:06:50.60#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:06:50.60#ibcon#first serial, iclass 33, count 0 2006.183.08:06:50.60#ibcon#enter sib2, iclass 33, count 0 2006.183.08:06:50.60#ibcon#flushed, iclass 33, count 0 2006.183.08:06:50.60#ibcon#about to write, iclass 33, count 0 2006.183.08:06:50.60#ibcon#wrote, iclass 33, count 0 2006.183.08:06:50.60#ibcon#about to read 3, iclass 33, count 0 2006.183.08:06:50.62#ibcon#read 3, iclass 33, count 0 2006.183.08:06:50.62#ibcon#about to read 4, iclass 33, count 0 2006.183.08:06:50.62#ibcon#read 4, iclass 33, count 0 2006.183.08:06:50.62#ibcon#about to read 5, iclass 33, count 0 2006.183.08:06:50.62#ibcon#read 5, iclass 33, count 0 2006.183.08:06:50.62#ibcon#about to read 6, iclass 33, count 0 2006.183.08:06:50.62#ibcon#read 6, iclass 33, count 0 2006.183.08:06:50.62#ibcon#end of sib2, iclass 33, count 0 2006.183.08:06:50.62#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:06:50.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:06:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:06:50.62#ibcon#*before write, iclass 33, count 0 2006.183.08:06:50.62#ibcon#enter sib2, iclass 33, count 0 2006.183.08:06:50.62#ibcon#flushed, iclass 33, count 0 2006.183.08:06:50.62#ibcon#about to write, iclass 33, count 0 2006.183.08:06:50.62#ibcon#wrote, iclass 33, count 0 2006.183.08:06:50.62#ibcon#about to read 3, iclass 33, count 0 2006.183.08:06:50.66#ibcon#read 3, iclass 33, count 0 2006.183.08:06:50.66#ibcon#about to read 4, iclass 33, count 0 2006.183.08:06:50.66#ibcon#read 4, iclass 33, count 0 2006.183.08:06:50.66#ibcon#about to read 5, iclass 33, count 0 2006.183.08:06:50.66#ibcon#read 5, iclass 33, count 0 2006.183.08:06:50.66#ibcon#about to read 6, iclass 33, count 0 2006.183.08:06:50.66#ibcon#read 6, iclass 33, count 0 2006.183.08:06:50.66#ibcon#end of sib2, iclass 33, count 0 2006.183.08:06:50.66#ibcon#*after write, iclass 33, count 0 2006.183.08:06:50.66#ibcon#*before return 0, iclass 33, count 0 2006.183.08:06:50.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:06:50.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:06:50.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:06:50.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:06:50.66$vc4f8/vb=1,4 2006.183.08:06:50.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.183.08:06:50.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.183.08:06:50.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:50.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:06:50.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:06:50.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:06:50.66#ibcon#enter wrdev, iclass 35, count 2 2006.183.08:06:50.66#ibcon#first serial, iclass 35, count 2 2006.183.08:06:50.66#ibcon#enter sib2, iclass 35, count 2 2006.183.08:06:50.66#ibcon#flushed, iclass 35, count 2 2006.183.08:06:50.66#ibcon#about to write, iclass 35, count 2 2006.183.08:06:50.66#ibcon#wrote, iclass 35, count 2 2006.183.08:06:50.66#ibcon#about to read 3, iclass 35, count 2 2006.183.08:06:50.68#ibcon#read 3, iclass 35, count 2 2006.183.08:06:50.68#ibcon#about to read 4, iclass 35, count 2 2006.183.08:06:50.68#ibcon#read 4, iclass 35, count 2 2006.183.08:06:50.68#ibcon#about to read 5, iclass 35, count 2 2006.183.08:06:50.68#ibcon#read 5, iclass 35, count 2 2006.183.08:06:50.68#ibcon#about to read 6, iclass 35, count 2 2006.183.08:06:50.68#ibcon#read 6, iclass 35, count 2 2006.183.08:06:50.68#ibcon#end of sib2, iclass 35, count 2 2006.183.08:06:50.68#ibcon#*mode == 0, iclass 35, count 2 2006.183.08:06:50.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.183.08:06:50.68#ibcon#[27=AT01-04\r\n] 2006.183.08:06:50.68#ibcon#*before write, iclass 35, count 2 2006.183.08:06:50.68#ibcon#enter sib2, iclass 35, count 2 2006.183.08:06:50.68#ibcon#flushed, iclass 35, count 2 2006.183.08:06:50.68#ibcon#about to write, iclass 35, count 2 2006.183.08:06:50.68#ibcon#wrote, iclass 35, count 2 2006.183.08:06:50.68#ibcon#about to read 3, iclass 35, count 2 2006.183.08:06:50.71#ibcon#read 3, iclass 35, count 2 2006.183.08:06:50.71#ibcon#about to read 4, iclass 35, count 2 2006.183.08:06:50.71#ibcon#read 4, iclass 35, count 2 2006.183.08:06:50.71#ibcon#about to read 5, iclass 35, count 2 2006.183.08:06:50.71#ibcon#read 5, iclass 35, count 2 2006.183.08:06:50.71#ibcon#about to read 6, iclass 35, count 2 2006.183.08:06:50.71#ibcon#read 6, iclass 35, count 2 2006.183.08:06:50.71#ibcon#end of sib2, iclass 35, count 2 2006.183.08:06:50.71#ibcon#*after write, iclass 35, count 2 2006.183.08:06:50.71#ibcon#*before return 0, iclass 35, count 2 2006.183.08:06:50.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:06:50.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:06:50.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.183.08:06:50.71#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:50.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:06:50.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:06:50.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:06:50.83#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:06:50.83#ibcon#first serial, iclass 35, count 0 2006.183.08:06:50.83#ibcon#enter sib2, iclass 35, count 0 2006.183.08:06:50.83#ibcon#flushed, iclass 35, count 0 2006.183.08:06:50.83#ibcon#about to write, iclass 35, count 0 2006.183.08:06:50.83#ibcon#wrote, iclass 35, count 0 2006.183.08:06:50.83#ibcon#about to read 3, iclass 35, count 0 2006.183.08:06:50.85#ibcon#read 3, iclass 35, count 0 2006.183.08:06:50.85#ibcon#about to read 4, iclass 35, count 0 2006.183.08:06:50.85#ibcon#read 4, iclass 35, count 0 2006.183.08:06:50.85#ibcon#about to read 5, iclass 35, count 0 2006.183.08:06:50.85#ibcon#read 5, iclass 35, count 0 2006.183.08:06:50.85#ibcon#about to read 6, iclass 35, count 0 2006.183.08:06:50.85#ibcon#read 6, iclass 35, count 0 2006.183.08:06:50.85#ibcon#end of sib2, iclass 35, count 0 2006.183.08:06:50.85#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:06:50.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:06:50.85#ibcon#[27=USB\r\n] 2006.183.08:06:50.85#ibcon#*before write, iclass 35, count 0 2006.183.08:06:50.85#ibcon#enter sib2, iclass 35, count 0 2006.183.08:06:50.85#ibcon#flushed, iclass 35, count 0 2006.183.08:06:50.85#ibcon#about to write, iclass 35, count 0 2006.183.08:06:50.85#ibcon#wrote, iclass 35, count 0 2006.183.08:06:50.85#ibcon#about to read 3, iclass 35, count 0 2006.183.08:06:50.88#ibcon#read 3, iclass 35, count 0 2006.183.08:06:50.88#ibcon#about to read 4, iclass 35, count 0 2006.183.08:06:50.88#ibcon#read 4, iclass 35, count 0 2006.183.08:06:50.88#ibcon#about to read 5, iclass 35, count 0 2006.183.08:06:50.88#ibcon#read 5, iclass 35, count 0 2006.183.08:06:50.88#ibcon#about to read 6, iclass 35, count 0 2006.183.08:06:50.88#ibcon#read 6, iclass 35, count 0 2006.183.08:06:50.88#ibcon#end of sib2, iclass 35, count 0 2006.183.08:06:50.88#ibcon#*after write, iclass 35, count 0 2006.183.08:06:50.88#ibcon#*before return 0, iclass 35, count 0 2006.183.08:06:50.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:06:50.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:06:50.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:06:50.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:06:50.88$vc4f8/vblo=2,640.99 2006.183.08:06:50.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.08:06:50.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.08:06:50.88#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:50.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:50.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:50.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:50.88#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:06:50.88#ibcon#first serial, iclass 37, count 0 2006.183.08:06:50.88#ibcon#enter sib2, iclass 37, count 0 2006.183.08:06:50.88#ibcon#flushed, iclass 37, count 0 2006.183.08:06:50.88#ibcon#about to write, iclass 37, count 0 2006.183.08:06:50.88#ibcon#wrote, iclass 37, count 0 2006.183.08:06:50.88#ibcon#about to read 3, iclass 37, count 0 2006.183.08:06:50.90#ibcon#read 3, iclass 37, count 0 2006.183.08:06:50.90#ibcon#about to read 4, iclass 37, count 0 2006.183.08:06:50.90#ibcon#read 4, iclass 37, count 0 2006.183.08:06:50.90#ibcon#about to read 5, iclass 37, count 0 2006.183.08:06:50.90#ibcon#read 5, iclass 37, count 0 2006.183.08:06:50.90#ibcon#about to read 6, iclass 37, count 0 2006.183.08:06:50.90#ibcon#read 6, iclass 37, count 0 2006.183.08:06:50.90#ibcon#end of sib2, iclass 37, count 0 2006.183.08:06:50.90#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:06:50.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:06:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:06:50.90#ibcon#*before write, iclass 37, count 0 2006.183.08:06:50.90#ibcon#enter sib2, iclass 37, count 0 2006.183.08:06:50.90#ibcon#flushed, iclass 37, count 0 2006.183.08:06:50.90#ibcon#about to write, iclass 37, count 0 2006.183.08:06:50.90#ibcon#wrote, iclass 37, count 0 2006.183.08:06:50.90#ibcon#about to read 3, iclass 37, count 0 2006.183.08:06:50.94#ibcon#read 3, iclass 37, count 0 2006.183.08:06:50.94#ibcon#about to read 4, iclass 37, count 0 2006.183.08:06:50.94#ibcon#read 4, iclass 37, count 0 2006.183.08:06:50.94#ibcon#about to read 5, iclass 37, count 0 2006.183.08:06:50.94#ibcon#read 5, iclass 37, count 0 2006.183.08:06:50.94#ibcon#about to read 6, iclass 37, count 0 2006.183.08:06:50.94#ibcon#read 6, iclass 37, count 0 2006.183.08:06:50.94#ibcon#end of sib2, iclass 37, count 0 2006.183.08:06:50.94#ibcon#*after write, iclass 37, count 0 2006.183.08:06:50.94#ibcon#*before return 0, iclass 37, count 0 2006.183.08:06:50.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:50.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:06:50.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:06:50.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:06:50.94$vc4f8/vb=2,4 2006.183.08:06:50.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.08:06:50.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.08:06:50.94#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:50.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:51.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:51.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:51.00#ibcon#enter wrdev, iclass 39, count 2 2006.183.08:06:51.00#ibcon#first serial, iclass 39, count 2 2006.183.08:06:51.00#ibcon#enter sib2, iclass 39, count 2 2006.183.08:06:51.00#ibcon#flushed, iclass 39, count 2 2006.183.08:06:51.00#ibcon#about to write, iclass 39, count 2 2006.183.08:06:51.00#ibcon#wrote, iclass 39, count 2 2006.183.08:06:51.00#ibcon#about to read 3, iclass 39, count 2 2006.183.08:06:51.02#ibcon#read 3, iclass 39, count 2 2006.183.08:06:51.02#ibcon#about to read 4, iclass 39, count 2 2006.183.08:06:51.02#ibcon#read 4, iclass 39, count 2 2006.183.08:06:51.02#ibcon#about to read 5, iclass 39, count 2 2006.183.08:06:51.02#ibcon#read 5, iclass 39, count 2 2006.183.08:06:51.02#ibcon#about to read 6, iclass 39, count 2 2006.183.08:06:51.02#ibcon#read 6, iclass 39, count 2 2006.183.08:06:51.02#ibcon#end of sib2, iclass 39, count 2 2006.183.08:06:51.02#ibcon#*mode == 0, iclass 39, count 2 2006.183.08:06:51.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.08:06:51.02#ibcon#[27=AT02-04\r\n] 2006.183.08:06:51.02#ibcon#*before write, iclass 39, count 2 2006.183.08:06:51.02#ibcon#enter sib2, iclass 39, count 2 2006.183.08:06:51.02#ibcon#flushed, iclass 39, count 2 2006.183.08:06:51.02#ibcon#about to write, iclass 39, count 2 2006.183.08:06:51.02#ibcon#wrote, iclass 39, count 2 2006.183.08:06:51.02#ibcon#about to read 3, iclass 39, count 2 2006.183.08:06:51.05#ibcon#read 3, iclass 39, count 2 2006.183.08:06:51.05#ibcon#about to read 4, iclass 39, count 2 2006.183.08:06:51.05#ibcon#read 4, iclass 39, count 2 2006.183.08:06:51.05#ibcon#about to read 5, iclass 39, count 2 2006.183.08:06:51.05#ibcon#read 5, iclass 39, count 2 2006.183.08:06:51.05#ibcon#about to read 6, iclass 39, count 2 2006.183.08:06:51.05#ibcon#read 6, iclass 39, count 2 2006.183.08:06:51.05#ibcon#end of sib2, iclass 39, count 2 2006.183.08:06:51.05#ibcon#*after write, iclass 39, count 2 2006.183.08:06:51.05#ibcon#*before return 0, iclass 39, count 2 2006.183.08:06:51.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:51.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:06:51.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.08:06:51.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:51.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:51.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:51.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:51.17#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:06:51.17#ibcon#first serial, iclass 39, count 0 2006.183.08:06:51.17#ibcon#enter sib2, iclass 39, count 0 2006.183.08:06:51.17#ibcon#flushed, iclass 39, count 0 2006.183.08:06:51.17#ibcon#about to write, iclass 39, count 0 2006.183.08:06:51.17#ibcon#wrote, iclass 39, count 0 2006.183.08:06:51.17#ibcon#about to read 3, iclass 39, count 0 2006.183.08:06:51.19#ibcon#read 3, iclass 39, count 0 2006.183.08:06:51.19#ibcon#about to read 4, iclass 39, count 0 2006.183.08:06:51.19#ibcon#read 4, iclass 39, count 0 2006.183.08:06:51.19#ibcon#about to read 5, iclass 39, count 0 2006.183.08:06:51.19#ibcon#read 5, iclass 39, count 0 2006.183.08:06:51.19#ibcon#about to read 6, iclass 39, count 0 2006.183.08:06:51.19#ibcon#read 6, iclass 39, count 0 2006.183.08:06:51.19#ibcon#end of sib2, iclass 39, count 0 2006.183.08:06:51.19#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:06:51.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:06:51.19#ibcon#[27=USB\r\n] 2006.183.08:06:51.19#ibcon#*before write, iclass 39, count 0 2006.183.08:06:51.19#ibcon#enter sib2, iclass 39, count 0 2006.183.08:06:51.19#ibcon#flushed, iclass 39, count 0 2006.183.08:06:51.19#ibcon#about to write, iclass 39, count 0 2006.183.08:06:51.19#ibcon#wrote, iclass 39, count 0 2006.183.08:06:51.19#ibcon#about to read 3, iclass 39, count 0 2006.183.08:06:51.22#ibcon#read 3, iclass 39, count 0 2006.183.08:06:51.22#ibcon#about to read 4, iclass 39, count 0 2006.183.08:06:51.22#ibcon#read 4, iclass 39, count 0 2006.183.08:06:51.22#ibcon#about to read 5, iclass 39, count 0 2006.183.08:06:51.22#ibcon#read 5, iclass 39, count 0 2006.183.08:06:51.22#ibcon#about to read 6, iclass 39, count 0 2006.183.08:06:51.22#ibcon#read 6, iclass 39, count 0 2006.183.08:06:51.22#ibcon#end of sib2, iclass 39, count 0 2006.183.08:06:51.22#ibcon#*after write, iclass 39, count 0 2006.183.08:06:51.22#ibcon#*before return 0, iclass 39, count 0 2006.183.08:06:51.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:51.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:06:51.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:06:51.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:06:51.22$vc4f8/vblo=3,656.99 2006.183.08:06:51.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:06:51.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:06:51.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:51.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:51.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:51.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:51.22#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:06:51.22#ibcon#first serial, iclass 3, count 0 2006.183.08:06:51.22#ibcon#enter sib2, iclass 3, count 0 2006.183.08:06:51.22#ibcon#flushed, iclass 3, count 0 2006.183.08:06:51.22#ibcon#about to write, iclass 3, count 0 2006.183.08:06:51.22#ibcon#wrote, iclass 3, count 0 2006.183.08:06:51.22#ibcon#about to read 3, iclass 3, count 0 2006.183.08:06:51.24#ibcon#read 3, iclass 3, count 0 2006.183.08:06:51.24#ibcon#about to read 4, iclass 3, count 0 2006.183.08:06:51.24#ibcon#read 4, iclass 3, count 0 2006.183.08:06:51.24#ibcon#about to read 5, iclass 3, count 0 2006.183.08:06:51.24#ibcon#read 5, iclass 3, count 0 2006.183.08:06:51.24#ibcon#about to read 6, iclass 3, count 0 2006.183.08:06:51.24#ibcon#read 6, iclass 3, count 0 2006.183.08:06:51.24#ibcon#end of sib2, iclass 3, count 0 2006.183.08:06:51.24#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:06:51.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:06:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:06:51.24#ibcon#*before write, iclass 3, count 0 2006.183.08:06:51.24#ibcon#enter sib2, iclass 3, count 0 2006.183.08:06:51.24#ibcon#flushed, iclass 3, count 0 2006.183.08:06:51.24#ibcon#about to write, iclass 3, count 0 2006.183.08:06:51.24#ibcon#wrote, iclass 3, count 0 2006.183.08:06:51.24#ibcon#about to read 3, iclass 3, count 0 2006.183.08:06:51.28#ibcon#read 3, iclass 3, count 0 2006.183.08:06:51.28#ibcon#about to read 4, iclass 3, count 0 2006.183.08:06:51.28#ibcon#read 4, iclass 3, count 0 2006.183.08:06:51.28#ibcon#about to read 5, iclass 3, count 0 2006.183.08:06:51.28#ibcon#read 5, iclass 3, count 0 2006.183.08:06:51.28#ibcon#about to read 6, iclass 3, count 0 2006.183.08:06:51.28#ibcon#read 6, iclass 3, count 0 2006.183.08:06:51.28#ibcon#end of sib2, iclass 3, count 0 2006.183.08:06:51.28#ibcon#*after write, iclass 3, count 0 2006.183.08:06:51.28#ibcon#*before return 0, iclass 3, count 0 2006.183.08:06:51.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:51.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:06:51.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:06:51.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:06:51.28$vc4f8/vb=3,4 2006.183.08:06:51.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.08:06:51.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.08:06:51.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:51.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:51.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:51.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:51.34#ibcon#enter wrdev, iclass 5, count 2 2006.183.08:06:51.34#ibcon#first serial, iclass 5, count 2 2006.183.08:06:51.34#ibcon#enter sib2, iclass 5, count 2 2006.183.08:06:51.34#ibcon#flushed, iclass 5, count 2 2006.183.08:06:51.34#ibcon#about to write, iclass 5, count 2 2006.183.08:06:51.34#ibcon#wrote, iclass 5, count 2 2006.183.08:06:51.34#ibcon#about to read 3, iclass 5, count 2 2006.183.08:06:51.36#ibcon#read 3, iclass 5, count 2 2006.183.08:06:51.36#ibcon#about to read 4, iclass 5, count 2 2006.183.08:06:51.36#ibcon#read 4, iclass 5, count 2 2006.183.08:06:51.36#ibcon#about to read 5, iclass 5, count 2 2006.183.08:06:51.36#ibcon#read 5, iclass 5, count 2 2006.183.08:06:51.36#ibcon#about to read 6, iclass 5, count 2 2006.183.08:06:51.36#ibcon#read 6, iclass 5, count 2 2006.183.08:06:51.36#ibcon#end of sib2, iclass 5, count 2 2006.183.08:06:51.36#ibcon#*mode == 0, iclass 5, count 2 2006.183.08:06:51.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.08:06:51.36#ibcon#[27=AT03-04\r\n] 2006.183.08:06:51.36#ibcon#*before write, iclass 5, count 2 2006.183.08:06:51.36#ibcon#enter sib2, iclass 5, count 2 2006.183.08:06:51.36#ibcon#flushed, iclass 5, count 2 2006.183.08:06:51.36#ibcon#about to write, iclass 5, count 2 2006.183.08:06:51.36#ibcon#wrote, iclass 5, count 2 2006.183.08:06:51.36#ibcon#about to read 3, iclass 5, count 2 2006.183.08:06:51.39#ibcon#read 3, iclass 5, count 2 2006.183.08:06:51.39#ibcon#about to read 4, iclass 5, count 2 2006.183.08:06:51.39#ibcon#read 4, iclass 5, count 2 2006.183.08:06:51.39#ibcon#about to read 5, iclass 5, count 2 2006.183.08:06:51.39#ibcon#read 5, iclass 5, count 2 2006.183.08:06:51.39#ibcon#about to read 6, iclass 5, count 2 2006.183.08:06:51.39#ibcon#read 6, iclass 5, count 2 2006.183.08:06:51.39#ibcon#end of sib2, iclass 5, count 2 2006.183.08:06:51.39#ibcon#*after write, iclass 5, count 2 2006.183.08:06:51.39#ibcon#*before return 0, iclass 5, count 2 2006.183.08:06:51.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:51.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:06:51.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.08:06:51.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:51.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:51.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:51.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:51.51#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:06:51.51#ibcon#first serial, iclass 5, count 0 2006.183.08:06:51.51#ibcon#enter sib2, iclass 5, count 0 2006.183.08:06:51.51#ibcon#flushed, iclass 5, count 0 2006.183.08:06:51.51#ibcon#about to write, iclass 5, count 0 2006.183.08:06:51.51#ibcon#wrote, iclass 5, count 0 2006.183.08:06:51.51#ibcon#about to read 3, iclass 5, count 0 2006.183.08:06:51.53#ibcon#read 3, iclass 5, count 0 2006.183.08:06:51.53#ibcon#about to read 4, iclass 5, count 0 2006.183.08:06:51.53#ibcon#read 4, iclass 5, count 0 2006.183.08:06:51.53#ibcon#about to read 5, iclass 5, count 0 2006.183.08:06:51.53#ibcon#read 5, iclass 5, count 0 2006.183.08:06:51.53#ibcon#about to read 6, iclass 5, count 0 2006.183.08:06:51.53#ibcon#read 6, iclass 5, count 0 2006.183.08:06:51.53#ibcon#end of sib2, iclass 5, count 0 2006.183.08:06:51.53#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:06:51.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:06:51.53#ibcon#[27=USB\r\n] 2006.183.08:06:51.53#ibcon#*before write, iclass 5, count 0 2006.183.08:06:51.53#ibcon#enter sib2, iclass 5, count 0 2006.183.08:06:51.53#ibcon#flushed, iclass 5, count 0 2006.183.08:06:51.53#ibcon#about to write, iclass 5, count 0 2006.183.08:06:51.53#ibcon#wrote, iclass 5, count 0 2006.183.08:06:51.53#ibcon#about to read 3, iclass 5, count 0 2006.183.08:06:51.56#ibcon#read 3, iclass 5, count 0 2006.183.08:06:51.56#ibcon#about to read 4, iclass 5, count 0 2006.183.08:06:51.56#ibcon#read 4, iclass 5, count 0 2006.183.08:06:51.56#ibcon#about to read 5, iclass 5, count 0 2006.183.08:06:51.56#ibcon#read 5, iclass 5, count 0 2006.183.08:06:51.56#ibcon#about to read 6, iclass 5, count 0 2006.183.08:06:51.56#ibcon#read 6, iclass 5, count 0 2006.183.08:06:51.56#ibcon#end of sib2, iclass 5, count 0 2006.183.08:06:51.56#ibcon#*after write, iclass 5, count 0 2006.183.08:06:51.56#ibcon#*before return 0, iclass 5, count 0 2006.183.08:06:51.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:51.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:06:51.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:06:51.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:06:51.56$vc4f8/vblo=4,712.99 2006.183.08:06:51.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.08:06:51.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.08:06:51.56#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:51.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:51.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:51.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:51.56#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:06:51.56#ibcon#first serial, iclass 7, count 0 2006.183.08:06:51.56#ibcon#enter sib2, iclass 7, count 0 2006.183.08:06:51.56#ibcon#flushed, iclass 7, count 0 2006.183.08:06:51.56#ibcon#about to write, iclass 7, count 0 2006.183.08:06:51.56#ibcon#wrote, iclass 7, count 0 2006.183.08:06:51.56#ibcon#about to read 3, iclass 7, count 0 2006.183.08:06:51.58#ibcon#read 3, iclass 7, count 0 2006.183.08:06:51.58#ibcon#about to read 4, iclass 7, count 0 2006.183.08:06:51.58#ibcon#read 4, iclass 7, count 0 2006.183.08:06:51.58#ibcon#about to read 5, iclass 7, count 0 2006.183.08:06:51.58#ibcon#read 5, iclass 7, count 0 2006.183.08:06:51.58#ibcon#about to read 6, iclass 7, count 0 2006.183.08:06:51.58#ibcon#read 6, iclass 7, count 0 2006.183.08:06:51.58#ibcon#end of sib2, iclass 7, count 0 2006.183.08:06:51.58#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:06:51.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:06:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:06:51.58#ibcon#*before write, iclass 7, count 0 2006.183.08:06:51.58#ibcon#enter sib2, iclass 7, count 0 2006.183.08:06:51.58#ibcon#flushed, iclass 7, count 0 2006.183.08:06:51.58#ibcon#about to write, iclass 7, count 0 2006.183.08:06:51.58#ibcon#wrote, iclass 7, count 0 2006.183.08:06:51.58#ibcon#about to read 3, iclass 7, count 0 2006.183.08:06:51.62#ibcon#read 3, iclass 7, count 0 2006.183.08:06:51.62#ibcon#about to read 4, iclass 7, count 0 2006.183.08:06:51.62#ibcon#read 4, iclass 7, count 0 2006.183.08:06:51.62#ibcon#about to read 5, iclass 7, count 0 2006.183.08:06:51.62#ibcon#read 5, iclass 7, count 0 2006.183.08:06:51.62#ibcon#about to read 6, iclass 7, count 0 2006.183.08:06:51.62#ibcon#read 6, iclass 7, count 0 2006.183.08:06:51.62#ibcon#end of sib2, iclass 7, count 0 2006.183.08:06:51.62#ibcon#*after write, iclass 7, count 0 2006.183.08:06:51.62#ibcon#*before return 0, iclass 7, count 0 2006.183.08:06:51.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:51.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:06:51.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:06:51.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:06:51.62$vc4f8/vb=4,4 2006.183.08:06:51.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.08:06:51.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.08:06:51.62#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:51.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:51.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:51.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:51.68#ibcon#enter wrdev, iclass 11, count 2 2006.183.08:06:51.68#ibcon#first serial, iclass 11, count 2 2006.183.08:06:51.68#ibcon#enter sib2, iclass 11, count 2 2006.183.08:06:51.68#ibcon#flushed, iclass 11, count 2 2006.183.08:06:51.68#ibcon#about to write, iclass 11, count 2 2006.183.08:06:51.68#ibcon#wrote, iclass 11, count 2 2006.183.08:06:51.68#ibcon#about to read 3, iclass 11, count 2 2006.183.08:06:51.70#ibcon#read 3, iclass 11, count 2 2006.183.08:06:51.70#ibcon#about to read 4, iclass 11, count 2 2006.183.08:06:51.70#ibcon#read 4, iclass 11, count 2 2006.183.08:06:51.70#ibcon#about to read 5, iclass 11, count 2 2006.183.08:06:51.70#ibcon#read 5, iclass 11, count 2 2006.183.08:06:51.70#ibcon#about to read 6, iclass 11, count 2 2006.183.08:06:51.70#ibcon#read 6, iclass 11, count 2 2006.183.08:06:51.70#ibcon#end of sib2, iclass 11, count 2 2006.183.08:06:51.70#ibcon#*mode == 0, iclass 11, count 2 2006.183.08:06:51.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.08:06:51.70#ibcon#[27=AT04-04\r\n] 2006.183.08:06:51.70#ibcon#*before write, iclass 11, count 2 2006.183.08:06:51.70#ibcon#enter sib2, iclass 11, count 2 2006.183.08:06:51.70#ibcon#flushed, iclass 11, count 2 2006.183.08:06:51.70#ibcon#about to write, iclass 11, count 2 2006.183.08:06:51.70#ibcon#wrote, iclass 11, count 2 2006.183.08:06:51.70#ibcon#about to read 3, iclass 11, count 2 2006.183.08:06:51.73#ibcon#read 3, iclass 11, count 2 2006.183.08:06:51.73#ibcon#about to read 4, iclass 11, count 2 2006.183.08:06:51.73#ibcon#read 4, iclass 11, count 2 2006.183.08:06:51.73#ibcon#about to read 5, iclass 11, count 2 2006.183.08:06:51.73#ibcon#read 5, iclass 11, count 2 2006.183.08:06:51.73#ibcon#about to read 6, iclass 11, count 2 2006.183.08:06:51.73#ibcon#read 6, iclass 11, count 2 2006.183.08:06:51.73#ibcon#end of sib2, iclass 11, count 2 2006.183.08:06:51.73#ibcon#*after write, iclass 11, count 2 2006.183.08:06:51.73#ibcon#*before return 0, iclass 11, count 2 2006.183.08:06:51.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:51.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:06:51.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.08:06:51.73#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:51.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:51.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:51.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:51.85#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:06:51.85#ibcon#first serial, iclass 11, count 0 2006.183.08:06:51.85#ibcon#enter sib2, iclass 11, count 0 2006.183.08:06:51.85#ibcon#flushed, iclass 11, count 0 2006.183.08:06:51.85#ibcon#about to write, iclass 11, count 0 2006.183.08:06:51.85#ibcon#wrote, iclass 11, count 0 2006.183.08:06:51.85#ibcon#about to read 3, iclass 11, count 0 2006.183.08:06:51.87#ibcon#read 3, iclass 11, count 0 2006.183.08:06:51.87#ibcon#about to read 4, iclass 11, count 0 2006.183.08:06:51.87#ibcon#read 4, iclass 11, count 0 2006.183.08:06:51.87#ibcon#about to read 5, iclass 11, count 0 2006.183.08:06:51.87#ibcon#read 5, iclass 11, count 0 2006.183.08:06:51.87#ibcon#about to read 6, iclass 11, count 0 2006.183.08:06:51.87#ibcon#read 6, iclass 11, count 0 2006.183.08:06:51.87#ibcon#end of sib2, iclass 11, count 0 2006.183.08:06:51.87#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:06:51.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:06:51.87#ibcon#[27=USB\r\n] 2006.183.08:06:51.87#ibcon#*before write, iclass 11, count 0 2006.183.08:06:51.87#ibcon#enter sib2, iclass 11, count 0 2006.183.08:06:51.87#ibcon#flushed, iclass 11, count 0 2006.183.08:06:51.87#ibcon#about to write, iclass 11, count 0 2006.183.08:06:51.87#ibcon#wrote, iclass 11, count 0 2006.183.08:06:51.87#ibcon#about to read 3, iclass 11, count 0 2006.183.08:06:51.90#ibcon#read 3, iclass 11, count 0 2006.183.08:06:51.90#ibcon#about to read 4, iclass 11, count 0 2006.183.08:06:51.90#ibcon#read 4, iclass 11, count 0 2006.183.08:06:51.90#ibcon#about to read 5, iclass 11, count 0 2006.183.08:06:51.90#ibcon#read 5, iclass 11, count 0 2006.183.08:06:51.90#ibcon#about to read 6, iclass 11, count 0 2006.183.08:06:51.90#ibcon#read 6, iclass 11, count 0 2006.183.08:06:51.90#ibcon#end of sib2, iclass 11, count 0 2006.183.08:06:51.90#ibcon#*after write, iclass 11, count 0 2006.183.08:06:51.90#ibcon#*before return 0, iclass 11, count 0 2006.183.08:06:51.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:51.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:06:51.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:06:51.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:06:51.90$vc4f8/vblo=5,744.99 2006.183.08:06:51.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.08:06:51.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.08:06:51.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:51.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:51.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:51.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:51.90#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:06:51.90#ibcon#first serial, iclass 13, count 0 2006.183.08:06:51.90#ibcon#enter sib2, iclass 13, count 0 2006.183.08:06:51.90#ibcon#flushed, iclass 13, count 0 2006.183.08:06:51.90#ibcon#about to write, iclass 13, count 0 2006.183.08:06:51.90#ibcon#wrote, iclass 13, count 0 2006.183.08:06:51.90#ibcon#about to read 3, iclass 13, count 0 2006.183.08:06:51.92#ibcon#read 3, iclass 13, count 0 2006.183.08:06:51.92#ibcon#about to read 4, iclass 13, count 0 2006.183.08:06:51.92#ibcon#read 4, iclass 13, count 0 2006.183.08:06:51.92#ibcon#about to read 5, iclass 13, count 0 2006.183.08:06:51.92#ibcon#read 5, iclass 13, count 0 2006.183.08:06:51.92#ibcon#about to read 6, iclass 13, count 0 2006.183.08:06:51.92#ibcon#read 6, iclass 13, count 0 2006.183.08:06:51.92#ibcon#end of sib2, iclass 13, count 0 2006.183.08:06:51.92#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:06:51.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:06:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:06:51.92#ibcon#*before write, iclass 13, count 0 2006.183.08:06:51.92#ibcon#enter sib2, iclass 13, count 0 2006.183.08:06:51.92#ibcon#flushed, iclass 13, count 0 2006.183.08:06:51.92#ibcon#about to write, iclass 13, count 0 2006.183.08:06:51.92#ibcon#wrote, iclass 13, count 0 2006.183.08:06:51.92#ibcon#about to read 3, iclass 13, count 0 2006.183.08:06:51.96#ibcon#read 3, iclass 13, count 0 2006.183.08:06:51.96#ibcon#about to read 4, iclass 13, count 0 2006.183.08:06:51.96#ibcon#read 4, iclass 13, count 0 2006.183.08:06:51.96#ibcon#about to read 5, iclass 13, count 0 2006.183.08:06:51.96#ibcon#read 5, iclass 13, count 0 2006.183.08:06:51.96#ibcon#about to read 6, iclass 13, count 0 2006.183.08:06:51.96#ibcon#read 6, iclass 13, count 0 2006.183.08:06:51.96#ibcon#end of sib2, iclass 13, count 0 2006.183.08:06:51.96#ibcon#*after write, iclass 13, count 0 2006.183.08:06:51.96#ibcon#*before return 0, iclass 13, count 0 2006.183.08:06:51.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:51.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:06:51.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:06:51.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:06:51.96$vc4f8/vb=5,4 2006.183.08:06:51.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.08:06:51.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.08:06:51.96#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:51.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:52.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:52.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:52.02#ibcon#enter wrdev, iclass 15, count 2 2006.183.08:06:52.02#ibcon#first serial, iclass 15, count 2 2006.183.08:06:52.02#ibcon#enter sib2, iclass 15, count 2 2006.183.08:06:52.02#ibcon#flushed, iclass 15, count 2 2006.183.08:06:52.02#ibcon#about to write, iclass 15, count 2 2006.183.08:06:52.02#ibcon#wrote, iclass 15, count 2 2006.183.08:06:52.02#ibcon#about to read 3, iclass 15, count 2 2006.183.08:06:52.04#ibcon#read 3, iclass 15, count 2 2006.183.08:06:52.04#ibcon#about to read 4, iclass 15, count 2 2006.183.08:06:52.04#ibcon#read 4, iclass 15, count 2 2006.183.08:06:52.04#ibcon#about to read 5, iclass 15, count 2 2006.183.08:06:52.04#ibcon#read 5, iclass 15, count 2 2006.183.08:06:52.04#ibcon#about to read 6, iclass 15, count 2 2006.183.08:06:52.04#ibcon#read 6, iclass 15, count 2 2006.183.08:06:52.04#ibcon#end of sib2, iclass 15, count 2 2006.183.08:06:52.04#ibcon#*mode == 0, iclass 15, count 2 2006.183.08:06:52.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.08:06:52.04#ibcon#[27=AT05-04\r\n] 2006.183.08:06:52.04#ibcon#*before write, iclass 15, count 2 2006.183.08:06:52.04#ibcon#enter sib2, iclass 15, count 2 2006.183.08:06:52.04#ibcon#flushed, iclass 15, count 2 2006.183.08:06:52.04#ibcon#about to write, iclass 15, count 2 2006.183.08:06:52.04#ibcon#wrote, iclass 15, count 2 2006.183.08:06:52.04#ibcon#about to read 3, iclass 15, count 2 2006.183.08:06:52.07#ibcon#read 3, iclass 15, count 2 2006.183.08:06:52.07#ibcon#about to read 4, iclass 15, count 2 2006.183.08:06:52.07#ibcon#read 4, iclass 15, count 2 2006.183.08:06:52.07#ibcon#about to read 5, iclass 15, count 2 2006.183.08:06:52.07#ibcon#read 5, iclass 15, count 2 2006.183.08:06:52.07#ibcon#about to read 6, iclass 15, count 2 2006.183.08:06:52.07#ibcon#read 6, iclass 15, count 2 2006.183.08:06:52.07#ibcon#end of sib2, iclass 15, count 2 2006.183.08:06:52.07#ibcon#*after write, iclass 15, count 2 2006.183.08:06:52.07#ibcon#*before return 0, iclass 15, count 2 2006.183.08:06:52.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:52.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:06:52.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.08:06:52.07#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:52.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:52.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:52.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:52.19#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:06:52.19#ibcon#first serial, iclass 15, count 0 2006.183.08:06:52.19#ibcon#enter sib2, iclass 15, count 0 2006.183.08:06:52.19#ibcon#flushed, iclass 15, count 0 2006.183.08:06:52.19#ibcon#about to write, iclass 15, count 0 2006.183.08:06:52.19#ibcon#wrote, iclass 15, count 0 2006.183.08:06:52.19#ibcon#about to read 3, iclass 15, count 0 2006.183.08:06:52.21#ibcon#read 3, iclass 15, count 0 2006.183.08:06:52.21#ibcon#about to read 4, iclass 15, count 0 2006.183.08:06:52.21#ibcon#read 4, iclass 15, count 0 2006.183.08:06:52.21#ibcon#about to read 5, iclass 15, count 0 2006.183.08:06:52.21#ibcon#read 5, iclass 15, count 0 2006.183.08:06:52.21#ibcon#about to read 6, iclass 15, count 0 2006.183.08:06:52.21#ibcon#read 6, iclass 15, count 0 2006.183.08:06:52.21#ibcon#end of sib2, iclass 15, count 0 2006.183.08:06:52.21#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:06:52.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:06:52.21#ibcon#[27=USB\r\n] 2006.183.08:06:52.21#ibcon#*before write, iclass 15, count 0 2006.183.08:06:52.21#ibcon#enter sib2, iclass 15, count 0 2006.183.08:06:52.21#ibcon#flushed, iclass 15, count 0 2006.183.08:06:52.21#ibcon#about to write, iclass 15, count 0 2006.183.08:06:52.21#ibcon#wrote, iclass 15, count 0 2006.183.08:06:52.21#ibcon#about to read 3, iclass 15, count 0 2006.183.08:06:52.24#ibcon#read 3, iclass 15, count 0 2006.183.08:06:52.24#ibcon#about to read 4, iclass 15, count 0 2006.183.08:06:52.24#ibcon#read 4, iclass 15, count 0 2006.183.08:06:52.24#ibcon#about to read 5, iclass 15, count 0 2006.183.08:06:52.24#ibcon#read 5, iclass 15, count 0 2006.183.08:06:52.24#ibcon#about to read 6, iclass 15, count 0 2006.183.08:06:52.24#ibcon#read 6, iclass 15, count 0 2006.183.08:06:52.24#ibcon#end of sib2, iclass 15, count 0 2006.183.08:06:52.24#ibcon#*after write, iclass 15, count 0 2006.183.08:06:52.24#ibcon#*before return 0, iclass 15, count 0 2006.183.08:06:52.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:52.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:06:52.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:06:52.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:06:52.24$vc4f8/vblo=6,752.99 2006.183.08:06:52.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.08:06:52.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.08:06:52.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:06:52.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:52.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:52.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:52.24#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:06:52.24#ibcon#first serial, iclass 17, count 0 2006.183.08:06:52.24#ibcon#enter sib2, iclass 17, count 0 2006.183.08:06:52.24#ibcon#flushed, iclass 17, count 0 2006.183.08:06:52.24#ibcon#about to write, iclass 17, count 0 2006.183.08:06:52.24#ibcon#wrote, iclass 17, count 0 2006.183.08:06:52.24#ibcon#about to read 3, iclass 17, count 0 2006.183.08:06:52.26#ibcon#read 3, iclass 17, count 0 2006.183.08:06:52.26#ibcon#about to read 4, iclass 17, count 0 2006.183.08:06:52.26#ibcon#read 4, iclass 17, count 0 2006.183.08:06:52.26#ibcon#about to read 5, iclass 17, count 0 2006.183.08:06:52.26#ibcon#read 5, iclass 17, count 0 2006.183.08:06:52.26#ibcon#about to read 6, iclass 17, count 0 2006.183.08:06:52.26#ibcon#read 6, iclass 17, count 0 2006.183.08:06:52.26#ibcon#end of sib2, iclass 17, count 0 2006.183.08:06:52.26#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:06:52.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:06:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:06:52.26#ibcon#*before write, iclass 17, count 0 2006.183.08:06:52.26#ibcon#enter sib2, iclass 17, count 0 2006.183.08:06:52.26#ibcon#flushed, iclass 17, count 0 2006.183.08:06:52.26#ibcon#about to write, iclass 17, count 0 2006.183.08:06:52.26#ibcon#wrote, iclass 17, count 0 2006.183.08:06:52.26#ibcon#about to read 3, iclass 17, count 0 2006.183.08:06:52.30#ibcon#read 3, iclass 17, count 0 2006.183.08:06:52.30#ibcon#about to read 4, iclass 17, count 0 2006.183.08:06:52.30#ibcon#read 4, iclass 17, count 0 2006.183.08:06:52.30#ibcon#about to read 5, iclass 17, count 0 2006.183.08:06:52.30#ibcon#read 5, iclass 17, count 0 2006.183.08:06:52.30#ibcon#about to read 6, iclass 17, count 0 2006.183.08:06:52.30#ibcon#read 6, iclass 17, count 0 2006.183.08:06:52.30#ibcon#end of sib2, iclass 17, count 0 2006.183.08:06:52.30#ibcon#*after write, iclass 17, count 0 2006.183.08:06:52.30#ibcon#*before return 0, iclass 17, count 0 2006.183.08:06:52.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:52.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:06:52.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:06:52.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:06:52.30$vc4f8/vb=6,4 2006.183.08:06:52.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.08:06:52.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.08:06:52.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:06:52.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:52.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:52.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:52.36#ibcon#enter wrdev, iclass 19, count 2 2006.183.08:06:52.36#ibcon#first serial, iclass 19, count 2 2006.183.08:06:52.36#ibcon#enter sib2, iclass 19, count 2 2006.183.08:06:52.36#ibcon#flushed, iclass 19, count 2 2006.183.08:06:52.36#ibcon#about to write, iclass 19, count 2 2006.183.08:06:52.36#ibcon#wrote, iclass 19, count 2 2006.183.08:06:52.36#ibcon#about to read 3, iclass 19, count 2 2006.183.08:06:52.38#ibcon#read 3, iclass 19, count 2 2006.183.08:06:52.38#ibcon#about to read 4, iclass 19, count 2 2006.183.08:06:52.38#ibcon#read 4, iclass 19, count 2 2006.183.08:06:52.38#ibcon#about to read 5, iclass 19, count 2 2006.183.08:06:52.38#ibcon#read 5, iclass 19, count 2 2006.183.08:06:52.38#ibcon#about to read 6, iclass 19, count 2 2006.183.08:06:52.38#ibcon#read 6, iclass 19, count 2 2006.183.08:06:52.38#ibcon#end of sib2, iclass 19, count 2 2006.183.08:06:52.38#ibcon#*mode == 0, iclass 19, count 2 2006.183.08:06:52.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.08:06:52.38#ibcon#[27=AT06-04\r\n] 2006.183.08:06:52.38#ibcon#*before write, iclass 19, count 2 2006.183.08:06:52.38#ibcon#enter sib2, iclass 19, count 2 2006.183.08:06:52.38#ibcon#flushed, iclass 19, count 2 2006.183.08:06:52.38#ibcon#about to write, iclass 19, count 2 2006.183.08:06:52.38#ibcon#wrote, iclass 19, count 2 2006.183.08:06:52.38#ibcon#about to read 3, iclass 19, count 2 2006.183.08:06:52.41#ibcon#read 3, iclass 19, count 2 2006.183.08:06:52.41#ibcon#about to read 4, iclass 19, count 2 2006.183.08:06:52.41#ibcon#read 4, iclass 19, count 2 2006.183.08:06:52.41#ibcon#about to read 5, iclass 19, count 2 2006.183.08:06:52.41#ibcon#read 5, iclass 19, count 2 2006.183.08:06:52.41#ibcon#about to read 6, iclass 19, count 2 2006.183.08:06:52.41#ibcon#read 6, iclass 19, count 2 2006.183.08:06:52.41#ibcon#end of sib2, iclass 19, count 2 2006.183.08:06:52.41#ibcon#*after write, iclass 19, count 2 2006.183.08:06:52.41#ibcon#*before return 0, iclass 19, count 2 2006.183.08:06:52.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:52.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:06:52.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.08:06:52.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:06:52.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:52.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:52.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:52.53#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:06:52.53#ibcon#first serial, iclass 19, count 0 2006.183.08:06:52.53#ibcon#enter sib2, iclass 19, count 0 2006.183.08:06:52.53#ibcon#flushed, iclass 19, count 0 2006.183.08:06:52.53#ibcon#about to write, iclass 19, count 0 2006.183.08:06:52.53#ibcon#wrote, iclass 19, count 0 2006.183.08:06:52.53#ibcon#about to read 3, iclass 19, count 0 2006.183.08:06:52.55#ibcon#read 3, iclass 19, count 0 2006.183.08:06:52.55#ibcon#about to read 4, iclass 19, count 0 2006.183.08:06:52.55#ibcon#read 4, iclass 19, count 0 2006.183.08:06:52.55#ibcon#about to read 5, iclass 19, count 0 2006.183.08:06:52.55#ibcon#read 5, iclass 19, count 0 2006.183.08:06:52.55#ibcon#about to read 6, iclass 19, count 0 2006.183.08:06:52.55#ibcon#read 6, iclass 19, count 0 2006.183.08:06:52.55#ibcon#end of sib2, iclass 19, count 0 2006.183.08:06:52.55#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:06:52.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:06:52.55#ibcon#[27=USB\r\n] 2006.183.08:06:52.55#ibcon#*before write, iclass 19, count 0 2006.183.08:06:52.55#ibcon#enter sib2, iclass 19, count 0 2006.183.08:06:52.55#ibcon#flushed, iclass 19, count 0 2006.183.08:06:52.55#ibcon#about to write, iclass 19, count 0 2006.183.08:06:52.55#ibcon#wrote, iclass 19, count 0 2006.183.08:06:52.55#ibcon#about to read 3, iclass 19, count 0 2006.183.08:06:52.58#ibcon#read 3, iclass 19, count 0 2006.183.08:06:52.58#ibcon#about to read 4, iclass 19, count 0 2006.183.08:06:52.58#ibcon#read 4, iclass 19, count 0 2006.183.08:06:52.58#ibcon#about to read 5, iclass 19, count 0 2006.183.08:06:52.58#ibcon#read 5, iclass 19, count 0 2006.183.08:06:52.58#ibcon#about to read 6, iclass 19, count 0 2006.183.08:06:52.58#ibcon#read 6, iclass 19, count 0 2006.183.08:06:52.58#ibcon#end of sib2, iclass 19, count 0 2006.183.08:06:52.58#ibcon#*after write, iclass 19, count 0 2006.183.08:06:52.58#ibcon#*before return 0, iclass 19, count 0 2006.183.08:06:52.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:52.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:06:52.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:06:52.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:06:52.58$vc4f8/vabw=wide 2006.183.08:06:52.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.08:06:52.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.08:06:52.58#ibcon#ireg 8 cls_cnt 0 2006.183.08:06:52.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:52.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:52.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:52.58#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:06:52.58#ibcon#first serial, iclass 21, count 0 2006.183.08:06:52.58#ibcon#enter sib2, iclass 21, count 0 2006.183.08:06:52.58#ibcon#flushed, iclass 21, count 0 2006.183.08:06:52.58#ibcon#about to write, iclass 21, count 0 2006.183.08:06:52.58#ibcon#wrote, iclass 21, count 0 2006.183.08:06:52.58#ibcon#about to read 3, iclass 21, count 0 2006.183.08:06:52.60#ibcon#read 3, iclass 21, count 0 2006.183.08:06:52.60#ibcon#about to read 4, iclass 21, count 0 2006.183.08:06:52.60#ibcon#read 4, iclass 21, count 0 2006.183.08:06:52.60#ibcon#about to read 5, iclass 21, count 0 2006.183.08:06:52.60#ibcon#read 5, iclass 21, count 0 2006.183.08:06:52.60#ibcon#about to read 6, iclass 21, count 0 2006.183.08:06:52.60#ibcon#read 6, iclass 21, count 0 2006.183.08:06:52.60#ibcon#end of sib2, iclass 21, count 0 2006.183.08:06:52.60#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:06:52.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:06:52.60#ibcon#[25=BW32\r\n] 2006.183.08:06:52.60#ibcon#*before write, iclass 21, count 0 2006.183.08:06:52.60#ibcon#enter sib2, iclass 21, count 0 2006.183.08:06:52.60#ibcon#flushed, iclass 21, count 0 2006.183.08:06:52.60#ibcon#about to write, iclass 21, count 0 2006.183.08:06:52.60#ibcon#wrote, iclass 21, count 0 2006.183.08:06:52.60#ibcon#about to read 3, iclass 21, count 0 2006.183.08:06:52.63#ibcon#read 3, iclass 21, count 0 2006.183.08:06:52.63#ibcon#about to read 4, iclass 21, count 0 2006.183.08:06:52.63#ibcon#read 4, iclass 21, count 0 2006.183.08:06:52.63#ibcon#about to read 5, iclass 21, count 0 2006.183.08:06:52.63#ibcon#read 5, iclass 21, count 0 2006.183.08:06:52.63#ibcon#about to read 6, iclass 21, count 0 2006.183.08:06:52.63#ibcon#read 6, iclass 21, count 0 2006.183.08:06:52.63#ibcon#end of sib2, iclass 21, count 0 2006.183.08:06:52.63#ibcon#*after write, iclass 21, count 0 2006.183.08:06:52.63#ibcon#*before return 0, iclass 21, count 0 2006.183.08:06:52.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:52.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:06:52.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:06:52.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:06:52.63$vc4f8/vbbw=wide 2006.183.08:06:52.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:06:52.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:06:52.63#ibcon#ireg 8 cls_cnt 0 2006.183.08:06:52.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:06:52.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:06:52.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:06:52.70#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:06:52.70#ibcon#first serial, iclass 23, count 0 2006.183.08:06:52.70#ibcon#enter sib2, iclass 23, count 0 2006.183.08:06:52.70#ibcon#flushed, iclass 23, count 0 2006.183.08:06:52.70#ibcon#about to write, iclass 23, count 0 2006.183.08:06:52.70#ibcon#wrote, iclass 23, count 0 2006.183.08:06:52.70#ibcon#about to read 3, iclass 23, count 0 2006.183.08:06:52.72#ibcon#read 3, iclass 23, count 0 2006.183.08:06:52.72#ibcon#about to read 4, iclass 23, count 0 2006.183.08:06:52.72#ibcon#read 4, iclass 23, count 0 2006.183.08:06:52.72#ibcon#about to read 5, iclass 23, count 0 2006.183.08:06:52.72#ibcon#read 5, iclass 23, count 0 2006.183.08:06:52.72#ibcon#about to read 6, iclass 23, count 0 2006.183.08:06:52.72#ibcon#read 6, iclass 23, count 0 2006.183.08:06:52.72#ibcon#end of sib2, iclass 23, count 0 2006.183.08:06:52.72#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:06:52.72#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:06:52.72#ibcon#[27=BW32\r\n] 2006.183.08:06:52.72#ibcon#*before write, iclass 23, count 0 2006.183.08:06:52.72#ibcon#enter sib2, iclass 23, count 0 2006.183.08:06:52.72#ibcon#flushed, iclass 23, count 0 2006.183.08:06:52.72#ibcon#about to write, iclass 23, count 0 2006.183.08:06:52.72#ibcon#wrote, iclass 23, count 0 2006.183.08:06:52.72#ibcon#about to read 3, iclass 23, count 0 2006.183.08:06:52.75#ibcon#read 3, iclass 23, count 0 2006.183.08:06:52.75#ibcon#about to read 4, iclass 23, count 0 2006.183.08:06:52.75#ibcon#read 4, iclass 23, count 0 2006.183.08:06:52.75#ibcon#about to read 5, iclass 23, count 0 2006.183.08:06:52.75#ibcon#read 5, iclass 23, count 0 2006.183.08:06:52.75#ibcon#about to read 6, iclass 23, count 0 2006.183.08:06:52.75#ibcon#read 6, iclass 23, count 0 2006.183.08:06:52.75#ibcon#end of sib2, iclass 23, count 0 2006.183.08:06:52.75#ibcon#*after write, iclass 23, count 0 2006.183.08:06:52.75#ibcon#*before return 0, iclass 23, count 0 2006.183.08:06:52.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:06:52.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:06:52.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:06:52.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:06:52.75$4f8m12a/ifd4f 2006.183.08:06:52.75$ifd4f/lo= 2006.183.08:06:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:06:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:06:52.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:06:52.75$ifd4f/patch= 2006.183.08:06:52.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:06:52.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:06:52.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:06:52.75$4f8m12a/"form=m,16.000,1:2 2006.183.08:06:52.75$4f8m12a/"tpicd 2006.183.08:06:52.75$4f8m12a/echo=off 2006.183.08:06:52.75$4f8m12a/xlog=off 2006.183.08:06:52.75:!2006.183.08:07:20 2006.183.08:07:01.13#trakl#Source acquired 2006.183.08:07:02.13#flagr#flagr/antenna,acquired 2006.183.08:07:20.00:preob 2006.183.08:07:21.13/onsource/TRACKING 2006.183.08:07:21.13:!2006.183.08:07:30 2006.183.08:07:30.00:data_valid=on 2006.183.08:07:30.00:midob 2006.183.08:07:30.13/onsource/TRACKING 2006.183.08:07:30.13/wx/28.32,996.5,86 2006.183.08:07:30.20/cable/+6.4529E-03 2006.183.08:07:31.29/va/01,08,usb,yes,28,30 2006.183.08:07:31.29/va/02,07,usb,yes,29,30 2006.183.08:07:31.29/va/03,06,usb,yes,30,30 2006.183.08:07:31.29/va/04,07,usb,yes,29,32 2006.183.08:07:31.29/va/05,07,usb,yes,31,32 2006.183.08:07:31.29/va/06,06,usb,yes,30,30 2006.183.08:07:31.29/va/07,06,usb,yes,30,30 2006.183.08:07:31.29/va/08,07,usb,yes,29,28 2006.183.08:07:31.52/valo/01,532.99,yes,locked 2006.183.08:07:31.52/valo/02,572.99,yes,locked 2006.183.08:07:31.52/valo/03,672.99,yes,locked 2006.183.08:07:31.52/valo/04,832.99,yes,locked 2006.183.08:07:31.52/valo/05,652.99,yes,locked 2006.183.08:07:31.52/valo/06,772.99,yes,locked 2006.183.08:07:31.52/valo/07,832.99,yes,locked 2006.183.08:07:31.52/valo/08,852.99,yes,locked 2006.183.08:07:32.61/vb/01,04,usb,yes,29,27 2006.183.08:07:32.61/vb/02,04,usb,yes,31,32 2006.183.08:07:32.61/vb/03,04,usb,yes,27,31 2006.183.08:07:32.61/vb/04,04,usb,yes,28,28 2006.183.08:07:32.61/vb/05,04,usb,yes,26,30 2006.183.08:07:32.61/vb/06,04,usb,yes,27,30 2006.183.08:07:32.61/vb/07,04,usb,yes,29,29 2006.183.08:07:32.61/vb/08,04,usb,yes,27,30 2006.183.08:07:32.84/vblo/01,632.99,yes,locked 2006.183.08:07:32.84/vblo/02,640.99,yes,locked 2006.183.08:07:32.84/vblo/03,656.99,yes,locked 2006.183.08:07:32.84/vblo/04,712.99,yes,locked 2006.183.08:07:32.84/vblo/05,744.99,yes,locked 2006.183.08:07:32.84/vblo/06,752.99,yes,locked 2006.183.08:07:32.84/vblo/07,734.99,yes,locked 2006.183.08:07:32.84/vblo/08,744.99,yes,locked 2006.183.08:07:32.99/vabw/8 2006.183.08:07:33.14/vbbw/8 2006.183.08:07:33.23/xfe/off,on,14.5 2006.183.08:07:33.62/ifatt/23,28,28,28 2006.183.08:07:34.08/fmout-gps/S +3.34E-07 2006.183.08:07:34.12:!2006.183.08:08:30 2006.183.08:08:30.02:data_valid=off 2006.183.08:08:30.02:postob 2006.183.08:08:30.18/cable/+6.4503E-03 2006.183.08:08:30.21/wx/28.34,996.5,86 2006.183.08:08:31.08/fmout-gps/S +3.34E-07 2006.183.08:08:31.08:scan_name=183-0809,k06183,60 2006.183.08:08:31.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.183.08:08:31.15#flagr#flagr/antenna,new-source 2006.183.08:08:32.14:checkk5 2006.183.08:08:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:08:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:08:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:08:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:08:34.00/chk_obsdata//k5ts1/T1830807??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:08:34.37/chk_obsdata//k5ts2/T1830807??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:08:34.74/chk_obsdata//k5ts3/T1830807??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:08:35.11/chk_obsdata//k5ts4/T1830807??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:08:35.80/k5log//k5ts1_log_newline 2006.183.08:08:36.49/k5log//k5ts2_log_newline 2006.183.08:08:37.18/k5log//k5ts3_log_newline 2006.183.08:08:37.88/k5log//k5ts4_log_newline 2006.183.08:08:37.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:08:37.90:4f8m12a=2 2006.183.08:08:37.90$4f8m12a/echo=on 2006.183.08:08:37.90$4f8m12a/pcalon 2006.183.08:08:37.90$pcalon/"no phase cal control is implemented here 2006.183.08:08:37.90$4f8m12a/"tpicd=stop 2006.183.08:08:37.90$4f8m12a/vc4f8 2006.183.08:08:37.90$vc4f8/valo=1,532.99 2006.183.08:08:37.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.08:08:37.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.08:08:37.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:37.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:37.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:37.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:37.91#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:08:37.91#ibcon#first serial, iclass 34, count 0 2006.183.08:08:37.91#ibcon#enter sib2, iclass 34, count 0 2006.183.08:08:37.91#ibcon#flushed, iclass 34, count 0 2006.183.08:08:37.91#ibcon#about to write, iclass 34, count 0 2006.183.08:08:37.91#ibcon#wrote, iclass 34, count 0 2006.183.08:08:37.91#ibcon#about to read 3, iclass 34, count 0 2006.183.08:08:37.94#ibcon#read 3, iclass 34, count 0 2006.183.08:08:37.94#ibcon#about to read 4, iclass 34, count 0 2006.183.08:08:37.94#ibcon#read 4, iclass 34, count 0 2006.183.08:08:37.94#ibcon#about to read 5, iclass 34, count 0 2006.183.08:08:37.94#ibcon#read 5, iclass 34, count 0 2006.183.08:08:37.94#ibcon#about to read 6, iclass 34, count 0 2006.183.08:08:37.94#ibcon#read 6, iclass 34, count 0 2006.183.08:08:37.94#ibcon#end of sib2, iclass 34, count 0 2006.183.08:08:37.94#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:08:37.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:08:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:08:37.94#ibcon#*before write, iclass 34, count 0 2006.183.08:08:37.94#ibcon#enter sib2, iclass 34, count 0 2006.183.08:08:37.94#ibcon#flushed, iclass 34, count 0 2006.183.08:08:37.94#ibcon#about to write, iclass 34, count 0 2006.183.08:08:37.94#ibcon#wrote, iclass 34, count 0 2006.183.08:08:37.94#ibcon#about to read 3, iclass 34, count 0 2006.183.08:08:37.99#ibcon#read 3, iclass 34, count 0 2006.183.08:08:37.99#ibcon#about to read 4, iclass 34, count 0 2006.183.08:08:37.99#ibcon#read 4, iclass 34, count 0 2006.183.08:08:37.99#ibcon#about to read 5, iclass 34, count 0 2006.183.08:08:37.99#ibcon#read 5, iclass 34, count 0 2006.183.08:08:37.99#ibcon#about to read 6, iclass 34, count 0 2006.183.08:08:37.99#ibcon#read 6, iclass 34, count 0 2006.183.08:08:37.99#ibcon#end of sib2, iclass 34, count 0 2006.183.08:08:37.99#ibcon#*after write, iclass 34, count 0 2006.183.08:08:37.99#ibcon#*before return 0, iclass 34, count 0 2006.183.08:08:38.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:38.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:38.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:08:38.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:08:38.00$vc4f8/va=1,8 2006.183.08:08:38.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.08:08:38.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.08:08:38.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:38.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:38.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:38.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:38.00#ibcon#enter wrdev, iclass 36, count 2 2006.183.08:08:38.00#ibcon#first serial, iclass 36, count 2 2006.183.08:08:38.00#ibcon#enter sib2, iclass 36, count 2 2006.183.08:08:38.00#ibcon#flushed, iclass 36, count 2 2006.183.08:08:38.00#ibcon#about to write, iclass 36, count 2 2006.183.08:08:38.00#ibcon#wrote, iclass 36, count 2 2006.183.08:08:38.00#ibcon#about to read 3, iclass 36, count 2 2006.183.08:08:38.02#ibcon#read 3, iclass 36, count 2 2006.183.08:08:38.02#ibcon#about to read 4, iclass 36, count 2 2006.183.08:08:38.02#ibcon#read 4, iclass 36, count 2 2006.183.08:08:38.02#ibcon#about to read 5, iclass 36, count 2 2006.183.08:08:38.02#ibcon#read 5, iclass 36, count 2 2006.183.08:08:38.02#ibcon#about to read 6, iclass 36, count 2 2006.183.08:08:38.02#ibcon#read 6, iclass 36, count 2 2006.183.08:08:38.02#ibcon#end of sib2, iclass 36, count 2 2006.183.08:08:38.02#ibcon#*mode == 0, iclass 36, count 2 2006.183.08:08:38.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.08:08:38.02#ibcon#[25=AT01-08\r\n] 2006.183.08:08:38.02#ibcon#*before write, iclass 36, count 2 2006.183.08:08:38.02#ibcon#enter sib2, iclass 36, count 2 2006.183.08:08:38.02#ibcon#flushed, iclass 36, count 2 2006.183.08:08:38.02#ibcon#about to write, iclass 36, count 2 2006.183.08:08:38.02#ibcon#wrote, iclass 36, count 2 2006.183.08:08:38.02#ibcon#about to read 3, iclass 36, count 2 2006.183.08:08:38.05#ibcon#read 3, iclass 36, count 2 2006.183.08:08:38.05#ibcon#about to read 4, iclass 36, count 2 2006.183.08:08:38.05#ibcon#read 4, iclass 36, count 2 2006.183.08:08:38.05#ibcon#about to read 5, iclass 36, count 2 2006.183.08:08:38.05#ibcon#read 5, iclass 36, count 2 2006.183.08:08:38.05#ibcon#about to read 6, iclass 36, count 2 2006.183.08:08:38.06#ibcon#read 6, iclass 36, count 2 2006.183.08:08:38.06#ibcon#end of sib2, iclass 36, count 2 2006.183.08:08:38.06#ibcon#*after write, iclass 36, count 2 2006.183.08:08:38.06#ibcon#*before return 0, iclass 36, count 2 2006.183.08:08:38.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:38.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:38.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.08:08:38.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:38.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:38.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:38.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:38.17#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:08:38.17#ibcon#first serial, iclass 36, count 0 2006.183.08:08:38.17#ibcon#enter sib2, iclass 36, count 0 2006.183.08:08:38.17#ibcon#flushed, iclass 36, count 0 2006.183.08:08:38.17#ibcon#about to write, iclass 36, count 0 2006.183.08:08:38.17#ibcon#wrote, iclass 36, count 0 2006.183.08:08:38.17#ibcon#about to read 3, iclass 36, count 0 2006.183.08:08:38.19#ibcon#read 3, iclass 36, count 0 2006.183.08:08:38.19#ibcon#about to read 4, iclass 36, count 0 2006.183.08:08:38.19#ibcon#read 4, iclass 36, count 0 2006.183.08:08:38.19#ibcon#about to read 5, iclass 36, count 0 2006.183.08:08:38.19#ibcon#read 5, iclass 36, count 0 2006.183.08:08:38.19#ibcon#about to read 6, iclass 36, count 0 2006.183.08:08:38.19#ibcon#read 6, iclass 36, count 0 2006.183.08:08:38.19#ibcon#end of sib2, iclass 36, count 0 2006.183.08:08:38.19#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:08:38.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:08:38.19#ibcon#[25=USB\r\n] 2006.183.08:08:38.20#ibcon#*before write, iclass 36, count 0 2006.183.08:08:38.20#ibcon#enter sib2, iclass 36, count 0 2006.183.08:08:38.20#ibcon#flushed, iclass 36, count 0 2006.183.08:08:38.20#ibcon#about to write, iclass 36, count 0 2006.183.08:08:38.20#ibcon#wrote, iclass 36, count 0 2006.183.08:08:38.20#ibcon#about to read 3, iclass 36, count 0 2006.183.08:08:38.23#ibcon#read 3, iclass 36, count 0 2006.183.08:08:38.23#ibcon#about to read 4, iclass 36, count 0 2006.183.08:08:38.23#ibcon#read 4, iclass 36, count 0 2006.183.08:08:38.23#ibcon#about to read 5, iclass 36, count 0 2006.183.08:08:38.23#ibcon#read 5, iclass 36, count 0 2006.183.08:08:38.23#ibcon#about to read 6, iclass 36, count 0 2006.183.08:08:38.23#ibcon#read 6, iclass 36, count 0 2006.183.08:08:38.23#ibcon#end of sib2, iclass 36, count 0 2006.183.08:08:38.23#ibcon#*after write, iclass 36, count 0 2006.183.08:08:38.23#ibcon#*before return 0, iclass 36, count 0 2006.183.08:08:38.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:38.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:38.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:08:38.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:08:38.23$vc4f8/valo=2,572.99 2006.183.08:08:38.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.08:08:38.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.08:08:38.23#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:38.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:38.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:38.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:38.23#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:08:38.23#ibcon#first serial, iclass 38, count 0 2006.183.08:08:38.23#ibcon#enter sib2, iclass 38, count 0 2006.183.08:08:38.23#ibcon#flushed, iclass 38, count 0 2006.183.08:08:38.23#ibcon#about to write, iclass 38, count 0 2006.183.08:08:38.23#ibcon#wrote, iclass 38, count 0 2006.183.08:08:38.23#ibcon#about to read 3, iclass 38, count 0 2006.183.08:08:38.24#ibcon#read 3, iclass 38, count 0 2006.183.08:08:38.24#ibcon#about to read 4, iclass 38, count 0 2006.183.08:08:38.24#ibcon#read 4, iclass 38, count 0 2006.183.08:08:38.24#ibcon#about to read 5, iclass 38, count 0 2006.183.08:08:38.24#ibcon#read 5, iclass 38, count 0 2006.183.08:08:38.24#ibcon#about to read 6, iclass 38, count 0 2006.183.08:08:38.24#ibcon#read 6, iclass 38, count 0 2006.183.08:08:38.24#ibcon#end of sib2, iclass 38, count 0 2006.183.08:08:38.24#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:08:38.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:08:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:08:38.25#ibcon#*before write, iclass 38, count 0 2006.183.08:08:38.25#ibcon#enter sib2, iclass 38, count 0 2006.183.08:08:38.25#ibcon#flushed, iclass 38, count 0 2006.183.08:08:38.25#ibcon#about to write, iclass 38, count 0 2006.183.08:08:38.25#ibcon#wrote, iclass 38, count 0 2006.183.08:08:38.25#ibcon#about to read 3, iclass 38, count 0 2006.183.08:08:38.28#ibcon#read 3, iclass 38, count 0 2006.183.08:08:38.28#ibcon#about to read 4, iclass 38, count 0 2006.183.08:08:38.28#ibcon#read 4, iclass 38, count 0 2006.183.08:08:38.28#ibcon#about to read 5, iclass 38, count 0 2006.183.08:08:38.28#ibcon#read 5, iclass 38, count 0 2006.183.08:08:38.28#ibcon#about to read 6, iclass 38, count 0 2006.183.08:08:38.28#ibcon#read 6, iclass 38, count 0 2006.183.08:08:38.28#ibcon#end of sib2, iclass 38, count 0 2006.183.08:08:38.28#ibcon#*after write, iclass 38, count 0 2006.183.08:08:38.28#ibcon#*before return 0, iclass 38, count 0 2006.183.08:08:38.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:38.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:38.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:08:38.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:08:38.29$vc4f8/va=2,7 2006.183.08:08:38.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.08:08:38.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.08:08:38.29#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:38.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:38.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:38.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:38.34#ibcon#enter wrdev, iclass 40, count 2 2006.183.08:08:38.34#ibcon#first serial, iclass 40, count 2 2006.183.08:08:38.34#ibcon#enter sib2, iclass 40, count 2 2006.183.08:08:38.34#ibcon#flushed, iclass 40, count 2 2006.183.08:08:38.34#ibcon#about to write, iclass 40, count 2 2006.183.08:08:38.35#ibcon#wrote, iclass 40, count 2 2006.183.08:08:38.35#ibcon#about to read 3, iclass 40, count 2 2006.183.08:08:38.36#ibcon#read 3, iclass 40, count 2 2006.183.08:08:38.36#ibcon#about to read 4, iclass 40, count 2 2006.183.08:08:38.36#ibcon#read 4, iclass 40, count 2 2006.183.08:08:38.36#ibcon#about to read 5, iclass 40, count 2 2006.183.08:08:38.36#ibcon#read 5, iclass 40, count 2 2006.183.08:08:38.36#ibcon#about to read 6, iclass 40, count 2 2006.183.08:08:38.36#ibcon#read 6, iclass 40, count 2 2006.183.08:08:38.36#ibcon#end of sib2, iclass 40, count 2 2006.183.08:08:38.36#ibcon#*mode == 0, iclass 40, count 2 2006.183.08:08:38.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.08:08:38.36#ibcon#[25=AT02-07\r\n] 2006.183.08:08:38.37#ibcon#*before write, iclass 40, count 2 2006.183.08:08:38.37#ibcon#enter sib2, iclass 40, count 2 2006.183.08:08:38.37#ibcon#flushed, iclass 40, count 2 2006.183.08:08:38.37#ibcon#about to write, iclass 40, count 2 2006.183.08:08:38.37#ibcon#wrote, iclass 40, count 2 2006.183.08:08:38.37#ibcon#about to read 3, iclass 40, count 2 2006.183.08:08:38.39#ibcon#read 3, iclass 40, count 2 2006.183.08:08:38.39#ibcon#about to read 4, iclass 40, count 2 2006.183.08:08:38.39#ibcon#read 4, iclass 40, count 2 2006.183.08:08:38.39#ibcon#about to read 5, iclass 40, count 2 2006.183.08:08:38.39#ibcon#read 5, iclass 40, count 2 2006.183.08:08:38.39#ibcon#about to read 6, iclass 40, count 2 2006.183.08:08:38.39#ibcon#read 6, iclass 40, count 2 2006.183.08:08:38.39#ibcon#end of sib2, iclass 40, count 2 2006.183.08:08:38.39#ibcon#*after write, iclass 40, count 2 2006.183.08:08:38.39#ibcon#*before return 0, iclass 40, count 2 2006.183.08:08:38.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:38.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:38.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.08:08:38.40#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:38.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:38.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:38.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:38.52#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:08:38.52#ibcon#first serial, iclass 40, count 0 2006.183.08:08:38.52#ibcon#enter sib2, iclass 40, count 0 2006.183.08:08:38.52#ibcon#flushed, iclass 40, count 0 2006.183.08:08:38.52#ibcon#about to write, iclass 40, count 0 2006.183.08:08:38.52#ibcon#wrote, iclass 40, count 0 2006.183.08:08:38.52#ibcon#about to read 3, iclass 40, count 0 2006.183.08:08:38.53#ibcon#read 3, iclass 40, count 0 2006.183.08:08:38.53#ibcon#about to read 4, iclass 40, count 0 2006.183.08:08:38.53#ibcon#read 4, iclass 40, count 0 2006.183.08:08:38.53#ibcon#about to read 5, iclass 40, count 0 2006.183.08:08:38.53#ibcon#read 5, iclass 40, count 0 2006.183.08:08:38.53#ibcon#about to read 6, iclass 40, count 0 2006.183.08:08:38.53#ibcon#read 6, iclass 40, count 0 2006.183.08:08:38.54#ibcon#end of sib2, iclass 40, count 0 2006.183.08:08:38.54#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:08:38.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:08:38.54#ibcon#[25=USB\r\n] 2006.183.08:08:38.54#ibcon#*before write, iclass 40, count 0 2006.183.08:08:38.54#ibcon#enter sib2, iclass 40, count 0 2006.183.08:08:38.54#ibcon#flushed, iclass 40, count 0 2006.183.08:08:38.54#ibcon#about to write, iclass 40, count 0 2006.183.08:08:38.54#ibcon#wrote, iclass 40, count 0 2006.183.08:08:38.54#ibcon#about to read 3, iclass 40, count 0 2006.183.08:08:38.56#ibcon#read 3, iclass 40, count 0 2006.183.08:08:38.56#ibcon#about to read 4, iclass 40, count 0 2006.183.08:08:38.56#ibcon#read 4, iclass 40, count 0 2006.183.08:08:38.56#ibcon#about to read 5, iclass 40, count 0 2006.183.08:08:38.56#ibcon#read 5, iclass 40, count 0 2006.183.08:08:38.56#ibcon#about to read 6, iclass 40, count 0 2006.183.08:08:38.56#ibcon#read 6, iclass 40, count 0 2006.183.08:08:38.56#ibcon#end of sib2, iclass 40, count 0 2006.183.08:08:38.56#ibcon#*after write, iclass 40, count 0 2006.183.08:08:38.56#ibcon#*before return 0, iclass 40, count 0 2006.183.08:08:38.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:38.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:38.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:08:38.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:08:38.57$vc4f8/valo=3,672.99 2006.183.08:08:38.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.08:08:38.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.08:08:38.57#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:38.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:38.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:38.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:38.57#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:08:38.57#ibcon#first serial, iclass 4, count 0 2006.183.08:08:38.57#ibcon#enter sib2, iclass 4, count 0 2006.183.08:08:38.57#ibcon#flushed, iclass 4, count 0 2006.183.08:08:38.57#ibcon#about to write, iclass 4, count 0 2006.183.08:08:38.57#ibcon#wrote, iclass 4, count 0 2006.183.08:08:38.57#ibcon#about to read 3, iclass 4, count 0 2006.183.08:08:38.59#ibcon#read 3, iclass 4, count 0 2006.183.08:08:38.59#ibcon#about to read 4, iclass 4, count 0 2006.183.08:08:38.59#ibcon#read 4, iclass 4, count 0 2006.183.08:08:38.59#ibcon#about to read 5, iclass 4, count 0 2006.183.08:08:38.59#ibcon#read 5, iclass 4, count 0 2006.183.08:08:38.59#ibcon#about to read 6, iclass 4, count 0 2006.183.08:08:38.59#ibcon#read 6, iclass 4, count 0 2006.183.08:08:38.59#ibcon#end of sib2, iclass 4, count 0 2006.183.08:08:38.59#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:08:38.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:08:38.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:08:38.59#ibcon#*before write, iclass 4, count 0 2006.183.08:08:38.59#ibcon#enter sib2, iclass 4, count 0 2006.183.08:08:38.59#ibcon#flushed, iclass 4, count 0 2006.183.08:08:38.59#ibcon#about to write, iclass 4, count 0 2006.183.08:08:38.59#ibcon#wrote, iclass 4, count 0 2006.183.08:08:38.59#ibcon#about to read 3, iclass 4, count 0 2006.183.08:08:38.63#ibcon#read 3, iclass 4, count 0 2006.183.08:08:38.63#ibcon#about to read 4, iclass 4, count 0 2006.183.08:08:38.63#ibcon#read 4, iclass 4, count 0 2006.183.08:08:38.63#ibcon#about to read 5, iclass 4, count 0 2006.183.08:08:38.63#ibcon#read 5, iclass 4, count 0 2006.183.08:08:38.63#ibcon#about to read 6, iclass 4, count 0 2006.183.08:08:38.63#ibcon#read 6, iclass 4, count 0 2006.183.08:08:38.63#ibcon#end of sib2, iclass 4, count 0 2006.183.08:08:38.64#ibcon#*after write, iclass 4, count 0 2006.183.08:08:38.64#ibcon#*before return 0, iclass 4, count 0 2006.183.08:08:38.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:38.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:38.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:08:38.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:08:38.64$vc4f8/va=3,6 2006.183.08:08:38.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.08:08:38.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.08:08:38.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:38.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:38.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:38.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:38.69#ibcon#enter wrdev, iclass 6, count 2 2006.183.08:08:38.69#ibcon#first serial, iclass 6, count 2 2006.183.08:08:38.69#ibcon#enter sib2, iclass 6, count 2 2006.183.08:08:38.69#ibcon#flushed, iclass 6, count 2 2006.183.08:08:38.69#ibcon#about to write, iclass 6, count 2 2006.183.08:08:38.69#ibcon#wrote, iclass 6, count 2 2006.183.08:08:38.69#ibcon#about to read 3, iclass 6, count 2 2006.183.08:08:38.70#ibcon#read 3, iclass 6, count 2 2006.183.08:08:38.70#ibcon#about to read 4, iclass 6, count 2 2006.183.08:08:38.70#ibcon#read 4, iclass 6, count 2 2006.183.08:08:38.70#ibcon#about to read 5, iclass 6, count 2 2006.183.08:08:38.70#ibcon#read 5, iclass 6, count 2 2006.183.08:08:38.70#ibcon#about to read 6, iclass 6, count 2 2006.183.08:08:38.70#ibcon#read 6, iclass 6, count 2 2006.183.08:08:38.70#ibcon#end of sib2, iclass 6, count 2 2006.183.08:08:38.70#ibcon#*mode == 0, iclass 6, count 2 2006.183.08:08:38.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.08:08:38.71#ibcon#[25=AT03-06\r\n] 2006.183.08:08:38.71#ibcon#*before write, iclass 6, count 2 2006.183.08:08:38.71#ibcon#enter sib2, iclass 6, count 2 2006.183.08:08:38.71#ibcon#flushed, iclass 6, count 2 2006.183.08:08:38.71#ibcon#about to write, iclass 6, count 2 2006.183.08:08:38.71#ibcon#wrote, iclass 6, count 2 2006.183.08:08:38.71#ibcon#about to read 3, iclass 6, count 2 2006.183.08:08:38.73#ibcon#read 3, iclass 6, count 2 2006.183.08:08:38.73#ibcon#about to read 4, iclass 6, count 2 2006.183.08:08:38.73#ibcon#read 4, iclass 6, count 2 2006.183.08:08:38.73#ibcon#about to read 5, iclass 6, count 2 2006.183.08:08:38.73#ibcon#read 5, iclass 6, count 2 2006.183.08:08:38.73#ibcon#about to read 6, iclass 6, count 2 2006.183.08:08:38.73#ibcon#read 6, iclass 6, count 2 2006.183.08:08:38.73#ibcon#end of sib2, iclass 6, count 2 2006.183.08:08:38.74#ibcon#*after write, iclass 6, count 2 2006.183.08:08:38.74#ibcon#*before return 0, iclass 6, count 2 2006.183.08:08:38.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:38.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:38.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.08:08:38.74#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:38.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:38.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:38.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:38.85#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:08:38.85#ibcon#first serial, iclass 6, count 0 2006.183.08:08:38.85#ibcon#enter sib2, iclass 6, count 0 2006.183.08:08:38.85#ibcon#flushed, iclass 6, count 0 2006.183.08:08:38.85#ibcon#about to write, iclass 6, count 0 2006.183.08:08:38.85#ibcon#wrote, iclass 6, count 0 2006.183.08:08:38.85#ibcon#about to read 3, iclass 6, count 0 2006.183.08:08:38.87#ibcon#read 3, iclass 6, count 0 2006.183.08:08:38.87#ibcon#about to read 4, iclass 6, count 0 2006.183.08:08:38.87#ibcon#read 4, iclass 6, count 0 2006.183.08:08:38.87#ibcon#about to read 5, iclass 6, count 0 2006.183.08:08:38.87#ibcon#read 5, iclass 6, count 0 2006.183.08:08:38.87#ibcon#about to read 6, iclass 6, count 0 2006.183.08:08:38.87#ibcon#read 6, iclass 6, count 0 2006.183.08:08:38.87#ibcon#end of sib2, iclass 6, count 0 2006.183.08:08:38.87#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:08:38.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:08:38.87#ibcon#[25=USB\r\n] 2006.183.08:08:38.88#ibcon#*before write, iclass 6, count 0 2006.183.08:08:38.88#ibcon#enter sib2, iclass 6, count 0 2006.183.08:08:38.88#ibcon#flushed, iclass 6, count 0 2006.183.08:08:38.88#ibcon#about to write, iclass 6, count 0 2006.183.08:08:38.88#ibcon#wrote, iclass 6, count 0 2006.183.08:08:38.88#ibcon#about to read 3, iclass 6, count 0 2006.183.08:08:38.90#ibcon#read 3, iclass 6, count 0 2006.183.08:08:38.90#ibcon#about to read 4, iclass 6, count 0 2006.183.08:08:38.90#ibcon#read 4, iclass 6, count 0 2006.183.08:08:38.90#ibcon#about to read 5, iclass 6, count 0 2006.183.08:08:38.90#ibcon#read 5, iclass 6, count 0 2006.183.08:08:38.90#ibcon#about to read 6, iclass 6, count 0 2006.183.08:08:38.90#ibcon#read 6, iclass 6, count 0 2006.183.08:08:38.90#ibcon#end of sib2, iclass 6, count 0 2006.183.08:08:38.90#ibcon#*after write, iclass 6, count 0 2006.183.08:08:38.90#ibcon#*before return 0, iclass 6, count 0 2006.183.08:08:38.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:38.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:38.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:08:38.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:08:38.91$vc4f8/valo=4,832.99 2006.183.08:08:38.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.08:08:38.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.08:08:38.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:38.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:38.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:38.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:38.91#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:08:38.91#ibcon#first serial, iclass 10, count 0 2006.183.08:08:38.91#ibcon#enter sib2, iclass 10, count 0 2006.183.08:08:38.91#ibcon#flushed, iclass 10, count 0 2006.183.08:08:38.91#ibcon#about to write, iclass 10, count 0 2006.183.08:08:38.91#ibcon#wrote, iclass 10, count 0 2006.183.08:08:38.91#ibcon#about to read 3, iclass 10, count 0 2006.183.08:08:38.92#ibcon#read 3, iclass 10, count 0 2006.183.08:08:38.92#ibcon#about to read 4, iclass 10, count 0 2006.183.08:08:38.92#ibcon#read 4, iclass 10, count 0 2006.183.08:08:38.92#ibcon#about to read 5, iclass 10, count 0 2006.183.08:08:38.92#ibcon#read 5, iclass 10, count 0 2006.183.08:08:38.92#ibcon#about to read 6, iclass 10, count 0 2006.183.08:08:38.92#ibcon#read 6, iclass 10, count 0 2006.183.08:08:38.92#ibcon#end of sib2, iclass 10, count 0 2006.183.08:08:38.92#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:08:38.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:08:38.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:08:38.93#ibcon#*before write, iclass 10, count 0 2006.183.08:08:38.93#ibcon#enter sib2, iclass 10, count 0 2006.183.08:08:38.93#ibcon#flushed, iclass 10, count 0 2006.183.08:08:38.93#ibcon#about to write, iclass 10, count 0 2006.183.08:08:38.93#ibcon#wrote, iclass 10, count 0 2006.183.08:08:38.93#ibcon#about to read 3, iclass 10, count 0 2006.183.08:08:38.96#ibcon#read 3, iclass 10, count 0 2006.183.08:08:38.96#ibcon#about to read 4, iclass 10, count 0 2006.183.08:08:38.96#ibcon#read 4, iclass 10, count 0 2006.183.08:08:38.96#ibcon#about to read 5, iclass 10, count 0 2006.183.08:08:38.96#ibcon#read 5, iclass 10, count 0 2006.183.08:08:38.96#ibcon#about to read 6, iclass 10, count 0 2006.183.08:08:38.96#ibcon#read 6, iclass 10, count 0 2006.183.08:08:38.96#ibcon#end of sib2, iclass 10, count 0 2006.183.08:08:38.96#ibcon#*after write, iclass 10, count 0 2006.183.08:08:38.96#ibcon#*before return 0, iclass 10, count 0 2006.183.08:08:38.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:38.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:38.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:08:38.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:08:38.97$vc4f8/va=4,7 2006.183.08:08:38.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.08:08:38.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.08:08:38.97#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:38.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:39.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:39.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:39.02#ibcon#enter wrdev, iclass 12, count 2 2006.183.08:08:39.02#ibcon#first serial, iclass 12, count 2 2006.183.08:08:39.02#ibcon#enter sib2, iclass 12, count 2 2006.183.08:08:39.02#ibcon#flushed, iclass 12, count 2 2006.183.08:08:39.02#ibcon#about to write, iclass 12, count 2 2006.183.08:08:39.02#ibcon#wrote, iclass 12, count 2 2006.183.08:08:39.02#ibcon#about to read 3, iclass 12, count 2 2006.183.08:08:39.04#ibcon#read 3, iclass 12, count 2 2006.183.08:08:39.04#ibcon#about to read 4, iclass 12, count 2 2006.183.08:08:39.04#ibcon#read 4, iclass 12, count 2 2006.183.08:08:39.04#ibcon#about to read 5, iclass 12, count 2 2006.183.08:08:39.04#ibcon#read 5, iclass 12, count 2 2006.183.08:08:39.04#ibcon#about to read 6, iclass 12, count 2 2006.183.08:08:39.04#ibcon#read 6, iclass 12, count 2 2006.183.08:08:39.04#ibcon#end of sib2, iclass 12, count 2 2006.183.08:08:39.04#ibcon#*mode == 0, iclass 12, count 2 2006.183.08:08:39.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.08:08:39.04#ibcon#[25=AT04-07\r\n] 2006.183.08:08:39.04#ibcon#*before write, iclass 12, count 2 2006.183.08:08:39.05#ibcon#enter sib2, iclass 12, count 2 2006.183.08:08:39.05#ibcon#flushed, iclass 12, count 2 2006.183.08:08:39.05#ibcon#about to write, iclass 12, count 2 2006.183.08:08:39.05#ibcon#wrote, iclass 12, count 2 2006.183.08:08:39.05#ibcon#about to read 3, iclass 12, count 2 2006.183.08:08:39.07#ibcon#read 3, iclass 12, count 2 2006.183.08:08:39.07#ibcon#about to read 4, iclass 12, count 2 2006.183.08:08:39.07#ibcon#read 4, iclass 12, count 2 2006.183.08:08:39.07#ibcon#about to read 5, iclass 12, count 2 2006.183.08:08:39.07#ibcon#read 5, iclass 12, count 2 2006.183.08:08:39.07#ibcon#about to read 6, iclass 12, count 2 2006.183.08:08:39.07#ibcon#read 6, iclass 12, count 2 2006.183.08:08:39.07#ibcon#end of sib2, iclass 12, count 2 2006.183.08:08:39.08#ibcon#*after write, iclass 12, count 2 2006.183.08:08:39.08#ibcon#*before return 0, iclass 12, count 2 2006.183.08:08:39.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:39.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:39.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.08:08:39.08#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:39.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:39.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:39.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:39.19#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:08:39.19#ibcon#first serial, iclass 12, count 0 2006.183.08:08:39.19#ibcon#enter sib2, iclass 12, count 0 2006.183.08:08:39.19#ibcon#flushed, iclass 12, count 0 2006.183.08:08:39.19#ibcon#about to write, iclass 12, count 0 2006.183.08:08:39.19#ibcon#wrote, iclass 12, count 0 2006.183.08:08:39.19#ibcon#about to read 3, iclass 12, count 0 2006.183.08:08:39.21#ibcon#read 3, iclass 12, count 0 2006.183.08:08:39.21#ibcon#about to read 4, iclass 12, count 0 2006.183.08:08:39.21#ibcon#read 4, iclass 12, count 0 2006.183.08:08:39.22#ibcon#about to read 5, iclass 12, count 0 2006.183.08:08:39.22#ibcon#read 5, iclass 12, count 0 2006.183.08:08:39.22#ibcon#about to read 6, iclass 12, count 0 2006.183.08:08:39.22#ibcon#read 6, iclass 12, count 0 2006.183.08:08:39.22#ibcon#end of sib2, iclass 12, count 0 2006.183.08:08:39.22#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:08:39.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:08:39.22#ibcon#[25=USB\r\n] 2006.183.08:08:39.22#ibcon#*before write, iclass 12, count 0 2006.183.08:08:39.22#ibcon#enter sib2, iclass 12, count 0 2006.183.08:08:39.22#ibcon#flushed, iclass 12, count 0 2006.183.08:08:39.22#ibcon#about to write, iclass 12, count 0 2006.183.08:08:39.22#ibcon#wrote, iclass 12, count 0 2006.183.08:08:39.22#ibcon#about to read 3, iclass 12, count 0 2006.183.08:08:39.24#ibcon#read 3, iclass 12, count 0 2006.183.08:08:39.24#ibcon#about to read 4, iclass 12, count 0 2006.183.08:08:39.24#ibcon#read 4, iclass 12, count 0 2006.183.08:08:39.24#ibcon#about to read 5, iclass 12, count 0 2006.183.08:08:39.24#ibcon#read 5, iclass 12, count 0 2006.183.08:08:39.24#ibcon#about to read 6, iclass 12, count 0 2006.183.08:08:39.24#ibcon#read 6, iclass 12, count 0 2006.183.08:08:39.24#ibcon#end of sib2, iclass 12, count 0 2006.183.08:08:39.25#ibcon#*after write, iclass 12, count 0 2006.183.08:08:39.25#ibcon#*before return 0, iclass 12, count 0 2006.183.08:08:39.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:39.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:39.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:08:39.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:08:39.25$vc4f8/valo=5,652.99 2006.183.08:08:39.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:08:39.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:08:39.25#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:39.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:39.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:39.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:39.25#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:08:39.25#ibcon#first serial, iclass 14, count 0 2006.183.08:08:39.25#ibcon#enter sib2, iclass 14, count 0 2006.183.08:08:39.25#ibcon#flushed, iclass 14, count 0 2006.183.08:08:39.25#ibcon#about to write, iclass 14, count 0 2006.183.08:08:39.25#ibcon#wrote, iclass 14, count 0 2006.183.08:08:39.25#ibcon#about to read 3, iclass 14, count 0 2006.183.08:08:39.26#ibcon#read 3, iclass 14, count 0 2006.183.08:08:39.26#ibcon#about to read 4, iclass 14, count 0 2006.183.08:08:39.26#ibcon#read 4, iclass 14, count 0 2006.183.08:08:39.26#ibcon#about to read 5, iclass 14, count 0 2006.183.08:08:39.26#ibcon#read 5, iclass 14, count 0 2006.183.08:08:39.26#ibcon#about to read 6, iclass 14, count 0 2006.183.08:08:39.26#ibcon#read 6, iclass 14, count 0 2006.183.08:08:39.26#ibcon#end of sib2, iclass 14, count 0 2006.183.08:08:39.26#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:08:39.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:08:39.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:08:39.27#ibcon#*before write, iclass 14, count 0 2006.183.08:08:39.27#ibcon#enter sib2, iclass 14, count 0 2006.183.08:08:39.27#ibcon#flushed, iclass 14, count 0 2006.183.08:08:39.27#ibcon#about to write, iclass 14, count 0 2006.183.08:08:39.27#ibcon#wrote, iclass 14, count 0 2006.183.08:08:39.27#ibcon#about to read 3, iclass 14, count 0 2006.183.08:08:39.30#ibcon#read 3, iclass 14, count 0 2006.183.08:08:39.30#ibcon#about to read 4, iclass 14, count 0 2006.183.08:08:39.30#ibcon#read 4, iclass 14, count 0 2006.183.08:08:39.30#ibcon#about to read 5, iclass 14, count 0 2006.183.08:08:39.30#ibcon#read 5, iclass 14, count 0 2006.183.08:08:39.30#ibcon#about to read 6, iclass 14, count 0 2006.183.08:08:39.30#ibcon#read 6, iclass 14, count 0 2006.183.08:08:39.30#ibcon#end of sib2, iclass 14, count 0 2006.183.08:08:39.30#ibcon#*after write, iclass 14, count 0 2006.183.08:08:39.30#ibcon#*before return 0, iclass 14, count 0 2006.183.08:08:39.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:39.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:39.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:08:39.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:08:39.31$vc4f8/va=5,7 2006.183.08:08:39.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.08:08:39.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.08:08:39.31#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:39.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:39.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:39.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:39.36#ibcon#enter wrdev, iclass 16, count 2 2006.183.08:08:39.36#ibcon#first serial, iclass 16, count 2 2006.183.08:08:39.36#ibcon#enter sib2, iclass 16, count 2 2006.183.08:08:39.36#ibcon#flushed, iclass 16, count 2 2006.183.08:08:39.36#ibcon#about to write, iclass 16, count 2 2006.183.08:08:39.36#ibcon#wrote, iclass 16, count 2 2006.183.08:08:39.36#ibcon#about to read 3, iclass 16, count 2 2006.183.08:08:39.38#ibcon#read 3, iclass 16, count 2 2006.183.08:08:39.38#ibcon#about to read 4, iclass 16, count 2 2006.183.08:08:39.38#ibcon#read 4, iclass 16, count 2 2006.183.08:08:39.38#ibcon#about to read 5, iclass 16, count 2 2006.183.08:08:39.38#ibcon#read 5, iclass 16, count 2 2006.183.08:08:39.38#ibcon#about to read 6, iclass 16, count 2 2006.183.08:08:39.38#ibcon#read 6, iclass 16, count 2 2006.183.08:08:39.38#ibcon#end of sib2, iclass 16, count 2 2006.183.08:08:39.38#ibcon#*mode == 0, iclass 16, count 2 2006.183.08:08:39.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.08:08:39.39#ibcon#[25=AT05-07\r\n] 2006.183.08:08:39.39#ibcon#*before write, iclass 16, count 2 2006.183.08:08:39.39#ibcon#enter sib2, iclass 16, count 2 2006.183.08:08:39.39#ibcon#flushed, iclass 16, count 2 2006.183.08:08:39.39#ibcon#about to write, iclass 16, count 2 2006.183.08:08:39.39#ibcon#wrote, iclass 16, count 2 2006.183.08:08:39.39#ibcon#about to read 3, iclass 16, count 2 2006.183.08:08:39.41#ibcon#read 3, iclass 16, count 2 2006.183.08:08:39.41#ibcon#about to read 4, iclass 16, count 2 2006.183.08:08:39.41#ibcon#read 4, iclass 16, count 2 2006.183.08:08:39.41#ibcon#about to read 5, iclass 16, count 2 2006.183.08:08:39.41#ibcon#read 5, iclass 16, count 2 2006.183.08:08:39.41#ibcon#about to read 6, iclass 16, count 2 2006.183.08:08:39.41#ibcon#read 6, iclass 16, count 2 2006.183.08:08:39.41#ibcon#end of sib2, iclass 16, count 2 2006.183.08:08:39.41#ibcon#*after write, iclass 16, count 2 2006.183.08:08:39.41#ibcon#*before return 0, iclass 16, count 2 2006.183.08:08:39.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:39.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:39.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.08:08:39.42#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:39.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:39.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:39.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:39.53#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:08:39.53#ibcon#first serial, iclass 16, count 0 2006.183.08:08:39.53#ibcon#enter sib2, iclass 16, count 0 2006.183.08:08:39.53#ibcon#flushed, iclass 16, count 0 2006.183.08:08:39.53#ibcon#about to write, iclass 16, count 0 2006.183.08:08:39.53#ibcon#wrote, iclass 16, count 0 2006.183.08:08:39.53#ibcon#about to read 3, iclass 16, count 0 2006.183.08:08:39.55#ibcon#read 3, iclass 16, count 0 2006.183.08:08:39.55#ibcon#about to read 4, iclass 16, count 0 2006.183.08:08:39.55#ibcon#read 4, iclass 16, count 0 2006.183.08:08:39.55#ibcon#about to read 5, iclass 16, count 0 2006.183.08:08:39.55#ibcon#read 5, iclass 16, count 0 2006.183.08:08:39.55#ibcon#about to read 6, iclass 16, count 0 2006.183.08:08:39.55#ibcon#read 6, iclass 16, count 0 2006.183.08:08:39.55#ibcon#end of sib2, iclass 16, count 0 2006.183.08:08:39.55#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:08:39.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:08:39.55#ibcon#[25=USB\r\n] 2006.183.08:08:39.56#ibcon#*before write, iclass 16, count 0 2006.183.08:08:39.56#ibcon#enter sib2, iclass 16, count 0 2006.183.08:08:39.56#ibcon#flushed, iclass 16, count 0 2006.183.08:08:39.56#ibcon#about to write, iclass 16, count 0 2006.183.08:08:39.56#ibcon#wrote, iclass 16, count 0 2006.183.08:08:39.56#ibcon#about to read 3, iclass 16, count 0 2006.183.08:08:39.58#ibcon#read 3, iclass 16, count 0 2006.183.08:08:39.58#ibcon#about to read 4, iclass 16, count 0 2006.183.08:08:39.58#ibcon#read 4, iclass 16, count 0 2006.183.08:08:39.58#ibcon#about to read 5, iclass 16, count 0 2006.183.08:08:39.58#ibcon#read 5, iclass 16, count 0 2006.183.08:08:39.58#ibcon#about to read 6, iclass 16, count 0 2006.183.08:08:39.58#ibcon#read 6, iclass 16, count 0 2006.183.08:08:39.58#ibcon#end of sib2, iclass 16, count 0 2006.183.08:08:39.58#ibcon#*after write, iclass 16, count 0 2006.183.08:08:39.58#ibcon#*before return 0, iclass 16, count 0 2006.183.08:08:39.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:39.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:39.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:08:39.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:08:39.59$vc4f8/valo=6,772.99 2006.183.08:08:39.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:08:39.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:08:39.59#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:39.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:39.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:39.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:39.59#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:08:39.59#ibcon#first serial, iclass 18, count 0 2006.183.08:08:39.59#ibcon#enter sib2, iclass 18, count 0 2006.183.08:08:39.59#ibcon#flushed, iclass 18, count 0 2006.183.08:08:39.59#ibcon#about to write, iclass 18, count 0 2006.183.08:08:39.59#ibcon#wrote, iclass 18, count 0 2006.183.08:08:39.59#ibcon#about to read 3, iclass 18, count 0 2006.183.08:08:39.61#ibcon#read 3, iclass 18, count 0 2006.183.08:08:39.61#ibcon#about to read 4, iclass 18, count 0 2006.183.08:08:39.61#ibcon#read 4, iclass 18, count 0 2006.183.08:08:39.61#ibcon#about to read 5, iclass 18, count 0 2006.183.08:08:39.61#ibcon#read 5, iclass 18, count 0 2006.183.08:08:39.61#ibcon#about to read 6, iclass 18, count 0 2006.183.08:08:39.61#ibcon#read 6, iclass 18, count 0 2006.183.08:08:39.61#ibcon#end of sib2, iclass 18, count 0 2006.183.08:08:39.61#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:08:39.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:08:39.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:08:39.61#ibcon#*before write, iclass 18, count 0 2006.183.08:08:39.61#ibcon#enter sib2, iclass 18, count 0 2006.183.08:08:39.61#ibcon#flushed, iclass 18, count 0 2006.183.08:08:39.61#ibcon#about to write, iclass 18, count 0 2006.183.08:08:39.61#ibcon#wrote, iclass 18, count 0 2006.183.08:08:39.61#ibcon#about to read 3, iclass 18, count 0 2006.183.08:08:39.65#ibcon#read 3, iclass 18, count 0 2006.183.08:08:39.65#ibcon#about to read 4, iclass 18, count 0 2006.183.08:08:39.65#ibcon#read 4, iclass 18, count 0 2006.183.08:08:39.65#ibcon#about to read 5, iclass 18, count 0 2006.183.08:08:39.65#ibcon#read 5, iclass 18, count 0 2006.183.08:08:39.65#ibcon#about to read 6, iclass 18, count 0 2006.183.08:08:39.65#ibcon#read 6, iclass 18, count 0 2006.183.08:08:39.65#ibcon#end of sib2, iclass 18, count 0 2006.183.08:08:39.66#ibcon#*after write, iclass 18, count 0 2006.183.08:08:39.66#ibcon#*before return 0, iclass 18, count 0 2006.183.08:08:39.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:39.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:39.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:08:39.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:08:39.66$vc4f8/va=6,6 2006.183.08:08:39.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.08:08:39.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.08:08:39.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:39.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:08:39.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:08:39.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:08:39.70#ibcon#enter wrdev, iclass 20, count 2 2006.183.08:08:39.70#ibcon#first serial, iclass 20, count 2 2006.183.08:08:39.70#ibcon#enter sib2, iclass 20, count 2 2006.183.08:08:39.70#ibcon#flushed, iclass 20, count 2 2006.183.08:08:39.70#ibcon#about to write, iclass 20, count 2 2006.183.08:08:39.70#ibcon#wrote, iclass 20, count 2 2006.183.08:08:39.70#ibcon#about to read 3, iclass 20, count 2 2006.183.08:08:39.72#ibcon#read 3, iclass 20, count 2 2006.183.08:08:39.72#ibcon#about to read 4, iclass 20, count 2 2006.183.08:08:39.72#ibcon#read 4, iclass 20, count 2 2006.183.08:08:39.72#ibcon#about to read 5, iclass 20, count 2 2006.183.08:08:39.72#ibcon#read 5, iclass 20, count 2 2006.183.08:08:39.72#ibcon#about to read 6, iclass 20, count 2 2006.183.08:08:39.72#ibcon#read 6, iclass 20, count 2 2006.183.08:08:39.72#ibcon#end of sib2, iclass 20, count 2 2006.183.08:08:39.72#ibcon#*mode == 0, iclass 20, count 2 2006.183.08:08:39.72#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.08:08:39.72#ibcon#[25=AT06-06\r\n] 2006.183.08:08:39.73#ibcon#*before write, iclass 20, count 2 2006.183.08:08:39.73#ibcon#enter sib2, iclass 20, count 2 2006.183.08:08:39.73#ibcon#flushed, iclass 20, count 2 2006.183.08:08:39.73#ibcon#about to write, iclass 20, count 2 2006.183.08:08:39.73#ibcon#wrote, iclass 20, count 2 2006.183.08:08:39.73#ibcon#about to read 3, iclass 20, count 2 2006.183.08:08:39.75#ibcon#read 3, iclass 20, count 2 2006.183.08:08:39.75#ibcon#about to read 4, iclass 20, count 2 2006.183.08:08:39.75#ibcon#read 4, iclass 20, count 2 2006.183.08:08:39.75#ibcon#about to read 5, iclass 20, count 2 2006.183.08:08:39.75#ibcon#read 5, iclass 20, count 2 2006.183.08:08:39.75#ibcon#about to read 6, iclass 20, count 2 2006.183.08:08:39.75#ibcon#read 6, iclass 20, count 2 2006.183.08:08:39.75#ibcon#end of sib2, iclass 20, count 2 2006.183.08:08:39.76#ibcon#*after write, iclass 20, count 2 2006.183.08:08:39.76#ibcon#*before return 0, iclass 20, count 2 2006.183.08:08:39.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:08:39.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:08:39.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.08:08:39.76#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:39.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:08:39.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:08:39.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:08:39.87#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:08:39.87#ibcon#first serial, iclass 20, count 0 2006.183.08:08:39.87#ibcon#enter sib2, iclass 20, count 0 2006.183.08:08:39.87#ibcon#flushed, iclass 20, count 0 2006.183.08:08:39.87#ibcon#about to write, iclass 20, count 0 2006.183.08:08:39.87#ibcon#wrote, iclass 20, count 0 2006.183.08:08:39.87#ibcon#about to read 3, iclass 20, count 0 2006.183.08:08:39.89#ibcon#read 3, iclass 20, count 0 2006.183.08:08:39.89#ibcon#about to read 4, iclass 20, count 0 2006.183.08:08:39.89#ibcon#read 4, iclass 20, count 0 2006.183.08:08:39.89#ibcon#about to read 5, iclass 20, count 0 2006.183.08:08:39.89#ibcon#read 5, iclass 20, count 0 2006.183.08:08:39.89#ibcon#about to read 6, iclass 20, count 0 2006.183.08:08:39.89#ibcon#read 6, iclass 20, count 0 2006.183.08:08:39.89#ibcon#end of sib2, iclass 20, count 0 2006.183.08:08:39.89#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:08:39.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:08:39.89#ibcon#[25=USB\r\n] 2006.183.08:08:39.90#ibcon#*before write, iclass 20, count 0 2006.183.08:08:39.90#ibcon#enter sib2, iclass 20, count 0 2006.183.08:08:39.90#ibcon#flushed, iclass 20, count 0 2006.183.08:08:39.90#ibcon#about to write, iclass 20, count 0 2006.183.08:08:39.90#ibcon#wrote, iclass 20, count 0 2006.183.08:08:39.90#ibcon#about to read 3, iclass 20, count 0 2006.183.08:08:39.92#ibcon#read 3, iclass 20, count 0 2006.183.08:08:39.92#ibcon#about to read 4, iclass 20, count 0 2006.183.08:08:39.92#ibcon#read 4, iclass 20, count 0 2006.183.08:08:39.92#ibcon#about to read 5, iclass 20, count 0 2006.183.08:08:39.92#ibcon#read 5, iclass 20, count 0 2006.183.08:08:39.92#ibcon#about to read 6, iclass 20, count 0 2006.183.08:08:39.92#ibcon#read 6, iclass 20, count 0 2006.183.08:08:39.92#ibcon#end of sib2, iclass 20, count 0 2006.183.08:08:39.92#ibcon#*after write, iclass 20, count 0 2006.183.08:08:39.92#ibcon#*before return 0, iclass 20, count 0 2006.183.08:08:39.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:08:39.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:08:39.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:08:39.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:08:39.93$vc4f8/valo=7,832.99 2006.183.08:08:39.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.08:08:39.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.08:08:39.93#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:39.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:08:39.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:08:39.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:08:39.93#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:08:39.93#ibcon#first serial, iclass 22, count 0 2006.183.08:08:39.93#ibcon#enter sib2, iclass 22, count 0 2006.183.08:08:39.93#ibcon#flushed, iclass 22, count 0 2006.183.08:08:39.93#ibcon#about to write, iclass 22, count 0 2006.183.08:08:39.93#ibcon#wrote, iclass 22, count 0 2006.183.08:08:39.93#ibcon#about to read 3, iclass 22, count 0 2006.183.08:08:39.94#ibcon#read 3, iclass 22, count 0 2006.183.08:08:39.94#ibcon#about to read 4, iclass 22, count 0 2006.183.08:08:39.94#ibcon#read 4, iclass 22, count 0 2006.183.08:08:39.94#ibcon#about to read 5, iclass 22, count 0 2006.183.08:08:39.94#ibcon#read 5, iclass 22, count 0 2006.183.08:08:39.94#ibcon#about to read 6, iclass 22, count 0 2006.183.08:08:39.94#ibcon#read 6, iclass 22, count 0 2006.183.08:08:39.94#ibcon#end of sib2, iclass 22, count 0 2006.183.08:08:39.94#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:08:39.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:08:39.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:08:39.95#ibcon#*before write, iclass 22, count 0 2006.183.08:08:39.95#ibcon#enter sib2, iclass 22, count 0 2006.183.08:08:39.95#ibcon#flushed, iclass 22, count 0 2006.183.08:08:39.95#ibcon#about to write, iclass 22, count 0 2006.183.08:08:39.95#ibcon#wrote, iclass 22, count 0 2006.183.08:08:39.95#ibcon#about to read 3, iclass 22, count 0 2006.183.08:08:39.98#ibcon#read 3, iclass 22, count 0 2006.183.08:08:39.98#ibcon#about to read 4, iclass 22, count 0 2006.183.08:08:39.98#ibcon#read 4, iclass 22, count 0 2006.183.08:08:39.98#ibcon#about to read 5, iclass 22, count 0 2006.183.08:08:39.98#ibcon#read 5, iclass 22, count 0 2006.183.08:08:39.98#ibcon#about to read 6, iclass 22, count 0 2006.183.08:08:39.98#ibcon#read 6, iclass 22, count 0 2006.183.08:08:39.98#ibcon#end of sib2, iclass 22, count 0 2006.183.08:08:39.98#ibcon#*after write, iclass 22, count 0 2006.183.08:08:39.98#ibcon#*before return 0, iclass 22, count 0 2006.183.08:08:39.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:08:39.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:08:39.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:08:39.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:08:39.99$vc4f8/va=7,6 2006.183.08:08:39.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.08:08:39.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.08:08:39.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:39.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:08:40.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:08:40.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:08:40.04#ibcon#enter wrdev, iclass 24, count 2 2006.183.08:08:40.04#ibcon#first serial, iclass 24, count 2 2006.183.08:08:40.04#ibcon#enter sib2, iclass 24, count 2 2006.183.08:08:40.04#ibcon#flushed, iclass 24, count 2 2006.183.08:08:40.04#ibcon#about to write, iclass 24, count 2 2006.183.08:08:40.04#ibcon#wrote, iclass 24, count 2 2006.183.08:08:40.04#ibcon#about to read 3, iclass 24, count 2 2006.183.08:08:40.06#ibcon#read 3, iclass 24, count 2 2006.183.08:08:40.06#ibcon#about to read 4, iclass 24, count 2 2006.183.08:08:40.06#ibcon#read 4, iclass 24, count 2 2006.183.08:08:40.06#ibcon#about to read 5, iclass 24, count 2 2006.183.08:08:40.06#ibcon#read 5, iclass 24, count 2 2006.183.08:08:40.06#ibcon#about to read 6, iclass 24, count 2 2006.183.08:08:40.06#ibcon#read 6, iclass 24, count 2 2006.183.08:08:40.06#ibcon#end of sib2, iclass 24, count 2 2006.183.08:08:40.06#ibcon#*mode == 0, iclass 24, count 2 2006.183.08:08:40.06#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.08:08:40.06#ibcon#[25=AT07-06\r\n] 2006.183.08:08:40.06#ibcon#*before write, iclass 24, count 2 2006.183.08:08:40.07#ibcon#enter sib2, iclass 24, count 2 2006.183.08:08:40.07#ibcon#flushed, iclass 24, count 2 2006.183.08:08:40.07#ibcon#about to write, iclass 24, count 2 2006.183.08:08:40.07#ibcon#wrote, iclass 24, count 2 2006.183.08:08:40.07#ibcon#about to read 3, iclass 24, count 2 2006.183.08:08:40.09#ibcon#read 3, iclass 24, count 2 2006.183.08:08:40.09#ibcon#about to read 4, iclass 24, count 2 2006.183.08:08:40.09#ibcon#read 4, iclass 24, count 2 2006.183.08:08:40.09#ibcon#about to read 5, iclass 24, count 2 2006.183.08:08:40.09#ibcon#read 5, iclass 24, count 2 2006.183.08:08:40.09#ibcon#about to read 6, iclass 24, count 2 2006.183.08:08:40.09#ibcon#read 6, iclass 24, count 2 2006.183.08:08:40.09#ibcon#end of sib2, iclass 24, count 2 2006.183.08:08:40.10#ibcon#*after write, iclass 24, count 2 2006.183.08:08:40.10#ibcon#*before return 0, iclass 24, count 2 2006.183.08:08:40.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:08:40.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:08:40.10#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.08:08:40.10#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:40.10#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:08:40.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:08:40.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:08:40.21#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:08:40.21#ibcon#first serial, iclass 24, count 0 2006.183.08:08:40.22#ibcon#enter sib2, iclass 24, count 0 2006.183.08:08:40.22#ibcon#flushed, iclass 24, count 0 2006.183.08:08:40.22#ibcon#about to write, iclass 24, count 0 2006.183.08:08:40.22#ibcon#wrote, iclass 24, count 0 2006.183.08:08:40.22#ibcon#about to read 3, iclass 24, count 0 2006.183.08:08:40.23#ibcon#read 3, iclass 24, count 0 2006.183.08:08:40.23#ibcon#about to read 4, iclass 24, count 0 2006.183.08:08:40.23#ibcon#read 4, iclass 24, count 0 2006.183.08:08:40.23#ibcon#about to read 5, iclass 24, count 0 2006.183.08:08:40.23#ibcon#read 5, iclass 24, count 0 2006.183.08:08:40.23#ibcon#about to read 6, iclass 24, count 0 2006.183.08:08:40.23#ibcon#read 6, iclass 24, count 0 2006.183.08:08:40.23#ibcon#end of sib2, iclass 24, count 0 2006.183.08:08:40.23#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:08:40.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:08:40.23#ibcon#[25=USB\r\n] 2006.183.08:08:40.23#ibcon#*before write, iclass 24, count 0 2006.183.08:08:40.24#ibcon#enter sib2, iclass 24, count 0 2006.183.08:08:40.24#ibcon#flushed, iclass 24, count 0 2006.183.08:08:40.24#ibcon#about to write, iclass 24, count 0 2006.183.08:08:40.24#ibcon#wrote, iclass 24, count 0 2006.183.08:08:40.24#ibcon#about to read 3, iclass 24, count 0 2006.183.08:08:40.26#ibcon#read 3, iclass 24, count 0 2006.183.08:08:40.26#ibcon#about to read 4, iclass 24, count 0 2006.183.08:08:40.26#ibcon#read 4, iclass 24, count 0 2006.183.08:08:40.26#ibcon#about to read 5, iclass 24, count 0 2006.183.08:08:40.26#ibcon#read 5, iclass 24, count 0 2006.183.08:08:40.26#ibcon#about to read 6, iclass 24, count 0 2006.183.08:08:40.26#ibcon#read 6, iclass 24, count 0 2006.183.08:08:40.26#ibcon#end of sib2, iclass 24, count 0 2006.183.08:08:40.26#ibcon#*after write, iclass 24, count 0 2006.183.08:08:40.27#ibcon#*before return 0, iclass 24, count 0 2006.183.08:08:40.27#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:08:40.27#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:08:40.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:08:40.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:08:40.27$vc4f8/valo=8,852.99 2006.183.08:08:40.27#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.08:08:40.27#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.08:08:40.27#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:40.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:08:40.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:08:40.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:08:40.27#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:08:40.27#ibcon#first serial, iclass 26, count 0 2006.183.08:08:40.27#ibcon#enter sib2, iclass 26, count 0 2006.183.08:08:40.27#ibcon#flushed, iclass 26, count 0 2006.183.08:08:40.27#ibcon#about to write, iclass 26, count 0 2006.183.08:08:40.27#ibcon#wrote, iclass 26, count 0 2006.183.08:08:40.27#ibcon#about to read 3, iclass 26, count 0 2006.183.08:08:40.28#ibcon#read 3, iclass 26, count 0 2006.183.08:08:40.28#ibcon#about to read 4, iclass 26, count 0 2006.183.08:08:40.28#ibcon#read 4, iclass 26, count 0 2006.183.08:08:40.28#ibcon#about to read 5, iclass 26, count 0 2006.183.08:08:40.28#ibcon#read 5, iclass 26, count 0 2006.183.08:08:40.28#ibcon#about to read 6, iclass 26, count 0 2006.183.08:08:40.28#ibcon#read 6, iclass 26, count 0 2006.183.08:08:40.28#ibcon#end of sib2, iclass 26, count 0 2006.183.08:08:40.28#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:08:40.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:08:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:08:40.29#ibcon#*before write, iclass 26, count 0 2006.183.08:08:40.29#ibcon#enter sib2, iclass 26, count 0 2006.183.08:08:40.29#ibcon#flushed, iclass 26, count 0 2006.183.08:08:40.29#ibcon#about to write, iclass 26, count 0 2006.183.08:08:40.29#ibcon#wrote, iclass 26, count 0 2006.183.08:08:40.29#ibcon#about to read 3, iclass 26, count 0 2006.183.08:08:40.32#ibcon#read 3, iclass 26, count 0 2006.183.08:08:40.32#ibcon#about to read 4, iclass 26, count 0 2006.183.08:08:40.32#ibcon#read 4, iclass 26, count 0 2006.183.08:08:40.32#ibcon#about to read 5, iclass 26, count 0 2006.183.08:08:40.32#ibcon#read 5, iclass 26, count 0 2006.183.08:08:40.32#ibcon#about to read 6, iclass 26, count 0 2006.183.08:08:40.32#ibcon#read 6, iclass 26, count 0 2006.183.08:08:40.32#ibcon#end of sib2, iclass 26, count 0 2006.183.08:08:40.32#ibcon#*after write, iclass 26, count 0 2006.183.08:08:40.32#ibcon#*before return 0, iclass 26, count 0 2006.183.08:08:40.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:08:40.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:08:40.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:08:40.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:08:40.33$vc4f8/va=8,7 2006.183.08:08:40.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.08:08:40.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.08:08:40.33#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:40.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:08:40.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:08:40.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:08:40.38#ibcon#enter wrdev, iclass 28, count 2 2006.183.08:08:40.38#ibcon#first serial, iclass 28, count 2 2006.183.08:08:40.38#ibcon#enter sib2, iclass 28, count 2 2006.183.08:08:40.38#ibcon#flushed, iclass 28, count 2 2006.183.08:08:40.38#ibcon#about to write, iclass 28, count 2 2006.183.08:08:40.38#ibcon#wrote, iclass 28, count 2 2006.183.08:08:40.38#ibcon#about to read 3, iclass 28, count 2 2006.183.08:08:40.40#ibcon#read 3, iclass 28, count 2 2006.183.08:08:40.40#ibcon#about to read 4, iclass 28, count 2 2006.183.08:08:40.40#ibcon#read 4, iclass 28, count 2 2006.183.08:08:40.40#ibcon#about to read 5, iclass 28, count 2 2006.183.08:08:40.40#ibcon#read 5, iclass 28, count 2 2006.183.08:08:40.40#ibcon#about to read 6, iclass 28, count 2 2006.183.08:08:40.40#ibcon#read 6, iclass 28, count 2 2006.183.08:08:40.41#ibcon#end of sib2, iclass 28, count 2 2006.183.08:08:40.41#ibcon#*mode == 0, iclass 28, count 2 2006.183.08:08:40.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.08:08:40.41#ibcon#[25=AT08-07\r\n] 2006.183.08:08:40.41#ibcon#*before write, iclass 28, count 2 2006.183.08:08:40.41#ibcon#enter sib2, iclass 28, count 2 2006.183.08:08:40.41#ibcon#flushed, iclass 28, count 2 2006.183.08:08:40.41#ibcon#about to write, iclass 28, count 2 2006.183.08:08:40.41#ibcon#wrote, iclass 28, count 2 2006.183.08:08:40.41#ibcon#about to read 3, iclass 28, count 2 2006.183.08:08:40.43#ibcon#read 3, iclass 28, count 2 2006.183.08:08:40.43#ibcon#about to read 4, iclass 28, count 2 2006.183.08:08:40.43#ibcon#read 4, iclass 28, count 2 2006.183.08:08:40.43#ibcon#about to read 5, iclass 28, count 2 2006.183.08:08:40.43#ibcon#read 5, iclass 28, count 2 2006.183.08:08:40.43#ibcon#about to read 6, iclass 28, count 2 2006.183.08:08:40.43#ibcon#read 6, iclass 28, count 2 2006.183.08:08:40.43#ibcon#end of sib2, iclass 28, count 2 2006.183.08:08:40.43#ibcon#*after write, iclass 28, count 2 2006.183.08:08:40.43#ibcon#*before return 0, iclass 28, count 2 2006.183.08:08:40.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:08:40.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:08:40.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.08:08:40.44#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:40.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:08:40.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:08:40.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:08:40.55#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:08:40.55#ibcon#first serial, iclass 28, count 0 2006.183.08:08:40.55#ibcon#enter sib2, iclass 28, count 0 2006.183.08:08:40.55#ibcon#flushed, iclass 28, count 0 2006.183.08:08:40.55#ibcon#about to write, iclass 28, count 0 2006.183.08:08:40.55#ibcon#wrote, iclass 28, count 0 2006.183.08:08:40.55#ibcon#about to read 3, iclass 28, count 0 2006.183.08:08:40.57#ibcon#read 3, iclass 28, count 0 2006.183.08:08:40.57#ibcon#about to read 4, iclass 28, count 0 2006.183.08:08:40.57#ibcon#read 4, iclass 28, count 0 2006.183.08:08:40.57#ibcon#about to read 5, iclass 28, count 0 2006.183.08:08:40.57#ibcon#read 5, iclass 28, count 0 2006.183.08:08:40.57#ibcon#about to read 6, iclass 28, count 0 2006.183.08:08:40.57#ibcon#read 6, iclass 28, count 0 2006.183.08:08:40.57#ibcon#end of sib2, iclass 28, count 0 2006.183.08:08:40.57#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:08:40.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:08:40.57#ibcon#[25=USB\r\n] 2006.183.08:08:40.58#ibcon#*before write, iclass 28, count 0 2006.183.08:08:40.58#ibcon#enter sib2, iclass 28, count 0 2006.183.08:08:40.58#ibcon#flushed, iclass 28, count 0 2006.183.08:08:40.58#ibcon#about to write, iclass 28, count 0 2006.183.08:08:40.58#ibcon#wrote, iclass 28, count 0 2006.183.08:08:40.58#ibcon#about to read 3, iclass 28, count 0 2006.183.08:08:40.60#ibcon#read 3, iclass 28, count 0 2006.183.08:08:40.60#ibcon#about to read 4, iclass 28, count 0 2006.183.08:08:40.60#ibcon#read 4, iclass 28, count 0 2006.183.08:08:40.60#ibcon#about to read 5, iclass 28, count 0 2006.183.08:08:40.60#ibcon#read 5, iclass 28, count 0 2006.183.08:08:40.60#ibcon#about to read 6, iclass 28, count 0 2006.183.08:08:40.60#ibcon#read 6, iclass 28, count 0 2006.183.08:08:40.60#ibcon#end of sib2, iclass 28, count 0 2006.183.08:08:40.60#ibcon#*after write, iclass 28, count 0 2006.183.08:08:40.60#ibcon#*before return 0, iclass 28, count 0 2006.183.08:08:40.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:08:40.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:08:40.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:08:40.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:08:40.61$vc4f8/vblo=1,632.99 2006.183.08:08:40.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:08:40.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:08:40.61#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:40.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:08:40.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:08:40.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:08:40.61#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:08:40.61#ibcon#first serial, iclass 30, count 0 2006.183.08:08:40.61#ibcon#enter sib2, iclass 30, count 0 2006.183.08:08:40.61#ibcon#flushed, iclass 30, count 0 2006.183.08:08:40.61#ibcon#about to write, iclass 30, count 0 2006.183.08:08:40.61#ibcon#wrote, iclass 30, count 0 2006.183.08:08:40.61#ibcon#about to read 3, iclass 30, count 0 2006.183.08:08:40.62#ibcon#read 3, iclass 30, count 0 2006.183.08:08:40.62#ibcon#about to read 4, iclass 30, count 0 2006.183.08:08:40.62#ibcon#read 4, iclass 30, count 0 2006.183.08:08:40.62#ibcon#about to read 5, iclass 30, count 0 2006.183.08:08:40.62#ibcon#read 5, iclass 30, count 0 2006.183.08:08:40.62#ibcon#about to read 6, iclass 30, count 0 2006.183.08:08:40.62#ibcon#read 6, iclass 30, count 0 2006.183.08:08:40.62#ibcon#end of sib2, iclass 30, count 0 2006.183.08:08:40.62#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:08:40.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:08:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:08:40.63#ibcon#*before write, iclass 30, count 0 2006.183.08:08:40.63#ibcon#enter sib2, iclass 30, count 0 2006.183.08:08:40.63#ibcon#flushed, iclass 30, count 0 2006.183.08:08:40.63#ibcon#about to write, iclass 30, count 0 2006.183.08:08:40.63#ibcon#wrote, iclass 30, count 0 2006.183.08:08:40.63#ibcon#about to read 3, iclass 30, count 0 2006.183.08:08:40.66#ibcon#read 3, iclass 30, count 0 2006.183.08:08:40.66#ibcon#about to read 4, iclass 30, count 0 2006.183.08:08:40.66#ibcon#read 4, iclass 30, count 0 2006.183.08:08:40.66#ibcon#about to read 5, iclass 30, count 0 2006.183.08:08:40.66#ibcon#read 5, iclass 30, count 0 2006.183.08:08:40.66#ibcon#about to read 6, iclass 30, count 0 2006.183.08:08:40.66#ibcon#read 6, iclass 30, count 0 2006.183.08:08:40.66#ibcon#end of sib2, iclass 30, count 0 2006.183.08:08:40.66#ibcon#*after write, iclass 30, count 0 2006.183.08:08:40.66#ibcon#*before return 0, iclass 30, count 0 2006.183.08:08:40.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:08:40.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:08:40.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:08:40.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:08:40.67$vc4f8/vb=1,4 2006.183.08:08:40.67#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.08:08:40.67#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.08:08:40.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:40.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:08:40.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:08:40.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:08:40.67#ibcon#enter wrdev, iclass 32, count 2 2006.183.08:08:40.67#ibcon#first serial, iclass 32, count 2 2006.183.08:08:40.67#ibcon#enter sib2, iclass 32, count 2 2006.183.08:08:40.67#ibcon#flushed, iclass 32, count 2 2006.183.08:08:40.67#ibcon#about to write, iclass 32, count 2 2006.183.08:08:40.67#ibcon#wrote, iclass 32, count 2 2006.183.08:08:40.67#ibcon#about to read 3, iclass 32, count 2 2006.183.08:08:40.68#ibcon#read 3, iclass 32, count 2 2006.183.08:08:40.68#ibcon#about to read 4, iclass 32, count 2 2006.183.08:08:40.68#ibcon#read 4, iclass 32, count 2 2006.183.08:08:40.68#ibcon#about to read 5, iclass 32, count 2 2006.183.08:08:40.68#ibcon#read 5, iclass 32, count 2 2006.183.08:08:40.68#ibcon#about to read 6, iclass 32, count 2 2006.183.08:08:40.68#ibcon#read 6, iclass 32, count 2 2006.183.08:08:40.68#ibcon#end of sib2, iclass 32, count 2 2006.183.08:08:40.68#ibcon#*mode == 0, iclass 32, count 2 2006.183.08:08:40.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.08:08:40.68#ibcon#[27=AT01-04\r\n] 2006.183.08:08:40.69#ibcon#*before write, iclass 32, count 2 2006.183.08:08:40.69#ibcon#enter sib2, iclass 32, count 2 2006.183.08:08:40.69#ibcon#flushed, iclass 32, count 2 2006.183.08:08:40.69#ibcon#about to write, iclass 32, count 2 2006.183.08:08:40.69#ibcon#wrote, iclass 32, count 2 2006.183.08:08:40.69#ibcon#about to read 3, iclass 32, count 2 2006.183.08:08:40.71#ibcon#read 3, iclass 32, count 2 2006.183.08:08:40.71#ibcon#about to read 4, iclass 32, count 2 2006.183.08:08:40.71#ibcon#read 4, iclass 32, count 2 2006.183.08:08:40.71#ibcon#about to read 5, iclass 32, count 2 2006.183.08:08:40.71#ibcon#read 5, iclass 32, count 2 2006.183.08:08:40.71#ibcon#about to read 6, iclass 32, count 2 2006.183.08:08:40.71#ibcon#read 6, iclass 32, count 2 2006.183.08:08:40.71#ibcon#end of sib2, iclass 32, count 2 2006.183.08:08:40.71#ibcon#*after write, iclass 32, count 2 2006.183.08:08:40.71#ibcon#*before return 0, iclass 32, count 2 2006.183.08:08:40.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:08:40.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:08:40.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.08:08:40.72#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:40.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:08:40.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:08:40.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:08:40.83#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:08:40.83#ibcon#first serial, iclass 32, count 0 2006.183.08:08:40.83#ibcon#enter sib2, iclass 32, count 0 2006.183.08:08:40.83#ibcon#flushed, iclass 32, count 0 2006.183.08:08:40.83#ibcon#about to write, iclass 32, count 0 2006.183.08:08:40.83#ibcon#wrote, iclass 32, count 0 2006.183.08:08:40.83#ibcon#about to read 3, iclass 32, count 0 2006.183.08:08:40.85#ibcon#read 3, iclass 32, count 0 2006.183.08:08:40.85#ibcon#about to read 4, iclass 32, count 0 2006.183.08:08:40.85#ibcon#read 4, iclass 32, count 0 2006.183.08:08:40.85#ibcon#about to read 5, iclass 32, count 0 2006.183.08:08:40.85#ibcon#read 5, iclass 32, count 0 2006.183.08:08:40.85#ibcon#about to read 6, iclass 32, count 0 2006.183.08:08:40.85#ibcon#read 6, iclass 32, count 0 2006.183.08:08:40.85#ibcon#end of sib2, iclass 32, count 0 2006.183.08:08:40.85#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:08:40.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:08:40.85#ibcon#[27=USB\r\n] 2006.183.08:08:40.86#ibcon#*before write, iclass 32, count 0 2006.183.08:08:40.86#ibcon#enter sib2, iclass 32, count 0 2006.183.08:08:40.86#ibcon#flushed, iclass 32, count 0 2006.183.08:08:40.86#ibcon#about to write, iclass 32, count 0 2006.183.08:08:40.86#ibcon#wrote, iclass 32, count 0 2006.183.08:08:40.86#ibcon#about to read 3, iclass 32, count 0 2006.183.08:08:40.88#ibcon#read 3, iclass 32, count 0 2006.183.08:08:40.88#ibcon#about to read 4, iclass 32, count 0 2006.183.08:08:40.88#ibcon#read 4, iclass 32, count 0 2006.183.08:08:40.88#ibcon#about to read 5, iclass 32, count 0 2006.183.08:08:40.88#ibcon#read 5, iclass 32, count 0 2006.183.08:08:40.88#ibcon#about to read 6, iclass 32, count 0 2006.183.08:08:40.88#ibcon#read 6, iclass 32, count 0 2006.183.08:08:40.88#ibcon#end of sib2, iclass 32, count 0 2006.183.08:08:40.88#ibcon#*after write, iclass 32, count 0 2006.183.08:08:40.88#ibcon#*before return 0, iclass 32, count 0 2006.183.08:08:40.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:08:40.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:08:40.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:08:40.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:08:40.89$vc4f8/vblo=2,640.99 2006.183.08:08:40.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.08:08:40.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.08:08:40.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:40.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:40.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:40.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:40.89#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:08:40.89#ibcon#first serial, iclass 34, count 0 2006.183.08:08:40.89#ibcon#enter sib2, iclass 34, count 0 2006.183.08:08:40.89#ibcon#flushed, iclass 34, count 0 2006.183.08:08:40.89#ibcon#about to write, iclass 34, count 0 2006.183.08:08:40.89#ibcon#wrote, iclass 34, count 0 2006.183.08:08:40.89#ibcon#about to read 3, iclass 34, count 0 2006.183.08:08:40.90#ibcon#read 3, iclass 34, count 0 2006.183.08:08:40.90#ibcon#about to read 4, iclass 34, count 0 2006.183.08:08:40.90#ibcon#read 4, iclass 34, count 0 2006.183.08:08:40.90#ibcon#about to read 5, iclass 34, count 0 2006.183.08:08:40.90#ibcon#read 5, iclass 34, count 0 2006.183.08:08:40.90#ibcon#about to read 6, iclass 34, count 0 2006.183.08:08:40.90#ibcon#read 6, iclass 34, count 0 2006.183.08:08:40.90#ibcon#end of sib2, iclass 34, count 0 2006.183.08:08:40.90#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:08:40.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:08:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:08:40.91#ibcon#*before write, iclass 34, count 0 2006.183.08:08:40.91#ibcon#enter sib2, iclass 34, count 0 2006.183.08:08:40.91#ibcon#flushed, iclass 34, count 0 2006.183.08:08:40.91#ibcon#about to write, iclass 34, count 0 2006.183.08:08:40.91#ibcon#wrote, iclass 34, count 0 2006.183.08:08:40.91#ibcon#about to read 3, iclass 34, count 0 2006.183.08:08:40.94#ibcon#read 3, iclass 34, count 0 2006.183.08:08:40.94#ibcon#about to read 4, iclass 34, count 0 2006.183.08:08:40.94#ibcon#read 4, iclass 34, count 0 2006.183.08:08:40.94#ibcon#about to read 5, iclass 34, count 0 2006.183.08:08:40.94#ibcon#read 5, iclass 34, count 0 2006.183.08:08:40.94#ibcon#about to read 6, iclass 34, count 0 2006.183.08:08:40.94#ibcon#read 6, iclass 34, count 0 2006.183.08:08:40.94#ibcon#end of sib2, iclass 34, count 0 2006.183.08:08:40.94#ibcon#*after write, iclass 34, count 0 2006.183.08:08:40.94#ibcon#*before return 0, iclass 34, count 0 2006.183.08:08:40.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:40.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:08:40.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:08:40.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:08:40.95$vc4f8/vb=2,4 2006.183.08:08:40.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.08:08:40.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.08:08:40.95#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:40.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:41.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:41.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:41.01#ibcon#enter wrdev, iclass 36, count 2 2006.183.08:08:41.01#ibcon#first serial, iclass 36, count 2 2006.183.08:08:41.01#ibcon#enter sib2, iclass 36, count 2 2006.183.08:08:41.01#ibcon#flushed, iclass 36, count 2 2006.183.08:08:41.01#ibcon#about to write, iclass 36, count 2 2006.183.08:08:41.01#ibcon#wrote, iclass 36, count 2 2006.183.08:08:41.01#ibcon#about to read 3, iclass 36, count 2 2006.183.08:08:41.02#ibcon#read 3, iclass 36, count 2 2006.183.08:08:41.02#ibcon#about to read 4, iclass 36, count 2 2006.183.08:08:41.02#ibcon#read 4, iclass 36, count 2 2006.183.08:08:41.02#ibcon#about to read 5, iclass 36, count 2 2006.183.08:08:41.02#ibcon#read 5, iclass 36, count 2 2006.183.08:08:41.02#ibcon#about to read 6, iclass 36, count 2 2006.183.08:08:41.02#ibcon#read 6, iclass 36, count 2 2006.183.08:08:41.02#ibcon#end of sib2, iclass 36, count 2 2006.183.08:08:41.02#ibcon#*mode == 0, iclass 36, count 2 2006.183.08:08:41.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.08:08:41.02#ibcon#[27=AT02-04\r\n] 2006.183.08:08:41.02#ibcon#*before write, iclass 36, count 2 2006.183.08:08:41.02#ibcon#enter sib2, iclass 36, count 2 2006.183.08:08:41.03#ibcon#flushed, iclass 36, count 2 2006.183.08:08:41.03#ibcon#about to write, iclass 36, count 2 2006.183.08:08:41.03#ibcon#wrote, iclass 36, count 2 2006.183.08:08:41.03#ibcon#about to read 3, iclass 36, count 2 2006.183.08:08:41.05#ibcon#read 3, iclass 36, count 2 2006.183.08:08:41.05#ibcon#about to read 4, iclass 36, count 2 2006.183.08:08:41.05#ibcon#read 4, iclass 36, count 2 2006.183.08:08:41.05#ibcon#about to read 5, iclass 36, count 2 2006.183.08:08:41.05#ibcon#read 5, iclass 36, count 2 2006.183.08:08:41.05#ibcon#about to read 6, iclass 36, count 2 2006.183.08:08:41.05#ibcon#read 6, iclass 36, count 2 2006.183.08:08:41.05#ibcon#end of sib2, iclass 36, count 2 2006.183.08:08:41.05#ibcon#*after write, iclass 36, count 2 2006.183.08:08:41.06#ibcon#*before return 0, iclass 36, count 2 2006.183.08:08:41.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:41.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:08:41.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.08:08:41.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:41.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:41.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:41.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:41.17#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:08:41.17#ibcon#first serial, iclass 36, count 0 2006.183.08:08:41.17#ibcon#enter sib2, iclass 36, count 0 2006.183.08:08:41.17#ibcon#flushed, iclass 36, count 0 2006.183.08:08:41.17#ibcon#about to write, iclass 36, count 0 2006.183.08:08:41.17#ibcon#wrote, iclass 36, count 0 2006.183.08:08:41.17#ibcon#about to read 3, iclass 36, count 0 2006.183.08:08:41.21#ibcon#read 3, iclass 36, count 0 2006.183.08:08:41.21#ibcon#about to read 4, iclass 36, count 0 2006.183.08:08:41.21#ibcon#read 4, iclass 36, count 0 2006.183.08:08:41.21#ibcon#about to read 5, iclass 36, count 0 2006.183.08:08:41.21#ibcon#read 5, iclass 36, count 0 2006.183.08:08:41.21#ibcon#about to read 6, iclass 36, count 0 2006.183.08:08:41.21#ibcon#read 6, iclass 36, count 0 2006.183.08:08:41.21#ibcon#end of sib2, iclass 36, count 0 2006.183.08:08:41.21#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:08:41.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:08:41.21#ibcon#[27=USB\r\n] 2006.183.08:08:41.21#ibcon#*before write, iclass 36, count 0 2006.183.08:08:41.21#ibcon#enter sib2, iclass 36, count 0 2006.183.08:08:41.21#ibcon#flushed, iclass 36, count 0 2006.183.08:08:41.21#ibcon#about to write, iclass 36, count 0 2006.183.08:08:41.21#ibcon#wrote, iclass 36, count 0 2006.183.08:08:41.21#ibcon#about to read 3, iclass 36, count 0 2006.183.08:08:41.23#ibcon#read 3, iclass 36, count 0 2006.183.08:08:41.23#ibcon#about to read 4, iclass 36, count 0 2006.183.08:08:41.23#ibcon#read 4, iclass 36, count 0 2006.183.08:08:41.23#ibcon#about to read 5, iclass 36, count 0 2006.183.08:08:41.23#ibcon#read 5, iclass 36, count 0 2006.183.08:08:41.23#ibcon#about to read 6, iclass 36, count 0 2006.183.08:08:41.23#ibcon#read 6, iclass 36, count 0 2006.183.08:08:41.23#ibcon#end of sib2, iclass 36, count 0 2006.183.08:08:41.23#ibcon#*after write, iclass 36, count 0 2006.183.08:08:41.23#ibcon#*before return 0, iclass 36, count 0 2006.183.08:08:41.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:41.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:08:41.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:08:41.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:08:41.24$vc4f8/vblo=3,656.99 2006.183.08:08:41.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.08:08:41.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.08:08:41.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:41.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:41.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:41.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:41.24#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:08:41.24#ibcon#first serial, iclass 38, count 0 2006.183.08:08:41.24#ibcon#enter sib2, iclass 38, count 0 2006.183.08:08:41.24#ibcon#flushed, iclass 38, count 0 2006.183.08:08:41.24#ibcon#about to write, iclass 38, count 0 2006.183.08:08:41.24#ibcon#wrote, iclass 38, count 0 2006.183.08:08:41.24#ibcon#about to read 3, iclass 38, count 0 2006.183.08:08:41.25#ibcon#read 3, iclass 38, count 0 2006.183.08:08:41.25#ibcon#about to read 4, iclass 38, count 0 2006.183.08:08:41.25#ibcon#read 4, iclass 38, count 0 2006.183.08:08:41.25#ibcon#about to read 5, iclass 38, count 0 2006.183.08:08:41.25#ibcon#read 5, iclass 38, count 0 2006.183.08:08:41.25#ibcon#about to read 6, iclass 38, count 0 2006.183.08:08:41.25#ibcon#read 6, iclass 38, count 0 2006.183.08:08:41.25#ibcon#end of sib2, iclass 38, count 0 2006.183.08:08:41.25#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:08:41.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:08:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:08:41.26#ibcon#*before write, iclass 38, count 0 2006.183.08:08:41.26#ibcon#enter sib2, iclass 38, count 0 2006.183.08:08:41.26#ibcon#flushed, iclass 38, count 0 2006.183.08:08:41.26#ibcon#about to write, iclass 38, count 0 2006.183.08:08:41.26#ibcon#wrote, iclass 38, count 0 2006.183.08:08:41.26#ibcon#about to read 3, iclass 38, count 0 2006.183.08:08:41.29#ibcon#read 3, iclass 38, count 0 2006.183.08:08:41.29#ibcon#about to read 4, iclass 38, count 0 2006.183.08:08:41.29#ibcon#read 4, iclass 38, count 0 2006.183.08:08:41.29#ibcon#about to read 5, iclass 38, count 0 2006.183.08:08:41.29#ibcon#read 5, iclass 38, count 0 2006.183.08:08:41.29#ibcon#about to read 6, iclass 38, count 0 2006.183.08:08:41.29#ibcon#read 6, iclass 38, count 0 2006.183.08:08:41.29#ibcon#end of sib2, iclass 38, count 0 2006.183.08:08:41.29#ibcon#*after write, iclass 38, count 0 2006.183.08:08:41.29#ibcon#*before return 0, iclass 38, count 0 2006.183.08:08:41.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:41.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:08:41.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:08:41.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:08:41.30$vc4f8/vb=3,4 2006.183.08:08:41.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.08:08:41.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.08:08:41.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:41.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:41.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:41.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:41.35#ibcon#enter wrdev, iclass 40, count 2 2006.183.08:08:41.35#ibcon#first serial, iclass 40, count 2 2006.183.08:08:41.35#ibcon#enter sib2, iclass 40, count 2 2006.183.08:08:41.35#ibcon#flushed, iclass 40, count 2 2006.183.08:08:41.35#ibcon#about to write, iclass 40, count 2 2006.183.08:08:41.35#ibcon#wrote, iclass 40, count 2 2006.183.08:08:41.35#ibcon#about to read 3, iclass 40, count 2 2006.183.08:08:41.37#ibcon#read 3, iclass 40, count 2 2006.183.08:08:41.37#ibcon#about to read 4, iclass 40, count 2 2006.183.08:08:41.37#ibcon#read 4, iclass 40, count 2 2006.183.08:08:41.37#ibcon#about to read 5, iclass 40, count 2 2006.183.08:08:41.37#ibcon#read 5, iclass 40, count 2 2006.183.08:08:41.37#ibcon#about to read 6, iclass 40, count 2 2006.183.08:08:41.37#ibcon#read 6, iclass 40, count 2 2006.183.08:08:41.37#ibcon#end of sib2, iclass 40, count 2 2006.183.08:08:41.37#ibcon#*mode == 0, iclass 40, count 2 2006.183.08:08:41.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.08:08:41.37#ibcon#[27=AT03-04\r\n] 2006.183.08:08:41.37#ibcon#*before write, iclass 40, count 2 2006.183.08:08:41.38#ibcon#enter sib2, iclass 40, count 2 2006.183.08:08:41.38#ibcon#flushed, iclass 40, count 2 2006.183.08:08:41.38#ibcon#about to write, iclass 40, count 2 2006.183.08:08:41.38#ibcon#wrote, iclass 40, count 2 2006.183.08:08:41.38#ibcon#about to read 3, iclass 40, count 2 2006.183.08:08:41.40#ibcon#read 3, iclass 40, count 2 2006.183.08:08:41.40#ibcon#about to read 4, iclass 40, count 2 2006.183.08:08:41.40#ibcon#read 4, iclass 40, count 2 2006.183.08:08:41.40#ibcon#about to read 5, iclass 40, count 2 2006.183.08:08:41.40#ibcon#read 5, iclass 40, count 2 2006.183.08:08:41.40#ibcon#about to read 6, iclass 40, count 2 2006.183.08:08:41.40#ibcon#read 6, iclass 40, count 2 2006.183.08:08:41.40#ibcon#end of sib2, iclass 40, count 2 2006.183.08:08:41.40#ibcon#*after write, iclass 40, count 2 2006.183.08:08:41.40#ibcon#*before return 0, iclass 40, count 2 2006.183.08:08:41.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:41.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:08:41.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.08:08:41.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:41.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:41.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:41.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:41.52#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:08:41.52#ibcon#first serial, iclass 40, count 0 2006.183.08:08:41.52#ibcon#enter sib2, iclass 40, count 0 2006.183.08:08:41.52#ibcon#flushed, iclass 40, count 0 2006.183.08:08:41.52#ibcon#about to write, iclass 40, count 0 2006.183.08:08:41.52#ibcon#wrote, iclass 40, count 0 2006.183.08:08:41.52#ibcon#about to read 3, iclass 40, count 0 2006.183.08:08:41.54#ibcon#read 3, iclass 40, count 0 2006.183.08:08:41.54#ibcon#about to read 4, iclass 40, count 0 2006.183.08:08:41.54#ibcon#read 4, iclass 40, count 0 2006.183.08:08:41.54#ibcon#about to read 5, iclass 40, count 0 2006.183.08:08:41.54#ibcon#read 5, iclass 40, count 0 2006.183.08:08:41.54#ibcon#about to read 6, iclass 40, count 0 2006.183.08:08:41.54#ibcon#read 6, iclass 40, count 0 2006.183.08:08:41.54#ibcon#end of sib2, iclass 40, count 0 2006.183.08:08:41.54#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:08:41.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:08:41.54#ibcon#[27=USB\r\n] 2006.183.08:08:41.54#ibcon#*before write, iclass 40, count 0 2006.183.08:08:41.55#ibcon#enter sib2, iclass 40, count 0 2006.183.08:08:41.55#ibcon#flushed, iclass 40, count 0 2006.183.08:08:41.55#ibcon#about to write, iclass 40, count 0 2006.183.08:08:41.55#ibcon#wrote, iclass 40, count 0 2006.183.08:08:41.55#ibcon#about to read 3, iclass 40, count 0 2006.183.08:08:41.57#ibcon#read 3, iclass 40, count 0 2006.183.08:08:41.57#ibcon#about to read 4, iclass 40, count 0 2006.183.08:08:41.57#ibcon#read 4, iclass 40, count 0 2006.183.08:08:41.57#ibcon#about to read 5, iclass 40, count 0 2006.183.08:08:41.57#ibcon#read 5, iclass 40, count 0 2006.183.08:08:41.57#ibcon#about to read 6, iclass 40, count 0 2006.183.08:08:41.57#ibcon#read 6, iclass 40, count 0 2006.183.08:08:41.57#ibcon#end of sib2, iclass 40, count 0 2006.183.08:08:41.57#ibcon#*after write, iclass 40, count 0 2006.183.08:08:41.57#ibcon#*before return 0, iclass 40, count 0 2006.183.08:08:41.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:41.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:08:41.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:08:41.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:08:41.58$vc4f8/vblo=4,712.99 2006.183.08:08:41.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.08:08:41.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.08:08:41.58#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:41.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:41.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:41.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:41.58#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:08:41.58#ibcon#first serial, iclass 4, count 0 2006.183.08:08:41.58#ibcon#enter sib2, iclass 4, count 0 2006.183.08:08:41.58#ibcon#flushed, iclass 4, count 0 2006.183.08:08:41.58#ibcon#about to write, iclass 4, count 0 2006.183.08:08:41.58#ibcon#wrote, iclass 4, count 0 2006.183.08:08:41.58#ibcon#about to read 3, iclass 4, count 0 2006.183.08:08:41.59#ibcon#read 3, iclass 4, count 0 2006.183.08:08:41.59#ibcon#about to read 4, iclass 4, count 0 2006.183.08:08:41.59#ibcon#read 4, iclass 4, count 0 2006.183.08:08:41.59#ibcon#about to read 5, iclass 4, count 0 2006.183.08:08:41.59#ibcon#read 5, iclass 4, count 0 2006.183.08:08:41.59#ibcon#about to read 6, iclass 4, count 0 2006.183.08:08:41.59#ibcon#read 6, iclass 4, count 0 2006.183.08:08:41.59#ibcon#end of sib2, iclass 4, count 0 2006.183.08:08:41.59#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:08:41.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:08:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:08:41.59#ibcon#*before write, iclass 4, count 0 2006.183.08:08:41.60#ibcon#enter sib2, iclass 4, count 0 2006.183.08:08:41.60#ibcon#flushed, iclass 4, count 0 2006.183.08:08:41.60#ibcon#about to write, iclass 4, count 0 2006.183.08:08:41.60#ibcon#wrote, iclass 4, count 0 2006.183.08:08:41.60#ibcon#about to read 3, iclass 4, count 0 2006.183.08:08:41.63#ibcon#read 3, iclass 4, count 0 2006.183.08:08:41.63#ibcon#about to read 4, iclass 4, count 0 2006.183.08:08:41.63#ibcon#read 4, iclass 4, count 0 2006.183.08:08:41.63#ibcon#about to read 5, iclass 4, count 0 2006.183.08:08:41.63#ibcon#read 5, iclass 4, count 0 2006.183.08:08:41.63#ibcon#about to read 6, iclass 4, count 0 2006.183.08:08:41.63#ibcon#read 6, iclass 4, count 0 2006.183.08:08:41.63#ibcon#end of sib2, iclass 4, count 0 2006.183.08:08:41.63#ibcon#*after write, iclass 4, count 0 2006.183.08:08:41.63#ibcon#*before return 0, iclass 4, count 0 2006.183.08:08:41.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:41.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:08:41.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:08:41.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:08:41.64$vc4f8/vb=4,4 2006.183.08:08:41.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.08:08:41.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.08:08:41.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:41.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:41.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:41.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:41.69#ibcon#enter wrdev, iclass 6, count 2 2006.183.08:08:41.69#ibcon#first serial, iclass 6, count 2 2006.183.08:08:41.69#ibcon#enter sib2, iclass 6, count 2 2006.183.08:08:41.69#ibcon#flushed, iclass 6, count 2 2006.183.08:08:41.69#ibcon#about to write, iclass 6, count 2 2006.183.08:08:41.69#ibcon#wrote, iclass 6, count 2 2006.183.08:08:41.69#ibcon#about to read 3, iclass 6, count 2 2006.183.08:08:41.71#ibcon#read 3, iclass 6, count 2 2006.183.08:08:41.71#ibcon#about to read 4, iclass 6, count 2 2006.183.08:08:41.71#ibcon#read 4, iclass 6, count 2 2006.183.08:08:41.71#ibcon#about to read 5, iclass 6, count 2 2006.183.08:08:41.71#ibcon#read 5, iclass 6, count 2 2006.183.08:08:41.71#ibcon#about to read 6, iclass 6, count 2 2006.183.08:08:41.71#ibcon#read 6, iclass 6, count 2 2006.183.08:08:41.71#ibcon#end of sib2, iclass 6, count 2 2006.183.08:08:41.71#ibcon#*mode == 0, iclass 6, count 2 2006.183.08:08:41.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.08:08:41.72#ibcon#[27=AT04-04\r\n] 2006.183.08:08:41.72#ibcon#*before write, iclass 6, count 2 2006.183.08:08:41.72#ibcon#enter sib2, iclass 6, count 2 2006.183.08:08:41.72#ibcon#flushed, iclass 6, count 2 2006.183.08:08:41.72#ibcon#about to write, iclass 6, count 2 2006.183.08:08:41.72#ibcon#wrote, iclass 6, count 2 2006.183.08:08:41.72#ibcon#about to read 3, iclass 6, count 2 2006.183.08:08:41.74#ibcon#read 3, iclass 6, count 2 2006.183.08:08:41.74#ibcon#about to read 4, iclass 6, count 2 2006.183.08:08:41.74#ibcon#read 4, iclass 6, count 2 2006.183.08:08:41.74#ibcon#about to read 5, iclass 6, count 2 2006.183.08:08:41.74#ibcon#read 5, iclass 6, count 2 2006.183.08:08:41.74#ibcon#about to read 6, iclass 6, count 2 2006.183.08:08:41.74#ibcon#read 6, iclass 6, count 2 2006.183.08:08:41.74#ibcon#end of sib2, iclass 6, count 2 2006.183.08:08:41.74#ibcon#*after write, iclass 6, count 2 2006.183.08:08:41.75#ibcon#*before return 0, iclass 6, count 2 2006.183.08:08:41.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:41.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:08:41.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.08:08:41.75#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:41.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:41.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:41.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:41.86#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:08:41.86#ibcon#first serial, iclass 6, count 0 2006.183.08:08:41.86#ibcon#enter sib2, iclass 6, count 0 2006.183.08:08:41.86#ibcon#flushed, iclass 6, count 0 2006.183.08:08:41.86#ibcon#about to write, iclass 6, count 0 2006.183.08:08:41.86#ibcon#wrote, iclass 6, count 0 2006.183.08:08:41.86#ibcon#about to read 3, iclass 6, count 0 2006.183.08:08:41.88#ibcon#read 3, iclass 6, count 0 2006.183.08:08:41.88#ibcon#about to read 4, iclass 6, count 0 2006.183.08:08:41.88#ibcon#read 4, iclass 6, count 0 2006.183.08:08:41.88#ibcon#about to read 5, iclass 6, count 0 2006.183.08:08:41.88#ibcon#read 5, iclass 6, count 0 2006.183.08:08:41.88#ibcon#about to read 6, iclass 6, count 0 2006.183.08:08:41.88#ibcon#read 6, iclass 6, count 0 2006.183.08:08:41.88#ibcon#end of sib2, iclass 6, count 0 2006.183.08:08:41.88#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:08:41.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:08:41.88#ibcon#[27=USB\r\n] 2006.183.08:08:41.88#ibcon#*before write, iclass 6, count 0 2006.183.08:08:41.89#ibcon#enter sib2, iclass 6, count 0 2006.183.08:08:41.89#ibcon#flushed, iclass 6, count 0 2006.183.08:08:41.89#ibcon#about to write, iclass 6, count 0 2006.183.08:08:41.89#ibcon#wrote, iclass 6, count 0 2006.183.08:08:41.89#ibcon#about to read 3, iclass 6, count 0 2006.183.08:08:41.91#ibcon#read 3, iclass 6, count 0 2006.183.08:08:41.91#ibcon#about to read 4, iclass 6, count 0 2006.183.08:08:41.91#ibcon#read 4, iclass 6, count 0 2006.183.08:08:41.91#ibcon#about to read 5, iclass 6, count 0 2006.183.08:08:41.91#ibcon#read 5, iclass 6, count 0 2006.183.08:08:41.91#ibcon#about to read 6, iclass 6, count 0 2006.183.08:08:41.91#ibcon#read 6, iclass 6, count 0 2006.183.08:08:41.91#ibcon#end of sib2, iclass 6, count 0 2006.183.08:08:41.91#ibcon#*after write, iclass 6, count 0 2006.183.08:08:41.91#ibcon#*before return 0, iclass 6, count 0 2006.183.08:08:41.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:41.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:08:41.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:08:41.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:08:41.92$vc4f8/vblo=5,744.99 2006.183.08:08:41.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.08:08:41.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.08:08:41.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:41.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:41.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:41.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:41.92#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:08:41.92#ibcon#first serial, iclass 10, count 0 2006.183.08:08:41.92#ibcon#enter sib2, iclass 10, count 0 2006.183.08:08:41.92#ibcon#flushed, iclass 10, count 0 2006.183.08:08:41.92#ibcon#about to write, iclass 10, count 0 2006.183.08:08:41.92#ibcon#wrote, iclass 10, count 0 2006.183.08:08:41.92#ibcon#about to read 3, iclass 10, count 0 2006.183.08:08:41.94#ibcon#read 3, iclass 10, count 0 2006.183.08:08:41.94#ibcon#about to read 4, iclass 10, count 0 2006.183.08:08:41.94#ibcon#read 4, iclass 10, count 0 2006.183.08:08:41.94#ibcon#about to read 5, iclass 10, count 0 2006.183.08:08:41.94#ibcon#read 5, iclass 10, count 0 2006.183.08:08:41.94#ibcon#about to read 6, iclass 10, count 0 2006.183.08:08:41.94#ibcon#read 6, iclass 10, count 0 2006.183.08:08:41.94#ibcon#end of sib2, iclass 10, count 0 2006.183.08:08:41.94#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:08:41.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:08:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:08:41.94#ibcon#*before write, iclass 10, count 0 2006.183.08:08:41.94#ibcon#enter sib2, iclass 10, count 0 2006.183.08:08:41.94#ibcon#flushed, iclass 10, count 0 2006.183.08:08:41.94#ibcon#about to write, iclass 10, count 0 2006.183.08:08:41.94#ibcon#wrote, iclass 10, count 0 2006.183.08:08:41.94#ibcon#about to read 3, iclass 10, count 0 2006.183.08:08:41.98#ibcon#read 3, iclass 10, count 0 2006.183.08:08:41.98#ibcon#about to read 4, iclass 10, count 0 2006.183.08:08:41.98#ibcon#read 4, iclass 10, count 0 2006.183.08:08:41.98#ibcon#about to read 5, iclass 10, count 0 2006.183.08:08:41.98#ibcon#read 5, iclass 10, count 0 2006.183.08:08:41.98#ibcon#about to read 6, iclass 10, count 0 2006.183.08:08:41.98#ibcon#read 6, iclass 10, count 0 2006.183.08:08:41.98#ibcon#end of sib2, iclass 10, count 0 2006.183.08:08:41.99#ibcon#*after write, iclass 10, count 0 2006.183.08:08:41.99#ibcon#*before return 0, iclass 10, count 0 2006.183.08:08:41.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:41.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:08:41.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:08:41.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:08:41.99$vc4f8/vb=5,4 2006.183.08:08:41.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.08:08:41.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.08:08:41.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:41.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:42.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:42.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:42.04#ibcon#enter wrdev, iclass 12, count 2 2006.183.08:08:42.04#ibcon#first serial, iclass 12, count 2 2006.183.08:08:42.04#ibcon#enter sib2, iclass 12, count 2 2006.183.08:08:42.04#ibcon#flushed, iclass 12, count 2 2006.183.08:08:42.04#ibcon#about to write, iclass 12, count 2 2006.183.08:08:42.04#ibcon#wrote, iclass 12, count 2 2006.183.08:08:42.04#ibcon#about to read 3, iclass 12, count 2 2006.183.08:08:42.05#ibcon#read 3, iclass 12, count 2 2006.183.08:08:42.05#ibcon#about to read 4, iclass 12, count 2 2006.183.08:08:42.05#ibcon#read 4, iclass 12, count 2 2006.183.08:08:42.05#ibcon#about to read 5, iclass 12, count 2 2006.183.08:08:42.05#ibcon#read 5, iclass 12, count 2 2006.183.08:08:42.05#ibcon#about to read 6, iclass 12, count 2 2006.183.08:08:42.05#ibcon#read 6, iclass 12, count 2 2006.183.08:08:42.05#ibcon#end of sib2, iclass 12, count 2 2006.183.08:08:42.05#ibcon#*mode == 0, iclass 12, count 2 2006.183.08:08:42.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.08:08:42.05#ibcon#[27=AT05-04\r\n] 2006.183.08:08:42.05#ibcon#*before write, iclass 12, count 2 2006.183.08:08:42.05#ibcon#enter sib2, iclass 12, count 2 2006.183.08:08:42.06#ibcon#flushed, iclass 12, count 2 2006.183.08:08:42.06#ibcon#about to write, iclass 12, count 2 2006.183.08:08:42.06#ibcon#wrote, iclass 12, count 2 2006.183.08:08:42.06#ibcon#about to read 3, iclass 12, count 2 2006.183.08:08:42.08#ibcon#read 3, iclass 12, count 2 2006.183.08:08:42.08#ibcon#about to read 4, iclass 12, count 2 2006.183.08:08:42.08#ibcon#read 4, iclass 12, count 2 2006.183.08:08:42.08#ibcon#about to read 5, iclass 12, count 2 2006.183.08:08:42.08#ibcon#read 5, iclass 12, count 2 2006.183.08:08:42.08#ibcon#about to read 6, iclass 12, count 2 2006.183.08:08:42.08#ibcon#read 6, iclass 12, count 2 2006.183.08:08:42.08#ibcon#end of sib2, iclass 12, count 2 2006.183.08:08:42.08#ibcon#*after write, iclass 12, count 2 2006.183.08:08:42.09#ibcon#*before return 0, iclass 12, count 2 2006.183.08:08:42.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:42.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:08:42.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.08:08:42.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:42.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:42.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:42.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:42.20#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:08:42.20#ibcon#first serial, iclass 12, count 0 2006.183.08:08:42.20#ibcon#enter sib2, iclass 12, count 0 2006.183.08:08:42.20#ibcon#flushed, iclass 12, count 0 2006.183.08:08:42.20#ibcon#about to write, iclass 12, count 0 2006.183.08:08:42.20#ibcon#wrote, iclass 12, count 0 2006.183.08:08:42.20#ibcon#about to read 3, iclass 12, count 0 2006.183.08:08:42.22#ibcon#read 3, iclass 12, count 0 2006.183.08:08:42.22#ibcon#about to read 4, iclass 12, count 0 2006.183.08:08:42.22#ibcon#read 4, iclass 12, count 0 2006.183.08:08:42.22#ibcon#about to read 5, iclass 12, count 0 2006.183.08:08:42.22#ibcon#read 5, iclass 12, count 0 2006.183.08:08:42.22#ibcon#about to read 6, iclass 12, count 0 2006.183.08:08:42.22#ibcon#read 6, iclass 12, count 0 2006.183.08:08:42.22#ibcon#end of sib2, iclass 12, count 0 2006.183.08:08:42.22#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:08:42.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:08:42.22#ibcon#[27=USB\r\n] 2006.183.08:08:42.22#ibcon#*before write, iclass 12, count 0 2006.183.08:08:42.22#ibcon#enter sib2, iclass 12, count 0 2006.183.08:08:42.23#ibcon#flushed, iclass 12, count 0 2006.183.08:08:42.23#ibcon#about to write, iclass 12, count 0 2006.183.08:08:42.23#ibcon#wrote, iclass 12, count 0 2006.183.08:08:42.23#ibcon#about to read 3, iclass 12, count 0 2006.183.08:08:42.25#ibcon#read 3, iclass 12, count 0 2006.183.08:08:42.25#ibcon#about to read 4, iclass 12, count 0 2006.183.08:08:42.25#ibcon#read 4, iclass 12, count 0 2006.183.08:08:42.25#ibcon#about to read 5, iclass 12, count 0 2006.183.08:08:42.25#ibcon#read 5, iclass 12, count 0 2006.183.08:08:42.25#ibcon#about to read 6, iclass 12, count 0 2006.183.08:08:42.25#ibcon#read 6, iclass 12, count 0 2006.183.08:08:42.25#ibcon#end of sib2, iclass 12, count 0 2006.183.08:08:42.26#ibcon#*after write, iclass 12, count 0 2006.183.08:08:42.26#ibcon#*before return 0, iclass 12, count 0 2006.183.08:08:42.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:42.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:08:42.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:08:42.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:08:42.26$vc4f8/vblo=6,752.99 2006.183.08:08:42.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:08:42.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:08:42.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:08:42.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:42.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:42.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:42.26#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:08:42.26#ibcon#first serial, iclass 14, count 0 2006.183.08:08:42.26#ibcon#enter sib2, iclass 14, count 0 2006.183.08:08:42.26#ibcon#flushed, iclass 14, count 0 2006.183.08:08:42.26#ibcon#about to write, iclass 14, count 0 2006.183.08:08:42.26#ibcon#wrote, iclass 14, count 0 2006.183.08:08:42.26#ibcon#about to read 3, iclass 14, count 0 2006.183.08:08:42.27#ibcon#read 3, iclass 14, count 0 2006.183.08:08:42.27#ibcon#about to read 4, iclass 14, count 0 2006.183.08:08:42.27#ibcon#read 4, iclass 14, count 0 2006.183.08:08:42.27#ibcon#about to read 5, iclass 14, count 0 2006.183.08:08:42.27#ibcon#read 5, iclass 14, count 0 2006.183.08:08:42.27#ibcon#about to read 6, iclass 14, count 0 2006.183.08:08:42.27#ibcon#read 6, iclass 14, count 0 2006.183.08:08:42.27#ibcon#end of sib2, iclass 14, count 0 2006.183.08:08:42.27#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:08:42.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:08:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:08:42.28#ibcon#*before write, iclass 14, count 0 2006.183.08:08:42.28#ibcon#enter sib2, iclass 14, count 0 2006.183.08:08:42.28#ibcon#flushed, iclass 14, count 0 2006.183.08:08:42.28#ibcon#about to write, iclass 14, count 0 2006.183.08:08:42.28#ibcon#wrote, iclass 14, count 0 2006.183.08:08:42.28#ibcon#about to read 3, iclass 14, count 0 2006.183.08:08:42.31#ibcon#read 3, iclass 14, count 0 2006.183.08:08:42.31#ibcon#about to read 4, iclass 14, count 0 2006.183.08:08:42.31#ibcon#read 4, iclass 14, count 0 2006.183.08:08:42.31#ibcon#about to read 5, iclass 14, count 0 2006.183.08:08:42.31#ibcon#read 5, iclass 14, count 0 2006.183.08:08:42.31#ibcon#about to read 6, iclass 14, count 0 2006.183.08:08:42.31#ibcon#read 6, iclass 14, count 0 2006.183.08:08:42.31#ibcon#end of sib2, iclass 14, count 0 2006.183.08:08:42.31#ibcon#*after write, iclass 14, count 0 2006.183.08:08:42.31#ibcon#*before return 0, iclass 14, count 0 2006.183.08:08:42.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:42.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:08:42.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:08:42.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:08:42.32$vc4f8/vb=6,4 2006.183.08:08:42.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.08:08:42.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.08:08:42.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:08:42.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:42.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:42.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:42.37#ibcon#enter wrdev, iclass 16, count 2 2006.183.08:08:42.37#ibcon#first serial, iclass 16, count 2 2006.183.08:08:42.37#ibcon#enter sib2, iclass 16, count 2 2006.183.08:08:42.37#ibcon#flushed, iclass 16, count 2 2006.183.08:08:42.37#ibcon#about to write, iclass 16, count 2 2006.183.08:08:42.37#ibcon#wrote, iclass 16, count 2 2006.183.08:08:42.37#ibcon#about to read 3, iclass 16, count 2 2006.183.08:08:42.39#ibcon#read 3, iclass 16, count 2 2006.183.08:08:42.39#ibcon#about to read 4, iclass 16, count 2 2006.183.08:08:42.39#ibcon#read 4, iclass 16, count 2 2006.183.08:08:42.39#ibcon#about to read 5, iclass 16, count 2 2006.183.08:08:42.39#ibcon#read 5, iclass 16, count 2 2006.183.08:08:42.39#ibcon#about to read 6, iclass 16, count 2 2006.183.08:08:42.39#ibcon#read 6, iclass 16, count 2 2006.183.08:08:42.39#ibcon#end of sib2, iclass 16, count 2 2006.183.08:08:42.39#ibcon#*mode == 0, iclass 16, count 2 2006.183.08:08:42.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.08:08:42.39#ibcon#[27=AT06-04\r\n] 2006.183.08:08:42.40#ibcon#*before write, iclass 16, count 2 2006.183.08:08:42.40#ibcon#enter sib2, iclass 16, count 2 2006.183.08:08:42.40#ibcon#flushed, iclass 16, count 2 2006.183.08:08:42.40#ibcon#about to write, iclass 16, count 2 2006.183.08:08:42.40#ibcon#wrote, iclass 16, count 2 2006.183.08:08:42.40#ibcon#about to read 3, iclass 16, count 2 2006.183.08:08:42.42#ibcon#read 3, iclass 16, count 2 2006.183.08:08:42.42#ibcon#about to read 4, iclass 16, count 2 2006.183.08:08:42.42#ibcon#read 4, iclass 16, count 2 2006.183.08:08:42.42#ibcon#about to read 5, iclass 16, count 2 2006.183.08:08:42.42#ibcon#read 5, iclass 16, count 2 2006.183.08:08:42.42#ibcon#about to read 6, iclass 16, count 2 2006.183.08:08:42.42#ibcon#read 6, iclass 16, count 2 2006.183.08:08:42.42#ibcon#end of sib2, iclass 16, count 2 2006.183.08:08:42.42#ibcon#*after write, iclass 16, count 2 2006.183.08:08:42.42#ibcon#*before return 0, iclass 16, count 2 2006.183.08:08:42.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:42.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:08:42.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.08:08:42.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:08:42.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:42.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:42.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:42.54#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:08:42.54#ibcon#first serial, iclass 16, count 0 2006.183.08:08:42.54#ibcon#enter sib2, iclass 16, count 0 2006.183.08:08:42.54#ibcon#flushed, iclass 16, count 0 2006.183.08:08:42.54#ibcon#about to write, iclass 16, count 0 2006.183.08:08:42.54#ibcon#wrote, iclass 16, count 0 2006.183.08:08:42.54#ibcon#about to read 3, iclass 16, count 0 2006.183.08:08:42.56#ibcon#read 3, iclass 16, count 0 2006.183.08:08:42.56#ibcon#about to read 4, iclass 16, count 0 2006.183.08:08:42.56#ibcon#read 4, iclass 16, count 0 2006.183.08:08:42.56#ibcon#about to read 5, iclass 16, count 0 2006.183.08:08:42.56#ibcon#read 5, iclass 16, count 0 2006.183.08:08:42.56#ibcon#about to read 6, iclass 16, count 0 2006.183.08:08:42.56#ibcon#read 6, iclass 16, count 0 2006.183.08:08:42.56#ibcon#end of sib2, iclass 16, count 0 2006.183.08:08:42.56#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:08:42.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:08:42.56#ibcon#[27=USB\r\n] 2006.183.08:08:42.56#ibcon#*before write, iclass 16, count 0 2006.183.08:08:42.57#ibcon#enter sib2, iclass 16, count 0 2006.183.08:08:42.57#ibcon#flushed, iclass 16, count 0 2006.183.08:08:42.57#ibcon#about to write, iclass 16, count 0 2006.183.08:08:42.57#ibcon#wrote, iclass 16, count 0 2006.183.08:08:42.57#ibcon#about to read 3, iclass 16, count 0 2006.183.08:08:42.59#ibcon#read 3, iclass 16, count 0 2006.183.08:08:42.59#ibcon#about to read 4, iclass 16, count 0 2006.183.08:08:42.59#ibcon#read 4, iclass 16, count 0 2006.183.08:08:42.59#ibcon#about to read 5, iclass 16, count 0 2006.183.08:08:42.59#ibcon#read 5, iclass 16, count 0 2006.183.08:08:42.59#ibcon#about to read 6, iclass 16, count 0 2006.183.08:08:42.59#ibcon#read 6, iclass 16, count 0 2006.183.08:08:42.59#ibcon#end of sib2, iclass 16, count 0 2006.183.08:08:42.59#ibcon#*after write, iclass 16, count 0 2006.183.08:08:42.59#ibcon#*before return 0, iclass 16, count 0 2006.183.08:08:42.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:42.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:08:42.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:08:42.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:08:42.60$vc4f8/vabw=wide 2006.183.08:08:42.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:08:42.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:08:42.60#ibcon#ireg 8 cls_cnt 0 2006.183.08:08:42.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:42.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:42.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:42.60#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:08:42.60#ibcon#first serial, iclass 18, count 0 2006.183.08:08:42.60#ibcon#enter sib2, iclass 18, count 0 2006.183.08:08:42.60#ibcon#flushed, iclass 18, count 0 2006.183.08:08:42.60#ibcon#about to write, iclass 18, count 0 2006.183.08:08:42.60#ibcon#wrote, iclass 18, count 0 2006.183.08:08:42.60#ibcon#about to read 3, iclass 18, count 0 2006.183.08:08:42.62#ibcon#read 3, iclass 18, count 0 2006.183.08:08:42.62#ibcon#about to read 4, iclass 18, count 0 2006.183.08:08:42.62#ibcon#read 4, iclass 18, count 0 2006.183.08:08:42.62#ibcon#about to read 5, iclass 18, count 0 2006.183.08:08:42.62#ibcon#read 5, iclass 18, count 0 2006.183.08:08:42.62#ibcon#about to read 6, iclass 18, count 0 2006.183.08:08:42.62#ibcon#read 6, iclass 18, count 0 2006.183.08:08:42.62#ibcon#end of sib2, iclass 18, count 0 2006.183.08:08:42.62#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:08:42.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:08:42.62#ibcon#[25=BW32\r\n] 2006.183.08:08:42.62#ibcon#*before write, iclass 18, count 0 2006.183.08:08:42.62#ibcon#enter sib2, iclass 18, count 0 2006.183.08:08:42.62#ibcon#flushed, iclass 18, count 0 2006.183.08:08:42.62#ibcon#about to write, iclass 18, count 0 2006.183.08:08:42.62#ibcon#wrote, iclass 18, count 0 2006.183.08:08:42.62#ibcon#about to read 3, iclass 18, count 0 2006.183.08:08:42.65#ibcon#read 3, iclass 18, count 0 2006.183.08:08:42.65#ibcon#about to read 4, iclass 18, count 0 2006.183.08:08:42.65#ibcon#read 4, iclass 18, count 0 2006.183.08:08:42.65#ibcon#about to read 5, iclass 18, count 0 2006.183.08:08:42.65#ibcon#read 5, iclass 18, count 0 2006.183.08:08:42.65#ibcon#about to read 6, iclass 18, count 0 2006.183.08:08:42.65#ibcon#read 6, iclass 18, count 0 2006.183.08:08:42.65#ibcon#end of sib2, iclass 18, count 0 2006.183.08:08:42.66#ibcon#*after write, iclass 18, count 0 2006.183.08:08:42.66#ibcon#*before return 0, iclass 18, count 0 2006.183.08:08:42.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:42.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:08:42.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:08:42.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:08:42.66$vc4f8/vbbw=wide 2006.183.08:08:42.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.08:08:42.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.08:08:42.66#ibcon#ireg 8 cls_cnt 0 2006.183.08:08:42.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:08:42.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:08:42.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:08:42.72#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:08:42.72#ibcon#first serial, iclass 20, count 0 2006.183.08:08:42.72#ibcon#enter sib2, iclass 20, count 0 2006.183.08:08:42.72#ibcon#flushed, iclass 20, count 0 2006.183.08:08:42.72#ibcon#about to write, iclass 20, count 0 2006.183.08:08:42.72#ibcon#wrote, iclass 20, count 0 2006.183.08:08:42.72#ibcon#about to read 3, iclass 20, count 0 2006.183.08:08:42.73#ibcon#read 3, iclass 20, count 0 2006.183.08:08:42.73#ibcon#about to read 4, iclass 20, count 0 2006.183.08:08:42.73#ibcon#read 4, iclass 20, count 0 2006.183.08:08:42.73#ibcon#about to read 5, iclass 20, count 0 2006.183.08:08:42.73#ibcon#read 5, iclass 20, count 0 2006.183.08:08:42.73#ibcon#about to read 6, iclass 20, count 0 2006.183.08:08:42.73#ibcon#read 6, iclass 20, count 0 2006.183.08:08:42.73#ibcon#end of sib2, iclass 20, count 0 2006.183.08:08:42.73#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:08:42.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:08:42.74#ibcon#[27=BW32\r\n] 2006.183.08:08:42.74#ibcon#*before write, iclass 20, count 0 2006.183.08:08:42.74#ibcon#enter sib2, iclass 20, count 0 2006.183.08:08:42.74#ibcon#flushed, iclass 20, count 0 2006.183.08:08:42.74#ibcon#about to write, iclass 20, count 0 2006.183.08:08:42.74#ibcon#wrote, iclass 20, count 0 2006.183.08:08:42.74#ibcon#about to read 3, iclass 20, count 0 2006.183.08:08:42.76#ibcon#read 3, iclass 20, count 0 2006.183.08:08:42.76#ibcon#about to read 4, iclass 20, count 0 2006.183.08:08:42.76#ibcon#read 4, iclass 20, count 0 2006.183.08:08:42.76#ibcon#about to read 5, iclass 20, count 0 2006.183.08:08:42.76#ibcon#read 5, iclass 20, count 0 2006.183.08:08:42.76#ibcon#about to read 6, iclass 20, count 0 2006.183.08:08:42.76#ibcon#read 6, iclass 20, count 0 2006.183.08:08:42.76#ibcon#end of sib2, iclass 20, count 0 2006.183.08:08:42.76#ibcon#*after write, iclass 20, count 0 2006.183.08:08:42.77#ibcon#*before return 0, iclass 20, count 0 2006.183.08:08:42.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:08:42.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:08:42.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:08:42.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:08:42.77$4f8m12a/ifd4f 2006.183.08:08:42.77$ifd4f/lo= 2006.183.08:08:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:08:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:08:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:08:42.77$ifd4f/patch= 2006.183.08:08:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:08:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:08:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:08:42.77$4f8m12a/"form=m,16.000,1:2 2006.183.08:08:42.77$4f8m12a/"tpicd 2006.183.08:08:42.77$4f8m12a/echo=off 2006.183.08:08:42.77$4f8m12a/xlog=off 2006.183.08:08:42.77:!2006.183.08:09:10 2006.183.08:08:54.14#trakl#Source acquired 2006.183.08:08:55.15#flagr#flagr/antenna,acquired 2006.183.08:09:10.02:preob 2006.183.08:09:11.15/onsource/TRACKING 2006.183.08:09:11.15:!2006.183.08:09:20 2006.183.08:09:20.02:data_valid=on 2006.183.08:09:20.02:midob 2006.183.08:09:21.15/onsource/TRACKING 2006.183.08:09:21.15/wx/28.34,996.5,85 2006.183.08:09:21.19/cable/+6.4510E-03 2006.183.08:09:22.28/va/01,08,usb,yes,29,31 2006.183.08:09:22.28/va/02,07,usb,yes,29,31 2006.183.08:09:22.28/va/03,06,usb,yes,31,31 2006.183.08:09:22.28/va/04,07,usb,yes,30,32 2006.183.08:09:22.28/va/05,07,usb,yes,32,33 2006.183.08:09:22.28/va/06,06,usb,yes,31,31 2006.183.08:09:22.28/va/07,06,usb,yes,31,31 2006.183.08:09:22.28/va/08,07,usb,yes,30,29 2006.183.08:09:22.51/valo/01,532.99,yes,locked 2006.183.08:09:22.51/valo/02,572.99,yes,locked 2006.183.08:09:22.51/valo/03,672.99,yes,locked 2006.183.08:09:22.51/valo/04,832.99,yes,locked 2006.183.08:09:22.51/valo/05,652.99,yes,locked 2006.183.08:09:22.51/valo/06,772.99,yes,locked 2006.183.08:09:22.51/valo/07,832.99,yes,locked 2006.183.08:09:22.51/valo/08,852.99,yes,locked 2006.183.08:09:23.60/vb/01,04,usb,yes,29,28 2006.183.08:09:23.60/vb/02,04,usb,yes,31,33 2006.183.08:09:23.60/vb/03,04,usb,yes,28,31 2006.183.08:09:23.60/vb/04,04,usb,yes,29,29 2006.183.08:09:23.60/vb/05,04,usb,yes,27,31 2006.183.08:09:23.60/vb/06,04,usb,yes,28,31 2006.183.08:09:23.60/vb/07,04,usb,yes,30,30 2006.183.08:09:23.60/vb/08,04,usb,yes,28,31 2006.183.08:09:23.83/vblo/01,632.99,yes,locked 2006.183.08:09:23.83/vblo/02,640.99,yes,locked 2006.183.08:09:23.83/vblo/03,656.99,yes,locked 2006.183.08:09:23.83/vblo/04,712.99,yes,locked 2006.183.08:09:23.83/vblo/05,744.99,yes,locked 2006.183.08:09:23.83/vblo/06,752.99,yes,locked 2006.183.08:09:23.83/vblo/07,734.99,yes,locked 2006.183.08:09:23.83/vblo/08,744.99,yes,locked 2006.183.08:09:23.98/vabw/8 2006.183.08:09:24.13/vbbw/8 2006.183.08:09:24.27/xfe/off,on,14.5 2006.183.08:09:24.64/ifatt/23,28,28,28 2006.183.08:09:25.07/fmout-gps/S +3.34E-07 2006.183.08:09:25.15:!2006.183.08:10:20 2006.183.08:10:20.02:data_valid=off 2006.183.08:10:20.02:postob 2006.183.08:10:20.12/cable/+6.4509E-03 2006.183.08:10:20.13/wx/28.35,996.5,85 2006.183.08:10:21.07/fmout-gps/S +3.33E-07 2006.183.08:10:21.08:scan_name=183-0811,k06183,60 2006.183.08:10:21.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.183.08:10:22.15#flagr#flagr/antenna,new-source 2006.183.08:10:22.15:checkk5 2006.183.08:10:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:10:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:10:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:10:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:10:24.02/chk_obsdata//k5ts1/T1830809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:10:24.39/chk_obsdata//k5ts2/T1830809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:10:24.76/chk_obsdata//k5ts3/T1830809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:10:25.13/chk_obsdata//k5ts4/T1830809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:10:25.82/k5log//k5ts1_log_newline 2006.183.08:10:26.51/k5log//k5ts2_log_newline 2006.183.08:10:27.24/k5log//k5ts3_log_newline 2006.183.08:10:27.93/k5log//k5ts4_log_newline 2006.183.08:10:27.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:10:27.95:4f8m12a=2 2006.183.08:10:27.95$4f8m12a/echo=on 2006.183.08:10:27.95$4f8m12a/pcalon 2006.183.08:10:27.95$pcalon/"no phase cal control is implemented here 2006.183.08:10:27.95$4f8m12a/"tpicd=stop 2006.183.08:10:27.95$4f8m12a/vc4f8 2006.183.08:10:27.95$vc4f8/valo=1,532.99 2006.183.08:10:27.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:10:27.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:10:27.96#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:27.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:10:27.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:10:27.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:10:27.96#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:10:27.96#ibcon#first serial, iclass 28, count 0 2006.183.08:10:27.96#ibcon#enter sib2, iclass 28, count 0 2006.183.08:10:27.96#ibcon#flushed, iclass 28, count 0 2006.183.08:10:27.96#ibcon#about to write, iclass 28, count 0 2006.183.08:10:27.96#ibcon#wrote, iclass 28, count 0 2006.183.08:10:27.96#ibcon#about to read 3, iclass 28, count 0 2006.183.08:10:28.00#ibcon#read 3, iclass 28, count 0 2006.183.08:10:28.00#ibcon#about to read 4, iclass 28, count 0 2006.183.08:10:28.00#ibcon#read 4, iclass 28, count 0 2006.183.08:10:28.00#ibcon#about to read 5, iclass 28, count 0 2006.183.08:10:28.00#ibcon#read 5, iclass 28, count 0 2006.183.08:10:28.00#ibcon#about to read 6, iclass 28, count 0 2006.183.08:10:28.00#ibcon#read 6, iclass 28, count 0 2006.183.08:10:28.00#ibcon#end of sib2, iclass 28, count 0 2006.183.08:10:28.00#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:10:28.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:10:28.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:10:28.00#ibcon#*before write, iclass 28, count 0 2006.183.08:10:28.00#ibcon#enter sib2, iclass 28, count 0 2006.183.08:10:28.00#ibcon#flushed, iclass 28, count 0 2006.183.08:10:28.00#ibcon#about to write, iclass 28, count 0 2006.183.08:10:28.00#ibcon#wrote, iclass 28, count 0 2006.183.08:10:28.00#ibcon#about to read 3, iclass 28, count 0 2006.183.08:10:28.01#abcon#{5=INTERFACE CLEAR} 2006.183.08:10:28.04#ibcon#read 3, iclass 28, count 0 2006.183.08:10:28.04#ibcon#about to read 4, iclass 28, count 0 2006.183.08:10:28.04#ibcon#read 4, iclass 28, count 0 2006.183.08:10:28.04#ibcon#about to read 5, iclass 28, count 0 2006.183.08:10:28.04#ibcon#read 5, iclass 28, count 0 2006.183.08:10:28.04#ibcon#about to read 6, iclass 28, count 0 2006.183.08:10:28.04#ibcon#read 6, iclass 28, count 0 2006.183.08:10:28.04#ibcon#end of sib2, iclass 28, count 0 2006.183.08:10:28.04#ibcon#*after write, iclass 28, count 0 2006.183.08:10:28.04#ibcon#*before return 0, iclass 28, count 0 2006.183.08:10:28.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:10:28.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:10:28.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:10:28.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:10:28.04$vc4f8/va=1,8 2006.183.08:10:28.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.08:10:28.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.08:10:28.04#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:28.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:10:28.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:10:28.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:10:28.05#ibcon#enter wrdev, iclass 32, count 2 2006.183.08:10:28.05#ibcon#first serial, iclass 32, count 2 2006.183.08:10:28.05#ibcon#enter sib2, iclass 32, count 2 2006.183.08:10:28.05#ibcon#flushed, iclass 32, count 2 2006.183.08:10:28.05#ibcon#about to write, iclass 32, count 2 2006.183.08:10:28.05#ibcon#wrote, iclass 32, count 2 2006.183.08:10:28.05#ibcon#about to read 3, iclass 32, count 2 2006.183.08:10:28.06#ibcon#read 3, iclass 32, count 2 2006.183.08:10:28.06#ibcon#about to read 4, iclass 32, count 2 2006.183.08:10:28.06#ibcon#read 4, iclass 32, count 2 2006.183.08:10:28.06#ibcon#about to read 5, iclass 32, count 2 2006.183.08:10:28.06#ibcon#read 5, iclass 32, count 2 2006.183.08:10:28.06#ibcon#about to read 6, iclass 32, count 2 2006.183.08:10:28.06#ibcon#read 6, iclass 32, count 2 2006.183.08:10:28.06#ibcon#end of sib2, iclass 32, count 2 2006.183.08:10:28.06#ibcon#*mode == 0, iclass 32, count 2 2006.183.08:10:28.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.08:10:28.06#ibcon#[25=AT01-08\r\n] 2006.183.08:10:28.06#ibcon#*before write, iclass 32, count 2 2006.183.08:10:28.06#ibcon#enter sib2, iclass 32, count 2 2006.183.08:10:28.06#ibcon#flushed, iclass 32, count 2 2006.183.08:10:28.06#ibcon#about to write, iclass 32, count 2 2006.183.08:10:28.06#ibcon#wrote, iclass 32, count 2 2006.183.08:10:28.06#ibcon#about to read 3, iclass 32, count 2 2006.183.08:10:28.08#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:10:28.09#ibcon#read 3, iclass 32, count 2 2006.183.08:10:28.09#ibcon#about to read 4, iclass 32, count 2 2006.183.08:10:28.09#ibcon#read 4, iclass 32, count 2 2006.183.08:10:28.09#ibcon#about to read 5, iclass 32, count 2 2006.183.08:10:28.09#ibcon#read 5, iclass 32, count 2 2006.183.08:10:28.09#ibcon#about to read 6, iclass 32, count 2 2006.183.08:10:28.09#ibcon#read 6, iclass 32, count 2 2006.183.08:10:28.09#ibcon#end of sib2, iclass 32, count 2 2006.183.08:10:28.09#ibcon#*after write, iclass 32, count 2 2006.183.08:10:28.09#ibcon#*before return 0, iclass 32, count 2 2006.183.08:10:28.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:10:28.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:10:28.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.08:10:28.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:28.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:10:28.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:10:28.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:10:28.21#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:10:28.21#ibcon#first serial, iclass 32, count 0 2006.183.08:10:28.21#ibcon#enter sib2, iclass 32, count 0 2006.183.08:10:28.21#ibcon#flushed, iclass 32, count 0 2006.183.08:10:28.21#ibcon#about to write, iclass 32, count 0 2006.183.08:10:28.21#ibcon#wrote, iclass 32, count 0 2006.183.08:10:28.21#ibcon#about to read 3, iclass 32, count 0 2006.183.08:10:28.23#ibcon#read 3, iclass 32, count 0 2006.183.08:10:28.23#ibcon#about to read 4, iclass 32, count 0 2006.183.08:10:28.23#ibcon#read 4, iclass 32, count 0 2006.183.08:10:28.23#ibcon#about to read 5, iclass 32, count 0 2006.183.08:10:28.23#ibcon#read 5, iclass 32, count 0 2006.183.08:10:28.23#ibcon#about to read 6, iclass 32, count 0 2006.183.08:10:28.23#ibcon#read 6, iclass 32, count 0 2006.183.08:10:28.23#ibcon#end of sib2, iclass 32, count 0 2006.183.08:10:28.23#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:10:28.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:10:28.23#ibcon#[25=USB\r\n] 2006.183.08:10:28.23#ibcon#*before write, iclass 32, count 0 2006.183.08:10:28.23#ibcon#enter sib2, iclass 32, count 0 2006.183.08:10:28.23#ibcon#flushed, iclass 32, count 0 2006.183.08:10:28.23#ibcon#about to write, iclass 32, count 0 2006.183.08:10:28.23#ibcon#wrote, iclass 32, count 0 2006.183.08:10:28.23#ibcon#about to read 3, iclass 32, count 0 2006.183.08:10:28.26#ibcon#read 3, iclass 32, count 0 2006.183.08:10:28.26#ibcon#about to read 4, iclass 32, count 0 2006.183.08:10:28.26#ibcon#read 4, iclass 32, count 0 2006.183.08:10:28.26#ibcon#about to read 5, iclass 32, count 0 2006.183.08:10:28.26#ibcon#read 5, iclass 32, count 0 2006.183.08:10:28.26#ibcon#about to read 6, iclass 32, count 0 2006.183.08:10:28.26#ibcon#read 6, iclass 32, count 0 2006.183.08:10:28.26#ibcon#end of sib2, iclass 32, count 0 2006.183.08:10:28.26#ibcon#*after write, iclass 32, count 0 2006.183.08:10:28.26#ibcon#*before return 0, iclass 32, count 0 2006.183.08:10:28.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:10:28.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:10:28.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:10:28.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:10:28.26$vc4f8/valo=2,572.99 2006.183.08:10:28.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.08:10:28.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.08:10:28.27#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:28.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:28.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:28.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:28.27#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:10:28.27#ibcon#first serial, iclass 35, count 0 2006.183.08:10:28.27#ibcon#enter sib2, iclass 35, count 0 2006.183.08:10:28.27#ibcon#flushed, iclass 35, count 0 2006.183.08:10:28.27#ibcon#about to write, iclass 35, count 0 2006.183.08:10:28.27#ibcon#wrote, iclass 35, count 0 2006.183.08:10:28.27#ibcon#about to read 3, iclass 35, count 0 2006.183.08:10:28.29#ibcon#read 3, iclass 35, count 0 2006.183.08:10:28.29#ibcon#about to read 4, iclass 35, count 0 2006.183.08:10:28.29#ibcon#read 4, iclass 35, count 0 2006.183.08:10:28.29#ibcon#about to read 5, iclass 35, count 0 2006.183.08:10:28.29#ibcon#read 5, iclass 35, count 0 2006.183.08:10:28.29#ibcon#about to read 6, iclass 35, count 0 2006.183.08:10:28.29#ibcon#read 6, iclass 35, count 0 2006.183.08:10:28.29#ibcon#end of sib2, iclass 35, count 0 2006.183.08:10:28.29#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:10:28.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:10:28.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:10:28.29#ibcon#*before write, iclass 35, count 0 2006.183.08:10:28.29#ibcon#enter sib2, iclass 35, count 0 2006.183.08:10:28.29#ibcon#flushed, iclass 35, count 0 2006.183.08:10:28.29#ibcon#about to write, iclass 35, count 0 2006.183.08:10:28.29#ibcon#wrote, iclass 35, count 0 2006.183.08:10:28.29#ibcon#about to read 3, iclass 35, count 0 2006.183.08:10:28.33#ibcon#read 3, iclass 35, count 0 2006.183.08:10:28.33#ibcon#about to read 4, iclass 35, count 0 2006.183.08:10:28.33#ibcon#read 4, iclass 35, count 0 2006.183.08:10:28.33#ibcon#about to read 5, iclass 35, count 0 2006.183.08:10:28.33#ibcon#read 5, iclass 35, count 0 2006.183.08:10:28.33#ibcon#about to read 6, iclass 35, count 0 2006.183.08:10:28.33#ibcon#read 6, iclass 35, count 0 2006.183.08:10:28.33#ibcon#end of sib2, iclass 35, count 0 2006.183.08:10:28.33#ibcon#*after write, iclass 35, count 0 2006.183.08:10:28.33#ibcon#*before return 0, iclass 35, count 0 2006.183.08:10:28.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:28.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:28.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:10:28.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:10:28.33$vc4f8/va=2,7 2006.183.08:10:28.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.08:10:28.34#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.08:10:28.34#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:28.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:28.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:28.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:28.37#ibcon#enter wrdev, iclass 37, count 2 2006.183.08:10:28.37#ibcon#first serial, iclass 37, count 2 2006.183.08:10:28.37#ibcon#enter sib2, iclass 37, count 2 2006.183.08:10:28.37#ibcon#flushed, iclass 37, count 2 2006.183.08:10:28.37#ibcon#about to write, iclass 37, count 2 2006.183.08:10:28.37#ibcon#wrote, iclass 37, count 2 2006.183.08:10:28.37#ibcon#about to read 3, iclass 37, count 2 2006.183.08:10:28.40#ibcon#read 3, iclass 37, count 2 2006.183.08:10:28.40#ibcon#about to read 4, iclass 37, count 2 2006.183.08:10:28.40#ibcon#read 4, iclass 37, count 2 2006.183.08:10:28.40#ibcon#about to read 5, iclass 37, count 2 2006.183.08:10:28.40#ibcon#read 5, iclass 37, count 2 2006.183.08:10:28.40#ibcon#about to read 6, iclass 37, count 2 2006.183.08:10:28.40#ibcon#read 6, iclass 37, count 2 2006.183.08:10:28.40#ibcon#end of sib2, iclass 37, count 2 2006.183.08:10:28.40#ibcon#*mode == 0, iclass 37, count 2 2006.183.08:10:28.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.08:10:28.40#ibcon#[25=AT02-07\r\n] 2006.183.08:10:28.40#ibcon#*before write, iclass 37, count 2 2006.183.08:10:28.40#ibcon#enter sib2, iclass 37, count 2 2006.183.08:10:28.40#ibcon#flushed, iclass 37, count 2 2006.183.08:10:28.40#ibcon#about to write, iclass 37, count 2 2006.183.08:10:28.40#ibcon#wrote, iclass 37, count 2 2006.183.08:10:28.40#ibcon#about to read 3, iclass 37, count 2 2006.183.08:10:28.43#ibcon#read 3, iclass 37, count 2 2006.183.08:10:28.43#ibcon#about to read 4, iclass 37, count 2 2006.183.08:10:28.43#ibcon#read 4, iclass 37, count 2 2006.183.08:10:28.43#ibcon#about to read 5, iclass 37, count 2 2006.183.08:10:28.43#ibcon#read 5, iclass 37, count 2 2006.183.08:10:28.43#ibcon#about to read 6, iclass 37, count 2 2006.183.08:10:28.43#ibcon#read 6, iclass 37, count 2 2006.183.08:10:28.43#ibcon#end of sib2, iclass 37, count 2 2006.183.08:10:28.43#ibcon#*after write, iclass 37, count 2 2006.183.08:10:28.43#ibcon#*before return 0, iclass 37, count 2 2006.183.08:10:28.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:28.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:28.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.08:10:28.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:28.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:28.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:28.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:28.55#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:10:28.55#ibcon#first serial, iclass 37, count 0 2006.183.08:10:28.55#ibcon#enter sib2, iclass 37, count 0 2006.183.08:10:28.55#ibcon#flushed, iclass 37, count 0 2006.183.08:10:28.55#ibcon#about to write, iclass 37, count 0 2006.183.08:10:28.55#ibcon#wrote, iclass 37, count 0 2006.183.08:10:28.55#ibcon#about to read 3, iclass 37, count 0 2006.183.08:10:28.57#ibcon#read 3, iclass 37, count 0 2006.183.08:10:28.57#ibcon#about to read 4, iclass 37, count 0 2006.183.08:10:28.57#ibcon#read 4, iclass 37, count 0 2006.183.08:10:28.57#ibcon#about to read 5, iclass 37, count 0 2006.183.08:10:28.57#ibcon#read 5, iclass 37, count 0 2006.183.08:10:28.57#ibcon#about to read 6, iclass 37, count 0 2006.183.08:10:28.57#ibcon#read 6, iclass 37, count 0 2006.183.08:10:28.57#ibcon#end of sib2, iclass 37, count 0 2006.183.08:10:28.57#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:10:28.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:10:28.57#ibcon#[25=USB\r\n] 2006.183.08:10:28.57#ibcon#*before write, iclass 37, count 0 2006.183.08:10:28.57#ibcon#enter sib2, iclass 37, count 0 2006.183.08:10:28.57#ibcon#flushed, iclass 37, count 0 2006.183.08:10:28.57#ibcon#about to write, iclass 37, count 0 2006.183.08:10:28.57#ibcon#wrote, iclass 37, count 0 2006.183.08:10:28.57#ibcon#about to read 3, iclass 37, count 0 2006.183.08:10:28.60#ibcon#read 3, iclass 37, count 0 2006.183.08:10:28.60#ibcon#about to read 4, iclass 37, count 0 2006.183.08:10:28.60#ibcon#read 4, iclass 37, count 0 2006.183.08:10:28.60#ibcon#about to read 5, iclass 37, count 0 2006.183.08:10:28.60#ibcon#read 5, iclass 37, count 0 2006.183.08:10:28.60#ibcon#about to read 6, iclass 37, count 0 2006.183.08:10:28.60#ibcon#read 6, iclass 37, count 0 2006.183.08:10:28.60#ibcon#end of sib2, iclass 37, count 0 2006.183.08:10:28.60#ibcon#*after write, iclass 37, count 0 2006.183.08:10:28.60#ibcon#*before return 0, iclass 37, count 0 2006.183.08:10:28.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:28.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:28.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:10:28.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:10:28.60$vc4f8/valo=3,672.99 2006.183.08:10:28.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.08:10:28.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.08:10:28.60#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:28.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:28.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:28.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:28.61#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:10:28.61#ibcon#first serial, iclass 39, count 0 2006.183.08:10:28.61#ibcon#enter sib2, iclass 39, count 0 2006.183.08:10:28.61#ibcon#flushed, iclass 39, count 0 2006.183.08:10:28.61#ibcon#about to write, iclass 39, count 0 2006.183.08:10:28.61#ibcon#wrote, iclass 39, count 0 2006.183.08:10:28.61#ibcon#about to read 3, iclass 39, count 0 2006.183.08:10:28.62#ibcon#read 3, iclass 39, count 0 2006.183.08:10:28.62#ibcon#about to read 4, iclass 39, count 0 2006.183.08:10:28.62#ibcon#read 4, iclass 39, count 0 2006.183.08:10:28.62#ibcon#about to read 5, iclass 39, count 0 2006.183.08:10:28.62#ibcon#read 5, iclass 39, count 0 2006.183.08:10:28.62#ibcon#about to read 6, iclass 39, count 0 2006.183.08:10:28.62#ibcon#read 6, iclass 39, count 0 2006.183.08:10:28.62#ibcon#end of sib2, iclass 39, count 0 2006.183.08:10:28.62#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:10:28.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:10:28.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:10:28.62#ibcon#*before write, iclass 39, count 0 2006.183.08:10:28.62#ibcon#enter sib2, iclass 39, count 0 2006.183.08:10:28.62#ibcon#flushed, iclass 39, count 0 2006.183.08:10:28.62#ibcon#about to write, iclass 39, count 0 2006.183.08:10:28.62#ibcon#wrote, iclass 39, count 0 2006.183.08:10:28.62#ibcon#about to read 3, iclass 39, count 0 2006.183.08:10:28.66#ibcon#read 3, iclass 39, count 0 2006.183.08:10:28.66#ibcon#about to read 4, iclass 39, count 0 2006.183.08:10:28.66#ibcon#read 4, iclass 39, count 0 2006.183.08:10:28.66#ibcon#about to read 5, iclass 39, count 0 2006.183.08:10:28.66#ibcon#read 5, iclass 39, count 0 2006.183.08:10:28.66#ibcon#about to read 6, iclass 39, count 0 2006.183.08:10:28.66#ibcon#read 6, iclass 39, count 0 2006.183.08:10:28.66#ibcon#end of sib2, iclass 39, count 0 2006.183.08:10:28.66#ibcon#*after write, iclass 39, count 0 2006.183.08:10:28.66#ibcon#*before return 0, iclass 39, count 0 2006.183.08:10:28.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:28.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:28.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:10:28.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:10:28.66$vc4f8/va=3,6 2006.183.08:10:28.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.183.08:10:28.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.183.08:10:28.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:28.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:28.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:28.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:28.72#ibcon#enter wrdev, iclass 3, count 2 2006.183.08:10:28.72#ibcon#first serial, iclass 3, count 2 2006.183.08:10:28.72#ibcon#enter sib2, iclass 3, count 2 2006.183.08:10:28.72#ibcon#flushed, iclass 3, count 2 2006.183.08:10:28.72#ibcon#about to write, iclass 3, count 2 2006.183.08:10:28.72#ibcon#wrote, iclass 3, count 2 2006.183.08:10:28.72#ibcon#about to read 3, iclass 3, count 2 2006.183.08:10:28.73#ibcon#read 3, iclass 3, count 2 2006.183.08:10:28.73#ibcon#about to read 4, iclass 3, count 2 2006.183.08:10:28.73#ibcon#read 4, iclass 3, count 2 2006.183.08:10:28.73#ibcon#about to read 5, iclass 3, count 2 2006.183.08:10:28.73#ibcon#read 5, iclass 3, count 2 2006.183.08:10:28.73#ibcon#about to read 6, iclass 3, count 2 2006.183.08:10:28.73#ibcon#read 6, iclass 3, count 2 2006.183.08:10:28.73#ibcon#end of sib2, iclass 3, count 2 2006.183.08:10:28.73#ibcon#*mode == 0, iclass 3, count 2 2006.183.08:10:28.73#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.183.08:10:28.73#ibcon#[25=AT03-06\r\n] 2006.183.08:10:28.73#ibcon#*before write, iclass 3, count 2 2006.183.08:10:28.73#ibcon#enter sib2, iclass 3, count 2 2006.183.08:10:28.73#ibcon#flushed, iclass 3, count 2 2006.183.08:10:28.73#ibcon#about to write, iclass 3, count 2 2006.183.08:10:28.73#ibcon#wrote, iclass 3, count 2 2006.183.08:10:28.73#ibcon#about to read 3, iclass 3, count 2 2006.183.08:10:28.76#ibcon#read 3, iclass 3, count 2 2006.183.08:10:28.76#ibcon#about to read 4, iclass 3, count 2 2006.183.08:10:28.76#ibcon#read 4, iclass 3, count 2 2006.183.08:10:28.76#ibcon#about to read 5, iclass 3, count 2 2006.183.08:10:28.76#ibcon#read 5, iclass 3, count 2 2006.183.08:10:28.76#ibcon#about to read 6, iclass 3, count 2 2006.183.08:10:28.76#ibcon#read 6, iclass 3, count 2 2006.183.08:10:28.76#ibcon#end of sib2, iclass 3, count 2 2006.183.08:10:28.76#ibcon#*after write, iclass 3, count 2 2006.183.08:10:28.76#ibcon#*before return 0, iclass 3, count 2 2006.183.08:10:28.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:28.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:28.76#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.183.08:10:28.76#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:28.76#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:28.88#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:28.88#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:28.88#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:10:28.88#ibcon#first serial, iclass 3, count 0 2006.183.08:10:28.88#ibcon#enter sib2, iclass 3, count 0 2006.183.08:10:28.88#ibcon#flushed, iclass 3, count 0 2006.183.08:10:28.88#ibcon#about to write, iclass 3, count 0 2006.183.08:10:28.88#ibcon#wrote, iclass 3, count 0 2006.183.08:10:28.88#ibcon#about to read 3, iclass 3, count 0 2006.183.08:10:28.90#ibcon#read 3, iclass 3, count 0 2006.183.08:10:28.90#ibcon#about to read 4, iclass 3, count 0 2006.183.08:10:28.90#ibcon#read 4, iclass 3, count 0 2006.183.08:10:28.90#ibcon#about to read 5, iclass 3, count 0 2006.183.08:10:28.90#ibcon#read 5, iclass 3, count 0 2006.183.08:10:28.90#ibcon#about to read 6, iclass 3, count 0 2006.183.08:10:28.90#ibcon#read 6, iclass 3, count 0 2006.183.08:10:28.90#ibcon#end of sib2, iclass 3, count 0 2006.183.08:10:28.90#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:10:28.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:10:28.90#ibcon#[25=USB\r\n] 2006.183.08:10:28.90#ibcon#*before write, iclass 3, count 0 2006.183.08:10:28.90#ibcon#enter sib2, iclass 3, count 0 2006.183.08:10:28.90#ibcon#flushed, iclass 3, count 0 2006.183.08:10:28.90#ibcon#about to write, iclass 3, count 0 2006.183.08:10:28.90#ibcon#wrote, iclass 3, count 0 2006.183.08:10:28.90#ibcon#about to read 3, iclass 3, count 0 2006.183.08:10:28.93#ibcon#read 3, iclass 3, count 0 2006.183.08:10:28.93#ibcon#about to read 4, iclass 3, count 0 2006.183.08:10:28.93#ibcon#read 4, iclass 3, count 0 2006.183.08:10:28.93#ibcon#about to read 5, iclass 3, count 0 2006.183.08:10:28.93#ibcon#read 5, iclass 3, count 0 2006.183.08:10:28.93#ibcon#about to read 6, iclass 3, count 0 2006.183.08:10:28.93#ibcon#read 6, iclass 3, count 0 2006.183.08:10:28.93#ibcon#end of sib2, iclass 3, count 0 2006.183.08:10:28.93#ibcon#*after write, iclass 3, count 0 2006.183.08:10:28.93#ibcon#*before return 0, iclass 3, count 0 2006.183.08:10:28.93#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:28.93#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:28.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:10:28.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:10:28.93$vc4f8/valo=4,832.99 2006.183.08:10:28.93#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.08:10:28.93#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.08:10:28.93#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:28.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:28.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:28.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:28.94#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:10:28.94#ibcon#first serial, iclass 5, count 0 2006.183.08:10:28.94#ibcon#enter sib2, iclass 5, count 0 2006.183.08:10:28.94#ibcon#flushed, iclass 5, count 0 2006.183.08:10:28.94#ibcon#about to write, iclass 5, count 0 2006.183.08:10:28.94#ibcon#wrote, iclass 5, count 0 2006.183.08:10:28.94#ibcon#about to read 3, iclass 5, count 0 2006.183.08:10:28.95#ibcon#read 3, iclass 5, count 0 2006.183.08:10:28.95#ibcon#about to read 4, iclass 5, count 0 2006.183.08:10:28.95#ibcon#read 4, iclass 5, count 0 2006.183.08:10:28.95#ibcon#about to read 5, iclass 5, count 0 2006.183.08:10:28.95#ibcon#read 5, iclass 5, count 0 2006.183.08:10:28.95#ibcon#about to read 6, iclass 5, count 0 2006.183.08:10:28.95#ibcon#read 6, iclass 5, count 0 2006.183.08:10:28.95#ibcon#end of sib2, iclass 5, count 0 2006.183.08:10:28.95#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:10:28.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:10:28.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:10:28.95#ibcon#*before write, iclass 5, count 0 2006.183.08:10:28.95#ibcon#enter sib2, iclass 5, count 0 2006.183.08:10:28.95#ibcon#flushed, iclass 5, count 0 2006.183.08:10:28.95#ibcon#about to write, iclass 5, count 0 2006.183.08:10:28.95#ibcon#wrote, iclass 5, count 0 2006.183.08:10:28.95#ibcon#about to read 3, iclass 5, count 0 2006.183.08:10:28.99#ibcon#read 3, iclass 5, count 0 2006.183.08:10:28.99#ibcon#about to read 4, iclass 5, count 0 2006.183.08:10:28.99#ibcon#read 4, iclass 5, count 0 2006.183.08:10:28.99#ibcon#about to read 5, iclass 5, count 0 2006.183.08:10:28.99#ibcon#read 5, iclass 5, count 0 2006.183.08:10:28.99#ibcon#about to read 6, iclass 5, count 0 2006.183.08:10:28.99#ibcon#read 6, iclass 5, count 0 2006.183.08:10:28.99#ibcon#end of sib2, iclass 5, count 0 2006.183.08:10:28.99#ibcon#*after write, iclass 5, count 0 2006.183.08:10:28.99#ibcon#*before return 0, iclass 5, count 0 2006.183.08:10:28.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:28.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:28.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:10:28.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:10:28.99$vc4f8/va=4,7 2006.183.08:10:28.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.08:10:28.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.08:10:29.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:29.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:29.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:29.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:29.05#ibcon#enter wrdev, iclass 7, count 2 2006.183.08:10:29.05#ibcon#first serial, iclass 7, count 2 2006.183.08:10:29.05#ibcon#enter sib2, iclass 7, count 2 2006.183.08:10:29.05#ibcon#flushed, iclass 7, count 2 2006.183.08:10:29.05#ibcon#about to write, iclass 7, count 2 2006.183.08:10:29.05#ibcon#wrote, iclass 7, count 2 2006.183.08:10:29.05#ibcon#about to read 3, iclass 7, count 2 2006.183.08:10:29.06#ibcon#read 3, iclass 7, count 2 2006.183.08:10:29.06#ibcon#about to read 4, iclass 7, count 2 2006.183.08:10:29.06#ibcon#read 4, iclass 7, count 2 2006.183.08:10:29.06#ibcon#about to read 5, iclass 7, count 2 2006.183.08:10:29.06#ibcon#read 5, iclass 7, count 2 2006.183.08:10:29.06#ibcon#about to read 6, iclass 7, count 2 2006.183.08:10:29.06#ibcon#read 6, iclass 7, count 2 2006.183.08:10:29.06#ibcon#end of sib2, iclass 7, count 2 2006.183.08:10:29.06#ibcon#*mode == 0, iclass 7, count 2 2006.183.08:10:29.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.08:10:29.06#ibcon#[25=AT04-07\r\n] 2006.183.08:10:29.06#ibcon#*before write, iclass 7, count 2 2006.183.08:10:29.06#ibcon#enter sib2, iclass 7, count 2 2006.183.08:10:29.06#ibcon#flushed, iclass 7, count 2 2006.183.08:10:29.06#ibcon#about to write, iclass 7, count 2 2006.183.08:10:29.06#ibcon#wrote, iclass 7, count 2 2006.183.08:10:29.06#ibcon#about to read 3, iclass 7, count 2 2006.183.08:10:29.09#ibcon#read 3, iclass 7, count 2 2006.183.08:10:29.09#ibcon#about to read 4, iclass 7, count 2 2006.183.08:10:29.09#ibcon#read 4, iclass 7, count 2 2006.183.08:10:29.09#ibcon#about to read 5, iclass 7, count 2 2006.183.08:10:29.09#ibcon#read 5, iclass 7, count 2 2006.183.08:10:29.09#ibcon#about to read 6, iclass 7, count 2 2006.183.08:10:29.09#ibcon#read 6, iclass 7, count 2 2006.183.08:10:29.09#ibcon#end of sib2, iclass 7, count 2 2006.183.08:10:29.09#ibcon#*after write, iclass 7, count 2 2006.183.08:10:29.09#ibcon#*before return 0, iclass 7, count 2 2006.183.08:10:29.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:29.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:29.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.08:10:29.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:29.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:29.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:29.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:29.21#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:10:29.21#ibcon#first serial, iclass 7, count 0 2006.183.08:10:29.21#ibcon#enter sib2, iclass 7, count 0 2006.183.08:10:29.21#ibcon#flushed, iclass 7, count 0 2006.183.08:10:29.21#ibcon#about to write, iclass 7, count 0 2006.183.08:10:29.21#ibcon#wrote, iclass 7, count 0 2006.183.08:10:29.21#ibcon#about to read 3, iclass 7, count 0 2006.183.08:10:29.23#ibcon#read 3, iclass 7, count 0 2006.183.08:10:29.23#ibcon#about to read 4, iclass 7, count 0 2006.183.08:10:29.23#ibcon#read 4, iclass 7, count 0 2006.183.08:10:29.23#ibcon#about to read 5, iclass 7, count 0 2006.183.08:10:29.23#ibcon#read 5, iclass 7, count 0 2006.183.08:10:29.23#ibcon#about to read 6, iclass 7, count 0 2006.183.08:10:29.23#ibcon#read 6, iclass 7, count 0 2006.183.08:10:29.23#ibcon#end of sib2, iclass 7, count 0 2006.183.08:10:29.23#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:10:29.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:10:29.23#ibcon#[25=USB\r\n] 2006.183.08:10:29.23#ibcon#*before write, iclass 7, count 0 2006.183.08:10:29.23#ibcon#enter sib2, iclass 7, count 0 2006.183.08:10:29.23#ibcon#flushed, iclass 7, count 0 2006.183.08:10:29.23#ibcon#about to write, iclass 7, count 0 2006.183.08:10:29.23#ibcon#wrote, iclass 7, count 0 2006.183.08:10:29.23#ibcon#about to read 3, iclass 7, count 0 2006.183.08:10:29.26#ibcon#read 3, iclass 7, count 0 2006.183.08:10:29.26#ibcon#about to read 4, iclass 7, count 0 2006.183.08:10:29.26#ibcon#read 4, iclass 7, count 0 2006.183.08:10:29.26#ibcon#about to read 5, iclass 7, count 0 2006.183.08:10:29.26#ibcon#read 5, iclass 7, count 0 2006.183.08:10:29.26#ibcon#about to read 6, iclass 7, count 0 2006.183.08:10:29.26#ibcon#read 6, iclass 7, count 0 2006.183.08:10:29.26#ibcon#end of sib2, iclass 7, count 0 2006.183.08:10:29.26#ibcon#*after write, iclass 7, count 0 2006.183.08:10:29.26#ibcon#*before return 0, iclass 7, count 0 2006.183.08:10:29.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:29.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:29.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:10:29.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:10:29.26$vc4f8/valo=5,652.99 2006.183.08:10:29.27#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:10:29.27#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:10:29.27#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:29.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:29.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:29.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:29.27#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:10:29.27#ibcon#first serial, iclass 11, count 0 2006.183.08:10:29.27#ibcon#enter sib2, iclass 11, count 0 2006.183.08:10:29.27#ibcon#flushed, iclass 11, count 0 2006.183.08:10:29.27#ibcon#about to write, iclass 11, count 0 2006.183.08:10:29.27#ibcon#wrote, iclass 11, count 0 2006.183.08:10:29.27#ibcon#about to read 3, iclass 11, count 0 2006.183.08:10:29.28#ibcon#read 3, iclass 11, count 0 2006.183.08:10:29.28#ibcon#about to read 4, iclass 11, count 0 2006.183.08:10:29.28#ibcon#read 4, iclass 11, count 0 2006.183.08:10:29.28#ibcon#about to read 5, iclass 11, count 0 2006.183.08:10:29.28#ibcon#read 5, iclass 11, count 0 2006.183.08:10:29.28#ibcon#about to read 6, iclass 11, count 0 2006.183.08:10:29.28#ibcon#read 6, iclass 11, count 0 2006.183.08:10:29.28#ibcon#end of sib2, iclass 11, count 0 2006.183.08:10:29.28#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:10:29.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:10:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:10:29.28#ibcon#*before write, iclass 11, count 0 2006.183.08:10:29.28#ibcon#enter sib2, iclass 11, count 0 2006.183.08:10:29.28#ibcon#flushed, iclass 11, count 0 2006.183.08:10:29.28#ibcon#about to write, iclass 11, count 0 2006.183.08:10:29.28#ibcon#wrote, iclass 11, count 0 2006.183.08:10:29.28#ibcon#about to read 3, iclass 11, count 0 2006.183.08:10:29.32#ibcon#read 3, iclass 11, count 0 2006.183.08:10:29.32#ibcon#about to read 4, iclass 11, count 0 2006.183.08:10:29.32#ibcon#read 4, iclass 11, count 0 2006.183.08:10:29.32#ibcon#about to read 5, iclass 11, count 0 2006.183.08:10:29.32#ibcon#read 5, iclass 11, count 0 2006.183.08:10:29.32#ibcon#about to read 6, iclass 11, count 0 2006.183.08:10:29.32#ibcon#read 6, iclass 11, count 0 2006.183.08:10:29.32#ibcon#end of sib2, iclass 11, count 0 2006.183.08:10:29.32#ibcon#*after write, iclass 11, count 0 2006.183.08:10:29.32#ibcon#*before return 0, iclass 11, count 0 2006.183.08:10:29.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:29.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:29.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:10:29.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:10:29.32$vc4f8/va=5,7 2006.183.08:10:29.33#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.08:10:29.33#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.08:10:29.33#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:29.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:29.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:29.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:29.37#ibcon#enter wrdev, iclass 13, count 2 2006.183.08:10:29.37#ibcon#first serial, iclass 13, count 2 2006.183.08:10:29.37#ibcon#enter sib2, iclass 13, count 2 2006.183.08:10:29.37#ibcon#flushed, iclass 13, count 2 2006.183.08:10:29.37#ibcon#about to write, iclass 13, count 2 2006.183.08:10:29.37#ibcon#wrote, iclass 13, count 2 2006.183.08:10:29.37#ibcon#about to read 3, iclass 13, count 2 2006.183.08:10:29.39#ibcon#read 3, iclass 13, count 2 2006.183.08:10:29.39#ibcon#about to read 4, iclass 13, count 2 2006.183.08:10:29.39#ibcon#read 4, iclass 13, count 2 2006.183.08:10:29.39#ibcon#about to read 5, iclass 13, count 2 2006.183.08:10:29.39#ibcon#read 5, iclass 13, count 2 2006.183.08:10:29.39#ibcon#about to read 6, iclass 13, count 2 2006.183.08:10:29.39#ibcon#read 6, iclass 13, count 2 2006.183.08:10:29.39#ibcon#end of sib2, iclass 13, count 2 2006.183.08:10:29.39#ibcon#*mode == 0, iclass 13, count 2 2006.183.08:10:29.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.08:10:29.39#ibcon#[25=AT05-07\r\n] 2006.183.08:10:29.39#ibcon#*before write, iclass 13, count 2 2006.183.08:10:29.39#ibcon#enter sib2, iclass 13, count 2 2006.183.08:10:29.39#ibcon#flushed, iclass 13, count 2 2006.183.08:10:29.39#ibcon#about to write, iclass 13, count 2 2006.183.08:10:29.39#ibcon#wrote, iclass 13, count 2 2006.183.08:10:29.39#ibcon#about to read 3, iclass 13, count 2 2006.183.08:10:29.42#ibcon#read 3, iclass 13, count 2 2006.183.08:10:29.42#ibcon#about to read 4, iclass 13, count 2 2006.183.08:10:29.42#ibcon#read 4, iclass 13, count 2 2006.183.08:10:29.42#ibcon#about to read 5, iclass 13, count 2 2006.183.08:10:29.42#ibcon#read 5, iclass 13, count 2 2006.183.08:10:29.42#ibcon#about to read 6, iclass 13, count 2 2006.183.08:10:29.42#ibcon#read 6, iclass 13, count 2 2006.183.08:10:29.42#ibcon#end of sib2, iclass 13, count 2 2006.183.08:10:29.42#ibcon#*after write, iclass 13, count 2 2006.183.08:10:29.42#ibcon#*before return 0, iclass 13, count 2 2006.183.08:10:29.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:29.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:29.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.08:10:29.42#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:29.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:29.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:29.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:29.54#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:10:29.54#ibcon#first serial, iclass 13, count 0 2006.183.08:10:29.54#ibcon#enter sib2, iclass 13, count 0 2006.183.08:10:29.54#ibcon#flushed, iclass 13, count 0 2006.183.08:10:29.54#ibcon#about to write, iclass 13, count 0 2006.183.08:10:29.54#ibcon#wrote, iclass 13, count 0 2006.183.08:10:29.54#ibcon#about to read 3, iclass 13, count 0 2006.183.08:10:29.56#ibcon#read 3, iclass 13, count 0 2006.183.08:10:29.56#ibcon#about to read 4, iclass 13, count 0 2006.183.08:10:29.56#ibcon#read 4, iclass 13, count 0 2006.183.08:10:29.56#ibcon#about to read 5, iclass 13, count 0 2006.183.08:10:29.56#ibcon#read 5, iclass 13, count 0 2006.183.08:10:29.56#ibcon#about to read 6, iclass 13, count 0 2006.183.08:10:29.56#ibcon#read 6, iclass 13, count 0 2006.183.08:10:29.56#ibcon#end of sib2, iclass 13, count 0 2006.183.08:10:29.56#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:10:29.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:10:29.56#ibcon#[25=USB\r\n] 2006.183.08:10:29.56#ibcon#*before write, iclass 13, count 0 2006.183.08:10:29.56#ibcon#enter sib2, iclass 13, count 0 2006.183.08:10:29.56#ibcon#flushed, iclass 13, count 0 2006.183.08:10:29.56#ibcon#about to write, iclass 13, count 0 2006.183.08:10:29.56#ibcon#wrote, iclass 13, count 0 2006.183.08:10:29.56#ibcon#about to read 3, iclass 13, count 0 2006.183.08:10:29.59#ibcon#read 3, iclass 13, count 0 2006.183.08:10:29.59#ibcon#about to read 4, iclass 13, count 0 2006.183.08:10:29.59#ibcon#read 4, iclass 13, count 0 2006.183.08:10:29.59#ibcon#about to read 5, iclass 13, count 0 2006.183.08:10:29.59#ibcon#read 5, iclass 13, count 0 2006.183.08:10:29.59#ibcon#about to read 6, iclass 13, count 0 2006.183.08:10:29.59#ibcon#read 6, iclass 13, count 0 2006.183.08:10:29.59#ibcon#end of sib2, iclass 13, count 0 2006.183.08:10:29.59#ibcon#*after write, iclass 13, count 0 2006.183.08:10:29.59#ibcon#*before return 0, iclass 13, count 0 2006.183.08:10:29.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:29.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:29.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:10:29.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:10:29.59$vc4f8/valo=6,772.99 2006.183.08:10:29.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.08:10:29.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.08:10:29.59#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:29.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:29.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:29.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:29.60#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:10:29.60#ibcon#first serial, iclass 15, count 0 2006.183.08:10:29.60#ibcon#enter sib2, iclass 15, count 0 2006.183.08:10:29.60#ibcon#flushed, iclass 15, count 0 2006.183.08:10:29.60#ibcon#about to write, iclass 15, count 0 2006.183.08:10:29.60#ibcon#wrote, iclass 15, count 0 2006.183.08:10:29.60#ibcon#about to read 3, iclass 15, count 0 2006.183.08:10:29.61#ibcon#read 3, iclass 15, count 0 2006.183.08:10:29.61#ibcon#about to read 4, iclass 15, count 0 2006.183.08:10:29.61#ibcon#read 4, iclass 15, count 0 2006.183.08:10:29.61#ibcon#about to read 5, iclass 15, count 0 2006.183.08:10:29.61#ibcon#read 5, iclass 15, count 0 2006.183.08:10:29.61#ibcon#about to read 6, iclass 15, count 0 2006.183.08:10:29.61#ibcon#read 6, iclass 15, count 0 2006.183.08:10:29.61#ibcon#end of sib2, iclass 15, count 0 2006.183.08:10:29.61#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:10:29.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:10:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:10:29.61#ibcon#*before write, iclass 15, count 0 2006.183.08:10:29.61#ibcon#enter sib2, iclass 15, count 0 2006.183.08:10:29.61#ibcon#flushed, iclass 15, count 0 2006.183.08:10:29.61#ibcon#about to write, iclass 15, count 0 2006.183.08:10:29.61#ibcon#wrote, iclass 15, count 0 2006.183.08:10:29.61#ibcon#about to read 3, iclass 15, count 0 2006.183.08:10:29.65#ibcon#read 3, iclass 15, count 0 2006.183.08:10:29.65#ibcon#about to read 4, iclass 15, count 0 2006.183.08:10:29.65#ibcon#read 4, iclass 15, count 0 2006.183.08:10:29.65#ibcon#about to read 5, iclass 15, count 0 2006.183.08:10:29.65#ibcon#read 5, iclass 15, count 0 2006.183.08:10:29.65#ibcon#about to read 6, iclass 15, count 0 2006.183.08:10:29.65#ibcon#read 6, iclass 15, count 0 2006.183.08:10:29.65#ibcon#end of sib2, iclass 15, count 0 2006.183.08:10:29.65#ibcon#*after write, iclass 15, count 0 2006.183.08:10:29.65#ibcon#*before return 0, iclass 15, count 0 2006.183.08:10:29.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:29.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:29.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:10:29.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:10:29.65$vc4f8/va=6,6 2006.183.08:10:29.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.08:10:29.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.08:10:29.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:29.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:10:29.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:10:29.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:10:29.71#ibcon#enter wrdev, iclass 17, count 2 2006.183.08:10:29.71#ibcon#first serial, iclass 17, count 2 2006.183.08:10:29.71#ibcon#enter sib2, iclass 17, count 2 2006.183.08:10:29.71#ibcon#flushed, iclass 17, count 2 2006.183.08:10:29.71#ibcon#about to write, iclass 17, count 2 2006.183.08:10:29.71#ibcon#wrote, iclass 17, count 2 2006.183.08:10:29.71#ibcon#about to read 3, iclass 17, count 2 2006.183.08:10:29.72#ibcon#read 3, iclass 17, count 2 2006.183.08:10:29.72#ibcon#about to read 4, iclass 17, count 2 2006.183.08:10:29.72#ibcon#read 4, iclass 17, count 2 2006.183.08:10:29.72#ibcon#about to read 5, iclass 17, count 2 2006.183.08:10:29.72#ibcon#read 5, iclass 17, count 2 2006.183.08:10:29.72#ibcon#about to read 6, iclass 17, count 2 2006.183.08:10:29.72#ibcon#read 6, iclass 17, count 2 2006.183.08:10:29.72#ibcon#end of sib2, iclass 17, count 2 2006.183.08:10:29.72#ibcon#*mode == 0, iclass 17, count 2 2006.183.08:10:29.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.08:10:29.72#ibcon#[25=AT06-06\r\n] 2006.183.08:10:29.72#ibcon#*before write, iclass 17, count 2 2006.183.08:10:29.72#ibcon#enter sib2, iclass 17, count 2 2006.183.08:10:29.72#ibcon#flushed, iclass 17, count 2 2006.183.08:10:29.72#ibcon#about to write, iclass 17, count 2 2006.183.08:10:29.72#ibcon#wrote, iclass 17, count 2 2006.183.08:10:29.72#ibcon#about to read 3, iclass 17, count 2 2006.183.08:10:29.75#ibcon#read 3, iclass 17, count 2 2006.183.08:10:29.75#ibcon#about to read 4, iclass 17, count 2 2006.183.08:10:29.75#ibcon#read 4, iclass 17, count 2 2006.183.08:10:29.75#ibcon#about to read 5, iclass 17, count 2 2006.183.08:10:29.75#ibcon#read 5, iclass 17, count 2 2006.183.08:10:29.75#ibcon#about to read 6, iclass 17, count 2 2006.183.08:10:29.75#ibcon#read 6, iclass 17, count 2 2006.183.08:10:29.75#ibcon#end of sib2, iclass 17, count 2 2006.183.08:10:29.75#ibcon#*after write, iclass 17, count 2 2006.183.08:10:29.75#ibcon#*before return 0, iclass 17, count 2 2006.183.08:10:29.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:10:29.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:10:29.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.08:10:29.75#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:29.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:10:29.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:10:29.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:10:29.87#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:10:29.87#ibcon#first serial, iclass 17, count 0 2006.183.08:10:29.87#ibcon#enter sib2, iclass 17, count 0 2006.183.08:10:29.87#ibcon#flushed, iclass 17, count 0 2006.183.08:10:29.87#ibcon#about to write, iclass 17, count 0 2006.183.08:10:29.87#ibcon#wrote, iclass 17, count 0 2006.183.08:10:29.87#ibcon#about to read 3, iclass 17, count 0 2006.183.08:10:29.89#ibcon#read 3, iclass 17, count 0 2006.183.08:10:29.89#ibcon#about to read 4, iclass 17, count 0 2006.183.08:10:29.89#ibcon#read 4, iclass 17, count 0 2006.183.08:10:29.89#ibcon#about to read 5, iclass 17, count 0 2006.183.08:10:29.89#ibcon#read 5, iclass 17, count 0 2006.183.08:10:29.89#ibcon#about to read 6, iclass 17, count 0 2006.183.08:10:29.89#ibcon#read 6, iclass 17, count 0 2006.183.08:10:29.89#ibcon#end of sib2, iclass 17, count 0 2006.183.08:10:29.89#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:10:29.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:10:29.89#ibcon#[25=USB\r\n] 2006.183.08:10:29.89#ibcon#*before write, iclass 17, count 0 2006.183.08:10:29.89#ibcon#enter sib2, iclass 17, count 0 2006.183.08:10:29.89#ibcon#flushed, iclass 17, count 0 2006.183.08:10:29.89#ibcon#about to write, iclass 17, count 0 2006.183.08:10:29.89#ibcon#wrote, iclass 17, count 0 2006.183.08:10:29.89#ibcon#about to read 3, iclass 17, count 0 2006.183.08:10:29.92#ibcon#read 3, iclass 17, count 0 2006.183.08:10:29.92#ibcon#about to read 4, iclass 17, count 0 2006.183.08:10:29.92#ibcon#read 4, iclass 17, count 0 2006.183.08:10:29.92#ibcon#about to read 5, iclass 17, count 0 2006.183.08:10:29.92#ibcon#read 5, iclass 17, count 0 2006.183.08:10:29.92#ibcon#about to read 6, iclass 17, count 0 2006.183.08:10:29.92#ibcon#read 6, iclass 17, count 0 2006.183.08:10:29.92#ibcon#end of sib2, iclass 17, count 0 2006.183.08:10:29.92#ibcon#*after write, iclass 17, count 0 2006.183.08:10:29.92#ibcon#*before return 0, iclass 17, count 0 2006.183.08:10:29.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:10:29.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:10:29.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:10:29.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:10:29.92$vc4f8/valo=7,832.99 2006.183.08:10:29.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.08:10:29.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.08:10:29.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:29.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:10:29.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:10:29.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:10:29.93#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:10:29.93#ibcon#first serial, iclass 19, count 0 2006.183.08:10:29.93#ibcon#enter sib2, iclass 19, count 0 2006.183.08:10:29.93#ibcon#flushed, iclass 19, count 0 2006.183.08:10:29.93#ibcon#about to write, iclass 19, count 0 2006.183.08:10:29.93#ibcon#wrote, iclass 19, count 0 2006.183.08:10:29.93#ibcon#about to read 3, iclass 19, count 0 2006.183.08:10:29.94#ibcon#read 3, iclass 19, count 0 2006.183.08:10:29.94#ibcon#about to read 4, iclass 19, count 0 2006.183.08:10:29.94#ibcon#read 4, iclass 19, count 0 2006.183.08:10:29.94#ibcon#about to read 5, iclass 19, count 0 2006.183.08:10:29.94#ibcon#read 5, iclass 19, count 0 2006.183.08:10:29.94#ibcon#about to read 6, iclass 19, count 0 2006.183.08:10:29.94#ibcon#read 6, iclass 19, count 0 2006.183.08:10:29.94#ibcon#end of sib2, iclass 19, count 0 2006.183.08:10:29.94#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:10:29.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:10:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:10:29.94#ibcon#*before write, iclass 19, count 0 2006.183.08:10:29.94#ibcon#enter sib2, iclass 19, count 0 2006.183.08:10:29.94#ibcon#flushed, iclass 19, count 0 2006.183.08:10:29.94#ibcon#about to write, iclass 19, count 0 2006.183.08:10:29.94#ibcon#wrote, iclass 19, count 0 2006.183.08:10:29.94#ibcon#about to read 3, iclass 19, count 0 2006.183.08:10:29.98#ibcon#read 3, iclass 19, count 0 2006.183.08:10:29.98#ibcon#about to read 4, iclass 19, count 0 2006.183.08:10:29.98#ibcon#read 4, iclass 19, count 0 2006.183.08:10:29.98#ibcon#about to read 5, iclass 19, count 0 2006.183.08:10:29.98#ibcon#read 5, iclass 19, count 0 2006.183.08:10:29.98#ibcon#about to read 6, iclass 19, count 0 2006.183.08:10:29.98#ibcon#read 6, iclass 19, count 0 2006.183.08:10:29.98#ibcon#end of sib2, iclass 19, count 0 2006.183.08:10:29.98#ibcon#*after write, iclass 19, count 0 2006.183.08:10:29.98#ibcon#*before return 0, iclass 19, count 0 2006.183.08:10:29.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:10:29.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:10:29.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:10:29.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:10:29.98$vc4f8/va=7,6 2006.183.08:10:29.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.08:10:29.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.08:10:29.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:29.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:10:30.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:10:30.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:10:30.03#ibcon#enter wrdev, iclass 21, count 2 2006.183.08:10:30.03#ibcon#first serial, iclass 21, count 2 2006.183.08:10:30.03#ibcon#enter sib2, iclass 21, count 2 2006.183.08:10:30.03#ibcon#flushed, iclass 21, count 2 2006.183.08:10:30.03#ibcon#about to write, iclass 21, count 2 2006.183.08:10:30.03#ibcon#wrote, iclass 21, count 2 2006.183.08:10:30.03#ibcon#about to read 3, iclass 21, count 2 2006.183.08:10:30.05#ibcon#read 3, iclass 21, count 2 2006.183.08:10:30.05#ibcon#about to read 4, iclass 21, count 2 2006.183.08:10:30.05#ibcon#read 4, iclass 21, count 2 2006.183.08:10:30.05#ibcon#about to read 5, iclass 21, count 2 2006.183.08:10:30.05#ibcon#read 5, iclass 21, count 2 2006.183.08:10:30.05#ibcon#about to read 6, iclass 21, count 2 2006.183.08:10:30.05#ibcon#read 6, iclass 21, count 2 2006.183.08:10:30.05#ibcon#end of sib2, iclass 21, count 2 2006.183.08:10:30.05#ibcon#*mode == 0, iclass 21, count 2 2006.183.08:10:30.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.08:10:30.05#ibcon#[25=AT07-06\r\n] 2006.183.08:10:30.05#ibcon#*before write, iclass 21, count 2 2006.183.08:10:30.05#ibcon#enter sib2, iclass 21, count 2 2006.183.08:10:30.05#ibcon#flushed, iclass 21, count 2 2006.183.08:10:30.05#ibcon#about to write, iclass 21, count 2 2006.183.08:10:30.05#ibcon#wrote, iclass 21, count 2 2006.183.08:10:30.05#ibcon#about to read 3, iclass 21, count 2 2006.183.08:10:30.08#ibcon#read 3, iclass 21, count 2 2006.183.08:10:30.08#ibcon#about to read 4, iclass 21, count 2 2006.183.08:10:30.08#ibcon#read 4, iclass 21, count 2 2006.183.08:10:30.08#ibcon#about to read 5, iclass 21, count 2 2006.183.08:10:30.08#ibcon#read 5, iclass 21, count 2 2006.183.08:10:30.08#ibcon#about to read 6, iclass 21, count 2 2006.183.08:10:30.08#ibcon#read 6, iclass 21, count 2 2006.183.08:10:30.08#ibcon#end of sib2, iclass 21, count 2 2006.183.08:10:30.08#ibcon#*after write, iclass 21, count 2 2006.183.08:10:30.08#ibcon#*before return 0, iclass 21, count 2 2006.183.08:10:30.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:10:30.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:10:30.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.08:10:30.08#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:30.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:10:30.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:10:30.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:10:30.20#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:10:30.20#ibcon#first serial, iclass 21, count 0 2006.183.08:10:30.20#ibcon#enter sib2, iclass 21, count 0 2006.183.08:10:30.20#ibcon#flushed, iclass 21, count 0 2006.183.08:10:30.20#ibcon#about to write, iclass 21, count 0 2006.183.08:10:30.20#ibcon#wrote, iclass 21, count 0 2006.183.08:10:30.20#ibcon#about to read 3, iclass 21, count 0 2006.183.08:10:30.22#ibcon#read 3, iclass 21, count 0 2006.183.08:10:30.22#ibcon#about to read 4, iclass 21, count 0 2006.183.08:10:30.22#ibcon#read 4, iclass 21, count 0 2006.183.08:10:30.22#ibcon#about to read 5, iclass 21, count 0 2006.183.08:10:30.22#ibcon#read 5, iclass 21, count 0 2006.183.08:10:30.22#ibcon#about to read 6, iclass 21, count 0 2006.183.08:10:30.22#ibcon#read 6, iclass 21, count 0 2006.183.08:10:30.22#ibcon#end of sib2, iclass 21, count 0 2006.183.08:10:30.22#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:10:30.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:10:30.22#ibcon#[25=USB\r\n] 2006.183.08:10:30.22#ibcon#*before write, iclass 21, count 0 2006.183.08:10:30.22#ibcon#enter sib2, iclass 21, count 0 2006.183.08:10:30.22#ibcon#flushed, iclass 21, count 0 2006.183.08:10:30.22#ibcon#about to write, iclass 21, count 0 2006.183.08:10:30.22#ibcon#wrote, iclass 21, count 0 2006.183.08:10:30.22#ibcon#about to read 3, iclass 21, count 0 2006.183.08:10:30.25#ibcon#read 3, iclass 21, count 0 2006.183.08:10:30.25#ibcon#about to read 4, iclass 21, count 0 2006.183.08:10:30.25#ibcon#read 4, iclass 21, count 0 2006.183.08:10:30.25#ibcon#about to read 5, iclass 21, count 0 2006.183.08:10:30.25#ibcon#read 5, iclass 21, count 0 2006.183.08:10:30.25#ibcon#about to read 6, iclass 21, count 0 2006.183.08:10:30.25#ibcon#read 6, iclass 21, count 0 2006.183.08:10:30.25#ibcon#end of sib2, iclass 21, count 0 2006.183.08:10:30.25#ibcon#*after write, iclass 21, count 0 2006.183.08:10:30.25#ibcon#*before return 0, iclass 21, count 0 2006.183.08:10:30.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:10:30.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:10:30.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:10:30.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:10:30.25$vc4f8/valo=8,852.99 2006.183.08:10:30.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:10:30.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:10:30.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:30.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:10:30.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:10:30.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:10:30.26#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:10:30.26#ibcon#first serial, iclass 23, count 0 2006.183.08:10:30.26#ibcon#enter sib2, iclass 23, count 0 2006.183.08:10:30.26#ibcon#flushed, iclass 23, count 0 2006.183.08:10:30.26#ibcon#about to write, iclass 23, count 0 2006.183.08:10:30.26#ibcon#wrote, iclass 23, count 0 2006.183.08:10:30.26#ibcon#about to read 3, iclass 23, count 0 2006.183.08:10:30.27#ibcon#read 3, iclass 23, count 0 2006.183.08:10:30.27#ibcon#about to read 4, iclass 23, count 0 2006.183.08:10:30.27#ibcon#read 4, iclass 23, count 0 2006.183.08:10:30.27#ibcon#about to read 5, iclass 23, count 0 2006.183.08:10:30.27#ibcon#read 5, iclass 23, count 0 2006.183.08:10:30.27#ibcon#about to read 6, iclass 23, count 0 2006.183.08:10:30.27#ibcon#read 6, iclass 23, count 0 2006.183.08:10:30.27#ibcon#end of sib2, iclass 23, count 0 2006.183.08:10:30.27#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:10:30.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:10:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:10:30.27#ibcon#*before write, iclass 23, count 0 2006.183.08:10:30.27#ibcon#enter sib2, iclass 23, count 0 2006.183.08:10:30.27#ibcon#flushed, iclass 23, count 0 2006.183.08:10:30.27#ibcon#about to write, iclass 23, count 0 2006.183.08:10:30.27#ibcon#wrote, iclass 23, count 0 2006.183.08:10:30.27#ibcon#about to read 3, iclass 23, count 0 2006.183.08:10:30.31#ibcon#read 3, iclass 23, count 0 2006.183.08:10:30.31#ibcon#about to read 4, iclass 23, count 0 2006.183.08:10:30.31#ibcon#read 4, iclass 23, count 0 2006.183.08:10:30.31#ibcon#about to read 5, iclass 23, count 0 2006.183.08:10:30.31#ibcon#read 5, iclass 23, count 0 2006.183.08:10:30.31#ibcon#about to read 6, iclass 23, count 0 2006.183.08:10:30.31#ibcon#read 6, iclass 23, count 0 2006.183.08:10:30.31#ibcon#end of sib2, iclass 23, count 0 2006.183.08:10:30.31#ibcon#*after write, iclass 23, count 0 2006.183.08:10:30.31#ibcon#*before return 0, iclass 23, count 0 2006.183.08:10:30.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:10:30.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:10:30.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:10:30.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:10:30.31$vc4f8/va=8,7 2006.183.08:10:30.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.08:10:30.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.08:10:30.31#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:30.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:10:30.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:10:30.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:10:30.37#ibcon#enter wrdev, iclass 25, count 2 2006.183.08:10:30.37#ibcon#first serial, iclass 25, count 2 2006.183.08:10:30.37#ibcon#enter sib2, iclass 25, count 2 2006.183.08:10:30.37#ibcon#flushed, iclass 25, count 2 2006.183.08:10:30.37#ibcon#about to write, iclass 25, count 2 2006.183.08:10:30.37#ibcon#wrote, iclass 25, count 2 2006.183.08:10:30.37#ibcon#about to read 3, iclass 25, count 2 2006.183.08:10:30.39#ibcon#read 3, iclass 25, count 2 2006.183.08:10:30.39#ibcon#about to read 4, iclass 25, count 2 2006.183.08:10:30.39#ibcon#read 4, iclass 25, count 2 2006.183.08:10:30.39#ibcon#about to read 5, iclass 25, count 2 2006.183.08:10:30.39#ibcon#read 5, iclass 25, count 2 2006.183.08:10:30.39#ibcon#about to read 6, iclass 25, count 2 2006.183.08:10:30.39#ibcon#read 6, iclass 25, count 2 2006.183.08:10:30.39#ibcon#end of sib2, iclass 25, count 2 2006.183.08:10:30.39#ibcon#*mode == 0, iclass 25, count 2 2006.183.08:10:30.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.08:10:30.39#ibcon#[25=AT08-07\r\n] 2006.183.08:10:30.39#ibcon#*before write, iclass 25, count 2 2006.183.08:10:30.39#ibcon#enter sib2, iclass 25, count 2 2006.183.08:10:30.39#ibcon#flushed, iclass 25, count 2 2006.183.08:10:30.39#ibcon#about to write, iclass 25, count 2 2006.183.08:10:30.39#ibcon#wrote, iclass 25, count 2 2006.183.08:10:30.39#ibcon#about to read 3, iclass 25, count 2 2006.183.08:10:30.42#ibcon#read 3, iclass 25, count 2 2006.183.08:10:30.42#ibcon#about to read 4, iclass 25, count 2 2006.183.08:10:30.42#ibcon#read 4, iclass 25, count 2 2006.183.08:10:30.42#ibcon#about to read 5, iclass 25, count 2 2006.183.08:10:30.42#ibcon#read 5, iclass 25, count 2 2006.183.08:10:30.42#ibcon#about to read 6, iclass 25, count 2 2006.183.08:10:30.42#ibcon#read 6, iclass 25, count 2 2006.183.08:10:30.42#ibcon#end of sib2, iclass 25, count 2 2006.183.08:10:30.42#ibcon#*after write, iclass 25, count 2 2006.183.08:10:30.42#ibcon#*before return 0, iclass 25, count 2 2006.183.08:10:30.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:10:30.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:10:30.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.08:10:30.42#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:30.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:10:30.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:10:30.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:10:30.54#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:10:30.54#ibcon#first serial, iclass 25, count 0 2006.183.08:10:30.54#ibcon#enter sib2, iclass 25, count 0 2006.183.08:10:30.54#ibcon#flushed, iclass 25, count 0 2006.183.08:10:30.54#ibcon#about to write, iclass 25, count 0 2006.183.08:10:30.54#ibcon#wrote, iclass 25, count 0 2006.183.08:10:30.54#ibcon#about to read 3, iclass 25, count 0 2006.183.08:10:30.56#ibcon#read 3, iclass 25, count 0 2006.183.08:10:30.56#ibcon#about to read 4, iclass 25, count 0 2006.183.08:10:30.56#ibcon#read 4, iclass 25, count 0 2006.183.08:10:30.56#ibcon#about to read 5, iclass 25, count 0 2006.183.08:10:30.56#ibcon#read 5, iclass 25, count 0 2006.183.08:10:30.56#ibcon#about to read 6, iclass 25, count 0 2006.183.08:10:30.56#ibcon#read 6, iclass 25, count 0 2006.183.08:10:30.56#ibcon#end of sib2, iclass 25, count 0 2006.183.08:10:30.56#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:10:30.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:10:30.56#ibcon#[25=USB\r\n] 2006.183.08:10:30.56#ibcon#*before write, iclass 25, count 0 2006.183.08:10:30.56#ibcon#enter sib2, iclass 25, count 0 2006.183.08:10:30.56#ibcon#flushed, iclass 25, count 0 2006.183.08:10:30.56#ibcon#about to write, iclass 25, count 0 2006.183.08:10:30.56#ibcon#wrote, iclass 25, count 0 2006.183.08:10:30.56#ibcon#about to read 3, iclass 25, count 0 2006.183.08:10:30.59#ibcon#read 3, iclass 25, count 0 2006.183.08:10:30.59#ibcon#about to read 4, iclass 25, count 0 2006.183.08:10:30.59#ibcon#read 4, iclass 25, count 0 2006.183.08:10:30.59#ibcon#about to read 5, iclass 25, count 0 2006.183.08:10:30.59#ibcon#read 5, iclass 25, count 0 2006.183.08:10:30.59#ibcon#about to read 6, iclass 25, count 0 2006.183.08:10:30.59#ibcon#read 6, iclass 25, count 0 2006.183.08:10:30.59#ibcon#end of sib2, iclass 25, count 0 2006.183.08:10:30.59#ibcon#*after write, iclass 25, count 0 2006.183.08:10:30.59#ibcon#*before return 0, iclass 25, count 0 2006.183.08:10:30.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:10:30.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:10:30.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:10:30.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:10:30.59$vc4f8/vblo=1,632.99 2006.183.08:10:30.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.08:10:30.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.08:10:30.59#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:30.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:10:30.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:10:30.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:10:30.60#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:10:30.60#ibcon#first serial, iclass 27, count 0 2006.183.08:10:30.60#ibcon#enter sib2, iclass 27, count 0 2006.183.08:10:30.60#ibcon#flushed, iclass 27, count 0 2006.183.08:10:30.60#ibcon#about to write, iclass 27, count 0 2006.183.08:10:30.60#ibcon#wrote, iclass 27, count 0 2006.183.08:10:30.60#ibcon#about to read 3, iclass 27, count 0 2006.183.08:10:30.61#ibcon#read 3, iclass 27, count 0 2006.183.08:10:30.61#ibcon#about to read 4, iclass 27, count 0 2006.183.08:10:30.61#ibcon#read 4, iclass 27, count 0 2006.183.08:10:30.61#ibcon#about to read 5, iclass 27, count 0 2006.183.08:10:30.61#ibcon#read 5, iclass 27, count 0 2006.183.08:10:30.61#ibcon#about to read 6, iclass 27, count 0 2006.183.08:10:30.61#ibcon#read 6, iclass 27, count 0 2006.183.08:10:30.61#ibcon#end of sib2, iclass 27, count 0 2006.183.08:10:30.61#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:10:30.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:10:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:10:30.61#ibcon#*before write, iclass 27, count 0 2006.183.08:10:30.61#ibcon#enter sib2, iclass 27, count 0 2006.183.08:10:30.61#ibcon#flushed, iclass 27, count 0 2006.183.08:10:30.61#ibcon#about to write, iclass 27, count 0 2006.183.08:10:30.61#ibcon#wrote, iclass 27, count 0 2006.183.08:10:30.61#ibcon#about to read 3, iclass 27, count 0 2006.183.08:10:30.65#ibcon#read 3, iclass 27, count 0 2006.183.08:10:30.65#ibcon#about to read 4, iclass 27, count 0 2006.183.08:10:30.65#ibcon#read 4, iclass 27, count 0 2006.183.08:10:30.65#ibcon#about to read 5, iclass 27, count 0 2006.183.08:10:30.65#ibcon#read 5, iclass 27, count 0 2006.183.08:10:30.65#ibcon#about to read 6, iclass 27, count 0 2006.183.08:10:30.65#ibcon#read 6, iclass 27, count 0 2006.183.08:10:30.65#ibcon#end of sib2, iclass 27, count 0 2006.183.08:10:30.65#ibcon#*after write, iclass 27, count 0 2006.183.08:10:30.65#ibcon#*before return 0, iclass 27, count 0 2006.183.08:10:30.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:10:30.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:10:30.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:10:30.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:10:30.65$vc4f8/vb=1,4 2006.183.08:10:30.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.08:10:30.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.08:10:30.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:30.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:10:30.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:10:30.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:10:30.66#ibcon#enter wrdev, iclass 29, count 2 2006.183.08:10:30.66#ibcon#first serial, iclass 29, count 2 2006.183.08:10:30.66#ibcon#enter sib2, iclass 29, count 2 2006.183.08:10:30.66#ibcon#flushed, iclass 29, count 2 2006.183.08:10:30.66#ibcon#about to write, iclass 29, count 2 2006.183.08:10:30.66#ibcon#wrote, iclass 29, count 2 2006.183.08:10:30.66#ibcon#about to read 3, iclass 29, count 2 2006.183.08:10:30.67#ibcon#read 3, iclass 29, count 2 2006.183.08:10:30.67#ibcon#about to read 4, iclass 29, count 2 2006.183.08:10:30.67#ibcon#read 4, iclass 29, count 2 2006.183.08:10:30.67#ibcon#about to read 5, iclass 29, count 2 2006.183.08:10:30.67#ibcon#read 5, iclass 29, count 2 2006.183.08:10:30.67#ibcon#about to read 6, iclass 29, count 2 2006.183.08:10:30.67#ibcon#read 6, iclass 29, count 2 2006.183.08:10:30.67#ibcon#end of sib2, iclass 29, count 2 2006.183.08:10:30.67#ibcon#*mode == 0, iclass 29, count 2 2006.183.08:10:30.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.08:10:30.67#ibcon#[27=AT01-04\r\n] 2006.183.08:10:30.67#ibcon#*before write, iclass 29, count 2 2006.183.08:10:30.67#ibcon#enter sib2, iclass 29, count 2 2006.183.08:10:30.67#ibcon#flushed, iclass 29, count 2 2006.183.08:10:30.67#ibcon#about to write, iclass 29, count 2 2006.183.08:10:30.67#ibcon#wrote, iclass 29, count 2 2006.183.08:10:30.67#ibcon#about to read 3, iclass 29, count 2 2006.183.08:10:30.70#ibcon#read 3, iclass 29, count 2 2006.183.08:10:30.70#ibcon#about to read 4, iclass 29, count 2 2006.183.08:10:30.70#ibcon#read 4, iclass 29, count 2 2006.183.08:10:30.70#ibcon#about to read 5, iclass 29, count 2 2006.183.08:10:30.70#ibcon#read 5, iclass 29, count 2 2006.183.08:10:30.70#ibcon#about to read 6, iclass 29, count 2 2006.183.08:10:30.70#ibcon#read 6, iclass 29, count 2 2006.183.08:10:30.70#ibcon#end of sib2, iclass 29, count 2 2006.183.08:10:30.70#ibcon#*after write, iclass 29, count 2 2006.183.08:10:30.70#ibcon#*before return 0, iclass 29, count 2 2006.183.08:10:30.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:10:30.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:10:30.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.08:10:30.70#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:30.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:10:30.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:10:30.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:10:30.82#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:10:30.82#ibcon#first serial, iclass 29, count 0 2006.183.08:10:30.82#ibcon#enter sib2, iclass 29, count 0 2006.183.08:10:30.82#ibcon#flushed, iclass 29, count 0 2006.183.08:10:30.82#ibcon#about to write, iclass 29, count 0 2006.183.08:10:30.82#ibcon#wrote, iclass 29, count 0 2006.183.08:10:30.82#ibcon#about to read 3, iclass 29, count 0 2006.183.08:10:30.84#ibcon#read 3, iclass 29, count 0 2006.183.08:10:30.84#ibcon#about to read 4, iclass 29, count 0 2006.183.08:10:30.84#ibcon#read 4, iclass 29, count 0 2006.183.08:10:30.84#ibcon#about to read 5, iclass 29, count 0 2006.183.08:10:30.84#ibcon#read 5, iclass 29, count 0 2006.183.08:10:30.84#ibcon#about to read 6, iclass 29, count 0 2006.183.08:10:30.84#ibcon#read 6, iclass 29, count 0 2006.183.08:10:30.84#ibcon#end of sib2, iclass 29, count 0 2006.183.08:10:30.84#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:10:30.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:10:30.84#ibcon#[27=USB\r\n] 2006.183.08:10:30.84#ibcon#*before write, iclass 29, count 0 2006.183.08:10:30.84#ibcon#enter sib2, iclass 29, count 0 2006.183.08:10:30.84#ibcon#flushed, iclass 29, count 0 2006.183.08:10:30.84#ibcon#about to write, iclass 29, count 0 2006.183.08:10:30.84#ibcon#wrote, iclass 29, count 0 2006.183.08:10:30.84#ibcon#about to read 3, iclass 29, count 0 2006.183.08:10:30.87#ibcon#read 3, iclass 29, count 0 2006.183.08:10:30.87#ibcon#about to read 4, iclass 29, count 0 2006.183.08:10:30.87#ibcon#read 4, iclass 29, count 0 2006.183.08:10:30.87#ibcon#about to read 5, iclass 29, count 0 2006.183.08:10:30.87#ibcon#read 5, iclass 29, count 0 2006.183.08:10:30.87#ibcon#about to read 6, iclass 29, count 0 2006.183.08:10:30.87#ibcon#read 6, iclass 29, count 0 2006.183.08:10:30.87#ibcon#end of sib2, iclass 29, count 0 2006.183.08:10:30.87#ibcon#*after write, iclass 29, count 0 2006.183.08:10:30.87#ibcon#*before return 0, iclass 29, count 0 2006.183.08:10:30.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:10:30.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:10:30.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:10:30.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:10:30.87$vc4f8/vblo=2,640.99 2006.183.08:10:30.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.08:10:30.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.08:10:30.87#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:30.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:10:30.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:10:30.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:10:30.88#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:10:30.88#ibcon#first serial, iclass 31, count 0 2006.183.08:10:30.88#ibcon#enter sib2, iclass 31, count 0 2006.183.08:10:30.88#ibcon#flushed, iclass 31, count 0 2006.183.08:10:30.88#ibcon#about to write, iclass 31, count 0 2006.183.08:10:30.88#ibcon#wrote, iclass 31, count 0 2006.183.08:10:30.88#ibcon#about to read 3, iclass 31, count 0 2006.183.08:10:30.89#ibcon#read 3, iclass 31, count 0 2006.183.08:10:30.89#ibcon#about to read 4, iclass 31, count 0 2006.183.08:10:30.89#ibcon#read 4, iclass 31, count 0 2006.183.08:10:30.89#ibcon#about to read 5, iclass 31, count 0 2006.183.08:10:30.89#ibcon#read 5, iclass 31, count 0 2006.183.08:10:30.89#ibcon#about to read 6, iclass 31, count 0 2006.183.08:10:30.89#ibcon#read 6, iclass 31, count 0 2006.183.08:10:30.89#ibcon#end of sib2, iclass 31, count 0 2006.183.08:10:30.89#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:10:30.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:10:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:10:30.89#ibcon#*before write, iclass 31, count 0 2006.183.08:10:30.89#ibcon#enter sib2, iclass 31, count 0 2006.183.08:10:30.89#ibcon#flushed, iclass 31, count 0 2006.183.08:10:30.89#ibcon#about to write, iclass 31, count 0 2006.183.08:10:30.89#ibcon#wrote, iclass 31, count 0 2006.183.08:10:30.89#ibcon#about to read 3, iclass 31, count 0 2006.183.08:10:30.93#ibcon#read 3, iclass 31, count 0 2006.183.08:10:30.93#ibcon#about to read 4, iclass 31, count 0 2006.183.08:10:30.93#ibcon#read 4, iclass 31, count 0 2006.183.08:10:30.93#ibcon#about to read 5, iclass 31, count 0 2006.183.08:10:30.93#ibcon#read 5, iclass 31, count 0 2006.183.08:10:30.93#ibcon#about to read 6, iclass 31, count 0 2006.183.08:10:30.93#ibcon#read 6, iclass 31, count 0 2006.183.08:10:30.93#ibcon#end of sib2, iclass 31, count 0 2006.183.08:10:30.93#ibcon#*after write, iclass 31, count 0 2006.183.08:10:30.93#ibcon#*before return 0, iclass 31, count 0 2006.183.08:10:30.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:10:30.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:10:30.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:10:30.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:10:30.93$vc4f8/vb=2,4 2006.183.08:10:30.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.08:10:30.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.08:10:30.94#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:30.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:10:30.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:10:30.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:10:30.98#ibcon#enter wrdev, iclass 33, count 2 2006.183.08:10:30.98#ibcon#first serial, iclass 33, count 2 2006.183.08:10:30.98#ibcon#enter sib2, iclass 33, count 2 2006.183.08:10:30.98#ibcon#flushed, iclass 33, count 2 2006.183.08:10:30.98#ibcon#about to write, iclass 33, count 2 2006.183.08:10:30.98#ibcon#wrote, iclass 33, count 2 2006.183.08:10:30.98#ibcon#about to read 3, iclass 33, count 2 2006.183.08:10:31.00#ibcon#read 3, iclass 33, count 2 2006.183.08:10:31.00#ibcon#about to read 4, iclass 33, count 2 2006.183.08:10:31.00#ibcon#read 4, iclass 33, count 2 2006.183.08:10:31.00#ibcon#about to read 5, iclass 33, count 2 2006.183.08:10:31.00#ibcon#read 5, iclass 33, count 2 2006.183.08:10:31.00#ibcon#about to read 6, iclass 33, count 2 2006.183.08:10:31.00#ibcon#read 6, iclass 33, count 2 2006.183.08:10:31.00#ibcon#end of sib2, iclass 33, count 2 2006.183.08:10:31.00#ibcon#*mode == 0, iclass 33, count 2 2006.183.08:10:31.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.08:10:31.00#ibcon#[27=AT02-04\r\n] 2006.183.08:10:31.00#ibcon#*before write, iclass 33, count 2 2006.183.08:10:31.00#ibcon#enter sib2, iclass 33, count 2 2006.183.08:10:31.00#ibcon#flushed, iclass 33, count 2 2006.183.08:10:31.00#ibcon#about to write, iclass 33, count 2 2006.183.08:10:31.00#ibcon#wrote, iclass 33, count 2 2006.183.08:10:31.00#ibcon#about to read 3, iclass 33, count 2 2006.183.08:10:31.03#ibcon#read 3, iclass 33, count 2 2006.183.08:10:31.03#ibcon#about to read 4, iclass 33, count 2 2006.183.08:10:31.03#ibcon#read 4, iclass 33, count 2 2006.183.08:10:31.03#ibcon#about to read 5, iclass 33, count 2 2006.183.08:10:31.03#ibcon#read 5, iclass 33, count 2 2006.183.08:10:31.03#ibcon#about to read 6, iclass 33, count 2 2006.183.08:10:31.03#ibcon#read 6, iclass 33, count 2 2006.183.08:10:31.03#ibcon#end of sib2, iclass 33, count 2 2006.183.08:10:31.03#ibcon#*after write, iclass 33, count 2 2006.183.08:10:31.03#ibcon#*before return 0, iclass 33, count 2 2006.183.08:10:31.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:10:31.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:10:31.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.08:10:31.03#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:31.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:10:31.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:10:31.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:10:31.15#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:10:31.15#ibcon#first serial, iclass 33, count 0 2006.183.08:10:31.15#ibcon#enter sib2, iclass 33, count 0 2006.183.08:10:31.15#ibcon#flushed, iclass 33, count 0 2006.183.08:10:31.15#ibcon#about to write, iclass 33, count 0 2006.183.08:10:31.15#ibcon#wrote, iclass 33, count 0 2006.183.08:10:31.15#ibcon#about to read 3, iclass 33, count 0 2006.183.08:10:31.17#ibcon#read 3, iclass 33, count 0 2006.183.08:10:31.17#ibcon#about to read 4, iclass 33, count 0 2006.183.08:10:31.17#ibcon#read 4, iclass 33, count 0 2006.183.08:10:31.17#ibcon#about to read 5, iclass 33, count 0 2006.183.08:10:31.17#ibcon#read 5, iclass 33, count 0 2006.183.08:10:31.17#ibcon#about to read 6, iclass 33, count 0 2006.183.08:10:31.17#ibcon#read 6, iclass 33, count 0 2006.183.08:10:31.17#ibcon#end of sib2, iclass 33, count 0 2006.183.08:10:31.17#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:10:31.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:10:31.17#ibcon#[27=USB\r\n] 2006.183.08:10:31.17#ibcon#*before write, iclass 33, count 0 2006.183.08:10:31.17#ibcon#enter sib2, iclass 33, count 0 2006.183.08:10:31.17#ibcon#flushed, iclass 33, count 0 2006.183.08:10:31.17#ibcon#about to write, iclass 33, count 0 2006.183.08:10:31.17#ibcon#wrote, iclass 33, count 0 2006.183.08:10:31.17#ibcon#about to read 3, iclass 33, count 0 2006.183.08:10:31.21#ibcon#read 3, iclass 33, count 0 2006.183.08:10:31.21#ibcon#about to read 4, iclass 33, count 0 2006.183.08:10:31.21#ibcon#read 4, iclass 33, count 0 2006.183.08:10:31.21#ibcon#about to read 5, iclass 33, count 0 2006.183.08:10:31.21#ibcon#read 5, iclass 33, count 0 2006.183.08:10:31.21#ibcon#about to read 6, iclass 33, count 0 2006.183.08:10:31.21#ibcon#read 6, iclass 33, count 0 2006.183.08:10:31.21#ibcon#end of sib2, iclass 33, count 0 2006.183.08:10:31.21#ibcon#*after write, iclass 33, count 0 2006.183.08:10:31.21#ibcon#*before return 0, iclass 33, count 0 2006.183.08:10:31.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:10:31.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:10:31.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:10:31.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:10:31.21$vc4f8/vblo=3,656.99 2006.183.08:10:31.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.08:10:31.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.08:10:31.21#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:31.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:31.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:31.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:31.21#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:10:31.21#ibcon#first serial, iclass 35, count 0 2006.183.08:10:31.21#ibcon#enter sib2, iclass 35, count 0 2006.183.08:10:31.21#ibcon#flushed, iclass 35, count 0 2006.183.08:10:31.21#ibcon#about to write, iclass 35, count 0 2006.183.08:10:31.21#ibcon#wrote, iclass 35, count 0 2006.183.08:10:31.21#ibcon#about to read 3, iclass 35, count 0 2006.183.08:10:31.22#ibcon#read 3, iclass 35, count 0 2006.183.08:10:31.22#ibcon#about to read 4, iclass 35, count 0 2006.183.08:10:31.22#ibcon#read 4, iclass 35, count 0 2006.183.08:10:31.22#ibcon#about to read 5, iclass 35, count 0 2006.183.08:10:31.22#ibcon#read 5, iclass 35, count 0 2006.183.08:10:31.22#ibcon#about to read 6, iclass 35, count 0 2006.183.08:10:31.22#ibcon#read 6, iclass 35, count 0 2006.183.08:10:31.22#ibcon#end of sib2, iclass 35, count 0 2006.183.08:10:31.22#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:10:31.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:10:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:10:31.22#ibcon#*before write, iclass 35, count 0 2006.183.08:10:31.22#ibcon#enter sib2, iclass 35, count 0 2006.183.08:10:31.22#ibcon#flushed, iclass 35, count 0 2006.183.08:10:31.22#ibcon#about to write, iclass 35, count 0 2006.183.08:10:31.22#ibcon#wrote, iclass 35, count 0 2006.183.08:10:31.22#ibcon#about to read 3, iclass 35, count 0 2006.183.08:10:31.26#ibcon#read 3, iclass 35, count 0 2006.183.08:10:31.26#ibcon#about to read 4, iclass 35, count 0 2006.183.08:10:31.26#ibcon#read 4, iclass 35, count 0 2006.183.08:10:31.26#ibcon#about to read 5, iclass 35, count 0 2006.183.08:10:31.26#ibcon#read 5, iclass 35, count 0 2006.183.08:10:31.26#ibcon#about to read 6, iclass 35, count 0 2006.183.08:10:31.26#ibcon#read 6, iclass 35, count 0 2006.183.08:10:31.26#ibcon#end of sib2, iclass 35, count 0 2006.183.08:10:31.26#ibcon#*after write, iclass 35, count 0 2006.183.08:10:31.26#ibcon#*before return 0, iclass 35, count 0 2006.183.08:10:31.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:31.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:10:31.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:10:31.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:10:31.26$vc4f8/vb=3,4 2006.183.08:10:31.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.08:10:31.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.08:10:31.26#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:31.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:31.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:31.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:31.33#ibcon#enter wrdev, iclass 37, count 2 2006.183.08:10:31.33#ibcon#first serial, iclass 37, count 2 2006.183.08:10:31.33#ibcon#enter sib2, iclass 37, count 2 2006.183.08:10:31.33#ibcon#flushed, iclass 37, count 2 2006.183.08:10:31.33#ibcon#about to write, iclass 37, count 2 2006.183.08:10:31.33#ibcon#wrote, iclass 37, count 2 2006.183.08:10:31.33#ibcon#about to read 3, iclass 37, count 2 2006.183.08:10:31.35#ibcon#read 3, iclass 37, count 2 2006.183.08:10:31.35#ibcon#about to read 4, iclass 37, count 2 2006.183.08:10:31.35#ibcon#read 4, iclass 37, count 2 2006.183.08:10:31.35#ibcon#about to read 5, iclass 37, count 2 2006.183.08:10:31.35#ibcon#read 5, iclass 37, count 2 2006.183.08:10:31.35#ibcon#about to read 6, iclass 37, count 2 2006.183.08:10:31.35#ibcon#read 6, iclass 37, count 2 2006.183.08:10:31.35#ibcon#end of sib2, iclass 37, count 2 2006.183.08:10:31.35#ibcon#*mode == 0, iclass 37, count 2 2006.183.08:10:31.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.08:10:31.35#ibcon#[27=AT03-04\r\n] 2006.183.08:10:31.35#ibcon#*before write, iclass 37, count 2 2006.183.08:10:31.35#ibcon#enter sib2, iclass 37, count 2 2006.183.08:10:31.35#ibcon#flushed, iclass 37, count 2 2006.183.08:10:31.35#ibcon#about to write, iclass 37, count 2 2006.183.08:10:31.35#ibcon#wrote, iclass 37, count 2 2006.183.08:10:31.35#ibcon#about to read 3, iclass 37, count 2 2006.183.08:10:31.38#ibcon#read 3, iclass 37, count 2 2006.183.08:10:31.38#ibcon#about to read 4, iclass 37, count 2 2006.183.08:10:31.38#ibcon#read 4, iclass 37, count 2 2006.183.08:10:31.38#ibcon#about to read 5, iclass 37, count 2 2006.183.08:10:31.38#ibcon#read 5, iclass 37, count 2 2006.183.08:10:31.38#ibcon#about to read 6, iclass 37, count 2 2006.183.08:10:31.38#ibcon#read 6, iclass 37, count 2 2006.183.08:10:31.38#ibcon#end of sib2, iclass 37, count 2 2006.183.08:10:31.38#ibcon#*after write, iclass 37, count 2 2006.183.08:10:31.38#ibcon#*before return 0, iclass 37, count 2 2006.183.08:10:31.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:31.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:10:31.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.08:10:31.38#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:31.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:31.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:31.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:31.50#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:10:31.50#ibcon#first serial, iclass 37, count 0 2006.183.08:10:31.50#ibcon#enter sib2, iclass 37, count 0 2006.183.08:10:31.50#ibcon#flushed, iclass 37, count 0 2006.183.08:10:31.50#ibcon#about to write, iclass 37, count 0 2006.183.08:10:31.50#ibcon#wrote, iclass 37, count 0 2006.183.08:10:31.50#ibcon#about to read 3, iclass 37, count 0 2006.183.08:10:31.52#ibcon#read 3, iclass 37, count 0 2006.183.08:10:31.52#ibcon#about to read 4, iclass 37, count 0 2006.183.08:10:31.52#ibcon#read 4, iclass 37, count 0 2006.183.08:10:31.52#ibcon#about to read 5, iclass 37, count 0 2006.183.08:10:31.52#ibcon#read 5, iclass 37, count 0 2006.183.08:10:31.52#ibcon#about to read 6, iclass 37, count 0 2006.183.08:10:31.52#ibcon#read 6, iclass 37, count 0 2006.183.08:10:31.52#ibcon#end of sib2, iclass 37, count 0 2006.183.08:10:31.52#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:10:31.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:10:31.52#ibcon#[27=USB\r\n] 2006.183.08:10:31.52#ibcon#*before write, iclass 37, count 0 2006.183.08:10:31.52#ibcon#enter sib2, iclass 37, count 0 2006.183.08:10:31.52#ibcon#flushed, iclass 37, count 0 2006.183.08:10:31.52#ibcon#about to write, iclass 37, count 0 2006.183.08:10:31.52#ibcon#wrote, iclass 37, count 0 2006.183.08:10:31.52#ibcon#about to read 3, iclass 37, count 0 2006.183.08:10:31.55#ibcon#read 3, iclass 37, count 0 2006.183.08:10:31.55#ibcon#about to read 4, iclass 37, count 0 2006.183.08:10:31.55#ibcon#read 4, iclass 37, count 0 2006.183.08:10:31.55#ibcon#about to read 5, iclass 37, count 0 2006.183.08:10:31.55#ibcon#read 5, iclass 37, count 0 2006.183.08:10:31.55#ibcon#about to read 6, iclass 37, count 0 2006.183.08:10:31.55#ibcon#read 6, iclass 37, count 0 2006.183.08:10:31.55#ibcon#end of sib2, iclass 37, count 0 2006.183.08:10:31.55#ibcon#*after write, iclass 37, count 0 2006.183.08:10:31.55#ibcon#*before return 0, iclass 37, count 0 2006.183.08:10:31.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:31.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:10:31.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:10:31.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:10:31.55$vc4f8/vblo=4,712.99 2006.183.08:10:31.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.08:10:31.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.08:10:31.55#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:31.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:31.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:31.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:31.56#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:10:31.56#ibcon#first serial, iclass 39, count 0 2006.183.08:10:31.56#ibcon#enter sib2, iclass 39, count 0 2006.183.08:10:31.56#ibcon#flushed, iclass 39, count 0 2006.183.08:10:31.56#ibcon#about to write, iclass 39, count 0 2006.183.08:10:31.56#ibcon#wrote, iclass 39, count 0 2006.183.08:10:31.56#ibcon#about to read 3, iclass 39, count 0 2006.183.08:10:31.57#ibcon#read 3, iclass 39, count 0 2006.183.08:10:31.57#ibcon#about to read 4, iclass 39, count 0 2006.183.08:10:31.57#ibcon#read 4, iclass 39, count 0 2006.183.08:10:31.57#ibcon#about to read 5, iclass 39, count 0 2006.183.08:10:31.57#ibcon#read 5, iclass 39, count 0 2006.183.08:10:31.57#ibcon#about to read 6, iclass 39, count 0 2006.183.08:10:31.57#ibcon#read 6, iclass 39, count 0 2006.183.08:10:31.57#ibcon#end of sib2, iclass 39, count 0 2006.183.08:10:31.57#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:10:31.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:10:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:10:31.57#ibcon#*before write, iclass 39, count 0 2006.183.08:10:31.57#ibcon#enter sib2, iclass 39, count 0 2006.183.08:10:31.57#ibcon#flushed, iclass 39, count 0 2006.183.08:10:31.57#ibcon#about to write, iclass 39, count 0 2006.183.08:10:31.57#ibcon#wrote, iclass 39, count 0 2006.183.08:10:31.57#ibcon#about to read 3, iclass 39, count 0 2006.183.08:10:31.61#ibcon#read 3, iclass 39, count 0 2006.183.08:10:31.61#ibcon#about to read 4, iclass 39, count 0 2006.183.08:10:31.61#ibcon#read 4, iclass 39, count 0 2006.183.08:10:31.61#ibcon#about to read 5, iclass 39, count 0 2006.183.08:10:31.61#ibcon#read 5, iclass 39, count 0 2006.183.08:10:31.61#ibcon#about to read 6, iclass 39, count 0 2006.183.08:10:31.61#ibcon#read 6, iclass 39, count 0 2006.183.08:10:31.61#ibcon#end of sib2, iclass 39, count 0 2006.183.08:10:31.61#ibcon#*after write, iclass 39, count 0 2006.183.08:10:31.61#ibcon#*before return 0, iclass 39, count 0 2006.183.08:10:31.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:31.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:10:31.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:10:31.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:10:31.61$vc4f8/vb=4,4 2006.183.08:10:31.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.183.08:10:31.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.183.08:10:31.61#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:31.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:31.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:31.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:31.67#ibcon#enter wrdev, iclass 3, count 2 2006.183.08:10:31.67#ibcon#first serial, iclass 3, count 2 2006.183.08:10:31.67#ibcon#enter sib2, iclass 3, count 2 2006.183.08:10:31.67#ibcon#flushed, iclass 3, count 2 2006.183.08:10:31.67#ibcon#about to write, iclass 3, count 2 2006.183.08:10:31.67#ibcon#wrote, iclass 3, count 2 2006.183.08:10:31.67#ibcon#about to read 3, iclass 3, count 2 2006.183.08:10:31.69#ibcon#read 3, iclass 3, count 2 2006.183.08:10:31.69#ibcon#about to read 4, iclass 3, count 2 2006.183.08:10:31.69#ibcon#read 4, iclass 3, count 2 2006.183.08:10:31.69#ibcon#about to read 5, iclass 3, count 2 2006.183.08:10:31.69#ibcon#read 5, iclass 3, count 2 2006.183.08:10:31.69#ibcon#about to read 6, iclass 3, count 2 2006.183.08:10:31.69#ibcon#read 6, iclass 3, count 2 2006.183.08:10:31.69#ibcon#end of sib2, iclass 3, count 2 2006.183.08:10:31.69#ibcon#*mode == 0, iclass 3, count 2 2006.183.08:10:31.69#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.183.08:10:31.69#ibcon#[27=AT04-04\r\n] 2006.183.08:10:31.69#ibcon#*before write, iclass 3, count 2 2006.183.08:10:31.69#ibcon#enter sib2, iclass 3, count 2 2006.183.08:10:31.69#ibcon#flushed, iclass 3, count 2 2006.183.08:10:31.69#ibcon#about to write, iclass 3, count 2 2006.183.08:10:31.69#ibcon#wrote, iclass 3, count 2 2006.183.08:10:31.69#ibcon#about to read 3, iclass 3, count 2 2006.183.08:10:31.72#ibcon#read 3, iclass 3, count 2 2006.183.08:10:31.72#ibcon#about to read 4, iclass 3, count 2 2006.183.08:10:31.72#ibcon#read 4, iclass 3, count 2 2006.183.08:10:31.72#ibcon#about to read 5, iclass 3, count 2 2006.183.08:10:31.72#ibcon#read 5, iclass 3, count 2 2006.183.08:10:31.72#ibcon#about to read 6, iclass 3, count 2 2006.183.08:10:31.72#ibcon#read 6, iclass 3, count 2 2006.183.08:10:31.72#ibcon#end of sib2, iclass 3, count 2 2006.183.08:10:31.72#ibcon#*after write, iclass 3, count 2 2006.183.08:10:31.72#ibcon#*before return 0, iclass 3, count 2 2006.183.08:10:31.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:31.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:10:31.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.183.08:10:31.72#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:31.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:31.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:31.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:31.84#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:10:31.84#ibcon#first serial, iclass 3, count 0 2006.183.08:10:31.84#ibcon#enter sib2, iclass 3, count 0 2006.183.08:10:31.84#ibcon#flushed, iclass 3, count 0 2006.183.08:10:31.84#ibcon#about to write, iclass 3, count 0 2006.183.08:10:31.84#ibcon#wrote, iclass 3, count 0 2006.183.08:10:31.84#ibcon#about to read 3, iclass 3, count 0 2006.183.08:10:31.86#ibcon#read 3, iclass 3, count 0 2006.183.08:10:31.86#ibcon#about to read 4, iclass 3, count 0 2006.183.08:10:31.86#ibcon#read 4, iclass 3, count 0 2006.183.08:10:31.86#ibcon#about to read 5, iclass 3, count 0 2006.183.08:10:31.86#ibcon#read 5, iclass 3, count 0 2006.183.08:10:31.86#ibcon#about to read 6, iclass 3, count 0 2006.183.08:10:31.86#ibcon#read 6, iclass 3, count 0 2006.183.08:10:31.86#ibcon#end of sib2, iclass 3, count 0 2006.183.08:10:31.86#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:10:31.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:10:31.86#ibcon#[27=USB\r\n] 2006.183.08:10:31.86#ibcon#*before write, iclass 3, count 0 2006.183.08:10:31.86#ibcon#enter sib2, iclass 3, count 0 2006.183.08:10:31.86#ibcon#flushed, iclass 3, count 0 2006.183.08:10:31.86#ibcon#about to write, iclass 3, count 0 2006.183.08:10:31.86#ibcon#wrote, iclass 3, count 0 2006.183.08:10:31.86#ibcon#about to read 3, iclass 3, count 0 2006.183.08:10:31.89#ibcon#read 3, iclass 3, count 0 2006.183.08:10:31.89#ibcon#about to read 4, iclass 3, count 0 2006.183.08:10:31.89#ibcon#read 4, iclass 3, count 0 2006.183.08:10:31.89#ibcon#about to read 5, iclass 3, count 0 2006.183.08:10:31.89#ibcon#read 5, iclass 3, count 0 2006.183.08:10:31.89#ibcon#about to read 6, iclass 3, count 0 2006.183.08:10:31.89#ibcon#read 6, iclass 3, count 0 2006.183.08:10:31.89#ibcon#end of sib2, iclass 3, count 0 2006.183.08:10:31.89#ibcon#*after write, iclass 3, count 0 2006.183.08:10:31.89#ibcon#*before return 0, iclass 3, count 0 2006.183.08:10:31.89#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:31.89#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:10:31.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:10:31.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:10:31.89$vc4f8/vblo=5,744.99 2006.183.08:10:31.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.08:10:31.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.08:10:31.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:31.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:31.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:31.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:31.90#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:10:31.90#ibcon#first serial, iclass 5, count 0 2006.183.08:10:31.90#ibcon#enter sib2, iclass 5, count 0 2006.183.08:10:31.90#ibcon#flushed, iclass 5, count 0 2006.183.08:10:31.90#ibcon#about to write, iclass 5, count 0 2006.183.08:10:31.90#ibcon#wrote, iclass 5, count 0 2006.183.08:10:31.90#ibcon#about to read 3, iclass 5, count 0 2006.183.08:10:31.91#ibcon#read 3, iclass 5, count 0 2006.183.08:10:31.91#ibcon#about to read 4, iclass 5, count 0 2006.183.08:10:31.91#ibcon#read 4, iclass 5, count 0 2006.183.08:10:31.91#ibcon#about to read 5, iclass 5, count 0 2006.183.08:10:31.91#ibcon#read 5, iclass 5, count 0 2006.183.08:10:31.91#ibcon#about to read 6, iclass 5, count 0 2006.183.08:10:31.91#ibcon#read 6, iclass 5, count 0 2006.183.08:10:31.91#ibcon#end of sib2, iclass 5, count 0 2006.183.08:10:31.91#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:10:31.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:10:31.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:10:31.91#ibcon#*before write, iclass 5, count 0 2006.183.08:10:31.91#ibcon#enter sib2, iclass 5, count 0 2006.183.08:10:31.91#ibcon#flushed, iclass 5, count 0 2006.183.08:10:31.91#ibcon#about to write, iclass 5, count 0 2006.183.08:10:31.91#ibcon#wrote, iclass 5, count 0 2006.183.08:10:31.91#ibcon#about to read 3, iclass 5, count 0 2006.183.08:10:31.95#ibcon#read 3, iclass 5, count 0 2006.183.08:10:31.95#ibcon#about to read 4, iclass 5, count 0 2006.183.08:10:31.95#ibcon#read 4, iclass 5, count 0 2006.183.08:10:31.95#ibcon#about to read 5, iclass 5, count 0 2006.183.08:10:31.95#ibcon#read 5, iclass 5, count 0 2006.183.08:10:31.95#ibcon#about to read 6, iclass 5, count 0 2006.183.08:10:31.95#ibcon#read 6, iclass 5, count 0 2006.183.08:10:31.95#ibcon#end of sib2, iclass 5, count 0 2006.183.08:10:31.95#ibcon#*after write, iclass 5, count 0 2006.183.08:10:31.95#ibcon#*before return 0, iclass 5, count 0 2006.183.08:10:31.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:31.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:10:31.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:10:31.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:10:31.95$vc4f8/vb=5,4 2006.183.08:10:31.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.08:10:31.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.08:10:31.96#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:31.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:32.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:32.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:32.01#ibcon#enter wrdev, iclass 7, count 2 2006.183.08:10:32.01#ibcon#first serial, iclass 7, count 2 2006.183.08:10:32.01#ibcon#enter sib2, iclass 7, count 2 2006.183.08:10:32.01#ibcon#flushed, iclass 7, count 2 2006.183.08:10:32.01#ibcon#about to write, iclass 7, count 2 2006.183.08:10:32.01#ibcon#wrote, iclass 7, count 2 2006.183.08:10:32.01#ibcon#about to read 3, iclass 7, count 2 2006.183.08:10:32.02#ibcon#read 3, iclass 7, count 2 2006.183.08:10:32.02#ibcon#about to read 4, iclass 7, count 2 2006.183.08:10:32.02#ibcon#read 4, iclass 7, count 2 2006.183.08:10:32.02#ibcon#about to read 5, iclass 7, count 2 2006.183.08:10:32.02#ibcon#read 5, iclass 7, count 2 2006.183.08:10:32.02#ibcon#about to read 6, iclass 7, count 2 2006.183.08:10:32.02#ibcon#read 6, iclass 7, count 2 2006.183.08:10:32.02#ibcon#end of sib2, iclass 7, count 2 2006.183.08:10:32.02#ibcon#*mode == 0, iclass 7, count 2 2006.183.08:10:32.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.08:10:32.02#ibcon#[27=AT05-04\r\n] 2006.183.08:10:32.02#ibcon#*before write, iclass 7, count 2 2006.183.08:10:32.02#ibcon#enter sib2, iclass 7, count 2 2006.183.08:10:32.02#ibcon#flushed, iclass 7, count 2 2006.183.08:10:32.02#ibcon#about to write, iclass 7, count 2 2006.183.08:10:32.02#ibcon#wrote, iclass 7, count 2 2006.183.08:10:32.02#ibcon#about to read 3, iclass 7, count 2 2006.183.08:10:32.05#ibcon#read 3, iclass 7, count 2 2006.183.08:10:32.05#ibcon#about to read 4, iclass 7, count 2 2006.183.08:10:32.05#ibcon#read 4, iclass 7, count 2 2006.183.08:10:32.05#ibcon#about to read 5, iclass 7, count 2 2006.183.08:10:32.05#ibcon#read 5, iclass 7, count 2 2006.183.08:10:32.05#ibcon#about to read 6, iclass 7, count 2 2006.183.08:10:32.05#ibcon#read 6, iclass 7, count 2 2006.183.08:10:32.05#ibcon#end of sib2, iclass 7, count 2 2006.183.08:10:32.05#ibcon#*after write, iclass 7, count 2 2006.183.08:10:32.05#ibcon#*before return 0, iclass 7, count 2 2006.183.08:10:32.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:32.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:10:32.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.08:10:32.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:32.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:32.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:32.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:32.17#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:10:32.17#ibcon#first serial, iclass 7, count 0 2006.183.08:10:32.17#ibcon#enter sib2, iclass 7, count 0 2006.183.08:10:32.17#ibcon#flushed, iclass 7, count 0 2006.183.08:10:32.17#ibcon#about to write, iclass 7, count 0 2006.183.08:10:32.17#ibcon#wrote, iclass 7, count 0 2006.183.08:10:32.17#ibcon#about to read 3, iclass 7, count 0 2006.183.08:10:32.19#ibcon#read 3, iclass 7, count 0 2006.183.08:10:32.19#ibcon#about to read 4, iclass 7, count 0 2006.183.08:10:32.19#ibcon#read 4, iclass 7, count 0 2006.183.08:10:32.19#ibcon#about to read 5, iclass 7, count 0 2006.183.08:10:32.19#ibcon#read 5, iclass 7, count 0 2006.183.08:10:32.19#ibcon#about to read 6, iclass 7, count 0 2006.183.08:10:32.19#ibcon#read 6, iclass 7, count 0 2006.183.08:10:32.19#ibcon#end of sib2, iclass 7, count 0 2006.183.08:10:32.19#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:10:32.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:10:32.19#ibcon#[27=USB\r\n] 2006.183.08:10:32.19#ibcon#*before write, iclass 7, count 0 2006.183.08:10:32.19#ibcon#enter sib2, iclass 7, count 0 2006.183.08:10:32.19#ibcon#flushed, iclass 7, count 0 2006.183.08:10:32.19#ibcon#about to write, iclass 7, count 0 2006.183.08:10:32.19#ibcon#wrote, iclass 7, count 0 2006.183.08:10:32.19#ibcon#about to read 3, iclass 7, count 0 2006.183.08:10:32.22#ibcon#read 3, iclass 7, count 0 2006.183.08:10:32.22#ibcon#about to read 4, iclass 7, count 0 2006.183.08:10:32.22#ibcon#read 4, iclass 7, count 0 2006.183.08:10:32.22#ibcon#about to read 5, iclass 7, count 0 2006.183.08:10:32.22#ibcon#read 5, iclass 7, count 0 2006.183.08:10:32.22#ibcon#about to read 6, iclass 7, count 0 2006.183.08:10:32.22#ibcon#read 6, iclass 7, count 0 2006.183.08:10:32.22#ibcon#end of sib2, iclass 7, count 0 2006.183.08:10:32.22#ibcon#*after write, iclass 7, count 0 2006.183.08:10:32.22#ibcon#*before return 0, iclass 7, count 0 2006.183.08:10:32.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:32.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:10:32.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:10:32.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:10:32.22$vc4f8/vblo=6,752.99 2006.183.08:10:32.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:10:32.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:10:32.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:10:32.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:32.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:32.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:32.23#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:10:32.23#ibcon#first serial, iclass 11, count 0 2006.183.08:10:32.23#ibcon#enter sib2, iclass 11, count 0 2006.183.08:10:32.23#ibcon#flushed, iclass 11, count 0 2006.183.08:10:32.23#ibcon#about to write, iclass 11, count 0 2006.183.08:10:32.23#ibcon#wrote, iclass 11, count 0 2006.183.08:10:32.23#ibcon#about to read 3, iclass 11, count 0 2006.183.08:10:32.24#ibcon#read 3, iclass 11, count 0 2006.183.08:10:32.24#ibcon#about to read 4, iclass 11, count 0 2006.183.08:10:32.24#ibcon#read 4, iclass 11, count 0 2006.183.08:10:32.24#ibcon#about to read 5, iclass 11, count 0 2006.183.08:10:32.24#ibcon#read 5, iclass 11, count 0 2006.183.08:10:32.24#ibcon#about to read 6, iclass 11, count 0 2006.183.08:10:32.24#ibcon#read 6, iclass 11, count 0 2006.183.08:10:32.24#ibcon#end of sib2, iclass 11, count 0 2006.183.08:10:32.24#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:10:32.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:10:32.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:10:32.24#ibcon#*before write, iclass 11, count 0 2006.183.08:10:32.24#ibcon#enter sib2, iclass 11, count 0 2006.183.08:10:32.24#ibcon#flushed, iclass 11, count 0 2006.183.08:10:32.24#ibcon#about to write, iclass 11, count 0 2006.183.08:10:32.24#ibcon#wrote, iclass 11, count 0 2006.183.08:10:32.24#ibcon#about to read 3, iclass 11, count 0 2006.183.08:10:32.28#ibcon#read 3, iclass 11, count 0 2006.183.08:10:32.28#ibcon#about to read 4, iclass 11, count 0 2006.183.08:10:32.28#ibcon#read 4, iclass 11, count 0 2006.183.08:10:32.28#ibcon#about to read 5, iclass 11, count 0 2006.183.08:10:32.28#ibcon#read 5, iclass 11, count 0 2006.183.08:10:32.28#ibcon#about to read 6, iclass 11, count 0 2006.183.08:10:32.28#ibcon#read 6, iclass 11, count 0 2006.183.08:10:32.28#ibcon#end of sib2, iclass 11, count 0 2006.183.08:10:32.28#ibcon#*after write, iclass 11, count 0 2006.183.08:10:32.28#ibcon#*before return 0, iclass 11, count 0 2006.183.08:10:32.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:32.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:10:32.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:10:32.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:10:32.28$vc4f8/vb=6,4 2006.183.08:10:32.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.08:10:32.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.08:10:32.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:10:32.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:32.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:32.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:32.34#ibcon#enter wrdev, iclass 13, count 2 2006.183.08:10:32.34#ibcon#first serial, iclass 13, count 2 2006.183.08:10:32.34#ibcon#enter sib2, iclass 13, count 2 2006.183.08:10:32.34#ibcon#flushed, iclass 13, count 2 2006.183.08:10:32.34#ibcon#about to write, iclass 13, count 2 2006.183.08:10:32.34#ibcon#wrote, iclass 13, count 2 2006.183.08:10:32.34#ibcon#about to read 3, iclass 13, count 2 2006.183.08:10:32.36#ibcon#read 3, iclass 13, count 2 2006.183.08:10:32.36#ibcon#about to read 4, iclass 13, count 2 2006.183.08:10:32.36#ibcon#read 4, iclass 13, count 2 2006.183.08:10:32.36#ibcon#about to read 5, iclass 13, count 2 2006.183.08:10:32.36#ibcon#read 5, iclass 13, count 2 2006.183.08:10:32.36#ibcon#about to read 6, iclass 13, count 2 2006.183.08:10:32.36#ibcon#read 6, iclass 13, count 2 2006.183.08:10:32.36#ibcon#end of sib2, iclass 13, count 2 2006.183.08:10:32.36#ibcon#*mode == 0, iclass 13, count 2 2006.183.08:10:32.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.08:10:32.36#ibcon#[27=AT06-04\r\n] 2006.183.08:10:32.36#ibcon#*before write, iclass 13, count 2 2006.183.08:10:32.36#ibcon#enter sib2, iclass 13, count 2 2006.183.08:10:32.36#ibcon#flushed, iclass 13, count 2 2006.183.08:10:32.36#ibcon#about to write, iclass 13, count 2 2006.183.08:10:32.36#ibcon#wrote, iclass 13, count 2 2006.183.08:10:32.36#ibcon#about to read 3, iclass 13, count 2 2006.183.08:10:32.39#ibcon#read 3, iclass 13, count 2 2006.183.08:10:32.39#ibcon#about to read 4, iclass 13, count 2 2006.183.08:10:32.39#ibcon#read 4, iclass 13, count 2 2006.183.08:10:32.39#ibcon#about to read 5, iclass 13, count 2 2006.183.08:10:32.39#ibcon#read 5, iclass 13, count 2 2006.183.08:10:32.39#ibcon#about to read 6, iclass 13, count 2 2006.183.08:10:32.39#ibcon#read 6, iclass 13, count 2 2006.183.08:10:32.39#ibcon#end of sib2, iclass 13, count 2 2006.183.08:10:32.39#ibcon#*after write, iclass 13, count 2 2006.183.08:10:32.39#ibcon#*before return 0, iclass 13, count 2 2006.183.08:10:32.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:32.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:10:32.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.08:10:32.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:10:32.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:32.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:32.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:32.51#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:10:32.51#ibcon#first serial, iclass 13, count 0 2006.183.08:10:32.51#ibcon#enter sib2, iclass 13, count 0 2006.183.08:10:32.51#ibcon#flushed, iclass 13, count 0 2006.183.08:10:32.51#ibcon#about to write, iclass 13, count 0 2006.183.08:10:32.51#ibcon#wrote, iclass 13, count 0 2006.183.08:10:32.51#ibcon#about to read 3, iclass 13, count 0 2006.183.08:10:32.53#ibcon#read 3, iclass 13, count 0 2006.183.08:10:32.53#ibcon#about to read 4, iclass 13, count 0 2006.183.08:10:32.53#ibcon#read 4, iclass 13, count 0 2006.183.08:10:32.53#ibcon#about to read 5, iclass 13, count 0 2006.183.08:10:32.53#ibcon#read 5, iclass 13, count 0 2006.183.08:10:32.53#ibcon#about to read 6, iclass 13, count 0 2006.183.08:10:32.53#ibcon#read 6, iclass 13, count 0 2006.183.08:10:32.53#ibcon#end of sib2, iclass 13, count 0 2006.183.08:10:32.53#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:10:32.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:10:32.53#ibcon#[27=USB\r\n] 2006.183.08:10:32.53#ibcon#*before write, iclass 13, count 0 2006.183.08:10:32.53#ibcon#enter sib2, iclass 13, count 0 2006.183.08:10:32.53#ibcon#flushed, iclass 13, count 0 2006.183.08:10:32.53#ibcon#about to write, iclass 13, count 0 2006.183.08:10:32.53#ibcon#wrote, iclass 13, count 0 2006.183.08:10:32.53#ibcon#about to read 3, iclass 13, count 0 2006.183.08:10:32.56#ibcon#read 3, iclass 13, count 0 2006.183.08:10:32.56#ibcon#about to read 4, iclass 13, count 0 2006.183.08:10:32.56#ibcon#read 4, iclass 13, count 0 2006.183.08:10:32.56#ibcon#about to read 5, iclass 13, count 0 2006.183.08:10:32.56#ibcon#read 5, iclass 13, count 0 2006.183.08:10:32.56#ibcon#about to read 6, iclass 13, count 0 2006.183.08:10:32.56#ibcon#read 6, iclass 13, count 0 2006.183.08:10:32.56#ibcon#end of sib2, iclass 13, count 0 2006.183.08:10:32.56#ibcon#*after write, iclass 13, count 0 2006.183.08:10:32.56#ibcon#*before return 0, iclass 13, count 0 2006.183.08:10:32.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:32.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:10:32.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:10:32.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:10:32.56$vc4f8/vabw=wide 2006.183.08:10:32.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.08:10:32.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.08:10:32.56#ibcon#ireg 8 cls_cnt 0 2006.183.08:10:32.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:32.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:32.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:32.57#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:10:32.57#ibcon#first serial, iclass 15, count 0 2006.183.08:10:32.57#ibcon#enter sib2, iclass 15, count 0 2006.183.08:10:32.57#ibcon#flushed, iclass 15, count 0 2006.183.08:10:32.57#ibcon#about to write, iclass 15, count 0 2006.183.08:10:32.57#ibcon#wrote, iclass 15, count 0 2006.183.08:10:32.57#ibcon#about to read 3, iclass 15, count 0 2006.183.08:10:32.58#ibcon#read 3, iclass 15, count 0 2006.183.08:10:32.58#ibcon#about to read 4, iclass 15, count 0 2006.183.08:10:32.58#ibcon#read 4, iclass 15, count 0 2006.183.08:10:32.58#ibcon#about to read 5, iclass 15, count 0 2006.183.08:10:32.58#ibcon#read 5, iclass 15, count 0 2006.183.08:10:32.58#ibcon#about to read 6, iclass 15, count 0 2006.183.08:10:32.58#ibcon#read 6, iclass 15, count 0 2006.183.08:10:32.58#ibcon#end of sib2, iclass 15, count 0 2006.183.08:10:32.58#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:10:32.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:10:32.58#ibcon#[25=BW32\r\n] 2006.183.08:10:32.58#ibcon#*before write, iclass 15, count 0 2006.183.08:10:32.58#ibcon#enter sib2, iclass 15, count 0 2006.183.08:10:32.58#ibcon#flushed, iclass 15, count 0 2006.183.08:10:32.58#ibcon#about to write, iclass 15, count 0 2006.183.08:10:32.58#ibcon#wrote, iclass 15, count 0 2006.183.08:10:32.58#ibcon#about to read 3, iclass 15, count 0 2006.183.08:10:32.61#ibcon#read 3, iclass 15, count 0 2006.183.08:10:32.61#ibcon#about to read 4, iclass 15, count 0 2006.183.08:10:32.61#ibcon#read 4, iclass 15, count 0 2006.183.08:10:32.61#ibcon#about to read 5, iclass 15, count 0 2006.183.08:10:32.61#ibcon#read 5, iclass 15, count 0 2006.183.08:10:32.61#ibcon#about to read 6, iclass 15, count 0 2006.183.08:10:32.61#ibcon#read 6, iclass 15, count 0 2006.183.08:10:32.61#ibcon#end of sib2, iclass 15, count 0 2006.183.08:10:32.61#ibcon#*after write, iclass 15, count 0 2006.183.08:10:32.61#ibcon#*before return 0, iclass 15, count 0 2006.183.08:10:32.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:32.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:10:32.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:10:32.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:10:32.61$vc4f8/vbbw=wide 2006.183.08:10:32.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.08:10:32.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.08:10:32.61#ibcon#ireg 8 cls_cnt 0 2006.183.08:10:32.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:10:32.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:10:32.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:10:32.68#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:10:32.68#ibcon#first serial, iclass 17, count 0 2006.183.08:10:32.68#ibcon#enter sib2, iclass 17, count 0 2006.183.08:10:32.68#ibcon#flushed, iclass 17, count 0 2006.183.08:10:32.68#ibcon#about to write, iclass 17, count 0 2006.183.08:10:32.68#ibcon#wrote, iclass 17, count 0 2006.183.08:10:32.68#ibcon#about to read 3, iclass 17, count 0 2006.183.08:10:32.70#ibcon#read 3, iclass 17, count 0 2006.183.08:10:32.70#ibcon#about to read 4, iclass 17, count 0 2006.183.08:10:32.70#ibcon#read 4, iclass 17, count 0 2006.183.08:10:32.70#ibcon#about to read 5, iclass 17, count 0 2006.183.08:10:32.70#ibcon#read 5, iclass 17, count 0 2006.183.08:10:32.70#ibcon#about to read 6, iclass 17, count 0 2006.183.08:10:32.70#ibcon#read 6, iclass 17, count 0 2006.183.08:10:32.70#ibcon#end of sib2, iclass 17, count 0 2006.183.08:10:32.70#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:10:32.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:10:32.70#ibcon#[27=BW32\r\n] 2006.183.08:10:32.70#ibcon#*before write, iclass 17, count 0 2006.183.08:10:32.70#ibcon#enter sib2, iclass 17, count 0 2006.183.08:10:32.70#ibcon#flushed, iclass 17, count 0 2006.183.08:10:32.70#ibcon#about to write, iclass 17, count 0 2006.183.08:10:32.70#ibcon#wrote, iclass 17, count 0 2006.183.08:10:32.70#ibcon#about to read 3, iclass 17, count 0 2006.183.08:10:32.73#ibcon#read 3, iclass 17, count 0 2006.183.08:10:32.73#ibcon#about to read 4, iclass 17, count 0 2006.183.08:10:32.73#ibcon#read 4, iclass 17, count 0 2006.183.08:10:32.73#ibcon#about to read 5, iclass 17, count 0 2006.183.08:10:32.73#ibcon#read 5, iclass 17, count 0 2006.183.08:10:32.73#ibcon#about to read 6, iclass 17, count 0 2006.183.08:10:32.73#ibcon#read 6, iclass 17, count 0 2006.183.08:10:32.73#ibcon#end of sib2, iclass 17, count 0 2006.183.08:10:32.73#ibcon#*after write, iclass 17, count 0 2006.183.08:10:32.73#ibcon#*before return 0, iclass 17, count 0 2006.183.08:10:32.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:10:32.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:10:32.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:10:32.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:10:32.73$4f8m12a/ifd4f 2006.183.08:10:32.74$ifd4f/lo= 2006.183.08:10:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:10:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:10:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:10:32.74$ifd4f/patch= 2006.183.08:10:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:10:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:10:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:10:32.74$4f8m12a/"form=m,16.000,1:2 2006.183.08:10:32.74$4f8m12a/"tpicd 2006.183.08:10:32.74$4f8m12a/echo=off 2006.183.08:10:32.74$4f8m12a/xlog=off 2006.183.08:10:32.74:!2006.183.08:11:00 2006.183.08:10:41.14#trakl#Source acquired 2006.183.08:10:42.14#flagr#flagr/antenna,acquired 2006.183.08:11:00.01:preob 2006.183.08:11:01.14/onsource/TRACKING 2006.183.08:11:01.15:!2006.183.08:11:10 2006.183.08:11:10.01:data_valid=on 2006.183.08:11:10.02:midob 2006.183.08:11:11.14/onsource/TRACKING 2006.183.08:11:11.15/wx/28.34,996.5,85 2006.183.08:11:11.23/cable/+6.4510E-03 2006.183.08:11:12.32/va/01,08,usb,yes,29,31 2006.183.08:11:12.32/va/02,07,usb,yes,30,31 2006.183.08:11:12.32/va/03,06,usb,yes,31,32 2006.183.08:11:12.32/va/04,07,usb,yes,31,33 2006.183.08:11:12.32/va/05,07,usb,yes,32,34 2006.183.08:11:12.32/va/06,06,usb,yes,31,31 2006.183.08:11:12.32/va/07,06,usb,yes,32,31 2006.183.08:11:12.32/va/08,07,usb,yes,30,30 2006.183.08:11:12.55/valo/01,532.99,yes,locked 2006.183.08:11:12.55/valo/02,572.99,yes,locked 2006.183.08:11:12.55/valo/03,672.99,yes,locked 2006.183.08:11:12.55/valo/04,832.99,yes,locked 2006.183.08:11:12.55/valo/05,652.99,yes,locked 2006.183.08:11:12.55/valo/06,772.99,yes,locked 2006.183.08:11:12.55/valo/07,832.99,yes,locked 2006.183.08:11:12.55/valo/08,852.99,yes,locked 2006.183.08:11:13.64/vb/01,04,usb,yes,29,28 2006.183.08:11:13.64/vb/02,04,usb,yes,31,33 2006.183.08:11:13.64/vb/03,04,usb,yes,28,31 2006.183.08:11:13.64/vb/04,04,usb,yes,28,29 2006.183.08:11:13.64/vb/05,04,usb,yes,27,31 2006.183.08:11:13.64/vb/06,04,usb,yes,28,31 2006.183.08:11:13.64/vb/07,04,usb,yes,30,30 2006.183.08:11:13.64/vb/08,04,usb,yes,28,31 2006.183.08:11:13.87/vblo/01,632.99,yes,locked 2006.183.08:11:13.87/vblo/02,640.99,yes,locked 2006.183.08:11:13.87/vblo/03,656.99,yes,locked 2006.183.08:11:13.87/vblo/04,712.99,yes,locked 2006.183.08:11:13.87/vblo/05,744.99,yes,locked 2006.183.08:11:13.87/vblo/06,752.99,yes,locked 2006.183.08:11:13.87/vblo/07,734.99,yes,locked 2006.183.08:11:13.87/vblo/08,744.99,yes,locked 2006.183.08:11:14.02/vabw/8 2006.183.08:11:14.17/vbbw/8 2006.183.08:11:14.28/xfe/off,on,14.2 2006.183.08:11:14.66/ifatt/23,28,28,28 2006.183.08:11:15.07/fmout-gps/S +3.33E-07 2006.183.08:11:15.12:!2006.183.08:12:10 2006.183.08:12:10.01:data_valid=off 2006.183.08:12:10.02:postob 2006.183.08:12:10.16/cable/+6.4518E-03 2006.183.08:12:10.17/wx/28.34,996.6,86 2006.183.08:12:11.07/fmout-gps/S +3.35E-07 2006.183.08:12:11.08:scan_name=183-0813,k06183,60 2006.183.08:12:11.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.183.08:12:12.14#flagr#flagr/antenna,new-source 2006.183.08:12:12.15:checkk5 2006.183.08:12:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:12:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:12:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:12:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:12:14.02/chk_obsdata//k5ts1/T1830811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:12:14.39/chk_obsdata//k5ts2/T1830811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:12:14.76/chk_obsdata//k5ts3/T1830811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:12:15.13/chk_obsdata//k5ts4/T1830811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:12:15.86/k5log//k5ts1_log_newline 2006.183.08:12:16.55/k5log//k5ts2_log_newline 2006.183.08:12:17.24/k5log//k5ts3_log_newline 2006.183.08:12:17.93/k5log//k5ts4_log_newline 2006.183.08:12:17.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:12:17.95:4f8m12a=2 2006.183.08:12:17.95$4f8m12a/echo=on 2006.183.08:12:17.95$4f8m12a/pcalon 2006.183.08:12:17.95$pcalon/"no phase cal control is implemented here 2006.183.08:12:17.95$4f8m12a/"tpicd=stop 2006.183.08:12:17.95$4f8m12a/vc4f8 2006.183.08:12:17.95$vc4f8/valo=1,532.99 2006.183.08:12:17.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.08:12:17.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.08:12:17.96#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:17.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:17.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:17.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:17.96#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:12:17.96#ibcon#first serial, iclass 24, count 0 2006.183.08:12:17.96#ibcon#enter sib2, iclass 24, count 0 2006.183.08:12:17.96#ibcon#flushed, iclass 24, count 0 2006.183.08:12:17.96#ibcon#about to write, iclass 24, count 0 2006.183.08:12:17.96#ibcon#wrote, iclass 24, count 0 2006.183.08:12:17.96#ibcon#about to read 3, iclass 24, count 0 2006.183.08:12:18.00#ibcon#read 3, iclass 24, count 0 2006.183.08:12:18.00#ibcon#about to read 4, iclass 24, count 0 2006.183.08:12:18.00#ibcon#read 4, iclass 24, count 0 2006.183.08:12:18.00#ibcon#about to read 5, iclass 24, count 0 2006.183.08:12:18.00#ibcon#read 5, iclass 24, count 0 2006.183.08:12:18.00#ibcon#about to read 6, iclass 24, count 0 2006.183.08:12:18.00#ibcon#read 6, iclass 24, count 0 2006.183.08:12:18.00#ibcon#end of sib2, iclass 24, count 0 2006.183.08:12:18.00#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:12:18.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:12:18.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:12:18.00#ibcon#*before write, iclass 24, count 0 2006.183.08:12:18.00#ibcon#enter sib2, iclass 24, count 0 2006.183.08:12:18.00#ibcon#flushed, iclass 24, count 0 2006.183.08:12:18.00#ibcon#about to write, iclass 24, count 0 2006.183.08:12:18.00#ibcon#wrote, iclass 24, count 0 2006.183.08:12:18.00#ibcon#about to read 3, iclass 24, count 0 2006.183.08:12:18.04#ibcon#read 3, iclass 24, count 0 2006.183.08:12:18.04#ibcon#about to read 4, iclass 24, count 0 2006.183.08:12:18.04#ibcon#read 4, iclass 24, count 0 2006.183.08:12:18.04#ibcon#about to read 5, iclass 24, count 0 2006.183.08:12:18.04#ibcon#read 5, iclass 24, count 0 2006.183.08:12:18.04#ibcon#about to read 6, iclass 24, count 0 2006.183.08:12:18.04#ibcon#read 6, iclass 24, count 0 2006.183.08:12:18.04#ibcon#end of sib2, iclass 24, count 0 2006.183.08:12:18.04#ibcon#*after write, iclass 24, count 0 2006.183.08:12:18.04#ibcon#*before return 0, iclass 24, count 0 2006.183.08:12:18.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:18.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:18.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:12:18.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:12:18.04$vc4f8/va=1,8 2006.183.08:12:18.04#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.08:12:18.04#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.08:12:18.04#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:18.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:18.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:18.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:18.04#ibcon#enter wrdev, iclass 26, count 2 2006.183.08:12:18.04#ibcon#first serial, iclass 26, count 2 2006.183.08:12:18.04#ibcon#enter sib2, iclass 26, count 2 2006.183.08:12:18.04#ibcon#flushed, iclass 26, count 2 2006.183.08:12:18.04#ibcon#about to write, iclass 26, count 2 2006.183.08:12:18.04#ibcon#wrote, iclass 26, count 2 2006.183.08:12:18.04#ibcon#about to read 3, iclass 26, count 2 2006.183.08:12:18.07#ibcon#read 3, iclass 26, count 2 2006.183.08:12:18.07#ibcon#about to read 4, iclass 26, count 2 2006.183.08:12:18.07#ibcon#read 4, iclass 26, count 2 2006.183.08:12:18.07#ibcon#about to read 5, iclass 26, count 2 2006.183.08:12:18.07#ibcon#read 5, iclass 26, count 2 2006.183.08:12:18.07#ibcon#about to read 6, iclass 26, count 2 2006.183.08:12:18.07#ibcon#read 6, iclass 26, count 2 2006.183.08:12:18.07#ibcon#end of sib2, iclass 26, count 2 2006.183.08:12:18.07#ibcon#*mode == 0, iclass 26, count 2 2006.183.08:12:18.07#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.08:12:18.07#ibcon#[25=AT01-08\r\n] 2006.183.08:12:18.07#ibcon#*before write, iclass 26, count 2 2006.183.08:12:18.07#ibcon#enter sib2, iclass 26, count 2 2006.183.08:12:18.07#ibcon#flushed, iclass 26, count 2 2006.183.08:12:18.07#ibcon#about to write, iclass 26, count 2 2006.183.08:12:18.07#ibcon#wrote, iclass 26, count 2 2006.183.08:12:18.07#ibcon#about to read 3, iclass 26, count 2 2006.183.08:12:18.10#ibcon#read 3, iclass 26, count 2 2006.183.08:12:18.10#ibcon#about to read 4, iclass 26, count 2 2006.183.08:12:18.10#ibcon#read 4, iclass 26, count 2 2006.183.08:12:18.10#ibcon#about to read 5, iclass 26, count 2 2006.183.08:12:18.10#ibcon#read 5, iclass 26, count 2 2006.183.08:12:18.10#ibcon#about to read 6, iclass 26, count 2 2006.183.08:12:18.10#ibcon#read 6, iclass 26, count 2 2006.183.08:12:18.10#ibcon#end of sib2, iclass 26, count 2 2006.183.08:12:18.10#ibcon#*after write, iclass 26, count 2 2006.183.08:12:18.10#ibcon#*before return 0, iclass 26, count 2 2006.183.08:12:18.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:18.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:18.10#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.08:12:18.10#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:18.10#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:18.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:18.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:18.21#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:12:18.21#ibcon#first serial, iclass 26, count 0 2006.183.08:12:18.21#ibcon#enter sib2, iclass 26, count 0 2006.183.08:12:18.21#ibcon#flushed, iclass 26, count 0 2006.183.08:12:18.21#ibcon#about to write, iclass 26, count 0 2006.183.08:12:18.21#ibcon#wrote, iclass 26, count 0 2006.183.08:12:18.21#ibcon#about to read 3, iclass 26, count 0 2006.183.08:12:18.23#ibcon#read 3, iclass 26, count 0 2006.183.08:12:18.23#ibcon#about to read 4, iclass 26, count 0 2006.183.08:12:18.23#ibcon#read 4, iclass 26, count 0 2006.183.08:12:18.23#ibcon#about to read 5, iclass 26, count 0 2006.183.08:12:18.23#ibcon#read 5, iclass 26, count 0 2006.183.08:12:18.23#ibcon#about to read 6, iclass 26, count 0 2006.183.08:12:18.23#ibcon#read 6, iclass 26, count 0 2006.183.08:12:18.23#ibcon#end of sib2, iclass 26, count 0 2006.183.08:12:18.23#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:12:18.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:12:18.23#ibcon#[25=USB\r\n] 2006.183.08:12:18.23#ibcon#*before write, iclass 26, count 0 2006.183.08:12:18.23#ibcon#enter sib2, iclass 26, count 0 2006.183.08:12:18.23#ibcon#flushed, iclass 26, count 0 2006.183.08:12:18.23#ibcon#about to write, iclass 26, count 0 2006.183.08:12:18.23#ibcon#wrote, iclass 26, count 0 2006.183.08:12:18.23#ibcon#about to read 3, iclass 26, count 0 2006.183.08:12:18.26#ibcon#read 3, iclass 26, count 0 2006.183.08:12:18.26#ibcon#about to read 4, iclass 26, count 0 2006.183.08:12:18.26#ibcon#read 4, iclass 26, count 0 2006.183.08:12:18.26#ibcon#about to read 5, iclass 26, count 0 2006.183.08:12:18.26#ibcon#read 5, iclass 26, count 0 2006.183.08:12:18.26#ibcon#about to read 6, iclass 26, count 0 2006.183.08:12:18.26#ibcon#read 6, iclass 26, count 0 2006.183.08:12:18.26#ibcon#end of sib2, iclass 26, count 0 2006.183.08:12:18.26#ibcon#*after write, iclass 26, count 0 2006.183.08:12:18.26#ibcon#*before return 0, iclass 26, count 0 2006.183.08:12:18.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:18.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:18.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:12:18.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:12:18.26$vc4f8/valo=2,572.99 2006.183.08:12:18.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:12:18.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:12:18.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:18.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:18.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:18.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:18.26#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:12:18.26#ibcon#first serial, iclass 28, count 0 2006.183.08:12:18.26#ibcon#enter sib2, iclass 28, count 0 2006.183.08:12:18.26#ibcon#flushed, iclass 28, count 0 2006.183.08:12:18.26#ibcon#about to write, iclass 28, count 0 2006.183.08:12:18.26#ibcon#wrote, iclass 28, count 0 2006.183.08:12:18.26#ibcon#about to read 3, iclass 28, count 0 2006.183.08:12:18.29#ibcon#read 3, iclass 28, count 0 2006.183.08:12:18.29#ibcon#about to read 4, iclass 28, count 0 2006.183.08:12:18.29#ibcon#read 4, iclass 28, count 0 2006.183.08:12:18.29#ibcon#about to read 5, iclass 28, count 0 2006.183.08:12:18.29#ibcon#read 5, iclass 28, count 0 2006.183.08:12:18.29#ibcon#about to read 6, iclass 28, count 0 2006.183.08:12:18.29#ibcon#read 6, iclass 28, count 0 2006.183.08:12:18.29#ibcon#end of sib2, iclass 28, count 0 2006.183.08:12:18.29#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:12:18.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:12:18.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:12:18.29#ibcon#*before write, iclass 28, count 0 2006.183.08:12:18.29#ibcon#enter sib2, iclass 28, count 0 2006.183.08:12:18.29#ibcon#flushed, iclass 28, count 0 2006.183.08:12:18.29#ibcon#about to write, iclass 28, count 0 2006.183.08:12:18.29#ibcon#wrote, iclass 28, count 0 2006.183.08:12:18.29#ibcon#about to read 3, iclass 28, count 0 2006.183.08:12:18.33#ibcon#read 3, iclass 28, count 0 2006.183.08:12:18.33#ibcon#about to read 4, iclass 28, count 0 2006.183.08:12:18.33#ibcon#read 4, iclass 28, count 0 2006.183.08:12:18.33#ibcon#about to read 5, iclass 28, count 0 2006.183.08:12:18.33#ibcon#read 5, iclass 28, count 0 2006.183.08:12:18.33#ibcon#about to read 6, iclass 28, count 0 2006.183.08:12:18.33#ibcon#read 6, iclass 28, count 0 2006.183.08:12:18.33#ibcon#end of sib2, iclass 28, count 0 2006.183.08:12:18.33#ibcon#*after write, iclass 28, count 0 2006.183.08:12:18.33#ibcon#*before return 0, iclass 28, count 0 2006.183.08:12:18.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:18.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:18.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:12:18.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:12:18.33$vc4f8/va=2,7 2006.183.08:12:18.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.08:12:18.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.08:12:18.33#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:18.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:18.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:18.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:18.39#ibcon#enter wrdev, iclass 30, count 2 2006.183.08:12:18.39#ibcon#first serial, iclass 30, count 2 2006.183.08:12:18.39#ibcon#enter sib2, iclass 30, count 2 2006.183.08:12:18.39#ibcon#flushed, iclass 30, count 2 2006.183.08:12:18.39#ibcon#about to write, iclass 30, count 2 2006.183.08:12:18.39#ibcon#wrote, iclass 30, count 2 2006.183.08:12:18.39#ibcon#about to read 3, iclass 30, count 2 2006.183.08:12:18.40#ibcon#read 3, iclass 30, count 2 2006.183.08:12:18.40#ibcon#about to read 4, iclass 30, count 2 2006.183.08:12:18.40#ibcon#read 4, iclass 30, count 2 2006.183.08:12:18.40#ibcon#about to read 5, iclass 30, count 2 2006.183.08:12:18.40#ibcon#read 5, iclass 30, count 2 2006.183.08:12:18.40#ibcon#about to read 6, iclass 30, count 2 2006.183.08:12:18.40#ibcon#read 6, iclass 30, count 2 2006.183.08:12:18.40#ibcon#end of sib2, iclass 30, count 2 2006.183.08:12:18.40#ibcon#*mode == 0, iclass 30, count 2 2006.183.08:12:18.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.08:12:18.40#ibcon#[25=AT02-07\r\n] 2006.183.08:12:18.40#ibcon#*before write, iclass 30, count 2 2006.183.08:12:18.40#ibcon#enter sib2, iclass 30, count 2 2006.183.08:12:18.40#ibcon#flushed, iclass 30, count 2 2006.183.08:12:18.40#ibcon#about to write, iclass 30, count 2 2006.183.08:12:18.40#ibcon#wrote, iclass 30, count 2 2006.183.08:12:18.40#ibcon#about to read 3, iclass 30, count 2 2006.183.08:12:18.43#ibcon#read 3, iclass 30, count 2 2006.183.08:12:18.43#ibcon#about to read 4, iclass 30, count 2 2006.183.08:12:18.43#ibcon#read 4, iclass 30, count 2 2006.183.08:12:18.43#ibcon#about to read 5, iclass 30, count 2 2006.183.08:12:18.43#ibcon#read 5, iclass 30, count 2 2006.183.08:12:18.43#ibcon#about to read 6, iclass 30, count 2 2006.183.08:12:18.43#ibcon#read 6, iclass 30, count 2 2006.183.08:12:18.43#ibcon#end of sib2, iclass 30, count 2 2006.183.08:12:18.43#ibcon#*after write, iclass 30, count 2 2006.183.08:12:18.43#ibcon#*before return 0, iclass 30, count 2 2006.183.08:12:18.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:18.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:18.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.08:12:18.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:18.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:18.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:18.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:18.55#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:12:18.55#ibcon#first serial, iclass 30, count 0 2006.183.08:12:18.55#ibcon#enter sib2, iclass 30, count 0 2006.183.08:12:18.55#ibcon#flushed, iclass 30, count 0 2006.183.08:12:18.55#ibcon#about to write, iclass 30, count 0 2006.183.08:12:18.55#ibcon#wrote, iclass 30, count 0 2006.183.08:12:18.55#ibcon#about to read 3, iclass 30, count 0 2006.183.08:12:18.57#ibcon#read 3, iclass 30, count 0 2006.183.08:12:18.57#ibcon#about to read 4, iclass 30, count 0 2006.183.08:12:18.57#ibcon#read 4, iclass 30, count 0 2006.183.08:12:18.57#ibcon#about to read 5, iclass 30, count 0 2006.183.08:12:18.57#ibcon#read 5, iclass 30, count 0 2006.183.08:12:18.57#ibcon#about to read 6, iclass 30, count 0 2006.183.08:12:18.57#ibcon#read 6, iclass 30, count 0 2006.183.08:12:18.57#ibcon#end of sib2, iclass 30, count 0 2006.183.08:12:18.57#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:12:18.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:12:18.57#ibcon#[25=USB\r\n] 2006.183.08:12:18.57#ibcon#*before write, iclass 30, count 0 2006.183.08:12:18.57#ibcon#enter sib2, iclass 30, count 0 2006.183.08:12:18.57#ibcon#flushed, iclass 30, count 0 2006.183.08:12:18.57#ibcon#about to write, iclass 30, count 0 2006.183.08:12:18.57#ibcon#wrote, iclass 30, count 0 2006.183.08:12:18.57#ibcon#about to read 3, iclass 30, count 0 2006.183.08:12:18.60#ibcon#read 3, iclass 30, count 0 2006.183.08:12:18.60#ibcon#about to read 4, iclass 30, count 0 2006.183.08:12:18.60#ibcon#read 4, iclass 30, count 0 2006.183.08:12:18.60#ibcon#about to read 5, iclass 30, count 0 2006.183.08:12:18.60#ibcon#read 5, iclass 30, count 0 2006.183.08:12:18.60#ibcon#about to read 6, iclass 30, count 0 2006.183.08:12:18.60#ibcon#read 6, iclass 30, count 0 2006.183.08:12:18.60#ibcon#end of sib2, iclass 30, count 0 2006.183.08:12:18.60#ibcon#*after write, iclass 30, count 0 2006.183.08:12:18.60#ibcon#*before return 0, iclass 30, count 0 2006.183.08:12:18.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:18.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:18.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:12:18.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:12:18.60$vc4f8/valo=3,672.99 2006.183.08:12:18.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.08:12:18.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.08:12:18.60#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:18.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:18.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:18.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:18.60#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:12:18.60#ibcon#first serial, iclass 32, count 0 2006.183.08:12:18.60#ibcon#enter sib2, iclass 32, count 0 2006.183.08:12:18.60#ibcon#flushed, iclass 32, count 0 2006.183.08:12:18.60#ibcon#about to write, iclass 32, count 0 2006.183.08:12:18.60#ibcon#wrote, iclass 32, count 0 2006.183.08:12:18.60#ibcon#about to read 3, iclass 32, count 0 2006.183.08:12:18.63#ibcon#read 3, iclass 32, count 0 2006.183.08:12:18.63#ibcon#about to read 4, iclass 32, count 0 2006.183.08:12:18.63#ibcon#read 4, iclass 32, count 0 2006.183.08:12:18.63#ibcon#about to read 5, iclass 32, count 0 2006.183.08:12:18.63#ibcon#read 5, iclass 32, count 0 2006.183.08:12:18.63#ibcon#about to read 6, iclass 32, count 0 2006.183.08:12:18.63#ibcon#read 6, iclass 32, count 0 2006.183.08:12:18.63#ibcon#end of sib2, iclass 32, count 0 2006.183.08:12:18.63#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:12:18.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:12:18.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:12:18.63#ibcon#*before write, iclass 32, count 0 2006.183.08:12:18.63#ibcon#enter sib2, iclass 32, count 0 2006.183.08:12:18.63#ibcon#flushed, iclass 32, count 0 2006.183.08:12:18.63#ibcon#about to write, iclass 32, count 0 2006.183.08:12:18.63#ibcon#wrote, iclass 32, count 0 2006.183.08:12:18.63#ibcon#about to read 3, iclass 32, count 0 2006.183.08:12:18.67#ibcon#read 3, iclass 32, count 0 2006.183.08:12:18.67#ibcon#about to read 4, iclass 32, count 0 2006.183.08:12:18.67#ibcon#read 4, iclass 32, count 0 2006.183.08:12:18.67#ibcon#about to read 5, iclass 32, count 0 2006.183.08:12:18.67#ibcon#read 5, iclass 32, count 0 2006.183.08:12:18.67#ibcon#about to read 6, iclass 32, count 0 2006.183.08:12:18.67#ibcon#read 6, iclass 32, count 0 2006.183.08:12:18.67#ibcon#end of sib2, iclass 32, count 0 2006.183.08:12:18.67#ibcon#*after write, iclass 32, count 0 2006.183.08:12:18.67#ibcon#*before return 0, iclass 32, count 0 2006.183.08:12:18.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:18.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:18.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:12:18.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:12:18.67$vc4f8/va=3,6 2006.183.08:12:18.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.08:12:18.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.08:12:18.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:18.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:18.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:18.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:18.73#ibcon#enter wrdev, iclass 34, count 2 2006.183.08:12:18.73#ibcon#first serial, iclass 34, count 2 2006.183.08:12:18.73#ibcon#enter sib2, iclass 34, count 2 2006.183.08:12:18.73#ibcon#flushed, iclass 34, count 2 2006.183.08:12:18.73#ibcon#about to write, iclass 34, count 2 2006.183.08:12:18.73#ibcon#wrote, iclass 34, count 2 2006.183.08:12:18.73#ibcon#about to read 3, iclass 34, count 2 2006.183.08:12:18.74#ibcon#read 3, iclass 34, count 2 2006.183.08:12:18.74#ibcon#about to read 4, iclass 34, count 2 2006.183.08:12:18.74#ibcon#read 4, iclass 34, count 2 2006.183.08:12:18.74#ibcon#about to read 5, iclass 34, count 2 2006.183.08:12:18.74#ibcon#read 5, iclass 34, count 2 2006.183.08:12:18.74#ibcon#about to read 6, iclass 34, count 2 2006.183.08:12:18.74#ibcon#read 6, iclass 34, count 2 2006.183.08:12:18.74#ibcon#end of sib2, iclass 34, count 2 2006.183.08:12:18.74#ibcon#*mode == 0, iclass 34, count 2 2006.183.08:12:18.74#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.08:12:18.74#ibcon#[25=AT03-06\r\n] 2006.183.08:12:18.74#ibcon#*before write, iclass 34, count 2 2006.183.08:12:18.74#ibcon#enter sib2, iclass 34, count 2 2006.183.08:12:18.74#ibcon#flushed, iclass 34, count 2 2006.183.08:12:18.74#ibcon#about to write, iclass 34, count 2 2006.183.08:12:18.74#ibcon#wrote, iclass 34, count 2 2006.183.08:12:18.74#ibcon#about to read 3, iclass 34, count 2 2006.183.08:12:18.77#ibcon#read 3, iclass 34, count 2 2006.183.08:12:18.77#ibcon#about to read 4, iclass 34, count 2 2006.183.08:12:18.77#ibcon#read 4, iclass 34, count 2 2006.183.08:12:18.77#ibcon#about to read 5, iclass 34, count 2 2006.183.08:12:18.77#ibcon#read 5, iclass 34, count 2 2006.183.08:12:18.77#ibcon#about to read 6, iclass 34, count 2 2006.183.08:12:18.77#ibcon#read 6, iclass 34, count 2 2006.183.08:12:18.77#ibcon#end of sib2, iclass 34, count 2 2006.183.08:12:18.77#ibcon#*after write, iclass 34, count 2 2006.183.08:12:18.77#ibcon#*before return 0, iclass 34, count 2 2006.183.08:12:18.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:18.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:18.77#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.08:12:18.77#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:18.77#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:18.89#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:18.89#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:18.89#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:12:18.89#ibcon#first serial, iclass 34, count 0 2006.183.08:12:18.89#ibcon#enter sib2, iclass 34, count 0 2006.183.08:12:18.89#ibcon#flushed, iclass 34, count 0 2006.183.08:12:18.89#ibcon#about to write, iclass 34, count 0 2006.183.08:12:18.89#ibcon#wrote, iclass 34, count 0 2006.183.08:12:18.89#ibcon#about to read 3, iclass 34, count 0 2006.183.08:12:18.91#ibcon#read 3, iclass 34, count 0 2006.183.08:12:18.91#ibcon#about to read 4, iclass 34, count 0 2006.183.08:12:18.91#ibcon#read 4, iclass 34, count 0 2006.183.08:12:18.91#ibcon#about to read 5, iclass 34, count 0 2006.183.08:12:18.91#ibcon#read 5, iclass 34, count 0 2006.183.08:12:18.91#ibcon#about to read 6, iclass 34, count 0 2006.183.08:12:18.91#ibcon#read 6, iclass 34, count 0 2006.183.08:12:18.91#ibcon#end of sib2, iclass 34, count 0 2006.183.08:12:18.91#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:12:18.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:12:18.91#ibcon#[25=USB\r\n] 2006.183.08:12:18.91#ibcon#*before write, iclass 34, count 0 2006.183.08:12:18.91#ibcon#enter sib2, iclass 34, count 0 2006.183.08:12:18.91#ibcon#flushed, iclass 34, count 0 2006.183.08:12:18.91#ibcon#about to write, iclass 34, count 0 2006.183.08:12:18.91#ibcon#wrote, iclass 34, count 0 2006.183.08:12:18.91#ibcon#about to read 3, iclass 34, count 0 2006.183.08:12:18.94#ibcon#read 3, iclass 34, count 0 2006.183.08:12:18.94#ibcon#about to read 4, iclass 34, count 0 2006.183.08:12:18.94#ibcon#read 4, iclass 34, count 0 2006.183.08:12:18.94#ibcon#about to read 5, iclass 34, count 0 2006.183.08:12:18.94#ibcon#read 5, iclass 34, count 0 2006.183.08:12:18.94#ibcon#about to read 6, iclass 34, count 0 2006.183.08:12:18.94#ibcon#read 6, iclass 34, count 0 2006.183.08:12:18.94#ibcon#end of sib2, iclass 34, count 0 2006.183.08:12:18.94#ibcon#*after write, iclass 34, count 0 2006.183.08:12:18.94#ibcon#*before return 0, iclass 34, count 0 2006.183.08:12:18.94#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:18.94#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:18.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:12:18.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:12:18.94$vc4f8/valo=4,832.99 2006.183.08:12:18.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.08:12:18.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.08:12:18.94#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:18.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:18.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:18.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:18.94#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:12:18.94#ibcon#first serial, iclass 36, count 0 2006.183.08:12:18.94#ibcon#enter sib2, iclass 36, count 0 2006.183.08:12:18.94#ibcon#flushed, iclass 36, count 0 2006.183.08:12:18.94#ibcon#about to write, iclass 36, count 0 2006.183.08:12:18.94#ibcon#wrote, iclass 36, count 0 2006.183.08:12:18.94#ibcon#about to read 3, iclass 36, count 0 2006.183.08:12:18.97#ibcon#read 3, iclass 36, count 0 2006.183.08:12:18.97#ibcon#about to read 4, iclass 36, count 0 2006.183.08:12:18.97#ibcon#read 4, iclass 36, count 0 2006.183.08:12:18.97#ibcon#about to read 5, iclass 36, count 0 2006.183.08:12:18.97#ibcon#read 5, iclass 36, count 0 2006.183.08:12:18.97#ibcon#about to read 6, iclass 36, count 0 2006.183.08:12:18.97#ibcon#read 6, iclass 36, count 0 2006.183.08:12:18.97#ibcon#end of sib2, iclass 36, count 0 2006.183.08:12:18.97#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:12:18.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:12:18.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:12:18.97#ibcon#*before write, iclass 36, count 0 2006.183.08:12:18.97#ibcon#enter sib2, iclass 36, count 0 2006.183.08:12:18.97#ibcon#flushed, iclass 36, count 0 2006.183.08:12:18.97#ibcon#about to write, iclass 36, count 0 2006.183.08:12:18.97#ibcon#wrote, iclass 36, count 0 2006.183.08:12:18.97#ibcon#about to read 3, iclass 36, count 0 2006.183.08:12:19.01#ibcon#read 3, iclass 36, count 0 2006.183.08:12:19.01#ibcon#about to read 4, iclass 36, count 0 2006.183.08:12:19.01#ibcon#read 4, iclass 36, count 0 2006.183.08:12:19.01#ibcon#about to read 5, iclass 36, count 0 2006.183.08:12:19.01#ibcon#read 5, iclass 36, count 0 2006.183.08:12:19.01#ibcon#about to read 6, iclass 36, count 0 2006.183.08:12:19.01#ibcon#read 6, iclass 36, count 0 2006.183.08:12:19.01#ibcon#end of sib2, iclass 36, count 0 2006.183.08:12:19.01#ibcon#*after write, iclass 36, count 0 2006.183.08:12:19.01#ibcon#*before return 0, iclass 36, count 0 2006.183.08:12:19.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:19.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:19.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:12:19.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:12:19.01$vc4f8/va=4,7 2006.183.08:12:19.01#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.08:12:19.01#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.08:12:19.01#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:19.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:19.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:19.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:19.06#ibcon#enter wrdev, iclass 38, count 2 2006.183.08:12:19.06#ibcon#first serial, iclass 38, count 2 2006.183.08:12:19.06#ibcon#enter sib2, iclass 38, count 2 2006.183.08:12:19.06#ibcon#flushed, iclass 38, count 2 2006.183.08:12:19.06#ibcon#about to write, iclass 38, count 2 2006.183.08:12:19.06#ibcon#wrote, iclass 38, count 2 2006.183.08:12:19.06#ibcon#about to read 3, iclass 38, count 2 2006.183.08:12:19.08#ibcon#read 3, iclass 38, count 2 2006.183.08:12:19.08#ibcon#about to read 4, iclass 38, count 2 2006.183.08:12:19.08#ibcon#read 4, iclass 38, count 2 2006.183.08:12:19.08#ibcon#about to read 5, iclass 38, count 2 2006.183.08:12:19.08#ibcon#read 5, iclass 38, count 2 2006.183.08:12:19.08#ibcon#about to read 6, iclass 38, count 2 2006.183.08:12:19.08#ibcon#read 6, iclass 38, count 2 2006.183.08:12:19.08#ibcon#end of sib2, iclass 38, count 2 2006.183.08:12:19.08#ibcon#*mode == 0, iclass 38, count 2 2006.183.08:12:19.08#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.08:12:19.08#ibcon#[25=AT04-07\r\n] 2006.183.08:12:19.08#ibcon#*before write, iclass 38, count 2 2006.183.08:12:19.08#ibcon#enter sib2, iclass 38, count 2 2006.183.08:12:19.08#ibcon#flushed, iclass 38, count 2 2006.183.08:12:19.08#ibcon#about to write, iclass 38, count 2 2006.183.08:12:19.08#ibcon#wrote, iclass 38, count 2 2006.183.08:12:19.08#ibcon#about to read 3, iclass 38, count 2 2006.183.08:12:19.11#ibcon#read 3, iclass 38, count 2 2006.183.08:12:19.11#ibcon#about to read 4, iclass 38, count 2 2006.183.08:12:19.11#ibcon#read 4, iclass 38, count 2 2006.183.08:12:19.11#ibcon#about to read 5, iclass 38, count 2 2006.183.08:12:19.11#ibcon#read 5, iclass 38, count 2 2006.183.08:12:19.11#ibcon#about to read 6, iclass 38, count 2 2006.183.08:12:19.11#ibcon#read 6, iclass 38, count 2 2006.183.08:12:19.11#ibcon#end of sib2, iclass 38, count 2 2006.183.08:12:19.11#ibcon#*after write, iclass 38, count 2 2006.183.08:12:19.11#ibcon#*before return 0, iclass 38, count 2 2006.183.08:12:19.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:19.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:19.11#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.08:12:19.11#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:19.11#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:19.23#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:19.23#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:19.23#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:12:19.23#ibcon#first serial, iclass 38, count 0 2006.183.08:12:19.23#ibcon#enter sib2, iclass 38, count 0 2006.183.08:12:19.23#ibcon#flushed, iclass 38, count 0 2006.183.08:12:19.23#ibcon#about to write, iclass 38, count 0 2006.183.08:12:19.23#ibcon#wrote, iclass 38, count 0 2006.183.08:12:19.23#ibcon#about to read 3, iclass 38, count 0 2006.183.08:12:19.25#ibcon#read 3, iclass 38, count 0 2006.183.08:12:19.25#ibcon#about to read 4, iclass 38, count 0 2006.183.08:12:19.25#ibcon#read 4, iclass 38, count 0 2006.183.08:12:19.25#ibcon#about to read 5, iclass 38, count 0 2006.183.08:12:19.25#ibcon#read 5, iclass 38, count 0 2006.183.08:12:19.25#ibcon#about to read 6, iclass 38, count 0 2006.183.08:12:19.25#ibcon#read 6, iclass 38, count 0 2006.183.08:12:19.25#ibcon#end of sib2, iclass 38, count 0 2006.183.08:12:19.25#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:12:19.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:12:19.25#ibcon#[25=USB\r\n] 2006.183.08:12:19.25#ibcon#*before write, iclass 38, count 0 2006.183.08:12:19.25#ibcon#enter sib2, iclass 38, count 0 2006.183.08:12:19.25#ibcon#flushed, iclass 38, count 0 2006.183.08:12:19.25#ibcon#about to write, iclass 38, count 0 2006.183.08:12:19.25#ibcon#wrote, iclass 38, count 0 2006.183.08:12:19.25#ibcon#about to read 3, iclass 38, count 0 2006.183.08:12:19.28#ibcon#read 3, iclass 38, count 0 2006.183.08:12:19.28#ibcon#about to read 4, iclass 38, count 0 2006.183.08:12:19.28#ibcon#read 4, iclass 38, count 0 2006.183.08:12:19.28#ibcon#about to read 5, iclass 38, count 0 2006.183.08:12:19.28#ibcon#read 5, iclass 38, count 0 2006.183.08:12:19.28#ibcon#about to read 6, iclass 38, count 0 2006.183.08:12:19.28#ibcon#read 6, iclass 38, count 0 2006.183.08:12:19.28#ibcon#end of sib2, iclass 38, count 0 2006.183.08:12:19.28#ibcon#*after write, iclass 38, count 0 2006.183.08:12:19.28#ibcon#*before return 0, iclass 38, count 0 2006.183.08:12:19.28#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:19.28#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:19.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:12:19.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:12:19.28$vc4f8/valo=5,652.99 2006.183.08:12:19.28#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.08:12:19.28#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.08:12:19.28#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:19.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:19.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:19.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:19.28#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:12:19.28#ibcon#first serial, iclass 40, count 0 2006.183.08:12:19.28#ibcon#enter sib2, iclass 40, count 0 2006.183.08:12:19.28#ibcon#flushed, iclass 40, count 0 2006.183.08:12:19.28#ibcon#about to write, iclass 40, count 0 2006.183.08:12:19.28#ibcon#wrote, iclass 40, count 0 2006.183.08:12:19.28#ibcon#about to read 3, iclass 40, count 0 2006.183.08:12:19.30#ibcon#read 3, iclass 40, count 0 2006.183.08:12:19.30#ibcon#about to read 4, iclass 40, count 0 2006.183.08:12:19.30#ibcon#read 4, iclass 40, count 0 2006.183.08:12:19.30#ibcon#about to read 5, iclass 40, count 0 2006.183.08:12:19.30#ibcon#read 5, iclass 40, count 0 2006.183.08:12:19.30#ibcon#about to read 6, iclass 40, count 0 2006.183.08:12:19.30#ibcon#read 6, iclass 40, count 0 2006.183.08:12:19.30#ibcon#end of sib2, iclass 40, count 0 2006.183.08:12:19.30#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:12:19.30#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:12:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:12:19.30#ibcon#*before write, iclass 40, count 0 2006.183.08:12:19.30#ibcon#enter sib2, iclass 40, count 0 2006.183.08:12:19.30#ibcon#flushed, iclass 40, count 0 2006.183.08:12:19.30#ibcon#about to write, iclass 40, count 0 2006.183.08:12:19.30#ibcon#wrote, iclass 40, count 0 2006.183.08:12:19.30#ibcon#about to read 3, iclass 40, count 0 2006.183.08:12:19.34#ibcon#read 3, iclass 40, count 0 2006.183.08:12:19.34#ibcon#about to read 4, iclass 40, count 0 2006.183.08:12:19.34#ibcon#read 4, iclass 40, count 0 2006.183.08:12:19.34#ibcon#about to read 5, iclass 40, count 0 2006.183.08:12:19.34#ibcon#read 5, iclass 40, count 0 2006.183.08:12:19.34#ibcon#about to read 6, iclass 40, count 0 2006.183.08:12:19.34#ibcon#read 6, iclass 40, count 0 2006.183.08:12:19.34#ibcon#end of sib2, iclass 40, count 0 2006.183.08:12:19.34#ibcon#*after write, iclass 40, count 0 2006.183.08:12:19.34#ibcon#*before return 0, iclass 40, count 0 2006.183.08:12:19.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:19.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:19.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:12:19.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:12:19.34$vc4f8/va=5,7 2006.183.08:12:19.34#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.08:12:19.34#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.08:12:19.34#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:19.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:19.40#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:19.40#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:19.40#ibcon#enter wrdev, iclass 4, count 2 2006.183.08:12:19.40#ibcon#first serial, iclass 4, count 2 2006.183.08:12:19.40#ibcon#enter sib2, iclass 4, count 2 2006.183.08:12:19.40#ibcon#flushed, iclass 4, count 2 2006.183.08:12:19.40#ibcon#about to write, iclass 4, count 2 2006.183.08:12:19.40#ibcon#wrote, iclass 4, count 2 2006.183.08:12:19.40#ibcon#about to read 3, iclass 4, count 2 2006.183.08:12:19.42#ibcon#read 3, iclass 4, count 2 2006.183.08:12:19.42#ibcon#about to read 4, iclass 4, count 2 2006.183.08:12:19.42#ibcon#read 4, iclass 4, count 2 2006.183.08:12:19.42#ibcon#about to read 5, iclass 4, count 2 2006.183.08:12:19.42#ibcon#read 5, iclass 4, count 2 2006.183.08:12:19.42#ibcon#about to read 6, iclass 4, count 2 2006.183.08:12:19.42#ibcon#read 6, iclass 4, count 2 2006.183.08:12:19.42#ibcon#end of sib2, iclass 4, count 2 2006.183.08:12:19.42#ibcon#*mode == 0, iclass 4, count 2 2006.183.08:12:19.42#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.08:12:19.42#ibcon#[25=AT05-07\r\n] 2006.183.08:12:19.42#ibcon#*before write, iclass 4, count 2 2006.183.08:12:19.42#ibcon#enter sib2, iclass 4, count 2 2006.183.08:12:19.42#ibcon#flushed, iclass 4, count 2 2006.183.08:12:19.42#ibcon#about to write, iclass 4, count 2 2006.183.08:12:19.42#ibcon#wrote, iclass 4, count 2 2006.183.08:12:19.42#ibcon#about to read 3, iclass 4, count 2 2006.183.08:12:19.45#ibcon#read 3, iclass 4, count 2 2006.183.08:12:19.45#ibcon#about to read 4, iclass 4, count 2 2006.183.08:12:19.45#ibcon#read 4, iclass 4, count 2 2006.183.08:12:19.45#ibcon#about to read 5, iclass 4, count 2 2006.183.08:12:19.45#ibcon#read 5, iclass 4, count 2 2006.183.08:12:19.45#ibcon#about to read 6, iclass 4, count 2 2006.183.08:12:19.45#ibcon#read 6, iclass 4, count 2 2006.183.08:12:19.45#ibcon#end of sib2, iclass 4, count 2 2006.183.08:12:19.45#ibcon#*after write, iclass 4, count 2 2006.183.08:12:19.45#ibcon#*before return 0, iclass 4, count 2 2006.183.08:12:19.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:19.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:19.45#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.08:12:19.45#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:19.45#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:19.57#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:19.57#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:19.57#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:12:19.57#ibcon#first serial, iclass 4, count 0 2006.183.08:12:19.57#ibcon#enter sib2, iclass 4, count 0 2006.183.08:12:19.57#ibcon#flushed, iclass 4, count 0 2006.183.08:12:19.57#ibcon#about to write, iclass 4, count 0 2006.183.08:12:19.57#ibcon#wrote, iclass 4, count 0 2006.183.08:12:19.57#ibcon#about to read 3, iclass 4, count 0 2006.183.08:12:19.59#ibcon#read 3, iclass 4, count 0 2006.183.08:12:19.59#ibcon#about to read 4, iclass 4, count 0 2006.183.08:12:19.59#ibcon#read 4, iclass 4, count 0 2006.183.08:12:19.59#ibcon#about to read 5, iclass 4, count 0 2006.183.08:12:19.59#ibcon#read 5, iclass 4, count 0 2006.183.08:12:19.59#ibcon#about to read 6, iclass 4, count 0 2006.183.08:12:19.59#ibcon#read 6, iclass 4, count 0 2006.183.08:12:19.59#ibcon#end of sib2, iclass 4, count 0 2006.183.08:12:19.59#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:12:19.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:12:19.59#ibcon#[25=USB\r\n] 2006.183.08:12:19.59#ibcon#*before write, iclass 4, count 0 2006.183.08:12:19.59#ibcon#enter sib2, iclass 4, count 0 2006.183.08:12:19.59#ibcon#flushed, iclass 4, count 0 2006.183.08:12:19.59#ibcon#about to write, iclass 4, count 0 2006.183.08:12:19.59#ibcon#wrote, iclass 4, count 0 2006.183.08:12:19.59#ibcon#about to read 3, iclass 4, count 0 2006.183.08:12:19.62#ibcon#read 3, iclass 4, count 0 2006.183.08:12:19.62#ibcon#about to read 4, iclass 4, count 0 2006.183.08:12:19.62#ibcon#read 4, iclass 4, count 0 2006.183.08:12:19.62#ibcon#about to read 5, iclass 4, count 0 2006.183.08:12:19.62#ibcon#read 5, iclass 4, count 0 2006.183.08:12:19.62#ibcon#about to read 6, iclass 4, count 0 2006.183.08:12:19.62#ibcon#read 6, iclass 4, count 0 2006.183.08:12:19.62#ibcon#end of sib2, iclass 4, count 0 2006.183.08:12:19.62#ibcon#*after write, iclass 4, count 0 2006.183.08:12:19.62#ibcon#*before return 0, iclass 4, count 0 2006.183.08:12:19.62#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:19.62#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:19.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:12:19.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:12:19.62$vc4f8/valo=6,772.99 2006.183.08:12:19.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.08:12:19.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.08:12:19.62#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:19.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:19.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:19.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:19.62#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:12:19.62#ibcon#first serial, iclass 6, count 0 2006.183.08:12:19.62#ibcon#enter sib2, iclass 6, count 0 2006.183.08:12:19.62#ibcon#flushed, iclass 6, count 0 2006.183.08:12:19.62#ibcon#about to write, iclass 6, count 0 2006.183.08:12:19.62#ibcon#wrote, iclass 6, count 0 2006.183.08:12:19.62#ibcon#about to read 3, iclass 6, count 0 2006.183.08:12:19.65#ibcon#read 3, iclass 6, count 0 2006.183.08:12:19.65#ibcon#about to read 4, iclass 6, count 0 2006.183.08:12:19.65#ibcon#read 4, iclass 6, count 0 2006.183.08:12:19.65#ibcon#about to read 5, iclass 6, count 0 2006.183.08:12:19.65#ibcon#read 5, iclass 6, count 0 2006.183.08:12:19.65#ibcon#about to read 6, iclass 6, count 0 2006.183.08:12:19.65#ibcon#read 6, iclass 6, count 0 2006.183.08:12:19.65#ibcon#end of sib2, iclass 6, count 0 2006.183.08:12:19.65#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:12:19.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:12:19.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:12:19.65#ibcon#*before write, iclass 6, count 0 2006.183.08:12:19.65#ibcon#enter sib2, iclass 6, count 0 2006.183.08:12:19.65#ibcon#flushed, iclass 6, count 0 2006.183.08:12:19.65#ibcon#about to write, iclass 6, count 0 2006.183.08:12:19.65#ibcon#wrote, iclass 6, count 0 2006.183.08:12:19.65#ibcon#about to read 3, iclass 6, count 0 2006.183.08:12:19.69#ibcon#read 3, iclass 6, count 0 2006.183.08:12:19.69#ibcon#about to read 4, iclass 6, count 0 2006.183.08:12:19.69#ibcon#read 4, iclass 6, count 0 2006.183.08:12:19.69#ibcon#about to read 5, iclass 6, count 0 2006.183.08:12:19.69#ibcon#read 5, iclass 6, count 0 2006.183.08:12:19.69#ibcon#about to read 6, iclass 6, count 0 2006.183.08:12:19.69#ibcon#read 6, iclass 6, count 0 2006.183.08:12:19.69#ibcon#end of sib2, iclass 6, count 0 2006.183.08:12:19.69#ibcon#*after write, iclass 6, count 0 2006.183.08:12:19.69#ibcon#*before return 0, iclass 6, count 0 2006.183.08:12:19.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:19.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:19.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:12:19.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:12:19.69$vc4f8/va=6,6 2006.183.08:12:19.69#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.08:12:19.69#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.08:12:19.69#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:19.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:19.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:19.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:19.75#ibcon#enter wrdev, iclass 10, count 2 2006.183.08:12:19.75#ibcon#first serial, iclass 10, count 2 2006.183.08:12:19.75#ibcon#enter sib2, iclass 10, count 2 2006.183.08:12:19.75#ibcon#flushed, iclass 10, count 2 2006.183.08:12:19.75#ibcon#about to write, iclass 10, count 2 2006.183.08:12:19.75#ibcon#wrote, iclass 10, count 2 2006.183.08:12:19.75#ibcon#about to read 3, iclass 10, count 2 2006.183.08:12:19.76#ibcon#read 3, iclass 10, count 2 2006.183.08:12:19.76#ibcon#about to read 4, iclass 10, count 2 2006.183.08:12:19.76#ibcon#read 4, iclass 10, count 2 2006.183.08:12:19.76#ibcon#about to read 5, iclass 10, count 2 2006.183.08:12:19.76#ibcon#read 5, iclass 10, count 2 2006.183.08:12:19.76#ibcon#about to read 6, iclass 10, count 2 2006.183.08:12:19.76#ibcon#read 6, iclass 10, count 2 2006.183.08:12:19.76#ibcon#end of sib2, iclass 10, count 2 2006.183.08:12:19.76#ibcon#*mode == 0, iclass 10, count 2 2006.183.08:12:19.76#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.08:12:19.76#ibcon#[25=AT06-06\r\n] 2006.183.08:12:19.76#ibcon#*before write, iclass 10, count 2 2006.183.08:12:19.76#ibcon#enter sib2, iclass 10, count 2 2006.183.08:12:19.76#ibcon#flushed, iclass 10, count 2 2006.183.08:12:19.76#ibcon#about to write, iclass 10, count 2 2006.183.08:12:19.76#ibcon#wrote, iclass 10, count 2 2006.183.08:12:19.76#ibcon#about to read 3, iclass 10, count 2 2006.183.08:12:19.79#ibcon#read 3, iclass 10, count 2 2006.183.08:12:19.79#ibcon#about to read 4, iclass 10, count 2 2006.183.08:12:19.79#ibcon#read 4, iclass 10, count 2 2006.183.08:12:19.79#ibcon#about to read 5, iclass 10, count 2 2006.183.08:12:19.79#ibcon#read 5, iclass 10, count 2 2006.183.08:12:19.79#ibcon#about to read 6, iclass 10, count 2 2006.183.08:12:19.79#ibcon#read 6, iclass 10, count 2 2006.183.08:12:19.79#ibcon#end of sib2, iclass 10, count 2 2006.183.08:12:19.79#ibcon#*after write, iclass 10, count 2 2006.183.08:12:19.79#ibcon#*before return 0, iclass 10, count 2 2006.183.08:12:19.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:19.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:19.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.08:12:19.79#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:19.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:19.86#abcon#<5=/10 1.6 4.4 28.34 86 996.6\r\n> 2006.183.08:12:19.88#abcon#{5=INTERFACE CLEAR} 2006.183.08:12:19.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:19.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:19.91#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:12:19.91#ibcon#first serial, iclass 10, count 0 2006.183.08:12:19.91#ibcon#enter sib2, iclass 10, count 0 2006.183.08:12:19.91#ibcon#flushed, iclass 10, count 0 2006.183.08:12:19.91#ibcon#about to write, iclass 10, count 0 2006.183.08:12:19.91#ibcon#wrote, iclass 10, count 0 2006.183.08:12:19.91#ibcon#about to read 3, iclass 10, count 0 2006.183.08:12:19.93#ibcon#read 3, iclass 10, count 0 2006.183.08:12:19.93#ibcon#about to read 4, iclass 10, count 0 2006.183.08:12:19.93#ibcon#read 4, iclass 10, count 0 2006.183.08:12:19.93#ibcon#about to read 5, iclass 10, count 0 2006.183.08:12:19.93#ibcon#read 5, iclass 10, count 0 2006.183.08:12:19.93#ibcon#about to read 6, iclass 10, count 0 2006.183.08:12:19.93#ibcon#read 6, iclass 10, count 0 2006.183.08:12:19.93#ibcon#end of sib2, iclass 10, count 0 2006.183.08:12:19.93#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:12:19.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:12:19.93#ibcon#[25=USB\r\n] 2006.183.08:12:19.93#ibcon#*before write, iclass 10, count 0 2006.183.08:12:19.93#ibcon#enter sib2, iclass 10, count 0 2006.183.08:12:19.93#ibcon#flushed, iclass 10, count 0 2006.183.08:12:19.93#ibcon#about to write, iclass 10, count 0 2006.183.08:12:19.93#ibcon#wrote, iclass 10, count 0 2006.183.08:12:19.93#ibcon#about to read 3, iclass 10, count 0 2006.183.08:12:19.94#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:12:19.96#ibcon#read 3, iclass 10, count 0 2006.183.08:12:19.96#ibcon#about to read 4, iclass 10, count 0 2006.183.08:12:19.96#ibcon#read 4, iclass 10, count 0 2006.183.08:12:19.96#ibcon#about to read 5, iclass 10, count 0 2006.183.08:12:19.96#ibcon#read 5, iclass 10, count 0 2006.183.08:12:19.96#ibcon#about to read 6, iclass 10, count 0 2006.183.08:12:19.96#ibcon#read 6, iclass 10, count 0 2006.183.08:12:19.96#ibcon#end of sib2, iclass 10, count 0 2006.183.08:12:19.96#ibcon#*after write, iclass 10, count 0 2006.183.08:12:19.96#ibcon#*before return 0, iclass 10, count 0 2006.183.08:12:19.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:19.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:19.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:12:19.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:12:19.96$vc4f8/valo=7,832.99 2006.183.08:12:19.96#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.08:12:19.96#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.08:12:19.96#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:19.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:12:19.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:12:19.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:12:19.96#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:12:19.96#ibcon#first serial, iclass 16, count 0 2006.183.08:12:19.96#ibcon#enter sib2, iclass 16, count 0 2006.183.08:12:19.96#ibcon#flushed, iclass 16, count 0 2006.183.08:12:19.96#ibcon#about to write, iclass 16, count 0 2006.183.08:12:19.96#ibcon#wrote, iclass 16, count 0 2006.183.08:12:19.96#ibcon#about to read 3, iclass 16, count 0 2006.183.08:12:19.98#ibcon#read 3, iclass 16, count 0 2006.183.08:12:19.98#ibcon#about to read 4, iclass 16, count 0 2006.183.08:12:19.98#ibcon#read 4, iclass 16, count 0 2006.183.08:12:19.98#ibcon#about to read 5, iclass 16, count 0 2006.183.08:12:19.98#ibcon#read 5, iclass 16, count 0 2006.183.08:12:19.98#ibcon#about to read 6, iclass 16, count 0 2006.183.08:12:19.98#ibcon#read 6, iclass 16, count 0 2006.183.08:12:19.98#ibcon#end of sib2, iclass 16, count 0 2006.183.08:12:19.98#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:12:19.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:12:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:12:19.98#ibcon#*before write, iclass 16, count 0 2006.183.08:12:19.98#ibcon#enter sib2, iclass 16, count 0 2006.183.08:12:19.98#ibcon#flushed, iclass 16, count 0 2006.183.08:12:19.98#ibcon#about to write, iclass 16, count 0 2006.183.08:12:19.98#ibcon#wrote, iclass 16, count 0 2006.183.08:12:19.98#ibcon#about to read 3, iclass 16, count 0 2006.183.08:12:20.02#ibcon#read 3, iclass 16, count 0 2006.183.08:12:20.02#ibcon#about to read 4, iclass 16, count 0 2006.183.08:12:20.02#ibcon#read 4, iclass 16, count 0 2006.183.08:12:20.02#ibcon#about to read 5, iclass 16, count 0 2006.183.08:12:20.02#ibcon#read 5, iclass 16, count 0 2006.183.08:12:20.02#ibcon#about to read 6, iclass 16, count 0 2006.183.08:12:20.02#ibcon#read 6, iclass 16, count 0 2006.183.08:12:20.02#ibcon#end of sib2, iclass 16, count 0 2006.183.08:12:20.02#ibcon#*after write, iclass 16, count 0 2006.183.08:12:20.02#ibcon#*before return 0, iclass 16, count 0 2006.183.08:12:20.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:12:20.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:12:20.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:12:20.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:12:20.02$vc4f8/va=7,6 2006.183.08:12:20.02#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.08:12:20.02#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.08:12:20.02#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:20.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:12:20.08#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:12:20.08#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:12:20.08#ibcon#enter wrdev, iclass 18, count 2 2006.183.08:12:20.08#ibcon#first serial, iclass 18, count 2 2006.183.08:12:20.08#ibcon#enter sib2, iclass 18, count 2 2006.183.08:12:20.08#ibcon#flushed, iclass 18, count 2 2006.183.08:12:20.08#ibcon#about to write, iclass 18, count 2 2006.183.08:12:20.08#ibcon#wrote, iclass 18, count 2 2006.183.08:12:20.08#ibcon#about to read 3, iclass 18, count 2 2006.183.08:12:20.10#ibcon#read 3, iclass 18, count 2 2006.183.08:12:20.10#ibcon#about to read 4, iclass 18, count 2 2006.183.08:12:20.10#ibcon#read 4, iclass 18, count 2 2006.183.08:12:20.10#ibcon#about to read 5, iclass 18, count 2 2006.183.08:12:20.10#ibcon#read 5, iclass 18, count 2 2006.183.08:12:20.10#ibcon#about to read 6, iclass 18, count 2 2006.183.08:12:20.10#ibcon#read 6, iclass 18, count 2 2006.183.08:12:20.10#ibcon#end of sib2, iclass 18, count 2 2006.183.08:12:20.10#ibcon#*mode == 0, iclass 18, count 2 2006.183.08:12:20.10#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.08:12:20.10#ibcon#[25=AT07-06\r\n] 2006.183.08:12:20.10#ibcon#*before write, iclass 18, count 2 2006.183.08:12:20.10#ibcon#enter sib2, iclass 18, count 2 2006.183.08:12:20.10#ibcon#flushed, iclass 18, count 2 2006.183.08:12:20.10#ibcon#about to write, iclass 18, count 2 2006.183.08:12:20.10#ibcon#wrote, iclass 18, count 2 2006.183.08:12:20.10#ibcon#about to read 3, iclass 18, count 2 2006.183.08:12:20.13#ibcon#read 3, iclass 18, count 2 2006.183.08:12:20.13#ibcon#about to read 4, iclass 18, count 2 2006.183.08:12:20.13#ibcon#read 4, iclass 18, count 2 2006.183.08:12:20.13#ibcon#about to read 5, iclass 18, count 2 2006.183.08:12:20.13#ibcon#read 5, iclass 18, count 2 2006.183.08:12:20.13#ibcon#about to read 6, iclass 18, count 2 2006.183.08:12:20.13#ibcon#read 6, iclass 18, count 2 2006.183.08:12:20.13#ibcon#end of sib2, iclass 18, count 2 2006.183.08:12:20.13#ibcon#*after write, iclass 18, count 2 2006.183.08:12:20.13#ibcon#*before return 0, iclass 18, count 2 2006.183.08:12:20.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:12:20.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:12:20.13#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.08:12:20.13#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:20.13#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:12:20.25#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:12:20.25#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:12:20.25#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:12:20.25#ibcon#first serial, iclass 18, count 0 2006.183.08:12:20.25#ibcon#enter sib2, iclass 18, count 0 2006.183.08:12:20.25#ibcon#flushed, iclass 18, count 0 2006.183.08:12:20.25#ibcon#about to write, iclass 18, count 0 2006.183.08:12:20.25#ibcon#wrote, iclass 18, count 0 2006.183.08:12:20.25#ibcon#about to read 3, iclass 18, count 0 2006.183.08:12:20.27#ibcon#read 3, iclass 18, count 0 2006.183.08:12:20.27#ibcon#about to read 4, iclass 18, count 0 2006.183.08:12:20.27#ibcon#read 4, iclass 18, count 0 2006.183.08:12:20.27#ibcon#about to read 5, iclass 18, count 0 2006.183.08:12:20.27#ibcon#read 5, iclass 18, count 0 2006.183.08:12:20.27#ibcon#about to read 6, iclass 18, count 0 2006.183.08:12:20.27#ibcon#read 6, iclass 18, count 0 2006.183.08:12:20.27#ibcon#end of sib2, iclass 18, count 0 2006.183.08:12:20.27#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:12:20.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:12:20.27#ibcon#[25=USB\r\n] 2006.183.08:12:20.27#ibcon#*before write, iclass 18, count 0 2006.183.08:12:20.27#ibcon#enter sib2, iclass 18, count 0 2006.183.08:12:20.27#ibcon#flushed, iclass 18, count 0 2006.183.08:12:20.27#ibcon#about to write, iclass 18, count 0 2006.183.08:12:20.27#ibcon#wrote, iclass 18, count 0 2006.183.08:12:20.27#ibcon#about to read 3, iclass 18, count 0 2006.183.08:12:20.30#ibcon#read 3, iclass 18, count 0 2006.183.08:12:20.30#ibcon#about to read 4, iclass 18, count 0 2006.183.08:12:20.30#ibcon#read 4, iclass 18, count 0 2006.183.08:12:20.30#ibcon#about to read 5, iclass 18, count 0 2006.183.08:12:20.30#ibcon#read 5, iclass 18, count 0 2006.183.08:12:20.30#ibcon#about to read 6, iclass 18, count 0 2006.183.08:12:20.30#ibcon#read 6, iclass 18, count 0 2006.183.08:12:20.30#ibcon#end of sib2, iclass 18, count 0 2006.183.08:12:20.30#ibcon#*after write, iclass 18, count 0 2006.183.08:12:20.30#ibcon#*before return 0, iclass 18, count 0 2006.183.08:12:20.30#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:12:20.30#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:12:20.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:12:20.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:12:20.30$vc4f8/valo=8,852.99 2006.183.08:12:20.30#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.08:12:20.30#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.08:12:20.30#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:20.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:12:20.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:12:20.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:12:20.30#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:12:20.30#ibcon#first serial, iclass 20, count 0 2006.183.08:12:20.30#ibcon#enter sib2, iclass 20, count 0 2006.183.08:12:20.30#ibcon#flushed, iclass 20, count 0 2006.183.08:12:20.30#ibcon#about to write, iclass 20, count 0 2006.183.08:12:20.30#ibcon#wrote, iclass 20, count 0 2006.183.08:12:20.30#ibcon#about to read 3, iclass 20, count 0 2006.183.08:12:20.32#ibcon#read 3, iclass 20, count 0 2006.183.08:12:20.32#ibcon#about to read 4, iclass 20, count 0 2006.183.08:12:20.32#ibcon#read 4, iclass 20, count 0 2006.183.08:12:20.32#ibcon#about to read 5, iclass 20, count 0 2006.183.08:12:20.32#ibcon#read 5, iclass 20, count 0 2006.183.08:12:20.32#ibcon#about to read 6, iclass 20, count 0 2006.183.08:12:20.32#ibcon#read 6, iclass 20, count 0 2006.183.08:12:20.32#ibcon#end of sib2, iclass 20, count 0 2006.183.08:12:20.32#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:12:20.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:12:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:12:20.32#ibcon#*before write, iclass 20, count 0 2006.183.08:12:20.32#ibcon#enter sib2, iclass 20, count 0 2006.183.08:12:20.32#ibcon#flushed, iclass 20, count 0 2006.183.08:12:20.32#ibcon#about to write, iclass 20, count 0 2006.183.08:12:20.32#ibcon#wrote, iclass 20, count 0 2006.183.08:12:20.32#ibcon#about to read 3, iclass 20, count 0 2006.183.08:12:20.36#ibcon#read 3, iclass 20, count 0 2006.183.08:12:20.36#ibcon#about to read 4, iclass 20, count 0 2006.183.08:12:20.36#ibcon#read 4, iclass 20, count 0 2006.183.08:12:20.36#ibcon#about to read 5, iclass 20, count 0 2006.183.08:12:20.36#ibcon#read 5, iclass 20, count 0 2006.183.08:12:20.36#ibcon#about to read 6, iclass 20, count 0 2006.183.08:12:20.36#ibcon#read 6, iclass 20, count 0 2006.183.08:12:20.36#ibcon#end of sib2, iclass 20, count 0 2006.183.08:12:20.36#ibcon#*after write, iclass 20, count 0 2006.183.08:12:20.36#ibcon#*before return 0, iclass 20, count 0 2006.183.08:12:20.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:12:20.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:12:20.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:12:20.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:12:20.36$vc4f8/va=8,7 2006.183.08:12:20.36#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.08:12:20.36#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.08:12:20.36#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:20.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:12:20.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:12:20.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:12:20.43#ibcon#enter wrdev, iclass 22, count 2 2006.183.08:12:20.43#ibcon#first serial, iclass 22, count 2 2006.183.08:12:20.43#ibcon#enter sib2, iclass 22, count 2 2006.183.08:12:20.43#ibcon#flushed, iclass 22, count 2 2006.183.08:12:20.43#ibcon#about to write, iclass 22, count 2 2006.183.08:12:20.43#ibcon#wrote, iclass 22, count 2 2006.183.08:12:20.43#ibcon#about to read 3, iclass 22, count 2 2006.183.08:12:20.44#ibcon#read 3, iclass 22, count 2 2006.183.08:12:20.44#ibcon#about to read 4, iclass 22, count 2 2006.183.08:12:20.44#ibcon#read 4, iclass 22, count 2 2006.183.08:12:20.44#ibcon#about to read 5, iclass 22, count 2 2006.183.08:12:20.44#ibcon#read 5, iclass 22, count 2 2006.183.08:12:20.44#ibcon#about to read 6, iclass 22, count 2 2006.183.08:12:20.44#ibcon#read 6, iclass 22, count 2 2006.183.08:12:20.44#ibcon#end of sib2, iclass 22, count 2 2006.183.08:12:20.44#ibcon#*mode == 0, iclass 22, count 2 2006.183.08:12:20.44#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.08:12:20.44#ibcon#[25=AT08-07\r\n] 2006.183.08:12:20.44#ibcon#*before write, iclass 22, count 2 2006.183.08:12:20.44#ibcon#enter sib2, iclass 22, count 2 2006.183.08:12:20.44#ibcon#flushed, iclass 22, count 2 2006.183.08:12:20.44#ibcon#about to write, iclass 22, count 2 2006.183.08:12:20.44#ibcon#wrote, iclass 22, count 2 2006.183.08:12:20.44#ibcon#about to read 3, iclass 22, count 2 2006.183.08:12:20.47#ibcon#read 3, iclass 22, count 2 2006.183.08:12:20.47#ibcon#about to read 4, iclass 22, count 2 2006.183.08:12:20.47#ibcon#read 4, iclass 22, count 2 2006.183.08:12:20.47#ibcon#about to read 5, iclass 22, count 2 2006.183.08:12:20.47#ibcon#read 5, iclass 22, count 2 2006.183.08:12:20.47#ibcon#about to read 6, iclass 22, count 2 2006.183.08:12:20.47#ibcon#read 6, iclass 22, count 2 2006.183.08:12:20.47#ibcon#end of sib2, iclass 22, count 2 2006.183.08:12:20.47#ibcon#*after write, iclass 22, count 2 2006.183.08:12:20.47#ibcon#*before return 0, iclass 22, count 2 2006.183.08:12:20.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:12:20.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:12:20.47#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.08:12:20.47#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:20.47#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:12:20.59#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:12:20.59#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:12:20.59#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:12:20.59#ibcon#first serial, iclass 22, count 0 2006.183.08:12:20.59#ibcon#enter sib2, iclass 22, count 0 2006.183.08:12:20.59#ibcon#flushed, iclass 22, count 0 2006.183.08:12:20.59#ibcon#about to write, iclass 22, count 0 2006.183.08:12:20.59#ibcon#wrote, iclass 22, count 0 2006.183.08:12:20.59#ibcon#about to read 3, iclass 22, count 0 2006.183.08:12:20.61#ibcon#read 3, iclass 22, count 0 2006.183.08:12:20.61#ibcon#about to read 4, iclass 22, count 0 2006.183.08:12:20.61#ibcon#read 4, iclass 22, count 0 2006.183.08:12:20.61#ibcon#about to read 5, iclass 22, count 0 2006.183.08:12:20.61#ibcon#read 5, iclass 22, count 0 2006.183.08:12:20.61#ibcon#about to read 6, iclass 22, count 0 2006.183.08:12:20.61#ibcon#read 6, iclass 22, count 0 2006.183.08:12:20.61#ibcon#end of sib2, iclass 22, count 0 2006.183.08:12:20.61#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:12:20.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:12:20.61#ibcon#[25=USB\r\n] 2006.183.08:12:20.61#ibcon#*before write, iclass 22, count 0 2006.183.08:12:20.61#ibcon#enter sib2, iclass 22, count 0 2006.183.08:12:20.61#ibcon#flushed, iclass 22, count 0 2006.183.08:12:20.61#ibcon#about to write, iclass 22, count 0 2006.183.08:12:20.61#ibcon#wrote, iclass 22, count 0 2006.183.08:12:20.61#ibcon#about to read 3, iclass 22, count 0 2006.183.08:12:20.64#ibcon#read 3, iclass 22, count 0 2006.183.08:12:20.64#ibcon#about to read 4, iclass 22, count 0 2006.183.08:12:20.64#ibcon#read 4, iclass 22, count 0 2006.183.08:12:20.64#ibcon#about to read 5, iclass 22, count 0 2006.183.08:12:20.64#ibcon#read 5, iclass 22, count 0 2006.183.08:12:20.64#ibcon#about to read 6, iclass 22, count 0 2006.183.08:12:20.64#ibcon#read 6, iclass 22, count 0 2006.183.08:12:20.64#ibcon#end of sib2, iclass 22, count 0 2006.183.08:12:20.64#ibcon#*after write, iclass 22, count 0 2006.183.08:12:20.64#ibcon#*before return 0, iclass 22, count 0 2006.183.08:12:20.64#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:12:20.64#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:12:20.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:12:20.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:12:20.64$vc4f8/vblo=1,632.99 2006.183.08:12:20.64#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.08:12:20.64#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.08:12:20.64#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:20.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:20.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:20.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:20.64#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:12:20.64#ibcon#first serial, iclass 24, count 0 2006.183.08:12:20.64#ibcon#enter sib2, iclass 24, count 0 2006.183.08:12:20.64#ibcon#flushed, iclass 24, count 0 2006.183.08:12:20.64#ibcon#about to write, iclass 24, count 0 2006.183.08:12:20.64#ibcon#wrote, iclass 24, count 0 2006.183.08:12:20.64#ibcon#about to read 3, iclass 24, count 0 2006.183.08:12:20.67#ibcon#read 3, iclass 24, count 0 2006.183.08:12:20.67#ibcon#about to read 4, iclass 24, count 0 2006.183.08:12:20.67#ibcon#read 4, iclass 24, count 0 2006.183.08:12:20.67#ibcon#about to read 5, iclass 24, count 0 2006.183.08:12:20.67#ibcon#read 5, iclass 24, count 0 2006.183.08:12:20.67#ibcon#about to read 6, iclass 24, count 0 2006.183.08:12:20.67#ibcon#read 6, iclass 24, count 0 2006.183.08:12:20.67#ibcon#end of sib2, iclass 24, count 0 2006.183.08:12:20.67#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:12:20.67#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:12:20.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:12:20.67#ibcon#*before write, iclass 24, count 0 2006.183.08:12:20.67#ibcon#enter sib2, iclass 24, count 0 2006.183.08:12:20.67#ibcon#flushed, iclass 24, count 0 2006.183.08:12:20.67#ibcon#about to write, iclass 24, count 0 2006.183.08:12:20.67#ibcon#wrote, iclass 24, count 0 2006.183.08:12:20.67#ibcon#about to read 3, iclass 24, count 0 2006.183.08:12:20.71#ibcon#read 3, iclass 24, count 0 2006.183.08:12:20.71#ibcon#about to read 4, iclass 24, count 0 2006.183.08:12:20.71#ibcon#read 4, iclass 24, count 0 2006.183.08:12:20.71#ibcon#about to read 5, iclass 24, count 0 2006.183.08:12:20.71#ibcon#read 5, iclass 24, count 0 2006.183.08:12:20.71#ibcon#about to read 6, iclass 24, count 0 2006.183.08:12:20.71#ibcon#read 6, iclass 24, count 0 2006.183.08:12:20.71#ibcon#end of sib2, iclass 24, count 0 2006.183.08:12:20.71#ibcon#*after write, iclass 24, count 0 2006.183.08:12:20.71#ibcon#*before return 0, iclass 24, count 0 2006.183.08:12:20.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:20.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:12:20.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:12:20.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:12:20.71$vc4f8/vb=1,4 2006.183.08:12:20.71#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.08:12:20.71#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.08:12:20.71#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:20.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:20.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:20.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:20.71#ibcon#enter wrdev, iclass 26, count 2 2006.183.08:12:20.71#ibcon#first serial, iclass 26, count 2 2006.183.08:12:20.71#ibcon#enter sib2, iclass 26, count 2 2006.183.08:12:20.71#ibcon#flushed, iclass 26, count 2 2006.183.08:12:20.71#ibcon#about to write, iclass 26, count 2 2006.183.08:12:20.71#ibcon#wrote, iclass 26, count 2 2006.183.08:12:20.71#ibcon#about to read 3, iclass 26, count 2 2006.183.08:12:20.73#ibcon#read 3, iclass 26, count 2 2006.183.08:12:20.73#ibcon#about to read 4, iclass 26, count 2 2006.183.08:12:20.73#ibcon#read 4, iclass 26, count 2 2006.183.08:12:20.73#ibcon#about to read 5, iclass 26, count 2 2006.183.08:12:20.73#ibcon#read 5, iclass 26, count 2 2006.183.08:12:20.73#ibcon#about to read 6, iclass 26, count 2 2006.183.08:12:20.73#ibcon#read 6, iclass 26, count 2 2006.183.08:12:20.73#ibcon#end of sib2, iclass 26, count 2 2006.183.08:12:20.73#ibcon#*mode == 0, iclass 26, count 2 2006.183.08:12:20.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.08:12:20.73#ibcon#[27=AT01-04\r\n] 2006.183.08:12:20.73#ibcon#*before write, iclass 26, count 2 2006.183.08:12:20.73#ibcon#enter sib2, iclass 26, count 2 2006.183.08:12:20.73#ibcon#flushed, iclass 26, count 2 2006.183.08:12:20.73#ibcon#about to write, iclass 26, count 2 2006.183.08:12:20.73#ibcon#wrote, iclass 26, count 2 2006.183.08:12:20.73#ibcon#about to read 3, iclass 26, count 2 2006.183.08:12:20.76#ibcon#read 3, iclass 26, count 2 2006.183.08:12:20.76#ibcon#about to read 4, iclass 26, count 2 2006.183.08:12:20.76#ibcon#read 4, iclass 26, count 2 2006.183.08:12:20.76#ibcon#about to read 5, iclass 26, count 2 2006.183.08:12:20.76#ibcon#read 5, iclass 26, count 2 2006.183.08:12:20.76#ibcon#about to read 6, iclass 26, count 2 2006.183.08:12:20.76#ibcon#read 6, iclass 26, count 2 2006.183.08:12:20.76#ibcon#end of sib2, iclass 26, count 2 2006.183.08:12:20.76#ibcon#*after write, iclass 26, count 2 2006.183.08:12:20.76#ibcon#*before return 0, iclass 26, count 2 2006.183.08:12:20.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:20.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:12:20.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.08:12:20.76#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:20.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:20.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:20.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:20.88#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:12:20.88#ibcon#first serial, iclass 26, count 0 2006.183.08:12:20.88#ibcon#enter sib2, iclass 26, count 0 2006.183.08:12:20.88#ibcon#flushed, iclass 26, count 0 2006.183.08:12:20.88#ibcon#about to write, iclass 26, count 0 2006.183.08:12:20.88#ibcon#wrote, iclass 26, count 0 2006.183.08:12:20.88#ibcon#about to read 3, iclass 26, count 0 2006.183.08:12:20.90#ibcon#read 3, iclass 26, count 0 2006.183.08:12:20.90#ibcon#about to read 4, iclass 26, count 0 2006.183.08:12:20.90#ibcon#read 4, iclass 26, count 0 2006.183.08:12:20.90#ibcon#about to read 5, iclass 26, count 0 2006.183.08:12:20.90#ibcon#read 5, iclass 26, count 0 2006.183.08:12:20.90#ibcon#about to read 6, iclass 26, count 0 2006.183.08:12:20.90#ibcon#read 6, iclass 26, count 0 2006.183.08:12:20.90#ibcon#end of sib2, iclass 26, count 0 2006.183.08:12:20.90#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:12:20.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:12:20.90#ibcon#[27=USB\r\n] 2006.183.08:12:20.90#ibcon#*before write, iclass 26, count 0 2006.183.08:12:20.90#ibcon#enter sib2, iclass 26, count 0 2006.183.08:12:20.90#ibcon#flushed, iclass 26, count 0 2006.183.08:12:20.90#ibcon#about to write, iclass 26, count 0 2006.183.08:12:20.90#ibcon#wrote, iclass 26, count 0 2006.183.08:12:20.90#ibcon#about to read 3, iclass 26, count 0 2006.183.08:12:20.93#ibcon#read 3, iclass 26, count 0 2006.183.08:12:20.93#ibcon#about to read 4, iclass 26, count 0 2006.183.08:12:20.93#ibcon#read 4, iclass 26, count 0 2006.183.08:12:20.93#ibcon#about to read 5, iclass 26, count 0 2006.183.08:12:20.93#ibcon#read 5, iclass 26, count 0 2006.183.08:12:20.93#ibcon#about to read 6, iclass 26, count 0 2006.183.08:12:20.93#ibcon#read 6, iclass 26, count 0 2006.183.08:12:20.93#ibcon#end of sib2, iclass 26, count 0 2006.183.08:12:20.93#ibcon#*after write, iclass 26, count 0 2006.183.08:12:20.93#ibcon#*before return 0, iclass 26, count 0 2006.183.08:12:20.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:20.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:12:20.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:12:20.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:12:20.93$vc4f8/vblo=2,640.99 2006.183.08:12:20.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:12:20.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:12:20.93#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:20.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:20.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:20.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:20.93#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:12:20.93#ibcon#first serial, iclass 28, count 0 2006.183.08:12:20.93#ibcon#enter sib2, iclass 28, count 0 2006.183.08:12:20.93#ibcon#flushed, iclass 28, count 0 2006.183.08:12:20.93#ibcon#about to write, iclass 28, count 0 2006.183.08:12:20.93#ibcon#wrote, iclass 28, count 0 2006.183.08:12:20.93#ibcon#about to read 3, iclass 28, count 0 2006.183.08:12:20.95#ibcon#read 3, iclass 28, count 0 2006.183.08:12:20.95#ibcon#about to read 4, iclass 28, count 0 2006.183.08:12:20.95#ibcon#read 4, iclass 28, count 0 2006.183.08:12:20.95#ibcon#about to read 5, iclass 28, count 0 2006.183.08:12:20.95#ibcon#read 5, iclass 28, count 0 2006.183.08:12:20.95#ibcon#about to read 6, iclass 28, count 0 2006.183.08:12:20.95#ibcon#read 6, iclass 28, count 0 2006.183.08:12:20.95#ibcon#end of sib2, iclass 28, count 0 2006.183.08:12:20.95#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:12:20.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:12:20.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:12:20.95#ibcon#*before write, iclass 28, count 0 2006.183.08:12:20.95#ibcon#enter sib2, iclass 28, count 0 2006.183.08:12:20.95#ibcon#flushed, iclass 28, count 0 2006.183.08:12:20.95#ibcon#about to write, iclass 28, count 0 2006.183.08:12:20.95#ibcon#wrote, iclass 28, count 0 2006.183.08:12:20.95#ibcon#about to read 3, iclass 28, count 0 2006.183.08:12:20.99#ibcon#read 3, iclass 28, count 0 2006.183.08:12:20.99#ibcon#about to read 4, iclass 28, count 0 2006.183.08:12:20.99#ibcon#read 4, iclass 28, count 0 2006.183.08:12:20.99#ibcon#about to read 5, iclass 28, count 0 2006.183.08:12:20.99#ibcon#read 5, iclass 28, count 0 2006.183.08:12:20.99#ibcon#about to read 6, iclass 28, count 0 2006.183.08:12:20.99#ibcon#read 6, iclass 28, count 0 2006.183.08:12:20.99#ibcon#end of sib2, iclass 28, count 0 2006.183.08:12:20.99#ibcon#*after write, iclass 28, count 0 2006.183.08:12:20.99#ibcon#*before return 0, iclass 28, count 0 2006.183.08:12:20.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:20.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:12:20.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:12:20.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:12:20.99$vc4f8/vb=2,4 2006.183.08:12:20.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.08:12:20.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.08:12:20.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:20.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:21.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:21.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:21.05#ibcon#enter wrdev, iclass 30, count 2 2006.183.08:12:21.05#ibcon#first serial, iclass 30, count 2 2006.183.08:12:21.05#ibcon#enter sib2, iclass 30, count 2 2006.183.08:12:21.05#ibcon#flushed, iclass 30, count 2 2006.183.08:12:21.05#ibcon#about to write, iclass 30, count 2 2006.183.08:12:21.05#ibcon#wrote, iclass 30, count 2 2006.183.08:12:21.05#ibcon#about to read 3, iclass 30, count 2 2006.183.08:12:21.07#ibcon#read 3, iclass 30, count 2 2006.183.08:12:21.07#ibcon#about to read 4, iclass 30, count 2 2006.183.08:12:21.07#ibcon#read 4, iclass 30, count 2 2006.183.08:12:21.07#ibcon#about to read 5, iclass 30, count 2 2006.183.08:12:21.07#ibcon#read 5, iclass 30, count 2 2006.183.08:12:21.07#ibcon#about to read 6, iclass 30, count 2 2006.183.08:12:21.07#ibcon#read 6, iclass 30, count 2 2006.183.08:12:21.07#ibcon#end of sib2, iclass 30, count 2 2006.183.08:12:21.07#ibcon#*mode == 0, iclass 30, count 2 2006.183.08:12:21.07#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.08:12:21.07#ibcon#[27=AT02-04\r\n] 2006.183.08:12:21.07#ibcon#*before write, iclass 30, count 2 2006.183.08:12:21.07#ibcon#enter sib2, iclass 30, count 2 2006.183.08:12:21.07#ibcon#flushed, iclass 30, count 2 2006.183.08:12:21.07#ibcon#about to write, iclass 30, count 2 2006.183.08:12:21.07#ibcon#wrote, iclass 30, count 2 2006.183.08:12:21.07#ibcon#about to read 3, iclass 30, count 2 2006.183.08:12:21.10#ibcon#read 3, iclass 30, count 2 2006.183.08:12:21.10#ibcon#about to read 4, iclass 30, count 2 2006.183.08:12:21.10#ibcon#read 4, iclass 30, count 2 2006.183.08:12:21.10#ibcon#about to read 5, iclass 30, count 2 2006.183.08:12:21.10#ibcon#read 5, iclass 30, count 2 2006.183.08:12:21.10#ibcon#about to read 6, iclass 30, count 2 2006.183.08:12:21.10#ibcon#read 6, iclass 30, count 2 2006.183.08:12:21.10#ibcon#end of sib2, iclass 30, count 2 2006.183.08:12:21.10#ibcon#*after write, iclass 30, count 2 2006.183.08:12:21.10#ibcon#*before return 0, iclass 30, count 2 2006.183.08:12:21.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:21.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:12:21.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.08:12:21.10#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:21.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:21.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:21.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:21.22#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:12:21.22#ibcon#first serial, iclass 30, count 0 2006.183.08:12:21.22#ibcon#enter sib2, iclass 30, count 0 2006.183.08:12:21.22#ibcon#flushed, iclass 30, count 0 2006.183.08:12:21.22#ibcon#about to write, iclass 30, count 0 2006.183.08:12:21.22#ibcon#wrote, iclass 30, count 0 2006.183.08:12:21.22#ibcon#about to read 3, iclass 30, count 0 2006.183.08:12:21.24#ibcon#read 3, iclass 30, count 0 2006.183.08:12:21.24#ibcon#about to read 4, iclass 30, count 0 2006.183.08:12:21.24#ibcon#read 4, iclass 30, count 0 2006.183.08:12:21.24#ibcon#about to read 5, iclass 30, count 0 2006.183.08:12:21.24#ibcon#read 5, iclass 30, count 0 2006.183.08:12:21.24#ibcon#about to read 6, iclass 30, count 0 2006.183.08:12:21.24#ibcon#read 6, iclass 30, count 0 2006.183.08:12:21.24#ibcon#end of sib2, iclass 30, count 0 2006.183.08:12:21.24#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:12:21.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:12:21.24#ibcon#[27=USB\r\n] 2006.183.08:12:21.24#ibcon#*before write, iclass 30, count 0 2006.183.08:12:21.24#ibcon#enter sib2, iclass 30, count 0 2006.183.08:12:21.24#ibcon#flushed, iclass 30, count 0 2006.183.08:12:21.24#ibcon#about to write, iclass 30, count 0 2006.183.08:12:21.24#ibcon#wrote, iclass 30, count 0 2006.183.08:12:21.24#ibcon#about to read 3, iclass 30, count 0 2006.183.08:12:21.27#ibcon#read 3, iclass 30, count 0 2006.183.08:12:21.27#ibcon#about to read 4, iclass 30, count 0 2006.183.08:12:21.27#ibcon#read 4, iclass 30, count 0 2006.183.08:12:21.27#ibcon#about to read 5, iclass 30, count 0 2006.183.08:12:21.27#ibcon#read 5, iclass 30, count 0 2006.183.08:12:21.27#ibcon#about to read 6, iclass 30, count 0 2006.183.08:12:21.27#ibcon#read 6, iclass 30, count 0 2006.183.08:12:21.27#ibcon#end of sib2, iclass 30, count 0 2006.183.08:12:21.27#ibcon#*after write, iclass 30, count 0 2006.183.08:12:21.27#ibcon#*before return 0, iclass 30, count 0 2006.183.08:12:21.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:21.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:12:21.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:12:21.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:12:21.27$vc4f8/vblo=3,656.99 2006.183.08:12:21.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.08:12:21.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.08:12:21.27#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:21.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:21.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:21.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:21.27#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:12:21.27#ibcon#first serial, iclass 32, count 0 2006.183.08:12:21.27#ibcon#enter sib2, iclass 32, count 0 2006.183.08:12:21.27#ibcon#flushed, iclass 32, count 0 2006.183.08:12:21.27#ibcon#about to write, iclass 32, count 0 2006.183.08:12:21.27#ibcon#wrote, iclass 32, count 0 2006.183.08:12:21.27#ibcon#about to read 3, iclass 32, count 0 2006.183.08:12:21.29#ibcon#read 3, iclass 32, count 0 2006.183.08:12:21.29#ibcon#about to read 4, iclass 32, count 0 2006.183.08:12:21.29#ibcon#read 4, iclass 32, count 0 2006.183.08:12:21.29#ibcon#about to read 5, iclass 32, count 0 2006.183.08:12:21.29#ibcon#read 5, iclass 32, count 0 2006.183.08:12:21.29#ibcon#about to read 6, iclass 32, count 0 2006.183.08:12:21.29#ibcon#read 6, iclass 32, count 0 2006.183.08:12:21.29#ibcon#end of sib2, iclass 32, count 0 2006.183.08:12:21.29#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:12:21.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:12:21.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:12:21.29#ibcon#*before write, iclass 32, count 0 2006.183.08:12:21.29#ibcon#enter sib2, iclass 32, count 0 2006.183.08:12:21.29#ibcon#flushed, iclass 32, count 0 2006.183.08:12:21.29#ibcon#about to write, iclass 32, count 0 2006.183.08:12:21.29#ibcon#wrote, iclass 32, count 0 2006.183.08:12:21.29#ibcon#about to read 3, iclass 32, count 0 2006.183.08:12:21.33#ibcon#read 3, iclass 32, count 0 2006.183.08:12:21.33#ibcon#about to read 4, iclass 32, count 0 2006.183.08:12:21.33#ibcon#read 4, iclass 32, count 0 2006.183.08:12:21.33#ibcon#about to read 5, iclass 32, count 0 2006.183.08:12:21.33#ibcon#read 5, iclass 32, count 0 2006.183.08:12:21.33#ibcon#about to read 6, iclass 32, count 0 2006.183.08:12:21.33#ibcon#read 6, iclass 32, count 0 2006.183.08:12:21.33#ibcon#end of sib2, iclass 32, count 0 2006.183.08:12:21.33#ibcon#*after write, iclass 32, count 0 2006.183.08:12:21.33#ibcon#*before return 0, iclass 32, count 0 2006.183.08:12:21.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:21.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:12:21.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:12:21.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:12:21.33$vc4f8/vb=3,4 2006.183.08:12:21.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.08:12:21.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.08:12:21.33#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:21.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:21.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:21.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:21.39#ibcon#enter wrdev, iclass 34, count 2 2006.183.08:12:21.39#ibcon#first serial, iclass 34, count 2 2006.183.08:12:21.39#ibcon#enter sib2, iclass 34, count 2 2006.183.08:12:21.39#ibcon#flushed, iclass 34, count 2 2006.183.08:12:21.39#ibcon#about to write, iclass 34, count 2 2006.183.08:12:21.39#ibcon#wrote, iclass 34, count 2 2006.183.08:12:21.39#ibcon#about to read 3, iclass 34, count 2 2006.183.08:12:21.41#ibcon#read 3, iclass 34, count 2 2006.183.08:12:21.41#ibcon#about to read 4, iclass 34, count 2 2006.183.08:12:21.41#ibcon#read 4, iclass 34, count 2 2006.183.08:12:21.41#ibcon#about to read 5, iclass 34, count 2 2006.183.08:12:21.41#ibcon#read 5, iclass 34, count 2 2006.183.08:12:21.41#ibcon#about to read 6, iclass 34, count 2 2006.183.08:12:21.41#ibcon#read 6, iclass 34, count 2 2006.183.08:12:21.41#ibcon#end of sib2, iclass 34, count 2 2006.183.08:12:21.41#ibcon#*mode == 0, iclass 34, count 2 2006.183.08:12:21.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.08:12:21.41#ibcon#[27=AT03-04\r\n] 2006.183.08:12:21.41#ibcon#*before write, iclass 34, count 2 2006.183.08:12:21.41#ibcon#enter sib2, iclass 34, count 2 2006.183.08:12:21.41#ibcon#flushed, iclass 34, count 2 2006.183.08:12:21.41#ibcon#about to write, iclass 34, count 2 2006.183.08:12:21.41#ibcon#wrote, iclass 34, count 2 2006.183.08:12:21.41#ibcon#about to read 3, iclass 34, count 2 2006.183.08:12:21.44#ibcon#read 3, iclass 34, count 2 2006.183.08:12:21.44#ibcon#about to read 4, iclass 34, count 2 2006.183.08:12:21.44#ibcon#read 4, iclass 34, count 2 2006.183.08:12:21.44#ibcon#about to read 5, iclass 34, count 2 2006.183.08:12:21.44#ibcon#read 5, iclass 34, count 2 2006.183.08:12:21.44#ibcon#about to read 6, iclass 34, count 2 2006.183.08:12:21.44#ibcon#read 6, iclass 34, count 2 2006.183.08:12:21.44#ibcon#end of sib2, iclass 34, count 2 2006.183.08:12:21.44#ibcon#*after write, iclass 34, count 2 2006.183.08:12:21.44#ibcon#*before return 0, iclass 34, count 2 2006.183.08:12:21.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:21.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:12:21.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.08:12:21.44#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:21.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:21.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:21.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:21.56#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:12:21.56#ibcon#first serial, iclass 34, count 0 2006.183.08:12:21.56#ibcon#enter sib2, iclass 34, count 0 2006.183.08:12:21.56#ibcon#flushed, iclass 34, count 0 2006.183.08:12:21.56#ibcon#about to write, iclass 34, count 0 2006.183.08:12:21.56#ibcon#wrote, iclass 34, count 0 2006.183.08:12:21.56#ibcon#about to read 3, iclass 34, count 0 2006.183.08:12:21.58#ibcon#read 3, iclass 34, count 0 2006.183.08:12:21.58#ibcon#about to read 4, iclass 34, count 0 2006.183.08:12:21.58#ibcon#read 4, iclass 34, count 0 2006.183.08:12:21.58#ibcon#about to read 5, iclass 34, count 0 2006.183.08:12:21.58#ibcon#read 5, iclass 34, count 0 2006.183.08:12:21.58#ibcon#about to read 6, iclass 34, count 0 2006.183.08:12:21.58#ibcon#read 6, iclass 34, count 0 2006.183.08:12:21.58#ibcon#end of sib2, iclass 34, count 0 2006.183.08:12:21.58#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:12:21.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:12:21.58#ibcon#[27=USB\r\n] 2006.183.08:12:21.58#ibcon#*before write, iclass 34, count 0 2006.183.08:12:21.58#ibcon#enter sib2, iclass 34, count 0 2006.183.08:12:21.58#ibcon#flushed, iclass 34, count 0 2006.183.08:12:21.58#ibcon#about to write, iclass 34, count 0 2006.183.08:12:21.58#ibcon#wrote, iclass 34, count 0 2006.183.08:12:21.58#ibcon#about to read 3, iclass 34, count 0 2006.183.08:12:21.61#ibcon#read 3, iclass 34, count 0 2006.183.08:12:21.61#ibcon#about to read 4, iclass 34, count 0 2006.183.08:12:21.61#ibcon#read 4, iclass 34, count 0 2006.183.08:12:21.61#ibcon#about to read 5, iclass 34, count 0 2006.183.08:12:21.61#ibcon#read 5, iclass 34, count 0 2006.183.08:12:21.61#ibcon#about to read 6, iclass 34, count 0 2006.183.08:12:21.61#ibcon#read 6, iclass 34, count 0 2006.183.08:12:21.61#ibcon#end of sib2, iclass 34, count 0 2006.183.08:12:21.61#ibcon#*after write, iclass 34, count 0 2006.183.08:12:21.61#ibcon#*before return 0, iclass 34, count 0 2006.183.08:12:21.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:21.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:12:21.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:12:21.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:12:21.61$vc4f8/vblo=4,712.99 2006.183.08:12:21.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.08:12:21.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.08:12:21.61#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:21.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:21.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:21.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:21.61#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:12:21.61#ibcon#first serial, iclass 36, count 0 2006.183.08:12:21.61#ibcon#enter sib2, iclass 36, count 0 2006.183.08:12:21.61#ibcon#flushed, iclass 36, count 0 2006.183.08:12:21.61#ibcon#about to write, iclass 36, count 0 2006.183.08:12:21.61#ibcon#wrote, iclass 36, count 0 2006.183.08:12:21.61#ibcon#about to read 3, iclass 36, count 0 2006.183.08:12:21.63#ibcon#read 3, iclass 36, count 0 2006.183.08:12:21.63#ibcon#about to read 4, iclass 36, count 0 2006.183.08:12:21.63#ibcon#read 4, iclass 36, count 0 2006.183.08:12:21.63#ibcon#about to read 5, iclass 36, count 0 2006.183.08:12:21.63#ibcon#read 5, iclass 36, count 0 2006.183.08:12:21.63#ibcon#about to read 6, iclass 36, count 0 2006.183.08:12:21.63#ibcon#read 6, iclass 36, count 0 2006.183.08:12:21.63#ibcon#end of sib2, iclass 36, count 0 2006.183.08:12:21.63#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:12:21.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:12:21.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:12:21.63#ibcon#*before write, iclass 36, count 0 2006.183.08:12:21.63#ibcon#enter sib2, iclass 36, count 0 2006.183.08:12:21.63#ibcon#flushed, iclass 36, count 0 2006.183.08:12:21.63#ibcon#about to write, iclass 36, count 0 2006.183.08:12:21.63#ibcon#wrote, iclass 36, count 0 2006.183.08:12:21.63#ibcon#about to read 3, iclass 36, count 0 2006.183.08:12:21.67#ibcon#read 3, iclass 36, count 0 2006.183.08:12:21.67#ibcon#about to read 4, iclass 36, count 0 2006.183.08:12:21.67#ibcon#read 4, iclass 36, count 0 2006.183.08:12:21.67#ibcon#about to read 5, iclass 36, count 0 2006.183.08:12:21.67#ibcon#read 5, iclass 36, count 0 2006.183.08:12:21.67#ibcon#about to read 6, iclass 36, count 0 2006.183.08:12:21.67#ibcon#read 6, iclass 36, count 0 2006.183.08:12:21.67#ibcon#end of sib2, iclass 36, count 0 2006.183.08:12:21.67#ibcon#*after write, iclass 36, count 0 2006.183.08:12:21.67#ibcon#*before return 0, iclass 36, count 0 2006.183.08:12:21.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:21.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:12:21.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:12:21.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:12:21.67$vc4f8/vb=4,4 2006.183.08:12:21.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.08:12:21.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.08:12:21.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:21.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:21.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:21.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:21.73#ibcon#enter wrdev, iclass 38, count 2 2006.183.08:12:21.73#ibcon#first serial, iclass 38, count 2 2006.183.08:12:21.73#ibcon#enter sib2, iclass 38, count 2 2006.183.08:12:21.73#ibcon#flushed, iclass 38, count 2 2006.183.08:12:21.73#ibcon#about to write, iclass 38, count 2 2006.183.08:12:21.73#ibcon#wrote, iclass 38, count 2 2006.183.08:12:21.73#ibcon#about to read 3, iclass 38, count 2 2006.183.08:12:21.75#ibcon#read 3, iclass 38, count 2 2006.183.08:12:21.75#ibcon#about to read 4, iclass 38, count 2 2006.183.08:12:21.75#ibcon#read 4, iclass 38, count 2 2006.183.08:12:21.75#ibcon#about to read 5, iclass 38, count 2 2006.183.08:12:21.75#ibcon#read 5, iclass 38, count 2 2006.183.08:12:21.75#ibcon#about to read 6, iclass 38, count 2 2006.183.08:12:21.75#ibcon#read 6, iclass 38, count 2 2006.183.08:12:21.75#ibcon#end of sib2, iclass 38, count 2 2006.183.08:12:21.75#ibcon#*mode == 0, iclass 38, count 2 2006.183.08:12:21.75#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.08:12:21.75#ibcon#[27=AT04-04\r\n] 2006.183.08:12:21.75#ibcon#*before write, iclass 38, count 2 2006.183.08:12:21.75#ibcon#enter sib2, iclass 38, count 2 2006.183.08:12:21.75#ibcon#flushed, iclass 38, count 2 2006.183.08:12:21.75#ibcon#about to write, iclass 38, count 2 2006.183.08:12:21.75#ibcon#wrote, iclass 38, count 2 2006.183.08:12:21.75#ibcon#about to read 3, iclass 38, count 2 2006.183.08:12:21.78#ibcon#read 3, iclass 38, count 2 2006.183.08:12:21.78#ibcon#about to read 4, iclass 38, count 2 2006.183.08:12:21.78#ibcon#read 4, iclass 38, count 2 2006.183.08:12:21.78#ibcon#about to read 5, iclass 38, count 2 2006.183.08:12:21.78#ibcon#read 5, iclass 38, count 2 2006.183.08:12:21.78#ibcon#about to read 6, iclass 38, count 2 2006.183.08:12:21.78#ibcon#read 6, iclass 38, count 2 2006.183.08:12:21.78#ibcon#end of sib2, iclass 38, count 2 2006.183.08:12:21.78#ibcon#*after write, iclass 38, count 2 2006.183.08:12:21.78#ibcon#*before return 0, iclass 38, count 2 2006.183.08:12:21.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:21.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:12:21.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.08:12:21.78#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:21.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:21.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:21.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:21.90#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:12:21.90#ibcon#first serial, iclass 38, count 0 2006.183.08:12:21.90#ibcon#enter sib2, iclass 38, count 0 2006.183.08:12:21.90#ibcon#flushed, iclass 38, count 0 2006.183.08:12:21.90#ibcon#about to write, iclass 38, count 0 2006.183.08:12:21.90#ibcon#wrote, iclass 38, count 0 2006.183.08:12:21.90#ibcon#about to read 3, iclass 38, count 0 2006.183.08:12:21.92#ibcon#read 3, iclass 38, count 0 2006.183.08:12:21.92#ibcon#about to read 4, iclass 38, count 0 2006.183.08:12:21.92#ibcon#read 4, iclass 38, count 0 2006.183.08:12:21.92#ibcon#about to read 5, iclass 38, count 0 2006.183.08:12:21.92#ibcon#read 5, iclass 38, count 0 2006.183.08:12:21.92#ibcon#about to read 6, iclass 38, count 0 2006.183.08:12:21.92#ibcon#read 6, iclass 38, count 0 2006.183.08:12:21.92#ibcon#end of sib2, iclass 38, count 0 2006.183.08:12:21.92#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:12:21.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:12:21.92#ibcon#[27=USB\r\n] 2006.183.08:12:21.92#ibcon#*before write, iclass 38, count 0 2006.183.08:12:21.92#ibcon#enter sib2, iclass 38, count 0 2006.183.08:12:21.92#ibcon#flushed, iclass 38, count 0 2006.183.08:12:21.92#ibcon#about to write, iclass 38, count 0 2006.183.08:12:21.92#ibcon#wrote, iclass 38, count 0 2006.183.08:12:21.92#ibcon#about to read 3, iclass 38, count 0 2006.183.08:12:21.95#ibcon#read 3, iclass 38, count 0 2006.183.08:12:21.95#ibcon#about to read 4, iclass 38, count 0 2006.183.08:12:21.95#ibcon#read 4, iclass 38, count 0 2006.183.08:12:21.95#ibcon#about to read 5, iclass 38, count 0 2006.183.08:12:21.95#ibcon#read 5, iclass 38, count 0 2006.183.08:12:21.95#ibcon#about to read 6, iclass 38, count 0 2006.183.08:12:21.95#ibcon#read 6, iclass 38, count 0 2006.183.08:12:21.95#ibcon#end of sib2, iclass 38, count 0 2006.183.08:12:21.95#ibcon#*after write, iclass 38, count 0 2006.183.08:12:21.95#ibcon#*before return 0, iclass 38, count 0 2006.183.08:12:21.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:21.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:12:21.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:12:21.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:12:21.95$vc4f8/vblo=5,744.99 2006.183.08:12:21.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.08:12:21.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.08:12:21.95#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:21.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:21.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:21.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:21.95#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:12:21.95#ibcon#first serial, iclass 40, count 0 2006.183.08:12:21.95#ibcon#enter sib2, iclass 40, count 0 2006.183.08:12:21.95#ibcon#flushed, iclass 40, count 0 2006.183.08:12:21.95#ibcon#about to write, iclass 40, count 0 2006.183.08:12:21.95#ibcon#wrote, iclass 40, count 0 2006.183.08:12:21.95#ibcon#about to read 3, iclass 40, count 0 2006.183.08:12:21.97#ibcon#read 3, iclass 40, count 0 2006.183.08:12:21.97#ibcon#about to read 4, iclass 40, count 0 2006.183.08:12:21.97#ibcon#read 4, iclass 40, count 0 2006.183.08:12:21.97#ibcon#about to read 5, iclass 40, count 0 2006.183.08:12:21.97#ibcon#read 5, iclass 40, count 0 2006.183.08:12:21.97#ibcon#about to read 6, iclass 40, count 0 2006.183.08:12:21.97#ibcon#read 6, iclass 40, count 0 2006.183.08:12:21.97#ibcon#end of sib2, iclass 40, count 0 2006.183.08:12:21.97#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:12:21.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:12:21.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:12:21.97#ibcon#*before write, iclass 40, count 0 2006.183.08:12:21.97#ibcon#enter sib2, iclass 40, count 0 2006.183.08:12:21.97#ibcon#flushed, iclass 40, count 0 2006.183.08:12:21.97#ibcon#about to write, iclass 40, count 0 2006.183.08:12:21.97#ibcon#wrote, iclass 40, count 0 2006.183.08:12:21.97#ibcon#about to read 3, iclass 40, count 0 2006.183.08:12:22.01#ibcon#read 3, iclass 40, count 0 2006.183.08:12:22.01#ibcon#about to read 4, iclass 40, count 0 2006.183.08:12:22.01#ibcon#read 4, iclass 40, count 0 2006.183.08:12:22.01#ibcon#about to read 5, iclass 40, count 0 2006.183.08:12:22.01#ibcon#read 5, iclass 40, count 0 2006.183.08:12:22.01#ibcon#about to read 6, iclass 40, count 0 2006.183.08:12:22.01#ibcon#read 6, iclass 40, count 0 2006.183.08:12:22.01#ibcon#end of sib2, iclass 40, count 0 2006.183.08:12:22.01#ibcon#*after write, iclass 40, count 0 2006.183.08:12:22.01#ibcon#*before return 0, iclass 40, count 0 2006.183.08:12:22.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:22.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:12:22.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:12:22.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:12:22.01$vc4f8/vb=5,4 2006.183.08:12:22.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.08:12:22.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.08:12:22.01#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:22.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:22.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:22.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:22.07#ibcon#enter wrdev, iclass 4, count 2 2006.183.08:12:22.07#ibcon#first serial, iclass 4, count 2 2006.183.08:12:22.07#ibcon#enter sib2, iclass 4, count 2 2006.183.08:12:22.07#ibcon#flushed, iclass 4, count 2 2006.183.08:12:22.07#ibcon#about to write, iclass 4, count 2 2006.183.08:12:22.07#ibcon#wrote, iclass 4, count 2 2006.183.08:12:22.07#ibcon#about to read 3, iclass 4, count 2 2006.183.08:12:22.09#ibcon#read 3, iclass 4, count 2 2006.183.08:12:22.09#ibcon#about to read 4, iclass 4, count 2 2006.183.08:12:22.09#ibcon#read 4, iclass 4, count 2 2006.183.08:12:22.09#ibcon#about to read 5, iclass 4, count 2 2006.183.08:12:22.09#ibcon#read 5, iclass 4, count 2 2006.183.08:12:22.09#ibcon#about to read 6, iclass 4, count 2 2006.183.08:12:22.09#ibcon#read 6, iclass 4, count 2 2006.183.08:12:22.09#ibcon#end of sib2, iclass 4, count 2 2006.183.08:12:22.09#ibcon#*mode == 0, iclass 4, count 2 2006.183.08:12:22.09#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.08:12:22.09#ibcon#[27=AT05-04\r\n] 2006.183.08:12:22.09#ibcon#*before write, iclass 4, count 2 2006.183.08:12:22.09#ibcon#enter sib2, iclass 4, count 2 2006.183.08:12:22.09#ibcon#flushed, iclass 4, count 2 2006.183.08:12:22.09#ibcon#about to write, iclass 4, count 2 2006.183.08:12:22.09#ibcon#wrote, iclass 4, count 2 2006.183.08:12:22.09#ibcon#about to read 3, iclass 4, count 2 2006.183.08:12:22.12#ibcon#read 3, iclass 4, count 2 2006.183.08:12:22.12#ibcon#about to read 4, iclass 4, count 2 2006.183.08:12:22.12#ibcon#read 4, iclass 4, count 2 2006.183.08:12:22.12#ibcon#about to read 5, iclass 4, count 2 2006.183.08:12:22.12#ibcon#read 5, iclass 4, count 2 2006.183.08:12:22.12#ibcon#about to read 6, iclass 4, count 2 2006.183.08:12:22.12#ibcon#read 6, iclass 4, count 2 2006.183.08:12:22.12#ibcon#end of sib2, iclass 4, count 2 2006.183.08:12:22.12#ibcon#*after write, iclass 4, count 2 2006.183.08:12:22.12#ibcon#*before return 0, iclass 4, count 2 2006.183.08:12:22.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:22.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:12:22.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.08:12:22.12#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:22.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:22.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:22.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:22.24#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:12:22.24#ibcon#first serial, iclass 4, count 0 2006.183.08:12:22.24#ibcon#enter sib2, iclass 4, count 0 2006.183.08:12:22.24#ibcon#flushed, iclass 4, count 0 2006.183.08:12:22.24#ibcon#about to write, iclass 4, count 0 2006.183.08:12:22.24#ibcon#wrote, iclass 4, count 0 2006.183.08:12:22.24#ibcon#about to read 3, iclass 4, count 0 2006.183.08:12:22.26#ibcon#read 3, iclass 4, count 0 2006.183.08:12:22.26#ibcon#about to read 4, iclass 4, count 0 2006.183.08:12:22.26#ibcon#read 4, iclass 4, count 0 2006.183.08:12:22.26#ibcon#about to read 5, iclass 4, count 0 2006.183.08:12:22.26#ibcon#read 5, iclass 4, count 0 2006.183.08:12:22.26#ibcon#about to read 6, iclass 4, count 0 2006.183.08:12:22.26#ibcon#read 6, iclass 4, count 0 2006.183.08:12:22.26#ibcon#end of sib2, iclass 4, count 0 2006.183.08:12:22.26#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:12:22.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:12:22.26#ibcon#[27=USB\r\n] 2006.183.08:12:22.26#ibcon#*before write, iclass 4, count 0 2006.183.08:12:22.26#ibcon#enter sib2, iclass 4, count 0 2006.183.08:12:22.26#ibcon#flushed, iclass 4, count 0 2006.183.08:12:22.26#ibcon#about to write, iclass 4, count 0 2006.183.08:12:22.26#ibcon#wrote, iclass 4, count 0 2006.183.08:12:22.26#ibcon#about to read 3, iclass 4, count 0 2006.183.08:12:22.29#ibcon#read 3, iclass 4, count 0 2006.183.08:12:22.29#ibcon#about to read 4, iclass 4, count 0 2006.183.08:12:22.29#ibcon#read 4, iclass 4, count 0 2006.183.08:12:22.29#ibcon#about to read 5, iclass 4, count 0 2006.183.08:12:22.29#ibcon#read 5, iclass 4, count 0 2006.183.08:12:22.29#ibcon#about to read 6, iclass 4, count 0 2006.183.08:12:22.29#ibcon#read 6, iclass 4, count 0 2006.183.08:12:22.29#ibcon#end of sib2, iclass 4, count 0 2006.183.08:12:22.29#ibcon#*after write, iclass 4, count 0 2006.183.08:12:22.29#ibcon#*before return 0, iclass 4, count 0 2006.183.08:12:22.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:22.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:12:22.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:12:22.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:12:22.29$vc4f8/vblo=6,752.99 2006.183.08:12:22.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.08:12:22.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.08:12:22.29#ibcon#ireg 17 cls_cnt 0 2006.183.08:12:22.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:22.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:22.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:22.29#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:12:22.29#ibcon#first serial, iclass 6, count 0 2006.183.08:12:22.29#ibcon#enter sib2, iclass 6, count 0 2006.183.08:12:22.29#ibcon#flushed, iclass 6, count 0 2006.183.08:12:22.29#ibcon#about to write, iclass 6, count 0 2006.183.08:12:22.29#ibcon#wrote, iclass 6, count 0 2006.183.08:12:22.29#ibcon#about to read 3, iclass 6, count 0 2006.183.08:12:22.32#ibcon#read 3, iclass 6, count 0 2006.183.08:12:22.32#ibcon#about to read 4, iclass 6, count 0 2006.183.08:12:22.32#ibcon#read 4, iclass 6, count 0 2006.183.08:12:22.32#ibcon#about to read 5, iclass 6, count 0 2006.183.08:12:22.32#ibcon#read 5, iclass 6, count 0 2006.183.08:12:22.32#ibcon#about to read 6, iclass 6, count 0 2006.183.08:12:22.32#ibcon#read 6, iclass 6, count 0 2006.183.08:12:22.32#ibcon#end of sib2, iclass 6, count 0 2006.183.08:12:22.32#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:12:22.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:12:22.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:12:22.32#ibcon#*before write, iclass 6, count 0 2006.183.08:12:22.32#ibcon#enter sib2, iclass 6, count 0 2006.183.08:12:22.32#ibcon#flushed, iclass 6, count 0 2006.183.08:12:22.32#ibcon#about to write, iclass 6, count 0 2006.183.08:12:22.32#ibcon#wrote, iclass 6, count 0 2006.183.08:12:22.32#ibcon#about to read 3, iclass 6, count 0 2006.183.08:12:22.36#ibcon#read 3, iclass 6, count 0 2006.183.08:12:22.36#ibcon#about to read 4, iclass 6, count 0 2006.183.08:12:22.36#ibcon#read 4, iclass 6, count 0 2006.183.08:12:22.36#ibcon#about to read 5, iclass 6, count 0 2006.183.08:12:22.36#ibcon#read 5, iclass 6, count 0 2006.183.08:12:22.36#ibcon#about to read 6, iclass 6, count 0 2006.183.08:12:22.36#ibcon#read 6, iclass 6, count 0 2006.183.08:12:22.36#ibcon#end of sib2, iclass 6, count 0 2006.183.08:12:22.36#ibcon#*after write, iclass 6, count 0 2006.183.08:12:22.36#ibcon#*before return 0, iclass 6, count 0 2006.183.08:12:22.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:22.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:12:22.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:12:22.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:12:22.36$vc4f8/vb=6,4 2006.183.08:12:22.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.08:12:22.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.08:12:22.36#ibcon#ireg 11 cls_cnt 2 2006.183.08:12:22.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:22.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:22.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:22.41#ibcon#enter wrdev, iclass 10, count 2 2006.183.08:12:22.41#ibcon#first serial, iclass 10, count 2 2006.183.08:12:22.41#ibcon#enter sib2, iclass 10, count 2 2006.183.08:12:22.41#ibcon#flushed, iclass 10, count 2 2006.183.08:12:22.41#ibcon#about to write, iclass 10, count 2 2006.183.08:12:22.41#ibcon#wrote, iclass 10, count 2 2006.183.08:12:22.41#ibcon#about to read 3, iclass 10, count 2 2006.183.08:12:22.43#ibcon#read 3, iclass 10, count 2 2006.183.08:12:22.43#ibcon#about to read 4, iclass 10, count 2 2006.183.08:12:22.43#ibcon#read 4, iclass 10, count 2 2006.183.08:12:22.43#ibcon#about to read 5, iclass 10, count 2 2006.183.08:12:22.43#ibcon#read 5, iclass 10, count 2 2006.183.08:12:22.43#ibcon#about to read 6, iclass 10, count 2 2006.183.08:12:22.43#ibcon#read 6, iclass 10, count 2 2006.183.08:12:22.43#ibcon#end of sib2, iclass 10, count 2 2006.183.08:12:22.43#ibcon#*mode == 0, iclass 10, count 2 2006.183.08:12:22.43#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.08:12:22.43#ibcon#[27=AT06-04\r\n] 2006.183.08:12:22.43#ibcon#*before write, iclass 10, count 2 2006.183.08:12:22.43#ibcon#enter sib2, iclass 10, count 2 2006.183.08:12:22.43#ibcon#flushed, iclass 10, count 2 2006.183.08:12:22.43#ibcon#about to write, iclass 10, count 2 2006.183.08:12:22.43#ibcon#wrote, iclass 10, count 2 2006.183.08:12:22.43#ibcon#about to read 3, iclass 10, count 2 2006.183.08:12:22.46#ibcon#read 3, iclass 10, count 2 2006.183.08:12:22.46#ibcon#about to read 4, iclass 10, count 2 2006.183.08:12:22.46#ibcon#read 4, iclass 10, count 2 2006.183.08:12:22.46#ibcon#about to read 5, iclass 10, count 2 2006.183.08:12:22.46#ibcon#read 5, iclass 10, count 2 2006.183.08:12:22.46#ibcon#about to read 6, iclass 10, count 2 2006.183.08:12:22.46#ibcon#read 6, iclass 10, count 2 2006.183.08:12:22.46#ibcon#end of sib2, iclass 10, count 2 2006.183.08:12:22.46#ibcon#*after write, iclass 10, count 2 2006.183.08:12:22.46#ibcon#*before return 0, iclass 10, count 2 2006.183.08:12:22.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:22.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:12:22.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.08:12:22.46#ibcon#ireg 7 cls_cnt 0 2006.183.08:12:22.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:22.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:22.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:22.58#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:12:22.58#ibcon#first serial, iclass 10, count 0 2006.183.08:12:22.58#ibcon#enter sib2, iclass 10, count 0 2006.183.08:12:22.58#ibcon#flushed, iclass 10, count 0 2006.183.08:12:22.58#ibcon#about to write, iclass 10, count 0 2006.183.08:12:22.58#ibcon#wrote, iclass 10, count 0 2006.183.08:12:22.58#ibcon#about to read 3, iclass 10, count 0 2006.183.08:12:22.60#ibcon#read 3, iclass 10, count 0 2006.183.08:12:22.60#ibcon#about to read 4, iclass 10, count 0 2006.183.08:12:22.60#ibcon#read 4, iclass 10, count 0 2006.183.08:12:22.60#ibcon#about to read 5, iclass 10, count 0 2006.183.08:12:22.60#ibcon#read 5, iclass 10, count 0 2006.183.08:12:22.60#ibcon#about to read 6, iclass 10, count 0 2006.183.08:12:22.60#ibcon#read 6, iclass 10, count 0 2006.183.08:12:22.60#ibcon#end of sib2, iclass 10, count 0 2006.183.08:12:22.60#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:12:22.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:12:22.60#ibcon#[27=USB\r\n] 2006.183.08:12:22.60#ibcon#*before write, iclass 10, count 0 2006.183.08:12:22.60#ibcon#enter sib2, iclass 10, count 0 2006.183.08:12:22.60#ibcon#flushed, iclass 10, count 0 2006.183.08:12:22.60#ibcon#about to write, iclass 10, count 0 2006.183.08:12:22.60#ibcon#wrote, iclass 10, count 0 2006.183.08:12:22.60#ibcon#about to read 3, iclass 10, count 0 2006.183.08:12:22.63#ibcon#read 3, iclass 10, count 0 2006.183.08:12:22.63#ibcon#about to read 4, iclass 10, count 0 2006.183.08:12:22.63#ibcon#read 4, iclass 10, count 0 2006.183.08:12:22.63#ibcon#about to read 5, iclass 10, count 0 2006.183.08:12:22.63#ibcon#read 5, iclass 10, count 0 2006.183.08:12:22.63#ibcon#about to read 6, iclass 10, count 0 2006.183.08:12:22.63#ibcon#read 6, iclass 10, count 0 2006.183.08:12:22.63#ibcon#end of sib2, iclass 10, count 0 2006.183.08:12:22.63#ibcon#*after write, iclass 10, count 0 2006.183.08:12:22.63#ibcon#*before return 0, iclass 10, count 0 2006.183.08:12:22.63#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:22.63#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:12:22.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:12:22.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:12:22.63$vc4f8/vabw=wide 2006.183.08:12:22.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.08:12:22.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.08:12:22.63#ibcon#ireg 8 cls_cnt 0 2006.183.08:12:22.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:12:22.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:12:22.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:12:22.63#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:12:22.63#ibcon#first serial, iclass 12, count 0 2006.183.08:12:22.63#ibcon#enter sib2, iclass 12, count 0 2006.183.08:12:22.63#ibcon#flushed, iclass 12, count 0 2006.183.08:12:22.63#ibcon#about to write, iclass 12, count 0 2006.183.08:12:22.63#ibcon#wrote, iclass 12, count 0 2006.183.08:12:22.63#ibcon#about to read 3, iclass 12, count 0 2006.183.08:12:22.65#ibcon#read 3, iclass 12, count 0 2006.183.08:12:22.65#ibcon#about to read 4, iclass 12, count 0 2006.183.08:12:22.65#ibcon#read 4, iclass 12, count 0 2006.183.08:12:22.65#ibcon#about to read 5, iclass 12, count 0 2006.183.08:12:22.65#ibcon#read 5, iclass 12, count 0 2006.183.08:12:22.65#ibcon#about to read 6, iclass 12, count 0 2006.183.08:12:22.65#ibcon#read 6, iclass 12, count 0 2006.183.08:12:22.65#ibcon#end of sib2, iclass 12, count 0 2006.183.08:12:22.65#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:12:22.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:12:22.65#ibcon#[25=BW32\r\n] 2006.183.08:12:22.65#ibcon#*before write, iclass 12, count 0 2006.183.08:12:22.65#ibcon#enter sib2, iclass 12, count 0 2006.183.08:12:22.65#ibcon#flushed, iclass 12, count 0 2006.183.08:12:22.65#ibcon#about to write, iclass 12, count 0 2006.183.08:12:22.65#ibcon#wrote, iclass 12, count 0 2006.183.08:12:22.65#ibcon#about to read 3, iclass 12, count 0 2006.183.08:12:22.68#ibcon#read 3, iclass 12, count 0 2006.183.08:12:22.68#ibcon#about to read 4, iclass 12, count 0 2006.183.08:12:22.68#ibcon#read 4, iclass 12, count 0 2006.183.08:12:22.68#ibcon#about to read 5, iclass 12, count 0 2006.183.08:12:22.68#ibcon#read 5, iclass 12, count 0 2006.183.08:12:22.68#ibcon#about to read 6, iclass 12, count 0 2006.183.08:12:22.68#ibcon#read 6, iclass 12, count 0 2006.183.08:12:22.68#ibcon#end of sib2, iclass 12, count 0 2006.183.08:12:22.68#ibcon#*after write, iclass 12, count 0 2006.183.08:12:22.68#ibcon#*before return 0, iclass 12, count 0 2006.183.08:12:22.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:12:22.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:12:22.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:12:22.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:12:22.68$vc4f8/vbbw=wide 2006.183.08:12:22.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:12:22.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:12:22.68#ibcon#ireg 8 cls_cnt 0 2006.183.08:12:22.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:12:22.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:12:22.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:12:22.75#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:12:22.75#ibcon#first serial, iclass 14, count 0 2006.183.08:12:22.75#ibcon#enter sib2, iclass 14, count 0 2006.183.08:12:22.75#ibcon#flushed, iclass 14, count 0 2006.183.08:12:22.75#ibcon#about to write, iclass 14, count 0 2006.183.08:12:22.75#ibcon#wrote, iclass 14, count 0 2006.183.08:12:22.75#ibcon#about to read 3, iclass 14, count 0 2006.183.08:12:22.77#ibcon#read 3, iclass 14, count 0 2006.183.08:12:22.77#ibcon#about to read 4, iclass 14, count 0 2006.183.08:12:22.77#ibcon#read 4, iclass 14, count 0 2006.183.08:12:22.77#ibcon#about to read 5, iclass 14, count 0 2006.183.08:12:22.77#ibcon#read 5, iclass 14, count 0 2006.183.08:12:22.77#ibcon#about to read 6, iclass 14, count 0 2006.183.08:12:22.77#ibcon#read 6, iclass 14, count 0 2006.183.08:12:22.77#ibcon#end of sib2, iclass 14, count 0 2006.183.08:12:22.77#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:12:22.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:12:22.77#ibcon#[27=BW32\r\n] 2006.183.08:12:22.77#ibcon#*before write, iclass 14, count 0 2006.183.08:12:22.77#ibcon#enter sib2, iclass 14, count 0 2006.183.08:12:22.77#ibcon#flushed, iclass 14, count 0 2006.183.08:12:22.77#ibcon#about to write, iclass 14, count 0 2006.183.08:12:22.77#ibcon#wrote, iclass 14, count 0 2006.183.08:12:22.77#ibcon#about to read 3, iclass 14, count 0 2006.183.08:12:22.80#ibcon#read 3, iclass 14, count 0 2006.183.08:12:22.80#ibcon#about to read 4, iclass 14, count 0 2006.183.08:12:22.80#ibcon#read 4, iclass 14, count 0 2006.183.08:12:22.80#ibcon#about to read 5, iclass 14, count 0 2006.183.08:12:22.80#ibcon#read 5, iclass 14, count 0 2006.183.08:12:22.80#ibcon#about to read 6, iclass 14, count 0 2006.183.08:12:22.80#ibcon#read 6, iclass 14, count 0 2006.183.08:12:22.80#ibcon#end of sib2, iclass 14, count 0 2006.183.08:12:22.80#ibcon#*after write, iclass 14, count 0 2006.183.08:12:22.80#ibcon#*before return 0, iclass 14, count 0 2006.183.08:12:22.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:12:22.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:12:22.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:12:22.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:12:22.80$4f8m12a/ifd4f 2006.183.08:12:22.80$ifd4f/lo= 2006.183.08:12:22.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:12:22.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:12:22.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:12:22.81$ifd4f/patch= 2006.183.08:12:22.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:12:22.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:12:22.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:12:22.81$4f8m12a/"form=m,16.000,1:2 2006.183.08:12:22.81$4f8m12a/"tpicd 2006.183.08:12:22.81$4f8m12a/echo=off 2006.183.08:12:22.81$4f8m12a/xlog=off 2006.183.08:12:22.81:!2006.183.08:12:50 2006.183.08:12:34.14#trakl#Source acquired 2006.183.08:12:35.14#flagr#flagr/antenna,acquired 2006.183.08:12:50.01:preob 2006.183.08:12:51.14/onsource/TRACKING 2006.183.08:12:51.14:!2006.183.08:13:00 2006.183.08:13:00.00:data_valid=on 2006.183.08:13:00.00:midob 2006.183.08:13:00.14/onsource/TRACKING 2006.183.08:13:00.14/wx/28.34,996.6,86 2006.183.08:13:00.28/cable/+6.4526E-03 2006.183.08:13:01.37/va/01,08,usb,yes,30,31 2006.183.08:13:01.37/va/02,07,usb,yes,30,31 2006.183.08:13:01.37/va/03,06,usb,yes,31,32 2006.183.08:13:01.37/va/04,07,usb,yes,31,33 2006.183.08:13:01.37/va/05,07,usb,yes,32,34 2006.183.08:13:01.37/va/06,06,usb,yes,31,31 2006.183.08:13:01.37/va/07,06,usb,yes,32,31 2006.183.08:13:01.37/va/08,07,usb,yes,30,29 2006.183.08:13:01.60/valo/01,532.99,yes,locked 2006.183.08:13:01.60/valo/02,572.99,yes,locked 2006.183.08:13:01.60/valo/03,672.99,yes,locked 2006.183.08:13:01.60/valo/04,832.99,yes,locked 2006.183.08:13:01.60/valo/05,652.99,yes,locked 2006.183.08:13:01.60/valo/06,772.99,yes,locked 2006.183.08:13:01.60/valo/07,832.99,yes,locked 2006.183.08:13:01.60/valo/08,852.99,yes,locked 2006.183.08:13:02.69/vb/01,04,usb,yes,29,28 2006.183.08:13:02.69/vb/02,04,usb,yes,31,33 2006.183.08:13:02.69/vb/03,04,usb,yes,28,31 2006.183.08:13:02.69/vb/04,04,usb,yes,28,29 2006.183.08:13:02.69/vb/05,04,usb,yes,27,31 2006.183.08:13:02.69/vb/06,04,usb,yes,28,31 2006.183.08:13:02.69/vb/07,04,usb,yes,30,30 2006.183.08:13:02.69/vb/08,04,usb,yes,28,31 2006.183.08:13:02.92/vblo/01,632.99,yes,locked 2006.183.08:13:02.92/vblo/02,640.99,yes,locked 2006.183.08:13:02.92/vblo/03,656.99,yes,locked 2006.183.08:13:02.92/vblo/04,712.99,yes,locked 2006.183.08:13:02.92/vblo/05,744.99,yes,locked 2006.183.08:13:02.92/vblo/06,752.99,yes,locked 2006.183.08:13:02.92/vblo/07,734.99,yes,locked 2006.183.08:13:02.92/vblo/08,744.99,yes,locked 2006.183.08:13:03.07/vabw/8 2006.183.08:13:03.22/vbbw/8 2006.183.08:13:03.31/xfe/off,on,15.0 2006.183.08:13:03.70/ifatt/23,28,28,28 2006.183.08:13:04.07/fmout-gps/S +3.35E-07 2006.183.08:13:04.12:!2006.183.08:14:00 2006.183.08:14:00.01:data_valid=off 2006.183.08:14:00.01:postob 2006.183.08:14:00.21/cable/+6.4513E-03 2006.183.08:14:00.21/wx/28.34,996.6,86 2006.183.08:14:01.07/fmout-gps/S +3.36E-07 2006.183.08:14:01.07:scan_name=183-0814,k06183,60 2006.183.08:14:01.07:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.183.08:14:01.14#flagr#flagr/antenna,new-source 2006.183.08:14:02.14:checkk5 2006.183.08:14:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:14:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:14:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:14:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:14:04.01/chk_obsdata//k5ts1/T1830813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:14:04.38/chk_obsdata//k5ts2/T1830813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:14:04.75/chk_obsdata//k5ts3/T1830813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:14:05.12/chk_obsdata//k5ts4/T1830813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:14:05.81/k5log//k5ts1_log_newline 2006.183.08:14:06.50/k5log//k5ts2_log_newline 2006.183.08:14:07.19/k5log//k5ts3_log_newline 2006.183.08:14:07.89/k5log//k5ts4_log_newline 2006.183.08:14:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:14:07.91:4f8m12a=2 2006.183.08:14:07.91$4f8m12a/echo=on 2006.183.08:14:07.91$4f8m12a/pcalon 2006.183.08:14:07.91$pcalon/"no phase cal control is implemented here 2006.183.08:14:07.91$4f8m12a/"tpicd=stop 2006.183.08:14:07.91$4f8m12a/vc4f8 2006.183.08:14:07.91$vc4f8/valo=1,532.99 2006.183.08:14:07.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.08:14:07.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.08:14:07.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:07.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:07.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:07.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:07.92#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:14:07.92#ibcon#first serial, iclass 21, count 0 2006.183.08:14:07.92#ibcon#enter sib2, iclass 21, count 0 2006.183.08:14:07.92#ibcon#flushed, iclass 21, count 0 2006.183.08:14:07.92#ibcon#about to write, iclass 21, count 0 2006.183.08:14:07.92#ibcon#wrote, iclass 21, count 0 2006.183.08:14:07.92#ibcon#about to read 3, iclass 21, count 0 2006.183.08:14:07.96#ibcon#read 3, iclass 21, count 0 2006.183.08:14:07.96#ibcon#about to read 4, iclass 21, count 0 2006.183.08:14:07.96#ibcon#read 4, iclass 21, count 0 2006.183.08:14:07.96#ibcon#about to read 5, iclass 21, count 0 2006.183.08:14:07.96#ibcon#read 5, iclass 21, count 0 2006.183.08:14:07.96#ibcon#about to read 6, iclass 21, count 0 2006.183.08:14:07.96#ibcon#read 6, iclass 21, count 0 2006.183.08:14:07.96#ibcon#end of sib2, iclass 21, count 0 2006.183.08:14:07.96#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:14:07.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:14:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:14:07.96#ibcon#*before write, iclass 21, count 0 2006.183.08:14:07.96#ibcon#enter sib2, iclass 21, count 0 2006.183.08:14:07.96#ibcon#flushed, iclass 21, count 0 2006.183.08:14:07.96#ibcon#about to write, iclass 21, count 0 2006.183.08:14:07.96#ibcon#wrote, iclass 21, count 0 2006.183.08:14:07.96#ibcon#about to read 3, iclass 21, count 0 2006.183.08:14:08.00#ibcon#read 3, iclass 21, count 0 2006.183.08:14:08.00#ibcon#about to read 4, iclass 21, count 0 2006.183.08:14:08.00#ibcon#read 4, iclass 21, count 0 2006.183.08:14:08.00#ibcon#about to read 5, iclass 21, count 0 2006.183.08:14:08.00#ibcon#read 5, iclass 21, count 0 2006.183.08:14:08.00#ibcon#about to read 6, iclass 21, count 0 2006.183.08:14:08.00#ibcon#read 6, iclass 21, count 0 2006.183.08:14:08.00#ibcon#end of sib2, iclass 21, count 0 2006.183.08:14:08.00#ibcon#*after write, iclass 21, count 0 2006.183.08:14:08.00#ibcon#*before return 0, iclass 21, count 0 2006.183.08:14:08.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:08.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:08.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:14:08.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:14:08.00$vc4f8/va=1,8 2006.183.08:14:08.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.08:14:08.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.08:14:08.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:08.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:08.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:08.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:08.00#ibcon#enter wrdev, iclass 23, count 2 2006.183.08:14:08.00#ibcon#first serial, iclass 23, count 2 2006.183.08:14:08.00#ibcon#enter sib2, iclass 23, count 2 2006.183.08:14:08.00#ibcon#flushed, iclass 23, count 2 2006.183.08:14:08.00#ibcon#about to write, iclass 23, count 2 2006.183.08:14:08.00#ibcon#wrote, iclass 23, count 2 2006.183.08:14:08.00#ibcon#about to read 3, iclass 23, count 2 2006.183.08:14:08.02#ibcon#read 3, iclass 23, count 2 2006.183.08:14:08.02#ibcon#about to read 4, iclass 23, count 2 2006.183.08:14:08.02#ibcon#read 4, iclass 23, count 2 2006.183.08:14:08.02#ibcon#about to read 5, iclass 23, count 2 2006.183.08:14:08.02#ibcon#read 5, iclass 23, count 2 2006.183.08:14:08.02#ibcon#about to read 6, iclass 23, count 2 2006.183.08:14:08.02#ibcon#read 6, iclass 23, count 2 2006.183.08:14:08.02#ibcon#end of sib2, iclass 23, count 2 2006.183.08:14:08.02#ibcon#*mode == 0, iclass 23, count 2 2006.183.08:14:08.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.08:14:08.02#ibcon#[25=AT01-08\r\n] 2006.183.08:14:08.02#ibcon#*before write, iclass 23, count 2 2006.183.08:14:08.02#ibcon#enter sib2, iclass 23, count 2 2006.183.08:14:08.02#ibcon#flushed, iclass 23, count 2 2006.183.08:14:08.02#ibcon#about to write, iclass 23, count 2 2006.183.08:14:08.02#ibcon#wrote, iclass 23, count 2 2006.183.08:14:08.02#ibcon#about to read 3, iclass 23, count 2 2006.183.08:14:08.05#ibcon#read 3, iclass 23, count 2 2006.183.08:14:08.05#ibcon#about to read 4, iclass 23, count 2 2006.183.08:14:08.05#ibcon#read 4, iclass 23, count 2 2006.183.08:14:08.05#ibcon#about to read 5, iclass 23, count 2 2006.183.08:14:08.05#ibcon#read 5, iclass 23, count 2 2006.183.08:14:08.05#ibcon#about to read 6, iclass 23, count 2 2006.183.08:14:08.05#ibcon#read 6, iclass 23, count 2 2006.183.08:14:08.05#ibcon#end of sib2, iclass 23, count 2 2006.183.08:14:08.05#ibcon#*after write, iclass 23, count 2 2006.183.08:14:08.05#ibcon#*before return 0, iclass 23, count 2 2006.183.08:14:08.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:08.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:08.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.08:14:08.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:08.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:08.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:08.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:08.17#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:14:08.17#ibcon#first serial, iclass 23, count 0 2006.183.08:14:08.17#ibcon#enter sib2, iclass 23, count 0 2006.183.08:14:08.17#ibcon#flushed, iclass 23, count 0 2006.183.08:14:08.17#ibcon#about to write, iclass 23, count 0 2006.183.08:14:08.17#ibcon#wrote, iclass 23, count 0 2006.183.08:14:08.17#ibcon#about to read 3, iclass 23, count 0 2006.183.08:14:08.19#ibcon#read 3, iclass 23, count 0 2006.183.08:14:08.19#ibcon#about to read 4, iclass 23, count 0 2006.183.08:14:08.19#ibcon#read 4, iclass 23, count 0 2006.183.08:14:08.19#ibcon#about to read 5, iclass 23, count 0 2006.183.08:14:08.19#ibcon#read 5, iclass 23, count 0 2006.183.08:14:08.19#ibcon#about to read 6, iclass 23, count 0 2006.183.08:14:08.19#ibcon#read 6, iclass 23, count 0 2006.183.08:14:08.19#ibcon#end of sib2, iclass 23, count 0 2006.183.08:14:08.19#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:14:08.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:14:08.19#ibcon#[25=USB\r\n] 2006.183.08:14:08.19#ibcon#*before write, iclass 23, count 0 2006.183.08:14:08.19#ibcon#enter sib2, iclass 23, count 0 2006.183.08:14:08.19#ibcon#flushed, iclass 23, count 0 2006.183.08:14:08.19#ibcon#about to write, iclass 23, count 0 2006.183.08:14:08.19#ibcon#wrote, iclass 23, count 0 2006.183.08:14:08.19#ibcon#about to read 3, iclass 23, count 0 2006.183.08:14:08.22#ibcon#read 3, iclass 23, count 0 2006.183.08:14:08.22#ibcon#about to read 4, iclass 23, count 0 2006.183.08:14:08.22#ibcon#read 4, iclass 23, count 0 2006.183.08:14:08.22#ibcon#about to read 5, iclass 23, count 0 2006.183.08:14:08.22#ibcon#read 5, iclass 23, count 0 2006.183.08:14:08.22#ibcon#about to read 6, iclass 23, count 0 2006.183.08:14:08.22#ibcon#read 6, iclass 23, count 0 2006.183.08:14:08.22#ibcon#end of sib2, iclass 23, count 0 2006.183.08:14:08.22#ibcon#*after write, iclass 23, count 0 2006.183.08:14:08.22#ibcon#*before return 0, iclass 23, count 0 2006.183.08:14:08.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:08.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:08.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:14:08.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:14:08.22$vc4f8/valo=2,572.99 2006.183.08:14:08.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.08:14:08.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.08:14:08.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:08.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:08.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:08.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:08.22#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:14:08.22#ibcon#first serial, iclass 25, count 0 2006.183.08:14:08.22#ibcon#enter sib2, iclass 25, count 0 2006.183.08:14:08.22#ibcon#flushed, iclass 25, count 0 2006.183.08:14:08.22#ibcon#about to write, iclass 25, count 0 2006.183.08:14:08.22#ibcon#wrote, iclass 25, count 0 2006.183.08:14:08.22#ibcon#about to read 3, iclass 25, count 0 2006.183.08:14:08.25#ibcon#read 3, iclass 25, count 0 2006.183.08:14:08.25#ibcon#about to read 4, iclass 25, count 0 2006.183.08:14:08.25#ibcon#read 4, iclass 25, count 0 2006.183.08:14:08.25#ibcon#about to read 5, iclass 25, count 0 2006.183.08:14:08.25#ibcon#read 5, iclass 25, count 0 2006.183.08:14:08.25#ibcon#about to read 6, iclass 25, count 0 2006.183.08:14:08.25#ibcon#read 6, iclass 25, count 0 2006.183.08:14:08.25#ibcon#end of sib2, iclass 25, count 0 2006.183.08:14:08.25#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:14:08.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:14:08.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:14:08.25#ibcon#*before write, iclass 25, count 0 2006.183.08:14:08.25#ibcon#enter sib2, iclass 25, count 0 2006.183.08:14:08.25#ibcon#flushed, iclass 25, count 0 2006.183.08:14:08.25#ibcon#about to write, iclass 25, count 0 2006.183.08:14:08.25#ibcon#wrote, iclass 25, count 0 2006.183.08:14:08.25#ibcon#about to read 3, iclass 25, count 0 2006.183.08:14:08.28#ibcon#read 3, iclass 25, count 0 2006.183.08:14:08.28#ibcon#about to read 4, iclass 25, count 0 2006.183.08:14:08.28#ibcon#read 4, iclass 25, count 0 2006.183.08:14:08.28#ibcon#about to read 5, iclass 25, count 0 2006.183.08:14:08.28#ibcon#read 5, iclass 25, count 0 2006.183.08:14:08.28#ibcon#about to read 6, iclass 25, count 0 2006.183.08:14:08.28#ibcon#read 6, iclass 25, count 0 2006.183.08:14:08.28#ibcon#end of sib2, iclass 25, count 0 2006.183.08:14:08.28#ibcon#*after write, iclass 25, count 0 2006.183.08:14:08.28#ibcon#*before return 0, iclass 25, count 0 2006.183.08:14:08.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:08.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:08.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:14:08.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:14:08.28$vc4f8/va=2,7 2006.183.08:14:08.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.08:14:08.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.08:14:08.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:08.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:08.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:08.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:08.35#ibcon#enter wrdev, iclass 27, count 2 2006.183.08:14:08.35#ibcon#first serial, iclass 27, count 2 2006.183.08:14:08.35#ibcon#enter sib2, iclass 27, count 2 2006.183.08:14:08.35#ibcon#flushed, iclass 27, count 2 2006.183.08:14:08.35#ibcon#about to write, iclass 27, count 2 2006.183.08:14:08.35#ibcon#wrote, iclass 27, count 2 2006.183.08:14:08.35#ibcon#about to read 3, iclass 27, count 2 2006.183.08:14:08.37#ibcon#read 3, iclass 27, count 2 2006.183.08:14:08.37#ibcon#about to read 4, iclass 27, count 2 2006.183.08:14:08.37#ibcon#read 4, iclass 27, count 2 2006.183.08:14:08.37#ibcon#about to read 5, iclass 27, count 2 2006.183.08:14:08.37#ibcon#read 5, iclass 27, count 2 2006.183.08:14:08.37#ibcon#about to read 6, iclass 27, count 2 2006.183.08:14:08.37#ibcon#read 6, iclass 27, count 2 2006.183.08:14:08.37#ibcon#end of sib2, iclass 27, count 2 2006.183.08:14:08.37#ibcon#*mode == 0, iclass 27, count 2 2006.183.08:14:08.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.08:14:08.37#ibcon#[25=AT02-07\r\n] 2006.183.08:14:08.37#ibcon#*before write, iclass 27, count 2 2006.183.08:14:08.37#ibcon#enter sib2, iclass 27, count 2 2006.183.08:14:08.37#ibcon#flushed, iclass 27, count 2 2006.183.08:14:08.37#ibcon#about to write, iclass 27, count 2 2006.183.08:14:08.37#ibcon#wrote, iclass 27, count 2 2006.183.08:14:08.37#ibcon#about to read 3, iclass 27, count 2 2006.183.08:14:08.39#ibcon#read 3, iclass 27, count 2 2006.183.08:14:08.39#ibcon#about to read 4, iclass 27, count 2 2006.183.08:14:08.39#ibcon#read 4, iclass 27, count 2 2006.183.08:14:08.39#ibcon#about to read 5, iclass 27, count 2 2006.183.08:14:08.39#ibcon#read 5, iclass 27, count 2 2006.183.08:14:08.39#ibcon#about to read 6, iclass 27, count 2 2006.183.08:14:08.39#ibcon#read 6, iclass 27, count 2 2006.183.08:14:08.39#ibcon#end of sib2, iclass 27, count 2 2006.183.08:14:08.39#ibcon#*after write, iclass 27, count 2 2006.183.08:14:08.39#ibcon#*before return 0, iclass 27, count 2 2006.183.08:14:08.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:08.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:08.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.08:14:08.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:08.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:08.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:08.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:08.51#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:14:08.51#ibcon#first serial, iclass 27, count 0 2006.183.08:14:08.51#ibcon#enter sib2, iclass 27, count 0 2006.183.08:14:08.51#ibcon#flushed, iclass 27, count 0 2006.183.08:14:08.51#ibcon#about to write, iclass 27, count 0 2006.183.08:14:08.51#ibcon#wrote, iclass 27, count 0 2006.183.08:14:08.51#ibcon#about to read 3, iclass 27, count 0 2006.183.08:14:08.53#ibcon#read 3, iclass 27, count 0 2006.183.08:14:08.53#ibcon#about to read 4, iclass 27, count 0 2006.183.08:14:08.53#ibcon#read 4, iclass 27, count 0 2006.183.08:14:08.53#ibcon#about to read 5, iclass 27, count 0 2006.183.08:14:08.53#ibcon#read 5, iclass 27, count 0 2006.183.08:14:08.53#ibcon#about to read 6, iclass 27, count 0 2006.183.08:14:08.53#ibcon#read 6, iclass 27, count 0 2006.183.08:14:08.53#ibcon#end of sib2, iclass 27, count 0 2006.183.08:14:08.53#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:14:08.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:14:08.53#ibcon#[25=USB\r\n] 2006.183.08:14:08.53#ibcon#*before write, iclass 27, count 0 2006.183.08:14:08.53#ibcon#enter sib2, iclass 27, count 0 2006.183.08:14:08.53#ibcon#flushed, iclass 27, count 0 2006.183.08:14:08.53#ibcon#about to write, iclass 27, count 0 2006.183.08:14:08.53#ibcon#wrote, iclass 27, count 0 2006.183.08:14:08.53#ibcon#about to read 3, iclass 27, count 0 2006.183.08:14:08.56#ibcon#read 3, iclass 27, count 0 2006.183.08:14:08.56#ibcon#about to read 4, iclass 27, count 0 2006.183.08:14:08.56#ibcon#read 4, iclass 27, count 0 2006.183.08:14:08.56#ibcon#about to read 5, iclass 27, count 0 2006.183.08:14:08.56#ibcon#read 5, iclass 27, count 0 2006.183.08:14:08.56#ibcon#about to read 6, iclass 27, count 0 2006.183.08:14:08.56#ibcon#read 6, iclass 27, count 0 2006.183.08:14:08.56#ibcon#end of sib2, iclass 27, count 0 2006.183.08:14:08.56#ibcon#*after write, iclass 27, count 0 2006.183.08:14:08.56#ibcon#*before return 0, iclass 27, count 0 2006.183.08:14:08.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:08.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:08.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:14:08.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:14:08.56$vc4f8/valo=3,672.99 2006.183.08:14:08.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.08:14:08.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.08:14:08.56#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:08.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:08.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:08.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:08.56#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:14:08.56#ibcon#first serial, iclass 29, count 0 2006.183.08:14:08.56#ibcon#enter sib2, iclass 29, count 0 2006.183.08:14:08.56#ibcon#flushed, iclass 29, count 0 2006.183.08:14:08.56#ibcon#about to write, iclass 29, count 0 2006.183.08:14:08.56#ibcon#wrote, iclass 29, count 0 2006.183.08:14:08.56#ibcon#about to read 3, iclass 29, count 0 2006.183.08:14:08.58#ibcon#read 3, iclass 29, count 0 2006.183.08:14:08.58#ibcon#about to read 4, iclass 29, count 0 2006.183.08:14:08.58#ibcon#read 4, iclass 29, count 0 2006.183.08:14:08.58#ibcon#about to read 5, iclass 29, count 0 2006.183.08:14:08.58#ibcon#read 5, iclass 29, count 0 2006.183.08:14:08.58#ibcon#about to read 6, iclass 29, count 0 2006.183.08:14:08.58#ibcon#read 6, iclass 29, count 0 2006.183.08:14:08.58#ibcon#end of sib2, iclass 29, count 0 2006.183.08:14:08.58#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:14:08.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:14:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:14:08.58#ibcon#*before write, iclass 29, count 0 2006.183.08:14:08.58#ibcon#enter sib2, iclass 29, count 0 2006.183.08:14:08.58#ibcon#flushed, iclass 29, count 0 2006.183.08:14:08.58#ibcon#about to write, iclass 29, count 0 2006.183.08:14:08.58#ibcon#wrote, iclass 29, count 0 2006.183.08:14:08.58#ibcon#about to read 3, iclass 29, count 0 2006.183.08:14:08.62#ibcon#read 3, iclass 29, count 0 2006.183.08:14:08.62#ibcon#about to read 4, iclass 29, count 0 2006.183.08:14:08.62#ibcon#read 4, iclass 29, count 0 2006.183.08:14:08.62#ibcon#about to read 5, iclass 29, count 0 2006.183.08:14:08.62#ibcon#read 5, iclass 29, count 0 2006.183.08:14:08.62#ibcon#about to read 6, iclass 29, count 0 2006.183.08:14:08.62#ibcon#read 6, iclass 29, count 0 2006.183.08:14:08.62#ibcon#end of sib2, iclass 29, count 0 2006.183.08:14:08.62#ibcon#*after write, iclass 29, count 0 2006.183.08:14:08.62#ibcon#*before return 0, iclass 29, count 0 2006.183.08:14:08.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:08.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:08.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:14:08.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:14:08.62$vc4f8/va=3,6 2006.183.08:14:08.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.08:14:08.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.08:14:08.62#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:08.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:08.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:08.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:08.69#ibcon#enter wrdev, iclass 31, count 2 2006.183.08:14:08.69#ibcon#first serial, iclass 31, count 2 2006.183.08:14:08.69#ibcon#enter sib2, iclass 31, count 2 2006.183.08:14:08.69#ibcon#flushed, iclass 31, count 2 2006.183.08:14:08.69#ibcon#about to write, iclass 31, count 2 2006.183.08:14:08.69#ibcon#wrote, iclass 31, count 2 2006.183.08:14:08.69#ibcon#about to read 3, iclass 31, count 2 2006.183.08:14:08.71#ibcon#read 3, iclass 31, count 2 2006.183.08:14:08.71#ibcon#about to read 4, iclass 31, count 2 2006.183.08:14:08.71#ibcon#read 4, iclass 31, count 2 2006.183.08:14:08.71#ibcon#about to read 5, iclass 31, count 2 2006.183.08:14:08.71#ibcon#read 5, iclass 31, count 2 2006.183.08:14:08.71#ibcon#about to read 6, iclass 31, count 2 2006.183.08:14:08.71#ibcon#read 6, iclass 31, count 2 2006.183.08:14:08.71#ibcon#end of sib2, iclass 31, count 2 2006.183.08:14:08.71#ibcon#*mode == 0, iclass 31, count 2 2006.183.08:14:08.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.08:14:08.71#ibcon#[25=AT03-06\r\n] 2006.183.08:14:08.71#ibcon#*before write, iclass 31, count 2 2006.183.08:14:08.71#ibcon#enter sib2, iclass 31, count 2 2006.183.08:14:08.71#ibcon#flushed, iclass 31, count 2 2006.183.08:14:08.71#ibcon#about to write, iclass 31, count 2 2006.183.08:14:08.71#ibcon#wrote, iclass 31, count 2 2006.183.08:14:08.71#ibcon#about to read 3, iclass 31, count 2 2006.183.08:14:08.73#ibcon#read 3, iclass 31, count 2 2006.183.08:14:08.73#ibcon#about to read 4, iclass 31, count 2 2006.183.08:14:08.73#ibcon#read 4, iclass 31, count 2 2006.183.08:14:08.73#ibcon#about to read 5, iclass 31, count 2 2006.183.08:14:08.73#ibcon#read 5, iclass 31, count 2 2006.183.08:14:08.73#ibcon#about to read 6, iclass 31, count 2 2006.183.08:14:08.73#ibcon#read 6, iclass 31, count 2 2006.183.08:14:08.73#ibcon#end of sib2, iclass 31, count 2 2006.183.08:14:08.73#ibcon#*after write, iclass 31, count 2 2006.183.08:14:08.73#ibcon#*before return 0, iclass 31, count 2 2006.183.08:14:08.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:08.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:08.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.08:14:08.73#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:08.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:08.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:08.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:08.85#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:14:08.85#ibcon#first serial, iclass 31, count 0 2006.183.08:14:08.85#ibcon#enter sib2, iclass 31, count 0 2006.183.08:14:08.85#ibcon#flushed, iclass 31, count 0 2006.183.08:14:08.85#ibcon#about to write, iclass 31, count 0 2006.183.08:14:08.85#ibcon#wrote, iclass 31, count 0 2006.183.08:14:08.85#ibcon#about to read 3, iclass 31, count 0 2006.183.08:14:08.87#ibcon#read 3, iclass 31, count 0 2006.183.08:14:08.87#ibcon#about to read 4, iclass 31, count 0 2006.183.08:14:08.87#ibcon#read 4, iclass 31, count 0 2006.183.08:14:08.87#ibcon#about to read 5, iclass 31, count 0 2006.183.08:14:08.87#ibcon#read 5, iclass 31, count 0 2006.183.08:14:08.87#ibcon#about to read 6, iclass 31, count 0 2006.183.08:14:08.87#ibcon#read 6, iclass 31, count 0 2006.183.08:14:08.87#ibcon#end of sib2, iclass 31, count 0 2006.183.08:14:08.87#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:14:08.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:14:08.87#ibcon#[25=USB\r\n] 2006.183.08:14:08.87#ibcon#*before write, iclass 31, count 0 2006.183.08:14:08.87#ibcon#enter sib2, iclass 31, count 0 2006.183.08:14:08.87#ibcon#flushed, iclass 31, count 0 2006.183.08:14:08.87#ibcon#about to write, iclass 31, count 0 2006.183.08:14:08.87#ibcon#wrote, iclass 31, count 0 2006.183.08:14:08.87#ibcon#about to read 3, iclass 31, count 0 2006.183.08:14:08.90#ibcon#read 3, iclass 31, count 0 2006.183.08:14:08.90#ibcon#about to read 4, iclass 31, count 0 2006.183.08:14:08.90#ibcon#read 4, iclass 31, count 0 2006.183.08:14:08.90#ibcon#about to read 5, iclass 31, count 0 2006.183.08:14:08.90#ibcon#read 5, iclass 31, count 0 2006.183.08:14:08.90#ibcon#about to read 6, iclass 31, count 0 2006.183.08:14:08.90#ibcon#read 6, iclass 31, count 0 2006.183.08:14:08.90#ibcon#end of sib2, iclass 31, count 0 2006.183.08:14:08.90#ibcon#*after write, iclass 31, count 0 2006.183.08:14:08.90#ibcon#*before return 0, iclass 31, count 0 2006.183.08:14:08.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:08.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:08.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:14:08.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:14:08.90$vc4f8/valo=4,832.99 2006.183.08:14:08.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.08:14:08.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.08:14:08.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:08.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:14:08.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:14:08.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:14:08.90#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:14:08.90#ibcon#first serial, iclass 33, count 0 2006.183.08:14:08.90#ibcon#enter sib2, iclass 33, count 0 2006.183.08:14:08.90#ibcon#flushed, iclass 33, count 0 2006.183.08:14:08.90#ibcon#about to write, iclass 33, count 0 2006.183.08:14:08.90#ibcon#wrote, iclass 33, count 0 2006.183.08:14:08.90#ibcon#about to read 3, iclass 33, count 0 2006.183.08:14:08.92#ibcon#read 3, iclass 33, count 0 2006.183.08:14:08.92#ibcon#about to read 4, iclass 33, count 0 2006.183.08:14:08.92#ibcon#read 4, iclass 33, count 0 2006.183.08:14:08.92#ibcon#about to read 5, iclass 33, count 0 2006.183.08:14:08.92#ibcon#read 5, iclass 33, count 0 2006.183.08:14:08.92#ibcon#about to read 6, iclass 33, count 0 2006.183.08:14:08.92#ibcon#read 6, iclass 33, count 0 2006.183.08:14:08.92#ibcon#end of sib2, iclass 33, count 0 2006.183.08:14:08.92#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:14:08.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:14:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:14:08.92#ibcon#*before write, iclass 33, count 0 2006.183.08:14:08.92#ibcon#enter sib2, iclass 33, count 0 2006.183.08:14:08.92#ibcon#flushed, iclass 33, count 0 2006.183.08:14:08.92#ibcon#about to write, iclass 33, count 0 2006.183.08:14:08.92#ibcon#wrote, iclass 33, count 0 2006.183.08:14:08.92#ibcon#about to read 3, iclass 33, count 0 2006.183.08:14:08.96#ibcon#read 3, iclass 33, count 0 2006.183.08:14:08.96#ibcon#about to read 4, iclass 33, count 0 2006.183.08:14:08.96#ibcon#read 4, iclass 33, count 0 2006.183.08:14:08.96#ibcon#about to read 5, iclass 33, count 0 2006.183.08:14:08.96#ibcon#read 5, iclass 33, count 0 2006.183.08:14:08.96#ibcon#about to read 6, iclass 33, count 0 2006.183.08:14:08.96#ibcon#read 6, iclass 33, count 0 2006.183.08:14:08.96#ibcon#end of sib2, iclass 33, count 0 2006.183.08:14:08.96#ibcon#*after write, iclass 33, count 0 2006.183.08:14:08.96#ibcon#*before return 0, iclass 33, count 0 2006.183.08:14:08.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:14:08.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:14:08.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:14:08.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:14:08.96$vc4f8/va=4,7 2006.183.08:14:08.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.183.08:14:08.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.183.08:14:08.96#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:08.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:14:09.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:14:09.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:14:09.02#ibcon#enter wrdev, iclass 35, count 2 2006.183.08:14:09.02#ibcon#first serial, iclass 35, count 2 2006.183.08:14:09.02#ibcon#enter sib2, iclass 35, count 2 2006.183.08:14:09.02#ibcon#flushed, iclass 35, count 2 2006.183.08:14:09.02#ibcon#about to write, iclass 35, count 2 2006.183.08:14:09.02#ibcon#wrote, iclass 35, count 2 2006.183.08:14:09.02#ibcon#about to read 3, iclass 35, count 2 2006.183.08:14:09.04#ibcon#read 3, iclass 35, count 2 2006.183.08:14:09.04#ibcon#about to read 4, iclass 35, count 2 2006.183.08:14:09.04#ibcon#read 4, iclass 35, count 2 2006.183.08:14:09.04#ibcon#about to read 5, iclass 35, count 2 2006.183.08:14:09.04#ibcon#read 5, iclass 35, count 2 2006.183.08:14:09.04#ibcon#about to read 6, iclass 35, count 2 2006.183.08:14:09.04#ibcon#read 6, iclass 35, count 2 2006.183.08:14:09.04#ibcon#end of sib2, iclass 35, count 2 2006.183.08:14:09.04#ibcon#*mode == 0, iclass 35, count 2 2006.183.08:14:09.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.183.08:14:09.04#ibcon#[25=AT04-07\r\n] 2006.183.08:14:09.04#ibcon#*before write, iclass 35, count 2 2006.183.08:14:09.04#ibcon#enter sib2, iclass 35, count 2 2006.183.08:14:09.04#ibcon#flushed, iclass 35, count 2 2006.183.08:14:09.04#ibcon#about to write, iclass 35, count 2 2006.183.08:14:09.04#ibcon#wrote, iclass 35, count 2 2006.183.08:14:09.04#ibcon#about to read 3, iclass 35, count 2 2006.183.08:14:09.07#ibcon#read 3, iclass 35, count 2 2006.183.08:14:09.07#ibcon#about to read 4, iclass 35, count 2 2006.183.08:14:09.07#ibcon#read 4, iclass 35, count 2 2006.183.08:14:09.07#ibcon#about to read 5, iclass 35, count 2 2006.183.08:14:09.07#ibcon#read 5, iclass 35, count 2 2006.183.08:14:09.07#ibcon#about to read 6, iclass 35, count 2 2006.183.08:14:09.07#ibcon#read 6, iclass 35, count 2 2006.183.08:14:09.07#ibcon#end of sib2, iclass 35, count 2 2006.183.08:14:09.07#ibcon#*after write, iclass 35, count 2 2006.183.08:14:09.07#ibcon#*before return 0, iclass 35, count 2 2006.183.08:14:09.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:14:09.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:14:09.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.183.08:14:09.07#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:09.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:14:09.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:14:09.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:14:09.19#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:14:09.19#ibcon#first serial, iclass 35, count 0 2006.183.08:14:09.19#ibcon#enter sib2, iclass 35, count 0 2006.183.08:14:09.19#ibcon#flushed, iclass 35, count 0 2006.183.08:14:09.19#ibcon#about to write, iclass 35, count 0 2006.183.08:14:09.19#ibcon#wrote, iclass 35, count 0 2006.183.08:14:09.19#ibcon#about to read 3, iclass 35, count 0 2006.183.08:14:09.21#ibcon#read 3, iclass 35, count 0 2006.183.08:14:09.21#ibcon#about to read 4, iclass 35, count 0 2006.183.08:14:09.21#ibcon#read 4, iclass 35, count 0 2006.183.08:14:09.21#ibcon#about to read 5, iclass 35, count 0 2006.183.08:14:09.21#ibcon#read 5, iclass 35, count 0 2006.183.08:14:09.21#ibcon#about to read 6, iclass 35, count 0 2006.183.08:14:09.21#ibcon#read 6, iclass 35, count 0 2006.183.08:14:09.21#ibcon#end of sib2, iclass 35, count 0 2006.183.08:14:09.21#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:14:09.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:14:09.21#ibcon#[25=USB\r\n] 2006.183.08:14:09.21#ibcon#*before write, iclass 35, count 0 2006.183.08:14:09.21#ibcon#enter sib2, iclass 35, count 0 2006.183.08:14:09.21#ibcon#flushed, iclass 35, count 0 2006.183.08:14:09.21#ibcon#about to write, iclass 35, count 0 2006.183.08:14:09.21#ibcon#wrote, iclass 35, count 0 2006.183.08:14:09.21#ibcon#about to read 3, iclass 35, count 0 2006.183.08:14:09.24#ibcon#read 3, iclass 35, count 0 2006.183.08:14:09.24#ibcon#about to read 4, iclass 35, count 0 2006.183.08:14:09.24#ibcon#read 4, iclass 35, count 0 2006.183.08:14:09.24#ibcon#about to read 5, iclass 35, count 0 2006.183.08:14:09.24#ibcon#read 5, iclass 35, count 0 2006.183.08:14:09.24#ibcon#about to read 6, iclass 35, count 0 2006.183.08:14:09.24#ibcon#read 6, iclass 35, count 0 2006.183.08:14:09.24#ibcon#end of sib2, iclass 35, count 0 2006.183.08:14:09.24#ibcon#*after write, iclass 35, count 0 2006.183.08:14:09.24#ibcon#*before return 0, iclass 35, count 0 2006.183.08:14:09.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:14:09.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:14:09.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:14:09.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:14:09.24$vc4f8/valo=5,652.99 2006.183.08:14:09.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.08:14:09.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.08:14:09.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:09.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:09.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:09.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:09.24#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:14:09.24#ibcon#first serial, iclass 37, count 0 2006.183.08:14:09.24#ibcon#enter sib2, iclass 37, count 0 2006.183.08:14:09.24#ibcon#flushed, iclass 37, count 0 2006.183.08:14:09.24#ibcon#about to write, iclass 37, count 0 2006.183.08:14:09.24#ibcon#wrote, iclass 37, count 0 2006.183.08:14:09.24#ibcon#about to read 3, iclass 37, count 0 2006.183.08:14:09.26#ibcon#read 3, iclass 37, count 0 2006.183.08:14:09.26#ibcon#about to read 4, iclass 37, count 0 2006.183.08:14:09.26#ibcon#read 4, iclass 37, count 0 2006.183.08:14:09.26#ibcon#about to read 5, iclass 37, count 0 2006.183.08:14:09.26#ibcon#read 5, iclass 37, count 0 2006.183.08:14:09.26#ibcon#about to read 6, iclass 37, count 0 2006.183.08:14:09.26#ibcon#read 6, iclass 37, count 0 2006.183.08:14:09.26#ibcon#end of sib2, iclass 37, count 0 2006.183.08:14:09.26#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:14:09.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:14:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:14:09.26#ibcon#*before write, iclass 37, count 0 2006.183.08:14:09.26#ibcon#enter sib2, iclass 37, count 0 2006.183.08:14:09.26#ibcon#flushed, iclass 37, count 0 2006.183.08:14:09.26#ibcon#about to write, iclass 37, count 0 2006.183.08:14:09.26#ibcon#wrote, iclass 37, count 0 2006.183.08:14:09.26#ibcon#about to read 3, iclass 37, count 0 2006.183.08:14:09.30#ibcon#read 3, iclass 37, count 0 2006.183.08:14:09.30#ibcon#about to read 4, iclass 37, count 0 2006.183.08:14:09.30#ibcon#read 4, iclass 37, count 0 2006.183.08:14:09.30#ibcon#about to read 5, iclass 37, count 0 2006.183.08:14:09.30#ibcon#read 5, iclass 37, count 0 2006.183.08:14:09.30#ibcon#about to read 6, iclass 37, count 0 2006.183.08:14:09.30#ibcon#read 6, iclass 37, count 0 2006.183.08:14:09.30#ibcon#end of sib2, iclass 37, count 0 2006.183.08:14:09.30#ibcon#*after write, iclass 37, count 0 2006.183.08:14:09.30#ibcon#*before return 0, iclass 37, count 0 2006.183.08:14:09.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:09.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:09.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:14:09.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:14:09.30$vc4f8/va=5,7 2006.183.08:14:09.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.08:14:09.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.08:14:09.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:09.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:09.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:09.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:09.36#ibcon#enter wrdev, iclass 39, count 2 2006.183.08:14:09.36#ibcon#first serial, iclass 39, count 2 2006.183.08:14:09.36#ibcon#enter sib2, iclass 39, count 2 2006.183.08:14:09.36#ibcon#flushed, iclass 39, count 2 2006.183.08:14:09.36#ibcon#about to write, iclass 39, count 2 2006.183.08:14:09.36#ibcon#wrote, iclass 39, count 2 2006.183.08:14:09.36#ibcon#about to read 3, iclass 39, count 2 2006.183.08:14:09.38#ibcon#read 3, iclass 39, count 2 2006.183.08:14:09.38#ibcon#about to read 4, iclass 39, count 2 2006.183.08:14:09.38#ibcon#read 4, iclass 39, count 2 2006.183.08:14:09.38#ibcon#about to read 5, iclass 39, count 2 2006.183.08:14:09.38#ibcon#read 5, iclass 39, count 2 2006.183.08:14:09.38#ibcon#about to read 6, iclass 39, count 2 2006.183.08:14:09.38#ibcon#read 6, iclass 39, count 2 2006.183.08:14:09.38#ibcon#end of sib2, iclass 39, count 2 2006.183.08:14:09.38#ibcon#*mode == 0, iclass 39, count 2 2006.183.08:14:09.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.08:14:09.38#ibcon#[25=AT05-07\r\n] 2006.183.08:14:09.38#ibcon#*before write, iclass 39, count 2 2006.183.08:14:09.38#ibcon#enter sib2, iclass 39, count 2 2006.183.08:14:09.38#ibcon#flushed, iclass 39, count 2 2006.183.08:14:09.38#ibcon#about to write, iclass 39, count 2 2006.183.08:14:09.38#ibcon#wrote, iclass 39, count 2 2006.183.08:14:09.38#ibcon#about to read 3, iclass 39, count 2 2006.183.08:14:09.41#ibcon#read 3, iclass 39, count 2 2006.183.08:14:09.41#ibcon#about to read 4, iclass 39, count 2 2006.183.08:14:09.41#ibcon#read 4, iclass 39, count 2 2006.183.08:14:09.41#ibcon#about to read 5, iclass 39, count 2 2006.183.08:14:09.41#ibcon#read 5, iclass 39, count 2 2006.183.08:14:09.41#ibcon#about to read 6, iclass 39, count 2 2006.183.08:14:09.41#ibcon#read 6, iclass 39, count 2 2006.183.08:14:09.41#ibcon#end of sib2, iclass 39, count 2 2006.183.08:14:09.41#ibcon#*after write, iclass 39, count 2 2006.183.08:14:09.41#ibcon#*before return 0, iclass 39, count 2 2006.183.08:14:09.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:09.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:09.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.08:14:09.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:09.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:09.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:09.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:09.53#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:14:09.53#ibcon#first serial, iclass 39, count 0 2006.183.08:14:09.53#ibcon#enter sib2, iclass 39, count 0 2006.183.08:14:09.53#ibcon#flushed, iclass 39, count 0 2006.183.08:14:09.53#ibcon#about to write, iclass 39, count 0 2006.183.08:14:09.53#ibcon#wrote, iclass 39, count 0 2006.183.08:14:09.53#ibcon#about to read 3, iclass 39, count 0 2006.183.08:14:09.55#ibcon#read 3, iclass 39, count 0 2006.183.08:14:09.55#ibcon#about to read 4, iclass 39, count 0 2006.183.08:14:09.55#ibcon#read 4, iclass 39, count 0 2006.183.08:14:09.55#ibcon#about to read 5, iclass 39, count 0 2006.183.08:14:09.55#ibcon#read 5, iclass 39, count 0 2006.183.08:14:09.55#ibcon#about to read 6, iclass 39, count 0 2006.183.08:14:09.55#ibcon#read 6, iclass 39, count 0 2006.183.08:14:09.55#ibcon#end of sib2, iclass 39, count 0 2006.183.08:14:09.55#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:14:09.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:14:09.55#ibcon#[25=USB\r\n] 2006.183.08:14:09.55#ibcon#*before write, iclass 39, count 0 2006.183.08:14:09.55#ibcon#enter sib2, iclass 39, count 0 2006.183.08:14:09.55#ibcon#flushed, iclass 39, count 0 2006.183.08:14:09.55#ibcon#about to write, iclass 39, count 0 2006.183.08:14:09.55#ibcon#wrote, iclass 39, count 0 2006.183.08:14:09.55#ibcon#about to read 3, iclass 39, count 0 2006.183.08:14:09.58#ibcon#read 3, iclass 39, count 0 2006.183.08:14:09.58#ibcon#about to read 4, iclass 39, count 0 2006.183.08:14:09.58#ibcon#read 4, iclass 39, count 0 2006.183.08:14:09.58#ibcon#about to read 5, iclass 39, count 0 2006.183.08:14:09.58#ibcon#read 5, iclass 39, count 0 2006.183.08:14:09.58#ibcon#about to read 6, iclass 39, count 0 2006.183.08:14:09.58#ibcon#read 6, iclass 39, count 0 2006.183.08:14:09.58#ibcon#end of sib2, iclass 39, count 0 2006.183.08:14:09.58#ibcon#*after write, iclass 39, count 0 2006.183.08:14:09.58#ibcon#*before return 0, iclass 39, count 0 2006.183.08:14:09.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:09.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:09.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:14:09.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:14:09.58$vc4f8/valo=6,772.99 2006.183.08:14:09.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:14:09.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:14:09.58#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:09.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:09.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:09.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:09.58#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:14:09.58#ibcon#first serial, iclass 3, count 0 2006.183.08:14:09.58#ibcon#enter sib2, iclass 3, count 0 2006.183.08:14:09.58#ibcon#flushed, iclass 3, count 0 2006.183.08:14:09.58#ibcon#about to write, iclass 3, count 0 2006.183.08:14:09.58#ibcon#wrote, iclass 3, count 0 2006.183.08:14:09.58#ibcon#about to read 3, iclass 3, count 0 2006.183.08:14:09.60#ibcon#read 3, iclass 3, count 0 2006.183.08:14:09.60#ibcon#about to read 4, iclass 3, count 0 2006.183.08:14:09.60#ibcon#read 4, iclass 3, count 0 2006.183.08:14:09.60#ibcon#about to read 5, iclass 3, count 0 2006.183.08:14:09.60#ibcon#read 5, iclass 3, count 0 2006.183.08:14:09.60#ibcon#about to read 6, iclass 3, count 0 2006.183.08:14:09.60#ibcon#read 6, iclass 3, count 0 2006.183.08:14:09.60#ibcon#end of sib2, iclass 3, count 0 2006.183.08:14:09.60#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:14:09.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:14:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:14:09.60#ibcon#*before write, iclass 3, count 0 2006.183.08:14:09.60#ibcon#enter sib2, iclass 3, count 0 2006.183.08:14:09.60#ibcon#flushed, iclass 3, count 0 2006.183.08:14:09.60#ibcon#about to write, iclass 3, count 0 2006.183.08:14:09.60#ibcon#wrote, iclass 3, count 0 2006.183.08:14:09.60#ibcon#about to read 3, iclass 3, count 0 2006.183.08:14:09.64#ibcon#read 3, iclass 3, count 0 2006.183.08:14:09.64#ibcon#about to read 4, iclass 3, count 0 2006.183.08:14:09.64#ibcon#read 4, iclass 3, count 0 2006.183.08:14:09.64#ibcon#about to read 5, iclass 3, count 0 2006.183.08:14:09.64#ibcon#read 5, iclass 3, count 0 2006.183.08:14:09.64#ibcon#about to read 6, iclass 3, count 0 2006.183.08:14:09.64#ibcon#read 6, iclass 3, count 0 2006.183.08:14:09.64#ibcon#end of sib2, iclass 3, count 0 2006.183.08:14:09.64#ibcon#*after write, iclass 3, count 0 2006.183.08:14:09.64#ibcon#*before return 0, iclass 3, count 0 2006.183.08:14:09.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:09.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:09.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:14:09.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:14:09.64$vc4f8/va=6,6 2006.183.08:14:09.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.08:14:09.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.08:14:09.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:09.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:09.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:09.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:09.70#ibcon#enter wrdev, iclass 5, count 2 2006.183.08:14:09.70#ibcon#first serial, iclass 5, count 2 2006.183.08:14:09.70#ibcon#enter sib2, iclass 5, count 2 2006.183.08:14:09.70#ibcon#flushed, iclass 5, count 2 2006.183.08:14:09.70#ibcon#about to write, iclass 5, count 2 2006.183.08:14:09.70#ibcon#wrote, iclass 5, count 2 2006.183.08:14:09.70#ibcon#about to read 3, iclass 5, count 2 2006.183.08:14:09.73#ibcon#read 3, iclass 5, count 2 2006.183.08:14:09.73#ibcon#about to read 4, iclass 5, count 2 2006.183.08:14:09.73#ibcon#read 4, iclass 5, count 2 2006.183.08:14:09.73#ibcon#about to read 5, iclass 5, count 2 2006.183.08:14:09.73#ibcon#read 5, iclass 5, count 2 2006.183.08:14:09.73#ibcon#about to read 6, iclass 5, count 2 2006.183.08:14:09.73#ibcon#read 6, iclass 5, count 2 2006.183.08:14:09.73#ibcon#end of sib2, iclass 5, count 2 2006.183.08:14:09.73#ibcon#*mode == 0, iclass 5, count 2 2006.183.08:14:09.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.08:14:09.73#ibcon#[25=AT06-06\r\n] 2006.183.08:14:09.73#ibcon#*before write, iclass 5, count 2 2006.183.08:14:09.73#ibcon#enter sib2, iclass 5, count 2 2006.183.08:14:09.73#ibcon#flushed, iclass 5, count 2 2006.183.08:14:09.73#ibcon#about to write, iclass 5, count 2 2006.183.08:14:09.73#ibcon#wrote, iclass 5, count 2 2006.183.08:14:09.73#ibcon#about to read 3, iclass 5, count 2 2006.183.08:14:09.75#ibcon#read 3, iclass 5, count 2 2006.183.08:14:09.75#ibcon#about to read 4, iclass 5, count 2 2006.183.08:14:09.75#ibcon#read 4, iclass 5, count 2 2006.183.08:14:09.75#ibcon#about to read 5, iclass 5, count 2 2006.183.08:14:09.75#ibcon#read 5, iclass 5, count 2 2006.183.08:14:09.75#ibcon#about to read 6, iclass 5, count 2 2006.183.08:14:09.75#ibcon#read 6, iclass 5, count 2 2006.183.08:14:09.75#ibcon#end of sib2, iclass 5, count 2 2006.183.08:14:09.75#ibcon#*after write, iclass 5, count 2 2006.183.08:14:09.75#ibcon#*before return 0, iclass 5, count 2 2006.183.08:14:09.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:09.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:09.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.08:14:09.75#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:09.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:09.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:09.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:09.87#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:14:09.87#ibcon#first serial, iclass 5, count 0 2006.183.08:14:09.87#ibcon#enter sib2, iclass 5, count 0 2006.183.08:14:09.87#ibcon#flushed, iclass 5, count 0 2006.183.08:14:09.87#ibcon#about to write, iclass 5, count 0 2006.183.08:14:09.87#ibcon#wrote, iclass 5, count 0 2006.183.08:14:09.87#ibcon#about to read 3, iclass 5, count 0 2006.183.08:14:09.89#ibcon#read 3, iclass 5, count 0 2006.183.08:14:09.89#ibcon#about to read 4, iclass 5, count 0 2006.183.08:14:09.89#ibcon#read 4, iclass 5, count 0 2006.183.08:14:09.89#ibcon#about to read 5, iclass 5, count 0 2006.183.08:14:09.89#ibcon#read 5, iclass 5, count 0 2006.183.08:14:09.89#ibcon#about to read 6, iclass 5, count 0 2006.183.08:14:09.89#ibcon#read 6, iclass 5, count 0 2006.183.08:14:09.89#ibcon#end of sib2, iclass 5, count 0 2006.183.08:14:09.89#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:14:09.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:14:09.89#ibcon#[25=USB\r\n] 2006.183.08:14:09.89#ibcon#*before write, iclass 5, count 0 2006.183.08:14:09.89#ibcon#enter sib2, iclass 5, count 0 2006.183.08:14:09.89#ibcon#flushed, iclass 5, count 0 2006.183.08:14:09.89#ibcon#about to write, iclass 5, count 0 2006.183.08:14:09.89#ibcon#wrote, iclass 5, count 0 2006.183.08:14:09.89#ibcon#about to read 3, iclass 5, count 0 2006.183.08:14:09.92#ibcon#read 3, iclass 5, count 0 2006.183.08:14:09.92#ibcon#about to read 4, iclass 5, count 0 2006.183.08:14:09.92#ibcon#read 4, iclass 5, count 0 2006.183.08:14:09.92#ibcon#about to read 5, iclass 5, count 0 2006.183.08:14:09.92#ibcon#read 5, iclass 5, count 0 2006.183.08:14:09.92#ibcon#about to read 6, iclass 5, count 0 2006.183.08:14:09.92#ibcon#read 6, iclass 5, count 0 2006.183.08:14:09.92#ibcon#end of sib2, iclass 5, count 0 2006.183.08:14:09.92#ibcon#*after write, iclass 5, count 0 2006.183.08:14:09.92#ibcon#*before return 0, iclass 5, count 0 2006.183.08:14:09.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:09.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:09.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:14:09.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:14:09.92$vc4f8/valo=7,832.99 2006.183.08:14:09.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.08:14:09.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.08:14:09.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:09.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:09.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:09.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:09.92#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:14:09.92#ibcon#first serial, iclass 7, count 0 2006.183.08:14:09.92#ibcon#enter sib2, iclass 7, count 0 2006.183.08:14:09.92#ibcon#flushed, iclass 7, count 0 2006.183.08:14:09.92#ibcon#about to write, iclass 7, count 0 2006.183.08:14:09.92#ibcon#wrote, iclass 7, count 0 2006.183.08:14:09.92#ibcon#about to read 3, iclass 7, count 0 2006.183.08:14:09.94#ibcon#read 3, iclass 7, count 0 2006.183.08:14:09.94#ibcon#about to read 4, iclass 7, count 0 2006.183.08:14:09.94#ibcon#read 4, iclass 7, count 0 2006.183.08:14:09.94#ibcon#about to read 5, iclass 7, count 0 2006.183.08:14:09.94#ibcon#read 5, iclass 7, count 0 2006.183.08:14:09.94#ibcon#about to read 6, iclass 7, count 0 2006.183.08:14:09.94#ibcon#read 6, iclass 7, count 0 2006.183.08:14:09.94#ibcon#end of sib2, iclass 7, count 0 2006.183.08:14:09.94#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:14:09.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:14:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:14:09.94#ibcon#*before write, iclass 7, count 0 2006.183.08:14:09.94#ibcon#enter sib2, iclass 7, count 0 2006.183.08:14:09.94#ibcon#flushed, iclass 7, count 0 2006.183.08:14:09.94#ibcon#about to write, iclass 7, count 0 2006.183.08:14:09.94#ibcon#wrote, iclass 7, count 0 2006.183.08:14:09.94#ibcon#about to read 3, iclass 7, count 0 2006.183.08:14:09.98#ibcon#read 3, iclass 7, count 0 2006.183.08:14:09.98#ibcon#about to read 4, iclass 7, count 0 2006.183.08:14:09.98#ibcon#read 4, iclass 7, count 0 2006.183.08:14:09.98#ibcon#about to read 5, iclass 7, count 0 2006.183.08:14:09.98#ibcon#read 5, iclass 7, count 0 2006.183.08:14:09.98#ibcon#about to read 6, iclass 7, count 0 2006.183.08:14:09.98#ibcon#read 6, iclass 7, count 0 2006.183.08:14:09.98#ibcon#end of sib2, iclass 7, count 0 2006.183.08:14:09.98#ibcon#*after write, iclass 7, count 0 2006.183.08:14:09.98#ibcon#*before return 0, iclass 7, count 0 2006.183.08:14:09.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:09.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:09.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:14:09.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:14:09.98$vc4f8/va=7,6 2006.183.08:14:09.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.08:14:09.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.08:14:09.98#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:09.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:14:10.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:14:10.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:14:10.04#ibcon#enter wrdev, iclass 11, count 2 2006.183.08:14:10.04#ibcon#first serial, iclass 11, count 2 2006.183.08:14:10.04#ibcon#enter sib2, iclass 11, count 2 2006.183.08:14:10.04#ibcon#flushed, iclass 11, count 2 2006.183.08:14:10.04#ibcon#about to write, iclass 11, count 2 2006.183.08:14:10.04#ibcon#wrote, iclass 11, count 2 2006.183.08:14:10.04#ibcon#about to read 3, iclass 11, count 2 2006.183.08:14:10.06#ibcon#read 3, iclass 11, count 2 2006.183.08:14:10.06#ibcon#about to read 4, iclass 11, count 2 2006.183.08:14:10.06#ibcon#read 4, iclass 11, count 2 2006.183.08:14:10.06#ibcon#about to read 5, iclass 11, count 2 2006.183.08:14:10.06#ibcon#read 5, iclass 11, count 2 2006.183.08:14:10.06#ibcon#about to read 6, iclass 11, count 2 2006.183.08:14:10.06#ibcon#read 6, iclass 11, count 2 2006.183.08:14:10.06#ibcon#end of sib2, iclass 11, count 2 2006.183.08:14:10.06#ibcon#*mode == 0, iclass 11, count 2 2006.183.08:14:10.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.08:14:10.06#ibcon#[25=AT07-06\r\n] 2006.183.08:14:10.06#ibcon#*before write, iclass 11, count 2 2006.183.08:14:10.06#ibcon#enter sib2, iclass 11, count 2 2006.183.08:14:10.06#ibcon#flushed, iclass 11, count 2 2006.183.08:14:10.06#ibcon#about to write, iclass 11, count 2 2006.183.08:14:10.06#ibcon#wrote, iclass 11, count 2 2006.183.08:14:10.06#ibcon#about to read 3, iclass 11, count 2 2006.183.08:14:10.09#ibcon#read 3, iclass 11, count 2 2006.183.08:14:10.09#ibcon#about to read 4, iclass 11, count 2 2006.183.08:14:10.09#ibcon#read 4, iclass 11, count 2 2006.183.08:14:10.09#ibcon#about to read 5, iclass 11, count 2 2006.183.08:14:10.09#ibcon#read 5, iclass 11, count 2 2006.183.08:14:10.09#ibcon#about to read 6, iclass 11, count 2 2006.183.08:14:10.09#ibcon#read 6, iclass 11, count 2 2006.183.08:14:10.09#ibcon#end of sib2, iclass 11, count 2 2006.183.08:14:10.09#ibcon#*after write, iclass 11, count 2 2006.183.08:14:10.09#ibcon#*before return 0, iclass 11, count 2 2006.183.08:14:10.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:14:10.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:14:10.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.08:14:10.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:10.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:14:10.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:14:10.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:14:10.21#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:14:10.21#ibcon#first serial, iclass 11, count 0 2006.183.08:14:10.21#ibcon#enter sib2, iclass 11, count 0 2006.183.08:14:10.21#ibcon#flushed, iclass 11, count 0 2006.183.08:14:10.21#ibcon#about to write, iclass 11, count 0 2006.183.08:14:10.21#ibcon#wrote, iclass 11, count 0 2006.183.08:14:10.21#ibcon#about to read 3, iclass 11, count 0 2006.183.08:14:10.23#ibcon#read 3, iclass 11, count 0 2006.183.08:14:10.23#ibcon#about to read 4, iclass 11, count 0 2006.183.08:14:10.23#ibcon#read 4, iclass 11, count 0 2006.183.08:14:10.23#ibcon#about to read 5, iclass 11, count 0 2006.183.08:14:10.23#ibcon#read 5, iclass 11, count 0 2006.183.08:14:10.23#ibcon#about to read 6, iclass 11, count 0 2006.183.08:14:10.23#ibcon#read 6, iclass 11, count 0 2006.183.08:14:10.23#ibcon#end of sib2, iclass 11, count 0 2006.183.08:14:10.23#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:14:10.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:14:10.23#ibcon#[25=USB\r\n] 2006.183.08:14:10.23#ibcon#*before write, iclass 11, count 0 2006.183.08:14:10.23#ibcon#enter sib2, iclass 11, count 0 2006.183.08:14:10.23#ibcon#flushed, iclass 11, count 0 2006.183.08:14:10.23#ibcon#about to write, iclass 11, count 0 2006.183.08:14:10.23#ibcon#wrote, iclass 11, count 0 2006.183.08:14:10.23#ibcon#about to read 3, iclass 11, count 0 2006.183.08:14:10.26#ibcon#read 3, iclass 11, count 0 2006.183.08:14:10.26#ibcon#about to read 4, iclass 11, count 0 2006.183.08:14:10.26#ibcon#read 4, iclass 11, count 0 2006.183.08:14:10.26#ibcon#about to read 5, iclass 11, count 0 2006.183.08:14:10.26#ibcon#read 5, iclass 11, count 0 2006.183.08:14:10.26#ibcon#about to read 6, iclass 11, count 0 2006.183.08:14:10.26#ibcon#read 6, iclass 11, count 0 2006.183.08:14:10.26#ibcon#end of sib2, iclass 11, count 0 2006.183.08:14:10.26#ibcon#*after write, iclass 11, count 0 2006.183.08:14:10.26#ibcon#*before return 0, iclass 11, count 0 2006.183.08:14:10.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:14:10.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:14:10.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:14:10.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:14:10.26$vc4f8/valo=8,852.99 2006.183.08:14:10.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.08:14:10.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.08:14:10.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:10.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:14:10.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:14:10.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:14:10.26#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:14:10.26#ibcon#first serial, iclass 13, count 0 2006.183.08:14:10.26#ibcon#enter sib2, iclass 13, count 0 2006.183.08:14:10.26#ibcon#flushed, iclass 13, count 0 2006.183.08:14:10.26#ibcon#about to write, iclass 13, count 0 2006.183.08:14:10.26#ibcon#wrote, iclass 13, count 0 2006.183.08:14:10.26#ibcon#about to read 3, iclass 13, count 0 2006.183.08:14:10.28#ibcon#read 3, iclass 13, count 0 2006.183.08:14:10.28#ibcon#about to read 4, iclass 13, count 0 2006.183.08:14:10.28#ibcon#read 4, iclass 13, count 0 2006.183.08:14:10.28#ibcon#about to read 5, iclass 13, count 0 2006.183.08:14:10.28#ibcon#read 5, iclass 13, count 0 2006.183.08:14:10.28#ibcon#about to read 6, iclass 13, count 0 2006.183.08:14:10.28#ibcon#read 6, iclass 13, count 0 2006.183.08:14:10.28#ibcon#end of sib2, iclass 13, count 0 2006.183.08:14:10.28#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:14:10.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:14:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:14:10.28#ibcon#*before write, iclass 13, count 0 2006.183.08:14:10.28#ibcon#enter sib2, iclass 13, count 0 2006.183.08:14:10.28#ibcon#flushed, iclass 13, count 0 2006.183.08:14:10.28#ibcon#about to write, iclass 13, count 0 2006.183.08:14:10.28#ibcon#wrote, iclass 13, count 0 2006.183.08:14:10.28#ibcon#about to read 3, iclass 13, count 0 2006.183.08:14:10.32#ibcon#read 3, iclass 13, count 0 2006.183.08:14:10.32#ibcon#about to read 4, iclass 13, count 0 2006.183.08:14:10.32#ibcon#read 4, iclass 13, count 0 2006.183.08:14:10.32#ibcon#about to read 5, iclass 13, count 0 2006.183.08:14:10.32#ibcon#read 5, iclass 13, count 0 2006.183.08:14:10.32#ibcon#about to read 6, iclass 13, count 0 2006.183.08:14:10.32#ibcon#read 6, iclass 13, count 0 2006.183.08:14:10.32#ibcon#end of sib2, iclass 13, count 0 2006.183.08:14:10.32#ibcon#*after write, iclass 13, count 0 2006.183.08:14:10.32#ibcon#*before return 0, iclass 13, count 0 2006.183.08:14:10.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:14:10.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:14:10.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:14:10.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:14:10.32$vc4f8/va=8,7 2006.183.08:14:10.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.08:14:10.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.08:14:10.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:10.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:14:10.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:14:10.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:14:10.38#ibcon#enter wrdev, iclass 15, count 2 2006.183.08:14:10.38#ibcon#first serial, iclass 15, count 2 2006.183.08:14:10.38#ibcon#enter sib2, iclass 15, count 2 2006.183.08:14:10.38#ibcon#flushed, iclass 15, count 2 2006.183.08:14:10.38#ibcon#about to write, iclass 15, count 2 2006.183.08:14:10.38#ibcon#wrote, iclass 15, count 2 2006.183.08:14:10.38#ibcon#about to read 3, iclass 15, count 2 2006.183.08:14:10.40#ibcon#read 3, iclass 15, count 2 2006.183.08:14:10.40#ibcon#about to read 4, iclass 15, count 2 2006.183.08:14:10.40#ibcon#read 4, iclass 15, count 2 2006.183.08:14:10.40#ibcon#about to read 5, iclass 15, count 2 2006.183.08:14:10.40#ibcon#read 5, iclass 15, count 2 2006.183.08:14:10.40#ibcon#about to read 6, iclass 15, count 2 2006.183.08:14:10.40#ibcon#read 6, iclass 15, count 2 2006.183.08:14:10.40#ibcon#end of sib2, iclass 15, count 2 2006.183.08:14:10.40#ibcon#*mode == 0, iclass 15, count 2 2006.183.08:14:10.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.08:14:10.40#ibcon#[25=AT08-07\r\n] 2006.183.08:14:10.40#ibcon#*before write, iclass 15, count 2 2006.183.08:14:10.40#ibcon#enter sib2, iclass 15, count 2 2006.183.08:14:10.40#ibcon#flushed, iclass 15, count 2 2006.183.08:14:10.40#ibcon#about to write, iclass 15, count 2 2006.183.08:14:10.40#ibcon#wrote, iclass 15, count 2 2006.183.08:14:10.40#ibcon#about to read 3, iclass 15, count 2 2006.183.08:14:10.43#ibcon#read 3, iclass 15, count 2 2006.183.08:14:10.43#ibcon#about to read 4, iclass 15, count 2 2006.183.08:14:10.43#ibcon#read 4, iclass 15, count 2 2006.183.08:14:10.43#ibcon#about to read 5, iclass 15, count 2 2006.183.08:14:10.43#ibcon#read 5, iclass 15, count 2 2006.183.08:14:10.43#ibcon#about to read 6, iclass 15, count 2 2006.183.08:14:10.43#ibcon#read 6, iclass 15, count 2 2006.183.08:14:10.43#ibcon#end of sib2, iclass 15, count 2 2006.183.08:14:10.43#ibcon#*after write, iclass 15, count 2 2006.183.08:14:10.43#ibcon#*before return 0, iclass 15, count 2 2006.183.08:14:10.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:14:10.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:14:10.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.08:14:10.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:10.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:14:10.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:14:10.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:14:10.55#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:14:10.55#ibcon#first serial, iclass 15, count 0 2006.183.08:14:10.55#ibcon#enter sib2, iclass 15, count 0 2006.183.08:14:10.55#ibcon#flushed, iclass 15, count 0 2006.183.08:14:10.55#ibcon#about to write, iclass 15, count 0 2006.183.08:14:10.55#ibcon#wrote, iclass 15, count 0 2006.183.08:14:10.55#ibcon#about to read 3, iclass 15, count 0 2006.183.08:14:10.57#ibcon#read 3, iclass 15, count 0 2006.183.08:14:10.57#ibcon#about to read 4, iclass 15, count 0 2006.183.08:14:10.57#ibcon#read 4, iclass 15, count 0 2006.183.08:14:10.57#ibcon#about to read 5, iclass 15, count 0 2006.183.08:14:10.57#ibcon#read 5, iclass 15, count 0 2006.183.08:14:10.57#ibcon#about to read 6, iclass 15, count 0 2006.183.08:14:10.57#ibcon#read 6, iclass 15, count 0 2006.183.08:14:10.57#ibcon#end of sib2, iclass 15, count 0 2006.183.08:14:10.57#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:14:10.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:14:10.57#ibcon#[25=USB\r\n] 2006.183.08:14:10.57#ibcon#*before write, iclass 15, count 0 2006.183.08:14:10.57#ibcon#enter sib2, iclass 15, count 0 2006.183.08:14:10.57#ibcon#flushed, iclass 15, count 0 2006.183.08:14:10.57#ibcon#about to write, iclass 15, count 0 2006.183.08:14:10.57#ibcon#wrote, iclass 15, count 0 2006.183.08:14:10.57#ibcon#about to read 3, iclass 15, count 0 2006.183.08:14:10.60#ibcon#read 3, iclass 15, count 0 2006.183.08:14:10.60#ibcon#about to read 4, iclass 15, count 0 2006.183.08:14:10.60#ibcon#read 4, iclass 15, count 0 2006.183.08:14:10.60#ibcon#about to read 5, iclass 15, count 0 2006.183.08:14:10.60#ibcon#read 5, iclass 15, count 0 2006.183.08:14:10.60#ibcon#about to read 6, iclass 15, count 0 2006.183.08:14:10.60#ibcon#read 6, iclass 15, count 0 2006.183.08:14:10.60#ibcon#end of sib2, iclass 15, count 0 2006.183.08:14:10.60#ibcon#*after write, iclass 15, count 0 2006.183.08:14:10.60#ibcon#*before return 0, iclass 15, count 0 2006.183.08:14:10.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:14:10.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:14:10.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:14:10.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:14:10.60$vc4f8/vblo=1,632.99 2006.183.08:14:10.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.08:14:10.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.08:14:10.60#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:10.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:14:10.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:14:10.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:14:10.60#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:14:10.60#ibcon#first serial, iclass 17, count 0 2006.183.08:14:10.60#ibcon#enter sib2, iclass 17, count 0 2006.183.08:14:10.60#ibcon#flushed, iclass 17, count 0 2006.183.08:14:10.60#ibcon#about to write, iclass 17, count 0 2006.183.08:14:10.60#ibcon#wrote, iclass 17, count 0 2006.183.08:14:10.60#ibcon#about to read 3, iclass 17, count 0 2006.183.08:14:10.62#ibcon#read 3, iclass 17, count 0 2006.183.08:14:10.62#ibcon#about to read 4, iclass 17, count 0 2006.183.08:14:10.62#ibcon#read 4, iclass 17, count 0 2006.183.08:14:10.62#ibcon#about to read 5, iclass 17, count 0 2006.183.08:14:10.62#ibcon#read 5, iclass 17, count 0 2006.183.08:14:10.62#ibcon#about to read 6, iclass 17, count 0 2006.183.08:14:10.62#ibcon#read 6, iclass 17, count 0 2006.183.08:14:10.62#ibcon#end of sib2, iclass 17, count 0 2006.183.08:14:10.62#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:14:10.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:14:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:14:10.62#ibcon#*before write, iclass 17, count 0 2006.183.08:14:10.62#ibcon#enter sib2, iclass 17, count 0 2006.183.08:14:10.62#ibcon#flushed, iclass 17, count 0 2006.183.08:14:10.62#ibcon#about to write, iclass 17, count 0 2006.183.08:14:10.62#ibcon#wrote, iclass 17, count 0 2006.183.08:14:10.62#ibcon#about to read 3, iclass 17, count 0 2006.183.08:14:10.66#ibcon#read 3, iclass 17, count 0 2006.183.08:14:10.66#ibcon#about to read 4, iclass 17, count 0 2006.183.08:14:10.66#ibcon#read 4, iclass 17, count 0 2006.183.08:14:10.66#ibcon#about to read 5, iclass 17, count 0 2006.183.08:14:10.66#ibcon#read 5, iclass 17, count 0 2006.183.08:14:10.66#ibcon#about to read 6, iclass 17, count 0 2006.183.08:14:10.66#ibcon#read 6, iclass 17, count 0 2006.183.08:14:10.66#ibcon#end of sib2, iclass 17, count 0 2006.183.08:14:10.66#ibcon#*after write, iclass 17, count 0 2006.183.08:14:10.66#ibcon#*before return 0, iclass 17, count 0 2006.183.08:14:10.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:14:10.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:14:10.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:14:10.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:14:10.66$vc4f8/vb=1,4 2006.183.08:14:10.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.08:14:10.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.08:14:10.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:10.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:14:10.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:14:10.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:14:10.66#ibcon#enter wrdev, iclass 19, count 2 2006.183.08:14:10.66#ibcon#first serial, iclass 19, count 2 2006.183.08:14:10.66#ibcon#enter sib2, iclass 19, count 2 2006.183.08:14:10.66#ibcon#flushed, iclass 19, count 2 2006.183.08:14:10.66#ibcon#about to write, iclass 19, count 2 2006.183.08:14:10.66#ibcon#wrote, iclass 19, count 2 2006.183.08:14:10.66#ibcon#about to read 3, iclass 19, count 2 2006.183.08:14:10.68#ibcon#read 3, iclass 19, count 2 2006.183.08:14:10.68#ibcon#about to read 4, iclass 19, count 2 2006.183.08:14:10.68#ibcon#read 4, iclass 19, count 2 2006.183.08:14:10.68#ibcon#about to read 5, iclass 19, count 2 2006.183.08:14:10.68#ibcon#read 5, iclass 19, count 2 2006.183.08:14:10.68#ibcon#about to read 6, iclass 19, count 2 2006.183.08:14:10.68#ibcon#read 6, iclass 19, count 2 2006.183.08:14:10.68#ibcon#end of sib2, iclass 19, count 2 2006.183.08:14:10.68#ibcon#*mode == 0, iclass 19, count 2 2006.183.08:14:10.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.08:14:10.68#ibcon#[27=AT01-04\r\n] 2006.183.08:14:10.68#ibcon#*before write, iclass 19, count 2 2006.183.08:14:10.68#ibcon#enter sib2, iclass 19, count 2 2006.183.08:14:10.68#ibcon#flushed, iclass 19, count 2 2006.183.08:14:10.68#ibcon#about to write, iclass 19, count 2 2006.183.08:14:10.68#ibcon#wrote, iclass 19, count 2 2006.183.08:14:10.68#ibcon#about to read 3, iclass 19, count 2 2006.183.08:14:10.71#ibcon#read 3, iclass 19, count 2 2006.183.08:14:10.71#ibcon#about to read 4, iclass 19, count 2 2006.183.08:14:10.71#ibcon#read 4, iclass 19, count 2 2006.183.08:14:10.71#ibcon#about to read 5, iclass 19, count 2 2006.183.08:14:10.71#ibcon#read 5, iclass 19, count 2 2006.183.08:14:10.71#ibcon#about to read 6, iclass 19, count 2 2006.183.08:14:10.71#ibcon#read 6, iclass 19, count 2 2006.183.08:14:10.71#ibcon#end of sib2, iclass 19, count 2 2006.183.08:14:10.71#ibcon#*after write, iclass 19, count 2 2006.183.08:14:10.71#ibcon#*before return 0, iclass 19, count 2 2006.183.08:14:10.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:14:10.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:14:10.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.08:14:10.71#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:10.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:14:10.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:14:10.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:14:10.83#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:14:10.83#ibcon#first serial, iclass 19, count 0 2006.183.08:14:10.83#ibcon#enter sib2, iclass 19, count 0 2006.183.08:14:10.83#ibcon#flushed, iclass 19, count 0 2006.183.08:14:10.83#ibcon#about to write, iclass 19, count 0 2006.183.08:14:10.83#ibcon#wrote, iclass 19, count 0 2006.183.08:14:10.83#ibcon#about to read 3, iclass 19, count 0 2006.183.08:14:10.85#ibcon#read 3, iclass 19, count 0 2006.183.08:14:10.85#ibcon#about to read 4, iclass 19, count 0 2006.183.08:14:10.85#ibcon#read 4, iclass 19, count 0 2006.183.08:14:10.85#ibcon#about to read 5, iclass 19, count 0 2006.183.08:14:10.85#ibcon#read 5, iclass 19, count 0 2006.183.08:14:10.85#ibcon#about to read 6, iclass 19, count 0 2006.183.08:14:10.85#ibcon#read 6, iclass 19, count 0 2006.183.08:14:10.85#ibcon#end of sib2, iclass 19, count 0 2006.183.08:14:10.85#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:14:10.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:14:10.85#ibcon#[27=USB\r\n] 2006.183.08:14:10.85#ibcon#*before write, iclass 19, count 0 2006.183.08:14:10.85#ibcon#enter sib2, iclass 19, count 0 2006.183.08:14:10.85#ibcon#flushed, iclass 19, count 0 2006.183.08:14:10.85#ibcon#about to write, iclass 19, count 0 2006.183.08:14:10.85#ibcon#wrote, iclass 19, count 0 2006.183.08:14:10.85#ibcon#about to read 3, iclass 19, count 0 2006.183.08:14:10.88#ibcon#read 3, iclass 19, count 0 2006.183.08:14:10.88#ibcon#about to read 4, iclass 19, count 0 2006.183.08:14:10.88#ibcon#read 4, iclass 19, count 0 2006.183.08:14:10.88#ibcon#about to read 5, iclass 19, count 0 2006.183.08:14:10.88#ibcon#read 5, iclass 19, count 0 2006.183.08:14:10.88#ibcon#about to read 6, iclass 19, count 0 2006.183.08:14:10.88#ibcon#read 6, iclass 19, count 0 2006.183.08:14:10.88#ibcon#end of sib2, iclass 19, count 0 2006.183.08:14:10.88#ibcon#*after write, iclass 19, count 0 2006.183.08:14:10.88#ibcon#*before return 0, iclass 19, count 0 2006.183.08:14:10.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:14:10.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:14:10.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:14:10.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:14:10.88$vc4f8/vblo=2,640.99 2006.183.08:14:10.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.08:14:10.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.08:14:10.88#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:10.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:10.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:10.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:10.88#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:14:10.88#ibcon#first serial, iclass 21, count 0 2006.183.08:14:10.88#ibcon#enter sib2, iclass 21, count 0 2006.183.08:14:10.88#ibcon#flushed, iclass 21, count 0 2006.183.08:14:10.88#ibcon#about to write, iclass 21, count 0 2006.183.08:14:10.88#ibcon#wrote, iclass 21, count 0 2006.183.08:14:10.88#ibcon#about to read 3, iclass 21, count 0 2006.183.08:14:10.90#ibcon#read 3, iclass 21, count 0 2006.183.08:14:10.90#ibcon#about to read 4, iclass 21, count 0 2006.183.08:14:10.90#ibcon#read 4, iclass 21, count 0 2006.183.08:14:10.90#ibcon#about to read 5, iclass 21, count 0 2006.183.08:14:10.90#ibcon#read 5, iclass 21, count 0 2006.183.08:14:10.90#ibcon#about to read 6, iclass 21, count 0 2006.183.08:14:10.90#ibcon#read 6, iclass 21, count 0 2006.183.08:14:10.90#ibcon#end of sib2, iclass 21, count 0 2006.183.08:14:10.90#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:14:10.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:14:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:14:10.90#ibcon#*before write, iclass 21, count 0 2006.183.08:14:10.90#ibcon#enter sib2, iclass 21, count 0 2006.183.08:14:10.90#ibcon#flushed, iclass 21, count 0 2006.183.08:14:10.90#ibcon#about to write, iclass 21, count 0 2006.183.08:14:10.90#ibcon#wrote, iclass 21, count 0 2006.183.08:14:10.90#ibcon#about to read 3, iclass 21, count 0 2006.183.08:14:10.94#ibcon#read 3, iclass 21, count 0 2006.183.08:14:10.94#ibcon#about to read 4, iclass 21, count 0 2006.183.08:14:10.94#ibcon#read 4, iclass 21, count 0 2006.183.08:14:10.94#ibcon#about to read 5, iclass 21, count 0 2006.183.08:14:10.94#ibcon#read 5, iclass 21, count 0 2006.183.08:14:10.94#ibcon#about to read 6, iclass 21, count 0 2006.183.08:14:10.94#ibcon#read 6, iclass 21, count 0 2006.183.08:14:10.94#ibcon#end of sib2, iclass 21, count 0 2006.183.08:14:10.94#ibcon#*after write, iclass 21, count 0 2006.183.08:14:10.94#ibcon#*before return 0, iclass 21, count 0 2006.183.08:14:10.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:10.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:14:10.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:14:10.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:14:10.94$vc4f8/vb=2,4 2006.183.08:14:10.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.08:14:10.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.08:14:10.94#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:10.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:11.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:11.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:11.00#ibcon#enter wrdev, iclass 23, count 2 2006.183.08:14:11.00#ibcon#first serial, iclass 23, count 2 2006.183.08:14:11.00#ibcon#enter sib2, iclass 23, count 2 2006.183.08:14:11.00#ibcon#flushed, iclass 23, count 2 2006.183.08:14:11.00#ibcon#about to write, iclass 23, count 2 2006.183.08:14:11.00#ibcon#wrote, iclass 23, count 2 2006.183.08:14:11.00#ibcon#about to read 3, iclass 23, count 2 2006.183.08:14:11.02#ibcon#read 3, iclass 23, count 2 2006.183.08:14:11.02#ibcon#about to read 4, iclass 23, count 2 2006.183.08:14:11.02#ibcon#read 4, iclass 23, count 2 2006.183.08:14:11.02#ibcon#about to read 5, iclass 23, count 2 2006.183.08:14:11.02#ibcon#read 5, iclass 23, count 2 2006.183.08:14:11.02#ibcon#about to read 6, iclass 23, count 2 2006.183.08:14:11.02#ibcon#read 6, iclass 23, count 2 2006.183.08:14:11.02#ibcon#end of sib2, iclass 23, count 2 2006.183.08:14:11.02#ibcon#*mode == 0, iclass 23, count 2 2006.183.08:14:11.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.08:14:11.02#ibcon#[27=AT02-04\r\n] 2006.183.08:14:11.02#ibcon#*before write, iclass 23, count 2 2006.183.08:14:11.02#ibcon#enter sib2, iclass 23, count 2 2006.183.08:14:11.02#ibcon#flushed, iclass 23, count 2 2006.183.08:14:11.02#ibcon#about to write, iclass 23, count 2 2006.183.08:14:11.02#ibcon#wrote, iclass 23, count 2 2006.183.08:14:11.02#ibcon#about to read 3, iclass 23, count 2 2006.183.08:14:11.05#ibcon#read 3, iclass 23, count 2 2006.183.08:14:11.05#ibcon#about to read 4, iclass 23, count 2 2006.183.08:14:11.05#ibcon#read 4, iclass 23, count 2 2006.183.08:14:11.05#ibcon#about to read 5, iclass 23, count 2 2006.183.08:14:11.05#ibcon#read 5, iclass 23, count 2 2006.183.08:14:11.05#ibcon#about to read 6, iclass 23, count 2 2006.183.08:14:11.05#ibcon#read 6, iclass 23, count 2 2006.183.08:14:11.05#ibcon#end of sib2, iclass 23, count 2 2006.183.08:14:11.05#ibcon#*after write, iclass 23, count 2 2006.183.08:14:11.05#ibcon#*before return 0, iclass 23, count 2 2006.183.08:14:11.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:11.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:14:11.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.08:14:11.05#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:11.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:11.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:11.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:11.17#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:14:11.17#ibcon#first serial, iclass 23, count 0 2006.183.08:14:11.17#ibcon#enter sib2, iclass 23, count 0 2006.183.08:14:11.17#ibcon#flushed, iclass 23, count 0 2006.183.08:14:11.17#ibcon#about to write, iclass 23, count 0 2006.183.08:14:11.17#ibcon#wrote, iclass 23, count 0 2006.183.08:14:11.17#ibcon#about to read 3, iclass 23, count 0 2006.183.08:14:11.19#ibcon#read 3, iclass 23, count 0 2006.183.08:14:11.19#ibcon#about to read 4, iclass 23, count 0 2006.183.08:14:11.19#ibcon#read 4, iclass 23, count 0 2006.183.08:14:11.19#ibcon#about to read 5, iclass 23, count 0 2006.183.08:14:11.19#ibcon#read 5, iclass 23, count 0 2006.183.08:14:11.19#ibcon#about to read 6, iclass 23, count 0 2006.183.08:14:11.19#ibcon#read 6, iclass 23, count 0 2006.183.08:14:11.19#ibcon#end of sib2, iclass 23, count 0 2006.183.08:14:11.19#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:14:11.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:14:11.19#ibcon#[27=USB\r\n] 2006.183.08:14:11.19#ibcon#*before write, iclass 23, count 0 2006.183.08:14:11.19#ibcon#enter sib2, iclass 23, count 0 2006.183.08:14:11.19#ibcon#flushed, iclass 23, count 0 2006.183.08:14:11.19#ibcon#about to write, iclass 23, count 0 2006.183.08:14:11.19#ibcon#wrote, iclass 23, count 0 2006.183.08:14:11.19#ibcon#about to read 3, iclass 23, count 0 2006.183.08:14:11.22#ibcon#read 3, iclass 23, count 0 2006.183.08:14:11.22#ibcon#about to read 4, iclass 23, count 0 2006.183.08:14:11.22#ibcon#read 4, iclass 23, count 0 2006.183.08:14:11.22#ibcon#about to read 5, iclass 23, count 0 2006.183.08:14:11.22#ibcon#read 5, iclass 23, count 0 2006.183.08:14:11.22#ibcon#about to read 6, iclass 23, count 0 2006.183.08:14:11.22#ibcon#read 6, iclass 23, count 0 2006.183.08:14:11.22#ibcon#end of sib2, iclass 23, count 0 2006.183.08:14:11.22#ibcon#*after write, iclass 23, count 0 2006.183.08:14:11.22#ibcon#*before return 0, iclass 23, count 0 2006.183.08:14:11.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:11.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:14:11.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:14:11.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:14:11.22$vc4f8/vblo=3,656.99 2006.183.08:14:11.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.08:14:11.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.08:14:11.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:11.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:11.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:11.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:11.22#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:14:11.22#ibcon#first serial, iclass 25, count 0 2006.183.08:14:11.22#ibcon#enter sib2, iclass 25, count 0 2006.183.08:14:11.22#ibcon#flushed, iclass 25, count 0 2006.183.08:14:11.22#ibcon#about to write, iclass 25, count 0 2006.183.08:14:11.22#ibcon#wrote, iclass 25, count 0 2006.183.08:14:11.22#ibcon#about to read 3, iclass 25, count 0 2006.183.08:14:11.24#ibcon#read 3, iclass 25, count 0 2006.183.08:14:11.24#ibcon#about to read 4, iclass 25, count 0 2006.183.08:14:11.24#ibcon#read 4, iclass 25, count 0 2006.183.08:14:11.24#ibcon#about to read 5, iclass 25, count 0 2006.183.08:14:11.24#ibcon#read 5, iclass 25, count 0 2006.183.08:14:11.24#ibcon#about to read 6, iclass 25, count 0 2006.183.08:14:11.24#ibcon#read 6, iclass 25, count 0 2006.183.08:14:11.24#ibcon#end of sib2, iclass 25, count 0 2006.183.08:14:11.24#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:14:11.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:14:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:14:11.24#ibcon#*before write, iclass 25, count 0 2006.183.08:14:11.24#ibcon#enter sib2, iclass 25, count 0 2006.183.08:14:11.24#ibcon#flushed, iclass 25, count 0 2006.183.08:14:11.24#ibcon#about to write, iclass 25, count 0 2006.183.08:14:11.24#ibcon#wrote, iclass 25, count 0 2006.183.08:14:11.24#ibcon#about to read 3, iclass 25, count 0 2006.183.08:14:11.28#ibcon#read 3, iclass 25, count 0 2006.183.08:14:11.28#ibcon#about to read 4, iclass 25, count 0 2006.183.08:14:11.28#ibcon#read 4, iclass 25, count 0 2006.183.08:14:11.28#ibcon#about to read 5, iclass 25, count 0 2006.183.08:14:11.28#ibcon#read 5, iclass 25, count 0 2006.183.08:14:11.28#ibcon#about to read 6, iclass 25, count 0 2006.183.08:14:11.28#ibcon#read 6, iclass 25, count 0 2006.183.08:14:11.28#ibcon#end of sib2, iclass 25, count 0 2006.183.08:14:11.28#ibcon#*after write, iclass 25, count 0 2006.183.08:14:11.28#ibcon#*before return 0, iclass 25, count 0 2006.183.08:14:11.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:11.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:14:11.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:14:11.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:14:11.28$vc4f8/vb=3,4 2006.183.08:14:11.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.08:14:11.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.08:14:11.28#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:11.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:11.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:11.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:11.34#ibcon#enter wrdev, iclass 27, count 2 2006.183.08:14:11.34#ibcon#first serial, iclass 27, count 2 2006.183.08:14:11.34#ibcon#enter sib2, iclass 27, count 2 2006.183.08:14:11.34#ibcon#flushed, iclass 27, count 2 2006.183.08:14:11.34#ibcon#about to write, iclass 27, count 2 2006.183.08:14:11.34#ibcon#wrote, iclass 27, count 2 2006.183.08:14:11.34#ibcon#about to read 3, iclass 27, count 2 2006.183.08:14:11.36#ibcon#read 3, iclass 27, count 2 2006.183.08:14:11.36#ibcon#about to read 4, iclass 27, count 2 2006.183.08:14:11.36#ibcon#read 4, iclass 27, count 2 2006.183.08:14:11.36#ibcon#about to read 5, iclass 27, count 2 2006.183.08:14:11.36#ibcon#read 5, iclass 27, count 2 2006.183.08:14:11.36#ibcon#about to read 6, iclass 27, count 2 2006.183.08:14:11.36#ibcon#read 6, iclass 27, count 2 2006.183.08:14:11.36#ibcon#end of sib2, iclass 27, count 2 2006.183.08:14:11.36#ibcon#*mode == 0, iclass 27, count 2 2006.183.08:14:11.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.08:14:11.36#ibcon#[27=AT03-04\r\n] 2006.183.08:14:11.36#ibcon#*before write, iclass 27, count 2 2006.183.08:14:11.36#ibcon#enter sib2, iclass 27, count 2 2006.183.08:14:11.36#ibcon#flushed, iclass 27, count 2 2006.183.08:14:11.36#ibcon#about to write, iclass 27, count 2 2006.183.08:14:11.36#ibcon#wrote, iclass 27, count 2 2006.183.08:14:11.36#ibcon#about to read 3, iclass 27, count 2 2006.183.08:14:11.39#ibcon#read 3, iclass 27, count 2 2006.183.08:14:11.39#ibcon#about to read 4, iclass 27, count 2 2006.183.08:14:11.39#ibcon#read 4, iclass 27, count 2 2006.183.08:14:11.39#ibcon#about to read 5, iclass 27, count 2 2006.183.08:14:11.39#ibcon#read 5, iclass 27, count 2 2006.183.08:14:11.39#ibcon#about to read 6, iclass 27, count 2 2006.183.08:14:11.39#ibcon#read 6, iclass 27, count 2 2006.183.08:14:11.39#ibcon#end of sib2, iclass 27, count 2 2006.183.08:14:11.39#ibcon#*after write, iclass 27, count 2 2006.183.08:14:11.39#ibcon#*before return 0, iclass 27, count 2 2006.183.08:14:11.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:11.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:14:11.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.08:14:11.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:11.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:11.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:11.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:11.51#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:14:11.51#ibcon#first serial, iclass 27, count 0 2006.183.08:14:11.51#ibcon#enter sib2, iclass 27, count 0 2006.183.08:14:11.51#ibcon#flushed, iclass 27, count 0 2006.183.08:14:11.51#ibcon#about to write, iclass 27, count 0 2006.183.08:14:11.51#ibcon#wrote, iclass 27, count 0 2006.183.08:14:11.51#ibcon#about to read 3, iclass 27, count 0 2006.183.08:14:11.53#ibcon#read 3, iclass 27, count 0 2006.183.08:14:11.53#ibcon#about to read 4, iclass 27, count 0 2006.183.08:14:11.53#ibcon#read 4, iclass 27, count 0 2006.183.08:14:11.53#ibcon#about to read 5, iclass 27, count 0 2006.183.08:14:11.53#ibcon#read 5, iclass 27, count 0 2006.183.08:14:11.53#ibcon#about to read 6, iclass 27, count 0 2006.183.08:14:11.53#ibcon#read 6, iclass 27, count 0 2006.183.08:14:11.53#ibcon#end of sib2, iclass 27, count 0 2006.183.08:14:11.53#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:14:11.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:14:11.53#ibcon#[27=USB\r\n] 2006.183.08:14:11.53#ibcon#*before write, iclass 27, count 0 2006.183.08:14:11.53#ibcon#enter sib2, iclass 27, count 0 2006.183.08:14:11.53#ibcon#flushed, iclass 27, count 0 2006.183.08:14:11.53#ibcon#about to write, iclass 27, count 0 2006.183.08:14:11.53#ibcon#wrote, iclass 27, count 0 2006.183.08:14:11.53#ibcon#about to read 3, iclass 27, count 0 2006.183.08:14:11.56#ibcon#read 3, iclass 27, count 0 2006.183.08:14:11.56#ibcon#about to read 4, iclass 27, count 0 2006.183.08:14:11.56#ibcon#read 4, iclass 27, count 0 2006.183.08:14:11.56#ibcon#about to read 5, iclass 27, count 0 2006.183.08:14:11.56#ibcon#read 5, iclass 27, count 0 2006.183.08:14:11.56#ibcon#about to read 6, iclass 27, count 0 2006.183.08:14:11.56#ibcon#read 6, iclass 27, count 0 2006.183.08:14:11.56#ibcon#end of sib2, iclass 27, count 0 2006.183.08:14:11.56#ibcon#*after write, iclass 27, count 0 2006.183.08:14:11.56#ibcon#*before return 0, iclass 27, count 0 2006.183.08:14:11.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:11.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:14:11.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:14:11.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:14:11.56$vc4f8/vblo=4,712.99 2006.183.08:14:11.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.08:14:11.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.08:14:11.56#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:11.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:11.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:11.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:11.56#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:14:11.56#ibcon#first serial, iclass 29, count 0 2006.183.08:14:11.56#ibcon#enter sib2, iclass 29, count 0 2006.183.08:14:11.56#ibcon#flushed, iclass 29, count 0 2006.183.08:14:11.56#ibcon#about to write, iclass 29, count 0 2006.183.08:14:11.56#ibcon#wrote, iclass 29, count 0 2006.183.08:14:11.56#ibcon#about to read 3, iclass 29, count 0 2006.183.08:14:11.58#ibcon#read 3, iclass 29, count 0 2006.183.08:14:11.58#ibcon#about to read 4, iclass 29, count 0 2006.183.08:14:11.58#ibcon#read 4, iclass 29, count 0 2006.183.08:14:11.58#ibcon#about to read 5, iclass 29, count 0 2006.183.08:14:11.58#ibcon#read 5, iclass 29, count 0 2006.183.08:14:11.58#ibcon#about to read 6, iclass 29, count 0 2006.183.08:14:11.58#ibcon#read 6, iclass 29, count 0 2006.183.08:14:11.58#ibcon#end of sib2, iclass 29, count 0 2006.183.08:14:11.58#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:14:11.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:14:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:14:11.58#ibcon#*before write, iclass 29, count 0 2006.183.08:14:11.58#ibcon#enter sib2, iclass 29, count 0 2006.183.08:14:11.58#ibcon#flushed, iclass 29, count 0 2006.183.08:14:11.58#ibcon#about to write, iclass 29, count 0 2006.183.08:14:11.58#ibcon#wrote, iclass 29, count 0 2006.183.08:14:11.58#ibcon#about to read 3, iclass 29, count 0 2006.183.08:14:11.62#ibcon#read 3, iclass 29, count 0 2006.183.08:14:11.62#ibcon#about to read 4, iclass 29, count 0 2006.183.08:14:11.62#ibcon#read 4, iclass 29, count 0 2006.183.08:14:11.62#ibcon#about to read 5, iclass 29, count 0 2006.183.08:14:11.62#ibcon#read 5, iclass 29, count 0 2006.183.08:14:11.62#ibcon#about to read 6, iclass 29, count 0 2006.183.08:14:11.62#ibcon#read 6, iclass 29, count 0 2006.183.08:14:11.62#ibcon#end of sib2, iclass 29, count 0 2006.183.08:14:11.62#ibcon#*after write, iclass 29, count 0 2006.183.08:14:11.62#ibcon#*before return 0, iclass 29, count 0 2006.183.08:14:11.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:11.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:14:11.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:14:11.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:14:11.62$vc4f8/vb=4,4 2006.183.08:14:11.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.08:14:11.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.08:14:11.62#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:11.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:11.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:11.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:11.68#ibcon#enter wrdev, iclass 31, count 2 2006.183.08:14:11.68#ibcon#first serial, iclass 31, count 2 2006.183.08:14:11.68#ibcon#enter sib2, iclass 31, count 2 2006.183.08:14:11.68#ibcon#flushed, iclass 31, count 2 2006.183.08:14:11.68#ibcon#about to write, iclass 31, count 2 2006.183.08:14:11.68#ibcon#wrote, iclass 31, count 2 2006.183.08:14:11.68#ibcon#about to read 3, iclass 31, count 2 2006.183.08:14:11.70#ibcon#read 3, iclass 31, count 2 2006.183.08:14:11.70#ibcon#about to read 4, iclass 31, count 2 2006.183.08:14:11.70#ibcon#read 4, iclass 31, count 2 2006.183.08:14:11.70#ibcon#about to read 5, iclass 31, count 2 2006.183.08:14:11.70#ibcon#read 5, iclass 31, count 2 2006.183.08:14:11.70#ibcon#about to read 6, iclass 31, count 2 2006.183.08:14:11.70#ibcon#read 6, iclass 31, count 2 2006.183.08:14:11.70#ibcon#end of sib2, iclass 31, count 2 2006.183.08:14:11.70#ibcon#*mode == 0, iclass 31, count 2 2006.183.08:14:11.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.08:14:11.70#ibcon#[27=AT04-04\r\n] 2006.183.08:14:11.70#ibcon#*before write, iclass 31, count 2 2006.183.08:14:11.70#ibcon#enter sib2, iclass 31, count 2 2006.183.08:14:11.70#ibcon#flushed, iclass 31, count 2 2006.183.08:14:11.70#ibcon#about to write, iclass 31, count 2 2006.183.08:14:11.70#ibcon#wrote, iclass 31, count 2 2006.183.08:14:11.70#ibcon#about to read 3, iclass 31, count 2 2006.183.08:14:11.73#abcon#<5=/10 1.6 4.4 28.34 86 996.6\r\n> 2006.183.08:14:11.73#ibcon#read 3, iclass 31, count 2 2006.183.08:14:11.73#ibcon#about to read 4, iclass 31, count 2 2006.183.08:14:11.73#ibcon#read 4, iclass 31, count 2 2006.183.08:14:11.73#ibcon#about to read 5, iclass 31, count 2 2006.183.08:14:11.73#ibcon#read 5, iclass 31, count 2 2006.183.08:14:11.73#ibcon#about to read 6, iclass 31, count 2 2006.183.08:14:11.73#ibcon#read 6, iclass 31, count 2 2006.183.08:14:11.73#ibcon#end of sib2, iclass 31, count 2 2006.183.08:14:11.73#ibcon#*after write, iclass 31, count 2 2006.183.08:14:11.73#ibcon#*before return 0, iclass 31, count 2 2006.183.08:14:11.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:11.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:14:11.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.08:14:11.73#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:11.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:11.75#abcon#{5=INTERFACE CLEAR} 2006.183.08:14:11.81#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:14:11.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:11.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:11.85#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:14:11.85#ibcon#first serial, iclass 31, count 0 2006.183.08:14:11.85#ibcon#enter sib2, iclass 31, count 0 2006.183.08:14:11.85#ibcon#flushed, iclass 31, count 0 2006.183.08:14:11.85#ibcon#about to write, iclass 31, count 0 2006.183.08:14:11.85#ibcon#wrote, iclass 31, count 0 2006.183.08:14:11.85#ibcon#about to read 3, iclass 31, count 0 2006.183.08:14:11.87#ibcon#read 3, iclass 31, count 0 2006.183.08:14:11.87#ibcon#about to read 4, iclass 31, count 0 2006.183.08:14:11.87#ibcon#read 4, iclass 31, count 0 2006.183.08:14:11.87#ibcon#about to read 5, iclass 31, count 0 2006.183.08:14:11.87#ibcon#read 5, iclass 31, count 0 2006.183.08:14:11.87#ibcon#about to read 6, iclass 31, count 0 2006.183.08:14:11.87#ibcon#read 6, iclass 31, count 0 2006.183.08:14:11.87#ibcon#end of sib2, iclass 31, count 0 2006.183.08:14:11.87#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:14:11.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:14:11.87#ibcon#[27=USB\r\n] 2006.183.08:14:11.87#ibcon#*before write, iclass 31, count 0 2006.183.08:14:11.87#ibcon#enter sib2, iclass 31, count 0 2006.183.08:14:11.87#ibcon#flushed, iclass 31, count 0 2006.183.08:14:11.87#ibcon#about to write, iclass 31, count 0 2006.183.08:14:11.87#ibcon#wrote, iclass 31, count 0 2006.183.08:14:11.87#ibcon#about to read 3, iclass 31, count 0 2006.183.08:14:11.90#ibcon#read 3, iclass 31, count 0 2006.183.08:14:11.90#ibcon#about to read 4, iclass 31, count 0 2006.183.08:14:11.90#ibcon#read 4, iclass 31, count 0 2006.183.08:14:11.90#ibcon#about to read 5, iclass 31, count 0 2006.183.08:14:11.90#ibcon#read 5, iclass 31, count 0 2006.183.08:14:11.90#ibcon#about to read 6, iclass 31, count 0 2006.183.08:14:11.90#ibcon#read 6, iclass 31, count 0 2006.183.08:14:11.90#ibcon#end of sib2, iclass 31, count 0 2006.183.08:14:11.90#ibcon#*after write, iclass 31, count 0 2006.183.08:14:11.90#ibcon#*before return 0, iclass 31, count 0 2006.183.08:14:11.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:11.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:14:11.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:14:11.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:14:11.90$vc4f8/vblo=5,744.99 2006.183.08:14:11.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.08:14:11.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.08:14:11.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:11.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:11.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:11.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:11.90#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:14:11.90#ibcon#first serial, iclass 37, count 0 2006.183.08:14:11.90#ibcon#enter sib2, iclass 37, count 0 2006.183.08:14:11.90#ibcon#flushed, iclass 37, count 0 2006.183.08:14:11.90#ibcon#about to write, iclass 37, count 0 2006.183.08:14:11.90#ibcon#wrote, iclass 37, count 0 2006.183.08:14:11.90#ibcon#about to read 3, iclass 37, count 0 2006.183.08:14:11.92#ibcon#read 3, iclass 37, count 0 2006.183.08:14:11.92#ibcon#about to read 4, iclass 37, count 0 2006.183.08:14:11.92#ibcon#read 4, iclass 37, count 0 2006.183.08:14:11.92#ibcon#about to read 5, iclass 37, count 0 2006.183.08:14:11.92#ibcon#read 5, iclass 37, count 0 2006.183.08:14:11.92#ibcon#about to read 6, iclass 37, count 0 2006.183.08:14:11.92#ibcon#read 6, iclass 37, count 0 2006.183.08:14:11.92#ibcon#end of sib2, iclass 37, count 0 2006.183.08:14:11.92#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:14:11.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:14:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:14:11.92#ibcon#*before write, iclass 37, count 0 2006.183.08:14:11.92#ibcon#enter sib2, iclass 37, count 0 2006.183.08:14:11.92#ibcon#flushed, iclass 37, count 0 2006.183.08:14:11.92#ibcon#about to write, iclass 37, count 0 2006.183.08:14:11.92#ibcon#wrote, iclass 37, count 0 2006.183.08:14:11.92#ibcon#about to read 3, iclass 37, count 0 2006.183.08:14:11.96#ibcon#read 3, iclass 37, count 0 2006.183.08:14:11.96#ibcon#about to read 4, iclass 37, count 0 2006.183.08:14:11.96#ibcon#read 4, iclass 37, count 0 2006.183.08:14:11.96#ibcon#about to read 5, iclass 37, count 0 2006.183.08:14:11.96#ibcon#read 5, iclass 37, count 0 2006.183.08:14:11.96#ibcon#about to read 6, iclass 37, count 0 2006.183.08:14:11.96#ibcon#read 6, iclass 37, count 0 2006.183.08:14:11.96#ibcon#end of sib2, iclass 37, count 0 2006.183.08:14:11.96#ibcon#*after write, iclass 37, count 0 2006.183.08:14:11.96#ibcon#*before return 0, iclass 37, count 0 2006.183.08:14:11.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:11.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:14:11.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:14:11.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:14:11.96$vc4f8/vb=5,4 2006.183.08:14:11.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.08:14:11.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.08:14:11.96#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:11.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:12.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:12.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:12.02#ibcon#enter wrdev, iclass 39, count 2 2006.183.08:14:12.02#ibcon#first serial, iclass 39, count 2 2006.183.08:14:12.02#ibcon#enter sib2, iclass 39, count 2 2006.183.08:14:12.02#ibcon#flushed, iclass 39, count 2 2006.183.08:14:12.02#ibcon#about to write, iclass 39, count 2 2006.183.08:14:12.02#ibcon#wrote, iclass 39, count 2 2006.183.08:14:12.02#ibcon#about to read 3, iclass 39, count 2 2006.183.08:14:12.04#ibcon#read 3, iclass 39, count 2 2006.183.08:14:12.04#ibcon#about to read 4, iclass 39, count 2 2006.183.08:14:12.04#ibcon#read 4, iclass 39, count 2 2006.183.08:14:12.04#ibcon#about to read 5, iclass 39, count 2 2006.183.08:14:12.04#ibcon#read 5, iclass 39, count 2 2006.183.08:14:12.04#ibcon#about to read 6, iclass 39, count 2 2006.183.08:14:12.04#ibcon#read 6, iclass 39, count 2 2006.183.08:14:12.04#ibcon#end of sib2, iclass 39, count 2 2006.183.08:14:12.04#ibcon#*mode == 0, iclass 39, count 2 2006.183.08:14:12.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.08:14:12.04#ibcon#[27=AT05-04\r\n] 2006.183.08:14:12.04#ibcon#*before write, iclass 39, count 2 2006.183.08:14:12.04#ibcon#enter sib2, iclass 39, count 2 2006.183.08:14:12.04#ibcon#flushed, iclass 39, count 2 2006.183.08:14:12.04#ibcon#about to write, iclass 39, count 2 2006.183.08:14:12.04#ibcon#wrote, iclass 39, count 2 2006.183.08:14:12.04#ibcon#about to read 3, iclass 39, count 2 2006.183.08:14:12.07#ibcon#read 3, iclass 39, count 2 2006.183.08:14:12.07#ibcon#about to read 4, iclass 39, count 2 2006.183.08:14:12.07#ibcon#read 4, iclass 39, count 2 2006.183.08:14:12.07#ibcon#about to read 5, iclass 39, count 2 2006.183.08:14:12.07#ibcon#read 5, iclass 39, count 2 2006.183.08:14:12.07#ibcon#about to read 6, iclass 39, count 2 2006.183.08:14:12.07#ibcon#read 6, iclass 39, count 2 2006.183.08:14:12.07#ibcon#end of sib2, iclass 39, count 2 2006.183.08:14:12.07#ibcon#*after write, iclass 39, count 2 2006.183.08:14:12.07#ibcon#*before return 0, iclass 39, count 2 2006.183.08:14:12.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:12.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:14:12.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.08:14:12.07#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:12.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:12.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:12.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:12.19#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:14:12.19#ibcon#first serial, iclass 39, count 0 2006.183.08:14:12.19#ibcon#enter sib2, iclass 39, count 0 2006.183.08:14:12.19#ibcon#flushed, iclass 39, count 0 2006.183.08:14:12.19#ibcon#about to write, iclass 39, count 0 2006.183.08:14:12.19#ibcon#wrote, iclass 39, count 0 2006.183.08:14:12.19#ibcon#about to read 3, iclass 39, count 0 2006.183.08:14:12.21#ibcon#read 3, iclass 39, count 0 2006.183.08:14:12.21#ibcon#about to read 4, iclass 39, count 0 2006.183.08:14:12.21#ibcon#read 4, iclass 39, count 0 2006.183.08:14:12.21#ibcon#about to read 5, iclass 39, count 0 2006.183.08:14:12.21#ibcon#read 5, iclass 39, count 0 2006.183.08:14:12.21#ibcon#about to read 6, iclass 39, count 0 2006.183.08:14:12.21#ibcon#read 6, iclass 39, count 0 2006.183.08:14:12.21#ibcon#end of sib2, iclass 39, count 0 2006.183.08:14:12.21#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:14:12.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:14:12.21#ibcon#[27=USB\r\n] 2006.183.08:14:12.21#ibcon#*before write, iclass 39, count 0 2006.183.08:14:12.21#ibcon#enter sib2, iclass 39, count 0 2006.183.08:14:12.21#ibcon#flushed, iclass 39, count 0 2006.183.08:14:12.21#ibcon#about to write, iclass 39, count 0 2006.183.08:14:12.21#ibcon#wrote, iclass 39, count 0 2006.183.08:14:12.21#ibcon#about to read 3, iclass 39, count 0 2006.183.08:14:12.24#ibcon#read 3, iclass 39, count 0 2006.183.08:14:12.24#ibcon#about to read 4, iclass 39, count 0 2006.183.08:14:12.24#ibcon#read 4, iclass 39, count 0 2006.183.08:14:12.24#ibcon#about to read 5, iclass 39, count 0 2006.183.08:14:12.24#ibcon#read 5, iclass 39, count 0 2006.183.08:14:12.24#ibcon#about to read 6, iclass 39, count 0 2006.183.08:14:12.24#ibcon#read 6, iclass 39, count 0 2006.183.08:14:12.24#ibcon#end of sib2, iclass 39, count 0 2006.183.08:14:12.24#ibcon#*after write, iclass 39, count 0 2006.183.08:14:12.24#ibcon#*before return 0, iclass 39, count 0 2006.183.08:14:12.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:12.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:14:12.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:14:12.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:14:12.24$vc4f8/vblo=6,752.99 2006.183.08:14:12.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:14:12.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:14:12.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:14:12.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:12.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:12.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:12.24#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:14:12.24#ibcon#first serial, iclass 3, count 0 2006.183.08:14:12.24#ibcon#enter sib2, iclass 3, count 0 2006.183.08:14:12.24#ibcon#flushed, iclass 3, count 0 2006.183.08:14:12.24#ibcon#about to write, iclass 3, count 0 2006.183.08:14:12.24#ibcon#wrote, iclass 3, count 0 2006.183.08:14:12.24#ibcon#about to read 3, iclass 3, count 0 2006.183.08:14:12.26#ibcon#read 3, iclass 3, count 0 2006.183.08:14:12.26#ibcon#about to read 4, iclass 3, count 0 2006.183.08:14:12.26#ibcon#read 4, iclass 3, count 0 2006.183.08:14:12.26#ibcon#about to read 5, iclass 3, count 0 2006.183.08:14:12.26#ibcon#read 5, iclass 3, count 0 2006.183.08:14:12.26#ibcon#about to read 6, iclass 3, count 0 2006.183.08:14:12.26#ibcon#read 6, iclass 3, count 0 2006.183.08:14:12.26#ibcon#end of sib2, iclass 3, count 0 2006.183.08:14:12.26#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:14:12.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:14:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:14:12.26#ibcon#*before write, iclass 3, count 0 2006.183.08:14:12.26#ibcon#enter sib2, iclass 3, count 0 2006.183.08:14:12.26#ibcon#flushed, iclass 3, count 0 2006.183.08:14:12.26#ibcon#about to write, iclass 3, count 0 2006.183.08:14:12.26#ibcon#wrote, iclass 3, count 0 2006.183.08:14:12.26#ibcon#about to read 3, iclass 3, count 0 2006.183.08:14:12.30#ibcon#read 3, iclass 3, count 0 2006.183.08:14:12.30#ibcon#about to read 4, iclass 3, count 0 2006.183.08:14:12.30#ibcon#read 4, iclass 3, count 0 2006.183.08:14:12.30#ibcon#about to read 5, iclass 3, count 0 2006.183.08:14:12.30#ibcon#read 5, iclass 3, count 0 2006.183.08:14:12.30#ibcon#about to read 6, iclass 3, count 0 2006.183.08:14:12.30#ibcon#read 6, iclass 3, count 0 2006.183.08:14:12.30#ibcon#end of sib2, iclass 3, count 0 2006.183.08:14:12.30#ibcon#*after write, iclass 3, count 0 2006.183.08:14:12.30#ibcon#*before return 0, iclass 3, count 0 2006.183.08:14:12.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:12.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:14:12.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:14:12.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:14:12.30$vc4f8/vb=6,4 2006.183.08:14:12.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.08:14:12.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.08:14:12.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:14:12.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:12.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:12.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:12.36#ibcon#enter wrdev, iclass 5, count 2 2006.183.08:14:12.36#ibcon#first serial, iclass 5, count 2 2006.183.08:14:12.36#ibcon#enter sib2, iclass 5, count 2 2006.183.08:14:12.36#ibcon#flushed, iclass 5, count 2 2006.183.08:14:12.36#ibcon#about to write, iclass 5, count 2 2006.183.08:14:12.36#ibcon#wrote, iclass 5, count 2 2006.183.08:14:12.36#ibcon#about to read 3, iclass 5, count 2 2006.183.08:14:12.38#ibcon#read 3, iclass 5, count 2 2006.183.08:14:12.38#ibcon#about to read 4, iclass 5, count 2 2006.183.08:14:12.38#ibcon#read 4, iclass 5, count 2 2006.183.08:14:12.38#ibcon#about to read 5, iclass 5, count 2 2006.183.08:14:12.38#ibcon#read 5, iclass 5, count 2 2006.183.08:14:12.38#ibcon#about to read 6, iclass 5, count 2 2006.183.08:14:12.38#ibcon#read 6, iclass 5, count 2 2006.183.08:14:12.38#ibcon#end of sib2, iclass 5, count 2 2006.183.08:14:12.38#ibcon#*mode == 0, iclass 5, count 2 2006.183.08:14:12.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.08:14:12.38#ibcon#[27=AT06-04\r\n] 2006.183.08:14:12.38#ibcon#*before write, iclass 5, count 2 2006.183.08:14:12.38#ibcon#enter sib2, iclass 5, count 2 2006.183.08:14:12.38#ibcon#flushed, iclass 5, count 2 2006.183.08:14:12.38#ibcon#about to write, iclass 5, count 2 2006.183.08:14:12.38#ibcon#wrote, iclass 5, count 2 2006.183.08:14:12.38#ibcon#about to read 3, iclass 5, count 2 2006.183.08:14:12.41#ibcon#read 3, iclass 5, count 2 2006.183.08:14:12.41#ibcon#about to read 4, iclass 5, count 2 2006.183.08:14:12.41#ibcon#read 4, iclass 5, count 2 2006.183.08:14:12.41#ibcon#about to read 5, iclass 5, count 2 2006.183.08:14:12.41#ibcon#read 5, iclass 5, count 2 2006.183.08:14:12.41#ibcon#about to read 6, iclass 5, count 2 2006.183.08:14:12.41#ibcon#read 6, iclass 5, count 2 2006.183.08:14:12.41#ibcon#end of sib2, iclass 5, count 2 2006.183.08:14:12.41#ibcon#*after write, iclass 5, count 2 2006.183.08:14:12.41#ibcon#*before return 0, iclass 5, count 2 2006.183.08:14:12.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:12.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:14:12.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.08:14:12.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:14:12.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:12.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:12.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:12.53#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:14:12.53#ibcon#first serial, iclass 5, count 0 2006.183.08:14:12.53#ibcon#enter sib2, iclass 5, count 0 2006.183.08:14:12.53#ibcon#flushed, iclass 5, count 0 2006.183.08:14:12.53#ibcon#about to write, iclass 5, count 0 2006.183.08:14:12.53#ibcon#wrote, iclass 5, count 0 2006.183.08:14:12.53#ibcon#about to read 3, iclass 5, count 0 2006.183.08:14:12.55#ibcon#read 3, iclass 5, count 0 2006.183.08:14:12.55#ibcon#about to read 4, iclass 5, count 0 2006.183.08:14:12.55#ibcon#read 4, iclass 5, count 0 2006.183.08:14:12.55#ibcon#about to read 5, iclass 5, count 0 2006.183.08:14:12.55#ibcon#read 5, iclass 5, count 0 2006.183.08:14:12.55#ibcon#about to read 6, iclass 5, count 0 2006.183.08:14:12.55#ibcon#read 6, iclass 5, count 0 2006.183.08:14:12.55#ibcon#end of sib2, iclass 5, count 0 2006.183.08:14:12.55#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:14:12.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:14:12.55#ibcon#[27=USB\r\n] 2006.183.08:14:12.55#ibcon#*before write, iclass 5, count 0 2006.183.08:14:12.55#ibcon#enter sib2, iclass 5, count 0 2006.183.08:14:12.55#ibcon#flushed, iclass 5, count 0 2006.183.08:14:12.55#ibcon#about to write, iclass 5, count 0 2006.183.08:14:12.55#ibcon#wrote, iclass 5, count 0 2006.183.08:14:12.55#ibcon#about to read 3, iclass 5, count 0 2006.183.08:14:12.58#ibcon#read 3, iclass 5, count 0 2006.183.08:14:12.58#ibcon#about to read 4, iclass 5, count 0 2006.183.08:14:12.58#ibcon#read 4, iclass 5, count 0 2006.183.08:14:12.58#ibcon#about to read 5, iclass 5, count 0 2006.183.08:14:12.58#ibcon#read 5, iclass 5, count 0 2006.183.08:14:12.58#ibcon#about to read 6, iclass 5, count 0 2006.183.08:14:12.58#ibcon#read 6, iclass 5, count 0 2006.183.08:14:12.58#ibcon#end of sib2, iclass 5, count 0 2006.183.08:14:12.58#ibcon#*after write, iclass 5, count 0 2006.183.08:14:12.58#ibcon#*before return 0, iclass 5, count 0 2006.183.08:14:12.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:12.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:14:12.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:14:12.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:14:12.58$vc4f8/vabw=wide 2006.183.08:14:12.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.08:14:12.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.08:14:12.58#ibcon#ireg 8 cls_cnt 0 2006.183.08:14:12.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:12.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:12.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:12.58#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:14:12.58#ibcon#first serial, iclass 7, count 0 2006.183.08:14:12.58#ibcon#enter sib2, iclass 7, count 0 2006.183.08:14:12.58#ibcon#flushed, iclass 7, count 0 2006.183.08:14:12.58#ibcon#about to write, iclass 7, count 0 2006.183.08:14:12.58#ibcon#wrote, iclass 7, count 0 2006.183.08:14:12.58#ibcon#about to read 3, iclass 7, count 0 2006.183.08:14:12.60#ibcon#read 3, iclass 7, count 0 2006.183.08:14:12.60#ibcon#about to read 4, iclass 7, count 0 2006.183.08:14:12.60#ibcon#read 4, iclass 7, count 0 2006.183.08:14:12.60#ibcon#about to read 5, iclass 7, count 0 2006.183.08:14:12.60#ibcon#read 5, iclass 7, count 0 2006.183.08:14:12.60#ibcon#about to read 6, iclass 7, count 0 2006.183.08:14:12.60#ibcon#read 6, iclass 7, count 0 2006.183.08:14:12.60#ibcon#end of sib2, iclass 7, count 0 2006.183.08:14:12.60#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:14:12.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:14:12.60#ibcon#[25=BW32\r\n] 2006.183.08:14:12.60#ibcon#*before write, iclass 7, count 0 2006.183.08:14:12.60#ibcon#enter sib2, iclass 7, count 0 2006.183.08:14:12.60#ibcon#flushed, iclass 7, count 0 2006.183.08:14:12.60#ibcon#about to write, iclass 7, count 0 2006.183.08:14:12.60#ibcon#wrote, iclass 7, count 0 2006.183.08:14:12.60#ibcon#about to read 3, iclass 7, count 0 2006.183.08:14:12.63#ibcon#read 3, iclass 7, count 0 2006.183.08:14:12.63#ibcon#about to read 4, iclass 7, count 0 2006.183.08:14:12.63#ibcon#read 4, iclass 7, count 0 2006.183.08:14:12.63#ibcon#about to read 5, iclass 7, count 0 2006.183.08:14:12.63#ibcon#read 5, iclass 7, count 0 2006.183.08:14:12.63#ibcon#about to read 6, iclass 7, count 0 2006.183.08:14:12.63#ibcon#read 6, iclass 7, count 0 2006.183.08:14:12.63#ibcon#end of sib2, iclass 7, count 0 2006.183.08:14:12.63#ibcon#*after write, iclass 7, count 0 2006.183.08:14:12.63#ibcon#*before return 0, iclass 7, count 0 2006.183.08:14:12.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:12.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:14:12.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:14:12.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:14:12.63$vc4f8/vbbw=wide 2006.183.08:14:12.63#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:14:12.63#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:14:12.63#ibcon#ireg 8 cls_cnt 0 2006.183.08:14:12.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:14:12.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:14:12.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:14:12.70#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:14:12.70#ibcon#first serial, iclass 11, count 0 2006.183.08:14:12.70#ibcon#enter sib2, iclass 11, count 0 2006.183.08:14:12.70#ibcon#flushed, iclass 11, count 0 2006.183.08:14:12.70#ibcon#about to write, iclass 11, count 0 2006.183.08:14:12.70#ibcon#wrote, iclass 11, count 0 2006.183.08:14:12.70#ibcon#about to read 3, iclass 11, count 0 2006.183.08:14:12.72#ibcon#read 3, iclass 11, count 0 2006.183.08:14:12.72#ibcon#about to read 4, iclass 11, count 0 2006.183.08:14:12.72#ibcon#read 4, iclass 11, count 0 2006.183.08:14:12.72#ibcon#about to read 5, iclass 11, count 0 2006.183.08:14:12.72#ibcon#read 5, iclass 11, count 0 2006.183.08:14:12.72#ibcon#about to read 6, iclass 11, count 0 2006.183.08:14:12.72#ibcon#read 6, iclass 11, count 0 2006.183.08:14:12.72#ibcon#end of sib2, iclass 11, count 0 2006.183.08:14:12.72#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:14:12.72#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:14:12.72#ibcon#[27=BW32\r\n] 2006.183.08:14:12.72#ibcon#*before write, iclass 11, count 0 2006.183.08:14:12.72#ibcon#enter sib2, iclass 11, count 0 2006.183.08:14:12.72#ibcon#flushed, iclass 11, count 0 2006.183.08:14:12.72#ibcon#about to write, iclass 11, count 0 2006.183.08:14:12.72#ibcon#wrote, iclass 11, count 0 2006.183.08:14:12.72#ibcon#about to read 3, iclass 11, count 0 2006.183.08:14:12.75#ibcon#read 3, iclass 11, count 0 2006.183.08:14:12.75#ibcon#about to read 4, iclass 11, count 0 2006.183.08:14:12.75#ibcon#read 4, iclass 11, count 0 2006.183.08:14:12.75#ibcon#about to read 5, iclass 11, count 0 2006.183.08:14:12.75#ibcon#read 5, iclass 11, count 0 2006.183.08:14:12.75#ibcon#about to read 6, iclass 11, count 0 2006.183.08:14:12.75#ibcon#read 6, iclass 11, count 0 2006.183.08:14:12.75#ibcon#end of sib2, iclass 11, count 0 2006.183.08:14:12.75#ibcon#*after write, iclass 11, count 0 2006.183.08:14:12.75#ibcon#*before return 0, iclass 11, count 0 2006.183.08:14:12.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:14:12.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:14:12.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:14:12.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:14:12.75$4f8m12a/ifd4f 2006.183.08:14:12.75$ifd4f/lo= 2006.183.08:14:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:14:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:14:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:14:12.75$ifd4f/patch= 2006.183.08:14:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:14:12.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:14:12.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:14:12.76$4f8m12a/"form=m,16.000,1:2 2006.183.08:14:12.76$4f8m12a/"tpicd 2006.183.08:14:12.76$4f8m12a/echo=off 2006.183.08:14:12.76$4f8m12a/xlog=off 2006.183.08:14:12.76:!2006.183.08:14:40 2006.183.08:14:18.14#trakl#Source acquired 2006.183.08:14:19.14#flagr#flagr/antenna,acquired 2006.183.08:14:40.01:preob 2006.183.08:14:41.13/onsource/TRACKING 2006.183.08:14:41.13:!2006.183.08:14:50 2006.183.08:14:50.00:data_valid=on 2006.183.08:14:50.00:midob 2006.183.08:14:50.13/onsource/TRACKING 2006.183.08:14:50.13/wx/28.33,996.6,86 2006.183.08:14:50.28/cable/+6.4502E-03 2006.183.08:14:51.37/va/01,08,usb,yes,29,31 2006.183.08:14:51.37/va/02,07,usb,yes,30,31 2006.183.08:14:51.37/va/03,06,usb,yes,31,32 2006.183.08:14:51.37/va/04,07,usb,yes,31,33 2006.183.08:14:51.37/va/05,07,usb,yes,32,34 2006.183.08:14:51.37/va/06,06,usb,yes,31,31 2006.183.08:14:51.37/va/07,06,usb,yes,32,31 2006.183.08:14:51.37/va/08,07,usb,yes,30,29 2006.183.08:14:51.60/valo/01,532.99,yes,locked 2006.183.08:14:51.60/valo/02,572.99,yes,locked 2006.183.08:14:51.60/valo/03,672.99,yes,locked 2006.183.08:14:51.60/valo/04,832.99,yes,locked 2006.183.08:14:51.60/valo/05,652.99,yes,locked 2006.183.08:14:51.60/valo/06,772.99,yes,locked 2006.183.08:14:51.60/valo/07,832.99,yes,locked 2006.183.08:14:51.60/valo/08,852.99,yes,locked 2006.183.08:14:52.69/vb/01,04,usb,yes,29,28 2006.183.08:14:52.69/vb/02,04,usb,yes,31,33 2006.183.08:14:52.69/vb/03,04,usb,yes,28,31 2006.183.08:14:52.69/vb/04,04,usb,yes,28,29 2006.183.08:14:52.69/vb/05,04,usb,yes,27,31 2006.183.08:14:52.69/vb/06,04,usb,yes,28,31 2006.183.08:14:52.69/vb/07,04,usb,yes,30,30 2006.183.08:14:52.69/vb/08,04,usb,yes,28,31 2006.183.08:14:52.92/vblo/01,632.99,yes,locked 2006.183.08:14:52.92/vblo/02,640.99,yes,locked 2006.183.08:14:52.92/vblo/03,656.99,yes,locked 2006.183.08:14:52.92/vblo/04,712.99,yes,locked 2006.183.08:14:52.92/vblo/05,744.99,yes,locked 2006.183.08:14:52.92/vblo/06,752.99,yes,locked 2006.183.08:14:52.92/vblo/07,734.99,yes,locked 2006.183.08:14:52.92/vblo/08,744.99,yes,locked 2006.183.08:14:53.07/vabw/8 2006.183.08:14:53.22/vbbw/8 2006.183.08:14:53.31/xfe/off,on,15.2 2006.183.08:14:53.69/ifatt/23,28,28,28 2006.183.08:14:54.07/fmout-gps/S +3.36E-07 2006.183.08:14:54.12:!2006.183.08:15:50 2006.183.08:15:50.00:data_valid=off 2006.183.08:15:50.01:postob 2006.183.08:15:50.16/cable/+6.4507E-03 2006.183.08:15:50.17/wx/28.33,996.6,86 2006.183.08:15:51.07/fmout-gps/S +3.36E-07 2006.183.08:15:51.08:scan_name=183-0816,k06183,60 2006.183.08:15:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.183.08:15:51.13#flagr#flagr/antenna,new-source 2006.183.08:15:52.13:checkk5 2006.183.08:15:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:15:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:15:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:15:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:15:54.02/chk_obsdata//k5ts1/T1830814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:15:54.39/chk_obsdata//k5ts2/T1830814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:15:54.76/chk_obsdata//k5ts3/T1830814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:15:55.13/chk_obsdata//k5ts4/T1830814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:15:55.82/k5log//k5ts1_log_newline 2006.183.08:15:56.50/k5log//k5ts2_log_newline 2006.183.08:15:57.19/k5log//k5ts3_log_newline 2006.183.08:15:57.89/k5log//k5ts4_log_newline 2006.183.08:15:57.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:15:57.91:4f8m12a=2 2006.183.08:15:57.91$4f8m12a/echo=on 2006.183.08:15:57.91$4f8m12a/pcalon 2006.183.08:15:57.91$pcalon/"no phase cal control is implemented here 2006.183.08:15:57.91$4f8m12a/"tpicd=stop 2006.183.08:15:57.91$4f8m12a/vc4f8 2006.183.08:15:57.91$vc4f8/valo=1,532.99 2006.183.08:15:57.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:15:57.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:15:57.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:15:57.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:15:57.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:15:57.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:15:57.92#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:15:57.92#ibcon#first serial, iclass 18, count 0 2006.183.08:15:57.92#ibcon#enter sib2, iclass 18, count 0 2006.183.08:15:57.92#ibcon#flushed, iclass 18, count 0 2006.183.08:15:57.92#ibcon#about to write, iclass 18, count 0 2006.183.08:15:57.92#ibcon#wrote, iclass 18, count 0 2006.183.08:15:57.92#ibcon#about to read 3, iclass 18, count 0 2006.183.08:15:57.96#ibcon#read 3, iclass 18, count 0 2006.183.08:15:57.96#ibcon#about to read 4, iclass 18, count 0 2006.183.08:15:57.96#ibcon#read 4, iclass 18, count 0 2006.183.08:15:57.96#ibcon#about to read 5, iclass 18, count 0 2006.183.08:15:57.96#ibcon#read 5, iclass 18, count 0 2006.183.08:15:57.96#ibcon#about to read 6, iclass 18, count 0 2006.183.08:15:57.96#ibcon#read 6, iclass 18, count 0 2006.183.08:15:57.96#ibcon#end of sib2, iclass 18, count 0 2006.183.08:15:57.96#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:15:57.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:15:57.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:15:57.96#ibcon#*before write, iclass 18, count 0 2006.183.08:15:57.96#ibcon#enter sib2, iclass 18, count 0 2006.183.08:15:57.96#ibcon#flushed, iclass 18, count 0 2006.183.08:15:57.96#ibcon#about to write, iclass 18, count 0 2006.183.08:15:57.96#ibcon#wrote, iclass 18, count 0 2006.183.08:15:57.96#ibcon#about to read 3, iclass 18, count 0 2006.183.08:15:58.00#ibcon#read 3, iclass 18, count 0 2006.183.08:15:58.00#ibcon#about to read 4, iclass 18, count 0 2006.183.08:15:58.00#ibcon#read 4, iclass 18, count 0 2006.183.08:15:58.00#ibcon#about to read 5, iclass 18, count 0 2006.183.08:15:58.00#ibcon#read 5, iclass 18, count 0 2006.183.08:15:58.00#ibcon#about to read 6, iclass 18, count 0 2006.183.08:15:58.00#ibcon#read 6, iclass 18, count 0 2006.183.08:15:58.00#ibcon#end of sib2, iclass 18, count 0 2006.183.08:15:58.00#ibcon#*after write, iclass 18, count 0 2006.183.08:15:58.00#ibcon#*before return 0, iclass 18, count 0 2006.183.08:15:58.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:15:58.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:15:58.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:15:58.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:15:58.00$vc4f8/va=1,8 2006.183.08:15:58.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.08:15:58.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.08:15:58.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:15:58.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:15:58.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:15:58.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:15:58.00#ibcon#enter wrdev, iclass 20, count 2 2006.183.08:15:58.00#ibcon#first serial, iclass 20, count 2 2006.183.08:15:58.00#ibcon#enter sib2, iclass 20, count 2 2006.183.08:15:58.00#ibcon#flushed, iclass 20, count 2 2006.183.08:15:58.00#ibcon#about to write, iclass 20, count 2 2006.183.08:15:58.00#ibcon#wrote, iclass 20, count 2 2006.183.08:15:58.00#ibcon#about to read 3, iclass 20, count 2 2006.183.08:15:58.02#ibcon#read 3, iclass 20, count 2 2006.183.08:15:58.02#ibcon#about to read 4, iclass 20, count 2 2006.183.08:15:58.02#ibcon#read 4, iclass 20, count 2 2006.183.08:15:58.02#ibcon#about to read 5, iclass 20, count 2 2006.183.08:15:58.02#ibcon#read 5, iclass 20, count 2 2006.183.08:15:58.02#ibcon#about to read 6, iclass 20, count 2 2006.183.08:15:58.02#ibcon#read 6, iclass 20, count 2 2006.183.08:15:58.02#ibcon#end of sib2, iclass 20, count 2 2006.183.08:15:58.02#ibcon#*mode == 0, iclass 20, count 2 2006.183.08:15:58.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.08:15:58.02#ibcon#[25=AT01-08\r\n] 2006.183.08:15:58.02#ibcon#*before write, iclass 20, count 2 2006.183.08:15:58.02#ibcon#enter sib2, iclass 20, count 2 2006.183.08:15:58.02#ibcon#flushed, iclass 20, count 2 2006.183.08:15:58.02#ibcon#about to write, iclass 20, count 2 2006.183.08:15:58.02#ibcon#wrote, iclass 20, count 2 2006.183.08:15:58.02#ibcon#about to read 3, iclass 20, count 2 2006.183.08:15:58.06#ibcon#read 3, iclass 20, count 2 2006.183.08:15:58.06#ibcon#about to read 4, iclass 20, count 2 2006.183.08:15:58.06#ibcon#read 4, iclass 20, count 2 2006.183.08:15:58.06#ibcon#about to read 5, iclass 20, count 2 2006.183.08:15:58.06#ibcon#read 5, iclass 20, count 2 2006.183.08:15:58.06#ibcon#about to read 6, iclass 20, count 2 2006.183.08:15:58.06#ibcon#read 6, iclass 20, count 2 2006.183.08:15:58.06#ibcon#end of sib2, iclass 20, count 2 2006.183.08:15:58.06#ibcon#*after write, iclass 20, count 2 2006.183.08:15:58.06#ibcon#*before return 0, iclass 20, count 2 2006.183.08:15:58.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:15:58.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:15:58.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.08:15:58.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:15:58.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:15:58.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:15:58.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:15:58.17#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:15:58.17#ibcon#first serial, iclass 20, count 0 2006.183.08:15:58.17#ibcon#enter sib2, iclass 20, count 0 2006.183.08:15:58.17#ibcon#flushed, iclass 20, count 0 2006.183.08:15:58.17#ibcon#about to write, iclass 20, count 0 2006.183.08:15:58.17#ibcon#wrote, iclass 20, count 0 2006.183.08:15:58.17#ibcon#about to read 3, iclass 20, count 0 2006.183.08:15:58.19#ibcon#read 3, iclass 20, count 0 2006.183.08:15:58.19#ibcon#about to read 4, iclass 20, count 0 2006.183.08:15:58.19#ibcon#read 4, iclass 20, count 0 2006.183.08:15:58.19#ibcon#about to read 5, iclass 20, count 0 2006.183.08:15:58.19#ibcon#read 5, iclass 20, count 0 2006.183.08:15:58.19#ibcon#about to read 6, iclass 20, count 0 2006.183.08:15:58.19#ibcon#read 6, iclass 20, count 0 2006.183.08:15:58.19#ibcon#end of sib2, iclass 20, count 0 2006.183.08:15:58.19#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:15:58.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:15:58.19#ibcon#[25=USB\r\n] 2006.183.08:15:58.19#ibcon#*before write, iclass 20, count 0 2006.183.08:15:58.19#ibcon#enter sib2, iclass 20, count 0 2006.183.08:15:58.19#ibcon#flushed, iclass 20, count 0 2006.183.08:15:58.19#ibcon#about to write, iclass 20, count 0 2006.183.08:15:58.19#ibcon#wrote, iclass 20, count 0 2006.183.08:15:58.19#ibcon#about to read 3, iclass 20, count 0 2006.183.08:15:58.22#ibcon#read 3, iclass 20, count 0 2006.183.08:15:58.22#ibcon#about to read 4, iclass 20, count 0 2006.183.08:15:58.22#ibcon#read 4, iclass 20, count 0 2006.183.08:15:58.22#ibcon#about to read 5, iclass 20, count 0 2006.183.08:15:58.22#ibcon#read 5, iclass 20, count 0 2006.183.08:15:58.22#ibcon#about to read 6, iclass 20, count 0 2006.183.08:15:58.22#ibcon#read 6, iclass 20, count 0 2006.183.08:15:58.22#ibcon#end of sib2, iclass 20, count 0 2006.183.08:15:58.22#ibcon#*after write, iclass 20, count 0 2006.183.08:15:58.22#ibcon#*before return 0, iclass 20, count 0 2006.183.08:15:58.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:15:58.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:15:58.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:15:58.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:15:58.22$vc4f8/valo=2,572.99 2006.183.08:15:58.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.08:15:58.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.08:15:58.22#ibcon#ireg 17 cls_cnt 0 2006.183.08:15:58.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:15:58.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:15:58.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:15:58.22#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:15:58.22#ibcon#first serial, iclass 22, count 0 2006.183.08:15:58.22#ibcon#enter sib2, iclass 22, count 0 2006.183.08:15:58.22#ibcon#flushed, iclass 22, count 0 2006.183.08:15:58.22#ibcon#about to write, iclass 22, count 0 2006.183.08:15:58.22#ibcon#wrote, iclass 22, count 0 2006.183.08:15:58.22#ibcon#about to read 3, iclass 22, count 0 2006.183.08:15:58.25#ibcon#read 3, iclass 22, count 0 2006.183.08:15:58.25#ibcon#about to read 4, iclass 22, count 0 2006.183.08:15:58.25#ibcon#read 4, iclass 22, count 0 2006.183.08:15:58.25#ibcon#about to read 5, iclass 22, count 0 2006.183.08:15:58.25#ibcon#read 5, iclass 22, count 0 2006.183.08:15:58.25#ibcon#about to read 6, iclass 22, count 0 2006.183.08:15:58.25#ibcon#read 6, iclass 22, count 0 2006.183.08:15:58.25#ibcon#end of sib2, iclass 22, count 0 2006.183.08:15:58.25#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:15:58.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:15:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:15:58.25#ibcon#*before write, iclass 22, count 0 2006.183.08:15:58.25#ibcon#enter sib2, iclass 22, count 0 2006.183.08:15:58.25#ibcon#flushed, iclass 22, count 0 2006.183.08:15:58.25#ibcon#about to write, iclass 22, count 0 2006.183.08:15:58.25#ibcon#wrote, iclass 22, count 0 2006.183.08:15:58.25#ibcon#about to read 3, iclass 22, count 0 2006.183.08:15:58.29#ibcon#read 3, iclass 22, count 0 2006.183.08:15:58.29#ibcon#about to read 4, iclass 22, count 0 2006.183.08:15:58.29#ibcon#read 4, iclass 22, count 0 2006.183.08:15:58.29#ibcon#about to read 5, iclass 22, count 0 2006.183.08:15:58.29#ibcon#read 5, iclass 22, count 0 2006.183.08:15:58.29#ibcon#about to read 6, iclass 22, count 0 2006.183.08:15:58.29#ibcon#read 6, iclass 22, count 0 2006.183.08:15:58.29#ibcon#end of sib2, iclass 22, count 0 2006.183.08:15:58.29#ibcon#*after write, iclass 22, count 0 2006.183.08:15:58.29#ibcon#*before return 0, iclass 22, count 0 2006.183.08:15:58.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:15:58.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:15:58.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:15:58.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:15:58.29$vc4f8/va=2,7 2006.183.08:15:58.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.08:15:58.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.08:15:58.29#ibcon#ireg 11 cls_cnt 2 2006.183.08:15:58.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:15:58.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:15:58.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:15:58.35#ibcon#enter wrdev, iclass 24, count 2 2006.183.08:15:58.35#ibcon#first serial, iclass 24, count 2 2006.183.08:15:58.35#ibcon#enter sib2, iclass 24, count 2 2006.183.08:15:58.35#ibcon#flushed, iclass 24, count 2 2006.183.08:15:58.35#ibcon#about to write, iclass 24, count 2 2006.183.08:15:58.35#ibcon#wrote, iclass 24, count 2 2006.183.08:15:58.35#ibcon#about to read 3, iclass 24, count 2 2006.183.08:15:58.36#ibcon#read 3, iclass 24, count 2 2006.183.08:15:58.36#ibcon#about to read 4, iclass 24, count 2 2006.183.08:15:58.36#ibcon#read 4, iclass 24, count 2 2006.183.08:15:58.36#ibcon#about to read 5, iclass 24, count 2 2006.183.08:15:58.36#ibcon#read 5, iclass 24, count 2 2006.183.08:15:58.36#ibcon#about to read 6, iclass 24, count 2 2006.183.08:15:58.36#ibcon#read 6, iclass 24, count 2 2006.183.08:15:58.36#ibcon#end of sib2, iclass 24, count 2 2006.183.08:15:58.36#ibcon#*mode == 0, iclass 24, count 2 2006.183.08:15:58.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.08:15:58.36#ibcon#[25=AT02-07\r\n] 2006.183.08:15:58.36#ibcon#*before write, iclass 24, count 2 2006.183.08:15:58.36#ibcon#enter sib2, iclass 24, count 2 2006.183.08:15:58.36#ibcon#flushed, iclass 24, count 2 2006.183.08:15:58.36#ibcon#about to write, iclass 24, count 2 2006.183.08:15:58.36#ibcon#wrote, iclass 24, count 2 2006.183.08:15:58.36#ibcon#about to read 3, iclass 24, count 2 2006.183.08:15:58.39#ibcon#read 3, iclass 24, count 2 2006.183.08:15:58.39#ibcon#about to read 4, iclass 24, count 2 2006.183.08:15:58.39#ibcon#read 4, iclass 24, count 2 2006.183.08:15:58.39#ibcon#about to read 5, iclass 24, count 2 2006.183.08:15:58.39#ibcon#read 5, iclass 24, count 2 2006.183.08:15:58.39#ibcon#about to read 6, iclass 24, count 2 2006.183.08:15:58.39#ibcon#read 6, iclass 24, count 2 2006.183.08:15:58.39#ibcon#end of sib2, iclass 24, count 2 2006.183.08:15:58.39#ibcon#*after write, iclass 24, count 2 2006.183.08:15:58.39#ibcon#*before return 0, iclass 24, count 2 2006.183.08:15:58.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:15:58.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:15:58.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.08:15:58.39#ibcon#ireg 7 cls_cnt 0 2006.183.08:15:58.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:15:58.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:15:58.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:15:58.51#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:15:58.51#ibcon#first serial, iclass 24, count 0 2006.183.08:15:58.51#ibcon#enter sib2, iclass 24, count 0 2006.183.08:15:58.51#ibcon#flushed, iclass 24, count 0 2006.183.08:15:58.51#ibcon#about to write, iclass 24, count 0 2006.183.08:15:58.51#ibcon#wrote, iclass 24, count 0 2006.183.08:15:58.51#ibcon#about to read 3, iclass 24, count 0 2006.183.08:15:58.53#ibcon#read 3, iclass 24, count 0 2006.183.08:15:58.53#ibcon#about to read 4, iclass 24, count 0 2006.183.08:15:58.53#ibcon#read 4, iclass 24, count 0 2006.183.08:15:58.53#ibcon#about to read 5, iclass 24, count 0 2006.183.08:15:58.53#ibcon#read 5, iclass 24, count 0 2006.183.08:15:58.53#ibcon#about to read 6, iclass 24, count 0 2006.183.08:15:58.53#ibcon#read 6, iclass 24, count 0 2006.183.08:15:58.53#ibcon#end of sib2, iclass 24, count 0 2006.183.08:15:58.53#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:15:58.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:15:58.53#ibcon#[25=USB\r\n] 2006.183.08:15:58.53#ibcon#*before write, iclass 24, count 0 2006.183.08:15:58.53#ibcon#enter sib2, iclass 24, count 0 2006.183.08:15:58.53#ibcon#flushed, iclass 24, count 0 2006.183.08:15:58.53#ibcon#about to write, iclass 24, count 0 2006.183.08:15:58.53#ibcon#wrote, iclass 24, count 0 2006.183.08:15:58.53#ibcon#about to read 3, iclass 24, count 0 2006.183.08:15:58.56#ibcon#read 3, iclass 24, count 0 2006.183.08:15:58.56#ibcon#about to read 4, iclass 24, count 0 2006.183.08:15:58.56#ibcon#read 4, iclass 24, count 0 2006.183.08:15:58.56#ibcon#about to read 5, iclass 24, count 0 2006.183.08:15:58.56#ibcon#read 5, iclass 24, count 0 2006.183.08:15:58.56#ibcon#about to read 6, iclass 24, count 0 2006.183.08:15:58.56#ibcon#read 6, iclass 24, count 0 2006.183.08:15:58.56#ibcon#end of sib2, iclass 24, count 0 2006.183.08:15:58.56#ibcon#*after write, iclass 24, count 0 2006.183.08:15:58.56#ibcon#*before return 0, iclass 24, count 0 2006.183.08:15:58.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:15:58.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:15:58.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:15:58.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:15:58.56$vc4f8/valo=3,672.99 2006.183.08:15:58.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.08:15:58.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.08:15:58.56#ibcon#ireg 17 cls_cnt 0 2006.183.08:15:58.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:15:58.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:15:58.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:15:58.56#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:15:58.56#ibcon#first serial, iclass 26, count 0 2006.183.08:15:58.56#ibcon#enter sib2, iclass 26, count 0 2006.183.08:15:58.56#ibcon#flushed, iclass 26, count 0 2006.183.08:15:58.56#ibcon#about to write, iclass 26, count 0 2006.183.08:15:58.56#ibcon#wrote, iclass 26, count 0 2006.183.08:15:58.56#ibcon#about to read 3, iclass 26, count 0 2006.183.08:15:58.59#ibcon#read 3, iclass 26, count 0 2006.183.08:15:58.59#ibcon#about to read 4, iclass 26, count 0 2006.183.08:15:58.59#ibcon#read 4, iclass 26, count 0 2006.183.08:15:58.59#ibcon#about to read 5, iclass 26, count 0 2006.183.08:15:58.59#ibcon#read 5, iclass 26, count 0 2006.183.08:15:58.59#ibcon#about to read 6, iclass 26, count 0 2006.183.08:15:58.59#ibcon#read 6, iclass 26, count 0 2006.183.08:15:58.59#ibcon#end of sib2, iclass 26, count 0 2006.183.08:15:58.59#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:15:58.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:15:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:15:58.59#ibcon#*before write, iclass 26, count 0 2006.183.08:15:58.59#ibcon#enter sib2, iclass 26, count 0 2006.183.08:15:58.59#ibcon#flushed, iclass 26, count 0 2006.183.08:15:58.59#ibcon#about to write, iclass 26, count 0 2006.183.08:15:58.59#ibcon#wrote, iclass 26, count 0 2006.183.08:15:58.59#ibcon#about to read 3, iclass 26, count 0 2006.183.08:15:58.63#ibcon#read 3, iclass 26, count 0 2006.183.08:15:58.63#ibcon#about to read 4, iclass 26, count 0 2006.183.08:15:58.63#ibcon#read 4, iclass 26, count 0 2006.183.08:15:58.63#ibcon#about to read 5, iclass 26, count 0 2006.183.08:15:58.63#ibcon#read 5, iclass 26, count 0 2006.183.08:15:58.63#ibcon#about to read 6, iclass 26, count 0 2006.183.08:15:58.63#ibcon#read 6, iclass 26, count 0 2006.183.08:15:58.63#ibcon#end of sib2, iclass 26, count 0 2006.183.08:15:58.63#ibcon#*after write, iclass 26, count 0 2006.183.08:15:58.63#ibcon#*before return 0, iclass 26, count 0 2006.183.08:15:58.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:15:58.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:15:58.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:15:58.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:15:58.63$vc4f8/va=3,6 2006.183.08:15:58.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.08:15:58.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.08:15:58.63#ibcon#ireg 11 cls_cnt 2 2006.183.08:15:58.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:15:58.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:15:58.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:15:58.68#ibcon#enter wrdev, iclass 28, count 2 2006.183.08:15:58.69#ibcon#first serial, iclass 28, count 2 2006.183.08:15:58.69#ibcon#enter sib2, iclass 28, count 2 2006.183.08:15:58.69#ibcon#flushed, iclass 28, count 2 2006.183.08:15:58.69#ibcon#about to write, iclass 28, count 2 2006.183.08:15:58.69#ibcon#wrote, iclass 28, count 2 2006.183.08:15:58.69#ibcon#about to read 3, iclass 28, count 2 2006.183.08:15:58.70#ibcon#read 3, iclass 28, count 2 2006.183.08:15:58.70#ibcon#about to read 4, iclass 28, count 2 2006.183.08:15:58.70#ibcon#read 4, iclass 28, count 2 2006.183.08:15:58.70#ibcon#about to read 5, iclass 28, count 2 2006.183.08:15:58.70#ibcon#read 5, iclass 28, count 2 2006.183.08:15:58.70#ibcon#about to read 6, iclass 28, count 2 2006.183.08:15:58.70#ibcon#read 6, iclass 28, count 2 2006.183.08:15:58.70#ibcon#end of sib2, iclass 28, count 2 2006.183.08:15:58.70#ibcon#*mode == 0, iclass 28, count 2 2006.183.08:15:58.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.08:15:58.70#ibcon#[25=AT03-06\r\n] 2006.183.08:15:58.70#ibcon#*before write, iclass 28, count 2 2006.183.08:15:58.70#ibcon#enter sib2, iclass 28, count 2 2006.183.08:15:58.70#ibcon#flushed, iclass 28, count 2 2006.183.08:15:58.70#ibcon#about to write, iclass 28, count 2 2006.183.08:15:58.70#ibcon#wrote, iclass 28, count 2 2006.183.08:15:58.70#ibcon#about to read 3, iclass 28, count 2 2006.183.08:15:58.73#ibcon#read 3, iclass 28, count 2 2006.183.08:15:58.73#ibcon#about to read 4, iclass 28, count 2 2006.183.08:15:58.73#ibcon#read 4, iclass 28, count 2 2006.183.08:15:58.73#ibcon#about to read 5, iclass 28, count 2 2006.183.08:15:58.73#ibcon#read 5, iclass 28, count 2 2006.183.08:15:58.73#ibcon#about to read 6, iclass 28, count 2 2006.183.08:15:58.73#ibcon#read 6, iclass 28, count 2 2006.183.08:15:58.73#ibcon#end of sib2, iclass 28, count 2 2006.183.08:15:58.73#ibcon#*after write, iclass 28, count 2 2006.183.08:15:58.73#ibcon#*before return 0, iclass 28, count 2 2006.183.08:15:58.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:15:58.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:15:58.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.08:15:58.73#ibcon#ireg 7 cls_cnt 0 2006.183.08:15:58.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:15:58.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:15:58.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:15:58.85#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:15:58.85#ibcon#first serial, iclass 28, count 0 2006.183.08:15:58.85#ibcon#enter sib2, iclass 28, count 0 2006.183.08:15:58.85#ibcon#flushed, iclass 28, count 0 2006.183.08:15:58.85#ibcon#about to write, iclass 28, count 0 2006.183.08:15:58.85#ibcon#wrote, iclass 28, count 0 2006.183.08:15:58.85#ibcon#about to read 3, iclass 28, count 0 2006.183.08:15:58.87#ibcon#read 3, iclass 28, count 0 2006.183.08:15:58.87#ibcon#about to read 4, iclass 28, count 0 2006.183.08:15:58.87#ibcon#read 4, iclass 28, count 0 2006.183.08:15:58.87#ibcon#about to read 5, iclass 28, count 0 2006.183.08:15:58.87#ibcon#read 5, iclass 28, count 0 2006.183.08:15:58.87#ibcon#about to read 6, iclass 28, count 0 2006.183.08:15:58.87#ibcon#read 6, iclass 28, count 0 2006.183.08:15:58.87#ibcon#end of sib2, iclass 28, count 0 2006.183.08:15:58.87#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:15:58.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:15:58.87#ibcon#[25=USB\r\n] 2006.183.08:15:58.87#ibcon#*before write, iclass 28, count 0 2006.183.08:15:58.87#ibcon#enter sib2, iclass 28, count 0 2006.183.08:15:58.87#ibcon#flushed, iclass 28, count 0 2006.183.08:15:58.87#ibcon#about to write, iclass 28, count 0 2006.183.08:15:58.87#ibcon#wrote, iclass 28, count 0 2006.183.08:15:58.87#ibcon#about to read 3, iclass 28, count 0 2006.183.08:15:58.90#ibcon#read 3, iclass 28, count 0 2006.183.08:15:58.90#ibcon#about to read 4, iclass 28, count 0 2006.183.08:15:58.90#ibcon#read 4, iclass 28, count 0 2006.183.08:15:58.90#ibcon#about to read 5, iclass 28, count 0 2006.183.08:15:58.90#ibcon#read 5, iclass 28, count 0 2006.183.08:15:58.90#ibcon#about to read 6, iclass 28, count 0 2006.183.08:15:58.90#ibcon#read 6, iclass 28, count 0 2006.183.08:15:58.90#ibcon#end of sib2, iclass 28, count 0 2006.183.08:15:58.90#ibcon#*after write, iclass 28, count 0 2006.183.08:15:58.90#ibcon#*before return 0, iclass 28, count 0 2006.183.08:15:58.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:15:58.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:15:58.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:15:58.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:15:58.90$vc4f8/valo=4,832.99 2006.183.08:15:58.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:15:58.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:15:58.90#ibcon#ireg 17 cls_cnt 0 2006.183.08:15:58.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:15:58.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:15:58.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:15:58.90#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:15:58.90#ibcon#first serial, iclass 30, count 0 2006.183.08:15:58.90#ibcon#enter sib2, iclass 30, count 0 2006.183.08:15:58.90#ibcon#flushed, iclass 30, count 0 2006.183.08:15:58.90#ibcon#about to write, iclass 30, count 0 2006.183.08:15:58.90#ibcon#wrote, iclass 30, count 0 2006.183.08:15:58.90#ibcon#about to read 3, iclass 30, count 0 2006.183.08:15:58.93#ibcon#read 3, iclass 30, count 0 2006.183.08:15:58.93#ibcon#about to read 4, iclass 30, count 0 2006.183.08:15:58.93#ibcon#read 4, iclass 30, count 0 2006.183.08:15:58.93#ibcon#about to read 5, iclass 30, count 0 2006.183.08:15:58.93#ibcon#read 5, iclass 30, count 0 2006.183.08:15:58.93#ibcon#about to read 6, iclass 30, count 0 2006.183.08:15:58.93#ibcon#read 6, iclass 30, count 0 2006.183.08:15:58.93#ibcon#end of sib2, iclass 30, count 0 2006.183.08:15:58.93#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:15:58.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:15:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:15:58.93#ibcon#*before write, iclass 30, count 0 2006.183.08:15:58.93#ibcon#enter sib2, iclass 30, count 0 2006.183.08:15:58.93#ibcon#flushed, iclass 30, count 0 2006.183.08:15:58.93#ibcon#about to write, iclass 30, count 0 2006.183.08:15:58.93#ibcon#wrote, iclass 30, count 0 2006.183.08:15:58.93#ibcon#about to read 3, iclass 30, count 0 2006.183.08:15:58.97#ibcon#read 3, iclass 30, count 0 2006.183.08:15:58.97#ibcon#about to read 4, iclass 30, count 0 2006.183.08:15:58.97#ibcon#read 4, iclass 30, count 0 2006.183.08:15:58.97#ibcon#about to read 5, iclass 30, count 0 2006.183.08:15:58.97#ibcon#read 5, iclass 30, count 0 2006.183.08:15:58.97#ibcon#about to read 6, iclass 30, count 0 2006.183.08:15:58.97#ibcon#read 6, iclass 30, count 0 2006.183.08:15:58.97#ibcon#end of sib2, iclass 30, count 0 2006.183.08:15:58.97#ibcon#*after write, iclass 30, count 0 2006.183.08:15:58.97#ibcon#*before return 0, iclass 30, count 0 2006.183.08:15:58.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:15:58.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:15:58.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:15:58.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:15:58.97$vc4f8/va=4,7 2006.183.08:15:58.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.08:15:58.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.08:15:58.97#ibcon#ireg 11 cls_cnt 2 2006.183.08:15:58.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:15:59.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:15:59.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:15:59.02#ibcon#enter wrdev, iclass 32, count 2 2006.183.08:15:59.02#ibcon#first serial, iclass 32, count 2 2006.183.08:15:59.02#ibcon#enter sib2, iclass 32, count 2 2006.183.08:15:59.02#ibcon#flushed, iclass 32, count 2 2006.183.08:15:59.02#ibcon#about to write, iclass 32, count 2 2006.183.08:15:59.02#ibcon#wrote, iclass 32, count 2 2006.183.08:15:59.02#ibcon#about to read 3, iclass 32, count 2 2006.183.08:15:59.04#ibcon#read 3, iclass 32, count 2 2006.183.08:15:59.04#ibcon#about to read 4, iclass 32, count 2 2006.183.08:15:59.04#ibcon#read 4, iclass 32, count 2 2006.183.08:15:59.04#ibcon#about to read 5, iclass 32, count 2 2006.183.08:15:59.04#ibcon#read 5, iclass 32, count 2 2006.183.08:15:59.04#ibcon#about to read 6, iclass 32, count 2 2006.183.08:15:59.04#ibcon#read 6, iclass 32, count 2 2006.183.08:15:59.04#ibcon#end of sib2, iclass 32, count 2 2006.183.08:15:59.04#ibcon#*mode == 0, iclass 32, count 2 2006.183.08:15:59.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.08:15:59.04#ibcon#[25=AT04-07\r\n] 2006.183.08:15:59.04#ibcon#*before write, iclass 32, count 2 2006.183.08:15:59.04#ibcon#enter sib2, iclass 32, count 2 2006.183.08:15:59.04#ibcon#flushed, iclass 32, count 2 2006.183.08:15:59.04#ibcon#about to write, iclass 32, count 2 2006.183.08:15:59.04#ibcon#wrote, iclass 32, count 2 2006.183.08:15:59.04#ibcon#about to read 3, iclass 32, count 2 2006.183.08:15:59.07#ibcon#read 3, iclass 32, count 2 2006.183.08:15:59.07#ibcon#about to read 4, iclass 32, count 2 2006.183.08:15:59.07#ibcon#read 4, iclass 32, count 2 2006.183.08:15:59.07#ibcon#about to read 5, iclass 32, count 2 2006.183.08:15:59.07#ibcon#read 5, iclass 32, count 2 2006.183.08:15:59.07#ibcon#about to read 6, iclass 32, count 2 2006.183.08:15:59.07#ibcon#read 6, iclass 32, count 2 2006.183.08:15:59.07#ibcon#end of sib2, iclass 32, count 2 2006.183.08:15:59.07#ibcon#*after write, iclass 32, count 2 2006.183.08:15:59.07#ibcon#*before return 0, iclass 32, count 2 2006.183.08:15:59.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:15:59.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:15:59.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.08:15:59.07#ibcon#ireg 7 cls_cnt 0 2006.183.08:15:59.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:15:59.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:15:59.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:15:59.19#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:15:59.19#ibcon#first serial, iclass 32, count 0 2006.183.08:15:59.19#ibcon#enter sib2, iclass 32, count 0 2006.183.08:15:59.19#ibcon#flushed, iclass 32, count 0 2006.183.08:15:59.19#ibcon#about to write, iclass 32, count 0 2006.183.08:15:59.19#ibcon#wrote, iclass 32, count 0 2006.183.08:15:59.19#ibcon#about to read 3, iclass 32, count 0 2006.183.08:15:59.21#ibcon#read 3, iclass 32, count 0 2006.183.08:15:59.21#ibcon#about to read 4, iclass 32, count 0 2006.183.08:15:59.21#ibcon#read 4, iclass 32, count 0 2006.183.08:15:59.21#ibcon#about to read 5, iclass 32, count 0 2006.183.08:15:59.21#ibcon#read 5, iclass 32, count 0 2006.183.08:15:59.21#ibcon#about to read 6, iclass 32, count 0 2006.183.08:15:59.21#ibcon#read 6, iclass 32, count 0 2006.183.08:15:59.21#ibcon#end of sib2, iclass 32, count 0 2006.183.08:15:59.21#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:15:59.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:15:59.21#ibcon#[25=USB\r\n] 2006.183.08:15:59.21#ibcon#*before write, iclass 32, count 0 2006.183.08:15:59.21#ibcon#enter sib2, iclass 32, count 0 2006.183.08:15:59.21#ibcon#flushed, iclass 32, count 0 2006.183.08:15:59.21#ibcon#about to write, iclass 32, count 0 2006.183.08:15:59.21#ibcon#wrote, iclass 32, count 0 2006.183.08:15:59.21#ibcon#about to read 3, iclass 32, count 0 2006.183.08:15:59.24#ibcon#read 3, iclass 32, count 0 2006.183.08:15:59.24#ibcon#about to read 4, iclass 32, count 0 2006.183.08:15:59.24#ibcon#read 4, iclass 32, count 0 2006.183.08:15:59.24#ibcon#about to read 5, iclass 32, count 0 2006.183.08:15:59.24#ibcon#read 5, iclass 32, count 0 2006.183.08:15:59.24#ibcon#about to read 6, iclass 32, count 0 2006.183.08:15:59.24#ibcon#read 6, iclass 32, count 0 2006.183.08:15:59.24#ibcon#end of sib2, iclass 32, count 0 2006.183.08:15:59.24#ibcon#*after write, iclass 32, count 0 2006.183.08:15:59.24#ibcon#*before return 0, iclass 32, count 0 2006.183.08:15:59.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:15:59.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:15:59.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:15:59.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:15:59.24$vc4f8/valo=5,652.99 2006.183.08:15:59.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.08:15:59.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.08:15:59.24#ibcon#ireg 17 cls_cnt 0 2006.183.08:15:59.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:15:59.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:15:59.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:15:59.24#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:15:59.24#ibcon#first serial, iclass 34, count 0 2006.183.08:15:59.24#ibcon#enter sib2, iclass 34, count 0 2006.183.08:15:59.24#ibcon#flushed, iclass 34, count 0 2006.183.08:15:59.24#ibcon#about to write, iclass 34, count 0 2006.183.08:15:59.24#ibcon#wrote, iclass 34, count 0 2006.183.08:15:59.24#ibcon#about to read 3, iclass 34, count 0 2006.183.08:15:59.26#ibcon#read 3, iclass 34, count 0 2006.183.08:15:59.26#ibcon#about to read 4, iclass 34, count 0 2006.183.08:15:59.26#ibcon#read 4, iclass 34, count 0 2006.183.08:15:59.26#ibcon#about to read 5, iclass 34, count 0 2006.183.08:15:59.26#ibcon#read 5, iclass 34, count 0 2006.183.08:15:59.26#ibcon#about to read 6, iclass 34, count 0 2006.183.08:15:59.26#ibcon#read 6, iclass 34, count 0 2006.183.08:15:59.26#ibcon#end of sib2, iclass 34, count 0 2006.183.08:15:59.26#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:15:59.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:15:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:15:59.26#ibcon#*before write, iclass 34, count 0 2006.183.08:15:59.26#ibcon#enter sib2, iclass 34, count 0 2006.183.08:15:59.26#ibcon#flushed, iclass 34, count 0 2006.183.08:15:59.26#ibcon#about to write, iclass 34, count 0 2006.183.08:15:59.26#ibcon#wrote, iclass 34, count 0 2006.183.08:15:59.26#ibcon#about to read 3, iclass 34, count 0 2006.183.08:15:59.30#ibcon#read 3, iclass 34, count 0 2006.183.08:15:59.30#ibcon#about to read 4, iclass 34, count 0 2006.183.08:15:59.30#ibcon#read 4, iclass 34, count 0 2006.183.08:15:59.30#ibcon#about to read 5, iclass 34, count 0 2006.183.08:15:59.30#ibcon#read 5, iclass 34, count 0 2006.183.08:15:59.30#ibcon#about to read 6, iclass 34, count 0 2006.183.08:15:59.30#ibcon#read 6, iclass 34, count 0 2006.183.08:15:59.30#ibcon#end of sib2, iclass 34, count 0 2006.183.08:15:59.30#ibcon#*after write, iclass 34, count 0 2006.183.08:15:59.30#ibcon#*before return 0, iclass 34, count 0 2006.183.08:15:59.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:15:59.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:15:59.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:15:59.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:15:59.30$vc4f8/va=5,7 2006.183.08:15:59.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.08:15:59.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.08:15:59.30#ibcon#ireg 11 cls_cnt 2 2006.183.08:15:59.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:15:59.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:15:59.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:15:59.36#ibcon#enter wrdev, iclass 36, count 2 2006.183.08:15:59.36#ibcon#first serial, iclass 36, count 2 2006.183.08:15:59.36#ibcon#enter sib2, iclass 36, count 2 2006.183.08:15:59.36#ibcon#flushed, iclass 36, count 2 2006.183.08:15:59.36#ibcon#about to write, iclass 36, count 2 2006.183.08:15:59.36#ibcon#wrote, iclass 36, count 2 2006.183.08:15:59.36#ibcon#about to read 3, iclass 36, count 2 2006.183.08:15:59.38#ibcon#read 3, iclass 36, count 2 2006.183.08:15:59.38#ibcon#about to read 4, iclass 36, count 2 2006.183.08:15:59.38#ibcon#read 4, iclass 36, count 2 2006.183.08:15:59.38#ibcon#about to read 5, iclass 36, count 2 2006.183.08:15:59.38#ibcon#read 5, iclass 36, count 2 2006.183.08:15:59.38#ibcon#about to read 6, iclass 36, count 2 2006.183.08:15:59.38#ibcon#read 6, iclass 36, count 2 2006.183.08:15:59.38#ibcon#end of sib2, iclass 36, count 2 2006.183.08:15:59.38#ibcon#*mode == 0, iclass 36, count 2 2006.183.08:15:59.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.08:15:59.38#ibcon#[25=AT05-07\r\n] 2006.183.08:15:59.38#ibcon#*before write, iclass 36, count 2 2006.183.08:15:59.38#ibcon#enter sib2, iclass 36, count 2 2006.183.08:15:59.38#ibcon#flushed, iclass 36, count 2 2006.183.08:15:59.38#ibcon#about to write, iclass 36, count 2 2006.183.08:15:59.38#ibcon#wrote, iclass 36, count 2 2006.183.08:15:59.38#ibcon#about to read 3, iclass 36, count 2 2006.183.08:15:59.41#ibcon#read 3, iclass 36, count 2 2006.183.08:15:59.41#ibcon#about to read 4, iclass 36, count 2 2006.183.08:15:59.41#ibcon#read 4, iclass 36, count 2 2006.183.08:15:59.41#ibcon#about to read 5, iclass 36, count 2 2006.183.08:15:59.41#ibcon#read 5, iclass 36, count 2 2006.183.08:15:59.41#ibcon#about to read 6, iclass 36, count 2 2006.183.08:15:59.41#ibcon#read 6, iclass 36, count 2 2006.183.08:15:59.41#ibcon#end of sib2, iclass 36, count 2 2006.183.08:15:59.41#ibcon#*after write, iclass 36, count 2 2006.183.08:15:59.41#ibcon#*before return 0, iclass 36, count 2 2006.183.08:15:59.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:15:59.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:15:59.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.08:15:59.41#ibcon#ireg 7 cls_cnt 0 2006.183.08:15:59.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:15:59.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:15:59.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:15:59.53#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:15:59.53#ibcon#first serial, iclass 36, count 0 2006.183.08:15:59.53#ibcon#enter sib2, iclass 36, count 0 2006.183.08:15:59.53#ibcon#flushed, iclass 36, count 0 2006.183.08:15:59.53#ibcon#about to write, iclass 36, count 0 2006.183.08:15:59.53#ibcon#wrote, iclass 36, count 0 2006.183.08:15:59.53#ibcon#about to read 3, iclass 36, count 0 2006.183.08:15:59.55#ibcon#read 3, iclass 36, count 0 2006.183.08:15:59.55#ibcon#about to read 4, iclass 36, count 0 2006.183.08:15:59.55#ibcon#read 4, iclass 36, count 0 2006.183.08:15:59.55#ibcon#about to read 5, iclass 36, count 0 2006.183.08:15:59.55#ibcon#read 5, iclass 36, count 0 2006.183.08:15:59.55#ibcon#about to read 6, iclass 36, count 0 2006.183.08:15:59.55#ibcon#read 6, iclass 36, count 0 2006.183.08:15:59.55#ibcon#end of sib2, iclass 36, count 0 2006.183.08:15:59.55#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:15:59.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:15:59.55#ibcon#[25=USB\r\n] 2006.183.08:15:59.55#ibcon#*before write, iclass 36, count 0 2006.183.08:15:59.55#ibcon#enter sib2, iclass 36, count 0 2006.183.08:15:59.55#ibcon#flushed, iclass 36, count 0 2006.183.08:15:59.55#ibcon#about to write, iclass 36, count 0 2006.183.08:15:59.55#ibcon#wrote, iclass 36, count 0 2006.183.08:15:59.55#ibcon#about to read 3, iclass 36, count 0 2006.183.08:15:59.58#ibcon#read 3, iclass 36, count 0 2006.183.08:15:59.58#ibcon#about to read 4, iclass 36, count 0 2006.183.08:15:59.58#ibcon#read 4, iclass 36, count 0 2006.183.08:15:59.58#ibcon#about to read 5, iclass 36, count 0 2006.183.08:15:59.58#ibcon#read 5, iclass 36, count 0 2006.183.08:15:59.58#ibcon#about to read 6, iclass 36, count 0 2006.183.08:15:59.58#ibcon#read 6, iclass 36, count 0 2006.183.08:15:59.58#ibcon#end of sib2, iclass 36, count 0 2006.183.08:15:59.58#ibcon#*after write, iclass 36, count 0 2006.183.08:15:59.58#ibcon#*before return 0, iclass 36, count 0 2006.183.08:15:59.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:15:59.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:15:59.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:15:59.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:15:59.58$vc4f8/valo=6,772.99 2006.183.08:15:59.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.08:15:59.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.08:15:59.58#ibcon#ireg 17 cls_cnt 0 2006.183.08:15:59.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:15:59.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:15:59.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:15:59.58#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:15:59.58#ibcon#first serial, iclass 38, count 0 2006.183.08:15:59.58#ibcon#enter sib2, iclass 38, count 0 2006.183.08:15:59.58#ibcon#flushed, iclass 38, count 0 2006.183.08:15:59.58#ibcon#about to write, iclass 38, count 0 2006.183.08:15:59.58#ibcon#wrote, iclass 38, count 0 2006.183.08:15:59.58#ibcon#about to read 3, iclass 38, count 0 2006.183.08:15:59.61#ibcon#read 3, iclass 38, count 0 2006.183.08:15:59.61#ibcon#about to read 4, iclass 38, count 0 2006.183.08:15:59.61#ibcon#read 4, iclass 38, count 0 2006.183.08:15:59.61#ibcon#about to read 5, iclass 38, count 0 2006.183.08:15:59.61#ibcon#read 5, iclass 38, count 0 2006.183.08:15:59.61#ibcon#about to read 6, iclass 38, count 0 2006.183.08:15:59.61#ibcon#read 6, iclass 38, count 0 2006.183.08:15:59.61#ibcon#end of sib2, iclass 38, count 0 2006.183.08:15:59.61#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:15:59.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:15:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:15:59.61#ibcon#*before write, iclass 38, count 0 2006.183.08:15:59.61#ibcon#enter sib2, iclass 38, count 0 2006.183.08:15:59.61#ibcon#flushed, iclass 38, count 0 2006.183.08:15:59.61#ibcon#about to write, iclass 38, count 0 2006.183.08:15:59.61#ibcon#wrote, iclass 38, count 0 2006.183.08:15:59.61#ibcon#about to read 3, iclass 38, count 0 2006.183.08:15:59.65#ibcon#read 3, iclass 38, count 0 2006.183.08:15:59.65#ibcon#about to read 4, iclass 38, count 0 2006.183.08:15:59.65#ibcon#read 4, iclass 38, count 0 2006.183.08:15:59.65#ibcon#about to read 5, iclass 38, count 0 2006.183.08:15:59.65#ibcon#read 5, iclass 38, count 0 2006.183.08:15:59.65#ibcon#about to read 6, iclass 38, count 0 2006.183.08:15:59.65#ibcon#read 6, iclass 38, count 0 2006.183.08:15:59.65#ibcon#end of sib2, iclass 38, count 0 2006.183.08:15:59.65#ibcon#*after write, iclass 38, count 0 2006.183.08:15:59.65#ibcon#*before return 0, iclass 38, count 0 2006.183.08:15:59.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:15:59.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:15:59.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:15:59.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:15:59.65$vc4f8/va=6,6 2006.183.08:15:59.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.08:15:59.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.08:15:59.65#ibcon#ireg 11 cls_cnt 2 2006.183.08:15:59.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:15:59.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:15:59.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:15:59.70#ibcon#enter wrdev, iclass 40, count 2 2006.183.08:15:59.71#ibcon#first serial, iclass 40, count 2 2006.183.08:15:59.71#ibcon#enter sib2, iclass 40, count 2 2006.183.08:15:59.71#ibcon#flushed, iclass 40, count 2 2006.183.08:15:59.71#ibcon#about to write, iclass 40, count 2 2006.183.08:15:59.71#ibcon#wrote, iclass 40, count 2 2006.183.08:15:59.71#ibcon#about to read 3, iclass 40, count 2 2006.183.08:15:59.72#ibcon#read 3, iclass 40, count 2 2006.183.08:15:59.72#ibcon#about to read 4, iclass 40, count 2 2006.183.08:15:59.72#ibcon#read 4, iclass 40, count 2 2006.183.08:15:59.72#ibcon#about to read 5, iclass 40, count 2 2006.183.08:15:59.72#ibcon#read 5, iclass 40, count 2 2006.183.08:15:59.72#ibcon#about to read 6, iclass 40, count 2 2006.183.08:15:59.72#ibcon#read 6, iclass 40, count 2 2006.183.08:15:59.72#ibcon#end of sib2, iclass 40, count 2 2006.183.08:15:59.72#ibcon#*mode == 0, iclass 40, count 2 2006.183.08:15:59.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.08:15:59.72#ibcon#[25=AT06-06\r\n] 2006.183.08:15:59.72#ibcon#*before write, iclass 40, count 2 2006.183.08:15:59.72#ibcon#enter sib2, iclass 40, count 2 2006.183.08:15:59.72#ibcon#flushed, iclass 40, count 2 2006.183.08:15:59.72#ibcon#about to write, iclass 40, count 2 2006.183.08:15:59.72#ibcon#wrote, iclass 40, count 2 2006.183.08:15:59.72#ibcon#about to read 3, iclass 40, count 2 2006.183.08:15:59.75#ibcon#read 3, iclass 40, count 2 2006.183.08:15:59.75#ibcon#about to read 4, iclass 40, count 2 2006.183.08:15:59.75#ibcon#read 4, iclass 40, count 2 2006.183.08:15:59.75#ibcon#about to read 5, iclass 40, count 2 2006.183.08:15:59.75#ibcon#read 5, iclass 40, count 2 2006.183.08:15:59.75#ibcon#about to read 6, iclass 40, count 2 2006.183.08:15:59.75#ibcon#read 6, iclass 40, count 2 2006.183.08:15:59.75#ibcon#end of sib2, iclass 40, count 2 2006.183.08:15:59.75#ibcon#*after write, iclass 40, count 2 2006.183.08:15:59.75#ibcon#*before return 0, iclass 40, count 2 2006.183.08:15:59.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:15:59.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:15:59.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.08:15:59.75#ibcon#ireg 7 cls_cnt 0 2006.183.08:15:59.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:15:59.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:15:59.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:15:59.87#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:15:59.87#ibcon#first serial, iclass 40, count 0 2006.183.08:15:59.87#ibcon#enter sib2, iclass 40, count 0 2006.183.08:15:59.87#ibcon#flushed, iclass 40, count 0 2006.183.08:15:59.87#ibcon#about to write, iclass 40, count 0 2006.183.08:15:59.87#ibcon#wrote, iclass 40, count 0 2006.183.08:15:59.87#ibcon#about to read 3, iclass 40, count 0 2006.183.08:15:59.89#ibcon#read 3, iclass 40, count 0 2006.183.08:15:59.89#ibcon#about to read 4, iclass 40, count 0 2006.183.08:15:59.89#ibcon#read 4, iclass 40, count 0 2006.183.08:15:59.89#ibcon#about to read 5, iclass 40, count 0 2006.183.08:15:59.89#ibcon#read 5, iclass 40, count 0 2006.183.08:15:59.89#ibcon#about to read 6, iclass 40, count 0 2006.183.08:15:59.89#ibcon#read 6, iclass 40, count 0 2006.183.08:15:59.89#ibcon#end of sib2, iclass 40, count 0 2006.183.08:15:59.89#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:15:59.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:15:59.89#ibcon#[25=USB\r\n] 2006.183.08:15:59.89#ibcon#*before write, iclass 40, count 0 2006.183.08:15:59.89#ibcon#enter sib2, iclass 40, count 0 2006.183.08:15:59.89#ibcon#flushed, iclass 40, count 0 2006.183.08:15:59.89#ibcon#about to write, iclass 40, count 0 2006.183.08:15:59.89#ibcon#wrote, iclass 40, count 0 2006.183.08:15:59.89#ibcon#about to read 3, iclass 40, count 0 2006.183.08:15:59.92#ibcon#read 3, iclass 40, count 0 2006.183.08:15:59.92#ibcon#about to read 4, iclass 40, count 0 2006.183.08:15:59.92#ibcon#read 4, iclass 40, count 0 2006.183.08:15:59.92#ibcon#about to read 5, iclass 40, count 0 2006.183.08:15:59.92#ibcon#read 5, iclass 40, count 0 2006.183.08:15:59.92#ibcon#about to read 6, iclass 40, count 0 2006.183.08:15:59.92#ibcon#read 6, iclass 40, count 0 2006.183.08:15:59.92#ibcon#end of sib2, iclass 40, count 0 2006.183.08:15:59.92#ibcon#*after write, iclass 40, count 0 2006.183.08:15:59.92#ibcon#*before return 0, iclass 40, count 0 2006.183.08:15:59.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:15:59.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:15:59.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:15:59.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:15:59.92$vc4f8/valo=7,832.99 2006.183.08:15:59.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.08:15:59.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.08:15:59.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:15:59.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:15:59.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:15:59.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:15:59.92#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:15:59.92#ibcon#first serial, iclass 4, count 0 2006.183.08:15:59.92#ibcon#enter sib2, iclass 4, count 0 2006.183.08:15:59.92#ibcon#flushed, iclass 4, count 0 2006.183.08:15:59.92#ibcon#about to write, iclass 4, count 0 2006.183.08:15:59.92#ibcon#wrote, iclass 4, count 0 2006.183.08:15:59.92#ibcon#about to read 3, iclass 4, count 0 2006.183.08:15:59.94#ibcon#read 3, iclass 4, count 0 2006.183.08:15:59.94#ibcon#about to read 4, iclass 4, count 0 2006.183.08:15:59.94#ibcon#read 4, iclass 4, count 0 2006.183.08:15:59.94#ibcon#about to read 5, iclass 4, count 0 2006.183.08:15:59.94#ibcon#read 5, iclass 4, count 0 2006.183.08:15:59.94#ibcon#about to read 6, iclass 4, count 0 2006.183.08:15:59.94#ibcon#read 6, iclass 4, count 0 2006.183.08:15:59.94#ibcon#end of sib2, iclass 4, count 0 2006.183.08:15:59.94#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:15:59.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:15:59.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:15:59.94#ibcon#*before write, iclass 4, count 0 2006.183.08:15:59.94#ibcon#enter sib2, iclass 4, count 0 2006.183.08:15:59.94#ibcon#flushed, iclass 4, count 0 2006.183.08:15:59.94#ibcon#about to write, iclass 4, count 0 2006.183.08:15:59.94#ibcon#wrote, iclass 4, count 0 2006.183.08:15:59.94#ibcon#about to read 3, iclass 4, count 0 2006.183.08:15:59.98#ibcon#read 3, iclass 4, count 0 2006.183.08:15:59.98#ibcon#about to read 4, iclass 4, count 0 2006.183.08:15:59.98#ibcon#read 4, iclass 4, count 0 2006.183.08:15:59.98#ibcon#about to read 5, iclass 4, count 0 2006.183.08:15:59.98#ibcon#read 5, iclass 4, count 0 2006.183.08:15:59.98#ibcon#about to read 6, iclass 4, count 0 2006.183.08:15:59.98#ibcon#read 6, iclass 4, count 0 2006.183.08:15:59.98#ibcon#end of sib2, iclass 4, count 0 2006.183.08:15:59.98#ibcon#*after write, iclass 4, count 0 2006.183.08:15:59.98#ibcon#*before return 0, iclass 4, count 0 2006.183.08:15:59.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:15:59.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:15:59.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:15:59.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:15:59.98$vc4f8/va=7,6 2006.183.08:15:59.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.08:15:59.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.08:15:59.98#ibcon#ireg 11 cls_cnt 2 2006.183.08:15:59.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:16:00.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:16:00.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:16:00.04#ibcon#enter wrdev, iclass 6, count 2 2006.183.08:16:00.04#ibcon#first serial, iclass 6, count 2 2006.183.08:16:00.04#ibcon#enter sib2, iclass 6, count 2 2006.183.08:16:00.04#ibcon#flushed, iclass 6, count 2 2006.183.08:16:00.04#ibcon#about to write, iclass 6, count 2 2006.183.08:16:00.04#ibcon#wrote, iclass 6, count 2 2006.183.08:16:00.04#ibcon#about to read 3, iclass 6, count 2 2006.183.08:16:00.06#ibcon#read 3, iclass 6, count 2 2006.183.08:16:00.06#ibcon#about to read 4, iclass 6, count 2 2006.183.08:16:00.06#ibcon#read 4, iclass 6, count 2 2006.183.08:16:00.06#ibcon#about to read 5, iclass 6, count 2 2006.183.08:16:00.06#ibcon#read 5, iclass 6, count 2 2006.183.08:16:00.06#ibcon#about to read 6, iclass 6, count 2 2006.183.08:16:00.06#ibcon#read 6, iclass 6, count 2 2006.183.08:16:00.06#ibcon#end of sib2, iclass 6, count 2 2006.183.08:16:00.06#ibcon#*mode == 0, iclass 6, count 2 2006.183.08:16:00.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.08:16:00.06#ibcon#[25=AT07-06\r\n] 2006.183.08:16:00.06#ibcon#*before write, iclass 6, count 2 2006.183.08:16:00.06#ibcon#enter sib2, iclass 6, count 2 2006.183.08:16:00.06#ibcon#flushed, iclass 6, count 2 2006.183.08:16:00.06#ibcon#about to write, iclass 6, count 2 2006.183.08:16:00.06#ibcon#wrote, iclass 6, count 2 2006.183.08:16:00.06#ibcon#about to read 3, iclass 6, count 2 2006.183.08:16:00.09#ibcon#read 3, iclass 6, count 2 2006.183.08:16:00.09#ibcon#about to read 4, iclass 6, count 2 2006.183.08:16:00.09#ibcon#read 4, iclass 6, count 2 2006.183.08:16:00.09#ibcon#about to read 5, iclass 6, count 2 2006.183.08:16:00.09#ibcon#read 5, iclass 6, count 2 2006.183.08:16:00.09#ibcon#about to read 6, iclass 6, count 2 2006.183.08:16:00.09#ibcon#read 6, iclass 6, count 2 2006.183.08:16:00.09#ibcon#end of sib2, iclass 6, count 2 2006.183.08:16:00.09#ibcon#*after write, iclass 6, count 2 2006.183.08:16:00.09#ibcon#*before return 0, iclass 6, count 2 2006.183.08:16:00.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:16:00.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:16:00.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.08:16:00.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:00.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:16:00.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:16:00.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:16:00.21#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:16:00.21#ibcon#first serial, iclass 6, count 0 2006.183.08:16:00.21#ibcon#enter sib2, iclass 6, count 0 2006.183.08:16:00.21#ibcon#flushed, iclass 6, count 0 2006.183.08:16:00.21#ibcon#about to write, iclass 6, count 0 2006.183.08:16:00.21#ibcon#wrote, iclass 6, count 0 2006.183.08:16:00.21#ibcon#about to read 3, iclass 6, count 0 2006.183.08:16:00.23#ibcon#read 3, iclass 6, count 0 2006.183.08:16:00.23#ibcon#about to read 4, iclass 6, count 0 2006.183.08:16:00.23#ibcon#read 4, iclass 6, count 0 2006.183.08:16:00.23#ibcon#about to read 5, iclass 6, count 0 2006.183.08:16:00.23#ibcon#read 5, iclass 6, count 0 2006.183.08:16:00.23#ibcon#about to read 6, iclass 6, count 0 2006.183.08:16:00.23#ibcon#read 6, iclass 6, count 0 2006.183.08:16:00.23#ibcon#end of sib2, iclass 6, count 0 2006.183.08:16:00.23#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:16:00.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:16:00.23#ibcon#[25=USB\r\n] 2006.183.08:16:00.23#ibcon#*before write, iclass 6, count 0 2006.183.08:16:00.23#ibcon#enter sib2, iclass 6, count 0 2006.183.08:16:00.23#ibcon#flushed, iclass 6, count 0 2006.183.08:16:00.23#ibcon#about to write, iclass 6, count 0 2006.183.08:16:00.23#ibcon#wrote, iclass 6, count 0 2006.183.08:16:00.23#ibcon#about to read 3, iclass 6, count 0 2006.183.08:16:00.26#ibcon#read 3, iclass 6, count 0 2006.183.08:16:00.26#ibcon#about to read 4, iclass 6, count 0 2006.183.08:16:00.26#ibcon#read 4, iclass 6, count 0 2006.183.08:16:00.26#ibcon#about to read 5, iclass 6, count 0 2006.183.08:16:00.26#ibcon#read 5, iclass 6, count 0 2006.183.08:16:00.26#ibcon#about to read 6, iclass 6, count 0 2006.183.08:16:00.26#ibcon#read 6, iclass 6, count 0 2006.183.08:16:00.26#ibcon#end of sib2, iclass 6, count 0 2006.183.08:16:00.26#ibcon#*after write, iclass 6, count 0 2006.183.08:16:00.26#ibcon#*before return 0, iclass 6, count 0 2006.183.08:16:00.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:16:00.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:16:00.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:16:00.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:16:00.26$vc4f8/valo=8,852.99 2006.183.08:16:00.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.08:16:00.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.08:16:00.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:16:00.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:16:00.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:16:00.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:16:00.26#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:16:00.26#ibcon#first serial, iclass 10, count 0 2006.183.08:16:00.26#ibcon#enter sib2, iclass 10, count 0 2006.183.08:16:00.26#ibcon#flushed, iclass 10, count 0 2006.183.08:16:00.26#ibcon#about to write, iclass 10, count 0 2006.183.08:16:00.26#ibcon#wrote, iclass 10, count 0 2006.183.08:16:00.26#ibcon#about to read 3, iclass 10, count 0 2006.183.08:16:00.28#ibcon#read 3, iclass 10, count 0 2006.183.08:16:00.28#ibcon#about to read 4, iclass 10, count 0 2006.183.08:16:00.28#ibcon#read 4, iclass 10, count 0 2006.183.08:16:00.28#ibcon#about to read 5, iclass 10, count 0 2006.183.08:16:00.28#ibcon#read 5, iclass 10, count 0 2006.183.08:16:00.28#ibcon#about to read 6, iclass 10, count 0 2006.183.08:16:00.28#ibcon#read 6, iclass 10, count 0 2006.183.08:16:00.28#ibcon#end of sib2, iclass 10, count 0 2006.183.08:16:00.28#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:16:00.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:16:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:16:00.28#ibcon#*before write, iclass 10, count 0 2006.183.08:16:00.28#ibcon#enter sib2, iclass 10, count 0 2006.183.08:16:00.28#ibcon#flushed, iclass 10, count 0 2006.183.08:16:00.28#ibcon#about to write, iclass 10, count 0 2006.183.08:16:00.28#ibcon#wrote, iclass 10, count 0 2006.183.08:16:00.28#ibcon#about to read 3, iclass 10, count 0 2006.183.08:16:00.32#ibcon#read 3, iclass 10, count 0 2006.183.08:16:00.32#ibcon#about to read 4, iclass 10, count 0 2006.183.08:16:00.32#ibcon#read 4, iclass 10, count 0 2006.183.08:16:00.32#ibcon#about to read 5, iclass 10, count 0 2006.183.08:16:00.32#ibcon#read 5, iclass 10, count 0 2006.183.08:16:00.32#ibcon#about to read 6, iclass 10, count 0 2006.183.08:16:00.32#ibcon#read 6, iclass 10, count 0 2006.183.08:16:00.32#ibcon#end of sib2, iclass 10, count 0 2006.183.08:16:00.32#ibcon#*after write, iclass 10, count 0 2006.183.08:16:00.32#ibcon#*before return 0, iclass 10, count 0 2006.183.08:16:00.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:16:00.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:16:00.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:16:00.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:16:00.32$vc4f8/va=8,7 2006.183.08:16:00.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.08:16:00.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.08:16:00.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:16:00.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:16:00.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:16:00.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:16:00.38#ibcon#enter wrdev, iclass 12, count 2 2006.183.08:16:00.38#ibcon#first serial, iclass 12, count 2 2006.183.08:16:00.38#ibcon#enter sib2, iclass 12, count 2 2006.183.08:16:00.38#ibcon#flushed, iclass 12, count 2 2006.183.08:16:00.38#ibcon#about to write, iclass 12, count 2 2006.183.08:16:00.38#ibcon#wrote, iclass 12, count 2 2006.183.08:16:00.38#ibcon#about to read 3, iclass 12, count 2 2006.183.08:16:00.40#ibcon#read 3, iclass 12, count 2 2006.183.08:16:00.40#ibcon#about to read 4, iclass 12, count 2 2006.183.08:16:00.40#ibcon#read 4, iclass 12, count 2 2006.183.08:16:00.40#ibcon#about to read 5, iclass 12, count 2 2006.183.08:16:00.40#ibcon#read 5, iclass 12, count 2 2006.183.08:16:00.40#ibcon#about to read 6, iclass 12, count 2 2006.183.08:16:00.40#ibcon#read 6, iclass 12, count 2 2006.183.08:16:00.40#ibcon#end of sib2, iclass 12, count 2 2006.183.08:16:00.40#ibcon#*mode == 0, iclass 12, count 2 2006.183.08:16:00.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.08:16:00.40#ibcon#[25=AT08-07\r\n] 2006.183.08:16:00.40#ibcon#*before write, iclass 12, count 2 2006.183.08:16:00.40#ibcon#enter sib2, iclass 12, count 2 2006.183.08:16:00.40#ibcon#flushed, iclass 12, count 2 2006.183.08:16:00.40#ibcon#about to write, iclass 12, count 2 2006.183.08:16:00.40#ibcon#wrote, iclass 12, count 2 2006.183.08:16:00.40#ibcon#about to read 3, iclass 12, count 2 2006.183.08:16:00.43#ibcon#read 3, iclass 12, count 2 2006.183.08:16:00.43#ibcon#about to read 4, iclass 12, count 2 2006.183.08:16:00.43#ibcon#read 4, iclass 12, count 2 2006.183.08:16:00.43#ibcon#about to read 5, iclass 12, count 2 2006.183.08:16:00.43#ibcon#read 5, iclass 12, count 2 2006.183.08:16:00.43#ibcon#about to read 6, iclass 12, count 2 2006.183.08:16:00.43#ibcon#read 6, iclass 12, count 2 2006.183.08:16:00.43#ibcon#end of sib2, iclass 12, count 2 2006.183.08:16:00.43#ibcon#*after write, iclass 12, count 2 2006.183.08:16:00.43#ibcon#*before return 0, iclass 12, count 2 2006.183.08:16:00.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:16:00.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:16:00.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.08:16:00.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:00.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:16:00.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:16:00.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:16:00.55#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:16:00.55#ibcon#first serial, iclass 12, count 0 2006.183.08:16:00.55#ibcon#enter sib2, iclass 12, count 0 2006.183.08:16:00.55#ibcon#flushed, iclass 12, count 0 2006.183.08:16:00.55#ibcon#about to write, iclass 12, count 0 2006.183.08:16:00.55#ibcon#wrote, iclass 12, count 0 2006.183.08:16:00.55#ibcon#about to read 3, iclass 12, count 0 2006.183.08:16:00.57#ibcon#read 3, iclass 12, count 0 2006.183.08:16:00.57#ibcon#about to read 4, iclass 12, count 0 2006.183.08:16:00.57#ibcon#read 4, iclass 12, count 0 2006.183.08:16:00.57#ibcon#about to read 5, iclass 12, count 0 2006.183.08:16:00.57#ibcon#read 5, iclass 12, count 0 2006.183.08:16:00.57#ibcon#about to read 6, iclass 12, count 0 2006.183.08:16:00.57#ibcon#read 6, iclass 12, count 0 2006.183.08:16:00.57#ibcon#end of sib2, iclass 12, count 0 2006.183.08:16:00.57#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:16:00.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:16:00.57#ibcon#[25=USB\r\n] 2006.183.08:16:00.57#ibcon#*before write, iclass 12, count 0 2006.183.08:16:00.57#ibcon#enter sib2, iclass 12, count 0 2006.183.08:16:00.57#ibcon#flushed, iclass 12, count 0 2006.183.08:16:00.57#ibcon#about to write, iclass 12, count 0 2006.183.08:16:00.57#ibcon#wrote, iclass 12, count 0 2006.183.08:16:00.57#ibcon#about to read 3, iclass 12, count 0 2006.183.08:16:00.60#ibcon#read 3, iclass 12, count 0 2006.183.08:16:00.60#ibcon#about to read 4, iclass 12, count 0 2006.183.08:16:00.60#ibcon#read 4, iclass 12, count 0 2006.183.08:16:00.60#ibcon#about to read 5, iclass 12, count 0 2006.183.08:16:00.60#ibcon#read 5, iclass 12, count 0 2006.183.08:16:00.60#ibcon#about to read 6, iclass 12, count 0 2006.183.08:16:00.60#ibcon#read 6, iclass 12, count 0 2006.183.08:16:00.60#ibcon#end of sib2, iclass 12, count 0 2006.183.08:16:00.60#ibcon#*after write, iclass 12, count 0 2006.183.08:16:00.60#ibcon#*before return 0, iclass 12, count 0 2006.183.08:16:00.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:16:00.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:16:00.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:16:00.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:16:00.60$vc4f8/vblo=1,632.99 2006.183.08:16:00.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:16:00.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:16:00.60#ibcon#ireg 17 cls_cnt 0 2006.183.08:16:00.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:16:00.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:16:00.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:16:00.60#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:16:00.60#ibcon#first serial, iclass 14, count 0 2006.183.08:16:00.60#ibcon#enter sib2, iclass 14, count 0 2006.183.08:16:00.60#ibcon#flushed, iclass 14, count 0 2006.183.08:16:00.60#ibcon#about to write, iclass 14, count 0 2006.183.08:16:00.60#ibcon#wrote, iclass 14, count 0 2006.183.08:16:00.60#ibcon#about to read 3, iclass 14, count 0 2006.183.08:16:00.63#ibcon#read 3, iclass 14, count 0 2006.183.08:16:00.63#ibcon#about to read 4, iclass 14, count 0 2006.183.08:16:00.63#ibcon#read 4, iclass 14, count 0 2006.183.08:16:00.63#ibcon#about to read 5, iclass 14, count 0 2006.183.08:16:00.63#ibcon#read 5, iclass 14, count 0 2006.183.08:16:00.63#ibcon#about to read 6, iclass 14, count 0 2006.183.08:16:00.63#ibcon#read 6, iclass 14, count 0 2006.183.08:16:00.63#ibcon#end of sib2, iclass 14, count 0 2006.183.08:16:00.63#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:16:00.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:16:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:16:00.63#ibcon#*before write, iclass 14, count 0 2006.183.08:16:00.63#ibcon#enter sib2, iclass 14, count 0 2006.183.08:16:00.63#ibcon#flushed, iclass 14, count 0 2006.183.08:16:00.63#ibcon#about to write, iclass 14, count 0 2006.183.08:16:00.63#ibcon#wrote, iclass 14, count 0 2006.183.08:16:00.63#ibcon#about to read 3, iclass 14, count 0 2006.183.08:16:00.67#ibcon#read 3, iclass 14, count 0 2006.183.08:16:00.67#ibcon#about to read 4, iclass 14, count 0 2006.183.08:16:00.67#ibcon#read 4, iclass 14, count 0 2006.183.08:16:00.67#ibcon#about to read 5, iclass 14, count 0 2006.183.08:16:00.67#ibcon#read 5, iclass 14, count 0 2006.183.08:16:00.67#ibcon#about to read 6, iclass 14, count 0 2006.183.08:16:00.67#ibcon#read 6, iclass 14, count 0 2006.183.08:16:00.67#ibcon#end of sib2, iclass 14, count 0 2006.183.08:16:00.67#ibcon#*after write, iclass 14, count 0 2006.183.08:16:00.67#ibcon#*before return 0, iclass 14, count 0 2006.183.08:16:00.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:16:00.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:16:00.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:16:00.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:16:00.67$vc4f8/vb=1,4 2006.183.08:16:00.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.08:16:00.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.08:16:00.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:16:00.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:16:00.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:16:00.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:16:00.67#ibcon#enter wrdev, iclass 16, count 2 2006.183.08:16:00.67#ibcon#first serial, iclass 16, count 2 2006.183.08:16:00.67#ibcon#enter sib2, iclass 16, count 2 2006.183.08:16:00.67#ibcon#flushed, iclass 16, count 2 2006.183.08:16:00.67#ibcon#about to write, iclass 16, count 2 2006.183.08:16:00.67#ibcon#wrote, iclass 16, count 2 2006.183.08:16:00.67#ibcon#about to read 3, iclass 16, count 2 2006.183.08:16:00.69#ibcon#read 3, iclass 16, count 2 2006.183.08:16:00.69#ibcon#about to read 4, iclass 16, count 2 2006.183.08:16:00.69#ibcon#read 4, iclass 16, count 2 2006.183.08:16:00.69#ibcon#about to read 5, iclass 16, count 2 2006.183.08:16:00.69#ibcon#read 5, iclass 16, count 2 2006.183.08:16:00.69#ibcon#about to read 6, iclass 16, count 2 2006.183.08:16:00.69#ibcon#read 6, iclass 16, count 2 2006.183.08:16:00.69#ibcon#end of sib2, iclass 16, count 2 2006.183.08:16:00.69#ibcon#*mode == 0, iclass 16, count 2 2006.183.08:16:00.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.08:16:00.69#ibcon#[27=AT01-04\r\n] 2006.183.08:16:00.69#ibcon#*before write, iclass 16, count 2 2006.183.08:16:00.69#ibcon#enter sib2, iclass 16, count 2 2006.183.08:16:00.69#ibcon#flushed, iclass 16, count 2 2006.183.08:16:00.69#ibcon#about to write, iclass 16, count 2 2006.183.08:16:00.69#ibcon#wrote, iclass 16, count 2 2006.183.08:16:00.69#ibcon#about to read 3, iclass 16, count 2 2006.183.08:16:00.72#ibcon#read 3, iclass 16, count 2 2006.183.08:16:00.72#ibcon#about to read 4, iclass 16, count 2 2006.183.08:16:00.72#ibcon#read 4, iclass 16, count 2 2006.183.08:16:00.72#ibcon#about to read 5, iclass 16, count 2 2006.183.08:16:00.72#ibcon#read 5, iclass 16, count 2 2006.183.08:16:00.72#ibcon#about to read 6, iclass 16, count 2 2006.183.08:16:00.72#ibcon#read 6, iclass 16, count 2 2006.183.08:16:00.72#ibcon#end of sib2, iclass 16, count 2 2006.183.08:16:00.72#ibcon#*after write, iclass 16, count 2 2006.183.08:16:00.72#ibcon#*before return 0, iclass 16, count 2 2006.183.08:16:00.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:16:00.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:16:00.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.08:16:00.72#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:00.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:16:00.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:16:00.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:16:00.84#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:16:00.84#ibcon#first serial, iclass 16, count 0 2006.183.08:16:00.84#ibcon#enter sib2, iclass 16, count 0 2006.183.08:16:00.84#ibcon#flushed, iclass 16, count 0 2006.183.08:16:00.84#ibcon#about to write, iclass 16, count 0 2006.183.08:16:00.84#ibcon#wrote, iclass 16, count 0 2006.183.08:16:00.84#ibcon#about to read 3, iclass 16, count 0 2006.183.08:16:00.86#ibcon#read 3, iclass 16, count 0 2006.183.08:16:00.86#ibcon#about to read 4, iclass 16, count 0 2006.183.08:16:00.86#ibcon#read 4, iclass 16, count 0 2006.183.08:16:00.86#ibcon#about to read 5, iclass 16, count 0 2006.183.08:16:00.86#ibcon#read 5, iclass 16, count 0 2006.183.08:16:00.86#ibcon#about to read 6, iclass 16, count 0 2006.183.08:16:00.86#ibcon#read 6, iclass 16, count 0 2006.183.08:16:00.86#ibcon#end of sib2, iclass 16, count 0 2006.183.08:16:00.86#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:16:00.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:16:00.86#ibcon#[27=USB\r\n] 2006.183.08:16:00.86#ibcon#*before write, iclass 16, count 0 2006.183.08:16:00.86#ibcon#enter sib2, iclass 16, count 0 2006.183.08:16:00.86#ibcon#flushed, iclass 16, count 0 2006.183.08:16:00.86#ibcon#about to write, iclass 16, count 0 2006.183.08:16:00.86#ibcon#wrote, iclass 16, count 0 2006.183.08:16:00.86#ibcon#about to read 3, iclass 16, count 0 2006.183.08:16:00.89#ibcon#read 3, iclass 16, count 0 2006.183.08:16:00.89#ibcon#about to read 4, iclass 16, count 0 2006.183.08:16:00.89#ibcon#read 4, iclass 16, count 0 2006.183.08:16:00.89#ibcon#about to read 5, iclass 16, count 0 2006.183.08:16:00.89#ibcon#read 5, iclass 16, count 0 2006.183.08:16:00.89#ibcon#about to read 6, iclass 16, count 0 2006.183.08:16:00.89#ibcon#read 6, iclass 16, count 0 2006.183.08:16:00.89#ibcon#end of sib2, iclass 16, count 0 2006.183.08:16:00.89#ibcon#*after write, iclass 16, count 0 2006.183.08:16:00.89#ibcon#*before return 0, iclass 16, count 0 2006.183.08:16:00.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:16:00.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:16:00.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:16:00.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:16:00.89$vc4f8/vblo=2,640.99 2006.183.08:16:00.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:16:00.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:16:00.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:16:00.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:16:00.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:16:00.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:16:00.89#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:16:00.89#ibcon#first serial, iclass 18, count 0 2006.183.08:16:00.89#ibcon#enter sib2, iclass 18, count 0 2006.183.08:16:00.89#ibcon#flushed, iclass 18, count 0 2006.183.08:16:00.89#ibcon#about to write, iclass 18, count 0 2006.183.08:16:00.89#ibcon#wrote, iclass 18, count 0 2006.183.08:16:00.89#ibcon#about to read 3, iclass 18, count 0 2006.183.08:16:00.91#ibcon#read 3, iclass 18, count 0 2006.183.08:16:00.91#ibcon#about to read 4, iclass 18, count 0 2006.183.08:16:00.91#ibcon#read 4, iclass 18, count 0 2006.183.08:16:00.91#ibcon#about to read 5, iclass 18, count 0 2006.183.08:16:00.91#ibcon#read 5, iclass 18, count 0 2006.183.08:16:00.91#ibcon#about to read 6, iclass 18, count 0 2006.183.08:16:00.91#ibcon#read 6, iclass 18, count 0 2006.183.08:16:00.91#ibcon#end of sib2, iclass 18, count 0 2006.183.08:16:00.91#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:16:00.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:16:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:16:00.91#ibcon#*before write, iclass 18, count 0 2006.183.08:16:00.91#ibcon#enter sib2, iclass 18, count 0 2006.183.08:16:00.91#ibcon#flushed, iclass 18, count 0 2006.183.08:16:00.91#ibcon#about to write, iclass 18, count 0 2006.183.08:16:00.91#ibcon#wrote, iclass 18, count 0 2006.183.08:16:00.91#ibcon#about to read 3, iclass 18, count 0 2006.183.08:16:00.95#ibcon#read 3, iclass 18, count 0 2006.183.08:16:00.95#ibcon#about to read 4, iclass 18, count 0 2006.183.08:16:00.95#ibcon#read 4, iclass 18, count 0 2006.183.08:16:00.95#ibcon#about to read 5, iclass 18, count 0 2006.183.08:16:00.95#ibcon#read 5, iclass 18, count 0 2006.183.08:16:00.95#ibcon#about to read 6, iclass 18, count 0 2006.183.08:16:00.95#ibcon#read 6, iclass 18, count 0 2006.183.08:16:00.95#ibcon#end of sib2, iclass 18, count 0 2006.183.08:16:00.95#ibcon#*after write, iclass 18, count 0 2006.183.08:16:00.95#ibcon#*before return 0, iclass 18, count 0 2006.183.08:16:00.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:16:00.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:16:00.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:16:00.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:16:00.95$vc4f8/vb=2,4 2006.183.08:16:00.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.08:16:00.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.08:16:00.95#ibcon#ireg 11 cls_cnt 2 2006.183.08:16:00.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:16:01.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:16:01.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:16:01.01#ibcon#enter wrdev, iclass 20, count 2 2006.183.08:16:01.01#ibcon#first serial, iclass 20, count 2 2006.183.08:16:01.01#ibcon#enter sib2, iclass 20, count 2 2006.183.08:16:01.01#ibcon#flushed, iclass 20, count 2 2006.183.08:16:01.01#ibcon#about to write, iclass 20, count 2 2006.183.08:16:01.01#ibcon#wrote, iclass 20, count 2 2006.183.08:16:01.01#ibcon#about to read 3, iclass 20, count 2 2006.183.08:16:01.03#ibcon#read 3, iclass 20, count 2 2006.183.08:16:01.03#ibcon#about to read 4, iclass 20, count 2 2006.183.08:16:01.03#ibcon#read 4, iclass 20, count 2 2006.183.08:16:01.03#ibcon#about to read 5, iclass 20, count 2 2006.183.08:16:01.03#ibcon#read 5, iclass 20, count 2 2006.183.08:16:01.03#ibcon#about to read 6, iclass 20, count 2 2006.183.08:16:01.03#ibcon#read 6, iclass 20, count 2 2006.183.08:16:01.03#ibcon#end of sib2, iclass 20, count 2 2006.183.08:16:01.03#ibcon#*mode == 0, iclass 20, count 2 2006.183.08:16:01.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.08:16:01.03#ibcon#[27=AT02-04\r\n] 2006.183.08:16:01.03#ibcon#*before write, iclass 20, count 2 2006.183.08:16:01.03#ibcon#enter sib2, iclass 20, count 2 2006.183.08:16:01.03#ibcon#flushed, iclass 20, count 2 2006.183.08:16:01.03#ibcon#about to write, iclass 20, count 2 2006.183.08:16:01.03#ibcon#wrote, iclass 20, count 2 2006.183.08:16:01.03#ibcon#about to read 3, iclass 20, count 2 2006.183.08:16:01.06#ibcon#read 3, iclass 20, count 2 2006.183.08:16:01.06#ibcon#about to read 4, iclass 20, count 2 2006.183.08:16:01.06#ibcon#read 4, iclass 20, count 2 2006.183.08:16:01.06#ibcon#about to read 5, iclass 20, count 2 2006.183.08:16:01.06#ibcon#read 5, iclass 20, count 2 2006.183.08:16:01.06#ibcon#about to read 6, iclass 20, count 2 2006.183.08:16:01.06#ibcon#read 6, iclass 20, count 2 2006.183.08:16:01.06#ibcon#end of sib2, iclass 20, count 2 2006.183.08:16:01.06#ibcon#*after write, iclass 20, count 2 2006.183.08:16:01.06#ibcon#*before return 0, iclass 20, count 2 2006.183.08:16:01.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:16:01.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:16:01.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.08:16:01.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:01.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:16:01.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:16:01.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:16:01.18#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:16:01.18#ibcon#first serial, iclass 20, count 0 2006.183.08:16:01.18#ibcon#enter sib2, iclass 20, count 0 2006.183.08:16:01.18#ibcon#flushed, iclass 20, count 0 2006.183.08:16:01.18#ibcon#about to write, iclass 20, count 0 2006.183.08:16:01.18#ibcon#wrote, iclass 20, count 0 2006.183.08:16:01.18#ibcon#about to read 3, iclass 20, count 0 2006.183.08:16:01.20#ibcon#read 3, iclass 20, count 0 2006.183.08:16:01.20#ibcon#about to read 4, iclass 20, count 0 2006.183.08:16:01.20#ibcon#read 4, iclass 20, count 0 2006.183.08:16:01.20#ibcon#about to read 5, iclass 20, count 0 2006.183.08:16:01.20#ibcon#read 5, iclass 20, count 0 2006.183.08:16:01.20#ibcon#about to read 6, iclass 20, count 0 2006.183.08:16:01.20#ibcon#read 6, iclass 20, count 0 2006.183.08:16:01.20#ibcon#end of sib2, iclass 20, count 0 2006.183.08:16:01.20#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:16:01.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:16:01.20#ibcon#[27=USB\r\n] 2006.183.08:16:01.20#ibcon#*before write, iclass 20, count 0 2006.183.08:16:01.20#ibcon#enter sib2, iclass 20, count 0 2006.183.08:16:01.20#ibcon#flushed, iclass 20, count 0 2006.183.08:16:01.20#ibcon#about to write, iclass 20, count 0 2006.183.08:16:01.20#ibcon#wrote, iclass 20, count 0 2006.183.08:16:01.20#ibcon#about to read 3, iclass 20, count 0 2006.183.08:16:01.23#ibcon#read 3, iclass 20, count 0 2006.183.08:16:01.23#ibcon#about to read 4, iclass 20, count 0 2006.183.08:16:01.23#ibcon#read 4, iclass 20, count 0 2006.183.08:16:01.23#ibcon#about to read 5, iclass 20, count 0 2006.183.08:16:01.23#ibcon#read 5, iclass 20, count 0 2006.183.08:16:01.23#ibcon#about to read 6, iclass 20, count 0 2006.183.08:16:01.23#ibcon#read 6, iclass 20, count 0 2006.183.08:16:01.23#ibcon#end of sib2, iclass 20, count 0 2006.183.08:16:01.23#ibcon#*after write, iclass 20, count 0 2006.183.08:16:01.23#ibcon#*before return 0, iclass 20, count 0 2006.183.08:16:01.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:16:01.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:16:01.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:16:01.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:16:01.23$vc4f8/vblo=3,656.99 2006.183.08:16:01.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.08:16:01.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.08:16:01.23#ibcon#ireg 17 cls_cnt 0 2006.183.08:16:01.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:16:01.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:16:01.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:16:01.23#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:16:01.23#ibcon#first serial, iclass 22, count 0 2006.183.08:16:01.23#ibcon#enter sib2, iclass 22, count 0 2006.183.08:16:01.23#ibcon#flushed, iclass 22, count 0 2006.183.08:16:01.23#ibcon#about to write, iclass 22, count 0 2006.183.08:16:01.23#ibcon#wrote, iclass 22, count 0 2006.183.08:16:01.23#ibcon#about to read 3, iclass 22, count 0 2006.183.08:16:01.25#ibcon#read 3, iclass 22, count 0 2006.183.08:16:01.25#ibcon#about to read 4, iclass 22, count 0 2006.183.08:16:01.25#ibcon#read 4, iclass 22, count 0 2006.183.08:16:01.25#ibcon#about to read 5, iclass 22, count 0 2006.183.08:16:01.25#ibcon#read 5, iclass 22, count 0 2006.183.08:16:01.25#ibcon#about to read 6, iclass 22, count 0 2006.183.08:16:01.25#ibcon#read 6, iclass 22, count 0 2006.183.08:16:01.25#ibcon#end of sib2, iclass 22, count 0 2006.183.08:16:01.25#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:16:01.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:16:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:16:01.25#ibcon#*before write, iclass 22, count 0 2006.183.08:16:01.25#ibcon#enter sib2, iclass 22, count 0 2006.183.08:16:01.25#ibcon#flushed, iclass 22, count 0 2006.183.08:16:01.25#ibcon#about to write, iclass 22, count 0 2006.183.08:16:01.25#ibcon#wrote, iclass 22, count 0 2006.183.08:16:01.25#ibcon#about to read 3, iclass 22, count 0 2006.183.08:16:01.29#ibcon#read 3, iclass 22, count 0 2006.183.08:16:01.29#ibcon#about to read 4, iclass 22, count 0 2006.183.08:16:01.29#ibcon#read 4, iclass 22, count 0 2006.183.08:16:01.29#ibcon#about to read 5, iclass 22, count 0 2006.183.08:16:01.29#ibcon#read 5, iclass 22, count 0 2006.183.08:16:01.29#ibcon#about to read 6, iclass 22, count 0 2006.183.08:16:01.29#ibcon#read 6, iclass 22, count 0 2006.183.08:16:01.29#ibcon#end of sib2, iclass 22, count 0 2006.183.08:16:01.29#ibcon#*after write, iclass 22, count 0 2006.183.08:16:01.29#ibcon#*before return 0, iclass 22, count 0 2006.183.08:16:01.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:16:01.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:16:01.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:16:01.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:16:01.29$vc4f8/vb=3,4 2006.183.08:16:01.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.08:16:01.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.08:16:01.29#ibcon#ireg 11 cls_cnt 2 2006.183.08:16:01.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:16:01.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:16:01.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:16:01.35#ibcon#enter wrdev, iclass 24, count 2 2006.183.08:16:01.35#ibcon#first serial, iclass 24, count 2 2006.183.08:16:01.35#ibcon#enter sib2, iclass 24, count 2 2006.183.08:16:01.35#ibcon#flushed, iclass 24, count 2 2006.183.08:16:01.35#ibcon#about to write, iclass 24, count 2 2006.183.08:16:01.35#ibcon#wrote, iclass 24, count 2 2006.183.08:16:01.35#ibcon#about to read 3, iclass 24, count 2 2006.183.08:16:01.37#ibcon#read 3, iclass 24, count 2 2006.183.08:16:01.37#ibcon#about to read 4, iclass 24, count 2 2006.183.08:16:01.37#ibcon#read 4, iclass 24, count 2 2006.183.08:16:01.37#ibcon#about to read 5, iclass 24, count 2 2006.183.08:16:01.37#ibcon#read 5, iclass 24, count 2 2006.183.08:16:01.37#ibcon#about to read 6, iclass 24, count 2 2006.183.08:16:01.37#ibcon#read 6, iclass 24, count 2 2006.183.08:16:01.37#ibcon#end of sib2, iclass 24, count 2 2006.183.08:16:01.37#ibcon#*mode == 0, iclass 24, count 2 2006.183.08:16:01.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.08:16:01.37#ibcon#[27=AT03-04\r\n] 2006.183.08:16:01.37#ibcon#*before write, iclass 24, count 2 2006.183.08:16:01.37#ibcon#enter sib2, iclass 24, count 2 2006.183.08:16:01.37#ibcon#flushed, iclass 24, count 2 2006.183.08:16:01.37#ibcon#about to write, iclass 24, count 2 2006.183.08:16:01.37#ibcon#wrote, iclass 24, count 2 2006.183.08:16:01.37#ibcon#about to read 3, iclass 24, count 2 2006.183.08:16:01.40#ibcon#read 3, iclass 24, count 2 2006.183.08:16:01.40#ibcon#about to read 4, iclass 24, count 2 2006.183.08:16:01.40#ibcon#read 4, iclass 24, count 2 2006.183.08:16:01.40#ibcon#about to read 5, iclass 24, count 2 2006.183.08:16:01.40#ibcon#read 5, iclass 24, count 2 2006.183.08:16:01.40#ibcon#about to read 6, iclass 24, count 2 2006.183.08:16:01.40#ibcon#read 6, iclass 24, count 2 2006.183.08:16:01.40#ibcon#end of sib2, iclass 24, count 2 2006.183.08:16:01.40#ibcon#*after write, iclass 24, count 2 2006.183.08:16:01.40#ibcon#*before return 0, iclass 24, count 2 2006.183.08:16:01.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:16:01.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:16:01.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.08:16:01.40#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:01.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:16:01.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:16:01.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:16:01.52#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:16:01.52#ibcon#first serial, iclass 24, count 0 2006.183.08:16:01.52#ibcon#enter sib2, iclass 24, count 0 2006.183.08:16:01.52#ibcon#flushed, iclass 24, count 0 2006.183.08:16:01.52#ibcon#about to write, iclass 24, count 0 2006.183.08:16:01.52#ibcon#wrote, iclass 24, count 0 2006.183.08:16:01.52#ibcon#about to read 3, iclass 24, count 0 2006.183.08:16:01.54#ibcon#read 3, iclass 24, count 0 2006.183.08:16:01.54#ibcon#about to read 4, iclass 24, count 0 2006.183.08:16:01.54#ibcon#read 4, iclass 24, count 0 2006.183.08:16:01.54#ibcon#about to read 5, iclass 24, count 0 2006.183.08:16:01.54#ibcon#read 5, iclass 24, count 0 2006.183.08:16:01.54#ibcon#about to read 6, iclass 24, count 0 2006.183.08:16:01.54#ibcon#read 6, iclass 24, count 0 2006.183.08:16:01.54#ibcon#end of sib2, iclass 24, count 0 2006.183.08:16:01.54#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:16:01.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:16:01.54#ibcon#[27=USB\r\n] 2006.183.08:16:01.54#ibcon#*before write, iclass 24, count 0 2006.183.08:16:01.54#ibcon#enter sib2, iclass 24, count 0 2006.183.08:16:01.54#ibcon#flushed, iclass 24, count 0 2006.183.08:16:01.54#ibcon#about to write, iclass 24, count 0 2006.183.08:16:01.54#ibcon#wrote, iclass 24, count 0 2006.183.08:16:01.54#ibcon#about to read 3, iclass 24, count 0 2006.183.08:16:01.57#ibcon#read 3, iclass 24, count 0 2006.183.08:16:01.57#ibcon#about to read 4, iclass 24, count 0 2006.183.08:16:01.57#ibcon#read 4, iclass 24, count 0 2006.183.08:16:01.57#ibcon#about to read 5, iclass 24, count 0 2006.183.08:16:01.57#ibcon#read 5, iclass 24, count 0 2006.183.08:16:01.57#ibcon#about to read 6, iclass 24, count 0 2006.183.08:16:01.57#ibcon#read 6, iclass 24, count 0 2006.183.08:16:01.57#ibcon#end of sib2, iclass 24, count 0 2006.183.08:16:01.57#ibcon#*after write, iclass 24, count 0 2006.183.08:16:01.57#ibcon#*before return 0, iclass 24, count 0 2006.183.08:16:01.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:16:01.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:16:01.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:16:01.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:16:01.57$vc4f8/vblo=4,712.99 2006.183.08:16:01.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.08:16:01.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.08:16:01.57#ibcon#ireg 17 cls_cnt 0 2006.183.08:16:01.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:16:01.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:16:01.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:16:01.57#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:16:01.57#ibcon#first serial, iclass 26, count 0 2006.183.08:16:01.57#ibcon#enter sib2, iclass 26, count 0 2006.183.08:16:01.57#ibcon#flushed, iclass 26, count 0 2006.183.08:16:01.57#ibcon#about to write, iclass 26, count 0 2006.183.08:16:01.57#ibcon#wrote, iclass 26, count 0 2006.183.08:16:01.57#ibcon#about to read 3, iclass 26, count 0 2006.183.08:16:01.59#ibcon#read 3, iclass 26, count 0 2006.183.08:16:01.59#ibcon#about to read 4, iclass 26, count 0 2006.183.08:16:01.59#ibcon#read 4, iclass 26, count 0 2006.183.08:16:01.59#ibcon#about to read 5, iclass 26, count 0 2006.183.08:16:01.59#ibcon#read 5, iclass 26, count 0 2006.183.08:16:01.59#ibcon#about to read 6, iclass 26, count 0 2006.183.08:16:01.59#ibcon#read 6, iclass 26, count 0 2006.183.08:16:01.59#ibcon#end of sib2, iclass 26, count 0 2006.183.08:16:01.59#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:16:01.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:16:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:16:01.59#ibcon#*before write, iclass 26, count 0 2006.183.08:16:01.59#ibcon#enter sib2, iclass 26, count 0 2006.183.08:16:01.59#ibcon#flushed, iclass 26, count 0 2006.183.08:16:01.59#ibcon#about to write, iclass 26, count 0 2006.183.08:16:01.59#ibcon#wrote, iclass 26, count 0 2006.183.08:16:01.59#ibcon#about to read 3, iclass 26, count 0 2006.183.08:16:01.63#ibcon#read 3, iclass 26, count 0 2006.183.08:16:01.63#ibcon#about to read 4, iclass 26, count 0 2006.183.08:16:01.63#ibcon#read 4, iclass 26, count 0 2006.183.08:16:01.63#ibcon#about to read 5, iclass 26, count 0 2006.183.08:16:01.63#ibcon#read 5, iclass 26, count 0 2006.183.08:16:01.63#ibcon#about to read 6, iclass 26, count 0 2006.183.08:16:01.63#ibcon#read 6, iclass 26, count 0 2006.183.08:16:01.63#ibcon#end of sib2, iclass 26, count 0 2006.183.08:16:01.63#ibcon#*after write, iclass 26, count 0 2006.183.08:16:01.63#ibcon#*before return 0, iclass 26, count 0 2006.183.08:16:01.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:16:01.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:16:01.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:16:01.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:16:01.63$vc4f8/vb=4,4 2006.183.08:16:01.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.08:16:01.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.08:16:01.63#ibcon#ireg 11 cls_cnt 2 2006.183.08:16:01.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:16:01.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:16:01.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:16:01.69#ibcon#enter wrdev, iclass 28, count 2 2006.183.08:16:01.69#ibcon#first serial, iclass 28, count 2 2006.183.08:16:01.69#ibcon#enter sib2, iclass 28, count 2 2006.183.08:16:01.69#ibcon#flushed, iclass 28, count 2 2006.183.08:16:01.69#ibcon#about to write, iclass 28, count 2 2006.183.08:16:01.69#ibcon#wrote, iclass 28, count 2 2006.183.08:16:01.69#ibcon#about to read 3, iclass 28, count 2 2006.183.08:16:01.71#ibcon#read 3, iclass 28, count 2 2006.183.08:16:01.71#ibcon#about to read 4, iclass 28, count 2 2006.183.08:16:01.71#ibcon#read 4, iclass 28, count 2 2006.183.08:16:01.71#ibcon#about to read 5, iclass 28, count 2 2006.183.08:16:01.71#ibcon#read 5, iclass 28, count 2 2006.183.08:16:01.71#ibcon#about to read 6, iclass 28, count 2 2006.183.08:16:01.71#ibcon#read 6, iclass 28, count 2 2006.183.08:16:01.71#ibcon#end of sib2, iclass 28, count 2 2006.183.08:16:01.71#ibcon#*mode == 0, iclass 28, count 2 2006.183.08:16:01.71#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.08:16:01.71#ibcon#[27=AT04-04\r\n] 2006.183.08:16:01.71#ibcon#*before write, iclass 28, count 2 2006.183.08:16:01.71#ibcon#enter sib2, iclass 28, count 2 2006.183.08:16:01.71#ibcon#flushed, iclass 28, count 2 2006.183.08:16:01.71#ibcon#about to write, iclass 28, count 2 2006.183.08:16:01.71#ibcon#wrote, iclass 28, count 2 2006.183.08:16:01.71#ibcon#about to read 3, iclass 28, count 2 2006.183.08:16:01.74#ibcon#read 3, iclass 28, count 2 2006.183.08:16:01.74#ibcon#about to read 4, iclass 28, count 2 2006.183.08:16:01.74#ibcon#read 4, iclass 28, count 2 2006.183.08:16:01.74#ibcon#about to read 5, iclass 28, count 2 2006.183.08:16:01.74#ibcon#read 5, iclass 28, count 2 2006.183.08:16:01.74#ibcon#about to read 6, iclass 28, count 2 2006.183.08:16:01.74#ibcon#read 6, iclass 28, count 2 2006.183.08:16:01.74#ibcon#end of sib2, iclass 28, count 2 2006.183.08:16:01.74#ibcon#*after write, iclass 28, count 2 2006.183.08:16:01.74#ibcon#*before return 0, iclass 28, count 2 2006.183.08:16:01.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:16:01.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:16:01.74#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.08:16:01.74#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:01.74#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:16:01.86#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:16:01.86#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:16:01.86#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:16:01.86#ibcon#first serial, iclass 28, count 0 2006.183.08:16:01.86#ibcon#enter sib2, iclass 28, count 0 2006.183.08:16:01.86#ibcon#flushed, iclass 28, count 0 2006.183.08:16:01.86#ibcon#about to write, iclass 28, count 0 2006.183.08:16:01.86#ibcon#wrote, iclass 28, count 0 2006.183.08:16:01.86#ibcon#about to read 3, iclass 28, count 0 2006.183.08:16:01.88#ibcon#read 3, iclass 28, count 0 2006.183.08:16:01.88#ibcon#about to read 4, iclass 28, count 0 2006.183.08:16:01.88#ibcon#read 4, iclass 28, count 0 2006.183.08:16:01.88#ibcon#about to read 5, iclass 28, count 0 2006.183.08:16:01.88#ibcon#read 5, iclass 28, count 0 2006.183.08:16:01.88#ibcon#about to read 6, iclass 28, count 0 2006.183.08:16:01.88#ibcon#read 6, iclass 28, count 0 2006.183.08:16:01.88#ibcon#end of sib2, iclass 28, count 0 2006.183.08:16:01.88#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:16:01.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:16:01.88#ibcon#[27=USB\r\n] 2006.183.08:16:01.88#ibcon#*before write, iclass 28, count 0 2006.183.08:16:01.88#ibcon#enter sib2, iclass 28, count 0 2006.183.08:16:01.88#ibcon#flushed, iclass 28, count 0 2006.183.08:16:01.88#ibcon#about to write, iclass 28, count 0 2006.183.08:16:01.88#ibcon#wrote, iclass 28, count 0 2006.183.08:16:01.88#ibcon#about to read 3, iclass 28, count 0 2006.183.08:16:01.91#ibcon#read 3, iclass 28, count 0 2006.183.08:16:01.91#ibcon#about to read 4, iclass 28, count 0 2006.183.08:16:01.91#ibcon#read 4, iclass 28, count 0 2006.183.08:16:01.91#ibcon#about to read 5, iclass 28, count 0 2006.183.08:16:01.91#ibcon#read 5, iclass 28, count 0 2006.183.08:16:01.91#ibcon#about to read 6, iclass 28, count 0 2006.183.08:16:01.91#ibcon#read 6, iclass 28, count 0 2006.183.08:16:01.91#ibcon#end of sib2, iclass 28, count 0 2006.183.08:16:01.91#ibcon#*after write, iclass 28, count 0 2006.183.08:16:01.91#ibcon#*before return 0, iclass 28, count 0 2006.183.08:16:01.91#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:16:01.91#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:16:01.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:16:01.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:16:01.91$vc4f8/vblo=5,744.99 2006.183.08:16:01.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:16:01.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:16:01.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:16:01.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:16:01.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:16:01.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:16:01.91#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:16:01.91#ibcon#first serial, iclass 30, count 0 2006.183.08:16:01.91#ibcon#enter sib2, iclass 30, count 0 2006.183.08:16:01.91#ibcon#flushed, iclass 30, count 0 2006.183.08:16:01.91#ibcon#about to write, iclass 30, count 0 2006.183.08:16:01.91#ibcon#wrote, iclass 30, count 0 2006.183.08:16:01.91#ibcon#about to read 3, iclass 30, count 0 2006.183.08:16:01.93#ibcon#read 3, iclass 30, count 0 2006.183.08:16:01.93#ibcon#about to read 4, iclass 30, count 0 2006.183.08:16:01.93#ibcon#read 4, iclass 30, count 0 2006.183.08:16:01.93#ibcon#about to read 5, iclass 30, count 0 2006.183.08:16:01.93#ibcon#read 5, iclass 30, count 0 2006.183.08:16:01.93#ibcon#about to read 6, iclass 30, count 0 2006.183.08:16:01.93#ibcon#read 6, iclass 30, count 0 2006.183.08:16:01.93#ibcon#end of sib2, iclass 30, count 0 2006.183.08:16:01.93#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:16:01.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:16:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:16:01.93#ibcon#*before write, iclass 30, count 0 2006.183.08:16:01.93#ibcon#enter sib2, iclass 30, count 0 2006.183.08:16:01.93#ibcon#flushed, iclass 30, count 0 2006.183.08:16:01.93#ibcon#about to write, iclass 30, count 0 2006.183.08:16:01.93#ibcon#wrote, iclass 30, count 0 2006.183.08:16:01.93#ibcon#about to read 3, iclass 30, count 0 2006.183.08:16:01.97#ibcon#read 3, iclass 30, count 0 2006.183.08:16:01.97#ibcon#about to read 4, iclass 30, count 0 2006.183.08:16:01.97#ibcon#read 4, iclass 30, count 0 2006.183.08:16:01.97#ibcon#about to read 5, iclass 30, count 0 2006.183.08:16:01.97#ibcon#read 5, iclass 30, count 0 2006.183.08:16:01.97#ibcon#about to read 6, iclass 30, count 0 2006.183.08:16:01.97#ibcon#read 6, iclass 30, count 0 2006.183.08:16:01.97#ibcon#end of sib2, iclass 30, count 0 2006.183.08:16:01.97#ibcon#*after write, iclass 30, count 0 2006.183.08:16:01.97#ibcon#*before return 0, iclass 30, count 0 2006.183.08:16:01.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:16:01.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:16:01.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:16:01.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:16:01.97$vc4f8/vb=5,4 2006.183.08:16:01.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.08:16:01.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.08:16:01.97#ibcon#ireg 11 cls_cnt 2 2006.183.08:16:01.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:16:02.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:16:02.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:16:02.03#ibcon#enter wrdev, iclass 32, count 2 2006.183.08:16:02.03#ibcon#first serial, iclass 32, count 2 2006.183.08:16:02.03#ibcon#enter sib2, iclass 32, count 2 2006.183.08:16:02.03#ibcon#flushed, iclass 32, count 2 2006.183.08:16:02.03#ibcon#about to write, iclass 32, count 2 2006.183.08:16:02.03#ibcon#wrote, iclass 32, count 2 2006.183.08:16:02.03#ibcon#about to read 3, iclass 32, count 2 2006.183.08:16:02.05#ibcon#read 3, iclass 32, count 2 2006.183.08:16:02.05#ibcon#about to read 4, iclass 32, count 2 2006.183.08:16:02.05#ibcon#read 4, iclass 32, count 2 2006.183.08:16:02.05#ibcon#about to read 5, iclass 32, count 2 2006.183.08:16:02.05#ibcon#read 5, iclass 32, count 2 2006.183.08:16:02.05#ibcon#about to read 6, iclass 32, count 2 2006.183.08:16:02.05#ibcon#read 6, iclass 32, count 2 2006.183.08:16:02.05#ibcon#end of sib2, iclass 32, count 2 2006.183.08:16:02.05#ibcon#*mode == 0, iclass 32, count 2 2006.183.08:16:02.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.08:16:02.05#ibcon#[27=AT05-04\r\n] 2006.183.08:16:02.05#ibcon#*before write, iclass 32, count 2 2006.183.08:16:02.05#ibcon#enter sib2, iclass 32, count 2 2006.183.08:16:02.05#ibcon#flushed, iclass 32, count 2 2006.183.08:16:02.05#ibcon#about to write, iclass 32, count 2 2006.183.08:16:02.05#ibcon#wrote, iclass 32, count 2 2006.183.08:16:02.05#ibcon#about to read 3, iclass 32, count 2 2006.183.08:16:02.08#ibcon#read 3, iclass 32, count 2 2006.183.08:16:02.08#ibcon#about to read 4, iclass 32, count 2 2006.183.08:16:02.08#ibcon#read 4, iclass 32, count 2 2006.183.08:16:02.08#ibcon#about to read 5, iclass 32, count 2 2006.183.08:16:02.08#ibcon#read 5, iclass 32, count 2 2006.183.08:16:02.08#ibcon#about to read 6, iclass 32, count 2 2006.183.08:16:02.08#ibcon#read 6, iclass 32, count 2 2006.183.08:16:02.08#ibcon#end of sib2, iclass 32, count 2 2006.183.08:16:02.08#ibcon#*after write, iclass 32, count 2 2006.183.08:16:02.08#ibcon#*before return 0, iclass 32, count 2 2006.183.08:16:02.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:16:02.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:16:02.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.08:16:02.08#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:02.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:16:02.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:16:02.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:16:02.20#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:16:02.20#ibcon#first serial, iclass 32, count 0 2006.183.08:16:02.20#ibcon#enter sib2, iclass 32, count 0 2006.183.08:16:02.20#ibcon#flushed, iclass 32, count 0 2006.183.08:16:02.20#ibcon#about to write, iclass 32, count 0 2006.183.08:16:02.20#ibcon#wrote, iclass 32, count 0 2006.183.08:16:02.20#ibcon#about to read 3, iclass 32, count 0 2006.183.08:16:02.22#ibcon#read 3, iclass 32, count 0 2006.183.08:16:02.22#ibcon#about to read 4, iclass 32, count 0 2006.183.08:16:02.22#ibcon#read 4, iclass 32, count 0 2006.183.08:16:02.22#ibcon#about to read 5, iclass 32, count 0 2006.183.08:16:02.22#ibcon#read 5, iclass 32, count 0 2006.183.08:16:02.22#ibcon#about to read 6, iclass 32, count 0 2006.183.08:16:02.22#ibcon#read 6, iclass 32, count 0 2006.183.08:16:02.22#ibcon#end of sib2, iclass 32, count 0 2006.183.08:16:02.22#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:16:02.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:16:02.22#ibcon#[27=USB\r\n] 2006.183.08:16:02.22#ibcon#*before write, iclass 32, count 0 2006.183.08:16:02.22#ibcon#enter sib2, iclass 32, count 0 2006.183.08:16:02.22#ibcon#flushed, iclass 32, count 0 2006.183.08:16:02.22#ibcon#about to write, iclass 32, count 0 2006.183.08:16:02.22#ibcon#wrote, iclass 32, count 0 2006.183.08:16:02.22#ibcon#about to read 3, iclass 32, count 0 2006.183.08:16:02.25#ibcon#read 3, iclass 32, count 0 2006.183.08:16:02.25#ibcon#about to read 4, iclass 32, count 0 2006.183.08:16:02.25#ibcon#read 4, iclass 32, count 0 2006.183.08:16:02.25#ibcon#about to read 5, iclass 32, count 0 2006.183.08:16:02.25#ibcon#read 5, iclass 32, count 0 2006.183.08:16:02.25#ibcon#about to read 6, iclass 32, count 0 2006.183.08:16:02.25#ibcon#read 6, iclass 32, count 0 2006.183.08:16:02.25#ibcon#end of sib2, iclass 32, count 0 2006.183.08:16:02.25#ibcon#*after write, iclass 32, count 0 2006.183.08:16:02.25#ibcon#*before return 0, iclass 32, count 0 2006.183.08:16:02.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:16:02.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:16:02.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:16:02.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:16:02.25$vc4f8/vblo=6,752.99 2006.183.08:16:02.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.08:16:02.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.08:16:02.25#ibcon#ireg 17 cls_cnt 0 2006.183.08:16:02.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:16:02.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:16:02.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:16:02.25#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:16:02.25#ibcon#first serial, iclass 34, count 0 2006.183.08:16:02.25#ibcon#enter sib2, iclass 34, count 0 2006.183.08:16:02.25#ibcon#flushed, iclass 34, count 0 2006.183.08:16:02.25#ibcon#about to write, iclass 34, count 0 2006.183.08:16:02.25#ibcon#wrote, iclass 34, count 0 2006.183.08:16:02.25#ibcon#about to read 3, iclass 34, count 0 2006.183.08:16:02.27#ibcon#read 3, iclass 34, count 0 2006.183.08:16:02.27#ibcon#about to read 4, iclass 34, count 0 2006.183.08:16:02.27#ibcon#read 4, iclass 34, count 0 2006.183.08:16:02.27#ibcon#about to read 5, iclass 34, count 0 2006.183.08:16:02.27#ibcon#read 5, iclass 34, count 0 2006.183.08:16:02.27#ibcon#about to read 6, iclass 34, count 0 2006.183.08:16:02.27#ibcon#read 6, iclass 34, count 0 2006.183.08:16:02.27#ibcon#end of sib2, iclass 34, count 0 2006.183.08:16:02.27#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:16:02.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:16:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:16:02.27#ibcon#*before write, iclass 34, count 0 2006.183.08:16:02.27#ibcon#enter sib2, iclass 34, count 0 2006.183.08:16:02.27#ibcon#flushed, iclass 34, count 0 2006.183.08:16:02.27#ibcon#about to write, iclass 34, count 0 2006.183.08:16:02.27#ibcon#wrote, iclass 34, count 0 2006.183.08:16:02.27#ibcon#about to read 3, iclass 34, count 0 2006.183.08:16:02.31#ibcon#read 3, iclass 34, count 0 2006.183.08:16:02.31#ibcon#about to read 4, iclass 34, count 0 2006.183.08:16:02.31#ibcon#read 4, iclass 34, count 0 2006.183.08:16:02.31#ibcon#about to read 5, iclass 34, count 0 2006.183.08:16:02.31#ibcon#read 5, iclass 34, count 0 2006.183.08:16:02.31#ibcon#about to read 6, iclass 34, count 0 2006.183.08:16:02.31#ibcon#read 6, iclass 34, count 0 2006.183.08:16:02.31#ibcon#end of sib2, iclass 34, count 0 2006.183.08:16:02.31#ibcon#*after write, iclass 34, count 0 2006.183.08:16:02.31#ibcon#*before return 0, iclass 34, count 0 2006.183.08:16:02.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:16:02.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:16:02.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:16:02.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:16:02.31$vc4f8/vb=6,4 2006.183.08:16:02.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.08:16:02.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.08:16:02.31#ibcon#ireg 11 cls_cnt 2 2006.183.08:16:02.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:16:02.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:16:02.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:16:02.37#ibcon#enter wrdev, iclass 36, count 2 2006.183.08:16:02.37#ibcon#first serial, iclass 36, count 2 2006.183.08:16:02.37#ibcon#enter sib2, iclass 36, count 2 2006.183.08:16:02.37#ibcon#flushed, iclass 36, count 2 2006.183.08:16:02.37#ibcon#about to write, iclass 36, count 2 2006.183.08:16:02.37#ibcon#wrote, iclass 36, count 2 2006.183.08:16:02.37#ibcon#about to read 3, iclass 36, count 2 2006.183.08:16:02.39#ibcon#read 3, iclass 36, count 2 2006.183.08:16:02.39#ibcon#about to read 4, iclass 36, count 2 2006.183.08:16:02.39#ibcon#read 4, iclass 36, count 2 2006.183.08:16:02.39#ibcon#about to read 5, iclass 36, count 2 2006.183.08:16:02.39#ibcon#read 5, iclass 36, count 2 2006.183.08:16:02.39#ibcon#about to read 6, iclass 36, count 2 2006.183.08:16:02.39#ibcon#read 6, iclass 36, count 2 2006.183.08:16:02.39#ibcon#end of sib2, iclass 36, count 2 2006.183.08:16:02.39#ibcon#*mode == 0, iclass 36, count 2 2006.183.08:16:02.39#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.08:16:02.39#ibcon#[27=AT06-04\r\n] 2006.183.08:16:02.39#ibcon#*before write, iclass 36, count 2 2006.183.08:16:02.39#ibcon#enter sib2, iclass 36, count 2 2006.183.08:16:02.39#ibcon#flushed, iclass 36, count 2 2006.183.08:16:02.39#ibcon#about to write, iclass 36, count 2 2006.183.08:16:02.39#ibcon#wrote, iclass 36, count 2 2006.183.08:16:02.39#ibcon#about to read 3, iclass 36, count 2 2006.183.08:16:02.42#ibcon#read 3, iclass 36, count 2 2006.183.08:16:02.42#ibcon#about to read 4, iclass 36, count 2 2006.183.08:16:02.42#ibcon#read 4, iclass 36, count 2 2006.183.08:16:02.42#ibcon#about to read 5, iclass 36, count 2 2006.183.08:16:02.42#ibcon#read 5, iclass 36, count 2 2006.183.08:16:02.42#ibcon#about to read 6, iclass 36, count 2 2006.183.08:16:02.42#ibcon#read 6, iclass 36, count 2 2006.183.08:16:02.42#ibcon#end of sib2, iclass 36, count 2 2006.183.08:16:02.42#ibcon#*after write, iclass 36, count 2 2006.183.08:16:02.42#ibcon#*before return 0, iclass 36, count 2 2006.183.08:16:02.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:16:02.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:16:02.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.08:16:02.42#ibcon#ireg 7 cls_cnt 0 2006.183.08:16:02.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:16:02.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:16:02.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:16:02.54#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:16:02.54#ibcon#first serial, iclass 36, count 0 2006.183.08:16:02.54#ibcon#enter sib2, iclass 36, count 0 2006.183.08:16:02.54#ibcon#flushed, iclass 36, count 0 2006.183.08:16:02.54#ibcon#about to write, iclass 36, count 0 2006.183.08:16:02.54#ibcon#wrote, iclass 36, count 0 2006.183.08:16:02.54#ibcon#about to read 3, iclass 36, count 0 2006.183.08:16:02.56#ibcon#read 3, iclass 36, count 0 2006.183.08:16:02.56#ibcon#about to read 4, iclass 36, count 0 2006.183.08:16:02.56#ibcon#read 4, iclass 36, count 0 2006.183.08:16:02.56#ibcon#about to read 5, iclass 36, count 0 2006.183.08:16:02.56#ibcon#read 5, iclass 36, count 0 2006.183.08:16:02.56#ibcon#about to read 6, iclass 36, count 0 2006.183.08:16:02.56#ibcon#read 6, iclass 36, count 0 2006.183.08:16:02.56#ibcon#end of sib2, iclass 36, count 0 2006.183.08:16:02.56#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:16:02.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:16:02.56#ibcon#[27=USB\r\n] 2006.183.08:16:02.56#ibcon#*before write, iclass 36, count 0 2006.183.08:16:02.56#ibcon#enter sib2, iclass 36, count 0 2006.183.08:16:02.56#ibcon#flushed, iclass 36, count 0 2006.183.08:16:02.56#ibcon#about to write, iclass 36, count 0 2006.183.08:16:02.56#ibcon#wrote, iclass 36, count 0 2006.183.08:16:02.56#ibcon#about to read 3, iclass 36, count 0 2006.183.08:16:02.59#ibcon#read 3, iclass 36, count 0 2006.183.08:16:02.59#ibcon#about to read 4, iclass 36, count 0 2006.183.08:16:02.59#ibcon#read 4, iclass 36, count 0 2006.183.08:16:02.59#ibcon#about to read 5, iclass 36, count 0 2006.183.08:16:02.59#ibcon#read 5, iclass 36, count 0 2006.183.08:16:02.59#ibcon#about to read 6, iclass 36, count 0 2006.183.08:16:02.59#ibcon#read 6, iclass 36, count 0 2006.183.08:16:02.59#ibcon#end of sib2, iclass 36, count 0 2006.183.08:16:02.59#ibcon#*after write, iclass 36, count 0 2006.183.08:16:02.59#ibcon#*before return 0, iclass 36, count 0 2006.183.08:16:02.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:16:02.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:16:02.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:16:02.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:16:02.59$vc4f8/vabw=wide 2006.183.08:16:02.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.08:16:02.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.08:16:02.59#ibcon#ireg 8 cls_cnt 0 2006.183.08:16:02.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:16:02.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:16:02.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:16:02.59#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:16:02.59#ibcon#first serial, iclass 38, count 0 2006.183.08:16:02.59#ibcon#enter sib2, iclass 38, count 0 2006.183.08:16:02.59#ibcon#flushed, iclass 38, count 0 2006.183.08:16:02.59#ibcon#about to write, iclass 38, count 0 2006.183.08:16:02.59#ibcon#wrote, iclass 38, count 0 2006.183.08:16:02.59#ibcon#about to read 3, iclass 38, count 0 2006.183.08:16:02.61#ibcon#read 3, iclass 38, count 0 2006.183.08:16:02.61#ibcon#about to read 4, iclass 38, count 0 2006.183.08:16:02.61#ibcon#read 4, iclass 38, count 0 2006.183.08:16:02.61#ibcon#about to read 5, iclass 38, count 0 2006.183.08:16:02.61#ibcon#read 5, iclass 38, count 0 2006.183.08:16:02.61#ibcon#about to read 6, iclass 38, count 0 2006.183.08:16:02.61#ibcon#read 6, iclass 38, count 0 2006.183.08:16:02.61#ibcon#end of sib2, iclass 38, count 0 2006.183.08:16:02.61#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:16:02.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:16:02.61#ibcon#[25=BW32\r\n] 2006.183.08:16:02.61#ibcon#*before write, iclass 38, count 0 2006.183.08:16:02.61#ibcon#enter sib2, iclass 38, count 0 2006.183.08:16:02.61#ibcon#flushed, iclass 38, count 0 2006.183.08:16:02.61#ibcon#about to write, iclass 38, count 0 2006.183.08:16:02.61#ibcon#wrote, iclass 38, count 0 2006.183.08:16:02.61#ibcon#about to read 3, iclass 38, count 0 2006.183.08:16:02.64#ibcon#read 3, iclass 38, count 0 2006.183.08:16:02.64#ibcon#about to read 4, iclass 38, count 0 2006.183.08:16:02.64#ibcon#read 4, iclass 38, count 0 2006.183.08:16:02.64#ibcon#about to read 5, iclass 38, count 0 2006.183.08:16:02.64#ibcon#read 5, iclass 38, count 0 2006.183.08:16:02.64#ibcon#about to read 6, iclass 38, count 0 2006.183.08:16:02.64#ibcon#read 6, iclass 38, count 0 2006.183.08:16:02.64#ibcon#end of sib2, iclass 38, count 0 2006.183.08:16:02.64#ibcon#*after write, iclass 38, count 0 2006.183.08:16:02.64#ibcon#*before return 0, iclass 38, count 0 2006.183.08:16:02.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:16:02.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:16:02.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:16:02.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:16:02.64$vc4f8/vbbw=wide 2006.183.08:16:02.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.08:16:02.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.08:16:02.64#ibcon#ireg 8 cls_cnt 0 2006.183.08:16:02.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:16:02.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:16:02.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:16:02.71#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:16:02.71#ibcon#first serial, iclass 40, count 0 2006.183.08:16:02.71#ibcon#enter sib2, iclass 40, count 0 2006.183.08:16:02.71#ibcon#flushed, iclass 40, count 0 2006.183.08:16:02.71#ibcon#about to write, iclass 40, count 0 2006.183.08:16:02.71#ibcon#wrote, iclass 40, count 0 2006.183.08:16:02.71#ibcon#about to read 3, iclass 40, count 0 2006.183.08:16:02.73#ibcon#read 3, iclass 40, count 0 2006.183.08:16:02.73#ibcon#about to read 4, iclass 40, count 0 2006.183.08:16:02.73#ibcon#read 4, iclass 40, count 0 2006.183.08:16:02.73#ibcon#about to read 5, iclass 40, count 0 2006.183.08:16:02.73#ibcon#read 5, iclass 40, count 0 2006.183.08:16:02.73#ibcon#about to read 6, iclass 40, count 0 2006.183.08:16:02.73#ibcon#read 6, iclass 40, count 0 2006.183.08:16:02.73#ibcon#end of sib2, iclass 40, count 0 2006.183.08:16:02.73#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:16:02.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:16:02.73#ibcon#[27=BW32\r\n] 2006.183.08:16:02.73#ibcon#*before write, iclass 40, count 0 2006.183.08:16:02.73#ibcon#enter sib2, iclass 40, count 0 2006.183.08:16:02.73#ibcon#flushed, iclass 40, count 0 2006.183.08:16:02.73#ibcon#about to write, iclass 40, count 0 2006.183.08:16:02.73#ibcon#wrote, iclass 40, count 0 2006.183.08:16:02.73#ibcon#about to read 3, iclass 40, count 0 2006.183.08:16:02.76#ibcon#read 3, iclass 40, count 0 2006.183.08:16:02.76#ibcon#about to read 4, iclass 40, count 0 2006.183.08:16:02.76#ibcon#read 4, iclass 40, count 0 2006.183.08:16:02.76#ibcon#about to read 5, iclass 40, count 0 2006.183.08:16:02.76#ibcon#read 5, iclass 40, count 0 2006.183.08:16:02.76#ibcon#about to read 6, iclass 40, count 0 2006.183.08:16:02.76#ibcon#read 6, iclass 40, count 0 2006.183.08:16:02.76#ibcon#end of sib2, iclass 40, count 0 2006.183.08:16:02.76#ibcon#*after write, iclass 40, count 0 2006.183.08:16:02.76#ibcon#*before return 0, iclass 40, count 0 2006.183.08:16:02.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:16:02.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:16:02.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:16:02.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:16:02.76$4f8m12a/ifd4f 2006.183.08:16:02.76$ifd4f/lo= 2006.183.08:16:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:16:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:16:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:16:02.76$ifd4f/patch= 2006.183.08:16:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:16:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:16:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:16:02.76$4f8m12a/"form=m,16.000,1:2 2006.183.08:16:02.77$4f8m12a/"tpicd 2006.183.08:16:02.77$4f8m12a/echo=off 2006.183.08:16:02.77$4f8m12a/xlog=off 2006.183.08:16:02.77:!2006.183.08:16:40 2006.183.08:16:19.13#trakl#Source acquired 2006.183.08:16:21.13#flagr#flagr/antenna,acquired 2006.183.08:16:40.01:preob 2006.183.08:16:41.14/onsource/TRACKING 2006.183.08:16:41.14:!2006.183.08:16:50 2006.183.08:16:50.00:data_valid=on 2006.183.08:16:50.00:midob 2006.183.08:16:50.14/onsource/TRACKING 2006.183.08:16:50.14/wx/28.33,996.6,86 2006.183.08:16:50.24/cable/+6.4504E-03 2006.183.08:16:51.33/va/01,08,usb,yes,28,30 2006.183.08:16:51.33/va/02,07,usb,yes,28,30 2006.183.08:16:51.33/va/03,06,usb,yes,30,30 2006.183.08:16:51.33/va/04,07,usb,yes,29,31 2006.183.08:16:51.33/va/05,07,usb,yes,30,32 2006.183.08:16:51.33/va/06,06,usb,yes,29,29 2006.183.08:16:51.33/va/07,06,usb,yes,30,30 2006.183.08:16:51.33/va/08,07,usb,yes,28,28 2006.183.08:16:51.56/valo/01,532.99,yes,locked 2006.183.08:16:51.56/valo/02,572.99,yes,locked 2006.183.08:16:51.56/valo/03,672.99,yes,locked 2006.183.08:16:51.56/valo/04,832.99,yes,locked 2006.183.08:16:51.56/valo/05,652.99,yes,locked 2006.183.08:16:51.56/valo/06,772.99,yes,locked 2006.183.08:16:51.56/valo/07,832.99,yes,locked 2006.183.08:16:51.56/valo/08,852.99,yes,locked 2006.183.08:16:52.65/vb/01,04,usb,yes,29,27 2006.183.08:16:52.65/vb/02,04,usb,yes,30,32 2006.183.08:16:52.65/vb/03,04,usb,yes,27,30 2006.183.08:16:52.65/vb/04,04,usb,yes,28,28 2006.183.08:16:52.65/vb/05,04,usb,yes,26,30 2006.183.08:16:52.65/vb/06,04,usb,yes,27,30 2006.183.08:16:52.65/vb/07,04,usb,yes,29,29 2006.183.08:16:52.65/vb/08,04,usb,yes,27,30 2006.183.08:16:52.89/vblo/01,632.99,yes,locked 2006.183.08:16:52.89/vblo/02,640.99,yes,locked 2006.183.08:16:52.89/vblo/03,656.99,yes,locked 2006.183.08:16:52.89/vblo/04,712.99,yes,locked 2006.183.08:16:52.89/vblo/05,744.99,yes,locked 2006.183.08:16:52.89/vblo/06,752.99,yes,locked 2006.183.08:16:52.89/vblo/07,734.99,yes,locked 2006.183.08:16:52.89/vblo/08,744.99,yes,locked 2006.183.08:16:53.04/vabw/8 2006.183.08:16:53.19/vbbw/8 2006.183.08:16:53.28/xfe/off,on,15.5 2006.183.08:16:53.65/ifatt/23,28,28,28 2006.183.08:16:54.07/fmout-gps/S +3.37E-07 2006.183.08:16:54.12:!2006.183.08:17:50 2006.183.08:17:50.01:data_valid=off 2006.183.08:17:50.01:postob 2006.183.08:17:50.09/cable/+6.4500E-03 2006.183.08:17:50.09/wx/28.32,996.6,86 2006.183.08:17:51.07/fmout-gps/S +3.38E-07 2006.183.08:17:51.07:scan_name=183-0819,k06183,60 2006.183.08:17:51.07:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.183.08:17:52.14#flagr#flagr/antenna,new-source 2006.183.08:17:52.14:checkk5 2006.183.08:17:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:17:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:17:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:17:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:17:54.03/chk_obsdata//k5ts1/T1830816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:17:54.39/chk_obsdata//k5ts2/T1830816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:17:54.77/chk_obsdata//k5ts3/T1830816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:17:55.14/chk_obsdata//k5ts4/T1830816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:17:55.85/k5log//k5ts1_log_newline 2006.183.08:17:56.55/k5log//k5ts2_log_newline 2006.183.08:17:57.25/k5log//k5ts3_log_newline 2006.183.08:17:57.95/k5log//k5ts4_log_newline 2006.183.08:17:57.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:17:57.97:4f8m12a=3 2006.183.08:17:57.97$4f8m12a/echo=on 2006.183.08:17:57.97$4f8m12a/pcalon 2006.183.08:17:57.97$pcalon/"no phase cal control is implemented here 2006.183.08:17:57.97$4f8m12a/"tpicd=stop 2006.183.08:17:57.97$4f8m12a/vc4f8 2006.183.08:17:57.97$vc4f8/valo=1,532.99 2006.183.08:17:57.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.08:17:57.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.08:17:57.98#ibcon#ireg 17 cls_cnt 0 2006.183.08:17:57.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:17:57.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:17:57.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:17:57.98#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:17:57.98#ibcon#first serial, iclass 19, count 0 2006.183.08:17:57.98#ibcon#enter sib2, iclass 19, count 0 2006.183.08:17:57.98#ibcon#flushed, iclass 19, count 0 2006.183.08:17:57.98#ibcon#about to write, iclass 19, count 0 2006.183.08:17:57.98#ibcon#wrote, iclass 19, count 0 2006.183.08:17:57.98#ibcon#about to read 3, iclass 19, count 0 2006.183.08:17:58.02#ibcon#read 3, iclass 19, count 0 2006.183.08:17:58.02#ibcon#about to read 4, iclass 19, count 0 2006.183.08:17:58.02#ibcon#read 4, iclass 19, count 0 2006.183.08:17:58.02#ibcon#about to read 5, iclass 19, count 0 2006.183.08:17:58.02#ibcon#read 5, iclass 19, count 0 2006.183.08:17:58.02#ibcon#about to read 6, iclass 19, count 0 2006.183.08:17:58.02#ibcon#read 6, iclass 19, count 0 2006.183.08:17:58.02#ibcon#end of sib2, iclass 19, count 0 2006.183.08:17:58.02#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:17:58.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:17:58.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:17:58.02#ibcon#*before write, iclass 19, count 0 2006.183.08:17:58.02#ibcon#enter sib2, iclass 19, count 0 2006.183.08:17:58.02#ibcon#flushed, iclass 19, count 0 2006.183.08:17:58.02#ibcon#about to write, iclass 19, count 0 2006.183.08:17:58.02#ibcon#wrote, iclass 19, count 0 2006.183.08:17:58.02#ibcon#about to read 3, iclass 19, count 0 2006.183.08:17:58.06#ibcon#read 3, iclass 19, count 0 2006.183.08:17:58.06#ibcon#about to read 4, iclass 19, count 0 2006.183.08:17:58.06#ibcon#read 4, iclass 19, count 0 2006.183.08:17:58.06#ibcon#about to read 5, iclass 19, count 0 2006.183.08:17:58.06#ibcon#read 5, iclass 19, count 0 2006.183.08:17:58.06#ibcon#about to read 6, iclass 19, count 0 2006.183.08:17:58.06#ibcon#read 6, iclass 19, count 0 2006.183.08:17:58.06#ibcon#end of sib2, iclass 19, count 0 2006.183.08:17:58.06#ibcon#*after write, iclass 19, count 0 2006.183.08:17:58.06#ibcon#*before return 0, iclass 19, count 0 2006.183.08:17:58.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:17:58.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:17:58.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:17:58.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:17:58.06$vc4f8/va=1,8 2006.183.08:17:58.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.08:17:58.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.08:17:58.06#ibcon#ireg 11 cls_cnt 2 2006.183.08:17:58.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:17:58.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:17:58.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:17:58.06#ibcon#enter wrdev, iclass 21, count 2 2006.183.08:17:58.06#ibcon#first serial, iclass 21, count 2 2006.183.08:17:58.06#ibcon#enter sib2, iclass 21, count 2 2006.183.08:17:58.06#ibcon#flushed, iclass 21, count 2 2006.183.08:17:58.06#ibcon#about to write, iclass 21, count 2 2006.183.08:17:58.06#ibcon#wrote, iclass 21, count 2 2006.183.08:17:58.06#ibcon#about to read 3, iclass 21, count 2 2006.183.08:17:58.09#ibcon#read 3, iclass 21, count 2 2006.183.08:17:58.09#ibcon#about to read 4, iclass 21, count 2 2006.183.08:17:58.09#ibcon#read 4, iclass 21, count 2 2006.183.08:17:58.09#ibcon#about to read 5, iclass 21, count 2 2006.183.08:17:58.09#ibcon#read 5, iclass 21, count 2 2006.183.08:17:58.09#ibcon#about to read 6, iclass 21, count 2 2006.183.08:17:58.09#ibcon#read 6, iclass 21, count 2 2006.183.08:17:58.09#ibcon#end of sib2, iclass 21, count 2 2006.183.08:17:58.09#ibcon#*mode == 0, iclass 21, count 2 2006.183.08:17:58.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.08:17:58.09#ibcon#[25=AT01-08\r\n] 2006.183.08:17:58.09#ibcon#*before write, iclass 21, count 2 2006.183.08:17:58.09#ibcon#enter sib2, iclass 21, count 2 2006.183.08:17:58.09#ibcon#flushed, iclass 21, count 2 2006.183.08:17:58.09#ibcon#about to write, iclass 21, count 2 2006.183.08:17:58.09#ibcon#wrote, iclass 21, count 2 2006.183.08:17:58.09#ibcon#about to read 3, iclass 21, count 2 2006.183.08:17:58.12#ibcon#read 3, iclass 21, count 2 2006.183.08:17:58.12#ibcon#about to read 4, iclass 21, count 2 2006.183.08:17:58.12#ibcon#read 4, iclass 21, count 2 2006.183.08:17:58.12#ibcon#about to read 5, iclass 21, count 2 2006.183.08:17:58.12#ibcon#read 5, iclass 21, count 2 2006.183.08:17:58.12#ibcon#about to read 6, iclass 21, count 2 2006.183.08:17:58.12#ibcon#read 6, iclass 21, count 2 2006.183.08:17:58.12#ibcon#end of sib2, iclass 21, count 2 2006.183.08:17:58.12#ibcon#*after write, iclass 21, count 2 2006.183.08:17:58.12#ibcon#*before return 0, iclass 21, count 2 2006.183.08:17:58.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:17:58.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:17:58.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.08:17:58.12#ibcon#ireg 7 cls_cnt 0 2006.183.08:17:58.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:17:58.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:17:58.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:17:58.24#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:17:58.24#ibcon#first serial, iclass 21, count 0 2006.183.08:17:58.24#ibcon#enter sib2, iclass 21, count 0 2006.183.08:17:58.24#ibcon#flushed, iclass 21, count 0 2006.183.08:17:58.24#ibcon#about to write, iclass 21, count 0 2006.183.08:17:58.24#ibcon#wrote, iclass 21, count 0 2006.183.08:17:58.24#ibcon#about to read 3, iclass 21, count 0 2006.183.08:17:58.26#ibcon#read 3, iclass 21, count 0 2006.183.08:17:58.26#ibcon#about to read 4, iclass 21, count 0 2006.183.08:17:58.26#ibcon#read 4, iclass 21, count 0 2006.183.08:17:58.26#ibcon#about to read 5, iclass 21, count 0 2006.183.08:17:58.26#ibcon#read 5, iclass 21, count 0 2006.183.08:17:58.26#ibcon#about to read 6, iclass 21, count 0 2006.183.08:17:58.26#ibcon#read 6, iclass 21, count 0 2006.183.08:17:58.26#ibcon#end of sib2, iclass 21, count 0 2006.183.08:17:58.26#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:17:58.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:17:58.26#ibcon#[25=USB\r\n] 2006.183.08:17:58.26#ibcon#*before write, iclass 21, count 0 2006.183.08:17:58.26#ibcon#enter sib2, iclass 21, count 0 2006.183.08:17:58.26#ibcon#flushed, iclass 21, count 0 2006.183.08:17:58.26#ibcon#about to write, iclass 21, count 0 2006.183.08:17:58.26#ibcon#wrote, iclass 21, count 0 2006.183.08:17:58.26#ibcon#about to read 3, iclass 21, count 0 2006.183.08:17:58.29#ibcon#read 3, iclass 21, count 0 2006.183.08:17:58.29#ibcon#about to read 4, iclass 21, count 0 2006.183.08:17:58.29#ibcon#read 4, iclass 21, count 0 2006.183.08:17:58.29#ibcon#about to read 5, iclass 21, count 0 2006.183.08:17:58.29#ibcon#read 5, iclass 21, count 0 2006.183.08:17:58.29#ibcon#about to read 6, iclass 21, count 0 2006.183.08:17:58.29#ibcon#read 6, iclass 21, count 0 2006.183.08:17:58.29#ibcon#end of sib2, iclass 21, count 0 2006.183.08:17:58.29#ibcon#*after write, iclass 21, count 0 2006.183.08:17:58.29#ibcon#*before return 0, iclass 21, count 0 2006.183.08:17:58.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:17:58.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:17:58.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:17:58.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:17:58.29$vc4f8/valo=2,572.99 2006.183.08:17:58.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:17:58.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:17:58.29#ibcon#ireg 17 cls_cnt 0 2006.183.08:17:58.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:17:58.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:17:58.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:17:58.29#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:17:58.29#ibcon#first serial, iclass 23, count 0 2006.183.08:17:58.29#ibcon#enter sib2, iclass 23, count 0 2006.183.08:17:58.29#ibcon#flushed, iclass 23, count 0 2006.183.08:17:58.29#ibcon#about to write, iclass 23, count 0 2006.183.08:17:58.29#ibcon#wrote, iclass 23, count 0 2006.183.08:17:58.29#ibcon#about to read 3, iclass 23, count 0 2006.183.08:17:58.31#ibcon#read 3, iclass 23, count 0 2006.183.08:17:58.31#ibcon#about to read 4, iclass 23, count 0 2006.183.08:17:58.31#ibcon#read 4, iclass 23, count 0 2006.183.08:17:58.31#ibcon#about to read 5, iclass 23, count 0 2006.183.08:17:58.31#ibcon#read 5, iclass 23, count 0 2006.183.08:17:58.31#ibcon#about to read 6, iclass 23, count 0 2006.183.08:17:58.31#ibcon#read 6, iclass 23, count 0 2006.183.08:17:58.31#ibcon#end of sib2, iclass 23, count 0 2006.183.08:17:58.31#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:17:58.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:17:58.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:17:58.31#ibcon#*before write, iclass 23, count 0 2006.183.08:17:58.31#ibcon#enter sib2, iclass 23, count 0 2006.183.08:17:58.31#ibcon#flushed, iclass 23, count 0 2006.183.08:17:58.31#ibcon#about to write, iclass 23, count 0 2006.183.08:17:58.31#ibcon#wrote, iclass 23, count 0 2006.183.08:17:58.31#ibcon#about to read 3, iclass 23, count 0 2006.183.08:17:58.35#ibcon#read 3, iclass 23, count 0 2006.183.08:17:58.35#ibcon#about to read 4, iclass 23, count 0 2006.183.08:17:58.35#ibcon#read 4, iclass 23, count 0 2006.183.08:17:58.35#ibcon#about to read 5, iclass 23, count 0 2006.183.08:17:58.35#ibcon#read 5, iclass 23, count 0 2006.183.08:17:58.35#ibcon#about to read 6, iclass 23, count 0 2006.183.08:17:58.35#ibcon#read 6, iclass 23, count 0 2006.183.08:17:58.35#ibcon#end of sib2, iclass 23, count 0 2006.183.08:17:58.35#ibcon#*after write, iclass 23, count 0 2006.183.08:17:58.35#ibcon#*before return 0, iclass 23, count 0 2006.183.08:17:58.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:17:58.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:17:58.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:17:58.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:17:58.35$vc4f8/va=2,7 2006.183.08:17:58.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.08:17:58.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.08:17:58.35#ibcon#ireg 11 cls_cnt 2 2006.183.08:17:58.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:17:58.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:17:58.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:17:58.42#ibcon#enter wrdev, iclass 25, count 2 2006.183.08:17:58.42#ibcon#first serial, iclass 25, count 2 2006.183.08:17:58.42#ibcon#enter sib2, iclass 25, count 2 2006.183.08:17:58.42#ibcon#flushed, iclass 25, count 2 2006.183.08:17:58.42#ibcon#about to write, iclass 25, count 2 2006.183.08:17:58.42#ibcon#wrote, iclass 25, count 2 2006.183.08:17:58.42#ibcon#about to read 3, iclass 25, count 2 2006.183.08:17:58.44#ibcon#read 3, iclass 25, count 2 2006.183.08:17:58.44#ibcon#about to read 4, iclass 25, count 2 2006.183.08:17:58.44#ibcon#read 4, iclass 25, count 2 2006.183.08:17:58.44#ibcon#about to read 5, iclass 25, count 2 2006.183.08:17:58.44#ibcon#read 5, iclass 25, count 2 2006.183.08:17:58.44#ibcon#about to read 6, iclass 25, count 2 2006.183.08:17:58.44#ibcon#read 6, iclass 25, count 2 2006.183.08:17:58.44#ibcon#end of sib2, iclass 25, count 2 2006.183.08:17:58.44#ibcon#*mode == 0, iclass 25, count 2 2006.183.08:17:58.44#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.08:17:58.44#ibcon#[25=AT02-07\r\n] 2006.183.08:17:58.44#ibcon#*before write, iclass 25, count 2 2006.183.08:17:58.44#ibcon#enter sib2, iclass 25, count 2 2006.183.08:17:58.44#ibcon#flushed, iclass 25, count 2 2006.183.08:17:58.44#ibcon#about to write, iclass 25, count 2 2006.183.08:17:58.44#ibcon#wrote, iclass 25, count 2 2006.183.08:17:58.44#ibcon#about to read 3, iclass 25, count 2 2006.183.08:17:58.46#ibcon#read 3, iclass 25, count 2 2006.183.08:17:58.46#ibcon#about to read 4, iclass 25, count 2 2006.183.08:17:58.46#ibcon#read 4, iclass 25, count 2 2006.183.08:17:58.46#ibcon#about to read 5, iclass 25, count 2 2006.183.08:17:58.46#ibcon#read 5, iclass 25, count 2 2006.183.08:17:58.46#ibcon#about to read 6, iclass 25, count 2 2006.183.08:17:58.46#ibcon#read 6, iclass 25, count 2 2006.183.08:17:58.46#ibcon#end of sib2, iclass 25, count 2 2006.183.08:17:58.46#ibcon#*after write, iclass 25, count 2 2006.183.08:17:58.46#ibcon#*before return 0, iclass 25, count 2 2006.183.08:17:58.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:17:58.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:17:58.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.08:17:58.46#ibcon#ireg 7 cls_cnt 0 2006.183.08:17:58.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:17:58.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:17:58.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:17:58.58#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:17:58.58#ibcon#first serial, iclass 25, count 0 2006.183.08:17:58.58#ibcon#enter sib2, iclass 25, count 0 2006.183.08:17:58.58#ibcon#flushed, iclass 25, count 0 2006.183.08:17:58.58#ibcon#about to write, iclass 25, count 0 2006.183.08:17:58.58#ibcon#wrote, iclass 25, count 0 2006.183.08:17:58.58#ibcon#about to read 3, iclass 25, count 0 2006.183.08:17:58.60#ibcon#read 3, iclass 25, count 0 2006.183.08:17:58.60#ibcon#about to read 4, iclass 25, count 0 2006.183.08:17:58.60#ibcon#read 4, iclass 25, count 0 2006.183.08:17:58.60#ibcon#about to read 5, iclass 25, count 0 2006.183.08:17:58.60#ibcon#read 5, iclass 25, count 0 2006.183.08:17:58.60#ibcon#about to read 6, iclass 25, count 0 2006.183.08:17:58.60#ibcon#read 6, iclass 25, count 0 2006.183.08:17:58.60#ibcon#end of sib2, iclass 25, count 0 2006.183.08:17:58.60#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:17:58.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:17:58.60#ibcon#[25=USB\r\n] 2006.183.08:17:58.60#ibcon#*before write, iclass 25, count 0 2006.183.08:17:58.60#ibcon#enter sib2, iclass 25, count 0 2006.183.08:17:58.60#ibcon#flushed, iclass 25, count 0 2006.183.08:17:58.60#ibcon#about to write, iclass 25, count 0 2006.183.08:17:58.60#ibcon#wrote, iclass 25, count 0 2006.183.08:17:58.60#ibcon#about to read 3, iclass 25, count 0 2006.183.08:17:58.63#ibcon#read 3, iclass 25, count 0 2006.183.08:17:58.63#ibcon#about to read 4, iclass 25, count 0 2006.183.08:17:58.63#ibcon#read 4, iclass 25, count 0 2006.183.08:17:58.63#ibcon#about to read 5, iclass 25, count 0 2006.183.08:17:58.63#ibcon#read 5, iclass 25, count 0 2006.183.08:17:58.63#ibcon#about to read 6, iclass 25, count 0 2006.183.08:17:58.63#ibcon#read 6, iclass 25, count 0 2006.183.08:17:58.63#ibcon#end of sib2, iclass 25, count 0 2006.183.08:17:58.63#ibcon#*after write, iclass 25, count 0 2006.183.08:17:58.63#ibcon#*before return 0, iclass 25, count 0 2006.183.08:17:58.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:17:58.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:17:58.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:17:58.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:17:58.63$vc4f8/valo=3,672.99 2006.183.08:17:58.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.08:17:58.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.08:17:58.63#ibcon#ireg 17 cls_cnt 0 2006.183.08:17:58.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:17:58.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:17:58.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:17:58.63#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:17:58.63#ibcon#first serial, iclass 27, count 0 2006.183.08:17:58.63#ibcon#enter sib2, iclass 27, count 0 2006.183.08:17:58.63#ibcon#flushed, iclass 27, count 0 2006.183.08:17:58.63#ibcon#about to write, iclass 27, count 0 2006.183.08:17:58.63#ibcon#wrote, iclass 27, count 0 2006.183.08:17:58.63#ibcon#about to read 3, iclass 27, count 0 2006.183.08:17:58.65#ibcon#read 3, iclass 27, count 0 2006.183.08:17:58.65#ibcon#about to read 4, iclass 27, count 0 2006.183.08:17:58.65#ibcon#read 4, iclass 27, count 0 2006.183.08:17:58.65#ibcon#about to read 5, iclass 27, count 0 2006.183.08:17:58.65#ibcon#read 5, iclass 27, count 0 2006.183.08:17:58.65#ibcon#about to read 6, iclass 27, count 0 2006.183.08:17:58.65#ibcon#read 6, iclass 27, count 0 2006.183.08:17:58.65#ibcon#end of sib2, iclass 27, count 0 2006.183.08:17:58.65#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:17:58.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:17:58.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:17:58.65#ibcon#*before write, iclass 27, count 0 2006.183.08:17:58.65#ibcon#enter sib2, iclass 27, count 0 2006.183.08:17:58.65#ibcon#flushed, iclass 27, count 0 2006.183.08:17:58.65#ibcon#about to write, iclass 27, count 0 2006.183.08:17:58.65#ibcon#wrote, iclass 27, count 0 2006.183.08:17:58.65#ibcon#about to read 3, iclass 27, count 0 2006.183.08:17:58.69#ibcon#read 3, iclass 27, count 0 2006.183.08:17:58.69#ibcon#about to read 4, iclass 27, count 0 2006.183.08:17:58.69#ibcon#read 4, iclass 27, count 0 2006.183.08:17:58.69#ibcon#about to read 5, iclass 27, count 0 2006.183.08:17:58.69#ibcon#read 5, iclass 27, count 0 2006.183.08:17:58.69#ibcon#about to read 6, iclass 27, count 0 2006.183.08:17:58.69#ibcon#read 6, iclass 27, count 0 2006.183.08:17:58.69#ibcon#end of sib2, iclass 27, count 0 2006.183.08:17:58.69#ibcon#*after write, iclass 27, count 0 2006.183.08:17:58.69#ibcon#*before return 0, iclass 27, count 0 2006.183.08:17:58.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:17:58.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:17:58.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:17:58.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:17:58.69$vc4f8/va=3,6 2006.183.08:17:58.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.08:17:58.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.08:17:58.69#ibcon#ireg 11 cls_cnt 2 2006.183.08:17:58.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:17:58.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:17:58.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:17:58.76#ibcon#enter wrdev, iclass 29, count 2 2006.183.08:17:58.76#ibcon#first serial, iclass 29, count 2 2006.183.08:17:58.76#ibcon#enter sib2, iclass 29, count 2 2006.183.08:17:58.76#ibcon#flushed, iclass 29, count 2 2006.183.08:17:58.76#ibcon#about to write, iclass 29, count 2 2006.183.08:17:58.76#ibcon#wrote, iclass 29, count 2 2006.183.08:17:58.76#ibcon#about to read 3, iclass 29, count 2 2006.183.08:17:58.78#ibcon#read 3, iclass 29, count 2 2006.183.08:17:58.78#ibcon#about to read 4, iclass 29, count 2 2006.183.08:17:58.78#ibcon#read 4, iclass 29, count 2 2006.183.08:17:58.78#ibcon#about to read 5, iclass 29, count 2 2006.183.08:17:58.78#ibcon#read 5, iclass 29, count 2 2006.183.08:17:58.78#ibcon#about to read 6, iclass 29, count 2 2006.183.08:17:58.78#ibcon#read 6, iclass 29, count 2 2006.183.08:17:58.78#ibcon#end of sib2, iclass 29, count 2 2006.183.08:17:58.78#ibcon#*mode == 0, iclass 29, count 2 2006.183.08:17:58.78#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.08:17:58.78#ibcon#[25=AT03-06\r\n] 2006.183.08:17:58.78#ibcon#*before write, iclass 29, count 2 2006.183.08:17:58.78#ibcon#enter sib2, iclass 29, count 2 2006.183.08:17:58.78#ibcon#flushed, iclass 29, count 2 2006.183.08:17:58.78#ibcon#about to write, iclass 29, count 2 2006.183.08:17:58.78#ibcon#wrote, iclass 29, count 2 2006.183.08:17:58.78#ibcon#about to read 3, iclass 29, count 2 2006.183.08:17:58.80#ibcon#read 3, iclass 29, count 2 2006.183.08:17:58.80#ibcon#about to read 4, iclass 29, count 2 2006.183.08:17:58.80#ibcon#read 4, iclass 29, count 2 2006.183.08:17:58.80#ibcon#about to read 5, iclass 29, count 2 2006.183.08:17:58.80#ibcon#read 5, iclass 29, count 2 2006.183.08:17:58.80#ibcon#about to read 6, iclass 29, count 2 2006.183.08:17:58.80#ibcon#read 6, iclass 29, count 2 2006.183.08:17:58.80#ibcon#end of sib2, iclass 29, count 2 2006.183.08:17:58.80#ibcon#*after write, iclass 29, count 2 2006.183.08:17:58.80#ibcon#*before return 0, iclass 29, count 2 2006.183.08:17:58.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:17:58.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:17:58.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.08:17:58.80#ibcon#ireg 7 cls_cnt 0 2006.183.08:17:58.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:17:58.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:17:58.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:17:58.92#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:17:58.92#ibcon#first serial, iclass 29, count 0 2006.183.08:17:58.92#ibcon#enter sib2, iclass 29, count 0 2006.183.08:17:58.92#ibcon#flushed, iclass 29, count 0 2006.183.08:17:58.92#ibcon#about to write, iclass 29, count 0 2006.183.08:17:58.92#ibcon#wrote, iclass 29, count 0 2006.183.08:17:58.92#ibcon#about to read 3, iclass 29, count 0 2006.183.08:17:58.94#ibcon#read 3, iclass 29, count 0 2006.183.08:17:58.94#ibcon#about to read 4, iclass 29, count 0 2006.183.08:17:58.94#ibcon#read 4, iclass 29, count 0 2006.183.08:17:58.94#ibcon#about to read 5, iclass 29, count 0 2006.183.08:17:58.94#ibcon#read 5, iclass 29, count 0 2006.183.08:17:58.94#ibcon#about to read 6, iclass 29, count 0 2006.183.08:17:58.94#ibcon#read 6, iclass 29, count 0 2006.183.08:17:58.94#ibcon#end of sib2, iclass 29, count 0 2006.183.08:17:58.94#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:17:58.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:17:58.94#ibcon#[25=USB\r\n] 2006.183.08:17:58.94#ibcon#*before write, iclass 29, count 0 2006.183.08:17:58.94#ibcon#enter sib2, iclass 29, count 0 2006.183.08:17:58.94#ibcon#flushed, iclass 29, count 0 2006.183.08:17:58.94#ibcon#about to write, iclass 29, count 0 2006.183.08:17:58.94#ibcon#wrote, iclass 29, count 0 2006.183.08:17:58.94#ibcon#about to read 3, iclass 29, count 0 2006.183.08:17:58.97#ibcon#read 3, iclass 29, count 0 2006.183.08:17:58.97#ibcon#about to read 4, iclass 29, count 0 2006.183.08:17:58.97#ibcon#read 4, iclass 29, count 0 2006.183.08:17:58.97#ibcon#about to read 5, iclass 29, count 0 2006.183.08:17:58.97#ibcon#read 5, iclass 29, count 0 2006.183.08:17:58.97#ibcon#about to read 6, iclass 29, count 0 2006.183.08:17:58.97#ibcon#read 6, iclass 29, count 0 2006.183.08:17:58.97#ibcon#end of sib2, iclass 29, count 0 2006.183.08:17:58.97#ibcon#*after write, iclass 29, count 0 2006.183.08:17:58.97#ibcon#*before return 0, iclass 29, count 0 2006.183.08:17:58.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:17:58.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:17:58.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:17:58.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:17:58.97$vc4f8/valo=4,832.99 2006.183.08:17:58.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.08:17:58.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.08:17:58.97#ibcon#ireg 17 cls_cnt 0 2006.183.08:17:58.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:17:58.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:17:58.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:17:58.97#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:17:58.97#ibcon#first serial, iclass 31, count 0 2006.183.08:17:58.97#ibcon#enter sib2, iclass 31, count 0 2006.183.08:17:58.97#ibcon#flushed, iclass 31, count 0 2006.183.08:17:58.97#ibcon#about to write, iclass 31, count 0 2006.183.08:17:58.97#ibcon#wrote, iclass 31, count 0 2006.183.08:17:58.97#ibcon#about to read 3, iclass 31, count 0 2006.183.08:17:58.99#ibcon#read 3, iclass 31, count 0 2006.183.08:17:58.99#ibcon#about to read 4, iclass 31, count 0 2006.183.08:17:58.99#ibcon#read 4, iclass 31, count 0 2006.183.08:17:58.99#ibcon#about to read 5, iclass 31, count 0 2006.183.08:17:58.99#ibcon#read 5, iclass 31, count 0 2006.183.08:17:58.99#ibcon#about to read 6, iclass 31, count 0 2006.183.08:17:58.99#ibcon#read 6, iclass 31, count 0 2006.183.08:17:58.99#ibcon#end of sib2, iclass 31, count 0 2006.183.08:17:58.99#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:17:58.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:17:58.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:17:58.99#ibcon#*before write, iclass 31, count 0 2006.183.08:17:58.99#ibcon#enter sib2, iclass 31, count 0 2006.183.08:17:58.99#ibcon#flushed, iclass 31, count 0 2006.183.08:17:58.99#ibcon#about to write, iclass 31, count 0 2006.183.08:17:58.99#ibcon#wrote, iclass 31, count 0 2006.183.08:17:58.99#ibcon#about to read 3, iclass 31, count 0 2006.183.08:17:59.03#ibcon#read 3, iclass 31, count 0 2006.183.08:17:59.03#ibcon#about to read 4, iclass 31, count 0 2006.183.08:17:59.03#ibcon#read 4, iclass 31, count 0 2006.183.08:17:59.03#ibcon#about to read 5, iclass 31, count 0 2006.183.08:17:59.03#ibcon#read 5, iclass 31, count 0 2006.183.08:17:59.03#ibcon#about to read 6, iclass 31, count 0 2006.183.08:17:59.03#ibcon#read 6, iclass 31, count 0 2006.183.08:17:59.03#ibcon#end of sib2, iclass 31, count 0 2006.183.08:17:59.03#ibcon#*after write, iclass 31, count 0 2006.183.08:17:59.03#ibcon#*before return 0, iclass 31, count 0 2006.183.08:17:59.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:17:59.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:17:59.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:17:59.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:17:59.03$vc4f8/va=4,7 2006.183.08:17:59.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.08:17:59.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.08:17:59.03#ibcon#ireg 11 cls_cnt 2 2006.183.08:17:59.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:17:59.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:17:59.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:17:59.09#ibcon#enter wrdev, iclass 33, count 2 2006.183.08:17:59.09#ibcon#first serial, iclass 33, count 2 2006.183.08:17:59.09#ibcon#enter sib2, iclass 33, count 2 2006.183.08:17:59.09#ibcon#flushed, iclass 33, count 2 2006.183.08:17:59.09#ibcon#about to write, iclass 33, count 2 2006.183.08:17:59.09#ibcon#wrote, iclass 33, count 2 2006.183.08:17:59.09#ibcon#about to read 3, iclass 33, count 2 2006.183.08:17:59.11#ibcon#read 3, iclass 33, count 2 2006.183.08:17:59.11#ibcon#about to read 4, iclass 33, count 2 2006.183.08:17:59.11#ibcon#read 4, iclass 33, count 2 2006.183.08:17:59.11#ibcon#about to read 5, iclass 33, count 2 2006.183.08:17:59.11#ibcon#read 5, iclass 33, count 2 2006.183.08:17:59.11#ibcon#about to read 6, iclass 33, count 2 2006.183.08:17:59.11#ibcon#read 6, iclass 33, count 2 2006.183.08:17:59.11#ibcon#end of sib2, iclass 33, count 2 2006.183.08:17:59.11#ibcon#*mode == 0, iclass 33, count 2 2006.183.08:17:59.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.08:17:59.11#ibcon#[25=AT04-07\r\n] 2006.183.08:17:59.11#ibcon#*before write, iclass 33, count 2 2006.183.08:17:59.11#ibcon#enter sib2, iclass 33, count 2 2006.183.08:17:59.11#ibcon#flushed, iclass 33, count 2 2006.183.08:17:59.11#ibcon#about to write, iclass 33, count 2 2006.183.08:17:59.11#ibcon#wrote, iclass 33, count 2 2006.183.08:17:59.11#ibcon#about to read 3, iclass 33, count 2 2006.183.08:17:59.14#ibcon#read 3, iclass 33, count 2 2006.183.08:17:59.14#ibcon#about to read 4, iclass 33, count 2 2006.183.08:17:59.14#ibcon#read 4, iclass 33, count 2 2006.183.08:17:59.14#ibcon#about to read 5, iclass 33, count 2 2006.183.08:17:59.14#ibcon#read 5, iclass 33, count 2 2006.183.08:17:59.14#ibcon#about to read 6, iclass 33, count 2 2006.183.08:17:59.14#ibcon#read 6, iclass 33, count 2 2006.183.08:17:59.14#ibcon#end of sib2, iclass 33, count 2 2006.183.08:17:59.14#ibcon#*after write, iclass 33, count 2 2006.183.08:17:59.14#ibcon#*before return 0, iclass 33, count 2 2006.183.08:17:59.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:17:59.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:17:59.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.08:17:59.14#ibcon#ireg 7 cls_cnt 0 2006.183.08:17:59.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:17:59.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:17:59.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:17:59.26#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:17:59.26#ibcon#first serial, iclass 33, count 0 2006.183.08:17:59.26#ibcon#enter sib2, iclass 33, count 0 2006.183.08:17:59.26#ibcon#flushed, iclass 33, count 0 2006.183.08:17:59.26#ibcon#about to write, iclass 33, count 0 2006.183.08:17:59.26#ibcon#wrote, iclass 33, count 0 2006.183.08:17:59.26#ibcon#about to read 3, iclass 33, count 0 2006.183.08:17:59.28#ibcon#read 3, iclass 33, count 0 2006.183.08:17:59.28#ibcon#about to read 4, iclass 33, count 0 2006.183.08:17:59.28#ibcon#read 4, iclass 33, count 0 2006.183.08:17:59.28#ibcon#about to read 5, iclass 33, count 0 2006.183.08:17:59.28#ibcon#read 5, iclass 33, count 0 2006.183.08:17:59.28#ibcon#about to read 6, iclass 33, count 0 2006.183.08:17:59.28#ibcon#read 6, iclass 33, count 0 2006.183.08:17:59.28#ibcon#end of sib2, iclass 33, count 0 2006.183.08:17:59.28#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:17:59.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:17:59.28#ibcon#[25=USB\r\n] 2006.183.08:17:59.28#ibcon#*before write, iclass 33, count 0 2006.183.08:17:59.28#ibcon#enter sib2, iclass 33, count 0 2006.183.08:17:59.28#ibcon#flushed, iclass 33, count 0 2006.183.08:17:59.28#ibcon#about to write, iclass 33, count 0 2006.183.08:17:59.28#ibcon#wrote, iclass 33, count 0 2006.183.08:17:59.28#ibcon#about to read 3, iclass 33, count 0 2006.183.08:17:59.31#ibcon#read 3, iclass 33, count 0 2006.183.08:17:59.31#ibcon#about to read 4, iclass 33, count 0 2006.183.08:17:59.31#ibcon#read 4, iclass 33, count 0 2006.183.08:17:59.31#ibcon#about to read 5, iclass 33, count 0 2006.183.08:17:59.31#ibcon#read 5, iclass 33, count 0 2006.183.08:17:59.31#ibcon#about to read 6, iclass 33, count 0 2006.183.08:17:59.31#ibcon#read 6, iclass 33, count 0 2006.183.08:17:59.31#ibcon#end of sib2, iclass 33, count 0 2006.183.08:17:59.31#ibcon#*after write, iclass 33, count 0 2006.183.08:17:59.31#ibcon#*before return 0, iclass 33, count 0 2006.183.08:17:59.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:17:59.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:17:59.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:17:59.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:17:59.31$vc4f8/valo=5,652.99 2006.183.08:17:59.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.08:17:59.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.08:17:59.31#ibcon#ireg 17 cls_cnt 0 2006.183.08:17:59.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:17:59.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:17:59.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:17:59.31#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:17:59.31#ibcon#first serial, iclass 35, count 0 2006.183.08:17:59.31#ibcon#enter sib2, iclass 35, count 0 2006.183.08:17:59.31#ibcon#flushed, iclass 35, count 0 2006.183.08:17:59.31#ibcon#about to write, iclass 35, count 0 2006.183.08:17:59.31#ibcon#wrote, iclass 35, count 0 2006.183.08:17:59.31#ibcon#about to read 3, iclass 35, count 0 2006.183.08:17:59.33#ibcon#read 3, iclass 35, count 0 2006.183.08:17:59.33#ibcon#about to read 4, iclass 35, count 0 2006.183.08:17:59.33#ibcon#read 4, iclass 35, count 0 2006.183.08:17:59.33#ibcon#about to read 5, iclass 35, count 0 2006.183.08:17:59.33#ibcon#read 5, iclass 35, count 0 2006.183.08:17:59.33#ibcon#about to read 6, iclass 35, count 0 2006.183.08:17:59.33#ibcon#read 6, iclass 35, count 0 2006.183.08:17:59.33#ibcon#end of sib2, iclass 35, count 0 2006.183.08:17:59.33#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:17:59.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:17:59.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:17:59.33#ibcon#*before write, iclass 35, count 0 2006.183.08:17:59.33#ibcon#enter sib2, iclass 35, count 0 2006.183.08:17:59.33#ibcon#flushed, iclass 35, count 0 2006.183.08:17:59.33#ibcon#about to write, iclass 35, count 0 2006.183.08:17:59.33#ibcon#wrote, iclass 35, count 0 2006.183.08:17:59.33#ibcon#about to read 3, iclass 35, count 0 2006.183.08:17:59.37#ibcon#read 3, iclass 35, count 0 2006.183.08:17:59.37#ibcon#about to read 4, iclass 35, count 0 2006.183.08:17:59.37#ibcon#read 4, iclass 35, count 0 2006.183.08:17:59.37#ibcon#about to read 5, iclass 35, count 0 2006.183.08:17:59.37#ibcon#read 5, iclass 35, count 0 2006.183.08:17:59.37#ibcon#about to read 6, iclass 35, count 0 2006.183.08:17:59.37#ibcon#read 6, iclass 35, count 0 2006.183.08:17:59.37#ibcon#end of sib2, iclass 35, count 0 2006.183.08:17:59.37#ibcon#*after write, iclass 35, count 0 2006.183.08:17:59.37#ibcon#*before return 0, iclass 35, count 0 2006.183.08:17:59.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:17:59.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:17:59.37#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:17:59.37#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:17:59.37$vc4f8/va=5,7 2006.183.08:17:59.37#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.08:17:59.37#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.08:17:59.37#ibcon#ireg 11 cls_cnt 2 2006.183.08:17:59.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:17:59.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:17:59.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:17:59.43#ibcon#enter wrdev, iclass 37, count 2 2006.183.08:17:59.43#ibcon#first serial, iclass 37, count 2 2006.183.08:17:59.43#ibcon#enter sib2, iclass 37, count 2 2006.183.08:17:59.43#ibcon#flushed, iclass 37, count 2 2006.183.08:17:59.43#ibcon#about to write, iclass 37, count 2 2006.183.08:17:59.43#ibcon#wrote, iclass 37, count 2 2006.183.08:17:59.43#ibcon#about to read 3, iclass 37, count 2 2006.183.08:17:59.45#ibcon#read 3, iclass 37, count 2 2006.183.08:17:59.45#ibcon#about to read 4, iclass 37, count 2 2006.183.08:17:59.45#ibcon#read 4, iclass 37, count 2 2006.183.08:17:59.45#ibcon#about to read 5, iclass 37, count 2 2006.183.08:17:59.45#ibcon#read 5, iclass 37, count 2 2006.183.08:17:59.45#ibcon#about to read 6, iclass 37, count 2 2006.183.08:17:59.45#ibcon#read 6, iclass 37, count 2 2006.183.08:17:59.45#ibcon#end of sib2, iclass 37, count 2 2006.183.08:17:59.45#ibcon#*mode == 0, iclass 37, count 2 2006.183.08:17:59.45#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.08:17:59.45#ibcon#[25=AT05-07\r\n] 2006.183.08:17:59.45#ibcon#*before write, iclass 37, count 2 2006.183.08:17:59.45#ibcon#enter sib2, iclass 37, count 2 2006.183.08:17:59.45#ibcon#flushed, iclass 37, count 2 2006.183.08:17:59.45#ibcon#about to write, iclass 37, count 2 2006.183.08:17:59.45#ibcon#wrote, iclass 37, count 2 2006.183.08:17:59.45#ibcon#about to read 3, iclass 37, count 2 2006.183.08:17:59.48#ibcon#read 3, iclass 37, count 2 2006.183.08:17:59.48#ibcon#about to read 4, iclass 37, count 2 2006.183.08:17:59.48#ibcon#read 4, iclass 37, count 2 2006.183.08:17:59.48#ibcon#about to read 5, iclass 37, count 2 2006.183.08:17:59.48#ibcon#read 5, iclass 37, count 2 2006.183.08:17:59.48#ibcon#about to read 6, iclass 37, count 2 2006.183.08:17:59.48#ibcon#read 6, iclass 37, count 2 2006.183.08:17:59.48#ibcon#end of sib2, iclass 37, count 2 2006.183.08:17:59.48#ibcon#*after write, iclass 37, count 2 2006.183.08:17:59.48#ibcon#*before return 0, iclass 37, count 2 2006.183.08:17:59.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:17:59.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:17:59.48#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.08:17:59.48#ibcon#ireg 7 cls_cnt 0 2006.183.08:17:59.48#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:17:59.60#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:17:59.60#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:17:59.60#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:17:59.60#ibcon#first serial, iclass 37, count 0 2006.183.08:17:59.60#ibcon#enter sib2, iclass 37, count 0 2006.183.08:17:59.60#ibcon#flushed, iclass 37, count 0 2006.183.08:17:59.60#ibcon#about to write, iclass 37, count 0 2006.183.08:17:59.60#ibcon#wrote, iclass 37, count 0 2006.183.08:17:59.60#ibcon#about to read 3, iclass 37, count 0 2006.183.08:17:59.62#ibcon#read 3, iclass 37, count 0 2006.183.08:17:59.62#ibcon#about to read 4, iclass 37, count 0 2006.183.08:17:59.62#ibcon#read 4, iclass 37, count 0 2006.183.08:17:59.62#ibcon#about to read 5, iclass 37, count 0 2006.183.08:17:59.62#ibcon#read 5, iclass 37, count 0 2006.183.08:17:59.62#ibcon#about to read 6, iclass 37, count 0 2006.183.08:17:59.62#ibcon#read 6, iclass 37, count 0 2006.183.08:17:59.62#ibcon#end of sib2, iclass 37, count 0 2006.183.08:17:59.62#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:17:59.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:17:59.62#ibcon#[25=USB\r\n] 2006.183.08:17:59.62#ibcon#*before write, iclass 37, count 0 2006.183.08:17:59.62#ibcon#enter sib2, iclass 37, count 0 2006.183.08:17:59.62#ibcon#flushed, iclass 37, count 0 2006.183.08:17:59.62#ibcon#about to write, iclass 37, count 0 2006.183.08:17:59.62#ibcon#wrote, iclass 37, count 0 2006.183.08:17:59.62#ibcon#about to read 3, iclass 37, count 0 2006.183.08:17:59.65#ibcon#read 3, iclass 37, count 0 2006.183.08:17:59.65#ibcon#about to read 4, iclass 37, count 0 2006.183.08:17:59.65#ibcon#read 4, iclass 37, count 0 2006.183.08:17:59.65#ibcon#about to read 5, iclass 37, count 0 2006.183.08:17:59.65#ibcon#read 5, iclass 37, count 0 2006.183.08:17:59.65#ibcon#about to read 6, iclass 37, count 0 2006.183.08:17:59.65#ibcon#read 6, iclass 37, count 0 2006.183.08:17:59.65#ibcon#end of sib2, iclass 37, count 0 2006.183.08:17:59.65#ibcon#*after write, iclass 37, count 0 2006.183.08:17:59.65#ibcon#*before return 0, iclass 37, count 0 2006.183.08:17:59.65#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:17:59.65#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:17:59.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:17:59.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:17:59.65$vc4f8/valo=6,772.99 2006.183.08:17:59.65#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.08:17:59.65#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.08:17:59.65#ibcon#ireg 17 cls_cnt 0 2006.183.08:17:59.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:17:59.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:17:59.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:17:59.65#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:17:59.65#ibcon#first serial, iclass 39, count 0 2006.183.08:17:59.65#ibcon#enter sib2, iclass 39, count 0 2006.183.08:17:59.65#ibcon#flushed, iclass 39, count 0 2006.183.08:17:59.65#ibcon#about to write, iclass 39, count 0 2006.183.08:17:59.65#ibcon#wrote, iclass 39, count 0 2006.183.08:17:59.65#ibcon#about to read 3, iclass 39, count 0 2006.183.08:17:59.67#ibcon#read 3, iclass 39, count 0 2006.183.08:17:59.67#ibcon#about to read 4, iclass 39, count 0 2006.183.08:17:59.67#ibcon#read 4, iclass 39, count 0 2006.183.08:17:59.67#ibcon#about to read 5, iclass 39, count 0 2006.183.08:17:59.67#ibcon#read 5, iclass 39, count 0 2006.183.08:17:59.67#ibcon#about to read 6, iclass 39, count 0 2006.183.08:17:59.67#ibcon#read 6, iclass 39, count 0 2006.183.08:17:59.67#ibcon#end of sib2, iclass 39, count 0 2006.183.08:17:59.67#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:17:59.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:17:59.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:17:59.67#ibcon#*before write, iclass 39, count 0 2006.183.08:17:59.67#ibcon#enter sib2, iclass 39, count 0 2006.183.08:17:59.67#ibcon#flushed, iclass 39, count 0 2006.183.08:17:59.67#ibcon#about to write, iclass 39, count 0 2006.183.08:17:59.67#ibcon#wrote, iclass 39, count 0 2006.183.08:17:59.67#ibcon#about to read 3, iclass 39, count 0 2006.183.08:17:59.71#ibcon#read 3, iclass 39, count 0 2006.183.08:17:59.71#ibcon#about to read 4, iclass 39, count 0 2006.183.08:17:59.71#ibcon#read 4, iclass 39, count 0 2006.183.08:17:59.71#ibcon#about to read 5, iclass 39, count 0 2006.183.08:17:59.71#ibcon#read 5, iclass 39, count 0 2006.183.08:17:59.71#ibcon#about to read 6, iclass 39, count 0 2006.183.08:17:59.71#ibcon#read 6, iclass 39, count 0 2006.183.08:17:59.71#ibcon#end of sib2, iclass 39, count 0 2006.183.08:17:59.71#ibcon#*after write, iclass 39, count 0 2006.183.08:17:59.71#ibcon#*before return 0, iclass 39, count 0 2006.183.08:17:59.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:17:59.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:17:59.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:17:59.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:17:59.71$vc4f8/va=6,6 2006.183.08:17:59.71#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.183.08:17:59.71#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.183.08:17:59.71#ibcon#ireg 11 cls_cnt 2 2006.183.08:17:59.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:17:59.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:17:59.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:17:59.78#ibcon#enter wrdev, iclass 3, count 2 2006.183.08:17:59.78#ibcon#first serial, iclass 3, count 2 2006.183.08:17:59.78#ibcon#enter sib2, iclass 3, count 2 2006.183.08:17:59.78#ibcon#flushed, iclass 3, count 2 2006.183.08:17:59.78#ibcon#about to write, iclass 3, count 2 2006.183.08:17:59.78#ibcon#wrote, iclass 3, count 2 2006.183.08:17:59.78#ibcon#about to read 3, iclass 3, count 2 2006.183.08:17:59.80#ibcon#read 3, iclass 3, count 2 2006.183.08:17:59.80#ibcon#about to read 4, iclass 3, count 2 2006.183.08:17:59.80#ibcon#read 4, iclass 3, count 2 2006.183.08:17:59.80#ibcon#about to read 5, iclass 3, count 2 2006.183.08:17:59.80#ibcon#read 5, iclass 3, count 2 2006.183.08:17:59.80#ibcon#about to read 6, iclass 3, count 2 2006.183.08:17:59.80#ibcon#read 6, iclass 3, count 2 2006.183.08:17:59.80#ibcon#end of sib2, iclass 3, count 2 2006.183.08:17:59.80#ibcon#*mode == 0, iclass 3, count 2 2006.183.08:17:59.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.183.08:17:59.80#ibcon#[25=AT06-06\r\n] 2006.183.08:17:59.80#ibcon#*before write, iclass 3, count 2 2006.183.08:17:59.80#ibcon#enter sib2, iclass 3, count 2 2006.183.08:17:59.80#ibcon#flushed, iclass 3, count 2 2006.183.08:17:59.80#ibcon#about to write, iclass 3, count 2 2006.183.08:17:59.80#ibcon#wrote, iclass 3, count 2 2006.183.08:17:59.80#ibcon#about to read 3, iclass 3, count 2 2006.183.08:17:59.82#ibcon#read 3, iclass 3, count 2 2006.183.08:17:59.82#ibcon#about to read 4, iclass 3, count 2 2006.183.08:17:59.82#ibcon#read 4, iclass 3, count 2 2006.183.08:17:59.82#ibcon#about to read 5, iclass 3, count 2 2006.183.08:17:59.82#ibcon#read 5, iclass 3, count 2 2006.183.08:17:59.82#ibcon#about to read 6, iclass 3, count 2 2006.183.08:17:59.82#ibcon#read 6, iclass 3, count 2 2006.183.08:17:59.82#ibcon#end of sib2, iclass 3, count 2 2006.183.08:17:59.82#ibcon#*after write, iclass 3, count 2 2006.183.08:17:59.82#ibcon#*before return 0, iclass 3, count 2 2006.183.08:17:59.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:17:59.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:17:59.82#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.183.08:17:59.82#ibcon#ireg 7 cls_cnt 0 2006.183.08:17:59.82#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:17:59.94#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:17:59.94#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:17:59.94#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:17:59.94#ibcon#first serial, iclass 3, count 0 2006.183.08:17:59.94#ibcon#enter sib2, iclass 3, count 0 2006.183.08:17:59.94#ibcon#flushed, iclass 3, count 0 2006.183.08:17:59.94#ibcon#about to write, iclass 3, count 0 2006.183.08:17:59.94#ibcon#wrote, iclass 3, count 0 2006.183.08:17:59.94#ibcon#about to read 3, iclass 3, count 0 2006.183.08:17:59.96#ibcon#read 3, iclass 3, count 0 2006.183.08:17:59.96#ibcon#about to read 4, iclass 3, count 0 2006.183.08:17:59.96#ibcon#read 4, iclass 3, count 0 2006.183.08:17:59.96#ibcon#about to read 5, iclass 3, count 0 2006.183.08:17:59.96#ibcon#read 5, iclass 3, count 0 2006.183.08:17:59.96#ibcon#about to read 6, iclass 3, count 0 2006.183.08:17:59.96#ibcon#read 6, iclass 3, count 0 2006.183.08:17:59.96#ibcon#end of sib2, iclass 3, count 0 2006.183.08:17:59.96#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:17:59.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:17:59.96#ibcon#[25=USB\r\n] 2006.183.08:17:59.96#ibcon#*before write, iclass 3, count 0 2006.183.08:17:59.96#ibcon#enter sib2, iclass 3, count 0 2006.183.08:17:59.96#ibcon#flushed, iclass 3, count 0 2006.183.08:17:59.96#ibcon#about to write, iclass 3, count 0 2006.183.08:17:59.96#ibcon#wrote, iclass 3, count 0 2006.183.08:17:59.96#ibcon#about to read 3, iclass 3, count 0 2006.183.08:17:59.99#ibcon#read 3, iclass 3, count 0 2006.183.08:17:59.99#ibcon#about to read 4, iclass 3, count 0 2006.183.08:17:59.99#ibcon#read 4, iclass 3, count 0 2006.183.08:17:59.99#ibcon#about to read 5, iclass 3, count 0 2006.183.08:17:59.99#ibcon#read 5, iclass 3, count 0 2006.183.08:17:59.99#ibcon#about to read 6, iclass 3, count 0 2006.183.08:17:59.99#ibcon#read 6, iclass 3, count 0 2006.183.08:17:59.99#ibcon#end of sib2, iclass 3, count 0 2006.183.08:17:59.99#ibcon#*after write, iclass 3, count 0 2006.183.08:17:59.99#ibcon#*before return 0, iclass 3, count 0 2006.183.08:17:59.99#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:17:59.99#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:17:59.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:17:59.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:17:59.99$vc4f8/valo=7,832.99 2006.183.08:17:59.99#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.08:17:59.99#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.08:17:59.99#ibcon#ireg 17 cls_cnt 0 2006.183.08:17:59.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:17:59.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:17:59.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:17:59.99#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:17:59.99#ibcon#first serial, iclass 5, count 0 2006.183.08:17:59.99#ibcon#enter sib2, iclass 5, count 0 2006.183.08:17:59.99#ibcon#flushed, iclass 5, count 0 2006.183.08:17:59.99#ibcon#about to write, iclass 5, count 0 2006.183.08:17:59.99#ibcon#wrote, iclass 5, count 0 2006.183.08:17:59.99#ibcon#about to read 3, iclass 5, count 0 2006.183.08:18:00.01#ibcon#read 3, iclass 5, count 0 2006.183.08:18:00.01#ibcon#about to read 4, iclass 5, count 0 2006.183.08:18:00.01#ibcon#read 4, iclass 5, count 0 2006.183.08:18:00.01#ibcon#about to read 5, iclass 5, count 0 2006.183.08:18:00.01#ibcon#read 5, iclass 5, count 0 2006.183.08:18:00.01#ibcon#about to read 6, iclass 5, count 0 2006.183.08:18:00.01#ibcon#read 6, iclass 5, count 0 2006.183.08:18:00.01#ibcon#end of sib2, iclass 5, count 0 2006.183.08:18:00.01#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:18:00.01#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:18:00.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:18:00.01#ibcon#*before write, iclass 5, count 0 2006.183.08:18:00.01#ibcon#enter sib2, iclass 5, count 0 2006.183.08:18:00.01#ibcon#flushed, iclass 5, count 0 2006.183.08:18:00.01#ibcon#about to write, iclass 5, count 0 2006.183.08:18:00.01#ibcon#wrote, iclass 5, count 0 2006.183.08:18:00.01#ibcon#about to read 3, iclass 5, count 0 2006.183.08:18:00.05#ibcon#read 3, iclass 5, count 0 2006.183.08:18:00.05#ibcon#about to read 4, iclass 5, count 0 2006.183.08:18:00.05#ibcon#read 4, iclass 5, count 0 2006.183.08:18:00.05#ibcon#about to read 5, iclass 5, count 0 2006.183.08:18:00.05#ibcon#read 5, iclass 5, count 0 2006.183.08:18:00.05#ibcon#about to read 6, iclass 5, count 0 2006.183.08:18:00.05#ibcon#read 6, iclass 5, count 0 2006.183.08:18:00.05#ibcon#end of sib2, iclass 5, count 0 2006.183.08:18:00.05#ibcon#*after write, iclass 5, count 0 2006.183.08:18:00.05#ibcon#*before return 0, iclass 5, count 0 2006.183.08:18:00.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:18:00.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:18:00.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:18:00.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:18:00.05$vc4f8/va=7,6 2006.183.08:18:00.05#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.08:18:00.05#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.08:18:00.05#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:00.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:18:00.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:18:00.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:18:00.11#ibcon#enter wrdev, iclass 7, count 2 2006.183.08:18:00.11#ibcon#first serial, iclass 7, count 2 2006.183.08:18:00.11#ibcon#enter sib2, iclass 7, count 2 2006.183.08:18:00.11#ibcon#flushed, iclass 7, count 2 2006.183.08:18:00.11#ibcon#about to write, iclass 7, count 2 2006.183.08:18:00.11#ibcon#wrote, iclass 7, count 2 2006.183.08:18:00.11#ibcon#about to read 3, iclass 7, count 2 2006.183.08:18:00.13#ibcon#read 3, iclass 7, count 2 2006.183.08:18:00.13#ibcon#about to read 4, iclass 7, count 2 2006.183.08:18:00.13#ibcon#read 4, iclass 7, count 2 2006.183.08:18:00.13#ibcon#about to read 5, iclass 7, count 2 2006.183.08:18:00.13#ibcon#read 5, iclass 7, count 2 2006.183.08:18:00.13#ibcon#about to read 6, iclass 7, count 2 2006.183.08:18:00.13#ibcon#read 6, iclass 7, count 2 2006.183.08:18:00.13#ibcon#end of sib2, iclass 7, count 2 2006.183.08:18:00.13#ibcon#*mode == 0, iclass 7, count 2 2006.183.08:18:00.13#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.08:18:00.13#ibcon#[25=AT07-06\r\n] 2006.183.08:18:00.13#ibcon#*before write, iclass 7, count 2 2006.183.08:18:00.13#ibcon#enter sib2, iclass 7, count 2 2006.183.08:18:00.13#ibcon#flushed, iclass 7, count 2 2006.183.08:18:00.13#ibcon#about to write, iclass 7, count 2 2006.183.08:18:00.13#ibcon#wrote, iclass 7, count 2 2006.183.08:18:00.13#ibcon#about to read 3, iclass 7, count 2 2006.183.08:18:00.16#ibcon#read 3, iclass 7, count 2 2006.183.08:18:00.16#ibcon#about to read 4, iclass 7, count 2 2006.183.08:18:00.16#ibcon#read 4, iclass 7, count 2 2006.183.08:18:00.16#ibcon#about to read 5, iclass 7, count 2 2006.183.08:18:00.16#ibcon#read 5, iclass 7, count 2 2006.183.08:18:00.16#ibcon#about to read 6, iclass 7, count 2 2006.183.08:18:00.16#ibcon#read 6, iclass 7, count 2 2006.183.08:18:00.16#ibcon#end of sib2, iclass 7, count 2 2006.183.08:18:00.16#ibcon#*after write, iclass 7, count 2 2006.183.08:18:00.16#ibcon#*before return 0, iclass 7, count 2 2006.183.08:18:00.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:18:00.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:18:00.16#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.08:18:00.16#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:00.16#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:18:00.28#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:18:00.28#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:18:00.28#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:18:00.28#ibcon#first serial, iclass 7, count 0 2006.183.08:18:00.28#ibcon#enter sib2, iclass 7, count 0 2006.183.08:18:00.28#ibcon#flushed, iclass 7, count 0 2006.183.08:18:00.28#ibcon#about to write, iclass 7, count 0 2006.183.08:18:00.28#ibcon#wrote, iclass 7, count 0 2006.183.08:18:00.28#ibcon#about to read 3, iclass 7, count 0 2006.183.08:18:00.30#ibcon#read 3, iclass 7, count 0 2006.183.08:18:00.30#ibcon#about to read 4, iclass 7, count 0 2006.183.08:18:00.30#ibcon#read 4, iclass 7, count 0 2006.183.08:18:00.30#ibcon#about to read 5, iclass 7, count 0 2006.183.08:18:00.30#ibcon#read 5, iclass 7, count 0 2006.183.08:18:00.30#ibcon#about to read 6, iclass 7, count 0 2006.183.08:18:00.30#ibcon#read 6, iclass 7, count 0 2006.183.08:18:00.30#ibcon#end of sib2, iclass 7, count 0 2006.183.08:18:00.30#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:18:00.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:18:00.30#ibcon#[25=USB\r\n] 2006.183.08:18:00.30#ibcon#*before write, iclass 7, count 0 2006.183.08:18:00.30#ibcon#enter sib2, iclass 7, count 0 2006.183.08:18:00.30#ibcon#flushed, iclass 7, count 0 2006.183.08:18:00.30#ibcon#about to write, iclass 7, count 0 2006.183.08:18:00.30#ibcon#wrote, iclass 7, count 0 2006.183.08:18:00.30#ibcon#about to read 3, iclass 7, count 0 2006.183.08:18:00.33#ibcon#read 3, iclass 7, count 0 2006.183.08:18:00.33#ibcon#about to read 4, iclass 7, count 0 2006.183.08:18:00.33#ibcon#read 4, iclass 7, count 0 2006.183.08:18:00.33#ibcon#about to read 5, iclass 7, count 0 2006.183.08:18:00.33#ibcon#read 5, iclass 7, count 0 2006.183.08:18:00.33#ibcon#about to read 6, iclass 7, count 0 2006.183.08:18:00.33#ibcon#read 6, iclass 7, count 0 2006.183.08:18:00.33#ibcon#end of sib2, iclass 7, count 0 2006.183.08:18:00.33#ibcon#*after write, iclass 7, count 0 2006.183.08:18:00.33#ibcon#*before return 0, iclass 7, count 0 2006.183.08:18:00.33#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:18:00.33#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:18:00.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:18:00.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:18:00.33$vc4f8/valo=8,852.99 2006.183.08:18:00.33#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:18:00.33#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:18:00.33#ibcon#ireg 17 cls_cnt 0 2006.183.08:18:00.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:18:00.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:18:00.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:18:00.33#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:18:00.33#ibcon#first serial, iclass 11, count 0 2006.183.08:18:00.33#ibcon#enter sib2, iclass 11, count 0 2006.183.08:18:00.33#ibcon#flushed, iclass 11, count 0 2006.183.08:18:00.33#ibcon#about to write, iclass 11, count 0 2006.183.08:18:00.33#ibcon#wrote, iclass 11, count 0 2006.183.08:18:00.33#ibcon#about to read 3, iclass 11, count 0 2006.183.08:18:00.35#ibcon#read 3, iclass 11, count 0 2006.183.08:18:00.35#ibcon#about to read 4, iclass 11, count 0 2006.183.08:18:00.35#ibcon#read 4, iclass 11, count 0 2006.183.08:18:00.35#ibcon#about to read 5, iclass 11, count 0 2006.183.08:18:00.35#ibcon#read 5, iclass 11, count 0 2006.183.08:18:00.35#ibcon#about to read 6, iclass 11, count 0 2006.183.08:18:00.35#ibcon#read 6, iclass 11, count 0 2006.183.08:18:00.35#ibcon#end of sib2, iclass 11, count 0 2006.183.08:18:00.35#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:18:00.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:18:00.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:18:00.35#ibcon#*before write, iclass 11, count 0 2006.183.08:18:00.35#ibcon#enter sib2, iclass 11, count 0 2006.183.08:18:00.35#ibcon#flushed, iclass 11, count 0 2006.183.08:18:00.35#ibcon#about to write, iclass 11, count 0 2006.183.08:18:00.35#ibcon#wrote, iclass 11, count 0 2006.183.08:18:00.35#ibcon#about to read 3, iclass 11, count 0 2006.183.08:18:00.39#ibcon#read 3, iclass 11, count 0 2006.183.08:18:00.39#ibcon#about to read 4, iclass 11, count 0 2006.183.08:18:00.39#ibcon#read 4, iclass 11, count 0 2006.183.08:18:00.39#ibcon#about to read 5, iclass 11, count 0 2006.183.08:18:00.39#ibcon#read 5, iclass 11, count 0 2006.183.08:18:00.39#ibcon#about to read 6, iclass 11, count 0 2006.183.08:18:00.39#ibcon#read 6, iclass 11, count 0 2006.183.08:18:00.39#ibcon#end of sib2, iclass 11, count 0 2006.183.08:18:00.39#ibcon#*after write, iclass 11, count 0 2006.183.08:18:00.39#ibcon#*before return 0, iclass 11, count 0 2006.183.08:18:00.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:18:00.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:18:00.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:18:00.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:18:00.39$vc4f8/va=8,7 2006.183.08:18:00.39#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.08:18:00.39#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.08:18:00.39#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:00.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:18:00.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:18:00.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:18:00.45#ibcon#enter wrdev, iclass 13, count 2 2006.183.08:18:00.45#ibcon#first serial, iclass 13, count 2 2006.183.08:18:00.45#ibcon#enter sib2, iclass 13, count 2 2006.183.08:18:00.45#ibcon#flushed, iclass 13, count 2 2006.183.08:18:00.45#ibcon#about to write, iclass 13, count 2 2006.183.08:18:00.45#ibcon#wrote, iclass 13, count 2 2006.183.08:18:00.45#ibcon#about to read 3, iclass 13, count 2 2006.183.08:18:00.47#ibcon#read 3, iclass 13, count 2 2006.183.08:18:00.47#ibcon#about to read 4, iclass 13, count 2 2006.183.08:18:00.47#ibcon#read 4, iclass 13, count 2 2006.183.08:18:00.47#ibcon#about to read 5, iclass 13, count 2 2006.183.08:18:00.47#ibcon#read 5, iclass 13, count 2 2006.183.08:18:00.47#ibcon#about to read 6, iclass 13, count 2 2006.183.08:18:00.47#ibcon#read 6, iclass 13, count 2 2006.183.08:18:00.47#ibcon#end of sib2, iclass 13, count 2 2006.183.08:18:00.47#ibcon#*mode == 0, iclass 13, count 2 2006.183.08:18:00.47#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.08:18:00.47#ibcon#[25=AT08-07\r\n] 2006.183.08:18:00.47#ibcon#*before write, iclass 13, count 2 2006.183.08:18:00.47#ibcon#enter sib2, iclass 13, count 2 2006.183.08:18:00.47#ibcon#flushed, iclass 13, count 2 2006.183.08:18:00.47#ibcon#about to write, iclass 13, count 2 2006.183.08:18:00.47#ibcon#wrote, iclass 13, count 2 2006.183.08:18:00.47#ibcon#about to read 3, iclass 13, count 2 2006.183.08:18:00.50#ibcon#read 3, iclass 13, count 2 2006.183.08:18:00.50#ibcon#about to read 4, iclass 13, count 2 2006.183.08:18:00.50#ibcon#read 4, iclass 13, count 2 2006.183.08:18:00.50#ibcon#about to read 5, iclass 13, count 2 2006.183.08:18:00.50#ibcon#read 5, iclass 13, count 2 2006.183.08:18:00.50#ibcon#about to read 6, iclass 13, count 2 2006.183.08:18:00.50#ibcon#read 6, iclass 13, count 2 2006.183.08:18:00.50#ibcon#end of sib2, iclass 13, count 2 2006.183.08:18:00.50#ibcon#*after write, iclass 13, count 2 2006.183.08:18:00.50#ibcon#*before return 0, iclass 13, count 2 2006.183.08:18:00.50#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:18:00.50#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:18:00.50#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.08:18:00.50#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:00.50#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:18:00.62#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:18:00.62#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:18:00.62#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:18:00.62#ibcon#first serial, iclass 13, count 0 2006.183.08:18:00.62#ibcon#enter sib2, iclass 13, count 0 2006.183.08:18:00.62#ibcon#flushed, iclass 13, count 0 2006.183.08:18:00.62#ibcon#about to write, iclass 13, count 0 2006.183.08:18:00.62#ibcon#wrote, iclass 13, count 0 2006.183.08:18:00.62#ibcon#about to read 3, iclass 13, count 0 2006.183.08:18:00.64#ibcon#read 3, iclass 13, count 0 2006.183.08:18:00.64#ibcon#about to read 4, iclass 13, count 0 2006.183.08:18:00.64#ibcon#read 4, iclass 13, count 0 2006.183.08:18:00.64#ibcon#about to read 5, iclass 13, count 0 2006.183.08:18:00.64#ibcon#read 5, iclass 13, count 0 2006.183.08:18:00.64#ibcon#about to read 6, iclass 13, count 0 2006.183.08:18:00.64#ibcon#read 6, iclass 13, count 0 2006.183.08:18:00.64#ibcon#end of sib2, iclass 13, count 0 2006.183.08:18:00.64#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:18:00.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:18:00.64#ibcon#[25=USB\r\n] 2006.183.08:18:00.64#ibcon#*before write, iclass 13, count 0 2006.183.08:18:00.64#ibcon#enter sib2, iclass 13, count 0 2006.183.08:18:00.64#ibcon#flushed, iclass 13, count 0 2006.183.08:18:00.64#ibcon#about to write, iclass 13, count 0 2006.183.08:18:00.64#ibcon#wrote, iclass 13, count 0 2006.183.08:18:00.64#ibcon#about to read 3, iclass 13, count 0 2006.183.08:18:00.67#ibcon#read 3, iclass 13, count 0 2006.183.08:18:00.67#ibcon#about to read 4, iclass 13, count 0 2006.183.08:18:00.67#ibcon#read 4, iclass 13, count 0 2006.183.08:18:00.67#ibcon#about to read 5, iclass 13, count 0 2006.183.08:18:00.67#ibcon#read 5, iclass 13, count 0 2006.183.08:18:00.67#ibcon#about to read 6, iclass 13, count 0 2006.183.08:18:00.67#ibcon#read 6, iclass 13, count 0 2006.183.08:18:00.67#ibcon#end of sib2, iclass 13, count 0 2006.183.08:18:00.67#ibcon#*after write, iclass 13, count 0 2006.183.08:18:00.67#ibcon#*before return 0, iclass 13, count 0 2006.183.08:18:00.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:18:00.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:18:00.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:18:00.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:18:00.67$vc4f8/vblo=1,632.99 2006.183.08:18:00.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.08:18:00.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.08:18:00.67#ibcon#ireg 17 cls_cnt 0 2006.183.08:18:00.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:18:00.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:18:00.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:18:00.67#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:18:00.67#ibcon#first serial, iclass 15, count 0 2006.183.08:18:00.67#ibcon#enter sib2, iclass 15, count 0 2006.183.08:18:00.67#ibcon#flushed, iclass 15, count 0 2006.183.08:18:00.67#ibcon#about to write, iclass 15, count 0 2006.183.08:18:00.67#ibcon#wrote, iclass 15, count 0 2006.183.08:18:00.67#ibcon#about to read 3, iclass 15, count 0 2006.183.08:18:00.69#ibcon#read 3, iclass 15, count 0 2006.183.08:18:00.69#ibcon#about to read 4, iclass 15, count 0 2006.183.08:18:00.69#ibcon#read 4, iclass 15, count 0 2006.183.08:18:00.69#ibcon#about to read 5, iclass 15, count 0 2006.183.08:18:00.69#ibcon#read 5, iclass 15, count 0 2006.183.08:18:00.69#ibcon#about to read 6, iclass 15, count 0 2006.183.08:18:00.69#ibcon#read 6, iclass 15, count 0 2006.183.08:18:00.69#ibcon#end of sib2, iclass 15, count 0 2006.183.08:18:00.69#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:18:00.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:18:00.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:18:00.69#ibcon#*before write, iclass 15, count 0 2006.183.08:18:00.69#ibcon#enter sib2, iclass 15, count 0 2006.183.08:18:00.69#ibcon#flushed, iclass 15, count 0 2006.183.08:18:00.69#ibcon#about to write, iclass 15, count 0 2006.183.08:18:00.69#ibcon#wrote, iclass 15, count 0 2006.183.08:18:00.69#ibcon#about to read 3, iclass 15, count 0 2006.183.08:18:00.73#ibcon#read 3, iclass 15, count 0 2006.183.08:18:00.73#ibcon#about to read 4, iclass 15, count 0 2006.183.08:18:00.73#ibcon#read 4, iclass 15, count 0 2006.183.08:18:00.73#ibcon#about to read 5, iclass 15, count 0 2006.183.08:18:00.73#ibcon#read 5, iclass 15, count 0 2006.183.08:18:00.73#ibcon#about to read 6, iclass 15, count 0 2006.183.08:18:00.73#ibcon#read 6, iclass 15, count 0 2006.183.08:18:00.73#ibcon#end of sib2, iclass 15, count 0 2006.183.08:18:00.73#ibcon#*after write, iclass 15, count 0 2006.183.08:18:00.73#ibcon#*before return 0, iclass 15, count 0 2006.183.08:18:00.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:18:00.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:18:00.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:18:00.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:18:00.73$vc4f8/vb=1,4 2006.183.08:18:00.73#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.08:18:00.73#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.08:18:00.73#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:00.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:18:00.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:18:00.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:18:00.73#ibcon#enter wrdev, iclass 17, count 2 2006.183.08:18:00.73#ibcon#first serial, iclass 17, count 2 2006.183.08:18:00.73#ibcon#enter sib2, iclass 17, count 2 2006.183.08:18:00.73#ibcon#flushed, iclass 17, count 2 2006.183.08:18:00.73#ibcon#about to write, iclass 17, count 2 2006.183.08:18:00.73#ibcon#wrote, iclass 17, count 2 2006.183.08:18:00.73#ibcon#about to read 3, iclass 17, count 2 2006.183.08:18:00.75#ibcon#read 3, iclass 17, count 2 2006.183.08:18:00.75#ibcon#about to read 4, iclass 17, count 2 2006.183.08:18:00.75#ibcon#read 4, iclass 17, count 2 2006.183.08:18:00.75#ibcon#about to read 5, iclass 17, count 2 2006.183.08:18:00.75#ibcon#read 5, iclass 17, count 2 2006.183.08:18:00.75#ibcon#about to read 6, iclass 17, count 2 2006.183.08:18:00.75#ibcon#read 6, iclass 17, count 2 2006.183.08:18:00.75#ibcon#end of sib2, iclass 17, count 2 2006.183.08:18:00.75#ibcon#*mode == 0, iclass 17, count 2 2006.183.08:18:00.75#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.08:18:00.75#ibcon#[27=AT01-04\r\n] 2006.183.08:18:00.75#ibcon#*before write, iclass 17, count 2 2006.183.08:18:00.75#ibcon#enter sib2, iclass 17, count 2 2006.183.08:18:00.75#ibcon#flushed, iclass 17, count 2 2006.183.08:18:00.75#ibcon#about to write, iclass 17, count 2 2006.183.08:18:00.75#ibcon#wrote, iclass 17, count 2 2006.183.08:18:00.75#ibcon#about to read 3, iclass 17, count 2 2006.183.08:18:00.78#ibcon#read 3, iclass 17, count 2 2006.183.08:18:00.78#ibcon#about to read 4, iclass 17, count 2 2006.183.08:18:00.78#ibcon#read 4, iclass 17, count 2 2006.183.08:18:00.78#ibcon#about to read 5, iclass 17, count 2 2006.183.08:18:00.78#ibcon#read 5, iclass 17, count 2 2006.183.08:18:00.78#ibcon#about to read 6, iclass 17, count 2 2006.183.08:18:00.78#ibcon#read 6, iclass 17, count 2 2006.183.08:18:00.78#ibcon#end of sib2, iclass 17, count 2 2006.183.08:18:00.78#ibcon#*after write, iclass 17, count 2 2006.183.08:18:00.78#ibcon#*before return 0, iclass 17, count 2 2006.183.08:18:00.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:18:00.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:18:00.78#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.08:18:00.78#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:00.78#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:18:00.90#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:18:00.90#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:18:00.90#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:18:00.90#ibcon#first serial, iclass 17, count 0 2006.183.08:18:00.90#ibcon#enter sib2, iclass 17, count 0 2006.183.08:18:00.90#ibcon#flushed, iclass 17, count 0 2006.183.08:18:00.90#ibcon#about to write, iclass 17, count 0 2006.183.08:18:00.90#ibcon#wrote, iclass 17, count 0 2006.183.08:18:00.90#ibcon#about to read 3, iclass 17, count 0 2006.183.08:18:00.92#ibcon#read 3, iclass 17, count 0 2006.183.08:18:00.92#ibcon#about to read 4, iclass 17, count 0 2006.183.08:18:00.92#ibcon#read 4, iclass 17, count 0 2006.183.08:18:00.92#ibcon#about to read 5, iclass 17, count 0 2006.183.08:18:00.92#ibcon#read 5, iclass 17, count 0 2006.183.08:18:00.92#ibcon#about to read 6, iclass 17, count 0 2006.183.08:18:00.92#ibcon#read 6, iclass 17, count 0 2006.183.08:18:00.92#ibcon#end of sib2, iclass 17, count 0 2006.183.08:18:00.92#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:18:00.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:18:00.92#ibcon#[27=USB\r\n] 2006.183.08:18:00.92#ibcon#*before write, iclass 17, count 0 2006.183.08:18:00.92#ibcon#enter sib2, iclass 17, count 0 2006.183.08:18:00.92#ibcon#flushed, iclass 17, count 0 2006.183.08:18:00.92#ibcon#about to write, iclass 17, count 0 2006.183.08:18:00.92#ibcon#wrote, iclass 17, count 0 2006.183.08:18:00.92#ibcon#about to read 3, iclass 17, count 0 2006.183.08:18:00.95#ibcon#read 3, iclass 17, count 0 2006.183.08:18:00.95#ibcon#about to read 4, iclass 17, count 0 2006.183.08:18:00.95#ibcon#read 4, iclass 17, count 0 2006.183.08:18:00.95#ibcon#about to read 5, iclass 17, count 0 2006.183.08:18:00.95#ibcon#read 5, iclass 17, count 0 2006.183.08:18:00.95#ibcon#about to read 6, iclass 17, count 0 2006.183.08:18:00.95#ibcon#read 6, iclass 17, count 0 2006.183.08:18:00.95#ibcon#end of sib2, iclass 17, count 0 2006.183.08:18:00.95#ibcon#*after write, iclass 17, count 0 2006.183.08:18:00.95#ibcon#*before return 0, iclass 17, count 0 2006.183.08:18:00.95#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:18:00.95#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:18:00.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:18:00.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:18:00.95$vc4f8/vblo=2,640.99 2006.183.08:18:00.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.08:18:00.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.08:18:00.95#ibcon#ireg 17 cls_cnt 0 2006.183.08:18:00.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:18:00.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:18:00.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:18:00.95#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:18:00.95#ibcon#first serial, iclass 19, count 0 2006.183.08:18:00.95#ibcon#enter sib2, iclass 19, count 0 2006.183.08:18:00.95#ibcon#flushed, iclass 19, count 0 2006.183.08:18:00.95#ibcon#about to write, iclass 19, count 0 2006.183.08:18:00.95#ibcon#wrote, iclass 19, count 0 2006.183.08:18:00.95#ibcon#about to read 3, iclass 19, count 0 2006.183.08:18:00.97#ibcon#read 3, iclass 19, count 0 2006.183.08:18:00.97#ibcon#about to read 4, iclass 19, count 0 2006.183.08:18:00.97#ibcon#read 4, iclass 19, count 0 2006.183.08:18:00.97#ibcon#about to read 5, iclass 19, count 0 2006.183.08:18:00.97#ibcon#read 5, iclass 19, count 0 2006.183.08:18:00.97#ibcon#about to read 6, iclass 19, count 0 2006.183.08:18:00.97#ibcon#read 6, iclass 19, count 0 2006.183.08:18:00.97#ibcon#end of sib2, iclass 19, count 0 2006.183.08:18:00.97#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:18:00.97#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:18:00.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:18:00.97#ibcon#*before write, iclass 19, count 0 2006.183.08:18:00.97#ibcon#enter sib2, iclass 19, count 0 2006.183.08:18:00.97#ibcon#flushed, iclass 19, count 0 2006.183.08:18:00.97#ibcon#about to write, iclass 19, count 0 2006.183.08:18:00.97#ibcon#wrote, iclass 19, count 0 2006.183.08:18:00.97#ibcon#about to read 3, iclass 19, count 0 2006.183.08:18:01.01#ibcon#read 3, iclass 19, count 0 2006.183.08:18:01.01#ibcon#about to read 4, iclass 19, count 0 2006.183.08:18:01.01#ibcon#read 4, iclass 19, count 0 2006.183.08:18:01.01#ibcon#about to read 5, iclass 19, count 0 2006.183.08:18:01.01#ibcon#read 5, iclass 19, count 0 2006.183.08:18:01.01#ibcon#about to read 6, iclass 19, count 0 2006.183.08:18:01.01#ibcon#read 6, iclass 19, count 0 2006.183.08:18:01.01#ibcon#end of sib2, iclass 19, count 0 2006.183.08:18:01.01#ibcon#*after write, iclass 19, count 0 2006.183.08:18:01.01#ibcon#*before return 0, iclass 19, count 0 2006.183.08:18:01.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:18:01.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:18:01.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:18:01.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:18:01.01$vc4f8/vb=2,4 2006.183.08:18:01.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.08:18:01.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.08:18:01.01#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:01.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:18:01.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:18:01.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:18:01.07#ibcon#enter wrdev, iclass 21, count 2 2006.183.08:18:01.07#ibcon#first serial, iclass 21, count 2 2006.183.08:18:01.07#ibcon#enter sib2, iclass 21, count 2 2006.183.08:18:01.07#ibcon#flushed, iclass 21, count 2 2006.183.08:18:01.07#ibcon#about to write, iclass 21, count 2 2006.183.08:18:01.07#ibcon#wrote, iclass 21, count 2 2006.183.08:18:01.07#ibcon#about to read 3, iclass 21, count 2 2006.183.08:18:01.09#ibcon#read 3, iclass 21, count 2 2006.183.08:18:01.09#ibcon#about to read 4, iclass 21, count 2 2006.183.08:18:01.09#ibcon#read 4, iclass 21, count 2 2006.183.08:18:01.09#ibcon#about to read 5, iclass 21, count 2 2006.183.08:18:01.09#ibcon#read 5, iclass 21, count 2 2006.183.08:18:01.09#ibcon#about to read 6, iclass 21, count 2 2006.183.08:18:01.09#ibcon#read 6, iclass 21, count 2 2006.183.08:18:01.09#ibcon#end of sib2, iclass 21, count 2 2006.183.08:18:01.09#ibcon#*mode == 0, iclass 21, count 2 2006.183.08:18:01.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.08:18:01.09#ibcon#[27=AT02-04\r\n] 2006.183.08:18:01.09#ibcon#*before write, iclass 21, count 2 2006.183.08:18:01.09#ibcon#enter sib2, iclass 21, count 2 2006.183.08:18:01.09#ibcon#flushed, iclass 21, count 2 2006.183.08:18:01.09#ibcon#about to write, iclass 21, count 2 2006.183.08:18:01.09#ibcon#wrote, iclass 21, count 2 2006.183.08:18:01.09#ibcon#about to read 3, iclass 21, count 2 2006.183.08:18:01.12#ibcon#read 3, iclass 21, count 2 2006.183.08:18:01.12#ibcon#about to read 4, iclass 21, count 2 2006.183.08:18:01.12#ibcon#read 4, iclass 21, count 2 2006.183.08:18:01.12#ibcon#about to read 5, iclass 21, count 2 2006.183.08:18:01.12#ibcon#read 5, iclass 21, count 2 2006.183.08:18:01.12#ibcon#about to read 6, iclass 21, count 2 2006.183.08:18:01.12#ibcon#read 6, iclass 21, count 2 2006.183.08:18:01.12#ibcon#end of sib2, iclass 21, count 2 2006.183.08:18:01.12#ibcon#*after write, iclass 21, count 2 2006.183.08:18:01.12#ibcon#*before return 0, iclass 21, count 2 2006.183.08:18:01.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:18:01.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:18:01.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.08:18:01.12#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:01.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:18:01.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:18:01.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:18:01.24#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:18:01.24#ibcon#first serial, iclass 21, count 0 2006.183.08:18:01.24#ibcon#enter sib2, iclass 21, count 0 2006.183.08:18:01.24#ibcon#flushed, iclass 21, count 0 2006.183.08:18:01.24#ibcon#about to write, iclass 21, count 0 2006.183.08:18:01.24#ibcon#wrote, iclass 21, count 0 2006.183.08:18:01.24#ibcon#about to read 3, iclass 21, count 0 2006.183.08:18:01.26#ibcon#read 3, iclass 21, count 0 2006.183.08:18:01.26#ibcon#about to read 4, iclass 21, count 0 2006.183.08:18:01.26#ibcon#read 4, iclass 21, count 0 2006.183.08:18:01.26#ibcon#about to read 5, iclass 21, count 0 2006.183.08:18:01.26#ibcon#read 5, iclass 21, count 0 2006.183.08:18:01.26#ibcon#about to read 6, iclass 21, count 0 2006.183.08:18:01.26#ibcon#read 6, iclass 21, count 0 2006.183.08:18:01.26#ibcon#end of sib2, iclass 21, count 0 2006.183.08:18:01.26#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:18:01.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:18:01.26#ibcon#[27=USB\r\n] 2006.183.08:18:01.26#ibcon#*before write, iclass 21, count 0 2006.183.08:18:01.26#ibcon#enter sib2, iclass 21, count 0 2006.183.08:18:01.26#ibcon#flushed, iclass 21, count 0 2006.183.08:18:01.26#ibcon#about to write, iclass 21, count 0 2006.183.08:18:01.26#ibcon#wrote, iclass 21, count 0 2006.183.08:18:01.26#ibcon#about to read 3, iclass 21, count 0 2006.183.08:18:01.29#ibcon#read 3, iclass 21, count 0 2006.183.08:18:01.29#ibcon#about to read 4, iclass 21, count 0 2006.183.08:18:01.29#ibcon#read 4, iclass 21, count 0 2006.183.08:18:01.29#ibcon#about to read 5, iclass 21, count 0 2006.183.08:18:01.29#ibcon#read 5, iclass 21, count 0 2006.183.08:18:01.29#ibcon#about to read 6, iclass 21, count 0 2006.183.08:18:01.29#ibcon#read 6, iclass 21, count 0 2006.183.08:18:01.29#ibcon#end of sib2, iclass 21, count 0 2006.183.08:18:01.29#ibcon#*after write, iclass 21, count 0 2006.183.08:18:01.29#ibcon#*before return 0, iclass 21, count 0 2006.183.08:18:01.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:18:01.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:18:01.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:18:01.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:18:01.29$vc4f8/vblo=3,656.99 2006.183.08:18:01.29#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:18:01.29#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:18:01.29#ibcon#ireg 17 cls_cnt 0 2006.183.08:18:01.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:18:01.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:18:01.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:18:01.29#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:18:01.29#ibcon#first serial, iclass 23, count 0 2006.183.08:18:01.29#ibcon#enter sib2, iclass 23, count 0 2006.183.08:18:01.29#ibcon#flushed, iclass 23, count 0 2006.183.08:18:01.29#ibcon#about to write, iclass 23, count 0 2006.183.08:18:01.29#ibcon#wrote, iclass 23, count 0 2006.183.08:18:01.29#ibcon#about to read 3, iclass 23, count 0 2006.183.08:18:01.31#ibcon#read 3, iclass 23, count 0 2006.183.08:18:01.31#ibcon#about to read 4, iclass 23, count 0 2006.183.08:18:01.31#ibcon#read 4, iclass 23, count 0 2006.183.08:18:01.31#ibcon#about to read 5, iclass 23, count 0 2006.183.08:18:01.31#ibcon#read 5, iclass 23, count 0 2006.183.08:18:01.31#ibcon#about to read 6, iclass 23, count 0 2006.183.08:18:01.31#ibcon#read 6, iclass 23, count 0 2006.183.08:18:01.31#ibcon#end of sib2, iclass 23, count 0 2006.183.08:18:01.31#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:18:01.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:18:01.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:18:01.31#ibcon#*before write, iclass 23, count 0 2006.183.08:18:01.31#ibcon#enter sib2, iclass 23, count 0 2006.183.08:18:01.31#ibcon#flushed, iclass 23, count 0 2006.183.08:18:01.31#ibcon#about to write, iclass 23, count 0 2006.183.08:18:01.31#ibcon#wrote, iclass 23, count 0 2006.183.08:18:01.31#ibcon#about to read 3, iclass 23, count 0 2006.183.08:18:01.35#ibcon#read 3, iclass 23, count 0 2006.183.08:18:01.35#ibcon#about to read 4, iclass 23, count 0 2006.183.08:18:01.35#ibcon#read 4, iclass 23, count 0 2006.183.08:18:01.35#ibcon#about to read 5, iclass 23, count 0 2006.183.08:18:01.35#ibcon#read 5, iclass 23, count 0 2006.183.08:18:01.35#ibcon#about to read 6, iclass 23, count 0 2006.183.08:18:01.35#ibcon#read 6, iclass 23, count 0 2006.183.08:18:01.35#ibcon#end of sib2, iclass 23, count 0 2006.183.08:18:01.35#ibcon#*after write, iclass 23, count 0 2006.183.08:18:01.35#ibcon#*before return 0, iclass 23, count 0 2006.183.08:18:01.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:18:01.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:18:01.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:18:01.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:18:01.35$vc4f8/vb=3,4 2006.183.08:18:01.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.08:18:01.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.08:18:01.35#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:01.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:18:01.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:18:01.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:18:01.42#ibcon#enter wrdev, iclass 25, count 2 2006.183.08:18:01.42#ibcon#first serial, iclass 25, count 2 2006.183.08:18:01.42#ibcon#enter sib2, iclass 25, count 2 2006.183.08:18:01.42#ibcon#flushed, iclass 25, count 2 2006.183.08:18:01.42#ibcon#about to write, iclass 25, count 2 2006.183.08:18:01.42#ibcon#wrote, iclass 25, count 2 2006.183.08:18:01.42#ibcon#about to read 3, iclass 25, count 2 2006.183.08:18:01.44#ibcon#read 3, iclass 25, count 2 2006.183.08:18:01.44#ibcon#about to read 4, iclass 25, count 2 2006.183.08:18:01.44#ibcon#read 4, iclass 25, count 2 2006.183.08:18:01.44#ibcon#about to read 5, iclass 25, count 2 2006.183.08:18:01.44#ibcon#read 5, iclass 25, count 2 2006.183.08:18:01.44#ibcon#about to read 6, iclass 25, count 2 2006.183.08:18:01.44#ibcon#read 6, iclass 25, count 2 2006.183.08:18:01.44#ibcon#end of sib2, iclass 25, count 2 2006.183.08:18:01.44#ibcon#*mode == 0, iclass 25, count 2 2006.183.08:18:01.44#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.08:18:01.44#ibcon#[27=AT03-04\r\n] 2006.183.08:18:01.44#ibcon#*before write, iclass 25, count 2 2006.183.08:18:01.44#ibcon#enter sib2, iclass 25, count 2 2006.183.08:18:01.44#ibcon#flushed, iclass 25, count 2 2006.183.08:18:01.44#ibcon#about to write, iclass 25, count 2 2006.183.08:18:01.44#ibcon#wrote, iclass 25, count 2 2006.183.08:18:01.44#ibcon#about to read 3, iclass 25, count 2 2006.183.08:18:01.46#ibcon#read 3, iclass 25, count 2 2006.183.08:18:01.46#ibcon#about to read 4, iclass 25, count 2 2006.183.08:18:01.46#ibcon#read 4, iclass 25, count 2 2006.183.08:18:01.46#ibcon#about to read 5, iclass 25, count 2 2006.183.08:18:01.46#ibcon#read 5, iclass 25, count 2 2006.183.08:18:01.46#ibcon#about to read 6, iclass 25, count 2 2006.183.08:18:01.46#ibcon#read 6, iclass 25, count 2 2006.183.08:18:01.46#ibcon#end of sib2, iclass 25, count 2 2006.183.08:18:01.46#ibcon#*after write, iclass 25, count 2 2006.183.08:18:01.46#ibcon#*before return 0, iclass 25, count 2 2006.183.08:18:01.46#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:18:01.46#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:18:01.46#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.08:18:01.46#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:01.46#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:18:01.58#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:18:01.58#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:18:01.58#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:18:01.58#ibcon#first serial, iclass 25, count 0 2006.183.08:18:01.58#ibcon#enter sib2, iclass 25, count 0 2006.183.08:18:01.58#ibcon#flushed, iclass 25, count 0 2006.183.08:18:01.58#ibcon#about to write, iclass 25, count 0 2006.183.08:18:01.58#ibcon#wrote, iclass 25, count 0 2006.183.08:18:01.58#ibcon#about to read 3, iclass 25, count 0 2006.183.08:18:01.60#ibcon#read 3, iclass 25, count 0 2006.183.08:18:01.60#ibcon#about to read 4, iclass 25, count 0 2006.183.08:18:01.60#ibcon#read 4, iclass 25, count 0 2006.183.08:18:01.60#ibcon#about to read 5, iclass 25, count 0 2006.183.08:18:01.60#ibcon#read 5, iclass 25, count 0 2006.183.08:18:01.60#ibcon#about to read 6, iclass 25, count 0 2006.183.08:18:01.60#ibcon#read 6, iclass 25, count 0 2006.183.08:18:01.60#ibcon#end of sib2, iclass 25, count 0 2006.183.08:18:01.60#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:18:01.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:18:01.60#ibcon#[27=USB\r\n] 2006.183.08:18:01.60#ibcon#*before write, iclass 25, count 0 2006.183.08:18:01.60#ibcon#enter sib2, iclass 25, count 0 2006.183.08:18:01.60#ibcon#flushed, iclass 25, count 0 2006.183.08:18:01.60#ibcon#about to write, iclass 25, count 0 2006.183.08:18:01.60#ibcon#wrote, iclass 25, count 0 2006.183.08:18:01.60#ibcon#about to read 3, iclass 25, count 0 2006.183.08:18:01.63#ibcon#read 3, iclass 25, count 0 2006.183.08:18:01.63#ibcon#about to read 4, iclass 25, count 0 2006.183.08:18:01.63#ibcon#read 4, iclass 25, count 0 2006.183.08:18:01.63#ibcon#about to read 5, iclass 25, count 0 2006.183.08:18:01.63#ibcon#read 5, iclass 25, count 0 2006.183.08:18:01.63#ibcon#about to read 6, iclass 25, count 0 2006.183.08:18:01.63#ibcon#read 6, iclass 25, count 0 2006.183.08:18:01.63#ibcon#end of sib2, iclass 25, count 0 2006.183.08:18:01.63#ibcon#*after write, iclass 25, count 0 2006.183.08:18:01.63#ibcon#*before return 0, iclass 25, count 0 2006.183.08:18:01.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:18:01.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:18:01.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:18:01.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:18:01.63$vc4f8/vblo=4,712.99 2006.183.08:18:01.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.08:18:01.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.08:18:01.63#ibcon#ireg 17 cls_cnt 0 2006.183.08:18:01.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:18:01.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:18:01.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:18:01.63#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:18:01.63#ibcon#first serial, iclass 27, count 0 2006.183.08:18:01.63#ibcon#enter sib2, iclass 27, count 0 2006.183.08:18:01.63#ibcon#flushed, iclass 27, count 0 2006.183.08:18:01.63#ibcon#about to write, iclass 27, count 0 2006.183.08:18:01.63#ibcon#wrote, iclass 27, count 0 2006.183.08:18:01.63#ibcon#about to read 3, iclass 27, count 0 2006.183.08:18:01.65#ibcon#read 3, iclass 27, count 0 2006.183.08:18:01.65#ibcon#about to read 4, iclass 27, count 0 2006.183.08:18:01.65#ibcon#read 4, iclass 27, count 0 2006.183.08:18:01.65#ibcon#about to read 5, iclass 27, count 0 2006.183.08:18:01.65#ibcon#read 5, iclass 27, count 0 2006.183.08:18:01.65#ibcon#about to read 6, iclass 27, count 0 2006.183.08:18:01.65#ibcon#read 6, iclass 27, count 0 2006.183.08:18:01.65#ibcon#end of sib2, iclass 27, count 0 2006.183.08:18:01.65#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:18:01.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:18:01.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:18:01.65#ibcon#*before write, iclass 27, count 0 2006.183.08:18:01.65#ibcon#enter sib2, iclass 27, count 0 2006.183.08:18:01.65#ibcon#flushed, iclass 27, count 0 2006.183.08:18:01.65#ibcon#about to write, iclass 27, count 0 2006.183.08:18:01.65#ibcon#wrote, iclass 27, count 0 2006.183.08:18:01.65#ibcon#about to read 3, iclass 27, count 0 2006.183.08:18:01.69#ibcon#read 3, iclass 27, count 0 2006.183.08:18:01.69#ibcon#about to read 4, iclass 27, count 0 2006.183.08:18:01.69#ibcon#read 4, iclass 27, count 0 2006.183.08:18:01.69#ibcon#about to read 5, iclass 27, count 0 2006.183.08:18:01.69#ibcon#read 5, iclass 27, count 0 2006.183.08:18:01.69#ibcon#about to read 6, iclass 27, count 0 2006.183.08:18:01.69#ibcon#read 6, iclass 27, count 0 2006.183.08:18:01.69#ibcon#end of sib2, iclass 27, count 0 2006.183.08:18:01.69#ibcon#*after write, iclass 27, count 0 2006.183.08:18:01.69#ibcon#*before return 0, iclass 27, count 0 2006.183.08:18:01.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:18:01.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:18:01.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:18:01.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:18:01.69$vc4f8/vb=4,4 2006.183.08:18:01.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.08:18:01.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.08:18:01.69#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:01.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:18:01.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:18:01.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:18:01.75#ibcon#enter wrdev, iclass 29, count 2 2006.183.08:18:01.75#ibcon#first serial, iclass 29, count 2 2006.183.08:18:01.75#ibcon#enter sib2, iclass 29, count 2 2006.183.08:18:01.75#ibcon#flushed, iclass 29, count 2 2006.183.08:18:01.75#ibcon#about to write, iclass 29, count 2 2006.183.08:18:01.75#ibcon#wrote, iclass 29, count 2 2006.183.08:18:01.75#ibcon#about to read 3, iclass 29, count 2 2006.183.08:18:01.77#ibcon#read 3, iclass 29, count 2 2006.183.08:18:01.77#ibcon#about to read 4, iclass 29, count 2 2006.183.08:18:01.77#ibcon#read 4, iclass 29, count 2 2006.183.08:18:01.77#ibcon#about to read 5, iclass 29, count 2 2006.183.08:18:01.77#ibcon#read 5, iclass 29, count 2 2006.183.08:18:01.77#ibcon#about to read 6, iclass 29, count 2 2006.183.08:18:01.77#ibcon#read 6, iclass 29, count 2 2006.183.08:18:01.77#ibcon#end of sib2, iclass 29, count 2 2006.183.08:18:01.77#ibcon#*mode == 0, iclass 29, count 2 2006.183.08:18:01.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.08:18:01.77#ibcon#[27=AT04-04\r\n] 2006.183.08:18:01.77#ibcon#*before write, iclass 29, count 2 2006.183.08:18:01.77#ibcon#enter sib2, iclass 29, count 2 2006.183.08:18:01.77#ibcon#flushed, iclass 29, count 2 2006.183.08:18:01.77#ibcon#about to write, iclass 29, count 2 2006.183.08:18:01.77#ibcon#wrote, iclass 29, count 2 2006.183.08:18:01.77#ibcon#about to read 3, iclass 29, count 2 2006.183.08:18:01.80#ibcon#read 3, iclass 29, count 2 2006.183.08:18:01.80#ibcon#about to read 4, iclass 29, count 2 2006.183.08:18:01.80#ibcon#read 4, iclass 29, count 2 2006.183.08:18:01.80#ibcon#about to read 5, iclass 29, count 2 2006.183.08:18:01.80#ibcon#read 5, iclass 29, count 2 2006.183.08:18:01.80#ibcon#about to read 6, iclass 29, count 2 2006.183.08:18:01.80#ibcon#read 6, iclass 29, count 2 2006.183.08:18:01.80#ibcon#end of sib2, iclass 29, count 2 2006.183.08:18:01.80#ibcon#*after write, iclass 29, count 2 2006.183.08:18:01.80#ibcon#*before return 0, iclass 29, count 2 2006.183.08:18:01.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:18:01.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:18:01.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.08:18:01.80#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:01.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:18:01.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:18:01.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:18:01.92#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:18:01.92#ibcon#first serial, iclass 29, count 0 2006.183.08:18:01.92#ibcon#enter sib2, iclass 29, count 0 2006.183.08:18:01.92#ibcon#flushed, iclass 29, count 0 2006.183.08:18:01.92#ibcon#about to write, iclass 29, count 0 2006.183.08:18:01.92#ibcon#wrote, iclass 29, count 0 2006.183.08:18:01.92#ibcon#about to read 3, iclass 29, count 0 2006.183.08:18:01.94#ibcon#read 3, iclass 29, count 0 2006.183.08:18:01.94#ibcon#about to read 4, iclass 29, count 0 2006.183.08:18:01.94#ibcon#read 4, iclass 29, count 0 2006.183.08:18:01.94#ibcon#about to read 5, iclass 29, count 0 2006.183.08:18:01.94#ibcon#read 5, iclass 29, count 0 2006.183.08:18:01.94#ibcon#about to read 6, iclass 29, count 0 2006.183.08:18:01.94#ibcon#read 6, iclass 29, count 0 2006.183.08:18:01.94#ibcon#end of sib2, iclass 29, count 0 2006.183.08:18:01.94#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:18:01.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:18:01.94#ibcon#[27=USB\r\n] 2006.183.08:18:01.94#ibcon#*before write, iclass 29, count 0 2006.183.08:18:01.94#ibcon#enter sib2, iclass 29, count 0 2006.183.08:18:01.94#ibcon#flushed, iclass 29, count 0 2006.183.08:18:01.94#ibcon#about to write, iclass 29, count 0 2006.183.08:18:01.94#ibcon#wrote, iclass 29, count 0 2006.183.08:18:01.94#ibcon#about to read 3, iclass 29, count 0 2006.183.08:18:01.97#ibcon#read 3, iclass 29, count 0 2006.183.08:18:01.97#ibcon#about to read 4, iclass 29, count 0 2006.183.08:18:01.97#ibcon#read 4, iclass 29, count 0 2006.183.08:18:01.97#ibcon#about to read 5, iclass 29, count 0 2006.183.08:18:01.97#ibcon#read 5, iclass 29, count 0 2006.183.08:18:01.97#ibcon#about to read 6, iclass 29, count 0 2006.183.08:18:01.97#ibcon#read 6, iclass 29, count 0 2006.183.08:18:01.97#ibcon#end of sib2, iclass 29, count 0 2006.183.08:18:01.97#ibcon#*after write, iclass 29, count 0 2006.183.08:18:01.97#ibcon#*before return 0, iclass 29, count 0 2006.183.08:18:01.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:18:01.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:18:01.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:18:01.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:18:01.97$vc4f8/vblo=5,744.99 2006.183.08:18:01.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.08:18:01.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.08:18:01.97#ibcon#ireg 17 cls_cnt 0 2006.183.08:18:01.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:18:01.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:18:01.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:18:01.97#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:18:01.97#ibcon#first serial, iclass 31, count 0 2006.183.08:18:01.97#ibcon#enter sib2, iclass 31, count 0 2006.183.08:18:01.97#ibcon#flushed, iclass 31, count 0 2006.183.08:18:01.97#ibcon#about to write, iclass 31, count 0 2006.183.08:18:01.97#ibcon#wrote, iclass 31, count 0 2006.183.08:18:01.97#ibcon#about to read 3, iclass 31, count 0 2006.183.08:18:01.99#ibcon#read 3, iclass 31, count 0 2006.183.08:18:01.99#ibcon#about to read 4, iclass 31, count 0 2006.183.08:18:01.99#ibcon#read 4, iclass 31, count 0 2006.183.08:18:01.99#ibcon#about to read 5, iclass 31, count 0 2006.183.08:18:01.99#ibcon#read 5, iclass 31, count 0 2006.183.08:18:01.99#ibcon#about to read 6, iclass 31, count 0 2006.183.08:18:01.99#ibcon#read 6, iclass 31, count 0 2006.183.08:18:01.99#ibcon#end of sib2, iclass 31, count 0 2006.183.08:18:01.99#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:18:01.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:18:01.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:18:01.99#ibcon#*before write, iclass 31, count 0 2006.183.08:18:01.99#ibcon#enter sib2, iclass 31, count 0 2006.183.08:18:01.99#ibcon#flushed, iclass 31, count 0 2006.183.08:18:01.99#ibcon#about to write, iclass 31, count 0 2006.183.08:18:01.99#ibcon#wrote, iclass 31, count 0 2006.183.08:18:01.99#ibcon#about to read 3, iclass 31, count 0 2006.183.08:18:02.03#ibcon#read 3, iclass 31, count 0 2006.183.08:18:02.03#ibcon#about to read 4, iclass 31, count 0 2006.183.08:18:02.03#ibcon#read 4, iclass 31, count 0 2006.183.08:18:02.03#ibcon#about to read 5, iclass 31, count 0 2006.183.08:18:02.03#ibcon#read 5, iclass 31, count 0 2006.183.08:18:02.03#ibcon#about to read 6, iclass 31, count 0 2006.183.08:18:02.03#ibcon#read 6, iclass 31, count 0 2006.183.08:18:02.03#ibcon#end of sib2, iclass 31, count 0 2006.183.08:18:02.03#ibcon#*after write, iclass 31, count 0 2006.183.08:18:02.03#ibcon#*before return 0, iclass 31, count 0 2006.183.08:18:02.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:18:02.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:18:02.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:18:02.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:18:02.03$vc4f8/vb=5,4 2006.183.08:18:02.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.08:18:02.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.08:18:02.03#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:02.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:18:02.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:18:02.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:18:02.09#ibcon#enter wrdev, iclass 33, count 2 2006.183.08:18:02.09#ibcon#first serial, iclass 33, count 2 2006.183.08:18:02.09#ibcon#enter sib2, iclass 33, count 2 2006.183.08:18:02.09#ibcon#flushed, iclass 33, count 2 2006.183.08:18:02.09#ibcon#about to write, iclass 33, count 2 2006.183.08:18:02.09#ibcon#wrote, iclass 33, count 2 2006.183.08:18:02.09#ibcon#about to read 3, iclass 33, count 2 2006.183.08:18:02.11#ibcon#read 3, iclass 33, count 2 2006.183.08:18:02.11#ibcon#about to read 4, iclass 33, count 2 2006.183.08:18:02.11#ibcon#read 4, iclass 33, count 2 2006.183.08:18:02.11#ibcon#about to read 5, iclass 33, count 2 2006.183.08:18:02.11#ibcon#read 5, iclass 33, count 2 2006.183.08:18:02.11#ibcon#about to read 6, iclass 33, count 2 2006.183.08:18:02.11#ibcon#read 6, iclass 33, count 2 2006.183.08:18:02.11#ibcon#end of sib2, iclass 33, count 2 2006.183.08:18:02.11#ibcon#*mode == 0, iclass 33, count 2 2006.183.08:18:02.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.08:18:02.11#ibcon#[27=AT05-04\r\n] 2006.183.08:18:02.11#ibcon#*before write, iclass 33, count 2 2006.183.08:18:02.11#ibcon#enter sib2, iclass 33, count 2 2006.183.08:18:02.11#ibcon#flushed, iclass 33, count 2 2006.183.08:18:02.11#ibcon#about to write, iclass 33, count 2 2006.183.08:18:02.11#ibcon#wrote, iclass 33, count 2 2006.183.08:18:02.11#ibcon#about to read 3, iclass 33, count 2 2006.183.08:18:02.14#ibcon#read 3, iclass 33, count 2 2006.183.08:18:02.14#ibcon#about to read 4, iclass 33, count 2 2006.183.08:18:02.14#ibcon#read 4, iclass 33, count 2 2006.183.08:18:02.14#ibcon#about to read 5, iclass 33, count 2 2006.183.08:18:02.14#ibcon#read 5, iclass 33, count 2 2006.183.08:18:02.14#ibcon#about to read 6, iclass 33, count 2 2006.183.08:18:02.14#ibcon#read 6, iclass 33, count 2 2006.183.08:18:02.14#ibcon#end of sib2, iclass 33, count 2 2006.183.08:18:02.14#ibcon#*after write, iclass 33, count 2 2006.183.08:18:02.14#ibcon#*before return 0, iclass 33, count 2 2006.183.08:18:02.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:18:02.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:18:02.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.08:18:02.14#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:02.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:18:02.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:18:02.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:18:02.26#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:18:02.26#ibcon#first serial, iclass 33, count 0 2006.183.08:18:02.26#ibcon#enter sib2, iclass 33, count 0 2006.183.08:18:02.26#ibcon#flushed, iclass 33, count 0 2006.183.08:18:02.26#ibcon#about to write, iclass 33, count 0 2006.183.08:18:02.26#ibcon#wrote, iclass 33, count 0 2006.183.08:18:02.26#ibcon#about to read 3, iclass 33, count 0 2006.183.08:18:02.28#ibcon#read 3, iclass 33, count 0 2006.183.08:18:02.28#ibcon#about to read 4, iclass 33, count 0 2006.183.08:18:02.28#ibcon#read 4, iclass 33, count 0 2006.183.08:18:02.28#ibcon#about to read 5, iclass 33, count 0 2006.183.08:18:02.28#ibcon#read 5, iclass 33, count 0 2006.183.08:18:02.28#ibcon#about to read 6, iclass 33, count 0 2006.183.08:18:02.28#ibcon#read 6, iclass 33, count 0 2006.183.08:18:02.28#ibcon#end of sib2, iclass 33, count 0 2006.183.08:18:02.28#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:18:02.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:18:02.28#ibcon#[27=USB\r\n] 2006.183.08:18:02.28#ibcon#*before write, iclass 33, count 0 2006.183.08:18:02.28#ibcon#enter sib2, iclass 33, count 0 2006.183.08:18:02.28#ibcon#flushed, iclass 33, count 0 2006.183.08:18:02.28#ibcon#about to write, iclass 33, count 0 2006.183.08:18:02.28#ibcon#wrote, iclass 33, count 0 2006.183.08:18:02.28#ibcon#about to read 3, iclass 33, count 0 2006.183.08:18:02.31#ibcon#read 3, iclass 33, count 0 2006.183.08:18:02.31#ibcon#about to read 4, iclass 33, count 0 2006.183.08:18:02.31#ibcon#read 4, iclass 33, count 0 2006.183.08:18:02.31#ibcon#about to read 5, iclass 33, count 0 2006.183.08:18:02.31#ibcon#read 5, iclass 33, count 0 2006.183.08:18:02.31#ibcon#about to read 6, iclass 33, count 0 2006.183.08:18:02.31#ibcon#read 6, iclass 33, count 0 2006.183.08:18:02.31#ibcon#end of sib2, iclass 33, count 0 2006.183.08:18:02.31#ibcon#*after write, iclass 33, count 0 2006.183.08:18:02.31#ibcon#*before return 0, iclass 33, count 0 2006.183.08:18:02.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:18:02.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:18:02.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:18:02.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:18:02.31$vc4f8/vblo=6,752.99 2006.183.08:18:02.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.08:18:02.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.08:18:02.31#ibcon#ireg 17 cls_cnt 0 2006.183.08:18:02.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:18:02.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:18:02.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:18:02.31#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:18:02.31#ibcon#first serial, iclass 35, count 0 2006.183.08:18:02.31#ibcon#enter sib2, iclass 35, count 0 2006.183.08:18:02.31#ibcon#flushed, iclass 35, count 0 2006.183.08:18:02.31#ibcon#about to write, iclass 35, count 0 2006.183.08:18:02.31#ibcon#wrote, iclass 35, count 0 2006.183.08:18:02.31#ibcon#about to read 3, iclass 35, count 0 2006.183.08:18:02.34#ibcon#read 3, iclass 35, count 0 2006.183.08:18:02.34#ibcon#about to read 4, iclass 35, count 0 2006.183.08:18:02.34#ibcon#read 4, iclass 35, count 0 2006.183.08:18:02.34#ibcon#about to read 5, iclass 35, count 0 2006.183.08:18:02.34#ibcon#read 5, iclass 35, count 0 2006.183.08:18:02.34#ibcon#about to read 6, iclass 35, count 0 2006.183.08:18:02.34#ibcon#read 6, iclass 35, count 0 2006.183.08:18:02.34#ibcon#end of sib2, iclass 35, count 0 2006.183.08:18:02.34#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:18:02.34#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:18:02.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:18:02.34#ibcon#*before write, iclass 35, count 0 2006.183.08:18:02.34#ibcon#enter sib2, iclass 35, count 0 2006.183.08:18:02.34#ibcon#flushed, iclass 35, count 0 2006.183.08:18:02.34#ibcon#about to write, iclass 35, count 0 2006.183.08:18:02.34#ibcon#wrote, iclass 35, count 0 2006.183.08:18:02.34#ibcon#about to read 3, iclass 35, count 0 2006.183.08:18:02.38#ibcon#read 3, iclass 35, count 0 2006.183.08:18:02.38#ibcon#about to read 4, iclass 35, count 0 2006.183.08:18:02.38#ibcon#read 4, iclass 35, count 0 2006.183.08:18:02.38#ibcon#about to read 5, iclass 35, count 0 2006.183.08:18:02.38#ibcon#read 5, iclass 35, count 0 2006.183.08:18:02.38#ibcon#about to read 6, iclass 35, count 0 2006.183.08:18:02.38#ibcon#read 6, iclass 35, count 0 2006.183.08:18:02.38#ibcon#end of sib2, iclass 35, count 0 2006.183.08:18:02.38#ibcon#*after write, iclass 35, count 0 2006.183.08:18:02.38#ibcon#*before return 0, iclass 35, count 0 2006.183.08:18:02.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:18:02.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:18:02.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:18:02.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:18:02.38$vc4f8/vb=6,4 2006.183.08:18:02.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.08:18:02.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.08:18:02.38#ibcon#ireg 11 cls_cnt 2 2006.183.08:18:02.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:18:02.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:18:02.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:18:02.43#ibcon#enter wrdev, iclass 37, count 2 2006.183.08:18:02.43#ibcon#first serial, iclass 37, count 2 2006.183.08:18:02.43#ibcon#enter sib2, iclass 37, count 2 2006.183.08:18:02.43#ibcon#flushed, iclass 37, count 2 2006.183.08:18:02.43#ibcon#about to write, iclass 37, count 2 2006.183.08:18:02.43#ibcon#wrote, iclass 37, count 2 2006.183.08:18:02.43#ibcon#about to read 3, iclass 37, count 2 2006.183.08:18:02.45#ibcon#read 3, iclass 37, count 2 2006.183.08:18:02.45#ibcon#about to read 4, iclass 37, count 2 2006.183.08:18:02.45#ibcon#read 4, iclass 37, count 2 2006.183.08:18:02.45#ibcon#about to read 5, iclass 37, count 2 2006.183.08:18:02.45#ibcon#read 5, iclass 37, count 2 2006.183.08:18:02.45#ibcon#about to read 6, iclass 37, count 2 2006.183.08:18:02.45#ibcon#read 6, iclass 37, count 2 2006.183.08:18:02.45#ibcon#end of sib2, iclass 37, count 2 2006.183.08:18:02.45#ibcon#*mode == 0, iclass 37, count 2 2006.183.08:18:02.45#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.08:18:02.45#ibcon#[27=AT06-04\r\n] 2006.183.08:18:02.45#ibcon#*before write, iclass 37, count 2 2006.183.08:18:02.45#ibcon#enter sib2, iclass 37, count 2 2006.183.08:18:02.45#ibcon#flushed, iclass 37, count 2 2006.183.08:18:02.45#ibcon#about to write, iclass 37, count 2 2006.183.08:18:02.45#ibcon#wrote, iclass 37, count 2 2006.183.08:18:02.45#ibcon#about to read 3, iclass 37, count 2 2006.183.08:18:02.48#ibcon#read 3, iclass 37, count 2 2006.183.08:18:02.48#ibcon#about to read 4, iclass 37, count 2 2006.183.08:18:02.48#ibcon#read 4, iclass 37, count 2 2006.183.08:18:02.48#ibcon#about to read 5, iclass 37, count 2 2006.183.08:18:02.48#ibcon#read 5, iclass 37, count 2 2006.183.08:18:02.48#ibcon#about to read 6, iclass 37, count 2 2006.183.08:18:02.48#ibcon#read 6, iclass 37, count 2 2006.183.08:18:02.48#ibcon#end of sib2, iclass 37, count 2 2006.183.08:18:02.48#ibcon#*after write, iclass 37, count 2 2006.183.08:18:02.48#ibcon#*before return 0, iclass 37, count 2 2006.183.08:18:02.48#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:18:02.48#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:18:02.48#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.08:18:02.48#ibcon#ireg 7 cls_cnt 0 2006.183.08:18:02.48#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:18:02.60#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:18:02.60#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:18:02.60#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:18:02.60#ibcon#first serial, iclass 37, count 0 2006.183.08:18:02.60#ibcon#enter sib2, iclass 37, count 0 2006.183.08:18:02.60#ibcon#flushed, iclass 37, count 0 2006.183.08:18:02.60#ibcon#about to write, iclass 37, count 0 2006.183.08:18:02.60#ibcon#wrote, iclass 37, count 0 2006.183.08:18:02.60#ibcon#about to read 3, iclass 37, count 0 2006.183.08:18:02.62#ibcon#read 3, iclass 37, count 0 2006.183.08:18:02.62#ibcon#about to read 4, iclass 37, count 0 2006.183.08:18:02.62#ibcon#read 4, iclass 37, count 0 2006.183.08:18:02.62#ibcon#about to read 5, iclass 37, count 0 2006.183.08:18:02.62#ibcon#read 5, iclass 37, count 0 2006.183.08:18:02.62#ibcon#about to read 6, iclass 37, count 0 2006.183.08:18:02.62#ibcon#read 6, iclass 37, count 0 2006.183.08:18:02.62#ibcon#end of sib2, iclass 37, count 0 2006.183.08:18:02.62#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:18:02.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:18:02.62#ibcon#[27=USB\r\n] 2006.183.08:18:02.62#ibcon#*before write, iclass 37, count 0 2006.183.08:18:02.62#ibcon#enter sib2, iclass 37, count 0 2006.183.08:18:02.62#ibcon#flushed, iclass 37, count 0 2006.183.08:18:02.62#ibcon#about to write, iclass 37, count 0 2006.183.08:18:02.62#ibcon#wrote, iclass 37, count 0 2006.183.08:18:02.62#ibcon#about to read 3, iclass 37, count 0 2006.183.08:18:02.65#ibcon#read 3, iclass 37, count 0 2006.183.08:18:02.65#ibcon#about to read 4, iclass 37, count 0 2006.183.08:18:02.65#ibcon#read 4, iclass 37, count 0 2006.183.08:18:02.65#ibcon#about to read 5, iclass 37, count 0 2006.183.08:18:02.65#ibcon#read 5, iclass 37, count 0 2006.183.08:18:02.65#ibcon#about to read 6, iclass 37, count 0 2006.183.08:18:02.65#ibcon#read 6, iclass 37, count 0 2006.183.08:18:02.65#ibcon#end of sib2, iclass 37, count 0 2006.183.08:18:02.65#ibcon#*after write, iclass 37, count 0 2006.183.08:18:02.65#ibcon#*before return 0, iclass 37, count 0 2006.183.08:18:02.65#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:18:02.65#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:18:02.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:18:02.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:18:02.65$vc4f8/vabw=wide 2006.183.08:18:02.65#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.08:18:02.65#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.08:18:02.65#ibcon#ireg 8 cls_cnt 0 2006.183.08:18:02.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:18:02.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:18:02.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:18:02.65#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:18:02.65#ibcon#first serial, iclass 39, count 0 2006.183.08:18:02.65#ibcon#enter sib2, iclass 39, count 0 2006.183.08:18:02.65#ibcon#flushed, iclass 39, count 0 2006.183.08:18:02.65#ibcon#about to write, iclass 39, count 0 2006.183.08:18:02.65#ibcon#wrote, iclass 39, count 0 2006.183.08:18:02.65#ibcon#about to read 3, iclass 39, count 0 2006.183.08:18:02.67#ibcon#read 3, iclass 39, count 0 2006.183.08:18:02.67#ibcon#about to read 4, iclass 39, count 0 2006.183.08:18:02.67#ibcon#read 4, iclass 39, count 0 2006.183.08:18:02.67#ibcon#about to read 5, iclass 39, count 0 2006.183.08:18:02.67#ibcon#read 5, iclass 39, count 0 2006.183.08:18:02.67#ibcon#about to read 6, iclass 39, count 0 2006.183.08:18:02.67#ibcon#read 6, iclass 39, count 0 2006.183.08:18:02.67#ibcon#end of sib2, iclass 39, count 0 2006.183.08:18:02.67#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:18:02.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:18:02.67#ibcon#[25=BW32\r\n] 2006.183.08:18:02.67#ibcon#*before write, iclass 39, count 0 2006.183.08:18:02.67#ibcon#enter sib2, iclass 39, count 0 2006.183.08:18:02.67#ibcon#flushed, iclass 39, count 0 2006.183.08:18:02.67#ibcon#about to write, iclass 39, count 0 2006.183.08:18:02.67#ibcon#wrote, iclass 39, count 0 2006.183.08:18:02.67#ibcon#about to read 3, iclass 39, count 0 2006.183.08:18:02.70#ibcon#read 3, iclass 39, count 0 2006.183.08:18:02.70#ibcon#about to read 4, iclass 39, count 0 2006.183.08:18:02.70#ibcon#read 4, iclass 39, count 0 2006.183.08:18:02.70#ibcon#about to read 5, iclass 39, count 0 2006.183.08:18:02.70#ibcon#read 5, iclass 39, count 0 2006.183.08:18:02.70#ibcon#about to read 6, iclass 39, count 0 2006.183.08:18:02.70#ibcon#read 6, iclass 39, count 0 2006.183.08:18:02.70#ibcon#end of sib2, iclass 39, count 0 2006.183.08:18:02.70#ibcon#*after write, iclass 39, count 0 2006.183.08:18:02.70#ibcon#*before return 0, iclass 39, count 0 2006.183.08:18:02.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:18:02.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:18:02.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:18:02.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:18:02.70$vc4f8/vbbw=wide 2006.183.08:18:02.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:18:02.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:18:02.70#ibcon#ireg 8 cls_cnt 0 2006.183.08:18:02.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:18:02.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:18:02.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:18:02.77#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:18:02.77#ibcon#first serial, iclass 3, count 0 2006.183.08:18:02.77#ibcon#enter sib2, iclass 3, count 0 2006.183.08:18:02.77#ibcon#flushed, iclass 3, count 0 2006.183.08:18:02.77#ibcon#about to write, iclass 3, count 0 2006.183.08:18:02.77#ibcon#wrote, iclass 3, count 0 2006.183.08:18:02.77#ibcon#about to read 3, iclass 3, count 0 2006.183.08:18:02.79#ibcon#read 3, iclass 3, count 0 2006.183.08:18:02.79#ibcon#about to read 4, iclass 3, count 0 2006.183.08:18:02.79#ibcon#read 4, iclass 3, count 0 2006.183.08:18:02.79#ibcon#about to read 5, iclass 3, count 0 2006.183.08:18:02.79#ibcon#read 5, iclass 3, count 0 2006.183.08:18:02.79#ibcon#about to read 6, iclass 3, count 0 2006.183.08:18:02.79#ibcon#read 6, iclass 3, count 0 2006.183.08:18:02.79#ibcon#end of sib2, iclass 3, count 0 2006.183.08:18:02.79#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:18:02.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:18:02.79#ibcon#[27=BW32\r\n] 2006.183.08:18:02.79#ibcon#*before write, iclass 3, count 0 2006.183.08:18:02.79#ibcon#enter sib2, iclass 3, count 0 2006.183.08:18:02.79#ibcon#flushed, iclass 3, count 0 2006.183.08:18:02.79#ibcon#about to write, iclass 3, count 0 2006.183.08:18:02.79#ibcon#wrote, iclass 3, count 0 2006.183.08:18:02.79#ibcon#about to read 3, iclass 3, count 0 2006.183.08:18:02.82#ibcon#read 3, iclass 3, count 0 2006.183.08:18:02.82#ibcon#about to read 4, iclass 3, count 0 2006.183.08:18:02.82#ibcon#read 4, iclass 3, count 0 2006.183.08:18:02.82#ibcon#about to read 5, iclass 3, count 0 2006.183.08:18:02.82#ibcon#read 5, iclass 3, count 0 2006.183.08:18:02.82#ibcon#about to read 6, iclass 3, count 0 2006.183.08:18:02.82#ibcon#read 6, iclass 3, count 0 2006.183.08:18:02.82#ibcon#end of sib2, iclass 3, count 0 2006.183.08:18:02.82#ibcon#*after write, iclass 3, count 0 2006.183.08:18:02.82#ibcon#*before return 0, iclass 3, count 0 2006.183.08:18:02.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:18:02.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:18:02.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:18:02.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:18:02.82$4f8m12a/ifd4f 2006.183.08:18:02.82$ifd4f/lo= 2006.183.08:18:02.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:18:02.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:18:02.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:18:02.82$ifd4f/patch= 2006.183.08:18:02.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:18:02.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:18:02.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:18:02.82$4f8m12a/"form=m,16.000,1:2 2006.183.08:18:02.82$4f8m12a/"tpicd 2006.183.08:18:02.82$4f8m12a/echo=off 2006.183.08:18:02.82$4f8m12a/xlog=off 2006.183.08:18:02.82:!2006.183.08:19:40 2006.183.08:18:16.14#trakl#Source acquired 2006.183.08:18:17.14#flagr#flagr/antenna,acquired 2006.183.08:19:40.00:preob 2006.183.08:19:40.14/onsource/TRACKING 2006.183.08:19:40.14:!2006.183.08:19:50 2006.183.08:19:50.00:data_valid=on 2006.183.08:19:50.00:midob 2006.183.08:19:50.14/onsource/TRACKING 2006.183.08:19:50.14/wx/28.31,996.6,87 2006.183.08:19:50.28/cable/+6.4501E-03 2006.183.08:19:51.37/va/01,08,usb,yes,29,30 2006.183.08:19:51.37/va/02,07,usb,yes,29,30 2006.183.08:19:51.37/va/03,06,usb,yes,30,31 2006.183.08:19:51.37/va/04,07,usb,yes,30,32 2006.183.08:19:51.37/va/05,07,usb,yes,31,33 2006.183.08:19:51.37/va/06,06,usb,yes,30,30 2006.183.08:19:51.37/va/07,06,usb,yes,31,30 2006.183.08:19:51.37/va/08,07,usb,yes,29,29 2006.183.08:19:51.60/valo/01,532.99,yes,locked 2006.183.08:19:51.60/valo/02,572.99,yes,locked 2006.183.08:19:51.60/valo/03,672.99,yes,locked 2006.183.08:19:51.60/valo/04,832.99,yes,locked 2006.183.08:19:51.60/valo/05,652.99,yes,locked 2006.183.08:19:51.60/valo/06,772.99,yes,locked 2006.183.08:19:51.60/valo/07,832.99,yes,locked 2006.183.08:19:51.60/valo/08,852.99,yes,locked 2006.183.08:19:52.69/vb/01,04,usb,yes,29,28 2006.183.08:19:52.69/vb/02,04,usb,yes,31,32 2006.183.08:19:52.69/vb/03,04,usb,yes,27,31 2006.183.08:19:52.69/vb/04,04,usb,yes,28,28 2006.183.08:19:52.69/vb/05,04,usb,yes,27,30 2006.183.08:19:52.69/vb/06,04,usb,yes,28,30 2006.183.08:19:52.69/vb/07,04,usb,yes,30,29 2006.183.08:19:52.69/vb/08,04,usb,yes,27,30 2006.183.08:19:52.92/vblo/01,632.99,yes,locked 2006.183.08:19:52.92/vblo/02,640.99,yes,locked 2006.183.08:19:52.92/vblo/03,656.99,yes,locked 2006.183.08:19:52.92/vblo/04,712.99,yes,locked 2006.183.08:19:52.92/vblo/05,744.99,yes,locked 2006.183.08:19:52.92/vblo/06,752.99,yes,locked 2006.183.08:19:52.92/vblo/07,734.99,yes,locked 2006.183.08:19:52.92/vblo/08,744.99,yes,locked 2006.183.08:19:53.07/vabw/8 2006.183.08:19:53.22/vbbw/8 2006.183.08:19:53.43/xfe/off,on,14.7 2006.183.08:19:53.81/ifatt/23,28,28,28 2006.183.08:19:54.08/fmout-gps/S +3.38E-07 2006.183.08:19:54.16:!2006.183.08:20:50 2006.183.08:20:50.00:data_valid=off 2006.183.08:20:50.01:postob 2006.183.08:20:50.16/cable/+6.4496E-03 2006.183.08:20:50.17/wx/28.30,996.6,86 2006.183.08:20:51.07/fmout-gps/S +3.38E-07 2006.183.08:20:51.08:scan_name=183-0823,k06183,60 2006.183.08:20:51.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.183.08:20:51.14#flagr#flagr/antenna,new-source 2006.183.08:20:52.14:checkk5 2006.183.08:20:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:20:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:20:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:20:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:20:54.01/chk_obsdata//k5ts1/T1830819??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:20:54.38/chk_obsdata//k5ts2/T1830819??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:20:54.76/chk_obsdata//k5ts3/T1830819??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:20:55.13/chk_obsdata//k5ts4/T1830819??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:20:55.83/k5log//k5ts1_log_newline 2006.183.08:20:56.54/k5log//k5ts2_log_newline 2006.183.08:20:57.25/k5log//k5ts3_log_newline 2006.183.08:20:57.95/k5log//k5ts4_log_newline 2006.183.08:20:57.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:20:57.97:4f8m12a=3 2006.183.08:20:57.97$4f8m12a/echo=on 2006.183.08:20:57.97$4f8m12a/pcalon 2006.183.08:20:57.98$pcalon/"no phase cal control is implemented here 2006.183.08:20:57.98$4f8m12a/"tpicd=stop 2006.183.08:20:57.98$4f8m12a/vc4f8 2006.183.08:20:57.98$vc4f8/valo=1,532.99 2006.183.08:20:57.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.08:20:57.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.08:20:57.98#ibcon#ireg 17 cls_cnt 0 2006.183.08:20:57.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:20:57.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:20:57.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:20:57.98#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:20:57.98#ibcon#first serial, iclass 40, count 0 2006.183.08:20:57.98#ibcon#enter sib2, iclass 40, count 0 2006.183.08:20:57.98#ibcon#flushed, iclass 40, count 0 2006.183.08:20:57.98#ibcon#about to write, iclass 40, count 0 2006.183.08:20:57.98#ibcon#wrote, iclass 40, count 0 2006.183.08:20:57.98#ibcon#about to read 3, iclass 40, count 0 2006.183.08:20:58.02#ibcon#read 3, iclass 40, count 0 2006.183.08:20:58.02#ibcon#about to read 4, iclass 40, count 0 2006.183.08:20:58.02#ibcon#read 4, iclass 40, count 0 2006.183.08:20:58.02#ibcon#about to read 5, iclass 40, count 0 2006.183.08:20:58.02#ibcon#read 5, iclass 40, count 0 2006.183.08:20:58.02#ibcon#about to read 6, iclass 40, count 0 2006.183.08:20:58.02#ibcon#read 6, iclass 40, count 0 2006.183.08:20:58.02#ibcon#end of sib2, iclass 40, count 0 2006.183.08:20:58.02#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:20:58.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:20:58.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:20:58.02#ibcon#*before write, iclass 40, count 0 2006.183.08:20:58.02#ibcon#enter sib2, iclass 40, count 0 2006.183.08:20:58.02#ibcon#flushed, iclass 40, count 0 2006.183.08:20:58.02#ibcon#about to write, iclass 40, count 0 2006.183.08:20:58.02#ibcon#wrote, iclass 40, count 0 2006.183.08:20:58.02#ibcon#about to read 3, iclass 40, count 0 2006.183.08:20:58.06#ibcon#read 3, iclass 40, count 0 2006.183.08:20:58.06#ibcon#about to read 4, iclass 40, count 0 2006.183.08:20:58.06#ibcon#read 4, iclass 40, count 0 2006.183.08:20:58.06#ibcon#about to read 5, iclass 40, count 0 2006.183.08:20:58.06#ibcon#read 5, iclass 40, count 0 2006.183.08:20:58.06#ibcon#about to read 6, iclass 40, count 0 2006.183.08:20:58.06#ibcon#read 6, iclass 40, count 0 2006.183.08:20:58.06#ibcon#end of sib2, iclass 40, count 0 2006.183.08:20:58.06#ibcon#*after write, iclass 40, count 0 2006.183.08:20:58.06#ibcon#*before return 0, iclass 40, count 0 2006.183.08:20:58.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:20:58.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:20:58.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:20:58.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:20:58.06$vc4f8/va=1,8 2006.183.08:20:58.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.08:20:58.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.08:20:58.06#ibcon#ireg 11 cls_cnt 2 2006.183.08:20:58.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:20:58.06#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:20:58.06#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:20:58.06#ibcon#enter wrdev, iclass 4, count 2 2006.183.08:20:58.06#ibcon#first serial, iclass 4, count 2 2006.183.08:20:58.06#ibcon#enter sib2, iclass 4, count 2 2006.183.08:20:58.06#ibcon#flushed, iclass 4, count 2 2006.183.08:20:58.06#ibcon#about to write, iclass 4, count 2 2006.183.08:20:58.06#ibcon#wrote, iclass 4, count 2 2006.183.08:20:58.06#ibcon#about to read 3, iclass 4, count 2 2006.183.08:20:58.08#ibcon#read 3, iclass 4, count 2 2006.183.08:20:58.08#ibcon#about to read 4, iclass 4, count 2 2006.183.08:20:58.08#ibcon#read 4, iclass 4, count 2 2006.183.08:20:58.08#ibcon#about to read 5, iclass 4, count 2 2006.183.08:20:58.08#ibcon#read 5, iclass 4, count 2 2006.183.08:20:58.08#ibcon#about to read 6, iclass 4, count 2 2006.183.08:20:58.08#ibcon#read 6, iclass 4, count 2 2006.183.08:20:58.08#ibcon#end of sib2, iclass 4, count 2 2006.183.08:20:58.08#ibcon#*mode == 0, iclass 4, count 2 2006.183.08:20:58.08#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.08:20:58.08#ibcon#[25=AT01-08\r\n] 2006.183.08:20:58.08#ibcon#*before write, iclass 4, count 2 2006.183.08:20:58.08#ibcon#enter sib2, iclass 4, count 2 2006.183.08:20:58.08#ibcon#flushed, iclass 4, count 2 2006.183.08:20:58.08#ibcon#about to write, iclass 4, count 2 2006.183.08:20:58.08#ibcon#wrote, iclass 4, count 2 2006.183.08:20:58.08#ibcon#about to read 3, iclass 4, count 2 2006.183.08:20:58.11#ibcon#read 3, iclass 4, count 2 2006.183.08:20:58.11#ibcon#about to read 4, iclass 4, count 2 2006.183.08:20:58.11#ibcon#read 4, iclass 4, count 2 2006.183.08:20:58.11#ibcon#about to read 5, iclass 4, count 2 2006.183.08:20:58.11#ibcon#read 5, iclass 4, count 2 2006.183.08:20:58.11#ibcon#about to read 6, iclass 4, count 2 2006.183.08:20:58.11#ibcon#read 6, iclass 4, count 2 2006.183.08:20:58.11#ibcon#end of sib2, iclass 4, count 2 2006.183.08:20:58.11#ibcon#*after write, iclass 4, count 2 2006.183.08:20:58.11#ibcon#*before return 0, iclass 4, count 2 2006.183.08:20:58.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:20:58.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:20:58.11#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.08:20:58.11#ibcon#ireg 7 cls_cnt 0 2006.183.08:20:58.11#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:20:58.23#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:20:58.23#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:20:58.23#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:20:58.23#ibcon#first serial, iclass 4, count 0 2006.183.08:20:58.23#ibcon#enter sib2, iclass 4, count 0 2006.183.08:20:58.23#ibcon#flushed, iclass 4, count 0 2006.183.08:20:58.23#ibcon#about to write, iclass 4, count 0 2006.183.08:20:58.23#ibcon#wrote, iclass 4, count 0 2006.183.08:20:58.23#ibcon#about to read 3, iclass 4, count 0 2006.183.08:20:58.25#ibcon#read 3, iclass 4, count 0 2006.183.08:20:58.25#ibcon#about to read 4, iclass 4, count 0 2006.183.08:20:58.25#ibcon#read 4, iclass 4, count 0 2006.183.08:20:58.25#ibcon#about to read 5, iclass 4, count 0 2006.183.08:20:58.25#ibcon#read 5, iclass 4, count 0 2006.183.08:20:58.25#ibcon#about to read 6, iclass 4, count 0 2006.183.08:20:58.25#ibcon#read 6, iclass 4, count 0 2006.183.08:20:58.25#ibcon#end of sib2, iclass 4, count 0 2006.183.08:20:58.25#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:20:58.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:20:58.25#ibcon#[25=USB\r\n] 2006.183.08:20:58.25#ibcon#*before write, iclass 4, count 0 2006.183.08:20:58.25#ibcon#enter sib2, iclass 4, count 0 2006.183.08:20:58.25#ibcon#flushed, iclass 4, count 0 2006.183.08:20:58.25#ibcon#about to write, iclass 4, count 0 2006.183.08:20:58.25#ibcon#wrote, iclass 4, count 0 2006.183.08:20:58.25#ibcon#about to read 3, iclass 4, count 0 2006.183.08:20:58.28#ibcon#read 3, iclass 4, count 0 2006.183.08:20:58.28#ibcon#about to read 4, iclass 4, count 0 2006.183.08:20:58.28#ibcon#read 4, iclass 4, count 0 2006.183.08:20:58.28#ibcon#about to read 5, iclass 4, count 0 2006.183.08:20:58.28#ibcon#read 5, iclass 4, count 0 2006.183.08:20:58.28#ibcon#about to read 6, iclass 4, count 0 2006.183.08:20:58.28#ibcon#read 6, iclass 4, count 0 2006.183.08:20:58.28#ibcon#end of sib2, iclass 4, count 0 2006.183.08:20:58.28#ibcon#*after write, iclass 4, count 0 2006.183.08:20:58.28#ibcon#*before return 0, iclass 4, count 0 2006.183.08:20:58.28#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:20:58.28#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:20:58.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:20:58.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:20:58.28$vc4f8/valo=2,572.99 2006.183.08:20:58.28#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.08:20:58.28#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.08:20:58.28#ibcon#ireg 17 cls_cnt 0 2006.183.08:20:58.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:20:58.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:20:58.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:20:58.28#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:20:58.28#ibcon#first serial, iclass 6, count 0 2006.183.08:20:58.28#ibcon#enter sib2, iclass 6, count 0 2006.183.08:20:58.28#ibcon#flushed, iclass 6, count 0 2006.183.08:20:58.28#ibcon#about to write, iclass 6, count 0 2006.183.08:20:58.28#ibcon#wrote, iclass 6, count 0 2006.183.08:20:58.28#ibcon#about to read 3, iclass 6, count 0 2006.183.08:20:58.31#ibcon#read 3, iclass 6, count 0 2006.183.08:20:58.31#ibcon#about to read 4, iclass 6, count 0 2006.183.08:20:58.31#ibcon#read 4, iclass 6, count 0 2006.183.08:20:58.31#ibcon#about to read 5, iclass 6, count 0 2006.183.08:20:58.31#ibcon#read 5, iclass 6, count 0 2006.183.08:20:58.31#ibcon#about to read 6, iclass 6, count 0 2006.183.08:20:58.31#ibcon#read 6, iclass 6, count 0 2006.183.08:20:58.31#ibcon#end of sib2, iclass 6, count 0 2006.183.08:20:58.31#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:20:58.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:20:58.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:20:58.31#ibcon#*before write, iclass 6, count 0 2006.183.08:20:58.31#ibcon#enter sib2, iclass 6, count 0 2006.183.08:20:58.31#ibcon#flushed, iclass 6, count 0 2006.183.08:20:58.31#ibcon#about to write, iclass 6, count 0 2006.183.08:20:58.31#ibcon#wrote, iclass 6, count 0 2006.183.08:20:58.31#ibcon#about to read 3, iclass 6, count 0 2006.183.08:20:58.35#ibcon#read 3, iclass 6, count 0 2006.183.08:20:58.35#ibcon#about to read 4, iclass 6, count 0 2006.183.08:20:58.35#ibcon#read 4, iclass 6, count 0 2006.183.08:20:58.35#ibcon#about to read 5, iclass 6, count 0 2006.183.08:20:58.35#ibcon#read 5, iclass 6, count 0 2006.183.08:20:58.35#ibcon#about to read 6, iclass 6, count 0 2006.183.08:20:58.35#ibcon#read 6, iclass 6, count 0 2006.183.08:20:58.35#ibcon#end of sib2, iclass 6, count 0 2006.183.08:20:58.35#ibcon#*after write, iclass 6, count 0 2006.183.08:20:58.35#ibcon#*before return 0, iclass 6, count 0 2006.183.08:20:58.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:20:58.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:20:58.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:20:58.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:20:58.35$vc4f8/va=2,7 2006.183.08:20:58.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.08:20:58.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.08:20:58.35#ibcon#ireg 11 cls_cnt 2 2006.183.08:20:58.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:20:58.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:20:58.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:20:58.40#ibcon#enter wrdev, iclass 10, count 2 2006.183.08:20:58.40#ibcon#first serial, iclass 10, count 2 2006.183.08:20:58.40#ibcon#enter sib2, iclass 10, count 2 2006.183.08:20:58.40#ibcon#flushed, iclass 10, count 2 2006.183.08:20:58.40#ibcon#about to write, iclass 10, count 2 2006.183.08:20:58.40#ibcon#wrote, iclass 10, count 2 2006.183.08:20:58.40#ibcon#about to read 3, iclass 10, count 2 2006.183.08:20:58.42#ibcon#read 3, iclass 10, count 2 2006.183.08:20:58.42#ibcon#about to read 4, iclass 10, count 2 2006.183.08:20:58.42#ibcon#read 4, iclass 10, count 2 2006.183.08:20:58.42#ibcon#about to read 5, iclass 10, count 2 2006.183.08:20:58.42#ibcon#read 5, iclass 10, count 2 2006.183.08:20:58.42#ibcon#about to read 6, iclass 10, count 2 2006.183.08:20:58.42#ibcon#read 6, iclass 10, count 2 2006.183.08:20:58.42#ibcon#end of sib2, iclass 10, count 2 2006.183.08:20:58.42#ibcon#*mode == 0, iclass 10, count 2 2006.183.08:20:58.42#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.08:20:58.42#ibcon#[25=AT02-07\r\n] 2006.183.08:20:58.42#ibcon#*before write, iclass 10, count 2 2006.183.08:20:58.42#ibcon#enter sib2, iclass 10, count 2 2006.183.08:20:58.42#ibcon#flushed, iclass 10, count 2 2006.183.08:20:58.42#ibcon#about to write, iclass 10, count 2 2006.183.08:20:58.42#ibcon#wrote, iclass 10, count 2 2006.183.08:20:58.42#ibcon#about to read 3, iclass 10, count 2 2006.183.08:20:58.45#ibcon#read 3, iclass 10, count 2 2006.183.08:20:58.45#ibcon#about to read 4, iclass 10, count 2 2006.183.08:20:58.45#ibcon#read 4, iclass 10, count 2 2006.183.08:20:58.45#ibcon#about to read 5, iclass 10, count 2 2006.183.08:20:58.45#ibcon#read 5, iclass 10, count 2 2006.183.08:20:58.45#ibcon#about to read 6, iclass 10, count 2 2006.183.08:20:58.45#ibcon#read 6, iclass 10, count 2 2006.183.08:20:58.45#ibcon#end of sib2, iclass 10, count 2 2006.183.08:20:58.45#ibcon#*after write, iclass 10, count 2 2006.183.08:20:58.45#ibcon#*before return 0, iclass 10, count 2 2006.183.08:20:58.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:20:58.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:20:58.45#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.08:20:58.45#ibcon#ireg 7 cls_cnt 0 2006.183.08:20:58.45#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:20:58.57#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:20:58.57#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:20:58.57#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:20:58.57#ibcon#first serial, iclass 10, count 0 2006.183.08:20:58.57#ibcon#enter sib2, iclass 10, count 0 2006.183.08:20:58.57#ibcon#flushed, iclass 10, count 0 2006.183.08:20:58.57#ibcon#about to write, iclass 10, count 0 2006.183.08:20:58.57#ibcon#wrote, iclass 10, count 0 2006.183.08:20:58.57#ibcon#about to read 3, iclass 10, count 0 2006.183.08:20:58.59#ibcon#read 3, iclass 10, count 0 2006.183.08:20:58.59#ibcon#about to read 4, iclass 10, count 0 2006.183.08:20:58.59#ibcon#read 4, iclass 10, count 0 2006.183.08:20:58.59#ibcon#about to read 5, iclass 10, count 0 2006.183.08:20:58.59#ibcon#read 5, iclass 10, count 0 2006.183.08:20:58.59#ibcon#about to read 6, iclass 10, count 0 2006.183.08:20:58.59#ibcon#read 6, iclass 10, count 0 2006.183.08:20:58.59#ibcon#end of sib2, iclass 10, count 0 2006.183.08:20:58.59#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:20:58.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:20:58.59#ibcon#[25=USB\r\n] 2006.183.08:20:58.59#ibcon#*before write, iclass 10, count 0 2006.183.08:20:58.59#ibcon#enter sib2, iclass 10, count 0 2006.183.08:20:58.59#ibcon#flushed, iclass 10, count 0 2006.183.08:20:58.59#ibcon#about to write, iclass 10, count 0 2006.183.08:20:58.59#ibcon#wrote, iclass 10, count 0 2006.183.08:20:58.59#ibcon#about to read 3, iclass 10, count 0 2006.183.08:20:58.62#ibcon#read 3, iclass 10, count 0 2006.183.08:20:58.62#ibcon#about to read 4, iclass 10, count 0 2006.183.08:20:58.62#ibcon#read 4, iclass 10, count 0 2006.183.08:20:58.62#ibcon#about to read 5, iclass 10, count 0 2006.183.08:20:58.62#ibcon#read 5, iclass 10, count 0 2006.183.08:20:58.62#ibcon#about to read 6, iclass 10, count 0 2006.183.08:20:58.62#ibcon#read 6, iclass 10, count 0 2006.183.08:20:58.62#ibcon#end of sib2, iclass 10, count 0 2006.183.08:20:58.62#ibcon#*after write, iclass 10, count 0 2006.183.08:20:58.62#ibcon#*before return 0, iclass 10, count 0 2006.183.08:20:58.62#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:20:58.62#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:20:58.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:20:58.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:20:58.62$vc4f8/valo=3,672.99 2006.183.08:20:58.62#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.08:20:58.62#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.08:20:58.62#ibcon#ireg 17 cls_cnt 0 2006.183.08:20:58.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:20:58.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:20:58.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:20:58.62#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:20:58.62#ibcon#first serial, iclass 12, count 0 2006.183.08:20:58.62#ibcon#enter sib2, iclass 12, count 0 2006.183.08:20:58.62#ibcon#flushed, iclass 12, count 0 2006.183.08:20:58.62#ibcon#about to write, iclass 12, count 0 2006.183.08:20:58.62#ibcon#wrote, iclass 12, count 0 2006.183.08:20:58.62#ibcon#about to read 3, iclass 12, count 0 2006.183.08:20:58.65#ibcon#read 3, iclass 12, count 0 2006.183.08:20:58.65#ibcon#about to read 4, iclass 12, count 0 2006.183.08:20:58.65#ibcon#read 4, iclass 12, count 0 2006.183.08:20:58.65#ibcon#about to read 5, iclass 12, count 0 2006.183.08:20:58.65#ibcon#read 5, iclass 12, count 0 2006.183.08:20:58.65#ibcon#about to read 6, iclass 12, count 0 2006.183.08:20:58.65#ibcon#read 6, iclass 12, count 0 2006.183.08:20:58.65#ibcon#end of sib2, iclass 12, count 0 2006.183.08:20:58.65#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:20:58.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:20:58.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:20:58.65#ibcon#*before write, iclass 12, count 0 2006.183.08:20:58.65#ibcon#enter sib2, iclass 12, count 0 2006.183.08:20:58.65#ibcon#flushed, iclass 12, count 0 2006.183.08:20:58.65#ibcon#about to write, iclass 12, count 0 2006.183.08:20:58.65#ibcon#wrote, iclass 12, count 0 2006.183.08:20:58.65#ibcon#about to read 3, iclass 12, count 0 2006.183.08:20:58.69#ibcon#read 3, iclass 12, count 0 2006.183.08:20:58.69#ibcon#about to read 4, iclass 12, count 0 2006.183.08:20:58.69#ibcon#read 4, iclass 12, count 0 2006.183.08:20:58.69#ibcon#about to read 5, iclass 12, count 0 2006.183.08:20:58.69#ibcon#read 5, iclass 12, count 0 2006.183.08:20:58.69#ibcon#about to read 6, iclass 12, count 0 2006.183.08:20:58.69#ibcon#read 6, iclass 12, count 0 2006.183.08:20:58.69#ibcon#end of sib2, iclass 12, count 0 2006.183.08:20:58.69#ibcon#*after write, iclass 12, count 0 2006.183.08:20:58.69#ibcon#*before return 0, iclass 12, count 0 2006.183.08:20:58.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:20:58.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:20:58.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:20:58.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:20:58.69$vc4f8/va=3,6 2006.183.08:20:58.69#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.08:20:58.69#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.08:20:58.69#ibcon#ireg 11 cls_cnt 2 2006.183.08:20:58.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:20:58.74#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:20:58.74#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:20:58.74#ibcon#enter wrdev, iclass 14, count 2 2006.183.08:20:58.74#ibcon#first serial, iclass 14, count 2 2006.183.08:20:58.74#ibcon#enter sib2, iclass 14, count 2 2006.183.08:20:58.74#ibcon#flushed, iclass 14, count 2 2006.183.08:20:58.74#ibcon#about to write, iclass 14, count 2 2006.183.08:20:58.74#ibcon#wrote, iclass 14, count 2 2006.183.08:20:58.74#ibcon#about to read 3, iclass 14, count 2 2006.183.08:20:58.76#ibcon#read 3, iclass 14, count 2 2006.183.08:20:58.76#ibcon#about to read 4, iclass 14, count 2 2006.183.08:20:58.76#ibcon#read 4, iclass 14, count 2 2006.183.08:20:58.76#ibcon#about to read 5, iclass 14, count 2 2006.183.08:20:58.76#ibcon#read 5, iclass 14, count 2 2006.183.08:20:58.76#ibcon#about to read 6, iclass 14, count 2 2006.183.08:20:58.76#ibcon#read 6, iclass 14, count 2 2006.183.08:20:58.76#ibcon#end of sib2, iclass 14, count 2 2006.183.08:20:58.76#ibcon#*mode == 0, iclass 14, count 2 2006.183.08:20:58.76#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.08:20:58.76#ibcon#[25=AT03-06\r\n] 2006.183.08:20:58.76#ibcon#*before write, iclass 14, count 2 2006.183.08:20:58.76#ibcon#enter sib2, iclass 14, count 2 2006.183.08:20:58.76#ibcon#flushed, iclass 14, count 2 2006.183.08:20:58.76#ibcon#about to write, iclass 14, count 2 2006.183.08:20:58.76#ibcon#wrote, iclass 14, count 2 2006.183.08:20:58.76#ibcon#about to read 3, iclass 14, count 2 2006.183.08:20:58.79#ibcon#read 3, iclass 14, count 2 2006.183.08:20:58.79#ibcon#about to read 4, iclass 14, count 2 2006.183.08:20:58.79#ibcon#read 4, iclass 14, count 2 2006.183.08:20:58.79#ibcon#about to read 5, iclass 14, count 2 2006.183.08:20:58.79#ibcon#read 5, iclass 14, count 2 2006.183.08:20:58.79#ibcon#about to read 6, iclass 14, count 2 2006.183.08:20:58.79#ibcon#read 6, iclass 14, count 2 2006.183.08:20:58.79#ibcon#end of sib2, iclass 14, count 2 2006.183.08:20:58.79#ibcon#*after write, iclass 14, count 2 2006.183.08:20:58.79#ibcon#*before return 0, iclass 14, count 2 2006.183.08:20:58.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:20:58.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:20:58.79#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.08:20:58.79#ibcon#ireg 7 cls_cnt 0 2006.183.08:20:58.79#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:20:58.83#abcon#<5=/10 1.6 5.0 28.30 86 996.6\r\n> 2006.183.08:20:58.86#abcon#{5=INTERFACE CLEAR} 2006.183.08:20:58.91#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:20:58.91#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:20:58.91#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:20:58.91#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:20:58.91#ibcon#first serial, iclass 14, count 0 2006.183.08:20:58.91#ibcon#enter sib2, iclass 14, count 0 2006.183.08:20:58.91#ibcon#flushed, iclass 14, count 0 2006.183.08:20:58.91#ibcon#about to write, iclass 14, count 0 2006.183.08:20:58.91#ibcon#wrote, iclass 14, count 0 2006.183.08:20:58.91#ibcon#about to read 3, iclass 14, count 0 2006.183.08:20:58.94#ibcon#read 3, iclass 14, count 0 2006.183.08:20:58.94#ibcon#about to read 4, iclass 14, count 0 2006.183.08:20:58.95#ibcon#read 4, iclass 14, count 0 2006.183.08:20:58.95#ibcon#about to read 5, iclass 14, count 0 2006.183.08:20:58.95#ibcon#read 5, iclass 14, count 0 2006.183.08:20:58.95#ibcon#about to read 6, iclass 14, count 0 2006.183.08:20:58.95#ibcon#read 6, iclass 14, count 0 2006.183.08:20:58.95#ibcon#end of sib2, iclass 14, count 0 2006.183.08:20:58.95#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:20:58.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:20:58.95#ibcon#[25=USB\r\n] 2006.183.08:20:58.95#ibcon#*before write, iclass 14, count 0 2006.183.08:20:58.95#ibcon#enter sib2, iclass 14, count 0 2006.183.08:20:58.95#ibcon#flushed, iclass 14, count 0 2006.183.08:20:58.95#ibcon#about to write, iclass 14, count 0 2006.183.08:20:58.95#ibcon#wrote, iclass 14, count 0 2006.183.08:20:58.95#ibcon#about to read 3, iclass 14, count 0 2006.183.08:20:58.97#ibcon#read 3, iclass 14, count 0 2006.183.08:20:58.97#ibcon#about to read 4, iclass 14, count 0 2006.183.08:20:58.97#ibcon#read 4, iclass 14, count 0 2006.183.08:20:58.97#ibcon#about to read 5, iclass 14, count 0 2006.183.08:20:58.97#ibcon#read 5, iclass 14, count 0 2006.183.08:20:58.97#ibcon#about to read 6, iclass 14, count 0 2006.183.08:20:58.97#ibcon#read 6, iclass 14, count 0 2006.183.08:20:58.97#ibcon#end of sib2, iclass 14, count 0 2006.183.08:20:58.97#ibcon#*after write, iclass 14, count 0 2006.183.08:20:58.97#ibcon#*before return 0, iclass 14, count 0 2006.183.08:20:58.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:20:58.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:20:58.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:20:58.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:20:58.97$vc4f8/valo=4,832.99 2006.183.08:20:58.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.08:20:58.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.08:20:58.97#ibcon#ireg 17 cls_cnt 0 2006.183.08:20:58.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:20:58.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:20:58.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:20:58.97#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:20:58.97#ibcon#first serial, iclass 20, count 0 2006.183.08:20:58.97#ibcon#enter sib2, iclass 20, count 0 2006.183.08:20:58.97#ibcon#flushed, iclass 20, count 0 2006.183.08:20:58.97#ibcon#about to write, iclass 20, count 0 2006.183.08:20:58.97#ibcon#wrote, iclass 20, count 0 2006.183.08:20:58.97#ibcon#about to read 3, iclass 20, count 0 2006.183.08:20:58.99#ibcon#read 3, iclass 20, count 0 2006.183.08:20:58.99#ibcon#about to read 4, iclass 20, count 0 2006.183.08:20:58.99#ibcon#read 4, iclass 20, count 0 2006.183.08:20:58.99#ibcon#about to read 5, iclass 20, count 0 2006.183.08:20:58.99#ibcon#read 5, iclass 20, count 0 2006.183.08:20:58.99#ibcon#about to read 6, iclass 20, count 0 2006.183.08:20:58.99#ibcon#read 6, iclass 20, count 0 2006.183.08:20:58.99#ibcon#end of sib2, iclass 20, count 0 2006.183.08:20:58.99#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:20:58.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:20:58.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:20:58.99#ibcon#*before write, iclass 20, count 0 2006.183.08:20:58.99#ibcon#enter sib2, iclass 20, count 0 2006.183.08:20:58.99#ibcon#flushed, iclass 20, count 0 2006.183.08:20:58.99#ibcon#about to write, iclass 20, count 0 2006.183.08:20:58.99#ibcon#wrote, iclass 20, count 0 2006.183.08:20:58.99#ibcon#about to read 3, iclass 20, count 0 2006.183.08:20:59.03#ibcon#read 3, iclass 20, count 0 2006.183.08:20:59.03#ibcon#about to read 4, iclass 20, count 0 2006.183.08:20:59.03#ibcon#read 4, iclass 20, count 0 2006.183.08:20:59.03#ibcon#about to read 5, iclass 20, count 0 2006.183.08:20:59.03#ibcon#read 5, iclass 20, count 0 2006.183.08:20:59.03#ibcon#about to read 6, iclass 20, count 0 2006.183.08:20:59.03#ibcon#read 6, iclass 20, count 0 2006.183.08:20:59.03#ibcon#end of sib2, iclass 20, count 0 2006.183.08:20:59.03#ibcon#*after write, iclass 20, count 0 2006.183.08:20:59.03#ibcon#*before return 0, iclass 20, count 0 2006.183.08:20:59.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:20:59.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:20:59.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:20:59.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:20:59.03$vc4f8/va=4,7 2006.183.08:20:59.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.08:20:59.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.08:20:59.03#ibcon#ireg 11 cls_cnt 2 2006.183.08:20:59.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:20:59.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:20:59.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:20:59.09#ibcon#enter wrdev, iclass 22, count 2 2006.183.08:20:59.09#ibcon#first serial, iclass 22, count 2 2006.183.08:20:59.09#ibcon#enter sib2, iclass 22, count 2 2006.183.08:20:59.09#ibcon#flushed, iclass 22, count 2 2006.183.08:20:59.09#ibcon#about to write, iclass 22, count 2 2006.183.08:20:59.09#ibcon#wrote, iclass 22, count 2 2006.183.08:20:59.09#ibcon#about to read 3, iclass 22, count 2 2006.183.08:20:59.11#ibcon#read 3, iclass 22, count 2 2006.183.08:20:59.11#ibcon#about to read 4, iclass 22, count 2 2006.183.08:20:59.11#ibcon#read 4, iclass 22, count 2 2006.183.08:20:59.11#ibcon#about to read 5, iclass 22, count 2 2006.183.08:20:59.11#ibcon#read 5, iclass 22, count 2 2006.183.08:20:59.11#ibcon#about to read 6, iclass 22, count 2 2006.183.08:20:59.11#ibcon#read 6, iclass 22, count 2 2006.183.08:20:59.11#ibcon#end of sib2, iclass 22, count 2 2006.183.08:20:59.11#ibcon#*mode == 0, iclass 22, count 2 2006.183.08:20:59.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.08:20:59.11#ibcon#[25=AT04-07\r\n] 2006.183.08:20:59.11#ibcon#*before write, iclass 22, count 2 2006.183.08:20:59.11#ibcon#enter sib2, iclass 22, count 2 2006.183.08:20:59.11#ibcon#flushed, iclass 22, count 2 2006.183.08:20:59.11#ibcon#about to write, iclass 22, count 2 2006.183.08:20:59.11#ibcon#wrote, iclass 22, count 2 2006.183.08:20:59.11#ibcon#about to read 3, iclass 22, count 2 2006.183.08:20:59.14#ibcon#read 3, iclass 22, count 2 2006.183.08:20:59.14#ibcon#about to read 4, iclass 22, count 2 2006.183.08:20:59.14#ibcon#read 4, iclass 22, count 2 2006.183.08:20:59.14#ibcon#about to read 5, iclass 22, count 2 2006.183.08:20:59.14#ibcon#read 5, iclass 22, count 2 2006.183.08:20:59.14#ibcon#about to read 6, iclass 22, count 2 2006.183.08:20:59.14#ibcon#read 6, iclass 22, count 2 2006.183.08:20:59.14#ibcon#end of sib2, iclass 22, count 2 2006.183.08:20:59.14#ibcon#*after write, iclass 22, count 2 2006.183.08:20:59.14#ibcon#*before return 0, iclass 22, count 2 2006.183.08:20:59.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:20:59.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:20:59.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.08:20:59.14#ibcon#ireg 7 cls_cnt 0 2006.183.08:20:59.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:20:59.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:20:59.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:20:59.26#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:20:59.26#ibcon#first serial, iclass 22, count 0 2006.183.08:20:59.26#ibcon#enter sib2, iclass 22, count 0 2006.183.08:20:59.26#ibcon#flushed, iclass 22, count 0 2006.183.08:20:59.26#ibcon#about to write, iclass 22, count 0 2006.183.08:20:59.26#ibcon#wrote, iclass 22, count 0 2006.183.08:20:59.26#ibcon#about to read 3, iclass 22, count 0 2006.183.08:20:59.28#ibcon#read 3, iclass 22, count 0 2006.183.08:20:59.28#ibcon#about to read 4, iclass 22, count 0 2006.183.08:20:59.28#ibcon#read 4, iclass 22, count 0 2006.183.08:20:59.28#ibcon#about to read 5, iclass 22, count 0 2006.183.08:20:59.28#ibcon#read 5, iclass 22, count 0 2006.183.08:20:59.28#ibcon#about to read 6, iclass 22, count 0 2006.183.08:20:59.28#ibcon#read 6, iclass 22, count 0 2006.183.08:20:59.28#ibcon#end of sib2, iclass 22, count 0 2006.183.08:20:59.28#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:20:59.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:20:59.28#ibcon#[25=USB\r\n] 2006.183.08:20:59.28#ibcon#*before write, iclass 22, count 0 2006.183.08:20:59.28#ibcon#enter sib2, iclass 22, count 0 2006.183.08:20:59.28#ibcon#flushed, iclass 22, count 0 2006.183.08:20:59.28#ibcon#about to write, iclass 22, count 0 2006.183.08:20:59.28#ibcon#wrote, iclass 22, count 0 2006.183.08:20:59.28#ibcon#about to read 3, iclass 22, count 0 2006.183.08:20:59.31#ibcon#read 3, iclass 22, count 0 2006.183.08:20:59.31#ibcon#about to read 4, iclass 22, count 0 2006.183.08:20:59.31#ibcon#read 4, iclass 22, count 0 2006.183.08:20:59.31#ibcon#about to read 5, iclass 22, count 0 2006.183.08:20:59.31#ibcon#read 5, iclass 22, count 0 2006.183.08:20:59.31#ibcon#about to read 6, iclass 22, count 0 2006.183.08:20:59.31#ibcon#read 6, iclass 22, count 0 2006.183.08:20:59.31#ibcon#end of sib2, iclass 22, count 0 2006.183.08:20:59.31#ibcon#*after write, iclass 22, count 0 2006.183.08:20:59.31#ibcon#*before return 0, iclass 22, count 0 2006.183.08:20:59.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:20:59.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:20:59.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:20:59.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:20:59.31$vc4f8/valo=5,652.99 2006.183.08:20:59.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.08:20:59.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.08:20:59.31#ibcon#ireg 17 cls_cnt 0 2006.183.08:20:59.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:20:59.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:20:59.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:20:59.31#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:20:59.31#ibcon#first serial, iclass 24, count 0 2006.183.08:20:59.31#ibcon#enter sib2, iclass 24, count 0 2006.183.08:20:59.31#ibcon#flushed, iclass 24, count 0 2006.183.08:20:59.31#ibcon#about to write, iclass 24, count 0 2006.183.08:20:59.31#ibcon#wrote, iclass 24, count 0 2006.183.08:20:59.31#ibcon#about to read 3, iclass 24, count 0 2006.183.08:20:59.33#ibcon#read 3, iclass 24, count 0 2006.183.08:20:59.33#ibcon#about to read 4, iclass 24, count 0 2006.183.08:20:59.33#ibcon#read 4, iclass 24, count 0 2006.183.08:20:59.33#ibcon#about to read 5, iclass 24, count 0 2006.183.08:20:59.33#ibcon#read 5, iclass 24, count 0 2006.183.08:20:59.33#ibcon#about to read 6, iclass 24, count 0 2006.183.08:20:59.33#ibcon#read 6, iclass 24, count 0 2006.183.08:20:59.33#ibcon#end of sib2, iclass 24, count 0 2006.183.08:20:59.33#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:20:59.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:20:59.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:20:59.33#ibcon#*before write, iclass 24, count 0 2006.183.08:20:59.33#ibcon#enter sib2, iclass 24, count 0 2006.183.08:20:59.33#ibcon#flushed, iclass 24, count 0 2006.183.08:20:59.33#ibcon#about to write, iclass 24, count 0 2006.183.08:20:59.33#ibcon#wrote, iclass 24, count 0 2006.183.08:20:59.33#ibcon#about to read 3, iclass 24, count 0 2006.183.08:20:59.37#ibcon#read 3, iclass 24, count 0 2006.183.08:20:59.37#ibcon#about to read 4, iclass 24, count 0 2006.183.08:20:59.37#ibcon#read 4, iclass 24, count 0 2006.183.08:20:59.37#ibcon#about to read 5, iclass 24, count 0 2006.183.08:20:59.37#ibcon#read 5, iclass 24, count 0 2006.183.08:20:59.37#ibcon#about to read 6, iclass 24, count 0 2006.183.08:20:59.37#ibcon#read 6, iclass 24, count 0 2006.183.08:20:59.37#ibcon#end of sib2, iclass 24, count 0 2006.183.08:20:59.37#ibcon#*after write, iclass 24, count 0 2006.183.08:20:59.37#ibcon#*before return 0, iclass 24, count 0 2006.183.08:20:59.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:20:59.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:20:59.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:20:59.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:20:59.37$vc4f8/va=5,7 2006.183.08:20:59.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.08:20:59.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.08:20:59.37#ibcon#ireg 11 cls_cnt 2 2006.183.08:20:59.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:20:59.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:20:59.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:20:59.43#ibcon#enter wrdev, iclass 26, count 2 2006.183.08:20:59.43#ibcon#first serial, iclass 26, count 2 2006.183.08:20:59.43#ibcon#enter sib2, iclass 26, count 2 2006.183.08:20:59.43#ibcon#flushed, iclass 26, count 2 2006.183.08:20:59.43#ibcon#about to write, iclass 26, count 2 2006.183.08:20:59.43#ibcon#wrote, iclass 26, count 2 2006.183.08:20:59.43#ibcon#about to read 3, iclass 26, count 2 2006.183.08:20:59.45#ibcon#read 3, iclass 26, count 2 2006.183.08:20:59.45#ibcon#about to read 4, iclass 26, count 2 2006.183.08:20:59.45#ibcon#read 4, iclass 26, count 2 2006.183.08:20:59.45#ibcon#about to read 5, iclass 26, count 2 2006.183.08:20:59.45#ibcon#read 5, iclass 26, count 2 2006.183.08:20:59.45#ibcon#about to read 6, iclass 26, count 2 2006.183.08:20:59.45#ibcon#read 6, iclass 26, count 2 2006.183.08:20:59.45#ibcon#end of sib2, iclass 26, count 2 2006.183.08:20:59.45#ibcon#*mode == 0, iclass 26, count 2 2006.183.08:20:59.45#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.08:20:59.45#ibcon#[25=AT05-07\r\n] 2006.183.08:20:59.45#ibcon#*before write, iclass 26, count 2 2006.183.08:20:59.45#ibcon#enter sib2, iclass 26, count 2 2006.183.08:20:59.45#ibcon#flushed, iclass 26, count 2 2006.183.08:20:59.45#ibcon#about to write, iclass 26, count 2 2006.183.08:20:59.45#ibcon#wrote, iclass 26, count 2 2006.183.08:20:59.45#ibcon#about to read 3, iclass 26, count 2 2006.183.08:20:59.48#ibcon#read 3, iclass 26, count 2 2006.183.08:20:59.48#ibcon#about to read 4, iclass 26, count 2 2006.183.08:20:59.48#ibcon#read 4, iclass 26, count 2 2006.183.08:20:59.48#ibcon#about to read 5, iclass 26, count 2 2006.183.08:20:59.48#ibcon#read 5, iclass 26, count 2 2006.183.08:20:59.48#ibcon#about to read 6, iclass 26, count 2 2006.183.08:20:59.48#ibcon#read 6, iclass 26, count 2 2006.183.08:20:59.48#ibcon#end of sib2, iclass 26, count 2 2006.183.08:20:59.48#ibcon#*after write, iclass 26, count 2 2006.183.08:20:59.48#ibcon#*before return 0, iclass 26, count 2 2006.183.08:20:59.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:20:59.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:20:59.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.08:20:59.48#ibcon#ireg 7 cls_cnt 0 2006.183.08:20:59.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:20:59.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:20:59.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:20:59.60#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:20:59.60#ibcon#first serial, iclass 26, count 0 2006.183.08:20:59.60#ibcon#enter sib2, iclass 26, count 0 2006.183.08:20:59.60#ibcon#flushed, iclass 26, count 0 2006.183.08:20:59.60#ibcon#about to write, iclass 26, count 0 2006.183.08:20:59.60#ibcon#wrote, iclass 26, count 0 2006.183.08:20:59.60#ibcon#about to read 3, iclass 26, count 0 2006.183.08:20:59.62#ibcon#read 3, iclass 26, count 0 2006.183.08:20:59.62#ibcon#about to read 4, iclass 26, count 0 2006.183.08:20:59.62#ibcon#read 4, iclass 26, count 0 2006.183.08:20:59.62#ibcon#about to read 5, iclass 26, count 0 2006.183.08:20:59.62#ibcon#read 5, iclass 26, count 0 2006.183.08:20:59.62#ibcon#about to read 6, iclass 26, count 0 2006.183.08:20:59.62#ibcon#read 6, iclass 26, count 0 2006.183.08:20:59.62#ibcon#end of sib2, iclass 26, count 0 2006.183.08:20:59.62#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:20:59.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:20:59.62#ibcon#[25=USB\r\n] 2006.183.08:20:59.62#ibcon#*before write, iclass 26, count 0 2006.183.08:20:59.62#ibcon#enter sib2, iclass 26, count 0 2006.183.08:20:59.62#ibcon#flushed, iclass 26, count 0 2006.183.08:20:59.62#ibcon#about to write, iclass 26, count 0 2006.183.08:20:59.62#ibcon#wrote, iclass 26, count 0 2006.183.08:20:59.62#ibcon#about to read 3, iclass 26, count 0 2006.183.08:20:59.65#ibcon#read 3, iclass 26, count 0 2006.183.08:20:59.65#ibcon#about to read 4, iclass 26, count 0 2006.183.08:20:59.65#ibcon#read 4, iclass 26, count 0 2006.183.08:20:59.65#ibcon#about to read 5, iclass 26, count 0 2006.183.08:20:59.65#ibcon#read 5, iclass 26, count 0 2006.183.08:20:59.65#ibcon#about to read 6, iclass 26, count 0 2006.183.08:20:59.65#ibcon#read 6, iclass 26, count 0 2006.183.08:20:59.65#ibcon#end of sib2, iclass 26, count 0 2006.183.08:20:59.65#ibcon#*after write, iclass 26, count 0 2006.183.08:20:59.65#ibcon#*before return 0, iclass 26, count 0 2006.183.08:20:59.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:20:59.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:20:59.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:20:59.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:20:59.65$vc4f8/valo=6,772.99 2006.183.08:20:59.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:20:59.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:20:59.65#ibcon#ireg 17 cls_cnt 0 2006.183.08:20:59.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:20:59.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:20:59.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:20:59.65#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:20:59.65#ibcon#first serial, iclass 28, count 0 2006.183.08:20:59.65#ibcon#enter sib2, iclass 28, count 0 2006.183.08:20:59.65#ibcon#flushed, iclass 28, count 0 2006.183.08:20:59.65#ibcon#about to write, iclass 28, count 0 2006.183.08:20:59.65#ibcon#wrote, iclass 28, count 0 2006.183.08:20:59.65#ibcon#about to read 3, iclass 28, count 0 2006.183.08:20:59.67#ibcon#read 3, iclass 28, count 0 2006.183.08:20:59.67#ibcon#about to read 4, iclass 28, count 0 2006.183.08:20:59.67#ibcon#read 4, iclass 28, count 0 2006.183.08:20:59.67#ibcon#about to read 5, iclass 28, count 0 2006.183.08:20:59.67#ibcon#read 5, iclass 28, count 0 2006.183.08:20:59.67#ibcon#about to read 6, iclass 28, count 0 2006.183.08:20:59.67#ibcon#read 6, iclass 28, count 0 2006.183.08:20:59.67#ibcon#end of sib2, iclass 28, count 0 2006.183.08:20:59.67#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:20:59.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:20:59.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:20:59.67#ibcon#*before write, iclass 28, count 0 2006.183.08:20:59.67#ibcon#enter sib2, iclass 28, count 0 2006.183.08:20:59.67#ibcon#flushed, iclass 28, count 0 2006.183.08:20:59.67#ibcon#about to write, iclass 28, count 0 2006.183.08:20:59.67#ibcon#wrote, iclass 28, count 0 2006.183.08:20:59.67#ibcon#about to read 3, iclass 28, count 0 2006.183.08:20:59.71#ibcon#read 3, iclass 28, count 0 2006.183.08:20:59.71#ibcon#about to read 4, iclass 28, count 0 2006.183.08:20:59.71#ibcon#read 4, iclass 28, count 0 2006.183.08:20:59.71#ibcon#about to read 5, iclass 28, count 0 2006.183.08:20:59.71#ibcon#read 5, iclass 28, count 0 2006.183.08:20:59.71#ibcon#about to read 6, iclass 28, count 0 2006.183.08:20:59.71#ibcon#read 6, iclass 28, count 0 2006.183.08:20:59.71#ibcon#end of sib2, iclass 28, count 0 2006.183.08:20:59.71#ibcon#*after write, iclass 28, count 0 2006.183.08:20:59.71#ibcon#*before return 0, iclass 28, count 0 2006.183.08:20:59.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:20:59.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:20:59.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:20:59.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:20:59.71$vc4f8/va=6,6 2006.183.08:20:59.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.183.08:20:59.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.183.08:20:59.71#ibcon#ireg 11 cls_cnt 2 2006.183.08:20:59.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:20:59.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:20:59.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:20:59.77#ibcon#enter wrdev, iclass 30, count 2 2006.183.08:20:59.77#ibcon#first serial, iclass 30, count 2 2006.183.08:20:59.77#ibcon#enter sib2, iclass 30, count 2 2006.183.08:20:59.77#ibcon#flushed, iclass 30, count 2 2006.183.08:20:59.77#ibcon#about to write, iclass 30, count 2 2006.183.08:20:59.77#ibcon#wrote, iclass 30, count 2 2006.183.08:20:59.77#ibcon#about to read 3, iclass 30, count 2 2006.183.08:20:59.79#ibcon#read 3, iclass 30, count 2 2006.183.08:20:59.79#ibcon#about to read 4, iclass 30, count 2 2006.183.08:20:59.79#ibcon#read 4, iclass 30, count 2 2006.183.08:20:59.79#ibcon#about to read 5, iclass 30, count 2 2006.183.08:20:59.79#ibcon#read 5, iclass 30, count 2 2006.183.08:20:59.79#ibcon#about to read 6, iclass 30, count 2 2006.183.08:20:59.79#ibcon#read 6, iclass 30, count 2 2006.183.08:20:59.79#ibcon#end of sib2, iclass 30, count 2 2006.183.08:20:59.79#ibcon#*mode == 0, iclass 30, count 2 2006.183.08:20:59.79#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.183.08:20:59.79#ibcon#[25=AT06-06\r\n] 2006.183.08:20:59.79#ibcon#*before write, iclass 30, count 2 2006.183.08:20:59.79#ibcon#enter sib2, iclass 30, count 2 2006.183.08:20:59.79#ibcon#flushed, iclass 30, count 2 2006.183.08:20:59.79#ibcon#about to write, iclass 30, count 2 2006.183.08:20:59.79#ibcon#wrote, iclass 30, count 2 2006.183.08:20:59.79#ibcon#about to read 3, iclass 30, count 2 2006.183.08:20:59.82#ibcon#read 3, iclass 30, count 2 2006.183.08:20:59.82#ibcon#about to read 4, iclass 30, count 2 2006.183.08:20:59.82#ibcon#read 4, iclass 30, count 2 2006.183.08:20:59.82#ibcon#about to read 5, iclass 30, count 2 2006.183.08:20:59.82#ibcon#read 5, iclass 30, count 2 2006.183.08:20:59.82#ibcon#about to read 6, iclass 30, count 2 2006.183.08:20:59.82#ibcon#read 6, iclass 30, count 2 2006.183.08:20:59.82#ibcon#end of sib2, iclass 30, count 2 2006.183.08:20:59.82#ibcon#*after write, iclass 30, count 2 2006.183.08:20:59.82#ibcon#*before return 0, iclass 30, count 2 2006.183.08:20:59.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:20:59.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.183.08:20:59.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.183.08:20:59.82#ibcon#ireg 7 cls_cnt 0 2006.183.08:20:59.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:20:59.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:20:59.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:20:59.94#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:20:59.94#ibcon#first serial, iclass 30, count 0 2006.183.08:20:59.94#ibcon#enter sib2, iclass 30, count 0 2006.183.08:20:59.94#ibcon#flushed, iclass 30, count 0 2006.183.08:20:59.94#ibcon#about to write, iclass 30, count 0 2006.183.08:20:59.94#ibcon#wrote, iclass 30, count 0 2006.183.08:20:59.94#ibcon#about to read 3, iclass 30, count 0 2006.183.08:20:59.96#ibcon#read 3, iclass 30, count 0 2006.183.08:20:59.96#ibcon#about to read 4, iclass 30, count 0 2006.183.08:20:59.96#ibcon#read 4, iclass 30, count 0 2006.183.08:20:59.96#ibcon#about to read 5, iclass 30, count 0 2006.183.08:20:59.96#ibcon#read 5, iclass 30, count 0 2006.183.08:20:59.96#ibcon#about to read 6, iclass 30, count 0 2006.183.08:20:59.96#ibcon#read 6, iclass 30, count 0 2006.183.08:20:59.96#ibcon#end of sib2, iclass 30, count 0 2006.183.08:20:59.96#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:20:59.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:20:59.96#ibcon#[25=USB\r\n] 2006.183.08:20:59.96#ibcon#*before write, iclass 30, count 0 2006.183.08:20:59.96#ibcon#enter sib2, iclass 30, count 0 2006.183.08:20:59.96#ibcon#flushed, iclass 30, count 0 2006.183.08:20:59.96#ibcon#about to write, iclass 30, count 0 2006.183.08:20:59.96#ibcon#wrote, iclass 30, count 0 2006.183.08:20:59.96#ibcon#about to read 3, iclass 30, count 0 2006.183.08:20:59.99#ibcon#read 3, iclass 30, count 0 2006.183.08:20:59.99#ibcon#about to read 4, iclass 30, count 0 2006.183.08:20:59.99#ibcon#read 4, iclass 30, count 0 2006.183.08:20:59.99#ibcon#about to read 5, iclass 30, count 0 2006.183.08:20:59.99#ibcon#read 5, iclass 30, count 0 2006.183.08:20:59.99#ibcon#about to read 6, iclass 30, count 0 2006.183.08:20:59.99#ibcon#read 6, iclass 30, count 0 2006.183.08:20:59.99#ibcon#end of sib2, iclass 30, count 0 2006.183.08:20:59.99#ibcon#*after write, iclass 30, count 0 2006.183.08:20:59.99#ibcon#*before return 0, iclass 30, count 0 2006.183.08:20:59.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:20:59.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.183.08:20:59.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:20:59.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:20:59.99$vc4f8/valo=7,832.99 2006.183.08:20:59.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.08:20:59.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.08:20:59.99#ibcon#ireg 17 cls_cnt 0 2006.183.08:20:59.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:20:59.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:20:59.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:20:59.99#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:20:59.99#ibcon#first serial, iclass 32, count 0 2006.183.08:20:59.99#ibcon#enter sib2, iclass 32, count 0 2006.183.08:20:59.99#ibcon#flushed, iclass 32, count 0 2006.183.08:20:59.99#ibcon#about to write, iclass 32, count 0 2006.183.08:20:59.99#ibcon#wrote, iclass 32, count 0 2006.183.08:20:59.99#ibcon#about to read 3, iclass 32, count 0 2006.183.08:21:00.01#ibcon#read 3, iclass 32, count 0 2006.183.08:21:00.01#ibcon#about to read 4, iclass 32, count 0 2006.183.08:21:00.01#ibcon#read 4, iclass 32, count 0 2006.183.08:21:00.01#ibcon#about to read 5, iclass 32, count 0 2006.183.08:21:00.01#ibcon#read 5, iclass 32, count 0 2006.183.08:21:00.01#ibcon#about to read 6, iclass 32, count 0 2006.183.08:21:00.01#ibcon#read 6, iclass 32, count 0 2006.183.08:21:00.01#ibcon#end of sib2, iclass 32, count 0 2006.183.08:21:00.01#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:21:00.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:21:00.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:21:00.01#ibcon#*before write, iclass 32, count 0 2006.183.08:21:00.01#ibcon#enter sib2, iclass 32, count 0 2006.183.08:21:00.01#ibcon#flushed, iclass 32, count 0 2006.183.08:21:00.01#ibcon#about to write, iclass 32, count 0 2006.183.08:21:00.01#ibcon#wrote, iclass 32, count 0 2006.183.08:21:00.01#ibcon#about to read 3, iclass 32, count 0 2006.183.08:21:00.05#ibcon#read 3, iclass 32, count 0 2006.183.08:21:00.05#ibcon#about to read 4, iclass 32, count 0 2006.183.08:21:00.05#ibcon#read 4, iclass 32, count 0 2006.183.08:21:00.05#ibcon#about to read 5, iclass 32, count 0 2006.183.08:21:00.05#ibcon#read 5, iclass 32, count 0 2006.183.08:21:00.05#ibcon#about to read 6, iclass 32, count 0 2006.183.08:21:00.05#ibcon#read 6, iclass 32, count 0 2006.183.08:21:00.05#ibcon#end of sib2, iclass 32, count 0 2006.183.08:21:00.05#ibcon#*after write, iclass 32, count 0 2006.183.08:21:00.05#ibcon#*before return 0, iclass 32, count 0 2006.183.08:21:00.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:21:00.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:21:00.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:21:00.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:21:00.05$vc4f8/va=7,6 2006.183.08:21:00.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.183.08:21:00.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.183.08:21:00.05#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:00.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:21:00.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:21:00.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:21:00.11#ibcon#enter wrdev, iclass 34, count 2 2006.183.08:21:00.11#ibcon#first serial, iclass 34, count 2 2006.183.08:21:00.11#ibcon#enter sib2, iclass 34, count 2 2006.183.08:21:00.11#ibcon#flushed, iclass 34, count 2 2006.183.08:21:00.11#ibcon#about to write, iclass 34, count 2 2006.183.08:21:00.11#ibcon#wrote, iclass 34, count 2 2006.183.08:21:00.11#ibcon#about to read 3, iclass 34, count 2 2006.183.08:21:00.13#ibcon#read 3, iclass 34, count 2 2006.183.08:21:00.13#ibcon#about to read 4, iclass 34, count 2 2006.183.08:21:00.13#ibcon#read 4, iclass 34, count 2 2006.183.08:21:00.13#ibcon#about to read 5, iclass 34, count 2 2006.183.08:21:00.13#ibcon#read 5, iclass 34, count 2 2006.183.08:21:00.13#ibcon#about to read 6, iclass 34, count 2 2006.183.08:21:00.13#ibcon#read 6, iclass 34, count 2 2006.183.08:21:00.13#ibcon#end of sib2, iclass 34, count 2 2006.183.08:21:00.13#ibcon#*mode == 0, iclass 34, count 2 2006.183.08:21:00.13#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.183.08:21:00.13#ibcon#[25=AT07-06\r\n] 2006.183.08:21:00.13#ibcon#*before write, iclass 34, count 2 2006.183.08:21:00.13#ibcon#enter sib2, iclass 34, count 2 2006.183.08:21:00.13#ibcon#flushed, iclass 34, count 2 2006.183.08:21:00.13#ibcon#about to write, iclass 34, count 2 2006.183.08:21:00.13#ibcon#wrote, iclass 34, count 2 2006.183.08:21:00.13#ibcon#about to read 3, iclass 34, count 2 2006.183.08:21:00.16#ibcon#read 3, iclass 34, count 2 2006.183.08:21:00.16#ibcon#about to read 4, iclass 34, count 2 2006.183.08:21:00.16#ibcon#read 4, iclass 34, count 2 2006.183.08:21:00.16#ibcon#about to read 5, iclass 34, count 2 2006.183.08:21:00.16#ibcon#read 5, iclass 34, count 2 2006.183.08:21:00.16#ibcon#about to read 6, iclass 34, count 2 2006.183.08:21:00.16#ibcon#read 6, iclass 34, count 2 2006.183.08:21:00.16#ibcon#end of sib2, iclass 34, count 2 2006.183.08:21:00.16#ibcon#*after write, iclass 34, count 2 2006.183.08:21:00.16#ibcon#*before return 0, iclass 34, count 2 2006.183.08:21:00.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:21:00.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.183.08:21:00.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.183.08:21:00.16#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:00.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:21:00.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:21:00.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:21:00.28#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:21:00.28#ibcon#first serial, iclass 34, count 0 2006.183.08:21:00.28#ibcon#enter sib2, iclass 34, count 0 2006.183.08:21:00.28#ibcon#flushed, iclass 34, count 0 2006.183.08:21:00.28#ibcon#about to write, iclass 34, count 0 2006.183.08:21:00.28#ibcon#wrote, iclass 34, count 0 2006.183.08:21:00.28#ibcon#about to read 3, iclass 34, count 0 2006.183.08:21:00.30#ibcon#read 3, iclass 34, count 0 2006.183.08:21:00.30#ibcon#about to read 4, iclass 34, count 0 2006.183.08:21:00.30#ibcon#read 4, iclass 34, count 0 2006.183.08:21:00.30#ibcon#about to read 5, iclass 34, count 0 2006.183.08:21:00.30#ibcon#read 5, iclass 34, count 0 2006.183.08:21:00.30#ibcon#about to read 6, iclass 34, count 0 2006.183.08:21:00.30#ibcon#read 6, iclass 34, count 0 2006.183.08:21:00.30#ibcon#end of sib2, iclass 34, count 0 2006.183.08:21:00.30#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:21:00.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:21:00.30#ibcon#[25=USB\r\n] 2006.183.08:21:00.30#ibcon#*before write, iclass 34, count 0 2006.183.08:21:00.30#ibcon#enter sib2, iclass 34, count 0 2006.183.08:21:00.30#ibcon#flushed, iclass 34, count 0 2006.183.08:21:00.30#ibcon#about to write, iclass 34, count 0 2006.183.08:21:00.30#ibcon#wrote, iclass 34, count 0 2006.183.08:21:00.30#ibcon#about to read 3, iclass 34, count 0 2006.183.08:21:00.33#ibcon#read 3, iclass 34, count 0 2006.183.08:21:00.33#ibcon#about to read 4, iclass 34, count 0 2006.183.08:21:00.33#ibcon#read 4, iclass 34, count 0 2006.183.08:21:00.33#ibcon#about to read 5, iclass 34, count 0 2006.183.08:21:00.33#ibcon#read 5, iclass 34, count 0 2006.183.08:21:00.33#ibcon#about to read 6, iclass 34, count 0 2006.183.08:21:00.33#ibcon#read 6, iclass 34, count 0 2006.183.08:21:00.33#ibcon#end of sib2, iclass 34, count 0 2006.183.08:21:00.33#ibcon#*after write, iclass 34, count 0 2006.183.08:21:00.33#ibcon#*before return 0, iclass 34, count 0 2006.183.08:21:00.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:21:00.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.183.08:21:00.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:21:00.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:21:00.33$vc4f8/valo=8,852.99 2006.183.08:21:00.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.183.08:21:00.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.183.08:21:00.33#ibcon#ireg 17 cls_cnt 0 2006.183.08:21:00.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:21:00.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:21:00.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:21:00.33#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:21:00.33#ibcon#first serial, iclass 36, count 0 2006.183.08:21:00.33#ibcon#enter sib2, iclass 36, count 0 2006.183.08:21:00.33#ibcon#flushed, iclass 36, count 0 2006.183.08:21:00.33#ibcon#about to write, iclass 36, count 0 2006.183.08:21:00.33#ibcon#wrote, iclass 36, count 0 2006.183.08:21:00.33#ibcon#about to read 3, iclass 36, count 0 2006.183.08:21:00.35#ibcon#read 3, iclass 36, count 0 2006.183.08:21:00.35#ibcon#about to read 4, iclass 36, count 0 2006.183.08:21:00.35#ibcon#read 4, iclass 36, count 0 2006.183.08:21:00.35#ibcon#about to read 5, iclass 36, count 0 2006.183.08:21:00.35#ibcon#read 5, iclass 36, count 0 2006.183.08:21:00.35#ibcon#about to read 6, iclass 36, count 0 2006.183.08:21:00.35#ibcon#read 6, iclass 36, count 0 2006.183.08:21:00.35#ibcon#end of sib2, iclass 36, count 0 2006.183.08:21:00.35#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:21:00.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:21:00.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:21:00.35#ibcon#*before write, iclass 36, count 0 2006.183.08:21:00.35#ibcon#enter sib2, iclass 36, count 0 2006.183.08:21:00.35#ibcon#flushed, iclass 36, count 0 2006.183.08:21:00.35#ibcon#about to write, iclass 36, count 0 2006.183.08:21:00.35#ibcon#wrote, iclass 36, count 0 2006.183.08:21:00.35#ibcon#about to read 3, iclass 36, count 0 2006.183.08:21:00.39#ibcon#read 3, iclass 36, count 0 2006.183.08:21:00.39#ibcon#about to read 4, iclass 36, count 0 2006.183.08:21:00.39#ibcon#read 4, iclass 36, count 0 2006.183.08:21:00.39#ibcon#about to read 5, iclass 36, count 0 2006.183.08:21:00.39#ibcon#read 5, iclass 36, count 0 2006.183.08:21:00.39#ibcon#about to read 6, iclass 36, count 0 2006.183.08:21:00.39#ibcon#read 6, iclass 36, count 0 2006.183.08:21:00.39#ibcon#end of sib2, iclass 36, count 0 2006.183.08:21:00.39#ibcon#*after write, iclass 36, count 0 2006.183.08:21:00.39#ibcon#*before return 0, iclass 36, count 0 2006.183.08:21:00.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:21:00.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.183.08:21:00.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:21:00.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:21:00.39$vc4f8/va=8,7 2006.183.08:21:00.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.183.08:21:00.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.183.08:21:00.39#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:00.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:21:00.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:21:00.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:21:00.45#ibcon#enter wrdev, iclass 38, count 2 2006.183.08:21:00.45#ibcon#first serial, iclass 38, count 2 2006.183.08:21:00.45#ibcon#enter sib2, iclass 38, count 2 2006.183.08:21:00.45#ibcon#flushed, iclass 38, count 2 2006.183.08:21:00.45#ibcon#about to write, iclass 38, count 2 2006.183.08:21:00.45#ibcon#wrote, iclass 38, count 2 2006.183.08:21:00.45#ibcon#about to read 3, iclass 38, count 2 2006.183.08:21:00.47#ibcon#read 3, iclass 38, count 2 2006.183.08:21:00.47#ibcon#about to read 4, iclass 38, count 2 2006.183.08:21:00.47#ibcon#read 4, iclass 38, count 2 2006.183.08:21:00.47#ibcon#about to read 5, iclass 38, count 2 2006.183.08:21:00.47#ibcon#read 5, iclass 38, count 2 2006.183.08:21:00.47#ibcon#about to read 6, iclass 38, count 2 2006.183.08:21:00.47#ibcon#read 6, iclass 38, count 2 2006.183.08:21:00.47#ibcon#end of sib2, iclass 38, count 2 2006.183.08:21:00.47#ibcon#*mode == 0, iclass 38, count 2 2006.183.08:21:00.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.183.08:21:00.47#ibcon#[25=AT08-07\r\n] 2006.183.08:21:00.47#ibcon#*before write, iclass 38, count 2 2006.183.08:21:00.47#ibcon#enter sib2, iclass 38, count 2 2006.183.08:21:00.47#ibcon#flushed, iclass 38, count 2 2006.183.08:21:00.47#ibcon#about to write, iclass 38, count 2 2006.183.08:21:00.47#ibcon#wrote, iclass 38, count 2 2006.183.08:21:00.47#ibcon#about to read 3, iclass 38, count 2 2006.183.08:21:00.50#ibcon#read 3, iclass 38, count 2 2006.183.08:21:00.50#ibcon#about to read 4, iclass 38, count 2 2006.183.08:21:00.50#ibcon#read 4, iclass 38, count 2 2006.183.08:21:00.50#ibcon#about to read 5, iclass 38, count 2 2006.183.08:21:00.50#ibcon#read 5, iclass 38, count 2 2006.183.08:21:00.50#ibcon#about to read 6, iclass 38, count 2 2006.183.08:21:00.50#ibcon#read 6, iclass 38, count 2 2006.183.08:21:00.50#ibcon#end of sib2, iclass 38, count 2 2006.183.08:21:00.50#ibcon#*after write, iclass 38, count 2 2006.183.08:21:00.50#ibcon#*before return 0, iclass 38, count 2 2006.183.08:21:00.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:21:00.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.183.08:21:00.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.183.08:21:00.50#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:00.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:21:00.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:21:00.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:21:00.62#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:21:00.62#ibcon#first serial, iclass 38, count 0 2006.183.08:21:00.62#ibcon#enter sib2, iclass 38, count 0 2006.183.08:21:00.62#ibcon#flushed, iclass 38, count 0 2006.183.08:21:00.62#ibcon#about to write, iclass 38, count 0 2006.183.08:21:00.62#ibcon#wrote, iclass 38, count 0 2006.183.08:21:00.62#ibcon#about to read 3, iclass 38, count 0 2006.183.08:21:00.64#ibcon#read 3, iclass 38, count 0 2006.183.08:21:00.64#ibcon#about to read 4, iclass 38, count 0 2006.183.08:21:00.64#ibcon#read 4, iclass 38, count 0 2006.183.08:21:00.64#ibcon#about to read 5, iclass 38, count 0 2006.183.08:21:00.64#ibcon#read 5, iclass 38, count 0 2006.183.08:21:00.64#ibcon#about to read 6, iclass 38, count 0 2006.183.08:21:00.64#ibcon#read 6, iclass 38, count 0 2006.183.08:21:00.64#ibcon#end of sib2, iclass 38, count 0 2006.183.08:21:00.64#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:21:00.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:21:00.64#ibcon#[25=USB\r\n] 2006.183.08:21:00.64#ibcon#*before write, iclass 38, count 0 2006.183.08:21:00.64#ibcon#enter sib2, iclass 38, count 0 2006.183.08:21:00.64#ibcon#flushed, iclass 38, count 0 2006.183.08:21:00.64#ibcon#about to write, iclass 38, count 0 2006.183.08:21:00.64#ibcon#wrote, iclass 38, count 0 2006.183.08:21:00.64#ibcon#about to read 3, iclass 38, count 0 2006.183.08:21:00.67#ibcon#read 3, iclass 38, count 0 2006.183.08:21:00.67#ibcon#about to read 4, iclass 38, count 0 2006.183.08:21:00.67#ibcon#read 4, iclass 38, count 0 2006.183.08:21:00.67#ibcon#about to read 5, iclass 38, count 0 2006.183.08:21:00.67#ibcon#read 5, iclass 38, count 0 2006.183.08:21:00.67#ibcon#about to read 6, iclass 38, count 0 2006.183.08:21:00.67#ibcon#read 6, iclass 38, count 0 2006.183.08:21:00.67#ibcon#end of sib2, iclass 38, count 0 2006.183.08:21:00.67#ibcon#*after write, iclass 38, count 0 2006.183.08:21:00.67#ibcon#*before return 0, iclass 38, count 0 2006.183.08:21:00.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:21:00.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.183.08:21:00.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:21:00.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:21:00.67$vc4f8/vblo=1,632.99 2006.183.08:21:00.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.183.08:21:00.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.183.08:21:00.67#ibcon#ireg 17 cls_cnt 0 2006.183.08:21:00.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:21:00.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:21:00.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:21:00.67#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:21:00.67#ibcon#first serial, iclass 40, count 0 2006.183.08:21:00.67#ibcon#enter sib2, iclass 40, count 0 2006.183.08:21:00.67#ibcon#flushed, iclass 40, count 0 2006.183.08:21:00.67#ibcon#about to write, iclass 40, count 0 2006.183.08:21:00.67#ibcon#wrote, iclass 40, count 0 2006.183.08:21:00.67#ibcon#about to read 3, iclass 40, count 0 2006.183.08:21:00.70#ibcon#read 3, iclass 40, count 0 2006.183.08:21:00.70#ibcon#about to read 4, iclass 40, count 0 2006.183.08:21:00.70#ibcon#read 4, iclass 40, count 0 2006.183.08:21:00.70#ibcon#about to read 5, iclass 40, count 0 2006.183.08:21:00.70#ibcon#read 5, iclass 40, count 0 2006.183.08:21:00.70#ibcon#about to read 6, iclass 40, count 0 2006.183.08:21:00.70#ibcon#read 6, iclass 40, count 0 2006.183.08:21:00.70#ibcon#end of sib2, iclass 40, count 0 2006.183.08:21:00.70#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:21:00.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:21:00.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:21:00.70#ibcon#*before write, iclass 40, count 0 2006.183.08:21:00.70#ibcon#enter sib2, iclass 40, count 0 2006.183.08:21:00.70#ibcon#flushed, iclass 40, count 0 2006.183.08:21:00.70#ibcon#about to write, iclass 40, count 0 2006.183.08:21:00.70#ibcon#wrote, iclass 40, count 0 2006.183.08:21:00.70#ibcon#about to read 3, iclass 40, count 0 2006.183.08:21:00.74#ibcon#read 3, iclass 40, count 0 2006.183.08:21:00.74#ibcon#about to read 4, iclass 40, count 0 2006.183.08:21:00.74#ibcon#read 4, iclass 40, count 0 2006.183.08:21:00.74#ibcon#about to read 5, iclass 40, count 0 2006.183.08:21:00.74#ibcon#read 5, iclass 40, count 0 2006.183.08:21:00.74#ibcon#about to read 6, iclass 40, count 0 2006.183.08:21:00.74#ibcon#read 6, iclass 40, count 0 2006.183.08:21:00.74#ibcon#end of sib2, iclass 40, count 0 2006.183.08:21:00.74#ibcon#*after write, iclass 40, count 0 2006.183.08:21:00.74#ibcon#*before return 0, iclass 40, count 0 2006.183.08:21:00.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:21:00.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.183.08:21:00.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:21:00.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:21:00.74$vc4f8/vb=1,4 2006.183.08:21:00.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.183.08:21:00.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.183.08:21:00.74#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:00.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:21:00.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:21:00.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:21:00.74#ibcon#enter wrdev, iclass 4, count 2 2006.183.08:21:00.74#ibcon#first serial, iclass 4, count 2 2006.183.08:21:00.74#ibcon#enter sib2, iclass 4, count 2 2006.183.08:21:00.74#ibcon#flushed, iclass 4, count 2 2006.183.08:21:00.74#ibcon#about to write, iclass 4, count 2 2006.183.08:21:00.74#ibcon#wrote, iclass 4, count 2 2006.183.08:21:00.74#ibcon#about to read 3, iclass 4, count 2 2006.183.08:21:00.76#ibcon#read 3, iclass 4, count 2 2006.183.08:21:00.76#ibcon#about to read 4, iclass 4, count 2 2006.183.08:21:00.76#ibcon#read 4, iclass 4, count 2 2006.183.08:21:00.76#ibcon#about to read 5, iclass 4, count 2 2006.183.08:21:00.76#ibcon#read 5, iclass 4, count 2 2006.183.08:21:00.76#ibcon#about to read 6, iclass 4, count 2 2006.183.08:21:00.76#ibcon#read 6, iclass 4, count 2 2006.183.08:21:00.76#ibcon#end of sib2, iclass 4, count 2 2006.183.08:21:00.76#ibcon#*mode == 0, iclass 4, count 2 2006.183.08:21:00.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.183.08:21:00.76#ibcon#[27=AT01-04\r\n] 2006.183.08:21:00.76#ibcon#*before write, iclass 4, count 2 2006.183.08:21:00.76#ibcon#enter sib2, iclass 4, count 2 2006.183.08:21:00.76#ibcon#flushed, iclass 4, count 2 2006.183.08:21:00.76#ibcon#about to write, iclass 4, count 2 2006.183.08:21:00.76#ibcon#wrote, iclass 4, count 2 2006.183.08:21:00.76#ibcon#about to read 3, iclass 4, count 2 2006.183.08:21:00.79#ibcon#read 3, iclass 4, count 2 2006.183.08:21:00.79#ibcon#about to read 4, iclass 4, count 2 2006.183.08:21:00.79#ibcon#read 4, iclass 4, count 2 2006.183.08:21:00.79#ibcon#about to read 5, iclass 4, count 2 2006.183.08:21:00.79#ibcon#read 5, iclass 4, count 2 2006.183.08:21:00.79#ibcon#about to read 6, iclass 4, count 2 2006.183.08:21:00.79#ibcon#read 6, iclass 4, count 2 2006.183.08:21:00.79#ibcon#end of sib2, iclass 4, count 2 2006.183.08:21:00.79#ibcon#*after write, iclass 4, count 2 2006.183.08:21:00.79#ibcon#*before return 0, iclass 4, count 2 2006.183.08:21:00.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:21:00.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.183.08:21:00.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.183.08:21:00.79#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:00.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:21:00.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:21:00.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:21:00.91#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:21:00.91#ibcon#first serial, iclass 4, count 0 2006.183.08:21:00.91#ibcon#enter sib2, iclass 4, count 0 2006.183.08:21:00.91#ibcon#flushed, iclass 4, count 0 2006.183.08:21:00.91#ibcon#about to write, iclass 4, count 0 2006.183.08:21:00.91#ibcon#wrote, iclass 4, count 0 2006.183.08:21:00.91#ibcon#about to read 3, iclass 4, count 0 2006.183.08:21:00.93#ibcon#read 3, iclass 4, count 0 2006.183.08:21:00.93#ibcon#about to read 4, iclass 4, count 0 2006.183.08:21:00.93#ibcon#read 4, iclass 4, count 0 2006.183.08:21:00.93#ibcon#about to read 5, iclass 4, count 0 2006.183.08:21:00.93#ibcon#read 5, iclass 4, count 0 2006.183.08:21:00.93#ibcon#about to read 6, iclass 4, count 0 2006.183.08:21:00.93#ibcon#read 6, iclass 4, count 0 2006.183.08:21:00.93#ibcon#end of sib2, iclass 4, count 0 2006.183.08:21:00.93#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:21:00.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:21:00.93#ibcon#[27=USB\r\n] 2006.183.08:21:00.93#ibcon#*before write, iclass 4, count 0 2006.183.08:21:00.93#ibcon#enter sib2, iclass 4, count 0 2006.183.08:21:00.93#ibcon#flushed, iclass 4, count 0 2006.183.08:21:00.93#ibcon#about to write, iclass 4, count 0 2006.183.08:21:00.93#ibcon#wrote, iclass 4, count 0 2006.183.08:21:00.93#ibcon#about to read 3, iclass 4, count 0 2006.183.08:21:00.96#ibcon#read 3, iclass 4, count 0 2006.183.08:21:00.96#ibcon#about to read 4, iclass 4, count 0 2006.183.08:21:00.96#ibcon#read 4, iclass 4, count 0 2006.183.08:21:00.96#ibcon#about to read 5, iclass 4, count 0 2006.183.08:21:00.96#ibcon#read 5, iclass 4, count 0 2006.183.08:21:00.96#ibcon#about to read 6, iclass 4, count 0 2006.183.08:21:00.96#ibcon#read 6, iclass 4, count 0 2006.183.08:21:00.96#ibcon#end of sib2, iclass 4, count 0 2006.183.08:21:00.96#ibcon#*after write, iclass 4, count 0 2006.183.08:21:00.96#ibcon#*before return 0, iclass 4, count 0 2006.183.08:21:00.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:21:00.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.183.08:21:00.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:21:00.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:21:00.96$vc4f8/vblo=2,640.99 2006.183.08:21:00.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.183.08:21:00.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.183.08:21:00.96#ibcon#ireg 17 cls_cnt 0 2006.183.08:21:00.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:21:00.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:21:00.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:21:00.96#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:21:00.96#ibcon#first serial, iclass 6, count 0 2006.183.08:21:00.96#ibcon#enter sib2, iclass 6, count 0 2006.183.08:21:00.96#ibcon#flushed, iclass 6, count 0 2006.183.08:21:00.96#ibcon#about to write, iclass 6, count 0 2006.183.08:21:00.96#ibcon#wrote, iclass 6, count 0 2006.183.08:21:00.96#ibcon#about to read 3, iclass 6, count 0 2006.183.08:21:00.98#ibcon#read 3, iclass 6, count 0 2006.183.08:21:00.98#ibcon#about to read 4, iclass 6, count 0 2006.183.08:21:00.98#ibcon#read 4, iclass 6, count 0 2006.183.08:21:00.98#ibcon#about to read 5, iclass 6, count 0 2006.183.08:21:00.98#ibcon#read 5, iclass 6, count 0 2006.183.08:21:00.98#ibcon#about to read 6, iclass 6, count 0 2006.183.08:21:00.98#ibcon#read 6, iclass 6, count 0 2006.183.08:21:00.98#ibcon#end of sib2, iclass 6, count 0 2006.183.08:21:00.98#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:21:00.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:21:00.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:21:00.98#ibcon#*before write, iclass 6, count 0 2006.183.08:21:00.98#ibcon#enter sib2, iclass 6, count 0 2006.183.08:21:00.98#ibcon#flushed, iclass 6, count 0 2006.183.08:21:00.98#ibcon#about to write, iclass 6, count 0 2006.183.08:21:00.98#ibcon#wrote, iclass 6, count 0 2006.183.08:21:00.98#ibcon#about to read 3, iclass 6, count 0 2006.183.08:21:01.02#ibcon#read 3, iclass 6, count 0 2006.183.08:21:01.02#ibcon#about to read 4, iclass 6, count 0 2006.183.08:21:01.02#ibcon#read 4, iclass 6, count 0 2006.183.08:21:01.02#ibcon#about to read 5, iclass 6, count 0 2006.183.08:21:01.02#ibcon#read 5, iclass 6, count 0 2006.183.08:21:01.02#ibcon#about to read 6, iclass 6, count 0 2006.183.08:21:01.02#ibcon#read 6, iclass 6, count 0 2006.183.08:21:01.02#ibcon#end of sib2, iclass 6, count 0 2006.183.08:21:01.02#ibcon#*after write, iclass 6, count 0 2006.183.08:21:01.02#ibcon#*before return 0, iclass 6, count 0 2006.183.08:21:01.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:21:01.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.183.08:21:01.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:21:01.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:21:01.02$vc4f8/vb=2,4 2006.183.08:21:01.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.183.08:21:01.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.183.08:21:01.02#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:01.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:21:01.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:21:01.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:21:01.08#ibcon#enter wrdev, iclass 10, count 2 2006.183.08:21:01.08#ibcon#first serial, iclass 10, count 2 2006.183.08:21:01.08#ibcon#enter sib2, iclass 10, count 2 2006.183.08:21:01.08#ibcon#flushed, iclass 10, count 2 2006.183.08:21:01.08#ibcon#about to write, iclass 10, count 2 2006.183.08:21:01.08#ibcon#wrote, iclass 10, count 2 2006.183.08:21:01.08#ibcon#about to read 3, iclass 10, count 2 2006.183.08:21:01.10#ibcon#read 3, iclass 10, count 2 2006.183.08:21:01.10#ibcon#about to read 4, iclass 10, count 2 2006.183.08:21:01.10#ibcon#read 4, iclass 10, count 2 2006.183.08:21:01.10#ibcon#about to read 5, iclass 10, count 2 2006.183.08:21:01.10#ibcon#read 5, iclass 10, count 2 2006.183.08:21:01.10#ibcon#about to read 6, iclass 10, count 2 2006.183.08:21:01.10#ibcon#read 6, iclass 10, count 2 2006.183.08:21:01.10#ibcon#end of sib2, iclass 10, count 2 2006.183.08:21:01.10#ibcon#*mode == 0, iclass 10, count 2 2006.183.08:21:01.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.183.08:21:01.10#ibcon#[27=AT02-04\r\n] 2006.183.08:21:01.10#ibcon#*before write, iclass 10, count 2 2006.183.08:21:01.10#ibcon#enter sib2, iclass 10, count 2 2006.183.08:21:01.10#ibcon#flushed, iclass 10, count 2 2006.183.08:21:01.10#ibcon#about to write, iclass 10, count 2 2006.183.08:21:01.10#ibcon#wrote, iclass 10, count 2 2006.183.08:21:01.10#ibcon#about to read 3, iclass 10, count 2 2006.183.08:21:01.13#ibcon#read 3, iclass 10, count 2 2006.183.08:21:01.13#ibcon#about to read 4, iclass 10, count 2 2006.183.08:21:01.13#ibcon#read 4, iclass 10, count 2 2006.183.08:21:01.13#ibcon#about to read 5, iclass 10, count 2 2006.183.08:21:01.13#ibcon#read 5, iclass 10, count 2 2006.183.08:21:01.13#ibcon#about to read 6, iclass 10, count 2 2006.183.08:21:01.13#ibcon#read 6, iclass 10, count 2 2006.183.08:21:01.13#ibcon#end of sib2, iclass 10, count 2 2006.183.08:21:01.13#ibcon#*after write, iclass 10, count 2 2006.183.08:21:01.13#ibcon#*before return 0, iclass 10, count 2 2006.183.08:21:01.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:21:01.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.183.08:21:01.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.183.08:21:01.13#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:01.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:21:01.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:21:01.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:21:01.25#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:21:01.25#ibcon#first serial, iclass 10, count 0 2006.183.08:21:01.25#ibcon#enter sib2, iclass 10, count 0 2006.183.08:21:01.25#ibcon#flushed, iclass 10, count 0 2006.183.08:21:01.25#ibcon#about to write, iclass 10, count 0 2006.183.08:21:01.25#ibcon#wrote, iclass 10, count 0 2006.183.08:21:01.25#ibcon#about to read 3, iclass 10, count 0 2006.183.08:21:01.27#ibcon#read 3, iclass 10, count 0 2006.183.08:21:01.27#ibcon#about to read 4, iclass 10, count 0 2006.183.08:21:01.27#ibcon#read 4, iclass 10, count 0 2006.183.08:21:01.27#ibcon#about to read 5, iclass 10, count 0 2006.183.08:21:01.27#ibcon#read 5, iclass 10, count 0 2006.183.08:21:01.27#ibcon#about to read 6, iclass 10, count 0 2006.183.08:21:01.27#ibcon#read 6, iclass 10, count 0 2006.183.08:21:01.27#ibcon#end of sib2, iclass 10, count 0 2006.183.08:21:01.27#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:21:01.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:21:01.27#ibcon#[27=USB\r\n] 2006.183.08:21:01.27#ibcon#*before write, iclass 10, count 0 2006.183.08:21:01.27#ibcon#enter sib2, iclass 10, count 0 2006.183.08:21:01.27#ibcon#flushed, iclass 10, count 0 2006.183.08:21:01.27#ibcon#about to write, iclass 10, count 0 2006.183.08:21:01.27#ibcon#wrote, iclass 10, count 0 2006.183.08:21:01.27#ibcon#about to read 3, iclass 10, count 0 2006.183.08:21:01.30#ibcon#read 3, iclass 10, count 0 2006.183.08:21:01.30#ibcon#about to read 4, iclass 10, count 0 2006.183.08:21:01.30#ibcon#read 4, iclass 10, count 0 2006.183.08:21:01.30#ibcon#about to read 5, iclass 10, count 0 2006.183.08:21:01.30#ibcon#read 5, iclass 10, count 0 2006.183.08:21:01.30#ibcon#about to read 6, iclass 10, count 0 2006.183.08:21:01.30#ibcon#read 6, iclass 10, count 0 2006.183.08:21:01.30#ibcon#end of sib2, iclass 10, count 0 2006.183.08:21:01.30#ibcon#*after write, iclass 10, count 0 2006.183.08:21:01.30#ibcon#*before return 0, iclass 10, count 0 2006.183.08:21:01.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:21:01.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.183.08:21:01.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:21:01.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:21:01.30$vc4f8/vblo=3,656.99 2006.183.08:21:01.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.183.08:21:01.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.183.08:21:01.30#ibcon#ireg 17 cls_cnt 0 2006.183.08:21:01.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:21:01.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:21:01.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:21:01.30#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:21:01.30#ibcon#first serial, iclass 12, count 0 2006.183.08:21:01.30#ibcon#enter sib2, iclass 12, count 0 2006.183.08:21:01.30#ibcon#flushed, iclass 12, count 0 2006.183.08:21:01.30#ibcon#about to write, iclass 12, count 0 2006.183.08:21:01.30#ibcon#wrote, iclass 12, count 0 2006.183.08:21:01.30#ibcon#about to read 3, iclass 12, count 0 2006.183.08:21:01.32#ibcon#read 3, iclass 12, count 0 2006.183.08:21:01.32#ibcon#about to read 4, iclass 12, count 0 2006.183.08:21:01.32#ibcon#read 4, iclass 12, count 0 2006.183.08:21:01.32#ibcon#about to read 5, iclass 12, count 0 2006.183.08:21:01.32#ibcon#read 5, iclass 12, count 0 2006.183.08:21:01.32#ibcon#about to read 6, iclass 12, count 0 2006.183.08:21:01.32#ibcon#read 6, iclass 12, count 0 2006.183.08:21:01.32#ibcon#end of sib2, iclass 12, count 0 2006.183.08:21:01.32#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:21:01.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:21:01.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:21:01.32#ibcon#*before write, iclass 12, count 0 2006.183.08:21:01.32#ibcon#enter sib2, iclass 12, count 0 2006.183.08:21:01.32#ibcon#flushed, iclass 12, count 0 2006.183.08:21:01.32#ibcon#about to write, iclass 12, count 0 2006.183.08:21:01.32#ibcon#wrote, iclass 12, count 0 2006.183.08:21:01.32#ibcon#about to read 3, iclass 12, count 0 2006.183.08:21:01.36#ibcon#read 3, iclass 12, count 0 2006.183.08:21:01.36#ibcon#about to read 4, iclass 12, count 0 2006.183.08:21:01.36#ibcon#read 4, iclass 12, count 0 2006.183.08:21:01.36#ibcon#about to read 5, iclass 12, count 0 2006.183.08:21:01.36#ibcon#read 5, iclass 12, count 0 2006.183.08:21:01.36#ibcon#about to read 6, iclass 12, count 0 2006.183.08:21:01.36#ibcon#read 6, iclass 12, count 0 2006.183.08:21:01.36#ibcon#end of sib2, iclass 12, count 0 2006.183.08:21:01.36#ibcon#*after write, iclass 12, count 0 2006.183.08:21:01.36#ibcon#*before return 0, iclass 12, count 0 2006.183.08:21:01.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:21:01.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.183.08:21:01.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:21:01.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:21:01.36$vc4f8/vb=3,4 2006.183.08:21:01.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.183.08:21:01.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.183.08:21:01.36#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:01.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:21:01.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:21:01.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:21:01.42#ibcon#enter wrdev, iclass 14, count 2 2006.183.08:21:01.42#ibcon#first serial, iclass 14, count 2 2006.183.08:21:01.42#ibcon#enter sib2, iclass 14, count 2 2006.183.08:21:01.42#ibcon#flushed, iclass 14, count 2 2006.183.08:21:01.42#ibcon#about to write, iclass 14, count 2 2006.183.08:21:01.42#ibcon#wrote, iclass 14, count 2 2006.183.08:21:01.42#ibcon#about to read 3, iclass 14, count 2 2006.183.08:21:01.44#ibcon#read 3, iclass 14, count 2 2006.183.08:21:01.44#ibcon#about to read 4, iclass 14, count 2 2006.183.08:21:01.44#ibcon#read 4, iclass 14, count 2 2006.183.08:21:01.44#ibcon#about to read 5, iclass 14, count 2 2006.183.08:21:01.44#ibcon#read 5, iclass 14, count 2 2006.183.08:21:01.44#ibcon#about to read 6, iclass 14, count 2 2006.183.08:21:01.44#ibcon#read 6, iclass 14, count 2 2006.183.08:21:01.44#ibcon#end of sib2, iclass 14, count 2 2006.183.08:21:01.44#ibcon#*mode == 0, iclass 14, count 2 2006.183.08:21:01.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.183.08:21:01.44#ibcon#[27=AT03-04\r\n] 2006.183.08:21:01.44#ibcon#*before write, iclass 14, count 2 2006.183.08:21:01.44#ibcon#enter sib2, iclass 14, count 2 2006.183.08:21:01.44#ibcon#flushed, iclass 14, count 2 2006.183.08:21:01.44#ibcon#about to write, iclass 14, count 2 2006.183.08:21:01.44#ibcon#wrote, iclass 14, count 2 2006.183.08:21:01.44#ibcon#about to read 3, iclass 14, count 2 2006.183.08:21:01.47#ibcon#read 3, iclass 14, count 2 2006.183.08:21:01.47#ibcon#about to read 4, iclass 14, count 2 2006.183.08:21:01.47#ibcon#read 4, iclass 14, count 2 2006.183.08:21:01.47#ibcon#about to read 5, iclass 14, count 2 2006.183.08:21:01.47#ibcon#read 5, iclass 14, count 2 2006.183.08:21:01.47#ibcon#about to read 6, iclass 14, count 2 2006.183.08:21:01.47#ibcon#read 6, iclass 14, count 2 2006.183.08:21:01.47#ibcon#end of sib2, iclass 14, count 2 2006.183.08:21:01.47#ibcon#*after write, iclass 14, count 2 2006.183.08:21:01.47#ibcon#*before return 0, iclass 14, count 2 2006.183.08:21:01.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:21:01.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.183.08:21:01.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.183.08:21:01.47#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:01.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:21:01.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:21:01.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:21:01.59#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:21:01.59#ibcon#first serial, iclass 14, count 0 2006.183.08:21:01.59#ibcon#enter sib2, iclass 14, count 0 2006.183.08:21:01.59#ibcon#flushed, iclass 14, count 0 2006.183.08:21:01.59#ibcon#about to write, iclass 14, count 0 2006.183.08:21:01.59#ibcon#wrote, iclass 14, count 0 2006.183.08:21:01.59#ibcon#about to read 3, iclass 14, count 0 2006.183.08:21:01.61#ibcon#read 3, iclass 14, count 0 2006.183.08:21:01.61#ibcon#about to read 4, iclass 14, count 0 2006.183.08:21:01.61#ibcon#read 4, iclass 14, count 0 2006.183.08:21:01.61#ibcon#about to read 5, iclass 14, count 0 2006.183.08:21:01.61#ibcon#read 5, iclass 14, count 0 2006.183.08:21:01.61#ibcon#about to read 6, iclass 14, count 0 2006.183.08:21:01.61#ibcon#read 6, iclass 14, count 0 2006.183.08:21:01.61#ibcon#end of sib2, iclass 14, count 0 2006.183.08:21:01.61#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:21:01.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:21:01.61#ibcon#[27=USB\r\n] 2006.183.08:21:01.61#ibcon#*before write, iclass 14, count 0 2006.183.08:21:01.61#ibcon#enter sib2, iclass 14, count 0 2006.183.08:21:01.61#ibcon#flushed, iclass 14, count 0 2006.183.08:21:01.61#ibcon#about to write, iclass 14, count 0 2006.183.08:21:01.61#ibcon#wrote, iclass 14, count 0 2006.183.08:21:01.61#ibcon#about to read 3, iclass 14, count 0 2006.183.08:21:01.64#ibcon#read 3, iclass 14, count 0 2006.183.08:21:01.64#ibcon#about to read 4, iclass 14, count 0 2006.183.08:21:01.64#ibcon#read 4, iclass 14, count 0 2006.183.08:21:01.64#ibcon#about to read 5, iclass 14, count 0 2006.183.08:21:01.64#ibcon#read 5, iclass 14, count 0 2006.183.08:21:01.64#ibcon#about to read 6, iclass 14, count 0 2006.183.08:21:01.64#ibcon#read 6, iclass 14, count 0 2006.183.08:21:01.64#ibcon#end of sib2, iclass 14, count 0 2006.183.08:21:01.64#ibcon#*after write, iclass 14, count 0 2006.183.08:21:01.64#ibcon#*before return 0, iclass 14, count 0 2006.183.08:21:01.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:21:01.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.183.08:21:01.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:21:01.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:21:01.64$vc4f8/vblo=4,712.99 2006.183.08:21:01.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.183.08:21:01.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.183.08:21:01.64#ibcon#ireg 17 cls_cnt 0 2006.183.08:21:01.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:21:01.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:21:01.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:21:01.64#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:21:01.64#ibcon#first serial, iclass 16, count 0 2006.183.08:21:01.64#ibcon#enter sib2, iclass 16, count 0 2006.183.08:21:01.64#ibcon#flushed, iclass 16, count 0 2006.183.08:21:01.64#ibcon#about to write, iclass 16, count 0 2006.183.08:21:01.64#ibcon#wrote, iclass 16, count 0 2006.183.08:21:01.64#ibcon#about to read 3, iclass 16, count 0 2006.183.08:21:01.67#ibcon#read 3, iclass 16, count 0 2006.183.08:21:01.67#ibcon#about to read 4, iclass 16, count 0 2006.183.08:21:01.67#ibcon#read 4, iclass 16, count 0 2006.183.08:21:01.67#ibcon#about to read 5, iclass 16, count 0 2006.183.08:21:01.67#ibcon#read 5, iclass 16, count 0 2006.183.08:21:01.67#ibcon#about to read 6, iclass 16, count 0 2006.183.08:21:01.67#ibcon#read 6, iclass 16, count 0 2006.183.08:21:01.67#ibcon#end of sib2, iclass 16, count 0 2006.183.08:21:01.67#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:21:01.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:21:01.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:21:01.67#ibcon#*before write, iclass 16, count 0 2006.183.08:21:01.67#ibcon#enter sib2, iclass 16, count 0 2006.183.08:21:01.67#ibcon#flushed, iclass 16, count 0 2006.183.08:21:01.67#ibcon#about to write, iclass 16, count 0 2006.183.08:21:01.67#ibcon#wrote, iclass 16, count 0 2006.183.08:21:01.67#ibcon#about to read 3, iclass 16, count 0 2006.183.08:21:01.71#ibcon#read 3, iclass 16, count 0 2006.183.08:21:01.71#ibcon#about to read 4, iclass 16, count 0 2006.183.08:21:01.71#ibcon#read 4, iclass 16, count 0 2006.183.08:21:01.71#ibcon#about to read 5, iclass 16, count 0 2006.183.08:21:01.71#ibcon#read 5, iclass 16, count 0 2006.183.08:21:01.71#ibcon#about to read 6, iclass 16, count 0 2006.183.08:21:01.71#ibcon#read 6, iclass 16, count 0 2006.183.08:21:01.71#ibcon#end of sib2, iclass 16, count 0 2006.183.08:21:01.71#ibcon#*after write, iclass 16, count 0 2006.183.08:21:01.71#ibcon#*before return 0, iclass 16, count 0 2006.183.08:21:01.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:21:01.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.183.08:21:01.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:21:01.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:21:01.71$vc4f8/vb=4,4 2006.183.08:21:01.71#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.183.08:21:01.71#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.183.08:21:01.71#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:01.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:21:01.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:21:01.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:21:01.76#ibcon#enter wrdev, iclass 18, count 2 2006.183.08:21:01.76#ibcon#first serial, iclass 18, count 2 2006.183.08:21:01.76#ibcon#enter sib2, iclass 18, count 2 2006.183.08:21:01.76#ibcon#flushed, iclass 18, count 2 2006.183.08:21:01.76#ibcon#about to write, iclass 18, count 2 2006.183.08:21:01.76#ibcon#wrote, iclass 18, count 2 2006.183.08:21:01.76#ibcon#about to read 3, iclass 18, count 2 2006.183.08:21:01.78#ibcon#read 3, iclass 18, count 2 2006.183.08:21:01.78#ibcon#about to read 4, iclass 18, count 2 2006.183.08:21:01.78#ibcon#read 4, iclass 18, count 2 2006.183.08:21:01.78#ibcon#about to read 5, iclass 18, count 2 2006.183.08:21:01.78#ibcon#read 5, iclass 18, count 2 2006.183.08:21:01.78#ibcon#about to read 6, iclass 18, count 2 2006.183.08:21:01.78#ibcon#read 6, iclass 18, count 2 2006.183.08:21:01.78#ibcon#end of sib2, iclass 18, count 2 2006.183.08:21:01.78#ibcon#*mode == 0, iclass 18, count 2 2006.183.08:21:01.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.183.08:21:01.78#ibcon#[27=AT04-04\r\n] 2006.183.08:21:01.78#ibcon#*before write, iclass 18, count 2 2006.183.08:21:01.78#ibcon#enter sib2, iclass 18, count 2 2006.183.08:21:01.78#ibcon#flushed, iclass 18, count 2 2006.183.08:21:01.78#ibcon#about to write, iclass 18, count 2 2006.183.08:21:01.78#ibcon#wrote, iclass 18, count 2 2006.183.08:21:01.78#ibcon#about to read 3, iclass 18, count 2 2006.183.08:21:01.81#ibcon#read 3, iclass 18, count 2 2006.183.08:21:01.81#ibcon#about to read 4, iclass 18, count 2 2006.183.08:21:01.81#ibcon#read 4, iclass 18, count 2 2006.183.08:21:01.81#ibcon#about to read 5, iclass 18, count 2 2006.183.08:21:01.81#ibcon#read 5, iclass 18, count 2 2006.183.08:21:01.81#ibcon#about to read 6, iclass 18, count 2 2006.183.08:21:01.81#ibcon#read 6, iclass 18, count 2 2006.183.08:21:01.81#ibcon#end of sib2, iclass 18, count 2 2006.183.08:21:01.81#ibcon#*after write, iclass 18, count 2 2006.183.08:21:01.81#ibcon#*before return 0, iclass 18, count 2 2006.183.08:21:01.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:21:01.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.183.08:21:01.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.183.08:21:01.81#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:01.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:21:01.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:21:01.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:21:01.93#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:21:01.93#ibcon#first serial, iclass 18, count 0 2006.183.08:21:01.93#ibcon#enter sib2, iclass 18, count 0 2006.183.08:21:01.93#ibcon#flushed, iclass 18, count 0 2006.183.08:21:01.93#ibcon#about to write, iclass 18, count 0 2006.183.08:21:01.93#ibcon#wrote, iclass 18, count 0 2006.183.08:21:01.93#ibcon#about to read 3, iclass 18, count 0 2006.183.08:21:01.95#ibcon#read 3, iclass 18, count 0 2006.183.08:21:01.95#ibcon#about to read 4, iclass 18, count 0 2006.183.08:21:01.95#ibcon#read 4, iclass 18, count 0 2006.183.08:21:01.95#ibcon#about to read 5, iclass 18, count 0 2006.183.08:21:01.95#ibcon#read 5, iclass 18, count 0 2006.183.08:21:01.95#ibcon#about to read 6, iclass 18, count 0 2006.183.08:21:01.95#ibcon#read 6, iclass 18, count 0 2006.183.08:21:01.95#ibcon#end of sib2, iclass 18, count 0 2006.183.08:21:01.95#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:21:01.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:21:01.95#ibcon#[27=USB\r\n] 2006.183.08:21:01.95#ibcon#*before write, iclass 18, count 0 2006.183.08:21:01.95#ibcon#enter sib2, iclass 18, count 0 2006.183.08:21:01.95#ibcon#flushed, iclass 18, count 0 2006.183.08:21:01.95#ibcon#about to write, iclass 18, count 0 2006.183.08:21:01.95#ibcon#wrote, iclass 18, count 0 2006.183.08:21:01.95#ibcon#about to read 3, iclass 18, count 0 2006.183.08:21:01.98#ibcon#read 3, iclass 18, count 0 2006.183.08:21:01.98#ibcon#about to read 4, iclass 18, count 0 2006.183.08:21:01.98#ibcon#read 4, iclass 18, count 0 2006.183.08:21:01.98#ibcon#about to read 5, iclass 18, count 0 2006.183.08:21:01.98#ibcon#read 5, iclass 18, count 0 2006.183.08:21:01.98#ibcon#about to read 6, iclass 18, count 0 2006.183.08:21:01.98#ibcon#read 6, iclass 18, count 0 2006.183.08:21:01.98#ibcon#end of sib2, iclass 18, count 0 2006.183.08:21:01.98#ibcon#*after write, iclass 18, count 0 2006.183.08:21:01.98#ibcon#*before return 0, iclass 18, count 0 2006.183.08:21:01.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:21:01.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.183.08:21:01.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:21:01.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:21:01.98$vc4f8/vblo=5,744.99 2006.183.08:21:01.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.183.08:21:01.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.183.08:21:01.98#ibcon#ireg 17 cls_cnt 0 2006.183.08:21:01.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:21:01.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:21:01.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:21:01.98#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:21:01.98#ibcon#first serial, iclass 20, count 0 2006.183.08:21:01.98#ibcon#enter sib2, iclass 20, count 0 2006.183.08:21:01.98#ibcon#flushed, iclass 20, count 0 2006.183.08:21:01.98#ibcon#about to write, iclass 20, count 0 2006.183.08:21:01.98#ibcon#wrote, iclass 20, count 0 2006.183.08:21:01.98#ibcon#about to read 3, iclass 20, count 0 2006.183.08:21:02.00#ibcon#read 3, iclass 20, count 0 2006.183.08:21:02.00#ibcon#about to read 4, iclass 20, count 0 2006.183.08:21:02.00#ibcon#read 4, iclass 20, count 0 2006.183.08:21:02.00#ibcon#about to read 5, iclass 20, count 0 2006.183.08:21:02.00#ibcon#read 5, iclass 20, count 0 2006.183.08:21:02.00#ibcon#about to read 6, iclass 20, count 0 2006.183.08:21:02.00#ibcon#read 6, iclass 20, count 0 2006.183.08:21:02.00#ibcon#end of sib2, iclass 20, count 0 2006.183.08:21:02.00#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:21:02.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:21:02.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:21:02.00#ibcon#*before write, iclass 20, count 0 2006.183.08:21:02.00#ibcon#enter sib2, iclass 20, count 0 2006.183.08:21:02.00#ibcon#flushed, iclass 20, count 0 2006.183.08:21:02.00#ibcon#about to write, iclass 20, count 0 2006.183.08:21:02.00#ibcon#wrote, iclass 20, count 0 2006.183.08:21:02.00#ibcon#about to read 3, iclass 20, count 0 2006.183.08:21:02.04#ibcon#read 3, iclass 20, count 0 2006.183.08:21:02.04#ibcon#about to read 4, iclass 20, count 0 2006.183.08:21:02.04#ibcon#read 4, iclass 20, count 0 2006.183.08:21:02.04#ibcon#about to read 5, iclass 20, count 0 2006.183.08:21:02.04#ibcon#read 5, iclass 20, count 0 2006.183.08:21:02.04#ibcon#about to read 6, iclass 20, count 0 2006.183.08:21:02.04#ibcon#read 6, iclass 20, count 0 2006.183.08:21:02.04#ibcon#end of sib2, iclass 20, count 0 2006.183.08:21:02.04#ibcon#*after write, iclass 20, count 0 2006.183.08:21:02.04#ibcon#*before return 0, iclass 20, count 0 2006.183.08:21:02.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:21:02.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.183.08:21:02.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:21:02.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:21:02.04$vc4f8/vb=5,4 2006.183.08:21:02.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.183.08:21:02.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.183.08:21:02.04#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:02.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:21:02.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:21:02.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:21:02.10#ibcon#enter wrdev, iclass 22, count 2 2006.183.08:21:02.10#ibcon#first serial, iclass 22, count 2 2006.183.08:21:02.10#ibcon#enter sib2, iclass 22, count 2 2006.183.08:21:02.10#ibcon#flushed, iclass 22, count 2 2006.183.08:21:02.10#ibcon#about to write, iclass 22, count 2 2006.183.08:21:02.10#ibcon#wrote, iclass 22, count 2 2006.183.08:21:02.10#ibcon#about to read 3, iclass 22, count 2 2006.183.08:21:02.12#ibcon#read 3, iclass 22, count 2 2006.183.08:21:02.12#ibcon#about to read 4, iclass 22, count 2 2006.183.08:21:02.12#ibcon#read 4, iclass 22, count 2 2006.183.08:21:02.12#ibcon#about to read 5, iclass 22, count 2 2006.183.08:21:02.12#ibcon#read 5, iclass 22, count 2 2006.183.08:21:02.12#ibcon#about to read 6, iclass 22, count 2 2006.183.08:21:02.12#ibcon#read 6, iclass 22, count 2 2006.183.08:21:02.12#ibcon#end of sib2, iclass 22, count 2 2006.183.08:21:02.12#ibcon#*mode == 0, iclass 22, count 2 2006.183.08:21:02.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.183.08:21:02.12#ibcon#[27=AT05-04\r\n] 2006.183.08:21:02.12#ibcon#*before write, iclass 22, count 2 2006.183.08:21:02.12#ibcon#enter sib2, iclass 22, count 2 2006.183.08:21:02.12#ibcon#flushed, iclass 22, count 2 2006.183.08:21:02.12#ibcon#about to write, iclass 22, count 2 2006.183.08:21:02.12#ibcon#wrote, iclass 22, count 2 2006.183.08:21:02.12#ibcon#about to read 3, iclass 22, count 2 2006.183.08:21:02.15#ibcon#read 3, iclass 22, count 2 2006.183.08:21:02.15#ibcon#about to read 4, iclass 22, count 2 2006.183.08:21:02.15#ibcon#read 4, iclass 22, count 2 2006.183.08:21:02.15#ibcon#about to read 5, iclass 22, count 2 2006.183.08:21:02.15#ibcon#read 5, iclass 22, count 2 2006.183.08:21:02.15#ibcon#about to read 6, iclass 22, count 2 2006.183.08:21:02.15#ibcon#read 6, iclass 22, count 2 2006.183.08:21:02.15#ibcon#end of sib2, iclass 22, count 2 2006.183.08:21:02.15#ibcon#*after write, iclass 22, count 2 2006.183.08:21:02.15#ibcon#*before return 0, iclass 22, count 2 2006.183.08:21:02.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:21:02.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.183.08:21:02.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.183.08:21:02.15#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:02.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:21:02.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:21:02.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:21:02.27#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:21:02.27#ibcon#first serial, iclass 22, count 0 2006.183.08:21:02.27#ibcon#enter sib2, iclass 22, count 0 2006.183.08:21:02.27#ibcon#flushed, iclass 22, count 0 2006.183.08:21:02.27#ibcon#about to write, iclass 22, count 0 2006.183.08:21:02.27#ibcon#wrote, iclass 22, count 0 2006.183.08:21:02.27#ibcon#about to read 3, iclass 22, count 0 2006.183.08:21:02.29#ibcon#read 3, iclass 22, count 0 2006.183.08:21:02.29#ibcon#about to read 4, iclass 22, count 0 2006.183.08:21:02.29#ibcon#read 4, iclass 22, count 0 2006.183.08:21:02.29#ibcon#about to read 5, iclass 22, count 0 2006.183.08:21:02.29#ibcon#read 5, iclass 22, count 0 2006.183.08:21:02.29#ibcon#about to read 6, iclass 22, count 0 2006.183.08:21:02.29#ibcon#read 6, iclass 22, count 0 2006.183.08:21:02.29#ibcon#end of sib2, iclass 22, count 0 2006.183.08:21:02.29#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:21:02.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:21:02.29#ibcon#[27=USB\r\n] 2006.183.08:21:02.29#ibcon#*before write, iclass 22, count 0 2006.183.08:21:02.29#ibcon#enter sib2, iclass 22, count 0 2006.183.08:21:02.29#ibcon#flushed, iclass 22, count 0 2006.183.08:21:02.29#ibcon#about to write, iclass 22, count 0 2006.183.08:21:02.29#ibcon#wrote, iclass 22, count 0 2006.183.08:21:02.29#ibcon#about to read 3, iclass 22, count 0 2006.183.08:21:02.32#ibcon#read 3, iclass 22, count 0 2006.183.08:21:02.32#ibcon#about to read 4, iclass 22, count 0 2006.183.08:21:02.32#ibcon#read 4, iclass 22, count 0 2006.183.08:21:02.32#ibcon#about to read 5, iclass 22, count 0 2006.183.08:21:02.32#ibcon#read 5, iclass 22, count 0 2006.183.08:21:02.32#ibcon#about to read 6, iclass 22, count 0 2006.183.08:21:02.32#ibcon#read 6, iclass 22, count 0 2006.183.08:21:02.32#ibcon#end of sib2, iclass 22, count 0 2006.183.08:21:02.32#ibcon#*after write, iclass 22, count 0 2006.183.08:21:02.32#ibcon#*before return 0, iclass 22, count 0 2006.183.08:21:02.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:21:02.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.183.08:21:02.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:21:02.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:21:02.32$vc4f8/vblo=6,752.99 2006.183.08:21:02.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.183.08:21:02.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.183.08:21:02.32#ibcon#ireg 17 cls_cnt 0 2006.183.08:21:02.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:21:02.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:21:02.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:21:02.32#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:21:02.32#ibcon#first serial, iclass 24, count 0 2006.183.08:21:02.32#ibcon#enter sib2, iclass 24, count 0 2006.183.08:21:02.32#ibcon#flushed, iclass 24, count 0 2006.183.08:21:02.32#ibcon#about to write, iclass 24, count 0 2006.183.08:21:02.32#ibcon#wrote, iclass 24, count 0 2006.183.08:21:02.32#ibcon#about to read 3, iclass 24, count 0 2006.183.08:21:02.34#ibcon#read 3, iclass 24, count 0 2006.183.08:21:02.34#ibcon#about to read 4, iclass 24, count 0 2006.183.08:21:02.34#ibcon#read 4, iclass 24, count 0 2006.183.08:21:02.34#ibcon#about to read 5, iclass 24, count 0 2006.183.08:21:02.34#ibcon#read 5, iclass 24, count 0 2006.183.08:21:02.34#ibcon#about to read 6, iclass 24, count 0 2006.183.08:21:02.34#ibcon#read 6, iclass 24, count 0 2006.183.08:21:02.34#ibcon#end of sib2, iclass 24, count 0 2006.183.08:21:02.34#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:21:02.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:21:02.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:21:02.34#ibcon#*before write, iclass 24, count 0 2006.183.08:21:02.34#ibcon#enter sib2, iclass 24, count 0 2006.183.08:21:02.34#ibcon#flushed, iclass 24, count 0 2006.183.08:21:02.34#ibcon#about to write, iclass 24, count 0 2006.183.08:21:02.34#ibcon#wrote, iclass 24, count 0 2006.183.08:21:02.34#ibcon#about to read 3, iclass 24, count 0 2006.183.08:21:02.38#ibcon#read 3, iclass 24, count 0 2006.183.08:21:02.38#ibcon#about to read 4, iclass 24, count 0 2006.183.08:21:02.38#ibcon#read 4, iclass 24, count 0 2006.183.08:21:02.38#ibcon#about to read 5, iclass 24, count 0 2006.183.08:21:02.38#ibcon#read 5, iclass 24, count 0 2006.183.08:21:02.38#ibcon#about to read 6, iclass 24, count 0 2006.183.08:21:02.38#ibcon#read 6, iclass 24, count 0 2006.183.08:21:02.38#ibcon#end of sib2, iclass 24, count 0 2006.183.08:21:02.38#ibcon#*after write, iclass 24, count 0 2006.183.08:21:02.38#ibcon#*before return 0, iclass 24, count 0 2006.183.08:21:02.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:21:02.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.183.08:21:02.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:21:02.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:21:02.38$vc4f8/vb=6,4 2006.183.08:21:02.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.183.08:21:02.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.183.08:21:02.38#ibcon#ireg 11 cls_cnt 2 2006.183.08:21:02.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:21:02.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:21:02.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:21:02.44#ibcon#enter wrdev, iclass 26, count 2 2006.183.08:21:02.44#ibcon#first serial, iclass 26, count 2 2006.183.08:21:02.44#ibcon#enter sib2, iclass 26, count 2 2006.183.08:21:02.44#ibcon#flushed, iclass 26, count 2 2006.183.08:21:02.44#ibcon#about to write, iclass 26, count 2 2006.183.08:21:02.44#ibcon#wrote, iclass 26, count 2 2006.183.08:21:02.44#ibcon#about to read 3, iclass 26, count 2 2006.183.08:21:02.46#ibcon#read 3, iclass 26, count 2 2006.183.08:21:02.46#ibcon#about to read 4, iclass 26, count 2 2006.183.08:21:02.46#ibcon#read 4, iclass 26, count 2 2006.183.08:21:02.46#ibcon#about to read 5, iclass 26, count 2 2006.183.08:21:02.46#ibcon#read 5, iclass 26, count 2 2006.183.08:21:02.46#ibcon#about to read 6, iclass 26, count 2 2006.183.08:21:02.46#ibcon#read 6, iclass 26, count 2 2006.183.08:21:02.46#ibcon#end of sib2, iclass 26, count 2 2006.183.08:21:02.46#ibcon#*mode == 0, iclass 26, count 2 2006.183.08:21:02.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.183.08:21:02.46#ibcon#[27=AT06-04\r\n] 2006.183.08:21:02.46#ibcon#*before write, iclass 26, count 2 2006.183.08:21:02.46#ibcon#enter sib2, iclass 26, count 2 2006.183.08:21:02.46#ibcon#flushed, iclass 26, count 2 2006.183.08:21:02.46#ibcon#about to write, iclass 26, count 2 2006.183.08:21:02.46#ibcon#wrote, iclass 26, count 2 2006.183.08:21:02.46#ibcon#about to read 3, iclass 26, count 2 2006.183.08:21:02.49#ibcon#read 3, iclass 26, count 2 2006.183.08:21:02.49#ibcon#about to read 4, iclass 26, count 2 2006.183.08:21:02.49#ibcon#read 4, iclass 26, count 2 2006.183.08:21:02.49#ibcon#about to read 5, iclass 26, count 2 2006.183.08:21:02.49#ibcon#read 5, iclass 26, count 2 2006.183.08:21:02.49#ibcon#about to read 6, iclass 26, count 2 2006.183.08:21:02.49#ibcon#read 6, iclass 26, count 2 2006.183.08:21:02.49#ibcon#end of sib2, iclass 26, count 2 2006.183.08:21:02.49#ibcon#*after write, iclass 26, count 2 2006.183.08:21:02.49#ibcon#*before return 0, iclass 26, count 2 2006.183.08:21:02.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:21:02.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.183.08:21:02.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.183.08:21:02.49#ibcon#ireg 7 cls_cnt 0 2006.183.08:21:02.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:21:02.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:21:02.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:21:02.61#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:21:02.61#ibcon#first serial, iclass 26, count 0 2006.183.08:21:02.61#ibcon#enter sib2, iclass 26, count 0 2006.183.08:21:02.61#ibcon#flushed, iclass 26, count 0 2006.183.08:21:02.61#ibcon#about to write, iclass 26, count 0 2006.183.08:21:02.61#ibcon#wrote, iclass 26, count 0 2006.183.08:21:02.61#ibcon#about to read 3, iclass 26, count 0 2006.183.08:21:02.63#ibcon#read 3, iclass 26, count 0 2006.183.08:21:02.63#ibcon#about to read 4, iclass 26, count 0 2006.183.08:21:02.63#ibcon#read 4, iclass 26, count 0 2006.183.08:21:02.63#ibcon#about to read 5, iclass 26, count 0 2006.183.08:21:02.63#ibcon#read 5, iclass 26, count 0 2006.183.08:21:02.63#ibcon#about to read 6, iclass 26, count 0 2006.183.08:21:02.63#ibcon#read 6, iclass 26, count 0 2006.183.08:21:02.63#ibcon#end of sib2, iclass 26, count 0 2006.183.08:21:02.63#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:21:02.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:21:02.63#ibcon#[27=USB\r\n] 2006.183.08:21:02.63#ibcon#*before write, iclass 26, count 0 2006.183.08:21:02.63#ibcon#enter sib2, iclass 26, count 0 2006.183.08:21:02.63#ibcon#flushed, iclass 26, count 0 2006.183.08:21:02.63#ibcon#about to write, iclass 26, count 0 2006.183.08:21:02.63#ibcon#wrote, iclass 26, count 0 2006.183.08:21:02.63#ibcon#about to read 3, iclass 26, count 0 2006.183.08:21:02.66#ibcon#read 3, iclass 26, count 0 2006.183.08:21:02.66#ibcon#about to read 4, iclass 26, count 0 2006.183.08:21:02.66#ibcon#read 4, iclass 26, count 0 2006.183.08:21:02.66#ibcon#about to read 5, iclass 26, count 0 2006.183.08:21:02.66#ibcon#read 5, iclass 26, count 0 2006.183.08:21:02.66#ibcon#about to read 6, iclass 26, count 0 2006.183.08:21:02.66#ibcon#read 6, iclass 26, count 0 2006.183.08:21:02.66#ibcon#end of sib2, iclass 26, count 0 2006.183.08:21:02.66#ibcon#*after write, iclass 26, count 0 2006.183.08:21:02.66#ibcon#*before return 0, iclass 26, count 0 2006.183.08:21:02.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:21:02.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.183.08:21:02.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:21:02.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:21:02.66$vc4f8/vabw=wide 2006.183.08:21:02.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:21:02.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:21:02.66#ibcon#ireg 8 cls_cnt 0 2006.183.08:21:02.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:21:02.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:21:02.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:21:02.66#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:21:02.66#ibcon#first serial, iclass 28, count 0 2006.183.08:21:02.66#ibcon#enter sib2, iclass 28, count 0 2006.183.08:21:02.66#ibcon#flushed, iclass 28, count 0 2006.183.08:21:02.66#ibcon#about to write, iclass 28, count 0 2006.183.08:21:02.66#ibcon#wrote, iclass 28, count 0 2006.183.08:21:02.66#ibcon#about to read 3, iclass 28, count 0 2006.183.08:21:02.69#ibcon#read 3, iclass 28, count 0 2006.183.08:21:02.69#ibcon#about to read 4, iclass 28, count 0 2006.183.08:21:02.69#ibcon#read 4, iclass 28, count 0 2006.183.08:21:02.69#ibcon#about to read 5, iclass 28, count 0 2006.183.08:21:02.69#ibcon#read 5, iclass 28, count 0 2006.183.08:21:02.69#ibcon#about to read 6, iclass 28, count 0 2006.183.08:21:02.69#ibcon#read 6, iclass 28, count 0 2006.183.08:21:02.69#ibcon#end of sib2, iclass 28, count 0 2006.183.08:21:02.69#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:21:02.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:21:02.69#ibcon#[25=BW32\r\n] 2006.183.08:21:02.69#ibcon#*before write, iclass 28, count 0 2006.183.08:21:02.69#ibcon#enter sib2, iclass 28, count 0 2006.183.08:21:02.69#ibcon#flushed, iclass 28, count 0 2006.183.08:21:02.69#ibcon#about to write, iclass 28, count 0 2006.183.08:21:02.69#ibcon#wrote, iclass 28, count 0 2006.183.08:21:02.69#ibcon#about to read 3, iclass 28, count 0 2006.183.08:21:02.72#ibcon#read 3, iclass 28, count 0 2006.183.08:21:02.72#ibcon#about to read 4, iclass 28, count 0 2006.183.08:21:02.72#ibcon#read 4, iclass 28, count 0 2006.183.08:21:02.72#ibcon#about to read 5, iclass 28, count 0 2006.183.08:21:02.72#ibcon#read 5, iclass 28, count 0 2006.183.08:21:02.72#ibcon#about to read 6, iclass 28, count 0 2006.183.08:21:02.72#ibcon#read 6, iclass 28, count 0 2006.183.08:21:02.72#ibcon#end of sib2, iclass 28, count 0 2006.183.08:21:02.72#ibcon#*after write, iclass 28, count 0 2006.183.08:21:02.72#ibcon#*before return 0, iclass 28, count 0 2006.183.08:21:02.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:21:02.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:21:02.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:21:02.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:21:02.72$vc4f8/vbbw=wide 2006.183.08:21:02.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:21:02.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:21:02.72#ibcon#ireg 8 cls_cnt 0 2006.183.08:21:02.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:21:02.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:21:02.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:21:02.78#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:21:02.78#ibcon#first serial, iclass 30, count 0 2006.183.08:21:02.78#ibcon#enter sib2, iclass 30, count 0 2006.183.08:21:02.78#ibcon#flushed, iclass 30, count 0 2006.183.08:21:02.78#ibcon#about to write, iclass 30, count 0 2006.183.08:21:02.78#ibcon#wrote, iclass 30, count 0 2006.183.08:21:02.78#ibcon#about to read 3, iclass 30, count 0 2006.183.08:21:02.80#ibcon#read 3, iclass 30, count 0 2006.183.08:21:02.80#ibcon#about to read 4, iclass 30, count 0 2006.183.08:21:02.80#ibcon#read 4, iclass 30, count 0 2006.183.08:21:02.80#ibcon#about to read 5, iclass 30, count 0 2006.183.08:21:02.80#ibcon#read 5, iclass 30, count 0 2006.183.08:21:02.80#ibcon#about to read 6, iclass 30, count 0 2006.183.08:21:02.80#ibcon#read 6, iclass 30, count 0 2006.183.08:21:02.80#ibcon#end of sib2, iclass 30, count 0 2006.183.08:21:02.80#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:21:02.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:21:02.80#ibcon#[27=BW32\r\n] 2006.183.08:21:02.80#ibcon#*before write, iclass 30, count 0 2006.183.08:21:02.80#ibcon#enter sib2, iclass 30, count 0 2006.183.08:21:02.80#ibcon#flushed, iclass 30, count 0 2006.183.08:21:02.80#ibcon#about to write, iclass 30, count 0 2006.183.08:21:02.80#ibcon#wrote, iclass 30, count 0 2006.183.08:21:02.80#ibcon#about to read 3, iclass 30, count 0 2006.183.08:21:02.83#ibcon#read 3, iclass 30, count 0 2006.183.08:21:02.83#ibcon#about to read 4, iclass 30, count 0 2006.183.08:21:02.83#ibcon#read 4, iclass 30, count 0 2006.183.08:21:02.83#ibcon#about to read 5, iclass 30, count 0 2006.183.08:21:02.83#ibcon#read 5, iclass 30, count 0 2006.183.08:21:02.83#ibcon#about to read 6, iclass 30, count 0 2006.183.08:21:02.83#ibcon#read 6, iclass 30, count 0 2006.183.08:21:02.83#ibcon#end of sib2, iclass 30, count 0 2006.183.08:21:02.83#ibcon#*after write, iclass 30, count 0 2006.183.08:21:02.83#ibcon#*before return 0, iclass 30, count 0 2006.183.08:21:02.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:21:02.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:21:02.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:21:02.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:21:02.83$4f8m12a/ifd4f 2006.183.08:21:02.83$ifd4f/lo= 2006.183.08:21:02.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:21:02.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:21:02.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:21:02.83$ifd4f/patch= 2006.183.08:21:02.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:21:02.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:21:02.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:21:02.83$4f8m12a/"form=m,16.000,1:2 2006.183.08:21:02.83$4f8m12a/"tpicd 2006.183.08:21:02.83$4f8m12a/echo=off 2006.183.08:21:02.83$4f8m12a/xlog=off 2006.183.08:21:02.83:!2006.183.08:23:10 2006.183.08:21:12.14#trakl#Source acquired 2006.183.08:21:12.14#flagr#flagr/antenna,acquired 2006.183.08:23:10.00:preob 2006.183.08:23:10.13/onsource/TRACKING 2006.183.08:23:10.13:!2006.183.08:23:20 2006.183.08:23:20.00:data_valid=on 2006.183.08:23:20.00:midob 2006.183.08:23:21.13/onsource/TRACKING 2006.183.08:23:21.13/wx/28.28,996.7,87 2006.183.08:23:21.21/cable/+6.4510E-03 2006.183.08:23:22.30/va/01,08,usb,yes,33,35 2006.183.08:23:22.30/va/02,07,usb,yes,33,35 2006.183.08:23:22.30/va/03,06,usb,yes,35,35 2006.183.08:23:22.30/va/04,07,usb,yes,34,36 2006.183.08:23:22.30/va/05,07,usb,yes,36,38 2006.183.08:23:22.30/va/06,06,usb,yes,35,35 2006.183.08:23:22.30/va/07,06,usb,yes,35,35 2006.183.08:23:22.30/va/08,07,usb,yes,34,33 2006.183.08:23:22.53/valo/01,532.99,yes,locked 2006.183.08:23:22.53/valo/02,572.99,yes,locked 2006.183.08:23:22.53/valo/03,672.99,yes,locked 2006.183.08:23:22.53/valo/04,832.99,yes,locked 2006.183.08:23:22.53/valo/05,652.99,yes,locked 2006.183.08:23:22.53/valo/06,772.99,yes,locked 2006.183.08:23:22.53/valo/07,832.99,yes,locked 2006.183.08:23:22.53/valo/08,852.99,yes,locked 2006.183.08:23:23.62/vb/01,04,usb,yes,31,30 2006.183.08:23:23.62/vb/02,04,usb,yes,33,34 2006.183.08:23:23.62/vb/03,04,usb,yes,29,33 2006.183.08:23:23.62/vb/04,04,usb,yes,30,30 2006.183.08:23:23.62/vb/05,04,usb,yes,29,33 2006.183.08:23:23.62/vb/06,04,usb,yes,30,32 2006.183.08:23:23.62/vb/07,04,usb,yes,32,32 2006.183.08:23:23.62/vb/08,04,usb,yes,29,33 2006.183.08:23:23.85/vblo/01,632.99,yes,locked 2006.183.08:23:23.85/vblo/02,640.99,yes,locked 2006.183.08:23:23.85/vblo/03,656.99,yes,locked 2006.183.08:23:23.85/vblo/04,712.99,yes,locked 2006.183.08:23:23.85/vblo/05,744.99,yes,locked 2006.183.08:23:23.85/vblo/06,752.99,yes,locked 2006.183.08:23:23.85/vblo/07,734.99,yes,locked 2006.183.08:23:23.85/vblo/08,744.99,yes,locked 2006.183.08:23:24.00/vabw/8 2006.183.08:23:24.15/vbbw/8 2006.183.08:23:24.24/xfe/off,on,14.5 2006.183.08:23:24.61/ifatt/23,28,28,28 2006.183.08:23:25.08/fmout-gps/S +3.36E-07 2006.183.08:23:25.16:!2006.183.08:24:20 2006.183.08:24:20.01:data_valid=off 2006.183.08:24:20.02:postob 2006.183.08:24:20.17/cable/+6.4500E-03 2006.183.08:24:20.21/wx/28.27,996.7,87 2006.183.08:24:21.07/fmout-gps/S +3.35E-07 2006.183.08:24:21.07:scan_name=183-0825,k06183,60 2006.183.08:24:21.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.183.08:24:21.13#flagr#flagr/antenna,new-source 2006.183.08:24:22.13:checkk5 2006.183.08:24:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:24:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:24:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:24:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:24:24.00/chk_obsdata//k5ts1/T1830823??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:24:24.38/chk_obsdata//k5ts2/T1830823??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:24:24.74/chk_obsdata//k5ts3/T1830823??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:24:25.11/chk_obsdata//k5ts4/T1830823??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:24:25.80/k5log//k5ts1_log_newline 2006.183.08:24:26.48/k5log//k5ts2_log_newline 2006.183.08:24:27.17/k5log//k5ts3_log_newline 2006.183.08:24:27.86/k5log//k5ts4_log_newline 2006.183.08:24:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:24:27.88:4f8m12a=3 2006.183.08:24:27.88$4f8m12a/echo=on 2006.183.08:24:27.88$4f8m12a/pcalon 2006.183.08:24:27.88$pcalon/"no phase cal control is implemented here 2006.183.08:24:27.89$4f8m12a/"tpicd=stop 2006.183.08:24:27.89$4f8m12a/vc4f8 2006.183.08:24:27.89$vc4f8/valo=1,532.99 2006.183.08:24:27.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:24:27.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:24:27.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:27.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:27.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:27.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:27.89#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:24:27.89#ibcon#first serial, iclass 3, count 0 2006.183.08:24:27.89#ibcon#enter sib2, iclass 3, count 0 2006.183.08:24:27.89#ibcon#flushed, iclass 3, count 0 2006.183.08:24:27.89#ibcon#about to write, iclass 3, count 0 2006.183.08:24:27.89#ibcon#wrote, iclass 3, count 0 2006.183.08:24:27.89#ibcon#about to read 3, iclass 3, count 0 2006.183.08:24:27.90#ibcon#read 3, iclass 3, count 0 2006.183.08:24:27.90#ibcon#about to read 4, iclass 3, count 0 2006.183.08:24:27.90#ibcon#read 4, iclass 3, count 0 2006.183.08:24:27.90#ibcon#about to read 5, iclass 3, count 0 2006.183.08:24:27.90#ibcon#read 5, iclass 3, count 0 2006.183.08:24:27.90#ibcon#about to read 6, iclass 3, count 0 2006.183.08:24:27.90#ibcon#read 6, iclass 3, count 0 2006.183.08:24:27.90#ibcon#end of sib2, iclass 3, count 0 2006.183.08:24:27.90#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:24:27.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:24:27.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:24:27.90#ibcon#*before write, iclass 3, count 0 2006.183.08:24:27.90#ibcon#enter sib2, iclass 3, count 0 2006.183.08:24:27.90#ibcon#flushed, iclass 3, count 0 2006.183.08:24:27.90#ibcon#about to write, iclass 3, count 0 2006.183.08:24:27.90#ibcon#wrote, iclass 3, count 0 2006.183.08:24:27.90#ibcon#about to read 3, iclass 3, count 0 2006.183.08:24:27.95#ibcon#read 3, iclass 3, count 0 2006.183.08:24:27.95#ibcon#about to read 4, iclass 3, count 0 2006.183.08:24:27.95#ibcon#read 4, iclass 3, count 0 2006.183.08:24:27.95#ibcon#about to read 5, iclass 3, count 0 2006.183.08:24:27.95#ibcon#read 5, iclass 3, count 0 2006.183.08:24:27.95#ibcon#about to read 6, iclass 3, count 0 2006.183.08:24:27.95#ibcon#read 6, iclass 3, count 0 2006.183.08:24:27.95#ibcon#end of sib2, iclass 3, count 0 2006.183.08:24:27.95#ibcon#*after write, iclass 3, count 0 2006.183.08:24:27.95#ibcon#*before return 0, iclass 3, count 0 2006.183.08:24:27.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:27.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:27.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:24:27.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:24:27.95$vc4f8/va=1,8 2006.183.08:24:27.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.08:24:27.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.08:24:27.95#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:27.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:27.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:27.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:27.95#ibcon#enter wrdev, iclass 5, count 2 2006.183.08:24:27.95#ibcon#first serial, iclass 5, count 2 2006.183.08:24:27.95#ibcon#enter sib2, iclass 5, count 2 2006.183.08:24:27.95#ibcon#flushed, iclass 5, count 2 2006.183.08:24:27.95#ibcon#about to write, iclass 5, count 2 2006.183.08:24:27.95#ibcon#wrote, iclass 5, count 2 2006.183.08:24:27.95#ibcon#about to read 3, iclass 5, count 2 2006.183.08:24:27.97#ibcon#read 3, iclass 5, count 2 2006.183.08:24:27.97#ibcon#about to read 4, iclass 5, count 2 2006.183.08:24:27.97#ibcon#read 4, iclass 5, count 2 2006.183.08:24:27.97#ibcon#about to read 5, iclass 5, count 2 2006.183.08:24:27.97#ibcon#read 5, iclass 5, count 2 2006.183.08:24:27.97#ibcon#about to read 6, iclass 5, count 2 2006.183.08:24:27.97#ibcon#read 6, iclass 5, count 2 2006.183.08:24:27.97#ibcon#end of sib2, iclass 5, count 2 2006.183.08:24:27.97#ibcon#*mode == 0, iclass 5, count 2 2006.183.08:24:27.97#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.08:24:27.97#ibcon#[25=AT01-08\r\n] 2006.183.08:24:27.97#ibcon#*before write, iclass 5, count 2 2006.183.08:24:27.97#ibcon#enter sib2, iclass 5, count 2 2006.183.08:24:27.97#ibcon#flushed, iclass 5, count 2 2006.183.08:24:27.97#ibcon#about to write, iclass 5, count 2 2006.183.08:24:27.97#ibcon#wrote, iclass 5, count 2 2006.183.08:24:27.97#ibcon#about to read 3, iclass 5, count 2 2006.183.08:24:28.00#ibcon#read 3, iclass 5, count 2 2006.183.08:24:28.00#ibcon#about to read 4, iclass 5, count 2 2006.183.08:24:28.00#ibcon#read 4, iclass 5, count 2 2006.183.08:24:28.00#ibcon#about to read 5, iclass 5, count 2 2006.183.08:24:28.00#ibcon#read 5, iclass 5, count 2 2006.183.08:24:28.00#ibcon#about to read 6, iclass 5, count 2 2006.183.08:24:28.00#ibcon#read 6, iclass 5, count 2 2006.183.08:24:28.01#ibcon#end of sib2, iclass 5, count 2 2006.183.08:24:28.01#ibcon#*after write, iclass 5, count 2 2006.183.08:24:28.01#ibcon#*before return 0, iclass 5, count 2 2006.183.08:24:28.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:28.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:28.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.08:24:28.01#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:28.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:28.12#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:28.12#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:28.12#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:24:28.12#ibcon#first serial, iclass 5, count 0 2006.183.08:24:28.12#ibcon#enter sib2, iclass 5, count 0 2006.183.08:24:28.12#ibcon#flushed, iclass 5, count 0 2006.183.08:24:28.12#ibcon#about to write, iclass 5, count 0 2006.183.08:24:28.12#ibcon#wrote, iclass 5, count 0 2006.183.08:24:28.12#ibcon#about to read 3, iclass 5, count 0 2006.183.08:24:28.14#ibcon#read 3, iclass 5, count 0 2006.183.08:24:28.14#ibcon#about to read 4, iclass 5, count 0 2006.183.08:24:28.14#ibcon#read 4, iclass 5, count 0 2006.183.08:24:28.14#ibcon#about to read 5, iclass 5, count 0 2006.183.08:24:28.14#ibcon#read 5, iclass 5, count 0 2006.183.08:24:28.14#ibcon#about to read 6, iclass 5, count 0 2006.183.08:24:28.14#ibcon#read 6, iclass 5, count 0 2006.183.08:24:28.14#ibcon#end of sib2, iclass 5, count 0 2006.183.08:24:28.14#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:24:28.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:24:28.14#ibcon#[25=USB\r\n] 2006.183.08:24:28.14#ibcon#*before write, iclass 5, count 0 2006.183.08:24:28.14#ibcon#enter sib2, iclass 5, count 0 2006.183.08:24:28.14#ibcon#flushed, iclass 5, count 0 2006.183.08:24:28.14#ibcon#about to write, iclass 5, count 0 2006.183.08:24:28.14#ibcon#wrote, iclass 5, count 0 2006.183.08:24:28.14#ibcon#about to read 3, iclass 5, count 0 2006.183.08:24:28.17#ibcon#read 3, iclass 5, count 0 2006.183.08:24:28.17#ibcon#about to read 4, iclass 5, count 0 2006.183.08:24:28.17#ibcon#read 4, iclass 5, count 0 2006.183.08:24:28.17#ibcon#about to read 5, iclass 5, count 0 2006.183.08:24:28.17#ibcon#read 5, iclass 5, count 0 2006.183.08:24:28.17#ibcon#about to read 6, iclass 5, count 0 2006.183.08:24:28.17#ibcon#read 6, iclass 5, count 0 2006.183.08:24:28.17#ibcon#end of sib2, iclass 5, count 0 2006.183.08:24:28.17#ibcon#*after write, iclass 5, count 0 2006.183.08:24:28.17#ibcon#*before return 0, iclass 5, count 0 2006.183.08:24:28.17#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:28.17#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:28.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:24:28.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:24:28.17$vc4f8/valo=2,572.99 2006.183.08:24:28.17#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.08:24:28.17#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.08:24:28.17#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:28.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:28.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:28.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:28.17#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:24:28.17#ibcon#first serial, iclass 7, count 0 2006.183.08:24:28.17#ibcon#enter sib2, iclass 7, count 0 2006.183.08:24:28.17#ibcon#flushed, iclass 7, count 0 2006.183.08:24:28.17#ibcon#about to write, iclass 7, count 0 2006.183.08:24:28.17#ibcon#wrote, iclass 7, count 0 2006.183.08:24:28.17#ibcon#about to read 3, iclass 7, count 0 2006.183.08:24:28.20#ibcon#read 3, iclass 7, count 0 2006.183.08:24:28.20#ibcon#about to read 4, iclass 7, count 0 2006.183.08:24:28.20#ibcon#read 4, iclass 7, count 0 2006.183.08:24:28.20#ibcon#about to read 5, iclass 7, count 0 2006.183.08:24:28.20#ibcon#read 5, iclass 7, count 0 2006.183.08:24:28.20#ibcon#about to read 6, iclass 7, count 0 2006.183.08:24:28.20#ibcon#read 6, iclass 7, count 0 2006.183.08:24:28.20#ibcon#end of sib2, iclass 7, count 0 2006.183.08:24:28.20#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:24:28.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:24:28.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:24:28.20#ibcon#*before write, iclass 7, count 0 2006.183.08:24:28.20#ibcon#enter sib2, iclass 7, count 0 2006.183.08:24:28.20#ibcon#flushed, iclass 7, count 0 2006.183.08:24:28.20#ibcon#about to write, iclass 7, count 0 2006.183.08:24:28.20#ibcon#wrote, iclass 7, count 0 2006.183.08:24:28.20#ibcon#about to read 3, iclass 7, count 0 2006.183.08:24:28.24#ibcon#read 3, iclass 7, count 0 2006.183.08:24:28.24#ibcon#about to read 4, iclass 7, count 0 2006.183.08:24:28.24#ibcon#read 4, iclass 7, count 0 2006.183.08:24:28.24#ibcon#about to read 5, iclass 7, count 0 2006.183.08:24:28.24#ibcon#read 5, iclass 7, count 0 2006.183.08:24:28.24#ibcon#about to read 6, iclass 7, count 0 2006.183.08:24:28.24#ibcon#read 6, iclass 7, count 0 2006.183.08:24:28.24#ibcon#end of sib2, iclass 7, count 0 2006.183.08:24:28.24#ibcon#*after write, iclass 7, count 0 2006.183.08:24:28.24#ibcon#*before return 0, iclass 7, count 0 2006.183.08:24:28.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:28.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:28.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:24:28.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:24:28.24$vc4f8/va=2,7 2006.183.08:24:28.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.08:24:28.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.08:24:28.24#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:28.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:28.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:28.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:28.29#ibcon#enter wrdev, iclass 11, count 2 2006.183.08:24:28.29#ibcon#first serial, iclass 11, count 2 2006.183.08:24:28.29#ibcon#enter sib2, iclass 11, count 2 2006.183.08:24:28.29#ibcon#flushed, iclass 11, count 2 2006.183.08:24:28.29#ibcon#about to write, iclass 11, count 2 2006.183.08:24:28.29#ibcon#wrote, iclass 11, count 2 2006.183.08:24:28.29#ibcon#about to read 3, iclass 11, count 2 2006.183.08:24:28.31#ibcon#read 3, iclass 11, count 2 2006.183.08:24:28.31#ibcon#about to read 4, iclass 11, count 2 2006.183.08:24:28.31#ibcon#read 4, iclass 11, count 2 2006.183.08:24:28.31#ibcon#about to read 5, iclass 11, count 2 2006.183.08:24:28.31#ibcon#read 5, iclass 11, count 2 2006.183.08:24:28.31#ibcon#about to read 6, iclass 11, count 2 2006.183.08:24:28.31#ibcon#read 6, iclass 11, count 2 2006.183.08:24:28.31#ibcon#end of sib2, iclass 11, count 2 2006.183.08:24:28.31#ibcon#*mode == 0, iclass 11, count 2 2006.183.08:24:28.31#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.08:24:28.31#ibcon#[25=AT02-07\r\n] 2006.183.08:24:28.31#ibcon#*before write, iclass 11, count 2 2006.183.08:24:28.31#ibcon#enter sib2, iclass 11, count 2 2006.183.08:24:28.31#ibcon#flushed, iclass 11, count 2 2006.183.08:24:28.31#ibcon#about to write, iclass 11, count 2 2006.183.08:24:28.31#ibcon#wrote, iclass 11, count 2 2006.183.08:24:28.31#ibcon#about to read 3, iclass 11, count 2 2006.183.08:24:28.34#ibcon#read 3, iclass 11, count 2 2006.183.08:24:28.34#ibcon#about to read 4, iclass 11, count 2 2006.183.08:24:28.34#ibcon#read 4, iclass 11, count 2 2006.183.08:24:28.34#ibcon#about to read 5, iclass 11, count 2 2006.183.08:24:28.34#ibcon#read 5, iclass 11, count 2 2006.183.08:24:28.34#ibcon#about to read 6, iclass 11, count 2 2006.183.08:24:28.34#ibcon#read 6, iclass 11, count 2 2006.183.08:24:28.34#ibcon#end of sib2, iclass 11, count 2 2006.183.08:24:28.34#ibcon#*after write, iclass 11, count 2 2006.183.08:24:28.34#ibcon#*before return 0, iclass 11, count 2 2006.183.08:24:28.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:28.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:28.34#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.08:24:28.34#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:28.34#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:28.46#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:28.46#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:28.46#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:24:28.46#ibcon#first serial, iclass 11, count 0 2006.183.08:24:28.46#ibcon#enter sib2, iclass 11, count 0 2006.183.08:24:28.46#ibcon#flushed, iclass 11, count 0 2006.183.08:24:28.46#ibcon#about to write, iclass 11, count 0 2006.183.08:24:28.46#ibcon#wrote, iclass 11, count 0 2006.183.08:24:28.46#ibcon#about to read 3, iclass 11, count 0 2006.183.08:24:28.48#ibcon#read 3, iclass 11, count 0 2006.183.08:24:28.48#ibcon#about to read 4, iclass 11, count 0 2006.183.08:24:28.48#ibcon#read 4, iclass 11, count 0 2006.183.08:24:28.48#ibcon#about to read 5, iclass 11, count 0 2006.183.08:24:28.48#ibcon#read 5, iclass 11, count 0 2006.183.08:24:28.48#ibcon#about to read 6, iclass 11, count 0 2006.183.08:24:28.48#ibcon#read 6, iclass 11, count 0 2006.183.08:24:28.48#ibcon#end of sib2, iclass 11, count 0 2006.183.08:24:28.48#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:24:28.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:24:28.48#ibcon#[25=USB\r\n] 2006.183.08:24:28.48#ibcon#*before write, iclass 11, count 0 2006.183.08:24:28.48#ibcon#enter sib2, iclass 11, count 0 2006.183.08:24:28.48#ibcon#flushed, iclass 11, count 0 2006.183.08:24:28.48#ibcon#about to write, iclass 11, count 0 2006.183.08:24:28.48#ibcon#wrote, iclass 11, count 0 2006.183.08:24:28.48#ibcon#about to read 3, iclass 11, count 0 2006.183.08:24:28.51#ibcon#read 3, iclass 11, count 0 2006.183.08:24:28.51#ibcon#about to read 4, iclass 11, count 0 2006.183.08:24:28.51#ibcon#read 4, iclass 11, count 0 2006.183.08:24:28.51#ibcon#about to read 5, iclass 11, count 0 2006.183.08:24:28.51#ibcon#read 5, iclass 11, count 0 2006.183.08:24:28.51#ibcon#about to read 6, iclass 11, count 0 2006.183.08:24:28.51#ibcon#read 6, iclass 11, count 0 2006.183.08:24:28.51#ibcon#end of sib2, iclass 11, count 0 2006.183.08:24:28.51#ibcon#*after write, iclass 11, count 0 2006.183.08:24:28.51#ibcon#*before return 0, iclass 11, count 0 2006.183.08:24:28.51#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:28.51#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:28.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:24:28.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:24:28.51$vc4f8/valo=3,672.99 2006.183.08:24:28.51#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.08:24:28.51#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.08:24:28.51#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:28.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:28.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:28.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:28.51#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:24:28.51#ibcon#first serial, iclass 13, count 0 2006.183.08:24:28.51#ibcon#enter sib2, iclass 13, count 0 2006.183.08:24:28.51#ibcon#flushed, iclass 13, count 0 2006.183.08:24:28.51#ibcon#about to write, iclass 13, count 0 2006.183.08:24:28.51#ibcon#wrote, iclass 13, count 0 2006.183.08:24:28.51#ibcon#about to read 3, iclass 13, count 0 2006.183.08:24:28.54#ibcon#read 3, iclass 13, count 0 2006.183.08:24:28.54#ibcon#about to read 4, iclass 13, count 0 2006.183.08:24:28.54#ibcon#read 4, iclass 13, count 0 2006.183.08:24:28.54#ibcon#about to read 5, iclass 13, count 0 2006.183.08:24:28.54#ibcon#read 5, iclass 13, count 0 2006.183.08:24:28.54#ibcon#about to read 6, iclass 13, count 0 2006.183.08:24:28.54#ibcon#read 6, iclass 13, count 0 2006.183.08:24:28.54#ibcon#end of sib2, iclass 13, count 0 2006.183.08:24:28.54#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:24:28.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:24:28.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:24:28.54#ibcon#*before write, iclass 13, count 0 2006.183.08:24:28.54#ibcon#enter sib2, iclass 13, count 0 2006.183.08:24:28.54#ibcon#flushed, iclass 13, count 0 2006.183.08:24:28.54#ibcon#about to write, iclass 13, count 0 2006.183.08:24:28.54#ibcon#wrote, iclass 13, count 0 2006.183.08:24:28.54#ibcon#about to read 3, iclass 13, count 0 2006.183.08:24:28.58#ibcon#read 3, iclass 13, count 0 2006.183.08:24:28.58#ibcon#about to read 4, iclass 13, count 0 2006.183.08:24:28.58#ibcon#read 4, iclass 13, count 0 2006.183.08:24:28.58#ibcon#about to read 5, iclass 13, count 0 2006.183.08:24:28.58#ibcon#read 5, iclass 13, count 0 2006.183.08:24:28.58#ibcon#about to read 6, iclass 13, count 0 2006.183.08:24:28.58#ibcon#read 6, iclass 13, count 0 2006.183.08:24:28.58#ibcon#end of sib2, iclass 13, count 0 2006.183.08:24:28.58#ibcon#*after write, iclass 13, count 0 2006.183.08:24:28.58#ibcon#*before return 0, iclass 13, count 0 2006.183.08:24:28.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:28.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:28.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:24:28.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:24:28.58$vc4f8/va=3,6 2006.183.08:24:28.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.08:24:28.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.08:24:28.58#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:28.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:28.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:28.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:28.63#ibcon#enter wrdev, iclass 15, count 2 2006.183.08:24:28.63#ibcon#first serial, iclass 15, count 2 2006.183.08:24:28.63#ibcon#enter sib2, iclass 15, count 2 2006.183.08:24:28.63#ibcon#flushed, iclass 15, count 2 2006.183.08:24:28.63#ibcon#about to write, iclass 15, count 2 2006.183.08:24:28.63#ibcon#wrote, iclass 15, count 2 2006.183.08:24:28.63#ibcon#about to read 3, iclass 15, count 2 2006.183.08:24:28.65#ibcon#read 3, iclass 15, count 2 2006.183.08:24:28.65#ibcon#about to read 4, iclass 15, count 2 2006.183.08:24:28.65#ibcon#read 4, iclass 15, count 2 2006.183.08:24:28.65#ibcon#about to read 5, iclass 15, count 2 2006.183.08:24:28.65#ibcon#read 5, iclass 15, count 2 2006.183.08:24:28.65#ibcon#about to read 6, iclass 15, count 2 2006.183.08:24:28.65#ibcon#read 6, iclass 15, count 2 2006.183.08:24:28.65#ibcon#end of sib2, iclass 15, count 2 2006.183.08:24:28.65#ibcon#*mode == 0, iclass 15, count 2 2006.183.08:24:28.65#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.08:24:28.65#ibcon#[25=AT03-06\r\n] 2006.183.08:24:28.65#ibcon#*before write, iclass 15, count 2 2006.183.08:24:28.65#ibcon#enter sib2, iclass 15, count 2 2006.183.08:24:28.65#ibcon#flushed, iclass 15, count 2 2006.183.08:24:28.65#ibcon#about to write, iclass 15, count 2 2006.183.08:24:28.65#ibcon#wrote, iclass 15, count 2 2006.183.08:24:28.65#ibcon#about to read 3, iclass 15, count 2 2006.183.08:24:28.68#ibcon#read 3, iclass 15, count 2 2006.183.08:24:28.68#ibcon#about to read 4, iclass 15, count 2 2006.183.08:24:28.68#ibcon#read 4, iclass 15, count 2 2006.183.08:24:28.68#ibcon#about to read 5, iclass 15, count 2 2006.183.08:24:28.68#ibcon#read 5, iclass 15, count 2 2006.183.08:24:28.68#ibcon#about to read 6, iclass 15, count 2 2006.183.08:24:28.68#ibcon#read 6, iclass 15, count 2 2006.183.08:24:28.68#ibcon#end of sib2, iclass 15, count 2 2006.183.08:24:28.68#ibcon#*after write, iclass 15, count 2 2006.183.08:24:28.68#ibcon#*before return 0, iclass 15, count 2 2006.183.08:24:28.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:28.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:28.68#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.08:24:28.68#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:28.68#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:28.80#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:28.80#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:28.80#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:24:28.80#ibcon#first serial, iclass 15, count 0 2006.183.08:24:28.80#ibcon#enter sib2, iclass 15, count 0 2006.183.08:24:28.80#ibcon#flushed, iclass 15, count 0 2006.183.08:24:28.80#ibcon#about to write, iclass 15, count 0 2006.183.08:24:28.80#ibcon#wrote, iclass 15, count 0 2006.183.08:24:28.80#ibcon#about to read 3, iclass 15, count 0 2006.183.08:24:28.82#ibcon#read 3, iclass 15, count 0 2006.183.08:24:28.82#ibcon#about to read 4, iclass 15, count 0 2006.183.08:24:28.82#ibcon#read 4, iclass 15, count 0 2006.183.08:24:28.82#ibcon#about to read 5, iclass 15, count 0 2006.183.08:24:28.82#ibcon#read 5, iclass 15, count 0 2006.183.08:24:28.82#ibcon#about to read 6, iclass 15, count 0 2006.183.08:24:28.82#ibcon#read 6, iclass 15, count 0 2006.183.08:24:28.82#ibcon#end of sib2, iclass 15, count 0 2006.183.08:24:28.82#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:24:28.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:24:28.82#ibcon#[25=USB\r\n] 2006.183.08:24:28.82#ibcon#*before write, iclass 15, count 0 2006.183.08:24:28.82#ibcon#enter sib2, iclass 15, count 0 2006.183.08:24:28.82#ibcon#flushed, iclass 15, count 0 2006.183.08:24:28.82#ibcon#about to write, iclass 15, count 0 2006.183.08:24:28.82#ibcon#wrote, iclass 15, count 0 2006.183.08:24:28.82#ibcon#about to read 3, iclass 15, count 0 2006.183.08:24:28.85#ibcon#read 3, iclass 15, count 0 2006.183.08:24:28.85#ibcon#about to read 4, iclass 15, count 0 2006.183.08:24:28.85#ibcon#read 4, iclass 15, count 0 2006.183.08:24:28.85#ibcon#about to read 5, iclass 15, count 0 2006.183.08:24:28.85#ibcon#read 5, iclass 15, count 0 2006.183.08:24:28.85#ibcon#about to read 6, iclass 15, count 0 2006.183.08:24:28.85#ibcon#read 6, iclass 15, count 0 2006.183.08:24:28.85#ibcon#end of sib2, iclass 15, count 0 2006.183.08:24:28.85#ibcon#*after write, iclass 15, count 0 2006.183.08:24:28.85#ibcon#*before return 0, iclass 15, count 0 2006.183.08:24:28.85#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:28.85#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:28.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:24:28.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:24:28.85$vc4f8/valo=4,832.99 2006.183.08:24:28.85#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.08:24:28.85#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.08:24:28.85#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:28.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:28.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:28.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:28.85#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:24:28.85#ibcon#first serial, iclass 17, count 0 2006.183.08:24:28.85#ibcon#enter sib2, iclass 17, count 0 2006.183.08:24:28.85#ibcon#flushed, iclass 17, count 0 2006.183.08:24:28.85#ibcon#about to write, iclass 17, count 0 2006.183.08:24:28.85#ibcon#wrote, iclass 17, count 0 2006.183.08:24:28.85#ibcon#about to read 3, iclass 17, count 0 2006.183.08:24:28.88#ibcon#read 3, iclass 17, count 0 2006.183.08:24:28.88#ibcon#about to read 4, iclass 17, count 0 2006.183.08:24:28.88#ibcon#read 4, iclass 17, count 0 2006.183.08:24:28.88#ibcon#about to read 5, iclass 17, count 0 2006.183.08:24:28.88#ibcon#read 5, iclass 17, count 0 2006.183.08:24:28.88#ibcon#about to read 6, iclass 17, count 0 2006.183.08:24:28.88#ibcon#read 6, iclass 17, count 0 2006.183.08:24:28.88#ibcon#end of sib2, iclass 17, count 0 2006.183.08:24:28.88#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:24:28.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:24:28.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:24:28.88#ibcon#*before write, iclass 17, count 0 2006.183.08:24:28.88#ibcon#enter sib2, iclass 17, count 0 2006.183.08:24:28.88#ibcon#flushed, iclass 17, count 0 2006.183.08:24:28.88#ibcon#about to write, iclass 17, count 0 2006.183.08:24:28.88#ibcon#wrote, iclass 17, count 0 2006.183.08:24:28.88#ibcon#about to read 3, iclass 17, count 0 2006.183.08:24:28.92#ibcon#read 3, iclass 17, count 0 2006.183.08:24:28.92#ibcon#about to read 4, iclass 17, count 0 2006.183.08:24:28.92#ibcon#read 4, iclass 17, count 0 2006.183.08:24:28.92#ibcon#about to read 5, iclass 17, count 0 2006.183.08:24:28.92#ibcon#read 5, iclass 17, count 0 2006.183.08:24:28.92#ibcon#about to read 6, iclass 17, count 0 2006.183.08:24:28.92#ibcon#read 6, iclass 17, count 0 2006.183.08:24:28.92#ibcon#end of sib2, iclass 17, count 0 2006.183.08:24:28.92#ibcon#*after write, iclass 17, count 0 2006.183.08:24:28.92#ibcon#*before return 0, iclass 17, count 0 2006.183.08:24:28.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:28.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:28.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:24:28.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:24:28.92$vc4f8/va=4,7 2006.183.08:24:28.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.08:24:28.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.08:24:28.92#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:28.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:28.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:28.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:28.97#ibcon#enter wrdev, iclass 19, count 2 2006.183.08:24:28.97#ibcon#first serial, iclass 19, count 2 2006.183.08:24:28.97#ibcon#enter sib2, iclass 19, count 2 2006.183.08:24:28.97#ibcon#flushed, iclass 19, count 2 2006.183.08:24:28.97#ibcon#about to write, iclass 19, count 2 2006.183.08:24:28.97#ibcon#wrote, iclass 19, count 2 2006.183.08:24:28.97#ibcon#about to read 3, iclass 19, count 2 2006.183.08:24:28.99#ibcon#read 3, iclass 19, count 2 2006.183.08:24:28.99#ibcon#about to read 4, iclass 19, count 2 2006.183.08:24:28.99#ibcon#read 4, iclass 19, count 2 2006.183.08:24:28.99#ibcon#about to read 5, iclass 19, count 2 2006.183.08:24:28.99#ibcon#read 5, iclass 19, count 2 2006.183.08:24:28.99#ibcon#about to read 6, iclass 19, count 2 2006.183.08:24:28.99#ibcon#read 6, iclass 19, count 2 2006.183.08:24:28.99#ibcon#end of sib2, iclass 19, count 2 2006.183.08:24:28.99#ibcon#*mode == 0, iclass 19, count 2 2006.183.08:24:28.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.08:24:28.99#ibcon#[25=AT04-07\r\n] 2006.183.08:24:28.99#ibcon#*before write, iclass 19, count 2 2006.183.08:24:28.99#ibcon#enter sib2, iclass 19, count 2 2006.183.08:24:28.99#ibcon#flushed, iclass 19, count 2 2006.183.08:24:28.99#ibcon#about to write, iclass 19, count 2 2006.183.08:24:28.99#ibcon#wrote, iclass 19, count 2 2006.183.08:24:28.99#ibcon#about to read 3, iclass 19, count 2 2006.183.08:24:29.02#ibcon#read 3, iclass 19, count 2 2006.183.08:24:29.02#ibcon#about to read 4, iclass 19, count 2 2006.183.08:24:29.02#ibcon#read 4, iclass 19, count 2 2006.183.08:24:29.02#ibcon#about to read 5, iclass 19, count 2 2006.183.08:24:29.02#ibcon#read 5, iclass 19, count 2 2006.183.08:24:29.02#ibcon#about to read 6, iclass 19, count 2 2006.183.08:24:29.02#ibcon#read 6, iclass 19, count 2 2006.183.08:24:29.02#ibcon#end of sib2, iclass 19, count 2 2006.183.08:24:29.02#ibcon#*after write, iclass 19, count 2 2006.183.08:24:29.02#ibcon#*before return 0, iclass 19, count 2 2006.183.08:24:29.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:29.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:29.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.08:24:29.02#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:29.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:29.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:29.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:29.14#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:24:29.14#ibcon#first serial, iclass 19, count 0 2006.183.08:24:29.14#ibcon#enter sib2, iclass 19, count 0 2006.183.08:24:29.14#ibcon#flushed, iclass 19, count 0 2006.183.08:24:29.14#ibcon#about to write, iclass 19, count 0 2006.183.08:24:29.14#ibcon#wrote, iclass 19, count 0 2006.183.08:24:29.14#ibcon#about to read 3, iclass 19, count 0 2006.183.08:24:29.16#ibcon#read 3, iclass 19, count 0 2006.183.08:24:29.16#ibcon#about to read 4, iclass 19, count 0 2006.183.08:24:29.16#ibcon#read 4, iclass 19, count 0 2006.183.08:24:29.16#ibcon#about to read 5, iclass 19, count 0 2006.183.08:24:29.16#ibcon#read 5, iclass 19, count 0 2006.183.08:24:29.16#ibcon#about to read 6, iclass 19, count 0 2006.183.08:24:29.16#ibcon#read 6, iclass 19, count 0 2006.183.08:24:29.16#ibcon#end of sib2, iclass 19, count 0 2006.183.08:24:29.16#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:24:29.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:24:29.16#ibcon#[25=USB\r\n] 2006.183.08:24:29.16#ibcon#*before write, iclass 19, count 0 2006.183.08:24:29.16#ibcon#enter sib2, iclass 19, count 0 2006.183.08:24:29.16#ibcon#flushed, iclass 19, count 0 2006.183.08:24:29.16#ibcon#about to write, iclass 19, count 0 2006.183.08:24:29.16#ibcon#wrote, iclass 19, count 0 2006.183.08:24:29.16#ibcon#about to read 3, iclass 19, count 0 2006.183.08:24:29.19#ibcon#read 3, iclass 19, count 0 2006.183.08:24:29.19#ibcon#about to read 4, iclass 19, count 0 2006.183.08:24:29.19#ibcon#read 4, iclass 19, count 0 2006.183.08:24:29.19#ibcon#about to read 5, iclass 19, count 0 2006.183.08:24:29.19#ibcon#read 5, iclass 19, count 0 2006.183.08:24:29.19#ibcon#about to read 6, iclass 19, count 0 2006.183.08:24:29.19#ibcon#read 6, iclass 19, count 0 2006.183.08:24:29.19#ibcon#end of sib2, iclass 19, count 0 2006.183.08:24:29.19#ibcon#*after write, iclass 19, count 0 2006.183.08:24:29.19#ibcon#*before return 0, iclass 19, count 0 2006.183.08:24:29.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:29.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:29.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:24:29.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:24:29.19$vc4f8/valo=5,652.99 2006.183.08:24:29.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.08:24:29.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.08:24:29.19#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:29.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:29.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:29.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:29.19#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:24:29.19#ibcon#first serial, iclass 21, count 0 2006.183.08:24:29.19#ibcon#enter sib2, iclass 21, count 0 2006.183.08:24:29.19#ibcon#flushed, iclass 21, count 0 2006.183.08:24:29.19#ibcon#about to write, iclass 21, count 0 2006.183.08:24:29.19#ibcon#wrote, iclass 21, count 0 2006.183.08:24:29.19#ibcon#about to read 3, iclass 21, count 0 2006.183.08:24:29.21#ibcon#read 3, iclass 21, count 0 2006.183.08:24:29.21#ibcon#about to read 4, iclass 21, count 0 2006.183.08:24:29.21#ibcon#read 4, iclass 21, count 0 2006.183.08:24:29.21#ibcon#about to read 5, iclass 21, count 0 2006.183.08:24:29.21#ibcon#read 5, iclass 21, count 0 2006.183.08:24:29.21#ibcon#about to read 6, iclass 21, count 0 2006.183.08:24:29.21#ibcon#read 6, iclass 21, count 0 2006.183.08:24:29.21#ibcon#end of sib2, iclass 21, count 0 2006.183.08:24:29.21#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:24:29.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:24:29.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:24:29.21#ibcon#*before write, iclass 21, count 0 2006.183.08:24:29.21#ibcon#enter sib2, iclass 21, count 0 2006.183.08:24:29.21#ibcon#flushed, iclass 21, count 0 2006.183.08:24:29.21#ibcon#about to write, iclass 21, count 0 2006.183.08:24:29.21#ibcon#wrote, iclass 21, count 0 2006.183.08:24:29.21#ibcon#about to read 3, iclass 21, count 0 2006.183.08:24:29.25#ibcon#read 3, iclass 21, count 0 2006.183.08:24:29.25#ibcon#about to read 4, iclass 21, count 0 2006.183.08:24:29.25#ibcon#read 4, iclass 21, count 0 2006.183.08:24:29.25#ibcon#about to read 5, iclass 21, count 0 2006.183.08:24:29.25#ibcon#read 5, iclass 21, count 0 2006.183.08:24:29.25#ibcon#about to read 6, iclass 21, count 0 2006.183.08:24:29.25#ibcon#read 6, iclass 21, count 0 2006.183.08:24:29.25#ibcon#end of sib2, iclass 21, count 0 2006.183.08:24:29.25#ibcon#*after write, iclass 21, count 0 2006.183.08:24:29.25#ibcon#*before return 0, iclass 21, count 0 2006.183.08:24:29.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:29.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:29.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:24:29.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:24:29.25$vc4f8/va=5,7 2006.183.08:24:29.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.08:24:29.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.08:24:29.25#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:29.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:29.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:29.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:29.31#ibcon#enter wrdev, iclass 23, count 2 2006.183.08:24:29.31#ibcon#first serial, iclass 23, count 2 2006.183.08:24:29.31#ibcon#enter sib2, iclass 23, count 2 2006.183.08:24:29.31#ibcon#flushed, iclass 23, count 2 2006.183.08:24:29.31#ibcon#about to write, iclass 23, count 2 2006.183.08:24:29.31#ibcon#wrote, iclass 23, count 2 2006.183.08:24:29.31#ibcon#about to read 3, iclass 23, count 2 2006.183.08:24:29.33#ibcon#read 3, iclass 23, count 2 2006.183.08:24:29.33#ibcon#about to read 4, iclass 23, count 2 2006.183.08:24:29.33#ibcon#read 4, iclass 23, count 2 2006.183.08:24:29.33#ibcon#about to read 5, iclass 23, count 2 2006.183.08:24:29.33#ibcon#read 5, iclass 23, count 2 2006.183.08:24:29.33#ibcon#about to read 6, iclass 23, count 2 2006.183.08:24:29.33#ibcon#read 6, iclass 23, count 2 2006.183.08:24:29.33#ibcon#end of sib2, iclass 23, count 2 2006.183.08:24:29.33#ibcon#*mode == 0, iclass 23, count 2 2006.183.08:24:29.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.08:24:29.33#ibcon#[25=AT05-07\r\n] 2006.183.08:24:29.33#ibcon#*before write, iclass 23, count 2 2006.183.08:24:29.33#ibcon#enter sib2, iclass 23, count 2 2006.183.08:24:29.33#ibcon#flushed, iclass 23, count 2 2006.183.08:24:29.33#ibcon#about to write, iclass 23, count 2 2006.183.08:24:29.33#ibcon#wrote, iclass 23, count 2 2006.183.08:24:29.33#ibcon#about to read 3, iclass 23, count 2 2006.183.08:24:29.36#ibcon#read 3, iclass 23, count 2 2006.183.08:24:29.36#ibcon#about to read 4, iclass 23, count 2 2006.183.08:24:29.36#ibcon#read 4, iclass 23, count 2 2006.183.08:24:29.36#ibcon#about to read 5, iclass 23, count 2 2006.183.08:24:29.36#ibcon#read 5, iclass 23, count 2 2006.183.08:24:29.36#ibcon#about to read 6, iclass 23, count 2 2006.183.08:24:29.36#ibcon#read 6, iclass 23, count 2 2006.183.08:24:29.36#ibcon#end of sib2, iclass 23, count 2 2006.183.08:24:29.36#ibcon#*after write, iclass 23, count 2 2006.183.08:24:29.36#ibcon#*before return 0, iclass 23, count 2 2006.183.08:24:29.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:29.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:29.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.08:24:29.36#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:29.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:29.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:29.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:29.48#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:24:29.48#ibcon#first serial, iclass 23, count 0 2006.183.08:24:29.48#ibcon#enter sib2, iclass 23, count 0 2006.183.08:24:29.48#ibcon#flushed, iclass 23, count 0 2006.183.08:24:29.48#ibcon#about to write, iclass 23, count 0 2006.183.08:24:29.48#ibcon#wrote, iclass 23, count 0 2006.183.08:24:29.48#ibcon#about to read 3, iclass 23, count 0 2006.183.08:24:29.50#ibcon#read 3, iclass 23, count 0 2006.183.08:24:29.50#ibcon#about to read 4, iclass 23, count 0 2006.183.08:24:29.50#ibcon#read 4, iclass 23, count 0 2006.183.08:24:29.50#ibcon#about to read 5, iclass 23, count 0 2006.183.08:24:29.50#ibcon#read 5, iclass 23, count 0 2006.183.08:24:29.50#ibcon#about to read 6, iclass 23, count 0 2006.183.08:24:29.50#ibcon#read 6, iclass 23, count 0 2006.183.08:24:29.50#ibcon#end of sib2, iclass 23, count 0 2006.183.08:24:29.50#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:24:29.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:24:29.50#ibcon#[25=USB\r\n] 2006.183.08:24:29.50#ibcon#*before write, iclass 23, count 0 2006.183.08:24:29.50#ibcon#enter sib2, iclass 23, count 0 2006.183.08:24:29.50#ibcon#flushed, iclass 23, count 0 2006.183.08:24:29.50#ibcon#about to write, iclass 23, count 0 2006.183.08:24:29.50#ibcon#wrote, iclass 23, count 0 2006.183.08:24:29.50#ibcon#about to read 3, iclass 23, count 0 2006.183.08:24:29.53#ibcon#read 3, iclass 23, count 0 2006.183.08:24:29.53#ibcon#about to read 4, iclass 23, count 0 2006.183.08:24:29.53#ibcon#read 4, iclass 23, count 0 2006.183.08:24:29.53#ibcon#about to read 5, iclass 23, count 0 2006.183.08:24:29.53#ibcon#read 5, iclass 23, count 0 2006.183.08:24:29.53#ibcon#about to read 6, iclass 23, count 0 2006.183.08:24:29.53#ibcon#read 6, iclass 23, count 0 2006.183.08:24:29.53#ibcon#end of sib2, iclass 23, count 0 2006.183.08:24:29.53#ibcon#*after write, iclass 23, count 0 2006.183.08:24:29.53#ibcon#*before return 0, iclass 23, count 0 2006.183.08:24:29.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:29.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:29.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:24:29.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:24:29.53$vc4f8/valo=6,772.99 2006.183.08:24:29.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.08:24:29.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.08:24:29.53#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:29.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:29.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:29.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:29.53#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:24:29.53#ibcon#first serial, iclass 25, count 0 2006.183.08:24:29.53#ibcon#enter sib2, iclass 25, count 0 2006.183.08:24:29.53#ibcon#flushed, iclass 25, count 0 2006.183.08:24:29.53#ibcon#about to write, iclass 25, count 0 2006.183.08:24:29.53#ibcon#wrote, iclass 25, count 0 2006.183.08:24:29.53#ibcon#about to read 3, iclass 25, count 0 2006.183.08:24:29.55#ibcon#read 3, iclass 25, count 0 2006.183.08:24:29.55#ibcon#about to read 4, iclass 25, count 0 2006.183.08:24:29.55#ibcon#read 4, iclass 25, count 0 2006.183.08:24:29.55#ibcon#about to read 5, iclass 25, count 0 2006.183.08:24:29.55#ibcon#read 5, iclass 25, count 0 2006.183.08:24:29.55#ibcon#about to read 6, iclass 25, count 0 2006.183.08:24:29.55#ibcon#read 6, iclass 25, count 0 2006.183.08:24:29.55#ibcon#end of sib2, iclass 25, count 0 2006.183.08:24:29.55#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:24:29.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:24:29.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:24:29.55#ibcon#*before write, iclass 25, count 0 2006.183.08:24:29.55#ibcon#enter sib2, iclass 25, count 0 2006.183.08:24:29.55#ibcon#flushed, iclass 25, count 0 2006.183.08:24:29.55#ibcon#about to write, iclass 25, count 0 2006.183.08:24:29.55#ibcon#wrote, iclass 25, count 0 2006.183.08:24:29.55#ibcon#about to read 3, iclass 25, count 0 2006.183.08:24:29.59#ibcon#read 3, iclass 25, count 0 2006.183.08:24:29.59#ibcon#about to read 4, iclass 25, count 0 2006.183.08:24:29.59#ibcon#read 4, iclass 25, count 0 2006.183.08:24:29.59#ibcon#about to read 5, iclass 25, count 0 2006.183.08:24:29.59#ibcon#read 5, iclass 25, count 0 2006.183.08:24:29.59#ibcon#about to read 6, iclass 25, count 0 2006.183.08:24:29.59#ibcon#read 6, iclass 25, count 0 2006.183.08:24:29.59#ibcon#end of sib2, iclass 25, count 0 2006.183.08:24:29.59#ibcon#*after write, iclass 25, count 0 2006.183.08:24:29.59#ibcon#*before return 0, iclass 25, count 0 2006.183.08:24:29.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:29.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:29.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:24:29.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:24:29.59$vc4f8/va=6,6 2006.183.08:24:29.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.183.08:24:29.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.183.08:24:29.59#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:29.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:24:29.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:24:29.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:24:29.65#ibcon#enter wrdev, iclass 27, count 2 2006.183.08:24:29.65#ibcon#first serial, iclass 27, count 2 2006.183.08:24:29.65#ibcon#enter sib2, iclass 27, count 2 2006.183.08:24:29.65#ibcon#flushed, iclass 27, count 2 2006.183.08:24:29.65#ibcon#about to write, iclass 27, count 2 2006.183.08:24:29.65#ibcon#wrote, iclass 27, count 2 2006.183.08:24:29.65#ibcon#about to read 3, iclass 27, count 2 2006.183.08:24:29.67#ibcon#read 3, iclass 27, count 2 2006.183.08:24:29.67#ibcon#about to read 4, iclass 27, count 2 2006.183.08:24:29.67#ibcon#read 4, iclass 27, count 2 2006.183.08:24:29.67#ibcon#about to read 5, iclass 27, count 2 2006.183.08:24:29.67#ibcon#read 5, iclass 27, count 2 2006.183.08:24:29.67#ibcon#about to read 6, iclass 27, count 2 2006.183.08:24:29.67#ibcon#read 6, iclass 27, count 2 2006.183.08:24:29.67#ibcon#end of sib2, iclass 27, count 2 2006.183.08:24:29.67#ibcon#*mode == 0, iclass 27, count 2 2006.183.08:24:29.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.183.08:24:29.67#ibcon#[25=AT06-06\r\n] 2006.183.08:24:29.67#ibcon#*before write, iclass 27, count 2 2006.183.08:24:29.67#ibcon#enter sib2, iclass 27, count 2 2006.183.08:24:29.67#ibcon#flushed, iclass 27, count 2 2006.183.08:24:29.67#ibcon#about to write, iclass 27, count 2 2006.183.08:24:29.67#ibcon#wrote, iclass 27, count 2 2006.183.08:24:29.67#ibcon#about to read 3, iclass 27, count 2 2006.183.08:24:29.70#ibcon#read 3, iclass 27, count 2 2006.183.08:24:29.70#ibcon#about to read 4, iclass 27, count 2 2006.183.08:24:29.70#ibcon#read 4, iclass 27, count 2 2006.183.08:24:29.70#ibcon#about to read 5, iclass 27, count 2 2006.183.08:24:29.70#ibcon#read 5, iclass 27, count 2 2006.183.08:24:29.70#ibcon#about to read 6, iclass 27, count 2 2006.183.08:24:29.70#ibcon#read 6, iclass 27, count 2 2006.183.08:24:29.70#ibcon#end of sib2, iclass 27, count 2 2006.183.08:24:29.70#ibcon#*after write, iclass 27, count 2 2006.183.08:24:29.70#ibcon#*before return 0, iclass 27, count 2 2006.183.08:24:29.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:24:29.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.183.08:24:29.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.183.08:24:29.70#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:29.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:24:29.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:24:29.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:24:29.82#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:24:29.82#ibcon#first serial, iclass 27, count 0 2006.183.08:24:29.82#ibcon#enter sib2, iclass 27, count 0 2006.183.08:24:29.82#ibcon#flushed, iclass 27, count 0 2006.183.08:24:29.82#ibcon#about to write, iclass 27, count 0 2006.183.08:24:29.82#ibcon#wrote, iclass 27, count 0 2006.183.08:24:29.82#ibcon#about to read 3, iclass 27, count 0 2006.183.08:24:29.84#ibcon#read 3, iclass 27, count 0 2006.183.08:24:29.84#ibcon#about to read 4, iclass 27, count 0 2006.183.08:24:29.84#ibcon#read 4, iclass 27, count 0 2006.183.08:24:29.84#ibcon#about to read 5, iclass 27, count 0 2006.183.08:24:29.84#ibcon#read 5, iclass 27, count 0 2006.183.08:24:29.84#ibcon#about to read 6, iclass 27, count 0 2006.183.08:24:29.84#ibcon#read 6, iclass 27, count 0 2006.183.08:24:29.84#ibcon#end of sib2, iclass 27, count 0 2006.183.08:24:29.84#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:24:29.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:24:29.84#ibcon#[25=USB\r\n] 2006.183.08:24:29.84#ibcon#*before write, iclass 27, count 0 2006.183.08:24:29.84#ibcon#enter sib2, iclass 27, count 0 2006.183.08:24:29.84#ibcon#flushed, iclass 27, count 0 2006.183.08:24:29.84#ibcon#about to write, iclass 27, count 0 2006.183.08:24:29.84#ibcon#wrote, iclass 27, count 0 2006.183.08:24:29.84#ibcon#about to read 3, iclass 27, count 0 2006.183.08:24:29.87#ibcon#read 3, iclass 27, count 0 2006.183.08:24:29.87#ibcon#about to read 4, iclass 27, count 0 2006.183.08:24:29.87#ibcon#read 4, iclass 27, count 0 2006.183.08:24:29.87#ibcon#about to read 5, iclass 27, count 0 2006.183.08:24:29.87#ibcon#read 5, iclass 27, count 0 2006.183.08:24:29.87#ibcon#about to read 6, iclass 27, count 0 2006.183.08:24:29.87#ibcon#read 6, iclass 27, count 0 2006.183.08:24:29.87#ibcon#end of sib2, iclass 27, count 0 2006.183.08:24:29.87#ibcon#*after write, iclass 27, count 0 2006.183.08:24:29.87#ibcon#*before return 0, iclass 27, count 0 2006.183.08:24:29.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:24:29.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.183.08:24:29.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:24:29.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:24:29.87$vc4f8/valo=7,832.99 2006.183.08:24:29.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.08:24:29.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.08:24:29.87#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:29.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:24:29.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:24:29.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:24:29.87#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:24:29.87#ibcon#first serial, iclass 29, count 0 2006.183.08:24:29.87#ibcon#enter sib2, iclass 29, count 0 2006.183.08:24:29.87#ibcon#flushed, iclass 29, count 0 2006.183.08:24:29.87#ibcon#about to write, iclass 29, count 0 2006.183.08:24:29.87#ibcon#wrote, iclass 29, count 0 2006.183.08:24:29.87#ibcon#about to read 3, iclass 29, count 0 2006.183.08:24:29.89#ibcon#read 3, iclass 29, count 0 2006.183.08:24:29.89#ibcon#about to read 4, iclass 29, count 0 2006.183.08:24:29.89#ibcon#read 4, iclass 29, count 0 2006.183.08:24:29.89#ibcon#about to read 5, iclass 29, count 0 2006.183.08:24:29.89#ibcon#read 5, iclass 29, count 0 2006.183.08:24:29.89#ibcon#about to read 6, iclass 29, count 0 2006.183.08:24:29.89#ibcon#read 6, iclass 29, count 0 2006.183.08:24:29.89#ibcon#end of sib2, iclass 29, count 0 2006.183.08:24:29.89#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:24:29.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:24:29.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:24:29.89#ibcon#*before write, iclass 29, count 0 2006.183.08:24:29.89#ibcon#enter sib2, iclass 29, count 0 2006.183.08:24:29.89#ibcon#flushed, iclass 29, count 0 2006.183.08:24:29.89#ibcon#about to write, iclass 29, count 0 2006.183.08:24:29.89#ibcon#wrote, iclass 29, count 0 2006.183.08:24:29.89#ibcon#about to read 3, iclass 29, count 0 2006.183.08:24:29.93#ibcon#read 3, iclass 29, count 0 2006.183.08:24:29.93#ibcon#about to read 4, iclass 29, count 0 2006.183.08:24:29.93#ibcon#read 4, iclass 29, count 0 2006.183.08:24:29.93#ibcon#about to read 5, iclass 29, count 0 2006.183.08:24:29.93#ibcon#read 5, iclass 29, count 0 2006.183.08:24:29.93#ibcon#about to read 6, iclass 29, count 0 2006.183.08:24:29.93#ibcon#read 6, iclass 29, count 0 2006.183.08:24:29.93#ibcon#end of sib2, iclass 29, count 0 2006.183.08:24:29.93#ibcon#*after write, iclass 29, count 0 2006.183.08:24:29.93#ibcon#*before return 0, iclass 29, count 0 2006.183.08:24:29.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:24:29.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:24:29.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:24:29.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:24:29.93$vc4f8/va=7,6 2006.183.08:24:29.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.183.08:24:29.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.183.08:24:29.93#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:29.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:24:29.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:24:29.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:24:29.99#ibcon#enter wrdev, iclass 31, count 2 2006.183.08:24:29.99#ibcon#first serial, iclass 31, count 2 2006.183.08:24:29.99#ibcon#enter sib2, iclass 31, count 2 2006.183.08:24:29.99#ibcon#flushed, iclass 31, count 2 2006.183.08:24:29.99#ibcon#about to write, iclass 31, count 2 2006.183.08:24:29.99#ibcon#wrote, iclass 31, count 2 2006.183.08:24:29.99#ibcon#about to read 3, iclass 31, count 2 2006.183.08:24:30.01#ibcon#read 3, iclass 31, count 2 2006.183.08:24:30.01#ibcon#about to read 4, iclass 31, count 2 2006.183.08:24:30.01#ibcon#read 4, iclass 31, count 2 2006.183.08:24:30.01#ibcon#about to read 5, iclass 31, count 2 2006.183.08:24:30.01#ibcon#read 5, iclass 31, count 2 2006.183.08:24:30.01#ibcon#about to read 6, iclass 31, count 2 2006.183.08:24:30.01#ibcon#read 6, iclass 31, count 2 2006.183.08:24:30.01#ibcon#end of sib2, iclass 31, count 2 2006.183.08:24:30.01#ibcon#*mode == 0, iclass 31, count 2 2006.183.08:24:30.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.183.08:24:30.01#ibcon#[25=AT07-06\r\n] 2006.183.08:24:30.01#ibcon#*before write, iclass 31, count 2 2006.183.08:24:30.01#ibcon#enter sib2, iclass 31, count 2 2006.183.08:24:30.01#ibcon#flushed, iclass 31, count 2 2006.183.08:24:30.01#ibcon#about to write, iclass 31, count 2 2006.183.08:24:30.01#ibcon#wrote, iclass 31, count 2 2006.183.08:24:30.01#ibcon#about to read 3, iclass 31, count 2 2006.183.08:24:30.04#ibcon#read 3, iclass 31, count 2 2006.183.08:24:30.04#ibcon#about to read 4, iclass 31, count 2 2006.183.08:24:30.04#ibcon#read 4, iclass 31, count 2 2006.183.08:24:30.04#ibcon#about to read 5, iclass 31, count 2 2006.183.08:24:30.04#ibcon#read 5, iclass 31, count 2 2006.183.08:24:30.04#ibcon#about to read 6, iclass 31, count 2 2006.183.08:24:30.04#ibcon#read 6, iclass 31, count 2 2006.183.08:24:30.04#ibcon#end of sib2, iclass 31, count 2 2006.183.08:24:30.04#ibcon#*after write, iclass 31, count 2 2006.183.08:24:30.04#ibcon#*before return 0, iclass 31, count 2 2006.183.08:24:30.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:24:30.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.183.08:24:30.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.183.08:24:30.04#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:30.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:24:30.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:24:30.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:24:30.16#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:24:30.16#ibcon#first serial, iclass 31, count 0 2006.183.08:24:30.16#ibcon#enter sib2, iclass 31, count 0 2006.183.08:24:30.16#ibcon#flushed, iclass 31, count 0 2006.183.08:24:30.16#ibcon#about to write, iclass 31, count 0 2006.183.08:24:30.16#ibcon#wrote, iclass 31, count 0 2006.183.08:24:30.16#ibcon#about to read 3, iclass 31, count 0 2006.183.08:24:30.18#ibcon#read 3, iclass 31, count 0 2006.183.08:24:30.18#ibcon#about to read 4, iclass 31, count 0 2006.183.08:24:30.18#ibcon#read 4, iclass 31, count 0 2006.183.08:24:30.18#ibcon#about to read 5, iclass 31, count 0 2006.183.08:24:30.18#ibcon#read 5, iclass 31, count 0 2006.183.08:24:30.18#ibcon#about to read 6, iclass 31, count 0 2006.183.08:24:30.18#ibcon#read 6, iclass 31, count 0 2006.183.08:24:30.18#ibcon#end of sib2, iclass 31, count 0 2006.183.08:24:30.18#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:24:30.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:24:30.18#ibcon#[25=USB\r\n] 2006.183.08:24:30.18#ibcon#*before write, iclass 31, count 0 2006.183.08:24:30.18#ibcon#enter sib2, iclass 31, count 0 2006.183.08:24:30.18#ibcon#flushed, iclass 31, count 0 2006.183.08:24:30.18#ibcon#about to write, iclass 31, count 0 2006.183.08:24:30.18#ibcon#wrote, iclass 31, count 0 2006.183.08:24:30.18#ibcon#about to read 3, iclass 31, count 0 2006.183.08:24:30.21#ibcon#read 3, iclass 31, count 0 2006.183.08:24:30.21#ibcon#about to read 4, iclass 31, count 0 2006.183.08:24:30.21#ibcon#read 4, iclass 31, count 0 2006.183.08:24:30.21#ibcon#about to read 5, iclass 31, count 0 2006.183.08:24:30.21#ibcon#read 5, iclass 31, count 0 2006.183.08:24:30.21#ibcon#about to read 6, iclass 31, count 0 2006.183.08:24:30.21#ibcon#read 6, iclass 31, count 0 2006.183.08:24:30.21#ibcon#end of sib2, iclass 31, count 0 2006.183.08:24:30.21#ibcon#*after write, iclass 31, count 0 2006.183.08:24:30.21#ibcon#*before return 0, iclass 31, count 0 2006.183.08:24:30.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:24:30.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.183.08:24:30.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:24:30.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:24:30.21$vc4f8/valo=8,852.99 2006.183.08:24:30.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.183.08:24:30.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.183.08:24:30.21#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:30.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:24:30.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:24:30.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:24:30.21#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:24:30.21#ibcon#first serial, iclass 33, count 0 2006.183.08:24:30.21#ibcon#enter sib2, iclass 33, count 0 2006.183.08:24:30.21#ibcon#flushed, iclass 33, count 0 2006.183.08:24:30.21#ibcon#about to write, iclass 33, count 0 2006.183.08:24:30.21#ibcon#wrote, iclass 33, count 0 2006.183.08:24:30.21#ibcon#about to read 3, iclass 33, count 0 2006.183.08:24:30.23#ibcon#read 3, iclass 33, count 0 2006.183.08:24:30.23#ibcon#about to read 4, iclass 33, count 0 2006.183.08:24:30.23#ibcon#read 4, iclass 33, count 0 2006.183.08:24:30.23#ibcon#about to read 5, iclass 33, count 0 2006.183.08:24:30.23#ibcon#read 5, iclass 33, count 0 2006.183.08:24:30.23#ibcon#about to read 6, iclass 33, count 0 2006.183.08:24:30.23#ibcon#read 6, iclass 33, count 0 2006.183.08:24:30.23#ibcon#end of sib2, iclass 33, count 0 2006.183.08:24:30.23#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:24:30.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:24:30.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:24:30.23#ibcon#*before write, iclass 33, count 0 2006.183.08:24:30.23#ibcon#enter sib2, iclass 33, count 0 2006.183.08:24:30.23#ibcon#flushed, iclass 33, count 0 2006.183.08:24:30.23#ibcon#about to write, iclass 33, count 0 2006.183.08:24:30.23#ibcon#wrote, iclass 33, count 0 2006.183.08:24:30.23#ibcon#about to read 3, iclass 33, count 0 2006.183.08:24:30.27#ibcon#read 3, iclass 33, count 0 2006.183.08:24:30.27#ibcon#about to read 4, iclass 33, count 0 2006.183.08:24:30.27#ibcon#read 4, iclass 33, count 0 2006.183.08:24:30.27#ibcon#about to read 5, iclass 33, count 0 2006.183.08:24:30.27#ibcon#read 5, iclass 33, count 0 2006.183.08:24:30.27#ibcon#about to read 6, iclass 33, count 0 2006.183.08:24:30.27#ibcon#read 6, iclass 33, count 0 2006.183.08:24:30.27#ibcon#end of sib2, iclass 33, count 0 2006.183.08:24:30.27#ibcon#*after write, iclass 33, count 0 2006.183.08:24:30.27#ibcon#*before return 0, iclass 33, count 0 2006.183.08:24:30.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:24:30.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.183.08:24:30.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:24:30.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:24:30.27$vc4f8/va=8,7 2006.183.08:24:30.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.183.08:24:30.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.183.08:24:30.27#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:30.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:24:30.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:24:30.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:24:30.33#ibcon#enter wrdev, iclass 35, count 2 2006.183.08:24:30.33#ibcon#first serial, iclass 35, count 2 2006.183.08:24:30.33#ibcon#enter sib2, iclass 35, count 2 2006.183.08:24:30.33#ibcon#flushed, iclass 35, count 2 2006.183.08:24:30.33#ibcon#about to write, iclass 35, count 2 2006.183.08:24:30.33#ibcon#wrote, iclass 35, count 2 2006.183.08:24:30.33#ibcon#about to read 3, iclass 35, count 2 2006.183.08:24:30.35#ibcon#read 3, iclass 35, count 2 2006.183.08:24:30.35#ibcon#about to read 4, iclass 35, count 2 2006.183.08:24:30.35#ibcon#read 4, iclass 35, count 2 2006.183.08:24:30.35#ibcon#about to read 5, iclass 35, count 2 2006.183.08:24:30.35#ibcon#read 5, iclass 35, count 2 2006.183.08:24:30.35#ibcon#about to read 6, iclass 35, count 2 2006.183.08:24:30.35#ibcon#read 6, iclass 35, count 2 2006.183.08:24:30.35#ibcon#end of sib2, iclass 35, count 2 2006.183.08:24:30.35#ibcon#*mode == 0, iclass 35, count 2 2006.183.08:24:30.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.183.08:24:30.35#ibcon#[25=AT08-07\r\n] 2006.183.08:24:30.35#ibcon#*before write, iclass 35, count 2 2006.183.08:24:30.35#ibcon#enter sib2, iclass 35, count 2 2006.183.08:24:30.35#ibcon#flushed, iclass 35, count 2 2006.183.08:24:30.35#ibcon#about to write, iclass 35, count 2 2006.183.08:24:30.35#ibcon#wrote, iclass 35, count 2 2006.183.08:24:30.35#ibcon#about to read 3, iclass 35, count 2 2006.183.08:24:30.38#ibcon#read 3, iclass 35, count 2 2006.183.08:24:30.38#ibcon#about to read 4, iclass 35, count 2 2006.183.08:24:30.38#ibcon#read 4, iclass 35, count 2 2006.183.08:24:30.38#ibcon#about to read 5, iclass 35, count 2 2006.183.08:24:30.38#ibcon#read 5, iclass 35, count 2 2006.183.08:24:30.38#ibcon#about to read 6, iclass 35, count 2 2006.183.08:24:30.38#ibcon#read 6, iclass 35, count 2 2006.183.08:24:30.38#ibcon#end of sib2, iclass 35, count 2 2006.183.08:24:30.38#ibcon#*after write, iclass 35, count 2 2006.183.08:24:30.38#ibcon#*before return 0, iclass 35, count 2 2006.183.08:24:30.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:24:30.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.183.08:24:30.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.183.08:24:30.38#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:30.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:24:30.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:24:30.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:24:30.50#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:24:30.50#ibcon#first serial, iclass 35, count 0 2006.183.08:24:30.50#ibcon#enter sib2, iclass 35, count 0 2006.183.08:24:30.50#ibcon#flushed, iclass 35, count 0 2006.183.08:24:30.50#ibcon#about to write, iclass 35, count 0 2006.183.08:24:30.50#ibcon#wrote, iclass 35, count 0 2006.183.08:24:30.50#ibcon#about to read 3, iclass 35, count 0 2006.183.08:24:30.52#ibcon#read 3, iclass 35, count 0 2006.183.08:24:30.52#ibcon#about to read 4, iclass 35, count 0 2006.183.08:24:30.52#ibcon#read 4, iclass 35, count 0 2006.183.08:24:30.52#ibcon#about to read 5, iclass 35, count 0 2006.183.08:24:30.52#ibcon#read 5, iclass 35, count 0 2006.183.08:24:30.52#ibcon#about to read 6, iclass 35, count 0 2006.183.08:24:30.52#ibcon#read 6, iclass 35, count 0 2006.183.08:24:30.52#ibcon#end of sib2, iclass 35, count 0 2006.183.08:24:30.52#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:24:30.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:24:30.52#ibcon#[25=USB\r\n] 2006.183.08:24:30.52#ibcon#*before write, iclass 35, count 0 2006.183.08:24:30.52#ibcon#enter sib2, iclass 35, count 0 2006.183.08:24:30.52#ibcon#flushed, iclass 35, count 0 2006.183.08:24:30.52#ibcon#about to write, iclass 35, count 0 2006.183.08:24:30.52#ibcon#wrote, iclass 35, count 0 2006.183.08:24:30.52#ibcon#about to read 3, iclass 35, count 0 2006.183.08:24:30.55#ibcon#read 3, iclass 35, count 0 2006.183.08:24:30.55#ibcon#about to read 4, iclass 35, count 0 2006.183.08:24:30.55#ibcon#read 4, iclass 35, count 0 2006.183.08:24:30.55#ibcon#about to read 5, iclass 35, count 0 2006.183.08:24:30.55#ibcon#read 5, iclass 35, count 0 2006.183.08:24:30.55#ibcon#about to read 6, iclass 35, count 0 2006.183.08:24:30.55#ibcon#read 6, iclass 35, count 0 2006.183.08:24:30.55#ibcon#end of sib2, iclass 35, count 0 2006.183.08:24:30.55#ibcon#*after write, iclass 35, count 0 2006.183.08:24:30.55#ibcon#*before return 0, iclass 35, count 0 2006.183.08:24:30.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:24:30.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.183.08:24:30.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:24:30.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:24:30.55$vc4f8/vblo=1,632.99 2006.183.08:24:30.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.183.08:24:30.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.183.08:24:30.55#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:30.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:24:30.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:24:30.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:24:30.55#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:24:30.55#ibcon#first serial, iclass 37, count 0 2006.183.08:24:30.55#ibcon#enter sib2, iclass 37, count 0 2006.183.08:24:30.55#ibcon#flushed, iclass 37, count 0 2006.183.08:24:30.55#ibcon#about to write, iclass 37, count 0 2006.183.08:24:30.55#ibcon#wrote, iclass 37, count 0 2006.183.08:24:30.55#ibcon#about to read 3, iclass 37, count 0 2006.183.08:24:30.57#ibcon#read 3, iclass 37, count 0 2006.183.08:24:30.57#ibcon#about to read 4, iclass 37, count 0 2006.183.08:24:30.57#ibcon#read 4, iclass 37, count 0 2006.183.08:24:30.57#ibcon#about to read 5, iclass 37, count 0 2006.183.08:24:30.57#ibcon#read 5, iclass 37, count 0 2006.183.08:24:30.57#ibcon#about to read 6, iclass 37, count 0 2006.183.08:24:30.57#ibcon#read 6, iclass 37, count 0 2006.183.08:24:30.57#ibcon#end of sib2, iclass 37, count 0 2006.183.08:24:30.57#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:24:30.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:24:30.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:24:30.57#ibcon#*before write, iclass 37, count 0 2006.183.08:24:30.57#ibcon#enter sib2, iclass 37, count 0 2006.183.08:24:30.57#ibcon#flushed, iclass 37, count 0 2006.183.08:24:30.57#ibcon#about to write, iclass 37, count 0 2006.183.08:24:30.57#ibcon#wrote, iclass 37, count 0 2006.183.08:24:30.57#ibcon#about to read 3, iclass 37, count 0 2006.183.08:24:30.61#ibcon#read 3, iclass 37, count 0 2006.183.08:24:30.61#ibcon#about to read 4, iclass 37, count 0 2006.183.08:24:30.61#ibcon#read 4, iclass 37, count 0 2006.183.08:24:30.61#ibcon#about to read 5, iclass 37, count 0 2006.183.08:24:30.61#ibcon#read 5, iclass 37, count 0 2006.183.08:24:30.61#ibcon#about to read 6, iclass 37, count 0 2006.183.08:24:30.61#ibcon#read 6, iclass 37, count 0 2006.183.08:24:30.61#ibcon#end of sib2, iclass 37, count 0 2006.183.08:24:30.61#ibcon#*after write, iclass 37, count 0 2006.183.08:24:30.61#ibcon#*before return 0, iclass 37, count 0 2006.183.08:24:30.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:24:30.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.183.08:24:30.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:24:30.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:24:30.61$vc4f8/vb=1,4 2006.183.08:24:30.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.183.08:24:30.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.183.08:24:30.61#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:30.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:24:30.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:24:30.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:24:30.61#ibcon#enter wrdev, iclass 39, count 2 2006.183.08:24:30.61#ibcon#first serial, iclass 39, count 2 2006.183.08:24:30.61#ibcon#enter sib2, iclass 39, count 2 2006.183.08:24:30.61#ibcon#flushed, iclass 39, count 2 2006.183.08:24:30.61#ibcon#about to write, iclass 39, count 2 2006.183.08:24:30.61#ibcon#wrote, iclass 39, count 2 2006.183.08:24:30.61#ibcon#about to read 3, iclass 39, count 2 2006.183.08:24:30.63#ibcon#read 3, iclass 39, count 2 2006.183.08:24:30.63#ibcon#about to read 4, iclass 39, count 2 2006.183.08:24:30.63#ibcon#read 4, iclass 39, count 2 2006.183.08:24:30.63#ibcon#about to read 5, iclass 39, count 2 2006.183.08:24:30.63#ibcon#read 5, iclass 39, count 2 2006.183.08:24:30.63#ibcon#about to read 6, iclass 39, count 2 2006.183.08:24:30.63#ibcon#read 6, iclass 39, count 2 2006.183.08:24:30.63#ibcon#end of sib2, iclass 39, count 2 2006.183.08:24:30.63#ibcon#*mode == 0, iclass 39, count 2 2006.183.08:24:30.63#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.183.08:24:30.63#ibcon#[27=AT01-04\r\n] 2006.183.08:24:30.63#ibcon#*before write, iclass 39, count 2 2006.183.08:24:30.63#ibcon#enter sib2, iclass 39, count 2 2006.183.08:24:30.63#ibcon#flushed, iclass 39, count 2 2006.183.08:24:30.63#ibcon#about to write, iclass 39, count 2 2006.183.08:24:30.63#ibcon#wrote, iclass 39, count 2 2006.183.08:24:30.63#ibcon#about to read 3, iclass 39, count 2 2006.183.08:24:30.66#ibcon#read 3, iclass 39, count 2 2006.183.08:24:30.66#ibcon#about to read 4, iclass 39, count 2 2006.183.08:24:30.66#ibcon#read 4, iclass 39, count 2 2006.183.08:24:30.66#ibcon#about to read 5, iclass 39, count 2 2006.183.08:24:30.66#ibcon#read 5, iclass 39, count 2 2006.183.08:24:30.66#ibcon#about to read 6, iclass 39, count 2 2006.183.08:24:30.66#ibcon#read 6, iclass 39, count 2 2006.183.08:24:30.66#ibcon#end of sib2, iclass 39, count 2 2006.183.08:24:30.66#ibcon#*after write, iclass 39, count 2 2006.183.08:24:30.66#ibcon#*before return 0, iclass 39, count 2 2006.183.08:24:30.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:24:30.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.183.08:24:30.66#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.183.08:24:30.66#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:30.66#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:24:30.78#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:24:30.78#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:24:30.78#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:24:30.78#ibcon#first serial, iclass 39, count 0 2006.183.08:24:30.78#ibcon#enter sib2, iclass 39, count 0 2006.183.08:24:30.78#ibcon#flushed, iclass 39, count 0 2006.183.08:24:30.78#ibcon#about to write, iclass 39, count 0 2006.183.08:24:30.78#ibcon#wrote, iclass 39, count 0 2006.183.08:24:30.78#ibcon#about to read 3, iclass 39, count 0 2006.183.08:24:30.80#ibcon#read 3, iclass 39, count 0 2006.183.08:24:30.80#ibcon#about to read 4, iclass 39, count 0 2006.183.08:24:30.80#ibcon#read 4, iclass 39, count 0 2006.183.08:24:30.80#ibcon#about to read 5, iclass 39, count 0 2006.183.08:24:30.80#ibcon#read 5, iclass 39, count 0 2006.183.08:24:30.80#ibcon#about to read 6, iclass 39, count 0 2006.183.08:24:30.80#ibcon#read 6, iclass 39, count 0 2006.183.08:24:30.80#ibcon#end of sib2, iclass 39, count 0 2006.183.08:24:30.80#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:24:30.80#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:24:30.80#ibcon#[27=USB\r\n] 2006.183.08:24:30.80#ibcon#*before write, iclass 39, count 0 2006.183.08:24:30.80#ibcon#enter sib2, iclass 39, count 0 2006.183.08:24:30.80#ibcon#flushed, iclass 39, count 0 2006.183.08:24:30.80#ibcon#about to write, iclass 39, count 0 2006.183.08:24:30.80#ibcon#wrote, iclass 39, count 0 2006.183.08:24:30.80#ibcon#about to read 3, iclass 39, count 0 2006.183.08:24:30.83#ibcon#read 3, iclass 39, count 0 2006.183.08:24:30.83#ibcon#about to read 4, iclass 39, count 0 2006.183.08:24:30.83#ibcon#read 4, iclass 39, count 0 2006.183.08:24:30.83#ibcon#about to read 5, iclass 39, count 0 2006.183.08:24:30.83#ibcon#read 5, iclass 39, count 0 2006.183.08:24:30.83#ibcon#about to read 6, iclass 39, count 0 2006.183.08:24:30.83#ibcon#read 6, iclass 39, count 0 2006.183.08:24:30.83#ibcon#end of sib2, iclass 39, count 0 2006.183.08:24:30.83#ibcon#*after write, iclass 39, count 0 2006.183.08:24:30.83#ibcon#*before return 0, iclass 39, count 0 2006.183.08:24:30.83#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:24:30.83#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.183.08:24:30.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:24:30.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:24:30.83$vc4f8/vblo=2,640.99 2006.183.08:24:30.83#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.183.08:24:30.83#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.183.08:24:30.83#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:30.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:30.83#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:30.83#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:30.83#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:24:30.83#ibcon#first serial, iclass 3, count 0 2006.183.08:24:30.83#ibcon#enter sib2, iclass 3, count 0 2006.183.08:24:30.83#ibcon#flushed, iclass 3, count 0 2006.183.08:24:30.83#ibcon#about to write, iclass 3, count 0 2006.183.08:24:30.83#ibcon#wrote, iclass 3, count 0 2006.183.08:24:30.83#ibcon#about to read 3, iclass 3, count 0 2006.183.08:24:30.85#ibcon#read 3, iclass 3, count 0 2006.183.08:24:30.85#ibcon#about to read 4, iclass 3, count 0 2006.183.08:24:30.85#ibcon#read 4, iclass 3, count 0 2006.183.08:24:30.85#ibcon#about to read 5, iclass 3, count 0 2006.183.08:24:30.85#ibcon#read 5, iclass 3, count 0 2006.183.08:24:30.85#ibcon#about to read 6, iclass 3, count 0 2006.183.08:24:30.85#ibcon#read 6, iclass 3, count 0 2006.183.08:24:30.85#ibcon#end of sib2, iclass 3, count 0 2006.183.08:24:30.85#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:24:30.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:24:30.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:24:30.85#ibcon#*before write, iclass 3, count 0 2006.183.08:24:30.85#ibcon#enter sib2, iclass 3, count 0 2006.183.08:24:30.85#ibcon#flushed, iclass 3, count 0 2006.183.08:24:30.85#ibcon#about to write, iclass 3, count 0 2006.183.08:24:30.85#ibcon#wrote, iclass 3, count 0 2006.183.08:24:30.85#ibcon#about to read 3, iclass 3, count 0 2006.183.08:24:30.89#ibcon#read 3, iclass 3, count 0 2006.183.08:24:30.89#ibcon#about to read 4, iclass 3, count 0 2006.183.08:24:30.89#ibcon#read 4, iclass 3, count 0 2006.183.08:24:30.89#ibcon#about to read 5, iclass 3, count 0 2006.183.08:24:30.89#ibcon#read 5, iclass 3, count 0 2006.183.08:24:30.89#ibcon#about to read 6, iclass 3, count 0 2006.183.08:24:30.89#ibcon#read 6, iclass 3, count 0 2006.183.08:24:30.89#ibcon#end of sib2, iclass 3, count 0 2006.183.08:24:30.89#ibcon#*after write, iclass 3, count 0 2006.183.08:24:30.89#ibcon#*before return 0, iclass 3, count 0 2006.183.08:24:30.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:30.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.183.08:24:30.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:24:30.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:24:30.89$vc4f8/vb=2,4 2006.183.08:24:30.89#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.183.08:24:30.89#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.183.08:24:30.89#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:30.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:30.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:30.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:30.95#ibcon#enter wrdev, iclass 5, count 2 2006.183.08:24:30.95#ibcon#first serial, iclass 5, count 2 2006.183.08:24:30.95#ibcon#enter sib2, iclass 5, count 2 2006.183.08:24:30.95#ibcon#flushed, iclass 5, count 2 2006.183.08:24:30.95#ibcon#about to write, iclass 5, count 2 2006.183.08:24:30.95#ibcon#wrote, iclass 5, count 2 2006.183.08:24:30.95#ibcon#about to read 3, iclass 5, count 2 2006.183.08:24:30.97#ibcon#read 3, iclass 5, count 2 2006.183.08:24:30.97#ibcon#about to read 4, iclass 5, count 2 2006.183.08:24:30.97#ibcon#read 4, iclass 5, count 2 2006.183.08:24:30.97#ibcon#about to read 5, iclass 5, count 2 2006.183.08:24:30.97#ibcon#read 5, iclass 5, count 2 2006.183.08:24:30.97#ibcon#about to read 6, iclass 5, count 2 2006.183.08:24:30.97#ibcon#read 6, iclass 5, count 2 2006.183.08:24:30.97#ibcon#end of sib2, iclass 5, count 2 2006.183.08:24:30.97#ibcon#*mode == 0, iclass 5, count 2 2006.183.08:24:30.97#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.183.08:24:30.97#ibcon#[27=AT02-04\r\n] 2006.183.08:24:30.97#ibcon#*before write, iclass 5, count 2 2006.183.08:24:30.97#ibcon#enter sib2, iclass 5, count 2 2006.183.08:24:30.97#ibcon#flushed, iclass 5, count 2 2006.183.08:24:30.97#ibcon#about to write, iclass 5, count 2 2006.183.08:24:30.97#ibcon#wrote, iclass 5, count 2 2006.183.08:24:30.97#ibcon#about to read 3, iclass 5, count 2 2006.183.08:24:31.00#ibcon#read 3, iclass 5, count 2 2006.183.08:24:31.00#ibcon#about to read 4, iclass 5, count 2 2006.183.08:24:31.00#ibcon#read 4, iclass 5, count 2 2006.183.08:24:31.00#ibcon#about to read 5, iclass 5, count 2 2006.183.08:24:31.00#ibcon#read 5, iclass 5, count 2 2006.183.08:24:31.00#ibcon#about to read 6, iclass 5, count 2 2006.183.08:24:31.00#ibcon#read 6, iclass 5, count 2 2006.183.08:24:31.00#ibcon#end of sib2, iclass 5, count 2 2006.183.08:24:31.00#ibcon#*after write, iclass 5, count 2 2006.183.08:24:31.00#ibcon#*before return 0, iclass 5, count 2 2006.183.08:24:31.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:31.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.183.08:24:31.00#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.183.08:24:31.00#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:31.00#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:31.12#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:31.12#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:31.12#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:24:31.12#ibcon#first serial, iclass 5, count 0 2006.183.08:24:31.12#ibcon#enter sib2, iclass 5, count 0 2006.183.08:24:31.12#ibcon#flushed, iclass 5, count 0 2006.183.08:24:31.12#ibcon#about to write, iclass 5, count 0 2006.183.08:24:31.12#ibcon#wrote, iclass 5, count 0 2006.183.08:24:31.12#ibcon#about to read 3, iclass 5, count 0 2006.183.08:24:31.14#ibcon#read 3, iclass 5, count 0 2006.183.08:24:31.14#ibcon#about to read 4, iclass 5, count 0 2006.183.08:24:31.14#ibcon#read 4, iclass 5, count 0 2006.183.08:24:31.14#ibcon#about to read 5, iclass 5, count 0 2006.183.08:24:31.14#ibcon#read 5, iclass 5, count 0 2006.183.08:24:31.14#ibcon#about to read 6, iclass 5, count 0 2006.183.08:24:31.14#ibcon#read 6, iclass 5, count 0 2006.183.08:24:31.14#ibcon#end of sib2, iclass 5, count 0 2006.183.08:24:31.14#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:24:31.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:24:31.14#ibcon#[27=USB\r\n] 2006.183.08:24:31.14#ibcon#*before write, iclass 5, count 0 2006.183.08:24:31.14#ibcon#enter sib2, iclass 5, count 0 2006.183.08:24:31.14#ibcon#flushed, iclass 5, count 0 2006.183.08:24:31.14#ibcon#about to write, iclass 5, count 0 2006.183.08:24:31.14#ibcon#wrote, iclass 5, count 0 2006.183.08:24:31.14#ibcon#about to read 3, iclass 5, count 0 2006.183.08:24:31.17#ibcon#read 3, iclass 5, count 0 2006.183.08:24:31.17#ibcon#about to read 4, iclass 5, count 0 2006.183.08:24:31.17#ibcon#read 4, iclass 5, count 0 2006.183.08:24:31.17#ibcon#about to read 5, iclass 5, count 0 2006.183.08:24:31.17#ibcon#read 5, iclass 5, count 0 2006.183.08:24:31.17#ibcon#about to read 6, iclass 5, count 0 2006.183.08:24:31.17#ibcon#read 6, iclass 5, count 0 2006.183.08:24:31.17#ibcon#end of sib2, iclass 5, count 0 2006.183.08:24:31.17#ibcon#*after write, iclass 5, count 0 2006.183.08:24:31.17#ibcon#*before return 0, iclass 5, count 0 2006.183.08:24:31.17#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:31.17#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.183.08:24:31.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:24:31.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:24:31.17$vc4f8/vblo=3,656.99 2006.183.08:24:31.17#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.183.08:24:31.17#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.183.08:24:31.17#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:31.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:31.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:31.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:31.17#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:24:31.17#ibcon#first serial, iclass 7, count 0 2006.183.08:24:31.17#ibcon#enter sib2, iclass 7, count 0 2006.183.08:24:31.17#ibcon#flushed, iclass 7, count 0 2006.183.08:24:31.17#ibcon#about to write, iclass 7, count 0 2006.183.08:24:31.17#ibcon#wrote, iclass 7, count 0 2006.183.08:24:31.17#ibcon#about to read 3, iclass 7, count 0 2006.183.08:24:31.20#ibcon#read 3, iclass 7, count 0 2006.183.08:24:31.20#ibcon#about to read 4, iclass 7, count 0 2006.183.08:24:31.20#ibcon#read 4, iclass 7, count 0 2006.183.08:24:31.20#ibcon#about to read 5, iclass 7, count 0 2006.183.08:24:31.20#ibcon#read 5, iclass 7, count 0 2006.183.08:24:31.20#ibcon#about to read 6, iclass 7, count 0 2006.183.08:24:31.20#ibcon#read 6, iclass 7, count 0 2006.183.08:24:31.20#ibcon#end of sib2, iclass 7, count 0 2006.183.08:24:31.20#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:24:31.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:24:31.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:24:31.20#ibcon#*before write, iclass 7, count 0 2006.183.08:24:31.20#ibcon#enter sib2, iclass 7, count 0 2006.183.08:24:31.20#ibcon#flushed, iclass 7, count 0 2006.183.08:24:31.20#ibcon#about to write, iclass 7, count 0 2006.183.08:24:31.20#ibcon#wrote, iclass 7, count 0 2006.183.08:24:31.20#ibcon#about to read 3, iclass 7, count 0 2006.183.08:24:31.24#ibcon#read 3, iclass 7, count 0 2006.183.08:24:31.24#ibcon#about to read 4, iclass 7, count 0 2006.183.08:24:31.24#ibcon#read 4, iclass 7, count 0 2006.183.08:24:31.24#ibcon#about to read 5, iclass 7, count 0 2006.183.08:24:31.24#ibcon#read 5, iclass 7, count 0 2006.183.08:24:31.24#ibcon#about to read 6, iclass 7, count 0 2006.183.08:24:31.24#ibcon#read 6, iclass 7, count 0 2006.183.08:24:31.24#ibcon#end of sib2, iclass 7, count 0 2006.183.08:24:31.24#ibcon#*after write, iclass 7, count 0 2006.183.08:24:31.24#ibcon#*before return 0, iclass 7, count 0 2006.183.08:24:31.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:31.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.183.08:24:31.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:24:31.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:24:31.24$vc4f8/vb=3,4 2006.183.08:24:31.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.183.08:24:31.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.183.08:24:31.24#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:31.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:31.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:31.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:31.29#ibcon#enter wrdev, iclass 11, count 2 2006.183.08:24:31.29#ibcon#first serial, iclass 11, count 2 2006.183.08:24:31.29#ibcon#enter sib2, iclass 11, count 2 2006.183.08:24:31.29#ibcon#flushed, iclass 11, count 2 2006.183.08:24:31.29#ibcon#about to write, iclass 11, count 2 2006.183.08:24:31.29#ibcon#wrote, iclass 11, count 2 2006.183.08:24:31.29#ibcon#about to read 3, iclass 11, count 2 2006.183.08:24:31.31#ibcon#read 3, iclass 11, count 2 2006.183.08:24:31.31#ibcon#about to read 4, iclass 11, count 2 2006.183.08:24:31.31#ibcon#read 4, iclass 11, count 2 2006.183.08:24:31.31#ibcon#about to read 5, iclass 11, count 2 2006.183.08:24:31.31#ibcon#read 5, iclass 11, count 2 2006.183.08:24:31.31#ibcon#about to read 6, iclass 11, count 2 2006.183.08:24:31.31#ibcon#read 6, iclass 11, count 2 2006.183.08:24:31.31#ibcon#end of sib2, iclass 11, count 2 2006.183.08:24:31.31#ibcon#*mode == 0, iclass 11, count 2 2006.183.08:24:31.31#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.183.08:24:31.31#ibcon#[27=AT03-04\r\n] 2006.183.08:24:31.31#ibcon#*before write, iclass 11, count 2 2006.183.08:24:31.31#ibcon#enter sib2, iclass 11, count 2 2006.183.08:24:31.31#ibcon#flushed, iclass 11, count 2 2006.183.08:24:31.31#ibcon#about to write, iclass 11, count 2 2006.183.08:24:31.31#ibcon#wrote, iclass 11, count 2 2006.183.08:24:31.31#ibcon#about to read 3, iclass 11, count 2 2006.183.08:24:31.34#ibcon#read 3, iclass 11, count 2 2006.183.08:24:31.34#ibcon#about to read 4, iclass 11, count 2 2006.183.08:24:31.34#ibcon#read 4, iclass 11, count 2 2006.183.08:24:31.34#ibcon#about to read 5, iclass 11, count 2 2006.183.08:24:31.34#ibcon#read 5, iclass 11, count 2 2006.183.08:24:31.34#ibcon#about to read 6, iclass 11, count 2 2006.183.08:24:31.34#ibcon#read 6, iclass 11, count 2 2006.183.08:24:31.34#ibcon#end of sib2, iclass 11, count 2 2006.183.08:24:31.34#ibcon#*after write, iclass 11, count 2 2006.183.08:24:31.34#ibcon#*before return 0, iclass 11, count 2 2006.183.08:24:31.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:31.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.183.08:24:31.34#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.183.08:24:31.34#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:31.34#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:31.46#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:31.46#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:31.46#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:24:31.46#ibcon#first serial, iclass 11, count 0 2006.183.08:24:31.46#ibcon#enter sib2, iclass 11, count 0 2006.183.08:24:31.46#ibcon#flushed, iclass 11, count 0 2006.183.08:24:31.46#ibcon#about to write, iclass 11, count 0 2006.183.08:24:31.46#ibcon#wrote, iclass 11, count 0 2006.183.08:24:31.46#ibcon#about to read 3, iclass 11, count 0 2006.183.08:24:31.48#ibcon#read 3, iclass 11, count 0 2006.183.08:24:31.48#ibcon#about to read 4, iclass 11, count 0 2006.183.08:24:31.48#ibcon#read 4, iclass 11, count 0 2006.183.08:24:31.48#ibcon#about to read 5, iclass 11, count 0 2006.183.08:24:31.48#ibcon#read 5, iclass 11, count 0 2006.183.08:24:31.48#ibcon#about to read 6, iclass 11, count 0 2006.183.08:24:31.48#ibcon#read 6, iclass 11, count 0 2006.183.08:24:31.48#ibcon#end of sib2, iclass 11, count 0 2006.183.08:24:31.48#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:24:31.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:24:31.48#ibcon#[27=USB\r\n] 2006.183.08:24:31.48#ibcon#*before write, iclass 11, count 0 2006.183.08:24:31.48#ibcon#enter sib2, iclass 11, count 0 2006.183.08:24:31.48#ibcon#flushed, iclass 11, count 0 2006.183.08:24:31.48#ibcon#about to write, iclass 11, count 0 2006.183.08:24:31.48#ibcon#wrote, iclass 11, count 0 2006.183.08:24:31.48#ibcon#about to read 3, iclass 11, count 0 2006.183.08:24:31.51#ibcon#read 3, iclass 11, count 0 2006.183.08:24:31.51#ibcon#about to read 4, iclass 11, count 0 2006.183.08:24:31.51#ibcon#read 4, iclass 11, count 0 2006.183.08:24:31.51#ibcon#about to read 5, iclass 11, count 0 2006.183.08:24:31.51#ibcon#read 5, iclass 11, count 0 2006.183.08:24:31.51#ibcon#about to read 6, iclass 11, count 0 2006.183.08:24:31.51#ibcon#read 6, iclass 11, count 0 2006.183.08:24:31.51#ibcon#end of sib2, iclass 11, count 0 2006.183.08:24:31.51#ibcon#*after write, iclass 11, count 0 2006.183.08:24:31.51#ibcon#*before return 0, iclass 11, count 0 2006.183.08:24:31.51#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:31.51#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.183.08:24:31.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:24:31.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:24:31.51$vc4f8/vblo=4,712.99 2006.183.08:24:31.51#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.183.08:24:31.51#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.183.08:24:31.51#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:31.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:31.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:31.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:31.51#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:24:31.51#ibcon#first serial, iclass 13, count 0 2006.183.08:24:31.51#ibcon#enter sib2, iclass 13, count 0 2006.183.08:24:31.51#ibcon#flushed, iclass 13, count 0 2006.183.08:24:31.51#ibcon#about to write, iclass 13, count 0 2006.183.08:24:31.51#ibcon#wrote, iclass 13, count 0 2006.183.08:24:31.51#ibcon#about to read 3, iclass 13, count 0 2006.183.08:24:31.53#ibcon#read 3, iclass 13, count 0 2006.183.08:24:31.53#ibcon#about to read 4, iclass 13, count 0 2006.183.08:24:31.53#ibcon#read 4, iclass 13, count 0 2006.183.08:24:31.53#ibcon#about to read 5, iclass 13, count 0 2006.183.08:24:31.53#ibcon#read 5, iclass 13, count 0 2006.183.08:24:31.53#ibcon#about to read 6, iclass 13, count 0 2006.183.08:24:31.53#ibcon#read 6, iclass 13, count 0 2006.183.08:24:31.53#ibcon#end of sib2, iclass 13, count 0 2006.183.08:24:31.53#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:24:31.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:24:31.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:24:31.53#ibcon#*before write, iclass 13, count 0 2006.183.08:24:31.53#ibcon#enter sib2, iclass 13, count 0 2006.183.08:24:31.53#ibcon#flushed, iclass 13, count 0 2006.183.08:24:31.53#ibcon#about to write, iclass 13, count 0 2006.183.08:24:31.53#ibcon#wrote, iclass 13, count 0 2006.183.08:24:31.53#ibcon#about to read 3, iclass 13, count 0 2006.183.08:24:31.57#ibcon#read 3, iclass 13, count 0 2006.183.08:24:31.57#ibcon#about to read 4, iclass 13, count 0 2006.183.08:24:31.57#ibcon#read 4, iclass 13, count 0 2006.183.08:24:31.57#ibcon#about to read 5, iclass 13, count 0 2006.183.08:24:31.57#ibcon#read 5, iclass 13, count 0 2006.183.08:24:31.57#ibcon#about to read 6, iclass 13, count 0 2006.183.08:24:31.57#ibcon#read 6, iclass 13, count 0 2006.183.08:24:31.57#ibcon#end of sib2, iclass 13, count 0 2006.183.08:24:31.57#ibcon#*after write, iclass 13, count 0 2006.183.08:24:31.57#ibcon#*before return 0, iclass 13, count 0 2006.183.08:24:31.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:31.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.183.08:24:31.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:24:31.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:24:31.57$vc4f8/vb=4,4 2006.183.08:24:31.57#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.183.08:24:31.57#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.183.08:24:31.57#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:31.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:31.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:31.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:31.63#ibcon#enter wrdev, iclass 15, count 2 2006.183.08:24:31.63#ibcon#first serial, iclass 15, count 2 2006.183.08:24:31.63#ibcon#enter sib2, iclass 15, count 2 2006.183.08:24:31.63#ibcon#flushed, iclass 15, count 2 2006.183.08:24:31.63#ibcon#about to write, iclass 15, count 2 2006.183.08:24:31.63#ibcon#wrote, iclass 15, count 2 2006.183.08:24:31.63#ibcon#about to read 3, iclass 15, count 2 2006.183.08:24:31.65#ibcon#read 3, iclass 15, count 2 2006.183.08:24:31.65#ibcon#about to read 4, iclass 15, count 2 2006.183.08:24:31.65#ibcon#read 4, iclass 15, count 2 2006.183.08:24:31.65#ibcon#about to read 5, iclass 15, count 2 2006.183.08:24:31.65#ibcon#read 5, iclass 15, count 2 2006.183.08:24:31.65#ibcon#about to read 6, iclass 15, count 2 2006.183.08:24:31.65#ibcon#read 6, iclass 15, count 2 2006.183.08:24:31.65#ibcon#end of sib2, iclass 15, count 2 2006.183.08:24:31.65#ibcon#*mode == 0, iclass 15, count 2 2006.183.08:24:31.65#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.183.08:24:31.65#ibcon#[27=AT04-04\r\n] 2006.183.08:24:31.65#ibcon#*before write, iclass 15, count 2 2006.183.08:24:31.65#ibcon#enter sib2, iclass 15, count 2 2006.183.08:24:31.65#ibcon#flushed, iclass 15, count 2 2006.183.08:24:31.65#ibcon#about to write, iclass 15, count 2 2006.183.08:24:31.65#ibcon#wrote, iclass 15, count 2 2006.183.08:24:31.65#ibcon#about to read 3, iclass 15, count 2 2006.183.08:24:31.68#ibcon#read 3, iclass 15, count 2 2006.183.08:24:31.68#ibcon#about to read 4, iclass 15, count 2 2006.183.08:24:31.68#ibcon#read 4, iclass 15, count 2 2006.183.08:24:31.68#ibcon#about to read 5, iclass 15, count 2 2006.183.08:24:31.68#ibcon#read 5, iclass 15, count 2 2006.183.08:24:31.68#ibcon#about to read 6, iclass 15, count 2 2006.183.08:24:31.68#ibcon#read 6, iclass 15, count 2 2006.183.08:24:31.68#ibcon#end of sib2, iclass 15, count 2 2006.183.08:24:31.68#ibcon#*after write, iclass 15, count 2 2006.183.08:24:31.68#ibcon#*before return 0, iclass 15, count 2 2006.183.08:24:31.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:31.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.183.08:24:31.68#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.183.08:24:31.68#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:31.68#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:31.80#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:31.80#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:31.80#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:24:31.80#ibcon#first serial, iclass 15, count 0 2006.183.08:24:31.80#ibcon#enter sib2, iclass 15, count 0 2006.183.08:24:31.80#ibcon#flushed, iclass 15, count 0 2006.183.08:24:31.80#ibcon#about to write, iclass 15, count 0 2006.183.08:24:31.80#ibcon#wrote, iclass 15, count 0 2006.183.08:24:31.80#ibcon#about to read 3, iclass 15, count 0 2006.183.08:24:31.82#ibcon#read 3, iclass 15, count 0 2006.183.08:24:31.82#ibcon#about to read 4, iclass 15, count 0 2006.183.08:24:31.82#ibcon#read 4, iclass 15, count 0 2006.183.08:24:31.82#ibcon#about to read 5, iclass 15, count 0 2006.183.08:24:31.82#ibcon#read 5, iclass 15, count 0 2006.183.08:24:31.82#ibcon#about to read 6, iclass 15, count 0 2006.183.08:24:31.82#ibcon#read 6, iclass 15, count 0 2006.183.08:24:31.82#ibcon#end of sib2, iclass 15, count 0 2006.183.08:24:31.82#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:24:31.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:24:31.82#ibcon#[27=USB\r\n] 2006.183.08:24:31.82#ibcon#*before write, iclass 15, count 0 2006.183.08:24:31.82#ibcon#enter sib2, iclass 15, count 0 2006.183.08:24:31.82#ibcon#flushed, iclass 15, count 0 2006.183.08:24:31.82#ibcon#about to write, iclass 15, count 0 2006.183.08:24:31.82#ibcon#wrote, iclass 15, count 0 2006.183.08:24:31.82#ibcon#about to read 3, iclass 15, count 0 2006.183.08:24:31.85#ibcon#read 3, iclass 15, count 0 2006.183.08:24:31.85#ibcon#about to read 4, iclass 15, count 0 2006.183.08:24:31.85#ibcon#read 4, iclass 15, count 0 2006.183.08:24:31.85#ibcon#about to read 5, iclass 15, count 0 2006.183.08:24:31.85#ibcon#read 5, iclass 15, count 0 2006.183.08:24:31.85#ibcon#about to read 6, iclass 15, count 0 2006.183.08:24:31.85#ibcon#read 6, iclass 15, count 0 2006.183.08:24:31.85#ibcon#end of sib2, iclass 15, count 0 2006.183.08:24:31.85#ibcon#*after write, iclass 15, count 0 2006.183.08:24:31.85#ibcon#*before return 0, iclass 15, count 0 2006.183.08:24:31.85#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:31.85#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.183.08:24:31.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:24:31.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:24:31.85$vc4f8/vblo=5,744.99 2006.183.08:24:31.85#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.183.08:24:31.85#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.183.08:24:31.85#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:31.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:31.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:31.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:31.85#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:24:31.85#ibcon#first serial, iclass 17, count 0 2006.183.08:24:31.85#ibcon#enter sib2, iclass 17, count 0 2006.183.08:24:31.85#ibcon#flushed, iclass 17, count 0 2006.183.08:24:31.85#ibcon#about to write, iclass 17, count 0 2006.183.08:24:31.85#ibcon#wrote, iclass 17, count 0 2006.183.08:24:31.85#ibcon#about to read 3, iclass 17, count 0 2006.183.08:24:31.88#ibcon#read 3, iclass 17, count 0 2006.183.08:24:31.88#ibcon#about to read 4, iclass 17, count 0 2006.183.08:24:31.88#ibcon#read 4, iclass 17, count 0 2006.183.08:24:31.88#ibcon#about to read 5, iclass 17, count 0 2006.183.08:24:31.88#ibcon#read 5, iclass 17, count 0 2006.183.08:24:31.88#ibcon#about to read 6, iclass 17, count 0 2006.183.08:24:31.88#ibcon#read 6, iclass 17, count 0 2006.183.08:24:31.88#ibcon#end of sib2, iclass 17, count 0 2006.183.08:24:31.88#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:24:31.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:24:31.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:24:31.88#ibcon#*before write, iclass 17, count 0 2006.183.08:24:31.88#ibcon#enter sib2, iclass 17, count 0 2006.183.08:24:31.88#ibcon#flushed, iclass 17, count 0 2006.183.08:24:31.88#ibcon#about to write, iclass 17, count 0 2006.183.08:24:31.88#ibcon#wrote, iclass 17, count 0 2006.183.08:24:31.88#ibcon#about to read 3, iclass 17, count 0 2006.183.08:24:31.92#ibcon#read 3, iclass 17, count 0 2006.183.08:24:31.92#ibcon#about to read 4, iclass 17, count 0 2006.183.08:24:31.92#ibcon#read 4, iclass 17, count 0 2006.183.08:24:31.92#ibcon#about to read 5, iclass 17, count 0 2006.183.08:24:31.92#ibcon#read 5, iclass 17, count 0 2006.183.08:24:31.92#ibcon#about to read 6, iclass 17, count 0 2006.183.08:24:31.92#ibcon#read 6, iclass 17, count 0 2006.183.08:24:31.92#ibcon#end of sib2, iclass 17, count 0 2006.183.08:24:31.92#ibcon#*after write, iclass 17, count 0 2006.183.08:24:31.92#ibcon#*before return 0, iclass 17, count 0 2006.183.08:24:31.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:31.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.183.08:24:31.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:24:31.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:24:31.92$vc4f8/vb=5,4 2006.183.08:24:31.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.183.08:24:31.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.183.08:24:31.92#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:31.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:31.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:31.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:31.97#ibcon#enter wrdev, iclass 19, count 2 2006.183.08:24:31.97#ibcon#first serial, iclass 19, count 2 2006.183.08:24:31.97#ibcon#enter sib2, iclass 19, count 2 2006.183.08:24:31.97#ibcon#flushed, iclass 19, count 2 2006.183.08:24:31.97#ibcon#about to write, iclass 19, count 2 2006.183.08:24:31.97#ibcon#wrote, iclass 19, count 2 2006.183.08:24:31.97#ibcon#about to read 3, iclass 19, count 2 2006.183.08:24:31.99#ibcon#read 3, iclass 19, count 2 2006.183.08:24:31.99#ibcon#about to read 4, iclass 19, count 2 2006.183.08:24:31.99#ibcon#read 4, iclass 19, count 2 2006.183.08:24:31.99#ibcon#about to read 5, iclass 19, count 2 2006.183.08:24:31.99#ibcon#read 5, iclass 19, count 2 2006.183.08:24:31.99#ibcon#about to read 6, iclass 19, count 2 2006.183.08:24:31.99#ibcon#read 6, iclass 19, count 2 2006.183.08:24:31.99#ibcon#end of sib2, iclass 19, count 2 2006.183.08:24:31.99#ibcon#*mode == 0, iclass 19, count 2 2006.183.08:24:31.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.183.08:24:31.99#ibcon#[27=AT05-04\r\n] 2006.183.08:24:31.99#ibcon#*before write, iclass 19, count 2 2006.183.08:24:31.99#ibcon#enter sib2, iclass 19, count 2 2006.183.08:24:31.99#ibcon#flushed, iclass 19, count 2 2006.183.08:24:31.99#ibcon#about to write, iclass 19, count 2 2006.183.08:24:31.99#ibcon#wrote, iclass 19, count 2 2006.183.08:24:31.99#ibcon#about to read 3, iclass 19, count 2 2006.183.08:24:32.02#ibcon#read 3, iclass 19, count 2 2006.183.08:24:32.02#ibcon#about to read 4, iclass 19, count 2 2006.183.08:24:32.02#ibcon#read 4, iclass 19, count 2 2006.183.08:24:32.02#ibcon#about to read 5, iclass 19, count 2 2006.183.08:24:32.02#ibcon#read 5, iclass 19, count 2 2006.183.08:24:32.02#ibcon#about to read 6, iclass 19, count 2 2006.183.08:24:32.02#ibcon#read 6, iclass 19, count 2 2006.183.08:24:32.02#ibcon#end of sib2, iclass 19, count 2 2006.183.08:24:32.02#ibcon#*after write, iclass 19, count 2 2006.183.08:24:32.02#ibcon#*before return 0, iclass 19, count 2 2006.183.08:24:32.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:32.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.183.08:24:32.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.183.08:24:32.02#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:32.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:32.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:32.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:32.14#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:24:32.14#ibcon#first serial, iclass 19, count 0 2006.183.08:24:32.14#ibcon#enter sib2, iclass 19, count 0 2006.183.08:24:32.14#ibcon#flushed, iclass 19, count 0 2006.183.08:24:32.14#ibcon#about to write, iclass 19, count 0 2006.183.08:24:32.14#ibcon#wrote, iclass 19, count 0 2006.183.08:24:32.14#ibcon#about to read 3, iclass 19, count 0 2006.183.08:24:32.16#ibcon#read 3, iclass 19, count 0 2006.183.08:24:32.16#ibcon#about to read 4, iclass 19, count 0 2006.183.08:24:32.16#ibcon#read 4, iclass 19, count 0 2006.183.08:24:32.16#ibcon#about to read 5, iclass 19, count 0 2006.183.08:24:32.16#ibcon#read 5, iclass 19, count 0 2006.183.08:24:32.16#ibcon#about to read 6, iclass 19, count 0 2006.183.08:24:32.16#ibcon#read 6, iclass 19, count 0 2006.183.08:24:32.16#ibcon#end of sib2, iclass 19, count 0 2006.183.08:24:32.16#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:24:32.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:24:32.16#ibcon#[27=USB\r\n] 2006.183.08:24:32.16#ibcon#*before write, iclass 19, count 0 2006.183.08:24:32.16#ibcon#enter sib2, iclass 19, count 0 2006.183.08:24:32.16#ibcon#flushed, iclass 19, count 0 2006.183.08:24:32.16#ibcon#about to write, iclass 19, count 0 2006.183.08:24:32.16#ibcon#wrote, iclass 19, count 0 2006.183.08:24:32.16#ibcon#about to read 3, iclass 19, count 0 2006.183.08:24:32.19#ibcon#read 3, iclass 19, count 0 2006.183.08:24:32.19#ibcon#about to read 4, iclass 19, count 0 2006.183.08:24:32.19#ibcon#read 4, iclass 19, count 0 2006.183.08:24:32.19#ibcon#about to read 5, iclass 19, count 0 2006.183.08:24:32.19#ibcon#read 5, iclass 19, count 0 2006.183.08:24:32.19#ibcon#about to read 6, iclass 19, count 0 2006.183.08:24:32.19#ibcon#read 6, iclass 19, count 0 2006.183.08:24:32.19#ibcon#end of sib2, iclass 19, count 0 2006.183.08:24:32.19#ibcon#*after write, iclass 19, count 0 2006.183.08:24:32.19#ibcon#*before return 0, iclass 19, count 0 2006.183.08:24:32.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:32.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.183.08:24:32.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:24:32.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:24:32.19$vc4f8/vblo=6,752.99 2006.183.08:24:32.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.183.08:24:32.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.183.08:24:32.19#ibcon#ireg 17 cls_cnt 0 2006.183.08:24:32.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:32.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:32.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:32.19#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:24:32.19#ibcon#first serial, iclass 21, count 0 2006.183.08:24:32.19#ibcon#enter sib2, iclass 21, count 0 2006.183.08:24:32.19#ibcon#flushed, iclass 21, count 0 2006.183.08:24:32.19#ibcon#about to write, iclass 21, count 0 2006.183.08:24:32.19#ibcon#wrote, iclass 21, count 0 2006.183.08:24:32.19#ibcon#about to read 3, iclass 21, count 0 2006.183.08:24:32.21#ibcon#read 3, iclass 21, count 0 2006.183.08:24:32.21#ibcon#about to read 4, iclass 21, count 0 2006.183.08:24:32.21#ibcon#read 4, iclass 21, count 0 2006.183.08:24:32.21#ibcon#about to read 5, iclass 21, count 0 2006.183.08:24:32.21#ibcon#read 5, iclass 21, count 0 2006.183.08:24:32.21#ibcon#about to read 6, iclass 21, count 0 2006.183.08:24:32.21#ibcon#read 6, iclass 21, count 0 2006.183.08:24:32.21#ibcon#end of sib2, iclass 21, count 0 2006.183.08:24:32.21#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:24:32.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:24:32.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:24:32.21#ibcon#*before write, iclass 21, count 0 2006.183.08:24:32.21#ibcon#enter sib2, iclass 21, count 0 2006.183.08:24:32.21#ibcon#flushed, iclass 21, count 0 2006.183.08:24:32.21#ibcon#about to write, iclass 21, count 0 2006.183.08:24:32.21#ibcon#wrote, iclass 21, count 0 2006.183.08:24:32.21#ibcon#about to read 3, iclass 21, count 0 2006.183.08:24:32.25#ibcon#read 3, iclass 21, count 0 2006.183.08:24:32.25#ibcon#about to read 4, iclass 21, count 0 2006.183.08:24:32.25#ibcon#read 4, iclass 21, count 0 2006.183.08:24:32.25#ibcon#about to read 5, iclass 21, count 0 2006.183.08:24:32.25#ibcon#read 5, iclass 21, count 0 2006.183.08:24:32.25#ibcon#about to read 6, iclass 21, count 0 2006.183.08:24:32.25#ibcon#read 6, iclass 21, count 0 2006.183.08:24:32.25#ibcon#end of sib2, iclass 21, count 0 2006.183.08:24:32.25#ibcon#*after write, iclass 21, count 0 2006.183.08:24:32.25#ibcon#*before return 0, iclass 21, count 0 2006.183.08:24:32.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:32.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.183.08:24:32.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:24:32.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:24:32.25$vc4f8/vb=6,4 2006.183.08:24:32.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.183.08:24:32.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.183.08:24:32.25#ibcon#ireg 11 cls_cnt 2 2006.183.08:24:32.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:32.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:32.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:32.31#ibcon#enter wrdev, iclass 23, count 2 2006.183.08:24:32.31#ibcon#first serial, iclass 23, count 2 2006.183.08:24:32.31#ibcon#enter sib2, iclass 23, count 2 2006.183.08:24:32.31#ibcon#flushed, iclass 23, count 2 2006.183.08:24:32.31#ibcon#about to write, iclass 23, count 2 2006.183.08:24:32.31#ibcon#wrote, iclass 23, count 2 2006.183.08:24:32.31#ibcon#about to read 3, iclass 23, count 2 2006.183.08:24:32.33#ibcon#read 3, iclass 23, count 2 2006.183.08:24:32.33#ibcon#about to read 4, iclass 23, count 2 2006.183.08:24:32.33#ibcon#read 4, iclass 23, count 2 2006.183.08:24:32.33#ibcon#about to read 5, iclass 23, count 2 2006.183.08:24:32.33#ibcon#read 5, iclass 23, count 2 2006.183.08:24:32.33#ibcon#about to read 6, iclass 23, count 2 2006.183.08:24:32.33#ibcon#read 6, iclass 23, count 2 2006.183.08:24:32.33#ibcon#end of sib2, iclass 23, count 2 2006.183.08:24:32.33#ibcon#*mode == 0, iclass 23, count 2 2006.183.08:24:32.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.183.08:24:32.33#ibcon#[27=AT06-04\r\n] 2006.183.08:24:32.33#ibcon#*before write, iclass 23, count 2 2006.183.08:24:32.33#ibcon#enter sib2, iclass 23, count 2 2006.183.08:24:32.33#ibcon#flushed, iclass 23, count 2 2006.183.08:24:32.33#ibcon#about to write, iclass 23, count 2 2006.183.08:24:32.33#ibcon#wrote, iclass 23, count 2 2006.183.08:24:32.33#ibcon#about to read 3, iclass 23, count 2 2006.183.08:24:32.36#ibcon#read 3, iclass 23, count 2 2006.183.08:24:32.36#ibcon#about to read 4, iclass 23, count 2 2006.183.08:24:32.36#ibcon#read 4, iclass 23, count 2 2006.183.08:24:32.36#ibcon#about to read 5, iclass 23, count 2 2006.183.08:24:32.36#ibcon#read 5, iclass 23, count 2 2006.183.08:24:32.36#ibcon#about to read 6, iclass 23, count 2 2006.183.08:24:32.36#ibcon#read 6, iclass 23, count 2 2006.183.08:24:32.36#ibcon#end of sib2, iclass 23, count 2 2006.183.08:24:32.36#ibcon#*after write, iclass 23, count 2 2006.183.08:24:32.36#ibcon#*before return 0, iclass 23, count 2 2006.183.08:24:32.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:32.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.183.08:24:32.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.183.08:24:32.36#ibcon#ireg 7 cls_cnt 0 2006.183.08:24:32.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:32.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:32.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:32.48#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:24:32.48#ibcon#first serial, iclass 23, count 0 2006.183.08:24:32.48#ibcon#enter sib2, iclass 23, count 0 2006.183.08:24:32.48#ibcon#flushed, iclass 23, count 0 2006.183.08:24:32.48#ibcon#about to write, iclass 23, count 0 2006.183.08:24:32.48#ibcon#wrote, iclass 23, count 0 2006.183.08:24:32.48#ibcon#about to read 3, iclass 23, count 0 2006.183.08:24:32.50#ibcon#read 3, iclass 23, count 0 2006.183.08:24:32.50#ibcon#about to read 4, iclass 23, count 0 2006.183.08:24:32.50#ibcon#read 4, iclass 23, count 0 2006.183.08:24:32.50#ibcon#about to read 5, iclass 23, count 0 2006.183.08:24:32.50#ibcon#read 5, iclass 23, count 0 2006.183.08:24:32.50#ibcon#about to read 6, iclass 23, count 0 2006.183.08:24:32.50#ibcon#read 6, iclass 23, count 0 2006.183.08:24:32.50#ibcon#end of sib2, iclass 23, count 0 2006.183.08:24:32.50#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:24:32.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:24:32.50#ibcon#[27=USB\r\n] 2006.183.08:24:32.50#ibcon#*before write, iclass 23, count 0 2006.183.08:24:32.50#ibcon#enter sib2, iclass 23, count 0 2006.183.08:24:32.50#ibcon#flushed, iclass 23, count 0 2006.183.08:24:32.50#ibcon#about to write, iclass 23, count 0 2006.183.08:24:32.50#ibcon#wrote, iclass 23, count 0 2006.183.08:24:32.50#ibcon#about to read 3, iclass 23, count 0 2006.183.08:24:32.53#ibcon#read 3, iclass 23, count 0 2006.183.08:24:32.53#ibcon#about to read 4, iclass 23, count 0 2006.183.08:24:32.53#ibcon#read 4, iclass 23, count 0 2006.183.08:24:32.53#ibcon#about to read 5, iclass 23, count 0 2006.183.08:24:32.53#ibcon#read 5, iclass 23, count 0 2006.183.08:24:32.53#ibcon#about to read 6, iclass 23, count 0 2006.183.08:24:32.53#ibcon#read 6, iclass 23, count 0 2006.183.08:24:32.53#ibcon#end of sib2, iclass 23, count 0 2006.183.08:24:32.53#ibcon#*after write, iclass 23, count 0 2006.183.08:24:32.53#ibcon#*before return 0, iclass 23, count 0 2006.183.08:24:32.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:32.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.183.08:24:32.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:24:32.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:24:32.53$vc4f8/vabw=wide 2006.183.08:24:32.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.183.08:24:32.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.183.08:24:32.53#ibcon#ireg 8 cls_cnt 0 2006.183.08:24:32.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:32.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:32.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:32.53#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:24:32.53#ibcon#first serial, iclass 25, count 0 2006.183.08:24:32.53#ibcon#enter sib2, iclass 25, count 0 2006.183.08:24:32.53#ibcon#flushed, iclass 25, count 0 2006.183.08:24:32.53#ibcon#about to write, iclass 25, count 0 2006.183.08:24:32.53#ibcon#wrote, iclass 25, count 0 2006.183.08:24:32.53#ibcon#about to read 3, iclass 25, count 0 2006.183.08:24:32.55#ibcon#read 3, iclass 25, count 0 2006.183.08:24:32.55#ibcon#about to read 4, iclass 25, count 0 2006.183.08:24:32.55#ibcon#read 4, iclass 25, count 0 2006.183.08:24:32.55#ibcon#about to read 5, iclass 25, count 0 2006.183.08:24:32.55#ibcon#read 5, iclass 25, count 0 2006.183.08:24:32.55#ibcon#about to read 6, iclass 25, count 0 2006.183.08:24:32.55#ibcon#read 6, iclass 25, count 0 2006.183.08:24:32.55#ibcon#end of sib2, iclass 25, count 0 2006.183.08:24:32.55#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:24:32.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:24:32.55#ibcon#[25=BW32\r\n] 2006.183.08:24:32.55#ibcon#*before write, iclass 25, count 0 2006.183.08:24:32.55#ibcon#enter sib2, iclass 25, count 0 2006.183.08:24:32.55#ibcon#flushed, iclass 25, count 0 2006.183.08:24:32.55#ibcon#about to write, iclass 25, count 0 2006.183.08:24:32.55#ibcon#wrote, iclass 25, count 0 2006.183.08:24:32.55#ibcon#about to read 3, iclass 25, count 0 2006.183.08:24:32.58#ibcon#read 3, iclass 25, count 0 2006.183.08:24:32.58#ibcon#about to read 4, iclass 25, count 0 2006.183.08:24:32.58#ibcon#read 4, iclass 25, count 0 2006.183.08:24:32.58#ibcon#about to read 5, iclass 25, count 0 2006.183.08:24:32.58#ibcon#read 5, iclass 25, count 0 2006.183.08:24:32.58#ibcon#about to read 6, iclass 25, count 0 2006.183.08:24:32.58#ibcon#read 6, iclass 25, count 0 2006.183.08:24:32.58#ibcon#end of sib2, iclass 25, count 0 2006.183.08:24:32.58#ibcon#*after write, iclass 25, count 0 2006.183.08:24:32.58#ibcon#*before return 0, iclass 25, count 0 2006.183.08:24:32.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:32.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.183.08:24:32.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:24:32.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:24:32.58$vc4f8/vbbw=wide 2006.183.08:24:32.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.183.08:24:32.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.183.08:24:32.58#ibcon#ireg 8 cls_cnt 0 2006.183.08:24:32.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:24:32.59#abcon#<5=/10 1.9 4.9 28.26 87 996.7\r\n> 2006.183.08:24:32.61#abcon#{5=INTERFACE CLEAR} 2006.183.08:24:32.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:24:32.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:24:32.65#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:24:32.65#ibcon#first serial, iclass 28, count 0 2006.183.08:24:32.65#ibcon#enter sib2, iclass 28, count 0 2006.183.08:24:32.65#ibcon#flushed, iclass 28, count 0 2006.183.08:24:32.65#ibcon#about to write, iclass 28, count 0 2006.183.08:24:32.65#ibcon#wrote, iclass 28, count 0 2006.183.08:24:32.65#ibcon#about to read 3, iclass 28, count 0 2006.183.08:24:32.67#ibcon#read 3, iclass 28, count 0 2006.183.08:24:32.67#ibcon#about to read 4, iclass 28, count 0 2006.183.08:24:32.67#ibcon#read 4, iclass 28, count 0 2006.183.08:24:32.67#ibcon#about to read 5, iclass 28, count 0 2006.183.08:24:32.67#ibcon#read 5, iclass 28, count 0 2006.183.08:24:32.67#ibcon#about to read 6, iclass 28, count 0 2006.183.08:24:32.67#ibcon#read 6, iclass 28, count 0 2006.183.08:24:32.67#ibcon#end of sib2, iclass 28, count 0 2006.183.08:24:32.67#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:24:32.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:24:32.67#ibcon#[27=BW32\r\n] 2006.183.08:24:32.67#ibcon#*before write, iclass 28, count 0 2006.183.08:24:32.67#ibcon#enter sib2, iclass 28, count 0 2006.183.08:24:32.67#ibcon#flushed, iclass 28, count 0 2006.183.08:24:32.67#ibcon#about to write, iclass 28, count 0 2006.183.08:24:32.67#ibcon#wrote, iclass 28, count 0 2006.183.08:24:32.67#ibcon#about to read 3, iclass 28, count 0 2006.183.08:24:32.67#abcon#[5=S1D000X0/0*\r\n] 2006.183.08:24:32.70#ibcon#read 3, iclass 28, count 0 2006.183.08:24:32.70#ibcon#about to read 4, iclass 28, count 0 2006.183.08:24:32.70#ibcon#read 4, iclass 28, count 0 2006.183.08:24:32.70#ibcon#about to read 5, iclass 28, count 0 2006.183.08:24:32.70#ibcon#read 5, iclass 28, count 0 2006.183.08:24:32.70#ibcon#about to read 6, iclass 28, count 0 2006.183.08:24:32.70#ibcon#read 6, iclass 28, count 0 2006.183.08:24:32.70#ibcon#end of sib2, iclass 28, count 0 2006.183.08:24:32.70#ibcon#*after write, iclass 28, count 0 2006.183.08:24:32.70#ibcon#*before return 0, iclass 28, count 0 2006.183.08:24:32.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:24:32.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.183.08:24:32.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:24:32.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:24:32.70$4f8m12a/ifd4f 2006.183.08:24:32.70$ifd4f/lo= 2006.183.08:24:32.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:24:32.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:24:32.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:24:32.70$ifd4f/patch= 2006.183.08:24:32.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:24:32.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:24:32.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:24:32.70$4f8m12a/"form=m,16.000,1:2 2006.183.08:24:32.70$4f8m12a/"tpicd 2006.183.08:24:32.70$4f8m12a/echo=off 2006.183.08:24:32.70$4f8m12a/xlog=off 2006.183.08:24:32.70:!2006.183.08:25:20 2006.183.08:25:02.14#trakl#Source acquired 2006.183.08:25:03.14#flagr#flagr/antenna,acquired 2006.183.08:25:20.00:preob 2006.183.08:25:20.14/onsource/TRACKING 2006.183.08:25:20.14:!2006.183.08:25:30 2006.183.08:25:30.00:data_valid=on 2006.183.08:25:30.00:midob 2006.183.08:25:30.14/onsource/TRACKING 2006.183.08:25:30.14/wx/28.26,996.7,87 2006.183.08:25:30.29/cable/+6.4499E-03 2006.183.08:25:31.38/va/01,08,usb,yes,29,31 2006.183.08:25:31.38/va/02,07,usb,yes,29,31 2006.183.08:25:31.38/va/03,06,usb,yes,31,31 2006.183.08:25:31.38/va/04,07,usb,yes,30,32 2006.183.08:25:31.38/va/05,07,usb,yes,32,34 2006.183.08:25:31.38/va/06,06,usb,yes,31,31 2006.183.08:25:31.38/va/07,06,usb,yes,32,31 2006.183.08:25:31.38/va/08,07,usb,yes,30,29 2006.183.08:25:31.61/valo/01,532.99,yes,locked 2006.183.08:25:31.61/valo/02,572.99,yes,locked 2006.183.08:25:31.61/valo/03,672.99,yes,locked 2006.183.08:25:31.61/valo/04,832.99,yes,locked 2006.183.08:25:31.61/valo/05,652.99,yes,locked 2006.183.08:25:31.61/valo/06,772.99,yes,locked 2006.183.08:25:31.61/valo/07,832.99,yes,locked 2006.183.08:25:31.61/valo/08,852.99,yes,locked 2006.183.08:25:32.70/vb/01,04,usb,yes,29,28 2006.183.08:25:32.70/vb/02,04,usb,yes,31,32 2006.183.08:25:32.70/vb/03,04,usb,yes,27,31 2006.183.08:25:32.70/vb/04,04,usb,yes,28,28 2006.183.08:25:32.70/vb/05,04,usb,yes,27,31 2006.183.08:25:32.70/vb/06,04,usb,yes,28,31 2006.183.08:25:32.70/vb/07,04,usb,yes,30,30 2006.183.08:25:32.70/vb/08,04,usb,yes,28,31 2006.183.08:25:32.93/vblo/01,632.99,yes,locked 2006.183.08:25:32.93/vblo/02,640.99,yes,locked 2006.183.08:25:32.93/vblo/03,656.99,yes,locked 2006.183.08:25:32.93/vblo/04,712.99,yes,locked 2006.183.08:25:32.93/vblo/05,744.99,yes,locked 2006.183.08:25:32.93/vblo/06,752.99,yes,locked 2006.183.08:25:32.93/vblo/07,734.99,yes,locked 2006.183.08:25:32.93/vblo/08,744.99,yes,locked 2006.183.08:25:33.08/vabw/8 2006.183.08:25:33.23/vbbw/8 2006.183.08:25:33.40/xfe/off,on,14.5 2006.183.08:25:33.79/ifatt/23,28,28,28 2006.183.08:25:34.08/fmout-gps/S +3.34E-07 2006.183.08:25:34.12:!2006.183.08:26:30 2006.183.08:26:30.00:data_valid=off 2006.183.08:26:30.00:postob 2006.183.08:26:30.08/cable/+6.4500E-03 2006.183.08:26:30.08/wx/28.25,996.7,87 2006.183.08:26:31.08/fmout-gps/S +3.34E-07 2006.183.08:26:31.08:scan_name=183-0827,k06183,60 2006.183.08:26:31.09:source=3c418,203837.03,511912.7,2000.0,cw 2006.183.08:26:31.14#flagr#flagr/antenna,new-source 2006.183.08:26:32.14:checkk5 2006.183.08:26:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:26:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:26:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:26:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:26:34.01/chk_obsdata//k5ts1/T1830825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:26:34.38/chk_obsdata//k5ts2/T1830825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:26:34.74/chk_obsdata//k5ts3/T1830825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:26:35.11/chk_obsdata//k5ts4/T1830825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:26:35.80/k5log//k5ts1_log_newline 2006.183.08:26:36.49/k5log//k5ts2_log_newline 2006.183.08:26:37.18/k5log//k5ts3_log_newline 2006.183.08:26:37.88/k5log//k5ts4_log_newline 2006.183.08:26:37.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:26:37.90:4f8m12a=3 2006.183.08:26:37.90$4f8m12a/echo=on 2006.183.08:26:37.90$4f8m12a/pcalon 2006.183.08:26:37.91$pcalon/"no phase cal control is implemented here 2006.183.08:26:37.91$4f8m12a/"tpicd=stop 2006.183.08:26:37.91$4f8m12a/vc4f8 2006.183.08:26:37.91$vc4f8/valo=1,532.99 2006.183.08:26:37.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.08:26:37.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.08:26:37.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:37.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:37.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:37.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:37.91#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:26:37.91#ibcon#first serial, iclass 10, count 0 2006.183.08:26:37.91#ibcon#enter sib2, iclass 10, count 0 2006.183.08:26:37.91#ibcon#flushed, iclass 10, count 0 2006.183.08:26:37.91#ibcon#about to write, iclass 10, count 0 2006.183.08:26:37.91#ibcon#wrote, iclass 10, count 0 2006.183.08:26:37.91#ibcon#about to read 3, iclass 10, count 0 2006.183.08:26:37.95#ibcon#read 3, iclass 10, count 0 2006.183.08:26:37.95#ibcon#about to read 4, iclass 10, count 0 2006.183.08:26:37.95#ibcon#read 4, iclass 10, count 0 2006.183.08:26:37.95#ibcon#about to read 5, iclass 10, count 0 2006.183.08:26:37.95#ibcon#read 5, iclass 10, count 0 2006.183.08:26:37.95#ibcon#about to read 6, iclass 10, count 0 2006.183.08:26:37.95#ibcon#read 6, iclass 10, count 0 2006.183.08:26:37.95#ibcon#end of sib2, iclass 10, count 0 2006.183.08:26:37.95#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:26:37.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:26:37.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:26:37.95#ibcon#*before write, iclass 10, count 0 2006.183.08:26:37.95#ibcon#enter sib2, iclass 10, count 0 2006.183.08:26:37.95#ibcon#flushed, iclass 10, count 0 2006.183.08:26:37.95#ibcon#about to write, iclass 10, count 0 2006.183.08:26:37.95#ibcon#wrote, iclass 10, count 0 2006.183.08:26:37.95#ibcon#about to read 3, iclass 10, count 0 2006.183.08:26:38.00#ibcon#read 3, iclass 10, count 0 2006.183.08:26:38.00#ibcon#about to read 4, iclass 10, count 0 2006.183.08:26:38.00#ibcon#read 4, iclass 10, count 0 2006.183.08:26:38.00#ibcon#about to read 5, iclass 10, count 0 2006.183.08:26:38.00#ibcon#read 5, iclass 10, count 0 2006.183.08:26:38.00#ibcon#about to read 6, iclass 10, count 0 2006.183.08:26:38.00#ibcon#read 6, iclass 10, count 0 2006.183.08:26:38.00#ibcon#end of sib2, iclass 10, count 0 2006.183.08:26:38.00#ibcon#*after write, iclass 10, count 0 2006.183.08:26:38.00#ibcon#*before return 0, iclass 10, count 0 2006.183.08:26:38.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:38.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:38.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:26:38.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:26:38.00$vc4f8/va=1,8 2006.183.08:26:38.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.08:26:38.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.08:26:38.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:38.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:38.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:38.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:38.00#ibcon#enter wrdev, iclass 12, count 2 2006.183.08:26:38.00#ibcon#first serial, iclass 12, count 2 2006.183.08:26:38.00#ibcon#enter sib2, iclass 12, count 2 2006.183.08:26:38.00#ibcon#flushed, iclass 12, count 2 2006.183.08:26:38.00#ibcon#about to write, iclass 12, count 2 2006.183.08:26:38.00#ibcon#wrote, iclass 12, count 2 2006.183.08:26:38.00#ibcon#about to read 3, iclass 12, count 2 2006.183.08:26:38.03#ibcon#read 3, iclass 12, count 2 2006.183.08:26:38.03#ibcon#about to read 4, iclass 12, count 2 2006.183.08:26:38.03#ibcon#read 4, iclass 12, count 2 2006.183.08:26:38.03#ibcon#about to read 5, iclass 12, count 2 2006.183.08:26:38.03#ibcon#read 5, iclass 12, count 2 2006.183.08:26:38.03#ibcon#about to read 6, iclass 12, count 2 2006.183.08:26:38.03#ibcon#read 6, iclass 12, count 2 2006.183.08:26:38.03#ibcon#end of sib2, iclass 12, count 2 2006.183.08:26:38.03#ibcon#*mode == 0, iclass 12, count 2 2006.183.08:26:38.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.08:26:38.03#ibcon#[25=AT01-08\r\n] 2006.183.08:26:38.03#ibcon#*before write, iclass 12, count 2 2006.183.08:26:38.03#ibcon#enter sib2, iclass 12, count 2 2006.183.08:26:38.03#ibcon#flushed, iclass 12, count 2 2006.183.08:26:38.03#ibcon#about to write, iclass 12, count 2 2006.183.08:26:38.03#ibcon#wrote, iclass 12, count 2 2006.183.08:26:38.03#ibcon#about to read 3, iclass 12, count 2 2006.183.08:26:38.06#ibcon#read 3, iclass 12, count 2 2006.183.08:26:38.06#ibcon#about to read 4, iclass 12, count 2 2006.183.08:26:38.06#ibcon#read 4, iclass 12, count 2 2006.183.08:26:38.06#ibcon#about to read 5, iclass 12, count 2 2006.183.08:26:38.06#ibcon#read 5, iclass 12, count 2 2006.183.08:26:38.06#ibcon#about to read 6, iclass 12, count 2 2006.183.08:26:38.06#ibcon#read 6, iclass 12, count 2 2006.183.08:26:38.06#ibcon#end of sib2, iclass 12, count 2 2006.183.08:26:38.06#ibcon#*after write, iclass 12, count 2 2006.183.08:26:38.06#ibcon#*before return 0, iclass 12, count 2 2006.183.08:26:38.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:38.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:38.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.08:26:38.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:38.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:38.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:38.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:38.18#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:26:38.18#ibcon#first serial, iclass 12, count 0 2006.183.08:26:38.18#ibcon#enter sib2, iclass 12, count 0 2006.183.08:26:38.18#ibcon#flushed, iclass 12, count 0 2006.183.08:26:38.18#ibcon#about to write, iclass 12, count 0 2006.183.08:26:38.18#ibcon#wrote, iclass 12, count 0 2006.183.08:26:38.18#ibcon#about to read 3, iclass 12, count 0 2006.183.08:26:38.20#ibcon#read 3, iclass 12, count 0 2006.183.08:26:38.20#ibcon#about to read 4, iclass 12, count 0 2006.183.08:26:38.20#ibcon#read 4, iclass 12, count 0 2006.183.08:26:38.20#ibcon#about to read 5, iclass 12, count 0 2006.183.08:26:38.20#ibcon#read 5, iclass 12, count 0 2006.183.08:26:38.20#ibcon#about to read 6, iclass 12, count 0 2006.183.08:26:38.20#ibcon#read 6, iclass 12, count 0 2006.183.08:26:38.20#ibcon#end of sib2, iclass 12, count 0 2006.183.08:26:38.20#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:26:38.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:26:38.20#ibcon#[25=USB\r\n] 2006.183.08:26:38.20#ibcon#*before write, iclass 12, count 0 2006.183.08:26:38.20#ibcon#enter sib2, iclass 12, count 0 2006.183.08:26:38.20#ibcon#flushed, iclass 12, count 0 2006.183.08:26:38.20#ibcon#about to write, iclass 12, count 0 2006.183.08:26:38.20#ibcon#wrote, iclass 12, count 0 2006.183.08:26:38.20#ibcon#about to read 3, iclass 12, count 0 2006.183.08:26:38.23#ibcon#read 3, iclass 12, count 0 2006.183.08:26:38.23#ibcon#about to read 4, iclass 12, count 0 2006.183.08:26:38.23#ibcon#read 4, iclass 12, count 0 2006.183.08:26:38.23#ibcon#about to read 5, iclass 12, count 0 2006.183.08:26:38.23#ibcon#read 5, iclass 12, count 0 2006.183.08:26:38.23#ibcon#about to read 6, iclass 12, count 0 2006.183.08:26:38.23#ibcon#read 6, iclass 12, count 0 2006.183.08:26:38.23#ibcon#end of sib2, iclass 12, count 0 2006.183.08:26:38.23#ibcon#*after write, iclass 12, count 0 2006.183.08:26:38.23#ibcon#*before return 0, iclass 12, count 0 2006.183.08:26:38.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:38.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:38.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:26:38.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:26:38.23$vc4f8/valo=2,572.99 2006.183.08:26:38.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:26:38.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:26:38.23#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:38.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:38.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:38.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:38.23#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:26:38.23#ibcon#first serial, iclass 14, count 0 2006.183.08:26:38.23#ibcon#enter sib2, iclass 14, count 0 2006.183.08:26:38.23#ibcon#flushed, iclass 14, count 0 2006.183.08:26:38.23#ibcon#about to write, iclass 14, count 0 2006.183.08:26:38.23#ibcon#wrote, iclass 14, count 0 2006.183.08:26:38.23#ibcon#about to read 3, iclass 14, count 0 2006.183.08:26:38.25#ibcon#read 3, iclass 14, count 0 2006.183.08:26:38.25#ibcon#about to read 4, iclass 14, count 0 2006.183.08:26:38.25#ibcon#read 4, iclass 14, count 0 2006.183.08:26:38.25#ibcon#about to read 5, iclass 14, count 0 2006.183.08:26:38.25#ibcon#read 5, iclass 14, count 0 2006.183.08:26:38.25#ibcon#about to read 6, iclass 14, count 0 2006.183.08:26:38.25#ibcon#read 6, iclass 14, count 0 2006.183.08:26:38.25#ibcon#end of sib2, iclass 14, count 0 2006.183.08:26:38.25#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:26:38.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:26:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:26:38.25#ibcon#*before write, iclass 14, count 0 2006.183.08:26:38.25#ibcon#enter sib2, iclass 14, count 0 2006.183.08:26:38.25#ibcon#flushed, iclass 14, count 0 2006.183.08:26:38.25#ibcon#about to write, iclass 14, count 0 2006.183.08:26:38.25#ibcon#wrote, iclass 14, count 0 2006.183.08:26:38.25#ibcon#about to read 3, iclass 14, count 0 2006.183.08:26:38.29#ibcon#read 3, iclass 14, count 0 2006.183.08:26:38.29#ibcon#about to read 4, iclass 14, count 0 2006.183.08:26:38.29#ibcon#read 4, iclass 14, count 0 2006.183.08:26:38.29#ibcon#about to read 5, iclass 14, count 0 2006.183.08:26:38.29#ibcon#read 5, iclass 14, count 0 2006.183.08:26:38.29#ibcon#about to read 6, iclass 14, count 0 2006.183.08:26:38.29#ibcon#read 6, iclass 14, count 0 2006.183.08:26:38.29#ibcon#end of sib2, iclass 14, count 0 2006.183.08:26:38.29#ibcon#*after write, iclass 14, count 0 2006.183.08:26:38.29#ibcon#*before return 0, iclass 14, count 0 2006.183.08:26:38.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:38.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:38.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:26:38.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:26:38.29$vc4f8/va=2,7 2006.183.08:26:38.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.08:26:38.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.08:26:38.29#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:38.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:38.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:38.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:38.35#ibcon#enter wrdev, iclass 16, count 2 2006.183.08:26:38.35#ibcon#first serial, iclass 16, count 2 2006.183.08:26:38.35#ibcon#enter sib2, iclass 16, count 2 2006.183.08:26:38.35#ibcon#flushed, iclass 16, count 2 2006.183.08:26:38.35#ibcon#about to write, iclass 16, count 2 2006.183.08:26:38.35#ibcon#wrote, iclass 16, count 2 2006.183.08:26:38.35#ibcon#about to read 3, iclass 16, count 2 2006.183.08:26:38.37#ibcon#read 3, iclass 16, count 2 2006.183.08:26:38.37#ibcon#about to read 4, iclass 16, count 2 2006.183.08:26:38.37#ibcon#read 4, iclass 16, count 2 2006.183.08:26:38.37#ibcon#about to read 5, iclass 16, count 2 2006.183.08:26:38.37#ibcon#read 5, iclass 16, count 2 2006.183.08:26:38.37#ibcon#about to read 6, iclass 16, count 2 2006.183.08:26:38.37#ibcon#read 6, iclass 16, count 2 2006.183.08:26:38.37#ibcon#end of sib2, iclass 16, count 2 2006.183.08:26:38.37#ibcon#*mode == 0, iclass 16, count 2 2006.183.08:26:38.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.08:26:38.37#ibcon#[25=AT02-07\r\n] 2006.183.08:26:38.37#ibcon#*before write, iclass 16, count 2 2006.183.08:26:38.37#ibcon#enter sib2, iclass 16, count 2 2006.183.08:26:38.37#ibcon#flushed, iclass 16, count 2 2006.183.08:26:38.37#ibcon#about to write, iclass 16, count 2 2006.183.08:26:38.37#ibcon#wrote, iclass 16, count 2 2006.183.08:26:38.37#ibcon#about to read 3, iclass 16, count 2 2006.183.08:26:38.40#ibcon#read 3, iclass 16, count 2 2006.183.08:26:38.40#ibcon#about to read 4, iclass 16, count 2 2006.183.08:26:38.40#ibcon#read 4, iclass 16, count 2 2006.183.08:26:38.40#ibcon#about to read 5, iclass 16, count 2 2006.183.08:26:38.40#ibcon#read 5, iclass 16, count 2 2006.183.08:26:38.40#ibcon#about to read 6, iclass 16, count 2 2006.183.08:26:38.40#ibcon#read 6, iclass 16, count 2 2006.183.08:26:38.40#ibcon#end of sib2, iclass 16, count 2 2006.183.08:26:38.40#ibcon#*after write, iclass 16, count 2 2006.183.08:26:38.40#ibcon#*before return 0, iclass 16, count 2 2006.183.08:26:38.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:38.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:38.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.08:26:38.40#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:38.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:38.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:38.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:38.53#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:26:38.53#ibcon#first serial, iclass 16, count 0 2006.183.08:26:38.53#ibcon#enter sib2, iclass 16, count 0 2006.183.08:26:38.53#ibcon#flushed, iclass 16, count 0 2006.183.08:26:38.53#ibcon#about to write, iclass 16, count 0 2006.183.08:26:38.53#ibcon#wrote, iclass 16, count 0 2006.183.08:26:38.53#ibcon#about to read 3, iclass 16, count 0 2006.183.08:26:38.54#ibcon#read 3, iclass 16, count 0 2006.183.08:26:38.54#ibcon#about to read 4, iclass 16, count 0 2006.183.08:26:38.54#ibcon#read 4, iclass 16, count 0 2006.183.08:26:38.54#ibcon#about to read 5, iclass 16, count 0 2006.183.08:26:38.54#ibcon#read 5, iclass 16, count 0 2006.183.08:26:38.54#ibcon#about to read 6, iclass 16, count 0 2006.183.08:26:38.54#ibcon#read 6, iclass 16, count 0 2006.183.08:26:38.54#ibcon#end of sib2, iclass 16, count 0 2006.183.08:26:38.54#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:26:38.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:26:38.54#ibcon#[25=USB\r\n] 2006.183.08:26:38.54#ibcon#*before write, iclass 16, count 0 2006.183.08:26:38.54#ibcon#enter sib2, iclass 16, count 0 2006.183.08:26:38.54#ibcon#flushed, iclass 16, count 0 2006.183.08:26:38.54#ibcon#about to write, iclass 16, count 0 2006.183.08:26:38.54#ibcon#wrote, iclass 16, count 0 2006.183.08:26:38.54#ibcon#about to read 3, iclass 16, count 0 2006.183.08:26:38.57#ibcon#read 3, iclass 16, count 0 2006.183.08:26:38.57#ibcon#about to read 4, iclass 16, count 0 2006.183.08:26:38.57#ibcon#read 4, iclass 16, count 0 2006.183.08:26:38.57#ibcon#about to read 5, iclass 16, count 0 2006.183.08:26:38.57#ibcon#read 5, iclass 16, count 0 2006.183.08:26:38.57#ibcon#about to read 6, iclass 16, count 0 2006.183.08:26:38.57#ibcon#read 6, iclass 16, count 0 2006.183.08:26:38.57#ibcon#end of sib2, iclass 16, count 0 2006.183.08:26:38.57#ibcon#*after write, iclass 16, count 0 2006.183.08:26:38.57#ibcon#*before return 0, iclass 16, count 0 2006.183.08:26:38.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:38.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:38.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:26:38.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:26:38.57$vc4f8/valo=3,672.99 2006.183.08:26:38.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:26:38.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:26:38.57#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:38.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:38.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:38.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:38.57#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:26:38.57#ibcon#first serial, iclass 18, count 0 2006.183.08:26:38.57#ibcon#enter sib2, iclass 18, count 0 2006.183.08:26:38.57#ibcon#flushed, iclass 18, count 0 2006.183.08:26:38.57#ibcon#about to write, iclass 18, count 0 2006.183.08:26:38.57#ibcon#wrote, iclass 18, count 0 2006.183.08:26:38.57#ibcon#about to read 3, iclass 18, count 0 2006.183.08:26:38.60#ibcon#read 3, iclass 18, count 0 2006.183.08:26:38.60#ibcon#about to read 4, iclass 18, count 0 2006.183.08:26:38.60#ibcon#read 4, iclass 18, count 0 2006.183.08:26:38.60#ibcon#about to read 5, iclass 18, count 0 2006.183.08:26:38.60#ibcon#read 5, iclass 18, count 0 2006.183.08:26:38.60#ibcon#about to read 6, iclass 18, count 0 2006.183.08:26:38.60#ibcon#read 6, iclass 18, count 0 2006.183.08:26:38.60#ibcon#end of sib2, iclass 18, count 0 2006.183.08:26:38.60#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:26:38.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:26:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:26:38.60#ibcon#*before write, iclass 18, count 0 2006.183.08:26:38.60#ibcon#enter sib2, iclass 18, count 0 2006.183.08:26:38.60#ibcon#flushed, iclass 18, count 0 2006.183.08:26:38.60#ibcon#about to write, iclass 18, count 0 2006.183.08:26:38.60#ibcon#wrote, iclass 18, count 0 2006.183.08:26:38.60#ibcon#about to read 3, iclass 18, count 0 2006.183.08:26:38.64#ibcon#read 3, iclass 18, count 0 2006.183.08:26:38.64#ibcon#about to read 4, iclass 18, count 0 2006.183.08:26:38.64#ibcon#read 4, iclass 18, count 0 2006.183.08:26:38.64#ibcon#about to read 5, iclass 18, count 0 2006.183.08:26:38.64#ibcon#read 5, iclass 18, count 0 2006.183.08:26:38.64#ibcon#about to read 6, iclass 18, count 0 2006.183.08:26:38.64#ibcon#read 6, iclass 18, count 0 2006.183.08:26:38.64#ibcon#end of sib2, iclass 18, count 0 2006.183.08:26:38.64#ibcon#*after write, iclass 18, count 0 2006.183.08:26:38.64#ibcon#*before return 0, iclass 18, count 0 2006.183.08:26:38.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:38.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:38.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:26:38.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:26:38.64$vc4f8/va=3,6 2006.183.08:26:38.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.08:26:38.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.08:26:38.64#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:38.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:38.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:38.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:38.69#ibcon#enter wrdev, iclass 20, count 2 2006.183.08:26:38.69#ibcon#first serial, iclass 20, count 2 2006.183.08:26:38.69#ibcon#enter sib2, iclass 20, count 2 2006.183.08:26:38.69#ibcon#flushed, iclass 20, count 2 2006.183.08:26:38.69#ibcon#about to write, iclass 20, count 2 2006.183.08:26:38.69#ibcon#wrote, iclass 20, count 2 2006.183.08:26:38.69#ibcon#about to read 3, iclass 20, count 2 2006.183.08:26:38.71#ibcon#read 3, iclass 20, count 2 2006.183.08:26:38.71#ibcon#about to read 4, iclass 20, count 2 2006.183.08:26:38.71#ibcon#read 4, iclass 20, count 2 2006.183.08:26:38.71#ibcon#about to read 5, iclass 20, count 2 2006.183.08:26:38.71#ibcon#read 5, iclass 20, count 2 2006.183.08:26:38.71#ibcon#about to read 6, iclass 20, count 2 2006.183.08:26:38.71#ibcon#read 6, iclass 20, count 2 2006.183.08:26:38.71#ibcon#end of sib2, iclass 20, count 2 2006.183.08:26:38.71#ibcon#*mode == 0, iclass 20, count 2 2006.183.08:26:38.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.08:26:38.71#ibcon#[25=AT03-06\r\n] 2006.183.08:26:38.71#ibcon#*before write, iclass 20, count 2 2006.183.08:26:38.71#ibcon#enter sib2, iclass 20, count 2 2006.183.08:26:38.71#ibcon#flushed, iclass 20, count 2 2006.183.08:26:38.71#ibcon#about to write, iclass 20, count 2 2006.183.08:26:38.71#ibcon#wrote, iclass 20, count 2 2006.183.08:26:38.71#ibcon#about to read 3, iclass 20, count 2 2006.183.08:26:38.74#ibcon#read 3, iclass 20, count 2 2006.183.08:26:38.74#ibcon#about to read 4, iclass 20, count 2 2006.183.08:26:38.74#ibcon#read 4, iclass 20, count 2 2006.183.08:26:38.74#ibcon#about to read 5, iclass 20, count 2 2006.183.08:26:38.74#ibcon#read 5, iclass 20, count 2 2006.183.08:26:38.74#ibcon#about to read 6, iclass 20, count 2 2006.183.08:26:38.74#ibcon#read 6, iclass 20, count 2 2006.183.08:26:38.74#ibcon#end of sib2, iclass 20, count 2 2006.183.08:26:38.74#ibcon#*after write, iclass 20, count 2 2006.183.08:26:38.74#ibcon#*before return 0, iclass 20, count 2 2006.183.08:26:38.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:38.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:38.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.08:26:38.74#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:38.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:38.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:38.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:38.86#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:26:38.86#ibcon#first serial, iclass 20, count 0 2006.183.08:26:38.86#ibcon#enter sib2, iclass 20, count 0 2006.183.08:26:38.86#ibcon#flushed, iclass 20, count 0 2006.183.08:26:38.86#ibcon#about to write, iclass 20, count 0 2006.183.08:26:38.86#ibcon#wrote, iclass 20, count 0 2006.183.08:26:38.86#ibcon#about to read 3, iclass 20, count 0 2006.183.08:26:38.88#ibcon#read 3, iclass 20, count 0 2006.183.08:26:38.88#ibcon#about to read 4, iclass 20, count 0 2006.183.08:26:38.88#ibcon#read 4, iclass 20, count 0 2006.183.08:26:38.88#ibcon#about to read 5, iclass 20, count 0 2006.183.08:26:38.88#ibcon#read 5, iclass 20, count 0 2006.183.08:26:38.88#ibcon#about to read 6, iclass 20, count 0 2006.183.08:26:38.88#ibcon#read 6, iclass 20, count 0 2006.183.08:26:38.88#ibcon#end of sib2, iclass 20, count 0 2006.183.08:26:38.88#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:26:38.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:26:38.88#ibcon#[25=USB\r\n] 2006.183.08:26:38.88#ibcon#*before write, iclass 20, count 0 2006.183.08:26:38.88#ibcon#enter sib2, iclass 20, count 0 2006.183.08:26:38.88#ibcon#flushed, iclass 20, count 0 2006.183.08:26:38.88#ibcon#about to write, iclass 20, count 0 2006.183.08:26:38.88#ibcon#wrote, iclass 20, count 0 2006.183.08:26:38.88#ibcon#about to read 3, iclass 20, count 0 2006.183.08:26:38.91#ibcon#read 3, iclass 20, count 0 2006.183.08:26:38.91#ibcon#about to read 4, iclass 20, count 0 2006.183.08:26:38.91#ibcon#read 4, iclass 20, count 0 2006.183.08:26:38.91#ibcon#about to read 5, iclass 20, count 0 2006.183.08:26:38.91#ibcon#read 5, iclass 20, count 0 2006.183.08:26:38.91#ibcon#about to read 6, iclass 20, count 0 2006.183.08:26:38.91#ibcon#read 6, iclass 20, count 0 2006.183.08:26:38.91#ibcon#end of sib2, iclass 20, count 0 2006.183.08:26:38.91#ibcon#*after write, iclass 20, count 0 2006.183.08:26:38.91#ibcon#*before return 0, iclass 20, count 0 2006.183.08:26:38.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:38.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:38.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:26:38.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:26:38.91$vc4f8/valo=4,832.99 2006.183.08:26:38.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.08:26:38.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.08:26:38.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:38.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:38.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:38.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:38.91#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:26:38.91#ibcon#first serial, iclass 22, count 0 2006.183.08:26:38.91#ibcon#enter sib2, iclass 22, count 0 2006.183.08:26:38.91#ibcon#flushed, iclass 22, count 0 2006.183.08:26:38.91#ibcon#about to write, iclass 22, count 0 2006.183.08:26:38.91#ibcon#wrote, iclass 22, count 0 2006.183.08:26:38.91#ibcon#about to read 3, iclass 22, count 0 2006.183.08:26:38.93#ibcon#read 3, iclass 22, count 0 2006.183.08:26:38.93#ibcon#about to read 4, iclass 22, count 0 2006.183.08:26:38.93#ibcon#read 4, iclass 22, count 0 2006.183.08:26:38.93#ibcon#about to read 5, iclass 22, count 0 2006.183.08:26:38.93#ibcon#read 5, iclass 22, count 0 2006.183.08:26:38.93#ibcon#about to read 6, iclass 22, count 0 2006.183.08:26:38.93#ibcon#read 6, iclass 22, count 0 2006.183.08:26:38.93#ibcon#end of sib2, iclass 22, count 0 2006.183.08:26:38.93#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:26:38.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:26:38.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:26:38.93#ibcon#*before write, iclass 22, count 0 2006.183.08:26:38.93#ibcon#enter sib2, iclass 22, count 0 2006.183.08:26:38.93#ibcon#flushed, iclass 22, count 0 2006.183.08:26:38.93#ibcon#about to write, iclass 22, count 0 2006.183.08:26:38.93#ibcon#wrote, iclass 22, count 0 2006.183.08:26:38.93#ibcon#about to read 3, iclass 22, count 0 2006.183.08:26:38.97#ibcon#read 3, iclass 22, count 0 2006.183.08:26:38.97#ibcon#about to read 4, iclass 22, count 0 2006.183.08:26:38.97#ibcon#read 4, iclass 22, count 0 2006.183.08:26:38.97#ibcon#about to read 5, iclass 22, count 0 2006.183.08:26:38.97#ibcon#read 5, iclass 22, count 0 2006.183.08:26:38.97#ibcon#about to read 6, iclass 22, count 0 2006.183.08:26:38.97#ibcon#read 6, iclass 22, count 0 2006.183.08:26:38.97#ibcon#end of sib2, iclass 22, count 0 2006.183.08:26:38.97#ibcon#*after write, iclass 22, count 0 2006.183.08:26:38.97#ibcon#*before return 0, iclass 22, count 0 2006.183.08:26:38.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:38.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:38.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:26:38.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:26:38.97$vc4f8/va=4,7 2006.183.08:26:38.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.08:26:38.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.08:26:38.97#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:38.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:39.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:39.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:39.03#ibcon#enter wrdev, iclass 24, count 2 2006.183.08:26:39.03#ibcon#first serial, iclass 24, count 2 2006.183.08:26:39.03#ibcon#enter sib2, iclass 24, count 2 2006.183.08:26:39.03#ibcon#flushed, iclass 24, count 2 2006.183.08:26:39.03#ibcon#about to write, iclass 24, count 2 2006.183.08:26:39.03#ibcon#wrote, iclass 24, count 2 2006.183.08:26:39.03#ibcon#about to read 3, iclass 24, count 2 2006.183.08:26:39.05#ibcon#read 3, iclass 24, count 2 2006.183.08:26:39.05#ibcon#about to read 4, iclass 24, count 2 2006.183.08:26:39.05#ibcon#read 4, iclass 24, count 2 2006.183.08:26:39.05#ibcon#about to read 5, iclass 24, count 2 2006.183.08:26:39.05#ibcon#read 5, iclass 24, count 2 2006.183.08:26:39.05#ibcon#about to read 6, iclass 24, count 2 2006.183.08:26:39.05#ibcon#read 6, iclass 24, count 2 2006.183.08:26:39.05#ibcon#end of sib2, iclass 24, count 2 2006.183.08:26:39.05#ibcon#*mode == 0, iclass 24, count 2 2006.183.08:26:39.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.08:26:39.05#ibcon#[25=AT04-07\r\n] 2006.183.08:26:39.05#ibcon#*before write, iclass 24, count 2 2006.183.08:26:39.05#ibcon#enter sib2, iclass 24, count 2 2006.183.08:26:39.05#ibcon#flushed, iclass 24, count 2 2006.183.08:26:39.05#ibcon#about to write, iclass 24, count 2 2006.183.08:26:39.05#ibcon#wrote, iclass 24, count 2 2006.183.08:26:39.05#ibcon#about to read 3, iclass 24, count 2 2006.183.08:26:39.08#ibcon#read 3, iclass 24, count 2 2006.183.08:26:39.08#ibcon#about to read 4, iclass 24, count 2 2006.183.08:26:39.08#ibcon#read 4, iclass 24, count 2 2006.183.08:26:39.08#ibcon#about to read 5, iclass 24, count 2 2006.183.08:26:39.08#ibcon#read 5, iclass 24, count 2 2006.183.08:26:39.08#ibcon#about to read 6, iclass 24, count 2 2006.183.08:26:39.08#ibcon#read 6, iclass 24, count 2 2006.183.08:26:39.08#ibcon#end of sib2, iclass 24, count 2 2006.183.08:26:39.08#ibcon#*after write, iclass 24, count 2 2006.183.08:26:39.08#ibcon#*before return 0, iclass 24, count 2 2006.183.08:26:39.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:39.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:39.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.08:26:39.08#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:39.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:39.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:39.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:39.20#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:26:39.20#ibcon#first serial, iclass 24, count 0 2006.183.08:26:39.20#ibcon#enter sib2, iclass 24, count 0 2006.183.08:26:39.20#ibcon#flushed, iclass 24, count 0 2006.183.08:26:39.20#ibcon#about to write, iclass 24, count 0 2006.183.08:26:39.20#ibcon#wrote, iclass 24, count 0 2006.183.08:26:39.20#ibcon#about to read 3, iclass 24, count 0 2006.183.08:26:39.22#ibcon#read 3, iclass 24, count 0 2006.183.08:26:39.22#ibcon#about to read 4, iclass 24, count 0 2006.183.08:26:39.22#ibcon#read 4, iclass 24, count 0 2006.183.08:26:39.22#ibcon#about to read 5, iclass 24, count 0 2006.183.08:26:39.22#ibcon#read 5, iclass 24, count 0 2006.183.08:26:39.22#ibcon#about to read 6, iclass 24, count 0 2006.183.08:26:39.22#ibcon#read 6, iclass 24, count 0 2006.183.08:26:39.22#ibcon#end of sib2, iclass 24, count 0 2006.183.08:26:39.22#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:26:39.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:26:39.22#ibcon#[25=USB\r\n] 2006.183.08:26:39.22#ibcon#*before write, iclass 24, count 0 2006.183.08:26:39.22#ibcon#enter sib2, iclass 24, count 0 2006.183.08:26:39.22#ibcon#flushed, iclass 24, count 0 2006.183.08:26:39.22#ibcon#about to write, iclass 24, count 0 2006.183.08:26:39.22#ibcon#wrote, iclass 24, count 0 2006.183.08:26:39.22#ibcon#about to read 3, iclass 24, count 0 2006.183.08:26:39.25#ibcon#read 3, iclass 24, count 0 2006.183.08:26:39.25#ibcon#about to read 4, iclass 24, count 0 2006.183.08:26:39.25#ibcon#read 4, iclass 24, count 0 2006.183.08:26:39.25#ibcon#about to read 5, iclass 24, count 0 2006.183.08:26:39.25#ibcon#read 5, iclass 24, count 0 2006.183.08:26:39.25#ibcon#about to read 6, iclass 24, count 0 2006.183.08:26:39.25#ibcon#read 6, iclass 24, count 0 2006.183.08:26:39.25#ibcon#end of sib2, iclass 24, count 0 2006.183.08:26:39.25#ibcon#*after write, iclass 24, count 0 2006.183.08:26:39.25#ibcon#*before return 0, iclass 24, count 0 2006.183.08:26:39.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:39.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:39.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:26:39.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:26:39.25$vc4f8/valo=5,652.99 2006.183.08:26:39.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.08:26:39.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.08:26:39.25#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:39.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:39.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:39.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:39.25#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:26:39.25#ibcon#first serial, iclass 26, count 0 2006.183.08:26:39.25#ibcon#enter sib2, iclass 26, count 0 2006.183.08:26:39.25#ibcon#flushed, iclass 26, count 0 2006.183.08:26:39.25#ibcon#about to write, iclass 26, count 0 2006.183.08:26:39.25#ibcon#wrote, iclass 26, count 0 2006.183.08:26:39.25#ibcon#about to read 3, iclass 26, count 0 2006.183.08:26:39.27#ibcon#read 3, iclass 26, count 0 2006.183.08:26:39.27#ibcon#about to read 4, iclass 26, count 0 2006.183.08:26:39.27#ibcon#read 4, iclass 26, count 0 2006.183.08:26:39.27#ibcon#about to read 5, iclass 26, count 0 2006.183.08:26:39.27#ibcon#read 5, iclass 26, count 0 2006.183.08:26:39.27#ibcon#about to read 6, iclass 26, count 0 2006.183.08:26:39.27#ibcon#read 6, iclass 26, count 0 2006.183.08:26:39.27#ibcon#end of sib2, iclass 26, count 0 2006.183.08:26:39.27#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:26:39.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:26:39.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:26:39.27#ibcon#*before write, iclass 26, count 0 2006.183.08:26:39.27#ibcon#enter sib2, iclass 26, count 0 2006.183.08:26:39.27#ibcon#flushed, iclass 26, count 0 2006.183.08:26:39.27#ibcon#about to write, iclass 26, count 0 2006.183.08:26:39.27#ibcon#wrote, iclass 26, count 0 2006.183.08:26:39.27#ibcon#about to read 3, iclass 26, count 0 2006.183.08:26:39.31#ibcon#read 3, iclass 26, count 0 2006.183.08:26:39.31#ibcon#about to read 4, iclass 26, count 0 2006.183.08:26:39.31#ibcon#read 4, iclass 26, count 0 2006.183.08:26:39.31#ibcon#about to read 5, iclass 26, count 0 2006.183.08:26:39.31#ibcon#read 5, iclass 26, count 0 2006.183.08:26:39.31#ibcon#about to read 6, iclass 26, count 0 2006.183.08:26:39.31#ibcon#read 6, iclass 26, count 0 2006.183.08:26:39.31#ibcon#end of sib2, iclass 26, count 0 2006.183.08:26:39.31#ibcon#*after write, iclass 26, count 0 2006.183.08:26:39.31#ibcon#*before return 0, iclass 26, count 0 2006.183.08:26:39.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:39.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:39.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:26:39.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:26:39.31$vc4f8/va=5,7 2006.183.08:26:39.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.08:26:39.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.08:26:39.31#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:39.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:39.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:39.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:39.37#ibcon#enter wrdev, iclass 28, count 2 2006.183.08:26:39.37#ibcon#first serial, iclass 28, count 2 2006.183.08:26:39.37#ibcon#enter sib2, iclass 28, count 2 2006.183.08:26:39.37#ibcon#flushed, iclass 28, count 2 2006.183.08:26:39.37#ibcon#about to write, iclass 28, count 2 2006.183.08:26:39.37#ibcon#wrote, iclass 28, count 2 2006.183.08:26:39.37#ibcon#about to read 3, iclass 28, count 2 2006.183.08:26:39.39#ibcon#read 3, iclass 28, count 2 2006.183.08:26:39.39#ibcon#about to read 4, iclass 28, count 2 2006.183.08:26:39.39#ibcon#read 4, iclass 28, count 2 2006.183.08:26:39.39#ibcon#about to read 5, iclass 28, count 2 2006.183.08:26:39.39#ibcon#read 5, iclass 28, count 2 2006.183.08:26:39.39#ibcon#about to read 6, iclass 28, count 2 2006.183.08:26:39.39#ibcon#read 6, iclass 28, count 2 2006.183.08:26:39.39#ibcon#end of sib2, iclass 28, count 2 2006.183.08:26:39.39#ibcon#*mode == 0, iclass 28, count 2 2006.183.08:26:39.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.08:26:39.39#ibcon#[25=AT05-07\r\n] 2006.183.08:26:39.39#ibcon#*before write, iclass 28, count 2 2006.183.08:26:39.39#ibcon#enter sib2, iclass 28, count 2 2006.183.08:26:39.39#ibcon#flushed, iclass 28, count 2 2006.183.08:26:39.39#ibcon#about to write, iclass 28, count 2 2006.183.08:26:39.39#ibcon#wrote, iclass 28, count 2 2006.183.08:26:39.39#ibcon#about to read 3, iclass 28, count 2 2006.183.08:26:39.42#ibcon#read 3, iclass 28, count 2 2006.183.08:26:39.42#ibcon#about to read 4, iclass 28, count 2 2006.183.08:26:39.42#ibcon#read 4, iclass 28, count 2 2006.183.08:26:39.42#ibcon#about to read 5, iclass 28, count 2 2006.183.08:26:39.42#ibcon#read 5, iclass 28, count 2 2006.183.08:26:39.42#ibcon#about to read 6, iclass 28, count 2 2006.183.08:26:39.42#ibcon#read 6, iclass 28, count 2 2006.183.08:26:39.42#ibcon#end of sib2, iclass 28, count 2 2006.183.08:26:39.42#ibcon#*after write, iclass 28, count 2 2006.183.08:26:39.42#ibcon#*before return 0, iclass 28, count 2 2006.183.08:26:39.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:39.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:39.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.08:26:39.42#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:39.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:39.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:39.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:39.54#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:26:39.54#ibcon#first serial, iclass 28, count 0 2006.183.08:26:39.54#ibcon#enter sib2, iclass 28, count 0 2006.183.08:26:39.54#ibcon#flushed, iclass 28, count 0 2006.183.08:26:39.54#ibcon#about to write, iclass 28, count 0 2006.183.08:26:39.54#ibcon#wrote, iclass 28, count 0 2006.183.08:26:39.54#ibcon#about to read 3, iclass 28, count 0 2006.183.08:26:39.56#ibcon#read 3, iclass 28, count 0 2006.183.08:26:39.56#ibcon#about to read 4, iclass 28, count 0 2006.183.08:26:39.56#ibcon#read 4, iclass 28, count 0 2006.183.08:26:39.56#ibcon#about to read 5, iclass 28, count 0 2006.183.08:26:39.56#ibcon#read 5, iclass 28, count 0 2006.183.08:26:39.56#ibcon#about to read 6, iclass 28, count 0 2006.183.08:26:39.56#ibcon#read 6, iclass 28, count 0 2006.183.08:26:39.56#ibcon#end of sib2, iclass 28, count 0 2006.183.08:26:39.56#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:26:39.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:26:39.56#ibcon#[25=USB\r\n] 2006.183.08:26:39.56#ibcon#*before write, iclass 28, count 0 2006.183.08:26:39.56#ibcon#enter sib2, iclass 28, count 0 2006.183.08:26:39.56#ibcon#flushed, iclass 28, count 0 2006.183.08:26:39.56#ibcon#about to write, iclass 28, count 0 2006.183.08:26:39.56#ibcon#wrote, iclass 28, count 0 2006.183.08:26:39.56#ibcon#about to read 3, iclass 28, count 0 2006.183.08:26:39.59#ibcon#read 3, iclass 28, count 0 2006.183.08:26:39.59#ibcon#about to read 4, iclass 28, count 0 2006.183.08:26:39.59#ibcon#read 4, iclass 28, count 0 2006.183.08:26:39.59#ibcon#about to read 5, iclass 28, count 0 2006.183.08:26:39.59#ibcon#read 5, iclass 28, count 0 2006.183.08:26:39.59#ibcon#about to read 6, iclass 28, count 0 2006.183.08:26:39.59#ibcon#read 6, iclass 28, count 0 2006.183.08:26:39.59#ibcon#end of sib2, iclass 28, count 0 2006.183.08:26:39.59#ibcon#*after write, iclass 28, count 0 2006.183.08:26:39.59#ibcon#*before return 0, iclass 28, count 0 2006.183.08:26:39.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:39.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:39.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:26:39.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:26:39.59$vc4f8/valo=6,772.99 2006.183.08:26:39.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:26:39.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:26:39.59#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:39.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:39.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:39.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:39.59#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:26:39.59#ibcon#first serial, iclass 30, count 0 2006.183.08:26:39.59#ibcon#enter sib2, iclass 30, count 0 2006.183.08:26:39.59#ibcon#flushed, iclass 30, count 0 2006.183.08:26:39.59#ibcon#about to write, iclass 30, count 0 2006.183.08:26:39.59#ibcon#wrote, iclass 30, count 0 2006.183.08:26:39.59#ibcon#about to read 3, iclass 30, count 0 2006.183.08:26:39.62#ibcon#read 3, iclass 30, count 0 2006.183.08:26:39.62#ibcon#about to read 4, iclass 30, count 0 2006.183.08:26:39.62#ibcon#read 4, iclass 30, count 0 2006.183.08:26:39.62#ibcon#about to read 5, iclass 30, count 0 2006.183.08:26:39.62#ibcon#read 5, iclass 30, count 0 2006.183.08:26:39.62#ibcon#about to read 6, iclass 30, count 0 2006.183.08:26:39.62#ibcon#read 6, iclass 30, count 0 2006.183.08:26:39.62#ibcon#end of sib2, iclass 30, count 0 2006.183.08:26:39.62#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:26:39.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:26:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:26:39.62#ibcon#*before write, iclass 30, count 0 2006.183.08:26:39.62#ibcon#enter sib2, iclass 30, count 0 2006.183.08:26:39.62#ibcon#flushed, iclass 30, count 0 2006.183.08:26:39.62#ibcon#about to write, iclass 30, count 0 2006.183.08:26:39.62#ibcon#wrote, iclass 30, count 0 2006.183.08:26:39.62#ibcon#about to read 3, iclass 30, count 0 2006.183.08:26:39.66#ibcon#read 3, iclass 30, count 0 2006.183.08:26:39.66#ibcon#about to read 4, iclass 30, count 0 2006.183.08:26:39.66#ibcon#read 4, iclass 30, count 0 2006.183.08:26:39.66#ibcon#about to read 5, iclass 30, count 0 2006.183.08:26:39.66#ibcon#read 5, iclass 30, count 0 2006.183.08:26:39.66#ibcon#about to read 6, iclass 30, count 0 2006.183.08:26:39.66#ibcon#read 6, iclass 30, count 0 2006.183.08:26:39.66#ibcon#end of sib2, iclass 30, count 0 2006.183.08:26:39.66#ibcon#*after write, iclass 30, count 0 2006.183.08:26:39.66#ibcon#*before return 0, iclass 30, count 0 2006.183.08:26:39.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:39.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:39.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:26:39.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:26:39.66$vc4f8/va=6,6 2006.183.08:26:39.66#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.183.08:26:39.66#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.183.08:26:39.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:39.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:26:39.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:26:39.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:26:39.71#ibcon#enter wrdev, iclass 32, count 2 2006.183.08:26:39.71#ibcon#first serial, iclass 32, count 2 2006.183.08:26:39.71#ibcon#enter sib2, iclass 32, count 2 2006.183.08:26:39.71#ibcon#flushed, iclass 32, count 2 2006.183.08:26:39.71#ibcon#about to write, iclass 32, count 2 2006.183.08:26:39.71#ibcon#wrote, iclass 32, count 2 2006.183.08:26:39.71#ibcon#about to read 3, iclass 32, count 2 2006.183.08:26:39.73#ibcon#read 3, iclass 32, count 2 2006.183.08:26:39.73#ibcon#about to read 4, iclass 32, count 2 2006.183.08:26:39.73#ibcon#read 4, iclass 32, count 2 2006.183.08:26:39.73#ibcon#about to read 5, iclass 32, count 2 2006.183.08:26:39.73#ibcon#read 5, iclass 32, count 2 2006.183.08:26:39.73#ibcon#about to read 6, iclass 32, count 2 2006.183.08:26:39.73#ibcon#read 6, iclass 32, count 2 2006.183.08:26:39.73#ibcon#end of sib2, iclass 32, count 2 2006.183.08:26:39.73#ibcon#*mode == 0, iclass 32, count 2 2006.183.08:26:39.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.183.08:26:39.73#ibcon#[25=AT06-06\r\n] 2006.183.08:26:39.73#ibcon#*before write, iclass 32, count 2 2006.183.08:26:39.73#ibcon#enter sib2, iclass 32, count 2 2006.183.08:26:39.73#ibcon#flushed, iclass 32, count 2 2006.183.08:26:39.73#ibcon#about to write, iclass 32, count 2 2006.183.08:26:39.73#ibcon#wrote, iclass 32, count 2 2006.183.08:26:39.73#ibcon#about to read 3, iclass 32, count 2 2006.183.08:26:39.76#ibcon#read 3, iclass 32, count 2 2006.183.08:26:39.76#ibcon#about to read 4, iclass 32, count 2 2006.183.08:26:39.76#ibcon#read 4, iclass 32, count 2 2006.183.08:26:39.76#ibcon#about to read 5, iclass 32, count 2 2006.183.08:26:39.76#ibcon#read 5, iclass 32, count 2 2006.183.08:26:39.76#ibcon#about to read 6, iclass 32, count 2 2006.183.08:26:39.76#ibcon#read 6, iclass 32, count 2 2006.183.08:26:39.76#ibcon#end of sib2, iclass 32, count 2 2006.183.08:26:39.76#ibcon#*after write, iclass 32, count 2 2006.183.08:26:39.76#ibcon#*before return 0, iclass 32, count 2 2006.183.08:26:39.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:26:39.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.183.08:26:39.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.183.08:26:39.76#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:39.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:26:39.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:26:39.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:26:39.88#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:26:39.88#ibcon#first serial, iclass 32, count 0 2006.183.08:26:39.88#ibcon#enter sib2, iclass 32, count 0 2006.183.08:26:39.88#ibcon#flushed, iclass 32, count 0 2006.183.08:26:39.88#ibcon#about to write, iclass 32, count 0 2006.183.08:26:39.88#ibcon#wrote, iclass 32, count 0 2006.183.08:26:39.88#ibcon#about to read 3, iclass 32, count 0 2006.183.08:26:39.90#ibcon#read 3, iclass 32, count 0 2006.183.08:26:39.90#ibcon#about to read 4, iclass 32, count 0 2006.183.08:26:39.90#ibcon#read 4, iclass 32, count 0 2006.183.08:26:39.90#ibcon#about to read 5, iclass 32, count 0 2006.183.08:26:39.90#ibcon#read 5, iclass 32, count 0 2006.183.08:26:39.90#ibcon#about to read 6, iclass 32, count 0 2006.183.08:26:39.90#ibcon#read 6, iclass 32, count 0 2006.183.08:26:39.90#ibcon#end of sib2, iclass 32, count 0 2006.183.08:26:39.90#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:26:39.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:26:39.90#ibcon#[25=USB\r\n] 2006.183.08:26:39.90#ibcon#*before write, iclass 32, count 0 2006.183.08:26:39.90#ibcon#enter sib2, iclass 32, count 0 2006.183.08:26:39.90#ibcon#flushed, iclass 32, count 0 2006.183.08:26:39.90#ibcon#about to write, iclass 32, count 0 2006.183.08:26:39.90#ibcon#wrote, iclass 32, count 0 2006.183.08:26:39.90#ibcon#about to read 3, iclass 32, count 0 2006.183.08:26:39.93#ibcon#read 3, iclass 32, count 0 2006.183.08:26:39.93#ibcon#about to read 4, iclass 32, count 0 2006.183.08:26:39.93#ibcon#read 4, iclass 32, count 0 2006.183.08:26:39.93#ibcon#about to read 5, iclass 32, count 0 2006.183.08:26:39.93#ibcon#read 5, iclass 32, count 0 2006.183.08:26:39.93#ibcon#about to read 6, iclass 32, count 0 2006.183.08:26:39.93#ibcon#read 6, iclass 32, count 0 2006.183.08:26:39.93#ibcon#end of sib2, iclass 32, count 0 2006.183.08:26:39.93#ibcon#*after write, iclass 32, count 0 2006.183.08:26:39.93#ibcon#*before return 0, iclass 32, count 0 2006.183.08:26:39.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:26:39.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.183.08:26:39.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:26:39.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:26:39.93$vc4f8/valo=7,832.99 2006.183.08:26:39.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.183.08:26:39.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.183.08:26:39.93#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:39.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:26:39.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:26:39.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:26:39.93#ibcon#enter wrdev, iclass 34, count 0 2006.183.08:26:39.93#ibcon#first serial, iclass 34, count 0 2006.183.08:26:39.93#ibcon#enter sib2, iclass 34, count 0 2006.183.08:26:39.93#ibcon#flushed, iclass 34, count 0 2006.183.08:26:39.93#ibcon#about to write, iclass 34, count 0 2006.183.08:26:39.93#ibcon#wrote, iclass 34, count 0 2006.183.08:26:39.93#ibcon#about to read 3, iclass 34, count 0 2006.183.08:26:39.95#ibcon#read 3, iclass 34, count 0 2006.183.08:26:39.95#ibcon#about to read 4, iclass 34, count 0 2006.183.08:26:39.95#ibcon#read 4, iclass 34, count 0 2006.183.08:26:39.95#ibcon#about to read 5, iclass 34, count 0 2006.183.08:26:39.95#ibcon#read 5, iclass 34, count 0 2006.183.08:26:39.95#ibcon#about to read 6, iclass 34, count 0 2006.183.08:26:39.95#ibcon#read 6, iclass 34, count 0 2006.183.08:26:39.95#ibcon#end of sib2, iclass 34, count 0 2006.183.08:26:39.95#ibcon#*mode == 0, iclass 34, count 0 2006.183.08:26:39.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.183.08:26:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:26:39.95#ibcon#*before write, iclass 34, count 0 2006.183.08:26:39.95#ibcon#enter sib2, iclass 34, count 0 2006.183.08:26:39.95#ibcon#flushed, iclass 34, count 0 2006.183.08:26:39.95#ibcon#about to write, iclass 34, count 0 2006.183.08:26:39.95#ibcon#wrote, iclass 34, count 0 2006.183.08:26:39.95#ibcon#about to read 3, iclass 34, count 0 2006.183.08:26:39.99#ibcon#read 3, iclass 34, count 0 2006.183.08:26:39.99#ibcon#about to read 4, iclass 34, count 0 2006.183.08:26:39.99#ibcon#read 4, iclass 34, count 0 2006.183.08:26:39.99#ibcon#about to read 5, iclass 34, count 0 2006.183.08:26:39.99#ibcon#read 5, iclass 34, count 0 2006.183.08:26:39.99#ibcon#about to read 6, iclass 34, count 0 2006.183.08:26:39.99#ibcon#read 6, iclass 34, count 0 2006.183.08:26:39.99#ibcon#end of sib2, iclass 34, count 0 2006.183.08:26:39.99#ibcon#*after write, iclass 34, count 0 2006.183.08:26:39.99#ibcon#*before return 0, iclass 34, count 0 2006.183.08:26:39.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:26:39.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.183.08:26:39.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.183.08:26:39.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.183.08:26:39.99$vc4f8/va=7,6 2006.183.08:26:39.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.183.08:26:39.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.183.08:26:39.99#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:39.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:26:40.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:26:40.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:26:40.05#ibcon#enter wrdev, iclass 36, count 2 2006.183.08:26:40.05#ibcon#first serial, iclass 36, count 2 2006.183.08:26:40.05#ibcon#enter sib2, iclass 36, count 2 2006.183.08:26:40.05#ibcon#flushed, iclass 36, count 2 2006.183.08:26:40.05#ibcon#about to write, iclass 36, count 2 2006.183.08:26:40.05#ibcon#wrote, iclass 36, count 2 2006.183.08:26:40.05#ibcon#about to read 3, iclass 36, count 2 2006.183.08:26:40.07#ibcon#read 3, iclass 36, count 2 2006.183.08:26:40.07#ibcon#about to read 4, iclass 36, count 2 2006.183.08:26:40.07#ibcon#read 4, iclass 36, count 2 2006.183.08:26:40.07#ibcon#about to read 5, iclass 36, count 2 2006.183.08:26:40.07#ibcon#read 5, iclass 36, count 2 2006.183.08:26:40.07#ibcon#about to read 6, iclass 36, count 2 2006.183.08:26:40.07#ibcon#read 6, iclass 36, count 2 2006.183.08:26:40.07#ibcon#end of sib2, iclass 36, count 2 2006.183.08:26:40.07#ibcon#*mode == 0, iclass 36, count 2 2006.183.08:26:40.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.183.08:26:40.07#ibcon#[25=AT07-06\r\n] 2006.183.08:26:40.07#ibcon#*before write, iclass 36, count 2 2006.183.08:26:40.07#ibcon#enter sib2, iclass 36, count 2 2006.183.08:26:40.07#ibcon#flushed, iclass 36, count 2 2006.183.08:26:40.07#ibcon#about to write, iclass 36, count 2 2006.183.08:26:40.07#ibcon#wrote, iclass 36, count 2 2006.183.08:26:40.07#ibcon#about to read 3, iclass 36, count 2 2006.183.08:26:40.10#ibcon#read 3, iclass 36, count 2 2006.183.08:26:40.10#ibcon#about to read 4, iclass 36, count 2 2006.183.08:26:40.10#ibcon#read 4, iclass 36, count 2 2006.183.08:26:40.10#ibcon#about to read 5, iclass 36, count 2 2006.183.08:26:40.10#ibcon#read 5, iclass 36, count 2 2006.183.08:26:40.10#ibcon#about to read 6, iclass 36, count 2 2006.183.08:26:40.10#ibcon#read 6, iclass 36, count 2 2006.183.08:26:40.10#ibcon#end of sib2, iclass 36, count 2 2006.183.08:26:40.10#ibcon#*after write, iclass 36, count 2 2006.183.08:26:40.10#ibcon#*before return 0, iclass 36, count 2 2006.183.08:26:40.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:26:40.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.183.08:26:40.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.183.08:26:40.10#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:40.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:26:40.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:26:40.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:26:40.22#ibcon#enter wrdev, iclass 36, count 0 2006.183.08:26:40.22#ibcon#first serial, iclass 36, count 0 2006.183.08:26:40.22#ibcon#enter sib2, iclass 36, count 0 2006.183.08:26:40.22#ibcon#flushed, iclass 36, count 0 2006.183.08:26:40.22#ibcon#about to write, iclass 36, count 0 2006.183.08:26:40.22#ibcon#wrote, iclass 36, count 0 2006.183.08:26:40.22#ibcon#about to read 3, iclass 36, count 0 2006.183.08:26:40.24#ibcon#read 3, iclass 36, count 0 2006.183.08:26:40.24#ibcon#about to read 4, iclass 36, count 0 2006.183.08:26:40.24#ibcon#read 4, iclass 36, count 0 2006.183.08:26:40.24#ibcon#about to read 5, iclass 36, count 0 2006.183.08:26:40.24#ibcon#read 5, iclass 36, count 0 2006.183.08:26:40.24#ibcon#about to read 6, iclass 36, count 0 2006.183.08:26:40.24#ibcon#read 6, iclass 36, count 0 2006.183.08:26:40.24#ibcon#end of sib2, iclass 36, count 0 2006.183.08:26:40.24#ibcon#*mode == 0, iclass 36, count 0 2006.183.08:26:40.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.183.08:26:40.24#ibcon#[25=USB\r\n] 2006.183.08:26:40.24#ibcon#*before write, iclass 36, count 0 2006.183.08:26:40.24#ibcon#enter sib2, iclass 36, count 0 2006.183.08:26:40.24#ibcon#flushed, iclass 36, count 0 2006.183.08:26:40.24#ibcon#about to write, iclass 36, count 0 2006.183.08:26:40.24#ibcon#wrote, iclass 36, count 0 2006.183.08:26:40.24#ibcon#about to read 3, iclass 36, count 0 2006.183.08:26:40.27#ibcon#read 3, iclass 36, count 0 2006.183.08:26:40.27#ibcon#about to read 4, iclass 36, count 0 2006.183.08:26:40.27#ibcon#read 4, iclass 36, count 0 2006.183.08:26:40.27#ibcon#about to read 5, iclass 36, count 0 2006.183.08:26:40.27#ibcon#read 5, iclass 36, count 0 2006.183.08:26:40.27#ibcon#about to read 6, iclass 36, count 0 2006.183.08:26:40.27#ibcon#read 6, iclass 36, count 0 2006.183.08:26:40.27#ibcon#end of sib2, iclass 36, count 0 2006.183.08:26:40.27#ibcon#*after write, iclass 36, count 0 2006.183.08:26:40.27#ibcon#*before return 0, iclass 36, count 0 2006.183.08:26:40.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:26:40.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.183.08:26:40.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.183.08:26:40.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.183.08:26:40.27$vc4f8/valo=8,852.99 2006.183.08:26:40.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.183.08:26:40.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.183.08:26:40.27#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:40.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:26:40.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:26:40.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:26:40.27#ibcon#enter wrdev, iclass 38, count 0 2006.183.08:26:40.27#ibcon#first serial, iclass 38, count 0 2006.183.08:26:40.27#ibcon#enter sib2, iclass 38, count 0 2006.183.08:26:40.27#ibcon#flushed, iclass 38, count 0 2006.183.08:26:40.27#ibcon#about to write, iclass 38, count 0 2006.183.08:26:40.27#ibcon#wrote, iclass 38, count 0 2006.183.08:26:40.27#ibcon#about to read 3, iclass 38, count 0 2006.183.08:26:40.29#ibcon#read 3, iclass 38, count 0 2006.183.08:26:40.29#ibcon#about to read 4, iclass 38, count 0 2006.183.08:26:40.29#ibcon#read 4, iclass 38, count 0 2006.183.08:26:40.29#ibcon#about to read 5, iclass 38, count 0 2006.183.08:26:40.29#ibcon#read 5, iclass 38, count 0 2006.183.08:26:40.29#ibcon#about to read 6, iclass 38, count 0 2006.183.08:26:40.29#ibcon#read 6, iclass 38, count 0 2006.183.08:26:40.29#ibcon#end of sib2, iclass 38, count 0 2006.183.08:26:40.29#ibcon#*mode == 0, iclass 38, count 0 2006.183.08:26:40.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.183.08:26:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:26:40.29#ibcon#*before write, iclass 38, count 0 2006.183.08:26:40.29#ibcon#enter sib2, iclass 38, count 0 2006.183.08:26:40.29#ibcon#flushed, iclass 38, count 0 2006.183.08:26:40.29#ibcon#about to write, iclass 38, count 0 2006.183.08:26:40.29#ibcon#wrote, iclass 38, count 0 2006.183.08:26:40.29#ibcon#about to read 3, iclass 38, count 0 2006.183.08:26:40.33#ibcon#read 3, iclass 38, count 0 2006.183.08:26:40.33#ibcon#about to read 4, iclass 38, count 0 2006.183.08:26:40.33#ibcon#read 4, iclass 38, count 0 2006.183.08:26:40.33#ibcon#about to read 5, iclass 38, count 0 2006.183.08:26:40.33#ibcon#read 5, iclass 38, count 0 2006.183.08:26:40.33#ibcon#about to read 6, iclass 38, count 0 2006.183.08:26:40.33#ibcon#read 6, iclass 38, count 0 2006.183.08:26:40.33#ibcon#end of sib2, iclass 38, count 0 2006.183.08:26:40.33#ibcon#*after write, iclass 38, count 0 2006.183.08:26:40.33#ibcon#*before return 0, iclass 38, count 0 2006.183.08:26:40.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:26:40.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.183.08:26:40.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.183.08:26:40.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.183.08:26:40.33$vc4f8/va=8,7 2006.183.08:26:40.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.183.08:26:40.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.183.08:26:40.33#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:40.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:26:40.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:26:40.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:26:40.39#ibcon#enter wrdev, iclass 40, count 2 2006.183.08:26:40.39#ibcon#first serial, iclass 40, count 2 2006.183.08:26:40.39#ibcon#enter sib2, iclass 40, count 2 2006.183.08:26:40.39#ibcon#flushed, iclass 40, count 2 2006.183.08:26:40.39#ibcon#about to write, iclass 40, count 2 2006.183.08:26:40.39#ibcon#wrote, iclass 40, count 2 2006.183.08:26:40.39#ibcon#about to read 3, iclass 40, count 2 2006.183.08:26:40.41#ibcon#read 3, iclass 40, count 2 2006.183.08:26:40.41#ibcon#about to read 4, iclass 40, count 2 2006.183.08:26:40.41#ibcon#read 4, iclass 40, count 2 2006.183.08:26:40.41#ibcon#about to read 5, iclass 40, count 2 2006.183.08:26:40.41#ibcon#read 5, iclass 40, count 2 2006.183.08:26:40.41#ibcon#about to read 6, iclass 40, count 2 2006.183.08:26:40.41#ibcon#read 6, iclass 40, count 2 2006.183.08:26:40.41#ibcon#end of sib2, iclass 40, count 2 2006.183.08:26:40.41#ibcon#*mode == 0, iclass 40, count 2 2006.183.08:26:40.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.183.08:26:40.41#ibcon#[25=AT08-07\r\n] 2006.183.08:26:40.41#ibcon#*before write, iclass 40, count 2 2006.183.08:26:40.41#ibcon#enter sib2, iclass 40, count 2 2006.183.08:26:40.41#ibcon#flushed, iclass 40, count 2 2006.183.08:26:40.41#ibcon#about to write, iclass 40, count 2 2006.183.08:26:40.41#ibcon#wrote, iclass 40, count 2 2006.183.08:26:40.41#ibcon#about to read 3, iclass 40, count 2 2006.183.08:26:40.44#ibcon#read 3, iclass 40, count 2 2006.183.08:26:40.44#ibcon#about to read 4, iclass 40, count 2 2006.183.08:26:40.44#ibcon#read 4, iclass 40, count 2 2006.183.08:26:40.44#ibcon#about to read 5, iclass 40, count 2 2006.183.08:26:40.44#ibcon#read 5, iclass 40, count 2 2006.183.08:26:40.44#ibcon#about to read 6, iclass 40, count 2 2006.183.08:26:40.44#ibcon#read 6, iclass 40, count 2 2006.183.08:26:40.44#ibcon#end of sib2, iclass 40, count 2 2006.183.08:26:40.44#ibcon#*after write, iclass 40, count 2 2006.183.08:26:40.44#ibcon#*before return 0, iclass 40, count 2 2006.183.08:26:40.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:26:40.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.183.08:26:40.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.183.08:26:40.44#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:40.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:26:40.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:26:40.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:26:40.56#ibcon#enter wrdev, iclass 40, count 0 2006.183.08:26:40.56#ibcon#first serial, iclass 40, count 0 2006.183.08:26:40.56#ibcon#enter sib2, iclass 40, count 0 2006.183.08:26:40.56#ibcon#flushed, iclass 40, count 0 2006.183.08:26:40.56#ibcon#about to write, iclass 40, count 0 2006.183.08:26:40.56#ibcon#wrote, iclass 40, count 0 2006.183.08:26:40.56#ibcon#about to read 3, iclass 40, count 0 2006.183.08:26:40.58#ibcon#read 3, iclass 40, count 0 2006.183.08:26:40.58#ibcon#about to read 4, iclass 40, count 0 2006.183.08:26:40.58#ibcon#read 4, iclass 40, count 0 2006.183.08:26:40.58#ibcon#about to read 5, iclass 40, count 0 2006.183.08:26:40.58#ibcon#read 5, iclass 40, count 0 2006.183.08:26:40.58#ibcon#about to read 6, iclass 40, count 0 2006.183.08:26:40.58#ibcon#read 6, iclass 40, count 0 2006.183.08:26:40.58#ibcon#end of sib2, iclass 40, count 0 2006.183.08:26:40.58#ibcon#*mode == 0, iclass 40, count 0 2006.183.08:26:40.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.183.08:26:40.58#ibcon#[25=USB\r\n] 2006.183.08:26:40.58#ibcon#*before write, iclass 40, count 0 2006.183.08:26:40.58#ibcon#enter sib2, iclass 40, count 0 2006.183.08:26:40.58#ibcon#flushed, iclass 40, count 0 2006.183.08:26:40.58#ibcon#about to write, iclass 40, count 0 2006.183.08:26:40.58#ibcon#wrote, iclass 40, count 0 2006.183.08:26:40.58#ibcon#about to read 3, iclass 40, count 0 2006.183.08:26:40.61#ibcon#read 3, iclass 40, count 0 2006.183.08:26:40.61#ibcon#about to read 4, iclass 40, count 0 2006.183.08:26:40.61#ibcon#read 4, iclass 40, count 0 2006.183.08:26:40.61#ibcon#about to read 5, iclass 40, count 0 2006.183.08:26:40.61#ibcon#read 5, iclass 40, count 0 2006.183.08:26:40.61#ibcon#about to read 6, iclass 40, count 0 2006.183.08:26:40.61#ibcon#read 6, iclass 40, count 0 2006.183.08:26:40.61#ibcon#end of sib2, iclass 40, count 0 2006.183.08:26:40.61#ibcon#*after write, iclass 40, count 0 2006.183.08:26:40.61#ibcon#*before return 0, iclass 40, count 0 2006.183.08:26:40.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:26:40.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.183.08:26:40.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.183.08:26:40.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.183.08:26:40.61$vc4f8/vblo=1,632.99 2006.183.08:26:40.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.183.08:26:40.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.183.08:26:40.61#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:40.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:26:40.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:26:40.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:26:40.61#ibcon#enter wrdev, iclass 4, count 0 2006.183.08:26:40.61#ibcon#first serial, iclass 4, count 0 2006.183.08:26:40.61#ibcon#enter sib2, iclass 4, count 0 2006.183.08:26:40.61#ibcon#flushed, iclass 4, count 0 2006.183.08:26:40.61#ibcon#about to write, iclass 4, count 0 2006.183.08:26:40.61#ibcon#wrote, iclass 4, count 0 2006.183.08:26:40.61#ibcon#about to read 3, iclass 4, count 0 2006.183.08:26:40.63#ibcon#read 3, iclass 4, count 0 2006.183.08:26:40.63#ibcon#about to read 4, iclass 4, count 0 2006.183.08:26:40.63#ibcon#read 4, iclass 4, count 0 2006.183.08:26:40.63#ibcon#about to read 5, iclass 4, count 0 2006.183.08:26:40.63#ibcon#read 5, iclass 4, count 0 2006.183.08:26:40.63#ibcon#about to read 6, iclass 4, count 0 2006.183.08:26:40.63#ibcon#read 6, iclass 4, count 0 2006.183.08:26:40.63#ibcon#end of sib2, iclass 4, count 0 2006.183.08:26:40.63#ibcon#*mode == 0, iclass 4, count 0 2006.183.08:26:40.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.183.08:26:40.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:26:40.63#ibcon#*before write, iclass 4, count 0 2006.183.08:26:40.63#ibcon#enter sib2, iclass 4, count 0 2006.183.08:26:40.63#ibcon#flushed, iclass 4, count 0 2006.183.08:26:40.63#ibcon#about to write, iclass 4, count 0 2006.183.08:26:40.63#ibcon#wrote, iclass 4, count 0 2006.183.08:26:40.63#ibcon#about to read 3, iclass 4, count 0 2006.183.08:26:40.67#ibcon#read 3, iclass 4, count 0 2006.183.08:26:40.67#ibcon#about to read 4, iclass 4, count 0 2006.183.08:26:40.67#ibcon#read 4, iclass 4, count 0 2006.183.08:26:40.67#ibcon#about to read 5, iclass 4, count 0 2006.183.08:26:40.67#ibcon#read 5, iclass 4, count 0 2006.183.08:26:40.67#ibcon#about to read 6, iclass 4, count 0 2006.183.08:26:40.67#ibcon#read 6, iclass 4, count 0 2006.183.08:26:40.67#ibcon#end of sib2, iclass 4, count 0 2006.183.08:26:40.67#ibcon#*after write, iclass 4, count 0 2006.183.08:26:40.67#ibcon#*before return 0, iclass 4, count 0 2006.183.08:26:40.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:26:40.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.183.08:26:40.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.183.08:26:40.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.183.08:26:40.67$vc4f8/vb=1,4 2006.183.08:26:40.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.183.08:26:40.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.183.08:26:40.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:40.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:26:40.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:26:40.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:26:40.67#ibcon#enter wrdev, iclass 6, count 2 2006.183.08:26:40.67#ibcon#first serial, iclass 6, count 2 2006.183.08:26:40.67#ibcon#enter sib2, iclass 6, count 2 2006.183.08:26:40.67#ibcon#flushed, iclass 6, count 2 2006.183.08:26:40.67#ibcon#about to write, iclass 6, count 2 2006.183.08:26:40.67#ibcon#wrote, iclass 6, count 2 2006.183.08:26:40.67#ibcon#about to read 3, iclass 6, count 2 2006.183.08:26:40.69#ibcon#read 3, iclass 6, count 2 2006.183.08:26:40.69#ibcon#about to read 4, iclass 6, count 2 2006.183.08:26:40.69#ibcon#read 4, iclass 6, count 2 2006.183.08:26:40.69#ibcon#about to read 5, iclass 6, count 2 2006.183.08:26:40.69#ibcon#read 5, iclass 6, count 2 2006.183.08:26:40.69#ibcon#about to read 6, iclass 6, count 2 2006.183.08:26:40.69#ibcon#read 6, iclass 6, count 2 2006.183.08:26:40.69#ibcon#end of sib2, iclass 6, count 2 2006.183.08:26:40.69#ibcon#*mode == 0, iclass 6, count 2 2006.183.08:26:40.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.183.08:26:40.69#ibcon#[27=AT01-04\r\n] 2006.183.08:26:40.69#ibcon#*before write, iclass 6, count 2 2006.183.08:26:40.69#ibcon#enter sib2, iclass 6, count 2 2006.183.08:26:40.69#ibcon#flushed, iclass 6, count 2 2006.183.08:26:40.69#ibcon#about to write, iclass 6, count 2 2006.183.08:26:40.69#ibcon#wrote, iclass 6, count 2 2006.183.08:26:40.69#ibcon#about to read 3, iclass 6, count 2 2006.183.08:26:40.72#ibcon#read 3, iclass 6, count 2 2006.183.08:26:40.72#ibcon#about to read 4, iclass 6, count 2 2006.183.08:26:40.72#ibcon#read 4, iclass 6, count 2 2006.183.08:26:40.72#ibcon#about to read 5, iclass 6, count 2 2006.183.08:26:40.72#ibcon#read 5, iclass 6, count 2 2006.183.08:26:40.72#ibcon#about to read 6, iclass 6, count 2 2006.183.08:26:40.72#ibcon#read 6, iclass 6, count 2 2006.183.08:26:40.72#ibcon#end of sib2, iclass 6, count 2 2006.183.08:26:40.72#ibcon#*after write, iclass 6, count 2 2006.183.08:26:40.72#ibcon#*before return 0, iclass 6, count 2 2006.183.08:26:40.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:26:40.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.183.08:26:40.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.183.08:26:40.72#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:40.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:26:40.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:26:40.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:26:40.84#ibcon#enter wrdev, iclass 6, count 0 2006.183.08:26:40.84#ibcon#first serial, iclass 6, count 0 2006.183.08:26:40.84#ibcon#enter sib2, iclass 6, count 0 2006.183.08:26:40.84#ibcon#flushed, iclass 6, count 0 2006.183.08:26:40.84#ibcon#about to write, iclass 6, count 0 2006.183.08:26:40.84#ibcon#wrote, iclass 6, count 0 2006.183.08:26:40.84#ibcon#about to read 3, iclass 6, count 0 2006.183.08:26:40.86#ibcon#read 3, iclass 6, count 0 2006.183.08:26:40.86#ibcon#about to read 4, iclass 6, count 0 2006.183.08:26:40.86#ibcon#read 4, iclass 6, count 0 2006.183.08:26:40.86#ibcon#about to read 5, iclass 6, count 0 2006.183.08:26:40.86#ibcon#read 5, iclass 6, count 0 2006.183.08:26:40.86#ibcon#about to read 6, iclass 6, count 0 2006.183.08:26:40.86#ibcon#read 6, iclass 6, count 0 2006.183.08:26:40.86#ibcon#end of sib2, iclass 6, count 0 2006.183.08:26:40.86#ibcon#*mode == 0, iclass 6, count 0 2006.183.08:26:40.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.183.08:26:40.86#ibcon#[27=USB\r\n] 2006.183.08:26:40.86#ibcon#*before write, iclass 6, count 0 2006.183.08:26:40.86#ibcon#enter sib2, iclass 6, count 0 2006.183.08:26:40.86#ibcon#flushed, iclass 6, count 0 2006.183.08:26:40.86#ibcon#about to write, iclass 6, count 0 2006.183.08:26:40.86#ibcon#wrote, iclass 6, count 0 2006.183.08:26:40.86#ibcon#about to read 3, iclass 6, count 0 2006.183.08:26:40.89#ibcon#read 3, iclass 6, count 0 2006.183.08:26:40.89#ibcon#about to read 4, iclass 6, count 0 2006.183.08:26:40.89#ibcon#read 4, iclass 6, count 0 2006.183.08:26:40.89#ibcon#about to read 5, iclass 6, count 0 2006.183.08:26:40.89#ibcon#read 5, iclass 6, count 0 2006.183.08:26:40.89#ibcon#about to read 6, iclass 6, count 0 2006.183.08:26:40.89#ibcon#read 6, iclass 6, count 0 2006.183.08:26:40.89#ibcon#end of sib2, iclass 6, count 0 2006.183.08:26:40.89#ibcon#*after write, iclass 6, count 0 2006.183.08:26:40.89#ibcon#*before return 0, iclass 6, count 0 2006.183.08:26:40.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:26:40.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.183.08:26:40.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.183.08:26:40.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.183.08:26:40.89$vc4f8/vblo=2,640.99 2006.183.08:26:40.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.183.08:26:40.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.183.08:26:40.89#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:40.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:40.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:40.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:40.89#ibcon#enter wrdev, iclass 10, count 0 2006.183.08:26:40.89#ibcon#first serial, iclass 10, count 0 2006.183.08:26:40.89#ibcon#enter sib2, iclass 10, count 0 2006.183.08:26:40.89#ibcon#flushed, iclass 10, count 0 2006.183.08:26:40.89#ibcon#about to write, iclass 10, count 0 2006.183.08:26:40.89#ibcon#wrote, iclass 10, count 0 2006.183.08:26:40.89#ibcon#about to read 3, iclass 10, count 0 2006.183.08:26:40.91#ibcon#read 3, iclass 10, count 0 2006.183.08:26:40.91#ibcon#about to read 4, iclass 10, count 0 2006.183.08:26:40.91#ibcon#read 4, iclass 10, count 0 2006.183.08:26:40.91#ibcon#about to read 5, iclass 10, count 0 2006.183.08:26:40.91#ibcon#read 5, iclass 10, count 0 2006.183.08:26:40.91#ibcon#about to read 6, iclass 10, count 0 2006.183.08:26:40.91#ibcon#read 6, iclass 10, count 0 2006.183.08:26:40.91#ibcon#end of sib2, iclass 10, count 0 2006.183.08:26:40.91#ibcon#*mode == 0, iclass 10, count 0 2006.183.08:26:40.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.183.08:26:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:26:40.91#ibcon#*before write, iclass 10, count 0 2006.183.08:26:40.91#ibcon#enter sib2, iclass 10, count 0 2006.183.08:26:40.91#ibcon#flushed, iclass 10, count 0 2006.183.08:26:40.91#ibcon#about to write, iclass 10, count 0 2006.183.08:26:40.91#ibcon#wrote, iclass 10, count 0 2006.183.08:26:40.91#ibcon#about to read 3, iclass 10, count 0 2006.183.08:26:40.95#ibcon#read 3, iclass 10, count 0 2006.183.08:26:40.95#ibcon#about to read 4, iclass 10, count 0 2006.183.08:26:40.95#ibcon#read 4, iclass 10, count 0 2006.183.08:26:40.95#ibcon#about to read 5, iclass 10, count 0 2006.183.08:26:40.95#ibcon#read 5, iclass 10, count 0 2006.183.08:26:40.95#ibcon#about to read 6, iclass 10, count 0 2006.183.08:26:40.95#ibcon#read 6, iclass 10, count 0 2006.183.08:26:40.95#ibcon#end of sib2, iclass 10, count 0 2006.183.08:26:40.95#ibcon#*after write, iclass 10, count 0 2006.183.08:26:40.95#ibcon#*before return 0, iclass 10, count 0 2006.183.08:26:40.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:40.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.183.08:26:40.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.183.08:26:40.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.183.08:26:40.95$vc4f8/vb=2,4 2006.183.08:26:40.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.183.08:26:40.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.183.08:26:40.95#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:40.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:41.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:41.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:41.01#ibcon#enter wrdev, iclass 12, count 2 2006.183.08:26:41.01#ibcon#first serial, iclass 12, count 2 2006.183.08:26:41.01#ibcon#enter sib2, iclass 12, count 2 2006.183.08:26:41.01#ibcon#flushed, iclass 12, count 2 2006.183.08:26:41.01#ibcon#about to write, iclass 12, count 2 2006.183.08:26:41.01#ibcon#wrote, iclass 12, count 2 2006.183.08:26:41.01#ibcon#about to read 3, iclass 12, count 2 2006.183.08:26:41.03#ibcon#read 3, iclass 12, count 2 2006.183.08:26:41.03#ibcon#about to read 4, iclass 12, count 2 2006.183.08:26:41.03#ibcon#read 4, iclass 12, count 2 2006.183.08:26:41.03#ibcon#about to read 5, iclass 12, count 2 2006.183.08:26:41.03#ibcon#read 5, iclass 12, count 2 2006.183.08:26:41.03#ibcon#about to read 6, iclass 12, count 2 2006.183.08:26:41.03#ibcon#read 6, iclass 12, count 2 2006.183.08:26:41.03#ibcon#end of sib2, iclass 12, count 2 2006.183.08:26:41.03#ibcon#*mode == 0, iclass 12, count 2 2006.183.08:26:41.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.183.08:26:41.03#ibcon#[27=AT02-04\r\n] 2006.183.08:26:41.03#ibcon#*before write, iclass 12, count 2 2006.183.08:26:41.03#ibcon#enter sib2, iclass 12, count 2 2006.183.08:26:41.03#ibcon#flushed, iclass 12, count 2 2006.183.08:26:41.03#ibcon#about to write, iclass 12, count 2 2006.183.08:26:41.03#ibcon#wrote, iclass 12, count 2 2006.183.08:26:41.03#ibcon#about to read 3, iclass 12, count 2 2006.183.08:26:41.06#ibcon#read 3, iclass 12, count 2 2006.183.08:26:41.06#ibcon#about to read 4, iclass 12, count 2 2006.183.08:26:41.06#ibcon#read 4, iclass 12, count 2 2006.183.08:26:41.06#ibcon#about to read 5, iclass 12, count 2 2006.183.08:26:41.06#ibcon#read 5, iclass 12, count 2 2006.183.08:26:41.06#ibcon#about to read 6, iclass 12, count 2 2006.183.08:26:41.06#ibcon#read 6, iclass 12, count 2 2006.183.08:26:41.06#ibcon#end of sib2, iclass 12, count 2 2006.183.08:26:41.06#ibcon#*after write, iclass 12, count 2 2006.183.08:26:41.06#ibcon#*before return 0, iclass 12, count 2 2006.183.08:26:41.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:41.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.183.08:26:41.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.183.08:26:41.06#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:41.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:41.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:41.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:41.18#ibcon#enter wrdev, iclass 12, count 0 2006.183.08:26:41.18#ibcon#first serial, iclass 12, count 0 2006.183.08:26:41.18#ibcon#enter sib2, iclass 12, count 0 2006.183.08:26:41.18#ibcon#flushed, iclass 12, count 0 2006.183.08:26:41.18#ibcon#about to write, iclass 12, count 0 2006.183.08:26:41.18#ibcon#wrote, iclass 12, count 0 2006.183.08:26:41.18#ibcon#about to read 3, iclass 12, count 0 2006.183.08:26:41.20#ibcon#read 3, iclass 12, count 0 2006.183.08:26:41.20#ibcon#about to read 4, iclass 12, count 0 2006.183.08:26:41.20#ibcon#read 4, iclass 12, count 0 2006.183.08:26:41.20#ibcon#about to read 5, iclass 12, count 0 2006.183.08:26:41.20#ibcon#read 5, iclass 12, count 0 2006.183.08:26:41.20#ibcon#about to read 6, iclass 12, count 0 2006.183.08:26:41.20#ibcon#read 6, iclass 12, count 0 2006.183.08:26:41.20#ibcon#end of sib2, iclass 12, count 0 2006.183.08:26:41.20#ibcon#*mode == 0, iclass 12, count 0 2006.183.08:26:41.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.183.08:26:41.20#ibcon#[27=USB\r\n] 2006.183.08:26:41.20#ibcon#*before write, iclass 12, count 0 2006.183.08:26:41.20#ibcon#enter sib2, iclass 12, count 0 2006.183.08:26:41.20#ibcon#flushed, iclass 12, count 0 2006.183.08:26:41.20#ibcon#about to write, iclass 12, count 0 2006.183.08:26:41.20#ibcon#wrote, iclass 12, count 0 2006.183.08:26:41.20#ibcon#about to read 3, iclass 12, count 0 2006.183.08:26:41.23#ibcon#read 3, iclass 12, count 0 2006.183.08:26:41.23#ibcon#about to read 4, iclass 12, count 0 2006.183.08:26:41.23#ibcon#read 4, iclass 12, count 0 2006.183.08:26:41.23#ibcon#about to read 5, iclass 12, count 0 2006.183.08:26:41.23#ibcon#read 5, iclass 12, count 0 2006.183.08:26:41.23#ibcon#about to read 6, iclass 12, count 0 2006.183.08:26:41.23#ibcon#read 6, iclass 12, count 0 2006.183.08:26:41.23#ibcon#end of sib2, iclass 12, count 0 2006.183.08:26:41.23#ibcon#*after write, iclass 12, count 0 2006.183.08:26:41.23#ibcon#*before return 0, iclass 12, count 0 2006.183.08:26:41.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:41.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.183.08:26:41.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.183.08:26:41.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.183.08:26:41.23$vc4f8/vblo=3,656.99 2006.183.08:26:41.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.183.08:26:41.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.183.08:26:41.23#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:41.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:41.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:41.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:41.23#ibcon#enter wrdev, iclass 14, count 0 2006.183.08:26:41.23#ibcon#first serial, iclass 14, count 0 2006.183.08:26:41.23#ibcon#enter sib2, iclass 14, count 0 2006.183.08:26:41.23#ibcon#flushed, iclass 14, count 0 2006.183.08:26:41.23#ibcon#about to write, iclass 14, count 0 2006.183.08:26:41.23#ibcon#wrote, iclass 14, count 0 2006.183.08:26:41.23#ibcon#about to read 3, iclass 14, count 0 2006.183.08:26:41.25#ibcon#read 3, iclass 14, count 0 2006.183.08:26:41.25#ibcon#about to read 4, iclass 14, count 0 2006.183.08:26:41.25#ibcon#read 4, iclass 14, count 0 2006.183.08:26:41.25#ibcon#about to read 5, iclass 14, count 0 2006.183.08:26:41.25#ibcon#read 5, iclass 14, count 0 2006.183.08:26:41.25#ibcon#about to read 6, iclass 14, count 0 2006.183.08:26:41.25#ibcon#read 6, iclass 14, count 0 2006.183.08:26:41.25#ibcon#end of sib2, iclass 14, count 0 2006.183.08:26:41.25#ibcon#*mode == 0, iclass 14, count 0 2006.183.08:26:41.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.183.08:26:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:26:41.25#ibcon#*before write, iclass 14, count 0 2006.183.08:26:41.25#ibcon#enter sib2, iclass 14, count 0 2006.183.08:26:41.25#ibcon#flushed, iclass 14, count 0 2006.183.08:26:41.25#ibcon#about to write, iclass 14, count 0 2006.183.08:26:41.25#ibcon#wrote, iclass 14, count 0 2006.183.08:26:41.25#ibcon#about to read 3, iclass 14, count 0 2006.183.08:26:41.29#ibcon#read 3, iclass 14, count 0 2006.183.08:26:41.29#ibcon#about to read 4, iclass 14, count 0 2006.183.08:26:41.29#ibcon#read 4, iclass 14, count 0 2006.183.08:26:41.29#ibcon#about to read 5, iclass 14, count 0 2006.183.08:26:41.29#ibcon#read 5, iclass 14, count 0 2006.183.08:26:41.29#ibcon#about to read 6, iclass 14, count 0 2006.183.08:26:41.29#ibcon#read 6, iclass 14, count 0 2006.183.08:26:41.29#ibcon#end of sib2, iclass 14, count 0 2006.183.08:26:41.29#ibcon#*after write, iclass 14, count 0 2006.183.08:26:41.29#ibcon#*before return 0, iclass 14, count 0 2006.183.08:26:41.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:41.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.183.08:26:41.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.183.08:26:41.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.183.08:26:41.29$vc4f8/vb=3,4 2006.183.08:26:41.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.183.08:26:41.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.183.08:26:41.29#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:41.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:41.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:41.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:41.35#ibcon#enter wrdev, iclass 16, count 2 2006.183.08:26:41.35#ibcon#first serial, iclass 16, count 2 2006.183.08:26:41.35#ibcon#enter sib2, iclass 16, count 2 2006.183.08:26:41.35#ibcon#flushed, iclass 16, count 2 2006.183.08:26:41.35#ibcon#about to write, iclass 16, count 2 2006.183.08:26:41.35#ibcon#wrote, iclass 16, count 2 2006.183.08:26:41.35#ibcon#about to read 3, iclass 16, count 2 2006.183.08:26:41.37#ibcon#read 3, iclass 16, count 2 2006.183.08:26:41.37#ibcon#about to read 4, iclass 16, count 2 2006.183.08:26:41.37#ibcon#read 4, iclass 16, count 2 2006.183.08:26:41.37#ibcon#about to read 5, iclass 16, count 2 2006.183.08:26:41.37#ibcon#read 5, iclass 16, count 2 2006.183.08:26:41.37#ibcon#about to read 6, iclass 16, count 2 2006.183.08:26:41.37#ibcon#read 6, iclass 16, count 2 2006.183.08:26:41.37#ibcon#end of sib2, iclass 16, count 2 2006.183.08:26:41.37#ibcon#*mode == 0, iclass 16, count 2 2006.183.08:26:41.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.183.08:26:41.37#ibcon#[27=AT03-04\r\n] 2006.183.08:26:41.37#ibcon#*before write, iclass 16, count 2 2006.183.08:26:41.37#ibcon#enter sib2, iclass 16, count 2 2006.183.08:26:41.37#ibcon#flushed, iclass 16, count 2 2006.183.08:26:41.37#ibcon#about to write, iclass 16, count 2 2006.183.08:26:41.37#ibcon#wrote, iclass 16, count 2 2006.183.08:26:41.37#ibcon#about to read 3, iclass 16, count 2 2006.183.08:26:41.40#ibcon#read 3, iclass 16, count 2 2006.183.08:26:41.40#ibcon#about to read 4, iclass 16, count 2 2006.183.08:26:41.40#ibcon#read 4, iclass 16, count 2 2006.183.08:26:41.40#ibcon#about to read 5, iclass 16, count 2 2006.183.08:26:41.40#ibcon#read 5, iclass 16, count 2 2006.183.08:26:41.40#ibcon#about to read 6, iclass 16, count 2 2006.183.08:26:41.40#ibcon#read 6, iclass 16, count 2 2006.183.08:26:41.40#ibcon#end of sib2, iclass 16, count 2 2006.183.08:26:41.40#ibcon#*after write, iclass 16, count 2 2006.183.08:26:41.40#ibcon#*before return 0, iclass 16, count 2 2006.183.08:26:41.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:41.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.183.08:26:41.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.183.08:26:41.40#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:41.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:41.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:41.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:41.52#ibcon#enter wrdev, iclass 16, count 0 2006.183.08:26:41.52#ibcon#first serial, iclass 16, count 0 2006.183.08:26:41.52#ibcon#enter sib2, iclass 16, count 0 2006.183.08:26:41.52#ibcon#flushed, iclass 16, count 0 2006.183.08:26:41.52#ibcon#about to write, iclass 16, count 0 2006.183.08:26:41.52#ibcon#wrote, iclass 16, count 0 2006.183.08:26:41.52#ibcon#about to read 3, iclass 16, count 0 2006.183.08:26:41.54#ibcon#read 3, iclass 16, count 0 2006.183.08:26:41.54#ibcon#about to read 4, iclass 16, count 0 2006.183.08:26:41.54#ibcon#read 4, iclass 16, count 0 2006.183.08:26:41.54#ibcon#about to read 5, iclass 16, count 0 2006.183.08:26:41.54#ibcon#read 5, iclass 16, count 0 2006.183.08:26:41.54#ibcon#about to read 6, iclass 16, count 0 2006.183.08:26:41.54#ibcon#read 6, iclass 16, count 0 2006.183.08:26:41.54#ibcon#end of sib2, iclass 16, count 0 2006.183.08:26:41.54#ibcon#*mode == 0, iclass 16, count 0 2006.183.08:26:41.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.183.08:26:41.54#ibcon#[27=USB\r\n] 2006.183.08:26:41.54#ibcon#*before write, iclass 16, count 0 2006.183.08:26:41.54#ibcon#enter sib2, iclass 16, count 0 2006.183.08:26:41.54#ibcon#flushed, iclass 16, count 0 2006.183.08:26:41.54#ibcon#about to write, iclass 16, count 0 2006.183.08:26:41.54#ibcon#wrote, iclass 16, count 0 2006.183.08:26:41.54#ibcon#about to read 3, iclass 16, count 0 2006.183.08:26:41.57#ibcon#read 3, iclass 16, count 0 2006.183.08:26:41.57#ibcon#about to read 4, iclass 16, count 0 2006.183.08:26:41.57#ibcon#read 4, iclass 16, count 0 2006.183.08:26:41.57#ibcon#about to read 5, iclass 16, count 0 2006.183.08:26:41.57#ibcon#read 5, iclass 16, count 0 2006.183.08:26:41.57#ibcon#about to read 6, iclass 16, count 0 2006.183.08:26:41.57#ibcon#read 6, iclass 16, count 0 2006.183.08:26:41.57#ibcon#end of sib2, iclass 16, count 0 2006.183.08:26:41.57#ibcon#*after write, iclass 16, count 0 2006.183.08:26:41.57#ibcon#*before return 0, iclass 16, count 0 2006.183.08:26:41.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:41.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.183.08:26:41.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.183.08:26:41.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.183.08:26:41.57$vc4f8/vblo=4,712.99 2006.183.08:26:41.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.183.08:26:41.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.183.08:26:41.57#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:41.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:41.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:41.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:41.57#ibcon#enter wrdev, iclass 18, count 0 2006.183.08:26:41.57#ibcon#first serial, iclass 18, count 0 2006.183.08:26:41.57#ibcon#enter sib2, iclass 18, count 0 2006.183.08:26:41.57#ibcon#flushed, iclass 18, count 0 2006.183.08:26:41.57#ibcon#about to write, iclass 18, count 0 2006.183.08:26:41.57#ibcon#wrote, iclass 18, count 0 2006.183.08:26:41.57#ibcon#about to read 3, iclass 18, count 0 2006.183.08:26:41.59#ibcon#read 3, iclass 18, count 0 2006.183.08:26:41.59#ibcon#about to read 4, iclass 18, count 0 2006.183.08:26:41.59#ibcon#read 4, iclass 18, count 0 2006.183.08:26:41.59#ibcon#about to read 5, iclass 18, count 0 2006.183.08:26:41.59#ibcon#read 5, iclass 18, count 0 2006.183.08:26:41.59#ibcon#about to read 6, iclass 18, count 0 2006.183.08:26:41.59#ibcon#read 6, iclass 18, count 0 2006.183.08:26:41.59#ibcon#end of sib2, iclass 18, count 0 2006.183.08:26:41.59#ibcon#*mode == 0, iclass 18, count 0 2006.183.08:26:41.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.183.08:26:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:26:41.59#ibcon#*before write, iclass 18, count 0 2006.183.08:26:41.59#ibcon#enter sib2, iclass 18, count 0 2006.183.08:26:41.59#ibcon#flushed, iclass 18, count 0 2006.183.08:26:41.59#ibcon#about to write, iclass 18, count 0 2006.183.08:26:41.59#ibcon#wrote, iclass 18, count 0 2006.183.08:26:41.59#ibcon#about to read 3, iclass 18, count 0 2006.183.08:26:41.63#ibcon#read 3, iclass 18, count 0 2006.183.08:26:41.63#ibcon#about to read 4, iclass 18, count 0 2006.183.08:26:41.63#ibcon#read 4, iclass 18, count 0 2006.183.08:26:41.63#ibcon#about to read 5, iclass 18, count 0 2006.183.08:26:41.63#ibcon#read 5, iclass 18, count 0 2006.183.08:26:41.63#ibcon#about to read 6, iclass 18, count 0 2006.183.08:26:41.63#ibcon#read 6, iclass 18, count 0 2006.183.08:26:41.63#ibcon#end of sib2, iclass 18, count 0 2006.183.08:26:41.63#ibcon#*after write, iclass 18, count 0 2006.183.08:26:41.63#ibcon#*before return 0, iclass 18, count 0 2006.183.08:26:41.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:41.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.183.08:26:41.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.183.08:26:41.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.183.08:26:41.63$vc4f8/vb=4,4 2006.183.08:26:41.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.183.08:26:41.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.183.08:26:41.63#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:41.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:41.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:41.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:41.69#ibcon#enter wrdev, iclass 20, count 2 2006.183.08:26:41.69#ibcon#first serial, iclass 20, count 2 2006.183.08:26:41.69#ibcon#enter sib2, iclass 20, count 2 2006.183.08:26:41.69#ibcon#flushed, iclass 20, count 2 2006.183.08:26:41.69#ibcon#about to write, iclass 20, count 2 2006.183.08:26:41.69#ibcon#wrote, iclass 20, count 2 2006.183.08:26:41.69#ibcon#about to read 3, iclass 20, count 2 2006.183.08:26:41.71#ibcon#read 3, iclass 20, count 2 2006.183.08:26:41.71#ibcon#about to read 4, iclass 20, count 2 2006.183.08:26:41.71#ibcon#read 4, iclass 20, count 2 2006.183.08:26:41.71#ibcon#about to read 5, iclass 20, count 2 2006.183.08:26:41.71#ibcon#read 5, iclass 20, count 2 2006.183.08:26:41.71#ibcon#about to read 6, iclass 20, count 2 2006.183.08:26:41.71#ibcon#read 6, iclass 20, count 2 2006.183.08:26:41.71#ibcon#end of sib2, iclass 20, count 2 2006.183.08:26:41.71#ibcon#*mode == 0, iclass 20, count 2 2006.183.08:26:41.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.183.08:26:41.71#ibcon#[27=AT04-04\r\n] 2006.183.08:26:41.71#ibcon#*before write, iclass 20, count 2 2006.183.08:26:41.71#ibcon#enter sib2, iclass 20, count 2 2006.183.08:26:41.71#ibcon#flushed, iclass 20, count 2 2006.183.08:26:41.71#ibcon#about to write, iclass 20, count 2 2006.183.08:26:41.71#ibcon#wrote, iclass 20, count 2 2006.183.08:26:41.71#ibcon#about to read 3, iclass 20, count 2 2006.183.08:26:41.74#ibcon#read 3, iclass 20, count 2 2006.183.08:26:41.74#ibcon#about to read 4, iclass 20, count 2 2006.183.08:26:41.74#ibcon#read 4, iclass 20, count 2 2006.183.08:26:41.74#ibcon#about to read 5, iclass 20, count 2 2006.183.08:26:41.74#ibcon#read 5, iclass 20, count 2 2006.183.08:26:41.74#ibcon#about to read 6, iclass 20, count 2 2006.183.08:26:41.74#ibcon#read 6, iclass 20, count 2 2006.183.08:26:41.74#ibcon#end of sib2, iclass 20, count 2 2006.183.08:26:41.74#ibcon#*after write, iclass 20, count 2 2006.183.08:26:41.74#ibcon#*before return 0, iclass 20, count 2 2006.183.08:26:41.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:41.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.183.08:26:41.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.183.08:26:41.74#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:41.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:41.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:41.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:41.86#ibcon#enter wrdev, iclass 20, count 0 2006.183.08:26:41.86#ibcon#first serial, iclass 20, count 0 2006.183.08:26:41.86#ibcon#enter sib2, iclass 20, count 0 2006.183.08:26:41.86#ibcon#flushed, iclass 20, count 0 2006.183.08:26:41.86#ibcon#about to write, iclass 20, count 0 2006.183.08:26:41.86#ibcon#wrote, iclass 20, count 0 2006.183.08:26:41.86#ibcon#about to read 3, iclass 20, count 0 2006.183.08:26:41.88#ibcon#read 3, iclass 20, count 0 2006.183.08:26:41.88#ibcon#about to read 4, iclass 20, count 0 2006.183.08:26:41.88#ibcon#read 4, iclass 20, count 0 2006.183.08:26:41.88#ibcon#about to read 5, iclass 20, count 0 2006.183.08:26:41.88#ibcon#read 5, iclass 20, count 0 2006.183.08:26:41.88#ibcon#about to read 6, iclass 20, count 0 2006.183.08:26:41.88#ibcon#read 6, iclass 20, count 0 2006.183.08:26:41.88#ibcon#end of sib2, iclass 20, count 0 2006.183.08:26:41.88#ibcon#*mode == 0, iclass 20, count 0 2006.183.08:26:41.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.183.08:26:41.88#ibcon#[27=USB\r\n] 2006.183.08:26:41.88#ibcon#*before write, iclass 20, count 0 2006.183.08:26:41.88#ibcon#enter sib2, iclass 20, count 0 2006.183.08:26:41.88#ibcon#flushed, iclass 20, count 0 2006.183.08:26:41.88#ibcon#about to write, iclass 20, count 0 2006.183.08:26:41.88#ibcon#wrote, iclass 20, count 0 2006.183.08:26:41.88#ibcon#about to read 3, iclass 20, count 0 2006.183.08:26:41.91#ibcon#read 3, iclass 20, count 0 2006.183.08:26:41.91#ibcon#about to read 4, iclass 20, count 0 2006.183.08:26:41.91#ibcon#read 4, iclass 20, count 0 2006.183.08:26:41.91#ibcon#about to read 5, iclass 20, count 0 2006.183.08:26:41.91#ibcon#read 5, iclass 20, count 0 2006.183.08:26:41.91#ibcon#about to read 6, iclass 20, count 0 2006.183.08:26:41.91#ibcon#read 6, iclass 20, count 0 2006.183.08:26:41.91#ibcon#end of sib2, iclass 20, count 0 2006.183.08:26:41.91#ibcon#*after write, iclass 20, count 0 2006.183.08:26:41.91#ibcon#*before return 0, iclass 20, count 0 2006.183.08:26:41.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:41.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.183.08:26:41.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.183.08:26:41.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.183.08:26:41.91$vc4f8/vblo=5,744.99 2006.183.08:26:41.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.183.08:26:41.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.183.08:26:41.91#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:41.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:41.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:41.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:41.91#ibcon#enter wrdev, iclass 22, count 0 2006.183.08:26:41.91#ibcon#first serial, iclass 22, count 0 2006.183.08:26:41.91#ibcon#enter sib2, iclass 22, count 0 2006.183.08:26:41.91#ibcon#flushed, iclass 22, count 0 2006.183.08:26:41.91#ibcon#about to write, iclass 22, count 0 2006.183.08:26:41.91#ibcon#wrote, iclass 22, count 0 2006.183.08:26:41.91#ibcon#about to read 3, iclass 22, count 0 2006.183.08:26:41.93#ibcon#read 3, iclass 22, count 0 2006.183.08:26:41.93#ibcon#about to read 4, iclass 22, count 0 2006.183.08:26:41.93#ibcon#read 4, iclass 22, count 0 2006.183.08:26:41.93#ibcon#about to read 5, iclass 22, count 0 2006.183.08:26:41.93#ibcon#read 5, iclass 22, count 0 2006.183.08:26:41.93#ibcon#about to read 6, iclass 22, count 0 2006.183.08:26:41.93#ibcon#read 6, iclass 22, count 0 2006.183.08:26:41.93#ibcon#end of sib2, iclass 22, count 0 2006.183.08:26:41.93#ibcon#*mode == 0, iclass 22, count 0 2006.183.08:26:41.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.183.08:26:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:26:41.93#ibcon#*before write, iclass 22, count 0 2006.183.08:26:41.93#ibcon#enter sib2, iclass 22, count 0 2006.183.08:26:41.93#ibcon#flushed, iclass 22, count 0 2006.183.08:26:41.93#ibcon#about to write, iclass 22, count 0 2006.183.08:26:41.93#ibcon#wrote, iclass 22, count 0 2006.183.08:26:41.93#ibcon#about to read 3, iclass 22, count 0 2006.183.08:26:41.97#ibcon#read 3, iclass 22, count 0 2006.183.08:26:41.97#ibcon#about to read 4, iclass 22, count 0 2006.183.08:26:41.97#ibcon#read 4, iclass 22, count 0 2006.183.08:26:41.97#ibcon#about to read 5, iclass 22, count 0 2006.183.08:26:41.97#ibcon#read 5, iclass 22, count 0 2006.183.08:26:41.97#ibcon#about to read 6, iclass 22, count 0 2006.183.08:26:41.97#ibcon#read 6, iclass 22, count 0 2006.183.08:26:41.97#ibcon#end of sib2, iclass 22, count 0 2006.183.08:26:41.97#ibcon#*after write, iclass 22, count 0 2006.183.08:26:41.97#ibcon#*before return 0, iclass 22, count 0 2006.183.08:26:41.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:41.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.183.08:26:41.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.183.08:26:41.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.183.08:26:41.97$vc4f8/vb=5,4 2006.183.08:26:41.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.183.08:26:41.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.183.08:26:41.97#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:41.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:42.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:42.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:42.03#ibcon#enter wrdev, iclass 24, count 2 2006.183.08:26:42.03#ibcon#first serial, iclass 24, count 2 2006.183.08:26:42.03#ibcon#enter sib2, iclass 24, count 2 2006.183.08:26:42.03#ibcon#flushed, iclass 24, count 2 2006.183.08:26:42.03#ibcon#about to write, iclass 24, count 2 2006.183.08:26:42.03#ibcon#wrote, iclass 24, count 2 2006.183.08:26:42.03#ibcon#about to read 3, iclass 24, count 2 2006.183.08:26:42.05#ibcon#read 3, iclass 24, count 2 2006.183.08:26:42.05#ibcon#about to read 4, iclass 24, count 2 2006.183.08:26:42.05#ibcon#read 4, iclass 24, count 2 2006.183.08:26:42.05#ibcon#about to read 5, iclass 24, count 2 2006.183.08:26:42.05#ibcon#read 5, iclass 24, count 2 2006.183.08:26:42.05#ibcon#about to read 6, iclass 24, count 2 2006.183.08:26:42.05#ibcon#read 6, iclass 24, count 2 2006.183.08:26:42.05#ibcon#end of sib2, iclass 24, count 2 2006.183.08:26:42.05#ibcon#*mode == 0, iclass 24, count 2 2006.183.08:26:42.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.183.08:26:42.05#ibcon#[27=AT05-04\r\n] 2006.183.08:26:42.05#ibcon#*before write, iclass 24, count 2 2006.183.08:26:42.05#ibcon#enter sib2, iclass 24, count 2 2006.183.08:26:42.05#ibcon#flushed, iclass 24, count 2 2006.183.08:26:42.05#ibcon#about to write, iclass 24, count 2 2006.183.08:26:42.05#ibcon#wrote, iclass 24, count 2 2006.183.08:26:42.05#ibcon#about to read 3, iclass 24, count 2 2006.183.08:26:42.08#ibcon#read 3, iclass 24, count 2 2006.183.08:26:42.08#ibcon#about to read 4, iclass 24, count 2 2006.183.08:26:42.08#ibcon#read 4, iclass 24, count 2 2006.183.08:26:42.08#ibcon#about to read 5, iclass 24, count 2 2006.183.08:26:42.08#ibcon#read 5, iclass 24, count 2 2006.183.08:26:42.08#ibcon#about to read 6, iclass 24, count 2 2006.183.08:26:42.08#ibcon#read 6, iclass 24, count 2 2006.183.08:26:42.08#ibcon#end of sib2, iclass 24, count 2 2006.183.08:26:42.08#ibcon#*after write, iclass 24, count 2 2006.183.08:26:42.08#ibcon#*before return 0, iclass 24, count 2 2006.183.08:26:42.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:42.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.183.08:26:42.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.183.08:26:42.08#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:42.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:42.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:42.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:42.20#ibcon#enter wrdev, iclass 24, count 0 2006.183.08:26:42.20#ibcon#first serial, iclass 24, count 0 2006.183.08:26:42.20#ibcon#enter sib2, iclass 24, count 0 2006.183.08:26:42.20#ibcon#flushed, iclass 24, count 0 2006.183.08:26:42.20#ibcon#about to write, iclass 24, count 0 2006.183.08:26:42.20#ibcon#wrote, iclass 24, count 0 2006.183.08:26:42.20#ibcon#about to read 3, iclass 24, count 0 2006.183.08:26:42.24#ibcon#read 3, iclass 24, count 0 2006.183.08:26:42.24#ibcon#about to read 4, iclass 24, count 0 2006.183.08:26:42.24#ibcon#read 4, iclass 24, count 0 2006.183.08:26:42.24#ibcon#about to read 5, iclass 24, count 0 2006.183.08:26:42.24#ibcon#read 5, iclass 24, count 0 2006.183.08:26:42.24#ibcon#about to read 6, iclass 24, count 0 2006.183.08:26:42.24#ibcon#read 6, iclass 24, count 0 2006.183.08:26:42.24#ibcon#end of sib2, iclass 24, count 0 2006.183.08:26:42.24#ibcon#*mode == 0, iclass 24, count 0 2006.183.08:26:42.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.183.08:26:42.24#ibcon#[27=USB\r\n] 2006.183.08:26:42.24#ibcon#*before write, iclass 24, count 0 2006.183.08:26:42.24#ibcon#enter sib2, iclass 24, count 0 2006.183.08:26:42.24#ibcon#flushed, iclass 24, count 0 2006.183.08:26:42.24#ibcon#about to write, iclass 24, count 0 2006.183.08:26:42.24#ibcon#wrote, iclass 24, count 0 2006.183.08:26:42.24#ibcon#about to read 3, iclass 24, count 0 2006.183.08:26:42.26#ibcon#read 3, iclass 24, count 0 2006.183.08:26:42.26#ibcon#about to read 4, iclass 24, count 0 2006.183.08:26:42.26#ibcon#read 4, iclass 24, count 0 2006.183.08:26:42.26#ibcon#about to read 5, iclass 24, count 0 2006.183.08:26:42.26#ibcon#read 5, iclass 24, count 0 2006.183.08:26:42.26#ibcon#about to read 6, iclass 24, count 0 2006.183.08:26:42.26#ibcon#read 6, iclass 24, count 0 2006.183.08:26:42.26#ibcon#end of sib2, iclass 24, count 0 2006.183.08:26:42.26#ibcon#*after write, iclass 24, count 0 2006.183.08:26:42.26#ibcon#*before return 0, iclass 24, count 0 2006.183.08:26:42.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:42.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.183.08:26:42.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.183.08:26:42.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.183.08:26:42.26$vc4f8/vblo=6,752.99 2006.183.08:26:42.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.183.08:26:42.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.183.08:26:42.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:26:42.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:42.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:42.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:42.26#ibcon#enter wrdev, iclass 26, count 0 2006.183.08:26:42.26#ibcon#first serial, iclass 26, count 0 2006.183.08:26:42.26#ibcon#enter sib2, iclass 26, count 0 2006.183.08:26:42.26#ibcon#flushed, iclass 26, count 0 2006.183.08:26:42.26#ibcon#about to write, iclass 26, count 0 2006.183.08:26:42.26#ibcon#wrote, iclass 26, count 0 2006.183.08:26:42.26#ibcon#about to read 3, iclass 26, count 0 2006.183.08:26:42.28#ibcon#read 3, iclass 26, count 0 2006.183.08:26:42.28#ibcon#about to read 4, iclass 26, count 0 2006.183.08:26:42.28#ibcon#read 4, iclass 26, count 0 2006.183.08:26:42.28#ibcon#about to read 5, iclass 26, count 0 2006.183.08:26:42.28#ibcon#read 5, iclass 26, count 0 2006.183.08:26:42.28#ibcon#about to read 6, iclass 26, count 0 2006.183.08:26:42.28#ibcon#read 6, iclass 26, count 0 2006.183.08:26:42.28#ibcon#end of sib2, iclass 26, count 0 2006.183.08:26:42.28#ibcon#*mode == 0, iclass 26, count 0 2006.183.08:26:42.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.183.08:26:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:26:42.28#ibcon#*before write, iclass 26, count 0 2006.183.08:26:42.28#ibcon#enter sib2, iclass 26, count 0 2006.183.08:26:42.28#ibcon#flushed, iclass 26, count 0 2006.183.08:26:42.28#ibcon#about to write, iclass 26, count 0 2006.183.08:26:42.28#ibcon#wrote, iclass 26, count 0 2006.183.08:26:42.28#ibcon#about to read 3, iclass 26, count 0 2006.183.08:26:42.32#ibcon#read 3, iclass 26, count 0 2006.183.08:26:42.32#ibcon#about to read 4, iclass 26, count 0 2006.183.08:26:42.32#ibcon#read 4, iclass 26, count 0 2006.183.08:26:42.32#ibcon#about to read 5, iclass 26, count 0 2006.183.08:26:42.32#ibcon#read 5, iclass 26, count 0 2006.183.08:26:42.32#ibcon#about to read 6, iclass 26, count 0 2006.183.08:26:42.32#ibcon#read 6, iclass 26, count 0 2006.183.08:26:42.32#ibcon#end of sib2, iclass 26, count 0 2006.183.08:26:42.32#ibcon#*after write, iclass 26, count 0 2006.183.08:26:42.32#ibcon#*before return 0, iclass 26, count 0 2006.183.08:26:42.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:42.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.183.08:26:42.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.183.08:26:42.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.183.08:26:42.32$vc4f8/vb=6,4 2006.183.08:26:42.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.183.08:26:42.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.183.08:26:42.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:26:42.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:42.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:42.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:42.38#ibcon#enter wrdev, iclass 28, count 2 2006.183.08:26:42.38#ibcon#first serial, iclass 28, count 2 2006.183.08:26:42.38#ibcon#enter sib2, iclass 28, count 2 2006.183.08:26:42.38#ibcon#flushed, iclass 28, count 2 2006.183.08:26:42.38#ibcon#about to write, iclass 28, count 2 2006.183.08:26:42.38#ibcon#wrote, iclass 28, count 2 2006.183.08:26:42.38#ibcon#about to read 3, iclass 28, count 2 2006.183.08:26:42.40#ibcon#read 3, iclass 28, count 2 2006.183.08:26:42.40#ibcon#about to read 4, iclass 28, count 2 2006.183.08:26:42.40#ibcon#read 4, iclass 28, count 2 2006.183.08:26:42.40#ibcon#about to read 5, iclass 28, count 2 2006.183.08:26:42.40#ibcon#read 5, iclass 28, count 2 2006.183.08:26:42.40#ibcon#about to read 6, iclass 28, count 2 2006.183.08:26:42.40#ibcon#read 6, iclass 28, count 2 2006.183.08:26:42.40#ibcon#end of sib2, iclass 28, count 2 2006.183.08:26:42.40#ibcon#*mode == 0, iclass 28, count 2 2006.183.08:26:42.40#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.183.08:26:42.40#ibcon#[27=AT06-04\r\n] 2006.183.08:26:42.40#ibcon#*before write, iclass 28, count 2 2006.183.08:26:42.40#ibcon#enter sib2, iclass 28, count 2 2006.183.08:26:42.40#ibcon#flushed, iclass 28, count 2 2006.183.08:26:42.40#ibcon#about to write, iclass 28, count 2 2006.183.08:26:42.40#ibcon#wrote, iclass 28, count 2 2006.183.08:26:42.40#ibcon#about to read 3, iclass 28, count 2 2006.183.08:26:42.43#ibcon#read 3, iclass 28, count 2 2006.183.08:26:42.43#ibcon#about to read 4, iclass 28, count 2 2006.183.08:26:42.43#ibcon#read 4, iclass 28, count 2 2006.183.08:26:42.43#ibcon#about to read 5, iclass 28, count 2 2006.183.08:26:42.43#ibcon#read 5, iclass 28, count 2 2006.183.08:26:42.43#ibcon#about to read 6, iclass 28, count 2 2006.183.08:26:42.43#ibcon#read 6, iclass 28, count 2 2006.183.08:26:42.43#ibcon#end of sib2, iclass 28, count 2 2006.183.08:26:42.43#ibcon#*after write, iclass 28, count 2 2006.183.08:26:42.43#ibcon#*before return 0, iclass 28, count 2 2006.183.08:26:42.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:42.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.183.08:26:42.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.183.08:26:42.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:26:42.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:42.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:42.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:42.55#ibcon#enter wrdev, iclass 28, count 0 2006.183.08:26:42.55#ibcon#first serial, iclass 28, count 0 2006.183.08:26:42.55#ibcon#enter sib2, iclass 28, count 0 2006.183.08:26:42.55#ibcon#flushed, iclass 28, count 0 2006.183.08:26:42.55#ibcon#about to write, iclass 28, count 0 2006.183.08:26:42.55#ibcon#wrote, iclass 28, count 0 2006.183.08:26:42.55#ibcon#about to read 3, iclass 28, count 0 2006.183.08:26:42.57#ibcon#read 3, iclass 28, count 0 2006.183.08:26:42.57#ibcon#about to read 4, iclass 28, count 0 2006.183.08:26:42.57#ibcon#read 4, iclass 28, count 0 2006.183.08:26:42.57#ibcon#about to read 5, iclass 28, count 0 2006.183.08:26:42.57#ibcon#read 5, iclass 28, count 0 2006.183.08:26:42.57#ibcon#about to read 6, iclass 28, count 0 2006.183.08:26:42.57#ibcon#read 6, iclass 28, count 0 2006.183.08:26:42.57#ibcon#end of sib2, iclass 28, count 0 2006.183.08:26:42.57#ibcon#*mode == 0, iclass 28, count 0 2006.183.08:26:42.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.183.08:26:42.57#ibcon#[27=USB\r\n] 2006.183.08:26:42.57#ibcon#*before write, iclass 28, count 0 2006.183.08:26:42.57#ibcon#enter sib2, iclass 28, count 0 2006.183.08:26:42.57#ibcon#flushed, iclass 28, count 0 2006.183.08:26:42.57#ibcon#about to write, iclass 28, count 0 2006.183.08:26:42.57#ibcon#wrote, iclass 28, count 0 2006.183.08:26:42.57#ibcon#about to read 3, iclass 28, count 0 2006.183.08:26:42.60#ibcon#read 3, iclass 28, count 0 2006.183.08:26:42.60#ibcon#about to read 4, iclass 28, count 0 2006.183.08:26:42.60#ibcon#read 4, iclass 28, count 0 2006.183.08:26:42.60#ibcon#about to read 5, iclass 28, count 0 2006.183.08:26:42.60#ibcon#read 5, iclass 28, count 0 2006.183.08:26:42.60#ibcon#about to read 6, iclass 28, count 0 2006.183.08:26:42.60#ibcon#read 6, iclass 28, count 0 2006.183.08:26:42.60#ibcon#end of sib2, iclass 28, count 0 2006.183.08:26:42.60#ibcon#*after write, iclass 28, count 0 2006.183.08:26:42.60#ibcon#*before return 0, iclass 28, count 0 2006.183.08:26:42.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:42.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.183.08:26:42.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.183.08:26:42.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.183.08:26:42.60$vc4f8/vabw=wide 2006.183.08:26:42.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.183.08:26:42.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.183.08:26:42.60#ibcon#ireg 8 cls_cnt 0 2006.183.08:26:42.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:42.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:42.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:42.60#ibcon#enter wrdev, iclass 30, count 0 2006.183.08:26:42.60#ibcon#first serial, iclass 30, count 0 2006.183.08:26:42.60#ibcon#enter sib2, iclass 30, count 0 2006.183.08:26:42.60#ibcon#flushed, iclass 30, count 0 2006.183.08:26:42.60#ibcon#about to write, iclass 30, count 0 2006.183.08:26:42.60#ibcon#wrote, iclass 30, count 0 2006.183.08:26:42.60#ibcon#about to read 3, iclass 30, count 0 2006.183.08:26:42.62#ibcon#read 3, iclass 30, count 0 2006.183.08:26:42.62#ibcon#about to read 4, iclass 30, count 0 2006.183.08:26:42.62#ibcon#read 4, iclass 30, count 0 2006.183.08:26:42.62#ibcon#about to read 5, iclass 30, count 0 2006.183.08:26:42.62#ibcon#read 5, iclass 30, count 0 2006.183.08:26:42.62#ibcon#about to read 6, iclass 30, count 0 2006.183.08:26:42.62#ibcon#read 6, iclass 30, count 0 2006.183.08:26:42.62#ibcon#end of sib2, iclass 30, count 0 2006.183.08:26:42.62#ibcon#*mode == 0, iclass 30, count 0 2006.183.08:26:42.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.183.08:26:42.62#ibcon#[25=BW32\r\n] 2006.183.08:26:42.62#ibcon#*before write, iclass 30, count 0 2006.183.08:26:42.62#ibcon#enter sib2, iclass 30, count 0 2006.183.08:26:42.62#ibcon#flushed, iclass 30, count 0 2006.183.08:26:42.62#ibcon#about to write, iclass 30, count 0 2006.183.08:26:42.62#ibcon#wrote, iclass 30, count 0 2006.183.08:26:42.62#ibcon#about to read 3, iclass 30, count 0 2006.183.08:26:42.65#ibcon#read 3, iclass 30, count 0 2006.183.08:26:42.65#ibcon#about to read 4, iclass 30, count 0 2006.183.08:26:42.65#ibcon#read 4, iclass 30, count 0 2006.183.08:26:42.65#ibcon#about to read 5, iclass 30, count 0 2006.183.08:26:42.65#ibcon#read 5, iclass 30, count 0 2006.183.08:26:42.65#ibcon#about to read 6, iclass 30, count 0 2006.183.08:26:42.65#ibcon#read 6, iclass 30, count 0 2006.183.08:26:42.65#ibcon#end of sib2, iclass 30, count 0 2006.183.08:26:42.65#ibcon#*after write, iclass 30, count 0 2006.183.08:26:42.65#ibcon#*before return 0, iclass 30, count 0 2006.183.08:26:42.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:42.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.183.08:26:42.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.183.08:26:42.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.183.08:26:42.65$vc4f8/vbbw=wide 2006.183.08:26:42.65#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.183.08:26:42.65#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.183.08:26:42.65#ibcon#ireg 8 cls_cnt 0 2006.183.08:26:42.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:26:42.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:26:42.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:26:42.72#ibcon#enter wrdev, iclass 32, count 0 2006.183.08:26:42.72#ibcon#first serial, iclass 32, count 0 2006.183.08:26:42.72#ibcon#enter sib2, iclass 32, count 0 2006.183.08:26:42.72#ibcon#flushed, iclass 32, count 0 2006.183.08:26:42.72#ibcon#about to write, iclass 32, count 0 2006.183.08:26:42.72#ibcon#wrote, iclass 32, count 0 2006.183.08:26:42.72#ibcon#about to read 3, iclass 32, count 0 2006.183.08:26:42.74#ibcon#read 3, iclass 32, count 0 2006.183.08:26:42.74#ibcon#about to read 4, iclass 32, count 0 2006.183.08:26:42.74#ibcon#read 4, iclass 32, count 0 2006.183.08:26:42.74#ibcon#about to read 5, iclass 32, count 0 2006.183.08:26:42.74#ibcon#read 5, iclass 32, count 0 2006.183.08:26:42.74#ibcon#about to read 6, iclass 32, count 0 2006.183.08:26:42.74#ibcon#read 6, iclass 32, count 0 2006.183.08:26:42.74#ibcon#end of sib2, iclass 32, count 0 2006.183.08:26:42.74#ibcon#*mode == 0, iclass 32, count 0 2006.183.08:26:42.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.183.08:26:42.74#ibcon#[27=BW32\r\n] 2006.183.08:26:42.74#ibcon#*before write, iclass 32, count 0 2006.183.08:26:42.74#ibcon#enter sib2, iclass 32, count 0 2006.183.08:26:42.74#ibcon#flushed, iclass 32, count 0 2006.183.08:26:42.74#ibcon#about to write, iclass 32, count 0 2006.183.08:26:42.74#ibcon#wrote, iclass 32, count 0 2006.183.08:26:42.74#ibcon#about to read 3, iclass 32, count 0 2006.183.08:26:42.77#ibcon#read 3, iclass 32, count 0 2006.183.08:26:42.77#ibcon#about to read 4, iclass 32, count 0 2006.183.08:26:42.77#ibcon#read 4, iclass 32, count 0 2006.183.08:26:42.77#ibcon#about to read 5, iclass 32, count 0 2006.183.08:26:42.77#ibcon#read 5, iclass 32, count 0 2006.183.08:26:42.77#ibcon#about to read 6, iclass 32, count 0 2006.183.08:26:42.77#ibcon#read 6, iclass 32, count 0 2006.183.08:26:42.77#ibcon#end of sib2, iclass 32, count 0 2006.183.08:26:42.77#ibcon#*after write, iclass 32, count 0 2006.183.08:26:42.77#ibcon#*before return 0, iclass 32, count 0 2006.183.08:26:42.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:26:42.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.183.08:26:42.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.183.08:26:42.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.183.08:26:42.77$4f8m12a/ifd4f 2006.183.08:26:42.77$ifd4f/lo= 2006.183.08:26:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:26:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:26:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:26:42.77$ifd4f/patch= 2006.183.08:26:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:26:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:26:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:26:42.77$4f8m12a/"form=m,16.000,1:2 2006.183.08:26:42.77$4f8m12a/"tpicd 2006.183.08:26:42.77$4f8m12a/echo=off 2006.183.08:26:42.77$4f8m12a/xlog=off 2006.183.08:26:42.77:!2006.183.08:27:10 2006.183.08:26:52.14#trakl#Source acquired 2006.183.08:26:52.14#flagr#flagr/antenna,acquired 2006.183.08:27:10.00:preob 2006.183.08:27:11.14/onsource/TRACKING 2006.183.08:27:11.14:!2006.183.08:27:20 2006.183.08:27:20.00:data_valid=on 2006.183.08:27:20.00:midob 2006.183.08:27:20.14/onsource/TRACKING 2006.183.08:27:20.14/wx/28.24,996.7,87 2006.183.08:27:20.32/cable/+6.4488E-03 2006.183.08:27:21.41/va/01,08,usb,yes,34,36 2006.183.08:27:21.41/va/02,07,usb,yes,34,36 2006.183.08:27:21.41/va/03,06,usb,yes,36,37 2006.183.08:27:21.41/va/04,07,usb,yes,35,38 2006.183.08:27:21.41/va/05,07,usb,yes,38,40 2006.183.08:27:21.41/va/06,06,usb,yes,37,37 2006.183.08:27:21.41/va/07,06,usb,yes,37,37 2006.183.08:27:21.41/va/08,07,usb,yes,36,35 2006.183.08:27:21.64/valo/01,532.99,yes,locked 2006.183.08:27:21.64/valo/02,572.99,yes,locked 2006.183.08:27:21.64/valo/03,672.99,yes,locked 2006.183.08:27:21.64/valo/04,832.99,yes,locked 2006.183.08:27:21.64/valo/05,652.99,yes,locked 2006.183.08:27:21.64/valo/06,772.99,yes,locked 2006.183.08:27:21.64/valo/07,832.99,yes,locked 2006.183.08:27:21.64/valo/08,852.99,yes,locked 2006.183.08:27:22.73/vb/01,04,usb,yes,32,31 2006.183.08:27:22.73/vb/02,04,usb,yes,34,36 2006.183.08:27:22.73/vb/03,04,usb,yes,30,34 2006.183.08:27:22.73/vb/04,04,usb,yes,32,32 2006.183.08:27:22.73/vb/05,04,usb,yes,30,34 2006.183.08:27:22.73/vb/06,04,usb,yes,31,34 2006.183.08:27:22.73/vb/07,04,usb,yes,33,34 2006.183.08:27:22.73/vb/08,04,usb,yes,30,34 2006.183.08:27:22.97/vblo/01,632.99,yes,locked 2006.183.08:27:22.97/vblo/02,640.99,yes,locked 2006.183.08:27:22.97/vblo/03,656.99,yes,locked 2006.183.08:27:22.97/vblo/04,712.99,yes,locked 2006.183.08:27:22.97/vblo/05,744.99,yes,locked 2006.183.08:27:22.97/vblo/06,752.99,yes,locked 2006.183.08:27:22.97/vblo/07,734.99,yes,locked 2006.183.08:27:22.97/vblo/08,744.99,yes,locked 2006.183.08:27:23.12/vabw/8 2006.183.08:27:23.27/vbbw/8 2006.183.08:27:23.38/xfe/off,on,14.5 2006.183.08:27:23.75/ifatt/23,28,28,28 2006.183.08:27:24.08/fmout-gps/S +3.35E-07 2006.183.08:27:24.16:!2006.183.08:28:20 2006.183.08:28:20.00:data_valid=off 2006.183.08:28:20.00:postob 2006.183.08:28:20.09/cable/+6.4493E-03 2006.183.08:28:20.09/wx/28.23,996.8,87 2006.183.08:28:21.07/fmout-gps/S +3.35E-07 2006.183.08:28:21.07:scan_name=183-0829,k06183,60 2006.183.08:28:21.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.183.08:28:21.14#flagr#flagr/antenna,new-source 2006.183.08:28:22.14:checkk5 2006.183.08:28:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.183.08:28:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.183.08:28:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.183.08:28:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.183.08:28:24.01/chk_obsdata//k5ts1/T1830827??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:28:24.39/chk_obsdata//k5ts2/T1830827??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:28:24.75/chk_obsdata//k5ts3/T1830827??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:28:25.14/chk_obsdata//k5ts4/T1830827??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.183.08:28:25.84/k5log//k5ts1_log_newline 2006.183.08:28:26.54/k5log//k5ts2_log_newline 2006.183.08:28:27.22/k5log//k5ts3_log_newline 2006.183.08:28:27.91/k5log//k5ts4_log_newline 2006.183.08:28:27.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:28:27.94:4f8m12a=3 2006.183.08:28:27.94$4f8m12a/echo=on 2006.183.08:28:27.94$4f8m12a/pcalon 2006.183.08:28:27.94$pcalon/"no phase cal control is implemented here 2006.183.08:28:27.94$4f8m12a/"tpicd=stop 2006.183.08:28:27.94$4f8m12a/vc4f8 2006.183.08:28:27.94$vc4f8/valo=1,532.99 2006.183.08:28:27.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.08:28:27.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.08:28:27.94#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:27.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:27.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:27.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:27.94#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:28:27.94#ibcon#first serial, iclass 5, count 0 2006.183.08:28:27.94#ibcon#enter sib2, iclass 5, count 0 2006.183.08:28:27.94#ibcon#flushed, iclass 5, count 0 2006.183.08:28:27.94#ibcon#about to write, iclass 5, count 0 2006.183.08:28:27.94#ibcon#wrote, iclass 5, count 0 2006.183.08:28:27.94#ibcon#about to read 3, iclass 5, count 0 2006.183.08:28:27.98#ibcon#read 3, iclass 5, count 0 2006.183.08:28:27.98#ibcon#about to read 4, iclass 5, count 0 2006.183.08:28:27.98#ibcon#read 4, iclass 5, count 0 2006.183.08:28:27.98#ibcon#about to read 5, iclass 5, count 0 2006.183.08:28:27.98#ibcon#read 5, iclass 5, count 0 2006.183.08:28:27.98#ibcon#about to read 6, iclass 5, count 0 2006.183.08:28:27.98#ibcon#read 6, iclass 5, count 0 2006.183.08:28:27.98#ibcon#end of sib2, iclass 5, count 0 2006.183.08:28:27.98#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:28:27.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:28:27.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.183.08:28:27.98#ibcon#*before write, iclass 5, count 0 2006.183.08:28:27.98#ibcon#enter sib2, iclass 5, count 0 2006.183.08:28:27.98#ibcon#flushed, iclass 5, count 0 2006.183.08:28:27.98#ibcon#about to write, iclass 5, count 0 2006.183.08:28:27.98#ibcon#wrote, iclass 5, count 0 2006.183.08:28:27.98#ibcon#about to read 3, iclass 5, count 0 2006.183.08:28:28.03#ibcon#read 3, iclass 5, count 0 2006.183.08:28:28.03#ibcon#about to read 4, iclass 5, count 0 2006.183.08:28:28.03#ibcon#read 4, iclass 5, count 0 2006.183.08:28:28.03#ibcon#about to read 5, iclass 5, count 0 2006.183.08:28:28.03#ibcon#read 5, iclass 5, count 0 2006.183.08:28:28.03#ibcon#about to read 6, iclass 5, count 0 2006.183.08:28:28.03#ibcon#read 6, iclass 5, count 0 2006.183.08:28:28.03#ibcon#end of sib2, iclass 5, count 0 2006.183.08:28:28.03#ibcon#*after write, iclass 5, count 0 2006.183.08:28:28.03#ibcon#*before return 0, iclass 5, count 0 2006.183.08:28:28.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:28.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:28.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:28:28.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:28:28.03$vc4f8/va=1,8 2006.183.08:28:28.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.08:28:28.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.08:28:28.03#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:28.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:28.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:28.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:28.03#ibcon#enter wrdev, iclass 7, count 2 2006.183.08:28:28.03#ibcon#first serial, iclass 7, count 2 2006.183.08:28:28.03#ibcon#enter sib2, iclass 7, count 2 2006.183.08:28:28.03#ibcon#flushed, iclass 7, count 2 2006.183.08:28:28.03#ibcon#about to write, iclass 7, count 2 2006.183.08:28:28.03#ibcon#wrote, iclass 7, count 2 2006.183.08:28:28.03#ibcon#about to read 3, iclass 7, count 2 2006.183.08:28:28.06#ibcon#read 3, iclass 7, count 2 2006.183.08:28:28.06#ibcon#about to read 4, iclass 7, count 2 2006.183.08:28:28.06#ibcon#read 4, iclass 7, count 2 2006.183.08:28:28.06#ibcon#about to read 5, iclass 7, count 2 2006.183.08:28:28.06#ibcon#read 5, iclass 7, count 2 2006.183.08:28:28.06#ibcon#about to read 6, iclass 7, count 2 2006.183.08:28:28.06#ibcon#read 6, iclass 7, count 2 2006.183.08:28:28.06#ibcon#end of sib2, iclass 7, count 2 2006.183.08:28:28.06#ibcon#*mode == 0, iclass 7, count 2 2006.183.08:28:28.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.08:28:28.06#ibcon#[25=AT01-08\r\n] 2006.183.08:28:28.06#ibcon#*before write, iclass 7, count 2 2006.183.08:28:28.06#ibcon#enter sib2, iclass 7, count 2 2006.183.08:28:28.06#ibcon#flushed, iclass 7, count 2 2006.183.08:28:28.06#ibcon#about to write, iclass 7, count 2 2006.183.08:28:28.06#ibcon#wrote, iclass 7, count 2 2006.183.08:28:28.06#ibcon#about to read 3, iclass 7, count 2 2006.183.08:28:28.09#ibcon#read 3, iclass 7, count 2 2006.183.08:28:28.09#ibcon#about to read 4, iclass 7, count 2 2006.183.08:28:28.09#ibcon#read 4, iclass 7, count 2 2006.183.08:28:28.09#ibcon#about to read 5, iclass 7, count 2 2006.183.08:28:28.09#ibcon#read 5, iclass 7, count 2 2006.183.08:28:28.09#ibcon#about to read 6, iclass 7, count 2 2006.183.08:28:28.09#ibcon#read 6, iclass 7, count 2 2006.183.08:28:28.09#ibcon#end of sib2, iclass 7, count 2 2006.183.08:28:28.09#ibcon#*after write, iclass 7, count 2 2006.183.08:28:28.09#ibcon#*before return 0, iclass 7, count 2 2006.183.08:28:28.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:28.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:28.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.08:28:28.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:28.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:28.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:28.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:28.21#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:28:28.21#ibcon#first serial, iclass 7, count 0 2006.183.08:28:28.21#ibcon#enter sib2, iclass 7, count 0 2006.183.08:28:28.21#ibcon#flushed, iclass 7, count 0 2006.183.08:28:28.21#ibcon#about to write, iclass 7, count 0 2006.183.08:28:28.21#ibcon#wrote, iclass 7, count 0 2006.183.08:28:28.21#ibcon#about to read 3, iclass 7, count 0 2006.183.08:28:28.23#ibcon#read 3, iclass 7, count 0 2006.183.08:28:28.23#ibcon#about to read 4, iclass 7, count 0 2006.183.08:28:28.23#ibcon#read 4, iclass 7, count 0 2006.183.08:28:28.23#ibcon#about to read 5, iclass 7, count 0 2006.183.08:28:28.23#ibcon#read 5, iclass 7, count 0 2006.183.08:28:28.23#ibcon#about to read 6, iclass 7, count 0 2006.183.08:28:28.23#ibcon#read 6, iclass 7, count 0 2006.183.08:28:28.23#ibcon#end of sib2, iclass 7, count 0 2006.183.08:28:28.23#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:28:28.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:28:28.23#ibcon#[25=USB\r\n] 2006.183.08:28:28.23#ibcon#*before write, iclass 7, count 0 2006.183.08:28:28.23#ibcon#enter sib2, iclass 7, count 0 2006.183.08:28:28.23#ibcon#flushed, iclass 7, count 0 2006.183.08:28:28.23#ibcon#about to write, iclass 7, count 0 2006.183.08:28:28.23#ibcon#wrote, iclass 7, count 0 2006.183.08:28:28.23#ibcon#about to read 3, iclass 7, count 0 2006.183.08:28:28.26#ibcon#read 3, iclass 7, count 0 2006.183.08:28:28.26#ibcon#about to read 4, iclass 7, count 0 2006.183.08:28:28.26#ibcon#read 4, iclass 7, count 0 2006.183.08:28:28.26#ibcon#about to read 5, iclass 7, count 0 2006.183.08:28:28.26#ibcon#read 5, iclass 7, count 0 2006.183.08:28:28.26#ibcon#about to read 6, iclass 7, count 0 2006.183.08:28:28.26#ibcon#read 6, iclass 7, count 0 2006.183.08:28:28.26#ibcon#end of sib2, iclass 7, count 0 2006.183.08:28:28.26#ibcon#*after write, iclass 7, count 0 2006.183.08:28:28.26#ibcon#*before return 0, iclass 7, count 0 2006.183.08:28:28.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:28.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:28.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:28:28.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:28:28.26$vc4f8/valo=2,572.99 2006.183.08:28:28.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:28:28.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:28:28.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:28.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:28.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:28.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:28.26#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:28:28.26#ibcon#first serial, iclass 11, count 0 2006.183.08:28:28.26#ibcon#enter sib2, iclass 11, count 0 2006.183.08:28:28.26#ibcon#flushed, iclass 11, count 0 2006.183.08:28:28.26#ibcon#about to write, iclass 11, count 0 2006.183.08:28:28.26#ibcon#wrote, iclass 11, count 0 2006.183.08:28:28.26#ibcon#about to read 3, iclass 11, count 0 2006.183.08:28:28.28#ibcon#read 3, iclass 11, count 0 2006.183.08:28:28.28#ibcon#about to read 4, iclass 11, count 0 2006.183.08:28:28.28#ibcon#read 4, iclass 11, count 0 2006.183.08:28:28.28#ibcon#about to read 5, iclass 11, count 0 2006.183.08:28:28.28#ibcon#read 5, iclass 11, count 0 2006.183.08:28:28.28#ibcon#about to read 6, iclass 11, count 0 2006.183.08:28:28.28#ibcon#read 6, iclass 11, count 0 2006.183.08:28:28.28#ibcon#end of sib2, iclass 11, count 0 2006.183.08:28:28.28#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:28:28.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:28:28.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.183.08:28:28.28#ibcon#*before write, iclass 11, count 0 2006.183.08:28:28.28#ibcon#enter sib2, iclass 11, count 0 2006.183.08:28:28.28#ibcon#flushed, iclass 11, count 0 2006.183.08:28:28.28#ibcon#about to write, iclass 11, count 0 2006.183.08:28:28.28#ibcon#wrote, iclass 11, count 0 2006.183.08:28:28.28#ibcon#about to read 3, iclass 11, count 0 2006.183.08:28:28.32#ibcon#read 3, iclass 11, count 0 2006.183.08:28:28.32#ibcon#about to read 4, iclass 11, count 0 2006.183.08:28:28.32#ibcon#read 4, iclass 11, count 0 2006.183.08:28:28.32#ibcon#about to read 5, iclass 11, count 0 2006.183.08:28:28.32#ibcon#read 5, iclass 11, count 0 2006.183.08:28:28.32#ibcon#about to read 6, iclass 11, count 0 2006.183.08:28:28.32#ibcon#read 6, iclass 11, count 0 2006.183.08:28:28.32#ibcon#end of sib2, iclass 11, count 0 2006.183.08:28:28.32#ibcon#*after write, iclass 11, count 0 2006.183.08:28:28.32#ibcon#*before return 0, iclass 11, count 0 2006.183.08:28:28.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:28.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:28.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:28:28.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:28:28.32$vc4f8/va=2,7 2006.183.08:28:28.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.08:28:28.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.08:28:28.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:28.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:28.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:28.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:28.38#ibcon#enter wrdev, iclass 13, count 2 2006.183.08:28:28.38#ibcon#first serial, iclass 13, count 2 2006.183.08:28:28.38#ibcon#enter sib2, iclass 13, count 2 2006.183.08:28:28.38#ibcon#flushed, iclass 13, count 2 2006.183.08:28:28.38#ibcon#about to write, iclass 13, count 2 2006.183.08:28:28.38#ibcon#wrote, iclass 13, count 2 2006.183.08:28:28.38#ibcon#about to read 3, iclass 13, count 2 2006.183.08:28:28.40#ibcon#read 3, iclass 13, count 2 2006.183.08:28:28.40#ibcon#about to read 4, iclass 13, count 2 2006.183.08:28:28.40#ibcon#read 4, iclass 13, count 2 2006.183.08:28:28.40#ibcon#about to read 5, iclass 13, count 2 2006.183.08:28:28.40#ibcon#read 5, iclass 13, count 2 2006.183.08:28:28.40#ibcon#about to read 6, iclass 13, count 2 2006.183.08:28:28.40#ibcon#read 6, iclass 13, count 2 2006.183.08:28:28.40#ibcon#end of sib2, iclass 13, count 2 2006.183.08:28:28.40#ibcon#*mode == 0, iclass 13, count 2 2006.183.08:28:28.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.08:28:28.40#ibcon#[25=AT02-07\r\n] 2006.183.08:28:28.40#ibcon#*before write, iclass 13, count 2 2006.183.08:28:28.40#ibcon#enter sib2, iclass 13, count 2 2006.183.08:28:28.40#ibcon#flushed, iclass 13, count 2 2006.183.08:28:28.40#ibcon#about to write, iclass 13, count 2 2006.183.08:28:28.40#ibcon#wrote, iclass 13, count 2 2006.183.08:28:28.40#ibcon#about to read 3, iclass 13, count 2 2006.183.08:28:28.43#ibcon#read 3, iclass 13, count 2 2006.183.08:28:28.43#ibcon#about to read 4, iclass 13, count 2 2006.183.08:28:28.43#ibcon#read 4, iclass 13, count 2 2006.183.08:28:28.43#ibcon#about to read 5, iclass 13, count 2 2006.183.08:28:28.43#ibcon#read 5, iclass 13, count 2 2006.183.08:28:28.43#ibcon#about to read 6, iclass 13, count 2 2006.183.08:28:28.43#ibcon#read 6, iclass 13, count 2 2006.183.08:28:28.43#ibcon#end of sib2, iclass 13, count 2 2006.183.08:28:28.43#ibcon#*after write, iclass 13, count 2 2006.183.08:28:28.43#ibcon#*before return 0, iclass 13, count 2 2006.183.08:28:28.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:28.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:28.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.08:28:28.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:28.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:28.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:28.56#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:28.56#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:28:28.56#ibcon#first serial, iclass 13, count 0 2006.183.08:28:28.56#ibcon#enter sib2, iclass 13, count 0 2006.183.08:28:28.56#ibcon#flushed, iclass 13, count 0 2006.183.08:28:28.56#ibcon#about to write, iclass 13, count 0 2006.183.08:28:28.56#ibcon#wrote, iclass 13, count 0 2006.183.08:28:28.56#ibcon#about to read 3, iclass 13, count 0 2006.183.08:28:28.57#ibcon#read 3, iclass 13, count 0 2006.183.08:28:28.57#ibcon#about to read 4, iclass 13, count 0 2006.183.08:28:28.57#ibcon#read 4, iclass 13, count 0 2006.183.08:28:28.57#ibcon#about to read 5, iclass 13, count 0 2006.183.08:28:28.57#ibcon#read 5, iclass 13, count 0 2006.183.08:28:28.57#ibcon#about to read 6, iclass 13, count 0 2006.183.08:28:28.57#ibcon#read 6, iclass 13, count 0 2006.183.08:28:28.57#ibcon#end of sib2, iclass 13, count 0 2006.183.08:28:28.57#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:28:28.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:28:28.57#ibcon#[25=USB\r\n] 2006.183.08:28:28.57#ibcon#*before write, iclass 13, count 0 2006.183.08:28:28.57#ibcon#enter sib2, iclass 13, count 0 2006.183.08:28:28.57#ibcon#flushed, iclass 13, count 0 2006.183.08:28:28.57#ibcon#about to write, iclass 13, count 0 2006.183.08:28:28.57#ibcon#wrote, iclass 13, count 0 2006.183.08:28:28.57#ibcon#about to read 3, iclass 13, count 0 2006.183.08:28:28.60#ibcon#read 3, iclass 13, count 0 2006.183.08:28:28.60#ibcon#about to read 4, iclass 13, count 0 2006.183.08:28:28.60#ibcon#read 4, iclass 13, count 0 2006.183.08:28:28.60#ibcon#about to read 5, iclass 13, count 0 2006.183.08:28:28.60#ibcon#read 5, iclass 13, count 0 2006.183.08:28:28.60#ibcon#about to read 6, iclass 13, count 0 2006.183.08:28:28.60#ibcon#read 6, iclass 13, count 0 2006.183.08:28:28.60#ibcon#end of sib2, iclass 13, count 0 2006.183.08:28:28.60#ibcon#*after write, iclass 13, count 0 2006.183.08:28:28.60#ibcon#*before return 0, iclass 13, count 0 2006.183.08:28:28.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:28.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:28.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:28:28.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:28:28.60$vc4f8/valo=3,672.99 2006.183.08:28:28.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.08:28:28.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.08:28:28.60#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:28.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:28.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:28.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:28.60#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:28:28.60#ibcon#first serial, iclass 15, count 0 2006.183.08:28:28.60#ibcon#enter sib2, iclass 15, count 0 2006.183.08:28:28.60#ibcon#flushed, iclass 15, count 0 2006.183.08:28:28.60#ibcon#about to write, iclass 15, count 0 2006.183.08:28:28.60#ibcon#wrote, iclass 15, count 0 2006.183.08:28:28.60#ibcon#about to read 3, iclass 15, count 0 2006.183.08:28:28.63#ibcon#read 3, iclass 15, count 0 2006.183.08:28:28.63#ibcon#about to read 4, iclass 15, count 0 2006.183.08:28:28.63#ibcon#read 4, iclass 15, count 0 2006.183.08:28:28.63#ibcon#about to read 5, iclass 15, count 0 2006.183.08:28:28.63#ibcon#read 5, iclass 15, count 0 2006.183.08:28:28.63#ibcon#about to read 6, iclass 15, count 0 2006.183.08:28:28.63#ibcon#read 6, iclass 15, count 0 2006.183.08:28:28.63#ibcon#end of sib2, iclass 15, count 0 2006.183.08:28:28.63#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:28:28.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:28:28.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.183.08:28:28.63#ibcon#*before write, iclass 15, count 0 2006.183.08:28:28.63#ibcon#enter sib2, iclass 15, count 0 2006.183.08:28:28.63#ibcon#flushed, iclass 15, count 0 2006.183.08:28:28.63#ibcon#about to write, iclass 15, count 0 2006.183.08:28:28.63#ibcon#wrote, iclass 15, count 0 2006.183.08:28:28.63#ibcon#about to read 3, iclass 15, count 0 2006.183.08:28:28.67#ibcon#read 3, iclass 15, count 0 2006.183.08:28:28.67#ibcon#about to read 4, iclass 15, count 0 2006.183.08:28:28.67#ibcon#read 4, iclass 15, count 0 2006.183.08:28:28.67#ibcon#about to read 5, iclass 15, count 0 2006.183.08:28:28.67#ibcon#read 5, iclass 15, count 0 2006.183.08:28:28.67#ibcon#about to read 6, iclass 15, count 0 2006.183.08:28:28.67#ibcon#read 6, iclass 15, count 0 2006.183.08:28:28.67#ibcon#end of sib2, iclass 15, count 0 2006.183.08:28:28.67#ibcon#*after write, iclass 15, count 0 2006.183.08:28:28.67#ibcon#*before return 0, iclass 15, count 0 2006.183.08:28:28.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:28.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:28.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:28:28.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:28:28.67$vc4f8/va=3,6 2006.183.08:28:28.67#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.08:28:28.67#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.08:28:28.67#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:28.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:28.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:28.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:28.72#ibcon#enter wrdev, iclass 17, count 2 2006.183.08:28:28.72#ibcon#first serial, iclass 17, count 2 2006.183.08:28:28.72#ibcon#enter sib2, iclass 17, count 2 2006.183.08:28:28.72#ibcon#flushed, iclass 17, count 2 2006.183.08:28:28.72#ibcon#about to write, iclass 17, count 2 2006.183.08:28:28.72#ibcon#wrote, iclass 17, count 2 2006.183.08:28:28.72#ibcon#about to read 3, iclass 17, count 2 2006.183.08:28:28.74#ibcon#read 3, iclass 17, count 2 2006.183.08:28:28.74#ibcon#about to read 4, iclass 17, count 2 2006.183.08:28:28.74#ibcon#read 4, iclass 17, count 2 2006.183.08:28:28.74#ibcon#about to read 5, iclass 17, count 2 2006.183.08:28:28.74#ibcon#read 5, iclass 17, count 2 2006.183.08:28:28.74#ibcon#about to read 6, iclass 17, count 2 2006.183.08:28:28.74#ibcon#read 6, iclass 17, count 2 2006.183.08:28:28.74#ibcon#end of sib2, iclass 17, count 2 2006.183.08:28:28.74#ibcon#*mode == 0, iclass 17, count 2 2006.183.08:28:28.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.08:28:28.74#ibcon#[25=AT03-06\r\n] 2006.183.08:28:28.74#ibcon#*before write, iclass 17, count 2 2006.183.08:28:28.74#ibcon#enter sib2, iclass 17, count 2 2006.183.08:28:28.74#ibcon#flushed, iclass 17, count 2 2006.183.08:28:28.74#ibcon#about to write, iclass 17, count 2 2006.183.08:28:28.74#ibcon#wrote, iclass 17, count 2 2006.183.08:28:28.74#ibcon#about to read 3, iclass 17, count 2 2006.183.08:28:28.77#ibcon#read 3, iclass 17, count 2 2006.183.08:28:28.77#ibcon#about to read 4, iclass 17, count 2 2006.183.08:28:28.77#ibcon#read 4, iclass 17, count 2 2006.183.08:28:28.77#ibcon#about to read 5, iclass 17, count 2 2006.183.08:28:28.77#ibcon#read 5, iclass 17, count 2 2006.183.08:28:28.77#ibcon#about to read 6, iclass 17, count 2 2006.183.08:28:28.77#ibcon#read 6, iclass 17, count 2 2006.183.08:28:28.77#ibcon#end of sib2, iclass 17, count 2 2006.183.08:28:28.77#ibcon#*after write, iclass 17, count 2 2006.183.08:28:28.77#ibcon#*before return 0, iclass 17, count 2 2006.183.08:28:28.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:28.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:28.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.08:28:28.77#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:28.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:28.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:28.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:28.89#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:28:28.89#ibcon#first serial, iclass 17, count 0 2006.183.08:28:28.89#ibcon#enter sib2, iclass 17, count 0 2006.183.08:28:28.89#ibcon#flushed, iclass 17, count 0 2006.183.08:28:28.89#ibcon#about to write, iclass 17, count 0 2006.183.08:28:28.89#ibcon#wrote, iclass 17, count 0 2006.183.08:28:28.89#ibcon#about to read 3, iclass 17, count 0 2006.183.08:28:28.91#ibcon#read 3, iclass 17, count 0 2006.183.08:28:28.91#ibcon#about to read 4, iclass 17, count 0 2006.183.08:28:28.91#ibcon#read 4, iclass 17, count 0 2006.183.08:28:28.91#ibcon#about to read 5, iclass 17, count 0 2006.183.08:28:28.91#ibcon#read 5, iclass 17, count 0 2006.183.08:28:28.91#ibcon#about to read 6, iclass 17, count 0 2006.183.08:28:28.91#ibcon#read 6, iclass 17, count 0 2006.183.08:28:28.91#ibcon#end of sib2, iclass 17, count 0 2006.183.08:28:28.91#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:28:28.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:28:28.91#ibcon#[25=USB\r\n] 2006.183.08:28:28.91#ibcon#*before write, iclass 17, count 0 2006.183.08:28:28.91#ibcon#enter sib2, iclass 17, count 0 2006.183.08:28:28.91#ibcon#flushed, iclass 17, count 0 2006.183.08:28:28.91#ibcon#about to write, iclass 17, count 0 2006.183.08:28:28.91#ibcon#wrote, iclass 17, count 0 2006.183.08:28:28.91#ibcon#about to read 3, iclass 17, count 0 2006.183.08:28:28.94#ibcon#read 3, iclass 17, count 0 2006.183.08:28:28.94#ibcon#about to read 4, iclass 17, count 0 2006.183.08:28:28.94#ibcon#read 4, iclass 17, count 0 2006.183.08:28:28.94#ibcon#about to read 5, iclass 17, count 0 2006.183.08:28:28.94#ibcon#read 5, iclass 17, count 0 2006.183.08:28:28.94#ibcon#about to read 6, iclass 17, count 0 2006.183.08:28:28.94#ibcon#read 6, iclass 17, count 0 2006.183.08:28:28.94#ibcon#end of sib2, iclass 17, count 0 2006.183.08:28:28.94#ibcon#*after write, iclass 17, count 0 2006.183.08:28:28.94#ibcon#*before return 0, iclass 17, count 0 2006.183.08:28:28.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:28.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:28.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:28:28.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:28:28.94$vc4f8/valo=4,832.99 2006.183.08:28:28.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.08:28:28.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.08:28:28.94#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:28.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:28.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:28.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:28.94#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:28:28.94#ibcon#first serial, iclass 19, count 0 2006.183.08:28:28.94#ibcon#enter sib2, iclass 19, count 0 2006.183.08:28:28.94#ibcon#flushed, iclass 19, count 0 2006.183.08:28:28.94#ibcon#about to write, iclass 19, count 0 2006.183.08:28:28.94#ibcon#wrote, iclass 19, count 0 2006.183.08:28:28.94#ibcon#about to read 3, iclass 19, count 0 2006.183.08:28:28.96#ibcon#read 3, iclass 19, count 0 2006.183.08:28:28.96#ibcon#about to read 4, iclass 19, count 0 2006.183.08:28:28.96#ibcon#read 4, iclass 19, count 0 2006.183.08:28:28.96#ibcon#about to read 5, iclass 19, count 0 2006.183.08:28:28.96#ibcon#read 5, iclass 19, count 0 2006.183.08:28:28.96#ibcon#about to read 6, iclass 19, count 0 2006.183.08:28:28.96#ibcon#read 6, iclass 19, count 0 2006.183.08:28:28.96#ibcon#end of sib2, iclass 19, count 0 2006.183.08:28:28.96#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:28:28.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:28:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.183.08:28:28.96#ibcon#*before write, iclass 19, count 0 2006.183.08:28:28.96#ibcon#enter sib2, iclass 19, count 0 2006.183.08:28:28.96#ibcon#flushed, iclass 19, count 0 2006.183.08:28:28.96#ibcon#about to write, iclass 19, count 0 2006.183.08:28:28.96#ibcon#wrote, iclass 19, count 0 2006.183.08:28:28.96#ibcon#about to read 3, iclass 19, count 0 2006.183.08:28:29.00#ibcon#read 3, iclass 19, count 0 2006.183.08:28:29.00#ibcon#about to read 4, iclass 19, count 0 2006.183.08:28:29.00#ibcon#read 4, iclass 19, count 0 2006.183.08:28:29.00#ibcon#about to read 5, iclass 19, count 0 2006.183.08:28:29.00#ibcon#read 5, iclass 19, count 0 2006.183.08:28:29.00#ibcon#about to read 6, iclass 19, count 0 2006.183.08:28:29.00#ibcon#read 6, iclass 19, count 0 2006.183.08:28:29.00#ibcon#end of sib2, iclass 19, count 0 2006.183.08:28:29.00#ibcon#*after write, iclass 19, count 0 2006.183.08:28:29.00#ibcon#*before return 0, iclass 19, count 0 2006.183.08:28:29.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:29.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:29.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:28:29.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:28:29.00$vc4f8/va=4,7 2006.183.08:28:29.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.08:28:29.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.08:28:29.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:29.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:29.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:29.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:29.06#ibcon#enter wrdev, iclass 21, count 2 2006.183.08:28:29.06#ibcon#first serial, iclass 21, count 2 2006.183.08:28:29.06#ibcon#enter sib2, iclass 21, count 2 2006.183.08:28:29.06#ibcon#flushed, iclass 21, count 2 2006.183.08:28:29.06#ibcon#about to write, iclass 21, count 2 2006.183.08:28:29.06#ibcon#wrote, iclass 21, count 2 2006.183.08:28:29.06#ibcon#about to read 3, iclass 21, count 2 2006.183.08:28:29.08#ibcon#read 3, iclass 21, count 2 2006.183.08:28:29.08#ibcon#about to read 4, iclass 21, count 2 2006.183.08:28:29.08#ibcon#read 4, iclass 21, count 2 2006.183.08:28:29.08#ibcon#about to read 5, iclass 21, count 2 2006.183.08:28:29.08#ibcon#read 5, iclass 21, count 2 2006.183.08:28:29.08#ibcon#about to read 6, iclass 21, count 2 2006.183.08:28:29.08#ibcon#read 6, iclass 21, count 2 2006.183.08:28:29.08#ibcon#end of sib2, iclass 21, count 2 2006.183.08:28:29.08#ibcon#*mode == 0, iclass 21, count 2 2006.183.08:28:29.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.08:28:29.08#ibcon#[25=AT04-07\r\n] 2006.183.08:28:29.08#ibcon#*before write, iclass 21, count 2 2006.183.08:28:29.08#ibcon#enter sib2, iclass 21, count 2 2006.183.08:28:29.08#ibcon#flushed, iclass 21, count 2 2006.183.08:28:29.08#ibcon#about to write, iclass 21, count 2 2006.183.08:28:29.08#ibcon#wrote, iclass 21, count 2 2006.183.08:28:29.08#ibcon#about to read 3, iclass 21, count 2 2006.183.08:28:29.11#ibcon#read 3, iclass 21, count 2 2006.183.08:28:29.11#ibcon#about to read 4, iclass 21, count 2 2006.183.08:28:29.11#ibcon#read 4, iclass 21, count 2 2006.183.08:28:29.11#ibcon#about to read 5, iclass 21, count 2 2006.183.08:28:29.11#ibcon#read 5, iclass 21, count 2 2006.183.08:28:29.11#ibcon#about to read 6, iclass 21, count 2 2006.183.08:28:29.11#ibcon#read 6, iclass 21, count 2 2006.183.08:28:29.11#ibcon#end of sib2, iclass 21, count 2 2006.183.08:28:29.11#ibcon#*after write, iclass 21, count 2 2006.183.08:28:29.11#ibcon#*before return 0, iclass 21, count 2 2006.183.08:28:29.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:29.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:29.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.08:28:29.11#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:29.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:29.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:29.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:29.23#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:28:29.23#ibcon#first serial, iclass 21, count 0 2006.183.08:28:29.23#ibcon#enter sib2, iclass 21, count 0 2006.183.08:28:29.23#ibcon#flushed, iclass 21, count 0 2006.183.08:28:29.23#ibcon#about to write, iclass 21, count 0 2006.183.08:28:29.23#ibcon#wrote, iclass 21, count 0 2006.183.08:28:29.23#ibcon#about to read 3, iclass 21, count 0 2006.183.08:28:29.25#ibcon#read 3, iclass 21, count 0 2006.183.08:28:29.25#ibcon#about to read 4, iclass 21, count 0 2006.183.08:28:29.25#ibcon#read 4, iclass 21, count 0 2006.183.08:28:29.25#ibcon#about to read 5, iclass 21, count 0 2006.183.08:28:29.25#ibcon#read 5, iclass 21, count 0 2006.183.08:28:29.25#ibcon#about to read 6, iclass 21, count 0 2006.183.08:28:29.25#ibcon#read 6, iclass 21, count 0 2006.183.08:28:29.25#ibcon#end of sib2, iclass 21, count 0 2006.183.08:28:29.25#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:28:29.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:28:29.25#ibcon#[25=USB\r\n] 2006.183.08:28:29.25#ibcon#*before write, iclass 21, count 0 2006.183.08:28:29.25#ibcon#enter sib2, iclass 21, count 0 2006.183.08:28:29.25#ibcon#flushed, iclass 21, count 0 2006.183.08:28:29.25#ibcon#about to write, iclass 21, count 0 2006.183.08:28:29.25#ibcon#wrote, iclass 21, count 0 2006.183.08:28:29.25#ibcon#about to read 3, iclass 21, count 0 2006.183.08:28:29.28#ibcon#read 3, iclass 21, count 0 2006.183.08:28:29.28#ibcon#about to read 4, iclass 21, count 0 2006.183.08:28:29.28#ibcon#read 4, iclass 21, count 0 2006.183.08:28:29.28#ibcon#about to read 5, iclass 21, count 0 2006.183.08:28:29.28#ibcon#read 5, iclass 21, count 0 2006.183.08:28:29.28#ibcon#about to read 6, iclass 21, count 0 2006.183.08:28:29.28#ibcon#read 6, iclass 21, count 0 2006.183.08:28:29.28#ibcon#end of sib2, iclass 21, count 0 2006.183.08:28:29.28#ibcon#*after write, iclass 21, count 0 2006.183.08:28:29.28#ibcon#*before return 0, iclass 21, count 0 2006.183.08:28:29.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:29.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:29.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:28:29.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:28:29.28$vc4f8/valo=5,652.99 2006.183.08:28:29.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:28:29.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:28:29.28#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:29.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:29.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:29.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:29.28#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:28:29.28#ibcon#first serial, iclass 23, count 0 2006.183.08:28:29.28#ibcon#enter sib2, iclass 23, count 0 2006.183.08:28:29.28#ibcon#flushed, iclass 23, count 0 2006.183.08:28:29.28#ibcon#about to write, iclass 23, count 0 2006.183.08:28:29.28#ibcon#wrote, iclass 23, count 0 2006.183.08:28:29.28#ibcon#about to read 3, iclass 23, count 0 2006.183.08:28:29.30#ibcon#read 3, iclass 23, count 0 2006.183.08:28:29.30#ibcon#about to read 4, iclass 23, count 0 2006.183.08:28:29.30#ibcon#read 4, iclass 23, count 0 2006.183.08:28:29.30#ibcon#about to read 5, iclass 23, count 0 2006.183.08:28:29.30#ibcon#read 5, iclass 23, count 0 2006.183.08:28:29.30#ibcon#about to read 6, iclass 23, count 0 2006.183.08:28:29.30#ibcon#read 6, iclass 23, count 0 2006.183.08:28:29.30#ibcon#end of sib2, iclass 23, count 0 2006.183.08:28:29.30#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:28:29.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:28:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.183.08:28:29.30#ibcon#*before write, iclass 23, count 0 2006.183.08:28:29.30#ibcon#enter sib2, iclass 23, count 0 2006.183.08:28:29.30#ibcon#flushed, iclass 23, count 0 2006.183.08:28:29.30#ibcon#about to write, iclass 23, count 0 2006.183.08:28:29.30#ibcon#wrote, iclass 23, count 0 2006.183.08:28:29.30#ibcon#about to read 3, iclass 23, count 0 2006.183.08:28:29.34#ibcon#read 3, iclass 23, count 0 2006.183.08:28:29.34#ibcon#about to read 4, iclass 23, count 0 2006.183.08:28:29.34#ibcon#read 4, iclass 23, count 0 2006.183.08:28:29.34#ibcon#about to read 5, iclass 23, count 0 2006.183.08:28:29.34#ibcon#read 5, iclass 23, count 0 2006.183.08:28:29.34#ibcon#about to read 6, iclass 23, count 0 2006.183.08:28:29.34#ibcon#read 6, iclass 23, count 0 2006.183.08:28:29.34#ibcon#end of sib2, iclass 23, count 0 2006.183.08:28:29.34#ibcon#*after write, iclass 23, count 0 2006.183.08:28:29.34#ibcon#*before return 0, iclass 23, count 0 2006.183.08:28:29.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:29.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:29.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:28:29.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:28:29.34$vc4f8/va=5,7 2006.183.08:28:29.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.08:28:29.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.08:28:29.34#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:29.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:29.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:29.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:29.40#ibcon#enter wrdev, iclass 25, count 2 2006.183.08:28:29.40#ibcon#first serial, iclass 25, count 2 2006.183.08:28:29.40#ibcon#enter sib2, iclass 25, count 2 2006.183.08:28:29.40#ibcon#flushed, iclass 25, count 2 2006.183.08:28:29.40#ibcon#about to write, iclass 25, count 2 2006.183.08:28:29.40#ibcon#wrote, iclass 25, count 2 2006.183.08:28:29.40#ibcon#about to read 3, iclass 25, count 2 2006.183.08:28:29.42#ibcon#read 3, iclass 25, count 2 2006.183.08:28:29.42#ibcon#about to read 4, iclass 25, count 2 2006.183.08:28:29.42#ibcon#read 4, iclass 25, count 2 2006.183.08:28:29.42#ibcon#about to read 5, iclass 25, count 2 2006.183.08:28:29.42#ibcon#read 5, iclass 25, count 2 2006.183.08:28:29.42#ibcon#about to read 6, iclass 25, count 2 2006.183.08:28:29.42#ibcon#read 6, iclass 25, count 2 2006.183.08:28:29.42#ibcon#end of sib2, iclass 25, count 2 2006.183.08:28:29.42#ibcon#*mode == 0, iclass 25, count 2 2006.183.08:28:29.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.08:28:29.42#ibcon#[25=AT05-07\r\n] 2006.183.08:28:29.42#ibcon#*before write, iclass 25, count 2 2006.183.08:28:29.42#ibcon#enter sib2, iclass 25, count 2 2006.183.08:28:29.42#ibcon#flushed, iclass 25, count 2 2006.183.08:28:29.42#ibcon#about to write, iclass 25, count 2 2006.183.08:28:29.42#ibcon#wrote, iclass 25, count 2 2006.183.08:28:29.42#ibcon#about to read 3, iclass 25, count 2 2006.183.08:28:29.45#ibcon#read 3, iclass 25, count 2 2006.183.08:28:29.45#ibcon#about to read 4, iclass 25, count 2 2006.183.08:28:29.45#ibcon#read 4, iclass 25, count 2 2006.183.08:28:29.45#ibcon#about to read 5, iclass 25, count 2 2006.183.08:28:29.45#ibcon#read 5, iclass 25, count 2 2006.183.08:28:29.45#ibcon#about to read 6, iclass 25, count 2 2006.183.08:28:29.45#ibcon#read 6, iclass 25, count 2 2006.183.08:28:29.45#ibcon#end of sib2, iclass 25, count 2 2006.183.08:28:29.45#ibcon#*after write, iclass 25, count 2 2006.183.08:28:29.45#ibcon#*before return 0, iclass 25, count 2 2006.183.08:28:29.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:29.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:29.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.08:28:29.45#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:29.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:29.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:29.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:29.57#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:28:29.57#ibcon#first serial, iclass 25, count 0 2006.183.08:28:29.57#ibcon#enter sib2, iclass 25, count 0 2006.183.08:28:29.57#ibcon#flushed, iclass 25, count 0 2006.183.08:28:29.57#ibcon#about to write, iclass 25, count 0 2006.183.08:28:29.57#ibcon#wrote, iclass 25, count 0 2006.183.08:28:29.57#ibcon#about to read 3, iclass 25, count 0 2006.183.08:28:29.59#ibcon#read 3, iclass 25, count 0 2006.183.08:28:29.59#ibcon#about to read 4, iclass 25, count 0 2006.183.08:28:29.59#ibcon#read 4, iclass 25, count 0 2006.183.08:28:29.59#ibcon#about to read 5, iclass 25, count 0 2006.183.08:28:29.59#ibcon#read 5, iclass 25, count 0 2006.183.08:28:29.59#ibcon#about to read 6, iclass 25, count 0 2006.183.08:28:29.59#ibcon#read 6, iclass 25, count 0 2006.183.08:28:29.59#ibcon#end of sib2, iclass 25, count 0 2006.183.08:28:29.59#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:28:29.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:28:29.59#ibcon#[25=USB\r\n] 2006.183.08:28:29.59#ibcon#*before write, iclass 25, count 0 2006.183.08:28:29.59#ibcon#enter sib2, iclass 25, count 0 2006.183.08:28:29.59#ibcon#flushed, iclass 25, count 0 2006.183.08:28:29.59#ibcon#about to write, iclass 25, count 0 2006.183.08:28:29.59#ibcon#wrote, iclass 25, count 0 2006.183.08:28:29.59#ibcon#about to read 3, iclass 25, count 0 2006.183.08:28:29.62#ibcon#read 3, iclass 25, count 0 2006.183.08:28:29.62#ibcon#about to read 4, iclass 25, count 0 2006.183.08:28:29.62#ibcon#read 4, iclass 25, count 0 2006.183.08:28:29.62#ibcon#about to read 5, iclass 25, count 0 2006.183.08:28:29.62#ibcon#read 5, iclass 25, count 0 2006.183.08:28:29.62#ibcon#about to read 6, iclass 25, count 0 2006.183.08:28:29.62#ibcon#read 6, iclass 25, count 0 2006.183.08:28:29.62#ibcon#end of sib2, iclass 25, count 0 2006.183.08:28:29.62#ibcon#*after write, iclass 25, count 0 2006.183.08:28:29.62#ibcon#*before return 0, iclass 25, count 0 2006.183.08:28:29.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:29.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:29.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:28:29.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:28:29.62$vc4f8/valo=6,772.99 2006.183.08:28:29.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.08:28:29.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.08:28:29.62#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:29.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:29.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:29.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:29.62#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:28:29.62#ibcon#first serial, iclass 27, count 0 2006.183.08:28:29.62#ibcon#enter sib2, iclass 27, count 0 2006.183.08:28:29.62#ibcon#flushed, iclass 27, count 0 2006.183.08:28:29.62#ibcon#about to write, iclass 27, count 0 2006.183.08:28:29.62#ibcon#wrote, iclass 27, count 0 2006.183.08:28:29.62#ibcon#about to read 3, iclass 27, count 0 2006.183.08:28:29.64#ibcon#read 3, iclass 27, count 0 2006.183.08:28:29.64#ibcon#about to read 4, iclass 27, count 0 2006.183.08:28:29.64#ibcon#read 4, iclass 27, count 0 2006.183.08:28:29.64#ibcon#about to read 5, iclass 27, count 0 2006.183.08:28:29.64#ibcon#read 5, iclass 27, count 0 2006.183.08:28:29.64#ibcon#about to read 6, iclass 27, count 0 2006.183.08:28:29.64#ibcon#read 6, iclass 27, count 0 2006.183.08:28:29.64#ibcon#end of sib2, iclass 27, count 0 2006.183.08:28:29.64#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:28:29.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:28:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.183.08:28:29.64#ibcon#*before write, iclass 27, count 0 2006.183.08:28:29.64#ibcon#enter sib2, iclass 27, count 0 2006.183.08:28:29.64#ibcon#flushed, iclass 27, count 0 2006.183.08:28:29.64#ibcon#about to write, iclass 27, count 0 2006.183.08:28:29.64#ibcon#wrote, iclass 27, count 0 2006.183.08:28:29.64#ibcon#about to read 3, iclass 27, count 0 2006.183.08:28:29.68#ibcon#read 3, iclass 27, count 0 2006.183.08:28:29.68#ibcon#about to read 4, iclass 27, count 0 2006.183.08:28:29.68#ibcon#read 4, iclass 27, count 0 2006.183.08:28:29.68#ibcon#about to read 5, iclass 27, count 0 2006.183.08:28:29.68#ibcon#read 5, iclass 27, count 0 2006.183.08:28:29.68#ibcon#about to read 6, iclass 27, count 0 2006.183.08:28:29.68#ibcon#read 6, iclass 27, count 0 2006.183.08:28:29.68#ibcon#end of sib2, iclass 27, count 0 2006.183.08:28:29.68#ibcon#*after write, iclass 27, count 0 2006.183.08:28:29.68#ibcon#*before return 0, iclass 27, count 0 2006.183.08:28:29.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:29.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:29.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:28:29.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:28:29.68$vc4f8/va=6,6 2006.183.08:28:29.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.183.08:28:29.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.183.08:28:29.68#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:29.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:28:29.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:28:29.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:28:29.74#ibcon#enter wrdev, iclass 29, count 2 2006.183.08:28:29.74#ibcon#first serial, iclass 29, count 2 2006.183.08:28:29.74#ibcon#enter sib2, iclass 29, count 2 2006.183.08:28:29.74#ibcon#flushed, iclass 29, count 2 2006.183.08:28:29.74#ibcon#about to write, iclass 29, count 2 2006.183.08:28:29.74#ibcon#wrote, iclass 29, count 2 2006.183.08:28:29.74#ibcon#about to read 3, iclass 29, count 2 2006.183.08:28:29.76#ibcon#read 3, iclass 29, count 2 2006.183.08:28:29.76#ibcon#about to read 4, iclass 29, count 2 2006.183.08:28:29.76#ibcon#read 4, iclass 29, count 2 2006.183.08:28:29.76#ibcon#about to read 5, iclass 29, count 2 2006.183.08:28:29.76#ibcon#read 5, iclass 29, count 2 2006.183.08:28:29.76#ibcon#about to read 6, iclass 29, count 2 2006.183.08:28:29.76#ibcon#read 6, iclass 29, count 2 2006.183.08:28:29.76#ibcon#end of sib2, iclass 29, count 2 2006.183.08:28:29.76#ibcon#*mode == 0, iclass 29, count 2 2006.183.08:28:29.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.183.08:28:29.76#ibcon#[25=AT06-06\r\n] 2006.183.08:28:29.76#ibcon#*before write, iclass 29, count 2 2006.183.08:28:29.76#ibcon#enter sib2, iclass 29, count 2 2006.183.08:28:29.76#ibcon#flushed, iclass 29, count 2 2006.183.08:28:29.76#ibcon#about to write, iclass 29, count 2 2006.183.08:28:29.76#ibcon#wrote, iclass 29, count 2 2006.183.08:28:29.76#ibcon#about to read 3, iclass 29, count 2 2006.183.08:28:29.79#ibcon#read 3, iclass 29, count 2 2006.183.08:28:29.79#ibcon#about to read 4, iclass 29, count 2 2006.183.08:28:29.79#ibcon#read 4, iclass 29, count 2 2006.183.08:28:29.79#ibcon#about to read 5, iclass 29, count 2 2006.183.08:28:29.79#ibcon#read 5, iclass 29, count 2 2006.183.08:28:29.79#ibcon#about to read 6, iclass 29, count 2 2006.183.08:28:29.79#ibcon#read 6, iclass 29, count 2 2006.183.08:28:29.79#ibcon#end of sib2, iclass 29, count 2 2006.183.08:28:29.79#ibcon#*after write, iclass 29, count 2 2006.183.08:28:29.79#ibcon#*before return 0, iclass 29, count 2 2006.183.08:28:29.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:28:29.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.183.08:28:29.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.183.08:28:29.79#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:29.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:28:29.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:28:29.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:28:29.91#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:28:29.91#ibcon#first serial, iclass 29, count 0 2006.183.08:28:29.91#ibcon#enter sib2, iclass 29, count 0 2006.183.08:28:29.91#ibcon#flushed, iclass 29, count 0 2006.183.08:28:29.91#ibcon#about to write, iclass 29, count 0 2006.183.08:28:29.91#ibcon#wrote, iclass 29, count 0 2006.183.08:28:29.91#ibcon#about to read 3, iclass 29, count 0 2006.183.08:28:29.93#ibcon#read 3, iclass 29, count 0 2006.183.08:28:29.93#ibcon#about to read 4, iclass 29, count 0 2006.183.08:28:29.93#ibcon#read 4, iclass 29, count 0 2006.183.08:28:29.93#ibcon#about to read 5, iclass 29, count 0 2006.183.08:28:29.93#ibcon#read 5, iclass 29, count 0 2006.183.08:28:29.93#ibcon#about to read 6, iclass 29, count 0 2006.183.08:28:29.93#ibcon#read 6, iclass 29, count 0 2006.183.08:28:29.93#ibcon#end of sib2, iclass 29, count 0 2006.183.08:28:29.93#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:28:29.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:28:29.93#ibcon#[25=USB\r\n] 2006.183.08:28:29.93#ibcon#*before write, iclass 29, count 0 2006.183.08:28:29.93#ibcon#enter sib2, iclass 29, count 0 2006.183.08:28:29.93#ibcon#flushed, iclass 29, count 0 2006.183.08:28:29.93#ibcon#about to write, iclass 29, count 0 2006.183.08:28:29.93#ibcon#wrote, iclass 29, count 0 2006.183.08:28:29.93#ibcon#about to read 3, iclass 29, count 0 2006.183.08:28:29.96#ibcon#read 3, iclass 29, count 0 2006.183.08:28:29.96#ibcon#about to read 4, iclass 29, count 0 2006.183.08:28:29.96#ibcon#read 4, iclass 29, count 0 2006.183.08:28:29.96#ibcon#about to read 5, iclass 29, count 0 2006.183.08:28:29.96#ibcon#read 5, iclass 29, count 0 2006.183.08:28:29.96#ibcon#about to read 6, iclass 29, count 0 2006.183.08:28:29.96#ibcon#read 6, iclass 29, count 0 2006.183.08:28:29.96#ibcon#end of sib2, iclass 29, count 0 2006.183.08:28:29.96#ibcon#*after write, iclass 29, count 0 2006.183.08:28:29.96#ibcon#*before return 0, iclass 29, count 0 2006.183.08:28:29.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:28:29.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.183.08:28:29.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:28:29.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:28:29.96$vc4f8/valo=7,832.99 2006.183.08:28:29.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.183.08:28:29.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.183.08:28:29.96#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:29.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:28:29.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:28:29.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:28:29.96#ibcon#enter wrdev, iclass 31, count 0 2006.183.08:28:29.96#ibcon#first serial, iclass 31, count 0 2006.183.08:28:29.96#ibcon#enter sib2, iclass 31, count 0 2006.183.08:28:29.96#ibcon#flushed, iclass 31, count 0 2006.183.08:28:29.96#ibcon#about to write, iclass 31, count 0 2006.183.08:28:29.96#ibcon#wrote, iclass 31, count 0 2006.183.08:28:29.96#ibcon#about to read 3, iclass 31, count 0 2006.183.08:28:29.98#ibcon#read 3, iclass 31, count 0 2006.183.08:28:29.98#ibcon#about to read 4, iclass 31, count 0 2006.183.08:28:29.98#ibcon#read 4, iclass 31, count 0 2006.183.08:28:29.98#ibcon#about to read 5, iclass 31, count 0 2006.183.08:28:29.98#ibcon#read 5, iclass 31, count 0 2006.183.08:28:29.98#ibcon#about to read 6, iclass 31, count 0 2006.183.08:28:29.98#ibcon#read 6, iclass 31, count 0 2006.183.08:28:29.98#ibcon#end of sib2, iclass 31, count 0 2006.183.08:28:29.98#ibcon#*mode == 0, iclass 31, count 0 2006.183.08:28:29.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.183.08:28:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.183.08:28:29.98#ibcon#*before write, iclass 31, count 0 2006.183.08:28:29.98#ibcon#enter sib2, iclass 31, count 0 2006.183.08:28:29.98#ibcon#flushed, iclass 31, count 0 2006.183.08:28:29.98#ibcon#about to write, iclass 31, count 0 2006.183.08:28:29.98#ibcon#wrote, iclass 31, count 0 2006.183.08:28:29.98#ibcon#about to read 3, iclass 31, count 0 2006.183.08:28:30.02#ibcon#read 3, iclass 31, count 0 2006.183.08:28:30.02#ibcon#about to read 4, iclass 31, count 0 2006.183.08:28:30.02#ibcon#read 4, iclass 31, count 0 2006.183.08:28:30.02#ibcon#about to read 5, iclass 31, count 0 2006.183.08:28:30.02#ibcon#read 5, iclass 31, count 0 2006.183.08:28:30.02#ibcon#about to read 6, iclass 31, count 0 2006.183.08:28:30.02#ibcon#read 6, iclass 31, count 0 2006.183.08:28:30.02#ibcon#end of sib2, iclass 31, count 0 2006.183.08:28:30.02#ibcon#*after write, iclass 31, count 0 2006.183.08:28:30.02#ibcon#*before return 0, iclass 31, count 0 2006.183.08:28:30.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:28:30.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.183.08:28:30.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.183.08:28:30.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.183.08:28:30.02$vc4f8/va=7,6 2006.183.08:28:30.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.183.08:28:30.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.183.08:28:30.02#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:30.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:28:30.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:28:30.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:28:30.08#ibcon#enter wrdev, iclass 33, count 2 2006.183.08:28:30.08#ibcon#first serial, iclass 33, count 2 2006.183.08:28:30.08#ibcon#enter sib2, iclass 33, count 2 2006.183.08:28:30.08#ibcon#flushed, iclass 33, count 2 2006.183.08:28:30.08#ibcon#about to write, iclass 33, count 2 2006.183.08:28:30.08#ibcon#wrote, iclass 33, count 2 2006.183.08:28:30.08#ibcon#about to read 3, iclass 33, count 2 2006.183.08:28:30.10#ibcon#read 3, iclass 33, count 2 2006.183.08:28:30.10#ibcon#about to read 4, iclass 33, count 2 2006.183.08:28:30.10#ibcon#read 4, iclass 33, count 2 2006.183.08:28:30.10#ibcon#about to read 5, iclass 33, count 2 2006.183.08:28:30.10#ibcon#read 5, iclass 33, count 2 2006.183.08:28:30.10#ibcon#about to read 6, iclass 33, count 2 2006.183.08:28:30.10#ibcon#read 6, iclass 33, count 2 2006.183.08:28:30.10#ibcon#end of sib2, iclass 33, count 2 2006.183.08:28:30.10#ibcon#*mode == 0, iclass 33, count 2 2006.183.08:28:30.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.183.08:28:30.10#ibcon#[25=AT07-06\r\n] 2006.183.08:28:30.10#ibcon#*before write, iclass 33, count 2 2006.183.08:28:30.10#ibcon#enter sib2, iclass 33, count 2 2006.183.08:28:30.10#ibcon#flushed, iclass 33, count 2 2006.183.08:28:30.10#ibcon#about to write, iclass 33, count 2 2006.183.08:28:30.10#ibcon#wrote, iclass 33, count 2 2006.183.08:28:30.10#ibcon#about to read 3, iclass 33, count 2 2006.183.08:28:30.13#ibcon#read 3, iclass 33, count 2 2006.183.08:28:30.13#ibcon#about to read 4, iclass 33, count 2 2006.183.08:28:30.13#ibcon#read 4, iclass 33, count 2 2006.183.08:28:30.13#ibcon#about to read 5, iclass 33, count 2 2006.183.08:28:30.13#ibcon#read 5, iclass 33, count 2 2006.183.08:28:30.13#ibcon#about to read 6, iclass 33, count 2 2006.183.08:28:30.13#ibcon#read 6, iclass 33, count 2 2006.183.08:28:30.13#ibcon#end of sib2, iclass 33, count 2 2006.183.08:28:30.13#ibcon#*after write, iclass 33, count 2 2006.183.08:28:30.13#ibcon#*before return 0, iclass 33, count 2 2006.183.08:28:30.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:28:30.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.183.08:28:30.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.183.08:28:30.13#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:30.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:28:30.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:28:30.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:28:30.25#ibcon#enter wrdev, iclass 33, count 0 2006.183.08:28:30.25#ibcon#first serial, iclass 33, count 0 2006.183.08:28:30.25#ibcon#enter sib2, iclass 33, count 0 2006.183.08:28:30.25#ibcon#flushed, iclass 33, count 0 2006.183.08:28:30.25#ibcon#about to write, iclass 33, count 0 2006.183.08:28:30.25#ibcon#wrote, iclass 33, count 0 2006.183.08:28:30.25#ibcon#about to read 3, iclass 33, count 0 2006.183.08:28:30.27#ibcon#read 3, iclass 33, count 0 2006.183.08:28:30.27#ibcon#about to read 4, iclass 33, count 0 2006.183.08:28:30.27#ibcon#read 4, iclass 33, count 0 2006.183.08:28:30.27#ibcon#about to read 5, iclass 33, count 0 2006.183.08:28:30.27#ibcon#read 5, iclass 33, count 0 2006.183.08:28:30.27#ibcon#about to read 6, iclass 33, count 0 2006.183.08:28:30.27#ibcon#read 6, iclass 33, count 0 2006.183.08:28:30.27#ibcon#end of sib2, iclass 33, count 0 2006.183.08:28:30.27#ibcon#*mode == 0, iclass 33, count 0 2006.183.08:28:30.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.183.08:28:30.27#ibcon#[25=USB\r\n] 2006.183.08:28:30.27#ibcon#*before write, iclass 33, count 0 2006.183.08:28:30.27#ibcon#enter sib2, iclass 33, count 0 2006.183.08:28:30.27#ibcon#flushed, iclass 33, count 0 2006.183.08:28:30.27#ibcon#about to write, iclass 33, count 0 2006.183.08:28:30.27#ibcon#wrote, iclass 33, count 0 2006.183.08:28:30.27#ibcon#about to read 3, iclass 33, count 0 2006.183.08:28:30.30#ibcon#read 3, iclass 33, count 0 2006.183.08:28:30.30#ibcon#about to read 4, iclass 33, count 0 2006.183.08:28:30.30#ibcon#read 4, iclass 33, count 0 2006.183.08:28:30.30#ibcon#about to read 5, iclass 33, count 0 2006.183.08:28:30.30#ibcon#read 5, iclass 33, count 0 2006.183.08:28:30.30#ibcon#about to read 6, iclass 33, count 0 2006.183.08:28:30.30#ibcon#read 6, iclass 33, count 0 2006.183.08:28:30.30#ibcon#end of sib2, iclass 33, count 0 2006.183.08:28:30.30#ibcon#*after write, iclass 33, count 0 2006.183.08:28:30.30#ibcon#*before return 0, iclass 33, count 0 2006.183.08:28:30.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:28:30.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.183.08:28:30.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.183.08:28:30.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.183.08:28:30.30$vc4f8/valo=8,852.99 2006.183.08:28:30.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.183.08:28:30.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.183.08:28:30.30#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:30.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:28:30.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:28:30.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:28:30.30#ibcon#enter wrdev, iclass 35, count 0 2006.183.08:28:30.30#ibcon#first serial, iclass 35, count 0 2006.183.08:28:30.30#ibcon#enter sib2, iclass 35, count 0 2006.183.08:28:30.30#ibcon#flushed, iclass 35, count 0 2006.183.08:28:30.30#ibcon#about to write, iclass 35, count 0 2006.183.08:28:30.30#ibcon#wrote, iclass 35, count 0 2006.183.08:28:30.30#ibcon#about to read 3, iclass 35, count 0 2006.183.08:28:30.32#ibcon#read 3, iclass 35, count 0 2006.183.08:28:30.32#ibcon#about to read 4, iclass 35, count 0 2006.183.08:28:30.32#ibcon#read 4, iclass 35, count 0 2006.183.08:28:30.32#ibcon#about to read 5, iclass 35, count 0 2006.183.08:28:30.32#ibcon#read 5, iclass 35, count 0 2006.183.08:28:30.32#ibcon#about to read 6, iclass 35, count 0 2006.183.08:28:30.32#ibcon#read 6, iclass 35, count 0 2006.183.08:28:30.32#ibcon#end of sib2, iclass 35, count 0 2006.183.08:28:30.32#ibcon#*mode == 0, iclass 35, count 0 2006.183.08:28:30.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.183.08:28:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.183.08:28:30.32#ibcon#*before write, iclass 35, count 0 2006.183.08:28:30.32#ibcon#enter sib2, iclass 35, count 0 2006.183.08:28:30.32#ibcon#flushed, iclass 35, count 0 2006.183.08:28:30.32#ibcon#about to write, iclass 35, count 0 2006.183.08:28:30.32#ibcon#wrote, iclass 35, count 0 2006.183.08:28:30.32#ibcon#about to read 3, iclass 35, count 0 2006.183.08:28:30.36#ibcon#read 3, iclass 35, count 0 2006.183.08:28:30.36#ibcon#about to read 4, iclass 35, count 0 2006.183.08:28:30.36#ibcon#read 4, iclass 35, count 0 2006.183.08:28:30.36#ibcon#about to read 5, iclass 35, count 0 2006.183.08:28:30.36#ibcon#read 5, iclass 35, count 0 2006.183.08:28:30.36#ibcon#about to read 6, iclass 35, count 0 2006.183.08:28:30.36#ibcon#read 6, iclass 35, count 0 2006.183.08:28:30.36#ibcon#end of sib2, iclass 35, count 0 2006.183.08:28:30.36#ibcon#*after write, iclass 35, count 0 2006.183.08:28:30.36#ibcon#*before return 0, iclass 35, count 0 2006.183.08:28:30.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:28:30.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.183.08:28:30.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.183.08:28:30.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.183.08:28:30.36$vc4f8/va=8,7 2006.183.08:28:30.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.183.08:28:30.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.183.08:28:30.36#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:30.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:28:30.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:28:30.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:28:30.42#ibcon#enter wrdev, iclass 37, count 2 2006.183.08:28:30.42#ibcon#first serial, iclass 37, count 2 2006.183.08:28:30.42#ibcon#enter sib2, iclass 37, count 2 2006.183.08:28:30.42#ibcon#flushed, iclass 37, count 2 2006.183.08:28:30.42#ibcon#about to write, iclass 37, count 2 2006.183.08:28:30.42#ibcon#wrote, iclass 37, count 2 2006.183.08:28:30.42#ibcon#about to read 3, iclass 37, count 2 2006.183.08:28:30.44#ibcon#read 3, iclass 37, count 2 2006.183.08:28:30.44#ibcon#about to read 4, iclass 37, count 2 2006.183.08:28:30.44#ibcon#read 4, iclass 37, count 2 2006.183.08:28:30.44#ibcon#about to read 5, iclass 37, count 2 2006.183.08:28:30.44#ibcon#read 5, iclass 37, count 2 2006.183.08:28:30.44#ibcon#about to read 6, iclass 37, count 2 2006.183.08:28:30.44#ibcon#read 6, iclass 37, count 2 2006.183.08:28:30.44#ibcon#end of sib2, iclass 37, count 2 2006.183.08:28:30.44#ibcon#*mode == 0, iclass 37, count 2 2006.183.08:28:30.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.183.08:28:30.44#ibcon#[25=AT08-07\r\n] 2006.183.08:28:30.44#ibcon#*before write, iclass 37, count 2 2006.183.08:28:30.44#ibcon#enter sib2, iclass 37, count 2 2006.183.08:28:30.44#ibcon#flushed, iclass 37, count 2 2006.183.08:28:30.44#ibcon#about to write, iclass 37, count 2 2006.183.08:28:30.44#ibcon#wrote, iclass 37, count 2 2006.183.08:28:30.44#ibcon#about to read 3, iclass 37, count 2 2006.183.08:28:30.47#ibcon#read 3, iclass 37, count 2 2006.183.08:28:30.47#ibcon#about to read 4, iclass 37, count 2 2006.183.08:28:30.47#ibcon#read 4, iclass 37, count 2 2006.183.08:28:30.47#ibcon#about to read 5, iclass 37, count 2 2006.183.08:28:30.47#ibcon#read 5, iclass 37, count 2 2006.183.08:28:30.47#ibcon#about to read 6, iclass 37, count 2 2006.183.08:28:30.47#ibcon#read 6, iclass 37, count 2 2006.183.08:28:30.47#ibcon#end of sib2, iclass 37, count 2 2006.183.08:28:30.47#ibcon#*after write, iclass 37, count 2 2006.183.08:28:30.47#ibcon#*before return 0, iclass 37, count 2 2006.183.08:28:30.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:28:30.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.183.08:28:30.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.183.08:28:30.47#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:30.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:28:30.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:28:30.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:28:30.59#ibcon#enter wrdev, iclass 37, count 0 2006.183.08:28:30.59#ibcon#first serial, iclass 37, count 0 2006.183.08:28:30.59#ibcon#enter sib2, iclass 37, count 0 2006.183.08:28:30.59#ibcon#flushed, iclass 37, count 0 2006.183.08:28:30.59#ibcon#about to write, iclass 37, count 0 2006.183.08:28:30.59#ibcon#wrote, iclass 37, count 0 2006.183.08:28:30.59#ibcon#about to read 3, iclass 37, count 0 2006.183.08:28:30.61#ibcon#read 3, iclass 37, count 0 2006.183.08:28:30.61#ibcon#about to read 4, iclass 37, count 0 2006.183.08:28:30.61#ibcon#read 4, iclass 37, count 0 2006.183.08:28:30.61#ibcon#about to read 5, iclass 37, count 0 2006.183.08:28:30.61#ibcon#read 5, iclass 37, count 0 2006.183.08:28:30.61#ibcon#about to read 6, iclass 37, count 0 2006.183.08:28:30.61#ibcon#read 6, iclass 37, count 0 2006.183.08:28:30.61#ibcon#end of sib2, iclass 37, count 0 2006.183.08:28:30.61#ibcon#*mode == 0, iclass 37, count 0 2006.183.08:28:30.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.183.08:28:30.61#ibcon#[25=USB\r\n] 2006.183.08:28:30.61#ibcon#*before write, iclass 37, count 0 2006.183.08:28:30.61#ibcon#enter sib2, iclass 37, count 0 2006.183.08:28:30.61#ibcon#flushed, iclass 37, count 0 2006.183.08:28:30.61#ibcon#about to write, iclass 37, count 0 2006.183.08:28:30.61#ibcon#wrote, iclass 37, count 0 2006.183.08:28:30.61#ibcon#about to read 3, iclass 37, count 0 2006.183.08:28:30.64#ibcon#read 3, iclass 37, count 0 2006.183.08:28:30.64#ibcon#about to read 4, iclass 37, count 0 2006.183.08:28:30.64#ibcon#read 4, iclass 37, count 0 2006.183.08:28:30.64#ibcon#about to read 5, iclass 37, count 0 2006.183.08:28:30.64#ibcon#read 5, iclass 37, count 0 2006.183.08:28:30.64#ibcon#about to read 6, iclass 37, count 0 2006.183.08:28:30.64#ibcon#read 6, iclass 37, count 0 2006.183.08:28:30.64#ibcon#end of sib2, iclass 37, count 0 2006.183.08:28:30.64#ibcon#*after write, iclass 37, count 0 2006.183.08:28:30.64#ibcon#*before return 0, iclass 37, count 0 2006.183.08:28:30.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:28:30.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.183.08:28:30.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.183.08:28:30.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.183.08:28:30.64$vc4f8/vblo=1,632.99 2006.183.08:28:30.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.183.08:28:30.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.183.08:28:30.64#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:30.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:28:30.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:28:30.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:28:30.64#ibcon#enter wrdev, iclass 39, count 0 2006.183.08:28:30.64#ibcon#first serial, iclass 39, count 0 2006.183.08:28:30.64#ibcon#enter sib2, iclass 39, count 0 2006.183.08:28:30.64#ibcon#flushed, iclass 39, count 0 2006.183.08:28:30.64#ibcon#about to write, iclass 39, count 0 2006.183.08:28:30.64#ibcon#wrote, iclass 39, count 0 2006.183.08:28:30.64#ibcon#about to read 3, iclass 39, count 0 2006.183.08:28:30.66#ibcon#read 3, iclass 39, count 0 2006.183.08:28:30.66#ibcon#about to read 4, iclass 39, count 0 2006.183.08:28:30.66#ibcon#read 4, iclass 39, count 0 2006.183.08:28:30.66#ibcon#about to read 5, iclass 39, count 0 2006.183.08:28:30.66#ibcon#read 5, iclass 39, count 0 2006.183.08:28:30.66#ibcon#about to read 6, iclass 39, count 0 2006.183.08:28:30.66#ibcon#read 6, iclass 39, count 0 2006.183.08:28:30.66#ibcon#end of sib2, iclass 39, count 0 2006.183.08:28:30.66#ibcon#*mode == 0, iclass 39, count 0 2006.183.08:28:30.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.183.08:28:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.183.08:28:30.66#ibcon#*before write, iclass 39, count 0 2006.183.08:28:30.66#ibcon#enter sib2, iclass 39, count 0 2006.183.08:28:30.66#ibcon#flushed, iclass 39, count 0 2006.183.08:28:30.66#ibcon#about to write, iclass 39, count 0 2006.183.08:28:30.66#ibcon#wrote, iclass 39, count 0 2006.183.08:28:30.66#ibcon#about to read 3, iclass 39, count 0 2006.183.08:28:30.70#ibcon#read 3, iclass 39, count 0 2006.183.08:28:30.70#ibcon#about to read 4, iclass 39, count 0 2006.183.08:28:30.70#ibcon#read 4, iclass 39, count 0 2006.183.08:28:30.70#ibcon#about to read 5, iclass 39, count 0 2006.183.08:28:30.70#ibcon#read 5, iclass 39, count 0 2006.183.08:28:30.70#ibcon#about to read 6, iclass 39, count 0 2006.183.08:28:30.70#ibcon#read 6, iclass 39, count 0 2006.183.08:28:30.70#ibcon#end of sib2, iclass 39, count 0 2006.183.08:28:30.70#ibcon#*after write, iclass 39, count 0 2006.183.08:28:30.70#ibcon#*before return 0, iclass 39, count 0 2006.183.08:28:30.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:28:30.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.183.08:28:30.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.183.08:28:30.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.183.08:28:30.70$vc4f8/vb=1,4 2006.183.08:28:30.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.183.08:28:30.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.183.08:28:30.70#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:30.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:28:30.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:28:30.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:28:30.70#ibcon#enter wrdev, iclass 3, count 2 2006.183.08:28:30.70#ibcon#first serial, iclass 3, count 2 2006.183.08:28:30.70#ibcon#enter sib2, iclass 3, count 2 2006.183.08:28:30.70#ibcon#flushed, iclass 3, count 2 2006.183.08:28:30.70#ibcon#about to write, iclass 3, count 2 2006.183.08:28:30.70#ibcon#wrote, iclass 3, count 2 2006.183.08:28:30.70#ibcon#about to read 3, iclass 3, count 2 2006.183.08:28:30.72#ibcon#read 3, iclass 3, count 2 2006.183.08:28:30.72#ibcon#about to read 4, iclass 3, count 2 2006.183.08:28:30.72#ibcon#read 4, iclass 3, count 2 2006.183.08:28:30.72#ibcon#about to read 5, iclass 3, count 2 2006.183.08:28:30.72#ibcon#read 5, iclass 3, count 2 2006.183.08:28:30.72#ibcon#about to read 6, iclass 3, count 2 2006.183.08:28:30.72#ibcon#read 6, iclass 3, count 2 2006.183.08:28:30.72#ibcon#end of sib2, iclass 3, count 2 2006.183.08:28:30.72#ibcon#*mode == 0, iclass 3, count 2 2006.183.08:28:30.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.183.08:28:30.72#ibcon#[27=AT01-04\r\n] 2006.183.08:28:30.72#ibcon#*before write, iclass 3, count 2 2006.183.08:28:30.72#ibcon#enter sib2, iclass 3, count 2 2006.183.08:28:30.72#ibcon#flushed, iclass 3, count 2 2006.183.08:28:30.72#ibcon#about to write, iclass 3, count 2 2006.183.08:28:30.72#ibcon#wrote, iclass 3, count 2 2006.183.08:28:30.72#ibcon#about to read 3, iclass 3, count 2 2006.183.08:28:30.75#ibcon#read 3, iclass 3, count 2 2006.183.08:28:30.75#ibcon#about to read 4, iclass 3, count 2 2006.183.08:28:30.75#ibcon#read 4, iclass 3, count 2 2006.183.08:28:30.75#ibcon#about to read 5, iclass 3, count 2 2006.183.08:28:30.75#ibcon#read 5, iclass 3, count 2 2006.183.08:28:30.75#ibcon#about to read 6, iclass 3, count 2 2006.183.08:28:30.75#ibcon#read 6, iclass 3, count 2 2006.183.08:28:30.75#ibcon#end of sib2, iclass 3, count 2 2006.183.08:28:30.75#ibcon#*after write, iclass 3, count 2 2006.183.08:28:30.75#ibcon#*before return 0, iclass 3, count 2 2006.183.08:28:30.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:28:30.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.183.08:28:30.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.183.08:28:30.75#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:30.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:28:30.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:28:30.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:28:30.88#ibcon#enter wrdev, iclass 3, count 0 2006.183.08:28:30.88#ibcon#first serial, iclass 3, count 0 2006.183.08:28:30.88#ibcon#enter sib2, iclass 3, count 0 2006.183.08:28:30.88#ibcon#flushed, iclass 3, count 0 2006.183.08:28:30.88#ibcon#about to write, iclass 3, count 0 2006.183.08:28:30.88#ibcon#wrote, iclass 3, count 0 2006.183.08:28:30.88#ibcon#about to read 3, iclass 3, count 0 2006.183.08:28:30.89#ibcon#read 3, iclass 3, count 0 2006.183.08:28:30.89#ibcon#about to read 4, iclass 3, count 0 2006.183.08:28:30.89#ibcon#read 4, iclass 3, count 0 2006.183.08:28:30.89#ibcon#about to read 5, iclass 3, count 0 2006.183.08:28:30.89#ibcon#read 5, iclass 3, count 0 2006.183.08:28:30.89#ibcon#about to read 6, iclass 3, count 0 2006.183.08:28:30.89#ibcon#read 6, iclass 3, count 0 2006.183.08:28:30.89#ibcon#end of sib2, iclass 3, count 0 2006.183.08:28:30.89#ibcon#*mode == 0, iclass 3, count 0 2006.183.08:28:30.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.183.08:28:30.89#ibcon#[27=USB\r\n] 2006.183.08:28:30.89#ibcon#*before write, iclass 3, count 0 2006.183.08:28:30.89#ibcon#enter sib2, iclass 3, count 0 2006.183.08:28:30.89#ibcon#flushed, iclass 3, count 0 2006.183.08:28:30.89#ibcon#about to write, iclass 3, count 0 2006.183.08:28:30.89#ibcon#wrote, iclass 3, count 0 2006.183.08:28:30.89#ibcon#about to read 3, iclass 3, count 0 2006.183.08:28:30.92#ibcon#read 3, iclass 3, count 0 2006.183.08:28:30.92#ibcon#about to read 4, iclass 3, count 0 2006.183.08:28:30.92#ibcon#read 4, iclass 3, count 0 2006.183.08:28:30.92#ibcon#about to read 5, iclass 3, count 0 2006.183.08:28:30.92#ibcon#read 5, iclass 3, count 0 2006.183.08:28:30.92#ibcon#about to read 6, iclass 3, count 0 2006.183.08:28:30.92#ibcon#read 6, iclass 3, count 0 2006.183.08:28:30.92#ibcon#end of sib2, iclass 3, count 0 2006.183.08:28:30.92#ibcon#*after write, iclass 3, count 0 2006.183.08:28:30.92#ibcon#*before return 0, iclass 3, count 0 2006.183.08:28:30.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:28:30.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.183.08:28:30.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.183.08:28:30.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.183.08:28:30.92$vc4f8/vblo=2,640.99 2006.183.08:28:30.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.183.08:28:30.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.183.08:28:30.92#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:30.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:30.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:30.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:30.92#ibcon#enter wrdev, iclass 5, count 0 2006.183.08:28:30.92#ibcon#first serial, iclass 5, count 0 2006.183.08:28:30.92#ibcon#enter sib2, iclass 5, count 0 2006.183.08:28:30.92#ibcon#flushed, iclass 5, count 0 2006.183.08:28:30.92#ibcon#about to write, iclass 5, count 0 2006.183.08:28:30.92#ibcon#wrote, iclass 5, count 0 2006.183.08:28:30.92#ibcon#about to read 3, iclass 5, count 0 2006.183.08:28:30.94#ibcon#read 3, iclass 5, count 0 2006.183.08:28:30.94#ibcon#about to read 4, iclass 5, count 0 2006.183.08:28:30.94#ibcon#read 4, iclass 5, count 0 2006.183.08:28:30.94#ibcon#about to read 5, iclass 5, count 0 2006.183.08:28:30.94#ibcon#read 5, iclass 5, count 0 2006.183.08:28:30.94#ibcon#about to read 6, iclass 5, count 0 2006.183.08:28:30.94#ibcon#read 6, iclass 5, count 0 2006.183.08:28:30.94#ibcon#end of sib2, iclass 5, count 0 2006.183.08:28:30.94#ibcon#*mode == 0, iclass 5, count 0 2006.183.08:28:30.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.183.08:28:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.183.08:28:30.94#ibcon#*before write, iclass 5, count 0 2006.183.08:28:30.94#ibcon#enter sib2, iclass 5, count 0 2006.183.08:28:30.94#ibcon#flushed, iclass 5, count 0 2006.183.08:28:30.94#ibcon#about to write, iclass 5, count 0 2006.183.08:28:30.94#ibcon#wrote, iclass 5, count 0 2006.183.08:28:30.94#ibcon#about to read 3, iclass 5, count 0 2006.183.08:28:30.98#ibcon#read 3, iclass 5, count 0 2006.183.08:28:30.98#ibcon#about to read 4, iclass 5, count 0 2006.183.08:28:30.98#ibcon#read 4, iclass 5, count 0 2006.183.08:28:30.98#ibcon#about to read 5, iclass 5, count 0 2006.183.08:28:30.98#ibcon#read 5, iclass 5, count 0 2006.183.08:28:30.98#ibcon#about to read 6, iclass 5, count 0 2006.183.08:28:30.98#ibcon#read 6, iclass 5, count 0 2006.183.08:28:30.98#ibcon#end of sib2, iclass 5, count 0 2006.183.08:28:30.98#ibcon#*after write, iclass 5, count 0 2006.183.08:28:30.98#ibcon#*before return 0, iclass 5, count 0 2006.183.08:28:30.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:30.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.183.08:28:30.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.183.08:28:30.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.183.08:28:30.98$vc4f8/vb=2,4 2006.183.08:28:30.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.183.08:28:30.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.183.08:28:30.98#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:30.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:31.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:31.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:31.04#ibcon#enter wrdev, iclass 7, count 2 2006.183.08:28:31.04#ibcon#first serial, iclass 7, count 2 2006.183.08:28:31.04#ibcon#enter sib2, iclass 7, count 2 2006.183.08:28:31.04#ibcon#flushed, iclass 7, count 2 2006.183.08:28:31.04#ibcon#about to write, iclass 7, count 2 2006.183.08:28:31.04#ibcon#wrote, iclass 7, count 2 2006.183.08:28:31.04#ibcon#about to read 3, iclass 7, count 2 2006.183.08:28:31.06#ibcon#read 3, iclass 7, count 2 2006.183.08:28:31.06#ibcon#about to read 4, iclass 7, count 2 2006.183.08:28:31.06#ibcon#read 4, iclass 7, count 2 2006.183.08:28:31.06#ibcon#about to read 5, iclass 7, count 2 2006.183.08:28:31.06#ibcon#read 5, iclass 7, count 2 2006.183.08:28:31.06#ibcon#about to read 6, iclass 7, count 2 2006.183.08:28:31.06#ibcon#read 6, iclass 7, count 2 2006.183.08:28:31.06#ibcon#end of sib2, iclass 7, count 2 2006.183.08:28:31.06#ibcon#*mode == 0, iclass 7, count 2 2006.183.08:28:31.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.183.08:28:31.06#ibcon#[27=AT02-04\r\n] 2006.183.08:28:31.06#ibcon#*before write, iclass 7, count 2 2006.183.08:28:31.06#ibcon#enter sib2, iclass 7, count 2 2006.183.08:28:31.06#ibcon#flushed, iclass 7, count 2 2006.183.08:28:31.06#ibcon#about to write, iclass 7, count 2 2006.183.08:28:31.06#ibcon#wrote, iclass 7, count 2 2006.183.08:28:31.06#ibcon#about to read 3, iclass 7, count 2 2006.183.08:28:31.09#ibcon#read 3, iclass 7, count 2 2006.183.08:28:31.09#ibcon#about to read 4, iclass 7, count 2 2006.183.08:28:31.09#ibcon#read 4, iclass 7, count 2 2006.183.08:28:31.09#ibcon#about to read 5, iclass 7, count 2 2006.183.08:28:31.09#ibcon#read 5, iclass 7, count 2 2006.183.08:28:31.09#ibcon#about to read 6, iclass 7, count 2 2006.183.08:28:31.09#ibcon#read 6, iclass 7, count 2 2006.183.08:28:31.09#ibcon#end of sib2, iclass 7, count 2 2006.183.08:28:31.09#ibcon#*after write, iclass 7, count 2 2006.183.08:28:31.09#ibcon#*before return 0, iclass 7, count 2 2006.183.08:28:31.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:31.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.183.08:28:31.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.183.08:28:31.09#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:31.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:31.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:31.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:31.21#ibcon#enter wrdev, iclass 7, count 0 2006.183.08:28:31.21#ibcon#first serial, iclass 7, count 0 2006.183.08:28:31.21#ibcon#enter sib2, iclass 7, count 0 2006.183.08:28:31.21#ibcon#flushed, iclass 7, count 0 2006.183.08:28:31.21#ibcon#about to write, iclass 7, count 0 2006.183.08:28:31.21#ibcon#wrote, iclass 7, count 0 2006.183.08:28:31.21#ibcon#about to read 3, iclass 7, count 0 2006.183.08:28:31.23#ibcon#read 3, iclass 7, count 0 2006.183.08:28:31.23#ibcon#about to read 4, iclass 7, count 0 2006.183.08:28:31.23#ibcon#read 4, iclass 7, count 0 2006.183.08:28:31.23#ibcon#about to read 5, iclass 7, count 0 2006.183.08:28:31.23#ibcon#read 5, iclass 7, count 0 2006.183.08:28:31.23#ibcon#about to read 6, iclass 7, count 0 2006.183.08:28:31.23#ibcon#read 6, iclass 7, count 0 2006.183.08:28:31.23#ibcon#end of sib2, iclass 7, count 0 2006.183.08:28:31.23#ibcon#*mode == 0, iclass 7, count 0 2006.183.08:28:31.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.183.08:28:31.23#ibcon#[27=USB\r\n] 2006.183.08:28:31.23#ibcon#*before write, iclass 7, count 0 2006.183.08:28:31.23#ibcon#enter sib2, iclass 7, count 0 2006.183.08:28:31.23#ibcon#flushed, iclass 7, count 0 2006.183.08:28:31.23#ibcon#about to write, iclass 7, count 0 2006.183.08:28:31.23#ibcon#wrote, iclass 7, count 0 2006.183.08:28:31.23#ibcon#about to read 3, iclass 7, count 0 2006.183.08:28:31.26#ibcon#read 3, iclass 7, count 0 2006.183.08:28:31.26#ibcon#about to read 4, iclass 7, count 0 2006.183.08:28:31.26#ibcon#read 4, iclass 7, count 0 2006.183.08:28:31.26#ibcon#about to read 5, iclass 7, count 0 2006.183.08:28:31.26#ibcon#read 5, iclass 7, count 0 2006.183.08:28:31.26#ibcon#about to read 6, iclass 7, count 0 2006.183.08:28:31.26#ibcon#read 6, iclass 7, count 0 2006.183.08:28:31.26#ibcon#end of sib2, iclass 7, count 0 2006.183.08:28:31.26#ibcon#*after write, iclass 7, count 0 2006.183.08:28:31.26#ibcon#*before return 0, iclass 7, count 0 2006.183.08:28:31.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:31.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.183.08:28:31.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.183.08:28:31.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.183.08:28:31.26$vc4f8/vblo=3,656.99 2006.183.08:28:31.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.183.08:28:31.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.183.08:28:31.26#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:31.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:31.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:31.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:31.26#ibcon#enter wrdev, iclass 11, count 0 2006.183.08:28:31.26#ibcon#first serial, iclass 11, count 0 2006.183.08:28:31.26#ibcon#enter sib2, iclass 11, count 0 2006.183.08:28:31.26#ibcon#flushed, iclass 11, count 0 2006.183.08:28:31.26#ibcon#about to write, iclass 11, count 0 2006.183.08:28:31.26#ibcon#wrote, iclass 11, count 0 2006.183.08:28:31.26#ibcon#about to read 3, iclass 11, count 0 2006.183.08:28:31.28#ibcon#read 3, iclass 11, count 0 2006.183.08:28:31.28#ibcon#about to read 4, iclass 11, count 0 2006.183.08:28:31.28#ibcon#read 4, iclass 11, count 0 2006.183.08:28:31.28#ibcon#about to read 5, iclass 11, count 0 2006.183.08:28:31.28#ibcon#read 5, iclass 11, count 0 2006.183.08:28:31.28#ibcon#about to read 6, iclass 11, count 0 2006.183.08:28:31.28#ibcon#read 6, iclass 11, count 0 2006.183.08:28:31.28#ibcon#end of sib2, iclass 11, count 0 2006.183.08:28:31.28#ibcon#*mode == 0, iclass 11, count 0 2006.183.08:28:31.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.183.08:28:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.183.08:28:31.28#ibcon#*before write, iclass 11, count 0 2006.183.08:28:31.28#ibcon#enter sib2, iclass 11, count 0 2006.183.08:28:31.28#ibcon#flushed, iclass 11, count 0 2006.183.08:28:31.28#ibcon#about to write, iclass 11, count 0 2006.183.08:28:31.28#ibcon#wrote, iclass 11, count 0 2006.183.08:28:31.28#ibcon#about to read 3, iclass 11, count 0 2006.183.08:28:31.32#ibcon#read 3, iclass 11, count 0 2006.183.08:28:31.32#ibcon#about to read 4, iclass 11, count 0 2006.183.08:28:31.32#ibcon#read 4, iclass 11, count 0 2006.183.08:28:31.32#ibcon#about to read 5, iclass 11, count 0 2006.183.08:28:31.32#ibcon#read 5, iclass 11, count 0 2006.183.08:28:31.32#ibcon#about to read 6, iclass 11, count 0 2006.183.08:28:31.32#ibcon#read 6, iclass 11, count 0 2006.183.08:28:31.32#ibcon#end of sib2, iclass 11, count 0 2006.183.08:28:31.32#ibcon#*after write, iclass 11, count 0 2006.183.08:28:31.32#ibcon#*before return 0, iclass 11, count 0 2006.183.08:28:31.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:31.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.183.08:28:31.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.183.08:28:31.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.183.08:28:31.32$vc4f8/vb=3,4 2006.183.08:28:31.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.183.08:28:31.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.183.08:28:31.32#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:31.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:31.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:31.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:31.38#ibcon#enter wrdev, iclass 13, count 2 2006.183.08:28:31.38#ibcon#first serial, iclass 13, count 2 2006.183.08:28:31.38#ibcon#enter sib2, iclass 13, count 2 2006.183.08:28:31.38#ibcon#flushed, iclass 13, count 2 2006.183.08:28:31.38#ibcon#about to write, iclass 13, count 2 2006.183.08:28:31.38#ibcon#wrote, iclass 13, count 2 2006.183.08:28:31.38#ibcon#about to read 3, iclass 13, count 2 2006.183.08:28:31.40#ibcon#read 3, iclass 13, count 2 2006.183.08:28:31.40#ibcon#about to read 4, iclass 13, count 2 2006.183.08:28:31.40#ibcon#read 4, iclass 13, count 2 2006.183.08:28:31.40#ibcon#about to read 5, iclass 13, count 2 2006.183.08:28:31.40#ibcon#read 5, iclass 13, count 2 2006.183.08:28:31.40#ibcon#about to read 6, iclass 13, count 2 2006.183.08:28:31.40#ibcon#read 6, iclass 13, count 2 2006.183.08:28:31.40#ibcon#end of sib2, iclass 13, count 2 2006.183.08:28:31.40#ibcon#*mode == 0, iclass 13, count 2 2006.183.08:28:31.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.183.08:28:31.40#ibcon#[27=AT03-04\r\n] 2006.183.08:28:31.40#ibcon#*before write, iclass 13, count 2 2006.183.08:28:31.40#ibcon#enter sib2, iclass 13, count 2 2006.183.08:28:31.40#ibcon#flushed, iclass 13, count 2 2006.183.08:28:31.40#ibcon#about to write, iclass 13, count 2 2006.183.08:28:31.40#ibcon#wrote, iclass 13, count 2 2006.183.08:28:31.40#ibcon#about to read 3, iclass 13, count 2 2006.183.08:28:31.43#ibcon#read 3, iclass 13, count 2 2006.183.08:28:31.43#ibcon#about to read 4, iclass 13, count 2 2006.183.08:28:31.43#ibcon#read 4, iclass 13, count 2 2006.183.08:28:31.43#ibcon#about to read 5, iclass 13, count 2 2006.183.08:28:31.43#ibcon#read 5, iclass 13, count 2 2006.183.08:28:31.43#ibcon#about to read 6, iclass 13, count 2 2006.183.08:28:31.43#ibcon#read 6, iclass 13, count 2 2006.183.08:28:31.43#ibcon#end of sib2, iclass 13, count 2 2006.183.08:28:31.43#ibcon#*after write, iclass 13, count 2 2006.183.08:28:31.43#ibcon#*before return 0, iclass 13, count 2 2006.183.08:28:31.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:31.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.183.08:28:31.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.183.08:28:31.43#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:31.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:31.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:31.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:31.55#ibcon#enter wrdev, iclass 13, count 0 2006.183.08:28:31.55#ibcon#first serial, iclass 13, count 0 2006.183.08:28:31.55#ibcon#enter sib2, iclass 13, count 0 2006.183.08:28:31.55#ibcon#flushed, iclass 13, count 0 2006.183.08:28:31.55#ibcon#about to write, iclass 13, count 0 2006.183.08:28:31.55#ibcon#wrote, iclass 13, count 0 2006.183.08:28:31.55#ibcon#about to read 3, iclass 13, count 0 2006.183.08:28:31.57#ibcon#read 3, iclass 13, count 0 2006.183.08:28:31.57#ibcon#about to read 4, iclass 13, count 0 2006.183.08:28:31.57#ibcon#read 4, iclass 13, count 0 2006.183.08:28:31.57#ibcon#about to read 5, iclass 13, count 0 2006.183.08:28:31.57#ibcon#read 5, iclass 13, count 0 2006.183.08:28:31.57#ibcon#about to read 6, iclass 13, count 0 2006.183.08:28:31.57#ibcon#read 6, iclass 13, count 0 2006.183.08:28:31.57#ibcon#end of sib2, iclass 13, count 0 2006.183.08:28:31.57#ibcon#*mode == 0, iclass 13, count 0 2006.183.08:28:31.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.183.08:28:31.57#ibcon#[27=USB\r\n] 2006.183.08:28:31.57#ibcon#*before write, iclass 13, count 0 2006.183.08:28:31.57#ibcon#enter sib2, iclass 13, count 0 2006.183.08:28:31.57#ibcon#flushed, iclass 13, count 0 2006.183.08:28:31.57#ibcon#about to write, iclass 13, count 0 2006.183.08:28:31.57#ibcon#wrote, iclass 13, count 0 2006.183.08:28:31.57#ibcon#about to read 3, iclass 13, count 0 2006.183.08:28:31.60#ibcon#read 3, iclass 13, count 0 2006.183.08:28:31.60#ibcon#about to read 4, iclass 13, count 0 2006.183.08:28:31.60#ibcon#read 4, iclass 13, count 0 2006.183.08:28:31.60#ibcon#about to read 5, iclass 13, count 0 2006.183.08:28:31.60#ibcon#read 5, iclass 13, count 0 2006.183.08:28:31.60#ibcon#about to read 6, iclass 13, count 0 2006.183.08:28:31.60#ibcon#read 6, iclass 13, count 0 2006.183.08:28:31.60#ibcon#end of sib2, iclass 13, count 0 2006.183.08:28:31.60#ibcon#*after write, iclass 13, count 0 2006.183.08:28:31.60#ibcon#*before return 0, iclass 13, count 0 2006.183.08:28:31.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:31.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.183.08:28:31.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.183.08:28:31.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.183.08:28:31.60$vc4f8/vblo=4,712.99 2006.183.08:28:31.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.183.08:28:31.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.183.08:28:31.60#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:31.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:31.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:31.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:31.60#ibcon#enter wrdev, iclass 15, count 0 2006.183.08:28:31.60#ibcon#first serial, iclass 15, count 0 2006.183.08:28:31.60#ibcon#enter sib2, iclass 15, count 0 2006.183.08:28:31.60#ibcon#flushed, iclass 15, count 0 2006.183.08:28:31.60#ibcon#about to write, iclass 15, count 0 2006.183.08:28:31.60#ibcon#wrote, iclass 15, count 0 2006.183.08:28:31.60#ibcon#about to read 3, iclass 15, count 0 2006.183.08:28:31.62#ibcon#read 3, iclass 15, count 0 2006.183.08:28:31.62#ibcon#about to read 4, iclass 15, count 0 2006.183.08:28:31.62#ibcon#read 4, iclass 15, count 0 2006.183.08:28:31.62#ibcon#about to read 5, iclass 15, count 0 2006.183.08:28:31.62#ibcon#read 5, iclass 15, count 0 2006.183.08:28:31.62#ibcon#about to read 6, iclass 15, count 0 2006.183.08:28:31.62#ibcon#read 6, iclass 15, count 0 2006.183.08:28:31.62#ibcon#end of sib2, iclass 15, count 0 2006.183.08:28:31.62#ibcon#*mode == 0, iclass 15, count 0 2006.183.08:28:31.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.183.08:28:31.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.183.08:28:31.62#ibcon#*before write, iclass 15, count 0 2006.183.08:28:31.62#ibcon#enter sib2, iclass 15, count 0 2006.183.08:28:31.62#ibcon#flushed, iclass 15, count 0 2006.183.08:28:31.62#ibcon#about to write, iclass 15, count 0 2006.183.08:28:31.62#ibcon#wrote, iclass 15, count 0 2006.183.08:28:31.62#ibcon#about to read 3, iclass 15, count 0 2006.183.08:28:31.66#ibcon#read 3, iclass 15, count 0 2006.183.08:28:31.66#ibcon#about to read 4, iclass 15, count 0 2006.183.08:28:31.66#ibcon#read 4, iclass 15, count 0 2006.183.08:28:31.66#ibcon#about to read 5, iclass 15, count 0 2006.183.08:28:31.66#ibcon#read 5, iclass 15, count 0 2006.183.08:28:31.66#ibcon#about to read 6, iclass 15, count 0 2006.183.08:28:31.66#ibcon#read 6, iclass 15, count 0 2006.183.08:28:31.66#ibcon#end of sib2, iclass 15, count 0 2006.183.08:28:31.66#ibcon#*after write, iclass 15, count 0 2006.183.08:28:31.66#ibcon#*before return 0, iclass 15, count 0 2006.183.08:28:31.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:31.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.183.08:28:31.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.183.08:28:31.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.183.08:28:31.66$vc4f8/vb=4,4 2006.183.08:28:31.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.183.08:28:31.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.183.08:28:31.66#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:31.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:31.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:31.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:31.72#ibcon#enter wrdev, iclass 17, count 2 2006.183.08:28:31.72#ibcon#first serial, iclass 17, count 2 2006.183.08:28:31.72#ibcon#enter sib2, iclass 17, count 2 2006.183.08:28:31.72#ibcon#flushed, iclass 17, count 2 2006.183.08:28:31.72#ibcon#about to write, iclass 17, count 2 2006.183.08:28:31.72#ibcon#wrote, iclass 17, count 2 2006.183.08:28:31.72#ibcon#about to read 3, iclass 17, count 2 2006.183.08:28:31.74#ibcon#read 3, iclass 17, count 2 2006.183.08:28:31.74#ibcon#about to read 4, iclass 17, count 2 2006.183.08:28:31.74#ibcon#read 4, iclass 17, count 2 2006.183.08:28:31.74#ibcon#about to read 5, iclass 17, count 2 2006.183.08:28:31.74#ibcon#read 5, iclass 17, count 2 2006.183.08:28:31.74#ibcon#about to read 6, iclass 17, count 2 2006.183.08:28:31.74#ibcon#read 6, iclass 17, count 2 2006.183.08:28:31.74#ibcon#end of sib2, iclass 17, count 2 2006.183.08:28:31.74#ibcon#*mode == 0, iclass 17, count 2 2006.183.08:28:31.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.183.08:28:31.74#ibcon#[27=AT04-04\r\n] 2006.183.08:28:31.74#ibcon#*before write, iclass 17, count 2 2006.183.08:28:31.74#ibcon#enter sib2, iclass 17, count 2 2006.183.08:28:31.74#ibcon#flushed, iclass 17, count 2 2006.183.08:28:31.74#ibcon#about to write, iclass 17, count 2 2006.183.08:28:31.74#ibcon#wrote, iclass 17, count 2 2006.183.08:28:31.74#ibcon#about to read 3, iclass 17, count 2 2006.183.08:28:31.77#ibcon#read 3, iclass 17, count 2 2006.183.08:28:31.77#ibcon#about to read 4, iclass 17, count 2 2006.183.08:28:31.77#ibcon#read 4, iclass 17, count 2 2006.183.08:28:31.77#ibcon#about to read 5, iclass 17, count 2 2006.183.08:28:31.77#ibcon#read 5, iclass 17, count 2 2006.183.08:28:31.77#ibcon#about to read 6, iclass 17, count 2 2006.183.08:28:31.77#ibcon#read 6, iclass 17, count 2 2006.183.08:28:31.77#ibcon#end of sib2, iclass 17, count 2 2006.183.08:28:31.77#ibcon#*after write, iclass 17, count 2 2006.183.08:28:31.77#ibcon#*before return 0, iclass 17, count 2 2006.183.08:28:31.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:31.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.183.08:28:31.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.183.08:28:31.77#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:31.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:31.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:31.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:31.89#ibcon#enter wrdev, iclass 17, count 0 2006.183.08:28:31.89#ibcon#first serial, iclass 17, count 0 2006.183.08:28:31.89#ibcon#enter sib2, iclass 17, count 0 2006.183.08:28:31.89#ibcon#flushed, iclass 17, count 0 2006.183.08:28:31.89#ibcon#about to write, iclass 17, count 0 2006.183.08:28:31.89#ibcon#wrote, iclass 17, count 0 2006.183.08:28:31.89#ibcon#about to read 3, iclass 17, count 0 2006.183.08:28:31.91#ibcon#read 3, iclass 17, count 0 2006.183.08:28:31.91#ibcon#about to read 4, iclass 17, count 0 2006.183.08:28:31.91#ibcon#read 4, iclass 17, count 0 2006.183.08:28:31.91#ibcon#about to read 5, iclass 17, count 0 2006.183.08:28:31.91#ibcon#read 5, iclass 17, count 0 2006.183.08:28:31.91#ibcon#about to read 6, iclass 17, count 0 2006.183.08:28:31.91#ibcon#read 6, iclass 17, count 0 2006.183.08:28:31.91#ibcon#end of sib2, iclass 17, count 0 2006.183.08:28:31.91#ibcon#*mode == 0, iclass 17, count 0 2006.183.08:28:31.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.183.08:28:31.91#ibcon#[27=USB\r\n] 2006.183.08:28:31.91#ibcon#*before write, iclass 17, count 0 2006.183.08:28:31.91#ibcon#enter sib2, iclass 17, count 0 2006.183.08:28:31.91#ibcon#flushed, iclass 17, count 0 2006.183.08:28:31.91#ibcon#about to write, iclass 17, count 0 2006.183.08:28:31.91#ibcon#wrote, iclass 17, count 0 2006.183.08:28:31.91#ibcon#about to read 3, iclass 17, count 0 2006.183.08:28:31.94#ibcon#read 3, iclass 17, count 0 2006.183.08:28:31.94#ibcon#about to read 4, iclass 17, count 0 2006.183.08:28:31.94#ibcon#read 4, iclass 17, count 0 2006.183.08:28:31.94#ibcon#about to read 5, iclass 17, count 0 2006.183.08:28:31.94#ibcon#read 5, iclass 17, count 0 2006.183.08:28:31.94#ibcon#about to read 6, iclass 17, count 0 2006.183.08:28:31.94#ibcon#read 6, iclass 17, count 0 2006.183.08:28:31.94#ibcon#end of sib2, iclass 17, count 0 2006.183.08:28:31.94#ibcon#*after write, iclass 17, count 0 2006.183.08:28:31.94#ibcon#*before return 0, iclass 17, count 0 2006.183.08:28:31.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:31.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.183.08:28:31.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.183.08:28:31.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.183.08:28:31.94$vc4f8/vblo=5,744.99 2006.183.08:28:31.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.183.08:28:31.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.183.08:28:31.94#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:31.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:31.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:31.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:31.94#ibcon#enter wrdev, iclass 19, count 0 2006.183.08:28:31.94#ibcon#first serial, iclass 19, count 0 2006.183.08:28:31.94#ibcon#enter sib2, iclass 19, count 0 2006.183.08:28:31.94#ibcon#flushed, iclass 19, count 0 2006.183.08:28:31.94#ibcon#about to write, iclass 19, count 0 2006.183.08:28:31.94#ibcon#wrote, iclass 19, count 0 2006.183.08:28:31.94#ibcon#about to read 3, iclass 19, count 0 2006.183.08:28:31.96#ibcon#read 3, iclass 19, count 0 2006.183.08:28:31.96#ibcon#about to read 4, iclass 19, count 0 2006.183.08:28:31.96#ibcon#read 4, iclass 19, count 0 2006.183.08:28:31.96#ibcon#about to read 5, iclass 19, count 0 2006.183.08:28:31.96#ibcon#read 5, iclass 19, count 0 2006.183.08:28:31.96#ibcon#about to read 6, iclass 19, count 0 2006.183.08:28:31.96#ibcon#read 6, iclass 19, count 0 2006.183.08:28:31.96#ibcon#end of sib2, iclass 19, count 0 2006.183.08:28:31.96#ibcon#*mode == 0, iclass 19, count 0 2006.183.08:28:31.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.183.08:28:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.183.08:28:31.96#ibcon#*before write, iclass 19, count 0 2006.183.08:28:31.96#ibcon#enter sib2, iclass 19, count 0 2006.183.08:28:31.96#ibcon#flushed, iclass 19, count 0 2006.183.08:28:31.96#ibcon#about to write, iclass 19, count 0 2006.183.08:28:31.96#ibcon#wrote, iclass 19, count 0 2006.183.08:28:31.96#ibcon#about to read 3, iclass 19, count 0 2006.183.08:28:32.00#ibcon#read 3, iclass 19, count 0 2006.183.08:28:32.00#ibcon#about to read 4, iclass 19, count 0 2006.183.08:28:32.00#ibcon#read 4, iclass 19, count 0 2006.183.08:28:32.00#ibcon#about to read 5, iclass 19, count 0 2006.183.08:28:32.00#ibcon#read 5, iclass 19, count 0 2006.183.08:28:32.00#ibcon#about to read 6, iclass 19, count 0 2006.183.08:28:32.00#ibcon#read 6, iclass 19, count 0 2006.183.08:28:32.00#ibcon#end of sib2, iclass 19, count 0 2006.183.08:28:32.00#ibcon#*after write, iclass 19, count 0 2006.183.08:28:32.00#ibcon#*before return 0, iclass 19, count 0 2006.183.08:28:32.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:32.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.183.08:28:32.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.183.08:28:32.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.183.08:28:32.00$vc4f8/vb=5,4 2006.183.08:28:32.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.183.08:28:32.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.183.08:28:32.00#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:32.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:32.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:32.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:32.06#ibcon#enter wrdev, iclass 21, count 2 2006.183.08:28:32.06#ibcon#first serial, iclass 21, count 2 2006.183.08:28:32.06#ibcon#enter sib2, iclass 21, count 2 2006.183.08:28:32.06#ibcon#flushed, iclass 21, count 2 2006.183.08:28:32.06#ibcon#about to write, iclass 21, count 2 2006.183.08:28:32.06#ibcon#wrote, iclass 21, count 2 2006.183.08:28:32.06#ibcon#about to read 3, iclass 21, count 2 2006.183.08:28:32.08#ibcon#read 3, iclass 21, count 2 2006.183.08:28:32.08#ibcon#about to read 4, iclass 21, count 2 2006.183.08:28:32.08#ibcon#read 4, iclass 21, count 2 2006.183.08:28:32.08#ibcon#about to read 5, iclass 21, count 2 2006.183.08:28:32.08#ibcon#read 5, iclass 21, count 2 2006.183.08:28:32.08#ibcon#about to read 6, iclass 21, count 2 2006.183.08:28:32.08#ibcon#read 6, iclass 21, count 2 2006.183.08:28:32.08#ibcon#end of sib2, iclass 21, count 2 2006.183.08:28:32.08#ibcon#*mode == 0, iclass 21, count 2 2006.183.08:28:32.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.183.08:28:32.08#ibcon#[27=AT05-04\r\n] 2006.183.08:28:32.08#ibcon#*before write, iclass 21, count 2 2006.183.08:28:32.08#ibcon#enter sib2, iclass 21, count 2 2006.183.08:28:32.08#ibcon#flushed, iclass 21, count 2 2006.183.08:28:32.08#ibcon#about to write, iclass 21, count 2 2006.183.08:28:32.08#ibcon#wrote, iclass 21, count 2 2006.183.08:28:32.08#ibcon#about to read 3, iclass 21, count 2 2006.183.08:28:32.11#ibcon#read 3, iclass 21, count 2 2006.183.08:28:32.11#ibcon#about to read 4, iclass 21, count 2 2006.183.08:28:32.11#ibcon#read 4, iclass 21, count 2 2006.183.08:28:32.11#ibcon#about to read 5, iclass 21, count 2 2006.183.08:28:32.11#ibcon#read 5, iclass 21, count 2 2006.183.08:28:32.11#ibcon#about to read 6, iclass 21, count 2 2006.183.08:28:32.11#ibcon#read 6, iclass 21, count 2 2006.183.08:28:32.11#ibcon#end of sib2, iclass 21, count 2 2006.183.08:28:32.11#ibcon#*after write, iclass 21, count 2 2006.183.08:28:32.11#ibcon#*before return 0, iclass 21, count 2 2006.183.08:28:32.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:32.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.183.08:28:32.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.183.08:28:32.11#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:32.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:32.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:32.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:32.23#ibcon#enter wrdev, iclass 21, count 0 2006.183.08:28:32.23#ibcon#first serial, iclass 21, count 0 2006.183.08:28:32.23#ibcon#enter sib2, iclass 21, count 0 2006.183.08:28:32.23#ibcon#flushed, iclass 21, count 0 2006.183.08:28:32.23#ibcon#about to write, iclass 21, count 0 2006.183.08:28:32.23#ibcon#wrote, iclass 21, count 0 2006.183.08:28:32.23#ibcon#about to read 3, iclass 21, count 0 2006.183.08:28:32.25#ibcon#read 3, iclass 21, count 0 2006.183.08:28:32.25#ibcon#about to read 4, iclass 21, count 0 2006.183.08:28:32.25#ibcon#read 4, iclass 21, count 0 2006.183.08:28:32.25#ibcon#about to read 5, iclass 21, count 0 2006.183.08:28:32.25#ibcon#read 5, iclass 21, count 0 2006.183.08:28:32.25#ibcon#about to read 6, iclass 21, count 0 2006.183.08:28:32.25#ibcon#read 6, iclass 21, count 0 2006.183.08:28:32.25#ibcon#end of sib2, iclass 21, count 0 2006.183.08:28:32.25#ibcon#*mode == 0, iclass 21, count 0 2006.183.08:28:32.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.183.08:28:32.25#ibcon#[27=USB\r\n] 2006.183.08:28:32.25#ibcon#*before write, iclass 21, count 0 2006.183.08:28:32.25#ibcon#enter sib2, iclass 21, count 0 2006.183.08:28:32.25#ibcon#flushed, iclass 21, count 0 2006.183.08:28:32.25#ibcon#about to write, iclass 21, count 0 2006.183.08:28:32.25#ibcon#wrote, iclass 21, count 0 2006.183.08:28:32.25#ibcon#about to read 3, iclass 21, count 0 2006.183.08:28:32.28#ibcon#read 3, iclass 21, count 0 2006.183.08:28:32.28#ibcon#about to read 4, iclass 21, count 0 2006.183.08:28:32.28#ibcon#read 4, iclass 21, count 0 2006.183.08:28:32.28#ibcon#about to read 5, iclass 21, count 0 2006.183.08:28:32.28#ibcon#read 5, iclass 21, count 0 2006.183.08:28:32.28#ibcon#about to read 6, iclass 21, count 0 2006.183.08:28:32.28#ibcon#read 6, iclass 21, count 0 2006.183.08:28:32.28#ibcon#end of sib2, iclass 21, count 0 2006.183.08:28:32.28#ibcon#*after write, iclass 21, count 0 2006.183.08:28:32.28#ibcon#*before return 0, iclass 21, count 0 2006.183.08:28:32.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:32.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.183.08:28:32.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.183.08:28:32.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.183.08:28:32.28$vc4f8/vblo=6,752.99 2006.183.08:28:32.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.183.08:28:32.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.183.08:28:32.28#ibcon#ireg 17 cls_cnt 0 2006.183.08:28:32.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:32.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:32.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:32.28#ibcon#enter wrdev, iclass 23, count 0 2006.183.08:28:32.28#ibcon#first serial, iclass 23, count 0 2006.183.08:28:32.28#ibcon#enter sib2, iclass 23, count 0 2006.183.08:28:32.28#ibcon#flushed, iclass 23, count 0 2006.183.08:28:32.28#ibcon#about to write, iclass 23, count 0 2006.183.08:28:32.28#ibcon#wrote, iclass 23, count 0 2006.183.08:28:32.28#ibcon#about to read 3, iclass 23, count 0 2006.183.08:28:32.30#ibcon#read 3, iclass 23, count 0 2006.183.08:28:32.30#ibcon#about to read 4, iclass 23, count 0 2006.183.08:28:32.30#ibcon#read 4, iclass 23, count 0 2006.183.08:28:32.30#ibcon#about to read 5, iclass 23, count 0 2006.183.08:28:32.30#ibcon#read 5, iclass 23, count 0 2006.183.08:28:32.30#ibcon#about to read 6, iclass 23, count 0 2006.183.08:28:32.30#ibcon#read 6, iclass 23, count 0 2006.183.08:28:32.30#ibcon#end of sib2, iclass 23, count 0 2006.183.08:28:32.30#ibcon#*mode == 0, iclass 23, count 0 2006.183.08:28:32.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.183.08:28:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.183.08:28:32.30#ibcon#*before write, iclass 23, count 0 2006.183.08:28:32.30#ibcon#enter sib2, iclass 23, count 0 2006.183.08:28:32.30#ibcon#flushed, iclass 23, count 0 2006.183.08:28:32.30#ibcon#about to write, iclass 23, count 0 2006.183.08:28:32.30#ibcon#wrote, iclass 23, count 0 2006.183.08:28:32.30#ibcon#about to read 3, iclass 23, count 0 2006.183.08:28:32.34#ibcon#read 3, iclass 23, count 0 2006.183.08:28:32.34#ibcon#about to read 4, iclass 23, count 0 2006.183.08:28:32.34#ibcon#read 4, iclass 23, count 0 2006.183.08:28:32.34#ibcon#about to read 5, iclass 23, count 0 2006.183.08:28:32.34#ibcon#read 5, iclass 23, count 0 2006.183.08:28:32.34#ibcon#about to read 6, iclass 23, count 0 2006.183.08:28:32.34#ibcon#read 6, iclass 23, count 0 2006.183.08:28:32.34#ibcon#end of sib2, iclass 23, count 0 2006.183.08:28:32.34#ibcon#*after write, iclass 23, count 0 2006.183.08:28:32.34#ibcon#*before return 0, iclass 23, count 0 2006.183.08:28:32.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:32.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.183.08:28:32.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.183.08:28:32.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.183.08:28:32.34$vc4f8/vb=6,4 2006.183.08:28:32.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.183.08:28:32.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.183.08:28:32.34#ibcon#ireg 11 cls_cnt 2 2006.183.08:28:32.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:32.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:32.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:32.40#ibcon#enter wrdev, iclass 25, count 2 2006.183.08:28:32.40#ibcon#first serial, iclass 25, count 2 2006.183.08:28:32.40#ibcon#enter sib2, iclass 25, count 2 2006.183.08:28:32.40#ibcon#flushed, iclass 25, count 2 2006.183.08:28:32.40#ibcon#about to write, iclass 25, count 2 2006.183.08:28:32.40#ibcon#wrote, iclass 25, count 2 2006.183.08:28:32.40#ibcon#about to read 3, iclass 25, count 2 2006.183.08:28:32.42#ibcon#read 3, iclass 25, count 2 2006.183.08:28:32.42#ibcon#about to read 4, iclass 25, count 2 2006.183.08:28:32.42#ibcon#read 4, iclass 25, count 2 2006.183.08:28:32.42#ibcon#about to read 5, iclass 25, count 2 2006.183.08:28:32.42#ibcon#read 5, iclass 25, count 2 2006.183.08:28:32.42#ibcon#about to read 6, iclass 25, count 2 2006.183.08:28:32.42#ibcon#read 6, iclass 25, count 2 2006.183.08:28:32.42#ibcon#end of sib2, iclass 25, count 2 2006.183.08:28:32.42#ibcon#*mode == 0, iclass 25, count 2 2006.183.08:28:32.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.183.08:28:32.42#ibcon#[27=AT06-04\r\n] 2006.183.08:28:32.42#ibcon#*before write, iclass 25, count 2 2006.183.08:28:32.42#ibcon#enter sib2, iclass 25, count 2 2006.183.08:28:32.42#ibcon#flushed, iclass 25, count 2 2006.183.08:28:32.42#ibcon#about to write, iclass 25, count 2 2006.183.08:28:32.42#ibcon#wrote, iclass 25, count 2 2006.183.08:28:32.42#ibcon#about to read 3, iclass 25, count 2 2006.183.08:28:32.45#ibcon#read 3, iclass 25, count 2 2006.183.08:28:32.45#ibcon#about to read 4, iclass 25, count 2 2006.183.08:28:32.45#ibcon#read 4, iclass 25, count 2 2006.183.08:28:32.45#ibcon#about to read 5, iclass 25, count 2 2006.183.08:28:32.45#ibcon#read 5, iclass 25, count 2 2006.183.08:28:32.45#ibcon#about to read 6, iclass 25, count 2 2006.183.08:28:32.45#ibcon#read 6, iclass 25, count 2 2006.183.08:28:32.45#ibcon#end of sib2, iclass 25, count 2 2006.183.08:28:32.45#ibcon#*after write, iclass 25, count 2 2006.183.08:28:32.45#ibcon#*before return 0, iclass 25, count 2 2006.183.08:28:32.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:32.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.183.08:28:32.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.183.08:28:32.45#ibcon#ireg 7 cls_cnt 0 2006.183.08:28:32.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:32.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:32.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:32.57#ibcon#enter wrdev, iclass 25, count 0 2006.183.08:28:32.57#ibcon#first serial, iclass 25, count 0 2006.183.08:28:32.57#ibcon#enter sib2, iclass 25, count 0 2006.183.08:28:32.57#ibcon#flushed, iclass 25, count 0 2006.183.08:28:32.57#ibcon#about to write, iclass 25, count 0 2006.183.08:28:32.57#ibcon#wrote, iclass 25, count 0 2006.183.08:28:32.57#ibcon#about to read 3, iclass 25, count 0 2006.183.08:28:32.59#ibcon#read 3, iclass 25, count 0 2006.183.08:28:32.59#ibcon#about to read 4, iclass 25, count 0 2006.183.08:28:32.59#ibcon#read 4, iclass 25, count 0 2006.183.08:28:32.59#ibcon#about to read 5, iclass 25, count 0 2006.183.08:28:32.59#ibcon#read 5, iclass 25, count 0 2006.183.08:28:32.59#ibcon#about to read 6, iclass 25, count 0 2006.183.08:28:32.59#ibcon#read 6, iclass 25, count 0 2006.183.08:28:32.59#ibcon#end of sib2, iclass 25, count 0 2006.183.08:28:32.59#ibcon#*mode == 0, iclass 25, count 0 2006.183.08:28:32.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.183.08:28:32.59#ibcon#[27=USB\r\n] 2006.183.08:28:32.59#ibcon#*before write, iclass 25, count 0 2006.183.08:28:32.59#ibcon#enter sib2, iclass 25, count 0 2006.183.08:28:32.59#ibcon#flushed, iclass 25, count 0 2006.183.08:28:32.59#ibcon#about to write, iclass 25, count 0 2006.183.08:28:32.59#ibcon#wrote, iclass 25, count 0 2006.183.08:28:32.59#ibcon#about to read 3, iclass 25, count 0 2006.183.08:28:32.62#ibcon#read 3, iclass 25, count 0 2006.183.08:28:32.62#ibcon#about to read 4, iclass 25, count 0 2006.183.08:28:32.62#ibcon#read 4, iclass 25, count 0 2006.183.08:28:32.62#ibcon#about to read 5, iclass 25, count 0 2006.183.08:28:32.62#ibcon#read 5, iclass 25, count 0 2006.183.08:28:32.62#ibcon#about to read 6, iclass 25, count 0 2006.183.08:28:32.62#ibcon#read 6, iclass 25, count 0 2006.183.08:28:32.62#ibcon#end of sib2, iclass 25, count 0 2006.183.08:28:32.62#ibcon#*after write, iclass 25, count 0 2006.183.08:28:32.62#ibcon#*before return 0, iclass 25, count 0 2006.183.08:28:32.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:32.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.183.08:28:32.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.183.08:28:32.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.183.08:28:32.62$vc4f8/vabw=wide 2006.183.08:28:32.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.183.08:28:32.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.183.08:28:32.62#ibcon#ireg 8 cls_cnt 0 2006.183.08:28:32.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:32.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:32.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:32.62#ibcon#enter wrdev, iclass 27, count 0 2006.183.08:28:32.62#ibcon#first serial, iclass 27, count 0 2006.183.08:28:32.62#ibcon#enter sib2, iclass 27, count 0 2006.183.08:28:32.62#ibcon#flushed, iclass 27, count 0 2006.183.08:28:32.62#ibcon#about to write, iclass 27, count 0 2006.183.08:28:32.62#ibcon#wrote, iclass 27, count 0 2006.183.08:28:32.62#ibcon#about to read 3, iclass 27, count 0 2006.183.08:28:32.64#ibcon#read 3, iclass 27, count 0 2006.183.08:28:32.64#ibcon#about to read 4, iclass 27, count 0 2006.183.08:28:32.64#ibcon#read 4, iclass 27, count 0 2006.183.08:28:32.64#ibcon#about to read 5, iclass 27, count 0 2006.183.08:28:32.64#ibcon#read 5, iclass 27, count 0 2006.183.08:28:32.64#ibcon#about to read 6, iclass 27, count 0 2006.183.08:28:32.64#ibcon#read 6, iclass 27, count 0 2006.183.08:28:32.64#ibcon#end of sib2, iclass 27, count 0 2006.183.08:28:32.64#ibcon#*mode == 0, iclass 27, count 0 2006.183.08:28:32.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.183.08:28:32.64#ibcon#[25=BW32\r\n] 2006.183.08:28:32.64#ibcon#*before write, iclass 27, count 0 2006.183.08:28:32.64#ibcon#enter sib2, iclass 27, count 0 2006.183.08:28:32.64#ibcon#flushed, iclass 27, count 0 2006.183.08:28:32.64#ibcon#about to write, iclass 27, count 0 2006.183.08:28:32.64#ibcon#wrote, iclass 27, count 0 2006.183.08:28:32.64#ibcon#about to read 3, iclass 27, count 0 2006.183.08:28:32.67#ibcon#read 3, iclass 27, count 0 2006.183.08:28:32.67#ibcon#about to read 4, iclass 27, count 0 2006.183.08:28:32.67#ibcon#read 4, iclass 27, count 0 2006.183.08:28:32.67#ibcon#about to read 5, iclass 27, count 0 2006.183.08:28:32.67#ibcon#read 5, iclass 27, count 0 2006.183.08:28:32.67#ibcon#about to read 6, iclass 27, count 0 2006.183.08:28:32.67#ibcon#read 6, iclass 27, count 0 2006.183.08:28:32.67#ibcon#end of sib2, iclass 27, count 0 2006.183.08:28:32.67#ibcon#*after write, iclass 27, count 0 2006.183.08:28:32.67#ibcon#*before return 0, iclass 27, count 0 2006.183.08:28:32.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:32.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.183.08:28:32.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.183.08:28:32.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.183.08:28:32.67$vc4f8/vbbw=wide 2006.183.08:28:32.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.183.08:28:32.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.183.08:28:32.67#ibcon#ireg 8 cls_cnt 0 2006.183.08:28:32.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:28:32.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:28:32.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:28:32.74#ibcon#enter wrdev, iclass 29, count 0 2006.183.08:28:32.74#ibcon#first serial, iclass 29, count 0 2006.183.08:28:32.74#ibcon#enter sib2, iclass 29, count 0 2006.183.08:28:32.74#ibcon#flushed, iclass 29, count 0 2006.183.08:28:32.74#ibcon#about to write, iclass 29, count 0 2006.183.08:28:32.74#ibcon#wrote, iclass 29, count 0 2006.183.08:28:32.74#ibcon#about to read 3, iclass 29, count 0 2006.183.08:28:32.76#ibcon#read 3, iclass 29, count 0 2006.183.08:28:32.76#ibcon#about to read 4, iclass 29, count 0 2006.183.08:28:32.76#ibcon#read 4, iclass 29, count 0 2006.183.08:28:32.76#ibcon#about to read 5, iclass 29, count 0 2006.183.08:28:32.76#ibcon#read 5, iclass 29, count 0 2006.183.08:28:32.76#ibcon#about to read 6, iclass 29, count 0 2006.183.08:28:32.76#ibcon#read 6, iclass 29, count 0 2006.183.08:28:32.76#ibcon#end of sib2, iclass 29, count 0 2006.183.08:28:32.76#ibcon#*mode == 0, iclass 29, count 0 2006.183.08:28:32.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.183.08:28:32.76#ibcon#[27=BW32\r\n] 2006.183.08:28:32.76#ibcon#*before write, iclass 29, count 0 2006.183.08:28:32.76#ibcon#enter sib2, iclass 29, count 0 2006.183.08:28:32.76#ibcon#flushed, iclass 29, count 0 2006.183.08:28:32.76#ibcon#about to write, iclass 29, count 0 2006.183.08:28:32.76#ibcon#wrote, iclass 29, count 0 2006.183.08:28:32.76#ibcon#about to read 3, iclass 29, count 0 2006.183.08:28:32.79#ibcon#read 3, iclass 29, count 0 2006.183.08:28:32.79#ibcon#about to read 4, iclass 29, count 0 2006.183.08:28:32.79#ibcon#read 4, iclass 29, count 0 2006.183.08:28:32.79#ibcon#about to read 5, iclass 29, count 0 2006.183.08:28:32.79#ibcon#read 5, iclass 29, count 0 2006.183.08:28:32.79#ibcon#about to read 6, iclass 29, count 0 2006.183.08:28:32.79#ibcon#read 6, iclass 29, count 0 2006.183.08:28:32.79#ibcon#end of sib2, iclass 29, count 0 2006.183.08:28:32.79#ibcon#*after write, iclass 29, count 0 2006.183.08:28:32.79#ibcon#*before return 0, iclass 29, count 0 2006.183.08:28:32.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:28:32.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.183.08:28:32.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.183.08:28:32.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.183.08:28:32.79$4f8m12a/ifd4f 2006.183.08:28:32.79$ifd4f/lo= 2006.183.08:28:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.183.08:28:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.183.08:28:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.183.08:28:32.79$ifd4f/patch= 2006.183.08:28:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.183.08:28:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.183.08:28:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.183.08:28:32.79$4f8m12a/"form=m,16.000,1:2 2006.183.08:28:32.79$4f8m12a/"tpicd 2006.183.08:28:32.79$4f8m12a/echo=off 2006.183.08:28:32.79$4f8m12a/xlog=off 2006.183.08:28:32.79:!2006.183.08:29:00 2006.183.08:28:41.14#trakl#Source acquired 2006.183.08:28:42.14#flagr#flagr/antenna,acquired 2006.183.08:29:00.00:preob 2006.183.08:29:01.14/onsource/TRACKING 2006.183.08:29:01.14:!2006.183.08:29:10 2006.183.08:29:10.00:data_valid=on 2006.183.08:29:10.00:midob 2006.183.08:29:10.14/onsource/TRACKING 2006.183.08:29:10.14/wx/28.23,996.8,87 2006.183.08:29:10.21/cable/+6.4490E-03 2006.183.08:29:11.30/va/01,08,usb,yes,29,31 2006.183.08:29:11.30/va/02,07,usb,yes,29,31 2006.183.08:29:11.30/va/03,06,usb,yes,31,31 2006.183.08:29:11.30/va/04,07,usb,yes,30,32 2006.183.08:29:11.30/va/05,07,usb,yes,32,34 2006.183.08:29:11.30/va/06,06,usb,yes,31,31 2006.183.08:29:11.30/va/07,06,usb,yes,31,31 2006.183.08:29:11.30/va/08,07,usb,yes,30,29 2006.183.08:29:11.53/valo/01,532.99,yes,locked 2006.183.08:29:11.53/valo/02,572.99,yes,locked 2006.183.08:29:11.53/valo/03,672.99,yes,locked 2006.183.08:29:11.53/valo/04,832.99,yes,locked 2006.183.08:29:11.53/valo/05,652.99,yes,locked 2006.183.08:29:11.53/valo/06,772.99,yes,locked 2006.183.08:29:11.53/valo/07,832.99,yes,locked 2006.183.08:29:11.53/valo/08,852.99,yes,locked 2006.183.08:29:12.62/vb/01,04,usb,yes,29,28 2006.183.08:29:12.62/vb/02,04,usb,yes,31,32 2006.183.08:29:12.62/vb/03,04,usb,yes,27,31 2006.183.08:29:12.62/vb/04,04,usb,yes,28,28 2006.183.08:29:12.62/vb/05,04,usb,yes,27,31 2006.183.08:29:12.62/vb/06,04,usb,yes,28,31 2006.183.08:29:12.62/vb/07,04,usb,yes,30,30 2006.183.08:29:12.62/vb/08,04,usb,yes,27,31 2006.183.08:29:12.85/vblo/01,632.99,yes,locked 2006.183.08:29:12.85/vblo/02,640.99,yes,locked 2006.183.08:29:12.85/vblo/03,656.99,yes,locked 2006.183.08:29:12.85/vblo/04,712.99,yes,locked 2006.183.08:29:12.85/vblo/05,744.99,yes,locked 2006.183.08:29:12.85/vblo/06,752.99,yes,locked 2006.183.08:29:12.85/vblo/07,734.99,yes,locked 2006.183.08:29:12.85/vblo/08,744.99,yes,locked 2006.183.08:29:13.00/vabw/8 2006.183.08:29:13.15/vbbw/8 2006.183.08:29:13.24/xfe/off,on,14.7 2006.183.08:29:13.62/ifatt/23,28,28,28 2006.183.08:29:14.07/fmout-gps/S +3.34E-07 2006.183.08:29:14.11:!2006.183.08:30:10 2006.183.08:30:10.01:data_valid=off 2006.183.08:30:10.01:postob 2006.183.08:30:10.13/cable/+6.4493E-03 2006.183.08:30:10.13/wx/28.22,996.8,88 2006.183.08:30:11.08/fmout-gps/S +3.34E-07 2006.183.08:30:11.08:checkk5last 2006.183.08:30:11.09&checkk5last/chk_obsdata=1 2006.183.08:30:11.09&checkk5last/chk_obsdata=2 2006.183.08:30:11.09&checkk5last/chk_obsdata=3 2006.183.08:30:11.10&checkk5last/chk_obsdata=4 2006.183.08:30:11.10&checkk5last/k5log=1 2006.183.08:30:11.10&checkk5last/k5log=2 2006.183.08:30:11.10&checkk5last/k5log=3 2006.183.08:30:11.10&checkk5last/k5log=4 2006.183.08:30:11.10&checkk5last/obsinfo 2006.183.08:30:11.49/chk_obsdata//k5ts1/T1830829??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:30:11.86/chk_obsdata//k5ts2/T1830829??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:30:12.23/chk_obsdata//k5ts3/T1830829??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:30:12.59/chk_obsdata//k5ts4/T1830829??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.183.08:30:13.29/k5log//k5ts1_log_newline 2006.183.08:30:13.98/k5log//k5ts2_log_newline 2006.183.08:30:14.66/k5log//k5ts3_log_newline 2006.183.08:30:15.35/k5log//k5ts4_log_newline 2006.183.08:30:15.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.183.08:30:15.37:sched_end 2006.183.08:30:15.37&sched_end/stopcheck 2006.183.08:30:15.37&stopcheck/sy=killall check_fsrun.pl 2006.183.08:30:15.37&stopcheck/" sy=killall chmem.sh 2006.183.08:30:15.46:source=idle 2006.183.08:30:16.14#flagr#flagr/antenna,new-source 2006.183.08:30:16.14:stow 2006.183.08:30:16.15&stow/source=idle 2006.183.08:30:16.15&stow/"this is stow command. 2006.183.08:30:16.15&stow/antenna=m3 2006.183.08:30:20.01:!+10m 2006.183.08:40:20.02:standby 2006.183.08:40:20.02&standby/"this is standby command. 2006.183.08:40:20.02&standby/antenna=m0 2006.183.08:40:21.01:sy=cp /usr2/log/k06183ts.log /usr2/log_backup/ 2006.183.08:40:21.09:*end of schedule